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/*
This file is part of Fusion-Core-ISA.
Fusion-Core-ISA is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
Fusion-Core-ISA is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with Fusion-Core-ISA. If not, see <http://www.gnu.org/licenses/>.
*/
module shift_left_32(
input[31:0] a, //value to be shifted
output[31:0] out //output
);
//shifts everything left by 1
assign out[0] = a[31];
assign out[1] = a[0];
assign out[2] = a[1];
assign out[3] = a[2];
assign out[4] = a[3];
assign out[5] = a[4];
assign out[6] = a[5];
assign out[7] = a[6];
assign out[8] = a[7];
assign out[9] = a[8];
assign out[10] = a[9];
assign out[11] = a[10];
assign out[12] = a[11];
assign out[13] = a[12];
assign out[14] = a[13];
assign out[15] = a[14];
assign out[16] = a[15];
assign out[17] = a[16];
assign out[18] = a[17];
assign out[19] = a[18];
assign out[20] = a[19];
assign out[21] = a[20];
assign out[22] = a[21];
assign out[23] = a[22];
assign out[24] = a[23];
assign out[25] = a[24];
assign out[26] = a[25];
assign out[27] = a[26];
assign out[28] = a[27];
assign out[29] = a[28];
assign out[30] = a[29];
assign out[31] = a[30];
endmodule
|
// megafunction wizard: %Virtual JTAG%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: sld_virtual_jtag
// ============================================================
// File Name: vjtag.v
// Megafunction Name(s):
// sld_virtual_jtag
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module vjtag (
ir_out,
tdo,
ir_in,
tck,
tdi,
virtual_state_cdr,
virtual_state_cir,
virtual_state_e1dr,
virtual_state_e2dr,
virtual_state_pdr,
virtual_state_sdr,
virtual_state_udr,
virtual_state_uir);
input [1:0] ir_out;
input tdo;
output [1:0] ir_in;
output tck;
output tdi;
output virtual_state_cdr;
output virtual_state_cir;
output virtual_state_e1dr;
output virtual_state_e2dr;
output virtual_state_pdr;
output virtual_state_sdr;
output virtual_state_udr;
output virtual_state_uir;
wire sub_wire0;
wire sub_wire1;
wire [1:0] sub_wire2;
wire sub_wire3;
wire sub_wire4;
wire sub_wire5;
wire sub_wire6;
wire sub_wire7;
wire sub_wire8;
wire sub_wire9;
wire sub_wire10;
wire virtual_state_cir = sub_wire0;
wire virtual_state_pdr = sub_wire1;
wire [1:0] ir_in = sub_wire2[1:0];
wire tdi = sub_wire3;
wire virtual_state_udr = sub_wire4;
wire tck = sub_wire5;
wire virtual_state_e1dr = sub_wire6;
wire virtual_state_uir = sub_wire7;
wire virtual_state_cdr = sub_wire8;
wire virtual_state_e2dr = sub_wire9;
wire virtual_state_sdr = sub_wire10;
sld_virtual_jtag sld_virtual_jtag_component (
.ir_out (ir_out),
.tdo (tdo),
.virtual_state_cir (sub_wire0),
.virtual_state_pdr (sub_wire1),
.ir_in (sub_wire2),
.tdi (sub_wire3),
.virtual_state_udr (sub_wire4),
.tck (sub_wire5),
.virtual_state_e1dr (sub_wire6),
.virtual_state_uir (sub_wire7),
.virtual_state_cdr (sub_wire8),
.virtual_state_e2dr (sub_wire9),
.virtual_state_sdr (sub_wire10)
// synopsys translate_off
,
.jtag_state_cdr (),
.jtag_state_cir (),
.jtag_state_e1dr (),
.jtag_state_e1ir (),
.jtag_state_e2dr (),
.jtag_state_e2ir (),
.jtag_state_pdr (),
.jtag_state_pir (),
.jtag_state_rti (),
.jtag_state_sdr (),
.jtag_state_sdrs (),
.jtag_state_sir (),
.jtag_state_sirs (),
.jtag_state_tlr (),
.jtag_state_udr (),
.jtag_state_uir (),
.tms ()
// synopsys translate_on
);
defparam
sld_virtual_jtag_component.sld_auto_instance_index = "NO",
sld_virtual_jtag_component.sld_instance_index = 0,
sld_virtual_jtag_component.sld_ir_width = 2,
sld_virtual_jtag_component.sld_sim_action = "((0,2,0,4),(0,1,1,2),(0,2,12,8),(0,2,34,8),(0,2,56,8),(0,1,0,2),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8))",
sld_virtual_jtag_component.sld_sim_n_scan = 41,
sld_virtual_jtag_component.sld_sim_total_length = 312;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: show_jtag_state STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: SLD_AUTO_INSTANCE_INDEX STRING "NO"
// Retrieval info: CONSTANT: SLD_INSTANCE_INDEX NUMERIC "0"
// Retrieval info: CONSTANT: SLD_IR_WIDTH NUMERIC "2"
// Retrieval info: CONSTANT: SLD_SIM_ACTION STRING "((0,2,0,4),(0,1,1,2),(0,2,12,8),(0,2,34,8),(0,2,56,8),(0,1,0,2),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8))"
// Retrieval info: CONSTANT: SLD_SIM_N_SCAN NUMERIC "41"
// Retrieval info: CONSTANT: SLD_SIM_TOTAL_LENGTH NUMERIC "312"
// Retrieval info: USED_PORT: ir_in 0 0 2 0 OUTPUT NODEFVAL "ir_in[1..0]"
// Retrieval info: USED_PORT: ir_out 0 0 2 0 INPUT NODEFVAL "ir_out[1..0]"
// Retrieval info: USED_PORT: tck 0 0 0 0 OUTPUT NODEFVAL "tck"
// Retrieval info: USED_PORT: tdi 0 0 0 0 OUTPUT NODEFVAL "tdi"
// Retrieval info: USED_PORT: tdo 0 0 0 0 INPUT NODEFVAL "tdo"
// Retrieval info: USED_PORT: virtual_state_cdr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_cdr"
// Retrieval info: USED_PORT: virtual_state_cir 0 0 0 0 OUTPUT NODEFVAL "virtual_state_cir"
// Retrieval info: USED_PORT: virtual_state_e1dr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_e1dr"
// Retrieval info: USED_PORT: virtual_state_e2dr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_e2dr"
// Retrieval info: USED_PORT: virtual_state_pdr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_pdr"
// Retrieval info: USED_PORT: virtual_state_sdr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_sdr"
// Retrieval info: USED_PORT: virtual_state_udr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_udr"
// Retrieval info: USED_PORT: virtual_state_uir 0 0 0 0 OUTPUT NODEFVAL "virtual_state_uir"
// Retrieval info: CONNECT: @ir_out 0 0 2 0 ir_out 0 0 2 0
// Retrieval info: CONNECT: @tdo 0 0 0 0 tdo 0 0 0 0
// Retrieval info: CONNECT: ir_in 0 0 2 0 @ir_in 0 0 2 0
// Retrieval info: CONNECT: tck 0 0 0 0 @tck 0 0 0 0
// Retrieval info: CONNECT: tdi 0 0 0 0 @tdi 0 0 0 0
// Retrieval info: CONNECT: virtual_state_cdr 0 0 0 0 @virtual_state_cdr 0 0 0 0
// Retrieval info: CONNECT: virtual_state_cir 0 0 0 0 @virtual_state_cir 0 0 0 0
// Retrieval info: CONNECT: virtual_state_e1dr 0 0 0 0 @virtual_state_e1dr 0 0 0 0
// Retrieval info: CONNECT: virtual_state_e2dr 0 0 0 0 @virtual_state_e2dr 0 0 0 0
// Retrieval info: CONNECT: virtual_state_pdr 0 0 0 0 @virtual_state_pdr 0 0 0 0
// Retrieval info: CONNECT: virtual_state_sdr 0 0 0 0 @virtual_state_sdr 0 0 0 0
// Retrieval info: CONNECT: virtual_state_udr 0 0 0 0 @virtual_state_udr 0 0 0 0
// Retrieval info: CONNECT: virtual_state_uir 0 0 0 0 @virtual_state_uir 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL vjtag.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL vjtag.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL vjtag.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL vjtag.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL vjtag_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL vjtag_bb.v TRUE
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module up_gt (
// gt interface
gt_pll_rst,
gt_rx_rst,
gt_tx_rst,
up_lpm_dfe_n,
up_cpll_pd,
up_rx_sys_clk_sel,
up_rx_out_clk_sel,
up_tx_sys_clk_sel,
up_tx_out_clk_sel,
// receive interface
rx_clk,
rx_rst,
rx_jesd_rst,
rx_ext_sysref,
rx_sysref,
rx_ip_sync,
rx_sync,
rx_rst_done,
rx_pll_locked,
rx_error,
rx_rst_done_up,
// transmit interface
tx_clk,
tx_rst,
tx_jesd_rst,
tx_ext_sysref,
tx_sysref,
tx_sync,
tx_ip_sync,
tx_rst_done,
tx_pll_locked,
tx_error,
tx_rst_done_up,
// drp interface
up_drp_sel,
up_drp_wr,
up_drp_addr,
up_drp_wdata,
up_drp_rdata,
up_drp_ready,
up_drp_lanesel,
up_drp_rxrate,
// es interface
up_es_drp_sel,
up_es_drp_wr,
up_es_drp_addr,
up_es_drp_wdata,
up_es_drp_rdata,
up_es_drp_ready,
up_es_start,
up_es_stop,
up_es_init,
up_es_prescale,
up_es_voffset_range,
up_es_voffset_step,
up_es_voffset_max,
up_es_voffset_min,
up_es_hoffset_max,
up_es_hoffset_min,
up_es_hoffset_step,
up_es_start_addr,
up_es_sdata0,
up_es_sdata1,
up_es_sdata2,
up_es_sdata3,
up_es_sdata4,
up_es_qdata0,
up_es_qdata1,
up_es_qdata2,
up_es_qdata3,
up_es_qdata4,
up_es_dmaerr,
up_es_status,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
localparam PCORE_VERSION = 32'h00060162;
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
// gt interface
output gt_pll_rst;
output gt_rx_rst;
output gt_tx_rst;
output up_lpm_dfe_n;
output up_cpll_pd;
output [ 1:0] up_rx_sys_clk_sel;
output [ 2:0] up_rx_out_clk_sel;
output [ 1:0] up_tx_sys_clk_sel;
output [ 2:0] up_tx_out_clk_sel;
// receive interface
input rx_clk;
output rx_rst;
output rx_jesd_rst;
input rx_ext_sysref;
output rx_sysref;
input rx_ip_sync;
output rx_sync;
input [ 7:0] rx_rst_done;
input [ 7:0] rx_pll_locked;
input rx_error;
output rx_rst_done_up;
// transmit interface
input tx_clk;
output tx_rst;
output tx_jesd_rst;
input tx_ext_sysref;
output tx_sysref;
input tx_sync;
output tx_ip_sync;
input [ 7:0] tx_rst_done;
input [ 7:0] tx_pll_locked;
input tx_error;
output tx_rst_done_up;
// drp interface
output up_drp_sel;
output up_drp_wr;
output [11:0] up_drp_addr;
output [15:0] up_drp_wdata;
input [15:0] up_drp_rdata;
input up_drp_ready;
output [ 7:0] up_drp_lanesel;
input [ 7:0] up_drp_rxrate;
// es interface
input up_es_drp_sel;
input up_es_drp_wr;
input [11:0] up_es_drp_addr;
input [15:0] up_es_drp_wdata;
output [15:0] up_es_drp_rdata;
output up_es_drp_ready;
output up_es_start;
output up_es_stop;
output up_es_init;
output [ 4:0] up_es_prescale;
output [ 1:0] up_es_voffset_range;
output [ 7:0] up_es_voffset_step;
output [ 7:0] up_es_voffset_max;
output [ 7:0] up_es_voffset_min;
output [11:0] up_es_hoffset_max;
output [11:0] up_es_hoffset_min;
output [11:0] up_es_hoffset_step;
output [31:0] up_es_start_addr;
output [15:0] up_es_sdata0;
output [15:0] up_es_sdata1;
output [15:0] up_es_sdata2;
output [15:0] up_es_sdata3;
output [15:0] up_es_sdata4;
output [15:0] up_es_qdata0;
output [15:0] up_es_qdata1;
output [15:0] up_es_qdata2;
output [15:0] up_es_qdata3;
output [15:0] up_es_qdata4;
input up_es_dmaerr;
input up_es_status;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg up_gt_pll_preset = 'd1;
reg up_gt_rx_preset = 'd1;
reg up_gt_tx_preset = 'd1;
reg up_rx_preset = 'd1;
reg up_tx_preset = 'd1;
reg up_wack = 'd0;
reg [31:0] up_scratch = 'd0;
reg up_lpm_dfe_n = 'd0;
reg up_cpll_pd = 'd0;
reg up_drp_resetn = 'd0;
reg up_gt_pll_resetn = 'd0;
reg up_gt_rx_resetn = 'd0;
reg up_rx_resetn = 'd0;
reg [ 1:0] up_rx_sys_clk_sel = 'd0;
reg [ 2:0] up_rx_out_clk_sel = 'd0;
reg up_rx_sysref_sel = 'd0;
reg up_rx_sysref = 'd0;
reg up_rx_sync = 'd0;
reg up_gt_tx_resetn = 'd0;
reg up_tx_resetn = 'd0;
reg [ 1:0] up_tx_sys_clk_sel = 'd0;
reg [ 2:0] up_tx_out_clk_sel = 'd0;
reg up_tx_sysref_sel = 'd0;
reg up_tx_sysref = 'd0;
reg up_tx_sync = 'd0;
reg [ 7:0] up_drp_lanesel = 'd0;
reg up_drp_sel_int = 'd0;
reg up_drp_wr_int = 'd0;
reg up_drp_status = 'd0;
reg up_drp_rwn = 'd0;
reg [11:0] up_drp_addr_int = 'd0;
reg [15:0] up_drp_wdata_int = 'd0;
reg [15:0] up_drp_rdata_hold = 'd0;
reg up_es_init = 'd0;
reg up_es_stop = 'd0;
reg up_es_stop_hold = 'd0;
reg up_es_start = 'd0;
reg up_es_start_hold = 'd0;
reg [ 4:0] up_es_prescale = 'd0;
reg [ 1:0] up_es_voffset_range = 'd0;
reg [ 7:0] up_es_voffset_step = 'd0;
reg [ 7:0] up_es_voffset_max = 'd0;
reg [ 7:0] up_es_voffset_min = 'd0;
reg [11:0] up_es_hoffset_max = 'd0;
reg [11:0] up_es_hoffset_min = 'd0;
reg [11:0] up_es_hoffset_step = 'd0;
reg [31:0] up_es_start_addr = 'd0;
reg [15:0] up_es_sdata1 = 'd0;
reg [15:0] up_es_sdata0 = 'd0;
reg [15:0] up_es_sdata3 = 'd0;
reg [15:0] up_es_sdata2 = 'd0;
reg [15:0] up_es_sdata4 = 'd0;
reg [15:0] up_es_qdata1 = 'd0;
reg [15:0] up_es_qdata0 = 'd0;
reg [15:0] up_es_qdata3 = 'd0;
reg [15:0] up_es_qdata2 = 'd0;
reg [15:0] up_es_qdata4 = 'd0;
reg up_es_dmaerr_hold = 'd0;
reg up_rack = 'd0;
reg [31:0] up_rdata = 'd0;
reg [ 7:0] up_rx_rst_done_m1 = 'd0;
reg [ 7:0] up_rx_pll_locked_m1 = 'd0;
reg [ 7:0] up_tx_rst_done_m1 = 'd0;
reg [ 7:0] up_tx_pll_locked_m1 = 'd0;
reg [ 7:0] up_rx_rst_done = 'd0;
reg [ 7:0] up_rx_pll_locked = 'd0;
reg [ 7:0] up_tx_rst_done = 'd0;
reg [ 7:0] up_tx_pll_locked = 'd0;
reg rx_sysref_m1 = 'd0;
reg rx_sysref_m2 = 'd0;
reg rx_sysref_m3 = 'd0;
reg rx_sysref = 'd0;
reg rx_sync_m1 = 'd0;
reg rx_sync_m2 = 'd0;
reg rx_sync = 'd0;
reg tx_sysref_m1 = 'd0;
reg tx_sysref_m2 = 'd0;
reg tx_sysref_m3 = 'd0;
reg tx_sysref = 'd0;
reg tx_ip_sync_m1 = 'd0;
reg tx_ip_sync_m2 = 'd0;
reg tx_ip_sync = 'd0;
reg up_rx_status_m1 = 'd0;
reg up_rx_status = 'd0;
reg up_tx_status_m1 = 'd0;
reg up_tx_status = 'd0;
reg up_drp_sel = 'd0;
reg up_drp_wr = 'd0;
reg [11:0] up_drp_addr = 'd0;
reg [15:0] up_drp_wdata = 'd0;
reg [15:0] up_es_drp_rdata = 'd0;
reg up_es_drp_ready = 'd0;
reg [15:0] up_drp_rdata_int = 'd0;
reg up_drp_ready_int = 'd0;
// internal signals
wire up_wreq_s;
wire up_rreq_s;
wire up_rx_rst_done_s;
wire up_rx_pll_locked_s;
wire up_tx_rst_done_s;
wire up_tx_pll_locked_s;
wire rx_sysref_s;
wire tx_sysref_s;
// decode block select
assign up_wreq_s = (up_waddr[13:8] == 6'h00) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:8] == 6'h00) ? up_rreq : 1'b0;
// status inputs
assign up_rx_rst_done_s = & up_rx_rst_done;
assign up_rx_pll_locked_s = & up_rx_pll_locked;
assign up_tx_rst_done_s = & up_tx_rst_done;
assign up_tx_pll_locked_s = & up_tx_pll_locked;
// resets
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_gt_pll_preset <= 1'b1;
up_gt_rx_preset <= 1'b1;
up_gt_tx_preset <= 1'b1;
up_rx_preset <= 1'b1;
up_tx_preset <= 1'b1;
end else begin
up_gt_pll_preset <= ~up_gt_pll_resetn;
up_gt_rx_preset <= ~(up_gt_pll_resetn & up_gt_rx_resetn & up_rx_pll_locked_s);
up_gt_tx_preset <= ~(up_gt_pll_resetn & up_gt_tx_resetn & up_tx_pll_locked_s);
up_rx_preset <= ~(up_gt_pll_resetn & up_gt_rx_resetn & up_rx_resetn & up_rx_pll_locked_s & up_rx_rst_done_s);
up_tx_preset <= ~(up_gt_pll_resetn & up_gt_tx_resetn & up_tx_resetn & up_tx_pll_locked_s & up_tx_rst_done_s);
end
end
// up clock domain reset done
assign rx_rst_done_up = up_rx_rst_done_s;
assign tx_rst_done_up = up_tx_rst_done_s;
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 'd0;
up_scratch <= 'd0;
up_lpm_dfe_n <= 'd0;
up_cpll_pd <= 'd1;
up_drp_resetn <= 'd0;
up_gt_pll_resetn <= 'd0;
up_gt_rx_resetn <= 'd0;
up_rx_resetn <= 'd0;
up_rx_sys_clk_sel <= 2'b11;
up_rx_out_clk_sel <= 3'b010;
up_rx_sysref_sel <= 'd0;
up_rx_sysref <= 'd0;
up_rx_sync <= 'd0;
up_gt_tx_resetn <= 'd0;
up_tx_resetn <= 'd0;
up_tx_sys_clk_sel <= 2'b11;
up_tx_out_clk_sel <= 3'b010;
up_tx_sysref_sel <= 'd0;
up_tx_sysref <= 'd0;
up_tx_sync <= 'd0;
up_drp_lanesel <= 'd0;
up_drp_sel_int <= 'd0;
up_drp_wr_int <= 'd0;
up_drp_status <= 'd0;
up_drp_rwn <= 'd0;
up_drp_addr_int <= 'd0;
up_drp_wdata_int <= 'd0;
up_drp_rdata_hold <= 'd0;
up_es_init <= 'd0;
up_es_stop <= 'd0;
up_es_stop_hold <= 'd0;
up_es_start <= 'd0;
up_es_start_hold <= 'd0;
up_es_prescale <= 'd0;
up_es_voffset_range <= 'd0;
up_es_voffset_step <= 'd0;
up_es_voffset_max <= 'd0;
up_es_voffset_min <= 'd0;
up_es_hoffset_max <= 'd0;
up_es_hoffset_min <= 'd0;
up_es_hoffset_step <= 'd0;
up_es_start_addr <= 'd0;
up_es_sdata1 <= 'd0;
up_es_sdata0 <= 'd0;
up_es_sdata3 <= 'd0;
up_es_sdata2 <= 'd0;
up_es_sdata4 <= 'd0;
up_es_qdata1 <= 'd0;
up_es_qdata0 <= 'd0;
up_es_qdata3 <= 'd0;
up_es_qdata2 <= 'd0;
up_es_qdata4 <= 'd0;
up_es_dmaerr_hold <= 'd0;
end else begin
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
up_scratch <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h04)) begin
up_lpm_dfe_n <= up_wdata[1];
up_cpll_pd <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h05)) begin
up_drp_resetn <= up_wdata[1];
up_gt_pll_resetn <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h08)) begin
up_gt_rx_resetn <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h09)) begin
up_rx_resetn <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h0a)) begin
up_rx_sys_clk_sel <= up_wdata[5:4];
up_rx_out_clk_sel <= up_wdata[2:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h0b)) begin
up_rx_sysref_sel <= up_wdata[1];
up_rx_sysref <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h0c)) begin
up_rx_sync <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h18)) begin
up_gt_tx_resetn <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h19)) begin
up_tx_resetn <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1a)) begin
up_tx_sys_clk_sel <= up_wdata[5:4];
up_tx_out_clk_sel <= up_wdata[2:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1b)) begin
up_tx_sysref_sel <= up_wdata[1];
up_tx_sysref <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
up_tx_sync <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h23)) begin
up_drp_lanesel <= up_wdata[7:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h24)) begin
up_drp_sel_int <= 1'b1;
up_drp_wr_int <= ~up_wdata[28];
end else begin
up_drp_sel_int <= 1'b0;
up_drp_wr_int <= 1'b0;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h24)) begin
up_drp_status <= 1'b1;
end else if (up_drp_ready == 1'b1) begin
up_drp_status <= 1'b0;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h24)) begin
up_drp_rwn <= up_wdata[28];
up_drp_addr_int <= up_wdata[27:16];
up_drp_wdata_int <= up_wdata[15:0];
end
if (up_drp_ready_int == 1'b1) begin
up_drp_rdata_hold <= up_drp_rdata_int;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h28)) begin
up_es_init <= up_wdata[2];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h28)) begin
up_es_stop <= up_wdata[1];
up_es_stop_hold <= up_wdata[1];
end else begin
up_es_stop <= 1'd0;
up_es_stop_hold <= up_es_stop_hold;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h28)) begin
up_es_start <= up_wdata[0];
up_es_start_hold <= up_wdata[0];
end else begin
up_es_start <= 1'd0;
up_es_start_hold <= up_es_start_hold;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h29)) begin
up_es_prescale <= up_wdata[4:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2a)) begin
up_es_voffset_range <= up_wdata[25:24];
up_es_voffset_step <= up_wdata[23:16];
up_es_voffset_max <= up_wdata[15:8];
up_es_voffset_min <= up_wdata[7:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2b)) begin
up_es_hoffset_max <= up_wdata[27:16];
up_es_hoffset_min <= up_wdata[11:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2c)) begin
up_es_hoffset_step <= up_wdata[11:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2d)) begin
up_es_start_addr <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2e)) begin
up_es_sdata1 <= up_wdata[31:16];
up_es_sdata0 <= up_wdata[15:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2f)) begin
up_es_sdata3 <= up_wdata[31:16];
up_es_sdata2 <= up_wdata[15:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h30)) begin
up_es_sdata4 <= up_wdata[15:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h31)) begin
up_es_qdata1 <= up_wdata[31:16];
up_es_qdata0 <= up_wdata[15:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h32)) begin
up_es_qdata3 <= up_wdata[31:16];
up_es_qdata2 <= up_wdata[15:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h33)) begin
up_es_qdata4 <= up_wdata[15:0];
end
if (up_es_dmaerr == 1'b1) begin
up_es_dmaerr_hold <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h38)) begin
up_es_dmaerr_hold <= up_es_dmaerr_hold & ~up_wdata[1];
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr[7:0])
8'h00: up_rdata <= PCORE_VERSION;
8'h01: up_rdata <= PCORE_ID;
8'h02: up_rdata <= up_scratch;
8'h04: up_rdata <= {30'd0, up_lpm_dfe_n, up_cpll_pd};
8'h05: up_rdata <= {30'd0, up_drp_resetn, up_gt_pll_resetn};
8'h08: up_rdata <= {31'd0, up_gt_rx_resetn};
8'h09: up_rdata <= {31'd0, up_rx_resetn};
8'h0a: up_rdata <= {24'd0, 2'd0, up_rx_sys_clk_sel, 1'd0, up_rx_out_clk_sel};
8'h0b: up_rdata <= {30'd0, up_rx_sysref_sel, up_rx_sysref};
8'h0c: up_rdata <= {31'd0, up_rx_sync};
8'h0d: up_rdata <= {15'd0, up_rx_status, up_rx_rst_done, up_rx_pll_locked};
8'h18: up_rdata <= {31'd0, up_gt_tx_resetn};
8'h19: up_rdata <= {31'd0, up_tx_resetn};
8'h1a: up_rdata <= {24'd0, 2'd0, up_tx_sys_clk_sel, 1'd0, up_tx_out_clk_sel};
8'h1b: up_rdata <= {30'd0, up_tx_sysref_sel, up_tx_sysref};
8'h1c: up_rdata <= {31'd0, up_tx_sync};
8'h1d: up_rdata <= {15'd0, up_tx_status, up_tx_rst_done, up_tx_pll_locked};
8'h23: up_rdata <= {24'd0, up_drp_lanesel};
8'h24: up_rdata <= {3'd0, up_drp_rwn, up_drp_addr_int, up_drp_wdata_int};
8'h25: up_rdata <= {15'd0, up_drp_status, up_drp_rdata_int};
8'h28: up_rdata <= {29'd0, up_es_init, up_es_stop_hold, up_es_start_hold};
8'h29: up_rdata <= {27'd0, up_es_prescale};
8'h2a: up_rdata <= {6'd0, up_es_voffset_range, up_es_voffset_step, up_es_voffset_max, up_es_voffset_min};
8'h2b: up_rdata <= {4'd0, up_es_hoffset_max, 4'd0, up_es_hoffset_min};
8'h2c: up_rdata <= {20'd0, up_es_hoffset_step};
8'h2d: up_rdata <= up_es_start_addr;
8'h2e: up_rdata <= {up_es_sdata1, up_es_sdata0};
8'h2f: up_rdata <= {up_es_sdata3, up_es_sdata2};
8'h30: up_rdata <= up_es_sdata4;
8'h31: up_rdata <= {up_es_qdata1, up_es_qdata0};
8'h32: up_rdata <= {up_es_qdata3, up_es_qdata2};
8'h33: up_rdata <= up_es_qdata4;
8'h38: up_rdata <= {30'd0, up_es_dmaerr_hold, up_es_status};
8'h39: up_rdata <= {24'd0, up_drp_rxrate};
8'h3a: up_rdata <= PCORE_DEVICE_TYPE;
default: up_rdata <= 0;
endcase
end else begin
up_rdata <= 32'd0;
end
end
end
// resets
ad_rst i_gt_pll_rst_reg (.preset(up_gt_pll_preset), .clk(up_clk), .rst(gt_pll_rst));
ad_rst i_gt_rx_rst_reg (.preset(up_gt_rx_preset), .clk(up_clk), .rst(gt_rx_rst));
ad_rst i_gt_tx_rst_reg (.preset(up_gt_tx_preset), .clk(up_clk), .rst(gt_tx_rst));
ad_rst i_rx_rst_reg (.preset(up_rx_preset), .clk(rx_clk), .rst(rx_rst));
ad_rst i_j_rx_rst_reg (.preset(up_rx_preset), .clk(up_clk), .rst(rx_jesd_rst));
ad_rst i_tx_rst_reg (.preset(up_tx_preset), .clk(tx_clk), .rst(tx_rst));
ad_rst i_j_tx_rst_reg (.preset(up_tx_preset), .clk(up_clk), .rst(tx_jesd_rst));
// reset done & pll locked
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rx_rst_done_m1 <= 'd0;
up_rx_pll_locked_m1 <= 'd0;
up_tx_rst_done_m1 <= 'd0;
up_tx_pll_locked_m1 <= 'd0;
up_rx_rst_done <= 'd0;
up_rx_pll_locked <= 'd0;
up_tx_rst_done <= 'd0;
up_tx_pll_locked <= 'd0;
end else begin
up_rx_rst_done_m1 <= rx_rst_done;
up_rx_pll_locked_m1 <= rx_pll_locked;
up_tx_rst_done_m1 <= tx_rst_done;
up_tx_pll_locked_m1 <= tx_pll_locked;
up_rx_rst_done <= up_rx_rst_done_m1;
up_rx_pll_locked <= up_rx_pll_locked_m1;
up_tx_rst_done <= up_tx_rst_done_m1;
up_tx_pll_locked <= up_tx_pll_locked_m1;
end
end
// rx sysref & sync
assign rx_sysref_s = (up_rx_sysref_sel == 1'b1) ? rx_ext_sysref : up_rx_sysref;
always @(posedge rx_clk) begin
if (rx_rst == 1'b1) begin
rx_sysref_m1 <= 'd0;
rx_sysref_m2 <= 'd0;
rx_sysref_m3 <= 'd0;
rx_sysref <= 'd0;
rx_sync_m1 <= 'd0;
rx_sync_m2 <= 'd0;
rx_sync <= 'd0;
end else begin
rx_sysref_m1 <= rx_sysref_s;
rx_sysref_m2 <= rx_sysref_m1;
rx_sysref_m3 <= rx_sysref_m2;
rx_sysref <= rx_sysref_m2 & ~rx_sysref_m3;
rx_sync_m1 <= up_rx_sync & rx_ip_sync;
rx_sync_m2 <= rx_sync_m1;
rx_sync <= rx_sync_m2;
end
end
// tx sysref & sync
assign tx_sysref_s = (up_tx_sysref_sel == 1'b1) ? tx_ext_sysref : up_tx_sysref;
always @(posedge tx_clk) begin
if (tx_rst == 1'b1) begin
tx_sysref_m1 <= 'd0;
tx_sysref_m2 <= 'd0;
tx_sysref_m3 <= 'd0;
tx_sysref <= 'd0;
tx_ip_sync_m1 <= 'd0;
tx_ip_sync_m2 <= 'd0;
tx_ip_sync <= 'd0;
end else begin
tx_sysref_m1 <= tx_sysref_s;
tx_sysref_m2 <= tx_sysref_m1;
tx_sysref_m3 <= tx_sysref_m2;
tx_sysref <= tx_sysref_m2 & ~tx_sysref_m3;
tx_ip_sync_m1 <= up_tx_sync & tx_sync;
tx_ip_sync_m2 <= tx_ip_sync_m1;
tx_ip_sync <= tx_ip_sync_m2;
end
end
// status
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rx_status_m1 <= 'd0;
up_rx_status <= 'd0;
up_tx_status_m1 <= 'd0;
up_tx_status <= 'd0;
end else begin
up_rx_status_m1 <= rx_sync & ~rx_error;
up_rx_status <= up_rx_status_m1;
up_tx_status_m1 <= tx_ip_sync & ~tx_error;
up_tx_status <= up_tx_status_m1;
end
end
// drp mux
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_drp_sel <= 'd0;
up_drp_wr <= 'd0;
up_drp_addr <= 'd0;
up_drp_wdata <= 'd0;
up_es_drp_rdata <= 'd0;
up_es_drp_ready <= 'd0;
up_drp_rdata_int <= 'd0;
up_drp_ready_int <= 'd0;
end else begin
if (up_es_status == 1'b1) begin
up_drp_sel <= up_es_drp_sel;
up_drp_wr <= up_es_drp_wr;
up_drp_addr <= up_es_drp_addr;
up_drp_wdata <= up_es_drp_wdata;
up_es_drp_rdata <= up_drp_rdata;
up_es_drp_ready <= up_drp_ready;
up_drp_rdata_int <= 16'd0;
up_drp_ready_int <= 1'd0;
end else begin
up_drp_sel <= up_drp_sel_int;
up_drp_wr <= up_drp_wr_int;
up_drp_addr <= up_drp_addr_int;
up_drp_wdata <= up_drp_wdata_int;
up_es_drp_rdata <= 16'd0;
up_es_drp_ready <= 1'd0;
up_drp_rdata_int <= up_drp_rdata;
up_drp_ready_int <= up_drp_ready;
end
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLYGATE4SD1_SYMBOL_V
`define SKY130_FD_SC_HDLL__DLYGATE4SD1_SYMBOL_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__dlygate4sd1 (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLYGATE4SD1_SYMBOL_V
|
/***************************************************************************************************
** fpga_nes/hw/src/nes_top.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Top level module for an fpga-based Nintendo Entertainment System emulator.
***************************************************************************************************/
`timescale 1 ns/1 ps
module nes_top #(
parameter CLOCK_RATE = 100000000,
// Video Configuration
parameter FPS = 60,
parameter FRAME_WIDTH = 480,
parameter FRAME_HEIGHT = 272,
parameter X_OFFSET = 112,
parameter Y_OFFSET = 6,
parameter BG_COLOR = 8'h00
)(
input clk, // 100MHz system clock signal
input rst, // reset push button
input i_console_reset, // console reset
input [3:0] i_mute_control, // switches
// Video Interface
output o_video_hsync, // Video Active
output o_sof_stb, // Start of frame strobe
output [2:0] o_red, // vga red signal
output [2:0] o_green, // vga green signal
output [1:0] o_blue, // vga blue signal
// Joypad signals.
input [7:0] i_jp1_state, // State of joypad 1
input [7:0] i_jp2_state, // State of joypad 2
// Audio Interface
output o_audio, // pwm output audio channel
// Host Controller Interface
input i_hci_reset,
input [7:0] i_hci_opcode,
input i_hci_opcode_strobe,
output [15:0] o_hci_opcode_status,
output o_hci_opcode_ack,
input [15:0] i_hci_address,
input [31:0] i_hci_count,
input i_hci_data_strobe,
output o_hci_sm_ready,
input [7:0] i_hci_data,
output o_hci_data_strobe,
input i_hci_host_ready,
output [7:0] o_hci_data
);
//
// System Memory Buses
//
wire [ 7:0] cpumc_din;
wire [15:0] cpumc_a;
wire cpumc_r_nw;
wire [ 7:0] ppumc_din;
wire [13:0] ppumc_a;
wire ppumc_wr;
//
// RP2A03: Main processing chip including CPU, APU, joypad control, and sprite DMA control.
//
wire rp2a03_rdy;
wire [ 7:0] rp2a03_din;
wire rp2a03_nnmi;
wire [ 7:0] rp2a03_dout;
wire [15:0] rp2a03_a;
wire rp2a03_r_nw;
wire rp2a03_brk;
wire [ 3:0] rp2a03_dbgreg_sel;
wire [ 7:0] rp2a03_dbgreg_din;
wire rp2a03_dbgreg_wr;
wire [ 7:0] rp2a03_dbgreg_dout;
rp2a03 rp2a03_blk(
.clk_in (clk ),
.rst_in (rst ),
.rdy_in (rp2a03_rdy ),
.nres_in (~i_console_reset ),
.nnmi_in (rp2a03_nnmi ),
.r_nw_out (rp2a03_r_nw ),
.a_out (rp2a03_a ),
.d_in (rp2a03_din ),
.d_out (rp2a03_dout ),
.brk_out (rp2a03_brk ),
.i_jp1_state (i_jp1_state ),
.i_jp2_state (i_jp2_state ),
.mute_in (i_mute_control ),
.audio_out (o_audio ),
.dbgreg_sel_in (rp2a03_dbgreg_sel ),
.dbgreg_d_in (rp2a03_dbgreg_din ),
.dbgreg_wr_in (rp2a03_dbgreg_wr ),
.dbgreg_d_out (rp2a03_dbgreg_dout )
);
//
// CART: cartridge emulator
//
wire cart_prg_nce;
wire [ 7:0] cart_prg_dout;
wire [ 7:0] cart_chr_dout;
wire cart_ciram_nce;
wire cart_ciram_a10;
wire [39:0] cart_cfg;
wire cart_cfg_upd;
cart cart_blk(
.clk_in (clk ),
.cfg_in (cart_cfg ),
.cfg_upd_in (cart_cfg_upd ),
.prg_nce_in (cart_prg_nce ),
.prg_a_in (cpumc_a[14:0] ),
.prg_r_nw_in (cpumc_r_nw ),
.prg_d_in (cpumc_din ),
.prg_d_out (cart_prg_dout ),
.chr_a_in (ppumc_a ),
.chr_r_nw_in (~ppumc_wr ),
.chr_d_in (ppumc_din ),
.chr_d_out (cart_chr_dout ),
.ciram_nce_out (cart_ciram_nce ),
.ciram_a10_out (cart_ciram_a10 )
);
assign cart_prg_nce = ~cpumc_a[15];
//
// WRAM: internal work ram
//
wire wram_en;
wire [7:0] wram_dout;
wram wram_blk(
.clk_in (clk ),
.en_in (wram_en ),
.r_nw_in (cpumc_r_nw ),
.a_in (cpumc_a[10:0] ),
.d_in (cpumc_din ),
.d_out (wram_dout )
);
assign wram_en = (cpumc_a[15:13] == 0);
//
// VRAM: internal video ram
//
wire [10:0] vram_a;
wire [ 7:0] vram_dout;
vram vram_blk(
.clk_in (clk ),
.en_in (~cart_ciram_nce ),
.r_nw_in (~ppumc_wr ),
.a_in (vram_a ),
.d_in (ppumc_din ),
.d_out (vram_dout )
);
//
// PPU: picture processing unit block.
//
wire [ 2:0] ppu_ri_sel; // ppu register interface reg select
wire ppu_ri_ncs; // ppu register interface enable
wire ppu_ri_r_nw; // ppu register interface read/write select
wire [ 7:0] ppu_ri_din; // ppu register interface data input
wire [ 7:0] ppu_ri_dout; // ppu register interface data output
wire [13:0] ppu_vram_a; // ppu video ram address bus
wire ppu_vram_wr; // ppu video ram read/write select
wire [ 7:0] ppu_vram_din; // ppu video ram data bus (input)
wire [ 7:0] ppu_vram_dout; // ppu video ram data bus (output)
wire ppu_nvbl; // ppu /VBL signal.
// PPU snoops the CPU address bus for register reads/writes. Addresses 0x2000-0x2007
// are mapped to the PPU register space, with every 8 bytes mirrored through 0x3FFF.
assign ppu_ri_sel = cpumc_a[2:0];
assign ppu_ri_ncs = (cpumc_a[15:13] == 3'b001) ? 1'b0 : 1'b1;
assign ppu_ri_r_nw = cpumc_r_nw;
assign ppu_ri_din = cpumc_din;
ppu #(
.CLOCK_RATE (CLOCK_RATE ),
.FPS (FPS ),
//Should be at the center of the screen
.FRAME_WIDTH (FRAME_WIDTH ),
.FRAME_HEIGHT (FRAME_HEIGHT ),
.X_OFFSET (X_OFFSET ),
.Y_OFFSET (Y_OFFSET ),
.BG_COLOR (BG_COLOR )
)ppu_blk(
.clk_in (clk ),
.rst_in (rst ),
.ri_sel_in (ppu_ri_sel ),
.ri_ncs_in (ppu_ri_ncs ),
.ri_r_nw_in (ppu_ri_r_nw ),
.ri_d_in (ppu_ri_din ),
//Video
.o_video_hsync (o_video_hsync ),
.o_sof_stb (o_sof_stb ),
.o_r_out (o_red ),
.o_g_out (o_green ),
.o_b_out (o_blue ),
//VRAM
.ri_d_out (ppu_ri_dout ),
.nvbl_out (ppu_nvbl ),
.vram_a_out (ppu_vram_a ),
.vram_d_in (ppu_vram_din ),
.vram_d_out (ppu_vram_dout ),
.vram_wr_out (ppu_vram_wr )
);
assign vram_a = { cart_ciram_a10, ppumc_a[9:0] };
//
// HCI: host communication interface block. Interacts with NesDbg software through serial port.
//
wire hci_active;
wire [ 7:0] hci_cpu_din;
wire [ 7:0] hci_cpu_dout;
wire [15:0] hci_cpu_a;
wire hci_cpu_r_nw;
wire [ 7:0] hci_ppu_vram_din;
wire [ 7:0] hci_ppu_vram_dout;
wire [15:0] hci_ppu_vram_a;
wire hci_ppu_vram_wr;
nes_hci hci_blk(
.clk (clk ),
.rst (rst ),
//Host Interface
.i_reset_sm (i_hci_reset ),
.i_opcode (i_hci_opcode ),
.i_opcode_strobe (i_hci_opcode_strobe ),
.o_opcode_status (o_hci_opcode_status ),
.o_opcode_ack (o_hci_opcode_ack ),
.i_address (i_hci_address ),
.i_count (i_hci_count ),
.i_data_strobe (i_hci_data_strobe ),
.o_hci_ready (o_hci_sm_ready ),
.i_data (i_hci_data ),
.o_data_strobe (o_hci_data_strobe ),
.i_host_ready (i_hci_host_ready ),
.o_data (o_hci_data ),
//NES Interface
.i_cpu_break (rp2a03_brk ),
.o_cpu_r_nw (hci_cpu_r_nw ), //CPU Read/!Write Pin
.o_cpu_address (hci_cpu_a ),
.i_cpu_din (hci_cpu_din ),
.o_cpu_dout (hci_cpu_dout ),
.o_dbg_active (hci_active ),
.o_cpu_dbg_reg_wr (rp2a03_dbgreg_wr ),
.o_cpu_dbg_reg_sel (rp2a03_dbgreg_sel ),
.i_cpu_dbg_reg_din (rp2a03_dbgreg_dout ),
.o_cpu_dbg_reg_dout (rp2a03_dbgreg_din ),
.o_ppu_vram_wr (hci_ppu_vram_wr ),
.o_ppu_vram_address (hci_ppu_vram_a ),
.i_ppu_vram_din (hci_ppu_vram_din ),
.o_ppu_vram_dout (hci_ppu_vram_dout ),
.o_cart_cfg (cart_cfg ),
.o_cart_cfg_update (cart_cfg_upd )
);
// Mux cpumc signals from rp2a03 or hci blk, depending on debug break state (hci_active).
assign rp2a03_rdy = (hci_active) ? 1'b0 : 1'b1;
assign cpumc_a = (hci_active) ? hci_cpu_a : rp2a03_a;
assign cpumc_r_nw = (hci_active) ? hci_cpu_r_nw : rp2a03_r_nw;
assign cpumc_din = (hci_active) ? hci_cpu_dout : rp2a03_dout;
assign rp2a03_din = cart_prg_dout | wram_dout | ppu_ri_dout;
assign hci_cpu_din = cart_prg_dout | wram_dout | ppu_ri_dout;
// Mux ppumc signals from ppu or hci blk, depending on debug break state (hci_active).
assign ppumc_a = (hci_active) ? hci_ppu_vram_a[13:0] : ppu_vram_a;
assign ppumc_wr = (hci_active) ? hci_ppu_vram_wr : ppu_vram_wr;
assign ppumc_din = (hci_active) ? hci_ppu_vram_dout : ppu_vram_dout;
assign ppu_vram_din = cart_chr_dout | vram_dout;
assign hci_ppu_vram_din = cart_chr_dout | vram_dout;
// Issue NMI interupt on PPU vertical blank.
assign rp2a03_nnmi = ppu_nvbl;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR3B_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__NOR3B_BEHAVIORAL_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__nor3b (
Y ,
A ,
B ,
C_N
);
// Module ports
output Y ;
input A ;
input B ;
input C_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out ;
wire and0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y, C_N, nor0_out );
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR3B_BEHAVIORAL_V |
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 19:50:58 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_xbar_0_sim_netlist.v
// Design : ip_design_xbar_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_addr_arbiter_sasd
(m_valid_i,
SR,
aa_grant_rnw,
\m_ready_d_reg[0] ,
D,
m_ready_d0,
s_axi_bvalid,
m_axi_bready,
\gen_axilite.s_axi_bvalid_i_reg ,
s_axi_wready,
m_axi_wvalid,
\gen_axilite.s_axi_bvalid_i_reg_0 ,
m_axi_awvalid,
\gen_axilite.s_axi_bvalid_i_reg_1 ,
s_ready_i_reg,
m_valid_i_reg,
E,
\gen_axilite.s_axi_rvalid_i_reg ,
m_axi_arvalid,
m_ready_d0_0,
\m_ready_d_reg[0]_0 ,
\gen_no_arbiter.m_valid_i_reg_0 ,
s_axi_awready,
s_axi_arready,
s_axi_rvalid,
\m_atarget_enc_reg[2] ,
\m_axi_arprot[2] ,
\gen_axilite.s_axi_bvalid_i_reg_2 ,
aclk,
aresetn_d,
s_axi_awvalid,
s_axi_arvalid,
\m_ready_d_reg[0]_1 ,
\m_ready_d_reg[1] ,
m_ready_d,
\m_atarget_enc_reg[1] ,
Q,
s_axi_bready,
\m_atarget_enc_reg[2]_0 ,
s_axi_wvalid,
\m_atarget_enc_reg[2]_1 ,
\m_atarget_enc_reg[2]_2 ,
\m_atarget_enc_reg[1]_0 ,
\aresetn_d_reg[1] ,
aa_rready,
m_ready_d_1,
\m_atarget_enc_reg[0] ,
\m_atarget_enc_reg[1]_1 ,
s_axi_rready,
sr_rvalid,
\m_atarget_enc_reg[1]_2 ,
\gen_axilite.s_axi_arready_i_reg ,
\m_atarget_enc_reg[1]_3 ,
m_valid_i_reg_0,
m_axi_wready,
\m_atarget_enc_reg[2]_3 ,
s_axi_arprot,
s_axi_awprot,
s_axi_araddr,
s_axi_awaddr,
mi_wready,
mi_bvalid);
output m_valid_i;
output [0:0]SR;
output aa_grant_rnw;
output \m_ready_d_reg[0] ;
output [6:0]D;
output [0:0]m_ready_d0;
output [0:0]s_axi_bvalid;
output [5:0]m_axi_bready;
output \gen_axilite.s_axi_bvalid_i_reg ;
output [0:0]s_axi_wready;
output [5:0]m_axi_wvalid;
output \gen_axilite.s_axi_bvalid_i_reg_0 ;
output [5:0]m_axi_awvalid;
output \gen_axilite.s_axi_bvalid_i_reg_1 ;
output s_ready_i_reg;
output m_valid_i_reg;
output [0:0]E;
output \gen_axilite.s_axi_rvalid_i_reg ;
output [5:0]m_axi_arvalid;
output [0:0]m_ready_d0_0;
output \m_ready_d_reg[0]_0 ;
output \gen_no_arbiter.m_valid_i_reg_0 ;
output [0:0]s_axi_awready;
output [0:0]s_axi_arready;
output [0:0]s_axi_rvalid;
output [2:0]\m_atarget_enc_reg[2] ;
output [34:0]\m_axi_arprot[2] ;
output \gen_axilite.s_axi_bvalid_i_reg_2 ;
input aclk;
input aresetn_d;
input [0:0]s_axi_awvalid;
input [0:0]s_axi_arvalid;
input \m_ready_d_reg[0]_1 ;
input \m_ready_d_reg[1] ;
input [2:0]m_ready_d;
input \m_atarget_enc_reg[1] ;
input [6:0]Q;
input [0:0]s_axi_bready;
input \m_atarget_enc_reg[2]_0 ;
input [0:0]s_axi_wvalid;
input \m_atarget_enc_reg[2]_1 ;
input \m_atarget_enc_reg[2]_2 ;
input \m_atarget_enc_reg[1]_0 ;
input [1:0]\aresetn_d_reg[1] ;
input aa_rready;
input [1:0]m_ready_d_1;
input \m_atarget_enc_reg[0] ;
input \m_atarget_enc_reg[1]_1 ;
input [0:0]s_axi_rready;
input sr_rvalid;
input \m_atarget_enc_reg[1]_2 ;
input \gen_axilite.s_axi_arready_i_reg ;
input \m_atarget_enc_reg[1]_3 ;
input m_valid_i_reg_0;
input [1:0]m_axi_wready;
input [2:0]\m_atarget_enc_reg[2]_3 ;
input [2:0]s_axi_arprot;
input [2:0]s_axi_awprot;
input [31:0]s_axi_araddr;
input [31:0]s_axi_awaddr;
input [0:0]mi_wready;
input [0:0]mi_bvalid;
wire [6:0]D;
wire [0:0]E;
wire [6:0]Q;
wire [0:0]SR;
wire aa_grant_any;
wire aa_grant_rnw;
wire aa_rready;
wire aclk;
wire aresetn_d;
wire [1:0]\aresetn_d_reg[1] ;
wire \gen_axilite.s_axi_arready_i_reg ;
wire \gen_axilite.s_axi_bvalid_i_reg ;
wire \gen_axilite.s_axi_bvalid_i_reg_0 ;
wire \gen_axilite.s_axi_bvalid_i_reg_1 ;
wire \gen_axilite.s_axi_bvalid_i_reg_2 ;
wire \gen_axilite.s_axi_rvalid_i_reg ;
wire \gen_no_arbiter.grant_rnw_i_1_n_0 ;
wire \gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0 ;
wire \gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0 ;
wire \gen_no_arbiter.m_valid_i_i_1_n_0 ;
wire \gen_no_arbiter.m_valid_i_reg_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_1_n_0 ;
wire \m_atarget_enc_reg[0] ;
wire \m_atarget_enc_reg[1] ;
wire \m_atarget_enc_reg[1]_0 ;
wire \m_atarget_enc_reg[1]_1 ;
wire \m_atarget_enc_reg[1]_2 ;
wire \m_atarget_enc_reg[1]_3 ;
wire [2:0]\m_atarget_enc_reg[2] ;
wire \m_atarget_enc_reg[2]_0 ;
wire \m_atarget_enc_reg[2]_1 ;
wire \m_atarget_enc_reg[2]_2 ;
wire [2:0]\m_atarget_enc_reg[2]_3 ;
wire \m_atarget_hot[4]_i_2_n_0 ;
wire \m_atarget_hot[5]_i_2_n_0 ;
wire \m_atarget_hot[6]_i_10_n_0 ;
wire \m_atarget_hot[6]_i_11_n_0 ;
wire \m_atarget_hot[6]_i_12_n_0 ;
wire \m_atarget_hot[6]_i_2_n_0 ;
wire \m_atarget_hot[6]_i_3_n_0 ;
wire \m_atarget_hot[6]_i_4_n_0 ;
wire \m_atarget_hot[6]_i_5_n_0 ;
wire \m_atarget_hot[6]_i_6_n_0 ;
wire \m_atarget_hot[6]_i_7_n_0 ;
wire \m_atarget_hot[6]_i_8_n_0 ;
wire \m_atarget_hot[6]_i_9_n_0 ;
wire [34:0]\m_axi_arprot[2] ;
wire [5:0]m_axi_arvalid;
wire [5:0]m_axi_awvalid;
wire [5:0]m_axi_bready;
wire [1:0]m_axi_wready;
wire [5:0]m_axi_wvalid;
wire [2:0]m_ready_d;
wire [0:0]m_ready_d0;
wire [0:0]m_ready_d0_0;
wire \m_ready_d[0]_i_4_n_0 ;
wire [1:0]m_ready_d_1;
wire \m_ready_d_reg[0] ;
wire \m_ready_d_reg[0]_0 ;
wire \m_ready_d_reg[0]_1 ;
wire \m_ready_d_reg[1] ;
wire m_valid_i;
wire m_valid_i_i_2_n_0;
wire m_valid_i_i_3_n_0;
wire m_valid_i_reg;
wire m_valid_i_reg_0;
wire [0:0]mi_bvalid;
wire [0:0]mi_wready;
wire p_0_in1_in;
wire [48:1]s_amesg;
wire \s_arvalid_reg[0]_i_1_n_0 ;
wire \s_arvalid_reg_reg_n_0_[0] ;
wire s_awvalid_reg;
wire \s_awvalid_reg[0]_i_1_n_0 ;
wire [31:0]s_axi_araddr;
wire [2:0]s_axi_arprot;
wire [0:0]s_axi_arready;
wire [0:0]s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [2:0]s_axi_awprot;
wire [0:0]s_axi_awready;
wire [0:0]s_axi_awvalid;
wire [0:0]s_axi_bready;
wire [0:0]s_axi_bvalid;
wire [0:0]s_axi_rready;
wire [0:0]s_axi_rvalid;
wire [0:0]s_axi_wready;
wire [0:0]s_axi_wvalid;
wire s_ready_i;
wire s_ready_i_reg;
wire sr_rvalid;
LUT6 #(
.INIT(64'h5C505050F0F0F0F0))
\gen_axilite.s_axi_bvalid_i_i_1
(.I0(\gen_axilite.s_axi_bvalid_i_reg ),
.I1(mi_wready),
.I2(mi_bvalid),
.I3(\gen_axilite.s_axi_bvalid_i_reg_0 ),
.I4(\gen_axilite.s_axi_bvalid_i_reg_1 ),
.I5(Q[6]),
.O(\gen_axilite.s_axi_bvalid_i_reg_2 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'h04))
\gen_axilite.s_axi_bvalid_i_i_2
(.I0(m_ready_d[2]),
.I1(m_valid_i),
.I2(aa_grant_rnw),
.O(\gen_axilite.s_axi_bvalid_i_reg_1 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'h40))
\gen_axilite.s_axi_rvalid_i_i_2
(.I0(m_ready_d_1[1]),
.I1(m_valid_i),
.I2(aa_grant_rnw),
.O(\gen_axilite.s_axi_rvalid_i_reg ));
LUT6 #(
.INIT(64'hFFFFFF5300000050))
\gen_no_arbiter.grant_rnw_i_1
(.I0(s_awvalid_reg),
.I1(s_axi_awvalid),
.I2(s_axi_arvalid),
.I3(aa_grant_any),
.I4(m_valid_i),
.I5(aa_grant_rnw),
.O(\gen_no_arbiter.grant_rnw_i_1_n_0 ));
FDRE \gen_no_arbiter.grant_rnw_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_no_arbiter.grant_rnw_i_1_n_0 ),
.Q(aa_grant_rnw),
.R(SR));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[10]_i_1
(.I0(s_axi_araddr[9]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[9]),
.O(s_amesg[10]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[11]_i_1
(.I0(s_axi_araddr[10]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[10]),
.O(s_amesg[11]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[12]_i_1
(.I0(s_axi_araddr[11]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[11]),
.O(s_amesg[12]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[13]_i_1
(.I0(s_axi_araddr[12]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[12]),
.O(s_amesg[13]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[14]_i_1
(.I0(s_axi_araddr[13]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[13]),
.O(s_amesg[14]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[15]_i_1
(.I0(s_axi_araddr[14]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[14]),
.O(s_amesg[15]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[16]_i_1
(.I0(s_axi_araddr[15]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[15]),
.O(s_amesg[16]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[17]_i_1
(.I0(s_axi_araddr[16]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[16]),
.O(s_amesg[17]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[18]_i_1
(.I0(s_axi_araddr[17]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[17]),
.O(s_amesg[18]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[19]_i_1
(.I0(s_axi_araddr[18]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[18]),
.O(s_amesg[19]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[1]_i_1
(.I0(s_axi_araddr[0]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[0]),
.O(s_amesg[1]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[20]_i_1
(.I0(s_axi_araddr[19]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[19]),
.O(s_amesg[20]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[21]_i_1
(.I0(s_axi_araddr[20]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[20]),
.O(s_amesg[21]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[22]_i_1
(.I0(s_axi_araddr[21]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[21]),
.O(s_amesg[22]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[23]_i_1
(.I0(s_axi_araddr[22]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[22]),
.O(s_amesg[23]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[24]_i_1
(.I0(s_axi_araddr[23]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[23]),
.O(s_amesg[24]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[25]_i_1
(.I0(s_axi_araddr[24]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[24]),
.O(s_amesg[25]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[26]_i_1
(.I0(s_axi_araddr[25]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[25]),
.O(s_amesg[26]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[27]_i_1
(.I0(s_axi_araddr[26]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[26]),
.O(s_amesg[27]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[28]_i_1
(.I0(s_axi_araddr[27]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[27]),
.O(s_amesg[28]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[29]_i_1
(.I0(s_axi_araddr[28]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[28]),
.O(s_amesg[29]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[2]_i_1
(.I0(s_axi_araddr[1]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[1]),
.O(s_amesg[2]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[30]_i_1
(.I0(s_axi_araddr[29]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[29]),
.O(s_amesg[30]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[31]_i_1
(.I0(s_axi_araddr[30]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[30]),
.O(s_amesg[31]));
LUT1 #(
.INIT(2'h1))
\gen_no_arbiter.m_amesg_i[32]_i_1
(.I0(aresetn_d),
.O(SR));
LUT1 #(
.INIT(2'h1))
\gen_no_arbiter.m_amesg_i[32]_i_2
(.I0(aa_grant_any),
.O(p_0_in1_in));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[32]_i_3
(.I0(s_axi_araddr[31]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[31]),
.O(s_amesg[32]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[3]_i_1
(.I0(s_axi_araddr[2]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[2]),
.O(s_amesg[3]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[46]_i_1
(.I0(s_axi_arprot[0]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awprot[0]),
.O(s_amesg[46]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[47]_i_1
(.I0(s_axi_arprot[1]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awprot[1]),
.O(s_amesg[47]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[48]_i_1
(.I0(s_axi_arprot[2]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awprot[2]),
.O(s_amesg[48]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[4]_i_1
(.I0(s_axi_araddr[3]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[3]),
.O(s_amesg[4]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[5]_i_1
(.I0(s_axi_araddr[4]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[4]),
.O(s_amesg[5]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[6]_i_1
(.I0(s_axi_araddr[5]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[5]),
.O(s_amesg[6]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[7]_i_1
(.I0(s_axi_araddr[6]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[6]),
.O(s_amesg[7]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[8]_i_1
(.I0(s_axi_araddr[7]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[7]),
.O(s_amesg[8]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[9]_i_1
(.I0(s_axi_araddr[8]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[8]),
.O(s_amesg[9]));
FDRE \gen_no_arbiter.m_amesg_i_reg[10]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[10]),
.Q(\m_axi_arprot[2] [9]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[11]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[11]),
.Q(\m_axi_arprot[2] [10]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[12]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[12]),
.Q(\m_axi_arprot[2] [11]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[13]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[13]),
.Q(\m_axi_arprot[2] [12]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[14]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[14]),
.Q(\m_axi_arprot[2] [13]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[15]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[15]),
.Q(\m_axi_arprot[2] [14]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[16]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[16]),
.Q(\m_axi_arprot[2] [15]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[17]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[17]),
.Q(\m_axi_arprot[2] [16]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[18]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[18]),
.Q(\m_axi_arprot[2] [17]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[19]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[19]),
.Q(\m_axi_arprot[2] [18]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[1]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[1]),
.Q(\m_axi_arprot[2] [0]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[20]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[20]),
.Q(\m_axi_arprot[2] [19]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[21]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[21]),
.Q(\m_axi_arprot[2] [20]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[22]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[22]),
.Q(\m_axi_arprot[2] [21]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[23]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[23]),
.Q(\m_axi_arprot[2] [22]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[24]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[24]),
.Q(\m_axi_arprot[2] [23]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[25]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[25]),
.Q(\m_axi_arprot[2] [24]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[26]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[26]),
.Q(\m_axi_arprot[2] [25]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[27]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[27]),
.Q(\m_axi_arprot[2] [26]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[28]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[28]),
.Q(\m_axi_arprot[2] [27]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[29]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[29]),
.Q(\m_axi_arprot[2] [28]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[2]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[2]),
.Q(\m_axi_arprot[2] [1]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[30]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[30]),
.Q(\m_axi_arprot[2] [29]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[31]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[31]),
.Q(\m_axi_arprot[2] [30]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[32]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[32]),
.Q(\m_axi_arprot[2] [31]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[3]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[3]),
.Q(\m_axi_arprot[2] [2]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[46]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[46]),
.Q(\m_axi_arprot[2] [32]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[47]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[47]),
.Q(\m_axi_arprot[2] [33]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[48]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[48]),
.Q(\m_axi_arprot[2] [34]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[4]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[4]),
.Q(\m_axi_arprot[2] [3]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[5]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[5]),
.Q(\m_axi_arprot[2] [4]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[6]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[6]),
.Q(\m_axi_arprot[2] [5]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[7]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[7]),
.Q(\m_axi_arprot[2] [6]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[8]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[8]),
.Q(\m_axi_arprot[2] [7]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[9]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[9]),
.Q(\m_axi_arprot[2] [8]),
.R(SR));
LUT6 #(
.INIT(64'hAA00AAA800000000))
\gen_no_arbiter.m_grant_hot_i[0]_i_1
(.I0(\gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0 ),
.I1(s_axi_awvalid),
.I2(s_axi_arvalid),
.I3(aa_grant_any),
.I4(m_valid_i),
.I5(aresetn_d),
.O(\gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h00EFFFFFFFEFFFFF))
\gen_no_arbiter.m_grant_hot_i[0]_i_2
(.I0(\m_ready_d_reg[0]_1 ),
.I1(\m_ready_d_reg[1] ),
.I2(m_ready_d0),
.I3(aa_grant_rnw),
.I4(m_valid_i),
.I5(\m_ready_d[0]_i_4_n_0 ),
.O(\gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0 ));
LUT5 #(
.INIT(32'h30020002))
\gen_no_arbiter.m_grant_hot_i[0]_i_4
(.I0(m_axi_wready[0]),
.I1(\m_atarget_enc_reg[2]_3 [2]),
.I2(\m_atarget_enc_reg[2]_3 [1]),
.I3(\m_atarget_enc_reg[2]_3 [0]),
.I4(m_axi_wready[1]),
.O(\gen_no_arbiter.m_valid_i_reg_0 ));
FDRE \gen_no_arbiter.m_grant_hot_i_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0 ),
.Q(aa_grant_any),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hE4))
\gen_no_arbiter.m_valid_i_i_1
(.I0(m_valid_i),
.I1(aa_grant_any),
.I2(\gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0 ),
.O(\gen_no_arbiter.m_valid_i_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_no_arbiter.m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_no_arbiter.m_valid_i_i_1_n_0 ),
.Q(m_valid_i),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'h40))
\gen_no_arbiter.s_ready_i[0]_i_1
(.I0(m_valid_i),
.I1(aa_grant_any),
.I2(aresetn_d),
.O(\gen_no_arbiter.s_ready_i[0]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_no_arbiter.s_ready_i_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\gen_no_arbiter.s_ready_i[0]_i_1_n_0 ),
.Q(s_ready_i),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h8AAA))
\m_atarget_enc[0]_i_1
(.I0(aresetn_d),
.I1(\m_atarget_hot[6]_i_3_n_0 ),
.I2(\m_atarget_hot[6]_i_5_n_0 ),
.I3(\m_atarget_hot[5]_i_2_n_0 ),
.O(\m_atarget_enc_reg[2] [0]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'h0200))
\m_atarget_enc[1]_i_1
(.I0(aresetn_d),
.I1(\m_atarget_hot[6]_i_4_n_0 ),
.I2(\m_atarget_hot[6]_i_3_n_0 ),
.I3(\m_atarget_hot[6]_i_2_n_0 ),
.O(\m_atarget_enc_reg[2] [1]));
LUT6 #(
.INIT(64'h00000020AAAAAAAA))
\m_atarget_enc[2]_i_1
(.I0(aresetn_d),
.I1(\m_atarget_hot[6]_i_6_n_0 ),
.I2(\m_atarget_hot[6]_i_5_n_0 ),
.I3(\m_atarget_hot[6]_i_4_n_0 ),
.I4(\m_atarget_hot[6]_i_3_n_0 ),
.I5(\m_atarget_hot[6]_i_2_n_0 ),
.O(\m_atarget_enc_reg[2] [2]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h8))
\m_atarget_hot[0]_i_1
(.I0(\m_atarget_hot[6]_i_4_n_0 ),
.I1(aa_grant_any),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h8))
\m_atarget_hot[1]_i_1
(.I0(\m_atarget_hot[6]_i_3_n_0 ),
.I1(aa_grant_any),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'h8))
\m_atarget_hot[2]_i_1
(.I0(\m_atarget_hot[6]_i_6_n_0 ),
.I1(aa_grant_any),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h2))
\m_atarget_hot[3]_i_1
(.I0(aa_grant_any),
.I1(\m_atarget_hot[6]_i_5_n_0 ),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h8))
\m_atarget_hot[4]_i_1
(.I0(\m_atarget_hot[4]_i_2_n_0 ),
.I1(aa_grant_any),
.O(D[4]));
LUT6 #(
.INIT(64'h0000000000000001))
\m_atarget_hot[4]_i_2
(.I0(\m_axi_arprot[2] [17]),
.I1(\m_atarget_hot[6]_i_8_n_0 ),
.I2(\m_axi_arprot[2] [16]),
.I3(\m_axi_arprot[2] [19]),
.I4(\m_axi_arprot[2] [18]),
.I5(\m_atarget_hot[6]_i_7_n_0 ),
.O(\m_atarget_hot[4]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h2))
\m_atarget_hot[5]_i_1
(.I0(aa_grant_any),
.I1(\m_atarget_hot[5]_i_2_n_0 ),
.O(D[5]));
LUT6 #(
.INIT(64'hFFFFFFFEFFFFFFFF))
\m_atarget_hot[5]_i_2
(.I0(\m_atarget_hot[6]_i_7_n_0 ),
.I1(\m_axi_arprot[2] [17]),
.I2(\m_atarget_hot[6]_i_8_n_0 ),
.I3(\m_axi_arprot[2] [19]),
.I4(\m_axi_arprot[2] [18]),
.I5(\m_axi_arprot[2] [16]),
.O(\m_atarget_hot[5]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000020000000000))
\m_atarget_hot[6]_i_1
(.I0(\m_atarget_hot[6]_i_2_n_0 ),
.I1(\m_atarget_hot[6]_i_3_n_0 ),
.I2(\m_atarget_hot[6]_i_4_n_0 ),
.I3(\m_atarget_hot[6]_i_5_n_0 ),
.I4(\m_atarget_hot[6]_i_6_n_0 ),
.I5(aa_grant_any),
.O(D[6]));
LUT6 #(
.INIT(64'hFDFFFFFFFFFFFFFF))
\m_atarget_hot[6]_i_10
(.I0(\m_axi_arprot[2] [24]),
.I1(\m_axi_arprot[2] [20]),
.I2(\m_axi_arprot[2] [21]),
.I3(\m_axi_arprot[2] [23]),
.I4(\m_axi_arprot[2] [22]),
.I5(\m_axi_arprot[2] [25]),
.O(\m_atarget_hot[6]_i_10_n_0 ));
LUT5 #(
.INIT(32'hFFFFFFFE))
\m_atarget_hot[6]_i_11
(.I0(\m_axi_arprot[2] [18]),
.I1(\m_axi_arprot[2] [19]),
.I2(\m_axi_arprot[2] [16]),
.I3(\m_axi_arprot[2] [13]),
.I4(\m_axi_arprot[2] [12]),
.O(\m_atarget_hot[6]_i_11_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hEF))
\m_atarget_hot[6]_i_12
(.I0(\m_axi_arprot[2] [19]),
.I1(\m_axi_arprot[2] [18]),
.I2(\m_axi_arprot[2] [16]),
.O(\m_atarget_hot[6]_i_12_n_0 ));
LUT5 #(
.INIT(32'hFFFFFFFE))
\m_atarget_hot[6]_i_2
(.I0(\m_atarget_hot[6]_i_7_n_0 ),
.I1(\m_axi_arprot[2] [18]),
.I2(\m_axi_arprot[2] [19]),
.I3(\m_atarget_hot[6]_i_8_n_0 ),
.I4(\m_axi_arprot[2] [17]),
.O(\m_atarget_hot[6]_i_2_n_0 ));
LUT3 #(
.INIT(8'h01))
\m_atarget_hot[6]_i_3
(.I0(\m_atarget_hot[6]_i_9_n_0 ),
.I1(\m_atarget_hot[6]_i_10_n_0 ),
.I2(\m_axi_arprot[2] [15]),
.O(\m_atarget_hot[6]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0000000000010000))
\m_atarget_hot[6]_i_4
(.I0(\m_atarget_hot[6]_i_10_n_0 ),
.I1(\m_atarget_hot[6]_i_8_n_0 ),
.I2(\m_atarget_hot[6]_i_11_n_0 ),
.I3(\m_axi_arprot[2] [14]),
.I4(\m_axi_arprot[2] [17]),
.I5(\m_axi_arprot[2] [15]),
.O(\m_atarget_hot[6]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFEFFFF))
\m_atarget_hot[6]_i_5
(.I0(\m_atarget_hot[6]_i_10_n_0 ),
.I1(\m_atarget_hot[6]_i_8_n_0 ),
.I2(\m_atarget_hot[6]_i_12_n_0 ),
.I3(\m_axi_arprot[2] [14]),
.I4(\m_axi_arprot[2] [17]),
.I5(\m_axi_arprot[2] [15]),
.O(\m_atarget_hot[6]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\m_atarget_hot[6]_i_6
(.I0(\m_atarget_hot[6]_i_10_n_0 ),
.I1(\m_axi_arprot[2] [17]),
.I2(\m_atarget_hot[6]_i_8_n_0 ),
.I3(\m_axi_arprot[2] [16]),
.I4(\m_axi_arprot[2] [19]),
.I5(\m_axi_arprot[2] [18]),
.O(\m_atarget_hot[6]_i_6_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFDFF))
\m_atarget_hot[6]_i_7
(.I0(\m_axi_arprot[2] [24]),
.I1(\m_axi_arprot[2] [20]),
.I2(\m_axi_arprot[2] [25]),
.I3(\m_axi_arprot[2] [21]),
.I4(\m_axi_arprot[2] [23]),
.I5(\m_axi_arprot[2] [22]),
.O(\m_atarget_hot[6]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFEFF))
\m_atarget_hot[6]_i_8
(.I0(\m_axi_arprot[2] [26]),
.I1(\m_axi_arprot[2] [29]),
.I2(\m_axi_arprot[2] [27]),
.I3(\m_axi_arprot[2] [30]),
.I4(\m_axi_arprot[2] [31]),
.I5(\m_axi_arprot[2] [28]),
.O(\m_atarget_hot[6]_i_8_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'hFFFFFFFD))
\m_atarget_hot[6]_i_9
(.I0(\m_axi_arprot[2] [16]),
.I1(\m_axi_arprot[2] [18]),
.I2(\m_axi_arprot[2] [19]),
.I3(\m_atarget_hot[6]_i_8_n_0 ),
.I4(\m_axi_arprot[2] [17]),
.O(\m_atarget_hot[6]_i_9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'h0080))
\m_axi_arvalid[0]_INST_0
(.I0(Q[0]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d_1[1]),
.O(m_axi_arvalid[0]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'h0080))
\m_axi_arvalid[1]_INST_0
(.I0(Q[1]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d_1[1]),
.O(m_axi_arvalid[1]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h0080))
\m_axi_arvalid[2]_INST_0
(.I0(Q[2]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d_1[1]),
.O(m_axi_arvalid[2]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'h0080))
\m_axi_arvalid[3]_INST_0
(.I0(Q[3]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d_1[1]),
.O(m_axi_arvalid[3]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h0080))
\m_axi_arvalid[4]_INST_0
(.I0(Q[4]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d_1[1]),
.O(m_axi_arvalid[4]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h0080))
\m_axi_arvalid[5]_INST_0
(.I0(Q[5]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d_1[1]),
.O(m_axi_arvalid[5]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'h0020))
\m_axi_awvalid[0]_INST_0
(.I0(Q[0]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d[2]),
.O(m_axi_awvalid[0]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'h0020))
\m_axi_awvalid[1]_INST_0
(.I0(Q[1]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d[2]),
.O(m_axi_awvalid[1]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h0020))
\m_axi_awvalid[2]_INST_0
(.I0(Q[2]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d[2]),
.O(m_axi_awvalid[2]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'h0020))
\m_axi_awvalid[3]_INST_0
(.I0(Q[3]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d[2]),
.O(m_axi_awvalid[3]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h0020))
\m_axi_awvalid[4]_INST_0
(.I0(Q[4]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d[2]),
.O(m_axi_awvalid[4]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h0020))
\m_axi_awvalid[5]_INST_0
(.I0(Q[5]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d[2]),
.O(m_axi_awvalid[5]));
LUT5 #(
.INIT(32'h00200000))
\m_axi_bready[0]_INST_0
(.I0(Q[0]),
.I1(m_ready_d[0]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_bready),
.O(m_axi_bready[0]));
LUT5 #(
.INIT(32'h00200000))
\m_axi_bready[1]_INST_0
(.I0(Q[1]),
.I1(m_ready_d[0]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_bready),
.O(m_axi_bready[1]));
LUT5 #(
.INIT(32'h00200000))
\m_axi_bready[2]_INST_0
(.I0(Q[2]),
.I1(m_ready_d[0]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_bready),
.O(m_axi_bready[2]));
LUT5 #(
.INIT(32'h00200000))
\m_axi_bready[3]_INST_0
(.I0(Q[3]),
.I1(m_ready_d[0]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_bready),
.O(m_axi_bready[3]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'h00200000))
\m_axi_bready[4]_INST_0
(.I0(Q[4]),
.I1(m_ready_d[0]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_bready),
.O(m_axi_bready[4]));
LUT5 #(
.INIT(32'h00200000))
\m_axi_bready[5]_INST_0
(.I0(Q[5]),
.I1(m_ready_d[0]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_bready),
.O(m_axi_bready[5]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h00200000))
\m_axi_wvalid[0]_INST_0
(.I0(Q[0]),
.I1(m_ready_d[1]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_wvalid),
.O(m_axi_wvalid[0]));
LUT5 #(
.INIT(32'h00200000))
\m_axi_wvalid[1]_INST_0
(.I0(Q[1]),
.I1(m_ready_d[1]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_wvalid),
.O(m_axi_wvalid[1]));
LUT5 #(
.INIT(32'h00200000))
\m_axi_wvalid[2]_INST_0
(.I0(Q[2]),
.I1(m_ready_d[1]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_wvalid),
.O(m_axi_wvalid[2]));
LUT5 #(
.INIT(32'h00200000))
\m_axi_wvalid[3]_INST_0
(.I0(Q[3]),
.I1(m_ready_d[1]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_wvalid),
.O(m_axi_wvalid[3]));
LUT5 #(
.INIT(32'h00200000))
\m_axi_wvalid[4]_INST_0
(.I0(Q[4]),
.I1(m_ready_d[1]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_wvalid),
.O(m_axi_wvalid[4]));
LUT5 #(
.INIT(32'h00200000))
\m_axi_wvalid[5]_INST_0
(.I0(Q[5]),
.I1(m_ready_d[1]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_wvalid),
.O(m_axi_wvalid[5]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h0080FFFF))
\m_payload_i[34]_i_1
(.I0(s_axi_rready),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d_1[0]),
.I4(sr_rvalid),
.O(E));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h0020))
\m_ready_d[0]_i_2
(.I0(s_axi_bready),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d[0]),
.O(\gen_axilite.s_axi_bvalid_i_reg ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT2 #(
.INIT(4'h7))
\m_ready_d[0]_i_2__0
(.I0(aa_grant_rnw),
.I1(m_valid_i),
.O(\m_ready_d_reg[0]_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'hB))
\m_ready_d[0]_i_3
(.I0(\m_ready_d[0]_i_4_n_0 ),
.I1(aresetn_d),
.O(\m_ready_d_reg[0] ));
LUT6 #(
.INIT(64'h00000000FFFFA8AA))
\m_ready_d[0]_i_4
(.I0(\gen_axilite.s_axi_rvalid_i_reg ),
.I1(\m_atarget_enc_reg[1]_2 ),
.I2(\gen_axilite.s_axi_arready_i_reg ),
.I3(\m_atarget_enc_reg[1]_3 ),
.I4(m_ready_d_1[1]),
.I5(m_valid_i_reg_0),
.O(\m_ready_d[0]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h0020))
\m_ready_d[1]_i_2
(.I0(s_axi_wvalid),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d[1]),
.O(\gen_axilite.s_axi_bvalid_i_reg_0 ));
LUT6 #(
.INIT(64'hFFFDFF00FF00FF00))
\m_ready_d[1]_i_2__0
(.I0(\m_atarget_enc_reg[1]_3 ),
.I1(\gen_axilite.s_axi_arready_i_reg ),
.I2(\m_atarget_enc_reg[1]_2 ),
.I3(m_ready_d_1[1]),
.I4(m_valid_i),
.I5(aa_grant_rnw),
.O(m_ready_d0_0));
LUT6 #(
.INIT(64'hFF00FF00FFFDFF00))
\m_ready_d[2]_i_2
(.I0(\m_atarget_enc_reg[2]_1 ),
.I1(\m_atarget_enc_reg[2]_2 ),
.I2(\m_atarget_enc_reg[1]_0 ),
.I3(m_ready_d[2]),
.I4(m_valid_i),
.I5(aa_grant_rnw),
.O(m_ready_d0));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'h8A))
m_valid_i_i_1
(.I0(\aresetn_d_reg[1] [1]),
.I1(m_valid_i_i_2_n_0),
.I2(m_valid_i_i_3_n_0),
.O(m_valid_i_reg));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h8AAAAAAA))
m_valid_i_i_2
(.I0(sr_rvalid),
.I1(m_ready_d_1[0]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_rready),
.O(m_valid_i_i_2_n_0));
LUT6 #(
.INIT(64'h8AAAAAAA8AAA8AAA))
m_valid_i_i_3
(.I0(aa_rready),
.I1(m_ready_d_1[0]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(\m_atarget_enc_reg[0] ),
.I5(\m_atarget_enc_reg[1]_1 ),
.O(m_valid_i_i_3_n_0));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'h0040))
\s_arvalid_reg[0]_i_1
(.I0(s_awvalid_reg),
.I1(s_axi_arvalid),
.I2(aresetn_d),
.I3(s_ready_i),
.O(\s_arvalid_reg[0]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\s_arvalid_reg_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\s_arvalid_reg[0]_i_1_n_0 ),
.Q(\s_arvalid_reg_reg_n_0_[0] ),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000000D00000))
\s_awvalid_reg[0]_i_1
(.I0(s_axi_arvalid),
.I1(s_awvalid_reg),
.I2(s_axi_awvalid),
.I3(\s_arvalid_reg_reg_n_0_[0] ),
.I4(aresetn_d),
.I5(s_ready_i),
.O(\s_awvalid_reg[0]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\s_awvalid_reg_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\s_awvalid_reg[0]_i_1_n_0 ),
.Q(s_awvalid_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h8))
\s_axi_arready[0]_INST_0
(.I0(s_ready_i),
.I1(aa_grant_rnw),
.O(s_axi_arready));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT2 #(
.INIT(4'h2))
\s_axi_awready[0]_INST_0
(.I0(s_ready_i),
.I1(aa_grant_rnw),
.O(s_axi_awready));
LUT5 #(
.INIT(32'h00000400))
\s_axi_bvalid[0]_INST_0
(.I0(m_ready_d[0]),
.I1(m_valid_i),
.I2(aa_grant_rnw),
.I3(aa_grant_any),
.I4(\m_atarget_enc_reg[1] ),
.O(s_axi_bvalid));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h8))
\s_axi_rvalid[0]_INST_0
(.I0(aa_grant_any),
.I1(sr_rvalid),
.O(s_axi_rvalid));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h00000400))
\s_axi_wready[0]_INST_0
(.I0(m_ready_d[1]),
.I1(m_valid_i),
.I2(aa_grant_rnw),
.I3(aa_grant_any),
.I4(\m_atarget_enc_reg[2]_0 ),
.O(s_axi_wready));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'h8A))
s_ready_i_i_1
(.I0(\aresetn_d_reg[1] [0]),
.I1(m_valid_i_i_3_n_0),
.I2(m_valid_i_i_2_n_0),
.O(s_ready_i_reg));
endmodule
(* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "32" *) (* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_PROTOCOL = "2" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_WUSER_WIDTH = "1" *) (* C_CONNECTIVITY_MODE = "0" *) (* C_DEBUG = "1" *)
(* C_FAMILY = "zynq" *) (* C_M_AXI_ADDR_WIDTH = "192'b000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000001110000000000000000000000000000100000000000000000000000000000000111100000000000000000000000000001100" *) (* C_M_AXI_BASE_ADDR = "384'b000000000000000000000000000000000100000100100001000000000000000000000000000000000000000000000000010000010010000000000000000000000000000000000000000000000000000001000011110000110000000000000000000000000000000000000000000000000100001111000000000000000000000000000000000000000000000000000000010000111100000100000000000000000000000000000000000000000000000001000011110000100000000000000000" *)
(* C_M_AXI_READ_CONNECTIVITY = "192'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_M_AXI_READ_ISSUING = "192'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_M_AXI_SECURE = "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* C_M_AXI_WRITE_CONNECTIVITY = "192'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_M_AXI_WRITE_ISSUING = "192'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_NUM_ADDR_RANGES = "1" *)
(* C_NUM_MASTER_SLOTS = "6" *) (* C_NUM_SLAVE_SLOTS = "1" *) (* C_R_REGISTER = "1" *)
(* C_S_AXI_ARB_PRIORITY = "0" *) (* C_S_AXI_BASE_ID = "0" *) (* C_S_AXI_READ_ACCEPTANCE = "1" *)
(* C_S_AXI_SINGLE_THREAD = "1" *) (* C_S_AXI_THREAD_ID_WIDTH = "0" *) (* C_S_AXI_WRITE_ACCEPTANCE = "1" *)
(* DowngradeIPIdentifiedWarnings = "yes" *) (* P_ADDR_DECODE = "1" *) (* P_AXI3 = "1" *)
(* P_AXI4 = "0" *) (* P_AXILITE = "2" *) (* P_AXILITE_SIZE = "3'b010" *)
(* P_FAMILY = "zynq" *) (* P_INCR = "2'b01" *) (* P_LEN = "8" *)
(* P_LOCK = "1" *) (* P_M_AXI_ERR_MODE = "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* P_M_AXI_SUPPORTS_READ = "6'b111111" *)
(* P_M_AXI_SUPPORTS_WRITE = "6'b111111" *) (* P_ONES = "65'b11111111111111111111111111111111111111111111111111111111111111111" *) (* P_RANGE_CHECK = "1" *)
(* P_S_AXI_BASE_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* P_S_AXI_HIGH_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* P_S_AXI_SUPPORTS_READ = "1'b1" *)
(* P_S_AXI_SUPPORTS_WRITE = "1'b1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready);
input aclk;
input aresetn;
input [0:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [0:0]s_axi_awuser;
input [0:0]s_axi_awvalid;
output [0:0]s_axi_awready;
input [0:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input [0:0]s_axi_wlast;
input [0:0]s_axi_wuser;
input [0:0]s_axi_wvalid;
output [0:0]s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output [0:0]s_axi_bvalid;
input [0:0]s_axi_bready;
input [0:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [0:0]s_axi_aruser;
input [0:0]s_axi_arvalid;
output [0:0]s_axi_arready;
output [0:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output [0:0]s_axi_rlast;
output [0:0]s_axi_ruser;
output [0:0]s_axi_rvalid;
input [0:0]s_axi_rready;
output [5:0]m_axi_awid;
output [191:0]m_axi_awaddr;
output [47:0]m_axi_awlen;
output [17:0]m_axi_awsize;
output [11:0]m_axi_awburst;
output [5:0]m_axi_awlock;
output [23:0]m_axi_awcache;
output [17:0]m_axi_awprot;
output [23:0]m_axi_awregion;
output [23:0]m_axi_awqos;
output [5:0]m_axi_awuser;
output [5:0]m_axi_awvalid;
input [5:0]m_axi_awready;
output [5:0]m_axi_wid;
output [191:0]m_axi_wdata;
output [23:0]m_axi_wstrb;
output [5:0]m_axi_wlast;
output [5:0]m_axi_wuser;
output [5:0]m_axi_wvalid;
input [5:0]m_axi_wready;
input [5:0]m_axi_bid;
input [11:0]m_axi_bresp;
input [5:0]m_axi_buser;
input [5:0]m_axi_bvalid;
output [5:0]m_axi_bready;
output [5:0]m_axi_arid;
output [191:0]m_axi_araddr;
output [47:0]m_axi_arlen;
output [17:0]m_axi_arsize;
output [11:0]m_axi_arburst;
output [5:0]m_axi_arlock;
output [23:0]m_axi_arcache;
output [17:0]m_axi_arprot;
output [23:0]m_axi_arregion;
output [23:0]m_axi_arqos;
output [5:0]m_axi_aruser;
output [5:0]m_axi_arvalid;
input [5:0]m_axi_arready;
input [5:0]m_axi_rid;
input [191:0]m_axi_rdata;
input [11:0]m_axi_rresp;
input [5:0]m_axi_rlast;
input [5:0]m_axi_ruser;
input [5:0]m_axi_rvalid;
output [5:0]m_axi_rready;
wire \<const0> ;
wire aclk;
wire aresetn;
wire [11:0]\^m_axi_araddr ;
wire [2:0]\^m_axi_arprot ;
wire [5:0]m_axi_arready;
wire [5:0]m_axi_arvalid;
wire [191:172]\^m_axi_awaddr ;
wire [5:0]m_axi_awready;
wire [5:0]m_axi_awvalid;
wire [5:0]m_axi_bready;
wire [11:0]m_axi_bresp;
wire [5:0]m_axi_bvalid;
wire [191:0]m_axi_rdata;
wire [5:0]m_axi_rready;
wire [11:0]m_axi_rresp;
wire [5:0]m_axi_rvalid;
wire [5:0]m_axi_wready;
wire [5:0]m_axi_wvalid;
wire [31:0]s_axi_araddr;
wire [2:0]s_axi_arprot;
wire [0:0]s_axi_arready;
wire [0:0]s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [2:0]s_axi_awprot;
wire [0:0]s_axi_awready;
wire [0:0]s_axi_awvalid;
wire [0:0]s_axi_bready;
wire [1:0]s_axi_bresp;
wire [0:0]s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [0:0]s_axi_rready;
wire [1:0]s_axi_rresp;
wire [0:0]s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire [0:0]s_axi_wready;
wire [3:0]s_axi_wstrb;
wire [0:0]s_axi_wvalid;
assign m_axi_araddr[191:172] = \^m_axi_awaddr [191:172];
assign m_axi_araddr[171:160] = \^m_axi_araddr [11:0];
assign m_axi_araddr[159:140] = \^m_axi_awaddr [191:172];
assign m_axi_araddr[139:128] = \^m_axi_araddr [11:0];
assign m_axi_araddr[127:108] = \^m_axi_awaddr [191:172];
assign m_axi_araddr[107:96] = \^m_axi_araddr [11:0];
assign m_axi_araddr[95:76] = \^m_axi_awaddr [191:172];
assign m_axi_araddr[75:64] = \^m_axi_araddr [11:0];
assign m_axi_araddr[63:44] = \^m_axi_awaddr [191:172];
assign m_axi_araddr[43:32] = \^m_axi_araddr [11:0];
assign m_axi_araddr[31:12] = \^m_axi_awaddr [191:172];
assign m_axi_araddr[11:0] = \^m_axi_araddr [11:0];
assign m_axi_arburst[11] = \<const0> ;
assign m_axi_arburst[10] = \<const0> ;
assign m_axi_arburst[9] = \<const0> ;
assign m_axi_arburst[8] = \<const0> ;
assign m_axi_arburst[7] = \<const0> ;
assign m_axi_arburst[6] = \<const0> ;
assign m_axi_arburst[5] = \<const0> ;
assign m_axi_arburst[4] = \<const0> ;
assign m_axi_arburst[3] = \<const0> ;
assign m_axi_arburst[2] = \<const0> ;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const0> ;
assign m_axi_arcache[23] = \<const0> ;
assign m_axi_arcache[22] = \<const0> ;
assign m_axi_arcache[21] = \<const0> ;
assign m_axi_arcache[20] = \<const0> ;
assign m_axi_arcache[19] = \<const0> ;
assign m_axi_arcache[18] = \<const0> ;
assign m_axi_arcache[17] = \<const0> ;
assign m_axi_arcache[16] = \<const0> ;
assign m_axi_arcache[15] = \<const0> ;
assign m_axi_arcache[14] = \<const0> ;
assign m_axi_arcache[13] = \<const0> ;
assign m_axi_arcache[12] = \<const0> ;
assign m_axi_arcache[11] = \<const0> ;
assign m_axi_arcache[10] = \<const0> ;
assign m_axi_arcache[9] = \<const0> ;
assign m_axi_arcache[8] = \<const0> ;
assign m_axi_arcache[7] = \<const0> ;
assign m_axi_arcache[6] = \<const0> ;
assign m_axi_arcache[5] = \<const0> ;
assign m_axi_arcache[4] = \<const0> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[5] = \<const0> ;
assign m_axi_arid[4] = \<const0> ;
assign m_axi_arid[3] = \<const0> ;
assign m_axi_arid[2] = \<const0> ;
assign m_axi_arid[1] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[47] = \<const0> ;
assign m_axi_arlen[46] = \<const0> ;
assign m_axi_arlen[45] = \<const0> ;
assign m_axi_arlen[44] = \<const0> ;
assign m_axi_arlen[43] = \<const0> ;
assign m_axi_arlen[42] = \<const0> ;
assign m_axi_arlen[41] = \<const0> ;
assign m_axi_arlen[40] = \<const0> ;
assign m_axi_arlen[39] = \<const0> ;
assign m_axi_arlen[38] = \<const0> ;
assign m_axi_arlen[37] = \<const0> ;
assign m_axi_arlen[36] = \<const0> ;
assign m_axi_arlen[35] = \<const0> ;
assign m_axi_arlen[34] = \<const0> ;
assign m_axi_arlen[33] = \<const0> ;
assign m_axi_arlen[32] = \<const0> ;
assign m_axi_arlen[31] = \<const0> ;
assign m_axi_arlen[30] = \<const0> ;
assign m_axi_arlen[29] = \<const0> ;
assign m_axi_arlen[28] = \<const0> ;
assign m_axi_arlen[27] = \<const0> ;
assign m_axi_arlen[26] = \<const0> ;
assign m_axi_arlen[25] = \<const0> ;
assign m_axi_arlen[24] = \<const0> ;
assign m_axi_arlen[23] = \<const0> ;
assign m_axi_arlen[22] = \<const0> ;
assign m_axi_arlen[21] = \<const0> ;
assign m_axi_arlen[20] = \<const0> ;
assign m_axi_arlen[19] = \<const0> ;
assign m_axi_arlen[18] = \<const0> ;
assign m_axi_arlen[17] = \<const0> ;
assign m_axi_arlen[16] = \<const0> ;
assign m_axi_arlen[15] = \<const0> ;
assign m_axi_arlen[14] = \<const0> ;
assign m_axi_arlen[13] = \<const0> ;
assign m_axi_arlen[12] = \<const0> ;
assign m_axi_arlen[11] = \<const0> ;
assign m_axi_arlen[10] = \<const0> ;
assign m_axi_arlen[9] = \<const0> ;
assign m_axi_arlen[8] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[5] = \<const0> ;
assign m_axi_arlock[4] = \<const0> ;
assign m_axi_arlock[3] = \<const0> ;
assign m_axi_arlock[2] = \<const0> ;
assign m_axi_arlock[1] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arprot[17:15] = \^m_axi_arprot [2:0];
assign m_axi_arprot[14:12] = \^m_axi_arprot [2:0];
assign m_axi_arprot[11:9] = \^m_axi_arprot [2:0];
assign m_axi_arprot[8:6] = \^m_axi_arprot [2:0];
assign m_axi_arprot[5:3] = \^m_axi_arprot [2:0];
assign m_axi_arprot[2:0] = \^m_axi_arprot [2:0];
assign m_axi_arqos[23] = \<const0> ;
assign m_axi_arqos[22] = \<const0> ;
assign m_axi_arqos[21] = \<const0> ;
assign m_axi_arqos[20] = \<const0> ;
assign m_axi_arqos[19] = \<const0> ;
assign m_axi_arqos[18] = \<const0> ;
assign m_axi_arqos[17] = \<const0> ;
assign m_axi_arqos[16] = \<const0> ;
assign m_axi_arqos[15] = \<const0> ;
assign m_axi_arqos[14] = \<const0> ;
assign m_axi_arqos[13] = \<const0> ;
assign m_axi_arqos[12] = \<const0> ;
assign m_axi_arqos[11] = \<const0> ;
assign m_axi_arqos[10] = \<const0> ;
assign m_axi_arqos[9] = \<const0> ;
assign m_axi_arqos[8] = \<const0> ;
assign m_axi_arqos[7] = \<const0> ;
assign m_axi_arqos[6] = \<const0> ;
assign m_axi_arqos[5] = \<const0> ;
assign m_axi_arqos[4] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[23] = \<const0> ;
assign m_axi_arregion[22] = \<const0> ;
assign m_axi_arregion[21] = \<const0> ;
assign m_axi_arregion[20] = \<const0> ;
assign m_axi_arregion[19] = \<const0> ;
assign m_axi_arregion[18] = \<const0> ;
assign m_axi_arregion[17] = \<const0> ;
assign m_axi_arregion[16] = \<const0> ;
assign m_axi_arregion[15] = \<const0> ;
assign m_axi_arregion[14] = \<const0> ;
assign m_axi_arregion[13] = \<const0> ;
assign m_axi_arregion[12] = \<const0> ;
assign m_axi_arregion[11] = \<const0> ;
assign m_axi_arregion[10] = \<const0> ;
assign m_axi_arregion[9] = \<const0> ;
assign m_axi_arregion[8] = \<const0> ;
assign m_axi_arregion[7] = \<const0> ;
assign m_axi_arregion[6] = \<const0> ;
assign m_axi_arregion[5] = \<const0> ;
assign m_axi_arregion[4] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[17] = \<const0> ;
assign m_axi_arsize[16] = \<const0> ;
assign m_axi_arsize[15] = \<const0> ;
assign m_axi_arsize[14] = \<const0> ;
assign m_axi_arsize[13] = \<const0> ;
assign m_axi_arsize[12] = \<const0> ;
assign m_axi_arsize[11] = \<const0> ;
assign m_axi_arsize[10] = \<const0> ;
assign m_axi_arsize[9] = \<const0> ;
assign m_axi_arsize[8] = \<const0> ;
assign m_axi_arsize[7] = \<const0> ;
assign m_axi_arsize[6] = \<const0> ;
assign m_axi_arsize[5] = \<const0> ;
assign m_axi_arsize[4] = \<const0> ;
assign m_axi_arsize[3] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const0> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[5] = \<const0> ;
assign m_axi_aruser[4] = \<const0> ;
assign m_axi_aruser[3] = \<const0> ;
assign m_axi_aruser[2] = \<const0> ;
assign m_axi_aruser[1] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_awaddr[191:172] = \^m_axi_awaddr [191:172];
assign m_axi_awaddr[171:160] = \^m_axi_araddr [11:0];
assign m_axi_awaddr[159:140] = \^m_axi_awaddr [191:172];
assign m_axi_awaddr[139:128] = \^m_axi_araddr [11:0];
assign m_axi_awaddr[127:108] = \^m_axi_awaddr [191:172];
assign m_axi_awaddr[107:96] = \^m_axi_araddr [11:0];
assign m_axi_awaddr[95:76] = \^m_axi_awaddr [191:172];
assign m_axi_awaddr[75:64] = \^m_axi_araddr [11:0];
assign m_axi_awaddr[63:44] = \^m_axi_awaddr [191:172];
assign m_axi_awaddr[43:32] = \^m_axi_araddr [11:0];
assign m_axi_awaddr[31:12] = \^m_axi_awaddr [191:172];
assign m_axi_awaddr[11:0] = \^m_axi_araddr [11:0];
assign m_axi_awburst[11] = \<const0> ;
assign m_axi_awburst[10] = \<const0> ;
assign m_axi_awburst[9] = \<const0> ;
assign m_axi_awburst[8] = \<const0> ;
assign m_axi_awburst[7] = \<const0> ;
assign m_axi_awburst[6] = \<const0> ;
assign m_axi_awburst[5] = \<const0> ;
assign m_axi_awburst[4] = \<const0> ;
assign m_axi_awburst[3] = \<const0> ;
assign m_axi_awburst[2] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const0> ;
assign m_axi_awcache[23] = \<const0> ;
assign m_axi_awcache[22] = \<const0> ;
assign m_axi_awcache[21] = \<const0> ;
assign m_axi_awcache[20] = \<const0> ;
assign m_axi_awcache[19] = \<const0> ;
assign m_axi_awcache[18] = \<const0> ;
assign m_axi_awcache[17] = \<const0> ;
assign m_axi_awcache[16] = \<const0> ;
assign m_axi_awcache[15] = \<const0> ;
assign m_axi_awcache[14] = \<const0> ;
assign m_axi_awcache[13] = \<const0> ;
assign m_axi_awcache[12] = \<const0> ;
assign m_axi_awcache[11] = \<const0> ;
assign m_axi_awcache[10] = \<const0> ;
assign m_axi_awcache[9] = \<const0> ;
assign m_axi_awcache[8] = \<const0> ;
assign m_axi_awcache[7] = \<const0> ;
assign m_axi_awcache[6] = \<const0> ;
assign m_axi_awcache[5] = \<const0> ;
assign m_axi_awcache[4] = \<const0> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[5] = \<const0> ;
assign m_axi_awid[4] = \<const0> ;
assign m_axi_awid[3] = \<const0> ;
assign m_axi_awid[2] = \<const0> ;
assign m_axi_awid[1] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[47] = \<const0> ;
assign m_axi_awlen[46] = \<const0> ;
assign m_axi_awlen[45] = \<const0> ;
assign m_axi_awlen[44] = \<const0> ;
assign m_axi_awlen[43] = \<const0> ;
assign m_axi_awlen[42] = \<const0> ;
assign m_axi_awlen[41] = \<const0> ;
assign m_axi_awlen[40] = \<const0> ;
assign m_axi_awlen[39] = \<const0> ;
assign m_axi_awlen[38] = \<const0> ;
assign m_axi_awlen[37] = \<const0> ;
assign m_axi_awlen[36] = \<const0> ;
assign m_axi_awlen[35] = \<const0> ;
assign m_axi_awlen[34] = \<const0> ;
assign m_axi_awlen[33] = \<const0> ;
assign m_axi_awlen[32] = \<const0> ;
assign m_axi_awlen[31] = \<const0> ;
assign m_axi_awlen[30] = \<const0> ;
assign m_axi_awlen[29] = \<const0> ;
assign m_axi_awlen[28] = \<const0> ;
assign m_axi_awlen[27] = \<const0> ;
assign m_axi_awlen[26] = \<const0> ;
assign m_axi_awlen[25] = \<const0> ;
assign m_axi_awlen[24] = \<const0> ;
assign m_axi_awlen[23] = \<const0> ;
assign m_axi_awlen[22] = \<const0> ;
assign m_axi_awlen[21] = \<const0> ;
assign m_axi_awlen[20] = \<const0> ;
assign m_axi_awlen[19] = \<const0> ;
assign m_axi_awlen[18] = \<const0> ;
assign m_axi_awlen[17] = \<const0> ;
assign m_axi_awlen[16] = \<const0> ;
assign m_axi_awlen[15] = \<const0> ;
assign m_axi_awlen[14] = \<const0> ;
assign m_axi_awlen[13] = \<const0> ;
assign m_axi_awlen[12] = \<const0> ;
assign m_axi_awlen[11] = \<const0> ;
assign m_axi_awlen[10] = \<const0> ;
assign m_axi_awlen[9] = \<const0> ;
assign m_axi_awlen[8] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[5] = \<const0> ;
assign m_axi_awlock[4] = \<const0> ;
assign m_axi_awlock[3] = \<const0> ;
assign m_axi_awlock[2] = \<const0> ;
assign m_axi_awlock[1] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awprot[17:15] = \^m_axi_arprot [2:0];
assign m_axi_awprot[14:12] = \^m_axi_arprot [2:0];
assign m_axi_awprot[11:9] = \^m_axi_arprot [2:0];
assign m_axi_awprot[8:6] = \^m_axi_arprot [2:0];
assign m_axi_awprot[5:3] = \^m_axi_arprot [2:0];
assign m_axi_awprot[2:0] = \^m_axi_arprot [2:0];
assign m_axi_awqos[23] = \<const0> ;
assign m_axi_awqos[22] = \<const0> ;
assign m_axi_awqos[21] = \<const0> ;
assign m_axi_awqos[20] = \<const0> ;
assign m_axi_awqos[19] = \<const0> ;
assign m_axi_awqos[18] = \<const0> ;
assign m_axi_awqos[17] = \<const0> ;
assign m_axi_awqos[16] = \<const0> ;
assign m_axi_awqos[15] = \<const0> ;
assign m_axi_awqos[14] = \<const0> ;
assign m_axi_awqos[13] = \<const0> ;
assign m_axi_awqos[12] = \<const0> ;
assign m_axi_awqos[11] = \<const0> ;
assign m_axi_awqos[10] = \<const0> ;
assign m_axi_awqos[9] = \<const0> ;
assign m_axi_awqos[8] = \<const0> ;
assign m_axi_awqos[7] = \<const0> ;
assign m_axi_awqos[6] = \<const0> ;
assign m_axi_awqos[5] = \<const0> ;
assign m_axi_awqos[4] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[23] = \<const0> ;
assign m_axi_awregion[22] = \<const0> ;
assign m_axi_awregion[21] = \<const0> ;
assign m_axi_awregion[20] = \<const0> ;
assign m_axi_awregion[19] = \<const0> ;
assign m_axi_awregion[18] = \<const0> ;
assign m_axi_awregion[17] = \<const0> ;
assign m_axi_awregion[16] = \<const0> ;
assign m_axi_awregion[15] = \<const0> ;
assign m_axi_awregion[14] = \<const0> ;
assign m_axi_awregion[13] = \<const0> ;
assign m_axi_awregion[12] = \<const0> ;
assign m_axi_awregion[11] = \<const0> ;
assign m_axi_awregion[10] = \<const0> ;
assign m_axi_awregion[9] = \<const0> ;
assign m_axi_awregion[8] = \<const0> ;
assign m_axi_awregion[7] = \<const0> ;
assign m_axi_awregion[6] = \<const0> ;
assign m_axi_awregion[5] = \<const0> ;
assign m_axi_awregion[4] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[17] = \<const0> ;
assign m_axi_awsize[16] = \<const0> ;
assign m_axi_awsize[15] = \<const0> ;
assign m_axi_awsize[14] = \<const0> ;
assign m_axi_awsize[13] = \<const0> ;
assign m_axi_awsize[12] = \<const0> ;
assign m_axi_awsize[11] = \<const0> ;
assign m_axi_awsize[10] = \<const0> ;
assign m_axi_awsize[9] = \<const0> ;
assign m_axi_awsize[8] = \<const0> ;
assign m_axi_awsize[7] = \<const0> ;
assign m_axi_awsize[6] = \<const0> ;
assign m_axi_awsize[5] = \<const0> ;
assign m_axi_awsize[4] = \<const0> ;
assign m_axi_awsize[3] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const0> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[5] = \<const0> ;
assign m_axi_awuser[4] = \<const0> ;
assign m_axi_awuser[3] = \<const0> ;
assign m_axi_awuser[2] = \<const0> ;
assign m_axi_awuser[1] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_wdata[191:160] = s_axi_wdata;
assign m_axi_wdata[159:128] = s_axi_wdata;
assign m_axi_wdata[127:96] = s_axi_wdata;
assign m_axi_wdata[95:64] = s_axi_wdata;
assign m_axi_wdata[63:32] = s_axi_wdata;
assign m_axi_wdata[31:0] = s_axi_wdata;
assign m_axi_wid[5] = \<const0> ;
assign m_axi_wid[4] = \<const0> ;
assign m_axi_wid[3] = \<const0> ;
assign m_axi_wid[2] = \<const0> ;
assign m_axi_wid[1] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast[5] = \<const0> ;
assign m_axi_wlast[4] = \<const0> ;
assign m_axi_wlast[3] = \<const0> ;
assign m_axi_wlast[2] = \<const0> ;
assign m_axi_wlast[1] = \<const0> ;
assign m_axi_wlast[0] = \<const0> ;
assign m_axi_wstrb[23:20] = s_axi_wstrb;
assign m_axi_wstrb[19:16] = s_axi_wstrb;
assign m_axi_wstrb[15:12] = s_axi_wstrb;
assign m_axi_wstrb[11:8] = s_axi_wstrb;
assign m_axi_wstrb[7:4] = s_axi_wstrb;
assign m_axi_wstrb[3:0] = s_axi_wstrb;
assign m_axi_wuser[5] = \<const0> ;
assign m_axi_wuser[4] = \<const0> ;
assign m_axi_wuser[3] = \<const0> ;
assign m_axi_wuser[2] = \<const0> ;
assign m_axi_wuser[1] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
GND GND
(.G(\<const0> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_crossbar_sasd \gen_sasd.crossbar_sasd_0
(.Q({\^m_axi_arprot ,\^m_axi_awaddr ,\^m_axi_araddr }),
.aclk(aclk),
.aresetn(aresetn),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wready(m_axi_wready),
.m_axi_wvalid(m_axi_wvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.\s_axi_rdata[31] ({s_axi_rdata,s_axi_rresp}),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_crossbar_sasd
(Q,
\s_axi_rdata[31] ,
s_axi_bvalid,
m_axi_bready,
s_axi_wready,
m_axi_wvalid,
m_axi_awvalid,
m_axi_arvalid,
s_axi_bresp,
s_axi_awready,
s_axi_arready,
s_axi_rvalid,
m_axi_rready,
aresetn,
aclk,
s_axi_rready,
s_axi_awvalid,
s_axi_arvalid,
s_axi_bready,
s_axi_wvalid,
m_axi_bresp,
m_axi_rresp,
m_axi_rdata,
m_axi_rvalid,
m_axi_wready,
m_axi_bvalid,
m_axi_awready,
m_axi_arready,
s_axi_arprot,
s_axi_awprot,
s_axi_araddr,
s_axi_awaddr);
output [34:0]Q;
output [33:0]\s_axi_rdata[31] ;
output [0:0]s_axi_bvalid;
output [5:0]m_axi_bready;
output [0:0]s_axi_wready;
output [5:0]m_axi_wvalid;
output [5:0]m_axi_awvalid;
output [5:0]m_axi_arvalid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_awready;
output [0:0]s_axi_arready;
output [0:0]s_axi_rvalid;
output [5:0]m_axi_rready;
input aresetn;
input aclk;
input [0:0]s_axi_rready;
input [0:0]s_axi_awvalid;
input [0:0]s_axi_arvalid;
input [0:0]s_axi_bready;
input [0:0]s_axi_wvalid;
input [11:0]m_axi_bresp;
input [11:0]m_axi_rresp;
input [191:0]m_axi_rdata;
input [5:0]m_axi_rvalid;
input [5:0]m_axi_wready;
input [5:0]m_axi_bvalid;
input [5:0]m_axi_awready;
input [5:0]m_axi_arready;
input [2:0]s_axi_arprot;
input [2:0]s_axi_awprot;
input [31:0]s_axi_araddr;
input [31:0]s_axi_awaddr;
wire [34:0]Q;
wire aa_grant_rnw;
wire aa_rready;
wire aclk;
wire addr_arbiter_inst_n_10;
wire addr_arbiter_inst_n_19;
wire addr_arbiter_inst_n_27;
wire addr_arbiter_inst_n_3;
wire addr_arbiter_inst_n_34;
wire addr_arbiter_inst_n_35;
wire addr_arbiter_inst_n_36;
wire addr_arbiter_inst_n_38;
wire addr_arbiter_inst_n_4;
wire addr_arbiter_inst_n_46;
wire addr_arbiter_inst_n_47;
wire addr_arbiter_inst_n_51;
wire addr_arbiter_inst_n_52;
wire addr_arbiter_inst_n_53;
wire addr_arbiter_inst_n_6;
wire addr_arbiter_inst_n_8;
wire addr_arbiter_inst_n_89;
wire addr_arbiter_inst_n_9;
wire aresetn;
wire aresetn_d;
wire \gen_decerr.decerr_slave_inst_n_2 ;
wire \gen_decerr.decerr_slave_inst_n_3 ;
wire \gen_decerr.decerr_slave_inst_n_4 ;
wire \gen_decerr.decerr_slave_inst_n_5 ;
wire \gen_decerr.decerr_slave_inst_n_6 ;
wire \gen_decerr.decerr_slave_inst_n_7 ;
wire \gen_decerr.decerr_slave_inst_n_8 ;
wire [2:0]m_atarget_enc;
wire [6:0]m_atarget_hot;
wire [5:3]m_atarget_hot0;
wire [5:0]m_axi_arready;
wire [5:0]m_axi_arvalid;
wire [5:0]m_axi_awready;
wire [5:0]m_axi_awvalid;
wire [5:0]m_axi_bready;
wire [11:0]m_axi_bresp;
wire [5:0]m_axi_bvalid;
wire [191:0]m_axi_rdata;
wire [5:0]m_axi_rready;
wire [11:0]m_axi_rresp;
wire [5:0]m_axi_rvalid;
wire [5:0]m_axi_wready;
wire [5:0]m_axi_wvalid;
wire [1:0]m_ready_d;
wire [1:1]m_ready_d0;
wire [2:2]m_ready_d0_0;
wire [2:0]m_ready_d_1;
wire m_valid_i;
wire [6:6]mi_bvalid;
wire [6:6]mi_wready;
wire p_1_in;
wire reg_slice_r_n_2;
wire reg_slice_r_n_37;
wire reg_slice_r_n_38;
wire reg_slice_r_n_45;
wire reg_slice_r_n_46;
wire reset;
wire [31:0]s_axi_araddr;
wire [2:0]s_axi_arprot;
wire [0:0]s_axi_arready;
wire [0:0]s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [2:0]s_axi_awprot;
wire [0:0]s_axi_awready;
wire [0:0]s_axi_awvalid;
wire [0:0]s_axi_bready;
wire [1:0]s_axi_bresp;
wire \s_axi_bresp[0]_INST_0_i_1_n_0 ;
wire \s_axi_bresp[0]_INST_0_i_2_n_0 ;
wire \s_axi_bresp[1]_INST_0_i_1_n_0 ;
wire \s_axi_bresp[1]_INST_0_i_2_n_0 ;
wire [0:0]s_axi_bvalid;
wire [33:0]\s_axi_rdata[31] ;
wire [0:0]s_axi_rready;
wire [0:0]s_axi_rvalid;
wire [0:0]s_axi_wready;
wire [0:0]s_axi_wvalid;
wire splitter_ar_n_0;
wire splitter_ar_n_1;
wire splitter_aw_n_0;
wire splitter_aw_n_10;
wire splitter_aw_n_11;
wire splitter_aw_n_12;
wire splitter_aw_n_4;
wire splitter_aw_n_5;
wire splitter_aw_n_6;
wire splitter_aw_n_7;
wire splitter_aw_n_8;
wire splitter_aw_n_9;
wire sr_rvalid;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_addr_arbiter_sasd addr_arbiter_inst
(.D({addr_arbiter_inst_n_4,m_atarget_hot0[5],addr_arbiter_inst_n_6,m_atarget_hot0[3],addr_arbiter_inst_n_8,addr_arbiter_inst_n_9,addr_arbiter_inst_n_10}),
.E(p_1_in),
.Q(m_atarget_hot),
.SR(reset),
.aa_grant_rnw(aa_grant_rnw),
.aa_rready(aa_rready),
.aclk(aclk),
.aresetn_d(aresetn_d),
.\aresetn_d_reg[1] ({reg_slice_r_n_45,reg_slice_r_n_46}),
.\gen_axilite.s_axi_arready_i_reg (\gen_decerr.decerr_slave_inst_n_7 ),
.\gen_axilite.s_axi_bvalid_i_reg (addr_arbiter_inst_n_19),
.\gen_axilite.s_axi_bvalid_i_reg_0 (addr_arbiter_inst_n_27),
.\gen_axilite.s_axi_bvalid_i_reg_1 (addr_arbiter_inst_n_34),
.\gen_axilite.s_axi_bvalid_i_reg_2 (addr_arbiter_inst_n_89),
.\gen_axilite.s_axi_rvalid_i_reg (addr_arbiter_inst_n_38),
.\gen_no_arbiter.m_valid_i_reg_0 (addr_arbiter_inst_n_47),
.\m_atarget_enc_reg[0] (\gen_decerr.decerr_slave_inst_n_2 ),
.\m_atarget_enc_reg[1] (\gen_decerr.decerr_slave_inst_n_5 ),
.\m_atarget_enc_reg[1]_0 (splitter_aw_n_7),
.\m_atarget_enc_reg[1]_1 (reg_slice_r_n_38),
.\m_atarget_enc_reg[1]_2 (splitter_ar_n_0),
.\m_atarget_enc_reg[1]_3 (splitter_ar_n_1),
.\m_atarget_enc_reg[2] ({addr_arbiter_inst_n_51,addr_arbiter_inst_n_52,addr_arbiter_inst_n_53}),
.\m_atarget_enc_reg[2]_0 (\gen_decerr.decerr_slave_inst_n_3 ),
.\m_atarget_enc_reg[2]_1 (\gen_decerr.decerr_slave_inst_n_8 ),
.\m_atarget_enc_reg[2]_2 (splitter_aw_n_9),
.\m_atarget_enc_reg[2]_3 (m_atarget_enc),
.\m_axi_arprot[2] (Q),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bready(m_axi_bready),
.m_axi_wready({m_axi_wready[3],m_axi_wready[0]}),
.m_axi_wvalid(m_axi_wvalid),
.m_ready_d(m_ready_d_1),
.m_ready_d0(m_ready_d0_0),
.m_ready_d0_0(m_ready_d0),
.m_ready_d_1(m_ready_d),
.\m_ready_d_reg[0] (addr_arbiter_inst_n_3),
.\m_ready_d_reg[0]_0 (addr_arbiter_inst_n_46),
.\m_ready_d_reg[0]_1 (splitter_aw_n_0),
.\m_ready_d_reg[1] (splitter_aw_n_5),
.m_valid_i(m_valid_i),
.m_valid_i_reg(addr_arbiter_inst_n_36),
.m_valid_i_reg_0(reg_slice_r_n_2),
.mi_bvalid(mi_bvalid),
.mi_wready(mi_wready),
.s_axi_araddr(s_axi_araddr),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid),
.s_ready_i_reg(addr_arbiter_inst_n_35),
.sr_rvalid(sr_rvalid));
FDRE #(
.INIT(1'b0))
aresetn_d_reg
(.C(aclk),
.CE(1'b1),
.D(aresetn),
.Q(aresetn_d),
.R(1'b0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_decerr_slave \gen_decerr.decerr_slave_inst
(.Q(m_atarget_hot[6]),
.SR(reset),
.aa_rready(aa_rready),
.aclk(aclk),
.aresetn_d(aresetn_d),
.\gen_axilite.s_axi_awready_i_reg_0 (addr_arbiter_inst_n_89),
.\gen_no_arbiter.grant_rnw_reg (addr_arbiter_inst_n_27),
.\m_atarget_enc_reg[1] (splitter_aw_n_10),
.\m_atarget_enc_reg[1]_0 (splitter_aw_n_4),
.\m_atarget_enc_reg[1]_1 (splitter_aw_n_8),
.\m_atarget_enc_reg[2] (m_atarget_enc),
.\m_atarget_enc_reg[2]_0 (splitter_aw_n_6),
.\m_atarget_enc_reg[2]_1 (splitter_aw_n_12),
.\m_atarget_enc_reg[2]_2 (splitter_aw_n_11),
.m_axi_arready(m_axi_arready[1]),
.m_axi_awready(m_axi_awready[5:4]),
.m_axi_bvalid({m_axi_bvalid[5:4],m_axi_bvalid[0]}),
.m_axi_rvalid({m_axi_rvalid[5],m_axi_rvalid[1:0]}),
.m_axi_wready({m_axi_wready[3:2],m_axi_wready[0]}),
.\m_ready_d_reg[0] (\gen_decerr.decerr_slave_inst_n_5 ),
.\m_ready_d_reg[0]_0 (\gen_decerr.decerr_slave_inst_n_6 ),
.\m_ready_d_reg[1] (\gen_decerr.decerr_slave_inst_n_3 ),
.\m_ready_d_reg[1]_0 (\gen_decerr.decerr_slave_inst_n_4 ),
.\m_ready_d_reg[1]_1 (\gen_decerr.decerr_slave_inst_n_7 ),
.\m_ready_d_reg[1]_2 (addr_arbiter_inst_n_38),
.\m_ready_d_reg[2] (\gen_decerr.decerr_slave_inst_n_8 ),
.\m_ready_d_reg[2]_0 (addr_arbiter_inst_n_34),
.m_valid_i_reg(\gen_decerr.decerr_slave_inst_n_2 ),
.mi_bvalid(mi_bvalid),
.mi_wready(mi_wready));
FDRE #(
.INIT(1'b0))
\m_atarget_enc_reg[0]
(.C(aclk),
.CE(1'b1),
.D(addr_arbiter_inst_n_53),
.Q(m_atarget_enc[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\m_atarget_enc_reg[1]
(.C(aclk),
.CE(1'b1),
.D(addr_arbiter_inst_n_52),
.Q(m_atarget_enc[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\m_atarget_enc_reg[2]
(.C(aclk),
.CE(1'b1),
.D(addr_arbiter_inst_n_51),
.Q(m_atarget_enc[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\m_atarget_hot_reg[0]
(.C(aclk),
.CE(1'b1),
.D(addr_arbiter_inst_n_10),
.Q(m_atarget_hot[0]),
.R(reset));
FDRE #(
.INIT(1'b0))
\m_atarget_hot_reg[1]
(.C(aclk),
.CE(1'b1),
.D(addr_arbiter_inst_n_9),
.Q(m_atarget_hot[1]),
.R(reset));
FDRE #(
.INIT(1'b0))
\m_atarget_hot_reg[2]
(.C(aclk),
.CE(1'b1),
.D(addr_arbiter_inst_n_8),
.Q(m_atarget_hot[2]),
.R(reset));
FDRE #(
.INIT(1'b0))
\m_atarget_hot_reg[3]
(.C(aclk),
.CE(1'b1),
.D(m_atarget_hot0[3]),
.Q(m_atarget_hot[3]),
.R(reset));
FDRE #(
.INIT(1'b0))
\m_atarget_hot_reg[4]
(.C(aclk),
.CE(1'b1),
.D(addr_arbiter_inst_n_6),
.Q(m_atarget_hot[4]),
.R(reset));
FDRE #(
.INIT(1'b0))
\m_atarget_hot_reg[5]
(.C(aclk),
.CE(1'b1),
.D(m_atarget_hot0[5]),
.Q(m_atarget_hot[5]),
.R(reset));
FDRE #(
.INIT(1'b0))
\m_atarget_hot_reg[6]
(.C(aclk),
.CE(1'b1),
.D(addr_arbiter_inst_n_4),
.Q(m_atarget_hot[6]),
.R(reset));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice reg_slice_r
(.E(p_1_in),
.Q({\s_axi_rdata[31] ,reg_slice_r_n_37}),
.SR(reset),
.aa_grant_rnw(aa_grant_rnw),
.aa_rready(aa_rready),
.aclk(aclk),
.\aresetn_d_reg[0]_0 (addr_arbiter_inst_n_35),
.\aresetn_d_reg[1]_0 (addr_arbiter_inst_n_36),
.\m_atarget_enc_reg[2] (m_atarget_enc),
.\m_atarget_hot_reg[5] (m_atarget_hot[5:0]),
.m_axi_rdata(m_axi_rdata),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_rvalid(m_axi_rvalid[4:2]),
.m_ready_d(m_ready_d[0]),
.\m_ready_d_reg[1] (reg_slice_r_n_2),
.m_valid_i(m_valid_i),
.m_valid_i_reg_0(reg_slice_r_n_38),
.m_valid_i_reg_1({reg_slice_r_n_45,reg_slice_r_n_46}),
.s_axi_rready(s_axi_rready),
.sr_rvalid(sr_rvalid));
LUT2 #(
.INIT(4'hE))
\s_axi_bresp[0]_INST_0
(.I0(\s_axi_bresp[0]_INST_0_i_1_n_0 ),
.I1(\s_axi_bresp[0]_INST_0_i_2_n_0 ),
.O(s_axi_bresp[0]));
LUT6 #(
.INIT(64'h0F00FC0A0F000C0A))
\s_axi_bresp[0]_INST_0_i_1
(.I0(m_axi_bresp[0]),
.I1(m_axi_bresp[8]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[2]),
.I4(m_atarget_enc[1]),
.I5(m_axi_bresp[10]),
.O(\s_axi_bresp[0]_INST_0_i_1_n_0 ));
LUT6 #(
.INIT(64'h0F0A0C00000A0C00))
\s_axi_bresp[0]_INST_0_i_2
(.I0(m_axi_bresp[4]),
.I1(m_axi_bresp[2]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.I5(m_axi_bresp[6]),
.O(\s_axi_bresp[0]_INST_0_i_2_n_0 ));
LUT2 #(
.INIT(4'hE))
\s_axi_bresp[1]_INST_0
(.I0(\s_axi_bresp[1]_INST_0_i_1_n_0 ),
.I1(\s_axi_bresp[1]_INST_0_i_2_n_0 ),
.O(s_axi_bresp[1]));
LUT6 #(
.INIT(64'h0F00FC0A0F000C0A))
\s_axi_bresp[1]_INST_0_i_1
(.I0(m_axi_bresp[1]),
.I1(m_axi_bresp[9]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[2]),
.I4(m_atarget_enc[1]),
.I5(m_axi_bresp[11]),
.O(\s_axi_bresp[1]_INST_0_i_1_n_0 ));
LUT6 #(
.INIT(64'h0F0A0C00000A0C00))
\s_axi_bresp[1]_INST_0_i_2
(.I0(m_axi_bresp[5]),
.I1(m_axi_bresp[3]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.I5(m_axi_bresp[7]),
.O(\s_axi_bresp[1]_INST_0_i_2_n_0 ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_splitter__parameterized0 splitter_ar
(.Q(m_atarget_enc),
.aclk(aclk),
.aresetn_d(aresetn_d),
.aresetn_d_reg(addr_arbiter_inst_n_3),
.\gen_no_arbiter.grant_rnw_reg (addr_arbiter_inst_n_46),
.m_axi_arready({m_axi_arready[5:2],m_axi_arready[0]}),
.\m_payload_i_reg[0] (reg_slice_r_n_37),
.m_ready_d(m_ready_d),
.m_ready_d0(m_ready_d0),
.\m_ready_d_reg[1]_0 (splitter_ar_n_0),
.\m_ready_d_reg[1]_1 (splitter_ar_n_1),
.m_valid_i_reg(reg_slice_r_n_2),
.s_axi_rready(s_axi_rready),
.sr_rvalid(sr_rvalid));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_splitter splitter_aw
(.Q(m_atarget_enc),
.aclk(aclk),
.aresetn_d(aresetn_d),
.\gen_axilite.s_axi_awready_i_reg (\gen_decerr.decerr_slave_inst_n_4 ),
.\gen_axilite.s_axi_bvalid_i_reg (\gen_decerr.decerr_slave_inst_n_6 ),
.\gen_no_arbiter.grant_rnw_reg (addr_arbiter_inst_n_27),
.\gen_no_arbiter.grant_rnw_reg_0 (addr_arbiter_inst_n_19),
.\gen_no_arbiter.m_valid_i_reg (splitter_aw_n_5),
.\m_atarget_enc_reg[1] (\gen_decerr.decerr_slave_inst_n_5 ),
.\m_atarget_enc_reg[2] (\gen_decerr.decerr_slave_inst_n_3 ),
.\m_atarget_enc_reg[2]_0 (addr_arbiter_inst_n_47),
.m_axi_awready(m_axi_awready[3:0]),
.m_axi_bvalid(m_axi_bvalid[5:1]),
.m_axi_wready({m_axi_wready[5:4],m_axi_wready[1]}),
.m_ready_d(m_ready_d_1),
.m_ready_d0(m_ready_d0_0),
.\m_ready_d_reg[0]_0 (splitter_aw_n_0),
.\m_ready_d_reg[0]_1 (splitter_aw_n_4),
.\m_ready_d_reg[0]_2 (splitter_aw_n_8),
.\m_ready_d_reg[0]_3 (splitter_aw_n_11),
.\m_ready_d_reg[1]_0 (splitter_aw_n_6),
.\m_ready_d_reg[1]_1 (splitter_aw_n_10),
.\m_ready_d_reg[1]_2 (splitter_aw_n_12),
.\m_ready_d_reg[2]_0 (splitter_aw_n_7),
.\m_ready_d_reg[2]_1 (splitter_aw_n_9));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_decerr_slave
(mi_bvalid,
mi_wready,
m_valid_i_reg,
\m_ready_d_reg[1] ,
\m_ready_d_reg[1]_0 ,
\m_ready_d_reg[0] ,
\m_ready_d_reg[0]_0 ,
\m_ready_d_reg[1]_1 ,
\m_ready_d_reg[2] ,
SR,
\gen_axilite.s_axi_awready_i_reg_0 ,
aclk,
Q,
\m_ready_d_reg[1]_2 ,
aresetn_d,
m_axi_rvalid,
\m_atarget_enc_reg[2] ,
\m_atarget_enc_reg[2]_0 ,
\m_atarget_enc_reg[1] ,
m_axi_wready,
\m_atarget_enc_reg[2]_1 ,
\m_atarget_enc_reg[1]_0 ,
\m_atarget_enc_reg[1]_1 ,
m_axi_bvalid,
\m_atarget_enc_reg[2]_2 ,
m_axi_arready,
m_axi_awready,
aa_rready,
\gen_no_arbiter.grant_rnw_reg ,
\m_ready_d_reg[2]_0 );
output [0:0]mi_bvalid;
output [0:0]mi_wready;
output m_valid_i_reg;
output \m_ready_d_reg[1] ;
output \m_ready_d_reg[1]_0 ;
output \m_ready_d_reg[0] ;
output \m_ready_d_reg[0]_0 ;
output \m_ready_d_reg[1]_1 ;
output \m_ready_d_reg[2] ;
input [0:0]SR;
input \gen_axilite.s_axi_awready_i_reg_0 ;
input aclk;
input [0:0]Q;
input \m_ready_d_reg[1]_2 ;
input aresetn_d;
input [2:0]m_axi_rvalid;
input [2:0]\m_atarget_enc_reg[2] ;
input \m_atarget_enc_reg[2]_0 ;
input \m_atarget_enc_reg[1] ;
input [2:0]m_axi_wready;
input \m_atarget_enc_reg[2]_1 ;
input \m_atarget_enc_reg[1]_0 ;
input \m_atarget_enc_reg[1]_1 ;
input [2:0]m_axi_bvalid;
input \m_atarget_enc_reg[2]_2 ;
input [0:0]m_axi_arready;
input [1:0]m_axi_awready;
input aa_rready;
input \gen_no_arbiter.grant_rnw_reg ;
input \m_ready_d_reg[2]_0 ;
wire [0:0]Q;
wire [0:0]SR;
wire aa_rready;
wire aclk;
wire aresetn_d;
wire \gen_axilite.s_axi_arready_i_i_1_n_0 ;
wire \gen_axilite.s_axi_awready_i_i_1_n_0 ;
wire \gen_axilite.s_axi_awready_i_reg_0 ;
wire \gen_axilite.s_axi_rvalid_i_i_1_n_0 ;
wire \gen_no_arbiter.grant_rnw_reg ;
wire \m_atarget_enc_reg[1] ;
wire \m_atarget_enc_reg[1]_0 ;
wire \m_atarget_enc_reg[1]_1 ;
wire [2:0]\m_atarget_enc_reg[2] ;
wire \m_atarget_enc_reg[2]_0 ;
wire \m_atarget_enc_reg[2]_1 ;
wire \m_atarget_enc_reg[2]_2 ;
wire [0:0]m_axi_arready;
wire [1:0]m_axi_awready;
wire [2:0]m_axi_bvalid;
wire [2:0]m_axi_rvalid;
wire [2:0]m_axi_wready;
wire \m_ready_d_reg[0] ;
wire \m_ready_d_reg[0]_0 ;
wire \m_ready_d_reg[1] ;
wire \m_ready_d_reg[1]_0 ;
wire \m_ready_d_reg[1]_1 ;
wire \m_ready_d_reg[1]_2 ;
wire \m_ready_d_reg[2] ;
wire \m_ready_d_reg[2]_0 ;
wire m_valid_i_i_6_n_0;
wire m_valid_i_reg;
wire [6:6]mi_arready;
wire [0:0]mi_bvalid;
wire [6:6]mi_rvalid;
wire [0:0]mi_wready;
LUT5 #(
.INIT(32'hF07F0000))
\gen_axilite.s_axi_arready_i_i_1
(.I0(Q),
.I1(\m_ready_d_reg[1]_2 ),
.I2(mi_arready),
.I3(mi_rvalid),
.I4(aresetn_d),
.O(\gen_axilite.s_axi_arready_i_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_axilite.s_axi_arready_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_axilite.s_axi_arready_i_i_1_n_0 ),
.Q(mi_arready),
.R(1'b0));
LUT5 #(
.INIT(32'hBFFF4000))
\gen_axilite.s_axi_awready_i_i_1
(.I0(mi_bvalid),
.I1(\gen_no_arbiter.grant_rnw_reg ),
.I2(\m_ready_d_reg[2]_0 ),
.I3(Q),
.I4(mi_wready),
.O(\gen_axilite.s_axi_awready_i_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_axilite.s_axi_awready_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_axilite.s_axi_awready_i_i_1_n_0 ),
.Q(mi_wready),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_axilite.s_axi_bvalid_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_axilite.s_axi_awready_i_reg_0 ),
.Q(mi_bvalid),
.R(SR));
LUT5 #(
.INIT(32'h0FFF8800))
\gen_axilite.s_axi_rvalid_i_i_1
(.I0(mi_arready),
.I1(\m_ready_d_reg[1]_2 ),
.I2(aa_rready),
.I3(Q),
.I4(mi_rvalid),
.O(\gen_axilite.s_axi_rvalid_i_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_axilite.s_axi_rvalid_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_axilite.s_axi_rvalid_i_i_1_n_0 ),
.Q(mi_rvalid),
.R(SR));
LUT5 #(
.INIT(32'h08300800))
\m_ready_d[1]_i_5
(.I0(mi_arready),
.I1(\m_atarget_enc_reg[2] [1]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [2]),
.I4(m_axi_arready),
.O(\m_ready_d_reg[1]_1 ));
LUT6 #(
.INIT(64'hFF0F3F5FFFFF3F5F))
\m_ready_d[2]_i_4
(.I0(m_axi_awready[0]),
.I1(m_axi_awready[1]),
.I2(\m_atarget_enc_reg[2] [2]),
.I3(\m_atarget_enc_reg[2] [0]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(mi_wready),
.O(\m_ready_d_reg[2] ));
LUT6 #(
.INIT(64'hFFFFFFFF08030800))
m_valid_i_i_4
(.I0(m_axi_rvalid[2]),
.I1(\m_atarget_enc_reg[2] [0]),
.I2(\m_atarget_enc_reg[2] [1]),
.I3(\m_atarget_enc_reg[2] [2]),
.I4(m_axi_rvalid[0]),
.I5(m_valid_i_i_6_n_0),
.O(m_valid_i_reg));
LUT5 #(
.INIT(32'h08300800))
m_valid_i_i_6
(.I0(mi_rvalid),
.I1(\m_atarget_enc_reg[2] [1]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [2]),
.I4(m_axi_rvalid[1]),
.O(m_valid_i_i_6_n_0));
LUT6 #(
.INIT(64'h000000008A008A8A))
\s_axi_bvalid[0]_INST_0_i_1
(.I0(\m_atarget_enc_reg[1]_0 ),
.I1(\m_atarget_enc_reg[1]_1 ),
.I2(m_axi_bvalid[1]),
.I3(\m_atarget_enc_reg[2]_2 ),
.I4(m_axi_bvalid[2]),
.I5(\m_ready_d_reg[0]_0 ),
.O(\m_ready_d_reg[0] ));
LUT5 #(
.INIT(32'h00830080))
\s_axi_bvalid[0]_INST_0_i_5
(.I0(mi_bvalid),
.I1(\m_atarget_enc_reg[2] [1]),
.I2(\m_atarget_enc_reg[2] [2]),
.I3(\m_atarget_enc_reg[2] [0]),
.I4(m_axi_bvalid[0]),
.O(\m_ready_d_reg[0]_0 ));
LUT6 #(
.INIT(64'h000000008A008A8A))
\s_axi_wready[0]_INST_0_i_1
(.I0(\m_atarget_enc_reg[2]_0 ),
.I1(\m_atarget_enc_reg[1] ),
.I2(m_axi_wready[0]),
.I3(\m_atarget_enc_reg[2]_1 ),
.I4(m_axi_wready[2]),
.I5(\m_ready_d_reg[1]_0 ),
.O(\m_ready_d_reg[1] ));
LUT5 #(
.INIT(32'h0B000800))
\s_axi_wready[0]_INST_0_i_5
(.I0(mi_wready),
.I1(\m_atarget_enc_reg[2] [2]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [1]),
.I4(m_axi_wready[1]),
.O(\m_ready_d_reg[1]_0 ));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_splitter
(\m_ready_d_reg[0]_0 ,
m_ready_d,
\m_ready_d_reg[0]_1 ,
\gen_no_arbiter.m_valid_i_reg ,
\m_ready_d_reg[1]_0 ,
\m_ready_d_reg[2]_0 ,
\m_ready_d_reg[0]_2 ,
\m_ready_d_reg[2]_1 ,
\m_ready_d_reg[1]_1 ,
\m_ready_d_reg[0]_3 ,
\m_ready_d_reg[1]_2 ,
\m_atarget_enc_reg[2] ,
\gen_no_arbiter.grant_rnw_reg ,
m_ready_d0,
\gen_axilite.s_axi_bvalid_i_reg ,
\gen_no_arbiter.grant_rnw_reg_0 ,
\m_atarget_enc_reg[2]_0 ,
\gen_axilite.s_axi_awready_i_reg ,
m_axi_wready,
Q,
m_axi_bvalid,
m_axi_awready,
aresetn_d,
\m_atarget_enc_reg[1] ,
aclk);
output \m_ready_d_reg[0]_0 ;
output [2:0]m_ready_d;
output \m_ready_d_reg[0]_1 ;
output \gen_no_arbiter.m_valid_i_reg ;
output \m_ready_d_reg[1]_0 ;
output \m_ready_d_reg[2]_0 ;
output \m_ready_d_reg[0]_2 ;
output \m_ready_d_reg[2]_1 ;
output \m_ready_d_reg[1]_1 ;
output \m_ready_d_reg[0]_3 ;
output \m_ready_d_reg[1]_2 ;
input \m_atarget_enc_reg[2] ;
input \gen_no_arbiter.grant_rnw_reg ;
input [0:0]m_ready_d0;
input \gen_axilite.s_axi_bvalid_i_reg ;
input \gen_no_arbiter.grant_rnw_reg_0 ;
input \m_atarget_enc_reg[2]_0 ;
input \gen_axilite.s_axi_awready_i_reg ;
input [2:0]m_axi_wready;
input [2:0]Q;
input [4:0]m_axi_bvalid;
input [3:0]m_axi_awready;
input aresetn_d;
input \m_atarget_enc_reg[1] ;
input aclk;
wire [2:0]Q;
wire aclk;
wire aresetn_d;
wire \gen_axilite.s_axi_awready_i_reg ;
wire \gen_axilite.s_axi_bvalid_i_reg ;
wire \gen_no_arbiter.grant_rnw_reg ;
wire \gen_no_arbiter.grant_rnw_reg_0 ;
wire \gen_no_arbiter.m_valid_i_reg ;
wire \m_atarget_enc_reg[1] ;
wire \m_atarget_enc_reg[2] ;
wire \m_atarget_enc_reg[2]_0 ;
wire [3:0]m_axi_awready;
wire [4:0]m_axi_bvalid;
wire [2:0]m_axi_wready;
wire [2:0]m_ready_d;
wire [0:0]m_ready_d0;
wire \m_ready_d[0]_i_1_n_0 ;
wire \m_ready_d[1]_i_1_n_0 ;
wire \m_ready_d[2]_i_1_n_0 ;
wire \m_ready_d[2]_i_3_n_0 ;
wire \m_ready_d[2]_i_8_n_0 ;
wire \m_ready_d_reg[0]_0 ;
wire \m_ready_d_reg[0]_1 ;
wire \m_ready_d_reg[0]_2 ;
wire \m_ready_d_reg[0]_3 ;
wire \m_ready_d_reg[1]_0 ;
wire \m_ready_d_reg[1]_1 ;
wire \m_ready_d_reg[1]_2 ;
wire \m_ready_d_reg[2]_0 ;
wire \m_ready_d_reg[2]_1 ;
LUT5 #(
.INIT(32'h00045555))
\gen_no_arbiter.m_grant_hot_i[0]_i_3
(.I0(m_ready_d[1]),
.I1(\m_ready_d_reg[1]_0 ),
.I2(\m_atarget_enc_reg[2]_0 ),
.I3(\gen_axilite.s_axi_awready_i_reg ),
.I4(\gen_no_arbiter.grant_rnw_reg ),
.O(\gen_no_arbiter.m_valid_i_reg ));
LUT5 #(
.INIT(32'hBA000000))
\m_ready_d[0]_i_1
(.I0(m_ready_d[0]),
.I1(\m_atarget_enc_reg[1] ),
.I2(\gen_no_arbiter.grant_rnw_reg_0 ),
.I3(\m_ready_d[2]_i_3_n_0 ),
.I4(aresetn_d),
.O(\m_ready_d[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'hBA000000))
\m_ready_d[1]_i_1
(.I0(m_ready_d[1]),
.I1(\m_atarget_enc_reg[2] ),
.I2(\gen_no_arbiter.grant_rnw_reg ),
.I3(\m_ready_d[2]_i_3_n_0 ),
.I4(aresetn_d),
.O(\m_ready_d[1]_i_1_n_0 ));
LUT3 #(
.INIT(8'h80))
\m_ready_d[2]_i_1
(.I0(m_ready_d0),
.I1(\m_ready_d[2]_i_3_n_0 ),
.I2(aresetn_d),
.O(\m_ready_d[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'hBABBFFFF))
\m_ready_d[2]_i_3
(.I0(\m_ready_d_reg[0]_0 ),
.I1(m_ready_d[1]),
.I2(\m_atarget_enc_reg[2] ),
.I3(\gen_no_arbiter.grant_rnw_reg ),
.I4(m_ready_d0),
.O(\m_ready_d[2]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT5 #(
.INIT(32'h23002000))
\m_ready_d[2]_i_5
(.I0(m_axi_awready[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(m_axi_awready[2]),
.O(\m_ready_d_reg[2]_1 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT5 #(
.INIT(32'h00320002))
\m_ready_d[2]_i_6
(.I0(m_axi_awready[0]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(m_axi_awready[1]),
.O(\m_ready_d_reg[2]_0 ));
LUT5 #(
.INIT(32'h00045555))
\m_ready_d[2]_i_7
(.I0(m_ready_d[0]),
.I1(\m_ready_d_reg[0]_1 ),
.I2(\m_ready_d[2]_i_8_n_0 ),
.I3(\gen_axilite.s_axi_bvalid_i_reg ),
.I4(\gen_no_arbiter.grant_rnw_reg_0 ),
.O(\m_ready_d_reg[0]_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT5 #(
.INIT(32'h0C080008))
\m_ready_d[2]_i_8
(.I0(m_axi_bvalid[3]),
.I1(Q[2]),
.I2(Q[1]),
.I3(Q[0]),
.I4(m_axi_bvalid[4]),
.O(\m_ready_d[2]_i_8_n_0 ));
FDRE #(
.INIT(1'b0))
\m_ready_d_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[0]_i_1_n_0 ),
.Q(m_ready_d[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\m_ready_d_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[1]_i_1_n_0 ),
.Q(m_ready_d[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\m_ready_d_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[2]_i_1_n_0 ),
.Q(m_ready_d[2]),
.R(1'b0));
LUT6 #(
.INIT(64'hFFFF053FFFFFF53F))
\s_axi_bvalid[0]_INST_0_i_2
(.I0(m_axi_bvalid[0]),
.I1(m_axi_bvalid[1]),
.I2(Q[1]),
.I3(Q[0]),
.I4(Q[2]),
.I5(m_axi_bvalid[2]),
.O(\m_ready_d_reg[0]_1 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hFB))
\s_axi_bvalid[0]_INST_0_i_3
(.I0(Q[1]),
.I1(Q[2]),
.I2(Q[0]),
.O(\m_ready_d_reg[0]_2 ));
LUT3 #(
.INIT(8'hDF))
\s_axi_bvalid[0]_INST_0_i_4
(.I0(Q[2]),
.I1(Q[1]),
.I2(Q[0]),
.O(\m_ready_d_reg[0]_3 ));
LUT6 #(
.INIT(64'hFFFF530FFFFF53FF))
\s_axi_wready[0]_INST_0_i_2
(.I0(m_axi_wready[2]),
.I1(m_axi_wready[0]),
.I2(Q[2]),
.I3(Q[0]),
.I4(Q[1]),
.I5(m_axi_wready[1]),
.O(\m_ready_d_reg[1]_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hFE))
\s_axi_wready[0]_INST_0_i_3
(.I0(Q[1]),
.I1(Q[2]),
.I2(Q[0]),
.O(\m_ready_d_reg[1]_1 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hBF))
\s_axi_wready[0]_INST_0_i_4
(.I0(Q[2]),
.I1(Q[1]),
.I2(Q[0]),
.O(\m_ready_d_reg[1]_2 ));
endmodule
(* ORIG_REF_NAME = "axi_crossbar_v2_1_15_splitter" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_splitter__parameterized0
(\m_ready_d_reg[1]_0 ,
\m_ready_d_reg[1]_1 ,
m_ready_d,
m_axi_arready,
Q,
aresetn_d,
m_ready_d0,
m_valid_i_reg,
sr_rvalid,
\m_payload_i_reg[0] ,
s_axi_rready,
\gen_no_arbiter.grant_rnw_reg ,
aresetn_d_reg,
aclk);
output \m_ready_d_reg[1]_0 ;
output \m_ready_d_reg[1]_1 ;
output [1:0]m_ready_d;
input [4:0]m_axi_arready;
input [2:0]Q;
input aresetn_d;
input [0:0]m_ready_d0;
input m_valid_i_reg;
input sr_rvalid;
input [0:0]\m_payload_i_reg[0] ;
input [0:0]s_axi_rready;
input \gen_no_arbiter.grant_rnw_reg ;
input aresetn_d_reg;
input aclk;
wire [2:0]Q;
wire aclk;
wire aresetn_d;
wire aresetn_d_reg;
wire \gen_no_arbiter.grant_rnw_reg ;
wire [4:0]m_axi_arready;
wire [0:0]\m_payload_i_reg[0] ;
wire [1:0]m_ready_d;
wire [0:0]m_ready_d0;
wire \m_ready_d[0]_i_1_n_0 ;
wire \m_ready_d[1]_i_1_n_0 ;
wire \m_ready_d_reg[1]_0 ;
wire \m_ready_d_reg[1]_1 ;
wire m_valid_i_reg;
wire [0:0]s_axi_rready;
wire sr_rvalid;
LUT6 #(
.INIT(64'h00000000FFFF0080))
\m_ready_d[0]_i_1
(.I0(sr_rvalid),
.I1(\m_payload_i_reg[0] ),
.I2(s_axi_rready),
.I3(\gen_no_arbiter.grant_rnw_reg ),
.I4(m_ready_d[0]),
.I5(aresetn_d_reg),
.O(\m_ready_d[0]_i_1_n_0 ));
LUT3 #(
.INIT(8'h80))
\m_ready_d[1]_i_1
(.I0(aresetn_d),
.I1(m_ready_d0),
.I2(m_valid_i_reg),
.O(\m_ready_d[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF0FF5F3FFFFF5F3F))
\m_ready_d[1]_i_4
(.I0(m_axi_arready[2]),
.I1(m_axi_arready[1]),
.I2(Q[1]),
.I3(Q[0]),
.I4(Q[2]),
.I5(m_axi_arready[4]),
.O(\m_ready_d_reg[1]_1 ));
LUT5 #(
.INIT(32'h00230020))
\m_ready_d[1]_i_6
(.I0(m_axi_arready[3]),
.I1(Q[1]),
.I2(Q[2]),
.I3(Q[0]),
.I4(m_axi_arready[0]),
.O(\m_ready_d_reg[1]_0 ));
FDRE #(
.INIT(1'b0))
\m_ready_d_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[0]_i_1_n_0 ),
.Q(m_ready_d[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\m_ready_d_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[1]_i_1_n_0 ),
.Q(m_ready_d[1]),
.R(1'b0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice
(sr_rvalid,
aa_rready,
\m_ready_d_reg[1] ,
Q,
m_valid_i_reg_0,
m_axi_rready,
m_valid_i_reg_1,
\aresetn_d_reg[1]_0 ,
aclk,
\aresetn_d_reg[0]_0 ,
s_axi_rready,
aa_grant_rnw,
m_valid_i,
m_ready_d,
m_axi_rresp,
\m_atarget_enc_reg[2] ,
m_axi_rdata,
m_axi_rvalid,
\m_atarget_hot_reg[5] ,
SR,
E);
output sr_rvalid;
output aa_rready;
output \m_ready_d_reg[1] ;
output [34:0]Q;
output m_valid_i_reg_0;
output [5:0]m_axi_rready;
output [1:0]m_valid_i_reg_1;
input \aresetn_d_reg[1]_0 ;
input aclk;
input \aresetn_d_reg[0]_0 ;
input [0:0]s_axi_rready;
input aa_grant_rnw;
input m_valid_i;
input [0:0]m_ready_d;
input [11:0]m_axi_rresp;
input [2:0]\m_atarget_enc_reg[2] ;
input [191:0]m_axi_rdata;
input [2:0]m_axi_rvalid;
input [5:0]\m_atarget_hot_reg[5] ;
input [0:0]SR;
input [0:0]E;
wire [0:0]E;
wire [34:0]Q;
wire [0:0]SR;
wire aa_grant_rnw;
wire aa_rready;
wire aclk;
wire \aresetn_d_reg[0]_0 ;
wire \aresetn_d_reg[1]_0 ;
wire [2:0]\m_atarget_enc_reg[2] ;
wire [5:0]\m_atarget_hot_reg[5] ;
wire [191:0]m_axi_rdata;
wire [5:0]m_axi_rready;
wire [11:0]m_axi_rresp;
wire [2:0]m_axi_rvalid;
wire \m_payload_i[10]_i_2_n_0 ;
wire \m_payload_i[10]_i_3_n_0 ;
wire \m_payload_i[11]_i_2_n_0 ;
wire \m_payload_i[11]_i_3_n_0 ;
wire \m_payload_i[12]_i_2_n_0 ;
wire \m_payload_i[12]_i_3_n_0 ;
wire \m_payload_i[13]_i_2_n_0 ;
wire \m_payload_i[13]_i_3_n_0 ;
wire \m_payload_i[14]_i_2_n_0 ;
wire \m_payload_i[14]_i_3_n_0 ;
wire \m_payload_i[15]_i_2_n_0 ;
wire \m_payload_i[15]_i_3_n_0 ;
wire \m_payload_i[16]_i_2_n_0 ;
wire \m_payload_i[16]_i_3_n_0 ;
wire \m_payload_i[17]_i_2_n_0 ;
wire \m_payload_i[17]_i_3_n_0 ;
wire \m_payload_i[18]_i_2_n_0 ;
wire \m_payload_i[18]_i_3_n_0 ;
wire \m_payload_i[19]_i_2_n_0 ;
wire \m_payload_i[19]_i_3_n_0 ;
wire \m_payload_i[1]_i_2_n_0 ;
wire \m_payload_i[1]_i_3_n_0 ;
wire \m_payload_i[1]_i_4_n_0 ;
wire \m_payload_i[20]_i_2_n_0 ;
wire \m_payload_i[20]_i_3_n_0 ;
wire \m_payload_i[21]_i_2_n_0 ;
wire \m_payload_i[21]_i_3_n_0 ;
wire \m_payload_i[22]_i_2_n_0 ;
wire \m_payload_i[22]_i_3_n_0 ;
wire \m_payload_i[23]_i_2_n_0 ;
wire \m_payload_i[23]_i_3_n_0 ;
wire \m_payload_i[24]_i_2_n_0 ;
wire \m_payload_i[24]_i_3_n_0 ;
wire \m_payload_i[25]_i_2_n_0 ;
wire \m_payload_i[25]_i_3_n_0 ;
wire \m_payload_i[26]_i_2_n_0 ;
wire \m_payload_i[26]_i_3_n_0 ;
wire \m_payload_i[27]_i_2_n_0 ;
wire \m_payload_i[27]_i_3_n_0 ;
wire \m_payload_i[28]_i_2_n_0 ;
wire \m_payload_i[28]_i_3_n_0 ;
wire \m_payload_i[29]_i_2_n_0 ;
wire \m_payload_i[29]_i_3_n_0 ;
wire \m_payload_i[2]_i_2_n_0 ;
wire \m_payload_i[2]_i_3_n_0 ;
wire \m_payload_i[2]_i_4_n_0 ;
wire \m_payload_i[30]_i_2_n_0 ;
wire \m_payload_i[30]_i_3_n_0 ;
wire \m_payload_i[31]_i_2_n_0 ;
wire \m_payload_i[31]_i_3_n_0 ;
wire \m_payload_i[32]_i_2_n_0 ;
wire \m_payload_i[32]_i_3_n_0 ;
wire \m_payload_i[33]_i_2_n_0 ;
wire \m_payload_i[33]_i_3_n_0 ;
wire \m_payload_i[34]_i_3_n_0 ;
wire \m_payload_i[34]_i_4_n_0 ;
wire \m_payload_i[3]_i_2_n_0 ;
wire \m_payload_i[3]_i_3_n_0 ;
wire \m_payload_i[4]_i_2_n_0 ;
wire \m_payload_i[4]_i_3_n_0 ;
wire \m_payload_i[5]_i_2_n_0 ;
wire \m_payload_i[5]_i_3_n_0 ;
wire \m_payload_i[6]_i_2_n_0 ;
wire \m_payload_i[6]_i_3_n_0 ;
wire \m_payload_i[7]_i_2_n_0 ;
wire \m_payload_i[7]_i_3_n_0 ;
wire \m_payload_i[8]_i_2_n_0 ;
wire \m_payload_i[8]_i_3_n_0 ;
wire \m_payload_i[9]_i_2_n_0 ;
wire \m_payload_i[9]_i_3_n_0 ;
wire [0:0]m_ready_d;
wire \m_ready_d_reg[1] ;
wire m_valid_i;
wire m_valid_i_reg_0;
wire [1:0]m_valid_i_reg_1;
wire [0:0]s_axi_rready;
wire [34:0]skid_buffer;
wire \skid_buffer[10]_i_1_n_0 ;
wire \skid_buffer[11]_i_1_n_0 ;
wire \skid_buffer[12]_i_1_n_0 ;
wire \skid_buffer[13]_i_1_n_0 ;
wire \skid_buffer[14]_i_1_n_0 ;
wire \skid_buffer[15]_i_1_n_0 ;
wire \skid_buffer[16]_i_1_n_0 ;
wire \skid_buffer[17]_i_1_n_0 ;
wire \skid_buffer[18]_i_1_n_0 ;
wire \skid_buffer[19]_i_1_n_0 ;
wire \skid_buffer[20]_i_1_n_0 ;
wire \skid_buffer[21]_i_1_n_0 ;
wire \skid_buffer[22]_i_1_n_0 ;
wire \skid_buffer[23]_i_1_n_0 ;
wire \skid_buffer[24]_i_1_n_0 ;
wire \skid_buffer[25]_i_1_n_0 ;
wire \skid_buffer[26]_i_1_n_0 ;
wire \skid_buffer[27]_i_1_n_0 ;
wire \skid_buffer[28]_i_1_n_0 ;
wire \skid_buffer[29]_i_1_n_0 ;
wire \skid_buffer[30]_i_1_n_0 ;
wire \skid_buffer[31]_i_1_n_0 ;
wire \skid_buffer[32]_i_1_n_0 ;
wire \skid_buffer[33]_i_1_n_0 ;
wire \skid_buffer[34]_i_1_n_0 ;
wire \skid_buffer[3]_i_1_n_0 ;
wire \skid_buffer[4]_i_1_n_0 ;
wire \skid_buffer[5]_i_1_n_0 ;
wire \skid_buffer[6]_i_1_n_0 ;
wire \skid_buffer[7]_i_1_n_0 ;
wire \skid_buffer[8]_i_1_n_0 ;
wire \skid_buffer[9]_i_1_n_0 ;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
wire sr_rvalid;
FDRE #(
.INIT(1'b0))
\aresetn_d_reg[0]
(.C(aclk),
.CE(1'b1),
.D(1'b1),
.Q(m_valid_i_reg_1[0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\aresetn_d_reg[1]
(.C(aclk),
.CE(1'b1),
.D(m_valid_i_reg_1[0]),
.Q(m_valid_i_reg_1[1]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT2 #(
.INIT(4'h8))
\m_axi_rready[0]_INST_0
(.I0(aa_rready),
.I1(\m_atarget_hot_reg[5] [0]),
.O(m_axi_rready[0]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT2 #(
.INIT(4'h8))
\m_axi_rready[1]_INST_0
(.I0(aa_rready),
.I1(\m_atarget_hot_reg[5] [1]),
.O(m_axi_rready[1]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT2 #(
.INIT(4'h8))
\m_axi_rready[2]_INST_0
(.I0(aa_rready),
.I1(\m_atarget_hot_reg[5] [2]),
.O(m_axi_rready[2]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT2 #(
.INIT(4'h8))
\m_axi_rready[3]_INST_0
(.I0(aa_rready),
.I1(\m_atarget_hot_reg[5] [3]),
.O(m_axi_rready[3]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT2 #(
.INIT(4'h8))
\m_axi_rready[4]_INST_0
(.I0(aa_rready),
.I1(\m_atarget_hot_reg[5] [4]),
.O(m_axi_rready[4]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT2 #(
.INIT(4'h8))
\m_axi_rready[5]_INST_0
(.I0(aa_rready),
.I1(\m_atarget_hot_reg[5] [5]),
.O(m_axi_rready[5]));
LUT4 #(
.INIT(16'hEFE0))
\m_payload_i[10]_i_1
(.I0(\m_payload_i[10]_i_2_n_0 ),
.I1(\m_payload_i[10]_i_3_n_0 ),
.I2(aa_rready),
.I3(\skid_buffer_reg_n_0_[10] ),
.O(skid_buffer[10]));
LUT6 #(
.INIT(64'h00CA000F00CA0000))
\m_payload_i[10]_i_2
(.I0(m_axi_rdata[135]),
.I1(m_axi_rdata[167]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [1]),
.I4(\m_atarget_enc_reg[2] [2]),
.I5(m_axi_rdata[7]),
.O(\m_payload_i[10]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000CAF00000CA00))
\m_payload_i[10]_i_3
(.I0(m_axi_rdata[71]),
.I1(m_axi_rdata[103]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [1]),
.I4(\m_atarget_enc_reg[2] [2]),
.I5(m_axi_rdata[39]),
.O(\m_payload_i[10]_i_3_n_0 ));
LUT4 #(
.INIT(16'hEFE0))
\m_payload_i[11]_i_1
(.I0(\m_payload_i[11]_i_2_n_0 ),
.I1(\m_payload_i[11]_i_3_n_0 ),
.I2(aa_rready),
.I3(\skid_buffer_reg_n_0_[11] ),
.O(skid_buffer[11]));
LUT6 #(
.INIT(64'h00CF000A00C0000A))
\m_payload_i[11]_i_2
(.I0(m_axi_rdata[8]),
.I1(m_axi_rdata[168]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [1]),
.I4(\m_atarget_enc_reg[2] [2]),
.I5(m_axi_rdata[136]),
.O(\m_payload_i[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0F0A0C00000A0C00))
\m_payload_i[11]_i_3
(.I0(m_axi_rdata[72]),
.I1(m_axi_rdata[40]),
.I2(\m_atarget_enc_reg[2] [2]),
.I3(\m_atarget_enc_reg[2] [0]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[104]),
.O(\m_payload_i[11]_i_3_n_0 ));
LUT4 #(
.INIT(16'hEFE0))
\m_payload_i[12]_i_1
(.I0(\m_payload_i[12]_i_2_n_0 ),
.I1(\m_payload_i[12]_i_3_n_0 ),
.I2(aa_rready),
.I3(\skid_buffer_reg_n_0_[12] ),
.O(skid_buffer[12]));
LUT6 #(
.INIT(64'h0000FC0A00000C0A))
\m_payload_i[12]_i_2
(.I0(m_axi_rdata[9]),
.I1(m_axi_rdata[137]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [2]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[169]),
.O(\m_payload_i[12]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0F0A0C00000A0C00))
\m_payload_i[12]_i_3
(.I0(m_axi_rdata[73]),
.I1(m_axi_rdata[41]),
.I2(\m_atarget_enc_reg[2] [2]),
.I3(\m_atarget_enc_reg[2] [0]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[105]),
.O(\m_payload_i[12]_i_3_n_0 ));
LUT4 #(
.INIT(16'hEFE0))
\m_payload_i[13]_i_1
(.I0(\m_payload_i[13]_i_2_n_0 ),
.I1(\m_payload_i[13]_i_3_n_0 ),
.I2(aa_rready),
.I3(\skid_buffer_reg_n_0_[13] ),
.O(skid_buffer[13]));
LUT6 #(
.INIT(64'h0000FC0A00000C0A))
\m_payload_i[13]_i_2
(.I0(m_axi_rdata[10]),
.I1(m_axi_rdata[138]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [2]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[170]),
.O(\m_payload_i[13]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0F0A0C00000A0C00))
\m_payload_i[13]_i_3
(.I0(m_axi_rdata[74]),
.I1(m_axi_rdata[42]),
.I2(\m_atarget_enc_reg[2] [2]),
.I3(\m_atarget_enc_reg[2] [0]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[106]),
.O(\m_payload_i[13]_i_3_n_0 ));
LUT4 #(
.INIT(16'hEFE0))
\m_payload_i[14]_i_1
(.I0(\m_payload_i[14]_i_2_n_0 ),
.I1(\m_payload_i[14]_i_3_n_0 ),
.I2(aa_rready),
.I3(\skid_buffer_reg_n_0_[14] ),
.O(skid_buffer[14]));
LUT6 #(
.INIT(64'h0000FC0A00000C0A))
\m_payload_i[14]_i_2
(.I0(m_axi_rdata[11]),
.I1(m_axi_rdata[139]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [2]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[171]),
.O(\m_payload_i[14]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0C0F0A000C000A00))
\m_payload_i[14]_i_3
(.I0(m_axi_rdata[43]),
.I1(m_axi_rdata[107]),
.I2(\m_atarget_enc_reg[2] [2]),
.I3(\m_atarget_enc_reg[2] [0]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[75]),
.O(\m_payload_i[14]_i_3_n_0 ));
LUT4 #(
.INIT(16'hEFE0))
\m_payload_i[15]_i_1
(.I0(\m_payload_i[15]_i_2_n_0 ),
.I1(\m_payload_i[15]_i_3_n_0 ),
.I2(aa_rready),
.I3(\skid_buffer_reg_n_0_[15] ),
.O(skid_buffer[15]));
LUT6 #(
.INIT(64'h0F0A0C00000A0C00))
\m_payload_i[15]_i_2
(.I0(m_axi_rdata[76]),
.I1(m_axi_rdata[44]),
.I2(\m_atarget_enc_reg[2] [2]),
.I3(\m_atarget_enc_reg[2] [0]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[108]),
.O(\m_payload_i[15]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000FC0A00000C0A))
\m_payload_i[15]_i_3
(.I0(m_axi_rdata[12]),
.I1(m_axi_rdata[140]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [2]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[172]),
.O(\m_payload_i[15]_i_3_n_0 ));
LUT4 #(
.INIT(16'hEFE0))
\m_payload_i[16]_i_1
(.I0(\m_payload_i[16]_i_2_n_0 ),
.I1(\m_payload_i[16]_i_3_n_0 ),
.I2(aa_rready),
.I3(\skid_buffer_reg_n_0_[16] ),
.O(skid_buffer[16]));
LUT6 #(
.INIT(64'h0000FC0A00000C0A))
\m_payload_i[16]_i_2
(.I0(m_axi_rdata[13]),
.I1(m_axi_rdata[141]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [2]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[173]),
.O(\m_payload_i[16]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0F0A0C00000A0C00))
\m_payload_i[16]_i_3
(.I0(m_axi_rdata[77]),
.I1(m_axi_rdata[45]),
.I2(\m_atarget_enc_reg[2] [2]),
.I3(\m_atarget_enc_reg[2] [0]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[109]),
.O(\m_payload_i[16]_i_3_n_0 ));
LUT4 #(
.INIT(16'hEFE0))
\m_payload_i[17]_i_1
(.I0(\m_payload_i[17]_i_2_n_0 ),
.I1(\m_payload_i[17]_i_3_n_0 ),
.I2(aa_rready),
.I3(\skid_buffer_reg_n_0_[17] ),
.O(skid_buffer[17]));
LUT6 #(
.INIT(64'h0000FC0A00000C0A))
\m_payload_i[17]_i_2
(.I0(m_axi_rdata[14]),
.I1(m_axi_rdata[142]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [2]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[174]),
.O(\m_payload_i[17]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0F0A0C00000A0C00))
\m_payload_i[17]_i_3
(.I0(m_axi_rdata[78]),
.I1(m_axi_rdata[46]),
.I2(\m_atarget_enc_reg[2] [2]),
.I3(\m_atarget_enc_reg[2] [0]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[110]),
.O(\m_payload_i[17]_i_3_n_0 ));
LUT4 #(
.INIT(16'hEFE0))
\m_payload_i[18]_i_1
(.I0(\m_payload_i[18]_i_2_n_0 ),
.I1(\m_payload_i[18]_i_3_n_0 ),
.I2(aa_rready),
.I3(\skid_buffer_reg_n_0_[18] ),
.O(skid_buffer[18]));
LUT6 #(
.INIT(64'h00CF000A00C0000A))
\m_payload_i[18]_i_2
(.I0(m_axi_rdata[15]),
.I1(m_axi_rdata[175]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [1]),
.I4(\m_atarget_enc_reg[2] [2]),
.I5(m_axi_rdata[143]),
.O(\m_payload_i[18]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0F0A0C00000A0C00))
\m_payload_i[18]_i_3
(.I0(m_axi_rdata[79]),
.I1(m_axi_rdata[47]),
.I2(\m_atarget_enc_reg[2] [2]),
.I3(\m_atarget_enc_reg[2] [0]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[111]),
.O(\m_payload_i[18]_i_3_n_0 ));
LUT4 #(
.INIT(16'hEFE0))
\m_payload_i[19]_i_1
(.I0(\m_payload_i[19]_i_2_n_0 ),
.I1(\m_payload_i[19]_i_3_n_0 ),
.I2(aa_rready),
.I3(\skid_buffer_reg_n_0_[19] ),
.O(skid_buffer[19]));
LUT6 #(
.INIT(64'h00CF000A00C0000A))
\m_payload_i[19]_i_2
(.I0(m_axi_rdata[16]),
.I1(m_axi_rdata[176]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [1]),
.I4(\m_atarget_enc_reg[2] [2]),
.I5(m_axi_rdata[144]),
.O(\m_payload_i[19]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000CAF00000CA00))
\m_payload_i[19]_i_3
(.I0(m_axi_rdata[80]),
.I1(m_axi_rdata[112]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [1]),
.I4(\m_atarget_enc_reg[2] [2]),
.I5(m_axi_rdata[48]),
.O(\m_payload_i[19]_i_3_n_0 ));
LUT5 #(
.INIT(32'hEEE0EEEE))
\m_payload_i[1]_i_1
(.I0(\skid_buffer_reg_n_0_[1] ),
.I1(aa_rready),
.I2(\m_payload_i[1]_i_2_n_0 ),
.I3(\m_payload_i[1]_i_3_n_0 ),
.I4(\m_payload_i[1]_i_4_n_0 ),
.O(skid_buffer[1]));
LUT5 #(
.INIT(32'h02300200))
\m_payload_i[1]_i_2
(.I0(m_axi_rresp[8]),
.I1(\m_atarget_enc_reg[2] [1]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [2]),
.I4(m_axi_rresp[2]),
.O(\m_payload_i[1]_i_2_n_0 ));
LUT5 #(
.INIT(32'h03020002))
\m_payload_i[1]_i_3
(.I0(m_axi_rresp[0]),
.I1(\m_atarget_enc_reg[2] [2]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [1]),
.I4(m_axi_rresp[4]),
.O(\m_payload_i[1]_i_3_n_0 ));
LUT6 #(
.INIT(64'hA00A2AAAA0AA2AAA))
\m_payload_i[1]_i_4
(.I0(aa_rready),
.I1(m_axi_rresp[6]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [1]),
.I4(\m_atarget_enc_reg[2] [2]),
.I5(m_axi_rresp[10]),
.O(\m_payload_i[1]_i_4_n_0 ));
LUT4 #(
.INIT(16'hEFE0))
\m_payload_i[20]_i_1
(.I0(\m_payload_i[20]_i_2_n_0 ),
.I1(\m_payload_i[20]_i_3_n_0 ),
.I2(aa_rready),
.I3(\skid_buffer_reg_n_0_[20] ),
.O(skid_buffer[20]));
LUT6 #(
.INIT(64'h00CF000A00C0000A))
\m_payload_i[20]_i_2
(.I0(m_axi_rdata[17]),
.I1(m_axi_rdata[177]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [1]),
.I4(\m_atarget_enc_reg[2] [2]),
.I5(m_axi_rdata[145]),
.O(\m_payload_i[20]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0A0F0C000A000C00))
\m_payload_i[20]_i_3
(.I0(m_axi_rdata[113]),
.I1(m_axi_rdata[49]),
.I2(\m_atarget_enc_reg[2] [2]),
.I3(\m_atarget_enc_reg[2] [0]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[81]),
.O(\m_payload_i[20]_i_3_n_0 ));
LUT4 #(
.INIT(16'hEFE0))
\m_payload_i[21]_i_1
(.I0(\m_payload_i[21]_i_2_n_0 ),
.I1(\m_payload_i[21]_i_3_n_0 ),
.I2(aa_rready),
.I3(\skid_buffer_reg_n_0_[21] ),
.O(skid_buffer[21]));
LUT6 #(
.INIT(64'h0000FC0A00000C0A))
\m_payload_i[21]_i_2
(.I0(m_axi_rdata[18]),
.I1(m_axi_rdata[146]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [2]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[178]),
.O(\m_payload_i[21]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0F0A0C00000A0C00))
\m_payload_i[21]_i_3
(.I0(m_axi_rdata[82]),
.I1(m_axi_rdata[50]),
.I2(\m_atarget_enc_reg[2] [2]),
.I3(\m_atarget_enc_reg[2] [0]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[114]),
.O(\m_payload_i[21]_i_3_n_0 ));
LUT4 #(
.INIT(16'hEFE0))
\m_payload_i[22]_i_1
(.I0(\m_payload_i[22]_i_2_n_0 ),
.I1(\m_payload_i[22]_i_3_n_0 ),
.I2(aa_rready),
.I3(\skid_buffer_reg_n_0_[22] ),
.O(skid_buffer[22]));
LUT6 #(
.INIT(64'h00CF000A00C0000A))
\m_payload_i[22]_i_2
(.I0(m_axi_rdata[19]),
.I1(m_axi_rdata[179]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [1]),
.I4(\m_atarget_enc_reg[2] [2]),
.I5(m_axi_rdata[147]),
.O(\m_payload_i[22]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0F0A0C00000A0C00))
\m_payload_i[22]_i_3
(.I0(m_axi_rdata[83]),
.I1(m_axi_rdata[51]),
.I2(\m_atarget_enc_reg[2] [2]),
.I3(\m_atarget_enc_reg[2] [0]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[115]),
.O(\m_payload_i[22]_i_3_n_0 ));
LUT4 #(
.INIT(16'hEFE0))
\m_payload_i[23]_i_1
(.I0(\m_payload_i[23]_i_2_n_0 ),
.I1(\m_payload_i[23]_i_3_n_0 ),
.I2(aa_rready),
.I3(\skid_buffer_reg_n_0_[23] ),
.O(skid_buffer[23]));
LUT6 #(
.INIT(64'h00CF000A00C0000A))
\m_payload_i[23]_i_2
(.I0(m_axi_rdata[20]),
.I1(m_axi_rdata[180]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [1]),
.I4(\m_atarget_enc_reg[2] [2]),
.I5(m_axi_rdata[148]),
.O(\m_payload_i[23]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0F0A0C00000A0C00))
\m_payload_i[23]_i_3
(.I0(m_axi_rdata[84]),
.I1(m_axi_rdata[52]),
.I2(\m_atarget_enc_reg[2] [2]),
.I3(\m_atarget_enc_reg[2] [0]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[116]),
.O(\m_payload_i[23]_i_3_n_0 ));
LUT4 #(
.INIT(16'hEFE0))
\m_payload_i[24]_i_1
(.I0(\m_payload_i[24]_i_2_n_0 ),
.I1(\m_payload_i[24]_i_3_n_0 ),
.I2(aa_rready),
.I3(\skid_buffer_reg_n_0_[24] ),
.O(skid_buffer[24]));
LUT6 #(
.INIT(64'h0000FC0A00000C0A))
\m_payload_i[24]_i_2
(.I0(m_axi_rdata[21]),
.I1(m_axi_rdata[149]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [2]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[181]),
.O(\m_payload_i[24]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0F0A0C00000A0C00))
\m_payload_i[24]_i_3
(.I0(m_axi_rdata[85]),
.I1(m_axi_rdata[53]),
.I2(\m_atarget_enc_reg[2] [2]),
.I3(\m_atarget_enc_reg[2] [0]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[117]),
.O(\m_payload_i[24]_i_3_n_0 ));
LUT4 #(
.INIT(16'hEFE0))
\m_payload_i[25]_i_1
(.I0(\m_payload_i[25]_i_2_n_0 ),
.I1(\m_payload_i[25]_i_3_n_0 ),
.I2(aa_rready),
.I3(\skid_buffer_reg_n_0_[25] ),
.O(skid_buffer[25]));
LUT6 #(
.INIT(64'h0000FC0A00000C0A))
\m_payload_i[25]_i_2
(.I0(m_axi_rdata[22]),
.I1(m_axi_rdata[150]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [2]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[182]),
.O(\m_payload_i[25]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0F0A0C00000A0C00))
\m_payload_i[25]_i_3
(.I0(m_axi_rdata[86]),
.I1(m_axi_rdata[54]),
.I2(\m_atarget_enc_reg[2] [2]),
.I3(\m_atarget_enc_reg[2] [0]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[118]),
.O(\m_payload_i[25]_i_3_n_0 ));
LUT4 #(
.INIT(16'hEFE0))
\m_payload_i[26]_i_1
(.I0(\m_payload_i[26]_i_2_n_0 ),
.I1(\m_payload_i[26]_i_3_n_0 ),
.I2(aa_rready),
.I3(\skid_buffer_reg_n_0_[26] ),
.O(skid_buffer[26]));
LUT6 #(
.INIT(64'h00CF000A00C0000A))
\m_payload_i[26]_i_2
(.I0(m_axi_rdata[23]),
.I1(m_axi_rdata[183]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [1]),
.I4(\m_atarget_enc_reg[2] [2]),
.I5(m_axi_rdata[151]),
.O(\m_payload_i[26]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0F0A0C00000A0C00))
\m_payload_i[26]_i_3
(.I0(m_axi_rdata[87]),
.I1(m_axi_rdata[55]),
.I2(\m_atarget_enc_reg[2] [2]),
.I3(\m_atarget_enc_reg[2] [0]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[119]),
.O(\m_payload_i[26]_i_3_n_0 ));
LUT4 #(
.INIT(16'hEFE0))
\m_payload_i[27]_i_1
(.I0(\m_payload_i[27]_i_2_n_0 ),
.I1(\m_payload_i[27]_i_3_n_0 ),
.I2(aa_rready),
.I3(\skid_buffer_reg_n_0_[27] ),
.O(skid_buffer[27]));
LUT6 #(
.INIT(64'h00CF000A00C0000A))
\m_payload_i[27]_i_2
(.I0(m_axi_rdata[24]),
.I1(m_axi_rdata[184]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [1]),
.I4(\m_atarget_enc_reg[2] [2]),
.I5(m_axi_rdata[152]),
.O(\m_payload_i[27]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0A0F0C000A000C00))
\m_payload_i[27]_i_3
(.I0(m_axi_rdata[120]),
.I1(m_axi_rdata[56]),
.I2(\m_atarget_enc_reg[2] [2]),
.I3(\m_atarget_enc_reg[2] [0]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[88]),
.O(\m_payload_i[27]_i_3_n_0 ));
LUT4 #(
.INIT(16'hEFE0))
\m_payload_i[28]_i_1
(.I0(\m_payload_i[28]_i_2_n_0 ),
.I1(\m_payload_i[28]_i_3_n_0 ),
.I2(aa_rready),
.I3(\skid_buffer_reg_n_0_[28] ),
.O(skid_buffer[28]));
LUT6 #(
.INIT(64'h0A0F0C000A000C00))
\m_payload_i[28]_i_2
(.I0(m_axi_rdata[121]),
.I1(m_axi_rdata[57]),
.I2(\m_atarget_enc_reg[2] [2]),
.I3(\m_atarget_enc_reg[2] [0]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[89]),
.O(\m_payload_i[28]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000FC0A00000C0A))
\m_payload_i[28]_i_3
(.I0(m_axi_rdata[25]),
.I1(m_axi_rdata[153]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [2]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[185]),
.O(\m_payload_i[28]_i_3_n_0 ));
LUT4 #(
.INIT(16'hEFE0))
\m_payload_i[29]_i_1
(.I0(\m_payload_i[29]_i_2_n_0 ),
.I1(\m_payload_i[29]_i_3_n_0 ),
.I2(aa_rready),
.I3(\skid_buffer_reg_n_0_[29] ),
.O(skid_buffer[29]));
LUT6 #(
.INIT(64'h0A0F0C000A000C00))
\m_payload_i[29]_i_2
(.I0(m_axi_rdata[122]),
.I1(m_axi_rdata[58]),
.I2(\m_atarget_enc_reg[2] [2]),
.I3(\m_atarget_enc_reg[2] [0]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[90]),
.O(\m_payload_i[29]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000FC0A00000C0A))
\m_payload_i[29]_i_3
(.I0(m_axi_rdata[26]),
.I1(m_axi_rdata[154]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [2]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[186]),
.O(\m_payload_i[29]_i_3_n_0 ));
LUT5 #(
.INIT(32'hEEE0EEEE))
\m_payload_i[2]_i_1
(.I0(\skid_buffer_reg_n_0_[2] ),
.I1(aa_rready),
.I2(\m_payload_i[2]_i_2_n_0 ),
.I3(\m_payload_i[2]_i_3_n_0 ),
.I4(\m_payload_i[2]_i_4_n_0 ),
.O(skid_buffer[2]));
LUT5 #(
.INIT(32'h02300200))
\m_payload_i[2]_i_2
(.I0(m_axi_rresp[9]),
.I1(\m_atarget_enc_reg[2] [1]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [2]),
.I4(m_axi_rresp[3]),
.O(\m_payload_i[2]_i_2_n_0 ));
LUT5 #(
.INIT(32'h03020002))
\m_payload_i[2]_i_3
(.I0(m_axi_rresp[1]),
.I1(\m_atarget_enc_reg[2] [2]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [1]),
.I4(m_axi_rresp[5]),
.O(\m_payload_i[2]_i_3_n_0 ));
LUT6 #(
.INIT(64'hA00A2AAAA0AA2AAA))
\m_payload_i[2]_i_4
(.I0(aa_rready),
.I1(m_axi_rresp[7]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [1]),
.I4(\m_atarget_enc_reg[2] [2]),
.I5(m_axi_rresp[11]),
.O(\m_payload_i[2]_i_4_n_0 ));
LUT4 #(
.INIT(16'hEFE0))
\m_payload_i[30]_i_1
(.I0(\m_payload_i[30]_i_2_n_0 ),
.I1(\m_payload_i[30]_i_3_n_0 ),
.I2(aa_rready),
.I3(\skid_buffer_reg_n_0_[30] ),
.O(skid_buffer[30]));
LUT6 #(
.INIT(64'h0000FC0A00000C0A))
\m_payload_i[30]_i_2
(.I0(m_axi_rdata[27]),
.I1(m_axi_rdata[155]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [2]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[187]),
.O(\m_payload_i[30]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000CAF00000CA00))
\m_payload_i[30]_i_3
(.I0(m_axi_rdata[91]),
.I1(m_axi_rdata[123]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [1]),
.I4(\m_atarget_enc_reg[2] [2]),
.I5(m_axi_rdata[59]),
.O(\m_payload_i[30]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT4 #(
.INIT(16'hEFE0))
\m_payload_i[31]_i_1
(.I0(\m_payload_i[31]_i_2_n_0 ),
.I1(\m_payload_i[31]_i_3_n_0 ),
.I2(aa_rready),
.I3(\skid_buffer_reg_n_0_[31] ),
.O(skid_buffer[31]));
LUT6 #(
.INIT(64'h0F0A0C00000A0C00))
\m_payload_i[31]_i_2
(.I0(m_axi_rdata[92]),
.I1(m_axi_rdata[60]),
.I2(\m_atarget_enc_reg[2] [2]),
.I3(\m_atarget_enc_reg[2] [0]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[124]),
.O(\m_payload_i[31]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000FC0A00000C0A))
\m_payload_i[31]_i_3
(.I0(m_axi_rdata[28]),
.I1(m_axi_rdata[156]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [2]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[188]),
.O(\m_payload_i[31]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT4 #(
.INIT(16'hEFE0))
\m_payload_i[32]_i_1
(.I0(\m_payload_i[32]_i_2_n_0 ),
.I1(\m_payload_i[32]_i_3_n_0 ),
.I2(aa_rready),
.I3(\skid_buffer_reg_n_0_[32] ),
.O(skid_buffer[32]));
LUT6 #(
.INIT(64'h0A0F0C000A000C00))
\m_payload_i[32]_i_2
(.I0(m_axi_rdata[125]),
.I1(m_axi_rdata[61]),
.I2(\m_atarget_enc_reg[2] [2]),
.I3(\m_atarget_enc_reg[2] [0]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[93]),
.O(\m_payload_i[32]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000FC0A00000C0A))
\m_payload_i[32]_i_3
(.I0(m_axi_rdata[29]),
.I1(m_axi_rdata[157]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [2]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[189]),
.O(\m_payload_i[32]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT4 #(
.INIT(16'hEFE0))
\m_payload_i[33]_i_1
(.I0(\m_payload_i[33]_i_2_n_0 ),
.I1(\m_payload_i[33]_i_3_n_0 ),
.I2(aa_rready),
.I3(\skid_buffer_reg_n_0_[33] ),
.O(skid_buffer[33]));
LUT6 #(
.INIT(64'h0000FC0A00000C0A))
\m_payload_i[33]_i_2
(.I0(m_axi_rdata[30]),
.I1(m_axi_rdata[158]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [2]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[190]),
.O(\m_payload_i[33]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0F0A0C00000A0C00))
\m_payload_i[33]_i_3
(.I0(m_axi_rdata[94]),
.I1(m_axi_rdata[62]),
.I2(\m_atarget_enc_reg[2] [2]),
.I3(\m_atarget_enc_reg[2] [0]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[126]),
.O(\m_payload_i[33]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT4 #(
.INIT(16'hEFE0))
\m_payload_i[34]_i_2
(.I0(\m_payload_i[34]_i_3_n_0 ),
.I1(\m_payload_i[34]_i_4_n_0 ),
.I2(aa_rready),
.I3(\skid_buffer_reg_n_0_[34] ),
.O(skid_buffer[34]));
LUT6 #(
.INIT(64'h0000FC0A00000C0A))
\m_payload_i[34]_i_3
(.I0(m_axi_rdata[31]),
.I1(m_axi_rdata[159]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [2]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[191]),
.O(\m_payload_i[34]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0F0A0C00000A0C00))
\m_payload_i[34]_i_4
(.I0(m_axi_rdata[95]),
.I1(m_axi_rdata[63]),
.I2(\m_atarget_enc_reg[2] [2]),
.I3(\m_atarget_enc_reg[2] [0]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[127]),
.O(\m_payload_i[34]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT4 #(
.INIT(16'hEFE0))
\m_payload_i[3]_i_1
(.I0(\m_payload_i[3]_i_2_n_0 ),
.I1(\m_payload_i[3]_i_3_n_0 ),
.I2(aa_rready),
.I3(\skid_buffer_reg_n_0_[3] ),
.O(skid_buffer[3]));
LUT6 #(
.INIT(64'h0000FC0A00000C0A))
\m_payload_i[3]_i_2
(.I0(m_axi_rdata[0]),
.I1(m_axi_rdata[128]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [2]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[160]),
.O(\m_payload_i[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000CAF00000CA00))
\m_payload_i[3]_i_3
(.I0(m_axi_rdata[64]),
.I1(m_axi_rdata[96]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [1]),
.I4(\m_atarget_enc_reg[2] [2]),
.I5(m_axi_rdata[32]),
.O(\m_payload_i[3]_i_3_n_0 ));
LUT4 #(
.INIT(16'hEFE0))
\m_payload_i[4]_i_1
(.I0(\m_payload_i[4]_i_2_n_0 ),
.I1(\m_payload_i[4]_i_3_n_0 ),
.I2(aa_rready),
.I3(\skid_buffer_reg_n_0_[4] ),
.O(skid_buffer[4]));
LUT6 #(
.INIT(64'h00CF000A00C0000A))
\m_payload_i[4]_i_2
(.I0(m_axi_rdata[1]),
.I1(m_axi_rdata[161]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [1]),
.I4(\m_atarget_enc_reg[2] [2]),
.I5(m_axi_rdata[129]),
.O(\m_payload_i[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0F0A0C00000A0C00))
\m_payload_i[4]_i_3
(.I0(m_axi_rdata[65]),
.I1(m_axi_rdata[33]),
.I2(\m_atarget_enc_reg[2] [2]),
.I3(\m_atarget_enc_reg[2] [0]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[97]),
.O(\m_payload_i[4]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT4 #(
.INIT(16'hEFE0))
\m_payload_i[5]_i_1
(.I0(\m_payload_i[5]_i_2_n_0 ),
.I1(\m_payload_i[5]_i_3_n_0 ),
.I2(aa_rready),
.I3(\skid_buffer_reg_n_0_[5] ),
.O(skid_buffer[5]));
LUT6 #(
.INIT(64'h0000FC0A00000C0A))
\m_payload_i[5]_i_2
(.I0(m_axi_rdata[2]),
.I1(m_axi_rdata[130]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [2]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[162]),
.O(\m_payload_i[5]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0F0A0C00000A0C00))
\m_payload_i[5]_i_3
(.I0(m_axi_rdata[66]),
.I1(m_axi_rdata[34]),
.I2(\m_atarget_enc_reg[2] [2]),
.I3(\m_atarget_enc_reg[2] [0]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[98]),
.O(\m_payload_i[5]_i_3_n_0 ));
LUT4 #(
.INIT(16'hEFE0))
\m_payload_i[6]_i_1
(.I0(\m_payload_i[6]_i_2_n_0 ),
.I1(\m_payload_i[6]_i_3_n_0 ),
.I2(aa_rready),
.I3(\skid_buffer_reg_n_0_[6] ),
.O(skid_buffer[6]));
LUT6 #(
.INIT(64'h00CF000A00C0000A))
\m_payload_i[6]_i_2
(.I0(m_axi_rdata[3]),
.I1(m_axi_rdata[163]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [1]),
.I4(\m_atarget_enc_reg[2] [2]),
.I5(m_axi_rdata[131]),
.O(\m_payload_i[6]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000CAF00000CA00))
\m_payload_i[6]_i_3
(.I0(m_axi_rdata[67]),
.I1(m_axi_rdata[99]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [1]),
.I4(\m_atarget_enc_reg[2] [2]),
.I5(m_axi_rdata[35]),
.O(\m_payload_i[6]_i_3_n_0 ));
LUT4 #(
.INIT(16'hEFE0))
\m_payload_i[7]_i_1
(.I0(\m_payload_i[7]_i_2_n_0 ),
.I1(\m_payload_i[7]_i_3_n_0 ),
.I2(aa_rready),
.I3(\skid_buffer_reg_n_0_[7] ),
.O(skid_buffer[7]));
LUT6 #(
.INIT(64'h00CF000A00C0000A))
\m_payload_i[7]_i_2
(.I0(m_axi_rdata[4]),
.I1(m_axi_rdata[164]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [1]),
.I4(\m_atarget_enc_reg[2] [2]),
.I5(m_axi_rdata[132]),
.O(\m_payload_i[7]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0F0A0C00000A0C00))
\m_payload_i[7]_i_3
(.I0(m_axi_rdata[68]),
.I1(m_axi_rdata[36]),
.I2(\m_atarget_enc_reg[2] [2]),
.I3(\m_atarget_enc_reg[2] [0]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[100]),
.O(\m_payload_i[7]_i_3_n_0 ));
LUT4 #(
.INIT(16'hEFE0))
\m_payload_i[8]_i_1
(.I0(\m_payload_i[8]_i_2_n_0 ),
.I1(\m_payload_i[8]_i_3_n_0 ),
.I2(aa_rready),
.I3(\skid_buffer_reg_n_0_[8] ),
.O(skid_buffer[8]));
LUT6 #(
.INIT(64'h0000FC0A00000C0A))
\m_payload_i[8]_i_2
(.I0(m_axi_rdata[5]),
.I1(m_axi_rdata[133]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [2]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[165]),
.O(\m_payload_i[8]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0F0A0C00000A0C00))
\m_payload_i[8]_i_3
(.I0(m_axi_rdata[69]),
.I1(m_axi_rdata[37]),
.I2(\m_atarget_enc_reg[2] [2]),
.I3(\m_atarget_enc_reg[2] [0]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[101]),
.O(\m_payload_i[8]_i_3_n_0 ));
LUT4 #(
.INIT(16'hEFE0))
\m_payload_i[9]_i_1
(.I0(\m_payload_i[9]_i_2_n_0 ),
.I1(\m_payload_i[9]_i_3_n_0 ),
.I2(aa_rready),
.I3(\skid_buffer_reg_n_0_[9] ),
.O(skid_buffer[9]));
LUT6 #(
.INIT(64'h0000FC0A00000C0A))
\m_payload_i[9]_i_2
(.I0(m_axi_rdata[6]),
.I1(m_axi_rdata[134]),
.I2(\m_atarget_enc_reg[2] [0]),
.I3(\m_atarget_enc_reg[2] [2]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[166]),
.O(\m_payload_i[9]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0F0A0C00000A0C00))
\m_payload_i[9]_i_3
(.I0(m_axi_rdata[70]),
.I1(m_axi_rdata[38]),
.I2(\m_atarget_enc_reg[2] [2]),
.I3(\m_atarget_enc_reg[2] [0]),
.I4(\m_atarget_enc_reg[2] [1]),
.I5(m_axi_rdata[102]),
.O(\m_payload_i[9]_i_3_n_0 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(E),
.D(skid_buffer[0]),
.Q(Q[0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(E),
.D(skid_buffer[10]),
.Q(Q[10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(E),
.D(skid_buffer[11]),
.Q(Q[11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(E),
.D(skid_buffer[12]),
.Q(Q[12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(E),
.D(skid_buffer[13]),
.Q(Q[13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(E),
.D(skid_buffer[14]),
.Q(Q[14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(E),
.D(skid_buffer[15]),
.Q(Q[15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(E),
.D(skid_buffer[16]),
.Q(Q[16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(E),
.D(skid_buffer[17]),
.Q(Q[17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(E),
.D(skid_buffer[18]),
.Q(Q[18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(E),
.D(skid_buffer[19]),
.Q(Q[19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(E),
.D(skid_buffer[1]),
.Q(Q[1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(E),
.D(skid_buffer[20]),
.Q(Q[20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(E),
.D(skid_buffer[21]),
.Q(Q[21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(E),
.D(skid_buffer[22]),
.Q(Q[22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(E),
.D(skid_buffer[23]),
.Q(Q[23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(E),
.D(skid_buffer[24]),
.Q(Q[24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(E),
.D(skid_buffer[25]),
.Q(Q[25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(E),
.D(skid_buffer[26]),
.Q(Q[26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(E),
.D(skid_buffer[27]),
.Q(Q[27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(E),
.D(skid_buffer[28]),
.Q(Q[28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(E),
.D(skid_buffer[29]),
.Q(Q[29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(E),
.D(skid_buffer[2]),
.Q(Q[2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(E),
.D(skid_buffer[30]),
.Q(Q[30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(E),
.D(skid_buffer[31]),
.Q(Q[31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(E),
.D(skid_buffer[32]),
.Q(Q[32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(E),
.D(skid_buffer[33]),
.Q(Q[33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(E),
.D(skid_buffer[34]),
.Q(Q[34]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(E),
.D(skid_buffer[3]),
.Q(Q[3]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(E),
.D(skid_buffer[4]),
.Q(Q[4]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(E),
.D(skid_buffer[5]),
.Q(Q[5]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(E),
.D(skid_buffer[6]),
.Q(Q[6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(E),
.D(skid_buffer[7]),
.Q(Q[7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(E),
.D(skid_buffer[8]),
.Q(Q[8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(E),
.D(skid_buffer[9]),
.Q(Q[9]),
.R(1'b0));
LUT6 #(
.INIT(64'h000000007FFFFFFF))
\m_ready_d[1]_i_3
(.I0(sr_rvalid),
.I1(Q[0]),
.I2(s_axi_rready),
.I3(aa_grant_rnw),
.I4(m_valid_i),
.I5(m_ready_d),
.O(\m_ready_d_reg[1] ));
LUT6 #(
.INIT(64'hFFF05F3FFFFF5F3F))
m_valid_i_i_5
(.I0(m_axi_rvalid[1]),
.I1(m_axi_rvalid[0]),
.I2(\m_atarget_enc_reg[2] [1]),
.I3(\m_atarget_enc_reg[2] [0]),
.I4(\m_atarget_enc_reg[2] [2]),
.I5(m_axi_rvalid[2]),
.O(m_valid_i_reg_0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(\aresetn_d_reg[1]_0 ),
.Q(sr_rvalid),
.R(1'b0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(\aresetn_d_reg[0]_0 ),
.Q(aa_rready),
.R(1'b0));
LUT5 #(
.INIT(32'h7F7FFF00))
\skid_buffer[0]_i_1
(.I0(\m_atarget_enc_reg[2] [2]),
.I1(\m_atarget_enc_reg[2] [0]),
.I2(\m_atarget_enc_reg[2] [1]),
.I3(\skid_buffer_reg_n_0_[0] ),
.I4(aa_rready),
.O(skid_buffer[0]));
LUT2 #(
.INIT(4'hE))
\skid_buffer[10]_i_1
(.I0(\m_payload_i[10]_i_2_n_0 ),
.I1(\m_payload_i[10]_i_3_n_0 ),
.O(\skid_buffer[10]_i_1_n_0 ));
LUT2 #(
.INIT(4'hE))
\skid_buffer[11]_i_1
(.I0(\m_payload_i[11]_i_2_n_0 ),
.I1(\m_payload_i[11]_i_3_n_0 ),
.O(\skid_buffer[11]_i_1_n_0 ));
LUT2 #(
.INIT(4'hE))
\skid_buffer[12]_i_1
(.I0(\m_payload_i[12]_i_2_n_0 ),
.I1(\m_payload_i[12]_i_3_n_0 ),
.O(\skid_buffer[12]_i_1_n_0 ));
LUT2 #(
.INIT(4'hE))
\skid_buffer[13]_i_1
(.I0(\m_payload_i[13]_i_2_n_0 ),
.I1(\m_payload_i[13]_i_3_n_0 ),
.O(\skid_buffer[13]_i_1_n_0 ));
LUT2 #(
.INIT(4'hE))
\skid_buffer[14]_i_1
(.I0(\m_payload_i[14]_i_2_n_0 ),
.I1(\m_payload_i[14]_i_3_n_0 ),
.O(\skid_buffer[14]_i_1_n_0 ));
LUT2 #(
.INIT(4'hE))
\skid_buffer[15]_i_1
(.I0(\m_payload_i[15]_i_2_n_0 ),
.I1(\m_payload_i[15]_i_3_n_0 ),
.O(\skid_buffer[15]_i_1_n_0 ));
LUT2 #(
.INIT(4'hE))
\skid_buffer[16]_i_1
(.I0(\m_payload_i[16]_i_2_n_0 ),
.I1(\m_payload_i[16]_i_3_n_0 ),
.O(\skid_buffer[16]_i_1_n_0 ));
LUT2 #(
.INIT(4'hE))
\skid_buffer[17]_i_1
(.I0(\m_payload_i[17]_i_2_n_0 ),
.I1(\m_payload_i[17]_i_3_n_0 ),
.O(\skid_buffer[17]_i_1_n_0 ));
LUT2 #(
.INIT(4'hE))
\skid_buffer[18]_i_1
(.I0(\m_payload_i[18]_i_2_n_0 ),
.I1(\m_payload_i[18]_i_3_n_0 ),
.O(\skid_buffer[18]_i_1_n_0 ));
LUT2 #(
.INIT(4'hE))
\skid_buffer[19]_i_1
(.I0(\m_payload_i[19]_i_2_n_0 ),
.I1(\m_payload_i[19]_i_3_n_0 ),
.O(\skid_buffer[19]_i_1_n_0 ));
LUT2 #(
.INIT(4'hE))
\skid_buffer[20]_i_1
(.I0(\m_payload_i[20]_i_2_n_0 ),
.I1(\m_payload_i[20]_i_3_n_0 ),
.O(\skid_buffer[20]_i_1_n_0 ));
LUT2 #(
.INIT(4'hE))
\skid_buffer[21]_i_1
(.I0(\m_payload_i[21]_i_2_n_0 ),
.I1(\m_payload_i[21]_i_3_n_0 ),
.O(\skid_buffer[21]_i_1_n_0 ));
LUT2 #(
.INIT(4'hE))
\skid_buffer[22]_i_1
(.I0(\m_payload_i[22]_i_2_n_0 ),
.I1(\m_payload_i[22]_i_3_n_0 ),
.O(\skid_buffer[22]_i_1_n_0 ));
LUT2 #(
.INIT(4'hE))
\skid_buffer[23]_i_1
(.I0(\m_payload_i[23]_i_2_n_0 ),
.I1(\m_payload_i[23]_i_3_n_0 ),
.O(\skid_buffer[23]_i_1_n_0 ));
LUT2 #(
.INIT(4'hE))
\skid_buffer[24]_i_1
(.I0(\m_payload_i[24]_i_2_n_0 ),
.I1(\m_payload_i[24]_i_3_n_0 ),
.O(\skid_buffer[24]_i_1_n_0 ));
LUT2 #(
.INIT(4'hE))
\skid_buffer[25]_i_1
(.I0(\m_payload_i[25]_i_2_n_0 ),
.I1(\m_payload_i[25]_i_3_n_0 ),
.O(\skid_buffer[25]_i_1_n_0 ));
LUT2 #(
.INIT(4'hE))
\skid_buffer[26]_i_1
(.I0(\m_payload_i[26]_i_2_n_0 ),
.I1(\m_payload_i[26]_i_3_n_0 ),
.O(\skid_buffer[26]_i_1_n_0 ));
LUT2 #(
.INIT(4'hE))
\skid_buffer[27]_i_1
(.I0(\m_payload_i[27]_i_2_n_0 ),
.I1(\m_payload_i[27]_i_3_n_0 ),
.O(\skid_buffer[27]_i_1_n_0 ));
LUT2 #(
.INIT(4'hE))
\skid_buffer[28]_i_1
(.I0(\m_payload_i[28]_i_2_n_0 ),
.I1(\m_payload_i[28]_i_3_n_0 ),
.O(\skid_buffer[28]_i_1_n_0 ));
LUT2 #(
.INIT(4'hE))
\skid_buffer[29]_i_1
(.I0(\m_payload_i[29]_i_2_n_0 ),
.I1(\m_payload_i[29]_i_3_n_0 ),
.O(\skid_buffer[29]_i_1_n_0 ));
LUT2 #(
.INIT(4'hE))
\skid_buffer[30]_i_1
(.I0(\m_payload_i[30]_i_2_n_0 ),
.I1(\m_payload_i[30]_i_3_n_0 ),
.O(\skid_buffer[30]_i_1_n_0 ));
LUT2 #(
.INIT(4'hE))
\skid_buffer[31]_i_1
(.I0(\m_payload_i[31]_i_2_n_0 ),
.I1(\m_payload_i[31]_i_3_n_0 ),
.O(\skid_buffer[31]_i_1_n_0 ));
LUT2 #(
.INIT(4'hE))
\skid_buffer[32]_i_1
(.I0(\m_payload_i[32]_i_2_n_0 ),
.I1(\m_payload_i[32]_i_3_n_0 ),
.O(\skid_buffer[32]_i_1_n_0 ));
LUT2 #(
.INIT(4'hE))
\skid_buffer[33]_i_1
(.I0(\m_payload_i[33]_i_2_n_0 ),
.I1(\m_payload_i[33]_i_3_n_0 ),
.O(\skid_buffer[33]_i_1_n_0 ));
LUT2 #(
.INIT(4'hE))
\skid_buffer[34]_i_1
(.I0(\m_payload_i[34]_i_3_n_0 ),
.I1(\m_payload_i[34]_i_4_n_0 ),
.O(\skid_buffer[34]_i_1_n_0 ));
LUT2 #(
.INIT(4'hE))
\skid_buffer[3]_i_1
(.I0(\m_payload_i[3]_i_2_n_0 ),
.I1(\m_payload_i[3]_i_3_n_0 ),
.O(\skid_buffer[3]_i_1_n_0 ));
LUT2 #(
.INIT(4'hE))
\skid_buffer[4]_i_1
(.I0(\m_payload_i[4]_i_2_n_0 ),
.I1(\m_payload_i[4]_i_3_n_0 ),
.O(\skid_buffer[4]_i_1_n_0 ));
LUT2 #(
.INIT(4'hE))
\skid_buffer[5]_i_1
(.I0(\m_payload_i[5]_i_2_n_0 ),
.I1(\m_payload_i[5]_i_3_n_0 ),
.O(\skid_buffer[5]_i_1_n_0 ));
LUT2 #(
.INIT(4'hE))
\skid_buffer[6]_i_1
(.I0(\m_payload_i[6]_i_2_n_0 ),
.I1(\m_payload_i[6]_i_3_n_0 ),
.O(\skid_buffer[6]_i_1_n_0 ));
LUT2 #(
.INIT(4'hE))
\skid_buffer[7]_i_1
(.I0(\m_payload_i[7]_i_2_n_0 ),
.I1(\m_payload_i[7]_i_3_n_0 ),
.O(\skid_buffer[7]_i_1_n_0 ));
LUT2 #(
.INIT(4'hE))
\skid_buffer[8]_i_1
(.I0(\m_payload_i[8]_i_2_n_0 ),
.I1(\m_payload_i[8]_i_3_n_0 ),
.O(\skid_buffer[8]_i_1_n_0 ));
LUT2 #(
.INIT(4'hE))
\skid_buffer[9]_i_1
(.I0(\m_payload_i[9]_i_2_n_0 ),
.I1(\m_payload_i[9]_i_3_n_0 ),
.O(\skid_buffer[9]_i_1_n_0 ));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(1'b1),
.D(skid_buffer[0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[10]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[11]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[12]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[13]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[14]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[15]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[16]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[17]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[18]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[19]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(1'b1),
.D(skid_buffer[1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[20]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[21]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[22]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[23]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[24]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[25]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[26]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[27]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[28]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[29]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(1'b1),
.D(skid_buffer[2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[30]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[31]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[32]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[33]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[34]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[3]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[4]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[5]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[6]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[7]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[8]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[9]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
endmodule
(* CHECK_LICENSE_TYPE = "ip_design_xbar_0,axi_crossbar_v2_1_15_axi_crossbar,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "axi_crossbar_v2_1_15_axi_crossbar,Vivado 2017.3" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(aclk,
aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF M00_AXI:M01_AXI:M02_AXI:M03_AXI:M04_AXI:M05_AXI:M06_AXI:M07_AXI:M08_AXI:M09_AXI:M10_AXI:M11_AXI:M12_AXI:M13_AXI:M14_AXI:M15_AXI:S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI:S06_AXI:S07_AXI:S08_AXI:S09_AXI:S10_AXI:S11_AXI:S12_AXI:S13_AXI:S14_AXI:S15_AXI, ASSOCIATED_RESET ARESETN" *) input aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, TYPE INTERCONNECT" *) input aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *) input [31:0]s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *) input [2:0]s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *) input [0:0]s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *) output [0:0]s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *) input [31:0]s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *) input [0:0]s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *) output [0:0]s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *) output [1:0]s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *) output [0:0]s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *) input [0:0]s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *) input [31:0]s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *) input [2:0]s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *) input [0:0]s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *) output [0:0]s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *) output [31:0]s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *) output [1:0]s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *) output [0:0]s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) input [0:0]s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI AWADDR [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI AWADDR [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI AWADDR [31:0] [191:160]" *) output [191:0]m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWPROT [2:0] [11:9], xilinx.com:interface:aximm:1.0 M04_AXI AWPROT [2:0] [14:12], xilinx.com:interface:aximm:1.0 M05_AXI AWPROT [2:0] [17:15]" *) output [17:0]m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI AWVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI AWVALID [0:0] [5:5]" *) output [5:0]m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI AWREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI AWREADY [0:0] [5:5]" *) input [5:0]m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI WDATA [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI WDATA [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI WDATA [31:0] [191:160]" *) output [191:0]m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI WSTRB [3:0] [15:12], xilinx.com:interface:aximm:1.0 M04_AXI WSTRB [3:0] [19:16], xilinx.com:interface:aximm:1.0 M05_AXI WSTRB [3:0] [23:20]" *) output [23:0]m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI WVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI WVALID [0:0] [5:5]" *) output [5:0]m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI WREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI WREADY [0:0] [5:5]" *) input [5:0]m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI BRESP [1:0] [7:6], xilinx.com:interface:aximm:1.0 M04_AXI BRESP [1:0] [9:8], xilinx.com:interface:aximm:1.0 M05_AXI BRESP [1:0] [11:10]" *) input [11:0]m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI BVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI BVALID [0:0] [5:5]" *) input [5:0]m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI BREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI BREADY [0:0] [5:5]" *) output [5:0]m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI ARADDR [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI ARADDR [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI ARADDR [31:0] [191:160]" *) output [191:0]m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARPROT [2:0] [11:9], xilinx.com:interface:aximm:1.0 M04_AXI ARPROT [2:0] [14:12], xilinx.com:interface:aximm:1.0 M05_AXI ARPROT [2:0] [17:15]" *) output [17:0]m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI ARVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI ARVALID [0:0] [5:5]" *) output [5:0]m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI ARREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI ARREADY [0:0] [5:5]" *) input [5:0]m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI RDATA [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI RDATA [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI RDATA [31:0] [191:160]" *) input [191:0]m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI RRESP [1:0] [7:6], xilinx.com:interface:aximm:1.0 M04_AXI RRESP [1:0] [9:8], xilinx.com:interface:aximm:1.0 M05_AXI RRESP [1:0] [11:10]" *) input [11:0]m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI RVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI RVALID [0:0] [5:5]" *) input [5:0]m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI RREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI RREADY [0:0] [5:5]" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M01_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M02_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M03_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M04_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M05_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) output [5:0]m_axi_rready;
wire aclk;
wire aresetn;
wire [191:0]m_axi_araddr;
wire [17:0]m_axi_arprot;
wire [5:0]m_axi_arready;
wire [5:0]m_axi_arvalid;
wire [191:0]m_axi_awaddr;
wire [17:0]m_axi_awprot;
wire [5:0]m_axi_awready;
wire [5:0]m_axi_awvalid;
wire [5:0]m_axi_bready;
wire [11:0]m_axi_bresp;
wire [5:0]m_axi_bvalid;
wire [191:0]m_axi_rdata;
wire [5:0]m_axi_rready;
wire [11:0]m_axi_rresp;
wire [5:0]m_axi_rvalid;
wire [191:0]m_axi_wdata;
wire [5:0]m_axi_wready;
wire [23:0]m_axi_wstrb;
wire [5:0]m_axi_wvalid;
wire [31:0]s_axi_araddr;
wire [2:0]s_axi_arprot;
wire [0:0]s_axi_arready;
wire [0:0]s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [2:0]s_axi_awprot;
wire [0:0]s_axi_awready;
wire [0:0]s_axi_awvalid;
wire [0:0]s_axi_bready;
wire [1:0]s_axi_bresp;
wire [0:0]s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [0:0]s_axi_rready;
wire [1:0]s_axi_rresp;
wire [0:0]s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire [0:0]s_axi_wready;
wire [3:0]s_axi_wstrb;
wire [0:0]s_axi_wvalid;
wire [11:0]NLW_inst_m_axi_arburst_UNCONNECTED;
wire [23:0]NLW_inst_m_axi_arcache_UNCONNECTED;
wire [5:0]NLW_inst_m_axi_arid_UNCONNECTED;
wire [47:0]NLW_inst_m_axi_arlen_UNCONNECTED;
wire [5:0]NLW_inst_m_axi_arlock_UNCONNECTED;
wire [23:0]NLW_inst_m_axi_arqos_UNCONNECTED;
wire [23:0]NLW_inst_m_axi_arregion_UNCONNECTED;
wire [17:0]NLW_inst_m_axi_arsize_UNCONNECTED;
wire [5:0]NLW_inst_m_axi_aruser_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_awburst_UNCONNECTED;
wire [23:0]NLW_inst_m_axi_awcache_UNCONNECTED;
wire [5:0]NLW_inst_m_axi_awid_UNCONNECTED;
wire [47:0]NLW_inst_m_axi_awlen_UNCONNECTED;
wire [5:0]NLW_inst_m_axi_awlock_UNCONNECTED;
wire [23:0]NLW_inst_m_axi_awqos_UNCONNECTED;
wire [23:0]NLW_inst_m_axi_awregion_UNCONNECTED;
wire [17:0]NLW_inst_m_axi_awsize_UNCONNECTED;
wire [5:0]NLW_inst_m_axi_awuser_UNCONNECTED;
wire [5:0]NLW_inst_m_axi_wid_UNCONNECTED;
wire [5:0]NLW_inst_m_axi_wlast_UNCONNECTED;
wire [5:0]NLW_inst_m_axi_wuser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_bid_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_rid_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_rlast_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED;
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "32" *)
(* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_PROTOCOL = "2" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_CONNECTIVITY_MODE = "0" *)
(* C_DEBUG = "1" *)
(* C_FAMILY = "zynq" *)
(* C_M_AXI_ADDR_WIDTH = "192'b000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000001110000000000000000000000000000100000000000000000000000000000000111100000000000000000000000000001100" *)
(* C_M_AXI_BASE_ADDR = "384'b000000000000000000000000000000000100000100100001000000000000000000000000000000000000000000000000010000010010000000000000000000000000000000000000000000000000000001000011110000110000000000000000000000000000000000000000000000000100001111000000000000000000000000000000000000000000000000000000010000111100000100000000000000000000000000000000000000000000000001000011110000100000000000000000" *)
(* C_M_AXI_READ_CONNECTIVITY = "192'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
(* C_M_AXI_READ_ISSUING = "192'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
(* C_M_AXI_SECURE = "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* C_M_AXI_WRITE_CONNECTIVITY = "192'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
(* C_M_AXI_WRITE_ISSUING = "192'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
(* C_NUM_ADDR_RANGES = "1" *)
(* C_NUM_MASTER_SLOTS = "6" *)
(* C_NUM_SLAVE_SLOTS = "1" *)
(* C_R_REGISTER = "1" *)
(* C_S_AXI_ARB_PRIORITY = "0" *)
(* C_S_AXI_BASE_ID = "0" *)
(* C_S_AXI_READ_ACCEPTANCE = "1" *)
(* C_S_AXI_SINGLE_THREAD = "1" *)
(* C_S_AXI_THREAD_ID_WIDTH = "0" *)
(* C_S_AXI_WRITE_ACCEPTANCE = "1" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
(* P_ADDR_DECODE = "1" *)
(* P_AXI3 = "1" *)
(* P_AXI4 = "0" *)
(* P_AXILITE = "2" *)
(* P_AXILITE_SIZE = "3'b010" *)
(* P_FAMILY = "zynq" *)
(* P_INCR = "2'b01" *)
(* P_LEN = "8" *)
(* P_LOCK = "1" *)
(* P_M_AXI_ERR_MODE = "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* P_M_AXI_SUPPORTS_READ = "6'b111111" *)
(* P_M_AXI_SUPPORTS_WRITE = "6'b111111" *)
(* P_ONES = "65'b11111111111111111111111111111111111111111111111111111111111111111" *)
(* P_RANGE_CHECK = "1" *)
(* P_S_AXI_BASE_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *)
(* P_S_AXI_HIGH_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *)
(* P_S_AXI_SUPPORTS_READ = "1'b1" *)
(* P_S_AXI_SUPPORTS_WRITE = "1'b1" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar inst
(.aclk(aclk),
.aresetn(aresetn),
.m_axi_araddr(m_axi_araddr),
.m_axi_arburst(NLW_inst_m_axi_arburst_UNCONNECTED[11:0]),
.m_axi_arcache(NLW_inst_m_axi_arcache_UNCONNECTED[23:0]),
.m_axi_arid(NLW_inst_m_axi_arid_UNCONNECTED[5:0]),
.m_axi_arlen(NLW_inst_m_axi_arlen_UNCONNECTED[47:0]),
.m_axi_arlock(NLW_inst_m_axi_arlock_UNCONNECTED[5:0]),
.m_axi_arprot(m_axi_arprot),
.m_axi_arqos(NLW_inst_m_axi_arqos_UNCONNECTED[23:0]),
.m_axi_arready(m_axi_arready),
.m_axi_arregion(NLW_inst_m_axi_arregion_UNCONNECTED[23:0]),
.m_axi_arsize(NLW_inst_m_axi_arsize_UNCONNECTED[17:0]),
.m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[5:0]),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awburst(NLW_inst_m_axi_awburst_UNCONNECTED[11:0]),
.m_axi_awcache(NLW_inst_m_axi_awcache_UNCONNECTED[23:0]),
.m_axi_awid(NLW_inst_m_axi_awid_UNCONNECTED[5:0]),
.m_axi_awlen(NLW_inst_m_axi_awlen_UNCONNECTED[47:0]),
.m_axi_awlock(NLW_inst_m_axi_awlock_UNCONNECTED[5:0]),
.m_axi_awprot(m_axi_awprot),
.m_axi_awqos(NLW_inst_m_axi_awqos_UNCONNECTED[23:0]),
.m_axi_awready(m_axi_awready),
.m_axi_awregion(NLW_inst_m_axi_awregion_UNCONNECTED[23:0]),
.m_axi_awsize(NLW_inst_m_axi_awsize_UNCONNECTED[17:0]),
.m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[5:0]),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rlast({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_ruser({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[5:0]),
.m_axi_wlast(NLW_inst_m_axi_wlast_UNCONNECTED[5:0]),
.m_axi_wready(m_axi_wready),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[5:0]),
.m_axi_wvalid(m_axi_wvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arid(1'b0),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlock(1'b0),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(s_axi_arready),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_aruser(1'b0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awid(1'b0),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlock(1'b0),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(s_axi_awready),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awuser(1'b0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(NLW_inst_s_axi_bid_UNCONNECTED[0]),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(NLW_inst_s_axi_rid_UNCONNECTED[0]),
.s_axi_rlast(NLW_inst_s_axi_rlast_UNCONNECTED[0]),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wid(1'b0),
.s_axi_wlast(1'b1),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wuser(1'b0),
.s_axi_wvalid(s_axi_wvalid));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__A21O_BEHAVIORAL_PP_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__a21o (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21O_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND4_4_V
`define SKY130_FD_SC_LP__NAND4_4_V
/**
* nand4: 4-input NAND.
*
* Verilog wrapper for nand4 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand4_4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand4_4 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND4_4_V
|
// Copyright (C) 1991-2011 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// Quartus II 11.0 Build 157 04/27/2011
///////////////////////////////////////////////////////////////////////////////
//
// MAX IO Atom
//
//////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module max_asynch_io (datain, oe, padio, dataout);
parameter operation_mode = "input";
parameter bus_hold = "false";
parameter open_drain_output = "false";
parameter weak_pull_up = "false";
input datain, oe;
output dataout;
inout padio;
reg prev_value;
reg tmp_padio, tmp_dataout;
reg buf_control;
wire datain_in;
wire oe_in;
buf(datain_in, datain);
buf(oe_in, oe);
tri padio_tmp;
specify
(padio => dataout) = (0,0);
(datain => padio) = (0, 0);
(posedge oe => (padio +: padio_tmp)) = (0, 0);
(negedge oe => (padio +: 1'bz)) = (0, 0);
endspecify
initial
begin
prev_value = 'b1;
tmp_padio = 'bz;
end
always @(datain_in or oe_in or padio)
begin
if (bus_hold == "true" )
begin
buf_control = 'b1;
if (operation_mode == "input")
begin
prev_value = padio;
tmp_dataout = padio;
end
else if ( operation_mode == "output" || operation_mode == "bidir")
begin
if ( oe_in == 1)
begin
if ( open_drain_output == "true" )
begin
if (datain_in == 0)
begin
tmp_padio = 1'b0;
prev_value = 1'b0;
end
else if (datain_in == 1'bx)
begin
tmp_padio = 1'bx;
prev_value = 1'bx;
end
else // 'Z'
begin
if ( padio != 1'bz)
begin
prev_value = padio;
end
end
end // end open_drain_output , true
else
begin
tmp_padio = datain_in;
prev_value = datain_in;
end // end open_drain_output false
end // end oe_in == 1
else if ( oe_in == 0 )
begin
if ( padio !== 1'bz)
begin
prev_value = padio;
if ((padio === 1'bx) && (operation_mode == "output") && (padio_tmp === 1'bx) && (prev_value === 1'bx))
begin
prev_value = 'b0;
end
end
tmp_padio = 'bz;
end
else
begin
begin
tmp_padio = 1'bx;
prev_value = 1'bx;
end
end
if ( operation_mode == "bidir")
tmp_dataout = padio;
else
tmp_dataout = 1'bz;
if ( $realtime <= 1 )
prev_value = 0;
end
end
else // bus hold is false
if (bus_hold == "false")
begin
buf_control = 'b0;
if ( operation_mode == "input")
begin
tmp_dataout = padio;
if (weak_pull_up == "true")
begin
if (tmp_dataout === 1'bz)
tmp_dataout = 1'b1;
end
end
else if (operation_mode == "output" || operation_mode == "bidir")
begin
if ( operation_mode == "bidir")
begin
tmp_dataout = padio;
if (weak_pull_up == "true")
begin
if (tmp_dataout === 1'bz)
tmp_dataout = 1'b1;
end
end
if ( oe_in == 1 )
begin
if ( open_drain_output == "true" )
begin
if (datain_in == 0)
tmp_padio = 1'b0;
else if ( datain_in == 1'bx)
tmp_padio = 1'bx;
else
begin
tmp_padio = 1'bz;
if (weak_pull_up == "true")
begin
if (tmp_padio === 1'bz)
buf_control = 1;
end
end
end
else
begin
if ((datain_in !== 1'b1)&&(datain_in !== 1'b0)&&(datain_in !== 'bx))
tmp_padio = 'bz;
else
tmp_padio = datain_in;
if (weak_pull_up == "true")
begin
if (tmp_padio === 1'bz)
buf_control = 1;
end
end
end
else if ( oe_in == 0 )
begin
tmp_padio = 1'bz;
if (weak_pull_up == "true")
begin
if (tmp_padio === 1'bz)
begin
buf_control = 1;
end
end
end
else
tmp_padio = 1'bx;
end
else
begin
$display ("Error: Invalid operation_mode specified in max io atom!\n");
$display ("Time: %0t Instance: %m", $time);
end
end
end
bufif1 (weak1, weak0) b(padio_tmp, prev_value, buf_control); //weak value
pmos (padio_tmp, tmp_padio, 'b0);
pmos (dataout, tmp_dataout, 'b0);
pmos (padio, padio_tmp, 'b0);
endmodule
module max_io (datain, oe, padio, dataout);
parameter operation_mode = "input";
parameter bus_hold = "false";
parameter open_drain_output = "false";
parameter weak_pull_up = "false";
inout padio;
input datain, oe;
output dataout;
max_asynch_io asynch_inst (datain, oe, padio, dataout);
defparam
asynch_inst.operation_mode = operation_mode,
asynch_inst.bus_hold = bus_hold,
asynch_inst.open_drain_output = open_drain_output,
asynch_inst.weak_pull_up = weak_pull_up;
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// MAX MCELL ATOM
//
//////////////////////////////////////////////////////////////////////////////
// MAX MCELL ASYNCH
`timescale 1 ps/1 ps
module max_asynch_mcell (pterm0, pterm1, pterm2, pterm3, pterm4,
pterm5, fpin, pxor, pexpin, fbkin,
combout, pexpout, regin);
parameter operation_mode = "normal";
parameter pexp_mode = "off";
parameter register_mode = "dff";
input [51:0] pterm0, pterm1, pterm2, pterm3, pterm4, pterm5, pxor;
input pexpin, fbkin, fpin;
output combout, pexpout, regin;
reg icomb, ipexpout, tmp_comb, tmp_fpin;
reg tmp_pterm0, tmp_pterm1, tmp_pterm2;
reg tmp_pterm3, tmp_pterm4, tmp_pexpin;
wire [51:0] ipterm0, ipterm1, ipterm2, ipterm3, ipterm4, ipterm5, ipxor;
wire ipexpin;
wire ifpin;
buf (ipexpin, pexpin);
buf (ifpin, fpin);
buf (ipterm0[0], pterm0[0]);
buf (ipterm0[1], pterm0[1]);
buf (ipterm0[2], pterm0[2]);
buf (ipterm0[3], pterm0[3]);
buf (ipterm0[4], pterm0[4]);
buf (ipterm0[5], pterm0[5]);
buf (ipterm0[6], pterm0[6]);
buf (ipterm0[7], pterm0[7]);
buf (ipterm0[8], pterm0[8]);
buf (ipterm0[9], pterm0[9]);
buf (ipterm0[10], pterm0[10]);
buf (ipterm0[11], pterm0[11]);
buf (ipterm0[12], pterm0[12]);
buf (ipterm0[13], pterm0[13]);
buf (ipterm0[14], pterm0[14]);
buf (ipterm0[15], pterm0[15]);
buf (ipterm0[16], pterm0[16]);
buf (ipterm0[17], pterm0[17]);
buf (ipterm0[18], pterm0[18]);
buf (ipterm0[19], pterm0[19]);
buf (ipterm0[20], pterm0[20]);
buf (ipterm0[21], pterm0[21]);
buf (ipterm0[22], pterm0[22]);
buf (ipterm0[23], pterm0[23]);
buf (ipterm0[24], pterm0[24]);
buf (ipterm0[25], pterm0[25]);
buf (ipterm0[26], pterm0[26]);
buf (ipterm0[27], pterm0[27]);
buf (ipterm0[28], pterm0[28]);
buf (ipterm0[29], pterm0[29]);
buf (ipterm0[30], pterm0[30]);
buf (ipterm0[31], pterm0[31]);
buf (ipterm0[32], pterm0[32]);
buf (ipterm0[33], pterm0[33]);
buf (ipterm0[34], pterm0[34]);
buf (ipterm0[35], pterm0[35]);
buf (ipterm0[36], pterm0[36]);
buf (ipterm0[37], pterm0[37]);
buf (ipterm0[38], pterm0[38]);
buf (ipterm0[39], pterm0[39]);
buf (ipterm0[40], pterm0[40]);
buf (ipterm0[41], pterm0[41]);
buf (ipterm0[42], pterm0[42]);
buf (ipterm0[43], pterm0[43]);
buf (ipterm0[44], pterm0[44]);
buf (ipterm0[45], pterm0[45]);
buf (ipterm0[46], pterm0[46]);
buf (ipterm0[47], pterm0[47]);
buf (ipterm0[48], pterm0[48]);
buf (ipterm0[49], pterm0[49]);
buf (ipterm0[50], pterm0[50]);
buf (ipterm0[51], pterm0[51]);
buf (ipterm1[0], pterm1[0]);
buf (ipterm1[1], pterm1[1]);
buf (ipterm1[2], pterm1[2]);
buf (ipterm1[3], pterm1[3]);
buf (ipterm1[4], pterm1[4]);
buf (ipterm1[5], pterm1[5]);
buf (ipterm1[6], pterm1[6]);
buf (ipterm1[7], pterm1[7]);
buf (ipterm1[8], pterm1[8]);
buf (ipterm1[9], pterm1[9]);
buf (ipterm1[10], pterm1[10]);
buf (ipterm1[11], pterm1[11]);
buf (ipterm1[12], pterm1[12]);
buf (ipterm1[13], pterm1[13]);
buf (ipterm1[14], pterm1[14]);
buf (ipterm1[15], pterm1[15]);
buf (ipterm1[16], pterm1[16]);
buf (ipterm1[17], pterm1[17]);
buf (ipterm1[18], pterm1[18]);
buf (ipterm1[19], pterm1[19]);
buf (ipterm1[20], pterm1[20]);
buf (ipterm1[21], pterm1[21]);
buf (ipterm1[22], pterm1[22]);
buf (ipterm1[23], pterm1[23]);
buf (ipterm1[24], pterm1[24]);
buf (ipterm1[25], pterm1[25]);
buf (ipterm1[26], pterm1[26]);
buf (ipterm1[27], pterm1[27]);
buf (ipterm1[28], pterm1[28]);
buf (ipterm1[29], pterm1[29]);
buf (ipterm1[30], pterm1[30]);
buf (ipterm1[31], pterm1[31]);
buf (ipterm1[32], pterm1[32]);
buf (ipterm1[33], pterm1[33]);
buf (ipterm1[34], pterm1[34]);
buf (ipterm1[35], pterm1[35]);
buf (ipterm1[36], pterm1[36]);
buf (ipterm1[37], pterm1[37]);
buf (ipterm1[38], pterm1[38]);
buf (ipterm1[39], pterm1[39]);
buf (ipterm1[40], pterm1[40]);
buf (ipterm1[41], pterm1[41]);
buf (ipterm1[42], pterm1[42]);
buf (ipterm1[43], pterm1[43]);
buf (ipterm1[44], pterm1[44]);
buf (ipterm1[45], pterm1[45]);
buf (ipterm1[46], pterm1[46]);
buf (ipterm1[47], pterm1[47]);
buf (ipterm1[48], pterm1[48]);
buf (ipterm1[49], pterm1[49]);
buf (ipterm1[50], pterm1[50]);
buf (ipterm1[51], pterm1[51]);
buf (ipterm2[0], pterm2[0]);
buf (ipterm2[1], pterm2[1]);
buf (ipterm2[2], pterm2[2]);
buf (ipterm2[3], pterm2[3]);
buf (ipterm2[4], pterm2[4]);
buf (ipterm2[5], pterm2[5]);
buf (ipterm2[6], pterm2[6]);
buf (ipterm2[7], pterm2[7]);
buf (ipterm2[8], pterm2[8]);
buf (ipterm2[9], pterm2[9]);
buf (ipterm2[10], pterm2[10]);
buf (ipterm2[11], pterm2[11]);
buf (ipterm2[12], pterm2[12]);
buf (ipterm2[13], pterm2[13]);
buf (ipterm2[14], pterm2[14]);
buf (ipterm2[15], pterm2[15]);
buf (ipterm2[16], pterm2[16]);
buf (ipterm2[17], pterm2[17]);
buf (ipterm2[18], pterm2[18]);
buf (ipterm2[19], pterm2[19]);
buf (ipterm2[20], pterm2[20]);
buf (ipterm2[21], pterm2[21]);
buf (ipterm2[22], pterm2[22]);
buf (ipterm2[23], pterm2[23]);
buf (ipterm2[24], pterm2[24]);
buf (ipterm2[25], pterm2[25]);
buf (ipterm2[26], pterm2[26]);
buf (ipterm2[27], pterm2[27]);
buf (ipterm2[28], pterm2[28]);
buf (ipterm2[29], pterm2[29]);
buf (ipterm2[30], pterm2[30]);
buf (ipterm2[31], pterm2[31]);
buf (ipterm2[32], pterm2[32]);
buf (ipterm2[33], pterm2[33]);
buf (ipterm2[34], pterm2[34]);
buf (ipterm2[35], pterm2[35]);
buf (ipterm2[36], pterm2[36]);
buf (ipterm2[37], pterm2[37]);
buf (ipterm2[38], pterm2[38]);
buf (ipterm2[39], pterm2[39]);
buf (ipterm2[40], pterm2[40]);
buf (ipterm2[41], pterm2[41]);
buf (ipterm2[42], pterm2[42]);
buf (ipterm2[43], pterm2[43]);
buf (ipterm2[44], pterm2[44]);
buf (ipterm2[45], pterm2[45]);
buf (ipterm2[46], pterm2[46]);
buf (ipterm2[47], pterm2[47]);
buf (ipterm2[48], pterm2[48]);
buf (ipterm2[49], pterm2[49]);
buf (ipterm2[50], pterm2[50]);
buf (ipterm2[51], pterm2[51]);
buf (ipterm3[0], pterm3[0]);
buf (ipterm3[1], pterm3[1]);
buf (ipterm3[2], pterm3[2]);
buf (ipterm3[3], pterm3[3]);
buf (ipterm3[4], pterm3[4]);
buf (ipterm3[5], pterm3[5]);
buf (ipterm3[6], pterm3[6]);
buf (ipterm3[7], pterm3[7]);
buf (ipterm3[8], pterm3[8]);
buf (ipterm3[9], pterm3[9]);
buf (ipterm3[10], pterm3[10]);
buf (ipterm3[11], pterm3[11]);
buf (ipterm3[12], pterm3[12]);
buf (ipterm3[13], pterm3[13]);
buf (ipterm3[14], pterm3[14]);
buf (ipterm3[15], pterm3[15]);
buf (ipterm3[16], pterm3[16]);
buf (ipterm3[17], pterm3[17]);
buf (ipterm3[18], pterm3[18]);
buf (ipterm3[19], pterm3[19]);
buf (ipterm3[20], pterm3[20]);
buf (ipterm3[21], pterm3[21]);
buf (ipterm3[22], pterm3[22]);
buf (ipterm3[23], pterm3[23]);
buf (ipterm3[24], pterm3[24]);
buf (ipterm3[25], pterm3[25]);
buf (ipterm3[26], pterm3[26]);
buf (ipterm3[27], pterm3[27]);
buf (ipterm3[28], pterm3[28]);
buf (ipterm3[29], pterm3[29]);
buf (ipterm3[30], pterm3[30]);
buf (ipterm3[31], pterm3[31]);
buf (ipterm3[32], pterm3[32]);
buf (ipterm3[33], pterm3[33]);
buf (ipterm3[34], pterm3[34]);
buf (ipterm3[35], pterm3[35]);
buf (ipterm3[36], pterm3[36]);
buf (ipterm3[37], pterm3[37]);
buf (ipterm3[38], pterm3[38]);
buf (ipterm3[39], pterm3[39]);
buf (ipterm3[40], pterm3[40]);
buf (ipterm3[41], pterm3[41]);
buf (ipterm3[42], pterm3[42]);
buf (ipterm3[43], pterm3[43]);
buf (ipterm3[44], pterm3[44]);
buf (ipterm3[45], pterm3[45]);
buf (ipterm3[46], pterm3[46]);
buf (ipterm3[47], pterm3[47]);
buf (ipterm3[48], pterm3[48]);
buf (ipterm3[49], pterm3[49]);
buf (ipterm3[50], pterm3[50]);
buf (ipterm3[51], pterm3[51]);
buf (ipterm4[0], pterm4[0]);
buf (ipterm4[1], pterm4[1]);
buf (ipterm4[2], pterm4[2]);
buf (ipterm4[3], pterm4[3]);
buf (ipterm4[4], pterm4[4]);
buf (ipterm4[5], pterm4[5]);
buf (ipterm4[6], pterm4[6]);
buf (ipterm4[7], pterm4[7]);
buf (ipterm4[8], pterm4[8]);
buf (ipterm4[9], pterm4[9]);
buf (ipterm4[10], pterm4[10]);
buf (ipterm4[11], pterm4[11]);
buf (ipterm4[12], pterm4[12]);
buf (ipterm4[13], pterm4[13]);
buf (ipterm4[14], pterm4[14]);
buf (ipterm4[15], pterm4[15]);
buf (ipterm4[16], pterm4[16]);
buf (ipterm4[17], pterm4[17]);
buf (ipterm4[18], pterm4[18]);
buf (ipterm4[19], pterm4[19]);
buf (ipterm4[20], pterm4[20]);
buf (ipterm4[21], pterm4[21]);
buf (ipterm4[22], pterm4[22]);
buf (ipterm4[23], pterm4[23]);
buf (ipterm4[24], pterm4[24]);
buf (ipterm4[25], pterm4[25]);
buf (ipterm4[26], pterm4[26]);
buf (ipterm4[27], pterm4[27]);
buf (ipterm4[28], pterm4[28]);
buf (ipterm4[29], pterm4[29]);
buf (ipterm4[30], pterm4[30]);
buf (ipterm4[31], pterm4[31]);
buf (ipterm4[32], pterm4[32]);
buf (ipterm4[33], pterm4[33]);
buf (ipterm4[34], pterm4[34]);
buf (ipterm4[35], pterm4[35]);
buf (ipterm4[36], pterm4[36]);
buf (ipterm4[37], pterm4[37]);
buf (ipterm4[38], pterm4[38]);
buf (ipterm4[39], pterm4[39]);
buf (ipterm4[40], pterm4[40]);
buf (ipterm4[41], pterm4[41]);
buf (ipterm4[42], pterm4[42]);
buf (ipterm4[43], pterm4[43]);
buf (ipterm4[44], pterm4[44]);
buf (ipterm4[45], pterm4[45]);
buf (ipterm4[46], pterm4[46]);
buf (ipterm4[47], pterm4[47]);
buf (ipterm4[48], pterm4[48]);
buf (ipterm4[49], pterm4[49]);
buf (ipterm4[50], pterm4[50]);
buf (ipterm4[51], pterm4[51]);
buf (ipterm5[0], pterm5[0]);
buf (ipterm5[1], pterm5[1]);
buf (ipterm5[2], pterm5[2]);
buf (ipterm5[3], pterm5[3]);
buf (ipterm5[4], pterm5[4]);
buf (ipterm5[5], pterm5[5]);
buf (ipterm5[6], pterm5[6]);
buf (ipterm5[7], pterm5[7]);
buf (ipterm5[8], pterm5[8]);
buf (ipterm5[9], pterm5[9]);
buf (ipterm5[10], pterm5[10]);
buf (ipterm5[11], pterm5[11]);
buf (ipterm5[12], pterm5[12]);
buf (ipterm5[13], pterm5[13]);
buf (ipterm5[14], pterm5[14]);
buf (ipterm5[15], pterm5[15]);
buf (ipterm5[16], pterm5[16]);
buf (ipterm5[17], pterm5[17]);
buf (ipterm5[18], pterm5[18]);
buf (ipterm5[19], pterm5[19]);
buf (ipterm5[20], pterm5[20]);
buf (ipterm5[21], pterm5[21]);
buf (ipterm5[22], pterm5[22]);
buf (ipterm5[23], pterm5[23]);
buf (ipterm5[24], pterm5[24]);
buf (ipterm5[25], pterm5[25]);
buf (ipterm5[26], pterm5[26]);
buf (ipterm5[27], pterm5[27]);
buf (ipterm5[28], pterm5[28]);
buf (ipterm5[29], pterm5[29]);
buf (ipterm5[30], pterm5[30]);
buf (ipterm5[31], pterm5[31]);
buf (ipterm5[32], pterm5[32]);
buf (ipterm5[33], pterm5[33]);
buf (ipterm5[34], pterm5[34]);
buf (ipterm5[35], pterm5[35]);
buf (ipterm5[36], pterm5[36]);
buf (ipterm5[37], pterm5[37]);
buf (ipterm5[38], pterm5[38]);
buf (ipterm5[39], pterm5[39]);
buf (ipterm5[40], pterm5[40]);
buf (ipterm5[41], pterm5[41]);
buf (ipterm5[42], pterm5[42]);
buf (ipterm5[43], pterm5[43]);
buf (ipterm5[44], pterm5[44]);
buf (ipterm5[45], pterm5[45]);
buf (ipterm5[46], pterm5[46]);
buf (ipterm5[47], pterm5[47]);
buf (ipterm5[48], pterm5[48]);
buf (ipterm5[49], pterm5[49]);
buf (ipterm5[50], pterm5[50]);
buf (ipterm5[51], pterm5[51]);
buf (ipxor[0], pxor[0]);
buf (ipxor[1], pxor[1]);
buf (ipxor[2], pxor[2]);
buf (ipxor[3], pxor[3]);
buf (ipxor[4], pxor[4]);
buf (ipxor[5], pxor[5]);
buf (ipxor[6], pxor[6]);
buf (ipxor[7], pxor[7]);
buf (ipxor[8], pxor[8]);
buf (ipxor[9], pxor[9]);
buf (ipxor[10], pxor[10]);
buf (ipxor[11], pxor[11]);
buf (ipxor[12], pxor[12]);
buf (ipxor[13], pxor[13]);
buf (ipxor[14], pxor[14]);
buf (ipxor[15], pxor[15]);
buf (ipxor[16], pxor[16]);
buf (ipxor[17], pxor[17]);
buf (ipxor[18], pxor[18]);
buf (ipxor[19], pxor[19]);
buf (ipxor[20], pxor[20]);
buf (ipxor[21], pxor[21]);
buf (ipxor[22], pxor[22]);
buf (ipxor[23], pxor[23]);
buf (ipxor[24], pxor[24]);
buf (ipxor[25], pxor[25]);
buf (ipxor[26], pxor[26]);
buf (ipxor[27], pxor[27]);
buf (ipxor[28], pxor[28]);
buf (ipxor[29], pxor[29]);
buf (ipxor[30], pxor[30]);
buf (ipxor[31], pxor[31]);
buf (ipxor[32], pxor[32]);
buf (ipxor[33], pxor[33]);
buf (ipxor[34], pxor[34]);
buf (ipxor[35], pxor[35]);
buf (ipxor[36], pxor[36]);
buf (ipxor[37], pxor[37]);
buf (ipxor[38], pxor[38]);
buf (ipxor[39], pxor[39]);
buf (ipxor[40], pxor[40]);
buf (ipxor[41], pxor[41]);
buf (ipxor[42], pxor[42]);
buf (ipxor[43], pxor[43]);
buf (ipxor[44], pxor[44]);
buf (ipxor[45], pxor[45]);
buf (ipxor[46], pxor[46]);
buf (ipxor[47], pxor[47]);
buf (ipxor[48], pxor[48]);
buf (ipxor[49], pxor[49]);
buf (ipxor[50], pxor[50]);
buf (ipxor[51], pxor[51]);
specify
(pterm0[0] => combout) = (0, 0) ;
(pterm0[1] => combout) = (0, 0) ;
(pterm0[2] => combout) = (0, 0) ;
(pterm0[3] => combout) = (0, 0) ;
(pterm0[4] => combout) = (0, 0) ;
(pterm0[5] => combout) = (0, 0) ;
(pterm0[6] => combout) = (0, 0) ;
(pterm0[7] => combout) = (0, 0) ;
(pterm0[8] => combout) = (0, 0) ;
(pterm0[9] => combout) = (0, 0) ;
(pterm0[10] => combout) = (0, 0) ;
(pterm0[11] => combout) = (0, 0) ;
(pterm0[12] => combout) = (0, 0) ;
(pterm0[13] => combout) = (0, 0) ;
(pterm0[14] => combout) = (0, 0) ;
(pterm0[15] => combout) = (0, 0) ;
(pterm0[16] => combout) = (0, 0) ;
(pterm0[17] => combout) = (0, 0) ;
(pterm0[18] => combout) = (0, 0) ;
(pterm0[19] => combout) = (0, 0) ;
(pterm0[20] => combout) = (0, 0) ;
(pterm0[21] => combout) = (0, 0) ;
(pterm0[22] => combout) = (0, 0) ;
(pterm0[23] => combout) = (0, 0) ;
(pterm0[24] => combout) = (0, 0) ;
(pterm0[25] => combout) = (0, 0) ;
(pterm0[26] => combout) = (0, 0) ;
(pterm0[27] => combout) = (0, 0) ;
(pterm0[28] => combout) = (0, 0) ;
(pterm0[29] => combout) = (0, 0) ;
(pterm0[30] => combout) = (0, 0) ;
(pterm0[31] => combout) = (0, 0) ;
(pterm0[32] => combout) = (0, 0) ;
(pterm0[33] => combout) = (0, 0) ;
(pterm0[34] => combout) = (0, 0) ;
(pterm0[35] => combout) = (0, 0) ;
(pterm0[36] => combout) = (0, 0) ;
(pterm0[37] => combout) = (0, 0) ;
(pterm0[38] => combout) = (0, 0) ;
(pterm0[39] => combout) = (0, 0) ;
(pterm0[40] => combout) = (0, 0) ;
(pterm0[41] => combout) = (0, 0) ;
(pterm0[42] => combout) = (0, 0) ;
(pterm0[43] => combout) = (0, 0) ;
(pterm0[44] => combout) = (0, 0) ;
(pterm0[45] => combout) = (0, 0) ;
(pterm0[46] => combout) = (0, 0) ;
(pterm0[47] => combout) = (0, 0) ;
(pterm0[48] => combout) = (0, 0) ;
(pterm0[49] => combout) = (0, 0) ;
(pterm0[50] => combout) = (0, 0) ;
(pterm0[51] => combout) = (0, 0) ;
(pterm1[0] => combout) = (0, 0) ;
(pterm1[1] => combout) = (0, 0) ;
(pterm1[2] => combout) = (0, 0) ;
(pterm1[3] => combout) = (0, 0) ;
(pterm1[4] => combout) = (0, 0) ;
(pterm1[5] => combout) = (0, 0) ;
(pterm1[6] => combout) = (0, 0) ;
(pterm1[7] => combout) = (0, 0) ;
(pterm1[8] => combout) = (0, 0) ;
(pterm1[9] => combout) = (0, 0) ;
(pterm1[10] => combout) = (0, 0) ;
(pterm1[11] => combout) = (0, 0) ;
(pterm1[12] => combout) = (0, 0) ;
(pterm1[13] => combout) = (0, 0) ;
(pterm1[14] => combout) = (0, 0) ;
(pterm1[15] => combout) = (0, 0) ;
(pterm1[16] => combout) = (0, 0) ;
(pterm1[17] => combout) = (0, 0) ;
(pterm1[18] => combout) = (0, 0) ;
(pterm1[19] => combout) = (0, 0) ;
(pterm1[20] => combout) = (0, 0) ;
(pterm1[21] => combout) = (0, 0) ;
(pterm1[22] => combout) = (0, 0) ;
(pterm1[23] => combout) = (0, 0) ;
(pterm1[24] => combout) = (0, 0) ;
(pterm1[25] => combout) = (0, 0) ;
(pterm1[26] => combout) = (0, 0) ;
(pterm1[27] => combout) = (0, 0) ;
(pterm1[28] => combout) = (0, 0) ;
(pterm1[29] => combout) = (0, 0) ;
(pterm1[30] => combout) = (0, 0) ;
(pterm1[31] => combout) = (0, 0) ;
(pterm1[32] => combout) = (0, 0) ;
(pterm1[33] => combout) = (0, 0) ;
(pterm1[34] => combout) = (0, 0) ;
(pterm1[35] => combout) = (0, 0) ;
(pterm1[36] => combout) = (0, 0) ;
(pterm1[37] => combout) = (0, 0) ;
(pterm1[38] => combout) = (0, 0) ;
(pterm1[39] => combout) = (0, 0) ;
(pterm1[40] => combout) = (0, 0) ;
(pterm1[41] => combout) = (0, 0) ;
(pterm1[42] => combout) = (0, 0) ;
(pterm1[43] => combout) = (0, 0) ;
(pterm1[44] => combout) = (0, 0) ;
(pterm1[45] => combout) = (0, 0) ;
(pterm1[46] => combout) = (0, 0) ;
(pterm1[47] => combout) = (0, 0) ;
(pterm1[48] => combout) = (0, 0) ;
(pterm1[49] => combout) = (0, 0) ;
(pterm1[50] => combout) = (0, 0) ;
(pterm1[51] => combout) = (0, 0) ;
(pterm2[0] => combout) = (0, 0) ;
(pterm2[1] => combout) = (0, 0) ;
(pterm2[2] => combout) = (0, 0) ;
(pterm2[3] => combout) = (0, 0) ;
(pterm2[4] => combout) = (0, 0) ;
(pterm2[5] => combout) = (0, 0) ;
(pterm2[6] => combout) = (0, 0) ;
(pterm2[7] => combout) = (0, 0) ;
(pterm2[8] => combout) = (0, 0) ;
(pterm2[9] => combout) = (0, 0) ;
(pterm2[10] => combout) = (0, 0) ;
(pterm2[11] => combout) = (0, 0) ;
(pterm2[12] => combout) = (0, 0) ;
(pterm2[13] => combout) = (0, 0) ;
(pterm2[14] => combout) = (0, 0) ;
(pterm2[15] => combout) = (0, 0) ;
(pterm2[16] => combout) = (0, 0) ;
(pterm2[17] => combout) = (0, 0) ;
(pterm2[18] => combout) = (0, 0) ;
(pterm2[19] => combout) = (0, 0) ;
(pterm2[20] => combout) = (0, 0) ;
(pterm2[21] => combout) = (0, 0) ;
(pterm2[22] => combout) = (0, 0) ;
(pterm2[23] => combout) = (0, 0) ;
(pterm2[24] => combout) = (0, 0) ;
(pterm2[25] => combout) = (0, 0) ;
(pterm2[26] => combout) = (0, 0) ;
(pterm2[27] => combout) = (0, 0) ;
(pterm2[28] => combout) = (0, 0) ;
(pterm2[29] => combout) = (0, 0) ;
(pterm2[30] => combout) = (0, 0) ;
(pterm2[31] => combout) = (0, 0) ;
(pterm2[32] => combout) = (0, 0) ;
(pterm2[33] => combout) = (0, 0) ;
(pterm2[34] => combout) = (0, 0) ;
(pterm2[35] => combout) = (0, 0) ;
(pterm2[36] => combout) = (0, 0) ;
(pterm2[37] => combout) = (0, 0) ;
(pterm2[38] => combout) = (0, 0) ;
(pterm2[39] => combout) = (0, 0) ;
(pterm2[40] => combout) = (0, 0) ;
(pterm2[41] => combout) = (0, 0) ;
(pterm2[42] => combout) = (0, 0) ;
(pterm2[43] => combout) = (0, 0) ;
(pterm2[44] => combout) = (0, 0) ;
(pterm2[45] => combout) = (0, 0) ;
(pterm2[46] => combout) = (0, 0) ;
(pterm2[47] => combout) = (0, 0) ;
(pterm2[48] => combout) = (0, 0) ;
(pterm2[49] => combout) = (0, 0) ;
(pterm2[50] => combout) = (0, 0) ;
(pterm2[51] => combout) = (0, 0) ;
(pterm3[0] => combout) = (0, 0) ;
(pterm3[1] => combout) = (0, 0) ;
(pterm3[2] => combout) = (0, 0) ;
(pterm3[3] => combout) = (0, 0) ;
(pterm3[4] => combout) = (0, 0) ;
(pterm3[5] => combout) = (0, 0) ;
(pterm3[6] => combout) = (0, 0) ;
(pterm3[7] => combout) = (0, 0) ;
(pterm3[8] => combout) = (0, 0) ;
(pterm3[9] => combout) = (0, 0) ;
(pterm3[10] => combout) = (0, 0) ;
(pterm3[11] => combout) = (0, 0) ;
(pterm3[12] => combout) = (0, 0) ;
(pterm3[13] => combout) = (0, 0) ;
(pterm3[14] => combout) = (0, 0) ;
(pterm3[15] => combout) = (0, 0) ;
(pterm3[16] => combout) = (0, 0) ;
(pterm3[17] => combout) = (0, 0) ;
(pterm3[18] => combout) = (0, 0) ;
(pterm3[19] => combout) = (0, 0) ;
(pterm3[20] => combout) = (0, 0) ;
(pterm3[21] => combout) = (0, 0) ;
(pterm3[22] => combout) = (0, 0) ;
(pterm3[23] => combout) = (0, 0) ;
(pterm3[24] => combout) = (0, 0) ;
(pterm3[25] => combout) = (0, 0) ;
(pterm3[26] => combout) = (0, 0) ;
(pterm3[27] => combout) = (0, 0) ;
(pterm3[28] => combout) = (0, 0) ;
(pterm3[29] => combout) = (0, 0) ;
(pterm3[30] => combout) = (0, 0) ;
(pterm3[31] => combout) = (0, 0) ;
(pterm3[32] => combout) = (0, 0) ;
(pterm3[33] => combout) = (0, 0) ;
(pterm3[34] => combout) = (0, 0) ;
(pterm3[35] => combout) = (0, 0) ;
(pterm3[36] => combout) = (0, 0) ;
(pterm3[37] => combout) = (0, 0) ;
(pterm3[38] => combout) = (0, 0) ;
(pterm3[39] => combout) = (0, 0) ;
(pterm3[40] => combout) = (0, 0) ;
(pterm3[41] => combout) = (0, 0) ;
(pterm3[42] => combout) = (0, 0) ;
(pterm3[43] => combout) = (0, 0) ;
(pterm3[44] => combout) = (0, 0) ;
(pterm3[45] => combout) = (0, 0) ;
(pterm3[46] => combout) = (0, 0) ;
(pterm3[47] => combout) = (0, 0) ;
(pterm3[48] => combout) = (0, 0) ;
(pterm3[49] => combout) = (0, 0) ;
(pterm3[50] => combout) = (0, 0) ;
(pterm3[51] => combout) = (0, 0) ;
(pterm4[0] => combout) = (0, 0) ;
(pterm4[1] => combout) = (0, 0) ;
(pterm4[2] => combout) = (0, 0) ;
(pterm4[3] => combout) = (0, 0) ;
(pterm4[4] => combout) = (0, 0) ;
(pterm4[5] => combout) = (0, 0) ;
(pterm4[6] => combout) = (0, 0) ;
(pterm4[7] => combout) = (0, 0) ;
(pterm4[8] => combout) = (0, 0) ;
(pterm4[9] => combout) = (0, 0) ;
(pterm4[10] => combout) = (0, 0) ;
(pterm4[11] => combout) = (0, 0) ;
(pterm4[12] => combout) = (0, 0) ;
(pterm4[13] => combout) = (0, 0) ;
(pterm4[14] => combout) = (0, 0) ;
(pterm4[15] => combout) = (0, 0) ;
(pterm4[16] => combout) = (0, 0) ;
(pterm4[17] => combout) = (0, 0) ;
(pterm4[18] => combout) = (0, 0) ;
(pterm4[19] => combout) = (0, 0) ;
(pterm4[20] => combout) = (0, 0) ;
(pterm4[21] => combout) = (0, 0) ;
(pterm4[22] => combout) = (0, 0) ;
(pterm4[23] => combout) = (0, 0) ;
(pterm4[24] => combout) = (0, 0) ;
(pterm4[25] => combout) = (0, 0) ;
(pterm4[26] => combout) = (0, 0) ;
(pterm4[27] => combout) = (0, 0) ;
(pterm4[28] => combout) = (0, 0) ;
(pterm4[29] => combout) = (0, 0) ;
(pterm4[30] => combout) = (0, 0) ;
(pterm4[31] => combout) = (0, 0) ;
(pterm4[32] => combout) = (0, 0) ;
(pterm4[33] => combout) = (0, 0) ;
(pterm4[34] => combout) = (0, 0) ;
(pterm4[35] => combout) = (0, 0) ;
(pterm4[36] => combout) = (0, 0) ;
(pterm4[37] => combout) = (0, 0) ;
(pterm4[38] => combout) = (0, 0) ;
(pterm4[39] => combout) = (0, 0) ;
(pterm4[40] => combout) = (0, 0) ;
(pterm4[41] => combout) = (0, 0) ;
(pterm4[42] => combout) = (0, 0) ;
(pterm4[43] => combout) = (0, 0) ;
(pterm4[44] => combout) = (0, 0) ;
(pterm4[45] => combout) = (0, 0) ;
(pterm4[46] => combout) = (0, 0) ;
(pterm4[47] => combout) = (0, 0) ;
(pterm4[48] => combout) = (0, 0) ;
(pterm4[49] => combout) = (0, 0) ;
(pterm4[50] => combout) = (0, 0) ;
(pterm4[51] => combout) = (0, 0) ;
(pterm5[0] => combout) = (0, 0) ;
(pterm5[1] => combout) = (0, 0) ;
(pterm5[2] => combout) = (0, 0) ;
(pterm5[3] => combout) = (0, 0) ;
(pterm5[4] => combout) = (0, 0) ;
(pterm5[5] => combout) = (0, 0) ;
(pterm5[6] => combout) = (0, 0) ;
(pterm5[7] => combout) = (0, 0) ;
(pterm5[8] => combout) = (0, 0) ;
(pterm5[9] => combout) = (0, 0) ;
(pterm5[10] => combout) = (0, 0) ;
(pterm5[11] => combout) = (0, 0) ;
(pterm5[12] => combout) = (0, 0) ;
(pterm5[13] => combout) = (0, 0) ;
(pterm5[14] => combout) = (0, 0) ;
(pterm5[15] => combout) = (0, 0) ;
(pterm5[16] => combout) = (0, 0) ;
(pterm5[17] => combout) = (0, 0) ;
(pterm5[18] => combout) = (0, 0) ;
(pterm5[19] => combout) = (0, 0) ;
(pterm5[20] => combout) = (0, 0) ;
(pterm5[21] => combout) = (0, 0) ;
(pterm5[22] => combout) = (0, 0) ;
(pterm5[23] => combout) = (0, 0) ;
(pterm5[24] => combout) = (0, 0) ;
(pterm5[25] => combout) = (0, 0) ;
(pterm5[26] => combout) = (0, 0) ;
(pterm5[27] => combout) = (0, 0) ;
(pterm5[28] => combout) = (0, 0) ;
(pterm5[29] => combout) = (0, 0) ;
(pterm5[30] => combout) = (0, 0) ;
(pterm5[31] => combout) = (0, 0) ;
(pterm5[32] => combout) = (0, 0) ;
(pterm5[33] => combout) = (0, 0) ;
(pterm5[34] => combout) = (0, 0) ;
(pterm5[35] => combout) = (0, 0) ;
(pterm5[36] => combout) = (0, 0) ;
(pterm5[37] => combout) = (0, 0) ;
(pterm5[38] => combout) = (0, 0) ;
(pterm5[39] => combout) = (0, 0) ;
(pterm5[40] => combout) = (0, 0) ;
(pterm5[41] => combout) = (0, 0) ;
(pterm5[42] => combout) = (0, 0) ;
(pterm5[43] => combout) = (0, 0) ;
(pterm5[44] => combout) = (0, 0) ;
(pterm5[45] => combout) = (0, 0) ;
(pterm5[46] => combout) = (0, 0) ;
(pterm5[47] => combout) = (0, 0) ;
(pterm5[48] => combout) = (0, 0) ;
(pterm5[49] => combout) = (0, 0) ;
(pterm5[50] => combout) = (0, 0) ;
(pterm5[51] => combout) = (0, 0) ;
(pxor[0] => combout) = (0, 0) ;
(pxor[1] => combout) = (0, 0) ;
(pxor[2] => combout) = (0, 0) ;
(pxor[3] => combout) = (0, 0) ;
(pxor[4] => combout) = (0, 0) ;
(pxor[5] => combout) = (0, 0) ;
(pxor[6] => combout) = (0, 0) ;
(pxor[7] => combout) = (0, 0) ;
(pxor[8] => combout) = (0, 0) ;
(pxor[9] => combout) = (0, 0) ;
(pxor[10] => combout) = (0, 0) ;
(pxor[11] => combout) = (0, 0) ;
(pxor[12] => combout) = (0, 0) ;
(pxor[13] => combout) = (0, 0) ;
(pxor[14] => combout) = (0, 0) ;
(pxor[15] => combout) = (0, 0) ;
(pxor[16] => combout) = (0, 0) ;
(pxor[17] => combout) = (0, 0) ;
(pxor[18] => combout) = (0, 0) ;
(pxor[19] => combout) = (0, 0) ;
(pxor[20] => combout) = (0, 0) ;
(pxor[21] => combout) = (0, 0) ;
(pxor[22] => combout) = (0, 0) ;
(pxor[23] => combout) = (0, 0) ;
(pxor[24] => combout) = (0, 0) ;
(pxor[25] => combout) = (0, 0) ;
(pxor[26] => combout) = (0, 0) ;
(pxor[27] => combout) = (0, 0) ;
(pxor[28] => combout) = (0, 0) ;
(pxor[29] => combout) = (0, 0) ;
(pxor[30] => combout) = (0, 0) ;
(pxor[31] => combout) = (0, 0) ;
(pxor[32] => combout) = (0, 0) ;
(pxor[33] => combout) = (0, 0) ;
(pxor[34] => combout) = (0, 0) ;
(pxor[35] => combout) = (0, 0) ;
(pxor[36] => combout) = (0, 0) ;
(pxor[37] => combout) = (0, 0) ;
(pxor[38] => combout) = (0, 0) ;
(pxor[39] => combout) = (0, 0) ;
(pxor[40] => combout) = (0, 0) ;
(pxor[41] => combout) = (0, 0) ;
(pxor[42] => combout) = (0, 0) ;
(pxor[43] => combout) = (0, 0) ;
(pxor[44] => combout) = (0, 0) ;
(pxor[45] => combout) = (0, 0) ;
(pxor[46] => combout) = (0, 0) ;
(pxor[47] => combout) = (0, 0) ;
(pxor[48] => combout) = (0, 0) ;
(pxor[49] => combout) = (0, 0) ;
(pxor[50] => combout) = (0, 0) ;
(pxor[51] => combout) = (0, 0) ;
(pexpin => combout) = (0, 0) ;
(pterm0[0] => pexpout) = (0, 0) ;
(pterm0[1] => pexpout) = (0, 0) ;
(pterm0[2] => pexpout) = (0, 0) ;
(pterm0[3] => pexpout) = (0, 0) ;
(pterm0[4] => pexpout) = (0, 0) ;
(pterm0[5] => pexpout) = (0, 0) ;
(pterm0[6] => pexpout) = (0, 0) ;
(pterm0[7] => pexpout) = (0, 0) ;
(pterm0[8] => pexpout) = (0, 0) ;
(pterm0[9] => pexpout) = (0, 0) ;
(pterm0[10] => pexpout) = (0, 0) ;
(pterm0[11] => pexpout) = (0, 0) ;
(pterm0[12] => pexpout) = (0, 0) ;
(pterm0[13] => pexpout) = (0, 0) ;
(pterm0[14] => pexpout) = (0, 0) ;
(pterm0[15] => pexpout) = (0, 0) ;
(pterm0[16] => pexpout) = (0, 0) ;
(pterm0[17] => pexpout) = (0, 0) ;
(pterm0[18] => pexpout) = (0, 0) ;
(pterm0[19] => pexpout) = (0, 0) ;
(pterm0[20] => pexpout) = (0, 0) ;
(pterm0[21] => pexpout) = (0, 0) ;
(pterm0[22] => pexpout) = (0, 0) ;
(pterm0[23] => pexpout) = (0, 0) ;
(pterm0[24] => pexpout) = (0, 0) ;
(pterm0[25] => pexpout) = (0, 0) ;
(pterm0[26] => pexpout) = (0, 0) ;
(pterm0[27] => pexpout) = (0, 0) ;
(pterm0[28] => pexpout) = (0, 0) ;
(pterm0[29] => pexpout) = (0, 0) ;
(pterm0[30] => pexpout) = (0, 0) ;
(pterm0[31] => pexpout) = (0, 0) ;
(pterm0[32] => pexpout) = (0, 0) ;
(pterm0[33] => pexpout) = (0, 0) ;
(pterm0[34] => pexpout) = (0, 0) ;
(pterm0[35] => pexpout) = (0, 0) ;
(pterm0[36] => pexpout) = (0, 0) ;
(pterm0[37] => pexpout) = (0, 0) ;
(pterm0[38] => pexpout) = (0, 0) ;
(pterm0[39] => pexpout) = (0, 0) ;
(pterm0[40] => pexpout) = (0, 0) ;
(pterm0[41] => pexpout) = (0, 0) ;
(pterm0[42] => pexpout) = (0, 0) ;
(pterm0[43] => pexpout) = (0, 0) ;
(pterm0[44] => pexpout) = (0, 0) ;
(pterm0[45] => pexpout) = (0, 0) ;
(pterm0[46] => pexpout) = (0, 0) ;
(pterm0[47] => pexpout) = (0, 0) ;
(pterm0[48] => pexpout) = (0, 0) ;
(pterm0[49] => pexpout) = (0, 0) ;
(pterm0[50] => pexpout) = (0, 0) ;
(pterm0[51] => pexpout) = (0, 0) ;
(pterm1[0] => pexpout) = (0, 0) ;
(pterm1[1] => pexpout) = (0, 0) ;
(pterm1[2] => pexpout) = (0, 0) ;
(pterm1[3] => pexpout) = (0, 0) ;
(pterm1[4] => pexpout) = (0, 0) ;
(pterm1[5] => pexpout) = (0, 0) ;
(pterm1[6] => pexpout) = (0, 0) ;
(pterm1[7] => pexpout) = (0, 0) ;
(pterm1[8] => pexpout) = (0, 0) ;
(pterm1[9] => pexpout) = (0, 0) ;
(pterm1[10] => pexpout) = (0, 0) ;
(pterm1[11] => pexpout) = (0, 0) ;
(pterm1[12] => pexpout) = (0, 0) ;
(pterm1[13] => pexpout) = (0, 0) ;
(pterm1[14] => pexpout) = (0, 0) ;
(pterm1[15] => pexpout) = (0, 0) ;
(pterm1[16] => pexpout) = (0, 0) ;
(pterm1[17] => pexpout) = (0, 0) ;
(pterm1[18] => pexpout) = (0, 0) ;
(pterm1[19] => pexpout) = (0, 0) ;
(pterm1[20] => pexpout) = (0, 0) ;
(pterm1[21] => pexpout) = (0, 0) ;
(pterm1[22] => pexpout) = (0, 0) ;
(pterm1[23] => pexpout) = (0, 0) ;
(pterm1[24] => pexpout) = (0, 0) ;
(pterm1[25] => pexpout) = (0, 0) ;
(pterm1[26] => pexpout) = (0, 0) ;
(pterm1[27] => pexpout) = (0, 0) ;
(pterm1[28] => pexpout) = (0, 0) ;
(pterm1[29] => pexpout) = (0, 0) ;
(pterm1[30] => pexpout) = (0, 0) ;
(pterm1[31] => pexpout) = (0, 0) ;
(pterm1[32] => pexpout) = (0, 0) ;
(pterm1[33] => pexpout) = (0, 0) ;
(pterm1[34] => pexpout) = (0, 0) ;
(pterm1[35] => pexpout) = (0, 0) ;
(pterm1[36] => pexpout) = (0, 0) ;
(pterm1[37] => pexpout) = (0, 0) ;
(pterm1[38] => pexpout) = (0, 0) ;
(pterm1[39] => pexpout) = (0, 0) ;
(pterm1[40] => pexpout) = (0, 0) ;
(pterm1[41] => pexpout) = (0, 0) ;
(pterm1[42] => pexpout) = (0, 0) ;
(pterm1[43] => pexpout) = (0, 0) ;
(pterm1[44] => pexpout) = (0, 0) ;
(pterm1[45] => pexpout) = (0, 0) ;
(pterm1[46] => pexpout) = (0, 0) ;
(pterm1[47] => pexpout) = (0, 0) ;
(pterm1[48] => pexpout) = (0, 0) ;
(pterm1[49] => pexpout) = (0, 0) ;
(pterm1[50] => pexpout) = (0, 0) ;
(pterm1[51] => pexpout) = (0, 0) ;
(pterm2[0] => pexpout) = (0, 0) ;
(pterm2[1] => pexpout) = (0, 0) ;
(pterm2[2] => pexpout) = (0, 0) ;
(pterm2[3] => pexpout) = (0, 0) ;
(pterm2[4] => pexpout) = (0, 0) ;
(pterm2[5] => pexpout) = (0, 0) ;
(pterm2[6] => pexpout) = (0, 0) ;
(pterm2[7] => pexpout) = (0, 0) ;
(pterm2[8] => pexpout) = (0, 0) ;
(pterm2[9] => pexpout) = (0, 0) ;
(pterm2[10] => pexpout) = (0, 0) ;
(pterm2[11] => pexpout) = (0, 0) ;
(pterm2[12] => pexpout) = (0, 0) ;
(pterm2[13] => pexpout) = (0, 0) ;
(pterm2[14] => pexpout) = (0, 0) ;
(pterm2[15] => pexpout) = (0, 0) ;
(pterm2[16] => pexpout) = (0, 0) ;
(pterm2[17] => pexpout) = (0, 0) ;
(pterm2[18] => pexpout) = (0, 0) ;
(pterm2[19] => pexpout) = (0, 0) ;
(pterm2[20] => pexpout) = (0, 0) ;
(pterm2[21] => pexpout) = (0, 0) ;
(pterm2[22] => pexpout) = (0, 0) ;
(pterm2[23] => pexpout) = (0, 0) ;
(pterm2[24] => pexpout) = (0, 0) ;
(pterm2[25] => pexpout) = (0, 0) ;
(pterm2[26] => pexpout) = (0, 0) ;
(pterm2[27] => pexpout) = (0, 0) ;
(pterm2[28] => pexpout) = (0, 0) ;
(pterm2[29] => pexpout) = (0, 0) ;
(pterm2[30] => pexpout) = (0, 0) ;
(pterm2[31] => pexpout) = (0, 0) ;
(pterm2[32] => pexpout) = (0, 0) ;
(pterm2[33] => pexpout) = (0, 0) ;
(pterm2[34] => pexpout) = (0, 0) ;
(pterm2[35] => pexpout) = (0, 0) ;
(pterm2[36] => pexpout) = (0, 0) ;
(pterm2[37] => pexpout) = (0, 0) ;
(pterm2[38] => pexpout) = (0, 0) ;
(pterm2[39] => pexpout) = (0, 0) ;
(pterm2[40] => pexpout) = (0, 0) ;
(pterm2[41] => pexpout) = (0, 0) ;
(pterm2[42] => pexpout) = (0, 0) ;
(pterm2[43] => pexpout) = (0, 0) ;
(pterm2[44] => pexpout) = (0, 0) ;
(pterm2[45] => pexpout) = (0, 0) ;
(pterm2[46] => pexpout) = (0, 0) ;
(pterm2[47] => pexpout) = (0, 0) ;
(pterm2[48] => pexpout) = (0, 0) ;
(pterm2[49] => pexpout) = (0, 0) ;
(pterm2[50] => pexpout) = (0, 0) ;
(pterm2[51] => pexpout) = (0, 0) ;
(pterm3[0] => pexpout) = (0, 0) ;
(pterm3[1] => pexpout) = (0, 0) ;
(pterm3[2] => pexpout) = (0, 0) ;
(pterm3[3] => pexpout) = (0, 0) ;
(pterm3[4] => pexpout) = (0, 0) ;
(pterm3[5] => pexpout) = (0, 0) ;
(pterm3[6] => pexpout) = (0, 0) ;
(pterm3[7] => pexpout) = (0, 0) ;
(pterm3[8] => pexpout) = (0, 0) ;
(pterm3[9] => pexpout) = (0, 0) ;
(pterm3[10] => pexpout) = (0, 0) ;
(pterm3[11] => pexpout) = (0, 0) ;
(pterm3[12] => pexpout) = (0, 0) ;
(pterm3[13] => pexpout) = (0, 0) ;
(pterm3[14] => pexpout) = (0, 0) ;
(pterm3[15] => pexpout) = (0, 0) ;
(pterm3[16] => pexpout) = (0, 0) ;
(pterm3[17] => pexpout) = (0, 0) ;
(pterm3[18] => pexpout) = (0, 0) ;
(pterm3[19] => pexpout) = (0, 0) ;
(pterm3[20] => pexpout) = (0, 0) ;
(pterm3[21] => pexpout) = (0, 0) ;
(pterm3[22] => pexpout) = (0, 0) ;
(pterm3[23] => pexpout) = (0, 0) ;
(pterm3[24] => pexpout) = (0, 0) ;
(pterm3[25] => pexpout) = (0, 0) ;
(pterm3[26] => pexpout) = (0, 0) ;
(pterm3[27] => pexpout) = (0, 0) ;
(pterm3[28] => pexpout) = (0, 0) ;
(pterm3[29] => pexpout) = (0, 0) ;
(pterm3[30] => pexpout) = (0, 0) ;
(pterm3[31] => pexpout) = (0, 0) ;
(pterm3[32] => pexpout) = (0, 0) ;
(pterm3[33] => pexpout) = (0, 0) ;
(pterm3[34] => pexpout) = (0, 0) ;
(pterm3[35] => pexpout) = (0, 0) ;
(pterm3[36] => pexpout) = (0, 0) ;
(pterm3[37] => pexpout) = (0, 0) ;
(pterm3[38] => pexpout) = (0, 0) ;
(pterm3[39] => pexpout) = (0, 0) ;
(pterm3[40] => pexpout) = (0, 0) ;
(pterm3[41] => pexpout) = (0, 0) ;
(pterm3[42] => pexpout) = (0, 0) ;
(pterm3[43] => pexpout) = (0, 0) ;
(pterm3[44] => pexpout) = (0, 0) ;
(pterm3[45] => pexpout) = (0, 0) ;
(pterm3[46] => pexpout) = (0, 0) ;
(pterm3[47] => pexpout) = (0, 0) ;
(pterm3[48] => pexpout) = (0, 0) ;
(pterm3[49] => pexpout) = (0, 0) ;
(pterm3[50] => pexpout) = (0, 0) ;
(pterm3[51] => pexpout) = (0, 0) ;
(pterm4[0] => pexpout) = (0, 0) ;
(pterm4[1] => pexpout) = (0, 0) ;
(pterm4[2] => pexpout) = (0, 0) ;
(pterm4[3] => pexpout) = (0, 0) ;
(pterm4[4] => pexpout) = (0, 0) ;
(pterm4[5] => pexpout) = (0, 0) ;
(pterm4[6] => pexpout) = (0, 0) ;
(pterm4[7] => pexpout) = (0, 0) ;
(pterm4[8] => pexpout) = (0, 0) ;
(pterm4[9] => pexpout) = (0, 0) ;
(pterm4[10] => pexpout) = (0, 0) ;
(pterm4[11] => pexpout) = (0, 0) ;
(pterm4[12] => pexpout) = (0, 0) ;
(pterm4[13] => pexpout) = (0, 0) ;
(pterm4[14] => pexpout) = (0, 0) ;
(pterm4[15] => pexpout) = (0, 0) ;
(pterm4[16] => pexpout) = (0, 0) ;
(pterm4[17] => pexpout) = (0, 0) ;
(pterm4[18] => pexpout) = (0, 0) ;
(pterm4[19] => pexpout) = (0, 0) ;
(pterm4[20] => pexpout) = (0, 0) ;
(pterm4[21] => pexpout) = (0, 0) ;
(pterm4[22] => pexpout) = (0, 0) ;
(pterm4[23] => pexpout) = (0, 0) ;
(pterm4[24] => pexpout) = (0, 0) ;
(pterm4[25] => pexpout) = (0, 0) ;
(pterm4[26] => pexpout) = (0, 0) ;
(pterm4[27] => pexpout) = (0, 0) ;
(pterm4[28] => pexpout) = (0, 0) ;
(pterm4[29] => pexpout) = (0, 0) ;
(pterm4[30] => pexpout) = (0, 0) ;
(pterm4[31] => pexpout) = (0, 0) ;
(pterm4[32] => pexpout) = (0, 0) ;
(pterm4[33] => pexpout) = (0, 0) ;
(pterm4[34] => pexpout) = (0, 0) ;
(pterm4[35] => pexpout) = (0, 0) ;
(pterm4[36] => pexpout) = (0, 0) ;
(pterm4[37] => pexpout) = (0, 0) ;
(pterm4[38] => pexpout) = (0, 0) ;
(pterm4[39] => pexpout) = (0, 0) ;
(pterm4[40] => pexpout) = (0, 0) ;
(pterm4[41] => pexpout) = (0, 0) ;
(pterm4[42] => pexpout) = (0, 0) ;
(pterm4[43] => pexpout) = (0, 0) ;
(pterm4[44] => pexpout) = (0, 0) ;
(pterm4[45] => pexpout) = (0, 0) ;
(pterm4[46] => pexpout) = (0, 0) ;
(pterm4[47] => pexpout) = (0, 0) ;
(pterm4[48] => pexpout) = (0, 0) ;
(pterm4[49] => pexpout) = (0, 0) ;
(pterm4[50] => pexpout) = (0, 0) ;
(pterm4[51] => pexpout) = (0, 0) ;
(pterm5[0] => pexpout) = (0, 0) ;
(pterm5[1] => pexpout) = (0, 0) ;
(pterm5[2] => pexpout) = (0, 0) ;
(pterm5[3] => pexpout) = (0, 0) ;
(pterm5[4] => pexpout) = (0, 0) ;
(pterm5[5] => pexpout) = (0, 0) ;
(pterm5[6] => pexpout) = (0, 0) ;
(pterm5[7] => pexpout) = (0, 0) ;
(pterm5[8] => pexpout) = (0, 0) ;
(pterm5[9] => pexpout) = (0, 0) ;
(pterm5[10] => pexpout) = (0, 0) ;
(pterm5[11] => pexpout) = (0, 0) ;
(pterm5[12] => pexpout) = (0, 0) ;
(pterm5[13] => pexpout) = (0, 0) ;
(pterm5[14] => pexpout) = (0, 0) ;
(pterm5[15] => pexpout) = (0, 0) ;
(pterm5[16] => pexpout) = (0, 0) ;
(pterm5[17] => pexpout) = (0, 0) ;
(pterm5[18] => pexpout) = (0, 0) ;
(pterm5[19] => pexpout) = (0, 0) ;
(pterm5[20] => pexpout) = (0, 0) ;
(pterm5[21] => pexpout) = (0, 0) ;
(pterm5[22] => pexpout) = (0, 0) ;
(pterm5[23] => pexpout) = (0, 0) ;
(pterm5[24] => pexpout) = (0, 0) ;
(pterm5[25] => pexpout) = (0, 0) ;
(pterm5[26] => pexpout) = (0, 0) ;
(pterm5[27] => pexpout) = (0, 0) ;
(pterm5[28] => pexpout) = (0, 0) ;
(pterm5[29] => pexpout) = (0, 0) ;
(pterm5[30] => pexpout) = (0, 0) ;
(pterm5[31] => pexpout) = (0, 0) ;
(pterm5[32] => pexpout) = (0, 0) ;
(pterm5[33] => pexpout) = (0, 0) ;
(pterm5[34] => pexpout) = (0, 0) ;
(pterm5[35] => pexpout) = (0, 0) ;
(pterm5[36] => pexpout) = (0, 0) ;
(pterm5[37] => pexpout) = (0, 0) ;
(pterm5[38] => pexpout) = (0, 0) ;
(pterm5[39] => pexpout) = (0, 0) ;
(pterm5[40] => pexpout) = (0, 0) ;
(pterm5[41] => pexpout) = (0, 0) ;
(pterm5[42] => pexpout) = (0, 0) ;
(pterm5[43] => pexpout) = (0, 0) ;
(pterm5[44] => pexpout) = (0, 0) ;
(pterm5[45] => pexpout) = (0, 0) ;
(pterm5[46] => pexpout) = (0, 0) ;
(pterm5[47] => pexpout) = (0, 0) ;
(pterm5[48] => pexpout) = (0, 0) ;
(pterm5[49] => pexpout) = (0, 0) ;
(pterm5[50] => pexpout) = (0, 0) ;
(pterm5[51] => pexpout) = (0, 0) ;
(pexpin => pexpout) = (0, 0) ;
(pterm0[0] => regin) = (0, 0) ;
(pterm0[1] => regin) = (0, 0) ;
(pterm0[2] => regin) = (0, 0) ;
(pterm0[3] => regin) = (0, 0) ;
(pterm0[4] => regin) = (0, 0) ;
(pterm0[5] => regin) = (0, 0) ;
(pterm0[6] => regin) = (0, 0) ;
(pterm0[7] => regin) = (0, 0) ;
(pterm0[8] => regin) = (0, 0) ;
(pterm0[9] => regin) = (0, 0) ;
(pterm0[10] => regin) = (0, 0) ;
(pterm0[11] => regin) = (0, 0) ;
(pterm0[12] => regin) = (0, 0) ;
(pterm0[13] => regin) = (0, 0) ;
(pterm0[14] => regin) = (0, 0) ;
(pterm0[15] => regin) = (0, 0) ;
(pterm0[16] => regin) = (0, 0) ;
(pterm0[17] => regin) = (0, 0) ;
(pterm0[18] => regin) = (0, 0) ;
(pterm0[19] => regin) = (0, 0) ;
(pterm0[20] => regin) = (0, 0) ;
(pterm0[21] => regin) = (0, 0) ;
(pterm0[22] => regin) = (0, 0) ;
(pterm0[23] => regin) = (0, 0) ;
(pterm0[24] => regin) = (0, 0) ;
(pterm0[25] => regin) = (0, 0) ;
(pterm0[26] => regin) = (0, 0) ;
(pterm0[27] => regin) = (0, 0) ;
(pterm0[28] => regin) = (0, 0) ;
(pterm0[29] => regin) = (0, 0) ;
(pterm0[30] => regin) = (0, 0) ;
(pterm0[31] => regin) = (0, 0) ;
(pterm0[32] => regin) = (0, 0) ;
(pterm0[33] => regin) = (0, 0) ;
(pterm0[34] => regin) = (0, 0) ;
(pterm0[35] => regin) = (0, 0) ;
(pterm0[36] => regin) = (0, 0) ;
(pterm0[37] => regin) = (0, 0) ;
(pterm0[38] => regin) = (0, 0) ;
(pterm0[39] => regin) = (0, 0) ;
(pterm0[40] => regin) = (0, 0) ;
(pterm0[41] => regin) = (0, 0) ;
(pterm0[42] => regin) = (0, 0) ;
(pterm0[43] => regin) = (0, 0) ;
(pterm0[44] => regin) = (0, 0) ;
(pterm0[45] => regin) = (0, 0) ;
(pterm0[46] => regin) = (0, 0) ;
(pterm0[47] => regin) = (0, 0) ;
(pterm0[48] => regin) = (0, 0) ;
(pterm0[49] => regin) = (0, 0) ;
(pterm0[50] => regin) = (0, 0) ;
(pterm0[51] => regin) = (0, 0) ;
(pterm1[0] => regin) = (0, 0) ;
(pterm1[1] => regin) = (0, 0) ;
(pterm1[2] => regin) = (0, 0) ;
(pterm1[3] => regin) = (0, 0) ;
(pterm1[4] => regin) = (0, 0) ;
(pterm1[5] => regin) = (0, 0) ;
(pterm1[6] => regin) = (0, 0) ;
(pterm1[7] => regin) = (0, 0) ;
(pterm1[8] => regin) = (0, 0) ;
(pterm1[9] => regin) = (0, 0) ;
(pterm1[10] => regin) = (0, 0) ;
(pterm1[11] => regin) = (0, 0) ;
(pterm1[12] => regin) = (0, 0) ;
(pterm1[13] => regin) = (0, 0) ;
(pterm1[14] => regin) = (0, 0) ;
(pterm1[15] => regin) = (0, 0) ;
(pterm1[16] => regin) = (0, 0) ;
(pterm1[17] => regin) = (0, 0) ;
(pterm1[18] => regin) = (0, 0) ;
(pterm1[19] => regin) = (0, 0) ;
(pterm1[20] => regin) = (0, 0) ;
(pterm1[21] => regin) = (0, 0) ;
(pterm1[22] => regin) = (0, 0) ;
(pterm1[23] => regin) = (0, 0) ;
(pterm1[24] => regin) = (0, 0) ;
(pterm1[25] => regin) = (0, 0) ;
(pterm1[26] => regin) = (0, 0) ;
(pterm1[27] => regin) = (0, 0) ;
(pterm1[28] => regin) = (0, 0) ;
(pterm1[29] => regin) = (0, 0) ;
(pterm1[30] => regin) = (0, 0) ;
(pterm1[31] => regin) = (0, 0) ;
(pterm1[32] => regin) = (0, 0) ;
(pterm1[33] => regin) = (0, 0) ;
(pterm1[34] => regin) = (0, 0) ;
(pterm1[35] => regin) = (0, 0) ;
(pterm1[36] => regin) = (0, 0) ;
(pterm1[37] => regin) = (0, 0) ;
(pterm1[38] => regin) = (0, 0) ;
(pterm1[39] => regin) = (0, 0) ;
(pterm1[40] => regin) = (0, 0) ;
(pterm1[41] => regin) = (0, 0) ;
(pterm1[42] => regin) = (0, 0) ;
(pterm1[43] => regin) = (0, 0) ;
(pterm1[44] => regin) = (0, 0) ;
(pterm1[45] => regin) = (0, 0) ;
(pterm1[46] => regin) = (0, 0) ;
(pterm1[47] => regin) = (0, 0) ;
(pterm1[48] => regin) = (0, 0) ;
(pterm1[49] => regin) = (0, 0) ;
(pterm1[50] => regin) = (0, 0) ;
(pterm1[51] => regin) = (0, 0) ;
(pterm2[0] => regin) = (0, 0) ;
(pterm2[1] => regin) = (0, 0) ;
(pterm2[2] => regin) = (0, 0) ;
(pterm2[3] => regin) = (0, 0) ;
(pterm2[4] => regin) = (0, 0) ;
(pterm2[5] => regin) = (0, 0) ;
(pterm2[6] => regin) = (0, 0) ;
(pterm2[7] => regin) = (0, 0) ;
(pterm2[8] => regin) = (0, 0) ;
(pterm2[9] => regin) = (0, 0) ;
(pterm2[10] => regin) = (0, 0) ;
(pterm2[11] => regin) = (0, 0) ;
(pterm2[12] => regin) = (0, 0) ;
(pterm2[13] => regin) = (0, 0) ;
(pterm2[14] => regin) = (0, 0) ;
(pterm2[15] => regin) = (0, 0) ;
(pterm2[16] => regin) = (0, 0) ;
(pterm2[17] => regin) = (0, 0) ;
(pterm2[18] => regin) = (0, 0) ;
(pterm2[19] => regin) = (0, 0) ;
(pterm2[20] => regin) = (0, 0) ;
(pterm2[21] => regin) = (0, 0) ;
(pterm2[22] => regin) = (0, 0) ;
(pterm2[23] => regin) = (0, 0) ;
(pterm2[24] => regin) = (0, 0) ;
(pterm2[25] => regin) = (0, 0) ;
(pterm2[26] => regin) = (0, 0) ;
(pterm2[27] => regin) = (0, 0) ;
(pterm2[28] => regin) = (0, 0) ;
(pterm2[29] => regin) = (0, 0) ;
(pterm2[30] => regin) = (0, 0) ;
(pterm2[31] => regin) = (0, 0) ;
(pterm2[32] => regin) = (0, 0) ;
(pterm2[33] => regin) = (0, 0) ;
(pterm2[34] => regin) = (0, 0) ;
(pterm2[35] => regin) = (0, 0) ;
(pterm2[36] => regin) = (0, 0) ;
(pterm2[37] => regin) = (0, 0) ;
(pterm2[38] => regin) = (0, 0) ;
(pterm2[39] => regin) = (0, 0) ;
(pterm2[40] => regin) = (0, 0) ;
(pterm2[41] => regin) = (0, 0) ;
(pterm2[42] => regin) = (0, 0) ;
(pterm2[43] => regin) = (0, 0) ;
(pterm2[44] => regin) = (0, 0) ;
(pterm2[45] => regin) = (0, 0) ;
(pterm2[46] => regin) = (0, 0) ;
(pterm2[47] => regin) = (0, 0) ;
(pterm2[48] => regin) = (0, 0) ;
(pterm2[49] => regin) = (0, 0) ;
(pterm2[50] => regin) = (0, 0) ;
(pterm2[51] => regin) = (0, 0) ;
(pterm3[0] => regin) = (0, 0) ;
(pterm3[1] => regin) = (0, 0) ;
(pterm3[2] => regin) = (0, 0) ;
(pterm3[3] => regin) = (0, 0) ;
(pterm3[4] => regin) = (0, 0) ;
(pterm3[5] => regin) = (0, 0) ;
(pterm3[6] => regin) = (0, 0) ;
(pterm3[7] => regin) = (0, 0) ;
(pterm3[8] => regin) = (0, 0) ;
(pterm3[9] => regin) = (0, 0) ;
(pterm3[10] => regin) = (0, 0) ;
(pterm3[11] => regin) = (0, 0) ;
(pterm3[12] => regin) = (0, 0) ;
(pterm3[13] => regin) = (0, 0) ;
(pterm3[14] => regin) = (0, 0) ;
(pterm3[15] => regin) = (0, 0) ;
(pterm3[16] => regin) = (0, 0) ;
(pterm3[17] => regin) = (0, 0) ;
(pterm3[18] => regin) = (0, 0) ;
(pterm3[19] => regin) = (0, 0) ;
(pterm3[20] => regin) = (0, 0) ;
(pterm3[21] => regin) = (0, 0) ;
(pterm3[22] => regin) = (0, 0) ;
(pterm3[23] => regin) = (0, 0) ;
(pterm3[24] => regin) = (0, 0) ;
(pterm3[25] => regin) = (0, 0) ;
(pterm3[26] => regin) = (0, 0) ;
(pterm3[27] => regin) = (0, 0) ;
(pterm3[28] => regin) = (0, 0) ;
(pterm3[29] => regin) = (0, 0) ;
(pterm3[30] => regin) = (0, 0) ;
(pterm3[31] => regin) = (0, 0) ;
(pterm3[32] => regin) = (0, 0) ;
(pterm3[33] => regin) = (0, 0) ;
(pterm3[34] => regin) = (0, 0) ;
(pterm3[35] => regin) = (0, 0) ;
(pterm3[36] => regin) = (0, 0) ;
(pterm3[37] => regin) = (0, 0) ;
(pterm3[38] => regin) = (0, 0) ;
(pterm3[39] => regin) = (0, 0) ;
(pterm3[40] => regin) = (0, 0) ;
(pterm3[41] => regin) = (0, 0) ;
(pterm3[42] => regin) = (0, 0) ;
(pterm3[43] => regin) = (0, 0) ;
(pterm3[44] => regin) = (0, 0) ;
(pterm3[45] => regin) = (0, 0) ;
(pterm3[46] => regin) = (0, 0) ;
(pterm3[47] => regin) = (0, 0) ;
(pterm3[48] => regin) = (0, 0) ;
(pterm3[49] => regin) = (0, 0) ;
(pterm3[50] => regin) = (0, 0) ;
(pterm3[51] => regin) = (0, 0) ;
(pterm4[0] => regin) = (0, 0) ;
(pterm4[1] => regin) = (0, 0) ;
(pterm4[2] => regin) = (0, 0) ;
(pterm4[3] => regin) = (0, 0) ;
(pterm4[4] => regin) = (0, 0) ;
(pterm4[5] => regin) = (0, 0) ;
(pterm4[6] => regin) = (0, 0) ;
(pterm4[7] => regin) = (0, 0) ;
(pterm4[8] => regin) = (0, 0) ;
(pterm4[9] => regin) = (0, 0) ;
(pterm4[10] => regin) = (0, 0) ;
(pterm4[11] => regin) = (0, 0) ;
(pterm4[12] => regin) = (0, 0) ;
(pterm4[13] => regin) = (0, 0) ;
(pterm4[14] => regin) = (0, 0) ;
(pterm4[15] => regin) = (0, 0) ;
(pterm4[16] => regin) = (0, 0) ;
(pterm4[17] => regin) = (0, 0) ;
(pterm4[18] => regin) = (0, 0) ;
(pterm4[19] => regin) = (0, 0) ;
(pterm4[20] => regin) = (0, 0) ;
(pterm4[21] => regin) = (0, 0) ;
(pterm4[22] => regin) = (0, 0) ;
(pterm4[23] => regin) = (0, 0) ;
(pterm4[24] => regin) = (0, 0) ;
(pterm4[25] => regin) = (0, 0) ;
(pterm4[26] => regin) = (0, 0) ;
(pterm4[27] => regin) = (0, 0) ;
(pterm4[28] => regin) = (0, 0) ;
(pterm4[29] => regin) = (0, 0) ;
(pterm4[30] => regin) = (0, 0) ;
(pterm4[31] => regin) = (0, 0) ;
(pterm4[32] => regin) = (0, 0) ;
(pterm4[33] => regin) = (0, 0) ;
(pterm4[34] => regin) = (0, 0) ;
(pterm4[35] => regin) = (0, 0) ;
(pterm4[36] => regin) = (0, 0) ;
(pterm4[37] => regin) = (0, 0) ;
(pterm4[38] => regin) = (0, 0) ;
(pterm4[39] => regin) = (0, 0) ;
(pterm4[40] => regin) = (0, 0) ;
(pterm4[41] => regin) = (0, 0) ;
(pterm4[42] => regin) = (0, 0) ;
(pterm4[43] => regin) = (0, 0) ;
(pterm4[44] => regin) = (0, 0) ;
(pterm4[45] => regin) = (0, 0) ;
(pterm4[46] => regin) = (0, 0) ;
(pterm4[47] => regin) = (0, 0) ;
(pterm4[48] => regin) = (0, 0) ;
(pterm4[49] => regin) = (0, 0) ;
(pterm4[50] => regin) = (0, 0) ;
(pterm4[51] => regin) = (0, 0) ;
(pterm5[0] => regin) = (0, 0) ;
(pterm5[1] => regin) = (0, 0) ;
(pterm5[2] => regin) = (0, 0) ;
(pterm5[3] => regin) = (0, 0) ;
(pterm5[4] => regin) = (0, 0) ;
(pterm5[5] => regin) = (0, 0) ;
(pterm5[6] => regin) = (0, 0) ;
(pterm5[7] => regin) = (0, 0) ;
(pterm5[8] => regin) = (0, 0) ;
(pterm5[9] => regin) = (0, 0) ;
(pterm5[10] => regin) = (0, 0) ;
(pterm5[11] => regin) = (0, 0) ;
(pterm5[12] => regin) = (0, 0) ;
(pterm5[13] => regin) = (0, 0) ;
(pterm5[14] => regin) = (0, 0) ;
(pterm5[15] => regin) = (0, 0) ;
(pterm5[16] => regin) = (0, 0) ;
(pterm5[17] => regin) = (0, 0) ;
(pterm5[18] => regin) = (0, 0) ;
(pterm5[19] => regin) = (0, 0) ;
(pterm5[20] => regin) = (0, 0) ;
(pterm5[21] => regin) = (0, 0) ;
(pterm5[22] => regin) = (0, 0) ;
(pterm5[23] => regin) = (0, 0) ;
(pterm5[24] => regin) = (0, 0) ;
(pterm5[25] => regin) = (0, 0) ;
(pterm5[26] => regin) = (0, 0) ;
(pterm5[27] => regin) = (0, 0) ;
(pterm5[28] => regin) = (0, 0) ;
(pterm5[29] => regin) = (0, 0) ;
(pterm5[30] => regin) = (0, 0) ;
(pterm5[31] => regin) = (0, 0) ;
(pterm5[32] => regin) = (0, 0) ;
(pterm5[33] => regin) = (0, 0) ;
(pterm5[34] => regin) = (0, 0) ;
(pterm5[35] => regin) = (0, 0) ;
(pterm5[36] => regin) = (0, 0) ;
(pterm5[37] => regin) = (0, 0) ;
(pterm5[38] => regin) = (0, 0) ;
(pterm5[39] => regin) = (0, 0) ;
(pterm5[40] => regin) = (0, 0) ;
(pterm5[41] => regin) = (0, 0) ;
(pterm5[42] => regin) = (0, 0) ;
(pterm5[43] => regin) = (0, 0) ;
(pterm5[44] => regin) = (0, 0) ;
(pterm5[45] => regin) = (0, 0) ;
(pterm5[46] => regin) = (0, 0) ;
(pterm5[47] => regin) = (0, 0) ;
(pterm5[48] => regin) = (0, 0) ;
(pterm5[49] => regin) = (0, 0) ;
(pterm5[50] => regin) = (0, 0) ;
(pterm5[51] => regin) = (0, 0) ;
(pxor[0] => regin) = (0, 0) ;
(pxor[1] => regin) = (0, 0) ;
(pxor[2] => regin) = (0, 0) ;
(pxor[3] => regin) = (0, 0) ;
(pxor[4] => regin) = (0, 0) ;
(pxor[5] => regin) = (0, 0) ;
(pxor[6] => regin) = (0, 0) ;
(pxor[7] => regin) = (0, 0) ;
(pxor[8] => regin) = (0, 0) ;
(pxor[9] => regin) = (0, 0) ;
(pxor[10] => regin) = (0, 0) ;
(pxor[11] => regin) = (0, 0) ;
(pxor[12] => regin) = (0, 0) ;
(pxor[13] => regin) = (0, 0) ;
(pxor[14] => regin) = (0, 0) ;
(pxor[15] => regin) = (0, 0) ;
(pxor[16] => regin) = (0, 0) ;
(pxor[17] => regin) = (0, 0) ;
(pxor[18] => regin) = (0, 0) ;
(pxor[19] => regin) = (0, 0) ;
(pxor[20] => regin) = (0, 0) ;
(pxor[21] => regin) = (0, 0) ;
(pxor[22] => regin) = (0, 0) ;
(pxor[23] => regin) = (0, 0) ;
(pxor[24] => regin) = (0, 0) ;
(pxor[25] => regin) = (0, 0) ;
(pxor[26] => regin) = (0, 0) ;
(pxor[27] => regin) = (0, 0) ;
(pxor[28] => regin) = (0, 0) ;
(pxor[29] => regin) = (0, 0) ;
(pxor[30] => regin) = (0, 0) ;
(pxor[31] => regin) = (0, 0) ;
(pxor[32] => regin) = (0, 0) ;
(pxor[33] => regin) = (0, 0) ;
(pxor[34] => regin) = (0, 0) ;
(pxor[35] => regin) = (0, 0) ;
(pxor[36] => regin) = (0, 0) ;
(pxor[37] => regin) = (0, 0) ;
(pxor[38] => regin) = (0, 0) ;
(pxor[39] => regin) = (0, 0) ;
(pxor[40] => regin) = (0, 0) ;
(pxor[41] => regin) = (0, 0) ;
(pxor[42] => regin) = (0, 0) ;
(pxor[43] => regin) = (0, 0) ;
(pxor[44] => regin) = (0, 0) ;
(pxor[45] => regin) = (0, 0) ;
(pxor[46] => regin) = (0, 0) ;
(pxor[47] => regin) = (0, 0) ;
(pxor[48] => regin) = (0, 0) ;
(pxor[49] => regin) = (0, 0) ;
(pxor[50] => regin) = (0, 0) ;
(pxor[51] => regin) = (0, 0) ;
(pexpin => regin) = (0, 0) ;
(fpin => regin) = (0, 0);
(fbkin => regin) = (0, 0) ;
(fbkin => pexpout) = (0, 0) ;
(fbkin => combout) = (0, 0) ;
endspecify
always @ (ipterm0 or ipterm1 or ipterm2 or ipterm3
or ipterm4 or ipterm5 or ipxor or ipexpin or fbkin or ifpin)
begin
if (ifpin !== 'b0)
tmp_fpin = 'b1;
else
tmp_fpin = 'b0;
if (ipexpin !== 'b1)
tmp_pexpin = 'b0;
else
tmp_pexpin = 'b1;
if (&ipterm0 !== 'b1)
tmp_pterm0 = 'b0;
else
tmp_pterm0 = 'b1;
if (&ipterm1 !== 'b1)
tmp_pterm1 = 'b0;
else
tmp_pterm1 = 'b1;
if (&ipterm2 !== 'b1)
tmp_pterm2 = 'b0;
else
tmp_pterm2 = 'b1;
if (&ipterm3 !== 'b1)
tmp_pterm3 = 'b0;
else
tmp_pterm3 = 'b1;
if (&ipterm4 !== 'b1)
tmp_pterm4 = 'b0;
else
tmp_pterm4 = 'b1;
if (pexp_mode == "off")
begin
if (operation_mode == "normal")
begin
if (register_mode == "tff")
icomb = ((tmp_pterm0 | tmp_pterm1 | tmp_pterm2 | tmp_pterm3
| tmp_pterm4) | tmp_pexpin) ^ fbkin;
else
icomb = tmp_pterm0 | tmp_pterm1 | tmp_pterm2 | tmp_pterm3
| tmp_pterm4 | tmp_pexpin;
end
else if (operation_mode == "invert")
begin
if (register_mode == "tff")
icomb = ((tmp_pterm0 | tmp_pterm1 | tmp_pterm2 | tmp_pterm3
| tmp_pterm4 | tmp_pexpin) ^ (~fbkin));
else
icomb = (tmp_pterm0 | tmp_pterm1 | tmp_pterm2 | tmp_pterm3
| tmp_pterm4 | tmp_pexpin) ^ 'b1;
end
else if (operation_mode == "xor")
icomb = (tmp_pterm0 | tmp_pterm1 | tmp_pterm2 | tmp_pterm3
| tmp_pterm4 | tmp_pexpin) ^ &ipxor;
else if (operation_mode == "vcc")
begin
if (register_mode == "tff")
icomb = 1'b1 ^ fbkin;
else
icomb = tmp_fpin;
end
else
icomb = 'bz;
end
else //pexp_mode = on
begin
if (operation_mode == "normal")
begin
if (register_mode == "tff")
icomb = &ipterm5 ^ fbkin;
else
icomb = &ipterm5;
ipexpout = tmp_pterm0 | tmp_pterm1 | tmp_pterm2 | tmp_pterm3
| tmp_pterm4 | tmp_pexpin;
end
else if (operation_mode == "invert")
begin
if (register_mode == "tff")
icomb = &ipterm5 ^ (~fbkin);
else
icomb = &ipterm5 ^ 'b1;
ipexpout = tmp_pterm0 | tmp_pterm1 | tmp_pterm2 | tmp_pterm3
| tmp_pterm4 | tmp_pexpin;
end
else if (operation_mode == "xor")
begin
ipexpout = (tmp_pterm0 | tmp_pterm1 | tmp_pterm2 | tmp_pterm3
| tmp_pterm4 | tmp_pexpin);
icomb = &ipterm5 ^ &ipxor;
end
else if (operation_mode == "vcc")
begin
if (register_mode == "tff")
icomb = 1'b1 ^ fbkin;
else
icomb = tmp_fpin;
ipexpout = tmp_pterm0 | tmp_pterm1 | tmp_pterm2 | tmp_pterm3
| tmp_pterm4 | tmp_pexpin;
end
else
begin
icomb = 'bz;
ipexpout = 'bz;
end
end
end
and (pexpout, ipexpout, 'b1);
and (combout, icomb, 'b1);
and (regin, icomb, 'b1);
endmodule
// MAX MCELL REG
`timescale 1 ps/1 ps
module max_mcell_register (datain, clk, aclr, pclk, pena, paclr,
papre, regout, fbkout);
parameter operation_mode = "normal";
parameter power_up = "low";
parameter register_mode = "dff";
input datain, clk, aclr;
input [51:0] pclk, pena, paclr, papre;
output regout, fbkout;
reg iregout, oldclk1, oldclk2;
reg pena_viol, clk_per_viol, datain_viol, pclk_per_viol;
reg pterm_aclr, pterm_preset, ptermclk, penable;
wire reset;
wire [51:0] ipclk, ipena, ipaclr, ipapre;
reg violation;
wire clk_in;
wire iclr;
buf (clk_in, clk);
buf (iclr, aclr);
buf (ipclk[0], pclk[0]);
buf (ipclk[1], pclk[1]);
buf (ipclk[2], pclk[2]);
buf (ipclk[3], pclk[3]);
buf (ipclk[4], pclk[4]);
buf (ipclk[5], pclk[5]);
buf (ipclk[6], pclk[6]);
buf (ipclk[7], pclk[7]);
buf (ipclk[8], pclk[8]);
buf (ipclk[9], pclk[9]);
buf (ipclk[10], pclk[10]);
buf (ipclk[11], pclk[11]);
buf (ipclk[12], pclk[12]);
buf (ipclk[13], pclk[13]);
buf (ipclk[14], pclk[14]);
buf (ipclk[15], pclk[15]);
buf (ipclk[16], pclk[16]);
buf (ipclk[17], pclk[17]);
buf (ipclk[18], pclk[18]);
buf (ipclk[19], pclk[19]);
buf (ipclk[20], pclk[20]);
buf (ipclk[21], pclk[21]);
buf (ipclk[22], pclk[22]);
buf (ipclk[23], pclk[23]);
buf (ipclk[24], pclk[24]);
buf (ipclk[25], pclk[25]);
buf (ipclk[26], pclk[26]);
buf (ipclk[27], pclk[27]);
buf (ipclk[28], pclk[28]);
buf (ipclk[29], pclk[29]);
buf (ipclk[30], pclk[30]);
buf (ipclk[31], pclk[31]);
buf (ipclk[32], pclk[32]);
buf (ipclk[33], pclk[33]);
buf (ipclk[34], pclk[34]);
buf (ipclk[35], pclk[35]);
buf (ipclk[36], pclk[36]);
buf (ipclk[37], pclk[37]);
buf (ipclk[38], pclk[38]);
buf (ipclk[39], pclk[39]);
buf (ipclk[40], pclk[40]);
buf (ipclk[41], pclk[41]);
buf (ipclk[42], pclk[42]);
buf (ipclk[43], pclk[43]);
buf (ipclk[44], pclk[44]);
buf (ipclk[45], pclk[45]);
buf (ipclk[46], pclk[46]);
buf (ipclk[47], pclk[47]);
buf (ipclk[48], pclk[48]);
buf (ipclk[49], pclk[49]);
buf (ipclk[50], pclk[50]);
buf (ipclk[51], pclk[51]);
buf (ipena[0], pena[0]);
buf (ipena[1], pena[1]);
buf (ipena[2], pena[2]);
buf (ipena[3], pena[3]);
buf (ipena[4], pena[4]);
buf (ipena[5], pena[5]);
buf (ipena[6], pena[6]);
buf (ipena[7], pena[7]);
buf (ipena[8], pena[8]);
buf (ipena[9], pena[9]);
buf (ipena[10], pena[10]);
buf (ipena[11], pena[11]);
buf (ipena[12], pena[12]);
buf (ipena[13], pena[13]);
buf (ipena[14], pena[14]);
buf (ipena[15], pena[15]);
buf (ipena[16], pena[16]);
buf (ipena[17], pena[17]);
buf (ipena[18], pena[18]);
buf (ipena[19], pena[19]);
buf (ipena[20], pena[20]);
buf (ipena[21], pena[21]);
buf (ipena[22], pena[22]);
buf (ipena[23], pena[23]);
buf (ipena[24], pena[24]);
buf (ipena[25], pena[25]);
buf (ipena[26], pena[26]);
buf (ipena[27], pena[27]);
buf (ipena[28], pena[28]);
buf (ipena[29], pena[29]);
buf (ipena[30], pena[30]);
buf (ipena[31], pena[31]);
buf (ipena[32], pena[32]);
buf (ipena[33], pena[33]);
buf (ipena[34], pena[34]);
buf (ipena[35], pena[35]);
buf (ipena[36], pena[36]);
buf (ipena[37], pena[37]);
buf (ipena[38], pena[38]);
buf (ipena[39], pena[39]);
buf (ipena[40], pena[40]);
buf (ipena[41], pena[41]);
buf (ipena[42], pena[42]);
buf (ipena[43], pena[43]);
buf (ipena[44], pena[44]);
buf (ipena[45], pena[45]);
buf (ipena[46], pena[46]);
buf (ipena[47], pena[47]);
buf (ipena[48], pena[48]);
buf (ipena[49], pena[49]);
buf (ipena[50], pena[50]);
buf (ipena[51], pena[51]);
buf (ipaclr[0], paclr[0]);
buf (ipaclr[1], paclr[1]);
buf (ipaclr[2], paclr[2]);
buf (ipaclr[3], paclr[3]);
buf (ipaclr[4], paclr[4]);
buf (ipaclr[5], paclr[5]);
buf (ipaclr[6], paclr[6]);
buf (ipaclr[7], paclr[7]);
buf (ipaclr[8], paclr[8]);
buf (ipaclr[9], paclr[9]);
buf (ipaclr[10], paclr[10]);
buf (ipaclr[11], paclr[11]);
buf (ipaclr[12], paclr[12]);
buf (ipaclr[13], paclr[13]);
buf (ipaclr[14], paclr[14]);
buf (ipaclr[15], paclr[15]);
buf (ipaclr[16], paclr[16]);
buf (ipaclr[17], paclr[17]);
buf (ipaclr[18], paclr[18]);
buf (ipaclr[19], paclr[19]);
buf (ipaclr[20], paclr[20]);
buf (ipaclr[21], paclr[21]);
buf (ipaclr[22], paclr[22]);
buf (ipaclr[23], paclr[23]);
buf (ipaclr[24], paclr[24]);
buf (ipaclr[25], paclr[25]);
buf (ipaclr[26], paclr[26]);
buf (ipaclr[27], paclr[27]);
buf (ipaclr[28], paclr[28]);
buf (ipaclr[29], paclr[29]);
buf (ipaclr[30], paclr[30]);
buf (ipaclr[31], paclr[31]);
buf (ipaclr[32], paclr[32]);
buf (ipaclr[33], paclr[33]);
buf (ipaclr[34], paclr[34]);
buf (ipaclr[35], paclr[35]);
buf (ipaclr[36], paclr[36]);
buf (ipaclr[37], paclr[37]);
buf (ipaclr[38], paclr[38]);
buf (ipaclr[39], paclr[39]);
buf (ipaclr[40], paclr[40]);
buf (ipaclr[41], paclr[41]);
buf (ipaclr[42], paclr[42]);
buf (ipaclr[43], paclr[43]);
buf (ipaclr[44], paclr[44]);
buf (ipaclr[45], paclr[45]);
buf (ipaclr[46], paclr[46]);
buf (ipaclr[47], paclr[47]);
buf (ipaclr[48], paclr[48]);
buf (ipaclr[49], paclr[49]);
buf (ipaclr[50], paclr[50]);
buf (ipaclr[51], paclr[51]);
buf (ipapre[0], papre[0]);
buf (ipapre[1], papre[1]);
buf (ipapre[2], papre[2]);
buf (ipapre[3], papre[3]);
buf (ipapre[4], papre[4]);
buf (ipapre[5], papre[5]);
buf (ipapre[6], papre[6]);
buf (ipapre[7], papre[7]);
buf (ipapre[8], papre[8]);
buf (ipapre[9], papre[9]);
buf (ipapre[10], papre[10]);
buf (ipapre[11], papre[11]);
buf (ipapre[12], papre[12]);
buf (ipapre[13], papre[13]);
buf (ipapre[14], papre[14]);
buf (ipapre[15], papre[15]);
buf (ipapre[16], papre[16]);
buf (ipapre[17], papre[17]);
buf (ipapre[18], papre[18]);
buf (ipapre[19], papre[19]);
buf (ipapre[20], papre[20]);
buf (ipapre[21], papre[21]);
buf (ipapre[22], papre[22]);
buf (ipapre[23], papre[23]);
buf (ipapre[24], papre[24]);
buf (ipapre[25], papre[25]);
buf (ipapre[26], papre[26]);
buf (ipapre[27], papre[27]);
buf (ipapre[28], papre[28]);
buf (ipapre[29], papre[29]);
buf (ipapre[30], papre[30]);
buf (ipapre[31], papre[31]);
buf (ipapre[32], papre[32]);
buf (ipapre[33], papre[33]);
buf (ipapre[34], papre[34]);
buf (ipapre[35], papre[35]);
buf (ipapre[36], papre[36]);
buf (ipapre[37], papre[37]);
buf (ipapre[38], papre[38]);
buf (ipapre[39], papre[39]);
buf (ipapre[40], papre[40]);
buf (ipapre[41], papre[41]);
buf (ipapre[42], papre[42]);
buf (ipapre[43], papre[43]);
buf (ipapre[44], papre[44]);
buf (ipapre[45], papre[45]);
buf (ipapre[46], papre[46]);
buf (ipapre[47], papre[47]);
buf (ipapre[48], papre[48]);
buf (ipapre[49], papre[49]);
buf (ipapre[50], papre[50]);
buf (ipapre[51], papre[51]);
assign reset = (!iclr) && (&ipena);
specify
$period (posedge clk &&& reset, 0, clk_per_viol);
$setuphold (posedge clk &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge clk &&& reset, pena[0], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[1], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[2], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[3], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[4], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[5], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[6], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[7], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[8], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[9], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[10], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[11], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[12], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[13], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[14], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[15], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[16], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[17], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[18], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[19], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[20], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[21], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[22], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[23], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[24], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[25], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[26], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[27], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[28], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[29], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[30], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[31], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[32], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[33], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[34], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[35], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[36], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[37], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[38], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[39], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[40], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[41], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[42], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[43], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[44], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[45], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[46], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[47], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[48], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[49], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[50], 0, 0, pena_viol) ;
$setuphold (posedge clk &&& reset, pena[51], 0, 0, pena_viol) ;
$setuphold (posedge pclk[0] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[1] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[2] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[3] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[4] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[5] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[6] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[7] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[8] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[9] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[10] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[11] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[12] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[13] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[14] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[15] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[16] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[17] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[18] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[19] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[20] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[21] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[22] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[23] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[24] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[25] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[26] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[27] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[28] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[29] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[30] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[31] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[32] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[33] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[34] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[35] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[36] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[37] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[38] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[39] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[40] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[41] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[42] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[43] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[44] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[45] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[46] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[47] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[48] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[49] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[50] &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge pclk[51] &&& reset, datain, 0, 0, datain_viol) ;
(posedge clk => (regout +: datain)) = 0 ;
(posedge pclk[0] => (regout +: datain)) = (0, 0) ;
(posedge pclk[1] => (regout +: datain)) = (0, 0) ;
(posedge pclk[2] => (regout +: datain)) = (0, 0) ;
(posedge pclk[3] => (regout +: datain)) = (0, 0) ;
(posedge pclk[4] => (regout +: datain)) = (0, 0) ;
(posedge pclk[5] => (regout +: datain)) = (0, 0) ;
(posedge pclk[6] => (regout +: datain)) = (0, 0) ;
(posedge pclk[7] => (regout +: datain)) = (0, 0) ;
(posedge pclk[8] => (regout +: datain)) = (0, 0) ;
(posedge pclk[9] => (regout +: datain)) = (0, 0) ;
(posedge pclk[10] => (regout +: datain)) = (0, 0) ;
(posedge pclk[11] => (regout +: datain)) = (0, 0) ;
(posedge pclk[12] => (regout +: datain)) = (0, 0) ;
(posedge pclk[13] => (regout +: datain)) = (0, 0) ;
(posedge pclk[14] => (regout +: datain)) = (0, 0) ;
(posedge pclk[15] => (regout +: datain)) = (0, 0) ;
(posedge pclk[16] => (regout +: datain)) = (0, 0) ;
(posedge pclk[17] => (regout +: datain)) = (0, 0) ;
(posedge pclk[18] => (regout +: datain)) = (0, 0) ;
(posedge pclk[19] => (regout +: datain)) = (0, 0) ;
(posedge pclk[20] => (regout +: datain)) = (0, 0) ;
(posedge pclk[21] => (regout +: datain)) = (0, 0) ;
(posedge pclk[22] => (regout +: datain)) = (0, 0) ;
(posedge pclk[23] => (regout +: datain)) = (0, 0) ;
(posedge pclk[24] => (regout +: datain)) = (0, 0) ;
(posedge pclk[25] => (regout +: datain)) = (0, 0) ;
(posedge pclk[26] => (regout +: datain)) = (0, 0) ;
(posedge pclk[27] => (regout +: datain)) = (0, 0) ;
(posedge pclk[28] => (regout +: datain)) = (0, 0) ;
(posedge pclk[29] => (regout +: datain)) = (0, 0) ;
(posedge pclk[30] => (regout +: datain)) = (0, 0) ;
(posedge pclk[31] => (regout +: datain)) = (0, 0) ;
(posedge pclk[32] => (regout +: datain)) = (0, 0) ;
(posedge pclk[33] => (regout +: datain)) = (0, 0) ;
(posedge pclk[34] => (regout +: datain)) = (0, 0) ;
(posedge pclk[35] => (regout +: datain)) = (0, 0) ;
(posedge pclk[36] => (regout +: datain)) = (0, 0) ;
(posedge pclk[37] => (regout +: datain)) = (0, 0) ;
(posedge pclk[38] => (regout +: datain)) = (0, 0) ;
(posedge pclk[39] => (regout +: datain)) = (0, 0) ;
(posedge pclk[40] => (regout +: datain)) = (0, 0) ;
(posedge pclk[41] => (regout +: datain)) = (0, 0) ;
(posedge pclk[42] => (regout +: datain)) = (0, 0) ;
(posedge pclk[43] => (regout +: datain)) = (0, 0) ;
(posedge pclk[44] => (regout +: datain)) = (0, 0) ;
(posedge pclk[45] => (regout +: datain)) = (0, 0) ;
(posedge pclk[46] => (regout +: datain)) = (0, 0) ;
(posedge pclk[47] => (regout +: datain)) = (0, 0) ;
(posedge pclk[48] => (regout +: datain)) = (0, 0) ;
(posedge pclk[49] => (regout +: datain)) = (0, 0) ;
(posedge pclk[50] => (regout +: datain)) = (0, 0) ;
(posedge pclk[51] => (regout +: datain)) = (0, 0) ;
(posedge aclr => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[0] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[1] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[2] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[3] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[4] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[5] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[6] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[7] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[8] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[9] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[10] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[11] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[12] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[13] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[14] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[15] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[16] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[17] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[18] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[19] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[20] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[21] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[22] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[23] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[24] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[25] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[26] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[27] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[28] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[29] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[30] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[31] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[32] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[33] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[34] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[35] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[36] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[37] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[38] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[39] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[40] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[41] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[42] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[43] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[44] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[45] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[46] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[47] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[48] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[49] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[50] => (regout +: 1'b0)) = (0, 0) ;
(posedge paclr[51] => (regout +: 1'b0)) = (0, 0) ;
(posedge papre[0] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[1] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[2] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[3] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[4] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[5] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[6] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[7] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[8] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[9] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[10] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[11] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[12] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[13] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[14] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[15] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[16] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[17] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[18] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[19] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[20] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[21] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[22] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[23] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[24] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[25] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[26] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[27] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[28] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[29] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[30] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[31] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[32] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[33] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[34] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[35] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[36] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[37] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[38] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[39] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[40] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[41] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[42] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[43] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[44] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[45] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[46] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[47] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[48] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[49] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[50] => (regout +: 1'b1)) = (0, 0) ;
(posedge papre[51] => (regout +: 1'b1)) = (0, 0) ;
(posedge clk => (fbkout +: datain)) = 0 ;
(posedge pclk[0] => (fbkout +: datain)) = 0 ;
(posedge pclk[1] => (fbkout +: datain)) = 0 ;
(posedge pclk[2] => (fbkout +: datain)) = 0 ;
(posedge pclk[3] => (fbkout +: datain)) = 0 ;
(posedge pclk[4] => (fbkout +: datain)) = 0 ;
(posedge pclk[5] => (fbkout +: datain)) = 0 ;
(posedge pclk[6] => (fbkout +: datain)) = 0 ;
(posedge pclk[7] => (fbkout +: datain)) = 0 ;
(posedge pclk[8] => (fbkout +: datain)) = 0 ;
(posedge pclk[9] => (fbkout +: datain)) = 0 ;
(posedge pclk[10] => (fbkout +: datain)) = 0 ;
(posedge pclk[11] => (fbkout +: datain)) = 0 ;
(posedge pclk[12] => (fbkout +: datain)) = 0 ;
(posedge pclk[13] => (fbkout +: datain)) = 0 ;
(posedge pclk[14] => (fbkout +: datain)) = 0 ;
(posedge pclk[15] => (fbkout +: datain)) = 0 ;
(posedge pclk[16] => (fbkout +: datain)) = 0 ;
(posedge pclk[17] => (fbkout +: datain)) = 0 ;
(posedge pclk[18] => (fbkout +: datain)) = 0 ;
(posedge pclk[19] => (fbkout +: datain)) = 0 ;
(posedge pclk[20] => (fbkout +: datain)) = 0 ;
(posedge pclk[21] => (fbkout +: datain)) = 0 ;
(posedge pclk[22] => (fbkout +: datain)) = 0 ;
(posedge pclk[23] => (fbkout +: datain)) = 0 ;
(posedge pclk[24] => (fbkout +: datain)) = 0 ;
(posedge pclk[25] => (fbkout +: datain)) = 0 ;
(posedge pclk[26] => (fbkout +: datain)) = 0 ;
(posedge pclk[27] => (fbkout +: datain)) = 0 ;
(posedge pclk[28] => (fbkout +: datain)) = 0 ;
(posedge pclk[29] => (fbkout +: datain)) = 0 ;
(posedge pclk[30] => (fbkout +: datain)) = 0 ;
(posedge pclk[31] => (fbkout +: datain)) = 0 ;
(posedge pclk[32] => (fbkout +: datain)) = 0 ;
(posedge pclk[33] => (fbkout +: datain)) = 0 ;
(posedge pclk[34] => (fbkout +: datain)) = 0 ;
(posedge pclk[35] => (fbkout +: datain)) = 0 ;
(posedge pclk[36] => (fbkout +: datain)) = 0 ;
(posedge pclk[37] => (fbkout +: datain)) = 0 ;
(posedge pclk[38] => (fbkout +: datain)) = 0 ;
(posedge pclk[39] => (fbkout +: datain)) = 0 ;
(posedge pclk[40] => (fbkout +: datain)) = 0 ;
(posedge pclk[41] => (fbkout +: datain)) = 0 ;
(posedge pclk[42] => (fbkout +: datain)) = 0 ;
(posedge pclk[43] => (fbkout +: datain)) = 0 ;
(posedge pclk[44] => (fbkout +: datain)) = 0 ;
(posedge pclk[45] => (fbkout +: datain)) = 0 ;
(posedge pclk[46] => (fbkout +: datain)) = 0 ;
(posedge pclk[47] => (fbkout +: datain)) = 0 ;
(posedge pclk[48] => (fbkout +: datain)) = 0 ;
(posedge pclk[49] => (fbkout +: datain)) = 0 ;
(posedge pclk[50] => (fbkout +: datain)) = 0 ;
(posedge pclk[51] => (fbkout +: datain)) = 0 ;
(posedge aclr => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[0] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[1] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[2] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[3] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[4] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[5] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[6] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[7] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[8] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[9] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[10] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[11] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[12] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[13] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[14] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[15] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[16] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[17] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[18] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[19] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[20] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[21] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[22] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[23] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[24] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[25] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[26] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[27] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[28] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[29] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[30] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[31] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[32] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[33] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[34] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[35] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[36] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[37] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[38] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[39] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[40] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[41] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[42] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[43] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[44] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[45] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[46] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[47] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[48] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[49] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[50] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge paclr[51] => (fbkout +: 1'b0)) = (0, 0) ;
(posedge papre[0] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[1] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[2] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[3] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[4] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[5] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[6] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[7] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[8] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[9] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[10] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[11] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[12] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[13] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[14] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[15] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[16] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[17] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[18] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[19] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[20] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[21] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[22] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[23] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[24] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[25] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[26] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[27] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[28] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[29] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[30] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[31] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[32] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[33] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[34] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[35] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[36] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[37] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[38] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[39] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[40] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[41] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[42] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[43] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[44] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[45] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[46] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[47] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[48] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[49] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[50] => (fbkout +: 1'b1)) = (0, 0) ;
(posedge papre[51] => (fbkout +: 1'b1)) = (0, 0) ;
endspecify
initial
begin
penable = 'b1;
pterm_aclr = 'b0;
pterm_preset = 'b0;
ptermclk = 'b0;
oldclk1 = 'b0;
oldclk2 = 'b0;
violation = 0;
if (power_up == "low")
iregout = 'b0;
else if (power_up == "high")
iregout = 'b1;
end
always @(datain_viol or clk_per_viol or pclk_per_viol or pena_viol)
begin
violation = 1;
end
always @ (clk_in or iclr or ipaclr or ipapre or ipena or posedge violation
or ipclk)
begin
if (&ipclk !== 'b1)
ptermclk = 'b0;
else
ptermclk = 'b1;
if (&ipena == 'b0)
penable = 'b0;
else
penable = 'b1;
if ((&ipaclr) == 'b1)
pterm_aclr = 'b1;
else
pterm_aclr = 'b0;
if (&ipapre == 'b1)
pterm_preset = 'b1;
else
pterm_preset = 'b0;
if ((iclr == 'b1) || (pterm_aclr === 'b1))
iregout = 'b0;
else if (pterm_preset == 'b1)
iregout = 'b1;
else if (violation == 1'b1)
begin
violation = 0;
iregout = 'bx;
end
else if (penable == 'b1)
begin
if (((clk_in == 'b1) && (oldclk1 == 'b0)) || ((ptermclk == 'b1) && (oldclk2 == 'b0)))
begin
iregout = datain;
end
end
oldclk1 = clk_in;
oldclk2 = ptermclk;
end
and (regout, iregout, 'b1);
and (fbkout, iregout, 'b1);
endmodule
//
// MAX MCELL ATOM
//
`timescale 1 ps/1 ps
module max_mcell (pterm0, pterm1, pterm2, pterm3, pterm4, pterm5, pxor,
pexpin, clk, aclr, fpin, pclk, pena, paclr, papre,
dataout, pexpout);
parameter operation_mode = "normal";
parameter output_mode = "comb";
parameter register_mode = "dff";
parameter pexp_mode = "off";
parameter power_up = "low";
input [51:0] pterm0, pterm1, pterm2, pterm3, pterm4, pterm5;
input [51:0] pxor, pclk, pena, paclr, papre;
input pexpin, clk, aclr, fpin;
output dataout, pexpout;
wire fbk, dffin, combo, dffo;
max_asynch_mcell pcom (pterm0, pterm1, pterm2, pterm3, pterm4,
pterm5, fpin, pxor, pexpin, fbk, combo,
pexpout, dffin);
max_mcell_register preg (dffin, clk, aclr, pclk, pena, paclr,
papre, dffo, fbk);
defparam
pcom.operation_mode = operation_mode,
pcom.pexp_mode = pexp_mode,
pcom.register_mode = register_mode,
preg.operation_mode = operation_mode,
preg.power_up = power_up,
preg.register_mode = register_mode;
assign dataout = (output_mode == "comb") ? combo : dffo;
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// MAX SEXP ATOM
//
//////////////////////////////////////////////////////////////////////////////
// MAX SEXP ASYNCH
`timescale 1 ps/1 ps
module max_asynch_sexp (datain, dataout);
input [51:0] datain;
output dataout;
reg tmp_dataout;
wire [51:0] idatain;
buf (idatain[0], datain[0]);
buf (idatain[1], datain[1]);
buf (idatain[2], datain[2]);
buf (idatain[3], datain[3]);
buf (idatain[4], datain[4]);
buf (idatain[5], datain[5]);
buf (idatain[6], datain[6]);
buf (idatain[7], datain[7]);
buf (idatain[8], datain[8]);
buf (idatain[9], datain[9]);
buf (idatain[10], datain[10]);
buf (idatain[11], datain[11]);
buf (idatain[12], datain[12]);
buf (idatain[13], datain[13]);
buf (idatain[14], datain[14]);
buf (idatain[15], datain[15]);
buf (idatain[16], datain[16]);
buf (idatain[17], datain[17]);
buf (idatain[18], datain[18]);
buf (idatain[19], datain[19]);
buf (idatain[20], datain[20]);
buf (idatain[21], datain[21]);
buf (idatain[22], datain[22]);
buf (idatain[23], datain[23]);
buf (idatain[24], datain[24]);
buf (idatain[25], datain[25]);
buf (idatain[26], datain[26]);
buf (idatain[27], datain[27]);
buf (idatain[28], datain[28]);
buf (idatain[29], datain[29]);
buf (idatain[30], datain[30]);
buf (idatain[31], datain[31]);
buf (idatain[32], datain[32]);
buf (idatain[33], datain[33]);
buf (idatain[34], datain[34]);
buf (idatain[35], datain[35]);
buf (idatain[36], datain[36]);
buf (idatain[37], datain[37]);
buf (idatain[38], datain[38]);
buf (idatain[39], datain[39]);
buf (idatain[40], datain[40]);
buf (idatain[41], datain[41]);
buf (idatain[42], datain[42]);
buf (idatain[43], datain[43]);
buf (idatain[44], datain[44]);
buf (idatain[45], datain[45]);
buf (idatain[46], datain[46]);
buf (idatain[47], datain[47]);
buf (idatain[48], datain[48]);
buf (idatain[49], datain[49]);
buf (idatain[50], datain[50]);
buf (idatain[51], datain[51]);
specify
(datain[0] => dataout) = (0, 0) ;
(datain[1] => dataout) = (0, 0) ;
(datain[2] => dataout) = (0, 0) ;
(datain[3] => dataout) = (0, 0) ;
(datain[4] => dataout) = (0, 0) ;
(datain[5] => dataout) = (0, 0) ;
(datain[6] => dataout) = (0, 0) ;
(datain[7] => dataout) = (0, 0) ;
(datain[8] => dataout) = (0, 0) ;
(datain[9] => dataout) = (0, 0) ;
(datain[10] => dataout) = (0, 0) ;
(datain[11] => dataout) = (0, 0) ;
(datain[12] => dataout) = (0, 0) ;
(datain[13] => dataout) = (0, 0) ;
(datain[14] => dataout) = (0, 0) ;
(datain[15] => dataout) = (0, 0) ;
(datain[16] => dataout) = (0, 0) ;
(datain[17] => dataout) = (0, 0) ;
(datain[18] => dataout) = (0, 0) ;
(datain[19] => dataout) = (0, 0) ;
(datain[20] => dataout) = (0, 0) ;
(datain[21] => dataout) = (0, 0) ;
(datain[22] => dataout) = (0, 0) ;
(datain[23] => dataout) = (0, 0) ;
(datain[24] => dataout) = (0, 0) ;
(datain[25] => dataout) = (0, 0) ;
(datain[26] => dataout) = (0, 0) ;
(datain[27] => dataout) = (0, 0) ;
(datain[28] => dataout) = (0, 0) ;
(datain[29] => dataout) = (0, 0) ;
(datain[30] => dataout) = (0, 0) ;
(datain[31] => dataout) = (0, 0) ;
(datain[32] => dataout) = (0, 0) ;
(datain[33] => dataout) = (0, 0) ;
(datain[34] => dataout) = (0, 0) ;
(datain[35] => dataout) = (0, 0) ;
(datain[36] => dataout) = (0, 0) ;
(datain[37] => dataout) = (0, 0) ;
(datain[38] => dataout) = (0, 0) ;
(datain[39] => dataout) = (0, 0) ;
(datain[40] => dataout) = (0, 0) ;
(datain[41] => dataout) = (0, 0) ;
(datain[42] => dataout) = (0, 0) ;
(datain[43] => dataout) = (0, 0) ;
(datain[44] => dataout) = (0, 0) ;
(datain[45] => dataout) = (0, 0) ;
(datain[46] => dataout) = (0, 0) ;
(datain[47] => dataout) = (0, 0) ;
(datain[48] => dataout) = (0, 0) ;
(datain[49] => dataout) = (0, 0) ;
(datain[50] => dataout) = (0, 0) ;
(datain[51] => dataout) = (0, 0) ;
endspecify
always @ (idatain)
begin
tmp_dataout = ~(&idatain);
end
and (dataout, tmp_dataout, 'b1);
endmodule
//
// MAX SEXP ATOM
//
`timescale 1 ps/1 ps
module max_sexp (datain, dataout);
input [51:0] datain;
output dataout;
max_asynch_sexp pcom (datain, dataout);
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// The Core module to implement the core portion of the cpu
//
// ====================================================================
`include "e203_defines.v"
module e203_core(
output[`E203_PC_SIZE-1:0] inspect_pc,
`ifdef E203_HAS_CSR_EAI//{
output eai_csr_valid,
input eai_csr_ready,
output [31:0] eai_csr_addr,
output eai_csr_wr,
output [31:0] eai_csr_wdata,
input [31:0] eai_csr_rdata,
`endif//}
output core_wfi,
output tm_stop,
output core_cgstop,
output tcm_cgstop,
input [`E203_PC_SIZE-1:0] pc_rtvec,
input [`E203_HART_ID_W-1:0] core_mhartid,
input dbg_irq_r,
input [`E203_LIRQ_NUM-1:0] lcl_irq_r,
input [`E203_EVT_NUM-1:0] evt_r,
input ext_irq_r,
input sft_irq_r,
input tmr_irq_r,
//////////////////////////////////////////////////////////////
// From/To debug ctrl module
output wr_dcsr_ena ,
output wr_dpc_ena ,
output wr_dscratch_ena,
output [32-1:0] wr_csr_nxt ,
input [32-1:0] dcsr_r ,
input [`E203_PC_SIZE-1:0] dpc_r ,
input [32-1:0] dscratch_r,
output [`E203_PC_SIZE-1:0] cmt_dpc,
output cmt_dpc_ena,
output [3-1:0] cmt_dcause,
output cmt_dcause_ena,
input dbg_mode,
input dbg_halt_r,
input dbg_step_r,
input dbg_ebreakm_r,
input dbg_stopcycle,
`ifdef E203_HAS_ITCM //{
// The ITCM address region indication signal
input [`E203_ADDR_SIZE-1:0] itcm_region_indic,
input ifu2itcm_holdup,
//input ifu2itcm_replay,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// Bus Interface to ITCM, internal protocol called ICB (Internal Chip Bus)
// * Bus cmd channel
output ifu2itcm_icb_cmd_valid, // Handshake valid
input ifu2itcm_icb_cmd_ready, // Handshake ready
// Note: The data on rdata or wdata channel must be naturally
// aligned, this is in line with the AXI definition
output [`E203_ITCM_ADDR_WIDTH-1:0] ifu2itcm_icb_cmd_addr, // Bus transaction start addr
// * Bus RSP channel
input ifu2itcm_icb_rsp_valid, // Response valid
output ifu2itcm_icb_rsp_ready, // Response ready
input ifu2itcm_icb_rsp_err, // Response error
// Note: the RSP rdata is inline with AXI definition
input [`E203_ITCM_DATA_WIDTH-1:0] ifu2itcm_icb_rsp_rdata,
`endif//}
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to Private Peripheral Interface
input [`E203_ADDR_SIZE-1:0] ppi_region_indic,
//
input ppi_icb_enable,
// * Bus cmd channel
output ppi_icb_cmd_valid,
input ppi_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] ppi_icb_cmd_addr,
output ppi_icb_cmd_read,
output [`E203_XLEN-1:0] ppi_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] ppi_icb_cmd_wmask,
output ppi_icb_cmd_lock,
output ppi_icb_cmd_excl,
output [1:0] ppi_icb_cmd_size,
//
// * Bus RSP channel
input ppi_icb_rsp_valid,
output ppi_icb_rsp_ready,
input ppi_icb_rsp_err ,
input ppi_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] ppi_icb_rsp_rdata,
input [`E203_ADDR_SIZE-1:0] clint_region_indic,
input clint_icb_enable,
output clint_icb_cmd_valid,
input clint_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] clint_icb_cmd_addr,
output clint_icb_cmd_read,
output [`E203_XLEN-1:0] clint_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] clint_icb_cmd_wmask,
output clint_icb_cmd_lock,
output clint_icb_cmd_excl,
output [1:0] clint_icb_cmd_size,
//
// * Bus RSP channel
input clint_icb_rsp_valid,
output clint_icb_rsp_ready,
input clint_icb_rsp_err ,
input clint_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] clint_icb_rsp_rdata,
input [`E203_ADDR_SIZE-1:0] plic_region_indic,
input plic_icb_enable,
output plic_icb_cmd_valid,
input plic_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] plic_icb_cmd_addr,
output plic_icb_cmd_read,
output [`E203_XLEN-1:0] plic_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] plic_icb_cmd_wmask,
output plic_icb_cmd_lock,
output plic_icb_cmd_excl,
output [1:0] plic_icb_cmd_size,
//
// * Bus RSP channel
input plic_icb_rsp_valid,
output plic_icb_rsp_ready,
input plic_icb_rsp_err ,
input plic_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] plic_icb_rsp_rdata,
`ifdef E203_HAS_FIO //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to Fast I/O
input [`E203_ADDR_SIZE-1:0] fio_region_indic,
//
input fio_icb_enable,
// * Bus cmd channel
output fio_icb_cmd_valid,
input fio_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] fio_icb_cmd_addr,
output fio_icb_cmd_read,
output [`E203_XLEN-1:0] fio_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] fio_icb_cmd_wmask,
output fio_icb_cmd_lock,
output fio_icb_cmd_excl,
output [1:0] fio_icb_cmd_size,
//
// * Bus RSP channel
input fio_icb_rsp_valid,
output fio_icb_rsp_ready,
input fio_icb_rsp_err ,
input fio_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] fio_icb_rsp_rdata,
`endif//}
`ifdef E203_HAS_MEM_ITF //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface from Ifetch
//
input mem_icb_enable,
// * Bus cmd channel
output mem_icb_cmd_valid,
input mem_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] mem_icb_cmd_addr,
output mem_icb_cmd_read,
output [`E203_XLEN-1:0] mem_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] mem_icb_cmd_wmask,
output mem_icb_cmd_lock,
output mem_icb_cmd_excl,
output [1:0] mem_icb_cmd_size,
output [1:0] mem_icb_cmd_burst,
output [1:0] mem_icb_cmd_beat,
//
// * Bus RSP channel
input mem_icb_rsp_valid,
output mem_icb_rsp_ready,
input mem_icb_rsp_err ,
input mem_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] mem_icb_rsp_rdata,
`endif//}
`ifdef E203_HAS_ITCM //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to ITCM
//
// * Bus cmd channel
output lsu2itcm_icb_cmd_valid,
input lsu2itcm_icb_cmd_ready,
output [`E203_ITCM_ADDR_WIDTH-1:0] lsu2itcm_icb_cmd_addr,
output lsu2itcm_icb_cmd_read,
output [`E203_XLEN-1:0] lsu2itcm_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] lsu2itcm_icb_cmd_wmask,
output lsu2itcm_icb_cmd_lock,
output lsu2itcm_icb_cmd_excl,
output [1:0] lsu2itcm_icb_cmd_size,
//
// * Bus RSP channel
input lsu2itcm_icb_rsp_valid,
output lsu2itcm_icb_rsp_ready,
input lsu2itcm_icb_rsp_err ,
input lsu2itcm_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] lsu2itcm_icb_rsp_rdata,
`endif//}
`ifdef E203_HAS_DTCM //{
input [`E203_ADDR_SIZE-1:0] dtcm_region_indic,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to DTCM
//
// * Bus cmd channel
output lsu2dtcm_icb_cmd_valid,
input lsu2dtcm_icb_cmd_ready,
output [`E203_DTCM_ADDR_WIDTH-1:0] lsu2dtcm_icb_cmd_addr,
output lsu2dtcm_icb_cmd_read,
output [`E203_XLEN-1:0] lsu2dtcm_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] lsu2dtcm_icb_cmd_wmask,
output lsu2dtcm_icb_cmd_lock,
output lsu2dtcm_icb_cmd_excl,
output [1:0] lsu2dtcm_icb_cmd_size,
//
// * Bus RSP channel
input lsu2dtcm_icb_rsp_valid,
output lsu2dtcm_icb_rsp_ready,
input lsu2dtcm_icb_rsp_err ,
input lsu2dtcm_icb_rsp_excl_ok,
input [`E203_XLEN-1:0] lsu2dtcm_icb_rsp_rdata,
`endif//}
output exu_active,
output ifu_active,
output lsu_active,
output biu_active,
input clk_core_ifu,
input clk_core_exu,
input clk_core_lsu,
input clk_core_biu,
input clk_aon,
input test_mode,
input rst_n
);
`ifdef E203_HAS_MEM_ITF //{
wire ifu2biu_icb_cmd_valid;
wire ifu2biu_icb_cmd_ready;
wire [`E203_ADDR_SIZE-1:0] ifu2biu_icb_cmd_addr;
wire ifu2biu_icb_rsp_valid;
wire ifu2biu_icb_rsp_ready;
wire ifu2biu_icb_rsp_err ;
wire ifu2biu_icb_rsp_excl_ok;
wire [`E203_XLEN-1:0] ifu2biu_icb_rsp_rdata;
`endif//}
wire ifu_o_valid;
wire ifu_o_ready;
wire [`E203_INSTR_SIZE-1:0] ifu_o_ir;
wire [`E203_PC_SIZE-1:0] ifu_o_pc;
wire ifu_o_pc_vld;
wire ifu_o_misalgn;
wire ifu_o_buserr;
wire [`E203_RFIDX_WIDTH-1:0] ifu_o_rs1idx;
wire [`E203_RFIDX_WIDTH-1:0] ifu_o_rs2idx;
wire ifu_o_prdt_taken;
wire ifu_o_muldiv_b2b;
wire wfi_halt_ifu_req;
wire wfi_halt_ifu_ack;
wire pipe_flush_ack;
wire pipe_flush_req;
wire [`E203_PC_SIZE-1:0] pipe_flush_add_op1;
wire [`E203_PC_SIZE-1:0] pipe_flush_add_op2;
`ifdef E203_TIMING_BOOST//}
wire [`E203_PC_SIZE-1:0] pipe_flush_pc;
`endif//}
wire oitf_empty;
wire [`E203_XLEN-1:0] rf2ifu_x1;
wire [`E203_XLEN-1:0] rf2ifu_rs1;
wire dec2ifu_rden;
wire dec2ifu_rs1en;
wire [`E203_RFIDX_WIDTH-1:0] dec2ifu_rdidx;
wire dec2ifu_mulhsu;
wire dec2ifu_div ;
wire dec2ifu_rem ;
wire dec2ifu_divu ;
wire dec2ifu_remu ;
wire itcm_nohold;
e203_ifu u_e203_ifu(
.inspect_pc (inspect_pc),
.ifu_active (ifu_active),
.pc_rtvec (pc_rtvec),
.itcm_nohold (itcm_nohold),
`ifdef E203_HAS_ITCM //{
.ifu2itcm_holdup (ifu2itcm_holdup),
//.ifu2itcm_replay (ifu2itcm_replay),
// The ITCM address region indication signal
.itcm_region_indic (itcm_region_indic),
.ifu2itcm_icb_cmd_valid(ifu2itcm_icb_cmd_valid),
.ifu2itcm_icb_cmd_ready(ifu2itcm_icb_cmd_ready),
.ifu2itcm_icb_cmd_addr (ifu2itcm_icb_cmd_addr ),
.ifu2itcm_icb_rsp_valid(ifu2itcm_icb_rsp_valid),
.ifu2itcm_icb_rsp_ready(ifu2itcm_icb_rsp_ready),
.ifu2itcm_icb_rsp_err (ifu2itcm_icb_rsp_err ),
.ifu2itcm_icb_rsp_rdata(ifu2itcm_icb_rsp_rdata),
`endif//}
`ifdef E203_HAS_MEM_ITF //{
.ifu2biu_icb_cmd_valid (ifu2biu_icb_cmd_valid),
.ifu2biu_icb_cmd_ready (ifu2biu_icb_cmd_ready),
.ifu2biu_icb_cmd_addr (ifu2biu_icb_cmd_addr ),
.ifu2biu_icb_rsp_valid (ifu2biu_icb_rsp_valid),
.ifu2biu_icb_rsp_ready (ifu2biu_icb_rsp_ready),
.ifu2biu_icb_rsp_err (ifu2biu_icb_rsp_err ),
.ifu2biu_icb_rsp_rdata (ifu2biu_icb_rsp_rdata),
`endif//}
.ifu_o_valid (ifu_o_valid ),
.ifu_o_ready (ifu_o_ready ),
.ifu_o_ir (ifu_o_ir ),
.ifu_o_pc (ifu_o_pc ),
.ifu_o_pc_vld (ifu_o_pc_vld ),
.ifu_o_misalgn (ifu_o_misalgn ),
.ifu_o_buserr (ifu_o_buserr ),
.ifu_o_rs1idx (ifu_o_rs1idx ),
.ifu_o_rs2idx (ifu_o_rs2idx ),
.ifu_o_prdt_taken (ifu_o_prdt_taken ),
.ifu_o_muldiv_b2b (ifu_o_muldiv_b2b ),
.ifu_halt_req (wfi_halt_ifu_req),
.ifu_halt_ack (wfi_halt_ifu_ack),
.pipe_flush_ack (pipe_flush_ack ),
.pipe_flush_req (pipe_flush_req ),
.pipe_flush_add_op1 (pipe_flush_add_op1 ),
.pipe_flush_add_op2 (pipe_flush_add_op2 ),
`ifdef E203_TIMING_BOOST//}
.pipe_flush_pc (pipe_flush_pc),
`endif//}
.oitf_empty (oitf_empty ),
.rf2ifu_x1 (rf2ifu_x1 ),
.rf2ifu_rs1 (rf2ifu_rs1 ),
.dec2ifu_rden (dec2ifu_rden ),
.dec2ifu_rs1en (dec2ifu_rs1en),
.dec2ifu_rdidx (dec2ifu_rdidx),
.dec2ifu_mulhsu (dec2ifu_mulhsu),
.dec2ifu_div (dec2ifu_div ),
.dec2ifu_rem (dec2ifu_rem ),
.dec2ifu_divu (dec2ifu_divu ),
.dec2ifu_remu (dec2ifu_remu ),
.clk (clk_core_ifu ),
.rst_n (rst_n )
);
wire lsu_o_valid;
wire lsu_o_ready;
wire [`E203_XLEN-1:0] lsu_o_wbck_wdat;
wire [`E203_ITAG_WIDTH -1:0] lsu_o_wbck_itag;
wire lsu_o_wbck_err ;
wire lsu_o_cmt_buserr ;
wire lsu_o_cmt_ld;
wire lsu_o_cmt_st;
wire [`E203_ADDR_SIZE -1:0] lsu_o_cmt_badaddr;
wire agu_icb_cmd_valid;
wire agu_icb_cmd_ready;
wire [`E203_ADDR_SIZE-1:0] agu_icb_cmd_addr;
wire agu_icb_cmd_read;
wire [`E203_XLEN-1:0] agu_icb_cmd_wdata;
wire [`E203_XLEN/8-1:0] agu_icb_cmd_wmask;
wire agu_icb_cmd_lock;
wire agu_icb_cmd_excl;
wire [1:0] agu_icb_cmd_size;
wire agu_icb_cmd_back2agu;
wire agu_icb_cmd_usign;
wire [`E203_ITAG_WIDTH -1:0] agu_icb_cmd_itag;
wire agu_icb_rsp_valid;
wire agu_icb_rsp_ready;
wire agu_icb_rsp_err ;
wire agu_icb_rsp_excl_ok ;
wire [`E203_XLEN-1:0] agu_icb_rsp_rdata;
wire commit_mret;
wire commit_trap;
wire excp_active;
e203_exu u_e203_exu(
`ifdef E203_HAS_CSR_EAI//{
.eai_csr_valid (eai_csr_valid),
.eai_csr_ready (eai_csr_ready),
.eai_csr_addr (eai_csr_addr ),
.eai_csr_wr (eai_csr_wr ),
.eai_csr_wdata (eai_csr_wdata),
.eai_csr_rdata (eai_csr_rdata),
`endif//}
.excp_active (excp_active),
.commit_mret (commit_mret),
.commit_trap (commit_trap),
.test_mode (test_mode),
.core_wfi (core_wfi),
.tm_stop (tm_stop),
.itcm_nohold (itcm_nohold),
.core_cgstop (core_cgstop),
.tcm_cgstop (tcm_cgstop),
.exu_active (exu_active),
.core_mhartid (core_mhartid),
.dbg_irq_r (dbg_irq_r),
.lcl_irq_r (lcl_irq_r ),
.ext_irq_r (ext_irq_r ),
.sft_irq_r (sft_irq_r ),
.tmr_irq_r (tmr_irq_r ),
.evt_r (evt_r ),
.cmt_dpc (cmt_dpc ),
.cmt_dpc_ena (cmt_dpc_ena ),
.cmt_dcause (cmt_dcause ),
.cmt_dcause_ena (cmt_dcause_ena ),
.wr_dcsr_ena (wr_dcsr_ena ),
.wr_dpc_ena (wr_dpc_ena ),
.wr_dscratch_ena (wr_dscratch_ena),
.wr_csr_nxt (wr_csr_nxt ),
.dcsr_r (dcsr_r ),
.dpc_r (dpc_r ),
.dscratch_r (dscratch_r ),
.dbg_mode (dbg_mode ),
.dbg_halt_r (dbg_halt_r),
.dbg_step_r (dbg_step_r),
.dbg_ebreakm_r (dbg_ebreakm_r),
.dbg_stopcycle (dbg_stopcycle),
.i_valid (ifu_o_valid ),
.i_ready (ifu_o_ready ),
.i_ir (ifu_o_ir ),
.i_pc (ifu_o_pc ),
.i_pc_vld (ifu_o_pc_vld ),
.i_misalgn (ifu_o_misalgn ),
.i_buserr (ifu_o_buserr ),
.i_rs1idx (ifu_o_rs1idx ),
.i_rs2idx (ifu_o_rs2idx ),
.i_prdt_taken (ifu_o_prdt_taken ),
.i_muldiv_b2b (ifu_o_muldiv_b2b ),
.wfi_halt_ifu_req (wfi_halt_ifu_req),
.wfi_halt_ifu_ack (wfi_halt_ifu_ack),
.pipe_flush_ack (pipe_flush_ack ),
.pipe_flush_req (pipe_flush_req ),
.pipe_flush_add_op1 (pipe_flush_add_op1 ),
.pipe_flush_add_op2 (pipe_flush_add_op2 ),
`ifdef E203_TIMING_BOOST//}
.pipe_flush_pc (pipe_flush_pc),
`endif//}
.lsu_o_valid (lsu_o_valid ),
.lsu_o_ready (lsu_o_ready ),
.lsu_o_wbck_wdat (lsu_o_wbck_wdat ),
.lsu_o_wbck_itag (lsu_o_wbck_itag ),
.lsu_o_wbck_err (lsu_o_wbck_err ),
.lsu_o_cmt_buserr (lsu_o_cmt_buserr ),
.lsu_o_cmt_ld (lsu_o_cmt_ld),
.lsu_o_cmt_st (lsu_o_cmt_st),
.lsu_o_cmt_badaddr (lsu_o_cmt_badaddr ),
.agu_icb_cmd_valid (agu_icb_cmd_valid ),
.agu_icb_cmd_ready (agu_icb_cmd_ready ),
.agu_icb_cmd_addr (agu_icb_cmd_addr ),
.agu_icb_cmd_read (agu_icb_cmd_read ),
.agu_icb_cmd_wdata (agu_icb_cmd_wdata ),
.agu_icb_cmd_wmask (agu_icb_cmd_wmask ),
.agu_icb_cmd_lock (agu_icb_cmd_lock ),
.agu_icb_cmd_excl (agu_icb_cmd_excl ),
.agu_icb_cmd_size (agu_icb_cmd_size ),
.agu_icb_cmd_back2agu (agu_icb_cmd_back2agu),
.agu_icb_cmd_usign (agu_icb_cmd_usign ),
.agu_icb_cmd_itag (agu_icb_cmd_itag ),
.agu_icb_rsp_valid (agu_icb_rsp_valid ),
.agu_icb_rsp_ready (agu_icb_rsp_ready ),
.agu_icb_rsp_err (agu_icb_rsp_err ),
.agu_icb_rsp_excl_ok (agu_icb_rsp_excl_ok ),
.agu_icb_rsp_rdata (agu_icb_rsp_rdata ),
.oitf_empty (oitf_empty ),
.rf2ifu_x1 (rf2ifu_x1 ),
.rf2ifu_rs1 (rf2ifu_rs1 ),
.dec2ifu_rden (dec2ifu_rden ),
.dec2ifu_rs1en (dec2ifu_rs1en),
.dec2ifu_rdidx (dec2ifu_rdidx),
.dec2ifu_mulhsu (dec2ifu_mulhsu),
.dec2ifu_div (dec2ifu_div ),
.dec2ifu_rem (dec2ifu_rem ),
.dec2ifu_divu (dec2ifu_divu ),
.dec2ifu_remu (dec2ifu_remu ),
.clk_aon (clk_aon),
.clk (clk_core_exu),
.rst_n (rst_n )
);
wire lsu2biu_icb_cmd_valid;
wire lsu2biu_icb_cmd_ready;
wire [`E203_ADDR_SIZE-1:0] lsu2biu_icb_cmd_addr;
wire lsu2biu_icb_cmd_read;
wire [`E203_XLEN-1:0] lsu2biu_icb_cmd_wdata;
wire [`E203_XLEN/8-1:0] lsu2biu_icb_cmd_wmask;
wire lsu2biu_icb_cmd_lock;
wire lsu2biu_icb_cmd_excl;
wire [1:0] lsu2biu_icb_cmd_size;
wire lsu2biu_icb_rsp_valid;
wire lsu2biu_icb_rsp_ready;
wire lsu2biu_icb_rsp_err ;
wire lsu2biu_icb_rsp_excl_ok;
wire [`E203_XLEN-1:0] lsu2biu_icb_rsp_rdata;
e203_lsu u_e203_lsu(
.excp_active (excp_active),
.commit_mret (commit_mret),
.commit_trap (commit_trap),
.lsu_active (lsu_active),
.lsu_o_valid (lsu_o_valid ),
.lsu_o_ready (lsu_o_ready ),
.lsu_o_wbck_wdat (lsu_o_wbck_wdat ),
.lsu_o_wbck_itag (lsu_o_wbck_itag ),
.lsu_o_wbck_err (lsu_o_wbck_err ),
.lsu_o_cmt_buserr (lsu_o_cmt_buserr ),
.lsu_o_cmt_ld (lsu_o_cmt_ld),
.lsu_o_cmt_st (lsu_o_cmt_st),
.lsu_o_cmt_badaddr (lsu_o_cmt_badaddr ),
.agu_icb_cmd_valid (agu_icb_cmd_valid ),
.agu_icb_cmd_ready (agu_icb_cmd_ready ),
.agu_icb_cmd_addr (agu_icb_cmd_addr ),
.agu_icb_cmd_read (agu_icb_cmd_read ),
.agu_icb_cmd_wdata (agu_icb_cmd_wdata ),
.agu_icb_cmd_wmask (agu_icb_cmd_wmask ),
.agu_icb_cmd_lock (agu_icb_cmd_lock ),
.agu_icb_cmd_excl (agu_icb_cmd_excl ),
.agu_icb_cmd_size (agu_icb_cmd_size ),
.agu_icb_cmd_back2agu(agu_icb_cmd_back2agu ),
.agu_icb_cmd_usign (agu_icb_cmd_usign),
.agu_icb_cmd_itag (agu_icb_cmd_itag),
.agu_icb_rsp_valid (agu_icb_rsp_valid ),
.agu_icb_rsp_ready (agu_icb_rsp_ready ),
.agu_icb_rsp_err (agu_icb_rsp_err ),
.agu_icb_rsp_excl_ok (agu_icb_rsp_excl_ok),
.agu_icb_rsp_rdata (agu_icb_rsp_rdata),
`ifdef E203_HAS_ITCM //{
.itcm_region_indic (itcm_region_indic),
.itcm_icb_cmd_valid (lsu2itcm_icb_cmd_valid),
.itcm_icb_cmd_ready (lsu2itcm_icb_cmd_ready),
.itcm_icb_cmd_addr (lsu2itcm_icb_cmd_addr ),
.itcm_icb_cmd_read (lsu2itcm_icb_cmd_read ),
.itcm_icb_cmd_wdata (lsu2itcm_icb_cmd_wdata),
.itcm_icb_cmd_wmask (lsu2itcm_icb_cmd_wmask),
.itcm_icb_cmd_lock (lsu2itcm_icb_cmd_lock ),
.itcm_icb_cmd_excl (lsu2itcm_icb_cmd_excl ),
.itcm_icb_cmd_size (lsu2itcm_icb_cmd_size ),
.itcm_icb_rsp_valid (lsu2itcm_icb_rsp_valid),
.itcm_icb_rsp_ready (lsu2itcm_icb_rsp_ready),
.itcm_icb_rsp_err (lsu2itcm_icb_rsp_err ),
.itcm_icb_rsp_excl_ok(lsu2itcm_icb_rsp_excl_ok ),
.itcm_icb_rsp_rdata (lsu2itcm_icb_rsp_rdata),
`endif//}
`ifdef E203_HAS_DTCM //{
.dtcm_region_indic (dtcm_region_indic),
.dtcm_icb_cmd_valid (lsu2dtcm_icb_cmd_valid),
.dtcm_icb_cmd_ready (lsu2dtcm_icb_cmd_ready),
.dtcm_icb_cmd_addr (lsu2dtcm_icb_cmd_addr ),
.dtcm_icb_cmd_read (lsu2dtcm_icb_cmd_read ),
.dtcm_icb_cmd_wdata (lsu2dtcm_icb_cmd_wdata),
.dtcm_icb_cmd_wmask (lsu2dtcm_icb_cmd_wmask),
.dtcm_icb_cmd_lock (lsu2dtcm_icb_cmd_lock ),
.dtcm_icb_cmd_excl (lsu2dtcm_icb_cmd_excl ),
.dtcm_icb_cmd_size (lsu2dtcm_icb_cmd_size ),
.dtcm_icb_rsp_valid (lsu2dtcm_icb_rsp_valid),
.dtcm_icb_rsp_ready (lsu2dtcm_icb_rsp_ready),
.dtcm_icb_rsp_err (lsu2dtcm_icb_rsp_err ),
.dtcm_icb_rsp_excl_ok(lsu2dtcm_icb_rsp_excl_ok ),
.dtcm_icb_rsp_rdata (lsu2dtcm_icb_rsp_rdata),
`endif//}
.biu_icb_cmd_valid (lsu2biu_icb_cmd_valid),
.biu_icb_cmd_ready (lsu2biu_icb_cmd_ready),
.biu_icb_cmd_addr (lsu2biu_icb_cmd_addr ),
.biu_icb_cmd_read (lsu2biu_icb_cmd_read ),
.biu_icb_cmd_wdata (lsu2biu_icb_cmd_wdata),
.biu_icb_cmd_wmask (lsu2biu_icb_cmd_wmask),
.biu_icb_cmd_lock (lsu2biu_icb_cmd_lock ),
.biu_icb_cmd_excl (lsu2biu_icb_cmd_excl ),
.biu_icb_cmd_size (lsu2biu_icb_cmd_size ),
.biu_icb_rsp_valid (lsu2biu_icb_rsp_valid),
.biu_icb_rsp_ready (lsu2biu_icb_rsp_ready),
.biu_icb_rsp_err (lsu2biu_icb_rsp_err ),
.biu_icb_rsp_excl_ok(lsu2biu_icb_rsp_excl_ok),
.biu_icb_rsp_rdata (lsu2biu_icb_rsp_rdata),
.clk (clk_core_lsu ),
.rst_n (rst_n )
);
e203_biu u_e203_biu(
.biu_active (biu_active),
.lsu2biu_icb_cmd_valid (lsu2biu_icb_cmd_valid),
.lsu2biu_icb_cmd_ready (lsu2biu_icb_cmd_ready),
.lsu2biu_icb_cmd_addr (lsu2biu_icb_cmd_addr ),
.lsu2biu_icb_cmd_read (lsu2biu_icb_cmd_read ),
.lsu2biu_icb_cmd_wdata (lsu2biu_icb_cmd_wdata),
.lsu2biu_icb_cmd_wmask (lsu2biu_icb_cmd_wmask),
.lsu2biu_icb_cmd_lock (lsu2biu_icb_cmd_lock ),
.lsu2biu_icb_cmd_excl (lsu2biu_icb_cmd_excl ),
.lsu2biu_icb_cmd_size (lsu2biu_icb_cmd_size ),
.lsu2biu_icb_cmd_burst (2'b0),
.lsu2biu_icb_cmd_beat (2'b0 ),
.lsu2biu_icb_rsp_valid (lsu2biu_icb_rsp_valid),
.lsu2biu_icb_rsp_ready (lsu2biu_icb_rsp_ready),
.lsu2biu_icb_rsp_err (lsu2biu_icb_rsp_err ),
.lsu2biu_icb_rsp_excl_ok(lsu2biu_icb_rsp_excl_ok),
.lsu2biu_icb_rsp_rdata (lsu2biu_icb_rsp_rdata),
`ifdef E203_HAS_MEM_ITF //{
.ifu2biu_icb_cmd_valid (ifu2biu_icb_cmd_valid),
.ifu2biu_icb_cmd_ready (ifu2biu_icb_cmd_ready),
.ifu2biu_icb_cmd_addr (ifu2biu_icb_cmd_addr ),
.ifu2biu_icb_cmd_read (1'b1 ),
.ifu2biu_icb_cmd_wdata (`E203_XLEN'b0),
.ifu2biu_icb_cmd_wmask ({`E203_XLEN/8{1'b0}}),
.ifu2biu_icb_cmd_lock (1'b0 ),
.ifu2biu_icb_cmd_excl (1'b0 ),
.ifu2biu_icb_cmd_size (2'b10),
.ifu2biu_icb_cmd_burst (2'b0),
.ifu2biu_icb_cmd_beat (2'b0),
.ifu2biu_icb_rsp_valid (ifu2biu_icb_rsp_valid),
.ifu2biu_icb_rsp_ready (ifu2biu_icb_rsp_ready),
.ifu2biu_icb_rsp_err (ifu2biu_icb_rsp_err ),
.ifu2biu_icb_rsp_excl_ok(ifu2biu_icb_rsp_excl_ok),
.ifu2biu_icb_rsp_rdata (ifu2biu_icb_rsp_rdata),
`endif//}
.ppi_region_indic (ppi_region_indic ),
.ppi_icb_enable (ppi_icb_enable),
.ppi_icb_cmd_valid (ppi_icb_cmd_valid),
.ppi_icb_cmd_ready (ppi_icb_cmd_ready),
.ppi_icb_cmd_addr (ppi_icb_cmd_addr ),
.ppi_icb_cmd_read (ppi_icb_cmd_read ),
.ppi_icb_cmd_wdata (ppi_icb_cmd_wdata),
.ppi_icb_cmd_wmask (ppi_icb_cmd_wmask),
.ppi_icb_cmd_lock (ppi_icb_cmd_lock ),
.ppi_icb_cmd_excl (ppi_icb_cmd_excl ),
.ppi_icb_cmd_size (ppi_icb_cmd_size ),
.ppi_icb_cmd_burst (),
.ppi_icb_cmd_beat (),
.ppi_icb_rsp_valid (ppi_icb_rsp_valid),
.ppi_icb_rsp_ready (ppi_icb_rsp_ready),
.ppi_icb_rsp_err (ppi_icb_rsp_err ),
.ppi_icb_rsp_excl_ok (ppi_icb_rsp_excl_ok),
.ppi_icb_rsp_rdata (ppi_icb_rsp_rdata),
.plic_icb_enable (plic_icb_enable),
.plic_region_indic (plic_region_indic ),
.plic_icb_cmd_valid (plic_icb_cmd_valid),
.plic_icb_cmd_ready (plic_icb_cmd_ready),
.plic_icb_cmd_addr (plic_icb_cmd_addr ),
.plic_icb_cmd_read (plic_icb_cmd_read ),
.plic_icb_cmd_wdata (plic_icb_cmd_wdata),
.plic_icb_cmd_wmask (plic_icb_cmd_wmask),
.plic_icb_cmd_lock (plic_icb_cmd_lock ),
.plic_icb_cmd_excl (plic_icb_cmd_excl ),
.plic_icb_cmd_size (plic_icb_cmd_size ),
.plic_icb_cmd_burst (),
.plic_icb_cmd_beat (),
.plic_icb_rsp_valid (plic_icb_rsp_valid),
.plic_icb_rsp_ready (plic_icb_rsp_ready),
.plic_icb_rsp_err (plic_icb_rsp_err ),
.plic_icb_rsp_excl_ok (plic_icb_rsp_excl_ok),
.plic_icb_rsp_rdata (plic_icb_rsp_rdata),
.clint_icb_enable (clint_icb_enable),
.clint_region_indic (clint_region_indic ),
.clint_icb_cmd_valid (clint_icb_cmd_valid),
.clint_icb_cmd_ready (clint_icb_cmd_ready),
.clint_icb_cmd_addr (clint_icb_cmd_addr ),
.clint_icb_cmd_read (clint_icb_cmd_read ),
.clint_icb_cmd_wdata (clint_icb_cmd_wdata),
.clint_icb_cmd_wmask (clint_icb_cmd_wmask),
.clint_icb_cmd_lock (clint_icb_cmd_lock ),
.clint_icb_cmd_excl (clint_icb_cmd_excl ),
.clint_icb_cmd_size (clint_icb_cmd_size ),
.clint_icb_cmd_burst (),
.clint_icb_cmd_beat (),
.clint_icb_rsp_valid (clint_icb_rsp_valid),
.clint_icb_rsp_ready (clint_icb_rsp_ready),
.clint_icb_rsp_err (clint_icb_rsp_err ),
.clint_icb_rsp_excl_ok (clint_icb_rsp_excl_ok),
.clint_icb_rsp_rdata (clint_icb_rsp_rdata),
`ifdef E203_HAS_FIO //{
.fio_region_indic (fio_region_indic ),
.fio_icb_enable (fio_icb_enable),
.fio_icb_cmd_valid (fio_icb_cmd_valid),
.fio_icb_cmd_ready (fio_icb_cmd_ready),
.fio_icb_cmd_addr (fio_icb_cmd_addr ),
.fio_icb_cmd_read (fio_icb_cmd_read ),
.fio_icb_cmd_wdata (fio_icb_cmd_wdata),
.fio_icb_cmd_wmask (fio_icb_cmd_wmask),
.fio_icb_cmd_lock (fio_icb_cmd_lock ),
.fio_icb_cmd_excl (fio_icb_cmd_excl ),
.fio_icb_cmd_size (fio_icb_cmd_size ),
.fio_icb_cmd_burst (),
.fio_icb_cmd_beat (),
.fio_icb_rsp_valid (fio_icb_rsp_valid),
.fio_icb_rsp_ready (fio_icb_rsp_ready),
.fio_icb_rsp_err (fio_icb_rsp_err ),
.fio_icb_rsp_excl_ok (fio_icb_rsp_excl_ok ),
.fio_icb_rsp_rdata (fio_icb_rsp_rdata),
`endif//}
`ifdef E203_HAS_MEM_ITF //{
.mem_icb_enable (mem_icb_enable),
.mem_icb_cmd_valid (mem_icb_cmd_valid),
.mem_icb_cmd_ready (mem_icb_cmd_ready),
.mem_icb_cmd_addr (mem_icb_cmd_addr ),
.mem_icb_cmd_read (mem_icb_cmd_read ),
.mem_icb_cmd_wdata (mem_icb_cmd_wdata),
.mem_icb_cmd_wmask (mem_icb_cmd_wmask),
.mem_icb_cmd_lock (mem_icb_cmd_lock ),
.mem_icb_cmd_excl (mem_icb_cmd_excl ),
.mem_icb_cmd_size (mem_icb_cmd_size ),
.mem_icb_cmd_burst (mem_icb_cmd_burst),
.mem_icb_cmd_beat (mem_icb_cmd_beat ),
.mem_icb_rsp_valid (mem_icb_rsp_valid),
.mem_icb_rsp_ready (mem_icb_rsp_ready),
.mem_icb_rsp_err (mem_icb_rsp_err ),
.mem_icb_rsp_excl_ok (mem_icb_rsp_excl_ok ),
.mem_icb_rsp_rdata (mem_icb_rsp_rdata),
`endif//}
.clk (clk_core_biu ),
.rst_n (rst_n )
);
endmodule
|
module module2(clk_, rst_, bar0, bar1, foo0, foo1);
input clk_;
input rst_;
input [1:0] bar0;
input [1:0] bar1;
output [1:0] foo0;
output [1:0] foo1;
parameter poser_tied = 1'b1;
parameter poser_width_in = 0+1-0+1+1-0+1;
parameter poser_width_out = 0+1-0+1+1-0+1;
parameter poser_grid_width = 5;
parameter poser_grid_depth = 9;
parameter [poser_grid_width-1:0] cellTypes [0:poser_grid_depth-1] = '{ 5'b11111,5'b11111,5'b11111,5'b11111,5'b11111,5'b11111,5'b11111,5'b11111,5'b11111 };
wire [poser_width_in-1:0] poser_inputs;
assign poser_inputs = { bar0,bar1 };
wire [poser_width_out-1:0] poser_outputs;
assign { foo0,foo1 } = poser_outputs;
wire [poser_grid_width-1:0] poser_grid_output [0:poser_grid_depth-1];
wire poser_clk;
assign poser_clk = clk_;
wire poser_rst;
assign poser_rst = rst_;
for (genvar D = 0; D < poser_grid_depth; D++) begin
for (genvar W = 0; W < poser_grid_width; W++) begin
if (D == 0) begin
if (W == 0) begin
poserCell #(.cellType(cellTypes[D][W]), .activeRst(0)) pc (.clk(poser_clk),
.rst(poser_rst),
.i(^{ poser_tied ,
poser_inputs[W%poser_width_in] }),
.o(poser_grid_output[D][W]));
end else begin
poserCell #(.cellType(cellTypes[D][W]), .activeRst(0)) pc (.clk(poser_clk),
.rst(poser_rst),
.i(^{ poser_grid_output[D][W-1],
poser_inputs[W%poser_width_in] }),
.o(poser_grid_output[D][W]));
end
end else begin
if (W == 0) begin
poserCell #(.cellType(cellTypes[D][W]), .activeRst(0)) pc (.clk(poser_clk),
.rst(poser_rst),
.i(^{ poser_grid_output[D-1][W],
poser_grid_output[D-1][poser_grid_depth-1] }),
.o(poser_grid_output[D][W]));
end else begin
poserCell #(.cellType(cellTypes[D][W]), .activeRst(0)) pc (.clk(poser_clk),
.rst(poser_rst),
.i(^{ poser_grid_output[D-1][W],
poser_grid_output[D][W-1] }),
.o(poser_grid_output[D][W]));
end
end
end
end
generate
if (poser_width_out == 1) begin
poserMux #(.poser_mux_width_in(poser_grid_width)) pm (.i(poser_grid_output[poser_grid_depth-1]),
.o(poser_outputs));
end
else if (poser_grid_width == poser_width_out) begin
assign poser_outputs = poser_grid_output[poser_grid_depth-1];
end
else if (poser_grid_width > poser_width_out) begin
wire [poser_grid_width-1:0] poser_grid_output_last;
assign poser_grid_output_last = poser_grid_output[poser_grid_depth-1];
poserMux #(.poser_mux_width_in((poser_grid_width - poser_width_out) + 1)) pm (.i(poser_grid_output_last[poser_grid_width-1:poser_width_out-1]),
.o(poser_outputs[poser_width_out-1]));
assign poser_outputs[poser_width_out-2:0] = poser_grid_output_last[poser_width_out-2:0];
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND3B_4_V
`define SKY130_FD_SC_HD__NAND3B_4_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog wrapper for nand3b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nand3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nand3b_4 (
Y ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nand3b_4 (
Y ,
A_N,
B ,
C
);
output Y ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND3B_4_V
|
////////////////////////////////////////////////////////////////////////////////
//
// Filename: wbdblpriarb.v
//
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
//
// Purpose: This should almost be identical to the priority arbiter, save
// for a simple diffence: it allows the arbitration of two
// separate wishbone buses. The purpose of this is to push the address
// resolution back one cycle, so that by the first clock visible to this
// core, it is known which of two parts of the bus the desired address
// will be on, save that we still use the arbiter since the underlying
// device doesn't know that there are two wishbone buses.
//
// So at this point we've deviated from the WB spec somewhat, by allowing
// two CYC and two STB lines. Everything else is the same. This allows
// (in this case the Zip CPU) to determine whether or not the access
// will be to the local ZipSystem bus or the external WB bus on the clock
// before the local bus access, otherwise peripherals were needing to do
// multiple device selection comparisons/test within a clock: 1) is this
// for the local or external bus, and 2) is this referencing me as a
// peripheral. This then caused the ZipCPU to fail all timing specs.
// By creating the two pairs of lines, CYC_A/STB_A and CYC_B/STB_B, the
// determination of local vs external can be made one clock earlier
// where there's still time for the logic, and the second comparison
// now has time to complete.
//
// So let me try to explain this again. To use this arbiter, one of the
// two masters sets CYC and STB before, only the master determines which
// of two address spaces the CYC and STB apply to before the clock and
// only sets the appropriate CYC and STB lines. Then, on the clock tick,
// the arbiter determines who gets *both* busses, as they both share every
// other WB line. Thus, only one of CYC_A and CYC_B going out will ever
// be high at a given time.
//
// Hopefully this makes more sense than it sounds. If not, check out the
// code below for a better explanation.
//
// 20150919 -- Added supported for the WB error signal.
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015,2017, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
module wbdblpriarb(i_clk, i_rst,
// Bus A
i_a_cyc_a,i_a_cyc_b,i_a_stb_a,i_a_stb_b,i_a_we,i_a_adr, i_a_dat, i_a_sel, o_a_ack, o_a_stall, o_a_err,
// Bus B
i_b_cyc_a,i_b_cyc_b,i_b_stb_a,i_b_stb_b,i_b_we,i_b_adr, i_b_dat, i_b_sel, o_b_ack, o_b_stall, o_b_err,
// Both buses
o_cyc_a, o_cyc_b, o_stb_a, o_stb_b, o_we, o_adr, o_dat, o_sel,
i_ack, i_stall, i_err);
parameter DW=32, AW=32;
// Wishbone doesn't use an i_ce signal. While it could, they dislike
// what it would (might) do to the synchronous reset signal, i_rst.
input wire i_clk, i_rst;
// Bus A
input wire i_a_cyc_a, i_a_cyc_b, i_a_stb_a, i_a_stb_b, i_a_we;
input wire [(AW-1):0] i_a_adr;
input wire [(DW-1):0] i_a_dat;
input wire [(DW/8-1):0] i_a_sel;
output wire o_a_ack, o_a_stall, o_a_err;
// Bus B
input wire i_b_cyc_a, i_b_cyc_b, i_b_stb_a, i_b_stb_b, i_b_we;
input wire [(AW-1):0] i_b_adr;
input wire [(DW-1):0] i_b_dat;
input wire [(DW/8-1):0] i_b_sel;
output wire o_b_ack, o_b_stall, o_b_err;
//
output wire o_cyc_a,o_cyc_b, o_stb_a, o_stb_b, o_we;
output wire [(AW-1):0] o_adr;
output wire [(DW-1):0] o_dat;
output wire [(DW/8-1):0] o_sel;
input wire i_ack, i_stall, i_err;
// All of our logic is really captured in the 'r_a_owner' register.
// This register determines who owns the bus. If no one is requesting
// the bus, ownership goes to A on the next clock. Otherwise, if B is
// requesting the bus and A is not, then ownership goes to not A on
// the next clock. (Sounds simple ...)
//
// The CYC logic is here to make certain that, by the time we determine
// who the bus owner is, we can do so based upon determined criteria.
reg r_a_owner;
assign o_cyc_a = ((r_a_owner) ? i_a_cyc_a : i_b_cyc_a);
assign o_cyc_b = ((r_a_owner) ? i_a_cyc_b : i_b_cyc_b);
initial r_a_owner = 1'b1;
always @(posedge i_clk)
if (i_rst)
r_a_owner <= 1'b1;
/*
// Remain with the "last owner" until 1) the other bus requests
// access, and 2) the last owner no longer wants it. This
// logic "idles" on the last owner.
//
// This is an alternating bus owner strategy
//
else if ((!o_cyc_a)&&(!o_cyc_b))
r_a_owner <= ((i_b_stb_a)||(i_b_stb_b))? 1'b0:1'b1;
//
// Expanding this out
//
// else if ((r_a_owner)&&((i_a_cyc_a)||(i_a_cyc_b)))
// r_a_owner <= 1'b1;
// else if ((!r_a_owner)&&((i_b_cyc_a)||(i_b_cyc_b)))
// r_a_owner <= 1'b0;
// else if ((r_a_owner)&&((i_b_stb_a)||(i_b_stb_b)))
// r_a_owner <= 1'b0;
// else if ((!r_a_owner)&&((i_a_stb_a)||(i_a_stb_b)))
// r_a_owner <= 1'b0;
//
// Logic required:
//
// Reset line
// + 9 inputs (data)
// + 9 inputs (CE)
// Could be done with three LUTs
// First two evaluate o_cyc_a and o_cyc_b (above)
*/
// Option 2:
//
// "Idle" on A as the owner.
// If a request is made from B, AND A is idle, THEN
// switch. Otherwise, if B is ever idle, revert back to A
// regardless of whether A wants it or not.
else if ((!i_b_cyc_a)&&(!i_b_cyc_b))
r_a_owner <= 1'b1;
else if ((!i_a_cyc_a)&&(!i_a_cyc_b)
&&((i_b_stb_a)||(i_b_stb_b)))
r_a_owner <= 1'b0;
assign o_we = (r_a_owner) ? i_a_we : i_b_we;
`ifdef ZERO_ON_IDLE
//
// ZERO_ON_IDLE uses more logic than the alternative. It should be
// useful for reducing power, as these circuits tend to drive wires
// all the way across the design, but it may also slow down the master
// clock. I've used it as an option when using VERILATOR, 'cause
// zeroing things on idle can make them stand out all the more when
// staring at wires and dumps and such.
//
wire o_cyc, o_stb;
assign o_cyc = ((o_cyc_a)||(o_cyc_b));
assign o_stb = (o_cyc)&&((o_stb_a)||(o_stb_b));
assign o_stb_a = (r_a_owner) ? (i_a_stb_a)&&(o_cyc_a) : (i_b_stb_a)&&(o_cyc_a);
assign o_stb_b = (r_a_owner) ? (i_a_stb_b)&&(o_cyc_b) : (i_b_stb_b)&&(o_cyc_b);
assign o_adr = ((o_stb_a)|(o_stb_b))?((r_a_owner) ? i_a_adr : i_b_adr):0;
assign o_dat = (o_stb)?((r_a_owner) ? i_a_dat : i_b_dat):0;
assign o_sel = (o_stb)?((r_a_owner) ? i_a_sel : i_b_sel):0;
assign o_a_ack = (o_cyc)&&( r_a_owner) ? i_ack : 1'b0;
assign o_b_ack = (o_cyc)&&(!r_a_owner) ? i_ack : 1'b0;
assign o_a_stall = (o_cyc)&&( r_a_owner) ? i_stall : 1'b1;
assign o_b_stall = (o_cyc)&&(!r_a_owner) ? i_stall : 1'b1;
assign o_a_err = (o_cyc)&&( r_a_owner) ? i_err : 1'b0;
assign o_b_err = (o_cyc)&&(!r_a_owner) ? i_err : 1'b0;
`else
// Realistically, if neither master owns the bus, the output is a
// don't care. Thus we trigger off whether or not 'A' owns the bus.
// If 'B' owns it all we care is that 'A' does not. Likewise, if
// neither owns the bus than the values on these various lines are
// irrelevant.
assign o_stb_a = (r_a_owner) ? i_a_stb_a : i_b_stb_a;
assign o_stb_b = (r_a_owner) ? i_a_stb_b : i_b_stb_b;
assign o_adr = (r_a_owner) ? i_a_adr : i_b_adr;
assign o_dat = (r_a_owner) ? i_a_dat : i_b_dat;
assign o_sel = (r_a_owner) ? i_a_sel : i_b_sel;
// We cannot allow the return acknowledgement to ever go high if
// the master in question does not own the bus. Hence we force it
// low if the particular master doesn't own the bus.
assign o_a_ack = ( r_a_owner) ? i_ack : 1'b0;
assign o_b_ack = (!r_a_owner) ? i_ack : 1'b0;
// Stall must be asserted on the same cycle the input master asserts
// the bus, if the bus isn't granted to him.
assign o_a_stall = ( r_a_owner) ? i_stall : 1'b1;
assign o_b_stall = (!r_a_owner) ? i_stall : 1'b1;
//
// These error lines will be implemented soon, as soon as the rest of
// the Zip CPU is ready to support them.
//
assign o_a_err = ( r_a_owner) ? i_err : 1'b0;
assign o_b_err = (!r_a_owner) ? i_err : 1'b0;
`endif
endmodule
|
`timescale 1ns/1ps
//Reads from accumulate buffer and writes directly to indexed location in DRAM
module accumulator #(
parameter DDR_BASE=31'h00000000,
parameter ADDRESS_WIDTH=31
) (
clk,
reset,
//External writes to accumulator
accumulate_buffer_writedata,
accumulate_buffer_slave_write,
accumulate_buffer_waitrequest,
//Local writes to accumulator
accumulator_local_writedata,
accumulator_local_wrreq,
accumulator_local_full,
accumulator_local_empty,
//Write interface to write into DDR memory
wr_control_fixed_location,
wr_control_write_base,
wr_control_write_length,
wr_control_go,
wr_control_done,
wr_user_write_buffer,
wr_user_buffer_data,
wr_user_buffer_full,
rd_control_fixed_location,
rd_control_read_base,
rd_control_read_length,
rd_control_go,
rd_control_done,
rd_user_read_buffer,
rd_user_buffer_data,
rd_user_data_available,
do_local_accumulate,
end_local_accumulate,
do_ext_accumulate,
end_ext_accumulate,
links_processed
//log_2_num_workers_in
);
//max number of external updates that we perform before timing out
localparam MAX_EXT_UPDATES = 10;
localparam DATA_WIDTH=256;
localparam NUM_STATES=19;
localparam STATE_IDLE =1;
localparam STATE_WAIT_READ =2;
localparam STATE_READ_KEY_VAL =3;
localparam STATE_READ_DELTA_VAL =4;
localparam STATE_WAIT_DELTA_VAL =5;
localparam STATE_READ_WAIT_CYCLE=6;
localparam STATE_ACCUMULATE =7;
localparam WAIT_ADD_1 =8;
localparam WAIT_ADD_2 =9;
localparam WAIT_ADD_3 =10;
localparam WAIT_ADD_4 =11;
localparam WAIT_ADD_5 =12;
localparam WAIT_ADD_6 =13;
localparam STATE_UPDATE_DRAM =14;
localparam STATE_WRITE_DRAM =15;
localparam STATE_WAIT_DONE =16;
localparam STATE_START_LOCAL_ACCUMULATE =17;
localparam STATE_START_EXT_ACCUMULATE =18;
localparam STATE_FINISH_ACCUMULATE =19;
////////////Ports///////////////////
input clk;
input reset;
//Interface for external writes//
input [63:0] accumulate_buffer_writedata;
input accumulate_buffer_slave_write;
output accumulate_buffer_waitrequest;
//Signals for local accumulation
input [63:0] accumulator_local_writedata;
input accumulator_local_wrreq;
output accumulator_local_full;
output accumulator_local_empty;
// Write control inputs and outputs
output wire wr_control_fixed_location;
output reg [30:0] wr_control_write_base;
output reg [30:0] wr_control_write_length;
output reg wr_control_go;
input wire wr_control_done;
// Write user logic inputs and outputs
output reg wr_user_write_buffer;
output reg [255:0] wr_user_buffer_data;
input wire wr_user_buffer_full;
//Read control inputs and outputs
output wire rd_control_fixed_location;
output reg [30:0] rd_control_read_base;
output reg [30:0] rd_control_read_length;
output reg rd_control_go;
input rd_control_done;
output reg rd_user_read_buffer;
input wire [255:0] rd_user_buffer_data;
input wire rd_user_data_available;
input wire do_local_accumulate;
input wire end_local_accumulate;
input wire do_ext_accumulate;
output reg end_ext_accumulate;
output reg [31:0] links_processed;
//input [31:0] log_2_num_workers_in; //returns the log2(number of workers) - useful for mask calculation in key hashing
wire [31:0] log_2_num_workers_in; //returns the log2(number of workers) - useful for mask calculation in key hashing
assign log_2_num_workers_in=0;
///////////Registers/////////////////////
reg [ADDRESS_WIDTH-1:0] wr_control_write_base_next;
reg [ADDRESS_WIDTH-1:0] wr_control_write_length_next;
reg wr_control_go_next;
reg wr_user_write_buffer_next;
reg accumulate_fifo_read_slave_read_next;
reg [30:0] rd_control_read_base_next;
reg [30:0] rd_control_read_length_next;
reg rd_control_go_next;
reg rd_user_read_buffer_next;
reg accum_type, accum_type_next;
reg accumulator_local_read_next;
//Read interface to read from accumulator FIFO
wire [63: 0] accumulate_fifo_read_slave_readdata;
wire accumulate_fifo_read_slave_waitrequest;
reg accumulate_fifo_read_slave_read;
wire [63:0] accumulator_local_readdata;
reg accumulator_local_read;
reg [log2(NUM_STATES)-1:0] state, state_next;
reg [31:0] key, message, key_next, message_next;
reg [255:0] wr_user_buffer_data_next;
reg [255:0] read_data, read_data_next;
wire overflow;
wire [31:0] accumulated_delta_val;
reg [31:0] delta_val, delta_val_next;
reg end_ext_accumulate_next;
//reg end_local_accumulate_next;
//address
wire [ADDRESS_WIDTH-1:0] key_ddr_addr;
//total links we have accumulated so far
reg [31:0] links_processed_next;
reg [31:0] ext_update_count, ext_update_count_next;
localparam LOCAL=0; //local update
localparam EXT=1; //external update
localparam DELTA_VAL_OFFSET_FROM_RECORD_BASE=8; //Record is organized as [key (offset=0), val(offset=4), delta_val(offset=8), pri, pointer, size, 0, 0]
assign wr_control_fixed_location=1'b0;
assign rd_control_fixed_location=1'b0;
assign accumulate_key = key;
assign key_ddr_addr = DDR_BASE+(key<<5);
//delta val = deltaval + message
///////////key to ddr hashing for multinode clusters
wire [31:0] key_to_ddr_mask;
//assign key_to_ddr_mask = {{32{1'b1}}<<log_2_num_workers_in};
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
float_add_sub float_add_sub(
.clock (clk),
.clk_en (1'b1),
.dataa (delta_val),
.datab (message),
.overflow(overflow),
.result (accumulated_delta_val)
);
always@(*)
begin
accumulate_fifo_read_slave_read_next = 1'b0;
key_next = key;
message_next = message;
wr_control_write_length_next = wr_control_write_length;
wr_control_write_base_next = wr_control_write_base;
wr_control_go_next = 1'b0;
wr_user_write_buffer_next = 1'b0;
state_next = state;
accum_type_next = accum_type;
accumulator_local_read_next = 1'b0;
rd_control_read_base_next = rd_control_read_base;
rd_control_read_length_next = rd_control_read_length;
rd_control_go_next = 1'b0;
rd_user_read_buffer_next = 1'b0;
wr_user_buffer_data_next = wr_user_buffer_data;
//locking variables
//end_local_accumulate_next = 1'b0;
end_ext_accumulate_next = 1'b0;
links_processed_next = links_processed;
ext_update_count_next = ext_update_count;
read_data_next = read_data;
delta_val_next = delta_val;
case(state)
STATE_IDLE: begin
links_processed_next = 0;
ext_update_count_next = 0;
if(do_local_accumulate) begin
//if(!accumulator_local_empty) begin
state_next = STATE_START_LOCAL_ACCUMULATE;
end
else if(do_ext_accumulate) begin
state_next = STATE_START_EXT_ACCUMULATE;
end
end
STATE_START_LOCAL_ACCUMULATE: begin
if(!accumulator_local_empty) begin
//links_processed_next = links_processed+1;
state_next = STATE_WAIT_READ;
accumulator_local_read_next = 1'b1;
accum_type_next = LOCAL;
end
else if(end_local_accumulate) begin
state_next = STATE_IDLE;
end
else
state_next = STATE_START_LOCAL_ACCUMULATE;
end
STATE_START_EXT_ACCUMULATE: begin
if(ext_update_count==MAX_EXT_UPDATES) begin //WE HAVE SERVICED MAX NUMBER OF EXT UPDATES
end_ext_accumulate_next = 1'b1;
state_next = STATE_FINISH_ACCUMULATE;
end
else if(!accumulate_fifo_read_slave_waitrequest) begin //if fifo is not empty, start reading first key
ext_update_count_next = ext_update_count+1;
state_next = STATE_WAIT_READ;
accumulate_fifo_read_slave_read_next = 1'b1;
accum_type_next = EXT;
end
else begin //FIFO IS EMPTY AND WE HAVENT RECEIVED ANY UPDATES YET
end_ext_accumulate_next = 1'b1;
state_next = STATE_FINISH_ACCUMULATE;
end
end
STATE_WAIT_READ: begin
state_next = STATE_READ_KEY_VAL;
end
STATE_READ_KEY_VAL: begin
if(accum_type==EXT) begin
key_next = accumulate_fifo_read_slave_readdata[63:32];
message_next = accumulate_fifo_read_slave_readdata[31:0];
end
else begin
key_next = accumulator_local_readdata[63:32];
message_next = accumulator_local_readdata[31:0];
end
state_next = STATE_READ_DELTA_VAL;
end
STATE_READ_DELTA_VAL: begin
//rd_control_read_base_next = DDR_BASE+(key<<5);
rd_control_read_base_next = DDR_BASE+((key>>log_2_num_workers_in)<<5);
rd_control_read_length_next = 32;
rd_control_go_next = 1'b1;
state_next = STATE_WAIT_DELTA_VAL;
end
STATE_WAIT_DELTA_VAL: begin //
//if(rd_control_done&&rd_user_data_available) begin //deepak - debug:latchup
if(rd_user_data_available) begin //deepak - debug:latchup
rd_user_read_buffer_next = 1'b1;
state_next = STATE_READ_WAIT_CYCLE;
end
end
STATE_READ_WAIT_CYCLE: begin
read_data_next = rd_user_buffer_data;
delta_val_next = rd_user_buffer_data[95:64]; //extract delta v
state_next = STATE_ACCUMULATE;
end
STATE_ACCUMULATE: begin
state_next = WAIT_ADD_1;
end
//7 cycles for wait latency (floating point addition)
WAIT_ADD_1: state_next = WAIT_ADD_2;
WAIT_ADD_2: state_next = WAIT_ADD_3;
WAIT_ADD_3: state_next = WAIT_ADD_4;
WAIT_ADD_4: state_next = WAIT_ADD_5;
WAIT_ADD_5: state_next = WAIT_ADD_6;
WAIT_ADD_6: state_next = STATE_UPDATE_DRAM;
STATE_UPDATE_DRAM: begin
wr_user_buffer_data_next = {read_data[255:96],accumulated_delta_val,read_data[63:0]}; //
wr_control_write_base_next = rd_control_read_base;
wr_control_write_length_next = 32;
wr_control_go_next = 1'b1;
state_next = STATE_WRITE_DRAM;
end
STATE_WRITE_DRAM: begin
if(!wr_user_buffer_full) begin
wr_user_write_buffer_next = 1'b1;
state_next = STATE_WAIT_DONE;
end
end
STATE_WAIT_DONE: begin
if(wr_control_done) begin
links_processed_next = (accum_type==LOCAL)?(links_processed+1):links_processed;
state_next = (accum_type==LOCAL)?STATE_START_LOCAL_ACCUMULATE:STATE_START_EXT_ACCUMULATE;
end
end
STATE_FINISH_ACCUMULATE:begin
state_next = STATE_IDLE;
end
endcase
end
always@(posedge clk or posedge reset)
begin
if(reset) begin
state <= STATE_IDLE;
accumulate_fifo_read_slave_read <= 1'b0;
key <= 0;
message <= 0;
wr_control_write_length <= 0;
wr_control_write_base <= 0;
wr_control_go <= 0;
wr_user_write_buffer <= 1'b0;
accum_type <= 0;
accumulator_local_read <= 0;
wr_user_buffer_data <= 0;
rd_control_read_base <= 0;
rd_control_read_length <= 0;
rd_control_go <= 1'b0;
rd_user_read_buffer <= 0;
delta_val <= 0;
links_processed <= 0;
ext_update_count <= 0;
//end_local_accumulate <= 0;
end_ext_accumulate <= 0;
read_data <= 0;
end
else begin
state <= state_next;
accumulate_fifo_read_slave_read <= accumulate_fifo_read_slave_read_next;
key <= key_next;
message <= message_next;
wr_control_write_length <= wr_control_write_length_next;
wr_control_write_base <= wr_control_write_base_next;
wr_control_go <= wr_control_go_next;
wr_user_write_buffer <= wr_user_write_buffer_next;
accum_type <= accum_type_next;
accumulator_local_read <= accumulator_local_read_next;
wr_user_buffer_data <= wr_user_buffer_data_next;
rd_control_read_base <= rd_control_read_base_next;
rd_control_read_length <= rd_control_read_length_next;
rd_control_go <= rd_control_go_next;
rd_user_read_buffer <= rd_user_read_buffer_next;
delta_val <= delta_val_next;
links_processed <= links_processed_next;
ext_update_count <= ext_update_count_next;
//end_local_accumulate <= end_local_accumulate_next;
end_ext_accumulate <= end_ext_accumulate_next;
read_data <= read_data_next;
end
end
//Local accumulator FIFO (Receives local updates from compute unit)
txfifo #(
.DATA_WIDTH(64),
// .LOCAL_FIFO_DEPTH(4096)
.LOCAL_FIFO_DEPTH(512)
)accumulator_local_fifo (
.clock (clk),
.aclr (reset),
.data (accumulator_local_writedata),
.rdreq (accumulator_local_read),
.wrreq (accumulator_local_wrreq),
.q (accumulator_local_readdata),
.empty (accumulator_local_empty),
.full (accumulator_local_full),
.usedw (),
.almost_full ()
);
//External accumulator FIFO (receives external updates from netfpga pipeline)
txfifo #(
.DATA_WIDTH(64),
.LOCAL_FIFO_DEPTH(4096)
)accumulate_ext_fifo (
.clock (clk),
.aclr (reset),
.data (accumulate_buffer_writedata),
.rdreq (accumulate_fifo_read_slave_read),
.wrreq (accumulate_buffer_slave_write),
.q (accumulate_fifo_read_slave_readdata),
.empty (accumulate_fifo_read_slave_waitrequest),
.full (accumulate_buffer_waitrequest),
.usedw (),
.almost_full ()
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND2_SYMBOL_V
`define SKY130_FD_SC_HDLL__NAND2_SYMBOL_V
/**
* nand2: 2-input NAND.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__nand2 (
//# {{data|Data Signals}}
input A,
input B,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND2_SYMBOL_V
|
//Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:47:07 MST 2014
//Date : Mon Mar 28 23:20:24 2016
//Host : ubuntu-desktop running 64-bit Ubuntu 14.04.4 LTS
//Command : generate_target design_1_wrapper.bd
//Design : design_1_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module design_1_wrapper
(ACLK,
ARESETN_I,
ARESETN_P,
M_AXI_PORT_araddr,
M_AXI_PORT_arburst,
M_AXI_PORT_arcache,
M_AXI_PORT_arid,
M_AXI_PORT_arlen,
M_AXI_PORT_arlock,
M_AXI_PORT_arprot,
M_AXI_PORT_arqos,
M_AXI_PORT_arready,
M_AXI_PORT_arregion,
M_AXI_PORT_arsize,
M_AXI_PORT_arvalid,
M_AXI_PORT_awaddr,
M_AXI_PORT_awburst,
M_AXI_PORT_awcache,
M_AXI_PORT_awid,
M_AXI_PORT_awlen,
M_AXI_PORT_awlock,
M_AXI_PORT_awprot,
M_AXI_PORT_awqos,
M_AXI_PORT_awready,
M_AXI_PORT_awregion,
M_AXI_PORT_awsize,
M_AXI_PORT_awvalid,
M_AXI_PORT_bid,
M_AXI_PORT_bready,
M_AXI_PORT_bresp,
M_AXI_PORT_bvalid,
M_AXI_PORT_rdata,
M_AXI_PORT_rid,
M_AXI_PORT_rlast,
M_AXI_PORT_rready,
M_AXI_PORT_rresp,
M_AXI_PORT_rvalid,
M_AXI_PORT_wdata,
M_AXI_PORT_wlast,
M_AXI_PORT_wready,
M_AXI_PORT_wstrb,
M_AXI_PORT_wvalid,
S_AXI_PORT_araddr,
S_AXI_PORT_arburst,
S_AXI_PORT_arcache,
S_AXI_PORT_arid,
S_AXI_PORT_arlen,
S_AXI_PORT_arlock,
S_AXI_PORT_arprot,
S_AXI_PORT_arqos,
S_AXI_PORT_arready,
S_AXI_PORT_arsize,
S_AXI_PORT_arvalid,
S_AXI_PORT_awaddr,
S_AXI_PORT_awburst,
S_AXI_PORT_awcache,
S_AXI_PORT_awid,
S_AXI_PORT_awlen,
S_AXI_PORT_awlock,
S_AXI_PORT_awprot,
S_AXI_PORT_awqos,
S_AXI_PORT_awready,
S_AXI_PORT_awsize,
S_AXI_PORT_awvalid,
S_AXI_PORT_bid,
S_AXI_PORT_bready,
S_AXI_PORT_bresp,
S_AXI_PORT_bvalid,
S_AXI_PORT_rdata,
S_AXI_PORT_rid,
S_AXI_PORT_rlast,
S_AXI_PORT_rready,
S_AXI_PORT_rresp,
S_AXI_PORT_rvalid,
S_AXI_PORT_wdata,
S_AXI_PORT_wlast,
S_AXI_PORT_wready,
S_AXI_PORT_wstrb,
S_AXI_PORT_wvalid,
UART_rxd,
UART_txd,
interrupt);
input ACLK;
input ARESETN_I;
input ARESETN_P;
output [31:0]M_AXI_PORT_araddr;
output [1:0]M_AXI_PORT_arburst;
output [3:0]M_AXI_PORT_arcache;
output [1:0]M_AXI_PORT_arid;
output [7:0]M_AXI_PORT_arlen;
output [0:0]M_AXI_PORT_arlock;
output [2:0]M_AXI_PORT_arprot;
output [3:0]M_AXI_PORT_arqos;
input [0:0]M_AXI_PORT_arready;
output [3:0]M_AXI_PORT_arregion;
output [2:0]M_AXI_PORT_arsize;
output [0:0]M_AXI_PORT_arvalid;
output [31:0]M_AXI_PORT_awaddr;
output [1:0]M_AXI_PORT_awburst;
output [3:0]M_AXI_PORT_awcache;
output [1:0]M_AXI_PORT_awid;
output [7:0]M_AXI_PORT_awlen;
output [0:0]M_AXI_PORT_awlock;
output [2:0]M_AXI_PORT_awprot;
output [3:0]M_AXI_PORT_awqos;
input [0:0]M_AXI_PORT_awready;
output [3:0]M_AXI_PORT_awregion;
output [2:0]M_AXI_PORT_awsize;
output [0:0]M_AXI_PORT_awvalid;
input [1:0]M_AXI_PORT_bid;
output [0:0]M_AXI_PORT_bready;
input [1:0]M_AXI_PORT_bresp;
input [0:0]M_AXI_PORT_bvalid;
input [31:0]M_AXI_PORT_rdata;
input [1:0]M_AXI_PORT_rid;
input [0:0]M_AXI_PORT_rlast;
output [0:0]M_AXI_PORT_rready;
input [1:0]M_AXI_PORT_rresp;
input [0:0]M_AXI_PORT_rvalid;
output [31:0]M_AXI_PORT_wdata;
output [0:0]M_AXI_PORT_wlast;
input [0:0]M_AXI_PORT_wready;
output [3:0]M_AXI_PORT_wstrb;
output [0:0]M_AXI_PORT_wvalid;
input [31:0]S_AXI_PORT_araddr;
input [1:0]S_AXI_PORT_arburst;
input [3:0]S_AXI_PORT_arcache;
input [1:0]S_AXI_PORT_arid;
input [7:0]S_AXI_PORT_arlen;
input [0:0]S_AXI_PORT_arlock;
input [2:0]S_AXI_PORT_arprot;
input [3:0]S_AXI_PORT_arqos;
output [0:0]S_AXI_PORT_arready;
input [2:0]S_AXI_PORT_arsize;
input [0:0]S_AXI_PORT_arvalid;
input [31:0]S_AXI_PORT_awaddr;
input [1:0]S_AXI_PORT_awburst;
input [3:0]S_AXI_PORT_awcache;
input [1:0]S_AXI_PORT_awid;
input [7:0]S_AXI_PORT_awlen;
input [0:0]S_AXI_PORT_awlock;
input [2:0]S_AXI_PORT_awprot;
input [3:0]S_AXI_PORT_awqos;
output [0:0]S_AXI_PORT_awready;
input [2:0]S_AXI_PORT_awsize;
input [0:0]S_AXI_PORT_awvalid;
output [1:0]S_AXI_PORT_bid;
input [0:0]S_AXI_PORT_bready;
output [1:0]S_AXI_PORT_bresp;
output [0:0]S_AXI_PORT_bvalid;
output [31:0]S_AXI_PORT_rdata;
output [1:0]S_AXI_PORT_rid;
output [0:0]S_AXI_PORT_rlast;
input [0:0]S_AXI_PORT_rready;
output [1:0]S_AXI_PORT_rresp;
output [0:0]S_AXI_PORT_rvalid;
input [31:0]S_AXI_PORT_wdata;
input [0:0]S_AXI_PORT_wlast;
output [0:0]S_AXI_PORT_wready;
input [3:0]S_AXI_PORT_wstrb;
input [0:0]S_AXI_PORT_wvalid;
input UART_rxd;
output UART_txd;
output interrupt;
wire ACLK;
wire ARESETN_I;
wire ARESETN_P;
wire [31:0]M_AXI_PORT_araddr;
wire [1:0]M_AXI_PORT_arburst;
wire [3:0]M_AXI_PORT_arcache;
wire [1:0]M_AXI_PORT_arid;
wire [7:0]M_AXI_PORT_arlen;
wire [0:0]M_AXI_PORT_arlock;
wire [2:0]M_AXI_PORT_arprot;
wire [3:0]M_AXI_PORT_arqos;
wire [0:0]M_AXI_PORT_arready;
wire [3:0]M_AXI_PORT_arregion;
wire [2:0]M_AXI_PORT_arsize;
wire [0:0]M_AXI_PORT_arvalid;
wire [31:0]M_AXI_PORT_awaddr;
wire [1:0]M_AXI_PORT_awburst;
wire [3:0]M_AXI_PORT_awcache;
wire [1:0]M_AXI_PORT_awid;
wire [7:0]M_AXI_PORT_awlen;
wire [0:0]M_AXI_PORT_awlock;
wire [2:0]M_AXI_PORT_awprot;
wire [3:0]M_AXI_PORT_awqos;
wire [0:0]M_AXI_PORT_awready;
wire [3:0]M_AXI_PORT_awregion;
wire [2:0]M_AXI_PORT_awsize;
wire [0:0]M_AXI_PORT_awvalid;
wire [1:0]M_AXI_PORT_bid;
wire [0:0]M_AXI_PORT_bready;
wire [1:0]M_AXI_PORT_bresp;
wire [0:0]M_AXI_PORT_bvalid;
wire [31:0]M_AXI_PORT_rdata;
wire [1:0]M_AXI_PORT_rid;
wire [0:0]M_AXI_PORT_rlast;
wire [0:0]M_AXI_PORT_rready;
wire [1:0]M_AXI_PORT_rresp;
wire [0:0]M_AXI_PORT_rvalid;
wire [31:0]M_AXI_PORT_wdata;
wire [0:0]M_AXI_PORT_wlast;
wire [0:0]M_AXI_PORT_wready;
wire [3:0]M_AXI_PORT_wstrb;
wire [0:0]M_AXI_PORT_wvalid;
wire [31:0]S_AXI_PORT_araddr;
wire [1:0]S_AXI_PORT_arburst;
wire [3:0]S_AXI_PORT_arcache;
wire [1:0]S_AXI_PORT_arid;
wire [7:0]S_AXI_PORT_arlen;
wire [0:0]S_AXI_PORT_arlock;
wire [2:0]S_AXI_PORT_arprot;
wire [3:0]S_AXI_PORT_arqos;
wire [0:0]S_AXI_PORT_arready;
wire [2:0]S_AXI_PORT_arsize;
wire [0:0]S_AXI_PORT_arvalid;
wire [31:0]S_AXI_PORT_awaddr;
wire [1:0]S_AXI_PORT_awburst;
wire [3:0]S_AXI_PORT_awcache;
wire [1:0]S_AXI_PORT_awid;
wire [7:0]S_AXI_PORT_awlen;
wire [0:0]S_AXI_PORT_awlock;
wire [2:0]S_AXI_PORT_awprot;
wire [3:0]S_AXI_PORT_awqos;
wire [0:0]S_AXI_PORT_awready;
wire [2:0]S_AXI_PORT_awsize;
wire [0:0]S_AXI_PORT_awvalid;
wire [1:0]S_AXI_PORT_bid;
wire [0:0]S_AXI_PORT_bready;
wire [1:0]S_AXI_PORT_bresp;
wire [0:0]S_AXI_PORT_bvalid;
wire [31:0]S_AXI_PORT_rdata;
wire [1:0]S_AXI_PORT_rid;
wire [0:0]S_AXI_PORT_rlast;
wire [0:0]S_AXI_PORT_rready;
wire [1:0]S_AXI_PORT_rresp;
wire [0:0]S_AXI_PORT_rvalid;
wire [31:0]S_AXI_PORT_wdata;
wire [0:0]S_AXI_PORT_wlast;
wire [0:0]S_AXI_PORT_wready;
wire [3:0]S_AXI_PORT_wstrb;
wire [0:0]S_AXI_PORT_wvalid;
wire UART_rxd;
wire UART_txd;
wire interrupt;
design_1 design_1_i
(.ACLK(ACLK),
.ARESETN_I(ARESETN_I),
.ARESETN_P(ARESETN_P),
.M_AXI_PORT_araddr(M_AXI_PORT_araddr),
.M_AXI_PORT_arburst(M_AXI_PORT_arburst),
.M_AXI_PORT_arcache(M_AXI_PORT_arcache),
.M_AXI_PORT_arid(M_AXI_PORT_arid),
.M_AXI_PORT_arlen(M_AXI_PORT_arlen),
.M_AXI_PORT_arlock(M_AXI_PORT_arlock),
.M_AXI_PORT_arprot(M_AXI_PORT_arprot),
.M_AXI_PORT_arqos(M_AXI_PORT_arqos),
.M_AXI_PORT_arready(M_AXI_PORT_arready),
.M_AXI_PORT_arregion(M_AXI_PORT_arregion),
.M_AXI_PORT_arsize(M_AXI_PORT_arsize),
.M_AXI_PORT_arvalid(M_AXI_PORT_arvalid),
.M_AXI_PORT_awaddr(M_AXI_PORT_awaddr),
.M_AXI_PORT_awburst(M_AXI_PORT_awburst),
.M_AXI_PORT_awcache(M_AXI_PORT_awcache),
.M_AXI_PORT_awid(M_AXI_PORT_awid),
.M_AXI_PORT_awlen(M_AXI_PORT_awlen),
.M_AXI_PORT_awlock(M_AXI_PORT_awlock),
.M_AXI_PORT_awprot(M_AXI_PORT_awprot),
.M_AXI_PORT_awqos(M_AXI_PORT_awqos),
.M_AXI_PORT_awready(M_AXI_PORT_awready),
.M_AXI_PORT_awregion(M_AXI_PORT_awregion),
.M_AXI_PORT_awsize(M_AXI_PORT_awsize),
.M_AXI_PORT_awvalid(M_AXI_PORT_awvalid),
.M_AXI_PORT_bid(M_AXI_PORT_bid),
.M_AXI_PORT_bready(M_AXI_PORT_bready),
.M_AXI_PORT_bresp(M_AXI_PORT_bresp),
.M_AXI_PORT_bvalid(M_AXI_PORT_bvalid),
.M_AXI_PORT_rdata(M_AXI_PORT_rdata),
.M_AXI_PORT_rid(M_AXI_PORT_rid),
.M_AXI_PORT_rlast(M_AXI_PORT_rlast),
.M_AXI_PORT_rready(M_AXI_PORT_rready),
.M_AXI_PORT_rresp(M_AXI_PORT_rresp),
.M_AXI_PORT_rvalid(M_AXI_PORT_rvalid),
.M_AXI_PORT_wdata(M_AXI_PORT_wdata),
.M_AXI_PORT_wlast(M_AXI_PORT_wlast),
.M_AXI_PORT_wready(M_AXI_PORT_wready),
.M_AXI_PORT_wstrb(M_AXI_PORT_wstrb),
.M_AXI_PORT_wvalid(M_AXI_PORT_wvalid),
.S_AXI_PORT_araddr(S_AXI_PORT_araddr),
.S_AXI_PORT_arburst(S_AXI_PORT_arburst),
.S_AXI_PORT_arcache(S_AXI_PORT_arcache),
.S_AXI_PORT_arid(S_AXI_PORT_arid),
.S_AXI_PORT_arlen(S_AXI_PORT_arlen),
.S_AXI_PORT_arlock(S_AXI_PORT_arlock),
.S_AXI_PORT_arprot(S_AXI_PORT_arprot),
.S_AXI_PORT_arqos(S_AXI_PORT_arqos),
.S_AXI_PORT_arready(S_AXI_PORT_arready),
.S_AXI_PORT_arsize(S_AXI_PORT_arsize),
.S_AXI_PORT_arvalid(S_AXI_PORT_arvalid),
.S_AXI_PORT_awaddr(S_AXI_PORT_awaddr),
.S_AXI_PORT_awburst(S_AXI_PORT_awburst),
.S_AXI_PORT_awcache(S_AXI_PORT_awcache),
.S_AXI_PORT_awid(S_AXI_PORT_awid),
.S_AXI_PORT_awlen(S_AXI_PORT_awlen),
.S_AXI_PORT_awlock(S_AXI_PORT_awlock),
.S_AXI_PORT_awprot(S_AXI_PORT_awprot),
.S_AXI_PORT_awqos(S_AXI_PORT_awqos),
.S_AXI_PORT_awready(S_AXI_PORT_awready),
.S_AXI_PORT_awsize(S_AXI_PORT_awsize),
.S_AXI_PORT_awvalid(S_AXI_PORT_awvalid),
.S_AXI_PORT_bid(S_AXI_PORT_bid),
.S_AXI_PORT_bready(S_AXI_PORT_bready),
.S_AXI_PORT_bresp(S_AXI_PORT_bresp),
.S_AXI_PORT_bvalid(S_AXI_PORT_bvalid),
.S_AXI_PORT_rdata(S_AXI_PORT_rdata),
.S_AXI_PORT_rid(S_AXI_PORT_rid),
.S_AXI_PORT_rlast(S_AXI_PORT_rlast),
.S_AXI_PORT_rready(S_AXI_PORT_rready),
.S_AXI_PORT_rresp(S_AXI_PORT_rresp),
.S_AXI_PORT_rvalid(S_AXI_PORT_rvalid),
.S_AXI_PORT_wdata(S_AXI_PORT_wdata),
.S_AXI_PORT_wlast(S_AXI_PORT_wlast),
.S_AXI_PORT_wready(S_AXI_PORT_wready),
.S_AXI_PORT_wstrb(S_AXI_PORT_wstrb),
.S_AXI_PORT_wvalid(S_AXI_PORT_wvalid),
.UART_rxd(UART_rxd),
.UART_txd(UART_txd),
.interrupt(interrupt));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFXBP_2_V
`define SKY130_FD_SC_HD__DFXBP_2_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog wrapper for dfxbp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dfxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dfxbp_2 (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dfxbp_2 (
Q ,
Q_N,
CLK,
D
);
output Q ;
output Q_N;
input CLK;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFXBP_2_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's interface to SPRs ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Decoding of SPR addresses and access to SPRs ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_sprs.v,v $
// Revision 1.11 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.9.4.1 2003/12/17 13:43:38 simons
// Exception prefix configuration changed.
//
// Revision 1.9 2002/09/07 05:42:02 lampret
// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
//
// Revision 1.8 2002/08/28 01:44:25 lampret
// Removed some commented RTL. Fixed SR/ESR flag bug.
//
// Revision 1.7 2002/03/29 15:16:56 lampret
// Some of the warnings fixed.
//
// Revision 1.6 2002/03/11 01:26:57 lampret
// Changed generation of SPR address. Now it is ORed from base and offset instead of a sum.
//
// Revision 1.5 2002/02/01 19:56:54 lampret
// Fixed combinational loops.
//
// Revision 1.4 2002/01/23 07:52:36 lampret
// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.
//
// Revision 1.3 2002/01/19 09:27:49 lampret
// SR[TEE] should be zero after reset.
//
// Revision 1.2 2002/01/18 07:56:00 lampret
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.12 2001/11/23 21:42:31 simons
// Program counter divided to PPC and NPC.
//
// Revision 1.11 2001/11/23 08:38:51 lampret
// Changed DSR/DRR behavior and exception detection.
//
// Revision 1.10 2001/11/12 01:45:41 lampret
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
//
// Revision 1.9 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8 2001/10/14 13:12:10 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.3 2001/08/13 03:36:20 lampret
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:21 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "rtl/verilog/or1200/timescale.v"
// synopsys translate_on
`include "rtl/verilog/or1200/or1200_defines.v"
module or1200_sprs(
// Clk & Rst
clk, rst,
// Internal CPU interface
flagforw, flag_we, flag, cyforw, cy_we, carry,
addrbase, addrofs, dat_i, alu_op, branch_op,
epcr, eear, esr, except_started,
to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr_we, to_sr, sr,
spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc, spr_dat_mac,
// From/to other RISC units
spr_dat_pic, spr_dat_tt, spr_dat_pm,
spr_dat_dmmu, spr_dat_immu, spr_dat_du,
spr_addr, spr_dat_o, spr_cs, spr_we,
du_addr, du_dat_du, du_read,
du_write, du_dat_cpu
);
parameter width = `OR1200_OPERAND_WIDTH;
//
// I/O Ports
//
//
// Internal CPU interface
//
input clk; // Clock
input rst; // Reset
input flagforw; // From ALU
input flag_we; // From ALU
output flag; // SR[F]
input cyforw; // From ALU
input cy_we; // From ALU
output carry; // SR[CY]
input [width-1:0] addrbase; // SPR base address
input [15:0] addrofs; // SPR offset
input [width-1:0] dat_i; // SPR write data
input [`OR1200_ALUOP_WIDTH-1:0] alu_op; // ALU operation
input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; // Branch operation
input [width-1:0] epcr; // EPCR0
input [width-1:0] eear; // EEAR0
input [`OR1200_SR_WIDTH-1:0] esr; // ESR0
input except_started; // Exception was started
output [width-1:0] to_wbmux; // For l.mfspr
output epcr_we; // EPCR0 write enable
output eear_we; // EEAR0 write enable
output esr_we; // ESR0 write enable
output pc_we; // PC write enable
output sr_we; // Write enable SR
output [`OR1200_SR_WIDTH-1:0] to_sr; // Data to SR
output [`OR1200_SR_WIDTH-1:0] sr; // SR
input [31:0] spr_dat_cfgr; // Data from CFGR
input [31:0] spr_dat_rf; // Data from RF
input [31:0] spr_dat_npc; // Data from NPC
input [31:0] spr_dat_ppc; // Data from PPC
input [31:0] spr_dat_mac; // Data from MAC
//
// To/from other RISC units
//
input [31:0] spr_dat_pic; // Data from PIC
input [31:0] spr_dat_tt; // Data from TT
input [31:0] spr_dat_pm; // Data from PM
input [31:0] spr_dat_dmmu; // Data from DMMU
input [31:0] spr_dat_immu; // Data from IMMU
input [31:0] spr_dat_du; // Data from DU
output [31:0] spr_addr; // SPR Address
output [31:0] spr_dat_o; // Data to unit
output [31:0] spr_cs; // Unit select
output spr_we; // SPR write enable
//
// To/from Debug Unit
//
input [width-1:0] du_addr; // Address
input [width-1:0] du_dat_du; // Data from DU to SPRS
input du_read; // Read qualifier
input du_write; // Write qualifier
output [width-1:0] du_dat_cpu; // Data from SPRS to DU
//
// Internal regs & wires
//
reg [`OR1200_SR_WIDTH-1:0] sr; // SR
reg write_spr; // Write SPR
reg read_spr; // Read SPR
reg [width-1:0] to_wbmux; // For l.mfspr
wire cfgr_sel; // Select for cfg regs
wire rf_sel; // Select for RF
wire npc_sel; // Select for NPC
wire ppc_sel; // Select for PPC
wire sr_sel; // Select for SR
wire epcr_sel; // Select for EPCR0
wire eear_sel; // Select for EEAR0
wire esr_sel; // Select for ESR0
wire [31:0] sys_data; // Read data from system SPRs
wire du_access; // Debug unit access
wire [`OR1200_ALUOP_WIDTH-1:0] sprs_op; // ALU operation
reg [31:0] unqualified_cs; // Unqualified chip selects
//
// Decide if it is debug unit access
//
assign du_access = du_read | du_write;
//
// Generate sprs opcode
//
assign sprs_op = du_write ? `OR1200_ALUOP_MTSR : du_read ? `OR1200_ALUOP_MFSR : alu_op;
//
// Generate SPR address from base address and offset
// OR from debug unit address
//
assign spr_addr = du_access ? du_addr : addrbase | {16'h0000, addrofs};
//
// SPR is written by debug unit or by l.mtspr
//
assign spr_dat_o = du_write ? du_dat_du : dat_i;
//
// debug unit data input:
// - write into debug unit SPRs by debug unit itself
// - read of SPRS by debug unit
// - write into debug unit SPRs by l.mtspr
//
assign du_dat_cpu = du_write ? du_dat_du : du_read ? to_wbmux : dat_i;
//
// Write into SPRs when l.mtspr
//
assign spr_we = du_write | write_spr;
//
// Qualify chip selects
//
assign spr_cs = unqualified_cs & {32{read_spr | write_spr}};
//
// Decoding of groups
//
always @(spr_addr)
case (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
`OR1200_SPR_GROUP_WIDTH'd00: unqualified_cs = 32'b00000000_00000000_00000000_00000001;
`OR1200_SPR_GROUP_WIDTH'd01: unqualified_cs = 32'b00000000_00000000_00000000_00000010;
`OR1200_SPR_GROUP_WIDTH'd02: unqualified_cs = 32'b00000000_00000000_00000000_00000100;
`OR1200_SPR_GROUP_WIDTH'd03: unqualified_cs = 32'b00000000_00000000_00000000_00001000;
`OR1200_SPR_GROUP_WIDTH'd04: unqualified_cs = 32'b00000000_00000000_00000000_00010000;
`OR1200_SPR_GROUP_WIDTH'd05: unqualified_cs = 32'b00000000_00000000_00000000_00100000;
`OR1200_SPR_GROUP_WIDTH'd06: unqualified_cs = 32'b00000000_00000000_00000000_01000000;
`OR1200_SPR_GROUP_WIDTH'd07: unqualified_cs = 32'b00000000_00000000_00000000_10000000;
`OR1200_SPR_GROUP_WIDTH'd08: unqualified_cs = 32'b00000000_00000000_00000001_00000000;
`OR1200_SPR_GROUP_WIDTH'd09: unqualified_cs = 32'b00000000_00000000_00000010_00000000;
`OR1200_SPR_GROUP_WIDTH'd10: unqualified_cs = 32'b00000000_00000000_00000100_00000000;
`OR1200_SPR_GROUP_WIDTH'd11: unqualified_cs = 32'b00000000_00000000_00001000_00000000;
`OR1200_SPR_GROUP_WIDTH'd12: unqualified_cs = 32'b00000000_00000000_00010000_00000000;
`OR1200_SPR_GROUP_WIDTH'd13: unqualified_cs = 32'b00000000_00000000_00100000_00000000;
`OR1200_SPR_GROUP_WIDTH'd14: unqualified_cs = 32'b00000000_00000000_01000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd15: unqualified_cs = 32'b00000000_00000000_10000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd16: unqualified_cs = 32'b00000000_00000001_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd17: unqualified_cs = 32'b00000000_00000010_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd18: unqualified_cs = 32'b00000000_00000100_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd19: unqualified_cs = 32'b00000000_00001000_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd20: unqualified_cs = 32'b00000000_00010000_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd21: unqualified_cs = 32'b00000000_00100000_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd22: unqualified_cs = 32'b00000000_01000000_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd23: unqualified_cs = 32'b00000000_10000000_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd24: unqualified_cs = 32'b00000001_00000000_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd25: unqualified_cs = 32'b00000010_00000000_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd26: unqualified_cs = 32'b00000100_00000000_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd27: unqualified_cs = 32'b00001000_00000000_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd28: unqualified_cs = 32'b00010000_00000000_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd29: unqualified_cs = 32'b00100000_00000000_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd30: unqualified_cs = 32'b01000000_00000000_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd31: unqualified_cs = 32'b10000000_00000000_00000000_00000000;
endcase
//
// SPRs System Group
//
//
// What to write into SR
//
assign to_sr[`OR1200_SR_FO:`OR1200_SR_OV] =
(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_FO:`OR1200_SR_OV] :
(write_spr && sr_sel) ? {1'b1, spr_dat_o[`OR1200_SR_FO-1:`OR1200_SR_OV]}:
sr[`OR1200_SR_FO:`OR1200_SR_OV];
assign to_sr[`OR1200_SR_CY] =
(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CY] :
cy_we ? cyforw :
(write_spr && sr_sel) ? spr_dat_o[`OR1200_SR_CY] :
sr[`OR1200_SR_CY];
assign to_sr[`OR1200_SR_F] =
(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_F] :
flag_we ? flagforw :
(write_spr && sr_sel) ? spr_dat_o[`OR1200_SR_F] :
sr[`OR1200_SR_F];
assign to_sr[`OR1200_SR_CE:`OR1200_SR_SM] =
(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CE:`OR1200_SR_SM] :
(write_spr && sr_sel) ? spr_dat_o[`OR1200_SR_CE:`OR1200_SR_SM]:
sr[`OR1200_SR_CE:`OR1200_SR_SM];
//
// Selects for system SPRs
//
assign cfgr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:4] == `OR1200_SPR_CFGR));
assign rf_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:5] == `OR1200_SPR_RF));
assign npc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_NPC));
assign ppc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_PPC));
assign sr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_SR));
assign epcr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EPCR));
assign eear_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EEAR));
assign esr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_ESR));
//
// Write enables for system SPRs
//
assign sr_we = (write_spr && sr_sel) | (branch_op == `OR1200_BRANCHOP_RFE) | flag_we | cy_we;
assign pc_we = (write_spr && (npc_sel | ppc_sel));
assign epcr_we = (write_spr && epcr_sel);
assign eear_we = (write_spr && eear_sel);
assign esr_we = (write_spr && esr_sel);
//
// Output from system SPRs
//
assign sys_data = (spr_dat_cfgr & {32{read_spr & cfgr_sel}}) |
(spr_dat_rf & {32{read_spr & rf_sel}}) |
(spr_dat_npc & {32{read_spr & npc_sel}}) |
(spr_dat_ppc & {32{read_spr & ppc_sel}}) |
({{32-`OR1200_SR_WIDTH{1'b0}},sr} & {32{read_spr & sr_sel}}) |
(epcr & {32{read_spr & epcr_sel}}) |
(eear & {32{read_spr & eear_sel}}) |
({{32-`OR1200_SR_WIDTH{1'b0}},esr} & {32{read_spr & esr_sel}});
//
// Flag alias
//
assign flag = sr[`OR1200_SR_F];
//
// Carry alias
//
assign carry = sr[`OR1200_SR_CY];
//
// Supervision register
//
always @(posedge clk or posedge rst)
if (rst)
sr <= #1 {1'b1, `OR1200_SR_EPH_DEF, {`OR1200_SR_WIDTH-3{1'b0}}, 1'b1};
else if (except_started) begin
sr[`OR1200_SR_SM] <= #1 1'b1;
sr[`OR1200_SR_TEE] <= #1 1'b0;
sr[`OR1200_SR_IEE] <= #1 1'b0;
sr[`OR1200_SR_DME] <= #1 1'b0;
sr[`OR1200_SR_IME] <= #1 1'b0;
end
else if (sr_we)
sr <= #1 to_sr[`OR1200_SR_WIDTH-1:0];
//
// MTSPR/MFSPR interface
//
always @(sprs_op or spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or
spr_dat_dmmu or spr_dat_immu or spr_dat_du or spr_dat_tt) begin
case (sprs_op) // synopsys parallel_case
`OR1200_ALUOP_MTSR : begin
write_spr = 1'b1;
read_spr = 1'b0;
to_wbmux = 32'b0;
end
`OR1200_ALUOP_MFSR : begin
casex (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
`OR1200_SPR_GROUP_TT:
to_wbmux = spr_dat_tt;
`OR1200_SPR_GROUP_PIC:
to_wbmux = spr_dat_pic;
`OR1200_SPR_GROUP_PM:
to_wbmux = spr_dat_pm;
`OR1200_SPR_GROUP_DMMU:
to_wbmux = spr_dat_dmmu;
`OR1200_SPR_GROUP_IMMU:
to_wbmux = spr_dat_immu;
`OR1200_SPR_GROUP_MAC:
to_wbmux = spr_dat_mac;
`OR1200_SPR_GROUP_DU:
to_wbmux = spr_dat_du;
`OR1200_SPR_GROUP_SYS:
to_wbmux = sys_data;
default:
to_wbmux = 32'b0;
endcase
write_spr = 1'b0;
read_spr = 1'b1;
end
default : begin
write_spr = 1'b0;
read_spr = 1'b0;
to_wbmux = 32'b0;
end
endcase
end
endmodule
|
//----------------------------------------------------------------------------
// Wishbone SRAM controller
//----------------------------------------------------------------------------
module wb_sram16 #(
parameter adr_width = 19,
parameter latency = 0 // 0 .. 7
) (
input clk,
input reset,
// Wishbone interface
input wb_stb_i,
input wb_cyc_i,
input wb_tga_i,
output reg wb_ack_o,
input wb_we_i,
input [18:0] wb_adr_i,
input [1:0] wb_sel_i,
input [15:0] wb_dat_i,
output reg [15:0] wb_dat_o,
// SRAM connection
output reg [adr_width-1:0] sram_adr,
inout [15:0] sram_dat,
output reg [1:0] sram_be_n, // Byte Enable
output reg sram_ce_n, // Chip Enable
output reg sram_oe_n, // Output Enable
output reg sram_we_n // Write Enable
);
//----------------------------------------------------------------------------
//
//----------------------------------------------------------------------------
// Wishbone handling
wire wb_rd = wb_stb_i & wb_cyc_i & ~wb_we_i & ~wb_ack_o;
wire wb_wr = wb_stb_i & wb_cyc_i & wb_we_i & ~wb_ack_o;
// Translate wishbone address to sram address
wire [adr_width-1:0] adr = wb_adr_i[adr_width-1:0];
// Tri-State-Driver
reg [15:0] wdat;
reg wdat_oe;
assign sram_dat = wdat_oe ? wdat : 16'bz;
// Latency countdown
reg [2:0] lcount;
//----------------------------------------------------------------------------
// State Machine
//----------------------------------------------------------------------------
parameter s_idle = 0;
parameter s_read = 1;
parameter s_write = 2;
reg [2:0] state;
always @(posedge clk)
begin
if (reset) begin
state <= s_idle;
lcount <= 0;
wb_ack_o <= 0;
end else begin
case (state)
s_idle: begin
wb_ack_o <= 0;
if (wb_rd) begin
sram_ce_n <= 0;
sram_oe_n <= 0;
sram_we_n <= 1;
sram_adr <= adr;
sram_be_n <= 2'b00;
wdat_oe <= 0;
lcount <= latency;
state <= s_read;
end else if (wb_wr) begin
sram_ce_n <= 0;
sram_oe_n <= 1;
sram_we_n <= 0;
sram_adr <= adr;
sram_be_n <= ~wb_sel_i;
wdat <= wb_dat_i;
wdat_oe <= 1;
lcount <= latency;
state <= s_write;
end else begin
sram_ce_n <= 1;
sram_oe_n <= 1;
sram_we_n <= 1;
wdat_oe <= 0;
end
end
s_read: begin
if (lcount != 0) begin
lcount <= lcount - 1;
end else begin
sram_ce_n <= 1;
sram_oe_n <= 1;
sram_we_n <= 1;
wb_dat_o <= sram_dat;
wb_ack_o <= 1;
state <= s_idle;
end
end
s_write: begin
if (lcount != 0) begin
lcount <= lcount - 1;
end else begin
sram_ce_n <= 1;
sram_oe_n <= 1;
sram_we_n <= 1;
wb_ack_o <= 1; // XXX We could acknoledge write XXX
state <= s_idle; // XXX requests 1 cycle ahead XXX
end
end
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O21A_PP_SYMBOL_V
`define SKY130_FD_SC_HVL__O21A_PP_SYMBOL_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__o21a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O21A_PP_SYMBOL_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : EP_MEM.v
// Version : 2.4
//--------------------------------------------------------------------------------
//-- Filename: EP_MEM.v
//--
//-- Description: Endpoint Memory: 8KB organized as 4 x (512 DW) BlockRAM banks.
//-- Block RAM Port A: Read Port
//-- Block RAM Port B: Write Port
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module EP_MEM (
clk_i,
a_rd_a_i_0, // [8:0]
a_rd_d_o_0, // [31:0]
a_rd_en_i_0,
b_wr_a_i_0, // [8:0]
b_wr_d_i_0, // [31:0]
b_wr_en_i_0,
b_rd_d_o_0, // [31:0]
b_rd_en_i_0,
a_rd_a_i_1, // [8:0]
a_rd_d_o_1, // [31:0]
a_rd_en_i_1,
b_wr_a_i_1, // [8:0]
b_wr_d_i_1, // [31:0]
b_wr_en_i_1,
b_rd_d_o_1, // [31:0]
b_rd_en_i_1,
a_rd_a_i_2, // [8:0]
a_rd_d_o_2, // [31:0]
a_rd_en_i_2,
b_wr_a_i_2, // [8:0]
b_wr_d_i_2, // [31:0]
b_wr_en_i_2,
b_rd_d_o_2, // [31:0]
b_rd_en_i_2,
a_rd_a_i_3, // [8:0]
a_rd_d_o_3, // [31:0]
a_rd_en_i_3,
b_wr_a_i_3, // [8:0]
b_wr_d_i_3, // [31:0]
b_wr_en_i_3,
b_rd_d_o_3, // [31:0]
b_rd_en_i_3
);
input clk_i;
input [08:00] a_rd_a_i_0;
output [31:00] a_rd_d_o_0;
input a_rd_en_i_0;
input [08:00] b_wr_a_i_0;
input [31:00] b_wr_d_i_0;
input b_wr_en_i_0;
output [31:00] b_rd_d_o_0;
input b_rd_en_i_0;
input [08:00] a_rd_a_i_1;
output [31:00] a_rd_d_o_1;
input a_rd_en_i_1;
input [08:00] b_wr_a_i_1;
input [31:00] b_wr_d_i_1;
input b_wr_en_i_1;
output [31:00] b_rd_d_o_1;
input b_rd_en_i_1;
input [08:00] a_rd_a_i_2;
output [31:00] a_rd_d_o_2;
input a_rd_en_i_2;
input [08:00] b_wr_a_i_2;
input [31:00] b_wr_d_i_2;
input b_wr_en_i_2;
output [31:00] b_rd_d_o_2;
input b_rd_en_i_2;
input [08:00] a_rd_a_i_3;
output [31:00] a_rd_d_o_3;
input a_rd_en_i_3;
input [08:00] b_wr_a_i_3;
input [31:00] b_wr_d_i_3;
input b_wr_en_i_3;
output [31:00] b_rd_d_o_3;
input b_rd_en_i_3;
//----------------------------------------------------------------
//
// 4 x 512 DWs Buffer Banks (512 x 32 bits + 512 x 4 bits)
//
//----------------------------------------------------------------
RAMB36 #(
.DOA_REG(1), // Optional output registers on A port (0 or 1)
.DOB_REG(1), // Optional output registers on B port (0 or 1)
.INIT_A(36'h000000000), // Initial values on A output port
.INIT_B(36'h000000000), // Initial values on B output port
.RAM_EXTENSION_A("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
.RAM_EXTENSION_B("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
.READ_WIDTH_A(36), // Valid values are 1, 2, 4, 9, 18, or 36
.READ_WIDTH_B(36), // Valid values are 1, 2, 4, 9, 18, or 36
.SIM_COLLISION_CHECK("ALL"), // Collision check enable "ALL", "WARNING_ONLY",
// "GENERATE_X_ONLY" or "NONE
.SRVAL_A(36'h000000000), // Set/Reset value for A port output
.SRVAL_B(36'h000000000), // Set/Reset value for B port output
.WRITE_MODE_A("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
.WRITE_MODE_B("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
.WRITE_WIDTH_A(36), // Valid values are 1, 2, 4, 9, 18, or 36
.WRITE_WIDTH_B(36), // Valid values are 1, 2, 4, 9, 18, or 36
// The following INIT_xx declarations specify the initial contents of the RAM
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
// The next set of INITP_xx are for the parity bits
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000)
) ep_io_mem (
.DOA(a_rd_d_o_0[31:0]), // 32-bit A port data output
.DOB(b_rd_d_o_0[31:0]), // 32-bit B port data output
.DOPA(), // 4-bit A port parity data output
.DOPB(), // 4-bit B port parity data output
.ADDRA({1'b0,a_rd_a_i_0[8:0],6'b0}), // 16-bit A port address input
.ADDRB({1'b0,b_wr_a_i_0[8:0],6'b0}), // 16-bit B port address input
.CLKA(clk_i), // 1-bit A port clock input
.CLKB(clk_i), // 1-bit B port clock input
.DIA(32'b0), // 32-bit A port data input
.DIB(b_wr_d_i_0[31:0]), // 32-bit B port data input
.DIPA(4'b0000), // 4-bit A port parity data input
.DIPB(4'b0), // 4-bit B port parity data input
.ENA(a_rd_en_i_0), // 1-bit A port enable input
.ENB(b_rd_en_i_0), // 1-bit B port enable input
.REGCEA(1'b1), // 1-bit A port register enable input
.REGCEB(1'b1), // 1-bit B port register enable input
.SSRA(1'b0), // 1-bit A port set/reset input
.SSRB(1'b0), // 1-bit B port set/reset input
.WEA(4'b0), // 4-bit A port write enable input
.WEB({b_wr_en_i_0, b_wr_en_i_0, b_wr_en_i_0, b_wr_en_i_0}), // 4-bit B port write enable input
.CASCADEINLATA (1'b0),
.CASCADEINREGA (1'b0),
.CASCADEOUTLATA (),
.CASCADEOUTREGA (),
.CASCADEINLATB (1'b0),
.CASCADEINREGB (1'b0),
.CASCADEOUTLATB (),
.CASCADEOUTREGB ()
);
RAMB36 #(
.DOA_REG(1), // Optional output registers on A port (0 or 1)
.DOB_REG(1), // Optional output registers on B port (0 or 1)
.INIT_A(36'h000000000), // Initial values on A output port
.INIT_B(36'h000000000), // Initial values on B output port
.RAM_EXTENSION_A("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
.RAM_EXTENSION_B("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
.READ_WIDTH_A(36), // Valid values are 1, 2, 4, 9, 18, or 36
.READ_WIDTH_B(36), // Valid values are 1, 2, 4, 9, 18, or 36
.SIM_COLLISION_CHECK("ALL"), // Collision check enable "ALL", "WARNING_ONLY",
// "GENERATE_X_ONLY" or "NONE
.SRVAL_A(36'h000000000), // Set/Reset value for A port output
.SRVAL_B(36'h000000000), // Set/Reset value for B port output
.WRITE_MODE_A("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
.WRITE_MODE_B("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
.WRITE_WIDTH_A(36), // Valid values are 1, 2, 4, 9, 18, or 36
.WRITE_WIDTH_B(36), // Valid values are 1, 2, 4, 9, 18, or 36
// The following INIT_xx declarations specify the initial contents of the RAM
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
// The next set of INITP_xx are for the parity bits
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000)
) ep_mem32 (
.DOA(a_rd_d_o_1[31:0]), // 32-bit A port data output
.DOB(b_rd_d_o_1[31:0]), // 32-bit B port data output
.DOPA(), // 4-bit A port parity data output
.DOPB(), // 4-bit B port parity data output
.ADDRA({1'b0,a_rd_a_i_1[8:0],6'b0}), // 16-bit A port address input
.ADDRB({1'b0,b_wr_a_i_1[8:0],6'b0}), // 16-bit B port address input
.CLKA(clk_i), // 1-bit A port clock input
.CLKB(clk_i), // 1-bit B port clock input
.DIA(32'b0), // 32-bit A port data input
.DIB(b_wr_d_i_1[31:0]), // 32-bit B port data input
.DIPA(4'b0000), // 4-bit A port parity data input
.DIPB(4'b0), // 4-bit B port parity data input
.ENA(a_rd_en_i_1), // 1-bit A port enable input
.ENB(b_rd_en_i_1), // 1-bit B port enable input
.REGCEA(1'b1), // 1-bit A port register enable input
.REGCEB(1'b1), // 1-bit B port register enable input
.SSRA(1'b0), // 1-bit A port set/reset input
.SSRB(1'b0), // 1-bit B port set/reset input
.WEA(4'b0), // 4-bit A port write enable input
.WEB({b_wr_en_i_1, b_wr_en_i_1, b_wr_en_i_1, b_wr_en_i_1}), // 4-bit B port write enable input
.CASCADEINLATA (1'b0),
.CASCADEINREGA (1'b0),
.CASCADEOUTLATA (),
.CASCADEOUTREGA (),
.CASCADEINLATB (1'b0),
.CASCADEINREGB (1'b0),
.CASCADEOUTLATB (),
.CASCADEOUTREGB ()
);
RAMB36 #(
.DOA_REG(1), // Optional output registers on A port (0 or 1)
.DOB_REG(1), // Optional output registers on B port (0 or 1)
.INIT_A(36'h000000000), // Initial values on A output port
.INIT_B(36'h000000000), // Initial values on B output port
.RAM_EXTENSION_A("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
.RAM_EXTENSION_B("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
.READ_WIDTH_A(36), // Valid values are 1, 2, 4, 9, 18, or 36
.READ_WIDTH_B(36), // Valid values are 1, 2, 4, 9, 18, or 36
.SIM_COLLISION_CHECK("ALL"), // Collision check enable "ALL", "WARNING_ONLY",
// "GENERATE_X_ONLY" or "NONE
.SRVAL_A(36'h000000000), // Set/Reset value for A port output
.SRVAL_B(36'h000000000), // Set/Reset value for B port output
.WRITE_MODE_A("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
.WRITE_MODE_B("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
.WRITE_WIDTH_A(36), // Valid values are 1, 2, 4, 9, 18, or 36
.WRITE_WIDTH_B(36), // Valid values are 1, 2, 4, 9, 18, or 36
// The following INIT_xx declarations specify the initial contents of the RAM
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
// The next set of INITP_xx are for the parity bits
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000)
) ep_mem64 (
.DOA(a_rd_d_o_2[31:0]), // 32-bit A port data output
.DOB(b_rd_d_o_2[31:0]), // 32-bit B port data output
.DOPA(), // 4-bit A port parity data output
.DOPB(), // 4-bit B port parity data output
.ADDRA({1'b0,a_rd_a_i_2[8:0],6'b0}), // 16-bit A port address input
.ADDRB({1'b0,b_wr_a_i_2[8:0],6'b0}), // 16-bit B port address input
.CLKA(clk_i), // 1-bit A port clock input
.CLKB(clk_i), // 1-bit B port clock input
.DIA(32'b0), // 32-bit A port data input
.DIB(b_wr_d_i_2[31:0]), // 32-bit B port data input
.DIPA(4'b0000), // 4-bit A port parity data input
.DIPB(4'b0), // 4-bit B port parity data input
.ENA(a_rd_en_i_2), // 1-bit A port enable input
.ENB(b_rd_en_i_2), // 1-bit B port enable input
.REGCEA(1'b1), // 1-bit A port register enable input
.REGCEB(1'b1), // 1-bit B port register enable input
.SSRA(1'b0), // 1-bit A port set/reset input
.SSRB(1'b0), // 1-bit B port set/reset input
.WEA(4'b0), // 4-bit A port write enable input
.WEB({b_wr_en_i_2, b_wr_en_i_2, b_wr_en_i_2, b_wr_en_i_2}), // 4-bit B port write enable input
.CASCADEINLATA (1'b0),
.CASCADEINREGA (1'b0),
.CASCADEOUTLATA (),
.CASCADEOUTREGA (),
.CASCADEINLATB (1'b0),
.CASCADEINREGB (1'b0),
.CASCADEOUTLATB (),
.CASCADEOUTREGB ()
);
RAMB36 #(
.DOA_REG(1), // Optional output registers on A port (0 or 1)
.DOB_REG(1), // Optional output registers on B port (0 or 1)
.INIT_A(36'h000000000), // Initial values on A output port
.INIT_B(36'h000000000), // Initial values on B output port
.RAM_EXTENSION_A("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
.RAM_EXTENSION_B("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
.READ_WIDTH_A(36), // Valid values are 1, 2, 4, 9, 18, or 36
.READ_WIDTH_B(36), // Valid values are 1, 2, 4, 9, 18, or 36
.SIM_COLLISION_CHECK("ALL"), // Collision check enable "ALL", "WARNING_ONLY",
// "GENERATE_X_ONLY" or "NONE
.SRVAL_A(36'h000000000), // Set/Reset value for A port output
.SRVAL_B(36'h000000000), // Set/Reset value for B port output
.WRITE_MODE_A("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
.WRITE_MODE_B("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
.WRITE_WIDTH_A(36), // Valid values are 1, 2, 4, 9, 18, or 36
.WRITE_WIDTH_B(36), // Valid values are 1, 2, 4, 9, 18, or 36
// The following INIT_xx declarations specify the initial contents of the RAM
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
// The next set of INITP_xx are for the parity bits
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000)
) ep_mem_erom (
.DOA(a_rd_d_o_3[31:0]), // 32-bit A port data output
.DOB(b_rd_d_o_3[31:0]), // 32-bit B port data output
.DOPA(), // 4-bit A port parity data output
.DOPB(), // 4-bit B port parity data output
.ADDRA({1'b0,a_rd_a_i_3[8:0],6'b0}), // 16-bit A port address input
.ADDRB({1'b0,b_wr_a_i_3[8:0],6'b0}), // 16-bit B port address input
.CLKA(clk_i), // 1-bit A port clock input
.CLKB(clk_i), // 1-bit B port clock input
.DIA(32'b0), // 32-bit A port data input
.DIB(b_wr_d_i_3[31:0]), // 32-bit B port data input
.DIPA(4'b0000), // 4-bit A port parity data input
.DIPB(4'b0), // 4-bit B port parity data input
.ENA(a_rd_en_i_3), // 1-bit A port enable input
.ENB(b_rd_en_i_3), // 1-bit B port enable input
.REGCEA(1'b1), // 1-bit A port register enable input
.REGCEB(1'b1), // 1-bit B port register enable input
.SSRA(1'b0), // 1-bit A port set/reset input
.SSRB(1'b0), // 1-bit B port set/reset input
.WEA(4'b0), // 4-bit A port write enable input
.WEB({b_wr_en_i_3, b_wr_en_i_3, b_wr_en_i_3, b_wr_en_i_3}), // 4-bit B port write enable input
.CASCADEINLATA (1'b0),
.CASCADEINREGA (1'b0),
.CASCADEOUTLATA (),
.CASCADEOUTREGA (),
.CASCADEINLATB (1'b0),
.CASCADEINREGB (1'b0),
.CASCADEOUTLATB (),
.CASCADEOUTREGB ()
);
endmodule
|
`include "rtl/verilog/or1200/or1200_defines.v"
`include "rtl/verilog/bench_timescale.v"
//
// Top of OR1200 inside test bench
//
`define OR1200_TOP xess_top.i_xess_fpga.or1200_top
module or1200_monitor2;
wire [31:0] r0;
wire [31:0] r1;
wire [31:0] r2;
wire [31:0] r3;
wire [31:0] r4;
wire [31:0] r5;
wire [31:0] r6;
wire [31:0] r7;
wire [31:0] r8;
wire [31:0] r9;
wire [31:0] r10;
wire [31:0] r11;
wire [31:0] r12;
wire [31:0] r13;
wire [31:0] r14;
wire [31:0] r15;
wire [31:0] r16;
wire [31:0] r17;
wire [31:0] r18;
wire [31:0] r19;
wire [31:0] r20;
wire [31:0] r21;
wire [31:0] r22;
wire [31:0] r23;
wire [31:0] r24;
wire [31:0] r25;
wire [31:0] r26;
wire [31:0] r27;
wire [31:0] r28;
wire [31:0] r29;
wire [31:0] r30;
wire [31:0] r31;
assign r0 = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[32*0+31:32*0];
assign r1 = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[32*1+31:32*1];
assign r2 = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[32*2+31:32*2];
assign r3 = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[32*3+31:32*3];
assign r4 = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[32*4+31:32*4];
assign r5 = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[32*5+31:32*5];
assign r6 = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[32*6+31:32*6];
assign r7 = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[32*7+31:32*7];
assign r8 = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[32*8+31:32*8];
assign r9 = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[32*9+31:32*9];
assign r10 = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[32*10+31:32*10];
assign r11 = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[32*11+31:32*11];
assign r12 = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[32*12+31:32*12];
assign r13 = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[32*13+31:32*13];
assign r14 = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[32*14+31:32*14];
assign r15 = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[32*15+31:32*15];
assign r16 = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[32*16+31:32*16];
assign r17 = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[32*17+31:32*17];
assign r18 = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[32*18+31:32*18];
assign r19 = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[32*19+31:32*19];
assign r20 = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[32*20+31:32*20];
assign r21 = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[32*21+31:32*21];
assign r22 = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[32*22+31:32*22];
assign r23 = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[32*23+31:32*23];
assign r24 = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[32*24+31:32*24];
assign r25 = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[32*25+31:32*25];
assign r26 = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[32*26+31:32*26];
assign r27 = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[32*27+31:32*27];
assign r28 = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[32*28+31:32*28];
assign r29 = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[32*29+31:32*29];
assign r30 = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[32*30+31:32*30];
assign r31 = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[32*31+31:32*31];
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02:09:44 10/15/2013
// Design Name: Logica_Bola
// Module Name: C:/Users/Fabian/Documents/GitHub/taller-diseno-digital/Lab4/lab_pong/test_logica_bola.v
// Project Name: lab_pong
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Logica_Bola
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_logica_bola;
// Inputs
reg clock;
reg reset;
reg actualizar_posicion;
reg revisar_bordes;
reg choque_barra;
// Outputs
wire [9:0] ball_x;
wire [8:0] ball_y;
// Instantiate the Unit Under Test (UUT)
Logica_Bola uut (
.clock(clock),
.reset(reset),
.actualizar_posicion(actualizar_posicion),
.revisar_bordes(revisar_bordes),
.choque_barra(choque_barra),
.ball_x(ball_x),
.ball_y(ball_y)
);
initial begin
// Initialize Inputs
clock = 0;
reset = 0;
actualizar_posicion = 0;
revisar_bordes = 0;
choque_barra = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR3B_4_V
`define SKY130_FD_SC_HS__NOR3B_4_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog wrapper for nor3b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nor3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nor3b_4 (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND
);
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
sky130_fd_sc_hs__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nor3b_4 (
Y ,
A ,
B ,
C_N
);
output Y ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR3B_4_V
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2017 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2018.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Analog Auxiliary SYSMON Input Buffer
// /___/ /\ Filename : IBUF_ANALOG.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// 10/30/13 - Initial version.
// 02/04/15 - 845545 - Remove pulldown and strength specification.
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module IBUF_ANALOG
`ifdef XIL_TIMING
#(
parameter LOC = "UNPLACED"
)
`endif
(
output O,
input I
);
// define constants
localparam MODULE_NAME = "IBUF_ANALOG";
tri0 glblGSR = glbl.GSR;
// begin behavioral model
assign O = I;
// end behavioral model
`ifndef XIL_XECLIB
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
`endif
endmodule
`endcelldefine
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUFINV_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__BUFINV_BEHAVIORAL_PP_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__bufinv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUFINV_BEHAVIORAL_PP_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12.07.2017 22:01:56
// Design Name:
// Module Name: t_ex
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments: Just like with t_id, full testing of alu.v is not needed
// as that was done in t_alu. This testbench tests the multiplexers in this block
// to make sure they work as intended, as well as the wires are connected
// correctly. The branch adder is also given a simple test too.
//
//////////////////////////////////////////////////////////////////////////////////
module t_ex;
// Inputs
reg [31:0] pcplus4, srca, regread2, signimm;
reg [4:0] rt, rd;
reg [2:0] alucontrol;
reg alusrc, regdst, regwrite1, memtoreg1, memwrite1, branch1;
// Outputs
wire [31:0] aluresult, pcbranch, writedata;
wire [4:0] writereg;
wire regwrite2, memtoreg2, memwrite2, branch2, zerowire;
execute uut(
.ALUResult( aluresult ),
.PCBranchE( pcbranch ),
.WriteDataE( writedata ),
.WriteRegE( writereg ),
.RegWriteE2( regwrite2 ),
.MemToRegE2( memtoreg2 ),
.MemWriteE2( memwrite2 ),
.BranchE2( branch2 ),
.ZerowireE( zerowire ),
.PCPlus4E( pcplus4 ),
.srcA( srca ),
.RegRead2( regread2 ),
.SignImmE( signimm ),
.rt( rt ),
.rd( rd ),
.ALUControlE( alucontrol ),
.ALUSrcE( alusrc ),
.RegDstE( regdst ),
.RegWriteE1( regwrite1 ),
.MemToRegE1( memtoreg1 ),
.MemWriteE1( memwrite1 ),
.BranchE1( branch1 )
);
initial begin
// Initialise the inputs
pcplus4 = 0; srca = 0; regread2 = 0; signimm = 0;
rt = 0; rd = 0;
alucontrol = 0;
alusrc = 0; regdst = 0; regwrite1 = 0; memtoreg1 = 0; memwrite1 = 0; branch1 = 0;
// display test signals
$display(srca);
$display(regread2);
// Wait 100ns for global resets
#100;
// Test RegDst
rt = 5'b01000; rd = 5'b01001; regdst = 1;
#20 regdst = 0; // writereg should switch from 0x09 to 0x08
#20 rt = 0; rd = 0; // reset
#100;
// Test ALUSrc with ALUControl (i.e. simulate a I-type and R-type instruction)
#20 srca = 32'h00001111; regread2 = 32'hFFFF0000; signimm = 32'hFFFFFFFF; alusrc = 0; alucontrol = 3'b001; // r-type or instruction
// expected output should be 00001111 OR FFFF0000 = FFFF1111; writedata = 32'hFFFF0000; zerowire = 0;
#20 alusrc = 1; // i-type or instruction, expected output should be 00001111 OR FFFFFFFF = FFFFFFFF; writedata = 32'hFFFF0000; zerowire = 0;
#20 srca = 0; regread2 = 0; signimm = 0; alusrc = 0; alucontrol = 3'b000; // reset
#100;
// Test Branch Circuit
pcplus4 = 32'h00000004; signimm = 32'h00000001; // expected output: pcbranch = 4 + (1<<2) = 32'h00000008;
// Test Follow-through signals
#20 regwrite1 = 1; memtoreg1 = 1; memwrite1 = 1; branch1 = 1;
// expected output regwrite2 = 1; memtoreg2 = 1; memwrite2 = 1; branch2 = 1;
#20 regwrite1 = 0; memtoreg1 = 0; memwrite1 = 0; branch1 = 0;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DIODE_BLACKBOX_V
`define SKY130_FD_SC_LP__DIODE_BLACKBOX_V
/**
* diode: Antenna tie-down diode.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__diode (
DIODE
);
input DIODE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DIODE_BLACKBOX_V
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/12.1/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $
// $Revision: #1 $
// $Date: 2012/08/12 $
// $Author: swbranch $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_pipeline_base (
clk,
reset,
in_ready,
in_valid,
in_data,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter PIPELINE_READY = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input clk;
input reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
reg full0;
reg full1;
reg [DATA_WIDTH-1:0] data0;
reg [DATA_WIDTH-1:0] data1;
assign out_valid = full1;
assign out_data = data1;
generate if (PIPELINE_READY == 1)
begin : REGISTERED_READY_PLINE
assign in_ready = !full0;
always @(posedge clk, posedge reset) begin
if (reset) begin
data0 <= {DATA_WIDTH{1'b0}};
data1 <= {DATA_WIDTH{1'b0}};
end else begin
// ----------------------------
// always load the second slot if we can
// ----------------------------
if (~full0)
data0 <= in_data;
// ----------------------------
// first slot is loaded either from the second,
// or with new data
// ----------------------------
if (~full1 || (out_ready && out_valid)) begin
if (full0)
data1 <= data0;
else
data1 <= in_data;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
full0 <= 1'b0;
full1 <= 1'b0;
end else begin
// no data in pipeline
if (~full0 & ~full1) begin
if (in_valid) begin
full1 <= 1'b1;
end
end // ~f1 & ~f0
// one datum in pipeline
if (full1 & ~full0) begin
if (in_valid & ~out_ready) begin
full0 <= 1'b1;
end
// back to empty
if (~in_valid & out_ready) begin
full1 <= 1'b0;
end
end // f1 & ~f0
// two data in pipeline
if (full1 & full0) begin
// go back to one datum state
if (out_ready) begin
full0 <= 1'b0;
end
end // end go back to one datum stage
end
end
end
else
begin : UNREGISTERED_READY_PLINE
// in_ready will be a pass through of the out_ready signal as it is not registered
assign in_ready = (~full1) | out_ready;
always @(posedge clk or posedge reset) begin
if (reset) begin
data1 <= 'b0;
full1 <= 1'b0;
end
else begin
if (in_ready) begin
data1 <= in_data;
full1 <= in_valid;
end
end
end
end
endgenerate
endmodule
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_SYSTEMV3_CH0_DETECTION_TRUE (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg d1_data_in;
reg d2_data_in;
wire data_in;
reg edge_capture;
wire edge_capture_wr_strobe;
wire edge_detect;
wire read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({1 {(address == 0)}} & data_in) |
({1 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture <= 0;
else if (edge_detect)
edge_capture <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_data_in <= 0;
d2_data_in <= 0;
end
else if (clk_en)
begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = d1_data_in & ~d2_data_in;
endmodule
|
//======================================================================
//
// tb_sha256_stream.v
// -----------
// Testbench for the SHA-256 stream interface wrapper.
//
//
// Author: Olof Kindgren
// Copyright (c) 2016, Olof Kindgren
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module tb_sha256_stream();
vlog_tb_utils vtu();
parameter DW = 32;
reg clk = 1'b1;
reg rst = 1'b1;
wire [DW-1:0] tdata;
wire tvalid;
wire tready;
wire [511:0] tdata_resized;
wire tvalid_resized;
wire tready_resized;
wire [255:0] digest;
wire digest_valid;
always #5 clk <= !clk;
initial #20 rst = 1'b0;
stream_writer
#(.WIDTH (DW),
.MAX_BLOCK_SIZE (1))
writer
(.clk (clk),
.stream_m_data_o (tdata),
.stream_m_valid_o (tvalid),
.stream_m_ready_i (tready));
stream_upsizer
#(.DW_IN (DW),
.SCALE (512/DW),
.BIG_ENDIAN(1))
upsizer
(.clk (clk),
.rst (rst),
//Slave Interface
.s_data_i (tdata),
.s_valid_i (tvalid),
.s_ready_o (tready),
//Master Interface
.m_data_o (tdata_resized),
.m_valid_o (tvalid_resized),
.m_ready_i (tready_resized));
sha256_stream dut
(.clk (clk),
.rst (rst),
.mode (1'b1),
.s_tdata_i (tdata_resized),
.s_tlast_i (1'b0),
.s_tvalid_i (tvalid_resized),
.s_tready_o (tready_resized),
.digest_o (digest),
.digest_valid_o (digest_valid));
integer digested_blocks = 0;
always @(posedge digest_valid)
digested_blocks = digested_blocks + 1;
reg [DW-1:0] word;
reg [1024*8-1:0] filename = "";
integer filesize;
integer f;
integer c;
reg [255:0] expected_sha;
initial begin
if (!$value$plusargs("file=%s", filename)) begin
$display("No file specified");
$finish;
end
if (!$value$plusargs("expected_sha=%d", expected_sha)) begin
$display("No expected SHA specified. Will only print SHA, not verify");
end
@(negedge rst);
@(posedge clk);
f = $fopen(filename, "rb");
c = $fread(word, f);
while (c) begin
writer.write_word(word);
c = $fread(word, f);
end
filesize = $ftell(f);
$fclose(f);
while(digested_blocks*64 < filesize)
@(posedge clk);
$display("%h", digest);
if (expected_sha)
if (expected_sha == digest)
$display("SHA ok");
else
$display("SHA failed! Expected %h", expected_sha);
$finish;
end
endmodule
|
(** * Hoare: Hoare Logic, Part I *)
Set Warnings "-notation-overridden,-parsing".
From PLF Require Import Maps.
From Coq Require Import Bool.Bool.
From Coq Require Import Arith.Arith.
From Coq Require Import Arith.EqNat.
From Coq Require Import Arith.PeanoNat. Import Nat.
From Coq Require Import Lia.
From PLF Require Export Imp.
(** In the final chaper of _Logical Foundations_ (_Software
Foundations_, volume 1), we began applying the mathematical tools
developed in the first part of the course to studying the theory
of a small programming language, Imp.
- We defined a type of _abstract syntax trees_ for Imp, together
with an _evaluation relation_ (a partial function on states)
that specifies the _operational semantics_ of programs.
The language we defined, though small, captures some of the key
features of full-blown languages like C, C++, and Java,
including the fundamental notion of mutable state and some
common control structures.
- We proved a number of _metatheoretic properties_ -- "meta" in
the sense that they are properties of the language as a whole,
rather than of particular programs in the language. These
included:
- determinism of evaluation
- equivalence of some different ways of writing down the
definitions (e.g., functional and relational definitions of
arithmetic expression evaluation)
- guaranteed termination of certain classes of programs
- correctness (in the sense of preserving meaning) of a number
of useful program transformations
- behavioral equivalence of programs (in the [Equiv]
chapter). *)
(** If we stopped here, we would already have something useful: a set
of tools for defining and discussing programming languages and
language features that are mathematically precise, flexible, and
easy to work with, applied to a set of key properties. All of
these properties are things that language designers, compiler
writers, and users might care about knowing. Indeed, many of them
are so fundamental to our understanding of the programming
languages we deal with that we might not consciously recognize
them as "theorems." But properties that seem intuitively obvious
can sometimes be quite subtle (sometimes also subtly wrong!).
We'll return to the theme of metatheoretic properties of whole
languages later in this volume when we discuss _types_ and _type
soundness_. In this chapter, though, we turn to a different set
of issues.
*)
(** Our goal is to carry out some simple examples of _program
verification_ -- i.e., to use the precise definition of Imp to
prove formally that particular programs satisfy particular
specifications of their behavior. We'll develop a reasoning
system called _Floyd-Hoare Logic_ -- often shortened to just
_Hoare Logic_ -- in which each of the syntactic constructs of Imp
is equipped with a generic "proof rule" that can be used to reason
compositionally about the correctness of programs involving this
construct.
Hoare Logic originated in the 1960s, and it continues to be the
subject of intensive research right up to the present day. It
lies at the core of a multitude of tools that are being used in
academia and industry to specify and verify real software systems.
Hoare Logic combines two beautiful ideas: a natural way of writing
down _specifications_ of programs, and a _compositional proof
technique_ for proving that programs are correct with respect to
such specifications -- where by "compositional" we mean that the
structure of proofs directly mirrors the structure of the programs
that they are about. *)
(* ################################################################# *)
(** * Assertions *)
(** An _assertion_ is a claim about the current state of memory. We will
use assertions to write program specifications. *)
Definition Assertion := state -> Prop.
(** For example,
- [fun st => st X = 3] holds if the value of [X] according to [st] is [3],
- [fun st => True] always holds, and
- [fun st => False] never holds. *)
(** **** Exercise: 1 star, standard, optional (assertions)
Paraphrase the following assertions in English (or your favorite
natural language). *)
Module ExAssertions.
Definition assn1 : Assertion := fun st => st X <= st Y.
Definition assn2 : Assertion :=
fun st => st X = 3 \/ st X <= st Y.
Definition assn3 : Assertion :=
fun st => st Z * st Z <= st X /\
~ (((S (st Z)) * (S (st Z))) <= st X).
Definition assn4 : Assertion :=
fun st => st Z = max (st X) (st Y).
(* FILL IN HERE *)
End ExAssertions.
(** [] *)
(** This way of writing assertions can be a little bit heavy,
for two reasons: (1) every single assertion that we ever write is
going to begin with [fun st => ]; and (2) this state [st] is the
only one that we ever use to look up variables in assertions (we
will never need to talk about two different memory states at the
same time). For discussing examples informally, we'll adopt some
simplifying conventions: we'll drop the initial [fun st =>], and
we'll write just [X] to mean [st X]. Thus, instead of writing
fun st => st X = m
we'll write just
X = m
*)
(** This example also illustrates a convention that we'll use
throughout the Hoare Logic chapters: in informal assertions,
capital letters like [X], [Y], and [Z] are Imp variables, while
lowercase letters like [x], [y], [m], and [n] are ordinary Coq
variables (of type [nat]). This is why, when translating from
informal to formal, we replace [X] with [st X] but leave [m]
alone. *)
(** Given two assertions [P] and [Q], we say that [P] _implies_ [Q],
written [P ->> Q], if, whenever [P] holds in some state [st], [Q]
also holds. *)
Definition assert_implies (P Q : Assertion) : Prop :=
forall st, P st -> Q st.
Declare Scope hoare_spec_scope.
Notation "P ->> Q" := (assert_implies P Q)
(at level 80) : hoare_spec_scope.
Open Scope hoare_spec_scope.
(** (The [hoare_spec_scope] annotation here tells Coq that this
notation is not global but is intended to be used in particular
contexts. The [Open Scope] tells Coq that this file is one such
context.) *)
(** We'll also want the "iff" variant of implication between
assertions: *)
Notation "P <<->> Q" :=
(P ->> Q /\ Q ->> P) (at level 80) : hoare_spec_scope.
(** Our convention can be implemented uses Coq coercions and anotation
scopes (much as we did with [%imp] in [Imp]) to automatically
lift [aexp]s, numbers, and [Prop]s into [Assertion]s when they appear
in the [%assertion] scope or when Coq knows the type of an
expression is [Assertion]. *)
Definition Aexp : Type := state -> nat.
Definition assert_of_Prop (P : Prop) : Assertion := fun _ => P.
Definition Aexp_of_nat (n : nat) : Aexp := fun _ => n.
Definition Aexp_of_aexp (a : aexp) : Aexp := fun st => aeval st a.
Coercion assert_of_Prop : Sortclass >-> Assertion.
Coercion Aexp_of_nat : nat >-> Aexp.
Coercion Aexp_of_aexp : aexp >-> Aexp.
Arguments assert_of_Prop /.
Arguments Aexp_of_nat /.
Arguments Aexp_of_aexp /.
Declare Scope assertion_scope.
Bind Scope assertion_scope with Assertion.
Bind Scope assertion_scope with Aexp.
Delimit Scope assertion_scope with assertion.
Notation assert P := (P%assertion : Assertion).
Notation mkAexp a := (a%assertion : Aexp).
Notation "~ P" := (fun st => ~ assert P st) : assertion_scope.
Notation "P /\ Q" := (fun st => assert P st /\ assert Q st) : assertion_scope.
Notation "P \/ Q" := (fun st => assert P st \/ assert Q st) : assertion_scope.
Notation "P -> Q" := (fun st => assert P st -> assert Q st) : assertion_scope.
Notation "P <-> Q" := (fun st => assert P st <-> assert Q st) : assertion_scope.
Notation "a = b" := (fun st => mkAexp a st = mkAexp b st) : assertion_scope.
Notation "a <> b" := (fun st => mkAexp a st <> mkAexp b st) : assertion_scope.
Notation "a <= b" := (fun st => mkAexp a st <= mkAexp b st) : assertion_scope.
Notation "a < b" := (fun st => mkAexp a st < mkAexp b st) : assertion_scope.
Notation "a >= b" := (fun st => mkAexp a st >= mkAexp b st) : assertion_scope.
Notation "a > b" := (fun st => mkAexp a st > mkAexp b st) : assertion_scope.
Notation "a + b" := (fun st => mkAexp a st + mkAexp b st) : assertion_scope.
Notation "a - b" := (fun st => mkAexp a st - mkAexp b st) : assertion_scope.
Notation "a * b" := (fun st => mkAexp a st * mkAexp b st) : assertion_scope.
(** One small limitation of this approach is that we don't have
an automatic way to coerce function applications that appear
within an assertion to make appropriate use of the state.
Instead, we use an explicit [ap] operator to lift the function. *)
Definition ap {X} (f : nat -> X) (x : Aexp) :=
fun st => f (x st).
Definition ap2 {X} (f : nat -> nat -> X) (x : Aexp) (y : Aexp) (st : state) :=
f (x st) (y st).
Module ExPrettyAssertions.
Definition ex1 : Assertion := X = 3.
Definition ex2 : Assertion := True.
Definition ex3 : Assertion := False.
Definition assn1 : Assertion := X <= Y.
Definition assn2 : Assertion := X = 3 \/ X <= Y.
Definition assn3 : Assertion :=
Z * Z <= X /\ ~ (((ap S Z) * (ap S Z)) <= X).
Definition assn4 : Assertion :=
Z = ap2 max X Y.
End ExPrettyAssertions.
(* ################################################################# *)
(** * Hoare Triples, Informally *)
(** A _Hoare triple_ is a claim about the state before and after executing
a command. A standard notation is
{P} c {Q}
meaning:
- If command [c] begins execution in a state satisfying assertion [P],
- and if [c] eventually terminates in some final state,
- then that final state will satisfy the assertion [Q].
Assertion [P] is called the _precondition_ of the triple, and [Q] is
the _postcondition_.
Because single braces are already used in other ways in Coq, we'll write
Hoare triples with double braces:
{{P}} c {{Q}}
*)
(**
For example,
- [{{X = 0}} X := X + 1 {{X = 1}}] is a valid Hoare triple,
stating that command [X := X + 1] would transform a state in which
[X = 0] to a state in which [X = 1].
- [{{X = m}} X := X + 1 {{X = m + 1}}], is also a valid Hoare triple.
It's even more descriptive of the exact behavior of that command than
the previous example. *)
(** **** Exercise: 1 star, standard, optional (triples)
Paraphrase the following Hoare triples in English.
1) {{True}} c {{X = 5}}
2) forall m, {{X = m}} c {{X = m + 5)}}
3) {{X <= Y}} c {{Y <= X}}
4) {{True}} c {{False}}
5) forall m,
{{X = m}}
c
{{Y = real_fact m}}
6) forall m,
{{X = m}}
c
{{(Z * Z) <= m /\ ~ (((S Z) * (S Z)) <= m)}}
*)
(*
1) {{True}} c {{X = 5}}
c results in 5 assigned in variable X.
2) forall m, {{X = m}} c {{X = m + 5)}}
c adds 5 to X.
3) {{X <= Y}} c {{Y <= X}}
if X <= Y, c results in Y <= X.
4) {{True}} c {{False}}
c never terminates.
5) forall m,
{{X = m}}
c
{{Y = real_fact m}}
c sets Y to real_fact X.
6) forall m,
{{X = m}}
c
{{(Z * Z) <= m /\ ~ (((S Z) * (S Z)) <= m)}}
when input with X = m, c converts the state into that
that (Z + 1) * (Z + 1) > m.
*)
(* [] *)
(** **** Exercise: 1 star, standard, optional (valid_triples)
Which of the following Hoare triples are _valid_ -- i.e., the
claimed relation between [P], [c], and [Q] is true?
1) {{True}} X := 5 {{X = 5}}
2) {{X = 2}} X := X + 1 {{X = 3}}
3) {{True}} X := 5; Y := 0 {{X = 5}}
4) {{X = 2 /\ X = 3}} X := 5 {{X = 0}}
5) {{True}} skip {{False}}
6) {{False}} skip {{True}}
7) {{True}} while true do skip end {{False}}
8) {{X = 0}}
while X = 0 do X := X + 1 end
{{X = 1}}
9) {{X = 1}}
while ~(X = 0) do X := X + 1 end
{{X = 100}}
*)
(*
1) {{True}} X := 5 {{X = 5}}
valid
2) {{X = 2}} X := X + 1 {{X = 3}}
valid
3) {{True}} X := 5; Y := 0 {{X = 5}}
valid
4) {{X = 2 /\ X = 3}} X := 5 {{X = 0}}
invalid
5) {{True}} skip {{False}}
invalid
6) {{False}} skip {{True}}
valid
7) {{True}} while true do skip end {{False}}
valid
8) {{X = 0}}
while X = 0 do X := X + 1 end
{{X = 1}}
valid
9) {{X = 1}}
while ~(X = 0) do X := X + 1 end
{{X = 100}}
valid
*)
(* [] *)
(* ################################################################# *)
(** * Hoare Triples, Formally *)
(** We can formalize Hoare triples and their notation in Coq as follows: *)
Definition hoare_triple
(P : Assertion) (c : com) (Q : Assertion) : Prop :=
forall st st',
st =[ c ]=> st' ->
P st ->
Q st'.
Notation "{{ P }} c {{ Q }}" :=
(hoare_triple P c Q) (at level 90, c custom com at level 99)
: hoare_spec_scope.
Check ({{True}} X := 0 {{True}}).
(** **** Exercise: 1 star, standard (hoare_post_true) *)
(** Prove that if [Q] holds in every state, then any triple with [Q]
as its postcondition is valid. *)
Theorem hoare_post_true : forall (P Q : Assertion) c,
(forall st, Q st) ->
{{P}} c {{Q}}.
Proof.
intros; intro; intros.
apply H.
Qed.
(** [] *)
(** **** Exercise: 1 star, standard (hoare_pre_false) *)
(** Prove that if [P] holds in no state, then any triple with [P] as
its precondition is valid. *)
Ltac intro_all := repeat intro.
Theorem hoare_pre_false : forall (P Q : Assertion) c,
(forall st, ~ (P st)) ->
{{P}} c {{Q}}.
Proof.
intro_all.
apply H in H1. inversion H1.
Qed.
(** [] *)
(* ################################################################# *)
(** * Proof Rules *)
(** The goal of Hoare logic is to provide a _compositional_
method for proving the validity of specific Hoare triples. That
is, we want the structure of a program's correctness proof to
mirror the structure of the program itself. To this end, in the
sections below, we'll introduce a rule for reasoning about each of
the different syntactic forms of commands in Imp -- one for
assignment, one for sequencing, one for conditionals, etc. -- plus
a couple of "structural" rules for gluing things together. We
will then be able to prove programs correct using these proof
rules, without ever unfolding the definition of [hoare_triple]. *)
(* ================================================================= *)
(** ** Assignment *)
(** The rule for assignment is the most fundamental of the Hoare
logic proof rules. Here's how it works.
Consider this incomplete Hoare triple:
{{ ??? }} X := Y {{ X = 1 }}
We want to assign [Y] to [X] and finish in a state where [X] is [1].
What could the precondition be?
One possibility is [Y = 1], because if [Y] is already [1] then
assigning it to [X] causes [X] to be [1]. That leads to a valid
Hoare triple:
{{ Y = 1 }} X := Y {{ X = 1 }}
It may seem as though coming up with that precondition must have
taken some clever thought. But there is a mechanical way we could
have done it: if we take the postcondition [X = 1] and in it
replace [X] with [Y]---that is, replace the left-hand side of the
assignment statement with the right-hand side---we get the
precondition, [Y = 1]. *)
(** That same technique works in more complicated cases. For
example,
{{ ??? }} X := X + Y {{ X = 1 }}
If we replace the [X] in [X = 1] with [X + Y], we get [X + Y = 1].
That again leads to a valid Hoare triple:
{{ X + Y = 1 }} X := X + Y {{ X = 1 }}
Why does this technique work? The postcondition identifies some
property [P] that we want to hold of the variable [X] being
assigned. In this case, [P] is "equals [1]". To complete the
triple and make it valid, we need to identify a precondition that
guarantees that property will hold of [X]. Such a precondition
must ensure that the same property holds of _whatever is being
assigned to_ [X]. So, in the example, we need "equals [1]" to
hold of [X + Y]. That's exactly what the technique guarantees.
*)
(** In general, the postcondition could be some arbitrary assertion
[Q], and the right-hand side of the assignment could be some
arithmetic expression [a]:
{{ ??? }} X := a {{ Q }}
The precondition would then be [Q], but with any occurrences of
[X] in it replaced by [a]. Let's introduce a notation for this
idea of replacing occurrences: Define [Q [X |-> a]] to mean "[Q]
where [a] is substituted in place of [X]".
That yields the Hoare logic rule for assignment:
{{ Q [X |-> a] }} X := a {{ Q }}
One way of reading that rule is: If you want statement [X := a]
to terminate in a state that satisfies assertion [Q], then it
suffices to start in a state that also satisfies [Q], except
where [a] is substituted for every occurrence of [X].
To many people, this rule seems "backwards" at first, because
it proceeds from the postcondition to the precondition. Actually
it makes good sense to go in this direction: the postcondition is
often what is more important, because it characterizes what we
can assume afer running the code.
Nonetheless, it's also possible to formulate a "forward" assignment
rule. We'll do that later in some exercises. *)
(** Here are some valid instances of the assignment rule:
{{ (X <= 5) [X |-> X + 1] }} (that is, X + 1 <= 5)
X := X + 1
{{ X <= 5 }}
{{ (X = 3) [X |-> 3] }} (that is, 3 = 3)
X := 3
{{ X = 3 }}
{{ (0 <= X /\ X <= 5) [X |-> 3] (that is, 0 <= 3 /\ 3 <= 5)
X := 3
{{ 0 <= X /\ X <= 5 }}
*)
(** To formalize the rule, we must first formalize the idea of
"substituting an expression for an Imp variable in an assertion",
which we refer to as assertion substitution, or [assn_sub]. That
is, given a proposition [P], a variable [X], and an arithmetic
expression [a], we want to derive another proposition [P'] that is
just the same as [P] except that [P'] should mention [a] wherever
[P] mentions [X]. *)
(** Since [P] is an arbitrary Coq assertion, we can't directly "edit"
its text. However, we can achieve the same effect by evaluating
[P] in an updated state: *)
Definition assn_sub X a (P:Assertion) : Assertion :=
fun (st : state) =>
P (X !-> aeval st a ; st).
Notation "P [ X |-> a ]" := (assn_sub X a P)
(at level 10, X at next level, a custom com).
(** That is, [P [X |-> a]] stands for an assertion -- let's call it [P'] --
that is just like [P] except that, wherever [P] looks up the
variable [X] in the current state, [P'] instead uses the value
of the expression [a]. *)
(** To see how this works, let's calculate what happens with a couple
of examples. First, suppose [P'] is [(X <= 5) [X |-> 3]] -- that
is, more formally, [P'] is the Coq expression
fun st =>
(fun st' => st' X <= 5)
(X !-> aeval st 3 ; st),
which simplifies to
fun st =>
(fun st' => st' X <= 5)
(X !-> 3 ; st)
and further simplifies to
fun st =>
((X !-> 3 ; st) X) <= 5
and finally to
fun st =>
3 <= 5.
That is, [P'] is the assertion that [3] is less than or equal to
[5] (as expected). *)
(** For a more interesting example, suppose [P'] is [(X <= 5) [X |->
X + 1]]. Formally, [P'] is the Coq expression
fun st =>
(fun st' => st' X <= 5)
(X !-> aeval st (X + 1) ; st),
which simplifies to
fun st =>
(X !-> aeval st (X + 1) ; st) X <= 5
and further simplifies to
fun st =>
(aeval st (X + 1)) <= 5.
That is, [P'] is the assertion that [X + 1] is at most [5].
*)
(** Now, using the concept of substitution, we can give the precise
proof rule for assignment:
------------------------------ (hoare_asgn)
{{Q [X |-> a]}} X := a {{Q}}
*)
(** We can prove formally that this rule is indeed valid. *)
Theorem hoare_asgn : forall Q X a,
{{Q [X |-> a]}} X := a {{Q}}.
Proof.
unfold hoare_triple.
intros Q X a st st' HE HQ.
inversion HE. subst.
unfold assn_sub in HQ. assumption. Qed.
(** Here's a first formal proof using this rule. *)
Example assn_sub_example :
{{(X < 5) [X |-> X + 1]}}
X := X + 1
{{X < 5}}.
Proof.
(* WORKED IN CLASS *)
apply hoare_asgn. Qed.
(** (Of course, what would be even more helpful is to prove this
simpler triple:
{{X < 4}} X := X + 1 {{X < 5}}
We will see how to do so in the next section. *)
(** **** Exercise: 2 stars, standard, optional (hoare_asgn_examples)
Complete these Hoare triples...
1) {{ ??? }}
X ::= 2 * X
{{ X <= 10 }}
2) {{ ??? }}
X := 3
{{ 0 <= X /\ X <= 5 }}
...using the names [assn_sub_ex1] and [assn_sub_ex2], and prove
both with just [apply hoare_asgn]. If you find that tactic doesn't
suffice, double check that you have completed the triple properly. *)
Example hoare_asgn_example_1 :
{{ (X <= 10) [X |-> 2 * X] }} X := 2 * X {{ X <= 10 }}.
Proof. apply hoare_asgn. Qed.
Example hoare_asgn_example_2 :
{{ (0 <= X /\ X <= 5) [X |-> 3] }}
X := 3
{{ 0 <= X /\ X <= 5 }}.
Proof. apply hoare_asgn. Qed.
(* Do not modify the following line: *)
Definition manual_grade_for_hoare_asgn_examples : option (nat*string) := None.
(** [] *)
(** **** Exercise: 2 stars, standard, especially useful (hoare_asgn_wrong)
The assignment rule looks backward to almost everyone the first
time they see it. If it still seems puzzling, it may help
to think a little about alternative "forward" rules. Here is a
seemingly natural one:
------------------------------ (hoare_asgn_wrong)
{{ True }} X := a {{ X = a }}
Give a counterexample showing that this rule is incorrect and
argue informally that it is really a counterexample. (Hint:
The rule universally quantifies over the arithmetic expression
[a], and your counterexample needs to exhibit an [a] for which
the rule doesn't work.) *)
Ltac pose_st name :=
remember (empty_st : state) as name eqn:H_st; clear H_st.
Example hoare_asgn_wrong :
~ ({{ True }} X := X + 1 {{ X = X + 1 }}).
Proof.
intros.
intro.
pose_st st.
assert ((X !-> 0; st) =[ X := X + 1 ]=> (X !-> 1; st)).
{ replace (X !-> 1; st) with (X !-> 1; X !-> 0; st) by
apply t_update_shadow.
constructor. easy.
}
assert (T: True) by auto.
apply H in H0. apply H0 in T. simpl in T.
rewrite t_update_eq in T. inversion T.
Qed.
(* Do not modify the following line: *)
Definition manual_grade_for_hoare_asgn_wrong : option (nat*string) := None.
(** [] *)
(** **** Exercise: 3 stars, advanced (hoare_asgn_fwd)
However, by using a _parameter_ [m] (a Coq number) to remember the
original value of [X] we can define a Hoare rule for assignment
that does, intuitively, "work forwards" rather than backwards.
------------------------------------------ (hoare_asgn_fwd)
{{fun st => P st /\ st X = m}}
X := a
{{fun st => P st' /\ st X = aeval st' a }}
(where st' = (X !-> m ; st))
Note that we use the original value of [X] to reconstruct the
state [st'] before the assignment took place. Prove that this rule
is correct. (Also note that this rule is more complicated than
[hoare_asgn].)
*)
Theorem hoare_asgn_fwd :
forall m a P,
{{fun st => P st /\ st X = m}}
X := a
{{fun st => P (X !-> m ; st)
/\ st X = aeval (X !-> m ; st) a }}.
Proof.
intro_all.
inversion H; subst.
destruct H0.
rewrite t_update_shadow.
split.
- (* P (X !-> m; st) *)
subst. rewrite t_update_same. apply H0.
- (* X !-> aeval st a; st) X = aeval (X !-> m; st) a *)
subst. rewrite t_update_same. rewrite t_update_eq. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars, advanced, optional (hoare_asgn_fwd_exists)
Another way to define a forward rule for assignment is to
existentially quantify over the previous value of the assigned
variable. Prove that it is correct.
------------------------------------ (hoare_asgn_fwd_exists)
{{fun st => P st}}
X := a
{{fun st => exists m, P (X !-> m ; st) /\
st X = aeval (X !-> m ; st) a }}
*)
Theorem hoare_asgn_fwd_exists :
forall a P,
{{fun st => P st}}
X := a
{{fun st => exists m, P (X !-> m ; st) /\
st X = aeval (X !-> m ; st) a }}.
Proof.
intro_all.
inversion H; subst.
exists (st X).
split.
- rewrite t_update_shadow. rewrite t_update_same. apply H0.
- rewrite t_update_shadow. rewrite t_update_same. rewrite t_update_eq.
reflexivity.
Qed.
(** [] *)
(* ================================================================= *)
(** ** Consequence *)
(** Sometimes the preconditions and postconditions we get from the
Hoare rules won't quite be the ones we want in the particular
situation at hand -- they may be logically equivalent but have a
different syntactic form that fails to unify with the goal we are
trying to prove, or they actually may be logically weaker (for
preconditions) or stronger (for postconditions) than what we need. *)
(** For instance, while
{{(X = 3) [X |-> 3]}} X := 3 {{X = 3}},
follows directly from the assignment rule,
{{True}} X := 3 {{X = 3}}
does not. This triple is valid, but it is not an instance of
[hoare_asgn] because [True] and [(X = 3) [X |-> 3]] are not
syntactically equal assertions. However, they are logically
_equivalent_, so if one triple is valid, then the other must
certainly be as well. We can capture this observation with the
following rule:
{{P'}} c {{Q}}
P <<->> P'
----------------------------- (hoare_consequence_pre_equiv)
{{P}} c {{Q}}
*)
(** Taking this line of thought a bit further, we can see that
strengthening the precondition or weakening the postcondition of a
valid triple always produces another valid triple. This
observation is captured by two _Rules of Consequence_.
{{P'}} c {{Q}}
P ->> P'
----------------------------- (hoare_consequence_pre)
{{P}} c {{Q}}
{{P}} c {{Q'}}
Q' ->> Q
----------------------------- (hoare_consequence_post)
{{P}} c {{Q}}
*)
(** Here are the formal versions: *)
Theorem hoare_consequence_pre : forall (P P' Q : Assertion) c,
{{P'}} c {{Q}} ->
P ->> P' ->
{{P}} c {{Q}}.
Proof.
unfold hoare_triple, "->>".
intros P P' Q c Hhoare Himp st st' Heval Hpre.
apply Hhoare with (st := st).
- assumption.
- apply Himp. assumption.
Qed.
Theorem hoare_consequence_post : forall (P Q Q' : Assertion) c,
{{P}} c {{Q'}} ->
Q' ->> Q ->
{{P}} c {{Q}}.
Proof.
unfold hoare_triple, "->>".
intros P Q Q' c Hhoare Himp st st' Heval Hpre.
apply Himp.
apply Hhoare with (st := st).
- assumption.
- assumption.
Qed.
(** For example, we can use the first consequence rule like this:
{{ True }} ->>
{{ (X = 1) [X |-> 1] }}
X := 1
{{ X = 1 }}
Or, formally... *)
Example hoare_asgn_example1 :
{{True}} X := 1 {{X = 1}}.
Proof.
(* WORKED IN CLASS *)
apply hoare_consequence_pre with (P' := (X = 1) [X |-> 1]).
- apply hoare_asgn.
- unfold "->>", assn_sub, t_update.
intros st _. simpl. reflexivity.
Qed.
(** We can also use it to prove the example mentioned earlier.
{{ X < 4 }} ->>
{{ (X < 5)[X |-> X + 1] }}
X := X + 1
{{ X < 5 }}
Or, formally ... *)
Example assn_sub_example2 :
{{X < 4}}
X := X + 1
{{X < 5}}.
Proof.
(* WORKED IN CLASS *)
apply hoare_consequence_pre with (P' := (X < 5) [X |-> X + 1]).
- apply hoare_asgn.
- unfold "->>", assn_sub, t_update.
intros st H. simpl in *. lia.
Qed.
(** Finally, here is a combined rule of consequence that allows us to
vary both the precondition and the postcondition.
{{P'}} c {{Q'}}
P ->> P'
Q' ->> Q
----------------------------- (hoare_consequence)
{{P}} c {{Q}}
*)
Theorem hoare_consequence : forall (P P' Q Q' : Assertion) c,
{{P'}} c {{Q'}} ->
P ->> P' ->
Q' ->> Q ->
{{P}} c {{Q}}.
Proof.
intros P P' Q Q' c Htriple Hpre Hpost.
apply hoare_consequence_pre with (P' := P').
- apply hoare_consequence_post with (Q' := Q').
+ assumption.
+ assumption.
- assumption.
Qed.
(* ================================================================= *)
(** ** Automation *)
(** Many of the proofs we have done so far with Hoare triples can be
streamlined using the automation techniques that we introduced in
the [Auto] chapter of _Logical Foundations_.
Recall that the [auto] tactic can be told to [unfold] definitions
as part of its proof search. Let's give that hint for the
definitions and coercions we're using: *)
Hint Unfold assert_implies hoare_triple assn_sub t_update : core.
Hint Unfold assert_of_Prop Aexp_of_nat Aexp_of_aexp : core.
(** Also recall that [auto] will search for a proof involving [intros]
and [apply]. By default, the theorems that it will apply include
any of the local hypotheses, as well as theorems in a core
database. *)
(** The proof of [hoare_consequence_pre], repeated below, looks
like an opportune place for such automation, because all it does
is [unfold], [intros], and [apply]. It uses [assumption], too,
but that's just application of a hypothesis. *)
Theorem hoare_consequence_pre' : forall (P P' Q : Assertion) c,
{{P'}} c {{Q}} ->
P ->> P' ->
{{P}} c {{Q}}.
Proof.
unfold hoare_triple, "->>".
intros P P' Q c Hhoare Himp st st' Heval Hpre.
apply Hhoare with (st := st).
- assumption.
- apply Himp. assumption.
Qed.
(** Merely using [auto], though, doesn't complete the proof. *)
Theorem hoare_consequence_pre'' : forall (P P' Q : Assertion) c,
{{P'}} c {{Q}} ->
P ->> P' ->
{{P}} c {{Q}}.
Proof.
auto. (* no progress *)
Abort.
(** The problem is the [apply Hhoare with...] part of the proof. Coq
isn't able to figure out how to instantiate [st] without some help
from us. Recall, though, that there are versions of many tactics
that will use _existential variables_ to make progress even when
the regular versions of those tactics would get stuck.
Here, the [eapply] tactic will introduce an existential variable
[?st] as a placeholder for [st], and [eassumption] will
instantiate [?st] with [st] when it discovers [st] in assumption
[Heval]. By using [eapply] we are essentially telling Coq, "Be
patient: The missing part is going to be filled in later in the
proof." *)
Theorem hoare_consequence_pre''' : forall (P P' Q : Assertion) c,
{{P'}} c {{Q}} ->
P ->> P' ->
{{P}} c {{Q}}.
Proof.
unfold hoare_triple, "->>".
intros P P' Q c Hhoare Himp st st' Heval Hpre.
eapply Hhoare.
- eassumption.
- apply Himp. assumption.
Qed.
(** Tactic [eauto] will use [eapply] as part of its proof search.
So, the entire proof can be done in just one line. *)
Theorem hoare_consequence_pre'''' : forall (P P' Q : Assertion) c,
{{P'}} c {{Q}} ->
P ->> P' ->
{{P}} c {{Q}}.
Proof.
eauto.
Qed.
(** Of course, it's hard to predict that [eauto] suffices here
without having gone through the original proof of
[hoare_consequence_pre] to see the tactics it used. But now that
we know [eauto] works, it's a good bet that it will also work for
[hoare_consequence_post]. *)
Theorem hoare_consequence_post' : forall (P Q Q' : Assertion) c,
{{P}} c {{Q'}} ->
Q' ->> Q ->
{{P}} c {{Q}}.
Proof.
eauto.
Qed.
(** We can also use [eapply] to streamline a proof,
[hoare_asgn_example1], that we did earlier as an example of using
the consequence rule: *)
Example hoare_asgn_example1' :
{{True}} X := 1 {{X = 1}}.
Proof.
eapply hoare_consequence_pre. (* no need to state an assertion *)
- apply hoare_asgn.
- unfold "->>", assn_sub, t_update.
intros st _. simpl. reflexivity.
Qed.
(** The final bullet of that proof also looks like a candidate for
automation. *)
Example hoare_asgn_example1'' :
{{True}} X := 1 {{X = 1}}.
Proof.
eapply hoare_consequence_pre.
- apply hoare_asgn.
- auto.
Qed.
(** Now we have quite a nice proof script: it simply identifies the
Hoare rules that need to be used and leaves the remaining
low-level details up to Coq to figure out. *)
(** By now it might be apparent that the _entire_ proof could be
automated if we added [hoare_consequence_pre] and [hoare_asgn] to
the hint database. We won't do that in this chapter, so that we
can get a better understanding of when and how the Hoare rules are
used. In the next chapter, [Hoare2], we'll dive deeper into
automating entire proofs of Hoare triples. *)
(** The other example of using consequence that we did earlier,
[hoare_asgn_example2], requires a little more work to automate.
We can streamline the first line with [eapply], but we can't just use
[auto] for the final bullet, since it needs [omega]. *)
Example assn_sub_example2' :
{{X < 4}}
X := X + 1
{{X < 5}}.
Proof.
eapply hoare_consequence_pre.
- apply hoare_asgn.
- auto. (* no progress *)
unfold "->>", assn_sub, t_update.
intros st H. simpl in *. lia.
Qed.
(** Let's introduce our own tactic to handle both that bullet and the
bullet from example 1: *)
Ltac assn_auto :=
try auto; (* as in example 1, above *)
try (unfold "->>", assn_sub, t_update;
intros; simpl in *; lia). (* as in example 2 *)
Example assn_sub_example2'' :
{{X < 4}}
X := X + 1
{{X < 5}}.
Proof.
eapply hoare_consequence_pre.
- apply hoare_asgn.
- assn_auto.
Qed.
Example hoare_asgn_example1''':
{{True}} X := 1 {{X = 1}}.
Proof.
eapply hoare_consequence_pre.
- apply hoare_asgn.
- assn_auto.
Qed.
(** Again, we have quite a nice proof script. All the low-level
details of proof about assertions have been taken care of
automatically. Of course, [assn_auto] isn't able to prove
everything we could possibly want to know about assertions --
there's no magic here! But it's good enough so far. *)
(** **** Exercise: 2 stars, standard (hoare_asgn_examples_2)
Prove these triples. Try to make your proof scripts as nicely automated
as those above. *)
Example assn_sub_ex1' :
{{ X <= 5 }}
X := 2 * X
{{ X <= 10 }}.
Proof.
eapply hoare_consequence_pre.
- apply hoare_asgn.
- assn_auto.
Qed.
Example assn_sub_ex2' :
{{ 0 <= 3 /\ 3 <= 5 }}
X := 3
{{ 0 <= X /\ X <= 5 }}.
Proof.
eapply hoare_consequence_pre.
- apply hoare_asgn.
- assn_auto.
Qed.
(** [] *)
(* ================================================================= *)
(** ** Skip *)
(** Since [skip] doesn't change the state, it preserves any
assertion [P]:
-------------------- (hoare_skip)
{{ P }} skip {{ P }}
*)
Theorem hoare_skip : forall P,
{{P}} skip {{P}}.
Proof.
intros P st st' H HP. inversion H; subst. assumption.
Qed.
(* ================================================================= *)
(** ** Sequencing *)
(** If command [c1] takes any state where [P] holds to a state where
[Q] holds, and if [c2] takes any state where [Q] holds to one
where [R] holds, then doing [c1] followed by [c2] will take any
state where [P] holds to one where [R] holds:
{{ P }} c1 {{ Q }}
{{ Q }} c2 {{ R }}
---------------------- (hoare_seq)
{{ P }} c1;c2 {{ R }}
*)
Theorem hoare_seq : forall P Q R c1 c2,
{{Q}} c2 {{R}} ->
{{P}} c1 {{Q}} ->
{{P}} c1; c2 {{R}}.
Proof.
unfold hoare_triple.
intros P Q R c1 c2 H1 H2 st st' H12 Pre.
inversion H12; subst.
eauto.
Qed.
(** Note that, in the formal rule [hoare_seq], the premises are
given in backwards order ([c2] before [c1]). This matches the
natural flow of information in many of the situations where we'll
use the rule, since the natural way to construct a Hoare-logic
proof is to begin at the end of the program (with the final
postcondition) and push postconditions backwards through commands
until we reach the beginning. *)
(** Here's an example of a program involving sequencing. Note the use
of [hoare_seq] in conjunction with [hoare_consequence_pre] and the
[eapply] tactic. *)
Example hoare_asgn_example3 : forall (a:aexp) (n:nat),
{{a = n}}
X := a; skip
{{X = n}}.
Proof.
intros a n. eapply hoare_seq.
- (* right part of seq *)
apply hoare_skip.
- (* left part of seq *)
eapply hoare_consequence_pre.
+ apply hoare_asgn.
+ assn_auto.
Qed.
(** Informally, a nice way of displaying a proof using the sequencing
rule is as a "decorated program" where the intermediate assertion
[Q] is written between [c1] and [c2]:
{{ a = n }}
X := a;
{{ X = n }} <--- decoration for Q
skip
{{ X = n }}
*)
(** **** Exercise: 2 stars, standard, especially useful (hoare_asgn_example4)
Translate this "decorated program" into a formal proof:
{{ True }} ->>
{{ 1 = 1 }}
X := 1;
{{ X = 1 }} ->>
{{ X = 1 /\ 2 = 2 }}
Y := 2
{{ X = 1 /\ Y = 2 }}
Note the use of "[->>]" decorations, each marking a use of
[hoare_consequence_pre].
We've started you off by providing a use of [hoare_seq] that
explicitly identifies [X = 1] as the intermediate assertion. *)
Example hoare_asgn_example4 :
{{ True }}
X := 1; Y := 2
{{ X = 1 /\ Y = 2 }}.
Proof.
apply hoare_seq with (Q := (X = 1)%assertion).
- intro_all.
eapply hoare_asgn.
+ apply H.
+ inversion H; subst. assn_auto.
- intro_all.
eapply hoare_asgn.
+ apply H.
+ inversion H; subst. assn_auto.
Qed.
(** [] *)
(** **** Exercise: 3 stars, standard (swap_exercise)
Write an Imp program [c] that swaps the values of [X] and [Y] and
show that it satisfies the following specification:
{{X <= Y}} c {{Y <= X}}
Your proof should not need to use [unfold hoare_triple]. (Hint:
Remember that the assignment rule works best when it's applied
"back to front," from the postcondition to the precondition. So
your proof will want to start at the end and work back to the
beginning of your program.) *)
Definition swap_program : com :=
<{
Z := X;
X := Y;
Y := Z
}>.
Theorem swap_exercise :
{{X <= Y}}
swap_program
{{Y <= X}}.
Proof.
pose_st st.
eapply hoare_seq.
- eapply hoare_seq.
+ apply hoare_asgn.
+ apply hoare_asgn.
- simpl.
eapply hoare_consequence_pre.
apply hoare_asgn.
auto.
Qed.
(** [] *)
(** **** Exercise: 4 stars, standard (invalid_triple)
Show that
{{ a = n }}
X := 3;; Y := a
{{ Y = n }}
is not a valid Hoare triple for some choices of [a] and [n].
Conceptual hint: invent a particular [a] and [n] for which the triple
in invalid, then use those to complete the proof.
Technical hint: hypothesis [H], below, begins [forall a n, ...].
You'll want to instantiate that for the particular [a] and [n]
you've invented. You can do that with [assert] and [apply], but
Coq offers an even easier tactic: [specialize]. If you write
specialize H with (a := your_a) (n := your_n)
the hypothesis will be instantiated on [your_a] and [your_n].
*)
Theorem invalid_triple : ~ forall (a : aexp) (n : nat),
{{ a = n }}
X := 3; Y := a
{{ Y = n }}.
Proof.
unfold hoare_triple.
intro.
(* take a := X and n := 0 *)
specialize H with (a := X) (n := 0).
pose_st st.
remember ((X !-> 0; st) : state) as st1.
remember ((Y !-> 3; X !-> 3; st) : state) as st2.
specialize H with (st := st1) (st' := st2).
subst.
simpl in H. repeat rewrite t_update_eq in H.
assert (~ (X !-> 0; st) =[ X := 3; Y := X ]=> (Y !-> 3; X !-> 3; st)).
{ intro. apply H in H0. inversion H0. auto.
}
(* now we prove (X !-> 0; st) =[ X := 3; Y := X ]=> (Y !-> 3; X !-> 3; st) *)
apply H0.
econstructor.
econstructor.
auto.
simpl.
rewrite t_update_shadow.
econstructor.
auto.
Qed.
(** [] *)
(* ================================================================= *)
(** ** Conditionals *)
(** What sort of rule do we want for reasoning about conditional
commands?
Certainly, if the same assertion [Q] holds after executing
either of the branches, then it holds after the whole conditional.
So we might be tempted to write:
{{P}} c1 {{Q}}
{{P}} c2 {{Q}}
---------------------------------
{{P}} if b then c1 else c2 {{Q}}
*)
(** However, this is rather weak. For example, using this rule,
we cannot show
{{ True }}
if X = 0
then Y := 2
else Y := X + 1
end
{{ X <= Y }}
since the rule tells us nothing about the state in which the
assignments take place in the "then" and "else" branches. *)
(** Fortunately, we can say something more precise. In the
"then" branch, we know that the boolean expression [b] evaluates to
[true], and in the "else" branch, we know it evaluates to [false].
Making this information available in the premises of the rule gives
us more information to work with when reasoning about the behavior
of [c1] and [c2] (i.e., the reasons why they establish the
postcondition [Q]).
{{P /\ b}} c1 {{Q}}
{{P /\ ~ b}} c2 {{Q}}
------------------------------------ (hoare_if)
{{P}} if b then c1 else c2 end {{Q}}
*)
(** To interpret this rule formally, we need to do a little work.
Strictly speaking, the assertion we've written, [P /\ b], is the
conjunction of an assertion and a boolean expression -- i.e., it
doesn't typecheck. To fix this, we need a way of formally
"lifting" any bexp [b] to an assertion. We'll write [bassn b] for
the assertion "the boolean expression [b] evaluates to [true] (in
the given state)." *)
Definition bassn b : Assertion :=
fun st => (beval st b = true).
Coercion bassn : bexp >-> Assertion.
Arguments bassn /.
Hint Unfold bassn : core.
(** A couple of useful facts about [bassn]: *)
Lemma bexp_eval_true : forall b st,
beval st b = true -> (bassn b) st.
Proof. auto. Qed.
Lemma bexp_eval_false : forall b st,
beval st b = false -> ~ ((bassn b) st).
Proof. congruence. Qed.
Hint Resolve bexp_eval_false : core.
(** We mentioned the [congruence] tactic in passing in [Auto] when
building the [find_rwd] tactic. Like [find_rwd], [congruence] is able to
automatically find that both [beval st b = false] and [beval st b = true]
are being assumed, notice the contradiction, and [discriminate] to complete
the proof. *)
(** Now we can formalize the Hoare proof rule for conditionals
and prove it correct. *)
Theorem hoare_if : forall P Q (b:bexp) c1 c2,
{{ P /\ b }} c1 {{Q}} ->
{{ P /\ ~ b}} c2 {{Q}} ->
{{P}} if b then c1 else c2 end {{Q}}.
(** That is (unwrapping the notations):
Theorem hoare_if : forall P Q b c1 c2,
{{fun st => P st /\ bassn b st}} c1 {{Q}} ->
{{fun st => P st /\ ~ (bassn b st)}} c2 {{Q}} ->
{{P}} if b then c1 else c2 end {{Q}}.
*)
Proof.
intros P Q b c1 c2 HTrue HFalse st st' HE HP.
inversion HE; subst; eauto.
Qed.
(* ----------------------------------------------------------------- *)
(** *** Example *)
(** Here is a formal proof that the program we used to motivate the
rule satisfies the specification we gave. *)
Example if_example :
{{True}}
if (X = 0)
then Y := 2
else Y := X + 1
end
{{X <= Y}}.
Proof.
apply hoare_if.
- (* Then *)
eapply hoare_consequence_pre.
+ apply hoare_asgn.
+ assn_auto. (* no progress *)
unfold "->>", assn_sub, t_update, bassn.
simpl. intros st [_ H].
apply eqb_eq in H.
rewrite H. lia.
- (* Else *)
eapply hoare_consequence_pre.
+ apply hoare_asgn.
+ assn_auto.
Qed.
(** As we did earlier, it would be nice to eliminate all the low-level
proof script that isn't about the Hoare rules. Unfortunately, the
[assn_auto] tactic we wrote wasn't quite up to the job. Looking
at the proof of [if_example], we can see why. We had to unfold a
definition ([bassn]) and use a theorem ([eqb_eq]) that we didn't
need in earlier proofs. So, let's add those into our tactic,
and clean it up a little in the process. *)
Ltac assn_auto' :=
unfold "->>", assn_sub, t_update, bassn;
intros; simpl in *;
try rewrite -> eqb_eq in *; (* for equalities *)
auto; try lia.
(** Now the proof is quite streamlined. *)
Example if_example'' :
{{True}}
if X = 0
then Y := 2
else Y := X + 1
end
{{X <= Y}}.
Proof.
apply hoare_if.
- eapply hoare_consequence_pre.
+ apply hoare_asgn.
+ assn_auto'.
- eapply hoare_consequence_pre.
+ apply hoare_asgn.
+ assn_auto'.
Qed.
(** We can even shorten it a little bit more. *)
Example if_example''' :
{{True}}
if X = 0
then Y := 2
else Y := X + 1
end
{{X <= Y}}.
Proof.
apply hoare_if; eapply hoare_consequence_pre;
try apply hoare_asgn; try assn_auto'.
Qed.
(** For later proofs, it will help to extend [assn_auto'] to handle
inequalities, too. *)
Ltac assn_auto'' :=
unfold "->>", assn_sub, t_update, bassn;
intros; simpl in *;
try rewrite -> eqb_eq in *;
try rewrite -> leb_le in *; (* for inequalities *)
auto; try lia.
(** **** Exercise: 2 stars, standard (if_minus_plus)
Prove the theorem below using [hoare_if]. Do not use [unfold
hoare_triple]. *)
Theorem if_minus_plus :
{{True}}
if (X <= Y)
then Z := Y - X
else Y := X + Z
end
{{Y = X + Z}}.
Proof.
apply hoare_if.
- eapply hoare_consequence_pre.
+ apply hoare_asgn.
+ assn_auto''.
- eapply hoare_consequence_pre.
+ apply hoare_asgn.
+ assn_auto''.
Qed.
(** [] *)
(* ----------------------------------------------------------------- *)
(** *** Exercise: One-sided conditionals *)
(** In this exercise we consider extending Imp with "one-sided
conditionals" of the form [if1 b then c end]. Here [b] is a boolean
expression, and [c] is a command. If [b] evaluates to [true], then
command [c] is evaluated. If [b] evaluates to [false], then [if1 b
then c end] does nothing.
We recommend that you complete this exercise before attempting the
ones that follow, as it should help solidify your understanding of
the material. *)
(** The first step is to extend the syntax of commands and introduce
the usual notations. (We've done this for you. We use a separate
module to prevent polluting the global name space.) *)
Module If1.
Inductive com : Type :=
| CSkip : com
| CAss : string -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CIf1 : bexp -> com -> com.
Notation "'if1' x 'then' y 'end'" :=
(CIf1 x y)
(in custom com at level 0, x custom com at level 99).
Notation "'skip'" :=
CSkip (in custom com at level 0).
Notation "x := y" :=
(CAss x y)
(in custom com at level 0, x constr at level 0,
y at level 85, no associativity).
Notation "x ; y" :=
(CSeq x y)
(in custom com at level 90, right associativity).
Notation "'if' x 'then' y 'else' z 'end'" :=
(CIf x y z)
(in custom com at level 89, x at level 99,
y at level 99, z at level 99).
Notation "'while' x 'do' y 'end'" :=
(CWhile x y)
(in custom com at level 89, x at level 99, y at level 99).
(** **** Exercise: 2 stars, standard (if1_ceval) *)
(** Add two new evaluation rules to relation [ceval], below, for
[if1]. Let the rules for [if] guide you.*)
Reserved Notation "st '=[' c ']=>'' st'"
(at level 40, c custom com at level 99,
st constr, st' constr at next level).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st,
st =[ skip ]=> st
| E_Ass : forall st a1 n x,
aeval st a1 = n ->
st =[ x := a1 ]=> (x !-> n ; st)
| E_Seq : forall c1 c2 st st' st'',
st =[ c1 ]=> st' ->
st' =[ c2 ]=> st'' ->
st =[ c1 ; c2 ]=> st''
| E_IfTrue : forall st st' b c1 c2,
beval st b = true ->
st =[ c1 ]=> st' ->
st =[ if b then c1 else c2 end ]=> st'
| E_IfFalse : forall st st' b c1 c2,
beval st b = false ->
st =[ c2 ]=> st' ->
st =[ if b then c1 else c2 end ]=> st'
| E_WhileFalse : forall b st c,
beval st b = false ->
st =[ while b do c end ]=> st
| E_WhileTrue : forall st st' st'' b c,
beval st b = true ->
st =[ c ]=> st' ->
st' =[ while b do c end ]=> st'' ->
st =[ while b do c end ]=> st''
(* Cheating version: *)
(* | E_If1 : forall st st' b c, *)
(* st =[ if b then c else skip end ]=> st' -> *)
(* st =[ if1 b then c end ]=> st' *)
(* No I will come up with a genuine one *)
| E_If1True : forall st st' b c,
beval st b = true ->
st =[ c ]=> st' ->
st =[ if1 b then c end ]=> st'
| E_If1False : forall st b c,
beval st b = false ->
st =[ if1 b then c end ]=> st
where "st '=[' c ']=>' st'" := (ceval c st st').
Hint Constructors ceval : core.
(** The following unit tests should be provable simply by [eauto] if
you have defined the rules for [if1] correctly. *)
Example if1true_test :
empty_st =[ if1 X = 0 then X := 1 end ]=> (X !-> 1).
Proof. auto. Qed.
Example if1false_test :
(X !-> 2) =[ if1 X = 0 then X := 1 end ]=> (X !-> 2).
Proof. auto. Qed.
(** [] *)
(** Now we have to repeat the definition and notation of Hoare triples,
so that they will use the updated [com] type. *)
Definition hoare_triple
(P : Assertion) (c : com) (Q : Assertion) : Prop :=
forall st st',
st =[ c ]=> st' ->
P st ->
Q st'.
Hint Unfold hoare_triple : core.
Notation "{{ P }} c {{ Q }}" := (hoare_triple P c Q)
(at level 90, c custom com at level 99)
: hoare_spec_scope.
(** **** Exercise: 2 stars, standard (hoare_if1) *)
(** Invent a Hoare logic proof rule for [if1]. State and prove a
theorem named [hoare_if1] that shows the validity of your rule.
Use [hoare_if] as a guide. Try to invent a rule that is
_complete_, meaning it can be used to prove the correctness of as
many one-sided conditionals as possible. Also try to keep your
rule _compositional_, meaning that any Imp command that appears
in a premise should syntactically be a part of the command
in the conclusion.
Hint: if you encounter difficulty getting Coq to parse part of
your rule as an assertion, try manually indicating that it should
be in the assertion scope. For example, if you want [e] to be
parsed as an assertion, write it as [(e)%assertion]. *)
Theorem hoare_if1 : forall (b:bexp) c P Q,
{{ P /\ b }} c {{ Q }} ->
(( P /\ ~b )%assertion ->> Q) ->
{{ P }} if1 b then c end {{ Q }}.
Proof.
intros.
intro_all.
inversion H1; subst; eauto.
Qed.
(** For full credit, prove formally [hoare_if1_good] that your rule is
precise enough to show the following valid Hoare triple:
{{ X + Y = Z }}
if1 ~(Y = 0) then
X := X + Y
end
{{ X = Z }}
*)
(* Do not modify the following line: *)
Definition manual_grade_for_hoare_if1 : option (nat*string) := None.
(** [] *)
(** Before the next exercise, we need to restate the Hoare rules of
consequence (for preconditions) and assignment for the new [com]
type. *)
Theorem hoare_consequence_pre : forall (P P' Q : Assertion) c,
{{P'}} c {{Q}} ->
P ->> P' ->
{{P}} c {{Q}}.
Proof.
eauto.
Qed.
Theorem hoare_asgn : forall Q X a,
{{Q [X |-> a]}} (X := a) {{Q}}.
Proof.
intros Q X a st st' Heval HQ.
inversion Heval; subst.
auto.
Qed.
(** **** Exercise: 2 stars, standard (hoare_if1_good) *)
(** Prove that your [if1] rule is complete enough for the following
valid Hoare triple.
Hint: [assn_auto''] once more will get you most but not all the way
to a completely automated proof. You can finish manually, or
tweak the tactic further. *)
Lemma hoare_if1_good :
{{ X + Y = Z }}
if1 ~(Y = 0) then
X := X + Y
end
{{ X = Z }}.
Proof.
apply hoare_if1.
- (* if1 true case *)
eapply hoare_consequence_pre.
+ apply hoare_asgn.
+ assn_auto.
- (* if1 false case *)
assn_auto''.
destruct H.
rewrite negb_true_iff in H0.
destruct (eqb_spec (st Y) 0).
+ lia.
+ congruence.
Qed.
(** [] *)
End If1.
(* ================================================================= *)
(** ** While Loops *)
(** The Hoare rule for [while] loops is based on the idea of an
_invariant_: an assertion whose truth is guaranteed before and
after executing a command. An assertion [P] is an invariant of [c] if
{{P}} c {{P}}
holds. Note that in the middle of executing [c], the invariant
might temporarily become false, but by the end of [c], it must be
restored. *)
(** As a first attempt at a [while] rule, we could try:
{{P}} c {{P}}
---------------------------
{{P} while b do c end {{P}}
That rule is valid: if [P] is an invariant of [c], as the premise
requires, then no matter how many times the loop body executes,
[P] is going to be true when the loop finally finishes.
But the rule also omits two crucial pieces of information. First,
the loop terminates when [b] becomes false. So we can strengthen
the postcondition in the conclusion:
{{P}} c {{P}}
---------------------------------
{{P} while b do c end {{P /\ ~b}}
Second, the loop body will be executed only if [b] is true. So we
can also strengthen the precondition in the premise:
{{P /\ b}} c {{P}}
--------------------------------- (hoare_while)
{{P} while b do c end {{P /\ ~b}}
*)
(** That is the Hoare [while] rule. Note how it combines
aspects of [skip] and conditionals:
- If the loop body executes zero times, the rule is like [skip] in
that the precondition survives to become (part of) the
postcondition.
- Like a conditional, we can assume guard [b] holds on entry to
the subcommand.
*)
Theorem hoare_while : forall P (b:bexp) c,
{{P /\ b}} c {{P}} ->
{{P}} while b do c end {{P /\ ~ b}}.
Proof.
intros P b c Hhoare st st' Heval HP.
(* We proceed by induction on [Heval], because, in the "keep looping" case,
its hypotheses talk about the whole loop instead of just [c]. The
[remember] is used to keep the original command in the hypotheses;
otherwise, it would be lost in the [induction]. By using [inversion]
we clear away all the cases except those involving [while]. *)
remember <{while b do c end}> as original_command eqn:Horig.
induction Heval;
try (inversion Horig; subst; clear Horig);
eauto.
Qed.
(** We say that [P] is a _loop invariant_ of [while b do c end] if [P]
suffices to prove [hoare_while] for that loop. Being a loop
invariant is different from being an invariant of the body,
because it means being able to prove correctness of the loop. For
example, [X = 0] is a loop invariant of
while X = 2 do X := 1 end
even though [X = 0] is not an invariant of [X := 1]. *)
(** This is a slightly (but crucially) weaker requirement. For
example, if [P] is the assertion [X = 0], then [P] _is_ an
invariant of the loop
while X = 2 do X := 1 end
although it is clearly _not_ preserved by the body of the
loop. *)
Example while_example :
{{X <= 3}}
while (X <= 2) do
X := X + 1
end
{{X = 3}}.
Proof.
eapply hoare_consequence_post.
- apply hoare_while.
eapply hoare_consequence_pre.
+ apply hoare_asgn.
+ assn_auto''.
- assn_auto''.
Qed.
(** If the loop never terminates, any postcondition will work. *)
Theorem always_loop_hoare : forall Q,
{{True}} while true do skip end {{Q}}.
Proof.
intros Q.
eapply hoare_consequence_post.
- apply hoare_while. apply hoare_post_true. auto.
- simpl. intros st [Hinv Hguard]. congruence.
Qed.
(** Of course, this result is not surprising if we remember that
the definition of [hoare_triple] asserts that the postcondition
must hold _only_ when the command terminates. If the command
doesn't terminate, we can prove anything we like about the
post-condition.
Hoare rules that specify what happens _if_ commands terminate,
without proving that they do, are said to describe a logic of
_partial_ correctness. It is also possible to give Hoare rules
for _total_ correctness, which additionally specifies that
commands must terminate. Total correctness is out of the scope of
this textbook. *)
(* ----------------------------------------------------------------- *)
(** *** Exercise: [REPEAT] *)
(** **** Exercise: 4 stars, advanced (hoare_repeat)
In this exercise, we'll add a new command to our language of
commands: [REPEAT] c [until] b [end]. You will write the
evaluation rule for [REPEAT] and add a new Hoare rule to the
language for programs involving it. (You may recall that the
evaluation rule is given in an example in the [Auto] chapter.
Try to figure it out yourself here rather than peeking.) *)
Module RepeatExercise.
Inductive com : Type :=
| CSkip : com
| CAss : string -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CRepeat : com -> bexp -> com.
(** [REPEAT] behaves like [while], except that the loop guard is
checked _after_ each execution of the body, with the loop
repeating as long as the guard stays _false_. Because of this,
the body will always execute at least once. *)
Notation "'repeat' e1 'until' b2 'end'" :=
(CRepeat e1 b2)
(in custom com at level 0,
e1 custom com at level 99, b2 custom com at level 99).
Notation "'skip'" :=
CSkip (in custom com at level 0).
Notation "x := y" :=
(CAss x y)
(in custom com at level 0, x constr at level 0,
y at level 85, no associativity).
Notation "x ; y" :=
(CSeq x y)
(in custom com at level 90, right associativity).
Notation "'if' x 'then' y 'else' z 'end'" :=
(CIf x y z)
(in custom com at level 89, x at level 99,
y at level 99, z at level 99).
Notation "'while' x 'do' y 'end'" :=
(CWhile x y)
(in custom com at level 89, x at level 99, y at level 99).
(** Add new rules for [REPEAT] to [ceval] below. You can use the rules
for [while] as a guide, but remember that the body of a [REPEAT]
should always execute at least once, and that the loop ends when
the guard becomes true. *)
Inductive ceval : state -> com -> state -> Prop :=
| E_Skip : forall st,
st =[ skip ]=> st
| E_Ass : forall st a1 n x,
aeval st a1 = n ->
st =[ x := a1 ]=> (x !-> n ; st)
| E_Seq : forall c1 c2 st st' st'',
st =[ c1 ]=> st' ->
st' =[ c2 ]=> st'' ->
st =[ c1 ; c2 ]=> st''
| E_IfTrue : forall st st' b c1 c2,
beval st b = true ->
st =[ c1 ]=> st' ->
st =[ if b then c1 else c2 end ]=> st'
| E_IfFalse : forall st st' b c1 c2,
beval st b = false ->
st =[ c2 ]=> st' ->
st =[ if b then c1 else c2 end ]=> st'
| E_WhileFalse : forall b st c,
beval st b = false ->
st =[ while b do c end ]=> st
| E_WhileTrue : forall st st' st'' b c,
beval st b = true ->
st =[ c ]=> st' ->
st' =[ while b do c end ]=> st'' ->
st =[ while b do c end ]=> st''
| E_RepeatTrue : forall b st st' c,
st =[ c ]=> st' ->
beval st' b = true ->
st =[ repeat c until b end ]=> st'
| E_RepeatFalse : forall st st' st'' b c,
st =[ c ]=> st' ->
beval st' b = false ->
st' =[ repeat c until b end ]=> st'' ->
st =[ repeat c until b end ]=> st''
where "st '=[' c ']=>' st'" := (ceval st c st').
(** A couple of definitions from above, copied here so they use the
new [ceval]. *)
Definition hoare_triple (P : Assertion) (c : com) (Q : Assertion)
: Prop :=
forall st st', st =[ c ]=> st' -> P st -> Q st'.
Notation "{{ P }} c {{ Q }}" :=
(hoare_triple P c Q) (at level 90, c custom com at level 99).
(** To make sure you've got the evaluation rules for [repeat] right,
prove that [ex1_repeat] evaluates correctly. *)
Definition ex1_repeat :=
<{ repeat
X := 1;
Y := Y + 1
until (X = 1) end }>.
Theorem ex1_repeat_works :
empty_st =[ ex1_repeat ]=> (Y !-> 1 ; X !-> 1).
Proof.
constructor.
econstructor.
- constructor. simpl. reflexivity.
- constructor. simpl. reflexivity.
- simpl. reflexivity.
Qed.
(** Now state and prove a theorem, [hoare_repeat], that expresses an
appropriate proof rule for [repeat] commands. Use [hoare_while]
as a model, and try to make your rule as precise as possible. *)
Theorem hoare_repeat: forall P c (b: bexp),
{{ P }} c {{ P }} ->
{{ P }} repeat c until b end {{ P /\ b }}.
Proof.
unfold hoare_triple.
intro_all.
remember <{ repeat c until b end }> as prog.
induction H0; inversion Heqprog; subst; clear Heqprog.
- (* repeat true *)
simpl in H.
specialize H with (st := st) (st' := st').
apply (H H0) in H1.
split; assumption.
- (* repeat false *)
simpl.
apply (H st st' H0_) in H1.
apply IHceval2; try reflexivity.
apply H1.
Qed.
Theorem hoare_repeat': forall P Q c (b: bexp),
{{ P }} c {{ (P /\ ~b) \/ (Q /\ b) }} ->
{{ P }} repeat c until b end {{ Q /\ b }}.
Proof.
unfold hoare_triple.
intro_all.
remember <{ repeat c until b end }> as prog.
induction H0; inversion Heqprog; subst; clear Heqprog.
- (* repeat true *)
simpl in H.
specialize H with (st := st) (st' := st').
apply (H H0) in H1.
destruct H1.
+ destruct H1. congruence.
+ destruct H1; split; assumption.
- (* repeat false *)
simpl.
apply (H st st' H0_) in H1.
destruct H1.
+ apply IHceval2; try reflexivity.
apply H1.
+ destruct H1. congruence.
Qed.
(** For full credit, make sure (informally) that your rule can be used
to prove the following valid Hoare triple:
{{ X > 0 }}
repeat
Y := X;
X := X - 1
until X = 0 end
{{ X = 0 /\ Y > 0 }}
*)
Theorem hoare_consequence_post : forall (P Q Q' : Assertion) c,
{{P}} c {{Q'}} ->
Q' ->> Q ->
{{P}} c {{Q}}.
Proof.
unfold hoare_triple, "->>".
intros P Q Q' c Hhoare Himp st st' Heval Hpre.
apply Himp.
apply Hhoare with (st := st).
- assumption.
- assumption.
Qed.
Theorem hoare_consequence_pre : forall (P P' Q : Assertion) c,
{{P'}} c {{Q}} ->
P ->> P' ->
{{P}} c {{Q}}.
Proof.
unfold hoare_triple, "->>".
intros P P' Q c Hhoare Himp st st' Heval Hpre.
apply Hhoare with (st := st).
- assumption.
- apply Himp. assumption.
Qed.
Theorem hoare_consequence : forall (P P' Q Q' : Assertion) c,
{{P'}} c {{Q'}} ->
P ->> P' ->
Q' ->> Q ->
{{P}} c {{Q}}.
Proof.
intros P P' Q Q' c Htriple Hpre Hpost.
apply hoare_consequence_pre with (P' := P').
- apply hoare_consequence_post with (Q' := Q').
+ assumption.
+ assumption.
- assumption.
Qed.
Theorem hoare_asgn : forall Q X a,
{{Q [X |-> a]}} (X := a) {{Q}}.
Proof.
intros Q X a st st' Heval HQ.
inversion Heval; subst.
auto.
Qed.
Theorem hoare_seq : forall P Q R c1 c2,
{{Q}} c2 {{R}} ->
{{P}} c1 {{Q}} ->
{{P}} c1; c2 {{R}}.
Proof.
unfold hoare_triple.
intros P Q R c1 c2 H1 H2 st st' H12 Pre.
inversion H12; subst.
eauto.
Qed.
Example hoare_repeat_example_1:
{{ X > 0 }}
repeat
Y := X;
X := X - 1
until X = 0 end
{{ X = 0 /\ Y > 0 }}.
Proof.
eapply hoare_consequence_post.
- apply hoare_repeat' with (Q := (Y > 0)%assertion).
eapply hoare_seq.
+ apply hoare_asgn.
+ eapply hoare_consequence_pre.
* apply hoare_asgn.
* assn_auto''.
- assn_auto''.
Qed.
End RepeatExercise.
(* Do not modify the following line: *)
Definition manual_grade_for_hoare_repeat : option (nat*string) := None.
(** [] *)
(* ################################################################# *)
(** * Summary *)
(** So far, we've introduced Hoare Logic as a tool for reasoning about
Imp programs.
The rules of Hoare Logic are:
--------------------------- (hoare_asgn)
{{Q [X |-> a]}} X:=a {{Q}}
-------------------- (hoare_skip)
{{ P }} skip {{ P }}
{{ P }} c1 {{ Q }}
{{ Q }} c2 {{ R }}
---------------------- (hoare_seq)
{{ P }} c1;c2 {{ R }}
{{P /\ b}} c1 {{Q}}
{{P /\ ~ b}} c2 {{Q}}
------------------------------------ (hoare_if)
{{P}} if b then c1 else c2 end {{Q}}
{{P /\ b}} c {{P}}
----------------------------------- (hoare_while)
{{P}} while b do c end {{P /\ ~ b}}
{{P'}} c {{Q'}}
P ->> P'
Q' ->> Q
----------------------------- (hoare_consequence)
{{P}} c {{Q}}
In the next chapter, we'll see how these rules are used to prove
that programs satisfy specifications of their behavior. *)
(* ################################################################# *)
(** * Additional Exercises *)
(* ================================================================= *)
(** ** Havoc *)
(** In this exercise, we will derive proof rules for a [HAVOC]
command, which is similar to the nondeterministic [any] expression
from the the [Imp] chapter.
First, we enclose this work in a separate module, and recall the
syntax and big-step semantics of Himp commands. *)
Module Himp.
Inductive com : Type :=
| CSkip : com
| CAss : string -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CHavoc : string -> com.
Notation "'havoc' l" := (CHavoc l)
(in custom com at level 60, l constr at level 0).
Notation "'skip'" :=
CSkip (in custom com at level 0).
Notation "x := y" :=
(CAss x y)
(in custom com at level 0, x constr at level 0,
y at level 85, no associativity).
Notation "x ; y" :=
(CSeq x y)
(in custom com at level 90, right associativity).
Notation "'if' x 'then' y 'else' z 'end'" :=
(CIf x y z)
(in custom com at level 89, x at level 99,
y at level 99, z at level 99).
Notation "'while' x 'do' y 'end'" :=
(CWhile x y)
(in custom com at level 89, x at level 99, y at level 99).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st,
st =[ skip ]=> st
| E_Ass : forall st a1 n x,
aeval st a1 = n ->
st =[ x := a1 ]=> (x !-> n ; st)
| E_Seq : forall c1 c2 st st' st'',
st =[ c1 ]=> st' ->
st' =[ c2 ]=> st'' ->
st =[ c1 ; c2 ]=> st''
| E_IfTrue : forall st st' b c1 c2,
beval st b = true ->
st =[ c1 ]=> st' ->
st =[ if b then c1 else c2 end ]=> st'
| E_IfFalse : forall st st' b c1 c2,
beval st b = false ->
st =[ c2 ]=> st' ->
st =[ if b then c1 else c2 end ]=> st'
| E_WhileFalse : forall b st c,
beval st b = false ->
st =[ while b do c end ]=> st
| E_WhileTrue : forall st st' st'' b c,
beval st b = true ->
st =[ c ]=> st' ->
st' =[ while b do c end ]=> st'' ->
st =[ while b do c end ]=> st''
| E_Havoc : forall st X n,
st =[ havoc X ]=> (X !-> n ; st)
where "st '=[' c ']=>' st'" := (ceval c st st').
Hint Constructors ceval : core.
(** The definition of Hoare triples is exactly as before. *)
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion) : Prop :=
forall st st', st =[ c ]=> st' -> P st -> Q st'.
Hint Unfold hoare_triple : core.
Notation "{{ P }} c {{ Q }}" := (hoare_triple P c Q)
(at level 90, c custom com at level 99)
: hoare_spec_scope.
(** And the precondition consequence rule is exactly as before. *)
Theorem hoare_consequence_pre : forall (P P' Q : Assertion) c,
{{P'}} c {{Q}} ->
P ->> P' ->
{{P}} c {{Q}}.
Proof. eauto. Qed.
(** **** Exercise: 3 stars, standard (hoare_havoc) *)
(** Complete the Hoare rule for [HAVOC] commands below by defining
[havoc_pre], and prove that the resulting rule is correct. *)
(* Let me first try out some examples *)
Example hoare_havoc_example_1:
{{ Y = 1 }} havoc X {{ Y = 1 }}.
Proof. intro_all. inversion H; subst. assn_auto''. Qed.
Example hoare_havoc_example_2:
{{ False }} havoc X {{ X = 1 }}.
Proof. intro_all. inversion H; subst. assn_auto''. Qed.
Example hoare_havoc_example_3:
{{ True }} havoc X {{ X >= 0 }}.
Proof. intro_all. inversion H; subst. assn_auto''. Qed.
Definition havoc_pre (X : string) (Q : Assertion) (st : total_map nat) : Prop :=
forall n, Q (X !-> n; st).
Theorem hoare_havoc : forall (Q : Assertion) (X : string),
{{ havoc_pre X Q }} havoc X {{ Q }}.
Proof.
unfold havoc_pre.
intro_all.
(* destruct H0 as [n0 H0]. *)
inversion H; subst; clear H.
(* destruct (eqb_spec n0 n). *)
specialize H0 with n.
apply H0.
Qed.
(** [] *)
(** **** Exercise: 3 stars, standard (havoc_post) *)
(** Complete the following proof without changing any of the provided
commands. If you find that it can't be completed, your definition of
[havoc_pre] is probably too strong. Find a way to relax it so that
[havoc_post] can be proved.
Hint: the [assn_auto] tactics we've built won't help you here.
You need to proceed manually. *)
Theorem havoc_post : forall (P : Assertion) (X : string),
{{ P }} havoc X {{ fun st => exists (n:nat), P [X |-> n] st }}.
Proof.
intros P X. eapply hoare_consequence_pre.
- apply hoare_havoc.
- unfold havoc_pre, "->>", assn_sub, bassn. simpl.
intros.
exists (st X).
rewrite t_update_shadow.
rewrite t_update_same.
apply H.
Qed.
(** [] *)
End Himp.
(* ================================================================= *)
(** ** Assert and Assume *)
(** **** Exercise: 4 stars, standard, optional (assert_vs_assume) *)
Module HoareAssertAssume.
(** In this exercise, we will extend IMP with two commands,
[assert] and [ASSUME]. Both commands are ways
to indicate that a certain statement should hold any time this part
of the program is reached. However they differ as follows:
- If an [assert] statement fails, it causes the program to go into
an error state and exit.
- If an [ASSUME] statement fails, the program fails to evaluate
at all. In other words, the program gets stuck and has no
final state.
The new set of commands is: *)
Inductive com : Type :=
| CSkip : com
| CAss : string -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CAssert : bexp -> com
| CAssume : bexp -> com.
Notation "'assert' l" := (CAssert l)
(in custom com at level 8, l custom com at level 0).
Notation "'assume' l" := (CAssume l)
(in custom com at level 8, l custom com at level 0).
Notation "'skip'" :=
CSkip (in custom com at level 0).
Notation "x := y" :=
(CAss x y)
(in custom com at level 0, x constr at level 0,
y at level 85, no associativity).
Notation "x ; y" :=
(CSeq x y)
(in custom com at level 90, right associativity).
Notation "'if' x 'then' y 'else' z 'end'" :=
(CIf x y z)
(in custom com at level 89, x at level 99,
y at level 99, z at level 99).
Notation "'while' x 'do' y 'end'" :=
(CWhile x y)
(in custom com at level 89, x at level 99, y at level 99).
(** To define the behavior of [assert] and [ASSUME], we need to add
notation for an error, which indicates that an assertion has
failed. We modify the [ceval] relation, therefore, so that
it relates a start state to either an end state or to [error].
The [result] type indicates the end value of a program,
either a state or an error: *)
Inductive result : Type :=
| RNormal : state -> result
| RError : result.
(** Now we are ready to give you the ceval relation for the new language. *)
Inductive ceval : com -> state -> result -> Prop :=
(* Old rules, several modified *)
| E_Skip : forall st,
st =[ skip ]=> RNormal st
| E_Ass : forall st a1 n x,
aeval st a1 = n ->
st =[ x := a1 ]=> RNormal (x !-> n ; st)
| E_SeqNormal : forall c1 c2 st st' r,
st =[ c1 ]=> RNormal st' ->
st' =[ c2 ]=> r ->
st =[ c1 ; c2 ]=> r
| E_SeqError : forall c1 c2 st,
st =[ c1 ]=> RError ->
st =[ c1 ; c2 ]=> RError
| E_IfTrue : forall st r b c1 c2,
beval st b = true ->
st =[ c1 ]=> r ->
st =[ if b then c1 else c2 end ]=> r
| E_IfFalse : forall st r b c1 c2,
beval st b = false ->
st =[ c2 ]=> r ->
st =[ if b then c1 else c2 end ]=> r
| E_WhileFalse : forall b st c,
beval st b = false ->
st =[ while b do c end ]=> RNormal st
| E_WhileTrueNormal : forall st st' r b c,
beval st b = true ->
st =[ c ]=> RNormal st' ->
st' =[ while b do c end ]=> r ->
st =[ while b do c end ]=> r
| E_WhileTrueError : forall st b c,
beval st b = true ->
st =[ c ]=> RError ->
st =[ while b do c end ]=> RError
(* Rules for Assert and Assume *)
| E_AssertTrue : forall st b,
beval st b = true ->
st =[ assert b ]=> RNormal st
| E_AssertFalse : forall st b,
beval st b = false ->
st =[ assert b ]=> RError
| E_Assume : forall st b,
beval st b = true ->
st =[ assume b ]=> RNormal st
where "st '=[' c ']=>' r" := (ceval c st r).
(** We redefine hoare triples: Now, [{{P}} c {{Q}}] means that,
whenever [c] is started in a state satisfying [P], and terminates
with result [r], then [r] is not an error and the state of [r]
satisfies [Q]. *)
Definition hoare_triple
(P : Assertion) (c : com) (Q : Assertion) : Prop :=
forall st r,
st =[ c ]=> r -> P st ->
(exists st', r = RNormal st' /\ Q st').
Notation "{{ P }} c {{ Q }}" :=
(hoare_triple P c Q) (at level 90, c custom com at level 99)
: hoare_spec_scope.
(** To test your understanding of this modification, give an example
precondition and postcondition that are satisfied by the [ASSUME]
statement but not by the [assert] statement. Then prove that any
triple for [assert] also works for [ASSUME]. *)
Theorem assert_assume_differ : exists (P:Assertion) b (Q:Assertion),
({{P}} assume b {{Q}}) /\ ~ ({{P}} assert b {{Q}}).
Proof.
exists (True%assertion).
exists <{ 0 = 1 }>.
exists (True%assertion).
split.
- intro_all.
inversion H; subst; clear H. simpl in H2. inversion H2.
- intro_all.
unfold hoare_triple in H.
pose_st st.
specialize H with (st:=st) (r:=RError).
assert (st =[ assert (0 = 1) ]=> RError) by now constructor.
assert (True%assertion) by auto.
apply (H H0) in H1.
destruct H1 as [st' [H1 H2]].
inversion H1.
Qed.
Theorem assert_implies_assume : forall P b Q,
({{P}} assert b {{Q}})
-> ({{P}} assume b {{Q}}).
Proof.
unfold hoare_triple.
intro_all.
inversion H0; subst.
exists st. split; try reflexivity.
specialize H with st (RNormal st).
assert (st =[ assert b ]=> RNormal st) by now constructor.
apply (H H2) in H1. destruct H1. destruct H1.
inversion H1; subst. apply H4.
Qed.
(** Your task is now to state Hoare rules for [assert] and [assume],
and use them to prove a simple program correct. Name your hoare
rule theorems [hoare_assert] and [hoare_assume].
For your benefit, we provide proofs for the old hoare rules
adapted to the new semantics. *)
Theorem hoare_asgn : forall Q X a,
{{Q [X |-> a]}} X := a {{Q}}.
Proof.
unfold hoare_triple.
intros Q X a st st' HE HQ.
inversion HE. subst.
exists (X !-> aeval st a ; st). split; try reflexivity.
assumption. Qed.
Theorem hoare_consequence_pre : forall (P P' Q : Assertion) c,
{{P'}} c {{Q}} ->
P ->> P' ->
{{P}} c {{Q}}.
Proof.
intros P P' Q c Hhoare Himp.
intros st st' Hc HP. apply (Hhoare st st').
assumption. apply Himp. assumption. Qed.
Theorem hoare_consequence_post : forall (P Q Q' : Assertion) c,
{{P}} c {{Q'}} ->
Q' ->> Q ->
{{P}} c {{Q}}.
Proof.
intros P Q Q' c Hhoare Himp.
intros st r Hc HP.
unfold hoare_triple in Hhoare.
assert (exists st', r = RNormal st' /\ Q' st').
{ apply (Hhoare st); assumption. }
destruct H as [st' [Hr HQ'] ].
exists st'. split; try assumption.
apply Himp. assumption.
Qed.
Theorem hoare_seq : forall P Q R c1 c2,
{{Q}} c2 {{R}} ->
{{P}} c1 {{Q}} ->
{{P}} c1;c2 {{R}}.
Proof.
intros P Q R c1 c2 H1 H2 st r H12 Pre.
inversion H12; subst.
- eapply H1.
+ apply H6.
+ apply H2 in H3. apply H3 in Pre.
destruct Pre as [st'0 [Heq HQ] ].
inversion Heq; subst. assumption.
- (* Find contradictory assumption *)
apply H2 in H5. apply H5 in Pre.
destruct Pre as [st' [C _] ].
inversion C.
Qed.
(** State and prove your hoare rules, [hoare_assert] and
[hoare_assume], below. *)
Theorem hoare_assert : forall P (b : bexp),
{{ P /\ b }} assert b {{ P }}.
Proof.
intro_all.
inversion H; subst; clear H.
- (* Assert true *)
exists st. easy.
- (* Assert false *)
destruct H0. congruence.
Qed.
Theorem hoare_assume : forall P (b : bexp),
{{ P }} assume b {{ P /\ b }}.
Proof.
intro_all.
inversion H; subst; clear H.
exists st. easy.
Qed.
(** Here are the other proof rules (sanity check) *)
(* NOTATION : IY -- Do we want <{ }> to be printing in here? *)
Theorem hoare_skip : forall P,
{{P}} skip {{P}}.
Proof.
intros P st st' H HP. inversion H. subst.
eexists. split. reflexivity. assumption.
Qed.
Theorem hoare_if : forall P Q (b:bexp) c1 c2,
{{ P /\ b}} c1 {{Q}} ->
{{ P /\ ~ b}} c2 {{Q}} ->
{{P}} if b then c1 else c2 end {{Q}}.
Proof.
intros P Q b c1 c2 HTrue HFalse st st' HE HP.
inversion HE; subst.
- (* b is true *)
apply (HTrue st st').
assumption.
split. assumption.
apply bexp_eval_true. assumption.
- (* b is false *)
apply (HFalse st st').
assumption.
split. assumption.
apply bexp_eval_false. assumption. Qed.
Theorem hoare_while : forall P (b:bexp) c,
{{P /\ b}} c {{P}} ->
{{P}} while b do c end {{ P /\ ~b}}.
Proof.
intros P b c Hhoare st st' He HP.
remember <{while b do c end}> as wcom eqn:Heqwcom.
induction He;
try (inversion Heqwcom); subst; clear Heqwcom.
- (* E_WhileFalse *)
eexists. split. reflexivity. split.
assumption. apply bexp_eval_false. assumption.
- (* E_WhileTrueNormal *)
clear IHHe1.
apply IHHe2. reflexivity.
clear IHHe2 He2 r.
unfold hoare_triple in Hhoare.
apply Hhoare in He1.
+ destruct He1 as [st1 [Heq Hst1] ].
inversion Heq; subst.
assumption.
+ split; assumption.
- (* E_WhileTrueError *)
exfalso. clear IHHe.
unfold hoare_triple in Hhoare.
apply Hhoare in He.
+ destruct He as [st' [C _] ]. inversion C.
+ split; assumption.
Qed.
Example assert_assume_example:
{{True}}
assume (X = 1);
X := X + 1;
assert (X = 2)
{{True}}.
Proof.
eapply hoare_seq.
- (* {{?Q}} X := X + 1; assert (X = 2) {{True}} *)
eapply hoare_seq.
+ apply hoare_assert.
+ apply hoare_asgn.
- (* {{True}} assume (X = 1) {{(fun st : state => True st /\ <{ X = 2 }> st) [X |-> X + 1]}} *)
eapply hoare_consequence_post.
+ apply hoare_assume.
+ assn_auto''.
Qed.
End HoareAssertAssume.
(** [] *)
(* 2020-09-09 21:08 *)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A21BOI_FUNCTIONAL_V
`define SKY130_FD_SC_HS__A21BOI_FUNCTIONAL_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a21boi (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
B1_N
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Local signals
wire b ;
wire and0_out ;
wire nor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , b, and0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A21BOI_FUNCTIONAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A22OI_FUNCTIONAL_V
`define SKY130_FD_SC_HD__A22OI_FUNCTIONAL_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__a22oi (
Y ,
A1,
A2,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y, nand0_out, nand1_out);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A22OI_FUNCTIONAL_V |
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21AI_1_V
`define SKY130_FD_SC_LP__O21AI_1_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog wrapper for o21ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o21ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o21ai_1 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o21ai_1 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21AI_1_V
|
// ==========================================================================
// crc Generation Unit - Linear Feedback Shift Register implementation
// (c) Kay Gorontzi, GHSi.de, distributed under the terms of LGPL
// https://www.ghsi.de/crc/index.php?
// https://www.ghsi.de/crc/index.php?
// =========================================================================
module sd_crc_16(
input clk, // Current bit valid (Clock)
input rst, // Init crc value
input en,
input bitval, // Next input bit
output reg [15:0] crc // Current output crc value
);
//Local Parameters
//Registers/Wires
wire inv;
//Submodules
//Asynchronous Logic
//Synchronsou Logic
assign inv = bitval ^ crc[15]; // XOR required?
always @(posedge clk or posedge rst) begin
if (rst) begin
crc = 0;
end
else begin
if (en==1) begin
crc[15] = crc[14];
crc[14] = crc[13];
crc[13] = crc[12];
crc[12] = crc[11] ^ inv;
crc[11] = crc[10];
crc[10] = crc[9];
crc[9] = crc[8];
crc[8] = crc[7];
crc[7] = crc[6];
crc[6] = crc[5];
crc[5] = crc[4] ^ inv;
crc[4] = crc[3];
crc[3] = crc[2];
crc[2] = crc[1];
crc[1] = crc[0];
crc[0] = inv;
end
end
end
endmodule
|
// ghrd_10as066n2_pr_region_controller_0.v
// Generated using ACDS version 17.1 240
`timescale 1 ps / 1 ps
module ghrd_10as066n2_pr_region_controller_0 (
input wire avl_csr_read, // avl_csr.read
input wire avl_csr_write, // .write
input wire [1:0] avl_csr_address, // .address
input wire [31:0] avl_csr_writedata, // .writedata
output wire [31:0] avl_csr_readdata, // .readdata
output wire bridge_freeze0_freeze, // bridge_freeze0.freeze
input wire bridge_freeze0_illegal_request, // .illegal_request
output wire bridge_freeze1_freeze, // bridge_freeze1.freeze
input wire bridge_freeze1_illegal_request, // .illegal_request
input wire clock_clk, // clock.clk
output wire pr_handshake_start_req, // pr_handshake.start_req
input wire pr_handshake_start_ack, // .start_ack
output wire pr_handshake_stop_req, // .stop_req
input wire pr_handshake_stop_ack, // .stop_ack
input wire reset_reset, // reset.reset
output wire reset_source_reset // reset_source.reset
);
ghrd_10as066n2_pr_region_controller_0_altera_pr_region_controller_171_lvntgla pr_region_controller_0 (
.avl_csr_read (avl_csr_read), // input, width = 1, avl_csr.read
.avl_csr_write (avl_csr_write), // input, width = 1, .write
.avl_csr_address (avl_csr_address), // input, width = 2, .address
.avl_csr_writedata (avl_csr_writedata), // input, width = 32, .writedata
.avl_csr_readdata (avl_csr_readdata), // output, width = 32, .readdata
.bridge_freeze0_freeze (bridge_freeze0_freeze), // output, width = 1, bridge_freeze0.freeze
.bridge_freeze0_illegal_request (bridge_freeze0_illegal_request), // input, width = 1, .illegal_request
.bridge_freeze1_freeze (bridge_freeze1_freeze), // output, width = 1, bridge_freeze1.freeze
.bridge_freeze1_illegal_request (bridge_freeze1_illegal_request), // input, width = 1, .illegal_request
.clock_clk (clock_clk), // input, width = 1, clock.clk
.pr_handshake_start_req (pr_handshake_start_req), // output, width = 1, pr_handshake.start_req
.pr_handshake_start_ack (pr_handshake_start_ack), // input, width = 1, .start_ack
.pr_handshake_stop_req (pr_handshake_stop_req), // output, width = 1, .stop_req
.pr_handshake_stop_ack (pr_handshake_stop_ack), // input, width = 1, .stop_ack
.reset_reset (reset_reset), // input, width = 1, reset.reset
.reset_source_reset (reset_source_reset) // output, width = 1, reset_source.reset
);
endmodule
|
// File: ./ex-target/WordContextProduct.v
// Generated by MyHDL 1.0dev
// Date: Mon Oct 5 14:11:53 2015
`timescale 1ns/10ps
module WordContextProduct (
y,
y_dword_vec,
y_dcontext_vec,
word_embv,
context_embv
);
// Word-context embeddings product and derivative model.
//
// :param y: return relu(dot(word_emb, context_emb)) as fixbv
// :param y_dword_vec: return d/dword relu(dot(word_emb, context_emb)) as vector of fixbv
// :param y_dcontext_vec: return d/dcontext relu(dot(word_emb, context_emb)) as vector of fixbv
// :param word_embv: word embedding vector of fixbv
// :param context_embv: context embedding vector of fixbv
// :param embedding_dim: embedding dimensionality
// :param leaky_val: factor for leaky ReLU, 0.0 without
// :param fix_min: fixbv min value
// :param fix_max: fixbv max value
// :param fix_res: fixbv resolution
output signed [15:0] y;
reg signed [15:0] y;
output [47:0] y_dword_vec;
reg [47:0] y_dword_vec;
output [47:0] y_dcontext_vec;
reg [47:0] y_dcontext_vec;
output [47:0] word_embv;
wire [47:0] word_embv;
output [47:0] context_embv;
wire [47:0] context_embv;
wire [47:0] y_dot_dword_vec;
reg signed [15:0] y_dot;
reg signed [15:0] y_relu_dx;
wire [47:0] y_dot_dcontext_vec;
wire signed [15:0] y_dot_dword_list [0:3-1];
wire signed [15:0] y_dot_dcontext_list [0:3-1];
wire signed [15:0] dot_a_list [0:3-1];
wire signed [15:0] dot_b_list [0:3-1];
assign context_embv[48-1:32] = None;
assign context_embv[32-1:16] = None;
assign context_embv[16-1:0] = None;
assign word_embv[48-1:32] = None;
assign word_embv[32-1:16] = None;
assign word_embv[16-1:0] = None;
always @(dot_a_list[0], dot_a_list[1], dot_a_list[2], dot_b_list[0], dot_b_list[1], dot_b_list[2]) begin: WORDCONTEXTPRODUCT_DOT_DOT
reg signed [32-1:0] y_sum;
integer j;
y_sum = fixbv(0.0);
for (j=0; j<3; j=j+1) begin
y_sum = (y_sum + (dot_a_list[j] * dot_b_list[j]));
end
y_dot = fixbv(y_sum);
end
assign y_dot_dword_vec = context_embv;
assign y_dot_dcontext_vec = word_embv;
always @(y_dot) begin: WORDCONTEXTPRODUCT_RELU_RELU
reg signed [16-1:0] zero;
reg signed [16-1:0] leaky;
if ((y_dot > zero)) begin
y = y_dot;
end
else begin
y = fixbv((leaky * y_dot));
end
end
always @(y_dot) begin: WORDCONTEXTPRODUCT_RELU_RELU_DX
reg signed [16-1:0] zero;
reg signed [16-1:0] leaky;
reg signed [16-1:0] one;
if ((y_dot > zero)) begin
y_relu_dx = one;
end
else begin
y_relu_dx = leaky;
end
end
always @(y_relu_dx, y_dot_dword_list[0], y_dot_dword_list[1], y_dot_dword_list[2]) begin: WORDCONTEXTPRODUCT_WCPROD_DWORD
integer j;
reg signed [16-1:0] prod;
for (j=0; j<3; j=j+1) begin
prod = fixbv((y_relu_dx * y_dot_dword_list[j]));
y_dword_vec[((j + 1) * 16)-1:(j * 16)] = prod;
end
end
always @(y_relu_dx, y_dot_dcontext_list[0], y_dot_dcontext_list[1], y_dot_dcontext_list[2]) begin: WORDCONTEXTPRODUCT_WCPROD_DCONTEXT
integer j;
reg signed [16-1:0] prod;
for (j=0; j<3; j=j+1) begin
prod = fixbv((y_relu_dx * y_dot_dcontext_list[j]));
y_dcontext_vec[((j + 1) * 16)-1:(j * 16)] = prod;
end
end
endmodule
|
`include "../src/fsctl.v"
module test_fsctl();
parameter integer C_SPEED_DATA_WIDTH = 16;
parameter integer C_REG_IDX_WIDTH = 8;
reg clk;
reg resetn;
reg wr_en;
reg[C_REG_IDX_WIDTH-1:0] wr_addr = 0;
reg[31:0] wr_data;
reg o_clk;
reg o_resetn;
wire br0_init;
wire br0_wr_en;
wire [C_SPEED_DATA_WIDTH-1:0] br0_data;
reg motor0_zpsign;
fsctl # (
.C_REG_IDX_WIDTH(C_REG_IDX_WIDTH),
.C_SPEED_DATA_WIDTH(C_SPEED_DATA_WIDTH)
) fsctl_inst (
.clk(clk),
.resetn(resetn),
.wr_en(wr_en),
.wr_addr(wr_addr),
.wr_data(wr_data),
.o_clk(o_clk),
.o_resetn(o_resetn),
.br0_init(br0_init),
.br0_wr_en(br0_wr_en),
.br0_data(br0_data),
.motor0_zpsign(motor0_zpsign)
);
initial begin
clk <= 1'b1;
forever #4 clk <= ~clk;
end
initial begin
o_clk <= 1'b1;
repeat (1) #1 o_clk <= 1'b1;
forever #1 o_clk <= ~o_clk;
end
initial begin
resetn <= 1'b0;
repeat (5) #2 resetn <= 1'b0;
forever #2 resetn <= 1'b1;
end
initial begin
o_resetn <= 1'b0;
repeat (5) #2 o_resetn <= 1'b0;
forever #2 o_resetn <= 1'b1;
end
reg[31:0] datacnt;
always @ (posedge clk) begin
if (resetn == 1'b0) begin
wr_en <= 0;
wr_addr <= 0;
wr_data <= 0;
datacnt <= 0;
end
else if (br0_init == 0) begin
if (datacnt == 0) begin
wr_en <= 1;
wr_addr <= 30;
wr_data <= 3;
end
else begin
wr_en <= 1;
wr_addr <= 34;
wr_data <= 32'hFFFFFFFF;
end
end
else if (br0_init == 1) begin
if (datacnt < 15) begin
if ({$random}%2 == 1) begin
wr_en <= 1;
wr_addr <= 31;
wr_data <= datacnt;
datacnt <= datacnt + 1;
end
else begin
wr_en <= 0;
end
end
else begin
wr_en <= 1;
wr_addr <= 30;
wr_data <= 0;
end
end
end
initial begin
motor0_zpsign <= 1'b0;
repeat (5) #2 motor0_zpsign <= 1'b0;
repeat (1000) #2 motor0_zpsign <= 1'b1;
end
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 09:39:16 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_auto_pc_0/zynq_design_1_auto_pc_0_sim_netlist.v
// Design : zynq_design_1_auto_pc_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "zynq_design_1_auto_pc_0,axi_protocol_converter_v2_1_13_axi_protocol_converter,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2" *)
(* NotValidForBitStream *)
module zynq_design_1_auto_pc_0
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *) input aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *) input aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *) input [11:0]s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [31:0]s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *) input [7:0]s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *) input [2:0]s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *) input [1:0]s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *) input [0:0]s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *) input [3:0]s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *) input [2:0]s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *) input [3:0]s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *) input [3:0]s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *) input s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *) output [11:0]s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *) input [11:0]s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [31:0]s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *) input [7:0]s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *) input [2:0]s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *) input [1:0]s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *) input [0:0]s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *) input [3:0]s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *) input [2:0]s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *) input [3:0]s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *) input [3:0]s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *) output [11:0]s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *) output s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) output [31:0]m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) output [2:0]m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) output m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) input m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) output [31:0]m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *) output [3:0]m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) output m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) input m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) input [1:0]m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) input m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) output m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) output [31:0]m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) output [2:0]m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) output m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) input m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) input [31:0]m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) input [1:0]m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) input m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) output m_axi_rready;
wire aclk;
wire aresetn;
wire [31:0]m_axi_araddr;
wire [2:0]m_axi_arprot;
wire m_axi_arready;
wire m_axi_arvalid;
wire [31:0]m_axi_awaddr;
wire [2:0]m_axi_awprot;
wire m_axi_awready;
wire m_axi_awvalid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire [31:0]m_axi_rdata;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire [31:0]m_axi_wdata;
wire m_axi_wready;
wire [3:0]m_axi_wstrb;
wire m_axi_wvalid;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire s_axi_arready;
wire [3:0]s_axi_arregion;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [0:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire s_axi_awready;
wire [3:0]s_axi_awregion;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire NLW_inst_m_axi_wlast_UNCONNECTED;
wire [1:0]NLW_inst_m_axi_arburst_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_arcache_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_arid_UNCONNECTED;
wire [7:0]NLW_inst_m_axi_arlen_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_arlock_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_arqos_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_arregion_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_arsize_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_aruser_UNCONNECTED;
wire [1:0]NLW_inst_m_axi_awburst_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_awcache_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_awid_UNCONNECTED;
wire [7:0]NLW_inst_m_axi_awlen_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_awlock_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_awqos_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_awregion_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_awsize_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_awuser_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_wid_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_wuser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED;
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "32" *)
(* C_AXI_ID_WIDTH = "12" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_SUPPORTS_READ = "1" *)
(* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_SUPPORTS_WRITE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_FAMILY = "zynq" *)
(* C_IGNORE_ID = "0" *)
(* C_M_AXI_PROTOCOL = "2" *)
(* C_S_AXI_PROTOCOL = "0" *)
(* C_TRANSLATION_MODE = "2" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
(* P_AXI3 = "1" *)
(* P_AXI4 = "0" *)
(* P_AXILITE = "2" *)
(* P_AXILITE_SIZE = "3'b010" *)
(* P_CONVERSION = "2" *)
(* P_DECERR = "2'b11" *)
(* P_INCR = "2'b01" *)
(* P_PROTECTION = "1" *)
(* P_SLVERR = "2'b10" *)
zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter inst
(.aclk(aclk),
.aresetn(aresetn),
.m_axi_araddr(m_axi_araddr),
.m_axi_arburst(NLW_inst_m_axi_arburst_UNCONNECTED[1:0]),
.m_axi_arcache(NLW_inst_m_axi_arcache_UNCONNECTED[3:0]),
.m_axi_arid(NLW_inst_m_axi_arid_UNCONNECTED[11:0]),
.m_axi_arlen(NLW_inst_m_axi_arlen_UNCONNECTED[7:0]),
.m_axi_arlock(NLW_inst_m_axi_arlock_UNCONNECTED[0]),
.m_axi_arprot(m_axi_arprot),
.m_axi_arqos(NLW_inst_m_axi_arqos_UNCONNECTED[3:0]),
.m_axi_arready(m_axi_arready),
.m_axi_arregion(NLW_inst_m_axi_arregion_UNCONNECTED[3:0]),
.m_axi_arsize(NLW_inst_m_axi_arsize_UNCONNECTED[2:0]),
.m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awburst(NLW_inst_m_axi_awburst_UNCONNECTED[1:0]),
.m_axi_awcache(NLW_inst_m_axi_awcache_UNCONNECTED[3:0]),
.m_axi_awid(NLW_inst_m_axi_awid_UNCONNECTED[11:0]),
.m_axi_awlen(NLW_inst_m_axi_awlen_UNCONNECTED[7:0]),
.m_axi_awlock(NLW_inst_m_axi_awlock_UNCONNECTED[0]),
.m_axi_awprot(m_axi_awprot),
.m_axi_awqos(NLW_inst_m_axi_awqos_UNCONNECTED[3:0]),
.m_axi_awready(m_axi_awready),
.m_axi_awregion(NLW_inst_m_axi_awregion_UNCONNECTED[3:0]),
.m_axi_awsize(NLW_inst_m_axi_awsize_UNCONNECTED[2:0]),
.m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'b0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rlast(1'b1),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_ruser(1'b0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[11:0]),
.m_axi_wlast(NLW_inst_m_axi_wlast_UNCONNECTED),
.m_axi_wready(m_axi_wready),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(m_axi_wvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arcache(s_axi_arcache),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arlock(s_axi_arlock),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_arready(s_axi_arready),
.s_axi_arregion(s_axi_arregion),
.s_axi_arsize(s_axi_arsize),
.s_axi_aruser(1'b0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awcache(s_axi_awcache),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awlock(s_axi_awlock),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awready(s_axi_awready),
.s_axi_awregion(s_axi_awregion),
.s_axi_awsize(s_axi_awsize),
.s_axi_awuser(1'b0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wuser(1'b0),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "32" *) (* C_AXI_ID_WIDTH = "12" *)
(* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_SUPPORTS_READ = "1" *) (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_SUPPORTS_WRITE = "1" *) (* C_AXI_WUSER_WIDTH = "1" *) (* C_FAMILY = "zynq" *)
(* C_IGNORE_ID = "0" *) (* C_M_AXI_PROTOCOL = "2" *) (* C_S_AXI_PROTOCOL = "0" *)
(* C_TRANSLATION_MODE = "2" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_axi_protocol_converter" *)
(* P_AXI3 = "1" *) (* P_AXI4 = "0" *) (* P_AXILITE = "2" *)
(* P_AXILITE_SIZE = "3'b010" *) (* P_CONVERSION = "2" *) (* P_DECERR = "2'b11" *)
(* P_INCR = "2'b01" *) (* P_PROTECTION = "1" *) (* P_SLVERR = "2'b10" *)
module zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready);
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [11:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awregion;
output [3:0]m_axi_awqos;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [11:0]m_axi_wid;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [11:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
output [11:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arregion;
output [3:0]m_axi_arqos;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [11:0]m_axi_rid;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
wire \<const0> ;
wire \<const1> ;
wire aclk;
wire aresetn;
wire [31:0]m_axi_araddr;
wire [2:0]m_axi_arprot;
wire m_axi_arready;
wire m_axi_arvalid;
wire [31:0]m_axi_awaddr;
wire [2:0]m_axi_awprot;
wire m_axi_awready;
wire m_axi_awvalid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire [31:0]m_axi_rdata;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire m_axi_wready;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const1> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[11] = \<const0> ;
assign m_axi_arid[10] = \<const0> ;
assign m_axi_arid[9] = \<const0> ;
assign m_axi_arid[8] = \<const0> ;
assign m_axi_arid[7] = \<const0> ;
assign m_axi_arid[6] = \<const0> ;
assign m_axi_arid[5] = \<const0> ;
assign m_axi_arid[4] = \<const0> ;
assign m_axi_arid[3] = \<const0> ;
assign m_axi_arid[2] = \<const0> ;
assign m_axi_arid[1] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const1> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const1> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[11] = \<const0> ;
assign m_axi_awid[10] = \<const0> ;
assign m_axi_awid[9] = \<const0> ;
assign m_axi_awid[8] = \<const0> ;
assign m_axi_awid[7] = \<const0> ;
assign m_axi_awid[6] = \<const0> ;
assign m_axi_awid[5] = \<const0> ;
assign m_axi_awid[4] = \<const0> ;
assign m_axi_awid[3] = \<const0> ;
assign m_axi_awid[2] = \<const0> ;
assign m_axi_awid[1] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const1> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_wdata[31:0] = s_axi_wdata;
assign m_axi_wid[11] = \<const0> ;
assign m_axi_wid[10] = \<const0> ;
assign m_axi_wid[9] = \<const0> ;
assign m_axi_wid[8] = \<const0> ;
assign m_axi_wid[7] = \<const0> ;
assign m_axi_wid[6] = \<const0> ;
assign m_axi_wid[5] = \<const0> ;
assign m_axi_wid[4] = \<const0> ;
assign m_axi_wid[3] = \<const0> ;
assign m_axi_wid[2] = \<const0> ;
assign m_axi_wid[1] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast = \<const1> ;
assign m_axi_wstrb[3:0] = s_axi_wstrb;
assign m_axi_wuser[0] = \<const0> ;
assign m_axi_wvalid = s_axi_wvalid;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
assign s_axi_wready = m_axi_wready;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s \gen_axilite.gen_b2s_conv.axilite_b2s
(.Q({m_axi_awprot,m_axi_awaddr[31:12]}),
.aclk(aclk),
.aresetn(aresetn),
.in({m_axi_rresp,m_axi_rdata}),
.m_axi_araddr(m_axi_araddr[11:0]),
.\m_axi_arprot[2] ({m_axi_arprot,m_axi_araddr[31:12]}),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr[11:0]),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize[1:0]),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize[1:0]),
.s_axi_awvalid(s_axi_awvalid),
.\s_axi_bid[11] ({s_axi_bid,s_axi_bresp}),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.\s_axi_rid[11] ({s_axi_rid,s_axi_rlast,s_axi_rresp,s_axi_rdata}),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s" *)
module zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s
(s_axi_rvalid,
s_axi_awready,
Q,
s_axi_arready,
\m_axi_arprot[2] ,
s_axi_bvalid,
\s_axi_bid[11] ,
\s_axi_rid[11] ,
m_axi_awvalid,
m_axi_bready,
m_axi_arvalid,
m_axi_rready,
m_axi_awaddr,
m_axi_araddr,
m_axi_awready,
m_axi_arready,
s_axi_rready,
s_axi_awvalid,
aclk,
in,
s_axi_awid,
s_axi_awlen,
s_axi_awburst,
s_axi_awsize,
s_axi_awprot,
s_axi_awaddr,
m_axi_bresp,
s_axi_arid,
s_axi_arlen,
s_axi_arburst,
s_axi_arsize,
s_axi_arprot,
s_axi_araddr,
m_axi_bvalid,
m_axi_rvalid,
s_axi_bready,
s_axi_arvalid,
aresetn);
output s_axi_rvalid;
output s_axi_awready;
output [22:0]Q;
output s_axi_arready;
output [22:0]\m_axi_arprot[2] ;
output s_axi_bvalid;
output [13:0]\s_axi_bid[11] ;
output [46:0]\s_axi_rid[11] ;
output m_axi_awvalid;
output m_axi_bready;
output m_axi_arvalid;
output m_axi_rready;
output [11:0]m_axi_awaddr;
output [11:0]m_axi_araddr;
input m_axi_awready;
input m_axi_arready;
input s_axi_rready;
input s_axi_awvalid;
input aclk;
input [33:0]in;
input [11:0]s_axi_awid;
input [7:0]s_axi_awlen;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awsize;
input [2:0]s_axi_awprot;
input [31:0]s_axi_awaddr;
input [1:0]m_axi_bresp;
input [11:0]s_axi_arid;
input [7:0]s_axi_arlen;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arsize;
input [2:0]s_axi_arprot;
input [31:0]s_axi_araddr;
input m_axi_bvalid;
input m_axi_rvalid;
input s_axi_bready;
input s_axi_arvalid;
input aresetn;
wire [11:4]C;
wire [22:0]Q;
wire \RD.ar_channel_0_n_10 ;
wire \RD.ar_channel_0_n_11 ;
wire \RD.ar_channel_0_n_47 ;
wire \RD.ar_channel_0_n_48 ;
wire \RD.ar_channel_0_n_49 ;
wire \RD.ar_channel_0_n_50 ;
wire \RD.ar_channel_0_n_8 ;
wire \RD.ar_channel_0_n_9 ;
wire \RD.r_channel_0_n_0 ;
wire \RD.r_channel_0_n_2 ;
wire SI_REG_n_134;
wire SI_REG_n_135;
wire SI_REG_n_136;
wire SI_REG_n_137;
wire SI_REG_n_138;
wire SI_REG_n_139;
wire SI_REG_n_140;
wire SI_REG_n_141;
wire SI_REG_n_142;
wire SI_REG_n_143;
wire SI_REG_n_144;
wire SI_REG_n_145;
wire SI_REG_n_146;
wire SI_REG_n_147;
wire SI_REG_n_148;
wire SI_REG_n_149;
wire SI_REG_n_150;
wire SI_REG_n_151;
wire SI_REG_n_158;
wire SI_REG_n_162;
wire SI_REG_n_163;
wire SI_REG_n_164;
wire SI_REG_n_165;
wire SI_REG_n_166;
wire SI_REG_n_167;
wire SI_REG_n_171;
wire SI_REG_n_175;
wire SI_REG_n_176;
wire SI_REG_n_177;
wire SI_REG_n_178;
wire SI_REG_n_179;
wire SI_REG_n_180;
wire SI_REG_n_181;
wire SI_REG_n_182;
wire SI_REG_n_183;
wire SI_REG_n_184;
wire SI_REG_n_185;
wire SI_REG_n_186;
wire SI_REG_n_187;
wire SI_REG_n_188;
wire SI_REG_n_189;
wire SI_REG_n_190;
wire SI_REG_n_191;
wire SI_REG_n_192;
wire SI_REG_n_193;
wire SI_REG_n_194;
wire SI_REG_n_195;
wire SI_REG_n_196;
wire SI_REG_n_20;
wire SI_REG_n_21;
wire SI_REG_n_22;
wire SI_REG_n_23;
wire SI_REG_n_29;
wire SI_REG_n_79;
wire SI_REG_n_80;
wire SI_REG_n_81;
wire SI_REG_n_82;
wire SI_REG_n_88;
wire \WR.aw_channel_0_n_10 ;
wire \WR.aw_channel_0_n_54 ;
wire \WR.aw_channel_0_n_55 ;
wire \WR.aw_channel_0_n_56 ;
wire \WR.aw_channel_0_n_57 ;
wire \WR.aw_channel_0_n_7 ;
wire \WR.aw_channel_0_n_9 ;
wire \WR.b_channel_0_n_1 ;
wire \WR.b_channel_0_n_2 ;
wire aclk;
wire [1:0]\ar_cmd_fsm_0/state ;
wire \ar_pipe/p_1_in ;
wire areset_d1;
wire areset_d1_i_1_n_0;
wire aresetn;
wire [1:0]\aw_cmd_fsm_0/state ;
wire \aw_pipe/p_1_in ;
wire [11:0]b_awid;
wire [7:0]b_awlen;
wire b_push;
wire [3:0]\cmd_translator_0/incr_cmd_0/axaddr_incr_reg ;
wire [3:0]\cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5 ;
wire \cmd_translator_0/incr_cmd_0/sel_first ;
wire \cmd_translator_0/incr_cmd_0/sel_first_4 ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/axaddr_offset ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/axaddr_offset_r ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2 ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/wrap_second_len ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/wrap_second_len_r ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3 ;
wire [33:0]in;
wire [11:0]m_axi_araddr;
wire [22:0]\m_axi_arprot[2] ;
wire m_axi_arready;
wire m_axi_arvalid;
wire [11:0]m_axi_awaddr;
wire m_axi_awready;
wire m_axi_awvalid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire m_axi_rready;
wire m_axi_rvalid;
wire r_rlast;
wire [11:0]s_arid;
wire [11:0]s_arid_r;
wire [11:0]s_awid;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [1:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [1:0]s_axi_awsize;
wire s_axi_awvalid;
wire [13:0]\s_axi_bid[11] ;
wire s_axi_bready;
wire s_axi_bvalid;
wire [46:0]\s_axi_rid[11] ;
wire s_axi_rready;
wire s_axi_rvalid;
wire [11:0]si_rs_araddr;
wire [1:1]si_rs_arburst;
wire [3:0]si_rs_arlen;
wire [1:0]si_rs_arsize;
wire si_rs_arvalid;
wire [11:0]si_rs_awaddr;
wire [1:1]si_rs_awburst;
wire [3:0]si_rs_awlen;
wire [1:0]si_rs_awsize;
wire si_rs_awvalid;
wire [11:0]si_rs_bid;
wire si_rs_bready;
wire [1:0]si_rs_bresp;
wire si_rs_bvalid;
wire [31:0]si_rs_rdata;
wire [11:0]si_rs_rid;
wire si_rs_rlast;
wire si_rs_rready;
wire [1:0]si_rs_rresp;
wire [3:0]wrap_cnt;
zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_ar_channel \RD.ar_channel_0
(.CO(SI_REG_n_147),
.D({\cmd_translator_0/wrap_cmd_0/wrap_second_len [3:2],\cmd_translator_0/wrap_cmd_0/wrap_second_len [0]}),
.E(\ar_pipe/p_1_in ),
.O({SI_REG_n_148,SI_REG_n_149,SI_REG_n_150,SI_REG_n_151}),
.Q(\ar_cmd_fsm_0/state ),
.S({\RD.ar_channel_0_n_47 ,\RD.ar_channel_0_n_48 ,\RD.ar_channel_0_n_49 ,\RD.ar_channel_0_n_50 }),
.aclk(aclk),
.areset_d1(areset_d1),
.\axaddr_incr_reg[3] (\cmd_translator_0/incr_cmd_0/axaddr_incr_reg ),
.axaddr_offset(\cmd_translator_0/wrap_cmd_0/axaddr_offset [2:0]),
.\axaddr_offset_r_reg[3] (\cmd_translator_0/wrap_cmd_0/axaddr_offset [3]),
.\axaddr_offset_r_reg[3]_0 (\cmd_translator_0/wrap_cmd_0/axaddr_offset_r ),
.\cnt_read_reg[2]_rep__0 (\RD.r_channel_0_n_0 ),
.m_axi_araddr(m_axi_araddr),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.\m_payload_i_reg[0] (\RD.ar_channel_0_n_9 ),
.\m_payload_i_reg[0]_0 (\RD.ar_channel_0_n_10 ),
.\m_payload_i_reg[11] ({SI_REG_n_143,SI_REG_n_144,SI_REG_n_145,SI_REG_n_146}),
.\m_payload_i_reg[38] (SI_REG_n_196),
.\m_payload_i_reg[3] ({SI_REG_n_139,SI_REG_n_140,SI_REG_n_141,SI_REG_n_142}),
.\m_payload_i_reg[44] (SI_REG_n_171),
.\m_payload_i_reg[46] (SI_REG_n_177),
.\m_payload_i_reg[47] (SI_REG_n_175),
.\m_payload_i_reg[51] (SI_REG_n_176),
.\m_payload_i_reg[64] ({s_arid,SI_REG_n_79,SI_REG_n_80,SI_REG_n_81,SI_REG_n_82,si_rs_arlen,si_rs_arburst,SI_REG_n_88,si_rs_arsize,si_rs_araddr}),
.\m_payload_i_reg[6] (SI_REG_n_187),
.\m_payload_i_reg[6]_0 ({SI_REG_n_188,SI_REG_n_189,SI_REG_n_190,SI_REG_n_191,SI_REG_n_192,SI_REG_n_193,SI_REG_n_194}),
.\r_arid_r_reg[11] (s_arid_r),
.r_push_r_reg(\RD.ar_channel_0_n_11 ),
.r_rlast(r_rlast),
.sel_first(\cmd_translator_0/incr_cmd_0/sel_first ),
.si_rs_arvalid(si_rs_arvalid),
.\wrap_boundary_axaddr_r_reg[11] (\RD.ar_channel_0_n_8 ),
.wrap_second_len(\cmd_translator_0/wrap_cmd_0/wrap_second_len [1]),
.\wrap_second_len_r_reg[3] ({\cmd_translator_0/wrap_cmd_0/wrap_second_len_r [3:2],\cmd_translator_0/wrap_cmd_0/wrap_second_len_r [0]}),
.\wrap_second_len_r_reg[3]_0 ({SI_REG_n_165,SI_REG_n_166,SI_REG_n_167}));
zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_r_channel \RD.r_channel_0
(.D(s_arid_r),
.aclk(aclk),
.areset_d1(areset_d1),
.in(in),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.m_valid_i_reg(\RD.r_channel_0_n_2 ),
.out({si_rs_rresp,si_rs_rdata}),
.r_rlast(r_rlast),
.s_ready_i_reg(SI_REG_n_178),
.si_rs_rready(si_rs_rready),
.\skid_buffer_reg[46] ({si_rs_rid,si_rs_rlast}),
.\state_reg[1]_rep (\RD.r_channel_0_n_0 ),
.\state_reg[1]_rep_0 (\RD.ar_channel_0_n_11 ));
zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axi_register_slice SI_REG
(.CO(SI_REG_n_134),
.D({wrap_cnt[3:2],wrap_cnt[0]}),
.E(\aw_pipe/p_1_in ),
.O({SI_REG_n_135,SI_REG_n_136,SI_REG_n_137,SI_REG_n_138}),
.Q({s_awid,SI_REG_n_20,SI_REG_n_21,SI_REG_n_22,SI_REG_n_23,si_rs_awlen,si_rs_awburst,SI_REG_n_29,si_rs_awsize,Q,si_rs_awaddr}),
.S({\WR.aw_channel_0_n_54 ,\WR.aw_channel_0_n_55 ,\WR.aw_channel_0_n_56 ,\WR.aw_channel_0_n_57 }),
.aclk(aclk),
.aresetn(aresetn),
.axaddr_incr_reg(\cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5 ),
.\axaddr_incr_reg[11] (C),
.\axaddr_incr_reg[11]_0 ({SI_REG_n_143,SI_REG_n_144,SI_REG_n_145,SI_REG_n_146}),
.\axaddr_incr_reg[3] ({SI_REG_n_148,SI_REG_n_149,SI_REG_n_150,SI_REG_n_151}),
.\axaddr_incr_reg[3]_0 (\cmd_translator_0/incr_cmd_0/axaddr_incr_reg ),
.\axaddr_incr_reg[7] ({SI_REG_n_139,SI_REG_n_140,SI_REG_n_141,SI_REG_n_142}),
.\axaddr_incr_reg[7]_0 (SI_REG_n_147),
.axaddr_offset(\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 [2:0]),
.axaddr_offset_0(\cmd_translator_0/wrap_cmd_0/axaddr_offset [2:0]),
.\axaddr_offset_r_reg[3] (SI_REG_n_179),
.\axaddr_offset_r_reg[3]_0 (SI_REG_n_187),
.\axaddr_offset_r_reg[3]_1 (\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 [3]),
.\axaddr_offset_r_reg[3]_2 (\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2 ),
.\axaddr_offset_r_reg[3]_3 (\cmd_translator_0/wrap_cmd_0/axaddr_offset [3]),
.\axaddr_offset_r_reg[3]_4 (\cmd_translator_0/wrap_cmd_0/axaddr_offset_r ),
.\axlen_cnt_reg[3] (SI_REG_n_162),
.\axlen_cnt_reg[3]_0 (SI_REG_n_175),
.b_push(b_push),
.\cnt_read_reg[3]_rep__0 (SI_REG_n_178),
.\cnt_read_reg[4] ({si_rs_rresp,si_rs_rdata}),
.\cnt_read_reg[4]_rep__0 (\RD.r_channel_0_n_2 ),
.\m_axi_araddr[10] (SI_REG_n_196),
.\m_axi_awaddr[10] (SI_REG_n_195),
.\m_payload_i_reg[3] ({\RD.ar_channel_0_n_47 ,\RD.ar_channel_0_n_48 ,\RD.ar_channel_0_n_49 ,\RD.ar_channel_0_n_50 }),
.m_valid_i_reg(\ar_pipe/p_1_in ),
.next_pending_r_reg(SI_REG_n_163),
.next_pending_r_reg_0(SI_REG_n_164),
.next_pending_r_reg_1(SI_REG_n_176),
.next_pending_r_reg_2(SI_REG_n_177),
.out(si_rs_bid),
.r_push_r_reg({si_rs_rid,si_rs_rlast}),
.\s_arid_r_reg[11] ({s_arid,SI_REG_n_79,SI_REG_n_80,SI_REG_n_81,SI_REG_n_82,si_rs_arlen,si_rs_arburst,SI_REG_n_88,si_rs_arsize,\m_axi_arprot[2] ,si_rs_araddr}),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize),
.s_axi_awvalid(s_axi_awvalid),
.\s_axi_bid[11] (\s_axi_bid[11] ),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.\s_axi_rid[11] (\s_axi_rid[11] ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.\s_bresp_acc_reg[1] (si_rs_bresp),
.sel_first(\cmd_translator_0/incr_cmd_0/sel_first_4 ),
.sel_first_2(\cmd_translator_0/incr_cmd_0/sel_first ),
.si_rs_arvalid(si_rs_arvalid),
.si_rs_awvalid(si_rs_awvalid),
.si_rs_bready(si_rs_bready),
.si_rs_bvalid(si_rs_bvalid),
.si_rs_rready(si_rs_rready),
.\state_reg[0]_rep (\WR.aw_channel_0_n_10 ),
.\state_reg[0]_rep_0 (\RD.ar_channel_0_n_9 ),
.\state_reg[1] (\ar_cmd_fsm_0/state ),
.\state_reg[1]_0 (\aw_cmd_fsm_0/state ),
.\state_reg[1]_rep (\WR.aw_channel_0_n_9 ),
.\state_reg[1]_rep_0 (\WR.aw_channel_0_n_7 ),
.\state_reg[1]_rep_1 (\RD.ar_channel_0_n_8 ),
.\state_reg[1]_rep_2 (\RD.ar_channel_0_n_10 ),
.\wrap_boundary_axaddr_r_reg[6] ({SI_REG_n_180,SI_REG_n_181,SI_REG_n_182,SI_REG_n_183,SI_REG_n_184,SI_REG_n_185,SI_REG_n_186}),
.\wrap_boundary_axaddr_r_reg[6]_0 ({SI_REG_n_188,SI_REG_n_189,SI_REG_n_190,SI_REG_n_191,SI_REG_n_192,SI_REG_n_193,SI_REG_n_194}),
.\wrap_cnt_r_reg[3] (SI_REG_n_158),
.\wrap_cnt_r_reg[3]_0 ({SI_REG_n_165,SI_REG_n_166,SI_REG_n_167}),
.\wrap_cnt_r_reg[3]_1 (SI_REG_n_171),
.wrap_second_len(\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 [1]),
.wrap_second_len_1(\cmd_translator_0/wrap_cmd_0/wrap_second_len [1]),
.\wrap_second_len_r_reg[3] ({\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 [3:2],\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 [0]}),
.\wrap_second_len_r_reg[3]_0 ({\cmd_translator_0/wrap_cmd_0/wrap_second_len [3:2],\cmd_translator_0/wrap_cmd_0/wrap_second_len [0]}),
.\wrap_second_len_r_reg[3]_1 ({\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3 [3:2],\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3 [0]}),
.\wrap_second_len_r_reg[3]_2 ({\cmd_translator_0/wrap_cmd_0/wrap_second_len_r [3:2],\cmd_translator_0/wrap_cmd_0/wrap_second_len_r [0]}));
zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_aw_channel \WR.aw_channel_0
(.CO(SI_REG_n_134),
.D(\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 [1]),
.E(\aw_pipe/p_1_in ),
.O({SI_REG_n_135,SI_REG_n_136,SI_REG_n_137,SI_REG_n_138}),
.Q(\aw_cmd_fsm_0/state ),
.S({\WR.aw_channel_0_n_54 ,\WR.aw_channel_0_n_55 ,\WR.aw_channel_0_n_56 ,\WR.aw_channel_0_n_57 }),
.aclk(aclk),
.areset_d1(areset_d1),
.\axaddr_incr_reg[3] (\cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5 ),
.\axaddr_offset_r_reg[3] (\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 [3]),
.\axaddr_offset_r_reg[3]_0 (\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2 ),
.b_push(b_push),
.\cnt_read_reg[0]_rep__0 (\WR.b_channel_0_n_1 ),
.\cnt_read_reg[1]_rep__1 (\WR.b_channel_0_n_2 ),
.in({b_awid,b_awlen}),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.\m_payload_i_reg[11] (C),
.\m_payload_i_reg[35] (\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 [2:0]),
.\m_payload_i_reg[38] (SI_REG_n_195),
.\m_payload_i_reg[44] (SI_REG_n_158),
.\m_payload_i_reg[46] (SI_REG_n_164),
.\m_payload_i_reg[47] (SI_REG_n_162),
.\m_payload_i_reg[48] (SI_REG_n_163),
.\m_payload_i_reg[64] ({s_awid,SI_REG_n_20,SI_REG_n_21,SI_REG_n_22,SI_REG_n_23,si_rs_awlen,si_rs_awburst,SI_REG_n_29,si_rs_awsize,si_rs_awaddr}),
.\m_payload_i_reg[6] (SI_REG_n_179),
.\m_payload_i_reg[6]_0 ({SI_REG_n_180,SI_REG_n_181,SI_REG_n_182,SI_REG_n_183,SI_REG_n_184,SI_REG_n_185,SI_REG_n_186}),
.sel_first(\cmd_translator_0/incr_cmd_0/sel_first_4 ),
.si_rs_awvalid(si_rs_awvalid),
.\state_reg[1]_rep (\WR.aw_channel_0_n_9 ),
.\state_reg[1]_rep_0 (\WR.aw_channel_0_n_10 ),
.\wrap_boundary_axaddr_r_reg[11] (\WR.aw_channel_0_n_7 ),
.\wrap_second_len_r_reg[3] ({\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3 [3:2],\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3 [0]}),
.\wrap_second_len_r_reg[3]_0 ({\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 [3:2],\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 [0]}),
.\wrap_second_len_r_reg[3]_1 ({wrap_cnt[3:2],wrap_cnt[0]}));
zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_b_channel \WR.b_channel_0
(.aclk(aclk),
.areset_d1(areset_d1),
.b_push(b_push),
.\cnt_read_reg[0]_rep__0 (\WR.b_channel_0_n_1 ),
.\cnt_read_reg[1]_rep__1 (\WR.b_channel_0_n_2 ),
.in({b_awid,b_awlen}),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.out(si_rs_bid),
.si_rs_bready(si_rs_bready),
.si_rs_bvalid(si_rs_bvalid),
.\skid_buffer_reg[1] (si_rs_bresp));
LUT1 #(
.INIT(2'h1))
areset_d1_i_1
(.I0(aresetn),
.O(areset_d1_i_1_n_0));
FDRE #(
.INIT(1'b0))
areset_d1_reg
(.C(aclk),
.CE(1'b1),
.D(areset_d1_i_1_n_0),
.Q(areset_d1),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_ar_channel" *)
module zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_ar_channel
(\axaddr_incr_reg[3] ,
sel_first,
Q,
wrap_second_len,
\wrap_boundary_axaddr_r_reg[11] ,
\m_payload_i_reg[0] ,
\m_payload_i_reg[0]_0 ,
r_push_r_reg,
\wrap_second_len_r_reg[3] ,
\axaddr_offset_r_reg[3] ,
\axaddr_offset_r_reg[3]_0 ,
m_axi_arvalid,
r_rlast,
E,
m_axi_araddr,
\r_arid_r_reg[11] ,
S,
aclk,
O,
\m_payload_i_reg[47] ,
si_rs_arvalid,
\m_payload_i_reg[44] ,
\m_payload_i_reg[64] ,
m_axi_arready,
CO,
\cnt_read_reg[2]_rep__0 ,
axaddr_offset,
\m_payload_i_reg[46] ,
\m_payload_i_reg[51] ,
areset_d1,
\m_payload_i_reg[6] ,
\m_payload_i_reg[3] ,
\m_payload_i_reg[11] ,
\m_payload_i_reg[38] ,
D,
\wrap_second_len_r_reg[3]_0 ,
\m_payload_i_reg[6]_0 );
output [3:0]\axaddr_incr_reg[3] ;
output sel_first;
output [1:0]Q;
output [0:0]wrap_second_len;
output \wrap_boundary_axaddr_r_reg[11] ;
output \m_payload_i_reg[0] ;
output \m_payload_i_reg[0]_0 ;
output r_push_r_reg;
output [2:0]\wrap_second_len_r_reg[3] ;
output [0:0]\axaddr_offset_r_reg[3] ;
output [3:0]\axaddr_offset_r_reg[3]_0 ;
output m_axi_arvalid;
output r_rlast;
output [0:0]E;
output [11:0]m_axi_araddr;
output [11:0]\r_arid_r_reg[11] ;
output [3:0]S;
input aclk;
input [3:0]O;
input \m_payload_i_reg[47] ;
input si_rs_arvalid;
input \m_payload_i_reg[44] ;
input [35:0]\m_payload_i_reg[64] ;
input m_axi_arready;
input [0:0]CO;
input \cnt_read_reg[2]_rep__0 ;
input [2:0]axaddr_offset;
input \m_payload_i_reg[46] ;
input \m_payload_i_reg[51] ;
input areset_d1;
input \m_payload_i_reg[6] ;
input [3:0]\m_payload_i_reg[3] ;
input [3:0]\m_payload_i_reg[11] ;
input \m_payload_i_reg[38] ;
input [2:0]D;
input [2:0]\wrap_second_len_r_reg[3]_0 ;
input [6:0]\m_payload_i_reg[6]_0 ;
wire [0:0]CO;
wire [2:0]D;
wire [0:0]E;
wire [3:0]O;
wire [1:0]Q;
wire [3:0]S;
wire aclk;
wire ar_cmd_fsm_0_n_0;
wire ar_cmd_fsm_0_n_12;
wire ar_cmd_fsm_0_n_15;
wire ar_cmd_fsm_0_n_16;
wire ar_cmd_fsm_0_n_17;
wire ar_cmd_fsm_0_n_20;
wire ar_cmd_fsm_0_n_21;
wire ar_cmd_fsm_0_n_3;
wire ar_cmd_fsm_0_n_8;
wire ar_cmd_fsm_0_n_9;
wire areset_d1;
wire [3:0]\axaddr_incr_reg[3] ;
wire [2:0]axaddr_offset;
wire [0:0]\axaddr_offset_r_reg[3] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire cmd_translator_0_n_0;
wire cmd_translator_0_n_10;
wire cmd_translator_0_n_11;
wire cmd_translator_0_n_13;
wire cmd_translator_0_n_2;
wire cmd_translator_0_n_8;
wire cmd_translator_0_n_9;
wire \cnt_read_reg[2]_rep__0 ;
wire incr_next_pending;
wire [11:0]m_axi_araddr;
wire m_axi_arready;
wire m_axi_arvalid;
wire \m_payload_i_reg[0] ;
wire \m_payload_i_reg[0]_0 ;
wire [3:0]\m_payload_i_reg[11] ;
wire \m_payload_i_reg[38] ;
wire [3:0]\m_payload_i_reg[3] ;
wire \m_payload_i_reg[44] ;
wire \m_payload_i_reg[46] ;
wire \m_payload_i_reg[47] ;
wire \m_payload_i_reg[51] ;
wire [35:0]\m_payload_i_reg[64] ;
wire \m_payload_i_reg[6] ;
wire [6:0]\m_payload_i_reg[6]_0 ;
wire [11:0]\r_arid_r_reg[11] ;
wire r_push_r_reg;
wire r_rlast;
wire sel_first;
wire sel_first_i;
wire si_rs_arvalid;
wire \wrap_boundary_axaddr_r_reg[11] ;
wire [1:1]\wrap_cmd_0/wrap_second_len_r ;
wire wrap_next_pending;
wire [0:0]wrap_second_len;
wire [2:0]\wrap_second_len_r_reg[3] ;
wire [2:0]\wrap_second_len_r_reg[3]_0 ;
zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm ar_cmd_fsm_0
(.D(ar_cmd_fsm_0_n_3),
.E(\wrap_boundary_axaddr_r_reg[11] ),
.Q(Q),
.aclk(aclk),
.areset_d1(areset_d1),
.\axaddr_incr_reg[11] (ar_cmd_fsm_0_n_17),
.axaddr_offset(axaddr_offset),
.\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3] ),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3]_0 [3]),
.\axaddr_wrap_reg[11] (ar_cmd_fsm_0_n_16),
.\axlen_cnt_reg[1] (ar_cmd_fsm_0_n_0),
.\axlen_cnt_reg[1]_0 ({ar_cmd_fsm_0_n_8,ar_cmd_fsm_0_n_9}),
.\axlen_cnt_reg[1]_1 ({cmd_translator_0_n_9,cmd_translator_0_n_10}),
.\axlen_cnt_reg[4] (cmd_translator_0_n_11),
.\cnt_read_reg[2]_rep__0 (\cnt_read_reg[2]_rep__0 ),
.incr_next_pending(incr_next_pending),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.\m_payload_i_reg[0] (\m_payload_i_reg[0]_0 ),
.\m_payload_i_reg[0]_0 (\m_payload_i_reg[0] ),
.\m_payload_i_reg[0]_1 (E),
.\m_payload_i_reg[44] (\m_payload_i_reg[44] ),
.\m_payload_i_reg[47] ({\m_payload_i_reg[64] [19],\m_payload_i_reg[64] [17:15]}),
.\m_payload_i_reg[51] (\m_payload_i_reg[51] ),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.next_pending_r_reg(cmd_translator_0_n_0),
.r_push_r_reg(r_push_r_reg),
.s_axburst_eq0_reg(ar_cmd_fsm_0_n_12),
.s_axburst_eq1_reg(ar_cmd_fsm_0_n_15),
.s_axburst_eq1_reg_0(cmd_translator_0_n_13),
.sel_first_i(sel_first_i),
.sel_first_reg(ar_cmd_fsm_0_n_20),
.sel_first_reg_0(ar_cmd_fsm_0_n_21),
.sel_first_reg_1(cmd_translator_0_n_2),
.sel_first_reg_2(sel_first),
.sel_first_reg_3(cmd_translator_0_n_8),
.si_rs_arvalid(si_rs_arvalid),
.wrap_next_pending(wrap_next_pending),
.wrap_second_len(wrap_second_len),
.\wrap_second_len_r_reg[1] (\wrap_cmd_0/wrap_second_len_r ));
zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 cmd_translator_0
(.CO(CO),
.D({ar_cmd_fsm_0_n_8,ar_cmd_fsm_0_n_9}),
.E(\wrap_boundary_axaddr_r_reg[11] ),
.O(O),
.Q({cmd_translator_0_n_9,cmd_translator_0_n_10}),
.S(S),
.aclk(aclk),
.\axaddr_incr_reg[11] (sel_first),
.\axaddr_incr_reg[3] (\axaddr_incr_reg[3] ),
.\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3]_0 ),
.\axaddr_offset_r_reg[3]_0 ({\axaddr_offset_r_reg[3] ,axaddr_offset}),
.incr_next_pending(incr_next_pending),
.m_axi_araddr(m_axi_araddr),
.m_axi_arready(m_axi_arready),
.\m_payload_i_reg[11] (\m_payload_i_reg[11] ),
.\m_payload_i_reg[38] (\m_payload_i_reg[38] ),
.\m_payload_i_reg[39] (ar_cmd_fsm_0_n_12),
.\m_payload_i_reg[39]_0 (ar_cmd_fsm_0_n_15),
.\m_payload_i_reg[3] (\m_payload_i_reg[3] ),
.\m_payload_i_reg[46] (\m_payload_i_reg[46] ),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.\m_payload_i_reg[51] (\m_payload_i_reg[64] [23:0]),
.\m_payload_i_reg[6] (\m_payload_i_reg[6]_0 ),
.m_valid_i_reg(ar_cmd_fsm_0_n_16),
.next_pending_r_reg(cmd_translator_0_n_0),
.next_pending_r_reg_0(cmd_translator_0_n_11),
.r_rlast(r_rlast),
.sel_first_i(sel_first_i),
.sel_first_reg_0(cmd_translator_0_n_2),
.sel_first_reg_1(cmd_translator_0_n_8),
.sel_first_reg_2(ar_cmd_fsm_0_n_17),
.sel_first_reg_3(ar_cmd_fsm_0_n_20),
.sel_first_reg_4(ar_cmd_fsm_0_n_21),
.si_rs_arvalid(si_rs_arvalid),
.\state_reg[0] (ar_cmd_fsm_0_n_0),
.\state_reg[0]_rep (cmd_translator_0_n_13),
.\state_reg[0]_rep_0 (\m_payload_i_reg[0] ),
.\state_reg[1] (Q),
.\state_reg[1]_rep (\m_payload_i_reg[0]_0 ),
.\state_reg[1]_rep_0 (r_push_r_reg),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[3] ({\wrap_second_len_r_reg[3] [2:1],\wrap_cmd_0/wrap_second_len_r ,\wrap_second_len_r_reg[3] [0]}),
.\wrap_second_len_r_reg[3]_0 ({D[2:1],wrap_second_len,D[0]}),
.\wrap_second_len_r_reg[3]_1 ({\wrap_second_len_r_reg[3]_0 [2:1],ar_cmd_fsm_0_n_3,\wrap_second_len_r_reg[3]_0 [0]}));
FDRE \s_arid_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [24]),
.Q(\r_arid_r_reg[11] [0]),
.R(1'b0));
FDRE \s_arid_r_reg[10]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [34]),
.Q(\r_arid_r_reg[11] [10]),
.R(1'b0));
FDRE \s_arid_r_reg[11]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [35]),
.Q(\r_arid_r_reg[11] [11]),
.R(1'b0));
FDRE \s_arid_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [25]),
.Q(\r_arid_r_reg[11] [1]),
.R(1'b0));
FDRE \s_arid_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [26]),
.Q(\r_arid_r_reg[11] [2]),
.R(1'b0));
FDRE \s_arid_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [27]),
.Q(\r_arid_r_reg[11] [3]),
.R(1'b0));
FDRE \s_arid_r_reg[4]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [28]),
.Q(\r_arid_r_reg[11] [4]),
.R(1'b0));
FDRE \s_arid_r_reg[5]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [29]),
.Q(\r_arid_r_reg[11] [5]),
.R(1'b0));
FDRE \s_arid_r_reg[6]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [30]),
.Q(\r_arid_r_reg[11] [6]),
.R(1'b0));
FDRE \s_arid_r_reg[7]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [31]),
.Q(\r_arid_r_reg[11] [7]),
.R(1'b0));
FDRE \s_arid_r_reg[8]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [32]),
.Q(\r_arid_r_reg[11] [8]),
.R(1'b0));
FDRE \s_arid_r_reg[9]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [33]),
.Q(\r_arid_r_reg[11] [9]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_aw_channel" *)
module zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_aw_channel
(\axaddr_incr_reg[3] ,
sel_first,
Q,
\wrap_boundary_axaddr_r_reg[11] ,
D,
\state_reg[1]_rep ,
\state_reg[1]_rep_0 ,
\wrap_second_len_r_reg[3] ,
\axaddr_offset_r_reg[3] ,
b_push,
\axaddr_offset_r_reg[3]_0 ,
E,
m_axi_awvalid,
m_axi_awaddr,
in,
S,
aclk,
O,
\m_payload_i_reg[47] ,
si_rs_awvalid,
\m_payload_i_reg[64] ,
\m_payload_i_reg[44] ,
\cnt_read_reg[1]_rep__1 ,
\cnt_read_reg[0]_rep__0 ,
m_axi_awready,
CO,
\m_payload_i_reg[35] ,
\m_payload_i_reg[48] ,
areset_d1,
\m_payload_i_reg[46] ,
\m_payload_i_reg[6] ,
\m_payload_i_reg[11] ,
\m_payload_i_reg[38] ,
\wrap_second_len_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_1 ,
\m_payload_i_reg[6]_0 );
output [3:0]\axaddr_incr_reg[3] ;
output sel_first;
output [1:0]Q;
output \wrap_boundary_axaddr_r_reg[11] ;
output [0:0]D;
output \state_reg[1]_rep ;
output \state_reg[1]_rep_0 ;
output [2:0]\wrap_second_len_r_reg[3] ;
output [0:0]\axaddr_offset_r_reg[3] ;
output b_push;
output [3:0]\axaddr_offset_r_reg[3]_0 ;
output [0:0]E;
output m_axi_awvalid;
output [11:0]m_axi_awaddr;
output [19:0]in;
output [3:0]S;
input aclk;
input [3:0]O;
input \m_payload_i_reg[47] ;
input si_rs_awvalid;
input [35:0]\m_payload_i_reg[64] ;
input \m_payload_i_reg[44] ;
input \cnt_read_reg[1]_rep__1 ;
input \cnt_read_reg[0]_rep__0 ;
input m_axi_awready;
input [0:0]CO;
input [2:0]\m_payload_i_reg[35] ;
input \m_payload_i_reg[48] ;
input areset_d1;
input \m_payload_i_reg[46] ;
input \m_payload_i_reg[6] ;
input [7:0]\m_payload_i_reg[11] ;
input \m_payload_i_reg[38] ;
input [2:0]\wrap_second_len_r_reg[3]_0 ;
input [2:0]\wrap_second_len_r_reg[3]_1 ;
input [6:0]\m_payload_i_reg[6]_0 ;
wire [0:0]CO;
wire [0:0]D;
wire [0:0]E;
wire [3:0]O;
wire [1:0]Q;
wire [3:0]S;
wire aclk;
wire areset_d1;
wire aw_cmd_fsm_0_n_0;
wire aw_cmd_fsm_0_n_13;
wire aw_cmd_fsm_0_n_17;
wire aw_cmd_fsm_0_n_20;
wire aw_cmd_fsm_0_n_21;
wire aw_cmd_fsm_0_n_24;
wire aw_cmd_fsm_0_n_25;
wire aw_cmd_fsm_0_n_3;
wire [3:0]\axaddr_incr_reg[3] ;
wire [0:0]\axaddr_offset_r_reg[3] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire b_push;
wire cmd_translator_0_n_0;
wire cmd_translator_0_n_1;
wire cmd_translator_0_n_10;
wire cmd_translator_0_n_11;
wire cmd_translator_0_n_12;
wire cmd_translator_0_n_13;
wire cmd_translator_0_n_14;
wire cmd_translator_0_n_15;
wire cmd_translator_0_n_16;
wire cmd_translator_0_n_17;
wire cmd_translator_0_n_2;
wire cmd_translator_0_n_9;
wire \cnt_read_reg[0]_rep__0 ;
wire \cnt_read_reg[1]_rep__1 ;
wire [19:0]in;
wire incr_next_pending;
wire [11:0]m_axi_awaddr;
wire m_axi_awready;
wire m_axi_awvalid;
wire [7:0]\m_payload_i_reg[11] ;
wire [2:0]\m_payload_i_reg[35] ;
wire \m_payload_i_reg[38] ;
wire \m_payload_i_reg[44] ;
wire \m_payload_i_reg[46] ;
wire \m_payload_i_reg[47] ;
wire \m_payload_i_reg[48] ;
wire [35:0]\m_payload_i_reg[64] ;
wire \m_payload_i_reg[6] ;
wire [6:0]\m_payload_i_reg[6]_0 ;
wire next;
wire [5:0]p_1_in;
wire sel_first;
wire sel_first__0;
wire sel_first_i;
wire si_rs_awvalid;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire \wrap_boundary_axaddr_r_reg[11] ;
wire [1:1]\wrap_cmd_0/wrap_second_len_r ;
wire wrap_next_pending;
wire [2:0]\wrap_second_len_r_reg[3] ;
wire [2:0]\wrap_second_len_r_reg[3]_0 ;
wire [2:0]\wrap_second_len_r_reg[3]_1 ;
zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm aw_cmd_fsm_0
(.D(aw_cmd_fsm_0_n_3),
.E(\wrap_boundary_axaddr_r_reg[11] ),
.Q(Q),
.aclk(aclk),
.areset_d1(areset_d1),
.\axaddr_incr_reg[11] (aw_cmd_fsm_0_n_21),
.\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3] ),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3]_0 [3]),
.\axaddr_wrap_reg[0] (aw_cmd_fsm_0_n_20),
.\axlen_cnt_reg[2] (cmd_translator_0_n_16),
.\axlen_cnt_reg[3] (cmd_translator_0_n_15),
.\axlen_cnt_reg[3]_0 (cmd_translator_0_n_17),
.\axlen_cnt_reg[4] (aw_cmd_fsm_0_n_0),
.\axlen_cnt_reg[4]_0 (cmd_translator_0_n_13),
.\axlen_cnt_reg[5] ({p_1_in[5:4],p_1_in[1:0]}),
.\axlen_cnt_reg[5]_0 ({cmd_translator_0_n_9,cmd_translator_0_n_10,cmd_translator_0_n_11,cmd_translator_0_n_12}),
.\cnt_read_reg[0]_rep__0 (\cnt_read_reg[0]_rep__0 ),
.\cnt_read_reg[1]_rep__1 (\cnt_read_reg[1]_rep__1 ),
.incr_next_pending(incr_next_pending),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.\m_payload_i_reg[0] (b_push),
.\m_payload_i_reg[0]_0 (E),
.\m_payload_i_reg[35] (\m_payload_i_reg[35] ),
.\m_payload_i_reg[44] (\m_payload_i_reg[44] ),
.\m_payload_i_reg[46] (\m_payload_i_reg[46] ),
.\m_payload_i_reg[48] (\m_payload_i_reg[48] ),
.\m_payload_i_reg[49] ({\m_payload_i_reg[64] [21:19],\m_payload_i_reg[64] [17:15]}),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.next(next),
.next_pending_r_reg(cmd_translator_0_n_0),
.next_pending_r_reg_0(cmd_translator_0_n_1),
.s_axburst_eq0_reg(aw_cmd_fsm_0_n_13),
.s_axburst_eq1_reg(aw_cmd_fsm_0_n_17),
.s_axburst_eq1_reg_0(cmd_translator_0_n_14),
.sel_first__0(sel_first__0),
.sel_first_i(sel_first_i),
.sel_first_reg(aw_cmd_fsm_0_n_24),
.sel_first_reg_0(aw_cmd_fsm_0_n_25),
.sel_first_reg_1(cmd_translator_0_n_2),
.sel_first_reg_2(sel_first),
.si_rs_awvalid(si_rs_awvalid),
.\state_reg[1]_rep_0 (\state_reg[1]_rep ),
.\state_reg[1]_rep_1 (\state_reg[1]_rep_0 ),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[1] (D),
.\wrap_second_len_r_reg[1]_0 (\wrap_cmd_0/wrap_second_len_r ));
zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator cmd_translator_0
(.CO(CO),
.D({p_1_in[5:4],p_1_in[1:0]}),
.E(\wrap_boundary_axaddr_r_reg[11] ),
.O(O),
.Q({cmd_translator_0_n_9,cmd_translator_0_n_10,cmd_translator_0_n_11,cmd_translator_0_n_12}),
.S(S),
.aclk(aclk),
.\axaddr_incr_reg[11] (sel_first),
.\axaddr_incr_reg[3] (\axaddr_incr_reg[3] ),
.\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3]_0 ),
.\axaddr_offset_r_reg[3]_0 ({\axaddr_offset_r_reg[3] ,\m_payload_i_reg[35] }),
.\axlen_cnt_reg[4] (cmd_translator_0_n_17),
.\axlen_cnt_reg[7] (cmd_translator_0_n_13),
.incr_next_pending(incr_next_pending),
.m_axi_awaddr(m_axi_awaddr),
.\m_payload_i_reg[11] (\m_payload_i_reg[11] ),
.\m_payload_i_reg[38] (\m_payload_i_reg[38] ),
.\m_payload_i_reg[39] (aw_cmd_fsm_0_n_13),
.\m_payload_i_reg[39]_0 (aw_cmd_fsm_0_n_17),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.\m_payload_i_reg[51] ({\m_payload_i_reg[64] [23:22],\m_payload_i_reg[64] [19:0]}),
.\m_payload_i_reg[6] (\m_payload_i_reg[6]_0 ),
.m_valid_i_reg(aw_cmd_fsm_0_n_20),
.next(next),
.next_pending_r_reg(cmd_translator_0_n_0),
.next_pending_r_reg_0(cmd_translator_0_n_1),
.next_pending_r_reg_1(cmd_translator_0_n_15),
.next_pending_r_reg_2(cmd_translator_0_n_16),
.sel_first__0(sel_first__0),
.sel_first_i(sel_first_i),
.sel_first_reg_0(cmd_translator_0_n_2),
.sel_first_reg_1(aw_cmd_fsm_0_n_21),
.sel_first_reg_2(aw_cmd_fsm_0_n_24),
.sel_first_reg_3(aw_cmd_fsm_0_n_25),
.\state_reg[0] (aw_cmd_fsm_0_n_0),
.\state_reg[0]_rep (b_push),
.\state_reg[1] (Q),
.\state_reg[1]_rep (cmd_translator_0_n_14),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[3] ({\wrap_second_len_r_reg[3] [2:1],\wrap_cmd_0/wrap_second_len_r ,\wrap_second_len_r_reg[3] [0]}),
.\wrap_second_len_r_reg[3]_0 ({\wrap_second_len_r_reg[3]_0 [2:1],D,\wrap_second_len_r_reg[3]_0 [0]}),
.\wrap_second_len_r_reg[3]_1 ({\wrap_second_len_r_reg[3]_1 [2:1],aw_cmd_fsm_0_n_3,\wrap_second_len_r_reg[3]_1 [0]}));
FDRE \s_awid_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [24]),
.Q(in[8]),
.R(1'b0));
FDRE \s_awid_r_reg[10]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [34]),
.Q(in[18]),
.R(1'b0));
FDRE \s_awid_r_reg[11]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [35]),
.Q(in[19]),
.R(1'b0));
FDRE \s_awid_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [25]),
.Q(in[9]),
.R(1'b0));
FDRE \s_awid_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [26]),
.Q(in[10]),
.R(1'b0));
FDRE \s_awid_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [27]),
.Q(in[11]),
.R(1'b0));
FDRE \s_awid_r_reg[4]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [28]),
.Q(in[12]),
.R(1'b0));
FDRE \s_awid_r_reg[5]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [29]),
.Q(in[13]),
.R(1'b0));
FDRE \s_awid_r_reg[6]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [30]),
.Q(in[14]),
.R(1'b0));
FDRE \s_awid_r_reg[7]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [31]),
.Q(in[15]),
.R(1'b0));
FDRE \s_awid_r_reg[8]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [32]),
.Q(in[16]),
.R(1'b0));
FDRE \s_awid_r_reg[9]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [33]),
.Q(in[17]),
.R(1'b0));
FDRE \s_awlen_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [16]),
.Q(in[0]),
.R(1'b0));
FDRE \s_awlen_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [17]),
.Q(in[1]),
.R(1'b0));
FDRE \s_awlen_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [18]),
.Q(in[2]),
.R(1'b0));
FDRE \s_awlen_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [19]),
.Q(in[3]),
.R(1'b0));
FDRE \s_awlen_r_reg[4]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [20]),
.Q(in[4]),
.R(1'b0));
FDRE \s_awlen_r_reg[5]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [21]),
.Q(in[5]),
.R(1'b0));
FDRE \s_awlen_r_reg[6]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [22]),
.Q(in[6]),
.R(1'b0));
FDRE \s_awlen_r_reg[7]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [23]),
.Q(in[7]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_b_channel" *)
module zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_b_channel
(si_rs_bvalid,
\cnt_read_reg[0]_rep__0 ,
\cnt_read_reg[1]_rep__1 ,
m_axi_bready,
out,
\skid_buffer_reg[1] ,
areset_d1,
aclk,
b_push,
si_rs_bready,
m_axi_bvalid,
in,
m_axi_bresp);
output si_rs_bvalid;
output \cnt_read_reg[0]_rep__0 ;
output \cnt_read_reg[1]_rep__1 ;
output m_axi_bready;
output [11:0]out;
output [1:0]\skid_buffer_reg[1] ;
input areset_d1;
input aclk;
input b_push;
input si_rs_bready;
input m_axi_bvalid;
input [19:0]in;
input [1:0]m_axi_bresp;
wire aclk;
wire areset_d1;
wire b_push;
wire bid_fifo_0_n_2;
wire bid_fifo_0_n_3;
wire bid_fifo_0_n_6;
wire \bresp_cnt[7]_i_3_n_0 ;
wire [7:0]bresp_cnt_reg__0;
wire bresp_push;
wire [1:0]cnt_read;
wire \cnt_read_reg[0]_rep__0 ;
wire \cnt_read_reg[1]_rep__1 ;
wire [19:0]in;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire mhandshake;
wire mhandshake_r;
wire [11:0]out;
wire [7:0]p_0_in;
wire s_bresp_acc0;
wire \s_bresp_acc[0]_i_1_n_0 ;
wire \s_bresp_acc[1]_i_1_n_0 ;
wire \s_bresp_acc_reg_n_0_[0] ;
wire \s_bresp_acc_reg_n_0_[1] ;
wire shandshake;
wire shandshake_r;
wire si_rs_bready;
wire si_rs_bvalid;
wire [1:0]\skid_buffer_reg[1] ;
zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo bid_fifo_0
(.D(bid_fifo_0_n_2),
.Q(cnt_read),
.SR(s_bresp_acc0),
.aclk(aclk),
.areset_d1(areset_d1),
.b_push(b_push),
.\bresp_cnt_reg[7] (bresp_cnt_reg__0),
.bvalid_i_reg(bid_fifo_0_n_6),
.bvalid_i_reg_0(si_rs_bvalid),
.\cnt_read_reg[0]_0 (bid_fifo_0_n_3),
.\cnt_read_reg[0]_rep__0_0 (\cnt_read_reg[0]_rep__0 ),
.\cnt_read_reg[1]_rep__1_0 (\cnt_read_reg[1]_rep__1 ),
.in(in),
.mhandshake_r(mhandshake_r),
.out(out),
.sel(bresp_push),
.shandshake_r(shandshake_r),
.si_rs_bready(si_rs_bready));
LUT1 #(
.INIT(2'h1))
\bresp_cnt[0]_i_1
(.I0(bresp_cnt_reg__0[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair121" *)
LUT2 #(
.INIT(4'h6))
\bresp_cnt[1]_i_1
(.I0(bresp_cnt_reg__0[1]),
.I1(bresp_cnt_reg__0[0]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair121" *)
LUT3 #(
.INIT(8'h6A))
\bresp_cnt[2]_i_1
(.I0(bresp_cnt_reg__0[2]),
.I1(bresp_cnt_reg__0[0]),
.I2(bresp_cnt_reg__0[1]),
.O(p_0_in[2]));
(* SOFT_HLUTNM = "soft_lutpair119" *)
LUT4 #(
.INIT(16'h6AAA))
\bresp_cnt[3]_i_1
(.I0(bresp_cnt_reg__0[3]),
.I1(bresp_cnt_reg__0[1]),
.I2(bresp_cnt_reg__0[0]),
.I3(bresp_cnt_reg__0[2]),
.O(p_0_in[3]));
(* SOFT_HLUTNM = "soft_lutpair119" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\bresp_cnt[4]_i_1
(.I0(bresp_cnt_reg__0[4]),
.I1(bresp_cnt_reg__0[2]),
.I2(bresp_cnt_reg__0[0]),
.I3(bresp_cnt_reg__0[1]),
.I4(bresp_cnt_reg__0[3]),
.O(p_0_in[4]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\bresp_cnt[5]_i_1
(.I0(bresp_cnt_reg__0[5]),
.I1(bresp_cnt_reg__0[3]),
.I2(bresp_cnt_reg__0[1]),
.I3(bresp_cnt_reg__0[0]),
.I4(bresp_cnt_reg__0[2]),
.I5(bresp_cnt_reg__0[4]),
.O(p_0_in[5]));
(* SOFT_HLUTNM = "soft_lutpair120" *)
LUT2 #(
.INIT(4'h6))
\bresp_cnt[6]_i_1
(.I0(bresp_cnt_reg__0[6]),
.I1(\bresp_cnt[7]_i_3_n_0 ),
.O(p_0_in[6]));
(* SOFT_HLUTNM = "soft_lutpair120" *)
LUT3 #(
.INIT(8'h6A))
\bresp_cnt[7]_i_2
(.I0(bresp_cnt_reg__0[7]),
.I1(\bresp_cnt[7]_i_3_n_0 ),
.I2(bresp_cnt_reg__0[6]),
.O(p_0_in[7]));
LUT6 #(
.INIT(64'h8000000000000000))
\bresp_cnt[7]_i_3
(.I0(bresp_cnt_reg__0[5]),
.I1(bresp_cnt_reg__0[3]),
.I2(bresp_cnt_reg__0[1]),
.I3(bresp_cnt_reg__0[0]),
.I4(bresp_cnt_reg__0[2]),
.I5(bresp_cnt_reg__0[4]),
.O(\bresp_cnt[7]_i_3_n_0 ));
FDRE \bresp_cnt_reg[0]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[0]),
.Q(bresp_cnt_reg__0[0]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[1]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[1]),
.Q(bresp_cnt_reg__0[1]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[2]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[2]),
.Q(bresp_cnt_reg__0[2]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[3]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[3]),
.Q(bresp_cnt_reg__0[3]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[4]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[4]),
.Q(bresp_cnt_reg__0[4]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[5]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[5]),
.Q(bresp_cnt_reg__0[5]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[6]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[6]),
.Q(bresp_cnt_reg__0[6]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[7]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[7]),
.Q(bresp_cnt_reg__0[7]),
.R(s_bresp_acc0));
zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0 bresp_fifo_0
(.D(bid_fifo_0_n_2),
.Q(cnt_read),
.aclk(aclk),
.areset_d1(areset_d1),
.\bresp_cnt_reg[3] (bid_fifo_0_n_3),
.in({\s_bresp_acc_reg_n_0_[1] ,\s_bresp_acc_reg_n_0_[0] }),
.m_axi_bready(m_axi_bready),
.m_axi_bvalid(m_axi_bvalid),
.mhandshake(mhandshake),
.mhandshake_r(mhandshake_r),
.sel(bresp_push),
.shandshake_r(shandshake_r),
.\skid_buffer_reg[1] (\skid_buffer_reg[1] ));
FDRE #(
.INIT(1'b0))
bvalid_i_reg
(.C(aclk),
.CE(1'b1),
.D(bid_fifo_0_n_6),
.Q(si_rs_bvalid),
.R(1'b0));
FDRE #(
.INIT(1'b0))
mhandshake_r_reg
(.C(aclk),
.CE(1'b1),
.D(mhandshake),
.Q(mhandshake_r),
.R(areset_d1));
LUT6 #(
.INIT(64'h00000000EACEAAAA))
\s_bresp_acc[0]_i_1
(.I0(\s_bresp_acc_reg_n_0_[0] ),
.I1(m_axi_bresp[0]),
.I2(m_axi_bresp[1]),
.I3(\s_bresp_acc_reg_n_0_[1] ),
.I4(mhandshake),
.I5(s_bresp_acc0),
.O(\s_bresp_acc[0]_i_1_n_0 ));
LUT4 #(
.INIT(16'h00EC))
\s_bresp_acc[1]_i_1
(.I0(m_axi_bresp[1]),
.I1(\s_bresp_acc_reg_n_0_[1] ),
.I2(mhandshake),
.I3(s_bresp_acc0),
.O(\s_bresp_acc[1]_i_1_n_0 ));
FDRE \s_bresp_acc_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\s_bresp_acc[0]_i_1_n_0 ),
.Q(\s_bresp_acc_reg_n_0_[0] ),
.R(1'b0));
FDRE \s_bresp_acc_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\s_bresp_acc[1]_i_1_n_0 ),
.Q(\s_bresp_acc_reg_n_0_[1] ),
.R(1'b0));
LUT2 #(
.INIT(4'h8))
shandshake_r_i_1
(.I0(si_rs_bvalid),
.I1(si_rs_bready),
.O(shandshake));
FDRE #(
.INIT(1'b0))
shandshake_r_reg
(.C(aclk),
.CE(1'b1),
.D(shandshake),
.Q(shandshake_r),
.R(areset_d1));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_cmd_translator" *)
module zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator
(next_pending_r_reg,
next_pending_r_reg_0,
sel_first_reg_0,
\axaddr_incr_reg[3] ,
\axaddr_incr_reg[11] ,
sel_first__0,
Q,
\axlen_cnt_reg[7] ,
\state_reg[1]_rep ,
next_pending_r_reg_1,
next_pending_r_reg_2,
\axlen_cnt_reg[4] ,
m_axi_awaddr,
\axaddr_offset_r_reg[3] ,
\wrap_second_len_r_reg[3] ,
S,
incr_next_pending,
aclk,
wrap_next_pending,
sel_first_i,
\m_payload_i_reg[39] ,
\m_payload_i_reg[39]_0 ,
sel_first_reg_1,
O,
sel_first_reg_2,
sel_first_reg_3,
\state_reg[0] ,
\m_payload_i_reg[47] ,
E,
\m_payload_i_reg[51] ,
CO,
D,
next,
\m_payload_i_reg[11] ,
\m_payload_i_reg[38] ,
m_valid_i_reg,
\axaddr_offset_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_1 ,
\m_payload_i_reg[6] ,
\state_reg[1] ,
\state_reg[0]_rep );
output next_pending_r_reg;
output next_pending_r_reg_0;
output sel_first_reg_0;
output [3:0]\axaddr_incr_reg[3] ;
output \axaddr_incr_reg[11] ;
output sel_first__0;
output [3:0]Q;
output \axlen_cnt_reg[7] ;
output \state_reg[1]_rep ;
output next_pending_r_reg_1;
output next_pending_r_reg_2;
output \axlen_cnt_reg[4] ;
output [11:0]m_axi_awaddr;
output [3:0]\axaddr_offset_r_reg[3] ;
output [3:0]\wrap_second_len_r_reg[3] ;
output [3:0]S;
input incr_next_pending;
input aclk;
input wrap_next_pending;
input sel_first_i;
input \m_payload_i_reg[39] ;
input \m_payload_i_reg[39]_0 ;
input sel_first_reg_1;
input [3:0]O;
input sel_first_reg_2;
input sel_first_reg_3;
input \state_reg[0] ;
input \m_payload_i_reg[47] ;
input [0:0]E;
input [21:0]\m_payload_i_reg[51] ;
input [0:0]CO;
input [3:0]D;
input next;
input [7:0]\m_payload_i_reg[11] ;
input \m_payload_i_reg[38] ;
input [0:0]m_valid_i_reg;
input [3:0]\axaddr_offset_r_reg[3]_0 ;
input [3:0]\wrap_second_len_r_reg[3]_0 ;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input [6:0]\m_payload_i_reg[6] ;
input [1:0]\state_reg[1] ;
input \state_reg[0]_rep ;
wire [0:0]CO;
wire [3:0]D;
wire [0:0]E;
wire [3:0]O;
wire [3:0]Q;
wire [3:0]S;
wire aclk;
wire [11:4]axaddr_incr_reg;
wire [3:0]\axaddr_incr_reg[3] ;
wire axaddr_incr_reg_11__s_net_1;
wire [3:0]\axaddr_offset_r_reg[3] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire \axlen_cnt_reg[4] ;
wire \axlen_cnt_reg[7] ;
wire incr_cmd_0_n_21;
wire incr_next_pending;
wire [11:0]m_axi_awaddr;
wire [7:0]\m_payload_i_reg[11] ;
wire \m_payload_i_reg[38] ;
wire \m_payload_i_reg[39] ;
wire \m_payload_i_reg[39]_0 ;
wire \m_payload_i_reg[47] ;
wire [21:0]\m_payload_i_reg[51] ;
wire [6:0]\m_payload_i_reg[6] ;
wire [0:0]m_valid_i_reg;
wire next;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire next_pending_r_reg_1;
wire next_pending_r_reg_2;
wire s_axburst_eq0;
wire s_axburst_eq1;
wire sel_first__0;
wire sel_first_i;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire sel_first_reg_3;
wire \state_reg[0] ;
wire \state_reg[0]_rep ;
wire [1:0]\state_reg[1] ;
wire \state_reg[1]_rep ;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3] ;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
assign \axaddr_incr_reg[11] = axaddr_incr_reg_11__s_net_1;
zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd incr_cmd_0
(.CO(CO),
.D(D),
.E(E),
.O(O),
.Q(Q),
.S(S),
.aclk(aclk),
.axaddr_incr_reg(axaddr_incr_reg),
.\axaddr_incr_reg[11]_0 (axaddr_incr_reg_11__s_net_1),
.\axaddr_incr_reg[3]_0 (\axaddr_incr_reg[3] ),
.\axlen_cnt_reg[4]_0 (\axlen_cnt_reg[4] ),
.\axlen_cnt_reg[7]_0 (\axlen_cnt_reg[7] ),
.incr_next_pending(incr_next_pending),
.\m_axi_awaddr[1] (incr_cmd_0_n_21),
.\m_payload_i_reg[11] (\m_payload_i_reg[11] ),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.\m_payload_i_reg[51] ({\m_payload_i_reg[51] [21:20],\m_payload_i_reg[51] [18],\m_payload_i_reg[51] [14:12],\m_payload_i_reg[51] [3:0]}),
.m_valid_i_reg(m_valid_i_reg),
.next_pending_r_reg_0(next_pending_r_reg),
.next_pending_r_reg_1(next_pending_r_reg_1),
.sel_first_reg_0(sel_first_reg_1),
.sel_first_reg_1(sel_first_reg_2),
.\state_reg[0] (\state_reg[0] ),
.\state_reg[0]_rep (\state_reg[0]_rep ),
.\state_reg[1] (\state_reg[1] ));
LUT3 #(
.INIT(8'hB8))
\memory_reg[3][0]_srl4_i_2
(.I0(s_axburst_eq1),
.I1(\m_payload_i_reg[51] [15]),
.I2(s_axburst_eq0),
.O(\state_reg[1]_rep ));
FDRE s_axburst_eq0_reg
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[39] ),
.Q(s_axburst_eq0),
.R(1'b0));
FDRE s_axburst_eq1_reg
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[39]_0 ),
.Q(s_axburst_eq1),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_i),
.Q(sel_first_reg_0),
.R(1'b0));
zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd wrap_cmd_0
(.E(E),
.aclk(aclk),
.axaddr_incr_reg(axaddr_incr_reg),
.\axaddr_incr_reg[3] ({\axaddr_incr_reg[3] [3:2],\axaddr_incr_reg[3] [0]}),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3] ),
.\axaddr_offset_r_reg[3]_1 (\axaddr_offset_r_reg[3]_0 ),
.m_axi_awaddr(m_axi_awaddr),
.\m_payload_i_reg[38] (\m_payload_i_reg[38] ),
.\m_payload_i_reg[47] ({\m_payload_i_reg[51] [19:15],\m_payload_i_reg[51] [13:0]}),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.m_valid_i_reg(m_valid_i_reg),
.next(next),
.next_pending_r_reg_0(next_pending_r_reg_0),
.next_pending_r_reg_1(next_pending_r_reg_2),
.sel_first_reg_0(sel_first__0),
.sel_first_reg_1(sel_first_reg_3),
.sel_first_reg_2(incr_cmd_0_n_21),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3] ),
.\wrap_second_len_r_reg[3]_1 (\wrap_second_len_r_reg[3]_0 ),
.\wrap_second_len_r_reg[3]_2 (\wrap_second_len_r_reg[3]_1 ));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_cmd_translator" *)
module zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1
(next_pending_r_reg,
wrap_next_pending,
sel_first_reg_0,
\axaddr_incr_reg[3] ,
\axaddr_incr_reg[11] ,
sel_first_reg_1,
Q,
next_pending_r_reg_0,
r_rlast,
\state_reg[0]_rep ,
m_axi_araddr,
\axaddr_offset_r_reg[3] ,
\wrap_second_len_r_reg[3] ,
S,
incr_next_pending,
aclk,
sel_first_i,
\m_payload_i_reg[39] ,
\m_payload_i_reg[39]_0 ,
sel_first_reg_2,
O,
sel_first_reg_3,
sel_first_reg_4,
\state_reg[0] ,
\m_payload_i_reg[47] ,
E,
\m_payload_i_reg[51] ,
\state_reg[0]_rep_0 ,
si_rs_arvalid,
\state_reg[1]_rep ,
CO,
\m_payload_i_reg[46] ,
\state_reg[1]_rep_0 ,
\m_payload_i_reg[3] ,
\m_payload_i_reg[11] ,
\m_payload_i_reg[38] ,
m_valid_i_reg,
D,
\axaddr_offset_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_1 ,
\m_payload_i_reg[6] ,
\state_reg[1] ,
m_axi_arready);
output next_pending_r_reg;
output wrap_next_pending;
output sel_first_reg_0;
output [3:0]\axaddr_incr_reg[3] ;
output \axaddr_incr_reg[11] ;
output sel_first_reg_1;
output [1:0]Q;
output next_pending_r_reg_0;
output r_rlast;
output \state_reg[0]_rep ;
output [11:0]m_axi_araddr;
output [3:0]\axaddr_offset_r_reg[3] ;
output [3:0]\wrap_second_len_r_reg[3] ;
output [3:0]S;
input incr_next_pending;
input aclk;
input sel_first_i;
input \m_payload_i_reg[39] ;
input \m_payload_i_reg[39]_0 ;
input sel_first_reg_2;
input [3:0]O;
input sel_first_reg_3;
input sel_first_reg_4;
input \state_reg[0] ;
input \m_payload_i_reg[47] ;
input [0:0]E;
input [23:0]\m_payload_i_reg[51] ;
input \state_reg[0]_rep_0 ;
input si_rs_arvalid;
input \state_reg[1]_rep ;
input [0:0]CO;
input \m_payload_i_reg[46] ;
input \state_reg[1]_rep_0 ;
input [3:0]\m_payload_i_reg[3] ;
input [3:0]\m_payload_i_reg[11] ;
input \m_payload_i_reg[38] ;
input [0:0]m_valid_i_reg;
input [1:0]D;
input [3:0]\axaddr_offset_r_reg[3]_0 ;
input [3:0]\wrap_second_len_r_reg[3]_0 ;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input [6:0]\m_payload_i_reg[6] ;
input [1:0]\state_reg[1] ;
input m_axi_arready;
wire [0:0]CO;
wire [1:0]D;
wire [0:0]E;
wire [3:0]O;
wire [1:0]Q;
wire [3:0]S;
wire aclk;
wire [11:4]axaddr_incr_reg;
wire [3:0]\axaddr_incr_reg[3] ;
wire axaddr_incr_reg_11__s_net_1;
wire [3:0]\axaddr_offset_r_reg[3] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire incr_cmd_0_n_16;
wire incr_cmd_0_n_17;
wire incr_next_pending;
wire [11:0]m_axi_araddr;
wire m_axi_arready;
wire [3:0]\m_payload_i_reg[11] ;
wire \m_payload_i_reg[38] ;
wire \m_payload_i_reg[39] ;
wire \m_payload_i_reg[39]_0 ;
wire [3:0]\m_payload_i_reg[3] ;
wire \m_payload_i_reg[46] ;
wire \m_payload_i_reg[47] ;
wire [23:0]\m_payload_i_reg[51] ;
wire [6:0]\m_payload_i_reg[6] ;
wire [0:0]m_valid_i_reg;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire r_rlast;
wire s_axburst_eq0;
wire s_axburst_eq1;
wire sel_first_i;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire sel_first_reg_3;
wire sel_first_reg_4;
wire si_rs_arvalid;
wire \state_reg[0] ;
wire \state_reg[0]_rep ;
wire \state_reg[0]_rep_0 ;
wire [1:0]\state_reg[1] ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3] ;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
assign \axaddr_incr_reg[11] = axaddr_incr_reg_11__s_net_1;
zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 incr_cmd_0
(.CO(CO),
.D(D),
.E(E),
.O(O),
.Q(Q),
.S(S),
.aclk(aclk),
.\axaddr_incr_reg[11]_0 ({axaddr_incr_reg[11:6],axaddr_incr_reg[4]}),
.\axaddr_incr_reg[11]_1 (axaddr_incr_reg_11__s_net_1),
.\axaddr_incr_reg[3]_0 (\axaddr_incr_reg[3] ),
.incr_next_pending(incr_next_pending),
.\m_axi_araddr[2] (incr_cmd_0_n_17),
.\m_axi_araddr[5] (incr_cmd_0_n_16),
.m_axi_arready(m_axi_arready),
.\m_payload_i_reg[11] (\m_payload_i_reg[11] ),
.\m_payload_i_reg[3] (\m_payload_i_reg[3] ),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.\m_payload_i_reg[51] ({\m_payload_i_reg[51] [23:20],\m_payload_i_reg[51] [18],\m_payload_i_reg[51] [14:12],\m_payload_i_reg[51] [5],\m_payload_i_reg[51] [3:0]}),
.m_valid_i_reg(m_valid_i_reg),
.next_pending_r_reg_0(next_pending_r_reg),
.next_pending_r_reg_1(next_pending_r_reg_0),
.sel_first_reg_0(sel_first_reg_2),
.sel_first_reg_1(sel_first_reg_3),
.\state_reg[0] (\state_reg[0] ),
.\state_reg[1] (\state_reg[1] ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'h1D))
r_rlast_r_i_1
(.I0(s_axburst_eq0),
.I1(\m_payload_i_reg[51] [15]),
.I2(s_axburst_eq1),
.O(r_rlast));
FDRE s_axburst_eq0_reg
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[39] ),
.Q(s_axburst_eq0),
.R(1'b0));
FDRE s_axburst_eq1_reg
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[39]_0 ),
.Q(s_axburst_eq1),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_i),
.Q(sel_first_reg_0),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'hB8))
\state[1]_i_3
(.I0(s_axburst_eq1),
.I1(\m_payload_i_reg[51] [15]),
.I2(s_axburst_eq0),
.O(\state_reg[0]_rep ));
zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 wrap_cmd_0
(.E(E),
.aclk(aclk),
.\axaddr_incr_reg[11] ({axaddr_incr_reg[11:6],axaddr_incr_reg[4]}),
.\axaddr_incr_reg[3] ({\axaddr_incr_reg[3] [3],\axaddr_incr_reg[3] [1:0]}),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3] ),
.\axaddr_offset_r_reg[3]_1 (\axaddr_offset_r_reg[3]_0 ),
.m_axi_araddr(m_axi_araddr),
.\m_payload_i_reg[38] (\m_payload_i_reg[38] ),
.\m_payload_i_reg[46] (\m_payload_i_reg[46] ),
.\m_payload_i_reg[47] ({\m_payload_i_reg[51] [19:15],\m_payload_i_reg[51] [13:0]}),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.m_valid_i_reg(m_valid_i_reg),
.sel_first_reg_0(sel_first_reg_1),
.sel_first_reg_1(sel_first_reg_4),
.sel_first_reg_2(incr_cmd_0_n_16),
.sel_first_reg_3(incr_cmd_0_n_17),
.si_rs_arvalid(si_rs_arvalid),
.\state_reg[0]_rep (\state_reg[0]_rep_0 ),
.\state_reg[1]_rep (\state_reg[1]_rep ),
.\state_reg[1]_rep_0 (\state_reg[1]_rep_0 ),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3] ),
.\wrap_second_len_r_reg[3]_1 (\wrap_second_len_r_reg[3]_0 ),
.\wrap_second_len_r_reg[3]_2 (\wrap_second_len_r_reg[3]_1 ));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_incr_cmd" *)
module zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd
(next_pending_r_reg_0,
\axaddr_incr_reg[3]_0 ,
axaddr_incr_reg,
\axaddr_incr_reg[11]_0 ,
Q,
\axlen_cnt_reg[7]_0 ,
next_pending_r_reg_1,
\axlen_cnt_reg[4]_0 ,
\m_axi_awaddr[1] ,
S,
incr_next_pending,
aclk,
sel_first_reg_0,
O,
sel_first_reg_1,
\state_reg[0] ,
\m_payload_i_reg[47] ,
CO,
E,
\m_payload_i_reg[51] ,
\m_payload_i_reg[11] ,
m_valid_i_reg,
D,
\state_reg[1] ,
\state_reg[0]_rep );
output next_pending_r_reg_0;
output [3:0]\axaddr_incr_reg[3]_0 ;
output [7:0]axaddr_incr_reg;
output \axaddr_incr_reg[11]_0 ;
output [3:0]Q;
output \axlen_cnt_reg[7]_0 ;
output next_pending_r_reg_1;
output \axlen_cnt_reg[4]_0 ;
output \m_axi_awaddr[1] ;
output [3:0]S;
input incr_next_pending;
input aclk;
input sel_first_reg_0;
input [3:0]O;
input sel_first_reg_1;
input \state_reg[0] ;
input \m_payload_i_reg[47] ;
input [0:0]CO;
input [0:0]E;
input [9:0]\m_payload_i_reg[51] ;
input [7:0]\m_payload_i_reg[11] ;
input [0:0]m_valid_i_reg;
input [3:0]D;
input [1:0]\state_reg[1] ;
input \state_reg[0]_rep ;
wire [0:0]CO;
wire [3:0]D;
wire [0:0]E;
wire [3:0]O;
wire [3:0]Q;
wire [3:0]S;
wire aclk;
wire \axaddr_incr[4]_i_2_n_0 ;
wire \axaddr_incr[4]_i_3_n_0 ;
wire \axaddr_incr[4]_i_4_n_0 ;
wire \axaddr_incr[4]_i_5_n_0 ;
wire \axaddr_incr[8]_i_2_n_0 ;
wire \axaddr_incr[8]_i_3_n_0 ;
wire \axaddr_incr[8]_i_4_n_0 ;
wire \axaddr_incr[8]_i_5_n_0 ;
wire [7:0]axaddr_incr_reg;
wire \axaddr_incr_reg[11]_0 ;
wire [3:0]\axaddr_incr_reg[3]_0 ;
wire \axaddr_incr_reg[4]_i_1_n_0 ;
wire \axaddr_incr_reg[4]_i_1_n_1 ;
wire \axaddr_incr_reg[4]_i_1_n_2 ;
wire \axaddr_incr_reg[4]_i_1_n_3 ;
wire \axaddr_incr_reg[4]_i_1_n_4 ;
wire \axaddr_incr_reg[4]_i_1_n_5 ;
wire \axaddr_incr_reg[4]_i_1_n_6 ;
wire \axaddr_incr_reg[4]_i_1_n_7 ;
wire \axaddr_incr_reg[8]_i_1_n_1 ;
wire \axaddr_incr_reg[8]_i_1_n_2 ;
wire \axaddr_incr_reg[8]_i_1_n_3 ;
wire \axaddr_incr_reg[8]_i_1_n_4 ;
wire \axaddr_incr_reg[8]_i_1_n_5 ;
wire \axaddr_incr_reg[8]_i_1_n_6 ;
wire \axaddr_incr_reg[8]_i_1_n_7 ;
wire \axlen_cnt[3]_i_1_n_0 ;
wire \axlen_cnt[7]_i_4_n_0 ;
wire \axlen_cnt_reg[4]_0 ;
wire \axlen_cnt_reg[7]_0 ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire \axlen_cnt_reg_n_0_[6] ;
wire \axlen_cnt_reg_n_0_[7] ;
wire incr_next_pending;
wire \m_axi_awaddr[1] ;
wire [7:0]\m_payload_i_reg[11] ;
wire \m_payload_i_reg[47] ;
wire [9:0]\m_payload_i_reg[51] ;
wire [0:0]m_valid_i_reg;
wire next_pending_r_reg_0;
wire next_pending_r_reg_1;
wire [7:2]p_1_in;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire \state_reg[0] ;
wire \state_reg[0]_rep ;
wire [1:0]\state_reg[1] ;
wire [3:3]\NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED ;
LUT6 #(
.INIT(64'h559AAAAAAAAAAAAA))
\axaddr_incr[0]_i_15
(.I0(\m_payload_i_reg[51] [3]),
.I1(\state_reg[1] [0]),
.I2(\state_reg[1] [1]),
.I3(\state_reg[0]_rep ),
.I4(\m_payload_i_reg[51] [5]),
.I5(\m_payload_i_reg[51] [4]),
.O(S[3]));
LUT6 #(
.INIT(64'h0000AAAA559AAAAA))
\axaddr_incr[0]_i_16
(.I0(\m_payload_i_reg[51] [2]),
.I1(\state_reg[1] [0]),
.I2(\state_reg[1] [1]),
.I3(\state_reg[0]_rep ),
.I4(\m_payload_i_reg[51] [5]),
.I5(\m_payload_i_reg[51] [4]),
.O(S[2]));
LUT6 #(
.INIT(64'h00000000559AAAAA))
\axaddr_incr[0]_i_17
(.I0(\m_payload_i_reg[51] [1]),
.I1(\state_reg[1] [0]),
.I2(\state_reg[1] [1]),
.I3(\state_reg[0]_rep ),
.I4(\m_payload_i_reg[51] [4]),
.I5(\m_payload_i_reg[51] [5]),
.O(S[1]));
LUT6 #(
.INIT(64'h000000000000559A))
\axaddr_incr[0]_i_18
(.I0(\m_payload_i_reg[51] [0]),
.I1(\state_reg[1] [0]),
.I2(\state_reg[1] [1]),
.I3(\state_reg[0]_rep ),
.I4(\m_payload_i_reg[51] [5]),
.I5(\m_payload_i_reg[51] [4]),
.O(S[0]));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_2
(.I0(\m_payload_i_reg[11] [3]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[3]),
.O(\axaddr_incr[4]_i_2_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_3
(.I0(\m_payload_i_reg[11] [2]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[2]),
.O(\axaddr_incr[4]_i_3_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_4
(.I0(\m_payload_i_reg[11] [1]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[1]),
.O(\axaddr_incr[4]_i_4_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_5
(.I0(\m_payload_i_reg[11] [0]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[0]),
.O(\axaddr_incr[4]_i_5_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_2
(.I0(\m_payload_i_reg[11] [7]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[7]),
.O(\axaddr_incr[8]_i_2_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_3
(.I0(\m_payload_i_reg[11] [6]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[6]),
.O(\axaddr_incr[8]_i_3_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_4
(.I0(\m_payload_i_reg[11] [5]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[5]),
.O(\axaddr_incr[8]_i_4_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_5
(.I0(\m_payload_i_reg[11] [4]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[4]),
.O(\axaddr_incr[8]_i_5_n_0 ));
FDRE \axaddr_incr_reg[0]
(.C(aclk),
.CE(sel_first_reg_0),
.D(O[0]),
.Q(\axaddr_incr_reg[3]_0 [0]),
.R(1'b0));
FDRE \axaddr_incr_reg[10]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[8]_i_1_n_5 ),
.Q(axaddr_incr_reg[6]),
.R(1'b0));
FDRE \axaddr_incr_reg[11]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[8]_i_1_n_4 ),
.Q(axaddr_incr_reg[7]),
.R(1'b0));
FDRE \axaddr_incr_reg[1]
(.C(aclk),
.CE(sel_first_reg_0),
.D(O[1]),
.Q(\axaddr_incr_reg[3]_0 [1]),
.R(1'b0));
FDRE \axaddr_incr_reg[2]
(.C(aclk),
.CE(sel_first_reg_0),
.D(O[2]),
.Q(\axaddr_incr_reg[3]_0 [2]),
.R(1'b0));
FDRE \axaddr_incr_reg[3]
(.C(aclk),
.CE(sel_first_reg_0),
.D(O[3]),
.Q(\axaddr_incr_reg[3]_0 [3]),
.R(1'b0));
FDRE \axaddr_incr_reg[4]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[4]_i_1_n_7 ),
.Q(axaddr_incr_reg[0]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[4]_i_1
(.CI(CO),
.CO({\axaddr_incr_reg[4]_i_1_n_0 ,\axaddr_incr_reg[4]_i_1_n_1 ,\axaddr_incr_reg[4]_i_1_n_2 ,\axaddr_incr_reg[4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[4]_i_1_n_4 ,\axaddr_incr_reg[4]_i_1_n_5 ,\axaddr_incr_reg[4]_i_1_n_6 ,\axaddr_incr_reg[4]_i_1_n_7 }),
.S({\axaddr_incr[4]_i_2_n_0 ,\axaddr_incr[4]_i_3_n_0 ,\axaddr_incr[4]_i_4_n_0 ,\axaddr_incr[4]_i_5_n_0 }));
FDRE \axaddr_incr_reg[5]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[4]_i_1_n_6 ),
.Q(axaddr_incr_reg[1]),
.R(1'b0));
FDRE \axaddr_incr_reg[6]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[4]_i_1_n_5 ),
.Q(axaddr_incr_reg[2]),
.R(1'b0));
FDRE \axaddr_incr_reg[7]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[4]_i_1_n_4 ),
.Q(axaddr_incr_reg[3]),
.R(1'b0));
FDRE \axaddr_incr_reg[8]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[8]_i_1_n_7 ),
.Q(axaddr_incr_reg[4]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[8]_i_1
(.CI(\axaddr_incr_reg[4]_i_1_n_0 ),
.CO({\NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED [3],\axaddr_incr_reg[8]_i_1_n_1 ,\axaddr_incr_reg[8]_i_1_n_2 ,\axaddr_incr_reg[8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[8]_i_1_n_4 ,\axaddr_incr_reg[8]_i_1_n_5 ,\axaddr_incr_reg[8]_i_1_n_6 ,\axaddr_incr_reg[8]_i_1_n_7 }),
.S({\axaddr_incr[8]_i_2_n_0 ,\axaddr_incr[8]_i_3_n_0 ,\axaddr_incr[8]_i_4_n_0 ,\axaddr_incr[8]_i_5_n_0 }));
FDRE \axaddr_incr_reg[9]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[8]_i_1_n_6 ),
.Q(axaddr_incr_reg[5]),
.R(1'b0));
LUT6 #(
.INIT(64'hF8F8F88F88888888))
\axlen_cnt[2]_i_1
(.I0(E),
.I1(\m_payload_i_reg[51] [7]),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(Q[0]),
.I4(Q[1]),
.I5(\state_reg[0] ),
.O(p_1_in[2]));
LUT6 #(
.INIT(64'hAAA90000FFFFFFFF))
\axlen_cnt[3]_i_1
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(Q[1]),
.I2(Q[0]),
.I3(\axlen_cnt_reg_n_0_[2] ),
.I4(\state_reg[0] ),
.I5(\m_payload_i_reg[47] ),
.O(\axlen_cnt[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair113" *)
LUT4 #(
.INIT(16'hFFFE))
\axlen_cnt[4]_i_2
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(Q[1]),
.I2(Q[0]),
.I3(\axlen_cnt_reg_n_0_[2] ),
.O(\axlen_cnt_reg[4]_0 ));
LUT6 #(
.INIT(64'hFFFFA900A900A900))
\axlen_cnt[6]_i_1
(.I0(\axlen_cnt_reg_n_0_[6] ),
.I1(\axlen_cnt_reg[7]_0 ),
.I2(Q[3]),
.I3(\state_reg[0] ),
.I4(E),
.I5(\m_payload_i_reg[51] [8]),
.O(p_1_in[6]));
LUT6 #(
.INIT(64'hFFFFA900A900A900))
\axlen_cnt[7]_i_2
(.I0(\axlen_cnt_reg_n_0_[7] ),
.I1(\axlen_cnt_reg[7]_0 ),
.I2(\axlen_cnt[7]_i_4_n_0 ),
.I3(\state_reg[0] ),
.I4(E),
.I5(\m_payload_i_reg[51] [9]),
.O(p_1_in[7]));
(* SOFT_HLUTNM = "soft_lutpair113" *)
LUT5 #(
.INIT(32'hFFFFFFFE))
\axlen_cnt[7]_i_3
(.I0(Q[2]),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(Q[0]),
.I3(Q[1]),
.I4(\axlen_cnt_reg_n_0_[3] ),
.O(\axlen_cnt_reg[7]_0 ));
LUT2 #(
.INIT(4'hE))
\axlen_cnt[7]_i_4
(.I0(\axlen_cnt_reg_n_0_[6] ),
.I1(Q[3]),
.O(\axlen_cnt[7]_i_4_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(D[0]),
.Q(Q[0]),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(D[1]),
.Q(Q[1]),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(p_1_in[2]),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[3]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
FDRE \axlen_cnt_reg[4]
(.C(aclk),
.CE(m_valid_i_reg),
.D(D[2]),
.Q(Q[2]),
.R(1'b0));
FDRE \axlen_cnt_reg[5]
(.C(aclk),
.CE(m_valid_i_reg),
.D(D[3]),
.Q(Q[3]),
.R(1'b0));
FDRE \axlen_cnt_reg[6]
(.C(aclk),
.CE(m_valid_i_reg),
.D(p_1_in[6]),
.Q(\axlen_cnt_reg_n_0_[6] ),
.R(1'b0));
FDRE \axlen_cnt_reg[7]
(.C(aclk),
.CE(m_valid_i_reg),
.D(p_1_in[7]),
.Q(\axlen_cnt_reg_n_0_[7] ),
.R(1'b0));
LUT4 #(
.INIT(16'hEF40))
\m_axi_awaddr[1]_INST_0_i_1
(.I0(\axaddr_incr_reg[11]_0 ),
.I1(\axaddr_incr_reg[3]_0 [1]),
.I2(\m_payload_i_reg[51] [6]),
.I3(\m_payload_i_reg[51] [1]),
.O(\m_axi_awaddr[1] ));
LUT6 #(
.INIT(64'h0000000000000001))
next_pending_r_i_3
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[7] ),
.I2(Q[2]),
.I3(\axlen_cnt_reg_n_0_[2] ),
.I4(Q[1]),
.I5(\axlen_cnt[7]_i_4_n_0 ),
.O(next_pending_r_reg_1));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(incr_next_pending),
.Q(next_pending_r_reg_0),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_1),
.Q(\axaddr_incr_reg[11]_0 ),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_incr_cmd" *)
module zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2
(next_pending_r_reg_0,
\axaddr_incr_reg[3]_0 ,
\axaddr_incr_reg[11]_0 ,
\axaddr_incr_reg[11]_1 ,
Q,
next_pending_r_reg_1,
\m_axi_araddr[5] ,
\m_axi_araddr[2] ,
S,
incr_next_pending,
aclk,
sel_first_reg_0,
O,
sel_first_reg_1,
\state_reg[0] ,
\m_payload_i_reg[47] ,
CO,
E,
\m_payload_i_reg[51] ,
\m_payload_i_reg[3] ,
\m_payload_i_reg[11] ,
m_valid_i_reg,
D,
\state_reg[1] ,
m_axi_arready);
output next_pending_r_reg_0;
output [3:0]\axaddr_incr_reg[3]_0 ;
output [6:0]\axaddr_incr_reg[11]_0 ;
output \axaddr_incr_reg[11]_1 ;
output [1:0]Q;
output next_pending_r_reg_1;
output \m_axi_araddr[5] ;
output \m_axi_araddr[2] ;
output [3:0]S;
input incr_next_pending;
input aclk;
input sel_first_reg_0;
input [3:0]O;
input sel_first_reg_1;
input \state_reg[0] ;
input \m_payload_i_reg[47] ;
input [0:0]CO;
input [0:0]E;
input [12:0]\m_payload_i_reg[51] ;
input [3:0]\m_payload_i_reg[3] ;
input [3:0]\m_payload_i_reg[11] ;
input [0:0]m_valid_i_reg;
input [1:0]D;
input [1:0]\state_reg[1] ;
input m_axi_arready;
wire [0:0]CO;
wire [1:0]D;
wire [0:0]E;
wire [3:0]O;
wire [1:0]Q;
wire [3:0]S;
wire aclk;
wire \axaddr_incr[4]_i_2__0_n_0 ;
wire \axaddr_incr[4]_i_3__0_n_0 ;
wire \axaddr_incr[4]_i_4__0_n_0 ;
wire \axaddr_incr[4]_i_5__0_n_0 ;
wire \axaddr_incr[8]_i_2__0_n_0 ;
wire \axaddr_incr[8]_i_3__0_n_0 ;
wire \axaddr_incr[8]_i_4__0_n_0 ;
wire \axaddr_incr[8]_i_5__0_n_0 ;
wire [5:5]axaddr_incr_reg;
wire [6:0]\axaddr_incr_reg[11]_0 ;
wire \axaddr_incr_reg[11]_1 ;
wire [3:0]\axaddr_incr_reg[3]_0 ;
wire \axaddr_incr_reg[4]_i_1__0_n_0 ;
wire \axaddr_incr_reg[4]_i_1__0_n_1 ;
wire \axaddr_incr_reg[4]_i_1__0_n_2 ;
wire \axaddr_incr_reg[4]_i_1__0_n_3 ;
wire \axaddr_incr_reg[4]_i_1__0_n_4 ;
wire \axaddr_incr_reg[4]_i_1__0_n_5 ;
wire \axaddr_incr_reg[4]_i_1__0_n_6 ;
wire \axaddr_incr_reg[4]_i_1__0_n_7 ;
wire \axaddr_incr_reg[8]_i_1__0_n_1 ;
wire \axaddr_incr_reg[8]_i_1__0_n_2 ;
wire \axaddr_incr_reg[8]_i_1__0_n_3 ;
wire \axaddr_incr_reg[8]_i_1__0_n_4 ;
wire \axaddr_incr_reg[8]_i_1__0_n_5 ;
wire \axaddr_incr_reg[8]_i_1__0_n_6 ;
wire \axaddr_incr_reg[8]_i_1__0_n_7 ;
wire \axlen_cnt[2]_i_1__1_n_0 ;
wire \axlen_cnt[3]_i_1__1_n_0 ;
wire \axlen_cnt[4]_i_1__0_n_0 ;
wire \axlen_cnt[4]_i_2__0_n_0 ;
wire \axlen_cnt[5]_i_1__0_n_0 ;
wire \axlen_cnt[5]_i_2_n_0 ;
wire \axlen_cnt[6]_i_1__0_n_0 ;
wire \axlen_cnt[7]_i_2__0_n_0 ;
wire \axlen_cnt[7]_i_3__0_n_0 ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire \axlen_cnt_reg_n_0_[4] ;
wire \axlen_cnt_reg_n_0_[5] ;
wire \axlen_cnt_reg_n_0_[6] ;
wire \axlen_cnt_reg_n_0_[7] ;
wire incr_next_pending;
wire \m_axi_araddr[2] ;
wire \m_axi_araddr[5] ;
wire m_axi_arready;
wire [3:0]\m_payload_i_reg[11] ;
wire [3:0]\m_payload_i_reg[3] ;
wire \m_payload_i_reg[47] ;
wire [12:0]\m_payload_i_reg[51] ;
wire [0:0]m_valid_i_reg;
wire next_pending_r_i_4__0_n_0;
wire next_pending_r_reg_0;
wire next_pending_r_reg_1;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire \state_reg[0] ;
wire [1:0]\state_reg[1] ;
wire [3:3]\NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED ;
LUT6 #(
.INIT(64'hAA6AAAAAAAAAAAAA))
\axaddr_incr[0]_i_15
(.I0(\m_payload_i_reg[51] [3]),
.I1(\m_payload_i_reg[51] [6]),
.I2(\m_payload_i_reg[51] [5]),
.I3(\state_reg[1] [1]),
.I4(\state_reg[1] [0]),
.I5(m_axi_arready),
.O(S[3]));
LUT6 #(
.INIT(64'h2A262A2A2A2A2A2A))
\axaddr_incr[0]_i_16
(.I0(\m_payload_i_reg[51] [2]),
.I1(\m_payload_i_reg[51] [6]),
.I2(\m_payload_i_reg[51] [5]),
.I3(\state_reg[1] [1]),
.I4(\state_reg[1] [0]),
.I5(m_axi_arready),
.O(S[2]));
LUT6 #(
.INIT(64'h0A060A0A0A0A0A0A))
\axaddr_incr[0]_i_17
(.I0(\m_payload_i_reg[51] [1]),
.I1(\m_payload_i_reg[51] [5]),
.I2(\m_payload_i_reg[51] [6]),
.I3(\state_reg[1] [1]),
.I4(\state_reg[1] [0]),
.I5(m_axi_arready),
.O(S[1]));
LUT6 #(
.INIT(64'h0201020202020202))
\axaddr_incr[0]_i_18
(.I0(\m_payload_i_reg[51] [0]),
.I1(\m_payload_i_reg[51] [6]),
.I2(\m_payload_i_reg[51] [5]),
.I3(\state_reg[1] [1]),
.I4(\state_reg[1] [0]),
.I5(m_axi_arready),
.O(S[0]));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_2__0
(.I0(\m_payload_i_reg[3] [3]),
.I1(\axaddr_incr_reg[11]_1 ),
.I2(\axaddr_incr_reg[11]_0 [2]),
.O(\axaddr_incr[4]_i_2__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_3__0
(.I0(\m_payload_i_reg[3] [2]),
.I1(\axaddr_incr_reg[11]_1 ),
.I2(\axaddr_incr_reg[11]_0 [1]),
.O(\axaddr_incr[4]_i_3__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_4__0
(.I0(\m_payload_i_reg[3] [1]),
.I1(\axaddr_incr_reg[11]_1 ),
.I2(axaddr_incr_reg),
.O(\axaddr_incr[4]_i_4__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_5__0
(.I0(\m_payload_i_reg[3] [0]),
.I1(\axaddr_incr_reg[11]_1 ),
.I2(\axaddr_incr_reg[11]_0 [0]),
.O(\axaddr_incr[4]_i_5__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_2__0
(.I0(\m_payload_i_reg[11] [3]),
.I1(\axaddr_incr_reg[11]_1 ),
.I2(\axaddr_incr_reg[11]_0 [6]),
.O(\axaddr_incr[8]_i_2__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_3__0
(.I0(\m_payload_i_reg[11] [2]),
.I1(\axaddr_incr_reg[11]_1 ),
.I2(\axaddr_incr_reg[11]_0 [5]),
.O(\axaddr_incr[8]_i_3__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_4__0
(.I0(\m_payload_i_reg[11] [1]),
.I1(\axaddr_incr_reg[11]_1 ),
.I2(\axaddr_incr_reg[11]_0 [4]),
.O(\axaddr_incr[8]_i_4__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_5__0
(.I0(\m_payload_i_reg[11] [0]),
.I1(\axaddr_incr_reg[11]_1 ),
.I2(\axaddr_incr_reg[11]_0 [3]),
.O(\axaddr_incr[8]_i_5__0_n_0 ));
FDRE \axaddr_incr_reg[0]
(.C(aclk),
.CE(sel_first_reg_0),
.D(O[0]),
.Q(\axaddr_incr_reg[3]_0 [0]),
.R(1'b0));
FDRE \axaddr_incr_reg[10]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[8]_i_1__0_n_5 ),
.Q(\axaddr_incr_reg[11]_0 [5]),
.R(1'b0));
FDRE \axaddr_incr_reg[11]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[8]_i_1__0_n_4 ),
.Q(\axaddr_incr_reg[11]_0 [6]),
.R(1'b0));
FDRE \axaddr_incr_reg[1]
(.C(aclk),
.CE(sel_first_reg_0),
.D(O[1]),
.Q(\axaddr_incr_reg[3]_0 [1]),
.R(1'b0));
FDRE \axaddr_incr_reg[2]
(.C(aclk),
.CE(sel_first_reg_0),
.D(O[2]),
.Q(\axaddr_incr_reg[3]_0 [2]),
.R(1'b0));
FDRE \axaddr_incr_reg[3]
(.C(aclk),
.CE(sel_first_reg_0),
.D(O[3]),
.Q(\axaddr_incr_reg[3]_0 [3]),
.R(1'b0));
FDRE \axaddr_incr_reg[4]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[4]_i_1__0_n_7 ),
.Q(\axaddr_incr_reg[11]_0 [0]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[4]_i_1__0
(.CI(CO),
.CO({\axaddr_incr_reg[4]_i_1__0_n_0 ,\axaddr_incr_reg[4]_i_1__0_n_1 ,\axaddr_incr_reg[4]_i_1__0_n_2 ,\axaddr_incr_reg[4]_i_1__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[4]_i_1__0_n_4 ,\axaddr_incr_reg[4]_i_1__0_n_5 ,\axaddr_incr_reg[4]_i_1__0_n_6 ,\axaddr_incr_reg[4]_i_1__0_n_7 }),
.S({\axaddr_incr[4]_i_2__0_n_0 ,\axaddr_incr[4]_i_3__0_n_0 ,\axaddr_incr[4]_i_4__0_n_0 ,\axaddr_incr[4]_i_5__0_n_0 }));
FDRE \axaddr_incr_reg[5]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[4]_i_1__0_n_6 ),
.Q(axaddr_incr_reg),
.R(1'b0));
FDRE \axaddr_incr_reg[6]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[4]_i_1__0_n_5 ),
.Q(\axaddr_incr_reg[11]_0 [1]),
.R(1'b0));
FDRE \axaddr_incr_reg[7]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[4]_i_1__0_n_4 ),
.Q(\axaddr_incr_reg[11]_0 [2]),
.R(1'b0));
FDRE \axaddr_incr_reg[8]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[8]_i_1__0_n_7 ),
.Q(\axaddr_incr_reg[11]_0 [3]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[8]_i_1__0
(.CI(\axaddr_incr_reg[4]_i_1__0_n_0 ),
.CO({\NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED [3],\axaddr_incr_reg[8]_i_1__0_n_1 ,\axaddr_incr_reg[8]_i_1__0_n_2 ,\axaddr_incr_reg[8]_i_1__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[8]_i_1__0_n_4 ,\axaddr_incr_reg[8]_i_1__0_n_5 ,\axaddr_incr_reg[8]_i_1__0_n_6 ,\axaddr_incr_reg[8]_i_1__0_n_7 }),
.S({\axaddr_incr[8]_i_2__0_n_0 ,\axaddr_incr[8]_i_3__0_n_0 ,\axaddr_incr[8]_i_4__0_n_0 ,\axaddr_incr[8]_i_5__0_n_0 }));
FDRE \axaddr_incr_reg[9]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[8]_i_1__0_n_6 ),
.Q(\axaddr_incr_reg[11]_0 [4]),
.R(1'b0));
LUT6 #(
.INIT(64'hF8F8F88F88888888))
\axlen_cnt[2]_i_1__1
(.I0(E),
.I1(\m_payload_i_reg[51] [8]),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(Q[0]),
.I4(Q[1]),
.I5(\state_reg[0] ),
.O(\axlen_cnt[2]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'hAAA90000FFFFFFFF))
\axlen_cnt[3]_i_1__1
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(Q[1]),
.I2(Q[0]),
.I3(\axlen_cnt_reg_n_0_[2] ),
.I4(\state_reg[0] ),
.I5(\m_payload_i_reg[47] ),
.O(\axlen_cnt[3]_i_1__1_n_0 ));
LUT5 #(
.INIT(32'hFF909090))
\axlen_cnt[4]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[4] ),
.I1(\axlen_cnt[4]_i_2__0_n_0 ),
.I2(\state_reg[0] ),
.I3(E),
.I4(\m_payload_i_reg[51] [9]),
.O(\axlen_cnt[4]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'hFFFE))
\axlen_cnt[4]_i_2__0
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(Q[1]),
.I2(Q[0]),
.I3(\axlen_cnt_reg_n_0_[2] ),
.O(\axlen_cnt[4]_i_2__0_n_0 ));
LUT5 #(
.INIT(32'hFF909090))
\axlen_cnt[5]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[5] ),
.I1(\axlen_cnt[5]_i_2_n_0 ),
.I2(\state_reg[0] ),
.I3(E),
.I4(\m_payload_i_reg[51] [10]),
.O(\axlen_cnt[5]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'hFFFFFFFE))
\axlen_cnt[5]_i_2
(.I0(\axlen_cnt_reg_n_0_[4] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(Q[0]),
.I3(Q[1]),
.I4(\axlen_cnt_reg_n_0_[3] ),
.O(\axlen_cnt[5]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFF909090))
\axlen_cnt[6]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[6] ),
.I1(\axlen_cnt[7]_i_3__0_n_0 ),
.I2(\state_reg[0] ),
.I3(E),
.I4(\m_payload_i_reg[51] [11]),
.O(\axlen_cnt[6]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hF8F8F88F88888888))
\axlen_cnt[7]_i_2__0
(.I0(E),
.I1(\m_payload_i_reg[51] [12]),
.I2(\axlen_cnt_reg_n_0_[7] ),
.I3(\axlen_cnt[7]_i_3__0_n_0 ),
.I4(\axlen_cnt_reg_n_0_[6] ),
.I5(\state_reg[0] ),
.O(\axlen_cnt[7]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\axlen_cnt[7]_i_3__0
(.I0(\axlen_cnt_reg_n_0_[5] ),
.I1(\axlen_cnt_reg_n_0_[3] ),
.I2(Q[1]),
.I3(Q[0]),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(\axlen_cnt_reg_n_0_[4] ),
.O(\axlen_cnt[7]_i_3__0_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(D[0]),
.Q(Q[0]),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(D[1]),
.Q(Q[1]),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[2]_i_1__1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[3]_i_1__1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
FDRE \axlen_cnt_reg[4]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[4]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[4] ),
.R(1'b0));
FDRE \axlen_cnt_reg[5]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[5]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[5] ),
.R(1'b0));
FDRE \axlen_cnt_reg[6]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[6]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[6] ),
.R(1'b0));
FDRE \axlen_cnt_reg[7]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[7]_i_2__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[7] ),
.R(1'b0));
LUT4 #(
.INIT(16'hEF40))
\m_axi_araddr[2]_INST_0_i_1
(.I0(\axaddr_incr_reg[11]_1 ),
.I1(\axaddr_incr_reg[3]_0 [2]),
.I2(\m_payload_i_reg[51] [7]),
.I3(\m_payload_i_reg[51] [2]),
.O(\m_axi_araddr[2] ));
LUT4 #(
.INIT(16'hEF40))
\m_axi_araddr[5]_INST_0_i_1
(.I0(\axaddr_incr_reg[11]_1 ),
.I1(axaddr_incr_reg),
.I2(\m_payload_i_reg[51] [7]),
.I3(\m_payload_i_reg[51] [4]),
.O(\m_axi_araddr[5] ));
LUT4 #(
.INIT(16'h0001))
next_pending_r_i_3__1
(.I0(\axlen_cnt_reg_n_0_[4] ),
.I1(\axlen_cnt_reg_n_0_[5] ),
.I2(\axlen_cnt_reg_n_0_[3] ),
.I3(next_pending_r_i_4__0_n_0),
.O(next_pending_r_reg_1));
LUT4 #(
.INIT(16'hFFFE))
next_pending_r_i_4__0
(.I0(Q[1]),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[6] ),
.I3(\axlen_cnt_reg_n_0_[7] ),
.O(next_pending_r_i_4__0_n_0));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(incr_next_pending),
.Q(next_pending_r_reg_0),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_1),
.Q(\axaddr_incr_reg[11]_1 ),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_r_channel" *)
module zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_r_channel
(\state_reg[1]_rep ,
m_axi_rready,
m_valid_i_reg,
out,
\skid_buffer_reg[46] ,
\state_reg[1]_rep_0 ,
aclk,
r_rlast,
s_ready_i_reg,
si_rs_rready,
m_axi_rvalid,
in,
areset_d1,
D);
output \state_reg[1]_rep ;
output m_axi_rready;
output m_valid_i_reg;
output [33:0]out;
output [12:0]\skid_buffer_reg[46] ;
input \state_reg[1]_rep_0 ;
input aclk;
input r_rlast;
input s_ready_i_reg;
input si_rs_rready;
input m_axi_rvalid;
input [33:0]in;
input areset_d1;
input [11:0]D;
wire [11:0]D;
wire aclk;
wire areset_d1;
wire [33:0]in;
wire m_axi_rready;
wire m_axi_rvalid;
wire m_valid_i_reg;
wire [33:0]out;
wire r_push_r;
wire r_rlast;
wire rd_data_fifo_0_n_0;
wire rd_data_fifo_0_n_2;
wire rd_data_fifo_0_n_3;
wire rd_data_fifo_0_n_5;
wire s_ready_i_reg;
wire si_rs_rready;
wire [12:0]\skid_buffer_reg[46] ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire [12:0]trans_in;
wire transaction_fifo_0_n_1;
wire wr_en0;
FDRE \r_arid_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(D[0]),
.Q(trans_in[1]),
.R(1'b0));
FDRE \r_arid_r_reg[10]
(.C(aclk),
.CE(1'b1),
.D(D[10]),
.Q(trans_in[11]),
.R(1'b0));
FDRE \r_arid_r_reg[11]
(.C(aclk),
.CE(1'b1),
.D(D[11]),
.Q(trans_in[12]),
.R(1'b0));
FDRE \r_arid_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(D[1]),
.Q(trans_in[2]),
.R(1'b0));
FDRE \r_arid_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(D[2]),
.Q(trans_in[3]),
.R(1'b0));
FDRE \r_arid_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(D[3]),
.Q(trans_in[4]),
.R(1'b0));
FDRE \r_arid_r_reg[4]
(.C(aclk),
.CE(1'b1),
.D(D[4]),
.Q(trans_in[5]),
.R(1'b0));
FDRE \r_arid_r_reg[5]
(.C(aclk),
.CE(1'b1),
.D(D[5]),
.Q(trans_in[6]),
.R(1'b0));
FDRE \r_arid_r_reg[6]
(.C(aclk),
.CE(1'b1),
.D(D[6]),
.Q(trans_in[7]),
.R(1'b0));
FDRE \r_arid_r_reg[7]
(.C(aclk),
.CE(1'b1),
.D(D[7]),
.Q(trans_in[8]),
.R(1'b0));
FDRE \r_arid_r_reg[8]
(.C(aclk),
.CE(1'b1),
.D(D[8]),
.Q(trans_in[9]),
.R(1'b0));
FDRE \r_arid_r_reg[9]
(.C(aclk),
.CE(1'b1),
.D(D[9]),
.Q(trans_in[10]),
.R(1'b0));
FDRE r_push_r_reg
(.C(aclk),
.CE(1'b1),
.D(\state_reg[1]_rep_0 ),
.Q(r_push_r),
.R(1'b0));
FDRE r_rlast_r_reg
(.C(aclk),
.CE(1'b1),
.D(r_rlast),
.Q(trans_in[0]),
.R(1'b0));
zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1 rd_data_fifo_0
(.aclk(aclk),
.areset_d1(areset_d1),
.\cnt_read_reg[3]_rep__2_0 (rd_data_fifo_0_n_0),
.\cnt_read_reg[4]_rep__0_0 (m_valid_i_reg),
.\cnt_read_reg[4]_rep__2_0 (rd_data_fifo_0_n_2),
.\cnt_read_reg[4]_rep__2_1 (rd_data_fifo_0_n_3),
.in(in),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.out(out),
.s_ready_i_reg(s_ready_i_reg),
.s_ready_i_reg_0(transaction_fifo_0_n_1),
.si_rs_rready(si_rs_rready),
.\state_reg[1]_rep (rd_data_fifo_0_n_5),
.wr_en0(wr_en0));
zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2 transaction_fifo_0
(.aclk(aclk),
.areset_d1(areset_d1),
.\cnt_read_reg[0]_rep__2 (rd_data_fifo_0_n_5),
.\cnt_read_reg[0]_rep__2_0 (rd_data_fifo_0_n_3),
.\cnt_read_reg[3]_rep__2 (rd_data_fifo_0_n_0),
.\cnt_read_reg[4]_rep__2 (transaction_fifo_0_n_1),
.\cnt_read_reg[4]_rep__2_0 (rd_data_fifo_0_n_2),
.in(trans_in),
.m_valid_i_reg(m_valid_i_reg),
.r_push_r(r_push_r),
.s_ready_i_reg(s_ready_i_reg),
.si_rs_rready(si_rs_rready),
.\skid_buffer_reg[46] (\skid_buffer_reg[46] ),
.\state_reg[1]_rep (\state_reg[1]_rep ),
.wr_en0(wr_en0));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm" *)
module zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm
(\axlen_cnt_reg[1] ,
Q,
D,
wrap_second_len,
r_push_r_reg,
\m_payload_i_reg[0] ,
\m_payload_i_reg[0]_0 ,
\axlen_cnt_reg[1]_0 ,
E,
\axaddr_offset_r_reg[3] ,
s_axburst_eq0_reg,
sel_first_i,
incr_next_pending,
s_axburst_eq1_reg,
\axaddr_wrap_reg[11] ,
\axaddr_incr_reg[11] ,
m_axi_arvalid,
\m_payload_i_reg[0]_1 ,
sel_first_reg,
sel_first_reg_0,
si_rs_arvalid,
\axlen_cnt_reg[4] ,
\m_payload_i_reg[44] ,
m_axi_arready,
s_axburst_eq1_reg_0,
\cnt_read_reg[2]_rep__0 ,
\m_payload_i_reg[47] ,
\axlen_cnt_reg[1]_1 ,
\wrap_second_len_r_reg[1] ,
axaddr_offset,
wrap_next_pending,
\m_payload_i_reg[51] ,
next_pending_r_reg,
areset_d1,
sel_first_reg_1,
\axaddr_offset_r_reg[3]_0 ,
\m_payload_i_reg[6] ,
sel_first_reg_2,
sel_first_reg_3,
aclk);
output \axlen_cnt_reg[1] ;
output [1:0]Q;
output [0:0]D;
output [0:0]wrap_second_len;
output r_push_r_reg;
output \m_payload_i_reg[0] ;
output \m_payload_i_reg[0]_0 ;
output [1:0]\axlen_cnt_reg[1]_0 ;
output [0:0]E;
output [0:0]\axaddr_offset_r_reg[3] ;
output s_axburst_eq0_reg;
output sel_first_i;
output incr_next_pending;
output s_axburst_eq1_reg;
output [0:0]\axaddr_wrap_reg[11] ;
output \axaddr_incr_reg[11] ;
output m_axi_arvalid;
output [0:0]\m_payload_i_reg[0]_1 ;
output sel_first_reg;
output sel_first_reg_0;
input si_rs_arvalid;
input \axlen_cnt_reg[4] ;
input \m_payload_i_reg[44] ;
input m_axi_arready;
input s_axburst_eq1_reg_0;
input \cnt_read_reg[2]_rep__0 ;
input [3:0]\m_payload_i_reg[47] ;
input [1:0]\axlen_cnt_reg[1]_1 ;
input [0:0]\wrap_second_len_r_reg[1] ;
input [2:0]axaddr_offset;
input wrap_next_pending;
input \m_payload_i_reg[51] ;
input next_pending_r_reg;
input areset_d1;
input sel_first_reg_1;
input [0:0]\axaddr_offset_r_reg[3]_0 ;
input \m_payload_i_reg[6] ;
input sel_first_reg_2;
input sel_first_reg_3;
input aclk;
wire [0:0]D;
wire [0:0]E;
wire [1:0]Q;
wire aclk;
wire areset_d1;
wire \axaddr_incr_reg[11] ;
wire [2:0]axaddr_offset;
wire [0:0]\axaddr_offset_r_reg[3] ;
wire [0:0]\axaddr_offset_r_reg[3]_0 ;
wire [0:0]\axaddr_wrap_reg[11] ;
wire \axlen_cnt_reg[1] ;
wire [1:0]\axlen_cnt_reg[1]_0 ;
wire [1:0]\axlen_cnt_reg[1]_1 ;
wire \axlen_cnt_reg[4] ;
wire \cnt_read_reg[2]_rep__0 ;
wire incr_next_pending;
wire m_axi_arready;
wire m_axi_arvalid;
wire \m_payload_i_reg[0] ;
wire \m_payload_i_reg[0]_0 ;
wire [0:0]\m_payload_i_reg[0]_1 ;
wire \m_payload_i_reg[44] ;
wire [3:0]\m_payload_i_reg[47] ;
wire \m_payload_i_reg[51] ;
wire \m_payload_i_reg[6] ;
wire next_pending_r_reg;
wire [1:0]next_state;
wire r_push_r_reg;
wire s_axburst_eq0_reg;
wire s_axburst_eq1_reg;
wire s_axburst_eq1_reg_0;
wire sel_first_i;
wire sel_first_reg;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire sel_first_reg_3;
wire si_rs_arvalid;
wire wrap_next_pending;
wire [0:0]wrap_second_len;
wire [0:0]\wrap_second_len_r_reg[1] ;
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'hAAEA))
\axaddr_incr[0]_i_1__0
(.I0(sel_first_reg_2),
.I1(m_axi_arready),
.I2(\m_payload_i_reg[0]_0 ),
.I3(\m_payload_i_reg[0] ),
.O(\axaddr_incr_reg[11] ));
LUT6 #(
.INIT(64'hAAAAACAAAAAAA0AA))
\axaddr_offset_r[3]_i_1__0
(.I0(\axaddr_offset_r_reg[3]_0 ),
.I1(\m_payload_i_reg[47] [3]),
.I2(\m_payload_i_reg[0]_0 ),
.I3(si_rs_arvalid),
.I4(\m_payload_i_reg[0] ),
.I5(\m_payload_i_reg[6] ),
.O(\axaddr_offset_r_reg[3] ));
LUT6 #(
.INIT(64'h0400FFFF04000400))
\axlen_cnt[0]_i_1__1
(.I0(Q[1]),
.I1(si_rs_arvalid),
.I2(Q[0]),
.I3(\m_payload_i_reg[47] [1]),
.I4(\axlen_cnt_reg[1]_1 [0]),
.I5(\axlen_cnt_reg[1] ),
.O(\axlen_cnt_reg[1]_0 [0]));
LUT5 #(
.INIT(32'hF88F8888))
\axlen_cnt[1]_i_1__1
(.I0(E),
.I1(\m_payload_i_reg[47] [2]),
.I2(\axlen_cnt_reg[1]_1 [1]),
.I3(\axlen_cnt_reg[1]_1 [0]),
.I4(\axlen_cnt_reg[1] ),
.O(\axlen_cnt_reg[1]_0 [1]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h00CA))
\axlen_cnt[7]_i_1__0
(.I0(si_rs_arvalid),
.I1(m_axi_arready),
.I2(\m_payload_i_reg[0]_0 ),
.I3(\m_payload_i_reg[0] ),
.O(\axaddr_wrap_reg[11] ));
LUT4 #(
.INIT(16'h00FB))
\axlen_cnt[7]_i_4__0
(.I0(Q[0]),
.I1(si_rs_arvalid),
.I2(Q[1]),
.I3(\axlen_cnt_reg[4] ),
.O(\axlen_cnt_reg[1] ));
LUT2 #(
.INIT(4'h2))
m_axi_arvalid_INST_0
(.I0(\m_payload_i_reg[0]_0 ),
.I1(\m_payload_i_reg[0] ),
.O(m_axi_arvalid));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hD5))
\m_payload_i[31]_i_1__0
(.I0(si_rs_arvalid),
.I1(\m_payload_i_reg[0] ),
.I2(\m_payload_i_reg[0]_0 ),
.O(\m_payload_i_reg[0]_1 ));
LUT5 #(
.INIT(32'h8BBB8B88))
next_pending_r_i_1__2
(.I0(\m_payload_i_reg[51] ),
.I1(E),
.I2(\axlen_cnt_reg[4] ),
.I3(r_push_r_reg),
.I4(next_pending_r_reg),
.O(incr_next_pending));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'h40))
r_push_r_i_1
(.I0(\m_payload_i_reg[0] ),
.I1(\m_payload_i_reg[0]_0 ),
.I2(m_axi_arready),
.O(r_push_r_reg));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'hFB08))
s_axburst_eq0_i_1__0
(.I0(wrap_next_pending),
.I1(\m_payload_i_reg[47] [0]),
.I2(sel_first_i),
.I3(incr_next_pending),
.O(s_axburst_eq0_reg));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'hABA8))
s_axburst_eq1_i_1__0
(.I0(wrap_next_pending),
.I1(\m_payload_i_reg[47] [0]),
.I2(sel_first_i),
.I3(incr_next_pending),
.O(s_axburst_eq1_reg));
LUT6 #(
.INIT(64'hFCFFFFFFCCCECCCE))
sel_first_i_1__0
(.I0(si_rs_arvalid),
.I1(areset_d1),
.I2(\m_payload_i_reg[0] ),
.I3(\m_payload_i_reg[0]_0 ),
.I4(m_axi_arready),
.I5(sel_first_reg_1),
.O(sel_first_i));
LUT6 #(
.INIT(64'hFFFFFFFFC4C4CFCC))
sel_first_i_1__3
(.I0(m_axi_arready),
.I1(sel_first_reg_2),
.I2(Q[1]),
.I3(si_rs_arvalid),
.I4(Q[0]),
.I5(areset_d1),
.O(sel_first_reg));
LUT6 #(
.INIT(64'hFFFFFFFFC4C4CFCC))
sel_first_i_1__4
(.I0(m_axi_arready),
.I1(sel_first_reg_3),
.I2(Q[1]),
.I3(si_rs_arvalid),
.I4(Q[0]),
.I5(areset_d1),
.O(sel_first_reg_0));
LUT6 #(
.INIT(64'h003030303E3E3E3E))
\state[0]_i_1__0
(.I0(si_rs_arvalid),
.I1(Q[1]),
.I2(Q[0]),
.I3(m_axi_arready),
.I4(s_axburst_eq1_reg_0),
.I5(\cnt_read_reg[2]_rep__0 ),
.O(next_state[0]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h00AAB000))
\state[1]_i_1
(.I0(\cnt_read_reg[2]_rep__0 ),
.I1(s_axburst_eq1_reg_0),
.I2(m_axi_arready),
.I3(\m_payload_i_reg[0]_0 ),
.I4(\m_payload_i_reg[0] ),
.O(next_state[1]));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[0]" *)
FDRE #(
.INIT(1'b0))
\state_reg[0]
(.C(aclk),
.CE(1'b1),
.D(next_state[0]),
.Q(Q[0]),
.R(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[0]" *)
FDRE #(
.INIT(1'b0))
\state_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(next_state[0]),
.Q(\m_payload_i_reg[0]_0 ),
.R(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[1]" *)
FDRE #(
.INIT(1'b0))
\state_reg[1]
(.C(aclk),
.CE(1'b1),
.D(next_state[1]),
.Q(Q[1]),
.R(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[1]" *)
FDRE #(
.INIT(1'b0))
\state_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(next_state[1]),
.Q(\m_payload_i_reg[0] ),
.R(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'h04))
\wrap_boundary_axaddr_r[11]_i_1__0
(.I0(\m_payload_i_reg[0] ),
.I1(si_rs_arvalid),
.I2(\m_payload_i_reg[0]_0 ),
.O(E));
LUT2 #(
.INIT(4'h9))
\wrap_cnt_r[1]_i_1__0
(.I0(wrap_second_len),
.I1(\m_payload_i_reg[44] ),
.O(D));
LUT6 #(
.INIT(64'hFF0000FCAAAAAAAA))
\wrap_second_len_r[1]_i_1__0
(.I0(\wrap_second_len_r_reg[1] ),
.I1(axaddr_offset[2]),
.I2(\axaddr_offset_r_reg[3] ),
.I3(axaddr_offset[0]),
.I4(axaddr_offset[1]),
.I5(E),
.O(wrap_second_len));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_simple_fifo" *)
module zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo
(\cnt_read_reg[0]_rep__0_0 ,
\cnt_read_reg[1]_rep__1_0 ,
D,
\cnt_read_reg[0]_0 ,
sel,
SR,
bvalid_i_reg,
out,
b_push,
shandshake_r,
Q,
areset_d1,
\bresp_cnt_reg[7] ,
mhandshake_r,
bvalid_i_reg_0,
si_rs_bready,
in,
aclk);
output \cnt_read_reg[0]_rep__0_0 ;
output \cnt_read_reg[1]_rep__1_0 ;
output [0:0]D;
output \cnt_read_reg[0]_0 ;
output sel;
output [0:0]SR;
output bvalid_i_reg;
output [11:0]out;
input b_push;
input shandshake_r;
input [1:0]Q;
input areset_d1;
input [7:0]\bresp_cnt_reg[7] ;
input mhandshake_r;
input bvalid_i_reg_0;
input si_rs_bready;
input [19:0]in;
input aclk;
wire [0:0]D;
wire [1:0]Q;
wire [0:0]SR;
wire aclk;
wire areset_d1;
wire b_push;
wire [7:0]\bresp_cnt_reg[7] ;
wire bvalid_i_i_2_n_0;
wire bvalid_i_reg;
wire bvalid_i_reg_0;
wire [1:0]cnt_read;
wire \cnt_read[0]_i_1__2_n_0 ;
wire \cnt_read[1]_i_1_n_0 ;
wire \cnt_read_reg[0]_0 ;
wire \cnt_read_reg[0]_rep__0_0 ;
wire \cnt_read_reg[0]_rep_n_0 ;
wire \cnt_read_reg[1]_rep__0_n_0 ;
wire \cnt_read_reg[1]_rep__1_0 ;
wire \cnt_read_reg[1]_rep_n_0 ;
wire [19:0]in;
wire \memory_reg[3][0]_srl4_i_3_n_0 ;
wire \memory_reg[3][0]_srl4_i_4_n_0 ;
wire \memory_reg[3][0]_srl4_i_5_n_0 ;
wire \memory_reg[3][0]_srl4_i_6_n_0 ;
wire \memory_reg[3][0]_srl4_n_0 ;
wire \memory_reg[3][1]_srl4_n_0 ;
wire \memory_reg[3][2]_srl4_n_0 ;
wire \memory_reg[3][3]_srl4_n_0 ;
wire \memory_reg[3][4]_srl4_n_0 ;
wire \memory_reg[3][5]_srl4_n_0 ;
wire \memory_reg[3][6]_srl4_n_0 ;
wire \memory_reg[3][7]_srl4_n_0 ;
wire mhandshake_r;
wire [11:0]out;
wire sel;
wire shandshake_r;
wire si_rs_bready;
(* SOFT_HLUTNM = "soft_lutpair115" *)
LUT2 #(
.INIT(4'hB))
\bresp_cnt[7]_i_1
(.I0(areset_d1),
.I1(\cnt_read_reg[0]_0 ),
.O(SR));
(* SOFT_HLUTNM = "soft_lutpair115" *)
LUT4 #(
.INIT(16'h002A))
bvalid_i_i_1
(.I0(bvalid_i_i_2_n_0),
.I1(bvalid_i_reg_0),
.I2(si_rs_bready),
.I3(areset_d1),
.O(bvalid_i_reg));
LUT6 #(
.INIT(64'hFFFFFFFF00070707))
bvalid_i_i_2
(.I0(\cnt_read_reg[1]_rep__1_0 ),
.I1(\cnt_read_reg[0]_rep__0_0 ),
.I2(shandshake_r),
.I3(Q[1]),
.I4(Q[0]),
.I5(bvalid_i_reg_0),
.O(bvalid_i_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair117" *)
LUT3 #(
.INIT(8'h69))
\cnt_read[0]_i_1
(.I0(\cnt_read_reg[0]_0 ),
.I1(shandshake_r),
.I2(Q[0]),
.O(D));
(* SOFT_HLUTNM = "soft_lutpair116" *)
LUT3 #(
.INIT(8'h96))
\cnt_read[0]_i_1__2
(.I0(\cnt_read_reg[0]_rep__0_0 ),
.I1(b_push),
.I2(shandshake_r),
.O(\cnt_read[0]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair116" *)
LUT4 #(
.INIT(16'hE718))
\cnt_read[1]_i_1
(.I0(\cnt_read_reg[0]_rep__0_0 ),
.I1(b_push),
.I2(shandshake_r),
.I3(\cnt_read_reg[1]_rep__1_0 ),
.O(\cnt_read[1]_i_1_n_0 ));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__2_n_0 ),
.Q(cnt_read[0]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__2_n_0 ),
.Q(\cnt_read_reg[0]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__2_n_0 ),
.Q(\cnt_read_reg[0]_rep__0_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1_n_0 ),
.Q(cnt_read[1]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1_n_0 ),
.Q(\cnt_read_reg[1]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1_n_0 ),
.Q(\cnt_read_reg[1]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1_n_0 ),
.Q(\cnt_read_reg[1]_rep__1_0 ),
.S(areset_d1));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][0]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep__0_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[0]),
.Q(\memory_reg[3][0]_srl4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair117" *)
LUT1 #(
.INIT(2'h1))
\memory_reg[3][0]_srl4_i_1__0
(.I0(\cnt_read_reg[0]_0 ),
.O(sel));
LUT6 #(
.INIT(64'hFFFEFFFFFFFFFFFE))
\memory_reg[3][0]_srl4_i_2__0
(.I0(\memory_reg[3][0]_srl4_i_3_n_0 ),
.I1(\memory_reg[3][0]_srl4_i_4_n_0 ),
.I2(\memory_reg[3][0]_srl4_i_5_n_0 ),
.I3(\memory_reg[3][0]_srl4_i_6_n_0 ),
.I4(\bresp_cnt_reg[7] [3]),
.I5(\memory_reg[3][3]_srl4_n_0 ),
.O(\cnt_read_reg[0]_0 ));
LUT6 #(
.INIT(64'h22F2FFFFFFFF22F2))
\memory_reg[3][0]_srl4_i_3
(.I0(\memory_reg[3][0]_srl4_n_0 ),
.I1(\bresp_cnt_reg[7] [0]),
.I2(\memory_reg[3][2]_srl4_n_0 ),
.I3(\bresp_cnt_reg[7] [2]),
.I4(\memory_reg[3][1]_srl4_n_0 ),
.I5(\bresp_cnt_reg[7] [1]),
.O(\memory_reg[3][0]_srl4_i_3_n_0 ));
LUT6 #(
.INIT(64'hF222FFFFFFFFF222))
\memory_reg[3][0]_srl4_i_4
(.I0(\bresp_cnt_reg[7] [5]),
.I1(\memory_reg[3][5]_srl4_n_0 ),
.I2(\cnt_read_reg[1]_rep__1_0 ),
.I3(\cnt_read_reg[0]_rep__0_0 ),
.I4(\bresp_cnt_reg[7] [7]),
.I5(\memory_reg[3][7]_srl4_n_0 ),
.O(\memory_reg[3][0]_srl4_i_4_n_0 ));
LUT6 #(
.INIT(64'h2FF22FF2FFFF2FF2))
\memory_reg[3][0]_srl4_i_5
(.I0(\bresp_cnt_reg[7] [2]),
.I1(\memory_reg[3][2]_srl4_n_0 ),
.I2(\memory_reg[3][4]_srl4_n_0 ),
.I3(\bresp_cnt_reg[7] [4]),
.I4(\bresp_cnt_reg[7] [0]),
.I5(\memory_reg[3][0]_srl4_n_0 ),
.O(\memory_reg[3][0]_srl4_i_5_n_0 ));
LUT5 #(
.INIT(32'h6F6FFF6F))
\memory_reg[3][0]_srl4_i_6
(.I0(\memory_reg[3][6]_srl4_n_0 ),
.I1(\bresp_cnt_reg[7] [6]),
.I2(mhandshake_r),
.I3(\memory_reg[3][5]_srl4_n_0 ),
.I4(\bresp_cnt_reg[7] [5]),
.O(\memory_reg[3][0]_srl4_i_6_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][10]_srl4
(.A0(cnt_read[0]),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[10]),
.Q(out[2]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][11]_srl4
(.A0(cnt_read[0]),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[11]),
.Q(out[3]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][12]_srl4
(.A0(cnt_read[0]),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[12]),
.Q(out[4]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][13]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[13]),
.Q(out[5]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][14]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[14]),
.Q(out[6]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][15]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[15]),
.Q(out[7]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][16]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[16]),
.Q(out[8]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][17]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[17]),
.Q(out[9]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][18]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[18]),
.Q(out[10]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][19]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[19]),
.Q(out[11]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][1]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep__0_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[1]),
.Q(\memory_reg[3][1]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][2]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep__0_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[2]),
.Q(\memory_reg[3][2]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][3]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep__0_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[3]),
.Q(\memory_reg[3][3]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][4]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][4]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep__0_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[4]),
.Q(\memory_reg[3][4]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][5]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][5]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep__0_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[5]),
.Q(\memory_reg[3][5]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][6]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][6]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[6]),
.Q(\memory_reg[3][6]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][7]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][7]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[7]),
.Q(\memory_reg[3][7]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][8]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[8]),
.Q(out[0]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][9]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[9]),
.Q(out[1]));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_simple_fifo" *)
module zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0
(mhandshake,
Q,
m_axi_bready,
\skid_buffer_reg[1] ,
m_axi_bvalid,
mhandshake_r,
shandshake_r,
\bresp_cnt_reg[3] ,
sel,
in,
aclk,
areset_d1,
D);
output mhandshake;
output [1:0]Q;
output m_axi_bready;
output [1:0]\skid_buffer_reg[1] ;
input m_axi_bvalid;
input mhandshake_r;
input shandshake_r;
input \bresp_cnt_reg[3] ;
input sel;
input [1:0]in;
input aclk;
input areset_d1;
input [0:0]D;
wire [0:0]D;
wire [1:0]Q;
wire aclk;
wire areset_d1;
wire \bresp_cnt_reg[3] ;
wire \cnt_read[1]_i_1__0_n_0 ;
wire [1:0]in;
wire m_axi_bready;
wire m_axi_bvalid;
wire mhandshake;
wire mhandshake_r;
wire sel;
wire shandshake_r;
wire [1:0]\skid_buffer_reg[1] ;
(* SOFT_HLUTNM = "soft_lutpair118" *)
LUT4 #(
.INIT(16'hA69A))
\cnt_read[1]_i_1__0
(.I0(Q[1]),
.I1(shandshake_r),
.I2(Q[0]),
.I3(\bresp_cnt_reg[3] ),
.O(\cnt_read[1]_i_1__0_n_0 ));
(* KEEP = "yes" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(D),
.Q(Q[0]),
.S(areset_d1));
(* KEEP = "yes" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__0_n_0 ),
.Q(Q[1]),
.S(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair118" *)
LUT3 #(
.INIT(8'h08))
m_axi_bready_INST_0
(.I0(Q[1]),
.I1(Q[0]),
.I2(mhandshake_r),
.O(m_axi_bready));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][0]_srl4
(.A0(Q[0]),
.A1(Q[1]),
.A2(1'b0),
.A3(1'b0),
.CE(sel),
.CLK(aclk),
.D(in[0]),
.Q(\skid_buffer_reg[1] [0]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][1]_srl4
(.A0(Q[0]),
.A1(Q[1]),
.A2(1'b0),
.A3(1'b0),
.CE(sel),
.CLK(aclk),
.D(in[1]),
.Q(\skid_buffer_reg[1] [1]));
LUT4 #(
.INIT(16'h2000))
mhandshake_r_i_1
(.I0(m_axi_bvalid),
.I1(mhandshake_r),
.I2(Q[0]),
.I3(Q[1]),
.O(mhandshake));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_simple_fifo" *)
module zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1
(\cnt_read_reg[3]_rep__2_0 ,
wr_en0,
\cnt_read_reg[4]_rep__2_0 ,
\cnt_read_reg[4]_rep__2_1 ,
m_axi_rready,
\state_reg[1]_rep ,
out,
s_ready_i_reg,
s_ready_i_reg_0,
si_rs_rready,
\cnt_read_reg[4]_rep__0_0 ,
m_axi_rvalid,
in,
aclk,
areset_d1);
output \cnt_read_reg[3]_rep__2_0 ;
output wr_en0;
output \cnt_read_reg[4]_rep__2_0 ;
output \cnt_read_reg[4]_rep__2_1 ;
output m_axi_rready;
output \state_reg[1]_rep ;
output [33:0]out;
input s_ready_i_reg;
input s_ready_i_reg_0;
input si_rs_rready;
input \cnt_read_reg[4]_rep__0_0 ;
input m_axi_rvalid;
input [33:0]in;
input aclk;
input areset_d1;
wire aclk;
wire areset_d1;
wire [4:0]cnt_read;
wire \cnt_read[0]_i_1__0_n_0 ;
wire \cnt_read[1]_i_1__2_n_0 ;
wire \cnt_read[2]_i_1_n_0 ;
wire \cnt_read[3]_i_1_n_0 ;
wire \cnt_read[4]_i_1_n_0 ;
wire \cnt_read[4]_i_2_n_0 ;
wire \cnt_read[4]_i_3_n_0 ;
wire \cnt_read_reg[0]_rep__0_n_0 ;
wire \cnt_read_reg[0]_rep__1_n_0 ;
wire \cnt_read_reg[0]_rep__2_n_0 ;
wire \cnt_read_reg[0]_rep_n_0 ;
wire \cnt_read_reg[1]_rep__0_n_0 ;
wire \cnt_read_reg[1]_rep__1_n_0 ;
wire \cnt_read_reg[1]_rep__2_n_0 ;
wire \cnt_read_reg[1]_rep_n_0 ;
wire \cnt_read_reg[2]_rep__0_n_0 ;
wire \cnt_read_reg[2]_rep__1_n_0 ;
wire \cnt_read_reg[2]_rep__2_n_0 ;
wire \cnt_read_reg[2]_rep_n_0 ;
wire \cnt_read_reg[3]_rep__0_n_0 ;
wire \cnt_read_reg[3]_rep__1_n_0 ;
wire \cnt_read_reg[3]_rep__2_0 ;
wire \cnt_read_reg[3]_rep_n_0 ;
wire \cnt_read_reg[4]_rep__0_0 ;
wire \cnt_read_reg[4]_rep__0_n_0 ;
wire \cnt_read_reg[4]_rep__1_n_0 ;
wire \cnt_read_reg[4]_rep__2_0 ;
wire \cnt_read_reg[4]_rep__2_1 ;
wire \cnt_read_reg[4]_rep_n_0 ;
wire [33:0]in;
wire m_axi_rready;
wire m_axi_rvalid;
wire [33:0]out;
wire s_ready_i_reg;
wire s_ready_i_reg_0;
wire si_rs_rready;
wire \state_reg[1]_rep ;
wire wr_en0;
wire \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ;
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'h96))
\cnt_read[0]_i_1__0
(.I0(\cnt_read_reg[0]_rep__2_n_0 ),
.I1(s_ready_i_reg),
.I2(wr_en0),
.O(\cnt_read[0]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'hA96A))
\cnt_read[1]_i_1__2
(.I0(\cnt_read_reg[1]_rep__2_n_0 ),
.I1(\cnt_read_reg[0]_rep__2_n_0 ),
.I2(wr_en0),
.I3(s_ready_i_reg),
.O(\cnt_read[1]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'hA6AAAA9A))
\cnt_read[2]_i_1
(.I0(\cnt_read_reg[2]_rep__2_n_0 ),
.I1(\cnt_read_reg[1]_rep__2_n_0 ),
.I2(s_ready_i_reg),
.I3(wr_en0),
.I4(\cnt_read_reg[0]_rep__2_n_0 ),
.O(\cnt_read[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAA96AAAAAAA))
\cnt_read[3]_i_1
(.I0(\cnt_read_reg[3]_rep__2_0 ),
.I1(\cnt_read_reg[2]_rep__2_n_0 ),
.I2(\cnt_read_reg[1]_rep__2_n_0 ),
.I3(\cnt_read_reg[0]_rep__2_n_0 ),
.I4(wr_en0),
.I5(s_ready_i_reg),
.O(\cnt_read[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAA55AAA6A6AAA6AA))
\cnt_read[4]_i_1
(.I0(\cnt_read_reg[4]_rep__2_0 ),
.I1(\cnt_read[4]_i_2_n_0 ),
.I2(\cnt_read[4]_i_3_n_0 ),
.I3(s_ready_i_reg_0),
.I4(\cnt_read_reg[4]_rep__2_1 ),
.I5(\cnt_read_reg[3]_rep__2_0 ),
.O(\cnt_read[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT2 #(
.INIT(4'h1))
\cnt_read[4]_i_2
(.I0(\cnt_read_reg[2]_rep__2_n_0 ),
.I1(\cnt_read_reg[1]_rep__2_n_0 ),
.O(\cnt_read[4]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'hFFFB))
\cnt_read[4]_i_3
(.I0(\cnt_read_reg[0]_rep__2_n_0 ),
.I1(si_rs_rready),
.I2(\cnt_read_reg[4]_rep__0_0 ),
.I3(wr_en0),
.O(\cnt_read[4]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'h80))
\cnt_read[4]_i_5
(.I0(\cnt_read_reg[0]_rep__2_n_0 ),
.I1(\cnt_read_reg[1]_rep__2_n_0 ),
.I2(\cnt_read_reg[2]_rep__2_n_0 ),
.O(\cnt_read_reg[4]_rep__2_1 ));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__0_n_0 ),
.Q(cnt_read[0]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__0_n_0 ),
.Q(\cnt_read_reg[0]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__0_n_0 ),
.Q(\cnt_read_reg[0]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__0_n_0 ),
.Q(\cnt_read_reg[0]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__0_n_0 ),
.Q(\cnt_read_reg[0]_rep__2_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(cnt_read[1]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(\cnt_read_reg[1]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(\cnt_read_reg[1]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(\cnt_read_reg[1]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(\cnt_read_reg[1]_rep__2_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(cnt_read[2]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep__2_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(cnt_read[3]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(\cnt_read_reg[3]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(\cnt_read_reg[3]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(\cnt_read_reg[3]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(\cnt_read_reg[3]_rep__2_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(cnt_read[4]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep__2_0 ),
.S(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'hF77F777F))
m_axi_rready_INST_0
(.I0(\cnt_read_reg[3]_rep__2_0 ),
.I1(\cnt_read_reg[4]_rep__2_0 ),
.I2(\cnt_read_reg[1]_rep__2_n_0 ),
.I3(\cnt_read_reg[2]_rep__2_n_0 ),
.I4(\cnt_read_reg[0]_rep__2_n_0 ),
.O(m_axi_rready));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][0]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[0]),
.Q(out[0]),
.Q31(\NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ));
LUT6 #(
.INIT(64'hAA2A2AAA2A2A2AAA))
\memory_reg[31][0]_srl32_i_1
(.I0(m_axi_rvalid),
.I1(\cnt_read_reg[3]_rep__2_0 ),
.I2(\cnt_read_reg[4]_rep__2_0 ),
.I3(\cnt_read_reg[1]_rep__2_n_0 ),
.I4(\cnt_read_reg[2]_rep__2_n_0 ),
.I5(\cnt_read_reg[0]_rep__2_n_0 ),
.O(wr_en0));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][10]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[10]),
.Q(out[10]),
.Q31(\NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][11]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[11]),
.Q(out[11]),
.Q31(\NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][12]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[12]),
.Q(out[12]),
.Q31(\NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][13]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[13]),
.Q(out[13]),
.Q31(\NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][14]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[14]),
.Q(out[14]),
.Q31(\NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][15]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[15]),
.Q(out[15]),
.Q31(\NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][16]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[16]),
.Q(out[16]),
.Q31(\NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][17]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[17]),
.Q(out[17]),
.Q31(\NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][18]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[18]),
.Q(out[18]),
.Q31(\NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][19]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[19]),
.Q(out[19]),
.Q31(\NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][1]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[1]),
.Q(out[1]),
.Q31(\NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][20]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[20]),
.Q(out[20]),
.Q31(\NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][21]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[21]),
.Q(out[21]),
.Q31(\NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][22]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[22]),
.Q(out[22]),
.Q31(\NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][23]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[23]),
.Q(out[23]),
.Q31(\NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][24]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[24]),
.Q(out[24]),
.Q31(\NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][25]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[25]),
.Q(out[25]),
.Q31(\NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][26]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[26]),
.Q(out[26]),
.Q31(\NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][27]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[27]),
.Q(out[27]),
.Q31(\NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][28]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[28]),
.Q(out[28]),
.Q31(\NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][29]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[29]),
.Q(out[29]),
.Q31(\NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][2]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[2]),
.Q(out[2]),
.Q31(\NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][30]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[30]),
.Q(out[30]),
.Q31(\NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][31]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[31]),
.Q(out[31]),
.Q31(\NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][32]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[32]),
.Q(out[32]),
.Q31(\NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][33]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[33]),
.Q(out[33]),
.Q31(\NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][3]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[3]),
.Q(out[3]),
.Q31(\NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][4]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[4]),
.Q(out[4]),
.Q31(\NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][5]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[5]),
.Q(out[5]),
.Q31(\NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][6]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[6]),
.Q(out[6]),
.Q31(\NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][7]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[7]),
.Q(out[7]),
.Q31(\NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][8]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[8]),
.Q(out[8]),
.Q31(\NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][9]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[9]),
.Q(out[9]),
.Q31(\NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'h7C000000))
\state[1]_i_4
(.I0(\cnt_read_reg[0]_rep__2_n_0 ),
.I1(\cnt_read_reg[2]_rep__2_n_0 ),
.I2(\cnt_read_reg[1]_rep__2_n_0 ),
.I3(\cnt_read_reg[4]_rep__2_0 ),
.I4(\cnt_read_reg[3]_rep__2_0 ),
.O(\state_reg[1]_rep ));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_simple_fifo" *)
module zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2
(\state_reg[1]_rep ,
\cnt_read_reg[4]_rep__2 ,
m_valid_i_reg,
\skid_buffer_reg[46] ,
r_push_r,
s_ready_i_reg,
\cnt_read_reg[0]_rep__2 ,
si_rs_rready,
wr_en0,
\cnt_read_reg[4]_rep__2_0 ,
\cnt_read_reg[3]_rep__2 ,
\cnt_read_reg[0]_rep__2_0 ,
in,
aclk,
areset_d1);
output \state_reg[1]_rep ;
output \cnt_read_reg[4]_rep__2 ;
output m_valid_i_reg;
output [12:0]\skid_buffer_reg[46] ;
input r_push_r;
input s_ready_i_reg;
input \cnt_read_reg[0]_rep__2 ;
input si_rs_rready;
input wr_en0;
input \cnt_read_reg[4]_rep__2_0 ;
input \cnt_read_reg[3]_rep__2 ;
input \cnt_read_reg[0]_rep__2_0 ;
input [12:0]in;
input aclk;
input areset_d1;
wire aclk;
wire areset_d1;
wire [4:0]cnt_read;
wire \cnt_read[0]_i_1__1_n_0 ;
wire \cnt_read[1]_i_1__1_n_0 ;
wire \cnt_read[2]_i_1__0_n_0 ;
wire \cnt_read[3]_i_1__0_n_0 ;
wire \cnt_read[4]_i_1__0_n_0 ;
wire \cnt_read[4]_i_2__0_n_0 ;
wire \cnt_read[4]_i_3__0_n_0 ;
wire \cnt_read[4]_i_4__0_n_0 ;
wire \cnt_read[4]_i_5__0_n_0 ;
wire \cnt_read_reg[0]_rep__0_n_0 ;
wire \cnt_read_reg[0]_rep__2 ;
wire \cnt_read_reg[0]_rep__2_0 ;
wire \cnt_read_reg[0]_rep_n_0 ;
wire \cnt_read_reg[1]_rep__0_n_0 ;
wire \cnt_read_reg[1]_rep_n_0 ;
wire \cnt_read_reg[2]_rep__0_n_0 ;
wire \cnt_read_reg[2]_rep_n_0 ;
wire \cnt_read_reg[3]_rep__0_n_0 ;
wire \cnt_read_reg[3]_rep__2 ;
wire \cnt_read_reg[3]_rep_n_0 ;
wire \cnt_read_reg[4]_rep__0_n_0 ;
wire \cnt_read_reg[4]_rep__2 ;
wire \cnt_read_reg[4]_rep__2_0 ;
wire \cnt_read_reg[4]_rep_n_0 ;
wire [12:0]in;
wire m_valid_i_reg;
wire r_push_r;
wire s_ready_i_reg;
wire si_rs_rready;
wire [12:0]\skid_buffer_reg[46] ;
wire \state_reg[1]_rep ;
wire wr_en0;
wire \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ;
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'h96))
\cnt_read[0]_i_1__1
(.I0(\cnt_read_reg[0]_rep__0_n_0 ),
.I1(s_ready_i_reg),
.I2(r_push_r),
.O(\cnt_read[0]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'hA69A))
\cnt_read[1]_i_1__1
(.I0(\cnt_read_reg[1]_rep__0_n_0 ),
.I1(\cnt_read_reg[0]_rep__0_n_0 ),
.I2(s_ready_i_reg),
.I3(r_push_r),
.O(\cnt_read[1]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT5 #(
.INIT(32'hAA6AA9AA))
\cnt_read[2]_i_1__0
(.I0(\cnt_read_reg[2]_rep__0_n_0 ),
.I1(\cnt_read_reg[1]_rep__0_n_0 ),
.I2(r_push_r),
.I3(s_ready_i_reg),
.I4(\cnt_read_reg[0]_rep__0_n_0 ),
.O(\cnt_read[2]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hAAAA6AAAAAA9AAAA))
\cnt_read[3]_i_1__0
(.I0(\cnt_read_reg[3]_rep__0_n_0 ),
.I1(\cnt_read_reg[2]_rep__0_n_0 ),
.I2(\cnt_read_reg[1]_rep__0_n_0 ),
.I3(r_push_r),
.I4(s_ready_i_reg),
.I5(\cnt_read_reg[0]_rep__0_n_0 ),
.O(\cnt_read[3]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h6A666A6AAA99AAAA))
\cnt_read[4]_i_1__0
(.I0(\cnt_read_reg[4]_rep__0_n_0 ),
.I1(\cnt_read[4]_i_2__0_n_0 ),
.I2(\cnt_read[4]_i_3__0_n_0 ),
.I3(\cnt_read[4]_i_4__0_n_0 ),
.I4(\cnt_read[4]_i_5__0_n_0 ),
.I5(\cnt_read_reg[3]_rep__0_n_0 ),
.O(\cnt_read[4]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'h8A))
\cnt_read[4]_i_2__0
(.I0(r_push_r),
.I1(m_valid_i_reg),
.I2(si_rs_rready),
.O(\cnt_read[4]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'h80))
\cnt_read[4]_i_3__0
(.I0(\cnt_read_reg[2]_rep__0_n_0 ),
.I1(\cnt_read_reg[1]_rep__0_n_0 ),
.I2(\cnt_read_reg[0]_rep__0_n_0 ),
.O(\cnt_read[4]_i_3__0_n_0 ));
LUT3 #(
.INIT(8'h4F))
\cnt_read[4]_i_4
(.I0(m_valid_i_reg),
.I1(si_rs_rready),
.I2(wr_en0),
.O(\cnt_read_reg[4]_rep__2 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'hFFFB))
\cnt_read[4]_i_4__0
(.I0(\cnt_read_reg[0]_rep__0_n_0 ),
.I1(si_rs_rready),
.I2(m_valid_i_reg),
.I3(r_push_r),
.O(\cnt_read[4]_i_4__0_n_0 ));
LUT2 #(
.INIT(4'h1))
\cnt_read[4]_i_5__0
(.I0(\cnt_read_reg[1]_rep__0_n_0 ),
.I1(\cnt_read_reg[2]_rep__0_n_0 ),
.O(\cnt_read[4]_i_5__0_n_0 ));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(cnt_read[0]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(\cnt_read_reg[0]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(\cnt_read_reg[0]_rep__0_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__1_n_0 ),
.Q(cnt_read[1]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__1_n_0 ),
.Q(\cnt_read_reg[1]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__1_n_0 ),
.Q(\cnt_read_reg[1]_rep__0_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1__0_n_0 ),
.Q(cnt_read[2]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1__0_n_0 ),
.Q(\cnt_read_reg[2]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1__0_n_0 ),
.Q(\cnt_read_reg[2]_rep__0_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(cnt_read[3]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(\cnt_read_reg[3]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(\cnt_read_reg[3]_rep__0_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1__0_n_0 ),
.Q(cnt_read[4]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1__0_n_0 ),
.Q(\cnt_read_reg[4]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1__0_n_0 ),
.Q(\cnt_read_reg[4]_rep__0_n_0 ),
.S(areset_d1));
LUT6 #(
.INIT(64'hFF80808080808080))
m_valid_i_i_2
(.I0(\cnt_read_reg[4]_rep__0_n_0 ),
.I1(\cnt_read_reg[3]_rep__0_n_0 ),
.I2(\cnt_read[4]_i_3__0_n_0 ),
.I3(\cnt_read_reg[4]_rep__2_0 ),
.I4(\cnt_read_reg[3]_rep__2 ),
.I5(\cnt_read_reg[0]_rep__2_0 ),
.O(m_valid_i_reg));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][0]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[0]),
.Q(\skid_buffer_reg[46] [0]),
.Q31(\NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][10]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[10]),
.Q(\skid_buffer_reg[46] [10]),
.Q31(\NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][11]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[11]),
.Q(\skid_buffer_reg[46] [11]),
.Q31(\NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][12]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[12]),
.Q(\skid_buffer_reg[46] [12]),
.Q31(\NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][1]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[1]),
.Q(\skid_buffer_reg[46] [1]),
.Q31(\NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][2]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[2]),
.Q(\skid_buffer_reg[46] [2]),
.Q31(\NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][3]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[3]),
.Q(\skid_buffer_reg[46] [3]),
.Q31(\NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][4]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[4]),
.Q(\skid_buffer_reg[46] [4]),
.Q31(\NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][5]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[5]),
.Q(\skid_buffer_reg[46] [5]),
.Q31(\NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][6]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[6]),
.Q(\skid_buffer_reg[46] [6]),
.Q31(\NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][7]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[7]),
.Q(\skid_buffer_reg[46] [7]),
.Q31(\NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][8]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[8]),
.Q(\skid_buffer_reg[46] [8]),
.Q31(\NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][9]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[9]),
.Q(\skid_buffer_reg[46] [9]),
.Q31(\NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ));
LUT6 #(
.INIT(64'hBEFEAAAAAAAAAAAA))
\state[1]_i_2
(.I0(\cnt_read_reg[0]_rep__2 ),
.I1(\cnt_read_reg[2]_rep__0_n_0 ),
.I2(\cnt_read_reg[1]_rep__0_n_0 ),
.I3(\cnt_read_reg[0]_rep__0_n_0 ),
.I4(\cnt_read_reg[3]_rep__0_n_0 ),
.I5(\cnt_read_reg[4]_rep__0_n_0 ),
.O(\state_reg[1]_rep ));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm" *)
module zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm
(\axlen_cnt_reg[4] ,
Q,
D,
\wrap_second_len_r_reg[1] ,
\state_reg[1]_rep_0 ,
\state_reg[1]_rep_1 ,
\axlen_cnt_reg[5] ,
E,
\axaddr_offset_r_reg[3] ,
s_axburst_eq0_reg,
wrap_next_pending,
sel_first_i,
incr_next_pending,
s_axburst_eq1_reg,
next,
\m_payload_i_reg[0] ,
\axaddr_wrap_reg[0] ,
\axaddr_incr_reg[11] ,
\m_payload_i_reg[0]_0 ,
m_axi_awvalid,
sel_first_reg,
sel_first_reg_0,
si_rs_awvalid,
\axlen_cnt_reg[3] ,
\m_payload_i_reg[44] ,
s_axburst_eq1_reg_0,
\cnt_read_reg[1]_rep__1 ,
\cnt_read_reg[0]_rep__0 ,
m_axi_awready,
\m_payload_i_reg[49] ,
\axlen_cnt_reg[5]_0 ,
\axlen_cnt_reg[3]_0 ,
\axlen_cnt_reg[4]_0 ,
\wrap_second_len_r_reg[1]_0 ,
\m_payload_i_reg[35] ,
\m_payload_i_reg[48] ,
next_pending_r_reg,
areset_d1,
sel_first_reg_1,
\m_payload_i_reg[46] ,
\axlen_cnt_reg[2] ,
next_pending_r_reg_0,
\axaddr_offset_r_reg[3]_0 ,
\m_payload_i_reg[6] ,
sel_first_reg_2,
sel_first__0,
aclk);
output \axlen_cnt_reg[4] ;
output [1:0]Q;
output [0:0]D;
output [0:0]\wrap_second_len_r_reg[1] ;
output \state_reg[1]_rep_0 ;
output \state_reg[1]_rep_1 ;
output [3:0]\axlen_cnt_reg[5] ;
output [0:0]E;
output [0:0]\axaddr_offset_r_reg[3] ;
output s_axburst_eq0_reg;
output wrap_next_pending;
output sel_first_i;
output incr_next_pending;
output s_axburst_eq1_reg;
output next;
output \m_payload_i_reg[0] ;
output [0:0]\axaddr_wrap_reg[0] ;
output \axaddr_incr_reg[11] ;
output [0:0]\m_payload_i_reg[0]_0 ;
output m_axi_awvalid;
output sel_first_reg;
output sel_first_reg_0;
input si_rs_awvalid;
input \axlen_cnt_reg[3] ;
input \m_payload_i_reg[44] ;
input s_axburst_eq1_reg_0;
input \cnt_read_reg[1]_rep__1 ;
input \cnt_read_reg[0]_rep__0 ;
input m_axi_awready;
input [5:0]\m_payload_i_reg[49] ;
input [3:0]\axlen_cnt_reg[5]_0 ;
input \axlen_cnt_reg[3]_0 ;
input \axlen_cnt_reg[4]_0 ;
input [0:0]\wrap_second_len_r_reg[1]_0 ;
input [2:0]\m_payload_i_reg[35] ;
input \m_payload_i_reg[48] ;
input next_pending_r_reg;
input areset_d1;
input sel_first_reg_1;
input \m_payload_i_reg[46] ;
input \axlen_cnt_reg[2] ;
input next_pending_r_reg_0;
input [0:0]\axaddr_offset_r_reg[3]_0 ;
input \m_payload_i_reg[6] ;
input sel_first_reg_2;
input sel_first__0;
input aclk;
wire [0:0]D;
wire [0:0]E;
wire [1:0]Q;
wire aclk;
wire areset_d1;
wire \axaddr_incr_reg[11] ;
wire [0:0]\axaddr_offset_r_reg[3] ;
wire [0:0]\axaddr_offset_r_reg[3]_0 ;
wire [0:0]\axaddr_wrap_reg[0] ;
wire \axlen_cnt_reg[2] ;
wire \axlen_cnt_reg[3] ;
wire \axlen_cnt_reg[3]_0 ;
wire \axlen_cnt_reg[4] ;
wire \axlen_cnt_reg[4]_0 ;
wire [3:0]\axlen_cnt_reg[5] ;
wire [3:0]\axlen_cnt_reg[5]_0 ;
wire \cnt_read_reg[0]_rep__0 ;
wire \cnt_read_reg[1]_rep__1 ;
wire incr_next_pending;
wire m_axi_awready;
wire m_axi_awvalid;
wire \m_payload_i_reg[0] ;
wire [0:0]\m_payload_i_reg[0]_0 ;
wire [2:0]\m_payload_i_reg[35] ;
wire \m_payload_i_reg[44] ;
wire \m_payload_i_reg[46] ;
wire \m_payload_i_reg[48] ;
wire [5:0]\m_payload_i_reg[49] ;
wire \m_payload_i_reg[6] ;
wire next;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire [0:0]next_state;
wire s_axburst_eq0_reg;
wire s_axburst_eq1_reg;
wire s_axburst_eq1_reg_0;
wire sel_first__0;
wire sel_first_i;
wire sel_first_reg;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire si_rs_awvalid;
wire \state[0]_i_2_n_0 ;
wire \state[1]_i_1__0_n_0 ;
wire \state_reg[1]_rep_0 ;
wire \state_reg[1]_rep_1 ;
wire wrap_next_pending;
wire [0:0]\wrap_second_len_r_reg[1] ;
wire [0:0]\wrap_second_len_r_reg[1]_0 ;
(* SOFT_HLUTNM = "soft_lutpair110" *)
LUT4 #(
.INIT(16'hEEFE))
\axaddr_incr[0]_i_1
(.I0(sel_first_reg_2),
.I1(\m_payload_i_reg[0] ),
.I2(\state_reg[1]_rep_0 ),
.I3(\state_reg[1]_rep_1 ),
.O(\axaddr_incr_reg[11] ));
LUT6 #(
.INIT(64'hAAAAACAAAAAAA0AA))
\axaddr_offset_r[3]_i_1
(.I0(\axaddr_offset_r_reg[3]_0 ),
.I1(\m_payload_i_reg[49] [3]),
.I2(\state_reg[1]_rep_1 ),
.I3(si_rs_awvalid),
.I4(\state_reg[1]_rep_0 ),
.I5(\m_payload_i_reg[6] ),
.O(\axaddr_offset_r_reg[3] ));
LUT6 #(
.INIT(64'h0400FFFF04000400))
\axlen_cnt[0]_i_1
(.I0(Q[1]),
.I1(si_rs_awvalid),
.I2(Q[0]),
.I3(\m_payload_i_reg[49] [1]),
.I4(\axlen_cnt_reg[5]_0 [0]),
.I5(\axlen_cnt_reg[4] ),
.O(\axlen_cnt_reg[5] [0]));
LUT5 #(
.INIT(32'hF88F8888))
\axlen_cnt[1]_i_1
(.I0(E),
.I1(\m_payload_i_reg[49] [2]),
.I2(\axlen_cnt_reg[5]_0 [1]),
.I3(\axlen_cnt_reg[5]_0 [0]),
.I4(\axlen_cnt_reg[4] ),
.O(\axlen_cnt_reg[5] [1]));
LUT5 #(
.INIT(32'hF88F8888))
\axlen_cnt[4]_i_1
(.I0(E),
.I1(\m_payload_i_reg[49] [4]),
.I2(\axlen_cnt_reg[5]_0 [2]),
.I3(\axlen_cnt_reg[3]_0 ),
.I4(\axlen_cnt_reg[4] ),
.O(\axlen_cnt_reg[5] [2]));
LUT5 #(
.INIT(32'hF88F8888))
\axlen_cnt[5]_i_1
(.I0(E),
.I1(\m_payload_i_reg[49] [5]),
.I2(\axlen_cnt_reg[5]_0 [3]),
.I3(\axlen_cnt_reg[4]_0 ),
.I4(\axlen_cnt_reg[4] ),
.O(\axlen_cnt_reg[5] [3]));
(* SOFT_HLUTNM = "soft_lutpair110" *)
LUT4 #(
.INIT(16'hCCFE))
\axlen_cnt[7]_i_1
(.I0(si_rs_awvalid),
.I1(\m_payload_i_reg[0] ),
.I2(\state_reg[1]_rep_0 ),
.I3(\state_reg[1]_rep_1 ),
.O(\axaddr_wrap_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair111" *)
LUT4 #(
.INIT(16'h00FB))
\axlen_cnt[7]_i_5
(.I0(Q[0]),
.I1(si_rs_awvalid),
.I2(Q[1]),
.I3(\axlen_cnt_reg[3] ),
.O(\axlen_cnt_reg[4] ));
(* SOFT_HLUTNM = "soft_lutpair112" *)
LUT2 #(
.INIT(4'h2))
m_axi_awvalid_INST_0
(.I0(\state_reg[1]_rep_1 ),
.I1(\state_reg[1]_rep_0 ),
.O(m_axi_awvalid));
LUT2 #(
.INIT(4'hB))
\m_payload_i[31]_i_1
(.I0(\m_payload_i_reg[0] ),
.I1(si_rs_awvalid),
.O(\m_payload_i_reg[0]_0 ));
LUT6 #(
.INIT(64'h88008888A800A8A8))
\memory_reg[3][0]_srl4_i_1
(.I0(\state_reg[1]_rep_1 ),
.I1(\state_reg[1]_rep_0 ),
.I2(m_axi_awready),
.I3(\cnt_read_reg[0]_rep__0 ),
.I4(\cnt_read_reg[1]_rep__1 ),
.I5(s_axburst_eq1_reg_0),
.O(\m_payload_i_reg[0] ));
LUT5 #(
.INIT(32'h8BBB8B88))
next_pending_r_i_1
(.I0(\m_payload_i_reg[48] ),
.I1(E),
.I2(\axlen_cnt_reg[3] ),
.I3(next),
.I4(next_pending_r_reg),
.O(incr_next_pending));
LUT5 #(
.INIT(32'h8BBB8B88))
next_pending_r_i_1__0
(.I0(\m_payload_i_reg[46] ),
.I1(E),
.I2(\axlen_cnt_reg[2] ),
.I3(next),
.I4(next_pending_r_reg_0),
.O(wrap_next_pending));
LUT6 #(
.INIT(64'hF3F35100FFFF0000))
next_pending_r_i_4
(.I0(s_axburst_eq1_reg_0),
.I1(\cnt_read_reg[1]_rep__1 ),
.I2(\cnt_read_reg[0]_rep__0 ),
.I3(m_axi_awready),
.I4(\state_reg[1]_rep_0 ),
.I5(\state_reg[1]_rep_1 ),
.O(next));
(* SOFT_HLUTNM = "soft_lutpair109" *)
LUT4 #(
.INIT(16'hFB08))
s_axburst_eq0_i_1
(.I0(wrap_next_pending),
.I1(\m_payload_i_reg[49] [0]),
.I2(sel_first_i),
.I3(incr_next_pending),
.O(s_axburst_eq0_reg));
(* SOFT_HLUTNM = "soft_lutpair109" *)
LUT4 #(
.INIT(16'hABA8))
s_axburst_eq1_i_1
(.I0(wrap_next_pending),
.I1(\m_payload_i_reg[49] [0]),
.I2(sel_first_i),
.I3(incr_next_pending),
.O(s_axburst_eq1_reg));
LUT6 #(
.INIT(64'hCCCEFCFFCCCECCCE))
sel_first_i_1
(.I0(si_rs_awvalid),
.I1(areset_d1),
.I2(\state_reg[1]_rep_1 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[0] ),
.I5(sel_first_reg_1),
.O(sel_first_i));
LUT6 #(
.INIT(64'hFFFFFFFF44440F04))
sel_first_i_1__1
(.I0(\m_payload_i_reg[0] ),
.I1(sel_first_reg_2),
.I2(Q[1]),
.I3(si_rs_awvalid),
.I4(Q[0]),
.I5(areset_d1),
.O(sel_first_reg));
LUT6 #(
.INIT(64'hFFFFFFFF44440F04))
sel_first_i_1__2
(.I0(\m_payload_i_reg[0] ),
.I1(sel_first__0),
.I2(Q[1]),
.I3(si_rs_awvalid),
.I4(Q[0]),
.I5(areset_d1),
.O(sel_first_reg_0));
(* SOFT_HLUTNM = "soft_lutpair111" *)
LUT3 #(
.INIT(8'h2F))
\state[0]_i_1
(.I0(si_rs_awvalid),
.I1(Q[0]),
.I2(\state[0]_i_2_n_0 ),
.O(next_state));
LUT6 #(
.INIT(64'hFA08FAFA0F0F0F0F))
\state[0]_i_2
(.I0(m_axi_awready),
.I1(s_axburst_eq1_reg_0),
.I2(\state_reg[1]_rep_0 ),
.I3(\cnt_read_reg[0]_rep__0 ),
.I4(\cnt_read_reg[1]_rep__1 ),
.I5(\state_reg[1]_rep_1 ),
.O(\state[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0C0CAE0000000000))
\state[1]_i_1__0
(.I0(s_axburst_eq1_reg_0),
.I1(\cnt_read_reg[1]_rep__1 ),
.I2(\cnt_read_reg[0]_rep__0 ),
.I3(m_axi_awready),
.I4(\state_reg[1]_rep_0 ),
.I5(\state_reg[1]_rep_1 ),
.O(\state[1]_i_1__0_n_0 ));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[0]" *)
FDRE #(
.INIT(1'b0))
\state_reg[0]
(.C(aclk),
.CE(1'b1),
.D(next_state),
.Q(Q[0]),
.R(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[0]" *)
FDRE #(
.INIT(1'b0))
\state_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(next_state),
.Q(\state_reg[1]_rep_1 ),
.R(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[1]" *)
FDRE #(
.INIT(1'b0))
\state_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\state[1]_i_1__0_n_0 ),
.Q(Q[1]),
.R(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[1]" *)
FDRE #(
.INIT(1'b0))
\state_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(\state[1]_i_1__0_n_0 ),
.Q(\state_reg[1]_rep_0 ),
.R(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair112" *)
LUT3 #(
.INIT(8'h04))
\wrap_boundary_axaddr_r[11]_i_1
(.I0(\state_reg[1]_rep_0 ),
.I1(si_rs_awvalid),
.I2(\state_reg[1]_rep_1 ),
.O(E));
LUT2 #(
.INIT(4'h9))
\wrap_cnt_r[1]_i_1
(.I0(\wrap_second_len_r_reg[1] ),
.I1(\m_payload_i_reg[44] ),
.O(D));
LUT6 #(
.INIT(64'hFF0000FCAAAAAAAA))
\wrap_second_len_r[1]_i_1
(.I0(\wrap_second_len_r_reg[1]_0 ),
.I1(\m_payload_i_reg[35] [2]),
.I2(\axaddr_offset_r_reg[3] ),
.I3(\m_payload_i_reg[35] [0]),
.I4(\m_payload_i_reg[35] [1]),
.I5(E),
.O(\wrap_second_len_r_reg[1] ));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_wrap_cmd" *)
module zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd
(next_pending_r_reg_0,
sel_first_reg_0,
next_pending_r_reg_1,
m_axi_awaddr,
\axaddr_offset_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_0 ,
wrap_next_pending,
aclk,
sel_first_reg_1,
E,
\m_payload_i_reg[47] ,
next,
axaddr_incr_reg,
\m_payload_i_reg[38] ,
\axaddr_incr_reg[3] ,
sel_first_reg_2,
\axaddr_offset_r_reg[3]_1 ,
\wrap_second_len_r_reg[3]_1 ,
m_valid_i_reg,
\wrap_second_len_r_reg[3]_2 ,
\m_payload_i_reg[6] );
output next_pending_r_reg_0;
output sel_first_reg_0;
output next_pending_r_reg_1;
output [11:0]m_axi_awaddr;
output [3:0]\axaddr_offset_r_reg[3]_0 ;
output [3:0]\wrap_second_len_r_reg[3]_0 ;
input wrap_next_pending;
input aclk;
input sel_first_reg_1;
input [0:0]E;
input [18:0]\m_payload_i_reg[47] ;
input next;
input [7:0]axaddr_incr_reg;
input \m_payload_i_reg[38] ;
input [2:0]\axaddr_incr_reg[3] ;
input sel_first_reg_2;
input [3:0]\axaddr_offset_r_reg[3]_1 ;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input [0:0]m_valid_i_reg;
input [3:0]\wrap_second_len_r_reg[3]_2 ;
input [6:0]\m_payload_i_reg[6] ;
wire [0:0]E;
wire aclk;
wire [7:0]axaddr_incr_reg;
wire [2:0]\axaddr_incr_reg[3] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire [3:0]\axaddr_offset_r_reg[3]_1 ;
wire [11:0]axaddr_wrap;
wire [11:0]axaddr_wrap0;
wire \axaddr_wrap[0]_i_1_n_0 ;
wire \axaddr_wrap[10]_i_1_n_0 ;
wire \axaddr_wrap[11]_i_1_n_0 ;
wire \axaddr_wrap[11]_i_2_n_0 ;
wire \axaddr_wrap[11]_i_4_n_0 ;
wire \axaddr_wrap[11]_i_5_n_0 ;
wire \axaddr_wrap[11]_i_6_n_0 ;
wire \axaddr_wrap[11]_i_7_n_0 ;
wire \axaddr_wrap[11]_i_8_n_0 ;
wire \axaddr_wrap[1]_i_1_n_0 ;
wire \axaddr_wrap[2]_i_1_n_0 ;
wire \axaddr_wrap[3]_i_1_n_0 ;
wire \axaddr_wrap[3]_i_3_n_0 ;
wire \axaddr_wrap[3]_i_4_n_0 ;
wire \axaddr_wrap[3]_i_5_n_0 ;
wire \axaddr_wrap[3]_i_6_n_0 ;
wire \axaddr_wrap[4]_i_1_n_0 ;
wire \axaddr_wrap[5]_i_1_n_0 ;
wire \axaddr_wrap[6]_i_1_n_0 ;
wire \axaddr_wrap[7]_i_1_n_0 ;
wire \axaddr_wrap[7]_i_3_n_0 ;
wire \axaddr_wrap[7]_i_4_n_0 ;
wire \axaddr_wrap[7]_i_5_n_0 ;
wire \axaddr_wrap[7]_i_6_n_0 ;
wire \axaddr_wrap[8]_i_1_n_0 ;
wire \axaddr_wrap[9]_i_1_n_0 ;
wire \axaddr_wrap_reg[11]_i_3_n_1 ;
wire \axaddr_wrap_reg[11]_i_3_n_2 ;
wire \axaddr_wrap_reg[11]_i_3_n_3 ;
wire \axaddr_wrap_reg[3]_i_2_n_0 ;
wire \axaddr_wrap_reg[3]_i_2_n_1 ;
wire \axaddr_wrap_reg[3]_i_2_n_2 ;
wire \axaddr_wrap_reg[3]_i_2_n_3 ;
wire \axaddr_wrap_reg[7]_i_2_n_0 ;
wire \axaddr_wrap_reg[7]_i_2_n_1 ;
wire \axaddr_wrap_reg[7]_i_2_n_2 ;
wire \axaddr_wrap_reg[7]_i_2_n_3 ;
wire \axlen_cnt[0]_i_1__0_n_0 ;
wire \axlen_cnt[1]_i_1__0_n_0 ;
wire \axlen_cnt[2]_i_1__0_n_0 ;
wire \axlen_cnt[3]_i_1__0_n_0 ;
wire \axlen_cnt_reg_n_0_[0] ;
wire \axlen_cnt_reg_n_0_[1] ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire [11:0]m_axi_awaddr;
wire \m_payload_i_reg[38] ;
wire [18:0]\m_payload_i_reg[47] ;
wire [6:0]\m_payload_i_reg[6] ;
wire [0:0]m_valid_i_reg;
wire next;
wire next_pending_r_reg_0;
wire next_pending_r_reg_1;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire [11:0]wrap_boundary_axaddr_r;
wire [3:0]wrap_cnt_r;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
wire [3:0]\wrap_second_len_r_reg[3]_2 ;
wire [3:3]\NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED ;
FDRE \axaddr_offset_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_1 [0]),
.Q(\axaddr_offset_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_1 [1]),
.Q(\axaddr_offset_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_1 [2]),
.Q(\axaddr_offset_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_1 [3]),
.Q(\axaddr_offset_r_reg[3]_0 [3]),
.R(1'b0));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[0]_i_1
(.I0(wrap_boundary_axaddr_r[0]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[0]),
.I3(next),
.I4(\m_payload_i_reg[47] [0]),
.O(\axaddr_wrap[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[10]_i_1
(.I0(wrap_boundary_axaddr_r[10]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[10]),
.I3(next),
.I4(\m_payload_i_reg[47] [10]),
.O(\axaddr_wrap[10]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[11]_i_1
(.I0(wrap_boundary_axaddr_r[11]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[11]),
.I3(next),
.I4(\m_payload_i_reg[47] [11]),
.O(\axaddr_wrap[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair114" *)
LUT3 #(
.INIT(8'h41))
\axaddr_wrap[11]_i_2
(.I0(\axaddr_wrap[11]_i_4_n_0 ),
.I1(wrap_cnt_r[3]),
.I2(\axlen_cnt_reg_n_0_[3] ),
.O(\axaddr_wrap[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6FF6FFFFFFFF6FF6))
\axaddr_wrap[11]_i_4
(.I0(wrap_cnt_r[0]),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(wrap_cnt_r[2]),
.I4(\axlen_cnt_reg_n_0_[1] ),
.I5(wrap_cnt_r[1]),
.O(\axaddr_wrap[11]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_5
(.I0(axaddr_wrap[11]),
.O(\axaddr_wrap[11]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_6
(.I0(axaddr_wrap[10]),
.O(\axaddr_wrap[11]_i_6_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_7
(.I0(axaddr_wrap[9]),
.O(\axaddr_wrap[11]_i_7_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_8
(.I0(axaddr_wrap[8]),
.O(\axaddr_wrap[11]_i_8_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[1]_i_1
(.I0(wrap_boundary_axaddr_r[1]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[1]),
.I3(next),
.I4(\m_payload_i_reg[47] [1]),
.O(\axaddr_wrap[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[2]_i_1
(.I0(wrap_boundary_axaddr_r[2]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[2]),
.I3(next),
.I4(\m_payload_i_reg[47] [2]),
.O(\axaddr_wrap[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[3]_i_1
(.I0(wrap_boundary_axaddr_r[3]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[3]),
.I3(next),
.I4(\m_payload_i_reg[47] [3]),
.O(\axaddr_wrap[3]_i_1_n_0 ));
LUT3 #(
.INIT(8'h6A))
\axaddr_wrap[3]_i_3
(.I0(axaddr_wrap[3]),
.I1(\m_payload_i_reg[47] [12]),
.I2(\m_payload_i_reg[47] [13]),
.O(\axaddr_wrap[3]_i_3_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_4
(.I0(axaddr_wrap[2]),
.I1(\m_payload_i_reg[47] [12]),
.I2(\m_payload_i_reg[47] [13]),
.O(\axaddr_wrap[3]_i_4_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_5
(.I0(axaddr_wrap[1]),
.I1(\m_payload_i_reg[47] [13]),
.I2(\m_payload_i_reg[47] [12]),
.O(\axaddr_wrap[3]_i_5_n_0 ));
LUT3 #(
.INIT(8'hA9))
\axaddr_wrap[3]_i_6
(.I0(axaddr_wrap[0]),
.I1(\m_payload_i_reg[47] [12]),
.I2(\m_payload_i_reg[47] [13]),
.O(\axaddr_wrap[3]_i_6_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[4]_i_1
(.I0(wrap_boundary_axaddr_r[4]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[4]),
.I3(next),
.I4(\m_payload_i_reg[47] [4]),
.O(\axaddr_wrap[4]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[5]_i_1
(.I0(wrap_boundary_axaddr_r[5]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[5]),
.I3(next),
.I4(\m_payload_i_reg[47] [5]),
.O(\axaddr_wrap[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[6]_i_1
(.I0(wrap_boundary_axaddr_r[6]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[6]),
.I3(next),
.I4(\m_payload_i_reg[47] [6]),
.O(\axaddr_wrap[6]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[7]_i_1
(.I0(wrap_boundary_axaddr_r[7]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[7]),
.I3(next),
.I4(\m_payload_i_reg[47] [7]),
.O(\axaddr_wrap[7]_i_1_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_3
(.I0(axaddr_wrap[7]),
.O(\axaddr_wrap[7]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_4
(.I0(axaddr_wrap[6]),
.O(\axaddr_wrap[7]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_5
(.I0(axaddr_wrap[5]),
.O(\axaddr_wrap[7]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_6
(.I0(axaddr_wrap[4]),
.O(\axaddr_wrap[7]_i_6_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[8]_i_1
(.I0(wrap_boundary_axaddr_r[8]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[8]),
.I3(next),
.I4(\m_payload_i_reg[47] [8]),
.O(\axaddr_wrap[8]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[9]_i_1
(.I0(wrap_boundary_axaddr_r[9]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[9]),
.I3(next),
.I4(\m_payload_i_reg[47] [9]),
.O(\axaddr_wrap[9]_i_1_n_0 ));
FDRE \axaddr_wrap_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[0]_i_1_n_0 ),
.Q(axaddr_wrap[0]),
.R(1'b0));
FDRE \axaddr_wrap_reg[10]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[10]_i_1_n_0 ),
.Q(axaddr_wrap[10]),
.R(1'b0));
FDRE \axaddr_wrap_reg[11]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[11]_i_1_n_0 ),
.Q(axaddr_wrap[11]),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[11]_i_3
(.CI(\axaddr_wrap_reg[7]_i_2_n_0 ),
.CO({\NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED [3],\axaddr_wrap_reg[11]_i_3_n_1 ,\axaddr_wrap_reg[11]_i_3_n_2 ,\axaddr_wrap_reg[11]_i_3_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(axaddr_wrap0[11:8]),
.S({\axaddr_wrap[11]_i_5_n_0 ,\axaddr_wrap[11]_i_6_n_0 ,\axaddr_wrap[11]_i_7_n_0 ,\axaddr_wrap[11]_i_8_n_0 }));
FDRE \axaddr_wrap_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[1]_i_1_n_0 ),
.Q(axaddr_wrap[1]),
.R(1'b0));
FDRE \axaddr_wrap_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[2]_i_1_n_0 ),
.Q(axaddr_wrap[2]),
.R(1'b0));
FDRE \axaddr_wrap_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[3]_i_1_n_0 ),
.Q(axaddr_wrap[3]),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[3]_i_2
(.CI(1'b0),
.CO({\axaddr_wrap_reg[3]_i_2_n_0 ,\axaddr_wrap_reg[3]_i_2_n_1 ,\axaddr_wrap_reg[3]_i_2_n_2 ,\axaddr_wrap_reg[3]_i_2_n_3 }),
.CYINIT(1'b0),
.DI(axaddr_wrap[3:0]),
.O(axaddr_wrap0[3:0]),
.S({\axaddr_wrap[3]_i_3_n_0 ,\axaddr_wrap[3]_i_4_n_0 ,\axaddr_wrap[3]_i_5_n_0 ,\axaddr_wrap[3]_i_6_n_0 }));
FDRE \axaddr_wrap_reg[4]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[4]_i_1_n_0 ),
.Q(axaddr_wrap[4]),
.R(1'b0));
FDRE \axaddr_wrap_reg[5]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[5]_i_1_n_0 ),
.Q(axaddr_wrap[5]),
.R(1'b0));
FDRE \axaddr_wrap_reg[6]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[6]_i_1_n_0 ),
.Q(axaddr_wrap[6]),
.R(1'b0));
FDRE \axaddr_wrap_reg[7]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[7]_i_1_n_0 ),
.Q(axaddr_wrap[7]),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[7]_i_2
(.CI(\axaddr_wrap_reg[3]_i_2_n_0 ),
.CO({\axaddr_wrap_reg[7]_i_2_n_0 ,\axaddr_wrap_reg[7]_i_2_n_1 ,\axaddr_wrap_reg[7]_i_2_n_2 ,\axaddr_wrap_reg[7]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(axaddr_wrap0[7:4]),
.S({\axaddr_wrap[7]_i_3_n_0 ,\axaddr_wrap[7]_i_4_n_0 ,\axaddr_wrap[7]_i_5_n_0 ,\axaddr_wrap[7]_i_6_n_0 }));
FDRE \axaddr_wrap_reg[8]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[8]_i_1_n_0 ),
.Q(axaddr_wrap[8]),
.R(1'b0));
FDRE \axaddr_wrap_reg[9]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[9]_i_1_n_0 ),
.Q(axaddr_wrap[9]),
.R(1'b0));
LUT6 #(
.INIT(64'hA3A3A3A3A3A3A3A0))
\axlen_cnt[0]_i_1__0
(.I0(\m_payload_i_reg[47] [15]),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(E),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(\axlen_cnt_reg_n_0_[1] ),
.I5(\axlen_cnt_reg_n_0_[2] ),
.O(\axlen_cnt[0]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hFFFF999800009998))
\axlen_cnt[1]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[1] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[3] ),
.I3(\axlen_cnt_reg_n_0_[2] ),
.I4(E),
.I5(\m_payload_i_reg[47] [16]),
.O(\axlen_cnt[1]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFA9A80000A9A8))
\axlen_cnt[2]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[2] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(E),
.I5(\m_payload_i_reg[47] [17]),
.O(\axlen_cnt[2]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFAAA80000AAA8))
\axlen_cnt[3]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(E),
.I5(\m_payload_i_reg[47] [18]),
.O(\axlen_cnt[3]_i_1__0_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[0]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[0] ),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[1]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[1] ),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[2]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[3]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[0]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[0]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[3] [0]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [0]),
.O(m_axi_awaddr[0]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[10]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[10]),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[6]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [10]),
.O(m_axi_awaddr[10]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[11]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[11]),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[7]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [11]),
.O(m_axi_awaddr[11]));
LUT5 #(
.INIT(32'hB8FFB800))
\m_axi_awaddr[1]_INST_0
(.I0(\m_payload_i_reg[47] [1]),
.I1(sel_first_reg_0),
.I2(axaddr_wrap[1]),
.I3(\m_payload_i_reg[47] [14]),
.I4(sel_first_reg_2),
.O(m_axi_awaddr[1]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[2]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[2]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[3] [1]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [2]),
.O(m_axi_awaddr[2]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[3]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[3]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[3] [2]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [3]),
.O(m_axi_awaddr[3]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[4]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[4]),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[0]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [4]),
.O(m_axi_awaddr[4]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[5]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[5]),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[1]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [5]),
.O(m_axi_awaddr[5]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[6]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[6]),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[2]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [6]),
.O(m_axi_awaddr[6]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[7]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[7]),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[3]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [7]),
.O(m_axi_awaddr[7]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[8]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[8]),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[4]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [8]),
.O(m_axi_awaddr[8]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[9]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[9]),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[5]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [9]),
.O(m_axi_awaddr[9]));
(* SOFT_HLUTNM = "soft_lutpair114" *)
LUT3 #(
.INIT(8'h01))
next_pending_r_i_3__0
(.I0(\axlen_cnt_reg_n_0_[2] ),
.I1(\axlen_cnt_reg_n_0_[1] ),
.I2(\axlen_cnt_reg_n_0_[3] ),
.O(next_pending_r_reg_1));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(wrap_next_pending),
.Q(next_pending_r_reg_0),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_1),
.Q(sel_first_reg_0),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[0]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [0]),
.Q(wrap_boundary_axaddr_r[0]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[10]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [10]),
.Q(wrap_boundary_axaddr_r[10]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[11]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [11]),
.Q(wrap_boundary_axaddr_r[11]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[1]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [1]),
.Q(wrap_boundary_axaddr_r[1]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[2]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [2]),
.Q(wrap_boundary_axaddr_r[2]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[3]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [3]),
.Q(wrap_boundary_axaddr_r[3]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[4]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [4]),
.Q(wrap_boundary_axaddr_r[4]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[5]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [5]),
.Q(wrap_boundary_axaddr_r[5]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[6]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [6]),
.Q(wrap_boundary_axaddr_r[6]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[7]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [7]),
.Q(wrap_boundary_axaddr_r[7]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[8]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [8]),
.Q(wrap_boundary_axaddr_r[8]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[9]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [9]),
.Q(wrap_boundary_axaddr_r[9]),
.R(1'b0));
FDRE \wrap_cnt_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [0]),
.Q(wrap_cnt_r[0]),
.R(1'b0));
FDRE \wrap_cnt_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [1]),
.Q(wrap_cnt_r[1]),
.R(1'b0));
FDRE \wrap_cnt_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [2]),
.Q(wrap_cnt_r[2]),
.R(1'b0));
FDRE \wrap_cnt_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [3]),
.Q(wrap_cnt_r[3]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [0]),
.Q(\wrap_second_len_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [1]),
.Q(\wrap_second_len_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [2]),
.Q(\wrap_second_len_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [3]),
.Q(\wrap_second_len_r_reg[3]_0 [3]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_wrap_cmd" *)
module zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3
(wrap_next_pending,
sel_first_reg_0,
m_axi_araddr,
\axaddr_offset_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_0 ,
aclk,
sel_first_reg_1,
E,
\m_payload_i_reg[47] ,
\state_reg[0]_rep ,
si_rs_arvalid,
\state_reg[1]_rep ,
\m_payload_i_reg[46] ,
\state_reg[1]_rep_0 ,
\axaddr_incr_reg[11] ,
\m_payload_i_reg[38] ,
\axaddr_incr_reg[3] ,
sel_first_reg_2,
sel_first_reg_3,
\axaddr_offset_r_reg[3]_1 ,
\wrap_second_len_r_reg[3]_1 ,
m_valid_i_reg,
\wrap_second_len_r_reg[3]_2 ,
\m_payload_i_reg[6] );
output wrap_next_pending;
output sel_first_reg_0;
output [11:0]m_axi_araddr;
output [3:0]\axaddr_offset_r_reg[3]_0 ;
output [3:0]\wrap_second_len_r_reg[3]_0 ;
input aclk;
input sel_first_reg_1;
input [0:0]E;
input [18:0]\m_payload_i_reg[47] ;
input \state_reg[0]_rep ;
input si_rs_arvalid;
input \state_reg[1]_rep ;
input \m_payload_i_reg[46] ;
input \state_reg[1]_rep_0 ;
input [6:0]\axaddr_incr_reg[11] ;
input \m_payload_i_reg[38] ;
input [2:0]\axaddr_incr_reg[3] ;
input sel_first_reg_2;
input sel_first_reg_3;
input [3:0]\axaddr_offset_r_reg[3]_1 ;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input [0:0]m_valid_i_reg;
input [3:0]\wrap_second_len_r_reg[3]_2 ;
input [6:0]\m_payload_i_reg[6] ;
wire [0:0]E;
wire aclk;
wire [6:0]\axaddr_incr_reg[11] ;
wire [2:0]\axaddr_incr_reg[3] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire [3:0]\axaddr_offset_r_reg[3]_1 ;
wire \axaddr_wrap[0]_i_1__0_n_0 ;
wire \axaddr_wrap[10]_i_1__0_n_0 ;
wire \axaddr_wrap[11]_i_1__0_n_0 ;
wire \axaddr_wrap[11]_i_2__0_n_0 ;
wire \axaddr_wrap[11]_i_4__0_n_0 ;
wire \axaddr_wrap[11]_i_5__0_n_0 ;
wire \axaddr_wrap[11]_i_6__0_n_0 ;
wire \axaddr_wrap[11]_i_7__0_n_0 ;
wire \axaddr_wrap[11]_i_8__0_n_0 ;
wire \axaddr_wrap[1]_i_1__0_n_0 ;
wire \axaddr_wrap[2]_i_1__0_n_0 ;
wire \axaddr_wrap[3]_i_1__0_n_0 ;
wire \axaddr_wrap[3]_i_3_n_0 ;
wire \axaddr_wrap[3]_i_4_n_0 ;
wire \axaddr_wrap[3]_i_5_n_0 ;
wire \axaddr_wrap[3]_i_6_n_0 ;
wire \axaddr_wrap[4]_i_1__0_n_0 ;
wire \axaddr_wrap[5]_i_1__0_n_0 ;
wire \axaddr_wrap[6]_i_1__0_n_0 ;
wire \axaddr_wrap[7]_i_1__0_n_0 ;
wire \axaddr_wrap[7]_i_3__0_n_0 ;
wire \axaddr_wrap[7]_i_4__0_n_0 ;
wire \axaddr_wrap[7]_i_5__0_n_0 ;
wire \axaddr_wrap[7]_i_6__0_n_0 ;
wire \axaddr_wrap[8]_i_1__0_n_0 ;
wire \axaddr_wrap[9]_i_1__0_n_0 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_1 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_2 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_3 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_4 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_5 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_6 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_7 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_0 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_1 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_2 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_3 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_4 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_5 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_6 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_7 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_0 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_1 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_2 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_3 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_4 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_5 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_6 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_7 ;
wire \axaddr_wrap_reg_n_0_[0] ;
wire \axaddr_wrap_reg_n_0_[10] ;
wire \axaddr_wrap_reg_n_0_[11] ;
wire \axaddr_wrap_reg_n_0_[1] ;
wire \axaddr_wrap_reg_n_0_[2] ;
wire \axaddr_wrap_reg_n_0_[3] ;
wire \axaddr_wrap_reg_n_0_[4] ;
wire \axaddr_wrap_reg_n_0_[5] ;
wire \axaddr_wrap_reg_n_0_[6] ;
wire \axaddr_wrap_reg_n_0_[7] ;
wire \axaddr_wrap_reg_n_0_[8] ;
wire \axaddr_wrap_reg_n_0_[9] ;
wire \axlen_cnt[0]_i_1__2_n_0 ;
wire \axlen_cnt[1]_i_1__2_n_0 ;
wire \axlen_cnt[2]_i_1__2_n_0 ;
wire \axlen_cnt[3]_i_1__2_n_0 ;
wire \axlen_cnt_reg_n_0_[0] ;
wire \axlen_cnt_reg_n_0_[1] ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire [11:0]m_axi_araddr;
wire \m_payload_i_reg[38] ;
wire \m_payload_i_reg[46] ;
wire [18:0]\m_payload_i_reg[47] ;
wire [6:0]\m_payload_i_reg[6] ;
wire [0:0]m_valid_i_reg;
wire next_pending_r_i_3__2_n_0;
wire next_pending_r_reg_n_0;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire sel_first_reg_3;
wire si_rs_arvalid;
wire \state_reg[0]_rep ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire \wrap_boundary_axaddr_r_reg_n_0_[0] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[10] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[11] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[1] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[2] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[3] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[4] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[5] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[6] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[7] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[8] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[9] ;
wire \wrap_cnt_r_reg_n_0_[0] ;
wire \wrap_cnt_r_reg_n_0_[1] ;
wire \wrap_cnt_r_reg_n_0_[2] ;
wire \wrap_cnt_r_reg_n_0_[3] ;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
wire [3:0]\wrap_second_len_r_reg[3]_2 ;
wire [3:3]\NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED ;
FDRE \axaddr_offset_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_1 [0]),
.Q(\axaddr_offset_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_1 [1]),
.Q(\axaddr_offset_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_1 [2]),
.Q(\axaddr_offset_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_1 [3]),
.Q(\axaddr_offset_r_reg[3]_0 [3]),
.R(1'b0));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[0]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[0] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[3]_i_2__0_n_7 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [0]),
.O(\axaddr_wrap[0]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[10]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[10] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[11]_i_3__0_n_5 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [10]),
.O(\axaddr_wrap[10]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[11]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[11] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[11]_i_3__0_n_4 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [11]),
.O(\axaddr_wrap[11]_i_1__0_n_0 ));
LUT3 #(
.INIT(8'h41))
\axaddr_wrap[11]_i_2__0
(.I0(\axaddr_wrap[11]_i_4__0_n_0 ),
.I1(\wrap_cnt_r_reg_n_0_[3] ),
.I2(\axlen_cnt_reg_n_0_[3] ),
.O(\axaddr_wrap[11]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'h6FF6FFFFFFFF6FF6))
\axaddr_wrap[11]_i_4__0
(.I0(\wrap_cnt_r_reg_n_0_[0] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\wrap_cnt_r_reg_n_0_[1] ),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(\wrap_cnt_r_reg_n_0_[2] ),
.O(\axaddr_wrap[11]_i_4__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_5__0
(.I0(\axaddr_wrap_reg_n_0_[11] ),
.O(\axaddr_wrap[11]_i_5__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_6__0
(.I0(\axaddr_wrap_reg_n_0_[10] ),
.O(\axaddr_wrap[11]_i_6__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_7__0
(.I0(\axaddr_wrap_reg_n_0_[9] ),
.O(\axaddr_wrap[11]_i_7__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_8__0
(.I0(\axaddr_wrap_reg_n_0_[8] ),
.O(\axaddr_wrap[11]_i_8__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[1]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[1] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[3]_i_2__0_n_6 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [1]),
.O(\axaddr_wrap[1]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[2]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[2] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[3]_i_2__0_n_5 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [2]),
.O(\axaddr_wrap[2]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[3]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[3] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[3]_i_2__0_n_4 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [3]),
.O(\axaddr_wrap[3]_i_1__0_n_0 ));
LUT3 #(
.INIT(8'h6A))
\axaddr_wrap[3]_i_3
(.I0(\axaddr_wrap_reg_n_0_[3] ),
.I1(\m_payload_i_reg[47] [12]),
.I2(\m_payload_i_reg[47] [13]),
.O(\axaddr_wrap[3]_i_3_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_4
(.I0(\axaddr_wrap_reg_n_0_[2] ),
.I1(\m_payload_i_reg[47] [12]),
.I2(\m_payload_i_reg[47] [13]),
.O(\axaddr_wrap[3]_i_4_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_5
(.I0(\axaddr_wrap_reg_n_0_[1] ),
.I1(\m_payload_i_reg[47] [13]),
.I2(\m_payload_i_reg[47] [12]),
.O(\axaddr_wrap[3]_i_5_n_0 ));
LUT3 #(
.INIT(8'hA9))
\axaddr_wrap[3]_i_6
(.I0(\axaddr_wrap_reg_n_0_[0] ),
.I1(\m_payload_i_reg[47] [12]),
.I2(\m_payload_i_reg[47] [13]),
.O(\axaddr_wrap[3]_i_6_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[4]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[4] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[7]_i_2__0_n_7 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [4]),
.O(\axaddr_wrap[4]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[5]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[5] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[7]_i_2__0_n_6 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [5]),
.O(\axaddr_wrap[5]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[6]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[6] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[7]_i_2__0_n_5 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [6]),
.O(\axaddr_wrap[6]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[7]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[7] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[7]_i_2__0_n_4 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [7]),
.O(\axaddr_wrap[7]_i_1__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_3__0
(.I0(\axaddr_wrap_reg_n_0_[7] ),
.O(\axaddr_wrap[7]_i_3__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_4__0
(.I0(\axaddr_wrap_reg_n_0_[6] ),
.O(\axaddr_wrap[7]_i_4__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_5__0
(.I0(\axaddr_wrap_reg_n_0_[5] ),
.O(\axaddr_wrap[7]_i_5__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_6__0
(.I0(\axaddr_wrap_reg_n_0_[4] ),
.O(\axaddr_wrap[7]_i_6__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[8]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[8] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[11]_i_3__0_n_7 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [8]),
.O(\axaddr_wrap[8]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[9]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[9] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[11]_i_3__0_n_6 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [9]),
.O(\axaddr_wrap[9]_i_1__0_n_0 ));
FDRE \axaddr_wrap_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[0]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[0] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[10]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[10]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[10] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[11]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[11]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[11] ),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[11]_i_3__0
(.CI(\axaddr_wrap_reg[7]_i_2__0_n_0 ),
.CO({\NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED [3],\axaddr_wrap_reg[11]_i_3__0_n_1 ,\axaddr_wrap_reg[11]_i_3__0_n_2 ,\axaddr_wrap_reg[11]_i_3__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_wrap_reg[11]_i_3__0_n_4 ,\axaddr_wrap_reg[11]_i_3__0_n_5 ,\axaddr_wrap_reg[11]_i_3__0_n_6 ,\axaddr_wrap_reg[11]_i_3__0_n_7 }),
.S({\axaddr_wrap[11]_i_5__0_n_0 ,\axaddr_wrap[11]_i_6__0_n_0 ,\axaddr_wrap[11]_i_7__0_n_0 ,\axaddr_wrap[11]_i_8__0_n_0 }));
FDRE \axaddr_wrap_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[1]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[1] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[2]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[2] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[3]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[3] ),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[3]_i_2__0
(.CI(1'b0),
.CO({\axaddr_wrap_reg[3]_i_2__0_n_0 ,\axaddr_wrap_reg[3]_i_2__0_n_1 ,\axaddr_wrap_reg[3]_i_2__0_n_2 ,\axaddr_wrap_reg[3]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({\axaddr_wrap_reg_n_0_[3] ,\axaddr_wrap_reg_n_0_[2] ,\axaddr_wrap_reg_n_0_[1] ,\axaddr_wrap_reg_n_0_[0] }),
.O({\axaddr_wrap_reg[3]_i_2__0_n_4 ,\axaddr_wrap_reg[3]_i_2__0_n_5 ,\axaddr_wrap_reg[3]_i_2__0_n_6 ,\axaddr_wrap_reg[3]_i_2__0_n_7 }),
.S({\axaddr_wrap[3]_i_3_n_0 ,\axaddr_wrap[3]_i_4_n_0 ,\axaddr_wrap[3]_i_5_n_0 ,\axaddr_wrap[3]_i_6_n_0 }));
FDRE \axaddr_wrap_reg[4]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[4]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[4] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[5]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[5]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[5] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[6]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[6]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[6] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[7]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[7]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[7] ),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[7]_i_2__0
(.CI(\axaddr_wrap_reg[3]_i_2__0_n_0 ),
.CO({\axaddr_wrap_reg[7]_i_2__0_n_0 ,\axaddr_wrap_reg[7]_i_2__0_n_1 ,\axaddr_wrap_reg[7]_i_2__0_n_2 ,\axaddr_wrap_reg[7]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_wrap_reg[7]_i_2__0_n_4 ,\axaddr_wrap_reg[7]_i_2__0_n_5 ,\axaddr_wrap_reg[7]_i_2__0_n_6 ,\axaddr_wrap_reg[7]_i_2__0_n_7 }),
.S({\axaddr_wrap[7]_i_3__0_n_0 ,\axaddr_wrap[7]_i_4__0_n_0 ,\axaddr_wrap[7]_i_5__0_n_0 ,\axaddr_wrap[7]_i_6__0_n_0 }));
FDRE \axaddr_wrap_reg[8]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[8]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[8] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[9]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[9]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[9] ),
.R(1'b0));
LUT6 #(
.INIT(64'hA3A3A3A3A3A3A3A0))
\axlen_cnt[0]_i_1__2
(.I0(\m_payload_i_reg[47] [15]),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(E),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(\axlen_cnt_reg_n_0_[1] ),
.O(\axlen_cnt[0]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'hFFFF999800009998))
\axlen_cnt[1]_i_1__2
(.I0(\axlen_cnt_reg_n_0_[1] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[3] ),
.I3(\axlen_cnt_reg_n_0_[2] ),
.I4(E),
.I5(\m_payload_i_reg[47] [16]),
.O(\axlen_cnt[1]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'hFFFFA9A80000A9A8))
\axlen_cnt[2]_i_1__2
(.I0(\axlen_cnt_reg_n_0_[2] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(E),
.I5(\m_payload_i_reg[47] [17]),
.O(\axlen_cnt[2]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'hFFFFAAA80000AAA8))
\axlen_cnt[3]_i_1__2
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(E),
.I5(\m_payload_i_reg[47] [18]),
.O(\axlen_cnt[3]_i_1__2_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[0]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[0] ),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[1]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[1] ),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[2]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[3]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[0]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[0] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[3] [0]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [0]),
.O(m_axi_araddr[0]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[10]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[10] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[11] [5]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [10]),
.O(m_axi_araddr[10]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[11]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[11] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[11] [6]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [11]),
.O(m_axi_araddr[11]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[1]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[1] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[3] [1]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [1]),
.O(m_axi_araddr[1]));
LUT5 #(
.INIT(32'hB8FFB800))
\m_axi_araddr[2]_INST_0
(.I0(\m_payload_i_reg[47] [2]),
.I1(sel_first_reg_0),
.I2(\axaddr_wrap_reg_n_0_[2] ),
.I3(\m_payload_i_reg[47] [14]),
.I4(sel_first_reg_3),
.O(m_axi_araddr[2]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[3]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[3] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[3] [2]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [3]),
.O(m_axi_araddr[3]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[4]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[4] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[11] [0]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [4]),
.O(m_axi_araddr[4]));
LUT5 #(
.INIT(32'hB8FFB800))
\m_axi_araddr[5]_INST_0
(.I0(\m_payload_i_reg[47] [5]),
.I1(sel_first_reg_0),
.I2(\axaddr_wrap_reg_n_0_[5] ),
.I3(\m_payload_i_reg[47] [14]),
.I4(sel_first_reg_2),
.O(m_axi_araddr[5]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[6]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[6] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[11] [1]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [6]),
.O(m_axi_araddr[6]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[7]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[7] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[11] [2]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [7]),
.O(m_axi_araddr[7]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[8]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[8] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[11] [3]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [8]),
.O(m_axi_araddr[8]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[9]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[9] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[11] [4]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [9]),
.O(m_axi_araddr[9]));
LUT5 #(
.INIT(32'hFD55FC0C))
next_pending_r_i_1__1
(.I0(\m_payload_i_reg[46] ),
.I1(next_pending_r_reg_n_0),
.I2(\state_reg[1]_rep_0 ),
.I3(next_pending_r_i_3__2_n_0),
.I4(E),
.O(wrap_next_pending));
LUT6 #(
.INIT(64'hFBFBFBFBFBFBFB00))
next_pending_r_i_3__2
(.I0(\state_reg[0]_rep ),
.I1(si_rs_arvalid),
.I2(\state_reg[1]_rep ),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(\axlen_cnt_reg_n_0_[1] ),
.O(next_pending_r_i_3__2_n_0));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(wrap_next_pending),
.Q(next_pending_r_reg_n_0),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_1),
.Q(sel_first_reg_0),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[0]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [0]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[0] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[10]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [10]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[10] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[11]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [11]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[11] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[1]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [1]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[1] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[2]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [2]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[2] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[3]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [3]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[3] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[4]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [4]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[4] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[5]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [5]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[5] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[6]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [6]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[6] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[7]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [7]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[7] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[8]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [8]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[8] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[9]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [9]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[9] ),
.R(1'b0));
FDRE \wrap_cnt_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [0]),
.Q(\wrap_cnt_r_reg_n_0_[0] ),
.R(1'b0));
FDRE \wrap_cnt_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [1]),
.Q(\wrap_cnt_r_reg_n_0_[1] ),
.R(1'b0));
FDRE \wrap_cnt_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [2]),
.Q(\wrap_cnt_r_reg_n_0_[2] ),
.R(1'b0));
FDRE \wrap_cnt_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [3]),
.Q(\wrap_cnt_r_reg_n_0_[3] ),
.R(1'b0));
FDRE \wrap_second_len_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [0]),
.Q(\wrap_second_len_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [1]),
.Q(\wrap_second_len_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [2]),
.Q(\wrap_second_len_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [3]),
.Q(\wrap_second_len_r_reg[3]_0 [3]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axi_register_slice" *)
module zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axi_register_slice
(s_axi_awready,
s_axi_arready,
si_rs_awvalid,
s_axi_bvalid,
si_rs_bready,
si_rs_arvalid,
s_axi_rvalid,
si_rs_rready,
Q,
\s_arid_r_reg[11] ,
\axaddr_incr_reg[11] ,
CO,
O,
\axaddr_incr_reg[7] ,
\axaddr_incr_reg[11]_0 ,
\axaddr_incr_reg[7]_0 ,
\axaddr_incr_reg[3] ,
D,
\wrap_second_len_r_reg[3] ,
\wrap_cnt_r_reg[3] ,
axaddr_offset,
\axlen_cnt_reg[3] ,
next_pending_r_reg,
next_pending_r_reg_0,
\wrap_cnt_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_0 ,
\wrap_cnt_r_reg[3]_1 ,
axaddr_offset_0,
\axlen_cnt_reg[3]_0 ,
next_pending_r_reg_1,
next_pending_r_reg_2,
\cnt_read_reg[3]_rep__0 ,
\axaddr_offset_r_reg[3] ,
\wrap_boundary_axaddr_r_reg[6] ,
\axaddr_offset_r_reg[3]_0 ,
\wrap_boundary_axaddr_r_reg[6]_0 ,
\m_axi_awaddr[10] ,
\m_axi_araddr[10] ,
\s_axi_bid[11] ,
\s_axi_rid[11] ,
aclk,
aresetn,
\state_reg[0]_rep ,
\state_reg[1]_rep ,
\state_reg[1] ,
\cnt_read_reg[4]_rep__0 ,
s_axi_rready,
b_push,
s_axi_awvalid,
S,
\m_payload_i_reg[3] ,
\wrap_second_len_r_reg[3]_1 ,
\state_reg[1]_0 ,
wrap_second_len,
\axaddr_offset_r_reg[3]_1 ,
\state_reg[1]_rep_0 ,
\axaddr_offset_r_reg[3]_2 ,
\wrap_second_len_r_reg[3]_2 ,
wrap_second_len_1,
\axaddr_offset_r_reg[3]_3 ,
\state_reg[1]_rep_1 ,
\axaddr_offset_r_reg[3]_4 ,
\state_reg[0]_rep_0 ,
\state_reg[1]_rep_2 ,
sel_first,
sel_first_2,
si_rs_bvalid,
s_axi_bready,
s_axi_arvalid,
s_axi_awid,
s_axi_awlen,
s_axi_awburst,
s_axi_awsize,
s_axi_awprot,
s_axi_awaddr,
s_axi_arid,
s_axi_arlen,
s_axi_arburst,
s_axi_arsize,
s_axi_arprot,
s_axi_araddr,
out,
\s_bresp_acc_reg[1] ,
r_push_r_reg,
\cnt_read_reg[4] ,
axaddr_incr_reg,
\axaddr_incr_reg[3]_0 ,
E,
m_valid_i_reg);
output s_axi_awready;
output s_axi_arready;
output si_rs_awvalid;
output s_axi_bvalid;
output si_rs_bready;
output si_rs_arvalid;
output s_axi_rvalid;
output si_rs_rready;
output [58:0]Q;
output [58:0]\s_arid_r_reg[11] ;
output [7:0]\axaddr_incr_reg[11] ;
output [0:0]CO;
output [3:0]O;
output [3:0]\axaddr_incr_reg[7] ;
output [3:0]\axaddr_incr_reg[11]_0 ;
output [0:0]\axaddr_incr_reg[7]_0 ;
output [3:0]\axaddr_incr_reg[3] ;
output [2:0]D;
output [2:0]\wrap_second_len_r_reg[3] ;
output \wrap_cnt_r_reg[3] ;
output [2:0]axaddr_offset;
output \axlen_cnt_reg[3] ;
output next_pending_r_reg;
output next_pending_r_reg_0;
output [2:0]\wrap_cnt_r_reg[3]_0 ;
output [2:0]\wrap_second_len_r_reg[3]_0 ;
output \wrap_cnt_r_reg[3]_1 ;
output [2:0]axaddr_offset_0;
output \axlen_cnt_reg[3]_0 ;
output next_pending_r_reg_1;
output next_pending_r_reg_2;
output \cnt_read_reg[3]_rep__0 ;
output \axaddr_offset_r_reg[3] ;
output [6:0]\wrap_boundary_axaddr_r_reg[6] ;
output \axaddr_offset_r_reg[3]_0 ;
output [6:0]\wrap_boundary_axaddr_r_reg[6]_0 ;
output \m_axi_awaddr[10] ;
output \m_axi_araddr[10] ;
output [13:0]\s_axi_bid[11] ;
output [46:0]\s_axi_rid[11] ;
input aclk;
input aresetn;
input \state_reg[0]_rep ;
input \state_reg[1]_rep ;
input [1:0]\state_reg[1] ;
input \cnt_read_reg[4]_rep__0 ;
input s_axi_rready;
input b_push;
input s_axi_awvalid;
input [3:0]S;
input [3:0]\m_payload_i_reg[3] ;
input [2:0]\wrap_second_len_r_reg[3]_1 ;
input [1:0]\state_reg[1]_0 ;
input [0:0]wrap_second_len;
input [0:0]\axaddr_offset_r_reg[3]_1 ;
input \state_reg[1]_rep_0 ;
input [3:0]\axaddr_offset_r_reg[3]_2 ;
input [2:0]\wrap_second_len_r_reg[3]_2 ;
input [0:0]wrap_second_len_1;
input [0:0]\axaddr_offset_r_reg[3]_3 ;
input \state_reg[1]_rep_1 ;
input [3:0]\axaddr_offset_r_reg[3]_4 ;
input \state_reg[0]_rep_0 ;
input \state_reg[1]_rep_2 ;
input sel_first;
input sel_first_2;
input si_rs_bvalid;
input s_axi_bready;
input s_axi_arvalid;
input [11:0]s_axi_awid;
input [7:0]s_axi_awlen;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awsize;
input [2:0]s_axi_awprot;
input [31:0]s_axi_awaddr;
input [11:0]s_axi_arid;
input [7:0]s_axi_arlen;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arsize;
input [2:0]s_axi_arprot;
input [31:0]s_axi_araddr;
input [11:0]out;
input [1:0]\s_bresp_acc_reg[1] ;
input [12:0]r_push_r_reg;
input [33:0]\cnt_read_reg[4] ;
input [3:0]axaddr_incr_reg;
input [3:0]\axaddr_incr_reg[3]_0 ;
input [0:0]E;
input [0:0]m_valid_i_reg;
wire [0:0]CO;
wire [2:0]D;
wire [0:0]E;
wire [3:0]O;
wire [58:0]Q;
wire [3:0]S;
wire aclk;
wire ar_pipe_n_2;
wire aresetn;
wire aw_pipe_n_1;
wire aw_pipe_n_97;
wire [3:0]axaddr_incr_reg;
wire [7:0]\axaddr_incr_reg[11] ;
wire [3:0]\axaddr_incr_reg[11]_0 ;
wire [3:0]\axaddr_incr_reg[3] ;
wire [3:0]\axaddr_incr_reg[3]_0 ;
wire [3:0]\axaddr_incr_reg[7] ;
wire [0:0]\axaddr_incr_reg[7]_0 ;
wire [2:0]axaddr_offset;
wire [2:0]axaddr_offset_0;
wire \axaddr_offset_r_reg[3] ;
wire \axaddr_offset_r_reg[3]_0 ;
wire [0:0]\axaddr_offset_r_reg[3]_1 ;
wire [3:0]\axaddr_offset_r_reg[3]_2 ;
wire [0:0]\axaddr_offset_r_reg[3]_3 ;
wire [3:0]\axaddr_offset_r_reg[3]_4 ;
wire \axlen_cnt_reg[3] ;
wire \axlen_cnt_reg[3]_0 ;
wire b_push;
wire \cnt_read_reg[3]_rep__0 ;
wire [33:0]\cnt_read_reg[4] ;
wire \cnt_read_reg[4]_rep__0 ;
wire \m_axi_araddr[10] ;
wire \m_axi_awaddr[10] ;
wire [3:0]\m_payload_i_reg[3] ;
wire [0:0]m_valid_i_reg;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire next_pending_r_reg_1;
wire next_pending_r_reg_2;
wire [11:0]out;
wire [12:0]r_push_r_reg;
wire [58:0]\s_arid_r_reg[11] ;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [1:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [1:0]s_axi_awsize;
wire s_axi_awvalid;
wire [13:0]\s_axi_bid[11] ;
wire s_axi_bready;
wire s_axi_bvalid;
wire [46:0]\s_axi_rid[11] ;
wire s_axi_rready;
wire s_axi_rvalid;
wire [1:0]\s_bresp_acc_reg[1] ;
wire sel_first;
wire sel_first_2;
wire si_rs_arvalid;
wire si_rs_awvalid;
wire si_rs_bready;
wire si_rs_bvalid;
wire si_rs_rready;
wire \state_reg[0]_rep ;
wire \state_reg[0]_rep_0 ;
wire [1:0]\state_reg[1] ;
wire [1:0]\state_reg[1]_0 ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire \state_reg[1]_rep_1 ;
wire \state_reg[1]_rep_2 ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6] ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6]_0 ;
wire \wrap_cnt_r_reg[3] ;
wire [2:0]\wrap_cnt_r_reg[3]_0 ;
wire \wrap_cnt_r_reg[3]_1 ;
wire [0:0]wrap_second_len;
wire [0:0]wrap_second_len_1;
wire [2:0]\wrap_second_len_r_reg[3] ;
wire [2:0]\wrap_second_len_r_reg[3]_0 ;
wire [2:0]\wrap_second_len_r_reg[3]_1 ;
wire [2:0]\wrap_second_len_r_reg[3]_2 ;
zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice ar_pipe
(.Q(\s_arid_r_reg[11] ),
.aclk(aclk),
.\aresetn_d_reg[0] (aw_pipe_n_1),
.\aresetn_d_reg[0]_0 (aw_pipe_n_97),
.\axaddr_incr_reg[11] (\axaddr_incr_reg[11]_0 ),
.\axaddr_incr_reg[3] (\axaddr_incr_reg[3] ),
.\axaddr_incr_reg[3]_0 (\axaddr_incr_reg[3]_0 ),
.\axaddr_incr_reg[7] (\axaddr_incr_reg[7] ),
.\axaddr_incr_reg[7]_0 (\axaddr_incr_reg[7]_0 ),
.\axaddr_offset_r_reg[0] (axaddr_offset_0[0]),
.\axaddr_offset_r_reg[1] (axaddr_offset_0[1]),
.\axaddr_offset_r_reg[2] (axaddr_offset_0[2]),
.\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3]_0 ),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3]_3 ),
.\axaddr_offset_r_reg[3]_1 (\axaddr_offset_r_reg[3]_4 ),
.\axlen_cnt_reg[3] (\axlen_cnt_reg[3]_0 ),
.\m_axi_araddr[10] (\m_axi_araddr[10] ),
.\m_payload_i_reg[3]_0 (\m_payload_i_reg[3] ),
.m_valid_i_reg_0(ar_pipe_n_2),
.m_valid_i_reg_1(m_valid_i_reg),
.next_pending_r_reg(next_pending_r_reg_1),
.next_pending_r_reg_0(next_pending_r_reg_2),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize),
.s_axi_arvalid(s_axi_arvalid),
.s_ready_i_reg_0(si_rs_arvalid),
.sel_first_2(sel_first_2),
.\state_reg[0]_rep (\state_reg[0]_rep_0 ),
.\state_reg[1] (\state_reg[1] ),
.\state_reg[1]_rep (\state_reg[1]_rep_1 ),
.\state_reg[1]_rep_0 (\state_reg[1]_rep_2 ),
.\wrap_boundary_axaddr_r_reg[6] (\wrap_boundary_axaddr_r_reg[6]_0 ),
.\wrap_cnt_r_reg[3] (\wrap_cnt_r_reg[3]_0 ),
.\wrap_cnt_r_reg[3]_0 (\wrap_cnt_r_reg[3]_1 ),
.wrap_second_len_1(wrap_second_len_1),
.\wrap_second_len_r_reg[3] (\wrap_second_len_r_reg[3]_0 ),
.\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3]_2 ));
zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice_0 aw_pipe
(.CO(CO),
.D(D),
.E(E),
.O(O),
.Q(Q),
.S(S),
.aclk(aclk),
.aresetn(aresetn),
.\aresetn_d_reg[1]_inv (aw_pipe_n_97),
.\aresetn_d_reg[1]_inv_0 (ar_pipe_n_2),
.axaddr_incr_reg(axaddr_incr_reg),
.\axaddr_incr_reg[11] (\axaddr_incr_reg[11] ),
.\axaddr_offset_r_reg[0] (axaddr_offset[0]),
.\axaddr_offset_r_reg[1] (axaddr_offset[1]),
.\axaddr_offset_r_reg[2] (axaddr_offset[2]),
.\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3] ),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3]_1 ),
.\axaddr_offset_r_reg[3]_1 (\axaddr_offset_r_reg[3]_2 ),
.\axlen_cnt_reg[3] (\axlen_cnt_reg[3] ),
.b_push(b_push),
.\m_axi_awaddr[10] (\m_axi_awaddr[10] ),
.m_valid_i_reg_0(si_rs_awvalid),
.next_pending_r_reg(next_pending_r_reg),
.next_pending_r_reg_0(next_pending_r_reg_0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize),
.s_axi_awvalid(s_axi_awvalid),
.s_ready_i_reg_0(aw_pipe_n_1),
.sel_first(sel_first),
.\state_reg[0]_rep (\state_reg[0]_rep ),
.\state_reg[1] (\state_reg[1]_0 ),
.\state_reg[1]_rep (\state_reg[1]_rep ),
.\state_reg[1]_rep_0 (\state_reg[1]_rep_0 ),
.\wrap_boundary_axaddr_r_reg[6] (\wrap_boundary_axaddr_r_reg[6] ),
.\wrap_cnt_r_reg[3] (\wrap_cnt_r_reg[3] ),
.wrap_second_len(wrap_second_len),
.\wrap_second_len_r_reg[3] (\wrap_second_len_r_reg[3] ),
.\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3]_1 ));
zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1 b_pipe
(.aclk(aclk),
.\aresetn_d_reg[0] (aw_pipe_n_1),
.\aresetn_d_reg[1]_inv (ar_pipe_n_2),
.out(out),
.\s_axi_bid[11] (\s_axi_bid[11] ),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.\s_bresp_acc_reg[1] (\s_bresp_acc_reg[1] ),
.si_rs_bvalid(si_rs_bvalid),
.\skid_buffer_reg[0]_0 (si_rs_bready));
zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2 r_pipe
(.aclk(aclk),
.\aresetn_d_reg[0] (aw_pipe_n_1),
.\aresetn_d_reg[1]_inv (ar_pipe_n_2),
.\cnt_read_reg[3]_rep__0 (\cnt_read_reg[3]_rep__0 ),
.\cnt_read_reg[4] (\cnt_read_reg[4] ),
.\cnt_read_reg[4]_rep__0 (\cnt_read_reg[4]_rep__0 ),
.r_push_r_reg(r_push_r_reg),
.\s_axi_rid[11] (\s_axi_rid[11] ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.\skid_buffer_reg[0]_0 (si_rs_rready));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axic_register_slice" *)
module zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice
(s_axi_arready,
s_ready_i_reg_0,
m_valid_i_reg_0,
Q,
\axaddr_incr_reg[7] ,
\axaddr_incr_reg[11] ,
\axaddr_incr_reg[7]_0 ,
\axaddr_incr_reg[3] ,
\wrap_cnt_r_reg[3] ,
\wrap_second_len_r_reg[3] ,
\wrap_cnt_r_reg[3]_0 ,
\axaddr_offset_r_reg[1] ,
\axaddr_offset_r_reg[0] ,
\axaddr_offset_r_reg[2] ,
\axlen_cnt_reg[3] ,
next_pending_r_reg,
next_pending_r_reg_0,
\axaddr_offset_r_reg[3] ,
\wrap_boundary_axaddr_r_reg[6] ,
\m_axi_araddr[10] ,
\aresetn_d_reg[0] ,
aclk,
\aresetn_d_reg[0]_0 ,
\state_reg[1] ,
\m_payload_i_reg[3]_0 ,
\wrap_second_len_r_reg[3]_0 ,
wrap_second_len_1,
\axaddr_offset_r_reg[3]_0 ,
\state_reg[1]_rep ,
\axaddr_offset_r_reg[3]_1 ,
\state_reg[0]_rep ,
\state_reg[1]_rep_0 ,
sel_first_2,
s_axi_arvalid,
s_axi_arid,
s_axi_arlen,
s_axi_arburst,
s_axi_arsize,
s_axi_arprot,
s_axi_araddr,
\axaddr_incr_reg[3]_0 ,
m_valid_i_reg_1);
output s_axi_arready;
output s_ready_i_reg_0;
output m_valid_i_reg_0;
output [58:0]Q;
output [3:0]\axaddr_incr_reg[7] ;
output [3:0]\axaddr_incr_reg[11] ;
output [0:0]\axaddr_incr_reg[7]_0 ;
output [3:0]\axaddr_incr_reg[3] ;
output [2:0]\wrap_cnt_r_reg[3] ;
output [2:0]\wrap_second_len_r_reg[3] ;
output \wrap_cnt_r_reg[3]_0 ;
output \axaddr_offset_r_reg[1] ;
output \axaddr_offset_r_reg[0] ;
output \axaddr_offset_r_reg[2] ;
output \axlen_cnt_reg[3] ;
output next_pending_r_reg;
output next_pending_r_reg_0;
output \axaddr_offset_r_reg[3] ;
output [6:0]\wrap_boundary_axaddr_r_reg[6] ;
output \m_axi_araddr[10] ;
input \aresetn_d_reg[0] ;
input aclk;
input \aresetn_d_reg[0]_0 ;
input [1:0]\state_reg[1] ;
input [3:0]\m_payload_i_reg[3]_0 ;
input [2:0]\wrap_second_len_r_reg[3]_0 ;
input [0:0]wrap_second_len_1;
input [0:0]\axaddr_offset_r_reg[3]_0 ;
input \state_reg[1]_rep ;
input [3:0]\axaddr_offset_r_reg[3]_1 ;
input \state_reg[0]_rep ;
input \state_reg[1]_rep_0 ;
input sel_first_2;
input s_axi_arvalid;
input [11:0]s_axi_arid;
input [7:0]s_axi_arlen;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arsize;
input [2:0]s_axi_arprot;
input [31:0]s_axi_araddr;
input [3:0]\axaddr_incr_reg[3]_0 ;
input [0:0]m_valid_i_reg_1;
wire [58:0]Q;
wire aclk;
wire \aresetn_d_reg[0] ;
wire \aresetn_d_reg[0]_0 ;
wire \axaddr_incr[0]_i_10__0_n_0 ;
wire \axaddr_incr[0]_i_12__0_n_0 ;
wire \axaddr_incr[0]_i_13__0_n_0 ;
wire \axaddr_incr[0]_i_14__0_n_0 ;
wire \axaddr_incr[0]_i_3__0_n_0 ;
wire \axaddr_incr[0]_i_4__0_n_0 ;
wire \axaddr_incr[0]_i_5__0_n_0 ;
wire \axaddr_incr[0]_i_6__0_n_0 ;
wire \axaddr_incr[0]_i_7__0_n_0 ;
wire \axaddr_incr[0]_i_8__0_n_0 ;
wire \axaddr_incr[0]_i_9__0_n_0 ;
wire \axaddr_incr[4]_i_10__0_n_0 ;
wire \axaddr_incr[4]_i_7__0_n_0 ;
wire \axaddr_incr[4]_i_8__0_n_0 ;
wire \axaddr_incr[4]_i_9__0_n_0 ;
wire \axaddr_incr[8]_i_10__0_n_0 ;
wire \axaddr_incr[8]_i_7__0_n_0 ;
wire \axaddr_incr[8]_i_8__0_n_0 ;
wire \axaddr_incr[8]_i_9__0_n_0 ;
wire \axaddr_incr_reg[0]_i_11__0_n_0 ;
wire \axaddr_incr_reg[0]_i_11__0_n_1 ;
wire \axaddr_incr_reg[0]_i_11__0_n_2 ;
wire \axaddr_incr_reg[0]_i_11__0_n_3 ;
wire \axaddr_incr_reg[0]_i_11__0_n_4 ;
wire \axaddr_incr_reg[0]_i_11__0_n_5 ;
wire \axaddr_incr_reg[0]_i_11__0_n_6 ;
wire \axaddr_incr_reg[0]_i_11__0_n_7 ;
wire \axaddr_incr_reg[0]_i_2__0_n_1 ;
wire \axaddr_incr_reg[0]_i_2__0_n_2 ;
wire \axaddr_incr_reg[0]_i_2__0_n_3 ;
wire [3:0]\axaddr_incr_reg[11] ;
wire [3:0]\axaddr_incr_reg[3] ;
wire [3:0]\axaddr_incr_reg[3]_0 ;
wire \axaddr_incr_reg[4]_i_6__0_n_0 ;
wire \axaddr_incr_reg[4]_i_6__0_n_1 ;
wire \axaddr_incr_reg[4]_i_6__0_n_2 ;
wire \axaddr_incr_reg[4]_i_6__0_n_3 ;
wire [3:0]\axaddr_incr_reg[7] ;
wire [0:0]\axaddr_incr_reg[7]_0 ;
wire \axaddr_incr_reg[8]_i_6__0_n_1 ;
wire \axaddr_incr_reg[8]_i_6__0_n_2 ;
wire \axaddr_incr_reg[8]_i_6__0_n_3 ;
wire \axaddr_offset_r[0]_i_2__0_n_0 ;
wire \axaddr_offset_r[1]_i_2__0_n_0 ;
wire \axaddr_offset_r[2]_i_2__0_n_0 ;
wire \axaddr_offset_r[2]_i_3__0_n_0 ;
wire \axaddr_offset_r_reg[0] ;
wire \axaddr_offset_r_reg[1] ;
wire \axaddr_offset_r_reg[2] ;
wire \axaddr_offset_r_reg[3] ;
wire [0:0]\axaddr_offset_r_reg[3]_0 ;
wire [3:0]\axaddr_offset_r_reg[3]_1 ;
wire \axlen_cnt_reg[3] ;
wire \m_axi_araddr[10] ;
wire \m_payload_i[0]_i_1__0_n_0 ;
wire \m_payload_i[10]_i_1__0_n_0 ;
wire \m_payload_i[11]_i_1__0_n_0 ;
wire \m_payload_i[12]_i_1__0_n_0 ;
wire \m_payload_i[13]_i_1__1_n_0 ;
wire \m_payload_i[14]_i_1__0_n_0 ;
wire \m_payload_i[15]_i_1__0_n_0 ;
wire \m_payload_i[16]_i_1__0_n_0 ;
wire \m_payload_i[17]_i_1__0_n_0 ;
wire \m_payload_i[18]_i_1__0_n_0 ;
wire \m_payload_i[19]_i_1__0_n_0 ;
wire \m_payload_i[1]_i_1__0_n_0 ;
wire \m_payload_i[20]_i_1__0_n_0 ;
wire \m_payload_i[21]_i_1__0_n_0 ;
wire \m_payload_i[22]_i_1__0_n_0 ;
wire \m_payload_i[23]_i_1__0_n_0 ;
wire \m_payload_i[24]_i_1__0_n_0 ;
wire \m_payload_i[25]_i_1__0_n_0 ;
wire \m_payload_i[26]_i_1__0_n_0 ;
wire \m_payload_i[27]_i_1__0_n_0 ;
wire \m_payload_i[28]_i_1__0_n_0 ;
wire \m_payload_i[29]_i_1__0_n_0 ;
wire \m_payload_i[2]_i_1__0_n_0 ;
wire \m_payload_i[30]_i_1__0_n_0 ;
wire \m_payload_i[31]_i_2__0_n_0 ;
wire \m_payload_i[32]_i_1__0_n_0 ;
wire \m_payload_i[33]_i_1__0_n_0 ;
wire \m_payload_i[34]_i_1__0_n_0 ;
wire \m_payload_i[35]_i_1__0_n_0 ;
wire \m_payload_i[36]_i_1__0_n_0 ;
wire \m_payload_i[38]_i_1__0_n_0 ;
wire \m_payload_i[39]_i_1__0_n_0 ;
wire \m_payload_i[3]_i_1__0_n_0 ;
wire \m_payload_i[44]_i_1__0_n_0 ;
wire \m_payload_i[45]_i_1__0_n_0 ;
wire \m_payload_i[46]_i_1__1_n_0 ;
wire \m_payload_i[47]_i_1__0_n_0 ;
wire \m_payload_i[48]_i_1__0_n_0 ;
wire \m_payload_i[49]_i_1__0_n_0 ;
wire \m_payload_i[4]_i_1__0_n_0 ;
wire \m_payload_i[50]_i_1__0_n_0 ;
wire \m_payload_i[51]_i_1__0_n_0 ;
wire \m_payload_i[53]_i_1__0_n_0 ;
wire \m_payload_i[54]_i_1__0_n_0 ;
wire \m_payload_i[55]_i_1__0_n_0 ;
wire \m_payload_i[56]_i_1__0_n_0 ;
wire \m_payload_i[57]_i_1__0_n_0 ;
wire \m_payload_i[58]_i_1__0_n_0 ;
wire \m_payload_i[59]_i_1__0_n_0 ;
wire \m_payload_i[5]_i_1__0_n_0 ;
wire \m_payload_i[60]_i_1__0_n_0 ;
wire \m_payload_i[61]_i_1__0_n_0 ;
wire \m_payload_i[62]_i_1__0_n_0 ;
wire \m_payload_i[63]_i_1__0_n_0 ;
wire \m_payload_i[64]_i_1__0_n_0 ;
wire \m_payload_i[6]_i_1__0_n_0 ;
wire \m_payload_i[7]_i_1__0_n_0 ;
wire \m_payload_i[8]_i_1__0_n_0 ;
wire \m_payload_i[9]_i_1__0_n_0 ;
wire [3:0]\m_payload_i_reg[3]_0 ;
wire m_valid_i0;
wire m_valid_i_reg_0;
wire [0:0]m_valid_i_reg_1;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [1:0]s_axi_arsize;
wire s_axi_arvalid;
wire s_ready_i0;
wire s_ready_i_reg_0;
wire sel_first_2;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[47] ;
wire \skid_buffer_reg_n_0_[48] ;
wire \skid_buffer_reg_n_0_[49] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[50] ;
wire \skid_buffer_reg_n_0_[51] ;
wire \skid_buffer_reg_n_0_[53] ;
wire \skid_buffer_reg_n_0_[54] ;
wire \skid_buffer_reg_n_0_[55] ;
wire \skid_buffer_reg_n_0_[56] ;
wire \skid_buffer_reg_n_0_[57] ;
wire \skid_buffer_reg_n_0_[58] ;
wire \skid_buffer_reg_n_0_[59] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[60] ;
wire \skid_buffer_reg_n_0_[61] ;
wire \skid_buffer_reg_n_0_[62] ;
wire \skid_buffer_reg_n_0_[63] ;
wire \skid_buffer_reg_n_0_[64] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
wire \state_reg[0]_rep ;
wire [1:0]\state_reg[1] ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire \wrap_boundary_axaddr_r[3]_i_2__0_n_0 ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6] ;
wire \wrap_cnt_r[3]_i_3__0_n_0 ;
wire [2:0]\wrap_cnt_r_reg[3] ;
wire \wrap_cnt_r_reg[3]_0 ;
wire [0:0]wrap_second_len_1;
wire \wrap_second_len_r[0]_i_2__0_n_0 ;
wire \wrap_second_len_r[0]_i_3__0_n_0 ;
wire \wrap_second_len_r[0]_i_4__0_n_0 ;
wire \wrap_second_len_r[3]_i_2__0_n_0 ;
wire [2:0]\wrap_second_len_r_reg[3] ;
wire [2:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:3]\NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED ;
FDRE #(
.INIT(1'b1))
\aresetn_d_reg[1]_inv
(.C(aclk),
.CE(1'b1),
.D(\aresetn_d_reg[0]_0 ),
.Q(m_valid_i_reg_0),
.R(1'b0));
LUT5 #(
.INIT(32'hFFE100E1))
\axaddr_incr[0]_i_10__0
(.I0(Q[36]),
.I1(Q[35]),
.I2(\axaddr_incr_reg[3]_0 [0]),
.I3(sel_first_2),
.I4(\axaddr_incr_reg[0]_i_11__0_n_7 ),
.O(\axaddr_incr[0]_i_10__0_n_0 ));
LUT3 #(
.INIT(8'h2A))
\axaddr_incr[0]_i_12__0
(.I0(Q[2]),
.I1(Q[35]),
.I2(Q[36]),
.O(\axaddr_incr[0]_i_12__0_n_0 ));
LUT2 #(
.INIT(4'h2))
\axaddr_incr[0]_i_13__0
(.I0(Q[1]),
.I1(Q[36]),
.O(\axaddr_incr[0]_i_13__0_n_0 ));
LUT3 #(
.INIT(8'h02))
\axaddr_incr[0]_i_14__0
(.I0(Q[0]),
.I1(Q[35]),
.I2(Q[36]),
.O(\axaddr_incr[0]_i_14__0_n_0 ));
LUT3 #(
.INIT(8'h08))
\axaddr_incr[0]_i_3__0
(.I0(Q[35]),
.I1(Q[36]),
.I2(sel_first_2),
.O(\axaddr_incr[0]_i_3__0_n_0 ));
LUT3 #(
.INIT(8'h04))
\axaddr_incr[0]_i_4__0
(.I0(Q[35]),
.I1(Q[36]),
.I2(sel_first_2),
.O(\axaddr_incr[0]_i_4__0_n_0 ));
LUT3 #(
.INIT(8'h04))
\axaddr_incr[0]_i_5__0
(.I0(Q[36]),
.I1(Q[35]),
.I2(sel_first_2),
.O(\axaddr_incr[0]_i_5__0_n_0 ));
LUT3 #(
.INIT(8'h01))
\axaddr_incr[0]_i_6__0
(.I0(Q[35]),
.I1(Q[36]),
.I2(sel_first_2),
.O(\axaddr_incr[0]_i_6__0_n_0 ));
LUT5 #(
.INIT(32'hFF780078))
\axaddr_incr[0]_i_7__0
(.I0(Q[36]),
.I1(Q[35]),
.I2(\axaddr_incr_reg[3]_0 [3]),
.I3(sel_first_2),
.I4(\axaddr_incr_reg[0]_i_11__0_n_4 ),
.O(\axaddr_incr[0]_i_7__0_n_0 ));
LUT5 #(
.INIT(32'hFFD200D2))
\axaddr_incr[0]_i_8__0
(.I0(Q[36]),
.I1(Q[35]),
.I2(\axaddr_incr_reg[3]_0 [2]),
.I3(sel_first_2),
.I4(\axaddr_incr_reg[0]_i_11__0_n_5 ),
.O(\axaddr_incr[0]_i_8__0_n_0 ));
LUT5 #(
.INIT(32'hFFD200D2))
\axaddr_incr[0]_i_9__0
(.I0(Q[35]),
.I1(Q[36]),
.I2(\axaddr_incr_reg[3]_0 [1]),
.I3(sel_first_2),
.I4(\axaddr_incr_reg[0]_i_11__0_n_6 ),
.O(\axaddr_incr[0]_i_9__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_10__0
(.I0(Q[4]),
.O(\axaddr_incr[4]_i_10__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_7__0
(.I0(Q[7]),
.O(\axaddr_incr[4]_i_7__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_8__0
(.I0(Q[6]),
.O(\axaddr_incr[4]_i_8__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_9__0
(.I0(Q[5]),
.O(\axaddr_incr[4]_i_9__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_10__0
(.I0(Q[8]),
.O(\axaddr_incr[8]_i_10__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_7__0
(.I0(Q[11]),
.O(\axaddr_incr[8]_i_7__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_8__0
(.I0(Q[10]),
.O(\axaddr_incr[8]_i_8__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_9__0
(.I0(Q[9]),
.O(\axaddr_incr[8]_i_9__0_n_0 ));
CARRY4 \axaddr_incr_reg[0]_i_11__0
(.CI(1'b0),
.CO({\axaddr_incr_reg[0]_i_11__0_n_0 ,\axaddr_incr_reg[0]_i_11__0_n_1 ,\axaddr_incr_reg[0]_i_11__0_n_2 ,\axaddr_incr_reg[0]_i_11__0_n_3 }),
.CYINIT(1'b0),
.DI({Q[3],\axaddr_incr[0]_i_12__0_n_0 ,\axaddr_incr[0]_i_13__0_n_0 ,\axaddr_incr[0]_i_14__0_n_0 }),
.O({\axaddr_incr_reg[0]_i_11__0_n_4 ,\axaddr_incr_reg[0]_i_11__0_n_5 ,\axaddr_incr_reg[0]_i_11__0_n_6 ,\axaddr_incr_reg[0]_i_11__0_n_7 }),
.S(\m_payload_i_reg[3]_0 ));
CARRY4 \axaddr_incr_reg[0]_i_2__0
(.CI(1'b0),
.CO({\axaddr_incr_reg[7]_0 ,\axaddr_incr_reg[0]_i_2__0_n_1 ,\axaddr_incr_reg[0]_i_2__0_n_2 ,\axaddr_incr_reg[0]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({\axaddr_incr[0]_i_3__0_n_0 ,\axaddr_incr[0]_i_4__0_n_0 ,\axaddr_incr[0]_i_5__0_n_0 ,\axaddr_incr[0]_i_6__0_n_0 }),
.O(\axaddr_incr_reg[3] ),
.S({\axaddr_incr[0]_i_7__0_n_0 ,\axaddr_incr[0]_i_8__0_n_0 ,\axaddr_incr[0]_i_9__0_n_0 ,\axaddr_incr[0]_i_10__0_n_0 }));
CARRY4 \axaddr_incr_reg[4]_i_6__0
(.CI(\axaddr_incr_reg[0]_i_11__0_n_0 ),
.CO({\axaddr_incr_reg[4]_i_6__0_n_0 ,\axaddr_incr_reg[4]_i_6__0_n_1 ,\axaddr_incr_reg[4]_i_6__0_n_2 ,\axaddr_incr_reg[4]_i_6__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\axaddr_incr_reg[7] ),
.S({\axaddr_incr[4]_i_7__0_n_0 ,\axaddr_incr[4]_i_8__0_n_0 ,\axaddr_incr[4]_i_9__0_n_0 ,\axaddr_incr[4]_i_10__0_n_0 }));
CARRY4 \axaddr_incr_reg[8]_i_6__0
(.CI(\axaddr_incr_reg[4]_i_6__0_n_0 ),
.CO({\NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED [3],\axaddr_incr_reg[8]_i_6__0_n_1 ,\axaddr_incr_reg[8]_i_6__0_n_2 ,\axaddr_incr_reg[8]_i_6__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\axaddr_incr_reg[11] ),
.S({\axaddr_incr[8]_i_7__0_n_0 ,\axaddr_incr[8]_i_8__0_n_0 ,\axaddr_incr[8]_i_9__0_n_0 ,\axaddr_incr[8]_i_10__0_n_0 }));
LUT6 #(
.INIT(64'hF0F0F0F0F088F0F0))
\axaddr_offset_r[0]_i_1__0
(.I0(\axaddr_offset_r[0]_i_2__0_n_0 ),
.I1(Q[39]),
.I2(\axaddr_offset_r_reg[3]_1 [0]),
.I3(\state_reg[1] [1]),
.I4(s_ready_i_reg_0),
.I5(\state_reg[1] [0]),
.O(\axaddr_offset_r_reg[0] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[0]_i_2__0
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[35]),
.I3(Q[2]),
.I4(Q[36]),
.I5(Q[0]),
.O(\axaddr_offset_r[0]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAC00FFFFAC000000))
\axaddr_offset_r[1]_i_1__0
(.I0(\axaddr_offset_r[2]_i_3__0_n_0 ),
.I1(\axaddr_offset_r[1]_i_2__0_n_0 ),
.I2(Q[35]),
.I3(Q[40]),
.I4(\state_reg[1]_rep ),
.I5(\axaddr_offset_r_reg[3]_1 [1]),
.O(\axaddr_offset_r_reg[1] ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[1]_i_2__0
(.I0(Q[3]),
.I1(Q[36]),
.I2(Q[1]),
.O(\axaddr_offset_r[1]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAC00FFFFAC000000))
\axaddr_offset_r[2]_i_1__0
(.I0(\axaddr_offset_r[2]_i_2__0_n_0 ),
.I1(\axaddr_offset_r[2]_i_3__0_n_0 ),
.I2(Q[35]),
.I3(Q[41]),
.I4(\state_reg[1]_rep ),
.I5(\axaddr_offset_r_reg[3]_1 [2]),
.O(\axaddr_offset_r_reg[2] ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[2]_i_2__0
(.I0(Q[5]),
.I1(Q[36]),
.I2(Q[3]),
.O(\axaddr_offset_r[2]_i_2__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[2]_i_3__0
(.I0(Q[4]),
.I1(Q[36]),
.I2(Q[2]),
.O(\axaddr_offset_r[2]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[3]_i_2__0
(.I0(Q[6]),
.I1(Q[4]),
.I2(Q[35]),
.I3(Q[5]),
.I4(Q[36]),
.I5(Q[3]),
.O(\axaddr_offset_r_reg[3] ));
LUT4 #(
.INIT(16'hFFDF))
\axlen_cnt[3]_i_2__0
(.I0(Q[42]),
.I1(\state_reg[0]_rep ),
.I2(s_ready_i_reg_0),
.I3(\state_reg[1]_rep_0 ),
.O(\axlen_cnt_reg[3] ));
LUT2 #(
.INIT(4'h2))
\m_axi_araddr[11]_INST_0_i_1
(.I0(Q[37]),
.I1(sel_first_2),
.O(\m_axi_araddr[10] ));
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1__0
(.I0(s_axi_araddr[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(\m_payload_i[0]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1__0
(.I0(s_axi_araddr[10]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(\m_payload_i[10]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1__0
(.I0(s_axi_araddr[11]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(\m_payload_i[11]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1__0
(.I0(s_axi_araddr[12]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(\m_payload_i[12]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1__1
(.I0(s_axi_araddr[13]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(\m_payload_i[13]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1__0
(.I0(s_axi_araddr[14]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(\m_payload_i[14]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1__0
(.I0(s_axi_araddr[15]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(\m_payload_i[15]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1__0
(.I0(s_axi_araddr[16]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(\m_payload_i[16]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1__0
(.I0(s_axi_araddr[17]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(\m_payload_i[17]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1__0
(.I0(s_axi_araddr[18]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(\m_payload_i[18]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1__0
(.I0(s_axi_araddr[19]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(\m_payload_i[19]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1__0
(.I0(s_axi_araddr[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(\m_payload_i[1]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1__0
(.I0(s_axi_araddr[20]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(\m_payload_i[20]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1__0
(.I0(s_axi_araddr[21]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(\m_payload_i[21]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1__0
(.I0(s_axi_araddr[22]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(\m_payload_i[22]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1__0
(.I0(s_axi_araddr[23]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(\m_payload_i[23]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1__0
(.I0(s_axi_araddr[24]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(\m_payload_i[24]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1__0
(.I0(s_axi_araddr[25]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(\m_payload_i[25]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1__0
(.I0(s_axi_araddr[26]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(\m_payload_i[26]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1__0
(.I0(s_axi_araddr[27]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(\m_payload_i[27]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1__0
(.I0(s_axi_araddr[28]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(\m_payload_i[28]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1__0
(.I0(s_axi_araddr[29]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(\m_payload_i[29]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1__0
(.I0(s_axi_araddr[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(\m_payload_i[2]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1__0
(.I0(s_axi_araddr[30]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(\m_payload_i[30]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_2__0
(.I0(s_axi_araddr[31]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(\m_payload_i[31]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1__0
(.I0(s_axi_arprot[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(\m_payload_i[32]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1__0
(.I0(s_axi_arprot[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(\m_payload_i[33]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1__0
(.I0(s_axi_arprot[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(\m_payload_i[34]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1__0
(.I0(s_axi_arsize[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(\m_payload_i[35]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1__0
(.I0(s_axi_arsize[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(\m_payload_i[36]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1__0
(.I0(s_axi_arburst[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(\m_payload_i[38]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1__0
(.I0(s_axi_arburst[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(\m_payload_i[39]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1__0
(.I0(s_axi_araddr[3]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(\m_payload_i[3]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1__0
(.I0(s_axi_arlen[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(\m_payload_i[44]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1__0
(.I0(s_axi_arlen[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(\m_payload_i[45]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_1__1
(.I0(s_axi_arlen[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(\m_payload_i[46]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[47]_i_1__0
(.I0(s_axi_arlen[3]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[47] ),
.O(\m_payload_i[47]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[48]_i_1__0
(.I0(s_axi_arlen[4]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[48] ),
.O(\m_payload_i[48]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[49]_i_1__0
(.I0(s_axi_arlen[5]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[49] ),
.O(\m_payload_i[49]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1__0
(.I0(s_axi_araddr[4]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(\m_payload_i[4]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[50]_i_1__0
(.I0(s_axi_arlen[6]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[50] ),
.O(\m_payload_i[50]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[51]_i_1__0
(.I0(s_axi_arlen[7]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[51] ),
.O(\m_payload_i[51]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[53]_i_1__0
(.I0(s_axi_arid[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[53] ),
.O(\m_payload_i[53]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[54]_i_1__0
(.I0(s_axi_arid[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[54] ),
.O(\m_payload_i[54]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[55]_i_1__0
(.I0(s_axi_arid[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[55] ),
.O(\m_payload_i[55]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[56]_i_1__0
(.I0(s_axi_arid[3]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[56] ),
.O(\m_payload_i[56]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[57]_i_1__0
(.I0(s_axi_arid[4]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[57] ),
.O(\m_payload_i[57]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[58]_i_1__0
(.I0(s_axi_arid[5]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[58] ),
.O(\m_payload_i[58]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[59]_i_1__0
(.I0(s_axi_arid[6]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[59] ),
.O(\m_payload_i[59]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1__0
(.I0(s_axi_araddr[5]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(\m_payload_i[5]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[60]_i_1__0
(.I0(s_axi_arid[7]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[60] ),
.O(\m_payload_i[60]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[61]_i_1__0
(.I0(s_axi_arid[8]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[61] ),
.O(\m_payload_i[61]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[62]_i_1__0
(.I0(s_axi_arid[9]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[62] ),
.O(\m_payload_i[62]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[63]_i_1__0
(.I0(s_axi_arid[10]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[63] ),
.O(\m_payload_i[63]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[64]_i_1__0
(.I0(s_axi_arid[11]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[64] ),
.O(\m_payload_i[64]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1__0
(.I0(s_axi_araddr[6]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(\m_payload_i[6]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1__0
(.I0(s_axi_araddr[7]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(\m_payload_i[7]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1__0
(.I0(s_axi_araddr[8]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(\m_payload_i[8]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1__0
(.I0(s_axi_araddr[9]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(\m_payload_i[9]_i_1__0_n_0 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[0]_i_1__0_n_0 ),
.Q(Q[0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[10]_i_1__0_n_0 ),
.Q(Q[10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[11]_i_1__0_n_0 ),
.Q(Q[11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[12]_i_1__0_n_0 ),
.Q(Q[12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[13]_i_1__1_n_0 ),
.Q(Q[13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[14]_i_1__0_n_0 ),
.Q(Q[14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[15]_i_1__0_n_0 ),
.Q(Q[15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[16]_i_1__0_n_0 ),
.Q(Q[16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[17]_i_1__0_n_0 ),
.Q(Q[17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[18]_i_1__0_n_0 ),
.Q(Q[18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[19]_i_1__0_n_0 ),
.Q(Q[19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[1]_i_1__0_n_0 ),
.Q(Q[1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[20]_i_1__0_n_0 ),
.Q(Q[20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[21]_i_1__0_n_0 ),
.Q(Q[21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[22]_i_1__0_n_0 ),
.Q(Q[22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[23]_i_1__0_n_0 ),
.Q(Q[23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[24]_i_1__0_n_0 ),
.Q(Q[24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[25]_i_1__0_n_0 ),
.Q(Q[25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[26]_i_1__0_n_0 ),
.Q(Q[26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[27]_i_1__0_n_0 ),
.Q(Q[27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[28]_i_1__0_n_0 ),
.Q(Q[28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[29]_i_1__0_n_0 ),
.Q(Q[29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[2]_i_1__0_n_0 ),
.Q(Q[2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[30]_i_1__0_n_0 ),
.Q(Q[30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[31]_i_2__0_n_0 ),
.Q(Q[31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[32]_i_1__0_n_0 ),
.Q(Q[32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[33]_i_1__0_n_0 ),
.Q(Q[33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[34]_i_1__0_n_0 ),
.Q(Q[34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[35]_i_1__0_n_0 ),
.Q(Q[35]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[36]_i_1__0_n_0 ),
.Q(Q[36]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[38]_i_1__0_n_0 ),
.Q(Q[37]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[39]_i_1__0_n_0 ),
.Q(Q[38]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[3]_i_1__0_n_0 ),
.Q(Q[3]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[44]_i_1__0_n_0 ),
.Q(Q[39]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[45]_i_1__0_n_0 ),
.Q(Q[40]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[46]_i_1__1_n_0 ),
.Q(Q[41]),
.R(1'b0));
FDRE \m_payload_i_reg[47]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[47]_i_1__0_n_0 ),
.Q(Q[42]),
.R(1'b0));
FDRE \m_payload_i_reg[48]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[48]_i_1__0_n_0 ),
.Q(Q[43]),
.R(1'b0));
FDRE \m_payload_i_reg[49]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[49]_i_1__0_n_0 ),
.Q(Q[44]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[4]_i_1__0_n_0 ),
.Q(Q[4]),
.R(1'b0));
FDRE \m_payload_i_reg[50]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[50]_i_1__0_n_0 ),
.Q(Q[45]),
.R(1'b0));
FDRE \m_payload_i_reg[51]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[51]_i_1__0_n_0 ),
.Q(Q[46]),
.R(1'b0));
FDRE \m_payload_i_reg[53]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[53]_i_1__0_n_0 ),
.Q(Q[47]),
.R(1'b0));
FDRE \m_payload_i_reg[54]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[54]_i_1__0_n_0 ),
.Q(Q[48]),
.R(1'b0));
FDRE \m_payload_i_reg[55]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[55]_i_1__0_n_0 ),
.Q(Q[49]),
.R(1'b0));
FDRE \m_payload_i_reg[56]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[56]_i_1__0_n_0 ),
.Q(Q[50]),
.R(1'b0));
FDRE \m_payload_i_reg[57]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[57]_i_1__0_n_0 ),
.Q(Q[51]),
.R(1'b0));
FDRE \m_payload_i_reg[58]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[58]_i_1__0_n_0 ),
.Q(Q[52]),
.R(1'b0));
FDRE \m_payload_i_reg[59]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[59]_i_1__0_n_0 ),
.Q(Q[53]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[5]_i_1__0_n_0 ),
.Q(Q[5]),
.R(1'b0));
FDRE \m_payload_i_reg[60]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[60]_i_1__0_n_0 ),
.Q(Q[54]),
.R(1'b0));
FDRE \m_payload_i_reg[61]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[61]_i_1__0_n_0 ),
.Q(Q[55]),
.R(1'b0));
FDRE \m_payload_i_reg[62]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[62]_i_1__0_n_0 ),
.Q(Q[56]),
.R(1'b0));
FDRE \m_payload_i_reg[63]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[63]_i_1__0_n_0 ),
.Q(Q[57]),
.R(1'b0));
FDRE \m_payload_i_reg[64]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[64]_i_1__0_n_0 ),
.Q(Q[58]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[6]_i_1__0_n_0 ),
.Q(Q[6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[7]_i_1__0_n_0 ),
.Q(Q[7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[8]_i_1__0_n_0 ),
.Q(Q[8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[9]_i_1__0_n_0 ),
.Q(Q[9]),
.R(1'b0));
LUT5 #(
.INIT(32'hBFFFBBBB))
m_valid_i_i_1__0
(.I0(s_axi_arvalid),
.I1(s_axi_arready),
.I2(\state_reg[0]_rep ),
.I3(\state_reg[1]_rep_0 ),
.I4(s_ready_i_reg_0),
.O(m_valid_i0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(s_ready_i_reg_0),
.R(m_valid_i_reg_0));
LUT5 #(
.INIT(32'hFFFFFFFD))
next_pending_r_i_2__1
(.I0(next_pending_r_reg_0),
.I1(Q[46]),
.I2(Q[44]),
.I3(Q[45]),
.I4(Q[43]),
.O(next_pending_r_reg));
LUT4 #(
.INIT(16'h0001))
next_pending_r_i_2__2
(.I0(Q[41]),
.I1(Q[39]),
.I2(Q[40]),
.I3(Q[42]),
.O(next_pending_r_reg_0));
LUT5 #(
.INIT(32'hF444FFFF))
s_ready_i_i_1__0
(.I0(s_axi_arvalid),
.I1(s_axi_arready),
.I2(\state_reg[0]_rep ),
.I3(\state_reg[1]_rep_0 ),
.I4(s_ready_i_reg_0),
.O(s_ready_i0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(s_axi_arready),
.R(\aresetn_d_reg[0] ));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arprot[0]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arprot[1]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arprot[2]),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arsize[0]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arsize[1]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arburst[0]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arburst[1]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[0]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[1]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[2]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[47]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[3]),
.Q(\skid_buffer_reg_n_0_[47] ),
.R(1'b0));
FDRE \skid_buffer_reg[48]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[4]),
.Q(\skid_buffer_reg_n_0_[48] ),
.R(1'b0));
FDRE \skid_buffer_reg[49]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[5]),
.Q(\skid_buffer_reg_n_0_[49] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[50]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[6]),
.Q(\skid_buffer_reg_n_0_[50] ),
.R(1'b0));
FDRE \skid_buffer_reg[51]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[7]),
.Q(\skid_buffer_reg_n_0_[51] ),
.R(1'b0));
FDRE \skid_buffer_reg[53]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[0]),
.Q(\skid_buffer_reg_n_0_[53] ),
.R(1'b0));
FDRE \skid_buffer_reg[54]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[1]),
.Q(\skid_buffer_reg_n_0_[54] ),
.R(1'b0));
FDRE \skid_buffer_reg[55]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[2]),
.Q(\skid_buffer_reg_n_0_[55] ),
.R(1'b0));
FDRE \skid_buffer_reg[56]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[3]),
.Q(\skid_buffer_reg_n_0_[56] ),
.R(1'b0));
FDRE \skid_buffer_reg[57]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[4]),
.Q(\skid_buffer_reg_n_0_[57] ),
.R(1'b0));
FDRE \skid_buffer_reg[58]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[5]),
.Q(\skid_buffer_reg_n_0_[58] ),
.R(1'b0));
FDRE \skid_buffer_reg[59]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[6]),
.Q(\skid_buffer_reg_n_0_[59] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[60]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[7]),
.Q(\skid_buffer_reg_n_0_[60] ),
.R(1'b0));
FDRE \skid_buffer_reg[61]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[8]),
.Q(\skid_buffer_reg_n_0_[61] ),
.R(1'b0));
FDRE \skid_buffer_reg[62]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[9]),
.Q(\skid_buffer_reg_n_0_[62] ),
.R(1'b0));
FDRE \skid_buffer_reg[63]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[10]),
.Q(\skid_buffer_reg_n_0_[63] ),
.R(1'b0));
FDRE \skid_buffer_reg[64]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[11]),
.Q(\skid_buffer_reg_n_0_[64] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'hAA8A))
\wrap_boundary_axaddr_r[0]_i_1__0
(.I0(Q[0]),
.I1(Q[36]),
.I2(Q[39]),
.I3(Q[35]),
.O(\wrap_boundary_axaddr_r_reg[6] [0]));
LUT5 #(
.INIT(32'h8A888AAA))
\wrap_boundary_axaddr_r[1]_i_1__0
(.I0(Q[1]),
.I1(Q[36]),
.I2(Q[39]),
.I3(Q[35]),
.I4(Q[40]),
.O(\wrap_boundary_axaddr_r_reg[6] [1]));
LUT6 #(
.INIT(64'hA0A0202AAAAA202A))
\wrap_boundary_axaddr_r[2]_i_1__0
(.I0(Q[2]),
.I1(Q[40]),
.I2(Q[35]),
.I3(Q[41]),
.I4(Q[36]),
.I5(Q[39]),
.O(\wrap_boundary_axaddr_r_reg[6] [2]));
LUT6 #(
.INIT(64'h020202A2A2A202A2))
\wrap_boundary_axaddr_r[3]_i_1__0
(.I0(Q[3]),
.I1(\wrap_boundary_axaddr_r[3]_i_2__0_n_0 ),
.I2(Q[36]),
.I3(Q[40]),
.I4(Q[35]),
.I5(Q[39]),
.O(\wrap_boundary_axaddr_r_reg[6] [3]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\wrap_boundary_axaddr_r[3]_i_2__0
(.I0(Q[41]),
.I1(Q[35]),
.I2(Q[42]),
.O(\wrap_boundary_axaddr_r[3]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'h002A882A222AAA2A))
\wrap_boundary_axaddr_r[4]_i_1__0
(.I0(Q[4]),
.I1(Q[35]),
.I2(Q[42]),
.I3(Q[36]),
.I4(Q[40]),
.I5(Q[41]),
.O(\wrap_boundary_axaddr_r_reg[6] [4]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT5 #(
.INIT(32'h2A222AAA))
\wrap_boundary_axaddr_r[5]_i_1__0
(.I0(Q[5]),
.I1(Q[36]),
.I2(Q[41]),
.I3(Q[35]),
.I4(Q[42]),
.O(\wrap_boundary_axaddr_r_reg[6] [5]));
LUT4 #(
.INIT(16'h2AAA))
\wrap_boundary_axaddr_r[6]_i_1__0
(.I0(Q[6]),
.I1(Q[36]),
.I2(Q[42]),
.I3(Q[35]),
.O(\wrap_boundary_axaddr_r_reg[6] [6]));
LUT6 #(
.INIT(64'hBBBBBABBCCCCC0CC))
\wrap_cnt_r[0]_i_1__0
(.I0(\wrap_second_len_r[0]_i_2__0_n_0 ),
.I1(\wrap_second_len_r_reg[3]_0 [0]),
.I2(\state_reg[1] [0]),
.I3(s_ready_i_reg_0),
.I4(\state_reg[1] [1]),
.I5(\wrap_second_len_r[0]_i_3__0_n_0 ),
.O(\wrap_cnt_r_reg[3] [0]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'h9A))
\wrap_cnt_r[2]_i_1__0
(.I0(\wrap_second_len_r_reg[3] [1]),
.I1(\wrap_cnt_r_reg[3]_0 ),
.I2(wrap_second_len_1),
.O(\wrap_cnt_r_reg[3] [1]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT4 #(
.INIT(16'hA6AA))
\wrap_cnt_r[3]_i_1__0
(.I0(\wrap_second_len_r_reg[3] [2]),
.I1(wrap_second_len_1),
.I2(\wrap_cnt_r_reg[3]_0 ),
.I3(\wrap_second_len_r_reg[3] [1]),
.O(\wrap_cnt_r_reg[3] [2]));
LUT5 #(
.INIT(32'hAAAAAAAB))
\wrap_cnt_r[3]_i_2__0
(.I0(\wrap_cnt_r[3]_i_3__0_n_0 ),
.I1(\axaddr_offset_r_reg[1] ),
.I2(\axaddr_offset_r_reg[0] ),
.I3(\axaddr_offset_r_reg[3]_0 ),
.I4(\axaddr_offset_r_reg[2] ),
.O(\wrap_cnt_r_reg[3]_0 ));
LUT6 #(
.INIT(64'h0F0F0F0F0F880F0F))
\wrap_cnt_r[3]_i_3__0
(.I0(\axaddr_offset_r[0]_i_2__0_n_0 ),
.I1(Q[39]),
.I2(\wrap_second_len_r_reg[3]_0 [0]),
.I3(\state_reg[1] [1]),
.I4(s_ready_i_reg_0),
.I5(\state_reg[1] [0]),
.O(\wrap_cnt_r[3]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'h4444454444444044))
\wrap_second_len_r[0]_i_1__0
(.I0(\wrap_second_len_r[0]_i_2__0_n_0 ),
.I1(\wrap_second_len_r_reg[3]_0 [0]),
.I2(\state_reg[1] [0]),
.I3(s_ready_i_reg_0),
.I4(\state_reg[1] [1]),
.I5(\wrap_second_len_r[0]_i_3__0_n_0 ),
.O(\wrap_second_len_r_reg[3] [0]));
LUT6 #(
.INIT(64'hAAAAA8080000A808))
\wrap_second_len_r[0]_i_2__0
(.I0(\wrap_second_len_r[0]_i_4__0_n_0 ),
.I1(Q[0]),
.I2(Q[36]),
.I3(Q[2]),
.I4(Q[35]),
.I5(\axaddr_offset_r[1]_i_2__0_n_0 ),
.O(\wrap_second_len_r[0]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFBA))
\wrap_second_len_r[0]_i_3__0
(.I0(\axaddr_offset_r_reg[2] ),
.I1(\state_reg[1]_rep ),
.I2(\axaddr_offset_r_reg[3]_1 [3]),
.I3(\wrap_second_len_r[3]_i_2__0_n_0 ),
.I4(\axaddr_offset_r_reg[0] ),
.I5(\axaddr_offset_r_reg[1] ),
.O(\wrap_second_len_r[0]_i_3__0_n_0 ));
LUT4 #(
.INIT(16'h0020))
\wrap_second_len_r[0]_i_4__0
(.I0(Q[39]),
.I1(\state_reg[1] [0]),
.I2(s_ready_i_reg_0),
.I3(\state_reg[1] [1]),
.O(\wrap_second_len_r[0]_i_4__0_n_0 ));
LUT6 #(
.INIT(64'hEE10FFFFEE100000))
\wrap_second_len_r[2]_i_1__0
(.I0(\axaddr_offset_r_reg[1] ),
.I1(\axaddr_offset_r_reg[0] ),
.I2(\axaddr_offset_r_reg[3]_0 ),
.I3(\axaddr_offset_r_reg[2] ),
.I4(\state_reg[1]_rep ),
.I5(\wrap_second_len_r_reg[3]_0 [1]),
.O(\wrap_second_len_r_reg[3] [1]));
LUT6 #(
.INIT(64'hFFFFFFF444444444))
\wrap_second_len_r[3]_i_1__0
(.I0(\state_reg[1]_rep ),
.I1(\wrap_second_len_r_reg[3]_0 [2]),
.I2(\axaddr_offset_r_reg[0] ),
.I3(\axaddr_offset_r_reg[1] ),
.I4(\axaddr_offset_r_reg[2] ),
.I5(\wrap_second_len_r[3]_i_2__0_n_0 ),
.O(\wrap_second_len_r_reg[3] [2]));
LUT6 #(
.INIT(64'h00000000EEE222E2))
\wrap_second_len_r[3]_i_2__0
(.I0(\axaddr_offset_r[2]_i_2__0_n_0 ),
.I1(Q[35]),
.I2(Q[4]),
.I3(Q[36]),
.I4(Q[6]),
.I5(\axlen_cnt_reg[3] ),
.O(\wrap_second_len_r[3]_i_2__0_n_0 ));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axic_register_slice" *)
module zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice_0
(s_axi_awready,
s_ready_i_reg_0,
m_valid_i_reg_0,
Q,
\axaddr_incr_reg[11] ,
CO,
O,
D,
\wrap_second_len_r_reg[3] ,
\wrap_cnt_r_reg[3] ,
\axaddr_offset_r_reg[1] ,
\axaddr_offset_r_reg[0] ,
\axaddr_offset_r_reg[2] ,
\axlen_cnt_reg[3] ,
next_pending_r_reg,
next_pending_r_reg_0,
\axaddr_offset_r_reg[3] ,
\wrap_boundary_axaddr_r_reg[6] ,
\m_axi_awaddr[10] ,
\aresetn_d_reg[1]_inv ,
aclk,
\aresetn_d_reg[1]_inv_0 ,
aresetn,
\state_reg[0]_rep ,
\state_reg[1]_rep ,
b_push,
s_axi_awvalid,
S,
\wrap_second_len_r_reg[3]_0 ,
\state_reg[1] ,
wrap_second_len,
\axaddr_offset_r_reg[3]_0 ,
\state_reg[1]_rep_0 ,
\axaddr_offset_r_reg[3]_1 ,
sel_first,
s_axi_awid,
s_axi_awlen,
s_axi_awburst,
s_axi_awsize,
s_axi_awprot,
s_axi_awaddr,
axaddr_incr_reg,
E);
output s_axi_awready;
output s_ready_i_reg_0;
output m_valid_i_reg_0;
output [58:0]Q;
output [7:0]\axaddr_incr_reg[11] ;
output [0:0]CO;
output [3:0]O;
output [2:0]D;
output [2:0]\wrap_second_len_r_reg[3] ;
output \wrap_cnt_r_reg[3] ;
output \axaddr_offset_r_reg[1] ;
output \axaddr_offset_r_reg[0] ;
output \axaddr_offset_r_reg[2] ;
output \axlen_cnt_reg[3] ;
output next_pending_r_reg;
output next_pending_r_reg_0;
output \axaddr_offset_r_reg[3] ;
output [6:0]\wrap_boundary_axaddr_r_reg[6] ;
output \m_axi_awaddr[10] ;
output \aresetn_d_reg[1]_inv ;
input aclk;
input \aresetn_d_reg[1]_inv_0 ;
input aresetn;
input \state_reg[0]_rep ;
input \state_reg[1]_rep ;
input b_push;
input s_axi_awvalid;
input [3:0]S;
input [2:0]\wrap_second_len_r_reg[3]_0 ;
input [1:0]\state_reg[1] ;
input [0:0]wrap_second_len;
input [0:0]\axaddr_offset_r_reg[3]_0 ;
input \state_reg[1]_rep_0 ;
input [3:0]\axaddr_offset_r_reg[3]_1 ;
input sel_first;
input [11:0]s_axi_awid;
input [7:0]s_axi_awlen;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awsize;
input [2:0]s_axi_awprot;
input [31:0]s_axi_awaddr;
input [3:0]axaddr_incr_reg;
input [0:0]E;
wire [3:0]C;
wire [0:0]CO;
wire [2:0]D;
wire [0:0]E;
wire [3:0]O;
wire [58:0]Q;
wire [3:0]S;
wire aclk;
wire aresetn;
wire \aresetn_d_reg[1]_inv ;
wire \aresetn_d_reg[1]_inv_0 ;
wire \aresetn_d_reg_n_0_[0] ;
wire \axaddr_incr[0]_i_10_n_0 ;
wire \axaddr_incr[0]_i_12_n_0 ;
wire \axaddr_incr[0]_i_13_n_0 ;
wire \axaddr_incr[0]_i_14_n_0 ;
wire \axaddr_incr[0]_i_3_n_0 ;
wire \axaddr_incr[0]_i_4_n_0 ;
wire \axaddr_incr[0]_i_5_n_0 ;
wire \axaddr_incr[0]_i_6_n_0 ;
wire \axaddr_incr[0]_i_7_n_0 ;
wire \axaddr_incr[0]_i_8_n_0 ;
wire \axaddr_incr[0]_i_9_n_0 ;
wire \axaddr_incr[4]_i_10_n_0 ;
wire \axaddr_incr[4]_i_7_n_0 ;
wire \axaddr_incr[4]_i_8_n_0 ;
wire \axaddr_incr[4]_i_9_n_0 ;
wire \axaddr_incr[8]_i_10_n_0 ;
wire \axaddr_incr[8]_i_7_n_0 ;
wire \axaddr_incr[8]_i_8_n_0 ;
wire \axaddr_incr[8]_i_9_n_0 ;
wire [3:0]axaddr_incr_reg;
wire \axaddr_incr_reg[0]_i_11_n_0 ;
wire \axaddr_incr_reg[0]_i_11_n_1 ;
wire \axaddr_incr_reg[0]_i_11_n_2 ;
wire \axaddr_incr_reg[0]_i_11_n_3 ;
wire \axaddr_incr_reg[0]_i_2_n_1 ;
wire \axaddr_incr_reg[0]_i_2_n_2 ;
wire \axaddr_incr_reg[0]_i_2_n_3 ;
wire [7:0]\axaddr_incr_reg[11] ;
wire \axaddr_incr_reg[4]_i_6_n_0 ;
wire \axaddr_incr_reg[4]_i_6_n_1 ;
wire \axaddr_incr_reg[4]_i_6_n_2 ;
wire \axaddr_incr_reg[4]_i_6_n_3 ;
wire \axaddr_incr_reg[8]_i_6_n_1 ;
wire \axaddr_incr_reg[8]_i_6_n_2 ;
wire \axaddr_incr_reg[8]_i_6_n_3 ;
wire \axaddr_offset_r[0]_i_2_n_0 ;
wire \axaddr_offset_r[1]_i_2_n_0 ;
wire \axaddr_offset_r[2]_i_2_n_0 ;
wire \axaddr_offset_r[2]_i_3_n_0 ;
wire \axaddr_offset_r_reg[0] ;
wire \axaddr_offset_r_reg[1] ;
wire \axaddr_offset_r_reg[2] ;
wire \axaddr_offset_r_reg[3] ;
wire [0:0]\axaddr_offset_r_reg[3]_0 ;
wire [3:0]\axaddr_offset_r_reg[3]_1 ;
wire \axlen_cnt_reg[3] ;
wire b_push;
wire \m_axi_awaddr[10] ;
wire m_valid_i0;
wire m_valid_i_reg_0;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [1:0]s_axi_awsize;
wire s_axi_awvalid;
wire s_ready_i0;
wire s_ready_i_reg_0;
wire sel_first;
wire [64:0]skid_buffer;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[47] ;
wire \skid_buffer_reg_n_0_[48] ;
wire \skid_buffer_reg_n_0_[49] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[50] ;
wire \skid_buffer_reg_n_0_[51] ;
wire \skid_buffer_reg_n_0_[53] ;
wire \skid_buffer_reg_n_0_[54] ;
wire \skid_buffer_reg_n_0_[55] ;
wire \skid_buffer_reg_n_0_[56] ;
wire \skid_buffer_reg_n_0_[57] ;
wire \skid_buffer_reg_n_0_[58] ;
wire \skid_buffer_reg_n_0_[59] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[60] ;
wire \skid_buffer_reg_n_0_[61] ;
wire \skid_buffer_reg_n_0_[62] ;
wire \skid_buffer_reg_n_0_[63] ;
wire \skid_buffer_reg_n_0_[64] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
wire \state_reg[0]_rep ;
wire [1:0]\state_reg[1] ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire \wrap_boundary_axaddr_r[3]_i_2_n_0 ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6] ;
wire \wrap_cnt_r[3]_i_3_n_0 ;
wire \wrap_cnt_r_reg[3] ;
wire [0:0]wrap_second_len;
wire \wrap_second_len_r[0]_i_2_n_0 ;
wire \wrap_second_len_r[0]_i_3_n_0 ;
wire \wrap_second_len_r[0]_i_4_n_0 ;
wire \wrap_second_len_r[3]_i_2_n_0 ;
wire [2:0]\wrap_second_len_r_reg[3] ;
wire [2:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:3]\NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED ;
LUT2 #(
.INIT(4'h7))
\aresetn_d[1]_inv_i_1
(.I0(\aresetn_d_reg_n_0_[0] ),
.I1(aresetn),
.O(\aresetn_d_reg[1]_inv ));
FDRE #(
.INIT(1'b0))
\aresetn_d_reg[0]
(.C(aclk),
.CE(1'b1),
.D(aresetn),
.Q(\aresetn_d_reg_n_0_[0] ),
.R(1'b0));
LUT5 #(
.INIT(32'hFFE100E1))
\axaddr_incr[0]_i_10
(.I0(Q[36]),
.I1(Q[35]),
.I2(axaddr_incr_reg[0]),
.I3(sel_first),
.I4(C[0]),
.O(\axaddr_incr[0]_i_10_n_0 ));
LUT3 #(
.INIT(8'h2A))
\axaddr_incr[0]_i_12
(.I0(Q[2]),
.I1(Q[35]),
.I2(Q[36]),
.O(\axaddr_incr[0]_i_12_n_0 ));
LUT2 #(
.INIT(4'h2))
\axaddr_incr[0]_i_13
(.I0(Q[1]),
.I1(Q[36]),
.O(\axaddr_incr[0]_i_13_n_0 ));
LUT3 #(
.INIT(8'h02))
\axaddr_incr[0]_i_14
(.I0(Q[0]),
.I1(Q[35]),
.I2(Q[36]),
.O(\axaddr_incr[0]_i_14_n_0 ));
LUT3 #(
.INIT(8'h08))
\axaddr_incr[0]_i_3
(.I0(Q[35]),
.I1(Q[36]),
.I2(sel_first),
.O(\axaddr_incr[0]_i_3_n_0 ));
LUT3 #(
.INIT(8'h04))
\axaddr_incr[0]_i_4
(.I0(Q[35]),
.I1(Q[36]),
.I2(sel_first),
.O(\axaddr_incr[0]_i_4_n_0 ));
LUT3 #(
.INIT(8'h04))
\axaddr_incr[0]_i_5
(.I0(Q[36]),
.I1(Q[35]),
.I2(sel_first),
.O(\axaddr_incr[0]_i_5_n_0 ));
LUT3 #(
.INIT(8'h01))
\axaddr_incr[0]_i_6
(.I0(Q[35]),
.I1(Q[36]),
.I2(sel_first),
.O(\axaddr_incr[0]_i_6_n_0 ));
LUT5 #(
.INIT(32'hFF780078))
\axaddr_incr[0]_i_7
(.I0(Q[36]),
.I1(Q[35]),
.I2(axaddr_incr_reg[3]),
.I3(sel_first),
.I4(C[3]),
.O(\axaddr_incr[0]_i_7_n_0 ));
LUT5 #(
.INIT(32'hFFD200D2))
\axaddr_incr[0]_i_8
(.I0(Q[36]),
.I1(Q[35]),
.I2(axaddr_incr_reg[2]),
.I3(sel_first),
.I4(C[2]),
.O(\axaddr_incr[0]_i_8_n_0 ));
LUT5 #(
.INIT(32'hFFD200D2))
\axaddr_incr[0]_i_9
(.I0(Q[35]),
.I1(Q[36]),
.I2(axaddr_incr_reg[1]),
.I3(sel_first),
.I4(C[1]),
.O(\axaddr_incr[0]_i_9_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_10
(.I0(Q[4]),
.O(\axaddr_incr[4]_i_10_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_7
(.I0(Q[7]),
.O(\axaddr_incr[4]_i_7_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_8
(.I0(Q[6]),
.O(\axaddr_incr[4]_i_8_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_9
(.I0(Q[5]),
.O(\axaddr_incr[4]_i_9_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_10
(.I0(Q[8]),
.O(\axaddr_incr[8]_i_10_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_7
(.I0(Q[11]),
.O(\axaddr_incr[8]_i_7_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_8
(.I0(Q[10]),
.O(\axaddr_incr[8]_i_8_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_9
(.I0(Q[9]),
.O(\axaddr_incr[8]_i_9_n_0 ));
CARRY4 \axaddr_incr_reg[0]_i_11
(.CI(1'b0),
.CO({\axaddr_incr_reg[0]_i_11_n_0 ,\axaddr_incr_reg[0]_i_11_n_1 ,\axaddr_incr_reg[0]_i_11_n_2 ,\axaddr_incr_reg[0]_i_11_n_3 }),
.CYINIT(1'b0),
.DI({Q[3],\axaddr_incr[0]_i_12_n_0 ,\axaddr_incr[0]_i_13_n_0 ,\axaddr_incr[0]_i_14_n_0 }),
.O(C),
.S(S));
CARRY4 \axaddr_incr_reg[0]_i_2
(.CI(1'b0),
.CO({CO,\axaddr_incr_reg[0]_i_2_n_1 ,\axaddr_incr_reg[0]_i_2_n_2 ,\axaddr_incr_reg[0]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({\axaddr_incr[0]_i_3_n_0 ,\axaddr_incr[0]_i_4_n_0 ,\axaddr_incr[0]_i_5_n_0 ,\axaddr_incr[0]_i_6_n_0 }),
.O(O),
.S({\axaddr_incr[0]_i_7_n_0 ,\axaddr_incr[0]_i_8_n_0 ,\axaddr_incr[0]_i_9_n_0 ,\axaddr_incr[0]_i_10_n_0 }));
CARRY4 \axaddr_incr_reg[4]_i_6
(.CI(\axaddr_incr_reg[0]_i_11_n_0 ),
.CO({\axaddr_incr_reg[4]_i_6_n_0 ,\axaddr_incr_reg[4]_i_6_n_1 ,\axaddr_incr_reg[4]_i_6_n_2 ,\axaddr_incr_reg[4]_i_6_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\axaddr_incr_reg[11] [3:0]),
.S({\axaddr_incr[4]_i_7_n_0 ,\axaddr_incr[4]_i_8_n_0 ,\axaddr_incr[4]_i_9_n_0 ,\axaddr_incr[4]_i_10_n_0 }));
CARRY4 \axaddr_incr_reg[8]_i_6
(.CI(\axaddr_incr_reg[4]_i_6_n_0 ),
.CO({\NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED [3],\axaddr_incr_reg[8]_i_6_n_1 ,\axaddr_incr_reg[8]_i_6_n_2 ,\axaddr_incr_reg[8]_i_6_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\axaddr_incr_reg[11] [7:4]),
.S({\axaddr_incr[8]_i_7_n_0 ,\axaddr_incr[8]_i_8_n_0 ,\axaddr_incr[8]_i_9_n_0 ,\axaddr_incr[8]_i_10_n_0 }));
LUT6 #(
.INIT(64'hF0F0F0F0F088F0F0))
\axaddr_offset_r[0]_i_1
(.I0(\axaddr_offset_r[0]_i_2_n_0 ),
.I1(Q[39]),
.I2(\axaddr_offset_r_reg[3]_1 [0]),
.I3(\state_reg[1] [1]),
.I4(m_valid_i_reg_0),
.I5(\state_reg[1] [0]),
.O(\axaddr_offset_r_reg[0] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[0]_i_2
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[35]),
.I3(Q[2]),
.I4(Q[36]),
.I5(Q[0]),
.O(\axaddr_offset_r[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAC00FFFFAC000000))
\axaddr_offset_r[1]_i_1
(.I0(\axaddr_offset_r[2]_i_3_n_0 ),
.I1(\axaddr_offset_r[1]_i_2_n_0 ),
.I2(Q[35]),
.I3(Q[40]),
.I4(\state_reg[1]_rep_0 ),
.I5(\axaddr_offset_r_reg[3]_1 [1]),
.O(\axaddr_offset_r_reg[1] ));
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[1]_i_2
(.I0(Q[3]),
.I1(Q[36]),
.I2(Q[1]),
.O(\axaddr_offset_r[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAC00FFFFAC000000))
\axaddr_offset_r[2]_i_1
(.I0(\axaddr_offset_r[2]_i_2_n_0 ),
.I1(\axaddr_offset_r[2]_i_3_n_0 ),
.I2(Q[35]),
.I3(Q[41]),
.I4(\state_reg[1]_rep_0 ),
.I5(\axaddr_offset_r_reg[3]_1 [2]),
.O(\axaddr_offset_r_reg[2] ));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[2]_i_2
(.I0(Q[5]),
.I1(Q[36]),
.I2(Q[3]),
.O(\axaddr_offset_r[2]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[2]_i_3
(.I0(Q[4]),
.I1(Q[36]),
.I2(Q[2]),
.O(\axaddr_offset_r[2]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[3]_i_2
(.I0(Q[6]),
.I1(Q[4]),
.I2(Q[35]),
.I3(Q[5]),
.I4(Q[36]),
.I5(Q[3]),
.O(\axaddr_offset_r_reg[3] ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT4 #(
.INIT(16'hFFDF))
\axlen_cnt[3]_i_2
(.I0(Q[42]),
.I1(\state_reg[0]_rep ),
.I2(m_valid_i_reg_0),
.I3(\state_reg[1]_rep ),
.O(\axlen_cnt_reg[3] ));
LUT2 #(
.INIT(4'h2))
\m_axi_awaddr[11]_INST_0_i_1
(.I0(Q[37]),
.I1(sel_first),
.O(\m_axi_awaddr[10] ));
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1
(.I0(s_axi_awaddr[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(skid_buffer[0]));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1
(.I0(s_axi_awaddr[10]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(skid_buffer[10]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1
(.I0(s_axi_awaddr[11]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(skid_buffer[11]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1
(.I0(s_axi_awaddr[12]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(skid_buffer[12]));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1__0
(.I0(s_axi_awaddr[13]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(skid_buffer[13]));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1
(.I0(s_axi_awaddr[14]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(skid_buffer[14]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1
(.I0(s_axi_awaddr[15]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(skid_buffer[15]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1
(.I0(s_axi_awaddr[16]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(skid_buffer[16]));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1
(.I0(s_axi_awaddr[17]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(skid_buffer[17]));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1
(.I0(s_axi_awaddr[18]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(skid_buffer[18]));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1
(.I0(s_axi_awaddr[19]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(skid_buffer[19]));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1
(.I0(s_axi_awaddr[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(skid_buffer[1]));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1
(.I0(s_axi_awaddr[20]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(skid_buffer[20]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1
(.I0(s_axi_awaddr[21]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(skid_buffer[21]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1
(.I0(s_axi_awaddr[22]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(skid_buffer[22]));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1
(.I0(s_axi_awaddr[23]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(skid_buffer[23]));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1
(.I0(s_axi_awaddr[24]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(skid_buffer[24]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1
(.I0(s_axi_awaddr[25]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(skid_buffer[25]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1
(.I0(s_axi_awaddr[26]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(skid_buffer[26]));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1
(.I0(s_axi_awaddr[27]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(skid_buffer[27]));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1
(.I0(s_axi_awaddr[28]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(skid_buffer[28]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1
(.I0(s_axi_awaddr[29]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(skid_buffer[29]));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1
(.I0(s_axi_awaddr[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(skid_buffer[2]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1
(.I0(s_axi_awaddr[30]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(skid_buffer[30]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_2
(.I0(s_axi_awaddr[31]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(skid_buffer[31]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1
(.I0(s_axi_awprot[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(skid_buffer[32]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1
(.I0(s_axi_awprot[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(skid_buffer[33]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1
(.I0(s_axi_awprot[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(skid_buffer[34]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1
(.I0(s_axi_awsize[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(skid_buffer[35]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1
(.I0(s_axi_awsize[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(skid_buffer[36]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1
(.I0(s_axi_awburst[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(skid_buffer[38]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1
(.I0(s_axi_awburst[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(skid_buffer[39]));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1
(.I0(s_axi_awaddr[3]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(skid_buffer[3]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1
(.I0(s_axi_awlen[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(skid_buffer[44]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1
(.I0(s_axi_awlen[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(skid_buffer[45]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_1__0
(.I0(s_axi_awlen[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(skid_buffer[46]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[47]_i_1
(.I0(s_axi_awlen[3]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[47] ),
.O(skid_buffer[47]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[48]_i_1
(.I0(s_axi_awlen[4]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[48] ),
.O(skid_buffer[48]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[49]_i_1
(.I0(s_axi_awlen[5]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[49] ),
.O(skid_buffer[49]));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1
(.I0(s_axi_awaddr[4]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(skid_buffer[4]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[50]_i_1
(.I0(s_axi_awlen[6]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[50] ),
.O(skid_buffer[50]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[51]_i_1
(.I0(s_axi_awlen[7]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[51] ),
.O(skid_buffer[51]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[53]_i_1
(.I0(s_axi_awid[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[53] ),
.O(skid_buffer[53]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[54]_i_1
(.I0(s_axi_awid[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[54] ),
.O(skid_buffer[54]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[55]_i_1
(.I0(s_axi_awid[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[55] ),
.O(skid_buffer[55]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[56]_i_1
(.I0(s_axi_awid[3]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[56] ),
.O(skid_buffer[56]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[57]_i_1
(.I0(s_axi_awid[4]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[57] ),
.O(skid_buffer[57]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[58]_i_1
(.I0(s_axi_awid[5]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[58] ),
.O(skid_buffer[58]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[59]_i_1
(.I0(s_axi_awid[6]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[59] ),
.O(skid_buffer[59]));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1
(.I0(s_axi_awaddr[5]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(skid_buffer[5]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[60]_i_1
(.I0(s_axi_awid[7]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[60] ),
.O(skid_buffer[60]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[61]_i_1
(.I0(s_axi_awid[8]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[61] ),
.O(skid_buffer[61]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[62]_i_1
(.I0(s_axi_awid[9]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[62] ),
.O(skid_buffer[62]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[63]_i_1
(.I0(s_axi_awid[10]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[63] ),
.O(skid_buffer[63]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[64]_i_1
(.I0(s_axi_awid[11]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[64] ),
.O(skid_buffer[64]));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1
(.I0(s_axi_awaddr[6]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(skid_buffer[6]));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1
(.I0(s_axi_awaddr[7]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(skid_buffer[7]));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1
(.I0(s_axi_awaddr[8]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(skid_buffer[8]));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1
(.I0(s_axi_awaddr[9]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(skid_buffer[9]));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(E),
.D(skid_buffer[0]),
.Q(Q[0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(E),
.D(skid_buffer[10]),
.Q(Q[10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(E),
.D(skid_buffer[11]),
.Q(Q[11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(E),
.D(skid_buffer[12]),
.Q(Q[12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(E),
.D(skid_buffer[13]),
.Q(Q[13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(E),
.D(skid_buffer[14]),
.Q(Q[14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(E),
.D(skid_buffer[15]),
.Q(Q[15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(E),
.D(skid_buffer[16]),
.Q(Q[16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(E),
.D(skid_buffer[17]),
.Q(Q[17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(E),
.D(skid_buffer[18]),
.Q(Q[18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(E),
.D(skid_buffer[19]),
.Q(Q[19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(E),
.D(skid_buffer[1]),
.Q(Q[1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(E),
.D(skid_buffer[20]),
.Q(Q[20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(E),
.D(skid_buffer[21]),
.Q(Q[21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(E),
.D(skid_buffer[22]),
.Q(Q[22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(E),
.D(skid_buffer[23]),
.Q(Q[23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(E),
.D(skid_buffer[24]),
.Q(Q[24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(E),
.D(skid_buffer[25]),
.Q(Q[25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(E),
.D(skid_buffer[26]),
.Q(Q[26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(E),
.D(skid_buffer[27]),
.Q(Q[27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(E),
.D(skid_buffer[28]),
.Q(Q[28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(E),
.D(skid_buffer[29]),
.Q(Q[29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(E),
.D(skid_buffer[2]),
.Q(Q[2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(E),
.D(skid_buffer[30]),
.Q(Q[30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(E),
.D(skid_buffer[31]),
.Q(Q[31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(E),
.D(skid_buffer[32]),
.Q(Q[32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(E),
.D(skid_buffer[33]),
.Q(Q[33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(E),
.D(skid_buffer[34]),
.Q(Q[34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(E),
.D(skid_buffer[35]),
.Q(Q[35]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(E),
.D(skid_buffer[36]),
.Q(Q[36]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(E),
.D(skid_buffer[38]),
.Q(Q[37]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(E),
.D(skid_buffer[39]),
.Q(Q[38]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(E),
.D(skid_buffer[3]),
.Q(Q[3]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(E),
.D(skid_buffer[44]),
.Q(Q[39]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(E),
.D(skid_buffer[45]),
.Q(Q[40]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(E),
.D(skid_buffer[46]),
.Q(Q[41]),
.R(1'b0));
FDRE \m_payload_i_reg[47]
(.C(aclk),
.CE(E),
.D(skid_buffer[47]),
.Q(Q[42]),
.R(1'b0));
FDRE \m_payload_i_reg[48]
(.C(aclk),
.CE(E),
.D(skid_buffer[48]),
.Q(Q[43]),
.R(1'b0));
FDRE \m_payload_i_reg[49]
(.C(aclk),
.CE(E),
.D(skid_buffer[49]),
.Q(Q[44]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(E),
.D(skid_buffer[4]),
.Q(Q[4]),
.R(1'b0));
FDRE \m_payload_i_reg[50]
(.C(aclk),
.CE(E),
.D(skid_buffer[50]),
.Q(Q[45]),
.R(1'b0));
FDRE \m_payload_i_reg[51]
(.C(aclk),
.CE(E),
.D(skid_buffer[51]),
.Q(Q[46]),
.R(1'b0));
FDRE \m_payload_i_reg[53]
(.C(aclk),
.CE(E),
.D(skid_buffer[53]),
.Q(Q[47]),
.R(1'b0));
FDRE \m_payload_i_reg[54]
(.C(aclk),
.CE(E),
.D(skid_buffer[54]),
.Q(Q[48]),
.R(1'b0));
FDRE \m_payload_i_reg[55]
(.C(aclk),
.CE(E),
.D(skid_buffer[55]),
.Q(Q[49]),
.R(1'b0));
FDRE \m_payload_i_reg[56]
(.C(aclk),
.CE(E),
.D(skid_buffer[56]),
.Q(Q[50]),
.R(1'b0));
FDRE \m_payload_i_reg[57]
(.C(aclk),
.CE(E),
.D(skid_buffer[57]),
.Q(Q[51]),
.R(1'b0));
FDRE \m_payload_i_reg[58]
(.C(aclk),
.CE(E),
.D(skid_buffer[58]),
.Q(Q[52]),
.R(1'b0));
FDRE \m_payload_i_reg[59]
(.C(aclk),
.CE(E),
.D(skid_buffer[59]),
.Q(Q[53]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(E),
.D(skid_buffer[5]),
.Q(Q[5]),
.R(1'b0));
FDRE \m_payload_i_reg[60]
(.C(aclk),
.CE(E),
.D(skid_buffer[60]),
.Q(Q[54]),
.R(1'b0));
FDRE \m_payload_i_reg[61]
(.C(aclk),
.CE(E),
.D(skid_buffer[61]),
.Q(Q[55]),
.R(1'b0));
FDRE \m_payload_i_reg[62]
(.C(aclk),
.CE(E),
.D(skid_buffer[62]),
.Q(Q[56]),
.R(1'b0));
FDRE \m_payload_i_reg[63]
(.C(aclk),
.CE(E),
.D(skid_buffer[63]),
.Q(Q[57]),
.R(1'b0));
FDRE \m_payload_i_reg[64]
(.C(aclk),
.CE(E),
.D(skid_buffer[64]),
.Q(Q[58]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(E),
.D(skid_buffer[6]),
.Q(Q[6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(E),
.D(skid_buffer[7]),
.Q(Q[7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(E),
.D(skid_buffer[8]),
.Q(Q[8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(E),
.D(skid_buffer[9]),
.Q(Q[9]),
.R(1'b0));
LUT4 #(
.INIT(16'hF4FF))
m_valid_i_i_1__2
(.I0(b_push),
.I1(m_valid_i_reg_0),
.I2(s_axi_awvalid),
.I3(s_axi_awready),
.O(m_valid_i0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(m_valid_i_reg_0),
.R(\aresetn_d_reg[1]_inv_0 ));
LUT5 #(
.INIT(32'hFFFFFFFE))
next_pending_r_i_2
(.I0(next_pending_r_reg_0),
.I1(Q[43]),
.I2(Q[44]),
.I3(Q[46]),
.I4(Q[45]),
.O(next_pending_r_reg));
LUT4 #(
.INIT(16'hFFFE))
next_pending_r_i_2__0
(.I0(Q[41]),
.I1(Q[39]),
.I2(Q[40]),
.I3(Q[42]),
.O(next_pending_r_reg_0));
LUT1 #(
.INIT(2'h1))
s_ready_i_i_1__1
(.I0(\aresetn_d_reg_n_0_[0] ),
.O(s_ready_i_reg_0));
LUT4 #(
.INIT(16'hBFBB))
s_ready_i_i_2
(.I0(b_push),
.I1(m_valid_i_reg_0),
.I2(s_axi_awvalid),
.I3(s_axi_awready),
.O(s_ready_i0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(s_axi_awready),
.R(s_ready_i_reg_0));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awprot[0]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awprot[1]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awprot[2]),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awsize[0]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awsize[1]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awburst[0]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awburst[1]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[0]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[1]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[2]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[47]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[3]),
.Q(\skid_buffer_reg_n_0_[47] ),
.R(1'b0));
FDRE \skid_buffer_reg[48]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[4]),
.Q(\skid_buffer_reg_n_0_[48] ),
.R(1'b0));
FDRE \skid_buffer_reg[49]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[5]),
.Q(\skid_buffer_reg_n_0_[49] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[50]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[6]),
.Q(\skid_buffer_reg_n_0_[50] ),
.R(1'b0));
FDRE \skid_buffer_reg[51]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[7]),
.Q(\skid_buffer_reg_n_0_[51] ),
.R(1'b0));
FDRE \skid_buffer_reg[53]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[0]),
.Q(\skid_buffer_reg_n_0_[53] ),
.R(1'b0));
FDRE \skid_buffer_reg[54]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[1]),
.Q(\skid_buffer_reg_n_0_[54] ),
.R(1'b0));
FDRE \skid_buffer_reg[55]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[2]),
.Q(\skid_buffer_reg_n_0_[55] ),
.R(1'b0));
FDRE \skid_buffer_reg[56]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[3]),
.Q(\skid_buffer_reg_n_0_[56] ),
.R(1'b0));
FDRE \skid_buffer_reg[57]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[4]),
.Q(\skid_buffer_reg_n_0_[57] ),
.R(1'b0));
FDRE \skid_buffer_reg[58]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[5]),
.Q(\skid_buffer_reg_n_0_[58] ),
.R(1'b0));
FDRE \skid_buffer_reg[59]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[6]),
.Q(\skid_buffer_reg_n_0_[59] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[60]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[7]),
.Q(\skid_buffer_reg_n_0_[60] ),
.R(1'b0));
FDRE \skid_buffer_reg[61]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[8]),
.Q(\skid_buffer_reg_n_0_[61] ),
.R(1'b0));
FDRE \skid_buffer_reg[62]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[9]),
.Q(\skid_buffer_reg_n_0_[62] ),
.R(1'b0));
FDRE \skid_buffer_reg[63]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[10]),
.Q(\skid_buffer_reg_n_0_[63] ),
.R(1'b0));
FDRE \skid_buffer_reg[64]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[11]),
.Q(\skid_buffer_reg_n_0_[64] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'hAA8A))
\wrap_boundary_axaddr_r[0]_i_1
(.I0(Q[0]),
.I1(Q[36]),
.I2(Q[39]),
.I3(Q[35]),
.O(\wrap_boundary_axaddr_r_reg[6] [0]));
LUT5 #(
.INIT(32'h8A888AAA))
\wrap_boundary_axaddr_r[1]_i_1
(.I0(Q[1]),
.I1(Q[36]),
.I2(Q[39]),
.I3(Q[35]),
.I4(Q[40]),
.O(\wrap_boundary_axaddr_r_reg[6] [1]));
LUT6 #(
.INIT(64'hA0A0202AAAAA202A))
\wrap_boundary_axaddr_r[2]_i_1
(.I0(Q[2]),
.I1(Q[40]),
.I2(Q[35]),
.I3(Q[41]),
.I4(Q[36]),
.I5(Q[39]),
.O(\wrap_boundary_axaddr_r_reg[6] [2]));
LUT6 #(
.INIT(64'h020202A2A2A202A2))
\wrap_boundary_axaddr_r[3]_i_1
(.I0(Q[3]),
.I1(\wrap_boundary_axaddr_r[3]_i_2_n_0 ),
.I2(Q[36]),
.I3(Q[40]),
.I4(Q[35]),
.I5(Q[39]),
.O(\wrap_boundary_axaddr_r_reg[6] [3]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hB8))
\wrap_boundary_axaddr_r[3]_i_2
(.I0(Q[41]),
.I1(Q[35]),
.I2(Q[42]),
.O(\wrap_boundary_axaddr_r[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h002A882A222AAA2A))
\wrap_boundary_axaddr_r[4]_i_1
(.I0(Q[4]),
.I1(Q[35]),
.I2(Q[42]),
.I3(Q[36]),
.I4(Q[40]),
.I5(Q[41]),
.O(\wrap_boundary_axaddr_r_reg[6] [4]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT5 #(
.INIT(32'h2A222AAA))
\wrap_boundary_axaddr_r[5]_i_1
(.I0(Q[5]),
.I1(Q[36]),
.I2(Q[41]),
.I3(Q[35]),
.I4(Q[42]),
.O(\wrap_boundary_axaddr_r_reg[6] [5]));
LUT4 #(
.INIT(16'h2AAA))
\wrap_boundary_axaddr_r[6]_i_1
(.I0(Q[6]),
.I1(Q[36]),
.I2(Q[42]),
.I3(Q[35]),
.O(\wrap_boundary_axaddr_r_reg[6] [6]));
LUT6 #(
.INIT(64'hBBBBBABBCCCCC0CC))
\wrap_cnt_r[0]_i_1
(.I0(\wrap_second_len_r[0]_i_2_n_0 ),
.I1(\wrap_second_len_r_reg[3]_0 [0]),
.I2(\state_reg[1] [0]),
.I3(m_valid_i_reg_0),
.I4(\state_reg[1] [1]),
.I5(\wrap_second_len_r[0]_i_3_n_0 ),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'h9A))
\wrap_cnt_r[2]_i_1
(.I0(\wrap_second_len_r_reg[3] [1]),
.I1(\wrap_cnt_r_reg[3] ),
.I2(wrap_second_len),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT4 #(
.INIT(16'hA6AA))
\wrap_cnt_r[3]_i_1
(.I0(\wrap_second_len_r_reg[3] [2]),
.I1(wrap_second_len),
.I2(\wrap_cnt_r_reg[3] ),
.I3(\wrap_second_len_r_reg[3] [1]),
.O(D[2]));
LUT5 #(
.INIT(32'hAAAAAAAB))
\wrap_cnt_r[3]_i_2
(.I0(\wrap_cnt_r[3]_i_3_n_0 ),
.I1(\axaddr_offset_r_reg[1] ),
.I2(\axaddr_offset_r_reg[0] ),
.I3(\axaddr_offset_r_reg[3]_0 ),
.I4(\axaddr_offset_r_reg[2] ),
.O(\wrap_cnt_r_reg[3] ));
LUT6 #(
.INIT(64'h0F0F0F0F0F880F0F))
\wrap_cnt_r[3]_i_3
(.I0(\axaddr_offset_r[0]_i_2_n_0 ),
.I1(Q[39]),
.I2(\wrap_second_len_r_reg[3]_0 [0]),
.I3(\state_reg[1] [1]),
.I4(m_valid_i_reg_0),
.I5(\state_reg[1] [0]),
.O(\wrap_cnt_r[3]_i_3_n_0 ));
LUT6 #(
.INIT(64'h4444454444444044))
\wrap_second_len_r[0]_i_1
(.I0(\wrap_second_len_r[0]_i_2_n_0 ),
.I1(\wrap_second_len_r_reg[3]_0 [0]),
.I2(\state_reg[1] [0]),
.I3(m_valid_i_reg_0),
.I4(\state_reg[1] [1]),
.I5(\wrap_second_len_r[0]_i_3_n_0 ),
.O(\wrap_second_len_r_reg[3] [0]));
LUT6 #(
.INIT(64'hAAAAA8080000A808))
\wrap_second_len_r[0]_i_2
(.I0(\wrap_second_len_r[0]_i_4_n_0 ),
.I1(Q[0]),
.I2(Q[36]),
.I3(Q[2]),
.I4(Q[35]),
.I5(\axaddr_offset_r[1]_i_2_n_0 ),
.O(\wrap_second_len_r[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFBA))
\wrap_second_len_r[0]_i_3
(.I0(\axaddr_offset_r_reg[2] ),
.I1(\state_reg[1]_rep_0 ),
.I2(\axaddr_offset_r_reg[3]_1 [3]),
.I3(\wrap_second_len_r[3]_i_2_n_0 ),
.I4(\axaddr_offset_r_reg[0] ),
.I5(\axaddr_offset_r_reg[1] ),
.O(\wrap_second_len_r[0]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT4 #(
.INIT(16'h0020))
\wrap_second_len_r[0]_i_4
(.I0(Q[39]),
.I1(\state_reg[0]_rep ),
.I2(m_valid_i_reg_0),
.I3(\state_reg[1]_rep ),
.O(\wrap_second_len_r[0]_i_4_n_0 ));
LUT6 #(
.INIT(64'hEE10FFFFEE100000))
\wrap_second_len_r[2]_i_1
(.I0(\axaddr_offset_r_reg[1] ),
.I1(\axaddr_offset_r_reg[0] ),
.I2(\axaddr_offset_r_reg[3]_0 ),
.I3(\axaddr_offset_r_reg[2] ),
.I4(\state_reg[1]_rep_0 ),
.I5(\wrap_second_len_r_reg[3]_0 [1]),
.O(\wrap_second_len_r_reg[3] [1]));
LUT6 #(
.INIT(64'hFFFFFFF444444444))
\wrap_second_len_r[3]_i_1
(.I0(\state_reg[1]_rep_0 ),
.I1(\wrap_second_len_r_reg[3]_0 [2]),
.I2(\axaddr_offset_r_reg[0] ),
.I3(\axaddr_offset_r_reg[1] ),
.I4(\axaddr_offset_r_reg[2] ),
.I5(\wrap_second_len_r[3]_i_2_n_0 ),
.O(\wrap_second_len_r_reg[3] [2]));
LUT6 #(
.INIT(64'h00000000EEE222E2))
\wrap_second_len_r[3]_i_2
(.I0(\axaddr_offset_r[2]_i_2_n_0 ),
.I1(Q[35]),
.I2(Q[4]),
.I3(Q[36]),
.I4(Q[6]),
.I5(\axlen_cnt_reg[3] ),
.O(\wrap_second_len_r[3]_i_2_n_0 ));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axic_register_slice" *)
module zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1
(s_axi_bvalid,
\skid_buffer_reg[0]_0 ,
\s_axi_bid[11] ,
\aresetn_d_reg[1]_inv ,
aclk,
\aresetn_d_reg[0] ,
si_rs_bvalid,
s_axi_bready,
out,
\s_bresp_acc_reg[1] );
output s_axi_bvalid;
output \skid_buffer_reg[0]_0 ;
output [13:0]\s_axi_bid[11] ;
input \aresetn_d_reg[1]_inv ;
input aclk;
input \aresetn_d_reg[0] ;
input si_rs_bvalid;
input s_axi_bready;
input [11:0]out;
input [1:0]\s_bresp_acc_reg[1] ;
wire aclk;
wire \aresetn_d_reg[0] ;
wire \aresetn_d_reg[1]_inv ;
wire \m_payload_i[0]_i_1__1_n_0 ;
wire \m_payload_i[10]_i_1__1_n_0 ;
wire \m_payload_i[11]_i_1__1_n_0 ;
wire \m_payload_i[12]_i_1__1_n_0 ;
wire \m_payload_i[13]_i_2_n_0 ;
wire \m_payload_i[1]_i_1__1_n_0 ;
wire \m_payload_i[2]_i_1__1_n_0 ;
wire \m_payload_i[3]_i_1__1_n_0 ;
wire \m_payload_i[4]_i_1__1_n_0 ;
wire \m_payload_i[5]_i_1__1_n_0 ;
wire \m_payload_i[6]_i_1__1_n_0 ;
wire \m_payload_i[7]_i_1__1_n_0 ;
wire \m_payload_i[8]_i_1__1_n_0 ;
wire \m_payload_i[9]_i_1__1_n_0 ;
wire m_valid_i0;
wire [11:0]out;
wire p_1_in;
wire [13:0]\s_axi_bid[11] ;
wire s_axi_bready;
wire s_axi_bvalid;
wire [1:0]\s_bresp_acc_reg[1] ;
wire s_ready_i0;
wire si_rs_bvalid;
wire \skid_buffer_reg[0]_0 ;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1__1
(.I0(\s_bresp_acc_reg[1] [0]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(\m_payload_i[0]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1__1
(.I0(out[8]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(\m_payload_i[10]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1__1
(.I0(out[9]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(\m_payload_i[11]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1__1
(.I0(out[10]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(\m_payload_i[12]_i_1__1_n_0 ));
LUT2 #(
.INIT(4'hB))
\m_payload_i[13]_i_1
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.O(p_1_in));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_2
(.I0(out[11]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(\m_payload_i[13]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1__1
(.I0(\s_bresp_acc_reg[1] [1]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(\m_payload_i[1]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1__1
(.I0(out[0]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(\m_payload_i[2]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1__1
(.I0(out[1]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(\m_payload_i[3]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1__1
(.I0(out[2]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(\m_payload_i[4]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1__1
(.I0(out[3]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(\m_payload_i[5]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1__1
(.I0(out[4]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(\m_payload_i[6]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1__1
(.I0(out[5]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(\m_payload_i[7]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1__1
(.I0(out[6]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(\m_payload_i[8]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1__1
(.I0(out[7]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(\m_payload_i[9]_i_1__1_n_0 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[0]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[10]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[11]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[12]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[13]_i_2_n_0 ),
.Q(\s_axi_bid[11] [13]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[1]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[2]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[3]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[4]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[5]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[6]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[7]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[8]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[9]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [9]),
.R(1'b0));
LUT4 #(
.INIT(16'hF4FF))
m_valid_i_i_1
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.I2(si_rs_bvalid),
.I3(\skid_buffer_reg[0]_0 ),
.O(m_valid_i0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(s_axi_bvalid),
.R(\aresetn_d_reg[1]_inv ));
LUT4 #(
.INIT(16'hF4FF))
s_ready_i_i_1
(.I0(si_rs_bvalid),
.I1(\skid_buffer_reg[0]_0 ),
.I2(s_axi_bready),
.I3(s_axi_bvalid),
.O(s_ready_i0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(\skid_buffer_reg[0]_0 ),
.R(\aresetn_d_reg[0] ));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\s_bresp_acc_reg[1] [0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[8]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[9]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[10]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[11]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\s_bresp_acc_reg[1] [1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[0]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[1]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[2]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[3]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[4]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[5]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[6]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[7]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axic_register_slice" *)
module zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2
(s_axi_rvalid,
\skid_buffer_reg[0]_0 ,
\cnt_read_reg[3]_rep__0 ,
\s_axi_rid[11] ,
\aresetn_d_reg[1]_inv ,
aclk,
\aresetn_d_reg[0] ,
\cnt_read_reg[4]_rep__0 ,
s_axi_rready,
r_push_r_reg,
\cnt_read_reg[4] );
output s_axi_rvalid;
output \skid_buffer_reg[0]_0 ;
output \cnt_read_reg[3]_rep__0 ;
output [46:0]\s_axi_rid[11] ;
input \aresetn_d_reg[1]_inv ;
input aclk;
input \aresetn_d_reg[0] ;
input \cnt_read_reg[4]_rep__0 ;
input s_axi_rready;
input [12:0]r_push_r_reg;
input [33:0]\cnt_read_reg[4] ;
wire aclk;
wire \aresetn_d_reg[0] ;
wire \aresetn_d_reg[1]_inv ;
wire \cnt_read_reg[3]_rep__0 ;
wire [33:0]\cnt_read_reg[4] ;
wire \cnt_read_reg[4]_rep__0 ;
wire \m_payload_i[0]_i_1__2_n_0 ;
wire \m_payload_i[10]_i_1__2_n_0 ;
wire \m_payload_i[11]_i_1__2_n_0 ;
wire \m_payload_i[12]_i_1__2_n_0 ;
wire \m_payload_i[13]_i_1__2_n_0 ;
wire \m_payload_i[14]_i_1__1_n_0 ;
wire \m_payload_i[15]_i_1__1_n_0 ;
wire \m_payload_i[16]_i_1__1_n_0 ;
wire \m_payload_i[17]_i_1__1_n_0 ;
wire \m_payload_i[18]_i_1__1_n_0 ;
wire \m_payload_i[19]_i_1__1_n_0 ;
wire \m_payload_i[1]_i_1__2_n_0 ;
wire \m_payload_i[20]_i_1__1_n_0 ;
wire \m_payload_i[21]_i_1__1_n_0 ;
wire \m_payload_i[22]_i_1__1_n_0 ;
wire \m_payload_i[23]_i_1__1_n_0 ;
wire \m_payload_i[24]_i_1__1_n_0 ;
wire \m_payload_i[25]_i_1__1_n_0 ;
wire \m_payload_i[26]_i_1__1_n_0 ;
wire \m_payload_i[27]_i_1__1_n_0 ;
wire \m_payload_i[28]_i_1__1_n_0 ;
wire \m_payload_i[29]_i_1__1_n_0 ;
wire \m_payload_i[2]_i_1__2_n_0 ;
wire \m_payload_i[30]_i_1__1_n_0 ;
wire \m_payload_i[31]_i_1__1_n_0 ;
wire \m_payload_i[32]_i_1__1_n_0 ;
wire \m_payload_i[33]_i_1__1_n_0 ;
wire \m_payload_i[34]_i_1__1_n_0 ;
wire \m_payload_i[35]_i_1__1_n_0 ;
wire \m_payload_i[36]_i_1__1_n_0 ;
wire \m_payload_i[37]_i_1_n_0 ;
wire \m_payload_i[38]_i_1__1_n_0 ;
wire \m_payload_i[39]_i_1__1_n_0 ;
wire \m_payload_i[3]_i_1__2_n_0 ;
wire \m_payload_i[40]_i_1_n_0 ;
wire \m_payload_i[41]_i_1_n_0 ;
wire \m_payload_i[42]_i_1_n_0 ;
wire \m_payload_i[43]_i_1_n_0 ;
wire \m_payload_i[44]_i_1__1_n_0 ;
wire \m_payload_i[45]_i_1__1_n_0 ;
wire \m_payload_i[46]_i_2_n_0 ;
wire \m_payload_i[4]_i_1__2_n_0 ;
wire \m_payload_i[5]_i_1__2_n_0 ;
wire \m_payload_i[6]_i_1__2_n_0 ;
wire \m_payload_i[7]_i_1__2_n_0 ;
wire \m_payload_i[8]_i_1__2_n_0 ;
wire \m_payload_i[9]_i_1__2_n_0 ;
wire m_valid_i_i_1__1_n_0;
wire p_1_in;
wire [12:0]r_push_r_reg;
wire [46:0]\s_axi_rid[11] ;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_ready_i_i_1__2_n_0;
wire \skid_buffer_reg[0]_0 ;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[37] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[40] ;
wire \skid_buffer_reg_n_0_[41] ;
wire \skid_buffer_reg_n_0_[42] ;
wire \skid_buffer_reg_n_0_[43] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT2 #(
.INIT(4'h2))
\cnt_read[3]_i_2
(.I0(\skid_buffer_reg[0]_0 ),
.I1(\cnt_read_reg[4]_rep__0 ),
.O(\cnt_read_reg[3]_rep__0 ));
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1__2
(.I0(\cnt_read_reg[4] [0]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(\m_payload_i[0]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair104" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1__2
(.I0(\cnt_read_reg[4] [10]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(\m_payload_i[10]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair103" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1__2
(.I0(\cnt_read_reg[4] [11]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(\m_payload_i[11]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair103" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1__2
(.I0(\cnt_read_reg[4] [12]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(\m_payload_i[12]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1__2
(.I0(\cnt_read_reg[4] [13]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(\m_payload_i[13]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1__1
(.I0(\cnt_read_reg[4] [14]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(\m_payload_i[14]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair101" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1__1
(.I0(\cnt_read_reg[4] [15]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(\m_payload_i[15]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair101" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1__1
(.I0(\cnt_read_reg[4] [16]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(\m_payload_i[16]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair100" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1__1
(.I0(\cnt_read_reg[4] [17]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(\m_payload_i[17]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair100" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1__1
(.I0(\cnt_read_reg[4] [18]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(\m_payload_i[18]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair99" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1__1
(.I0(\cnt_read_reg[4] [19]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(\m_payload_i[19]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair108" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1__2
(.I0(\cnt_read_reg[4] [1]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(\m_payload_i[1]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair99" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1__1
(.I0(\cnt_read_reg[4] [20]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(\m_payload_i[20]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair98" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1__1
(.I0(\cnt_read_reg[4] [21]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(\m_payload_i[21]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair98" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1__1
(.I0(\cnt_read_reg[4] [22]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(\m_payload_i[22]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair97" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1__1
(.I0(\cnt_read_reg[4] [23]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(\m_payload_i[23]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair97" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1__1
(.I0(\cnt_read_reg[4] [24]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(\m_payload_i[24]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1__1
(.I0(\cnt_read_reg[4] [25]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(\m_payload_i[25]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1__1
(.I0(\cnt_read_reg[4] [26]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(\m_payload_i[26]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1__1
(.I0(\cnt_read_reg[4] [27]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(\m_payload_i[27]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1__1
(.I0(\cnt_read_reg[4] [28]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(\m_payload_i[28]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1__1
(.I0(\cnt_read_reg[4] [29]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(\m_payload_i[29]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair108" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1__2
(.I0(\cnt_read_reg[4] [2]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(\m_payload_i[2]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1__1
(.I0(\cnt_read_reg[4] [30]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(\m_payload_i[30]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_1__1
(.I0(\cnt_read_reg[4] [31]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(\m_payload_i[31]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1__1
(.I0(\cnt_read_reg[4] [32]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(\m_payload_i[32]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1__1
(.I0(\cnt_read_reg[4] [33]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(\m_payload_i[33]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1__1
(.I0(r_push_r_reg[0]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(\m_payload_i[34]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1__1
(.I0(r_push_r_reg[1]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(\m_payload_i[35]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1__1
(.I0(r_push_r_reg[2]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(\m_payload_i[36]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[37]_i_1
(.I0(r_push_r_reg[3]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[37] ),
.O(\m_payload_i[37]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1__1
(.I0(r_push_r_reg[4]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(\m_payload_i[38]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1__1
(.I0(r_push_r_reg[5]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(\m_payload_i[39]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair107" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1__2
(.I0(\cnt_read_reg[4] [3]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(\m_payload_i[3]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[40]_i_1
(.I0(r_push_r_reg[6]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[40] ),
.O(\m_payload_i[40]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[41]_i_1
(.I0(r_push_r_reg[7]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[41] ),
.O(\m_payload_i[41]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[42]_i_1
(.I0(r_push_r_reg[8]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[42] ),
.O(\m_payload_i[42]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[43]_i_1
(.I0(r_push_r_reg[9]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[43] ),
.O(\m_payload_i[43]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1__1
(.I0(r_push_r_reg[10]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(\m_payload_i[44]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1__1
(.I0(r_push_r_reg[11]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(\m_payload_i[45]_i_1__1_n_0 ));
LUT2 #(
.INIT(4'hB))
\m_payload_i[46]_i_1
(.I0(s_axi_rready),
.I1(s_axi_rvalid),
.O(p_1_in));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_2
(.I0(r_push_r_reg[12]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(\m_payload_i[46]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair107" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1__2
(.I0(\cnt_read_reg[4] [4]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(\m_payload_i[4]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair106" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1__2
(.I0(\cnt_read_reg[4] [5]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(\m_payload_i[5]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair106" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1__2
(.I0(\cnt_read_reg[4] [6]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(\m_payload_i[6]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair105" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1__2
(.I0(\cnt_read_reg[4] [7]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(\m_payload_i[7]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair105" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1__2
(.I0(\cnt_read_reg[4] [8]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(\m_payload_i[8]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair104" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1__2
(.I0(\cnt_read_reg[4] [9]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(\m_payload_i[9]_i_1__2_n_0 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[0]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[10]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[11]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[12]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[13]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[14]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[15]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[16]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[17]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[18]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[19]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[1]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[20]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[21]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[22]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[23]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[24]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[25]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[26]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[27]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[28]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[29]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[2]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[30]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[31]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[32]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[33]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[34]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[35]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [35]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[36]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [36]),
.R(1'b0));
FDRE \m_payload_i_reg[37]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[37]_i_1_n_0 ),
.Q(\s_axi_rid[11] [37]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[38]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [38]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[39]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [39]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[3]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[40]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[40]_i_1_n_0 ),
.Q(\s_axi_rid[11] [40]),
.R(1'b0));
FDRE \m_payload_i_reg[41]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[41]_i_1_n_0 ),
.Q(\s_axi_rid[11] [41]),
.R(1'b0));
FDRE \m_payload_i_reg[42]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[42]_i_1_n_0 ),
.Q(\s_axi_rid[11] [42]),
.R(1'b0));
FDRE \m_payload_i_reg[43]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[43]_i_1_n_0 ),
.Q(\s_axi_rid[11] [43]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[44]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [44]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[45]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [45]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[46]_i_2_n_0 ),
.Q(\s_axi_rid[11] [46]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[4]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[5]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[6]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[7]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[8]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[9]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [9]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT4 #(
.INIT(16'h4FFF))
m_valid_i_i_1__1
(.I0(s_axi_rready),
.I1(s_axi_rvalid),
.I2(\cnt_read_reg[4]_rep__0 ),
.I3(\skid_buffer_reg[0]_0 ),
.O(m_valid_i_i_1__1_n_0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i_i_1__1_n_0),
.Q(s_axi_rvalid),
.R(\aresetn_d_reg[1]_inv ));
LUT4 #(
.INIT(16'hF8FF))
s_ready_i_i_1__2
(.I0(\cnt_read_reg[4]_rep__0 ),
.I1(\skid_buffer_reg[0]_0 ),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.O(s_ready_i_i_1__2_n_0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i_i_1__2_n_0),
.Q(\skid_buffer_reg[0]_0 ),
.R(\aresetn_d_reg[0] ));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [32]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [33]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[0]),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[1]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[2]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[37]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[3]),
.Q(\skid_buffer_reg_n_0_[37] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[4]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[5]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[40]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[6]),
.Q(\skid_buffer_reg_n_0_[40] ),
.R(1'b0));
FDRE \skid_buffer_reg[41]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[7]),
.Q(\skid_buffer_reg_n_0_[41] ),
.R(1'b0));
FDRE \skid_buffer_reg[42]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[8]),
.Q(\skid_buffer_reg_n_0_[42] ),
.R(1'b0));
FDRE \skid_buffer_reg[43]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[9]),
.Q(\skid_buffer_reg_n_0_[43] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[10]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[11]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[12]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKINV_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__CLKINV_BEHAVIORAL_PP_V
/**
* clkinv: Clock tree inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__clkinv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKINV_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INPUTISO0N_BLACKBOX_V
`define SKY130_FD_SC_HDLL__INPUTISO0N_BLACKBOX_V
/**
* inputiso0n: Input isolator with inverted enable.
*
* X = (A & SLEEP_B)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__inputiso0n (
X ,
A ,
SLEEP_B
);
output X ;
input A ;
input SLEEP_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INPUTISO0N_BLACKBOX_V
|
// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: altpll0.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module altpll0 (
inclk0,
c0,
locked);
input inclk0;
output c0;
output locked;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll0.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: GATE_LOCK_COUNTER NUMERIC "1048575"
// Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "YES"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
// Copyright (c) 2000-2012 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 29755 $
// $Date: 2012-10-22 13:58:12 +0000 (Mon, 22 Oct 2012) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
`ifdef BSV_ASYNC_RESET
`define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
`else
`define BSV_ARESET_EDGE_META
`endif
`ifdef BSV_RESET_FIFO_HEAD
`define BSV_ARESET_EDGE_HEAD `BSV_ARESET_EDGE_META
`else
`define BSV_ARESET_EDGE_HEAD
`endif
// Depth 1 FIFO
// Allows simultaneous ENQ and DEQ (at the expense of potentially
// causing combinational loops).
module FIFOL1(CLK,
RST,
D_IN,
ENQ,
FULL_N,
D_OUT,
DEQ,
EMPTY_N,
CLR);
parameter width = 1;
input CLK;
input RST;
input [width - 1 : 0] D_IN;
input ENQ;
input DEQ;
input CLR ;
output FULL_N;
output EMPTY_N;
output [width - 1 : 0] D_OUT;
reg empty_reg ;
reg [width - 1 : 0] D_OUT;
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
D_OUT <= `BSV_ASSIGNMENT_DELAY {((width + 1)/2) {2'b10}} ;
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
assign FULL_N = !empty_reg || DEQ;
assign EMPTY_N = empty_reg ;
always@(posedge CLK `BSV_ARESET_EDGE_META)
begin
if (RST == `BSV_RESET_VALUE)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end
else
begin
if (CLR)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end
else if (ENQ)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
end
else if (DEQ)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (DEQ)
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
always@(posedge CLK `BSV_ARESET_EDGE_HEAD)
begin
`ifdef BSV_RESET_FIFO_HEAD
if (RST == `BSV_RESET_VALUE)
begin
D_OUT <= `BSV_ASSIGNMENT_DELAY {width {1'b0}} ;
end
else
`endif
begin
if (ENQ)
D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN;
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
// synopsys translate_off
always@(posedge CLK)
begin: error_checks
reg deqerror, enqerror ;
deqerror = 0;
enqerror = 0;
if ( ! empty_reg && DEQ )
begin
deqerror = 1 ;
$display( "Warning: FIFOL1: %m -- Dequeuing from empty fifo" ) ;
end
if ( ! FULL_N && ENQ && ! DEQ)
begin
enqerror = 1 ;
$display( "Warning: FIFOL1: %m -- Enqueuing to a full fifo" ) ;
end
end
// synopsys translate_on
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Silicon Spectrum Corporation - All Rights Reserved
// Copyright (C) 2009 - All rights reserved
//
// This File is copyright Silicon Spectrum Corporation and is licensed for
// use by Conexant Systems, Inc., hereafter the "licensee", as defined by the NDA and the
// license agreement.
//
// This code may not be used as a basis for new development without a written
// agreement between Silicon Spectrum and the licensee.
//
// New development includes, but is not limited to new designs based on this
// code, using this code to aid verification or using this code to test code
// developed independently by the licensee.
//
// This copyright notice must be maintained as written, modifying or removing
// this copyright header will be considered a breach of the license agreement.
//
// The licensee may modify the code for the licensed project.
// Silicon Spectrum does not give up the copyright to the original
// file or encumber in any way.
//
// Use of this file is restricted by the license agreement between the
// licensee and Silicon Spectrum, Inc.
//
// Title : Pixel Cache Top Level
// File : ded_pix_cache.v
// Author : Frank Bruno
// Created : 08-Jul-2008
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// ded_pix_cache is used to handle all memory requests for the 2D/3D pipeline
// Requests from Lines and triangles as well as BLTs all pass through this
// Block.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module ded_pix_cache
#(parameter BYTES = 4)
(
input de_clk, // Drawing engine clock
input mc_clk, // memory controller clock
input de_rstn, // reset input bit_t
input [27:0] dorg_2, // Destination origin.
input [27:0] sorg_2, // Source origin.
input [27:0] zorg_2, // Z origin.
input [11:0] dptch_2, // destination pitch.
input [11:0] sptch_2, // source pitch.
input [11:0] zptch_2, // Z pitch.
input ld_wcnt,
input [3:0] fx_1, // lower nibble of the alu fx
input rmw,
// Needed by Pixel cache
input ps8_2, // pixel size equals eight
input ps16_2, // pixel size equals sixteen
input ps32_2, // pixel size equals sixteen
input [31:0] fore_2, // Foreground Color
input [31:0] back_2, // Background Color
input solid_2, // Solid indicator
input dr_trnsp_2, // Transparent indicator
input dx_pc_ld, // Load a pixel from execution
input dx_clip, // Line is being clipped
input [15:0] dx_real_dstx, // X destination
input [15:0] dx_real_dsty, // Y destination
input dx_pc_msk_last,// Don;t display last pixel
input dx_fg_bgn, // Foreground or background color
input dx_last_pixel, // We are receiving the last pix
// 3D Interface.
input valid_3d, // Valid pixel from the 3D engine.
input fg_bgn_3d, // Forground background from 3D engine.
input [15:0] x_out_3d, // X destination
input [15:0] y_out_3d, // Y destination
input pc_msk_last_3d,// Don;t display last pixel
input pc_last_3d, // Last pixel from the 3D engine.
input [31:0] pixel_3d, // 3D Pixel.
input [31:0] z_3d, // 3D Pixel.
input [7:0] alpha_3d, // 3D Alpha.
input [2:0] z_op, // Z operation
input z_en, // Z enabled
input z_ro, // Do not update Z
input active_3d_2,// #D is active.
// Needed by BLT
input de_pc_pop, // Pop from PC
input mc_popen, // increment from MC
input [15:0] srcx, // Source X address.
input [15:0] srcy, // Source Y address.
input [15:0] dstx, // Destination X address.
input [15:0] dsty, // Destination Y address.
input imem_rd, // Internal Memory read.
input dx_mem_req, // Internal Memory request.
input [3:0] mask_2,
input [1:0] stpl_2,
input [1:0] dr_apat_2,
input [1:0] dr_clp_2,
input rad_flg_2,
input [2:0] strt_wrd_2,
input [3:0] strt_byt_2,
input [2:0] strt_bit_2,
input [1:0] ps_2,
input [3:0] bsrcr_2, // Source blending function.
input [2:0] bdstr_2, // Destination blending fx
input blend_en_2, // Blending enable.
input [1:0] blend_reg_en_2,// Blending register enable.
input [7:0] bsrc_alpha_2, // Source alpha data.
input [7:0] bdst_alpha_2, // Destination alpha data.
input [3:0] rop_2, // Raster operation.
input [31:0] kcol_2, // Key Color.
input [2:0] key_ctrl_2, // Key control.
input [6:0] lft_enc_2,
input [6:0] rht_enc_2,
input [11:0] clp_min_2, // left clipping pointer
input [11:0] clp_max_2, // right clipping pointer
input [3:0] cmin_enc_2,
input [3:0] cmax_enc_2,
input y_clip_2,
input sol_2,
input eol_2,
input rst_wad_flg_2,
input [2:0] frst8_2,
output reg mc_acken,
output reg [(BYTES*8)-1:0] px_col, // pixel color select
output reg [BYTES-1:0] px_msk_color, // pixel mask
output reg [(BYTES*4)-1:0] px_a, // alpha out
output reg [31:0] de_mc_address,
output reg de_mc_read,
output reg de_mc_rmw,
output reg [3:0] de_mc_wcnt,
output reg pc_dirty, // data left in the pixel cache.
output reg pc_pending, // Pixel cache access pending
output reg pc_busy, // Pixel cache is busy
output reg pc_busy_3d, // Pixel cache is busy
output de_pc_empty,
output reg [31:0] fore_4, // foreground register output
output reg [31:0] back_4, // foreground register output.
output reg blt_actv_4,
output reg trnsp_4, solid_4,
output reg ps8_4,
output reg ps16_4,
output reg ps32_4,
output reg [1:0] stpl_4,
output reg [1:0] clp_4,
output reg line_actv_4,
output reg [1:0] apat_4,
output reg [3:0] mask_4,
output rad_flg_3,
output [2:0] strt_wrd_3,
output [3:0] strt_byt_3,
output [2:0] strt_bit_3,
output reg [2:0] strt_wrd_4,
output reg [3:0] strt_byt_4,
output reg [2:0] strt_bit_4,
output reg [1:0] ps_4,
output reg [3:0] bsrcr_4, // Source blending function.
output reg [2:0] bdstr_4, // Destination blending function.
output reg blend_en_4, // Blending enable.
output reg [1:0] blend_reg_en_4, // Blending enable.
output reg [7:0] bsrc_alpha_4, // Source alpha data.
output reg [7:0] bdst_alpha_4, // Destination alpha data.
output reg [3:0] rop_4, // Raster operation
output reg [31:0] kcol_4, // Key Color.
output reg [2:0] key_ctrl_4, // Key control.
output reg [6:0] lft_enc_4,
output reg [6:0] rht_enc_4,
output reg [11:0] clp_min_4, // left clipping pointer
output reg [11:0] clp_max_4, // right clipping pointer
output reg [3:0] cmin_enc_4,
output reg [3:0] cmax_enc_4,
output reg [13:0] x_bus_4, // bus from execution X dest counter
output reg y_clip_4,
output sol_4,
output reg eol_4,
output rst_wad_flg_3,
output mc_read_3,
output sol_3,
output reg [2:0] frst8_4,
output reg pc_empty,
output reg pc_last,
output reg [2:0] z_op_4, // Z operation
output reg z_en_4, // Z enabled
output reg z_ro_4, // Do not update Z
output reg [31:0] z_address_4, // Z Address.
output reg [(BYTES*8)-1:0] z_out // Z value to framebuffer
);
reg push_last;
reg [2:0] sol_4_int;
reg [31:0] pix_color; // Color into output fifo
reg [31:0] pix_z; // Color into output fifo
reg [7:0] pix_a; // Color into output fifo
reg push; // push into output fifo
reg [15:0] in_x, in_y; // X,Y into the output fifo
reg [1:0] depth; // encoded depth into fifo
reg [127:0] int_col;
reg [15:0] int_mask;
reg [3:0] wcnt;
reg [15:0] y_pos;
reg [13:0] x_pos;
reg [27:0] org_2;
reg [11:0] ptch_2;
reg same_page; // we are writing to the same mask
reg startup;
reg push_previous;
reg pipe_push_last;
reg fifo_rmw;
reg fifo_cmd;
reg [15:0] fifo_mask;
reg [127:0] fifo_color;
reg dx_delayed;
reg [31:0] fifo_kcol;
reg [1:0] fifo_ps;
reg [3:0] fifo_bsrcr;
reg [2:0] fifo_bdstr;
reg fifo_blend_en;
reg [1:0] fifo_blend_reg_en;
reg [7:0] fifo_bsrc_alpha;
reg [7:0] fifo_bdst_alpha;
reg [3:0] fifo_rop;
reg [2:0] fifo_key_ctrl;
reg [27:0] fifo_junk;
reg data_pending;
reg [31:0] p_mult, int_add;
reg [31:0] z_mult, int_zadd;
reg fifo_push;
reg [270:0] fifo_data; // Muxed data into fifo
reg [128:0] fifo_adata; // Muxed data into fifo
reg push_d;
reg [1:0] last_pixel_pipe;
reg [31:0] fifo_address;
reg [31:0] z_address;
reg [127:0] z_buffer, int_z;
reg [63:0] a_buffer;
reg [165:0] fifo_z;
reg hold_push_last;
reg hold_3d;
reg active_3d_del;
wire [6:0] wrusedw;
wire fifo_empty;
wire [270:0] fifo_dout; // Muxed data into fifo
wire [165:0] fifo_zout; // Muxed data into fifo
wire fifo_dout_extra;
wire [127:0] a_dout;
// Combine 2D and 3D signals (jmacleod).
wire pc_ld = dx_pc_ld | valid_3d; // Valid pixel
wire fg_bgn = (~valid_3d & dx_fg_bgn) | (valid_3d & fg_bgn_3d); // Forground background Select.
wire last_pixel = (~valid_3d & dx_last_pixel) | (valid_3d & pc_last_3d); // Last pixel
wire [15:0] real_dstx = ({16{~valid_3d}} & dx_real_dstx) | ({16{valid_3d}} & x_out_3d); // X destination
wire [15:0] real_dsty = ({16{~valid_3d}} & dx_real_dsty) | ({16{valid_3d}} & y_out_3d); // Y destination
wire pc_msk_last = (~valid_3d & dx_pc_msk_last) | (valid_3d & pc_msk_last_3d); // Last pixel mask.
wire clip = (~valid_3d) ? dx_clip : 1'b0;
// create org and pitch multiplexers
always @* begin
casex({push,imem_rd})
/* synopsys full_case parallel_case */
2'b1x:begin // Pixel Cache Color write to memory.
org_2 = dorg_2;
ptch_2 = dptch_2;
if (BYTES == 16) x_pos = {{2{in_x[15]}}, in_x[15:4]};
else if (BYTES == 8) x_pos = {in_x[15], in_x[15:3]};
else x_pos = in_x[15:2];
y_pos = in_y;
end
2'b01:begin // 2 D read from memory.
org_2 = sorg_2;
ptch_2 = sptch_2;
//if (BYTES == 16) x_pos = {{2{srcx[15]}}, srcx[15:6], 2'b0};
//else if (BYTES == 8) x_pos = {srcx[15], srcx[15:5], 2'b0};
//else x_pos = {srcx[15:4], 2'b0};
if (BYTES == 16) x_pos = {{2{srcx[15]}}, srcx[15:4]};
else if (BYTES == 8) x_pos = {srcx[15], srcx[15:4], 1'b0};
else x_pos = {srcx[15:4], 2'b0};
y_pos = srcy;
end
2'b00:begin // 2 D write to memory.
org_2 = dorg_2;
ptch_2 = dptch_2;
//if (BYTES == 16) x_pos = {{2{dstx[15]}}, dstx[15:6], 2'b0};
//else if (BYTES == 8) x_pos = {dstx[15], dstx[15:5], 2'b0};
//else x_pos = {dstx[15:4], 2'b0};
if (BYTES == 16) x_pos = {{2{dstx[15]}}, dstx[15:4]};
else if (BYTES == 8) x_pos = {dstx[15], dstx[15:4], 1'b0};
else x_pos = {dstx[15:4], 2'b0};
y_pos = dsty;
end
endcase
end
always @*
if (BYTES == 16) fifo_address = p_mult + int_add;
else if (BYTES == 8) fifo_address = {p_mult, 1'b0} + int_add;
else fifo_address = {p_mult, 2'b0} + int_add;
always @*
if (BYTES == 16) z_address = z_mult + int_zadd;
else if (BYTES == 8) z_address = {z_mult, 1'b0} + int_zadd;
else z_address = {z_mult, 2'b0} + int_zadd;
always @ (posedge de_clk) begin
if (push || dx_mem_req) begin
// Pitch conversion
p_mult <= (y_pos * {{4{ptch_2[11]}}, ptch_2});
z_mult <= (y_pos * {{4{zptch_2[11]}}, zptch_2});
`ifdef BYTE16 int_add <= (org_2 + {{14{x_pos[13]}}, x_pos}); `endif
`ifdef BYTE8 int_add <= ({org_2, 1'b0} + {{14{x_pos[13]}}, x_pos}); `endif
`ifdef BYTE4 int_add <= ({org_2, 2'b0} + {{14{x_pos[13]}}, x_pos}); `endif
`ifdef BYTE16 int_zadd <= (zorg_2 + {{14{x_pos[13]}}, x_pos}); `endif
`ifdef BYTE8 int_zadd <= ({zorg_2, 1'b0} + {{14{x_pos[13]}}, x_pos}); `endif
`ifdef BYTE4 int_zadd <= ({zorg_2, 2'b0} + {{14{x_pos[13]}}, x_pos}); `endif
fifo_rmw <= (rmw | blend_en_2);
fifo_kcol <= kcol_2;
fifo_ps <= ps_2;
fifo_bsrcr <= bsrcr_2;
fifo_bdstr <= bdstr_2;
fifo_blend_en <= blend_en_2;
fifo_blend_reg_en <= blend_reg_en_2;
fifo_bsrc_alpha <= bsrc_alpha_2;
fifo_bdst_alpha <= bdst_alpha_2;
fifo_rop <= rop_2;
fifo_key_ctrl <= key_ctrl_2;
fifo_junk[6:0] <= lft_enc_2;
fifo_junk[13:7] <= rht_enc_2;
fifo_junk[25:14] <= dstx[15:4];
fifo_junk[26] <= rst_wad_flg_2;
end
if (push) begin
fifo_color[7:0] <= ~int_mask[0] ? int_col[7:0] : fifo_color[7:0];
fifo_color[15:8] <= ~int_mask[1] ? int_col[15:8] : fifo_color[15:8];
fifo_color[23:16] <= ~int_mask[2] ? int_col[23:16] : fifo_color[23:16];
fifo_color[31:24] <= ~int_mask[3] ? int_col[31:24] : fifo_color[31:24];
fifo_color[39:32] <= ~int_mask[4] ? int_col[39:32] : fifo_color[39:32];
fifo_color[47:40] <= ~int_mask[5] ? int_col[47:40] : fifo_color[47:40];
fifo_color[55:48] <= ~int_mask[6] ? int_col[55:48] : fifo_color[55:48];
fifo_color[63:56] <= ~int_mask[7] ? int_col[63:56] : fifo_color[63:56];
fifo_color[71:64] <= ~int_mask[8] ? int_col[71:64] : fifo_color[71:64];
fifo_color[79:72] <= ~int_mask[9] ? int_col[79:72] : fifo_color[79:72];
fifo_color[87:80] <= ~int_mask[10] ? int_col[87:80] : fifo_color[87:80];
fifo_color[95:88] <= ~int_mask[11] ? int_col[95:88] : fifo_color[95:88];
fifo_color[103:96] <= ~int_mask[12] ? int_col[103:96] : fifo_color[103:96];
fifo_color[111:104] <= ~int_mask[13] ? int_col[111:104] : fifo_color[111:104];
fifo_color[119:112] <= ~int_mask[14] ? int_col[119:112] : fifo_color[119:112];
fifo_color[127:120] <= ~int_mask[15] ? int_col[127:120] : fifo_color[127:120];
z_buffer[7:0] <= ~int_mask[0] ? int_z[7:0] : z_buffer[7:0];
z_buffer[15:8] <= ~int_mask[1] ? int_z[15:8] : z_buffer[15:8];
z_buffer[23:16] <= ~int_mask[2] ? int_z[23:16] : z_buffer[23:16];
z_buffer[31:24] <= ~int_mask[3] ? int_z[31:24] : z_buffer[31:24];
z_buffer[39:32] <= ~int_mask[4] ? int_z[39:32] : z_buffer[39:32];
z_buffer[47:40] <= ~int_mask[5] ? int_z[47:40] : z_buffer[47:40];
z_buffer[55:48] <= ~int_mask[6] ? int_z[55:48] : z_buffer[55:48];
z_buffer[63:56] <= ~int_mask[7] ? int_z[63:56] : z_buffer[63:56];
z_buffer[71:64] <= ~int_mask[8] ? int_z[71:64] : z_buffer[71:64];
z_buffer[79:72] <= ~int_mask[9] ? int_z[79:72] : z_buffer[79:72];
z_buffer[87:80] <= ~int_mask[10] ? int_z[87:80] : z_buffer[87:80];
z_buffer[95:88] <= ~int_mask[11] ? int_z[95:88] : z_buffer[95:88];
z_buffer[103:96] <= ~int_mask[12] ? int_z[103:96] : z_buffer[103:96];
z_buffer[111:104] <= ~int_mask[13] ? int_z[111:104] : z_buffer[111:104];
z_buffer[119:112] <= ~int_mask[14] ? int_z[119:112] : z_buffer[119:112];
z_buffer[127:120] <= ~int_mask[15] ? int_z[127:120] : z_buffer[127:120];
a_buffer[7:0] <= ~int_mask[0] ? pix_a : a_buffer[7:0];
a_buffer[15:8] <= ~int_mask[2] ? pix_a : a_buffer[15:8];
a_buffer[23:16] <= ~int_mask[4] ? pix_a : a_buffer[23:16];
a_buffer[31:24] <= ~int_mask[6] ? pix_a : a_buffer[31:24];
a_buffer[39:32] <= ~int_mask[8] ? pix_a : a_buffer[39:32];
a_buffer[47:40] <= ~int_mask[10] ? pix_a : a_buffer[47:40];
a_buffer[55:48] <= ~int_mask[12] ? pix_a : a_buffer[55:48];
a_buffer[63:56] <= ~int_mask[14] ? pix_a : a_buffer[63:56];
fifo_mask <= ~same_page ? int_mask : int_mask & fifo_mask;
fifo_cmd <= 1'b0; // Line/ Triangle write
fifo_junk[27] <= sol_2;
end else if (dx_mem_req) begin
fifo_junk[27] <= ~imem_rd ? sol_2 : fifo_junk[27];
fifo_color[31:0] <= fore_2;
fifo_color[63:32] <= back_2;
fifo_color[67:64] <= mask_2;
fifo_color[68] <= ps8_2;
fifo_color[69] <= ps16_2;
fifo_color[70] <= ps32_2;
fifo_color[72:71] <= stpl_2;
fifo_color[73] <= dr_trnsp_2;
fifo_color[75:74] <= dr_clp_2;
fifo_color[77:76] <= dr_apat_2;
fifo_color[78] <= solid_2;
fifo_color[79] <= imem_rd;
fifo_color[80] <= rad_flg_2;
fifo_color[83:81] <= strt_wrd_2;
fifo_color[87:84] <= strt_byt_2;
fifo_color[90:88] <= strt_bit_2;
fifo_color[93:91] <= frst8_2;
fifo_color[105:94] <= clp_min_2;
fifo_color[117:106] <= clp_max_2;
fifo_color[121:118] <= cmin_enc_2;
fifo_color[125:122] <= cmax_enc_2;
fifo_color[126] <= y_clip_2;
fifo_color[127] <= eol_2;
fifo_mask <= {12'b0, wcnt};
fifo_cmd <= 1'b1; // BLT operation
end
end
always @(posedge de_clk or negedge de_rstn)
if (!de_rstn) begin
pix_color <= 32'b0;
pix_z <= 32'b0;
pix_a <= 8'b0;
push <= 1'b0;
pc_dirty <= 1'b0;
pc_pending <= 1'b0;
in_x <= 16'h0;
in_y <= 16'h0;
depth <= 2'b0;
pc_busy <= 1'b0;
pc_busy_3d <= 1'b0;
wcnt <= 4'b0;
startup <= 1'b1;
same_page <= 1'b0;
push_previous <= 1'b0;
push_last <= 1'b0;
pipe_push_last <= 1'b0;
dx_delayed <= 1'b0;
data_pending <= 1'b0;
fifo_data <= 271'b0;
fifo_adata <= 128'b0;
fifo_z <= 166'h0;
fifo_push <= 1'b0;
push_d <= 1'b0;
last_pixel_pipe<= 2'b0;
pc_empty <= 1'b0;
hold_push_last <= 1'b0;
hold_3d <= 1'b0;
active_3d_del <= 1'b0;
end else begin
active_3d_del <= active_3d_2;
pc_empty <= fifo_empty;
push_d <= push;
last_pixel_pipe <= {last_pixel_pipe[0], last_pixel};
fifo_push <= dx_delayed | push_previous | pipe_push_last;
fifo_adata <= {fifo_blend_reg_en, a_buffer};
fifo_data <= {
fifo_junk, // [270:243]
fifo_ps, // [242:241]
fifo_key_ctrl, // [240:238]
fifo_blend_en, // [237]
fifo_bsrcr, // [236:233]
fifo_bdstr, // [232:230]
fifo_rop, // [229:226]
fifo_bsrc_alpha, // [225:218]
fifo_bdst_alpha, // [217:210]
fifo_kcol, // [209:178]
fifo_rmw, // [177]
fifo_cmd, // [176]
fifo_address, // [175:144]
fifo_mask, // [143:128]
fifo_color // [127:0]
};
fifo_z <= {
active_3d_del | hold_3d, // [165]
z_en, // [164]
z_ro, // [163]
z_op, // [162:160]
z_address, // [159:128]
z_buffer // [127:0]
};
if (push_d && ~push_previous) data_pending <= 1'b1;
else if (push_d && push_previous || push_last) data_pending <= 1'b0;
push_previous <= 1'b0;
push_last <= 1'b0;
pipe_push_last <= push_last;
dx_delayed <= dx_mem_req;
if (ld_wcnt) wcnt <= fx_1[3:0] - 1'b1;
// pc_busy_3d <= (wrusedw > 64);
pc_busy_3d <= (wrusedw > 96);
pc_busy <= (wrusedw > 120);
// pc_busy <= ~fifo_empty;
push <= 1'b0;
// create the dirty flag
if (pc_ld && ~clip && ~pc_busy) pc_dirty <= 1'b1;
else if (fifo_empty) pc_dirty <= 1'b0;
// Ceate the busy flag
if (last_pixel) pc_pending <= 1'b0;
else if (pc_ld && ~pc_busy) pc_pending <= 1'b1;
//push_last <= (data_pending & last_pixel_pipe[1] & ~pc_busy) |
push_last <= ~hold_push_last & (data_pending & last_pixel_pipe[1] & ~last_pixel_pipe[0]) |
pc_ld & ~pc_busy & last_pixel & ~pc_msk_last & ~(dr_trnsp_2 & ~fg_bgn);
// pc_last <= ~hold_push_last & (data_pending & last_pixel_pipe[1] & ~last_pixel_pipe[0]) |
// pc_ld & ~pc_busy & last_pixel;
pc_last <= (last_pixel_pipe[1] & ~last_pixel_pipe[0]);
if (pc_ld && ~last_pixel) hold_push_last <= 1'b0;
else if (push_last) hold_push_last <= 1'b1;
if (pc_ld && ~last_pixel) hold_3d <= active_3d_2;
if (pc_ld && ~clip && ~pc_busy) begin
//startup <= last_pixel; // each new line
if (last_pixel) startup <= 1'b1;
else if ((~dr_trnsp_2 | dr_trnsp_2 & fg_bgn | solid_2) &
~(last_pixel & pc_msk_last)) startup <= 1'b0;
if (last_pixel) startup <= 1'b1; // each new line
// Added 3D data input (Jim MacLeod)
pix_color <= (solid_2) ? fore_2 :
(valid_3d & fg_bgn_3d) ? pixel_3d :
(fg_bgn) ? fore_2 : back_2;
pix_z <= z_3d;
pix_a <= alpha_3d;
// push if solid, not transparent or transparent + foreground
if ((~dr_trnsp_2 | dr_trnsp_2 & fg_bgn | solid_2) &
~(last_pixel & pc_msk_last)) begin
push <= 1'b1;
// X miss
if (BYTES == 16) begin
push_previous <= ~startup & ((in_x[15:4] != real_dstx[15:4]) |
(in_y != real_dsty));
// make sure to push if really last
same_page <= ~(startup | in_x[15:4] != real_dstx[15:4] |
in_y != real_dsty);
end else if (BYTES == 8) begin
push_previous <= ~startup & ((in_x[15:3] != real_dstx[15:3]) |
(in_y != real_dsty));
// make sure to push if really last
same_page <= ~(startup | in_x[15:3] != real_dstx[15:3] |
in_y != real_dsty);
end else begin
push_previous <= ~startup & ((in_x[15:2] != real_dstx[15:2]) |
(in_y != real_dsty));
// make sure to push if really last
same_page <= ~(startup | in_x[15:2] != real_dstx[15:2] |
in_y != real_dsty);
end
end
// don't push if masking last pix.
in_x <= real_dstx;
in_y <= real_dsty;
depth <= {ps32_2, ps16_2};
end
end
always @*
case (depth)
2'b00: int_col = {16{pix_color[7:0]}};
2'b01: int_col = {8{pix_color[15:0]}};
default: int_col = {4{pix_color}};
endcase // casex({solid_2, fg_bgn_2, ps32_2, ps16_2})
always @*
case (depth)
2'b00: int_z = {16{pix_z[7:0]}};
2'b01: int_z = {8{pix_z[15:0]}};
default: int_z = {4{pix_z}};
endcase // casex({solid_2, fg_bgn_2, ps32_2, ps16_2})
always @*
if (BYTES == 16)
casex ({depth, in_x[3:0]})
// synopsys parallel_case
6'b00_0000: int_mask = 16'hFFFE;
6'b00_0001: int_mask = 16'hFFFD;
6'b00_0010: int_mask = 16'hFFFB;
6'b00_0011: int_mask = 16'hFFF7;
6'b00_0100: int_mask = 16'hFFEF;
6'b00_0101: int_mask = 16'hFFDF;
6'b00_0110: int_mask = 16'hFFBF;
6'b00_0111: int_mask = 16'hFF7F;
6'b00_1000: int_mask = 16'hFEFF;
6'b00_1001: int_mask = 16'hFDFF;
6'b00_1010: int_mask = 16'hFBFF;
6'b00_1011: int_mask = 16'hF7FF;
6'b00_1100: int_mask = 16'hEFFF;
6'b00_1101: int_mask = 16'hDFFF;
6'b00_1110: int_mask = 16'hBFFF;
6'b00_1111: int_mask = 16'h7FFF;
6'b01_000x: int_mask = 16'hFFFC;
6'b01_001x: int_mask = 16'hFFF3;
6'b01_010x: int_mask = 16'hFFCF;
6'b01_011x: int_mask = 16'hFF3F;
6'b01_100x: int_mask = 16'hFCFF;
6'b01_101x: int_mask = 16'hF3FF;
6'b01_110x: int_mask = 16'hCFFF;
6'b01_111x: int_mask = 16'h3FFF;
6'b10_00xx: int_mask = 16'hFFF0;
6'b10_01xx: int_mask = 16'hFF0F;
6'b10_10xx: int_mask = 16'hF0FF;
default: int_mask = 16'h0FFF;
endcase // casex({depth, in_x[3:0]})
else if (BYTES == 8)
casex ({depth, in_x[3:0]})
// synopsys parallel_case
6'b00_x000: int_mask = 16'hFFFE;
6'b00_x001: int_mask = 16'hFFFD;
6'b00_x010: int_mask = 16'hFFFB;
6'b00_x011: int_mask = 16'hFFF7;
6'b00_x100: int_mask = 16'hFFEF;
6'b00_x101: int_mask = 16'hFFDF;
6'b00_x110: int_mask = 16'hFFBF;
6'b00_x111: int_mask = 16'hFF7F;
6'b01_x00x: int_mask = 16'hFFFC;
6'b01_x01x: int_mask = 16'hFFF3;
6'b01_x10x: int_mask = 16'hFFCF;
6'b01_x11x: int_mask = 16'hFF3F;
6'b10_x0xx: int_mask = 16'hFFF0;
default: int_mask = 16'hFF0F;
endcase // casex({depth, in_x[3:0]})
else
casex ({depth, in_x[3:0]})
// synopsys parallel_case
6'b00_xx00: int_mask = 16'hFFFE;
6'b00_xx01: int_mask = 16'hFFFD;
6'b00_xx10: int_mask = 16'hFFFB;
6'b00_xx11: int_mask = 16'hFFF7;
6'b01_xx0x: int_mask = 16'hFFFC;
6'b01_xx1x: int_mask = 16'hFFF3;
default: int_mask = 16'hFFF0;
endcase // casex({depth, in_x[3:0]})
`ifdef RAM_FIFO_271x128
async_fifo
#
(
.WIDTH (271),
.DEPTH (128),
.DLOG2 (7)
) u_fifo_271x128a
(
.aclr (de_rstn),
.wrclk (de_clk),
.wrreq (fifo_push),
.data (fifo_data),
.wr_empty (fifo_empty),
.wrusedw (wrusedw),
.rdclk (mc_clk),
.rdreq (de_pc_pop),
.q (fifo_dout),
.rd_empty (de_pc_empty)
);
async_fifo
#
(
.WIDTH (166),
.DEPTH (128),
.DLOG2 (7)
) u_fifo_181x128a
(
.aclr (de_rstn),
.wrclk (de_clk),
.wrreq (fifo_push),
.data (fifo_z),
.wr_empty (),
.wrusedw (),
.rdclk (mc_clk),
.rdreq (de_pc_pop),
.q (fifo_zout),
.rd_empty ()
);
`else
fifo_128x128a u0_fifo
(
.aclr (~de_rstn),
.data (fifo_data[127:0]),
.rdclk (mc_clk),
.rdreq (mc_acken), // de_pc_pop),
.wrclk (de_clk),
.wrreq (fifo_push),
.q (fifo_dout[127:0]),
.rdempty (de_pc_empty),
.wrempty (fifo_empty),
.wrusedw (wrusedw)
);
fifo_144x128a u1_fifo
(
.aclr (~de_rstn),
.data ({1'b0, fifo_data[270:128]}),
.rdclk (mc_clk),
.rdreq (mc_acken), // de_pc_pop),
.wrclk (de_clk),
.wrreq (fifo_push),
.q ({fifo_dout_extra, fifo_dout[270:128]})
);
fifo_181x128a u2_fifo
(
.aclr (~de_rstn),
.data (fifo_z),
.rdclk (mc_clk),
.rdreq (mc_acken), // de_pc_pop),
.wrclk (de_clk),
.wrreq (fifo_push),
.q (fifo_zout)
);
fifo_128x128a u3_fifo
(
.aclr (~de_rstn),
.data (fifo_adata),
.rdclk (mc_clk),
.rdreq (mc_acken), // de_pc_pop),
.wrclk (de_clk),
.wrreq (fifo_push),
.q (a_dout[127:0])
);
`endif // !`ifdef RAM_FIFO_267x128
always @(posedge mc_clk or negedge de_rstn)
if (!de_rstn) mc_acken <= 1'b0;
else mc_acken <= de_pc_pop;
always @(posedge mc_clk or negedge de_rstn)
if (!de_rstn) begin
px_col <= 128'b0;
px_a <= 64'b0;
px_msk_color <= 16'b0;
de_mc_address<= 32'b0;
de_mc_rmw <= 1'b0;
de_mc_read <= 1'b0;
de_mc_wcnt <= 4'b0;
blt_actv_4 <= 1'b0;
line_actv_4 <= 1'b0;
kcol_4 <= 32'b0;
bdst_alpha_4 <= 8'b0;
bsrc_alpha_4 <= 8'b0;
rop_4 <= 4'b0;
bdstr_4 <= 3'b0;
bsrcr_4 <= 4'b0;
blend_en_4 <= 1'b0;
key_ctrl_4 <= 3'b0;
ps_4 <= 2'b0;
lft_enc_4 <= 7'b0;
rht_enc_4 <= 7'b0;
clp_min_4 <= 12'b0;
clp_max_4 <= 12'b0;
cmin_enc_4 <= 4'b0;
cmax_enc_4 <= 4'b0;
y_clip_4 <= 1'b0;
eol_4 <= 1'b0;
fore_4 <= 32'b0;
back_4 <= 32'b0;
mask_4 <= 4'b0;
ps8_4 <= 1'b0;
ps16_4 <= 1'b0;
ps32_4 <= 1'b0;
stpl_4 <= 2'b0;
trnsp_4 <= 1'b0;
clp_4 <= 2'b0;
apat_4 <= 2'b0;
solid_4 <= 1'b0;
strt_wrd_4 <= 3'b0;
strt_byt_4 <= 4'b0;
strt_bit_4 <= 3'b0;
frst8_4 <= 3'b0;
z_en_4 <= 1'b0;
z_ro_4 <= 1'b0;
z_op_4 <= 3'b0;
z_address_4 <= 32'b0;
z_out <= 128'b0;
end else begin
if (mc_acken) begin
// Z stuff
z_en_4 <= (&fifo_zout[165:164]);
z_ro_4 <= fifo_zout[163];
z_op_4 <= fifo_zout[162:160];
z_address_4 <= fifo_zout[159:128];
z_out <= fifo_zout[127:0];
// Color stuff
px_a <= a_dout[63:0];
blend_reg_en_4<= a_dout[65:64];
px_col <= fifo_dout[127:0];
px_msk_color <= fifo_dout[143:128];
de_mc_address<= fifo_dout[175:144];
de_mc_rmw <= fifo_dout[177];
de_mc_read <= fifo_dout[176] & fifo_dout[79];
de_mc_wcnt <= ~fifo_dout[176] ? 4'b0 : fifo_dout[131:128];
blt_actv_4 <= fifo_dout[176];
line_actv_4 <= ~fifo_dout[176];
kcol_4 <= fifo_dout[209:178];
bdst_alpha_4 <= fifo_dout[217:210];
bsrc_alpha_4 <= fifo_dout[225:218];
rop_4 <= fifo_dout[229:226];
bdstr_4 <= fifo_dout[232:230];
bsrcr_4 <= fifo_dout[236:233];
blend_en_4 <= fifo_dout[237];
key_ctrl_4 <= fifo_dout[240:238];
ps_4 <= fifo_dout[242:241];
lft_enc_4 <= fifo_dout[249:243];
rht_enc_4 <= fifo_dout[256:250];
clp_min_4 <= fifo_dout[105:94];
clp_max_4 <= fifo_dout[117:106];
cmin_enc_4 <= fifo_dout[121:118];
cmax_enc_4 <= fifo_dout[125:122];
y_clip_4 <= fifo_dout[126];
eol_4 <= fifo_dout[127];
// BLT only flags
if (fifo_dout[176]) begin
fore_4 <= fifo_dout[31:0];
back_4 <= fifo_dout[63:32];
mask_4 <= fifo_dout[67:64];
ps8_4 <= fifo_dout[68];
ps16_4 <= fifo_dout[69];
ps32_4 <= fifo_dout[70];
stpl_4 <= fifo_dout[72:71];
trnsp_4 <= fifo_dout[73];
clp_4 <= fifo_dout[75:74];
apat_4 <= fifo_dout[77:76];
solid_4 <= fifo_dout[78];
if (fifo_dout[80]) begin
strt_wrd_4 <= fifo_dout[83:81];
strt_byt_4 <= fifo_dout[87:84];
strt_bit_4 <= fifo_dout[90:88];
end
frst8_4 <= fifo_dout[93:91];
end else begin // if (fifo_dout[172])
mask_4 <= 4'hF; // set mask to 1111 for line
end
end
end // else: !if(!de_rstn)
// page coordinate counter, used to track X during page cycles and produce
// the correct clipping mask
always @(posedge mc_clk)
if (mc_acken && (BYTES == 16)) x_bus_4 <= {2'b00, fifo_dout[268:257]};
else if (mc_acken && (BYTES == 8)) x_bus_4 <= {1'b0, fifo_dout[268:257], 1'b0};
else if (mc_acken) x_bus_4 <= {fifo_dout[268:257], 2'b00};
else if (mc_popen) x_bus_4 <= x_bus_4 + 14'h1;
`ifdef BYTE16
always @(posedge mc_clk)
if (mc_acken) sol_4_int <= fifo_dout[270];
else if (mc_popen) sol_4_int <= 1'b0;
assign sol_4 = sol_4_int[0];
`elsif BYTE8
always @(posedge mc_clk)
if (mc_acken) sol_4_int <= {1'b0, fifo_dout[270], 1'b0};
else if (mc_popen) sol_4_int <= sol_4_int - |sol_4_int;
assign sol_4 = |sol_4_int;
`else
always @(posedge mc_clk)
if (mc_acken) sol_4_int <= {fifo_dout[270], 2'b0};
else if (mc_popen) sol_4_int <= sol_4_int - |sol_4_int;
assign sol_4 = |sol_4_int;
`endif
assign rst_wad_flg_3 = fifo_dout[269];
assign rad_flg_3 = fifo_dout[80];
assign sol_3 = fifo_dout[270];
assign mc_read_3 = fifo_dout[172] & fifo_dout[79];
assign strt_wrd_3 = fifo_dout[80] ? fifo_dout[83:81] : strt_wrd_4;
assign strt_byt_3 = fifo_dout[80] ? fifo_dout[87:84] : strt_byt_4;
assign strt_bit_3 = fifo_dout[80] ? fifo_dout[90:88] : strt_bit_4;
endmodule
|
`default_nettype none
`timescale 1ns/1ns
module tb_memif();
wire clk, reset;
clock clock(clk, reset);
reg a_write = 0;
reg a_read = 0;
reg [31:0] a_writedata = 0;
reg [1:0] a_address;
wire [31:0] a_readdata;
wire a_waitrequest;
wire [17:0] b_address;
wire b_write;
wire b_read;
wire [35:0] b_writedata;
wire [35:0] b_readdata;
wire b_waitrequest;
memif memif0(
.clk(clk),
.reset(reset),
.s_address(a_address),
.s_write(a_write),
.s_read(a_read),
.s_writedata(a_writedata),
.s_readdata(a_readdata),
.s_waitrequest(a_waitrequest),
.m_address(b_address),
.m_write(b_write),
.m_read(b_read),
.m_writedata(b_writedata),
.m_readdata(b_readdata),
.m_waitrequest(b_waitrequest));
dlymemory memory(
.i_clk(clk),
.i_reset_n(reset),
.i_address(b_address),
.i_write(b_write),
.i_read(b_read),
.i_writedata(b_writedata),
.o_readdata(b_readdata),
.o_waitrequest(b_waitrequest));
initial begin
$dumpfile("dump.vcd");
$dumpvars();
memory.mem[4] = 123;
memory.mem[5] = 321;
memory.mem['o123] = 36'o112233445566;
#5;
#200;
// write address
@(posedge clk);
a_address <= 0;
a_write <= 1;
a_writedata <= 32'o123;
@(negedge a_write);
@(posedge clk);
a_address <= 2;
a_read <= 1;
@(negedge a_read);
@(posedge clk);
a_address <= 1;
a_read <= 1;
@(negedge a_read);
/*
// write low word
@(posedge clk);
a_address <= 1;
a_write <= 1;
a_writedata <= 32'o111222;
@(negedge a_write);
// write high word
@(posedge clk);
a_address <= 2;
a_write <= 1;
a_writedata <= 32'o333444;
@(negedge a_write);
*/
end
initial begin
#40000;
$finish;
end
always @(posedge clk) begin
if(~a_waitrequest & a_write)
a_write <= 0;
if(~a_waitrequest & a_read)
a_read <= 0;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A31OI_4_V
`define SKY130_FD_SC_LP__A31OI_4_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog wrapper for a31oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a31oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a31oi_4 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a31oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a31oi_4 (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a31oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A31OI_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYBUF4S25KAPWR_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__DLYBUF4S25KAPWR_PP_BLACKBOX_V
/**
* dlybuf4s25kapwr: Delay Buffer 4-stage 0.25um length inner stage
* gates on keep-alive power rail.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlybuf4s25kapwr (
X ,
A ,
VPWR ,
VGND ,
KAPWR,
VPB ,
VNB
);
output X ;
input A ;
input VPWR ;
input VGND ;
input KAPWR;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYBUF4S25KAPWR_PP_BLACKBOX_V
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
/*
Filename: translation_layer.v
Version: 1.0
Verilog Standard: Verilog-2001
Description: The translation layer provides a uniform interface for all classic
PCIe interfaces, such as all Altera devices, and all Xilinx devices (pre VC709).
Notes: Any modifications to this file should meet the conditions set
forth in the "Trellis Style Guide"
Author: Dustin Richmond (@darichmond)
Co-Authors:
*/
`include "trellis.vh" // Defines the user-facing signal widths.
`include "xilinx.vh"
module translation_xilinx
#(
parameter C_PCI_DATA_WIDTH = 256
)
(
input CLK,
input RST_IN,
// Interface: Xilinx RX
input [C_PCI_DATA_WIDTH-1:0] M_AXIS_RX_TDATA,
input [(C_PCI_DATA_WIDTH/8)-1:0] M_AXIS_RX_TKEEP,
input M_AXIS_RX_TLAST,
input M_AXIS_RX_TVALID,
output M_AXIS_RX_TREADY,
input [`SIG_XIL_RX_TUSER_W-1:0] M_AXIS_RX_TUSER,
output RX_NP_OK,
output RX_NP_REQ,
// Interface: Xilinx TX
output [C_PCI_DATA_WIDTH-1:0] S_AXIS_TX_TDATA,
output [(C_PCI_DATA_WIDTH/8)-1:0] S_AXIS_TX_TKEEP,
output S_AXIS_TX_TLAST,
output S_AXIS_TX_TVALID,
input S_AXIS_TX_TREADY,
output [`SIG_XIL_TX_TUSER_W-1:0] S_AXIS_TX_TUSER,
output TX_CFG_GNT,
// Interface: Xilinx Configuration
input [`SIG_BUSID_W-1:0] CFG_BUS_NUMBER,
input [`SIG_DEVID_W-1:0] CFG_DEVICE_NUMBER,
input [`SIG_FNID_W-1:0] CFG_FUNCTION_NUMBER,
input [`SIG_CFGREG_W-1:0] CFG_COMMAND,
input [`SIG_CFGREG_W-1:0] CFG_DCOMMAND,
input [`SIG_CFGREG_W-1:0] CFG_LSTATUS,
input [`SIG_CFGREG_W-1:0] CFG_LCOMMAND,
// Interface: Xilinx Flow Control
input [`SIG_FC_CPLD_W-1:0] FC_CPLD,
input [`SIG_FC_CPLH_W-1:0] FC_CPLH,
output [`SIG_FC_SEL_W-1:0] FC_SEL,
// Interface: Xilinx Interrupt
input CFG_INTERRUPT_MSIEN,
input CFG_INTERRUPT_RDY,
output CFG_INTERRUPT,
// Interface: RX Classic
output [C_PCI_DATA_WIDTH-1:0] RX_TLP,
output RX_TLP_VALID,
output RX_TLP_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RX_TLP_START_OFFSET,
output RX_TLP_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RX_TLP_END_OFFSET,
output [`SIG_BARDECODE_W-1:0] RX_TLP_BAR_DECODE,
input RX_TLP_READY,
// Interface: TX Classic
output TX_TLP_READY,
input [C_PCI_DATA_WIDTH-1:0] TX_TLP,
input TX_TLP_VALID,
input TX_TLP_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TX_TLP_START_OFFSET,
input TX_TLP_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TX_TLP_END_OFFSET,
// Interface: Configuration
output [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
output CONFIG_BUS_MASTER_ENABLE,
output [`SIG_LINKWIDTH_W-1:0] CONFIG_LINK_WIDTH,
output [`SIG_LINKRATE_W-1:0] CONFIG_LINK_RATE,
output [`SIG_MAXREAD_W-1:0] CONFIG_MAX_READ_REQUEST_SIZE,
output [`SIG_MAXPAYLOAD_W-1:0] CONFIG_MAX_PAYLOAD_SIZE,
output CONFIG_INTERRUPT_MSIENABLE,
output CONFIG_CPL_BOUNDARY_SEL,
// Interface: Flow Control
output [`SIG_FC_CPLD_W-1:0] CONFIG_MAX_CPL_DATA,
output [`SIG_FC_CPLH_W-1:0] CONFIG_MAX_CPL_HDR,
// Interface: Interrupt
output INTR_MSI_RDY, // High when interrupt is able to be sent
input INTR_MSI_REQUEST // High to request interrupt
);
/*
Notes on the Configuration Interface:
Link Width (cfg_lstatus[9:4]): 000001=x1, 000010=x2, 000100=x4, 001000=x8, 001100=x12, 010000=x16
Link Rate (cfg_lstatus[3:0]): 0001=2.5GT/s, 0010=5.0GT/s, 0011=8.0GT/s
Max Read Request Size (cfg_dcommand[14:12]): 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
Max Payload Size (cfg_dcommand[7:5]): 000=128B, 001=256B, 010=512B, 011=1024B
Bus Master Enable (cfg_command[2]): 1=Enabled, 0=Disabled
Read Completion Boundary (cfg_lcommand[3]): 0=64 bytes, 1=128 bytes
MSI Enable (cfg_msicsr[0]): 1=Enabled, 0=Disabled
Notes on the Flow Control Interface:
FC_CPLD (Xilinx) Receive credit limit for data
FC_CPLH (Xilinx) Receive credit limit for headers
FC_SEL (Xilinx Only) Selects the correct output on the FC_* signals
Notes on the TX Interface:
TX_CFG_GNT (Xilinx): 1=Always allow core to transmit internally generated TLPs
Notes on the RX Interface:
RX_NP_OK (Xilinx): 1=Always allow non posted transactions
*/
/*AUTOWIRE*/
reg rRxTlpValid;
reg rRxTlpEndFlag;
// Rx Interface (From PCIe Core)
assign RX_TLP = M_AXIS_RX_TDATA;
assign RX_TLP_VALID = M_AXIS_RX_TVALID;
// Rx Interface (To PCIe Core)
assign M_AXIS_RX_TREADY = RX_TLP_READY;
// TX Interface (From PCIe Core)
assign TX_TLP_READY = S_AXIS_TX_TREADY;
// TX Interface (TO PCIe Core)
assign S_AXIS_TX_TDATA = TX_TLP;
assign S_AXIS_TX_TVALID = TX_TLP_VALID;
assign S_AXIS_TX_TLAST = TX_TLP_END_FLAG;
// Configuration Interface
assign CONFIG_COMPLETER_ID = {CFG_BUS_NUMBER,CFG_DEVICE_NUMBER,CFG_FUNCTION_NUMBER};
assign CONFIG_BUS_MASTER_ENABLE = CFG_COMMAND[`CFG_COMMAND_BUSMSTR_R];
assign CONFIG_LINK_WIDTH = CFG_LSTATUS[`CFG_LSTATUS_LWIDTH_R];
assign CONFIG_LINK_RATE = CFG_LSTATUS[`CFG_LSTATUS_LRATE_R];
assign CONFIG_MAX_READ_REQUEST_SIZE = CFG_DCOMMAND[`CFG_DCOMMAND_MAXREQ_R];
assign CONFIG_MAX_PAYLOAD_SIZE = CFG_DCOMMAND[`CFG_DCOMMAND_MAXPAY_R];
assign CONFIG_INTERRUPT_MSIENABLE = CFG_INTERRUPT_MSIEN;
assign CONFIG_CPL_BOUNDARY_SEL = CFG_LCOMMAND[`CFG_LCOMMAND_RCB_R];
assign CONFIG_MAX_CPL_DATA = FC_CPLD;
assign CONFIG_MAX_CPL_HDR = FC_CPLH;
assign FC_SEL = `SIG_FC_SEL_RX_MAXALLOC_V;
assign RX_NP_OK = 1'b1;
assign RX_NP_REQ = 1'b1;
assign TX_CFG_GNT = 1'b1;
// Interrupt interface
assign CFG_INTERRUPT = INTR_MSI_REQUEST;
assign INTR_MSI_RDY = CFG_INTERRUPT_RDY;
generate
if (C_PCI_DATA_WIDTH == 9'd32) begin : gen_xilinx_32
assign RX_TLP_START_FLAG = ~rRxTlpValid | rRxTlpEndFlag;
assign RX_TLP_START_OFFSET = {clog2s(C_PCI_DATA_WIDTH/32){1'b0}};
assign RX_TLP_END_OFFSET = 0;
assign RX_TLP_END_FLAG = M_AXIS_RX_TLAST;
assign S_AXIS_TX_TKEEP = 4'hF;
end else if (C_PCI_DATA_WIDTH == 9'd64) begin : gen_xilinx_64
assign RX_TLP_START_FLAG = ~rRxTlpValid | rRxTlpEndFlag;
assign RX_TLP_START_OFFSET = {clog2s(C_PCI_DATA_WIDTH/32){1'b0}};
assign RX_TLP_END_OFFSET = M_AXIS_RX_TKEEP[4];
assign RX_TLP_END_FLAG = M_AXIS_RX_TLAST;
assign S_AXIS_TX_TKEEP = {{4{TX_TLP_END_OFFSET | ~TX_TLP_END_FLAG}},4'hF};
end else if (C_PCI_DATA_WIDTH == 9'd128) begin : gen_xilinx_128
assign RX_TLP_END_OFFSET = M_AXIS_RX_TUSER[20:19];
assign RX_TLP_END_FLAG = M_AXIS_RX_TUSER[21];
assign RX_TLP_START_FLAG = M_AXIS_RX_TUSER[14];
assign RX_TLP_START_OFFSET = M_AXIS_RX_TUSER[13:12];
assign S_AXIS_TX_TKEEP = {{4{~TX_TLP_END_FLAG | (TX_TLP_END_OFFSET == 2'b11)}},
{4{~TX_TLP_END_FLAG | (TX_TLP_END_OFFSET >= 2'b10)}},
{4{~TX_TLP_END_FLAG | (TX_TLP_END_OFFSET >= 2'b01)}},
{4{1'b1}}};// TODO: More efficient if we use masks...
end else if (C_PCI_DATA_WIDTH == 9'd256) begin : x256
// Not possible...
end
endgenerate
always @(posedge CLK) begin
rRxTlpValid <= RX_TLP_VALID;
rRxTlpEndFlag <= RX_TLP_END_FLAG;
end
endmodule // translation_layer
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_FPGA_SDRAM_test_component_ram_module (
// inputs:
data,
rdaddress,
rdclken,
wraddress,
wrclock,
wren,
// outputs:
q
)
;
output [ 15: 0] q;
input [ 15: 0] data;
input [ 24: 0] rdaddress;
input rdclken;
input [ 24: 0] wraddress;
input wrclock;
input wren;
reg [ 15: 0] mem_array [33554431: 0];
wire [ 15: 0] q;
reg [ 24: 0] read_address;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(rdaddress)
begin
read_address = rdaddress;
end
// Data read is asynchronous.
assign q = mem_array[read_address];
initial
$readmemh("soc_system_FPGA_SDRAM_test_component.dat", mem_array);
always @(posedge wrclock)
begin
// Write data
if (wren)
mem_array[wraddress] <= data;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// always @(rdaddress)
// begin
// read_address = rdaddress;
// end
//
//
// lpm_ram_dp lpm_ram_dp_component
// (
// .data (data),
// .q (q),
// .rdaddress (read_address),
// .rdclken (rdclken),
// .wraddress (wraddress),
// .wrclock (wrclock),
// .wren (wren)
// );
//
// defparam lpm_ram_dp_component.lpm_file = "UNUSED",
// lpm_ram_dp_component.lpm_hint = "USE_EAB=ON",
// lpm_ram_dp_component.lpm_indata = "REGISTERED",
// lpm_ram_dp_component.lpm_outdata = "UNREGISTERED",
// lpm_ram_dp_component.lpm_rdaddress_control = "UNREGISTERED",
// lpm_ram_dp_component.lpm_width = 16,
// lpm_ram_dp_component.lpm_widthad = 25,
// lpm_ram_dp_component.lpm_wraddress_control = "REGISTERED",
// lpm_ram_dp_component.suppress_memory_conversion_warnings = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_FPGA_SDRAM_test_component (
// inputs:
clk,
zs_addr,
zs_ba,
zs_cas_n,
zs_cke,
zs_cs_n,
zs_dqm,
zs_ras_n,
zs_we_n,
// outputs:
zs_dq
)
;
inout [ 15: 0] zs_dq;
input clk;
input [ 12: 0] zs_addr;
input [ 1: 0] zs_ba;
input zs_cas_n;
input zs_cke;
input zs_cs_n;
input [ 1: 0] zs_dqm;
input zs_ras_n;
input zs_we_n;
wire [ 23: 0] CODE;
wire [ 12: 0] a;
wire [ 9: 0] addr_col;
reg [ 14: 0] addr_crb;
wire [ 1: 0] ba;
wire cas_n;
wire cke;
wire [ 2: 0] cmd_code;
wire cs_n;
wire [ 1: 0] dqm;
wire [ 2: 0] index;
reg [ 2: 0] latency;
wire [ 1: 0] mask;
wire [ 15: 0] mem_bytes;
wire ras_n;
reg [ 24: 0] rd_addr_pipe_0;
reg [ 24: 0] rd_addr_pipe_1;
reg [ 24: 0] rd_addr_pipe_2;
reg [ 1: 0] rd_mask_pipe_0;
reg [ 1: 0] rd_mask_pipe_1;
reg [ 1: 0] rd_mask_pipe_2;
reg [ 2: 0] rd_valid_pipe;
wire [ 24: 0] read_addr;
wire [ 15: 0] read_data;
wire [ 1: 0] read_mask;
wire [ 15: 0] read_temp;
wire read_valid;
wire [ 15: 0] rmw_temp;
wire [ 24: 0] test_addr;
wire [ 23: 0] txt_code;
wire we_n;
wire [ 15: 0] zs_dq;
initial
begin
$write("\n");
$write("************************************************************\n");
$write("This testbench includes an SOPC Builder Generated Altera model:\n");
$write("'soc_system_FPGA_SDRAM_test_component.v', to simulate accesses to SDRAM.\n");
$write("Initial contents are loaded from the file: 'soc_system_FPGA_SDRAM_test_component.dat'.\n");
$write("************************************************************\n");
end
//Synchronous write when (CODE == 24'h205752 (write))
soc_system_FPGA_SDRAM_test_component_ram_module soc_system_FPGA_SDRAM_test_component_ram
(
.data (rmw_temp),
.q (read_data),
.rdaddress ((CODE == 24'h205752) ? test_addr : read_addr),
.rdclken (1'b1),
.wraddress (test_addr),
.wrclock (clk),
.wren (CODE == 24'h205752)
);
assign cke = zs_cke;
assign cs_n = zs_cs_n;
assign ras_n = zs_ras_n;
assign cas_n = zs_cas_n;
assign we_n = zs_we_n;
assign dqm = zs_dqm;
assign ba = zs_ba;
assign a = zs_addr;
assign cmd_code = {ras_n, cas_n, we_n};
assign CODE = (&cs_n) ? 24'h494e48 : txt_code;
assign addr_col = a[9 : 0];
assign test_addr = {addr_crb, addr_col};
assign mem_bytes = read_data;
assign rmw_temp[7 : 0] = dqm[0] ? mem_bytes[7 : 0] : zs_dq[7 : 0];
assign rmw_temp[15 : 8] = dqm[1] ? mem_bytes[15 : 8] : zs_dq[15 : 8];
// Handle Input.
always @(posedge clk)
begin
// No Activity of Clock Disabled
if (cke)
begin
// LMR: Get CAS_Latency.
if (CODE == 24'h4c4d52)
latency <= a[6 : 4];
// ACT: Get Row/Bank Address.
if (CODE == 24'h414354)
addr_crb <= {ba[1], a, ba[0]};
rd_valid_pipe[2] <= rd_valid_pipe[1];
rd_valid_pipe[1] <= rd_valid_pipe[0];
rd_valid_pipe[0] <= CODE == 24'h205244;
rd_addr_pipe_2 <= rd_addr_pipe_1;
rd_addr_pipe_1 <= rd_addr_pipe_0;
rd_addr_pipe_0 <= test_addr;
rd_mask_pipe_2 <= rd_mask_pipe_1;
rd_mask_pipe_1 <= rd_mask_pipe_0;
rd_mask_pipe_0 <= dqm;
end
end
assign read_temp[7 : 0] = mask[0] ? 8'bz : read_data[7 : 0];
assign read_temp[15 : 8] = mask[1] ? 8'bz : read_data[15 : 8];
//use index to select which pipeline stage drives addr
assign read_addr = (index == 0)? rd_addr_pipe_0 :
(index == 1)? rd_addr_pipe_1 :
rd_addr_pipe_2;
//use index to select which pipeline stage drives mask
assign read_mask = (index == 0)? rd_mask_pipe_0 :
(index == 1)? rd_mask_pipe_1 :
rd_mask_pipe_2;
//use index to select which pipeline stage drives valid
assign read_valid = (index == 0)? rd_valid_pipe[0] :
(index == 1)? rd_valid_pipe[1] :
rd_valid_pipe[2];
assign index = latency - 1'b1;
assign mask = read_mask;
assign zs_dq = read_valid ? read_temp : {16{1'bz}};
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign txt_code = (cmd_code == 3'h0)? 24'h4c4d52 :
(cmd_code == 3'h1)? 24'h415246 :
(cmd_code == 3'h2)? 24'h505245 :
(cmd_code == 3'h3)? 24'h414354 :
(cmd_code == 3'h4)? 24'h205752 :
(cmd_code == 3'h5)? 24'h205244 :
(cmd_code == 3'h6)? 24'h425354 :
(cmd_code == 3'h7)? 24'h4e4f50 :
24'h424144;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
|
// ====================================================================
// Radio-86RK FPGA REPLICA
//
// Copyright (C) 2011 Dmitry Tselikov
//
// This core is distributed under modified BSD license.
// For complete licensing information see LICENSE.TXT.
// --------------------------------------------------------------------
//
// An open implementation of K580WT57 DMA controller
//
// Author: Dmitry Tselikov http://bashkiria-2m.narod.ru/
//
// Design File: k580wt57.v
//
// Warning: This realization is not fully operational.
module k580wt57(
input clk,
input ce,
input reset,
input[3:0] iaddr,
input[7:0] idata,
input[3:0] drq,
input iwe_n,
input ird_n,
input hlda,
output hrq,
output reg[3:0] dack,
output[7:0] odata,
output[15:0] oaddr,
output owe_n,
output ord_n,
output oiowe_n,
output oiord_n );
parameter ST_IDLE = 3'b000;
parameter ST_WAIT = 3'b001;
parameter ST_T1 = 3'b010;
parameter ST_T2 = 3'b011;
parameter ST_T3 = 3'b100;
parameter ST_T4 = 3'b101;
parameter ST_T5 = 3'b110;
parameter ST_T6 = 3'b111;
reg[2:0] state;
reg[1:0] channel;
reg[7:0] mode;
reg[4:0] chstate;
reg[15:0] chaddr[3:0];
reg[15:0] chtcnt[3:0];
reg ff,exiwe_n;
assign hrq = state!=ST_IDLE;
assign odata = {3'b0,chstate};
assign oaddr = chaddr[channel];
assign owe_n = chtcnt[channel][14]==0 || state!=ST_T2;
assign ord_n = chtcnt[channel][15]==0 || (state!=ST_T1 && state!=ST_T2);
assign oiowe_n = chtcnt[channel][15]==0 || state!=ST_T2;
assign oiord_n = chtcnt[channel][14]==0 || (state!=ST_T1 && state!=ST_T2);
wire[3:0] mdrq = drq & mode[3:0];
always @(posedge clk or posedge reset) begin
if (reset) begin
state <= 0; ff <= 0; mode <= 0; exiwe_n <= 1'b1;
chstate <= 0; dack <= 0;
end else begin
exiwe_n <= iwe_n;
if (iwe_n && ~exiwe_n) begin
ff <= ~(ff|iaddr[3]);
if (ff) begin
if(iaddr==4'b0000) chaddr[0][15:8] <= idata;
if(iaddr==4'b0001) chtcnt[0][15:8] <= idata;
if(iaddr==4'b0010) chaddr[1][15:8] <= idata;
if(iaddr==4'b0011) chtcnt[1][15:8] <= idata;
if(iaddr==4'b0100) chaddr[2][15:8] <= idata;
if(iaddr==4'b0101) chtcnt[2][15:8] <= idata;
if(iaddr==4'b0110 || (iaddr==4'b0100 && mode[7]==1'b1)) chaddr[3][15:8] <= idata;
if(iaddr==4'b0111 || (iaddr==4'b0101 && mode[7]==1'b1)) chtcnt[3][15:8] <= idata;
end else begin
if(iaddr==4'b0000) chaddr[0][7:0] <= idata;
if(iaddr==4'b0001) chtcnt[0][7:0] <= idata;
if(iaddr==4'b0010) chaddr[1][7:0] <= idata;
if(iaddr==4'b0011) chtcnt[1][7:0] <= idata;
if(iaddr==4'b0100) chaddr[2][7:0] <= idata;
if(iaddr==4'b0101) chtcnt[2][7:0] <= idata;
if(iaddr==4'b0110 || (iaddr==4'b0100 && mode[7]==1'b1)) chaddr[3][7:0] <= idata;
if(iaddr==4'b0111 || (iaddr==4'b0101 && mode[7]==1'b1)) chtcnt[3][7:0] <= idata;
end
if (iaddr[3]) mode <= idata;
end
if (ce) begin
case (state)
ST_IDLE: begin
if (|mdrq) state <= ST_WAIT;
end
ST_WAIT: begin
if (hlda) state <= ST_T1;
casex (mdrq[3:1])
3'b1xx: channel <= 2'b11;
3'b01x: channel <= 2'b10;
3'b001: channel <= 2'b01;
3'b000: channel <= 2'b00;
endcase
end
ST_T1: begin
state <= ST_T2;
dack[channel] <= 1'b1;
end
ST_T2: begin
if (mdrq[channel]==0) begin
dack[channel] <= 0;
if (chtcnt[channel][13:0]==0) begin
chstate[channel] <= 1'b1;
if (mode[7]==1'b1 && channel==2'b10) begin
chaddr[channel] <= chaddr[2'b11];
chtcnt[channel][13:0] <= chtcnt[2'b11][13:0];
end
end else begin
chaddr[channel] <= chaddr[channel]+1'b1;
chtcnt[channel][13:0] <= chtcnt[channel][13:0]+14'h3FFF;
end
state <= ST_T3;
end
end
ST_T3: begin
state <= |mdrq ? ST_WAIT : ST_IDLE;
end
endcase
end
end
end
endmodule
|
/*this module will realise the 8 Registers the processor provides.
Tofu tries not to create a bus system. The Idea is to hardwire everything, this will prevent floating wires.
*/
module regbank (addr1, addr2, addrdest, data1, data2, datadest, control, enable);
input wire [2:0] addr1, addr2, addrdest, datadest;
output wire [7:0] data1, data2;
input wire [2:0] control;
input wire enable;
reg [7:0] r0,r1,r2,r3,r4,r5,r6,r7;
always @ (posedge enable) begin
if (control[0]) begin
case(addr1)
0 : data1 = r0;
1 : data1 = r1;
2 : data1 = r2;
3 : data1 = r3;
4 : data1 = r4;
5 : data1 = r5;
6 : data1 = r6;
default : data1 = r7;
endcase
end
if (control[1]) begin
case(addr2)
0 : data2 = r0;
1 : data2 = r1;
2 : data2 = r2;
3 : data2 = r3;
4 : data2 = r4;
5 : data2 = r5;
6 : data2 = r6;
default : data1 = r7;
endcase
end
if (control[2]) begin
case(addrdest)
0 : r0 = datadest;
1 : r1 = datadest;
2 : r2 = datadest;
3 : r3 = datadest;
4 : r4 = datadest;
5 : r5 = datadest;
6 : r6 = datadest;
default : r7 = datadest;
endcase
end
end
endmodule
|
//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2006, 2007, 2008 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.0
// \ \ Application: MIG
// / / Filename: ddr2_ctrl.v
// /___/ /\ Date Last Modified: $Date: 2008/12/23 14:26:00 $
// \ \ / \ Date Created: Wed Aug 30 2006
// \___\/\___\
//
//
//Device: Virtex-5
//Design Name: DDR/DDR2
//Purpose:
// This module is the main control logic of the memory interface. All
// commands are issued from here according to the burst, CAS Latency and the
// user commands.
//Reference:
//Revision History:
// Rev 1.2 - Fixed auto refresh to activate bug. KP 11-19-2007
// Rev 1.3 - For Dual Rank parts support CS logic modified. KP. 05/08/08
// Rev 1.4 - AUTO_REFRESH_WAIT state modified for Auto Refresh flag asserted
// immediately after calibration is completed. KP. 07/28/08
// Rev 1.5 - Assignment of bank_valid_r is modified to fix a bug in
// Bank Management logic. PK. 10/29/08
//*****************************************************************************
`timescale 1ns/1ps
module ddr2_ctrl #
(
// Following parameters are for 72-bit RDIMM design (for ML561 Reference
// board design). Actual values may be different. Actual parameters values
// are passed from design top module ddr2_mig module. Please refer to
// the ddr2_mig module for actual values.
parameter BANK_WIDTH = 2,
parameter COL_WIDTH = 10,
parameter CS_BITS = 0,
parameter CS_NUM = 1,
parameter ROW_WIDTH = 14,
parameter ADDITIVE_LAT = 0,
parameter BURST_LEN = 4,
parameter CAS_LAT = 5,
parameter ECC_ENABLE = 0,
parameter REG_ENABLE = 1,
parameter TREFI_NS = 7800,
parameter TRAS = 40000,
parameter TRCD = 15000,
parameter TRRD = 10000,
parameter TRFC = 105000,
parameter TRP = 15000,
parameter TRTP = 7500,
parameter TWR = 15000,
parameter TWTR = 10000,
parameter CLK_PERIOD = 3000,
parameter MULTI_BANK_EN = 1,
parameter TWO_T_TIME_EN = 0,
parameter DDR_TYPE = 1
)
(
input clk,
input rst,
input [2:0] af_cmd,
input [30:0] af_addr,
input af_empty,
input phy_init_done,
output ctrl_ref_flag,
output ctrl_af_rden,
output reg ctrl_wren,
output reg ctrl_rden,
output [ROW_WIDTH-1:0] ctrl_addr,
output [BANK_WIDTH-1:0] ctrl_ba,
output ctrl_ras_n,
output ctrl_cas_n,
output ctrl_we_n,
output [CS_NUM-1:0] ctrl_cs_n
, input sp_refresh_disable
);
// input address split into various ranges
localparam ROW_RANGE_START = COL_WIDTH;
localparam ROW_RANGE_END = ROW_WIDTH + ROW_RANGE_START - 1;
localparam BANK_RANGE_START = ROW_RANGE_END + 1;
localparam BANK_RANGE_END = BANK_WIDTH + BANK_RANGE_START - 1;
localparam CS_RANGE_START = BANK_RANGE_START + BANK_WIDTH;
localparam CS_RANGE_END = CS_BITS + CS_RANGE_START - 1;
// compare address (for determining bank/row hits) split into various ranges
// (compare address doesn't include column bits)
localparam CMP_WIDTH = CS_BITS + BANK_WIDTH + ROW_WIDTH;
localparam CMP_ROW_RANGE_START = 0;
localparam CMP_ROW_RANGE_END = ROW_WIDTH + CMP_ROW_RANGE_START - 1;
localparam CMP_BANK_RANGE_START = CMP_ROW_RANGE_END + 1;
localparam CMP_BANK_RANGE_END = BANK_WIDTH + CMP_BANK_RANGE_START - 1;
localparam CMP_CS_RANGE_START = CMP_BANK_RANGE_END + 1;
localparam CMP_CS_RANGE_END = CS_BITS + CMP_CS_RANGE_START-1;
localparam BURST_LEN_DIV2 = BURST_LEN / 2;
localparam OPEN_BANK_NUM = 4;
localparam CS_BITS_FIX = (CS_BITS == 0) ? 1 : CS_BITS;
// calculation counters based on clock cycle and memory parameters
// TRAS: ACTIVE->PRECHARGE interval - 2
localparam integer TRAS_CYC = (TRAS + CLK_PERIOD)/CLK_PERIOD;
// TRCD: ACTIVE->READ/WRITE interval - 3 (for DDR2 factor in ADD_LAT)
localparam integer TRRD_CYC = (TRRD + CLK_PERIOD)/CLK_PERIOD;
localparam integer TRCD_CYC = (((TRCD + CLK_PERIOD)/CLK_PERIOD) >
ADDITIVE_LAT )?
((TRCD+CLK_PERIOD)/ CLK_PERIOD) - ADDITIVE_LAT : 0;
// TRFC: REFRESH->REFRESH, REFRESH->ACTIVE interval - 2
localparam integer TRFC_CYC = (TRFC + CLK_PERIOD)/CLK_PERIOD;
// TRP: PRECHARGE->COMMAND interval - 2
// for precharge all add 1 extra clock cycle
localparam integer TRP_CYC = ((TRP + CLK_PERIOD)/CLK_PERIOD) +1;
// TRTP: READ->PRECHARGE interval - 2 (Al + BL/2 + (max (TRTP, 2tck))-2
localparam integer TRTP_TMP_MIN = (((TRTP + CLK_PERIOD)/CLK_PERIOD) >= 2)?
((TRTP + CLK_PERIOD)/CLK_PERIOD) : 2;
localparam integer TRTP_CYC = TRTP_TMP_MIN + ADDITIVE_LAT
+ BURST_LEN_DIV2 - 2;
// TWR: WRITE->PRECHARGE interval - 2
localparam integer WR_LAT = (DDR_TYPE > 0) ? CAS_LAT + ADDITIVE_LAT - 1 : 1;
localparam integer TWR_CYC = ((TWR + CLK_PERIOD)/CLK_PERIOD) +
WR_LAT + BURST_LEN_DIV2 ;
// TWTR: WRITE->READ interval - 3 (for DDR1, TWTR = 2 clks)
// DDR2 = CL-1 + BL/2 +TWTR
localparam integer TWTR_TMP_MIN = (TWTR + CLK_PERIOD)/CLK_PERIOD;
localparam integer TWTR_CYC = (DDR_TYPE > 0) ? (TWTR_TMP_MIN + (CAS_LAT -1)
+ BURST_LEN_DIV2 ): 2;
// TRTW: READ->WRITE interval - 3
// DDR1: CL + (BL/2)
// DDR2: (BL/2) + 2. Two more clocks are added to
// the DDR2 counter to account for the delay in
// arrival of the DQS during reads (pcb trace + buffer
// delays + memory parameters).
localparam TRTW_CYC = (DDR_TYPE > 0) ? BURST_LEN_DIV2 + 4 :
(CAS_LAT == 25) ? 2 + BURST_LEN_DIV2 : CAS_LAT + BURST_LEN_DIV2;
localparam integer CAS_LAT_RD = (CAS_LAT == 25) ? 2 : CAS_LAT;
// Make sure all values >= 0 (some may be = 0)
localparam TRAS_COUNT = (TRAS_CYC > 0) ? TRAS_CYC : 0;
localparam TRCD_COUNT = (TRCD_CYC > 0) ? TRCD_CYC : 0;
localparam TRRD_COUNT = (TRRD_CYC > 0) ? TRRD_CYC : 0;
localparam TRFC_COUNT = (TRFC_CYC > 0) ? TRFC_CYC : 0;
localparam TRP_COUNT = (TRP_CYC > 0) ? TRP_CYC : 0;
localparam TRTP_COUNT = (TRTP_CYC > 0) ? TRTP_CYC : 0;
localparam TWR_COUNT = (TWR_CYC > 0) ? TWR_CYC : 0;
localparam TWTR_COUNT = (TWTR_CYC > 0) ? TWTR_CYC : 0;
localparam TRTW_COUNT = (TRTW_CYC > 0) ? TRTW_CYC : 0;
// Auto refresh interval
localparam TREFI_COUNT = 12'b111111111111; //((TREFI_NS * 1000)/CLK_PERIOD) - 1;
// memory controller states
localparam CTRL_IDLE = 5'h00;
localparam CTRL_PRECHARGE = 5'h01;
localparam CTRL_PRECHARGE_WAIT = 5'h02;
localparam CTRL_AUTO_REFRESH = 5'h03;
localparam CTRL_AUTO_REFRESH_WAIT = 5'h04;
localparam CTRL_ACTIVE = 5'h05;
localparam CTRL_ACTIVE_WAIT = 5'h06;
localparam CTRL_BURST_READ = 5'h07;
localparam CTRL_READ_WAIT = 5'h08;
localparam CTRL_BURST_WRITE = 5'h09;
localparam CTRL_WRITE_WAIT = 5'h0A;
localparam CTRL_PRECHARGE_WAIT1 = 5'h0B;
reg [CMP_WIDTH-1:0] act_addr_r;
wire [30:0] af_addr_r;
reg [30:0] af_addr_r1;
reg [30:0] af_addr_r2;
reg [30:0] af_addr_r3;
wire [2:0] af_cmd_r;
reg [2:0] af_cmd_r1;
reg [2:0] af_cmd_r2;
reg af_valid_r;
reg af_valid_r1;
reg af_valid_r2;
reg [CS_BITS_FIX :0] auto_cnt_r;
reg auto_ref_r;
reg [(OPEN_BANK_NUM*CMP_WIDTH)-1:0] bank_cmp_addr_r;
reg [OPEN_BANK_NUM-1:0] bank_hit;
reg [OPEN_BANK_NUM-1:0] bank_hit_r;
reg [OPEN_BANK_NUM-1:0] bank_hit_r1;
reg [OPEN_BANK_NUM-1:0] bank_valid_r;
reg bank_conflict_r;
reg conflict_resolved_r;
reg ctrl_af_rden_r;
reg conflict_detect_r;
wire conflict_detect;
reg cs_change_r;
reg cs_change_sticky_r;
reg [ROW_WIDTH-1:0] ddr_addr_r;
wire [ROW_WIDTH-1:0] ddr_addr_col;
wire [ROW_WIDTH-1:0] ddr_addr_row;
reg [BANK_WIDTH-1:0] ddr_ba_r;
reg ddr_cas_n_r;
reg [CS_NUM-1:0] ddr_cs_n_r;
reg ddr_ras_n_r;
reg ddr_we_n_r;
reg [4:0] next_state;
reg no_precharge_wait_r;
reg no_precharge_r;
reg no_precharge_r1;
reg phy_init_done_r;
reg [4:0] precharge_ok_cnt_r;
reg precharge_ok_r;
reg [4:0] ras_cnt_r;
reg [3:0] rcd_cnt_r;
reg rcd_cnt_ok_r;
reg [2:0] rdburst_cnt_r;
reg rdburst_ok_r;
reg rdburst_rden_ok_r;
reg rd_af_flag_r;
wire rd_flag;
reg rd_flag_r;
reg [4:0] rd_to_wr_cnt_r;
reg rd_to_wr_ok_r;
reg ref_flag_r;
reg [11:0] refi_cnt_r;
reg refi_cnt_ok_r;
reg rst_r
/* synthesis syn_preserve = 1 */;
reg rst_r1
/* synthesis syn_maxfan = 10 */;
reg [7:0] rfc_cnt_r;
reg rfc_ok_r;
reg [3:0] row_miss;
reg [3:0] row_conflict_r;
reg [3:0] rp_cnt_r;
reg rp_cnt_ok_r;
reg [CMP_WIDTH-1:0] sb_open_add_r;
reg [4:0] state_r;
reg [4:0] state_r1;
wire sm_rden;
reg sm_rden_r;
reg [2:0] trrd_cnt_r;
reg trrd_cnt_ok_r;
reg [2:0] two_t_enable_r;
reg [CS_NUM-1:0] two_t_enable_r1;
reg [2:0] wrburst_cnt_r;
reg wrburst_ok_r;
reg wrburst_wren_ok_r;
wire wr_flag;
reg wr_flag_r;
reg [4:0] wr_to_rd_cnt_r;
reg wr_to_rd_ok_r;
// XST attributes for local reset "tree"
// synthesis attribute shreg_extract of rst_r is "no";
// synthesis attribute shreg_extract of rst_r1 is "no";
// synthesis attribute equivalent_register_removal of rst_r is "no"
//***************************************************************************
// sm_rden is used to assert read enable to the address FIFO
assign sm_rden = ((state_r == CTRL_BURST_WRITE) ||
(state_r == CTRL_BURST_READ)) ;
// Assert this when approaching refresh and not in an access
reg ref_approaching;
always @(posedge clk)
ref_approaching <= (refi_cnt_r >= (TREFI_COUNT -80)) & ~af_valid_r2;
reg ref_just_happened;
always @(posedge clk)
ref_just_happened <= (refi_cnt_r < 12'h30) & ~af_valid_r2;
// assert read flag to the adress FIFO
assign ctrl_af_rden = (sm_rden || rd_af_flag_r) & !(ref_approaching | ref_just_happened);
// local reset "tree" for controller logic only. Create this to ease timing
// on reset path. Prohibit equivalent register removal on RST_R to prevent
// "sharing" with other local reset trees (caution: make sure global fanout
// limit is set to large enough value, otherwise SLICES may be used for
// fanout control on RST_R.
always @(posedge clk) begin
rst_r <= rst;
rst_r1 <= rst_r;
end
//*****************************************************************
// interpret commands from Command/Address FIFO
//*****************************************************************
assign wr_flag = (af_valid_r2) ? ((af_cmd_r2 == 3'b000) ? 1'b1 : 1'b0): 1'b0;
assign rd_flag = (af_valid_r2) ? ((af_cmd_r2 == 3'b001) ? 1'b1 : 1'b0): 1'b0;
always @(posedge clk) begin
rd_flag_r <= rd_flag;
wr_flag_r <= wr_flag;
end
//////////////////////////////////////////////////
// The data from the address FIFO is fetched and
// stored in two register stages. The data will be
// pulled out of the second register stage whenever
// the state machine can handle new data from the
// address FIFO.
// This flag is asserted when there is no
// cmd & address in the pipe. When there is
// valid cmd & addr from the address FIFO the
// af_valid signals will be asserted. This flag will
// be set the cycle af_valid_r is de-asserted.
always @(posedge clk) begin
// for simulation purposes - to force CTRL_AF_RDEN low during reset
if (rst_r1)
rd_af_flag_r <= 1'd0;
else if (rd_af_flag_r) // jb - probably should find a way
// to stop this toggling all the time
rd_af_flag_r <= 0; // jb
else if((ctrl_af_rden_r) ||
(/*rd_af_flag_r &&*/ (af_valid_r || af_valid_r1)))
// Fixed bug where third addresses would get lost (pulled off fifo and
// then clobbered by other value later, thus ignored/skipped) - just
// make sure we don't get too excited and pull too many off at once - jb
rd_af_flag_r <= 1'd0;
else if (~af_valid_r1 || ~af_valid_r)
rd_af_flag_r <= 1'd1;
end // always @ (posedge clk)
// First register stage for the cmd & add from the FIFO.
// The af_valid_r signal gives the status of the data
// in this stage. The af_valid_r will be asserted when there
// is valid data. This register stage will be updated
// 1. read to the FIFO and the FIFO not empty
// 2. After write and read states
// 3. The valid signal is not asserted in the last stage.
always @(posedge clk) begin
if (rst_r1)begin
af_valid_r <= 1'd0;
end else begin
if (ctrl_af_rden_r || sm_rden_r || ~af_valid_r1
|| ~af_valid_r2)begin
af_valid_r <= ctrl_af_rden_r;
end
end
end
// The output register in the FIFO is used. The addr
// and command are already registered in the FIFO.
assign af_addr_r = af_addr;
assign af_cmd_r = af_cmd;
// Second register stage for the cmd & add from the FIFO.
// The af_valid_r1 signal gives the status of the data
// in this stage. The af_valid_r will be asserted when there
// is valid data. This register stage will be updated
// 1. read to the FIFO and the FIFO not empty and there
// is no valid data on this stage
// 2. After write and read states
// 3. The valid signal is not asserted in the last stage.
always@(posedge clk) begin
if (rst_r1)begin
af_valid_r1 <= 1'd0;
af_addr_r1 <= {31{1'bx}};
af_cmd_r1 <= {3{1'bx}};
end else if (~af_valid_r1 || sm_rden_r ||
~af_valid_r2) begin
af_valid_r1 <= af_valid_r;
af_addr_r1 <= af_addr_r;
af_cmd_r1 <= af_cmd_r;
end
end
// The state machine uses the address and command in this
// register stage. The data is fetched from the second
// register stage whenever the state machine can accept new
// addr. The conflict flags are also generated based on the
// second register stage and updated when the new address
// is loaded for the state machine.
always@(posedge clk) begin
if (rst_r1)begin
af_valid_r2 <= 1'd0;
af_addr_r2 <= {31{1'bx}};
af_cmd_r2 <= {3{1'bx}};
bank_hit_r <= {OPEN_BANK_NUM{1'bx}};
bank_conflict_r <= 1'bx;
row_conflict_r <= 4'bx;
end else if(sm_rden || ~af_valid_r2)begin
af_valid_r2 <= af_valid_r1;
af_addr_r2 <= af_addr_r1;
af_cmd_r2 <= af_cmd_r1;
if(MULTI_BANK_EN)begin
bank_hit_r <= bank_hit;
row_conflict_r <= row_miss;
bank_conflict_r <= (~(|bank_hit));
end else begin
bank_hit_r <= {OPEN_BANK_NUM{1'b0}};
bank_conflict_r <= 1'd0;
row_conflict_r[0] <= (af_addr_r1[CS_RANGE_END:ROW_RANGE_START]
!= sb_open_add_r[CMP_WIDTH-1:0]);
end
end
end // always@ (posedge clk)
//detecting cs change for multi chip select case
generate
if(CS_NUM > 1) begin: gen_cs_change
always @(posedge clk) begin
if(sm_rden || ~af_valid_r2)begin
cs_change_r <= af_addr_r1[CS_RANGE_END:CS_RANGE_START] !=
af_addr_r2[CS_RANGE_END:CS_RANGE_START] ;
cs_change_sticky_r <=
af_addr_r1[CS_RANGE_END:CS_RANGE_START] !=
af_addr_r2[CS_RANGE_END:CS_RANGE_START] ;
end else
cs_change_r <= 1'd0;
end
end // block: gen_cs_change
else begin: gen_cs_0
always @(posedge clk) begin
cs_change_r <= 1'd0;
cs_change_sticky_r <= 1'd0;
end
end
endgenerate
assign conflict_detect = (MULTI_BANK_EN) ?
((|(row_conflict_r[3:0] & bank_hit_r[3:0]))
| bank_conflict_r) & af_valid_r2 :
row_conflict_r[0] & af_valid_r2;
always @(posedge clk) begin
conflict_detect_r <= conflict_detect;
sm_rden_r <= sm_rden;
af_addr_r3 <= af_addr_r2;
ctrl_af_rden_r <= ctrl_af_rden & ~af_empty;
end
// conflict resolved signal. When this signal is asserted
// the conflict is resolved. The address to be compared
// for the conflict_resolved_r will be stored in act_add_r
// when the bank is opened.
always @(posedge clk) begin
conflict_resolved_r <= (act_addr_r ==
af_addr_r2[CS_RANGE_END:ROW_RANGE_START]);
if((state_r == CTRL_ACTIVE))
act_addr_r <= af_addr_r2[CS_RANGE_END:ROW_RANGE_START];
end
//***************************************************************************
// Bank management logic
// Semi-hardcoded for now for 4 banks
// will keep multiple banks open if MULTI_BANK_EN is true.
//***************************************************************************
genvar bank_i;
generate // if multiple bank option chosen
if(MULTI_BANK_EN) begin: gen_multi_bank_open
for (bank_i = 0; bank_i < OPEN_BANK_NUM;
bank_i = bank_i + 1) begin: gen_bank_hit1
// asserted if bank address match + open bank entry is valid
always @(*) begin
bank_hit[bank_i]
= ((bank_cmp_addr_r[(CMP_WIDTH*(bank_i+1))-1:
(CMP_WIDTH*bank_i)+ROW_WIDTH] ==
af_addr_r1[CS_RANGE_END:BANK_RANGE_START]) &&
bank_valid_r[bank_i]);
// asserted if row address match (no check for bank entry valid, rely
// on this term to be used in conjunction with BANK_HIT[])
row_miss[bank_i]
= (bank_cmp_addr_r[(CMP_WIDTH*bank_i)+ROW_WIDTH-1:
(CMP_WIDTH*bank_i)] !=
af_addr_r1[ROW_RANGE_END:ROW_RANGE_START]);
end
end
always @(posedge clk) begin
no_precharge_wait_r <= bank_valid_r[3] & bank_conflict_r;
bank_hit_r1 <= bank_hit_r;
end
always@(*)
no_precharge_r = ~bank_valid_r[3] & bank_conflict_r;
always@(posedge clk)
no_precharge_r1 <= no_precharge_r;
always @(posedge clk) begin
// Clear all bank valid bits during AR (i.e. since all banks get
// precharged during auto-refresh)
if ((state_r1 == CTRL_AUTO_REFRESH)) begin
bank_valid_r <= {OPEN_BANK_NUM{1'b0}};
bank_cmp_addr_r <= {(OPEN_BANK_NUM*CMP_WIDTH-1){1'b0}};
end else begin
if (state_r1 == CTRL_ACTIVE) begin
// 00 is always going to have the latest bank and row.
bank_cmp_addr_r[CMP_WIDTH-1:0]
<= af_addr_r3[CS_RANGE_END:ROW_RANGE_START];
// This indicates the bank was activated
bank_valid_r[0] <= 1'b1;
case ({bank_hit_r1[2:0]})
3'b001: begin
bank_cmp_addr_r[CMP_WIDTH-1:0]
<= af_addr_r3[CS_RANGE_END:ROW_RANGE_START];
// This indicates the bank was activated
bank_valid_r[0] <= 1'b1;
end
3'b010: begin //(b0->b1)
bank_cmp_addr_r[(2*CMP_WIDTH)-1:CMP_WIDTH]
<= bank_cmp_addr_r[CMP_WIDTH-1:0];
bank_valid_r[1] <= bank_valid_r[0];
end
3'b100:begin //(b0->b1, b1->b2)
bank_cmp_addr_r[(2*CMP_WIDTH)-1:CMP_WIDTH]
<= bank_cmp_addr_r[CMP_WIDTH-1:0];
bank_cmp_addr_r[(3*CMP_WIDTH)-1:2*CMP_WIDTH]
<= bank_cmp_addr_r[(2*CMP_WIDTH)-1:CMP_WIDTH];
bank_valid_r[1] <= bank_valid_r[0];
bank_valid_r[2] <= bank_valid_r[1];
end
default: begin //(b0->b1, b1->b2, b2->b3)
bank_cmp_addr_r[(2*CMP_WIDTH)-1:CMP_WIDTH]
<= bank_cmp_addr_r[CMP_WIDTH-1:0];
bank_cmp_addr_r[(3*CMP_WIDTH)-1:2*CMP_WIDTH]
<= bank_cmp_addr_r[(2*CMP_WIDTH)-1:CMP_WIDTH];
bank_cmp_addr_r[(4*CMP_WIDTH)-1:3*CMP_WIDTH]
<= bank_cmp_addr_r[(3*CMP_WIDTH)-1:2*CMP_WIDTH];
bank_valid_r[1] <= bank_valid_r[0];
bank_valid_r[2] <= bank_valid_r[1];
bank_valid_r[3] <= bank_valid_r[2];
end
endcase
end
end
end
end else begin: gen_single_bank_open // single bank option
always @(posedge clk) begin
no_precharge_r <= 1'd0;
no_precharge_r1 <= 1'd0;
no_precharge_wait_r <= 1'd0;
if (rst_r1)
sb_open_add_r <= {CMP_WIDTH{1'b0}};
else if (state_r == CTRL_ACTIVE)
sb_open_add_r <= af_addr_r2[CS_RANGE_END:ROW_RANGE_START];
end
end
endgenerate
//***************************************************************************
// Timing counters
//***************************************************************************
//*****************************************************************
// Write and read enable generation for PHY
//*****************************************************************
// write burst count. Counts from (BL/2 to 1).
// Also logic for controller write enable.
always @(posedge clk) begin
if (state_r == CTRL_BURST_WRITE) begin
wrburst_cnt_r <= BURST_LEN_DIV2;
end else if (wrburst_cnt_r >= 3'd1)
wrburst_cnt_r <= wrburst_cnt_r - 1;
end // always @ (posedge clk)
always @(posedge clk) begin
if (rst_r1) begin
ctrl_wren <= 1'b0;
end else if (state_r == CTRL_BURST_WRITE) begin
ctrl_wren <= 1'b1;
end else if (wrburst_wren_ok_r)
ctrl_wren <= 1'b0;
end
always @(posedge clk) begin
if ((state_r == CTRL_BURST_WRITE)
&& (BURST_LEN_DIV2 > 2))
wrburst_ok_r <= 1'd0;
else if ((wrburst_cnt_r <= 3'd3) ||
(BURST_LEN_DIV2 <= 2))
wrburst_ok_r <= 1'b1;
end
// flag to check when wrburst count has reached
// a value of 1. This flag is used in the ctrl_wren
// logic
always @(posedge clk) begin
if(wrburst_cnt_r == 3'd2)
wrburst_wren_ok_r <=1'b1;
else
wrburst_wren_ok_r <= 1'b0;
end
// read burst count. Counts from (BL/2 to 1)
always @(posedge clk) begin
if (state_r == CTRL_BURST_READ) begin
rdburst_cnt_r <= BURST_LEN_DIV2;
end else if (rdburst_cnt_r >= 3'd1)
rdburst_cnt_r <= rdburst_cnt_r - 1;
end // always @ (posedge clk)
always @(posedge clk) begin
if (rst_r1) begin
ctrl_rden <= 1'b0;
end else if (state_r == CTRL_BURST_READ) begin
ctrl_rden <= 1'b1;
end else if (rdburst_rden_ok_r)
ctrl_rden <= 1'b0;
end
// the rd_burst_ok_r signal will be asserted one cycle later
// in multi chip select cases if the back to back read is to
// different chip selects. The cs_changed_sticky_r signal will
// be asserted only for multi chip select cases.
always @(posedge clk) begin
if ((state_r == CTRL_BURST_READ)
&& (BURST_LEN_DIV2 > 2))
rdburst_ok_r <= 1'd0;
else if ((rdburst_cnt_r <=( 3'd3 - cs_change_sticky_r)) ||
(BURST_LEN_DIV2 <= 2))
rdburst_ok_r <= 1'b1;
end
// flag to check when rdburst count has reached
// a value of 1. This flag is used in the ctrl_rden
// logic
always @(posedge clk) begin
if (rdburst_cnt_r == 3'd2)
rdburst_rden_ok_r <= 1'b1;
else
rdburst_rden_ok_r <= 1'b0;
end
//*****************************************************************
// Various delay counters
// The counters are checked for value of <= 3 to determine the
// if the count values are reached during different commands.
// It is checked for 3 because
// 1. The counters are loaded during the state when the command
// state is reached (+1)
// 2. After the <= 3 condition is reached the sm takes two cycles
// to transition to the new command state (+2)
//*****************************************************************
// tRP count - precharge command period
always @(posedge clk) begin
if (state_r == CTRL_PRECHARGE)
rp_cnt_r <= TRP_COUNT;
else if (rp_cnt_r != 4'd0)
rp_cnt_r <= rp_cnt_r - 1;
end
always @(posedge clk) begin
if (state_r == CTRL_PRECHARGE)
rp_cnt_ok_r <= 1'd0;
else if (rp_cnt_r <= 4'd3)
rp_cnt_ok_r <= 1'd1;
end
// tRFC count - refresh-refresh, refresh-active
always @(posedge clk) begin
if (state_r == CTRL_AUTO_REFRESH)
rfc_cnt_r <= TRFC_COUNT;
else if (rfc_cnt_r != 8'd0)
rfc_cnt_r <= rfc_cnt_r - 1;
end
always @(posedge clk) begin
if (state_r == CTRL_AUTO_REFRESH)
rfc_ok_r <= 1'b0;
else if(rfc_cnt_r <= 8'd3)
rfc_ok_r <= 1'b1;
end
// tRCD count - active to read/write
always @(posedge clk) begin
if (state_r == CTRL_ACTIVE)
rcd_cnt_r <= TRCD_COUNT;
else if (rcd_cnt_r != 4'd0)
rcd_cnt_r <= rcd_cnt_r - 1;
end
always @(posedge clk) begin
if ((state_r == CTRL_ACTIVE)
&& (TRCD_COUNT > 2))
rcd_cnt_ok_r <= 1'd0;
else if (rcd_cnt_r <= 4'd3)
rcd_cnt_ok_r <= 1;
end
// tRRD count - active to active
always @(posedge clk) begin
if (state_r == CTRL_ACTIVE)
trrd_cnt_r <= TRRD_COUNT;
else if (trrd_cnt_r != 3'd0)
trrd_cnt_r <= trrd_cnt_r - 1;
end
always @(posedge clk) begin
if (state_r == CTRL_ACTIVE)
trrd_cnt_ok_r <= 1'd0;
else if (trrd_cnt_r <= 3'd3)
trrd_cnt_ok_r <= 1;
end
// tRAS count - active to precharge
always @(posedge clk) begin
if (state_r == CTRL_ACTIVE)
ras_cnt_r <= TRAS_COUNT;
else if (ras_cnt_r != 5'd0)
ras_cnt_r <= ras_cnt_r - 1;
end
// counter for write to prcharge
// read to precharge and
// activate to precharge
// precharge_ok_cnt_r is added with trtp count,
// there can be cases where the sm can go from
// activate to read and the act->pre count time
// would not have been satisfied. The rd->pre
// time is very less. wr->pre time is almost the
// same as act-> pre
always @(posedge clk) begin
if (state_r == CTRL_BURST_READ) begin
// assign only if the cnt is < TRTP_COUNT
if (precharge_ok_cnt_r < TRTP_COUNT)
precharge_ok_cnt_r <= TRTP_COUNT;
end else if (state_r == CTRL_BURST_WRITE)
precharge_ok_cnt_r <= TWR_COUNT;
else if (state_r == CTRL_ACTIVE)
precharge_ok_cnt_r <= TRAS_COUNT;
else if (precharge_ok_cnt_r != 5'd0)
precharge_ok_cnt_r <= precharge_ok_cnt_r - 1;
end
always @(posedge clk) begin
if ((state_r == CTRL_BURST_READ) ||
(state_r == CTRL_BURST_WRITE)||
(state_r == CTRL_ACTIVE))
precharge_ok_r <= 1'd0;
else if(precharge_ok_cnt_r <= 5'd3)
precharge_ok_r <=1'd1;
end
// write to read counter
// write to read includes : write latency + burst time + tWTR
always @(posedge clk) begin
if (rst_r1)
wr_to_rd_cnt_r <= 5'd0;
else if (state_r == CTRL_BURST_WRITE)
wr_to_rd_cnt_r <= (TWTR_COUNT);
else if (wr_to_rd_cnt_r != 5'd0)
wr_to_rd_cnt_r <= wr_to_rd_cnt_r - 1;
end
always @(posedge clk) begin
if (state_r == CTRL_BURST_WRITE)
wr_to_rd_ok_r <= 1'd0;
else if (wr_to_rd_cnt_r <= 5'd3)
wr_to_rd_ok_r <= 1'd1;
end
// read to write counter
always @(posedge clk) begin
if (rst_r1)
rd_to_wr_cnt_r <= 5'd0;
else if (state_r == CTRL_BURST_READ)
rd_to_wr_cnt_r <= (TRTW_COUNT);
else if (rd_to_wr_cnt_r != 5'd0)
rd_to_wr_cnt_r <= rd_to_wr_cnt_r - 1;
end
always @(posedge clk) begin
if (state_r == CTRL_BURST_READ)
rd_to_wr_ok_r <= 1'b0;
else if (rd_to_wr_cnt_r <= 5'd3)
rd_to_wr_ok_r <= 1'b1;
end
always @(posedge clk) begin
if(refi_cnt_r == (TREFI_COUNT -1))
refi_cnt_ok_r <= 1'b1;
else
refi_cnt_ok_r <= 1'b0;
end
// auto refresh interval counter in refresh_clk domain
always @(posedge clk) begin
if(rst_r1)
refi_cnt_r <= 12'd0;
else if(sp_refresh_disable)
refi_cnt_r <= 12'd123;
else if(refi_cnt_ok_r)
refi_cnt_r <= 12'd0;
else
refi_cnt_r <= refi_cnt_r + 1;
end // always @ (posedge clk)
// auto refresh flag
always @(posedge clk) begin
if (refi_cnt_ok_r) begin
ref_flag_r <= 1'b1;
end else begin
ref_flag_r <= 1'b0;
end
end // always @ (posedge clk)
assign ctrl_ref_flag = ref_flag_r;
//refresh flag detect
//auto_ref high indicates auto_refresh requirement
//auto_ref is held high until auto refresh command is issued.
always @(posedge clk)begin
if (rst_r1)
auto_ref_r <= 1'b0;
else if (ref_flag_r)
auto_ref_r <= 1'b1;
else if (state_r == CTRL_AUTO_REFRESH)
auto_ref_r <= 1'b0;
end
// keep track of which chip selects got auto-refreshed (avoid auto-refreshing
// all CS's at once to avoid current spike)
always @(posedge clk)begin
if (rst_r1 || (state_r1 == CTRL_PRECHARGE))
auto_cnt_r <= 'd0;
else if (state_r1 == CTRL_AUTO_REFRESH)
auto_cnt_r <= auto_cnt_r + 1;
end
// register for timing purposes. Extra delay doesn't really matter
always @(posedge clk)
phy_init_done_r <= phy_init_done;
always @(posedge clk)begin
if (rst_r1) begin
state_r <= CTRL_IDLE;
state_r1 <= CTRL_IDLE;
end else begin
state_r <= next_state;
state_r1 <= state_r;
end
end
//***************************************************************************
// main control state machine
//***************************************************************************
always @(*) begin
next_state = state_r;
(* full_case, parallel_case *) case (state_r)
CTRL_IDLE: begin
// perform auto refresh as soon as we are done with calibration.
// The calibration logic does not do any refreshes.
if (phy_init_done_r)
next_state = CTRL_AUTO_REFRESH;
end
CTRL_PRECHARGE: begin
if (auto_ref_r)
next_state = CTRL_PRECHARGE_WAIT1;
// when precharging an LRU bank, do not have to go to wait state
// since we can't possibly be activating row in same bank next
// disabled for 2t timing. There needs to be a gap between cmds
// in 2t timing
else if (no_precharge_wait_r && !TWO_T_TIME_EN)
next_state = CTRL_ACTIVE;
else
next_state = CTRL_PRECHARGE_WAIT;
end
CTRL_PRECHARGE_WAIT:begin
if (rp_cnt_ok_r)begin
if (auto_ref_r)
// precharge again to make sure we close all the banks
next_state = CTRL_PRECHARGE;
else
next_state = CTRL_ACTIVE;
end
end
CTRL_PRECHARGE_WAIT1:
if (rp_cnt_ok_r)
next_state = CTRL_AUTO_REFRESH;
CTRL_AUTO_REFRESH:
next_state = CTRL_AUTO_REFRESH_WAIT;
CTRL_AUTO_REFRESH_WAIT:
//staggering Auto refresh for multi
// chip select designs. The SM waits
// for the rfc time before issuing the
// next auto refresh.
if (auto_cnt_r < (CS_NUM))begin
if (rfc_ok_r )
next_state = CTRL_AUTO_REFRESH;
end else if (rfc_ok_r)begin
if(auto_ref_r)
// MIG 2.3: For deep designs if Auto Refresh
// flag asserted immediately after calibration is completed
next_state = CTRL_PRECHARGE;
else if ( wr_flag || rd_flag)
next_state = CTRL_ACTIVE;
end
CTRL_ACTIVE:
next_state = CTRL_ACTIVE_WAIT;
CTRL_ACTIVE_WAIT: begin
if (rcd_cnt_ok_r) begin
if ((conflict_detect_r && ~conflict_resolved_r) ||
auto_ref_r) begin
if (no_precharge_r1 && ~auto_ref_r && trrd_cnt_ok_r)
next_state = CTRL_ACTIVE;
else if(precharge_ok_r)
next_state = CTRL_PRECHARGE;
end else if ((wr_flag_r) && (rd_to_wr_ok_r))
next_state = CTRL_BURST_WRITE;
else if ((rd_flag_r)&& (wr_to_rd_ok_r))
next_state = CTRL_BURST_READ;
end
end
// beginning of write burst
CTRL_BURST_WRITE: begin
if (BURST_LEN_DIV2 == 1) begin
// special case if BL = 2 (i.e. burst lasts only one clk cycle)
if (wr_flag)
// if we have another non-conflict write command right after the
// current write, then stay in this state
next_state = CTRL_BURST_WRITE;
else
// otherwise, if we're done with this burst, and have no write
// immediately scheduled after this one, wait until write-read
// delay has passed
next_state = CTRL_WRITE_WAIT;
end else
// otherwise BL > 2, and we have at least one more write cycle for
// current burst
next_state = CTRL_WRITE_WAIT;
// continuation of write burst (also covers waiting after write burst
// has completed for write-read delay to pass)
end
CTRL_WRITE_WAIT: begin
if ((conflict_detect) || auto_ref_r) begin
if (no_precharge_r && ~auto_ref_r && wrburst_ok_r)
next_state = CTRL_ACTIVE;
else if (precharge_ok_r)
next_state = CTRL_PRECHARGE;
end else if (wrburst_ok_r && wr_flag)
next_state = CTRL_BURST_WRITE;
else if ((rd_flag) && (wr_to_rd_ok_r))
next_state = CTRL_BURST_READ;
end
CTRL_BURST_READ: begin
if (BURST_LEN_DIV2 == 1) begin
// special case if BL = 2 (i.e. burst lasts only one clk cycle)
if (rd_flag)
next_state = CTRL_BURST_READ;
else
next_state = CTRL_READ_WAIT;
end else
next_state = CTRL_READ_WAIT;
end
CTRL_READ_WAIT: begin
if ((conflict_detect) || auto_ref_r)begin
if (no_precharge_r && ~auto_ref_r && rdburst_ok_r)
next_state = CTRL_ACTIVE;
else if (precharge_ok_r)
next_state = CTRL_PRECHARGE;
// for burst of 4 in multi chip select
// if there is a change in cs wait one cycle before the
// next read command. cs_change_r will be asserted.
end else if (rdburst_ok_r && rd_flag && ~cs_change_r)
next_state = CTRL_BURST_READ;
else if (wr_flag && (rd_to_wr_ok_r))
next_state = CTRL_BURST_WRITE;
end
endcase
end
//***************************************************************************
// control signals to memory
//***************************************************************************
always @(posedge clk) begin
if ((state_r == CTRL_AUTO_REFRESH) ||
(state_r == CTRL_ACTIVE) ||
(state_r == CTRL_PRECHARGE)) begin
ddr_ras_n_r <= 1'b0;
two_t_enable_r[0] <= 1'b0;
end else begin
if (TWO_T_TIME_EN)
ddr_ras_n_r <= two_t_enable_r[0] ;
else
ddr_ras_n_r <= 1'd1;
two_t_enable_r[0] <= 1'b1;
end
end
always @(posedge clk)begin
if ((state_r == CTRL_BURST_WRITE) ||
(state_r == CTRL_BURST_READ) ||
(state_r == CTRL_AUTO_REFRESH)) begin
ddr_cas_n_r <= 1'b0;
two_t_enable_r[1] <= 1'b0;
end else begin
if (TWO_T_TIME_EN)
ddr_cas_n_r <= two_t_enable_r[1];
else
ddr_cas_n_r <= 1'b1;
two_t_enable_r[1] <= 1'b1;
end
end
always @(posedge clk) begin
if ((state_r == CTRL_BURST_WRITE) ||
(state_r == CTRL_PRECHARGE)) begin
ddr_we_n_r <= 1'b0;
two_t_enable_r[2] <= 1'b0;
end else begin
if(TWO_T_TIME_EN)
ddr_we_n_r <= two_t_enable_r[2];
else
ddr_we_n_r <= 1'b1;
two_t_enable_r[2] <= 1'b1;
end
end
// turn off auto-precharge when issuing commands (A10 = 0)
// mapping the col add for linear addressing.
generate
if (TWO_T_TIME_EN) begin: gen_addr_col_two_t
if (COL_WIDTH == ROW_WIDTH-1) begin: gen_ddr_addr_col_0
assign ddr_addr_col = {af_addr_r3[COL_WIDTH-1:10], 1'b0,
af_addr_r3[9:0]};
end else begin
if (COL_WIDTH > 10) begin: gen_ddr_addr_col_1
assign ddr_addr_col = {{(ROW_WIDTH-COL_WIDTH-1){1'b0}},
af_addr_r3[COL_WIDTH-1:10], 1'b0,
af_addr_r3[9:0]};
end else begin: gen_ddr_addr_col_2
assign ddr_addr_col = {{(ROW_WIDTH-COL_WIDTH-1){1'b0}}, 1'b0,
af_addr_r3[COL_WIDTH-1:0]};
end
end
end else begin: gen_addr_col_one_t
if (COL_WIDTH == ROW_WIDTH-1) begin: gen_ddr_addr_col_0_1
assign ddr_addr_col = {af_addr_r2[COL_WIDTH-1:10], 1'b0,
af_addr_r2[9:0]};
end else begin
if (COL_WIDTH > 10) begin: gen_ddr_addr_col_1_1
assign ddr_addr_col = {{(ROW_WIDTH-COL_WIDTH-1){1'b0}},
af_addr_r2[COL_WIDTH-1:10], 1'b0,
af_addr_r2[9:0]};
end else begin: gen_ddr_addr_col_2_1
assign ddr_addr_col = {{(ROW_WIDTH-COL_WIDTH-1){1'b0}}, 1'b0,
af_addr_r2[COL_WIDTH-1:0]};
end
end
end
endgenerate
// Assign address during row activate
generate
if (TWO_T_TIME_EN)
assign ddr_addr_row = af_addr_r3[ROW_RANGE_END:ROW_RANGE_START];
else
assign ddr_addr_row = af_addr_r2[ROW_RANGE_END:ROW_RANGE_START];
endgenerate
always @(posedge clk)begin
if ((state_r == CTRL_ACTIVE) ||
((state_r1 == CTRL_ACTIVE) && TWO_T_TIME_EN))
ddr_addr_r <= ddr_addr_row;
else if ((state_r == CTRL_BURST_WRITE) ||
(state_r == CTRL_BURST_READ) ||
(((state_r1 == CTRL_BURST_WRITE) ||
(state_r1 == CTRL_BURST_READ)) &&
TWO_T_TIME_EN))
ddr_addr_r <= ddr_addr_col;
else if (((state_r == CTRL_PRECHARGE) ||
((state_r1 == CTRL_PRECHARGE) && TWO_T_TIME_EN))
&& auto_ref_r) begin
// if we're precharging as a result of AUTO-REFRESH, precharge all banks
ddr_addr_r <= {ROW_WIDTH{1'b0}};
ddr_addr_r[10] <= 1'b1;
end else if ((state_r == CTRL_PRECHARGE) ||
((state_r1 == CTRL_PRECHARGE) && TWO_T_TIME_EN))
// if we're precharging to close a specific bank/row, set A10=0
ddr_addr_r <= {ROW_WIDTH{1'b0}};
else
ddr_addr_r <= {ROW_WIDTH{1'bx}};
end
always @(posedge clk)begin
// whenever we're precharging, we're either: (1) precharging all banks (in
// which case banks bits are don't care, (2) precharging the LRU bank,
// b/c we've exceeded the limit of # of banks open (need to close the LRU
// bank to make room for a new one), (3) we haven't exceed the maximum #
// of banks open, but we trying to open a different row in a bank that's
// already open
if (((state_r == CTRL_PRECHARGE) ||
((state_r1 == CTRL_PRECHARGE) && TWO_T_TIME_EN)) &&
bank_conflict_r && MULTI_BANK_EN)
// When LRU bank needs to be closed
ddr_ba_r <= bank_cmp_addr_r[(3*CMP_WIDTH)+CMP_BANK_RANGE_END:
(3*CMP_WIDTH)+CMP_BANK_RANGE_START];
else begin
// Either precharge due to refresh or bank hit case
if (TWO_T_TIME_EN)
ddr_ba_r <= af_addr_r3[BANK_RANGE_END:BANK_RANGE_START];
else
ddr_ba_r <= af_addr_r2[BANK_RANGE_END:BANK_RANGE_START];
end
end
// chip enable generation logic
generate
// if only one chip select, always assert it after reset
if (CS_BITS == 0) begin: gen_ddr_cs_0
always @(posedge clk)
if (rst_r1)
ddr_cs_n_r[0] <= 1'b1;
else
ddr_cs_n_r[0] <= 1'b0;
// otherwise if we have multiple chip selects
end else begin: gen_ddr_cs_1
if(TWO_T_TIME_EN) begin: gen_2t_cs
always @(posedge clk)
if (rst_r1)
ddr_cs_n_r <= {CS_NUM{1'b1}};
else if ((state_r1 == CTRL_AUTO_REFRESH)) begin
// if auto-refreshing, only auto-refresh one CS at any time (avoid
// beating on the ground plane by refreshing all CS's at same time)
ddr_cs_n_r <= {CS_NUM{1'b1}};
ddr_cs_n_r[auto_cnt_r] <= 1'b0;
end else if (auto_ref_r && (state_r1 == CTRL_PRECHARGE)) begin
ddr_cs_n_r <= {CS_NUM{1'b0}};
end else if ((state_r1 == CTRL_PRECHARGE) && ( bank_conflict_r
&& MULTI_BANK_EN))begin
// precharging the LRU bank
ddr_cs_n_r <= {CS_NUM{1'b1}};
ddr_cs_n_r[bank_cmp_addr_r[(3*CMP_WIDTH)+CMP_CS_RANGE_END:
(3*CMP_WIDTH)+CMP_CS_RANGE_START]] <= 1'b0;
end else begin
// otherwise, check the upper address bits to see which CS to assert
ddr_cs_n_r <= {CS_NUM{1'b1}};
ddr_cs_n_r[af_addr_r3[CS_RANGE_END:CS_RANGE_START]] <= 1'b0;
end // else: !if(((state_r == CTRL_PRECHARGE) ||...
end else begin: gen_1t_cs // block: gen_2t_cs
always @(posedge clk)
if (rst_r1)
ddr_cs_n_r <= {CS_NUM{1'b1}};
else if ((state_r == CTRL_AUTO_REFRESH) ) begin
// if auto-refreshing, only auto-refresh one CS at any time (avoid
// beating on the ground plane by refreshing all CS's at same time)
ddr_cs_n_r <= {CS_NUM{1'b1}};
ddr_cs_n_r[auto_cnt_r] <= 1'b0;
end else if (auto_ref_r && (state_r == CTRL_PRECHARGE) ) begin
ddr_cs_n_r <= {CS_NUM{1'b0}};
end else if ((state_r == CTRL_PRECHARGE) &&
(bank_conflict_r && MULTI_BANK_EN))begin
// precharging the LRU bank
ddr_cs_n_r <= {CS_NUM{1'b1}};
ddr_cs_n_r[bank_cmp_addr_r[(3*CMP_WIDTH)+CMP_CS_RANGE_END:
(3*CMP_WIDTH)+CMP_CS_RANGE_START]] <= 1'b0;
end else begin
// otherwise, check the upper address bits to see which CS to assert
ddr_cs_n_r <= {CS_NUM{1'b1}};
ddr_cs_n_r[af_addr_r2[CS_RANGE_END:CS_RANGE_START]] <= 1'b0;
end // else: !if(((state_r == CTRL_PRECHARGE) ||...
end // block: gen_1t_cs
end
endgenerate
// registring the two_t timing enable signal.
// This signal will be asserted (low) when the
// chip select has to be asserted.
always @(posedge clk)begin
if(&two_t_enable_r)
two_t_enable_r1 <= {CS_NUM{1'b1}};
else
two_t_enable_r1 <= {CS_NUM{1'b0}};
end
assign ctrl_addr = ddr_addr_r;
assign ctrl_ba = ddr_ba_r;
assign ctrl_ras_n = ddr_ras_n_r;
assign ctrl_cas_n = ddr_cas_n_r;
assign ctrl_we_n = ddr_we_n_r;
assign ctrl_cs_n = (TWO_T_TIME_EN) ?
(ddr_cs_n_r | two_t_enable_r1) :
ddr_cs_n_r;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: ccnu
// Engineer: Poyi Xiong
//
// Create Date: 01/12/2017 12:00:21 PM
// Design Name:
// Module Name: Clock_SR_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Clock_SR_tb #(parameter WIDTH=170, CNT_WIDTH=8)();
reg clk;
reg rst;
reg start;
reg [CNT_WIDTH-1:0] count;
wire clk_sr;
Clock_SR #(.WIDTH(WIDTH), .CNT_WIDTH(CNT_WIDTH))
DUT1(
.clk(clk),
.rst(rst),
.start(start),
.count(count),
.clk_sr(clk_sr)
);
initial begin
$dumpfile("Clock_SR.dump");
$dumpvars(0, Clock_SR);
end
initial begin
clk=0;
forever #50 clk=~clk;
end
initial begin
rst=1'b1;
#200 rst=1'b0;
end
initial begin
count=8'b0;
#50 count=8'b0;
forever #100 count=count+1'b1;
end
initial begin
start=1'b0;
#250 start=1'b1;
#100 start=1'b0;
#17600 start=1'b1;
#100 start=1'b0;
end
endmodule
|
// system_acl_iface_acl_kernel_interface_mm_interconnect_1.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.0 200 at 2015.04.18.10:44:33
`timescale 1 ps / 1 ps
module system_acl_iface_acl_kernel_interface_mm_interconnect_1 (
input wire clk_reset_clk_clk, // clk_reset_clk.clk
input wire kernel_clk_out_clk_clk, // kernel_clk_out_clk.clk
input wire address_span_extender_0_reset_reset_bridge_in_reset_reset, // address_span_extender_0_reset_reset_bridge_in_reset.reset
input wire kernel_cntrl_reset_reset_bridge_in_reset_reset, // kernel_cntrl_reset_reset_bridge_in_reset.reset
input wire sw_reset_clk_reset_reset_bridge_in_reset_reset, // sw_reset_clk_reset_reset_bridge_in_reset.reset
input wire [13:0] kernel_cntrl_m0_address, // kernel_cntrl_m0.address
output wire kernel_cntrl_m0_waitrequest, // .waitrequest
input wire [0:0] kernel_cntrl_m0_burstcount, // .burstcount
input wire [3:0] kernel_cntrl_m0_byteenable, // .byteenable
input wire kernel_cntrl_m0_read, // .read
output wire [31:0] kernel_cntrl_m0_readdata, // .readdata
output wire kernel_cntrl_m0_readdatavalid, // .readdatavalid
input wire kernel_cntrl_m0_write, // .write
input wire [31:0] kernel_cntrl_m0_writedata, // .writedata
input wire kernel_cntrl_m0_debugaccess, // .debugaccess
output wire address_span_extender_0_cntl_write, // address_span_extender_0_cntl.write
output wire address_span_extender_0_cntl_read, // .read
input wire [63:0] address_span_extender_0_cntl_readdata, // .readdata
output wire [63:0] address_span_extender_0_cntl_writedata, // .writedata
output wire [7:0] address_span_extender_0_cntl_byteenable, // .byteenable
output wire [9:0] address_span_extender_0_windowed_slave_address, // address_span_extender_0_windowed_slave.address
output wire address_span_extender_0_windowed_slave_write, // .write
output wire address_span_extender_0_windowed_slave_read, // .read
input wire [31:0] address_span_extender_0_windowed_slave_readdata, // .readdata
output wire [31:0] address_span_extender_0_windowed_slave_writedata, // .writedata
output wire [0:0] address_span_extender_0_windowed_slave_burstcount, // .burstcount
output wire [3:0] address_span_extender_0_windowed_slave_byteenable, // .byteenable
input wire address_span_extender_0_windowed_slave_readdatavalid, // .readdatavalid
input wire address_span_extender_0_windowed_slave_waitrequest, // .waitrequest
output wire irq_ena_0_s_write, // irq_ena_0_s.write
output wire irq_ena_0_s_read, // .read
input wire [31:0] irq_ena_0_s_readdata, // .readdata
output wire [31:0] irq_ena_0_s_writedata, // .writedata
output wire [3:0] irq_ena_0_s_byteenable, // .byteenable
input wire irq_ena_0_s_waitrequest, // .waitrequest
output wire mem_org_mode_s_write, // mem_org_mode_s.write
output wire mem_org_mode_s_read, // .read
input wire [31:0] mem_org_mode_s_readdata, // .readdata
output wire [31:0] mem_org_mode_s_writedata, // .writedata
input wire mem_org_mode_s_waitrequest, // .waitrequest
output wire sw_reset_s_write, // sw_reset_s.write
output wire sw_reset_s_read, // .read
input wire [63:0] sw_reset_s_readdata, // .readdata
output wire [63:0] sw_reset_s_writedata, // .writedata
output wire [7:0] sw_reset_s_byteenable, // .byteenable
input wire sw_reset_s_waitrequest, // .waitrequest
output wire [8:0] sys_description_rom_s1_address, // sys_description_rom_s1.address
output wire sys_description_rom_s1_write, // .write
input wire [63:0] sys_description_rom_s1_readdata, // .readdata
output wire [63:0] sys_description_rom_s1_writedata, // .writedata
output wire [7:0] sys_description_rom_s1_byteenable, // .byteenable
output wire sys_description_rom_s1_chipselect, // .chipselect
output wire sys_description_rom_s1_clken, // .clken
output wire sys_description_rom_s1_debugaccess, // .debugaccess
output wire version_id_0_s_read, // version_id_0_s.read
input wire [31:0] version_id_0_s_readdata // .readdata
);
wire kernel_cntrl_m0_translator_avalon_universal_master_0_waitrequest; // kernel_cntrl_m0_agent:av_waitrequest -> kernel_cntrl_m0_translator:uav_waitrequest
wire [2:0] kernel_cntrl_m0_translator_avalon_universal_master_0_burstcount; // kernel_cntrl_m0_translator:uav_burstcount -> kernel_cntrl_m0_agent:av_burstcount
wire [31:0] kernel_cntrl_m0_translator_avalon_universal_master_0_writedata; // kernel_cntrl_m0_translator:uav_writedata -> kernel_cntrl_m0_agent:av_writedata
wire [13:0] kernel_cntrl_m0_translator_avalon_universal_master_0_address; // kernel_cntrl_m0_translator:uav_address -> kernel_cntrl_m0_agent:av_address
wire kernel_cntrl_m0_translator_avalon_universal_master_0_lock; // kernel_cntrl_m0_translator:uav_lock -> kernel_cntrl_m0_agent:av_lock
wire kernel_cntrl_m0_translator_avalon_universal_master_0_write; // kernel_cntrl_m0_translator:uav_write -> kernel_cntrl_m0_agent:av_write
wire kernel_cntrl_m0_translator_avalon_universal_master_0_read; // kernel_cntrl_m0_translator:uav_read -> kernel_cntrl_m0_agent:av_read
wire [31:0] kernel_cntrl_m0_translator_avalon_universal_master_0_readdata; // kernel_cntrl_m0_agent:av_readdata -> kernel_cntrl_m0_translator:uav_readdata
wire kernel_cntrl_m0_translator_avalon_universal_master_0_debugaccess; // kernel_cntrl_m0_translator:uav_debugaccess -> kernel_cntrl_m0_agent:av_debugaccess
wire [3:0] kernel_cntrl_m0_translator_avalon_universal_master_0_byteenable; // kernel_cntrl_m0_translator:uav_byteenable -> kernel_cntrl_m0_agent:av_byteenable
wire kernel_cntrl_m0_translator_avalon_universal_master_0_readdatavalid; // kernel_cntrl_m0_agent:av_readdatavalid -> kernel_cntrl_m0_translator:uav_readdatavalid
wire address_span_extender_0_windowed_slave_agent_m0_waitrequest; // address_span_extender_0_windowed_slave_translator:uav_waitrequest -> address_span_extender_0_windowed_slave_agent:m0_waitrequest
wire [2:0] address_span_extender_0_windowed_slave_agent_m0_burstcount; // address_span_extender_0_windowed_slave_agent:m0_burstcount -> address_span_extender_0_windowed_slave_translator:uav_burstcount
wire [31:0] address_span_extender_0_windowed_slave_agent_m0_writedata; // address_span_extender_0_windowed_slave_agent:m0_writedata -> address_span_extender_0_windowed_slave_translator:uav_writedata
wire [13:0] address_span_extender_0_windowed_slave_agent_m0_address; // address_span_extender_0_windowed_slave_agent:m0_address -> address_span_extender_0_windowed_slave_translator:uav_address
wire address_span_extender_0_windowed_slave_agent_m0_write; // address_span_extender_0_windowed_slave_agent:m0_write -> address_span_extender_0_windowed_slave_translator:uav_write
wire address_span_extender_0_windowed_slave_agent_m0_lock; // address_span_extender_0_windowed_slave_agent:m0_lock -> address_span_extender_0_windowed_slave_translator:uav_lock
wire address_span_extender_0_windowed_slave_agent_m0_read; // address_span_extender_0_windowed_slave_agent:m0_read -> address_span_extender_0_windowed_slave_translator:uav_read
wire [31:0] address_span_extender_0_windowed_slave_agent_m0_readdata; // address_span_extender_0_windowed_slave_translator:uav_readdata -> address_span_extender_0_windowed_slave_agent:m0_readdata
wire address_span_extender_0_windowed_slave_agent_m0_readdatavalid; // address_span_extender_0_windowed_slave_translator:uav_readdatavalid -> address_span_extender_0_windowed_slave_agent:m0_readdatavalid
wire address_span_extender_0_windowed_slave_agent_m0_debugaccess; // address_span_extender_0_windowed_slave_agent:m0_debugaccess -> address_span_extender_0_windowed_slave_translator:uav_debugaccess
wire [3:0] address_span_extender_0_windowed_slave_agent_m0_byteenable; // address_span_extender_0_windowed_slave_agent:m0_byteenable -> address_span_extender_0_windowed_slave_translator:uav_byteenable
wire address_span_extender_0_windowed_slave_agent_rf_source_endofpacket; // address_span_extender_0_windowed_slave_agent:rf_source_endofpacket -> address_span_extender_0_windowed_slave_agent_rsp_fifo:in_endofpacket
wire address_span_extender_0_windowed_slave_agent_rf_source_valid; // address_span_extender_0_windowed_slave_agent:rf_source_valid -> address_span_extender_0_windowed_slave_agent_rsp_fifo:in_valid
wire address_span_extender_0_windowed_slave_agent_rf_source_startofpacket; // address_span_extender_0_windowed_slave_agent:rf_source_startofpacket -> address_span_extender_0_windowed_slave_agent_rsp_fifo:in_startofpacket
wire [89:0] address_span_extender_0_windowed_slave_agent_rf_source_data; // address_span_extender_0_windowed_slave_agent:rf_source_data -> address_span_extender_0_windowed_slave_agent_rsp_fifo:in_data
wire address_span_extender_0_windowed_slave_agent_rf_source_ready; // address_span_extender_0_windowed_slave_agent_rsp_fifo:in_ready -> address_span_extender_0_windowed_slave_agent:rf_source_ready
wire address_span_extender_0_windowed_slave_agent_rsp_fifo_out_endofpacket; // address_span_extender_0_windowed_slave_agent_rsp_fifo:out_endofpacket -> address_span_extender_0_windowed_slave_agent:rf_sink_endofpacket
wire address_span_extender_0_windowed_slave_agent_rsp_fifo_out_valid; // address_span_extender_0_windowed_slave_agent_rsp_fifo:out_valid -> address_span_extender_0_windowed_slave_agent:rf_sink_valid
wire address_span_extender_0_windowed_slave_agent_rsp_fifo_out_startofpacket; // address_span_extender_0_windowed_slave_agent_rsp_fifo:out_startofpacket -> address_span_extender_0_windowed_slave_agent:rf_sink_startofpacket
wire [89:0] address_span_extender_0_windowed_slave_agent_rsp_fifo_out_data; // address_span_extender_0_windowed_slave_agent_rsp_fifo:out_data -> address_span_extender_0_windowed_slave_agent:rf_sink_data
wire address_span_extender_0_windowed_slave_agent_rsp_fifo_out_ready; // address_span_extender_0_windowed_slave_agent:rf_sink_ready -> address_span_extender_0_windowed_slave_agent_rsp_fifo:out_ready
wire address_span_extender_0_windowed_slave_agent_rdata_fifo_src_valid; // address_span_extender_0_windowed_slave_agent:rdata_fifo_src_valid -> address_span_extender_0_windowed_slave_agent_rdata_fifo:in_valid
wire [33:0] address_span_extender_0_windowed_slave_agent_rdata_fifo_src_data; // address_span_extender_0_windowed_slave_agent:rdata_fifo_src_data -> address_span_extender_0_windowed_slave_agent_rdata_fifo:in_data
wire address_span_extender_0_windowed_slave_agent_rdata_fifo_src_ready; // address_span_extender_0_windowed_slave_agent_rdata_fifo:in_ready -> address_span_extender_0_windowed_slave_agent:rdata_fifo_src_ready
wire address_span_extender_0_windowed_slave_agent_rdata_fifo_out_valid; // address_span_extender_0_windowed_slave_agent_rdata_fifo:out_valid -> address_span_extender_0_windowed_slave_agent:rdata_fifo_sink_valid
wire [33:0] address_span_extender_0_windowed_slave_agent_rdata_fifo_out_data; // address_span_extender_0_windowed_slave_agent_rdata_fifo:out_data -> address_span_extender_0_windowed_slave_agent:rdata_fifo_sink_data
wire address_span_extender_0_windowed_slave_agent_rdata_fifo_out_ready; // address_span_extender_0_windowed_slave_agent:rdata_fifo_sink_ready -> address_span_extender_0_windowed_slave_agent_rdata_fifo:out_ready
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> address_span_extender_0_windowed_slave_agent:cp_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> address_span_extender_0_windowed_slave_agent:cp_valid
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> address_span_extender_0_windowed_slave_agent:cp_startofpacket
wire [88:0] cmd_mux_src_data; // cmd_mux:src_data -> address_span_extender_0_windowed_slave_agent:cp_data
wire [6:0] cmd_mux_src_channel; // cmd_mux:src_channel -> address_span_extender_0_windowed_slave_agent:cp_channel
wire cmd_mux_src_ready; // address_span_extender_0_windowed_slave_agent:cp_ready -> cmd_mux:src_ready
wire address_span_extender_0_cntl_agent_m0_waitrequest; // address_span_extender_0_cntl_translator:uav_waitrequest -> address_span_extender_0_cntl_agent:m0_waitrequest
wire [3:0] address_span_extender_0_cntl_agent_m0_burstcount; // address_span_extender_0_cntl_agent:m0_burstcount -> address_span_extender_0_cntl_translator:uav_burstcount
wire [63:0] address_span_extender_0_cntl_agent_m0_writedata; // address_span_extender_0_cntl_agent:m0_writedata -> address_span_extender_0_cntl_translator:uav_writedata
wire [13:0] address_span_extender_0_cntl_agent_m0_address; // address_span_extender_0_cntl_agent:m0_address -> address_span_extender_0_cntl_translator:uav_address
wire address_span_extender_0_cntl_agent_m0_write; // address_span_extender_0_cntl_agent:m0_write -> address_span_extender_0_cntl_translator:uav_write
wire address_span_extender_0_cntl_agent_m0_lock; // address_span_extender_0_cntl_agent:m0_lock -> address_span_extender_0_cntl_translator:uav_lock
wire address_span_extender_0_cntl_agent_m0_read; // address_span_extender_0_cntl_agent:m0_read -> address_span_extender_0_cntl_translator:uav_read
wire [63:0] address_span_extender_0_cntl_agent_m0_readdata; // address_span_extender_0_cntl_translator:uav_readdata -> address_span_extender_0_cntl_agent:m0_readdata
wire address_span_extender_0_cntl_agent_m0_readdatavalid; // address_span_extender_0_cntl_translator:uav_readdatavalid -> address_span_extender_0_cntl_agent:m0_readdatavalid
wire address_span_extender_0_cntl_agent_m0_debugaccess; // address_span_extender_0_cntl_agent:m0_debugaccess -> address_span_extender_0_cntl_translator:uav_debugaccess
wire [7:0] address_span_extender_0_cntl_agent_m0_byteenable; // address_span_extender_0_cntl_agent:m0_byteenable -> address_span_extender_0_cntl_translator:uav_byteenable
wire address_span_extender_0_cntl_agent_rf_source_endofpacket; // address_span_extender_0_cntl_agent:rf_source_endofpacket -> address_span_extender_0_cntl_agent_rsp_fifo:in_endofpacket
wire address_span_extender_0_cntl_agent_rf_source_valid; // address_span_extender_0_cntl_agent:rf_source_valid -> address_span_extender_0_cntl_agent_rsp_fifo:in_valid
wire address_span_extender_0_cntl_agent_rf_source_startofpacket; // address_span_extender_0_cntl_agent:rf_source_startofpacket -> address_span_extender_0_cntl_agent_rsp_fifo:in_startofpacket
wire [125:0] address_span_extender_0_cntl_agent_rf_source_data; // address_span_extender_0_cntl_agent:rf_source_data -> address_span_extender_0_cntl_agent_rsp_fifo:in_data
wire address_span_extender_0_cntl_agent_rf_source_ready; // address_span_extender_0_cntl_agent_rsp_fifo:in_ready -> address_span_extender_0_cntl_agent:rf_source_ready
wire address_span_extender_0_cntl_agent_rsp_fifo_out_endofpacket; // address_span_extender_0_cntl_agent_rsp_fifo:out_endofpacket -> address_span_extender_0_cntl_agent:rf_sink_endofpacket
wire address_span_extender_0_cntl_agent_rsp_fifo_out_valid; // address_span_extender_0_cntl_agent_rsp_fifo:out_valid -> address_span_extender_0_cntl_agent:rf_sink_valid
wire address_span_extender_0_cntl_agent_rsp_fifo_out_startofpacket; // address_span_extender_0_cntl_agent_rsp_fifo:out_startofpacket -> address_span_extender_0_cntl_agent:rf_sink_startofpacket
wire [125:0] address_span_extender_0_cntl_agent_rsp_fifo_out_data; // address_span_extender_0_cntl_agent_rsp_fifo:out_data -> address_span_extender_0_cntl_agent:rf_sink_data
wire address_span_extender_0_cntl_agent_rsp_fifo_out_ready; // address_span_extender_0_cntl_agent:rf_sink_ready -> address_span_extender_0_cntl_agent_rsp_fifo:out_ready
wire address_span_extender_0_cntl_agent_rdata_fifo_src_valid; // address_span_extender_0_cntl_agent:rdata_fifo_src_valid -> address_span_extender_0_cntl_agent_rdata_fifo:in_valid
wire [65:0] address_span_extender_0_cntl_agent_rdata_fifo_src_data; // address_span_extender_0_cntl_agent:rdata_fifo_src_data -> address_span_extender_0_cntl_agent_rdata_fifo:in_data
wire address_span_extender_0_cntl_agent_rdata_fifo_src_ready; // address_span_extender_0_cntl_agent_rdata_fifo:in_ready -> address_span_extender_0_cntl_agent:rdata_fifo_src_ready
wire address_span_extender_0_cntl_agent_rdata_fifo_out_valid; // address_span_extender_0_cntl_agent_rdata_fifo:out_valid -> address_span_extender_0_cntl_agent:rdata_fifo_sink_valid
wire [65:0] address_span_extender_0_cntl_agent_rdata_fifo_out_data; // address_span_extender_0_cntl_agent_rdata_fifo:out_data -> address_span_extender_0_cntl_agent:rdata_fifo_sink_data
wire address_span_extender_0_cntl_agent_rdata_fifo_out_ready; // address_span_extender_0_cntl_agent:rdata_fifo_sink_ready -> address_span_extender_0_cntl_agent_rdata_fifo:out_ready
wire sys_description_rom_s1_agent_m0_waitrequest; // sys_description_rom_s1_translator:uav_waitrequest -> sys_description_rom_s1_agent:m0_waitrequest
wire [3:0] sys_description_rom_s1_agent_m0_burstcount; // sys_description_rom_s1_agent:m0_burstcount -> sys_description_rom_s1_translator:uav_burstcount
wire [63:0] sys_description_rom_s1_agent_m0_writedata; // sys_description_rom_s1_agent:m0_writedata -> sys_description_rom_s1_translator:uav_writedata
wire [13:0] sys_description_rom_s1_agent_m0_address; // sys_description_rom_s1_agent:m0_address -> sys_description_rom_s1_translator:uav_address
wire sys_description_rom_s1_agent_m0_write; // sys_description_rom_s1_agent:m0_write -> sys_description_rom_s1_translator:uav_write
wire sys_description_rom_s1_agent_m0_lock; // sys_description_rom_s1_agent:m0_lock -> sys_description_rom_s1_translator:uav_lock
wire sys_description_rom_s1_agent_m0_read; // sys_description_rom_s1_agent:m0_read -> sys_description_rom_s1_translator:uav_read
wire [63:0] sys_description_rom_s1_agent_m0_readdata; // sys_description_rom_s1_translator:uav_readdata -> sys_description_rom_s1_agent:m0_readdata
wire sys_description_rom_s1_agent_m0_readdatavalid; // sys_description_rom_s1_translator:uav_readdatavalid -> sys_description_rom_s1_agent:m0_readdatavalid
wire sys_description_rom_s1_agent_m0_debugaccess; // sys_description_rom_s1_agent:m0_debugaccess -> sys_description_rom_s1_translator:uav_debugaccess
wire [7:0] sys_description_rom_s1_agent_m0_byteenable; // sys_description_rom_s1_agent:m0_byteenable -> sys_description_rom_s1_translator:uav_byteenable
wire sys_description_rom_s1_agent_rf_source_endofpacket; // sys_description_rom_s1_agent:rf_source_endofpacket -> sys_description_rom_s1_agent_rsp_fifo:in_endofpacket
wire sys_description_rom_s1_agent_rf_source_valid; // sys_description_rom_s1_agent:rf_source_valid -> sys_description_rom_s1_agent_rsp_fifo:in_valid
wire sys_description_rom_s1_agent_rf_source_startofpacket; // sys_description_rom_s1_agent:rf_source_startofpacket -> sys_description_rom_s1_agent_rsp_fifo:in_startofpacket
wire [125:0] sys_description_rom_s1_agent_rf_source_data; // sys_description_rom_s1_agent:rf_source_data -> sys_description_rom_s1_agent_rsp_fifo:in_data
wire sys_description_rom_s1_agent_rf_source_ready; // sys_description_rom_s1_agent_rsp_fifo:in_ready -> sys_description_rom_s1_agent:rf_source_ready
wire sys_description_rom_s1_agent_rsp_fifo_out_endofpacket; // sys_description_rom_s1_agent_rsp_fifo:out_endofpacket -> sys_description_rom_s1_agent:rf_sink_endofpacket
wire sys_description_rom_s1_agent_rsp_fifo_out_valid; // sys_description_rom_s1_agent_rsp_fifo:out_valid -> sys_description_rom_s1_agent:rf_sink_valid
wire sys_description_rom_s1_agent_rsp_fifo_out_startofpacket; // sys_description_rom_s1_agent_rsp_fifo:out_startofpacket -> sys_description_rom_s1_agent:rf_sink_startofpacket
wire [125:0] sys_description_rom_s1_agent_rsp_fifo_out_data; // sys_description_rom_s1_agent_rsp_fifo:out_data -> sys_description_rom_s1_agent:rf_sink_data
wire sys_description_rom_s1_agent_rsp_fifo_out_ready; // sys_description_rom_s1_agent:rf_sink_ready -> sys_description_rom_s1_agent_rsp_fifo:out_ready
wire sys_description_rom_s1_agent_rdata_fifo_src_valid; // sys_description_rom_s1_agent:rdata_fifo_src_valid -> sys_description_rom_s1_agent:rdata_fifo_sink_valid
wire [65:0] sys_description_rom_s1_agent_rdata_fifo_src_data; // sys_description_rom_s1_agent:rdata_fifo_src_data -> sys_description_rom_s1_agent:rdata_fifo_sink_data
wire sys_description_rom_s1_agent_rdata_fifo_src_ready; // sys_description_rom_s1_agent:rdata_fifo_sink_ready -> sys_description_rom_s1_agent:rdata_fifo_src_ready
wire sw_reset_s_agent_m0_waitrequest; // sw_reset_s_translator:uav_waitrequest -> sw_reset_s_agent:m0_waitrequest
wire [3:0] sw_reset_s_agent_m0_burstcount; // sw_reset_s_agent:m0_burstcount -> sw_reset_s_translator:uav_burstcount
wire [63:0] sw_reset_s_agent_m0_writedata; // sw_reset_s_agent:m0_writedata -> sw_reset_s_translator:uav_writedata
wire [13:0] sw_reset_s_agent_m0_address; // sw_reset_s_agent:m0_address -> sw_reset_s_translator:uav_address
wire sw_reset_s_agent_m0_write; // sw_reset_s_agent:m0_write -> sw_reset_s_translator:uav_write
wire sw_reset_s_agent_m0_lock; // sw_reset_s_agent:m0_lock -> sw_reset_s_translator:uav_lock
wire sw_reset_s_agent_m0_read; // sw_reset_s_agent:m0_read -> sw_reset_s_translator:uav_read
wire [63:0] sw_reset_s_agent_m0_readdata; // sw_reset_s_translator:uav_readdata -> sw_reset_s_agent:m0_readdata
wire sw_reset_s_agent_m0_readdatavalid; // sw_reset_s_translator:uav_readdatavalid -> sw_reset_s_agent:m0_readdatavalid
wire sw_reset_s_agent_m0_debugaccess; // sw_reset_s_agent:m0_debugaccess -> sw_reset_s_translator:uav_debugaccess
wire [7:0] sw_reset_s_agent_m0_byteenable; // sw_reset_s_agent:m0_byteenable -> sw_reset_s_translator:uav_byteenable
wire sw_reset_s_agent_rf_source_endofpacket; // sw_reset_s_agent:rf_source_endofpacket -> sw_reset_s_agent_rsp_fifo:in_endofpacket
wire sw_reset_s_agent_rf_source_valid; // sw_reset_s_agent:rf_source_valid -> sw_reset_s_agent_rsp_fifo:in_valid
wire sw_reset_s_agent_rf_source_startofpacket; // sw_reset_s_agent:rf_source_startofpacket -> sw_reset_s_agent_rsp_fifo:in_startofpacket
wire [125:0] sw_reset_s_agent_rf_source_data; // sw_reset_s_agent:rf_source_data -> sw_reset_s_agent_rsp_fifo:in_data
wire sw_reset_s_agent_rf_source_ready; // sw_reset_s_agent_rsp_fifo:in_ready -> sw_reset_s_agent:rf_source_ready
wire sw_reset_s_agent_rsp_fifo_out_endofpacket; // sw_reset_s_agent_rsp_fifo:out_endofpacket -> sw_reset_s_agent:rf_sink_endofpacket
wire sw_reset_s_agent_rsp_fifo_out_valid; // sw_reset_s_agent_rsp_fifo:out_valid -> sw_reset_s_agent:rf_sink_valid
wire sw_reset_s_agent_rsp_fifo_out_startofpacket; // sw_reset_s_agent_rsp_fifo:out_startofpacket -> sw_reset_s_agent:rf_sink_startofpacket
wire [125:0] sw_reset_s_agent_rsp_fifo_out_data; // sw_reset_s_agent_rsp_fifo:out_data -> sw_reset_s_agent:rf_sink_data
wire sw_reset_s_agent_rsp_fifo_out_ready; // sw_reset_s_agent:rf_sink_ready -> sw_reset_s_agent_rsp_fifo:out_ready
wire sw_reset_s_agent_rdata_fifo_src_valid; // sw_reset_s_agent:rdata_fifo_src_valid -> sw_reset_s_agent:rdata_fifo_sink_valid
wire [65:0] sw_reset_s_agent_rdata_fifo_src_data; // sw_reset_s_agent:rdata_fifo_src_data -> sw_reset_s_agent:rdata_fifo_sink_data
wire sw_reset_s_agent_rdata_fifo_src_ready; // sw_reset_s_agent:rdata_fifo_sink_ready -> sw_reset_s_agent:rdata_fifo_src_ready
wire mem_org_mode_s_agent_m0_waitrequest; // mem_org_mode_s_translator:uav_waitrequest -> mem_org_mode_s_agent:m0_waitrequest
wire [2:0] mem_org_mode_s_agent_m0_burstcount; // mem_org_mode_s_agent:m0_burstcount -> mem_org_mode_s_translator:uav_burstcount
wire [31:0] mem_org_mode_s_agent_m0_writedata; // mem_org_mode_s_agent:m0_writedata -> mem_org_mode_s_translator:uav_writedata
wire [13:0] mem_org_mode_s_agent_m0_address; // mem_org_mode_s_agent:m0_address -> mem_org_mode_s_translator:uav_address
wire mem_org_mode_s_agent_m0_write; // mem_org_mode_s_agent:m0_write -> mem_org_mode_s_translator:uav_write
wire mem_org_mode_s_agent_m0_lock; // mem_org_mode_s_agent:m0_lock -> mem_org_mode_s_translator:uav_lock
wire mem_org_mode_s_agent_m0_read; // mem_org_mode_s_agent:m0_read -> mem_org_mode_s_translator:uav_read
wire [31:0] mem_org_mode_s_agent_m0_readdata; // mem_org_mode_s_translator:uav_readdata -> mem_org_mode_s_agent:m0_readdata
wire mem_org_mode_s_agent_m0_readdatavalid; // mem_org_mode_s_translator:uav_readdatavalid -> mem_org_mode_s_agent:m0_readdatavalid
wire mem_org_mode_s_agent_m0_debugaccess; // mem_org_mode_s_agent:m0_debugaccess -> mem_org_mode_s_translator:uav_debugaccess
wire [3:0] mem_org_mode_s_agent_m0_byteenable; // mem_org_mode_s_agent:m0_byteenable -> mem_org_mode_s_translator:uav_byteenable
wire mem_org_mode_s_agent_rf_source_endofpacket; // mem_org_mode_s_agent:rf_source_endofpacket -> mem_org_mode_s_agent_rsp_fifo:in_endofpacket
wire mem_org_mode_s_agent_rf_source_valid; // mem_org_mode_s_agent:rf_source_valid -> mem_org_mode_s_agent_rsp_fifo:in_valid
wire mem_org_mode_s_agent_rf_source_startofpacket; // mem_org_mode_s_agent:rf_source_startofpacket -> mem_org_mode_s_agent_rsp_fifo:in_startofpacket
wire [89:0] mem_org_mode_s_agent_rf_source_data; // mem_org_mode_s_agent:rf_source_data -> mem_org_mode_s_agent_rsp_fifo:in_data
wire mem_org_mode_s_agent_rf_source_ready; // mem_org_mode_s_agent_rsp_fifo:in_ready -> mem_org_mode_s_agent:rf_source_ready
wire mem_org_mode_s_agent_rsp_fifo_out_endofpacket; // mem_org_mode_s_agent_rsp_fifo:out_endofpacket -> mem_org_mode_s_agent:rf_sink_endofpacket
wire mem_org_mode_s_agent_rsp_fifo_out_valid; // mem_org_mode_s_agent_rsp_fifo:out_valid -> mem_org_mode_s_agent:rf_sink_valid
wire mem_org_mode_s_agent_rsp_fifo_out_startofpacket; // mem_org_mode_s_agent_rsp_fifo:out_startofpacket -> mem_org_mode_s_agent:rf_sink_startofpacket
wire [89:0] mem_org_mode_s_agent_rsp_fifo_out_data; // mem_org_mode_s_agent_rsp_fifo:out_data -> mem_org_mode_s_agent:rf_sink_data
wire mem_org_mode_s_agent_rsp_fifo_out_ready; // mem_org_mode_s_agent:rf_sink_ready -> mem_org_mode_s_agent_rsp_fifo:out_ready
wire mem_org_mode_s_agent_rdata_fifo_src_valid; // mem_org_mode_s_agent:rdata_fifo_src_valid -> mem_org_mode_s_agent:rdata_fifo_sink_valid
wire [33:0] mem_org_mode_s_agent_rdata_fifo_src_data; // mem_org_mode_s_agent:rdata_fifo_src_data -> mem_org_mode_s_agent:rdata_fifo_sink_data
wire mem_org_mode_s_agent_rdata_fifo_src_ready; // mem_org_mode_s_agent:rdata_fifo_sink_ready -> mem_org_mode_s_agent:rdata_fifo_src_ready
wire cmd_mux_004_src_endofpacket; // cmd_mux_004:src_endofpacket -> mem_org_mode_s_agent:cp_endofpacket
wire cmd_mux_004_src_valid; // cmd_mux_004:src_valid -> mem_org_mode_s_agent:cp_valid
wire cmd_mux_004_src_startofpacket; // cmd_mux_004:src_startofpacket -> mem_org_mode_s_agent:cp_startofpacket
wire [88:0] cmd_mux_004_src_data; // cmd_mux_004:src_data -> mem_org_mode_s_agent:cp_data
wire [6:0] cmd_mux_004_src_channel; // cmd_mux_004:src_channel -> mem_org_mode_s_agent:cp_channel
wire cmd_mux_004_src_ready; // mem_org_mode_s_agent:cp_ready -> cmd_mux_004:src_ready
wire version_id_0_s_agent_m0_waitrequest; // version_id_0_s_translator:uav_waitrequest -> version_id_0_s_agent:m0_waitrequest
wire [2:0] version_id_0_s_agent_m0_burstcount; // version_id_0_s_agent:m0_burstcount -> version_id_0_s_translator:uav_burstcount
wire [31:0] version_id_0_s_agent_m0_writedata; // version_id_0_s_agent:m0_writedata -> version_id_0_s_translator:uav_writedata
wire [13:0] version_id_0_s_agent_m0_address; // version_id_0_s_agent:m0_address -> version_id_0_s_translator:uav_address
wire version_id_0_s_agent_m0_write; // version_id_0_s_agent:m0_write -> version_id_0_s_translator:uav_write
wire version_id_0_s_agent_m0_lock; // version_id_0_s_agent:m0_lock -> version_id_0_s_translator:uav_lock
wire version_id_0_s_agent_m0_read; // version_id_0_s_agent:m0_read -> version_id_0_s_translator:uav_read
wire [31:0] version_id_0_s_agent_m0_readdata; // version_id_0_s_translator:uav_readdata -> version_id_0_s_agent:m0_readdata
wire version_id_0_s_agent_m0_readdatavalid; // version_id_0_s_translator:uav_readdatavalid -> version_id_0_s_agent:m0_readdatavalid
wire version_id_0_s_agent_m0_debugaccess; // version_id_0_s_agent:m0_debugaccess -> version_id_0_s_translator:uav_debugaccess
wire [3:0] version_id_0_s_agent_m0_byteenable; // version_id_0_s_agent:m0_byteenable -> version_id_0_s_translator:uav_byteenable
wire version_id_0_s_agent_rf_source_endofpacket; // version_id_0_s_agent:rf_source_endofpacket -> version_id_0_s_agent_rsp_fifo:in_endofpacket
wire version_id_0_s_agent_rf_source_valid; // version_id_0_s_agent:rf_source_valid -> version_id_0_s_agent_rsp_fifo:in_valid
wire version_id_0_s_agent_rf_source_startofpacket; // version_id_0_s_agent:rf_source_startofpacket -> version_id_0_s_agent_rsp_fifo:in_startofpacket
wire [89:0] version_id_0_s_agent_rf_source_data; // version_id_0_s_agent:rf_source_data -> version_id_0_s_agent_rsp_fifo:in_data
wire version_id_0_s_agent_rf_source_ready; // version_id_0_s_agent_rsp_fifo:in_ready -> version_id_0_s_agent:rf_source_ready
wire version_id_0_s_agent_rsp_fifo_out_endofpacket; // version_id_0_s_agent_rsp_fifo:out_endofpacket -> version_id_0_s_agent:rf_sink_endofpacket
wire version_id_0_s_agent_rsp_fifo_out_valid; // version_id_0_s_agent_rsp_fifo:out_valid -> version_id_0_s_agent:rf_sink_valid
wire version_id_0_s_agent_rsp_fifo_out_startofpacket; // version_id_0_s_agent_rsp_fifo:out_startofpacket -> version_id_0_s_agent:rf_sink_startofpacket
wire [89:0] version_id_0_s_agent_rsp_fifo_out_data; // version_id_0_s_agent_rsp_fifo:out_data -> version_id_0_s_agent:rf_sink_data
wire version_id_0_s_agent_rsp_fifo_out_ready; // version_id_0_s_agent:rf_sink_ready -> version_id_0_s_agent_rsp_fifo:out_ready
wire version_id_0_s_agent_rdata_fifo_src_valid; // version_id_0_s_agent:rdata_fifo_src_valid -> version_id_0_s_agent:rdata_fifo_sink_valid
wire [33:0] version_id_0_s_agent_rdata_fifo_src_data; // version_id_0_s_agent:rdata_fifo_src_data -> version_id_0_s_agent:rdata_fifo_sink_data
wire version_id_0_s_agent_rdata_fifo_src_ready; // version_id_0_s_agent:rdata_fifo_sink_ready -> version_id_0_s_agent:rdata_fifo_src_ready
wire cmd_mux_005_src_endofpacket; // cmd_mux_005:src_endofpacket -> version_id_0_s_agent:cp_endofpacket
wire cmd_mux_005_src_valid; // cmd_mux_005:src_valid -> version_id_0_s_agent:cp_valid
wire cmd_mux_005_src_startofpacket; // cmd_mux_005:src_startofpacket -> version_id_0_s_agent:cp_startofpacket
wire [88:0] cmd_mux_005_src_data; // cmd_mux_005:src_data -> version_id_0_s_agent:cp_data
wire [6:0] cmd_mux_005_src_channel; // cmd_mux_005:src_channel -> version_id_0_s_agent:cp_channel
wire cmd_mux_005_src_ready; // version_id_0_s_agent:cp_ready -> cmd_mux_005:src_ready
wire irq_ena_0_s_agent_m0_waitrequest; // irq_ena_0_s_translator:uav_waitrequest -> irq_ena_0_s_agent:m0_waitrequest
wire [2:0] irq_ena_0_s_agent_m0_burstcount; // irq_ena_0_s_agent:m0_burstcount -> irq_ena_0_s_translator:uav_burstcount
wire [31:0] irq_ena_0_s_agent_m0_writedata; // irq_ena_0_s_agent:m0_writedata -> irq_ena_0_s_translator:uav_writedata
wire [13:0] irq_ena_0_s_agent_m0_address; // irq_ena_0_s_agent:m0_address -> irq_ena_0_s_translator:uav_address
wire irq_ena_0_s_agent_m0_write; // irq_ena_0_s_agent:m0_write -> irq_ena_0_s_translator:uav_write
wire irq_ena_0_s_agent_m0_lock; // irq_ena_0_s_agent:m0_lock -> irq_ena_0_s_translator:uav_lock
wire irq_ena_0_s_agent_m0_read; // irq_ena_0_s_agent:m0_read -> irq_ena_0_s_translator:uav_read
wire [31:0] irq_ena_0_s_agent_m0_readdata; // irq_ena_0_s_translator:uav_readdata -> irq_ena_0_s_agent:m0_readdata
wire irq_ena_0_s_agent_m0_readdatavalid; // irq_ena_0_s_translator:uav_readdatavalid -> irq_ena_0_s_agent:m0_readdatavalid
wire irq_ena_0_s_agent_m0_debugaccess; // irq_ena_0_s_agent:m0_debugaccess -> irq_ena_0_s_translator:uav_debugaccess
wire [3:0] irq_ena_0_s_agent_m0_byteenable; // irq_ena_0_s_agent:m0_byteenable -> irq_ena_0_s_translator:uav_byteenable
wire irq_ena_0_s_agent_rf_source_endofpacket; // irq_ena_0_s_agent:rf_source_endofpacket -> irq_ena_0_s_agent_rsp_fifo:in_endofpacket
wire irq_ena_0_s_agent_rf_source_valid; // irq_ena_0_s_agent:rf_source_valid -> irq_ena_0_s_agent_rsp_fifo:in_valid
wire irq_ena_0_s_agent_rf_source_startofpacket; // irq_ena_0_s_agent:rf_source_startofpacket -> irq_ena_0_s_agent_rsp_fifo:in_startofpacket
wire [89:0] irq_ena_0_s_agent_rf_source_data; // irq_ena_0_s_agent:rf_source_data -> irq_ena_0_s_agent_rsp_fifo:in_data
wire irq_ena_0_s_agent_rf_source_ready; // irq_ena_0_s_agent_rsp_fifo:in_ready -> irq_ena_0_s_agent:rf_source_ready
wire irq_ena_0_s_agent_rsp_fifo_out_endofpacket; // irq_ena_0_s_agent_rsp_fifo:out_endofpacket -> irq_ena_0_s_agent:rf_sink_endofpacket
wire irq_ena_0_s_agent_rsp_fifo_out_valid; // irq_ena_0_s_agent_rsp_fifo:out_valid -> irq_ena_0_s_agent:rf_sink_valid
wire irq_ena_0_s_agent_rsp_fifo_out_startofpacket; // irq_ena_0_s_agent_rsp_fifo:out_startofpacket -> irq_ena_0_s_agent:rf_sink_startofpacket
wire [89:0] irq_ena_0_s_agent_rsp_fifo_out_data; // irq_ena_0_s_agent_rsp_fifo:out_data -> irq_ena_0_s_agent:rf_sink_data
wire irq_ena_0_s_agent_rsp_fifo_out_ready; // irq_ena_0_s_agent:rf_sink_ready -> irq_ena_0_s_agent_rsp_fifo:out_ready
wire irq_ena_0_s_agent_rdata_fifo_src_valid; // irq_ena_0_s_agent:rdata_fifo_src_valid -> irq_ena_0_s_agent:rdata_fifo_sink_valid
wire [33:0] irq_ena_0_s_agent_rdata_fifo_src_data; // irq_ena_0_s_agent:rdata_fifo_src_data -> irq_ena_0_s_agent:rdata_fifo_sink_data
wire irq_ena_0_s_agent_rdata_fifo_src_ready; // irq_ena_0_s_agent:rdata_fifo_sink_ready -> irq_ena_0_s_agent:rdata_fifo_src_ready
wire cmd_mux_006_src_endofpacket; // cmd_mux_006:src_endofpacket -> irq_ena_0_s_agent:cp_endofpacket
wire cmd_mux_006_src_valid; // cmd_mux_006:src_valid -> irq_ena_0_s_agent:cp_valid
wire cmd_mux_006_src_startofpacket; // cmd_mux_006:src_startofpacket -> irq_ena_0_s_agent:cp_startofpacket
wire [88:0] cmd_mux_006_src_data; // cmd_mux_006:src_data -> irq_ena_0_s_agent:cp_data
wire [6:0] cmd_mux_006_src_channel; // cmd_mux_006:src_channel -> irq_ena_0_s_agent:cp_channel
wire cmd_mux_006_src_ready; // irq_ena_0_s_agent:cp_ready -> cmd_mux_006:src_ready
wire kernel_cntrl_m0_agent_cp_endofpacket; // kernel_cntrl_m0_agent:cp_endofpacket -> router:sink_endofpacket
wire kernel_cntrl_m0_agent_cp_valid; // kernel_cntrl_m0_agent:cp_valid -> router:sink_valid
wire kernel_cntrl_m0_agent_cp_startofpacket; // kernel_cntrl_m0_agent:cp_startofpacket -> router:sink_startofpacket
wire [88:0] kernel_cntrl_m0_agent_cp_data; // kernel_cntrl_m0_agent:cp_data -> router:sink_data
wire kernel_cntrl_m0_agent_cp_ready; // router:sink_ready -> kernel_cntrl_m0_agent:cp_ready
wire address_span_extender_0_windowed_slave_agent_rp_endofpacket; // address_span_extender_0_windowed_slave_agent:rp_endofpacket -> router_001:sink_endofpacket
wire address_span_extender_0_windowed_slave_agent_rp_valid; // address_span_extender_0_windowed_slave_agent:rp_valid -> router_001:sink_valid
wire address_span_extender_0_windowed_slave_agent_rp_startofpacket; // address_span_extender_0_windowed_slave_agent:rp_startofpacket -> router_001:sink_startofpacket
wire [88:0] address_span_extender_0_windowed_slave_agent_rp_data; // address_span_extender_0_windowed_slave_agent:rp_data -> router_001:sink_data
wire address_span_extender_0_windowed_slave_agent_rp_ready; // router_001:sink_ready -> address_span_extender_0_windowed_slave_agent:rp_ready
wire router_001_src_endofpacket; // router_001:src_endofpacket -> rsp_demux:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> rsp_demux:sink_valid
wire router_001_src_startofpacket; // router_001:src_startofpacket -> rsp_demux:sink_startofpacket
wire [88:0] router_001_src_data; // router_001:src_data -> rsp_demux:sink_data
wire [6:0] router_001_src_channel; // router_001:src_channel -> rsp_demux:sink_channel
wire router_001_src_ready; // rsp_demux:sink_ready -> router_001:src_ready
wire address_span_extender_0_cntl_agent_rp_endofpacket; // address_span_extender_0_cntl_agent:rp_endofpacket -> router_002:sink_endofpacket
wire address_span_extender_0_cntl_agent_rp_valid; // address_span_extender_0_cntl_agent:rp_valid -> router_002:sink_valid
wire address_span_extender_0_cntl_agent_rp_startofpacket; // address_span_extender_0_cntl_agent:rp_startofpacket -> router_002:sink_startofpacket
wire [124:0] address_span_extender_0_cntl_agent_rp_data; // address_span_extender_0_cntl_agent:rp_data -> router_002:sink_data
wire address_span_extender_0_cntl_agent_rp_ready; // router_002:sink_ready -> address_span_extender_0_cntl_agent:rp_ready
wire sys_description_rom_s1_agent_rp_endofpacket; // sys_description_rom_s1_agent:rp_endofpacket -> router_003:sink_endofpacket
wire sys_description_rom_s1_agent_rp_valid; // sys_description_rom_s1_agent:rp_valid -> router_003:sink_valid
wire sys_description_rom_s1_agent_rp_startofpacket; // sys_description_rom_s1_agent:rp_startofpacket -> router_003:sink_startofpacket
wire [124:0] sys_description_rom_s1_agent_rp_data; // sys_description_rom_s1_agent:rp_data -> router_003:sink_data
wire sys_description_rom_s1_agent_rp_ready; // router_003:sink_ready -> sys_description_rom_s1_agent:rp_ready
wire sw_reset_s_agent_rp_endofpacket; // sw_reset_s_agent:rp_endofpacket -> router_004:sink_endofpacket
wire sw_reset_s_agent_rp_valid; // sw_reset_s_agent:rp_valid -> router_004:sink_valid
wire sw_reset_s_agent_rp_startofpacket; // sw_reset_s_agent:rp_startofpacket -> router_004:sink_startofpacket
wire [124:0] sw_reset_s_agent_rp_data; // sw_reset_s_agent:rp_data -> router_004:sink_data
wire sw_reset_s_agent_rp_ready; // router_004:sink_ready -> sw_reset_s_agent:rp_ready
wire mem_org_mode_s_agent_rp_endofpacket; // mem_org_mode_s_agent:rp_endofpacket -> router_005:sink_endofpacket
wire mem_org_mode_s_agent_rp_valid; // mem_org_mode_s_agent:rp_valid -> router_005:sink_valid
wire mem_org_mode_s_agent_rp_startofpacket; // mem_org_mode_s_agent:rp_startofpacket -> router_005:sink_startofpacket
wire [88:0] mem_org_mode_s_agent_rp_data; // mem_org_mode_s_agent:rp_data -> router_005:sink_data
wire mem_org_mode_s_agent_rp_ready; // router_005:sink_ready -> mem_org_mode_s_agent:rp_ready
wire router_005_src_endofpacket; // router_005:src_endofpacket -> rsp_demux_004:sink_endofpacket
wire router_005_src_valid; // router_005:src_valid -> rsp_demux_004:sink_valid
wire router_005_src_startofpacket; // router_005:src_startofpacket -> rsp_demux_004:sink_startofpacket
wire [88:0] router_005_src_data; // router_005:src_data -> rsp_demux_004:sink_data
wire [6:0] router_005_src_channel; // router_005:src_channel -> rsp_demux_004:sink_channel
wire router_005_src_ready; // rsp_demux_004:sink_ready -> router_005:src_ready
wire version_id_0_s_agent_rp_endofpacket; // version_id_0_s_agent:rp_endofpacket -> router_006:sink_endofpacket
wire version_id_0_s_agent_rp_valid; // version_id_0_s_agent:rp_valid -> router_006:sink_valid
wire version_id_0_s_agent_rp_startofpacket; // version_id_0_s_agent:rp_startofpacket -> router_006:sink_startofpacket
wire [88:0] version_id_0_s_agent_rp_data; // version_id_0_s_agent:rp_data -> router_006:sink_data
wire version_id_0_s_agent_rp_ready; // router_006:sink_ready -> version_id_0_s_agent:rp_ready
wire router_006_src_endofpacket; // router_006:src_endofpacket -> rsp_demux_005:sink_endofpacket
wire router_006_src_valid; // router_006:src_valid -> rsp_demux_005:sink_valid
wire router_006_src_startofpacket; // router_006:src_startofpacket -> rsp_demux_005:sink_startofpacket
wire [88:0] router_006_src_data; // router_006:src_data -> rsp_demux_005:sink_data
wire [6:0] router_006_src_channel; // router_006:src_channel -> rsp_demux_005:sink_channel
wire router_006_src_ready; // rsp_demux_005:sink_ready -> router_006:src_ready
wire irq_ena_0_s_agent_rp_endofpacket; // irq_ena_0_s_agent:rp_endofpacket -> router_007:sink_endofpacket
wire irq_ena_0_s_agent_rp_valid; // irq_ena_0_s_agent:rp_valid -> router_007:sink_valid
wire irq_ena_0_s_agent_rp_startofpacket; // irq_ena_0_s_agent:rp_startofpacket -> router_007:sink_startofpacket
wire [88:0] irq_ena_0_s_agent_rp_data; // irq_ena_0_s_agent:rp_data -> router_007:sink_data
wire irq_ena_0_s_agent_rp_ready; // router_007:sink_ready -> irq_ena_0_s_agent:rp_ready
wire router_007_src_endofpacket; // router_007:src_endofpacket -> rsp_demux_006:sink_endofpacket
wire router_007_src_valid; // router_007:src_valid -> rsp_demux_006:sink_valid
wire router_007_src_startofpacket; // router_007:src_startofpacket -> rsp_demux_006:sink_startofpacket
wire [88:0] router_007_src_data; // router_007:src_data -> rsp_demux_006:sink_data
wire [6:0] router_007_src_channel; // router_007:src_channel -> rsp_demux_006:sink_channel
wire router_007_src_ready; // rsp_demux_006:sink_ready -> router_007:src_ready
wire router_src_endofpacket; // router:src_endofpacket -> kernel_cntrl_m0_limiter:cmd_sink_endofpacket
wire router_src_valid; // router:src_valid -> kernel_cntrl_m0_limiter:cmd_sink_valid
wire router_src_startofpacket; // router:src_startofpacket -> kernel_cntrl_m0_limiter:cmd_sink_startofpacket
wire [88:0] router_src_data; // router:src_data -> kernel_cntrl_m0_limiter:cmd_sink_data
wire [6:0] router_src_channel; // router:src_channel -> kernel_cntrl_m0_limiter:cmd_sink_channel
wire router_src_ready; // kernel_cntrl_m0_limiter:cmd_sink_ready -> router:src_ready
wire kernel_cntrl_m0_limiter_cmd_src_endofpacket; // kernel_cntrl_m0_limiter:cmd_src_endofpacket -> cmd_demux:sink_endofpacket
wire kernel_cntrl_m0_limiter_cmd_src_startofpacket; // kernel_cntrl_m0_limiter:cmd_src_startofpacket -> cmd_demux:sink_startofpacket
wire [88:0] kernel_cntrl_m0_limiter_cmd_src_data; // kernel_cntrl_m0_limiter:cmd_src_data -> cmd_demux:sink_data
wire [6:0] kernel_cntrl_m0_limiter_cmd_src_channel; // kernel_cntrl_m0_limiter:cmd_src_channel -> cmd_demux:sink_channel
wire kernel_cntrl_m0_limiter_cmd_src_ready; // cmd_demux:sink_ready -> kernel_cntrl_m0_limiter:cmd_src_ready
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> kernel_cntrl_m0_limiter:rsp_sink_endofpacket
wire rsp_mux_src_valid; // rsp_mux:src_valid -> kernel_cntrl_m0_limiter:rsp_sink_valid
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> kernel_cntrl_m0_limiter:rsp_sink_startofpacket
wire [88:0] rsp_mux_src_data; // rsp_mux:src_data -> kernel_cntrl_m0_limiter:rsp_sink_data
wire [6:0] rsp_mux_src_channel; // rsp_mux:src_channel -> kernel_cntrl_m0_limiter:rsp_sink_channel
wire rsp_mux_src_ready; // kernel_cntrl_m0_limiter:rsp_sink_ready -> rsp_mux:src_ready
wire kernel_cntrl_m0_limiter_rsp_src_endofpacket; // kernel_cntrl_m0_limiter:rsp_src_endofpacket -> kernel_cntrl_m0_agent:rp_endofpacket
wire kernel_cntrl_m0_limiter_rsp_src_valid; // kernel_cntrl_m0_limiter:rsp_src_valid -> kernel_cntrl_m0_agent:rp_valid
wire kernel_cntrl_m0_limiter_rsp_src_startofpacket; // kernel_cntrl_m0_limiter:rsp_src_startofpacket -> kernel_cntrl_m0_agent:rp_startofpacket
wire [88:0] kernel_cntrl_m0_limiter_rsp_src_data; // kernel_cntrl_m0_limiter:rsp_src_data -> kernel_cntrl_m0_agent:rp_data
wire [6:0] kernel_cntrl_m0_limiter_rsp_src_channel; // kernel_cntrl_m0_limiter:rsp_src_channel -> kernel_cntrl_m0_agent:rp_channel
wire kernel_cntrl_m0_limiter_rsp_src_ready; // kernel_cntrl_m0_agent:rp_ready -> kernel_cntrl_m0_limiter:rsp_src_ready
wire cmd_demux_src2_endofpacket; // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
wire cmd_demux_src2_valid; // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
wire cmd_demux_src2_startofpacket; // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
wire [88:0] cmd_demux_src2_data; // cmd_demux:src2_data -> cmd_mux_002:sink0_data
wire [6:0] cmd_demux_src2_channel; // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
wire cmd_demux_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
wire cmd_demux_src3_endofpacket; // cmd_demux:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
wire cmd_demux_src3_valid; // cmd_demux:src3_valid -> cmd_mux_003:sink0_valid
wire cmd_demux_src3_startofpacket; // cmd_demux:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
wire [88:0] cmd_demux_src3_data; // cmd_demux:src3_data -> cmd_mux_003:sink0_data
wire [6:0] cmd_demux_src3_channel; // cmd_demux:src3_channel -> cmd_mux_003:sink0_channel
wire cmd_demux_src3_ready; // cmd_mux_003:sink0_ready -> cmd_demux:src3_ready
wire cmd_demux_src4_endofpacket; // cmd_demux:src4_endofpacket -> cmd_mux_004:sink0_endofpacket
wire cmd_demux_src4_valid; // cmd_demux:src4_valid -> cmd_mux_004:sink0_valid
wire cmd_demux_src4_startofpacket; // cmd_demux:src4_startofpacket -> cmd_mux_004:sink0_startofpacket
wire [88:0] cmd_demux_src4_data; // cmd_demux:src4_data -> cmd_mux_004:sink0_data
wire [6:0] cmd_demux_src4_channel; // cmd_demux:src4_channel -> cmd_mux_004:sink0_channel
wire cmd_demux_src4_ready; // cmd_mux_004:sink0_ready -> cmd_demux:src4_ready
wire cmd_demux_src5_endofpacket; // cmd_demux:src5_endofpacket -> cmd_mux_005:sink0_endofpacket
wire cmd_demux_src5_valid; // cmd_demux:src5_valid -> cmd_mux_005:sink0_valid
wire cmd_demux_src5_startofpacket; // cmd_demux:src5_startofpacket -> cmd_mux_005:sink0_startofpacket
wire [88:0] cmd_demux_src5_data; // cmd_demux:src5_data -> cmd_mux_005:sink0_data
wire [6:0] cmd_demux_src5_channel; // cmd_demux:src5_channel -> cmd_mux_005:sink0_channel
wire cmd_demux_src5_ready; // cmd_mux_005:sink0_ready -> cmd_demux:src5_ready
wire cmd_demux_src6_endofpacket; // cmd_demux:src6_endofpacket -> cmd_mux_006:sink0_endofpacket
wire cmd_demux_src6_valid; // cmd_demux:src6_valid -> cmd_mux_006:sink0_valid
wire cmd_demux_src6_startofpacket; // cmd_demux:src6_startofpacket -> cmd_mux_006:sink0_startofpacket
wire [88:0] cmd_demux_src6_data; // cmd_demux:src6_data -> cmd_mux_006:sink0_data
wire [6:0] cmd_demux_src6_channel; // cmd_demux:src6_channel -> cmd_mux_006:sink0_channel
wire cmd_demux_src6_ready; // cmd_mux_006:sink0_ready -> cmd_demux:src6_ready
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
wire [88:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux:sink2_data
wire [6:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
wire rsp_demux_002_src0_ready; // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
wire rsp_demux_003_src0_endofpacket; // rsp_demux_003:src0_endofpacket -> rsp_mux:sink3_endofpacket
wire rsp_demux_003_src0_valid; // rsp_demux_003:src0_valid -> rsp_mux:sink3_valid
wire rsp_demux_003_src0_startofpacket; // rsp_demux_003:src0_startofpacket -> rsp_mux:sink3_startofpacket
wire [88:0] rsp_demux_003_src0_data; // rsp_demux_003:src0_data -> rsp_mux:sink3_data
wire [6:0] rsp_demux_003_src0_channel; // rsp_demux_003:src0_channel -> rsp_mux:sink3_channel
wire rsp_demux_003_src0_ready; // rsp_mux:sink3_ready -> rsp_demux_003:src0_ready
wire rsp_demux_004_src0_endofpacket; // rsp_demux_004:src0_endofpacket -> rsp_mux:sink4_endofpacket
wire rsp_demux_004_src0_valid; // rsp_demux_004:src0_valid -> rsp_mux:sink4_valid
wire rsp_demux_004_src0_startofpacket; // rsp_demux_004:src0_startofpacket -> rsp_mux:sink4_startofpacket
wire [88:0] rsp_demux_004_src0_data; // rsp_demux_004:src0_data -> rsp_mux:sink4_data
wire [6:0] rsp_demux_004_src0_channel; // rsp_demux_004:src0_channel -> rsp_mux:sink4_channel
wire rsp_demux_004_src0_ready; // rsp_mux:sink4_ready -> rsp_demux_004:src0_ready
wire rsp_demux_005_src0_endofpacket; // rsp_demux_005:src0_endofpacket -> rsp_mux:sink5_endofpacket
wire rsp_demux_005_src0_valid; // rsp_demux_005:src0_valid -> rsp_mux:sink5_valid
wire rsp_demux_005_src0_startofpacket; // rsp_demux_005:src0_startofpacket -> rsp_mux:sink5_startofpacket
wire [88:0] rsp_demux_005_src0_data; // rsp_demux_005:src0_data -> rsp_mux:sink5_data
wire [6:0] rsp_demux_005_src0_channel; // rsp_demux_005:src0_channel -> rsp_mux:sink5_channel
wire rsp_demux_005_src0_ready; // rsp_mux:sink5_ready -> rsp_demux_005:src0_ready
wire rsp_demux_006_src0_endofpacket; // rsp_demux_006:src0_endofpacket -> rsp_mux:sink6_endofpacket
wire rsp_demux_006_src0_valid; // rsp_demux_006:src0_valid -> rsp_mux:sink6_valid
wire rsp_demux_006_src0_startofpacket; // rsp_demux_006:src0_startofpacket -> rsp_mux:sink6_startofpacket
wire [88:0] rsp_demux_006_src0_data; // rsp_demux_006:src0_data -> rsp_mux:sink6_data
wire [6:0] rsp_demux_006_src0_channel; // rsp_demux_006:src0_channel -> rsp_mux:sink6_channel
wire rsp_demux_006_src0_ready; // rsp_mux:sink6_ready -> rsp_demux_006:src0_ready
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> address_span_extender_0_cntl_cmd_width_adapter:in_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> address_span_extender_0_cntl_cmd_width_adapter:in_valid
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> address_span_extender_0_cntl_cmd_width_adapter:in_startofpacket
wire [88:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> address_span_extender_0_cntl_cmd_width_adapter:in_data
wire [6:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> address_span_extender_0_cntl_cmd_width_adapter:in_channel
wire cmd_mux_001_src_ready; // address_span_extender_0_cntl_cmd_width_adapter:in_ready -> cmd_mux_001:src_ready
wire address_span_extender_0_cntl_cmd_width_adapter_src_endofpacket; // address_span_extender_0_cntl_cmd_width_adapter:out_endofpacket -> address_span_extender_0_cntl_agent:cp_endofpacket
wire address_span_extender_0_cntl_cmd_width_adapter_src_valid; // address_span_extender_0_cntl_cmd_width_adapter:out_valid -> address_span_extender_0_cntl_agent:cp_valid
wire address_span_extender_0_cntl_cmd_width_adapter_src_startofpacket; // address_span_extender_0_cntl_cmd_width_adapter:out_startofpacket -> address_span_extender_0_cntl_agent:cp_startofpacket
wire [124:0] address_span_extender_0_cntl_cmd_width_adapter_src_data; // address_span_extender_0_cntl_cmd_width_adapter:out_data -> address_span_extender_0_cntl_agent:cp_data
wire address_span_extender_0_cntl_cmd_width_adapter_src_ready; // address_span_extender_0_cntl_agent:cp_ready -> address_span_extender_0_cntl_cmd_width_adapter:out_ready
wire [6:0] address_span_extender_0_cntl_cmd_width_adapter_src_channel; // address_span_extender_0_cntl_cmd_width_adapter:out_channel -> address_span_extender_0_cntl_agent:cp_channel
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> sys_description_rom_s1_cmd_width_adapter:in_endofpacket
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> sys_description_rom_s1_cmd_width_adapter:in_valid
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> sys_description_rom_s1_cmd_width_adapter:in_startofpacket
wire [88:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> sys_description_rom_s1_cmd_width_adapter:in_data
wire [6:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> sys_description_rom_s1_cmd_width_adapter:in_channel
wire cmd_mux_002_src_ready; // sys_description_rom_s1_cmd_width_adapter:in_ready -> cmd_mux_002:src_ready
wire sys_description_rom_s1_cmd_width_adapter_src_endofpacket; // sys_description_rom_s1_cmd_width_adapter:out_endofpacket -> sys_description_rom_s1_agent:cp_endofpacket
wire sys_description_rom_s1_cmd_width_adapter_src_valid; // sys_description_rom_s1_cmd_width_adapter:out_valid -> sys_description_rom_s1_agent:cp_valid
wire sys_description_rom_s1_cmd_width_adapter_src_startofpacket; // sys_description_rom_s1_cmd_width_adapter:out_startofpacket -> sys_description_rom_s1_agent:cp_startofpacket
wire [124:0] sys_description_rom_s1_cmd_width_adapter_src_data; // sys_description_rom_s1_cmd_width_adapter:out_data -> sys_description_rom_s1_agent:cp_data
wire sys_description_rom_s1_cmd_width_adapter_src_ready; // sys_description_rom_s1_agent:cp_ready -> sys_description_rom_s1_cmd_width_adapter:out_ready
wire [6:0] sys_description_rom_s1_cmd_width_adapter_src_channel; // sys_description_rom_s1_cmd_width_adapter:out_channel -> sys_description_rom_s1_agent:cp_channel
wire cmd_mux_003_src_endofpacket; // cmd_mux_003:src_endofpacket -> sw_reset_s_cmd_width_adapter:in_endofpacket
wire cmd_mux_003_src_valid; // cmd_mux_003:src_valid -> sw_reset_s_cmd_width_adapter:in_valid
wire cmd_mux_003_src_startofpacket; // cmd_mux_003:src_startofpacket -> sw_reset_s_cmd_width_adapter:in_startofpacket
wire [88:0] cmd_mux_003_src_data; // cmd_mux_003:src_data -> sw_reset_s_cmd_width_adapter:in_data
wire [6:0] cmd_mux_003_src_channel; // cmd_mux_003:src_channel -> sw_reset_s_cmd_width_adapter:in_channel
wire cmd_mux_003_src_ready; // sw_reset_s_cmd_width_adapter:in_ready -> cmd_mux_003:src_ready
wire sw_reset_s_cmd_width_adapter_src_endofpacket; // sw_reset_s_cmd_width_adapter:out_endofpacket -> sw_reset_s_agent:cp_endofpacket
wire sw_reset_s_cmd_width_adapter_src_valid; // sw_reset_s_cmd_width_adapter:out_valid -> sw_reset_s_agent:cp_valid
wire sw_reset_s_cmd_width_adapter_src_startofpacket; // sw_reset_s_cmd_width_adapter:out_startofpacket -> sw_reset_s_agent:cp_startofpacket
wire [124:0] sw_reset_s_cmd_width_adapter_src_data; // sw_reset_s_cmd_width_adapter:out_data -> sw_reset_s_agent:cp_data
wire sw_reset_s_cmd_width_adapter_src_ready; // sw_reset_s_agent:cp_ready -> sw_reset_s_cmd_width_adapter:out_ready
wire [6:0] sw_reset_s_cmd_width_adapter_src_channel; // sw_reset_s_cmd_width_adapter:out_channel -> sw_reset_s_agent:cp_channel
wire router_002_src_endofpacket; // router_002:src_endofpacket -> address_span_extender_0_cntl_rsp_width_adapter:in_endofpacket
wire router_002_src_valid; // router_002:src_valid -> address_span_extender_0_cntl_rsp_width_adapter:in_valid
wire router_002_src_startofpacket; // router_002:src_startofpacket -> address_span_extender_0_cntl_rsp_width_adapter:in_startofpacket
wire [124:0] router_002_src_data; // router_002:src_data -> address_span_extender_0_cntl_rsp_width_adapter:in_data
wire [6:0] router_002_src_channel; // router_002:src_channel -> address_span_extender_0_cntl_rsp_width_adapter:in_channel
wire router_002_src_ready; // address_span_extender_0_cntl_rsp_width_adapter:in_ready -> router_002:src_ready
wire address_span_extender_0_cntl_rsp_width_adapter_src_endofpacket; // address_span_extender_0_cntl_rsp_width_adapter:out_endofpacket -> rsp_demux_001:sink_endofpacket
wire address_span_extender_0_cntl_rsp_width_adapter_src_valid; // address_span_extender_0_cntl_rsp_width_adapter:out_valid -> rsp_demux_001:sink_valid
wire address_span_extender_0_cntl_rsp_width_adapter_src_startofpacket; // address_span_extender_0_cntl_rsp_width_adapter:out_startofpacket -> rsp_demux_001:sink_startofpacket
wire [88:0] address_span_extender_0_cntl_rsp_width_adapter_src_data; // address_span_extender_0_cntl_rsp_width_adapter:out_data -> rsp_demux_001:sink_data
wire address_span_extender_0_cntl_rsp_width_adapter_src_ready; // rsp_demux_001:sink_ready -> address_span_extender_0_cntl_rsp_width_adapter:out_ready
wire [6:0] address_span_extender_0_cntl_rsp_width_adapter_src_channel; // address_span_extender_0_cntl_rsp_width_adapter:out_channel -> rsp_demux_001:sink_channel
wire router_003_src_endofpacket; // router_003:src_endofpacket -> sys_description_rom_s1_rsp_width_adapter:in_endofpacket
wire router_003_src_valid; // router_003:src_valid -> sys_description_rom_s1_rsp_width_adapter:in_valid
wire router_003_src_startofpacket; // router_003:src_startofpacket -> sys_description_rom_s1_rsp_width_adapter:in_startofpacket
wire [124:0] router_003_src_data; // router_003:src_data -> sys_description_rom_s1_rsp_width_adapter:in_data
wire [6:0] router_003_src_channel; // router_003:src_channel -> sys_description_rom_s1_rsp_width_adapter:in_channel
wire router_003_src_ready; // sys_description_rom_s1_rsp_width_adapter:in_ready -> router_003:src_ready
wire sys_description_rom_s1_rsp_width_adapter_src_endofpacket; // sys_description_rom_s1_rsp_width_adapter:out_endofpacket -> rsp_demux_002:sink_endofpacket
wire sys_description_rom_s1_rsp_width_adapter_src_valid; // sys_description_rom_s1_rsp_width_adapter:out_valid -> rsp_demux_002:sink_valid
wire sys_description_rom_s1_rsp_width_adapter_src_startofpacket; // sys_description_rom_s1_rsp_width_adapter:out_startofpacket -> rsp_demux_002:sink_startofpacket
wire [88:0] sys_description_rom_s1_rsp_width_adapter_src_data; // sys_description_rom_s1_rsp_width_adapter:out_data -> rsp_demux_002:sink_data
wire sys_description_rom_s1_rsp_width_adapter_src_ready; // rsp_demux_002:sink_ready -> sys_description_rom_s1_rsp_width_adapter:out_ready
wire [6:0] sys_description_rom_s1_rsp_width_adapter_src_channel; // sys_description_rom_s1_rsp_width_adapter:out_channel -> rsp_demux_002:sink_channel
wire router_004_src_endofpacket; // router_004:src_endofpacket -> sw_reset_s_rsp_width_adapter:in_endofpacket
wire router_004_src_valid; // router_004:src_valid -> sw_reset_s_rsp_width_adapter:in_valid
wire router_004_src_startofpacket; // router_004:src_startofpacket -> sw_reset_s_rsp_width_adapter:in_startofpacket
wire [124:0] router_004_src_data; // router_004:src_data -> sw_reset_s_rsp_width_adapter:in_data
wire [6:0] router_004_src_channel; // router_004:src_channel -> sw_reset_s_rsp_width_adapter:in_channel
wire router_004_src_ready; // sw_reset_s_rsp_width_adapter:in_ready -> router_004:src_ready
wire sw_reset_s_rsp_width_adapter_src_endofpacket; // sw_reset_s_rsp_width_adapter:out_endofpacket -> rsp_demux_003:sink_endofpacket
wire sw_reset_s_rsp_width_adapter_src_valid; // sw_reset_s_rsp_width_adapter:out_valid -> rsp_demux_003:sink_valid
wire sw_reset_s_rsp_width_adapter_src_startofpacket; // sw_reset_s_rsp_width_adapter:out_startofpacket -> rsp_demux_003:sink_startofpacket
wire [88:0] sw_reset_s_rsp_width_adapter_src_data; // sw_reset_s_rsp_width_adapter:out_data -> rsp_demux_003:sink_data
wire sw_reset_s_rsp_width_adapter_src_ready; // rsp_demux_003:sink_ready -> sw_reset_s_rsp_width_adapter:out_ready
wire [6:0] sw_reset_s_rsp_width_adapter_src_channel; // sw_reset_s_rsp_width_adapter:out_channel -> rsp_demux_003:sink_channel
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> crosser:in_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> crosser:in_valid
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> crosser:in_startofpacket
wire [88:0] cmd_demux_src0_data; // cmd_demux:src0_data -> crosser:in_data
wire [6:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> crosser:in_channel
wire cmd_demux_src0_ready; // crosser:in_ready -> cmd_demux:src0_ready
wire crosser_out_endofpacket; // crosser:out_endofpacket -> cmd_mux:sink0_endofpacket
wire crosser_out_valid; // crosser:out_valid -> cmd_mux:sink0_valid
wire crosser_out_startofpacket; // crosser:out_startofpacket -> cmd_mux:sink0_startofpacket
wire [88:0] crosser_out_data; // crosser:out_data -> cmd_mux:sink0_data
wire [6:0] crosser_out_channel; // crosser:out_channel -> cmd_mux:sink0_channel
wire crosser_out_ready; // cmd_mux:sink0_ready -> crosser:out_ready
wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> crosser_001:in_endofpacket
wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> crosser_001:in_valid
wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> crosser_001:in_startofpacket
wire [88:0] cmd_demux_src1_data; // cmd_demux:src1_data -> crosser_001:in_data
wire [6:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> crosser_001:in_channel
wire cmd_demux_src1_ready; // crosser_001:in_ready -> cmd_demux:src1_ready
wire crosser_001_out_endofpacket; // crosser_001:out_endofpacket -> cmd_mux_001:sink0_endofpacket
wire crosser_001_out_valid; // crosser_001:out_valid -> cmd_mux_001:sink0_valid
wire crosser_001_out_startofpacket; // crosser_001:out_startofpacket -> cmd_mux_001:sink0_startofpacket
wire [88:0] crosser_001_out_data; // crosser_001:out_data -> cmd_mux_001:sink0_data
wire [6:0] crosser_001_out_channel; // crosser_001:out_channel -> cmd_mux_001:sink0_channel
wire crosser_001_out_ready; // cmd_mux_001:sink0_ready -> crosser_001:out_ready
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> crosser_002:in_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> crosser_002:in_valid
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> crosser_002:in_startofpacket
wire [88:0] rsp_demux_src0_data; // rsp_demux:src0_data -> crosser_002:in_data
wire [6:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> crosser_002:in_channel
wire rsp_demux_src0_ready; // crosser_002:in_ready -> rsp_demux:src0_ready
wire crosser_002_out_endofpacket; // crosser_002:out_endofpacket -> rsp_mux:sink0_endofpacket
wire crosser_002_out_valid; // crosser_002:out_valid -> rsp_mux:sink0_valid
wire crosser_002_out_startofpacket; // crosser_002:out_startofpacket -> rsp_mux:sink0_startofpacket
wire [88:0] crosser_002_out_data; // crosser_002:out_data -> rsp_mux:sink0_data
wire [6:0] crosser_002_out_channel; // crosser_002:out_channel -> rsp_mux:sink0_channel
wire crosser_002_out_ready; // rsp_mux:sink0_ready -> crosser_002:out_ready
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> crosser_003:in_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> crosser_003:in_valid
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> crosser_003:in_startofpacket
wire [88:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> crosser_003:in_data
wire [6:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> crosser_003:in_channel
wire rsp_demux_001_src0_ready; // crosser_003:in_ready -> rsp_demux_001:src0_ready
wire crosser_003_out_endofpacket; // crosser_003:out_endofpacket -> rsp_mux:sink1_endofpacket
wire crosser_003_out_valid; // crosser_003:out_valid -> rsp_mux:sink1_valid
wire crosser_003_out_startofpacket; // crosser_003:out_startofpacket -> rsp_mux:sink1_startofpacket
wire [88:0] crosser_003_out_data; // crosser_003:out_data -> rsp_mux:sink1_data
wire [6:0] crosser_003_out_channel; // crosser_003:out_channel -> rsp_mux:sink1_channel
wire crosser_003_out_ready; // rsp_mux:sink1_ready -> crosser_003:out_ready
wire [6:0] kernel_cntrl_m0_limiter_cmd_valid_data; // kernel_cntrl_m0_limiter:cmd_src_valid -> cmd_demux:sink_valid
altera_merlin_master_translator #(
.AV_ADDRESS_W (14),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) kernel_cntrl_m0_translator (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (kernel_cntrl_m0_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (kernel_cntrl_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (kernel_cntrl_m0_translator_avalon_universal_master_0_read), // .read
.uav_write (kernel_cntrl_m0_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (kernel_cntrl_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (kernel_cntrl_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (kernel_cntrl_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (kernel_cntrl_m0_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (kernel_cntrl_m0_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (kernel_cntrl_m0_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (kernel_cntrl_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (kernel_cntrl_m0_address), // avalon_anti_master_0.address
.av_waitrequest (kernel_cntrl_m0_waitrequest), // .waitrequest
.av_burstcount (kernel_cntrl_m0_burstcount), // .burstcount
.av_byteenable (kernel_cntrl_m0_byteenable), // .byteenable
.av_read (kernel_cntrl_m0_read), // .read
.av_readdata (kernel_cntrl_m0_readdata), // .readdata
.av_readdatavalid (kernel_cntrl_m0_readdatavalid), // .readdatavalid
.av_write (kernel_cntrl_m0_write), // .write
.av_writedata (kernel_cntrl_m0_writedata), // .writedata
.av_debugaccess (kernel_cntrl_m0_debugaccess), // .debugaccess
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (10),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) address_span_extender_0_windowed_slave_translator (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (address_span_extender_0_windowed_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (address_span_extender_0_windowed_slave_agent_m0_burstcount), // .burstcount
.uav_read (address_span_extender_0_windowed_slave_agent_m0_read), // .read
.uav_write (address_span_extender_0_windowed_slave_agent_m0_write), // .write
.uav_waitrequest (address_span_extender_0_windowed_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (address_span_extender_0_windowed_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (address_span_extender_0_windowed_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (address_span_extender_0_windowed_slave_agent_m0_readdata), // .readdata
.uav_writedata (address_span_extender_0_windowed_slave_agent_m0_writedata), // .writedata
.uav_lock (address_span_extender_0_windowed_slave_agent_m0_lock), // .lock
.uav_debugaccess (address_span_extender_0_windowed_slave_agent_m0_debugaccess), // .debugaccess
.av_address (address_span_extender_0_windowed_slave_address), // avalon_anti_slave_0.address
.av_write (address_span_extender_0_windowed_slave_write), // .write
.av_read (address_span_extender_0_windowed_slave_read), // .read
.av_readdata (address_span_extender_0_windowed_slave_readdata), // .readdata
.av_writedata (address_span_extender_0_windowed_slave_writedata), // .writedata
.av_burstcount (address_span_extender_0_windowed_slave_burstcount), // .burstcount
.av_byteenable (address_span_extender_0_windowed_slave_byteenable), // .byteenable
.av_readdatavalid (address_span_extender_0_windowed_slave_readdatavalid), // .readdatavalid
.av_waitrequest (address_span_extender_0_windowed_slave_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (64),
.UAV_DATA_W (64),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (8),
.UAV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (4),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) address_span_extender_0_cntl_translator (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (address_span_extender_0_cntl_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (address_span_extender_0_cntl_agent_m0_burstcount), // .burstcount
.uav_read (address_span_extender_0_cntl_agent_m0_read), // .read
.uav_write (address_span_extender_0_cntl_agent_m0_write), // .write
.uav_waitrequest (address_span_extender_0_cntl_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (address_span_extender_0_cntl_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (address_span_extender_0_cntl_agent_m0_byteenable), // .byteenable
.uav_readdata (address_span_extender_0_cntl_agent_m0_readdata), // .readdata
.uav_writedata (address_span_extender_0_cntl_agent_m0_writedata), // .writedata
.uav_lock (address_span_extender_0_cntl_agent_m0_lock), // .lock
.uav_debugaccess (address_span_extender_0_cntl_agent_m0_debugaccess), // .debugaccess
.av_write (address_span_extender_0_cntl_write), // avalon_anti_slave_0.write
.av_read (address_span_extender_0_cntl_read), // .read
.av_readdata (address_span_extender_0_cntl_readdata), // .readdata
.av_writedata (address_span_extender_0_cntl_writedata), // .writedata
.av_byteenable (address_span_extender_0_cntl_byteenable), // .byteenable
.av_address (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (64),
.UAV_DATA_W (64),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (8),
.UAV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (4),
.AV_READLATENCY (2),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sys_description_rom_s1_translator (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sys_description_rom_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sys_description_rom_s1_agent_m0_burstcount), // .burstcount
.uav_read (sys_description_rom_s1_agent_m0_read), // .read
.uav_write (sys_description_rom_s1_agent_m0_write), // .write
.uav_waitrequest (sys_description_rom_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sys_description_rom_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sys_description_rom_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (sys_description_rom_s1_agent_m0_readdata), // .readdata
.uav_writedata (sys_description_rom_s1_agent_m0_writedata), // .writedata
.uav_lock (sys_description_rom_s1_agent_m0_lock), // .lock
.uav_debugaccess (sys_description_rom_s1_agent_m0_debugaccess), // .debugaccess
.av_address (sys_description_rom_s1_address), // avalon_anti_slave_0.address
.av_write (sys_description_rom_s1_write), // .write
.av_readdata (sys_description_rom_s1_readdata), // .readdata
.av_writedata (sys_description_rom_s1_writedata), // .writedata
.av_byteenable (sys_description_rom_s1_byteenable), // .byteenable
.av_chipselect (sys_description_rom_s1_chipselect), // .chipselect
.av_clken (sys_description_rom_s1_clken), // .clken
.av_debugaccess (sys_description_rom_s1_debugaccess), // .debugaccess
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (64),
.UAV_DATA_W (64),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (8),
.UAV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (4),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sw_reset_s_translator (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sw_reset_s_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sw_reset_s_agent_m0_burstcount), // .burstcount
.uav_read (sw_reset_s_agent_m0_read), // .read
.uav_write (sw_reset_s_agent_m0_write), // .write
.uav_waitrequest (sw_reset_s_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sw_reset_s_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sw_reset_s_agent_m0_byteenable), // .byteenable
.uav_readdata (sw_reset_s_agent_m0_readdata), // .readdata
.uav_writedata (sw_reset_s_agent_m0_writedata), // .writedata
.uav_lock (sw_reset_s_agent_m0_lock), // .lock
.uav_debugaccess (sw_reset_s_agent_m0_debugaccess), // .debugaccess
.av_write (sw_reset_s_write), // avalon_anti_slave_0.write
.av_read (sw_reset_s_read), // .read
.av_readdata (sw_reset_s_readdata), // .readdata
.av_writedata (sw_reset_s_writedata), // .writedata
.av_byteenable (sw_reset_s_byteenable), // .byteenable
.av_waitrequest (sw_reset_s_waitrequest), // .waitrequest
.av_address (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) mem_org_mode_s_translator (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (mem_org_mode_s_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (mem_org_mode_s_agent_m0_burstcount), // .burstcount
.uav_read (mem_org_mode_s_agent_m0_read), // .read
.uav_write (mem_org_mode_s_agent_m0_write), // .write
.uav_waitrequest (mem_org_mode_s_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (mem_org_mode_s_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (mem_org_mode_s_agent_m0_byteenable), // .byteenable
.uav_readdata (mem_org_mode_s_agent_m0_readdata), // .readdata
.uav_writedata (mem_org_mode_s_agent_m0_writedata), // .writedata
.uav_lock (mem_org_mode_s_agent_m0_lock), // .lock
.uav_debugaccess (mem_org_mode_s_agent_m0_debugaccess), // .debugaccess
.av_write (mem_org_mode_s_write), // avalon_anti_slave_0.write
.av_read (mem_org_mode_s_read), // .read
.av_readdata (mem_org_mode_s_readdata), // .readdata
.av_writedata (mem_org_mode_s_writedata), // .writedata
.av_waitrequest (mem_org_mode_s_waitrequest), // .waitrequest
.av_address (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) version_id_0_s_translator (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (version_id_0_s_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (version_id_0_s_agent_m0_burstcount), // .burstcount
.uav_read (version_id_0_s_agent_m0_read), // .read
.uav_write (version_id_0_s_agent_m0_write), // .write
.uav_waitrequest (version_id_0_s_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (version_id_0_s_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (version_id_0_s_agent_m0_byteenable), // .byteenable
.uav_readdata (version_id_0_s_agent_m0_readdata), // .readdata
.uav_writedata (version_id_0_s_agent_m0_writedata), // .writedata
.uav_lock (version_id_0_s_agent_m0_lock), // .lock
.uav_debugaccess (version_id_0_s_agent_m0_debugaccess), // .debugaccess
.av_read (version_id_0_s_read), // avalon_anti_slave_0.read
.av_readdata (version_id_0_s_readdata), // .readdata
.av_address (), // (terminated)
.av_write (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) irq_ena_0_s_translator (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (irq_ena_0_s_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (irq_ena_0_s_agent_m0_burstcount), // .burstcount
.uav_read (irq_ena_0_s_agent_m0_read), // .read
.uav_write (irq_ena_0_s_agent_m0_write), // .write
.uav_waitrequest (irq_ena_0_s_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (irq_ena_0_s_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (irq_ena_0_s_agent_m0_byteenable), // .byteenable
.uav_readdata (irq_ena_0_s_agent_m0_readdata), // .readdata
.uav_writedata (irq_ena_0_s_agent_m0_writedata), // .writedata
.uav_lock (irq_ena_0_s_agent_m0_lock), // .lock
.uav_debugaccess (irq_ena_0_s_agent_m0_debugaccess), // .debugaccess
.av_write (irq_ena_0_s_write), // avalon_anti_slave_0.write
.av_read (irq_ena_0_s_read), // .read
.av_readdata (irq_ena_0_s_readdata), // .readdata
.av_writedata (irq_ena_0_s_writedata), // .writedata
.av_byteenable (irq_ena_0_s_byteenable), // .byteenable
.av_waitrequest (irq_ena_0_s_waitrequest), // .waitrequest
.av_address (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (79),
.PKT_PROTECTION_L (77),
.PKT_BEGIN_BURST (68),
.PKT_BURSTWRAP_H (60),
.PKT_BURSTWRAP_L (60),
.PKT_BURST_SIZE_H (63),
.PKT_BURST_SIZE_L (61),
.PKT_BURST_TYPE_H (65),
.PKT_BURST_TYPE_L (64),
.PKT_BYTE_CNT_H (59),
.PKT_BYTE_CNT_L (56),
.PKT_ADDR_H (49),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_TRANS_LOCK (54),
.PKT_TRANS_EXCLUSIVE (55),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (70),
.PKT_DEST_ID_H (75),
.PKT_DEST_ID_L (73),
.PKT_THREAD_ID_H (76),
.PKT_THREAD_ID_L (76),
.PKT_CACHE_H (83),
.PKT_CACHE_L (80),
.PKT_DATA_SIDEBAND_H (67),
.PKT_DATA_SIDEBAND_L (67),
.PKT_QOS_H (69),
.PKT_QOS_L (69),
.PKT_ADDR_SIDEBAND_H (66),
.PKT_ADDR_SIDEBAND_L (66),
.PKT_RESPONSE_STATUS_H (85),
.PKT_RESPONSE_STATUS_L (84),
.PKT_ORI_BURST_SIZE_L (86),
.PKT_ORI_BURST_SIZE_H (88),
.ST_DATA_W (89),
.ST_CHANNEL_W (7),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (1),
.ID (0),
.BURSTWRAP_VALUE (1),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) kernel_cntrl_m0_agent (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (kernel_cntrl_m0_translator_avalon_universal_master_0_address), // av.address
.av_write (kernel_cntrl_m0_translator_avalon_universal_master_0_write), // .write
.av_read (kernel_cntrl_m0_translator_avalon_universal_master_0_read), // .read
.av_writedata (kernel_cntrl_m0_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (kernel_cntrl_m0_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (kernel_cntrl_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (kernel_cntrl_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (kernel_cntrl_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (kernel_cntrl_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (kernel_cntrl_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (kernel_cntrl_m0_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (kernel_cntrl_m0_agent_cp_valid), // cp.valid
.cp_data (kernel_cntrl_m0_agent_cp_data), // .data
.cp_startofpacket (kernel_cntrl_m0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (kernel_cntrl_m0_agent_cp_endofpacket), // .endofpacket
.cp_ready (kernel_cntrl_m0_agent_cp_ready), // .ready
.rp_valid (kernel_cntrl_m0_limiter_rsp_src_valid), // rp.valid
.rp_data (kernel_cntrl_m0_limiter_rsp_src_data), // .data
.rp_channel (kernel_cntrl_m0_limiter_rsp_src_channel), // .channel
.rp_startofpacket (kernel_cntrl_m0_limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (kernel_cntrl_m0_limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (kernel_cntrl_m0_limiter_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (68),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (49),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_TRANS_LOCK (54),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (70),
.PKT_DEST_ID_H (75),
.PKT_DEST_ID_L (73),
.PKT_BURSTWRAP_H (60),
.PKT_BURSTWRAP_L (60),
.PKT_BYTE_CNT_H (59),
.PKT_BYTE_CNT_L (56),
.PKT_PROTECTION_H (79),
.PKT_PROTECTION_L (77),
.PKT_RESPONSE_STATUS_H (85),
.PKT_RESPONSE_STATUS_L (84),
.PKT_BURST_SIZE_H (63),
.PKT_BURST_SIZE_L (61),
.PKT_ORI_BURST_SIZE_L (86),
.PKT_ORI_BURST_SIZE_H (88),
.ST_CHANNEL_W (7),
.ST_DATA_W (89),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) address_span_extender_0_windowed_slave_agent (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (address_span_extender_0_windowed_slave_agent_m0_address), // m0.address
.m0_burstcount (address_span_extender_0_windowed_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (address_span_extender_0_windowed_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (address_span_extender_0_windowed_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (address_span_extender_0_windowed_slave_agent_m0_lock), // .lock
.m0_readdata (address_span_extender_0_windowed_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (address_span_extender_0_windowed_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (address_span_extender_0_windowed_slave_agent_m0_read), // .read
.m0_waitrequest (address_span_extender_0_windowed_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (address_span_extender_0_windowed_slave_agent_m0_writedata), // .writedata
.m0_write (address_span_extender_0_windowed_slave_agent_m0_write), // .write
.rp_endofpacket (address_span_extender_0_windowed_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (address_span_extender_0_windowed_slave_agent_rp_ready), // .ready
.rp_valid (address_span_extender_0_windowed_slave_agent_rp_valid), // .valid
.rp_data (address_span_extender_0_windowed_slave_agent_rp_data), // .data
.rp_startofpacket (address_span_extender_0_windowed_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_src_ready), // cp.ready
.cp_valid (cmd_mux_src_valid), // .valid
.cp_data (cmd_mux_src_data), // .data
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_src_channel), // .channel
.rf_sink_ready (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (address_span_extender_0_windowed_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (address_span_extender_0_windowed_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (address_span_extender_0_windowed_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (address_span_extender_0_windowed_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (address_span_extender_0_windowed_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (address_span_extender_0_windowed_slave_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (address_span_extender_0_windowed_slave_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (address_span_extender_0_windowed_slave_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (address_span_extender_0_windowed_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (address_span_extender_0_windowed_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (address_span_extender_0_windowed_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (90),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) address_span_extender_0_windowed_slave_agent_rsp_fifo (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (address_span_extender_0_windowed_slave_agent_rf_source_data), // in.data
.in_valid (address_span_extender_0_windowed_slave_agent_rf_source_valid), // .valid
.in_ready (address_span_extender_0_windowed_slave_agent_rf_source_ready), // .ready
.in_startofpacket (address_span_extender_0_windowed_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (address_span_extender_0_windowed_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) address_span_extender_0_windowed_slave_agent_rdata_fifo (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (address_span_extender_0_windowed_slave_agent_rdata_fifo_src_data), // in.data
.in_valid (address_span_extender_0_windowed_slave_agent_rdata_fifo_src_valid), // .valid
.in_ready (address_span_extender_0_windowed_slave_agent_rdata_fifo_src_ready), // .ready
.out_data (address_span_extender_0_windowed_slave_agent_rdata_fifo_out_data), // out.data
.out_valid (address_span_extender_0_windowed_slave_agent_rdata_fifo_out_valid), // .valid
.out_ready (address_span_extender_0_windowed_slave_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (63),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (104),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (71),
.PKT_BYTEEN_L (64),
.PKT_ADDR_H (85),
.PKT_ADDR_L (72),
.PKT_TRANS_COMPRESSED_READ (86),
.PKT_TRANS_POSTED (87),
.PKT_TRANS_WRITE (88),
.PKT_TRANS_READ (89),
.PKT_TRANS_LOCK (90),
.PKT_SRC_ID_H (108),
.PKT_SRC_ID_L (106),
.PKT_DEST_ID_H (111),
.PKT_DEST_ID_L (109),
.PKT_BURSTWRAP_H (96),
.PKT_BURSTWRAP_L (96),
.PKT_BYTE_CNT_H (95),
.PKT_BYTE_CNT_L (92),
.PKT_PROTECTION_H (115),
.PKT_PROTECTION_L (113),
.PKT_RESPONSE_STATUS_H (121),
.PKT_RESPONSE_STATUS_L (120),
.PKT_BURST_SIZE_H (99),
.PKT_BURST_SIZE_L (97),
.PKT_ORI_BURST_SIZE_L (122),
.PKT_ORI_BURST_SIZE_H (124),
.ST_CHANNEL_W (7),
.ST_DATA_W (125),
.AVS_BURSTCOUNT_W (4),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) address_span_extender_0_cntl_agent (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (address_span_extender_0_cntl_agent_m0_address), // m0.address
.m0_burstcount (address_span_extender_0_cntl_agent_m0_burstcount), // .burstcount
.m0_byteenable (address_span_extender_0_cntl_agent_m0_byteenable), // .byteenable
.m0_debugaccess (address_span_extender_0_cntl_agent_m0_debugaccess), // .debugaccess
.m0_lock (address_span_extender_0_cntl_agent_m0_lock), // .lock
.m0_readdata (address_span_extender_0_cntl_agent_m0_readdata), // .readdata
.m0_readdatavalid (address_span_extender_0_cntl_agent_m0_readdatavalid), // .readdatavalid
.m0_read (address_span_extender_0_cntl_agent_m0_read), // .read
.m0_waitrequest (address_span_extender_0_cntl_agent_m0_waitrequest), // .waitrequest
.m0_writedata (address_span_extender_0_cntl_agent_m0_writedata), // .writedata
.m0_write (address_span_extender_0_cntl_agent_m0_write), // .write
.rp_endofpacket (address_span_extender_0_cntl_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (address_span_extender_0_cntl_agent_rp_ready), // .ready
.rp_valid (address_span_extender_0_cntl_agent_rp_valid), // .valid
.rp_data (address_span_extender_0_cntl_agent_rp_data), // .data
.rp_startofpacket (address_span_extender_0_cntl_agent_rp_startofpacket), // .startofpacket
.cp_ready (address_span_extender_0_cntl_cmd_width_adapter_src_ready), // cp.ready
.cp_valid (address_span_extender_0_cntl_cmd_width_adapter_src_valid), // .valid
.cp_data (address_span_extender_0_cntl_cmd_width_adapter_src_data), // .data
.cp_startofpacket (address_span_extender_0_cntl_cmd_width_adapter_src_startofpacket), // .startofpacket
.cp_endofpacket (address_span_extender_0_cntl_cmd_width_adapter_src_endofpacket), // .endofpacket
.cp_channel (address_span_extender_0_cntl_cmd_width_adapter_src_channel), // .channel
.rf_sink_ready (address_span_extender_0_cntl_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (address_span_extender_0_cntl_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (address_span_extender_0_cntl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (address_span_extender_0_cntl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (address_span_extender_0_cntl_agent_rsp_fifo_out_data), // .data
.rf_source_ready (address_span_extender_0_cntl_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (address_span_extender_0_cntl_agent_rf_source_valid), // .valid
.rf_source_startofpacket (address_span_extender_0_cntl_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (address_span_extender_0_cntl_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (address_span_extender_0_cntl_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (address_span_extender_0_cntl_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (address_span_extender_0_cntl_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (address_span_extender_0_cntl_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (address_span_extender_0_cntl_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (address_span_extender_0_cntl_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (address_span_extender_0_cntl_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (126),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) address_span_extender_0_cntl_agent_rsp_fifo (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (address_span_extender_0_cntl_agent_rf_source_data), // in.data
.in_valid (address_span_extender_0_cntl_agent_rf_source_valid), // .valid
.in_ready (address_span_extender_0_cntl_agent_rf_source_ready), // .ready
.in_startofpacket (address_span_extender_0_cntl_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (address_span_extender_0_cntl_agent_rf_source_endofpacket), // .endofpacket
.out_data (address_span_extender_0_cntl_agent_rsp_fifo_out_data), // out.data
.out_valid (address_span_extender_0_cntl_agent_rsp_fifo_out_valid), // .valid
.out_ready (address_span_extender_0_cntl_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (address_span_extender_0_cntl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (address_span_extender_0_cntl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (66),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) address_span_extender_0_cntl_agent_rdata_fifo (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (address_span_extender_0_cntl_agent_rdata_fifo_src_data), // in.data
.in_valid (address_span_extender_0_cntl_agent_rdata_fifo_src_valid), // .valid
.in_ready (address_span_extender_0_cntl_agent_rdata_fifo_src_ready), // .ready
.out_data (address_span_extender_0_cntl_agent_rdata_fifo_out_data), // out.data
.out_valid (address_span_extender_0_cntl_agent_rdata_fifo_out_valid), // .valid
.out_ready (address_span_extender_0_cntl_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (63),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (104),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (71),
.PKT_BYTEEN_L (64),
.PKT_ADDR_H (85),
.PKT_ADDR_L (72),
.PKT_TRANS_COMPRESSED_READ (86),
.PKT_TRANS_POSTED (87),
.PKT_TRANS_WRITE (88),
.PKT_TRANS_READ (89),
.PKT_TRANS_LOCK (90),
.PKT_SRC_ID_H (108),
.PKT_SRC_ID_L (106),
.PKT_DEST_ID_H (111),
.PKT_DEST_ID_L (109),
.PKT_BURSTWRAP_H (96),
.PKT_BURSTWRAP_L (96),
.PKT_BYTE_CNT_H (95),
.PKT_BYTE_CNT_L (92),
.PKT_PROTECTION_H (115),
.PKT_PROTECTION_L (113),
.PKT_RESPONSE_STATUS_H (121),
.PKT_RESPONSE_STATUS_L (120),
.PKT_BURST_SIZE_H (99),
.PKT_BURST_SIZE_L (97),
.PKT_ORI_BURST_SIZE_L (122),
.PKT_ORI_BURST_SIZE_H (124),
.ST_CHANNEL_W (7),
.ST_DATA_W (125),
.AVS_BURSTCOUNT_W (4),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sys_description_rom_s1_agent (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sys_description_rom_s1_agent_m0_address), // m0.address
.m0_burstcount (sys_description_rom_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (sys_description_rom_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sys_description_rom_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (sys_description_rom_s1_agent_m0_lock), // .lock
.m0_readdata (sys_description_rom_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (sys_description_rom_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sys_description_rom_s1_agent_m0_read), // .read
.m0_waitrequest (sys_description_rom_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sys_description_rom_s1_agent_m0_writedata), // .writedata
.m0_write (sys_description_rom_s1_agent_m0_write), // .write
.rp_endofpacket (sys_description_rom_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sys_description_rom_s1_agent_rp_ready), // .ready
.rp_valid (sys_description_rom_s1_agent_rp_valid), // .valid
.rp_data (sys_description_rom_s1_agent_rp_data), // .data
.rp_startofpacket (sys_description_rom_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (sys_description_rom_s1_cmd_width_adapter_src_ready), // cp.ready
.cp_valid (sys_description_rom_s1_cmd_width_adapter_src_valid), // .valid
.cp_data (sys_description_rom_s1_cmd_width_adapter_src_data), // .data
.cp_startofpacket (sys_description_rom_s1_cmd_width_adapter_src_startofpacket), // .startofpacket
.cp_endofpacket (sys_description_rom_s1_cmd_width_adapter_src_endofpacket), // .endofpacket
.cp_channel (sys_description_rom_s1_cmd_width_adapter_src_channel), // .channel
.rf_sink_ready (sys_description_rom_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sys_description_rom_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sys_description_rom_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sys_description_rom_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sys_description_rom_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sys_description_rom_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sys_description_rom_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sys_description_rom_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sys_description_rom_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sys_description_rom_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sys_description_rom_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sys_description_rom_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sys_description_rom_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sys_description_rom_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sys_description_rom_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sys_description_rom_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (126),
.FIFO_DEPTH (3),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sys_description_rom_s1_agent_rsp_fifo (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sys_description_rom_s1_agent_rf_source_data), // in.data
.in_valid (sys_description_rom_s1_agent_rf_source_valid), // .valid
.in_ready (sys_description_rom_s1_agent_rf_source_ready), // .ready
.in_startofpacket (sys_description_rom_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sys_description_rom_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (sys_description_rom_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (sys_description_rom_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (sys_description_rom_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sys_description_rom_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sys_description_rom_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (63),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (104),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (71),
.PKT_BYTEEN_L (64),
.PKT_ADDR_H (85),
.PKT_ADDR_L (72),
.PKT_TRANS_COMPRESSED_READ (86),
.PKT_TRANS_POSTED (87),
.PKT_TRANS_WRITE (88),
.PKT_TRANS_READ (89),
.PKT_TRANS_LOCK (90),
.PKT_SRC_ID_H (108),
.PKT_SRC_ID_L (106),
.PKT_DEST_ID_H (111),
.PKT_DEST_ID_L (109),
.PKT_BURSTWRAP_H (96),
.PKT_BURSTWRAP_L (96),
.PKT_BYTE_CNT_H (95),
.PKT_BYTE_CNT_L (92),
.PKT_PROTECTION_H (115),
.PKT_PROTECTION_L (113),
.PKT_RESPONSE_STATUS_H (121),
.PKT_RESPONSE_STATUS_L (120),
.PKT_BURST_SIZE_H (99),
.PKT_BURST_SIZE_L (97),
.PKT_ORI_BURST_SIZE_L (122),
.PKT_ORI_BURST_SIZE_H (124),
.ST_CHANNEL_W (7),
.ST_DATA_W (125),
.AVS_BURSTCOUNT_W (4),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sw_reset_s_agent (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sw_reset_s_agent_m0_address), // m0.address
.m0_burstcount (sw_reset_s_agent_m0_burstcount), // .burstcount
.m0_byteenable (sw_reset_s_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sw_reset_s_agent_m0_debugaccess), // .debugaccess
.m0_lock (sw_reset_s_agent_m0_lock), // .lock
.m0_readdata (sw_reset_s_agent_m0_readdata), // .readdata
.m0_readdatavalid (sw_reset_s_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sw_reset_s_agent_m0_read), // .read
.m0_waitrequest (sw_reset_s_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sw_reset_s_agent_m0_writedata), // .writedata
.m0_write (sw_reset_s_agent_m0_write), // .write
.rp_endofpacket (sw_reset_s_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sw_reset_s_agent_rp_ready), // .ready
.rp_valid (sw_reset_s_agent_rp_valid), // .valid
.rp_data (sw_reset_s_agent_rp_data), // .data
.rp_startofpacket (sw_reset_s_agent_rp_startofpacket), // .startofpacket
.cp_ready (sw_reset_s_cmd_width_adapter_src_ready), // cp.ready
.cp_valid (sw_reset_s_cmd_width_adapter_src_valid), // .valid
.cp_data (sw_reset_s_cmd_width_adapter_src_data), // .data
.cp_startofpacket (sw_reset_s_cmd_width_adapter_src_startofpacket), // .startofpacket
.cp_endofpacket (sw_reset_s_cmd_width_adapter_src_endofpacket), // .endofpacket
.cp_channel (sw_reset_s_cmd_width_adapter_src_channel), // .channel
.rf_sink_ready (sw_reset_s_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sw_reset_s_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sw_reset_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sw_reset_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sw_reset_s_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sw_reset_s_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sw_reset_s_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sw_reset_s_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sw_reset_s_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sw_reset_s_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sw_reset_s_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sw_reset_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sw_reset_s_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sw_reset_s_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sw_reset_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sw_reset_s_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (126),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sw_reset_s_agent_rsp_fifo (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sw_reset_s_agent_rf_source_data), // in.data
.in_valid (sw_reset_s_agent_rf_source_valid), // .valid
.in_ready (sw_reset_s_agent_rf_source_ready), // .ready
.in_startofpacket (sw_reset_s_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sw_reset_s_agent_rf_source_endofpacket), // .endofpacket
.out_data (sw_reset_s_agent_rsp_fifo_out_data), // out.data
.out_valid (sw_reset_s_agent_rsp_fifo_out_valid), // .valid
.out_ready (sw_reset_s_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sw_reset_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sw_reset_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (68),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (49),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_TRANS_LOCK (54),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (70),
.PKT_DEST_ID_H (75),
.PKT_DEST_ID_L (73),
.PKT_BURSTWRAP_H (60),
.PKT_BURSTWRAP_L (60),
.PKT_BYTE_CNT_H (59),
.PKT_BYTE_CNT_L (56),
.PKT_PROTECTION_H (79),
.PKT_PROTECTION_L (77),
.PKT_RESPONSE_STATUS_H (85),
.PKT_RESPONSE_STATUS_L (84),
.PKT_BURST_SIZE_H (63),
.PKT_BURST_SIZE_L (61),
.PKT_ORI_BURST_SIZE_L (86),
.PKT_ORI_BURST_SIZE_H (88),
.ST_CHANNEL_W (7),
.ST_DATA_W (89),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) mem_org_mode_s_agent (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (mem_org_mode_s_agent_m0_address), // m0.address
.m0_burstcount (mem_org_mode_s_agent_m0_burstcount), // .burstcount
.m0_byteenable (mem_org_mode_s_agent_m0_byteenable), // .byteenable
.m0_debugaccess (mem_org_mode_s_agent_m0_debugaccess), // .debugaccess
.m0_lock (mem_org_mode_s_agent_m0_lock), // .lock
.m0_readdata (mem_org_mode_s_agent_m0_readdata), // .readdata
.m0_readdatavalid (mem_org_mode_s_agent_m0_readdatavalid), // .readdatavalid
.m0_read (mem_org_mode_s_agent_m0_read), // .read
.m0_waitrequest (mem_org_mode_s_agent_m0_waitrequest), // .waitrequest
.m0_writedata (mem_org_mode_s_agent_m0_writedata), // .writedata
.m0_write (mem_org_mode_s_agent_m0_write), // .write
.rp_endofpacket (mem_org_mode_s_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (mem_org_mode_s_agent_rp_ready), // .ready
.rp_valid (mem_org_mode_s_agent_rp_valid), // .valid
.rp_data (mem_org_mode_s_agent_rp_data), // .data
.rp_startofpacket (mem_org_mode_s_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_004_src_ready), // cp.ready
.cp_valid (cmd_mux_004_src_valid), // .valid
.cp_data (cmd_mux_004_src_data), // .data
.cp_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_004_src_channel), // .channel
.rf_sink_ready (mem_org_mode_s_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (mem_org_mode_s_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (mem_org_mode_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (mem_org_mode_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (mem_org_mode_s_agent_rsp_fifo_out_data), // .data
.rf_source_ready (mem_org_mode_s_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (mem_org_mode_s_agent_rf_source_valid), // .valid
.rf_source_startofpacket (mem_org_mode_s_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (mem_org_mode_s_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (mem_org_mode_s_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (mem_org_mode_s_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (mem_org_mode_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (mem_org_mode_s_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (mem_org_mode_s_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (mem_org_mode_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (mem_org_mode_s_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (90),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) mem_org_mode_s_agent_rsp_fifo (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (mem_org_mode_s_agent_rf_source_data), // in.data
.in_valid (mem_org_mode_s_agent_rf_source_valid), // .valid
.in_ready (mem_org_mode_s_agent_rf_source_ready), // .ready
.in_startofpacket (mem_org_mode_s_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (mem_org_mode_s_agent_rf_source_endofpacket), // .endofpacket
.out_data (mem_org_mode_s_agent_rsp_fifo_out_data), // out.data
.out_valid (mem_org_mode_s_agent_rsp_fifo_out_valid), // .valid
.out_ready (mem_org_mode_s_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (mem_org_mode_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (mem_org_mode_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (68),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (49),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_TRANS_LOCK (54),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (70),
.PKT_DEST_ID_H (75),
.PKT_DEST_ID_L (73),
.PKT_BURSTWRAP_H (60),
.PKT_BURSTWRAP_L (60),
.PKT_BYTE_CNT_H (59),
.PKT_BYTE_CNT_L (56),
.PKT_PROTECTION_H (79),
.PKT_PROTECTION_L (77),
.PKT_RESPONSE_STATUS_H (85),
.PKT_RESPONSE_STATUS_L (84),
.PKT_BURST_SIZE_H (63),
.PKT_BURST_SIZE_L (61),
.PKT_ORI_BURST_SIZE_L (86),
.PKT_ORI_BURST_SIZE_H (88),
.ST_CHANNEL_W (7),
.ST_DATA_W (89),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) version_id_0_s_agent (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (version_id_0_s_agent_m0_address), // m0.address
.m0_burstcount (version_id_0_s_agent_m0_burstcount), // .burstcount
.m0_byteenable (version_id_0_s_agent_m0_byteenable), // .byteenable
.m0_debugaccess (version_id_0_s_agent_m0_debugaccess), // .debugaccess
.m0_lock (version_id_0_s_agent_m0_lock), // .lock
.m0_readdata (version_id_0_s_agent_m0_readdata), // .readdata
.m0_readdatavalid (version_id_0_s_agent_m0_readdatavalid), // .readdatavalid
.m0_read (version_id_0_s_agent_m0_read), // .read
.m0_waitrequest (version_id_0_s_agent_m0_waitrequest), // .waitrequest
.m0_writedata (version_id_0_s_agent_m0_writedata), // .writedata
.m0_write (version_id_0_s_agent_m0_write), // .write
.rp_endofpacket (version_id_0_s_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (version_id_0_s_agent_rp_ready), // .ready
.rp_valid (version_id_0_s_agent_rp_valid), // .valid
.rp_data (version_id_0_s_agent_rp_data), // .data
.rp_startofpacket (version_id_0_s_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_005_src_ready), // cp.ready
.cp_valid (cmd_mux_005_src_valid), // .valid
.cp_data (cmd_mux_005_src_data), // .data
.cp_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_005_src_channel), // .channel
.rf_sink_ready (version_id_0_s_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (version_id_0_s_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (version_id_0_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (version_id_0_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (version_id_0_s_agent_rsp_fifo_out_data), // .data
.rf_source_ready (version_id_0_s_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (version_id_0_s_agent_rf_source_valid), // .valid
.rf_source_startofpacket (version_id_0_s_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (version_id_0_s_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (version_id_0_s_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (version_id_0_s_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (version_id_0_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (version_id_0_s_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (version_id_0_s_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (version_id_0_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (version_id_0_s_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (90),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) version_id_0_s_agent_rsp_fifo (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (version_id_0_s_agent_rf_source_data), // in.data
.in_valid (version_id_0_s_agent_rf_source_valid), // .valid
.in_ready (version_id_0_s_agent_rf_source_ready), // .ready
.in_startofpacket (version_id_0_s_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (version_id_0_s_agent_rf_source_endofpacket), // .endofpacket
.out_data (version_id_0_s_agent_rsp_fifo_out_data), // out.data
.out_valid (version_id_0_s_agent_rsp_fifo_out_valid), // .valid
.out_ready (version_id_0_s_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (version_id_0_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (version_id_0_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (68),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (49),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_TRANS_LOCK (54),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (70),
.PKT_DEST_ID_H (75),
.PKT_DEST_ID_L (73),
.PKT_BURSTWRAP_H (60),
.PKT_BURSTWRAP_L (60),
.PKT_BYTE_CNT_H (59),
.PKT_BYTE_CNT_L (56),
.PKT_PROTECTION_H (79),
.PKT_PROTECTION_L (77),
.PKT_RESPONSE_STATUS_H (85),
.PKT_RESPONSE_STATUS_L (84),
.PKT_BURST_SIZE_H (63),
.PKT_BURST_SIZE_L (61),
.PKT_ORI_BURST_SIZE_L (86),
.PKT_ORI_BURST_SIZE_H (88),
.ST_CHANNEL_W (7),
.ST_DATA_W (89),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) irq_ena_0_s_agent (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (irq_ena_0_s_agent_m0_address), // m0.address
.m0_burstcount (irq_ena_0_s_agent_m0_burstcount), // .burstcount
.m0_byteenable (irq_ena_0_s_agent_m0_byteenable), // .byteenable
.m0_debugaccess (irq_ena_0_s_agent_m0_debugaccess), // .debugaccess
.m0_lock (irq_ena_0_s_agent_m0_lock), // .lock
.m0_readdata (irq_ena_0_s_agent_m0_readdata), // .readdata
.m0_readdatavalid (irq_ena_0_s_agent_m0_readdatavalid), // .readdatavalid
.m0_read (irq_ena_0_s_agent_m0_read), // .read
.m0_waitrequest (irq_ena_0_s_agent_m0_waitrequest), // .waitrequest
.m0_writedata (irq_ena_0_s_agent_m0_writedata), // .writedata
.m0_write (irq_ena_0_s_agent_m0_write), // .write
.rp_endofpacket (irq_ena_0_s_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (irq_ena_0_s_agent_rp_ready), // .ready
.rp_valid (irq_ena_0_s_agent_rp_valid), // .valid
.rp_data (irq_ena_0_s_agent_rp_data), // .data
.rp_startofpacket (irq_ena_0_s_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_006_src_ready), // cp.ready
.cp_valid (cmd_mux_006_src_valid), // .valid
.cp_data (cmd_mux_006_src_data), // .data
.cp_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_006_src_channel), // .channel
.rf_sink_ready (irq_ena_0_s_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (irq_ena_0_s_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (irq_ena_0_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (irq_ena_0_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (irq_ena_0_s_agent_rsp_fifo_out_data), // .data
.rf_source_ready (irq_ena_0_s_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (irq_ena_0_s_agent_rf_source_valid), // .valid
.rf_source_startofpacket (irq_ena_0_s_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (irq_ena_0_s_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (irq_ena_0_s_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (irq_ena_0_s_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (irq_ena_0_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (irq_ena_0_s_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (irq_ena_0_s_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (irq_ena_0_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (irq_ena_0_s_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (90),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) irq_ena_0_s_agent_rsp_fifo (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (irq_ena_0_s_agent_rf_source_data), // in.data
.in_valid (irq_ena_0_s_agent_rf_source_valid), // .valid
.in_ready (irq_ena_0_s_agent_rf_source_ready), // .ready
.in_startofpacket (irq_ena_0_s_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (irq_ena_0_s_agent_rf_source_endofpacket), // .endofpacket
.out_data (irq_ena_0_s_agent_rsp_fifo_out_data), // out.data
.out_valid (irq_ena_0_s_agent_rsp_fifo_out_valid), // .valid
.out_ready (irq_ena_0_s_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (irq_ena_0_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (irq_ena_0_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router router (
.sink_ready (kernel_cntrl_m0_agent_cp_ready), // sink.ready
.sink_valid (kernel_cntrl_m0_agent_cp_valid), // .valid
.sink_data (kernel_cntrl_m0_agent_cp_data), // .data
.sink_startofpacket (kernel_cntrl_m0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (kernel_cntrl_m0_agent_cp_endofpacket), // .endofpacket
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_001 router_001 (
.sink_ready (address_span_extender_0_windowed_slave_agent_rp_ready), // sink.ready
.sink_valid (address_span_extender_0_windowed_slave_agent_rp_valid), // .valid
.sink_data (address_span_extender_0_windowed_slave_agent_rp_data), // .data
.sink_startofpacket (address_span_extender_0_windowed_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (address_span_extender_0_windowed_slave_agent_rp_endofpacket), // .endofpacket
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_002 router_002 (
.sink_ready (address_span_extender_0_cntl_agent_rp_ready), // sink.ready
.sink_valid (address_span_extender_0_cntl_agent_rp_valid), // .valid
.sink_data (address_span_extender_0_cntl_agent_rp_data), // .data
.sink_startofpacket (address_span_extender_0_cntl_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (address_span_extender_0_cntl_agent_rp_endofpacket), // .endofpacket
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_003 router_003 (
.sink_ready (sys_description_rom_s1_agent_rp_ready), // sink.ready
.sink_valid (sys_description_rom_s1_agent_rp_valid), // .valid
.sink_data (sys_description_rom_s1_agent_rp_data), // .data
.sink_startofpacket (sys_description_rom_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sys_description_rom_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_003 router_004 (
.sink_ready (sw_reset_s_agent_rp_ready), // sink.ready
.sink_valid (sw_reset_s_agent_rp_valid), // .valid
.sink_data (sw_reset_s_agent_rp_data), // .data
.sink_startofpacket (sw_reset_s_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sw_reset_s_agent_rp_endofpacket), // .endofpacket
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_005 router_005 (
.sink_ready (mem_org_mode_s_agent_rp_ready), // sink.ready
.sink_valid (mem_org_mode_s_agent_rp_valid), // .valid
.sink_data (mem_org_mode_s_agent_rp_data), // .data
.sink_startofpacket (mem_org_mode_s_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (mem_org_mode_s_agent_rp_endofpacket), // .endofpacket
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_005_src_ready), // src.ready
.src_valid (router_005_src_valid), // .valid
.src_data (router_005_src_data), // .data
.src_channel (router_005_src_channel), // .channel
.src_startofpacket (router_005_src_startofpacket), // .startofpacket
.src_endofpacket (router_005_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_005 router_006 (
.sink_ready (version_id_0_s_agent_rp_ready), // sink.ready
.sink_valid (version_id_0_s_agent_rp_valid), // .valid
.sink_data (version_id_0_s_agent_rp_data), // .data
.sink_startofpacket (version_id_0_s_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (version_id_0_s_agent_rp_endofpacket), // .endofpacket
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_006_src_ready), // src.ready
.src_valid (router_006_src_valid), // .valid
.src_data (router_006_src_data), // .data
.src_channel (router_006_src_channel), // .channel
.src_startofpacket (router_006_src_startofpacket), // .startofpacket
.src_endofpacket (router_006_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_005 router_007 (
.sink_ready (irq_ena_0_s_agent_rp_ready), // sink.ready
.sink_valid (irq_ena_0_s_agent_rp_valid), // .valid
.sink_data (irq_ena_0_s_agent_rp_data), // .data
.sink_startofpacket (irq_ena_0_s_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (irq_ena_0_s_agent_rp_endofpacket), // .endofpacket
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_007_src_ready), // src.ready
.src_valid (router_007_src_valid), // .valid
.src_data (router_007_src_data), // .data
.src_channel (router_007_src_channel), // .channel
.src_startofpacket (router_007_src_startofpacket), // .startofpacket
.src_endofpacket (router_007_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (75),
.PKT_DEST_ID_L (73),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (70),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.MAX_OUTSTANDING_RESPONSES (5),
.PIPELINED (0),
.ST_DATA_W (89),
.ST_CHANNEL_W (7),
.VALID_WIDTH (7),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.PKT_BYTE_CNT_H (59),
.PKT_BYTE_CNT_L (56),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.REORDER (0)
) kernel_cntrl_m0_limiter (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_src_valid), // .valid
.cmd_sink_data (router_src_data), // .data
.cmd_sink_channel (router_src_channel), // .channel
.cmd_sink_startofpacket (router_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_src_endofpacket), // .endofpacket
.cmd_src_ready (kernel_cntrl_m0_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (kernel_cntrl_m0_limiter_cmd_src_data), // .data
.cmd_src_channel (kernel_cntrl_m0_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (kernel_cntrl_m0_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (kernel_cntrl_m0_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_src_valid), // .valid
.rsp_sink_channel (rsp_mux_src_channel), // .channel
.rsp_sink_data (rsp_mux_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rsp_src_ready (kernel_cntrl_m0_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (kernel_cntrl_m0_limiter_rsp_src_valid), // .valid
.rsp_src_data (kernel_cntrl_m0_limiter_rsp_src_data), // .data
.rsp_src_channel (kernel_cntrl_m0_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (kernel_cntrl_m0_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (kernel_cntrl_m0_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (kernel_cntrl_m0_limiter_cmd_valid_data) // cmd_valid.data
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_demux cmd_demux (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (kernel_cntrl_m0_limiter_cmd_src_ready), // sink.ready
.sink_channel (kernel_cntrl_m0_limiter_cmd_src_channel), // .channel
.sink_data (kernel_cntrl_m0_limiter_cmd_src_data), // .data
.sink_startofpacket (kernel_cntrl_m0_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (kernel_cntrl_m0_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (kernel_cntrl_m0_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_src1_ready), // src1.ready
.src1_valid (cmd_demux_src1_valid), // .valid
.src1_data (cmd_demux_src1_data), // .data
.src1_channel (cmd_demux_src1_channel), // .channel
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_src2_ready), // src2.ready
.src2_valid (cmd_demux_src2_valid), // .valid
.src2_data (cmd_demux_src2_data), // .data
.src2_channel (cmd_demux_src2_channel), // .channel
.src2_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_src3_ready), // src3.ready
.src3_valid (cmd_demux_src3_valid), // .valid
.src3_data (cmd_demux_src3_data), // .data
.src3_channel (cmd_demux_src3_channel), // .channel
.src3_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_src3_endofpacket), // .endofpacket
.src4_ready (cmd_demux_src4_ready), // src4.ready
.src4_valid (cmd_demux_src4_valid), // .valid
.src4_data (cmd_demux_src4_data), // .data
.src4_channel (cmd_demux_src4_channel), // .channel
.src4_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_demux_src4_endofpacket), // .endofpacket
.src5_ready (cmd_demux_src5_ready), // src5.ready
.src5_valid (cmd_demux_src5_valid), // .valid
.src5_data (cmd_demux_src5_data), // .data
.src5_channel (cmd_demux_src5_channel), // .channel
.src5_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_demux_src5_endofpacket), // .endofpacket
.src6_ready (cmd_demux_src6_ready), // src6.ready
.src6_valid (cmd_demux_src6_valid), // .valid
.src6_data (cmd_demux_src6_data), // .data
.src6_channel (cmd_demux_src6_channel), // .channel
.src6_startofpacket (cmd_demux_src6_startofpacket), // .startofpacket
.src6_endofpacket (cmd_demux_src6_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux cmd_mux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (crosser_out_ready), // sink0.ready
.sink0_valid (crosser_out_valid), // .valid
.sink0_channel (crosser_out_channel), // .channel
.sink0_data (crosser_out_data), // .data
.sink0_startofpacket (crosser_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_out_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux cmd_mux_001 (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (crosser_001_out_ready), // sink0.ready
.sink0_valid (crosser_001_out_valid), // .valid
.sink0_channel (crosser_001_out_channel), // .channel
.sink0_data (crosser_001_out_data), // .data
.sink0_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_001_out_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux_002 cmd_mux_002 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_src2_valid), // .valid
.sink0_channel (cmd_demux_src2_channel), // .channel
.sink0_data (cmd_demux_src2_data), // .data
.sink0_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src2_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux_002 cmd_mux_003 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_003_src_ready), // src.ready
.src_valid (cmd_mux_003_src_valid), // .valid
.src_data (cmd_mux_003_src_data), // .data
.src_channel (cmd_mux_003_src_channel), // .channel
.src_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src3_ready), // sink0.ready
.sink0_valid (cmd_demux_src3_valid), // .valid
.sink0_channel (cmd_demux_src3_channel), // .channel
.sink0_data (cmd_demux_src3_data), // .data
.sink0_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src3_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux_002 cmd_mux_004 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_004_src_ready), // src.ready
.src_valid (cmd_mux_004_src_valid), // .valid
.src_data (cmd_mux_004_src_data), // .data
.src_channel (cmd_mux_004_src_channel), // .channel
.src_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src4_ready), // sink0.ready
.sink0_valid (cmd_demux_src4_valid), // .valid
.sink0_channel (cmd_demux_src4_channel), // .channel
.sink0_data (cmd_demux_src4_data), // .data
.sink0_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src4_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux_002 cmd_mux_005 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_005_src_ready), // src.ready
.src_valid (cmd_mux_005_src_valid), // .valid
.src_data (cmd_mux_005_src_data), // .data
.src_channel (cmd_mux_005_src_channel), // .channel
.src_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src5_ready), // sink0.ready
.sink0_valid (cmd_demux_src5_valid), // .valid
.sink0_channel (cmd_demux_src5_channel), // .channel
.sink0_data (cmd_demux_src5_data), // .data
.sink0_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src5_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux_002 cmd_mux_006 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_006_src_ready), // src.ready
.src_valid (cmd_mux_006_src_valid), // .valid
.src_data (cmd_mux_006_src_data), // .data
.src_channel (cmd_mux_006_src_channel), // .channel
.src_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src6_ready), // sink0.ready
.sink0_valid (cmd_demux_src6_valid), // .valid
.sink0_channel (cmd_demux_src6_channel), // .channel
.sink0_data (cmd_demux_src6_data), // .data
.sink0_startofpacket (cmd_demux_src6_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src6_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux rsp_demux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_001_src_ready), // sink.ready
.sink_channel (router_001_src_channel), // .channel
.sink_data (router_001_src_data), // .data
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.sink_valid (router_001_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux rsp_demux_001 (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (address_span_extender_0_cntl_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (address_span_extender_0_cntl_rsp_width_adapter_src_channel), // .channel
.sink_data (address_span_extender_0_cntl_rsp_width_adapter_src_data), // .data
.sink_startofpacket (address_span_extender_0_cntl_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (address_span_extender_0_cntl_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (address_span_extender_0_cntl_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux_002 rsp_demux_002 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (sys_description_rom_s1_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (sys_description_rom_s1_rsp_width_adapter_src_channel), // .channel
.sink_data (sys_description_rom_s1_rsp_width_adapter_src_data), // .data
.sink_startofpacket (sys_description_rom_s1_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (sys_description_rom_s1_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (sys_description_rom_s1_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux_002 rsp_demux_003 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (sw_reset_s_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (sw_reset_s_rsp_width_adapter_src_channel), // .channel
.sink_data (sw_reset_s_rsp_width_adapter_src_data), // .data
.sink_startofpacket (sw_reset_s_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (sw_reset_s_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (sw_reset_s_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_demux_003_src0_valid), // .valid
.src0_data (rsp_demux_003_src0_data), // .data
.src0_channel (rsp_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_003_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux_002 rsp_demux_004 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_005_src_ready), // sink.ready
.sink_channel (router_005_src_channel), // .channel
.sink_data (router_005_src_data), // .data
.sink_startofpacket (router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (router_005_src_endofpacket), // .endofpacket
.sink_valid (router_005_src_valid), // .valid
.src0_ready (rsp_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_demux_004_src0_valid), // .valid
.src0_data (rsp_demux_004_src0_data), // .data
.src0_channel (rsp_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_004_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux_002 rsp_demux_005 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_006_src_ready), // sink.ready
.sink_channel (router_006_src_channel), // .channel
.sink_data (router_006_src_data), // .data
.sink_startofpacket (router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (router_006_src_endofpacket), // .endofpacket
.sink_valid (router_006_src_valid), // .valid
.src0_ready (rsp_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_demux_005_src0_valid), // .valid
.src0_data (rsp_demux_005_src0_data), // .data
.src0_channel (rsp_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_005_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux_002 rsp_demux_006 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_007_src_ready), // sink.ready
.sink_channel (router_007_src_channel), // .channel
.sink_data (router_007_src_data), // .data
.sink_startofpacket (router_007_src_startofpacket), // .startofpacket
.sink_endofpacket (router_007_src_endofpacket), // .endofpacket
.sink_valid (router_007_src_valid), // .valid
.src0_ready (rsp_demux_006_src0_ready), // src0.ready
.src0_valid (rsp_demux_006_src0_valid), // .valid
.src0_data (rsp_demux_006_src0_data), // .data
.src0_channel (rsp_demux_006_src0_channel), // .channel
.src0_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_006_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_mux rsp_mux (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (crosser_002_out_ready), // sink0.ready
.sink0_valid (crosser_002_out_valid), // .valid
.sink0_channel (crosser_002_out_channel), // .channel
.sink0_data (crosser_002_out_data), // .data
.sink0_startofpacket (crosser_002_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_002_out_endofpacket), // .endofpacket
.sink1_ready (crosser_003_out_ready), // sink1.ready
.sink1_valid (crosser_003_out_valid), // .valid
.sink1_channel (crosser_003_out_channel), // .channel
.sink1_data (crosser_003_out_data), // .data
.sink1_startofpacket (crosser_003_out_startofpacket), // .startofpacket
.sink1_endofpacket (crosser_003_out_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src0_valid), // .valid
.sink2_channel (rsp_demux_002_src0_channel), // .channel
.sink2_data (rsp_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_demux_003_src0_valid), // .valid
.sink3_channel (rsp_demux_003_src0_channel), // .channel
.sink3_data (rsp_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
.sink4_ready (rsp_demux_004_src0_ready), // sink4.ready
.sink4_valid (rsp_demux_004_src0_valid), // .valid
.sink4_channel (rsp_demux_004_src0_channel), // .channel
.sink4_data (rsp_demux_004_src0_data), // .data
.sink4_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_demux_004_src0_endofpacket), // .endofpacket
.sink5_ready (rsp_demux_005_src0_ready), // sink5.ready
.sink5_valid (rsp_demux_005_src0_valid), // .valid
.sink5_channel (rsp_demux_005_src0_channel), // .channel
.sink5_data (rsp_demux_005_src0_data), // .data
.sink5_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.sink5_endofpacket (rsp_demux_005_src0_endofpacket), // .endofpacket
.sink6_ready (rsp_demux_006_src0_ready), // sink6.ready
.sink6_valid (rsp_demux_006_src0_valid), // .valid
.sink6_channel (rsp_demux_006_src0_channel), // .channel
.sink6_data (rsp_demux_006_src0_data), // .data
.sink6_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
.sink6_endofpacket (rsp_demux_006_src0_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (49),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (59),
.IN_PKT_BYTE_CNT_L (56),
.IN_PKT_TRANS_COMPRESSED_READ (50),
.IN_PKT_BURSTWRAP_H (60),
.IN_PKT_BURSTWRAP_L (60),
.IN_PKT_BURST_SIZE_H (63),
.IN_PKT_BURST_SIZE_L (61),
.IN_PKT_RESPONSE_STATUS_H (85),
.IN_PKT_RESPONSE_STATUS_L (84),
.IN_PKT_TRANS_EXCLUSIVE (55),
.IN_PKT_BURST_TYPE_H (65),
.IN_PKT_BURST_TYPE_L (64),
.IN_PKT_ORI_BURST_SIZE_L (86),
.IN_PKT_ORI_BURST_SIZE_H (88),
.IN_ST_DATA_W (89),
.OUT_PKT_ADDR_H (85),
.OUT_PKT_ADDR_L (72),
.OUT_PKT_DATA_H (63),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (71),
.OUT_PKT_BYTEEN_L (64),
.OUT_PKT_BYTE_CNT_H (95),
.OUT_PKT_BYTE_CNT_L (92),
.OUT_PKT_TRANS_COMPRESSED_READ (86),
.OUT_PKT_BURST_SIZE_H (99),
.OUT_PKT_BURST_SIZE_L (97),
.OUT_PKT_RESPONSE_STATUS_H (121),
.OUT_PKT_RESPONSE_STATUS_L (120),
.OUT_PKT_TRANS_EXCLUSIVE (91),
.OUT_PKT_BURST_TYPE_H (101),
.OUT_PKT_BURST_TYPE_L (100),
.OUT_PKT_ORI_BURST_SIZE_L (122),
.OUT_PKT_ORI_BURST_SIZE_H (124),
.OUT_ST_DATA_W (125),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) address_span_extender_0_cntl_cmd_width_adapter (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_001_src_valid), // sink.valid
.in_channel (cmd_mux_001_src_channel), // .channel
.in_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_001_src_ready), // .ready
.in_data (cmd_mux_001_src_data), // .data
.out_endofpacket (address_span_extender_0_cntl_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (address_span_extender_0_cntl_cmd_width_adapter_src_data), // .data
.out_channel (address_span_extender_0_cntl_cmd_width_adapter_src_channel), // .channel
.out_valid (address_span_extender_0_cntl_cmd_width_adapter_src_valid), // .valid
.out_ready (address_span_extender_0_cntl_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (address_span_extender_0_cntl_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (49),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (59),
.IN_PKT_BYTE_CNT_L (56),
.IN_PKT_TRANS_COMPRESSED_READ (50),
.IN_PKT_BURSTWRAP_H (60),
.IN_PKT_BURSTWRAP_L (60),
.IN_PKT_BURST_SIZE_H (63),
.IN_PKT_BURST_SIZE_L (61),
.IN_PKT_RESPONSE_STATUS_H (85),
.IN_PKT_RESPONSE_STATUS_L (84),
.IN_PKT_TRANS_EXCLUSIVE (55),
.IN_PKT_BURST_TYPE_H (65),
.IN_PKT_BURST_TYPE_L (64),
.IN_PKT_ORI_BURST_SIZE_L (86),
.IN_PKT_ORI_BURST_SIZE_H (88),
.IN_ST_DATA_W (89),
.OUT_PKT_ADDR_H (85),
.OUT_PKT_ADDR_L (72),
.OUT_PKT_DATA_H (63),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (71),
.OUT_PKT_BYTEEN_L (64),
.OUT_PKT_BYTE_CNT_H (95),
.OUT_PKT_BYTE_CNT_L (92),
.OUT_PKT_TRANS_COMPRESSED_READ (86),
.OUT_PKT_BURST_SIZE_H (99),
.OUT_PKT_BURST_SIZE_L (97),
.OUT_PKT_RESPONSE_STATUS_H (121),
.OUT_PKT_RESPONSE_STATUS_L (120),
.OUT_PKT_TRANS_EXCLUSIVE (91),
.OUT_PKT_BURST_TYPE_H (101),
.OUT_PKT_BURST_TYPE_L (100),
.OUT_PKT_ORI_BURST_SIZE_L (122),
.OUT_PKT_ORI_BURST_SIZE_H (124),
.OUT_ST_DATA_W (125),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sys_description_rom_s1_cmd_width_adapter (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_002_src_valid), // sink.valid
.in_channel (cmd_mux_002_src_channel), // .channel
.in_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_002_src_ready), // .ready
.in_data (cmd_mux_002_src_data), // .data
.out_endofpacket (sys_description_rom_s1_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sys_description_rom_s1_cmd_width_adapter_src_data), // .data
.out_channel (sys_description_rom_s1_cmd_width_adapter_src_channel), // .channel
.out_valid (sys_description_rom_s1_cmd_width_adapter_src_valid), // .valid
.out_ready (sys_description_rom_s1_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (sys_description_rom_s1_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (49),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (59),
.IN_PKT_BYTE_CNT_L (56),
.IN_PKT_TRANS_COMPRESSED_READ (50),
.IN_PKT_BURSTWRAP_H (60),
.IN_PKT_BURSTWRAP_L (60),
.IN_PKT_BURST_SIZE_H (63),
.IN_PKT_BURST_SIZE_L (61),
.IN_PKT_RESPONSE_STATUS_H (85),
.IN_PKT_RESPONSE_STATUS_L (84),
.IN_PKT_TRANS_EXCLUSIVE (55),
.IN_PKT_BURST_TYPE_H (65),
.IN_PKT_BURST_TYPE_L (64),
.IN_PKT_ORI_BURST_SIZE_L (86),
.IN_PKT_ORI_BURST_SIZE_H (88),
.IN_ST_DATA_W (89),
.OUT_PKT_ADDR_H (85),
.OUT_PKT_ADDR_L (72),
.OUT_PKT_DATA_H (63),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (71),
.OUT_PKT_BYTEEN_L (64),
.OUT_PKT_BYTE_CNT_H (95),
.OUT_PKT_BYTE_CNT_L (92),
.OUT_PKT_TRANS_COMPRESSED_READ (86),
.OUT_PKT_BURST_SIZE_H (99),
.OUT_PKT_BURST_SIZE_L (97),
.OUT_PKT_RESPONSE_STATUS_H (121),
.OUT_PKT_RESPONSE_STATUS_L (120),
.OUT_PKT_TRANS_EXCLUSIVE (91),
.OUT_PKT_BURST_TYPE_H (101),
.OUT_PKT_BURST_TYPE_L (100),
.OUT_PKT_ORI_BURST_SIZE_L (122),
.OUT_PKT_ORI_BURST_SIZE_H (124),
.OUT_ST_DATA_W (125),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sw_reset_s_cmd_width_adapter (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_003_src_valid), // sink.valid
.in_channel (cmd_mux_003_src_channel), // .channel
.in_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_003_src_ready), // .ready
.in_data (cmd_mux_003_src_data), // .data
.out_endofpacket (sw_reset_s_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sw_reset_s_cmd_width_adapter_src_data), // .data
.out_channel (sw_reset_s_cmd_width_adapter_src_channel), // .channel
.out_valid (sw_reset_s_cmd_width_adapter_src_valid), // .valid
.out_ready (sw_reset_s_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (sw_reset_s_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (85),
.IN_PKT_ADDR_L (72),
.IN_PKT_DATA_H (63),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (71),
.IN_PKT_BYTEEN_L (64),
.IN_PKT_BYTE_CNT_H (95),
.IN_PKT_BYTE_CNT_L (92),
.IN_PKT_TRANS_COMPRESSED_READ (86),
.IN_PKT_BURSTWRAP_H (96),
.IN_PKT_BURSTWRAP_L (96),
.IN_PKT_BURST_SIZE_H (99),
.IN_PKT_BURST_SIZE_L (97),
.IN_PKT_RESPONSE_STATUS_H (121),
.IN_PKT_RESPONSE_STATUS_L (120),
.IN_PKT_TRANS_EXCLUSIVE (91),
.IN_PKT_BURST_TYPE_H (101),
.IN_PKT_BURST_TYPE_L (100),
.IN_PKT_ORI_BURST_SIZE_L (122),
.IN_PKT_ORI_BURST_SIZE_H (124),
.IN_ST_DATA_W (125),
.OUT_PKT_ADDR_H (49),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (59),
.OUT_PKT_BYTE_CNT_L (56),
.OUT_PKT_TRANS_COMPRESSED_READ (50),
.OUT_PKT_BURST_SIZE_H (63),
.OUT_PKT_BURST_SIZE_L (61),
.OUT_PKT_RESPONSE_STATUS_H (85),
.OUT_PKT_RESPONSE_STATUS_L (84),
.OUT_PKT_TRANS_EXCLUSIVE (55),
.OUT_PKT_BURST_TYPE_H (65),
.OUT_PKT_BURST_TYPE_L (64),
.OUT_PKT_ORI_BURST_SIZE_L (86),
.OUT_PKT_ORI_BURST_SIZE_H (88),
.OUT_ST_DATA_W (89),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) address_span_extender_0_cntl_rsp_width_adapter (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_002_src_valid), // sink.valid
.in_channel (router_002_src_channel), // .channel
.in_startofpacket (router_002_src_startofpacket), // .startofpacket
.in_endofpacket (router_002_src_endofpacket), // .endofpacket
.in_ready (router_002_src_ready), // .ready
.in_data (router_002_src_data), // .data
.out_endofpacket (address_span_extender_0_cntl_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (address_span_extender_0_cntl_rsp_width_adapter_src_data), // .data
.out_channel (address_span_extender_0_cntl_rsp_width_adapter_src_channel), // .channel
.out_valid (address_span_extender_0_cntl_rsp_width_adapter_src_valid), // .valid
.out_ready (address_span_extender_0_cntl_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (address_span_extender_0_cntl_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (85),
.IN_PKT_ADDR_L (72),
.IN_PKT_DATA_H (63),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (71),
.IN_PKT_BYTEEN_L (64),
.IN_PKT_BYTE_CNT_H (95),
.IN_PKT_BYTE_CNT_L (92),
.IN_PKT_TRANS_COMPRESSED_READ (86),
.IN_PKT_BURSTWRAP_H (96),
.IN_PKT_BURSTWRAP_L (96),
.IN_PKT_BURST_SIZE_H (99),
.IN_PKT_BURST_SIZE_L (97),
.IN_PKT_RESPONSE_STATUS_H (121),
.IN_PKT_RESPONSE_STATUS_L (120),
.IN_PKT_TRANS_EXCLUSIVE (91),
.IN_PKT_BURST_TYPE_H (101),
.IN_PKT_BURST_TYPE_L (100),
.IN_PKT_ORI_BURST_SIZE_L (122),
.IN_PKT_ORI_BURST_SIZE_H (124),
.IN_ST_DATA_W (125),
.OUT_PKT_ADDR_H (49),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (59),
.OUT_PKT_BYTE_CNT_L (56),
.OUT_PKT_TRANS_COMPRESSED_READ (50),
.OUT_PKT_BURST_SIZE_H (63),
.OUT_PKT_BURST_SIZE_L (61),
.OUT_PKT_RESPONSE_STATUS_H (85),
.OUT_PKT_RESPONSE_STATUS_L (84),
.OUT_PKT_TRANS_EXCLUSIVE (55),
.OUT_PKT_BURST_TYPE_H (65),
.OUT_PKT_BURST_TYPE_L (64),
.OUT_PKT_ORI_BURST_SIZE_L (86),
.OUT_PKT_ORI_BURST_SIZE_H (88),
.OUT_ST_DATA_W (89),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sys_description_rom_s1_rsp_width_adapter (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_003_src_valid), // sink.valid
.in_channel (router_003_src_channel), // .channel
.in_startofpacket (router_003_src_startofpacket), // .startofpacket
.in_endofpacket (router_003_src_endofpacket), // .endofpacket
.in_ready (router_003_src_ready), // .ready
.in_data (router_003_src_data), // .data
.out_endofpacket (sys_description_rom_s1_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sys_description_rom_s1_rsp_width_adapter_src_data), // .data
.out_channel (sys_description_rom_s1_rsp_width_adapter_src_channel), // .channel
.out_valid (sys_description_rom_s1_rsp_width_adapter_src_valid), // .valid
.out_ready (sys_description_rom_s1_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (sys_description_rom_s1_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (85),
.IN_PKT_ADDR_L (72),
.IN_PKT_DATA_H (63),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (71),
.IN_PKT_BYTEEN_L (64),
.IN_PKT_BYTE_CNT_H (95),
.IN_PKT_BYTE_CNT_L (92),
.IN_PKT_TRANS_COMPRESSED_READ (86),
.IN_PKT_BURSTWRAP_H (96),
.IN_PKT_BURSTWRAP_L (96),
.IN_PKT_BURST_SIZE_H (99),
.IN_PKT_BURST_SIZE_L (97),
.IN_PKT_RESPONSE_STATUS_H (121),
.IN_PKT_RESPONSE_STATUS_L (120),
.IN_PKT_TRANS_EXCLUSIVE (91),
.IN_PKT_BURST_TYPE_H (101),
.IN_PKT_BURST_TYPE_L (100),
.IN_PKT_ORI_BURST_SIZE_L (122),
.IN_PKT_ORI_BURST_SIZE_H (124),
.IN_ST_DATA_W (125),
.OUT_PKT_ADDR_H (49),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (59),
.OUT_PKT_BYTE_CNT_L (56),
.OUT_PKT_TRANS_COMPRESSED_READ (50),
.OUT_PKT_BURST_SIZE_H (63),
.OUT_PKT_BURST_SIZE_L (61),
.OUT_PKT_RESPONSE_STATUS_H (85),
.OUT_PKT_RESPONSE_STATUS_L (84),
.OUT_PKT_TRANS_EXCLUSIVE (55),
.OUT_PKT_BURST_TYPE_H (65),
.OUT_PKT_BURST_TYPE_L (64),
.OUT_PKT_ORI_BURST_SIZE_L (86),
.OUT_PKT_ORI_BURST_SIZE_H (88),
.OUT_ST_DATA_W (89),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sw_reset_s_rsp_width_adapter (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_004_src_valid), // sink.valid
.in_channel (router_004_src_channel), // .channel
.in_startofpacket (router_004_src_startofpacket), // .startofpacket
.in_endofpacket (router_004_src_endofpacket), // .endofpacket
.in_ready (router_004_src_ready), // .ready
.in_data (router_004_src_data), // .data
.out_endofpacket (sw_reset_s_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sw_reset_s_rsp_width_adapter_src_data), // .data
.out_channel (sw_reset_s_rsp_width_adapter_src_channel), // .channel
.out_valid (sw_reset_s_rsp_width_adapter_src_valid), // .valid
.out_ready (sw_reset_s_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (sw_reset_s_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (89),
.BITS_PER_SYMBOL (89),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (7),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser (
.in_clk (clk_reset_clk_clk), // in_clk.clk
.in_reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (kernel_clk_out_clk_clk), // out_clk.clk
.out_reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_demux_src0_ready), // in.ready
.in_valid (cmd_demux_src0_valid), // .valid
.in_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.in_channel (cmd_demux_src0_channel), // .channel
.in_data (cmd_demux_src0_data), // .data
.out_ready (crosser_out_ready), // out.ready
.out_valid (crosser_out_valid), // .valid
.out_startofpacket (crosser_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_out_endofpacket), // .endofpacket
.out_channel (crosser_out_channel), // .channel
.out_data (crosser_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (89),
.BITS_PER_SYMBOL (89),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (7),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_001 (
.in_clk (clk_reset_clk_clk), // in_clk.clk
.in_reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (kernel_clk_out_clk_clk), // out_clk.clk
.out_reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_demux_src1_ready), // in.ready
.in_valid (cmd_demux_src1_valid), // .valid
.in_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.in_channel (cmd_demux_src1_channel), // .channel
.in_data (cmd_demux_src1_data), // .data
.out_ready (crosser_001_out_ready), // out.ready
.out_valid (crosser_001_out_valid), // .valid
.out_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_001_out_endofpacket), // .endofpacket
.out_channel (crosser_001_out_channel), // .channel
.out_data (crosser_001_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (89),
.BITS_PER_SYMBOL (89),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (7),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_002 (
.in_clk (kernel_clk_out_clk_clk), // in_clk.clk
.in_reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_reset_clk_clk), // out_clk.clk
.out_reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_demux_src0_ready), // in.ready
.in_valid (rsp_demux_src0_valid), // .valid
.in_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.in_channel (rsp_demux_src0_channel), // .channel
.in_data (rsp_demux_src0_data), // .data
.out_ready (crosser_002_out_ready), // out.ready
.out_valid (crosser_002_out_valid), // .valid
.out_startofpacket (crosser_002_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_002_out_endofpacket), // .endofpacket
.out_channel (crosser_002_out_channel), // .channel
.out_data (crosser_002_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (89),
.BITS_PER_SYMBOL (89),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (7),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_003 (
.in_clk (kernel_clk_out_clk_clk), // in_clk.clk
.in_reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_reset_clk_clk), // out_clk.clk
.out_reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_demux_001_src0_ready), // in.ready
.in_valid (rsp_demux_001_src0_valid), // .valid
.in_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.in_channel (rsp_demux_001_src0_channel), // .channel
.in_data (rsp_demux_001_src0_data), // .data
.out_ready (crosser_003_out_ready), // out.ready
.out_valid (crosser_003_out_valid), // .valid
.out_startofpacket (crosser_003_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_003_out_endofpacket), // .endofpacket
.out_channel (crosser_003_out_channel), // .channel
.out_data (crosser_003_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
endmodule
|
`timescale 1 ns / 1 ps
module smvm(
input clk,
input reset,
input idle,
input start,
output stall,
output [63:0] ret_val,
output mc_req_ld,
output mc_req_st,
output [47:0] mc_req_vadr,
output [63:0] mc_req_wrd_rdctl,
input mc_rd_rq_stall,
input mc_wr_rq_stall,
input [31:0] mc_rsp_rdctl,
input [63:0] mc_rsp_data,
input mc_rsp_push,
output mc_rsp_stall,
input [47:0] x,
input [47:0] a,
input [47:0] y,
input [63:0] nnz,
input [63:0] a_mem_size,
input [63:0] result_size,
input [47:0] mcv);
reg [2:0] state, next_state;
`define IDLE 0
`define LD_RAM 1
`define LD_A 2
`define LD_X 3
`define STORE_RES 4
reg [47:0] r_x, next_r_x;
reg [47:0] r_a_ptr, next_r_a_ptr;
reg [47:0] r_y_ptr, next_r_y_ptr;
reg [63:0] r_nnz_left, next_r_nnz_left;
reg [63:0] r_a_bytes_left, next_r_a_bytes_left;
reg [63:0] r_result_left, next_r_result_left;
reg [47:0] r_mcv_ptr, next_r_mcv_ptr;
reg r_mc_req_ld, r_mc_req_st, next_r_mc_req_ld, next_r_mc_req_st;
reg [47:0] r_mc_req_vadr, next_r_mc_req_vadr;
reg [63:0] r_mc_req_wrd_rdctl, next_r_mc_req_wrd_rdctl;
wire [31:0] decode_row;
wire [31:0] decode_column;
wire [63:0] decode_value;
wire decode_push;
wire column_fifo_empty;
wire column_fifo_full;
wire column_fifo_hf;
wire [4:0] column_fifo_count;
wire [31:0] column_fifo_dout;
wire matrix_fifo_empty;
wire matrix_fifo_full;
wire matrix_fifo_hf;
wire [31:0] matrix_fifo_row;
wire [63:0] matrix_fifo_value;
reg a_near_empty;
reg r_mac_wr, next_r_mac_wr;
reg [63:0] r_mac_vector_in;
reg next_r_column_fifo_rd;
reg r_column_fifo_rd;
wire mac_push;
wire [63:0] mac_result;
reg result_fifo_rd, next_result_fifo_rd;
wire [63:0] result_fifo_dout;
wire result_fifo_full, result_fifo_empty;
reg idle_reset;
reg [7:0] counter, next_counter;
reg next_decode_push_in, decode_push_in;
wire packet_fifo_empty, decode_stall;
wire [63:0] packet_fifo_dout;
wire packet_fifo_hf;
wire packet_fifo_full;
wire [4:0] vector_fifo_count;
wire [63:0] vector_fifo_dout;
wire vector_fifo_empty, vector_fifo_full;
wire vector_fifo_hf;
reg rd_vector_fifo, next_rd_vector_fifo;
reg [4:0] mac_counter;
always @(posedge clk)
idle_reset <= idle || reset;
assign ret_val = 0;
//TODO: use stall
assign mc_rsp_stall = 0;
always @(posedge clk)
r_column_fifo_rd <= next_r_column_fifo_rd;
assign stall = (state != `IDLE);
always @(posedge clk)
a_near_empty <= ~|r_a_bytes_left[63:4];
reg [2:0] to_idle_count;
always @(posedge clk) begin
if(r_result_left == 0)
to_idle_count = to_idle_count + 1;
else
to_idle_count = 0;
end
always @* begin
next_state = state;
next_r_mc_req_ld = 0;
next_r_mc_req_st = 0;
next_r_mc_req_vadr = 0;
next_r_mc_req_wrd_rdctl = 0;
next_r_x = r_x;
next_r_a_ptr = r_a_ptr;
next_r_y_ptr = r_y_ptr;
next_r_nnz_left = r_nnz_left;
next_r_a_bytes_left = r_a_bytes_left;
next_r_result_left = r_result_left;
next_result_fifo_rd = 0;
next_r_column_fifo_rd <= 0;
next_r_mcv_ptr = r_mcv_ptr;
next_counter = counter;
case(state)
`IDLE: begin
next_r_a_bytes_left = 0;
next_counter = 0;
if(start) begin
next_state = `LD_RAM;
next_r_x = x;
next_r_a_ptr = a;
next_r_nnz_left = nnz;
next_r_a_bytes_left = a_mem_size;
next_r_result_left = result_size;
next_r_y_ptr = y;
next_r_mcv_ptr = mcv;
end
//TODO: make efficient
if(next_r_result_left == 0)
next_state = `IDLE;
end
`LD_RAM: begin
if(!mc_rd_rq_stall) begin
next_r_mc_req_ld = 1;
next_r_mc_req_vadr = r_mcv_ptr;
next_r_mc_req_wrd_rdctl = 2;
next_r_mcv_ptr = r_mcv_ptr + 8;
next_counter = counter + 1;
end
if(counter == 8'HFF)
next_state = `LD_A;
else
next_state = `LD_RAM;
end
`LD_A: begin
if((r_result_left == 0) && to_idle_count[2])
next_state = `IDLE;
else if(!mc_wr_rq_stall && !result_fifo_empty && (r_result_left != 0)) begin
next_result_fifo_rd = 1;
next_state = `STORE_RES;
end else if(!mc_rd_rq_stall & !column_fifo_empty && !vector_fifo_hf) begin
next_r_column_fifo_rd <= 1;
next_state = `LD_X;
end
if(!mc_rd_rq_stall && !(a_near_empty && !r_a_bytes_left[3:0]) && !packet_fifo_hf)begin //fix for non 8 divisible numbers
next_r_mc_req_ld = 1;
next_r_mc_req_vadr = r_a_ptr;
next_r_a_ptr = r_a_ptr + 8;
next_r_a_bytes_left = r_a_bytes_left - 8;
next_r_mc_req_wrd_rdctl = 0;
end
end
`LD_X: begin
next_r_mc_req_ld = 1;
next_r_mc_req_vadr = r_x + {column_fifo_dout, 3'H0};
next_r_mc_req_wrd_rdctl = {57'H0,column_fifo_count,2'H1};
if(!mc_rd_rq_stall & !column_fifo_empty && !vector_fifo_hf) begin
next_r_column_fifo_rd <= 1;
next_state = `LD_X;
end else
next_state = `LD_A;
end
`STORE_RES: begin
next_r_mc_req_st = 1;
next_r_mc_req_vadr = r_y_ptr;
next_r_y_ptr = r_y_ptr + 8;
next_r_mc_req_wrd_rdctl = result_fifo_dout;
next_r_result_left = r_result_left - 1;
if(r_result_left[63:2] == 0) begin
next_state = `LD_A;
end else if(!mc_wr_rq_stall && !result_fifo_empty) begin
next_result_fifo_rd = 1;
next_state = `STORE_RES;
end else
next_state = `LD_A;
end
endcase
if(r_mac_wr)begin
next_r_nnz_left = r_nnz_left - 1;
end
end
always @(posedge clk) begin
if(reset) begin
state <= `IDLE;
end else begin
state <= next_state;
end
r_x <= next_r_x;
r_a_ptr <= next_r_a_ptr;
r_nnz_left <= next_r_nnz_left;
r_a_bytes_left <= next_r_a_bytes_left;
r_result_left <= next_r_result_left;
r_mc_req_ld <= next_r_mc_req_ld;
r_mc_req_st <= next_r_mc_req_st;
r_mc_req_vadr <= next_r_mc_req_vadr;
r_mc_req_wrd_rdctl <= next_r_mc_req_wrd_rdctl;
result_fifo_rd <= next_result_fifo_rd;
r_y_ptr <= next_r_y_ptr;
r_mcv_ptr <= next_r_mcv_ptr;
counter <= next_counter;
if(start) begin
$display("start values:%x, %x, %x, %x, %x, %x, %x", a, x, y, nnz, a_mem_size, result_size, mcv);
end
end
assign mc_req_ld = r_mc_req_ld;
assign mc_req_st = r_mc_req_st;
assign mc_req_vadr = r_mc_req_vadr;
assign mc_req_wrd_rdctl = r_mc_req_wrd_rdctl;
always @*
next_decode_push_in = !packet_fifo_empty && !decode_stall && !matrix_fifo_hf && !column_fifo_hf;
always @(posedge clk) begin
decode_push_in <= next_decode_push_in;
end
reg [63:0] decode_data_in;
always @*
if(next_decode_push_in)
decode_data_in <= packet_fifo_dout;
else
decode_data_in <= mc_rsp_data;
//TODO: add half full flag
fifo_fwft_64x1024 packet_fifo(
.clk(clk),
.rst(idle_reset),
.din(mc_rsp_data),
.wr_en(mc_rsp_push && (mc_rsp_rdctl[1:0] == 0)),
.rd_en(next_decode_push_in),
.dout(packet_fifo_dout),
.full(packet_fifo_full),
.empty(packet_fifo_empty),
.prog_full(packet_fifo_hf));
spoonPacketDecoder decode(
.reset(idle_reset),
.clk(clk),
.data(decode_data_in),
.push_in(next_decode_push_in),
.ramIn(mc_rsp_push && (mc_rsp_rdctl[1:0] == 2)),
.value(decode_value),
.row(decode_row),
.column(decode_column),
.push_out(decode_push),
.stall(decode_stall));
wire cc_push;
wire [31:0] cc_column;
wire [4:0] cc_count;
column_counter cc(
.clk(clk),
.reset(idle_reset),
.push_in(decode_push),
.push_out(cc_push),
.in_col_index(decode_column),
.out_col_index(cc_column),
.out_count(cc_count));
assign column_fifo_count[4] = 0;
fifo_36x512_hf column_fifo(
.clk(clk),
.rst(idle_reset),
.din({cc_count[3:0], cc_column}),
.wr_en(cc_push),
.rd_en(next_r_column_fifo_rd),
.dout({column_fifo_count[3:0], column_fifo_dout}),
.full(column_fifo_full),
.empty(column_fifo_empty),
.prog_full(column_fifo_hf));
fifo_fwft_96x512_hf matrix_fifo(
.clk(clk),
.rst(idle_reset),
.din({decode_row, decode_value}),
.wr_en(decode_push),
.rd_en(r_mac_wr),
.dout({matrix_fifo_row, matrix_fifo_value}),
.full(matrix_fifo_full),
.empty(matrix_fifo_empty),
.prog_full(matrix_fifo_hf));
fifo_69x512_hf vector_fifo(
.clk(clk),
.rst(idle_reset),
.din({mc_rsp_rdctl[6:2],mc_rsp_data}),
.wr_en(mc_rsp_push & mc_rsp_rdctl[0]),
.rd_en(next_rd_vector_fifo),
.dout({vector_fifo_count, vector_fifo_dout}),
.full(vector_fifo_full),
.empty(vector_fifo_empty),
.prog_full(vector_fifo_hf));
wire result_fifo_hf;
always @* begin
next_rd_vector_fifo = (!vector_fifo_empty) && (mac_counter == 0) && (!rd_vector_fifo) && (!result_fifo_hf);
end
always @(posedge clk)
rd_vector_fifo <= next_rd_vector_fifo;
always @(posedge clk) begin
if(reset) begin
mac_counter <= 0;
r_mac_wr <= 0;
end else if(rd_vector_fifo) begin
if(mac_counter > 0)
$display("error over write");
mac_counter <= vector_fifo_count;
r_mac_vector_in <= vector_fifo_dout;
r_mac_wr <= 1;
end else if(mac_counter > 0) begin
r_mac_wr <= 1;
mac_counter <= mac_counter - 1;
end else begin
r_mac_wr <= 0;
end
end
//TODO: fix with fifo
mac the_mac(
.clk(clk),
.reset(idle_reset),
.row(matrix_fifo_row[9:0]),
.value0(matrix_fifo_value),
.value1(r_mac_vector_in),
.wr(r_mac_wr),
.push(mac_push),
.dout(mac_result),
.done(r_nnz_left == 0));
fifo_64x512_hf result_fifo(
.clk(clk),
.rst(idle_reset),
.din(mac_result),
.wr_en(mac_push),
.rd_en(next_result_fifo_rd),
.dout(result_fifo_dout),
.full(result_fifo_full),
.empty(result_fifo_empty),
.prog_full(result_fifo_hf));
//check for overflow fifo
always @(posedge clk) begin
if(vector_fifo_full)
$display("error:vector_fifo overflow");
if(result_fifo_full)
$display("error:result_fifo overflow");
if(matrix_fifo_full)
$display("error:matrix_fifo overflow");
if(column_fifo_full)
$display("error:column_fifo overflow");
if(packet_fifo_full)
$display("error:packet_fifo overflow");
if(packet_fifo_hf)
$display("note:packet_fifo half full");
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFXBP_BLACKBOX_V
`define SKY130_FD_SC_LP__DFXBP_BLACKBOX_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dfxbp (
Q ,
Q_N,
CLK,
D
);
output Q ;
output Q_N;
input CLK;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFXBP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A2BB2OI_4_V
`define SKY130_FD_SC_HS__A2BB2OI_4_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog wrapper for a2bb2oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a2bb2oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a2bb2oi_4 (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a2bb2oi_4 (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A2BB2OI_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A21O_1_V
`define SKY130_FD_SC_LS__A21O_1_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog wrapper for a21o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a21o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a21o_1 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a21o_1 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A21O_1_V
|
`default_nettype none
`timescale 1ns/1ns
module tb_sys_level;
`include "../task/task_disp_branch.v"
`include "../task/task_disp_loadstore.v"
localparam PL_CORE_CYCLE = 20; //It's necessary "Core Clock == Bus Clock". This restriction is removed near future.
localparam PL_BUS_CYCLE = 20; //
localparam PL_DPS_CYCLE = 18;
localparam PL_RESET_TIME = 20;
localparam PL_GCI_SIZE = 32'h0001_0000;
/****************************************
System
****************************************/
reg iCORE_CLOCK;
reg iBUS_CLOCK;
reg iDPS_CLOCK;
reg inRESET;
/****************************************
SCI
****************************************/
wire oSCI_TXD;
reg iSCI_RXD;
/****************************************
Memory BUS
****************************************/
//Req
wire oMEMORY_REQ;
wire iMEMORY_LOCK;
wire [1:0] oMEMORY_ORDER; //00=Byte Order 01=2Byte Order 10= Word Order 11= None
wire [3:0] oMEMORY_MASK;
wire oMEMORY_RW; //1:Write | 0:Read
wire [31:0] oMEMORY_ADDR;
//This -> Data RAM
wire [31:0] oMEMORY_DATA;
//Data RAM -> This
wire iMEMORY_VALID;
wire oMEMORY_BUSY;
wire [63:0] iMEMORY_DATA;
/****************************************
GCI BUS
****************************************/
//Request
wire oGCI_REQ; //Input
reg iGCI_BUSY;
wire oGCI_RW; //0=Read : 1=Write
wire [31:0] oGCI_ADDR;
wire [31:0] oGCI_DATA;
//Return
reg iGCI_REQ; //Output
wire oGCI_BUSY;
reg [31:0] iGCI_DATA;
//Interrupt
reg iGCI_IRQ_REQ;
reg [5:0] iGCI_IRQ_NUM;
wire oGCI_IRQ_ACK;
//Interrupt Controll
wire oIO_IRQ_CONFIG_TABLE_REQ;
wire [5:0] oIO_IRQ_CONFIG_TABLE_ENTRY;
wire oIO_IRQ_CONFIG_TABLE_FLAG_MASK;
wire oIO_IRQ_CONFIG_TABLE_FLAG_VALID;
wire [1:0] oIO_IRQ_CONFIG_TABLE_FLAG_LEVEL;
wire [31:0] oDEBUG_PC;
wire [31:0] oDEBUG0;
/****************************************
Debug
****************************************/
reg iDEBUG_UART_RXD;
wire oDEBUG_UART_TXD;
reg iDEBUG_PARA_REQ;
wire oDEBUG_PARA_BUSY;
reg [7:0] iDEBUG_PARA_CMD;
reg [31:0] iDEBUG_PARA_DATA;
wire oDEBUG_PARA_VALID;
reg iDEBUG_PARA_BUSY;
wire oDEBUG_PARA_ERROR;
wire [31:0] oDEBUG_PARA_DATA;
/******************************************************
Target
******************************************************/
mist1032isa TARGET(
/****************************************
System
****************************************/
.iCORE_CLOCK(iCORE_CLOCK),
.iBUS_CLOCK(iBUS_CLOCK),
.iDPS_CLOCK(iDPS_CLOCK),
.inRESET(inRESET),
/****************************************
SCI
****************************************/
.oSCI_TXD(oSCI_TXD),
.iSCI_RXD(iSCI_RXD),
/****************************************
Memory BUS
****************************************/
//Req
.oMEMORY_REQ(oMEMORY_REQ),
.iMEMORY_LOCK(iMEMORY_LOCK),
.oMEMORY_ORDER(oMEMORY_ORDER), //00=Byte Order 01=2Byte Order 10= Word Order 11= None
.oMEMORY_MASK(oMEMORY_MASK),
.oMEMORY_RW(oMEMORY_RW), //1:Write | 0:Read
.oMEMORY_ADDR(oMEMORY_ADDR),
//This -> Data RAM
.oMEMORY_DATA(oMEMORY_DATA),
//Data RAM -> This
.iMEMORY_VALID(iMEMORY_VALID),
.oMEMORY_BUSY(oMEMORY_BUSY),
.iMEMORY_DATA(iMEMORY_DATA),
/****************************************
GCI BUS
****************************************/
//Request
.oGCI_REQ(oGCI_REQ), //Input
.iGCI_BUSY(iGCI_BUSY),
.oGCI_RW(oGCI_RW), //0=Read : 1=Write
.oGCI_ADDR(oGCI_ADDR),
.oGCI_DATA(oGCI_DATA),
//Return
.iGCI_REQ(iGCI_REQ), //Output
.oGCI_BUSY(oGCI_BUSY),
.iGCI_DATA(iGCI_DATA),
//Interrupt
.iGCI_IRQ_REQ(iGCI_IRQ_REQ),
.iGCI_IRQ_NUM(iGCI_IRQ_NUM),
.oGCI_IRQ_ACK(oGCI_IRQ_ACK),
//Interrupt Controll
.oIO_IRQ_CONFIG_TABLE_REQ(oIO_IRQ_CONFIG_TABLE_REQ),
.oIO_IRQ_CONFIG_TABLE_ENTRY(oIO_IRQ_CONFIG_TABLE_ENTRY),
.oIO_IRQ_CONFIG_TABLE_FLAG_MASK(oIO_IRQ_CONFIG_TABLE_FLAG_MASK),
.oIO_IRQ_CONFIG_TABLE_FLAG_VALID(oIO_IRQ_CONFIG_TABLE_FLAG_VALID),
.oIO_IRQ_CONFIG_TABLE_FLAG_LEVEL(oIO_IRQ_CONFIG_TABLE_FLAG_LEVEL),
.oDEBUG_PC(oDEBUG_PC),
.oDEBUG0(oDEBUG0),
/****************************************
Debug
****************************************/
.iDEBUG_UART_RXD(iDEBUG_UART_RXD),
.oDEBUG_UART_TXD(oDEBUG_UART_TXD),
.iDEBUG_PARA_REQ(iDEBUG_PARA_REQ),
.oDEBUG_PARA_BUSY(oDEBUG_PARA_BUSY),
.iDEBUG_PARA_CMD(iDEBUG_PARA_CMD),
.iDEBUG_PARA_DATA(iDEBUG_PARA_DATA),
.oDEBUG_PARA_VALID(oDEBUG_PARA_VALID),
.iDEBUG_PARA_BUSY(iDEBUG_PARA_BUSY),
.oDEBUG_PARA_ERROR(oDEBUG_PARA_ERROR),
.oDEBUG_PARA_DATA(oDEBUG_PARA_DATA)
);
/******************************************************
Clock
******************************************************/
always#(PL_CORE_CYCLE/2)begin
iCORE_CLOCK = !iCORE_CLOCK;
end
always#(PL_BUS_CYCLE/2)begin
iBUS_CLOCK = !iBUS_CLOCK;
end
always#(PL_DPS_CYCLE/2)begin
iDPS_CLOCK = !iDPS_CLOCK;
end
/******************************************************
State
******************************************************/
initial begin
$display("Check Start");
//Initial
iCORE_CLOCK = 1'b0;
iBUS_CLOCK = 1'b0;
iDPS_CLOCK = 1'b0;
inRESET = 1'b0;
iSCI_RXD = 1'b1;
iGCI_BUSY = 1'b0;
iGCI_REQ = 1'b0;
iGCI_DATA = 32'h0;
iGCI_IRQ_REQ = 1'b0;
iGCI_IRQ_NUM = 6'h0;
iDEBUG_UART_RXD = 1'b1;
iDEBUG_PARA_REQ = 1'b0;
iDEBUG_PARA_CMD = 8'h0;
iDEBUG_PARA_DATA = 32'h0;
iDEBUG_PARA_BUSY = 1'b0;
//Reset After
#(PL_RESET_TIME);
inRESET = 1'b1;
//GCI Init
#(PL_BUS_CYCLE*32);
while(oGCI_BUSY) #(PL_BUS_CYCLE);
iGCI_REQ = 1'b1;
iGCI_DATA = PL_GCI_SIZE;
#(PL_BUS_CYCLE);
iGCI_REQ = 1'b0;
iGCI_DATA = 32'h0;
//#15000000 begin
#1500000000 begin
$stop;
end
end
/******************************************************
Memory Model
******************************************************/
sim_memory_model #(1, "tb_inst_test.hex") MEMORY_MODEL(
.iCLOCK(iCORE_CLOCK),
.inRESET(inRESET),
//Req
.iMEMORY_REQ(oMEMORY_REQ),
.oMEMORY_LOCK(iMEMORY_LOCK),
.iMEMORY_ORDER(oMEMORY_ORDER), //00=Byte Order 01=2Byte Order 10= Word Order 11= None
.iMEMORY_MASK(oMEMORY_MASK),
.iMEMORY_RW(oMEMORY_RW), //1:Write | 0:Read
.iMEMORY_ADDR(oMEMORY_ADDR),
//This -> Data RAM
.iMEMORY_DATA(oMEMORY_DATA),
//Data RAM -> This
.oMEMORY_VALID(iMEMORY_VALID),
.iMEMORY_LOCK(oMEMORY_BUSY),
.oMEMORY_DATA(iMEMORY_DATA)
);
always@(posedge iCORE_CLOCK)begin
if(inRESET)begin
//task_disp_branch();
task_disp_loadstore();
end
end
/******************************************************
Assertion
******************************************************/
/*
reg assert_check_flag;
reg [31:0] assert_wrong_number;
reg [31:0] assert_wrong_type;
reg [31:0] assert_result;
reg [31:0] assert_expect;
always@(posedge iCORE_CLOCK)begin
if(inRESET && oMEMORY_REQ && !iMEMORY_LOCK && oMEMORY_ORDER == 2'h2 && oMEMORY_RW)begin
//Finish Check
if(oMEMORY_ADDR == 32'h0002_0004)begin
if(!assert_check_flag)begin
$display("[SIM-ERR]Wrong Data.");
$display("[SIM-ERR]Wrong Type : %d", assert_wrong_type);
$display("[SIM-ERR]Index:%d, Expect:%x, Result:%x", assert_wrong_number, assert_expect, assert_result);
$display("[SIM-ERR]Simulation Finished.");
$finish;
end
else begin
$display("[SIM-OK]Simulation Finished.");
$finish;
end
end
//Check Flag
else if(oMEMORY_ADDR == 32'h0002_0000)begin
assert_check_flag = oMEMORY_DATA[24];
end
//Error Number
else if(oMEMORY_ADDR == 32'h0002_000c)begin
assert_wrong_number = {oMEMORY_DATA[7:0], oMEMORY_DATA[15:8], oMEMORY_DATA[23:16], oMEMORY_DATA[31:24]};
end
//Error Type
else if(oMEMORY_ADDR == 32'h0002_0008)begin
assert_wrong_type = {oMEMORY_DATA[7:0], oMEMORY_DATA[15:8], oMEMORY_DATA[23:16], oMEMORY_DATA[31:24]};
end
//Error Result
else if(oMEMORY_ADDR == 32'h0002_0010)begin
assert_result = {oMEMORY_DATA[7:0], oMEMORY_DATA[15:8], oMEMORY_DATA[23:16], oMEMORY_DATA[31:24]};
end
//Error Expect
else if(oMEMORY_ADDR == 32'h0002_0014)begin
assert_expect = {oMEMORY_DATA[7:0], oMEMORY_DATA[15:8], oMEMORY_DATA[23:16], oMEMORY_DATA[31:24]};
end
end
end
*/
endmodule
`default_nettype wire
|
/* Module from the schematic_gui program written by Andreas Ehliar <[email protected]>
This Verilog file is licensed under the CC0 license. */
module mux3 #(parameter WIREWIDTH = 1) (input wire [1:0] s,
input wire [WIREWIDTH:0] d0, d1, d2,
output reg [WIREWIDTH:0] o);
initial begin
$schematic_boundingbox(40,160);
$schematic_polygonstart;
$schematic_coord(10,10);
$schematic_coord(30,30);
$schematic_coord(30,130);
$schematic_coord(10,150);
$schematic_polygonend;
$schematic_linestart;
$schematic_coord(20,19);
$schematic_coord(20,10);
$schematic_lineend;
$schematic_connector(d0,0,40);
$schematic_connector(d1,0,80);
$schematic_connector(d2,0,120);
$schematic_connector(o,40,80);
$schematic_connector(s,20,0);
$schematic_symboltext("0", 20,40);
$schematic_symboltext("1", 20,80);
$schematic_symboltext("2", 20,120);
end
always @* begin
case(s)
0: o = d0;
1: o = d1;
default: o = d2;
endcase
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_alignment_pipeline
// Version: 1.0
// Verilog Standard: Verilog-2001
//
// Description: The TX alignment pipeline takes a formatted header and data and
// "aligns" them to create a formatted PKT. The aligner is used in both the TXC
// and TXR engines.
//
// The data interface (TX_DATA) is an interface for N 32-bit FIFOs, where N =
// (C_DATA_WIDTH/32). The START_FLAG signal indicates that the first dword of
// a packet is in FIFO 0 (TX_DATA[31:0]). Each FIFO interface also contains an
// END_FLAG signal in the END_FLAGS bus. When a bit in END_FLAGS bus is asserted,
// its corresponding fifo contains the last dword of data for the current
// packet. START_FLAG, END_FLAG and DATA are all qualified by the VALID signal,
// and read by the READY signal.
//
// The header interface (TX_HDR) presents the entire header in a single cycle on a
// fifo-like read-interface. The interface also contains the metadata signals
// NOPAYLOAD, ABLANKS, and LEN. NOPAYLOAD indicates that the header is not
// associated with a payload. ABLANKS indicates how many blanks are inserted
// between header and payload for address alignment. LEN indicates the length of
// the header (in DWORDS). The previous two signals determine the multiplexer
// schedule.
//
// The aligner is built around N alignment muxes that chose between header and
// data. The aligner uses a multiplexer ROM-based schedule to determine the
// outputs of the alignment muxes. This schedule is listed in the schedules.vh
// include file. It initializes the wSchedule ROM. The ROM is indexed by the
// concatenation of ABLANKS, (Header) LEN, and a saturating counter. The
// saturating counter stops when the selection bits for all multiplexers reach a
// steady state.
//
// See schedules.vh for more information regarding the wSchedule and wTxMuxInputs
// arrays.
//
// Plans:
// - At some point in the future, wSchedule and wTxMuxInputs should be set by
// initialization functions to improve extensibility and reusability, but it may
// decrease readability.
//
// - (with above) Right now the alignment pipeline works for devices that have 3
// or 4 header dwords and insert a maximum of one alignment blank. To extend
// this, wScheduleSelect, and C_MAX_SCHEDULE_LENGTH need to be
// changed. wSchedule select needs to incorporate additional information bits
// (including the minimum header length). and C_MAX_SCHEDULE_LENGTH must be
// calculated using a function (see previous note)
//
// Author: Dustin Richmond (@darichmond)
//----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "trellis.vh" // Defines the user-facing signal widths.
module tx_alignment_pipeline
#(parameter C_PIPELINE_OUTPUT = 1,
parameter C_PIPELINE_DATA_INPUT = 1,
parameter C_PIPELINE_HDR_INPUT = 1,
parameter C_USE_COMPUTE_REG = 1,
parameter C_USE_READY_REG = 1,
parameter C_DATA_WIDTH = 128,
parameter C_MAX_HDR_WIDTH = 128,
parameter C_VENDOR = "ALTERA")
(// Interface: Clocks
input CLK,
// Interface: Reset
input RST_IN,
// Interface: TX DATA FIFOS
input [(C_DATA_WIDTH/32)-1:0] TX_DATA_WORD_VALID,
input [C_DATA_WIDTH-1:0] TX_DATA,
input TX_DATA_START_FLAG,
input TX_DATA_PACKET_VALID,
input [(C_DATA_WIDTH/32)-1:0] TX_DATA_END_FLAGS,
output [(C_DATA_WIDTH/32)-1:0] TX_DATA_WORD_READY,
// Interface: TX HDR
input TX_HDR_VALID,
input [C_MAX_HDR_WIDTH-1:0] TX_HDR,
input [`SIG_LEN_W-1:0] TX_HDR_PAYLOAD_LEN,
input [`SIG_NONPAY_W-1:0] TX_HDR_NONPAY_LEN,
input [`SIG_PACKETLEN_W-1:0] TX_HDR_PACKET_LEN,
input TX_HDR_NOPAYLOAD,
output TX_HDR_READY,
// TX Interface (Unified)
input TX_PKT_READY,
output [C_DATA_WIDTH-1:0] TX_PKT,
output TX_PKT_START_FLAG,
output [clog2s(C_DATA_WIDTH/32)-1:0] TX_PKT_START_OFFSET,
output TX_PKT_END_FLAG,
output [clog2s(C_DATA_WIDTH/32)-1:0] TX_PKT_END_OFFSET,
output TX_PKT_VALID);
`include "functions.vh"
localparam C_OFFSET_WIDTH = clog2s(C_DATA_WIDTH/32);
localparam C_AGGREGATE_WIDTH = (C_DATA_WIDTH+C_MAX_HDR_WIDTH);
localparam C_MASK_WIDTH = (C_DATA_WIDTH/32);
localparam C_NUM_MUXES = (C_DATA_WIDTH/32);
localparam C_MUX_INPUTS = (C_DATA_WIDTH == 32)?5:4;
localparam C_CLOG_MUX_INPUTS = clog2s(C_MUX_INPUTS);
localparam C_MAX_SCHEDULE = (C_DATA_WIDTH == 256)? 2 : (C_DATA_WIDTH == 128)? 3: (C_DATA_WIDTH == 64)? 4: (C_DATA_WIDTH == 32)? 6 : 0;
localparam C_CLOG_MAX_SCHEDULE = clog2s(C_MAX_SCHEDULE);
genvar i;
// Wires from the data interface input registers
wire [(C_DATA_WIDTH/32)-1:0] wTxDataWordValid;
wire wTxDataPacketValid;
wire [(C_DATA_WIDTH/32)-1:0] wTxDataWordReady;
wire [C_DATA_WIDTH-1:0] wTxData;
wire wTxDataStartFlag;
wire [(C_DATA_WIDTH/32)-1:0] wTxDataEndFlags;
wire [(C_DATA_WIDTH/32)-1:0] wTxDataPacketWordValid;
wire [clog2s(C_DATA_WIDTH/32)-1:0] wTxDataEndOffset;
// Wires from the header interface input register
wire wTxHdrReady,_wTxHdrReady,__wTxHdrReady;
wire [C_MAX_HDR_WIDTH -1:0] wTxHdr,_wTxHdr,__wTxHdr;
wire wTxHdrValid,_wTxHdrValid,__wTxHdrValid;
wire wTxHdrNoPayload,_wTxHdrNoPayload,__wTxHdrNoPayload;
wire [`SIG_LEN_W-1:0] wTxHdrPayloadLen,_wTxHdrPayloadLen,__wTxHdrPayloadLen;
wire [`SIG_NONPAY_W-1:0] wTxHdrNonpayLen,_wTxHdrNonpayLen,__wTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wTxHdrPacketLen,_wTxHdrPacketLen,__wTxHdrPacketLen;
wire [`SIG_PACKETLEN_W:0] __wTxHdrPacketLenMinus1;
wire [C_MUX_INPUTS-1:0] __wTxHdrPacketMask;
wire [C_MUX_INPUTS-1:0] __wTxHdrLenMask;
// wSchedule is the array containing all of the schedules for each mux and ready signal
// wSchedule is indexed by the concatenation {Insert Blanks, Header Length, Saturating Counter}
wire [C_CLOG_MUX_INPUTS-1:0] wSchedule[C_NUM_MUXES-1:0][(1<<(3+C_CLOG_MAX_SCHEDULE))-1:0];
// Create an array of mux selects, and a bus of ready signals. The ready
// signals are indicate when a dword is being read from the input fifo and
// are statically determined in the schedules.vh file
wire [(3+C_CLOG_MAX_SCHEDULE)-1:0] wScheduleSelect;
wire [C_NUM_MUXES-1:0] __wTxHdrStartEndReady,_wTxHdrStartEndReady;
wire [C_NUM_MUXES-1:0] __wTxHdrStartReady,_wTxHdrStartReady;
wire [C_NUM_MUXES-1:0] __wTxHdrEndReady,_wTxHdrEndReady;
wire [C_NUM_MUXES-1:0] __wTxHdrSteadyStateReady,_wTxHdrSteadyStateReady;
wire [1:0] wReadyMuxSelect;
wire [C_NUM_MUXES-1:0] wReadyMux[3:0];
// Aggreate the header and the current data inputs into an array.
wire [31:0] wAggregate[C_AGGREGATE_WIDTH/32-1:0];
wire [32*C_MUX_INPUTS-1:0] wTxMuxInputs[C_NUM_MUXES-1:0];
wire [(C_CLOG_MUX_INPUTS*C_NUM_MUXES)-1:0] wTxMuxSelect,_wTxMuxSelect;
wire [C_NUM_MUXES-1:0] wTxMuxSelectDataReady,_wTxMuxSelectDataReady;
wire [C_NUM_MUXES-1:0] wTxMuxSelectDataReadyAndPayload,_wTxMuxSelectDataReadyAndPayload;
wire wTxMuxSelectDataEndFlag,_wTxMuxSelectDataEndFlag;
wire wTxMuxSelectDataStartFlag,_wTxMuxSelectDataStartFlag;
wire wTxMuxSelectPktStartFlag,_wTxMuxSelectPktStartFlag;
wire wTxMuxSelectReady,_wTxMuxSelectReady;
wire wTxMuxSelectValid,_wTxMuxSelectValid;
// Wires from the output of the muxes to the input of the output register stage
// wTxPktReady is asserted when a packet is complete
wire wTxPktReady;
wire wTxPktValid;
wire [C_DATA_WIDTH-1:0] wTxPkt;
wire wTxPktStartFlag;
wire wTxPktEndFlag;
wire [C_OFFSET_WIDTH:0] wTxPktEndOffset; // An additional bit for addition overflow
// Saturating Counter Wires
wire wSatCtrEnable;
wire wSatCtrReset;
wire [C_CLOG_MAX_SCHEDULE-1:0] wSatCtr;
// Packet Cycle Counter Wires
wire wPktCtrEnable;
wire wPktCtrReset;
wire [`SIG_PACKETLEN_W-1:0] wPktCtr;
wire wCounterReset;
`include "schedules.vh"
// Assignments for the Input Register Stage
assign __wTxHdrPacketLenMinus1 = __wTxHdrPacketLen - 1;
assign __wTxHdrSteadyStateReady = {C_NUM_MUXES{1'b1}};
assign __wTxHdrStartReady = {C_NUM_MUXES{1'b1}} >> __wTxHdrNonpayLen[C_OFFSET_WIDTH-1:0];
//assign __wTxHdrEndReady = __wTxHdrPacketMask ROTATE-RIGHT __wTxHdrNonpayLen[C_OFFSET_WIDTH-1:0];
assign __wTxHdrStartEndReady = __wTxHdrLenMask;
// Assignments for the computation stage
// Counter logic
assign wCounterReset = _wTxMuxSelectDataEndFlag & _wTxMuxSelectReady;
assign wSatCtrReset = RST_IN | wCounterReset;
assign wSatCtrEnable = _wTxMuxSelectReady & _wTxMuxSelectValid;
assign wPktCtrReset = RST_IN | wCounterReset;
assign wPktCtrEnable = _wTxMuxSelectReady & _wTxMuxSelectValid;
assign wScheduleSelect = {_wTxHdrNonpayLen[2:0],wSatCtr[C_CLOG_MAX_SCHEDULE-1:0]};
// Ready Mux Logic
assign wReadyMuxSelect[0] = _wTxMuxSelectDataStartFlag;
assign wReadyMuxSelect[1] = _wTxMuxSelectDataEndFlag;
assign wReadyMux[0] = _wTxHdrSteadyStateReady;
assign wReadyMux[1] = _wTxHdrStartReady;
assign wReadyMux[2] = _wTxHdrEndReady;
assign wReadyMux[3] = _wTxHdrStartEndReady;
assign _wTxMuxSelectValid = _wTxHdrValid;
assign _wTxMuxSelectDataReady = wReadyMux[wReadyMuxSelect] & {C_NUM_MUXES{(wPktCtr >= _wTxHdrNonpayLen[`SIG_NONPAY_W-1:clog2s(C_NUM_MUXES)])}};
assign _wTxMuxSelectDataReadyAndPayload = wReadyMux[wReadyMuxSelect] &
{C_NUM_MUXES{(wPktCtr >= _wTxHdrNonpayLen[`SIG_NONPAY_W-1:clog2s(C_NUM_MUXES)])}} &
{C_NUM_MUXES{~_wTxHdrNoPayload}} &
{C_NUM_MUXES{_wTxHdrValid}};
assign _wTxMuxSelectPktStartFlag = wPktCtr == 0;
assign _wTxMuxSelectDataStartFlag = wPktCtr == _wTxHdrNonpayLen[`SIG_NONPAY_W-1:clog2s(C_NUM_MUXES)];
assign _wTxMuxSelectDataEndFlag = ({wPktCtr,{clog2s(C_NUM_MUXES){1'b0}}} + C_NUM_MUXES) >= _wTxHdrPacketLen;// TODO: Simplify
// Assignments for the ready stage
assign wTxHdrReady = (wTxMuxSelectDataEndFlag & wTxMuxSelectValid & wTxMuxSelectReady) | ~wTxMuxSelectValid;
assign wTxMuxSelectReady = (wTxPktReady & wTxHdrNoPayload) |
(wTxPktReady & wTxDataPacketValid) |
(~wTxMuxSelectValid);
assign wTxPktStartFlag = wTxMuxSelectPktStartFlag;
assign wTxPktEndFlag = wTxMuxSelectDataEndFlag;
assign wTxPktEndOffset = wTxHdrPacketLen[C_OFFSET_WIDTH-1:0]-1; // TODO: Retime -1?
assign wTxPktValid = wTxMuxSelectValid & (wTxHdrNoPayload | (~wTxHdrNoPayload & wTxDataPacketValid));
// assign wTxDataWordReady = wTxMuxSelectDataReady & {C_NUM_MUXES{wTxPktReady & wTxMuxSelectValid & wTxDataPacketValid}};
assign wTxDataWordReady = wTxMuxSelectDataReadyAndPayload & {C_NUM_MUXES{wTxPktReady & wTxDataPacketValid}}; // TODO: Change this to bit-wise AND of wTxDataPacketValid
// Assignments for the output stage
assign TX_PKT_START_OFFSET = {C_OFFSET_WIDTH{1'b0}};
assign wTxDataPacketValid = wTxDataPacketWordValid != 0;
/*See comment block at start of module*/
generate
for(i = 0 ; i < C_NUM_MUXES ; i = i + 1) begin : muxes
assign _wTxMuxSelect[i*C_CLOG_MUX_INPUTS +: C_CLOG_MUX_INPUTS] = wSchedule[i][wScheduleSelect];
end
endgenerate
offset_to_mask
#(// Parameters
.C_MASK_SWAP (0),
.C_MASK_WIDTH (C_NUM_MUXES)
/*AUTOINSTPARAM*/)
packet_mask
(
// Outputs
.MASK (__wTxHdrPacketMask),
// Inputs
.OFFSET_ENABLE (1),
.OFFSET (__wTxHdrPacketLenMinus1[clog2s(C_NUM_MUXES)-1:0])
/*AUTOINST*/);
offset_to_mask
#(// Parameters
.C_MASK_SWAP (0),
.C_MASK_WIDTH (C_NUM_MUXES)
/*AUTOINSTPARAM*/)
len_mask
(// Outputs
.MASK (__wTxHdrLenMask),
// Inputs
.OFFSET_ENABLE (1),
.OFFSET (__wTxHdrPayloadLen[clog2s(C_NUM_MUXES)-1:0]-1)
/*AUTOINST*/);
rotate
#(// Parameters
.C_DIRECTION ("RIGHT"),
.C_WIDTH (C_NUM_MUXES)
/*AUTOINSTPARAM*/)
rot_inst
(// Outputs
.RD_DATA (__wTxHdrEndReady),
// Inputs
.WR_DATA (__wTxHdrPacketMask),
.WR_SHIFTAMT (__wTxHdrNonpayLen[C_OFFSET_WIDTH-1:0])
/*AUTOINST*/);
pipeline
#(// Parameters
.C_DEPTH (C_PIPELINE_HDR_INPUT?1:0),
.C_WIDTH (C_MAX_HDR_WIDTH + `SIG_NONPAY_W + `SIG_PACKETLEN_W + `SIG_LEN_W + 1),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
hdr_input_reg
(// Outputs
.WR_DATA_READY (TX_HDR_READY),
.RD_DATA ({__wTxHdr,__wTxHdrNonpayLen,__wTxHdrPacketLen,__wTxHdrPayloadLen,__wTxHdrNoPayload}),
.RD_DATA_VALID (__wTxHdrValid),
// Inputs
.WR_DATA ({TX_HDR,TX_HDR_NONPAY_LEN,TX_HDR_PACKET_LEN,TX_HDR_PAYLOAD_LEN,TX_HDR_NOPAYLOAD}),
.WR_DATA_VALID (TX_HDR_VALID),
.RD_DATA_READY (__wTxHdrReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
pipeline
#(// Parameters
.C_DEPTH (C_USE_COMPUTE_REG?1:0),
.C_WIDTH (C_MAX_HDR_WIDTH + `SIG_NONPAY_W + `SIG_PACKETLEN_W + `SIG_LEN_W + 1 + 4*C_MASK_WIDTH),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
compute_reg
(// Outputs
.WR_DATA_READY (__wTxHdrReady),
.RD_DATA ({_wTxHdr,_wTxHdrNonpayLen,_wTxHdrPacketLen,_wTxHdrPayloadLen,_wTxHdrNoPayload,
_wTxHdrSteadyStateReady,_wTxHdrStartReady,_wTxHdrEndReady,_wTxHdrStartEndReady}),
.RD_DATA_VALID (_wTxHdrValid),
// Inputs
.WR_DATA ({__wTxHdr,__wTxHdrNonpayLen,__wTxHdrPacketLen,__wTxHdrPayloadLen,__wTxHdrNoPayload,
__wTxHdrSteadyStateReady,__wTxHdrStartReady,__wTxHdrEndReady,__wTxHdrStartEndReady}),
.WR_DATA_VALID (__wTxHdrValid),
.RD_DATA_READY (_wTxMuxSelectDataEndFlag & _wTxMuxSelectReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
pipeline
#(// Parameters
.C_DEPTH (C_USE_READY_REG?1:0),
.C_WIDTH (C_MAX_HDR_WIDTH + `SIG_NONPAY_W + `SIG_PACKETLEN_W + `SIG_LEN_W + 1),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
ready_reg
(// Outputs
.WR_DATA_READY (_wTxHdrReady),
.RD_DATA ({wTxHdr,wTxHdrNonpayLen,wTxHdrPacketLen,wTxHdrPayloadLen,wTxHdrNoPayload}),
.RD_DATA_VALID (wTxHdrValid),
// Inputs
.WR_DATA ({_wTxHdr,_wTxHdrNonpayLen,_wTxHdrPacketLen,_wTxHdrPayloadLen,_wTxHdrNoPayload}),
.WR_DATA_VALID (_wTxHdrValid),
.RD_DATA_READY (wTxHdrReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
pipeline
#(// Parameters
.C_DEPTH (C_USE_READY_REG?1:0),
.C_WIDTH (2*C_NUM_MUXES + C_CLOG_MUX_INPUTS * C_NUM_MUXES + 3),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
select_reg
(// Outputs
.WR_DATA_READY (_wTxMuxSelectReady),
.RD_DATA ({wTxMuxSelectDataReady,wTxMuxSelect,
wTxMuxSelectDataEndFlag,wTxMuxSelectDataStartFlag,
wTxMuxSelectPktStartFlag,
wTxMuxSelectDataReadyAndPayload}),
.RD_DATA_VALID (wTxMuxSelectValid),
// Inputs
.WR_DATA ({_wTxMuxSelectDataReady,_wTxMuxSelect,
_wTxMuxSelectDataEndFlag,_wTxMuxSelectDataStartFlag,
_wTxMuxSelectPktStartFlag,
_wTxMuxSelectDataReadyAndPayload}),
.WR_DATA_VALID (_wTxMuxSelectValid),
.RD_DATA_READY (wTxMuxSelectReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
counter
#(// Parameters
.C_MAX_VALUE (C_MAX_SCHEDULE-1),
.C_SAT_VALUE (C_MAX_SCHEDULE-1),
.C_RST_VALUE (0)
/*AUTOINSTPARAM*/)
satctr_inst
(// Outputs
.VALUE (wSatCtr),
// Inputs
.CLK (CLK),
.RST_IN (wSatCtrReset),
.ENABLE (wSatCtrEnable)
/*AUTOINST*/);
counter
#(// Parameters
.C_MAX_VALUE (1<<`SIG_PACKETLEN_W),
.C_SAT_VALUE (1<<`SIG_PACKETLEN_W + 1), // Never saturate
.C_RST_VALUE (0)
/*AUTOINSTPARAM*/)
pktctr_inst
(// Outputs
.VALUE (wPktCtr),
// Inputs
.CLK (CLK),
.RST_IN (wPktCtrReset),
.ENABLE (wPktCtrEnable)
/*AUTOINST*/);
generate
for( i = 0 ; i < C_MAX_HDR_WIDTH/32 ; i = i + 1) begin : gen_aggregate
assign wAggregate[i] = wTxHdr[i*32 +: 32];
end
// pipeline
// #(// Parameters
// .C_DEPTH (C_PIPELINE_DATA_INPUT?1:0),
// .C_WIDTH (1),
// .C_USE_MEMORY (0)
// /*AUTOINSTPARAM*/)
// packet_valid_register
// (// Outputs
// .WR_DATA_READY (),
// .RD_DATA (),
// .RD_DATA_VALID (wTxDataPacketValid),
// // Inputs
// .WR_DATA (),
// .WR_DATA_VALID (TX_DATA_PACKET_VALID | ((wTxDataWordValid & wTxDataEndFlags[i])),
// .RD_DATA_READY (~wTxDataPacketValid |
// ((wTxDataEndFlags & wTxDataWordReady) != 0)),
// // TODO: End flag read? This is odd, you want to read when there is not a valid packet
// /*AUTOINST*/
// // Inputs
// .CLK (CLK),
// .RST_IN (RST_IN));
for( i = 0; i < C_NUM_MUXES ; i = i + 1) begin : gen_data_input_regs
assign wAggregate[i + C_MAX_HDR_WIDTH/32] = wTxData[32*i +: 32];
pipeline
#(// Parameters
.C_DEPTH (C_PIPELINE_DATA_INPUT?1:0),
.C_WIDTH (32),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
data_register_
(// Outputs
.WR_DATA_READY (TX_DATA_WORD_READY[i]),
.RD_DATA (wTxData[32*i +: 32]),
.RD_DATA_VALID (wTxDataWordValid[i]),
// Inputs
.WR_DATA (TX_DATA[32*i +: 32]),
.WR_DATA_VALID (TX_DATA_WORD_VALID[i]),
.RD_DATA_READY (wTxDataWordReady[i]),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
pipeline
#(// Parameters
.C_DEPTH (C_PIPELINE_DATA_INPUT?1:0),
.C_WIDTH (1),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
packet_valid_register
(// Outputs
.WR_DATA_READY (),
.RD_DATA (),
.RD_DATA_VALID (wTxDataPacketWordValid[i]),
// Inputs
.WR_DATA (),
.WR_DATA_VALID ((TX_DATA_END_FLAGS[i] & TX_DATA_WORD_VALID[i]) |
(TX_DATA_PACKET_VALID & TX_DATA_WORD_VALID[i] & (TX_DATA_END_FLAGS == 0))),
.RD_DATA_READY (wTxDataWordReady[i] | ~wTxDataPacketWordValid[i]),
// TODO: End flag read? This is odd, you want to read when there is not a valid packet
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
end
for( i = 0 ; i < C_NUM_MUXES ; i = i + 1) begin : gen_packet_format_multiplexers
mux
#(
// Parameters
.C_NUM_INPUTS (C_MUX_INPUTS),
.C_CLOG_NUM_INPUTS (C_CLOG_MUX_INPUTS),
.C_WIDTH (32),
.C_MUX_TYPE ("SELECT")
/*AUTOINSTPARAM*/)
dw_mux_
(
// Outputs
.MUX_OUTPUT (wTxPkt[32*i +: 32]),
// Inputs
.MUX_INPUTS (wTxMuxInputs[i]),
.MUX_SELECT (wTxMuxSelect[i*C_CLOG_MUX_INPUTS +: C_CLOG_MUX_INPUTS])
/*AUTOINST*/);
end
endgenerate
pipeline
#(
// Parameters
.C_DEPTH (C_PIPELINE_OUTPUT?1:0),
.C_WIDTH (C_DATA_WIDTH + 2 + C_OFFSET_WIDTH),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
output_register_inst
(
// Outputs
.WR_DATA_READY (wTxPktReady),
.RD_DATA ({TX_PKT,TX_PKT_START_FLAG,TX_PKT_END_FLAG,TX_PKT_END_OFFSET}),
.RD_DATA_VALID (TX_PKT_VALID),
// Inputs
.WR_DATA ({wTxPkt,wTxPktStartFlag,wTxPktEndFlag,wTxPktEndOffset[C_OFFSET_WIDTH-1:0]}),
.WR_DATA_VALID (wTxPktValid),
.RD_DATA_READY (TX_PKT_READY),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../common/")
// End:
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: RIT
// Engineer: Cody Cziesler and Nick Desaulniers
//
// Create Date: 11:47:57 04/07/2011
// Design Name: memory
// Module Name: memory
// Project Name: omicron
// Target Devices: Xilinx Spartan-3E
// Tool versions: ISE M.70d
// Description: The memory stage of the pipeline
//
// Revision:
// Revision 0.01 - File Created
// Revision 1.00 - Instantiated data memory, no branch control logic, untested
// Revision 2.00 - Added cu_branch, implemented m_branch_en (CRC)
// Revision 3.00 - Modified branch control decoding (NAD)
// Revision 4.00 - Fixed typo, spacing (CRC)
// Revision 5.00 - Changed size of cu_branch input (CRC)
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module memory(
input clk_n,
input rst_n,
input [15:0] ex_alu_result,
input [15:0] ex_register2_data,
input [2:0] ex_reg_waddr,
input cu_dm_wea,
input [1:0] cu_branch,
input ex_alu_z,
output [15:0] m_alu_result,
output [15:0] m_dm_dout,
output [2:0] m_reg_waddr,
output reg m_branch_en
);
// Branch Parameters
parameter DBR = 2'b00; // Don't Branch
parameter BEQ = 2'b01;
parameter BNE = 2'b10;
parameter JMP = 2'b11;
assign m_alu_result = ex_alu_result;
assign m_reg_waddr = ex_reg_waddr;
// Branch Control Decoding
// m_branch_en should be 1 if branching or jumping
always@( posedge clk_n or negedge rst_n ) begin
if( rst_n == 1'b0 ) begin
m_branch_en <= 1'b0;
end else begin
case( cu_branch )
DBR: begin // Don't Branch
m_branch_en <= 1'b0;
end
BEQ: begin
if( ex_alu_z == 1'b1 ) begin // BEQ && No Difference = 1
m_branch_en <= 1'b1;
end else begin // BEQ && Difference = 0
m_branch_en <= 1'b0;
end
end
BNE: begin
if( ex_alu_z == 1'b1 ) begin // BNE && No Difference = 0
m_branch_en <= 1'b0;
end else begin // BNE && Difference = 1
m_branch_en <= 1'b1;
end
end
JMP: begin // Jump (Always Branch)
m_branch_en <= 1'b1;
end
endcase
end
end
data_mem i_data_mem (
.clka(clk_n),
.rsta(1'b0),
.wea(cu_dm_wea),
.addra(ex_alu_result[6:0]),
.dina(ex_register2_data),
.douta(m_dm_dout[15:0])
);
endmodule
|
module sr_04(echo,clk,rst_n,distance_reg);
input echo,clk,rst_n;
output distance_reg;
reg[9:0]distance_reg,cnt;
wire start,finish;
reg echo_reg1,echo_reg2;
parameter idle=2'b00;
parameter state1=2'b01;
parameter state2=2'b10;
reg [1:0]state;
assign start=echo_reg1&~echo_reg2; //posedge
assign finish=~echo_reg1&echo_reg2; //negedge
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)begin echo_reg1<=0;echo_reg2<=0;end
else begin echo_reg1<=echo;echo_reg2<=echo_reg1;end
if(!rst_n)begin state<=idle;cnt<=0;end
else begin
case(state)
idle: begin
if(start)begin state<=state1;end
else begin state<=idle;end
end
state1:begin
if(finish)begin state<=state2;end
else begin cnt<=cnt+1'b1;state<=state1;end
end
state2:begin
cnt<=0;
distance_reg<=cnt;
state<=idle;
end
default: state<=idle;
endcase
end
end
endmodule |
//Register File
module regfile (
clk, // Clock
x, //External Input
ld, //Whether or not to load destination register from extenral input
d, //Destination register
sa, //1st Source Register
sb, // 2nd Source Register
a, // Output a
b // Output b
);
parameter n = 16; //n bits per register
parameter k = 4; //2^k registers
//--- Input Ports ---
input clk;
input [n-1:0] x;
input ld;
input [k-1:0] d, sa, sb;
//--- Output Ports ---
output wire [n - 1:0] a, b;
//-- Internal Data ---
wire [n - 1:0] a0, a1, b0, b1;
wire ld0, ld1;
generate
// Base case of 2 regfiles left
if (k == 1) begin
regfile1 #(.n(n)) rfile1A(clk, x, ld0, a0, b0);
regfile1 #(.n(n)) rfile1B(clk, x, ld1, a1, b1);
// 2^k bit regfile
end else begin
regfile #(.k(k-1), .n(n)) rFileA(clk, x, ld0, d[k-2:0], sa[k-2:0], sb[k-2:0], a0, b0);
regfile #(.k(k-1), .n(n)) rFileB(clk, x, ld1, d[k-2:0], sa[k-2:0], sb[k-2:0], a1, b1);
end
endgenerate
function [n-1:0] mux1w;
input v;
input [n-1:0]x1;
input [n-1:0]x2;
begin
if (v) begin
mux1w = x2;
end else begin
mux1w = x1;
end
end
endfunction
assign ld0 = (!d[k-1]) & ld;
assign ld1 = d[k-1] & ld;
assign a = mux1w(sa[k-1], a0, a1);
assign b = mux1w(sb[k-1], b0, b1);
endmodule
module regfile1 (
clk, // Clock
x, //External Input
ld, //Whether or not to load destination register from external input
r, // Output a
r // Output b
);
parameter n = 16; //n bit register
//--- Inputs ---
input clk;
input [n - 1: 0] x;
input ld;
//--- Outputs ---
output reg [n-1:0] r;
always @(posedge clk) begin
if (ld) begin
r <= x;
end else begin
r <= r;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYMETAL6S4S_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__DLYMETAL6S4S_PP_BLACKBOX_V
/**
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
* horizontal route.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlymetal6s4s (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYMETAL6S4S_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUF_0_V
`define SKY130_FD_SC_LP__BUF_0_V
/**
* buf: Buffer.
*
* Verilog wrapper for buf with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__buf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__buf_0 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__buf_0 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__buf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUF_0_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A311O_TB_V
`define SKY130_FD_SC_LP__A311O_TB_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a311o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 B1 = 1'b1;
#280 C1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 B1 = 1'b0;
#460 C1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 C1 = 1'b1;
#660 B1 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 C1 = 1'bx;
#840 B1 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_lp__a311o dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A311O_TB_V
|
// EMPTY !
// Need to specify directions and connections statically
module xmos_cpld_slice
(
// {ALTERA_ARGS_BEGIN} DO NOT REMOVE THIS LINE!
AB10,
AA11,
AB11,
AA12,
AB12,
AA13,
CLK,
AB13,
AA15,
AB15,
AA16,
AB17,
nRST,
B18,
AA18,
BA18,
BB17,
BA16,
BB15,
BA15,
BB13,
BA13,
BB12,
BA12,
BB11,
BA11,
BB10,
BA9,
BB9,
BA8,
BB7,
BA7,
BB6,
BA6,
BB4,
BA4,
BB2,
BA3,
BB1,
BA1,
AA1,
AB1,
AA3,
AB2,
AA4,
AB4,
P55,
AA6,
AB6,
AA7,
AB7,
AA8,
AB9,
AA9
// {ALTERA_ARGS_END} DO NOT REMOVE THIS LINE!
);
// {ALTERA_IO_BEGIN} DO NOT REMOVE THIS LINE!
inout AB10;
inout AA11;
inout AB11;
inout AA12;
inout AB12;
inout AA13;
input CLK;
inout AB13;
inout AA15;
inout AB15;
inout AA16;
inout AB17;
input nRST;
input B18;
inout AA18;
inout BA18;
inout BB17;
inout BA16;
inout BB15;
inout BA15;
inout BB13;
inout BA13;
inout BB12;
inout BA12;
inout BB11;
inout BA11;
input BB10;
input BA9;
input BB9;
input BA8;
input BB7;
input BA7;
input BB6;
input BA6;
input BB4;
input BA4;
input BB2;
input BA3;
input BB1;
input BA1;
input AA1;
input AB1;
input AA3;
input AB2;
input AA4;
input AB4;
input P55;
input AA6;
input AB6;
input AA7;
input AB7;
inout AA8;
input AB9;
input AA9;
// {ALTERA_IO_END} DO NOT REMOVE THIS LINE!
// {ALTERA_MODULE_BEGIN} DO NOT REMOVE THIS LINE!
// {ALTERA_MODULE_END} DO NOT REMOVE THIS LINE!
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD1_FUNCTIONAL_V
`define SKY130_FD_SC_LS__CLKDLYINV3SD1_FUNCTIONAL_V
/**
* clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__clkdlyinv3sd1 (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV3SD1_FUNCTIONAL_V |
//----------------------------------------------------------------------------
//-- rxleds: Uart-rx example 1
//-- The 4-bits less significant of the character received are shown in the
//-- red leds of the icestick board
//----------------------------------------------------------------------------
//-- (C) BQ. December 2015. Written by Juan Gonzalez (Obijuan)
//-- GPL license
//----------------------------------------------------------------------------
`default_nettype none
`include "baudgen.vh"
//-- Top entity
module rxleds #(
parameter BAUDRATE = `B115200
)(
input wire clk, //-- System clock
input wire rx, //-- Serial input
output reg [3:0] leds //-- Red leds
);
//-- Received character signal
wire rcv;
//-- Received data
wire [7:0] data;
//-- Reset signal
reg rstn = 0;
//-- Initialization
always @(posedge clk)
rstn <= 1;
//-- Receiver unit instantation
uart_rx #(BAUDRATE)
RX0 (.clk(clk), //-- System clock
.rstn(rstn), //-- Reset (Active low)
.rx(rx), //-- Serial input
.rcv(rcv), //-- Character received notification (1)
.data(data) //-- Character received
);
//-- Register the character received and show its 4 less significant leds
//-- in the icestick leds
always @(posedge clk)
if (!rstn)
leds <= 0;
//-- When there is data available, capture it!
else if (rcv == 1'b1)
leds <= data[3:0];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFRTN_TB_V
`define SKY130_FD_SC_LP__SDFRTN_TB_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sdfrtn.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg RESET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 D = 1'b1;
#200 RESET_B = 1'b1;
#220 SCD = 1'b1;
#240 SCE = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 D = 1'b0;
#360 RESET_B = 1'b0;
#380 SCD = 1'b0;
#400 SCE = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 SCE = 1'b1;
#600 SCD = 1'b1;
#620 RESET_B = 1'b1;
#640 D = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 SCE = 1'bx;
#760 SCD = 1'bx;
#780 RESET_B = 1'bx;
#800 D = 1'bx;
end
// Create a clock
reg CLK_N;
initial
begin
CLK_N = 1'b0;
end
always
begin
#5 CLK_N = ~CLK_N;
end
sky130_fd_sc_lp__sdfrtn dut (.D(D), .SCD(SCD), .SCE(SCE), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK_N(CLK_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFRTN_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFXTP_2_V
`define SKY130_FD_SC_HS__DFXTP_2_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog wrapper for dfxtp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dfxtp_2 (
CLK ,
D ,
Q ,
VPWR,
VGND
);
input CLK ;
input D ;
output Q ;
input VPWR;
input VGND;
sky130_fd_sc_hs__dfxtp base (
.CLK(CLK),
.D(D),
.Q(Q),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dfxtp_2 (
CLK,
D ,
Q
);
input CLK;
input D ;
output Q ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dfxtp base (
.CLK(CLK),
.D(D),
.Q(Q)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFXTP_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__INV_SYMBOL_V
`define SKY130_FD_SC_MS__INV_SYMBOL_V
/**
* inv: Inverter.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__inv (
//# {{data|Data Signals}}
input A,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__INV_SYMBOL_V
|
// part of NeoGS project
//
// (c) NedoPC 2007-2008
//
// modelling is in tb_dma1.*
// look also at dma_access.png
module dma_access(
input clk,
input rst_n,
input dma_req, // DMA request
input [21:0] dma_addr, // DMA address (2mb)
input dma_rnw, // DMA READ/nWRITE
input [7:0] dma_wd, // DMA data to write
output reg [7:0] dma_rd, // DMA data just read
output reg dma_busynready, // DMA BUSY/nREADY
output reg dma_ack, // positive pulse as dma_busynready goes high
output reg dma_end, // positive pulse as dma_busynready goes low
output wire mem_dma_bus, // DMA taking over the bus
output wire [21:0] mem_dma_addr, // DMA address going to the bus
output wire [7:0] mem_dma_wd, // DMA data going to the bus
input [7:0] mem_dma_rd, // DMA data going from the bus
output wire mem_dma_rnw, // DMA bus direction (1=read, 0=write)
output reg mem_dma_oe, // DMA read strobe going to the bus
output reg mem_dma_we, // DMA write pulse going to the bus
output reg busrq_n, // CPU signals
input busak_n // control
);
reg dma_bus;
reg [21:0] int_dma_addr;
reg int_dma_rnw;
reg [7:0] int_dma_wd;
wire [7:0] int_dma_rd;
assign mem_dma_bus = dma_bus;
assign mem_dma_addr = int_dma_addr;
assign mem_dma_wd = int_dma_wd;
assign mem_dma_rnw = int_dma_rnw;
assign int_dma_rd = mem_dma_rd;
localparam IDLE = 0;
localparam START = 1;
localparam WACK = 2;
localparam READ1 = 3;
localparam READ2 = 4;
localparam WRITE1 = 5;
localparam WRITE2 = 6;
reg [3:0] state;
reg [3:0] next_state;
// for simulation purposes
initial
begin
state <= IDLE;
busrq_n <= 1'b1;
mem_dma_oe <= 1'b1;
mem_dma_we <= 1'b1;
end
// FSM
always @(posedge clk, negedge rst_n)
begin
if( !rst_n )
state <= IDLE;
else
state <= next_state;
end
always @*
begin
case( state )
//////////////////////////////////////////////////////////////////////////////////////////
IDLE:
begin
if( dma_req==1'b1 )
next_state <= START;
else
next_state <= IDLE;
end
//////////////////////////////////////////////////////////////////////////////////////////
START:
begin
next_state <= WACK;
end
//////////////////////////////////////////////////////////////////////////////////////////
WACK:
begin
if( busak_n == 1'b1 ) ///// ACHTUNG WARNING!!! probably use here registered busak?
next_state <= WACK;
else // busak_n == 1'b0
begin
if( int_dma_rnw == 1'b1 ) // read
next_state <= READ1;
else // int_dma_rnw == 1'b0 - write
next_state <= WRITE1;
end
end
//////////////////////////////////////////////////////////////////////////////////////////
READ1:
begin
next_state <= READ2;
end
//////////////////////////////////////////////////////////////////////////////////////////
READ2:
begin
if( dma_req == 1'b0 )
next_state <= IDLE;
else // dma_req == 1'b1
begin
if( dma_rnw == 1'b1 ) // next is read
next_state <= READ1;
else // dma_rnw == 1'b0 - next is write
next_state <= WRITE1;
end
end
//////////////////////////////////////////////////////////////////////////////////////////
WRITE1:
begin
next_state <= WRITE2;
end
//////////////////////////////////////////////////////////////////////////////////////////
WRITE2:
begin
if( dma_req == 1'b0 )
next_state <= IDLE;
else // dma_req == 1'b1
begin
if( dma_rnw == 1'b1 ) // next is read
next_state <= READ1;
else // dma_rnw == 1'b0 - next is write
next_state <= WRITE1;
end
end
//////////////////////////////////////////////////////////////////////////////////////////
endcase
end
always @(posedge clk, negedge rst_n)
begin
if( !rst_n )
begin
busrq_n <= 1'b1;
dma_busynready <= 1'b0;
dma_ack <= 1'b0;
dma_end <= 1'b0;
dma_bus <= 1'b0;
mem_dma_oe <= 1'b1;
end
else case( next_state )
//////////////////////////////////////////////////////////////////////////////////////////
IDLE:
begin
dma_end <= 1'b0;
busrq_n <= 1'b1;
dma_bus <= 1'b0;
mem_dma_oe <= 1'b1;
end
//////////////////////////////////////////////////////////////////////////////////////////
START:
begin
// dma_bus <= 1'b0; // if rst=0>1 and dma_ack=1 --> ??? is this really needed?
busrq_n <= 1'b0;
dma_busynready <= 1'b1;
dma_ack <= 1'b1;
int_dma_rnw <= dma_rnw;
int_dma_addr <= dma_addr;
int_dma_wd <= dma_wd;
end
//////////////////////////////////////////////////////////////////////////////////////////
WACK:
begin
dma_ack <= 1'b0;
end
//////////////////////////////////////////////////////////////////////////////////////////
READ1:
begin
dma_bus <= 1'b1; // take over the bus
mem_dma_oe <= 1'b0;
if( dma_busynready == 1'b0 ) // if we are here from READ2 or WRITE2
begin
dma_busynready <= 1'b1;
dma_ack <= 1'b1;
dma_end <= 1'b0;
int_dma_rnw <= 1'b1;
int_dma_addr <= dma_addr;
end
end
//////////////////////////////////////////////////////////////////////////////////////////
READ2:
begin
dma_busynready <= 1'b0;
dma_ack <= 1'b0;
dma_end <= 1'b1;
dma_rd <= int_dma_rd;
end
//////////////////////////////////////////////////////////////////////////////////////////
WRITE1:
begin
dma_bus <= 1'b1; // take over the bus
mem_dma_oe <= 1'b1;
if( dma_busynready == 1'b0 ) // from READ2 or WRITE2
begin
dma_busynready <= 1'b1;
dma_ack <= 1'b1;
dma_end <= 1'b0;
int_dma_rnw <= 1'b0;
int_dma_addr <= dma_addr;
int_dma_wd <= dma_wd;
end
end
//////////////////////////////////////////////////////////////////////////////////////////
WRITE2:
begin
dma_busynready <= 1'b0;
dma_ack <= 1'b0;
dma_end <= 1'b1;
end
//////////////////////////////////////////////////////////////////////////////////////////
endcase
end
// mem_dma_we generator
always @(negedge clk,negedge rst_n)
begin
if( !rst_n )
mem_dma_we <= 1'b1;
else
begin
if( dma_bus )
begin
if( !int_dma_rnw )
mem_dma_we <= ~mem_dma_we;
end
else
mem_dma_we <= 1'b1;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__EINVP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__EINVP_BEHAVIORAL_PP_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__einvp (
Z ,
A ,
TE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_TE;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_TE, TE, VPWR, VGND );
notif1 notif10 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_TE);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__EINVP_BEHAVIORAL_PP_V |
`timescale 1ns/1ps
module tb;
`include "useful_tasks.v" // some helper tasks
// `include "ahb_driver.v"
reg rst_async; // asynchronous reset
wire rst_n; // synchronous reset (falling edge)
wire done_r;
wire clk;
parameter AW = 12;
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [AW-1:0] HADDR; // From U_AHB_DRIVER of ahb_driver.v
wire [31:0] HRDATA; // From U_CHIP of chip.v
wire HREADY; // From U_AHB_DRIVER of ahb_driver.v
wire HREADYOUT; // From U_CHIP of chip.v
wire HRESP; // From U_CHIP of chip.v
wire HSEL; // From U_AHB_DRIVER of ahb_driver.v
wire [2:0] HSIZE; // From U_AHB_DRIVER of ahb_driver.v
wire [1:0] HTRANS; // From U_AHB_DRIVER of ahb_driver.v
wire [31:0] HWDATA; // From U_AHB_DRIVER of ahb_driver.v
wire HWRITE; // From U_AHB_DRIVER of ahb_driver.v
// End of automatics
/* chip AUTO_TEMPLATE(
.HRESETn (rst_n),
); */
chip #(.AW(AW)) U_CHIP
(
.HCLK (clk),
/*AUTOINST*/
// Outputs
.HRDATA (HRDATA[31:0]),
.HREADYOUT (HREADYOUT),
.HRESP (HRESP),
// Inputs
.HADDR (HADDR[AW-1:0]),
.HREADY (HREADY),
.HRESETn (rst_n), // Templated
.HSEL (HSEL),
.HSIZE (HSIZE[2:0]),
.HTRANS (HTRANS[1:0]),
.HWDATA (HWDATA[31:0]),
.HWRITE (HWRITE));
/* ahb_driver AUTO_TEMPLATE(
.HRESETn (rst_n),
); */
ahb_driver #(.AW(AW)) U_AHB_DRIVER (
.HCLK (clk),
/*AUTOINST*/
// Outputs
.HSEL (HSEL),
.HADDR (HADDR[AW-1:0]),
.HTRANS (HTRANS[1:0]),
.HSIZE (HSIZE[2:0]),
.HWRITE (HWRITE),
.HWDATA (HWDATA[31:0]),
.HREADY (HREADY),
// Inputs
.HRESETn (rst_n), // Templated
.HREADYOUT (HREADYOUT),
.HRDATA (HRDATA[31:0]),
.HRESP (HRESP));
clock_gen U_CLK_GEN (
/*AUTOINST*/
// Outputs
.clk (clk));
/* reset_generator AUTO_TEMPLATE(
); */
reset_generator U_RESET_GEN (
/*AUTOINST*/
// Outputs
.rst_n (rst_n),
// Inputs
.clk (clk),
.rst_async (rst_async));
// Dump all nets to a vcd file called tb.vcd
initial
begin
$dumpfile("tb.vcd");
$dumpvars(0,tb);
end
// Start by pulsing the reset low for some nanoseconds
reg [31:0] tmp;
reg [7:0] tmp8;
initial begin
rst_async = 1'b0;
#100;
rst_async = 1'b1;
@(posedge clk);
@(posedge clk);
#3;
U_AHB_DRIVER.t_write32bits_non_seq(12'h010,32'hCAFEBABE);
@(posedge clk);
#3;
U_AHB_DRIVER.t_write32bits_non_seq(12'h014,32'h12345678);
@(posedge clk);
@(posedge clk);
#3;
U_AHB_DRIVER.t_read32bits_non_seq(12'h010,tmp);
check_32bits(tmp,32'hCAFEBABE);
@(posedge clk);
#3;
U_AHB_DRIVER.t_read32bits_non_seq(12'h014,tmp);
check_32bits(tmp,32'h12345678);
@(posedge clk);
#3;
U_AHB_DRIVER.t_write8bits_non_seq(12'h010,8'h55);
@(posedge clk);
#3;
U_AHB_DRIVER.t_read32bits_non_seq(12'h010,tmp);
check_32bits(tmp,32'hCAFEBA55);
@(posedge clk);
#3;
U_AHB_DRIVER.t_write8bits_non_seq(12'h011,8'hAA);
@(posedge clk);
#3;
U_AHB_DRIVER.t_write8bits_non_seq(12'h012,8'hBB);
@(posedge clk);
#3;
U_AHB_DRIVER.t_write8bits_non_seq(12'h013,8'hCC);
@(posedge clk);
#3;
U_AHB_DRIVER.t_read32bits_non_seq(12'h010,tmp);
check_32bits(tmp,32'hCCBBAA55);
@(posedge clk);
#3;
U_AHB_DRIVER.t_read8bits_non_seq(12'h010,tmp8);
check_8bits(tmp8,8'h55);
@(posedge clk);
#3;
U_AHB_DRIVER.t_read8bits_non_seq(12'h011,tmp8);
check_8bits(tmp8,8'hAA);
@(posedge clk);
#3;
U_AHB_DRIVER.t_read8bits_non_seq(12'h012,tmp8);
check_8bits(tmp8,8'hBB);
@(posedge clk);
#3;
U_AHB_DRIVER.t_read8bits_non_seq(12'h013,tmp8);
check_8bits(tmp8,8'hCC);
// Read immediatly followed by a write (Pipelining)
@(posedge clk);
#3;
U_AHB_DRIVER.t_read_then_write_32bits(12'h010,tmp,12'h014,32'hDEADBEEF);
check_32bits(tmp,32'hCCBBAA55);
U_AHB_DRIVER.t_read32bits_non_seq(12'h014,tmp);
check_32bits(tmp,32'h12345678);
@(posedge clk);
#1000;
$display("-I- Done !");
$finish;
end
// watchdog
initial begin
#100000;
$display("-E- Error (watchdog) !");
$finish;
end
endmodule // tb
/*
Local Variables:
verilog-library-directories:(
"."
)
End:
*/
|
// megafunction wizard: %LPM_MULT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_mult
// ============================================================
// File Name: mult8x8.v
// Megafunction Name(s):
// lpm_mult
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module mult8x8 (
dataa,
datab,
result);
input [7:0] dataa;
input [7:0] datab;
output [15:0] result;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: Latency NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "0"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "8"
// Retrieval info: PRIVATE: WidthB NUMERIC "8"
// Retrieval info: PRIVATE: WidthP NUMERIC "16"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: optimize NUMERIC "0"
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=5"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "16"
// Retrieval info: USED_PORT: dataa 0 0 8 0 INPUT NODEFVAL dataa[7..0]
// Retrieval info: USED_PORT: datab 0 0 8 0 INPUT NODEFVAL datab[7..0]
// Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL result[15..0]
// Retrieval info: CONNECT: @dataa 0 0 8 0 dataa 0 0 8 0
// Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
// Retrieval info: CONNECT: @datab 0 0 8 0 datab 0 0 8 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL mult8x8.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult8x8.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult8x8.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult8x8.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult8x8_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult8x8_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult8x8_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult8x8_wave*.jpg FALSE
// Retrieval info: LIB_FILE: lpm
|
(** * Equiv: Program Equivalence *)
(* $Date: 2012-04-06 19:32:51 -0400 (Fri, 06 Apr 2012) $ *)
Require Export Imp.
(** *** Some general advice for working on problems
- We've tried to make sure that most of the Coq proofs we ask you
to do are similar to proofs that we've provided. Before
starting to work on the homework problems, take the time to work
through our proofs (both informally, on paper, and in Coq) and
make sure you understand them in detail. This will save you a
lot of time.
- The Coq proofs we're doing now are sufficiently complicated that
it is more or less impossible to complete them simply by
"following your nose" or random hacking. You need to start with
an idea about why the property is true and how the proof is
going to go. The best way to do this is to write out at least a
sketch of an informal proof on paper -- one that intuitively
convinces you of the truth of the theorem -- before starting to
work on the formal one.
- Use automation to save work! Some of the proofs in this
chapter's exercises are pretty long if you try to write out all
the cases explicitly. *)
(* ####################################################### *)
(** * Behavioral Equivalence *)
(** In the last chapter, we investigated the correctness of a very
simple program transformation: the [optimize_0plus] function. The
programming language we were considering was the first version of
the language of arithmetic expressions -- with no variables -- so
in that setting it was very easy to define what it _means_ for a
program transformation to be correct: it should always yield a
program that evaluates to the same number as the original.
To go further and talk about the correctness of program
transformations in the full Imp language, we need to consider the
role of variables and state. *)
(* ####################################################### *)
(** ** Definitions *)
(** For [aexp]s and [bexp]s with variables, the definition we want is
clear. We say
that two [aexp]s or [bexp]s are _behaviorally equivalent_ if they
evaluate to the same result _in every state_. *)
Definition aequiv (a1 a2 : aexp) : Prop :=
forall (st:state),
aeval st a1 = aeval st a2.
Definition bequiv (b1 b2 : bexp) : Prop :=
forall (st:state),
beval st b1 = beval st b2.
(** For commands, the situation is a little more subtle. We can't
simply say "two commands are behaviorally equivalent if they
evaluate to the same ending state whenever they are started in the
same initial state," because some commands (in some starting
states) don't terminate in any final state at all! What we need
instead is this: two commands are behaviorally equivalent if, for
any given starting state, they either both diverge or both
terminate in the same final state. A compact way to express this
is "if the first one terminates in a particular state then so does
the second, and vice versa." *)
Definition cequiv (c1 c2 : com) : Prop :=
forall (st st' : state),
(c1 / st || st') <-> (c2 / st || st').
(** **** Exercise: 2 stars, optional (pairs_equiv) *)
(** Which of the following pairs of programs are equivalent? Write
"yes" or "no" for each one.
(a)
WHILE (BLe (ANum 1) (AId X)) DO
X ::= APlus (AId X) (ANum 1)
END
and
WHILE (BLe (ANum 2) (AId X)) DO
X ::= APlus (AId X) (ANum 1)
END
(* no *)
(b)
WHILE BTrue DO
WHILE BFalse DO X ::= APlus (AId X) (ANum 1) END
END
and
WHILE BFalse DO
WHILE BTrue DO X ::= APlus (AId X) (ANum 1) END
END
(* no *)
[] *)
(** **** Exercise: 3 stars (equiv_classes) *)
(** Given the following programs, group together those that are
equivalent in [Imp]. For example, if you think programs (a)
through (h) are all equivalent to each other, but not to (i), your
answer should look like this: {a,b,c,d,e,f,g,h} {i}.
(a)
WHILE X > 0 DO
X ::= X + 1
END
(b)
IFB X = 0 THEN
X ::= X + 1;
Y ::= 1
ELSE
Y ::= 0
FI;
X ::= X - Y;
Y ::= 0
(c)
SKIP
(d)
WHILE X <> 0 DO
X ::= X * Y + 1
END
(e)
Y ::= 0
(f)
Y ::= X + 1;
WHILE X <> Y DO
Y ::= X + 1
END
(g)
WHILE BTrue DO
SKIP
END
(h)
WHILE X <> X DO
X ::= X + 1
END
(i)
WHILE X <> Y DO
X ::= Y + 1
END
(* FILL IN HERE *)
[] *)
(* ####################################################### *)
(** ** Examples *)
(** Here are some simple examples of equivalences of arithmetic
and boolean expressions. *)
Theorem aequiv_example:
aequiv (AMinus (AId X) (AId X)) (ANum 0).
Proof.
intros st. simpl. apply minus_diag.
Qed.
Theorem bequiv_example:
bequiv (BEq (AMinus (AId X) (AId X)) (ANum 0)) BTrue.
Proof.
intros st. unfold beval.
rewrite aequiv_example. reflexivity.
Qed.
(** For examples of command equivalence, let's start by looking at
some trivial program transformations involving [SKIP]: *)
Theorem skip_left: forall c,
cequiv
(SKIP; c)
c.
Proof.
(* WORKED IN CLASS *)
intros c st st'.
split; intros H.
Case "->".
inversion H. subst.
inversion H2. subst.
assumption.
Case "<-".
apply E_Seq with st.
apply E_Skip.
assumption.
Qed.
(** **** Exercise: 2 stars (skip_right) *)
Theorem skip_right: forall c,
cequiv
(c; SKIP)
c.
Proof.
intros c st st'.
split; intros H.
Case "->".
com_cases (destruct c) SCase;
inversion H; subst;
try (inversion H2; subst; assumption);
try (inversion H5; subst; assumption).
Case "<-".
apply E_Seq with st'. assumption.
apply E_Skip.
Qed.
(** [] *)
(** Similarly, here is a simple transformations that simplifies [IFB]
commands: *)
Theorem IFB_true_simple: forall c1 c2,
cequiv
(IFB BTrue THEN c1 ELSE c2 FI)
c1.
Proof.
intros c1 c2.
split; intros H.
Case "->".
inversion H; subst. assumption. inversion H5.
Case "<-".
apply E_IfTrue. reflexivity. assumption. Qed.
(** Of course, few programmers would be tempted to write a conditional
whose guard is literally [BTrue]. A more interesting case is when
the guard is _equivalent_ to true:
_Theorem_: If [b] is equivalent to [BTrue], then [IFB b THEN c1
ELSE c2 FI] is equivalent to [c1].
_Proof_:
- ([->]) We must show, for all [st] and [st'], that if [IFB b
THEN c1 ELSE c2 FI / st || st'] then [c1 / st || st'].
Proceed by cases on the rules that could possibly have been
used to show [IFB b THEN c1 ELSE c2 FI / st || st'], namely
[E_IfTrue] and [E_IfFalse].
- Suppose the final rule rule in the derivation of [IFB b THEN
c1 ELSE c2 FI / st || st'] was [E_IfTrue]. We then have, by
the premises of [E_IfTrue], that [c1 / st || st']. This is
exactly what we set out to prove.
- On the other hand, suppose the final rule in the derivation
of [IFB b THEN c1 ELSE c2 FI / st || st'] was [E_IfFalse].
We then know that [beval st b = false] and [c2 / st || st'].
Recall that [b] is equivalent to [BTrue], i.e. forall [st],
[beval st b = beval st BTrue]. In particular, this means
that [beval st b = true], since [beval st BTrue = true]. But
this is a contradiction, since [E_IfFalse] requires that
[beval st b = false]. Thus, the final rule could not have
been [E_IfFalse].
- ([<-]) We must show, for all [st] and [st'], that if [c1 / st
|| st'] then [IFB b THEN c1 ELSE c2 FI / st || st'].
Since [b] is equivalent to [BTrue], we know that [beval st b] =
[beval st BTrue] = [true]. Together with the assumption that
[c1 / st || st'], we can apply [E_IfTrue] to derive [IFB b THEN
c1 ELSE c2 FI / st || st']. []
Here is the formal version of this proof: *)
Theorem IFB_true: forall b c1 c2,
bequiv b BTrue ->
cequiv
(IFB b THEN c1 ELSE c2 FI)
c1.
Proof.
intros b c1 c2 Hb.
split; intros H.
Case "->".
inversion H; subst.
SCase "b evaluates to true".
assumption.
SCase "b evaluates to false (contradiction)".
rewrite Hb in H5.
inversion H5.
Case "<-".
apply E_IfTrue; try assumption.
rewrite Hb. reflexivity. Qed.
(** **** Exercise: 2 stars, recommended (IFB_false) *)
Theorem IFB_false: forall b c1 c2,
bequiv b BFalse ->
cequiv
(IFB b THEN c1 ELSE c2 FI)
c2.
Proof.
intros b c1 c2 Hb.
split; intros H.
Case "->".
inversion H. subst.
SCase "b evaluates to true (contradiction)".
rewrite Hb in H5.
inversion H5.
SCase "b evaluates to false".
assumption.
Case "<-".
apply E_IfFalse; try assumption.
rewrite Hb. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars (swap_if_branches) *)
Theorem swap_if_branches: forall b e1 e2,
cequiv
(IFB b THEN e1 ELSE e2 FI)
(IFB BNot b THEN e2 ELSE e1 FI).
Proof.
intros b e1 e2.
split; intros H.
Case "->".
inversion H.
subst. apply E_IfFalse.
simpl. rewrite H5. reflexivity. assumption.
subst. apply E_IfTrue.
simpl. rewrite H5. reflexivity. assumption.
Case "<-".
inversion H.
subst. apply E_IfFalse.
simpl in H5. apply negb_true_iff in H5. assumption. assumption.
subst. apply E_IfTrue.
simpl in H5. apply negb_false_iff in H5. assumption. assumption.
Qed.
(** [] *)
(** For [WHILE] loops, we can give a similar pair of theorems. A loop
whose guard is equivalent to [BFalse] is equivalent to [SKIP],
while a loop whose guard is equivalent to [BTrue] is equivalent to
[WHILE BTrue DO SKIP END] (or any other non-terminating program).
The first of these facts is easy. *)
Theorem WHILE_false : forall b c,
bequiv b BFalse ->
cequiv
(WHILE b DO c END)
SKIP.
Proof.
intros b c Hb. split; intros H.
Case "->".
inversion H; subst.
SCase "E_WhileEnd".
apply E_Skip.
SCase "E_WhileLoop".
rewrite Hb in H2. inversion H2.
Case "<-".
inversion H; subst.
apply E_WhileEnd.
rewrite Hb.
reflexivity. Qed.
(** **** Exercise: 2 stars (WHILE_false_informal) *)
(** Write an informal proof of [WHILE_false].
(* FILL IN HERE *)
[]
*)
(** To prove the second fact, we need an auxiliary lemma stating that
[WHILE] loops whose guards are equivalent to [BTrue] never
terminate:
_Lemma_: If [b] is equivalent to [BTrue], then it cannot be the
case that [(WHILE b DO c END) / st || st'].
_Proof_: Suppose that [(WHILE b DO c END) / st || st']. We show,
by induction on a derivation of [(WHILE b DO c END) / st || st'],
that this assumption leads to a contradiction.
- Suppose [(WHILE b DO c END) / st || st'] is proved using rule
[E_WhileEnd]. Then by assumption [beval st b = false]. But
this contradicts the assumption that [b] is equivalent to
[BTrue].
- Suppose [(WHILE b DO c END) / st || st'] is proved using rule
[E_WhileLoop]. Then we are given the induction hypothesis
that [(WHILE b DO c END) / st || st'] is contradictory, which
is exactly what we are trying to prove!
- Since these are the only rules that could have been used to
prove [(WHILE b DO c END) / st || st'], the other cases of
the induction are immediately contradictory. [] *)
Lemma WHILE_true_nonterm : forall b c st st',
bequiv b BTrue ->
~( (WHILE b DO c END) / st || st' ).
Proof.
(* WORKED IN CLASS *)
intros b c st st' Hb.
intros H.
remember (WHILE b DO c END) as cw.
ceval_cases (induction H) Case;
(* Most rules don't apply, and we can rule them out
by inversion *)
inversion Heqcw; subst; clear Heqcw.
(* The two interesting cases are the ones for WHILE loops: *)
Case "E_WhileEnd". (* contradictory -- b is always true! *)
unfold bequiv in Hb.
rewrite Hb in H. inversion H.
Case "E_WhileLoop". (* immediate from the IH *)
apply IHceval2. reflexivity. Qed.
(** **** Exercise: 2 stars, optional (WHILE_true_nonterm_informal) *)
(** Explain what the lemma [WHILE_true_nonterm] means in English.
(* FILL IN HERE *)
*)
(** [] *)
(** **** Exercise: 2 stars, recommended (WHILE_true) *)
(** Hint: You'll want to use [WHILE_true_nonterm] here. *)
Theorem WHILE_true: forall b c,
bequiv b BTrue ->
cequiv
(WHILE b DO c END)
(WHILE BTrue DO SKIP END).
Proof.
intros b c Hb.
split; intros H.
Case "->".
assert (~((WHILE b DO c END) / st || st')) as H'.
apply WHILE_true_nonterm. apply Hb. contradiction.
Case "<-".
assert (~((WHILE BTrue DO SKIP END) / st || st')) as H'.
apply WHILE_true_nonterm. unfold bequiv. reflexivity. contradiction.
Qed.
(** [] *)
Theorem loop_unrolling: forall b c,
cequiv
(WHILE b DO c END)
(IFB b THEN (c; WHILE b DO c END) ELSE SKIP FI).
Proof.
(* WORKED IN CLASS *)
intros b c st st'.
split; intros Hce.
Case "->".
inversion Hce; subst.
SCase "loop doesn't run".
apply E_IfFalse. assumption. apply E_Skip.
SCase "loop runs".
apply E_IfTrue. assumption.
apply E_Seq with (st' := st'0). assumption. assumption.
Case "<-".
inversion Hce; subst.
SCase "loop runs".
inversion H5; subst.
apply E_WhileLoop with (st' := st'0).
assumption. assumption. assumption.
SCase "loop doesn't run".
inversion H5; subst. apply E_WhileEnd. assumption. Qed.
(** **** Exercise: 2 stars, optional (seq_assoc) *)
Theorem seq_assoc : forall c1 c2 c3,
cequiv ((c1;c2);c3) (c1;(c2;c3)).
Proof.
intros c1 c2 c3.
split; intros H.
Case "->".
inversion H. subst.
inversion H2. subst.
apply E_Seq with st'1. assumption.
apply E_Seq with st'0; assumption.
Case "<-".
inversion H. subst.
inversion H5. subst.
apply E_Seq with st'1.
apply E_Seq with st'0; assumption.
assumption.
Qed.
(** [] *)
(** ** The Functional Equivalence Axiom *)
(** Finally, let's look at simple equivalences involving assignments.
For example, we might expect to be able to show that [X ::= AId X]
is equivalent to [SKIP]. However, when we try to show it, we get
stuck in an interesting way. *)
Theorem identity_assignment_first_try : forall (X:id),
cequiv (X ::= AId X) SKIP.
Proof.
intros. split; intro H.
Case "->".
inversion H; subst. simpl.
replace (update st X (st X)) with st.
constructor.
(* Here we're stuck. The goal looks reasonable,
but in fact it is not provable! If we look back
at the set of lemmas we proved about [update] in
the last chapter, we can see that lemma
[update_same] almost does the job, but not quite:
it says that the original and updated states
agree at all values, but this is not the same
thing as saying that they are [=] in Coq's
sense! *)
Admitted.
(** What is going on here? Recall that our states are just
functions from identifiers to values. For Coq, functions are only
equal when their definitions are syntactically the same, modulo
simplification. (This is the only way we can legally apply the
[refl_equal] constructor of the inductively defined proposition
[eq]!) In practice, for functions built up by repeated uses of the
[update] operation, this means that two functions can be proven
equal only if they were constructed using the _same_ [update]
operations, applied in the same order. In the theorem above, the
sequence of updates on the first parameter [cequiv] is one longer
than for the second parameter, so it is no wonder that the
equality doesn't hold. *)
(** This problem is actually quite general. If we try to prove other
simple facts, such as
cequiv (X ::= APlus (AId X ANum 1) ;
X ::= APlus (AId X ANum 1))
(X ::= APlus (AId X ANum 2))
or
cequiv (X ::= ANum 1; Y ::= ANum 2)
(y ::= ANum 2; X ::= ANum 1)
we'll get stuck in the same way: we'll have two functions that
behave the same way on all inputs, but cannot be proven to be [eq]
to each other.
The reasoning principle we would like to use in these situations
is called _functional extensionality_:
forall x, f x = g x
-------------------
f = g
Although this principle is not derivable in Coq's built-in logic,
it is safe to add it as an additional _axiom_. *)
Axiom functional_extensionality : forall {X Y: Type} {f g : X -> Y},
(forall (x: X), f x = g x) -> f = g.
(** It can be shown that adding this axiom doesn't introduce any
inconsistencies into Coq. (In this way, it is similar to adding
one of the classical logic axioms, such as [excluded_middle].) *)
(** With the benefit of this axiom we can prove our theorem. *)
Theorem identity_assignment : forall (X:id),
cequiv
(X ::= AId X)
SKIP.
Proof.
intros. split; intro H.
Case "->".
inversion H; subst. simpl.
replace (update st X (st X)) with st.
constructor.
apply functional_extensionality. intro.
rewrite update_same; reflexivity.
Case "<-".
inversion H; subst.
assert (st' = (update st' X (st' X))).
apply functional_extensionality. intro.
rewrite update_same; reflexivity.
rewrite H0 at 2.
constructor. reflexivity.
Qed.
(** **** Exercise: 2 stars, recommended (assign_aequiv) *)
Theorem assign_aequiv : forall X e,
aequiv (AId X) e ->
cequiv SKIP (X ::= e).
Proof.
intros X e Ha. split; intro H.
Case "->".
replace st' with (update st X (aeval st e)).
apply E_Ass. reflexivity. unfold aequiv in Ha. simpl in Ha.
rewrite <- Ha. inversion H; subst.
apply functional_extensionality. intro.
rewrite update_same; reflexivity.
Case "<-".
inversion H; subst.
unfold aequiv in Ha. simpl in Ha. rewrite <- Ha.
replace (update st X (st X)) with st. apply E_Skip.
apply functional_extensionality. intro.
rewrite update_same; reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars, optional (functional_extensionality_failed_false) *)
(** As we just mentioned, functional extensionality doesn't add
any inconsistencies into Coq. However, consider the following
theorem. Inspired by it, we present an attempt to prove
[False]. Briefly explain why it will fail. *)
Theorem feff_1 : true = false -> False.
Proof.
intros. inversion H.
Qed.
Lemma feff_2 : empty_state = update empty_state X 0.
Proof.
apply functional_extensionality. intros.
destruct x as [n]. destruct n as [| n'].
Case "x = AId 0". reflexivity.
Case "x = AId (S n')". reflexivity.
Qed.
(* Lemma feff_3 : empty_state = update empty_state X 0 -> False.
Proof.
intros. inversion H. (* And this makes no progress! *)
Qed. *)
(** If we were able to prove [feff_3], then together with [feff_2],
a proof of [False] is immediate. Explain why the
[inversion H] fails, though it works in [feff_1]. *)
(* FILL IN HERE *)
(* ####################################################### *)
(** * Properties of Behavioral Equivalence *)
(** We now turn to developing some of the properties of the program
equivalences we have defined. *)
(* ####################################################### *)
(** ** Behavioral Equivalence is an Equivalence *)
(** First, we verify that the equivalences on [aexps], [bexps], and
[com]s really are _equivalences_ -- i.e., that they are reflexive,
symmetric, and transitive: *)
Lemma refl_aequiv : forall (a : aexp), aequiv a a.
Proof.
intros a st. reflexivity. Qed.
Lemma sym_aequiv : forall (a1 a2 : aexp),
aequiv a1 a2 -> aequiv a2 a1.
Proof.
intros a1 a2 H. intros st. symmetry. apply H. Qed.
Lemma trans_aequiv : forall (a1 a2 a3 : aexp),
aequiv a1 a2 -> aequiv a2 a3 -> aequiv a1 a3.
Proof.
unfold aequiv. intros a1 a2 a3 H12 H23 st.
rewrite (H12 st). rewrite (H23 st). reflexivity. Qed.
Lemma refl_bequiv : forall (b : bexp), bequiv b b.
Proof.
unfold bequiv. intros b st. reflexivity. Qed.
Lemma sym_bequiv : forall (b1 b2 : bexp),
bequiv b1 b2 -> bequiv b2 b1.
Proof.
unfold bequiv. intros b1 b2 H. intros st. symmetry. apply H. Qed.
Lemma trans_bequiv : forall (b1 b2 b3 : bexp),
bequiv b1 b2 -> bequiv b2 b3 -> bequiv b1 b3.
Proof.
unfold bequiv. intros b1 b2 b3 H12 H23 st.
rewrite (H12 st). rewrite (H23 st). reflexivity. Qed.
Lemma refl_cequiv : forall (c : com), cequiv c c.
Proof.
unfold cequiv. intros c st st'. apply iff_refl. Qed.
Lemma sym_cequiv : forall (c1 c2 : com),
cequiv c1 c2 -> cequiv c2 c1.
Proof.
unfold cequiv. intros c1 c2 H st st'.
assert (c1 / st || st' <-> c2 / st || st') as H'.
SCase "Proof of assertion". apply H.
apply iff_sym. assumption.
Qed.
Lemma iff_trans : forall (P1 P2 P3 : Prop),
(P1 <-> P2) -> (P2 <-> P3) -> (P1 <-> P3).
Proof.
intros P1 P2 P3 H12 H23.
inversion H12. inversion H23.
split; intros A.
apply H1. apply H. apply A.
apply H0. apply H2. apply A. Qed.
Lemma trans_cequiv : forall (c1 c2 c3 : com),
cequiv c1 c2 -> cequiv c2 c3 -> cequiv c1 c3.
Proof.
unfold cequiv. intros c1 c2 c3 H12 H23 st st'.
apply iff_trans with (c2 / st || st'). apply H12. apply H23. Qed.
(* ########################################################*)
(** ** Behavioral Equivalence is a Congruence *)
(** Less obviously, behavioral equivalence is also a _congruence_.
That is, the equivalence of two subprograms implies the
equivalence of the larger programs in which they are embedded:
aequiv a1 a1'
-----------------------------
cequiv (i ::= a1) (i ::= a1')
cequiv c1 c1'
cequiv c2 c2'
------------------------
cequiv (c1;c2) (c1';c2')
...and so on. (Note that we are using the inference rule notation
here not as part of a definition, but simply to write down some
valid implications in a readable format. We prove these
implications below.) *)
(** We will see a concrete example of why these congruence
properties are important in the following section (in the proof of
[fold_constants_com_sound]), but the main idea is that they allow
us to replace a small part of a large program with an equivalent
small part and know that the whole large programs are equivalent
_without_ doing an explicit proof about the non-varying parts --
i.e., the "proof burden" of a small change to a large program is
proportional to the size of the change, not the program. *)
Theorem CAss_congruence : forall i a1 a1',
aequiv a1 a1' ->
cequiv (CAss i a1) (CAss i a1').
Proof.
intros i a1 a2 Heqv st st'.
split; intros Hceval.
Case "->".
inversion Hceval. subst. apply E_Ass.
rewrite Heqv. reflexivity.
Case "<-".
inversion Hceval. subst. apply E_Ass.
rewrite Heqv. reflexivity. Qed.
(** The congruence property for loops is a little more interesting,
since it requires induction.
_Theorem_: Equivalence is a congruence for [WHILE] -- that is, if
[b1] is equivalent to [b1'] and [c1] is equivalent to [c1'], then
[WHILE b1 DO c1 END] is equivalent to [WHILE b1' DO c1' END].
_Proof_: Suppose [b1] is equivalent to [b1'] and [c1] is
equivalent to [c1']. We must show, for every [st] and [st'], that
[WHILE b1 DO c1 END / st || st'] iff [WHILE b1' DO c1' END / st
|| st']. We consider the two directions separately.
- ([->]) We show that [WHILE b1 DO c1 END / st || st'] implies
[WHILE b1' DO c1' END / st || st'], by induction on a
derivation of [WHILE b1 DO c1 END / st || st']. The only
nontrivial cases are when the final rule in the derivation is
[E_WhileEnd] or [E_WhileLoop].
- [E_WhileEnd]: In this case, the form of the rule gives us
[beval st b1 = false] and [st = st']. But then, since
[b1] and [b1'] are equivalent, we have [beval st b1' =
false], and [E-WhileEnd] applies, giving us [WHILE b1' DO
c1' END / st || st'], as required.
- [E_WhileLoop]: The form of the rule now gives us [beval st
b1 = true], with [c1 / st || st'0] and [WHILE b1 DO c1
END / st'0 || st'] for some state [st'0], with the
induction hypothesis [WHILE b1' DO c1' END / st'0 ||
st'].
Since [c1] and [c1'] are equivalent, we know that [c1' /
st || st'0]. And since [b1] and [b1'] are equivalent, we
have [beval st b1' = true]. Now [E-WhileLoop] applies,
giving us [WHILE b1' DO c1' END / st || st'], as
required.
- ([<-]) Similar. [] *)
Theorem CWhile_congruence : forall b1 b1' c1 c1',
bequiv b1 b1' -> cequiv c1 c1' ->
cequiv (WHILE b1 DO c1 END) (WHILE b1' DO c1' END).
Proof.
(* WORKED IN CLASS *)
unfold bequiv,cequiv.
intros b1 b1' c1 c1' Hb1e Hc1e st st'.
split; intros Hce.
Case "->".
remember (WHILE b1 DO c1 END) as cwhile.
induction Hce; inversion Heqcwhile; subst.
SCase "E_WhileEnd".
apply E_WhileEnd. rewrite <- Hb1e. apply H.
SCase "E_WhileLoop".
apply E_WhileLoop with (st' := st').
SSCase "show loop runs". rewrite <- Hb1e. apply H.
SSCase "body execution".
apply (Hc1e st st'). apply Hce1.
SSCase "subsequent loop execution".
apply IHHce2. reflexivity.
Case "<-".
remember (WHILE b1' DO c1' END) as c'while.
induction Hce; inversion Heqc'while; subst.
SCase "E_WhileEnd".
apply E_WhileEnd. rewrite -> Hb1e. apply H.
SCase "E_WhileLoop".
apply E_WhileLoop with (st' := st').
SSCase "show loop runs". rewrite -> Hb1e. apply H.
SSCase "body execution".
apply (Hc1e st st'). apply Hce1.
SSCase "subsequent loop execution".
apply IHHce2. reflexivity. Qed.
(** **** Exercise: 3 stars, optional (CSeq_congruence) *)
Theorem CSeq_congruence : forall c1 c1' c2 c2',
cequiv c1 c1' -> cequiv c2 c2' ->
cequiv (c1;c2) (c1';c2').
Proof.
intros c1 c1' c2 c2' H1 H2.
unfold cequiv in H1. unfold cequiv in H2.
split; intro H.
Case "->".
inversion H; subst.
apply E_Seq with st'0.
apply H1. assumption.
apply H2. assumption.
Case "<-".
inversion H; subst.
apply E_Seq with st'0.
apply H1. assumption.
apply H2. assumption.
Qed.
(** [] *)
(** **** Exercise: 3 stars (CIf_congruence) *)
Theorem CIf_congruence : forall b b' c1 c1' c2 c2',
bequiv b b' -> cequiv c1 c1' -> cequiv c2 c2' ->
cequiv (IFB b THEN c1 ELSE c2 FI) (IFB b' THEN c1' ELSE c2' FI).
Proof.
intros b b' c1 c1' c2 c2' Hb H1 H2.
unfold bequiv in Hb.
unfold cequiv in H1.
unfold cequiv in H2.
split; intro H.
Case "->".
inversion H; subst.
apply E_IfTrue.
rewrite <- Hb. assumption.
rewrite <- H1. assumption.
apply E_IfFalse.
rewrite <- Hb. assumption.
rewrite <- H2. assumption.
Case "<-".
inversion H; subst.
apply E_IfTrue.
rewrite Hb. assumption.
rewrite H1. assumption.
apply E_IfFalse.
rewrite Hb. assumption.
rewrite H2. assumption.
Qed.
(** [] *)
(** For example, here are two equivalent programs and a proof of their
equivalence... *)
Example congruence_example:
cequiv
(X ::= ANum 0;
IFB (BEq (AId X) (ANum 0))
THEN
Y ::= ANum 0
ELSE
Y ::= ANum 42
FI)
(X ::= ANum 0;
IFB (BEq (AId X) (ANum 0))
THEN
Y ::= AMinus (AId X) (AId X) (* <--- changed here *)
ELSE
Y ::= ANum 42
FI).
Proof.
apply CSeq_congruence.
apply refl_cequiv.
apply CIf_congruence.
apply refl_bequiv.
apply CAss_congruence. unfold aequiv. simpl.
symmetry. apply minus_diag.
apply refl_cequiv.
Qed.
(* ####################################################### *)
(** * Case Study: Constant Folding *)
(** A _program transformation_ is a function that takes a program
as input and produces some variant of the program as its
output. Compiler optimizations such as constant folding are
a canonical example, but there are many others. *)
(* ####################################################### *)
(** ** Soundness of Program Transformations *)
(** A program transformation is _sound_ if it preserves the
behavior of the original program.
We can define a notion of soundness for translations of
[aexp]s, [bexp]s, and [com]s. *)
Definition atrans_sound (atrans : aexp -> aexp) : Prop :=
forall (a : aexp),
aequiv a (atrans a).
Definition btrans_sound (btrans : bexp -> bexp) : Prop :=
forall (b : bexp),
bequiv b (btrans b).
Definition ctrans_sound (ctrans : com -> com) : Prop :=
forall (c : com),
cequiv c (ctrans c).
(* ######################################################## *)
(** ** The Constant-Folding Transformation *)
(** An expression is _constant_ when it contains no variable
references.
Constant folding is an optimization that finds constant
expressions and replaces them by their values. *)
Fixpoint fold_constants_aexp (a : aexp) : aexp :=
match a with
| ANum n => ANum n
| AId i => AId i
| APlus a1 a2 =>
match (fold_constants_aexp a1, fold_constants_aexp a2) with
| (ANum n1, ANum n2) => ANum (n1 + n2)
| (a1', a2') => APlus a1' a2'
end
| AMinus a1 a2 =>
match (fold_constants_aexp a1, fold_constants_aexp a2) with
| (ANum n1, ANum n2) => ANum (n1 - n2)
| (a1', a2') => AMinus a1' a2'
end
| AMult a1 a2 =>
match (fold_constants_aexp a1, fold_constants_aexp a2) with
| (ANum n1, ANum n2) => ANum (n1 * n2)
| (a1', a2') => AMult a1' a2'
end
end.
Example fold_aexp_ex1 :
fold_constants_aexp
(AMult (APlus (ANum 1) (ANum 2)) (AId X))
= AMult (ANum 3) (AId X).
Proof. reflexivity. Qed.
(** Note that this version of constant folding doesn't eliminate
trivial additions, etc. -- we are focusing attention on a single
optimization for the sake of simplicity. It is not hard to
incorporate other ways of simplifying expressions; the definitions
and proofs just get longer. *)
Example fold_aexp_ex2 :
fold_constants_aexp
(AMinus (AId X) (APlus (AMult (ANum 0) (ANum 6)) (AId Y)))
= AMinus (AId X) (APlus (ANum 0) (AId Y)).
Proof. reflexivity. Qed.
(** Not only can we lift [fold_constants_aexp] to [bexp]s (in the
[BEq] and [BLe] cases), we can also find constant _boolean_
expressions and reduce them in-place. *)
Fixpoint fold_constants_bexp (b : bexp) : bexp :=
match b with
| BTrue => BTrue
| BFalse => BFalse
| BEq a1 a2 =>
match (fold_constants_aexp a1, fold_constants_aexp a2) with
| (ANum n1, ANum n2) => if beq_nat n1 n2 then BTrue else BFalse
| (a1', a2') => BEq a1' a2'
end
| BLe a1 a2 =>
match (fold_constants_aexp a1, fold_constants_aexp a2) with
| (ANum n1, ANum n2) => if ble_nat n1 n2 then BTrue else BFalse
| (a1', a2') => BLe a1' a2'
end
| BNot b1 =>
match (fold_constants_bexp b1) with
| BTrue => BFalse
| BFalse => BTrue
| b1' => BNot b1'
end
| BAnd b1 b2 =>
match (fold_constants_bexp b1, fold_constants_bexp b2) with
| (BTrue, BTrue) => BTrue
| (BTrue, BFalse) => BFalse
| (BFalse, BTrue) => BFalse
| (BFalse, BFalse) => BFalse
| (b1', b2') => BAnd b1' b2'
end
end.
Example fold_bexp_ex1 :
fold_constants_bexp (BAnd BTrue (BNot (BAnd BFalse BTrue)))
= BTrue.
Proof. reflexivity. Qed.
Example fold_bexp_ex2 :
fold_constants_bexp
(BAnd (BEq (AId X) (AId Y))
(BEq (ANum 0)
(AMinus (ANum 2) (APlus (ANum 1) (ANum 1)))))
= BAnd (BEq (AId X) (AId Y)) BTrue.
Proof. reflexivity. Qed.
(** To fold constants in a command, we apply the appropriate folding
functions on all embedded expressions. *)
Fixpoint fold_constants_com (c : com) : com :=
match c with
| SKIP =>
SKIP
| i ::= a =>
CAss i (fold_constants_aexp a)
| c1 ; c2 =>
(fold_constants_com c1) ; (fold_constants_com c2)
| IFB b THEN c1 ELSE c2 FI =>
match fold_constants_bexp b with
| BTrue => fold_constants_com c1
| BFalse => fold_constants_com c2
| b' => IFB b' THEN fold_constants_com c1
ELSE fold_constants_com c2 FI
end
| WHILE b DO c END =>
match fold_constants_bexp b with
| BTrue => WHILE BTrue DO SKIP END
| BFalse => SKIP
| b' => WHILE b' DO (fold_constants_com c) END
end
end.
Example fold_com_ex1 :
fold_constants_com
(X ::= APlus (ANum 4) (ANum 5);
Y ::= AMinus (AId X) (ANum 3);
IFB BEq (AMinus (AId X) (AId Y)) (APlus (ANum 2) (ANum 4)) THEN
SKIP
ELSE
Y ::= ANum 0
FI;
IFB BLe (ANum 0) (AMinus (ANum 4) (APlus (ANum 2) (ANum 1))) THEN
Y ::= ANum 0
ELSE
SKIP
FI;
WHILE BEq (AId Y) (ANum 0) DO
X ::= APlus (AId X) (ANum 1)
END) =
(X ::= ANum 9;
Y ::= AMinus (AId X) (ANum 3);
IFB BEq (AMinus (AId X) (AId Y)) (ANum 6) THEN
SKIP
ELSE
(Y ::= ANum 0)
FI;
Y ::= ANum 0;
WHILE BEq (AId Y) (ANum 0) DO
X ::= APlus (AId X) (ANum 1)
END).
Proof. reflexivity. Qed.
(* ################################################### *)
(** ** Soundness of Constant Folding *)
(** Now we need to show that what we've done is correct. Here's
the proof for arithmetic expressions: *)
Theorem fold_constants_aexp_sound :
atrans_sound fold_constants_aexp.
Proof.
unfold atrans_sound. intros a. unfold aequiv. intros st.
aexp_cases (induction a) Case; simpl;
(* ANum and AId follow immediately *)
try reflexivity;
(* APlus, AMinus, and AMult follow from the IH
and the observation that
aeval st (APlus a1 a2)
= ANum ((aeval st a1) + (aeval st a2))
= aeval st (ANum ((aeval st a1) + (aeval st a2)))
(and similarly for AMinus/minus and AMult/mult) *)
try (destruct (fold_constants_aexp a1);
destruct (fold_constants_aexp a2);
rewrite IHa1; rewrite IHa2; reflexivity). Qed.
(** **** Exercise: 3 stars, optional (fold_bexp_BEq_informal) *)
(** Here is an informal proof of the [BEq] case of the soundness
argument for boolean expression constant folding. Read it
carefully and compare it to the formal proof that follows. Then
fill in the [BLe] case of the formal proof (without looking at the
[BEq] case, if possible).
_Theorem_: The constant folding function for booleans,
[fold_constants_bexp], is sound.
_Proof_: We must show that [b] is equivalent to [fold_constants_bexp],
for all boolean expressions [b]. Proceed by induction on [b]. We
show just the case where [b] has the form [BEq a1 a2].
In this case, we must show
beval st (BEq a1 a2)
= beval st (fold_constants_bexp (BEq a1 a2)).
There are two cases to consider:
- First, suppose [fold_constants_aexp a1 = ANum n1] and
[fold_constants_aexp a2 = ANum n2] for some [n1] and [n2].
In this case, we have
fold_constants_bexp (BEq a1 a2)
= if beq_nat n1 n2 then BTrue else BFalse
and
beval st (BEq a1 a2)
= beq_nat (aeval st a1) (aeval st a2).
By the soundness of constant folding for arithmetic
expressions (Lemma [fold_constants_aexp_sound]), we know
aeval st a1
= aeval st (fold_constants_aexp a1)
= aeval st (ANum n1)
= n1
and
aeval st a2
= aeval st (fold_constants_aexp a2)
= aeval st (ANum n2)
= n2,
so
beval st (BEq a1 a2)
= beq_nat (aeval a1) (aeval a2)
= beq_nat n1 n2.
Also, it is easy to see (by considering the cases [n1 = n2] and
[n1 <> n2] separately) that
beval st (if beq_nat n1 n2 then BTrue else BFalse)
= if beq_nat n1 n2 then beval st BTrue else beval st BFalse
= if beq_nat n1 n2 then true else false
= beq_nat n1 n2.
So
beval st (BEq a1 a2)
= beq_nat n1 n2.
= beval st (if beq_nat n1 n2 then BTrue else BFalse),
]]
as required.
- Otherwise, one of [fold_constants_aexp a1] and
[fold_constants_aexp a2] is not a constant. In this case, we
must show
beval st (BEq a1 a2)
= beval st (BEq (fold_constants_aexp a1)
(fold_constants_aexp a2)),
which, by the definition of [beval], is the same as showing
beq_nat (aeval st a1) (aeval st a2)
= beq_nat (aeval st (fold_constants_aexp a1))
(aeval st (fold_constants_aexp a2)).
But the soundness of constant folding for arithmetic
expressions ([fold_constants_aexp_sound]) gives us
aeval st a1 = aeval st (fold_constants_aexp a1)
aeval st a2 = aeval st (fold_constants_aexp a2),
completing the case. []
*)
Theorem fold_constants_bexp_sound:
btrans_sound fold_constants_bexp.
Proof.
unfold btrans_sound. intros b. unfold bequiv. intros st.
bexp_cases (induction b) Case;
(* BTrue and BFalse are immediate *)
try reflexivity.
Case "BEq".
(* Doing induction when there are a lot of constructors makes
specifying variable names a chore, but Coq doesn't always
choose nice variable names. We can rename entries in the
context with the [rename] tactic: [rename a into a1] will
change [a] to [a1] in the current goal and context. *)
rename a into a1. rename a0 into a2. simpl.
remember (fold_constants_aexp a1) as a1'.
remember (fold_constants_aexp a2) as a2'.
replace (aeval st a1) with (aeval st a1') by
(subst a1'; rewrite <- fold_constants_aexp_sound; reflexivity).
replace (aeval st a2) with (aeval st a2') by
(subst a2'; rewrite <- fold_constants_aexp_sound; reflexivity).
destruct a1'; destruct a2'; try reflexivity.
(* The only interesting case is when both a1 and a2
become constants after folding *)
simpl. destruct (beq_nat n n0); reflexivity.
Case "BLe".
rename a into a1. rename a0 into a2. simpl.
remember (fold_constants_aexp a1) as a1'.
remember (fold_constants_aexp a2) as a2'.
replace (aeval st a1) with (aeval st a1') by
(subst a1'; rewrite <- fold_constants_aexp_sound; reflexivity).
replace (aeval st a2) with (aeval st a2') by
(subst a2'; rewrite <- fold_constants_aexp_sound; reflexivity).
destruct a1'; destruct a2'; try reflexivity.
simpl. destruct (ble_nat n n0); reflexivity.
Case "BNot".
simpl. remember (fold_constants_bexp b) as b'.
rewrite IHb.
destruct b'; reflexivity.
Case "BAnd".
simpl.
remember (fold_constants_bexp b1) as b1'.
remember (fold_constants_bexp b2) as b2'.
rewrite IHb1. rewrite IHb2.
destruct b1'; destruct b2'; reflexivity. Qed.
(** [] *)
(** **** Exercise: 3 stars (fold_constants_com_sound) *)
(** Complete the [WHILE] case of the following proof. *)
Theorem fold_constants_com_sound :
ctrans_sound fold_constants_com.
Proof.
unfold ctrans_sound. intros c.
com_cases (induction c) Case; simpl.
Case "SKIP". apply refl_cequiv.
Case "::=". apply CAss_congruence. apply fold_constants_aexp_sound.
Case ";". apply CSeq_congruence; assumption.
Case "IFB".
assert (bequiv b (fold_constants_bexp b)).
SCase "Pf of assertion". apply fold_constants_bexp_sound.
remember (fold_constants_bexp b) as b'.
destruct b';
(* If the optimization doesn't eliminate the if, then the result
is easy to prove from the IH and fold_constants_bexp_sound *)
try (apply CIf_congruence; assumption).
SCase "b always true".
apply trans_cequiv with c1; try assumption.
apply IFB_true; assumption.
SCase "b always false".
apply trans_cequiv with c2; try assumption.
apply IFB_false; assumption.
Case "WHILE".
assert (bequiv b (fold_constants_bexp b)) by
apply fold_constants_bexp_sound.
remember (fold_constants_bexp b) as b'.
destruct b';
try (apply CWhile_congruence; assumption).
SCase "b always true".
apply WHILE_true. assumption.
SCase "b always false".
apply WHILE_false. assumption.
Qed.
(** [] *)
(* ########################################################## *)
(** *** Soundness of (0 + n) Elimination, Redux *)
(** **** Exercise: 4 stars, optional (optimize_0plus) *)
(** Recall the definition [optimize_0plus] from Imp.v:
Fixpoint optimize_0plus (e:aexp) : aexp :=
match e with
| ANum n =>
ANum n
| APlus (ANum 0) e2 =>
optimize_0plus e2
| APlus e1 e2 =>
APlus (optimize_0plus e1) (optimize_0plus e2)
| AMinus e1 e2 =>
AMinus (optimize_0plus e1) (optimize_0plus e2)
| AMult e1 e2 =>
AMult (optimize_0plus e1) (optimize_0plus e2)
end.
Note that this function is defined over the old [aexp]s,
without states.
Write a new version of this function that accounts for variables,
and analogous ones for [bexp]s and commands:
optimize_0plus_aexp
optimize_0plus_bexp
optimize_0plus_com
Prove that these three functions are sound, as we did for
[fold_constants_*]. Make sure you use the congruence lemmas in
the proof of [optimize_0plus_com] (otherwise it will be _long_!).
Then define an optimizer on commands that first folds
constants (using [fold_constants_com]) and then eliminates [0 + n]
terms (using [optimize_0plus_com]).
- Give a meaningful example of this optimizer's output.
- Prove that the optimizer is sound. (This part should be _very_
easy.) *)
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(** * Proving That Programs Are _Not_ Equivalent *)
(** Suppose that [c1] is a command of the form [X ::= a1; Y ::= a2]
and [c2] is the command [X ::= a1; Y ::= a2'], where [a2'] is
formed by substituting [a1] for all occurrences of [X] in [a2].
For example, [c1] and [c2] might be:
c1 = (X ::= 42 + 53;
Y ::= Y + X)
c2 = (X ::= 42 + 53;
Y ::= Y + (42 + 53))
Clearly, this _particular_ [c1] and [c2] are equivalent. Is this
true in general? *)
(** We will see in a moment that it is not, but it is worthwhile
to pause, now, and see if you can find a counter-example on your
own. *)
(** Here, formally, is the function that substitutes an arithmetic
expression for each occurrence of a given variable in another
expression: *)
Fixpoint subst_aexp (i : id) (u : aexp) (a : aexp) : aexp :=
match a with
| ANum n => ANum n
| AId i' => if beq_id i i' then u else AId i'
| APlus a1 a2 => APlus (subst_aexp i u a1) (subst_aexp i u a2)
| AMinus a1 a2 => AMinus (subst_aexp i u a1) (subst_aexp i u a2)
| AMult a1 a2 => AMult (subst_aexp i u a1) (subst_aexp i u a2)
end.
Example subst_aexp_ex :
subst_aexp X (APlus (ANum 42) (ANum 53)) (APlus (AId Y) (AId X)) =
(APlus (AId Y) (APlus (ANum 42) (ANum 53))).
Proof. reflexivity. Qed.
(** And here is the property we are interested in, expressing the
claim that commands [c1] and [c2] as described above are
always equivalent. *)
Definition subst_equiv_property := forall i1 i2 a1 a2,
cequiv (i1 ::= a1; i2 ::= a2)
(i1 ::= a1; i2 ::= subst_aexp i1 a1 a2).
(** Sadly, the property does _not_ always hold.
_Theorem_: It is not the case that, for all [i1], [i2], [a1],
and [a2],
cequiv (i1 ::= a1; i2 ::= a2)
(i1 ::= a1; i2 ::= subst_aexp i1 a1 a2).
]]
_Proof_: Suppose, for a contradiction, that for all [i1], [i2],
[a1], and [a2], we have
cequiv (i1 ::= a1; i2 ::= a2)
(i1 ::= a1; i2 ::= subst_aexp i1 a1 a2).
Consider the following program:
X ::= APlus (AId X) (ANum 1); Y ::= AId X
Note that
(X ::= APlus (AId X) (ANum 1); Y ::= AId X)
/ empty_state || st1,
where [st1 = { X |-> 1, Y |-> 1 }].
By our assumption, we know that
cequiv (X ::= APlus (AId X) (ANum 1); Y ::= AId X)
(X ::= APlus (AId X) (ANum 1); Y ::= APlus (AId X) (ANum 1))
so, by the definition of [cequiv], we have
(X ::= APlus (AId X) (ANum 1); Y ::= APlus (AId X) (ANum 1))
/ empty_state || st1.
But we can also derive
(X ::= APlus (AId X) (ANum 1); Y ::= APlus (AId X) (ANum 1))
/ empty_state || st2,
where [st2 = { X |-> 1, Y |-> 2 }]. Note that [st1 <> st2]; this
is a contradiction, since [ceval] is deterministic! [] *)
Theorem subst_inequiv :
~ subst_equiv_property.
Proof.
unfold subst_equiv_property.
intros Contra.
(* Here is the counterexample: assuming that [subst_equiv_property]
holds allows us to prove that these two programs are
equivalent... *)
remember (X ::= APlus (AId X) (ANum 1);
Y ::= AId X)
as c1.
remember (X ::= APlus (AId X) (ANum 1);
Y ::= APlus (AId X) (ANum 1))
as c2.
assert (cequiv c1 c2) by (subst; apply Contra).
(* ... allows us to show that the command [c2] can terminate
in two different final states:
st1 = {X |-> 1, Y |-> 1}
st2 = {X |-> 1, Y |-> 2}. *)
remember (update (update empty_state X 1) Y 1) as st1.
remember (update (update empty_state X 1) Y 2) as st2.
assert (H1: c1 / empty_state || st1);
assert (H2: c2 / empty_state || st2);
try (subst;
apply E_Seq with (st' := (update empty_state X 1));
apply E_Ass; reflexivity).
apply H in H1.
(* Finally, we use the fact that evaluation is deterministic
to obtain a contradiction. *)
assert (Hcontra: st1 = st2)
by (apply (ceval_deterministic c2 empty_state); assumption).
assert (Hcontra': st1 Y = st2 Y)
by (rewrite Hcontra; reflexivity).
subst. inversion Hcontra'. Qed.
(** **** Exercise: 4 stars, optional (better_subst_equiv) *)
(** The equivalence we had in mind above was not complete nonsense --
it was actually almost right. To make it correct, we just need to
exclude the case where the variable [X] occurs in the
right-hand-side of the first assignment statement. *)
Inductive var_not_used_in_aexp (X:id) : aexp -> Prop :=
| VNUNum: forall n, var_not_used_in_aexp X (ANum n)
| VNUId: forall Y, X <> Y -> var_not_used_in_aexp X (AId Y)
| VNUPlus: forall a1 a2,
var_not_used_in_aexp X a1 ->
var_not_used_in_aexp X a2 ->
var_not_used_in_aexp X (APlus a1 a2)
| VNUMinus: forall a1 a2,
var_not_used_in_aexp X a1 ->
var_not_used_in_aexp X a2 ->
var_not_used_in_aexp X (AMinus a1 a2)
| VNUMult: forall a1 a2,
var_not_used_in_aexp X a1 ->
var_not_used_in_aexp X a2 ->
var_not_used_in_aexp X (AMult a1 a2).
Lemma aeval_weakening : forall i st a ni,
var_not_used_in_aexp i a ->
aeval (update st i ni) a = aeval st a.
Proof.
intros i st a ni H.
aexp_cases (induction a) Case;
try reflexivity;
try (inversion H; subst;
apply update_neq; apply not_eq_beq_id_false; assumption);
try (inversion H; subst;
apply IHa1 in H2; apply IHa2 in H3;
simpl; rewrite H2; rewrite H3; reflexivity).
Qed.
(** Using [var_not_used_in_aexp], formalize and prove a correct verson
of [subst_equiv_property]. *)
Theorem subst_equiv : forall i1 i2 a1 a2,
var_not_used_in_aexp i1 a1 ->
cequiv (i1 ::= a1; i2 ::= a2)
(i1 ::= a1; i2 ::= subst_aexp i1 a1 a2).
Proof.
Admitted.
(** [] *)
(** **** Exercise: 3 stars, recommended (inequiv_exercise) *)
Theorem inequiv_exercise:
~ cequiv (WHILE BTrue DO SKIP END) SKIP.
Proof.
unfold cequiv. intros Contra.
assert (H1: SKIP / empty_state || empty_state ->
(WHILE BTrue DO SKIP END) / empty_state || empty_state) by
apply Contra.
assert (H2: ~((WHILE BTrue DO SKIP END) / empty_state || empty_state)) by
(apply WHILE_true_nonterm; unfold bequiv; reflexivity).
contradiction H2. apply H1. apply E_Skip.
Qed.
(** [] *)
(** * Extended exercise: Non-deterministic Imp *)
(** As we have seen (in theorem [ceval_deterministic] in the Imp
chapter), Imp's evaluation relation is deterministic. However,
_non_-determinism is an important part of the definition of many
real programming languages. For example, in many imperative
languages (such as C and its relatives), the order in which
function arguments are evaluated is unspecified. The program
fragment
x = 0;
f(++x, x);
might call [f] with arguments [(1, 0)] or [(1, 1)], depending how
the compiler chooses to order things. This can be a little
confusing for programmers, but it gives the compiler writer useful
freedom.
In this exercise, we will extend Imp with a simple
non-deterministic command and study how this change affects
program equivalence. The new command has the syntax [HAVOC X],
where [X] is an identifier. The effect of executing [HAVOC X] is
to assign an _arbitrary_ number to the variable [X],
non-deterministically. For example, after executing the program:
HAVOC Y;
Z ::= Y * 2
the value of [Y] can be any number, while the value of [Z] is
twice that of [Y] (so [Z] is always even). Note that we are not
saying anything about the /probabilities/ of the outcomes -- just
that there are (infinitely) many different outcomes that can
possibly happen after executing this non-deterministic code.
In a sense a variable on which we do [HAVOC] roughly corresponds
to an unitialized variable in the C programming language. After
the [HAVOC] the variable holds a fixed but arbitrary number. Most
sources of nondeterminism in language definitions are there
precisely because programmers don't care which choice is made (and
so it is good to leave it open to the compiler to choose whichever
will run faster).
We call this new language _Himp_ (``Imp extended with [HAVOC]''). *)
Module Himp.
(** To formalize the language, we first add a clause to the definition of
commands. *)
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CHavoc : id -> com. (* <---- new *)
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" | Case_aux c "HAVOC" ].
Notation "'SKIP'" :=
CSkip.
Notation "X '::=' a" :=
(CAss X a) (at level 60).
Notation "c1 ; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'HAVOC' l" := (CHavoc l) (at level 60).
(** **** Exercise: 2 stars (himp_ceval) *)
(** Now, we must extend the operational semantics. We have provided
a template for the [ceval] relation below, specifying the big-step
semantics. What rule(s) must be added to the definition of [ceval]
to formalize the behavior of the [HAVOC] command? *)
Reserved Notation "c1 '/' st '||' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st : state, SKIP / st || st
| E_Ass : forall (st : state) (a1 : aexp) (n : nat) (X : id),
aeval st a1 = n -> (X ::= a1) / st || update st X n
| E_Seq : forall (c1 c2 : com) (st st' st'' : state),
c1 / st || st' -> c2 / st' || st'' -> (c1 ; c2) / st || st''
| E_IfTrue : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = true ->
c1 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_IfFalse : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = false ->
c2 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_WhileEnd : forall (b1 : bexp) (st : state) (c1 : com),
beval st b1 = false -> (WHILE b1 DO c1 END) / st || st
| E_WhileLoop : forall (st st' st'' : state) (b1 : bexp) (c1 : com),
beval st b1 = true ->
c1 / st || st' ->
(WHILE b1 DO c1 END) / st' || st'' ->
(WHILE b1 DO c1 END) / st || st''
| E_Havoc : forall (st : state) (X : id) (n : nat),
(HAVOC X) / st || update st X n
where "c1 '/' st '||' st'" := (ceval c1 st st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass" | Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop"
| Case_aux c "E_Havoc"
].
(** As a sanity check, the following claims should be provable for
your definition: *)
Example havoc_example1 : (HAVOC X) / empty_state || update empty_state X 0.
Proof. constructor. Qed.
Example havoc_example2 :
(SKIP; HAVOC Z) / empty_state || update empty_state Z 42.
Proof. apply E_Seq with empty_state; constructor. Qed.
(** [] *)
(** Finally, we repeat the definition of command equivalence from above: *)
Definition cequiv (c1 c2 : com) : Prop := forall st st' : state,
c1 / st || st' <-> c2 / st || st'.
(** This definition still makes perfect sense in the case of always
terminating programs, so let's apply it to prove some
non-deterministic programs equivalent or non-equivalent. *)
(** **** Exercise: 3 stars (havoc_swap) *)
(** Are the following two programs equivalent? *)
Definition pXY :=
HAVOC X; HAVOC Y.
Definition pYX :=
HAVOC Y; HAVOC X.
(** If you think they are equivalent, prove it. If you think they are
not, prove that. *)
Theorem pXY_cequiv_pYX :
cequiv pXY pYX \/ ~cequiv pXY pYX.
Proof.
left. unfold pXY. unfold pYX.
split; intro H; inversion H; inversion H2; inversion H5; subst.
Case "->".
assert ((HAVOC Y; HAVOC X) / st || update (update st Y n0) X n).
apply E_Seq with (update st Y n0); apply E_Havoc.
assert ((update (update st Y n0) X n) = (update (update st X n) Y n0)).
apply functional_extensionality; intro. apply update_permute. reflexivity.
rewrite <- H1. assumption.
Case "<-".
assert ((HAVOC X; HAVOC Y) / st || update (update st X n0) Y n).
apply E_Seq with (update st X n0); apply E_Havoc.
assert ((update (update st X n0) Y n) = (update (update st Y n) X n0)).
apply functional_extensionality; intro. apply update_permute. reflexivity.
rewrite <- H1. assumption.
Qed.
(** **** Exercise: 4 stars (havoc_copy) *)
(** Are the following two programs equivalent? *)
Definition ptwice :=
HAVOC X; HAVOC Y.
Definition pcopy :=
HAVOC X; Y ::= AId X.
(** If you think they are equivalent, then prove it. If you think they
are not, then prove that. (Hint: You may find the [assert] tactic
useful.) *)
Theorem ptwice_cequiv_pcopy :
cequiv ptwice pcopy \/ ~cequiv ptwice pcopy.
Proof.
right. unfold ptwice. unfold pcopy. unfold cequiv. intro Contra.
remember empty_state as st.
remember (update (update empty_state X 0) Y 1) as st'.
assert ((HAVOC X; HAVOC Y) / st || st' ->
(HAVOC X; Y ::= AId X) / st || st') by apply Contra.
assert (~(HAVOC X; Y ::= AId X) / st || st').
Case "Proof of assertion".
subst. intro Hc.
inversion Hc; subst.
inversion H5; subst.
simpl in H6.
assert ((update (update empty_state X 0) Y 1) X = 0) by reflexivity.
assert ((update (update empty_state X 0) Y 1) Y = 1) by reflexivity.
rewrite <- H6 in H0.
rewrite <- H6 in H1.
assert ((st' X) = 0) by apply H0.
assert ((st' X) = 1) by apply H1.
rewrite H3 in H4. inversion H4.
contradiction H0.
subst. apply H. apply E_Seq with (update empty_state X 0); apply E_Havoc.
Qed.
(** [] *)
(** The definition of program equivalence we are using here has some
subtle consequences on programs that may loop forever. What
[cequiv] says is that the set of possible _terminating_ outcomes
of two equivalent programs is the same. However, in a language
with non-determinism, like Himp, some programs always terminate,
some programs always diverge, and some programs can
non-deterministically terminate in some runs and diverge in
others. The final part of the following optional exercise
illustrates this phenomenon.
*)
(** **** Exercise: 5 stars, optional (havoc_diverge) *)
(** Prove the following program equivalences and non-equivalences, and
try to understand why the [cequiv] definition has the behavior it
has on these examples. *)
Definition p1 : com :=
WHILE (BNot (BEq (AId X) (ANum 0))) DO
HAVOC Y;
X ::= APlus (AId X) (ANum 1)
END.
Definition p2 : com :=
WHILE (BNot (BEq (AId X) (ANum 0))) DO
SKIP
END.
Theorem p1_p2_equiv : cequiv p1 p2.
Proof. (* FILL IN HERE *) Admitted.
Definition p3 : com :=
Z ::= ANum 1;
WHILE (BNot (BEq (AId X) (ANum 0))) DO
HAVOC X;
HAVOC Z
END.
Definition p4 : com :=
X ::= (ANum 0);
Z ::= (ANum 1).
Theorem p3_p4_inequiv : ~ cequiv p3 p4.
Proof. (* FILL IN HERE *) Admitted.
Definition p5 : com :=
WHILE (BNot (BEq (AId X) (ANum 1))) DO
HAVOC X
END.
Definition p6 : com :=
X ::= ANum 1.
Theorem p5_p6_equiv : cequiv p5 p6.
Proof. (* FILL IN HERE *) Admitted.
(** [] *)
End Himp.
(* ####################################################### *)
(** * Doing Without Extensionality (Optional) *)
(** Purists might object to using the [functional_extensionality]
axiom. In general, it can be quite dangerous to add axioms,
particularly several at once (as they may be mutually
inconsistent). In fact, [functional_extensionality] and
[excluded_middle] can both be assumed without any problems, but
some Coq users prefer to avoid such "heavyweight" general
techniques, and instead craft solutions for specific problems that
stay within Coq's standard logic.
For our particular problem here, rather than extending the
definition of equality to do what we want on functions
representing states, we could instead give an explicit notion of
_equivalence_ on states. For example: *)
Definition stequiv (st1 st2 : state) : Prop :=
forall (X:id), st1 X = st2 X.
Notation "st1 '~' st2" := (stequiv st1 st2) (at level 30).
(** It is easy to prove that [stequiv] is an _equivalence_ (i.e., it
is reflexive, symmetric, and transitive), so it partitions the set
of all states into equivalence classes. *)
(** **** Exercise: 1 star, optional (stequiv_refl) *)
Lemma stequiv_refl : forall (st : state),
st ~ st.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star, optional (stequiv_sym) *)
Lemma stequiv_sym : forall (st1 st2 : state),
st1 ~ st2 ->
st2 ~ st1.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star, optional (stequiv_trans) *)
Lemma stequiv_trans : forall (st1 st2 st3 : state),
st1 ~ st2 ->
st2 ~ st3 ->
st1 ~ st3.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Another useful fact... *)
(** **** Exercise: 1 star, optional (stequiv_update) *)
Lemma stequiv_update : forall (st1 st2 : state),
st1 ~ st2 ->
forall (X:id) (n:nat),
update st1 X n ~ update st2 X n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** It is then straightforward to show that [aeval] and [beval] behave
uniformly on all members of an equivalence class: *)
(** **** Exercise: 2 stars, optional (stequiv_aeval) *)
Lemma stequiv_aeval : forall (st1 st2 : state),
st1 ~ st2 ->
forall (a:aexp), aeval st1 a = aeval st2 a.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional (stequiv_beval) *)
Lemma stequiv_beval : forall (st1 st2 : state),
st1 ~ st2 ->
forall (b:bexp), beval st1 b = beval st2 b.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** We can also characterize the behavior of [ceval] on equivalent
states (this result is a bit more complicated to write down
because [ceval] is a relation). *)
Lemma stequiv_ceval: forall (st1 st2 : state),
st1 ~ st2 ->
forall (c: com) (st1': state),
(c / st1 || st1') ->
exists st2' : state,
((c / st2 || st2') /\ st1' ~ st2').
Proof.
intros st1 st2 STEQV c st1' CEV1. generalize dependent st2.
induction CEV1; intros st2 STEQV.
Case "SKIP".
exists st2. split.
constructor.
assumption.
Case ":=".
exists (update st2 X n). split.
constructor. rewrite <- H. symmetry. apply stequiv_aeval.
assumption. apply stequiv_update. assumption.
Case ";".
destruct (IHCEV1_1 st2 STEQV) as [st2' [P1 EQV1]].
destruct (IHCEV1_2 st2' EQV1) as [st2'' [P2 EQV2]].
exists st2''. split.
apply E_Seq with st2'; assumption.
assumption.
Case "IfTrue".
destruct (IHCEV1 st2 STEQV) as [st2' [P EQV]].
exists st2'. split.
apply E_IfTrue. rewrite <- H. symmetry. apply stequiv_beval.
assumption. assumption. assumption.
Case "IfFalse".
destruct (IHCEV1 st2 STEQV) as [st2' [P EQV]].
exists st2'. split.
apply E_IfFalse. rewrite <- H. symmetry. apply stequiv_beval.
assumption. assumption. assumption.
Case "WhileEnd".
exists st2. split.
apply E_WhileEnd. rewrite <- H. symmetry. apply stequiv_beval.
assumption. assumption.
Case "WhileLoop".
destruct (IHCEV1_1 st2 STEQV) as [st2' [P1 EQV1]].
destruct (IHCEV1_2 st2' EQV1) as [st2'' [P2 EQV2]].
exists st2''. split.
apply E_WhileLoop with st2'. rewrite <- H. symmetry.
apply stequiv_beval. assumption. assumption. assumption.
assumption.
Qed.
(** Now we need to redefine [cequiv] to use [~] instead of [=]. It is
not completely trivial to do this in a way that keeps the
definition simple and symmetric, but here is one approach (thanks
to Andrew McCreight). We first define a looser variant of [||]
that "folds in" the notion of equivalence. *)
Reserved Notation "c1 '/' st '||'' st'" (at level 40, st at level 39).
Inductive ceval' : com -> state -> state -> Prop :=
| E_equiv : forall c st st' st'',
c / st || st' ->
st' ~ st'' ->
c / st ||' st''
where "c1 '/' st '||'' st'" := (ceval' c1 st st').
(** Now the revised definition of [cequiv'] looks familiar: *)
Definition cequiv' (c1 c2 : com) : Prop :=
forall (st st' : state),
(c1 / st ||' st') <-> (c2 / st ||' st').
(** A sanity check shows that the original notion of command
equivalence is at least as strong as this new one. (The converse
is not true, naturally.) *)
Lemma cequiv__cequiv' : forall (c1 c2: com),
cequiv c1 c2 -> cequiv' c1 c2.
Proof.
unfold cequiv, cequiv'; split; intros.
inversion H0 ; subst. apply E_equiv with st'0.
apply (H st st'0); assumption. assumption.
inversion H0 ; subst. apply E_equiv with st'0.
apply (H st st'0). assumption. assumption.
Qed.
(** **** Exercise: 2 stars, optional (identity_assignment') *)
(** Finally, here is our example once more... (You can complete the
proof.) *)
Example identity_assignment' :
cequiv' SKIP (X ::= AId X).
Proof.
unfold cequiv'. intros. split; intros.
Case "->".
inversion H; subst; clear H. inversion H0; subst.
apply E_equiv with (update st'0 X (st'0 X)).
constructor. reflexivity. apply stequiv_trans with st'0.
unfold stequiv. intros. apply update_same.
reflexivity. assumption.
Case "<-".
(* FILL IN HERE *) Admitted.
(** [] *)
(** On the whole, this explicit equivalence approach is considerably
harder to work with than relying on functional
extensionality. (Coq does have an advanced mechanism called
"setoids" that makes working with equivalences somewhat easier, by
allowing them to be registered with the system so that standard
rewriting tactics work for them almost as well as for equalities.)
But it is worth knowing about, because it applies even in
situations where the equivalence in question is _not_ over
functions. For example, if we chose to represent state mappings
as binary search trees, we would need to use an explicit
equivalence of this kind. *)
(* ####################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 4 stars, optional (for_while_equiv) *)
(** This exercise extends the optional [add_for_loop] exercise from
Imp.v, where you were asked to extend the language of commands
with C-style [for] loops. Prove that the command:
for (c1 ; b ; c2) {
c3
}
is equivalent to:
c1 ;
WHILE b DO
c3 ;
c2
END
*)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars, optional (swap_noninterfering_assignments) *)
Theorem swap_noninterfering_assignments: forall l1 l2 a1 a2,
l1 <> l2 ->
var_not_used_in_aexp l1 a2 ->
var_not_used_in_aexp l2 a1 ->
cequiv
(l1 ::= a1; l2 ::= a2)
(l2 ::= a2; l1 ::= a1).
Proof.
(* Hint: You'll need [functional_extensionality] *)
(* FILL IN HERE *) Admitted.
(** [] *)
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_multiport_fifo (clock, reset, enable, enq, deq, enq_data, deq_data, full, empty,
preload, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 1;
parameter depth = 2;
parameter enq_count = 2;
parameter deq_count = 2;
parameter preload_count = 0;
parameter pass_thru = 0;
parameter registered = 0;
parameter high_water_mark = 0;
parameter enq_latency = 0;
parameter deq_latency = 0;
parameter value_check = 0;
parameter full_check = 0;
parameter empty_check = 0;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input full, empty;
input [enq_count-1 : 0] enq;
input [deq_count-1 : 0] deq;
input [enq_count*width-1:0] enq_data;
input [deq_count*width-1:0] deq_data;
input [(preload_count?(preload_count*width):1) -1:0] preload;
output [`OVL_FIRE_WIDTH-1 : 0] fire;
// Parameters that should not be edited
parameter assert_name = "ASSERT_MULTIPORT_FIFO";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_SVA
`include "./sva05/ovl_multiport_fifo_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`endmodule // ovl_multiport_fifo
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_P_PP_PG_N_BLACKBOX_V
`define SKY130_FD_SC_HS__UDP_DFF_P_PP_PG_N_BLACKBOX_V
/**
* udp_dff$P_pp$PG$N: Positive edge triggered D flip-flop
* (Q output UDP).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dff$P_pp$PG$N (
Q ,
D ,
CLK ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input D ;
input CLK ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_P_PP_PG_N_BLACKBOX_V
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_soc_interface_wb_8;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] input_axis_tdata = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg output_axis_tready = 0;
reg [7:0] wb_dat_i = 0;
reg wb_ack_i = 0;
reg wb_err_i = 0;
// Outputs
wire input_axis_tready;
wire [7:0] output_axis_tdata;
wire output_axis_tvalid;
wire output_axis_tlast;
wire [35:0] wb_adr_o;
wire [7:0] wb_dat_o;
wire wb_we_o;
wire wb_stb_o;
wire wb_cyc_o;
wire busy;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
output_axis_tready,
wb_dat_i,
wb_ack_i,
wb_err_i);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
wb_adr_o,
wb_dat_o,
wb_we_o,
wb_stb_o,
wb_cyc_o,
busy);
// dump file
$dumpfile("test_soc_interface_wb_8.lxt");
$dumpvars(0, test_soc_interface_wb_8);
end
soc_interface_wb_8
UUT (
.clk(clk),
.rst(rst),
// axi input
.input_axis_tdata(input_axis_tdata),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
// axi output
.output_axis_tdata(output_axis_tdata),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
// WB interface
.wb_adr_o(wb_adr_o),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_we_o(wb_we_o),
.wb_stb_o(wb_stb_o),
.wb_ack_i(wb_ack_i),
.wb_err_i(wb_err_i),
.wb_cyc_o(wb_cyc_o),
// status
.busy(busy)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFRTN_TB_V
`define SKY130_FD_SC_HD__SDFRTN_TB_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__sdfrtn.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg RESET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 D = 1'b1;
#200 RESET_B = 1'b1;
#220 SCD = 1'b1;
#240 SCE = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 D = 1'b0;
#360 RESET_B = 1'b0;
#380 SCD = 1'b0;
#400 SCE = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 SCE = 1'b1;
#600 SCD = 1'b1;
#620 RESET_B = 1'b1;
#640 D = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 SCE = 1'bx;
#760 SCD = 1'bx;
#780 RESET_B = 1'bx;
#800 D = 1'bx;
end
// Create a clock
reg CLK_N;
initial
begin
CLK_N = 1'b0;
end
always
begin
#5 CLK_N = ~CLK_N;
end
sky130_fd_sc_hd__sdfrtn dut (.D(D), .SCD(SCD), .SCE(SCE), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK_N(CLK_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFRTN_TB_V
|
// File: fifo_memTBV.v
// Generated by MyHDL 0.10
// Date: Tue Aug 21 12:53:41 2018
`timescale 1ns/10ps
module fifo_memTBV (
);
// myHDL ->Verilog test bench for `fifo_mem` module
// Note:
// Not a complet testbench, could be better
reg wr = 0;
wire fifo_full;
reg clk = 0;
reg rst_n = 0;
reg rd = 0;
wire fifo_empty;
reg [7:0] data_in = 0;
wire [7:0] data_out;
wire clear;
wire fifo_threshold;
wire fifo_overflow;
wire fifo_underflow;
wire [4:0] fifo_mem0_0_wptr;
wire fifo_mem0_0_fifo_we;
wire [4:0] fifo_mem0_0_rptr;
wire fifo_mem0_0_fifo_rd;
wire fifo_mem0_0_write_pointer0_0_1_2_fifo_we_i;
reg [4:0] fifo_mem0_0_write_pointer0_0_1_2_wptr_i = 0;
wire fifo_mem0_0_read_pointer0_0_1_2_fifo_rd_i;
reg [4:0] fifo_mem0_0_read_pointer0_0_1_2_rptr_i = 0;
reg fifo_mem0_0_fifoStatus0_0_1_2_underflow_set = 0;
reg signed [4:0] fifo_mem0_0_fifoStatus0_0_1_2_pointer_result = 0;
reg fifo_mem0_0_fifoStatus0_0_1_2_pointer_equal = 0;
reg fifo_mem0_0_fifoStatus0_0_1_2_overflow_set = 0;
reg fifo_mem0_0_fifoStatus0_0_1_2_fifo_underflow_i = 0;
reg fifo_mem0_0_fifoStatus0_0_1_2_fifo_threshold_i = 0;
reg fifo_mem0_0_fifoStatus0_0_1_2_fifo_overflow_i = 0;
reg fifo_mem0_0_fifoStatus0_0_1_2_fifo_full_i = 0;
reg fifo_mem0_0_fifoStatus0_0_1_2_fifo_empty_i = 0;
reg fifo_mem0_0_fifoStatus0_0_1_2_fbit_comp = 0;
wire [7:0] TestData_i [0:16-1];
reg [7:0] fifo_mem0_0_memory_array0_0_1_2_data_out_i [0:16-1];
initial begin: INITIALIZE_FIFO_MEM0_0_MEMORY_ARRAY0_0_1_2_DATA_OUT_I
integer i;
for(i=0; i<16; i=i+1) begin
fifo_mem0_0_memory_array0_0_1_2_data_out_i[i] = 0;
end
end
assign clear = 1'd0;
always @(data_out, data_in, fifo_overflow, fifo_empty, fifo_underflow, fifo_threshold, clear, rd, clk, wr, fifo_full, rst_n) begin: FIFO_MEMTBV_PRINT_DATA
$write("%h", wr);
$write(" ");
$write("%h", rd);
$write(" ");
$write("%h", data_in);
$write(" ");
$write("%h", fifo_full);
$write(" ");
$write("%h", fifo_empty);
$write(" ");
$write("%h", fifo_threshold);
$write(" ");
$write("%h", fifo_overflow);
$write(" ");
$write("%h", fifo_underflow);
$write(" ");
$write("%h", data_out);
$write(" ");
$write("%h", clk);
$write(" ");
$write("%h", rst_n);
$write(" ");
$write("%h", clear);
$write("\n");
end
assign fifo_mem0_0_write_pointer0_0_1_2_fifo_we_i = ((!fifo_full) && wr);
always @(posedge clk, negedge rst_n) begin: FIFO_MEMTBV_FIFO_MEM0_0_WRITE_POINTER0_0_1_2_POINTERUPDATE
if (rst_n) begin
fifo_mem0_0_write_pointer0_0_1_2_wptr_i <= 0;
end
else if (fifo_mem0_0_write_pointer0_0_1_2_fifo_we_i) begin
fifo_mem0_0_write_pointer0_0_1_2_wptr_i <= (fifo_mem0_0_write_pointer0_0_1_2_wptr_i + 1);
end
else begin
fifo_mem0_0_write_pointer0_0_1_2_wptr_i <= fifo_mem0_0_write_pointer0_0_1_2_wptr_i;
end
end
assign fifo_mem0_0_fifo_we = fifo_mem0_0_write_pointer0_0_1_2_fifo_we_i;
assign fifo_mem0_0_wptr = fifo_mem0_0_write_pointer0_0_1_2_wptr_i;
assign fifo_mem0_0_read_pointer0_0_1_2_fifo_rd_i = ((!fifo_empty) && rd);
always @(posedge clk, negedge rst_n) begin: FIFO_MEMTBV_FIFO_MEM0_0_READ_POINTER0_0_1_2_POINTERUPDATE
if (rst_n) begin
fifo_mem0_0_read_pointer0_0_1_2_rptr_i <= 0;
end
else if (fifo_mem0_0_read_pointer0_0_1_2_fifo_rd_i) begin
fifo_mem0_0_read_pointer0_0_1_2_rptr_i <= (fifo_mem0_0_read_pointer0_0_1_2_rptr_i + 1);
end
else begin
fifo_mem0_0_read_pointer0_0_1_2_rptr_i <= fifo_mem0_0_read_pointer0_0_1_2_rptr_i;
end
end
assign fifo_mem0_0_fifo_rd = fifo_mem0_0_read_pointer0_0_1_2_fifo_rd_i;
assign fifo_mem0_0_rptr = fifo_mem0_0_read_pointer0_0_1_2_rptr_i;
always @(posedge clk) begin: FIFO_MEMTBV_FIFO_MEM0_0_MEMORY_ARRAY0_0_1_2_UPTAKE
if (fifo_mem0_0_fifo_we) begin
fifo_mem0_0_memory_array0_0_1_2_data_out_i[fifo_mem0_0_wptr[4-1:0]] <= data_in;
end
end
assign data_out = fifo_mem0_0_memory_array0_0_1_2_data_out_i[fifo_mem0_0_rptr[4-1:0]];
always @(negedge clear) begin: FIFO_MEMTBV_FIFO_MEM0_0_MEMORY_ARRAY0_0_1_2_CLEARMEM
integer i;
for (i=0; i<16; i=i+1) begin
fifo_mem0_0_memory_array0_0_1_2_data_out_i[i] <= 0;
end
end
always @(fifo_mem0_0_fifoStatus0_0_1_2_fifo_full_i, fifo_mem0_0_fifoStatus0_0_1_2_fifo_empty_i, rd, fifo_mem0_0_wptr, wr, fifo_mem0_0_rptr) begin: FIFO_MEMTBV_FIFO_MEM0_0_FIFOSTATUS0_0_1_2_LOGIC1
fifo_mem0_0_fifoStatus0_0_1_2_fbit_comp = (fifo_mem0_0_wptr[4] ^ fifo_mem0_0_rptr[4]);
if (($signed({1'b0, fifo_mem0_0_wptr[3-1:0]}) - fifo_mem0_0_rptr[3-1:0])) begin
fifo_mem0_0_fifoStatus0_0_1_2_pointer_equal = 0;
end
else begin
fifo_mem0_0_fifoStatus0_0_1_2_pointer_equal = 1;
end
fifo_mem0_0_fifoStatus0_0_1_2_pointer_result = (fifo_mem0_0_wptr[4-1:0] - fifo_mem0_0_rptr[4-1:0]);
fifo_mem0_0_fifoStatus0_0_1_2_overflow_set = (fifo_mem0_0_fifoStatus0_0_1_2_fifo_full_i & wr);
fifo_mem0_0_fifoStatus0_0_1_2_underflow_set = (fifo_mem0_0_fifoStatus0_0_1_2_fifo_empty_i & rd);
end
always @(fifo_mem0_0_fifoStatus0_0_1_2_fbit_comp, fifo_mem0_0_fifoStatus0_0_1_2_pointer_result, fifo_mem0_0_fifoStatus0_0_1_2_pointer_equal) begin: FIFO_MEMTBV_FIFO_MEM0_0_FIFOSTATUS0_0_1_2_LOGIC2
fifo_mem0_0_fifoStatus0_0_1_2_fifo_full_i = (fifo_mem0_0_fifoStatus0_0_1_2_fbit_comp & fifo_mem0_0_fifoStatus0_0_1_2_pointer_equal);
fifo_mem0_0_fifoStatus0_0_1_2_fifo_empty_i = ((!fifo_mem0_0_fifoStatus0_0_1_2_fbit_comp) & fifo_mem0_0_fifoStatus0_0_1_2_pointer_equal);
if ((fifo_mem0_0_fifoStatus0_0_1_2_pointer_result[4] || fifo_mem0_0_fifoStatus0_0_1_2_pointer_result[3])) begin
fifo_mem0_0_fifoStatus0_0_1_2_fifo_threshold_i = 1;
end
else begin
fifo_mem0_0_fifoStatus0_0_1_2_fifo_threshold_i = 0;
end
end
always @(posedge clk, negedge rst_n) begin: FIFO_MEMTBV_FIFO_MEM0_0_FIFOSTATUS0_0_1_2_OVERFLOWCONTROL
if (rst_n) begin
fifo_mem0_0_fifoStatus0_0_1_2_fifo_overflow_i <= 0;
end
else if (((fifo_mem0_0_fifoStatus0_0_1_2_overflow_set == 1) && (fifo_mem0_0_fifo_rd == 0))) begin
fifo_mem0_0_fifoStatus0_0_1_2_fifo_overflow_i <= 1;
end
else if (fifo_mem0_0_fifo_rd) begin
fifo_mem0_0_fifoStatus0_0_1_2_fifo_overflow_i <= 0;
end
else begin
fifo_mem0_0_fifoStatus0_0_1_2_fifo_overflow_i <= fifo_mem0_0_fifoStatus0_0_1_2_fifo_overflow_i;
end
end
always @(posedge clk, negedge rst_n) begin: FIFO_MEMTBV_FIFO_MEM0_0_FIFOSTATUS0_0_1_2_UNDERFLOWCONTROL
if (rst_n) begin
fifo_mem0_0_fifoStatus0_0_1_2_fifo_underflow_i <= 0;
end
else if (((fifo_mem0_0_fifoStatus0_0_1_2_underflow_set == 1) && (fifo_mem0_0_fifo_we == 0))) begin
fifo_mem0_0_fifoStatus0_0_1_2_fifo_underflow_i <= 1;
end
else if (fifo_mem0_0_fifo_we) begin
fifo_mem0_0_fifoStatus0_0_1_2_fifo_underflow_i <= 0;
end
else begin
fifo_mem0_0_fifoStatus0_0_1_2_fifo_underflow_i <= fifo_mem0_0_fifoStatus0_0_1_2_fifo_underflow_i;
end
end
assign fifo_full = fifo_mem0_0_fifoStatus0_0_1_2_fifo_full_i;
assign fifo_empty = fifo_mem0_0_fifoStatus0_0_1_2_fifo_empty_i;
assign fifo_threshold = fifo_mem0_0_fifoStatus0_0_1_2_fifo_threshold_i;
assign fifo_overflow = fifo_mem0_0_fifoStatus0_0_1_2_fifo_overflow_i;
assign fifo_underflow = fifo_mem0_0_fifoStatus0_0_1_2_fifo_underflow_i;
initial begin: FIFO_MEMTBV_CLK_SIGNAL
while (1'b1) begin
clk <= (!clk);
# 1;
end
end
initial begin: FIFO_MEMTBV_STIMULES
integer i;
i = 0;
while (1'b1) begin
case (i)
'h0: begin
wr <= 1;
rd <= 1;
end
'h10: begin
wr <= 0;
rd <= 1;
end
'h20: begin
wr <= 0;
rd <= 1;
end
'h30: begin
rst_n <= 1;
end
'h31: begin
rst_n <= 0;
end
'h32: begin
wr <= 1;
rd <= 1;
end
default: begin
// pass
end
endcase
if ((i < 16)) begin
data_in <= TestData_i[i];
end
else if (((i >= 16) && (i < 32))) begin
data_in <= TestData_i[($signed({1'b0, i}) - 16)];
end
else if (((i >= 32) && (i < 48))) begin
data_in <= TestData_i[($signed({1'b0, i}) - 32)];
end
else if (((i == 48) || (i == 49))) begin
// pass
end
else begin
data_in <= TestData_i[($signed({1'b0, i}) - 51)];
end
if ((i == 66)) begin
$finish;
end
i = i + 1;
@(posedge clk);
end
end
endmodule
|
// Check that the signedness of the element type of a queue is correctly handled
// whenn calling one of the pop methods with parenthesis.
module test;
bit failed = 1'b0;
`define check(x) \
if (!(x)) begin \
$display("FAILED(%0d): ", `__LINE__, `"x`"); \
failed = 1'b1; \
end
int unsigned x = 10;
int y = 10;
int z;
longint w;
shortint qs[$];
bit [15:0] qu[$];
initial begin
for (int i = 0; i < 16; i++) begin
qu.push_back(-1);
qs.push_back(-1);
end
// These all evaluate as signed
`check($signed(qu.pop_back()) < 0)
`check(qs.pop_back() < 0)
`check($signed(qu.pop_front()) < 0)
`check(qs.pop_front() < 0)
// These all evaluate as unsigned
`check(qu.pop_back() > 0)
`check({qs.pop_back()} > 0)
`check($unsigned(qs.pop_back()) > 0)
`check(qs.pop_back() > 16'h0)
`check(qu.pop_front() > 0)
`check({qs.pop_front()} > 0)
`check($unsigned(qs.pop_front()) > 0)
`check(qs.pop_front() > 16'h0)
// In arithmetic expressions if one operand is unsigned all operands are
// considered unsigned
z = qu.pop_back() + x;
`check(z === 65545)
z = qu.pop_back() + y;
`check(z === 65545)
z = qu.pop_front() + x;
`check(z === 65545)
z = qu.pop_front() + y;
`check(z === 65545)
z = qs.pop_back() + x;
`check(z === 65545)
z = qs.pop_back() + y;
`check(z === 9)
z = qs.pop_front() + x;
`check(z === 65545)
z = qs.pop_front() + y;
`check(z === 9)
// For ternary operators if one operand is unsigned the result is unsigend
z = x ? qu.pop_back() : x;
`check(z === 65535)
z = x ? qu.pop_back() : y;
`check(z === 65535)
z = x ? qu.pop_front() : x;
`check(z === 65535)
z = x ? qu.pop_front() : y;
`check(z === 65535)
z = x ? qs.pop_back() : x;
`check(z === 65535)
z = x ? qs.pop_back() : y;
`check(z === -1)
z = x ? qs.pop_front() : x;
`check(z === 65535)
z = x ? qs.pop_front() : y;
`check(z === -1)
// Size return value is always positive, but check that it gets padded
// properly
w = x ? qu.size() : 64'h123;
`check(w === 64'h4)
if (!failed) begin
$display("PASSED");
end
end
endmodule
|
/*
* File: lsu_mem2reg.v
* Project: pippo
* Designer: kiss@pwrsemi
* Mainteiner: kiss@pwrsemi
* Checker:
* Description:
*
*/
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "def_pippo.v"
module lsu_mem2reg(addr, lsu_op, memdata, regdata);
parameter width = `OPERAND_WIDTH;
//
// I/O
//
input [1:0] addr;
input [`LSUOP_WIDTH-1:0] lsu_op;
input [width-1:0] memdata;
output [width-1:0] regdata;
//
//
//
reg [width-1:0] regdata;
reg [width-1:0] aligned;
//
// Alignment: get data from memory bus
//
always @(addr or memdata) begin
`ifdef pippo_ADDITIONAL_SYNOPSYS_DIRECTIVES
case(addr) // synopsys parallel_case infer_mux
`else
case(addr) // synopsys parallel_case
`endif
2'b00:
aligned = memdata;
2'b01:
aligned = {memdata[23:0], 8'b0};
2'b10:
aligned = {memdata[15:0], 16'b0};
2'b11:
aligned = {memdata[7:0], 24'b0};
endcase
end
//
// Bytes
//
always @(lsu_op or aligned) begin
`ifdef pippo_ADDITIONAL_SYNOPSYS_DIRECTIVES
case(lsu_op) // synopsys parallel_case infer_mux
`else
case(lsu_op) // synopsys parallel_case
`endif
`LSUOP_LBZ: begin
regdata[7:0] = aligned[31:24];
regdata[31:8] = 24'b0;
end
`LSUOP_LHA: begin
regdata[15:0] = aligned[31:16];
regdata[31:16] = {16{aligned[31]}};
end
`LSUOP_LHZ: begin
regdata[15:0] = aligned[31:16];
regdata[31:16] = 16'b0;
end
`LSUOP_LHZB: begin
regdata[15:0] = {aligned[23:16], aligned[31:24]};
regdata[31:16] = 16'b0;
end
`LSUOP_LWZ: begin
regdata[31:0] = aligned[31:0];
end
`LSUOP_LWZB: begin
regdata[31:0] = {aligned[7:0], aligned[15:8], aligned[23:16], aligned[31:24]};
end
default:
regdata[31:0] = aligned[31:0];
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYMETAL6S4S_FUNCTIONAL_V
`define SKY130_FD_SC_MS__DLYMETAL6S4S_FUNCTIONAL_V
/**
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__dlymetal6s4s (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYMETAL6S4S_FUNCTIONAL_V |
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 15:19:47 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ led_controller_design_processing_system7_0_0_stub.v
// Design : led_controller_design_processing_system7_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2017.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(TTC0_WAVE0_OUT, TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID,
M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n,
DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN,
DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output FCLK_CLK0;
output FCLK_RESET0_N;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A211O_BLACKBOX_V
`define SKY130_FD_SC_MS__A211O_BLACKBOX_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a211o (
X ,
A1,
A2,
B1,
C1
);
output X ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A211O_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__XOR2_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__XOR2_BEHAVIORAL_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__xor2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire xor0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, B, A );
buf buf0 (X , xor0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__XOR2_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFXBP_1_V
`define SKY130_FD_SC_HD__SDFXBP_1_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog wrapper for sdfxbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__sdfxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__sdfxbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__sdfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__sdfxbp_1 (
Q ,
Q_N,
CLK,
D ,
SCD,
SCE
);
output Q ;
output Q_N;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__sdfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFXBP_1_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
module axi_hdmi_tx (
// hdmi interface
hdmi_clk,
hdmi_out_clk,
// 16-bit interface
hdmi_16_hsync,
hdmi_16_vsync,
hdmi_16_data_e,
hdmi_16_data,
hdmi_16_es_data,
// 24-bit interface
hdmi_24_hsync,
hdmi_24_vsync,
hdmi_24_data_e,
hdmi_24_data,
// 36-bit interface
hdmi_36_hsync,
hdmi_36_vsync,
hdmi_36_data_e,
hdmi_36_data,
// vdma interface
m_axis_mm2s_clk,
m_axis_mm2s_fsync,
m_axis_mm2s_fsync_ret,
m_axis_mm2s_tvalid,
m_axis_mm2s_tdata,
m_axis_mm2s_tkeep,
m_axis_mm2s_tlast,
m_axis_mm2s_tready,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rdata,
s_axi_rresp,
s_axi_rready);
// parameters
parameter PCORE_ID = 0;
parameter PCORE_Cr_Cb_N = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_EMBEDDED_SYNC = 0;
parameter C_S_AXI_MIN_SIZE = 32'hffff;
parameter C_BASEADDR = 32'hffffffff;
parameter C_HIGHADDR = 32'h00000000;
// hdmi interface
input hdmi_clk;
output hdmi_out_clk;
// 16-bit interface
output hdmi_16_hsync;
output hdmi_16_vsync;
output hdmi_16_data_e;
output [15:0] hdmi_16_data;
output [15:0] hdmi_16_es_data;
// 24-bit interface
output hdmi_24_hsync;
output hdmi_24_vsync;
output hdmi_24_data_e;
output [23:0] hdmi_24_data;
// 36-bit interface
output hdmi_36_hsync;
output hdmi_36_vsync;
output hdmi_36_data_e;
output [35:0] hdmi_36_data;
// vdma interface
input m_axis_mm2s_clk;
output m_axis_mm2s_fsync;
input m_axis_mm2s_fsync_ret;
input m_axis_mm2s_tvalid;
input [63:0] m_axis_mm2s_tdata;
input [ 7:0] m_axis_mm2s_tkeep;
input m_axis_mm2s_tlast;
output m_axis_mm2s_tready;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [31:0] s_axi_rdata;
output [ 1:0] s_axi_rresp;
input s_axi_rready;
// reset and clocks
wire up_rstn;
wire up_clk;
wire hdmi_rst;
wire vdma_clk;
wire vdma_rst;
// internal signals
wire up_sel_s;
wire up_wr_s;
wire [13:0] up_addr_s;
wire [31:0] up_wdata_s;
wire [31:0] up_rdata_s;
wire up_ack_s;
wire hdmi_full_range_s;
wire hdmi_csc_bypass_s;
wire [ 1:0] hdmi_srcsel_s;
wire [23:0] hdmi_const_rgb_s;
wire [15:0] hdmi_hl_active_s;
wire [15:0] hdmi_hl_width_s;
wire [15:0] hdmi_hs_width_s;
wire [15:0] hdmi_he_max_s;
wire [15:0] hdmi_he_min_s;
wire [15:0] hdmi_vf_active_s;
wire [15:0] hdmi_vf_width_s;
wire [15:0] hdmi_vs_width_s;
wire [15:0] hdmi_ve_max_s;
wire [15:0] hdmi_ve_min_s;
wire hdmi_fs_toggle_s;
wire [ 8:0] hdmi_raddr_g_s;
wire hdmi_tpm_oos_s;
wire hdmi_status_s;
wire vdma_fs_s;
wire vdma_fs_ret_s;
wire vdma_valid_s;
wire [63:0] vdma_data_s;
wire vdma_ready_s;
wire vdma_wr_s;
wire [ 8:0] vdma_waddr_s;
wire [47:0] vdma_wdata_s;
wire vdma_fs_ret_toggle_s;
wire [ 8:0] vdma_fs_waddr_s;
// signal name changes
assign up_rstn = s_axi_aresetn;
assign up_clk = s_axi_aclk;
assign vdma_clk = m_axis_mm2s_clk;
assign vdma_valid_s = m_axis_mm2s_tvalid;
assign vdma_data_s = m_axis_mm2s_tdata;
assign vdma_fs_ret_s = m_axis_mm2s_fsync_ret;
assign m_axis_mm2s_fsync = vdma_fs_s;
assign m_axis_mm2s_tready = vdma_ready_s;
// axi interface
up_axi #(
.PCORE_BASEADDR (C_BASEADDR),
.PCORE_HIGHADDR (C_HIGHADDR))
i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_rdata_s),
.up_ack (up_ack_s));
// processor interface
up_hdmi_tx i_up (
.hdmi_clk (hdmi_clk),
.hdmi_rst (hdmi_rst),
.hdmi_full_range (hdmi_full_range_s),
.hdmi_csc_bypass (hdmi_csc_bypass_s),
.hdmi_srcsel (hdmi_srcsel_s),
.hdmi_const_rgb (hdmi_const_rgb_s),
.hdmi_hl_active (hdmi_hl_active_s),
.hdmi_hl_width (hdmi_hl_width_s),
.hdmi_hs_width (hdmi_hs_width_s),
.hdmi_he_max (hdmi_he_max_s),
.hdmi_he_min (hdmi_he_min_s),
.hdmi_vf_active (hdmi_vf_active_s),
.hdmi_vf_width (hdmi_vf_width_s),
.hdmi_vs_width (hdmi_vs_width_s),
.hdmi_ve_max (hdmi_ve_max_s),
.hdmi_ve_min (hdmi_ve_min_s),
.hdmi_status (hdmi_status_s),
.hdmi_tpm_oos (hdmi_tpm_oos_s),
.hdmi_clk_ratio (32'd1),
.vdma_clk (vdma_clk),
.vdma_rst (vdma_rst),
.vdma_ovf (vdma_ovf_s),
.vdma_unf (vdma_unf_s),
.vdma_tpm_oos (vdma_tpm_oos_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_rdata_s),
.up_ack (up_ack_s));
// vdma interface
axi_hdmi_tx_vdma i_vdma (
.hdmi_fs_toggle (hdmi_fs_toggle_s),
.hdmi_raddr_g (hdmi_raddr_g_s),
.vdma_clk (vdma_clk),
.vdma_rst (vdma_rst),
.vdma_fs (vdma_fs_s),
.vdma_fs_ret (vdma_fs_ret_s),
.vdma_valid (vdma_valid_s),
.vdma_data (vdma_data_s),
.vdma_ready (vdma_ready_s),
.vdma_wr (vdma_wr_s),
.vdma_waddr (vdma_waddr_s),
.vdma_wdata (vdma_wdata_s),
.vdma_fs_ret_toggle (vdma_fs_ret_toggle_s),
.vdma_fs_waddr (vdma_fs_waddr_s),
.vdma_tpm_oos (vdma_tpm_oos_s),
.vdma_ovf (vdma_ovf_s),
.vdma_unf (vdma_unf_s));
// hdmi interface
axi_hdmi_tx_core #(
.Cr_Cb_N(PCORE_Cr_Cb_N),
.EMBEDDED_SYNC(PCORE_EMBEDDED_SYNC))
i_tx_core (
.hdmi_clk (hdmi_clk),
.hdmi_rst (hdmi_rst),
.hdmi_16_hsync (hdmi_16_hsync),
.hdmi_16_vsync (hdmi_16_vsync),
.hdmi_16_data_e (hdmi_16_data_e),
.hdmi_16_data (hdmi_16_data),
.hdmi_16_es_data (hdmi_16_es_data),
.hdmi_24_hsync (hdmi_24_hsync),
.hdmi_24_vsync (hdmi_24_vsync),
.hdmi_24_data_e (hdmi_24_data_e),
.hdmi_24_data (hdmi_24_data),
.hdmi_36_hsync (hdmi_36_hsync),
.hdmi_36_vsync (hdmi_36_vsync),
.hdmi_36_data_e (hdmi_36_data_e),
.hdmi_36_data (hdmi_36_data),
.hdmi_fs_toggle (hdmi_fs_toggle_s),
.hdmi_raddr_g (hdmi_raddr_g_s),
.hdmi_tpm_oos (hdmi_tpm_oos_s),
.hdmi_status (hdmi_status_s),
.vdma_clk (vdma_clk),
.vdma_wr (vdma_wr_s),
.vdma_waddr (vdma_waddr_s),
.vdma_wdata (vdma_wdata_s),
.vdma_fs_ret_toggle (vdma_fs_ret_toggle_s),
.vdma_fs_waddr (vdma_fs_waddr_s),
.hdmi_full_range (hdmi_full_range_s),
.hdmi_csc_bypass (hdmi_csc_bypass_s),
.hdmi_srcsel (hdmi_srcsel_s),
.hdmi_const_rgb (hdmi_const_rgb_s),
.hdmi_hl_active (hdmi_hl_active_s),
.hdmi_hl_width (hdmi_hl_width_s),
.hdmi_hs_width (hdmi_hs_width_s),
.hdmi_he_max (hdmi_he_max_s),
.hdmi_he_min (hdmi_he_min_s),
.hdmi_vf_active (hdmi_vf_active_s),
.hdmi_vf_width (hdmi_vf_width_s),
.hdmi_vs_width (hdmi_vs_width_s),
.hdmi_ve_max (hdmi_ve_max_s),
.hdmi_ve_min (hdmi_ve_min_s));
// hdmi output clock
ODDR #(.INIT(1'b0)) i_clk_oddr (
.R (1'b0),
.S (1'b0),
.CE (1'b1),
.D1 (1'b1),
.D2 (1'b0),
.C (hdmi_clk),
.Q (hdmi_out_clk));
endmodule
// ***************************************************************************
// ***************************************************************************
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PIO_RX_ENGINE.v
// Version : 1.3
//--
//-- Description: Local-Link Receive Unit.
//--
//--------------------------------------------------------------------------------
`timescale 1ps/1ps
module PIO_RX_ENGINE #(
parameter TCQ = 1,
parameter C_DATA_WIDTH = 64, // RX/TX interface data width
// Do not override parameters below this line
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // TSTRB width
) (
input clk,
input rst_n,
// AXI-S
input [C_DATA_WIDTH-1:0] m_axis_rx_tdata,
input [KEEP_WIDTH-1:0] m_axis_rx_tkeep,
input m_axis_rx_tlast,
input m_axis_rx_tvalid,
output reg m_axis_rx_tready,
input [21:0] m_axis_rx_tuser,
// Memory Read data handshake with Completion
// transmit unit. Transmit unit reponds to
// req_compl assertion and responds with compl_done
// assertion when a Completion w/ data is transmitted.
output reg req_compl,
output reg req_compl_wd,
input compl_done,
output reg [2:0] req_tc, // Memory Read TC
output reg req_td, // Memory Read TD
output reg req_ep, // Memory Read EP
output reg [1:0] req_attr, // Memory Read Attribute
output reg [9:0] req_len, // Memory Read Length (1DW)
output reg [15:0] req_rid, // Memory Read Requestor ID
output reg [7:0] req_tag, // Memory Read Tag
output reg [7:0] req_be, // Memory Read Byte Enables
output reg [12:0] req_addr, // Memory Read Address
// Memory interface used to save 1 DW data received
// on Memory Write 32 TLP. Data extracted from
// inbound TLP is presented to the Endpoint memory
// unit. Endpoint memory unit reacts to wr_en
// assertion and asserts wr_busy when it is
// processing written information.
output reg [10:0] wr_addr, // Memory Write Address
output reg [7:0] wr_be, // Memory Write Byte Enable
output reg [31:0] wr_data, // Memory Write Data
output reg wr_en, // Memory Write Enable
input wr_busy // Memory Write Busy
);
localparam PIO_RX_MEM_RD32_FMT_TYPE = 7'b00_00000;
localparam PIO_RX_MEM_WR32_FMT_TYPE = 7'b10_00000;
localparam PIO_RX_MEM_RD64_FMT_TYPE = 7'b01_00000;
localparam PIO_RX_MEM_WR64_FMT_TYPE = 7'b11_00000;
localparam PIO_RX_IO_RD32_FMT_TYPE = 7'b00_00010;
localparam PIO_RX_IO_WR32_FMT_TYPE = 7'b10_00010;
localparam PIO_RX_RST_STATE = 8'b00000000;
localparam PIO_RX_MEM_RD32_DW1DW2 = 8'b00000001;
localparam PIO_RX_MEM_WR32_DW1DW2 = 8'b00000010;
localparam PIO_RX_MEM_RD64_DW1DW2 = 8'b00000100;
localparam PIO_RX_MEM_WR64_DW1DW2 = 8'b00001000;
localparam PIO_RX_MEM_WR64_DW3 = 8'b00010000;
localparam PIO_RX_WAIT_STATE = 8'b00100000;
localparam PIO_RX_IO_WR_DW1DW2 = 8'b01000000;
localparam PIO_RX_IO_MEM_WR_WAIT_STATE = 8'b10000000;
// Local Registers
reg [7:0] state;
reg [7:0] tlp_type;
wire io_bar_hit_n;
wire mem32_bar_hit_n;
wire mem64_bar_hit_n;
wire erom_bar_hit_n;
reg [1:0] region_select;
generate
if (C_DATA_WIDTH == 64) begin : pio_rx_sm_64
wire sop; // Start of packet
reg in_packet_q;
// Generate a signal that indicates if we are currently receiving a packet.
// This value is one clock cycle delayed from what is actually on the AXIS
// data bus.
always@(posedge clk)
begin
if(!rst_n)
in_packet_q <= # TCQ 1'b0;
else if (m_axis_rx_tvalid && m_axis_rx_tready && m_axis_rx_tlast)
in_packet_q <= # TCQ 1'b0;
else if (sop && m_axis_rx_tready)
in_packet_q <= # TCQ 1'b1;
end
assign sop = !in_packet_q && m_axis_rx_tvalid;
always @ ( posedge clk ) begin
if (!rst_n )
begin
m_axis_rx_tready <= #TCQ 1'b0;
req_compl <= #TCQ 1'b0;
req_compl_wd <= #TCQ 1'b1;
req_tc <= #TCQ 3'b0;
req_td <= #TCQ 1'b0;
req_ep <= #TCQ 1'b0;
req_attr <= #TCQ 2'b0;
req_len <= #TCQ 10'b0;
req_rid <= #TCQ 16'b0;
req_tag <= #TCQ 8'b0;
req_be <= #TCQ 8'b0;
req_addr <= #TCQ 13'b0;
wr_be <= #TCQ 8'b0;
wr_addr <= #TCQ 11'b0;
wr_data <= #TCQ 32'b0;
wr_en <= #TCQ 1'b0;
state <= #TCQ PIO_RX_RST_STATE;
tlp_type <= #TCQ 8'b0;
end
else
begin
wr_en <= #TCQ 1'b0;
req_compl <= #TCQ 1'b0;
case (state)
PIO_RX_RST_STATE : begin
m_axis_rx_tready <= #TCQ 1'b1;
req_compl_wd <= #TCQ 1'b1;
if (sop)
begin
case (m_axis_rx_tdata[30:24])
PIO_RX_MEM_RD32_FMT_TYPE : begin
tlp_type <= #TCQ m_axis_rx_tdata[31:24];
req_len <= #TCQ m_axis_rx_tdata[9:0];
m_axis_rx_tready <= #TCQ 1'b0;
if (m_axis_rx_tdata[9:0] == 10'b1)
begin
req_tc <= #TCQ m_axis_rx_tdata[22:20];
req_td <= #TCQ m_axis_rx_tdata[15];
req_ep <= #TCQ m_axis_rx_tdata[14];
req_attr <= #TCQ m_axis_rx_tdata[13:12];
req_len <= #TCQ m_axis_rx_tdata[9:0];
req_rid <= #TCQ m_axis_rx_tdata[63:48];
req_tag <= #TCQ m_axis_rx_tdata[47:40];
req_be <= #TCQ m_axis_rx_tdata[39:32];
state <= #TCQ PIO_RX_MEM_RD32_DW1DW2;
end // if (m_axis_rx_tdata[9:0] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[9:0] == 10'b1)
end // PIO_RX_MEM_RD32_FMT_TYPE
PIO_RX_MEM_WR32_FMT_TYPE : begin
tlp_type <= #TCQ m_axis_rx_tdata[31:24];
req_len <= #TCQ m_axis_rx_tdata[9:0];
m_axis_rx_tready <= #TCQ 1'b0;
if (m_axis_rx_tdata[9:0] == 10'b1)
begin
wr_be <= #TCQ m_axis_rx_tdata[39:32];
state <= #TCQ PIO_RX_MEM_WR32_DW1DW2;
end // if (m_axis_rx_tdata[9:0] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[9:0] == 10'b1)
end // PIO_RX_MEM_WR32_FMT_TYPE
PIO_RX_MEM_RD64_FMT_TYPE : begin
tlp_type <= #TCQ m_axis_rx_tdata[31:24];
req_len <= #TCQ m_axis_rx_tdata[9:0];
m_axis_rx_tready <= #TCQ 1'b0;
if (m_axis_rx_tdata[9:0] == 10'b1)
begin
req_tc <= #TCQ m_axis_rx_tdata[22:20];
req_td <= #TCQ m_axis_rx_tdata[15];
req_ep <= #TCQ m_axis_rx_tdata[14];
req_attr <= #TCQ m_axis_rx_tdata[13:12];
req_len <= #TCQ m_axis_rx_tdata[9:0];
req_rid <= #TCQ m_axis_rx_tdata[63:48];
req_tag <= #TCQ m_axis_rx_tdata[47:40];
req_be <= #TCQ m_axis_rx_tdata[39:32];
state <= #TCQ PIO_RX_MEM_RD64_DW1DW2;
end // if (m_axis_rx_tdata[9:0] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[9:0] == 10'b1)
end // PIO_RX_MEM_RD64_FMT_TYPE
PIO_RX_MEM_WR64_FMT_TYPE : begin
tlp_type <= #TCQ m_axis_rx_tdata[31:24];
req_len <= #TCQ m_axis_rx_tdata[9:0];
if (m_axis_rx_tdata[9:0] == 10'b1) begin
wr_be <= #TCQ m_axis_rx_tdata[39:32];
state <= #TCQ PIO_RX_MEM_WR64_DW1DW2;
end // if (m_axis_rx_tdata[9:0] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[9:0] == 10'b1)
end // PIO_RX_MEM_WR64_FMT_TYPE
PIO_RX_IO_RD32_FMT_TYPE : begin
tlp_type <= #TCQ m_axis_rx_tdata[31:24];
req_len <= #TCQ m_axis_rx_tdata[9:0];
m_axis_rx_tready <= #TCQ 1'b0;
if (m_axis_rx_tdata[9:0] == 10'b1)
begin
req_tc <= #TCQ m_axis_rx_tdata[22:20];
req_td <= #TCQ m_axis_rx_tdata[15];
req_ep <= #TCQ m_axis_rx_tdata[14];
req_attr <= #TCQ m_axis_rx_tdata[13:12];
req_len <= #TCQ m_axis_rx_tdata[9:0];
req_rid <= #TCQ m_axis_rx_tdata[63:48];
req_tag <= #TCQ m_axis_rx_tdata[47:40];
req_be <= #TCQ m_axis_rx_tdata[39:32];
state <= #TCQ PIO_RX_MEM_RD32_DW1DW2;
end // if (m_axis_rx_tdata[9:0] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[9:0] == 10'b1)
end // PIO_RX_IO_RD32_FMT_TYPE
PIO_RX_IO_WR32_FMT_TYPE : begin
tlp_type <= #TCQ m_axis_rx_tdata[31:24];
req_len <= #TCQ m_axis_rx_tdata[9:0];
m_axis_rx_tready <= #TCQ 1'b0;
if (m_axis_rx_tdata[9:0] == 10'b1)
begin
req_tc <= #TCQ m_axis_rx_tdata[22:20];
req_td <= #TCQ m_axis_rx_tdata[15];
req_ep <= #TCQ m_axis_rx_tdata[14];
req_attr <= #TCQ m_axis_rx_tdata[13:12];
req_len <= #TCQ m_axis_rx_tdata[9:0];
req_rid <= #TCQ m_axis_rx_tdata[63:48];
req_tag <= #TCQ m_axis_rx_tdata[47:40];
req_be <= #TCQ m_axis_rx_tdata[39:32];
wr_be <= #TCQ m_axis_rx_tdata[39:32];
state <= #TCQ PIO_RX_IO_WR_DW1DW2;
end //if (m_axis_rx_tdata[9:0] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end //if !(m_axis_rx_tdata[9:0] == 10'b1)
end // PIO_RX_IO_WR32_FMT_TYPE
default : begin // other TLPs
state <= #TCQ PIO_RX_RST_STATE;
end // default
endcase
end // if (sop)
else
state <= #TCQ PIO_RX_RST_STATE;
end // PIO_RX_RST_STATE
PIO_RX_MEM_RD32_DW1DW2 : begin
if (m_axis_rx_tvalid)
begin
m_axis_rx_tready <= #TCQ 1'b0;
req_addr <= #TCQ {region_select[1:0],m_axis_rx_tdata[10:2], 2'b00};
req_compl <= #TCQ 1'b1;
req_compl_wd <= #TCQ 1'b1;
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tvalid)
else
state <= #TCQ PIO_RX_MEM_RD32_DW1DW2;
end // PIO_RX_MEM_RD32_DW1DW2
PIO_RX_MEM_WR32_DW1DW2 : begin
if (m_axis_rx_tvalid)
begin
wr_data <= #TCQ m_axis_rx_tdata[63:32];
wr_en <= #TCQ 1'b1;
m_axis_rx_tready <= #TCQ 1'b0;
wr_addr <= #TCQ {region_select[1:0],m_axis_rx_tdata[10:2]};
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tvalid)
else
state <= #TCQ PIO_RX_MEM_WR32_DW1DW2;
end // PIO_RX_MEM_WR32_DW1DW2
PIO_RX_MEM_RD64_DW1DW2 : begin
if (m_axis_rx_tvalid)
begin
req_addr <= #TCQ {region_select[1:0],m_axis_rx_tdata[42:34], 2'b00};
req_compl <= #TCQ 1'b1;
req_compl_wd <= #TCQ 1'b1;
m_axis_rx_tready <= #TCQ 1'b0;
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tvalid)
else
state <= #TCQ PIO_RX_MEM_RD64_DW1DW2;
end // PIO_RX_MEM_RD64_DW1DW2
PIO_RX_MEM_WR64_DW1DW2 : begin
if (m_axis_rx_tvalid)
begin
m_axis_rx_tready <= #TCQ 1'b0;
wr_addr <= #TCQ {region_select[1:0],m_axis_rx_tdata[42:34]};
state <= #TCQ PIO_RX_MEM_WR64_DW3;
end // if (m_axis_rx_tvalid)
else
state <= #TCQ PIO_RX_MEM_WR64_DW1DW2;
end // PIO_RX_MEM_WR64_DW1DW2
PIO_RX_MEM_WR64_DW3 : begin
if (m_axis_rx_tvalid)
begin
wr_data <= #TCQ m_axis_rx_tdata[31:0];
wr_en <= #TCQ 1'b1;
m_axis_rx_tready <= #TCQ 1'b0;
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tvalid)
else
state <= #TCQ PIO_RX_MEM_WR64_DW3;
end // PIO_RX_MEM_WR64_DW3
PIO_RX_IO_WR_DW1DW2 : begin
if (m_axis_rx_tvalid)
begin
wr_data <= #TCQ m_axis_rx_tdata[63:32];
wr_en <= #TCQ 1'b1;
m_axis_rx_tready <= #TCQ 1'b0;
wr_addr <= #TCQ {region_select[1:0],m_axis_rx_tdata[10:2]};
req_compl <= #TCQ 1'b1;
req_compl_wd <= #TCQ 1'b0;
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tvalid)
else
state <= #TCQ PIO_RX_IO_WR_DW1DW2;
end // PIO_RX_IO_WR_DW1DW2
PIO_RX_WAIT_STATE : begin
wr_en <= #TCQ 1'b0;
req_compl <= #TCQ 1'b0;
if ((tlp_type == PIO_RX_MEM_WR32_FMT_TYPE) && (!wr_busy))
begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_RX_RST_STATE;
end // if ((tlp_type == PIO_RX_MEM_WR32_FMT_TYPE) && (!wr_busy))
else if ((tlp_type == PIO_RX_IO_WR32_FMT_TYPE) && (!wr_busy))
begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_RX_RST_STATE;
end // if ((tlp_type == PIO_RX_IO_WR32_FMT_TYPE) && (!wr_busy))
else if ((tlp_type == PIO_RX_MEM_WR64_FMT_TYPE) && (!wr_busy))
begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_RX_RST_STATE;
end // if ((tlp_type == PIO_RX_MEM_WR64_FMT_TYPE) && (!wr_busy))
else if ((tlp_type == PIO_RX_MEM_RD32_FMT_TYPE) && (compl_done))
begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_RX_RST_STATE;
end // if ((tlp_type == PIO_RX_MEM_RD32_FMT_TYPE) && (compl_done))
else if ((tlp_type == PIO_RX_IO_RD32_FMT_TYPE) && (compl_done))
begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_RX_RST_STATE;
end // if ((tlp_type == PIO_RX_IO_RD32_FMT_TYPE) && (compl_done))
else if ((tlp_type == PIO_RX_MEM_RD64_FMT_TYPE) && (compl_done))
begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_RX_RST_STATE;
end // if ((tlp_type == PIO_RX_MEM_RD64_FMT_TYPE) && (compl_done))
else
state <= #TCQ PIO_RX_WAIT_STATE;
end // PIO_RX_WAIT_STATE
default : begin
// default case stmt
state <= #TCQ PIO_RX_RST_STATE;
end // default
endcase
end
end
end
else if (C_DATA_WIDTH == 128) begin : pio_rx_sm_128
// Define where the start of packet happens. Remember that PCIe dwords
// start on the right and get filled in to the left of the 128-bit data
// bus.
// Start of packet can only happen on byte 0 (right most byte) or on
// byte 8 (middle byte).
wire sof_present = m_axis_rx_tuser[14];
wire sof_right = !m_axis_rx_tuser[13] && sof_present;
wire sof_mid = m_axis_rx_tuser[13] && sof_present;
always @ ( posedge clk ) begin
if (!rst_n )
begin
m_axis_rx_tready <= #TCQ 1'b0;
req_compl <= #TCQ 1'b0;
req_compl_wd <= #TCQ 1'b1;
req_tc <= #TCQ 3'b0;
req_td <= #TCQ 1'b0;
req_ep <= #TCQ 1'b0;
req_attr <= #TCQ 2'b0;
req_len <= #TCQ 10'b0;
req_rid <= #TCQ 16'b0;
req_tag <= #TCQ 8'b0;
req_be <= #TCQ 8'b0;
req_addr <= #TCQ 13'b0;
wr_be <= #TCQ 8'b0;
wr_addr <= #TCQ 11'b0;
wr_data <= #TCQ 32'b0;
wr_en <= #TCQ 1'b0;
state <= #TCQ PIO_RX_RST_STATE;
tlp_type <= #TCQ 8'b0;
end // if (!rst_n )
else
begin
wr_en <= #TCQ 1'b0;
req_compl <= #TCQ 1'b0;
case (state)
PIO_RX_RST_STATE : begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_RX_RST_STATE;
req_compl_wd <= #TCQ 1'b1;
// Packet starts in the middle of the 128-bit bus.
if ((m_axis_rx_tvalid) && (m_axis_rx_tready))
begin
if (sof_mid)
begin
tlp_type <= #TCQ m_axis_rx_tdata[95:88];
req_len <= #TCQ m_axis_rx_tdata[73:64];
m_axis_rx_tready <= #TCQ 1'b0;
// Evaluate packet type
case (m_axis_rx_tdata[94:88])
PIO_RX_MEM_RD32_FMT_TYPE : begin
if (m_axis_rx_tdata[73:64] == 10'b1)
begin
req_tc <= #TCQ m_axis_rx_tdata[86:84];
req_td <= #TCQ m_axis_rx_tdata[79];
req_ep <= #TCQ m_axis_rx_tdata[78];
req_attr <= #TCQ m_axis_rx_tdata[77:76];
req_len <= #TCQ m_axis_rx_tdata[73:64];
req_rid <= #TCQ m_axis_rx_tdata[127:112];
req_tag <= #TCQ m_axis_rx_tdata[111:104];
req_be <= #TCQ m_axis_rx_tdata[103:96];
state <= #TCQ PIO_RX_MEM_RD32_DW1DW2;
end // if (m_axis_rx_tdata[73:64] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[73:64] == 10'b1)
end // PIO_RX_MEM_RD32_FMT_TYPE
PIO_RX_MEM_WR32_FMT_TYPE : begin
if (m_axis_rx_tdata[73:64] == 10'b1)
begin
wr_be <= #TCQ m_axis_rx_tdata[103:96];
state <= #TCQ PIO_RX_MEM_WR32_DW1DW2;
end // if (m_axis_rx_tdata[73:64] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[73:64] == 10'b1)
end // PIO_RX_MEM_WR32_FMT_TYPE
PIO_RX_MEM_RD64_FMT_TYPE : begin
if (m_axis_rx_tdata[73:64] == 10'b1)
begin
req_tc <= #TCQ m_axis_rx_tdata[86:84];
req_td <= #TCQ m_axis_rx_tdata[79];
req_ep <= #TCQ m_axis_rx_tdata[78];
req_attr <= #TCQ m_axis_rx_tdata[77:76];
req_len <= #TCQ m_axis_rx_tdata[73:64];
req_rid <= #TCQ m_axis_rx_tdata[127:112];
req_tag <= #TCQ m_axis_rx_tdata[111:104];
req_be <= #TCQ m_axis_rx_tdata[103:96];
state <= #TCQ PIO_RX_MEM_RD64_DW1DW2;
end // if !(m_axis_rx_tdata[73:64] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[73:64] == 10'b1)
end // PIO_RX_MEM_RD64_FMT_TYPE
PIO_RX_MEM_WR64_FMT_TYPE : begin
if (m_axis_rx_tdata[73:64] == 10'b1)
begin
wr_be <= #TCQ m_axis_rx_tdata[103:96];
state <= #TCQ PIO_RX_MEM_WR64_DW1DW2;
end // if (m_axis_rx_tdata[73:64] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[73:64] == 10'b1)
end // PIO_RX_MEM_WR64_FMT_TYPE
PIO_RX_IO_RD32_FMT_TYPE : begin
if (m_axis_rx_tdata[73:64] == 10'b1)
begin
req_tc <= #TCQ m_axis_rx_tdata[86:84];
req_td <= #TCQ m_axis_rx_tdata[79];
req_ep <= #TCQ m_axis_rx_tdata[78];
req_attr <= #TCQ m_axis_rx_tdata[77:76];
req_len <= #TCQ m_axis_rx_tdata[73:64];
req_rid <= #TCQ m_axis_rx_tdata[127:112];
req_tag <= #TCQ m_axis_rx_tdata[111:104];
req_be <= #TCQ m_axis_rx_tdata[103:96];
state <= #TCQ PIO_RX_MEM_RD32_DW1DW2;
end // if (m_axis_rx_tdata[73:64] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[73:64] == 10'b1)
end // PIO_RX_IO_RD32_FMT_TYPE
PIO_RX_IO_WR32_FMT_TYPE : begin
if (m_axis_rx_tdata[73:64] == 10'b1)
begin
req_tc <= #TCQ m_axis_rx_tdata[86:84];
req_td <= #TCQ m_axis_rx_tdata[79];
req_ep <= #TCQ m_axis_rx_tdata[78];
req_attr <= #TCQ m_axis_rx_tdata[77:76];
req_len <= #TCQ m_axis_rx_tdata[73:64];
req_rid <= #TCQ m_axis_rx_tdata[127:112];
req_tag <= #TCQ m_axis_rx_tdata[111:104];
wr_be <= #TCQ m_axis_rx_tdata[103:96];
state <= #TCQ PIO_RX_MEM_WR32_DW1DW2;
end // if (m_axis_rx_tdata[73:64] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[73:64] == 10'b1)
end // PIO_RX_IO_WR32_FMT_TYPE
default : begin // other TLPs
state <= #TCQ PIO_RX_RST_STATE;
end // default
endcase // case (m_axis_rx_tdata[94:88])
// Packet starts on the right of the data bus. Remember, packets start
// on the right and are filled to the left. The data-bus is filled 32-bits
// (one Dword) at time.
end
else if (sof_right)
begin
tlp_type <= #TCQ m_axis_rx_tdata[31:24];
req_len <= #TCQ m_axis_rx_tdata[9:0];
m_axis_rx_tready <= #TCQ 1'b0;
case (m_axis_rx_tdata[30:24])
PIO_RX_MEM_RD32_FMT_TYPE : begin
if (m_axis_rx_tdata[9:0] == 10'b1)
begin
req_tc <= #TCQ m_axis_rx_tdata[22:20];
req_td <= #TCQ m_axis_rx_tdata[15];
req_ep <= #TCQ m_axis_rx_tdata[14];
req_attr <= #TCQ m_axis_rx_tdata[13:12];
req_len <= #TCQ m_axis_rx_tdata[9:0];
req_rid <= #TCQ m_axis_rx_tdata[63:48];
req_tag <= #TCQ m_axis_rx_tdata[47:40];
req_be <= #TCQ m_axis_rx_tdata[39:32];
//lower qw
req_addr <= #TCQ {region_select[1:0],
m_axis_rx_tdata[74:66],2'b00};
req_compl <= #TCQ 1'b1;
req_compl_wd <= #TCQ 1'b1;
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tdata[9:0] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if (m_axis_rx_tdata[9:0] == 10'b1)
end // PIO_RX_MEM_RD32_FMT_TYPE
PIO_RX_MEM_WR32_FMT_TYPE : begin
if (m_axis_rx_tdata[9:0] == 10'b1)
begin
wr_be <= #TCQ m_axis_rx_tdata[39:32];
//lower qw
wr_data <= #TCQ m_axis_rx_tdata[127:96];
wr_en <= #TCQ 1'b1;
wr_addr <= #TCQ {region_select[1:0], m_axis_rx_tdata[74:66]};
wr_en <= #TCQ 1'b1;
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tdata[9:0] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[9:0] == 10'b1)
end // PIO_RX_MEM_WR32_FMT_TYPE
PIO_RX_MEM_RD64_FMT_TYPE : begin
if (m_axis_rx_tdata[9:0] == 10'b1)
begin
req_tc <= #TCQ m_axis_rx_tdata[22:20];
req_td <= #TCQ m_axis_rx_tdata[15];
req_ep <= #TCQ m_axis_rx_tdata[14];
req_attr <= #TCQ m_axis_rx_tdata[13:12];
req_len <= #TCQ m_axis_rx_tdata[9:0];
req_rid <= #TCQ m_axis_rx_tdata[63:48];
req_tag <= #TCQ m_axis_rx_tdata[47:40];
req_be <= #TCQ m_axis_rx_tdata[39:32];
//lower qw
// Upper 32-bits of 64-bit address not used, but would be captured
// in this state if used. Upper 32 address bits are on
//m_axis_rx_tdata[127:96]
req_addr <= #TCQ {region_select[1:0], m_axis_rx_tdata[74:66],2'b00};
req_compl <= #TCQ 1'b1;
req_compl_wd <= #TCQ 1'b1;
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tdata[9:0] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[9:0] == 10'b1)
end // PIO_RX_MEM_RD64_FMT_TYPE
PIO_RX_MEM_WR64_FMT_TYPE : begin
if (m_axis_rx_tdata[9:0] == 10'b1)
begin
wr_be <= #TCQ m_axis_rx_tdata[39:32];
// lower qw
wr_addr <= #TCQ {region_select[1:0], m_axis_rx_tdata[74:66]};
state <= #TCQ PIO_RX_MEM_WR64_DW3;
end // if (m_axis_rx_tdata[9:0] == 10'b1)
else
begin
state <= #TCQ PIO_RX_WAIT_STATE;
end // if !(m_axis_rx_tdata[9:0] == 10'b1)
end // PIO_RX_MEM_WR64_FMT_TYPE
PIO_RX_IO_RD32_FMT_TYPE : begin
if (m_axis_rx_tdata[9:0] == 10'b1)
begin
req_tc <= #TCQ m_axis_rx_tdata[22:20];
req_td <= #TCQ m_axis_rx_tdata[15];
req_ep <= #TCQ m_axis_rx_tdata[14];
req_attr <= #TCQ m_axis_rx_tdata[13:12];
req_len <= #TCQ m_axis_rx_tdata[9:0];
req_rid <= #TCQ m_axis_rx_tdata[63:48];
req_tag <= #TCQ m_axis_rx_tdata[47:40];
req_be <= #TCQ m_axis_rx_tdata[39:32];
//lower qw
req_addr <= #TCQ {region_select[1:0], m_axis_rx_tdata[74:66],2'b00};
req_compl <= #TCQ 1'b1;
req_compl_wd <= #TCQ 1'b1;
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tdata[9:0] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[9:0] == 10'b1)
end // PIO_RX_IO_RD32_FMT_TYPE
PIO_RX_IO_WR32_FMT_TYPE : begin
if (m_axis_rx_tdata[9:0] == 10'b1)
begin
wr_be <= #TCQ m_axis_rx_tdata[39:32];
//lower qw
req_tc <= #TCQ m_axis_rx_tdata[22:20];
req_td <= #TCQ m_axis_rx_tdata[15];
req_ep <= #TCQ m_axis_rx_tdata[14];
req_attr <= #TCQ m_axis_rx_tdata[13:12];
req_len <= #TCQ m_axis_rx_tdata[9:0];
req_rid <= #TCQ m_axis_rx_tdata[63:48];
req_tag <= #TCQ m_axis_rx_tdata[47:40];
wr_data <= #TCQ m_axis_rx_tdata[127:96];
wr_en <= #TCQ 1'b1;
wr_addr <= #TCQ {region_select[1:0], m_axis_rx_tdata[74:66]};
wr_en <= #TCQ 1'b1;
req_compl <= #TCQ 1'b1;
req_compl_wd <= #TCQ 1'b0;
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tdata[9:0] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[9:0] == 10'b1)
end // PIO_RX_IO_WR32_FMT_TYPE
endcase // case (m_axis_rx_tdata[30:24])
end // if (sof_right)
end
else // not a start of packet
state <= #TCQ PIO_RX_RST_STATE;
end //PIO_RX_RST_STATE
PIO_RX_MEM_WR64_DW3 : begin
if (m_axis_rx_tvalid)
begin
wr_data <= #TCQ m_axis_rx_tdata[31:0];
wr_en <= #TCQ 1'b1;
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tvalid)
else
begin
state <= #TCQ PIO_RX_MEM_WR64_DW3;
end // if !(m_axis_rx_tvalid)
end // PIO_RX_MEM_WR64_DW3
PIO_RX_MEM_RD32_DW1DW2 : begin
if (m_axis_rx_tvalid)
begin
m_axis_rx_tready <= #TCQ 1'b0;
req_addr <= #TCQ {region_select[1:0], m_axis_rx_tdata[10:2], 2'b00};
req_compl <= #TCQ 1'b1;
req_compl_wd <= #TCQ 1'b1;
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tvalid)
else
begin
state <= #TCQ PIO_RX_MEM_RD32_DW1DW2;
end // if !(m_axis_rx_tvalid)
end // PIO_RX_MEM_RD32_DW1DW2
PIO_RX_MEM_WR32_DW1DW2 : begin
if (m_axis_rx_tvalid)
begin
wr_data <= #TCQ m_axis_rx_tdata[63:32];
wr_en <= #TCQ 1'b1;
m_axis_rx_tready <= #TCQ 1'b0;
wr_addr <= #TCQ {region_select[1:0], m_axis_rx_tdata[10:2]};
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tvalid)
else
begin
state <= #TCQ PIO_RX_MEM_WR32_DW1DW2;
end // if !(m_axis_rx_tvalid)
end // PIO_RX_MEM_WR32_DW1DW2
PIO_RX_IO_WR_DW1DW2 : begin
if (m_axis_rx_tvalid)
begin
wr_data <= #TCQ m_axis_rx_tdata[63:32];
wr_en <= #TCQ 1'b1;
m_axis_rx_tready <= #TCQ 1'b0;
wr_addr <= #TCQ {region_select[1:0], m_axis_rx_tdata[10:2]};
req_compl <= #TCQ 1'b1;
req_compl_wd <= #TCQ 1'b0;
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tvalid)
else
begin
state <= #TCQ PIO_RX_MEM_WR32_DW1DW2;
end // if !(m_axis_rx_tvalid)
end // PIO_RX_IO_WR_DW1DW2
PIO_RX_MEM_RD64_DW1DW2 : begin
if (m_axis_rx_tvalid)
begin
req_addr <= #TCQ {region_select[1:0], m_axis_rx_tdata[10:2], 2'b00};
req_compl <= #TCQ 1'b1;
req_compl_wd <= #TCQ 1'b1;
m_axis_rx_tready <= #TCQ 1'b0;
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tvalid)
else
begin
state <= #TCQ PIO_RX_MEM_RD64_DW1DW2;
end // if !(m_axis_rx_tvalid)
end // PIO_RX_MEM_RD64_DW1DW2
PIO_RX_MEM_WR64_DW1DW2 : begin
if (m_axis_rx_tvalid)
begin
m_axis_rx_tready <= #TCQ 1'b0;
wr_addr <= #TCQ {region_select[1:0], m_axis_rx_tdata[10:2]};
// lower QW
wr_data <= #TCQ m_axis_rx_tdata[95:64];
wr_en <= #TCQ 1'b1;
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tvalid)
else
begin
state <= #TCQ PIO_RX_MEM_WR64_DW1DW2;
end // if (m_axis_rx_tvalid)
end // PIO_RX_MEM_WR64_DW1DW2
PIO_RX_WAIT_STATE : begin
wr_en <= #TCQ 1'b0;
req_compl <= #TCQ 1'b0;
if ((tlp_type == PIO_RX_MEM_WR32_FMT_TYPE) &&(!wr_busy))
begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_RX_RST_STATE;
end // if ((tlp_type == PIO_RX_MEM_WR32_FMT_TYPE) &&(!wr_busy))
else if ((tlp_type == PIO_RX_IO_WR32_FMT_TYPE) && (!compl_done))
begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_RX_RST_STATE;
end // if ((tlp_type == PIO_RX_IO_WR32_FMT_TYPE) && (!compl_done))
else if ((tlp_type == PIO_RX_MEM_WR64_FMT_TYPE) && (!wr_busy))
begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_RX_RST_STATE;
end // if ((tlp_type == PIO_RX_MEM_WR64_FMT_TYPE) && (!wr_busy))
else if ((tlp_type == PIO_RX_MEM_RD32_FMT_TYPE) && (compl_done))
begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_RX_RST_STATE;
end // if ((tlp_type == PIO_RX_MEM_RD32_FMT_TYPE) && (compl_done))
else if ((tlp_type == PIO_RX_IO_RD32_FMT_TYPE) && (compl_done))
begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_RX_RST_STATE;
end // if ((tlp_type == PIO_RX_IO_RD32_FMT_TYPE) && (compl_done))
else if ((tlp_type == PIO_RX_MEM_RD64_FMT_TYPE) && (compl_done))
begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_RX_RST_STATE;
end // if ((tlp_type == PIO_RX_MEM_RD64_FMT_TYPE) && (compl_done))
else
begin
state <= #TCQ PIO_RX_WAIT_STATE;
end
end // PIO_RX_WAIT_STATE
default : begin
// default case stmt
state <= #TCQ PIO_RX_RST_STATE;
end // default
endcase
end // if rst_n
end // always
end // pio_rx_sm_128
endgenerate
assign mem64_bar_hit_n = ~m_axis_rx_tuser[2];
assign io_bar_hit_n = 1'b1;
assign mem32_bar_hit_n = ~m_axis_rx_tuser[4];
assign erom_bar_hit_n = ~m_axis_rx_tuser[8];
always @*
begin
case ({io_bar_hit_n, mem32_bar_hit_n, mem64_bar_hit_n, erom_bar_hit_n})
4'b0111 : begin
region_select <= #TCQ 2'b00; // Select IO region
end // 4'b0111
4'b1011 : begin
region_select <= #TCQ 2'b01; // Select Mem32 region
end // 4'b1011
4'b1101 : begin
region_select <= #TCQ 2'b10; // Select Mem64 region
end // 4'b1101
4'b1110 : begin
region_select <= #TCQ 2'b11; // Select EROM region
end // 4'b1110
default : begin
region_select <= #TCQ 2'b00; // Error selection will select IO region
end // default
endcase // case ({io_bar_hit_n, mem32_bar_hit_n, mem64_bar_hit_n, erom_bar_hit_n})
end
// synthesis translate_off
reg [8*20:1] state_ascii;
always @(state)
begin
case (state)
PIO_RX_RST_STATE : state_ascii <= #TCQ "RX_RST_STATE";
PIO_RX_MEM_RD32_DW1DW2 : state_ascii <= #TCQ "RX_MEM_RD32_DW1DW2";
PIO_RX_MEM_WR32_DW1DW2 : state_ascii <= #TCQ "RX_MEM_WR32_DW1DW2";
PIO_RX_MEM_RD64_DW1DW2 : state_ascii <= #TCQ "RX_MEM_RD64_DW1DW2";
PIO_RX_MEM_WR64_DW1DW2 : state_ascii <= #TCQ "RX_MEM_WR64_DW1DW2";
PIO_RX_MEM_WR64_DW3 : state_ascii <= #TCQ "RX_MEM_WR64_DW3";
PIO_RX_WAIT_STATE : state_ascii <= #TCQ "RX_WAIT_STATE";
PIO_RX_IO_WR_DW1DW2 : state_ascii <= #TCQ "RX_IO_WR_DW1DW2";
PIO_RX_IO_MEM_WR_WAIT_STATE : state_ascii <= #TCQ "RX_IO_MEM_WR_WAIT_STATE";
default : state_ascii <= #TCQ "PIO 128 STATE ERR";
endcase
end
// synthesis translate_on
endmodule // PIO_RX_ENGINE
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISO0P_BLACKBOX_V
`define SKY130_FD_SC_LP__ISO0P_BLACKBOX_V
/**
* iso0p: ????.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__iso0p (
X ,
A ,
SLEEP
);
output X ;
input A ;
input SLEEP;
// Voltage supply signals
supply1 KAPWR;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISO0P_BLACKBOX_V
|
(** * Basics: Functional Programming in Coq *)
(*
[Admitted] is Coq's "escape hatch" that says accept this definition
without proof. We use it to mark the 'holes' in the development
that should be completed as part of your homework exercises. In
practice, [Admitted] is useful when you're incrementally developing
large proofs. *)
Definition admit {T: Type} : T. Admitted.
(* ###################################################################### *)
(** * Introduction *)
(** The functional programming style brings programming closer to
simple, everyday mathematics: If a procedure or method has no side
effects, then pretty much all you need to understand about it is
how it maps inputs to outputs -- that is, you can think of it as
just a concrete method for computing a mathematical function.
This is one sense of the word "functional" in "functional
programming." The direct connection between programs and simple
mathematical objects supports both formal proofs of correctness
and sound informal reasoning about program behavior.
The other sense in which functional programming is "functional" is
that it emphasizes the use of functions (or methods) as
_first-class_ values -- i.e., values that can be passed as
arguments to other functions, returned as results, stored in data
structures, etc. The recognition that functions can be treated as
data in this way enables a host of useful and powerful idioms.
Other common features of functional languages include _algebraic
data types_ and _pattern matching_, which make it easy to construct
and manipulate rich data structures, and sophisticated
_polymorphic type systems_ that support abstraction and code
reuse. Coq shares all of these features.
The first half of this chapter introduces the most essential
elements of Coq's functional programming language. The second
half introduces some basic _tactics_ that can be used to prove
simple properties of Coq programs.
*)
(* ###################################################################### *)
(** * Enumerated Types *)
(** One unusual aspect of Coq is that its set of built-in
features is _extremely_ small. For example, instead of providing
the usual palette of atomic data types (booleans, integers,
strings, etc.), Coq offers an extremely powerful mechanism for
defining new data types from scratch -- so powerful that all these
familiar types arise as instances.
Naturally, the Coq distribution comes with an extensive standard
library providing definitions of booleans, numbers, and many
common data structures like lists and hash tables. But there is
nothing magic or primitive about these library definitions: they
are ordinary user code. To illustrate this, we will explicitly
recapitulate all the definitions we need in this course, rather
than just getting them implicitly from the library.
To see how this mechanism works, let's start with a very simple
example. *)
(* ###################################################################### *)
(** ** Days of the Week *)
(** The following declaration tells Coq that we are defining
a new set of data values -- a _type_. *)
Inductive day : Type :=
| monday : day
| tuesday : day
| wednesday : day
| thursday : day
| friday : day
| saturday : day
| sunday : day.
(** The type is called [day], and its members are [monday],
[tuesday], etc. The second and following lines of the definition
can be read "[monday] is a [day], [tuesday] is a [day], etc."
Having defined [day], we can write functions that operate on
days. *)
Definition next_weekday (d:day) : day :=
match d with
| monday => tuesday
| tuesday => wednesday
| wednesday => thursday
| thursday => friday
| friday => monday
| saturday => monday
| sunday => monday
end.
(** One thing to note is that the argument and return types of
this function are explicitly declared. Like most functional
programming languages, Coq can often figure out these types for
itself when they are not given explicitly -- i.e., it performs
some _type inference_ -- but we'll always include them to make
reading easier. *)
(** Having defined a function, we should check that it works on
some examples. There are actually three different ways to do this
in Coq.
First, we can use the command [Eval compute] to evaluate a
compound expression involving [next_weekday]. *)
Eval compute in (next_weekday friday).
(* ==> monday : day *)
Eval compute in (next_weekday (next_weekday saturday)).
(* ==> tuesday : day *)
(** If you have a computer handy, this would be an excellent
moment to fire up the Coq interpreter under your favorite IDE --
either CoqIde or Proof General -- and try this for yourself. Load
this file ([Basics.v]) from the book's accompanying Coq sources,
find the above example, submit it to Coq, and observe the
result. *)
(** The keyword [compute] tells Coq precisely how to
evaluate the expression we give it. For the moment, [compute] is
the only one we'll need; later on we'll see some alternatives that
are sometimes useful. *)
(** Second, we can record what we _expect_ the result to be in
the form of a Coq example: *)
Example test_next_weekday:
(next_weekday (next_weekday saturday)) = tuesday.
(** This declaration does two things: it makes an
assertion (that the second weekday after [saturday] is [tuesday]),
and it gives the assertion a name that can be used to refer to it
later. *)
(** Having made the assertion, we can also ask Coq to verify it,
like this: *)
Proof. simpl. reflexivity. Qed.
(** The details are not important for now (we'll come back to
them in a bit), but essentially this can be read as "The assertion
we've just made can be proved by observing that both sides of the
equality evaluate to the same thing, after some simplification." *)
(** Third, we can ask Coq to _extract_, from our [Definition], a
program in some other, more conventional, programming
language (OCaml, Scheme, or Haskell) with a high-performance
compiler. This facility is very interesting, since it gives us a
way to construct _fully certified_ programs in mainstream
languages. Indeed, this is one of the main uses for which Coq was
developed. We'll come back to this topic in later chapters. More
information can also be found in the Coq'Art book by Bertot and
Casteran, as well as the Coq reference manual. *)
(* ###################################################################### *)
(** ** Booleans *)
(** In a similar way, we can define the standard type [bool] of
booleans, with members [true] and [false]. *)
Inductive bool : Type :=
| true : bool
| false : bool.
(** Although we are rolling our own booleans here for the sake
of building up everything from scratch, Coq does, of course,
provide a default implementation of the booleans in its standard
library, together with a multitude of useful functions and
lemmas. (Take a look at [Coq.Init.Datatypes] in the Coq library
documentation if you're interested.) Whenever possible, we'll
name our own definitions and theorems so that they exactly
coincide with the ones in the standard library. *)
(** Functions over booleans can be defined in the same way as
above: *)
Definition negb (b:bool) : bool :=
match b with
| true => false
| false => true
end.
Definition andb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => b2
| false => false
end.
Definition orb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => true
| false => b2
end.
(** The last two illustrate the syntax for multi-argument
function definitions. *)
(** The following four "unit tests" constitute a complete
specification -- a truth table -- for the [orb] function: *)
Example test_orb1: (orb true false) = true.
Proof. reflexivity. Qed.
Example test_orb2: (orb false false) = false.
Proof. reflexivity. Qed.
Example test_orb3: (orb false true) = true.
Proof. reflexivity. Qed.
Example test_orb4: (orb true true) = true.
Proof. reflexivity. Qed.
(** (Note that we've dropped the [simpl] in the proofs. It's not
actually needed because [reflexivity] automatically performs
simplification.) *)
(** _A note on notation_: In .v files, we use square brackets to
delimit fragments of Coq code within comments; this convention,
also used by the [coqdoc] documentation tool, keeps them visually
separate from the surrounding text. In the html version of the
files, these pieces of text appear in a [different font]. *)
(** The values [Admitted] and [admit] can be used to fill
a hole in an incomplete definition or proof. We'll use them in the
following exercises. In general, your job in the exercises is
to replace [admit] or [Admitted] with real definitions or proofs. *)
(** **** Exercise: 1 star (nandb) *)
(** Complete the definition of the following function, then make
sure that the [Example] assertions below can each be verified by
Coq. *)
(** This function should return [true] if either or both of
its inputs are [false]. *)
Definition nandb (b1:bool) (b2:bool) : bool :=
match (b1, b2) with
| (true, true) => false
| _ => true
end.
(** Remove "[Admitted.]" and fill in each proof with
"[Proof. reflexivity. Qed.]" *)
Example test_nandb1: (nandb true false) = true.
Proof. reflexivity. Qed.
Example test_nandb2: (nandb false false) = true.
Proof. reflexivity. Qed.
Example test_nandb3: (nandb false true) = true.
Proof. reflexivity. Qed.
Example test_nandb4: (nandb true true) = false.
Proof. reflexivity. Qed.
(** [] *)
(** **** Exercise: 1 star (andb3) *)
(** Do the same for the [andb3] function below. This function should
return [true] when all of its inputs are [true], and [false]
otherwise. *)
Definition andb3 (b1:bool) (b2:bool) (b3:bool) : bool :=
match (b1, b2, b3) with
| (true, true, true) => true
| _ => false
end.
Example test_andb31: (andb3 true true true) = true.
Proof. reflexivity. Qed.
Example test_andb32: (andb3 false true true) = false.
Proof. reflexivity. Qed.
Example test_andb33: (andb3 true false true) = false.
Proof. reflexivity. Qed.
Example test_andb34: (andb3 true true false) = false.
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** ** Function Types *)
(** The [Check] command causes Coq to print the type of an
expression. For example, the type of [negb true] is [bool]. *)
Check true.
(* ===> true : bool *)
Check (negb true).
(* ===> negb true : bool *)
(** Functions like [negb] itself are also data values, just like
[true] and [false]. Their types are called _function types_, and
they are written with arrows. *)
Check negb.
(* ===> negb : bool -> bool *)
(** The type of [negb], written [bool -> bool] and pronounced
"[bool] arrow [bool]," can be read, "Given an input of type
[bool], this function produces an output of type [bool]."
Similarly, the type of [andb], written [bool -> bool -> bool], can
be read, "Given two inputs, both of type [bool], this function
produces an output of type [bool]." *)
(* ###################################################################### *)
(** ** Numbers *)
(** _Technical digression_: Coq provides a fairly sophisticated
_module system_, to aid in organizing large developments. In this
course we won't need most of its features, but one is useful: If
we enclose a collection of declarations between [Module X] and
[End X] markers, then, in the remainder of the file after the
[End], these definitions will be referred to by names like [X.foo]
instead of just [foo]. Here, we use this feature to introduce the
definition of the type [nat] in an inner module so that it does
not shadow the one from the standard library. *)
Module Playground1.
(** The types we have defined so far are examples of "enumerated
types": their definitions explicitly enumerate a finite set of
elements. A more interesting way of defining a type is to give a
collection of "inductive rules" describing its elements. For
example, we can define the natural numbers as follows: *)
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
(** The clauses of this definition can be read:
- [O] is a natural number (note that this is the letter "[O]," not
the numeral "[0]").
- [S] is a "constructor" that takes a natural number and yields
another one -- that is, if [n] is a natural number, then [S n]
is too.
Let's look at this in a little more detail.
Every inductively defined set ([day], [nat], [bool], etc.) is
actually a set of _expressions_. The definition of [nat] says how
expressions in the set [nat] can be constructed:
- the expression [O] belongs to the set [nat];
- if [n] is an expression belonging to the set [nat], then [S n]
is also an expression belonging to the set [nat]; and
- expressions formed in these two ways are the only ones belonging
to the set [nat].
The same rules apply for our definitions of [day] and [bool]. The
annotations we used for their constructors are analogous to the
one for the [O] constructor, and indicate that each of those
constructors doesn't take any arguments. *)
(** These three conditions are the precise force of the
[Inductive] declaration. They imply that the expression [O], the
expression [S O], the expression [S (S O)], the expression
[S (S (S O))], and so on all belong to the set [nat], while other
expressions like [true], [andb true false], and [S (S false)] do
not.
We can write simple functions that pattern match on natural
numbers just as we did above -- for example, the predecessor
function: *)
Definition pred (n : nat) : nat :=
match n with
| O => O
| S n' => n'
end.
(** The second branch can be read: "if [n] has the form [S n']
for some [n'], then return [n']." *)
End Playground1.
Definition minustwo (n : nat) : nat :=
match n with
| O => O
| S O => O
| S (S n') => n'
end.
(** Because natural numbers are such a pervasive form of data,
Coq provides a tiny bit of built-in magic for parsing and printing
them: ordinary arabic numerals can be used as an alternative to
the "unary" notation defined by the constructors [S] and [O]. Coq
prints numbers in arabic form by default: *)
Check (S (S (S (S O)))).
Eval compute in (minustwo 4).
(** The constructor [S] has the type [nat -> nat], just like the
functions [minustwo] and [pred]: *)
Check S.
Check pred.
Check minustwo.
(** These are all things that can be applied to a number to yield a
number. However, there is a fundamental difference: functions
like [pred] and [minustwo] come with _computation rules_ -- e.g.,
the definition of [pred] says that [pred 2] can be simplified to
[1] -- while the definition of [S] has no such behavior attached.
Although it is like a function in the sense that it can be applied
to an argument, it does not _do_ anything at all! *)
(** For most function definitions over numbers, pure pattern
matching is not enough: we also need recursion. For example, to
check that a number [n] is even, we may need to recursively check
whether [n-2] is even. To write such functions, we use the
keyword [Fixpoint]. *)
Fixpoint evenb (n:nat) : bool :=
match n with
| O => true
| S O => false
| S (S n') => evenb n'
end.
(** We can define [oddb] by a similar [Fixpoint] declaration, but here
is a simpler definition that will be a bit easier to work with: *)
Definition oddb (n:nat) : bool := negb (evenb n).
Example test_oddb1: (oddb (S O)) = true.
Proof. reflexivity. Qed.
Example test_oddb2: (oddb (S (S (S (S O))))) = false.
Proof. reflexivity. Qed.
(** Naturally, we can also define multi-argument functions by
recursion. (Once again, we use a module to avoid polluting the
namespace.) *)
Module Playground2.
Fixpoint plus (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus n' m)
end.
(** Adding three to two now gives us five, as we'd expect. *)
Eval compute in (plus (S (S (S O))) (S (S O))).
(** The simplification that Coq performs to reach this conclusion can
be visualized as follows: *)
(* [plus (S (S (S O))) (S (S O))]
==> [S (plus (S (S O)) (S (S O)))] by the second clause of the [match]
==> [S (S (plus (S O) (S (S O))))] by the second clause of the [match]
==> [S (S (S (plus O (S (S O)))))] by the second clause of the [match]
==> [S (S (S (S (S O))))] by the first clause of the [match]
*)
(** As a notational convenience, if two or more arguments have
the same type, they can be written together. In the following
definition, [(n m : nat)] means just the same as if we had written
[(n : nat) (m : nat)]. *)
Fixpoint mult (n m : nat) : nat :=
match n with
| O => O
| S n' => plus m (mult n' m)
end.
Example test_mult1: (mult 3 3) = 9.
Proof. reflexivity. Qed.
(** You can match two expressions at once by putting a comma
between them: *)
Fixpoint minus (n m:nat) : nat :=
match n, m with
| O , _ => O
| S _ , O => n
| S n', S m' => minus n' m'
end.
(** The _ in the first line is a _wildcard pattern_. Writing _ in a
pattern is the same as writing some variable that doesn't get used
on the right-hand side. This avoids the need to invent a bogus
variable name. *)
End Playground2.
Fixpoint exp (base power : nat) : nat :=
match power with
| O => S O
| S p => mult base (exp base p)
end.
(** **** Exercise: 1 star (factorial) *)
(** Recall the standard factorial function:
<<
factorial(0) = 1
factorial(n) = n * factorial(n-1) (if n>0)
>>
Translate this into Coq. *)
Fixpoint factorial (n:nat) : nat :=
match n with
| 0 => 1
| S n => S n * (factorial n)
end.
Example test_factorial1: (factorial 3) = 6.
Proof. reflexivity. Qed.
Example test_factorial2: (factorial 5) = (mult 10 12).
Proof. reflexivity. Qed.
(** [] *)
(** We can make numerical expressions a little easier to read and
write by introducing "notations" for addition, multiplication, and
subtraction. *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x - y" := (minus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
Check ((0 + 1) + 1).
(** (The [level], [associativity], and [nat_scope] annotations
control how these notations are treated by Coq's parser. The
details are not important, but interested readers can refer to the
"More on Notation" subsection in the "Advanced Material" section at
the end of this chapter.) *)
(** Note that these do not change the definitions we've already
made: they are simply instructions to the Coq parser to accept [x
+ y] in place of [plus x y] and, conversely, to the Coq
pretty-printer to display [plus x y] as [x + y]. *)
(** When we say that Coq comes with nothing built-in, we really
mean it: even equality testing for numbers is a user-defined
operation! *)
(** The [beq_nat] function tests [nat]ural numbers for [eq]uality,
yielding a [b]oolean. Note the use of nested [match]es (we could
also have used a simultaneous match, as we did in [minus].) *)
Fixpoint beq_nat (n m : nat) : bool :=
match n with
| O => match m with
| O => true
| S m' => false
end
| S n' => match m with
| O => false
| S m' => beq_nat n' m'
end
end.
(** Similarly, the [ble_nat] function tests [nat]ural numbers for
[l]ess-or-[e]qual, yielding a [b]oolean. *)
Fixpoint ble_nat (n m : nat) : bool :=
match n with
| O => true
| S n' =>
match m with
| O => false
| S m' => ble_nat n' m'
end
end.
Example test_ble_nat1: (ble_nat 2 2) = true.
Proof. reflexivity. Qed.
Example test_ble_nat2: (ble_nat 2 4) = true.
Proof. reflexivity. Qed.
Example test_ble_nat3: (ble_nat 4 2) = false.
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars (blt_nat) *)
(** The [blt_nat] function tests [nat]ural numbers for [l]ess-[t]han,
yielding a [b]oolean. Instead of making up a new [Fixpoint] for
this one, define it in terms of a previously defined function. *)
Definition blt_nat (n m : nat) : bool :=
if beq_nat n m then false else ble_nat n m.
Example test_blt_nat1: (blt_nat 2 2) = false.
Proof. reflexivity. Qed.
Example test_blt_nat2: (blt_nat 2 4) = true.
Proof. reflexivity. Qed.
Example test_blt_nat3: (blt_nat 4 2) = false.
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Simplification *)
(** Now that we've defined a few datatypes and functions, let's
turn to the question of how to state and prove properties of their
behavior. Actually, in a sense, we've already started doing this:
each [Example] in the previous sections makes a precise claim
about the behavior of some function on some particular inputs.
The proofs of these claims were always the same: use [reflexivity]
to check that both sides of the [=] simplify to identical values.
(By the way, it will be useful later to know that
[reflexivity] actually does somewhat more simplification than [simpl]
does -- for example, it tries "unfolding" defined terms, replacing them with
their right-hand sides. The reason for this difference is that,
when reflexivity succeeds, the whole goal is finished and we don't
need to look at whatever expanded expressions [reflexivity] has
found; by contrast, [simpl] is used in situations where we may
have to read and understand the new goal, so we would not want it
blindly expanding definitions.)
The same sort of "proof by simplification" can be used to prove
more interesting properties as well. For example, the fact that
[0] is a "neutral element" for [+] on the left can be proved
just by observing that [0 + n] reduces to [n] no matter what
[n] is, a fact that can be read directly off the definition of [plus].*)
Theorem plus_O_n : forall n : nat, 0 + n = n.
Proof.
intros n. reflexivity. Qed.
(** (_Note_: You may notice that the above statement looks
different in the original source file and the final html output. In Coq
files, we write the [forall] universal quantifier using the
"_forall_" reserved identifier. This gets printed as an
upside-down "A", the familiar symbol used in logic.) *)
(** The form of this theorem and proof are almost exactly the
same as the examples above; there are just a few differences.
First, we've used the keyword [Theorem] instead of
[Example]. Indeed, the difference is purely a matter of
style; the keywords [Example] and [Theorem] (and a few others,
including [Lemma], [Fact], and [Remark]) mean exactly the same
thing to Coq.
Secondly, we've added the quantifier [forall n:nat], so that our
theorem talks about _all_ natural numbers [n]. In order to prove
theorems of this form, we need to to be able to reason by
_assuming_ the existence of an arbitrary natural number [n]. This
is achieved in the proof by [intros n], which moves the quantifier
from the goal to a "context" of current assumptions. In effect, we
start the proof by saying "OK, suppose [n] is some arbitrary number."
The keywords [intros], [simpl], and [reflexivity] are examples of
_tactics_. A tactic is a command that is used between [Proof] and
[Qed] to tell Coq how it should check the correctness of some
claim we are making. We will see several more tactics in the rest
of this lecture, and yet more in future lectures. *)
(** We could try to prove a similar theorem about [plus] *)
Theorem plus_n_O : forall n, n + 0 = n.
(** However, unlike the previous proof, [simpl] doesn't do anything in
this case *)
Proof.
simpl. (* Doesn't do anything! *)
Abort.
(** (Can you explain why this happens? Step through both proofs with
Coq and notice how the goal and context change.) *)
Theorem plus_1_l : forall n:nat, 1 + n = S n.
Proof.
intros n. reflexivity. Qed.
Theorem mult_0_l : forall n:nat, 0 * n = 0.
Proof.
intros n. reflexivity. Qed.
(** The [_l] suffix in the names of these theorems is
pronounced "on the left." *)
(* ###################################################################### *)
(** * Proof by Rewriting *)
(** Here is a slightly more interesting theorem: *)
Theorem plus_id_example : forall n m:nat,
n = m ->
n + n = m + m.
(** Instead of making a completely universal claim about all numbers
[n] and [m], this theorem talks about a more specialized property
that only holds when [n = m]. The arrow symbol is pronounced
"implies."
As before, we need to be able to reason by assuming the existence
of some numbers [n] and [m]. We also need to assume the hypothesis
[n = m]. The [intros] tactic will serve to move all three of these
from the goal into assumptions in the current context.
Since [n] and [m] are arbitrary numbers, we can't just use
simplification to prove this theorem. Instead, we prove it by
observing that, if we are assuming [n = m], then we can replace
[n] with [m] in the goal statement and obtain an equality with the
same expression on both sides. The tactic that tells Coq to
perform this replacement is called [rewrite]. *)
Proof.
intros n m. (* move both quantifiers into the context *)
intros H. (* move the hypothesis into the context *)
rewrite -> H. (* Rewrite the goal using the hypothesis *)
reflexivity. Qed.
(** The first line of the proof moves the universally quantified
variables [n] and [m] into the context. The second moves the
hypothesis [n = m] into the context and gives it the (arbitrary)
name [H]. The third tells Coq to rewrite the current goal ([n + n
= m + m]) by replacing the left side of the equality hypothesis
[H] with the right side.
(The arrow symbol in the [rewrite] has nothing to do with
implication: it tells Coq to apply the rewrite from left to right.
To rewrite from right to left, you can use [rewrite <-]. Try
making this change in the above proof and see what difference it
makes in Coq's behavior.) *)
(** **** Exercise: 1 star (plus_id_exercise) *)
(** Remove "[Admitted.]" and fill in the proof. *)
Theorem plus_id_exercise : forall n m o : nat,
n = m -> m = o -> n + m = m + o.
Proof.
intros n m o H1 H2.
rewrite -> H1. rewrite <- H2. reflexivity.
Qed.
(** [] *)
(** As we've seen in earlier examples, the [Admitted] command
tells Coq that we want to skip trying to prove this theorem and
just accept it as a given. This can be useful for developing
longer proofs, since we can state subsidiary facts that we believe
will be useful for making some larger argument, use [Admitted] to
accept them on faith for the moment, and continue thinking about
the larger argument until we are sure it makes sense; then we can
go back and fill in the proofs we skipped. Be careful, though:
every time you say [Admitted] (or [admit]) you are leaving a door
open for total nonsense to enter Coq's nice, rigorous, formally
checked world! *)
(** We can also use the [rewrite] tactic with a previously proved
theorem instead of a hypothesis from the context. *)
Theorem mult_0_plus : forall n m : nat,
(0 + n) * m = n * m.
Proof.
intros n m.
rewrite -> plus_O_n.
reflexivity. Qed.
(** **** Exercise: 2 stars (mult_S_1) *)
Theorem mult_S_1 : forall n m : nat,
m = S n ->
m * (1 + n) = m * m.
Proof.
intros n m H0.
rewrite -> H0.
rewrite <- plus_1_l.
reflexivity.
Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Case Analysis *)
(** Of course, not everything can be proved by simple
calculation: In general, unknown, hypothetical values (arbitrary
numbers, booleans, lists, etc.) can block the calculation.
For example, if we try to prove the following fact using the
[simpl] tactic as above, we get stuck. *)
Theorem plus_1_neq_0_firsttry : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n.
simpl. (* does nothing! *)
Abort.
(** The reason for this is that the definitions of both
[beq_nat] and [+] begin by performing a [match] on their first
argument. But here, the first argument to [+] is the unknown
number [n] and the argument to [beq_nat] is the compound
expression [n + 1]; neither can be simplified.
What we need is to be able to consider the possible forms of [n]
separately. If [n] is [O], then we can calculate the final result
of [beq_nat (n + 1) 0] and check that it is, indeed, [false].
And if [n = S n'] for some [n'], then, although we don't know
exactly what number [n + 1] yields, we can calculate that, at
least, it will begin with one [S], and this is enough to calculate
that, again, [beq_nat (n + 1) 0] will yield [false].
The tactic that tells Coq to consider, separately, the cases where
[n = O] and where [n = S n'] is called [destruct]. *)
Theorem plus_1_neq_0 : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n. destruct n as [| n'].
reflexivity.
reflexivity. Qed.
(** The [destruct] generates _two_ subgoals, which we must then
prove, separately, in order to get Coq to accept the theorem as
proved. (No special command is needed for moving from one subgoal
to the other. When the first subgoal has been proved, it just
disappears and we are left with the other "in focus.") In this
proof, each of the subgoals is easily proved by a single use of
[reflexivity].
The annotation "[as [| n']]" is called an _intro pattern_. It
tells Coq what variable names to introduce in each subgoal. In
general, what goes between the square brackets is a _list_ of
lists of names, separated by [|]. Here, the first component is
empty, since the [O] constructor is nullary (it doesn't carry any
data). The second component gives a single name, [n'], since [S]
is a unary constructor.
The [destruct] tactic can be used with any inductively defined
datatype. For example, we use it here to prove that boolean
negation is involutive -- i.e., that negation is its own
inverse. *)
Theorem negb_involutive : forall b : bool,
negb (negb b) = b.
Proof.
intros b. destruct b.
reflexivity.
reflexivity. Qed.
(** Note that the [destruct] here has no [as] clause because
none of the subcases of the [destruct] need to bind any variables,
so there is no need to specify any names. (We could also have
written [as [|]], or [as []].) In fact, we can omit the [as]
clause from _any_ [destruct] and Coq will fill in variable names
automatically. Although this is convenient, it is arguably bad
style, since Coq often makes confusing choices of names when left
to its own devices. *)
(** **** Exercise: 1 star (zero_nbeq_plus_1) *)
Theorem zero_nbeq_plus_1 : forall n : nat,
beq_nat 0 (n + 1) = false.
Proof.
intros n. destruct n as [| n'].
reflexivity. reflexivity.
Qed.
(** [] *)
(* ###################################################################### *)
(** * More Exercises *)
(** **** Exercise: 2 stars (boolean_functions) *)
(** Use the tactics you have learned so far to prove the following
theorem about boolean functions. *)
Theorem identity_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = x) ->
forall (b : bool), f (f b) = b.
Proof.
intros f H0 b. rewrite -> H0. rewrite H0. reflexivity.
Qed.
(** Now state and prove a theorem [negation_fn_applied_twice] similar
to the previous one but where the second hypothesis says that the
function [f] has the property that [f x = negb x].*)
Theorem negation_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = negb x) -> forall (b:bool), f (f b) = b.
Proof.
intros H1 H2 b. rewrite H2. rewrite H2. rewrite -> negb_involutive. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars (andb_eq_orb) *)
(** Prove the following theorem. (You may want to first prove a
subsidiary lemma or two. Alternatively, remember that you do
not have to introduce all hypotheses at the same time.) *)
Theorem andb_eq_orb :
forall (b c : bool),
(andb b c = orb b c) ->
b = c.
Proof.
intros b c. destruct b.
destruct c.
intros H0. reflexivity.
intros H0. simpl in H0. rewrite -> H0. reflexivity.
destruct c. simpl. intros H0. rewrite -> H0. reflexivity.
simpl. intros H0. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars (binary) *)
(** Consider a different, more efficient representation of natural
numbers using a binary rather than unary system. That is, instead
of saying that each natural number is either zero or the successor
of a natural number, we can say that each binary number is either
- zero,
- twice a binary number, or
- one more than twice a binary number.
(a) First, write an inductive definition of the type [bin]
corresponding to this description of binary numbers.
(Hint: Recall that the definition of [nat] from class,
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
says nothing about what [O] and [S] "mean." It just says "[O] is
in the set called [nat], and if [n] is in the set then so is [S
n]." The interpretation of [O] as zero and [S] as successor/plus
one comes from the way that we _use_ [nat] values, by writing
functions to do things with them, proving things about them, and
so on. Your definition of [bin] should be correspondingly simple;
it is the functions you will write next that will give it
mathematical meaning.)
(b) Next, write an increment function [incr] for binary numbers,
and a function [bin_to_nat] to convert binary numbers to unary numbers.
(c) Write five unit tests [test_bin_incr1], [test_bin_incr2], etc.
for your increment and binary-to-unary functions. Notice that
incrementing a binary number and then converting it to unary
should yield the same result as first converting it to unary and
then incrementing.
*)
(* FILL IN HERE *)
(** [] *)
(* ###################################################################### *)
(** * More on Notation (Advanced) *)
(** In general, sections marked Advanced are not needed to follow the
rest of the book, except possibly other Advanced sections. On a
first reading, you might want to skim these sections so that you
know what's there for future reference. *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
(** For each notation-symbol in Coq we can specify its _precedence level_
and its _associativity_. The precedence level n can be specified by the
keywords [at level n] and it is helpful to disambiguate
expressions containing different symbols. The associativity is helpful
to disambiguate expressions containing more occurrences of the same
symbol. For example, the parameters specified above for [+] and [*]
say that the expression [1+2*3*4] is a shorthand for the expression
[(1+((2*3)*4))]. Coq uses precedence levels from 0 to 100, and
_left_, _right_, or _no_ associativity.
Each notation-symbol in Coq is also active in a _notation scope_.
Coq tries to guess what scope you mean, so when you write [S(O*O)]
it guesses [nat_scope], but when you write the cartesian
product (tuple) type [bool*bool] it guesses [type_scope].
Occasionally you have to help it out with percent-notation by
writing [(x*y)%nat], and sometimes in Coq's feedback to you it
will use [%nat] to indicate what scope a notation is in.
Notation scopes also apply to numeral notation (3,4,5, etc.), so you
may sometimes see [0%nat] which means [O], or [0%Z] which means the
Integer zero.
*)
(** * [Fixpoint] and Structural Recursion (Advanced) *)
Fixpoint plus' (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus' n' m)
end.
(** When Coq checks this definition, it notes that [plus'] is
"decreasing on 1st argument." What this means is that we are
performing a _structural recursion_ over the argument [n] -- i.e.,
that we make recursive calls only on strictly smaller values of
[n]. This implies that all calls to [plus'] will eventually
terminate. Coq demands that some argument of _every_ [Fixpoint]
definition is "decreasing".
This requirement is a fundamental feature of Coq's design: In
particular, it guarantees that every function that can be defined
in Coq will terminate on all inputs. However, because Coq's
"decreasing analysis" is not very sophisticated, it is sometimes
necessary to write functions in slightly unnatural ways. *)
(** **** Exercise: 2 stars, optional (decreasing) *)
(** To get a concrete sense of this, find a way to write a sensible
[Fixpoint] definition (of a simple function on numbers, say) that
_does_ terminate on all inputs, but that Coq will reject because
of this restriction. *)
(* FILL IN HERE *)
(** [] *)
(** $Date: 2014-12-31 15:31:47 -0500 (Wed, 31 Dec 2014) $ *)
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: openMSP430_defines.v
//
// *Module Description:
// openMSP430 Configuration file
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 180 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2013-02-25 22:23:18 +0100 (Mon, 25. Feb 2013) $
//----------------------------------------------------------------------------
//`define OMSP_NO_INCLUDE
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
//============================================================================
//============================================================================
// BASIC SYSTEM CONFIGURATION
//============================================================================
//============================================================================
//
// Note: the sum of program, data and peripheral memory spaces must not
// exceed 64 kB
//
// Program Memory Size:
// Uncomment the required memory size
//-------------------------------------------------------
//`define PMEM_SIZE_CUSTOM
//`define PMEM_SIZE_59_KB
//`define PMEM_SIZE_55_KB
//`define PMEM_SIZE_54_KB
//`define PMEM_SIZE_51_KB
//`define PMEM_SIZE_48_KB
//`define PMEM_SIZE_41_KB
//`define PMEM_SIZE_32_KB
//`define PMEM_SIZE_24_KB
//`define PMEM_SIZE_16_KB
//`define PMEM_SIZE_12_KB
`define PMEM_SIZE_8_KB // MSP430F[12]232: 8kB Flash
//`define PMEM_SIZE_4_KB
//`define PMEM_SIZE_2_KB
//`define PMEM_SIZE_1_KB
// Data Memory Size:
// Uncomment the required memory size
//-------------------------------------------------------
//`define DMEM_SIZE_CUSTOM
//`define DMEM_SIZE_32_KB
//`define DMEM_SIZE_24_KB
//`define DMEM_SIZE_16_KB
//`define DMEM_SIZE_10_KB
//`define DMEM_SIZE_8_KB
//`define DMEM_SIZE_5_KB
//`define DMEM_SIZE_4_KB
//`define DMEM_SIZE_2p5_KB
//`define DMEM_SIZE_2_KB
//`define DMEM_SIZE_1_KB
//`define DMEM_SIZE_512_B // MSP430F2232: 512 Bytes RAM
`define DMEM_SIZE_256_B // MSP430F1232: 256 Bytes RAM
//`define DMEM_SIZE_128_B
// Include/Exclude Hardware Multiplier
//`define MULTIPLIER // MSP430F[12]232: no multiplier
// Include/Exclude Serial Debug interface
`define DBG_EN
//============================================================================
//============================================================================
// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
//============================================================================
//============================================================================
//-------------------------------------------------------
// Custom user version number
//-------------------------------------------------------
// This 5 bit field can be freely used in order to allow
// custom identification of the system through the debug
// interface.
// (see CPU_ID.USER_VERSION field in the documentation)
//-------------------------------------------------------
`define USER_VERSION 5'b00000
//-------------------------------------------------------
// Include/Exclude Watchdog timer
//-------------------------------------------------------
// When excluded, the following functionality will be
// lost:
// - Watchog (both interval and watchdog modes)
// - NMI interrupt edge selection
// - Possibility to generate a software PUC reset
//-------------------------------------------------------
// Hansi: we don't use the watchdog
// `define WATCHDOG
//-------------------------------------------------------
// Include/Exclude Non-Maskable-Interrupt support
//-------------------------------------------------------
// Hansi: we don't use the NMI
//`define NMI
//-------------------------------------------------------
// Input synchronizers
//-------------------------------------------------------
// In some cases, the asynchronous input ports might
// already be synchronized externally.
// If an extensive CDC design review showed that this
// is really the case, the individual synchronizers
// can be disabled with the following defines.
//
// Notes:
// - all three signals are all sampled in the MCLK domain
//
// - the dbg_en signal reset the debug interface
// when 0. Therefore make sure it is glitch free.
//
//-------------------------------------------------------
`define SYNC_NMI
//`define SYNC_CPU_EN
//`define SYNC_DBG_EN
//-------------------------------------------------------
// Peripheral Memory Space:
//-------------------------------------------------------
// The original MSP430 architecture map the peripherals
// from 0x0000 to 0x01FF (i.e. 512B of the memory space).
// The following defines allow you to expand this space
// up to 32 kB (i.e. from 0x0000 to 0x7fff).
// As a consequence, the data memory mapping will be
// shifted up and a custom linker script will therefore
// be required by the GCC compiler.
//-------------------------------------------------------
//`define PER_SIZE_CUSTOM
//`define PER_SIZE_32_KB
//`define PER_SIZE_16_KB
//`define PER_SIZE_8_KB
//`define PER_SIZE_4_KB
//`define PER_SIZE_2_KB
//`define PER_SIZE_1_KB
`define PER_SIZE_512_B
//-------------------------------------------------------
// Defines the debugger CPU_CTL.RST_BRK_EN reset value
// (CPU break on PUC reset)
//-------------------------------------------------------
// When defined, the CPU will automatically break after
// a PUC occurrence by default. This is typically useful
// when the program memory can only be initialized through
// the serial debug interface.
//-------------------------------------------------------
`define DBG_RST_BRK_EN
//============================================================================
//============================================================================
// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
//============================================================================
//============================================================================
//
// IMPORTANT NOTE: Please update following configuration options ONLY if
// you have a good reason to do so... and if you know what
// you are doing :-P
//
//============================================================================
//-------------------------------------------------------
// Select serial debug interface protocol
//-------------------------------------------------------
// DBG_UART -> Enable UART (8N1) debug interface
// DBG_I2C -> Enable I2C debug interface
//-------------------------------------------------------
//`define DBG_UART
`define DBG_I2C
//-------------------------------------------------------
// Enable the I2C broadcast address
//-------------------------------------------------------
// For multicore systems, a common I2C broadcast address
// can be given to all oMSP cores in order to
// synchronously RESET, START, STOP, or STEP all CPUs
// at once with a single I2C command.
// If you have a single openMSP430 in your system,
// this option can stay commented-out.
//-------------------------------------------------------
//`define DBG_I2C_BROADCAST
//-------------------------------------------------------
// Number of hardware breakpoint/watchpoint units
// (each unit contains two hardware addresses available
// for breakpoints or watchpoints):
// - DBG_HWBRK_0 -> Include hardware breakpoints unit 0
// - DBG_HWBRK_1 -> Include hardware breakpoints unit 1
// - DBG_HWBRK_2 -> Include hardware breakpoints unit 2
// - DBG_HWBRK_3 -> Include hardware breakpoints unit 3
//-------------------------------------------------------
// Please keep in mind that hardware breakpoints only
// make sense whenever the program memory is not an SRAM
// (i.e. Flash/OTP/ROM/...) or when you are interested
// in data breakpoints.
//-------------------------------------------------------
`define DBG_HWBRK_0
`define DBG_HWBRK_1
//`define DBG_HWBRK_2
//`define DBG_HWBRK_3
//-------------------------------------------------------
// Enable/Disable the hardware breakpoint RANGE mode
//-------------------------------------------------------
// When enabled this feature allows the hardware breakpoint
// units to stop the cpu whenever an instruction or data
// access lays within an address range.
// Note that this feature is not supported by GDB.
//-------------------------------------------------------
//`define DBG_HWBRK_RANGE
//-------------------------------------------------------
// Custom Program/Data and Peripheral Memory Spaces
//-------------------------------------------------------
// The following values are valid only if the
// corresponding *_SIZE_CUSTOM defines are uncommented:
//
// - *_SIZE : size of the section in bytes.
// - *_AWIDTH : address port width, this value must allow
// to address all WORDS of the section
// (i.e. the *_SIZE divided by 2)
//-------------------------------------------------------
// Custom Program memory (enabled with PMEM_SIZE_CUSTOM)
`define PMEM_CUSTOM_AWIDTH 10
`define PMEM_CUSTOM_SIZE 2048
// Custom Data memory (enabled with DMEM_SIZE_CUSTOM)
`define DMEM_CUSTOM_AWIDTH 6
`define DMEM_CUSTOM_SIZE 128
// Custom Peripheral memory (enabled with PER_SIZE_CUSTOM)
`define PER_CUSTOM_AWIDTH 8
`define PER_CUSTOM_SIZE 512
//-------------------------------------------------------
// ASIC version
//-------------------------------------------------------
// When uncommented, this define will enable the
// ASIC system configuration section (see below) and
// will activate scan support for production test.
//
// WARNING: if you target an FPGA, leave this define
// commented.
//-------------------------------------------------------
`define ASIC
//============================================================================
//============================================================================
// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS/PROFESSIONALS ONLY !!!! )
//============================================================================
//============================================================================
`ifdef ASIC
//===============================================================
// FINE GRAINED CLOCK GATING
//===============================================================
//-------------------------------------------------------
// When uncommented, this define will enable the fine
// grained clock gating of all registers in the core.
//-------------------------------------------------------
// Hansi: let the synthesis tool do the clock gating
//`define CLOCK_GATING
//===============================================================
// ASIC CLOCKING
//===============================================================
//-------------------------------------------------------
// When uncommented, this define will enable the ASIC
// architectural clock gating as well as the advanced low
// power modes support (most common).
// Comment this out in order to get FPGA-like clocking.
//-------------------------------------------------------
`define ASIC_CLOCKING
`ifdef ASIC_CLOCKING
//===============================================================
// LFXT CLOCK DOMAIN
//===============================================================
//-------------------------------------------------------
// When uncommented, this define will enable the lfxt_clk
// clock domain.
// When commented out, the whole chip is clocked with dco_clk.
//-------------------------------------------------------
// Hansi: no second clock
//`define LFXT_DOMAIN
//===============================================================
// CLOCK MUXES
//===============================================================
//-------------------------------------------------------
// MCLK: Clock Mux
//-------------------------------------------------------
// When uncommented, this define will enable the
// MCLK clock MUX allowing the selection between
// DCO_CLK and LFXT_CLK with the BCSCTL2.SELMx register.
// When commented, DCO_CLK is selected.
//-------------------------------------------------------
// Hansi: only use DCO_CLK
//`define MCLK_MUX
//-------------------------------------------------------
// SMCLK: Clock Mux
//-------------------------------------------------------
// When uncommented, this define will enable the
// SMCLK clock MUX allowing the selection between
// DCO_CLK and LFXT_CLK with the BCSCTL2.SELS register.
// When commented, DCO_CLK is selected.
//-------------------------------------------------------
// Hansi: only use DCO_CLK
//`define SMCLK_MUX
//-------------------------------------------------------
// WATCHDOG: Clock Mux
//-------------------------------------------------------
// When uncommented, this define will enable the
// Watchdog clock MUX allowing the selection between
// ACLK and SMCLK with the WDTCTL.WDTSSEL register.
// When commented out, ACLK is selected if the
// WATCHDOG_NOMUX_ACLK define is uncommented, SMCLK is
// selected otherwise.
//-------------------------------------------------------
// Hansi: only use DCO_CLK
//`define WATCHDOG_MUX
//`define WATCHDOG_NOMUX_ACLK
//===============================================================
// CLOCK DIVIDERS
//===============================================================
//-------------------------------------------------------
// MCLK: Clock divider
//-------------------------------------------------------
// When uncommented, this define will enable the
// MCLK clock divider (/1/2/4/8)
//-------------------------------------------------------
// Hansi: no divider
//`define MCLK_DIVIDER
//-------------------------------------------------------
// SMCLK: Clock divider (/1/2/4/8)
//-------------------------------------------------------
// When uncommented, this define will enable the
// SMCLK clock divider
//-------------------------------------------------------
// Hansi: no divider
//`define SMCLK_DIVIDER
//-------------------------------------------------------
// ACLK: Clock divider (/1/2/4/8)
//-------------------------------------------------------
// When uncommented, this define will enable the
// ACLK clock divider
//-------------------------------------------------------
// Hansi: no divider
//`define ACLK_DIVIDER
//===============================================================
// LOW POWER MODES
//===============================================================
//-------------------------------------------------------
// LOW POWER MODE: CPUOFF
//-------------------------------------------------------
// When uncommented, this define will include the
// clock gate allowing to switch off MCLK in
// all low power modes: LPM0, LPM1, LPM2, LPM3, LPM4
//-------------------------------------------------------
`define CPUOFF_EN
//-------------------------------------------------------
// LOW POWER MODE: SCG0
//-------------------------------------------------------
// When uncommented, this define will enable the
// DCO_ENABLE/WKUP port control (always 1 when commented).
// This allows to switch off the DCO oscillator in the
// following low power modes: LPM1, LPM3, LPM4
//-------------------------------------------------------
// Hansi: we don't switch off the DCO oscillator, because there is none
//`define SCG0_EN
//-------------------------------------------------------
// LOW POWER MODE: SCG1
//-------------------------------------------------------
// When uncommented, this define will include the
// clock gate allowing to switch off SMCLK in
// the following low power modes: LPM2, LPM3, LPM4
//-------------------------------------------------------
`define SCG1_EN
//-------------------------------------------------------
// LOW POWER MODE: OSCOFF
//-------------------------------------------------------
// When uncommented, this define will include the
// LFXT_CLK clock gate and enable the LFXT_ENABLE/WKUP
// port control (always 1 when commented).
// This allows to switch off the low frequency oscillator
// in the following low power modes: LPM4
//-------------------------------------------------------
// Hansi: we don't switch off the LFXT oscillator, because there is none
//`define OSCOFF_EN
`endif // ASIC_CLOCKING
`endif // ASIC
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//===== SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!! =====//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//
// PROGRAM, DATA & PERIPHERAL MEMORY CONFIGURATION
//==================================================
// Program Memory Size
`ifdef PMEM_SIZE_59_KB
`define PMEM_AWIDTH 15
`define PMEM_SIZE 60416
`endif
`ifdef PMEM_SIZE_55_KB
`define PMEM_AWIDTH 15
`define PMEM_SIZE 56320
`endif
`ifdef PMEM_SIZE_54_KB
`define PMEM_AWIDTH 15
`define PMEM_SIZE 55296
`endif
`ifdef PMEM_SIZE_51_KB
`define PMEM_AWIDTH 15
`define PMEM_SIZE 52224
`endif
`ifdef PMEM_SIZE_48_KB
`define PMEM_AWIDTH 15
`define PMEM_SIZE 49152
`endif
`ifdef PMEM_SIZE_41_KB
`define PMEM_AWIDTH 15
`define PMEM_SIZE 41984
`endif
`ifdef PMEM_SIZE_32_KB
`define PMEM_AWIDTH 14
`define PMEM_SIZE 32768
`endif
`ifdef PMEM_SIZE_24_KB
`define PMEM_AWIDTH 14
`define PMEM_SIZE 24576
`endif
`ifdef PMEM_SIZE_16_KB
`define PMEM_AWIDTH 13
`define PMEM_SIZE 16384
`endif
`ifdef PMEM_SIZE_12_KB
`define PMEM_AWIDTH 13
`define PMEM_SIZE 12288
`endif
`ifdef PMEM_SIZE_8_KB
`define PMEM_AWIDTH 12
`define PMEM_SIZE 8192
`endif
`ifdef PMEM_SIZE_4_KB
`define PMEM_AWIDTH 11
`define PMEM_SIZE 4096
`endif
`ifdef PMEM_SIZE_2_KB
`define PMEM_AWIDTH 10
`define PMEM_SIZE 2048
`endif
`ifdef PMEM_SIZE_1_KB
`define PMEM_AWIDTH 9
`define PMEM_SIZE 1024
`endif
`ifdef PMEM_SIZE_CUSTOM
`define PMEM_AWIDTH `PMEM_CUSTOM_AWIDTH
`define PMEM_SIZE `PMEM_CUSTOM_SIZE
`endif
// Data Memory Size
`ifdef DMEM_SIZE_32_KB
`define DMEM_AWIDTH 14
`define DMEM_SIZE 32768
`endif
`ifdef DMEM_SIZE_24_KB
`define DMEM_AWIDTH 14
`define DMEM_SIZE 24576
`endif
`ifdef DMEM_SIZE_16_KB
`define DMEM_AWIDTH 13
`define DMEM_SIZE 16384
`endif
`ifdef DMEM_SIZE_10_KB
`define DMEM_AWIDTH 13
`define DMEM_SIZE 10240
`endif
`ifdef DMEM_SIZE_8_KB
`define DMEM_AWIDTH 12
`define DMEM_SIZE 8192
`endif
`ifdef DMEM_SIZE_5_KB
`define DMEM_AWIDTH 12
`define DMEM_SIZE 5120
`endif
`ifdef DMEM_SIZE_4_KB
`define DMEM_AWIDTH 11
`define DMEM_SIZE 4096
`endif
`ifdef DMEM_SIZE_2p5_KB
`define DMEM_AWIDTH 11
`define DMEM_SIZE 2560
`endif
`ifdef DMEM_SIZE_2_KB
`define DMEM_AWIDTH 10
`define DMEM_SIZE 2048
`endif
`ifdef DMEM_SIZE_1_KB
`define DMEM_AWIDTH 9
`define DMEM_SIZE 1024
`endif
`ifdef DMEM_SIZE_512_B
`define DMEM_AWIDTH 8
`define DMEM_SIZE 512
`endif
`ifdef DMEM_SIZE_256_B
`define DMEM_AWIDTH 7
`define DMEM_SIZE 256
`endif
`ifdef DMEM_SIZE_128_B
`define DMEM_AWIDTH 6
`define DMEM_SIZE 128
`endif
`ifdef DMEM_SIZE_CUSTOM
`define DMEM_AWIDTH `DMEM_CUSTOM_AWIDTH
`define DMEM_SIZE `DMEM_CUSTOM_SIZE
`endif
// Peripheral Memory Size
`ifdef PER_SIZE_32_KB
`define PER_AWIDTH 14
`define PER_SIZE 32768
`endif
`ifdef PER_SIZE_16_KB
`define PER_AWIDTH 13
`define PER_SIZE 16384
`endif
`ifdef PER_SIZE_8_KB
`define PER_AWIDTH 12
`define PER_SIZE 8192
`endif
`ifdef PER_SIZE_4_KB
`define PER_AWIDTH 11
`define PER_SIZE 4096
`endif
`ifdef PER_SIZE_2_KB
`define PER_AWIDTH 10
`define PER_SIZE 2048
`endif
`ifdef PER_SIZE_1_KB
`define PER_AWIDTH 9
`define PER_SIZE 1024
`endif
`ifdef PER_SIZE_512_B
`define PER_AWIDTH 8
`define PER_SIZE 512
`endif
`ifdef PER_SIZE_CUSTOM
`define PER_AWIDTH `PER_CUSTOM_AWIDTH
`define PER_SIZE `PER_CUSTOM_SIZE
`endif
// Data Memory Base Adresses
`define DMEM_BASE `PER_SIZE
// Program & Data Memory most significant address bit (for 16 bit words)
`define PMEM_MSB `PMEM_AWIDTH-1
`define DMEM_MSB `DMEM_AWIDTH-1
`define PER_MSB `PER_AWIDTH-1
//
// STATES, REGISTER FIELDS, ...
//======================================
// Instructions type
`define INST_SO 0
`define INST_JMP 1
`define INST_TO 2
// Single-operand arithmetic
`define RRC 0
`define SWPB 1
`define RRA 2
`define SXT 3
`define PUSH 4
`define CALL 5
`define RETI 6
`define IRQ 7
// Conditional jump
`define JNE 0
`define JEQ 1
`define JNC 2
`define JC 3
`define JN 4
`define JGE 5
`define JL 6
`define JMP 7
// Two-operand arithmetic
`define MOV 0
`define ADD 1
`define ADDC 2
`define SUBC 3
`define SUB 4
`define CMP 5
`define DADD 6
`define BIT 7
`define BIC 8
`define BIS 9
`define XOR 10
`define AND 11
// Addressing modes
`define DIR 0
`define IDX 1
`define INDIR 2
`define INDIR_I 3
`define SYMB 4
`define IMM 5
`define ABS 6
`define CONST 7
// Instruction state machine
`define I_IRQ_FETCH 3'h0
`define I_IRQ_DONE 3'h1
`define I_DEC 3'h2
`define I_EXT1 3'h3
`define I_EXT2 3'h4
`define I_IDLE 3'h5
// Execution state machine
// (swapped E_IRQ_0 and E_IRQ_2 values to suppress glitch generation warning from lint tool)
`define E_IRQ_0 4'h2
`define E_IRQ_1 4'h1
`define E_IRQ_2 4'h0
`define E_IRQ_3 4'h3
`define E_IRQ_4 4'h4
`define E_SRC_AD 4'h5
`define E_SRC_RD 4'h6
`define E_SRC_WR 4'h7
`define E_DST_AD 4'h8
`define E_DST_RD 4'h9
`define E_DST_WR 4'hA
`define E_EXEC 4'hB
`define E_JUMP 4'hC
`define E_IDLE 4'hD
// ALU control signals
`define ALU_SRC_INV 0
`define ALU_INC 1
`define ALU_INC_C 2
`define ALU_ADD 3
`define ALU_AND 4
`define ALU_OR 5
`define ALU_XOR 6
`define ALU_DADD 7
`define ALU_STAT_7 8
`define ALU_STAT_F 9
`define ALU_SHIFT 10
`define EXEC_NO_WR 11
// Debug interface
`define DBG_UART_WR 18
`define DBG_UART_BW 17
`define DBG_UART_ADDR 16:11
// Debug interface CPU_CTL register
`define HALT 0
`define RUN 1
`define ISTEP 2
`define SW_BRK_EN 3
`define FRZ_BRK_EN 4
`define RST_BRK_EN 5
`define CPU_RST 6
// Debug interface CPU_STAT register
`define HALT_RUN 0
`define PUC_PND 1
`define SWBRK_PND 3
`define HWBRK0_PND 4
`define HWBRK1_PND 5
// Debug interface BRKx_CTL register
`define BRK_MODE_RD 0
`define BRK_MODE_WR 1
`define BRK_MODE 1:0
`define BRK_EN 2
`define BRK_I_EN 3
`define BRK_RANGE 4
// Basic clock module: BCSCTL1 Control Register
`define DIVAx 5:4
// Basic clock module: BCSCTL2 Control Register
`define SELMx 7
`define DIVMx 5:4
`define SELS 3
`define DIVSx 2:1
// MCLK Clock gate
`ifdef CPUOFF_EN
`define MCLK_CGATE
`else
`ifdef MCLK_DIVIDER
`define MCLK_CGATE
`endif
`endif
// SMCLK Clock gate
`ifdef SCG1_EN
`define SMCLK_CGATE
`else
`ifdef SMCLK_DIVIDER
`define SMCLK_CGATE
`endif
`endif
//
// DEBUG INTERFACE EXTRA CONFIGURATION
//======================================
// Debug interface: CPU version
`define CPU_VERSION 3'h2
// Debug interface: Software breakpoint opcode
`define DBG_SWBRK_OP 16'h4343
// Debug UART interface auto data synchronization
// If the following define is commented out, then
// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly
// defined.
`define DBG_UART_AUTO_SYNC
// Debug UART interface data rate
// In order to properly setup the UART debug interface, you
// need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and
// the chosen BAUD rate from the UART interface.
//
//`define DBG_UART_BAUD 9600
//`define DBG_UART_BAUD 19200
//`define DBG_UART_BAUD 38400
//`define DBG_UART_BAUD 57600
//`define DBG_UART_BAUD 115200
//`define DBG_UART_BAUD 230400
//`define DBG_UART_BAUD 460800
//`define DBG_UART_BAUD 576000
//`define DBG_UART_BAUD 921600
`define DBG_UART_BAUD 2000000
`define DBG_DCO_FREQ 20000000
`define DBG_UART_CNT ((`DBG_DCO_FREQ/`DBG_UART_BAUD)-1)
// Debug interface input synchronizer
`define SYNC_DBG_UART_RXD
// Enable/Disable the hardware breakpoint RANGE mode
`ifdef DBG_HWBRK_RANGE
`define HWBRK_RANGE 1'b1
`else
`define HWBRK_RANGE 1'b0
`endif
// Counter width for the debug interface UART
`define DBG_UART_XFER_CNT_W 16
// Check configuration
`ifdef DBG_EN
`ifdef DBG_UART
`ifdef DBG_I2C
CONFIGURATION ERROR: I2C AND UART DEBUG INTERFACE ARE BOTH ENABLED
`endif
`else
`ifdef DBG_I2C
`else
CONFIGURATION ERROR: I2C OR UART DEBUG INTERFACE SHOULD BE ENABLED
`endif
`endif
`endif
//
// MULTIPLIER CONFIGURATION
//======================================
// If uncommented, the following define selects
// the 16x16 multiplier (1 cycle) instead of the
// default 16x8 multplier (2 cycles)
//`define MPY_16x16
//======================================
// CONFIGURATION CHECKS
//======================================
`ifdef LFXT_DOMAIN
`else
`ifdef MCLK_MUX
CONFIGURATION ERROR: THE MCLK_MUX CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
`endif
`ifdef SMCLK_MUX
CONFIGURATION ERROR: THE SMCLK_MUX CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
`endif
`ifdef WATCHDOG_MUX
CONFIGURATION ERROR: THE WATCHDOG_MUX CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
`else
`ifdef WATCHDOG_NOMUX_ACLK
CONFIGURATION ERROR: THE WATCHDOG_NOMUX_ACLK CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
`endif
`endif
`ifdef OSCOFF_EN
CONFIGURATION ERROR: THE OSCOFF LOW POWER MODE CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
`endif
`endif
|
//Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
//Date : Wed Oct 18 20:30:29 2017
//Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
//Command : generate_target design_1.bd
//Design : design_1
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CORE_GENERATION_INFO = "design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=47,numReposBlks=26,numNonXlnxBlks=1,numHierBlks=21,maxHierDepth=1,numSysgenBlks=0,numHlsBlks=1,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_axi4_cnt=12,da_bram_cntlr_cnt=6,da_ps7_cnt=1,synth_mode=Global}" *) (* HW_HANDOFF = "design_1.hwdef" *)
module design_1
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb);
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DDR, AXI_ARBITRATION_SCHEME TDM, BURST_LENGTH 8, CAN_DEBUG false, CAS_LATENCY 11, CAS_WRITE_LATENCY 11, CS_ENABLED true, DATA_MASK_ENABLED true, DATA_WIDTH 8, MEMORY_TYPE COMPONENTS, MEM_ADDR_MAP ROW_COLUMN_BANK, SLOT Single, TIMEPERIOD_PS 1250" *) inout [14:0]DDR_addr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_ba;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_cas_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_ck_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_ck_p;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_cke;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_cs_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [3:0]DDR_dm;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [31:0]DDR_dq;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [3:0]DDR_dqs_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) inout [3:0]DDR_dqs_p;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_odt;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_ras_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_reset_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_we_n;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false" *) inout FIXED_IO_ddr_vrn;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout FIXED_IO_ddr_vrp;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]FIXED_IO_mio;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout FIXED_IO_ps_clk;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) inout FIXED_IO_ps_porb;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout FIXED_IO_ps_srstb;
wire [31:0]axi_mem_intercon_M00_AXI_ARADDR;
wire [1:0]axi_mem_intercon_M00_AXI_ARBURST;
wire [3:0]axi_mem_intercon_M00_AXI_ARCACHE;
wire [3:0]axi_mem_intercon_M00_AXI_ARLEN;
wire [1:0]axi_mem_intercon_M00_AXI_ARLOCK;
wire [2:0]axi_mem_intercon_M00_AXI_ARPROT;
wire [3:0]axi_mem_intercon_M00_AXI_ARQOS;
wire axi_mem_intercon_M00_AXI_ARREADY;
wire [2:0]axi_mem_intercon_M00_AXI_ARSIZE;
wire axi_mem_intercon_M00_AXI_ARVALID;
wire [31:0]axi_mem_intercon_M00_AXI_AWADDR;
wire [1:0]axi_mem_intercon_M00_AXI_AWBURST;
wire [3:0]axi_mem_intercon_M00_AXI_AWCACHE;
wire [3:0]axi_mem_intercon_M00_AXI_AWLEN;
wire [1:0]axi_mem_intercon_M00_AXI_AWLOCK;
wire [2:0]axi_mem_intercon_M00_AXI_AWPROT;
wire [3:0]axi_mem_intercon_M00_AXI_AWQOS;
wire axi_mem_intercon_M00_AXI_AWREADY;
wire [2:0]axi_mem_intercon_M00_AXI_AWSIZE;
wire axi_mem_intercon_M00_AXI_AWVALID;
wire axi_mem_intercon_M00_AXI_BREADY;
wire [1:0]axi_mem_intercon_M00_AXI_BRESP;
wire axi_mem_intercon_M00_AXI_BVALID;
wire [63:0]axi_mem_intercon_M00_AXI_RDATA;
wire axi_mem_intercon_M00_AXI_RLAST;
wire axi_mem_intercon_M00_AXI_RREADY;
wire [1:0]axi_mem_intercon_M00_AXI_RRESP;
wire axi_mem_intercon_M00_AXI_RVALID;
wire [63:0]axi_mem_intercon_M00_AXI_WDATA;
wire axi_mem_intercon_M00_AXI_WLAST;
wire axi_mem_intercon_M00_AXI_WREADY;
wire [7:0]axi_mem_intercon_M00_AXI_WSTRB;
wire axi_mem_intercon_M00_AXI_WVALID;
wire [31:0]convolve_kernel_0_bufi_PORTA_ADDR;
wire convolve_kernel_0_bufi_PORTA_CLK;
wire [31:0]convolve_kernel_0_bufi_PORTA_DIN;
wire [31:0]convolve_kernel_0_bufi_PORTA_DOUT;
wire convolve_kernel_0_bufi_PORTA_EN;
wire convolve_kernel_0_bufi_PORTA_RST;
wire [3:0]convolve_kernel_0_bufi_PORTA_WE;
wire [31:0]convolve_kernel_0_bufo_PORTA_ADDR;
wire convolve_kernel_0_bufo_PORTA_CLK;
wire [31:0]convolve_kernel_0_bufo_PORTA_DIN;
wire [31:0]convolve_kernel_0_bufo_PORTA_DOUT;
wire convolve_kernel_0_bufo_PORTA_EN;
wire convolve_kernel_0_bufo_PORTA_RST;
wire [3:0]convolve_kernel_0_bufo_PORTA_WE;
wire [31:0]convolve_kernel_0_bufw_PORTA_ADDR;
wire convolve_kernel_0_bufw_PORTA_CLK;
wire [31:0]convolve_kernel_0_bufw_PORTA_DIN;
wire [31:0]convolve_kernel_0_bufw_PORTA_DOUT;
wire convolve_kernel_0_bufw_PORTA_EN;
wire convolve_kernel_0_bufw_PORTA_RST;
wire [3:0]convolve_kernel_0_bufw_PORTA_WE;
wire [31:0]hier_bram_1_M00_AXI_ARADDR;
wire [1:0]hier_bram_1_M00_AXI_ARBURST;
wire [3:0]hier_bram_1_M00_AXI_ARCACHE;
wire [3:0]hier_bram_1_M00_AXI_ARLEN;
wire [1:0]hier_bram_1_M00_AXI_ARLOCK;
wire [2:0]hier_bram_1_M00_AXI_ARPROT;
wire [3:0]hier_bram_1_M00_AXI_ARQOS;
wire hier_bram_1_M00_AXI_ARREADY;
wire [2:0]hier_bram_1_M00_AXI_ARSIZE;
wire hier_bram_1_M00_AXI_ARVALID;
wire [31:0]hier_bram_1_M00_AXI_AWADDR;
wire [1:0]hier_bram_1_M00_AXI_AWBURST;
wire [3:0]hier_bram_1_M00_AXI_AWCACHE;
wire [3:0]hier_bram_1_M00_AXI_AWLEN;
wire [1:0]hier_bram_1_M00_AXI_AWLOCK;
wire [2:0]hier_bram_1_M00_AXI_AWPROT;
wire [3:0]hier_bram_1_M00_AXI_AWQOS;
wire hier_bram_1_M00_AXI_AWREADY;
wire [2:0]hier_bram_1_M00_AXI_AWSIZE;
wire hier_bram_1_M00_AXI_AWVALID;
wire hier_bram_1_M00_AXI_BREADY;
wire [1:0]hier_bram_1_M00_AXI_BRESP;
wire hier_bram_1_M00_AXI_BVALID;
wire [63:0]hier_bram_1_M00_AXI_RDATA;
wire hier_bram_1_M00_AXI_RLAST;
wire hier_bram_1_M00_AXI_RREADY;
wire [1:0]hier_bram_1_M00_AXI_RRESP;
wire hier_bram_1_M00_AXI_RVALID;
wire [63:0]hier_bram_1_M00_AXI_WDATA;
wire hier_bram_1_M00_AXI_WLAST;
wire hier_bram_1_M00_AXI_WREADY;
wire [7:0]hier_bram_1_M00_AXI_WSTRB;
wire hier_bram_1_M00_AXI_WVALID;
wire [31:0]hier_bram_2_M00_AXI_ARADDR;
wire [1:0]hier_bram_2_M00_AXI_ARBURST;
wire [3:0]hier_bram_2_M00_AXI_ARCACHE;
wire [3:0]hier_bram_2_M00_AXI_ARLEN;
wire [1:0]hier_bram_2_M00_AXI_ARLOCK;
wire [2:0]hier_bram_2_M00_AXI_ARPROT;
wire [3:0]hier_bram_2_M00_AXI_ARQOS;
wire hier_bram_2_M00_AXI_ARREADY;
wire [2:0]hier_bram_2_M00_AXI_ARSIZE;
wire hier_bram_2_M00_AXI_ARVALID;
wire [31:0]hier_bram_2_M00_AXI_AWADDR;
wire [1:0]hier_bram_2_M00_AXI_AWBURST;
wire [3:0]hier_bram_2_M00_AXI_AWCACHE;
wire [3:0]hier_bram_2_M00_AXI_AWLEN;
wire [1:0]hier_bram_2_M00_AXI_AWLOCK;
wire [2:0]hier_bram_2_M00_AXI_AWPROT;
wire [3:0]hier_bram_2_M00_AXI_AWQOS;
wire hier_bram_2_M00_AXI_AWREADY;
wire [2:0]hier_bram_2_M00_AXI_AWSIZE;
wire hier_bram_2_M00_AXI_AWVALID;
wire hier_bram_2_M00_AXI_BREADY;
wire [1:0]hier_bram_2_M00_AXI_BRESP;
wire hier_bram_2_M00_AXI_BVALID;
wire [63:0]hier_bram_2_M00_AXI_RDATA;
wire hier_bram_2_M00_AXI_RLAST;
wire hier_bram_2_M00_AXI_RREADY;
wire [1:0]hier_bram_2_M00_AXI_RRESP;
wire hier_bram_2_M00_AXI_RVALID;
wire [63:0]hier_bram_2_M00_AXI_WDATA;
wire hier_bram_2_M00_AXI_WLAST;
wire hier_bram_2_M00_AXI_WREADY;
wire [7:0]hier_bram_2_M00_AXI_WSTRB;
wire hier_bram_2_M00_AXI_WVALID;
wire [14:0]processing_system7_0_DDR_ADDR;
wire [2:0]processing_system7_0_DDR_BA;
wire processing_system7_0_DDR_CAS_N;
wire processing_system7_0_DDR_CKE;
wire processing_system7_0_DDR_CK_N;
wire processing_system7_0_DDR_CK_P;
wire processing_system7_0_DDR_CS_N;
wire [3:0]processing_system7_0_DDR_DM;
wire [31:0]processing_system7_0_DDR_DQ;
wire [3:0]processing_system7_0_DDR_DQS_N;
wire [3:0]processing_system7_0_DDR_DQS_P;
wire processing_system7_0_DDR_ODT;
wire processing_system7_0_DDR_RAS_N;
wire processing_system7_0_DDR_RESET_N;
wire processing_system7_0_DDR_WE_N;
wire processing_system7_0_FCLK_CLK0;
wire processing_system7_0_FCLK_RESET0_N;
wire processing_system7_0_FIXED_IO_DDR_VRN;
wire processing_system7_0_FIXED_IO_DDR_VRP;
wire [53:0]processing_system7_0_FIXED_IO_MIO;
wire processing_system7_0_FIXED_IO_PS_CLK;
wire processing_system7_0_FIXED_IO_PS_PORB;
wire processing_system7_0_FIXED_IO_PS_SRSTB;
wire [31:0]processing_system7_0_M_AXI_GP0_ARADDR;
wire [1:0]processing_system7_0_M_AXI_GP0_ARBURST;
wire [3:0]processing_system7_0_M_AXI_GP0_ARCACHE;
wire [11:0]processing_system7_0_M_AXI_GP0_ARID;
wire [3:0]processing_system7_0_M_AXI_GP0_ARLEN;
wire [1:0]processing_system7_0_M_AXI_GP0_ARLOCK;
wire [2:0]processing_system7_0_M_AXI_GP0_ARPROT;
wire [3:0]processing_system7_0_M_AXI_GP0_ARQOS;
wire processing_system7_0_M_AXI_GP0_ARREADY;
wire [2:0]processing_system7_0_M_AXI_GP0_ARSIZE;
wire processing_system7_0_M_AXI_GP0_ARVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_AWADDR;
wire [1:0]processing_system7_0_M_AXI_GP0_AWBURST;
wire [3:0]processing_system7_0_M_AXI_GP0_AWCACHE;
wire [11:0]processing_system7_0_M_AXI_GP0_AWID;
wire [3:0]processing_system7_0_M_AXI_GP0_AWLEN;
wire [1:0]processing_system7_0_M_AXI_GP0_AWLOCK;
wire [2:0]processing_system7_0_M_AXI_GP0_AWPROT;
wire [3:0]processing_system7_0_M_AXI_GP0_AWQOS;
wire processing_system7_0_M_AXI_GP0_AWREADY;
wire [2:0]processing_system7_0_M_AXI_GP0_AWSIZE;
wire processing_system7_0_M_AXI_GP0_AWVALID;
wire [11:0]processing_system7_0_M_AXI_GP0_BID;
wire processing_system7_0_M_AXI_GP0_BREADY;
wire [1:0]processing_system7_0_M_AXI_GP0_BRESP;
wire processing_system7_0_M_AXI_GP0_BVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_RDATA;
wire [11:0]processing_system7_0_M_AXI_GP0_RID;
wire processing_system7_0_M_AXI_GP0_RLAST;
wire processing_system7_0_M_AXI_GP0_RREADY;
wire [1:0]processing_system7_0_M_AXI_GP0_RRESP;
wire processing_system7_0_M_AXI_GP0_RVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_WDATA;
wire [11:0]processing_system7_0_M_AXI_GP0_WID;
wire processing_system7_0_M_AXI_GP0_WLAST;
wire processing_system7_0_M_AXI_GP0_WREADY;
wire [3:0]processing_system7_0_M_AXI_GP0_WSTRB;
wire processing_system7_0_M_AXI_GP0_WVALID;
wire [31:0]processing_system7_0_axi_periph_M00_AXI_ARADDR;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_ARREADY;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_ARVALID;
wire [31:0]processing_system7_0_axi_periph_M00_AXI_AWADDR;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_AWREADY;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_AWVALID;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_BREADY;
wire [1:0]processing_system7_0_axi_periph_M00_AXI_BRESP;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_BVALID;
wire [31:0]processing_system7_0_axi_periph_M00_AXI_RDATA;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_RREADY;
wire [1:0]processing_system7_0_axi_periph_M00_AXI_RRESP;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_RVALID;
wire [31:0]processing_system7_0_axi_periph_M00_AXI_WDATA;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_WREADY;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_WVALID;
wire [31:0]processing_system7_0_axi_periph_M01_AXI_ARADDR;
wire processing_system7_0_axi_periph_M01_AXI_ARREADY;
wire processing_system7_0_axi_periph_M01_AXI_ARVALID;
wire [31:0]processing_system7_0_axi_periph_M01_AXI_AWADDR;
wire processing_system7_0_axi_periph_M01_AXI_AWREADY;
wire processing_system7_0_axi_periph_M01_AXI_AWVALID;
wire processing_system7_0_axi_periph_M01_AXI_BREADY;
wire [1:0]processing_system7_0_axi_periph_M01_AXI_BRESP;
wire processing_system7_0_axi_periph_M01_AXI_BVALID;
wire [31:0]processing_system7_0_axi_periph_M01_AXI_RDATA;
wire processing_system7_0_axi_periph_M01_AXI_RREADY;
wire [1:0]processing_system7_0_axi_periph_M01_AXI_RRESP;
wire processing_system7_0_axi_periph_M01_AXI_RVALID;
wire [31:0]processing_system7_0_axi_periph_M01_AXI_WDATA;
wire processing_system7_0_axi_periph_M01_AXI_WREADY;
wire [3:0]processing_system7_0_axi_periph_M01_AXI_WSTRB;
wire processing_system7_0_axi_periph_M01_AXI_WVALID;
wire [31:0]processing_system7_0_axi_periph_M02_AXI_ARADDR;
wire [0:0]processing_system7_0_axi_periph_M02_AXI_ARREADY;
wire [0:0]processing_system7_0_axi_periph_M02_AXI_ARVALID;
wire [31:0]processing_system7_0_axi_periph_M02_AXI_AWADDR;
wire [0:0]processing_system7_0_axi_periph_M02_AXI_AWREADY;
wire [0:0]processing_system7_0_axi_periph_M02_AXI_AWVALID;
wire [0:0]processing_system7_0_axi_periph_M02_AXI_BREADY;
wire [1:0]processing_system7_0_axi_periph_M02_AXI_BRESP;
wire [0:0]processing_system7_0_axi_periph_M02_AXI_BVALID;
wire [31:0]processing_system7_0_axi_periph_M02_AXI_RDATA;
wire [0:0]processing_system7_0_axi_periph_M02_AXI_RREADY;
wire [1:0]processing_system7_0_axi_periph_M02_AXI_RRESP;
wire [0:0]processing_system7_0_axi_periph_M02_AXI_RVALID;
wire [31:0]processing_system7_0_axi_periph_M02_AXI_WDATA;
wire [0:0]processing_system7_0_axi_periph_M02_AXI_WREADY;
wire [0:0]processing_system7_0_axi_periph_M02_AXI_WVALID;
wire [31:0]processing_system7_0_axi_periph_M03_AXI_ARADDR;
wire [0:0]processing_system7_0_axi_periph_M03_AXI_ARREADY;
wire [0:0]processing_system7_0_axi_periph_M03_AXI_ARVALID;
wire [31:0]processing_system7_0_axi_periph_M03_AXI_AWADDR;
wire [0:0]processing_system7_0_axi_periph_M03_AXI_AWREADY;
wire [0:0]processing_system7_0_axi_periph_M03_AXI_AWVALID;
wire [0:0]processing_system7_0_axi_periph_M03_AXI_BREADY;
wire [1:0]processing_system7_0_axi_periph_M03_AXI_BRESP;
wire [0:0]processing_system7_0_axi_periph_M03_AXI_BVALID;
wire [31:0]processing_system7_0_axi_periph_M03_AXI_RDATA;
wire [0:0]processing_system7_0_axi_periph_M03_AXI_RREADY;
wire [1:0]processing_system7_0_axi_periph_M03_AXI_RRESP;
wire [0:0]processing_system7_0_axi_periph_M03_AXI_RVALID;
wire [31:0]processing_system7_0_axi_periph_M03_AXI_WDATA;
wire [0:0]processing_system7_0_axi_periph_M03_AXI_WREADY;
wire [0:0]processing_system7_0_axi_periph_M03_AXI_WVALID;
wire [0:0]rst_processing_system7_0_100M_interconnect_aresetn;
wire [0:0]rst_processing_system7_0_100M_peripheral_aresetn;
design_1_convolve_kernel_0_1 convolve_kernel_0
(.ap_clk(processing_system7_0_FCLK_CLK0),
.ap_rst_n(rst_processing_system7_0_100M_interconnect_aresetn),
.bufi_Addr_A(convolve_kernel_0_bufi_PORTA_ADDR),
.bufi_Clk_A(convolve_kernel_0_bufi_PORTA_CLK),
.bufi_Din_A(convolve_kernel_0_bufi_PORTA_DIN),
.bufi_Dout_A(convolve_kernel_0_bufi_PORTA_DOUT),
.bufi_EN_A(convolve_kernel_0_bufi_PORTA_EN),
.bufi_Rst_A(convolve_kernel_0_bufi_PORTA_RST),
.bufi_WEN_A(convolve_kernel_0_bufi_PORTA_WE),
.bufo_Addr_A(convolve_kernel_0_bufo_PORTA_ADDR),
.bufo_Clk_A(convolve_kernel_0_bufo_PORTA_CLK),
.bufo_Din_A(convolve_kernel_0_bufo_PORTA_DIN),
.bufo_Dout_A(convolve_kernel_0_bufo_PORTA_DOUT),
.bufo_EN_A(convolve_kernel_0_bufo_PORTA_EN),
.bufo_Rst_A(convolve_kernel_0_bufo_PORTA_RST),
.bufo_WEN_A(convolve_kernel_0_bufo_PORTA_WE),
.bufw_Addr_A(convolve_kernel_0_bufw_PORTA_ADDR),
.bufw_Clk_A(convolve_kernel_0_bufw_PORTA_CLK),
.bufw_Din_A(convolve_kernel_0_bufw_PORTA_DIN),
.bufw_Dout_A(convolve_kernel_0_bufw_PORTA_DOUT),
.bufw_EN_A(convolve_kernel_0_bufw_PORTA_EN),
.bufw_Rst_A(convolve_kernel_0_bufw_PORTA_RST),
.bufw_WEN_A(convolve_kernel_0_bufw_PORTA_WE),
.s_axi_control_ARADDR(processing_system7_0_axi_periph_M01_AXI_ARADDR[3:0]),
.s_axi_control_ARREADY(processing_system7_0_axi_periph_M01_AXI_ARREADY),
.s_axi_control_ARVALID(processing_system7_0_axi_periph_M01_AXI_ARVALID),
.s_axi_control_AWADDR(processing_system7_0_axi_periph_M01_AXI_AWADDR[3:0]),
.s_axi_control_AWREADY(processing_system7_0_axi_periph_M01_AXI_AWREADY),
.s_axi_control_AWVALID(processing_system7_0_axi_periph_M01_AXI_AWVALID),
.s_axi_control_BREADY(processing_system7_0_axi_periph_M01_AXI_BREADY),
.s_axi_control_BRESP(processing_system7_0_axi_periph_M01_AXI_BRESP),
.s_axi_control_BVALID(processing_system7_0_axi_periph_M01_AXI_BVALID),
.s_axi_control_RDATA(processing_system7_0_axi_periph_M01_AXI_RDATA),
.s_axi_control_RREADY(processing_system7_0_axi_periph_M01_AXI_RREADY),
.s_axi_control_RRESP(processing_system7_0_axi_periph_M01_AXI_RRESP),
.s_axi_control_RVALID(processing_system7_0_axi_periph_M01_AXI_RVALID),
.s_axi_control_WDATA(processing_system7_0_axi_periph_M01_AXI_WDATA),
.s_axi_control_WREADY(processing_system7_0_axi_periph_M01_AXI_WREADY),
.s_axi_control_WSTRB(processing_system7_0_axi_periph_M01_AXI_WSTRB),
.s_axi_control_WVALID(processing_system7_0_axi_periph_M01_AXI_WVALID));
hier_bram_0_imp_1VW8SCX hier_bram_0
(.ARESETN(rst_processing_system7_0_100M_interconnect_aresetn),
.BRAM_PORTB_addr(convolve_kernel_0_bufi_PORTA_ADDR),
.BRAM_PORTB_clk(convolve_kernel_0_bufi_PORTA_CLK),
.BRAM_PORTB_din(convolve_kernel_0_bufi_PORTA_DIN),
.BRAM_PORTB_dout(convolve_kernel_0_bufi_PORTA_DOUT),
.BRAM_PORTB_en(convolve_kernel_0_bufi_PORTA_EN),
.BRAM_PORTB_rst(convolve_kernel_0_bufi_PORTA_RST),
.BRAM_PORTB_we(convolve_kernel_0_bufi_PORTA_WE),
.M00_AXI_araddr(axi_mem_intercon_M00_AXI_ARADDR),
.M00_AXI_arburst(axi_mem_intercon_M00_AXI_ARBURST),
.M00_AXI_arcache(axi_mem_intercon_M00_AXI_ARCACHE),
.M00_AXI_arlen(axi_mem_intercon_M00_AXI_ARLEN),
.M00_AXI_arlock(axi_mem_intercon_M00_AXI_ARLOCK),
.M00_AXI_arprot(axi_mem_intercon_M00_AXI_ARPROT),
.M00_AXI_arqos(axi_mem_intercon_M00_AXI_ARQOS),
.M00_AXI_arready(axi_mem_intercon_M00_AXI_ARREADY),
.M00_AXI_arsize(axi_mem_intercon_M00_AXI_ARSIZE),
.M00_AXI_arvalid(axi_mem_intercon_M00_AXI_ARVALID),
.M00_AXI_awaddr(axi_mem_intercon_M00_AXI_AWADDR),
.M00_AXI_awburst(axi_mem_intercon_M00_AXI_AWBURST),
.M00_AXI_awcache(axi_mem_intercon_M00_AXI_AWCACHE),
.M00_AXI_awlen(axi_mem_intercon_M00_AXI_AWLEN),
.M00_AXI_awlock(axi_mem_intercon_M00_AXI_AWLOCK),
.M00_AXI_awprot(axi_mem_intercon_M00_AXI_AWPROT),
.M00_AXI_awqos(axi_mem_intercon_M00_AXI_AWQOS),
.M00_AXI_awready(axi_mem_intercon_M00_AXI_AWREADY),
.M00_AXI_awsize(axi_mem_intercon_M00_AXI_AWSIZE),
.M00_AXI_awvalid(axi_mem_intercon_M00_AXI_AWVALID),
.M00_AXI_bready(axi_mem_intercon_M00_AXI_BREADY),
.M00_AXI_bresp(axi_mem_intercon_M00_AXI_BRESP),
.M00_AXI_bvalid(axi_mem_intercon_M00_AXI_BVALID),
.M00_AXI_rdata(axi_mem_intercon_M00_AXI_RDATA),
.M00_AXI_rlast(axi_mem_intercon_M00_AXI_RLAST),
.M00_AXI_rready(axi_mem_intercon_M00_AXI_RREADY),
.M00_AXI_rresp(axi_mem_intercon_M00_AXI_RRESP),
.M00_AXI_rvalid(axi_mem_intercon_M00_AXI_RVALID),
.M00_AXI_wdata(axi_mem_intercon_M00_AXI_WDATA),
.M00_AXI_wlast(axi_mem_intercon_M00_AXI_WLAST),
.M00_AXI_wready(axi_mem_intercon_M00_AXI_WREADY),
.M00_AXI_wstrb(axi_mem_intercon_M00_AXI_WSTRB),
.M00_AXI_wvalid(axi_mem_intercon_M00_AXI_WVALID),
.S_AXI_LITE_araddr(processing_system7_0_axi_periph_M00_AXI_ARADDR),
.S_AXI_LITE_arready(processing_system7_0_axi_periph_M00_AXI_ARREADY),
.S_AXI_LITE_arvalid(processing_system7_0_axi_periph_M00_AXI_ARVALID),
.S_AXI_LITE_awaddr(processing_system7_0_axi_periph_M00_AXI_AWADDR),
.S_AXI_LITE_awready(processing_system7_0_axi_periph_M00_AXI_AWREADY),
.S_AXI_LITE_awvalid(processing_system7_0_axi_periph_M00_AXI_AWVALID),
.S_AXI_LITE_bready(processing_system7_0_axi_periph_M00_AXI_BREADY),
.S_AXI_LITE_bresp(processing_system7_0_axi_periph_M00_AXI_BRESP),
.S_AXI_LITE_bvalid(processing_system7_0_axi_periph_M00_AXI_BVALID),
.S_AXI_LITE_rdata(processing_system7_0_axi_periph_M00_AXI_RDATA),
.S_AXI_LITE_rready(processing_system7_0_axi_periph_M00_AXI_RREADY),
.S_AXI_LITE_rresp(processing_system7_0_axi_periph_M00_AXI_RRESP),
.S_AXI_LITE_rvalid(processing_system7_0_axi_periph_M00_AXI_RVALID),
.S_AXI_LITE_wdata(processing_system7_0_axi_periph_M00_AXI_WDATA),
.S_AXI_LITE_wready(processing_system7_0_axi_periph_M00_AXI_WREADY),
.S_AXI_LITE_wvalid(processing_system7_0_axi_periph_M00_AXI_WVALID),
.s_axi_lite_aclk(processing_system7_0_FCLK_CLK0),
.s_axi_lite_aresetn(rst_processing_system7_0_100M_peripheral_aresetn));
hier_bram_1_imp_1R79976 hier_bram_1
(.ARESETN(rst_processing_system7_0_100M_interconnect_aresetn),
.BRAM_PORTB_addr(convolve_kernel_0_bufw_PORTA_ADDR),
.BRAM_PORTB_clk(convolve_kernel_0_bufw_PORTA_CLK),
.BRAM_PORTB_din(convolve_kernel_0_bufw_PORTA_DIN),
.BRAM_PORTB_dout(convolve_kernel_0_bufw_PORTA_DOUT),
.BRAM_PORTB_en(convolve_kernel_0_bufw_PORTA_EN),
.BRAM_PORTB_rst(convolve_kernel_0_bufw_PORTA_RST),
.BRAM_PORTB_we(convolve_kernel_0_bufw_PORTA_WE),
.M00_AXI_araddr(hier_bram_1_M00_AXI_ARADDR),
.M00_AXI_arburst(hier_bram_1_M00_AXI_ARBURST),
.M00_AXI_arcache(hier_bram_1_M00_AXI_ARCACHE),
.M00_AXI_arlen(hier_bram_1_M00_AXI_ARLEN),
.M00_AXI_arlock(hier_bram_1_M00_AXI_ARLOCK),
.M00_AXI_arprot(hier_bram_1_M00_AXI_ARPROT),
.M00_AXI_arqos(hier_bram_1_M00_AXI_ARQOS),
.M00_AXI_arready(hier_bram_1_M00_AXI_ARREADY),
.M00_AXI_arsize(hier_bram_1_M00_AXI_ARSIZE),
.M00_AXI_arvalid(hier_bram_1_M00_AXI_ARVALID),
.M00_AXI_awaddr(hier_bram_1_M00_AXI_AWADDR),
.M00_AXI_awburst(hier_bram_1_M00_AXI_AWBURST),
.M00_AXI_awcache(hier_bram_1_M00_AXI_AWCACHE),
.M00_AXI_awlen(hier_bram_1_M00_AXI_AWLEN),
.M00_AXI_awlock(hier_bram_1_M00_AXI_AWLOCK),
.M00_AXI_awprot(hier_bram_1_M00_AXI_AWPROT),
.M00_AXI_awqos(hier_bram_1_M00_AXI_AWQOS),
.M00_AXI_awready(hier_bram_1_M00_AXI_AWREADY),
.M00_AXI_awsize(hier_bram_1_M00_AXI_AWSIZE),
.M00_AXI_awvalid(hier_bram_1_M00_AXI_AWVALID),
.M00_AXI_bready(hier_bram_1_M00_AXI_BREADY),
.M00_AXI_bresp(hier_bram_1_M00_AXI_BRESP),
.M00_AXI_bvalid(hier_bram_1_M00_AXI_BVALID),
.M00_AXI_rdata(hier_bram_1_M00_AXI_RDATA),
.M00_AXI_rlast(hier_bram_1_M00_AXI_RLAST),
.M00_AXI_rready(hier_bram_1_M00_AXI_RREADY),
.M00_AXI_rresp(hier_bram_1_M00_AXI_RRESP),
.M00_AXI_rvalid(hier_bram_1_M00_AXI_RVALID),
.M00_AXI_wdata(hier_bram_1_M00_AXI_WDATA),
.M00_AXI_wlast(hier_bram_1_M00_AXI_WLAST),
.M00_AXI_wready(hier_bram_1_M00_AXI_WREADY),
.M00_AXI_wstrb(hier_bram_1_M00_AXI_WSTRB),
.M00_AXI_wvalid(hier_bram_1_M00_AXI_WVALID),
.S_AXI_LITE_araddr(processing_system7_0_axi_periph_M02_AXI_ARADDR),
.S_AXI_LITE_arready(processing_system7_0_axi_periph_M02_AXI_ARREADY),
.S_AXI_LITE_arvalid(processing_system7_0_axi_periph_M02_AXI_ARVALID),
.S_AXI_LITE_awaddr(processing_system7_0_axi_periph_M02_AXI_AWADDR),
.S_AXI_LITE_awready(processing_system7_0_axi_periph_M02_AXI_AWREADY),
.S_AXI_LITE_awvalid(processing_system7_0_axi_periph_M02_AXI_AWVALID),
.S_AXI_LITE_bready(processing_system7_0_axi_periph_M02_AXI_BREADY),
.S_AXI_LITE_bresp(processing_system7_0_axi_periph_M02_AXI_BRESP),
.S_AXI_LITE_bvalid(processing_system7_0_axi_periph_M02_AXI_BVALID),
.S_AXI_LITE_rdata(processing_system7_0_axi_periph_M02_AXI_RDATA),
.S_AXI_LITE_rready(processing_system7_0_axi_periph_M02_AXI_RREADY),
.S_AXI_LITE_rresp(processing_system7_0_axi_periph_M02_AXI_RRESP),
.S_AXI_LITE_rvalid(processing_system7_0_axi_periph_M02_AXI_RVALID),
.S_AXI_LITE_wdata(processing_system7_0_axi_periph_M02_AXI_WDATA),
.S_AXI_LITE_wready(processing_system7_0_axi_periph_M02_AXI_WREADY),
.S_AXI_LITE_wvalid(processing_system7_0_axi_periph_M02_AXI_WVALID),
.s_axi_lite_aclk(processing_system7_0_FCLK_CLK0),
.s_axi_lite_aresetn(rst_processing_system7_0_100M_peripheral_aresetn));
hier_bram_2_imp_1OK8YL3 hier_bram_2
(.ARESETN(rst_processing_system7_0_100M_interconnect_aresetn),
.BRAM_PORTB_addr(convolve_kernel_0_bufo_PORTA_ADDR),
.BRAM_PORTB_clk(convolve_kernel_0_bufo_PORTA_CLK),
.BRAM_PORTB_din(convolve_kernel_0_bufo_PORTA_DIN),
.BRAM_PORTB_dout(convolve_kernel_0_bufo_PORTA_DOUT),
.BRAM_PORTB_en(convolve_kernel_0_bufo_PORTA_EN),
.BRAM_PORTB_rst(convolve_kernel_0_bufo_PORTA_RST),
.BRAM_PORTB_we(convolve_kernel_0_bufo_PORTA_WE),
.M00_AXI_araddr(hier_bram_2_M00_AXI_ARADDR),
.M00_AXI_arburst(hier_bram_2_M00_AXI_ARBURST),
.M00_AXI_arcache(hier_bram_2_M00_AXI_ARCACHE),
.M00_AXI_arlen(hier_bram_2_M00_AXI_ARLEN),
.M00_AXI_arlock(hier_bram_2_M00_AXI_ARLOCK),
.M00_AXI_arprot(hier_bram_2_M00_AXI_ARPROT),
.M00_AXI_arqos(hier_bram_2_M00_AXI_ARQOS),
.M00_AXI_arready(hier_bram_2_M00_AXI_ARREADY),
.M00_AXI_arsize(hier_bram_2_M00_AXI_ARSIZE),
.M00_AXI_arvalid(hier_bram_2_M00_AXI_ARVALID),
.M00_AXI_awaddr(hier_bram_2_M00_AXI_AWADDR),
.M00_AXI_awburst(hier_bram_2_M00_AXI_AWBURST),
.M00_AXI_awcache(hier_bram_2_M00_AXI_AWCACHE),
.M00_AXI_awlen(hier_bram_2_M00_AXI_AWLEN),
.M00_AXI_awlock(hier_bram_2_M00_AXI_AWLOCK),
.M00_AXI_awprot(hier_bram_2_M00_AXI_AWPROT),
.M00_AXI_awqos(hier_bram_2_M00_AXI_AWQOS),
.M00_AXI_awready(hier_bram_2_M00_AXI_AWREADY),
.M00_AXI_awsize(hier_bram_2_M00_AXI_AWSIZE),
.M00_AXI_awvalid(hier_bram_2_M00_AXI_AWVALID),
.M00_AXI_bready(hier_bram_2_M00_AXI_BREADY),
.M00_AXI_bresp(hier_bram_2_M00_AXI_BRESP),
.M00_AXI_bvalid(hier_bram_2_M00_AXI_BVALID),
.M00_AXI_rdata(hier_bram_2_M00_AXI_RDATA),
.M00_AXI_rlast(hier_bram_2_M00_AXI_RLAST),
.M00_AXI_rready(hier_bram_2_M00_AXI_RREADY),
.M00_AXI_rresp(hier_bram_2_M00_AXI_RRESP),
.M00_AXI_rvalid(hier_bram_2_M00_AXI_RVALID),
.M00_AXI_wdata(hier_bram_2_M00_AXI_WDATA),
.M00_AXI_wlast(hier_bram_2_M00_AXI_WLAST),
.M00_AXI_wready(hier_bram_2_M00_AXI_WREADY),
.M00_AXI_wstrb(hier_bram_2_M00_AXI_WSTRB),
.M00_AXI_wvalid(hier_bram_2_M00_AXI_WVALID),
.S_AXI_LITE_araddr(processing_system7_0_axi_periph_M03_AXI_ARADDR),
.S_AXI_LITE_arready(processing_system7_0_axi_periph_M03_AXI_ARREADY),
.S_AXI_LITE_arvalid(processing_system7_0_axi_periph_M03_AXI_ARVALID),
.S_AXI_LITE_awaddr(processing_system7_0_axi_periph_M03_AXI_AWADDR),
.S_AXI_LITE_awready(processing_system7_0_axi_periph_M03_AXI_AWREADY),
.S_AXI_LITE_awvalid(processing_system7_0_axi_periph_M03_AXI_AWVALID),
.S_AXI_LITE_bready(processing_system7_0_axi_periph_M03_AXI_BREADY),
.S_AXI_LITE_bresp(processing_system7_0_axi_periph_M03_AXI_BRESP),
.S_AXI_LITE_bvalid(processing_system7_0_axi_periph_M03_AXI_BVALID),
.S_AXI_LITE_rdata(processing_system7_0_axi_periph_M03_AXI_RDATA),
.S_AXI_LITE_rready(processing_system7_0_axi_periph_M03_AXI_RREADY),
.S_AXI_LITE_rresp(processing_system7_0_axi_periph_M03_AXI_RRESP),
.S_AXI_LITE_rvalid(processing_system7_0_axi_periph_M03_AXI_RVALID),
.S_AXI_LITE_wdata(processing_system7_0_axi_periph_M03_AXI_WDATA),
.S_AXI_LITE_wready(processing_system7_0_axi_periph_M03_AXI_WREADY),
.S_AXI_LITE_wvalid(processing_system7_0_axi_periph_M03_AXI_WVALID),
.s_axi_lite_aclk(processing_system7_0_FCLK_CLK0),
.s_axi_lite_aresetn(rst_processing_system7_0_100M_peripheral_aresetn));
design_1_processing_system7_0_0 processing_system7_0
(.DDR_Addr(DDR_addr[14:0]),
.DDR_BankAddr(DDR_ba[2:0]),
.DDR_CAS_n(DDR_cas_n),
.DDR_CKE(DDR_cke),
.DDR_CS_n(DDR_cs_n),
.DDR_Clk(DDR_ck_p),
.DDR_Clk_n(DDR_ck_n),
.DDR_DM(DDR_dm[3:0]),
.DDR_DQ(DDR_dq[31:0]),
.DDR_DQS(DDR_dqs_p[3:0]),
.DDR_DQS_n(DDR_dqs_n[3:0]),
.DDR_DRSTB(DDR_reset_n),
.DDR_ODT(DDR_odt),
.DDR_RAS_n(DDR_ras_n),
.DDR_VRN(FIXED_IO_ddr_vrn),
.DDR_VRP(FIXED_IO_ddr_vrp),
.DDR_WEB(DDR_we_n),
.FCLK_CLK0(processing_system7_0_FCLK_CLK0),
.FCLK_RESET0_N(processing_system7_0_FCLK_RESET0_N),
.MIO(FIXED_IO_mio[53:0]),
.M_AXI_GP0_ACLK(processing_system7_0_FCLK_CLK0),
.M_AXI_GP0_ARADDR(processing_system7_0_M_AXI_GP0_ARADDR),
.M_AXI_GP0_ARBURST(processing_system7_0_M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARCACHE(processing_system7_0_M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARID(processing_system7_0_M_AXI_GP0_ARID),
.M_AXI_GP0_ARLEN(processing_system7_0_M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARLOCK(processing_system7_0_M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARPROT(processing_system7_0_M_AXI_GP0_ARPROT),
.M_AXI_GP0_ARQOS(processing_system7_0_M_AXI_GP0_ARQOS),
.M_AXI_GP0_ARREADY(processing_system7_0_M_AXI_GP0_ARREADY),
.M_AXI_GP0_ARSIZE(processing_system7_0_M_AXI_GP0_ARSIZE),
.M_AXI_GP0_ARVALID(processing_system7_0_M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWADDR(processing_system7_0_M_AXI_GP0_AWADDR),
.M_AXI_GP0_AWBURST(processing_system7_0_M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWCACHE(processing_system7_0_M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWID(processing_system7_0_M_AXI_GP0_AWID),
.M_AXI_GP0_AWLEN(processing_system7_0_M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWLOCK(processing_system7_0_M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWPROT(processing_system7_0_M_AXI_GP0_AWPROT),
.M_AXI_GP0_AWQOS(processing_system7_0_M_AXI_GP0_AWQOS),
.M_AXI_GP0_AWREADY(processing_system7_0_M_AXI_GP0_AWREADY),
.M_AXI_GP0_AWSIZE(processing_system7_0_M_AXI_GP0_AWSIZE),
.M_AXI_GP0_AWVALID(processing_system7_0_M_AXI_GP0_AWVALID),
.M_AXI_GP0_BID(processing_system7_0_M_AXI_GP0_BID),
.M_AXI_GP0_BREADY(processing_system7_0_M_AXI_GP0_BREADY),
.M_AXI_GP0_BRESP(processing_system7_0_M_AXI_GP0_BRESP),
.M_AXI_GP0_BVALID(processing_system7_0_M_AXI_GP0_BVALID),
.M_AXI_GP0_RDATA(processing_system7_0_M_AXI_GP0_RDATA),
.M_AXI_GP0_RID(processing_system7_0_M_AXI_GP0_RID),
.M_AXI_GP0_RLAST(processing_system7_0_M_AXI_GP0_RLAST),
.M_AXI_GP0_RREADY(processing_system7_0_M_AXI_GP0_RREADY),
.M_AXI_GP0_RRESP(processing_system7_0_M_AXI_GP0_RRESP),
.M_AXI_GP0_RVALID(processing_system7_0_M_AXI_GP0_RVALID),
.M_AXI_GP0_WDATA(processing_system7_0_M_AXI_GP0_WDATA),
.M_AXI_GP0_WID(processing_system7_0_M_AXI_GP0_WID),
.M_AXI_GP0_WLAST(processing_system7_0_M_AXI_GP0_WLAST),
.M_AXI_GP0_WREADY(processing_system7_0_M_AXI_GP0_WREADY),
.M_AXI_GP0_WSTRB(processing_system7_0_M_AXI_GP0_WSTRB),
.M_AXI_GP0_WVALID(processing_system7_0_M_AXI_GP0_WVALID),
.PS_CLK(FIXED_IO_ps_clk),
.PS_PORB(FIXED_IO_ps_porb),
.PS_SRSTB(FIXED_IO_ps_srstb),
.S_AXI_HP0_ACLK(processing_system7_0_FCLK_CLK0),
.S_AXI_HP0_ARADDR(axi_mem_intercon_M00_AXI_ARADDR),
.S_AXI_HP0_ARBURST(axi_mem_intercon_M00_AXI_ARBURST),
.S_AXI_HP0_ARCACHE(axi_mem_intercon_M00_AXI_ARCACHE),
.S_AXI_HP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLEN(axi_mem_intercon_M00_AXI_ARLEN),
.S_AXI_HP0_ARLOCK(axi_mem_intercon_M00_AXI_ARLOCK),
.S_AXI_HP0_ARPROT(axi_mem_intercon_M00_AXI_ARPROT),
.S_AXI_HP0_ARQOS(axi_mem_intercon_M00_AXI_ARQOS),
.S_AXI_HP0_ARREADY(axi_mem_intercon_M00_AXI_ARREADY),
.S_AXI_HP0_ARSIZE(axi_mem_intercon_M00_AXI_ARSIZE),
.S_AXI_HP0_ARVALID(axi_mem_intercon_M00_AXI_ARVALID),
.S_AXI_HP0_AWADDR(axi_mem_intercon_M00_AXI_AWADDR),
.S_AXI_HP0_AWBURST(axi_mem_intercon_M00_AXI_AWBURST),
.S_AXI_HP0_AWCACHE(axi_mem_intercon_M00_AXI_AWCACHE),
.S_AXI_HP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLEN(axi_mem_intercon_M00_AXI_AWLEN),
.S_AXI_HP0_AWLOCK(axi_mem_intercon_M00_AXI_AWLOCK),
.S_AXI_HP0_AWPROT(axi_mem_intercon_M00_AXI_AWPROT),
.S_AXI_HP0_AWQOS(axi_mem_intercon_M00_AXI_AWQOS),
.S_AXI_HP0_AWREADY(axi_mem_intercon_M00_AXI_AWREADY),
.S_AXI_HP0_AWSIZE(axi_mem_intercon_M00_AXI_AWSIZE),
.S_AXI_HP0_AWVALID(axi_mem_intercon_M00_AXI_AWVALID),
.S_AXI_HP0_BREADY(axi_mem_intercon_M00_AXI_BREADY),
.S_AXI_HP0_BRESP(axi_mem_intercon_M00_AXI_BRESP),
.S_AXI_HP0_BVALID(axi_mem_intercon_M00_AXI_BVALID),
.S_AXI_HP0_RDATA(axi_mem_intercon_M00_AXI_RDATA),
.S_AXI_HP0_RDISSUECAP1_EN(1'b0),
.S_AXI_HP0_RLAST(axi_mem_intercon_M00_AXI_RLAST),
.S_AXI_HP0_RREADY(axi_mem_intercon_M00_AXI_RREADY),
.S_AXI_HP0_RRESP(axi_mem_intercon_M00_AXI_RRESP),
.S_AXI_HP0_RVALID(axi_mem_intercon_M00_AXI_RVALID),
.S_AXI_HP0_WDATA(axi_mem_intercon_M00_AXI_WDATA),
.S_AXI_HP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WLAST(axi_mem_intercon_M00_AXI_WLAST),
.S_AXI_HP0_WREADY(axi_mem_intercon_M00_AXI_WREADY),
.S_AXI_HP0_WRISSUECAP1_EN(1'b0),
.S_AXI_HP0_WSTRB(axi_mem_intercon_M00_AXI_WSTRB),
.S_AXI_HP0_WVALID(axi_mem_intercon_M00_AXI_WVALID),
.S_AXI_HP1_ACLK(processing_system7_0_FCLK_CLK0),
.S_AXI_HP1_ARADDR(hier_bram_1_M00_AXI_ARADDR),
.S_AXI_HP1_ARBURST(hier_bram_1_M00_AXI_ARBURST),
.S_AXI_HP1_ARCACHE(hier_bram_1_M00_AXI_ARCACHE),
.S_AXI_HP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLEN(hier_bram_1_M00_AXI_ARLEN),
.S_AXI_HP1_ARLOCK(hier_bram_1_M00_AXI_ARLOCK),
.S_AXI_HP1_ARPROT(hier_bram_1_M00_AXI_ARPROT),
.S_AXI_HP1_ARQOS(hier_bram_1_M00_AXI_ARQOS),
.S_AXI_HP1_ARREADY(hier_bram_1_M00_AXI_ARREADY),
.S_AXI_HP1_ARSIZE(hier_bram_1_M00_AXI_ARSIZE),
.S_AXI_HP1_ARVALID(hier_bram_1_M00_AXI_ARVALID),
.S_AXI_HP1_AWADDR(hier_bram_1_M00_AXI_AWADDR),
.S_AXI_HP1_AWBURST(hier_bram_1_M00_AXI_AWBURST),
.S_AXI_HP1_AWCACHE(hier_bram_1_M00_AXI_AWCACHE),
.S_AXI_HP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLEN(hier_bram_1_M00_AXI_AWLEN),
.S_AXI_HP1_AWLOCK(hier_bram_1_M00_AXI_AWLOCK),
.S_AXI_HP1_AWPROT(hier_bram_1_M00_AXI_AWPROT),
.S_AXI_HP1_AWQOS(hier_bram_1_M00_AXI_AWQOS),
.S_AXI_HP1_AWREADY(hier_bram_1_M00_AXI_AWREADY),
.S_AXI_HP1_AWSIZE(hier_bram_1_M00_AXI_AWSIZE),
.S_AXI_HP1_AWVALID(hier_bram_1_M00_AXI_AWVALID),
.S_AXI_HP1_BREADY(hier_bram_1_M00_AXI_BREADY),
.S_AXI_HP1_BRESP(hier_bram_1_M00_AXI_BRESP),
.S_AXI_HP1_BVALID(hier_bram_1_M00_AXI_BVALID),
.S_AXI_HP1_RDATA(hier_bram_1_M00_AXI_RDATA),
.S_AXI_HP1_RDISSUECAP1_EN(1'b0),
.S_AXI_HP1_RLAST(hier_bram_1_M00_AXI_RLAST),
.S_AXI_HP1_RREADY(hier_bram_1_M00_AXI_RREADY),
.S_AXI_HP1_RRESP(hier_bram_1_M00_AXI_RRESP),
.S_AXI_HP1_RVALID(hier_bram_1_M00_AXI_RVALID),
.S_AXI_HP1_WDATA(hier_bram_1_M00_AXI_WDATA),
.S_AXI_HP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WLAST(hier_bram_1_M00_AXI_WLAST),
.S_AXI_HP1_WREADY(hier_bram_1_M00_AXI_WREADY),
.S_AXI_HP1_WRISSUECAP1_EN(1'b0),
.S_AXI_HP1_WSTRB(hier_bram_1_M00_AXI_WSTRB),
.S_AXI_HP1_WVALID(hier_bram_1_M00_AXI_WVALID),
.S_AXI_HP2_ACLK(processing_system7_0_FCLK_CLK0),
.S_AXI_HP2_ARADDR(hier_bram_2_M00_AXI_ARADDR),
.S_AXI_HP2_ARBURST(hier_bram_2_M00_AXI_ARBURST),
.S_AXI_HP2_ARCACHE(hier_bram_2_M00_AXI_ARCACHE),
.S_AXI_HP2_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLEN(hier_bram_2_M00_AXI_ARLEN),
.S_AXI_HP2_ARLOCK(hier_bram_2_M00_AXI_ARLOCK),
.S_AXI_HP2_ARPROT(hier_bram_2_M00_AXI_ARPROT),
.S_AXI_HP2_ARQOS(hier_bram_2_M00_AXI_ARQOS),
.S_AXI_HP2_ARREADY(hier_bram_2_M00_AXI_ARREADY),
.S_AXI_HP2_ARSIZE(hier_bram_2_M00_AXI_ARSIZE),
.S_AXI_HP2_ARVALID(hier_bram_2_M00_AXI_ARVALID),
.S_AXI_HP2_AWADDR(hier_bram_2_M00_AXI_AWADDR),
.S_AXI_HP2_AWBURST(hier_bram_2_M00_AXI_AWBURST),
.S_AXI_HP2_AWCACHE(hier_bram_2_M00_AXI_AWCACHE),
.S_AXI_HP2_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLEN(hier_bram_2_M00_AXI_AWLEN),
.S_AXI_HP2_AWLOCK(hier_bram_2_M00_AXI_AWLOCK),
.S_AXI_HP2_AWPROT(hier_bram_2_M00_AXI_AWPROT),
.S_AXI_HP2_AWQOS(hier_bram_2_M00_AXI_AWQOS),
.S_AXI_HP2_AWREADY(hier_bram_2_M00_AXI_AWREADY),
.S_AXI_HP2_AWSIZE(hier_bram_2_M00_AXI_AWSIZE),
.S_AXI_HP2_AWVALID(hier_bram_2_M00_AXI_AWVALID),
.S_AXI_HP2_BREADY(hier_bram_2_M00_AXI_BREADY),
.S_AXI_HP2_BRESP(hier_bram_2_M00_AXI_BRESP),
.S_AXI_HP2_BVALID(hier_bram_2_M00_AXI_BVALID),
.S_AXI_HP2_RDATA(hier_bram_2_M00_AXI_RDATA),
.S_AXI_HP2_RDISSUECAP1_EN(1'b0),
.S_AXI_HP2_RLAST(hier_bram_2_M00_AXI_RLAST),
.S_AXI_HP2_RREADY(hier_bram_2_M00_AXI_RREADY),
.S_AXI_HP2_RRESP(hier_bram_2_M00_AXI_RRESP),
.S_AXI_HP2_RVALID(hier_bram_2_M00_AXI_RVALID),
.S_AXI_HP2_WDATA(hier_bram_2_M00_AXI_WDATA),
.S_AXI_HP2_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WLAST(hier_bram_2_M00_AXI_WLAST),
.S_AXI_HP2_WREADY(hier_bram_2_M00_AXI_WREADY),
.S_AXI_HP2_WRISSUECAP1_EN(1'b0),
.S_AXI_HP2_WSTRB(hier_bram_2_M00_AXI_WSTRB),
.S_AXI_HP2_WVALID(hier_bram_2_M00_AXI_WVALID),
.USB0_VBUS_PWRFAULT(1'b0));
design_1_processing_system7_0_axi_periph_0 processing_system7_0_axi_periph
(.ACLK(processing_system7_0_FCLK_CLK0),
.ARESETN(rst_processing_system7_0_100M_interconnect_aresetn),
.M00_ACLK(processing_system7_0_FCLK_CLK0),
.M00_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.M00_AXI_araddr(processing_system7_0_axi_periph_M00_AXI_ARADDR),
.M00_AXI_arready(processing_system7_0_axi_periph_M00_AXI_ARREADY),
.M00_AXI_arvalid(processing_system7_0_axi_periph_M00_AXI_ARVALID),
.M00_AXI_awaddr(processing_system7_0_axi_periph_M00_AXI_AWADDR),
.M00_AXI_awready(processing_system7_0_axi_periph_M00_AXI_AWREADY),
.M00_AXI_awvalid(processing_system7_0_axi_periph_M00_AXI_AWVALID),
.M00_AXI_bready(processing_system7_0_axi_periph_M00_AXI_BREADY),
.M00_AXI_bresp(processing_system7_0_axi_periph_M00_AXI_BRESP),
.M00_AXI_bvalid(processing_system7_0_axi_periph_M00_AXI_BVALID),
.M00_AXI_rdata(processing_system7_0_axi_periph_M00_AXI_RDATA),
.M00_AXI_rready(processing_system7_0_axi_periph_M00_AXI_RREADY),
.M00_AXI_rresp(processing_system7_0_axi_periph_M00_AXI_RRESP),
.M00_AXI_rvalid(processing_system7_0_axi_periph_M00_AXI_RVALID),
.M00_AXI_wdata(processing_system7_0_axi_periph_M00_AXI_WDATA),
.M00_AXI_wready(processing_system7_0_axi_periph_M00_AXI_WREADY),
.M00_AXI_wvalid(processing_system7_0_axi_periph_M00_AXI_WVALID),
.M01_ACLK(processing_system7_0_FCLK_CLK0),
.M01_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.M01_AXI_araddr(processing_system7_0_axi_periph_M01_AXI_ARADDR),
.M01_AXI_arready(processing_system7_0_axi_periph_M01_AXI_ARREADY),
.M01_AXI_arvalid(processing_system7_0_axi_periph_M01_AXI_ARVALID),
.M01_AXI_awaddr(processing_system7_0_axi_periph_M01_AXI_AWADDR),
.M01_AXI_awready(processing_system7_0_axi_periph_M01_AXI_AWREADY),
.M01_AXI_awvalid(processing_system7_0_axi_periph_M01_AXI_AWVALID),
.M01_AXI_bready(processing_system7_0_axi_periph_M01_AXI_BREADY),
.M01_AXI_bresp(processing_system7_0_axi_periph_M01_AXI_BRESP),
.M01_AXI_bvalid(processing_system7_0_axi_periph_M01_AXI_BVALID),
.M01_AXI_rdata(processing_system7_0_axi_periph_M01_AXI_RDATA),
.M01_AXI_rready(processing_system7_0_axi_periph_M01_AXI_RREADY),
.M01_AXI_rresp(processing_system7_0_axi_periph_M01_AXI_RRESP),
.M01_AXI_rvalid(processing_system7_0_axi_periph_M01_AXI_RVALID),
.M01_AXI_wdata(processing_system7_0_axi_periph_M01_AXI_WDATA),
.M01_AXI_wready(processing_system7_0_axi_periph_M01_AXI_WREADY),
.M01_AXI_wstrb(processing_system7_0_axi_periph_M01_AXI_WSTRB),
.M01_AXI_wvalid(processing_system7_0_axi_periph_M01_AXI_WVALID),
.M02_ACLK(processing_system7_0_FCLK_CLK0),
.M02_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.M02_AXI_araddr(processing_system7_0_axi_periph_M02_AXI_ARADDR),
.M02_AXI_arready(processing_system7_0_axi_periph_M02_AXI_ARREADY),
.M02_AXI_arvalid(processing_system7_0_axi_periph_M02_AXI_ARVALID),
.M02_AXI_awaddr(processing_system7_0_axi_periph_M02_AXI_AWADDR),
.M02_AXI_awready(processing_system7_0_axi_periph_M02_AXI_AWREADY),
.M02_AXI_awvalid(processing_system7_0_axi_periph_M02_AXI_AWVALID),
.M02_AXI_bready(processing_system7_0_axi_periph_M02_AXI_BREADY),
.M02_AXI_bresp(processing_system7_0_axi_periph_M02_AXI_BRESP),
.M02_AXI_bvalid(processing_system7_0_axi_periph_M02_AXI_BVALID),
.M02_AXI_rdata(processing_system7_0_axi_periph_M02_AXI_RDATA),
.M02_AXI_rready(processing_system7_0_axi_periph_M02_AXI_RREADY),
.M02_AXI_rresp(processing_system7_0_axi_periph_M02_AXI_RRESP),
.M02_AXI_rvalid(processing_system7_0_axi_periph_M02_AXI_RVALID),
.M02_AXI_wdata(processing_system7_0_axi_periph_M02_AXI_WDATA),
.M02_AXI_wready(processing_system7_0_axi_periph_M02_AXI_WREADY),
.M02_AXI_wvalid(processing_system7_0_axi_periph_M02_AXI_WVALID),
.M03_ACLK(processing_system7_0_FCLK_CLK0),
.M03_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.M03_AXI_araddr(processing_system7_0_axi_periph_M03_AXI_ARADDR),
.M03_AXI_arready(processing_system7_0_axi_periph_M03_AXI_ARREADY),
.M03_AXI_arvalid(processing_system7_0_axi_periph_M03_AXI_ARVALID),
.M03_AXI_awaddr(processing_system7_0_axi_periph_M03_AXI_AWADDR),
.M03_AXI_awready(processing_system7_0_axi_periph_M03_AXI_AWREADY),
.M03_AXI_awvalid(processing_system7_0_axi_periph_M03_AXI_AWVALID),
.M03_AXI_bready(processing_system7_0_axi_periph_M03_AXI_BREADY),
.M03_AXI_bresp(processing_system7_0_axi_periph_M03_AXI_BRESP),
.M03_AXI_bvalid(processing_system7_0_axi_periph_M03_AXI_BVALID),
.M03_AXI_rdata(processing_system7_0_axi_periph_M03_AXI_RDATA),
.M03_AXI_rready(processing_system7_0_axi_periph_M03_AXI_RREADY),
.M03_AXI_rresp(processing_system7_0_axi_periph_M03_AXI_RRESP),
.M03_AXI_rvalid(processing_system7_0_axi_periph_M03_AXI_RVALID),
.M03_AXI_wdata(processing_system7_0_axi_periph_M03_AXI_WDATA),
.M03_AXI_wready(processing_system7_0_axi_periph_M03_AXI_WREADY),
.M03_AXI_wvalid(processing_system7_0_axi_periph_M03_AXI_WVALID),
.S00_ACLK(processing_system7_0_FCLK_CLK0),
.S00_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.S00_AXI_araddr(processing_system7_0_M_AXI_GP0_ARADDR),
.S00_AXI_arburst(processing_system7_0_M_AXI_GP0_ARBURST),
.S00_AXI_arcache(processing_system7_0_M_AXI_GP0_ARCACHE),
.S00_AXI_arid(processing_system7_0_M_AXI_GP0_ARID),
.S00_AXI_arlen(processing_system7_0_M_AXI_GP0_ARLEN),
.S00_AXI_arlock(processing_system7_0_M_AXI_GP0_ARLOCK),
.S00_AXI_arprot(processing_system7_0_M_AXI_GP0_ARPROT),
.S00_AXI_arqos(processing_system7_0_M_AXI_GP0_ARQOS),
.S00_AXI_arready(processing_system7_0_M_AXI_GP0_ARREADY),
.S00_AXI_arsize(processing_system7_0_M_AXI_GP0_ARSIZE),
.S00_AXI_arvalid(processing_system7_0_M_AXI_GP0_ARVALID),
.S00_AXI_awaddr(processing_system7_0_M_AXI_GP0_AWADDR),
.S00_AXI_awburst(processing_system7_0_M_AXI_GP0_AWBURST),
.S00_AXI_awcache(processing_system7_0_M_AXI_GP0_AWCACHE),
.S00_AXI_awid(processing_system7_0_M_AXI_GP0_AWID),
.S00_AXI_awlen(processing_system7_0_M_AXI_GP0_AWLEN),
.S00_AXI_awlock(processing_system7_0_M_AXI_GP0_AWLOCK),
.S00_AXI_awprot(processing_system7_0_M_AXI_GP0_AWPROT),
.S00_AXI_awqos(processing_system7_0_M_AXI_GP0_AWQOS),
.S00_AXI_awready(processing_system7_0_M_AXI_GP0_AWREADY),
.S00_AXI_awsize(processing_system7_0_M_AXI_GP0_AWSIZE),
.S00_AXI_awvalid(processing_system7_0_M_AXI_GP0_AWVALID),
.S00_AXI_bid(processing_system7_0_M_AXI_GP0_BID),
.S00_AXI_bready(processing_system7_0_M_AXI_GP0_BREADY),
.S00_AXI_bresp(processing_system7_0_M_AXI_GP0_BRESP),
.S00_AXI_bvalid(processing_system7_0_M_AXI_GP0_BVALID),
.S00_AXI_rdata(processing_system7_0_M_AXI_GP0_RDATA),
.S00_AXI_rid(processing_system7_0_M_AXI_GP0_RID),
.S00_AXI_rlast(processing_system7_0_M_AXI_GP0_RLAST),
.S00_AXI_rready(processing_system7_0_M_AXI_GP0_RREADY),
.S00_AXI_rresp(processing_system7_0_M_AXI_GP0_RRESP),
.S00_AXI_rvalid(processing_system7_0_M_AXI_GP0_RVALID),
.S00_AXI_wdata(processing_system7_0_M_AXI_GP0_WDATA),
.S00_AXI_wid(processing_system7_0_M_AXI_GP0_WID),
.S00_AXI_wlast(processing_system7_0_M_AXI_GP0_WLAST),
.S00_AXI_wready(processing_system7_0_M_AXI_GP0_WREADY),
.S00_AXI_wstrb(processing_system7_0_M_AXI_GP0_WSTRB),
.S00_AXI_wvalid(processing_system7_0_M_AXI_GP0_WVALID));
design_1_rst_processing_system7_0_100M_0 rst_processing_system7_0_100M
(.aux_reset_in(1'b1),
.dcm_locked(1'b1),
.ext_reset_in(processing_system7_0_FCLK_RESET0_N),
.interconnect_aresetn(rst_processing_system7_0_100M_interconnect_aresetn),
.mb_debug_sys_rst(1'b0),
.peripheral_aresetn(rst_processing_system7_0_100M_peripheral_aresetn),
.slowest_sync_clk(processing_system7_0_FCLK_CLK0));
endmodule
module design_1_axi_mem_intercon_1
(ACLK,
ARESETN,
M00_ACLK,
M00_ARESETN,
M00_AXI_araddr,
M00_AXI_arburst,
M00_AXI_arcache,
M00_AXI_arlen,
M00_AXI_arlock,
M00_AXI_arprot,
M00_AXI_arqos,
M00_AXI_arready,
M00_AXI_arsize,
M00_AXI_arvalid,
M00_AXI_awaddr,
M00_AXI_awburst,
M00_AXI_awcache,
M00_AXI_awlen,
M00_AXI_awlock,
M00_AXI_awprot,
M00_AXI_awqos,
M00_AXI_awready,
M00_AXI_awsize,
M00_AXI_awvalid,
M00_AXI_bready,
M00_AXI_bresp,
M00_AXI_bvalid,
M00_AXI_rdata,
M00_AXI_rlast,
M00_AXI_rready,
M00_AXI_rresp,
M00_AXI_rvalid,
M00_AXI_wdata,
M00_AXI_wlast,
M00_AXI_wready,
M00_AXI_wstrb,
M00_AXI_wvalid,
M01_ACLK,
M01_ARESETN,
M01_AXI_araddr,
M01_AXI_arburst,
M01_AXI_arcache,
M01_AXI_arlen,
M01_AXI_arlock,
M01_AXI_arprot,
M01_AXI_arready,
M01_AXI_arsize,
M01_AXI_arvalid,
M01_AXI_awaddr,
M01_AXI_awburst,
M01_AXI_awcache,
M01_AXI_awlen,
M01_AXI_awlock,
M01_AXI_awprot,
M01_AXI_awready,
M01_AXI_awsize,
M01_AXI_awvalid,
M01_AXI_bready,
M01_AXI_bresp,
M01_AXI_bvalid,
M01_AXI_rdata,
M01_AXI_rlast,
M01_AXI_rready,
M01_AXI_rresp,
M01_AXI_rvalid,
M01_AXI_wdata,
M01_AXI_wlast,
M01_AXI_wready,
M01_AXI_wstrb,
M01_AXI_wvalid,
S00_ACLK,
S00_ARESETN,
S00_AXI_araddr,
S00_AXI_arburst,
S00_AXI_arcache,
S00_AXI_arlen,
S00_AXI_arprot,
S00_AXI_arready,
S00_AXI_arsize,
S00_AXI_arvalid,
S00_AXI_awaddr,
S00_AXI_awburst,
S00_AXI_awcache,
S00_AXI_awlen,
S00_AXI_awprot,
S00_AXI_awready,
S00_AXI_awsize,
S00_AXI_awvalid,
S00_AXI_bready,
S00_AXI_bresp,
S00_AXI_bvalid,
S00_AXI_rdata,
S00_AXI_rlast,
S00_AXI_rready,
S00_AXI_rresp,
S00_AXI_rvalid,
S00_AXI_wdata,
S00_AXI_wlast,
S00_AXI_wready,
S00_AXI_wstrb,
S00_AXI_wvalid);
input ACLK;
input ARESETN;
input M00_ACLK;
input M00_ARESETN;
output [31:0]M00_AXI_araddr;
output [1:0]M00_AXI_arburst;
output [3:0]M00_AXI_arcache;
output [3:0]M00_AXI_arlen;
output [1:0]M00_AXI_arlock;
output [2:0]M00_AXI_arprot;
output [3:0]M00_AXI_arqos;
input M00_AXI_arready;
output [2:0]M00_AXI_arsize;
output M00_AXI_arvalid;
output [31:0]M00_AXI_awaddr;
output [1:0]M00_AXI_awburst;
output [3:0]M00_AXI_awcache;
output [3:0]M00_AXI_awlen;
output [1:0]M00_AXI_awlock;
output [2:0]M00_AXI_awprot;
output [3:0]M00_AXI_awqos;
input M00_AXI_awready;
output [2:0]M00_AXI_awsize;
output M00_AXI_awvalid;
output M00_AXI_bready;
input [1:0]M00_AXI_bresp;
input M00_AXI_bvalid;
input [63:0]M00_AXI_rdata;
input M00_AXI_rlast;
output M00_AXI_rready;
input [1:0]M00_AXI_rresp;
input M00_AXI_rvalid;
output [63:0]M00_AXI_wdata;
output M00_AXI_wlast;
input M00_AXI_wready;
output [7:0]M00_AXI_wstrb;
output M00_AXI_wvalid;
input M01_ACLK;
input M01_ARESETN;
output [12:0]M01_AXI_araddr;
output [1:0]M01_AXI_arburst;
output [3:0]M01_AXI_arcache;
output [7:0]M01_AXI_arlen;
output [0:0]M01_AXI_arlock;
output [2:0]M01_AXI_arprot;
input M01_AXI_arready;
output [2:0]M01_AXI_arsize;
output M01_AXI_arvalid;
output [12:0]M01_AXI_awaddr;
output [1:0]M01_AXI_awburst;
output [3:0]M01_AXI_awcache;
output [7:0]M01_AXI_awlen;
output [0:0]M01_AXI_awlock;
output [2:0]M01_AXI_awprot;
input M01_AXI_awready;
output [2:0]M01_AXI_awsize;
output M01_AXI_awvalid;
output M01_AXI_bready;
input [1:0]M01_AXI_bresp;
input M01_AXI_bvalid;
input [31:0]M01_AXI_rdata;
input M01_AXI_rlast;
output M01_AXI_rready;
input [1:0]M01_AXI_rresp;
input M01_AXI_rvalid;
output [31:0]M01_AXI_wdata;
output M01_AXI_wlast;
input M01_AXI_wready;
output [3:0]M01_AXI_wstrb;
output M01_AXI_wvalid;
input S00_ACLK;
input S00_ARESETN;
input [31:0]S00_AXI_araddr;
input [1:0]S00_AXI_arburst;
input [3:0]S00_AXI_arcache;
input [7:0]S00_AXI_arlen;
input [2:0]S00_AXI_arprot;
output S00_AXI_arready;
input [2:0]S00_AXI_arsize;
input S00_AXI_arvalid;
input [31:0]S00_AXI_awaddr;
input [1:0]S00_AXI_awburst;
input [3:0]S00_AXI_awcache;
input [7:0]S00_AXI_awlen;
input [2:0]S00_AXI_awprot;
output S00_AXI_awready;
input [2:0]S00_AXI_awsize;
input S00_AXI_awvalid;
input S00_AXI_bready;
output [1:0]S00_AXI_bresp;
output S00_AXI_bvalid;
output [31:0]S00_AXI_rdata;
output S00_AXI_rlast;
input S00_AXI_rready;
output [1:0]S00_AXI_rresp;
output S00_AXI_rvalid;
input [31:0]S00_AXI_wdata;
input S00_AXI_wlast;
output S00_AXI_wready;
input [3:0]S00_AXI_wstrb;
input S00_AXI_wvalid;
wire M00_ACLK_1;
wire M00_ARESETN_1;
wire M01_ACLK_1;
wire M01_ARESETN_1;
wire S00_ACLK_1;
wire S00_ARESETN_1;
wire axi_mem_intercon_ACLK_net;
wire axi_mem_intercon_ARESETN_net;
wire [31:0]axi_mem_intercon_to_s00_couplers_ARADDR;
wire [1:0]axi_mem_intercon_to_s00_couplers_ARBURST;
wire [3:0]axi_mem_intercon_to_s00_couplers_ARCACHE;
wire [7:0]axi_mem_intercon_to_s00_couplers_ARLEN;
wire [2:0]axi_mem_intercon_to_s00_couplers_ARPROT;
wire axi_mem_intercon_to_s00_couplers_ARREADY;
wire [2:0]axi_mem_intercon_to_s00_couplers_ARSIZE;
wire axi_mem_intercon_to_s00_couplers_ARVALID;
wire [31:0]axi_mem_intercon_to_s00_couplers_AWADDR;
wire [1:0]axi_mem_intercon_to_s00_couplers_AWBURST;
wire [3:0]axi_mem_intercon_to_s00_couplers_AWCACHE;
wire [7:0]axi_mem_intercon_to_s00_couplers_AWLEN;
wire [2:0]axi_mem_intercon_to_s00_couplers_AWPROT;
wire axi_mem_intercon_to_s00_couplers_AWREADY;
wire [2:0]axi_mem_intercon_to_s00_couplers_AWSIZE;
wire axi_mem_intercon_to_s00_couplers_AWVALID;
wire axi_mem_intercon_to_s00_couplers_BREADY;
wire [1:0]axi_mem_intercon_to_s00_couplers_BRESP;
wire axi_mem_intercon_to_s00_couplers_BVALID;
wire [31:0]axi_mem_intercon_to_s00_couplers_RDATA;
wire axi_mem_intercon_to_s00_couplers_RLAST;
wire axi_mem_intercon_to_s00_couplers_RREADY;
wire [1:0]axi_mem_intercon_to_s00_couplers_RRESP;
wire axi_mem_intercon_to_s00_couplers_RVALID;
wire [31:0]axi_mem_intercon_to_s00_couplers_WDATA;
wire axi_mem_intercon_to_s00_couplers_WLAST;
wire axi_mem_intercon_to_s00_couplers_WREADY;
wire [3:0]axi_mem_intercon_to_s00_couplers_WSTRB;
wire axi_mem_intercon_to_s00_couplers_WVALID;
wire [31:0]m00_couplers_to_axi_mem_intercon_ARADDR;
wire [1:0]m00_couplers_to_axi_mem_intercon_ARBURST;
wire [3:0]m00_couplers_to_axi_mem_intercon_ARCACHE;
wire [3:0]m00_couplers_to_axi_mem_intercon_ARLEN;
wire [1:0]m00_couplers_to_axi_mem_intercon_ARLOCK;
wire [2:0]m00_couplers_to_axi_mem_intercon_ARPROT;
wire [3:0]m00_couplers_to_axi_mem_intercon_ARQOS;
wire m00_couplers_to_axi_mem_intercon_ARREADY;
wire [2:0]m00_couplers_to_axi_mem_intercon_ARSIZE;
wire m00_couplers_to_axi_mem_intercon_ARVALID;
wire [31:0]m00_couplers_to_axi_mem_intercon_AWADDR;
wire [1:0]m00_couplers_to_axi_mem_intercon_AWBURST;
wire [3:0]m00_couplers_to_axi_mem_intercon_AWCACHE;
wire [3:0]m00_couplers_to_axi_mem_intercon_AWLEN;
wire [1:0]m00_couplers_to_axi_mem_intercon_AWLOCK;
wire [2:0]m00_couplers_to_axi_mem_intercon_AWPROT;
wire [3:0]m00_couplers_to_axi_mem_intercon_AWQOS;
wire m00_couplers_to_axi_mem_intercon_AWREADY;
wire [2:0]m00_couplers_to_axi_mem_intercon_AWSIZE;
wire m00_couplers_to_axi_mem_intercon_AWVALID;
wire m00_couplers_to_axi_mem_intercon_BREADY;
wire [1:0]m00_couplers_to_axi_mem_intercon_BRESP;
wire m00_couplers_to_axi_mem_intercon_BVALID;
wire [63:0]m00_couplers_to_axi_mem_intercon_RDATA;
wire m00_couplers_to_axi_mem_intercon_RLAST;
wire m00_couplers_to_axi_mem_intercon_RREADY;
wire [1:0]m00_couplers_to_axi_mem_intercon_RRESP;
wire m00_couplers_to_axi_mem_intercon_RVALID;
wire [63:0]m00_couplers_to_axi_mem_intercon_WDATA;
wire m00_couplers_to_axi_mem_intercon_WLAST;
wire m00_couplers_to_axi_mem_intercon_WREADY;
wire [7:0]m00_couplers_to_axi_mem_intercon_WSTRB;
wire m00_couplers_to_axi_mem_intercon_WVALID;
wire [12:0]m01_couplers_to_axi_mem_intercon_ARADDR;
wire [1:0]m01_couplers_to_axi_mem_intercon_ARBURST;
wire [3:0]m01_couplers_to_axi_mem_intercon_ARCACHE;
wire [7:0]m01_couplers_to_axi_mem_intercon_ARLEN;
wire [0:0]m01_couplers_to_axi_mem_intercon_ARLOCK;
wire [2:0]m01_couplers_to_axi_mem_intercon_ARPROT;
wire m01_couplers_to_axi_mem_intercon_ARREADY;
wire [2:0]m01_couplers_to_axi_mem_intercon_ARSIZE;
wire m01_couplers_to_axi_mem_intercon_ARVALID;
wire [12:0]m01_couplers_to_axi_mem_intercon_AWADDR;
wire [1:0]m01_couplers_to_axi_mem_intercon_AWBURST;
wire [3:0]m01_couplers_to_axi_mem_intercon_AWCACHE;
wire [7:0]m01_couplers_to_axi_mem_intercon_AWLEN;
wire [0:0]m01_couplers_to_axi_mem_intercon_AWLOCK;
wire [2:0]m01_couplers_to_axi_mem_intercon_AWPROT;
wire m01_couplers_to_axi_mem_intercon_AWREADY;
wire [2:0]m01_couplers_to_axi_mem_intercon_AWSIZE;
wire m01_couplers_to_axi_mem_intercon_AWVALID;
wire m01_couplers_to_axi_mem_intercon_BREADY;
wire [1:0]m01_couplers_to_axi_mem_intercon_BRESP;
wire m01_couplers_to_axi_mem_intercon_BVALID;
wire [31:0]m01_couplers_to_axi_mem_intercon_RDATA;
wire m01_couplers_to_axi_mem_intercon_RLAST;
wire m01_couplers_to_axi_mem_intercon_RREADY;
wire [1:0]m01_couplers_to_axi_mem_intercon_RRESP;
wire m01_couplers_to_axi_mem_intercon_RVALID;
wire [31:0]m01_couplers_to_axi_mem_intercon_WDATA;
wire m01_couplers_to_axi_mem_intercon_WLAST;
wire m01_couplers_to_axi_mem_intercon_WREADY;
wire [3:0]m01_couplers_to_axi_mem_intercon_WSTRB;
wire m01_couplers_to_axi_mem_intercon_WVALID;
wire [31:0]s00_couplers_to_xbar_ARADDR;
wire [1:0]s00_couplers_to_xbar_ARBURST;
wire [3:0]s00_couplers_to_xbar_ARCACHE;
wire [7:0]s00_couplers_to_xbar_ARLEN;
wire [0:0]s00_couplers_to_xbar_ARLOCK;
wire [2:0]s00_couplers_to_xbar_ARPROT;
wire [3:0]s00_couplers_to_xbar_ARQOS;
wire [0:0]s00_couplers_to_xbar_ARREADY;
wire [2:0]s00_couplers_to_xbar_ARSIZE;
wire s00_couplers_to_xbar_ARVALID;
wire [31:0]s00_couplers_to_xbar_AWADDR;
wire [1:0]s00_couplers_to_xbar_AWBURST;
wire [3:0]s00_couplers_to_xbar_AWCACHE;
wire [7:0]s00_couplers_to_xbar_AWLEN;
wire [0:0]s00_couplers_to_xbar_AWLOCK;
wire [2:0]s00_couplers_to_xbar_AWPROT;
wire [3:0]s00_couplers_to_xbar_AWQOS;
wire [0:0]s00_couplers_to_xbar_AWREADY;
wire [2:0]s00_couplers_to_xbar_AWSIZE;
wire s00_couplers_to_xbar_AWVALID;
wire s00_couplers_to_xbar_BREADY;
wire [1:0]s00_couplers_to_xbar_BRESP;
wire [0:0]s00_couplers_to_xbar_BVALID;
wire [63:0]s00_couplers_to_xbar_RDATA;
wire [0:0]s00_couplers_to_xbar_RLAST;
wire s00_couplers_to_xbar_RREADY;
wire [1:0]s00_couplers_to_xbar_RRESP;
wire [0:0]s00_couplers_to_xbar_RVALID;
wire [63:0]s00_couplers_to_xbar_WDATA;
wire s00_couplers_to_xbar_WLAST;
wire [0:0]s00_couplers_to_xbar_WREADY;
wire [7:0]s00_couplers_to_xbar_WSTRB;
wire s00_couplers_to_xbar_WVALID;
wire [31:0]xbar_to_m00_couplers_ARADDR;
wire [1:0]xbar_to_m00_couplers_ARBURST;
wire [3:0]xbar_to_m00_couplers_ARCACHE;
wire [7:0]xbar_to_m00_couplers_ARLEN;
wire [0:0]xbar_to_m00_couplers_ARLOCK;
wire [2:0]xbar_to_m00_couplers_ARPROT;
wire [3:0]xbar_to_m00_couplers_ARQOS;
wire xbar_to_m00_couplers_ARREADY;
wire [3:0]xbar_to_m00_couplers_ARREGION;
wire [2:0]xbar_to_m00_couplers_ARSIZE;
wire [0:0]xbar_to_m00_couplers_ARVALID;
wire [31:0]xbar_to_m00_couplers_AWADDR;
wire [1:0]xbar_to_m00_couplers_AWBURST;
wire [3:0]xbar_to_m00_couplers_AWCACHE;
wire [7:0]xbar_to_m00_couplers_AWLEN;
wire [0:0]xbar_to_m00_couplers_AWLOCK;
wire [2:0]xbar_to_m00_couplers_AWPROT;
wire [3:0]xbar_to_m00_couplers_AWQOS;
wire xbar_to_m00_couplers_AWREADY;
wire [3:0]xbar_to_m00_couplers_AWREGION;
wire [2:0]xbar_to_m00_couplers_AWSIZE;
wire [0:0]xbar_to_m00_couplers_AWVALID;
wire [0:0]xbar_to_m00_couplers_BREADY;
wire [1:0]xbar_to_m00_couplers_BRESP;
wire xbar_to_m00_couplers_BVALID;
wire [63:0]xbar_to_m00_couplers_RDATA;
wire xbar_to_m00_couplers_RLAST;
wire [0:0]xbar_to_m00_couplers_RREADY;
wire [1:0]xbar_to_m00_couplers_RRESP;
wire xbar_to_m00_couplers_RVALID;
wire [63:0]xbar_to_m00_couplers_WDATA;
wire [0:0]xbar_to_m00_couplers_WLAST;
wire xbar_to_m00_couplers_WREADY;
wire [7:0]xbar_to_m00_couplers_WSTRB;
wire [0:0]xbar_to_m00_couplers_WVALID;
wire [63:32]xbar_to_m01_couplers_ARADDR;
wire [3:2]xbar_to_m01_couplers_ARBURST;
wire [7:4]xbar_to_m01_couplers_ARCACHE;
wire [15:8]xbar_to_m01_couplers_ARLEN;
wire [1:1]xbar_to_m01_couplers_ARLOCK;
wire [5:3]xbar_to_m01_couplers_ARPROT;
wire [7:4]xbar_to_m01_couplers_ARQOS;
wire xbar_to_m01_couplers_ARREADY;
wire [7:4]xbar_to_m01_couplers_ARREGION;
wire [5:3]xbar_to_m01_couplers_ARSIZE;
wire [1:1]xbar_to_m01_couplers_ARVALID;
wire [63:32]xbar_to_m01_couplers_AWADDR;
wire [3:2]xbar_to_m01_couplers_AWBURST;
wire [7:4]xbar_to_m01_couplers_AWCACHE;
wire [15:8]xbar_to_m01_couplers_AWLEN;
wire [1:1]xbar_to_m01_couplers_AWLOCK;
wire [5:3]xbar_to_m01_couplers_AWPROT;
wire [7:4]xbar_to_m01_couplers_AWQOS;
wire xbar_to_m01_couplers_AWREADY;
wire [7:4]xbar_to_m01_couplers_AWREGION;
wire [5:3]xbar_to_m01_couplers_AWSIZE;
wire [1:1]xbar_to_m01_couplers_AWVALID;
wire [1:1]xbar_to_m01_couplers_BREADY;
wire [1:0]xbar_to_m01_couplers_BRESP;
wire xbar_to_m01_couplers_BVALID;
wire [63:0]xbar_to_m01_couplers_RDATA;
wire xbar_to_m01_couplers_RLAST;
wire [1:1]xbar_to_m01_couplers_RREADY;
wire [1:0]xbar_to_m01_couplers_RRESP;
wire xbar_to_m01_couplers_RVALID;
wire [127:64]xbar_to_m01_couplers_WDATA;
wire [1:1]xbar_to_m01_couplers_WLAST;
wire xbar_to_m01_couplers_WREADY;
wire [15:8]xbar_to_m01_couplers_WSTRB;
wire [1:1]xbar_to_m01_couplers_WVALID;
assign M00_ACLK_1 = M00_ACLK;
assign M00_ARESETN_1 = M00_ARESETN;
assign M00_AXI_araddr[31:0] = m00_couplers_to_axi_mem_intercon_ARADDR;
assign M00_AXI_arburst[1:0] = m00_couplers_to_axi_mem_intercon_ARBURST;
assign M00_AXI_arcache[3:0] = m00_couplers_to_axi_mem_intercon_ARCACHE;
assign M00_AXI_arlen[3:0] = m00_couplers_to_axi_mem_intercon_ARLEN;
assign M00_AXI_arlock[1:0] = m00_couplers_to_axi_mem_intercon_ARLOCK;
assign M00_AXI_arprot[2:0] = m00_couplers_to_axi_mem_intercon_ARPROT;
assign M00_AXI_arqos[3:0] = m00_couplers_to_axi_mem_intercon_ARQOS;
assign M00_AXI_arsize[2:0] = m00_couplers_to_axi_mem_intercon_ARSIZE;
assign M00_AXI_arvalid = m00_couplers_to_axi_mem_intercon_ARVALID;
assign M00_AXI_awaddr[31:0] = m00_couplers_to_axi_mem_intercon_AWADDR;
assign M00_AXI_awburst[1:0] = m00_couplers_to_axi_mem_intercon_AWBURST;
assign M00_AXI_awcache[3:0] = m00_couplers_to_axi_mem_intercon_AWCACHE;
assign M00_AXI_awlen[3:0] = m00_couplers_to_axi_mem_intercon_AWLEN;
assign M00_AXI_awlock[1:0] = m00_couplers_to_axi_mem_intercon_AWLOCK;
assign M00_AXI_awprot[2:0] = m00_couplers_to_axi_mem_intercon_AWPROT;
assign M00_AXI_awqos[3:0] = m00_couplers_to_axi_mem_intercon_AWQOS;
assign M00_AXI_awsize[2:0] = m00_couplers_to_axi_mem_intercon_AWSIZE;
assign M00_AXI_awvalid = m00_couplers_to_axi_mem_intercon_AWVALID;
assign M00_AXI_bready = m00_couplers_to_axi_mem_intercon_BREADY;
assign M00_AXI_rready = m00_couplers_to_axi_mem_intercon_RREADY;
assign M00_AXI_wdata[63:0] = m00_couplers_to_axi_mem_intercon_WDATA;
assign M00_AXI_wlast = m00_couplers_to_axi_mem_intercon_WLAST;
assign M00_AXI_wstrb[7:0] = m00_couplers_to_axi_mem_intercon_WSTRB;
assign M00_AXI_wvalid = m00_couplers_to_axi_mem_intercon_WVALID;
assign M01_ACLK_1 = M01_ACLK;
assign M01_ARESETN_1 = M01_ARESETN;
assign M01_AXI_araddr[12:0] = m01_couplers_to_axi_mem_intercon_ARADDR;
assign M01_AXI_arburst[1:0] = m01_couplers_to_axi_mem_intercon_ARBURST;
assign M01_AXI_arcache[3:0] = m01_couplers_to_axi_mem_intercon_ARCACHE;
assign M01_AXI_arlen[7:0] = m01_couplers_to_axi_mem_intercon_ARLEN;
assign M01_AXI_arlock[0] = m01_couplers_to_axi_mem_intercon_ARLOCK;
assign M01_AXI_arprot[2:0] = m01_couplers_to_axi_mem_intercon_ARPROT;
assign M01_AXI_arsize[2:0] = m01_couplers_to_axi_mem_intercon_ARSIZE;
assign M01_AXI_arvalid = m01_couplers_to_axi_mem_intercon_ARVALID;
assign M01_AXI_awaddr[12:0] = m01_couplers_to_axi_mem_intercon_AWADDR;
assign M01_AXI_awburst[1:0] = m01_couplers_to_axi_mem_intercon_AWBURST;
assign M01_AXI_awcache[3:0] = m01_couplers_to_axi_mem_intercon_AWCACHE;
assign M01_AXI_awlen[7:0] = m01_couplers_to_axi_mem_intercon_AWLEN;
assign M01_AXI_awlock[0] = m01_couplers_to_axi_mem_intercon_AWLOCK;
assign M01_AXI_awprot[2:0] = m01_couplers_to_axi_mem_intercon_AWPROT;
assign M01_AXI_awsize[2:0] = m01_couplers_to_axi_mem_intercon_AWSIZE;
assign M01_AXI_awvalid = m01_couplers_to_axi_mem_intercon_AWVALID;
assign M01_AXI_bready = m01_couplers_to_axi_mem_intercon_BREADY;
assign M01_AXI_rready = m01_couplers_to_axi_mem_intercon_RREADY;
assign M01_AXI_wdata[31:0] = m01_couplers_to_axi_mem_intercon_WDATA;
assign M01_AXI_wlast = m01_couplers_to_axi_mem_intercon_WLAST;
assign M01_AXI_wstrb[3:0] = m01_couplers_to_axi_mem_intercon_WSTRB;
assign M01_AXI_wvalid = m01_couplers_to_axi_mem_intercon_WVALID;
assign S00_ACLK_1 = S00_ACLK;
assign S00_ARESETN_1 = S00_ARESETN;
assign S00_AXI_arready = axi_mem_intercon_to_s00_couplers_ARREADY;
assign S00_AXI_awready = axi_mem_intercon_to_s00_couplers_AWREADY;
assign S00_AXI_bresp[1:0] = axi_mem_intercon_to_s00_couplers_BRESP;
assign S00_AXI_bvalid = axi_mem_intercon_to_s00_couplers_BVALID;
assign S00_AXI_rdata[31:0] = axi_mem_intercon_to_s00_couplers_RDATA;
assign S00_AXI_rlast = axi_mem_intercon_to_s00_couplers_RLAST;
assign S00_AXI_rresp[1:0] = axi_mem_intercon_to_s00_couplers_RRESP;
assign S00_AXI_rvalid = axi_mem_intercon_to_s00_couplers_RVALID;
assign S00_AXI_wready = axi_mem_intercon_to_s00_couplers_WREADY;
assign axi_mem_intercon_ACLK_net = ACLK;
assign axi_mem_intercon_ARESETN_net = ARESETN;
assign axi_mem_intercon_to_s00_couplers_ARADDR = S00_AXI_araddr[31:0];
assign axi_mem_intercon_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0];
assign axi_mem_intercon_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0];
assign axi_mem_intercon_to_s00_couplers_ARLEN = S00_AXI_arlen[7:0];
assign axi_mem_intercon_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0];
assign axi_mem_intercon_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0];
assign axi_mem_intercon_to_s00_couplers_ARVALID = S00_AXI_arvalid;
assign axi_mem_intercon_to_s00_couplers_AWADDR = S00_AXI_awaddr[31:0];
assign axi_mem_intercon_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0];
assign axi_mem_intercon_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0];
assign axi_mem_intercon_to_s00_couplers_AWLEN = S00_AXI_awlen[7:0];
assign axi_mem_intercon_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0];
assign axi_mem_intercon_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0];
assign axi_mem_intercon_to_s00_couplers_AWVALID = S00_AXI_awvalid;
assign axi_mem_intercon_to_s00_couplers_BREADY = S00_AXI_bready;
assign axi_mem_intercon_to_s00_couplers_RREADY = S00_AXI_rready;
assign axi_mem_intercon_to_s00_couplers_WDATA = S00_AXI_wdata[31:0];
assign axi_mem_intercon_to_s00_couplers_WLAST = S00_AXI_wlast;
assign axi_mem_intercon_to_s00_couplers_WSTRB = S00_AXI_wstrb[3:0];
assign axi_mem_intercon_to_s00_couplers_WVALID = S00_AXI_wvalid;
assign m00_couplers_to_axi_mem_intercon_ARREADY = M00_AXI_arready;
assign m00_couplers_to_axi_mem_intercon_AWREADY = M00_AXI_awready;
assign m00_couplers_to_axi_mem_intercon_BRESP = M00_AXI_bresp[1:0];
assign m00_couplers_to_axi_mem_intercon_BVALID = M00_AXI_bvalid;
assign m00_couplers_to_axi_mem_intercon_RDATA = M00_AXI_rdata[63:0];
assign m00_couplers_to_axi_mem_intercon_RLAST = M00_AXI_rlast;
assign m00_couplers_to_axi_mem_intercon_RRESP = M00_AXI_rresp[1:0];
assign m00_couplers_to_axi_mem_intercon_RVALID = M00_AXI_rvalid;
assign m00_couplers_to_axi_mem_intercon_WREADY = M00_AXI_wready;
assign m01_couplers_to_axi_mem_intercon_ARREADY = M01_AXI_arready;
assign m01_couplers_to_axi_mem_intercon_AWREADY = M01_AXI_awready;
assign m01_couplers_to_axi_mem_intercon_BRESP = M01_AXI_bresp[1:0];
assign m01_couplers_to_axi_mem_intercon_BVALID = M01_AXI_bvalid;
assign m01_couplers_to_axi_mem_intercon_RDATA = M01_AXI_rdata[31:0];
assign m01_couplers_to_axi_mem_intercon_RLAST = M01_AXI_rlast;
assign m01_couplers_to_axi_mem_intercon_RRESP = M01_AXI_rresp[1:0];
assign m01_couplers_to_axi_mem_intercon_RVALID = M01_AXI_rvalid;
assign m01_couplers_to_axi_mem_intercon_WREADY = M01_AXI_wready;
m00_couplers_imp_1KZV5AP m00_couplers
(.M_ACLK(M00_ACLK_1),
.M_ARESETN(M00_ARESETN_1),
.M_AXI_araddr(m00_couplers_to_axi_mem_intercon_ARADDR),
.M_AXI_arburst(m00_couplers_to_axi_mem_intercon_ARBURST),
.M_AXI_arcache(m00_couplers_to_axi_mem_intercon_ARCACHE),
.M_AXI_arlen(m00_couplers_to_axi_mem_intercon_ARLEN),
.M_AXI_arlock(m00_couplers_to_axi_mem_intercon_ARLOCK),
.M_AXI_arprot(m00_couplers_to_axi_mem_intercon_ARPROT),
.M_AXI_arqos(m00_couplers_to_axi_mem_intercon_ARQOS),
.M_AXI_arready(m00_couplers_to_axi_mem_intercon_ARREADY),
.M_AXI_arsize(m00_couplers_to_axi_mem_intercon_ARSIZE),
.M_AXI_arvalid(m00_couplers_to_axi_mem_intercon_ARVALID),
.M_AXI_awaddr(m00_couplers_to_axi_mem_intercon_AWADDR),
.M_AXI_awburst(m00_couplers_to_axi_mem_intercon_AWBURST),
.M_AXI_awcache(m00_couplers_to_axi_mem_intercon_AWCACHE),
.M_AXI_awlen(m00_couplers_to_axi_mem_intercon_AWLEN),
.M_AXI_awlock(m00_couplers_to_axi_mem_intercon_AWLOCK),
.M_AXI_awprot(m00_couplers_to_axi_mem_intercon_AWPROT),
.M_AXI_awqos(m00_couplers_to_axi_mem_intercon_AWQOS),
.M_AXI_awready(m00_couplers_to_axi_mem_intercon_AWREADY),
.M_AXI_awsize(m00_couplers_to_axi_mem_intercon_AWSIZE),
.M_AXI_awvalid(m00_couplers_to_axi_mem_intercon_AWVALID),
.M_AXI_bready(m00_couplers_to_axi_mem_intercon_BREADY),
.M_AXI_bresp(m00_couplers_to_axi_mem_intercon_BRESP),
.M_AXI_bvalid(m00_couplers_to_axi_mem_intercon_BVALID),
.M_AXI_rdata(m00_couplers_to_axi_mem_intercon_RDATA),
.M_AXI_rlast(m00_couplers_to_axi_mem_intercon_RLAST),
.M_AXI_rready(m00_couplers_to_axi_mem_intercon_RREADY),
.M_AXI_rresp(m00_couplers_to_axi_mem_intercon_RRESP),
.M_AXI_rvalid(m00_couplers_to_axi_mem_intercon_RVALID),
.M_AXI_wdata(m00_couplers_to_axi_mem_intercon_WDATA),
.M_AXI_wlast(m00_couplers_to_axi_mem_intercon_WLAST),
.M_AXI_wready(m00_couplers_to_axi_mem_intercon_WREADY),
.M_AXI_wstrb(m00_couplers_to_axi_mem_intercon_WSTRB),
.M_AXI_wvalid(m00_couplers_to_axi_mem_intercon_WVALID),
.S_ACLK(axi_mem_intercon_ACLK_net),
.S_ARESETN(axi_mem_intercon_ARESETN_net),
.S_AXI_araddr(xbar_to_m00_couplers_ARADDR),
.S_AXI_arburst(xbar_to_m00_couplers_ARBURST),
.S_AXI_arcache(xbar_to_m00_couplers_ARCACHE),
.S_AXI_arlen(xbar_to_m00_couplers_ARLEN),
.S_AXI_arlock(xbar_to_m00_couplers_ARLOCK),
.S_AXI_arprot(xbar_to_m00_couplers_ARPROT),
.S_AXI_arqos(xbar_to_m00_couplers_ARQOS),
.S_AXI_arready(xbar_to_m00_couplers_ARREADY),
.S_AXI_arregion(xbar_to_m00_couplers_ARREGION),
.S_AXI_arsize(xbar_to_m00_couplers_ARSIZE),
.S_AXI_arvalid(xbar_to_m00_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m00_couplers_AWADDR),
.S_AXI_awburst(xbar_to_m00_couplers_AWBURST),
.S_AXI_awcache(xbar_to_m00_couplers_AWCACHE),
.S_AXI_awlen(xbar_to_m00_couplers_AWLEN),
.S_AXI_awlock(xbar_to_m00_couplers_AWLOCK),
.S_AXI_awprot(xbar_to_m00_couplers_AWPROT),
.S_AXI_awqos(xbar_to_m00_couplers_AWQOS),
.S_AXI_awready(xbar_to_m00_couplers_AWREADY),
.S_AXI_awregion(xbar_to_m00_couplers_AWREGION),
.S_AXI_awsize(xbar_to_m00_couplers_AWSIZE),
.S_AXI_awvalid(xbar_to_m00_couplers_AWVALID),
.S_AXI_bready(xbar_to_m00_couplers_BREADY),
.S_AXI_bresp(xbar_to_m00_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m00_couplers_BVALID),
.S_AXI_rdata(xbar_to_m00_couplers_RDATA),
.S_AXI_rlast(xbar_to_m00_couplers_RLAST),
.S_AXI_rready(xbar_to_m00_couplers_RREADY),
.S_AXI_rresp(xbar_to_m00_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m00_couplers_RVALID),
.S_AXI_wdata(xbar_to_m00_couplers_WDATA),
.S_AXI_wlast(xbar_to_m00_couplers_WLAST),
.S_AXI_wready(xbar_to_m00_couplers_WREADY),
.S_AXI_wstrb(xbar_to_m00_couplers_WSTRB),
.S_AXI_wvalid(xbar_to_m00_couplers_WVALID));
m01_couplers_imp_9HVA0G m01_couplers
(.M_ACLK(M01_ACLK_1),
.M_ARESETN(M01_ARESETN_1),
.M_AXI_araddr(m01_couplers_to_axi_mem_intercon_ARADDR),
.M_AXI_arburst(m01_couplers_to_axi_mem_intercon_ARBURST),
.M_AXI_arcache(m01_couplers_to_axi_mem_intercon_ARCACHE),
.M_AXI_arlen(m01_couplers_to_axi_mem_intercon_ARLEN),
.M_AXI_arlock(m01_couplers_to_axi_mem_intercon_ARLOCK),
.M_AXI_arprot(m01_couplers_to_axi_mem_intercon_ARPROT),
.M_AXI_arready(m01_couplers_to_axi_mem_intercon_ARREADY),
.M_AXI_arsize(m01_couplers_to_axi_mem_intercon_ARSIZE),
.M_AXI_arvalid(m01_couplers_to_axi_mem_intercon_ARVALID),
.M_AXI_awaddr(m01_couplers_to_axi_mem_intercon_AWADDR),
.M_AXI_awburst(m01_couplers_to_axi_mem_intercon_AWBURST),
.M_AXI_awcache(m01_couplers_to_axi_mem_intercon_AWCACHE),
.M_AXI_awlen(m01_couplers_to_axi_mem_intercon_AWLEN),
.M_AXI_awlock(m01_couplers_to_axi_mem_intercon_AWLOCK),
.M_AXI_awprot(m01_couplers_to_axi_mem_intercon_AWPROT),
.M_AXI_awready(m01_couplers_to_axi_mem_intercon_AWREADY),
.M_AXI_awsize(m01_couplers_to_axi_mem_intercon_AWSIZE),
.M_AXI_awvalid(m01_couplers_to_axi_mem_intercon_AWVALID),
.M_AXI_bready(m01_couplers_to_axi_mem_intercon_BREADY),
.M_AXI_bresp(m01_couplers_to_axi_mem_intercon_BRESP),
.M_AXI_bvalid(m01_couplers_to_axi_mem_intercon_BVALID),
.M_AXI_rdata(m01_couplers_to_axi_mem_intercon_RDATA),
.M_AXI_rlast(m01_couplers_to_axi_mem_intercon_RLAST),
.M_AXI_rready(m01_couplers_to_axi_mem_intercon_RREADY),
.M_AXI_rresp(m01_couplers_to_axi_mem_intercon_RRESP),
.M_AXI_rvalid(m01_couplers_to_axi_mem_intercon_RVALID),
.M_AXI_wdata(m01_couplers_to_axi_mem_intercon_WDATA),
.M_AXI_wlast(m01_couplers_to_axi_mem_intercon_WLAST),
.M_AXI_wready(m01_couplers_to_axi_mem_intercon_WREADY),
.M_AXI_wstrb(m01_couplers_to_axi_mem_intercon_WSTRB),
.M_AXI_wvalid(m01_couplers_to_axi_mem_intercon_WVALID),
.S_ACLK(axi_mem_intercon_ACLK_net),
.S_ARESETN(axi_mem_intercon_ARESETN_net),
.S_AXI_araddr(xbar_to_m01_couplers_ARADDR),
.S_AXI_arburst(xbar_to_m01_couplers_ARBURST),
.S_AXI_arcache(xbar_to_m01_couplers_ARCACHE),
.S_AXI_arlen(xbar_to_m01_couplers_ARLEN),
.S_AXI_arlock(xbar_to_m01_couplers_ARLOCK),
.S_AXI_arprot(xbar_to_m01_couplers_ARPROT),
.S_AXI_arqos(xbar_to_m01_couplers_ARQOS),
.S_AXI_arready(xbar_to_m01_couplers_ARREADY),
.S_AXI_arregion(xbar_to_m01_couplers_ARREGION),
.S_AXI_arsize(xbar_to_m01_couplers_ARSIZE),
.S_AXI_arvalid(xbar_to_m01_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m01_couplers_AWADDR),
.S_AXI_awburst(xbar_to_m01_couplers_AWBURST),
.S_AXI_awcache(xbar_to_m01_couplers_AWCACHE),
.S_AXI_awlen(xbar_to_m01_couplers_AWLEN),
.S_AXI_awlock(xbar_to_m01_couplers_AWLOCK),
.S_AXI_awprot(xbar_to_m01_couplers_AWPROT),
.S_AXI_awqos(xbar_to_m01_couplers_AWQOS),
.S_AXI_awready(xbar_to_m01_couplers_AWREADY),
.S_AXI_awregion(xbar_to_m01_couplers_AWREGION),
.S_AXI_awsize(xbar_to_m01_couplers_AWSIZE),
.S_AXI_awvalid(xbar_to_m01_couplers_AWVALID),
.S_AXI_bready(xbar_to_m01_couplers_BREADY),
.S_AXI_bresp(xbar_to_m01_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m01_couplers_BVALID),
.S_AXI_rdata(xbar_to_m01_couplers_RDATA),
.S_AXI_rlast(xbar_to_m01_couplers_RLAST),
.S_AXI_rready(xbar_to_m01_couplers_RREADY),
.S_AXI_rresp(xbar_to_m01_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m01_couplers_RVALID),
.S_AXI_wdata(xbar_to_m01_couplers_WDATA),
.S_AXI_wlast(xbar_to_m01_couplers_WLAST),
.S_AXI_wready(xbar_to_m01_couplers_WREADY),
.S_AXI_wstrb(xbar_to_m01_couplers_WSTRB),
.S_AXI_wvalid(xbar_to_m01_couplers_WVALID));
s00_couplers_imp_EIRLJN s00_couplers
(.M_ACLK(axi_mem_intercon_ACLK_net),
.M_ARESETN(axi_mem_intercon_ARESETN_net),
.M_AXI_araddr(s00_couplers_to_xbar_ARADDR),
.M_AXI_arburst(s00_couplers_to_xbar_ARBURST),
.M_AXI_arcache(s00_couplers_to_xbar_ARCACHE),
.M_AXI_arlen(s00_couplers_to_xbar_ARLEN),
.M_AXI_arlock(s00_couplers_to_xbar_ARLOCK),
.M_AXI_arprot(s00_couplers_to_xbar_ARPROT),
.M_AXI_arqos(s00_couplers_to_xbar_ARQOS),
.M_AXI_arready(s00_couplers_to_xbar_ARREADY),
.M_AXI_arsize(s00_couplers_to_xbar_ARSIZE),
.M_AXI_arvalid(s00_couplers_to_xbar_ARVALID),
.M_AXI_awaddr(s00_couplers_to_xbar_AWADDR),
.M_AXI_awburst(s00_couplers_to_xbar_AWBURST),
.M_AXI_awcache(s00_couplers_to_xbar_AWCACHE),
.M_AXI_awlen(s00_couplers_to_xbar_AWLEN),
.M_AXI_awlock(s00_couplers_to_xbar_AWLOCK),
.M_AXI_awprot(s00_couplers_to_xbar_AWPROT),
.M_AXI_awqos(s00_couplers_to_xbar_AWQOS),
.M_AXI_awready(s00_couplers_to_xbar_AWREADY),
.M_AXI_awsize(s00_couplers_to_xbar_AWSIZE),
.M_AXI_awvalid(s00_couplers_to_xbar_AWVALID),
.M_AXI_bready(s00_couplers_to_xbar_BREADY),
.M_AXI_bresp(s00_couplers_to_xbar_BRESP),
.M_AXI_bvalid(s00_couplers_to_xbar_BVALID),
.M_AXI_rdata(s00_couplers_to_xbar_RDATA),
.M_AXI_rlast(s00_couplers_to_xbar_RLAST),
.M_AXI_rready(s00_couplers_to_xbar_RREADY),
.M_AXI_rresp(s00_couplers_to_xbar_RRESP),
.M_AXI_rvalid(s00_couplers_to_xbar_RVALID),
.M_AXI_wdata(s00_couplers_to_xbar_WDATA),
.M_AXI_wlast(s00_couplers_to_xbar_WLAST),
.M_AXI_wready(s00_couplers_to_xbar_WREADY),
.M_AXI_wstrb(s00_couplers_to_xbar_WSTRB),
.M_AXI_wvalid(s00_couplers_to_xbar_WVALID),
.S_ACLK(S00_ACLK_1),
.S_ARESETN(S00_ARESETN_1),
.S_AXI_araddr(axi_mem_intercon_to_s00_couplers_ARADDR),
.S_AXI_arburst(axi_mem_intercon_to_s00_couplers_ARBURST),
.S_AXI_arcache(axi_mem_intercon_to_s00_couplers_ARCACHE),
.S_AXI_arlen(axi_mem_intercon_to_s00_couplers_ARLEN),
.S_AXI_arprot(axi_mem_intercon_to_s00_couplers_ARPROT),
.S_AXI_arready(axi_mem_intercon_to_s00_couplers_ARREADY),
.S_AXI_arsize(axi_mem_intercon_to_s00_couplers_ARSIZE),
.S_AXI_arvalid(axi_mem_intercon_to_s00_couplers_ARVALID),
.S_AXI_awaddr(axi_mem_intercon_to_s00_couplers_AWADDR),
.S_AXI_awburst(axi_mem_intercon_to_s00_couplers_AWBURST),
.S_AXI_awcache(axi_mem_intercon_to_s00_couplers_AWCACHE),
.S_AXI_awlen(axi_mem_intercon_to_s00_couplers_AWLEN),
.S_AXI_awprot(axi_mem_intercon_to_s00_couplers_AWPROT),
.S_AXI_awready(axi_mem_intercon_to_s00_couplers_AWREADY),
.S_AXI_awsize(axi_mem_intercon_to_s00_couplers_AWSIZE),
.S_AXI_awvalid(axi_mem_intercon_to_s00_couplers_AWVALID),
.S_AXI_bready(axi_mem_intercon_to_s00_couplers_BREADY),
.S_AXI_bresp(axi_mem_intercon_to_s00_couplers_BRESP),
.S_AXI_bvalid(axi_mem_intercon_to_s00_couplers_BVALID),
.S_AXI_rdata(axi_mem_intercon_to_s00_couplers_RDATA),
.S_AXI_rlast(axi_mem_intercon_to_s00_couplers_RLAST),
.S_AXI_rready(axi_mem_intercon_to_s00_couplers_RREADY),
.S_AXI_rresp(axi_mem_intercon_to_s00_couplers_RRESP),
.S_AXI_rvalid(axi_mem_intercon_to_s00_couplers_RVALID),
.S_AXI_wdata(axi_mem_intercon_to_s00_couplers_WDATA),
.S_AXI_wlast(axi_mem_intercon_to_s00_couplers_WLAST),
.S_AXI_wready(axi_mem_intercon_to_s00_couplers_WREADY),
.S_AXI_wstrb(axi_mem_intercon_to_s00_couplers_WSTRB),
.S_AXI_wvalid(axi_mem_intercon_to_s00_couplers_WVALID));
design_1_xbar_0 xbar
(.aclk(axi_mem_intercon_ACLK_net),
.aresetn(axi_mem_intercon_ARESETN_net),
.m_axi_araddr({xbar_to_m01_couplers_ARADDR,xbar_to_m00_couplers_ARADDR}),
.m_axi_arburst({xbar_to_m01_couplers_ARBURST,xbar_to_m00_couplers_ARBURST}),
.m_axi_arcache({xbar_to_m01_couplers_ARCACHE,xbar_to_m00_couplers_ARCACHE}),
.m_axi_arlen({xbar_to_m01_couplers_ARLEN,xbar_to_m00_couplers_ARLEN}),
.m_axi_arlock({xbar_to_m01_couplers_ARLOCK,xbar_to_m00_couplers_ARLOCK}),
.m_axi_arprot({xbar_to_m01_couplers_ARPROT,xbar_to_m00_couplers_ARPROT}),
.m_axi_arqos({xbar_to_m01_couplers_ARQOS,xbar_to_m00_couplers_ARQOS}),
.m_axi_arready({xbar_to_m01_couplers_ARREADY,xbar_to_m00_couplers_ARREADY}),
.m_axi_arregion({xbar_to_m01_couplers_ARREGION,xbar_to_m00_couplers_ARREGION}),
.m_axi_arsize({xbar_to_m01_couplers_ARSIZE,xbar_to_m00_couplers_ARSIZE}),
.m_axi_arvalid({xbar_to_m01_couplers_ARVALID,xbar_to_m00_couplers_ARVALID}),
.m_axi_awaddr({xbar_to_m01_couplers_AWADDR,xbar_to_m00_couplers_AWADDR}),
.m_axi_awburst({xbar_to_m01_couplers_AWBURST,xbar_to_m00_couplers_AWBURST}),
.m_axi_awcache({xbar_to_m01_couplers_AWCACHE,xbar_to_m00_couplers_AWCACHE}),
.m_axi_awlen({xbar_to_m01_couplers_AWLEN,xbar_to_m00_couplers_AWLEN}),
.m_axi_awlock({xbar_to_m01_couplers_AWLOCK,xbar_to_m00_couplers_AWLOCK}),
.m_axi_awprot({xbar_to_m01_couplers_AWPROT,xbar_to_m00_couplers_AWPROT}),
.m_axi_awqos({xbar_to_m01_couplers_AWQOS,xbar_to_m00_couplers_AWQOS}),
.m_axi_awready({xbar_to_m01_couplers_AWREADY,xbar_to_m00_couplers_AWREADY}),
.m_axi_awregion({xbar_to_m01_couplers_AWREGION,xbar_to_m00_couplers_AWREGION}),
.m_axi_awsize({xbar_to_m01_couplers_AWSIZE,xbar_to_m00_couplers_AWSIZE}),
.m_axi_awvalid({xbar_to_m01_couplers_AWVALID,xbar_to_m00_couplers_AWVALID}),
.m_axi_bready({xbar_to_m01_couplers_BREADY,xbar_to_m00_couplers_BREADY}),
.m_axi_bresp({xbar_to_m01_couplers_BRESP,xbar_to_m00_couplers_BRESP}),
.m_axi_bvalid({xbar_to_m01_couplers_BVALID,xbar_to_m00_couplers_BVALID}),
.m_axi_rdata({xbar_to_m01_couplers_RDATA,xbar_to_m00_couplers_RDATA}),
.m_axi_rlast({xbar_to_m01_couplers_RLAST,xbar_to_m00_couplers_RLAST}),
.m_axi_rready({xbar_to_m01_couplers_RREADY,xbar_to_m00_couplers_RREADY}),
.m_axi_rresp({xbar_to_m01_couplers_RRESP,xbar_to_m00_couplers_RRESP}),
.m_axi_rvalid({xbar_to_m01_couplers_RVALID,xbar_to_m00_couplers_RVALID}),
.m_axi_wdata({xbar_to_m01_couplers_WDATA,xbar_to_m00_couplers_WDATA}),
.m_axi_wlast({xbar_to_m01_couplers_WLAST,xbar_to_m00_couplers_WLAST}),
.m_axi_wready({xbar_to_m01_couplers_WREADY,xbar_to_m00_couplers_WREADY}),
.m_axi_wstrb({xbar_to_m01_couplers_WSTRB,xbar_to_m00_couplers_WSTRB}),
.m_axi_wvalid({xbar_to_m01_couplers_WVALID,xbar_to_m00_couplers_WVALID}),
.s_axi_araddr(s00_couplers_to_xbar_ARADDR),
.s_axi_arburst(s00_couplers_to_xbar_ARBURST),
.s_axi_arcache(s00_couplers_to_xbar_ARCACHE),
.s_axi_arlen(s00_couplers_to_xbar_ARLEN),
.s_axi_arlock(s00_couplers_to_xbar_ARLOCK),
.s_axi_arprot(s00_couplers_to_xbar_ARPROT),
.s_axi_arqos(s00_couplers_to_xbar_ARQOS),
.s_axi_arready(s00_couplers_to_xbar_ARREADY),
.s_axi_arsize(s00_couplers_to_xbar_ARSIZE),
.s_axi_arvalid(s00_couplers_to_xbar_ARVALID),
.s_axi_awaddr(s00_couplers_to_xbar_AWADDR),
.s_axi_awburst(s00_couplers_to_xbar_AWBURST),
.s_axi_awcache(s00_couplers_to_xbar_AWCACHE),
.s_axi_awlen(s00_couplers_to_xbar_AWLEN),
.s_axi_awlock(s00_couplers_to_xbar_AWLOCK),
.s_axi_awprot(s00_couplers_to_xbar_AWPROT),
.s_axi_awqos(s00_couplers_to_xbar_AWQOS),
.s_axi_awready(s00_couplers_to_xbar_AWREADY),
.s_axi_awsize(s00_couplers_to_xbar_AWSIZE),
.s_axi_awvalid(s00_couplers_to_xbar_AWVALID),
.s_axi_bready(s00_couplers_to_xbar_BREADY),
.s_axi_bresp(s00_couplers_to_xbar_BRESP),
.s_axi_bvalid(s00_couplers_to_xbar_BVALID),
.s_axi_rdata(s00_couplers_to_xbar_RDATA),
.s_axi_rlast(s00_couplers_to_xbar_RLAST),
.s_axi_rready(s00_couplers_to_xbar_RREADY),
.s_axi_rresp(s00_couplers_to_xbar_RRESP),
.s_axi_rvalid(s00_couplers_to_xbar_RVALID),
.s_axi_wdata(s00_couplers_to_xbar_WDATA),
.s_axi_wlast(s00_couplers_to_xbar_WLAST),
.s_axi_wready(s00_couplers_to_xbar_WREADY),
.s_axi_wstrb(s00_couplers_to_xbar_WSTRB),
.s_axi_wvalid(s00_couplers_to_xbar_WVALID));
endmodule
module design_1_axi_mem_intercon_2
(ACLK,
ARESETN,
M00_ACLK,
M00_ARESETN,
M00_AXI_araddr,
M00_AXI_arburst,
M00_AXI_arcache,
M00_AXI_arlen,
M00_AXI_arlock,
M00_AXI_arprot,
M00_AXI_arqos,
M00_AXI_arready,
M00_AXI_arsize,
M00_AXI_arvalid,
M00_AXI_awaddr,
M00_AXI_awburst,
M00_AXI_awcache,
M00_AXI_awlen,
M00_AXI_awlock,
M00_AXI_awprot,
M00_AXI_awqos,
M00_AXI_awready,
M00_AXI_awsize,
M00_AXI_awvalid,
M00_AXI_bready,
M00_AXI_bresp,
M00_AXI_bvalid,
M00_AXI_rdata,
M00_AXI_rlast,
M00_AXI_rready,
M00_AXI_rresp,
M00_AXI_rvalid,
M00_AXI_wdata,
M00_AXI_wlast,
M00_AXI_wready,
M00_AXI_wstrb,
M00_AXI_wvalid,
M01_ACLK,
M01_ARESETN,
M01_AXI_araddr,
M01_AXI_arburst,
M01_AXI_arcache,
M01_AXI_arlen,
M01_AXI_arlock,
M01_AXI_arprot,
M01_AXI_arready,
M01_AXI_arsize,
M01_AXI_arvalid,
M01_AXI_awaddr,
M01_AXI_awburst,
M01_AXI_awcache,
M01_AXI_awlen,
M01_AXI_awlock,
M01_AXI_awprot,
M01_AXI_awready,
M01_AXI_awsize,
M01_AXI_awvalid,
M01_AXI_bready,
M01_AXI_bresp,
M01_AXI_bvalid,
M01_AXI_rdata,
M01_AXI_rlast,
M01_AXI_rready,
M01_AXI_rresp,
M01_AXI_rvalid,
M01_AXI_wdata,
M01_AXI_wlast,
M01_AXI_wready,
M01_AXI_wstrb,
M01_AXI_wvalid,
S00_ACLK,
S00_ARESETN,
S00_AXI_araddr,
S00_AXI_arburst,
S00_AXI_arcache,
S00_AXI_arlen,
S00_AXI_arprot,
S00_AXI_arready,
S00_AXI_arsize,
S00_AXI_arvalid,
S00_AXI_awaddr,
S00_AXI_awburst,
S00_AXI_awcache,
S00_AXI_awlen,
S00_AXI_awprot,
S00_AXI_awready,
S00_AXI_awsize,
S00_AXI_awvalid,
S00_AXI_bready,
S00_AXI_bresp,
S00_AXI_bvalid,
S00_AXI_rdata,
S00_AXI_rlast,
S00_AXI_rready,
S00_AXI_rresp,
S00_AXI_rvalid,
S00_AXI_wdata,
S00_AXI_wlast,
S00_AXI_wready,
S00_AXI_wstrb,
S00_AXI_wvalid);
input ACLK;
input ARESETN;
input M00_ACLK;
input M00_ARESETN;
output [31:0]M00_AXI_araddr;
output [1:0]M00_AXI_arburst;
output [3:0]M00_AXI_arcache;
output [3:0]M00_AXI_arlen;
output [1:0]M00_AXI_arlock;
output [2:0]M00_AXI_arprot;
output [3:0]M00_AXI_arqos;
input M00_AXI_arready;
output [2:0]M00_AXI_arsize;
output M00_AXI_arvalid;
output [31:0]M00_AXI_awaddr;
output [1:0]M00_AXI_awburst;
output [3:0]M00_AXI_awcache;
output [3:0]M00_AXI_awlen;
output [1:0]M00_AXI_awlock;
output [2:0]M00_AXI_awprot;
output [3:0]M00_AXI_awqos;
input M00_AXI_awready;
output [2:0]M00_AXI_awsize;
output M00_AXI_awvalid;
output M00_AXI_bready;
input [1:0]M00_AXI_bresp;
input M00_AXI_bvalid;
input [63:0]M00_AXI_rdata;
input M00_AXI_rlast;
output M00_AXI_rready;
input [1:0]M00_AXI_rresp;
input M00_AXI_rvalid;
output [63:0]M00_AXI_wdata;
output M00_AXI_wlast;
input M00_AXI_wready;
output [7:0]M00_AXI_wstrb;
output M00_AXI_wvalid;
input M01_ACLK;
input M01_ARESETN;
output [12:0]M01_AXI_araddr;
output [1:0]M01_AXI_arburst;
output [3:0]M01_AXI_arcache;
output [7:0]M01_AXI_arlen;
output [0:0]M01_AXI_arlock;
output [2:0]M01_AXI_arprot;
input M01_AXI_arready;
output [2:0]M01_AXI_arsize;
output M01_AXI_arvalid;
output [12:0]M01_AXI_awaddr;
output [1:0]M01_AXI_awburst;
output [3:0]M01_AXI_awcache;
output [7:0]M01_AXI_awlen;
output [0:0]M01_AXI_awlock;
output [2:0]M01_AXI_awprot;
input M01_AXI_awready;
output [2:0]M01_AXI_awsize;
output M01_AXI_awvalid;
output M01_AXI_bready;
input [1:0]M01_AXI_bresp;
input M01_AXI_bvalid;
input [31:0]M01_AXI_rdata;
input M01_AXI_rlast;
output M01_AXI_rready;
input [1:0]M01_AXI_rresp;
input M01_AXI_rvalid;
output [31:0]M01_AXI_wdata;
output M01_AXI_wlast;
input M01_AXI_wready;
output [3:0]M01_AXI_wstrb;
output M01_AXI_wvalid;
input S00_ACLK;
input S00_ARESETN;
input [31:0]S00_AXI_araddr;
input [1:0]S00_AXI_arburst;
input [3:0]S00_AXI_arcache;
input [7:0]S00_AXI_arlen;
input [2:0]S00_AXI_arprot;
output S00_AXI_arready;
input [2:0]S00_AXI_arsize;
input S00_AXI_arvalid;
input [31:0]S00_AXI_awaddr;
input [1:0]S00_AXI_awburst;
input [3:0]S00_AXI_awcache;
input [7:0]S00_AXI_awlen;
input [2:0]S00_AXI_awprot;
output S00_AXI_awready;
input [2:0]S00_AXI_awsize;
input S00_AXI_awvalid;
input S00_AXI_bready;
output [1:0]S00_AXI_bresp;
output S00_AXI_bvalid;
output [31:0]S00_AXI_rdata;
output S00_AXI_rlast;
input S00_AXI_rready;
output [1:0]S00_AXI_rresp;
output S00_AXI_rvalid;
input [31:0]S00_AXI_wdata;
input S00_AXI_wlast;
output S00_AXI_wready;
input [3:0]S00_AXI_wstrb;
input S00_AXI_wvalid;
wire M00_ACLK_1;
wire M00_ARESETN_1;
wire M01_ACLK_1;
wire M01_ARESETN_1;
wire S00_ACLK_1;
wire S00_ARESETN_1;
wire axi_mem_intercon_ACLK_net;
wire axi_mem_intercon_ARESETN_net;
wire [31:0]axi_mem_intercon_to_s00_couplers_ARADDR;
wire [1:0]axi_mem_intercon_to_s00_couplers_ARBURST;
wire [3:0]axi_mem_intercon_to_s00_couplers_ARCACHE;
wire [7:0]axi_mem_intercon_to_s00_couplers_ARLEN;
wire [2:0]axi_mem_intercon_to_s00_couplers_ARPROT;
wire axi_mem_intercon_to_s00_couplers_ARREADY;
wire [2:0]axi_mem_intercon_to_s00_couplers_ARSIZE;
wire axi_mem_intercon_to_s00_couplers_ARVALID;
wire [31:0]axi_mem_intercon_to_s00_couplers_AWADDR;
wire [1:0]axi_mem_intercon_to_s00_couplers_AWBURST;
wire [3:0]axi_mem_intercon_to_s00_couplers_AWCACHE;
wire [7:0]axi_mem_intercon_to_s00_couplers_AWLEN;
wire [2:0]axi_mem_intercon_to_s00_couplers_AWPROT;
wire axi_mem_intercon_to_s00_couplers_AWREADY;
wire [2:0]axi_mem_intercon_to_s00_couplers_AWSIZE;
wire axi_mem_intercon_to_s00_couplers_AWVALID;
wire axi_mem_intercon_to_s00_couplers_BREADY;
wire [1:0]axi_mem_intercon_to_s00_couplers_BRESP;
wire axi_mem_intercon_to_s00_couplers_BVALID;
wire [31:0]axi_mem_intercon_to_s00_couplers_RDATA;
wire axi_mem_intercon_to_s00_couplers_RLAST;
wire axi_mem_intercon_to_s00_couplers_RREADY;
wire [1:0]axi_mem_intercon_to_s00_couplers_RRESP;
wire axi_mem_intercon_to_s00_couplers_RVALID;
wire [31:0]axi_mem_intercon_to_s00_couplers_WDATA;
wire axi_mem_intercon_to_s00_couplers_WLAST;
wire axi_mem_intercon_to_s00_couplers_WREADY;
wire [3:0]axi_mem_intercon_to_s00_couplers_WSTRB;
wire axi_mem_intercon_to_s00_couplers_WVALID;
wire [31:0]m00_couplers_to_axi_mem_intercon_ARADDR;
wire [1:0]m00_couplers_to_axi_mem_intercon_ARBURST;
wire [3:0]m00_couplers_to_axi_mem_intercon_ARCACHE;
wire [3:0]m00_couplers_to_axi_mem_intercon_ARLEN;
wire [1:0]m00_couplers_to_axi_mem_intercon_ARLOCK;
wire [2:0]m00_couplers_to_axi_mem_intercon_ARPROT;
wire [3:0]m00_couplers_to_axi_mem_intercon_ARQOS;
wire m00_couplers_to_axi_mem_intercon_ARREADY;
wire [2:0]m00_couplers_to_axi_mem_intercon_ARSIZE;
wire m00_couplers_to_axi_mem_intercon_ARVALID;
wire [31:0]m00_couplers_to_axi_mem_intercon_AWADDR;
wire [1:0]m00_couplers_to_axi_mem_intercon_AWBURST;
wire [3:0]m00_couplers_to_axi_mem_intercon_AWCACHE;
wire [3:0]m00_couplers_to_axi_mem_intercon_AWLEN;
wire [1:0]m00_couplers_to_axi_mem_intercon_AWLOCK;
wire [2:0]m00_couplers_to_axi_mem_intercon_AWPROT;
wire [3:0]m00_couplers_to_axi_mem_intercon_AWQOS;
wire m00_couplers_to_axi_mem_intercon_AWREADY;
wire [2:0]m00_couplers_to_axi_mem_intercon_AWSIZE;
wire m00_couplers_to_axi_mem_intercon_AWVALID;
wire m00_couplers_to_axi_mem_intercon_BREADY;
wire [1:0]m00_couplers_to_axi_mem_intercon_BRESP;
wire m00_couplers_to_axi_mem_intercon_BVALID;
wire [63:0]m00_couplers_to_axi_mem_intercon_RDATA;
wire m00_couplers_to_axi_mem_intercon_RLAST;
wire m00_couplers_to_axi_mem_intercon_RREADY;
wire [1:0]m00_couplers_to_axi_mem_intercon_RRESP;
wire m00_couplers_to_axi_mem_intercon_RVALID;
wire [63:0]m00_couplers_to_axi_mem_intercon_WDATA;
wire m00_couplers_to_axi_mem_intercon_WLAST;
wire m00_couplers_to_axi_mem_intercon_WREADY;
wire [7:0]m00_couplers_to_axi_mem_intercon_WSTRB;
wire m00_couplers_to_axi_mem_intercon_WVALID;
wire [12:0]m01_couplers_to_axi_mem_intercon_ARADDR;
wire [1:0]m01_couplers_to_axi_mem_intercon_ARBURST;
wire [3:0]m01_couplers_to_axi_mem_intercon_ARCACHE;
wire [7:0]m01_couplers_to_axi_mem_intercon_ARLEN;
wire [0:0]m01_couplers_to_axi_mem_intercon_ARLOCK;
wire [2:0]m01_couplers_to_axi_mem_intercon_ARPROT;
wire m01_couplers_to_axi_mem_intercon_ARREADY;
wire [2:0]m01_couplers_to_axi_mem_intercon_ARSIZE;
wire m01_couplers_to_axi_mem_intercon_ARVALID;
wire [12:0]m01_couplers_to_axi_mem_intercon_AWADDR;
wire [1:0]m01_couplers_to_axi_mem_intercon_AWBURST;
wire [3:0]m01_couplers_to_axi_mem_intercon_AWCACHE;
wire [7:0]m01_couplers_to_axi_mem_intercon_AWLEN;
wire [0:0]m01_couplers_to_axi_mem_intercon_AWLOCK;
wire [2:0]m01_couplers_to_axi_mem_intercon_AWPROT;
wire m01_couplers_to_axi_mem_intercon_AWREADY;
wire [2:0]m01_couplers_to_axi_mem_intercon_AWSIZE;
wire m01_couplers_to_axi_mem_intercon_AWVALID;
wire m01_couplers_to_axi_mem_intercon_BREADY;
wire [1:0]m01_couplers_to_axi_mem_intercon_BRESP;
wire m01_couplers_to_axi_mem_intercon_BVALID;
wire [31:0]m01_couplers_to_axi_mem_intercon_RDATA;
wire m01_couplers_to_axi_mem_intercon_RLAST;
wire m01_couplers_to_axi_mem_intercon_RREADY;
wire [1:0]m01_couplers_to_axi_mem_intercon_RRESP;
wire m01_couplers_to_axi_mem_intercon_RVALID;
wire [31:0]m01_couplers_to_axi_mem_intercon_WDATA;
wire m01_couplers_to_axi_mem_intercon_WLAST;
wire m01_couplers_to_axi_mem_intercon_WREADY;
wire [3:0]m01_couplers_to_axi_mem_intercon_WSTRB;
wire m01_couplers_to_axi_mem_intercon_WVALID;
wire [31:0]s00_couplers_to_xbar_ARADDR;
wire [1:0]s00_couplers_to_xbar_ARBURST;
wire [3:0]s00_couplers_to_xbar_ARCACHE;
wire [7:0]s00_couplers_to_xbar_ARLEN;
wire [0:0]s00_couplers_to_xbar_ARLOCK;
wire [2:0]s00_couplers_to_xbar_ARPROT;
wire [3:0]s00_couplers_to_xbar_ARQOS;
wire [0:0]s00_couplers_to_xbar_ARREADY;
wire [2:0]s00_couplers_to_xbar_ARSIZE;
wire s00_couplers_to_xbar_ARVALID;
wire [31:0]s00_couplers_to_xbar_AWADDR;
wire [1:0]s00_couplers_to_xbar_AWBURST;
wire [3:0]s00_couplers_to_xbar_AWCACHE;
wire [7:0]s00_couplers_to_xbar_AWLEN;
wire [0:0]s00_couplers_to_xbar_AWLOCK;
wire [2:0]s00_couplers_to_xbar_AWPROT;
wire [3:0]s00_couplers_to_xbar_AWQOS;
wire [0:0]s00_couplers_to_xbar_AWREADY;
wire [2:0]s00_couplers_to_xbar_AWSIZE;
wire s00_couplers_to_xbar_AWVALID;
wire s00_couplers_to_xbar_BREADY;
wire [1:0]s00_couplers_to_xbar_BRESP;
wire [0:0]s00_couplers_to_xbar_BVALID;
wire [63:0]s00_couplers_to_xbar_RDATA;
wire [0:0]s00_couplers_to_xbar_RLAST;
wire s00_couplers_to_xbar_RREADY;
wire [1:0]s00_couplers_to_xbar_RRESP;
wire [0:0]s00_couplers_to_xbar_RVALID;
wire [63:0]s00_couplers_to_xbar_WDATA;
wire s00_couplers_to_xbar_WLAST;
wire [0:0]s00_couplers_to_xbar_WREADY;
wire [7:0]s00_couplers_to_xbar_WSTRB;
wire s00_couplers_to_xbar_WVALID;
wire [31:0]xbar_to_m00_couplers_ARADDR;
wire [1:0]xbar_to_m00_couplers_ARBURST;
wire [3:0]xbar_to_m00_couplers_ARCACHE;
wire [7:0]xbar_to_m00_couplers_ARLEN;
wire [0:0]xbar_to_m00_couplers_ARLOCK;
wire [2:0]xbar_to_m00_couplers_ARPROT;
wire [3:0]xbar_to_m00_couplers_ARQOS;
wire xbar_to_m00_couplers_ARREADY;
wire [3:0]xbar_to_m00_couplers_ARREGION;
wire [2:0]xbar_to_m00_couplers_ARSIZE;
wire [0:0]xbar_to_m00_couplers_ARVALID;
wire [31:0]xbar_to_m00_couplers_AWADDR;
wire [1:0]xbar_to_m00_couplers_AWBURST;
wire [3:0]xbar_to_m00_couplers_AWCACHE;
wire [7:0]xbar_to_m00_couplers_AWLEN;
wire [0:0]xbar_to_m00_couplers_AWLOCK;
wire [2:0]xbar_to_m00_couplers_AWPROT;
wire [3:0]xbar_to_m00_couplers_AWQOS;
wire xbar_to_m00_couplers_AWREADY;
wire [3:0]xbar_to_m00_couplers_AWREGION;
wire [2:0]xbar_to_m00_couplers_AWSIZE;
wire [0:0]xbar_to_m00_couplers_AWVALID;
wire [0:0]xbar_to_m00_couplers_BREADY;
wire [1:0]xbar_to_m00_couplers_BRESP;
wire xbar_to_m00_couplers_BVALID;
wire [63:0]xbar_to_m00_couplers_RDATA;
wire xbar_to_m00_couplers_RLAST;
wire [0:0]xbar_to_m00_couplers_RREADY;
wire [1:0]xbar_to_m00_couplers_RRESP;
wire xbar_to_m00_couplers_RVALID;
wire [63:0]xbar_to_m00_couplers_WDATA;
wire [0:0]xbar_to_m00_couplers_WLAST;
wire xbar_to_m00_couplers_WREADY;
wire [7:0]xbar_to_m00_couplers_WSTRB;
wire [0:0]xbar_to_m00_couplers_WVALID;
wire [63:32]xbar_to_m01_couplers_ARADDR;
wire [3:2]xbar_to_m01_couplers_ARBURST;
wire [7:4]xbar_to_m01_couplers_ARCACHE;
wire [15:8]xbar_to_m01_couplers_ARLEN;
wire [1:1]xbar_to_m01_couplers_ARLOCK;
wire [5:3]xbar_to_m01_couplers_ARPROT;
wire [7:4]xbar_to_m01_couplers_ARQOS;
wire xbar_to_m01_couplers_ARREADY;
wire [7:4]xbar_to_m01_couplers_ARREGION;
wire [5:3]xbar_to_m01_couplers_ARSIZE;
wire [1:1]xbar_to_m01_couplers_ARVALID;
wire [63:32]xbar_to_m01_couplers_AWADDR;
wire [3:2]xbar_to_m01_couplers_AWBURST;
wire [7:4]xbar_to_m01_couplers_AWCACHE;
wire [15:8]xbar_to_m01_couplers_AWLEN;
wire [1:1]xbar_to_m01_couplers_AWLOCK;
wire [5:3]xbar_to_m01_couplers_AWPROT;
wire [7:4]xbar_to_m01_couplers_AWQOS;
wire xbar_to_m01_couplers_AWREADY;
wire [7:4]xbar_to_m01_couplers_AWREGION;
wire [5:3]xbar_to_m01_couplers_AWSIZE;
wire [1:1]xbar_to_m01_couplers_AWVALID;
wire [1:1]xbar_to_m01_couplers_BREADY;
wire [1:0]xbar_to_m01_couplers_BRESP;
wire xbar_to_m01_couplers_BVALID;
wire [63:0]xbar_to_m01_couplers_RDATA;
wire xbar_to_m01_couplers_RLAST;
wire [1:1]xbar_to_m01_couplers_RREADY;
wire [1:0]xbar_to_m01_couplers_RRESP;
wire xbar_to_m01_couplers_RVALID;
wire [127:64]xbar_to_m01_couplers_WDATA;
wire [1:1]xbar_to_m01_couplers_WLAST;
wire xbar_to_m01_couplers_WREADY;
wire [15:8]xbar_to_m01_couplers_WSTRB;
wire [1:1]xbar_to_m01_couplers_WVALID;
assign M00_ACLK_1 = M00_ACLK;
assign M00_ARESETN_1 = M00_ARESETN;
assign M00_AXI_araddr[31:0] = m00_couplers_to_axi_mem_intercon_ARADDR;
assign M00_AXI_arburst[1:0] = m00_couplers_to_axi_mem_intercon_ARBURST;
assign M00_AXI_arcache[3:0] = m00_couplers_to_axi_mem_intercon_ARCACHE;
assign M00_AXI_arlen[3:0] = m00_couplers_to_axi_mem_intercon_ARLEN;
assign M00_AXI_arlock[1:0] = m00_couplers_to_axi_mem_intercon_ARLOCK;
assign M00_AXI_arprot[2:0] = m00_couplers_to_axi_mem_intercon_ARPROT;
assign M00_AXI_arqos[3:0] = m00_couplers_to_axi_mem_intercon_ARQOS;
assign M00_AXI_arsize[2:0] = m00_couplers_to_axi_mem_intercon_ARSIZE;
assign M00_AXI_arvalid = m00_couplers_to_axi_mem_intercon_ARVALID;
assign M00_AXI_awaddr[31:0] = m00_couplers_to_axi_mem_intercon_AWADDR;
assign M00_AXI_awburst[1:0] = m00_couplers_to_axi_mem_intercon_AWBURST;
assign M00_AXI_awcache[3:0] = m00_couplers_to_axi_mem_intercon_AWCACHE;
assign M00_AXI_awlen[3:0] = m00_couplers_to_axi_mem_intercon_AWLEN;
assign M00_AXI_awlock[1:0] = m00_couplers_to_axi_mem_intercon_AWLOCK;
assign M00_AXI_awprot[2:0] = m00_couplers_to_axi_mem_intercon_AWPROT;
assign M00_AXI_awqos[3:0] = m00_couplers_to_axi_mem_intercon_AWQOS;
assign M00_AXI_awsize[2:0] = m00_couplers_to_axi_mem_intercon_AWSIZE;
assign M00_AXI_awvalid = m00_couplers_to_axi_mem_intercon_AWVALID;
assign M00_AXI_bready = m00_couplers_to_axi_mem_intercon_BREADY;
assign M00_AXI_rready = m00_couplers_to_axi_mem_intercon_RREADY;
assign M00_AXI_wdata[63:0] = m00_couplers_to_axi_mem_intercon_WDATA;
assign M00_AXI_wlast = m00_couplers_to_axi_mem_intercon_WLAST;
assign M00_AXI_wstrb[7:0] = m00_couplers_to_axi_mem_intercon_WSTRB;
assign M00_AXI_wvalid = m00_couplers_to_axi_mem_intercon_WVALID;
assign M01_ACLK_1 = M01_ACLK;
assign M01_ARESETN_1 = M01_ARESETN;
assign M01_AXI_araddr[12:0] = m01_couplers_to_axi_mem_intercon_ARADDR;
assign M01_AXI_arburst[1:0] = m01_couplers_to_axi_mem_intercon_ARBURST;
assign M01_AXI_arcache[3:0] = m01_couplers_to_axi_mem_intercon_ARCACHE;
assign M01_AXI_arlen[7:0] = m01_couplers_to_axi_mem_intercon_ARLEN;
assign M01_AXI_arlock[0] = m01_couplers_to_axi_mem_intercon_ARLOCK;
assign M01_AXI_arprot[2:0] = m01_couplers_to_axi_mem_intercon_ARPROT;
assign M01_AXI_arsize[2:0] = m01_couplers_to_axi_mem_intercon_ARSIZE;
assign M01_AXI_arvalid = m01_couplers_to_axi_mem_intercon_ARVALID;
assign M01_AXI_awaddr[12:0] = m01_couplers_to_axi_mem_intercon_AWADDR;
assign M01_AXI_awburst[1:0] = m01_couplers_to_axi_mem_intercon_AWBURST;
assign M01_AXI_awcache[3:0] = m01_couplers_to_axi_mem_intercon_AWCACHE;
assign M01_AXI_awlen[7:0] = m01_couplers_to_axi_mem_intercon_AWLEN;
assign M01_AXI_awlock[0] = m01_couplers_to_axi_mem_intercon_AWLOCK;
assign M01_AXI_awprot[2:0] = m01_couplers_to_axi_mem_intercon_AWPROT;
assign M01_AXI_awsize[2:0] = m01_couplers_to_axi_mem_intercon_AWSIZE;
assign M01_AXI_awvalid = m01_couplers_to_axi_mem_intercon_AWVALID;
assign M01_AXI_bready = m01_couplers_to_axi_mem_intercon_BREADY;
assign M01_AXI_rready = m01_couplers_to_axi_mem_intercon_RREADY;
assign M01_AXI_wdata[31:0] = m01_couplers_to_axi_mem_intercon_WDATA;
assign M01_AXI_wlast = m01_couplers_to_axi_mem_intercon_WLAST;
assign M01_AXI_wstrb[3:0] = m01_couplers_to_axi_mem_intercon_WSTRB;
assign M01_AXI_wvalid = m01_couplers_to_axi_mem_intercon_WVALID;
assign S00_ACLK_1 = S00_ACLK;
assign S00_ARESETN_1 = S00_ARESETN;
assign S00_AXI_arready = axi_mem_intercon_to_s00_couplers_ARREADY;
assign S00_AXI_awready = axi_mem_intercon_to_s00_couplers_AWREADY;
assign S00_AXI_bresp[1:0] = axi_mem_intercon_to_s00_couplers_BRESP;
assign S00_AXI_bvalid = axi_mem_intercon_to_s00_couplers_BVALID;
assign S00_AXI_rdata[31:0] = axi_mem_intercon_to_s00_couplers_RDATA;
assign S00_AXI_rlast = axi_mem_intercon_to_s00_couplers_RLAST;
assign S00_AXI_rresp[1:0] = axi_mem_intercon_to_s00_couplers_RRESP;
assign S00_AXI_rvalid = axi_mem_intercon_to_s00_couplers_RVALID;
assign S00_AXI_wready = axi_mem_intercon_to_s00_couplers_WREADY;
assign axi_mem_intercon_ACLK_net = ACLK;
assign axi_mem_intercon_ARESETN_net = ARESETN;
assign axi_mem_intercon_to_s00_couplers_ARADDR = S00_AXI_araddr[31:0];
assign axi_mem_intercon_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0];
assign axi_mem_intercon_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0];
assign axi_mem_intercon_to_s00_couplers_ARLEN = S00_AXI_arlen[7:0];
assign axi_mem_intercon_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0];
assign axi_mem_intercon_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0];
assign axi_mem_intercon_to_s00_couplers_ARVALID = S00_AXI_arvalid;
assign axi_mem_intercon_to_s00_couplers_AWADDR = S00_AXI_awaddr[31:0];
assign axi_mem_intercon_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0];
assign axi_mem_intercon_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0];
assign axi_mem_intercon_to_s00_couplers_AWLEN = S00_AXI_awlen[7:0];
assign axi_mem_intercon_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0];
assign axi_mem_intercon_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0];
assign axi_mem_intercon_to_s00_couplers_AWVALID = S00_AXI_awvalid;
assign axi_mem_intercon_to_s00_couplers_BREADY = S00_AXI_bready;
assign axi_mem_intercon_to_s00_couplers_RREADY = S00_AXI_rready;
assign axi_mem_intercon_to_s00_couplers_WDATA = S00_AXI_wdata[31:0];
assign axi_mem_intercon_to_s00_couplers_WLAST = S00_AXI_wlast;
assign axi_mem_intercon_to_s00_couplers_WSTRB = S00_AXI_wstrb[3:0];
assign axi_mem_intercon_to_s00_couplers_WVALID = S00_AXI_wvalid;
assign m00_couplers_to_axi_mem_intercon_ARREADY = M00_AXI_arready;
assign m00_couplers_to_axi_mem_intercon_AWREADY = M00_AXI_awready;
assign m00_couplers_to_axi_mem_intercon_BRESP = M00_AXI_bresp[1:0];
assign m00_couplers_to_axi_mem_intercon_BVALID = M00_AXI_bvalid;
assign m00_couplers_to_axi_mem_intercon_RDATA = M00_AXI_rdata[63:0];
assign m00_couplers_to_axi_mem_intercon_RLAST = M00_AXI_rlast;
assign m00_couplers_to_axi_mem_intercon_RRESP = M00_AXI_rresp[1:0];
assign m00_couplers_to_axi_mem_intercon_RVALID = M00_AXI_rvalid;
assign m00_couplers_to_axi_mem_intercon_WREADY = M00_AXI_wready;
assign m01_couplers_to_axi_mem_intercon_ARREADY = M01_AXI_arready;
assign m01_couplers_to_axi_mem_intercon_AWREADY = M01_AXI_awready;
assign m01_couplers_to_axi_mem_intercon_BRESP = M01_AXI_bresp[1:0];
assign m01_couplers_to_axi_mem_intercon_BVALID = M01_AXI_bvalid;
assign m01_couplers_to_axi_mem_intercon_RDATA = M01_AXI_rdata[31:0];
assign m01_couplers_to_axi_mem_intercon_RLAST = M01_AXI_rlast;
assign m01_couplers_to_axi_mem_intercon_RRESP = M01_AXI_rresp[1:0];
assign m01_couplers_to_axi_mem_intercon_RVALID = M01_AXI_rvalid;
assign m01_couplers_to_axi_mem_intercon_WREADY = M01_AXI_wready;
m00_couplers_imp_10LCABC m00_couplers
(.M_ACLK(M00_ACLK_1),
.M_ARESETN(M00_ARESETN_1),
.M_AXI_araddr(m00_couplers_to_axi_mem_intercon_ARADDR),
.M_AXI_arburst(m00_couplers_to_axi_mem_intercon_ARBURST),
.M_AXI_arcache(m00_couplers_to_axi_mem_intercon_ARCACHE),
.M_AXI_arlen(m00_couplers_to_axi_mem_intercon_ARLEN),
.M_AXI_arlock(m00_couplers_to_axi_mem_intercon_ARLOCK),
.M_AXI_arprot(m00_couplers_to_axi_mem_intercon_ARPROT),
.M_AXI_arqos(m00_couplers_to_axi_mem_intercon_ARQOS),
.M_AXI_arready(m00_couplers_to_axi_mem_intercon_ARREADY),
.M_AXI_arsize(m00_couplers_to_axi_mem_intercon_ARSIZE),
.M_AXI_arvalid(m00_couplers_to_axi_mem_intercon_ARVALID),
.M_AXI_awaddr(m00_couplers_to_axi_mem_intercon_AWADDR),
.M_AXI_awburst(m00_couplers_to_axi_mem_intercon_AWBURST),
.M_AXI_awcache(m00_couplers_to_axi_mem_intercon_AWCACHE),
.M_AXI_awlen(m00_couplers_to_axi_mem_intercon_AWLEN),
.M_AXI_awlock(m00_couplers_to_axi_mem_intercon_AWLOCK),
.M_AXI_awprot(m00_couplers_to_axi_mem_intercon_AWPROT),
.M_AXI_awqos(m00_couplers_to_axi_mem_intercon_AWQOS),
.M_AXI_awready(m00_couplers_to_axi_mem_intercon_AWREADY),
.M_AXI_awsize(m00_couplers_to_axi_mem_intercon_AWSIZE),
.M_AXI_awvalid(m00_couplers_to_axi_mem_intercon_AWVALID),
.M_AXI_bready(m00_couplers_to_axi_mem_intercon_BREADY),
.M_AXI_bresp(m00_couplers_to_axi_mem_intercon_BRESP),
.M_AXI_bvalid(m00_couplers_to_axi_mem_intercon_BVALID),
.M_AXI_rdata(m00_couplers_to_axi_mem_intercon_RDATA),
.M_AXI_rlast(m00_couplers_to_axi_mem_intercon_RLAST),
.M_AXI_rready(m00_couplers_to_axi_mem_intercon_RREADY),
.M_AXI_rresp(m00_couplers_to_axi_mem_intercon_RRESP),
.M_AXI_rvalid(m00_couplers_to_axi_mem_intercon_RVALID),
.M_AXI_wdata(m00_couplers_to_axi_mem_intercon_WDATA),
.M_AXI_wlast(m00_couplers_to_axi_mem_intercon_WLAST),
.M_AXI_wready(m00_couplers_to_axi_mem_intercon_WREADY),
.M_AXI_wstrb(m00_couplers_to_axi_mem_intercon_WSTRB),
.M_AXI_wvalid(m00_couplers_to_axi_mem_intercon_WVALID),
.S_ACLK(axi_mem_intercon_ACLK_net),
.S_ARESETN(axi_mem_intercon_ARESETN_net),
.S_AXI_araddr(xbar_to_m00_couplers_ARADDR),
.S_AXI_arburst(xbar_to_m00_couplers_ARBURST),
.S_AXI_arcache(xbar_to_m00_couplers_ARCACHE),
.S_AXI_arlen(xbar_to_m00_couplers_ARLEN),
.S_AXI_arlock(xbar_to_m00_couplers_ARLOCK),
.S_AXI_arprot(xbar_to_m00_couplers_ARPROT),
.S_AXI_arqos(xbar_to_m00_couplers_ARQOS),
.S_AXI_arready(xbar_to_m00_couplers_ARREADY),
.S_AXI_arregion(xbar_to_m00_couplers_ARREGION),
.S_AXI_arsize(xbar_to_m00_couplers_ARSIZE),
.S_AXI_arvalid(xbar_to_m00_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m00_couplers_AWADDR),
.S_AXI_awburst(xbar_to_m00_couplers_AWBURST),
.S_AXI_awcache(xbar_to_m00_couplers_AWCACHE),
.S_AXI_awlen(xbar_to_m00_couplers_AWLEN),
.S_AXI_awlock(xbar_to_m00_couplers_AWLOCK),
.S_AXI_awprot(xbar_to_m00_couplers_AWPROT),
.S_AXI_awqos(xbar_to_m00_couplers_AWQOS),
.S_AXI_awready(xbar_to_m00_couplers_AWREADY),
.S_AXI_awregion(xbar_to_m00_couplers_AWREGION),
.S_AXI_awsize(xbar_to_m00_couplers_AWSIZE),
.S_AXI_awvalid(xbar_to_m00_couplers_AWVALID),
.S_AXI_bready(xbar_to_m00_couplers_BREADY),
.S_AXI_bresp(xbar_to_m00_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m00_couplers_BVALID),
.S_AXI_rdata(xbar_to_m00_couplers_RDATA),
.S_AXI_rlast(xbar_to_m00_couplers_RLAST),
.S_AXI_rready(xbar_to_m00_couplers_RREADY),
.S_AXI_rresp(xbar_to_m00_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m00_couplers_RVALID),
.S_AXI_wdata(xbar_to_m00_couplers_WDATA),
.S_AXI_wlast(xbar_to_m00_couplers_WLAST),
.S_AXI_wready(xbar_to_m00_couplers_WREADY),
.S_AXI_wstrb(xbar_to_m00_couplers_WSTRB),
.S_AXI_wvalid(xbar_to_m00_couplers_WVALID));
m01_couplers_imp_U5OCM1 m01_couplers
(.M_ACLK(M01_ACLK_1),
.M_ARESETN(M01_ARESETN_1),
.M_AXI_araddr(m01_couplers_to_axi_mem_intercon_ARADDR),
.M_AXI_arburst(m01_couplers_to_axi_mem_intercon_ARBURST),
.M_AXI_arcache(m01_couplers_to_axi_mem_intercon_ARCACHE),
.M_AXI_arlen(m01_couplers_to_axi_mem_intercon_ARLEN),
.M_AXI_arlock(m01_couplers_to_axi_mem_intercon_ARLOCK),
.M_AXI_arprot(m01_couplers_to_axi_mem_intercon_ARPROT),
.M_AXI_arready(m01_couplers_to_axi_mem_intercon_ARREADY),
.M_AXI_arsize(m01_couplers_to_axi_mem_intercon_ARSIZE),
.M_AXI_arvalid(m01_couplers_to_axi_mem_intercon_ARVALID),
.M_AXI_awaddr(m01_couplers_to_axi_mem_intercon_AWADDR),
.M_AXI_awburst(m01_couplers_to_axi_mem_intercon_AWBURST),
.M_AXI_awcache(m01_couplers_to_axi_mem_intercon_AWCACHE),
.M_AXI_awlen(m01_couplers_to_axi_mem_intercon_AWLEN),
.M_AXI_awlock(m01_couplers_to_axi_mem_intercon_AWLOCK),
.M_AXI_awprot(m01_couplers_to_axi_mem_intercon_AWPROT),
.M_AXI_awready(m01_couplers_to_axi_mem_intercon_AWREADY),
.M_AXI_awsize(m01_couplers_to_axi_mem_intercon_AWSIZE),
.M_AXI_awvalid(m01_couplers_to_axi_mem_intercon_AWVALID),
.M_AXI_bready(m01_couplers_to_axi_mem_intercon_BREADY),
.M_AXI_bresp(m01_couplers_to_axi_mem_intercon_BRESP),
.M_AXI_bvalid(m01_couplers_to_axi_mem_intercon_BVALID),
.M_AXI_rdata(m01_couplers_to_axi_mem_intercon_RDATA),
.M_AXI_rlast(m01_couplers_to_axi_mem_intercon_RLAST),
.M_AXI_rready(m01_couplers_to_axi_mem_intercon_RREADY),
.M_AXI_rresp(m01_couplers_to_axi_mem_intercon_RRESP),
.M_AXI_rvalid(m01_couplers_to_axi_mem_intercon_RVALID),
.M_AXI_wdata(m01_couplers_to_axi_mem_intercon_WDATA),
.M_AXI_wlast(m01_couplers_to_axi_mem_intercon_WLAST),
.M_AXI_wready(m01_couplers_to_axi_mem_intercon_WREADY),
.M_AXI_wstrb(m01_couplers_to_axi_mem_intercon_WSTRB),
.M_AXI_wvalid(m01_couplers_to_axi_mem_intercon_WVALID),
.S_ACLK(axi_mem_intercon_ACLK_net),
.S_ARESETN(axi_mem_intercon_ARESETN_net),
.S_AXI_araddr(xbar_to_m01_couplers_ARADDR),
.S_AXI_arburst(xbar_to_m01_couplers_ARBURST),
.S_AXI_arcache(xbar_to_m01_couplers_ARCACHE),
.S_AXI_arlen(xbar_to_m01_couplers_ARLEN),
.S_AXI_arlock(xbar_to_m01_couplers_ARLOCK),
.S_AXI_arprot(xbar_to_m01_couplers_ARPROT),
.S_AXI_arqos(xbar_to_m01_couplers_ARQOS),
.S_AXI_arready(xbar_to_m01_couplers_ARREADY),
.S_AXI_arregion(xbar_to_m01_couplers_ARREGION),
.S_AXI_arsize(xbar_to_m01_couplers_ARSIZE),
.S_AXI_arvalid(xbar_to_m01_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m01_couplers_AWADDR),
.S_AXI_awburst(xbar_to_m01_couplers_AWBURST),
.S_AXI_awcache(xbar_to_m01_couplers_AWCACHE),
.S_AXI_awlen(xbar_to_m01_couplers_AWLEN),
.S_AXI_awlock(xbar_to_m01_couplers_AWLOCK),
.S_AXI_awprot(xbar_to_m01_couplers_AWPROT),
.S_AXI_awqos(xbar_to_m01_couplers_AWQOS),
.S_AXI_awready(xbar_to_m01_couplers_AWREADY),
.S_AXI_awregion(xbar_to_m01_couplers_AWREGION),
.S_AXI_awsize(xbar_to_m01_couplers_AWSIZE),
.S_AXI_awvalid(xbar_to_m01_couplers_AWVALID),
.S_AXI_bready(xbar_to_m01_couplers_BREADY),
.S_AXI_bresp(xbar_to_m01_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m01_couplers_BVALID),
.S_AXI_rdata(xbar_to_m01_couplers_RDATA),
.S_AXI_rlast(xbar_to_m01_couplers_RLAST),
.S_AXI_rready(xbar_to_m01_couplers_RREADY),
.S_AXI_rresp(xbar_to_m01_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m01_couplers_RVALID),
.S_AXI_wdata(xbar_to_m01_couplers_WDATA),
.S_AXI_wlast(xbar_to_m01_couplers_WLAST),
.S_AXI_wready(xbar_to_m01_couplers_WREADY),
.S_AXI_wstrb(xbar_to_m01_couplers_WSTRB),
.S_AXI_wvalid(xbar_to_m01_couplers_WVALID));
s00_couplers_imp_Y38QRE s00_couplers
(.M_ACLK(axi_mem_intercon_ACLK_net),
.M_ARESETN(axi_mem_intercon_ARESETN_net),
.M_AXI_araddr(s00_couplers_to_xbar_ARADDR),
.M_AXI_arburst(s00_couplers_to_xbar_ARBURST),
.M_AXI_arcache(s00_couplers_to_xbar_ARCACHE),
.M_AXI_arlen(s00_couplers_to_xbar_ARLEN),
.M_AXI_arlock(s00_couplers_to_xbar_ARLOCK),
.M_AXI_arprot(s00_couplers_to_xbar_ARPROT),
.M_AXI_arqos(s00_couplers_to_xbar_ARQOS),
.M_AXI_arready(s00_couplers_to_xbar_ARREADY),
.M_AXI_arsize(s00_couplers_to_xbar_ARSIZE),
.M_AXI_arvalid(s00_couplers_to_xbar_ARVALID),
.M_AXI_awaddr(s00_couplers_to_xbar_AWADDR),
.M_AXI_awburst(s00_couplers_to_xbar_AWBURST),
.M_AXI_awcache(s00_couplers_to_xbar_AWCACHE),
.M_AXI_awlen(s00_couplers_to_xbar_AWLEN),
.M_AXI_awlock(s00_couplers_to_xbar_AWLOCK),
.M_AXI_awprot(s00_couplers_to_xbar_AWPROT),
.M_AXI_awqos(s00_couplers_to_xbar_AWQOS),
.M_AXI_awready(s00_couplers_to_xbar_AWREADY),
.M_AXI_awsize(s00_couplers_to_xbar_AWSIZE),
.M_AXI_awvalid(s00_couplers_to_xbar_AWVALID),
.M_AXI_bready(s00_couplers_to_xbar_BREADY),
.M_AXI_bresp(s00_couplers_to_xbar_BRESP),
.M_AXI_bvalid(s00_couplers_to_xbar_BVALID),
.M_AXI_rdata(s00_couplers_to_xbar_RDATA),
.M_AXI_rlast(s00_couplers_to_xbar_RLAST),
.M_AXI_rready(s00_couplers_to_xbar_RREADY),
.M_AXI_rresp(s00_couplers_to_xbar_RRESP),
.M_AXI_rvalid(s00_couplers_to_xbar_RVALID),
.M_AXI_wdata(s00_couplers_to_xbar_WDATA),
.M_AXI_wlast(s00_couplers_to_xbar_WLAST),
.M_AXI_wready(s00_couplers_to_xbar_WREADY),
.M_AXI_wstrb(s00_couplers_to_xbar_WSTRB),
.M_AXI_wvalid(s00_couplers_to_xbar_WVALID),
.S_ACLK(S00_ACLK_1),
.S_ARESETN(S00_ARESETN_1),
.S_AXI_araddr(axi_mem_intercon_to_s00_couplers_ARADDR),
.S_AXI_arburst(axi_mem_intercon_to_s00_couplers_ARBURST),
.S_AXI_arcache(axi_mem_intercon_to_s00_couplers_ARCACHE),
.S_AXI_arlen(axi_mem_intercon_to_s00_couplers_ARLEN),
.S_AXI_arprot(axi_mem_intercon_to_s00_couplers_ARPROT),
.S_AXI_arready(axi_mem_intercon_to_s00_couplers_ARREADY),
.S_AXI_arsize(axi_mem_intercon_to_s00_couplers_ARSIZE),
.S_AXI_arvalid(axi_mem_intercon_to_s00_couplers_ARVALID),
.S_AXI_awaddr(axi_mem_intercon_to_s00_couplers_AWADDR),
.S_AXI_awburst(axi_mem_intercon_to_s00_couplers_AWBURST),
.S_AXI_awcache(axi_mem_intercon_to_s00_couplers_AWCACHE),
.S_AXI_awlen(axi_mem_intercon_to_s00_couplers_AWLEN),
.S_AXI_awprot(axi_mem_intercon_to_s00_couplers_AWPROT),
.S_AXI_awready(axi_mem_intercon_to_s00_couplers_AWREADY),
.S_AXI_awsize(axi_mem_intercon_to_s00_couplers_AWSIZE),
.S_AXI_awvalid(axi_mem_intercon_to_s00_couplers_AWVALID),
.S_AXI_bready(axi_mem_intercon_to_s00_couplers_BREADY),
.S_AXI_bresp(axi_mem_intercon_to_s00_couplers_BRESP),
.S_AXI_bvalid(axi_mem_intercon_to_s00_couplers_BVALID),
.S_AXI_rdata(axi_mem_intercon_to_s00_couplers_RDATA),
.S_AXI_rlast(axi_mem_intercon_to_s00_couplers_RLAST),
.S_AXI_rready(axi_mem_intercon_to_s00_couplers_RREADY),
.S_AXI_rresp(axi_mem_intercon_to_s00_couplers_RRESP),
.S_AXI_rvalid(axi_mem_intercon_to_s00_couplers_RVALID),
.S_AXI_wdata(axi_mem_intercon_to_s00_couplers_WDATA),
.S_AXI_wlast(axi_mem_intercon_to_s00_couplers_WLAST),
.S_AXI_wready(axi_mem_intercon_to_s00_couplers_WREADY),
.S_AXI_wstrb(axi_mem_intercon_to_s00_couplers_WSTRB),
.S_AXI_wvalid(axi_mem_intercon_to_s00_couplers_WVALID));
design_1_xbar_2 xbar
(.aclk(axi_mem_intercon_ACLK_net),
.aresetn(axi_mem_intercon_ARESETN_net),
.m_axi_araddr({xbar_to_m01_couplers_ARADDR,xbar_to_m00_couplers_ARADDR}),
.m_axi_arburst({xbar_to_m01_couplers_ARBURST,xbar_to_m00_couplers_ARBURST}),
.m_axi_arcache({xbar_to_m01_couplers_ARCACHE,xbar_to_m00_couplers_ARCACHE}),
.m_axi_arlen({xbar_to_m01_couplers_ARLEN,xbar_to_m00_couplers_ARLEN}),
.m_axi_arlock({xbar_to_m01_couplers_ARLOCK,xbar_to_m00_couplers_ARLOCK}),
.m_axi_arprot({xbar_to_m01_couplers_ARPROT,xbar_to_m00_couplers_ARPROT}),
.m_axi_arqos({xbar_to_m01_couplers_ARQOS,xbar_to_m00_couplers_ARQOS}),
.m_axi_arready({xbar_to_m01_couplers_ARREADY,xbar_to_m00_couplers_ARREADY}),
.m_axi_arregion({xbar_to_m01_couplers_ARREGION,xbar_to_m00_couplers_ARREGION}),
.m_axi_arsize({xbar_to_m01_couplers_ARSIZE,xbar_to_m00_couplers_ARSIZE}),
.m_axi_arvalid({xbar_to_m01_couplers_ARVALID,xbar_to_m00_couplers_ARVALID}),
.m_axi_awaddr({xbar_to_m01_couplers_AWADDR,xbar_to_m00_couplers_AWADDR}),
.m_axi_awburst({xbar_to_m01_couplers_AWBURST,xbar_to_m00_couplers_AWBURST}),
.m_axi_awcache({xbar_to_m01_couplers_AWCACHE,xbar_to_m00_couplers_AWCACHE}),
.m_axi_awlen({xbar_to_m01_couplers_AWLEN,xbar_to_m00_couplers_AWLEN}),
.m_axi_awlock({xbar_to_m01_couplers_AWLOCK,xbar_to_m00_couplers_AWLOCK}),
.m_axi_awprot({xbar_to_m01_couplers_AWPROT,xbar_to_m00_couplers_AWPROT}),
.m_axi_awqos({xbar_to_m01_couplers_AWQOS,xbar_to_m00_couplers_AWQOS}),
.m_axi_awready({xbar_to_m01_couplers_AWREADY,xbar_to_m00_couplers_AWREADY}),
.m_axi_awregion({xbar_to_m01_couplers_AWREGION,xbar_to_m00_couplers_AWREGION}),
.m_axi_awsize({xbar_to_m01_couplers_AWSIZE,xbar_to_m00_couplers_AWSIZE}),
.m_axi_awvalid({xbar_to_m01_couplers_AWVALID,xbar_to_m00_couplers_AWVALID}),
.m_axi_bready({xbar_to_m01_couplers_BREADY,xbar_to_m00_couplers_BREADY}),
.m_axi_bresp({xbar_to_m01_couplers_BRESP,xbar_to_m00_couplers_BRESP}),
.m_axi_bvalid({xbar_to_m01_couplers_BVALID,xbar_to_m00_couplers_BVALID}),
.m_axi_rdata({xbar_to_m01_couplers_RDATA,xbar_to_m00_couplers_RDATA}),
.m_axi_rlast({xbar_to_m01_couplers_RLAST,xbar_to_m00_couplers_RLAST}),
.m_axi_rready({xbar_to_m01_couplers_RREADY,xbar_to_m00_couplers_RREADY}),
.m_axi_rresp({xbar_to_m01_couplers_RRESP,xbar_to_m00_couplers_RRESP}),
.m_axi_rvalid({xbar_to_m01_couplers_RVALID,xbar_to_m00_couplers_RVALID}),
.m_axi_wdata({xbar_to_m01_couplers_WDATA,xbar_to_m00_couplers_WDATA}),
.m_axi_wlast({xbar_to_m01_couplers_WLAST,xbar_to_m00_couplers_WLAST}),
.m_axi_wready({xbar_to_m01_couplers_WREADY,xbar_to_m00_couplers_WREADY}),
.m_axi_wstrb({xbar_to_m01_couplers_WSTRB,xbar_to_m00_couplers_WSTRB}),
.m_axi_wvalid({xbar_to_m01_couplers_WVALID,xbar_to_m00_couplers_WVALID}),
.s_axi_araddr(s00_couplers_to_xbar_ARADDR),
.s_axi_arburst(s00_couplers_to_xbar_ARBURST),
.s_axi_arcache(s00_couplers_to_xbar_ARCACHE),
.s_axi_arlen(s00_couplers_to_xbar_ARLEN),
.s_axi_arlock(s00_couplers_to_xbar_ARLOCK),
.s_axi_arprot(s00_couplers_to_xbar_ARPROT),
.s_axi_arqos(s00_couplers_to_xbar_ARQOS),
.s_axi_arready(s00_couplers_to_xbar_ARREADY),
.s_axi_arsize(s00_couplers_to_xbar_ARSIZE),
.s_axi_arvalid(s00_couplers_to_xbar_ARVALID),
.s_axi_awaddr(s00_couplers_to_xbar_AWADDR),
.s_axi_awburst(s00_couplers_to_xbar_AWBURST),
.s_axi_awcache(s00_couplers_to_xbar_AWCACHE),
.s_axi_awlen(s00_couplers_to_xbar_AWLEN),
.s_axi_awlock(s00_couplers_to_xbar_AWLOCK),
.s_axi_awprot(s00_couplers_to_xbar_AWPROT),
.s_axi_awqos(s00_couplers_to_xbar_AWQOS),
.s_axi_awready(s00_couplers_to_xbar_AWREADY),
.s_axi_awsize(s00_couplers_to_xbar_AWSIZE),
.s_axi_awvalid(s00_couplers_to_xbar_AWVALID),
.s_axi_bready(s00_couplers_to_xbar_BREADY),
.s_axi_bresp(s00_couplers_to_xbar_BRESP),
.s_axi_bvalid(s00_couplers_to_xbar_BVALID),
.s_axi_rdata(s00_couplers_to_xbar_RDATA),
.s_axi_rlast(s00_couplers_to_xbar_RLAST),
.s_axi_rready(s00_couplers_to_xbar_RREADY),
.s_axi_rresp(s00_couplers_to_xbar_RRESP),
.s_axi_rvalid(s00_couplers_to_xbar_RVALID),
.s_axi_wdata(s00_couplers_to_xbar_WDATA),
.s_axi_wlast(s00_couplers_to_xbar_WLAST),
.s_axi_wready(s00_couplers_to_xbar_WREADY),
.s_axi_wstrb(s00_couplers_to_xbar_WSTRB),
.s_axi_wvalid(s00_couplers_to_xbar_WVALID));
endmodule
module design_1_axi_mem_intercon_3
(ACLK,
ARESETN,
M00_ACLK,
M00_ARESETN,
M00_AXI_araddr,
M00_AXI_arburst,
M00_AXI_arcache,
M00_AXI_arlen,
M00_AXI_arlock,
M00_AXI_arprot,
M00_AXI_arqos,
M00_AXI_arready,
M00_AXI_arsize,
M00_AXI_arvalid,
M00_AXI_awaddr,
M00_AXI_awburst,
M00_AXI_awcache,
M00_AXI_awlen,
M00_AXI_awlock,
M00_AXI_awprot,
M00_AXI_awqos,
M00_AXI_awready,
M00_AXI_awsize,
M00_AXI_awvalid,
M00_AXI_bready,
M00_AXI_bresp,
M00_AXI_bvalid,
M00_AXI_rdata,
M00_AXI_rlast,
M00_AXI_rready,
M00_AXI_rresp,
M00_AXI_rvalid,
M00_AXI_wdata,
M00_AXI_wlast,
M00_AXI_wready,
M00_AXI_wstrb,
M00_AXI_wvalid,
M01_ACLK,
M01_ARESETN,
M01_AXI_araddr,
M01_AXI_arburst,
M01_AXI_arcache,
M01_AXI_arlen,
M01_AXI_arlock,
M01_AXI_arprot,
M01_AXI_arready,
M01_AXI_arsize,
M01_AXI_arvalid,
M01_AXI_awaddr,
M01_AXI_awburst,
M01_AXI_awcache,
M01_AXI_awlen,
M01_AXI_awlock,
M01_AXI_awprot,
M01_AXI_awready,
M01_AXI_awsize,
M01_AXI_awvalid,
M01_AXI_bready,
M01_AXI_bresp,
M01_AXI_bvalid,
M01_AXI_rdata,
M01_AXI_rlast,
M01_AXI_rready,
M01_AXI_rresp,
M01_AXI_rvalid,
M01_AXI_wdata,
M01_AXI_wlast,
M01_AXI_wready,
M01_AXI_wstrb,
M01_AXI_wvalid,
S00_ACLK,
S00_ARESETN,
S00_AXI_araddr,
S00_AXI_arburst,
S00_AXI_arcache,
S00_AXI_arlen,
S00_AXI_arprot,
S00_AXI_arready,
S00_AXI_arsize,
S00_AXI_arvalid,
S00_AXI_awaddr,
S00_AXI_awburst,
S00_AXI_awcache,
S00_AXI_awlen,
S00_AXI_awprot,
S00_AXI_awready,
S00_AXI_awsize,
S00_AXI_awvalid,
S00_AXI_bready,
S00_AXI_bresp,
S00_AXI_bvalid,
S00_AXI_rdata,
S00_AXI_rlast,
S00_AXI_rready,
S00_AXI_rresp,
S00_AXI_rvalid,
S00_AXI_wdata,
S00_AXI_wlast,
S00_AXI_wready,
S00_AXI_wstrb,
S00_AXI_wvalid);
input ACLK;
input ARESETN;
input M00_ACLK;
input M00_ARESETN;
output [31:0]M00_AXI_araddr;
output [1:0]M00_AXI_arburst;
output [3:0]M00_AXI_arcache;
output [3:0]M00_AXI_arlen;
output [1:0]M00_AXI_arlock;
output [2:0]M00_AXI_arprot;
output [3:0]M00_AXI_arqos;
input M00_AXI_arready;
output [2:0]M00_AXI_arsize;
output M00_AXI_arvalid;
output [31:0]M00_AXI_awaddr;
output [1:0]M00_AXI_awburst;
output [3:0]M00_AXI_awcache;
output [3:0]M00_AXI_awlen;
output [1:0]M00_AXI_awlock;
output [2:0]M00_AXI_awprot;
output [3:0]M00_AXI_awqos;
input M00_AXI_awready;
output [2:0]M00_AXI_awsize;
output M00_AXI_awvalid;
output M00_AXI_bready;
input [1:0]M00_AXI_bresp;
input M00_AXI_bvalid;
input [63:0]M00_AXI_rdata;
input M00_AXI_rlast;
output M00_AXI_rready;
input [1:0]M00_AXI_rresp;
input M00_AXI_rvalid;
output [63:0]M00_AXI_wdata;
output M00_AXI_wlast;
input M00_AXI_wready;
output [7:0]M00_AXI_wstrb;
output M00_AXI_wvalid;
input M01_ACLK;
input M01_ARESETN;
output [12:0]M01_AXI_araddr;
output [1:0]M01_AXI_arburst;
output [3:0]M01_AXI_arcache;
output [7:0]M01_AXI_arlen;
output [0:0]M01_AXI_arlock;
output [2:0]M01_AXI_arprot;
input M01_AXI_arready;
output [2:0]M01_AXI_arsize;
output M01_AXI_arvalid;
output [12:0]M01_AXI_awaddr;
output [1:0]M01_AXI_awburst;
output [3:0]M01_AXI_awcache;
output [7:0]M01_AXI_awlen;
output [0:0]M01_AXI_awlock;
output [2:0]M01_AXI_awprot;
input M01_AXI_awready;
output [2:0]M01_AXI_awsize;
output M01_AXI_awvalid;
output M01_AXI_bready;
input [1:0]M01_AXI_bresp;
input M01_AXI_bvalid;
input [31:0]M01_AXI_rdata;
input M01_AXI_rlast;
output M01_AXI_rready;
input [1:0]M01_AXI_rresp;
input M01_AXI_rvalid;
output [31:0]M01_AXI_wdata;
output M01_AXI_wlast;
input M01_AXI_wready;
output [3:0]M01_AXI_wstrb;
output M01_AXI_wvalid;
input S00_ACLK;
input S00_ARESETN;
input [31:0]S00_AXI_araddr;
input [1:0]S00_AXI_arburst;
input [3:0]S00_AXI_arcache;
input [7:0]S00_AXI_arlen;
input [2:0]S00_AXI_arprot;
output S00_AXI_arready;
input [2:0]S00_AXI_arsize;
input S00_AXI_arvalid;
input [31:0]S00_AXI_awaddr;
input [1:0]S00_AXI_awburst;
input [3:0]S00_AXI_awcache;
input [7:0]S00_AXI_awlen;
input [2:0]S00_AXI_awprot;
output S00_AXI_awready;
input [2:0]S00_AXI_awsize;
input S00_AXI_awvalid;
input S00_AXI_bready;
output [1:0]S00_AXI_bresp;
output S00_AXI_bvalid;
output [31:0]S00_AXI_rdata;
output S00_AXI_rlast;
input S00_AXI_rready;
output [1:0]S00_AXI_rresp;
output S00_AXI_rvalid;
input [31:0]S00_AXI_wdata;
input S00_AXI_wlast;
output S00_AXI_wready;
input [3:0]S00_AXI_wstrb;
input S00_AXI_wvalid;
wire M00_ACLK_1;
wire M00_ARESETN_1;
wire M01_ACLK_1;
wire M01_ARESETN_1;
wire S00_ACLK_1;
wire S00_ARESETN_1;
wire axi_mem_intercon_ACLK_net;
wire axi_mem_intercon_ARESETN_net;
wire [31:0]axi_mem_intercon_to_s00_couplers_ARADDR;
wire [1:0]axi_mem_intercon_to_s00_couplers_ARBURST;
wire [3:0]axi_mem_intercon_to_s00_couplers_ARCACHE;
wire [7:0]axi_mem_intercon_to_s00_couplers_ARLEN;
wire [2:0]axi_mem_intercon_to_s00_couplers_ARPROT;
wire axi_mem_intercon_to_s00_couplers_ARREADY;
wire [2:0]axi_mem_intercon_to_s00_couplers_ARSIZE;
wire axi_mem_intercon_to_s00_couplers_ARVALID;
wire [31:0]axi_mem_intercon_to_s00_couplers_AWADDR;
wire [1:0]axi_mem_intercon_to_s00_couplers_AWBURST;
wire [3:0]axi_mem_intercon_to_s00_couplers_AWCACHE;
wire [7:0]axi_mem_intercon_to_s00_couplers_AWLEN;
wire [2:0]axi_mem_intercon_to_s00_couplers_AWPROT;
wire axi_mem_intercon_to_s00_couplers_AWREADY;
wire [2:0]axi_mem_intercon_to_s00_couplers_AWSIZE;
wire axi_mem_intercon_to_s00_couplers_AWVALID;
wire axi_mem_intercon_to_s00_couplers_BREADY;
wire [1:0]axi_mem_intercon_to_s00_couplers_BRESP;
wire axi_mem_intercon_to_s00_couplers_BVALID;
wire [31:0]axi_mem_intercon_to_s00_couplers_RDATA;
wire axi_mem_intercon_to_s00_couplers_RLAST;
wire axi_mem_intercon_to_s00_couplers_RREADY;
wire [1:0]axi_mem_intercon_to_s00_couplers_RRESP;
wire axi_mem_intercon_to_s00_couplers_RVALID;
wire [31:0]axi_mem_intercon_to_s00_couplers_WDATA;
wire axi_mem_intercon_to_s00_couplers_WLAST;
wire axi_mem_intercon_to_s00_couplers_WREADY;
wire [3:0]axi_mem_intercon_to_s00_couplers_WSTRB;
wire axi_mem_intercon_to_s00_couplers_WVALID;
wire [31:0]m00_couplers_to_axi_mem_intercon_ARADDR;
wire [1:0]m00_couplers_to_axi_mem_intercon_ARBURST;
wire [3:0]m00_couplers_to_axi_mem_intercon_ARCACHE;
wire [3:0]m00_couplers_to_axi_mem_intercon_ARLEN;
wire [1:0]m00_couplers_to_axi_mem_intercon_ARLOCK;
wire [2:0]m00_couplers_to_axi_mem_intercon_ARPROT;
wire [3:0]m00_couplers_to_axi_mem_intercon_ARQOS;
wire m00_couplers_to_axi_mem_intercon_ARREADY;
wire [2:0]m00_couplers_to_axi_mem_intercon_ARSIZE;
wire m00_couplers_to_axi_mem_intercon_ARVALID;
wire [31:0]m00_couplers_to_axi_mem_intercon_AWADDR;
wire [1:0]m00_couplers_to_axi_mem_intercon_AWBURST;
wire [3:0]m00_couplers_to_axi_mem_intercon_AWCACHE;
wire [3:0]m00_couplers_to_axi_mem_intercon_AWLEN;
wire [1:0]m00_couplers_to_axi_mem_intercon_AWLOCK;
wire [2:0]m00_couplers_to_axi_mem_intercon_AWPROT;
wire [3:0]m00_couplers_to_axi_mem_intercon_AWQOS;
wire m00_couplers_to_axi_mem_intercon_AWREADY;
wire [2:0]m00_couplers_to_axi_mem_intercon_AWSIZE;
wire m00_couplers_to_axi_mem_intercon_AWVALID;
wire m00_couplers_to_axi_mem_intercon_BREADY;
wire [1:0]m00_couplers_to_axi_mem_intercon_BRESP;
wire m00_couplers_to_axi_mem_intercon_BVALID;
wire [63:0]m00_couplers_to_axi_mem_intercon_RDATA;
wire m00_couplers_to_axi_mem_intercon_RLAST;
wire m00_couplers_to_axi_mem_intercon_RREADY;
wire [1:0]m00_couplers_to_axi_mem_intercon_RRESP;
wire m00_couplers_to_axi_mem_intercon_RVALID;
wire [63:0]m00_couplers_to_axi_mem_intercon_WDATA;
wire m00_couplers_to_axi_mem_intercon_WLAST;
wire m00_couplers_to_axi_mem_intercon_WREADY;
wire [7:0]m00_couplers_to_axi_mem_intercon_WSTRB;
wire m00_couplers_to_axi_mem_intercon_WVALID;
wire [12:0]m01_couplers_to_axi_mem_intercon_ARADDR;
wire [1:0]m01_couplers_to_axi_mem_intercon_ARBURST;
wire [3:0]m01_couplers_to_axi_mem_intercon_ARCACHE;
wire [7:0]m01_couplers_to_axi_mem_intercon_ARLEN;
wire [0:0]m01_couplers_to_axi_mem_intercon_ARLOCK;
wire [2:0]m01_couplers_to_axi_mem_intercon_ARPROT;
wire m01_couplers_to_axi_mem_intercon_ARREADY;
wire [2:0]m01_couplers_to_axi_mem_intercon_ARSIZE;
wire m01_couplers_to_axi_mem_intercon_ARVALID;
wire [12:0]m01_couplers_to_axi_mem_intercon_AWADDR;
wire [1:0]m01_couplers_to_axi_mem_intercon_AWBURST;
wire [3:0]m01_couplers_to_axi_mem_intercon_AWCACHE;
wire [7:0]m01_couplers_to_axi_mem_intercon_AWLEN;
wire [0:0]m01_couplers_to_axi_mem_intercon_AWLOCK;
wire [2:0]m01_couplers_to_axi_mem_intercon_AWPROT;
wire m01_couplers_to_axi_mem_intercon_AWREADY;
wire [2:0]m01_couplers_to_axi_mem_intercon_AWSIZE;
wire m01_couplers_to_axi_mem_intercon_AWVALID;
wire m01_couplers_to_axi_mem_intercon_BREADY;
wire [1:0]m01_couplers_to_axi_mem_intercon_BRESP;
wire m01_couplers_to_axi_mem_intercon_BVALID;
wire [31:0]m01_couplers_to_axi_mem_intercon_RDATA;
wire m01_couplers_to_axi_mem_intercon_RLAST;
wire m01_couplers_to_axi_mem_intercon_RREADY;
wire [1:0]m01_couplers_to_axi_mem_intercon_RRESP;
wire m01_couplers_to_axi_mem_intercon_RVALID;
wire [31:0]m01_couplers_to_axi_mem_intercon_WDATA;
wire m01_couplers_to_axi_mem_intercon_WLAST;
wire m01_couplers_to_axi_mem_intercon_WREADY;
wire [3:0]m01_couplers_to_axi_mem_intercon_WSTRB;
wire m01_couplers_to_axi_mem_intercon_WVALID;
wire [31:0]s00_couplers_to_xbar_ARADDR;
wire [1:0]s00_couplers_to_xbar_ARBURST;
wire [3:0]s00_couplers_to_xbar_ARCACHE;
wire [7:0]s00_couplers_to_xbar_ARLEN;
wire [0:0]s00_couplers_to_xbar_ARLOCK;
wire [2:0]s00_couplers_to_xbar_ARPROT;
wire [3:0]s00_couplers_to_xbar_ARQOS;
wire [0:0]s00_couplers_to_xbar_ARREADY;
wire [2:0]s00_couplers_to_xbar_ARSIZE;
wire s00_couplers_to_xbar_ARVALID;
wire [31:0]s00_couplers_to_xbar_AWADDR;
wire [1:0]s00_couplers_to_xbar_AWBURST;
wire [3:0]s00_couplers_to_xbar_AWCACHE;
wire [7:0]s00_couplers_to_xbar_AWLEN;
wire [0:0]s00_couplers_to_xbar_AWLOCK;
wire [2:0]s00_couplers_to_xbar_AWPROT;
wire [3:0]s00_couplers_to_xbar_AWQOS;
wire [0:0]s00_couplers_to_xbar_AWREADY;
wire [2:0]s00_couplers_to_xbar_AWSIZE;
wire s00_couplers_to_xbar_AWVALID;
wire s00_couplers_to_xbar_BREADY;
wire [1:0]s00_couplers_to_xbar_BRESP;
wire [0:0]s00_couplers_to_xbar_BVALID;
wire [63:0]s00_couplers_to_xbar_RDATA;
wire [0:0]s00_couplers_to_xbar_RLAST;
wire s00_couplers_to_xbar_RREADY;
wire [1:0]s00_couplers_to_xbar_RRESP;
wire [0:0]s00_couplers_to_xbar_RVALID;
wire [63:0]s00_couplers_to_xbar_WDATA;
wire s00_couplers_to_xbar_WLAST;
wire [0:0]s00_couplers_to_xbar_WREADY;
wire [7:0]s00_couplers_to_xbar_WSTRB;
wire s00_couplers_to_xbar_WVALID;
wire [31:0]xbar_to_m00_couplers_ARADDR;
wire [1:0]xbar_to_m00_couplers_ARBURST;
wire [3:0]xbar_to_m00_couplers_ARCACHE;
wire [7:0]xbar_to_m00_couplers_ARLEN;
wire [0:0]xbar_to_m00_couplers_ARLOCK;
wire [2:0]xbar_to_m00_couplers_ARPROT;
wire [3:0]xbar_to_m00_couplers_ARQOS;
wire xbar_to_m00_couplers_ARREADY;
wire [3:0]xbar_to_m00_couplers_ARREGION;
wire [2:0]xbar_to_m00_couplers_ARSIZE;
wire [0:0]xbar_to_m00_couplers_ARVALID;
wire [31:0]xbar_to_m00_couplers_AWADDR;
wire [1:0]xbar_to_m00_couplers_AWBURST;
wire [3:0]xbar_to_m00_couplers_AWCACHE;
wire [7:0]xbar_to_m00_couplers_AWLEN;
wire [0:0]xbar_to_m00_couplers_AWLOCK;
wire [2:0]xbar_to_m00_couplers_AWPROT;
wire [3:0]xbar_to_m00_couplers_AWQOS;
wire xbar_to_m00_couplers_AWREADY;
wire [3:0]xbar_to_m00_couplers_AWREGION;
wire [2:0]xbar_to_m00_couplers_AWSIZE;
wire [0:0]xbar_to_m00_couplers_AWVALID;
wire [0:0]xbar_to_m00_couplers_BREADY;
wire [1:0]xbar_to_m00_couplers_BRESP;
wire xbar_to_m00_couplers_BVALID;
wire [63:0]xbar_to_m00_couplers_RDATA;
wire xbar_to_m00_couplers_RLAST;
wire [0:0]xbar_to_m00_couplers_RREADY;
wire [1:0]xbar_to_m00_couplers_RRESP;
wire xbar_to_m00_couplers_RVALID;
wire [63:0]xbar_to_m00_couplers_WDATA;
wire [0:0]xbar_to_m00_couplers_WLAST;
wire xbar_to_m00_couplers_WREADY;
wire [7:0]xbar_to_m00_couplers_WSTRB;
wire [0:0]xbar_to_m00_couplers_WVALID;
wire [63:32]xbar_to_m01_couplers_ARADDR;
wire [3:2]xbar_to_m01_couplers_ARBURST;
wire [7:4]xbar_to_m01_couplers_ARCACHE;
wire [15:8]xbar_to_m01_couplers_ARLEN;
wire [1:1]xbar_to_m01_couplers_ARLOCK;
wire [5:3]xbar_to_m01_couplers_ARPROT;
wire [7:4]xbar_to_m01_couplers_ARQOS;
wire xbar_to_m01_couplers_ARREADY;
wire [7:4]xbar_to_m01_couplers_ARREGION;
wire [5:3]xbar_to_m01_couplers_ARSIZE;
wire [1:1]xbar_to_m01_couplers_ARVALID;
wire [63:32]xbar_to_m01_couplers_AWADDR;
wire [3:2]xbar_to_m01_couplers_AWBURST;
wire [7:4]xbar_to_m01_couplers_AWCACHE;
wire [15:8]xbar_to_m01_couplers_AWLEN;
wire [1:1]xbar_to_m01_couplers_AWLOCK;
wire [5:3]xbar_to_m01_couplers_AWPROT;
wire [7:4]xbar_to_m01_couplers_AWQOS;
wire xbar_to_m01_couplers_AWREADY;
wire [7:4]xbar_to_m01_couplers_AWREGION;
wire [5:3]xbar_to_m01_couplers_AWSIZE;
wire [1:1]xbar_to_m01_couplers_AWVALID;
wire [1:1]xbar_to_m01_couplers_BREADY;
wire [1:0]xbar_to_m01_couplers_BRESP;
wire xbar_to_m01_couplers_BVALID;
wire [63:0]xbar_to_m01_couplers_RDATA;
wire xbar_to_m01_couplers_RLAST;
wire [1:1]xbar_to_m01_couplers_RREADY;
wire [1:0]xbar_to_m01_couplers_RRESP;
wire xbar_to_m01_couplers_RVALID;
wire [127:64]xbar_to_m01_couplers_WDATA;
wire [1:1]xbar_to_m01_couplers_WLAST;
wire xbar_to_m01_couplers_WREADY;
wire [15:8]xbar_to_m01_couplers_WSTRB;
wire [1:1]xbar_to_m01_couplers_WVALID;
assign M00_ACLK_1 = M00_ACLK;
assign M00_ARESETN_1 = M00_ARESETN;
assign M00_AXI_araddr[31:0] = m00_couplers_to_axi_mem_intercon_ARADDR;
assign M00_AXI_arburst[1:0] = m00_couplers_to_axi_mem_intercon_ARBURST;
assign M00_AXI_arcache[3:0] = m00_couplers_to_axi_mem_intercon_ARCACHE;
assign M00_AXI_arlen[3:0] = m00_couplers_to_axi_mem_intercon_ARLEN;
assign M00_AXI_arlock[1:0] = m00_couplers_to_axi_mem_intercon_ARLOCK;
assign M00_AXI_arprot[2:0] = m00_couplers_to_axi_mem_intercon_ARPROT;
assign M00_AXI_arqos[3:0] = m00_couplers_to_axi_mem_intercon_ARQOS;
assign M00_AXI_arsize[2:0] = m00_couplers_to_axi_mem_intercon_ARSIZE;
assign M00_AXI_arvalid = m00_couplers_to_axi_mem_intercon_ARVALID;
assign M00_AXI_awaddr[31:0] = m00_couplers_to_axi_mem_intercon_AWADDR;
assign M00_AXI_awburst[1:0] = m00_couplers_to_axi_mem_intercon_AWBURST;
assign M00_AXI_awcache[3:0] = m00_couplers_to_axi_mem_intercon_AWCACHE;
assign M00_AXI_awlen[3:0] = m00_couplers_to_axi_mem_intercon_AWLEN;
assign M00_AXI_awlock[1:0] = m00_couplers_to_axi_mem_intercon_AWLOCK;
assign M00_AXI_awprot[2:0] = m00_couplers_to_axi_mem_intercon_AWPROT;
assign M00_AXI_awqos[3:0] = m00_couplers_to_axi_mem_intercon_AWQOS;
assign M00_AXI_awsize[2:0] = m00_couplers_to_axi_mem_intercon_AWSIZE;
assign M00_AXI_awvalid = m00_couplers_to_axi_mem_intercon_AWVALID;
assign M00_AXI_bready = m00_couplers_to_axi_mem_intercon_BREADY;
assign M00_AXI_rready = m00_couplers_to_axi_mem_intercon_RREADY;
assign M00_AXI_wdata[63:0] = m00_couplers_to_axi_mem_intercon_WDATA;
assign M00_AXI_wlast = m00_couplers_to_axi_mem_intercon_WLAST;
assign M00_AXI_wstrb[7:0] = m00_couplers_to_axi_mem_intercon_WSTRB;
assign M00_AXI_wvalid = m00_couplers_to_axi_mem_intercon_WVALID;
assign M01_ACLK_1 = M01_ACLK;
assign M01_ARESETN_1 = M01_ARESETN;
assign M01_AXI_araddr[12:0] = m01_couplers_to_axi_mem_intercon_ARADDR;
assign M01_AXI_arburst[1:0] = m01_couplers_to_axi_mem_intercon_ARBURST;
assign M01_AXI_arcache[3:0] = m01_couplers_to_axi_mem_intercon_ARCACHE;
assign M01_AXI_arlen[7:0] = m01_couplers_to_axi_mem_intercon_ARLEN;
assign M01_AXI_arlock[0] = m01_couplers_to_axi_mem_intercon_ARLOCK;
assign M01_AXI_arprot[2:0] = m01_couplers_to_axi_mem_intercon_ARPROT;
assign M01_AXI_arsize[2:0] = m01_couplers_to_axi_mem_intercon_ARSIZE;
assign M01_AXI_arvalid = m01_couplers_to_axi_mem_intercon_ARVALID;
assign M01_AXI_awaddr[12:0] = m01_couplers_to_axi_mem_intercon_AWADDR;
assign M01_AXI_awburst[1:0] = m01_couplers_to_axi_mem_intercon_AWBURST;
assign M01_AXI_awcache[3:0] = m01_couplers_to_axi_mem_intercon_AWCACHE;
assign M01_AXI_awlen[7:0] = m01_couplers_to_axi_mem_intercon_AWLEN;
assign M01_AXI_awlock[0] = m01_couplers_to_axi_mem_intercon_AWLOCK;
assign M01_AXI_awprot[2:0] = m01_couplers_to_axi_mem_intercon_AWPROT;
assign M01_AXI_awsize[2:0] = m01_couplers_to_axi_mem_intercon_AWSIZE;
assign M01_AXI_awvalid = m01_couplers_to_axi_mem_intercon_AWVALID;
assign M01_AXI_bready = m01_couplers_to_axi_mem_intercon_BREADY;
assign M01_AXI_rready = m01_couplers_to_axi_mem_intercon_RREADY;
assign M01_AXI_wdata[31:0] = m01_couplers_to_axi_mem_intercon_WDATA;
assign M01_AXI_wlast = m01_couplers_to_axi_mem_intercon_WLAST;
assign M01_AXI_wstrb[3:0] = m01_couplers_to_axi_mem_intercon_WSTRB;
assign M01_AXI_wvalid = m01_couplers_to_axi_mem_intercon_WVALID;
assign S00_ACLK_1 = S00_ACLK;
assign S00_ARESETN_1 = S00_ARESETN;
assign S00_AXI_arready = axi_mem_intercon_to_s00_couplers_ARREADY;
assign S00_AXI_awready = axi_mem_intercon_to_s00_couplers_AWREADY;
assign S00_AXI_bresp[1:0] = axi_mem_intercon_to_s00_couplers_BRESP;
assign S00_AXI_bvalid = axi_mem_intercon_to_s00_couplers_BVALID;
assign S00_AXI_rdata[31:0] = axi_mem_intercon_to_s00_couplers_RDATA;
assign S00_AXI_rlast = axi_mem_intercon_to_s00_couplers_RLAST;
assign S00_AXI_rresp[1:0] = axi_mem_intercon_to_s00_couplers_RRESP;
assign S00_AXI_rvalid = axi_mem_intercon_to_s00_couplers_RVALID;
assign S00_AXI_wready = axi_mem_intercon_to_s00_couplers_WREADY;
assign axi_mem_intercon_ACLK_net = ACLK;
assign axi_mem_intercon_ARESETN_net = ARESETN;
assign axi_mem_intercon_to_s00_couplers_ARADDR = S00_AXI_araddr[31:0];
assign axi_mem_intercon_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0];
assign axi_mem_intercon_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0];
assign axi_mem_intercon_to_s00_couplers_ARLEN = S00_AXI_arlen[7:0];
assign axi_mem_intercon_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0];
assign axi_mem_intercon_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0];
assign axi_mem_intercon_to_s00_couplers_ARVALID = S00_AXI_arvalid;
assign axi_mem_intercon_to_s00_couplers_AWADDR = S00_AXI_awaddr[31:0];
assign axi_mem_intercon_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0];
assign axi_mem_intercon_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0];
assign axi_mem_intercon_to_s00_couplers_AWLEN = S00_AXI_awlen[7:0];
assign axi_mem_intercon_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0];
assign axi_mem_intercon_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0];
assign axi_mem_intercon_to_s00_couplers_AWVALID = S00_AXI_awvalid;
assign axi_mem_intercon_to_s00_couplers_BREADY = S00_AXI_bready;
assign axi_mem_intercon_to_s00_couplers_RREADY = S00_AXI_rready;
assign axi_mem_intercon_to_s00_couplers_WDATA = S00_AXI_wdata[31:0];
assign axi_mem_intercon_to_s00_couplers_WLAST = S00_AXI_wlast;
assign axi_mem_intercon_to_s00_couplers_WSTRB = S00_AXI_wstrb[3:0];
assign axi_mem_intercon_to_s00_couplers_WVALID = S00_AXI_wvalid;
assign m00_couplers_to_axi_mem_intercon_ARREADY = M00_AXI_arready;
assign m00_couplers_to_axi_mem_intercon_AWREADY = M00_AXI_awready;
assign m00_couplers_to_axi_mem_intercon_BRESP = M00_AXI_bresp[1:0];
assign m00_couplers_to_axi_mem_intercon_BVALID = M00_AXI_bvalid;
assign m00_couplers_to_axi_mem_intercon_RDATA = M00_AXI_rdata[63:0];
assign m00_couplers_to_axi_mem_intercon_RLAST = M00_AXI_rlast;
assign m00_couplers_to_axi_mem_intercon_RRESP = M00_AXI_rresp[1:0];
assign m00_couplers_to_axi_mem_intercon_RVALID = M00_AXI_rvalid;
assign m00_couplers_to_axi_mem_intercon_WREADY = M00_AXI_wready;
assign m01_couplers_to_axi_mem_intercon_ARREADY = M01_AXI_arready;
assign m01_couplers_to_axi_mem_intercon_AWREADY = M01_AXI_awready;
assign m01_couplers_to_axi_mem_intercon_BRESP = M01_AXI_bresp[1:0];
assign m01_couplers_to_axi_mem_intercon_BVALID = M01_AXI_bvalid;
assign m01_couplers_to_axi_mem_intercon_RDATA = M01_AXI_rdata[31:0];
assign m01_couplers_to_axi_mem_intercon_RLAST = M01_AXI_rlast;
assign m01_couplers_to_axi_mem_intercon_RRESP = M01_AXI_rresp[1:0];
assign m01_couplers_to_axi_mem_intercon_RVALID = M01_AXI_rvalid;
assign m01_couplers_to_axi_mem_intercon_WREADY = M01_AXI_wready;
m00_couplers_imp_MBTM83 m00_couplers
(.M_ACLK(M00_ACLK_1),
.M_ARESETN(M00_ARESETN_1),
.M_AXI_araddr(m00_couplers_to_axi_mem_intercon_ARADDR),
.M_AXI_arburst(m00_couplers_to_axi_mem_intercon_ARBURST),
.M_AXI_arcache(m00_couplers_to_axi_mem_intercon_ARCACHE),
.M_AXI_arlen(m00_couplers_to_axi_mem_intercon_ARLEN),
.M_AXI_arlock(m00_couplers_to_axi_mem_intercon_ARLOCK),
.M_AXI_arprot(m00_couplers_to_axi_mem_intercon_ARPROT),
.M_AXI_arqos(m00_couplers_to_axi_mem_intercon_ARQOS),
.M_AXI_arready(m00_couplers_to_axi_mem_intercon_ARREADY),
.M_AXI_arsize(m00_couplers_to_axi_mem_intercon_ARSIZE),
.M_AXI_arvalid(m00_couplers_to_axi_mem_intercon_ARVALID),
.M_AXI_awaddr(m00_couplers_to_axi_mem_intercon_AWADDR),
.M_AXI_awburst(m00_couplers_to_axi_mem_intercon_AWBURST),
.M_AXI_awcache(m00_couplers_to_axi_mem_intercon_AWCACHE),
.M_AXI_awlen(m00_couplers_to_axi_mem_intercon_AWLEN),
.M_AXI_awlock(m00_couplers_to_axi_mem_intercon_AWLOCK),
.M_AXI_awprot(m00_couplers_to_axi_mem_intercon_AWPROT),
.M_AXI_awqos(m00_couplers_to_axi_mem_intercon_AWQOS),
.M_AXI_awready(m00_couplers_to_axi_mem_intercon_AWREADY),
.M_AXI_awsize(m00_couplers_to_axi_mem_intercon_AWSIZE),
.M_AXI_awvalid(m00_couplers_to_axi_mem_intercon_AWVALID),
.M_AXI_bready(m00_couplers_to_axi_mem_intercon_BREADY),
.M_AXI_bresp(m00_couplers_to_axi_mem_intercon_BRESP),
.M_AXI_bvalid(m00_couplers_to_axi_mem_intercon_BVALID),
.M_AXI_rdata(m00_couplers_to_axi_mem_intercon_RDATA),
.M_AXI_rlast(m00_couplers_to_axi_mem_intercon_RLAST),
.M_AXI_rready(m00_couplers_to_axi_mem_intercon_RREADY),
.M_AXI_rresp(m00_couplers_to_axi_mem_intercon_RRESP),
.M_AXI_rvalid(m00_couplers_to_axi_mem_intercon_RVALID),
.M_AXI_wdata(m00_couplers_to_axi_mem_intercon_WDATA),
.M_AXI_wlast(m00_couplers_to_axi_mem_intercon_WLAST),
.M_AXI_wready(m00_couplers_to_axi_mem_intercon_WREADY),
.M_AXI_wstrb(m00_couplers_to_axi_mem_intercon_WSTRB),
.M_AXI_wvalid(m00_couplers_to_axi_mem_intercon_WVALID),
.S_ACLK(axi_mem_intercon_ACLK_net),
.S_ARESETN(axi_mem_intercon_ARESETN_net),
.S_AXI_araddr(xbar_to_m00_couplers_ARADDR),
.S_AXI_arburst(xbar_to_m00_couplers_ARBURST),
.S_AXI_arcache(xbar_to_m00_couplers_ARCACHE),
.S_AXI_arlen(xbar_to_m00_couplers_ARLEN),
.S_AXI_arlock(xbar_to_m00_couplers_ARLOCK),
.S_AXI_arprot(xbar_to_m00_couplers_ARPROT),
.S_AXI_arqos(xbar_to_m00_couplers_ARQOS),
.S_AXI_arready(xbar_to_m00_couplers_ARREADY),
.S_AXI_arregion(xbar_to_m00_couplers_ARREGION),
.S_AXI_arsize(xbar_to_m00_couplers_ARSIZE),
.S_AXI_arvalid(xbar_to_m00_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m00_couplers_AWADDR),
.S_AXI_awburst(xbar_to_m00_couplers_AWBURST),
.S_AXI_awcache(xbar_to_m00_couplers_AWCACHE),
.S_AXI_awlen(xbar_to_m00_couplers_AWLEN),
.S_AXI_awlock(xbar_to_m00_couplers_AWLOCK),
.S_AXI_awprot(xbar_to_m00_couplers_AWPROT),
.S_AXI_awqos(xbar_to_m00_couplers_AWQOS),
.S_AXI_awready(xbar_to_m00_couplers_AWREADY),
.S_AXI_awregion(xbar_to_m00_couplers_AWREGION),
.S_AXI_awsize(xbar_to_m00_couplers_AWSIZE),
.S_AXI_awvalid(xbar_to_m00_couplers_AWVALID),
.S_AXI_bready(xbar_to_m00_couplers_BREADY),
.S_AXI_bresp(xbar_to_m00_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m00_couplers_BVALID),
.S_AXI_rdata(xbar_to_m00_couplers_RDATA),
.S_AXI_rlast(xbar_to_m00_couplers_RLAST),
.S_AXI_rready(xbar_to_m00_couplers_RREADY),
.S_AXI_rresp(xbar_to_m00_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m00_couplers_RVALID),
.S_AXI_wdata(xbar_to_m00_couplers_WDATA),
.S_AXI_wlast(xbar_to_m00_couplers_WLAST),
.S_AXI_wready(xbar_to_m00_couplers_WREADY),
.S_AXI_wstrb(xbar_to_m00_couplers_WSTRB),
.S_AXI_wvalid(xbar_to_m00_couplers_WVALID));
m01_couplers_imp_1H1JSWY m01_couplers
(.M_ACLK(M01_ACLK_1),
.M_ARESETN(M01_ARESETN_1),
.M_AXI_araddr(m01_couplers_to_axi_mem_intercon_ARADDR),
.M_AXI_arburst(m01_couplers_to_axi_mem_intercon_ARBURST),
.M_AXI_arcache(m01_couplers_to_axi_mem_intercon_ARCACHE),
.M_AXI_arlen(m01_couplers_to_axi_mem_intercon_ARLEN),
.M_AXI_arlock(m01_couplers_to_axi_mem_intercon_ARLOCK),
.M_AXI_arprot(m01_couplers_to_axi_mem_intercon_ARPROT),
.M_AXI_arready(m01_couplers_to_axi_mem_intercon_ARREADY),
.M_AXI_arsize(m01_couplers_to_axi_mem_intercon_ARSIZE),
.M_AXI_arvalid(m01_couplers_to_axi_mem_intercon_ARVALID),
.M_AXI_awaddr(m01_couplers_to_axi_mem_intercon_AWADDR),
.M_AXI_awburst(m01_couplers_to_axi_mem_intercon_AWBURST),
.M_AXI_awcache(m01_couplers_to_axi_mem_intercon_AWCACHE),
.M_AXI_awlen(m01_couplers_to_axi_mem_intercon_AWLEN),
.M_AXI_awlock(m01_couplers_to_axi_mem_intercon_AWLOCK),
.M_AXI_awprot(m01_couplers_to_axi_mem_intercon_AWPROT),
.M_AXI_awready(m01_couplers_to_axi_mem_intercon_AWREADY),
.M_AXI_awsize(m01_couplers_to_axi_mem_intercon_AWSIZE),
.M_AXI_awvalid(m01_couplers_to_axi_mem_intercon_AWVALID),
.M_AXI_bready(m01_couplers_to_axi_mem_intercon_BREADY),
.M_AXI_bresp(m01_couplers_to_axi_mem_intercon_BRESP),
.M_AXI_bvalid(m01_couplers_to_axi_mem_intercon_BVALID),
.M_AXI_rdata(m01_couplers_to_axi_mem_intercon_RDATA),
.M_AXI_rlast(m01_couplers_to_axi_mem_intercon_RLAST),
.M_AXI_rready(m01_couplers_to_axi_mem_intercon_RREADY),
.M_AXI_rresp(m01_couplers_to_axi_mem_intercon_RRESP),
.M_AXI_rvalid(m01_couplers_to_axi_mem_intercon_RVALID),
.M_AXI_wdata(m01_couplers_to_axi_mem_intercon_WDATA),
.M_AXI_wlast(m01_couplers_to_axi_mem_intercon_WLAST),
.M_AXI_wready(m01_couplers_to_axi_mem_intercon_WREADY),
.M_AXI_wstrb(m01_couplers_to_axi_mem_intercon_WSTRB),
.M_AXI_wvalid(m01_couplers_to_axi_mem_intercon_WVALID),
.S_ACLK(axi_mem_intercon_ACLK_net),
.S_ARESETN(axi_mem_intercon_ARESETN_net),
.S_AXI_araddr(xbar_to_m01_couplers_ARADDR),
.S_AXI_arburst(xbar_to_m01_couplers_ARBURST),
.S_AXI_arcache(xbar_to_m01_couplers_ARCACHE),
.S_AXI_arlen(xbar_to_m01_couplers_ARLEN),
.S_AXI_arlock(xbar_to_m01_couplers_ARLOCK),
.S_AXI_arprot(xbar_to_m01_couplers_ARPROT),
.S_AXI_arqos(xbar_to_m01_couplers_ARQOS),
.S_AXI_arready(xbar_to_m01_couplers_ARREADY),
.S_AXI_arregion(xbar_to_m01_couplers_ARREGION),
.S_AXI_arsize(xbar_to_m01_couplers_ARSIZE),
.S_AXI_arvalid(xbar_to_m01_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m01_couplers_AWADDR),
.S_AXI_awburst(xbar_to_m01_couplers_AWBURST),
.S_AXI_awcache(xbar_to_m01_couplers_AWCACHE),
.S_AXI_awlen(xbar_to_m01_couplers_AWLEN),
.S_AXI_awlock(xbar_to_m01_couplers_AWLOCK),
.S_AXI_awprot(xbar_to_m01_couplers_AWPROT),
.S_AXI_awqos(xbar_to_m01_couplers_AWQOS),
.S_AXI_awready(xbar_to_m01_couplers_AWREADY),
.S_AXI_awregion(xbar_to_m01_couplers_AWREGION),
.S_AXI_awsize(xbar_to_m01_couplers_AWSIZE),
.S_AXI_awvalid(xbar_to_m01_couplers_AWVALID),
.S_AXI_bready(xbar_to_m01_couplers_BREADY),
.S_AXI_bresp(xbar_to_m01_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m01_couplers_BVALID),
.S_AXI_rdata(xbar_to_m01_couplers_RDATA),
.S_AXI_rlast(xbar_to_m01_couplers_RLAST),
.S_AXI_rready(xbar_to_m01_couplers_RREADY),
.S_AXI_rresp(xbar_to_m01_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m01_couplers_RVALID),
.S_AXI_wdata(xbar_to_m01_couplers_WDATA),
.S_AXI_wlast(xbar_to_m01_couplers_WLAST),
.S_AXI_wready(xbar_to_m01_couplers_WREADY),
.S_AXI_wstrb(xbar_to_m01_couplers_WSTRB),
.S_AXI_wvalid(xbar_to_m01_couplers_WVALID));
s00_couplers_imp_1AYWH35 s00_couplers
(.M_ACLK(axi_mem_intercon_ACLK_net),
.M_ARESETN(axi_mem_intercon_ARESETN_net),
.M_AXI_araddr(s00_couplers_to_xbar_ARADDR),
.M_AXI_arburst(s00_couplers_to_xbar_ARBURST),
.M_AXI_arcache(s00_couplers_to_xbar_ARCACHE),
.M_AXI_arlen(s00_couplers_to_xbar_ARLEN),
.M_AXI_arlock(s00_couplers_to_xbar_ARLOCK),
.M_AXI_arprot(s00_couplers_to_xbar_ARPROT),
.M_AXI_arqos(s00_couplers_to_xbar_ARQOS),
.M_AXI_arready(s00_couplers_to_xbar_ARREADY),
.M_AXI_arsize(s00_couplers_to_xbar_ARSIZE),
.M_AXI_arvalid(s00_couplers_to_xbar_ARVALID),
.M_AXI_awaddr(s00_couplers_to_xbar_AWADDR),
.M_AXI_awburst(s00_couplers_to_xbar_AWBURST),
.M_AXI_awcache(s00_couplers_to_xbar_AWCACHE),
.M_AXI_awlen(s00_couplers_to_xbar_AWLEN),
.M_AXI_awlock(s00_couplers_to_xbar_AWLOCK),
.M_AXI_awprot(s00_couplers_to_xbar_AWPROT),
.M_AXI_awqos(s00_couplers_to_xbar_AWQOS),
.M_AXI_awready(s00_couplers_to_xbar_AWREADY),
.M_AXI_awsize(s00_couplers_to_xbar_AWSIZE),
.M_AXI_awvalid(s00_couplers_to_xbar_AWVALID),
.M_AXI_bready(s00_couplers_to_xbar_BREADY),
.M_AXI_bresp(s00_couplers_to_xbar_BRESP),
.M_AXI_bvalid(s00_couplers_to_xbar_BVALID),
.M_AXI_rdata(s00_couplers_to_xbar_RDATA),
.M_AXI_rlast(s00_couplers_to_xbar_RLAST),
.M_AXI_rready(s00_couplers_to_xbar_RREADY),
.M_AXI_rresp(s00_couplers_to_xbar_RRESP),
.M_AXI_rvalid(s00_couplers_to_xbar_RVALID),
.M_AXI_wdata(s00_couplers_to_xbar_WDATA),
.M_AXI_wlast(s00_couplers_to_xbar_WLAST),
.M_AXI_wready(s00_couplers_to_xbar_WREADY),
.M_AXI_wstrb(s00_couplers_to_xbar_WSTRB),
.M_AXI_wvalid(s00_couplers_to_xbar_WVALID),
.S_ACLK(S00_ACLK_1),
.S_ARESETN(S00_ARESETN_1),
.S_AXI_araddr(axi_mem_intercon_to_s00_couplers_ARADDR),
.S_AXI_arburst(axi_mem_intercon_to_s00_couplers_ARBURST),
.S_AXI_arcache(axi_mem_intercon_to_s00_couplers_ARCACHE),
.S_AXI_arlen(axi_mem_intercon_to_s00_couplers_ARLEN),
.S_AXI_arprot(axi_mem_intercon_to_s00_couplers_ARPROT),
.S_AXI_arready(axi_mem_intercon_to_s00_couplers_ARREADY),
.S_AXI_arsize(axi_mem_intercon_to_s00_couplers_ARSIZE),
.S_AXI_arvalid(axi_mem_intercon_to_s00_couplers_ARVALID),
.S_AXI_awaddr(axi_mem_intercon_to_s00_couplers_AWADDR),
.S_AXI_awburst(axi_mem_intercon_to_s00_couplers_AWBURST),
.S_AXI_awcache(axi_mem_intercon_to_s00_couplers_AWCACHE),
.S_AXI_awlen(axi_mem_intercon_to_s00_couplers_AWLEN),
.S_AXI_awprot(axi_mem_intercon_to_s00_couplers_AWPROT),
.S_AXI_awready(axi_mem_intercon_to_s00_couplers_AWREADY),
.S_AXI_awsize(axi_mem_intercon_to_s00_couplers_AWSIZE),
.S_AXI_awvalid(axi_mem_intercon_to_s00_couplers_AWVALID),
.S_AXI_bready(axi_mem_intercon_to_s00_couplers_BREADY),
.S_AXI_bresp(axi_mem_intercon_to_s00_couplers_BRESP),
.S_AXI_bvalid(axi_mem_intercon_to_s00_couplers_BVALID),
.S_AXI_rdata(axi_mem_intercon_to_s00_couplers_RDATA),
.S_AXI_rlast(axi_mem_intercon_to_s00_couplers_RLAST),
.S_AXI_rready(axi_mem_intercon_to_s00_couplers_RREADY),
.S_AXI_rresp(axi_mem_intercon_to_s00_couplers_RRESP),
.S_AXI_rvalid(axi_mem_intercon_to_s00_couplers_RVALID),
.S_AXI_wdata(axi_mem_intercon_to_s00_couplers_WDATA),
.S_AXI_wlast(axi_mem_intercon_to_s00_couplers_WLAST),
.S_AXI_wready(axi_mem_intercon_to_s00_couplers_WREADY),
.S_AXI_wstrb(axi_mem_intercon_to_s00_couplers_WSTRB),
.S_AXI_wvalid(axi_mem_intercon_to_s00_couplers_WVALID));
design_1_xbar_3 xbar
(.aclk(axi_mem_intercon_ACLK_net),
.aresetn(axi_mem_intercon_ARESETN_net),
.m_axi_araddr({xbar_to_m01_couplers_ARADDR,xbar_to_m00_couplers_ARADDR}),
.m_axi_arburst({xbar_to_m01_couplers_ARBURST,xbar_to_m00_couplers_ARBURST}),
.m_axi_arcache({xbar_to_m01_couplers_ARCACHE,xbar_to_m00_couplers_ARCACHE}),
.m_axi_arlen({xbar_to_m01_couplers_ARLEN,xbar_to_m00_couplers_ARLEN}),
.m_axi_arlock({xbar_to_m01_couplers_ARLOCK,xbar_to_m00_couplers_ARLOCK}),
.m_axi_arprot({xbar_to_m01_couplers_ARPROT,xbar_to_m00_couplers_ARPROT}),
.m_axi_arqos({xbar_to_m01_couplers_ARQOS,xbar_to_m00_couplers_ARQOS}),
.m_axi_arready({xbar_to_m01_couplers_ARREADY,xbar_to_m00_couplers_ARREADY}),
.m_axi_arregion({xbar_to_m01_couplers_ARREGION,xbar_to_m00_couplers_ARREGION}),
.m_axi_arsize({xbar_to_m01_couplers_ARSIZE,xbar_to_m00_couplers_ARSIZE}),
.m_axi_arvalid({xbar_to_m01_couplers_ARVALID,xbar_to_m00_couplers_ARVALID}),
.m_axi_awaddr({xbar_to_m01_couplers_AWADDR,xbar_to_m00_couplers_AWADDR}),
.m_axi_awburst({xbar_to_m01_couplers_AWBURST,xbar_to_m00_couplers_AWBURST}),
.m_axi_awcache({xbar_to_m01_couplers_AWCACHE,xbar_to_m00_couplers_AWCACHE}),
.m_axi_awlen({xbar_to_m01_couplers_AWLEN,xbar_to_m00_couplers_AWLEN}),
.m_axi_awlock({xbar_to_m01_couplers_AWLOCK,xbar_to_m00_couplers_AWLOCK}),
.m_axi_awprot({xbar_to_m01_couplers_AWPROT,xbar_to_m00_couplers_AWPROT}),
.m_axi_awqos({xbar_to_m01_couplers_AWQOS,xbar_to_m00_couplers_AWQOS}),
.m_axi_awready({xbar_to_m01_couplers_AWREADY,xbar_to_m00_couplers_AWREADY}),
.m_axi_awregion({xbar_to_m01_couplers_AWREGION,xbar_to_m00_couplers_AWREGION}),
.m_axi_awsize({xbar_to_m01_couplers_AWSIZE,xbar_to_m00_couplers_AWSIZE}),
.m_axi_awvalid({xbar_to_m01_couplers_AWVALID,xbar_to_m00_couplers_AWVALID}),
.m_axi_bready({xbar_to_m01_couplers_BREADY,xbar_to_m00_couplers_BREADY}),
.m_axi_bresp({xbar_to_m01_couplers_BRESP,xbar_to_m00_couplers_BRESP}),
.m_axi_bvalid({xbar_to_m01_couplers_BVALID,xbar_to_m00_couplers_BVALID}),
.m_axi_rdata({xbar_to_m01_couplers_RDATA,xbar_to_m00_couplers_RDATA}),
.m_axi_rlast({xbar_to_m01_couplers_RLAST,xbar_to_m00_couplers_RLAST}),
.m_axi_rready({xbar_to_m01_couplers_RREADY,xbar_to_m00_couplers_RREADY}),
.m_axi_rresp({xbar_to_m01_couplers_RRESP,xbar_to_m00_couplers_RRESP}),
.m_axi_rvalid({xbar_to_m01_couplers_RVALID,xbar_to_m00_couplers_RVALID}),
.m_axi_wdata({xbar_to_m01_couplers_WDATA,xbar_to_m00_couplers_WDATA}),
.m_axi_wlast({xbar_to_m01_couplers_WLAST,xbar_to_m00_couplers_WLAST}),
.m_axi_wready({xbar_to_m01_couplers_WREADY,xbar_to_m00_couplers_WREADY}),
.m_axi_wstrb({xbar_to_m01_couplers_WSTRB,xbar_to_m00_couplers_WSTRB}),
.m_axi_wvalid({xbar_to_m01_couplers_WVALID,xbar_to_m00_couplers_WVALID}),
.s_axi_araddr(s00_couplers_to_xbar_ARADDR),
.s_axi_arburst(s00_couplers_to_xbar_ARBURST),
.s_axi_arcache(s00_couplers_to_xbar_ARCACHE),
.s_axi_arlen(s00_couplers_to_xbar_ARLEN),
.s_axi_arlock(s00_couplers_to_xbar_ARLOCK),
.s_axi_arprot(s00_couplers_to_xbar_ARPROT),
.s_axi_arqos(s00_couplers_to_xbar_ARQOS),
.s_axi_arready(s00_couplers_to_xbar_ARREADY),
.s_axi_arsize(s00_couplers_to_xbar_ARSIZE),
.s_axi_arvalid(s00_couplers_to_xbar_ARVALID),
.s_axi_awaddr(s00_couplers_to_xbar_AWADDR),
.s_axi_awburst(s00_couplers_to_xbar_AWBURST),
.s_axi_awcache(s00_couplers_to_xbar_AWCACHE),
.s_axi_awlen(s00_couplers_to_xbar_AWLEN),
.s_axi_awlock(s00_couplers_to_xbar_AWLOCK),
.s_axi_awprot(s00_couplers_to_xbar_AWPROT),
.s_axi_awqos(s00_couplers_to_xbar_AWQOS),
.s_axi_awready(s00_couplers_to_xbar_AWREADY),
.s_axi_awsize(s00_couplers_to_xbar_AWSIZE),
.s_axi_awvalid(s00_couplers_to_xbar_AWVALID),
.s_axi_bready(s00_couplers_to_xbar_BREADY),
.s_axi_bresp(s00_couplers_to_xbar_BRESP),
.s_axi_bvalid(s00_couplers_to_xbar_BVALID),
.s_axi_rdata(s00_couplers_to_xbar_RDATA),
.s_axi_rlast(s00_couplers_to_xbar_RLAST),
.s_axi_rready(s00_couplers_to_xbar_RREADY),
.s_axi_rresp(s00_couplers_to_xbar_RRESP),
.s_axi_rvalid(s00_couplers_to_xbar_RVALID),
.s_axi_wdata(s00_couplers_to_xbar_WDATA),
.s_axi_wlast(s00_couplers_to_xbar_WLAST),
.s_axi_wready(s00_couplers_to_xbar_WREADY),
.s_axi_wstrb(s00_couplers_to_xbar_WSTRB),
.s_axi_wvalid(s00_couplers_to_xbar_WVALID));
endmodule
module design_1_processing_system7_0_axi_periph_0
(ACLK,
ARESETN,
M00_ACLK,
M00_ARESETN,
M00_AXI_araddr,
M00_AXI_arready,
M00_AXI_arvalid,
M00_AXI_awaddr,
M00_AXI_awready,
M00_AXI_awvalid,
M00_AXI_bready,
M00_AXI_bresp,
M00_AXI_bvalid,
M00_AXI_rdata,
M00_AXI_rready,
M00_AXI_rresp,
M00_AXI_rvalid,
M00_AXI_wdata,
M00_AXI_wready,
M00_AXI_wvalid,
M01_ACLK,
M01_ARESETN,
M01_AXI_araddr,
M01_AXI_arready,
M01_AXI_arvalid,
M01_AXI_awaddr,
M01_AXI_awready,
M01_AXI_awvalid,
M01_AXI_bready,
M01_AXI_bresp,
M01_AXI_bvalid,
M01_AXI_rdata,
M01_AXI_rready,
M01_AXI_rresp,
M01_AXI_rvalid,
M01_AXI_wdata,
M01_AXI_wready,
M01_AXI_wstrb,
M01_AXI_wvalid,
M02_ACLK,
M02_ARESETN,
M02_AXI_araddr,
M02_AXI_arready,
M02_AXI_arvalid,
M02_AXI_awaddr,
M02_AXI_awready,
M02_AXI_awvalid,
M02_AXI_bready,
M02_AXI_bresp,
M02_AXI_bvalid,
M02_AXI_rdata,
M02_AXI_rready,
M02_AXI_rresp,
M02_AXI_rvalid,
M02_AXI_wdata,
M02_AXI_wready,
M02_AXI_wvalid,
M03_ACLK,
M03_ARESETN,
M03_AXI_araddr,
M03_AXI_arready,
M03_AXI_arvalid,
M03_AXI_awaddr,
M03_AXI_awready,
M03_AXI_awvalid,
M03_AXI_bready,
M03_AXI_bresp,
M03_AXI_bvalid,
M03_AXI_rdata,
M03_AXI_rready,
M03_AXI_rresp,
M03_AXI_rvalid,
M03_AXI_wdata,
M03_AXI_wready,
M03_AXI_wvalid,
S00_ACLK,
S00_ARESETN,
S00_AXI_araddr,
S00_AXI_arburst,
S00_AXI_arcache,
S00_AXI_arid,
S00_AXI_arlen,
S00_AXI_arlock,
S00_AXI_arprot,
S00_AXI_arqos,
S00_AXI_arready,
S00_AXI_arsize,
S00_AXI_arvalid,
S00_AXI_awaddr,
S00_AXI_awburst,
S00_AXI_awcache,
S00_AXI_awid,
S00_AXI_awlen,
S00_AXI_awlock,
S00_AXI_awprot,
S00_AXI_awqos,
S00_AXI_awready,
S00_AXI_awsize,
S00_AXI_awvalid,
S00_AXI_bid,
S00_AXI_bready,
S00_AXI_bresp,
S00_AXI_bvalid,
S00_AXI_rdata,
S00_AXI_rid,
S00_AXI_rlast,
S00_AXI_rready,
S00_AXI_rresp,
S00_AXI_rvalid,
S00_AXI_wdata,
S00_AXI_wid,
S00_AXI_wlast,
S00_AXI_wready,
S00_AXI_wstrb,
S00_AXI_wvalid);
input ACLK;
input ARESETN;
input M00_ACLK;
input M00_ARESETN;
output [31:0]M00_AXI_araddr;
input [0:0]M00_AXI_arready;
output [0:0]M00_AXI_arvalid;
output [31:0]M00_AXI_awaddr;
input [0:0]M00_AXI_awready;
output [0:0]M00_AXI_awvalid;
output [0:0]M00_AXI_bready;
input [1:0]M00_AXI_bresp;
input [0:0]M00_AXI_bvalid;
input [31:0]M00_AXI_rdata;
output [0:0]M00_AXI_rready;
input [1:0]M00_AXI_rresp;
input [0:0]M00_AXI_rvalid;
output [31:0]M00_AXI_wdata;
input [0:0]M00_AXI_wready;
output [0:0]M00_AXI_wvalid;
input M01_ACLK;
input M01_ARESETN;
output [31:0]M01_AXI_araddr;
input M01_AXI_arready;
output M01_AXI_arvalid;
output [31:0]M01_AXI_awaddr;
input M01_AXI_awready;
output M01_AXI_awvalid;
output M01_AXI_bready;
input [1:0]M01_AXI_bresp;
input M01_AXI_bvalid;
input [31:0]M01_AXI_rdata;
output M01_AXI_rready;
input [1:0]M01_AXI_rresp;
input M01_AXI_rvalid;
output [31:0]M01_AXI_wdata;
input M01_AXI_wready;
output [3:0]M01_AXI_wstrb;
output M01_AXI_wvalid;
input M02_ACLK;
input M02_ARESETN;
output [31:0]M02_AXI_araddr;
input [0:0]M02_AXI_arready;
output [0:0]M02_AXI_arvalid;
output [31:0]M02_AXI_awaddr;
input [0:0]M02_AXI_awready;
output [0:0]M02_AXI_awvalid;
output [0:0]M02_AXI_bready;
input [1:0]M02_AXI_bresp;
input [0:0]M02_AXI_bvalid;
input [31:0]M02_AXI_rdata;
output [0:0]M02_AXI_rready;
input [1:0]M02_AXI_rresp;
input [0:0]M02_AXI_rvalid;
output [31:0]M02_AXI_wdata;
input [0:0]M02_AXI_wready;
output [0:0]M02_AXI_wvalid;
input M03_ACLK;
input M03_ARESETN;
output [31:0]M03_AXI_araddr;
input [0:0]M03_AXI_arready;
output [0:0]M03_AXI_arvalid;
output [31:0]M03_AXI_awaddr;
input [0:0]M03_AXI_awready;
output [0:0]M03_AXI_awvalid;
output [0:0]M03_AXI_bready;
input [1:0]M03_AXI_bresp;
input [0:0]M03_AXI_bvalid;
input [31:0]M03_AXI_rdata;
output [0:0]M03_AXI_rready;
input [1:0]M03_AXI_rresp;
input [0:0]M03_AXI_rvalid;
output [31:0]M03_AXI_wdata;
input [0:0]M03_AXI_wready;
output [0:0]M03_AXI_wvalid;
input S00_ACLK;
input S00_ARESETN;
input [31:0]S00_AXI_araddr;
input [1:0]S00_AXI_arburst;
input [3:0]S00_AXI_arcache;
input [11:0]S00_AXI_arid;
input [3:0]S00_AXI_arlen;
input [1:0]S00_AXI_arlock;
input [2:0]S00_AXI_arprot;
input [3:0]S00_AXI_arqos;
output S00_AXI_arready;
input [2:0]S00_AXI_arsize;
input S00_AXI_arvalid;
input [31:0]S00_AXI_awaddr;
input [1:0]S00_AXI_awburst;
input [3:0]S00_AXI_awcache;
input [11:0]S00_AXI_awid;
input [3:0]S00_AXI_awlen;
input [1:0]S00_AXI_awlock;
input [2:0]S00_AXI_awprot;
input [3:0]S00_AXI_awqos;
output S00_AXI_awready;
input [2:0]S00_AXI_awsize;
input S00_AXI_awvalid;
output [11:0]S00_AXI_bid;
input S00_AXI_bready;
output [1:0]S00_AXI_bresp;
output S00_AXI_bvalid;
output [31:0]S00_AXI_rdata;
output [11:0]S00_AXI_rid;
output S00_AXI_rlast;
input S00_AXI_rready;
output [1:0]S00_AXI_rresp;
output S00_AXI_rvalid;
input [31:0]S00_AXI_wdata;
input [11:0]S00_AXI_wid;
input S00_AXI_wlast;
output S00_AXI_wready;
input [3:0]S00_AXI_wstrb;
input S00_AXI_wvalid;
wire M00_ACLK_1;
wire M00_ARESETN_1;
wire M01_ACLK_1;
wire M01_ARESETN_1;
wire M02_ACLK_1;
wire M02_ARESETN_1;
wire M03_ACLK_1;
wire M03_ARESETN_1;
wire S00_ACLK_1;
wire S00_ARESETN_1;
wire [31:0]m00_couplers_to_processing_system7_0_axi_periph_ARADDR;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_ARREADY;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_ARVALID;
wire [31:0]m00_couplers_to_processing_system7_0_axi_periph_AWADDR;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_AWREADY;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_AWVALID;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_BREADY;
wire [1:0]m00_couplers_to_processing_system7_0_axi_periph_BRESP;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_BVALID;
wire [31:0]m00_couplers_to_processing_system7_0_axi_periph_RDATA;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_RREADY;
wire [1:0]m00_couplers_to_processing_system7_0_axi_periph_RRESP;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_RVALID;
wire [31:0]m00_couplers_to_processing_system7_0_axi_periph_WDATA;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_WREADY;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_WVALID;
wire [31:0]m01_couplers_to_processing_system7_0_axi_periph_ARADDR;
wire m01_couplers_to_processing_system7_0_axi_periph_ARREADY;
wire m01_couplers_to_processing_system7_0_axi_periph_ARVALID;
wire [31:0]m01_couplers_to_processing_system7_0_axi_periph_AWADDR;
wire m01_couplers_to_processing_system7_0_axi_periph_AWREADY;
wire m01_couplers_to_processing_system7_0_axi_periph_AWVALID;
wire m01_couplers_to_processing_system7_0_axi_periph_BREADY;
wire [1:0]m01_couplers_to_processing_system7_0_axi_periph_BRESP;
wire m01_couplers_to_processing_system7_0_axi_periph_BVALID;
wire [31:0]m01_couplers_to_processing_system7_0_axi_periph_RDATA;
wire m01_couplers_to_processing_system7_0_axi_periph_RREADY;
wire [1:0]m01_couplers_to_processing_system7_0_axi_periph_RRESP;
wire m01_couplers_to_processing_system7_0_axi_periph_RVALID;
wire [31:0]m01_couplers_to_processing_system7_0_axi_periph_WDATA;
wire m01_couplers_to_processing_system7_0_axi_periph_WREADY;
wire [3:0]m01_couplers_to_processing_system7_0_axi_periph_WSTRB;
wire m01_couplers_to_processing_system7_0_axi_periph_WVALID;
wire [31:0]m02_couplers_to_processing_system7_0_axi_periph_ARADDR;
wire [0:0]m02_couplers_to_processing_system7_0_axi_periph_ARREADY;
wire [0:0]m02_couplers_to_processing_system7_0_axi_periph_ARVALID;
wire [31:0]m02_couplers_to_processing_system7_0_axi_periph_AWADDR;
wire [0:0]m02_couplers_to_processing_system7_0_axi_periph_AWREADY;
wire [0:0]m02_couplers_to_processing_system7_0_axi_periph_AWVALID;
wire [0:0]m02_couplers_to_processing_system7_0_axi_periph_BREADY;
wire [1:0]m02_couplers_to_processing_system7_0_axi_periph_BRESP;
wire [0:0]m02_couplers_to_processing_system7_0_axi_periph_BVALID;
wire [31:0]m02_couplers_to_processing_system7_0_axi_periph_RDATA;
wire [0:0]m02_couplers_to_processing_system7_0_axi_periph_RREADY;
wire [1:0]m02_couplers_to_processing_system7_0_axi_periph_RRESP;
wire [0:0]m02_couplers_to_processing_system7_0_axi_periph_RVALID;
wire [31:0]m02_couplers_to_processing_system7_0_axi_periph_WDATA;
wire [0:0]m02_couplers_to_processing_system7_0_axi_periph_WREADY;
wire [0:0]m02_couplers_to_processing_system7_0_axi_periph_WVALID;
wire [31:0]m03_couplers_to_processing_system7_0_axi_periph_ARADDR;
wire [0:0]m03_couplers_to_processing_system7_0_axi_periph_ARREADY;
wire [0:0]m03_couplers_to_processing_system7_0_axi_periph_ARVALID;
wire [31:0]m03_couplers_to_processing_system7_0_axi_periph_AWADDR;
wire [0:0]m03_couplers_to_processing_system7_0_axi_periph_AWREADY;
wire [0:0]m03_couplers_to_processing_system7_0_axi_periph_AWVALID;
wire [0:0]m03_couplers_to_processing_system7_0_axi_periph_BREADY;
wire [1:0]m03_couplers_to_processing_system7_0_axi_periph_BRESP;
wire [0:0]m03_couplers_to_processing_system7_0_axi_periph_BVALID;
wire [31:0]m03_couplers_to_processing_system7_0_axi_periph_RDATA;
wire [0:0]m03_couplers_to_processing_system7_0_axi_periph_RREADY;
wire [1:0]m03_couplers_to_processing_system7_0_axi_periph_RRESP;
wire [0:0]m03_couplers_to_processing_system7_0_axi_periph_RVALID;
wire [31:0]m03_couplers_to_processing_system7_0_axi_periph_WDATA;
wire [0:0]m03_couplers_to_processing_system7_0_axi_periph_WREADY;
wire [0:0]m03_couplers_to_processing_system7_0_axi_periph_WVALID;
wire processing_system7_0_axi_periph_ACLK_net;
wire processing_system7_0_axi_periph_ARESETN_net;
wire [31:0]processing_system7_0_axi_periph_to_s00_couplers_ARADDR;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_ARBURST;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_ARCACHE;
wire [11:0]processing_system7_0_axi_periph_to_s00_couplers_ARID;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_ARLEN;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_ARLOCK;
wire [2:0]processing_system7_0_axi_periph_to_s00_couplers_ARPROT;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_ARQOS;
wire processing_system7_0_axi_periph_to_s00_couplers_ARREADY;
wire [2:0]processing_system7_0_axi_periph_to_s00_couplers_ARSIZE;
wire processing_system7_0_axi_periph_to_s00_couplers_ARVALID;
wire [31:0]processing_system7_0_axi_periph_to_s00_couplers_AWADDR;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_AWBURST;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_AWCACHE;
wire [11:0]processing_system7_0_axi_periph_to_s00_couplers_AWID;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_AWLEN;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_AWLOCK;
wire [2:0]processing_system7_0_axi_periph_to_s00_couplers_AWPROT;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_AWQOS;
wire processing_system7_0_axi_periph_to_s00_couplers_AWREADY;
wire [2:0]processing_system7_0_axi_periph_to_s00_couplers_AWSIZE;
wire processing_system7_0_axi_periph_to_s00_couplers_AWVALID;
wire [11:0]processing_system7_0_axi_periph_to_s00_couplers_BID;
wire processing_system7_0_axi_periph_to_s00_couplers_BREADY;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_BRESP;
wire processing_system7_0_axi_periph_to_s00_couplers_BVALID;
wire [31:0]processing_system7_0_axi_periph_to_s00_couplers_RDATA;
wire [11:0]processing_system7_0_axi_periph_to_s00_couplers_RID;
wire processing_system7_0_axi_periph_to_s00_couplers_RLAST;
wire processing_system7_0_axi_periph_to_s00_couplers_RREADY;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_RRESP;
wire processing_system7_0_axi_periph_to_s00_couplers_RVALID;
wire [31:0]processing_system7_0_axi_periph_to_s00_couplers_WDATA;
wire [11:0]processing_system7_0_axi_periph_to_s00_couplers_WID;
wire processing_system7_0_axi_periph_to_s00_couplers_WLAST;
wire processing_system7_0_axi_periph_to_s00_couplers_WREADY;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_WSTRB;
wire processing_system7_0_axi_periph_to_s00_couplers_WVALID;
wire [31:0]s00_couplers_to_xbar_ARADDR;
wire [2:0]s00_couplers_to_xbar_ARPROT;
wire [0:0]s00_couplers_to_xbar_ARREADY;
wire s00_couplers_to_xbar_ARVALID;
wire [31:0]s00_couplers_to_xbar_AWADDR;
wire [2:0]s00_couplers_to_xbar_AWPROT;
wire [0:0]s00_couplers_to_xbar_AWREADY;
wire s00_couplers_to_xbar_AWVALID;
wire s00_couplers_to_xbar_BREADY;
wire [1:0]s00_couplers_to_xbar_BRESP;
wire [0:0]s00_couplers_to_xbar_BVALID;
wire [31:0]s00_couplers_to_xbar_RDATA;
wire s00_couplers_to_xbar_RREADY;
wire [1:0]s00_couplers_to_xbar_RRESP;
wire [0:0]s00_couplers_to_xbar_RVALID;
wire [31:0]s00_couplers_to_xbar_WDATA;
wire [0:0]s00_couplers_to_xbar_WREADY;
wire [3:0]s00_couplers_to_xbar_WSTRB;
wire s00_couplers_to_xbar_WVALID;
wire [31:0]xbar_to_m00_couplers_ARADDR;
wire [0:0]xbar_to_m00_couplers_ARREADY;
wire [0:0]xbar_to_m00_couplers_ARVALID;
wire [31:0]xbar_to_m00_couplers_AWADDR;
wire [0:0]xbar_to_m00_couplers_AWREADY;
wire [0:0]xbar_to_m00_couplers_AWVALID;
wire [0:0]xbar_to_m00_couplers_BREADY;
wire [1:0]xbar_to_m00_couplers_BRESP;
wire [0:0]xbar_to_m00_couplers_BVALID;
wire [31:0]xbar_to_m00_couplers_RDATA;
wire [0:0]xbar_to_m00_couplers_RREADY;
wire [1:0]xbar_to_m00_couplers_RRESP;
wire [0:0]xbar_to_m00_couplers_RVALID;
wire [31:0]xbar_to_m00_couplers_WDATA;
wire [0:0]xbar_to_m00_couplers_WREADY;
wire [0:0]xbar_to_m00_couplers_WVALID;
wire [63:32]xbar_to_m01_couplers_ARADDR;
wire xbar_to_m01_couplers_ARREADY;
wire [1:1]xbar_to_m01_couplers_ARVALID;
wire [63:32]xbar_to_m01_couplers_AWADDR;
wire xbar_to_m01_couplers_AWREADY;
wire [1:1]xbar_to_m01_couplers_AWVALID;
wire [1:1]xbar_to_m01_couplers_BREADY;
wire [1:0]xbar_to_m01_couplers_BRESP;
wire xbar_to_m01_couplers_BVALID;
wire [31:0]xbar_to_m01_couplers_RDATA;
wire [1:1]xbar_to_m01_couplers_RREADY;
wire [1:0]xbar_to_m01_couplers_RRESP;
wire xbar_to_m01_couplers_RVALID;
wire [63:32]xbar_to_m01_couplers_WDATA;
wire xbar_to_m01_couplers_WREADY;
wire [7:4]xbar_to_m01_couplers_WSTRB;
wire [1:1]xbar_to_m01_couplers_WVALID;
wire [95:64]xbar_to_m02_couplers_ARADDR;
wire [0:0]xbar_to_m02_couplers_ARREADY;
wire [2:2]xbar_to_m02_couplers_ARVALID;
wire [95:64]xbar_to_m02_couplers_AWADDR;
wire [0:0]xbar_to_m02_couplers_AWREADY;
wire [2:2]xbar_to_m02_couplers_AWVALID;
wire [2:2]xbar_to_m02_couplers_BREADY;
wire [1:0]xbar_to_m02_couplers_BRESP;
wire [0:0]xbar_to_m02_couplers_BVALID;
wire [31:0]xbar_to_m02_couplers_RDATA;
wire [2:2]xbar_to_m02_couplers_RREADY;
wire [1:0]xbar_to_m02_couplers_RRESP;
wire [0:0]xbar_to_m02_couplers_RVALID;
wire [95:64]xbar_to_m02_couplers_WDATA;
wire [0:0]xbar_to_m02_couplers_WREADY;
wire [2:2]xbar_to_m02_couplers_WVALID;
wire [127:96]xbar_to_m03_couplers_ARADDR;
wire [0:0]xbar_to_m03_couplers_ARREADY;
wire [3:3]xbar_to_m03_couplers_ARVALID;
wire [127:96]xbar_to_m03_couplers_AWADDR;
wire [0:0]xbar_to_m03_couplers_AWREADY;
wire [3:3]xbar_to_m03_couplers_AWVALID;
wire [3:3]xbar_to_m03_couplers_BREADY;
wire [1:0]xbar_to_m03_couplers_BRESP;
wire [0:0]xbar_to_m03_couplers_BVALID;
wire [31:0]xbar_to_m03_couplers_RDATA;
wire [3:3]xbar_to_m03_couplers_RREADY;
wire [1:0]xbar_to_m03_couplers_RRESP;
wire [0:0]xbar_to_m03_couplers_RVALID;
wire [127:96]xbar_to_m03_couplers_WDATA;
wire [0:0]xbar_to_m03_couplers_WREADY;
wire [3:3]xbar_to_m03_couplers_WVALID;
wire [15:0]NLW_xbar_m_axi_wstrb_UNCONNECTED;
assign M00_ACLK_1 = M00_ACLK;
assign M00_ARESETN_1 = M00_ARESETN;
assign M00_AXI_araddr[31:0] = m00_couplers_to_processing_system7_0_axi_periph_ARADDR;
assign M00_AXI_arvalid[0] = m00_couplers_to_processing_system7_0_axi_periph_ARVALID;
assign M00_AXI_awaddr[31:0] = m00_couplers_to_processing_system7_0_axi_periph_AWADDR;
assign M00_AXI_awvalid[0] = m00_couplers_to_processing_system7_0_axi_periph_AWVALID;
assign M00_AXI_bready[0] = m00_couplers_to_processing_system7_0_axi_periph_BREADY;
assign M00_AXI_rready[0] = m00_couplers_to_processing_system7_0_axi_periph_RREADY;
assign M00_AXI_wdata[31:0] = m00_couplers_to_processing_system7_0_axi_periph_WDATA;
assign M00_AXI_wvalid[0] = m00_couplers_to_processing_system7_0_axi_periph_WVALID;
assign M01_ACLK_1 = M01_ACLK;
assign M01_ARESETN_1 = M01_ARESETN;
assign M01_AXI_araddr[31:0] = m01_couplers_to_processing_system7_0_axi_periph_ARADDR;
assign M01_AXI_arvalid = m01_couplers_to_processing_system7_0_axi_periph_ARVALID;
assign M01_AXI_awaddr[31:0] = m01_couplers_to_processing_system7_0_axi_periph_AWADDR;
assign M01_AXI_awvalid = m01_couplers_to_processing_system7_0_axi_periph_AWVALID;
assign M01_AXI_bready = m01_couplers_to_processing_system7_0_axi_periph_BREADY;
assign M01_AXI_rready = m01_couplers_to_processing_system7_0_axi_periph_RREADY;
assign M01_AXI_wdata[31:0] = m01_couplers_to_processing_system7_0_axi_periph_WDATA;
assign M01_AXI_wstrb[3:0] = m01_couplers_to_processing_system7_0_axi_periph_WSTRB;
assign M01_AXI_wvalid = m01_couplers_to_processing_system7_0_axi_periph_WVALID;
assign M02_ACLK_1 = M02_ACLK;
assign M02_ARESETN_1 = M02_ARESETN;
assign M02_AXI_araddr[31:0] = m02_couplers_to_processing_system7_0_axi_periph_ARADDR;
assign M02_AXI_arvalid[0] = m02_couplers_to_processing_system7_0_axi_periph_ARVALID;
assign M02_AXI_awaddr[31:0] = m02_couplers_to_processing_system7_0_axi_periph_AWADDR;
assign M02_AXI_awvalid[0] = m02_couplers_to_processing_system7_0_axi_periph_AWVALID;
assign M02_AXI_bready[0] = m02_couplers_to_processing_system7_0_axi_periph_BREADY;
assign M02_AXI_rready[0] = m02_couplers_to_processing_system7_0_axi_periph_RREADY;
assign M02_AXI_wdata[31:0] = m02_couplers_to_processing_system7_0_axi_periph_WDATA;
assign M02_AXI_wvalid[0] = m02_couplers_to_processing_system7_0_axi_periph_WVALID;
assign M03_ACLK_1 = M03_ACLK;
assign M03_ARESETN_1 = M03_ARESETN;
assign M03_AXI_araddr[31:0] = m03_couplers_to_processing_system7_0_axi_periph_ARADDR;
assign M03_AXI_arvalid[0] = m03_couplers_to_processing_system7_0_axi_periph_ARVALID;
assign M03_AXI_awaddr[31:0] = m03_couplers_to_processing_system7_0_axi_periph_AWADDR;
assign M03_AXI_awvalid[0] = m03_couplers_to_processing_system7_0_axi_periph_AWVALID;
assign M03_AXI_bready[0] = m03_couplers_to_processing_system7_0_axi_periph_BREADY;
assign M03_AXI_rready[0] = m03_couplers_to_processing_system7_0_axi_periph_RREADY;
assign M03_AXI_wdata[31:0] = m03_couplers_to_processing_system7_0_axi_periph_WDATA;
assign M03_AXI_wvalid[0] = m03_couplers_to_processing_system7_0_axi_periph_WVALID;
assign S00_ACLK_1 = S00_ACLK;
assign S00_ARESETN_1 = S00_ARESETN;
assign S00_AXI_arready = processing_system7_0_axi_periph_to_s00_couplers_ARREADY;
assign S00_AXI_awready = processing_system7_0_axi_periph_to_s00_couplers_AWREADY;
assign S00_AXI_bid[11:0] = processing_system7_0_axi_periph_to_s00_couplers_BID;
assign S00_AXI_bresp[1:0] = processing_system7_0_axi_periph_to_s00_couplers_BRESP;
assign S00_AXI_bvalid = processing_system7_0_axi_periph_to_s00_couplers_BVALID;
assign S00_AXI_rdata[31:0] = processing_system7_0_axi_periph_to_s00_couplers_RDATA;
assign S00_AXI_rid[11:0] = processing_system7_0_axi_periph_to_s00_couplers_RID;
assign S00_AXI_rlast = processing_system7_0_axi_periph_to_s00_couplers_RLAST;
assign S00_AXI_rresp[1:0] = processing_system7_0_axi_periph_to_s00_couplers_RRESP;
assign S00_AXI_rvalid = processing_system7_0_axi_periph_to_s00_couplers_RVALID;
assign S00_AXI_wready = processing_system7_0_axi_periph_to_s00_couplers_WREADY;
assign m00_couplers_to_processing_system7_0_axi_periph_ARREADY = M00_AXI_arready[0];
assign m00_couplers_to_processing_system7_0_axi_periph_AWREADY = M00_AXI_awready[0];
assign m00_couplers_to_processing_system7_0_axi_periph_BRESP = M00_AXI_bresp[1:0];
assign m00_couplers_to_processing_system7_0_axi_periph_BVALID = M00_AXI_bvalid[0];
assign m00_couplers_to_processing_system7_0_axi_periph_RDATA = M00_AXI_rdata[31:0];
assign m00_couplers_to_processing_system7_0_axi_periph_RRESP = M00_AXI_rresp[1:0];
assign m00_couplers_to_processing_system7_0_axi_periph_RVALID = M00_AXI_rvalid[0];
assign m00_couplers_to_processing_system7_0_axi_periph_WREADY = M00_AXI_wready[0];
assign m01_couplers_to_processing_system7_0_axi_periph_ARREADY = M01_AXI_arready;
assign m01_couplers_to_processing_system7_0_axi_periph_AWREADY = M01_AXI_awready;
assign m01_couplers_to_processing_system7_0_axi_periph_BRESP = M01_AXI_bresp[1:0];
assign m01_couplers_to_processing_system7_0_axi_periph_BVALID = M01_AXI_bvalid;
assign m01_couplers_to_processing_system7_0_axi_periph_RDATA = M01_AXI_rdata[31:0];
assign m01_couplers_to_processing_system7_0_axi_periph_RRESP = M01_AXI_rresp[1:0];
assign m01_couplers_to_processing_system7_0_axi_periph_RVALID = M01_AXI_rvalid;
assign m01_couplers_to_processing_system7_0_axi_periph_WREADY = M01_AXI_wready;
assign m02_couplers_to_processing_system7_0_axi_periph_ARREADY = M02_AXI_arready[0];
assign m02_couplers_to_processing_system7_0_axi_periph_AWREADY = M02_AXI_awready[0];
assign m02_couplers_to_processing_system7_0_axi_periph_BRESP = M02_AXI_bresp[1:0];
assign m02_couplers_to_processing_system7_0_axi_periph_BVALID = M02_AXI_bvalid[0];
assign m02_couplers_to_processing_system7_0_axi_periph_RDATA = M02_AXI_rdata[31:0];
assign m02_couplers_to_processing_system7_0_axi_periph_RRESP = M02_AXI_rresp[1:0];
assign m02_couplers_to_processing_system7_0_axi_periph_RVALID = M02_AXI_rvalid[0];
assign m02_couplers_to_processing_system7_0_axi_periph_WREADY = M02_AXI_wready[0];
assign m03_couplers_to_processing_system7_0_axi_periph_ARREADY = M03_AXI_arready[0];
assign m03_couplers_to_processing_system7_0_axi_periph_AWREADY = M03_AXI_awready[0];
assign m03_couplers_to_processing_system7_0_axi_periph_BRESP = M03_AXI_bresp[1:0];
assign m03_couplers_to_processing_system7_0_axi_periph_BVALID = M03_AXI_bvalid[0];
assign m03_couplers_to_processing_system7_0_axi_periph_RDATA = M03_AXI_rdata[31:0];
assign m03_couplers_to_processing_system7_0_axi_periph_RRESP = M03_AXI_rresp[1:0];
assign m03_couplers_to_processing_system7_0_axi_periph_RVALID = M03_AXI_rvalid[0];
assign m03_couplers_to_processing_system7_0_axi_periph_WREADY = M03_AXI_wready[0];
assign processing_system7_0_axi_periph_ACLK_net = ACLK;
assign processing_system7_0_axi_periph_ARESETN_net = ARESETN;
assign processing_system7_0_axi_periph_to_s00_couplers_ARADDR = S00_AXI_araddr[31:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARID = S00_AXI_arid[11:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARLEN = S00_AXI_arlen[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARLOCK = S00_AXI_arlock[1:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARQOS = S00_AXI_arqos[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARVALID = S00_AXI_arvalid;
assign processing_system7_0_axi_periph_to_s00_couplers_AWADDR = S00_AXI_awaddr[31:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWID = S00_AXI_awid[11:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWLEN = S00_AXI_awlen[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWLOCK = S00_AXI_awlock[1:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWQOS = S00_AXI_awqos[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWVALID = S00_AXI_awvalid;
assign processing_system7_0_axi_periph_to_s00_couplers_BREADY = S00_AXI_bready;
assign processing_system7_0_axi_periph_to_s00_couplers_RREADY = S00_AXI_rready;
assign processing_system7_0_axi_periph_to_s00_couplers_WDATA = S00_AXI_wdata[31:0];
assign processing_system7_0_axi_periph_to_s00_couplers_WID = S00_AXI_wid[11:0];
assign processing_system7_0_axi_periph_to_s00_couplers_WLAST = S00_AXI_wlast;
assign processing_system7_0_axi_periph_to_s00_couplers_WSTRB = S00_AXI_wstrb[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_WVALID = S00_AXI_wvalid;
m00_couplers_imp_OBU1DD m00_couplers
(.M_ACLK(M00_ACLK_1),
.M_ARESETN(M00_ARESETN_1),
.M_AXI_araddr(m00_couplers_to_processing_system7_0_axi_periph_ARADDR),
.M_AXI_arready(m00_couplers_to_processing_system7_0_axi_periph_ARREADY),
.M_AXI_arvalid(m00_couplers_to_processing_system7_0_axi_periph_ARVALID),
.M_AXI_awaddr(m00_couplers_to_processing_system7_0_axi_periph_AWADDR),
.M_AXI_awready(m00_couplers_to_processing_system7_0_axi_periph_AWREADY),
.M_AXI_awvalid(m00_couplers_to_processing_system7_0_axi_periph_AWVALID),
.M_AXI_bready(m00_couplers_to_processing_system7_0_axi_periph_BREADY),
.M_AXI_bresp(m00_couplers_to_processing_system7_0_axi_periph_BRESP),
.M_AXI_bvalid(m00_couplers_to_processing_system7_0_axi_periph_BVALID),
.M_AXI_rdata(m00_couplers_to_processing_system7_0_axi_periph_RDATA),
.M_AXI_rready(m00_couplers_to_processing_system7_0_axi_periph_RREADY),
.M_AXI_rresp(m00_couplers_to_processing_system7_0_axi_periph_RRESP),
.M_AXI_rvalid(m00_couplers_to_processing_system7_0_axi_periph_RVALID),
.M_AXI_wdata(m00_couplers_to_processing_system7_0_axi_periph_WDATA),
.M_AXI_wready(m00_couplers_to_processing_system7_0_axi_periph_WREADY),
.M_AXI_wvalid(m00_couplers_to_processing_system7_0_axi_periph_WVALID),
.S_ACLK(processing_system7_0_axi_periph_ACLK_net),
.S_ARESETN(processing_system7_0_axi_periph_ARESETN_net),
.S_AXI_araddr(xbar_to_m00_couplers_ARADDR),
.S_AXI_arready(xbar_to_m00_couplers_ARREADY),
.S_AXI_arvalid(xbar_to_m00_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m00_couplers_AWADDR),
.S_AXI_awready(xbar_to_m00_couplers_AWREADY),
.S_AXI_awvalid(xbar_to_m00_couplers_AWVALID),
.S_AXI_bready(xbar_to_m00_couplers_BREADY),
.S_AXI_bresp(xbar_to_m00_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m00_couplers_BVALID),
.S_AXI_rdata(xbar_to_m00_couplers_RDATA),
.S_AXI_rready(xbar_to_m00_couplers_RREADY),
.S_AXI_rresp(xbar_to_m00_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m00_couplers_RVALID),
.S_AXI_wdata(xbar_to_m00_couplers_WDATA),
.S_AXI_wready(xbar_to_m00_couplers_WREADY),
.S_AXI_wvalid(xbar_to_m00_couplers_WVALID));
m01_couplers_imp_1FBREZ4 m01_couplers
(.M_ACLK(M01_ACLK_1),
.M_ARESETN(M01_ARESETN_1),
.M_AXI_araddr(m01_couplers_to_processing_system7_0_axi_periph_ARADDR),
.M_AXI_arready(m01_couplers_to_processing_system7_0_axi_periph_ARREADY),
.M_AXI_arvalid(m01_couplers_to_processing_system7_0_axi_periph_ARVALID),
.M_AXI_awaddr(m01_couplers_to_processing_system7_0_axi_periph_AWADDR),
.M_AXI_awready(m01_couplers_to_processing_system7_0_axi_periph_AWREADY),
.M_AXI_awvalid(m01_couplers_to_processing_system7_0_axi_periph_AWVALID),
.M_AXI_bready(m01_couplers_to_processing_system7_0_axi_periph_BREADY),
.M_AXI_bresp(m01_couplers_to_processing_system7_0_axi_periph_BRESP),
.M_AXI_bvalid(m01_couplers_to_processing_system7_0_axi_periph_BVALID),
.M_AXI_rdata(m01_couplers_to_processing_system7_0_axi_periph_RDATA),
.M_AXI_rready(m01_couplers_to_processing_system7_0_axi_periph_RREADY),
.M_AXI_rresp(m01_couplers_to_processing_system7_0_axi_periph_RRESP),
.M_AXI_rvalid(m01_couplers_to_processing_system7_0_axi_periph_RVALID),
.M_AXI_wdata(m01_couplers_to_processing_system7_0_axi_periph_WDATA),
.M_AXI_wready(m01_couplers_to_processing_system7_0_axi_periph_WREADY),
.M_AXI_wstrb(m01_couplers_to_processing_system7_0_axi_periph_WSTRB),
.M_AXI_wvalid(m01_couplers_to_processing_system7_0_axi_periph_WVALID),
.S_ACLK(processing_system7_0_axi_periph_ACLK_net),
.S_ARESETN(processing_system7_0_axi_periph_ARESETN_net),
.S_AXI_araddr(xbar_to_m01_couplers_ARADDR),
.S_AXI_arready(xbar_to_m01_couplers_ARREADY),
.S_AXI_arvalid(xbar_to_m01_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m01_couplers_AWADDR),
.S_AXI_awready(xbar_to_m01_couplers_AWREADY),
.S_AXI_awvalid(xbar_to_m01_couplers_AWVALID),
.S_AXI_bready(xbar_to_m01_couplers_BREADY),
.S_AXI_bresp(xbar_to_m01_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m01_couplers_BVALID),
.S_AXI_rdata(xbar_to_m01_couplers_RDATA),
.S_AXI_rready(xbar_to_m01_couplers_RREADY),
.S_AXI_rresp(xbar_to_m01_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m01_couplers_RVALID),
.S_AXI_wdata(xbar_to_m01_couplers_WDATA),
.S_AXI_wready(xbar_to_m01_couplers_WREADY),
.S_AXI_wstrb(xbar_to_m01_couplers_WSTRB),
.S_AXI_wvalid(xbar_to_m01_couplers_WVALID));
m02_couplers_imp_MVV5YQ m02_couplers
(.M_ACLK(M02_ACLK_1),
.M_ARESETN(M02_ARESETN_1),
.M_AXI_araddr(m02_couplers_to_processing_system7_0_axi_periph_ARADDR),
.M_AXI_arready(m02_couplers_to_processing_system7_0_axi_periph_ARREADY),
.M_AXI_arvalid(m02_couplers_to_processing_system7_0_axi_periph_ARVALID),
.M_AXI_awaddr(m02_couplers_to_processing_system7_0_axi_periph_AWADDR),
.M_AXI_awready(m02_couplers_to_processing_system7_0_axi_periph_AWREADY),
.M_AXI_awvalid(m02_couplers_to_processing_system7_0_axi_periph_AWVALID),
.M_AXI_bready(m02_couplers_to_processing_system7_0_axi_periph_BREADY),
.M_AXI_bresp(m02_couplers_to_processing_system7_0_axi_periph_BRESP),
.M_AXI_bvalid(m02_couplers_to_processing_system7_0_axi_periph_BVALID),
.M_AXI_rdata(m02_couplers_to_processing_system7_0_axi_periph_RDATA),
.M_AXI_rready(m02_couplers_to_processing_system7_0_axi_periph_RREADY),
.M_AXI_rresp(m02_couplers_to_processing_system7_0_axi_periph_RRESP),
.M_AXI_rvalid(m02_couplers_to_processing_system7_0_axi_periph_RVALID),
.M_AXI_wdata(m02_couplers_to_processing_system7_0_axi_periph_WDATA),
.M_AXI_wready(m02_couplers_to_processing_system7_0_axi_periph_WREADY),
.M_AXI_wvalid(m02_couplers_to_processing_system7_0_axi_periph_WVALID),
.S_ACLK(processing_system7_0_axi_periph_ACLK_net),
.S_ARESETN(processing_system7_0_axi_periph_ARESETN_net),
.S_AXI_araddr(xbar_to_m02_couplers_ARADDR),
.S_AXI_arready(xbar_to_m02_couplers_ARREADY),
.S_AXI_arvalid(xbar_to_m02_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m02_couplers_AWADDR),
.S_AXI_awready(xbar_to_m02_couplers_AWREADY),
.S_AXI_awvalid(xbar_to_m02_couplers_AWVALID),
.S_AXI_bready(xbar_to_m02_couplers_BREADY),
.S_AXI_bresp(xbar_to_m02_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m02_couplers_BVALID),
.S_AXI_rdata(xbar_to_m02_couplers_RDATA),
.S_AXI_rready(xbar_to_m02_couplers_RREADY),
.S_AXI_rresp(xbar_to_m02_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m02_couplers_RVALID),
.S_AXI_wdata(xbar_to_m02_couplers_WDATA),
.S_AXI_wready(xbar_to_m02_couplers_WREADY),
.S_AXI_wvalid(xbar_to_m02_couplers_WVALID));
m03_couplers_imp_1GHG26R m03_couplers
(.M_ACLK(M03_ACLK_1),
.M_ARESETN(M03_ARESETN_1),
.M_AXI_araddr(m03_couplers_to_processing_system7_0_axi_periph_ARADDR),
.M_AXI_arready(m03_couplers_to_processing_system7_0_axi_periph_ARREADY),
.M_AXI_arvalid(m03_couplers_to_processing_system7_0_axi_periph_ARVALID),
.M_AXI_awaddr(m03_couplers_to_processing_system7_0_axi_periph_AWADDR),
.M_AXI_awready(m03_couplers_to_processing_system7_0_axi_periph_AWREADY),
.M_AXI_awvalid(m03_couplers_to_processing_system7_0_axi_periph_AWVALID),
.M_AXI_bready(m03_couplers_to_processing_system7_0_axi_periph_BREADY),
.M_AXI_bresp(m03_couplers_to_processing_system7_0_axi_periph_BRESP),
.M_AXI_bvalid(m03_couplers_to_processing_system7_0_axi_periph_BVALID),
.M_AXI_rdata(m03_couplers_to_processing_system7_0_axi_periph_RDATA),
.M_AXI_rready(m03_couplers_to_processing_system7_0_axi_periph_RREADY),
.M_AXI_rresp(m03_couplers_to_processing_system7_0_axi_periph_RRESP),
.M_AXI_rvalid(m03_couplers_to_processing_system7_0_axi_periph_RVALID),
.M_AXI_wdata(m03_couplers_to_processing_system7_0_axi_periph_WDATA),
.M_AXI_wready(m03_couplers_to_processing_system7_0_axi_periph_WREADY),
.M_AXI_wvalid(m03_couplers_to_processing_system7_0_axi_periph_WVALID),
.S_ACLK(processing_system7_0_axi_periph_ACLK_net),
.S_ARESETN(processing_system7_0_axi_periph_ARESETN_net),
.S_AXI_araddr(xbar_to_m03_couplers_ARADDR),
.S_AXI_arready(xbar_to_m03_couplers_ARREADY),
.S_AXI_arvalid(xbar_to_m03_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m03_couplers_AWADDR),
.S_AXI_awready(xbar_to_m03_couplers_AWREADY),
.S_AXI_awvalid(xbar_to_m03_couplers_AWVALID),
.S_AXI_bready(xbar_to_m03_couplers_BREADY),
.S_AXI_bresp(xbar_to_m03_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m03_couplers_BVALID),
.S_AXI_rdata(xbar_to_m03_couplers_RDATA),
.S_AXI_rready(xbar_to_m03_couplers_RREADY),
.S_AXI_rresp(xbar_to_m03_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m03_couplers_RVALID),
.S_AXI_wdata(xbar_to_m03_couplers_WDATA),
.S_AXI_wready(xbar_to_m03_couplers_WREADY),
.S_AXI_wvalid(xbar_to_m03_couplers_WVALID));
s00_couplers_imp_1CFO1MB s00_couplers
(.M_ACLK(processing_system7_0_axi_periph_ACLK_net),
.M_ARESETN(processing_system7_0_axi_periph_ARESETN_net),
.M_AXI_araddr(s00_couplers_to_xbar_ARADDR),
.M_AXI_arprot(s00_couplers_to_xbar_ARPROT),
.M_AXI_arready(s00_couplers_to_xbar_ARREADY),
.M_AXI_arvalid(s00_couplers_to_xbar_ARVALID),
.M_AXI_awaddr(s00_couplers_to_xbar_AWADDR),
.M_AXI_awprot(s00_couplers_to_xbar_AWPROT),
.M_AXI_awready(s00_couplers_to_xbar_AWREADY),
.M_AXI_awvalid(s00_couplers_to_xbar_AWVALID),
.M_AXI_bready(s00_couplers_to_xbar_BREADY),
.M_AXI_bresp(s00_couplers_to_xbar_BRESP),
.M_AXI_bvalid(s00_couplers_to_xbar_BVALID),
.M_AXI_rdata(s00_couplers_to_xbar_RDATA),
.M_AXI_rready(s00_couplers_to_xbar_RREADY),
.M_AXI_rresp(s00_couplers_to_xbar_RRESP),
.M_AXI_rvalid(s00_couplers_to_xbar_RVALID),
.M_AXI_wdata(s00_couplers_to_xbar_WDATA),
.M_AXI_wready(s00_couplers_to_xbar_WREADY),
.M_AXI_wstrb(s00_couplers_to_xbar_WSTRB),
.M_AXI_wvalid(s00_couplers_to_xbar_WVALID),
.S_ACLK(S00_ACLK_1),
.S_ARESETN(S00_ARESETN_1),
.S_AXI_araddr(processing_system7_0_axi_periph_to_s00_couplers_ARADDR),
.S_AXI_arburst(processing_system7_0_axi_periph_to_s00_couplers_ARBURST),
.S_AXI_arcache(processing_system7_0_axi_periph_to_s00_couplers_ARCACHE),
.S_AXI_arid(processing_system7_0_axi_periph_to_s00_couplers_ARID),
.S_AXI_arlen(processing_system7_0_axi_periph_to_s00_couplers_ARLEN),
.S_AXI_arlock(processing_system7_0_axi_periph_to_s00_couplers_ARLOCK),
.S_AXI_arprot(processing_system7_0_axi_periph_to_s00_couplers_ARPROT),
.S_AXI_arqos(processing_system7_0_axi_periph_to_s00_couplers_ARQOS),
.S_AXI_arready(processing_system7_0_axi_periph_to_s00_couplers_ARREADY),
.S_AXI_arsize(processing_system7_0_axi_periph_to_s00_couplers_ARSIZE),
.S_AXI_arvalid(processing_system7_0_axi_periph_to_s00_couplers_ARVALID),
.S_AXI_awaddr(processing_system7_0_axi_periph_to_s00_couplers_AWADDR),
.S_AXI_awburst(processing_system7_0_axi_periph_to_s00_couplers_AWBURST),
.S_AXI_awcache(processing_system7_0_axi_periph_to_s00_couplers_AWCACHE),
.S_AXI_awid(processing_system7_0_axi_periph_to_s00_couplers_AWID),
.S_AXI_awlen(processing_system7_0_axi_periph_to_s00_couplers_AWLEN),
.S_AXI_awlock(processing_system7_0_axi_periph_to_s00_couplers_AWLOCK),
.S_AXI_awprot(processing_system7_0_axi_periph_to_s00_couplers_AWPROT),
.S_AXI_awqos(processing_system7_0_axi_periph_to_s00_couplers_AWQOS),
.S_AXI_awready(processing_system7_0_axi_periph_to_s00_couplers_AWREADY),
.S_AXI_awsize(processing_system7_0_axi_periph_to_s00_couplers_AWSIZE),
.S_AXI_awvalid(processing_system7_0_axi_periph_to_s00_couplers_AWVALID),
.S_AXI_bid(processing_system7_0_axi_periph_to_s00_couplers_BID),
.S_AXI_bready(processing_system7_0_axi_periph_to_s00_couplers_BREADY),
.S_AXI_bresp(processing_system7_0_axi_periph_to_s00_couplers_BRESP),
.S_AXI_bvalid(processing_system7_0_axi_periph_to_s00_couplers_BVALID),
.S_AXI_rdata(processing_system7_0_axi_periph_to_s00_couplers_RDATA),
.S_AXI_rid(processing_system7_0_axi_periph_to_s00_couplers_RID),
.S_AXI_rlast(processing_system7_0_axi_periph_to_s00_couplers_RLAST),
.S_AXI_rready(processing_system7_0_axi_periph_to_s00_couplers_RREADY),
.S_AXI_rresp(processing_system7_0_axi_periph_to_s00_couplers_RRESP),
.S_AXI_rvalid(processing_system7_0_axi_periph_to_s00_couplers_RVALID),
.S_AXI_wdata(processing_system7_0_axi_periph_to_s00_couplers_WDATA),
.S_AXI_wid(processing_system7_0_axi_periph_to_s00_couplers_WID),
.S_AXI_wlast(processing_system7_0_axi_periph_to_s00_couplers_WLAST),
.S_AXI_wready(processing_system7_0_axi_periph_to_s00_couplers_WREADY),
.S_AXI_wstrb(processing_system7_0_axi_periph_to_s00_couplers_WSTRB),
.S_AXI_wvalid(processing_system7_0_axi_periph_to_s00_couplers_WVALID));
design_1_xbar_1 xbar
(.aclk(processing_system7_0_axi_periph_ACLK_net),
.aresetn(processing_system7_0_axi_periph_ARESETN_net),
.m_axi_araddr({xbar_to_m03_couplers_ARADDR,xbar_to_m02_couplers_ARADDR,xbar_to_m01_couplers_ARADDR,xbar_to_m00_couplers_ARADDR}),
.m_axi_arready({xbar_to_m03_couplers_ARREADY,xbar_to_m02_couplers_ARREADY,xbar_to_m01_couplers_ARREADY,xbar_to_m00_couplers_ARREADY}),
.m_axi_arvalid({xbar_to_m03_couplers_ARVALID,xbar_to_m02_couplers_ARVALID,xbar_to_m01_couplers_ARVALID,xbar_to_m00_couplers_ARVALID}),
.m_axi_awaddr({xbar_to_m03_couplers_AWADDR,xbar_to_m02_couplers_AWADDR,xbar_to_m01_couplers_AWADDR,xbar_to_m00_couplers_AWADDR}),
.m_axi_awready({xbar_to_m03_couplers_AWREADY,xbar_to_m02_couplers_AWREADY,xbar_to_m01_couplers_AWREADY,xbar_to_m00_couplers_AWREADY}),
.m_axi_awvalid({xbar_to_m03_couplers_AWVALID,xbar_to_m02_couplers_AWVALID,xbar_to_m01_couplers_AWVALID,xbar_to_m00_couplers_AWVALID}),
.m_axi_bready({xbar_to_m03_couplers_BREADY,xbar_to_m02_couplers_BREADY,xbar_to_m01_couplers_BREADY,xbar_to_m00_couplers_BREADY}),
.m_axi_bresp({xbar_to_m03_couplers_BRESP,xbar_to_m02_couplers_BRESP,xbar_to_m01_couplers_BRESP,xbar_to_m00_couplers_BRESP}),
.m_axi_bvalid({xbar_to_m03_couplers_BVALID,xbar_to_m02_couplers_BVALID,xbar_to_m01_couplers_BVALID,xbar_to_m00_couplers_BVALID}),
.m_axi_rdata({xbar_to_m03_couplers_RDATA,xbar_to_m02_couplers_RDATA,xbar_to_m01_couplers_RDATA,xbar_to_m00_couplers_RDATA}),
.m_axi_rready({xbar_to_m03_couplers_RREADY,xbar_to_m02_couplers_RREADY,xbar_to_m01_couplers_RREADY,xbar_to_m00_couplers_RREADY}),
.m_axi_rresp({xbar_to_m03_couplers_RRESP,xbar_to_m02_couplers_RRESP,xbar_to_m01_couplers_RRESP,xbar_to_m00_couplers_RRESP}),
.m_axi_rvalid({xbar_to_m03_couplers_RVALID,xbar_to_m02_couplers_RVALID,xbar_to_m01_couplers_RVALID,xbar_to_m00_couplers_RVALID}),
.m_axi_wdata({xbar_to_m03_couplers_WDATA,xbar_to_m02_couplers_WDATA,xbar_to_m01_couplers_WDATA,xbar_to_m00_couplers_WDATA}),
.m_axi_wready({xbar_to_m03_couplers_WREADY,xbar_to_m02_couplers_WREADY,xbar_to_m01_couplers_WREADY,xbar_to_m00_couplers_WREADY}),
.m_axi_wstrb({xbar_to_m01_couplers_WSTRB,NLW_xbar_m_axi_wstrb_UNCONNECTED[3:0]}),
.m_axi_wvalid({xbar_to_m03_couplers_WVALID,xbar_to_m02_couplers_WVALID,xbar_to_m01_couplers_WVALID,xbar_to_m00_couplers_WVALID}),
.s_axi_araddr(s00_couplers_to_xbar_ARADDR),
.s_axi_arprot(s00_couplers_to_xbar_ARPROT),
.s_axi_arready(s00_couplers_to_xbar_ARREADY),
.s_axi_arvalid(s00_couplers_to_xbar_ARVALID),
.s_axi_awaddr(s00_couplers_to_xbar_AWADDR),
.s_axi_awprot(s00_couplers_to_xbar_AWPROT),
.s_axi_awready(s00_couplers_to_xbar_AWREADY),
.s_axi_awvalid(s00_couplers_to_xbar_AWVALID),
.s_axi_bready(s00_couplers_to_xbar_BREADY),
.s_axi_bresp(s00_couplers_to_xbar_BRESP),
.s_axi_bvalid(s00_couplers_to_xbar_BVALID),
.s_axi_rdata(s00_couplers_to_xbar_RDATA),
.s_axi_rready(s00_couplers_to_xbar_RREADY),
.s_axi_rresp(s00_couplers_to_xbar_RRESP),
.s_axi_rvalid(s00_couplers_to_xbar_RVALID),
.s_axi_wdata(s00_couplers_to_xbar_WDATA),
.s_axi_wready(s00_couplers_to_xbar_WREADY),
.s_axi_wstrb(s00_couplers_to_xbar_WSTRB),
.s_axi_wvalid(s00_couplers_to_xbar_WVALID));
endmodule
module hier_bram_0_imp_1VW8SCX
(ARESETN,
BRAM_PORTB_addr,
BRAM_PORTB_clk,
BRAM_PORTB_din,
BRAM_PORTB_dout,
BRAM_PORTB_en,
BRAM_PORTB_rst,
BRAM_PORTB_we,
M00_AXI_araddr,
M00_AXI_arburst,
M00_AXI_arcache,
M00_AXI_arlen,
M00_AXI_arlock,
M00_AXI_arprot,
M00_AXI_arqos,
M00_AXI_arready,
M00_AXI_arsize,
M00_AXI_arvalid,
M00_AXI_awaddr,
M00_AXI_awburst,
M00_AXI_awcache,
M00_AXI_awlen,
M00_AXI_awlock,
M00_AXI_awprot,
M00_AXI_awqos,
M00_AXI_awready,
M00_AXI_awsize,
M00_AXI_awvalid,
M00_AXI_bready,
M00_AXI_bresp,
M00_AXI_bvalid,
M00_AXI_rdata,
M00_AXI_rlast,
M00_AXI_rready,
M00_AXI_rresp,
M00_AXI_rvalid,
M00_AXI_wdata,
M00_AXI_wlast,
M00_AXI_wready,
M00_AXI_wstrb,
M00_AXI_wvalid,
S_AXI_LITE_araddr,
S_AXI_LITE_arready,
S_AXI_LITE_arvalid,
S_AXI_LITE_awaddr,
S_AXI_LITE_awready,
S_AXI_LITE_awvalid,
S_AXI_LITE_bready,
S_AXI_LITE_bresp,
S_AXI_LITE_bvalid,
S_AXI_LITE_rdata,
S_AXI_LITE_rready,
S_AXI_LITE_rresp,
S_AXI_LITE_rvalid,
S_AXI_LITE_wdata,
S_AXI_LITE_wready,
S_AXI_LITE_wvalid,
s_axi_lite_aclk,
s_axi_lite_aresetn);
input [0:0]ARESETN;
input [31:0]BRAM_PORTB_addr;
input BRAM_PORTB_clk;
input [31:0]BRAM_PORTB_din;
output [31:0]BRAM_PORTB_dout;
input BRAM_PORTB_en;
input BRAM_PORTB_rst;
input [3:0]BRAM_PORTB_we;
output [31:0]M00_AXI_araddr;
output [1:0]M00_AXI_arburst;
output [3:0]M00_AXI_arcache;
output [3:0]M00_AXI_arlen;
output [1:0]M00_AXI_arlock;
output [2:0]M00_AXI_arprot;
output [3:0]M00_AXI_arqos;
input M00_AXI_arready;
output [2:0]M00_AXI_arsize;
output M00_AXI_arvalid;
output [31:0]M00_AXI_awaddr;
output [1:0]M00_AXI_awburst;
output [3:0]M00_AXI_awcache;
output [3:0]M00_AXI_awlen;
output [1:0]M00_AXI_awlock;
output [2:0]M00_AXI_awprot;
output [3:0]M00_AXI_awqos;
input M00_AXI_awready;
output [2:0]M00_AXI_awsize;
output M00_AXI_awvalid;
output M00_AXI_bready;
input [1:0]M00_AXI_bresp;
input M00_AXI_bvalid;
input [63:0]M00_AXI_rdata;
input M00_AXI_rlast;
output M00_AXI_rready;
input [1:0]M00_AXI_rresp;
input M00_AXI_rvalid;
output [63:0]M00_AXI_wdata;
output M00_AXI_wlast;
input M00_AXI_wready;
output [7:0]M00_AXI_wstrb;
output M00_AXI_wvalid;
input [31:0]S_AXI_LITE_araddr;
output [0:0]S_AXI_LITE_arready;
input [0:0]S_AXI_LITE_arvalid;
input [31:0]S_AXI_LITE_awaddr;
output [0:0]S_AXI_LITE_awready;
input [0:0]S_AXI_LITE_awvalid;
input [0:0]S_AXI_LITE_bready;
output [1:0]S_AXI_LITE_bresp;
output [0:0]S_AXI_LITE_bvalid;
output [31:0]S_AXI_LITE_rdata;
input [0:0]S_AXI_LITE_rready;
output [1:0]S_AXI_LITE_rresp;
output [0:0]S_AXI_LITE_rvalid;
input [31:0]S_AXI_LITE_wdata;
output [0:0]S_AXI_LITE_wready;
input [0:0]S_AXI_LITE_wvalid;
input s_axi_lite_aclk;
input [0:0]s_axi_lite_aresetn;
wire [12:0]axi_bram_ctrl_0_BRAM_PORTA_ADDR;
wire axi_bram_ctrl_0_BRAM_PORTA_CLK;
wire [31:0]axi_bram_ctrl_0_BRAM_PORTA_DIN;
wire [31:0]axi_bram_ctrl_0_BRAM_PORTA_DOUT;
wire axi_bram_ctrl_0_BRAM_PORTA_EN;
wire axi_bram_ctrl_0_BRAM_PORTA_RST;
wire [3:0]axi_bram_ctrl_0_BRAM_PORTA_WE;
wire [31:0]axi_cdma_0_M_AXI_ARADDR;
wire [1:0]axi_cdma_0_M_AXI_ARBURST;
wire [3:0]axi_cdma_0_M_AXI_ARCACHE;
wire [7:0]axi_cdma_0_M_AXI_ARLEN;
wire [2:0]axi_cdma_0_M_AXI_ARPROT;
wire axi_cdma_0_M_AXI_ARREADY;
wire [2:0]axi_cdma_0_M_AXI_ARSIZE;
wire axi_cdma_0_M_AXI_ARVALID;
wire [31:0]axi_cdma_0_M_AXI_AWADDR;
wire [1:0]axi_cdma_0_M_AXI_AWBURST;
wire [3:0]axi_cdma_0_M_AXI_AWCACHE;
wire [7:0]axi_cdma_0_M_AXI_AWLEN;
wire [2:0]axi_cdma_0_M_AXI_AWPROT;
wire axi_cdma_0_M_AXI_AWREADY;
wire [2:0]axi_cdma_0_M_AXI_AWSIZE;
wire axi_cdma_0_M_AXI_AWVALID;
wire axi_cdma_0_M_AXI_BREADY;
wire [1:0]axi_cdma_0_M_AXI_BRESP;
wire axi_cdma_0_M_AXI_BVALID;
wire [31:0]axi_cdma_0_M_AXI_RDATA;
wire axi_cdma_0_M_AXI_RLAST;
wire axi_cdma_0_M_AXI_RREADY;
wire [1:0]axi_cdma_0_M_AXI_RRESP;
wire axi_cdma_0_M_AXI_RVALID;
wire [31:0]axi_cdma_0_M_AXI_WDATA;
wire axi_cdma_0_M_AXI_WLAST;
wire axi_cdma_0_M_AXI_WREADY;
wire [3:0]axi_cdma_0_M_AXI_WSTRB;
wire axi_cdma_0_M_AXI_WVALID;
wire [31:0]axi_mem_intercon_M00_AXI_ARADDR;
wire [1:0]axi_mem_intercon_M00_AXI_ARBURST;
wire [3:0]axi_mem_intercon_M00_AXI_ARCACHE;
wire [3:0]axi_mem_intercon_M00_AXI_ARLEN;
wire [1:0]axi_mem_intercon_M00_AXI_ARLOCK;
wire [2:0]axi_mem_intercon_M00_AXI_ARPROT;
wire [3:0]axi_mem_intercon_M00_AXI_ARQOS;
wire axi_mem_intercon_M00_AXI_ARREADY;
wire [2:0]axi_mem_intercon_M00_AXI_ARSIZE;
wire axi_mem_intercon_M00_AXI_ARVALID;
wire [31:0]axi_mem_intercon_M00_AXI_AWADDR;
wire [1:0]axi_mem_intercon_M00_AXI_AWBURST;
wire [3:0]axi_mem_intercon_M00_AXI_AWCACHE;
wire [3:0]axi_mem_intercon_M00_AXI_AWLEN;
wire [1:0]axi_mem_intercon_M00_AXI_AWLOCK;
wire [2:0]axi_mem_intercon_M00_AXI_AWPROT;
wire [3:0]axi_mem_intercon_M00_AXI_AWQOS;
wire axi_mem_intercon_M00_AXI_AWREADY;
wire [2:0]axi_mem_intercon_M00_AXI_AWSIZE;
wire axi_mem_intercon_M00_AXI_AWVALID;
wire axi_mem_intercon_M00_AXI_BREADY;
wire [1:0]axi_mem_intercon_M00_AXI_BRESP;
wire axi_mem_intercon_M00_AXI_BVALID;
wire [63:0]axi_mem_intercon_M00_AXI_RDATA;
wire axi_mem_intercon_M00_AXI_RLAST;
wire axi_mem_intercon_M00_AXI_RREADY;
wire [1:0]axi_mem_intercon_M00_AXI_RRESP;
wire axi_mem_intercon_M00_AXI_RVALID;
wire [63:0]axi_mem_intercon_M00_AXI_WDATA;
wire axi_mem_intercon_M00_AXI_WLAST;
wire axi_mem_intercon_M00_AXI_WREADY;
wire [7:0]axi_mem_intercon_M00_AXI_WSTRB;
wire axi_mem_intercon_M00_AXI_WVALID;
wire [12:0]axi_mem_intercon_M01_AXI_ARADDR;
wire [1:0]axi_mem_intercon_M01_AXI_ARBURST;
wire [3:0]axi_mem_intercon_M01_AXI_ARCACHE;
wire [7:0]axi_mem_intercon_M01_AXI_ARLEN;
wire [0:0]axi_mem_intercon_M01_AXI_ARLOCK;
wire [2:0]axi_mem_intercon_M01_AXI_ARPROT;
wire axi_mem_intercon_M01_AXI_ARREADY;
wire [2:0]axi_mem_intercon_M01_AXI_ARSIZE;
wire axi_mem_intercon_M01_AXI_ARVALID;
wire [12:0]axi_mem_intercon_M01_AXI_AWADDR;
wire [1:0]axi_mem_intercon_M01_AXI_AWBURST;
wire [3:0]axi_mem_intercon_M01_AXI_AWCACHE;
wire [7:0]axi_mem_intercon_M01_AXI_AWLEN;
wire [0:0]axi_mem_intercon_M01_AXI_AWLOCK;
wire [2:0]axi_mem_intercon_M01_AXI_AWPROT;
wire axi_mem_intercon_M01_AXI_AWREADY;
wire [2:0]axi_mem_intercon_M01_AXI_AWSIZE;
wire axi_mem_intercon_M01_AXI_AWVALID;
wire axi_mem_intercon_M01_AXI_BREADY;
wire [1:0]axi_mem_intercon_M01_AXI_BRESP;
wire axi_mem_intercon_M01_AXI_BVALID;
wire [31:0]axi_mem_intercon_M01_AXI_RDATA;
wire axi_mem_intercon_M01_AXI_RLAST;
wire axi_mem_intercon_M01_AXI_RREADY;
wire [1:0]axi_mem_intercon_M01_AXI_RRESP;
wire axi_mem_intercon_M01_AXI_RVALID;
wire [31:0]axi_mem_intercon_M01_AXI_WDATA;
wire axi_mem_intercon_M01_AXI_WLAST;
wire axi_mem_intercon_M01_AXI_WREADY;
wire [3:0]axi_mem_intercon_M01_AXI_WSTRB;
wire axi_mem_intercon_M01_AXI_WVALID;
wire [31:0]matrix_mult_0_a_PORTA_ADDR;
wire matrix_mult_0_a_PORTA_CLK;
wire [31:0]matrix_mult_0_a_PORTA_DIN;
wire [31:0]matrix_mult_0_a_PORTA_DOUT;
wire matrix_mult_0_a_PORTA_EN;
wire matrix_mult_0_a_PORTA_RST;
wire [3:0]matrix_mult_0_a_PORTA_WE;
wire processing_system7_0_FCLK_CLK0;
wire [31:0]processing_system7_0_axi_periph_M00_AXI_ARADDR;
wire processing_system7_0_axi_periph_M00_AXI_ARREADY;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_ARVALID;
wire [31:0]processing_system7_0_axi_periph_M00_AXI_AWADDR;
wire processing_system7_0_axi_periph_M00_AXI_AWREADY;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_AWVALID;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_BREADY;
wire [1:0]processing_system7_0_axi_periph_M00_AXI_BRESP;
wire processing_system7_0_axi_periph_M00_AXI_BVALID;
wire [31:0]processing_system7_0_axi_periph_M00_AXI_RDATA;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_RREADY;
wire [1:0]processing_system7_0_axi_periph_M00_AXI_RRESP;
wire processing_system7_0_axi_periph_M00_AXI_RVALID;
wire [31:0]processing_system7_0_axi_periph_M00_AXI_WDATA;
wire processing_system7_0_axi_periph_M00_AXI_WREADY;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_WVALID;
wire [0:0]rst_processing_system7_0_100M_interconnect_aresetn;
wire [0:0]rst_processing_system7_0_100M_peripheral_aresetn;
assign BRAM_PORTB_dout[31:0] = matrix_mult_0_a_PORTA_DOUT;
assign M00_AXI_araddr[31:0] = axi_mem_intercon_M00_AXI_ARADDR;
assign M00_AXI_arburst[1:0] = axi_mem_intercon_M00_AXI_ARBURST;
assign M00_AXI_arcache[3:0] = axi_mem_intercon_M00_AXI_ARCACHE;
assign M00_AXI_arlen[3:0] = axi_mem_intercon_M00_AXI_ARLEN;
assign M00_AXI_arlock[1:0] = axi_mem_intercon_M00_AXI_ARLOCK;
assign M00_AXI_arprot[2:0] = axi_mem_intercon_M00_AXI_ARPROT;
assign M00_AXI_arqos[3:0] = axi_mem_intercon_M00_AXI_ARQOS;
assign M00_AXI_arsize[2:0] = axi_mem_intercon_M00_AXI_ARSIZE;
assign M00_AXI_arvalid = axi_mem_intercon_M00_AXI_ARVALID;
assign M00_AXI_awaddr[31:0] = axi_mem_intercon_M00_AXI_AWADDR;
assign M00_AXI_awburst[1:0] = axi_mem_intercon_M00_AXI_AWBURST;
assign M00_AXI_awcache[3:0] = axi_mem_intercon_M00_AXI_AWCACHE;
assign M00_AXI_awlen[3:0] = axi_mem_intercon_M00_AXI_AWLEN;
assign M00_AXI_awlock[1:0] = axi_mem_intercon_M00_AXI_AWLOCK;
assign M00_AXI_awprot[2:0] = axi_mem_intercon_M00_AXI_AWPROT;
assign M00_AXI_awqos[3:0] = axi_mem_intercon_M00_AXI_AWQOS;
assign M00_AXI_awsize[2:0] = axi_mem_intercon_M00_AXI_AWSIZE;
assign M00_AXI_awvalid = axi_mem_intercon_M00_AXI_AWVALID;
assign M00_AXI_bready = axi_mem_intercon_M00_AXI_BREADY;
assign M00_AXI_rready = axi_mem_intercon_M00_AXI_RREADY;
assign M00_AXI_wdata[63:0] = axi_mem_intercon_M00_AXI_WDATA;
assign M00_AXI_wlast = axi_mem_intercon_M00_AXI_WLAST;
assign M00_AXI_wstrb[7:0] = axi_mem_intercon_M00_AXI_WSTRB;
assign M00_AXI_wvalid = axi_mem_intercon_M00_AXI_WVALID;
assign S_AXI_LITE_arready[0] = processing_system7_0_axi_periph_M00_AXI_ARREADY;
assign S_AXI_LITE_awready[0] = processing_system7_0_axi_periph_M00_AXI_AWREADY;
assign S_AXI_LITE_bresp[1:0] = processing_system7_0_axi_periph_M00_AXI_BRESP;
assign S_AXI_LITE_bvalid[0] = processing_system7_0_axi_periph_M00_AXI_BVALID;
assign S_AXI_LITE_rdata[31:0] = processing_system7_0_axi_periph_M00_AXI_RDATA;
assign S_AXI_LITE_rresp[1:0] = processing_system7_0_axi_periph_M00_AXI_RRESP;
assign S_AXI_LITE_rvalid[0] = processing_system7_0_axi_periph_M00_AXI_RVALID;
assign S_AXI_LITE_wready[0] = processing_system7_0_axi_periph_M00_AXI_WREADY;
assign axi_mem_intercon_M00_AXI_ARREADY = M00_AXI_arready;
assign axi_mem_intercon_M00_AXI_AWREADY = M00_AXI_awready;
assign axi_mem_intercon_M00_AXI_BRESP = M00_AXI_bresp[1:0];
assign axi_mem_intercon_M00_AXI_BVALID = M00_AXI_bvalid;
assign axi_mem_intercon_M00_AXI_RDATA = M00_AXI_rdata[63:0];
assign axi_mem_intercon_M00_AXI_RLAST = M00_AXI_rlast;
assign axi_mem_intercon_M00_AXI_RRESP = M00_AXI_rresp[1:0];
assign axi_mem_intercon_M00_AXI_RVALID = M00_AXI_rvalid;
assign axi_mem_intercon_M00_AXI_WREADY = M00_AXI_wready;
assign matrix_mult_0_a_PORTA_ADDR = BRAM_PORTB_addr[31:0];
assign matrix_mult_0_a_PORTA_CLK = BRAM_PORTB_clk;
assign matrix_mult_0_a_PORTA_DIN = BRAM_PORTB_din[31:0];
assign matrix_mult_0_a_PORTA_EN = BRAM_PORTB_en;
assign matrix_mult_0_a_PORTA_RST = BRAM_PORTB_rst;
assign matrix_mult_0_a_PORTA_WE = BRAM_PORTB_we[3:0];
assign processing_system7_0_FCLK_CLK0 = s_axi_lite_aclk;
assign processing_system7_0_axi_periph_M00_AXI_ARADDR = S_AXI_LITE_araddr[31:0];
assign processing_system7_0_axi_periph_M00_AXI_ARVALID = S_AXI_LITE_arvalid[0];
assign processing_system7_0_axi_periph_M00_AXI_AWADDR = S_AXI_LITE_awaddr[31:0];
assign processing_system7_0_axi_periph_M00_AXI_AWVALID = S_AXI_LITE_awvalid[0];
assign processing_system7_0_axi_periph_M00_AXI_BREADY = S_AXI_LITE_bready[0];
assign processing_system7_0_axi_periph_M00_AXI_RREADY = S_AXI_LITE_rready[0];
assign processing_system7_0_axi_periph_M00_AXI_WDATA = S_AXI_LITE_wdata[31:0];
assign processing_system7_0_axi_periph_M00_AXI_WVALID = S_AXI_LITE_wvalid[0];
assign rst_processing_system7_0_100M_interconnect_aresetn = ARESETN[0];
assign rst_processing_system7_0_100M_peripheral_aresetn = s_axi_lite_aresetn[0];
design_1_axi_bram_ctrl_0_0 axi_bram_ctrl_0
(.bram_addr_a(axi_bram_ctrl_0_BRAM_PORTA_ADDR),
.bram_clk_a(axi_bram_ctrl_0_BRAM_PORTA_CLK),
.bram_en_a(axi_bram_ctrl_0_BRAM_PORTA_EN),
.bram_rddata_a(axi_bram_ctrl_0_BRAM_PORTA_DOUT),
.bram_rst_a(axi_bram_ctrl_0_BRAM_PORTA_RST),
.bram_we_a(axi_bram_ctrl_0_BRAM_PORTA_WE),
.bram_wrdata_a(axi_bram_ctrl_0_BRAM_PORTA_DIN),
.s_axi_aclk(processing_system7_0_FCLK_CLK0),
.s_axi_araddr(axi_mem_intercon_M01_AXI_ARADDR),
.s_axi_arburst(axi_mem_intercon_M01_AXI_ARBURST),
.s_axi_arcache(axi_mem_intercon_M01_AXI_ARCACHE),
.s_axi_aresetn(rst_processing_system7_0_100M_peripheral_aresetn),
.s_axi_arlen(axi_mem_intercon_M01_AXI_ARLEN),
.s_axi_arlock(axi_mem_intercon_M01_AXI_ARLOCK),
.s_axi_arprot(axi_mem_intercon_M01_AXI_ARPROT),
.s_axi_arready(axi_mem_intercon_M01_AXI_ARREADY),
.s_axi_arsize(axi_mem_intercon_M01_AXI_ARSIZE),
.s_axi_arvalid(axi_mem_intercon_M01_AXI_ARVALID),
.s_axi_awaddr(axi_mem_intercon_M01_AXI_AWADDR),
.s_axi_awburst(axi_mem_intercon_M01_AXI_AWBURST),
.s_axi_awcache(axi_mem_intercon_M01_AXI_AWCACHE),
.s_axi_awlen(axi_mem_intercon_M01_AXI_AWLEN),
.s_axi_awlock(axi_mem_intercon_M01_AXI_AWLOCK),
.s_axi_awprot(axi_mem_intercon_M01_AXI_AWPROT),
.s_axi_awready(axi_mem_intercon_M01_AXI_AWREADY),
.s_axi_awsize(axi_mem_intercon_M01_AXI_AWSIZE),
.s_axi_awvalid(axi_mem_intercon_M01_AXI_AWVALID),
.s_axi_bready(axi_mem_intercon_M01_AXI_BREADY),
.s_axi_bresp(axi_mem_intercon_M01_AXI_BRESP),
.s_axi_bvalid(axi_mem_intercon_M01_AXI_BVALID),
.s_axi_rdata(axi_mem_intercon_M01_AXI_RDATA),
.s_axi_rlast(axi_mem_intercon_M01_AXI_RLAST),
.s_axi_rready(axi_mem_intercon_M01_AXI_RREADY),
.s_axi_rresp(axi_mem_intercon_M01_AXI_RRESP),
.s_axi_rvalid(axi_mem_intercon_M01_AXI_RVALID),
.s_axi_wdata(axi_mem_intercon_M01_AXI_WDATA),
.s_axi_wlast(axi_mem_intercon_M01_AXI_WLAST),
.s_axi_wready(axi_mem_intercon_M01_AXI_WREADY),
.s_axi_wstrb(axi_mem_intercon_M01_AXI_WSTRB),
.s_axi_wvalid(axi_mem_intercon_M01_AXI_WVALID));
design_1_axi_cdma_0_0 axi_cdma_0
(.m_axi_aclk(processing_system7_0_FCLK_CLK0),
.m_axi_araddr(axi_cdma_0_M_AXI_ARADDR),
.m_axi_arburst(axi_cdma_0_M_AXI_ARBURST),
.m_axi_arcache(axi_cdma_0_M_AXI_ARCACHE),
.m_axi_arlen(axi_cdma_0_M_AXI_ARLEN),
.m_axi_arprot(axi_cdma_0_M_AXI_ARPROT),
.m_axi_arready(axi_cdma_0_M_AXI_ARREADY),
.m_axi_arsize(axi_cdma_0_M_AXI_ARSIZE),
.m_axi_arvalid(axi_cdma_0_M_AXI_ARVALID),
.m_axi_awaddr(axi_cdma_0_M_AXI_AWADDR),
.m_axi_awburst(axi_cdma_0_M_AXI_AWBURST),
.m_axi_awcache(axi_cdma_0_M_AXI_AWCACHE),
.m_axi_awlen(axi_cdma_0_M_AXI_AWLEN),
.m_axi_awprot(axi_cdma_0_M_AXI_AWPROT),
.m_axi_awready(axi_cdma_0_M_AXI_AWREADY),
.m_axi_awsize(axi_cdma_0_M_AXI_AWSIZE),
.m_axi_awvalid(axi_cdma_0_M_AXI_AWVALID),
.m_axi_bready(axi_cdma_0_M_AXI_BREADY),
.m_axi_bresp(axi_cdma_0_M_AXI_BRESP),
.m_axi_bvalid(axi_cdma_0_M_AXI_BVALID),
.m_axi_rdata(axi_cdma_0_M_AXI_RDATA),
.m_axi_rlast(axi_cdma_0_M_AXI_RLAST),
.m_axi_rready(axi_cdma_0_M_AXI_RREADY),
.m_axi_rresp(axi_cdma_0_M_AXI_RRESP),
.m_axi_rvalid(axi_cdma_0_M_AXI_RVALID),
.m_axi_wdata(axi_cdma_0_M_AXI_WDATA),
.m_axi_wlast(axi_cdma_0_M_AXI_WLAST),
.m_axi_wready(axi_cdma_0_M_AXI_WREADY),
.m_axi_wstrb(axi_cdma_0_M_AXI_WSTRB),
.m_axi_wvalid(axi_cdma_0_M_AXI_WVALID),
.s_axi_lite_aclk(processing_system7_0_FCLK_CLK0),
.s_axi_lite_araddr(processing_system7_0_axi_periph_M00_AXI_ARADDR[5:0]),
.s_axi_lite_aresetn(rst_processing_system7_0_100M_peripheral_aresetn),
.s_axi_lite_arready(processing_system7_0_axi_periph_M00_AXI_ARREADY),
.s_axi_lite_arvalid(processing_system7_0_axi_periph_M00_AXI_ARVALID),
.s_axi_lite_awaddr(processing_system7_0_axi_periph_M00_AXI_AWADDR[5:0]),
.s_axi_lite_awready(processing_system7_0_axi_periph_M00_AXI_AWREADY),
.s_axi_lite_awvalid(processing_system7_0_axi_periph_M00_AXI_AWVALID),
.s_axi_lite_bready(processing_system7_0_axi_periph_M00_AXI_BREADY),
.s_axi_lite_bresp(processing_system7_0_axi_periph_M00_AXI_BRESP),
.s_axi_lite_bvalid(processing_system7_0_axi_periph_M00_AXI_BVALID),
.s_axi_lite_rdata(processing_system7_0_axi_periph_M00_AXI_RDATA),
.s_axi_lite_rready(processing_system7_0_axi_periph_M00_AXI_RREADY),
.s_axi_lite_rresp(processing_system7_0_axi_periph_M00_AXI_RRESP),
.s_axi_lite_rvalid(processing_system7_0_axi_periph_M00_AXI_RVALID),
.s_axi_lite_wdata(processing_system7_0_axi_periph_M00_AXI_WDATA),
.s_axi_lite_wready(processing_system7_0_axi_periph_M00_AXI_WREADY),
.s_axi_lite_wvalid(processing_system7_0_axi_periph_M00_AXI_WVALID));
design_1_axi_mem_intercon_1 axi_mem_intercon
(.ACLK(processing_system7_0_FCLK_CLK0),
.ARESETN(rst_processing_system7_0_100M_interconnect_aresetn),
.M00_ACLK(processing_system7_0_FCLK_CLK0),
.M00_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.M00_AXI_araddr(axi_mem_intercon_M00_AXI_ARADDR),
.M00_AXI_arburst(axi_mem_intercon_M00_AXI_ARBURST),
.M00_AXI_arcache(axi_mem_intercon_M00_AXI_ARCACHE),
.M00_AXI_arlen(axi_mem_intercon_M00_AXI_ARLEN),
.M00_AXI_arlock(axi_mem_intercon_M00_AXI_ARLOCK),
.M00_AXI_arprot(axi_mem_intercon_M00_AXI_ARPROT),
.M00_AXI_arqos(axi_mem_intercon_M00_AXI_ARQOS),
.M00_AXI_arready(axi_mem_intercon_M00_AXI_ARREADY),
.M00_AXI_arsize(axi_mem_intercon_M00_AXI_ARSIZE),
.M00_AXI_arvalid(axi_mem_intercon_M00_AXI_ARVALID),
.M00_AXI_awaddr(axi_mem_intercon_M00_AXI_AWADDR),
.M00_AXI_awburst(axi_mem_intercon_M00_AXI_AWBURST),
.M00_AXI_awcache(axi_mem_intercon_M00_AXI_AWCACHE),
.M00_AXI_awlen(axi_mem_intercon_M00_AXI_AWLEN),
.M00_AXI_awlock(axi_mem_intercon_M00_AXI_AWLOCK),
.M00_AXI_awprot(axi_mem_intercon_M00_AXI_AWPROT),
.M00_AXI_awqos(axi_mem_intercon_M00_AXI_AWQOS),
.M00_AXI_awready(axi_mem_intercon_M00_AXI_AWREADY),
.M00_AXI_awsize(axi_mem_intercon_M00_AXI_AWSIZE),
.M00_AXI_awvalid(axi_mem_intercon_M00_AXI_AWVALID),
.M00_AXI_bready(axi_mem_intercon_M00_AXI_BREADY),
.M00_AXI_bresp(axi_mem_intercon_M00_AXI_BRESP),
.M00_AXI_bvalid(axi_mem_intercon_M00_AXI_BVALID),
.M00_AXI_rdata(axi_mem_intercon_M00_AXI_RDATA),
.M00_AXI_rlast(axi_mem_intercon_M00_AXI_RLAST),
.M00_AXI_rready(axi_mem_intercon_M00_AXI_RREADY),
.M00_AXI_rresp(axi_mem_intercon_M00_AXI_RRESP),
.M00_AXI_rvalid(axi_mem_intercon_M00_AXI_RVALID),
.M00_AXI_wdata(axi_mem_intercon_M00_AXI_WDATA),
.M00_AXI_wlast(axi_mem_intercon_M00_AXI_WLAST),
.M00_AXI_wready(axi_mem_intercon_M00_AXI_WREADY),
.M00_AXI_wstrb(axi_mem_intercon_M00_AXI_WSTRB),
.M00_AXI_wvalid(axi_mem_intercon_M00_AXI_WVALID),
.M01_ACLK(processing_system7_0_FCLK_CLK0),
.M01_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.M01_AXI_araddr(axi_mem_intercon_M01_AXI_ARADDR),
.M01_AXI_arburst(axi_mem_intercon_M01_AXI_ARBURST),
.M01_AXI_arcache(axi_mem_intercon_M01_AXI_ARCACHE),
.M01_AXI_arlen(axi_mem_intercon_M01_AXI_ARLEN),
.M01_AXI_arlock(axi_mem_intercon_M01_AXI_ARLOCK),
.M01_AXI_arprot(axi_mem_intercon_M01_AXI_ARPROT),
.M01_AXI_arready(axi_mem_intercon_M01_AXI_ARREADY),
.M01_AXI_arsize(axi_mem_intercon_M01_AXI_ARSIZE),
.M01_AXI_arvalid(axi_mem_intercon_M01_AXI_ARVALID),
.M01_AXI_awaddr(axi_mem_intercon_M01_AXI_AWADDR),
.M01_AXI_awburst(axi_mem_intercon_M01_AXI_AWBURST),
.M01_AXI_awcache(axi_mem_intercon_M01_AXI_AWCACHE),
.M01_AXI_awlen(axi_mem_intercon_M01_AXI_AWLEN),
.M01_AXI_awlock(axi_mem_intercon_M01_AXI_AWLOCK),
.M01_AXI_awprot(axi_mem_intercon_M01_AXI_AWPROT),
.M01_AXI_awready(axi_mem_intercon_M01_AXI_AWREADY),
.M01_AXI_awsize(axi_mem_intercon_M01_AXI_AWSIZE),
.M01_AXI_awvalid(axi_mem_intercon_M01_AXI_AWVALID),
.M01_AXI_bready(axi_mem_intercon_M01_AXI_BREADY),
.M01_AXI_bresp(axi_mem_intercon_M01_AXI_BRESP),
.M01_AXI_bvalid(axi_mem_intercon_M01_AXI_BVALID),
.M01_AXI_rdata(axi_mem_intercon_M01_AXI_RDATA),
.M01_AXI_rlast(axi_mem_intercon_M01_AXI_RLAST),
.M01_AXI_rready(axi_mem_intercon_M01_AXI_RREADY),
.M01_AXI_rresp(axi_mem_intercon_M01_AXI_RRESP),
.M01_AXI_rvalid(axi_mem_intercon_M01_AXI_RVALID),
.M01_AXI_wdata(axi_mem_intercon_M01_AXI_WDATA),
.M01_AXI_wlast(axi_mem_intercon_M01_AXI_WLAST),
.M01_AXI_wready(axi_mem_intercon_M01_AXI_WREADY),
.M01_AXI_wstrb(axi_mem_intercon_M01_AXI_WSTRB),
.M01_AXI_wvalid(axi_mem_intercon_M01_AXI_WVALID),
.S00_ACLK(processing_system7_0_FCLK_CLK0),
.S00_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.S00_AXI_araddr(axi_cdma_0_M_AXI_ARADDR),
.S00_AXI_arburst(axi_cdma_0_M_AXI_ARBURST),
.S00_AXI_arcache(axi_cdma_0_M_AXI_ARCACHE),
.S00_AXI_arlen(axi_cdma_0_M_AXI_ARLEN),
.S00_AXI_arprot(axi_cdma_0_M_AXI_ARPROT),
.S00_AXI_arready(axi_cdma_0_M_AXI_ARREADY),
.S00_AXI_arsize(axi_cdma_0_M_AXI_ARSIZE),
.S00_AXI_arvalid(axi_cdma_0_M_AXI_ARVALID),
.S00_AXI_awaddr(axi_cdma_0_M_AXI_AWADDR),
.S00_AXI_awburst(axi_cdma_0_M_AXI_AWBURST),
.S00_AXI_awcache(axi_cdma_0_M_AXI_AWCACHE),
.S00_AXI_awlen(axi_cdma_0_M_AXI_AWLEN),
.S00_AXI_awprot(axi_cdma_0_M_AXI_AWPROT),
.S00_AXI_awready(axi_cdma_0_M_AXI_AWREADY),
.S00_AXI_awsize(axi_cdma_0_M_AXI_AWSIZE),
.S00_AXI_awvalid(axi_cdma_0_M_AXI_AWVALID),
.S00_AXI_bready(axi_cdma_0_M_AXI_BREADY),
.S00_AXI_bresp(axi_cdma_0_M_AXI_BRESP),
.S00_AXI_bvalid(axi_cdma_0_M_AXI_BVALID),
.S00_AXI_rdata(axi_cdma_0_M_AXI_RDATA),
.S00_AXI_rlast(axi_cdma_0_M_AXI_RLAST),
.S00_AXI_rready(axi_cdma_0_M_AXI_RREADY),
.S00_AXI_rresp(axi_cdma_0_M_AXI_RRESP),
.S00_AXI_rvalid(axi_cdma_0_M_AXI_RVALID),
.S00_AXI_wdata(axi_cdma_0_M_AXI_WDATA),
.S00_AXI_wlast(axi_cdma_0_M_AXI_WLAST),
.S00_AXI_wready(axi_cdma_0_M_AXI_WREADY),
.S00_AXI_wstrb(axi_cdma_0_M_AXI_WSTRB),
.S00_AXI_wvalid(axi_cdma_0_M_AXI_WVALID));
design_1_blk_mem_gen_0_0 blk_mem_gen_0
(.addra({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,axi_bram_ctrl_0_BRAM_PORTA_ADDR}),
.addrb(matrix_mult_0_a_PORTA_ADDR),
.clka(axi_bram_ctrl_0_BRAM_PORTA_CLK),
.clkb(matrix_mult_0_a_PORTA_CLK),
.dina(axi_bram_ctrl_0_BRAM_PORTA_DIN),
.dinb(matrix_mult_0_a_PORTA_DIN),
.douta(axi_bram_ctrl_0_BRAM_PORTA_DOUT),
.doutb(matrix_mult_0_a_PORTA_DOUT),
.ena(axi_bram_ctrl_0_BRAM_PORTA_EN),
.enb(matrix_mult_0_a_PORTA_EN),
.rsta(axi_bram_ctrl_0_BRAM_PORTA_RST),
.rstb(matrix_mult_0_a_PORTA_RST),
.wea(axi_bram_ctrl_0_BRAM_PORTA_WE),
.web(matrix_mult_0_a_PORTA_WE));
endmodule
module hier_bram_1_imp_1R79976
(ARESETN,
BRAM_PORTB_addr,
BRAM_PORTB_clk,
BRAM_PORTB_din,
BRAM_PORTB_dout,
BRAM_PORTB_en,
BRAM_PORTB_rst,
BRAM_PORTB_we,
M00_AXI_araddr,
M00_AXI_arburst,
M00_AXI_arcache,
M00_AXI_arlen,
M00_AXI_arlock,
M00_AXI_arprot,
M00_AXI_arqos,
M00_AXI_arready,
M00_AXI_arsize,
M00_AXI_arvalid,
M00_AXI_awaddr,
M00_AXI_awburst,
M00_AXI_awcache,
M00_AXI_awlen,
M00_AXI_awlock,
M00_AXI_awprot,
M00_AXI_awqos,
M00_AXI_awready,
M00_AXI_awsize,
M00_AXI_awvalid,
M00_AXI_bready,
M00_AXI_bresp,
M00_AXI_bvalid,
M00_AXI_rdata,
M00_AXI_rlast,
M00_AXI_rready,
M00_AXI_rresp,
M00_AXI_rvalid,
M00_AXI_wdata,
M00_AXI_wlast,
M00_AXI_wready,
M00_AXI_wstrb,
M00_AXI_wvalid,
S_AXI_LITE_araddr,
S_AXI_LITE_arready,
S_AXI_LITE_arvalid,
S_AXI_LITE_awaddr,
S_AXI_LITE_awready,
S_AXI_LITE_awvalid,
S_AXI_LITE_bready,
S_AXI_LITE_bresp,
S_AXI_LITE_bvalid,
S_AXI_LITE_rdata,
S_AXI_LITE_rready,
S_AXI_LITE_rresp,
S_AXI_LITE_rvalid,
S_AXI_LITE_wdata,
S_AXI_LITE_wready,
S_AXI_LITE_wvalid,
s_axi_lite_aclk,
s_axi_lite_aresetn);
input [0:0]ARESETN;
input [31:0]BRAM_PORTB_addr;
input BRAM_PORTB_clk;
input [31:0]BRAM_PORTB_din;
output [31:0]BRAM_PORTB_dout;
input BRAM_PORTB_en;
input BRAM_PORTB_rst;
input [3:0]BRAM_PORTB_we;
output [31:0]M00_AXI_araddr;
output [1:0]M00_AXI_arburst;
output [3:0]M00_AXI_arcache;
output [3:0]M00_AXI_arlen;
output [1:0]M00_AXI_arlock;
output [2:0]M00_AXI_arprot;
output [3:0]M00_AXI_arqos;
input M00_AXI_arready;
output [2:0]M00_AXI_arsize;
output M00_AXI_arvalid;
output [31:0]M00_AXI_awaddr;
output [1:0]M00_AXI_awburst;
output [3:0]M00_AXI_awcache;
output [3:0]M00_AXI_awlen;
output [1:0]M00_AXI_awlock;
output [2:0]M00_AXI_awprot;
output [3:0]M00_AXI_awqos;
input M00_AXI_awready;
output [2:0]M00_AXI_awsize;
output M00_AXI_awvalid;
output M00_AXI_bready;
input [1:0]M00_AXI_bresp;
input M00_AXI_bvalid;
input [63:0]M00_AXI_rdata;
input M00_AXI_rlast;
output M00_AXI_rready;
input [1:0]M00_AXI_rresp;
input M00_AXI_rvalid;
output [63:0]M00_AXI_wdata;
output M00_AXI_wlast;
input M00_AXI_wready;
output [7:0]M00_AXI_wstrb;
output M00_AXI_wvalid;
input [31:0]S_AXI_LITE_araddr;
output [0:0]S_AXI_LITE_arready;
input [0:0]S_AXI_LITE_arvalid;
input [31:0]S_AXI_LITE_awaddr;
output [0:0]S_AXI_LITE_awready;
input [0:0]S_AXI_LITE_awvalid;
input [0:0]S_AXI_LITE_bready;
output [1:0]S_AXI_LITE_bresp;
output [0:0]S_AXI_LITE_bvalid;
output [31:0]S_AXI_LITE_rdata;
input [0:0]S_AXI_LITE_rready;
output [1:0]S_AXI_LITE_rresp;
output [0:0]S_AXI_LITE_rvalid;
input [31:0]S_AXI_LITE_wdata;
output [0:0]S_AXI_LITE_wready;
input [0:0]S_AXI_LITE_wvalid;
input s_axi_lite_aclk;
input [0:0]s_axi_lite_aresetn;
wire [12:0]axi_bram_ctrl_0_BRAM_PORTA_ADDR;
wire axi_bram_ctrl_0_BRAM_PORTA_CLK;
wire [31:0]axi_bram_ctrl_0_BRAM_PORTA_DIN;
wire [31:0]axi_bram_ctrl_0_BRAM_PORTA_DOUT;
wire axi_bram_ctrl_0_BRAM_PORTA_EN;
wire axi_bram_ctrl_0_BRAM_PORTA_RST;
wire [3:0]axi_bram_ctrl_0_BRAM_PORTA_WE;
wire [31:0]axi_cdma_0_M_AXI_ARADDR;
wire [1:0]axi_cdma_0_M_AXI_ARBURST;
wire [3:0]axi_cdma_0_M_AXI_ARCACHE;
wire [7:0]axi_cdma_0_M_AXI_ARLEN;
wire [2:0]axi_cdma_0_M_AXI_ARPROT;
wire axi_cdma_0_M_AXI_ARREADY;
wire [2:0]axi_cdma_0_M_AXI_ARSIZE;
wire axi_cdma_0_M_AXI_ARVALID;
wire [31:0]axi_cdma_0_M_AXI_AWADDR;
wire [1:0]axi_cdma_0_M_AXI_AWBURST;
wire [3:0]axi_cdma_0_M_AXI_AWCACHE;
wire [7:0]axi_cdma_0_M_AXI_AWLEN;
wire [2:0]axi_cdma_0_M_AXI_AWPROT;
wire axi_cdma_0_M_AXI_AWREADY;
wire [2:0]axi_cdma_0_M_AXI_AWSIZE;
wire axi_cdma_0_M_AXI_AWVALID;
wire axi_cdma_0_M_AXI_BREADY;
wire [1:0]axi_cdma_0_M_AXI_BRESP;
wire axi_cdma_0_M_AXI_BVALID;
wire [31:0]axi_cdma_0_M_AXI_RDATA;
wire axi_cdma_0_M_AXI_RLAST;
wire axi_cdma_0_M_AXI_RREADY;
wire [1:0]axi_cdma_0_M_AXI_RRESP;
wire axi_cdma_0_M_AXI_RVALID;
wire [31:0]axi_cdma_0_M_AXI_WDATA;
wire axi_cdma_0_M_AXI_WLAST;
wire axi_cdma_0_M_AXI_WREADY;
wire [3:0]axi_cdma_0_M_AXI_WSTRB;
wire axi_cdma_0_M_AXI_WVALID;
wire [31:0]axi_mem_intercon_M00_AXI_ARADDR;
wire [1:0]axi_mem_intercon_M00_AXI_ARBURST;
wire [3:0]axi_mem_intercon_M00_AXI_ARCACHE;
wire [3:0]axi_mem_intercon_M00_AXI_ARLEN;
wire [1:0]axi_mem_intercon_M00_AXI_ARLOCK;
wire [2:0]axi_mem_intercon_M00_AXI_ARPROT;
wire [3:0]axi_mem_intercon_M00_AXI_ARQOS;
wire axi_mem_intercon_M00_AXI_ARREADY;
wire [2:0]axi_mem_intercon_M00_AXI_ARSIZE;
wire axi_mem_intercon_M00_AXI_ARVALID;
wire [31:0]axi_mem_intercon_M00_AXI_AWADDR;
wire [1:0]axi_mem_intercon_M00_AXI_AWBURST;
wire [3:0]axi_mem_intercon_M00_AXI_AWCACHE;
wire [3:0]axi_mem_intercon_M00_AXI_AWLEN;
wire [1:0]axi_mem_intercon_M00_AXI_AWLOCK;
wire [2:0]axi_mem_intercon_M00_AXI_AWPROT;
wire [3:0]axi_mem_intercon_M00_AXI_AWQOS;
wire axi_mem_intercon_M00_AXI_AWREADY;
wire [2:0]axi_mem_intercon_M00_AXI_AWSIZE;
wire axi_mem_intercon_M00_AXI_AWVALID;
wire axi_mem_intercon_M00_AXI_BREADY;
wire [1:0]axi_mem_intercon_M00_AXI_BRESP;
wire axi_mem_intercon_M00_AXI_BVALID;
wire [63:0]axi_mem_intercon_M00_AXI_RDATA;
wire axi_mem_intercon_M00_AXI_RLAST;
wire axi_mem_intercon_M00_AXI_RREADY;
wire [1:0]axi_mem_intercon_M00_AXI_RRESP;
wire axi_mem_intercon_M00_AXI_RVALID;
wire [63:0]axi_mem_intercon_M00_AXI_WDATA;
wire axi_mem_intercon_M00_AXI_WLAST;
wire axi_mem_intercon_M00_AXI_WREADY;
wire [7:0]axi_mem_intercon_M00_AXI_WSTRB;
wire axi_mem_intercon_M00_AXI_WVALID;
wire [12:0]axi_mem_intercon_M01_AXI_ARADDR;
wire [1:0]axi_mem_intercon_M01_AXI_ARBURST;
wire [3:0]axi_mem_intercon_M01_AXI_ARCACHE;
wire [7:0]axi_mem_intercon_M01_AXI_ARLEN;
wire [0:0]axi_mem_intercon_M01_AXI_ARLOCK;
wire [2:0]axi_mem_intercon_M01_AXI_ARPROT;
wire axi_mem_intercon_M01_AXI_ARREADY;
wire [2:0]axi_mem_intercon_M01_AXI_ARSIZE;
wire axi_mem_intercon_M01_AXI_ARVALID;
wire [12:0]axi_mem_intercon_M01_AXI_AWADDR;
wire [1:0]axi_mem_intercon_M01_AXI_AWBURST;
wire [3:0]axi_mem_intercon_M01_AXI_AWCACHE;
wire [7:0]axi_mem_intercon_M01_AXI_AWLEN;
wire [0:0]axi_mem_intercon_M01_AXI_AWLOCK;
wire [2:0]axi_mem_intercon_M01_AXI_AWPROT;
wire axi_mem_intercon_M01_AXI_AWREADY;
wire [2:0]axi_mem_intercon_M01_AXI_AWSIZE;
wire axi_mem_intercon_M01_AXI_AWVALID;
wire axi_mem_intercon_M01_AXI_BREADY;
wire [1:0]axi_mem_intercon_M01_AXI_BRESP;
wire axi_mem_intercon_M01_AXI_BVALID;
wire [31:0]axi_mem_intercon_M01_AXI_RDATA;
wire axi_mem_intercon_M01_AXI_RLAST;
wire axi_mem_intercon_M01_AXI_RREADY;
wire [1:0]axi_mem_intercon_M01_AXI_RRESP;
wire axi_mem_intercon_M01_AXI_RVALID;
wire [31:0]axi_mem_intercon_M01_AXI_WDATA;
wire axi_mem_intercon_M01_AXI_WLAST;
wire axi_mem_intercon_M01_AXI_WREADY;
wire [3:0]axi_mem_intercon_M01_AXI_WSTRB;
wire axi_mem_intercon_M01_AXI_WVALID;
wire [31:0]matrix_mult_0_a_PORTA_ADDR;
wire matrix_mult_0_a_PORTA_CLK;
wire [31:0]matrix_mult_0_a_PORTA_DIN;
wire [31:0]matrix_mult_0_a_PORTA_DOUT;
wire matrix_mult_0_a_PORTA_EN;
wire matrix_mult_0_a_PORTA_RST;
wire [3:0]matrix_mult_0_a_PORTA_WE;
wire processing_system7_0_FCLK_CLK0;
wire [31:0]processing_system7_0_axi_periph_M00_AXI_ARADDR;
wire processing_system7_0_axi_periph_M00_AXI_ARREADY;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_ARVALID;
wire [31:0]processing_system7_0_axi_periph_M00_AXI_AWADDR;
wire processing_system7_0_axi_periph_M00_AXI_AWREADY;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_AWVALID;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_BREADY;
wire [1:0]processing_system7_0_axi_periph_M00_AXI_BRESP;
wire processing_system7_0_axi_periph_M00_AXI_BVALID;
wire [31:0]processing_system7_0_axi_periph_M00_AXI_RDATA;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_RREADY;
wire [1:0]processing_system7_0_axi_periph_M00_AXI_RRESP;
wire processing_system7_0_axi_periph_M00_AXI_RVALID;
wire [31:0]processing_system7_0_axi_periph_M00_AXI_WDATA;
wire processing_system7_0_axi_periph_M00_AXI_WREADY;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_WVALID;
wire [0:0]rst_processing_system7_0_100M_interconnect_aresetn;
wire [0:0]rst_processing_system7_0_100M_peripheral_aresetn;
assign BRAM_PORTB_dout[31:0] = matrix_mult_0_a_PORTA_DOUT;
assign M00_AXI_araddr[31:0] = axi_mem_intercon_M00_AXI_ARADDR;
assign M00_AXI_arburst[1:0] = axi_mem_intercon_M00_AXI_ARBURST;
assign M00_AXI_arcache[3:0] = axi_mem_intercon_M00_AXI_ARCACHE;
assign M00_AXI_arlen[3:0] = axi_mem_intercon_M00_AXI_ARLEN;
assign M00_AXI_arlock[1:0] = axi_mem_intercon_M00_AXI_ARLOCK;
assign M00_AXI_arprot[2:0] = axi_mem_intercon_M00_AXI_ARPROT;
assign M00_AXI_arqos[3:0] = axi_mem_intercon_M00_AXI_ARQOS;
assign M00_AXI_arsize[2:0] = axi_mem_intercon_M00_AXI_ARSIZE;
assign M00_AXI_arvalid = axi_mem_intercon_M00_AXI_ARVALID;
assign M00_AXI_awaddr[31:0] = axi_mem_intercon_M00_AXI_AWADDR;
assign M00_AXI_awburst[1:0] = axi_mem_intercon_M00_AXI_AWBURST;
assign M00_AXI_awcache[3:0] = axi_mem_intercon_M00_AXI_AWCACHE;
assign M00_AXI_awlen[3:0] = axi_mem_intercon_M00_AXI_AWLEN;
assign M00_AXI_awlock[1:0] = axi_mem_intercon_M00_AXI_AWLOCK;
assign M00_AXI_awprot[2:0] = axi_mem_intercon_M00_AXI_AWPROT;
assign M00_AXI_awqos[3:0] = axi_mem_intercon_M00_AXI_AWQOS;
assign M00_AXI_awsize[2:0] = axi_mem_intercon_M00_AXI_AWSIZE;
assign M00_AXI_awvalid = axi_mem_intercon_M00_AXI_AWVALID;
assign M00_AXI_bready = axi_mem_intercon_M00_AXI_BREADY;
assign M00_AXI_rready = axi_mem_intercon_M00_AXI_RREADY;
assign M00_AXI_wdata[63:0] = axi_mem_intercon_M00_AXI_WDATA;
assign M00_AXI_wlast = axi_mem_intercon_M00_AXI_WLAST;
assign M00_AXI_wstrb[7:0] = axi_mem_intercon_M00_AXI_WSTRB;
assign M00_AXI_wvalid = axi_mem_intercon_M00_AXI_WVALID;
assign S_AXI_LITE_arready[0] = processing_system7_0_axi_periph_M00_AXI_ARREADY;
assign S_AXI_LITE_awready[0] = processing_system7_0_axi_periph_M00_AXI_AWREADY;
assign S_AXI_LITE_bresp[1:0] = processing_system7_0_axi_periph_M00_AXI_BRESP;
assign S_AXI_LITE_bvalid[0] = processing_system7_0_axi_periph_M00_AXI_BVALID;
assign S_AXI_LITE_rdata[31:0] = processing_system7_0_axi_periph_M00_AXI_RDATA;
assign S_AXI_LITE_rresp[1:0] = processing_system7_0_axi_periph_M00_AXI_RRESP;
assign S_AXI_LITE_rvalid[0] = processing_system7_0_axi_periph_M00_AXI_RVALID;
assign S_AXI_LITE_wready[0] = processing_system7_0_axi_periph_M00_AXI_WREADY;
assign axi_mem_intercon_M00_AXI_ARREADY = M00_AXI_arready;
assign axi_mem_intercon_M00_AXI_AWREADY = M00_AXI_awready;
assign axi_mem_intercon_M00_AXI_BRESP = M00_AXI_bresp[1:0];
assign axi_mem_intercon_M00_AXI_BVALID = M00_AXI_bvalid;
assign axi_mem_intercon_M00_AXI_RDATA = M00_AXI_rdata[63:0];
assign axi_mem_intercon_M00_AXI_RLAST = M00_AXI_rlast;
assign axi_mem_intercon_M00_AXI_RRESP = M00_AXI_rresp[1:0];
assign axi_mem_intercon_M00_AXI_RVALID = M00_AXI_rvalid;
assign axi_mem_intercon_M00_AXI_WREADY = M00_AXI_wready;
assign matrix_mult_0_a_PORTA_ADDR = BRAM_PORTB_addr[31:0];
assign matrix_mult_0_a_PORTA_CLK = BRAM_PORTB_clk;
assign matrix_mult_0_a_PORTA_DIN = BRAM_PORTB_din[31:0];
assign matrix_mult_0_a_PORTA_EN = BRAM_PORTB_en;
assign matrix_mult_0_a_PORTA_RST = BRAM_PORTB_rst;
assign matrix_mult_0_a_PORTA_WE = BRAM_PORTB_we[3:0];
assign processing_system7_0_FCLK_CLK0 = s_axi_lite_aclk;
assign processing_system7_0_axi_periph_M00_AXI_ARADDR = S_AXI_LITE_araddr[31:0];
assign processing_system7_0_axi_periph_M00_AXI_ARVALID = S_AXI_LITE_arvalid[0];
assign processing_system7_0_axi_periph_M00_AXI_AWADDR = S_AXI_LITE_awaddr[31:0];
assign processing_system7_0_axi_periph_M00_AXI_AWVALID = S_AXI_LITE_awvalid[0];
assign processing_system7_0_axi_periph_M00_AXI_BREADY = S_AXI_LITE_bready[0];
assign processing_system7_0_axi_periph_M00_AXI_RREADY = S_AXI_LITE_rready[0];
assign processing_system7_0_axi_periph_M00_AXI_WDATA = S_AXI_LITE_wdata[31:0];
assign processing_system7_0_axi_periph_M00_AXI_WVALID = S_AXI_LITE_wvalid[0];
assign rst_processing_system7_0_100M_interconnect_aresetn = ARESETN[0];
assign rst_processing_system7_0_100M_peripheral_aresetn = s_axi_lite_aresetn[0];
design_1_axi_bram_ctrl_0_1 axi_bram_ctrl_0
(.bram_addr_a(axi_bram_ctrl_0_BRAM_PORTA_ADDR),
.bram_clk_a(axi_bram_ctrl_0_BRAM_PORTA_CLK),
.bram_en_a(axi_bram_ctrl_0_BRAM_PORTA_EN),
.bram_rddata_a(axi_bram_ctrl_0_BRAM_PORTA_DOUT),
.bram_rst_a(axi_bram_ctrl_0_BRAM_PORTA_RST),
.bram_we_a(axi_bram_ctrl_0_BRAM_PORTA_WE),
.bram_wrdata_a(axi_bram_ctrl_0_BRAM_PORTA_DIN),
.s_axi_aclk(processing_system7_0_FCLK_CLK0),
.s_axi_araddr(axi_mem_intercon_M01_AXI_ARADDR),
.s_axi_arburst(axi_mem_intercon_M01_AXI_ARBURST),
.s_axi_arcache(axi_mem_intercon_M01_AXI_ARCACHE),
.s_axi_aresetn(rst_processing_system7_0_100M_peripheral_aresetn),
.s_axi_arlen(axi_mem_intercon_M01_AXI_ARLEN),
.s_axi_arlock(axi_mem_intercon_M01_AXI_ARLOCK),
.s_axi_arprot(axi_mem_intercon_M01_AXI_ARPROT),
.s_axi_arready(axi_mem_intercon_M01_AXI_ARREADY),
.s_axi_arsize(axi_mem_intercon_M01_AXI_ARSIZE),
.s_axi_arvalid(axi_mem_intercon_M01_AXI_ARVALID),
.s_axi_awaddr(axi_mem_intercon_M01_AXI_AWADDR),
.s_axi_awburst(axi_mem_intercon_M01_AXI_AWBURST),
.s_axi_awcache(axi_mem_intercon_M01_AXI_AWCACHE),
.s_axi_awlen(axi_mem_intercon_M01_AXI_AWLEN),
.s_axi_awlock(axi_mem_intercon_M01_AXI_AWLOCK),
.s_axi_awprot(axi_mem_intercon_M01_AXI_AWPROT),
.s_axi_awready(axi_mem_intercon_M01_AXI_AWREADY),
.s_axi_awsize(axi_mem_intercon_M01_AXI_AWSIZE),
.s_axi_awvalid(axi_mem_intercon_M01_AXI_AWVALID),
.s_axi_bready(axi_mem_intercon_M01_AXI_BREADY),
.s_axi_bresp(axi_mem_intercon_M01_AXI_BRESP),
.s_axi_bvalid(axi_mem_intercon_M01_AXI_BVALID),
.s_axi_rdata(axi_mem_intercon_M01_AXI_RDATA),
.s_axi_rlast(axi_mem_intercon_M01_AXI_RLAST),
.s_axi_rready(axi_mem_intercon_M01_AXI_RREADY),
.s_axi_rresp(axi_mem_intercon_M01_AXI_RRESP),
.s_axi_rvalid(axi_mem_intercon_M01_AXI_RVALID),
.s_axi_wdata(axi_mem_intercon_M01_AXI_WDATA),
.s_axi_wlast(axi_mem_intercon_M01_AXI_WLAST),
.s_axi_wready(axi_mem_intercon_M01_AXI_WREADY),
.s_axi_wstrb(axi_mem_intercon_M01_AXI_WSTRB),
.s_axi_wvalid(axi_mem_intercon_M01_AXI_WVALID));
design_1_axi_cdma_0_2 axi_cdma_0
(.m_axi_aclk(processing_system7_0_FCLK_CLK0),
.m_axi_araddr(axi_cdma_0_M_AXI_ARADDR),
.m_axi_arburst(axi_cdma_0_M_AXI_ARBURST),
.m_axi_arcache(axi_cdma_0_M_AXI_ARCACHE),
.m_axi_arlen(axi_cdma_0_M_AXI_ARLEN),
.m_axi_arprot(axi_cdma_0_M_AXI_ARPROT),
.m_axi_arready(axi_cdma_0_M_AXI_ARREADY),
.m_axi_arsize(axi_cdma_0_M_AXI_ARSIZE),
.m_axi_arvalid(axi_cdma_0_M_AXI_ARVALID),
.m_axi_awaddr(axi_cdma_0_M_AXI_AWADDR),
.m_axi_awburst(axi_cdma_0_M_AXI_AWBURST),
.m_axi_awcache(axi_cdma_0_M_AXI_AWCACHE),
.m_axi_awlen(axi_cdma_0_M_AXI_AWLEN),
.m_axi_awprot(axi_cdma_0_M_AXI_AWPROT),
.m_axi_awready(axi_cdma_0_M_AXI_AWREADY),
.m_axi_awsize(axi_cdma_0_M_AXI_AWSIZE),
.m_axi_awvalid(axi_cdma_0_M_AXI_AWVALID),
.m_axi_bready(axi_cdma_0_M_AXI_BREADY),
.m_axi_bresp(axi_cdma_0_M_AXI_BRESP),
.m_axi_bvalid(axi_cdma_0_M_AXI_BVALID),
.m_axi_rdata(axi_cdma_0_M_AXI_RDATA),
.m_axi_rlast(axi_cdma_0_M_AXI_RLAST),
.m_axi_rready(axi_cdma_0_M_AXI_RREADY),
.m_axi_rresp(axi_cdma_0_M_AXI_RRESP),
.m_axi_rvalid(axi_cdma_0_M_AXI_RVALID),
.m_axi_wdata(axi_cdma_0_M_AXI_WDATA),
.m_axi_wlast(axi_cdma_0_M_AXI_WLAST),
.m_axi_wready(axi_cdma_0_M_AXI_WREADY),
.m_axi_wstrb(axi_cdma_0_M_AXI_WSTRB),
.m_axi_wvalid(axi_cdma_0_M_AXI_WVALID),
.s_axi_lite_aclk(processing_system7_0_FCLK_CLK0),
.s_axi_lite_araddr(processing_system7_0_axi_periph_M00_AXI_ARADDR[5:0]),
.s_axi_lite_aresetn(rst_processing_system7_0_100M_peripheral_aresetn),
.s_axi_lite_arready(processing_system7_0_axi_periph_M00_AXI_ARREADY),
.s_axi_lite_arvalid(processing_system7_0_axi_periph_M00_AXI_ARVALID),
.s_axi_lite_awaddr(processing_system7_0_axi_periph_M00_AXI_AWADDR[5:0]),
.s_axi_lite_awready(processing_system7_0_axi_periph_M00_AXI_AWREADY),
.s_axi_lite_awvalid(processing_system7_0_axi_periph_M00_AXI_AWVALID),
.s_axi_lite_bready(processing_system7_0_axi_periph_M00_AXI_BREADY),
.s_axi_lite_bresp(processing_system7_0_axi_periph_M00_AXI_BRESP),
.s_axi_lite_bvalid(processing_system7_0_axi_periph_M00_AXI_BVALID),
.s_axi_lite_rdata(processing_system7_0_axi_periph_M00_AXI_RDATA),
.s_axi_lite_rready(processing_system7_0_axi_periph_M00_AXI_RREADY),
.s_axi_lite_rresp(processing_system7_0_axi_periph_M00_AXI_RRESP),
.s_axi_lite_rvalid(processing_system7_0_axi_periph_M00_AXI_RVALID),
.s_axi_lite_wdata(processing_system7_0_axi_periph_M00_AXI_WDATA),
.s_axi_lite_wready(processing_system7_0_axi_periph_M00_AXI_WREADY),
.s_axi_lite_wvalid(processing_system7_0_axi_periph_M00_AXI_WVALID));
design_1_axi_mem_intercon_2 axi_mem_intercon
(.ACLK(processing_system7_0_FCLK_CLK0),
.ARESETN(rst_processing_system7_0_100M_interconnect_aresetn),
.M00_ACLK(processing_system7_0_FCLK_CLK0),
.M00_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.M00_AXI_araddr(axi_mem_intercon_M00_AXI_ARADDR),
.M00_AXI_arburst(axi_mem_intercon_M00_AXI_ARBURST),
.M00_AXI_arcache(axi_mem_intercon_M00_AXI_ARCACHE),
.M00_AXI_arlen(axi_mem_intercon_M00_AXI_ARLEN),
.M00_AXI_arlock(axi_mem_intercon_M00_AXI_ARLOCK),
.M00_AXI_arprot(axi_mem_intercon_M00_AXI_ARPROT),
.M00_AXI_arqos(axi_mem_intercon_M00_AXI_ARQOS),
.M00_AXI_arready(axi_mem_intercon_M00_AXI_ARREADY),
.M00_AXI_arsize(axi_mem_intercon_M00_AXI_ARSIZE),
.M00_AXI_arvalid(axi_mem_intercon_M00_AXI_ARVALID),
.M00_AXI_awaddr(axi_mem_intercon_M00_AXI_AWADDR),
.M00_AXI_awburst(axi_mem_intercon_M00_AXI_AWBURST),
.M00_AXI_awcache(axi_mem_intercon_M00_AXI_AWCACHE),
.M00_AXI_awlen(axi_mem_intercon_M00_AXI_AWLEN),
.M00_AXI_awlock(axi_mem_intercon_M00_AXI_AWLOCK),
.M00_AXI_awprot(axi_mem_intercon_M00_AXI_AWPROT),
.M00_AXI_awqos(axi_mem_intercon_M00_AXI_AWQOS),
.M00_AXI_awready(axi_mem_intercon_M00_AXI_AWREADY),
.M00_AXI_awsize(axi_mem_intercon_M00_AXI_AWSIZE),
.M00_AXI_awvalid(axi_mem_intercon_M00_AXI_AWVALID),
.M00_AXI_bready(axi_mem_intercon_M00_AXI_BREADY),
.M00_AXI_bresp(axi_mem_intercon_M00_AXI_BRESP),
.M00_AXI_bvalid(axi_mem_intercon_M00_AXI_BVALID),
.M00_AXI_rdata(axi_mem_intercon_M00_AXI_RDATA),
.M00_AXI_rlast(axi_mem_intercon_M00_AXI_RLAST),
.M00_AXI_rready(axi_mem_intercon_M00_AXI_RREADY),
.M00_AXI_rresp(axi_mem_intercon_M00_AXI_RRESP),
.M00_AXI_rvalid(axi_mem_intercon_M00_AXI_RVALID),
.M00_AXI_wdata(axi_mem_intercon_M00_AXI_WDATA),
.M00_AXI_wlast(axi_mem_intercon_M00_AXI_WLAST),
.M00_AXI_wready(axi_mem_intercon_M00_AXI_WREADY),
.M00_AXI_wstrb(axi_mem_intercon_M00_AXI_WSTRB),
.M00_AXI_wvalid(axi_mem_intercon_M00_AXI_WVALID),
.M01_ACLK(processing_system7_0_FCLK_CLK0),
.M01_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.M01_AXI_araddr(axi_mem_intercon_M01_AXI_ARADDR),
.M01_AXI_arburst(axi_mem_intercon_M01_AXI_ARBURST),
.M01_AXI_arcache(axi_mem_intercon_M01_AXI_ARCACHE),
.M01_AXI_arlen(axi_mem_intercon_M01_AXI_ARLEN),
.M01_AXI_arlock(axi_mem_intercon_M01_AXI_ARLOCK),
.M01_AXI_arprot(axi_mem_intercon_M01_AXI_ARPROT),
.M01_AXI_arready(axi_mem_intercon_M01_AXI_ARREADY),
.M01_AXI_arsize(axi_mem_intercon_M01_AXI_ARSIZE),
.M01_AXI_arvalid(axi_mem_intercon_M01_AXI_ARVALID),
.M01_AXI_awaddr(axi_mem_intercon_M01_AXI_AWADDR),
.M01_AXI_awburst(axi_mem_intercon_M01_AXI_AWBURST),
.M01_AXI_awcache(axi_mem_intercon_M01_AXI_AWCACHE),
.M01_AXI_awlen(axi_mem_intercon_M01_AXI_AWLEN),
.M01_AXI_awlock(axi_mem_intercon_M01_AXI_AWLOCK),
.M01_AXI_awprot(axi_mem_intercon_M01_AXI_AWPROT),
.M01_AXI_awready(axi_mem_intercon_M01_AXI_AWREADY),
.M01_AXI_awsize(axi_mem_intercon_M01_AXI_AWSIZE),
.M01_AXI_awvalid(axi_mem_intercon_M01_AXI_AWVALID),
.M01_AXI_bready(axi_mem_intercon_M01_AXI_BREADY),
.M01_AXI_bresp(axi_mem_intercon_M01_AXI_BRESP),
.M01_AXI_bvalid(axi_mem_intercon_M01_AXI_BVALID),
.M01_AXI_rdata(axi_mem_intercon_M01_AXI_RDATA),
.M01_AXI_rlast(axi_mem_intercon_M01_AXI_RLAST),
.M01_AXI_rready(axi_mem_intercon_M01_AXI_RREADY),
.M01_AXI_rresp(axi_mem_intercon_M01_AXI_RRESP),
.M01_AXI_rvalid(axi_mem_intercon_M01_AXI_RVALID),
.M01_AXI_wdata(axi_mem_intercon_M01_AXI_WDATA),
.M01_AXI_wlast(axi_mem_intercon_M01_AXI_WLAST),
.M01_AXI_wready(axi_mem_intercon_M01_AXI_WREADY),
.M01_AXI_wstrb(axi_mem_intercon_M01_AXI_WSTRB),
.M01_AXI_wvalid(axi_mem_intercon_M01_AXI_WVALID),
.S00_ACLK(processing_system7_0_FCLK_CLK0),
.S00_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.S00_AXI_araddr(axi_cdma_0_M_AXI_ARADDR),
.S00_AXI_arburst(axi_cdma_0_M_AXI_ARBURST),
.S00_AXI_arcache(axi_cdma_0_M_AXI_ARCACHE),
.S00_AXI_arlen(axi_cdma_0_M_AXI_ARLEN),
.S00_AXI_arprot(axi_cdma_0_M_AXI_ARPROT),
.S00_AXI_arready(axi_cdma_0_M_AXI_ARREADY),
.S00_AXI_arsize(axi_cdma_0_M_AXI_ARSIZE),
.S00_AXI_arvalid(axi_cdma_0_M_AXI_ARVALID),
.S00_AXI_awaddr(axi_cdma_0_M_AXI_AWADDR),
.S00_AXI_awburst(axi_cdma_0_M_AXI_AWBURST),
.S00_AXI_awcache(axi_cdma_0_M_AXI_AWCACHE),
.S00_AXI_awlen(axi_cdma_0_M_AXI_AWLEN),
.S00_AXI_awprot(axi_cdma_0_M_AXI_AWPROT),
.S00_AXI_awready(axi_cdma_0_M_AXI_AWREADY),
.S00_AXI_awsize(axi_cdma_0_M_AXI_AWSIZE),
.S00_AXI_awvalid(axi_cdma_0_M_AXI_AWVALID),
.S00_AXI_bready(axi_cdma_0_M_AXI_BREADY),
.S00_AXI_bresp(axi_cdma_0_M_AXI_BRESP),
.S00_AXI_bvalid(axi_cdma_0_M_AXI_BVALID),
.S00_AXI_rdata(axi_cdma_0_M_AXI_RDATA),
.S00_AXI_rlast(axi_cdma_0_M_AXI_RLAST),
.S00_AXI_rready(axi_cdma_0_M_AXI_RREADY),
.S00_AXI_rresp(axi_cdma_0_M_AXI_RRESP),
.S00_AXI_rvalid(axi_cdma_0_M_AXI_RVALID),
.S00_AXI_wdata(axi_cdma_0_M_AXI_WDATA),
.S00_AXI_wlast(axi_cdma_0_M_AXI_WLAST),
.S00_AXI_wready(axi_cdma_0_M_AXI_WREADY),
.S00_AXI_wstrb(axi_cdma_0_M_AXI_WSTRB),
.S00_AXI_wvalid(axi_cdma_0_M_AXI_WVALID));
design_1_blk_mem_gen_0_2 blk_mem_gen_0
(.addra({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,axi_bram_ctrl_0_BRAM_PORTA_ADDR}),
.addrb(matrix_mult_0_a_PORTA_ADDR),
.clka(axi_bram_ctrl_0_BRAM_PORTA_CLK),
.clkb(matrix_mult_0_a_PORTA_CLK),
.dina(axi_bram_ctrl_0_BRAM_PORTA_DIN),
.dinb(matrix_mult_0_a_PORTA_DIN),
.douta(axi_bram_ctrl_0_BRAM_PORTA_DOUT),
.doutb(matrix_mult_0_a_PORTA_DOUT),
.ena(axi_bram_ctrl_0_BRAM_PORTA_EN),
.enb(matrix_mult_0_a_PORTA_EN),
.rsta(axi_bram_ctrl_0_BRAM_PORTA_RST),
.rstb(matrix_mult_0_a_PORTA_RST),
.wea(axi_bram_ctrl_0_BRAM_PORTA_WE),
.web(matrix_mult_0_a_PORTA_WE));
endmodule
module hier_bram_2_imp_1OK8YL3
(ARESETN,
BRAM_PORTB_addr,
BRAM_PORTB_clk,
BRAM_PORTB_din,
BRAM_PORTB_dout,
BRAM_PORTB_en,
BRAM_PORTB_rst,
BRAM_PORTB_we,
M00_AXI_araddr,
M00_AXI_arburst,
M00_AXI_arcache,
M00_AXI_arlen,
M00_AXI_arlock,
M00_AXI_arprot,
M00_AXI_arqos,
M00_AXI_arready,
M00_AXI_arsize,
M00_AXI_arvalid,
M00_AXI_awaddr,
M00_AXI_awburst,
M00_AXI_awcache,
M00_AXI_awlen,
M00_AXI_awlock,
M00_AXI_awprot,
M00_AXI_awqos,
M00_AXI_awready,
M00_AXI_awsize,
M00_AXI_awvalid,
M00_AXI_bready,
M00_AXI_bresp,
M00_AXI_bvalid,
M00_AXI_rdata,
M00_AXI_rlast,
M00_AXI_rready,
M00_AXI_rresp,
M00_AXI_rvalid,
M00_AXI_wdata,
M00_AXI_wlast,
M00_AXI_wready,
M00_AXI_wstrb,
M00_AXI_wvalid,
S_AXI_LITE_araddr,
S_AXI_LITE_arready,
S_AXI_LITE_arvalid,
S_AXI_LITE_awaddr,
S_AXI_LITE_awready,
S_AXI_LITE_awvalid,
S_AXI_LITE_bready,
S_AXI_LITE_bresp,
S_AXI_LITE_bvalid,
S_AXI_LITE_rdata,
S_AXI_LITE_rready,
S_AXI_LITE_rresp,
S_AXI_LITE_rvalid,
S_AXI_LITE_wdata,
S_AXI_LITE_wready,
S_AXI_LITE_wvalid,
s_axi_lite_aclk,
s_axi_lite_aresetn);
input [0:0]ARESETN;
input [31:0]BRAM_PORTB_addr;
input BRAM_PORTB_clk;
input [31:0]BRAM_PORTB_din;
output [31:0]BRAM_PORTB_dout;
input BRAM_PORTB_en;
input BRAM_PORTB_rst;
input [3:0]BRAM_PORTB_we;
output [31:0]M00_AXI_araddr;
output [1:0]M00_AXI_arburst;
output [3:0]M00_AXI_arcache;
output [3:0]M00_AXI_arlen;
output [1:0]M00_AXI_arlock;
output [2:0]M00_AXI_arprot;
output [3:0]M00_AXI_arqos;
input M00_AXI_arready;
output [2:0]M00_AXI_arsize;
output M00_AXI_arvalid;
output [31:0]M00_AXI_awaddr;
output [1:0]M00_AXI_awburst;
output [3:0]M00_AXI_awcache;
output [3:0]M00_AXI_awlen;
output [1:0]M00_AXI_awlock;
output [2:0]M00_AXI_awprot;
output [3:0]M00_AXI_awqos;
input M00_AXI_awready;
output [2:0]M00_AXI_awsize;
output M00_AXI_awvalid;
output M00_AXI_bready;
input [1:0]M00_AXI_bresp;
input M00_AXI_bvalid;
input [63:0]M00_AXI_rdata;
input M00_AXI_rlast;
output M00_AXI_rready;
input [1:0]M00_AXI_rresp;
input M00_AXI_rvalid;
output [63:0]M00_AXI_wdata;
output M00_AXI_wlast;
input M00_AXI_wready;
output [7:0]M00_AXI_wstrb;
output M00_AXI_wvalid;
input [31:0]S_AXI_LITE_araddr;
output [0:0]S_AXI_LITE_arready;
input [0:0]S_AXI_LITE_arvalid;
input [31:0]S_AXI_LITE_awaddr;
output [0:0]S_AXI_LITE_awready;
input [0:0]S_AXI_LITE_awvalid;
input [0:0]S_AXI_LITE_bready;
output [1:0]S_AXI_LITE_bresp;
output [0:0]S_AXI_LITE_bvalid;
output [31:0]S_AXI_LITE_rdata;
input [0:0]S_AXI_LITE_rready;
output [1:0]S_AXI_LITE_rresp;
output [0:0]S_AXI_LITE_rvalid;
input [31:0]S_AXI_LITE_wdata;
output [0:0]S_AXI_LITE_wready;
input [0:0]S_AXI_LITE_wvalid;
input s_axi_lite_aclk;
input [0:0]s_axi_lite_aresetn;
wire [12:0]axi_bram_ctrl_0_BRAM_PORTA_ADDR;
wire axi_bram_ctrl_0_BRAM_PORTA_CLK;
wire [31:0]axi_bram_ctrl_0_BRAM_PORTA_DIN;
wire [31:0]axi_bram_ctrl_0_BRAM_PORTA_DOUT;
wire axi_bram_ctrl_0_BRAM_PORTA_EN;
wire axi_bram_ctrl_0_BRAM_PORTA_RST;
wire [3:0]axi_bram_ctrl_0_BRAM_PORTA_WE;
wire [31:0]axi_cdma_0_M_AXI_ARADDR;
wire [1:0]axi_cdma_0_M_AXI_ARBURST;
wire [3:0]axi_cdma_0_M_AXI_ARCACHE;
wire [7:0]axi_cdma_0_M_AXI_ARLEN;
wire [2:0]axi_cdma_0_M_AXI_ARPROT;
wire axi_cdma_0_M_AXI_ARREADY;
wire [2:0]axi_cdma_0_M_AXI_ARSIZE;
wire axi_cdma_0_M_AXI_ARVALID;
wire [31:0]axi_cdma_0_M_AXI_AWADDR;
wire [1:0]axi_cdma_0_M_AXI_AWBURST;
wire [3:0]axi_cdma_0_M_AXI_AWCACHE;
wire [7:0]axi_cdma_0_M_AXI_AWLEN;
wire [2:0]axi_cdma_0_M_AXI_AWPROT;
wire axi_cdma_0_M_AXI_AWREADY;
wire [2:0]axi_cdma_0_M_AXI_AWSIZE;
wire axi_cdma_0_M_AXI_AWVALID;
wire axi_cdma_0_M_AXI_BREADY;
wire [1:0]axi_cdma_0_M_AXI_BRESP;
wire axi_cdma_0_M_AXI_BVALID;
wire [31:0]axi_cdma_0_M_AXI_RDATA;
wire axi_cdma_0_M_AXI_RLAST;
wire axi_cdma_0_M_AXI_RREADY;
wire [1:0]axi_cdma_0_M_AXI_RRESP;
wire axi_cdma_0_M_AXI_RVALID;
wire [31:0]axi_cdma_0_M_AXI_WDATA;
wire axi_cdma_0_M_AXI_WLAST;
wire axi_cdma_0_M_AXI_WREADY;
wire [3:0]axi_cdma_0_M_AXI_WSTRB;
wire axi_cdma_0_M_AXI_WVALID;
wire [31:0]axi_mem_intercon_M00_AXI_ARADDR;
wire [1:0]axi_mem_intercon_M00_AXI_ARBURST;
wire [3:0]axi_mem_intercon_M00_AXI_ARCACHE;
wire [3:0]axi_mem_intercon_M00_AXI_ARLEN;
wire [1:0]axi_mem_intercon_M00_AXI_ARLOCK;
wire [2:0]axi_mem_intercon_M00_AXI_ARPROT;
wire [3:0]axi_mem_intercon_M00_AXI_ARQOS;
wire axi_mem_intercon_M00_AXI_ARREADY;
wire [2:0]axi_mem_intercon_M00_AXI_ARSIZE;
wire axi_mem_intercon_M00_AXI_ARVALID;
wire [31:0]axi_mem_intercon_M00_AXI_AWADDR;
wire [1:0]axi_mem_intercon_M00_AXI_AWBURST;
wire [3:0]axi_mem_intercon_M00_AXI_AWCACHE;
wire [3:0]axi_mem_intercon_M00_AXI_AWLEN;
wire [1:0]axi_mem_intercon_M00_AXI_AWLOCK;
wire [2:0]axi_mem_intercon_M00_AXI_AWPROT;
wire [3:0]axi_mem_intercon_M00_AXI_AWQOS;
wire axi_mem_intercon_M00_AXI_AWREADY;
wire [2:0]axi_mem_intercon_M00_AXI_AWSIZE;
wire axi_mem_intercon_M00_AXI_AWVALID;
wire axi_mem_intercon_M00_AXI_BREADY;
wire [1:0]axi_mem_intercon_M00_AXI_BRESP;
wire axi_mem_intercon_M00_AXI_BVALID;
wire [63:0]axi_mem_intercon_M00_AXI_RDATA;
wire axi_mem_intercon_M00_AXI_RLAST;
wire axi_mem_intercon_M00_AXI_RREADY;
wire [1:0]axi_mem_intercon_M00_AXI_RRESP;
wire axi_mem_intercon_M00_AXI_RVALID;
wire [63:0]axi_mem_intercon_M00_AXI_WDATA;
wire axi_mem_intercon_M00_AXI_WLAST;
wire axi_mem_intercon_M00_AXI_WREADY;
wire [7:0]axi_mem_intercon_M00_AXI_WSTRB;
wire axi_mem_intercon_M00_AXI_WVALID;
wire [12:0]axi_mem_intercon_M01_AXI_ARADDR;
wire [1:0]axi_mem_intercon_M01_AXI_ARBURST;
wire [3:0]axi_mem_intercon_M01_AXI_ARCACHE;
wire [7:0]axi_mem_intercon_M01_AXI_ARLEN;
wire [0:0]axi_mem_intercon_M01_AXI_ARLOCK;
wire [2:0]axi_mem_intercon_M01_AXI_ARPROT;
wire axi_mem_intercon_M01_AXI_ARREADY;
wire [2:0]axi_mem_intercon_M01_AXI_ARSIZE;
wire axi_mem_intercon_M01_AXI_ARVALID;
wire [12:0]axi_mem_intercon_M01_AXI_AWADDR;
wire [1:0]axi_mem_intercon_M01_AXI_AWBURST;
wire [3:0]axi_mem_intercon_M01_AXI_AWCACHE;
wire [7:0]axi_mem_intercon_M01_AXI_AWLEN;
wire [0:0]axi_mem_intercon_M01_AXI_AWLOCK;
wire [2:0]axi_mem_intercon_M01_AXI_AWPROT;
wire axi_mem_intercon_M01_AXI_AWREADY;
wire [2:0]axi_mem_intercon_M01_AXI_AWSIZE;
wire axi_mem_intercon_M01_AXI_AWVALID;
wire axi_mem_intercon_M01_AXI_BREADY;
wire [1:0]axi_mem_intercon_M01_AXI_BRESP;
wire axi_mem_intercon_M01_AXI_BVALID;
wire [31:0]axi_mem_intercon_M01_AXI_RDATA;
wire axi_mem_intercon_M01_AXI_RLAST;
wire axi_mem_intercon_M01_AXI_RREADY;
wire [1:0]axi_mem_intercon_M01_AXI_RRESP;
wire axi_mem_intercon_M01_AXI_RVALID;
wire [31:0]axi_mem_intercon_M01_AXI_WDATA;
wire axi_mem_intercon_M01_AXI_WLAST;
wire axi_mem_intercon_M01_AXI_WREADY;
wire [3:0]axi_mem_intercon_M01_AXI_WSTRB;
wire axi_mem_intercon_M01_AXI_WVALID;
wire [31:0]matrix_mult_0_a_PORTA_ADDR;
wire matrix_mult_0_a_PORTA_CLK;
wire [31:0]matrix_mult_0_a_PORTA_DIN;
wire [31:0]matrix_mult_0_a_PORTA_DOUT;
wire matrix_mult_0_a_PORTA_EN;
wire matrix_mult_0_a_PORTA_RST;
wire [3:0]matrix_mult_0_a_PORTA_WE;
wire processing_system7_0_FCLK_CLK0;
wire [31:0]processing_system7_0_axi_periph_M00_AXI_ARADDR;
wire processing_system7_0_axi_periph_M00_AXI_ARREADY;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_ARVALID;
wire [31:0]processing_system7_0_axi_periph_M00_AXI_AWADDR;
wire processing_system7_0_axi_periph_M00_AXI_AWREADY;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_AWVALID;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_BREADY;
wire [1:0]processing_system7_0_axi_periph_M00_AXI_BRESP;
wire processing_system7_0_axi_periph_M00_AXI_BVALID;
wire [31:0]processing_system7_0_axi_periph_M00_AXI_RDATA;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_RREADY;
wire [1:0]processing_system7_0_axi_periph_M00_AXI_RRESP;
wire processing_system7_0_axi_periph_M00_AXI_RVALID;
wire [31:0]processing_system7_0_axi_periph_M00_AXI_WDATA;
wire processing_system7_0_axi_periph_M00_AXI_WREADY;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_WVALID;
wire [0:0]rst_processing_system7_0_100M_interconnect_aresetn;
wire [0:0]rst_processing_system7_0_100M_peripheral_aresetn;
assign BRAM_PORTB_dout[31:0] = matrix_mult_0_a_PORTA_DOUT;
assign M00_AXI_araddr[31:0] = axi_mem_intercon_M00_AXI_ARADDR;
assign M00_AXI_arburst[1:0] = axi_mem_intercon_M00_AXI_ARBURST;
assign M00_AXI_arcache[3:0] = axi_mem_intercon_M00_AXI_ARCACHE;
assign M00_AXI_arlen[3:0] = axi_mem_intercon_M00_AXI_ARLEN;
assign M00_AXI_arlock[1:0] = axi_mem_intercon_M00_AXI_ARLOCK;
assign M00_AXI_arprot[2:0] = axi_mem_intercon_M00_AXI_ARPROT;
assign M00_AXI_arqos[3:0] = axi_mem_intercon_M00_AXI_ARQOS;
assign M00_AXI_arsize[2:0] = axi_mem_intercon_M00_AXI_ARSIZE;
assign M00_AXI_arvalid = axi_mem_intercon_M00_AXI_ARVALID;
assign M00_AXI_awaddr[31:0] = axi_mem_intercon_M00_AXI_AWADDR;
assign M00_AXI_awburst[1:0] = axi_mem_intercon_M00_AXI_AWBURST;
assign M00_AXI_awcache[3:0] = axi_mem_intercon_M00_AXI_AWCACHE;
assign M00_AXI_awlen[3:0] = axi_mem_intercon_M00_AXI_AWLEN;
assign M00_AXI_awlock[1:0] = axi_mem_intercon_M00_AXI_AWLOCK;
assign M00_AXI_awprot[2:0] = axi_mem_intercon_M00_AXI_AWPROT;
assign M00_AXI_awqos[3:0] = axi_mem_intercon_M00_AXI_AWQOS;
assign M00_AXI_awsize[2:0] = axi_mem_intercon_M00_AXI_AWSIZE;
assign M00_AXI_awvalid = axi_mem_intercon_M00_AXI_AWVALID;
assign M00_AXI_bready = axi_mem_intercon_M00_AXI_BREADY;
assign M00_AXI_rready = axi_mem_intercon_M00_AXI_RREADY;
assign M00_AXI_wdata[63:0] = axi_mem_intercon_M00_AXI_WDATA;
assign M00_AXI_wlast = axi_mem_intercon_M00_AXI_WLAST;
assign M00_AXI_wstrb[7:0] = axi_mem_intercon_M00_AXI_WSTRB;
assign M00_AXI_wvalid = axi_mem_intercon_M00_AXI_WVALID;
assign S_AXI_LITE_arready[0] = processing_system7_0_axi_periph_M00_AXI_ARREADY;
assign S_AXI_LITE_awready[0] = processing_system7_0_axi_periph_M00_AXI_AWREADY;
assign S_AXI_LITE_bresp[1:0] = processing_system7_0_axi_periph_M00_AXI_BRESP;
assign S_AXI_LITE_bvalid[0] = processing_system7_0_axi_periph_M00_AXI_BVALID;
assign S_AXI_LITE_rdata[31:0] = processing_system7_0_axi_periph_M00_AXI_RDATA;
assign S_AXI_LITE_rresp[1:0] = processing_system7_0_axi_periph_M00_AXI_RRESP;
assign S_AXI_LITE_rvalid[0] = processing_system7_0_axi_periph_M00_AXI_RVALID;
assign S_AXI_LITE_wready[0] = processing_system7_0_axi_periph_M00_AXI_WREADY;
assign axi_mem_intercon_M00_AXI_ARREADY = M00_AXI_arready;
assign axi_mem_intercon_M00_AXI_AWREADY = M00_AXI_awready;
assign axi_mem_intercon_M00_AXI_BRESP = M00_AXI_bresp[1:0];
assign axi_mem_intercon_M00_AXI_BVALID = M00_AXI_bvalid;
assign axi_mem_intercon_M00_AXI_RDATA = M00_AXI_rdata[63:0];
assign axi_mem_intercon_M00_AXI_RLAST = M00_AXI_rlast;
assign axi_mem_intercon_M00_AXI_RRESP = M00_AXI_rresp[1:0];
assign axi_mem_intercon_M00_AXI_RVALID = M00_AXI_rvalid;
assign axi_mem_intercon_M00_AXI_WREADY = M00_AXI_wready;
assign matrix_mult_0_a_PORTA_ADDR = BRAM_PORTB_addr[31:0];
assign matrix_mult_0_a_PORTA_CLK = BRAM_PORTB_clk;
assign matrix_mult_0_a_PORTA_DIN = BRAM_PORTB_din[31:0];
assign matrix_mult_0_a_PORTA_EN = BRAM_PORTB_en;
assign matrix_mult_0_a_PORTA_RST = BRAM_PORTB_rst;
assign matrix_mult_0_a_PORTA_WE = BRAM_PORTB_we[3:0];
assign processing_system7_0_FCLK_CLK0 = s_axi_lite_aclk;
assign processing_system7_0_axi_periph_M00_AXI_ARADDR = S_AXI_LITE_araddr[31:0];
assign processing_system7_0_axi_periph_M00_AXI_ARVALID = S_AXI_LITE_arvalid[0];
assign processing_system7_0_axi_periph_M00_AXI_AWADDR = S_AXI_LITE_awaddr[31:0];
assign processing_system7_0_axi_periph_M00_AXI_AWVALID = S_AXI_LITE_awvalid[0];
assign processing_system7_0_axi_periph_M00_AXI_BREADY = S_AXI_LITE_bready[0];
assign processing_system7_0_axi_periph_M00_AXI_RREADY = S_AXI_LITE_rready[0];
assign processing_system7_0_axi_periph_M00_AXI_WDATA = S_AXI_LITE_wdata[31:0];
assign processing_system7_0_axi_periph_M00_AXI_WVALID = S_AXI_LITE_wvalid[0];
assign rst_processing_system7_0_100M_interconnect_aresetn = ARESETN[0];
assign rst_processing_system7_0_100M_peripheral_aresetn = s_axi_lite_aresetn[0];
design_1_axi_bram_ctrl_0_2 axi_bram_ctrl_0
(.bram_addr_a(axi_bram_ctrl_0_BRAM_PORTA_ADDR),
.bram_clk_a(axi_bram_ctrl_0_BRAM_PORTA_CLK),
.bram_en_a(axi_bram_ctrl_0_BRAM_PORTA_EN),
.bram_rddata_a(axi_bram_ctrl_0_BRAM_PORTA_DOUT),
.bram_rst_a(axi_bram_ctrl_0_BRAM_PORTA_RST),
.bram_we_a(axi_bram_ctrl_0_BRAM_PORTA_WE),
.bram_wrdata_a(axi_bram_ctrl_0_BRAM_PORTA_DIN),
.s_axi_aclk(processing_system7_0_FCLK_CLK0),
.s_axi_araddr(axi_mem_intercon_M01_AXI_ARADDR),
.s_axi_arburst(axi_mem_intercon_M01_AXI_ARBURST),
.s_axi_arcache(axi_mem_intercon_M01_AXI_ARCACHE),
.s_axi_aresetn(rst_processing_system7_0_100M_peripheral_aresetn),
.s_axi_arlen(axi_mem_intercon_M01_AXI_ARLEN),
.s_axi_arlock(axi_mem_intercon_M01_AXI_ARLOCK),
.s_axi_arprot(axi_mem_intercon_M01_AXI_ARPROT),
.s_axi_arready(axi_mem_intercon_M01_AXI_ARREADY),
.s_axi_arsize(axi_mem_intercon_M01_AXI_ARSIZE),
.s_axi_arvalid(axi_mem_intercon_M01_AXI_ARVALID),
.s_axi_awaddr(axi_mem_intercon_M01_AXI_AWADDR),
.s_axi_awburst(axi_mem_intercon_M01_AXI_AWBURST),
.s_axi_awcache(axi_mem_intercon_M01_AXI_AWCACHE),
.s_axi_awlen(axi_mem_intercon_M01_AXI_AWLEN),
.s_axi_awlock(axi_mem_intercon_M01_AXI_AWLOCK),
.s_axi_awprot(axi_mem_intercon_M01_AXI_AWPROT),
.s_axi_awready(axi_mem_intercon_M01_AXI_AWREADY),
.s_axi_awsize(axi_mem_intercon_M01_AXI_AWSIZE),
.s_axi_awvalid(axi_mem_intercon_M01_AXI_AWVALID),
.s_axi_bready(axi_mem_intercon_M01_AXI_BREADY),
.s_axi_bresp(axi_mem_intercon_M01_AXI_BRESP),
.s_axi_bvalid(axi_mem_intercon_M01_AXI_BVALID),
.s_axi_rdata(axi_mem_intercon_M01_AXI_RDATA),
.s_axi_rlast(axi_mem_intercon_M01_AXI_RLAST),
.s_axi_rready(axi_mem_intercon_M01_AXI_RREADY),
.s_axi_rresp(axi_mem_intercon_M01_AXI_RRESP),
.s_axi_rvalid(axi_mem_intercon_M01_AXI_RVALID),
.s_axi_wdata(axi_mem_intercon_M01_AXI_WDATA),
.s_axi_wlast(axi_mem_intercon_M01_AXI_WLAST),
.s_axi_wready(axi_mem_intercon_M01_AXI_WREADY),
.s_axi_wstrb(axi_mem_intercon_M01_AXI_WSTRB),
.s_axi_wvalid(axi_mem_intercon_M01_AXI_WVALID));
design_1_axi_cdma_0_3 axi_cdma_0
(.m_axi_aclk(processing_system7_0_FCLK_CLK0),
.m_axi_araddr(axi_cdma_0_M_AXI_ARADDR),
.m_axi_arburst(axi_cdma_0_M_AXI_ARBURST),
.m_axi_arcache(axi_cdma_0_M_AXI_ARCACHE),
.m_axi_arlen(axi_cdma_0_M_AXI_ARLEN),
.m_axi_arprot(axi_cdma_0_M_AXI_ARPROT),
.m_axi_arready(axi_cdma_0_M_AXI_ARREADY),
.m_axi_arsize(axi_cdma_0_M_AXI_ARSIZE),
.m_axi_arvalid(axi_cdma_0_M_AXI_ARVALID),
.m_axi_awaddr(axi_cdma_0_M_AXI_AWADDR),
.m_axi_awburst(axi_cdma_0_M_AXI_AWBURST),
.m_axi_awcache(axi_cdma_0_M_AXI_AWCACHE),
.m_axi_awlen(axi_cdma_0_M_AXI_AWLEN),
.m_axi_awprot(axi_cdma_0_M_AXI_AWPROT),
.m_axi_awready(axi_cdma_0_M_AXI_AWREADY),
.m_axi_awsize(axi_cdma_0_M_AXI_AWSIZE),
.m_axi_awvalid(axi_cdma_0_M_AXI_AWVALID),
.m_axi_bready(axi_cdma_0_M_AXI_BREADY),
.m_axi_bresp(axi_cdma_0_M_AXI_BRESP),
.m_axi_bvalid(axi_cdma_0_M_AXI_BVALID),
.m_axi_rdata(axi_cdma_0_M_AXI_RDATA),
.m_axi_rlast(axi_cdma_0_M_AXI_RLAST),
.m_axi_rready(axi_cdma_0_M_AXI_RREADY),
.m_axi_rresp(axi_cdma_0_M_AXI_RRESP),
.m_axi_rvalid(axi_cdma_0_M_AXI_RVALID),
.m_axi_wdata(axi_cdma_0_M_AXI_WDATA),
.m_axi_wlast(axi_cdma_0_M_AXI_WLAST),
.m_axi_wready(axi_cdma_0_M_AXI_WREADY),
.m_axi_wstrb(axi_cdma_0_M_AXI_WSTRB),
.m_axi_wvalid(axi_cdma_0_M_AXI_WVALID),
.s_axi_lite_aclk(processing_system7_0_FCLK_CLK0),
.s_axi_lite_araddr(processing_system7_0_axi_periph_M00_AXI_ARADDR[5:0]),
.s_axi_lite_aresetn(rst_processing_system7_0_100M_peripheral_aresetn),
.s_axi_lite_arready(processing_system7_0_axi_periph_M00_AXI_ARREADY),
.s_axi_lite_arvalid(processing_system7_0_axi_periph_M00_AXI_ARVALID),
.s_axi_lite_awaddr(processing_system7_0_axi_periph_M00_AXI_AWADDR[5:0]),
.s_axi_lite_awready(processing_system7_0_axi_periph_M00_AXI_AWREADY),
.s_axi_lite_awvalid(processing_system7_0_axi_periph_M00_AXI_AWVALID),
.s_axi_lite_bready(processing_system7_0_axi_periph_M00_AXI_BREADY),
.s_axi_lite_bresp(processing_system7_0_axi_periph_M00_AXI_BRESP),
.s_axi_lite_bvalid(processing_system7_0_axi_periph_M00_AXI_BVALID),
.s_axi_lite_rdata(processing_system7_0_axi_periph_M00_AXI_RDATA),
.s_axi_lite_rready(processing_system7_0_axi_periph_M00_AXI_RREADY),
.s_axi_lite_rresp(processing_system7_0_axi_periph_M00_AXI_RRESP),
.s_axi_lite_rvalid(processing_system7_0_axi_periph_M00_AXI_RVALID),
.s_axi_lite_wdata(processing_system7_0_axi_periph_M00_AXI_WDATA),
.s_axi_lite_wready(processing_system7_0_axi_periph_M00_AXI_WREADY),
.s_axi_lite_wvalid(processing_system7_0_axi_periph_M00_AXI_WVALID));
design_1_axi_mem_intercon_3 axi_mem_intercon
(.ACLK(processing_system7_0_FCLK_CLK0),
.ARESETN(rst_processing_system7_0_100M_interconnect_aresetn),
.M00_ACLK(processing_system7_0_FCLK_CLK0),
.M00_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.M00_AXI_araddr(axi_mem_intercon_M00_AXI_ARADDR),
.M00_AXI_arburst(axi_mem_intercon_M00_AXI_ARBURST),
.M00_AXI_arcache(axi_mem_intercon_M00_AXI_ARCACHE),
.M00_AXI_arlen(axi_mem_intercon_M00_AXI_ARLEN),
.M00_AXI_arlock(axi_mem_intercon_M00_AXI_ARLOCK),
.M00_AXI_arprot(axi_mem_intercon_M00_AXI_ARPROT),
.M00_AXI_arqos(axi_mem_intercon_M00_AXI_ARQOS),
.M00_AXI_arready(axi_mem_intercon_M00_AXI_ARREADY),
.M00_AXI_arsize(axi_mem_intercon_M00_AXI_ARSIZE),
.M00_AXI_arvalid(axi_mem_intercon_M00_AXI_ARVALID),
.M00_AXI_awaddr(axi_mem_intercon_M00_AXI_AWADDR),
.M00_AXI_awburst(axi_mem_intercon_M00_AXI_AWBURST),
.M00_AXI_awcache(axi_mem_intercon_M00_AXI_AWCACHE),
.M00_AXI_awlen(axi_mem_intercon_M00_AXI_AWLEN),
.M00_AXI_awlock(axi_mem_intercon_M00_AXI_AWLOCK),
.M00_AXI_awprot(axi_mem_intercon_M00_AXI_AWPROT),
.M00_AXI_awqos(axi_mem_intercon_M00_AXI_AWQOS),
.M00_AXI_awready(axi_mem_intercon_M00_AXI_AWREADY),
.M00_AXI_awsize(axi_mem_intercon_M00_AXI_AWSIZE),
.M00_AXI_awvalid(axi_mem_intercon_M00_AXI_AWVALID),
.M00_AXI_bready(axi_mem_intercon_M00_AXI_BREADY),
.M00_AXI_bresp(axi_mem_intercon_M00_AXI_BRESP),
.M00_AXI_bvalid(axi_mem_intercon_M00_AXI_BVALID),
.M00_AXI_rdata(axi_mem_intercon_M00_AXI_RDATA),
.M00_AXI_rlast(axi_mem_intercon_M00_AXI_RLAST),
.M00_AXI_rready(axi_mem_intercon_M00_AXI_RREADY),
.M00_AXI_rresp(axi_mem_intercon_M00_AXI_RRESP),
.M00_AXI_rvalid(axi_mem_intercon_M00_AXI_RVALID),
.M00_AXI_wdata(axi_mem_intercon_M00_AXI_WDATA),
.M00_AXI_wlast(axi_mem_intercon_M00_AXI_WLAST),
.M00_AXI_wready(axi_mem_intercon_M00_AXI_WREADY),
.M00_AXI_wstrb(axi_mem_intercon_M00_AXI_WSTRB),
.M00_AXI_wvalid(axi_mem_intercon_M00_AXI_WVALID),
.M01_ACLK(processing_system7_0_FCLK_CLK0),
.M01_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.M01_AXI_araddr(axi_mem_intercon_M01_AXI_ARADDR),
.M01_AXI_arburst(axi_mem_intercon_M01_AXI_ARBURST),
.M01_AXI_arcache(axi_mem_intercon_M01_AXI_ARCACHE),
.M01_AXI_arlen(axi_mem_intercon_M01_AXI_ARLEN),
.M01_AXI_arlock(axi_mem_intercon_M01_AXI_ARLOCK),
.M01_AXI_arprot(axi_mem_intercon_M01_AXI_ARPROT),
.M01_AXI_arready(axi_mem_intercon_M01_AXI_ARREADY),
.M01_AXI_arsize(axi_mem_intercon_M01_AXI_ARSIZE),
.M01_AXI_arvalid(axi_mem_intercon_M01_AXI_ARVALID),
.M01_AXI_awaddr(axi_mem_intercon_M01_AXI_AWADDR),
.M01_AXI_awburst(axi_mem_intercon_M01_AXI_AWBURST),
.M01_AXI_awcache(axi_mem_intercon_M01_AXI_AWCACHE),
.M01_AXI_awlen(axi_mem_intercon_M01_AXI_AWLEN),
.M01_AXI_awlock(axi_mem_intercon_M01_AXI_AWLOCK),
.M01_AXI_awprot(axi_mem_intercon_M01_AXI_AWPROT),
.M01_AXI_awready(axi_mem_intercon_M01_AXI_AWREADY),
.M01_AXI_awsize(axi_mem_intercon_M01_AXI_AWSIZE),
.M01_AXI_awvalid(axi_mem_intercon_M01_AXI_AWVALID),
.M01_AXI_bready(axi_mem_intercon_M01_AXI_BREADY),
.M01_AXI_bresp(axi_mem_intercon_M01_AXI_BRESP),
.M01_AXI_bvalid(axi_mem_intercon_M01_AXI_BVALID),
.M01_AXI_rdata(axi_mem_intercon_M01_AXI_RDATA),
.M01_AXI_rlast(axi_mem_intercon_M01_AXI_RLAST),
.M01_AXI_rready(axi_mem_intercon_M01_AXI_RREADY),
.M01_AXI_rresp(axi_mem_intercon_M01_AXI_RRESP),
.M01_AXI_rvalid(axi_mem_intercon_M01_AXI_RVALID),
.M01_AXI_wdata(axi_mem_intercon_M01_AXI_WDATA),
.M01_AXI_wlast(axi_mem_intercon_M01_AXI_WLAST),
.M01_AXI_wready(axi_mem_intercon_M01_AXI_WREADY),
.M01_AXI_wstrb(axi_mem_intercon_M01_AXI_WSTRB),
.M01_AXI_wvalid(axi_mem_intercon_M01_AXI_WVALID),
.S00_ACLK(processing_system7_0_FCLK_CLK0),
.S00_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.S00_AXI_araddr(axi_cdma_0_M_AXI_ARADDR),
.S00_AXI_arburst(axi_cdma_0_M_AXI_ARBURST),
.S00_AXI_arcache(axi_cdma_0_M_AXI_ARCACHE),
.S00_AXI_arlen(axi_cdma_0_M_AXI_ARLEN),
.S00_AXI_arprot(axi_cdma_0_M_AXI_ARPROT),
.S00_AXI_arready(axi_cdma_0_M_AXI_ARREADY),
.S00_AXI_arsize(axi_cdma_0_M_AXI_ARSIZE),
.S00_AXI_arvalid(axi_cdma_0_M_AXI_ARVALID),
.S00_AXI_awaddr(axi_cdma_0_M_AXI_AWADDR),
.S00_AXI_awburst(axi_cdma_0_M_AXI_AWBURST),
.S00_AXI_awcache(axi_cdma_0_M_AXI_AWCACHE),
.S00_AXI_awlen(axi_cdma_0_M_AXI_AWLEN),
.S00_AXI_awprot(axi_cdma_0_M_AXI_AWPROT),
.S00_AXI_awready(axi_cdma_0_M_AXI_AWREADY),
.S00_AXI_awsize(axi_cdma_0_M_AXI_AWSIZE),
.S00_AXI_awvalid(axi_cdma_0_M_AXI_AWVALID),
.S00_AXI_bready(axi_cdma_0_M_AXI_BREADY),
.S00_AXI_bresp(axi_cdma_0_M_AXI_BRESP),
.S00_AXI_bvalid(axi_cdma_0_M_AXI_BVALID),
.S00_AXI_rdata(axi_cdma_0_M_AXI_RDATA),
.S00_AXI_rlast(axi_cdma_0_M_AXI_RLAST),
.S00_AXI_rready(axi_cdma_0_M_AXI_RREADY),
.S00_AXI_rresp(axi_cdma_0_M_AXI_RRESP),
.S00_AXI_rvalid(axi_cdma_0_M_AXI_RVALID),
.S00_AXI_wdata(axi_cdma_0_M_AXI_WDATA),
.S00_AXI_wlast(axi_cdma_0_M_AXI_WLAST),
.S00_AXI_wready(axi_cdma_0_M_AXI_WREADY),
.S00_AXI_wstrb(axi_cdma_0_M_AXI_WSTRB),
.S00_AXI_wvalid(axi_cdma_0_M_AXI_WVALID));
design_1_blk_mem_gen_0_3 blk_mem_gen_0
(.addra({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,axi_bram_ctrl_0_BRAM_PORTA_ADDR}),
.addrb(matrix_mult_0_a_PORTA_ADDR),
.clka(axi_bram_ctrl_0_BRAM_PORTA_CLK),
.clkb(matrix_mult_0_a_PORTA_CLK),
.dina(axi_bram_ctrl_0_BRAM_PORTA_DIN),
.dinb(matrix_mult_0_a_PORTA_DIN),
.douta(axi_bram_ctrl_0_BRAM_PORTA_DOUT),
.doutb(matrix_mult_0_a_PORTA_DOUT),
.ena(axi_bram_ctrl_0_BRAM_PORTA_EN),
.enb(matrix_mult_0_a_PORTA_EN),
.rsta(axi_bram_ctrl_0_BRAM_PORTA_RST),
.rstb(matrix_mult_0_a_PORTA_RST),
.wea(axi_bram_ctrl_0_BRAM_PORTA_WE),
.web(matrix_mult_0_a_PORTA_WE));
endmodule
module m00_couplers_imp_10LCABC
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arburst,
M_AXI_arcache,
M_AXI_arlen,
M_AXI_arlock,
M_AXI_arprot,
M_AXI_arqos,
M_AXI_arready,
M_AXI_arsize,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awburst,
M_AXI_awcache,
M_AXI_awlen,
M_AXI_awlock,
M_AXI_awprot,
M_AXI_awqos,
M_AXI_awready,
M_AXI_awsize,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rlast,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wlast,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arregion,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awregion,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input M_ARESETN;
output [31:0]M_AXI_araddr;
output [1:0]M_AXI_arburst;
output [3:0]M_AXI_arcache;
output [3:0]M_AXI_arlen;
output [1:0]M_AXI_arlock;
output [2:0]M_AXI_arprot;
output [3:0]M_AXI_arqos;
input M_AXI_arready;
output [2:0]M_AXI_arsize;
output M_AXI_arvalid;
output [31:0]M_AXI_awaddr;
output [1:0]M_AXI_awburst;
output [3:0]M_AXI_awcache;
output [3:0]M_AXI_awlen;
output [1:0]M_AXI_awlock;
output [2:0]M_AXI_awprot;
output [3:0]M_AXI_awqos;
input M_AXI_awready;
output [2:0]M_AXI_awsize;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [63:0]M_AXI_rdata;
input M_AXI_rlast;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [63:0]M_AXI_wdata;
output M_AXI_wlast;
input M_AXI_wready;
output [7:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [7:0]S_AXI_arlen;
input [0:0]S_AXI_arlock;
input [2:0]S_AXI_arprot;
input [3:0]S_AXI_arqos;
output S_AXI_arready;
input [3:0]S_AXI_arregion;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [7:0]S_AXI_awlen;
input [0:0]S_AXI_awlock;
input [2:0]S_AXI_awprot;
input [3:0]S_AXI_awqos;
output S_AXI_awready;
input [3:0]S_AXI_awregion;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [63:0]S_AXI_rdata;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [63:0]S_AXI_wdata;
input S_AXI_wlast;
output S_AXI_wready;
input [7:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire S_ACLK_1;
wire S_ARESETN_1;
wire [31:0]auto_pc_to_m00_couplers_ARADDR;
wire [1:0]auto_pc_to_m00_couplers_ARBURST;
wire [3:0]auto_pc_to_m00_couplers_ARCACHE;
wire [3:0]auto_pc_to_m00_couplers_ARLEN;
wire [1:0]auto_pc_to_m00_couplers_ARLOCK;
wire [2:0]auto_pc_to_m00_couplers_ARPROT;
wire [3:0]auto_pc_to_m00_couplers_ARQOS;
wire auto_pc_to_m00_couplers_ARREADY;
wire [2:0]auto_pc_to_m00_couplers_ARSIZE;
wire auto_pc_to_m00_couplers_ARVALID;
wire [31:0]auto_pc_to_m00_couplers_AWADDR;
wire [1:0]auto_pc_to_m00_couplers_AWBURST;
wire [3:0]auto_pc_to_m00_couplers_AWCACHE;
wire [3:0]auto_pc_to_m00_couplers_AWLEN;
wire [1:0]auto_pc_to_m00_couplers_AWLOCK;
wire [2:0]auto_pc_to_m00_couplers_AWPROT;
wire [3:0]auto_pc_to_m00_couplers_AWQOS;
wire auto_pc_to_m00_couplers_AWREADY;
wire [2:0]auto_pc_to_m00_couplers_AWSIZE;
wire auto_pc_to_m00_couplers_AWVALID;
wire auto_pc_to_m00_couplers_BREADY;
wire [1:0]auto_pc_to_m00_couplers_BRESP;
wire auto_pc_to_m00_couplers_BVALID;
wire [63:0]auto_pc_to_m00_couplers_RDATA;
wire auto_pc_to_m00_couplers_RLAST;
wire auto_pc_to_m00_couplers_RREADY;
wire [1:0]auto_pc_to_m00_couplers_RRESP;
wire auto_pc_to_m00_couplers_RVALID;
wire [63:0]auto_pc_to_m00_couplers_WDATA;
wire auto_pc_to_m00_couplers_WLAST;
wire auto_pc_to_m00_couplers_WREADY;
wire [7:0]auto_pc_to_m00_couplers_WSTRB;
wire auto_pc_to_m00_couplers_WVALID;
wire [31:0]m00_couplers_to_auto_pc_ARADDR;
wire [1:0]m00_couplers_to_auto_pc_ARBURST;
wire [3:0]m00_couplers_to_auto_pc_ARCACHE;
wire [7:0]m00_couplers_to_auto_pc_ARLEN;
wire [0:0]m00_couplers_to_auto_pc_ARLOCK;
wire [2:0]m00_couplers_to_auto_pc_ARPROT;
wire [3:0]m00_couplers_to_auto_pc_ARQOS;
wire m00_couplers_to_auto_pc_ARREADY;
wire [3:0]m00_couplers_to_auto_pc_ARREGION;
wire [2:0]m00_couplers_to_auto_pc_ARSIZE;
wire m00_couplers_to_auto_pc_ARVALID;
wire [31:0]m00_couplers_to_auto_pc_AWADDR;
wire [1:0]m00_couplers_to_auto_pc_AWBURST;
wire [3:0]m00_couplers_to_auto_pc_AWCACHE;
wire [7:0]m00_couplers_to_auto_pc_AWLEN;
wire [0:0]m00_couplers_to_auto_pc_AWLOCK;
wire [2:0]m00_couplers_to_auto_pc_AWPROT;
wire [3:0]m00_couplers_to_auto_pc_AWQOS;
wire m00_couplers_to_auto_pc_AWREADY;
wire [3:0]m00_couplers_to_auto_pc_AWREGION;
wire [2:0]m00_couplers_to_auto_pc_AWSIZE;
wire m00_couplers_to_auto_pc_AWVALID;
wire m00_couplers_to_auto_pc_BREADY;
wire [1:0]m00_couplers_to_auto_pc_BRESP;
wire m00_couplers_to_auto_pc_BVALID;
wire [63:0]m00_couplers_to_auto_pc_RDATA;
wire m00_couplers_to_auto_pc_RLAST;
wire m00_couplers_to_auto_pc_RREADY;
wire [1:0]m00_couplers_to_auto_pc_RRESP;
wire m00_couplers_to_auto_pc_RVALID;
wire [63:0]m00_couplers_to_auto_pc_WDATA;
wire m00_couplers_to_auto_pc_WLAST;
wire m00_couplers_to_auto_pc_WREADY;
wire [7:0]m00_couplers_to_auto_pc_WSTRB;
wire m00_couplers_to_auto_pc_WVALID;
assign M_AXI_araddr[31:0] = auto_pc_to_m00_couplers_ARADDR;
assign M_AXI_arburst[1:0] = auto_pc_to_m00_couplers_ARBURST;
assign M_AXI_arcache[3:0] = auto_pc_to_m00_couplers_ARCACHE;
assign M_AXI_arlen[3:0] = auto_pc_to_m00_couplers_ARLEN;
assign M_AXI_arlock[1:0] = auto_pc_to_m00_couplers_ARLOCK;
assign M_AXI_arprot[2:0] = auto_pc_to_m00_couplers_ARPROT;
assign M_AXI_arqos[3:0] = auto_pc_to_m00_couplers_ARQOS;
assign M_AXI_arsize[2:0] = auto_pc_to_m00_couplers_ARSIZE;
assign M_AXI_arvalid = auto_pc_to_m00_couplers_ARVALID;
assign M_AXI_awaddr[31:0] = auto_pc_to_m00_couplers_AWADDR;
assign M_AXI_awburst[1:0] = auto_pc_to_m00_couplers_AWBURST;
assign M_AXI_awcache[3:0] = auto_pc_to_m00_couplers_AWCACHE;
assign M_AXI_awlen[3:0] = auto_pc_to_m00_couplers_AWLEN;
assign M_AXI_awlock[1:0] = auto_pc_to_m00_couplers_AWLOCK;
assign M_AXI_awprot[2:0] = auto_pc_to_m00_couplers_AWPROT;
assign M_AXI_awqos[3:0] = auto_pc_to_m00_couplers_AWQOS;
assign M_AXI_awsize[2:0] = auto_pc_to_m00_couplers_AWSIZE;
assign M_AXI_awvalid = auto_pc_to_m00_couplers_AWVALID;
assign M_AXI_bready = auto_pc_to_m00_couplers_BREADY;
assign M_AXI_rready = auto_pc_to_m00_couplers_RREADY;
assign M_AXI_wdata[63:0] = auto_pc_to_m00_couplers_WDATA;
assign M_AXI_wlast = auto_pc_to_m00_couplers_WLAST;
assign M_AXI_wstrb[7:0] = auto_pc_to_m00_couplers_WSTRB;
assign M_AXI_wvalid = auto_pc_to_m00_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN;
assign S_AXI_arready = m00_couplers_to_auto_pc_ARREADY;
assign S_AXI_awready = m00_couplers_to_auto_pc_AWREADY;
assign S_AXI_bresp[1:0] = m00_couplers_to_auto_pc_BRESP;
assign S_AXI_bvalid = m00_couplers_to_auto_pc_BVALID;
assign S_AXI_rdata[63:0] = m00_couplers_to_auto_pc_RDATA;
assign S_AXI_rlast = m00_couplers_to_auto_pc_RLAST;
assign S_AXI_rresp[1:0] = m00_couplers_to_auto_pc_RRESP;
assign S_AXI_rvalid = m00_couplers_to_auto_pc_RVALID;
assign S_AXI_wready = m00_couplers_to_auto_pc_WREADY;
assign auto_pc_to_m00_couplers_ARREADY = M_AXI_arready;
assign auto_pc_to_m00_couplers_AWREADY = M_AXI_awready;
assign auto_pc_to_m00_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_pc_to_m00_couplers_BVALID = M_AXI_bvalid;
assign auto_pc_to_m00_couplers_RDATA = M_AXI_rdata[63:0];
assign auto_pc_to_m00_couplers_RLAST = M_AXI_rlast;
assign auto_pc_to_m00_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_pc_to_m00_couplers_RVALID = M_AXI_rvalid;
assign auto_pc_to_m00_couplers_WREADY = M_AXI_wready;
assign m00_couplers_to_auto_pc_ARADDR = S_AXI_araddr[31:0];
assign m00_couplers_to_auto_pc_ARBURST = S_AXI_arburst[1:0];
assign m00_couplers_to_auto_pc_ARCACHE = S_AXI_arcache[3:0];
assign m00_couplers_to_auto_pc_ARLEN = S_AXI_arlen[7:0];
assign m00_couplers_to_auto_pc_ARLOCK = S_AXI_arlock[0];
assign m00_couplers_to_auto_pc_ARPROT = S_AXI_arprot[2:0];
assign m00_couplers_to_auto_pc_ARQOS = S_AXI_arqos[3:0];
assign m00_couplers_to_auto_pc_ARREGION = S_AXI_arregion[3:0];
assign m00_couplers_to_auto_pc_ARSIZE = S_AXI_arsize[2:0];
assign m00_couplers_to_auto_pc_ARVALID = S_AXI_arvalid;
assign m00_couplers_to_auto_pc_AWADDR = S_AXI_awaddr[31:0];
assign m00_couplers_to_auto_pc_AWBURST = S_AXI_awburst[1:0];
assign m00_couplers_to_auto_pc_AWCACHE = S_AXI_awcache[3:0];
assign m00_couplers_to_auto_pc_AWLEN = S_AXI_awlen[7:0];
assign m00_couplers_to_auto_pc_AWLOCK = S_AXI_awlock[0];
assign m00_couplers_to_auto_pc_AWPROT = S_AXI_awprot[2:0];
assign m00_couplers_to_auto_pc_AWQOS = S_AXI_awqos[3:0];
assign m00_couplers_to_auto_pc_AWREGION = S_AXI_awregion[3:0];
assign m00_couplers_to_auto_pc_AWSIZE = S_AXI_awsize[2:0];
assign m00_couplers_to_auto_pc_AWVALID = S_AXI_awvalid;
assign m00_couplers_to_auto_pc_BREADY = S_AXI_bready;
assign m00_couplers_to_auto_pc_RREADY = S_AXI_rready;
assign m00_couplers_to_auto_pc_WDATA = S_AXI_wdata[63:0];
assign m00_couplers_to_auto_pc_WLAST = S_AXI_wlast;
assign m00_couplers_to_auto_pc_WSTRB = S_AXI_wstrb[7:0];
assign m00_couplers_to_auto_pc_WVALID = S_AXI_wvalid;
design_1_auto_pc_1 auto_pc
(.aclk(S_ACLK_1),
.aresetn(S_ARESETN_1),
.m_axi_araddr(auto_pc_to_m00_couplers_ARADDR),
.m_axi_arburst(auto_pc_to_m00_couplers_ARBURST),
.m_axi_arcache(auto_pc_to_m00_couplers_ARCACHE),
.m_axi_arlen(auto_pc_to_m00_couplers_ARLEN),
.m_axi_arlock(auto_pc_to_m00_couplers_ARLOCK),
.m_axi_arprot(auto_pc_to_m00_couplers_ARPROT),
.m_axi_arqos(auto_pc_to_m00_couplers_ARQOS),
.m_axi_arready(auto_pc_to_m00_couplers_ARREADY),
.m_axi_arsize(auto_pc_to_m00_couplers_ARSIZE),
.m_axi_arvalid(auto_pc_to_m00_couplers_ARVALID),
.m_axi_awaddr(auto_pc_to_m00_couplers_AWADDR),
.m_axi_awburst(auto_pc_to_m00_couplers_AWBURST),
.m_axi_awcache(auto_pc_to_m00_couplers_AWCACHE),
.m_axi_awlen(auto_pc_to_m00_couplers_AWLEN),
.m_axi_awlock(auto_pc_to_m00_couplers_AWLOCK),
.m_axi_awprot(auto_pc_to_m00_couplers_AWPROT),
.m_axi_awqos(auto_pc_to_m00_couplers_AWQOS),
.m_axi_awready(auto_pc_to_m00_couplers_AWREADY),
.m_axi_awsize(auto_pc_to_m00_couplers_AWSIZE),
.m_axi_awvalid(auto_pc_to_m00_couplers_AWVALID),
.m_axi_bready(auto_pc_to_m00_couplers_BREADY),
.m_axi_bresp(auto_pc_to_m00_couplers_BRESP),
.m_axi_bvalid(auto_pc_to_m00_couplers_BVALID),
.m_axi_rdata(auto_pc_to_m00_couplers_RDATA),
.m_axi_rlast(auto_pc_to_m00_couplers_RLAST),
.m_axi_rready(auto_pc_to_m00_couplers_RREADY),
.m_axi_rresp(auto_pc_to_m00_couplers_RRESP),
.m_axi_rvalid(auto_pc_to_m00_couplers_RVALID),
.m_axi_wdata(auto_pc_to_m00_couplers_WDATA),
.m_axi_wlast(auto_pc_to_m00_couplers_WLAST),
.m_axi_wready(auto_pc_to_m00_couplers_WREADY),
.m_axi_wstrb(auto_pc_to_m00_couplers_WSTRB),
.m_axi_wvalid(auto_pc_to_m00_couplers_WVALID),
.s_axi_araddr(m00_couplers_to_auto_pc_ARADDR),
.s_axi_arburst(m00_couplers_to_auto_pc_ARBURST),
.s_axi_arcache(m00_couplers_to_auto_pc_ARCACHE),
.s_axi_arlen(m00_couplers_to_auto_pc_ARLEN),
.s_axi_arlock(m00_couplers_to_auto_pc_ARLOCK),
.s_axi_arprot(m00_couplers_to_auto_pc_ARPROT),
.s_axi_arqos(m00_couplers_to_auto_pc_ARQOS),
.s_axi_arready(m00_couplers_to_auto_pc_ARREADY),
.s_axi_arregion(m00_couplers_to_auto_pc_ARREGION),
.s_axi_arsize(m00_couplers_to_auto_pc_ARSIZE),
.s_axi_arvalid(m00_couplers_to_auto_pc_ARVALID),
.s_axi_awaddr(m00_couplers_to_auto_pc_AWADDR),
.s_axi_awburst(m00_couplers_to_auto_pc_AWBURST),
.s_axi_awcache(m00_couplers_to_auto_pc_AWCACHE),
.s_axi_awlen(m00_couplers_to_auto_pc_AWLEN),
.s_axi_awlock(m00_couplers_to_auto_pc_AWLOCK),
.s_axi_awprot(m00_couplers_to_auto_pc_AWPROT),
.s_axi_awqos(m00_couplers_to_auto_pc_AWQOS),
.s_axi_awready(m00_couplers_to_auto_pc_AWREADY),
.s_axi_awregion(m00_couplers_to_auto_pc_AWREGION),
.s_axi_awsize(m00_couplers_to_auto_pc_AWSIZE),
.s_axi_awvalid(m00_couplers_to_auto_pc_AWVALID),
.s_axi_bready(m00_couplers_to_auto_pc_BREADY),
.s_axi_bresp(m00_couplers_to_auto_pc_BRESP),
.s_axi_bvalid(m00_couplers_to_auto_pc_BVALID),
.s_axi_rdata(m00_couplers_to_auto_pc_RDATA),
.s_axi_rlast(m00_couplers_to_auto_pc_RLAST),
.s_axi_rready(m00_couplers_to_auto_pc_RREADY),
.s_axi_rresp(m00_couplers_to_auto_pc_RRESP),
.s_axi_rvalid(m00_couplers_to_auto_pc_RVALID),
.s_axi_wdata(m00_couplers_to_auto_pc_WDATA),
.s_axi_wlast(m00_couplers_to_auto_pc_WLAST),
.s_axi_wready(m00_couplers_to_auto_pc_WREADY),
.s_axi_wstrb(m00_couplers_to_auto_pc_WSTRB),
.s_axi_wvalid(m00_couplers_to_auto_pc_WVALID));
endmodule
module m00_couplers_imp_1KZV5AP
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arburst,
M_AXI_arcache,
M_AXI_arlen,
M_AXI_arlock,
M_AXI_arprot,
M_AXI_arqos,
M_AXI_arready,
M_AXI_arsize,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awburst,
M_AXI_awcache,
M_AXI_awlen,
M_AXI_awlock,
M_AXI_awprot,
M_AXI_awqos,
M_AXI_awready,
M_AXI_awsize,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rlast,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wlast,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arregion,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awregion,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input M_ARESETN;
output [31:0]M_AXI_araddr;
output [1:0]M_AXI_arburst;
output [3:0]M_AXI_arcache;
output [3:0]M_AXI_arlen;
output [1:0]M_AXI_arlock;
output [2:0]M_AXI_arprot;
output [3:0]M_AXI_arqos;
input M_AXI_arready;
output [2:0]M_AXI_arsize;
output M_AXI_arvalid;
output [31:0]M_AXI_awaddr;
output [1:0]M_AXI_awburst;
output [3:0]M_AXI_awcache;
output [3:0]M_AXI_awlen;
output [1:0]M_AXI_awlock;
output [2:0]M_AXI_awprot;
output [3:0]M_AXI_awqos;
input M_AXI_awready;
output [2:0]M_AXI_awsize;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [63:0]M_AXI_rdata;
input M_AXI_rlast;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [63:0]M_AXI_wdata;
output M_AXI_wlast;
input M_AXI_wready;
output [7:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [7:0]S_AXI_arlen;
input [0:0]S_AXI_arlock;
input [2:0]S_AXI_arprot;
input [3:0]S_AXI_arqos;
output S_AXI_arready;
input [3:0]S_AXI_arregion;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [7:0]S_AXI_awlen;
input [0:0]S_AXI_awlock;
input [2:0]S_AXI_awprot;
input [3:0]S_AXI_awqos;
output S_AXI_awready;
input [3:0]S_AXI_awregion;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [63:0]S_AXI_rdata;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [63:0]S_AXI_wdata;
input S_AXI_wlast;
output S_AXI_wready;
input [7:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire S_ACLK_1;
wire S_ARESETN_1;
wire [31:0]auto_pc_to_m00_couplers_ARADDR;
wire [1:0]auto_pc_to_m00_couplers_ARBURST;
wire [3:0]auto_pc_to_m00_couplers_ARCACHE;
wire [3:0]auto_pc_to_m00_couplers_ARLEN;
wire [1:0]auto_pc_to_m00_couplers_ARLOCK;
wire [2:0]auto_pc_to_m00_couplers_ARPROT;
wire [3:0]auto_pc_to_m00_couplers_ARQOS;
wire auto_pc_to_m00_couplers_ARREADY;
wire [2:0]auto_pc_to_m00_couplers_ARSIZE;
wire auto_pc_to_m00_couplers_ARVALID;
wire [31:0]auto_pc_to_m00_couplers_AWADDR;
wire [1:0]auto_pc_to_m00_couplers_AWBURST;
wire [3:0]auto_pc_to_m00_couplers_AWCACHE;
wire [3:0]auto_pc_to_m00_couplers_AWLEN;
wire [1:0]auto_pc_to_m00_couplers_AWLOCK;
wire [2:0]auto_pc_to_m00_couplers_AWPROT;
wire [3:0]auto_pc_to_m00_couplers_AWQOS;
wire auto_pc_to_m00_couplers_AWREADY;
wire [2:0]auto_pc_to_m00_couplers_AWSIZE;
wire auto_pc_to_m00_couplers_AWVALID;
wire auto_pc_to_m00_couplers_BREADY;
wire [1:0]auto_pc_to_m00_couplers_BRESP;
wire auto_pc_to_m00_couplers_BVALID;
wire [63:0]auto_pc_to_m00_couplers_RDATA;
wire auto_pc_to_m00_couplers_RLAST;
wire auto_pc_to_m00_couplers_RREADY;
wire [1:0]auto_pc_to_m00_couplers_RRESP;
wire auto_pc_to_m00_couplers_RVALID;
wire [63:0]auto_pc_to_m00_couplers_WDATA;
wire auto_pc_to_m00_couplers_WLAST;
wire auto_pc_to_m00_couplers_WREADY;
wire [7:0]auto_pc_to_m00_couplers_WSTRB;
wire auto_pc_to_m00_couplers_WVALID;
wire [31:0]m00_couplers_to_auto_pc_ARADDR;
wire [1:0]m00_couplers_to_auto_pc_ARBURST;
wire [3:0]m00_couplers_to_auto_pc_ARCACHE;
wire [7:0]m00_couplers_to_auto_pc_ARLEN;
wire [0:0]m00_couplers_to_auto_pc_ARLOCK;
wire [2:0]m00_couplers_to_auto_pc_ARPROT;
wire [3:0]m00_couplers_to_auto_pc_ARQOS;
wire m00_couplers_to_auto_pc_ARREADY;
wire [3:0]m00_couplers_to_auto_pc_ARREGION;
wire [2:0]m00_couplers_to_auto_pc_ARSIZE;
wire m00_couplers_to_auto_pc_ARVALID;
wire [31:0]m00_couplers_to_auto_pc_AWADDR;
wire [1:0]m00_couplers_to_auto_pc_AWBURST;
wire [3:0]m00_couplers_to_auto_pc_AWCACHE;
wire [7:0]m00_couplers_to_auto_pc_AWLEN;
wire [0:0]m00_couplers_to_auto_pc_AWLOCK;
wire [2:0]m00_couplers_to_auto_pc_AWPROT;
wire [3:0]m00_couplers_to_auto_pc_AWQOS;
wire m00_couplers_to_auto_pc_AWREADY;
wire [3:0]m00_couplers_to_auto_pc_AWREGION;
wire [2:0]m00_couplers_to_auto_pc_AWSIZE;
wire m00_couplers_to_auto_pc_AWVALID;
wire m00_couplers_to_auto_pc_BREADY;
wire [1:0]m00_couplers_to_auto_pc_BRESP;
wire m00_couplers_to_auto_pc_BVALID;
wire [63:0]m00_couplers_to_auto_pc_RDATA;
wire m00_couplers_to_auto_pc_RLAST;
wire m00_couplers_to_auto_pc_RREADY;
wire [1:0]m00_couplers_to_auto_pc_RRESP;
wire m00_couplers_to_auto_pc_RVALID;
wire [63:0]m00_couplers_to_auto_pc_WDATA;
wire m00_couplers_to_auto_pc_WLAST;
wire m00_couplers_to_auto_pc_WREADY;
wire [7:0]m00_couplers_to_auto_pc_WSTRB;
wire m00_couplers_to_auto_pc_WVALID;
assign M_AXI_araddr[31:0] = auto_pc_to_m00_couplers_ARADDR;
assign M_AXI_arburst[1:0] = auto_pc_to_m00_couplers_ARBURST;
assign M_AXI_arcache[3:0] = auto_pc_to_m00_couplers_ARCACHE;
assign M_AXI_arlen[3:0] = auto_pc_to_m00_couplers_ARLEN;
assign M_AXI_arlock[1:0] = auto_pc_to_m00_couplers_ARLOCK;
assign M_AXI_arprot[2:0] = auto_pc_to_m00_couplers_ARPROT;
assign M_AXI_arqos[3:0] = auto_pc_to_m00_couplers_ARQOS;
assign M_AXI_arsize[2:0] = auto_pc_to_m00_couplers_ARSIZE;
assign M_AXI_arvalid = auto_pc_to_m00_couplers_ARVALID;
assign M_AXI_awaddr[31:0] = auto_pc_to_m00_couplers_AWADDR;
assign M_AXI_awburst[1:0] = auto_pc_to_m00_couplers_AWBURST;
assign M_AXI_awcache[3:0] = auto_pc_to_m00_couplers_AWCACHE;
assign M_AXI_awlen[3:0] = auto_pc_to_m00_couplers_AWLEN;
assign M_AXI_awlock[1:0] = auto_pc_to_m00_couplers_AWLOCK;
assign M_AXI_awprot[2:0] = auto_pc_to_m00_couplers_AWPROT;
assign M_AXI_awqos[3:0] = auto_pc_to_m00_couplers_AWQOS;
assign M_AXI_awsize[2:0] = auto_pc_to_m00_couplers_AWSIZE;
assign M_AXI_awvalid = auto_pc_to_m00_couplers_AWVALID;
assign M_AXI_bready = auto_pc_to_m00_couplers_BREADY;
assign M_AXI_rready = auto_pc_to_m00_couplers_RREADY;
assign M_AXI_wdata[63:0] = auto_pc_to_m00_couplers_WDATA;
assign M_AXI_wlast = auto_pc_to_m00_couplers_WLAST;
assign M_AXI_wstrb[7:0] = auto_pc_to_m00_couplers_WSTRB;
assign M_AXI_wvalid = auto_pc_to_m00_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN;
assign S_AXI_arready = m00_couplers_to_auto_pc_ARREADY;
assign S_AXI_awready = m00_couplers_to_auto_pc_AWREADY;
assign S_AXI_bresp[1:0] = m00_couplers_to_auto_pc_BRESP;
assign S_AXI_bvalid = m00_couplers_to_auto_pc_BVALID;
assign S_AXI_rdata[63:0] = m00_couplers_to_auto_pc_RDATA;
assign S_AXI_rlast = m00_couplers_to_auto_pc_RLAST;
assign S_AXI_rresp[1:0] = m00_couplers_to_auto_pc_RRESP;
assign S_AXI_rvalid = m00_couplers_to_auto_pc_RVALID;
assign S_AXI_wready = m00_couplers_to_auto_pc_WREADY;
assign auto_pc_to_m00_couplers_ARREADY = M_AXI_arready;
assign auto_pc_to_m00_couplers_AWREADY = M_AXI_awready;
assign auto_pc_to_m00_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_pc_to_m00_couplers_BVALID = M_AXI_bvalid;
assign auto_pc_to_m00_couplers_RDATA = M_AXI_rdata[63:0];
assign auto_pc_to_m00_couplers_RLAST = M_AXI_rlast;
assign auto_pc_to_m00_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_pc_to_m00_couplers_RVALID = M_AXI_rvalid;
assign auto_pc_to_m00_couplers_WREADY = M_AXI_wready;
assign m00_couplers_to_auto_pc_ARADDR = S_AXI_araddr[31:0];
assign m00_couplers_to_auto_pc_ARBURST = S_AXI_arburst[1:0];
assign m00_couplers_to_auto_pc_ARCACHE = S_AXI_arcache[3:0];
assign m00_couplers_to_auto_pc_ARLEN = S_AXI_arlen[7:0];
assign m00_couplers_to_auto_pc_ARLOCK = S_AXI_arlock[0];
assign m00_couplers_to_auto_pc_ARPROT = S_AXI_arprot[2:0];
assign m00_couplers_to_auto_pc_ARQOS = S_AXI_arqos[3:0];
assign m00_couplers_to_auto_pc_ARREGION = S_AXI_arregion[3:0];
assign m00_couplers_to_auto_pc_ARSIZE = S_AXI_arsize[2:0];
assign m00_couplers_to_auto_pc_ARVALID = S_AXI_arvalid;
assign m00_couplers_to_auto_pc_AWADDR = S_AXI_awaddr[31:0];
assign m00_couplers_to_auto_pc_AWBURST = S_AXI_awburst[1:0];
assign m00_couplers_to_auto_pc_AWCACHE = S_AXI_awcache[3:0];
assign m00_couplers_to_auto_pc_AWLEN = S_AXI_awlen[7:0];
assign m00_couplers_to_auto_pc_AWLOCK = S_AXI_awlock[0];
assign m00_couplers_to_auto_pc_AWPROT = S_AXI_awprot[2:0];
assign m00_couplers_to_auto_pc_AWQOS = S_AXI_awqos[3:0];
assign m00_couplers_to_auto_pc_AWREGION = S_AXI_awregion[3:0];
assign m00_couplers_to_auto_pc_AWSIZE = S_AXI_awsize[2:0];
assign m00_couplers_to_auto_pc_AWVALID = S_AXI_awvalid;
assign m00_couplers_to_auto_pc_BREADY = S_AXI_bready;
assign m00_couplers_to_auto_pc_RREADY = S_AXI_rready;
assign m00_couplers_to_auto_pc_WDATA = S_AXI_wdata[63:0];
assign m00_couplers_to_auto_pc_WLAST = S_AXI_wlast;
assign m00_couplers_to_auto_pc_WSTRB = S_AXI_wstrb[7:0];
assign m00_couplers_to_auto_pc_WVALID = S_AXI_wvalid;
design_1_auto_pc_0 auto_pc
(.aclk(S_ACLK_1),
.aresetn(S_ARESETN_1),
.m_axi_araddr(auto_pc_to_m00_couplers_ARADDR),
.m_axi_arburst(auto_pc_to_m00_couplers_ARBURST),
.m_axi_arcache(auto_pc_to_m00_couplers_ARCACHE),
.m_axi_arlen(auto_pc_to_m00_couplers_ARLEN),
.m_axi_arlock(auto_pc_to_m00_couplers_ARLOCK),
.m_axi_arprot(auto_pc_to_m00_couplers_ARPROT),
.m_axi_arqos(auto_pc_to_m00_couplers_ARQOS),
.m_axi_arready(auto_pc_to_m00_couplers_ARREADY),
.m_axi_arsize(auto_pc_to_m00_couplers_ARSIZE),
.m_axi_arvalid(auto_pc_to_m00_couplers_ARVALID),
.m_axi_awaddr(auto_pc_to_m00_couplers_AWADDR),
.m_axi_awburst(auto_pc_to_m00_couplers_AWBURST),
.m_axi_awcache(auto_pc_to_m00_couplers_AWCACHE),
.m_axi_awlen(auto_pc_to_m00_couplers_AWLEN),
.m_axi_awlock(auto_pc_to_m00_couplers_AWLOCK),
.m_axi_awprot(auto_pc_to_m00_couplers_AWPROT),
.m_axi_awqos(auto_pc_to_m00_couplers_AWQOS),
.m_axi_awready(auto_pc_to_m00_couplers_AWREADY),
.m_axi_awsize(auto_pc_to_m00_couplers_AWSIZE),
.m_axi_awvalid(auto_pc_to_m00_couplers_AWVALID),
.m_axi_bready(auto_pc_to_m00_couplers_BREADY),
.m_axi_bresp(auto_pc_to_m00_couplers_BRESP),
.m_axi_bvalid(auto_pc_to_m00_couplers_BVALID),
.m_axi_rdata(auto_pc_to_m00_couplers_RDATA),
.m_axi_rlast(auto_pc_to_m00_couplers_RLAST),
.m_axi_rready(auto_pc_to_m00_couplers_RREADY),
.m_axi_rresp(auto_pc_to_m00_couplers_RRESP),
.m_axi_rvalid(auto_pc_to_m00_couplers_RVALID),
.m_axi_wdata(auto_pc_to_m00_couplers_WDATA),
.m_axi_wlast(auto_pc_to_m00_couplers_WLAST),
.m_axi_wready(auto_pc_to_m00_couplers_WREADY),
.m_axi_wstrb(auto_pc_to_m00_couplers_WSTRB),
.m_axi_wvalid(auto_pc_to_m00_couplers_WVALID),
.s_axi_araddr(m00_couplers_to_auto_pc_ARADDR),
.s_axi_arburst(m00_couplers_to_auto_pc_ARBURST),
.s_axi_arcache(m00_couplers_to_auto_pc_ARCACHE),
.s_axi_arlen(m00_couplers_to_auto_pc_ARLEN),
.s_axi_arlock(m00_couplers_to_auto_pc_ARLOCK),
.s_axi_arprot(m00_couplers_to_auto_pc_ARPROT),
.s_axi_arqos(m00_couplers_to_auto_pc_ARQOS),
.s_axi_arready(m00_couplers_to_auto_pc_ARREADY),
.s_axi_arregion(m00_couplers_to_auto_pc_ARREGION),
.s_axi_arsize(m00_couplers_to_auto_pc_ARSIZE),
.s_axi_arvalid(m00_couplers_to_auto_pc_ARVALID),
.s_axi_awaddr(m00_couplers_to_auto_pc_AWADDR),
.s_axi_awburst(m00_couplers_to_auto_pc_AWBURST),
.s_axi_awcache(m00_couplers_to_auto_pc_AWCACHE),
.s_axi_awlen(m00_couplers_to_auto_pc_AWLEN),
.s_axi_awlock(m00_couplers_to_auto_pc_AWLOCK),
.s_axi_awprot(m00_couplers_to_auto_pc_AWPROT),
.s_axi_awqos(m00_couplers_to_auto_pc_AWQOS),
.s_axi_awready(m00_couplers_to_auto_pc_AWREADY),
.s_axi_awregion(m00_couplers_to_auto_pc_AWREGION),
.s_axi_awsize(m00_couplers_to_auto_pc_AWSIZE),
.s_axi_awvalid(m00_couplers_to_auto_pc_AWVALID),
.s_axi_bready(m00_couplers_to_auto_pc_BREADY),
.s_axi_bresp(m00_couplers_to_auto_pc_BRESP),
.s_axi_bvalid(m00_couplers_to_auto_pc_BVALID),
.s_axi_rdata(m00_couplers_to_auto_pc_RDATA),
.s_axi_rlast(m00_couplers_to_auto_pc_RLAST),
.s_axi_rready(m00_couplers_to_auto_pc_RREADY),
.s_axi_rresp(m00_couplers_to_auto_pc_RRESP),
.s_axi_rvalid(m00_couplers_to_auto_pc_RVALID),
.s_axi_wdata(m00_couplers_to_auto_pc_WDATA),
.s_axi_wlast(m00_couplers_to_auto_pc_WLAST),
.s_axi_wready(m00_couplers_to_auto_pc_WREADY),
.s_axi_wstrb(m00_couplers_to_auto_pc_WSTRB),
.s_axi_wvalid(m00_couplers_to_auto_pc_WVALID));
endmodule
module m00_couplers_imp_MBTM83
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arburst,
M_AXI_arcache,
M_AXI_arlen,
M_AXI_arlock,
M_AXI_arprot,
M_AXI_arqos,
M_AXI_arready,
M_AXI_arsize,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awburst,
M_AXI_awcache,
M_AXI_awlen,
M_AXI_awlock,
M_AXI_awprot,
M_AXI_awqos,
M_AXI_awready,
M_AXI_awsize,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rlast,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wlast,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arregion,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awregion,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input M_ARESETN;
output [31:0]M_AXI_araddr;
output [1:0]M_AXI_arburst;
output [3:0]M_AXI_arcache;
output [3:0]M_AXI_arlen;
output [1:0]M_AXI_arlock;
output [2:0]M_AXI_arprot;
output [3:0]M_AXI_arqos;
input M_AXI_arready;
output [2:0]M_AXI_arsize;
output M_AXI_arvalid;
output [31:0]M_AXI_awaddr;
output [1:0]M_AXI_awburst;
output [3:0]M_AXI_awcache;
output [3:0]M_AXI_awlen;
output [1:0]M_AXI_awlock;
output [2:0]M_AXI_awprot;
output [3:0]M_AXI_awqos;
input M_AXI_awready;
output [2:0]M_AXI_awsize;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [63:0]M_AXI_rdata;
input M_AXI_rlast;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [63:0]M_AXI_wdata;
output M_AXI_wlast;
input M_AXI_wready;
output [7:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [7:0]S_AXI_arlen;
input [0:0]S_AXI_arlock;
input [2:0]S_AXI_arprot;
input [3:0]S_AXI_arqos;
output S_AXI_arready;
input [3:0]S_AXI_arregion;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [7:0]S_AXI_awlen;
input [0:0]S_AXI_awlock;
input [2:0]S_AXI_awprot;
input [3:0]S_AXI_awqos;
output S_AXI_awready;
input [3:0]S_AXI_awregion;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [63:0]S_AXI_rdata;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [63:0]S_AXI_wdata;
input S_AXI_wlast;
output S_AXI_wready;
input [7:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire S_ACLK_1;
wire S_ARESETN_1;
wire [31:0]auto_pc_to_m00_couplers_ARADDR;
wire [1:0]auto_pc_to_m00_couplers_ARBURST;
wire [3:0]auto_pc_to_m00_couplers_ARCACHE;
wire [3:0]auto_pc_to_m00_couplers_ARLEN;
wire [1:0]auto_pc_to_m00_couplers_ARLOCK;
wire [2:0]auto_pc_to_m00_couplers_ARPROT;
wire [3:0]auto_pc_to_m00_couplers_ARQOS;
wire auto_pc_to_m00_couplers_ARREADY;
wire [2:0]auto_pc_to_m00_couplers_ARSIZE;
wire auto_pc_to_m00_couplers_ARVALID;
wire [31:0]auto_pc_to_m00_couplers_AWADDR;
wire [1:0]auto_pc_to_m00_couplers_AWBURST;
wire [3:0]auto_pc_to_m00_couplers_AWCACHE;
wire [3:0]auto_pc_to_m00_couplers_AWLEN;
wire [1:0]auto_pc_to_m00_couplers_AWLOCK;
wire [2:0]auto_pc_to_m00_couplers_AWPROT;
wire [3:0]auto_pc_to_m00_couplers_AWQOS;
wire auto_pc_to_m00_couplers_AWREADY;
wire [2:0]auto_pc_to_m00_couplers_AWSIZE;
wire auto_pc_to_m00_couplers_AWVALID;
wire auto_pc_to_m00_couplers_BREADY;
wire [1:0]auto_pc_to_m00_couplers_BRESP;
wire auto_pc_to_m00_couplers_BVALID;
wire [63:0]auto_pc_to_m00_couplers_RDATA;
wire auto_pc_to_m00_couplers_RLAST;
wire auto_pc_to_m00_couplers_RREADY;
wire [1:0]auto_pc_to_m00_couplers_RRESP;
wire auto_pc_to_m00_couplers_RVALID;
wire [63:0]auto_pc_to_m00_couplers_WDATA;
wire auto_pc_to_m00_couplers_WLAST;
wire auto_pc_to_m00_couplers_WREADY;
wire [7:0]auto_pc_to_m00_couplers_WSTRB;
wire auto_pc_to_m00_couplers_WVALID;
wire [31:0]m00_couplers_to_auto_pc_ARADDR;
wire [1:0]m00_couplers_to_auto_pc_ARBURST;
wire [3:0]m00_couplers_to_auto_pc_ARCACHE;
wire [7:0]m00_couplers_to_auto_pc_ARLEN;
wire [0:0]m00_couplers_to_auto_pc_ARLOCK;
wire [2:0]m00_couplers_to_auto_pc_ARPROT;
wire [3:0]m00_couplers_to_auto_pc_ARQOS;
wire m00_couplers_to_auto_pc_ARREADY;
wire [3:0]m00_couplers_to_auto_pc_ARREGION;
wire [2:0]m00_couplers_to_auto_pc_ARSIZE;
wire m00_couplers_to_auto_pc_ARVALID;
wire [31:0]m00_couplers_to_auto_pc_AWADDR;
wire [1:0]m00_couplers_to_auto_pc_AWBURST;
wire [3:0]m00_couplers_to_auto_pc_AWCACHE;
wire [7:0]m00_couplers_to_auto_pc_AWLEN;
wire [0:0]m00_couplers_to_auto_pc_AWLOCK;
wire [2:0]m00_couplers_to_auto_pc_AWPROT;
wire [3:0]m00_couplers_to_auto_pc_AWQOS;
wire m00_couplers_to_auto_pc_AWREADY;
wire [3:0]m00_couplers_to_auto_pc_AWREGION;
wire [2:0]m00_couplers_to_auto_pc_AWSIZE;
wire m00_couplers_to_auto_pc_AWVALID;
wire m00_couplers_to_auto_pc_BREADY;
wire [1:0]m00_couplers_to_auto_pc_BRESP;
wire m00_couplers_to_auto_pc_BVALID;
wire [63:0]m00_couplers_to_auto_pc_RDATA;
wire m00_couplers_to_auto_pc_RLAST;
wire m00_couplers_to_auto_pc_RREADY;
wire [1:0]m00_couplers_to_auto_pc_RRESP;
wire m00_couplers_to_auto_pc_RVALID;
wire [63:0]m00_couplers_to_auto_pc_WDATA;
wire m00_couplers_to_auto_pc_WLAST;
wire m00_couplers_to_auto_pc_WREADY;
wire [7:0]m00_couplers_to_auto_pc_WSTRB;
wire m00_couplers_to_auto_pc_WVALID;
assign M_AXI_araddr[31:0] = auto_pc_to_m00_couplers_ARADDR;
assign M_AXI_arburst[1:0] = auto_pc_to_m00_couplers_ARBURST;
assign M_AXI_arcache[3:0] = auto_pc_to_m00_couplers_ARCACHE;
assign M_AXI_arlen[3:0] = auto_pc_to_m00_couplers_ARLEN;
assign M_AXI_arlock[1:0] = auto_pc_to_m00_couplers_ARLOCK;
assign M_AXI_arprot[2:0] = auto_pc_to_m00_couplers_ARPROT;
assign M_AXI_arqos[3:0] = auto_pc_to_m00_couplers_ARQOS;
assign M_AXI_arsize[2:0] = auto_pc_to_m00_couplers_ARSIZE;
assign M_AXI_arvalid = auto_pc_to_m00_couplers_ARVALID;
assign M_AXI_awaddr[31:0] = auto_pc_to_m00_couplers_AWADDR;
assign M_AXI_awburst[1:0] = auto_pc_to_m00_couplers_AWBURST;
assign M_AXI_awcache[3:0] = auto_pc_to_m00_couplers_AWCACHE;
assign M_AXI_awlen[3:0] = auto_pc_to_m00_couplers_AWLEN;
assign M_AXI_awlock[1:0] = auto_pc_to_m00_couplers_AWLOCK;
assign M_AXI_awprot[2:0] = auto_pc_to_m00_couplers_AWPROT;
assign M_AXI_awqos[3:0] = auto_pc_to_m00_couplers_AWQOS;
assign M_AXI_awsize[2:0] = auto_pc_to_m00_couplers_AWSIZE;
assign M_AXI_awvalid = auto_pc_to_m00_couplers_AWVALID;
assign M_AXI_bready = auto_pc_to_m00_couplers_BREADY;
assign M_AXI_rready = auto_pc_to_m00_couplers_RREADY;
assign M_AXI_wdata[63:0] = auto_pc_to_m00_couplers_WDATA;
assign M_AXI_wlast = auto_pc_to_m00_couplers_WLAST;
assign M_AXI_wstrb[7:0] = auto_pc_to_m00_couplers_WSTRB;
assign M_AXI_wvalid = auto_pc_to_m00_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN;
assign S_AXI_arready = m00_couplers_to_auto_pc_ARREADY;
assign S_AXI_awready = m00_couplers_to_auto_pc_AWREADY;
assign S_AXI_bresp[1:0] = m00_couplers_to_auto_pc_BRESP;
assign S_AXI_bvalid = m00_couplers_to_auto_pc_BVALID;
assign S_AXI_rdata[63:0] = m00_couplers_to_auto_pc_RDATA;
assign S_AXI_rlast = m00_couplers_to_auto_pc_RLAST;
assign S_AXI_rresp[1:0] = m00_couplers_to_auto_pc_RRESP;
assign S_AXI_rvalid = m00_couplers_to_auto_pc_RVALID;
assign S_AXI_wready = m00_couplers_to_auto_pc_WREADY;
assign auto_pc_to_m00_couplers_ARREADY = M_AXI_arready;
assign auto_pc_to_m00_couplers_AWREADY = M_AXI_awready;
assign auto_pc_to_m00_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_pc_to_m00_couplers_BVALID = M_AXI_bvalid;
assign auto_pc_to_m00_couplers_RDATA = M_AXI_rdata[63:0];
assign auto_pc_to_m00_couplers_RLAST = M_AXI_rlast;
assign auto_pc_to_m00_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_pc_to_m00_couplers_RVALID = M_AXI_rvalid;
assign auto_pc_to_m00_couplers_WREADY = M_AXI_wready;
assign m00_couplers_to_auto_pc_ARADDR = S_AXI_araddr[31:0];
assign m00_couplers_to_auto_pc_ARBURST = S_AXI_arburst[1:0];
assign m00_couplers_to_auto_pc_ARCACHE = S_AXI_arcache[3:0];
assign m00_couplers_to_auto_pc_ARLEN = S_AXI_arlen[7:0];
assign m00_couplers_to_auto_pc_ARLOCK = S_AXI_arlock[0];
assign m00_couplers_to_auto_pc_ARPROT = S_AXI_arprot[2:0];
assign m00_couplers_to_auto_pc_ARQOS = S_AXI_arqos[3:0];
assign m00_couplers_to_auto_pc_ARREGION = S_AXI_arregion[3:0];
assign m00_couplers_to_auto_pc_ARSIZE = S_AXI_arsize[2:0];
assign m00_couplers_to_auto_pc_ARVALID = S_AXI_arvalid;
assign m00_couplers_to_auto_pc_AWADDR = S_AXI_awaddr[31:0];
assign m00_couplers_to_auto_pc_AWBURST = S_AXI_awburst[1:0];
assign m00_couplers_to_auto_pc_AWCACHE = S_AXI_awcache[3:0];
assign m00_couplers_to_auto_pc_AWLEN = S_AXI_awlen[7:0];
assign m00_couplers_to_auto_pc_AWLOCK = S_AXI_awlock[0];
assign m00_couplers_to_auto_pc_AWPROT = S_AXI_awprot[2:0];
assign m00_couplers_to_auto_pc_AWQOS = S_AXI_awqos[3:0];
assign m00_couplers_to_auto_pc_AWREGION = S_AXI_awregion[3:0];
assign m00_couplers_to_auto_pc_AWSIZE = S_AXI_awsize[2:0];
assign m00_couplers_to_auto_pc_AWVALID = S_AXI_awvalid;
assign m00_couplers_to_auto_pc_BREADY = S_AXI_bready;
assign m00_couplers_to_auto_pc_RREADY = S_AXI_rready;
assign m00_couplers_to_auto_pc_WDATA = S_AXI_wdata[63:0];
assign m00_couplers_to_auto_pc_WLAST = S_AXI_wlast;
assign m00_couplers_to_auto_pc_WSTRB = S_AXI_wstrb[7:0];
assign m00_couplers_to_auto_pc_WVALID = S_AXI_wvalid;
design_1_auto_pc_2 auto_pc
(.aclk(S_ACLK_1),
.aresetn(S_ARESETN_1),
.m_axi_araddr(auto_pc_to_m00_couplers_ARADDR),
.m_axi_arburst(auto_pc_to_m00_couplers_ARBURST),
.m_axi_arcache(auto_pc_to_m00_couplers_ARCACHE),
.m_axi_arlen(auto_pc_to_m00_couplers_ARLEN),
.m_axi_arlock(auto_pc_to_m00_couplers_ARLOCK),
.m_axi_arprot(auto_pc_to_m00_couplers_ARPROT),
.m_axi_arqos(auto_pc_to_m00_couplers_ARQOS),
.m_axi_arready(auto_pc_to_m00_couplers_ARREADY),
.m_axi_arsize(auto_pc_to_m00_couplers_ARSIZE),
.m_axi_arvalid(auto_pc_to_m00_couplers_ARVALID),
.m_axi_awaddr(auto_pc_to_m00_couplers_AWADDR),
.m_axi_awburst(auto_pc_to_m00_couplers_AWBURST),
.m_axi_awcache(auto_pc_to_m00_couplers_AWCACHE),
.m_axi_awlen(auto_pc_to_m00_couplers_AWLEN),
.m_axi_awlock(auto_pc_to_m00_couplers_AWLOCK),
.m_axi_awprot(auto_pc_to_m00_couplers_AWPROT),
.m_axi_awqos(auto_pc_to_m00_couplers_AWQOS),
.m_axi_awready(auto_pc_to_m00_couplers_AWREADY),
.m_axi_awsize(auto_pc_to_m00_couplers_AWSIZE),
.m_axi_awvalid(auto_pc_to_m00_couplers_AWVALID),
.m_axi_bready(auto_pc_to_m00_couplers_BREADY),
.m_axi_bresp(auto_pc_to_m00_couplers_BRESP),
.m_axi_bvalid(auto_pc_to_m00_couplers_BVALID),
.m_axi_rdata(auto_pc_to_m00_couplers_RDATA),
.m_axi_rlast(auto_pc_to_m00_couplers_RLAST),
.m_axi_rready(auto_pc_to_m00_couplers_RREADY),
.m_axi_rresp(auto_pc_to_m00_couplers_RRESP),
.m_axi_rvalid(auto_pc_to_m00_couplers_RVALID),
.m_axi_wdata(auto_pc_to_m00_couplers_WDATA),
.m_axi_wlast(auto_pc_to_m00_couplers_WLAST),
.m_axi_wready(auto_pc_to_m00_couplers_WREADY),
.m_axi_wstrb(auto_pc_to_m00_couplers_WSTRB),
.m_axi_wvalid(auto_pc_to_m00_couplers_WVALID),
.s_axi_araddr(m00_couplers_to_auto_pc_ARADDR),
.s_axi_arburst(m00_couplers_to_auto_pc_ARBURST),
.s_axi_arcache(m00_couplers_to_auto_pc_ARCACHE),
.s_axi_arlen(m00_couplers_to_auto_pc_ARLEN),
.s_axi_arlock(m00_couplers_to_auto_pc_ARLOCK),
.s_axi_arprot(m00_couplers_to_auto_pc_ARPROT),
.s_axi_arqos(m00_couplers_to_auto_pc_ARQOS),
.s_axi_arready(m00_couplers_to_auto_pc_ARREADY),
.s_axi_arregion(m00_couplers_to_auto_pc_ARREGION),
.s_axi_arsize(m00_couplers_to_auto_pc_ARSIZE),
.s_axi_arvalid(m00_couplers_to_auto_pc_ARVALID),
.s_axi_awaddr(m00_couplers_to_auto_pc_AWADDR),
.s_axi_awburst(m00_couplers_to_auto_pc_AWBURST),
.s_axi_awcache(m00_couplers_to_auto_pc_AWCACHE),
.s_axi_awlen(m00_couplers_to_auto_pc_AWLEN),
.s_axi_awlock(m00_couplers_to_auto_pc_AWLOCK),
.s_axi_awprot(m00_couplers_to_auto_pc_AWPROT),
.s_axi_awqos(m00_couplers_to_auto_pc_AWQOS),
.s_axi_awready(m00_couplers_to_auto_pc_AWREADY),
.s_axi_awregion(m00_couplers_to_auto_pc_AWREGION),
.s_axi_awsize(m00_couplers_to_auto_pc_AWSIZE),
.s_axi_awvalid(m00_couplers_to_auto_pc_AWVALID),
.s_axi_bready(m00_couplers_to_auto_pc_BREADY),
.s_axi_bresp(m00_couplers_to_auto_pc_BRESP),
.s_axi_bvalid(m00_couplers_to_auto_pc_BVALID),
.s_axi_rdata(m00_couplers_to_auto_pc_RDATA),
.s_axi_rlast(m00_couplers_to_auto_pc_RLAST),
.s_axi_rready(m00_couplers_to_auto_pc_RREADY),
.s_axi_rresp(m00_couplers_to_auto_pc_RRESP),
.s_axi_rvalid(m00_couplers_to_auto_pc_RVALID),
.s_axi_wdata(m00_couplers_to_auto_pc_WDATA),
.s_axi_wlast(m00_couplers_to_auto_pc_WLAST),
.s_axi_wready(m00_couplers_to_auto_pc_WREADY),
.s_axi_wstrb(m00_couplers_to_auto_pc_WSTRB),
.s_axi_wvalid(m00_couplers_to_auto_pc_WVALID));
endmodule
module m00_couplers_imp_OBU1DD
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arready,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awready,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wready,
S_AXI_wvalid);
input M_ACLK;
input M_ARESETN;
output [31:0]M_AXI_araddr;
input [0:0]M_AXI_arready;
output [0:0]M_AXI_arvalid;
output [31:0]M_AXI_awaddr;
input [0:0]M_AXI_awready;
output [0:0]M_AXI_awvalid;
output [0:0]M_AXI_bready;
input [1:0]M_AXI_bresp;
input [0:0]M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output [0:0]M_AXI_rready;
input [1:0]M_AXI_rresp;
input [0:0]M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input [0:0]M_AXI_wready;
output [0:0]M_AXI_wvalid;
input S_ACLK;
input S_ARESETN;
input [31:0]S_AXI_araddr;
output [0:0]S_AXI_arready;
input [0:0]S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
output [0:0]S_AXI_awready;
input [0:0]S_AXI_awvalid;
input [0:0]S_AXI_bready;
output [1:0]S_AXI_bresp;
output [0:0]S_AXI_bvalid;
output [31:0]S_AXI_rdata;
input [0:0]S_AXI_rready;
output [1:0]S_AXI_rresp;
output [0:0]S_AXI_rvalid;
input [31:0]S_AXI_wdata;
output [0:0]S_AXI_wready;
input [0:0]S_AXI_wvalid;
wire [31:0]m00_couplers_to_m00_couplers_ARADDR;
wire [0:0]m00_couplers_to_m00_couplers_ARREADY;
wire [0:0]m00_couplers_to_m00_couplers_ARVALID;
wire [31:0]m00_couplers_to_m00_couplers_AWADDR;
wire [0:0]m00_couplers_to_m00_couplers_AWREADY;
wire [0:0]m00_couplers_to_m00_couplers_AWVALID;
wire [0:0]m00_couplers_to_m00_couplers_BREADY;
wire [1:0]m00_couplers_to_m00_couplers_BRESP;
wire [0:0]m00_couplers_to_m00_couplers_BVALID;
wire [31:0]m00_couplers_to_m00_couplers_RDATA;
wire [0:0]m00_couplers_to_m00_couplers_RREADY;
wire [1:0]m00_couplers_to_m00_couplers_RRESP;
wire [0:0]m00_couplers_to_m00_couplers_RVALID;
wire [31:0]m00_couplers_to_m00_couplers_WDATA;
wire [0:0]m00_couplers_to_m00_couplers_WREADY;
wire [0:0]m00_couplers_to_m00_couplers_WVALID;
assign M_AXI_araddr[31:0] = m00_couplers_to_m00_couplers_ARADDR;
assign M_AXI_arvalid[0] = m00_couplers_to_m00_couplers_ARVALID;
assign M_AXI_awaddr[31:0] = m00_couplers_to_m00_couplers_AWADDR;
assign M_AXI_awvalid[0] = m00_couplers_to_m00_couplers_AWVALID;
assign M_AXI_bready[0] = m00_couplers_to_m00_couplers_BREADY;
assign M_AXI_rready[0] = m00_couplers_to_m00_couplers_RREADY;
assign M_AXI_wdata[31:0] = m00_couplers_to_m00_couplers_WDATA;
assign M_AXI_wvalid[0] = m00_couplers_to_m00_couplers_WVALID;
assign S_AXI_arready[0] = m00_couplers_to_m00_couplers_ARREADY;
assign S_AXI_awready[0] = m00_couplers_to_m00_couplers_AWREADY;
assign S_AXI_bresp[1:0] = m00_couplers_to_m00_couplers_BRESP;
assign S_AXI_bvalid[0] = m00_couplers_to_m00_couplers_BVALID;
assign S_AXI_rdata[31:0] = m00_couplers_to_m00_couplers_RDATA;
assign S_AXI_rresp[1:0] = m00_couplers_to_m00_couplers_RRESP;
assign S_AXI_rvalid[0] = m00_couplers_to_m00_couplers_RVALID;
assign S_AXI_wready[0] = m00_couplers_to_m00_couplers_WREADY;
assign m00_couplers_to_m00_couplers_ARADDR = S_AXI_araddr[31:0];
assign m00_couplers_to_m00_couplers_ARREADY = M_AXI_arready[0];
assign m00_couplers_to_m00_couplers_ARVALID = S_AXI_arvalid[0];
assign m00_couplers_to_m00_couplers_AWADDR = S_AXI_awaddr[31:0];
assign m00_couplers_to_m00_couplers_AWREADY = M_AXI_awready[0];
assign m00_couplers_to_m00_couplers_AWVALID = S_AXI_awvalid[0];
assign m00_couplers_to_m00_couplers_BREADY = S_AXI_bready[0];
assign m00_couplers_to_m00_couplers_BRESP = M_AXI_bresp[1:0];
assign m00_couplers_to_m00_couplers_BVALID = M_AXI_bvalid[0];
assign m00_couplers_to_m00_couplers_RDATA = M_AXI_rdata[31:0];
assign m00_couplers_to_m00_couplers_RREADY = S_AXI_rready[0];
assign m00_couplers_to_m00_couplers_RRESP = M_AXI_rresp[1:0];
assign m00_couplers_to_m00_couplers_RVALID = M_AXI_rvalid[0];
assign m00_couplers_to_m00_couplers_WDATA = S_AXI_wdata[31:0];
assign m00_couplers_to_m00_couplers_WREADY = M_AXI_wready[0];
assign m00_couplers_to_m00_couplers_WVALID = S_AXI_wvalid[0];
endmodule
module m01_couplers_imp_1FBREZ4
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arready,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awready,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input M_ARESETN;
output [31:0]M_AXI_araddr;
input M_AXI_arready;
output M_AXI_arvalid;
output [31:0]M_AXI_awaddr;
input M_AXI_awready;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input S_ARESETN;
input [31:0]S_AXI_araddr;
output S_AXI_arready;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
output S_AXI_awready;
input S_AXI_awvalid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire [31:0]m01_couplers_to_m01_couplers_ARADDR;
wire m01_couplers_to_m01_couplers_ARREADY;
wire m01_couplers_to_m01_couplers_ARVALID;
wire [31:0]m01_couplers_to_m01_couplers_AWADDR;
wire m01_couplers_to_m01_couplers_AWREADY;
wire m01_couplers_to_m01_couplers_AWVALID;
wire m01_couplers_to_m01_couplers_BREADY;
wire [1:0]m01_couplers_to_m01_couplers_BRESP;
wire m01_couplers_to_m01_couplers_BVALID;
wire [31:0]m01_couplers_to_m01_couplers_RDATA;
wire m01_couplers_to_m01_couplers_RREADY;
wire [1:0]m01_couplers_to_m01_couplers_RRESP;
wire m01_couplers_to_m01_couplers_RVALID;
wire [31:0]m01_couplers_to_m01_couplers_WDATA;
wire m01_couplers_to_m01_couplers_WREADY;
wire [3:0]m01_couplers_to_m01_couplers_WSTRB;
wire m01_couplers_to_m01_couplers_WVALID;
assign M_AXI_araddr[31:0] = m01_couplers_to_m01_couplers_ARADDR;
assign M_AXI_arvalid = m01_couplers_to_m01_couplers_ARVALID;
assign M_AXI_awaddr[31:0] = m01_couplers_to_m01_couplers_AWADDR;
assign M_AXI_awvalid = m01_couplers_to_m01_couplers_AWVALID;
assign M_AXI_bready = m01_couplers_to_m01_couplers_BREADY;
assign M_AXI_rready = m01_couplers_to_m01_couplers_RREADY;
assign M_AXI_wdata[31:0] = m01_couplers_to_m01_couplers_WDATA;
assign M_AXI_wstrb[3:0] = m01_couplers_to_m01_couplers_WSTRB;
assign M_AXI_wvalid = m01_couplers_to_m01_couplers_WVALID;
assign S_AXI_arready = m01_couplers_to_m01_couplers_ARREADY;
assign S_AXI_awready = m01_couplers_to_m01_couplers_AWREADY;
assign S_AXI_bresp[1:0] = m01_couplers_to_m01_couplers_BRESP;
assign S_AXI_bvalid = m01_couplers_to_m01_couplers_BVALID;
assign S_AXI_rdata[31:0] = m01_couplers_to_m01_couplers_RDATA;
assign S_AXI_rresp[1:0] = m01_couplers_to_m01_couplers_RRESP;
assign S_AXI_rvalid = m01_couplers_to_m01_couplers_RVALID;
assign S_AXI_wready = m01_couplers_to_m01_couplers_WREADY;
assign m01_couplers_to_m01_couplers_ARADDR = S_AXI_araddr[31:0];
assign m01_couplers_to_m01_couplers_ARREADY = M_AXI_arready;
assign m01_couplers_to_m01_couplers_ARVALID = S_AXI_arvalid;
assign m01_couplers_to_m01_couplers_AWADDR = S_AXI_awaddr[31:0];
assign m01_couplers_to_m01_couplers_AWREADY = M_AXI_awready;
assign m01_couplers_to_m01_couplers_AWVALID = S_AXI_awvalid;
assign m01_couplers_to_m01_couplers_BREADY = S_AXI_bready;
assign m01_couplers_to_m01_couplers_BRESP = M_AXI_bresp[1:0];
assign m01_couplers_to_m01_couplers_BVALID = M_AXI_bvalid;
assign m01_couplers_to_m01_couplers_RDATA = M_AXI_rdata[31:0];
assign m01_couplers_to_m01_couplers_RREADY = S_AXI_rready;
assign m01_couplers_to_m01_couplers_RRESP = M_AXI_rresp[1:0];
assign m01_couplers_to_m01_couplers_RVALID = M_AXI_rvalid;
assign m01_couplers_to_m01_couplers_WDATA = S_AXI_wdata[31:0];
assign m01_couplers_to_m01_couplers_WREADY = M_AXI_wready;
assign m01_couplers_to_m01_couplers_WSTRB = S_AXI_wstrb[3:0];
assign m01_couplers_to_m01_couplers_WVALID = S_AXI_wvalid;
endmodule
module m01_couplers_imp_1H1JSWY
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arburst,
M_AXI_arcache,
M_AXI_arlen,
M_AXI_arlock,
M_AXI_arprot,
M_AXI_arready,
M_AXI_arsize,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awburst,
M_AXI_awcache,
M_AXI_awlen,
M_AXI_awlock,
M_AXI_awprot,
M_AXI_awready,
M_AXI_awsize,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rlast,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wlast,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arregion,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awregion,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input M_ARESETN;
output [12:0]M_AXI_araddr;
output [1:0]M_AXI_arburst;
output [3:0]M_AXI_arcache;
output [7:0]M_AXI_arlen;
output [0:0]M_AXI_arlock;
output [2:0]M_AXI_arprot;
input M_AXI_arready;
output [2:0]M_AXI_arsize;
output M_AXI_arvalid;
output [12:0]M_AXI_awaddr;
output [1:0]M_AXI_awburst;
output [3:0]M_AXI_awcache;
output [7:0]M_AXI_awlen;
output [0:0]M_AXI_awlock;
output [2:0]M_AXI_awprot;
input M_AXI_awready;
output [2:0]M_AXI_awsize;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
input M_AXI_rlast;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
output M_AXI_wlast;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [7:0]S_AXI_arlen;
input [0:0]S_AXI_arlock;
input [2:0]S_AXI_arprot;
input [3:0]S_AXI_arqos;
output S_AXI_arready;
input [3:0]S_AXI_arregion;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [7:0]S_AXI_awlen;
input [0:0]S_AXI_awlock;
input [2:0]S_AXI_awprot;
input [3:0]S_AXI_awqos;
output S_AXI_awready;
input [3:0]S_AXI_awregion;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [63:0]S_AXI_rdata;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [63:0]S_AXI_wdata;
input S_AXI_wlast;
output S_AXI_wready;
input [7:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire S_ACLK_1;
wire S_ARESETN_1;
wire [12:0]auto_ds_to_m01_couplers_ARADDR;
wire [1:0]auto_ds_to_m01_couplers_ARBURST;
wire [3:0]auto_ds_to_m01_couplers_ARCACHE;
wire [7:0]auto_ds_to_m01_couplers_ARLEN;
wire [0:0]auto_ds_to_m01_couplers_ARLOCK;
wire [2:0]auto_ds_to_m01_couplers_ARPROT;
wire auto_ds_to_m01_couplers_ARREADY;
wire [2:0]auto_ds_to_m01_couplers_ARSIZE;
wire auto_ds_to_m01_couplers_ARVALID;
wire [12:0]auto_ds_to_m01_couplers_AWADDR;
wire [1:0]auto_ds_to_m01_couplers_AWBURST;
wire [3:0]auto_ds_to_m01_couplers_AWCACHE;
wire [7:0]auto_ds_to_m01_couplers_AWLEN;
wire [0:0]auto_ds_to_m01_couplers_AWLOCK;
wire [2:0]auto_ds_to_m01_couplers_AWPROT;
wire auto_ds_to_m01_couplers_AWREADY;
wire [2:0]auto_ds_to_m01_couplers_AWSIZE;
wire auto_ds_to_m01_couplers_AWVALID;
wire auto_ds_to_m01_couplers_BREADY;
wire [1:0]auto_ds_to_m01_couplers_BRESP;
wire auto_ds_to_m01_couplers_BVALID;
wire [31:0]auto_ds_to_m01_couplers_RDATA;
wire auto_ds_to_m01_couplers_RLAST;
wire auto_ds_to_m01_couplers_RREADY;
wire [1:0]auto_ds_to_m01_couplers_RRESP;
wire auto_ds_to_m01_couplers_RVALID;
wire [31:0]auto_ds_to_m01_couplers_WDATA;
wire auto_ds_to_m01_couplers_WLAST;
wire auto_ds_to_m01_couplers_WREADY;
wire [3:0]auto_ds_to_m01_couplers_WSTRB;
wire auto_ds_to_m01_couplers_WVALID;
wire [31:0]m01_couplers_to_auto_ds_ARADDR;
wire [1:0]m01_couplers_to_auto_ds_ARBURST;
wire [3:0]m01_couplers_to_auto_ds_ARCACHE;
wire [7:0]m01_couplers_to_auto_ds_ARLEN;
wire [0:0]m01_couplers_to_auto_ds_ARLOCK;
wire [2:0]m01_couplers_to_auto_ds_ARPROT;
wire [3:0]m01_couplers_to_auto_ds_ARQOS;
wire m01_couplers_to_auto_ds_ARREADY;
wire [3:0]m01_couplers_to_auto_ds_ARREGION;
wire [2:0]m01_couplers_to_auto_ds_ARSIZE;
wire m01_couplers_to_auto_ds_ARVALID;
wire [31:0]m01_couplers_to_auto_ds_AWADDR;
wire [1:0]m01_couplers_to_auto_ds_AWBURST;
wire [3:0]m01_couplers_to_auto_ds_AWCACHE;
wire [7:0]m01_couplers_to_auto_ds_AWLEN;
wire [0:0]m01_couplers_to_auto_ds_AWLOCK;
wire [2:0]m01_couplers_to_auto_ds_AWPROT;
wire [3:0]m01_couplers_to_auto_ds_AWQOS;
wire m01_couplers_to_auto_ds_AWREADY;
wire [3:0]m01_couplers_to_auto_ds_AWREGION;
wire [2:0]m01_couplers_to_auto_ds_AWSIZE;
wire m01_couplers_to_auto_ds_AWVALID;
wire m01_couplers_to_auto_ds_BREADY;
wire [1:0]m01_couplers_to_auto_ds_BRESP;
wire m01_couplers_to_auto_ds_BVALID;
wire [63:0]m01_couplers_to_auto_ds_RDATA;
wire m01_couplers_to_auto_ds_RLAST;
wire m01_couplers_to_auto_ds_RREADY;
wire [1:0]m01_couplers_to_auto_ds_RRESP;
wire m01_couplers_to_auto_ds_RVALID;
wire [63:0]m01_couplers_to_auto_ds_WDATA;
wire m01_couplers_to_auto_ds_WLAST;
wire m01_couplers_to_auto_ds_WREADY;
wire [7:0]m01_couplers_to_auto_ds_WSTRB;
wire m01_couplers_to_auto_ds_WVALID;
assign M_AXI_araddr[12:0] = auto_ds_to_m01_couplers_ARADDR;
assign M_AXI_arburst[1:0] = auto_ds_to_m01_couplers_ARBURST;
assign M_AXI_arcache[3:0] = auto_ds_to_m01_couplers_ARCACHE;
assign M_AXI_arlen[7:0] = auto_ds_to_m01_couplers_ARLEN;
assign M_AXI_arlock[0] = auto_ds_to_m01_couplers_ARLOCK;
assign M_AXI_arprot[2:0] = auto_ds_to_m01_couplers_ARPROT;
assign M_AXI_arsize[2:0] = auto_ds_to_m01_couplers_ARSIZE;
assign M_AXI_arvalid = auto_ds_to_m01_couplers_ARVALID;
assign M_AXI_awaddr[12:0] = auto_ds_to_m01_couplers_AWADDR;
assign M_AXI_awburst[1:0] = auto_ds_to_m01_couplers_AWBURST;
assign M_AXI_awcache[3:0] = auto_ds_to_m01_couplers_AWCACHE;
assign M_AXI_awlen[7:0] = auto_ds_to_m01_couplers_AWLEN;
assign M_AXI_awlock[0] = auto_ds_to_m01_couplers_AWLOCK;
assign M_AXI_awprot[2:0] = auto_ds_to_m01_couplers_AWPROT;
assign M_AXI_awsize[2:0] = auto_ds_to_m01_couplers_AWSIZE;
assign M_AXI_awvalid = auto_ds_to_m01_couplers_AWVALID;
assign M_AXI_bready = auto_ds_to_m01_couplers_BREADY;
assign M_AXI_rready = auto_ds_to_m01_couplers_RREADY;
assign M_AXI_wdata[31:0] = auto_ds_to_m01_couplers_WDATA;
assign M_AXI_wlast = auto_ds_to_m01_couplers_WLAST;
assign M_AXI_wstrb[3:0] = auto_ds_to_m01_couplers_WSTRB;
assign M_AXI_wvalid = auto_ds_to_m01_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN;
assign S_AXI_arready = m01_couplers_to_auto_ds_ARREADY;
assign S_AXI_awready = m01_couplers_to_auto_ds_AWREADY;
assign S_AXI_bresp[1:0] = m01_couplers_to_auto_ds_BRESP;
assign S_AXI_bvalid = m01_couplers_to_auto_ds_BVALID;
assign S_AXI_rdata[63:0] = m01_couplers_to_auto_ds_RDATA;
assign S_AXI_rlast = m01_couplers_to_auto_ds_RLAST;
assign S_AXI_rresp[1:0] = m01_couplers_to_auto_ds_RRESP;
assign S_AXI_rvalid = m01_couplers_to_auto_ds_RVALID;
assign S_AXI_wready = m01_couplers_to_auto_ds_WREADY;
assign auto_ds_to_m01_couplers_ARREADY = M_AXI_arready;
assign auto_ds_to_m01_couplers_AWREADY = M_AXI_awready;
assign auto_ds_to_m01_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_ds_to_m01_couplers_BVALID = M_AXI_bvalid;
assign auto_ds_to_m01_couplers_RDATA = M_AXI_rdata[31:0];
assign auto_ds_to_m01_couplers_RLAST = M_AXI_rlast;
assign auto_ds_to_m01_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_ds_to_m01_couplers_RVALID = M_AXI_rvalid;
assign auto_ds_to_m01_couplers_WREADY = M_AXI_wready;
assign m01_couplers_to_auto_ds_ARADDR = S_AXI_araddr[31:0];
assign m01_couplers_to_auto_ds_ARBURST = S_AXI_arburst[1:0];
assign m01_couplers_to_auto_ds_ARCACHE = S_AXI_arcache[3:0];
assign m01_couplers_to_auto_ds_ARLEN = S_AXI_arlen[7:0];
assign m01_couplers_to_auto_ds_ARLOCK = S_AXI_arlock[0];
assign m01_couplers_to_auto_ds_ARPROT = S_AXI_arprot[2:0];
assign m01_couplers_to_auto_ds_ARQOS = S_AXI_arqos[3:0];
assign m01_couplers_to_auto_ds_ARREGION = S_AXI_arregion[3:0];
assign m01_couplers_to_auto_ds_ARSIZE = S_AXI_arsize[2:0];
assign m01_couplers_to_auto_ds_ARVALID = S_AXI_arvalid;
assign m01_couplers_to_auto_ds_AWADDR = S_AXI_awaddr[31:0];
assign m01_couplers_to_auto_ds_AWBURST = S_AXI_awburst[1:0];
assign m01_couplers_to_auto_ds_AWCACHE = S_AXI_awcache[3:0];
assign m01_couplers_to_auto_ds_AWLEN = S_AXI_awlen[7:0];
assign m01_couplers_to_auto_ds_AWLOCK = S_AXI_awlock[0];
assign m01_couplers_to_auto_ds_AWPROT = S_AXI_awprot[2:0];
assign m01_couplers_to_auto_ds_AWQOS = S_AXI_awqos[3:0];
assign m01_couplers_to_auto_ds_AWREGION = S_AXI_awregion[3:0];
assign m01_couplers_to_auto_ds_AWSIZE = S_AXI_awsize[2:0];
assign m01_couplers_to_auto_ds_AWVALID = S_AXI_awvalid;
assign m01_couplers_to_auto_ds_BREADY = S_AXI_bready;
assign m01_couplers_to_auto_ds_RREADY = S_AXI_rready;
assign m01_couplers_to_auto_ds_WDATA = S_AXI_wdata[63:0];
assign m01_couplers_to_auto_ds_WLAST = S_AXI_wlast;
assign m01_couplers_to_auto_ds_WSTRB = S_AXI_wstrb[7:0];
assign m01_couplers_to_auto_ds_WVALID = S_AXI_wvalid;
design_1_auto_ds_2 auto_ds
(.m_axi_araddr(auto_ds_to_m01_couplers_ARADDR),
.m_axi_arburst(auto_ds_to_m01_couplers_ARBURST),
.m_axi_arcache(auto_ds_to_m01_couplers_ARCACHE),
.m_axi_arlen(auto_ds_to_m01_couplers_ARLEN),
.m_axi_arlock(auto_ds_to_m01_couplers_ARLOCK),
.m_axi_arprot(auto_ds_to_m01_couplers_ARPROT),
.m_axi_arready(auto_ds_to_m01_couplers_ARREADY),
.m_axi_arsize(auto_ds_to_m01_couplers_ARSIZE),
.m_axi_arvalid(auto_ds_to_m01_couplers_ARVALID),
.m_axi_awaddr(auto_ds_to_m01_couplers_AWADDR),
.m_axi_awburst(auto_ds_to_m01_couplers_AWBURST),
.m_axi_awcache(auto_ds_to_m01_couplers_AWCACHE),
.m_axi_awlen(auto_ds_to_m01_couplers_AWLEN),
.m_axi_awlock(auto_ds_to_m01_couplers_AWLOCK),
.m_axi_awprot(auto_ds_to_m01_couplers_AWPROT),
.m_axi_awready(auto_ds_to_m01_couplers_AWREADY),
.m_axi_awsize(auto_ds_to_m01_couplers_AWSIZE),
.m_axi_awvalid(auto_ds_to_m01_couplers_AWVALID),
.m_axi_bready(auto_ds_to_m01_couplers_BREADY),
.m_axi_bresp(auto_ds_to_m01_couplers_BRESP),
.m_axi_bvalid(auto_ds_to_m01_couplers_BVALID),
.m_axi_rdata(auto_ds_to_m01_couplers_RDATA),
.m_axi_rlast(auto_ds_to_m01_couplers_RLAST),
.m_axi_rready(auto_ds_to_m01_couplers_RREADY),
.m_axi_rresp(auto_ds_to_m01_couplers_RRESP),
.m_axi_rvalid(auto_ds_to_m01_couplers_RVALID),
.m_axi_wdata(auto_ds_to_m01_couplers_WDATA),
.m_axi_wlast(auto_ds_to_m01_couplers_WLAST),
.m_axi_wready(auto_ds_to_m01_couplers_WREADY),
.m_axi_wstrb(auto_ds_to_m01_couplers_WSTRB),
.m_axi_wvalid(auto_ds_to_m01_couplers_WVALID),
.s_axi_aclk(S_ACLK_1),
.s_axi_araddr(m01_couplers_to_auto_ds_ARADDR[12:0]),
.s_axi_arburst(m01_couplers_to_auto_ds_ARBURST),
.s_axi_arcache(m01_couplers_to_auto_ds_ARCACHE),
.s_axi_aresetn(S_ARESETN_1),
.s_axi_arlen(m01_couplers_to_auto_ds_ARLEN),
.s_axi_arlock(m01_couplers_to_auto_ds_ARLOCK),
.s_axi_arprot(m01_couplers_to_auto_ds_ARPROT),
.s_axi_arqos(m01_couplers_to_auto_ds_ARQOS),
.s_axi_arready(m01_couplers_to_auto_ds_ARREADY),
.s_axi_arregion(m01_couplers_to_auto_ds_ARREGION),
.s_axi_arsize(m01_couplers_to_auto_ds_ARSIZE),
.s_axi_arvalid(m01_couplers_to_auto_ds_ARVALID),
.s_axi_awaddr(m01_couplers_to_auto_ds_AWADDR[12:0]),
.s_axi_awburst(m01_couplers_to_auto_ds_AWBURST),
.s_axi_awcache(m01_couplers_to_auto_ds_AWCACHE),
.s_axi_awlen(m01_couplers_to_auto_ds_AWLEN),
.s_axi_awlock(m01_couplers_to_auto_ds_AWLOCK),
.s_axi_awprot(m01_couplers_to_auto_ds_AWPROT),
.s_axi_awqos(m01_couplers_to_auto_ds_AWQOS),
.s_axi_awready(m01_couplers_to_auto_ds_AWREADY),
.s_axi_awregion(m01_couplers_to_auto_ds_AWREGION),
.s_axi_awsize(m01_couplers_to_auto_ds_AWSIZE),
.s_axi_awvalid(m01_couplers_to_auto_ds_AWVALID),
.s_axi_bready(m01_couplers_to_auto_ds_BREADY),
.s_axi_bresp(m01_couplers_to_auto_ds_BRESP),
.s_axi_bvalid(m01_couplers_to_auto_ds_BVALID),
.s_axi_rdata(m01_couplers_to_auto_ds_RDATA),
.s_axi_rlast(m01_couplers_to_auto_ds_RLAST),
.s_axi_rready(m01_couplers_to_auto_ds_RREADY),
.s_axi_rresp(m01_couplers_to_auto_ds_RRESP),
.s_axi_rvalid(m01_couplers_to_auto_ds_RVALID),
.s_axi_wdata(m01_couplers_to_auto_ds_WDATA),
.s_axi_wlast(m01_couplers_to_auto_ds_WLAST),
.s_axi_wready(m01_couplers_to_auto_ds_WREADY),
.s_axi_wstrb(m01_couplers_to_auto_ds_WSTRB),
.s_axi_wvalid(m01_couplers_to_auto_ds_WVALID));
endmodule
module m01_couplers_imp_9HVA0G
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arburst,
M_AXI_arcache,
M_AXI_arlen,
M_AXI_arlock,
M_AXI_arprot,
M_AXI_arready,
M_AXI_arsize,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awburst,
M_AXI_awcache,
M_AXI_awlen,
M_AXI_awlock,
M_AXI_awprot,
M_AXI_awready,
M_AXI_awsize,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rlast,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wlast,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arregion,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awregion,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input M_ARESETN;
output [12:0]M_AXI_araddr;
output [1:0]M_AXI_arburst;
output [3:0]M_AXI_arcache;
output [7:0]M_AXI_arlen;
output [0:0]M_AXI_arlock;
output [2:0]M_AXI_arprot;
input M_AXI_arready;
output [2:0]M_AXI_arsize;
output M_AXI_arvalid;
output [12:0]M_AXI_awaddr;
output [1:0]M_AXI_awburst;
output [3:0]M_AXI_awcache;
output [7:0]M_AXI_awlen;
output [0:0]M_AXI_awlock;
output [2:0]M_AXI_awprot;
input M_AXI_awready;
output [2:0]M_AXI_awsize;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
input M_AXI_rlast;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
output M_AXI_wlast;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [7:0]S_AXI_arlen;
input [0:0]S_AXI_arlock;
input [2:0]S_AXI_arprot;
input [3:0]S_AXI_arqos;
output S_AXI_arready;
input [3:0]S_AXI_arregion;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [7:0]S_AXI_awlen;
input [0:0]S_AXI_awlock;
input [2:0]S_AXI_awprot;
input [3:0]S_AXI_awqos;
output S_AXI_awready;
input [3:0]S_AXI_awregion;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [63:0]S_AXI_rdata;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [63:0]S_AXI_wdata;
input S_AXI_wlast;
output S_AXI_wready;
input [7:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire S_ACLK_1;
wire S_ARESETN_1;
wire [12:0]auto_ds_to_m01_couplers_ARADDR;
wire [1:0]auto_ds_to_m01_couplers_ARBURST;
wire [3:0]auto_ds_to_m01_couplers_ARCACHE;
wire [7:0]auto_ds_to_m01_couplers_ARLEN;
wire [0:0]auto_ds_to_m01_couplers_ARLOCK;
wire [2:0]auto_ds_to_m01_couplers_ARPROT;
wire auto_ds_to_m01_couplers_ARREADY;
wire [2:0]auto_ds_to_m01_couplers_ARSIZE;
wire auto_ds_to_m01_couplers_ARVALID;
wire [12:0]auto_ds_to_m01_couplers_AWADDR;
wire [1:0]auto_ds_to_m01_couplers_AWBURST;
wire [3:0]auto_ds_to_m01_couplers_AWCACHE;
wire [7:0]auto_ds_to_m01_couplers_AWLEN;
wire [0:0]auto_ds_to_m01_couplers_AWLOCK;
wire [2:0]auto_ds_to_m01_couplers_AWPROT;
wire auto_ds_to_m01_couplers_AWREADY;
wire [2:0]auto_ds_to_m01_couplers_AWSIZE;
wire auto_ds_to_m01_couplers_AWVALID;
wire auto_ds_to_m01_couplers_BREADY;
wire [1:0]auto_ds_to_m01_couplers_BRESP;
wire auto_ds_to_m01_couplers_BVALID;
wire [31:0]auto_ds_to_m01_couplers_RDATA;
wire auto_ds_to_m01_couplers_RLAST;
wire auto_ds_to_m01_couplers_RREADY;
wire [1:0]auto_ds_to_m01_couplers_RRESP;
wire auto_ds_to_m01_couplers_RVALID;
wire [31:0]auto_ds_to_m01_couplers_WDATA;
wire auto_ds_to_m01_couplers_WLAST;
wire auto_ds_to_m01_couplers_WREADY;
wire [3:0]auto_ds_to_m01_couplers_WSTRB;
wire auto_ds_to_m01_couplers_WVALID;
wire [31:0]m01_couplers_to_auto_ds_ARADDR;
wire [1:0]m01_couplers_to_auto_ds_ARBURST;
wire [3:0]m01_couplers_to_auto_ds_ARCACHE;
wire [7:0]m01_couplers_to_auto_ds_ARLEN;
wire [0:0]m01_couplers_to_auto_ds_ARLOCK;
wire [2:0]m01_couplers_to_auto_ds_ARPROT;
wire [3:0]m01_couplers_to_auto_ds_ARQOS;
wire m01_couplers_to_auto_ds_ARREADY;
wire [3:0]m01_couplers_to_auto_ds_ARREGION;
wire [2:0]m01_couplers_to_auto_ds_ARSIZE;
wire m01_couplers_to_auto_ds_ARVALID;
wire [31:0]m01_couplers_to_auto_ds_AWADDR;
wire [1:0]m01_couplers_to_auto_ds_AWBURST;
wire [3:0]m01_couplers_to_auto_ds_AWCACHE;
wire [7:0]m01_couplers_to_auto_ds_AWLEN;
wire [0:0]m01_couplers_to_auto_ds_AWLOCK;
wire [2:0]m01_couplers_to_auto_ds_AWPROT;
wire [3:0]m01_couplers_to_auto_ds_AWQOS;
wire m01_couplers_to_auto_ds_AWREADY;
wire [3:0]m01_couplers_to_auto_ds_AWREGION;
wire [2:0]m01_couplers_to_auto_ds_AWSIZE;
wire m01_couplers_to_auto_ds_AWVALID;
wire m01_couplers_to_auto_ds_BREADY;
wire [1:0]m01_couplers_to_auto_ds_BRESP;
wire m01_couplers_to_auto_ds_BVALID;
wire [63:0]m01_couplers_to_auto_ds_RDATA;
wire m01_couplers_to_auto_ds_RLAST;
wire m01_couplers_to_auto_ds_RREADY;
wire [1:0]m01_couplers_to_auto_ds_RRESP;
wire m01_couplers_to_auto_ds_RVALID;
wire [63:0]m01_couplers_to_auto_ds_WDATA;
wire m01_couplers_to_auto_ds_WLAST;
wire m01_couplers_to_auto_ds_WREADY;
wire [7:0]m01_couplers_to_auto_ds_WSTRB;
wire m01_couplers_to_auto_ds_WVALID;
assign M_AXI_araddr[12:0] = auto_ds_to_m01_couplers_ARADDR;
assign M_AXI_arburst[1:0] = auto_ds_to_m01_couplers_ARBURST;
assign M_AXI_arcache[3:0] = auto_ds_to_m01_couplers_ARCACHE;
assign M_AXI_arlen[7:0] = auto_ds_to_m01_couplers_ARLEN;
assign M_AXI_arlock[0] = auto_ds_to_m01_couplers_ARLOCK;
assign M_AXI_arprot[2:0] = auto_ds_to_m01_couplers_ARPROT;
assign M_AXI_arsize[2:0] = auto_ds_to_m01_couplers_ARSIZE;
assign M_AXI_arvalid = auto_ds_to_m01_couplers_ARVALID;
assign M_AXI_awaddr[12:0] = auto_ds_to_m01_couplers_AWADDR;
assign M_AXI_awburst[1:0] = auto_ds_to_m01_couplers_AWBURST;
assign M_AXI_awcache[3:0] = auto_ds_to_m01_couplers_AWCACHE;
assign M_AXI_awlen[7:0] = auto_ds_to_m01_couplers_AWLEN;
assign M_AXI_awlock[0] = auto_ds_to_m01_couplers_AWLOCK;
assign M_AXI_awprot[2:0] = auto_ds_to_m01_couplers_AWPROT;
assign M_AXI_awsize[2:0] = auto_ds_to_m01_couplers_AWSIZE;
assign M_AXI_awvalid = auto_ds_to_m01_couplers_AWVALID;
assign M_AXI_bready = auto_ds_to_m01_couplers_BREADY;
assign M_AXI_rready = auto_ds_to_m01_couplers_RREADY;
assign M_AXI_wdata[31:0] = auto_ds_to_m01_couplers_WDATA;
assign M_AXI_wlast = auto_ds_to_m01_couplers_WLAST;
assign M_AXI_wstrb[3:0] = auto_ds_to_m01_couplers_WSTRB;
assign M_AXI_wvalid = auto_ds_to_m01_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN;
assign S_AXI_arready = m01_couplers_to_auto_ds_ARREADY;
assign S_AXI_awready = m01_couplers_to_auto_ds_AWREADY;
assign S_AXI_bresp[1:0] = m01_couplers_to_auto_ds_BRESP;
assign S_AXI_bvalid = m01_couplers_to_auto_ds_BVALID;
assign S_AXI_rdata[63:0] = m01_couplers_to_auto_ds_RDATA;
assign S_AXI_rlast = m01_couplers_to_auto_ds_RLAST;
assign S_AXI_rresp[1:0] = m01_couplers_to_auto_ds_RRESP;
assign S_AXI_rvalid = m01_couplers_to_auto_ds_RVALID;
assign S_AXI_wready = m01_couplers_to_auto_ds_WREADY;
assign auto_ds_to_m01_couplers_ARREADY = M_AXI_arready;
assign auto_ds_to_m01_couplers_AWREADY = M_AXI_awready;
assign auto_ds_to_m01_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_ds_to_m01_couplers_BVALID = M_AXI_bvalid;
assign auto_ds_to_m01_couplers_RDATA = M_AXI_rdata[31:0];
assign auto_ds_to_m01_couplers_RLAST = M_AXI_rlast;
assign auto_ds_to_m01_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_ds_to_m01_couplers_RVALID = M_AXI_rvalid;
assign auto_ds_to_m01_couplers_WREADY = M_AXI_wready;
assign m01_couplers_to_auto_ds_ARADDR = S_AXI_araddr[31:0];
assign m01_couplers_to_auto_ds_ARBURST = S_AXI_arburst[1:0];
assign m01_couplers_to_auto_ds_ARCACHE = S_AXI_arcache[3:0];
assign m01_couplers_to_auto_ds_ARLEN = S_AXI_arlen[7:0];
assign m01_couplers_to_auto_ds_ARLOCK = S_AXI_arlock[0];
assign m01_couplers_to_auto_ds_ARPROT = S_AXI_arprot[2:0];
assign m01_couplers_to_auto_ds_ARQOS = S_AXI_arqos[3:0];
assign m01_couplers_to_auto_ds_ARREGION = S_AXI_arregion[3:0];
assign m01_couplers_to_auto_ds_ARSIZE = S_AXI_arsize[2:0];
assign m01_couplers_to_auto_ds_ARVALID = S_AXI_arvalid;
assign m01_couplers_to_auto_ds_AWADDR = S_AXI_awaddr[31:0];
assign m01_couplers_to_auto_ds_AWBURST = S_AXI_awburst[1:0];
assign m01_couplers_to_auto_ds_AWCACHE = S_AXI_awcache[3:0];
assign m01_couplers_to_auto_ds_AWLEN = S_AXI_awlen[7:0];
assign m01_couplers_to_auto_ds_AWLOCK = S_AXI_awlock[0];
assign m01_couplers_to_auto_ds_AWPROT = S_AXI_awprot[2:0];
assign m01_couplers_to_auto_ds_AWQOS = S_AXI_awqos[3:0];
assign m01_couplers_to_auto_ds_AWREGION = S_AXI_awregion[3:0];
assign m01_couplers_to_auto_ds_AWSIZE = S_AXI_awsize[2:0];
assign m01_couplers_to_auto_ds_AWVALID = S_AXI_awvalid;
assign m01_couplers_to_auto_ds_BREADY = S_AXI_bready;
assign m01_couplers_to_auto_ds_RREADY = S_AXI_rready;
assign m01_couplers_to_auto_ds_WDATA = S_AXI_wdata[63:0];
assign m01_couplers_to_auto_ds_WLAST = S_AXI_wlast;
assign m01_couplers_to_auto_ds_WSTRB = S_AXI_wstrb[7:0];
assign m01_couplers_to_auto_ds_WVALID = S_AXI_wvalid;
design_1_auto_ds_0 auto_ds
(.m_axi_araddr(auto_ds_to_m01_couplers_ARADDR),
.m_axi_arburst(auto_ds_to_m01_couplers_ARBURST),
.m_axi_arcache(auto_ds_to_m01_couplers_ARCACHE),
.m_axi_arlen(auto_ds_to_m01_couplers_ARLEN),
.m_axi_arlock(auto_ds_to_m01_couplers_ARLOCK),
.m_axi_arprot(auto_ds_to_m01_couplers_ARPROT),
.m_axi_arready(auto_ds_to_m01_couplers_ARREADY),
.m_axi_arsize(auto_ds_to_m01_couplers_ARSIZE),
.m_axi_arvalid(auto_ds_to_m01_couplers_ARVALID),
.m_axi_awaddr(auto_ds_to_m01_couplers_AWADDR),
.m_axi_awburst(auto_ds_to_m01_couplers_AWBURST),
.m_axi_awcache(auto_ds_to_m01_couplers_AWCACHE),
.m_axi_awlen(auto_ds_to_m01_couplers_AWLEN),
.m_axi_awlock(auto_ds_to_m01_couplers_AWLOCK),
.m_axi_awprot(auto_ds_to_m01_couplers_AWPROT),
.m_axi_awready(auto_ds_to_m01_couplers_AWREADY),
.m_axi_awsize(auto_ds_to_m01_couplers_AWSIZE),
.m_axi_awvalid(auto_ds_to_m01_couplers_AWVALID),
.m_axi_bready(auto_ds_to_m01_couplers_BREADY),
.m_axi_bresp(auto_ds_to_m01_couplers_BRESP),
.m_axi_bvalid(auto_ds_to_m01_couplers_BVALID),
.m_axi_rdata(auto_ds_to_m01_couplers_RDATA),
.m_axi_rlast(auto_ds_to_m01_couplers_RLAST),
.m_axi_rready(auto_ds_to_m01_couplers_RREADY),
.m_axi_rresp(auto_ds_to_m01_couplers_RRESP),
.m_axi_rvalid(auto_ds_to_m01_couplers_RVALID),
.m_axi_wdata(auto_ds_to_m01_couplers_WDATA),
.m_axi_wlast(auto_ds_to_m01_couplers_WLAST),
.m_axi_wready(auto_ds_to_m01_couplers_WREADY),
.m_axi_wstrb(auto_ds_to_m01_couplers_WSTRB),
.m_axi_wvalid(auto_ds_to_m01_couplers_WVALID),
.s_axi_aclk(S_ACLK_1),
.s_axi_araddr(m01_couplers_to_auto_ds_ARADDR[12:0]),
.s_axi_arburst(m01_couplers_to_auto_ds_ARBURST),
.s_axi_arcache(m01_couplers_to_auto_ds_ARCACHE),
.s_axi_aresetn(S_ARESETN_1),
.s_axi_arlen(m01_couplers_to_auto_ds_ARLEN),
.s_axi_arlock(m01_couplers_to_auto_ds_ARLOCK),
.s_axi_arprot(m01_couplers_to_auto_ds_ARPROT),
.s_axi_arqos(m01_couplers_to_auto_ds_ARQOS),
.s_axi_arready(m01_couplers_to_auto_ds_ARREADY),
.s_axi_arregion(m01_couplers_to_auto_ds_ARREGION),
.s_axi_arsize(m01_couplers_to_auto_ds_ARSIZE),
.s_axi_arvalid(m01_couplers_to_auto_ds_ARVALID),
.s_axi_awaddr(m01_couplers_to_auto_ds_AWADDR[12:0]),
.s_axi_awburst(m01_couplers_to_auto_ds_AWBURST),
.s_axi_awcache(m01_couplers_to_auto_ds_AWCACHE),
.s_axi_awlen(m01_couplers_to_auto_ds_AWLEN),
.s_axi_awlock(m01_couplers_to_auto_ds_AWLOCK),
.s_axi_awprot(m01_couplers_to_auto_ds_AWPROT),
.s_axi_awqos(m01_couplers_to_auto_ds_AWQOS),
.s_axi_awready(m01_couplers_to_auto_ds_AWREADY),
.s_axi_awregion(m01_couplers_to_auto_ds_AWREGION),
.s_axi_awsize(m01_couplers_to_auto_ds_AWSIZE),
.s_axi_awvalid(m01_couplers_to_auto_ds_AWVALID),
.s_axi_bready(m01_couplers_to_auto_ds_BREADY),
.s_axi_bresp(m01_couplers_to_auto_ds_BRESP),
.s_axi_bvalid(m01_couplers_to_auto_ds_BVALID),
.s_axi_rdata(m01_couplers_to_auto_ds_RDATA),
.s_axi_rlast(m01_couplers_to_auto_ds_RLAST),
.s_axi_rready(m01_couplers_to_auto_ds_RREADY),
.s_axi_rresp(m01_couplers_to_auto_ds_RRESP),
.s_axi_rvalid(m01_couplers_to_auto_ds_RVALID),
.s_axi_wdata(m01_couplers_to_auto_ds_WDATA),
.s_axi_wlast(m01_couplers_to_auto_ds_WLAST),
.s_axi_wready(m01_couplers_to_auto_ds_WREADY),
.s_axi_wstrb(m01_couplers_to_auto_ds_WSTRB),
.s_axi_wvalid(m01_couplers_to_auto_ds_WVALID));
endmodule
module m01_couplers_imp_U5OCM1
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arburst,
M_AXI_arcache,
M_AXI_arlen,
M_AXI_arlock,
M_AXI_arprot,
M_AXI_arready,
M_AXI_arsize,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awburst,
M_AXI_awcache,
M_AXI_awlen,
M_AXI_awlock,
M_AXI_awprot,
M_AXI_awready,
M_AXI_awsize,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rlast,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wlast,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arregion,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awregion,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input M_ARESETN;
output [12:0]M_AXI_araddr;
output [1:0]M_AXI_arburst;
output [3:0]M_AXI_arcache;
output [7:0]M_AXI_arlen;
output [0:0]M_AXI_arlock;
output [2:0]M_AXI_arprot;
input M_AXI_arready;
output [2:0]M_AXI_arsize;
output M_AXI_arvalid;
output [12:0]M_AXI_awaddr;
output [1:0]M_AXI_awburst;
output [3:0]M_AXI_awcache;
output [7:0]M_AXI_awlen;
output [0:0]M_AXI_awlock;
output [2:0]M_AXI_awprot;
input M_AXI_awready;
output [2:0]M_AXI_awsize;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
input M_AXI_rlast;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
output M_AXI_wlast;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [7:0]S_AXI_arlen;
input [0:0]S_AXI_arlock;
input [2:0]S_AXI_arprot;
input [3:0]S_AXI_arqos;
output S_AXI_arready;
input [3:0]S_AXI_arregion;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [7:0]S_AXI_awlen;
input [0:0]S_AXI_awlock;
input [2:0]S_AXI_awprot;
input [3:0]S_AXI_awqos;
output S_AXI_awready;
input [3:0]S_AXI_awregion;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [63:0]S_AXI_rdata;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [63:0]S_AXI_wdata;
input S_AXI_wlast;
output S_AXI_wready;
input [7:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire S_ACLK_1;
wire S_ARESETN_1;
wire [12:0]auto_ds_to_m01_couplers_ARADDR;
wire [1:0]auto_ds_to_m01_couplers_ARBURST;
wire [3:0]auto_ds_to_m01_couplers_ARCACHE;
wire [7:0]auto_ds_to_m01_couplers_ARLEN;
wire [0:0]auto_ds_to_m01_couplers_ARLOCK;
wire [2:0]auto_ds_to_m01_couplers_ARPROT;
wire auto_ds_to_m01_couplers_ARREADY;
wire [2:0]auto_ds_to_m01_couplers_ARSIZE;
wire auto_ds_to_m01_couplers_ARVALID;
wire [12:0]auto_ds_to_m01_couplers_AWADDR;
wire [1:0]auto_ds_to_m01_couplers_AWBURST;
wire [3:0]auto_ds_to_m01_couplers_AWCACHE;
wire [7:0]auto_ds_to_m01_couplers_AWLEN;
wire [0:0]auto_ds_to_m01_couplers_AWLOCK;
wire [2:0]auto_ds_to_m01_couplers_AWPROT;
wire auto_ds_to_m01_couplers_AWREADY;
wire [2:0]auto_ds_to_m01_couplers_AWSIZE;
wire auto_ds_to_m01_couplers_AWVALID;
wire auto_ds_to_m01_couplers_BREADY;
wire [1:0]auto_ds_to_m01_couplers_BRESP;
wire auto_ds_to_m01_couplers_BVALID;
wire [31:0]auto_ds_to_m01_couplers_RDATA;
wire auto_ds_to_m01_couplers_RLAST;
wire auto_ds_to_m01_couplers_RREADY;
wire [1:0]auto_ds_to_m01_couplers_RRESP;
wire auto_ds_to_m01_couplers_RVALID;
wire [31:0]auto_ds_to_m01_couplers_WDATA;
wire auto_ds_to_m01_couplers_WLAST;
wire auto_ds_to_m01_couplers_WREADY;
wire [3:0]auto_ds_to_m01_couplers_WSTRB;
wire auto_ds_to_m01_couplers_WVALID;
wire [31:0]m01_couplers_to_auto_ds_ARADDR;
wire [1:0]m01_couplers_to_auto_ds_ARBURST;
wire [3:0]m01_couplers_to_auto_ds_ARCACHE;
wire [7:0]m01_couplers_to_auto_ds_ARLEN;
wire [0:0]m01_couplers_to_auto_ds_ARLOCK;
wire [2:0]m01_couplers_to_auto_ds_ARPROT;
wire [3:0]m01_couplers_to_auto_ds_ARQOS;
wire m01_couplers_to_auto_ds_ARREADY;
wire [3:0]m01_couplers_to_auto_ds_ARREGION;
wire [2:0]m01_couplers_to_auto_ds_ARSIZE;
wire m01_couplers_to_auto_ds_ARVALID;
wire [31:0]m01_couplers_to_auto_ds_AWADDR;
wire [1:0]m01_couplers_to_auto_ds_AWBURST;
wire [3:0]m01_couplers_to_auto_ds_AWCACHE;
wire [7:0]m01_couplers_to_auto_ds_AWLEN;
wire [0:0]m01_couplers_to_auto_ds_AWLOCK;
wire [2:0]m01_couplers_to_auto_ds_AWPROT;
wire [3:0]m01_couplers_to_auto_ds_AWQOS;
wire m01_couplers_to_auto_ds_AWREADY;
wire [3:0]m01_couplers_to_auto_ds_AWREGION;
wire [2:0]m01_couplers_to_auto_ds_AWSIZE;
wire m01_couplers_to_auto_ds_AWVALID;
wire m01_couplers_to_auto_ds_BREADY;
wire [1:0]m01_couplers_to_auto_ds_BRESP;
wire m01_couplers_to_auto_ds_BVALID;
wire [63:0]m01_couplers_to_auto_ds_RDATA;
wire m01_couplers_to_auto_ds_RLAST;
wire m01_couplers_to_auto_ds_RREADY;
wire [1:0]m01_couplers_to_auto_ds_RRESP;
wire m01_couplers_to_auto_ds_RVALID;
wire [63:0]m01_couplers_to_auto_ds_WDATA;
wire m01_couplers_to_auto_ds_WLAST;
wire m01_couplers_to_auto_ds_WREADY;
wire [7:0]m01_couplers_to_auto_ds_WSTRB;
wire m01_couplers_to_auto_ds_WVALID;
assign M_AXI_araddr[12:0] = auto_ds_to_m01_couplers_ARADDR;
assign M_AXI_arburst[1:0] = auto_ds_to_m01_couplers_ARBURST;
assign M_AXI_arcache[3:0] = auto_ds_to_m01_couplers_ARCACHE;
assign M_AXI_arlen[7:0] = auto_ds_to_m01_couplers_ARLEN;
assign M_AXI_arlock[0] = auto_ds_to_m01_couplers_ARLOCK;
assign M_AXI_arprot[2:0] = auto_ds_to_m01_couplers_ARPROT;
assign M_AXI_arsize[2:0] = auto_ds_to_m01_couplers_ARSIZE;
assign M_AXI_arvalid = auto_ds_to_m01_couplers_ARVALID;
assign M_AXI_awaddr[12:0] = auto_ds_to_m01_couplers_AWADDR;
assign M_AXI_awburst[1:0] = auto_ds_to_m01_couplers_AWBURST;
assign M_AXI_awcache[3:0] = auto_ds_to_m01_couplers_AWCACHE;
assign M_AXI_awlen[7:0] = auto_ds_to_m01_couplers_AWLEN;
assign M_AXI_awlock[0] = auto_ds_to_m01_couplers_AWLOCK;
assign M_AXI_awprot[2:0] = auto_ds_to_m01_couplers_AWPROT;
assign M_AXI_awsize[2:0] = auto_ds_to_m01_couplers_AWSIZE;
assign M_AXI_awvalid = auto_ds_to_m01_couplers_AWVALID;
assign M_AXI_bready = auto_ds_to_m01_couplers_BREADY;
assign M_AXI_rready = auto_ds_to_m01_couplers_RREADY;
assign M_AXI_wdata[31:0] = auto_ds_to_m01_couplers_WDATA;
assign M_AXI_wlast = auto_ds_to_m01_couplers_WLAST;
assign M_AXI_wstrb[3:0] = auto_ds_to_m01_couplers_WSTRB;
assign M_AXI_wvalid = auto_ds_to_m01_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN;
assign S_AXI_arready = m01_couplers_to_auto_ds_ARREADY;
assign S_AXI_awready = m01_couplers_to_auto_ds_AWREADY;
assign S_AXI_bresp[1:0] = m01_couplers_to_auto_ds_BRESP;
assign S_AXI_bvalid = m01_couplers_to_auto_ds_BVALID;
assign S_AXI_rdata[63:0] = m01_couplers_to_auto_ds_RDATA;
assign S_AXI_rlast = m01_couplers_to_auto_ds_RLAST;
assign S_AXI_rresp[1:0] = m01_couplers_to_auto_ds_RRESP;
assign S_AXI_rvalid = m01_couplers_to_auto_ds_RVALID;
assign S_AXI_wready = m01_couplers_to_auto_ds_WREADY;
assign auto_ds_to_m01_couplers_ARREADY = M_AXI_arready;
assign auto_ds_to_m01_couplers_AWREADY = M_AXI_awready;
assign auto_ds_to_m01_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_ds_to_m01_couplers_BVALID = M_AXI_bvalid;
assign auto_ds_to_m01_couplers_RDATA = M_AXI_rdata[31:0];
assign auto_ds_to_m01_couplers_RLAST = M_AXI_rlast;
assign auto_ds_to_m01_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_ds_to_m01_couplers_RVALID = M_AXI_rvalid;
assign auto_ds_to_m01_couplers_WREADY = M_AXI_wready;
assign m01_couplers_to_auto_ds_ARADDR = S_AXI_araddr[31:0];
assign m01_couplers_to_auto_ds_ARBURST = S_AXI_arburst[1:0];
assign m01_couplers_to_auto_ds_ARCACHE = S_AXI_arcache[3:0];
assign m01_couplers_to_auto_ds_ARLEN = S_AXI_arlen[7:0];
assign m01_couplers_to_auto_ds_ARLOCK = S_AXI_arlock[0];
assign m01_couplers_to_auto_ds_ARPROT = S_AXI_arprot[2:0];
assign m01_couplers_to_auto_ds_ARQOS = S_AXI_arqos[3:0];
assign m01_couplers_to_auto_ds_ARREGION = S_AXI_arregion[3:0];
assign m01_couplers_to_auto_ds_ARSIZE = S_AXI_arsize[2:0];
assign m01_couplers_to_auto_ds_ARVALID = S_AXI_arvalid;
assign m01_couplers_to_auto_ds_AWADDR = S_AXI_awaddr[31:0];
assign m01_couplers_to_auto_ds_AWBURST = S_AXI_awburst[1:0];
assign m01_couplers_to_auto_ds_AWCACHE = S_AXI_awcache[3:0];
assign m01_couplers_to_auto_ds_AWLEN = S_AXI_awlen[7:0];
assign m01_couplers_to_auto_ds_AWLOCK = S_AXI_awlock[0];
assign m01_couplers_to_auto_ds_AWPROT = S_AXI_awprot[2:0];
assign m01_couplers_to_auto_ds_AWQOS = S_AXI_awqos[3:0];
assign m01_couplers_to_auto_ds_AWREGION = S_AXI_awregion[3:0];
assign m01_couplers_to_auto_ds_AWSIZE = S_AXI_awsize[2:0];
assign m01_couplers_to_auto_ds_AWVALID = S_AXI_awvalid;
assign m01_couplers_to_auto_ds_BREADY = S_AXI_bready;
assign m01_couplers_to_auto_ds_RREADY = S_AXI_rready;
assign m01_couplers_to_auto_ds_WDATA = S_AXI_wdata[63:0];
assign m01_couplers_to_auto_ds_WLAST = S_AXI_wlast;
assign m01_couplers_to_auto_ds_WSTRB = S_AXI_wstrb[7:0];
assign m01_couplers_to_auto_ds_WVALID = S_AXI_wvalid;
design_1_auto_ds_1 auto_ds
(.m_axi_araddr(auto_ds_to_m01_couplers_ARADDR),
.m_axi_arburst(auto_ds_to_m01_couplers_ARBURST),
.m_axi_arcache(auto_ds_to_m01_couplers_ARCACHE),
.m_axi_arlen(auto_ds_to_m01_couplers_ARLEN),
.m_axi_arlock(auto_ds_to_m01_couplers_ARLOCK),
.m_axi_arprot(auto_ds_to_m01_couplers_ARPROT),
.m_axi_arready(auto_ds_to_m01_couplers_ARREADY),
.m_axi_arsize(auto_ds_to_m01_couplers_ARSIZE),
.m_axi_arvalid(auto_ds_to_m01_couplers_ARVALID),
.m_axi_awaddr(auto_ds_to_m01_couplers_AWADDR),
.m_axi_awburst(auto_ds_to_m01_couplers_AWBURST),
.m_axi_awcache(auto_ds_to_m01_couplers_AWCACHE),
.m_axi_awlen(auto_ds_to_m01_couplers_AWLEN),
.m_axi_awlock(auto_ds_to_m01_couplers_AWLOCK),
.m_axi_awprot(auto_ds_to_m01_couplers_AWPROT),
.m_axi_awready(auto_ds_to_m01_couplers_AWREADY),
.m_axi_awsize(auto_ds_to_m01_couplers_AWSIZE),
.m_axi_awvalid(auto_ds_to_m01_couplers_AWVALID),
.m_axi_bready(auto_ds_to_m01_couplers_BREADY),
.m_axi_bresp(auto_ds_to_m01_couplers_BRESP),
.m_axi_bvalid(auto_ds_to_m01_couplers_BVALID),
.m_axi_rdata(auto_ds_to_m01_couplers_RDATA),
.m_axi_rlast(auto_ds_to_m01_couplers_RLAST),
.m_axi_rready(auto_ds_to_m01_couplers_RREADY),
.m_axi_rresp(auto_ds_to_m01_couplers_RRESP),
.m_axi_rvalid(auto_ds_to_m01_couplers_RVALID),
.m_axi_wdata(auto_ds_to_m01_couplers_WDATA),
.m_axi_wlast(auto_ds_to_m01_couplers_WLAST),
.m_axi_wready(auto_ds_to_m01_couplers_WREADY),
.m_axi_wstrb(auto_ds_to_m01_couplers_WSTRB),
.m_axi_wvalid(auto_ds_to_m01_couplers_WVALID),
.s_axi_aclk(S_ACLK_1),
.s_axi_araddr(m01_couplers_to_auto_ds_ARADDR[12:0]),
.s_axi_arburst(m01_couplers_to_auto_ds_ARBURST),
.s_axi_arcache(m01_couplers_to_auto_ds_ARCACHE),
.s_axi_aresetn(S_ARESETN_1),
.s_axi_arlen(m01_couplers_to_auto_ds_ARLEN),
.s_axi_arlock(m01_couplers_to_auto_ds_ARLOCK),
.s_axi_arprot(m01_couplers_to_auto_ds_ARPROT),
.s_axi_arqos(m01_couplers_to_auto_ds_ARQOS),
.s_axi_arready(m01_couplers_to_auto_ds_ARREADY),
.s_axi_arregion(m01_couplers_to_auto_ds_ARREGION),
.s_axi_arsize(m01_couplers_to_auto_ds_ARSIZE),
.s_axi_arvalid(m01_couplers_to_auto_ds_ARVALID),
.s_axi_awaddr(m01_couplers_to_auto_ds_AWADDR[12:0]),
.s_axi_awburst(m01_couplers_to_auto_ds_AWBURST),
.s_axi_awcache(m01_couplers_to_auto_ds_AWCACHE),
.s_axi_awlen(m01_couplers_to_auto_ds_AWLEN),
.s_axi_awlock(m01_couplers_to_auto_ds_AWLOCK),
.s_axi_awprot(m01_couplers_to_auto_ds_AWPROT),
.s_axi_awqos(m01_couplers_to_auto_ds_AWQOS),
.s_axi_awready(m01_couplers_to_auto_ds_AWREADY),
.s_axi_awregion(m01_couplers_to_auto_ds_AWREGION),
.s_axi_awsize(m01_couplers_to_auto_ds_AWSIZE),
.s_axi_awvalid(m01_couplers_to_auto_ds_AWVALID),
.s_axi_bready(m01_couplers_to_auto_ds_BREADY),
.s_axi_bresp(m01_couplers_to_auto_ds_BRESP),
.s_axi_bvalid(m01_couplers_to_auto_ds_BVALID),
.s_axi_rdata(m01_couplers_to_auto_ds_RDATA),
.s_axi_rlast(m01_couplers_to_auto_ds_RLAST),
.s_axi_rready(m01_couplers_to_auto_ds_RREADY),
.s_axi_rresp(m01_couplers_to_auto_ds_RRESP),
.s_axi_rvalid(m01_couplers_to_auto_ds_RVALID),
.s_axi_wdata(m01_couplers_to_auto_ds_WDATA),
.s_axi_wlast(m01_couplers_to_auto_ds_WLAST),
.s_axi_wready(m01_couplers_to_auto_ds_WREADY),
.s_axi_wstrb(m01_couplers_to_auto_ds_WSTRB),
.s_axi_wvalid(m01_couplers_to_auto_ds_WVALID));
endmodule
module m02_couplers_imp_MVV5YQ
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arready,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awready,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wready,
S_AXI_wvalid);
input M_ACLK;
input M_ARESETN;
output [31:0]M_AXI_araddr;
input [0:0]M_AXI_arready;
output [0:0]M_AXI_arvalid;
output [31:0]M_AXI_awaddr;
input [0:0]M_AXI_awready;
output [0:0]M_AXI_awvalid;
output [0:0]M_AXI_bready;
input [1:0]M_AXI_bresp;
input [0:0]M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output [0:0]M_AXI_rready;
input [1:0]M_AXI_rresp;
input [0:0]M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input [0:0]M_AXI_wready;
output [0:0]M_AXI_wvalid;
input S_ACLK;
input S_ARESETN;
input [31:0]S_AXI_araddr;
output [0:0]S_AXI_arready;
input [0:0]S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
output [0:0]S_AXI_awready;
input [0:0]S_AXI_awvalid;
input [0:0]S_AXI_bready;
output [1:0]S_AXI_bresp;
output [0:0]S_AXI_bvalid;
output [31:0]S_AXI_rdata;
input [0:0]S_AXI_rready;
output [1:0]S_AXI_rresp;
output [0:0]S_AXI_rvalid;
input [31:0]S_AXI_wdata;
output [0:0]S_AXI_wready;
input [0:0]S_AXI_wvalid;
wire [31:0]m02_couplers_to_m02_couplers_ARADDR;
wire [0:0]m02_couplers_to_m02_couplers_ARREADY;
wire [0:0]m02_couplers_to_m02_couplers_ARVALID;
wire [31:0]m02_couplers_to_m02_couplers_AWADDR;
wire [0:0]m02_couplers_to_m02_couplers_AWREADY;
wire [0:0]m02_couplers_to_m02_couplers_AWVALID;
wire [0:0]m02_couplers_to_m02_couplers_BREADY;
wire [1:0]m02_couplers_to_m02_couplers_BRESP;
wire [0:0]m02_couplers_to_m02_couplers_BVALID;
wire [31:0]m02_couplers_to_m02_couplers_RDATA;
wire [0:0]m02_couplers_to_m02_couplers_RREADY;
wire [1:0]m02_couplers_to_m02_couplers_RRESP;
wire [0:0]m02_couplers_to_m02_couplers_RVALID;
wire [31:0]m02_couplers_to_m02_couplers_WDATA;
wire [0:0]m02_couplers_to_m02_couplers_WREADY;
wire [0:0]m02_couplers_to_m02_couplers_WVALID;
assign M_AXI_araddr[31:0] = m02_couplers_to_m02_couplers_ARADDR;
assign M_AXI_arvalid[0] = m02_couplers_to_m02_couplers_ARVALID;
assign M_AXI_awaddr[31:0] = m02_couplers_to_m02_couplers_AWADDR;
assign M_AXI_awvalid[0] = m02_couplers_to_m02_couplers_AWVALID;
assign M_AXI_bready[0] = m02_couplers_to_m02_couplers_BREADY;
assign M_AXI_rready[0] = m02_couplers_to_m02_couplers_RREADY;
assign M_AXI_wdata[31:0] = m02_couplers_to_m02_couplers_WDATA;
assign M_AXI_wvalid[0] = m02_couplers_to_m02_couplers_WVALID;
assign S_AXI_arready[0] = m02_couplers_to_m02_couplers_ARREADY;
assign S_AXI_awready[0] = m02_couplers_to_m02_couplers_AWREADY;
assign S_AXI_bresp[1:0] = m02_couplers_to_m02_couplers_BRESP;
assign S_AXI_bvalid[0] = m02_couplers_to_m02_couplers_BVALID;
assign S_AXI_rdata[31:0] = m02_couplers_to_m02_couplers_RDATA;
assign S_AXI_rresp[1:0] = m02_couplers_to_m02_couplers_RRESP;
assign S_AXI_rvalid[0] = m02_couplers_to_m02_couplers_RVALID;
assign S_AXI_wready[0] = m02_couplers_to_m02_couplers_WREADY;
assign m02_couplers_to_m02_couplers_ARADDR = S_AXI_araddr[31:0];
assign m02_couplers_to_m02_couplers_ARREADY = M_AXI_arready[0];
assign m02_couplers_to_m02_couplers_ARVALID = S_AXI_arvalid[0];
assign m02_couplers_to_m02_couplers_AWADDR = S_AXI_awaddr[31:0];
assign m02_couplers_to_m02_couplers_AWREADY = M_AXI_awready[0];
assign m02_couplers_to_m02_couplers_AWVALID = S_AXI_awvalid[0];
assign m02_couplers_to_m02_couplers_BREADY = S_AXI_bready[0];
assign m02_couplers_to_m02_couplers_BRESP = M_AXI_bresp[1:0];
assign m02_couplers_to_m02_couplers_BVALID = M_AXI_bvalid[0];
assign m02_couplers_to_m02_couplers_RDATA = M_AXI_rdata[31:0];
assign m02_couplers_to_m02_couplers_RREADY = S_AXI_rready[0];
assign m02_couplers_to_m02_couplers_RRESP = M_AXI_rresp[1:0];
assign m02_couplers_to_m02_couplers_RVALID = M_AXI_rvalid[0];
assign m02_couplers_to_m02_couplers_WDATA = S_AXI_wdata[31:0];
assign m02_couplers_to_m02_couplers_WREADY = M_AXI_wready[0];
assign m02_couplers_to_m02_couplers_WVALID = S_AXI_wvalid[0];
endmodule
module m03_couplers_imp_1GHG26R
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arready,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awready,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wready,
S_AXI_wvalid);
input M_ACLK;
input M_ARESETN;
output [31:0]M_AXI_araddr;
input [0:0]M_AXI_arready;
output [0:0]M_AXI_arvalid;
output [31:0]M_AXI_awaddr;
input [0:0]M_AXI_awready;
output [0:0]M_AXI_awvalid;
output [0:0]M_AXI_bready;
input [1:0]M_AXI_bresp;
input [0:0]M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output [0:0]M_AXI_rready;
input [1:0]M_AXI_rresp;
input [0:0]M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input [0:0]M_AXI_wready;
output [0:0]M_AXI_wvalid;
input S_ACLK;
input S_ARESETN;
input [31:0]S_AXI_araddr;
output [0:0]S_AXI_arready;
input [0:0]S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
output [0:0]S_AXI_awready;
input [0:0]S_AXI_awvalid;
input [0:0]S_AXI_bready;
output [1:0]S_AXI_bresp;
output [0:0]S_AXI_bvalid;
output [31:0]S_AXI_rdata;
input [0:0]S_AXI_rready;
output [1:0]S_AXI_rresp;
output [0:0]S_AXI_rvalid;
input [31:0]S_AXI_wdata;
output [0:0]S_AXI_wready;
input [0:0]S_AXI_wvalid;
wire [31:0]m03_couplers_to_m03_couplers_ARADDR;
wire [0:0]m03_couplers_to_m03_couplers_ARREADY;
wire [0:0]m03_couplers_to_m03_couplers_ARVALID;
wire [31:0]m03_couplers_to_m03_couplers_AWADDR;
wire [0:0]m03_couplers_to_m03_couplers_AWREADY;
wire [0:0]m03_couplers_to_m03_couplers_AWVALID;
wire [0:0]m03_couplers_to_m03_couplers_BREADY;
wire [1:0]m03_couplers_to_m03_couplers_BRESP;
wire [0:0]m03_couplers_to_m03_couplers_BVALID;
wire [31:0]m03_couplers_to_m03_couplers_RDATA;
wire [0:0]m03_couplers_to_m03_couplers_RREADY;
wire [1:0]m03_couplers_to_m03_couplers_RRESP;
wire [0:0]m03_couplers_to_m03_couplers_RVALID;
wire [31:0]m03_couplers_to_m03_couplers_WDATA;
wire [0:0]m03_couplers_to_m03_couplers_WREADY;
wire [0:0]m03_couplers_to_m03_couplers_WVALID;
assign M_AXI_araddr[31:0] = m03_couplers_to_m03_couplers_ARADDR;
assign M_AXI_arvalid[0] = m03_couplers_to_m03_couplers_ARVALID;
assign M_AXI_awaddr[31:0] = m03_couplers_to_m03_couplers_AWADDR;
assign M_AXI_awvalid[0] = m03_couplers_to_m03_couplers_AWVALID;
assign M_AXI_bready[0] = m03_couplers_to_m03_couplers_BREADY;
assign M_AXI_rready[0] = m03_couplers_to_m03_couplers_RREADY;
assign M_AXI_wdata[31:0] = m03_couplers_to_m03_couplers_WDATA;
assign M_AXI_wvalid[0] = m03_couplers_to_m03_couplers_WVALID;
assign S_AXI_arready[0] = m03_couplers_to_m03_couplers_ARREADY;
assign S_AXI_awready[0] = m03_couplers_to_m03_couplers_AWREADY;
assign S_AXI_bresp[1:0] = m03_couplers_to_m03_couplers_BRESP;
assign S_AXI_bvalid[0] = m03_couplers_to_m03_couplers_BVALID;
assign S_AXI_rdata[31:0] = m03_couplers_to_m03_couplers_RDATA;
assign S_AXI_rresp[1:0] = m03_couplers_to_m03_couplers_RRESP;
assign S_AXI_rvalid[0] = m03_couplers_to_m03_couplers_RVALID;
assign S_AXI_wready[0] = m03_couplers_to_m03_couplers_WREADY;
assign m03_couplers_to_m03_couplers_ARADDR = S_AXI_araddr[31:0];
assign m03_couplers_to_m03_couplers_ARREADY = M_AXI_arready[0];
assign m03_couplers_to_m03_couplers_ARVALID = S_AXI_arvalid[0];
assign m03_couplers_to_m03_couplers_AWADDR = S_AXI_awaddr[31:0];
assign m03_couplers_to_m03_couplers_AWREADY = M_AXI_awready[0];
assign m03_couplers_to_m03_couplers_AWVALID = S_AXI_awvalid[0];
assign m03_couplers_to_m03_couplers_BREADY = S_AXI_bready[0];
assign m03_couplers_to_m03_couplers_BRESP = M_AXI_bresp[1:0];
assign m03_couplers_to_m03_couplers_BVALID = M_AXI_bvalid[0];
assign m03_couplers_to_m03_couplers_RDATA = M_AXI_rdata[31:0];
assign m03_couplers_to_m03_couplers_RREADY = S_AXI_rready[0];
assign m03_couplers_to_m03_couplers_RRESP = M_AXI_rresp[1:0];
assign m03_couplers_to_m03_couplers_RVALID = M_AXI_rvalid[0];
assign m03_couplers_to_m03_couplers_WDATA = S_AXI_wdata[31:0];
assign m03_couplers_to_m03_couplers_WREADY = M_AXI_wready[0];
assign m03_couplers_to_m03_couplers_WVALID = S_AXI_wvalid[0];
endmodule
module s00_couplers_imp_1AYWH35
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arburst,
M_AXI_arcache,
M_AXI_arlen,
M_AXI_arlock,
M_AXI_arprot,
M_AXI_arqos,
M_AXI_arready,
M_AXI_arsize,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awburst,
M_AXI_awcache,
M_AXI_awlen,
M_AXI_awlock,
M_AXI_awprot,
M_AXI_awqos,
M_AXI_awready,
M_AXI_awsize,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rlast,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wlast,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arlen,
S_AXI_arprot,
S_AXI_arready,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awlen,
S_AXI_awprot,
S_AXI_awready,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input M_ARESETN;
output [31:0]M_AXI_araddr;
output [1:0]M_AXI_arburst;
output [3:0]M_AXI_arcache;
output [7:0]M_AXI_arlen;
output [0:0]M_AXI_arlock;
output [2:0]M_AXI_arprot;
output [3:0]M_AXI_arqos;
input M_AXI_arready;
output [2:0]M_AXI_arsize;
output M_AXI_arvalid;
output [31:0]M_AXI_awaddr;
output [1:0]M_AXI_awburst;
output [3:0]M_AXI_awcache;
output [7:0]M_AXI_awlen;
output [0:0]M_AXI_awlock;
output [2:0]M_AXI_awprot;
output [3:0]M_AXI_awqos;
input M_AXI_awready;
output [2:0]M_AXI_awsize;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [63:0]M_AXI_rdata;
input M_AXI_rlast;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [63:0]M_AXI_wdata;
output M_AXI_wlast;
input M_AXI_wready;
output [7:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [7:0]S_AXI_arlen;
input [2:0]S_AXI_arprot;
output S_AXI_arready;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [7:0]S_AXI_awlen;
input [2:0]S_AXI_awprot;
output S_AXI_awready;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
input S_AXI_wlast;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire S_ACLK_1;
wire S_ARESETN_1;
wire [31:0]auto_us_to_s00_couplers_ARADDR;
wire [1:0]auto_us_to_s00_couplers_ARBURST;
wire [3:0]auto_us_to_s00_couplers_ARCACHE;
wire [7:0]auto_us_to_s00_couplers_ARLEN;
wire [0:0]auto_us_to_s00_couplers_ARLOCK;
wire [2:0]auto_us_to_s00_couplers_ARPROT;
wire [3:0]auto_us_to_s00_couplers_ARQOS;
wire auto_us_to_s00_couplers_ARREADY;
wire [2:0]auto_us_to_s00_couplers_ARSIZE;
wire auto_us_to_s00_couplers_ARVALID;
wire [31:0]auto_us_to_s00_couplers_AWADDR;
wire [1:0]auto_us_to_s00_couplers_AWBURST;
wire [3:0]auto_us_to_s00_couplers_AWCACHE;
wire [7:0]auto_us_to_s00_couplers_AWLEN;
wire [0:0]auto_us_to_s00_couplers_AWLOCK;
wire [2:0]auto_us_to_s00_couplers_AWPROT;
wire [3:0]auto_us_to_s00_couplers_AWQOS;
wire auto_us_to_s00_couplers_AWREADY;
wire [2:0]auto_us_to_s00_couplers_AWSIZE;
wire auto_us_to_s00_couplers_AWVALID;
wire auto_us_to_s00_couplers_BREADY;
wire [1:0]auto_us_to_s00_couplers_BRESP;
wire auto_us_to_s00_couplers_BVALID;
wire [63:0]auto_us_to_s00_couplers_RDATA;
wire auto_us_to_s00_couplers_RLAST;
wire auto_us_to_s00_couplers_RREADY;
wire [1:0]auto_us_to_s00_couplers_RRESP;
wire auto_us_to_s00_couplers_RVALID;
wire [63:0]auto_us_to_s00_couplers_WDATA;
wire auto_us_to_s00_couplers_WLAST;
wire auto_us_to_s00_couplers_WREADY;
wire [7:0]auto_us_to_s00_couplers_WSTRB;
wire auto_us_to_s00_couplers_WVALID;
wire [31:0]s00_couplers_to_auto_us_ARADDR;
wire [1:0]s00_couplers_to_auto_us_ARBURST;
wire [3:0]s00_couplers_to_auto_us_ARCACHE;
wire [7:0]s00_couplers_to_auto_us_ARLEN;
wire [2:0]s00_couplers_to_auto_us_ARPROT;
wire s00_couplers_to_auto_us_ARREADY;
wire [2:0]s00_couplers_to_auto_us_ARSIZE;
wire s00_couplers_to_auto_us_ARVALID;
wire [31:0]s00_couplers_to_auto_us_AWADDR;
wire [1:0]s00_couplers_to_auto_us_AWBURST;
wire [3:0]s00_couplers_to_auto_us_AWCACHE;
wire [7:0]s00_couplers_to_auto_us_AWLEN;
wire [2:0]s00_couplers_to_auto_us_AWPROT;
wire s00_couplers_to_auto_us_AWREADY;
wire [2:0]s00_couplers_to_auto_us_AWSIZE;
wire s00_couplers_to_auto_us_AWVALID;
wire s00_couplers_to_auto_us_BREADY;
wire [1:0]s00_couplers_to_auto_us_BRESP;
wire s00_couplers_to_auto_us_BVALID;
wire [31:0]s00_couplers_to_auto_us_RDATA;
wire s00_couplers_to_auto_us_RLAST;
wire s00_couplers_to_auto_us_RREADY;
wire [1:0]s00_couplers_to_auto_us_RRESP;
wire s00_couplers_to_auto_us_RVALID;
wire [31:0]s00_couplers_to_auto_us_WDATA;
wire s00_couplers_to_auto_us_WLAST;
wire s00_couplers_to_auto_us_WREADY;
wire [3:0]s00_couplers_to_auto_us_WSTRB;
wire s00_couplers_to_auto_us_WVALID;
assign M_AXI_araddr[31:0] = auto_us_to_s00_couplers_ARADDR;
assign M_AXI_arburst[1:0] = auto_us_to_s00_couplers_ARBURST;
assign M_AXI_arcache[3:0] = auto_us_to_s00_couplers_ARCACHE;
assign M_AXI_arlen[7:0] = auto_us_to_s00_couplers_ARLEN;
assign M_AXI_arlock[0] = auto_us_to_s00_couplers_ARLOCK;
assign M_AXI_arprot[2:0] = auto_us_to_s00_couplers_ARPROT;
assign M_AXI_arqos[3:0] = auto_us_to_s00_couplers_ARQOS;
assign M_AXI_arsize[2:0] = auto_us_to_s00_couplers_ARSIZE;
assign M_AXI_arvalid = auto_us_to_s00_couplers_ARVALID;
assign M_AXI_awaddr[31:0] = auto_us_to_s00_couplers_AWADDR;
assign M_AXI_awburst[1:0] = auto_us_to_s00_couplers_AWBURST;
assign M_AXI_awcache[3:0] = auto_us_to_s00_couplers_AWCACHE;
assign M_AXI_awlen[7:0] = auto_us_to_s00_couplers_AWLEN;
assign M_AXI_awlock[0] = auto_us_to_s00_couplers_AWLOCK;
assign M_AXI_awprot[2:0] = auto_us_to_s00_couplers_AWPROT;
assign M_AXI_awqos[3:0] = auto_us_to_s00_couplers_AWQOS;
assign M_AXI_awsize[2:0] = auto_us_to_s00_couplers_AWSIZE;
assign M_AXI_awvalid = auto_us_to_s00_couplers_AWVALID;
assign M_AXI_bready = auto_us_to_s00_couplers_BREADY;
assign M_AXI_rready = auto_us_to_s00_couplers_RREADY;
assign M_AXI_wdata[63:0] = auto_us_to_s00_couplers_WDATA;
assign M_AXI_wlast = auto_us_to_s00_couplers_WLAST;
assign M_AXI_wstrb[7:0] = auto_us_to_s00_couplers_WSTRB;
assign M_AXI_wvalid = auto_us_to_s00_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN;
assign S_AXI_arready = s00_couplers_to_auto_us_ARREADY;
assign S_AXI_awready = s00_couplers_to_auto_us_AWREADY;
assign S_AXI_bresp[1:0] = s00_couplers_to_auto_us_BRESP;
assign S_AXI_bvalid = s00_couplers_to_auto_us_BVALID;
assign S_AXI_rdata[31:0] = s00_couplers_to_auto_us_RDATA;
assign S_AXI_rlast = s00_couplers_to_auto_us_RLAST;
assign S_AXI_rresp[1:0] = s00_couplers_to_auto_us_RRESP;
assign S_AXI_rvalid = s00_couplers_to_auto_us_RVALID;
assign S_AXI_wready = s00_couplers_to_auto_us_WREADY;
assign auto_us_to_s00_couplers_ARREADY = M_AXI_arready;
assign auto_us_to_s00_couplers_AWREADY = M_AXI_awready;
assign auto_us_to_s00_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_us_to_s00_couplers_BVALID = M_AXI_bvalid;
assign auto_us_to_s00_couplers_RDATA = M_AXI_rdata[63:0];
assign auto_us_to_s00_couplers_RLAST = M_AXI_rlast;
assign auto_us_to_s00_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_us_to_s00_couplers_RVALID = M_AXI_rvalid;
assign auto_us_to_s00_couplers_WREADY = M_AXI_wready;
assign s00_couplers_to_auto_us_ARADDR = S_AXI_araddr[31:0];
assign s00_couplers_to_auto_us_ARBURST = S_AXI_arburst[1:0];
assign s00_couplers_to_auto_us_ARCACHE = S_AXI_arcache[3:0];
assign s00_couplers_to_auto_us_ARLEN = S_AXI_arlen[7:0];
assign s00_couplers_to_auto_us_ARPROT = S_AXI_arprot[2:0];
assign s00_couplers_to_auto_us_ARSIZE = S_AXI_arsize[2:0];
assign s00_couplers_to_auto_us_ARVALID = S_AXI_arvalid;
assign s00_couplers_to_auto_us_AWADDR = S_AXI_awaddr[31:0];
assign s00_couplers_to_auto_us_AWBURST = S_AXI_awburst[1:0];
assign s00_couplers_to_auto_us_AWCACHE = S_AXI_awcache[3:0];
assign s00_couplers_to_auto_us_AWLEN = S_AXI_awlen[7:0];
assign s00_couplers_to_auto_us_AWPROT = S_AXI_awprot[2:0];
assign s00_couplers_to_auto_us_AWSIZE = S_AXI_awsize[2:0];
assign s00_couplers_to_auto_us_AWVALID = S_AXI_awvalid;
assign s00_couplers_to_auto_us_BREADY = S_AXI_bready;
assign s00_couplers_to_auto_us_RREADY = S_AXI_rready;
assign s00_couplers_to_auto_us_WDATA = S_AXI_wdata[31:0];
assign s00_couplers_to_auto_us_WLAST = S_AXI_wlast;
assign s00_couplers_to_auto_us_WSTRB = S_AXI_wstrb[3:0];
assign s00_couplers_to_auto_us_WVALID = S_AXI_wvalid;
design_1_auto_us_2 auto_us
(.m_axi_araddr(auto_us_to_s00_couplers_ARADDR),
.m_axi_arburst(auto_us_to_s00_couplers_ARBURST),
.m_axi_arcache(auto_us_to_s00_couplers_ARCACHE),
.m_axi_arlen(auto_us_to_s00_couplers_ARLEN),
.m_axi_arlock(auto_us_to_s00_couplers_ARLOCK),
.m_axi_arprot(auto_us_to_s00_couplers_ARPROT),
.m_axi_arqos(auto_us_to_s00_couplers_ARQOS),
.m_axi_arready(auto_us_to_s00_couplers_ARREADY),
.m_axi_arsize(auto_us_to_s00_couplers_ARSIZE),
.m_axi_arvalid(auto_us_to_s00_couplers_ARVALID),
.m_axi_awaddr(auto_us_to_s00_couplers_AWADDR),
.m_axi_awburst(auto_us_to_s00_couplers_AWBURST),
.m_axi_awcache(auto_us_to_s00_couplers_AWCACHE),
.m_axi_awlen(auto_us_to_s00_couplers_AWLEN),
.m_axi_awlock(auto_us_to_s00_couplers_AWLOCK),
.m_axi_awprot(auto_us_to_s00_couplers_AWPROT),
.m_axi_awqos(auto_us_to_s00_couplers_AWQOS),
.m_axi_awready(auto_us_to_s00_couplers_AWREADY),
.m_axi_awsize(auto_us_to_s00_couplers_AWSIZE),
.m_axi_awvalid(auto_us_to_s00_couplers_AWVALID),
.m_axi_bready(auto_us_to_s00_couplers_BREADY),
.m_axi_bresp(auto_us_to_s00_couplers_BRESP),
.m_axi_bvalid(auto_us_to_s00_couplers_BVALID),
.m_axi_rdata(auto_us_to_s00_couplers_RDATA),
.m_axi_rlast(auto_us_to_s00_couplers_RLAST),
.m_axi_rready(auto_us_to_s00_couplers_RREADY),
.m_axi_rresp(auto_us_to_s00_couplers_RRESP),
.m_axi_rvalid(auto_us_to_s00_couplers_RVALID),
.m_axi_wdata(auto_us_to_s00_couplers_WDATA),
.m_axi_wlast(auto_us_to_s00_couplers_WLAST),
.m_axi_wready(auto_us_to_s00_couplers_WREADY),
.m_axi_wstrb(auto_us_to_s00_couplers_WSTRB),
.m_axi_wvalid(auto_us_to_s00_couplers_WVALID),
.s_axi_aclk(S_ACLK_1),
.s_axi_araddr(s00_couplers_to_auto_us_ARADDR),
.s_axi_arburst(s00_couplers_to_auto_us_ARBURST),
.s_axi_arcache(s00_couplers_to_auto_us_ARCACHE),
.s_axi_aresetn(S_ARESETN_1),
.s_axi_arlen(s00_couplers_to_auto_us_ARLEN),
.s_axi_arlock(1'b0),
.s_axi_arprot(s00_couplers_to_auto_us_ARPROT),
.s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(s00_couplers_to_auto_us_ARREADY),
.s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arsize(s00_couplers_to_auto_us_ARSIZE),
.s_axi_arvalid(s00_couplers_to_auto_us_ARVALID),
.s_axi_awaddr(s00_couplers_to_auto_us_AWADDR),
.s_axi_awburst(s00_couplers_to_auto_us_AWBURST),
.s_axi_awcache(s00_couplers_to_auto_us_AWCACHE),
.s_axi_awlen(s00_couplers_to_auto_us_AWLEN),
.s_axi_awlock(1'b0),
.s_axi_awprot(s00_couplers_to_auto_us_AWPROT),
.s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(s00_couplers_to_auto_us_AWREADY),
.s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awsize(s00_couplers_to_auto_us_AWSIZE),
.s_axi_awvalid(s00_couplers_to_auto_us_AWVALID),
.s_axi_bready(s00_couplers_to_auto_us_BREADY),
.s_axi_bresp(s00_couplers_to_auto_us_BRESP),
.s_axi_bvalid(s00_couplers_to_auto_us_BVALID),
.s_axi_rdata(s00_couplers_to_auto_us_RDATA),
.s_axi_rlast(s00_couplers_to_auto_us_RLAST),
.s_axi_rready(s00_couplers_to_auto_us_RREADY),
.s_axi_rresp(s00_couplers_to_auto_us_RRESP),
.s_axi_rvalid(s00_couplers_to_auto_us_RVALID),
.s_axi_wdata(s00_couplers_to_auto_us_WDATA),
.s_axi_wlast(s00_couplers_to_auto_us_WLAST),
.s_axi_wready(s00_couplers_to_auto_us_WREADY),
.s_axi_wstrb(s00_couplers_to_auto_us_WSTRB),
.s_axi_wvalid(s00_couplers_to_auto_us_WVALID));
endmodule
module s00_couplers_imp_1CFO1MB
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arprot,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awprot,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arid,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awid,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rid,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wid,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input M_ARESETN;
output [31:0]M_AXI_araddr;
output [2:0]M_AXI_arprot;
input M_AXI_arready;
output M_AXI_arvalid;
output [31:0]M_AXI_awaddr;
output [2:0]M_AXI_awprot;
input M_AXI_awready;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [11:0]S_AXI_arid;
input [3:0]S_AXI_arlen;
input [1:0]S_AXI_arlock;
input [2:0]S_AXI_arprot;
input [3:0]S_AXI_arqos;
output S_AXI_arready;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [11:0]S_AXI_awid;
input [3:0]S_AXI_awlen;
input [1:0]S_AXI_awlock;
input [2:0]S_AXI_awprot;
input [3:0]S_AXI_awqos;
output S_AXI_awready;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
output [11:0]S_AXI_bid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
output [11:0]S_AXI_rid;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
input [11:0]S_AXI_wid;
input S_AXI_wlast;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire S_ACLK_1;
wire S_ARESETN_1;
wire [31:0]auto_pc_to_s00_couplers_ARADDR;
wire [2:0]auto_pc_to_s00_couplers_ARPROT;
wire auto_pc_to_s00_couplers_ARREADY;
wire auto_pc_to_s00_couplers_ARVALID;
wire [31:0]auto_pc_to_s00_couplers_AWADDR;
wire [2:0]auto_pc_to_s00_couplers_AWPROT;
wire auto_pc_to_s00_couplers_AWREADY;
wire auto_pc_to_s00_couplers_AWVALID;
wire auto_pc_to_s00_couplers_BREADY;
wire [1:0]auto_pc_to_s00_couplers_BRESP;
wire auto_pc_to_s00_couplers_BVALID;
wire [31:0]auto_pc_to_s00_couplers_RDATA;
wire auto_pc_to_s00_couplers_RREADY;
wire [1:0]auto_pc_to_s00_couplers_RRESP;
wire auto_pc_to_s00_couplers_RVALID;
wire [31:0]auto_pc_to_s00_couplers_WDATA;
wire auto_pc_to_s00_couplers_WREADY;
wire [3:0]auto_pc_to_s00_couplers_WSTRB;
wire auto_pc_to_s00_couplers_WVALID;
wire [31:0]s00_couplers_to_auto_pc_ARADDR;
wire [1:0]s00_couplers_to_auto_pc_ARBURST;
wire [3:0]s00_couplers_to_auto_pc_ARCACHE;
wire [11:0]s00_couplers_to_auto_pc_ARID;
wire [3:0]s00_couplers_to_auto_pc_ARLEN;
wire [1:0]s00_couplers_to_auto_pc_ARLOCK;
wire [2:0]s00_couplers_to_auto_pc_ARPROT;
wire [3:0]s00_couplers_to_auto_pc_ARQOS;
wire s00_couplers_to_auto_pc_ARREADY;
wire [2:0]s00_couplers_to_auto_pc_ARSIZE;
wire s00_couplers_to_auto_pc_ARVALID;
wire [31:0]s00_couplers_to_auto_pc_AWADDR;
wire [1:0]s00_couplers_to_auto_pc_AWBURST;
wire [3:0]s00_couplers_to_auto_pc_AWCACHE;
wire [11:0]s00_couplers_to_auto_pc_AWID;
wire [3:0]s00_couplers_to_auto_pc_AWLEN;
wire [1:0]s00_couplers_to_auto_pc_AWLOCK;
wire [2:0]s00_couplers_to_auto_pc_AWPROT;
wire [3:0]s00_couplers_to_auto_pc_AWQOS;
wire s00_couplers_to_auto_pc_AWREADY;
wire [2:0]s00_couplers_to_auto_pc_AWSIZE;
wire s00_couplers_to_auto_pc_AWVALID;
wire [11:0]s00_couplers_to_auto_pc_BID;
wire s00_couplers_to_auto_pc_BREADY;
wire [1:0]s00_couplers_to_auto_pc_BRESP;
wire s00_couplers_to_auto_pc_BVALID;
wire [31:0]s00_couplers_to_auto_pc_RDATA;
wire [11:0]s00_couplers_to_auto_pc_RID;
wire s00_couplers_to_auto_pc_RLAST;
wire s00_couplers_to_auto_pc_RREADY;
wire [1:0]s00_couplers_to_auto_pc_RRESP;
wire s00_couplers_to_auto_pc_RVALID;
wire [31:0]s00_couplers_to_auto_pc_WDATA;
wire [11:0]s00_couplers_to_auto_pc_WID;
wire s00_couplers_to_auto_pc_WLAST;
wire s00_couplers_to_auto_pc_WREADY;
wire [3:0]s00_couplers_to_auto_pc_WSTRB;
wire s00_couplers_to_auto_pc_WVALID;
assign M_AXI_araddr[31:0] = auto_pc_to_s00_couplers_ARADDR;
assign M_AXI_arprot[2:0] = auto_pc_to_s00_couplers_ARPROT;
assign M_AXI_arvalid = auto_pc_to_s00_couplers_ARVALID;
assign M_AXI_awaddr[31:0] = auto_pc_to_s00_couplers_AWADDR;
assign M_AXI_awprot[2:0] = auto_pc_to_s00_couplers_AWPROT;
assign M_AXI_awvalid = auto_pc_to_s00_couplers_AWVALID;
assign M_AXI_bready = auto_pc_to_s00_couplers_BREADY;
assign M_AXI_rready = auto_pc_to_s00_couplers_RREADY;
assign M_AXI_wdata[31:0] = auto_pc_to_s00_couplers_WDATA;
assign M_AXI_wstrb[3:0] = auto_pc_to_s00_couplers_WSTRB;
assign M_AXI_wvalid = auto_pc_to_s00_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN;
assign S_AXI_arready = s00_couplers_to_auto_pc_ARREADY;
assign S_AXI_awready = s00_couplers_to_auto_pc_AWREADY;
assign S_AXI_bid[11:0] = s00_couplers_to_auto_pc_BID;
assign S_AXI_bresp[1:0] = s00_couplers_to_auto_pc_BRESP;
assign S_AXI_bvalid = s00_couplers_to_auto_pc_BVALID;
assign S_AXI_rdata[31:0] = s00_couplers_to_auto_pc_RDATA;
assign S_AXI_rid[11:0] = s00_couplers_to_auto_pc_RID;
assign S_AXI_rlast = s00_couplers_to_auto_pc_RLAST;
assign S_AXI_rresp[1:0] = s00_couplers_to_auto_pc_RRESP;
assign S_AXI_rvalid = s00_couplers_to_auto_pc_RVALID;
assign S_AXI_wready = s00_couplers_to_auto_pc_WREADY;
assign auto_pc_to_s00_couplers_ARREADY = M_AXI_arready;
assign auto_pc_to_s00_couplers_AWREADY = M_AXI_awready;
assign auto_pc_to_s00_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_pc_to_s00_couplers_BVALID = M_AXI_bvalid;
assign auto_pc_to_s00_couplers_RDATA = M_AXI_rdata[31:0];
assign auto_pc_to_s00_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_pc_to_s00_couplers_RVALID = M_AXI_rvalid;
assign auto_pc_to_s00_couplers_WREADY = M_AXI_wready;
assign s00_couplers_to_auto_pc_ARADDR = S_AXI_araddr[31:0];
assign s00_couplers_to_auto_pc_ARBURST = S_AXI_arburst[1:0];
assign s00_couplers_to_auto_pc_ARCACHE = S_AXI_arcache[3:0];
assign s00_couplers_to_auto_pc_ARID = S_AXI_arid[11:0];
assign s00_couplers_to_auto_pc_ARLEN = S_AXI_arlen[3:0];
assign s00_couplers_to_auto_pc_ARLOCK = S_AXI_arlock[1:0];
assign s00_couplers_to_auto_pc_ARPROT = S_AXI_arprot[2:0];
assign s00_couplers_to_auto_pc_ARQOS = S_AXI_arqos[3:0];
assign s00_couplers_to_auto_pc_ARSIZE = S_AXI_arsize[2:0];
assign s00_couplers_to_auto_pc_ARVALID = S_AXI_arvalid;
assign s00_couplers_to_auto_pc_AWADDR = S_AXI_awaddr[31:0];
assign s00_couplers_to_auto_pc_AWBURST = S_AXI_awburst[1:0];
assign s00_couplers_to_auto_pc_AWCACHE = S_AXI_awcache[3:0];
assign s00_couplers_to_auto_pc_AWID = S_AXI_awid[11:0];
assign s00_couplers_to_auto_pc_AWLEN = S_AXI_awlen[3:0];
assign s00_couplers_to_auto_pc_AWLOCK = S_AXI_awlock[1:0];
assign s00_couplers_to_auto_pc_AWPROT = S_AXI_awprot[2:0];
assign s00_couplers_to_auto_pc_AWQOS = S_AXI_awqos[3:0];
assign s00_couplers_to_auto_pc_AWSIZE = S_AXI_awsize[2:0];
assign s00_couplers_to_auto_pc_AWVALID = S_AXI_awvalid;
assign s00_couplers_to_auto_pc_BREADY = S_AXI_bready;
assign s00_couplers_to_auto_pc_RREADY = S_AXI_rready;
assign s00_couplers_to_auto_pc_WDATA = S_AXI_wdata[31:0];
assign s00_couplers_to_auto_pc_WID = S_AXI_wid[11:0];
assign s00_couplers_to_auto_pc_WLAST = S_AXI_wlast;
assign s00_couplers_to_auto_pc_WSTRB = S_AXI_wstrb[3:0];
assign s00_couplers_to_auto_pc_WVALID = S_AXI_wvalid;
design_1_auto_pc_3 auto_pc
(.aclk(S_ACLK_1),
.aresetn(S_ARESETN_1),
.m_axi_araddr(auto_pc_to_s00_couplers_ARADDR),
.m_axi_arprot(auto_pc_to_s00_couplers_ARPROT),
.m_axi_arready(auto_pc_to_s00_couplers_ARREADY),
.m_axi_arvalid(auto_pc_to_s00_couplers_ARVALID),
.m_axi_awaddr(auto_pc_to_s00_couplers_AWADDR),
.m_axi_awprot(auto_pc_to_s00_couplers_AWPROT),
.m_axi_awready(auto_pc_to_s00_couplers_AWREADY),
.m_axi_awvalid(auto_pc_to_s00_couplers_AWVALID),
.m_axi_bready(auto_pc_to_s00_couplers_BREADY),
.m_axi_bresp(auto_pc_to_s00_couplers_BRESP),
.m_axi_bvalid(auto_pc_to_s00_couplers_BVALID),
.m_axi_rdata(auto_pc_to_s00_couplers_RDATA),
.m_axi_rready(auto_pc_to_s00_couplers_RREADY),
.m_axi_rresp(auto_pc_to_s00_couplers_RRESP),
.m_axi_rvalid(auto_pc_to_s00_couplers_RVALID),
.m_axi_wdata(auto_pc_to_s00_couplers_WDATA),
.m_axi_wready(auto_pc_to_s00_couplers_WREADY),
.m_axi_wstrb(auto_pc_to_s00_couplers_WSTRB),
.m_axi_wvalid(auto_pc_to_s00_couplers_WVALID),
.s_axi_araddr(s00_couplers_to_auto_pc_ARADDR),
.s_axi_arburst(s00_couplers_to_auto_pc_ARBURST),
.s_axi_arcache(s00_couplers_to_auto_pc_ARCACHE),
.s_axi_arid(s00_couplers_to_auto_pc_ARID),
.s_axi_arlen(s00_couplers_to_auto_pc_ARLEN),
.s_axi_arlock(s00_couplers_to_auto_pc_ARLOCK),
.s_axi_arprot(s00_couplers_to_auto_pc_ARPROT),
.s_axi_arqos(s00_couplers_to_auto_pc_ARQOS),
.s_axi_arready(s00_couplers_to_auto_pc_ARREADY),
.s_axi_arsize(s00_couplers_to_auto_pc_ARSIZE),
.s_axi_arvalid(s00_couplers_to_auto_pc_ARVALID),
.s_axi_awaddr(s00_couplers_to_auto_pc_AWADDR),
.s_axi_awburst(s00_couplers_to_auto_pc_AWBURST),
.s_axi_awcache(s00_couplers_to_auto_pc_AWCACHE),
.s_axi_awid(s00_couplers_to_auto_pc_AWID),
.s_axi_awlen(s00_couplers_to_auto_pc_AWLEN),
.s_axi_awlock(s00_couplers_to_auto_pc_AWLOCK),
.s_axi_awprot(s00_couplers_to_auto_pc_AWPROT),
.s_axi_awqos(s00_couplers_to_auto_pc_AWQOS),
.s_axi_awready(s00_couplers_to_auto_pc_AWREADY),
.s_axi_awsize(s00_couplers_to_auto_pc_AWSIZE),
.s_axi_awvalid(s00_couplers_to_auto_pc_AWVALID),
.s_axi_bid(s00_couplers_to_auto_pc_BID),
.s_axi_bready(s00_couplers_to_auto_pc_BREADY),
.s_axi_bresp(s00_couplers_to_auto_pc_BRESP),
.s_axi_bvalid(s00_couplers_to_auto_pc_BVALID),
.s_axi_rdata(s00_couplers_to_auto_pc_RDATA),
.s_axi_rid(s00_couplers_to_auto_pc_RID),
.s_axi_rlast(s00_couplers_to_auto_pc_RLAST),
.s_axi_rready(s00_couplers_to_auto_pc_RREADY),
.s_axi_rresp(s00_couplers_to_auto_pc_RRESP),
.s_axi_rvalid(s00_couplers_to_auto_pc_RVALID),
.s_axi_wdata(s00_couplers_to_auto_pc_WDATA),
.s_axi_wid(s00_couplers_to_auto_pc_WID),
.s_axi_wlast(s00_couplers_to_auto_pc_WLAST),
.s_axi_wready(s00_couplers_to_auto_pc_WREADY),
.s_axi_wstrb(s00_couplers_to_auto_pc_WSTRB),
.s_axi_wvalid(s00_couplers_to_auto_pc_WVALID));
endmodule
module s00_couplers_imp_EIRLJN
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arburst,
M_AXI_arcache,
M_AXI_arlen,
M_AXI_arlock,
M_AXI_arprot,
M_AXI_arqos,
M_AXI_arready,
M_AXI_arsize,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awburst,
M_AXI_awcache,
M_AXI_awlen,
M_AXI_awlock,
M_AXI_awprot,
M_AXI_awqos,
M_AXI_awready,
M_AXI_awsize,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rlast,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wlast,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arlen,
S_AXI_arprot,
S_AXI_arready,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awlen,
S_AXI_awprot,
S_AXI_awready,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input M_ARESETN;
output [31:0]M_AXI_araddr;
output [1:0]M_AXI_arburst;
output [3:0]M_AXI_arcache;
output [7:0]M_AXI_arlen;
output [0:0]M_AXI_arlock;
output [2:0]M_AXI_arprot;
output [3:0]M_AXI_arqos;
input M_AXI_arready;
output [2:0]M_AXI_arsize;
output M_AXI_arvalid;
output [31:0]M_AXI_awaddr;
output [1:0]M_AXI_awburst;
output [3:0]M_AXI_awcache;
output [7:0]M_AXI_awlen;
output [0:0]M_AXI_awlock;
output [2:0]M_AXI_awprot;
output [3:0]M_AXI_awqos;
input M_AXI_awready;
output [2:0]M_AXI_awsize;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [63:0]M_AXI_rdata;
input M_AXI_rlast;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [63:0]M_AXI_wdata;
output M_AXI_wlast;
input M_AXI_wready;
output [7:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [7:0]S_AXI_arlen;
input [2:0]S_AXI_arprot;
output S_AXI_arready;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [7:0]S_AXI_awlen;
input [2:0]S_AXI_awprot;
output S_AXI_awready;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
input S_AXI_wlast;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire S_ACLK_1;
wire S_ARESETN_1;
wire [31:0]auto_us_to_s00_couplers_ARADDR;
wire [1:0]auto_us_to_s00_couplers_ARBURST;
wire [3:0]auto_us_to_s00_couplers_ARCACHE;
wire [7:0]auto_us_to_s00_couplers_ARLEN;
wire [0:0]auto_us_to_s00_couplers_ARLOCK;
wire [2:0]auto_us_to_s00_couplers_ARPROT;
wire [3:0]auto_us_to_s00_couplers_ARQOS;
wire auto_us_to_s00_couplers_ARREADY;
wire [2:0]auto_us_to_s00_couplers_ARSIZE;
wire auto_us_to_s00_couplers_ARVALID;
wire [31:0]auto_us_to_s00_couplers_AWADDR;
wire [1:0]auto_us_to_s00_couplers_AWBURST;
wire [3:0]auto_us_to_s00_couplers_AWCACHE;
wire [7:0]auto_us_to_s00_couplers_AWLEN;
wire [0:0]auto_us_to_s00_couplers_AWLOCK;
wire [2:0]auto_us_to_s00_couplers_AWPROT;
wire [3:0]auto_us_to_s00_couplers_AWQOS;
wire auto_us_to_s00_couplers_AWREADY;
wire [2:0]auto_us_to_s00_couplers_AWSIZE;
wire auto_us_to_s00_couplers_AWVALID;
wire auto_us_to_s00_couplers_BREADY;
wire [1:0]auto_us_to_s00_couplers_BRESP;
wire auto_us_to_s00_couplers_BVALID;
wire [63:0]auto_us_to_s00_couplers_RDATA;
wire auto_us_to_s00_couplers_RLAST;
wire auto_us_to_s00_couplers_RREADY;
wire [1:0]auto_us_to_s00_couplers_RRESP;
wire auto_us_to_s00_couplers_RVALID;
wire [63:0]auto_us_to_s00_couplers_WDATA;
wire auto_us_to_s00_couplers_WLAST;
wire auto_us_to_s00_couplers_WREADY;
wire [7:0]auto_us_to_s00_couplers_WSTRB;
wire auto_us_to_s00_couplers_WVALID;
wire [31:0]s00_couplers_to_auto_us_ARADDR;
wire [1:0]s00_couplers_to_auto_us_ARBURST;
wire [3:0]s00_couplers_to_auto_us_ARCACHE;
wire [7:0]s00_couplers_to_auto_us_ARLEN;
wire [2:0]s00_couplers_to_auto_us_ARPROT;
wire s00_couplers_to_auto_us_ARREADY;
wire [2:0]s00_couplers_to_auto_us_ARSIZE;
wire s00_couplers_to_auto_us_ARVALID;
wire [31:0]s00_couplers_to_auto_us_AWADDR;
wire [1:0]s00_couplers_to_auto_us_AWBURST;
wire [3:0]s00_couplers_to_auto_us_AWCACHE;
wire [7:0]s00_couplers_to_auto_us_AWLEN;
wire [2:0]s00_couplers_to_auto_us_AWPROT;
wire s00_couplers_to_auto_us_AWREADY;
wire [2:0]s00_couplers_to_auto_us_AWSIZE;
wire s00_couplers_to_auto_us_AWVALID;
wire s00_couplers_to_auto_us_BREADY;
wire [1:0]s00_couplers_to_auto_us_BRESP;
wire s00_couplers_to_auto_us_BVALID;
wire [31:0]s00_couplers_to_auto_us_RDATA;
wire s00_couplers_to_auto_us_RLAST;
wire s00_couplers_to_auto_us_RREADY;
wire [1:0]s00_couplers_to_auto_us_RRESP;
wire s00_couplers_to_auto_us_RVALID;
wire [31:0]s00_couplers_to_auto_us_WDATA;
wire s00_couplers_to_auto_us_WLAST;
wire s00_couplers_to_auto_us_WREADY;
wire [3:0]s00_couplers_to_auto_us_WSTRB;
wire s00_couplers_to_auto_us_WVALID;
assign M_AXI_araddr[31:0] = auto_us_to_s00_couplers_ARADDR;
assign M_AXI_arburst[1:0] = auto_us_to_s00_couplers_ARBURST;
assign M_AXI_arcache[3:0] = auto_us_to_s00_couplers_ARCACHE;
assign M_AXI_arlen[7:0] = auto_us_to_s00_couplers_ARLEN;
assign M_AXI_arlock[0] = auto_us_to_s00_couplers_ARLOCK;
assign M_AXI_arprot[2:0] = auto_us_to_s00_couplers_ARPROT;
assign M_AXI_arqos[3:0] = auto_us_to_s00_couplers_ARQOS;
assign M_AXI_arsize[2:0] = auto_us_to_s00_couplers_ARSIZE;
assign M_AXI_arvalid = auto_us_to_s00_couplers_ARVALID;
assign M_AXI_awaddr[31:0] = auto_us_to_s00_couplers_AWADDR;
assign M_AXI_awburst[1:0] = auto_us_to_s00_couplers_AWBURST;
assign M_AXI_awcache[3:0] = auto_us_to_s00_couplers_AWCACHE;
assign M_AXI_awlen[7:0] = auto_us_to_s00_couplers_AWLEN;
assign M_AXI_awlock[0] = auto_us_to_s00_couplers_AWLOCK;
assign M_AXI_awprot[2:0] = auto_us_to_s00_couplers_AWPROT;
assign M_AXI_awqos[3:0] = auto_us_to_s00_couplers_AWQOS;
assign M_AXI_awsize[2:0] = auto_us_to_s00_couplers_AWSIZE;
assign M_AXI_awvalid = auto_us_to_s00_couplers_AWVALID;
assign M_AXI_bready = auto_us_to_s00_couplers_BREADY;
assign M_AXI_rready = auto_us_to_s00_couplers_RREADY;
assign M_AXI_wdata[63:0] = auto_us_to_s00_couplers_WDATA;
assign M_AXI_wlast = auto_us_to_s00_couplers_WLAST;
assign M_AXI_wstrb[7:0] = auto_us_to_s00_couplers_WSTRB;
assign M_AXI_wvalid = auto_us_to_s00_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN;
assign S_AXI_arready = s00_couplers_to_auto_us_ARREADY;
assign S_AXI_awready = s00_couplers_to_auto_us_AWREADY;
assign S_AXI_bresp[1:0] = s00_couplers_to_auto_us_BRESP;
assign S_AXI_bvalid = s00_couplers_to_auto_us_BVALID;
assign S_AXI_rdata[31:0] = s00_couplers_to_auto_us_RDATA;
assign S_AXI_rlast = s00_couplers_to_auto_us_RLAST;
assign S_AXI_rresp[1:0] = s00_couplers_to_auto_us_RRESP;
assign S_AXI_rvalid = s00_couplers_to_auto_us_RVALID;
assign S_AXI_wready = s00_couplers_to_auto_us_WREADY;
assign auto_us_to_s00_couplers_ARREADY = M_AXI_arready;
assign auto_us_to_s00_couplers_AWREADY = M_AXI_awready;
assign auto_us_to_s00_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_us_to_s00_couplers_BVALID = M_AXI_bvalid;
assign auto_us_to_s00_couplers_RDATA = M_AXI_rdata[63:0];
assign auto_us_to_s00_couplers_RLAST = M_AXI_rlast;
assign auto_us_to_s00_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_us_to_s00_couplers_RVALID = M_AXI_rvalid;
assign auto_us_to_s00_couplers_WREADY = M_AXI_wready;
assign s00_couplers_to_auto_us_ARADDR = S_AXI_araddr[31:0];
assign s00_couplers_to_auto_us_ARBURST = S_AXI_arburst[1:0];
assign s00_couplers_to_auto_us_ARCACHE = S_AXI_arcache[3:0];
assign s00_couplers_to_auto_us_ARLEN = S_AXI_arlen[7:0];
assign s00_couplers_to_auto_us_ARPROT = S_AXI_arprot[2:0];
assign s00_couplers_to_auto_us_ARSIZE = S_AXI_arsize[2:0];
assign s00_couplers_to_auto_us_ARVALID = S_AXI_arvalid;
assign s00_couplers_to_auto_us_AWADDR = S_AXI_awaddr[31:0];
assign s00_couplers_to_auto_us_AWBURST = S_AXI_awburst[1:0];
assign s00_couplers_to_auto_us_AWCACHE = S_AXI_awcache[3:0];
assign s00_couplers_to_auto_us_AWLEN = S_AXI_awlen[7:0];
assign s00_couplers_to_auto_us_AWPROT = S_AXI_awprot[2:0];
assign s00_couplers_to_auto_us_AWSIZE = S_AXI_awsize[2:0];
assign s00_couplers_to_auto_us_AWVALID = S_AXI_awvalid;
assign s00_couplers_to_auto_us_BREADY = S_AXI_bready;
assign s00_couplers_to_auto_us_RREADY = S_AXI_rready;
assign s00_couplers_to_auto_us_WDATA = S_AXI_wdata[31:0];
assign s00_couplers_to_auto_us_WLAST = S_AXI_wlast;
assign s00_couplers_to_auto_us_WSTRB = S_AXI_wstrb[3:0];
assign s00_couplers_to_auto_us_WVALID = S_AXI_wvalid;
design_1_auto_us_0 auto_us
(.m_axi_araddr(auto_us_to_s00_couplers_ARADDR),
.m_axi_arburst(auto_us_to_s00_couplers_ARBURST),
.m_axi_arcache(auto_us_to_s00_couplers_ARCACHE),
.m_axi_arlen(auto_us_to_s00_couplers_ARLEN),
.m_axi_arlock(auto_us_to_s00_couplers_ARLOCK),
.m_axi_arprot(auto_us_to_s00_couplers_ARPROT),
.m_axi_arqos(auto_us_to_s00_couplers_ARQOS),
.m_axi_arready(auto_us_to_s00_couplers_ARREADY),
.m_axi_arsize(auto_us_to_s00_couplers_ARSIZE),
.m_axi_arvalid(auto_us_to_s00_couplers_ARVALID),
.m_axi_awaddr(auto_us_to_s00_couplers_AWADDR),
.m_axi_awburst(auto_us_to_s00_couplers_AWBURST),
.m_axi_awcache(auto_us_to_s00_couplers_AWCACHE),
.m_axi_awlen(auto_us_to_s00_couplers_AWLEN),
.m_axi_awlock(auto_us_to_s00_couplers_AWLOCK),
.m_axi_awprot(auto_us_to_s00_couplers_AWPROT),
.m_axi_awqos(auto_us_to_s00_couplers_AWQOS),
.m_axi_awready(auto_us_to_s00_couplers_AWREADY),
.m_axi_awsize(auto_us_to_s00_couplers_AWSIZE),
.m_axi_awvalid(auto_us_to_s00_couplers_AWVALID),
.m_axi_bready(auto_us_to_s00_couplers_BREADY),
.m_axi_bresp(auto_us_to_s00_couplers_BRESP),
.m_axi_bvalid(auto_us_to_s00_couplers_BVALID),
.m_axi_rdata(auto_us_to_s00_couplers_RDATA),
.m_axi_rlast(auto_us_to_s00_couplers_RLAST),
.m_axi_rready(auto_us_to_s00_couplers_RREADY),
.m_axi_rresp(auto_us_to_s00_couplers_RRESP),
.m_axi_rvalid(auto_us_to_s00_couplers_RVALID),
.m_axi_wdata(auto_us_to_s00_couplers_WDATA),
.m_axi_wlast(auto_us_to_s00_couplers_WLAST),
.m_axi_wready(auto_us_to_s00_couplers_WREADY),
.m_axi_wstrb(auto_us_to_s00_couplers_WSTRB),
.m_axi_wvalid(auto_us_to_s00_couplers_WVALID),
.s_axi_aclk(S_ACLK_1),
.s_axi_araddr(s00_couplers_to_auto_us_ARADDR),
.s_axi_arburst(s00_couplers_to_auto_us_ARBURST),
.s_axi_arcache(s00_couplers_to_auto_us_ARCACHE),
.s_axi_aresetn(S_ARESETN_1),
.s_axi_arlen(s00_couplers_to_auto_us_ARLEN),
.s_axi_arlock(1'b0),
.s_axi_arprot(s00_couplers_to_auto_us_ARPROT),
.s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(s00_couplers_to_auto_us_ARREADY),
.s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arsize(s00_couplers_to_auto_us_ARSIZE),
.s_axi_arvalid(s00_couplers_to_auto_us_ARVALID),
.s_axi_awaddr(s00_couplers_to_auto_us_AWADDR),
.s_axi_awburst(s00_couplers_to_auto_us_AWBURST),
.s_axi_awcache(s00_couplers_to_auto_us_AWCACHE),
.s_axi_awlen(s00_couplers_to_auto_us_AWLEN),
.s_axi_awlock(1'b0),
.s_axi_awprot(s00_couplers_to_auto_us_AWPROT),
.s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(s00_couplers_to_auto_us_AWREADY),
.s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awsize(s00_couplers_to_auto_us_AWSIZE),
.s_axi_awvalid(s00_couplers_to_auto_us_AWVALID),
.s_axi_bready(s00_couplers_to_auto_us_BREADY),
.s_axi_bresp(s00_couplers_to_auto_us_BRESP),
.s_axi_bvalid(s00_couplers_to_auto_us_BVALID),
.s_axi_rdata(s00_couplers_to_auto_us_RDATA),
.s_axi_rlast(s00_couplers_to_auto_us_RLAST),
.s_axi_rready(s00_couplers_to_auto_us_RREADY),
.s_axi_rresp(s00_couplers_to_auto_us_RRESP),
.s_axi_rvalid(s00_couplers_to_auto_us_RVALID),
.s_axi_wdata(s00_couplers_to_auto_us_WDATA),
.s_axi_wlast(s00_couplers_to_auto_us_WLAST),
.s_axi_wready(s00_couplers_to_auto_us_WREADY),
.s_axi_wstrb(s00_couplers_to_auto_us_WSTRB),
.s_axi_wvalid(s00_couplers_to_auto_us_WVALID));
endmodule
module s00_couplers_imp_Y38QRE
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arburst,
M_AXI_arcache,
M_AXI_arlen,
M_AXI_arlock,
M_AXI_arprot,
M_AXI_arqos,
M_AXI_arready,
M_AXI_arsize,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awburst,
M_AXI_awcache,
M_AXI_awlen,
M_AXI_awlock,
M_AXI_awprot,
M_AXI_awqos,
M_AXI_awready,
M_AXI_awsize,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rlast,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wlast,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arlen,
S_AXI_arprot,
S_AXI_arready,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awlen,
S_AXI_awprot,
S_AXI_awready,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input M_ARESETN;
output [31:0]M_AXI_araddr;
output [1:0]M_AXI_arburst;
output [3:0]M_AXI_arcache;
output [7:0]M_AXI_arlen;
output [0:0]M_AXI_arlock;
output [2:0]M_AXI_arprot;
output [3:0]M_AXI_arqos;
input M_AXI_arready;
output [2:0]M_AXI_arsize;
output M_AXI_arvalid;
output [31:0]M_AXI_awaddr;
output [1:0]M_AXI_awburst;
output [3:0]M_AXI_awcache;
output [7:0]M_AXI_awlen;
output [0:0]M_AXI_awlock;
output [2:0]M_AXI_awprot;
output [3:0]M_AXI_awqos;
input M_AXI_awready;
output [2:0]M_AXI_awsize;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [63:0]M_AXI_rdata;
input M_AXI_rlast;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [63:0]M_AXI_wdata;
output M_AXI_wlast;
input M_AXI_wready;
output [7:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [7:0]S_AXI_arlen;
input [2:0]S_AXI_arprot;
output S_AXI_arready;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [7:0]S_AXI_awlen;
input [2:0]S_AXI_awprot;
output S_AXI_awready;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
input S_AXI_wlast;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire S_ACLK_1;
wire S_ARESETN_1;
wire [31:0]auto_us_to_s00_couplers_ARADDR;
wire [1:0]auto_us_to_s00_couplers_ARBURST;
wire [3:0]auto_us_to_s00_couplers_ARCACHE;
wire [7:0]auto_us_to_s00_couplers_ARLEN;
wire [0:0]auto_us_to_s00_couplers_ARLOCK;
wire [2:0]auto_us_to_s00_couplers_ARPROT;
wire [3:0]auto_us_to_s00_couplers_ARQOS;
wire auto_us_to_s00_couplers_ARREADY;
wire [2:0]auto_us_to_s00_couplers_ARSIZE;
wire auto_us_to_s00_couplers_ARVALID;
wire [31:0]auto_us_to_s00_couplers_AWADDR;
wire [1:0]auto_us_to_s00_couplers_AWBURST;
wire [3:0]auto_us_to_s00_couplers_AWCACHE;
wire [7:0]auto_us_to_s00_couplers_AWLEN;
wire [0:0]auto_us_to_s00_couplers_AWLOCK;
wire [2:0]auto_us_to_s00_couplers_AWPROT;
wire [3:0]auto_us_to_s00_couplers_AWQOS;
wire auto_us_to_s00_couplers_AWREADY;
wire [2:0]auto_us_to_s00_couplers_AWSIZE;
wire auto_us_to_s00_couplers_AWVALID;
wire auto_us_to_s00_couplers_BREADY;
wire [1:0]auto_us_to_s00_couplers_BRESP;
wire auto_us_to_s00_couplers_BVALID;
wire [63:0]auto_us_to_s00_couplers_RDATA;
wire auto_us_to_s00_couplers_RLAST;
wire auto_us_to_s00_couplers_RREADY;
wire [1:0]auto_us_to_s00_couplers_RRESP;
wire auto_us_to_s00_couplers_RVALID;
wire [63:0]auto_us_to_s00_couplers_WDATA;
wire auto_us_to_s00_couplers_WLAST;
wire auto_us_to_s00_couplers_WREADY;
wire [7:0]auto_us_to_s00_couplers_WSTRB;
wire auto_us_to_s00_couplers_WVALID;
wire [31:0]s00_couplers_to_auto_us_ARADDR;
wire [1:0]s00_couplers_to_auto_us_ARBURST;
wire [3:0]s00_couplers_to_auto_us_ARCACHE;
wire [7:0]s00_couplers_to_auto_us_ARLEN;
wire [2:0]s00_couplers_to_auto_us_ARPROT;
wire s00_couplers_to_auto_us_ARREADY;
wire [2:0]s00_couplers_to_auto_us_ARSIZE;
wire s00_couplers_to_auto_us_ARVALID;
wire [31:0]s00_couplers_to_auto_us_AWADDR;
wire [1:0]s00_couplers_to_auto_us_AWBURST;
wire [3:0]s00_couplers_to_auto_us_AWCACHE;
wire [7:0]s00_couplers_to_auto_us_AWLEN;
wire [2:0]s00_couplers_to_auto_us_AWPROT;
wire s00_couplers_to_auto_us_AWREADY;
wire [2:0]s00_couplers_to_auto_us_AWSIZE;
wire s00_couplers_to_auto_us_AWVALID;
wire s00_couplers_to_auto_us_BREADY;
wire [1:0]s00_couplers_to_auto_us_BRESP;
wire s00_couplers_to_auto_us_BVALID;
wire [31:0]s00_couplers_to_auto_us_RDATA;
wire s00_couplers_to_auto_us_RLAST;
wire s00_couplers_to_auto_us_RREADY;
wire [1:0]s00_couplers_to_auto_us_RRESP;
wire s00_couplers_to_auto_us_RVALID;
wire [31:0]s00_couplers_to_auto_us_WDATA;
wire s00_couplers_to_auto_us_WLAST;
wire s00_couplers_to_auto_us_WREADY;
wire [3:0]s00_couplers_to_auto_us_WSTRB;
wire s00_couplers_to_auto_us_WVALID;
assign M_AXI_araddr[31:0] = auto_us_to_s00_couplers_ARADDR;
assign M_AXI_arburst[1:0] = auto_us_to_s00_couplers_ARBURST;
assign M_AXI_arcache[3:0] = auto_us_to_s00_couplers_ARCACHE;
assign M_AXI_arlen[7:0] = auto_us_to_s00_couplers_ARLEN;
assign M_AXI_arlock[0] = auto_us_to_s00_couplers_ARLOCK;
assign M_AXI_arprot[2:0] = auto_us_to_s00_couplers_ARPROT;
assign M_AXI_arqos[3:0] = auto_us_to_s00_couplers_ARQOS;
assign M_AXI_arsize[2:0] = auto_us_to_s00_couplers_ARSIZE;
assign M_AXI_arvalid = auto_us_to_s00_couplers_ARVALID;
assign M_AXI_awaddr[31:0] = auto_us_to_s00_couplers_AWADDR;
assign M_AXI_awburst[1:0] = auto_us_to_s00_couplers_AWBURST;
assign M_AXI_awcache[3:0] = auto_us_to_s00_couplers_AWCACHE;
assign M_AXI_awlen[7:0] = auto_us_to_s00_couplers_AWLEN;
assign M_AXI_awlock[0] = auto_us_to_s00_couplers_AWLOCK;
assign M_AXI_awprot[2:0] = auto_us_to_s00_couplers_AWPROT;
assign M_AXI_awqos[3:0] = auto_us_to_s00_couplers_AWQOS;
assign M_AXI_awsize[2:0] = auto_us_to_s00_couplers_AWSIZE;
assign M_AXI_awvalid = auto_us_to_s00_couplers_AWVALID;
assign M_AXI_bready = auto_us_to_s00_couplers_BREADY;
assign M_AXI_rready = auto_us_to_s00_couplers_RREADY;
assign M_AXI_wdata[63:0] = auto_us_to_s00_couplers_WDATA;
assign M_AXI_wlast = auto_us_to_s00_couplers_WLAST;
assign M_AXI_wstrb[7:0] = auto_us_to_s00_couplers_WSTRB;
assign M_AXI_wvalid = auto_us_to_s00_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN;
assign S_AXI_arready = s00_couplers_to_auto_us_ARREADY;
assign S_AXI_awready = s00_couplers_to_auto_us_AWREADY;
assign S_AXI_bresp[1:0] = s00_couplers_to_auto_us_BRESP;
assign S_AXI_bvalid = s00_couplers_to_auto_us_BVALID;
assign S_AXI_rdata[31:0] = s00_couplers_to_auto_us_RDATA;
assign S_AXI_rlast = s00_couplers_to_auto_us_RLAST;
assign S_AXI_rresp[1:0] = s00_couplers_to_auto_us_RRESP;
assign S_AXI_rvalid = s00_couplers_to_auto_us_RVALID;
assign S_AXI_wready = s00_couplers_to_auto_us_WREADY;
assign auto_us_to_s00_couplers_ARREADY = M_AXI_arready;
assign auto_us_to_s00_couplers_AWREADY = M_AXI_awready;
assign auto_us_to_s00_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_us_to_s00_couplers_BVALID = M_AXI_bvalid;
assign auto_us_to_s00_couplers_RDATA = M_AXI_rdata[63:0];
assign auto_us_to_s00_couplers_RLAST = M_AXI_rlast;
assign auto_us_to_s00_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_us_to_s00_couplers_RVALID = M_AXI_rvalid;
assign auto_us_to_s00_couplers_WREADY = M_AXI_wready;
assign s00_couplers_to_auto_us_ARADDR = S_AXI_araddr[31:0];
assign s00_couplers_to_auto_us_ARBURST = S_AXI_arburst[1:0];
assign s00_couplers_to_auto_us_ARCACHE = S_AXI_arcache[3:0];
assign s00_couplers_to_auto_us_ARLEN = S_AXI_arlen[7:0];
assign s00_couplers_to_auto_us_ARPROT = S_AXI_arprot[2:0];
assign s00_couplers_to_auto_us_ARSIZE = S_AXI_arsize[2:0];
assign s00_couplers_to_auto_us_ARVALID = S_AXI_arvalid;
assign s00_couplers_to_auto_us_AWADDR = S_AXI_awaddr[31:0];
assign s00_couplers_to_auto_us_AWBURST = S_AXI_awburst[1:0];
assign s00_couplers_to_auto_us_AWCACHE = S_AXI_awcache[3:0];
assign s00_couplers_to_auto_us_AWLEN = S_AXI_awlen[7:0];
assign s00_couplers_to_auto_us_AWPROT = S_AXI_awprot[2:0];
assign s00_couplers_to_auto_us_AWSIZE = S_AXI_awsize[2:0];
assign s00_couplers_to_auto_us_AWVALID = S_AXI_awvalid;
assign s00_couplers_to_auto_us_BREADY = S_AXI_bready;
assign s00_couplers_to_auto_us_RREADY = S_AXI_rready;
assign s00_couplers_to_auto_us_WDATA = S_AXI_wdata[31:0];
assign s00_couplers_to_auto_us_WLAST = S_AXI_wlast;
assign s00_couplers_to_auto_us_WSTRB = S_AXI_wstrb[3:0];
assign s00_couplers_to_auto_us_WVALID = S_AXI_wvalid;
design_1_auto_us_1 auto_us
(.m_axi_araddr(auto_us_to_s00_couplers_ARADDR),
.m_axi_arburst(auto_us_to_s00_couplers_ARBURST),
.m_axi_arcache(auto_us_to_s00_couplers_ARCACHE),
.m_axi_arlen(auto_us_to_s00_couplers_ARLEN),
.m_axi_arlock(auto_us_to_s00_couplers_ARLOCK),
.m_axi_arprot(auto_us_to_s00_couplers_ARPROT),
.m_axi_arqos(auto_us_to_s00_couplers_ARQOS),
.m_axi_arready(auto_us_to_s00_couplers_ARREADY),
.m_axi_arsize(auto_us_to_s00_couplers_ARSIZE),
.m_axi_arvalid(auto_us_to_s00_couplers_ARVALID),
.m_axi_awaddr(auto_us_to_s00_couplers_AWADDR),
.m_axi_awburst(auto_us_to_s00_couplers_AWBURST),
.m_axi_awcache(auto_us_to_s00_couplers_AWCACHE),
.m_axi_awlen(auto_us_to_s00_couplers_AWLEN),
.m_axi_awlock(auto_us_to_s00_couplers_AWLOCK),
.m_axi_awprot(auto_us_to_s00_couplers_AWPROT),
.m_axi_awqos(auto_us_to_s00_couplers_AWQOS),
.m_axi_awready(auto_us_to_s00_couplers_AWREADY),
.m_axi_awsize(auto_us_to_s00_couplers_AWSIZE),
.m_axi_awvalid(auto_us_to_s00_couplers_AWVALID),
.m_axi_bready(auto_us_to_s00_couplers_BREADY),
.m_axi_bresp(auto_us_to_s00_couplers_BRESP),
.m_axi_bvalid(auto_us_to_s00_couplers_BVALID),
.m_axi_rdata(auto_us_to_s00_couplers_RDATA),
.m_axi_rlast(auto_us_to_s00_couplers_RLAST),
.m_axi_rready(auto_us_to_s00_couplers_RREADY),
.m_axi_rresp(auto_us_to_s00_couplers_RRESP),
.m_axi_rvalid(auto_us_to_s00_couplers_RVALID),
.m_axi_wdata(auto_us_to_s00_couplers_WDATA),
.m_axi_wlast(auto_us_to_s00_couplers_WLAST),
.m_axi_wready(auto_us_to_s00_couplers_WREADY),
.m_axi_wstrb(auto_us_to_s00_couplers_WSTRB),
.m_axi_wvalid(auto_us_to_s00_couplers_WVALID),
.s_axi_aclk(S_ACLK_1),
.s_axi_araddr(s00_couplers_to_auto_us_ARADDR),
.s_axi_arburst(s00_couplers_to_auto_us_ARBURST),
.s_axi_arcache(s00_couplers_to_auto_us_ARCACHE),
.s_axi_aresetn(S_ARESETN_1),
.s_axi_arlen(s00_couplers_to_auto_us_ARLEN),
.s_axi_arlock(1'b0),
.s_axi_arprot(s00_couplers_to_auto_us_ARPROT),
.s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(s00_couplers_to_auto_us_ARREADY),
.s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arsize(s00_couplers_to_auto_us_ARSIZE),
.s_axi_arvalid(s00_couplers_to_auto_us_ARVALID),
.s_axi_awaddr(s00_couplers_to_auto_us_AWADDR),
.s_axi_awburst(s00_couplers_to_auto_us_AWBURST),
.s_axi_awcache(s00_couplers_to_auto_us_AWCACHE),
.s_axi_awlen(s00_couplers_to_auto_us_AWLEN),
.s_axi_awlock(1'b0),
.s_axi_awprot(s00_couplers_to_auto_us_AWPROT),
.s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(s00_couplers_to_auto_us_AWREADY),
.s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awsize(s00_couplers_to_auto_us_AWSIZE),
.s_axi_awvalid(s00_couplers_to_auto_us_AWVALID),
.s_axi_bready(s00_couplers_to_auto_us_BREADY),
.s_axi_bresp(s00_couplers_to_auto_us_BRESP),
.s_axi_bvalid(s00_couplers_to_auto_us_BVALID),
.s_axi_rdata(s00_couplers_to_auto_us_RDATA),
.s_axi_rlast(s00_couplers_to_auto_us_RLAST),
.s_axi_rready(s00_couplers_to_auto_us_RREADY),
.s_axi_rresp(s00_couplers_to_auto_us_RRESP),
.s_axi_rvalid(s00_couplers_to_auto_us_RVALID),
.s_axi_wdata(s00_couplers_to_auto_us_WDATA),
.s_axi_wlast(s00_couplers_to_auto_us_WLAST),
.s_axi_wready(s00_couplers_to_auto_us_WREADY),
.s_axi_wstrb(s00_couplers_to_auto_us_WSTRB),
.s_axi_wvalid(s00_couplers_to_auto_us_WVALID));
endmodule
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// Copyright (c) 2014 Takashi Toyoshima <[email protected]>.
// All rights reserved. Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
module MC6502RegisterFile(
clk,
rst_x,
// InterruptLogic interfaces
il2rf_set_i,
il2rf_set_b,
il2rf_data,
il2rf_set_pcl,
il2rf_set_pch,
il2rf_pushed,
rf2il_s,
rf2il_psr,
rf2il_pc,
// RegisterFile interfaces
mc2rf_fetched,
mc2rf_pushed,
mc2rf_pull,
mc2rf_pc,
mc2rf_set_pc,
mc2rf_psr,
mc2rf_set_psr,
rf2mc_pc,
rf2mc_a,
rf2mc_x,
rf2mc_y,
rf2mc_s,
rf2mc_psr,
// ExecutionController interfaces
ec2rf_c,
ec2rf_set_c,
ec2rf_i,
ec2rf_set_i,
ec2rf_v,
ec2rf_set_v,
ec2rf_d,
ec2rf_set_d,
ec2rf_n,
ec2rf_set_n,
ec2rf_z,
ec2rf_set_z,
ec2rf_data,
ec2rf_set_a,
ec2rf_set_x,
ec2rf_set_y,
ec2rf_set_s,
ec2rf_set_pcl,
ec2rf_set_pch,
rf2ec_pcl,
rf2ec_pch,
rf2ec_a,
rf2ec_x,
rf2ec_y,
rf2ec_c,
rf2ec_d,
rf2ec_n,
rf2ec_v,
rf2ec_z);
input clk;
input rst_x;
input il2rf_set_i;
input il2rf_set_b;
input [ 7:0] il2rf_data;
input il2rf_set_pcl;
input il2rf_set_pch;
input il2rf_pushed;
output [ 7:0] rf2il_s;
output [ 7:0] rf2il_psr;
output [15:0] rf2il_pc;
input mc2rf_fetched;
input mc2rf_pushed;
input mc2rf_pull;
input [15:0] mc2rf_pc;
input mc2rf_set_pc;
input [ 7:0] mc2rf_psr;
input mc2rf_set_psr;
output [15:0] rf2mc_pc;
output [ 7:0] rf2mc_a;
output [ 7:0] rf2mc_x;
output [ 7:0] rf2mc_y;
output [ 7:0] rf2mc_s;
output [ 7:0] rf2mc_psr;
input ec2rf_c;
input ec2rf_set_c;
input ec2rf_i;
input ec2rf_set_i;
input ec2rf_v;
input ec2rf_set_v;
input ec2rf_d;
input ec2rf_set_d;
input ec2rf_n;
input ec2rf_set_n;
input ec2rf_z;
input ec2rf_set_z;
input [ 7:0] ec2rf_data;
input ec2rf_set_a;
input ec2rf_set_x;
input ec2rf_set_y;
input ec2rf_set_s;
input ec2rf_set_pcl;
input ec2rf_set_pch;
output [ 7:0] rf2ec_pcl;
output [ 7:0] rf2ec_pch;
output [ 7:0] rf2ec_a;
output [ 7:0] rf2ec_x;
output [ 7:0] rf2ec_y;
output rf2ec_c;
output rf2ec_d;
output rf2ec_n;
output rf2ec_v;
output rf2ec_z;
reg [ 7:0] r_pcl;
reg [ 7:0] r_pch;
reg [ 7:0] r_a;
reg [ 7:0] r_x;
reg [ 7:0] r_y;
reg [ 7:0] r_sp;
wire w_load_pc;
wire [15:0] w_next_pc;
wire [ 7:0] w_psr;
wire w_c;
wire w_i;
wire w_v;
wire w_d;
wire w_n;
wire w_z;
wire w_b;
wire w_set_c;
wire w_set_i;
wire w_set_v;
wire w_set_d;
wire w_set_n;
wire w_set_z;
wire w_set_b;
assign rf2il_s = r_sp;
assign rf2il_psr = w_psr;
assign rf2il_pc = { r_pch, r_pcl };
assign rf2mc_pc = { r_pch, r_pcl };
assign rf2mc_a = r_a;
assign rf2mc_x = r_x;
assign rf2mc_y = r_y;
assign rf2mc_s = r_sp;
assign rf2mc_psr = w_psr;
assign rf2ec_pcl = r_pcl;
assign rf2ec_pch = r_pch;
assign rf2ec_a = r_a;
assign rf2ec_x = r_x;
assign rf2ec_y = r_y;
assign rf2ec_c = w_psr[0];
assign rf2ec_d = w_psr[3];
assign rf2ec_n = w_psr[7];
assign rf2ec_v = w_psr[6];
assign rf2ec_z = w_psr[1];
assign w_load_pc = il2rf_set_pcl | il2rf_set_pch |
ec2rf_set_pcl | ec2rf_set_pch;
assign w_next_pc = { r_pch, r_pcl } + 16'h0001;
assign w_c = ec2rf_set_c ? ec2rf_c : mc2rf_psr[0];
assign w_set_c = ec2rf_set_c | mc2rf_set_psr;
assign w_i = ec2rf_set_i ? ec2rf_i : il2rf_set_i ? 1'b1 : mc2rf_psr[2];
assign w_set_i = ec2rf_set_i | mc2rf_set_psr | il2rf_set_i;
assign w_v = ec2rf_set_v ? ec2rf_v : mc2rf_psr[6];
assign w_set_v = ec2rf_set_v | mc2rf_set_psr;
assign w_d = ec2rf_set_d ? ec2rf_d : mc2rf_psr[3];
assign w_set_d = ec2rf_set_d | mc2rf_set_psr;
assign w_n = ec2rf_set_n ? ec2rf_n : mc2rf_psr[7];
assign w_set_n = ec2rf_set_n | mc2rf_set_psr;
assign w_z = ec2rf_set_z ? ec2rf_z : mc2rf_psr[1];
assign w_set_z = ec2rf_set_z | mc2rf_set_psr;
assign w_b = il2rf_set_b ? 1'b1 : mc2rf_psr[4];
assign w_set_b = mc2rf_set_psr | il2rf_set_b;
always @ (posedge clk or negedge rst_x) begin
if (!rst_x) begin
r_pcl <= 8'h00;
r_pch <= 8'h00;
r_a <= 8'h00;
r_x <= 8'h00;
r_y <= 8'h00;
r_sp <= 8'h00;
end else begin
if (w_load_pc) begin
if (il2rf_set_pcl) begin
r_pcl <= il2rf_data;
end else if (ec2rf_set_pcl) begin
r_pcl <= ec2rf_data;
end
if (il2rf_set_pch) begin
r_pch <= il2rf_data;
end else if (ec2rf_set_pch) begin
r_pch <= ec2rf_data;
end
end else begin
if (mc2rf_fetched) begin
r_pch <= w_next_pc[15:8];
r_pcl <= w_next_pc[ 7:0];
end else if (mc2rf_set_pc) begin
r_pch <= mc2rf_pc[15:8];
r_pcl <= mc2rf_pc[ 7:0];
end
end // else (w_load_pc)
if (ec2rf_set_a) begin
r_a <= ec2rf_data;
end
if (ec2rf_set_x) begin
r_x <= ec2rf_data;
end
if (ec2rf_set_y) begin
r_y <= ec2rf_data;
end
if (ec2rf_set_s) begin
r_sp <= ec2rf_data;
end else if (mc2rf_pushed | il2rf_pushed) begin
r_sp <= r_sp - 8'h01;
end else if (mc2rf_pull) begin
r_sp <= r_sp + 8'h01;
end
end
end // always @ (posedge clk or negedge rst_x)
MC6502ProcessorStatusRegister ps(
.clk (clk ),
.rst_x (rst_x ),
.i_c (w_c ),
.i_set_c(w_set_c),
.i_i (w_i ),
.i_set_i(w_set_i),
.i_v (w_v ),
.i_set_v(w_set_v),
.i_d (w_d ),
.i_set_d(w_set_d),
.i_n (w_n ),
.i_set_n(w_set_n),
.i_z (w_z ),
.i_set_z(w_set_z),
.i_b (w_b ),
.i_set_b(w_set_b),
.o_psr (w_psr ));
endmodule // MC6502RegisterFile
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