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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSRECEIVER_TB_V
`define SKY130_FD_SC_LP__BUSRECEIVER_TB_V
/**
* busreceiver: Bus signal receiver.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__busreceiver.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_lp__busreceiver dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSRECEIVER_TB_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Cal Poly Pomona
// Engineer: Byron Phung
//
// Create Date: 15:18:15 04/17/2016
// Design Name:
// Module Name: Search_4Comparators
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Search_4Comparators(
input clock,
input reset,
input [1023:0] data,
input [63:0] key,
output reg match
);
// Use the counter to determine which bits of data to use.
reg [7:0] counter;
// Track the data needed for each comparator.
reg [63:0] data1, data2, data3, data4;
// Track each match output for each comparator.
wire match1, match2, match3, match4;
Comparator c1
(
.data(data1),
.key(key),
.match(match1)
);
Comparator c2
(
.data(data2),
.key(key),
.match(match2)
);
Comparator c3
(
.data(data3),
.key(key),
.match(match3)
);
Comparator c4
(
.data(data4),
.key(key),
.match(match4)
);
// Sequential Logic
always @(posedge clock, posedge reset)
begin
// If reset, reset every variable to their defaults.
if (reset)
begin
counter <= 0;
match <= 0;
end
// Otherwise, calculate the desired values.
else
begin
// If the last count is reached, then reset the counter.
// Equation: last count = (data_size - comparator_size) / num_of_comparators
if (counter == 240)
begin
counter <= 0;
end
// Otherwise, increment the counter.
else
begin
counter <= counter + 1;
end
// If the comparators yield matches for any of the current searches,
// then set the overall match to 1.
if (match1 || match2 || match3 || match4)
match <= 1;
// Otherwise, set it to 0.
else
match <= 0;
end
end
always @*
begin
if (counter == 240)
begin
data1 = data[1023-4*counter-:64];
data2 = data[1023-4*counter-:64];
data3 = data[1023-4*counter-:64];
data4 = data[1023-4*counter-:64];
end
else
begin
data1 = data[1023-4*counter-:64];
data2 = data[1022-4*counter-:64];
data3 = data[1021-4*counter-:64];
data4 = data[1020-4*counter-:64];
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A221OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__A221OI_BEHAVIORAL_PP_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a221oi (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
// Local signals
wire B2 and0_out ;
wire B2 and1_out ;
wire nor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
nor nor0 (nor0_out_Y , and0_out, C1, and1_out);
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A221OI_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR4_TB_V
`define SKY130_FD_SC_LP__OR4_TB_V
/**
* or4: 4-input OR.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__or4.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_lp__or4 dut (.A(A), .B(B), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR4_TB_V
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2014 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file pcie_command_send_fifo.v when simulating
// the core, pcie_command_send_fifo. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module pcie_command_send_fifo(
rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
almost_full,
empty,
almost_empty,
rd_data_count,
wr_data_count
);
input rst;
input wr_clk;
input rd_clk;
input [127 : 0] din;
input wr_en;
input rd_en;
output [127 : 0] dout;
output full;
output almost_full;
output empty;
output almost_empty;
output [8 : 0] rd_data_count;
output [8 : 0] wr_data_count;
// synthesis translate_off
FIFO_GENERATOR_V8_4 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(9),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(128),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(128),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("virtex6"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(1),
.C_HAS_ALMOST_FULL(1),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(1),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(1),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x72"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(5),
.C_PROG_EMPTY_TYPE_RACH(5),
.C_PROG_EMPTY_TYPE_RDCH(5),
.C_PROG_EMPTY_TYPE_WACH(5),
.C_PROG_EMPTY_TYPE_WDCH(5),
.C_PROG_EMPTY_TYPE_WRCH(5),
.C_PROG_FULL_THRESH_ASSERT_VAL(511),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(510),
.C_PROG_FULL_TYPE(0),
.C_PROG_FULL_TYPE_AXIS(5),
.C_PROG_FULL_TYPE_RACH(5),
.C_PROG_FULL_TYPE_RDCH(5),
.C_PROG_FULL_TYPE_WACH(5),
.C_PROG_FULL_TYPE_WDCH(5),
.C_PROG_FULL_TYPE_WRCH(5),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(9),
.C_RD_DEPTH(512),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(9),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(2),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(9),
.C_WR_DEPTH(512),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(9),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.RST(rst),
.WR_CLK(wr_clk),
.RD_CLK(rd_clk),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.ALMOST_FULL(almost_full),
.EMPTY(empty),
.ALMOST_EMPTY(almost_empty),
.RD_DATA_COUNT(rd_data_count),
.WR_DATA_COUNT(wr_data_count),
.BACKUP(),
.BACKUP_MARKER(),
.CLK(),
.SRST(),
.WR_RST(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.WR_ACK(),
.OVERFLOW(),
.VALID(),
.UNDERFLOW(),
.DATA_COUNT(),
.PROG_FULL(),
.PROG_EMPTY(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW()
);
// synthesis translate_on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A41O_4_V
`define SKY130_FD_SC_MS__A41O_4_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog wrapper for a41o with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a41o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a41o_4 (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a41o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a41o_4 (
X ,
A1,
A2,
A3,
A4,
B1
);
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a41o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A41O_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A31O_0_V
`define SKY130_FD_SC_LP__A31O_0_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog wrapper for a31o with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a31o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a31o_0 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a31o_0 (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A31O_0_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CONB_TB_V
`define SKY130_FD_SC_HS__CONB_TB_V
/**
* conb: Constant value, low, high outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__conb.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
// Outputs are wires
wire HI;
wire LO;
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VPWR = 1'b0;
#60 VGND = 1'b1;
#80 VPWR = 1'b1;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 VPWR = 1'b1;
#160 VGND = 1'b1;
#180 VPWR = 1'bx;
#200 VGND = 1'bx;
end
sky130_fd_sc_hs__conb dut (.VPWR(VPWR), .VGND(VGND), .HI(HI), .LO(LO));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__CONB_TB_V
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
///** PCIe wrapper +
//*/
module pcie_hip_s4gx_gen2_x4_128_plus (
// inputs:
app_int_sts,
app_msi_num,
app_msi_req,
app_msi_tc,
cpl_err,
cpl_pending,
fixedclk_serdes,
lmi_addr,
lmi_din,
lmi_rden,
lmi_wren,
local_rstn,
pcie_rstn,
pclk_in,
pex_msi_num,
phystatus_ext,
pipe_mode,
pld_clk,
pm_auxpwr,
pm_data,
pm_event,
pme_to_cr,
reconfig_clk,
reconfig_clk_locked,
refclk,
rx_in0,
rx_in1,
rx_in2,
rx_in3,
rx_st_mask0,
rx_st_ready0,
rxdata0_ext,
rxdata1_ext,
rxdata2_ext,
rxdata3_ext,
rxdatak0_ext,
rxdatak1_ext,
rxdatak2_ext,
rxdatak3_ext,
rxelecidle0_ext,
rxelecidle1_ext,
rxelecidle2_ext,
rxelecidle3_ext,
rxstatus0_ext,
rxstatus1_ext,
rxstatus2_ext,
rxstatus3_ext,
rxvalid0_ext,
rxvalid1_ext,
rxvalid2_ext,
rxvalid3_ext,
test_in,
tx_st_data0,
tx_st_empty0,
tx_st_eop0,
tx_st_err0,
tx_st_sop0,
tx_st_valid0,
// outputs:
app_int_ack,
app_msi_ack,
clk250_out,
clk500_out,
core_clk_out,
lane_act,
lmi_ack,
lmi_dout,
ltssm,
pme_to_sr,
powerdown_ext,
rate_ext,
rc_pll_locked,
rx_st_bardec0,
rx_st_be0,
rx_st_data0,
rx_st_empty0,
rx_st_eop0,
rx_st_err0,
rx_st_sop0,
rx_st_valid0,
rxpolarity0_ext,
rxpolarity1_ext,
rxpolarity2_ext,
rxpolarity3_ext,
srstn,
test_out,
tl_cfg_add,
tl_cfg_ctl,
tl_cfg_ctl_wr,
tl_cfg_sts,
tl_cfg_sts_wr,
tx_cred0,
tx_fifo_empty0,
tx_out0,
tx_out1,
tx_out2,
tx_out3,
tx_st_ready0,
txcompl0_ext,
txcompl1_ext,
txcompl2_ext,
txcompl3_ext,
txdata0_ext,
txdata1_ext,
txdata2_ext,
txdata3_ext,
txdatak0_ext,
txdatak1_ext,
txdatak2_ext,
txdatak3_ext,
txdetectrx_ext,
txelecidle0_ext,
txelecidle1_ext,
txelecidle2_ext,
txelecidle3_ext
)
;
output app_int_ack;
output app_msi_ack;
output clk250_out;
output clk500_out;
output core_clk_out;
output [ 3: 0] lane_act;
output lmi_ack;
output [ 31: 0] lmi_dout;
output [ 4: 0] ltssm;
output pme_to_sr;
output [ 1: 0] powerdown_ext;
output rate_ext;
output rc_pll_locked;
output [ 7: 0] rx_st_bardec0;
output [ 15: 0] rx_st_be0;
output [127: 0] rx_st_data0;
output rx_st_empty0;
output rx_st_eop0;
output rx_st_err0;
output rx_st_sop0;
output rx_st_valid0;
output rxpolarity0_ext;
output rxpolarity1_ext;
output rxpolarity2_ext;
output rxpolarity3_ext;
output srstn;
output [ 8: 0] test_out;
output [ 3: 0] tl_cfg_add;
output [ 31: 0] tl_cfg_ctl;
output tl_cfg_ctl_wr;
output [ 52: 0] tl_cfg_sts;
output tl_cfg_sts_wr;
output [ 35: 0] tx_cred0;
output tx_fifo_empty0;
output tx_out0;
output tx_out1;
output tx_out2;
output tx_out3;
output tx_st_ready0;
output txcompl0_ext;
output txcompl1_ext;
output txcompl2_ext;
output txcompl3_ext;
output [ 7: 0] txdata0_ext;
output [ 7: 0] txdata1_ext;
output [ 7: 0] txdata2_ext;
output [ 7: 0] txdata3_ext;
output txdatak0_ext;
output txdatak1_ext;
output txdatak2_ext;
output txdatak3_ext;
output txdetectrx_ext;
output txelecidle0_ext;
output txelecidle1_ext;
output txelecidle2_ext;
output txelecidle3_ext;
input app_int_sts;
input [ 4: 0] app_msi_num;
input app_msi_req;
input [ 2: 0] app_msi_tc;
input [ 6: 0] cpl_err;
input cpl_pending;
input fixedclk_serdes;
input [ 11: 0] lmi_addr;
input [ 31: 0] lmi_din;
input lmi_rden;
input lmi_wren;
input local_rstn;
input pcie_rstn;
input pclk_in;
input [ 4: 0] pex_msi_num;
input phystatus_ext;
input pipe_mode;
input pld_clk;
input pm_auxpwr;
input [ 9: 0] pm_data;
input pm_event;
input pme_to_cr;
input reconfig_clk;
input reconfig_clk_locked;
input refclk;
input rx_in0;
input rx_in1;
input rx_in2;
input rx_in3;
input rx_st_mask0;
input rx_st_ready0;
input [ 7: 0] rxdata0_ext;
input [ 7: 0] rxdata1_ext;
input [ 7: 0] rxdata2_ext;
input [ 7: 0] rxdata3_ext;
input rxdatak0_ext;
input rxdatak1_ext;
input rxdatak2_ext;
input rxdatak3_ext;
input rxelecidle0_ext;
input rxelecidle1_ext;
input rxelecidle2_ext;
input rxelecidle3_ext;
input [ 2: 0] rxstatus0_ext;
input [ 2: 0] rxstatus1_ext;
input [ 2: 0] rxstatus2_ext;
input [ 2: 0] rxstatus3_ext;
input rxvalid0_ext;
input rxvalid1_ext;
input rxvalid2_ext;
input rxvalid3_ext;
input [ 39: 0] test_in;
input [127: 0] tx_st_data0;
input tx_st_empty0;
input tx_st_eop0;
input tx_st_err0;
input tx_st_sop0;
input tx_st_valid0;
wire app_int_ack;
wire app_msi_ack;
wire busy_altgxb_reconfig;
wire busy_altgxb_reconfig_altr;
wire clk250_out;
wire clk500_out;
wire core_clk_out;
wire crst;
wire data_valid;
wire dlup_exit;
wire [ 4: 0] gnd_hpg_ctrler;
wire gxb_powerdown;
wire hotrst_exit;
wire hotrst_exit_altr;
wire l2_exit;
wire [ 3: 0] lane_act;
wire lmi_ack;
wire [ 31: 0] lmi_dout;
wire [ 4: 0] ltssm;
wire npor;
wire npor_serdes_pll_locked;
wire offset_cancellation_reset;
wire open_rx_fifo_empty0;
wire open_rx_fifo_full0;
wire open_tx_fifo_full0;
wire [ 3: 0] open_tx_fifo_rdptr0;
wire [ 3: 0] open_tx_fifo_wrptr0;
wire otb0;
wire otb1;
wire pll_powerdown;
wire pme_to_sr;
wire [ 1: 0] powerdown_ext;
wire rate_ext;
wire rc_pll_locked;
wire [ 33: 0] reconfig_fromgxb;
wire [ 3: 0] reconfig_togxb;
wire [ 3: 0] rx_eqctrl_out;
wire [ 2: 0] rx_eqdcgain_out;
wire [ 7: 0] rx_st_bardec0;
wire [ 15: 0] rx_st_be0;
wire [127: 0] rx_st_data0;
wire rx_st_empty0;
wire rx_st_eop0;
wire rx_st_err0;
wire rx_st_sop0;
wire rx_st_valid0;
wire rxpolarity0_ext;
wire rxpolarity1_ext;
wire rxpolarity2_ext;
wire rxpolarity3_ext;
wire srst;
wire srstn;
wire [ 8: 0] test_out;
wire [ 3: 0] tl_cfg_add;
wire [ 31: 0] tl_cfg_ctl;
wire tl_cfg_ctl_wr;
wire [ 52: 0] tl_cfg_sts;
wire tl_cfg_sts_wr;
wire [ 35: 0] tx_cred0;
wire tx_fifo_empty0;
wire tx_out0;
wire tx_out1;
wire tx_out2;
wire tx_out3;
wire [ 4: 0] tx_preemp_0t_out;
wire [ 4: 0] tx_preemp_1t_out;
wire [ 4: 0] tx_preemp_2t_out;
wire tx_st_ready0;
wire [ 2: 0] tx_vodctrl_out;
wire txcompl0_ext;
wire txcompl1_ext;
wire txcompl2_ext;
wire txcompl3_ext;
wire [ 7: 0] txdata0_ext;
wire [ 7: 0] txdata1_ext;
wire [ 7: 0] txdata2_ext;
wire [ 7: 0] txdata3_ext;
wire txdatak0_ext;
wire txdatak1_ext;
wire txdatak2_ext;
wire txdatak3_ext;
wire txdetectrx_ext;
wire txelecidle0_ext;
wire txelecidle1_ext;
wire txelecidle2_ext;
wire txelecidle3_ext;
assign otb0 = 1'b0;
assign otb1 = 1'b1;
assign offset_cancellation_reset = ~reconfig_clk_locked;
assign reconfig_fromgxb[33 : 17] = 0;
assign gnd_hpg_ctrler = 0;
assign busy_altgxb_reconfig_altr = (pipe_mode==otb1)?otb0:busy_altgxb_reconfig;
assign gxb_powerdown = ~npor;
assign hotrst_exit_altr = hotrst_exit;
assign pll_powerdown = ~npor;
assign npor_serdes_pll_locked = pcie_rstn & local_rstn & rc_pll_locked;
assign npor = pcie_rstn & local_rstn;
pcie_hip_s4gx_gen2_x4_128 epmap
(
.app_int_ack (app_int_ack),
.app_int_sts (app_int_sts),
.app_msi_ack (app_msi_ack),
.app_msi_num (app_msi_num),
.app_msi_req (app_msi_req),
.app_msi_tc (app_msi_tc),
.busy_altgxb_reconfig (busy_altgxb_reconfig_altr),
.cal_blk_clk (reconfig_clk),
.clk250_out (clk250_out),
.clk500_out (clk500_out),
.core_clk_out (core_clk_out),
.cpl_err (cpl_err),
.cpl_pending (cpl_pending),
.crst (crst),
.dlup_exit (dlup_exit),
.fixedclk_serdes (fixedclk_serdes),
.gxb_powerdown (gxb_powerdown),
.hotrst_exit (hotrst_exit),
.hpg_ctrler (gnd_hpg_ctrler),
.l2_exit (l2_exit),
.lane_act (lane_act),
.lmi_ack (lmi_ack),
.lmi_addr (lmi_addr),
.lmi_din (lmi_din),
.lmi_dout (lmi_dout),
.lmi_rden (lmi_rden),
.lmi_wren (lmi_wren),
.ltssm (ltssm),
.npor (npor),
.pclk_in (pclk_in),
.pex_msi_num (pex_msi_num),
.phystatus_ext (phystatus_ext),
.pipe_mode (pipe_mode),
.pld_clk (pld_clk),
.pll_powerdown (pll_powerdown),
.pm_auxpwr (pm_auxpwr),
.pm_data (pm_data),
.pm_event (pm_event),
.pme_to_cr (pme_to_cr),
.pme_to_sr (pme_to_sr),
.powerdown_ext (powerdown_ext),
.rate_ext (rate_ext),
.rc_pll_locked (rc_pll_locked),
.reconfig_clk (reconfig_clk),
.reconfig_fromgxb (reconfig_fromgxb[16 : 0]),
.reconfig_togxb (reconfig_togxb),
.refclk (refclk),
.rx_fifo_empty0 (open_rx_fifo_empty0),
.rx_fifo_full0 (open_rx_fifo_full0),
.rx_in0 (rx_in0),
.rx_in1 (rx_in1),
.rx_in2 (rx_in2),
.rx_in3 (rx_in3),
.rx_st_bardec0 (rx_st_bardec0),
.rx_st_be0 (rx_st_be0),
.rx_st_data0 (rx_st_data0),
.rx_st_empty0 (rx_st_empty0),
.rx_st_eop0 (rx_st_eop0),
.rx_st_err0 (rx_st_err0),
.rx_st_mask0 (rx_st_mask0),
.rx_st_ready0 (rx_st_ready0),
.rx_st_sop0 (rx_st_sop0),
.rx_st_valid0 (rx_st_valid0),
.rxdata0_ext (rxdata0_ext),
.rxdata1_ext (rxdata1_ext),
.rxdata2_ext (rxdata2_ext),
.rxdata3_ext (rxdata3_ext),
.rxdatak0_ext (rxdatak0_ext),
.rxdatak1_ext (rxdatak1_ext),
.rxdatak2_ext (rxdatak2_ext),
.rxdatak3_ext (rxdatak3_ext),
.rxelecidle0_ext (rxelecidle0_ext),
.rxelecidle1_ext (rxelecidle1_ext),
.rxelecidle2_ext (rxelecidle2_ext),
.rxelecidle3_ext (rxelecidle3_ext),
.rxpolarity0_ext (rxpolarity0_ext),
.rxpolarity1_ext (rxpolarity1_ext),
.rxpolarity2_ext (rxpolarity2_ext),
.rxpolarity3_ext (rxpolarity3_ext),
.rxstatus0_ext (rxstatus0_ext),
.rxstatus1_ext (rxstatus1_ext),
.rxstatus2_ext (rxstatus2_ext),
.rxstatus3_ext (rxstatus3_ext),
.rxvalid0_ext (rxvalid0_ext),
.rxvalid1_ext (rxvalid1_ext),
.rxvalid2_ext (rxvalid2_ext),
.rxvalid3_ext (rxvalid3_ext),
.srst (srst),
.test_in (test_in),
.test_out (test_out),
.tl_cfg_add (tl_cfg_add),
.tl_cfg_ctl (tl_cfg_ctl),
.tl_cfg_ctl_wr (tl_cfg_ctl_wr),
.tl_cfg_sts (tl_cfg_sts),
.tl_cfg_sts_wr (tl_cfg_sts_wr),
.tx_cred0 (tx_cred0),
.tx_fifo_empty0 (tx_fifo_empty0),
.tx_fifo_full0 (open_tx_fifo_full0),
.tx_fifo_rdptr0 (open_tx_fifo_rdptr0),
.tx_fifo_wrptr0 (open_tx_fifo_wrptr0),
.tx_out0 (tx_out0),
.tx_out1 (tx_out1),
.tx_out2 (tx_out2),
.tx_out3 (tx_out3),
.tx_st_data0 (tx_st_data0),
.tx_st_empty0 (tx_st_empty0),
.tx_st_eop0 (tx_st_eop0),
.tx_st_err0 (tx_st_err0),
.tx_st_ready0 (tx_st_ready0),
.tx_st_sop0 (tx_st_sop0),
.tx_st_valid0 (tx_st_valid0),
.txcompl0_ext (txcompl0_ext),
.txcompl1_ext (txcompl1_ext),
.txcompl2_ext (txcompl2_ext),
.txcompl3_ext (txcompl3_ext),
.txdata0_ext (txdata0_ext),
.txdata1_ext (txdata1_ext),
.txdata2_ext (txdata2_ext),
.txdata3_ext (txdata3_ext),
.txdatak0_ext (txdatak0_ext),
.txdatak1_ext (txdatak1_ext),
.txdatak2_ext (txdatak2_ext),
.txdatak3_ext (txdatak3_ext),
.txdetectrx_ext (txdetectrx_ext),
.txelecidle0_ext (txelecidle0_ext),
.txelecidle1_ext (txelecidle1_ext),
.txelecidle2_ext (txelecidle2_ext),
.txelecidle3_ext (txelecidle3_ext)
);
altpcie_reconfig_4sgx reconfig
(
.busy (busy_altgxb_reconfig),
.data_valid (data_valid),
.logical_channel_address (3'b000),
.offset_cancellation_reset (offset_cancellation_reset),
.read (1'b0),
.reconfig_clk (reconfig_clk),
.reconfig_fromgxb (reconfig_fromgxb),
.reconfig_togxb (reconfig_togxb),
.rx_eqctrl (4'b0000),
.rx_eqctrl_out (rx_eqctrl_out),
.rx_eqdcgain (3'b000),
.rx_eqdcgain_out (rx_eqdcgain_out),
.tx_preemp_0t (5'b00000),
.tx_preemp_0t_out (tx_preemp_0t_out),
.tx_preemp_1t (5'b00000),
.tx_preemp_1t_out (tx_preemp_1t_out),
.tx_preemp_2t (5'b00000),
.tx_preemp_2t_out (tx_preemp_2t_out),
.tx_vodctrl (3'b000),
.tx_vodctrl_out (tx_vodctrl_out),
.write_all (1'b0)
);
pcie_hip_s4gx_gen2_x4_128_rs_hip rs_hip
(
.app_rstn (srstn),
.crst (crst),
.dlup_exit (dlup_exit),
.hotrst_exit (hotrst_exit_altr),
.l2_exit (l2_exit),
.ltssm (ltssm),
.npor (npor_serdes_pll_locked),
.pld_clk (pld_clk),
.srst (srst),
.test_sim (test_in[0])
);
endmodule
|
module InputCapture(clk_i,rst_i,ins_i,addr_bi,data_bi,data_bo,en_i,we_bi,timer1_i,timer2_i);
input clk_i;
input rst_i;
input ins_i;
input [12:0] addr_bi;
input [31:0] data_bi;
output [31:0] data_bo;
input en_i;
input we_bi;
input [31:0] timer1_i;
input [31:0] timer2_i;
wire icov_fifo_icconf;
wire icbne_fifo_icconf;
wire [31:0] tval_tc_fifo;
wire ins_prescaler_fifo;
wire ins_ed_prescaler;
wire [31:0] icconf_fifo_icconf;
wire [1:0] ictmr_from_icconf;
wire [2:0] icm_from_icconf;
wire [31:0] icconf_icconf_fifo;
FIFO fifo (.tval2_i(timer2_i), .tval1_i(tval_tc_fifo), .icov_o(icov_fifo_icconf), .icbne_o(icbne_fifo_icconf), .ictmr_i(ictmr_from_icconf), .icconf_o(icconf_fifo_icconf), .icconf_i(icconf_icconf_fifo), .ins_i(ins_prescaler_fifo), .we_bi(we_bi), .en_i(en_i), .data_bo(data_bo), .data_bi(data_bi), .addr_bi(addr_bi), .rst_i(rst_i), .clk_i(clk_i));
TimersControl timers_control (.tval_o(tval_tc_fifo), .ictmr_i(ictmr_from_icconf), .timer2_i(timer2_i), .timer1_i(timer1_i));
Prescaler prescaler (.ins_o(ins_prescaler_fifo), .ins_i(ins_ed_prescaler), .icm_i(icm_from_icconf), .rst_i(rst_i), .clk_i(clk_i));
EdgeDetector edge_detector (.ins_o(ins_ed_prescaler), .ins_i(ins_i), .icm_i(icm_from_icconf), .clk_i(clk_i));
ICCONF icconf (.ictmr_o(ictmr_from_icconf), .icm_o(icm_from_icconf), .icov_i(icov_fifo_icconf), .icbne_i(icbne_fifo_icconf), .icconf_o(icconf_icconf_fifo), .icconf_i(icconf_fifo_icconf));
endmodule
|
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author:
* Description:
*
* Changes:
*/
module sd_host_phy (
input clk,
input rst,
//Coniguration
input i_phy_crc_enable,
input i_phy_ddr_en,
input i_sd1_phy_flag,
input i_sd4_phy_flag,
//Command/Response Interface
input i_cmd_stb,
input [39:0] i_cmd,
input i_rsp_long_flag,
output reg o_rsp_stb,
output [135:0] o_rsp,
//Data
input i_data_en_stb,
output reg o_data_finish_ack_stb,
//Data From Host to SD Interface
input i_h2s_fifo_ready,
output o_h2s_fifo_activate,
input [23:0] i_h2s_fifo_size,
output o_h2s_fifo_stb,
input [31:0] i_h2s_fifo_data,
//Data From SD to Host Interface
input [1:0] i_s2h_fifo_ready,
output [1:0] o_s2h_fifo_activate,
input [23:0] i_s2h_fifo_size,
input i_s2h_fifo_stb,
output [31:0] o_s2h_fifo_data,
output o_interrupt
);
//local parameters
localparam IDLE = 4'h0;
localparam SEND_COMMAND = 4'h1;
localparam CMD_RESPONSE = 4'h2;
localparam SEND_DATA = 4'h1;
localparam READ_DATA = 4'h2;
//registes/wires
reg [3:0] cmd_state;
reg [3:0] data_state;
//submodules
//asynchronous logic
//synchronous logic
always @ (posedge clk) begin
//De-assert Strobes
o_rsp_stb <= 1'b0;
if (rst) begin
cmd_state <= IDLE;
end
else begin
case (cmd_state)
IDLE: begin
if (i_cmd_stb) begin
end
end
SEND_COMMAND: begin
end
CMD_RESPONSE: begin
end
default: begin
end
endcase
end
end
always @ (posedge clk) begin
o_data_finish_ack_stb <= 1'b0;
if (rst) begin
data_state <= IDLE;
end
else begin
case (data_state)
IDLE: begin
if (i_data_stb) begin
//
end
end
SEND_DATA: begin
end
READ_DATA: begin
end
default: begin
end
endcase
end
end
endmodule
|
/******************************************************************************
* File Name : ks233.v
* Package Module Name : Elliptic Curve Cryptoprocessor for GF(2^233)
* Author : Chester Rebeiro
* Date of Creation : 1/Apr/2008
* Type of file : Verilog source code
* Synopsis : Automatically generated code for karatsuba 233 bit
******************************************************************************/
`ifndef __KS_233_V__
`define __KS_233_V__
//`include "ks117.v"
//`include "ks116.v"
module ks233(a, b, d);
input wire [232:0] a;
input wire [232:0] b;
output wire [464:0] d;
wire [230:0] m1;
wire [232:0] m2;
wire [232:0] m3;
wire [116:0] ahl;
wire [116:0] bhl;
ks117 ksm1(a[116:0], b[116:0], m2);
ks116 ksm2(a[232:117], b[232:117], m1);
assign ahl[115:0] = a[232:117] ^ a[115:0];
assign ahl[116] = a[116];
assign bhl[115:0] = b[232:117] ^ b[115:0];
assign bhl[116] = b[116];
ks117 ksm3(ahl, bhl, m3);
assign d[00] = m2[00];
assign d[01] = m2[01];
assign d[02] = m2[02];
assign d[03] = m2[03];
assign d[04] = m2[04];
assign d[05] = m2[05];
assign d[06] = m2[06];
assign d[07] = m2[07];
assign d[08] = m2[08];
assign d[09] = m2[09];
assign d[10] = m2[10];
assign d[11] = m2[11];
assign d[12] = m2[12];
assign d[13] = m2[13];
assign d[14] = m2[14];
assign d[15] = m2[15];
assign d[16] = m2[16];
assign d[17] = m2[17];
assign d[18] = m2[18];
assign d[19] = m2[19];
assign d[20] = m2[20];
assign d[21] = m2[21];
assign d[22] = m2[22];
assign d[23] = m2[23];
assign d[24] = m2[24];
assign d[25] = m2[25];
assign d[26] = m2[26];
assign d[27] = m2[27];
assign d[28] = m2[28];
assign d[29] = m2[29];
assign d[30] = m2[30];
assign d[31] = m2[31];
assign d[32] = m2[32];
assign d[33] = m2[33];
assign d[34] = m2[34];
assign d[35] = m2[35];
assign d[36] = m2[36];
assign d[37] = m2[37];
assign d[38] = m2[38];
assign d[39] = m2[39];
assign d[40] = m2[40];
assign d[41] = m2[41];
assign d[42] = m2[42];
assign d[43] = m2[43];
assign d[44] = m2[44];
assign d[45] = m2[45];
assign d[46] = m2[46];
assign d[47] = m2[47];
assign d[48] = m2[48];
assign d[49] = m2[49];
assign d[50] = m2[50];
assign d[51] = m2[51];
assign d[52] = m2[52];
assign d[53] = m2[53];
assign d[54] = m2[54];
assign d[55] = m2[55];
assign d[56] = m2[56];
assign d[57] = m2[57];
assign d[58] = m2[58];
assign d[59] = m2[59];
assign d[60] = m2[60];
assign d[61] = m2[61];
assign d[62] = m2[62];
assign d[63] = m2[63];
assign d[64] = m2[64];
assign d[65] = m2[65];
assign d[66] = m2[66];
assign d[67] = m2[67];
assign d[68] = m2[68];
assign d[69] = m2[69];
assign d[70] = m2[70];
assign d[71] = m2[71];
assign d[72] = m2[72];
assign d[73] = m2[73];
assign d[74] = m2[74];
assign d[75] = m2[75];
assign d[76] = m2[76];
assign d[77] = m2[77];
assign d[78] = m2[78];
assign d[79] = m2[79];
assign d[80] = m2[80];
assign d[81] = m2[81];
assign d[82] = m2[82];
assign d[83] = m2[83];
assign d[84] = m2[84];
assign d[85] = m2[85];
assign d[86] = m2[86];
assign d[87] = m2[87];
assign d[88] = m2[88];
assign d[89] = m2[89];
assign d[90] = m2[90];
assign d[91] = m2[91];
assign d[92] = m2[92];
assign d[93] = m2[93];
assign d[94] = m2[94];
assign d[95] = m2[95];
assign d[96] = m2[96];
assign d[97] = m2[97];
assign d[98] = m2[98];
assign d[99] = m2[99];
assign d[100] = m2[100];
assign d[101] = m2[101];
assign d[102] = m2[102];
assign d[103] = m2[103];
assign d[104] = m2[104];
assign d[105] = m2[105];
assign d[106] = m2[106];
assign d[107] = m2[107];
assign d[108] = m2[108];
assign d[109] = m2[109];
assign d[110] = m2[110];
assign d[111] = m2[111];
assign d[112] = m2[112];
assign d[113] = m2[113];
assign d[114] = m2[114];
assign d[115] = m2[115];
assign d[116] = m2[116];
assign d[117] = m2[117] ^ m1[00] ^ m2[00] ^ m3[00];
assign d[118] = m2[118] ^ m1[01] ^ m2[01] ^ m3[01];
assign d[119] = m2[119] ^ m1[02] ^ m2[02] ^ m3[02];
assign d[120] = m2[120] ^ m1[03] ^ m2[03] ^ m3[03];
assign d[121] = m2[121] ^ m1[04] ^ m2[04] ^ m3[04];
assign d[122] = m2[122] ^ m1[05] ^ m2[05] ^ m3[05];
assign d[123] = m2[123] ^ m1[06] ^ m2[06] ^ m3[06];
assign d[124] = m2[124] ^ m1[07] ^ m2[07] ^ m3[07];
assign d[125] = m2[125] ^ m1[08] ^ m2[08] ^ m3[08];
assign d[126] = m2[126] ^ m1[09] ^ m2[09] ^ m3[09];
assign d[127] = m2[127] ^ m1[10] ^ m2[10] ^ m3[10];
assign d[128] = m2[128] ^ m1[11] ^ m2[11] ^ m3[11];
assign d[129] = m2[129] ^ m1[12] ^ m2[12] ^ m3[12];
assign d[130] = m2[130] ^ m1[13] ^ m2[13] ^ m3[13];
assign d[131] = m2[131] ^ m1[14] ^ m2[14] ^ m3[14];
assign d[132] = m2[132] ^ m1[15] ^ m2[15] ^ m3[15];
assign d[133] = m2[133] ^ m1[16] ^ m2[16] ^ m3[16];
assign d[134] = m2[134] ^ m1[17] ^ m2[17] ^ m3[17];
assign d[135] = m2[135] ^ m1[18] ^ m2[18] ^ m3[18];
assign d[136] = m2[136] ^ m1[19] ^ m2[19] ^ m3[19];
assign d[137] = m2[137] ^ m1[20] ^ m2[20] ^ m3[20];
assign d[138] = m2[138] ^ m1[21] ^ m2[21] ^ m3[21];
assign d[139] = m2[139] ^ m1[22] ^ m2[22] ^ m3[22];
assign d[140] = m2[140] ^ m1[23] ^ m2[23] ^ m3[23];
assign d[141] = m2[141] ^ m1[24] ^ m2[24] ^ m3[24];
assign d[142] = m2[142] ^ m1[25] ^ m2[25] ^ m3[25];
assign d[143] = m2[143] ^ m1[26] ^ m2[26] ^ m3[26];
assign d[144] = m2[144] ^ m1[27] ^ m2[27] ^ m3[27];
assign d[145] = m2[145] ^ m1[28] ^ m2[28] ^ m3[28];
assign d[146] = m2[146] ^ m1[29] ^ m2[29] ^ m3[29];
assign d[147] = m2[147] ^ m1[30] ^ m2[30] ^ m3[30];
assign d[148] = m2[148] ^ m1[31] ^ m2[31] ^ m3[31];
assign d[149] = m2[149] ^ m1[32] ^ m2[32] ^ m3[32];
assign d[150] = m2[150] ^ m1[33] ^ m2[33] ^ m3[33];
assign d[151] = m2[151] ^ m1[34] ^ m2[34] ^ m3[34];
assign d[152] = m2[152] ^ m1[35] ^ m2[35] ^ m3[35];
assign d[153] = m2[153] ^ m1[36] ^ m2[36] ^ m3[36];
assign d[154] = m2[154] ^ m1[37] ^ m2[37] ^ m3[37];
assign d[155] = m2[155] ^ m1[38] ^ m2[38] ^ m3[38];
assign d[156] = m2[156] ^ m1[39] ^ m2[39] ^ m3[39];
assign d[157] = m2[157] ^ m1[40] ^ m2[40] ^ m3[40];
assign d[158] = m2[158] ^ m1[41] ^ m2[41] ^ m3[41];
assign d[159] = m2[159] ^ m1[42] ^ m2[42] ^ m3[42];
assign d[160] = m2[160] ^ m1[43] ^ m2[43] ^ m3[43];
assign d[161] = m2[161] ^ m1[44] ^ m2[44] ^ m3[44];
assign d[162] = m2[162] ^ m1[45] ^ m2[45] ^ m3[45];
assign d[163] = m2[163] ^ m1[46] ^ m2[46] ^ m3[46];
assign d[164] = m2[164] ^ m1[47] ^ m2[47] ^ m3[47];
assign d[165] = m2[165] ^ m1[48] ^ m2[48] ^ m3[48];
assign d[166] = m2[166] ^ m1[49] ^ m2[49] ^ m3[49];
assign d[167] = m2[167] ^ m1[50] ^ m2[50] ^ m3[50];
assign d[168] = m2[168] ^ m1[51] ^ m2[51] ^ m3[51];
assign d[169] = m2[169] ^ m1[52] ^ m2[52] ^ m3[52];
assign d[170] = m2[170] ^ m1[53] ^ m2[53] ^ m3[53];
assign d[171] = m2[171] ^ m1[54] ^ m2[54] ^ m3[54];
assign d[172] = m2[172] ^ m1[55] ^ m2[55] ^ m3[55];
assign d[173] = m2[173] ^ m1[56] ^ m2[56] ^ m3[56];
assign d[174] = m2[174] ^ m1[57] ^ m2[57] ^ m3[57];
assign d[175] = m2[175] ^ m1[58] ^ m2[58] ^ m3[58];
assign d[176] = m2[176] ^ m1[59] ^ m2[59] ^ m3[59];
assign d[177] = m2[177] ^ m1[60] ^ m2[60] ^ m3[60];
assign d[178] = m2[178] ^ m1[61] ^ m2[61] ^ m3[61];
assign d[179] = m2[179] ^ m1[62] ^ m2[62] ^ m3[62];
assign d[180] = m2[180] ^ m1[63] ^ m2[63] ^ m3[63];
assign d[181] = m2[181] ^ m1[64] ^ m2[64] ^ m3[64];
assign d[182] = m2[182] ^ m1[65] ^ m2[65] ^ m3[65];
assign d[183] = m2[183] ^ m1[66] ^ m2[66] ^ m3[66];
assign d[184] = m2[184] ^ m1[67] ^ m2[67] ^ m3[67];
assign d[185] = m2[185] ^ m1[68] ^ m2[68] ^ m3[68];
assign d[186] = m2[186] ^ m1[69] ^ m2[69] ^ m3[69];
assign d[187] = m2[187] ^ m1[70] ^ m2[70] ^ m3[70];
assign d[188] = m2[188] ^ m1[71] ^ m2[71] ^ m3[71];
assign d[189] = m2[189] ^ m1[72] ^ m2[72] ^ m3[72];
assign d[190] = m2[190] ^ m1[73] ^ m2[73] ^ m3[73];
assign d[191] = m2[191] ^ m1[74] ^ m2[74] ^ m3[74];
assign d[192] = m2[192] ^ m1[75] ^ m2[75] ^ m3[75];
assign d[193] = m2[193] ^ m1[76] ^ m2[76] ^ m3[76];
assign d[194] = m2[194] ^ m1[77] ^ m2[77] ^ m3[77];
assign d[195] = m2[195] ^ m1[78] ^ m2[78] ^ m3[78];
assign d[196] = m2[196] ^ m1[79] ^ m2[79] ^ m3[79];
assign d[197] = m2[197] ^ m1[80] ^ m2[80] ^ m3[80];
assign d[198] = m2[198] ^ m1[81] ^ m2[81] ^ m3[81];
assign d[199] = m2[199] ^ m1[82] ^ m2[82] ^ m3[82];
assign d[200] = m2[200] ^ m1[83] ^ m2[83] ^ m3[83];
assign d[201] = m2[201] ^ m1[84] ^ m2[84] ^ m3[84];
assign d[202] = m2[202] ^ m1[85] ^ m2[85] ^ m3[85];
assign d[203] = m2[203] ^ m1[86] ^ m2[86] ^ m3[86];
assign d[204] = m2[204] ^ m1[87] ^ m2[87] ^ m3[87];
assign d[205] = m2[205] ^ m1[88] ^ m2[88] ^ m3[88];
assign d[206] = m2[206] ^ m1[89] ^ m2[89] ^ m3[89];
assign d[207] = m2[207] ^ m1[90] ^ m2[90] ^ m3[90];
assign d[208] = m2[208] ^ m1[91] ^ m2[91] ^ m3[91];
assign d[209] = m2[209] ^ m1[92] ^ m2[92] ^ m3[92];
assign d[210] = m2[210] ^ m1[93] ^ m2[93] ^ m3[93];
assign d[211] = m2[211] ^ m1[94] ^ m2[94] ^ m3[94];
assign d[212] = m2[212] ^ m1[95] ^ m2[95] ^ m3[95];
assign d[213] = m2[213] ^ m1[96] ^ m2[96] ^ m3[96];
assign d[214] = m2[214] ^ m1[97] ^ m2[97] ^ m3[97];
assign d[215] = m2[215] ^ m1[98] ^ m2[98] ^ m3[98];
assign d[216] = m2[216] ^ m1[99] ^ m2[99] ^ m3[99];
assign d[217] = m2[217] ^ m1[100] ^ m2[100] ^ m3[100];
assign d[218] = m2[218] ^ m1[101] ^ m2[101] ^ m3[101];
assign d[219] = m2[219] ^ m1[102] ^ m2[102] ^ m3[102];
assign d[220] = m2[220] ^ m1[103] ^ m2[103] ^ m3[103];
assign d[221] = m2[221] ^ m1[104] ^ m2[104] ^ m3[104];
assign d[222] = m2[222] ^ m1[105] ^ m2[105] ^ m3[105];
assign d[223] = m2[223] ^ m1[106] ^ m2[106] ^ m3[106];
assign d[224] = m2[224] ^ m1[107] ^ m2[107] ^ m3[107];
assign d[225] = m2[225] ^ m1[108] ^ m2[108] ^ m3[108];
assign d[226] = m2[226] ^ m1[109] ^ m2[109] ^ m3[109];
assign d[227] = m2[227] ^ m1[110] ^ m2[110] ^ m3[110];
assign d[228] = m2[228] ^ m1[111] ^ m2[111] ^ m3[111];
assign d[229] = m2[229] ^ m1[112] ^ m2[112] ^ m3[112];
assign d[230] = m2[230] ^ m1[113] ^ m2[113] ^ m3[113];
assign d[231] = m2[231] ^ m1[114] ^ m2[114] ^ m3[114];
assign d[232] = m2[232] ^ m1[115] ^ m2[115] ^ m3[115];
assign d[233] = m1[116] ^ m2[116] ^ m3[116];
assign d[234] = m1[117] ^ m2[117] ^ m3[117] ^ m1[00];
assign d[235] = m1[118] ^ m2[118] ^ m3[118] ^ m1[01];
assign d[236] = m1[119] ^ m2[119] ^ m3[119] ^ m1[02];
assign d[237] = m1[120] ^ m2[120] ^ m3[120] ^ m1[03];
assign d[238] = m1[121] ^ m2[121] ^ m3[121] ^ m1[04];
assign d[239] = m1[122] ^ m2[122] ^ m3[122] ^ m1[05];
assign d[240] = m1[123] ^ m2[123] ^ m3[123] ^ m1[06];
assign d[241] = m1[124] ^ m2[124] ^ m3[124] ^ m1[07];
assign d[242] = m1[125] ^ m2[125] ^ m3[125] ^ m1[08];
assign d[243] = m1[126] ^ m2[126] ^ m3[126] ^ m1[09];
assign d[244] = m1[127] ^ m2[127] ^ m3[127] ^ m1[10];
assign d[245] = m1[128] ^ m2[128] ^ m3[128] ^ m1[11];
assign d[246] = m1[129] ^ m2[129] ^ m3[129] ^ m1[12];
assign d[247] = m1[130] ^ m2[130] ^ m3[130] ^ m1[13];
assign d[248] = m1[131] ^ m2[131] ^ m3[131] ^ m1[14];
assign d[249] = m1[132] ^ m2[132] ^ m3[132] ^ m1[15];
assign d[250] = m1[133] ^ m2[133] ^ m3[133] ^ m1[16];
assign d[251] = m1[134] ^ m2[134] ^ m3[134] ^ m1[17];
assign d[252] = m1[135] ^ m2[135] ^ m3[135] ^ m1[18];
assign d[253] = m1[136] ^ m2[136] ^ m3[136] ^ m1[19];
assign d[254] = m1[137] ^ m2[137] ^ m3[137] ^ m1[20];
assign d[255] = m1[138] ^ m2[138] ^ m3[138] ^ m1[21];
assign d[256] = m1[139] ^ m2[139] ^ m3[139] ^ m1[22];
assign d[257] = m1[140] ^ m2[140] ^ m3[140] ^ m1[23];
assign d[258] = m1[141] ^ m2[141] ^ m3[141] ^ m1[24];
assign d[259] = m1[142] ^ m2[142] ^ m3[142] ^ m1[25];
assign d[260] = m1[143] ^ m2[143] ^ m3[143] ^ m1[26];
assign d[261] = m1[144] ^ m2[144] ^ m3[144] ^ m1[27];
assign d[262] = m1[145] ^ m2[145] ^ m3[145] ^ m1[28];
assign d[263] = m1[146] ^ m2[146] ^ m3[146] ^ m1[29];
assign d[264] = m1[147] ^ m2[147] ^ m3[147] ^ m1[30];
assign d[265] = m1[148] ^ m2[148] ^ m3[148] ^ m1[31];
assign d[266] = m1[149] ^ m2[149] ^ m3[149] ^ m1[32];
assign d[267] = m1[150] ^ m2[150] ^ m3[150] ^ m1[33];
assign d[268] = m1[151] ^ m2[151] ^ m3[151] ^ m1[34];
assign d[269] = m1[152] ^ m2[152] ^ m3[152] ^ m1[35];
assign d[270] = m1[153] ^ m2[153] ^ m3[153] ^ m1[36];
assign d[271] = m1[154] ^ m2[154] ^ m3[154] ^ m1[37];
assign d[272] = m1[155] ^ m2[155] ^ m3[155] ^ m1[38];
assign d[273] = m1[156] ^ m2[156] ^ m3[156] ^ m1[39];
assign d[274] = m1[157] ^ m2[157] ^ m3[157] ^ m1[40];
assign d[275] = m1[158] ^ m2[158] ^ m3[158] ^ m1[41];
assign d[276] = m1[159] ^ m2[159] ^ m3[159] ^ m1[42];
assign d[277] = m1[160] ^ m2[160] ^ m3[160] ^ m1[43];
assign d[278] = m1[161] ^ m2[161] ^ m3[161] ^ m1[44];
assign d[279] = m1[162] ^ m2[162] ^ m3[162] ^ m1[45];
assign d[280] = m1[163] ^ m2[163] ^ m3[163] ^ m1[46];
assign d[281] = m1[164] ^ m2[164] ^ m3[164] ^ m1[47];
assign d[282] = m1[165] ^ m2[165] ^ m3[165] ^ m1[48];
assign d[283] = m1[166] ^ m2[166] ^ m3[166] ^ m1[49];
assign d[284] = m1[167] ^ m2[167] ^ m3[167] ^ m1[50];
assign d[285] = m1[168] ^ m2[168] ^ m3[168] ^ m1[51];
assign d[286] = m1[169] ^ m2[169] ^ m3[169] ^ m1[52];
assign d[287] = m1[170] ^ m2[170] ^ m3[170] ^ m1[53];
assign d[288] = m1[171] ^ m2[171] ^ m3[171] ^ m1[54];
assign d[289] = m1[172] ^ m2[172] ^ m3[172] ^ m1[55];
assign d[290] = m1[173] ^ m2[173] ^ m3[173] ^ m1[56];
assign d[291] = m1[174] ^ m2[174] ^ m3[174] ^ m1[57];
assign d[292] = m1[175] ^ m2[175] ^ m3[175] ^ m1[58];
assign d[293] = m1[176] ^ m2[176] ^ m3[176] ^ m1[59];
assign d[294] = m1[177] ^ m2[177] ^ m3[177] ^ m1[60];
assign d[295] = m1[178] ^ m2[178] ^ m3[178] ^ m1[61];
assign d[296] = m1[179] ^ m2[179] ^ m3[179] ^ m1[62];
assign d[297] = m1[180] ^ m2[180] ^ m3[180] ^ m1[63];
assign d[298] = m1[181] ^ m2[181] ^ m3[181] ^ m1[64];
assign d[299] = m1[182] ^ m2[182] ^ m3[182] ^ m1[65];
assign d[300] = m1[183] ^ m2[183] ^ m3[183] ^ m1[66];
assign d[301] = m1[184] ^ m2[184] ^ m3[184] ^ m1[67];
assign d[302] = m1[185] ^ m2[185] ^ m3[185] ^ m1[68];
assign d[303] = m1[186] ^ m2[186] ^ m3[186] ^ m1[69];
assign d[304] = m1[187] ^ m2[187] ^ m3[187] ^ m1[70];
assign d[305] = m1[188] ^ m2[188] ^ m3[188] ^ m1[71];
assign d[306] = m1[189] ^ m2[189] ^ m3[189] ^ m1[72];
assign d[307] = m1[190] ^ m2[190] ^ m3[190] ^ m1[73];
assign d[308] = m1[191] ^ m2[191] ^ m3[191] ^ m1[74];
assign d[309] = m1[192] ^ m2[192] ^ m3[192] ^ m1[75];
assign d[310] = m1[193] ^ m2[193] ^ m3[193] ^ m1[76];
assign d[311] = m1[194] ^ m2[194] ^ m3[194] ^ m1[77];
assign d[312] = m1[195] ^ m2[195] ^ m3[195] ^ m1[78];
assign d[313] = m1[196] ^ m2[196] ^ m3[196] ^ m1[79];
assign d[314] = m1[197] ^ m2[197] ^ m3[197] ^ m1[80];
assign d[315] = m1[198] ^ m2[198] ^ m3[198] ^ m1[81];
assign d[316] = m1[199] ^ m2[199] ^ m3[199] ^ m1[82];
assign d[317] = m1[200] ^ m2[200] ^ m3[200] ^ m1[83];
assign d[318] = m1[201] ^ m2[201] ^ m3[201] ^ m1[84];
assign d[319] = m1[202] ^ m2[202] ^ m3[202] ^ m1[85];
assign d[320] = m1[203] ^ m2[203] ^ m3[203] ^ m1[86];
assign d[321] = m1[204] ^ m2[204] ^ m3[204] ^ m1[87];
assign d[322] = m1[205] ^ m2[205] ^ m3[205] ^ m1[88];
assign d[323] = m1[206] ^ m2[206] ^ m3[206] ^ m1[89];
assign d[324] = m1[207] ^ m2[207] ^ m3[207] ^ m1[90];
assign d[325] = m1[208] ^ m2[208] ^ m3[208] ^ m1[91];
assign d[326] = m1[209] ^ m2[209] ^ m3[209] ^ m1[92];
assign d[327] = m1[210] ^ m2[210] ^ m3[210] ^ m1[93];
assign d[328] = m1[211] ^ m2[211] ^ m3[211] ^ m1[94];
assign d[329] = m1[212] ^ m2[212] ^ m3[212] ^ m1[95];
assign d[330] = m1[213] ^ m2[213] ^ m3[213] ^ m1[96];
assign d[331] = m1[214] ^ m2[214] ^ m3[214] ^ m1[97];
assign d[332] = m1[215] ^ m2[215] ^ m3[215] ^ m1[98];
assign d[333] = m1[216] ^ m2[216] ^ m3[216] ^ m1[99];
assign d[334] = m1[217] ^ m2[217] ^ m3[217] ^ m1[100];
assign d[335] = m1[218] ^ m2[218] ^ m3[218] ^ m1[101];
assign d[336] = m1[219] ^ m2[219] ^ m3[219] ^ m1[102];
assign d[337] = m1[220] ^ m2[220] ^ m3[220] ^ m1[103];
assign d[338] = m1[221] ^ m2[221] ^ m3[221] ^ m1[104];
assign d[339] = m1[222] ^ m2[222] ^ m3[222] ^ m1[105];
assign d[340] = m1[223] ^ m2[223] ^ m3[223] ^ m1[106];
assign d[341] = m1[224] ^ m2[224] ^ m3[224] ^ m1[107];
assign d[342] = m1[225] ^ m2[225] ^ m3[225] ^ m1[108];
assign d[343] = m1[226] ^ m2[226] ^ m3[226] ^ m1[109];
assign d[344] = m1[227] ^ m2[227] ^ m3[227] ^ m1[110];
assign d[345] = m1[228] ^ m2[228] ^ m3[228] ^ m1[111];
assign d[346] = m1[229] ^ m2[229] ^ m3[229] ^ m1[112];
assign d[347] = m1[230] ^ m2[230] ^ m3[230] ^ m1[113];
assign d[348] = m2[231] ^ m3[231] ^ m1[114];
assign d[349] = m2[232] ^ m3[232] ^ m1[115];
assign d[350] = m1[116];
assign d[351] = m1[117];
assign d[352] = m1[118];
assign d[353] = m1[119];
assign d[354] = m1[120];
assign d[355] = m1[121];
assign d[356] = m1[122];
assign d[357] = m1[123];
assign d[358] = m1[124];
assign d[359] = m1[125];
assign d[360] = m1[126];
assign d[361] = m1[127];
assign d[362] = m1[128];
assign d[363] = m1[129];
assign d[364] = m1[130];
assign d[365] = m1[131];
assign d[366] = m1[132];
assign d[367] = m1[133];
assign d[368] = m1[134];
assign d[369] = m1[135];
assign d[370] = m1[136];
assign d[371] = m1[137];
assign d[372] = m1[138];
assign d[373] = m1[139];
assign d[374] = m1[140];
assign d[375] = m1[141];
assign d[376] = m1[142];
assign d[377] = m1[143];
assign d[378] = m1[144];
assign d[379] = m1[145];
assign d[380] = m1[146];
assign d[381] = m1[147];
assign d[382] = m1[148];
assign d[383] = m1[149];
assign d[384] = m1[150];
assign d[385] = m1[151];
assign d[386] = m1[152];
assign d[387] = m1[153];
assign d[388] = m1[154];
assign d[389] = m1[155];
assign d[390] = m1[156];
assign d[391] = m1[157];
assign d[392] = m1[158];
assign d[393] = m1[159];
assign d[394] = m1[160];
assign d[395] = m1[161];
assign d[396] = m1[162];
assign d[397] = m1[163];
assign d[398] = m1[164];
assign d[399] = m1[165];
assign d[400] = m1[166];
assign d[401] = m1[167];
assign d[402] = m1[168];
assign d[403] = m1[169];
assign d[404] = m1[170];
assign d[405] = m1[171];
assign d[406] = m1[172];
assign d[407] = m1[173];
assign d[408] = m1[174];
assign d[409] = m1[175];
assign d[410] = m1[176];
assign d[411] = m1[177];
assign d[412] = m1[178];
assign d[413] = m1[179];
assign d[414] = m1[180];
assign d[415] = m1[181];
assign d[416] = m1[182];
assign d[417] = m1[183];
assign d[418] = m1[184];
assign d[419] = m1[185];
assign d[420] = m1[186];
assign d[421] = m1[187];
assign d[422] = m1[188];
assign d[423] = m1[189];
assign d[424] = m1[190];
assign d[425] = m1[191];
assign d[426] = m1[192];
assign d[427] = m1[193];
assign d[428] = m1[194];
assign d[429] = m1[195];
assign d[430] = m1[196];
assign d[431] = m1[197];
assign d[432] = m1[198];
assign d[433] = m1[199];
assign d[434] = m1[200];
assign d[435] = m1[201];
assign d[436] = m1[202];
assign d[437] = m1[203];
assign d[438] = m1[204];
assign d[439] = m1[205];
assign d[440] = m1[206];
assign d[441] = m1[207];
assign d[442] = m1[208];
assign d[443] = m1[209];
assign d[444] = m1[210];
assign d[445] = m1[211];
assign d[446] = m1[212];
assign d[447] = m1[213];
assign d[448] = m1[214];
assign d[449] = m1[215];
assign d[450] = m1[216];
assign d[451] = m1[217];
assign d[452] = m1[218];
assign d[453] = m1[219];
assign d[454] = m1[220];
assign d[455] = m1[221];
assign d[456] = m1[222];
assign d[457] = m1[223];
assign d[458] = m1[224];
assign d[459] = m1[225];
assign d[460] = m1[226];
assign d[461] = m1[227];
assign d[462] = m1[228];
assign d[463] = m1[229];
assign d[464] = m1[230];
endmodule
`endif
|
`timescale 1ns / 1ps
/*
Group Members: Luis Calderon and Warren Seto
Lab Name: Introduction to Xilinx (Lab 1)
Project Name: eng312_proj1
Design Name: half_adder_test.v
Design Description: Verilog Test Fixture created by ISE for module: half_adder
*/
module half_adder_test;
// Input Registers:
reg iA;
reg iB;
// Output Registers:
wire oSUM;
wire oCARRY;
// Instantiate the Unit Under Test (UUT)
half_adder uut
(
.iA(iA),
.iB(iB),
.oSUM(oSUM),
.oCARRY(oCARRY)
);
// The code below tests the half-adder by manually changing the values of each input register
initial begin
// Set the both input registers as 0 as a default
iA = 0;
iB = 0;
// For five seconds, set one register to 1 while leaving the other as its default 0
#5 iA = 0; iB = 1;
// For five seconds, set the other register to 1 while flipping the other to its default 0
#5 iA = 1; iB = 0;
// For five seconds, set both registers to 1
#5 iA = 1; iB = 1;
end
initial #25 $finish; // The test should run for a total of 25 nanoseconds
endmodule
|
//------------------------------------------------------------------------------
// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//------------------------------------------------------------------------------
// ***************************
// * DO NOT MODIFY THIS FILE *
// ***************************
`timescale 1ps/1ps
module gtwizard_ultrascale_v1_7_1_gte4_drp_arb
#(
parameter [9:0] ADDR_TX_PROGCLK_SEL = 10'h00C,
parameter [9:0] ADDR_TX_PROGDIV_CFG = 10'h03E, //GTY /GTH addresses are different (003E in GTH; 0057 in GTY)
parameter [9:0] ADDR_RX_PROGDIV_CFG = 10'h0C6,
parameter [9:0] ADDR_X0E1 = 10'h0E1,
parameter [9:0] ADDR_X079 = 10'h079,
parameter [9:0] ADDR_X114 = 10'h114,
parameter C_NUM_CLIENTS = 2,
parameter C_ADDR_WIDTH = 9,
parameter C_DATA_WIDTH = 16
)
(
input wire DCLK_I,
input wire RESET_I,
input wire TX_CAL_DONE_I,
input wire RX_CAL_DONE_I,
input wire [C_NUM_CLIENTS-1:0] DEN_USR_I,
input wire [C_NUM_CLIENTS-1:0] DWE_USR_I,
input wire [(C_ADDR_WIDTH*C_NUM_CLIENTS)-1:0] DADDR_USR_I,
input wire [(C_DATA_WIDTH*C_NUM_CLIENTS)-1:0] DI_USR_I,
output reg [(C_DATA_WIDTH*C_NUM_CLIENTS)-1:0] DO_USR_O = 'h0,
output reg [C_NUM_CLIENTS-1:0] DRDY_USR_O = 'h0,
output reg DEN_O = 1'b0,
output reg DWE_O = 1'b0,
output reg [C_ADDR_WIDTH-1:0] DADDR_O = 1'b0,
output reg [C_DATA_WIDTH-1:0] DI_O = 'h0,
input wire [C_DATA_WIDTH-1:0] DO_I,
input wire DRDY_I
);
//
// log base 2
//
function integer clogb2;
input integer depth;
integer d;
begin
if (depth == 0)
clogb2 = 1;
else
begin
d = depth;
for (clogb2=0; d > 0; clogb2 = clogb2+1)
d = d >> 1;
end
end
endfunction
reg [clogb2(C_NUM_CLIENTS)-1:0] idx = 'b0;
reg done = 1'b0;
reg rd = 1'b0;
reg wr = 1'b0;
reg [C_NUM_CLIENTS-1:0] en = 'h0;
reg [C_NUM_CLIENTS-1:0] we = 'h0;
reg [(C_DATA_WIDTH*C_NUM_CLIENTS)-1:0] data_i = 'h0;
reg [(C_ADDR_WIDTH*C_NUM_CLIENTS)-1:0] addr_i = 'h0;
reg [C_DATA_WIDTH-1:0] di = 'h0;
reg [C_ADDR_WIDTH-1:0] daddr = 'h0;
reg [C_DATA_WIDTH-1:0] do_r = 'h0;
//
// Arbitration state machine encodings
//
localparam [3:0] ARB_START = 4'd1;
localparam [3:0] ARB_WAIT = 4'd2;
localparam [3:0] ARB_REPORT = 4'd4;
localparam [3:0] ARB_INC = 4'd8;
reg [3:0] arb_state = ARB_START;
//
// DRP state machine encodings
//
localparam [6:0] DRP_WAIT = 7'd1;
localparam [6:0] DRP_READ = 7'd2;
localparam [6:0] DRP_READ_ACK = 7'd4;
localparam [6:0] DRP_MODIFY = 7'd8;
localparam [6:0] DRP_WRITE = 7'd16;
localparam [6:0] DRP_WRITE_ACK = 7'd32;
localparam [6:0] DRP_DONE = 7'd64;
reg [6:0] drp_state = DRP_WAIT;
reg [7:0] timeout_cntr = 0;
integer i;
//
// Register incoming transactions: grab data, address, write enable when DEN is high
// Clear internal enable when transaction is (eventually) finished
//
always @(posedge DCLK_I)
begin
if (RESET_I)
begin
en <= 'b0;
we <= 'b0;
data_i <= 'b0;
addr_i <= 'b0;
end
else
begin
if (DEN_USR_I[0]) begin
en[0] <= 1'b1; // this means this client wants to do a transaction
we[0] <= DWE_USR_I[0];
//data_i[(i*C_DATA_WIDTH) +: C_DATA_WIDTH] <= DI_USR_I[(i*C_DATA_WIDTH) +: C_DATA_WIDTH];
//addr_i[(i*C_ADDR_WIDTH) +: C_ADDR_WIDTH] <= DADDR_USR_I[(i*C_ADDR_WIDTH) +: C_ADDR_WIDTH];
// if cpll cal not done (mask) from cpll cal, if user tries to write, always save progdiv to temp holding place.
if (!TX_CAL_DONE_I && DADDR_USR_I[(0*C_ADDR_WIDTH) +: C_ADDR_WIDTH] == ADDR_TX_PROGDIV_CFG && DWE_USR_I[0]) begin
addr_i[(0*C_ADDR_WIDTH) +: C_ADDR_WIDTH] <= ADDR_X079;
data_i[(0*C_DATA_WIDTH) +: C_DATA_WIDTH] <= {1'b1,DI_USR_I[(0*C_DATA_WIDTH) +: C_DATA_WIDTH-1]};
end
else if (!TX_CAL_DONE_I && DADDR_USR_I[(0*C_ADDR_WIDTH) +: C_ADDR_WIDTH] == ADDR_TX_PROGCLK_SEL && DWE_USR_I[0]) begin
addr_i[(0*C_ADDR_WIDTH) +: C_ADDR_WIDTH] <= ADDR_X0E1;
data_i[(0*C_DATA_WIDTH) +: C_DATA_WIDTH] <= {1'b1,DI_USR_I[(0*C_DATA_WIDTH) +: C_DATA_WIDTH-1]};
end
else if (!RX_CAL_DONE_I && DADDR_USR_I[(0*C_ADDR_WIDTH) +: C_ADDR_WIDTH] == ADDR_RX_PROGDIV_CFG && DWE_USR_I[0]) begin
addr_i[(0*C_ADDR_WIDTH) +: C_ADDR_WIDTH] <= ADDR_X114;
data_i[(0*C_DATA_WIDTH) +: C_DATA_WIDTH] <= {1'b1,DI_USR_I[(0*C_DATA_WIDTH) +: C_DATA_WIDTH-1]};
end
else begin
//behave normal
addr_i[(0*C_ADDR_WIDTH) +: C_ADDR_WIDTH] <= DADDR_USR_I[(0*C_ADDR_WIDTH) +: C_ADDR_WIDTH];
data_i[(0*C_DATA_WIDTH) +: C_DATA_WIDTH] <= DI_USR_I[(0*C_DATA_WIDTH) +: C_DATA_WIDTH];
end
end
for (i = 1; i < C_NUM_CLIENTS; i= i+1)
begin
if (DEN_USR_I[i])
begin
en[i] <= 1'b1; // this means this client wants to do a transaction
we[i] <= DWE_USR_I[i];
data_i[(i*C_DATA_WIDTH) +: C_DATA_WIDTH] <= DI_USR_I[(i*C_DATA_WIDTH) +: C_DATA_WIDTH];
addr_i[(i*C_ADDR_WIDTH) +: C_ADDR_WIDTH] <= DADDR_USR_I[(i*C_ADDR_WIDTH) +: C_ADDR_WIDTH];
end
end
if (done)
begin
en[idx] <= 1'b0;
we[idx] <= 1'b0;
end
end
end
//
// Arbitration FSM - does a round-robin arbritration scheme
//
always @(posedge DCLK_I)
begin
if (RESET_I)
begin
idx <= 'b0;
di <= 'b0;
daddr <= 'b0;
rd <= 1'b0;
wr <= 1'b0;
arb_state <= ARB_START;
DRDY_USR_O <= 'b0;
DO_USR_O <= 'b0;
end
else
begin
case (arb_state)
ARB_START: begin
if (en[idx] == 1'b1)
begin
di <= data_i[idx*C_DATA_WIDTH +: C_DATA_WIDTH];
daddr <= addr_i[idx*C_ADDR_WIDTH +: C_ADDR_WIDTH];
rd <= !we[idx];
wr <= we[idx];
arb_state <= ARB_WAIT;
end
else
begin
rd <= 1'b0;
wr <= 1'b0;
arb_state <= ARB_INC;
end
end
ARB_WAIT: begin
rd <= 1'b0;
wr <= 1'b0;
if (done == 1'b1)
arb_state <= ARB_REPORT;
else
arb_state <= ARB_WAIT;
end
ARB_REPORT: begin
DRDY_USR_O[idx] <= 1'b1;
DO_USR_O[idx*C_DATA_WIDTH +: C_DATA_WIDTH] <= do_r;
arb_state <= ARB_INC;
end
ARB_INC : begin
DRDY_USR_O[idx] <= 1'b0;
if (idx == C_NUM_CLIENTS-1)
idx <= 1'b0;
else
idx <= idx + 1;
arb_state <= ARB_START;
end
default: arb_state <= ARB_START;
endcase
end
end
//
// DRP FSM - does the actual DRP read or write
//
always @(posedge DCLK_I)
begin
if (RESET_I)
begin
DEN_O <= 1'b0;
DWE_O <= 1'b0;
DI_O <= 16'h0000;
DADDR_O <= 'b0;
do_r <= 'b0;
drp_state <= DRP_WAIT;
done <= 1'b0;
end
else
begin
case (drp_state)
DRP_WAIT: begin
timeout_cntr <= 8'h0;
if (rd) drp_state <= DRP_READ;
else if (wr) drp_state <= DRP_WRITE;
else drp_state <= DRP_WAIT;
end
DRP_READ: begin
DEN_O <= 1'b1;
DWE_O <= 1'b0;
DADDR_O <= daddr;
timeout_cntr <= 8'h0;
done <= 1'b0;
drp_state <= DRP_READ_ACK;
end
DRP_READ_ACK: begin
DEN_O <= 1'b0;
DWE_O <= 1'b0;
timeout_cntr <= timeout_cntr + 1;
if (DRDY_I == 1'b1 || timeout_cntr == 8'hFF)
begin
do_r <= DO_I;
done <= 1'b1;
drp_state <= DRP_DONE;
end
else
drp_state <= DRP_READ_ACK;
end
DRP_WRITE: begin
DEN_O <= 1'b1;
DWE_O <= 1'b1;
DADDR_O <= daddr;
DI_O <= di;
timeout_cntr <= 8'h0;
done <= 1'b0;
drp_state <= DRP_WRITE_ACK;
end
DRP_WRITE_ACK: begin
DEN_O <= 1'b0;
DWE_O <= 1'b0;
timeout_cntr <= timeout_cntr + 1;
if (DRDY_I == 1'b1 || timeout_cntr == 8'hFF)
begin
do_r <= DO_I;
done <= 1'b1;
drp_state <= DRP_DONE;
end
else
drp_state <= DRP_WRITE_ACK;
end
DRP_DONE: begin
timeout_cntr <= 8'h0;
done <= 1'b0; // done was asserted in the previous state
drp_state <= DRP_WAIT;
end
default: drp_state <= DRP_WAIT;
endcase
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17.10.2017 11:51:09
// Design Name:
// Module Name: srio_testbench
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module srio_testbench();
// wire declarations
reg log_clk_t;
reg log_rst_t;
// signals into the DUT
wire iotx_tvalid_t; // Indicates that the information on the channel is valid
reg iotx_tready_t; // Indicates that the data from the source is accepted (if valid)
wire iotx_tlast_t; // Indicates the last beat of a packet
wire [63:0] iotx_tdata_t; // Packet header and data
wire [7:0] iotx_tkeep_t; // Indicates whether the content of the associated byte of data is valid
wire [31:0] iotx_tuser_t; // Consists of the Source ID and Destination ID
reg iorx_tvalid_t; // Indicates that the information on the channel is valid
wire iorx_tready_t; // Indicates that the data from the source is accepted (if valid)
reg iorx_tlast_t; // Indicates the last beat of a packet
reg [63:0] iorx_tdata_t; // Packet header and data
reg [7:0] iorx_tkeep_t; // Indicates whether the content of the associated byte of data is valid
reg [31:0] iorx_tuser_t; // Consists of the Source ID and Destination ID
reg [2:0] current_state;
reg [2:0] next_state;
reg [4:0] some_counter;
// FSM
localparam [2:0] IDLE_S = 3'h00;
localparam [2:0] SEND_SW_S = 3'h01; // erase flash
localparam [2:0] SEND_DT_S = 3'h02; // send data
localparam [2:0] SEND_RD_S = 3'h03; // set some values
localparam [2:0] PRE_SEND_S = 3'h04; // preparation to send
localparam [2:0] FINAL_S = 3'h05; // send data
srio_response srio_rx(
.log_clk ( log_clk_t ),
.log_rst ( log_rst_t ),
.src_id ( 8'hFF ),
.id_override ( 1'b0 ),
// Regs with request data (from DSP to FPGA)
.axis_iorx_tvalid ( iorx_tvalid_t ),
.axis_iorx_tready ( iorx_tready_t ),
.axis_iorx_tlast ( iorx_tlast_t ),
.axis_iorx_tdata ( iorx_tdata_t ),
.axis_iorx_tkeep ( iorx_tkeep_t ),
.axis_iorx_tuser ( iorx_tuser_t ),
// Regs with response data (from FPGA to DSP)
.axis_iotx_tvalid ( iotx_tvalid_t ),
.axis_iotx_tlast ( iotx_tlast_t ),
.axis_iotx_tdata ( iotx_tdata_t ),
.axis_iotx_tkeep ( iotx_tkeep_t ),
.axis_iotx_tuser ( iotx_tuser_t ),
.axis_iotx_tready ( iotx_tready_t )
);
initial begin
log_clk_t = 1'b1;
log_rst_t = 1'b0;
iotx_tready_t = 1'b1;
iorx_tvalid_t = 1'b0;
iorx_tlast_t = 1'b0;
iorx_tuser_t = 32'h00;
iorx_tdata_t = 64'h00;
iorx_tkeep_t = 8'b0;
current_state = IDLE_S;
some_counter = 5'b0;
$display("<< Running testbench >>");
end
always // ãåíåðàòîð clk
#10 log_clk_t = !log_clk_t; // 50 MHz
event reset_trigger; // îáúÿâëåíèå ñîáûòèé
event reset_done_trigger;
// áëîê ôîðìèðîâàíèÿ Reset
initial begin
forever begin // áåñêîíå÷íûé öèêë
@(reset_trigger); // æä¸ì ñîáûòèÿ reset_trigger
@(negedge log_clk_t); // æä¸ì negedge clk_t
log_rst_t = 1'b1; // ñáðîñ
@(negedge log_clk_t);
log_rst_t = 1'b0;
-> reset_done_trigger; // ñîîáùàåì, ÷òî reset âûïîëíåí
end
end
always @( posedge log_clk_t or posedge log_rst_t ) begin
if( log_rst_t )
current_state = IDLE_S;
else
current_state = next_state;
end
// next-state logic
always @( current_state, iotx_tlast_t, some_counter, iorx_tready_t ) begin
next_state = IDLE_S;
case( current_state )
IDLE_S: begin
next_state = PRE_SEND_S;
end
SEND_SW_S: begin
next_state = SEND_DT_S;
end
SEND_DT_S: begin
next_state = PRE_SEND_S;
end
SEND_RD_S: begin
next_state = PRE_SEND_S;
end
PRE_SEND_S: begin
if( iotx_tlast_t == 1'b1 )
next_state = FINAL_S;
else if( some_counter < 5'h04 )
next_state = SEND_RD_S;
else if( (iorx_tready_t == 1'b1) && (some_counter == 5'h00))
next_state = SEND_SW_S;
else
next_state = PRE_SEND_S;
end
FINAL_S: begin
$finish;
end
endcase
end
// Õîä ñèìóëÿöèè
/*
initial
begin: TEST_CASE
#5 -> reset_trigger; // ñäåëàòü reset
@ (reset_done_trigger); // æä¸ì çàâåðøåíèÿ reset
end
*/
always @( current_state ) begin
case( current_state )
IDLE_S: begin
#5 -> reset_trigger; // ñäåëàòü reset
@ (reset_done_trigger); // æä¸ì çàâåðøåíèÿ reset
end
SEND_SW_S: begin
iorx_tuser_t = 32'h00cb00ff;
iorx_tdata_t = 64'h006020001093de10;
iorx_tkeep_t = 8'hFF;
iorx_tvalid_t = 1'b1;
iorx_tlast_t = 1'b0;
end
SEND_DT_S: begin
iorx_tdata_t = 64'hddbbddbbddbbddbb;
iorx_tvalid_t = 1'b1;
iorx_tlast_t = 1'b1;
iorx_tuser_t = 32'h00cb00ff;
some_counter = some_counter + 1'b1;
end
SEND_RD_S: begin
iorx_tdata_t = 64'h012420f01093de10;
iorx_tvalid_t = 1'b1;
iorx_tlast_t = 1'b1;
iorx_tuser_t = 32'h00cb00ff;
some_counter = some_counter + 1'b1;
end
PRE_SEND_S: begin
iorx_tvalid_t = 1'b0;
iorx_tlast_t = 1'b0;
iorx_tuser_t = 32'h00cb00ff;
iorx_tdata_t = 64'h00;
iorx_tkeep_t = 8'hFF;
end
endcase
end
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2013 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file Color_ROM.v when simulating
// the core, Color_ROM. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module Color_ROM(
clka,
addra,
douta
);
input clka;
input [11 : 0] addra;
output [7 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V6_2 #(
.C_ADDRA_WIDTH(12),
.C_ADDRB_WIDTH(12),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("Color_ROM.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(4000),
.C_READ_DEPTH_B(4000),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(1),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(4000),
.C_WRITE_DEPTH_B(4000),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan3e")
)
inst (
.CLKA(clka),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common single-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// single-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// - Artisan Single-Port Sync RAM ////
//// - Avant! Two-Port Sync RAM (*) ////
//// - Virage Single-Port Sync RAM ////
//// - Virtual Silicon Single-Port Sync RAM ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Xilinx Virtex RAMB16 ////
//// - Xilinx Virtex RAMB4 ////
//// - Altera LPM ////
//// ////
//// To Do: ////
//// - xilinx rams need external tri-state logic ////
//// - fix avant! two-port ram ////
//// - add additional RAMs ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_spram_1024x8.v,v $
// Revision 1.1 2006-12-21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.9 2005/10/19 11:37:56 jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.8 2004/06/08 18:15:32 lampret
// Changed behavior of the simulation generic models
//
// Revision 1.7 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.3.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.3 2003/04/07 01:19:07 lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.2 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/11/02 18:57:14 lampret
// Modified virtual silicon instantiations.
//
// Revision 1.7 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.1 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.2 2001/07/30 05:38:02 lampret
// Adding empty directories required by HDL coding guidelines
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_spram_1024x8(
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, doq
);
//
// Default address and data buses width
//
parameter aw = 10;
parameter dw = 8;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input we; // Write enable input
input oe; // Output enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Internal wires and registers
//
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
`ifdef OR1200_ARTISAN_SSP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_1024x8 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_1024x8_bist artisan_ssp(
`else
art_hssp_1024x8 artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
.WEN(~we),
.A(addr),
.D(di),
.OEN(~oe),
.Q(doq)
);
`else
`ifdef OR1200_AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
.web(~we),
.reb(),
.oeb(~oe),
.rcsb(),
.wcsb(),
.ra(addr),
.wa(addr),
.di(di),
.doq(doq)
);
`else
`ifdef OR1200_VIRAGE_SSP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
.clk(clk),
.adr(addr),
.d(di),
.we(we),
.oe(oe),
.me(ce),
.q(doq)
);
`else
`ifdef OR1200_VIRTUALSILICON_SSP
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_1024x8 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_1024x8_bist vs_ssp(
`else
vs_hdsp_1024x8 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
.DI(di),
.WEN(~we),
.CEN(~ce),
.OEN(~oe),
.DOUT(doq)
);
`else
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S4 ramb4_s4_0(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[3:0]),
.EN(ce),
.WE(we),
.DO(doq[3:0])
);
//
// Block 1
//
RAMB4_S4 ramb4_s4_1(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[7:4]),
.EN(ce),
.WE(we),
.DO(doq[7:4])
);
`else
`ifdef OR1200_XILINX_RAMB16
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
RAMB16_S9 ramb16_s9(
.CLK(clk),
.SSR(rst),
.ADDR({1'b0,addr}),
.DI(di),
.DIP(1'b0),
.EN(ce),
.WE(we),
.DO(doq),
.DOP()
);
`else
`ifdef OR1200_ALTERA_LPM
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
wire wr;
assign wr = ce & we;
initial $display("Using Altera LPM.");
lpm_ram_dq lpm_ram_dq_component (
.address(addr),
.inclock(clk),
.outclock(clk),
.data(di),
.we(wr),
.q(doq)
);
defparam lpm_ram_dq_component.lpm_width = dw,
lpm_ram_dq_component.lpm_widthad = aw,
lpm_ram_dq_component.lpm_indata = "REGISTERED",
lpm_ram_dq_component.lpm_address_control = "REGISTERED",
lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
// examplar attribute lpm_ram_dq_component NOOPT TRUE
`else
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
//
// RAM address register
//
always @(posedge clk or posedge rst)
if (rst)
addr_reg <= #1 {aw{1'b0}};
else if (ce)
addr_reg <= #1 addr;
//
// RAM write
//
always @(posedge clk)
if (ce && we)
mem[addr] <= #1 di;
`endif // !OR1200_ALTERA_LPM
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`endif // !OR1200_VIRTUALSILICON_SSP
`endif // !OR1200_VIRAGE_SSP
`endif // !OR1200_AVANT_ATP
`endif // !OR1200_ARTISAN_SSP
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR2_BEHAVIORAL_V
`define SKY130_FD_SC_HD__NOR2_BEHAVIORAL_V
/**
* nor2: 2-input NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__nor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, A, B );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR2_BEHAVIORAL_V |
`timescale 1ns / 1ps
`define SIM_FULL
module async_fifo_t;
// ins
reg wclk;
reg wrst;
reg [7:0] data_i;
reg ack_i;
reg rclk;
reg rrst;
reg pop_i;
async_fifo uut(
.wclk(wclk), .wrst(wrst), .data_i(data_i), .ack_i(ack_i),
.rclk(rclk), .rrst(rrst), .pop_i(pop_i));
parameter T_WCLK = 10;
parameter T_RCLK = 24;
always #(T_WCLK/2) wclk = ~wclk;
always #(T_RCLK/2) rclk = ~rclk;
initial begin
$dumpfile("async_fifo_t.lxt");
$dumpvars(0, async_fifo_t);
#(3000);
$finish(2);
end
initial begin
wclk = 0;
wrst = 0;
ack_i = 0;
data_i = 8'h20;
#(T_WCLK);
wrst = 1;
#(T_WCLK);
wrst = 0;
end
always begin
#(T_WCLK*15);
data_i = data_i + 1;
ack_i = 1;
#(T_WCLK);
ack_i = 0;
end
initial begin
rclk = 0;
rrst = 0;
pop_i = 0;
#(T_RCLK);
rrst = 1;
#(T_RCLK);
rrst = 0;
end
`ifndef SIM_FULL
always @(posedge rclk) begin
pop_i <= 0;
if (!uut.empty_o) begin
$display("read %h", uut.data_o);
pop_i <= 1;
end
end
`endif
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A221OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__A221OI_BEHAVIORAL_PP_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a221oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
nor nor0 (nor0_out_Y , and0_out, C1, and1_out);
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A221OI_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21BOI_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__A21BOI_PP_BLACKBOX_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a21boi (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21BOI_PP_BLACKBOX_V
|
/*******************************************************
* File Name : hdl/ks26.v
* Module Name : Karatsuba Multiplier
* Author : Chester Rebeiro
* Institute : Indian Institute of Technology, Madras
* Creation Time :
* Comment : Automatically generated from general.c
********************************************************/
`ifndef __KS_26_V__
`define __KS_26_V__
module Hks26(a, b, d);
input wire [0:25] a;
input wire [0:25] b;
output wire [0:50] d;
wire m0, m1, m2, m3, m4, m5, m6, m7, m8, m9, m10, m11, m12, m13, m14, m15, m16, m17, m18, m19, m20, m21, m22, m23, m24, m25;
wire m0_1, m0_2, m0_3, m0_4, m0_5, m0_6, m0_7, m0_8, m0_9, m0_10, m0_11, m0_12, m0_13, m0_14, m0_15, m0_16, m0_17, m0_18, m0_19, m0_20, m0_21, m0_22, m0_23, m0_24, m0_25;
wire m1_2, m1_3, m1_4, m1_5, m1_6, m1_7, m1_8, m1_9, m1_10, m1_11, m1_12, m1_13, m1_14, m1_15, m1_16, m1_17, m1_18, m1_19, m1_20, m1_21, m1_22, m1_23, m1_24, m1_25;
wire m2_3, m2_4, m2_5, m2_6, m2_7, m2_8, m2_9, m2_10, m2_11, m2_12, m2_13, m2_14, m2_15, m2_16, m2_17, m2_18, m2_19, m2_20, m2_21, m2_22, m2_23, m2_24, m2_25;
wire m3_4, m3_5, m3_6, m3_7, m3_8, m3_9, m3_10, m3_11, m3_12, m3_13, m3_14, m3_15, m3_16, m3_17, m3_18, m3_19, m3_20, m3_21, m3_22, m3_23, m3_24, m3_25;
wire m4_5, m4_6, m4_7, m4_8, m4_9, m4_10, m4_11, m4_12, m4_13, m4_14, m4_15, m4_16, m4_17, m4_18, m4_19, m4_20, m4_21, m4_22, m4_23, m4_24, m4_25;
wire m5_6, m5_7, m5_8, m5_9, m5_10, m5_11, m5_12, m5_13, m5_14, m5_15, m5_16, m5_17, m5_18, m5_19, m5_20, m5_21, m5_22, m5_23, m5_24, m5_25;
wire m6_7, m6_8, m6_9, m6_10, m6_11, m6_12, m6_13, m6_14, m6_15, m6_16, m6_17, m6_18, m6_19, m6_20, m6_21, m6_22, m6_23, m6_24, m6_25;
wire m7_8, m7_9, m7_10, m7_11, m7_12, m7_13, m7_14, m7_15, m7_16, m7_17, m7_18, m7_19, m7_20, m7_21, m7_22, m7_23, m7_24, m7_25;
wire m8_9, m8_10, m8_11, m8_12, m8_13, m8_14, m8_15, m8_16, m8_17, m8_18, m8_19, m8_20, m8_21, m8_22, m8_23, m8_24, m8_25;
wire m9_10, m9_11, m9_12, m9_13, m9_14, m9_15, m9_16, m9_17, m9_18, m9_19, m9_20, m9_21, m9_22, m9_23, m9_24, m9_25;
wire m10_11, m10_12, m10_13, m10_14, m10_15, m10_16, m10_17, m10_18, m10_19, m10_20, m10_21, m10_22, m10_23, m10_24, m10_25;
wire m11_12, m11_13, m11_14, m11_15, m11_16, m11_17, m11_18, m11_19, m11_20, m11_21, m11_22, m11_23, m11_24, m11_25;
wire m12_13, m12_14, m12_15, m12_16, m12_17, m12_18, m12_19, m12_20, m12_21, m12_22, m12_23, m12_24, m12_25;
wire m13_14, m13_15, m13_16, m13_17, m13_18, m13_19, m13_20, m13_21, m13_22, m13_23, m13_24, m13_25;
wire m14_15, m14_16, m14_17, m14_18, m14_19, m14_20, m14_21, m14_22, m14_23, m14_24, m14_25;
wire m15_16, m15_17, m15_18, m15_19, m15_20, m15_21, m15_22, m15_23, m15_24, m15_25;
wire m16_17, m16_18, m16_19, m16_20, m16_21, m16_22, m16_23, m16_24, m16_25;
wire m17_18, m17_19, m17_20, m17_21, m17_22, m17_23, m17_24, m17_25;
wire m18_19, m18_20, m18_21, m18_22, m18_23, m18_24, m18_25;
wire m19_20, m19_21, m19_22, m19_23, m19_24, m19_25;
wire m20_21, m20_22, m20_23, m20_24, m20_25;
wire m21_22, m21_23, m21_24, m21_25;
wire m22_23, m22_24, m22_25;
wire m23_24, m23_25;
wire m24_25;
assign m0 = a[0] & b[0];
assign m1 = a[1] & b[1];
assign m2 = a[2] & b[2];
assign m3 = a[3] & b[3];
assign m4 = a[4] & b[4];
assign m5 = a[5] & b[5];
assign m6 = a[6] & b[6];
assign m7 = a[7] & b[7];
assign m8 = a[8] & b[8];
assign m9 = a[9] & b[9];
assign m10 = a[10] & b[10];
assign m11 = a[11] & b[11];
assign m12 = a[12] & b[12];
assign m13 = a[13] & b[13];
assign m14 = a[14] & b[14];
assign m15 = a[15] & b[15];
assign m16 = a[16] & b[16];
assign m17 = a[17] & b[17];
assign m18 = a[18] & b[18];
assign m19 = a[19] & b[19];
assign m20 = a[20] & b[20];
assign m21 = a[21] & b[21];
assign m22 = a[22] & b[22];
assign m23 = a[23] & b[23];
assign m24 = a[24] & b[24];
assign m25 = a[25] & b[25];
assign m0_1 = (a[0] ^ a[1]) & (b[0] ^ b[1]);
assign m0_2 = (a[0] ^ a[2]) & (b[0] ^ b[2]);
assign m0_3 = (a[0] ^ a[3]) & (b[0] ^ b[3]);
assign m0_4 = (a[0] ^ a[4]) & (b[0] ^ b[4]);
assign m0_5 = (a[0] ^ a[5]) & (b[0] ^ b[5]);
assign m0_6 = (a[0] ^ a[6]) & (b[0] ^ b[6]);
assign m0_7 = (a[0] ^ a[7]) & (b[0] ^ b[7]);
assign m0_8 = (a[0] ^ a[8]) & (b[0] ^ b[8]);
assign m0_9 = (a[0] ^ a[9]) & (b[0] ^ b[9]);
assign m0_10 = (a[0] ^ a[10]) & (b[0] ^ b[10]);
assign m0_11 = (a[0] ^ a[11]) & (b[0] ^ b[11]);
assign m0_12 = (a[0] ^ a[12]) & (b[0] ^ b[12]);
assign m0_13 = (a[0] ^ a[13]) & (b[0] ^ b[13]);
assign m0_14 = (a[0] ^ a[14]) & (b[0] ^ b[14]);
assign m0_15 = (a[0] ^ a[15]) & (b[0] ^ b[15]);
assign m0_16 = (a[0] ^ a[16]) & (b[0] ^ b[16]);
assign m0_17 = (a[0] ^ a[17]) & (b[0] ^ b[17]);
assign m0_18 = (a[0] ^ a[18]) & (b[0] ^ b[18]);
assign m0_19 = (a[0] ^ a[19]) & (b[0] ^ b[19]);
assign m0_20 = (a[0] ^ a[20]) & (b[0] ^ b[20]);
assign m0_21 = (a[0] ^ a[21]) & (b[0] ^ b[21]);
assign m0_22 = (a[0] ^ a[22]) & (b[0] ^ b[22]);
assign m0_23 = (a[0] ^ a[23]) & (b[0] ^ b[23]);
assign m0_24 = (a[0] ^ a[24]) & (b[0] ^ b[24]);
assign m0_25 = (a[0] ^ a[25]) & (b[0] ^ b[25]);
assign m1_2 = (a[1] ^ a[2]) & (b[1] ^ b[2]);
assign m1_3 = (a[1] ^ a[3]) & (b[1] ^ b[3]);
assign m1_4 = (a[1] ^ a[4]) & (b[1] ^ b[4]);
assign m1_5 = (a[1] ^ a[5]) & (b[1] ^ b[5]);
assign m1_6 = (a[1] ^ a[6]) & (b[1] ^ b[6]);
assign m1_7 = (a[1] ^ a[7]) & (b[1] ^ b[7]);
assign m1_8 = (a[1] ^ a[8]) & (b[1] ^ b[8]);
assign m1_9 = (a[1] ^ a[9]) & (b[1] ^ b[9]);
assign m1_10 = (a[1] ^ a[10]) & (b[1] ^ b[10]);
assign m1_11 = (a[1] ^ a[11]) & (b[1] ^ b[11]);
assign m1_12 = (a[1] ^ a[12]) & (b[1] ^ b[12]);
assign m1_13 = (a[1] ^ a[13]) & (b[1] ^ b[13]);
assign m1_14 = (a[1] ^ a[14]) & (b[1] ^ b[14]);
assign m1_15 = (a[1] ^ a[15]) & (b[1] ^ b[15]);
assign m1_16 = (a[1] ^ a[16]) & (b[1] ^ b[16]);
assign m1_17 = (a[1] ^ a[17]) & (b[1] ^ b[17]);
assign m1_18 = (a[1] ^ a[18]) & (b[1] ^ b[18]);
assign m1_19 = (a[1] ^ a[19]) & (b[1] ^ b[19]);
assign m1_20 = (a[1] ^ a[20]) & (b[1] ^ b[20]);
assign m1_21 = (a[1] ^ a[21]) & (b[1] ^ b[21]);
assign m1_22 = (a[1] ^ a[22]) & (b[1] ^ b[22]);
assign m1_23 = (a[1] ^ a[23]) & (b[1] ^ b[23]);
assign m1_24 = (a[1] ^ a[24]) & (b[1] ^ b[24]);
assign m1_25 = (a[1] ^ a[25]) & (b[1] ^ b[25]);
assign m2_3 = (a[2] ^ a[3]) & (b[2] ^ b[3]);
assign m2_4 = (a[2] ^ a[4]) & (b[2] ^ b[4]);
assign m2_5 = (a[2] ^ a[5]) & (b[2] ^ b[5]);
assign m2_6 = (a[2] ^ a[6]) & (b[2] ^ b[6]);
assign m2_7 = (a[2] ^ a[7]) & (b[2] ^ b[7]);
assign m2_8 = (a[2] ^ a[8]) & (b[2] ^ b[8]);
assign m2_9 = (a[2] ^ a[9]) & (b[2] ^ b[9]);
assign m2_10 = (a[2] ^ a[10]) & (b[2] ^ b[10]);
assign m2_11 = (a[2] ^ a[11]) & (b[2] ^ b[11]);
assign m2_12 = (a[2] ^ a[12]) & (b[2] ^ b[12]);
assign m2_13 = (a[2] ^ a[13]) & (b[2] ^ b[13]);
assign m2_14 = (a[2] ^ a[14]) & (b[2] ^ b[14]);
assign m2_15 = (a[2] ^ a[15]) & (b[2] ^ b[15]);
assign m2_16 = (a[2] ^ a[16]) & (b[2] ^ b[16]);
assign m2_17 = (a[2] ^ a[17]) & (b[2] ^ b[17]);
assign m2_18 = (a[2] ^ a[18]) & (b[2] ^ b[18]);
assign m2_19 = (a[2] ^ a[19]) & (b[2] ^ b[19]);
assign m2_20 = (a[2] ^ a[20]) & (b[2] ^ b[20]);
assign m2_21 = (a[2] ^ a[21]) & (b[2] ^ b[21]);
assign m2_22 = (a[2] ^ a[22]) & (b[2] ^ b[22]);
assign m2_23 = (a[2] ^ a[23]) & (b[2] ^ b[23]);
assign m2_24 = (a[2] ^ a[24]) & (b[2] ^ b[24]);
assign m2_25 = (a[2] ^ a[25]) & (b[2] ^ b[25]);
assign m3_4 = (a[3] ^ a[4]) & (b[3] ^ b[4]);
assign m3_5 = (a[3] ^ a[5]) & (b[3] ^ b[5]);
assign m3_6 = (a[3] ^ a[6]) & (b[3] ^ b[6]);
assign m3_7 = (a[3] ^ a[7]) & (b[3] ^ b[7]);
assign m3_8 = (a[3] ^ a[8]) & (b[3] ^ b[8]);
assign m3_9 = (a[3] ^ a[9]) & (b[3] ^ b[9]);
assign m3_10 = (a[3] ^ a[10]) & (b[3] ^ b[10]);
assign m3_11 = (a[3] ^ a[11]) & (b[3] ^ b[11]);
assign m3_12 = (a[3] ^ a[12]) & (b[3] ^ b[12]);
assign m3_13 = (a[3] ^ a[13]) & (b[3] ^ b[13]);
assign m3_14 = (a[3] ^ a[14]) & (b[3] ^ b[14]);
assign m3_15 = (a[3] ^ a[15]) & (b[3] ^ b[15]);
assign m3_16 = (a[3] ^ a[16]) & (b[3] ^ b[16]);
assign m3_17 = (a[3] ^ a[17]) & (b[3] ^ b[17]);
assign m3_18 = (a[3] ^ a[18]) & (b[3] ^ b[18]);
assign m3_19 = (a[3] ^ a[19]) & (b[3] ^ b[19]);
assign m3_20 = (a[3] ^ a[20]) & (b[3] ^ b[20]);
assign m3_21 = (a[3] ^ a[21]) & (b[3] ^ b[21]);
assign m3_22 = (a[3] ^ a[22]) & (b[3] ^ b[22]);
assign m3_23 = (a[3] ^ a[23]) & (b[3] ^ b[23]);
assign m3_24 = (a[3] ^ a[24]) & (b[3] ^ b[24]);
assign m3_25 = (a[3] ^ a[25]) & (b[3] ^ b[25]);
assign m4_5 = (a[4] ^ a[5]) & (b[4] ^ b[5]);
assign m4_6 = (a[4] ^ a[6]) & (b[4] ^ b[6]);
assign m4_7 = (a[4] ^ a[7]) & (b[4] ^ b[7]);
assign m4_8 = (a[4] ^ a[8]) & (b[4] ^ b[8]);
assign m4_9 = (a[4] ^ a[9]) & (b[4] ^ b[9]);
assign m4_10 = (a[4] ^ a[10]) & (b[4] ^ b[10]);
assign m4_11 = (a[4] ^ a[11]) & (b[4] ^ b[11]);
assign m4_12 = (a[4] ^ a[12]) & (b[4] ^ b[12]);
assign m4_13 = (a[4] ^ a[13]) & (b[4] ^ b[13]);
assign m4_14 = (a[4] ^ a[14]) & (b[4] ^ b[14]);
assign m4_15 = (a[4] ^ a[15]) & (b[4] ^ b[15]);
assign m4_16 = (a[4] ^ a[16]) & (b[4] ^ b[16]);
assign m4_17 = (a[4] ^ a[17]) & (b[4] ^ b[17]);
assign m4_18 = (a[4] ^ a[18]) & (b[4] ^ b[18]);
assign m4_19 = (a[4] ^ a[19]) & (b[4] ^ b[19]);
assign m4_20 = (a[4] ^ a[20]) & (b[4] ^ b[20]);
assign m4_21 = (a[4] ^ a[21]) & (b[4] ^ b[21]);
assign m4_22 = (a[4] ^ a[22]) & (b[4] ^ b[22]);
assign m4_23 = (a[4] ^ a[23]) & (b[4] ^ b[23]);
assign m4_24 = (a[4] ^ a[24]) & (b[4] ^ b[24]);
assign m4_25 = (a[4] ^ a[25]) & (b[4] ^ b[25]);
assign m5_6 = (a[5] ^ a[6]) & (b[5] ^ b[6]);
assign m5_7 = (a[5] ^ a[7]) & (b[5] ^ b[7]);
assign m5_8 = (a[5] ^ a[8]) & (b[5] ^ b[8]);
assign m5_9 = (a[5] ^ a[9]) & (b[5] ^ b[9]);
assign m5_10 = (a[5] ^ a[10]) & (b[5] ^ b[10]);
assign m5_11 = (a[5] ^ a[11]) & (b[5] ^ b[11]);
assign m5_12 = (a[5] ^ a[12]) & (b[5] ^ b[12]);
assign m5_13 = (a[5] ^ a[13]) & (b[5] ^ b[13]);
assign m5_14 = (a[5] ^ a[14]) & (b[5] ^ b[14]);
assign m5_15 = (a[5] ^ a[15]) & (b[5] ^ b[15]);
assign m5_16 = (a[5] ^ a[16]) & (b[5] ^ b[16]);
assign m5_17 = (a[5] ^ a[17]) & (b[5] ^ b[17]);
assign m5_18 = (a[5] ^ a[18]) & (b[5] ^ b[18]);
assign m5_19 = (a[5] ^ a[19]) & (b[5] ^ b[19]);
assign m5_20 = (a[5] ^ a[20]) & (b[5] ^ b[20]);
assign m5_21 = (a[5] ^ a[21]) & (b[5] ^ b[21]);
assign m5_22 = (a[5] ^ a[22]) & (b[5] ^ b[22]);
assign m5_23 = (a[5] ^ a[23]) & (b[5] ^ b[23]);
assign m5_24 = (a[5] ^ a[24]) & (b[5] ^ b[24]);
assign m5_25 = (a[5] ^ a[25]) & (b[5] ^ b[25]);
assign m6_7 = (a[6] ^ a[7]) & (b[6] ^ b[7]);
assign m6_8 = (a[6] ^ a[8]) & (b[6] ^ b[8]);
assign m6_9 = (a[6] ^ a[9]) & (b[6] ^ b[9]);
assign m6_10 = (a[6] ^ a[10]) & (b[6] ^ b[10]);
assign m6_11 = (a[6] ^ a[11]) & (b[6] ^ b[11]);
assign m6_12 = (a[6] ^ a[12]) & (b[6] ^ b[12]);
assign m6_13 = (a[6] ^ a[13]) & (b[6] ^ b[13]);
assign m6_14 = (a[6] ^ a[14]) & (b[6] ^ b[14]);
assign m6_15 = (a[6] ^ a[15]) & (b[6] ^ b[15]);
assign m6_16 = (a[6] ^ a[16]) & (b[6] ^ b[16]);
assign m6_17 = (a[6] ^ a[17]) & (b[6] ^ b[17]);
assign m6_18 = (a[6] ^ a[18]) & (b[6] ^ b[18]);
assign m6_19 = (a[6] ^ a[19]) & (b[6] ^ b[19]);
assign m6_20 = (a[6] ^ a[20]) & (b[6] ^ b[20]);
assign m6_21 = (a[6] ^ a[21]) & (b[6] ^ b[21]);
assign m6_22 = (a[6] ^ a[22]) & (b[6] ^ b[22]);
assign m6_23 = (a[6] ^ a[23]) & (b[6] ^ b[23]);
assign m6_24 = (a[6] ^ a[24]) & (b[6] ^ b[24]);
assign m6_25 = (a[6] ^ a[25]) & (b[6] ^ b[25]);
assign m7_8 = (a[7] ^ a[8]) & (b[7] ^ b[8]);
assign m7_9 = (a[7] ^ a[9]) & (b[7] ^ b[9]);
assign m7_10 = (a[7] ^ a[10]) & (b[7] ^ b[10]);
assign m7_11 = (a[7] ^ a[11]) & (b[7] ^ b[11]);
assign m7_12 = (a[7] ^ a[12]) & (b[7] ^ b[12]);
assign m7_13 = (a[7] ^ a[13]) & (b[7] ^ b[13]);
assign m7_14 = (a[7] ^ a[14]) & (b[7] ^ b[14]);
assign m7_15 = (a[7] ^ a[15]) & (b[7] ^ b[15]);
assign m7_16 = (a[7] ^ a[16]) & (b[7] ^ b[16]);
assign m7_17 = (a[7] ^ a[17]) & (b[7] ^ b[17]);
assign m7_18 = (a[7] ^ a[18]) & (b[7] ^ b[18]);
assign m7_19 = (a[7] ^ a[19]) & (b[7] ^ b[19]);
assign m7_20 = (a[7] ^ a[20]) & (b[7] ^ b[20]);
assign m7_21 = (a[7] ^ a[21]) & (b[7] ^ b[21]);
assign m7_22 = (a[7] ^ a[22]) & (b[7] ^ b[22]);
assign m7_23 = (a[7] ^ a[23]) & (b[7] ^ b[23]);
assign m7_24 = (a[7] ^ a[24]) & (b[7] ^ b[24]);
assign m7_25 = (a[7] ^ a[25]) & (b[7] ^ b[25]);
assign m8_9 = (a[8] ^ a[9]) & (b[8] ^ b[9]);
assign m8_10 = (a[8] ^ a[10]) & (b[8] ^ b[10]);
assign m8_11 = (a[8] ^ a[11]) & (b[8] ^ b[11]);
assign m8_12 = (a[8] ^ a[12]) & (b[8] ^ b[12]);
assign m8_13 = (a[8] ^ a[13]) & (b[8] ^ b[13]);
assign m8_14 = (a[8] ^ a[14]) & (b[8] ^ b[14]);
assign m8_15 = (a[8] ^ a[15]) & (b[8] ^ b[15]);
assign m8_16 = (a[8] ^ a[16]) & (b[8] ^ b[16]);
assign m8_17 = (a[8] ^ a[17]) & (b[8] ^ b[17]);
assign m8_18 = (a[8] ^ a[18]) & (b[8] ^ b[18]);
assign m8_19 = (a[8] ^ a[19]) & (b[8] ^ b[19]);
assign m8_20 = (a[8] ^ a[20]) & (b[8] ^ b[20]);
assign m8_21 = (a[8] ^ a[21]) & (b[8] ^ b[21]);
assign m8_22 = (a[8] ^ a[22]) & (b[8] ^ b[22]);
assign m8_23 = (a[8] ^ a[23]) & (b[8] ^ b[23]);
assign m8_24 = (a[8] ^ a[24]) & (b[8] ^ b[24]);
assign m8_25 = (a[8] ^ a[25]) & (b[8] ^ b[25]);
assign m9_10 = (a[9] ^ a[10]) & (b[9] ^ b[10]);
assign m9_11 = (a[9] ^ a[11]) & (b[9] ^ b[11]);
assign m9_12 = (a[9] ^ a[12]) & (b[9] ^ b[12]);
assign m9_13 = (a[9] ^ a[13]) & (b[9] ^ b[13]);
assign m9_14 = (a[9] ^ a[14]) & (b[9] ^ b[14]);
assign m9_15 = (a[9] ^ a[15]) & (b[9] ^ b[15]);
assign m9_16 = (a[9] ^ a[16]) & (b[9] ^ b[16]);
assign m9_17 = (a[9] ^ a[17]) & (b[9] ^ b[17]);
assign m9_18 = (a[9] ^ a[18]) & (b[9] ^ b[18]);
assign m9_19 = (a[9] ^ a[19]) & (b[9] ^ b[19]);
assign m9_20 = (a[9] ^ a[20]) & (b[9] ^ b[20]);
assign m9_21 = (a[9] ^ a[21]) & (b[9] ^ b[21]);
assign m9_22 = (a[9] ^ a[22]) & (b[9] ^ b[22]);
assign m9_23 = (a[9] ^ a[23]) & (b[9] ^ b[23]);
assign m9_24 = (a[9] ^ a[24]) & (b[9] ^ b[24]);
assign m9_25 = (a[9] ^ a[25]) & (b[9] ^ b[25]);
assign m10_11 = (a[10] ^ a[11]) & (b[10] ^ b[11]);
assign m10_12 = (a[10] ^ a[12]) & (b[10] ^ b[12]);
assign m10_13 = (a[10] ^ a[13]) & (b[10] ^ b[13]);
assign m10_14 = (a[10] ^ a[14]) & (b[10] ^ b[14]);
assign m10_15 = (a[10] ^ a[15]) & (b[10] ^ b[15]);
assign m10_16 = (a[10] ^ a[16]) & (b[10] ^ b[16]);
assign m10_17 = (a[10] ^ a[17]) & (b[10] ^ b[17]);
assign m10_18 = (a[10] ^ a[18]) & (b[10] ^ b[18]);
assign m10_19 = (a[10] ^ a[19]) & (b[10] ^ b[19]);
assign m10_20 = (a[10] ^ a[20]) & (b[10] ^ b[20]);
assign m10_21 = (a[10] ^ a[21]) & (b[10] ^ b[21]);
assign m10_22 = (a[10] ^ a[22]) & (b[10] ^ b[22]);
assign m10_23 = (a[10] ^ a[23]) & (b[10] ^ b[23]);
assign m10_24 = (a[10] ^ a[24]) & (b[10] ^ b[24]);
assign m10_25 = (a[10] ^ a[25]) & (b[10] ^ b[25]);
assign m11_12 = (a[11] ^ a[12]) & (b[11] ^ b[12]);
assign m11_13 = (a[11] ^ a[13]) & (b[11] ^ b[13]);
assign m11_14 = (a[11] ^ a[14]) & (b[11] ^ b[14]);
assign m11_15 = (a[11] ^ a[15]) & (b[11] ^ b[15]);
assign m11_16 = (a[11] ^ a[16]) & (b[11] ^ b[16]);
assign m11_17 = (a[11] ^ a[17]) & (b[11] ^ b[17]);
assign m11_18 = (a[11] ^ a[18]) & (b[11] ^ b[18]);
assign m11_19 = (a[11] ^ a[19]) & (b[11] ^ b[19]);
assign m11_20 = (a[11] ^ a[20]) & (b[11] ^ b[20]);
assign m11_21 = (a[11] ^ a[21]) & (b[11] ^ b[21]);
assign m11_22 = (a[11] ^ a[22]) & (b[11] ^ b[22]);
assign m11_23 = (a[11] ^ a[23]) & (b[11] ^ b[23]);
assign m11_24 = (a[11] ^ a[24]) & (b[11] ^ b[24]);
assign m11_25 = (a[11] ^ a[25]) & (b[11] ^ b[25]);
assign m12_13 = (a[12] ^ a[13]) & (b[12] ^ b[13]);
assign m12_14 = (a[12] ^ a[14]) & (b[12] ^ b[14]);
assign m12_15 = (a[12] ^ a[15]) & (b[12] ^ b[15]);
assign m12_16 = (a[12] ^ a[16]) & (b[12] ^ b[16]);
assign m12_17 = (a[12] ^ a[17]) & (b[12] ^ b[17]);
assign m12_18 = (a[12] ^ a[18]) & (b[12] ^ b[18]);
assign m12_19 = (a[12] ^ a[19]) & (b[12] ^ b[19]);
assign m12_20 = (a[12] ^ a[20]) & (b[12] ^ b[20]);
assign m12_21 = (a[12] ^ a[21]) & (b[12] ^ b[21]);
assign m12_22 = (a[12] ^ a[22]) & (b[12] ^ b[22]);
assign m12_23 = (a[12] ^ a[23]) & (b[12] ^ b[23]);
assign m12_24 = (a[12] ^ a[24]) & (b[12] ^ b[24]);
assign m12_25 = (a[12] ^ a[25]) & (b[12] ^ b[25]);
assign m13_14 = (a[13] ^ a[14]) & (b[13] ^ b[14]);
assign m13_15 = (a[13] ^ a[15]) & (b[13] ^ b[15]);
assign m13_16 = (a[13] ^ a[16]) & (b[13] ^ b[16]);
assign m13_17 = (a[13] ^ a[17]) & (b[13] ^ b[17]);
assign m13_18 = (a[13] ^ a[18]) & (b[13] ^ b[18]);
assign m13_19 = (a[13] ^ a[19]) & (b[13] ^ b[19]);
assign m13_20 = (a[13] ^ a[20]) & (b[13] ^ b[20]);
assign m13_21 = (a[13] ^ a[21]) & (b[13] ^ b[21]);
assign m13_22 = (a[13] ^ a[22]) & (b[13] ^ b[22]);
assign m13_23 = (a[13] ^ a[23]) & (b[13] ^ b[23]);
assign m13_24 = (a[13] ^ a[24]) & (b[13] ^ b[24]);
assign m13_25 = (a[13] ^ a[25]) & (b[13] ^ b[25]);
assign m14_15 = (a[14] ^ a[15]) & (b[14] ^ b[15]);
assign m14_16 = (a[14] ^ a[16]) & (b[14] ^ b[16]);
assign m14_17 = (a[14] ^ a[17]) & (b[14] ^ b[17]);
assign m14_18 = (a[14] ^ a[18]) & (b[14] ^ b[18]);
assign m14_19 = (a[14] ^ a[19]) & (b[14] ^ b[19]);
assign m14_20 = (a[14] ^ a[20]) & (b[14] ^ b[20]);
assign m14_21 = (a[14] ^ a[21]) & (b[14] ^ b[21]);
assign m14_22 = (a[14] ^ a[22]) & (b[14] ^ b[22]);
assign m14_23 = (a[14] ^ a[23]) & (b[14] ^ b[23]);
assign m14_24 = (a[14] ^ a[24]) & (b[14] ^ b[24]);
assign m14_25 = (a[14] ^ a[25]) & (b[14] ^ b[25]);
assign m15_16 = (a[15] ^ a[16]) & (b[15] ^ b[16]);
assign m15_17 = (a[15] ^ a[17]) & (b[15] ^ b[17]);
assign m15_18 = (a[15] ^ a[18]) & (b[15] ^ b[18]);
assign m15_19 = (a[15] ^ a[19]) & (b[15] ^ b[19]);
assign m15_20 = (a[15] ^ a[20]) & (b[15] ^ b[20]);
assign m15_21 = (a[15] ^ a[21]) & (b[15] ^ b[21]);
assign m15_22 = (a[15] ^ a[22]) & (b[15] ^ b[22]);
assign m15_23 = (a[15] ^ a[23]) & (b[15] ^ b[23]);
assign m15_24 = (a[15] ^ a[24]) & (b[15] ^ b[24]);
assign m15_25 = (a[15] ^ a[25]) & (b[15] ^ b[25]);
assign m16_17 = (a[16] ^ a[17]) & (b[16] ^ b[17]);
assign m16_18 = (a[16] ^ a[18]) & (b[16] ^ b[18]);
assign m16_19 = (a[16] ^ a[19]) & (b[16] ^ b[19]);
assign m16_20 = (a[16] ^ a[20]) & (b[16] ^ b[20]);
assign m16_21 = (a[16] ^ a[21]) & (b[16] ^ b[21]);
assign m16_22 = (a[16] ^ a[22]) & (b[16] ^ b[22]);
assign m16_23 = (a[16] ^ a[23]) & (b[16] ^ b[23]);
assign m16_24 = (a[16] ^ a[24]) & (b[16] ^ b[24]);
assign m16_25 = (a[16] ^ a[25]) & (b[16] ^ b[25]);
assign m17_18 = (a[17] ^ a[18]) & (b[17] ^ b[18]);
assign m17_19 = (a[17] ^ a[19]) & (b[17] ^ b[19]);
assign m17_20 = (a[17] ^ a[20]) & (b[17] ^ b[20]);
assign m17_21 = (a[17] ^ a[21]) & (b[17] ^ b[21]);
assign m17_22 = (a[17] ^ a[22]) & (b[17] ^ b[22]);
assign m17_23 = (a[17] ^ a[23]) & (b[17] ^ b[23]);
assign m17_24 = (a[17] ^ a[24]) & (b[17] ^ b[24]);
assign m17_25 = (a[17] ^ a[25]) & (b[17] ^ b[25]);
assign m18_19 = (a[18] ^ a[19]) & (b[18] ^ b[19]);
assign m18_20 = (a[18] ^ a[20]) & (b[18] ^ b[20]);
assign m18_21 = (a[18] ^ a[21]) & (b[18] ^ b[21]);
assign m18_22 = (a[18] ^ a[22]) & (b[18] ^ b[22]);
assign m18_23 = (a[18] ^ a[23]) & (b[18] ^ b[23]);
assign m18_24 = (a[18] ^ a[24]) & (b[18] ^ b[24]);
assign m18_25 = (a[18] ^ a[25]) & (b[18] ^ b[25]);
assign m19_20 = (a[19] ^ a[20]) & (b[19] ^ b[20]);
assign m19_21 = (a[19] ^ a[21]) & (b[19] ^ b[21]);
assign m19_22 = (a[19] ^ a[22]) & (b[19] ^ b[22]);
assign m19_23 = (a[19] ^ a[23]) & (b[19] ^ b[23]);
assign m19_24 = (a[19] ^ a[24]) & (b[19] ^ b[24]);
assign m19_25 = (a[19] ^ a[25]) & (b[19] ^ b[25]);
assign m20_21 = (a[20] ^ a[21]) & (b[20] ^ b[21]);
assign m20_22 = (a[20] ^ a[22]) & (b[20] ^ b[22]);
assign m20_23 = (a[20] ^ a[23]) & (b[20] ^ b[23]);
assign m20_24 = (a[20] ^ a[24]) & (b[20] ^ b[24]);
assign m20_25 = (a[20] ^ a[25]) & (b[20] ^ b[25]);
assign m21_22 = (a[21] ^ a[22]) & (b[21] ^ b[22]);
assign m21_23 = (a[21] ^ a[23]) & (b[21] ^ b[23]);
assign m21_24 = (a[21] ^ a[24]) & (b[21] ^ b[24]);
assign m21_25 = (a[21] ^ a[25]) & (b[21] ^ b[25]);
assign m22_23 = (a[22] ^ a[23]) & (b[22] ^ b[23]);
assign m22_24 = (a[22] ^ a[24]) & (b[22] ^ b[24]);
assign m22_25 = (a[22] ^ a[25]) & (b[22] ^ b[25]);
assign m23_24 = (a[23] ^ a[24]) & (b[23] ^ b[24]);
assign m23_25 = (a[23] ^ a[25]) & (b[23] ^ b[25]);
assign m24_25 = (a[24] ^ a[25]) & (b[24] ^ b[25]);
assign d[0] = m0;
assign d[1] = m0_1 ^ m0 ^ m1;
assign d[2] = m0_2 ^ m0 ^ m1 ^ m2;
assign d[3] = m0_3 ^ m1_2 ^ m0 ^ m1 ^ m2 ^ m3;
assign d[4] = m0_4 ^ m1_3 ^ m0 ^ m1 ^ m2 ^ m3 ^ m4;
assign d[5] = m0_5 ^ m1_4 ^ m2_3 ^ m0 ^ m1 ^ m2 ^ m3 ^ m4 ^ m5;
assign d[6] = m0_6 ^ m1_5 ^ m2_4 ^ m0 ^ m1 ^ m2 ^ m3 ^ m4 ^ m5 ^ m6;
assign d[7] = m0_7 ^ m1_6 ^ m2_5 ^ m3_4 ^ m0 ^ m1 ^ m2 ^ m3 ^ m4 ^ m5 ^ m6 ^ m7;
assign d[8] = m0_8 ^ m1_7 ^ m2_6 ^ m3_5 ^ m0 ^ m1 ^ m2 ^ m3 ^ m4 ^ m5 ^ m6 ^ m7 ^ m8;
assign d[9] = m0_9 ^ m1_8 ^ m2_7 ^ m3_6 ^ m4_5 ^ m0 ^ m1 ^ m2 ^ m3 ^ m4 ^ m5 ^ m6 ^ m7 ^ m8 ^ m9;
assign d[10] = m0_10 ^ m1_9 ^ m2_8 ^ m3_7 ^ m4_6 ^ m0 ^ m1 ^ m2 ^ m3 ^ m4 ^ m5 ^ m6 ^ m7 ^ m8 ^ m9 ^ m10;
assign d[11] = m0_11 ^ m1_10 ^ m2_9 ^ m3_8 ^ m4_7 ^ m5_6 ^ m0 ^ m1 ^ m2 ^ m3 ^ m4 ^ m5 ^ m6 ^ m7 ^ m8 ^ m9 ^ m10 ^ m11;
assign d[12] = m0_12 ^ m1_11 ^ m2_10 ^ m3_9 ^ m4_8 ^ m5_7 ^ m0 ^ m1 ^ m2 ^ m3 ^ m4 ^ m5 ^ m6 ^ m7 ^ m8 ^ m9 ^ m10 ^ m11 ^ m12;
assign d[13] = m0_13 ^ m1_12 ^ m2_11 ^ m3_10 ^ m4_9 ^ m5_8 ^ m6_7 ^ m0 ^ m1 ^ m2 ^ m3 ^ m4 ^ m5 ^ m6 ^ m7 ^ m8 ^ m9 ^ m10 ^ m11 ^ m12 ^ m13;
assign d[14] = m0_14 ^ m1_13 ^ m2_12 ^ m3_11 ^ m4_10 ^ m5_9 ^ m6_8 ^ m0 ^ m1 ^ m2 ^ m3 ^ m4 ^ m5 ^ m6 ^ m7 ^ m8 ^ m9 ^ m10 ^ m11 ^ m12 ^ m13 ^ m14;
assign d[15] = m0_15 ^ m1_14 ^ m2_13 ^ m3_12 ^ m4_11 ^ m5_10 ^ m6_9 ^ m7_8 ^ m0 ^ m1 ^ m2 ^ m3 ^ m4 ^ m5 ^ m6 ^ m7 ^ m8 ^ m9 ^ m10 ^ m11 ^ m12 ^ m13 ^ m14 ^ m15;
assign d[16] = m0_16 ^ m1_15 ^ m2_14 ^ m3_13 ^ m4_12 ^ m5_11 ^ m6_10 ^ m7_9 ^ m0 ^ m1 ^ m2 ^ m3 ^ m4 ^ m5 ^ m6 ^ m7 ^ m8 ^ m9 ^ m10 ^ m11 ^ m12 ^ m13 ^ m14 ^ m15 ^ m16;
assign d[17] = m0_17 ^ m1_16 ^ m2_15 ^ m3_14 ^ m4_13 ^ m5_12 ^ m6_11 ^ m7_10 ^ m8_9 ^ m0 ^ m1 ^ m2 ^ m3 ^ m4 ^ m5 ^ m6 ^ m7 ^ m8 ^ m9 ^ m10 ^ m11 ^ m12 ^ m13 ^ m14 ^ m15 ^ m16 ^ m17;
assign d[18] = m0_18 ^ m1_17 ^ m2_16 ^ m3_15 ^ m4_14 ^ m5_13 ^ m6_12 ^ m7_11 ^ m8_10 ^ m0 ^ m1 ^ m2 ^ m3 ^ m4 ^ m5 ^ m6 ^ m7 ^ m8 ^ m9 ^ m10 ^ m11 ^ m12 ^ m13 ^ m14 ^ m15 ^ m16 ^ m17 ^ m18;
assign d[19] = m0_19 ^ m1_18 ^ m2_17 ^ m3_16 ^ m4_15 ^ m5_14 ^ m6_13 ^ m7_12 ^ m8_11 ^ m9_10 ^ m0 ^ m1 ^ m2 ^ m3 ^ m4 ^ m5 ^ m6 ^ m7 ^ m8 ^ m9 ^ m10 ^ m11 ^ m12 ^ m13 ^ m14 ^ m15 ^ m16 ^ m17 ^ m18 ^ m19;
assign d[20] = m0_20 ^ m1_19 ^ m2_18 ^ m3_17 ^ m4_16 ^ m5_15 ^ m6_14 ^ m7_13 ^ m8_12 ^ m9_11 ^ m0 ^ m1 ^ m2 ^ m3 ^ m4 ^ m5 ^ m6 ^ m7 ^ m8 ^ m9 ^ m10 ^ m11 ^ m12 ^ m13 ^ m14 ^ m15 ^ m16 ^ m17 ^ m18 ^ m19 ^ m20;
assign d[21] = m0_21 ^ m1_20 ^ m2_19 ^ m3_18 ^ m4_17 ^ m5_16 ^ m6_15 ^ m7_14 ^ m8_13 ^ m9_12 ^ m10_11 ^ m0 ^ m1 ^ m2 ^ m3 ^ m4 ^ m5 ^ m6 ^ m7 ^ m8 ^ m9 ^ m10 ^ m11 ^ m12 ^ m13 ^ m14 ^ m15 ^ m16 ^ m17 ^ m18 ^ m19 ^ m20 ^ m21;
assign d[22] = m0_22 ^ m1_21 ^ m2_20 ^ m3_19 ^ m4_18 ^ m5_17 ^ m6_16 ^ m7_15 ^ m8_14 ^ m9_13 ^ m10_12 ^ m0 ^ m1 ^ m2 ^ m3 ^ m4 ^ m5 ^ m6 ^ m7 ^ m8 ^ m9 ^ m10 ^ m11 ^ m12 ^ m13 ^ m14 ^ m15 ^ m16 ^ m17 ^ m18 ^ m19 ^ m20 ^ m21 ^ m22;
assign d[23] = m0_23 ^ m1_22 ^ m2_21 ^ m3_20 ^ m4_19 ^ m5_18 ^ m6_17 ^ m7_16 ^ m8_15 ^ m9_14 ^ m10_13 ^ m11_12 ^ m0 ^ m1 ^ m2 ^ m3 ^ m4 ^ m5 ^ m6 ^ m7 ^ m8 ^ m9 ^ m10 ^ m11 ^ m12 ^ m13 ^ m14 ^ m15 ^ m16 ^ m17 ^ m18 ^ m19 ^ m20 ^ m21 ^ m22 ^ m23;
assign d[24] = m0_24 ^ m1_23 ^ m2_22 ^ m3_21 ^ m4_20 ^ m5_19 ^ m6_18 ^ m7_17 ^ m8_16 ^ m9_15 ^ m10_14 ^ m11_13 ^ m0 ^ m1 ^ m2 ^ m3 ^ m4 ^ m5 ^ m6 ^ m7 ^ m8 ^ m9 ^ m10 ^ m11 ^ m12 ^ m13 ^ m14 ^ m15 ^ m16 ^ m17 ^ m18 ^ m19 ^ m20 ^ m21 ^ m22 ^ m23 ^ m24;
assign d[25] = m0_25 ^ m1_24 ^ m2_23 ^ m3_22 ^ m4_21 ^ m5_20 ^ m6_19 ^ m7_18 ^ m8_17 ^ m9_16 ^ m10_15 ^ m11_14 ^ m12_13 ^ m0 ^ m1 ^ m2 ^ m3 ^ m4 ^ m5 ^ m6 ^ m7 ^ m8 ^ m9 ^ m10 ^ m11 ^ m12 ^ m13 ^ m14 ^ m15 ^ m16 ^ m17 ^ m18 ^ m19 ^ m20 ^ m21 ^ m22 ^ m23 ^ m24 ^ m25;
assign d[26] = m1_25 ^ m2_24 ^ m3_23 ^ m4_22 ^ m5_21 ^ m6_20 ^ m7_19 ^ m8_18 ^ m9_17 ^ m10_16 ^ m11_15 ^ m12_14 ^ m1 ^ m2 ^ m3 ^ m4 ^ m5 ^ m6 ^ m7 ^ m8 ^ m9 ^ m10 ^ m11 ^ m12 ^ m13 ^ m14 ^ m15 ^ m16 ^ m17 ^ m18 ^ m19 ^ m20 ^ m21 ^ m22 ^ m23 ^ m24 ^ m25;
assign d[27] = m2_25 ^ m3_24 ^ m4_23 ^ m5_22 ^ m6_21 ^ m7_20 ^ m8_19 ^ m9_18 ^ m10_17 ^ m11_16 ^ m12_15 ^ m13_14 ^ m2 ^ m3 ^ m4 ^ m5 ^ m6 ^ m7 ^ m8 ^ m9 ^ m10 ^ m11 ^ m12 ^ m13 ^ m14 ^ m15 ^ m16 ^ m17 ^ m18 ^ m19 ^ m20 ^ m21 ^ m22 ^ m23 ^ m24 ^ m25;
assign d[28] = m3_25 ^ m4_24 ^ m5_23 ^ m6_22 ^ m7_21 ^ m8_20 ^ m9_19 ^ m10_18 ^ m11_17 ^ m12_16 ^ m13_15 ^ m3 ^ m4 ^ m5 ^ m6 ^ m7 ^ m8 ^ m9 ^ m10 ^ m11 ^ m12 ^ m13 ^ m14 ^ m15 ^ m16 ^ m17 ^ m18 ^ m19 ^ m20 ^ m21 ^ m22 ^ m23 ^ m24 ^ m25;
assign d[29] = m4_25 ^ m5_24 ^ m6_23 ^ m7_22 ^ m8_21 ^ m9_20 ^ m10_19 ^ m11_18 ^ m12_17 ^ m13_16 ^ m14_15 ^ m4 ^ m5 ^ m6 ^ m7 ^ m8 ^ m9 ^ m10 ^ m11 ^ m12 ^ m13 ^ m14 ^ m15 ^ m16 ^ m17 ^ m18 ^ m19 ^ m20 ^ m21 ^ m22 ^ m23 ^ m24 ^ m25;
assign d[30] = m5_25 ^ m6_24 ^ m7_23 ^ m8_22 ^ m9_21 ^ m10_20 ^ m11_19 ^ m12_18 ^ m13_17 ^ m14_16 ^ m5 ^ m6 ^ m7 ^ m8 ^ m9 ^ m10 ^ m11 ^ m12 ^ m13 ^ m14 ^ m15 ^ m16 ^ m17 ^ m18 ^ m19 ^ m20 ^ m21 ^ m22 ^ m23 ^ m24 ^ m25;
assign d[31] = m6_25 ^ m7_24 ^ m8_23 ^ m9_22 ^ m10_21 ^ m11_20 ^ m12_19 ^ m13_18 ^ m14_17 ^ m15_16 ^ m6 ^ m7 ^ m8 ^ m9 ^ m10 ^ m11 ^ m12 ^ m13 ^ m14 ^ m15 ^ m16 ^ m17 ^ m18 ^ m19 ^ m20 ^ m21 ^ m22 ^ m23 ^ m24 ^ m25;
assign d[32] = m7_25 ^ m8_24 ^ m9_23 ^ m10_22 ^ m11_21 ^ m12_20 ^ m13_19 ^ m14_18 ^ m15_17 ^ m7 ^ m8 ^ m9 ^ m10 ^ m11 ^ m12 ^ m13 ^ m14 ^ m15 ^ m16 ^ m17 ^ m18 ^ m19 ^ m20 ^ m21 ^ m22 ^ m23 ^ m24 ^ m25;
assign d[33] = m8_25 ^ m9_24 ^ m10_23 ^ m11_22 ^ m12_21 ^ m13_20 ^ m14_19 ^ m15_18 ^ m16_17 ^ m8 ^ m9 ^ m10 ^ m11 ^ m12 ^ m13 ^ m14 ^ m15 ^ m16 ^ m17 ^ m18 ^ m19 ^ m20 ^ m21 ^ m22 ^ m23 ^ m24 ^ m25;
assign d[34] = m9_25 ^ m10_24 ^ m11_23 ^ m12_22 ^ m13_21 ^ m14_20 ^ m15_19 ^ m16_18 ^ m9 ^ m10 ^ m11 ^ m12 ^ m13 ^ m14 ^ m15 ^ m16 ^ m17 ^ m18 ^ m19 ^ m20 ^ m21 ^ m22 ^ m23 ^ m24 ^ m25;
assign d[35] = m10_25 ^ m11_24 ^ m12_23 ^ m13_22 ^ m14_21 ^ m15_20 ^ m16_19 ^ m17_18 ^ m10 ^ m11 ^ m12 ^ m13 ^ m14 ^ m15 ^ m16 ^ m17 ^ m18 ^ m19 ^ m20 ^ m21 ^ m22 ^ m23 ^ m24 ^ m25;
assign d[36] = m11_25 ^ m12_24 ^ m13_23 ^ m14_22 ^ m15_21 ^ m16_20 ^ m17_19 ^ m11 ^ m12 ^ m13 ^ m14 ^ m15 ^ m16 ^ m17 ^ m18 ^ m19 ^ m20 ^ m21 ^ m22 ^ m23 ^ m24 ^ m25;
assign d[37] = m12_25 ^ m13_24 ^ m14_23 ^ m15_22 ^ m16_21 ^ m17_20 ^ m18_19 ^ m12 ^ m13 ^ m14 ^ m15 ^ m16 ^ m17 ^ m18 ^ m19 ^ m20 ^ m21 ^ m22 ^ m23 ^ m24 ^ m25;
assign d[38] = m13_25 ^ m14_24 ^ m15_23 ^ m16_22 ^ m17_21 ^ m18_20 ^ m13 ^ m14 ^ m15 ^ m16 ^ m17 ^ m18 ^ m19 ^ m20 ^ m21 ^ m22 ^ m23 ^ m24 ^ m25;
assign d[39] = m14_25 ^ m15_24 ^ m16_23 ^ m17_22 ^ m18_21 ^ m19_20 ^ m14 ^ m15 ^ m16 ^ m17 ^ m18 ^ m19 ^ m20 ^ m21 ^ m22 ^ m23 ^ m24 ^ m25;
assign d[40] = m15_25 ^ m16_24 ^ m17_23 ^ m18_22 ^ m19_21 ^ m15 ^ m16 ^ m17 ^ m18 ^ m19 ^ m20 ^ m21 ^ m22 ^ m23 ^ m24 ^ m25;
assign d[41] = m16_25 ^ m17_24 ^ m18_23 ^ m19_22 ^ m20_21 ^ m16 ^ m17 ^ m18 ^ m19 ^ m20 ^ m21 ^ m22 ^ m23 ^ m24 ^ m25;
assign d[42] = m17_25 ^ m18_24 ^ m19_23 ^ m20_22 ^ m17 ^ m18 ^ m19 ^ m20 ^ m21 ^ m22 ^ m23 ^ m24 ^ m25;
assign d[43] = m18_25 ^ m19_24 ^ m20_23 ^ m21_22 ^ m18 ^ m19 ^ m20 ^ m21 ^ m22 ^ m23 ^ m24 ^ m25;
assign d[44] = m19_25 ^ m20_24 ^ m21_23 ^ m19 ^ m20 ^ m21 ^ m22 ^ m23 ^ m24 ^ m25;
assign d[45] = m20_25 ^ m21_24 ^ m22_23 ^ m20 ^ m21 ^ m22 ^ m23 ^ m24 ^ m25;
assign d[46] = m21_25 ^ m22_24 ^ m21 ^ m22 ^ m23 ^ m24 ^ m25;
assign d[47] = m22_25 ^ m23_24 ^ m22 ^ m23 ^ m24 ^ m25;
assign d[48] = m23_25 ^ m23 ^ m24 ^ m25;
assign d[49] = m24_25 ^ m24 ^ m25;
assign d[50] = m25;
endmodule
`endif
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DIODE_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__DIODE_BEHAVIORAL_PP_V
/**
* diode: Antenna tie-down diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__diode (
DIODE,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
input DIODE;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DIODE_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND2_SYMBOL_V
`define SKY130_FD_SC_LP__AND2_SYMBOL_V
/**
* and2: 2-input AND.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__and2 (
//# {{data|Data Signals}}
input A,
input B,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND2_SYMBOL_V
|
/*
* These source files contain a hardware description of a network
* automatically generated by CONNECT (CONfigurable NEtwork Creation Tool).
*
* This product includes a hardware design developed by Carnegie Mellon
* University.
*
* Copyright (c) 2012 by Michael K. Papamichael, Carnegie Mellon University
*
* For more information, see the CONNECT project website at:
* http://www.ece.cmu.edu/~mpapamic/connect
*
* This design is provided for internal, non-commercial research use only,
* cannot be used for, or in support of, goods or services, and is not for
* redistribution, with or without modifications.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*
*/
//
// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17)
//
// On Mon Nov 14 15:54:42 EST 2016
//
// Method conflict info:
// Method: input_arbs_0_select
// Conflict-free: input_arbs_0_select,
// input_arbs_0_next,
// input_arbs_1_select,
// input_arbs_1_next,
// input_arbs_2_select,
// input_arbs_2_next,
// input_arbs_3_select,
// input_arbs_3_next,
// input_arbs_4_select,
// input_arbs_4_next
//
// Method: input_arbs_0_next
// Conflict-free: input_arbs_0_select,
// input_arbs_0_next,
// input_arbs_1_select,
// input_arbs_1_next,
// input_arbs_2_select,
// input_arbs_2_next,
// input_arbs_3_select,
// input_arbs_3_next,
// input_arbs_4_select,
// input_arbs_4_next
//
// Method: input_arbs_1_select
// Conflict-free: input_arbs_0_select,
// input_arbs_0_next,
// input_arbs_1_select,
// input_arbs_1_next,
// input_arbs_2_select,
// input_arbs_2_next,
// input_arbs_3_select,
// input_arbs_3_next,
// input_arbs_4_select,
// input_arbs_4_next
//
// Method: input_arbs_1_next
// Conflict-free: input_arbs_0_select,
// input_arbs_0_next,
// input_arbs_1_select,
// input_arbs_1_next,
// input_arbs_2_select,
// input_arbs_2_next,
// input_arbs_3_select,
// input_arbs_3_next,
// input_arbs_4_select,
// input_arbs_4_next
//
// Method: input_arbs_2_select
// Conflict-free: input_arbs_0_select,
// input_arbs_0_next,
// input_arbs_1_select,
// input_arbs_1_next,
// input_arbs_2_select,
// input_arbs_2_next,
// input_arbs_3_select,
// input_arbs_3_next,
// input_arbs_4_select,
// input_arbs_4_next
//
// Method: input_arbs_2_next
// Conflict-free: input_arbs_0_select,
// input_arbs_0_next,
// input_arbs_1_select,
// input_arbs_1_next,
// input_arbs_2_select,
// input_arbs_2_next,
// input_arbs_3_select,
// input_arbs_3_next,
// input_arbs_4_select,
// input_arbs_4_next
//
// Method: input_arbs_3_select
// Conflict-free: input_arbs_0_select,
// input_arbs_0_next,
// input_arbs_1_select,
// input_arbs_1_next,
// input_arbs_2_select,
// input_arbs_2_next,
// input_arbs_3_select,
// input_arbs_3_next,
// input_arbs_4_select,
// input_arbs_4_next
//
// Method: input_arbs_3_next
// Conflict-free: input_arbs_0_select,
// input_arbs_0_next,
// input_arbs_1_select,
// input_arbs_1_next,
// input_arbs_2_select,
// input_arbs_2_next,
// input_arbs_3_select,
// input_arbs_3_next,
// input_arbs_4_select,
// input_arbs_4_next
//
// Method: input_arbs_4_select
// Conflict-free: input_arbs_0_select,
// input_arbs_0_next,
// input_arbs_1_select,
// input_arbs_1_next,
// input_arbs_2_select,
// input_arbs_2_next,
// input_arbs_3_select,
// input_arbs_3_next,
// input_arbs_4_select,
// input_arbs_4_next
//
// Method: input_arbs_4_next
// Conflict-free: input_arbs_0_select,
// input_arbs_0_next,
// input_arbs_1_select,
// input_arbs_1_next,
// input_arbs_2_select,
// input_arbs_2_next,
// input_arbs_3_select,
// input_arbs_3_next,
// input_arbs_4_select,
// input_arbs_4_next
//
//
// Ports:
// Name I/O size props
// input_arbs_0_select O 5
// input_arbs_1_select O 5
// input_arbs_2_select O 5
// input_arbs_3_select O 5
// input_arbs_4_select O 5
// CLK I 1 unused
// RST_N I 1 unused
// input_arbs_0_select_requests I 5
// input_arbs_1_select_requests I 5
// input_arbs_2_select_requests I 5
// input_arbs_3_select_requests I 5
// input_arbs_4_select_requests I 5
// EN_input_arbs_0_next I 1 unused
// EN_input_arbs_1_next I 1 unused
// EN_input_arbs_2_next I 1 unused
// EN_input_arbs_3_next I 1 unused
// EN_input_arbs_4_next I 1 unused
//
// Combinational paths from inputs to outputs:
// input_arbs_0_select_requests -> input_arbs_0_select
// input_arbs_1_select_requests -> input_arbs_1_select
// input_arbs_2_select_requests -> input_arbs_2_select
// input_arbs_3_select_requests -> input_arbs_3_select
// input_arbs_4_select_requests -> input_arbs_4_select
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module mkRouterInputArbitersStatic(CLK,
RST_N,
input_arbs_0_select_requests,
input_arbs_0_select,
EN_input_arbs_0_next,
input_arbs_1_select_requests,
input_arbs_1_select,
EN_input_arbs_1_next,
input_arbs_2_select_requests,
input_arbs_2_select,
EN_input_arbs_2_next,
input_arbs_3_select_requests,
input_arbs_3_select,
EN_input_arbs_3_next,
input_arbs_4_select_requests,
input_arbs_4_select,
EN_input_arbs_4_next);
input CLK;
input RST_N;
// value method input_arbs_0_select
input [4 : 0] input_arbs_0_select_requests;
output [4 : 0] input_arbs_0_select;
// action method input_arbs_0_next
input EN_input_arbs_0_next;
// value method input_arbs_1_select
input [4 : 0] input_arbs_1_select_requests;
output [4 : 0] input_arbs_1_select;
// action method input_arbs_1_next
input EN_input_arbs_1_next;
// value method input_arbs_2_select
input [4 : 0] input_arbs_2_select_requests;
output [4 : 0] input_arbs_2_select;
// action method input_arbs_2_next
input EN_input_arbs_2_next;
// value method input_arbs_3_select
input [4 : 0] input_arbs_3_select_requests;
output [4 : 0] input_arbs_3_select;
// action method input_arbs_3_next
input EN_input_arbs_3_next;
// value method input_arbs_4_select
input [4 : 0] input_arbs_4_select_requests;
output [4 : 0] input_arbs_4_select;
// action method input_arbs_4_next
input EN_input_arbs_4_next;
// signals for module outputs
wire [4 : 0] input_arbs_0_select,
input_arbs_1_select,
input_arbs_2_select,
input_arbs_3_select,
input_arbs_4_select;
// value method input_arbs_0_select
assign input_arbs_0_select =
{ input_arbs_0_select_requests[4],
!input_arbs_0_select_requests[4] &&
input_arbs_0_select_requests[3],
!input_arbs_0_select_requests[4] &&
!input_arbs_0_select_requests[3] &&
input_arbs_0_select_requests[2],
!input_arbs_0_select_requests[4] &&
!input_arbs_0_select_requests[3] &&
!input_arbs_0_select_requests[2] &&
input_arbs_0_select_requests[1],
!input_arbs_0_select_requests[4] &&
!input_arbs_0_select_requests[3] &&
!input_arbs_0_select_requests[2] &&
!input_arbs_0_select_requests[1] &&
input_arbs_0_select_requests[0] } ;
// value method input_arbs_1_select
assign input_arbs_1_select =
{ !input_arbs_1_select_requests[0] &&
input_arbs_1_select_requests[4],
!input_arbs_1_select_requests[0] &&
!input_arbs_1_select_requests[4] &&
input_arbs_1_select_requests[3],
!input_arbs_1_select_requests[0] &&
!input_arbs_1_select_requests[4] &&
!input_arbs_1_select_requests[3] &&
input_arbs_1_select_requests[2],
!input_arbs_1_select_requests[0] &&
!input_arbs_1_select_requests[4] &&
!input_arbs_1_select_requests[3] &&
!input_arbs_1_select_requests[2] &&
input_arbs_1_select_requests[1],
input_arbs_1_select_requests[0] } ;
// value method input_arbs_2_select
assign input_arbs_2_select =
{ !input_arbs_2_select_requests[1] &&
!input_arbs_2_select_requests[0] &&
input_arbs_2_select_requests[4],
!input_arbs_2_select_requests[1] &&
!input_arbs_2_select_requests[0] &&
!input_arbs_2_select_requests[4] &&
input_arbs_2_select_requests[3],
!input_arbs_2_select_requests[1] &&
!input_arbs_2_select_requests[0] &&
!input_arbs_2_select_requests[4] &&
!input_arbs_2_select_requests[3] &&
input_arbs_2_select_requests[2],
input_arbs_2_select_requests[1],
!input_arbs_2_select_requests[1] &&
input_arbs_2_select_requests[0] } ;
// value method input_arbs_3_select
assign input_arbs_3_select =
{ !input_arbs_3_select_requests[2] &&
!input_arbs_3_select_requests[1] &&
!input_arbs_3_select_requests[0] &&
input_arbs_3_select_requests[4],
!input_arbs_3_select_requests[2] &&
!input_arbs_3_select_requests[1] &&
!input_arbs_3_select_requests[0] &&
!input_arbs_3_select_requests[4] &&
input_arbs_3_select_requests[3],
input_arbs_3_select_requests[2],
!input_arbs_3_select_requests[2] &&
input_arbs_3_select_requests[1],
!input_arbs_3_select_requests[2] &&
!input_arbs_3_select_requests[1] &&
input_arbs_3_select_requests[0] } ;
// value method input_arbs_4_select
assign input_arbs_4_select =
{ !input_arbs_4_select_requests[3] &&
!input_arbs_4_select_requests[2] &&
!input_arbs_4_select_requests[1] &&
!input_arbs_4_select_requests[0] &&
input_arbs_4_select_requests[4],
input_arbs_4_select_requests[3],
!input_arbs_4_select_requests[3] &&
input_arbs_4_select_requests[2],
!input_arbs_4_select_requests[3] &&
!input_arbs_4_select_requests[2] &&
input_arbs_4_select_requests[1],
!input_arbs_4_select_requests[3] &&
!input_arbs_4_select_requests[2] &&
!input_arbs_4_select_requests[1] &&
input_arbs_4_select_requests[0] } ;
endmodule // mkRouterInputArbitersStatic
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 20 02:48:51 2016
/////////////////////////////////////////////////////////////
module ACA_II_N16_Q8_DW01_add_J42_0 ( A, B, CI, SUM, CO );
input [8:0] A;
input [8:0] B;
output [8:0] SUM;
input CI;
output CO;
wire n38, n39, n40, n41, n42, n43, n44, n45;
NOR2X1TS U13 ( .A(A[3]), .B(B[3]), .Y(n40) );
OAI211X1TS U14 ( .A0(A[1]), .A1(B[1]), .B0(B[0]), .C0(A[0]), .Y(n38) );
OAI2BB1X1TS U15 ( .A0N(B[1]), .A1N(A[1]), .B0(n38), .Y(n39) );
AOI222X1TS U16 ( .A0(B[2]), .A1(A[2]), .B0(B[2]), .B1(n39), .C0(A[2]), .C1(
n39), .Y(n41) );
OAI2BB2XLTS U17 ( .B0(n41), .B1(n40), .A0N(A[3]), .A1N(B[3]), .Y(n42) );
CMPR32X2TS U18 ( .A(A[4]), .B(B[4]), .C(n42), .CO(n43), .S(SUM[4]) );
CMPR32X2TS U19 ( .A(A[5]), .B(B[5]), .C(n43), .CO(n44), .S(SUM[5]) );
CMPR32X2TS U20 ( .A(A[6]), .B(B[6]), .C(n44), .CO(n45), .S(SUM[6]) );
CMPR32X2TS U21 ( .A(A[7]), .B(B[7]), .C(n45), .CO(SUM[8]), .S(SUM[7]) );
initial $sdf_annotate("ACA_II_N16_Q8_syn.sdf");
endmodule
module ACA_II_N16_Q8_DW01_add_J42_1 ( A, B, CI, SUM, CO );
input [7:0] A;
input [7:0] B;
output [7:0] SUM;
input CI;
output CO;
wire n35, n36, n37, n38, n39, n40, n41, n42, n43;
NOR2XLTS U13 ( .A(A[3]), .B(B[3]), .Y(n37) );
XOR2XLTS U14 ( .A(B[7]), .B(n41), .Y(SUM[7]) );
OAI2BB2X1TS U15 ( .B0(n38), .B1(n37), .A0N(A[3]), .A1N(B[3]), .Y(n42) );
AOI222X2TS U16 ( .A0(B[2]), .A1(A[2]), .B0(B[2]), .B1(n36), .C0(A[2]), .C1(
n36), .Y(n38) );
ADDFHX2TS U17 ( .A(A[5]), .B(B[5]), .CI(n39), .CO(n43), .S(SUM[5]) );
OAI2BB1X1TS U18 ( .A0N(B[1]), .A1N(A[1]), .B0(n35), .Y(n36) );
XOR2X1TS U19 ( .A(A[7]), .B(n40), .Y(n41) );
OAI211X1TS U20 ( .A0(A[1]), .A1(B[1]), .B0(B[0]), .C0(A[0]), .Y(n35) );
CMPR32X2TS U21 ( .A(A[4]), .B(B[4]), .C(n42), .CO(n39), .S(SUM[4]) );
CMPR32X2TS U22 ( .A(A[6]), .B(B[6]), .C(n43), .CO(n40), .S(SUM[6]) );
initial $sdf_annotate("ACA_II_N16_Q8_syn.sdf");
endmodule
module ACA_II_N16_Q8 ( in1, in2, res );
input [15:0] in1;
input [15:0] in2;
output [16:0] res;
wire n2, n3, n4, n5, n6, n7, n8, n9, SYNOPSYS_UNCONNECTED_1,
SYNOPSYS_UNCONNECTED_2, SYNOPSYS_UNCONNECTED_3,
SYNOPSYS_UNCONNECTED_4, SYNOPSYS_UNCONNECTED_5,
SYNOPSYS_UNCONNECTED_6, SYNOPSYS_UNCONNECTED_7,
SYNOPSYS_UNCONNECTED_8;
ACA_II_N16_Q8_DW01_add_J42_0 add_x_3 ( .A({1'b0, in1[15:8]}), .B({1'b0,
in2[15:8]}), .CI(1'b0), .SUM({res[16:12], SYNOPSYS_UNCONNECTED_1,
SYNOPSYS_UNCONNECTED_2, SYNOPSYS_UNCONNECTED_3, SYNOPSYS_UNCONNECTED_4}) );
ACA_II_N16_Q8_DW01_add_J42_1 add_x_2 ( .A(in1[11:4]), .B(in2[11:4]), .CI(
1'b0), .SUM({res[11:8], SYNOPSYS_UNCONNECTED_5, SYNOPSYS_UNCONNECTED_6,
SYNOPSYS_UNCONNECTED_7, SYNOPSYS_UNCONNECTED_8}) );
XOR2XLTS U2 ( .A(n3), .B(n2), .Y(res[7]) );
XOR2XLTS U3 ( .A(in1[7]), .B(in2[7]), .Y(n2) );
ADDHXLTS U4 ( .A(in2[0]), .B(in1[0]), .CO(n9), .S(res[0]) );
CMPR32X2TS U5 ( .A(in1[6]), .B(in2[6]), .C(n4), .CO(n3), .S(res[6]) );
CMPR32X2TS U6 ( .A(in1[5]), .B(in2[5]), .C(n5), .CO(n4), .S(res[5]) );
CMPR32X2TS U7 ( .A(in1[4]), .B(in2[4]), .C(n6), .CO(n5), .S(res[4]) );
CMPR32X2TS U8 ( .A(in1[3]), .B(in2[3]), .C(n7), .CO(n6), .S(res[3]) );
CMPR32X2TS U9 ( .A(in1[2]), .B(in2[2]), .C(n8), .CO(n7), .S(res[2]) );
CMPR32X2TS U10 ( .A(in1[1]), .B(in2[1]), .C(n9), .CO(n8), .S(res[1]) );
initial $sdf_annotate("ACA_II_N16_Q8_syn.sdf");
endmodule
|
/*
SLICEM at the following:
SLICE_XxY*
Where Y any value
x
Always even (ie 100, 102, 104, etc)
In our ROI
x = 6, 8, 10, 12, 14
SRL16E: LOC + BEL
SRLC32E: LOC + BEL
RAM64X1S: LOCs but doesn't BEL (or maybe I'm using the wrong BEL?)
*/
module top(input clk, stb, di, output do);
localparam integer DIN_N = 256;
localparam integer DOUT_N = 256;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule
/*
Using UG474 recommended primitives
*/
module roi(input clk, input [255:0] din, output [255:0] dout);
my_RAM32X1S #(.LOC("SLICE_X12Y100"))
c0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
my_RAM32X1D #(.LOC("SLICE_X12Y101"))
c1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
my_RAM32M #(.LOC("SLICE_X12Y102"))
c2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
my_RAM64X1S #(.LOC("SLICE_X12Y103"))
c3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
my_RAM64X1D #(.LOC("SLICE_X12Y104"))
c4(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8]));
my_RAM64M #(.LOC("SLICE_X12Y105"))
c5(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8]));
my_RAM128X1S #(.LOC("SLICE_X12Y106"))
c6(.clk(clk), .din(din[ 48 +: 8]), .dout(dout[ 48 +: 8]));
my_RAM128X1D #(.LOC("SLICE_X12Y107"))
c7(.clk(clk), .din(din[ 56 +: 8]), .dout(dout[ 56 +: 8]));
my_RAM256X1S #(.LOC("SLICE_X12Y108"))
c8(.clk(clk), .din(din[ 64 +: 8]), .dout(dout[ 64 +: 8]));
//Multi-packing
my_RAM32X1S_2 #(.LOC("SLICE_X12Y110"))
m0(.clk(clk), .din(din[ 72 +: 8]), .dout(dout[ 72 +: 8]));
my_RAM32X1S_3 #(.LOC("SLICE_X12Y111"))
m1(.clk(clk), .din(din[ 80 +: 8]), .dout(dout[ 80 +: 8]));
my_RAM32X1S_4 #(.LOC("SLICE_X12Y112"))
m2(.clk(clk), .din(din[ 88 +: 8]), .dout(dout[ 88 +: 8]));
my_RAM64X1D_2 #(.LOC("SLICE_X12Y113"))
m3(.clk(clk), .din(din[ 96 +: 8]), .dout(dout[ 96 +: 8]));
//next round
my_RAM64X1S_2 #(.LOC("SLICE_X12Y114"))
m4(.clk(clk), .din(din[ 104 +: 8]), .dout(dout[ 104 +: 8]));
my_RAM64X1S_3 #(.LOC("SLICE_X12Y115"))
m5(.clk(clk), .din(din[ 112 +: 8]), .dout(dout[ 112 +: 8]));
my_RAM64X1S_4 #(.LOC("SLICE_X12Y116"))
m6(.clk(clk), .din(din[ 120 +: 8]), .dout(dout[ 120 +: 8]));
//...and out of bits
my_RAM128X1S_2 #(.LOC("SLICE_X12Y117"))
m7(.clk(clk), .din(din[ 200 +: 8]), .dout(dout[ 200 +: 8]));
my_SRLC32E #(.LOC("SLICE_X14Y100"), .BEL("A6LUT"))
s0(.clk(clk), .din(din[ 128 +: 8]), .dout(dout[ 128 +: 8]));
my_SRLC32E #(.LOC("SLICE_X14Y101"), .BEL("B6LUT"))
s1(.clk(clk), .din(din[ 136 +: 8]), .dout(dout[ 136 +: 8]));
my_SRLC32E #(.LOC("SLICE_X14Y102"), .BEL("C6LUT"))
s2(.clk(clk), .din(din[ 144 +: 8]), .dout(dout[ 144 +: 8]));
my_SRLC32E #(.LOC("SLICE_X14Y103"), .BEL("D6LUT"))
s3(.clk(clk), .din(din[ 152 +: 8]), .dout(dout[ 152 +: 8]));
my_SRL16E #(.LOC("SLICE_X14Y104"), .BEL("A6LUT"))
s4(.clk(clk), .din(din[ 160 +: 8]), .dout(dout[ 160 +: 8]));
my_SRL16E #(.LOC("SLICE_X14Y105"), .BEL("B6LUT"))
s5(.clk(clk), .din(din[ 168 +: 8]), .dout(dout[ 168 +: 8]));
my_SRL16E #(.LOC("SLICE_X14Y106"), .BEL("C6LUT"))
s6(.clk(clk), .din(din[ 176 +: 8]), .dout(dout[ 176 +: 8]));
my_SRL16E #(.LOC("SLICE_X14Y107"), .BEL("D6LUT"))
s7(.clk(clk), .din(din[ 184 +: 8]), .dout(dout[ 184 +: 8]));
//my_SRL16E_8 #(.LOC("SLICE_X14Y108"))
// s8(.clk(clk), .din(din[ 192 +: 8]), .dout(dout[ 192 +: 8]));
endmodule
//It created a LUT instead of aggregating using WA7MUX
module my_RAM64X1S_2_mux (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
assign dout[0] = din[0] ? oa : ob;
(* LOC=LOC, KEEP, DONT_TOUCH *)
RAM64X1S #(
) ramb (
.O(ob),
.A0(din[0]),
.A1(din[0]),
.A2(din[0]),
.A3(din[0]),
.A4(din[0]),
.A5(din[0]),
.D(din[0]),
.WCLK(clk),
.WE(din[0]));
(* LOC=LOC, KEEP, DONT_TOUCH *)
RAM64X1S #(
) rama (
.O(oa),
.A0(din[0]),
.A1(din[0]),
.A2(din[0]),
.A3(din[0]),
.A4(din[0]),
.A5(din[0]),
.D(din[0]),
.WCLK(clk),
.WE(din[0]));
endmodule
module my_SRL16E_4 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
(* LOC=LOC, BEL="D6LUT" *)
SRL16E #(
) lutd (
.Q(dout[3]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.CE(din[4]),
.CLK(din[5]),
.D(din[6]));
(* LOC=LOC, BEL="C6LUT" *)
SRL16E #(
) lutc (
.Q(dout[2]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.CE(din[4]),
.CLK(din[5]),
.D(din[6]));
(* LOC=LOC, BEL="B6LUT" *)
SRL16E #(
) lutb (
.Q(dout[1]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.CE(din[4]),
.CLK(din[5]),
.D(din[6]));
(* LOC=LOC, BEL="A6LUT" *)
SRL16E #(
) luta (
.Q(dout[0]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.CE(din[4]),
.CLK(din[5]),
.D(din[6]));
endmodule
module my_SRL16E_8 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
(* LOC=LOC, BEL="D6LUT" *)
SRL16E #(
) lutd2 (
.Q(dout[7]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.CE(din[4]),
.CLK(din[5]),
.D(din[6]));
(* LOC=LOC, BEL="D6LUT" *)
SRL16E #(
) lutd1 (
.Q(dout[6]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.CE(din[4]),
.CLK(din[5]),
.D(din[6]));
endmodule
module my_SRLC32E_4 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
(* LOC=LOC, BEL="D6LUT", KEEP, DONT_TOUCH *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0)
) lutd (
.Q(dout[3]),
.Q31(),
.A(din[4:0]),
.CE(din[5]),
.CLK(din[6]),
.D(din[7]));
(* LOC=LOC, BEL="C6LUT", KEEP, DONT_TOUCH *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0)
) lutc (
.Q(dout[2]),
.Q31(),
.A(din[4:0]),
.CE(din[5]),
.CLK(din[6]),
.D(din[7]));
(* LOC=LOC, BEL="B6LUT", KEEP, DONT_TOUCH *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0)
) lutb (
.Q(dout[1]),
.Q31(),
.A(din[4:0]),
.CE(din[5]),
.CLK(din[6]),
.D(din[7]));
(* LOC=LOC, BEL="A6LUT", KEEP, DONT_TOUCH *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0)
) luta (
.Q(dout[0]),
.Q31(),
.A(din[4:0]),
.CE(din[5]),
.CLK(din[6]),
.D(din[7]));
endmodule
module my_RAM32X1S_2 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
(* LOC=LOC *)
RAM32X1S #(
) lutd (
.O(dout[3]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.D(din[5]),
.WCLK(din[6]),
.WE(din[7]));
(* LOC=LOC *)
RAM32X1S #(
) lutc (
.O(dout[2]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.D(din[5]),
.WCLK(din[6]),
.WE(din[7]));
endmodule
module my_RAM32X1S_3 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
(* LOC=LOC *)
RAM32X1S #(
) lutd (
.O(dout[3]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.D(din[5]),
.WCLK(din[6]),
.WE(din[7]));
(* LOC=LOC *)
RAM32X1S #(
) lutc (
.O(dout[2]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.D(din[5]),
.WCLK(din[6]),
.WE(din[7]));
(* LOC=LOC *)
RAM32X1S #(
) lutb (
.O(dout[1]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.D(din[5]),
.WCLK(din[6]),
.WE(din[7]));
endmodule
module my_RAM32X1S_4 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
(* LOC=LOC *)
RAM32X1S #(
) lutd (
.O(dout[3]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.D(din[5]),
.WCLK(din[6]),
.WE(din[7]));
(* LOC=LOC *)
RAM32X1S #(
) lutc (
.O(dout[2]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.D(din[5]),
.WCLK(din[6]),
.WE(din[7]));
(* LOC=LOC *)
RAM32X1S #(
) lutb (
.O(dout[1]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.D(din[5]),
.WCLK(din[6]),
.WE(din[7]));
(* LOC=LOC *)
RAM32X1S #(
) luta (
.O(dout[0]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.D(din[5]),
.WCLK(din[6]),
.WE(din[7]));
endmodule
module my_RAM64X1S_2 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
(* LOC=LOC *)
RAM64X1S #(
) lutd (
.O(dout[3]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.A5(din[5]),
.D(din[6]),
.WCLK(clk),
.WE(din[0]));
(* LOC=LOC *)
RAM64X1S #(
) lutc (
.O(dout[2]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.A5(din[5]),
.D(din[6]),
.WCLK(clk),
.WE(din[0]));
endmodule
module my_RAM64X1S_3 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
(* LOC=LOC *)
RAM64X1S #(
) lutd (
.O(dout[3]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.A5(din[5]),
.D(din[6]),
.WCLK(clk),
.WE(din[0]));
(* LOC=LOC *)
RAM64X1S #(
) lutc (
.O(dout[2]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.A5(din[5]),
.D(din[6]),
.WCLK(clk),
.WE(din[0]));
(* LOC=LOC *)
RAM64X1S #(
) lutb (
.O(dout[1]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.A5(din[5]),
.D(din[6]),
.WCLK(clk),
.WE(din[0]));
endmodule
module my_RAM64X1S_4 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
(* LOC=LOC *)
RAM64X1S #(
) lutd (
.O(dout[3]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.A5(din[5]),
.D(din[6]),
.WCLK(clk),
.WE(din[0]));
(* LOC=LOC *)
RAM64X1S #(
) lutc (
.O(dout[2]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.A5(din[5]),
.D(din[6]),
.WCLK(clk),
.WE(din[0]));
(* LOC=LOC *)
RAM64X1S #(
) lutb (
.O(dout[1]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.A5(din[5]),
.D(din[6]),
.WCLK(clk),
.WE(din[0]));
(* LOC=LOC *)
RAM64X1S #(
) luta (
.O(dout[0]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.A5(din[5]),
.D(din[6]),
.WCLK(clk),
.WE(din[0]));
endmodule
module my_RAM64X1D_2 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
(* LOC=LOC, KEEP, DONT_TOUCH *)
RAM64X1D #(
.INIT(64'h0),
.IS_WCLK_INVERTED(1'b0)
) ramb (
.DPO(dout[1]),
.D(din[0]),
.WCLK(clk),
.WE(din[2]),
.A0(din[3]),
.A1(din[4]),
.A2(din[5]),
.A3(din[6]),
.A4(din[7]),
.A5(din[0]),
.DPRA0(din[1]),
.DPRA1(din[2]),
.DPRA2(din[3]),
.DPRA3(din[4]),
.DPRA4(din[5]),
.DPRA5(din[6]));
(* LOC=LOC, KEEP, DONT_TOUCH *)
RAM64X1D #(
.INIT(64'h0),
.IS_WCLK_INVERTED(1'b0)
) rama (
.DPO(dout[0]),
.D(din[0]),
.WCLK(clk),
.WE(din[2]),
.A0(din[3]),
.A1(din[4]),
.A2(din[5]),
.A3(din[6]),
.A4(din[7]),
.A5(din[0]),
.DPRA0(din[1]),
.DPRA1(din[2]),
.DPRA2(din[3]),
.DPRA3(din[4]),
.DPRA4(din[5]),
.DPRA5(din[6]));
endmodule
//BEL: yes
module my_SRLC32E (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
parameter BEL="A6LUT";
wire mc31c;
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0)
) lut (
.Q(dout[0]),
.Q31(mc31c),
.A(din[4:0]),
.CE(din[5]),
.CLK(din[6]),
.D(din[7]));
endmodule
//BEL: yes
module my_SRL16E (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
parameter BEL="A6LUT";
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
SRL16E #(
) SRL16E (
.Q(dout[0]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.CE(din[4]),
.CLK(din[5]),
.D(din[6]));
endmodule
module my_RAM64M (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
parameter BEL="A6LUT";
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
RAM64M #(
) RAM64M (
.DOA(dout[0]),
.DOB(dout[1]),
.DOC(dout[2]),
.DOD(dout[3]),
.ADDRA(din[0]),
.ADDRB(din[1]),
.ADDRC(din[2]),
.ADDRD(din[3]),
.DIA(din[4]),
.DIB(din[5]),
.DIC(din[6]),
.DID(din[7]),
.WCLK(clk),
.WE(din[1]));
endmodule
//Can't get BEL to work. Maybe can't since multiple?
module my_RAM64X1S (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
parameter BEL="A6LUT";
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
RAM64X1S #(
) RAM64X1S (
.O(dout[0]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.A5(din[5]),
.D(din[6]),
.WCLK(clk),
.WE(din[0]));
endmodule
module my_RAM64X1S_1 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
parameter BEL="A6LUT";
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
RAM64X1S_1 #(
) RAM64X1S_1 (
.O(dout[0]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.A5(din[5]),
.D(din[6]),
.WCLK(clk),
.WE(din[0]));
endmodule
module my_RAM64X2S (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
(* LOC=LOC, KEEP, DONT_TOUCH *)
RAM64X2S #(
) RAM64X2S (
.O0(dout[0]),
.O1(dout[1]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.A5(din[5]),
.D0(din[6]),
.D1(din[7]),
.WCLK(clk),
.WE(din[1]));
endmodule
module my_RAM64X1D (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
(* LOC=LOC, KEEP, DONT_TOUCH *)
RAM64X1D #(
.INIT(64'h0),
.IS_WCLK_INVERTED(1'b0)
) RAM64X1D (
.DPO(dout[0]),
.D(din[0]),
.WCLK(clk),
.WE(din[2]),
.A0(din[3]),
.A1(din[4]),
.A2(din[5]),
.A3(din[6]),
.A4(din[7]),
.A5(din[0]),
.DPRA0(din[1]),
.DPRA1(din[2]),
.DPRA2(din[3]),
.DPRA3(din[4]),
.DPRA4(din[5]),
.DPRA5(din[6]));
endmodule
module my_RAM128X1D (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
(* LOC=LOC, KEEP, DONT_TOUCH *)
RAM128X1D #(
.INIT(128'h0),
.IS_WCLK_INVERTED(1'b0)
) RAM128X1D (
.DPO(dout[0]),
.SPO(dout[1]),
.D(din[0]),
.WCLK(clk),
.WE(din[2]));
endmodule
module my_RAM128X1S (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
(* LOC=LOC, KEEP, DONT_TOUCH *)
RAM128X1S #(
) RAM128X1S (
.O(dout[0]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.A5(din[5]),
.A6(din[6]),
.D(din[7]),
.WCLK(din[0]),
.WE(din[1]));
endmodule
module my_RAM128X1S_2 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
(* LOC=LOC, KEEP, DONT_TOUCH *)
RAM128X1S #(
) lutb (
.O(dout[1]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.A5(din[5]),
.A6(din[6]),
.D(din[7]),
.WCLK(din[0]),
.WE(din[1]));
(* LOC=LOC, KEEP, DONT_TOUCH *)
RAM128X1S #(
) luta (
.O(dout[0]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.A5(din[5]),
.A6(din[6]),
.D(din[7]),
.WCLK(din[0]),
.WE(din[1]));
endmodule
module my_RAM256X1S (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
(* LOC=LOC, KEEP, DONT_TOUCH *)
RAM256X1S #(
) RAM256X1S (
.O(dout[0]),
.A({din[0], din[7:0]}),
.D(din[0]),
.WCLK(din[1]),
.WE(din[2]));
endmodule
module my_RAM32M (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
(* LOC=LOC, KEEP, DONT_TOUCH *)
RAM32M #(
) RAM32M (
.DOA(dout[1:0]),
.DOB(dout[3:2]),
.DOC(dout[5:4]),
.DOD(dout[7:6]),
.ADDRA(din[4:0]),
.ADDRB(din[4:0]),
.ADDRC(din[4:0]),
.ADDRD(din[4:0]),
.DIA(din[5:4]),
.DIB(din[6:5]),
.DIC(din[7:6]),
.DID(din[1:0]),
.WCLK(din[1]),
.WE(din[2]));
endmodule
module my_RAM32X1D (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
(* LOC=LOC, KEEP, DONT_TOUCH *)
RAM32X1D #(
) RAM32X1D (
.DPO(dout[0]),
.SPO(dout[1]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.D(din[5]),
.DPRA0(din[6]),
.DPRA1(din[7]),
.DPRA2(din[0]),
.DPRA3(din[1]),
.DPRA4(din[2]),
.WCLK(din[3]),
.WE(din[4]));
endmodule
/*
Invalid
It tries to place both at D6LUT
module my_RAM32X1D_2 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
(* LOC=LOC, KEEP, DONT_TOUCH *)
RAM32X1D #(
) lutb (
.DPO(dout[3]),
.SPO(dout[2]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.D(din[5]),
.DPRA0(din[6]),
.DPRA1(din[7]),
.DPRA2(din[0]),
.DPRA3(din[1]),
.DPRA4(din[2]),
.WCLK(din[3]),
.WE(din[4]));
(* LOC=LOC, KEEP, DONT_TOUCH *)
RAM32X1D #(
) luta (
.DPO(dout[1]),
.SPO(dout[0]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.D(din[5]),
.DPRA0(din[6]),
.DPRA1(din[7]),
.DPRA2(din[0]),
.DPRA3(din[1]),
.DPRA4(din[2]),
.WCLK(din[3]),
.WE(din[4]));
endmodule
*/
module my_RAM32X1S (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
parameter BEL="A6LUT";
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
RAM32X1S #(
) RAM32X1S (
.O(dout[0]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.D(din[5]),
.WCLK(din[6]),
.WE(din[7]));
endmodule
module my_RAM32X1S_1 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
parameter BEL="A6LUT";
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
RAM32X1S_1 #(
) RAM32X1S_1 (
.O(dout[0]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.D(din[5]),
.WCLK(din[6]),
.WE(din[7]));
endmodule
module my_RAM32X2S (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
(* LOC=LOC, KEEP, DONT_TOUCH *)
RAM32X2S #(
) RAM32X2S (
.O0(dout[0]),
.O1(dout[1]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.D0(din[5]),
.D1(din[6]),
.WCLK(din[7]),
.WE(din[0]));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND2_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__NAND2_PP_BLACKBOX_V
/**
* nand2: 2-input NAND.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__nand2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND2_PP_BLACKBOX_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express
// File : pcie3_7x_0_pcie_bram_7vx_rep.v
// Version : 3.0
//----------------------------------------------------------------------------//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express //
// Filename : pcie3_7x_0_pcie_bram_7vx_rep.v //
// Description : Instantiates replay buffer primitives; Single Port Replay //
// Buffer //
// //
//---------- PIPE Wrapper Hierarchy ------------------------------------------//
// pcie_bram_7vx_rep.v //
// pcie_bram_7vx_rep_8k.v //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie3_7x_0_pcie_bram_7vx_rep #(
parameter IMPL_TARGET = "HARD", // the implementation target, HARD or SOFT
parameter NO_DECODE_LOGIC = "TRUE", // No decode logic, TRUE or FALSE
parameter INTERFACE_SPEED = "500 MHZ", // the memory interface speed, 500 MHz or 250 MHz.
parameter COMPLETION_SPACE = "16 KB" // the completion FIFO spec, 8KB or 16KB
) (
input clk_i, // user clock
input reset_i, // bram reset
input [8:0] addr_i, // write address
input [127:0] wdata_i, // write data
input [15:0] wdip_i, // write parity
input wen0_i, // write enable
input wen1_i, // write enable
output [127:0] rdata_o, // read data
output [15:0] rdop_o // read parity
);
pcie3_7x_0_pcie_bram_7vx_rep_8k # (
.IMPL_TARGET(IMPL_TARGET),
.NO_DECODE_LOGIC(NO_DECODE_LOGIC),
.INTERFACE_SPEED(INTERFACE_SPEED),
.COMPLETION_SPACE(COMPLETION_SPACE)
)
U0
(
.clk_i (clk_i),
.reset_i (reset_i),
.addr_i (addr_i[8:0]),
.wdata_i (wdata_i[127:0]),
.wdip_i (wdip_i[15:0]),
.wen_i ({wen1_i, wen0_i}),
.rdata_o (rdata_o[127:0]),
.rdop_o (rdop_o[15:0])
);
endmodule // pcie_bram_7x_rep
|
//
// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23)
//
// On Mon Feb 3 15:07:11 EST 2014
//
//
// Ports:
// Name I/O size props
// RDY_server_request_put O 1 reg
// server_response_get O 153 reg
// RDY_server_response_get O 1 reg
// client_request_get O 59 reg
// RDY_client_request_get O 1 reg
// RDY_client_response_put O 1 reg
// pciDevice I 16
// CLK I 1 clock
// RST_N I 1 reset
// server_request_put I 153 reg
// client_response_put I 40 reg
// EN_server_request_put I 1
// EN_client_response_put I 1
// EN_server_response_get I 1
// EN_client_request_get I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkTLPSerializer(pciDevice,
CLK,
RST_N,
server_request_put,
EN_server_request_put,
RDY_server_request_put,
EN_server_response_get,
server_response_get,
RDY_server_response_get,
EN_client_request_get,
client_request_get,
RDY_client_request_get,
client_response_put,
EN_client_response_put,
RDY_client_response_put);
input [15 : 0] pciDevice;
input CLK;
input RST_N;
// action method server_request_put
input [152 : 0] server_request_put;
input EN_server_request_put;
output RDY_server_request_put;
// actionvalue method server_response_get
input EN_server_response_get;
output [152 : 0] server_response_get;
output RDY_server_response_get;
// actionvalue method client_request_get
input EN_client_request_get;
output [58 : 0] client_request_get;
output RDY_client_request_get;
// action method client_response_put
input [39 : 0] client_response_put;
input EN_client_response_put;
output RDY_client_response_put;
// signals for module outputs
wire [152 : 0] server_response_get;
wire [58 : 0] client_request_get;
wire RDY_client_request_get,
RDY_client_response_put,
RDY_server_request_put,
RDY_server_response_get;
// register cmpActive
reg cmpActive;
wire cmpActive_D_IN, cmpActive_EN;
// register cmpDWRemain
reg [9 : 0] cmpDWRemain;
wire [9 : 0] cmpDWRemain_D_IN;
wire cmpDWRemain_EN;
// register rdp
reg [1 : 0] rdp;
wire [1 : 0] rdp_D_IN;
wire rdp_EN;
// register rdv
reg [127 : 0] rdv;
wire [127 : 0] rdv_D_IN;
wire rdv_EN;
// register rss
reg [1 : 0] rss;
wire [1 : 0] rss_D_IN;
wire rss_EN;
// register tlpActive
reg tlpActive;
wire tlpActive_D_IN, tlpActive_EN;
// register tlpDW
reg [31 : 0] tlpDW;
wire [31 : 0] tlpDW_D_IN;
wire tlpDW_EN;
// register tlpDWAddr
reg [29 : 0] tlpDWAddr;
wire [29 : 0] tlpDWAddr_D_IN;
wire tlpDWAddr_EN;
// register tlpDWp
reg [1 : 0] tlpDWp;
wire [1 : 0] tlpDWp_D_IN;
wire tlpDWp_EN;
// register tlpFirst
reg tlpFirst;
wire tlpFirst_D_IN, tlpFirst_EN;
// register tlpReq
reg [63 : 0] tlpReq;
wire [63 : 0] tlpReq_D_IN;
wire tlpReq_EN;
// register tlpUnroll
reg [9 : 0] tlpUnroll;
wire [9 : 0] tlpUnroll_D_IN;
wire tlpUnroll_EN;
// ports of submodule cmpF
wire [55 : 0] cmpF_D_IN, cmpF_D_OUT;
wire cmpF_CLR, cmpF_DEQ, cmpF_EMPTY_N, cmpF_ENQ, cmpF_FULL_N;
// ports of submodule cpReqF
wire [58 : 0] cpReqF_D_IN, cpReqF_D_OUT;
wire cpReqF_CLR, cpReqF_DEQ, cpReqF_EMPTY_N, cpReqF_ENQ, cpReqF_FULL_N;
// ports of submodule cpRespF
wire [39 : 0] cpRespF_D_IN, cpRespF_D_OUT;
wire cpRespF_CLR, cpRespF_DEQ, cpRespF_EMPTY_N, cpRespF_ENQ, cpRespF_FULL_N;
// ports of submodule inF
wire [152 : 0] inF_D_IN, inF_D_OUT;
wire inF_CLR, inF_DEQ, inF_EMPTY_N, inF_ENQ, inF_FULL_N;
// ports of submodule outF
wire [152 : 0] outF_D_IN, outF_D_OUT;
wire outF_CLR, outF_DEQ, outF_EMPTY_N, outF_ENQ, outF_FULL_N;
// rule scheduling signals
wire WILL_FIRE_RL_tlpFirstComplWord,
WILL_FIRE_RL_tlpFirstRcv,
WILL_FIRE_RL_tlpNextComplWord,
WILL_FIRE_RL_tlpReqGen,
WILL_FIRE_RL_tlpStageNextWord;
// inputs to muxes for submodule ports
wire [152 : 0] MUX_outF_enq_1__VAL_1, MUX_outF_enq_1__VAL_2;
wire [29 : 0] MUX_tlpDWAddr_write_1__VAL_2;
wire [9 : 0] MUX_cmpDWRemain_write_1__VAL_1,
MUX_cmpDWRemain_write_1__VAL_2,
MUX_tlpUnroll_write_1__VAL_2;
wire [1 : 0] MUX_rdp_write_1__VAL_1,
MUX_rss_write_1__VAL_2,
MUX_tlpDWp_write_1__VAL_1;
wire MUX_cmpActive_write_1__SEL_1,
MUX_tlpActive_write_1__SEL_1,
MUX_tlpDWAddr_write_1__SEL_1,
MUX_tlpDWp_write_1__SEL_1;
// remaining internal signals
reg [31 : 0] v__h2549;
reg [15 : 0] lastRema__h7245;
reg [1 : 0] lowAddr10__h2074, x__h2304, x__h2327;
wire [127 : 0] pkt__h4230, pw_data__h7278;
wire [57 : 0] IF_tlpReq_3_BIT_62_4_THEN_tlpDWAddr_8_BITS_21__ETC___d113;
wire [31 : 0] IF_tlpReq_3_BIT_62_4_AND_NOT_tlpFirst_6_4_5_TH_ETC___d102,
wreq_data__h3050;
wire [15 : 0] pw_be__h7277;
wire [11 : 0] byteCount__h2076, x__h2295, x__h2297, y__h2296, y__h2298;
wire [6 : 0] lowAddr__h2075;
wire [3 : 0] _theResult_____2__h2491;
wire [2 : 0] x__h7701;
wire cpReqF_i_notFull__2_AND_NOT_tlpReq_3_BIT_62_4__ETC___d82;
// action method server_request_put
assign RDY_server_request_put = inF_FULL_N ;
// actionvalue method server_response_get
assign server_response_get = outF_D_OUT ;
assign RDY_server_response_get = outF_EMPTY_N ;
// actionvalue method client_request_get
assign client_request_get = cpReqF_D_OUT ;
assign RDY_client_request_get = cpReqF_EMPTY_N ;
// action method client_response_put
assign RDY_client_response_put = cpRespF_FULL_N ;
// submodule cmpF
FIFO2 #(.width(32'd56), .guarded(32'd1)) cmpF(.RST(RST_N),
.CLK(CLK),
.D_IN(cmpF_D_IN),
.ENQ(cmpF_ENQ),
.DEQ(cmpF_DEQ),
.CLR(cmpF_CLR),
.D_OUT(cmpF_D_OUT),
.FULL_N(cmpF_FULL_N),
.EMPTY_N(cmpF_EMPTY_N));
// submodule cpReqF
FIFO2 #(.width(32'd59), .guarded(32'd1)) cpReqF(.RST(RST_N),
.CLK(CLK),
.D_IN(cpReqF_D_IN),
.ENQ(cpReqF_ENQ),
.DEQ(cpReqF_DEQ),
.CLR(cpReqF_CLR),
.D_OUT(cpReqF_D_OUT),
.FULL_N(cpReqF_FULL_N),
.EMPTY_N(cpReqF_EMPTY_N));
// submodule cpRespF
FIFO2 #(.width(32'd40), .guarded(32'd1)) cpRespF(.RST(RST_N),
.CLK(CLK),
.D_IN(cpRespF_D_IN),
.ENQ(cpRespF_ENQ),
.DEQ(cpRespF_DEQ),
.CLR(cpRespF_CLR),
.D_OUT(cpRespF_D_OUT),
.FULL_N(cpRespF_FULL_N),
.EMPTY_N(cpRespF_EMPTY_N));
// submodule inF
FIFO2 #(.width(32'd153), .guarded(32'd1)) inF(.RST(RST_N),
.CLK(CLK),
.D_IN(inF_D_IN),
.ENQ(inF_ENQ),
.DEQ(inF_DEQ),
.CLR(inF_CLR),
.D_OUT(inF_D_OUT),
.FULL_N(inF_FULL_N),
.EMPTY_N(inF_EMPTY_N));
// submodule outF
FIFO2 #(.width(32'd153), .guarded(32'd1)) outF(.RST(RST_N),
.CLK(CLK),
.D_IN(outF_D_IN),
.ENQ(outF_ENQ),
.DEQ(outF_DEQ),
.CLR(outF_CLR),
.D_OUT(outF_D_OUT),
.FULL_N(outF_FULL_N),
.EMPTY_N(outF_EMPTY_N));
// rule RL_tlpFirstRcv
assign WILL_FIRE_RL_tlpFirstRcv =
inF_EMPTY_N &&
(!inF_D_OUT[152] || inF_D_OUT[110] || inF_D_OUT[125] ||
inF_D_OUT[124:120] != 5'b0 ||
inF_D_OUT[126] ||
cmpF_FULL_N) &&
!tlpActive ;
// rule RL_tlpReqGen
assign WILL_FIRE_RL_tlpReqGen =
cpReqF_i_notFull__2_AND_NOT_tlpReq_3_BIT_62_4__ETC___d82 &&
tlpActive ;
// rule RL_tlpFirstComplWord
assign WILL_FIRE_RL_tlpFirstComplWord =
cmpF_EMPTY_N && cpRespF_EMPTY_N && outF_FULL_N && !cmpActive ;
// rule RL_tlpStageNextWord
assign WILL_FIRE_RL_tlpStageNextWord =
cpRespF_EMPTY_N && cmpActive && cmpDWRemain != 10'd0 &&
!WILL_FIRE_RL_tlpNextComplWord ;
// rule RL_tlpNextComplWord
assign WILL_FIRE_RL_tlpNextComplWord =
outF_FULL_N && cmpActive && rss != 2'd0 ;
// inputs to muxes for submodule ports
assign MUX_cmpActive_write_1__SEL_1 =
WILL_FIRE_RL_tlpNextComplWord && rss == 2'd2 ;
assign MUX_tlpActive_write_1__SEL_1 =
WILL_FIRE_RL_tlpReqGen && tlpUnroll == 10'd1 ;
assign MUX_tlpDWAddr_write_1__SEL_1 =
WILL_FIRE_RL_tlpFirstRcv && inF_D_OUT[152] && !inF_D_OUT[110] &&
!inF_D_OUT[125] &&
inF_D_OUT[124:120] == 5'b0 ;
assign MUX_tlpDWp_write_1__SEL_1 =
WILL_FIRE_RL_tlpReqGen && tlpReq[62] && !tlpFirst ;
assign MUX_cmpDWRemain_write_1__VAL_1 = cmpF_D_OUT[21:12] - 10'd1 ;
assign MUX_cmpDWRemain_write_1__VAL_2 = cmpDWRemain - 10'd1 ;
assign MUX_outF_enq_1__VAL_1 =
{ 1'd1, cmpF_D_OUT[21:12] == 10'd1, 23'h2AFFFF, pkt__h4230 } ;
assign MUX_outF_enq_1__VAL_2 =
{ 1'd0, rss == 2'd2, 7'h2A, pw_be__h7277, pw_data__h7278 } ;
assign MUX_rdp_write_1__VAL_1 = rdp + 2'd1 ;
assign MUX_rss_write_1__VAL_2 = (cmpDWRemain == 10'd1) ? 2'd2 : 2'd1 ;
assign MUX_tlpDWAddr_write_1__VAL_2 = tlpDWAddr + 30'd1 ;
assign MUX_tlpDWp_write_1__VAL_1 = tlpDWp - 2'd1 ;
assign MUX_tlpUnroll_write_1__VAL_2 = tlpUnroll - 10'd1 ;
// register cmpActive
assign cmpActive_D_IN = !MUX_cmpActive_write_1__SEL_1 ;
assign cmpActive_EN =
WILL_FIRE_RL_tlpNextComplWord && rss == 2'd2 ||
WILL_FIRE_RL_tlpFirstComplWord && cmpF_D_OUT[21:12] != 10'd1 ;
// register cmpDWRemain
assign cmpDWRemain_D_IN =
WILL_FIRE_RL_tlpFirstComplWord ?
MUX_cmpDWRemain_write_1__VAL_1 :
MUX_cmpDWRemain_write_1__VAL_2 ;
assign cmpDWRemain_EN =
WILL_FIRE_RL_tlpFirstComplWord || WILL_FIRE_RL_tlpStageNextWord ;
// register rdp
assign rdp_D_IN =
WILL_FIRE_RL_tlpStageNextWord ? MUX_rdp_write_1__VAL_1 : 2'd0 ;
assign rdp_EN =
WILL_FIRE_RL_tlpStageNextWord || WILL_FIRE_RL_tlpNextComplWord ;
// register rdv
assign rdv_D_IN =
{ rdv[95:0],
cpRespF_D_OUT[7:0],
cpRespF_D_OUT[15:8],
cpRespF_D_OUT[23:16],
cpRespF_D_OUT[31:24] } ;
assign rdv_EN = WILL_FIRE_RL_tlpStageNextWord ;
// register rss
assign rss_D_IN =
MUX_cmpActive_write_1__SEL_1 ? 2'd0 : MUX_rss_write_1__VAL_2 ;
assign rss_EN =
WILL_FIRE_RL_tlpNextComplWord && rss == 2'd2 ||
WILL_FIRE_RL_tlpStageNextWord &&
(cmpDWRemain == 10'd1 || rdp == 2'd3) ;
// register tlpActive
assign tlpActive_D_IN = !MUX_tlpActive_write_1__SEL_1 ;
assign tlpActive_EN =
WILL_FIRE_RL_tlpReqGen && tlpUnroll == 10'd1 ||
WILL_FIRE_RL_tlpFirstRcv ;
// register tlpDW
assign tlpDW_D_IN = inF_D_OUT[31:0] ;
assign tlpDW_EN = MUX_tlpDWAddr_write_1__SEL_1 ;
// register tlpDWAddr
assign tlpDWAddr_D_IN =
MUX_tlpDWAddr_write_1__SEL_1 ?
inF_D_OUT[63:34] :
MUX_tlpDWAddr_write_1__VAL_2 ;
assign tlpDWAddr_EN =
WILL_FIRE_RL_tlpFirstRcv && inF_D_OUT[152] && !inF_D_OUT[110] &&
!inF_D_OUT[125] &&
inF_D_OUT[124:120] == 5'b0 ||
WILL_FIRE_RL_tlpReqGen ;
// register tlpDWp
assign tlpDWp_D_IN =
MUX_tlpDWp_write_1__SEL_1 ? MUX_tlpDWp_write_1__VAL_1 : 2'd3 ;
assign tlpDWp_EN =
WILL_FIRE_RL_tlpReqGen && tlpReq[62] && !tlpFirst ||
WILL_FIRE_RL_tlpFirstRcv && inF_D_OUT[152] && !inF_D_OUT[110] &&
!inF_D_OUT[125] &&
inF_D_OUT[124:120] == 5'b0 ;
// register tlpFirst
assign tlpFirst_D_IN = MUX_tlpDWAddr_write_1__SEL_1 ;
assign tlpFirst_EN =
WILL_FIRE_RL_tlpFirstRcv && inF_D_OUT[152] && !inF_D_OUT[110] &&
!inF_D_OUT[125] &&
inF_D_OUT[124:120] == 5'b0 ||
WILL_FIRE_RL_tlpReqGen ;
// register tlpReq
assign tlpReq_D_IN =
{ 1'b0,
inF_D_OUT[126:120],
1'b0,
inF_D_OUT[118:116],
4'b0,
inF_D_OUT[111:108],
2'b0,
inF_D_OUT[105:64] } ;
assign tlpReq_EN = MUX_tlpDWAddr_write_1__SEL_1 ;
// register tlpUnroll
assign tlpUnroll_D_IN =
MUX_tlpDWAddr_write_1__SEL_1 ?
inF_D_OUT[105:96] :
MUX_tlpUnroll_write_1__VAL_2 ;
assign tlpUnroll_EN =
WILL_FIRE_RL_tlpFirstRcv && inF_D_OUT[152] && !inF_D_OUT[110] &&
!inF_D_OUT[125] &&
inF_D_OUT[124:120] == 5'b0 ||
WILL_FIRE_RL_tlpReqGen ;
// submodule cmpF
assign cmpF_D_IN =
{ inF_D_OUT[95:80],
inF_D_OUT[118:116],
inF_D_OUT[79:72],
lowAddr__h2075,
inF_D_OUT[105:96],
byteCount__h2076 } ;
assign cmpF_ENQ =
WILL_FIRE_RL_tlpFirstRcv && inF_D_OUT[152] && !inF_D_OUT[110] &&
!inF_D_OUT[125] &&
inF_D_OUT[124:120] == 5'b0 &&
!inF_D_OUT[126] ;
assign cmpF_DEQ = WILL_FIRE_RL_tlpFirstComplWord ;
assign cmpF_CLR = 1'b0 ;
// submodule cpReqF
assign cpReqF_D_IN =
{ !tlpReq[62],
IF_tlpReq_3_BIT_62_4_THEN_tlpDWAddr_8_BITS_21__ETC___d113 } ;
assign cpReqF_ENQ =
cpReqF_i_notFull__2_AND_NOT_tlpReq_3_BIT_62_4__ETC___d82 &&
tlpActive ;
assign cpReqF_DEQ = EN_client_request_get ;
assign cpReqF_CLR = 1'b0 ;
// submodule cpRespF
assign cpRespF_D_IN = client_response_put ;
assign cpRespF_ENQ = EN_client_response_put ;
assign cpRespF_DEQ =
WILL_FIRE_RL_tlpFirstComplWord || WILL_FIRE_RL_tlpStageNextWord ;
assign cpRespF_CLR = 1'b0 ;
// submodule inF
assign inF_D_IN = server_request_put ;
assign inF_ENQ = EN_server_request_put ;
assign inF_DEQ =
WILL_FIRE_RL_tlpReqGen && tlpReq[62] && !tlpFirst ||
WILL_FIRE_RL_tlpFirstRcv ;
assign inF_CLR = 1'b0 ;
// submodule outF
assign outF_D_IN =
WILL_FIRE_RL_tlpFirstComplWord ?
MUX_outF_enq_1__VAL_1 :
MUX_outF_enq_1__VAL_2 ;
assign outF_ENQ =
WILL_FIRE_RL_tlpFirstComplWord || WILL_FIRE_RL_tlpNextComplWord ;
assign outF_DEQ = EN_server_response_get ;
assign outF_CLR = 1'b0 ;
// remaining internal signals
assign IF_tlpReq_3_BIT_62_4_AND_NOT_tlpFirst_6_4_5_TH_ETC___d102 =
(tlpReq[62] && !tlpFirst) ? v__h2549 : tlpDW ;
assign IF_tlpReq_3_BIT_62_4_THEN_tlpDWAddr_8_BITS_21__ETC___d113 =
tlpReq[62] ?
{ tlpDWAddr[21:0],
_theResult_____2__h2491,
wreq_data__h3050 } :
{ 24'hAAAAAA,
tlpReq[15:8],
tlpDWAddr[21:0],
_theResult_____2__h2491 } ;
assign _theResult_____2__h2491 =
tlpFirst ?
tlpReq[3:0] :
((tlpUnroll == 10'd1) ? tlpReq[7:4] : 4'hF) ;
assign byteCount__h2076 = x__h2295 - y__h2296 ;
assign cpReqF_i_notFull__2_AND_NOT_tlpReq_3_BIT_62_4__ETC___d82 =
cpReqF_FULL_N && (!tlpReq[62] || tlpFirst || inF_EMPTY_N) ;
assign lowAddr__h2075 = { inF_D_OUT[38:34], lowAddr10__h2074 } ;
assign pkt__h4230 =
{ 9'd148,
cmpF_D_OUT[39:37],
10'd0,
cmpF_D_OUT[21:12],
pciDevice,
4'd0,
cmpF_D_OUT[11:0],
cmpF_D_OUT[55:40],
cmpF_D_OUT[36:29],
1'b0,
cmpF_D_OUT[28:22],
cpRespF_D_OUT[7:0],
cpRespF_D_OUT[15:8],
cpRespF_D_OUT[23:16],
cpRespF_D_OUT[31:24] } ;
assign pw_be__h7277 = (rss == 2'd2) ? lastRema__h7245 : 16'd65535 ;
assign pw_data__h7278 =
x__h7701[1] ?
(x__h7701[0] ?
{ rdv[31:0], rdv[127:32] } :
{ rdv[63:0], rdv[127:64] }) :
(x__h7701[0] ? { rdv[95:0], rdv[127:96] } : rdv) ;
assign wreq_data__h3050 =
{ IF_tlpReq_3_BIT_62_4_AND_NOT_tlpFirst_6_4_5_TH_ETC___d102[7:0],
IF_tlpReq_3_BIT_62_4_AND_NOT_tlpFirst_6_4_5_TH_ETC___d102[15:8],
IF_tlpReq_3_BIT_62_4_AND_NOT_tlpFirst_6_4_5_TH_ETC___d102[23:16],
IF_tlpReq_3_BIT_62_4_AND_NOT_tlpFirst_6_4_5_TH_ETC___d102[31:24] } ;
assign x__h2295 = x__h2297 - y__h2298 ;
assign x__h2297 = { inF_D_OUT[105:96], 2'b0 } ;
assign x__h7701 = 3'h4 - { 1'd0, rdp } ;
assign y__h2296 =
(inF_D_OUT[105:96] == 10'd1) ? 12'd0 : { 10'd0, x__h2327 } ;
assign y__h2298 = { 10'd0, x__h2304 } ;
always@(inF_D_OUT)
begin
case (inF_D_OUT[67:64])
4'b1100: x__h2304 = 2'b10;
4'b1110: x__h2304 = 2'b01;
4'b1111: x__h2304 = 2'b0;
default: x__h2304 = 2'b11;
endcase
end
always@(inF_D_OUT)
begin
case (inF_D_OUT[71:68])
4'b1100: x__h2327 = 2'b10;
4'b1110: x__h2327 = 2'b01;
4'b1111: x__h2327 = 2'b0;
default: x__h2327 = 2'b11;
endcase
end
always@(tlpDWp or inF_D_OUT)
begin
case (tlpDWp)
2'd0: v__h2549 = inF_D_OUT[31:0];
2'd1: v__h2549 = inF_D_OUT[63:32];
2'd2: v__h2549 = inF_D_OUT[95:64];
2'd3: v__h2549 = inF_D_OUT[127:96];
endcase
end
always@(rdp)
begin
case (rdp)
2'b0: lastRema__h7245 = 16'hFFFF;
2'b01: lastRema__h7245 = 16'hF000;
2'b10: lastRema__h7245 = 16'hFF00;
2'd3: lastRema__h7245 = 16'hFFF0;
endcase
end
always@(inF_D_OUT)
begin
case (inF_D_OUT[67:64])
4'b1000: lowAddr10__h2074 = 2'b11;
4'b1100: lowAddr10__h2074 = 2'b10;
4'b1110: lowAddr10__h2074 = 2'b01;
default: lowAddr10__h2074 = 2'b0;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
cmpActive <= `BSV_ASSIGNMENT_DELAY 1'd0;
rdp <= `BSV_ASSIGNMENT_DELAY 2'd0;
rss <= `BSV_ASSIGNMENT_DELAY 2'd0;
tlpActive <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (cmpActive_EN) cmpActive <= `BSV_ASSIGNMENT_DELAY cmpActive_D_IN;
if (rdp_EN) rdp <= `BSV_ASSIGNMENT_DELAY rdp_D_IN;
if (rss_EN) rss <= `BSV_ASSIGNMENT_DELAY rss_D_IN;
if (tlpActive_EN) tlpActive <= `BSV_ASSIGNMENT_DELAY tlpActive_D_IN;
end
if (cmpDWRemain_EN) cmpDWRemain <= `BSV_ASSIGNMENT_DELAY cmpDWRemain_D_IN;
if (rdv_EN) rdv <= `BSV_ASSIGNMENT_DELAY rdv_D_IN;
if (tlpDW_EN) tlpDW <= `BSV_ASSIGNMENT_DELAY tlpDW_D_IN;
if (tlpDWAddr_EN) tlpDWAddr <= `BSV_ASSIGNMENT_DELAY tlpDWAddr_D_IN;
if (tlpDWp_EN) tlpDWp <= `BSV_ASSIGNMENT_DELAY tlpDWp_D_IN;
if (tlpFirst_EN) tlpFirst <= `BSV_ASSIGNMENT_DELAY tlpFirst_D_IN;
if (tlpReq_EN) tlpReq <= `BSV_ASSIGNMENT_DELAY tlpReq_D_IN;
if (tlpUnroll_EN) tlpUnroll <= `BSV_ASSIGNMENT_DELAY tlpUnroll_D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
cmpActive = 1'h0;
cmpDWRemain = 10'h2AA;
rdp = 2'h2;
rdv = 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
rss = 2'h2;
tlpActive = 1'h0;
tlpDW = 32'hAAAAAAAA;
tlpDWAddr = 30'h2AAAAAAA;
tlpDWp = 2'h2;
tlpFirst = 1'h0;
tlpReq = 64'hAAAAAAAAAAAAAAAA;
tlpUnroll = 10'h2AA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkTLPSerializer
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLXBP_TB_V
`define SKY130_FD_SC_MS__DLXBP_TB_V
/**
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dlxbp.v"
module top();
// Inputs are registered
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_ms__dlxbp dut (.D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLXBP_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISOLATCH_PP_SYMBOL_V
`define SKY130_FD_SC_LP__INPUTISOLATCH_PP_SYMBOL_V
/**
* inputisolatch: Latching input isolator with inverted enable.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__inputisolatch (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{power|Power}}
input SLEEP_B,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISOLATCH_PP_SYMBOL_V
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 09:04:39 2016
/////////////////////////////////////////////////////////////
module SNPS_CLOCK_GATE_HIGH_FSM_Add_Subtract_44 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Add_Subtract_Function_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W8_43 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Add_Subtract_Function_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W5_42 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Add_Subtract_Function_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_1_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Add_Subtract_Function_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_1_3 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Add_Subtract_Function_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_6 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Add_Subtract_Function_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_0_4 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Add_Subtract_Function_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_0_5 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Add_Subtract_Function_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule
module FPU_Add_Subtract_Function_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_FSM,
ack_FSM, Data_X, Data_Y, add_subt, r_mode, overflow_flag,
underflow_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
input [1:0] r_mode;
output [31:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM, add_subt;
output overflow_flag, underflow_flag, ready;
wire FSM_selector_C, add_overflow_flag, FSM_exp_operation_load_diff,
FSM_barrel_shifter_load, FSM_Add_Subt_Sgf_load, FSM_LZA_load,
FSM_Final_Result_load, FSM_selector_D, sign_final_result,
FS_Module_net3641811, final_result_ieee_Module_Sign_S_mux,
YRegister_net3641721, Exp_Operation_Module_exp_result_net3641775,
Leading_Zero_Detector_Module_Output_Reg_net3641739,
final_result_ieee_Module_Final_Result_IEEE_net3641721,
Add_Subt_Sgf_module_Add_Subt_Result_net3641757,
Oper_Start_in_module_MRegister_net3641793,
Barrel_Shifter_module_Output_Reg_net3641757, n400, n401, n404, n405,
n406, n407, n411, n412, n413, DP_OP_42J178_122_8048_n20,
DP_OP_42J178_122_8048_n19, DP_OP_42J178_122_8048_n18,
DP_OP_42J178_122_8048_n17, DP_OP_42J178_122_8048_n16,
DP_OP_42J178_122_8048_n15, DP_OP_42J178_122_8048_n14,
DP_OP_42J178_122_8048_n13, DP_OP_42J178_122_8048_n8,
DP_OP_42J178_122_8048_n7, DP_OP_42J178_122_8048_n6,
DP_OP_42J178_122_8048_n5, DP_OP_42J178_122_8048_n4,
DP_OP_42J178_122_8048_n3, DP_OP_42J178_122_8048_n2,
DP_OP_42J178_122_8048_n1, DP_OP_45J178_125_5354_n56,
DP_OP_45J178_125_5354_n55, DP_OP_45J178_125_5354_n54,
DP_OP_45J178_125_5354_n53, DP_OP_45J178_125_5354_n52,
DP_OP_45J178_125_5354_n51, DP_OP_45J178_125_5354_n50,
DP_OP_45J178_125_5354_n49, DP_OP_45J178_125_5354_n48,
DP_OP_45J178_125_5354_n47, DP_OP_45J178_125_5354_n46,
DP_OP_45J178_125_5354_n45, DP_OP_45J178_125_5354_n44,
DP_OP_45J178_125_5354_n43, DP_OP_45J178_125_5354_n42,
DP_OP_45J178_125_5354_n41, DP_OP_45J178_125_5354_n40,
DP_OP_45J178_125_5354_n39, DP_OP_45J178_125_5354_n38,
DP_OP_45J178_125_5354_n37, DP_OP_45J178_125_5354_n36,
DP_OP_45J178_125_5354_n35, DP_OP_45J178_125_5354_n34,
DP_OP_45J178_125_5354_n33, DP_OP_45J178_125_5354_n32,
DP_OP_45J178_125_5354_n31, DP_OP_45J178_125_5354_n26,
DP_OP_45J178_125_5354_n25, DP_OP_45J178_125_5354_n24,
DP_OP_45J178_125_5354_n23, DP_OP_45J178_125_5354_n22,
DP_OP_45J178_125_5354_n21, DP_OP_45J178_125_5354_n20,
DP_OP_45J178_125_5354_n19, DP_OP_45J178_125_5354_n18,
DP_OP_45J178_125_5354_n17, DP_OP_45J178_125_5354_n16,
DP_OP_45J178_125_5354_n15, DP_OP_45J178_125_5354_n14,
DP_OP_45J178_125_5354_n13, DP_OP_45J178_125_5354_n12,
DP_OP_45J178_125_5354_n11, DP_OP_45J178_125_5354_n10,
DP_OP_45J178_125_5354_n9, DP_OP_45J178_125_5354_n8,
DP_OP_45J178_125_5354_n7, DP_OP_45J178_125_5354_n6,
DP_OP_45J178_125_5354_n5, DP_OP_45J178_125_5354_n4,
DP_OP_45J178_125_5354_n3, DP_OP_45J178_125_5354_n2,
DP_OP_45J178_125_5354_n1, n420, n421, n422, n423, n424, n425, n426,
n427, n428, n429, n430, n431, n433, n434, n435, n436, n437, n438,
n439, n440, n441, n442, n443, n444, n445, n446, n447, n448, n449,
n450, n451, n452, n453, n454, n455, n456, n457, n458, n459, n460,
n461, n462, n463, n464, n465, n466, n467, n468, n469, n470, n471,
n472, n473, n474, n475, n476, n477, n478, n479, n480, n481, n482,
n483, n484, n485, n486, n487, n488, n489, n490, n491, n492, n493,
n494, n495, n496, n497, n498, n499, n500, n501, n502, n503, n504,
n505, n506, n507, n508, n509, n510, n511, n512, n513, n514, n515,
n516, n517, n518, n519, n520, n521, n522, n523, n524, n525, n526,
n527, n528, n529, n530, n531, n532, n533, n534, n535, n536, n537,
n538, n539, n540, n541, n542, n543, n544, n545, n546, n547, n548,
n549, n550, n551, n552, n553, n554, n555, n556, n557, n558, n559,
n560, n561, n562, n563, n564, n565, n566, n567, n568, n569, n570,
n571, n572, n573, n574, n575, n576, n577, n578, n579, n580, n581,
n582, n583, n584, n585, n586, n587, n588, n589, n590, n591, n592,
n593, n594, n595, n596, n597, n598, n599, n600, n601, n602, n603,
n604, n605, n606, n607, n608, n609, n610, n611, n612, n613, n614,
n615, n616, n617, n618, n619, n620, n621, n622, n623, n624, n625,
n626, n627, n628, n629, n630, n631, n632, n633, n634, n635, n636,
n637, n638, n639, n640, n641, n642, n643, n644, n645, n646, n647,
n648, n649, n650, n651, n652, n653, n654, n655, n656, n657, n658,
n659, n660, n661, n662, n663, n664, n665, n666, n667, n668, n669,
n670, n671, n672, n673, n674, n675, n676, n677, n678, n679, n680,
n681, n682, n683, n684, n685, n686, n687, n688, n689, n690, n691,
n692, n693, n694, n695, n696, n697, n698, n699, n700, n701, n702,
n703, n704, n705, n706, n707, n708, n709, n710, n711, n712, n713,
n714, n715, n716, n717, n718, n719, n720, n721, n722, n723, n724,
n725, n726, n727, n728, n729, n730, n731, n732, n733, n734, n735,
n736, n737, n738, n739, n740, n741, n742, n743, n744, n745, n746,
n747, n748, n749, n750, n751, n752, n753, n754, n755, n756, n757,
n758, n759, n760, n761, n762, n763, n764, n765, n766, n767, n768,
n769, n770, n771, n772, n773, n774, n775, n776, n778, n779, n780,
n781, n782, n783, n784, n785, n786, n787, n788, n789, n790, n791,
n792, n793, n794, n795, n796, n797, n798, n799, n800, n801, n802,
n803, n804, n805, n806, n807, n808, n809, n810, n811, n812, n813,
n814, n815, n816, n817, n818, n819, n820, n821, n822, n823, n824,
n825, n826, n827, n828, n829, n830, n831, n832, n833, n834, n835,
n836, n837, n838, n839, n840, n841, n842, n843, n844, n845, n846,
n847, n848, n850, n851, n852, n853, n854, n855, n856, n857, n858,
n859, n860, n861, n862, n863, n864, n865, n866, n867, n868, n869,
n870, n871, n872, n873, n874, n875, n876, n877, n878, n879, n880,
n881, n882, n883, n884, n885, n886, n887, n888, n889, n890, n891,
n892, n893, n894, n895, n896, n897, n898, n899, n900, n901, n902,
n903, n904, n905, n906, n907, n908, n909, n910, n911, n912, n913,
n914, n915, n916, n917, n918, n919, n920, n921, n922, n923, n924,
n925, n926, n927, n928, n929, n930, n931, n932, n933, n934, n935,
n936, n937, n938, n939, n940, n941, n942, n943, n944, n945, n946,
n947, n948, n949, n950, n951, n952, n953, n954, n955, n956, n957,
n958, n959, n960, n961, n962, n963, n964, n965, n966, n967, n968,
n969, n970, n971, n972, n973, n974, n976, n977, n978, n979, n980,
n981, n982, n983, n984, n985, n986, n987, n988, n989, n990, n991,
n992, n993, n994, n995, n997, n998, n999, n1000, n1001, n1002, n1003,
n1004, n1005, n1006, n1007, n1008, n1009, n1010, n1011, n1012, n1013,
n1014, n1015, n1016, n1017, n1018, n1019, n1020, n1021, n1022, n1023,
n1024, n1025, n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033,
n1034, n1035, n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043,
n1044, n1045, n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053,
n1054, n1055, n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063,
n1064, n1065, n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073,
n1074, n1075, n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083,
n1084, n1085, n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093,
n1094, n1095, n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1104,
n1105, n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114,
n1115, n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124,
n1125, n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134,
n1135, n1136, n1137, n1138, n1139;
wire [1:0] FSM_selector_B;
wire [31:0] intDX;
wire [30:0] intDY;
wire [30:0] DMP;
wire [30:0] DmP;
wire [7:0] exp_oper_result;
wire [7:0] S_Oper_A_exp;
wire [4:0] LZA_output;
wire [25:0] Add_Subt_result;
wire [25:0] Sgf_normalized_result;
wire [25:0] S_A_S_Oper_A;
wire [3:0] FS_Module_state_next;
wire [3:0] FS_Module_state_reg;
wire [30:0] Oper_Start_in_module_intm;
wire [30:0] Oper_Start_in_module_intM;
wire [7:0] Exp_Operation_Module_Data_S;
wire [26:0] Add_Subt_Sgf_module_S_to_D;
wire [4:0] Leading_Zero_Detector_Module_Codec_to_Reg;
wire [22:0] final_result_ieee_Module_Sgf_S_mux;
wire [7:0] final_result_ieee_Module_Exp_S_mux;
wire [51:0] Barrel_Shifter_module_Mux_Array_Data_array;
SNPS_CLOCK_GATE_HIGH_FSM_Add_Subtract_44 FS_Module_clk_gate_state_reg_reg (
.CLK(clk), .EN(n412), .ENCLK(FS_Module_net3641811), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_0_5 YRegister_clk_gate_Q_reg ( .CLK(clk), .EN(n411), .ENCLK(YRegister_net3641721), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W8_43 Exp_Operation_Module_exp_result_clk_gate_Q_reg (
.CLK(clk), .EN(FSM_exp_operation_load_diff), .ENCLK(
Exp_Operation_Module_exp_result_net3641775), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W5_42 Leading_Zero_Detector_Module_Output_Reg_clk_gate_Q_reg (
.CLK(clk), .EN(FSM_LZA_load), .ENCLK(
Leading_Zero_Detector_Module_Output_Reg_net3641739), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_0_4 final_result_ieee_Module_Final_Result_IEEE_clk_gate_Q_reg (
.CLK(clk), .EN(FSM_Final_Result_load), .ENCLK(
final_result_ieee_Module_Final_Result_IEEE_net3641721), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_1_2 Add_Subt_Sgf_module_Add_Subt_Result_clk_gate_Q_reg (
.CLK(clk), .EN(FSM_Add_Subt_Sgf_load), .ENCLK(
Add_Subt_Sgf_module_Add_Subt_Result_net3641757), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_6 Oper_Start_in_module_MRegister_clk_gate_Q_reg (
.CLK(clk), .EN(n413), .ENCLK(Oper_Start_in_module_MRegister_net3641793), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_1_3 Barrel_Shifter_module_Output_Reg_clk_gate_Q_reg (
.CLK(clk), .EN(FSM_barrel_shifter_load), .ENCLK(
Barrel_Shifter_module_Output_Reg_net3641757), .TE(1'b0) );
DFFRXLTS Exp_Operation_Module_exp_result_Q_reg_7_ ( .D(
Exp_Operation_Module_Data_S[7]), .CK(
Exp_Operation_Module_exp_result_net3641775), .RN(n421), .Q(
exp_oper_result[7]) );
DFFRXLTS Exp_Operation_Module_exp_result_Q_reg_6_ ( .D(
Exp_Operation_Module_Data_S[6]), .CK(
Exp_Operation_Module_exp_result_net3641775), .RN(n1108), .Q(
exp_oper_result[6]) );
DFFRXLTS Exp_Operation_Module_exp_result_Q_reg_5_ ( .D(
Exp_Operation_Module_Data_S[5]), .CK(
Exp_Operation_Module_exp_result_net3641775), .RN(n1109), .Q(
exp_oper_result[5]) );
DFFRXLTS Exp_Operation_Module_exp_result_Q_reg_1_ ( .D(
Exp_Operation_Module_Data_S[1]), .CK(
Exp_Operation_Module_exp_result_net3641775), .RN(n1104), .QN(n427) );
DFFRXLTS XRegister_Q_reg_31_ ( .D(Data_X[31]), .CK(YRegister_net3641721),
.RN(n1106), .Q(intDX[31]), .QN(n437) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_30_ ( .D(
Oper_Start_in_module_intM[30]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1106), .Q(DMP[30]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_29_ ( .D(
Oper_Start_in_module_intM[29]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1109), .Q(DMP[29]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_28_ ( .D(
Oper_Start_in_module_intM[28]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1110), .Q(DMP[28]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_27_ ( .D(
Oper_Start_in_module_intM[27]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1106), .Q(DMP[27]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_26_ ( .D(
Oper_Start_in_module_intM[26]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1107), .Q(DMP[26]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_25_ ( .D(
Oper_Start_in_module_intM[25]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1100), .Q(DMP[25]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_24_ ( .D(
Oper_Start_in_module_intM[24]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n421), .Q(DMP[24]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_23_ ( .D(
Oper_Start_in_module_intM[23]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n490), .Q(DMP[23]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_22_ ( .D(
Oper_Start_in_module_intM[22]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n421), .Q(DMP[22]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_21_ ( .D(
Oper_Start_in_module_intM[21]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1108), .Q(DMP[21]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_20_ ( .D(
Oper_Start_in_module_intM[20]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1107), .Q(DMP[20]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_19_ ( .D(
Oper_Start_in_module_intM[19]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1108), .Q(DMP[19]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_18_ ( .D(
Oper_Start_in_module_intM[18]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1110), .Q(DMP[18]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_17_ ( .D(
Oper_Start_in_module_intM[17]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1109), .Q(DMP[17]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_16_ ( .D(
Oper_Start_in_module_intM[16]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1106), .Q(DMP[16]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_15_ ( .D(
Oper_Start_in_module_intM[15]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1107), .Q(DMP[15]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_14_ ( .D(
Oper_Start_in_module_intM[14]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1108), .Q(DMP[14]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_13_ ( .D(
Oper_Start_in_module_intM[13]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n421), .Q(DMP[13]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_12_ ( .D(
Oper_Start_in_module_intM[12]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1110), .Q(DMP[12]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_11_ ( .D(
Oper_Start_in_module_intM[11]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1109), .Q(DMP[11]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_10_ ( .D(
Oper_Start_in_module_intM[10]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1106), .Q(DMP[10]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_9_ ( .D(
Oper_Start_in_module_intM[9]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1107), .Q(DMP[9]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_8_ ( .D(
Oper_Start_in_module_intM[8]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1110), .Q(DMP[8]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_7_ ( .D(
Oper_Start_in_module_intM[7]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1109), .Q(DMP[7]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_6_ ( .D(
Oper_Start_in_module_intM[6]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1106), .Q(DMP[6]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_5_ ( .D(
Oper_Start_in_module_intM[5]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1107), .Q(DMP[5]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_4_ ( .D(
Oper_Start_in_module_intM[4]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1102), .Q(DMP[4]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_3_ ( .D(
Oper_Start_in_module_intM[3]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1105), .Q(DMP[3]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_2_ ( .D(
Oper_Start_in_module_intM[2]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1108), .Q(DMP[2]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_1_ ( .D(
Oper_Start_in_module_intM[1]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1110), .Q(DMP[1]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_0_ ( .D(
Oper_Start_in_module_intM[0]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1109), .Q(DMP[0]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_30_ ( .D(
Oper_Start_in_module_intm[30]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n491), .Q(DmP[30]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_29_ ( .D(
Oper_Start_in_module_intm[29]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1106), .Q(DmP[29]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_28_ ( .D(
Oper_Start_in_module_intm[28]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1102), .Q(DmP[28]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_27_ ( .D(
Oper_Start_in_module_intm[27]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1101), .Q(DmP[27]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_26_ ( .D(
Oper_Start_in_module_intm[26]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n489), .Q(DmP[26]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_25_ ( .D(
Oper_Start_in_module_intm[25]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n422), .Q(DmP[25]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_24_ ( .D(
Oper_Start_in_module_intm[24]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1104), .Q(DmP[24]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_23_ ( .D(
Oper_Start_in_module_intm[23]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n421), .Q(DmP[23]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_22_ ( .D(
Oper_Start_in_module_intm[22]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n422), .Q(DmP[22]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_21_ ( .D(
Oper_Start_in_module_intm[21]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n422), .Q(DmP[21]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_20_ ( .D(
Oper_Start_in_module_intm[20]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n489), .Q(DmP[20]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_19_ ( .D(
Oper_Start_in_module_intm[19]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1102), .Q(DmP[19]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_18_ ( .D(
Oper_Start_in_module_intm[18]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1101), .Q(DmP[18]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_17_ ( .D(
Oper_Start_in_module_intm[17]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1105), .Q(DmP[17]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_16_ ( .D(
Oper_Start_in_module_intm[16]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1100), .Q(DmP[16]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_15_ ( .D(
Oper_Start_in_module_intm[15]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1101), .Q(DmP[15]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_14_ ( .D(
Oper_Start_in_module_intm[14]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1105), .Q(DmP[14]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_13_ ( .D(
Oper_Start_in_module_intm[13]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1101), .Q(DmP[13]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_12_ ( .D(
Oper_Start_in_module_intm[12]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1105), .Q(DmP[12]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_11_ ( .D(
Oper_Start_in_module_intm[11]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1100), .Q(DmP[11]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_10_ ( .D(
Oper_Start_in_module_intm[10]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n421), .Q(DmP[10]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_9_ ( .D(
Oper_Start_in_module_intm[9]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1110), .Q(DmP[9]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_8_ ( .D(
Oper_Start_in_module_intm[8]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1108), .Q(DmP[8]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_7_ ( .D(
Oper_Start_in_module_intm[7]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1104), .Q(DmP[7]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_6_ ( .D(
Oper_Start_in_module_intm[6]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n422), .Q(DmP[6]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_5_ ( .D(
Oper_Start_in_module_intm[5]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n422), .Q(DmP[5]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_4_ ( .D(
Oper_Start_in_module_intm[4]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n489), .Q(DmP[4]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_3_ ( .D(
Oper_Start_in_module_intm[3]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1106), .Q(DmP[3]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_2_ ( .D(
Oper_Start_in_module_intm[2]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n491), .Q(DmP[2]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_1_ ( .D(
Oper_Start_in_module_intm[1]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n490), .Q(DmP[1]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_0_ ( .D(
Oper_Start_in_module_intm[0]), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1101), .Q(DmP[0]) );
DFFRXLTS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_0_ ( .D(
Add_Subt_Sgf_module_S_to_D[0]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3641757), .RN(n1108), .Q(
Add_Subt_result[0]) );
DFFRXLTS Leading_Zero_Detector_Module_Output_Reg_Q_reg_2_ ( .D(
Leading_Zero_Detector_Module_Codec_to_Reg[2]), .CK(
Leading_Zero_Detector_Module_Output_Reg_net3641739), .RN(n422), .Q(
LZA_output[2]) );
DFFRXLTS Leading_Zero_Detector_Module_Output_Reg_Q_reg_1_ ( .D(
Leading_Zero_Detector_Module_Codec_to_Reg[1]), .CK(
Leading_Zero_Detector_Module_Output_Reg_net3641739), .RN(n1102), .Q(
LZA_output[1]) );
DFFRXLTS Leading_Zero_Detector_Module_Output_Reg_Q_reg_0_ ( .D(
Leading_Zero_Detector_Module_Codec_to_Reg[0]), .CK(
Leading_Zero_Detector_Module_Output_Reg_net3641739), .RN(n1102), .Q(
LZA_output[0]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_1_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[1]), .CK(clk), .RN(n491),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[27]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_0_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[0]), .CK(clk), .RN(n490),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[26]) );
DFFRXLTS Exp_Operation_Module_Overflow_Q_reg_0_ ( .D(n1112), .CK(
Exp_Operation_Module_exp_result_net3641775), .RN(n1109), .QN(n424) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(
final_result_ieee_Module_Sign_S_mux), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3641721), .RN(n1102),
.Q(final_result_ieee[31]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(
final_result_ieee_Module_Exp_S_mux[0]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3641721), .RN(n1101),
.Q(final_result_ieee[23]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(
final_result_ieee_Module_Exp_S_mux[1]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3641721), .RN(n1105),
.Q(final_result_ieee[24]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(
final_result_ieee_Module_Exp_S_mux[2]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3641721), .RN(n421), .Q(
final_result_ieee[25]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(
final_result_ieee_Module_Exp_S_mux[3]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3641721), .RN(n421), .Q(
final_result_ieee[26]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(
final_result_ieee_Module_Exp_S_mux[4]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3641721), .RN(n1102),
.Q(final_result_ieee[27]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(
final_result_ieee_Module_Exp_S_mux[5]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3641721), .RN(n1101),
.Q(final_result_ieee[28]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(
final_result_ieee_Module_Exp_S_mux[6]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3641721), .RN(n1105),
.Q(final_result_ieee[29]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(
final_result_ieee_Module_Exp_S_mux[7]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3641721), .RN(n1100),
.Q(final_result_ieee[30]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(
final_result_ieee_Module_Sgf_S_mux[0]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3641721), .RN(n421), .Q(
final_result_ieee[0]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(
final_result_ieee_Module_Sgf_S_mux[1]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3641721), .RN(n1101),
.Q(final_result_ieee[1]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(
final_result_ieee_Module_Sgf_S_mux[2]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3641721), .RN(n1100),
.Q(final_result_ieee[2]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(
final_result_ieee_Module_Sgf_S_mux[3]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3641721), .RN(n1105),
.Q(final_result_ieee[3]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(
final_result_ieee_Module_Sgf_S_mux[4]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3641721), .RN(n421), .Q(
final_result_ieee[4]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(
final_result_ieee_Module_Sgf_S_mux[5]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3641721), .RN(n1102),
.Q(final_result_ieee[5]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(
final_result_ieee_Module_Sgf_S_mux[6]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3641721), .RN(n1104),
.Q(final_result_ieee[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(
final_result_ieee_Module_Sgf_S_mux[7]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3641721), .RN(n422), .Q(
final_result_ieee[7]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(
final_result_ieee_Module_Sgf_S_mux[8]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3641721), .RN(n422), .Q(
final_result_ieee[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(
final_result_ieee_Module_Sgf_S_mux[9]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3641721), .RN(n489), .Q(
final_result_ieee[9]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(
final_result_ieee_Module_Sgf_S_mux[10]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3641721), .RN(n1106),
.Q(final_result_ieee[10]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(
final_result_ieee_Module_Sgf_S_mux[11]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3641721), .RN(n491), .Q(
final_result_ieee[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(
final_result_ieee_Module_Sgf_S_mux[12]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3641721), .RN(n490), .Q(
final_result_ieee[12]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(
final_result_ieee_Module_Sgf_S_mux[13]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3641721), .RN(n1101),
.Q(final_result_ieee[13]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(
final_result_ieee_Module_Sgf_S_mux[14]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3641721), .RN(n1102),
.Q(final_result_ieee[14]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(
final_result_ieee_Module_Sgf_S_mux[15]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3641721), .RN(n1104),
.Q(final_result_ieee[15]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(
final_result_ieee_Module_Sgf_S_mux[16]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3641721), .RN(n422), .Q(
final_result_ieee[16]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(
final_result_ieee_Module_Sgf_S_mux[17]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3641721), .RN(n1102),
.Q(final_result_ieee[17]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(
final_result_ieee_Module_Sgf_S_mux[18]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3641721), .RN(n1101),
.Q(final_result_ieee[18]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(
final_result_ieee_Module_Sgf_S_mux[19]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3641721), .RN(n1105),
.Q(final_result_ieee[19]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(
final_result_ieee_Module_Sgf_S_mux[20]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3641721), .RN(n1100),
.Q(final_result_ieee[20]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(
final_result_ieee_Module_Sgf_S_mux[21]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3641721), .RN(n490), .Q(
final_result_ieee[21]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(
final_result_ieee_Module_Sgf_S_mux[22]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3641721), .RN(n1100),
.Q(final_result_ieee[22]) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_25_ ( .D(n1114), .CK(
Barrel_Shifter_module_Output_Reg_net3641757), .RN(n1107), .Q(
Sgf_normalized_result[25]) );
DFFRXLTS Oper_Start_in_module_SignRegister_Q_reg_0_ ( .D(n1113), .CK(
Oper_Start_in_module_MRegister_net3641793), .RN(n1101), .Q(
sign_final_result), .QN(n439) );
CMPR32X2TS DP_OP_42J178_122_8048_U6 ( .A(DP_OP_42J178_122_8048_n17), .B(
S_Oper_A_exp[3]), .C(DP_OP_42J178_122_8048_n6), .CO(
DP_OP_42J178_122_8048_n5), .S(Exp_Operation_Module_Data_S[3]) );
CMPR32X2TS DP_OP_42J178_122_8048_U5 ( .A(DP_OP_42J178_122_8048_n16), .B(
S_Oper_A_exp[4]), .C(DP_OP_42J178_122_8048_n5), .CO(
DP_OP_42J178_122_8048_n4), .S(Exp_Operation_Module_Data_S[4]) );
CMPR32X2TS DP_OP_42J178_122_8048_U4 ( .A(DP_OP_42J178_122_8048_n15), .B(
S_Oper_A_exp[5]), .C(DP_OP_42J178_122_8048_n4), .CO(
DP_OP_42J178_122_8048_n3), .S(Exp_Operation_Module_Data_S[5]) );
CMPR32X2TS DP_OP_42J178_122_8048_U3 ( .A(DP_OP_42J178_122_8048_n14), .B(
S_Oper_A_exp[6]), .C(DP_OP_42J178_122_8048_n3), .CO(
DP_OP_42J178_122_8048_n2), .S(Exp_Operation_Module_Data_S[6]) );
CMPR32X2TS DP_OP_45J178_125_5354_U25 ( .A(DP_OP_45J178_125_5354_n54), .B(
S_A_S_Oper_A[2]), .C(DP_OP_45J178_125_5354_n25), .CO(
DP_OP_45J178_125_5354_n24), .S(Add_Subt_Sgf_module_S_to_D[2]) );
CMPR32X2TS DP_OP_45J178_125_5354_U22 ( .A(DP_OP_45J178_125_5354_n51), .B(
S_A_S_Oper_A[5]), .C(DP_OP_45J178_125_5354_n22), .CO(
DP_OP_45J178_125_5354_n21), .S(Add_Subt_Sgf_module_S_to_D[5]) );
CMPR32X2TS DP_OP_45J178_125_5354_U21 ( .A(DP_OP_45J178_125_5354_n50), .B(
S_A_S_Oper_A[6]), .C(DP_OP_45J178_125_5354_n21), .CO(
DP_OP_45J178_125_5354_n20), .S(Add_Subt_Sgf_module_S_to_D[6]) );
CMPR32X2TS DP_OP_45J178_125_5354_U20 ( .A(DP_OP_45J178_125_5354_n49), .B(
S_A_S_Oper_A[7]), .C(DP_OP_45J178_125_5354_n20), .CO(
DP_OP_45J178_125_5354_n19), .S(Add_Subt_Sgf_module_S_to_D[7]) );
CMPR32X2TS DP_OP_45J178_125_5354_U19 ( .A(DP_OP_45J178_125_5354_n48), .B(
S_A_S_Oper_A[8]), .C(DP_OP_45J178_125_5354_n19), .CO(
DP_OP_45J178_125_5354_n18), .S(Add_Subt_Sgf_module_S_to_D[8]) );
CMPR32X2TS DP_OP_45J178_125_5354_U18 ( .A(DP_OP_45J178_125_5354_n47), .B(
S_A_S_Oper_A[9]), .C(DP_OP_45J178_125_5354_n18), .CO(
DP_OP_45J178_125_5354_n17), .S(Add_Subt_Sgf_module_S_to_D[9]) );
CMPR32X2TS DP_OP_45J178_125_5354_U17 ( .A(DP_OP_45J178_125_5354_n46), .B(
S_A_S_Oper_A[10]), .C(DP_OP_45J178_125_5354_n17), .CO(
DP_OP_45J178_125_5354_n16), .S(Add_Subt_Sgf_module_S_to_D[10]) );
CMPR32X2TS DP_OP_45J178_125_5354_U16 ( .A(DP_OP_45J178_125_5354_n45), .B(
S_A_S_Oper_A[11]), .C(DP_OP_45J178_125_5354_n16), .CO(
DP_OP_45J178_125_5354_n15), .S(Add_Subt_Sgf_module_S_to_D[11]) );
CMPR32X2TS DP_OP_45J178_125_5354_U15 ( .A(DP_OP_45J178_125_5354_n44), .B(
S_A_S_Oper_A[12]), .C(DP_OP_45J178_125_5354_n15), .CO(
DP_OP_45J178_125_5354_n14), .S(Add_Subt_Sgf_module_S_to_D[12]) );
CMPR32X2TS DP_OP_45J178_125_5354_U14 ( .A(DP_OP_45J178_125_5354_n43), .B(
S_A_S_Oper_A[13]), .C(DP_OP_45J178_125_5354_n14), .CO(
DP_OP_45J178_125_5354_n13), .S(Add_Subt_Sgf_module_S_to_D[13]) );
CMPR32X2TS DP_OP_45J178_125_5354_U13 ( .A(DP_OP_45J178_125_5354_n42), .B(
S_A_S_Oper_A[14]), .C(DP_OP_45J178_125_5354_n13), .CO(
DP_OP_45J178_125_5354_n12), .S(Add_Subt_Sgf_module_S_to_D[14]) );
CMPR32X2TS DP_OP_45J178_125_5354_U11 ( .A(DP_OP_45J178_125_5354_n40), .B(
S_A_S_Oper_A[16]), .C(DP_OP_45J178_125_5354_n11), .CO(
DP_OP_45J178_125_5354_n10), .S(Add_Subt_Sgf_module_S_to_D[16]) );
CMPR32X2TS DP_OP_45J178_125_5354_U10 ( .A(DP_OP_45J178_125_5354_n39), .B(
S_A_S_Oper_A[17]), .C(DP_OP_45J178_125_5354_n10), .CO(
DP_OP_45J178_125_5354_n9), .S(Add_Subt_Sgf_module_S_to_D[17]) );
CMPR32X2TS DP_OP_45J178_125_5354_U9 ( .A(DP_OP_45J178_125_5354_n38), .B(
S_A_S_Oper_A[18]), .C(DP_OP_45J178_125_5354_n9), .CO(
DP_OP_45J178_125_5354_n8), .S(Add_Subt_Sgf_module_S_to_D[18]) );
CMPR32X2TS DP_OP_45J178_125_5354_U8 ( .A(DP_OP_45J178_125_5354_n37), .B(
S_A_S_Oper_A[19]), .C(DP_OP_45J178_125_5354_n8), .CO(
DP_OP_45J178_125_5354_n7), .S(Add_Subt_Sgf_module_S_to_D[19]) );
CMPR32X2TS DP_OP_45J178_125_5354_U6 ( .A(DP_OP_45J178_125_5354_n35), .B(
S_A_S_Oper_A[21]), .C(DP_OP_45J178_125_5354_n6), .CO(
DP_OP_45J178_125_5354_n5), .S(Add_Subt_Sgf_module_S_to_D[21]) );
CMPR32X2TS DP_OP_45J178_125_5354_U5 ( .A(DP_OP_45J178_125_5354_n34), .B(
S_A_S_Oper_A[22]), .C(DP_OP_45J178_125_5354_n5), .CO(
DP_OP_45J178_125_5354_n4), .S(Add_Subt_Sgf_module_S_to_D[22]) );
CMPR32X2TS DP_OP_45J178_125_5354_U4 ( .A(DP_OP_45J178_125_5354_n33), .B(
S_A_S_Oper_A[23]), .C(DP_OP_45J178_125_5354_n4), .CO(
DP_OP_45J178_125_5354_n3), .S(Add_Subt_Sgf_module_S_to_D[23]) );
CMPR32X2TS DP_OP_45J178_125_5354_U3 ( .A(DP_OP_45J178_125_5354_n32), .B(
S_A_S_Oper_A[24]), .C(DP_OP_45J178_125_5354_n3), .CO(
DP_OP_45J178_125_5354_n2), .S(Add_Subt_Sgf_module_S_to_D[24]) );
CMPR32X2TS DP_OP_45J178_125_5354_U2 ( .A(DP_OP_45J178_125_5354_n31), .B(
S_A_S_Oper_A[25]), .C(DP_OP_45J178_125_5354_n2), .CO(
DP_OP_45J178_125_5354_n1), .S(Add_Subt_Sgf_module_S_to_D[25]) );
DFFSX2TS R_0 ( .D(n1095), .CK(YRegister_net3641721), .SN(n491), .Q(n1111) );
DFFRX2TS YRegister_Q_reg_23_ ( .D(Data_Y[23]), .CK(YRegister_net3641721),
.RN(n1101), .Q(intDY[23]), .QN(n1091) );
DFFRX2TS YRegister_Q_reg_15_ ( .D(Data_Y[15]), .CK(YRegister_net3641721),
.RN(n1102), .Q(intDY[15]), .QN(n1090) );
DFFRX2TS YRegister_Q_reg_3_ ( .D(Data_Y[3]), .CK(YRegister_net3641721), .RN(
n1104), .Q(intDY[3]), .QN(n1088) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_19_ ( .D(
Add_Subt_Sgf_module_S_to_D[19]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3641757), .RN(n1106), .Q(
Add_Subt_result[19]), .QN(n1077) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_16_ ( .D(
Add_Subt_Sgf_module_S_to_D[16]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3641757), .RN(n1106), .Q(
Add_Subt_result[16]), .QN(n1076) );
DFFRX2TS YRegister_Q_reg_5_ ( .D(Data_Y[5]), .CK(YRegister_net3641721), .RN(
n1107), .Q(intDY[5]), .QN(n1062) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_10_ ( .D(
Add_Subt_Sgf_module_S_to_D[10]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3641757), .RN(n1110), .Q(
Add_Subt_result[10]), .QN(n1060) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_18_ ( .D(
Add_Subt_Sgf_module_S_to_D[18]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3641757), .RN(n421), .Q(
Add_Subt_result[18]), .QN(n1059) );
DFFRX2TS XRegister_Q_reg_16_ ( .D(Data_X[16]), .CK(YRegister_net3641721),
.RN(n1101), .Q(intDX[16]), .QN(n1053) );
DFFRX1TS Sel_D_Q_reg_0_ ( .D(n406), .CK(FS_Module_net3641811), .RN(n400),
.Q(FSM_selector_D) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_25_ ( .D(
Add_Subt_Sgf_module_S_to_D[25]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3641757), .RN(n1109), .Q(
Add_Subt_result[25]), .QN(n1052) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_25_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[25]), .CK(clk), .RN(n1101),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[51]), .QN(n1049) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_24_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[24]), .CK(clk), .RN(n490),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[50]), .QN(n1048) );
DFFRX2TS XRegister_Q_reg_5_ ( .D(Data_X[5]), .CK(YRegister_net3641721), .RN(
n422), .QN(n1046) );
DFFRX2TS Exp_Operation_Module_exp_result_Q_reg_4_ ( .D(
Exp_Operation_Module_Data_S[4]), .CK(
Exp_Operation_Module_exp_result_net3641775), .RN(n1106), .Q(
exp_oper_result[4]), .QN(n1044) );
DFFRX1TS XRegister_Q_reg_1_ ( .D(Data_X[1]), .CK(YRegister_net3641721), .RN(
n1101), .Q(intDX[1]), .QN(n1032) );
DFFRX2TS Exp_Operation_Module_exp_result_Q_reg_3_ ( .D(
Exp_Operation_Module_Data_S[3]), .CK(
Exp_Operation_Module_exp_result_net3641775), .RN(n1100), .Q(
exp_oper_result[3]), .QN(n1031) );
DFFRX2TS Sel_B_Q_reg_0_ ( .D(n405), .CK(FS_Module_net3641811), .RN(n400),
.Q(FSM_selector_B[0]), .QN(n1029) );
DFFRX2TS FS_Module_state_reg_reg_3_ ( .D(FS_Module_state_next[3]), .CK(
FS_Module_net3641811), .RN(n1102), .Q(FS_Module_state_reg[3]), .QN(
n1028) );
DFFRX2TS FS_Module_state_reg_reg_2_ ( .D(FS_Module_state_next[2]), .CK(
FS_Module_net3641811), .RN(n1105), .Q(FS_Module_state_reg[2]), .QN(
n1027) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_16_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[16]), .CK(clk), .RN(n421),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[42]), .QN(n1021) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_17_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[17]), .CK(clk), .RN(n1106),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[43]), .QN(n1020) );
DFFRX2TS YRegister_Q_reg_30_ ( .D(Data_Y[30]), .CK(YRegister_net3641721),
.RN(n1101), .Q(intDY[30]), .QN(n1018) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_17_ ( .D(
Add_Subt_Sgf_module_S_to_D[17]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3641757), .RN(n1109), .Q(
Add_Subt_result[17]), .QN(n1017) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_12_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[12]), .CK(clk), .RN(n1101),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[38]), .QN(n1016) );
DFFRX1TS XRegister_Q_reg_0_ ( .D(Data_X[0]), .CK(YRegister_net3641721), .RN(
n490), .Q(intDX[0]), .QN(n1015) );
DFFRX2TS XRegister_Q_reg_4_ ( .D(Data_X[4]), .CK(YRegister_net3641721), .RN(
n489), .Q(intDX[4]), .QN(n1014) );
DFFRX1TS XRegister_Q_reg_2_ ( .D(Data_X[2]), .CK(YRegister_net3641721), .RN(
n1102), .Q(intDX[2]), .QN(n1012) );
DFFRX2TS Sel_C_Q_reg_0_ ( .D(n407), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3641757), .RN(n400), .Q(
FSM_selector_C), .QN(n1045) );
DFFRX2TS Add_Subt_Sgf_module_Add_overflow_Result_Q_reg_0_ ( .D(
Add_Subt_Sgf_module_S_to_D[26]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3641757), .RN(n1109), .Q(
add_overflow_flag), .QN(n1003) );
DFFRX2TS Leading_Zero_Detector_Module_Output_Reg_Q_reg_3_ ( .D(
Leading_Zero_Detector_Module_Codec_to_Reg[3]), .CK(
Leading_Zero_Detector_Module_Output_Reg_net3641739), .RN(n1107), .Q(
LZA_output[3]), .QN(n1001) );
DFFRX2TS FS_Module_state_reg_reg_1_ ( .D(FS_Module_state_next[1]), .CK(
FS_Module_net3641811), .RN(n421), .Q(FS_Module_state_reg[1]), .QN(
n1000) );
CMPR32X2TS DP_OP_42J178_122_8048_U9 ( .A(S_Oper_A_exp[0]), .B(n1096), .C(
DP_OP_42J178_122_8048_n20), .CO(DP_OP_42J178_122_8048_n8), .S(
Exp_Operation_Module_Data_S[0]) );
CMPR32X2TS DP_OP_42J178_122_8048_U8 ( .A(DP_OP_42J178_122_8048_n19), .B(
S_Oper_A_exp[1]), .C(DP_OP_42J178_122_8048_n8), .CO(
DP_OP_42J178_122_8048_n7), .S(Exp_Operation_Module_Data_S[1]) );
CMPR32X2TS DP_OP_42J178_122_8048_U2 ( .A(DP_OP_42J178_122_8048_n13), .B(
S_Oper_A_exp[7]), .C(DP_OP_42J178_122_8048_n2), .CO(
DP_OP_42J178_122_8048_n1), .S(Exp_Operation_Module_Data_S[7]) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_2_ ( .D(
Add_Subt_Sgf_module_S_to_D[2]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3641757), .RN(n421), .Q(
Add_Subt_result[2]), .QN(n1075) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_5_ ( .D(
Add_Subt_Sgf_module_S_to_D[5]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3641757), .RN(n1106), .Q(
Add_Subt_result[5]), .QN(n1023) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_7_ ( .D(
Add_Subt_Sgf_module_S_to_D[7]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3641757), .RN(n1109), .Q(
Add_Subt_result[7]), .QN(n1094) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_23_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[23]), .CK(clk), .RN(n1104),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[49]), .QN(n1055) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_22_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[22]), .CK(clk), .RN(n422),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[48]), .QN(n1057) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_8_ ( .D(
Add_Subt_Sgf_module_S_to_D[8]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3641757), .RN(n1110), .Q(
Add_Subt_result[8]), .QN(n1002) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_9_ ( .D(
Add_Subt_Sgf_module_S_to_D[9]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3641757), .RN(n1107), .Q(
Add_Subt_result[9]), .QN(n1078) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_21_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[21]), .CK(clk), .RN(n1104),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[47]), .QN(n1054) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_18_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[18]), .CK(clk), .RN(n421),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[44]), .QN(n1058) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_19_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[19]), .CK(clk), .RN(n1102),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[45]), .QN(n1056) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_20_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[20]), .CK(clk), .RN(n1101),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[46]), .QN(n1051) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_12_ ( .D(
Add_Subt_Sgf_module_S_to_D[12]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3641757), .RN(n421), .Q(
Add_Subt_result[12]), .QN(n1022) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_13_ ( .D(
Add_Subt_Sgf_module_S_to_D[13]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3641757), .RN(n1107), .Q(
Add_Subt_result[13]), .QN(n1061) );
DFFRX1TS YRegister_Q_reg_29_ ( .D(Data_Y[29]), .CK(YRegister_net3641721),
.RN(n421), .Q(intDY[29]), .QN(n1083) );
DFFRX1TS YRegister_Q_reg_28_ ( .D(Data_Y[28]), .CK(YRegister_net3641721),
.RN(n1102), .Q(intDY[28]), .QN(n1063) );
DFFRX1TS YRegister_Q_reg_27_ ( .D(Data_Y[27]), .CK(YRegister_net3641721),
.RN(n1105), .Q(intDY[27]), .QN(n1074) );
DFFRX1TS YRegister_Q_reg_26_ ( .D(Data_Y[26]), .CK(YRegister_net3641721),
.RN(n1100), .Q(intDY[26]), .QN(n1089) );
DFFRX1TS YRegister_Q_reg_25_ ( .D(Data_Y[25]), .CK(YRegister_net3641721),
.RN(n422), .Q(intDY[25]), .QN(n1086) );
DFFRX1TS YRegister_Q_reg_24_ ( .D(Data_Y[24]), .CK(YRegister_net3641721),
.RN(n422), .Q(intDY[24]), .QN(n1067) );
DFFRX1TS YRegister_Q_reg_22_ ( .D(Data_Y[22]), .CK(YRegister_net3641721),
.RN(n1104), .Q(intDY[22]), .QN(n1026) );
DFFRX1TS YRegister_Q_reg_21_ ( .D(Data_Y[21]), .CK(YRegister_net3641721),
.RN(n422), .Q(intDY[21]), .QN(n1069) );
DFFRX1TS YRegister_Q_reg_20_ ( .D(Data_Y[20]), .CK(YRegister_net3641721),
.RN(n489), .Q(intDY[20]), .QN(n1071) );
DFFRX1TS YRegister_Q_reg_19_ ( .D(Data_Y[19]), .CK(YRegister_net3641721),
.RN(n1106), .Q(intDY[19]), .QN(n1024) );
DFFRX1TS YRegister_Q_reg_18_ ( .D(Data_Y[18]), .CK(YRegister_net3641721),
.RN(n491), .Q(intDY[18]), .QN(n1082) );
DFFRX1TS YRegister_Q_reg_17_ ( .D(Data_Y[17]), .CK(YRegister_net3641721),
.RN(n490), .Q(intDY[17]), .QN(n1085) );
DFFRX1TS YRegister_Q_reg_16_ ( .D(Data_Y[16]), .CK(YRegister_net3641721),
.RN(n1102), .Q(intDY[16]), .QN(n1064) );
DFFRX1TS YRegister_Q_reg_14_ ( .D(Data_Y[14]), .CK(YRegister_net3641721),
.RN(n1101), .Q(intDY[14]), .QN(n1025) );
DFFRX1TS YRegister_Q_reg_13_ ( .D(Data_Y[13]), .CK(YRegister_net3641721),
.RN(n422), .Q(intDY[13]), .QN(n1068) );
DFFRX1TS YRegister_Q_reg_11_ ( .D(Data_Y[11]), .CK(YRegister_net3641721),
.RN(n1100), .Q(intDY[11]), .QN(n1081) );
DFFRX1TS YRegister_Q_reg_10_ ( .D(Data_Y[10]), .CK(YRegister_net3641721),
.RN(n1102), .Q(intDY[10]), .QN(n1080) );
DFFRX1TS YRegister_Q_reg_9_ ( .D(Data_Y[9]), .CK(YRegister_net3641721), .RN(
n1101), .Q(intDY[9]), .QN(n1073) );
DFFRX1TS YRegister_Q_reg_8_ ( .D(Data_Y[8]), .CK(YRegister_net3641721), .RN(
n1102), .Q(intDY[8]), .QN(n1084) );
DFFRX1TS YRegister_Q_reg_7_ ( .D(Data_Y[7]), .CK(YRegister_net3641721), .RN(
n1105), .Q(intDY[7]), .QN(n1072) );
DFFRX1TS YRegister_Q_reg_6_ ( .D(Data_Y[6]), .CK(YRegister_net3641721), .RN(
n1100), .Q(intDY[6]), .QN(n1079) );
DFFRX1TS YRegister_Q_reg_4_ ( .D(Data_Y[4]), .CK(YRegister_net3641721), .RN(
n1100), .Q(intDY[4]), .QN(n1066) );
DFFRX1TS YRegister_Q_reg_2_ ( .D(Data_Y[2]), .CK(YRegister_net3641721), .RN(
n422), .Q(intDY[2]), .QN(n1070) );
DFFRX1TS YRegister_Q_reg_1_ ( .D(Data_Y[1]), .CK(YRegister_net3641721), .RN(
n1102), .Q(intDY[1]), .QN(n1087) );
DFFRX1TS YRegister_Q_reg_0_ ( .D(Data_Y[0]), .CK(YRegister_net3641721), .RN(
n1104), .Q(intDY[0]), .QN(n1092) );
DFFRX1TS XRegister_Q_reg_30_ ( .D(Data_X[30]), .CK(YRegister_net3641721),
.RN(n422), .Q(intDX[30]), .QN(n1047) );
DFFRX1TS XRegister_Q_reg_29_ ( .D(Data_X[29]), .CK(YRegister_net3641721),
.RN(n422), .Q(intDX[29]), .QN(n1033) );
DFFRX1TS XRegister_Q_reg_27_ ( .D(Data_X[27]), .CK(YRegister_net3641721),
.RN(n489), .Q(intDX[27]), .QN(n1013) );
DFFRX1TS XRegister_Q_reg_26_ ( .D(Data_X[26]), .CK(YRegister_net3641721),
.RN(n1106), .Q(intDX[26]), .QN(n1010) );
DFFRX1TS XRegister_Q_reg_25_ ( .D(Data_X[25]), .CK(YRegister_net3641721),
.RN(n491), .Q(intDX[25]), .QN(n1039) );
DFFRX1TS XRegister_Q_reg_24_ ( .D(Data_X[24]), .CK(YRegister_net3641721),
.RN(n490), .Q(intDX[24]), .QN(n1009) );
DFFRX1TS XRegister_Q_reg_23_ ( .D(Data_X[23]), .CK(YRegister_net3641721),
.RN(n1101), .Q(intDX[23]), .QN(n1043) );
DFFRX1TS XRegister_Q_reg_22_ ( .D(Data_X[22]), .CK(YRegister_net3641721),
.RN(n1102), .Q(intDX[22]), .QN(n1008) );
DFFRX1TS XRegister_Q_reg_21_ ( .D(Data_X[21]), .CK(YRegister_net3641721),
.RN(n1104), .Q(intDX[21]), .QN(n1042) );
DFFRX1TS XRegister_Q_reg_20_ ( .D(Data_X[20]), .CK(YRegister_net3641721),
.RN(n1101), .Q(intDX[20]), .QN(n1007) );
DFFRX1TS XRegister_Q_reg_19_ ( .D(Data_X[19]), .CK(YRegister_net3641721),
.RN(n1105), .Q(intDX[19]), .QN(n1038) );
DFFRX1TS XRegister_Q_reg_18_ ( .D(Data_X[18]), .CK(YRegister_net3641721),
.RN(n1100), .Q(intDX[18]), .QN(n1006) );
DFFRX1TS XRegister_Q_reg_17_ ( .D(Data_X[17]), .CK(YRegister_net3641721),
.RN(n422), .Q(intDX[17]), .QN(n1037) );
DFFRX1TS XRegister_Q_reg_15_ ( .D(Data_X[15]), .CK(YRegister_net3641721),
.RN(n1105), .Q(intDX[15]), .QN(n1041) );
DFFRX1TS XRegister_Q_reg_14_ ( .D(Data_X[14]), .CK(YRegister_net3641721),
.RN(n422), .Q(intDX[14]), .QN(n1005) );
DFFRX1TS XRegister_Q_reg_13_ ( .D(Data_X[13]), .CK(YRegister_net3641721),
.RN(n1101), .Q(intDX[13]), .QN(n1040) );
DFFRX1TS XRegister_Q_reg_12_ ( .D(Data_X[12]), .CK(YRegister_net3641721),
.RN(n421), .Q(intDX[12]), .QN(n1065) );
DFFRX1TS XRegister_Q_reg_11_ ( .D(Data_X[11]), .CK(YRegister_net3641721),
.RN(n421), .Q(intDX[11]), .QN(n1030) );
DFFRX1TS XRegister_Q_reg_10_ ( .D(Data_X[10]), .CK(YRegister_net3641721),
.RN(n1102), .Q(intDX[10]), .QN(n1011) );
DFFRX1TS XRegister_Q_reg_9_ ( .D(Data_X[9]), .CK(YRegister_net3641721), .RN(
n1105), .Q(intDX[9]), .QN(n1004) );
DFFRX1TS XRegister_Q_reg_8_ ( .D(Data_X[8]), .CK(YRegister_net3641721), .RN(
n489), .Q(intDX[8]), .QN(n1035) );
DFFRX1TS XRegister_Q_reg_6_ ( .D(Data_X[6]), .CK(YRegister_net3641721), .RN(
n1106), .Q(intDX[6]), .QN(n1019) );
DFFRX1TS XRegister_Q_reg_3_ ( .D(Data_X[3]), .CK(YRegister_net3641721), .RN(
n491), .Q(intDX[3]), .QN(n1034) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_13_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[13]), .CK(clk), .RN(n1108),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[39]) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_10_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[10]), .CK(clk), .RN(n421),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[36]) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_11_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[11]), .CK(clk), .RN(n1105),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[37]) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_14_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[14]), .CK(clk), .RN(n1100),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[40]) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_15_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[15]), .CK(clk), .RN(n421),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[41]) );
DFFRX2TS XRegister_Q_reg_7_ ( .D(Data_X[7]), .CK(YRegister_net3641721), .RN(
n1106), .QN(n1099) );
DFFRX2TS Leading_Zero_Detector_Module_Output_Reg_Q_reg_4_ ( .D(
Leading_Zero_Detector_Module_Codec_to_Reg[4]), .CK(
Leading_Zero_Detector_Module_Output_Reg_net3641739), .RN(n1100), .Q(
LZA_output[4]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_20_ ( .D(
Add_Subt_Sgf_module_S_to_D[20]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3641757), .RN(n1105), .Q(
Add_Subt_result[20]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_14_ ( .D(
Add_Subt_Sgf_module_S_to_D[14]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3641757), .RN(n1108), .Q(
Add_Subt_result[14]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_3_ ( .D(
Add_Subt_Sgf_module_S_to_D[3]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3641757), .RN(n1110), .Q(
Add_Subt_result[3]) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_6_ ( .D(
Add_Subt_Sgf_module_S_to_D[6]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3641757), .RN(n1108), .Q(
Add_Subt_result[6]) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_1_ ( .D(
Add_Subt_Sgf_module_S_to_D[1]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3641757), .RN(n1110), .Q(
Add_Subt_result[1]) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_4_ ( .D(
Add_Subt_Sgf_module_S_to_D[4]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3641757), .RN(n1108), .Q(
Add_Subt_result[4]) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_23_ ( .D(
Add_Subt_Sgf_module_S_to_D[23]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3641757), .RN(n1108), .Q(
Add_Subt_result[23]) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_11_ ( .D(
Add_Subt_Sgf_module_S_to_D[11]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3641757), .RN(n1107), .Q(
Add_Subt_result[11]) );
DFFRX2TS XRegister_Q_reg_28_ ( .D(Data_X[28]), .CK(YRegister_net3641721),
.RN(n491), .QN(n1098) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_9_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[9]), .CK(clk), .RN(n1102),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[35]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_5_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[5]), .CK(clk), .RN(n422),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[31]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_3_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[3]), .CK(clk), .RN(n489),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[29]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_7_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[7]), .CK(clk), .RN(n1106),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[33]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_4_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[4]), .CK(clk), .RN(n491),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[30]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_2_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[2]), .CK(clk), .RN(n490),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[28]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_6_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[6]), .CK(clk), .RN(n1102),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[32]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_8_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[8]), .CK(clk), .RN(n1101),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[34]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n1121), .CK(
Barrel_Shifter_module_Output_Reg_net3641757), .RN(n1109), .Q(
Sgf_normalized_result[23]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n1125), .CK(
Barrel_Shifter_module_Output_Reg_net3641757), .RN(n1108), .Q(
Sgf_normalized_result[22]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n1139), .CK(
Barrel_Shifter_module_Output_Reg_net3641757), .RN(n1106), .Q(
Sgf_normalized_result[0]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n1118), .CK(
Barrel_Shifter_module_Output_Reg_net3641757), .RN(n1109), .Q(
Sgf_normalized_result[1]) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_22_ ( .D(
Add_Subt_Sgf_module_S_to_D[22]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3641757), .RN(n1110), .Q(
Add_Subt_result[22]) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_24_ ( .D(
Add_Subt_Sgf_module_S_to_D[24]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3641757), .RN(n1106), .Q(
Add_Subt_result[24]) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_15_ ( .D(
Add_Subt_Sgf_module_S_to_D[15]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3641757), .RN(n1109), .Q(
Add_Subt_result[15]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_2_ ( .D(
Exp_Operation_Module_Data_S[2]), .CK(
Exp_Operation_Module_exp_result_net3641775), .RN(n1110), .Q(
exp_oper_result[2]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n1122), .CK(
Barrel_Shifter_module_Output_Reg_net3641757), .RN(n1110), .Q(
Sgf_normalized_result[2]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n1138), .CK(
Barrel_Shifter_module_Output_Reg_net3641757), .RN(n1109), .Q(
Sgf_normalized_result[12]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n1137), .CK(
Barrel_Shifter_module_Output_Reg_net3641757), .RN(n1110), .Q(
Sgf_normalized_result[13]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n1136), .CK(
Barrel_Shifter_module_Output_Reg_net3641757), .RN(n1108), .Q(
Sgf_normalized_result[11]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n1135), .CK(
Barrel_Shifter_module_Output_Reg_net3641757), .RN(n421), .Q(
Sgf_normalized_result[14]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n1134), .CK(
Barrel_Shifter_module_Output_Reg_net3641757), .RN(n1106), .Q(
Sgf_normalized_result[10]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n1133), .CK(
Barrel_Shifter_module_Output_Reg_net3641757), .RN(n1107), .Q(
Sgf_normalized_result[15]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n1132), .CK(
Barrel_Shifter_module_Output_Reg_net3641757), .RN(n1109), .Q(
Sgf_normalized_result[9]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n1131), .CK(
Barrel_Shifter_module_Output_Reg_net3641757), .RN(n1102), .Q(
Sgf_normalized_result[16]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n1130), .CK(
Barrel_Shifter_module_Output_Reg_net3641757), .RN(n1110), .Q(
Sgf_normalized_result[8]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n1129), .CK(
Barrel_Shifter_module_Output_Reg_net3641757), .RN(n422), .Q(
Sgf_normalized_result[17]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n1128), .CK(
Barrel_Shifter_module_Output_Reg_net3641757), .RN(n1108), .Q(
Sgf_normalized_result[7]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n1127), .CK(
Barrel_Shifter_module_Output_Reg_net3641757), .RN(n421), .Q(
Sgf_normalized_result[18]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n1126), .CK(
Barrel_Shifter_module_Output_Reg_net3641757), .RN(n1108), .Q(
Sgf_normalized_result[3]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n1124), .CK(
Barrel_Shifter_module_Output_Reg_net3641757), .RN(n1107), .Q(
Sgf_normalized_result[6]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n1123), .CK(
Barrel_Shifter_module_Output_Reg_net3641757), .RN(n1107), .Q(
Sgf_normalized_result[19]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n1120), .CK(
Barrel_Shifter_module_Output_Reg_net3641757), .RN(n1106), .Q(
Sgf_normalized_result[5]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n1119), .CK(
Barrel_Shifter_module_Output_Reg_net3641757), .RN(n1107), .Q(
Sgf_normalized_result[20]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_24_ ( .D(n1117), .CK(
Barrel_Shifter_module_Output_Reg_net3641757), .RN(n1110), .Q(
Sgf_normalized_result[24]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n1116), .CK(
Barrel_Shifter_module_Output_Reg_net3641757), .RN(n422), .Q(
Sgf_normalized_result[4]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n1115), .CK(
Barrel_Shifter_module_Output_Reg_net3641757), .RN(n1106), .Q(
Sgf_normalized_result[21]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_0_ ( .D(
Exp_Operation_Module_Data_S[0]), .CK(
Exp_Operation_Module_exp_result_net3641775), .RN(n422), .Q(
exp_oper_result[0]) );
DFFRX2TS YRegister_Q_reg_12_ ( .D(Data_Y[12]), .CK(YRegister_net3641721),
.RN(n1102), .Q(intDY[12]), .QN(n1036) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_21_ ( .D(
Add_Subt_Sgf_module_S_to_D[21]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3641757), .RN(n1107), .Q(
Add_Subt_result[21]), .QN(n1050) );
DFFRXLTS Exp_Operation_Module_Underflow_Q_reg_0_ ( .D(n401), .CK(
Exp_Operation_Module_exp_result_net3641775), .RN(n422), .Q(
underflow_flag), .QN(n1093) );
ADDFX1TS DP_OP_45J178_125_5354_U27 ( .A(S_A_S_Oper_A[0]), .B(n1097), .CI(
DP_OP_45J178_125_5354_n56), .CO(DP_OP_45J178_125_5354_n26), .S(
Add_Subt_Sgf_module_S_to_D[0]) );
ADDFX1TS DP_OP_45J178_125_5354_U26 ( .A(DP_OP_45J178_125_5354_n55), .B(
S_A_S_Oper_A[1]), .CI(DP_OP_45J178_125_5354_n26), .CO(
DP_OP_45J178_125_5354_n25), .S(Add_Subt_Sgf_module_S_to_D[1]) );
ADDFX1TS DP_OP_45J178_125_5354_U24 ( .A(DP_OP_45J178_125_5354_n53), .B(
S_A_S_Oper_A[3]), .CI(DP_OP_45J178_125_5354_n24), .CO(
DP_OP_45J178_125_5354_n23), .S(Add_Subt_Sgf_module_S_to_D[3]) );
ADDFX1TS DP_OP_45J178_125_5354_U23 ( .A(DP_OP_45J178_125_5354_n52), .B(
S_A_S_Oper_A[4]), .CI(DP_OP_45J178_125_5354_n23), .CO(
DP_OP_45J178_125_5354_n22), .S(Add_Subt_Sgf_module_S_to_D[4]) );
DFFRX4TS FS_Module_state_reg_reg_0_ ( .D(FS_Module_state_next[0]), .CK(
FS_Module_net3641811), .RN(n421), .Q(FS_Module_state_reg[0]) );
DFFRX2TS Sel_B_Q_reg_1_ ( .D(n404), .CK(FS_Module_net3641811), .RN(n400),
.Q(FSM_selector_B[1]), .QN(n440) );
CMPR32X2TS DP_OP_45J178_125_5354_U12 ( .A(DP_OP_45J178_125_5354_n41), .B(
S_A_S_Oper_A[15]), .C(DP_OP_45J178_125_5354_n12), .CO(
DP_OP_45J178_125_5354_n11), .S(Add_Subt_Sgf_module_S_to_D[15]) );
CMPR32X2TS DP_OP_42J178_122_8048_U7 ( .A(DP_OP_42J178_122_8048_n18), .B(
S_Oper_A_exp[2]), .C(DP_OP_42J178_122_8048_n7), .CO(
DP_OP_42J178_122_8048_n6), .S(Exp_Operation_Module_Data_S[2]) );
CMPR32X2TS DP_OP_45J178_125_5354_U7 ( .A(DP_OP_45J178_125_5354_n36), .B(
S_A_S_Oper_A[20]), .C(DP_OP_45J178_125_5354_n7), .CO(
DP_OP_45J178_125_5354_n6), .S(Add_Subt_Sgf_module_S_to_D[20]) );
CLKINVX6TS U648 ( .A(rst), .Y(n489) );
NOR2X4TS U649 ( .A(overflow_flag), .B(underflow_flag), .Y(n995) );
INVX8TS U650 ( .A(n930), .Y(n971) );
OAI33X1TS U651 ( .A0(sign_final_result), .A1(r_mode[0]), .A2(n442), .B0(n439), .B1(n441), .B2(r_mode[1]), .Y(n443) );
XOR2XLTS U652 ( .A(DP_OP_45J178_125_5354_n1), .B(n1097), .Y(
Add_Subt_Sgf_module_S_to_D[26]) );
BUFX6TS U653 ( .A(n971), .Y(n972) );
CLKINVX6TS U654 ( .A(n734), .Y(n661) );
NOR2XLTS U655 ( .A(n980), .B(n652), .Y(n626) );
OAI211XLTS U656 ( .A0(n790), .A1(n789), .B0(n788), .C0(n787), .Y(
FS_Module_state_next[3]) );
CLKINVX6TS U657 ( .A(n767), .Y(n648) );
NOR3BXLTS U658 ( .AN(n556), .B(n791), .C(n411), .Y(n444) );
OAI211XLTS U659 ( .A0(n869), .A1(n925), .B0(n868), .C0(n867), .Y(n874) );
NOR2BX4TS U660 ( .AN(n565), .B(n824), .Y(n566) );
CLKINVX3TS U661 ( .A(n538), .Y(n420) );
NAND3XLTS U662 ( .A(n1089), .B(n866), .C(intDX[26]), .Y(n868) );
NAND2BXLTS U663 ( .AN(intDX[27]), .B(intDY[27]), .Y(n866) );
BUFX6TS U664 ( .A(n489), .Y(n421) );
BUFX6TS U665 ( .A(n489), .Y(n1102) );
BUFX6TS U666 ( .A(n489), .Y(n1106) );
BUFX6TS U667 ( .A(n489), .Y(n1101) );
BUFX6TS U668 ( .A(n489), .Y(n422) );
AO22XLTS U669 ( .A0(n649), .A1(Add_Subt_result[12]), .B0(DmP[11]), .B1(n705),
.Y(n650) );
AO22XLTS U670 ( .A0(n704), .A1(n761), .B0(n760), .B1(n991), .Y(n423) );
AO22XLTS U671 ( .A0(n710), .A1(n669), .B0(n988), .B1(n725), .Y(n426) );
AO22XLTS U672 ( .A0(n704), .A1(n714), .B0(n703), .B1(n991), .Y(n425) );
AOI211X1TS U673 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[30]), .A1(
n430), .B0(n612), .C0(n640), .Y(n614) );
AOI211X1TS U674 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[31]), .A1(
n430), .B0(n604), .C0(n640), .Y(n606) );
AOI211X1TS U675 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[32]), .A1(
n430), .B0(n600), .C0(n640), .Y(n602) );
AOI211X1TS U676 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[29]), .A1(
n430), .B0(n608), .C0(n640), .Y(n610) );
AOI211X1TS U677 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[33]), .A1(
n430), .B0(n594), .C0(n640), .Y(n598) );
AOI211X1TS U678 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[28]), .A1(
n430), .B0(n616), .C0(n640), .Y(n618) );
AOI32X1TS U679 ( .A0(n704), .A1(n661), .A2(n989), .B0(n772), .B1(n661), .Y(
n773) );
OA21XLTS U680 ( .A0(n961), .A1(n591), .B0(n632), .Y(n428) );
OR2X1TS U681 ( .A(n440), .B(n936), .Y(n429) );
OAI221X1TS U682 ( .A0(n1034), .A1(intDY[3]), .B0(n1012), .B1(intDY[2]), .C0(
n448), .Y(n451) );
OAI221X1TS U683 ( .A0(n1007), .A1(intDY[20]), .B0(n1038), .B1(intDY[19]),
.C0(n462), .Y(n465) );
INVX1TS U684 ( .A(ready), .Y(n492) );
NOR2X4TS U685 ( .A(n534), .B(add_overflow_flag), .Y(n967) );
OA21XLTS U686 ( .A0(Sgf_normalized_result[1]), .A1(Sgf_normalized_result[0]),
.B0(n443), .Y(n790) );
NOR2X2TS U687 ( .A(n931), .B(n480), .Y(n786) );
NAND4X1TS U688 ( .A(n479), .B(n478), .C(n477), .D(n476), .Y(n931) );
NOR2X2TS U689 ( .A(n704), .B(n992), .Y(n772) );
AOI222X1TS U690 ( .A0(n637), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[47]), .B0(n566), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[39]), .C0(
Barrel_Shifter_module_Mux_Array_Data_array[31]), .C1(n587), .Y(n607)
);
AOI222X1TS U691 ( .A0(n637), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[44]), .B0(n566), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[36]), .C0(
Barrel_Shifter_module_Mux_Array_Data_array[28]), .C1(n587), .Y(n619)
);
AOI222X1TS U692 ( .A0(n637), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[45]), .B0(n566), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[37]), .C0(
Barrel_Shifter_module_Mux_Array_Data_array[29]), .C1(n587), .Y(n611)
);
AOI222X1TS U693 ( .A0(n637), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[48]), .B0(n566), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[40]), .C0(
Barrel_Shifter_module_Mux_Array_Data_array[32]), .C1(n587), .Y(n603)
);
AOI222X1TS U694 ( .A0(n637), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[49]), .B0(n566), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[41]), .C0(
Barrel_Shifter_module_Mux_Array_Data_array[33]), .C1(n587), .Y(n599)
);
AOI222X1TS U695 ( .A0(n637), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[46]), .B0(n566), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[38]), .C0(
Barrel_Shifter_module_Mux_Array_Data_array[30]), .C1(n587), .Y(n615)
);
NOR2X4TS U696 ( .A(n824), .B(n571), .Y(n587) );
INVX2TS U697 ( .A(n428), .Y(n430) );
NOR2X2TS U698 ( .A(n538), .B(n936), .Y(n954) );
INVX2TS U699 ( .A(n429), .Y(n431) );
BUFX4TS U700 ( .A(n1106), .Y(n1100) );
BUFX4TS U701 ( .A(n491), .Y(n1105) );
BUFX3TS U702 ( .A(n489), .Y(n490) );
AOI32X2TS U703 ( .A0(n700), .A1(n704), .A2(n699), .B0(n698), .B1(n991), .Y(
n724) );
NAND2X2TS U704 ( .A(n625), .B(n567), .Y(n564) );
AND2X6TS U705 ( .A(n826), .B(n623), .Y(n704) );
OAI221XLTS U706 ( .A0(n1033), .A1(intDY[29]), .B0(n1036), .B1(intDX[12]),
.C0(n471), .Y(n472) );
OAI2BB1X2TS U707 ( .A0N(exp_oper_result[0]), .A1N(n1029), .B0(n830), .Y(n652) );
AOI222X1TS U708 ( .A0(n985), .A1(n661), .B0(n989), .B1(n648), .C0(n988),
.C1(n986), .Y(n763) );
BUFX6TS U709 ( .A(n654), .Y(n986) );
INVX2TS U710 ( .A(n424), .Y(overflow_flag) );
INVX2TS U711 ( .A(n427), .Y(n433) );
INVX2TS U712 ( .A(n426), .Y(n434) );
AOI22X2TS U713 ( .A0(n710), .A1(n697), .B0(n696), .B1(n991), .Y(n759) );
INVX2TS U714 ( .A(n423), .Y(n435) );
INVX2TS U715 ( .A(n425), .Y(n436) );
INVX6TS U716 ( .A(n715), .Y(n706) );
BUFX6TS U717 ( .A(FSM_selector_D), .Y(n853) );
BUFX6TS U718 ( .A(n1045), .Y(n705) );
CLKINVX6TS U719 ( .A(n971), .Y(n973) );
INVX6TS U720 ( .A(n717), .Y(n708) );
OAI2BB1X2TS U721 ( .A0N(Add_Subt_result[24]), .A1N(n673), .B0(n672), .Y(n985) );
NOR2X1TS U722 ( .A(Add_Subt_result[23]), .B(Add_Subt_result[22]), .Y(n855)
);
OAI2BB1X2TS U723 ( .A0N(Add_Subt_result[22]), .A1N(n708), .B0(n670), .Y(n989) );
INVX2TS U724 ( .A(n437), .Y(n438) );
OAI221X1TS U725 ( .A0(n1053), .A1(intDY[16]), .B0(n1041), .B1(intDY[15]),
.C0(n460), .Y(n467) );
OAI221X1TS U726 ( .A0(n1009), .A1(intDY[24]), .B0(n1043), .B1(intDY[23]),
.C0(n468), .Y(n475) );
AOI221X1TS U727 ( .A0(intDX[30]), .A1(n1018), .B0(intDX[29]), .B1(n1083),
.C0(n871), .Y(n873) );
AOI222X1TS U728 ( .A0(n939), .A1(n636), .B0(FSM_selector_B[1]), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[38]), .C0(n937), .C1(n635),
.Y(n942) );
MXI2X2TS U729 ( .A(n1016), .B(n1051), .S0(exp_oper_result[3]), .Y(n937) );
NAND2X2TS U730 ( .A(n420), .B(exp_oper_result[4]), .Y(n570) );
OAI221X1TS U731 ( .A0(n1030), .A1(intDY[11]), .B0(n1011), .B1(intDY[10]),
.C0(n894), .Y(n457) );
OAI2BB2XLTS U732 ( .B0(n896), .B1(n903), .A0N(n895), .A1N(n894), .Y(n899) );
AOI22X2TS U733 ( .A0(n1030), .A1(intDY[11]), .B0(n1011), .B1(intDY[10]), .Y(
n894) );
AOI22X2TS U734 ( .A0(n526), .A1(Add_Subt_result[10]), .B0(n845), .B1(
Add_Subt_result[18]), .Y(n863) );
NOR2X2TS U735 ( .A(n841), .B(n499), .Y(n526) );
OAI211X1TS U736 ( .A0(FSM_selector_B[1]), .A1(n1031), .B0(n824), .C0(n590),
.Y(n536) );
NOR2X2TS U737 ( .A(n532), .B(n1003), .Y(n590) );
OAI211X2TS U738 ( .A0(intDX[12]), .A1(n1036), .B0(n901), .C0(n887), .Y(n903)
);
AOI211XLTS U739 ( .A0(intDY[16]), .A1(n1053), .B0(n915), .C0(n916), .Y(n907)
);
OAI211X2TS U740 ( .A0(intDX[20]), .A1(n1071), .B0(n921), .C0(n906), .Y(n915)
);
BUFX4TS U741 ( .A(n491), .Y(n1109) );
BUFX4TS U742 ( .A(n490), .Y(n1110) );
BUFX4TS U743 ( .A(n1101), .Y(n1107) );
BUFX4TS U744 ( .A(n489), .Y(n1108) );
BUFX3TS U745 ( .A(n489), .Y(n491) );
NOR2X4TS U746 ( .A(n595), .B(n958), .Y(n840) );
AOI21X2TS U747 ( .A0(FSM_selector_B[0]), .A1(n569), .B0(n568), .Y(n595) );
NOR4X4TS U748 ( .A(FS_Module_state_reg[0]), .B(FS_Module_state_reg[3]), .C(
FS_Module_state_reg[2]), .D(n1000), .Y(n413) );
NOR2X4TS U749 ( .A(n1029), .B(FSM_selector_B[1]), .Y(n625) );
BUFX6TS U750 ( .A(n995), .Y(n997) );
NOR3X1TS U751 ( .A(n1098), .B(n870), .C(intDY[28]), .Y(n871) );
OAI221X1TS U752 ( .A0(n1098), .A1(intDY[28]), .B0(n1013), .B1(intDY[27]),
.C0(n470), .Y(n473) );
BUFX6TS U753 ( .A(n626), .Y(n990) );
NOR2X2TS U754 ( .A(Add_Subt_result[11]), .B(Add_Subt_result[13]), .Y(n842)
);
OAI2BB1X2TS U755 ( .A0N(Add_Subt_result[23]), .A1N(n708), .B0(n668), .Y(n988) );
NOR2X2TS U756 ( .A(Add_Subt_result[6]), .B(Add_Subt_result[7]), .Y(n523) );
AOI22X2TS U757 ( .A0(n710), .A1(n680), .B0(n669), .B1(n725), .Y(n742) );
AOI22X2TS U758 ( .A0(n710), .A1(n696), .B0(n690), .B1(n725), .Y(n748) );
AOI22X2TS U759 ( .A0(n710), .A1(n690), .B0(n680), .B1(n725), .Y(n754) );
AOI22X2TS U760 ( .A0(n704), .A1(n663), .B0(n761), .B1(n725), .Y(n738) );
AOI22X2TS U761 ( .A0(n704), .A1(n684), .B0(n663), .B1(n725), .Y(n749) );
AOI22X2TS U762 ( .A0(n704), .A1(n698), .B0(n692), .B1(n725), .Y(n756) );
AOI22X2TS U763 ( .A0(n704), .A1(n692), .B0(n686), .B1(n725), .Y(n745) );
AOI22X2TS U764 ( .A0(n704), .A1(n686), .B0(n671), .B1(n725), .Y(n751) );
AOI22X2TS U765 ( .A0(n704), .A1(n727), .B0(n726), .B1(n725), .Y(n755) );
AOI22X2TS U766 ( .A0(n710), .A1(n726), .B0(n684), .B1(n725), .Y(n743) );
AOI22X2TS U767 ( .A0(n704), .A1(n703), .B0(n682), .B1(n725), .Y(n744) );
AOI22X2TS U768 ( .A0(n704), .A1(n660), .B0(n674), .B1(n725), .Y(n739) );
AOI22X2TS U769 ( .A0(n704), .A1(n682), .B0(n660), .B1(n991), .Y(n750) );
INVX4TS U770 ( .A(n710), .Y(n991) );
INVX4TS U771 ( .A(n710), .Y(n725) );
BUFX6TS U772 ( .A(FSM_selector_D), .Y(n854) );
BUFX6TS U773 ( .A(n814), .Y(n1097) );
NOR3X1TS U774 ( .A(n844), .B(Add_Subt_result[18]), .C(Add_Subt_result[14]),
.Y(n496) );
NOR2X4TS U775 ( .A(n1001), .B(LZA_output[4]), .Y(n565) );
NOR2X4TS U776 ( .A(LZA_output[3]), .B(LZA_output[4]), .Y(n569) );
NOR2X2TS U777 ( .A(LZA_output[4]), .B(n824), .Y(n636) );
OAI221X1TS U778 ( .A0(n1099), .A1(intDY[7]), .B0(n1019), .B1(intDY[6]), .C0(
n883), .Y(n459) );
AOI211XLTS U779 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[41]), .A1(
n562), .B0(n945), .C0(n547), .Y(n548) );
AOI211XLTS U780 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[40]), .A1(
n562), .B0(n945), .C0(n544), .Y(n545) );
AOI211XLTS U781 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[37]), .A1(
n562), .B0(n945), .C0(n539), .Y(n540) );
AOI211XLTS U782 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[36]), .A1(
n562), .B0(n945), .C0(n552), .Y(n553) );
NOR2XLTS U783 ( .A(n1081), .B(intDX[11]), .Y(n889) );
OAI21XLTS U784 ( .A0(intDX[15]), .A1(n1090), .B0(intDX[14]), .Y(n897) );
NOR2XLTS U785 ( .A(n910), .B(intDY[16]), .Y(n911) );
OAI21XLTS U786 ( .A0(intDX[23]), .A1(n1091), .B0(intDX[22]), .Y(n917) );
OR2X1TS U787 ( .A(FSM_selector_B[0]), .B(FSM_selector_B[1]), .Y(n538) );
NOR2XLTS U788 ( .A(n962), .B(n1051), .Y(n612) );
NOR2XLTS U789 ( .A(n991), .B(n661), .Y(n984) );
AOI31XLTS U790 ( .A0(n516), .A1(Add_Subt_result[6]), .A2(n1094), .B0(n515),
.Y(n518) );
OAI211XLTS U791 ( .A0(n434), .A1(n734), .B0(n678), .C0(n677), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[16]) );
OAI211XLTS U792 ( .A0(n759), .A1(n767), .B0(n729), .C0(n728), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[2]) );
OAI211XLTS U793 ( .A0(n948), .A1(n958), .B0(n643), .C0(n642), .Y(n1132) );
XOR2X1TS U794 ( .A(n1111), .B(n438), .Y(n480) );
BUFX4TS U795 ( .A(FSM_selector_D), .Y(n832) );
NOR2X2TS U796 ( .A(n480), .B(n832), .Y(n814) );
NOR3X2TS U797 ( .A(FS_Module_state_reg[3]), .B(n1000), .C(n1027), .Y(
FSM_Add_Subt_Sgf_load) );
NOR2X2TS U798 ( .A(FS_Module_state_reg[1]), .B(n1028), .Y(n555) );
AND3X1TS U799 ( .A(n555), .B(FS_Module_state_reg[0]), .C(
FS_Module_state_reg[2]), .Y(FSM_Final_Result_load) );
NOR2X2TS U800 ( .A(FS_Module_state_reg[1]), .B(FS_Module_state_reg[3]), .Y(
n558) );
INVX2TS U801 ( .A(FS_Module_state_reg[0]), .Y(n557) );
NOR2X2TS U802 ( .A(FS_Module_state_reg[2]), .B(n557), .Y(n627) );
CLKAND2X2TS U803 ( .A(n558), .B(n627), .Y(n411) );
NAND2X1TS U804 ( .A(FS_Module_state_reg[2]), .B(n558), .Y(n482) );
INVX2TS U805 ( .A(n482), .Y(n620) );
NAND2X1TS U806 ( .A(FS_Module_state_reg[0]), .B(n620), .Y(n998) );
AOI211XLTS U807 ( .A0(FS_Module_state_reg[0]), .A1(FSM_Add_Subt_Sgf_load),
.B0(n413), .C0(FSM_Final_Result_load), .Y(n445) );
NOR3X2TS U808 ( .A(FS_Module_state_reg[0]), .B(FS_Module_state_reg[2]), .C(
n1028), .Y(n850) );
NAND2X1TS U809 ( .A(FS_Module_state_reg[1]), .B(n850), .Y(n556) );
INVX2TS U810 ( .A(r_mode[1]), .Y(n442) );
INVX2TS U811 ( .A(r_mode[0]), .Y(n441) );
NAND2X1TS U812 ( .A(n627), .B(n555), .Y(n789) );
NOR2BX1TS U813 ( .AN(n790), .B(n789), .Y(n791) );
OAI211XLTS U814 ( .A0(FSM_selector_C), .A1(n998), .B0(n444), .C0(n445), .Y(
FS_Module_state_next[1]) );
INVX2TS U815 ( .A(n627), .Y(n446) );
OAI22X1TS U816 ( .A0(FS_Module_state_reg[0]), .A1(n482), .B0(n1000), .B1(
n446), .Y(FSM_exp_operation_load_diff) );
AOI22X1TS U817 ( .A0(intDX[30]), .A1(intDY[30]), .B0(n1018), .B1(n1047), .Y(
n453) );
AOI22X1TS U818 ( .A0(n1032), .A1(intDY[1]), .B0(n1015), .B1(intDY[0]), .Y(
n447) );
OAI221XLTS U819 ( .A0(n1032), .A1(intDY[1]), .B0(n1015), .B1(intDY[0]), .C0(
n447), .Y(n452) );
AOI22X1TS U820 ( .A0(n1034), .A1(intDY[3]), .B0(n1012), .B1(intDY[2]), .Y(
n448) );
AOI22X1TS U821 ( .A0(n1046), .A1(intDY[5]), .B0(n1014), .B1(intDY[4]), .Y(
n449) );
OAI221XLTS U822 ( .A0(n1046), .A1(intDY[5]), .B0(n1014), .B1(intDY[4]), .C0(
n449), .Y(n450) );
NOR4X1TS U823 ( .A(n453), .B(n452), .C(n451), .D(n450), .Y(n479) );
AOI22X1TS U824 ( .A0(intDY[7]), .A1(n1099), .B0(intDY[6]), .B1(n1019), .Y(
n883) );
AOI22X1TS U825 ( .A0(n1004), .A1(intDY[9]), .B0(n1035), .B1(intDY[8]), .Y(
n454) );
OAI221XLTS U826 ( .A0(n1004), .A1(intDY[9]), .B0(n1035), .B1(intDY[8]), .C0(
n454), .Y(n458) );
AOI22X1TS U827 ( .A0(n1005), .A1(intDY[14]), .B0(n1040), .B1(intDY[13]), .Y(
n455) );
OAI221XLTS U828 ( .A0(n1005), .A1(intDY[14]), .B0(n1040), .B1(intDY[13]),
.C0(n455), .Y(n456) );
NOR4X1TS U829 ( .A(n459), .B(n458), .C(n457), .D(n456), .Y(n478) );
AOI22X1TS U830 ( .A0(n1053), .A1(intDY[16]), .B0(n1041), .B1(intDY[15]), .Y(
n460) );
AOI22X1TS U831 ( .A0(n1006), .A1(intDY[18]), .B0(n1037), .B1(intDY[17]), .Y(
n461) );
OAI221XLTS U832 ( .A0(n1006), .A1(intDY[18]), .B0(n1037), .B1(intDY[17]),
.C0(n461), .Y(n466) );
AOI22X1TS U833 ( .A0(n1007), .A1(intDY[20]), .B0(n1038), .B1(intDY[19]), .Y(
n462) );
AOI22X1TS U834 ( .A0(n1008), .A1(intDY[22]), .B0(n1042), .B1(intDY[21]), .Y(
n463) );
OAI221XLTS U835 ( .A0(n1008), .A1(intDY[22]), .B0(n1042), .B1(intDY[21]),
.C0(n463), .Y(n464) );
NOR4X1TS U836 ( .A(n467), .B(n466), .C(n465), .D(n464), .Y(n477) );
AOI22X1TS U837 ( .A0(n1009), .A1(intDY[24]), .B0(n1043), .B1(intDY[23]), .Y(
n468) );
AOI22X1TS U838 ( .A0(n1010), .A1(intDY[26]), .B0(n1039), .B1(intDY[25]), .Y(
n469) );
OAI221XLTS U839 ( .A0(n1010), .A1(intDY[26]), .B0(n1039), .B1(intDY[25]),
.C0(n469), .Y(n474) );
AOI22X1TS U840 ( .A0(n1098), .A1(intDY[28]), .B0(n1013), .B1(intDY[27]), .Y(
n470) );
AOI22X1TS U841 ( .A0(n1033), .A1(intDY[29]), .B0(n1036), .B1(intDX[12]), .Y(
n471) );
NOR4X1TS U842 ( .A(n475), .B(n474), .C(n473), .D(n472), .Y(n476) );
AOI211XLTS U843 ( .A0(n786), .A1(n413), .B0(n555), .C0(
FSM_exp_operation_load_diff), .Y(n481) );
OAI21XLTS U844 ( .A0(FSM_selector_C), .A1(n998), .B0(n481), .Y(
FS_Module_state_next[2]) );
NAND3X2TS U845 ( .A(n1027), .B(n557), .C(n558), .Y(n400) );
AOI21X1TS U846 ( .A0(n627), .A1(FS_Module_state_reg[3]), .B0(n558), .Y(n485)
);
NOR3XLTS U847 ( .A(FS_Module_state_reg[0]), .B(FSM_selector_C), .C(n482),
.Y(n483) );
AOI211XLTS U848 ( .A0(FS_Module_state_reg[0]), .A1(n1000), .B0(n483), .C0(
n1003), .Y(n484) );
NAND3BXLTS U849 ( .AN(n485), .B(n484), .C(n400), .Y(n486) );
CLKBUFX3TS U850 ( .A(n486), .Y(n1096) );
AND4X1TS U851 ( .A(Exp_Operation_Module_Data_S[3]), .B(
Exp_Operation_Module_Data_S[2]), .C(Exp_Operation_Module_Data_S[1]),
.D(Exp_Operation_Module_Data_S[0]), .Y(n487) );
AND4X1TS U852 ( .A(Exp_Operation_Module_Data_S[6]), .B(
Exp_Operation_Module_Data_S[5]), .C(Exp_Operation_Module_Data_S[4]),
.D(n487), .Y(n488) );
XOR2X1TS U853 ( .A(DP_OP_42J178_122_8048_n1), .B(n1096), .Y(n781) );
AO21XLTS U854 ( .A0(Exp_Operation_Module_Data_S[7]), .A1(n488), .B0(n781),
.Y(n1112) );
BUFX3TS U855 ( .A(n489), .Y(n1104) );
NOR4X1TS U856 ( .A(FS_Module_state_reg[0]), .B(n1028), .C(n1000), .D(n1027),
.Y(ready) );
OA22X1TS U857 ( .A0(ack_FSM), .A1(n492), .B0(beg_FSM), .B1(n400), .Y(n412)
);
INVX2TS U858 ( .A(FSM_Add_Subt_Sgf_load), .Y(n493) );
OAI21XLTS U859 ( .A0(FS_Module_state_reg[0]), .A1(n493), .B0(n705), .Y(n407)
);
INVX2TS U860 ( .A(n850), .Y(n852) );
NOR2XLTS U861 ( .A(FS_Module_state_reg[1]), .B(n852), .Y(FSM_LZA_load) );
INVX2TS U862 ( .A(Add_Subt_result[0]), .Y(n716) );
AOI2BB1X1TS U863 ( .A0N(n716), .A1N(Add_Subt_result[1]), .B0(
Add_Subt_result[2]), .Y(n519) );
NOR2BX1TS U864 ( .AN(n519), .B(Add_Subt_result[3]), .Y(n507) );
NOR3X1TS U865 ( .A(Add_Subt_result[21]), .B(Add_Subt_result[20]), .C(
Add_Subt_result[19]), .Y(n502) );
INVX2TS U866 ( .A(n502), .Y(n494) );
NOR2X1TS U867 ( .A(Add_Subt_result[25]), .B(Add_Subt_result[24]), .Y(n859)
);
NAND2X1TS U868 ( .A(n859), .B(n855), .Y(n501) );
NOR2X2TS U869 ( .A(n494), .B(n501), .Y(n845) );
NOR2XLTS U870 ( .A(Add_Subt_result[15]), .B(Add_Subt_result[16]), .Y(n495)
);
NAND2X1TS U871 ( .A(n1017), .B(n495), .Y(n844) );
NAND2X1TS U872 ( .A(n845), .B(n496), .Y(n841) );
NAND2X1TS U873 ( .A(n842), .B(n1022), .Y(n499) );
NOR3X1TS U874 ( .A(Add_Subt_result[9]), .B(Add_Subt_result[10]), .C(
Add_Subt_result[8]), .Y(n497) );
NAND2X1TS U875 ( .A(n526), .B(n497), .Y(n522) );
NAND2X1TS U876 ( .A(n523), .B(n1023), .Y(n498) );
OR2X1TS U877 ( .A(n522), .B(n498), .Y(n504) );
NOR2X1TS U878 ( .A(n504), .B(Add_Subt_result[4]), .Y(n520) );
INVX2TS U879 ( .A(n520), .Y(n508) );
INVX2TS U880 ( .A(n522), .Y(n516) );
INVX2TS U881 ( .A(n841), .Y(n860) );
NAND2X1TS U882 ( .A(n860), .B(n499), .Y(n500) );
OAI211XLTS U883 ( .A0(n502), .A1(n501), .B0(n863), .C0(n500), .Y(n503) );
AOI31XLTS U884 ( .A0(n516), .A1(n523), .A2(Add_Subt_result[5]), .B0(n503),
.Y(n506) );
INVX2TS U885 ( .A(n504), .Y(n505) );
CLKAND2X2TS U886 ( .A(n505), .B(Add_Subt_result[4]), .Y(n524) );
INVX2TS U887 ( .A(n524), .Y(n517) );
OAI211XLTS U888 ( .A0(n507), .A1(n508), .B0(n506), .C0(n517), .Y(
Leading_Zero_Detector_Module_Codec_to_Reg[2]) );
NOR2X1TS U889 ( .A(n508), .B(Add_Subt_result[3]), .Y(n527) );
INVX2TS U890 ( .A(n527), .Y(n529) );
INVX2TS U891 ( .A(n845), .Y(n857) );
NOR4BX1TS U892 ( .AN(Add_Subt_result[14]), .B(n857), .C(Add_Subt_result[18]),
.D(n844), .Y(n509) );
AOI31X1TS U893 ( .A0(n860), .A1(Add_Subt_result[12]), .A2(n1061), .B0(n509),
.Y(n847) );
AOI21X1TS U894 ( .A0(n1050), .A1(Add_Subt_result[20]), .B0(
Add_Subt_result[22]), .Y(n510) );
AOI2BB1XLTS U895 ( .A0N(n510), .A1N(Add_Subt_result[23]), .B0(
Add_Subt_result[24]), .Y(n511) );
NOR2XLTS U896 ( .A(n511), .B(Add_Subt_result[25]), .Y(n512) );
AOI31XLTS U897 ( .A0(n845), .A1(Add_Subt_result[16]), .A2(n1017), .B0(n512),
.Y(n514) );
NAND4XLTS U898 ( .A(n860), .B(n842), .C(Add_Subt_result[8]), .D(n1078), .Y(
n513) );
NAND4XLTS U899 ( .A(n847), .B(n863), .C(n514), .D(n513), .Y(n515) );
OAI211XLTS U900 ( .A0(n519), .A1(n529), .B0(n518), .C0(n517), .Y(
Leading_Zero_Detector_Module_Codec_to_Reg[0]) );
AOI31XLTS U901 ( .A0(n1078), .A1(n1002), .A2(n1023), .B0(Add_Subt_result[10]), .Y(n525) );
OAI21XLTS U902 ( .A0(Add_Subt_result[3]), .A1(Add_Subt_result[2]), .B0(n520),
.Y(n521) );
OAI21X1TS U903 ( .A0(n523), .A1(n522), .B0(n521), .Y(n864) );
AOI211XLTS U904 ( .A0(n526), .A1(n525), .B0(n864), .C0(n524), .Y(n528) );
NAND3XLTS U905 ( .A(n527), .B(Add_Subt_result[1]), .C(n1075), .Y(n848) );
OAI211XLTS U906 ( .A0(n716), .A1(n529), .B0(n848), .C0(n528), .Y(
Leading_Zero_Detector_Module_Codec_to_Reg[4]) );
NAND2X1TS U907 ( .A(n420), .B(exp_oper_result[3]), .Y(n572) );
NOR2X2TS U908 ( .A(n572), .B(exp_oper_result[4]), .Y(n835) );
NOR2XLTS U909 ( .A(n1028), .B(n1003), .Y(n531) );
NAND2X1TS U910 ( .A(FSM_selector_C), .B(n1028), .Y(n534) );
INVX2TS U911 ( .A(n534), .Y(n530) );
NOR2X2TS U912 ( .A(n531), .B(n530), .Y(n567) );
INVX2TS U913 ( .A(n625), .Y(n824) );
NOR2XLTS U914 ( .A(FSM_selector_C), .B(FS_Module_state_reg[3]), .Y(n532) );
INVX2TS U915 ( .A(n590), .Y(n936) );
NOR2X2TS U916 ( .A(n824), .B(n936), .Y(n956) );
INVX2TS U917 ( .A(n956), .Y(n537) );
NOR2X1TS U918 ( .A(n1001), .B(n537), .Y(n592) );
NOR2X1TS U919 ( .A(n936), .B(n572), .Y(n593) );
AOI211X4TS U920 ( .A0(n835), .A1(n567), .B0(n592), .C0(n593), .Y(n596) );
NOR3X1TS U921 ( .A(exp_oper_result[4]), .B(FSM_selector_B[0]), .C(
exp_oper_result[3]), .Y(n533) );
NOR2X2TS U922 ( .A(n533), .B(FSM_selector_B[1]), .Y(n591) );
INVX4TS U923 ( .A(n967), .Y(n958) );
NOR2X4TS U924 ( .A(n591), .B(n958), .Y(n938) );
AOI22X1TS U925 ( .A0(n565), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[45]), .B0(n569), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[37]), .Y(n543) );
AOI2BB2XLTS U926 ( .B0(Barrel_Shifter_module_Mux_Array_Data_array[40]), .B1(
n938), .A0N(n543), .A1N(n564), .Y(n541) );
INVX2TS U927 ( .A(n591), .Y(n568) );
NAND2X1TS U928 ( .A(n567), .B(n568), .Y(n535) );
OAI211X2TS U929 ( .A0(LZA_output[3]), .A1(n537), .B0(n536), .C0(n535), .Y(
n562) );
NAND2X2TS U930 ( .A(n625), .B(LZA_output[4]), .Y(n838) );
AOI21X4TS U931 ( .A0(n838), .A1(n570), .B0(n936), .Y(n945) );
AOI22X1TS U932 ( .A0(n565), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[48]), .B0(n569), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[40]), .Y(n542) );
NAND2X2TS U933 ( .A(n625), .B(n967), .Y(n934) );
NAND2X2TS U934 ( .A(n835), .B(n967), .Y(n933) );
OAI22X1TS U935 ( .A0(n542), .A1(n934), .B0(n1057), .B1(n933), .Y(n539) );
OAI211XLTS U936 ( .A0(n596), .A1(n1056), .B0(n541), .C0(n540), .Y(n1136) );
AOI2BB2XLTS U937 ( .B0(Barrel_Shifter_module_Mux_Array_Data_array[37]), .B1(
n938), .A0N(n542), .A1N(n564), .Y(n546) );
OAI22X1TS U938 ( .A0(n543), .A1(n934), .B0(n1056), .B1(n933), .Y(n544) );
OAI211XLTS U939 ( .A0(n596), .A1(n1057), .B0(n546), .C0(n545), .Y(n1135) );
AOI22X1TS U940 ( .A0(n565), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[49]), .B0(n569), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[41]), .Y(n551) );
AOI2BB2XLTS U941 ( .B0(Barrel_Shifter_module_Mux_Array_Data_array[36]), .B1(
n938), .A0N(n551), .A1N(n564), .Y(n549) );
AOI22X1TS U942 ( .A0(n565), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[44]), .B0(n569), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[36]), .Y(n550) );
OAI22X1TS U943 ( .A0(n550), .A1(n934), .B0(n1058), .B1(n933), .Y(n547) );
OAI211XLTS U944 ( .A0(n596), .A1(n1055), .B0(n549), .C0(n548), .Y(n1133) );
AOI2BB2XLTS U945 ( .B0(Barrel_Shifter_module_Mux_Array_Data_array[41]), .B1(
n938), .A0N(n550), .A1N(n564), .Y(n554) );
OAI22X1TS U946 ( .A0(n551), .A1(n934), .B0(n1055), .B1(n933), .Y(n552) );
OAI211XLTS U947 ( .A0(n596), .A1(n1058), .B0(n554), .C0(n553), .Y(n1134) );
INVX2TS U948 ( .A(n413), .Y(n560) );
NAND3X1TS U949 ( .A(FS_Module_state_reg[2]), .B(n555), .C(n557), .Y(n999) );
OAI211X1TS U950 ( .A0(n705), .A1(n998), .B0(n999), .C0(n556), .Y(n784) );
AOI21X1TS U951 ( .A0(n558), .A1(n557), .B0(n784), .Y(n559) );
OAI211XLTS U952 ( .A0(n786), .A1(n560), .B0(n559), .C0(n789), .Y(
FS_Module_state_next[0]) );
AOI22X1TS U953 ( .A0(n565), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[47]), .B0(n569), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[39]), .Y(n935) );
AOI22X1TS U954 ( .A0(LZA_output[3]), .A1(n1051), .B0(n1016), .B1(n1001), .Y(
n939) );
CLKAND2X2TS U955 ( .A(n420), .B(n1044), .Y(n635) );
OAI22X1TS U956 ( .A0(n596), .A1(n1054), .B0(n942), .B1(n958), .Y(n561) );
AOI21X1TS U957 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[39]), .A1(
n562), .B0(n561), .Y(n563) );
INVX2TS U958 ( .A(n945), .Y(n962) );
OAI211XLTS U959 ( .A0(n935), .A1(n564), .B0(n563), .C0(n962), .Y(n1137) );
OAI22X4TS U960 ( .A0(n838), .A1(LZA_output[3]), .B0(exp_oper_result[3]),
.B1(n570), .Y(n637) );
INVX2TS U961 ( .A(n569), .Y(n571) );
INVX3TS U962 ( .A(n567), .Y(n961) );
OAI21X4TS U963 ( .A0(n961), .A1(n595), .B0(n936), .Y(n968) );
AOI22X1TS U964 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[49]), .A1(
n968), .B0(Barrel_Shifter_module_Mux_Array_Data_array[28]), .B1(n938),
.Y(n575) );
INVX2TS U965 ( .A(n933), .Y(n957) );
INVX2TS U966 ( .A(n570), .Y(n834) );
AOI21X1TS U967 ( .A0(n625), .A1(n571), .B0(n834), .Y(n573) );
AOI21X4TS U968 ( .A0(n573), .A1(n572), .B0(n936), .Y(n970) );
AOI21X1TS U969 ( .A0(n957), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[36]), .B0(n970), .Y(n574)
);
OAI211XLTS U970 ( .A0(n619), .A1(n958), .B0(n575), .C0(n574), .Y(n1121) );
AOI22X1TS U971 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[45]), .A1(
n968), .B0(Barrel_Shifter_module_Mux_Array_Data_array[32]), .B1(n938),
.Y(n577) );
AOI21X1TS U972 ( .A0(n957), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[40]), .B0(n970), .Y(n576)
);
OAI211XLTS U973 ( .A0(n603), .A1(n958), .B0(n577), .C0(n576), .Y(n1123) );
AOI22X1TS U974 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[47]), .A1(
n968), .B0(Barrel_Shifter_module_Mux_Array_Data_array[30]), .B1(n938),
.Y(n579) );
AOI21X1TS U975 ( .A0(n957), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[38]), .B0(n970), .Y(n578)
);
OAI211XLTS U976 ( .A0(n615), .A1(n958), .B0(n579), .C0(n578), .Y(n1115) );
OAI22X1TS U977 ( .A0(n1001), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[51]), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[43]), .B1(LZA_output[3]),
.Y(n630) );
MXI2X2TS U978 ( .A(n1020), .B(n1049), .S0(exp_oper_result[3]), .Y(n953) );
INVX2TS U979 ( .A(n595), .Y(n833) );
AOI22X1TS U980 ( .A0(n834), .A1(n953), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[27]), .B1(n833), .Y(n580)
);
OAI21X1TS U981 ( .A0(n630), .A1(n838), .B0(n580), .Y(n581) );
OAI32X1TS U982 ( .A0(n581), .A1(n835), .A2(n566), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[35]), .B1(n581), .Y(n792)
);
AOI21X1TS U983 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[50]), .A1(
n968), .B0(n970), .Y(n582) );
OAI21XLTS U984 ( .A0(n792), .A1(n958), .B0(n582), .Y(n1117) );
AOI22X1TS U985 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[31]), .A1(
n938), .B0(Barrel_Shifter_module_Mux_Array_Data_array[46]), .B1(n968),
.Y(n584) );
AOI21X1TS U986 ( .A0(n957), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[39]), .B0(n970), .Y(n583)
);
OAI211XLTS U987 ( .A0(n607), .A1(n958), .B0(n584), .C0(n583), .Y(n1119) );
AOI22X1TS U988 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[29]), .A1(
n938), .B0(Barrel_Shifter_module_Mux_Array_Data_array[48]), .B1(n968),
.Y(n586) );
AOI21X1TS U989 ( .A0(n957), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[37]), .B0(n970), .Y(n585)
);
OAI211XLTS U990 ( .A0(n611), .A1(n958), .B0(n586), .C0(n585), .Y(n1125) );
AOI22X1TS U991 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[33]), .A1(
n938), .B0(Barrel_Shifter_module_Mux_Array_Data_array[44]), .B1(n968),
.Y(n589) );
AOI21X1TS U992 ( .A0(n957), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[41]), .B0(n970), .Y(n588)
);
OAI211XLTS U993 ( .A0(n599), .A1(n958), .B0(n589), .C0(n588), .Y(n1127) );
NAND2X1TS U994 ( .A(n833), .B(n590), .Y(n632) );
NOR2XLTS U995 ( .A(n962), .B(n1055), .Y(n594) );
AO22X2TS U996 ( .A0(n593), .A1(exp_oper_result[4]), .B0(LZA_output[4]), .B1(
n592), .Y(n640) );
INVX2TS U997 ( .A(n596), .Y(n638) );
AOI22X1TS U998 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[44]), .A1(
n840), .B0(Barrel_Shifter_module_Mux_Array_Data_array[41]), .B1(n638),
.Y(n597) );
OAI211XLTS U999 ( .A0(n599), .A1(n961), .B0(n598), .C0(n597), .Y(n1128) );
NOR2XLTS U1000 ( .A(n962), .B(n1057), .Y(n600) );
AOI22X1TS U1001 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[45]), .A1(
n840), .B0(Barrel_Shifter_module_Mux_Array_Data_array[40]), .B1(n638),
.Y(n601) );
OAI211XLTS U1002 ( .A0(n603), .A1(n961), .B0(n602), .C0(n601), .Y(n1124) );
NOR2XLTS U1003 ( .A(n962), .B(n1054), .Y(n604) );
AOI22X1TS U1004 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[46]), .A1(
n840), .B0(Barrel_Shifter_module_Mux_Array_Data_array[39]), .B1(n638),
.Y(n605) );
OAI211XLTS U1005 ( .A0(n607), .A1(n961), .B0(n606), .C0(n605), .Y(n1120) );
NOR2XLTS U1006 ( .A(n962), .B(n1056), .Y(n608) );
AOI22X1TS U1007 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[48]), .A1(
n840), .B0(Barrel_Shifter_module_Mux_Array_Data_array[37]), .B1(n638),
.Y(n609) );
OAI211XLTS U1008 ( .A0(n611), .A1(n961), .B0(n610), .C0(n609), .Y(n1126) );
AOI22X1TS U1009 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[47]), .A1(
n840), .B0(Barrel_Shifter_module_Mux_Array_Data_array[38]), .B1(n638),
.Y(n613) );
OAI211XLTS U1010 ( .A0(n615), .A1(n961), .B0(n614), .C0(n613), .Y(n1116) );
NOR2XLTS U1011 ( .A(n962), .B(n1058), .Y(n616) );
AOI22X1TS U1012 ( .A0(n840), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[49]), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[36]), .B1(n638), .Y(n617)
);
OAI211XLTS U1013 ( .A0(n619), .A1(n961), .B0(n618), .C0(n617), .Y(n1122) );
NAND2X1TS U1014 ( .A(FSM_selector_C), .B(n620), .Y(n776) );
NOR2X1TS U1015 ( .A(n776), .B(add_overflow_flag), .Y(n649) );
INVX2TS U1016 ( .A(n649), .Y(n715) );
NOR2X1TS U1017 ( .A(n706), .B(n705), .Y(n673) );
INVX2TS U1018 ( .A(n673), .Y(n717) );
NAND2X1TS U1019 ( .A(n708), .B(n1052), .Y(n622) );
NAND2X1TS U1020 ( .A(n706), .B(n716), .Y(n621) );
CLKAND2X2TS U1021 ( .A(n622), .B(n621), .Y(n987) );
INVX2TS U1022 ( .A(n987), .Y(n760) );
NAND2X1TS U1023 ( .A(n625), .B(LZA_output[2]), .Y(n826) );
NAND2X1TS U1024 ( .A(n420), .B(exp_oper_result[2]), .Y(n623) );
BUFX3TS U1025 ( .A(n704), .Y(n710) );
NAND2X1TS U1026 ( .A(n625), .B(LZA_output[1]), .Y(n828) );
NAND2X1TS U1027 ( .A(n420), .B(n433), .Y(n624) );
CLKAND2X2TS U1028 ( .A(n828), .B(n624), .Y(n653) );
INVX2TS U1029 ( .A(n653), .Y(n980) );
AOI22X1TS U1030 ( .A0(n625), .A1(LZA_output[0]), .B0(FSM_selector_B[1]),
.B1(n1029), .Y(n830) );
INVX2TS U1031 ( .A(n990), .Y(n775) );
NOR2XLTS U1032 ( .A(n991), .B(n775), .Y(n629) );
NAND3X1TS U1033 ( .A(FS_Module_state_reg[1]), .B(FS_Module_state_reg[3]),
.C(n627), .Y(n785) );
AOI31XLTS U1034 ( .A0(n999), .A1(n785), .A2(n776), .B0(n1003), .Y(n628) );
INVX2TS U1035 ( .A(n628), .Y(n992) );
OAI32X1TS U1036 ( .A0(n760), .A1(n991), .A2(n775), .B0(n629), .B1(n992), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[25]) );
INVX2TS U1037 ( .A(n630), .Y(n955) );
AOI222X1TS U1038 ( .A0(n955), .A1(n636), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[43]), .B1(FSM_selector_B[1]), .C0(n953), .C1(n635), .Y(n960) );
AOI222X1TS U1039 ( .A0(n637), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[50]), .B0(n566), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[42]), .C0(n833), .C1(
Barrel_Shifter_module_Mux_Array_Data_array[34]), .Y(n959) );
OAI2BB2XLTS U1040 ( .B0(n961), .B1(n959), .A0N(n638), .A1N(
Barrel_Shifter_module_Mux_Array_Data_array[42]), .Y(n631) );
AOI211X1TS U1041 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[50]), .A1(
n945), .B0(n640), .C0(n631), .Y(n634) );
INVX2TS U1042 ( .A(n632), .Y(n641) );
NAND2X1TS U1043 ( .A(n641), .B(
Barrel_Shifter_module_Mux_Array_Data_array[34]), .Y(n633) );
OAI211XLTS U1044 ( .A0(n960), .A1(n958), .B0(n634), .C0(n633), .Y(n1130) );
OAI22X1TS U1045 ( .A0(n1001), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[50]), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[42]), .B1(LZA_output[3]),
.Y(n839) );
INVX2TS U1046 ( .A(n839), .Y(n947) );
MXI2X2TS U1047 ( .A(n1021), .B(n1048), .S0(exp_oper_result[3]), .Y(n946) );
AOI222X1TS U1048 ( .A0(n947), .A1(n636), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[42]), .B1(FSM_selector_B[1]), .C0(n946), .C1(n635), .Y(n948) );
AOI222X1TS U1049 ( .A0(n637), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[51]), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[43]), .B1(n566), .C0(n833),
.C1(Barrel_Shifter_module_Mux_Array_Data_array[35]), .Y(n949) );
OAI2BB2XLTS U1050 ( .B0(n961), .B1(n949), .A0N(n638), .A1N(
Barrel_Shifter_module_Mux_Array_Data_array[43]), .Y(n639) );
AOI211X1TS U1051 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[51]), .A1(
n945), .B0(n640), .C0(n639), .Y(n643) );
NAND2X1TS U1052 ( .A(Barrel_Shifter_module_Mux_Array_Data_array[35]), .B(
n641), .Y(n642) );
AOI22X1TS U1053 ( .A0(n706), .A1(Add_Subt_result[10]), .B0(DmP[13]), .B1(
n705), .Y(n644) );
OAI2BB1X1TS U1054 ( .A0N(Add_Subt_result[15]), .A1N(n708), .B0(n644), .Y(
n680) );
AOI22X1TS U1055 ( .A0(n706), .A1(Add_Subt_result[6]), .B0(DmP[17]), .B1(n705), .Y(n645) );
OAI21X1TS U1056 ( .A0(n717), .A1(n1077), .B0(n645), .Y(n669) );
NAND2X2TS U1057 ( .A(n980), .B(n652), .Y(n734) );
AO22XLTS U1058 ( .A0(n706), .A1(Add_Subt_result[13]), .B0(DmP[10]), .B1(n705), .Y(n646) );
AOI21X1TS U1059 ( .A0(Add_Subt_result[12]), .A1(n708), .B0(n646), .Y(n682)
);
AO22XLTS U1060 ( .A0(n706), .A1(Add_Subt_result[9]), .B0(DmP[14]), .B1(n705),
.Y(n647) );
AOI21X1TS U1061 ( .A0(Add_Subt_result[16]), .A1(n708), .B0(n647), .Y(n660)
);
NAND2X2TS U1062 ( .A(n652), .B(n653), .Y(n767) );
AOI21X1TS U1063 ( .A0(n708), .A1(Add_Subt_result[13]), .B0(n650), .Y(n684)
);
AO22XLTS U1064 ( .A0(n706), .A1(Add_Subt_result[8]), .B0(DmP[15]), .B1(n705),
.Y(n651) );
AOI21X1TS U1065 ( .A0(n708), .A1(Add_Subt_result[17]), .B0(n651), .Y(n663)
);
AOI22X1TS U1066 ( .A0(n990), .A1(n750), .B0(n648), .B1(n749), .Y(n658) );
NOR2XLTS U1067 ( .A(n653), .B(n652), .Y(n654) );
AO22XLTS U1068 ( .A0(n706), .A1(Add_Subt_result[11]), .B0(DmP[12]), .B1(n705), .Y(n655) );
AOI21X1TS U1069 ( .A0(Add_Subt_result[14]), .A1(n708), .B0(n655), .Y(n686)
);
AO22XLTS U1070 ( .A0(n706), .A1(Add_Subt_result[7]), .B0(DmP[16]), .B1(n1045), .Y(n656) );
AOI21X1TS U1071 ( .A0(Add_Subt_result[18]), .A1(n708), .B0(n656), .Y(n671)
);
NAND2X1TS U1072 ( .A(n986), .B(n751), .Y(n657) );
OAI211XLTS U1073 ( .A0(n742), .A1(n734), .B0(n658), .C0(n657), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[12]) );
AO22XLTS U1074 ( .A0(n706), .A1(Add_Subt_result[5]), .B0(DmP[18]), .B1(n1045), .Y(n659) );
AOI21X1TS U1075 ( .A0(Add_Subt_result[20]), .A1(n708), .B0(n659), .Y(n674)
);
AOI22X1TS U1076 ( .A0(n990), .A1(n751), .B0(n986), .B1(n739), .Y(n665) );
AO22XLTS U1077 ( .A0(n706), .A1(Add_Subt_result[4]), .B0(DmP[19]), .B1(n705),
.Y(n662) );
AOI21X1TS U1078 ( .A0(n708), .A1(Add_Subt_result[21]), .B0(n662), .Y(n761)
);
NAND2X1TS U1079 ( .A(n661), .B(n738), .Y(n664) );
OAI211XLTS U1080 ( .A0(n742), .A1(n767), .B0(n665), .C0(n664), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[14]) );
INVX2TS U1081 ( .A(n986), .Y(n737) );
AOI22X1TS U1082 ( .A0(n990), .A1(n749), .B0(n648), .B1(n751), .Y(n667) );
NAND2X1TS U1083 ( .A(n661), .B(n739), .Y(n666) );
OAI211XLTS U1084 ( .A0(n742), .A1(n737), .B0(n667), .C0(n666), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[13]) );
AOI22X1TS U1085 ( .A0(n706), .A1(Add_Subt_result[2]), .B0(DmP[21]), .B1(n705), .Y(n668) );
AOI22X1TS U1086 ( .A0(n706), .A1(Add_Subt_result[3]), .B0(DmP[20]), .B1(n705), .Y(n670) );
AOI2BB2X2TS U1087 ( .B0(n704), .B1(n671), .A0N(n989), .A1N(n710), .Y(n764)
);
AOI22X1TS U1088 ( .A0(n990), .A1(n738), .B0(n648), .B1(n764), .Y(n676) );
AOI22X1TS U1089 ( .A0(n706), .A1(Add_Subt_result[1]), .B0(DmP[22]), .B1(n705), .Y(n672) );
AOI2BB2X2TS U1090 ( .B0(n704), .B1(n674), .A0N(n985), .A1N(n704), .Y(n771)
);
NAND2X1TS U1091 ( .A(n661), .B(n771), .Y(n675) );
OAI211XLTS U1092 ( .A0(n434), .A1(n737), .B0(n676), .C0(n675), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[17]) );
AOI22X1TS U1093 ( .A0(n990), .A1(n739), .B0(n648), .B1(n738), .Y(n678) );
NAND2X1TS U1094 ( .A(n986), .B(n764), .Y(n677) );
AOI22X1TS U1095 ( .A0(n706), .A1(Add_Subt_result[14]), .B0(DmP[9]), .B1(n705), .Y(n679) );
OAI2BB1X1TS U1096 ( .A0N(Add_Subt_result[11]), .A1N(n708), .B0(n679), .Y(
n690) );
AO22XLTS U1097 ( .A0(n706), .A1(Add_Subt_result[17]), .B0(DmP[6]), .B1(n705),
.Y(n681) );
AOI21X1TS U1098 ( .A0(Add_Subt_result[8]), .A1(n708), .B0(n681), .Y(n703) );
AO22XLTS U1099 ( .A0(n706), .A1(Add_Subt_result[16]), .B0(DmP[7]), .B1(n705),
.Y(n683) );
AOI21X1TS U1100 ( .A0(n708), .A1(Add_Subt_result[9]), .B0(n683), .Y(n726) );
AOI22X1TS U1101 ( .A0(n990), .A1(n744), .B0(n648), .B1(n743), .Y(n688) );
AO22XLTS U1102 ( .A0(n706), .A1(Add_Subt_result[15]), .B0(DmP[8]), .B1(n705),
.Y(n685) );
AOI21X1TS U1103 ( .A0(Add_Subt_result[10]), .A1(n708), .B0(n685), .Y(n692)
);
NAND2X1TS U1104 ( .A(n986), .B(n745), .Y(n687) );
OAI211XLTS U1105 ( .A0(n754), .A1(n734), .B0(n688), .C0(n687), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[8]) );
AOI22X1TS U1106 ( .A0(n706), .A1(Add_Subt_result[18]), .B0(DmP[5]), .B1(n705), .Y(n689) );
OAI2BB1X1TS U1107 ( .A0N(Add_Subt_result[7]), .A1N(n708), .B0(n689), .Y(n696) );
AO22XLTS U1108 ( .A0(n706), .A1(Add_Subt_result[19]), .B0(DmP[4]), .B1(n705),
.Y(n691) );
AOI21X1TS U1109 ( .A0(Add_Subt_result[6]), .A1(n708), .B0(n691), .Y(n698) );
AOI22X1TS U1110 ( .A0(n990), .A1(n756), .B0(n986), .B1(n744), .Y(n694) );
NAND2X1TS U1111 ( .A(n661), .B(n743), .Y(n693) );
OAI211XLTS U1112 ( .A0(n748), .A1(n767), .B0(n694), .C0(n693), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[6]) );
AOI22X1TS U1113 ( .A0(n706), .A1(Add_Subt_result[22]), .B0(DmP[1]), .B1(n705), .Y(n695) );
OAI2BB1X1TS U1114 ( .A0N(Add_Subt_result[3]), .A1N(n708), .B0(n695), .Y(n697) );
AOI22X1TS U1115 ( .A0(n706), .A1(Add_Subt_result[23]), .B0(DmP[0]), .B1(n705), .Y(n700) );
NAND2X1TS U1116 ( .A(n708), .B(Add_Subt_result[2]), .Y(n699) );
NAND2X1TS U1117 ( .A(n706), .B(Add_Subt_result[21]), .Y(n701) );
OAI2BB1X1TS U1118 ( .A0N(DmP[2]), .A1N(n705), .B0(n701), .Y(n702) );
AOI21X1TS U1119 ( .A0(n708), .A1(Add_Subt_result[4]), .B0(n702), .Y(n714) );
AOI22X1TS U1120 ( .A0(n648), .A1(n724), .B0(n661), .B1(n436), .Y(n712) );
AOI22X1TS U1121 ( .A0(n708), .A1(Add_Subt_result[1]), .B0(n706), .B1(
Add_Subt_result[24]), .Y(n709) );
AO22XLTS U1122 ( .A0(n706), .A1(Add_Subt_result[20]), .B0(DmP[3]), .B1(n705),
.Y(n707) );
AOI21X1TS U1123 ( .A0(Add_Subt_result[5]), .A1(n708), .B0(n707), .Y(n727) );
AOI22X1TS U1124 ( .A0(n710), .A1(n709), .B0(n727), .B1(n991), .Y(n713) );
NAND2X1TS U1125 ( .A(n990), .B(n713), .Y(n711) );
OAI211XLTS U1126 ( .A0(n759), .A1(n737), .B0(n712), .C0(n711), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[1]) );
AOI22X1TS U1127 ( .A0(n648), .A1(n713), .B0(n986), .B1(n724), .Y(n721) );
INVX2TS U1128 ( .A(n714), .Y(n719) );
OAI22X1TS U1129 ( .A0(n717), .A1(n716), .B0(n1052), .B1(n715), .Y(n718) );
OAI221XLTS U1130 ( .A0(n704), .A1(n719), .B0(n725), .B1(n718), .C0(n990),
.Y(n720) );
OAI211XLTS U1131 ( .A0(n759), .A1(n734), .B0(n721), .C0(n720), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[0]) );
AOI22X1TS U1132 ( .A0(n990), .A1(n743), .B0(n648), .B1(n745), .Y(n723) );
NAND2X1TS U1133 ( .A(n661), .B(n750), .Y(n722) );
OAI211XLTS U1134 ( .A0(n754), .A1(n737), .B0(n723), .C0(n722), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[9]) );
AOI22X1TS U1135 ( .A0(n990), .A1(n724), .B0(n986), .B1(n436), .Y(n729) );
NAND2X1TS U1136 ( .A(n661), .B(n755), .Y(n728) );
AOI22X1TS U1137 ( .A0(n990), .A1(n745), .B0(n986), .B1(n750), .Y(n731) );
NAND2X1TS U1138 ( .A(n661), .B(n749), .Y(n730) );
OAI211XLTS U1139 ( .A0(n754), .A1(n767), .B0(n731), .C0(n730), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[10]) );
AOI22X1TS U1140 ( .A0(n990), .A1(n436), .B0(n648), .B1(n755), .Y(n733) );
NAND2X1TS U1141 ( .A(n986), .B(n756), .Y(n732) );
OAI211XLTS U1142 ( .A0(n748), .A1(n734), .B0(n733), .C0(n732), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[4]) );
AOI22X1TS U1143 ( .A0(n990), .A1(n755), .B0(n648), .B1(n756), .Y(n736) );
NAND2X1TS U1144 ( .A(n661), .B(n744), .Y(n735) );
OAI211XLTS U1145 ( .A0(n748), .A1(n737), .B0(n736), .C0(n735), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[5]) );
AOI22X1TS U1146 ( .A0(n648), .A1(n739), .B0(n986), .B1(n738), .Y(n741) );
NAND2X1TS U1147 ( .A(n661), .B(n764), .Y(n740) );
OAI211XLTS U1148 ( .A0(n775), .A1(n742), .B0(n741), .C0(n740), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[15]) );
AOI22X1TS U1149 ( .A0(n648), .A1(n744), .B0(n986), .B1(n743), .Y(n747) );
NAND2X1TS U1150 ( .A(n661), .B(n745), .Y(n746) );
OAI211XLTS U1151 ( .A0(n775), .A1(n748), .B0(n747), .C0(n746), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[7]) );
AOI22X1TS U1152 ( .A0(n648), .A1(n750), .B0(n986), .B1(n749), .Y(n753) );
NAND2X1TS U1153 ( .A(n661), .B(n751), .Y(n752) );
OAI211XLTS U1154 ( .A0(n775), .A1(n754), .B0(n753), .C0(n752), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[11]) );
AOI22X1TS U1155 ( .A0(n648), .A1(n436), .B0(n986), .B1(n755), .Y(n758) );
NAND2X1TS U1156 ( .A(n661), .B(n756), .Y(n757) );
OAI211XLTS U1157 ( .A0(n775), .A1(n759), .B0(n758), .C0(n757), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[3]) );
AOI22X1TS U1158 ( .A0(n990), .A1(n435), .B0(n772), .B1(n775), .Y(n762) );
OAI21XLTS U1159 ( .A0(n763), .A1(n991), .B0(n762), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[21]) );
AOI22X1TS U1160 ( .A0(n990), .A1(n764), .B0(n986), .B1(n771), .Y(n766) );
NAND2X1TS U1161 ( .A(n661), .B(n435), .Y(n765) );
OAI211XLTS U1162 ( .A0(n434), .A1(n767), .B0(n766), .C0(n765), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[18]) );
AOI22X1TS U1163 ( .A0(n986), .A1(n989), .B0(n661), .B1(n988), .Y(n770) );
AOI22X1TS U1164 ( .A0(n990), .A1(n771), .B0(n648), .B1(n435), .Y(n769) );
NAND2X1TS U1165 ( .A(n772), .B(n980), .Y(n768) );
OAI211XLTS U1166 ( .A0(n770), .A1(n991), .B0(n769), .C0(n768), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[20]) );
AOI22X1TS U1167 ( .A0(n648), .A1(n771), .B0(n986), .B1(n435), .Y(n774) );
OAI211XLTS U1168 ( .A0(n775), .A1(n434), .B0(n774), .C0(n773), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[19]) );
OAI21X1TS U1169 ( .A0(FS_Module_state_reg[0]), .A1(n776), .B0(n785), .Y(n783) );
INVX2TS U1170 ( .A(n783), .Y(n778) );
OR4X2TS U1171 ( .A(Exp_Operation_Module_Data_S[2]), .B(
Exp_Operation_Module_Data_S[1]), .C(Exp_Operation_Module_Data_S[0]),
.D(n778), .Y(n779) );
OR4X2TS U1172 ( .A(Exp_Operation_Module_Data_S[5]), .B(
Exp_Operation_Module_Data_S[4]), .C(Exp_Operation_Module_Data_S[3]),
.D(n779), .Y(n780) );
OR4X2TS U1173 ( .A(n781), .B(Exp_Operation_Module_Data_S[7]), .C(
Exp_Operation_Module_Data_S[6]), .D(n780), .Y(n782) );
OAI21XLTS U1174 ( .A0(n1093), .A1(n783), .B0(n782), .Y(n401) );
MX2X1TS U1175 ( .A(DMP[24]), .B(n433), .S0(n853), .Y(S_Oper_A_exp[1]) );
NOR4BX1TS U1176 ( .AN(n785), .B(FSM_Add_Subt_Sgf_load), .C(
FSM_Final_Result_load), .D(n784), .Y(n788) );
NAND2X1TS U1177 ( .A(n786), .B(n413), .Y(n787) );
OR2X1TS U1178 ( .A(n791), .B(n853), .Y(n406) );
OAI2BB2XLTS U1179 ( .B0(n967), .B1(n792), .A0N(
Barrel_Shifter_module_Mux_Array_Data_array[50]), .A1N(n840), .Y(n1118)
);
NOR2BX1TS U1180 ( .AN(Sgf_normalized_result[25]), .B(n853), .Y(n793) );
XOR2X1TS U1181 ( .A(n1097), .B(n793), .Y(DP_OP_45J178_125_5354_n31) );
NOR2BX1TS U1182 ( .AN(Sgf_normalized_result[24]), .B(n853), .Y(n794) );
XOR2X1TS U1183 ( .A(n1097), .B(n794), .Y(DP_OP_45J178_125_5354_n32) );
NOR2BX1TS U1184 ( .AN(Sgf_normalized_result[23]), .B(n832), .Y(n795) );
XOR2X1TS U1185 ( .A(n1097), .B(n795), .Y(DP_OP_45J178_125_5354_n33) );
NOR2BX1TS U1186 ( .AN(Sgf_normalized_result[22]), .B(n853), .Y(n796) );
XOR2X1TS U1187 ( .A(n1097), .B(n796), .Y(DP_OP_45J178_125_5354_n34) );
NOR2BX1TS U1188 ( .AN(Sgf_normalized_result[21]), .B(n853), .Y(n797) );
XOR2X1TS U1189 ( .A(n1097), .B(n797), .Y(DP_OP_45J178_125_5354_n35) );
NOR2BX1TS U1190 ( .AN(Sgf_normalized_result[20]), .B(n832), .Y(n798) );
XOR2X1TS U1191 ( .A(n1097), .B(n798), .Y(DP_OP_45J178_125_5354_n36) );
NOR2BX1TS U1192 ( .AN(Sgf_normalized_result[19]), .B(n853), .Y(n799) );
XOR2X1TS U1193 ( .A(n1097), .B(n799), .Y(DP_OP_45J178_125_5354_n37) );
NOR2BX1TS U1194 ( .AN(Sgf_normalized_result[18]), .B(n853), .Y(n800) );
XOR2X1TS U1195 ( .A(n1097), .B(n800), .Y(DP_OP_45J178_125_5354_n38) );
NOR2BX1TS U1196 ( .AN(Sgf_normalized_result[17]), .B(n853), .Y(n801) );
XOR2X1TS U1197 ( .A(n1097), .B(n801), .Y(DP_OP_45J178_125_5354_n39) );
NOR2BX1TS U1198 ( .AN(Sgf_normalized_result[16]), .B(n853), .Y(n802) );
XOR2X1TS U1199 ( .A(n1097), .B(n802), .Y(DP_OP_45J178_125_5354_n40) );
NOR2BX1TS U1200 ( .AN(Sgf_normalized_result[15]), .B(n853), .Y(n803) );
XOR2X1TS U1201 ( .A(n1097), .B(n803), .Y(DP_OP_45J178_125_5354_n41) );
NOR2BX1TS U1202 ( .AN(Sgf_normalized_result[14]), .B(n832), .Y(n804) );
XOR2X1TS U1203 ( .A(n1097), .B(n804), .Y(DP_OP_45J178_125_5354_n42) );
NOR2BX1TS U1204 ( .AN(Sgf_normalized_result[13]), .B(n832), .Y(n805) );
XOR2X1TS U1205 ( .A(n1097), .B(n805), .Y(DP_OP_45J178_125_5354_n43) );
NOR2BX1TS U1206 ( .AN(Sgf_normalized_result[12]), .B(n832), .Y(n806) );
XOR2X1TS U1207 ( .A(n1097), .B(n806), .Y(DP_OP_45J178_125_5354_n44) );
NOR2BX1TS U1208 ( .AN(Sgf_normalized_result[11]), .B(n853), .Y(n807) );
XOR2X1TS U1209 ( .A(n1097), .B(n807), .Y(DP_OP_45J178_125_5354_n45) );
NOR2BX1TS U1210 ( .AN(Sgf_normalized_result[10]), .B(n832), .Y(n808) );
XOR2X1TS U1211 ( .A(n1097), .B(n808), .Y(DP_OP_45J178_125_5354_n46) );
NOR2BX1TS U1212 ( .AN(Sgf_normalized_result[9]), .B(n832), .Y(n809) );
XOR2X1TS U1213 ( .A(n1097), .B(n809), .Y(DP_OP_45J178_125_5354_n47) );
NOR2BX1TS U1214 ( .AN(Sgf_normalized_result[8]), .B(n832), .Y(n810) );
XOR2X1TS U1215 ( .A(n814), .B(n810), .Y(DP_OP_45J178_125_5354_n48) );
NOR2BX1TS U1216 ( .AN(Sgf_normalized_result[7]), .B(n832), .Y(n811) );
XOR2X1TS U1217 ( .A(n814), .B(n811), .Y(DP_OP_45J178_125_5354_n49) );
NOR2BX1TS U1218 ( .AN(Sgf_normalized_result[6]), .B(n832), .Y(n812) );
XOR2X1TS U1219 ( .A(n814), .B(n812), .Y(DP_OP_45J178_125_5354_n50) );
NOR2BX1TS U1220 ( .AN(Sgf_normalized_result[5]), .B(n832), .Y(n813) );
XOR2X1TS U1221 ( .A(n814), .B(n813), .Y(DP_OP_45J178_125_5354_n51) );
NOR2BX1TS U1222 ( .AN(Sgf_normalized_result[4]), .B(n832), .Y(n815) );
XOR2X1TS U1223 ( .A(n1097), .B(n815), .Y(DP_OP_45J178_125_5354_n52) );
NOR2BX1TS U1224 ( .AN(Sgf_normalized_result[3]), .B(n832), .Y(n816) );
XOR2X1TS U1225 ( .A(n1097), .B(n816), .Y(DP_OP_45J178_125_5354_n53) );
OR2X1TS U1226 ( .A(n832), .B(Sgf_normalized_result[2]), .Y(n817) );
XOR2X1TS U1227 ( .A(n1097), .B(n817), .Y(DP_OP_45J178_125_5354_n54) );
NOR2BX1TS U1228 ( .AN(Sgf_normalized_result[1]), .B(n832), .Y(n818) );
XOR2X1TS U1229 ( .A(n1097), .B(n818), .Y(DP_OP_45J178_125_5354_n55) );
NOR2BX1TS U1230 ( .AN(Sgf_normalized_result[0]), .B(n832), .Y(n819) );
XOR2X1TS U1231 ( .A(n1097), .B(n819), .Y(DP_OP_45J178_125_5354_n56) );
CLKAND2X2TS U1232 ( .A(n420), .B(DmP[30]), .Y(n820) );
XOR2X1TS U1233 ( .A(n1096), .B(n820), .Y(DP_OP_42J178_122_8048_n13) );
CLKAND2X2TS U1234 ( .A(n420), .B(DmP[29]), .Y(n821) );
XOR2X1TS U1235 ( .A(n1096), .B(n821), .Y(DP_OP_42J178_122_8048_n14) );
CLKAND2X2TS U1236 ( .A(n420), .B(DmP[28]), .Y(n822) );
XOR2X1TS U1237 ( .A(n1096), .B(n822), .Y(DP_OP_42J178_122_8048_n15) );
OAI2BB1X1TS U1238 ( .A0N(n420), .A1N(DmP[27]), .B0(n838), .Y(n823) );
XOR2X1TS U1239 ( .A(n1096), .B(n823), .Y(DP_OP_42J178_122_8048_n16) );
OAI2BB2XLTS U1240 ( .B0(n824), .B1(n1001), .A0N(n420), .A1N(DmP[26]), .Y(
n825) );
XOR2X1TS U1241 ( .A(n1096), .B(n825), .Y(DP_OP_42J178_122_8048_n17) );
OAI2BB1X1TS U1242 ( .A0N(n420), .A1N(DmP[25]), .B0(n826), .Y(n827) );
XOR2X1TS U1243 ( .A(n1096), .B(n827), .Y(DP_OP_42J178_122_8048_n18) );
OAI2BB1X1TS U1244 ( .A0N(n420), .A1N(DmP[24]), .B0(n828), .Y(n829) );
XOR2X1TS U1245 ( .A(n1096), .B(n829), .Y(DP_OP_42J178_122_8048_n19) );
OAI2BB1X1TS U1246 ( .A0N(DmP[23]), .A1N(n1029), .B0(n830), .Y(n831) );
XOR2X1TS U1247 ( .A(n1096), .B(n831), .Y(DP_OP_42J178_122_8048_n20) );
NAND2BXLTS U1248 ( .AN(Sgf_normalized_result[25]), .B(n832), .Y(
S_A_S_Oper_A[25]) );
MX2X1TS U1249 ( .A(DMP[22]), .B(Sgf_normalized_result[24]), .S0(n853), .Y(
S_A_S_Oper_A[24]) );
MX2X1TS U1250 ( .A(DMP[21]), .B(Sgf_normalized_result[23]), .S0(n853), .Y(
S_A_S_Oper_A[23]) );
MX2X1TS U1251 ( .A(DMP[20]), .B(Sgf_normalized_result[22]), .S0(n853), .Y(
S_A_S_Oper_A[22]) );
MX2X1TS U1252 ( .A(DMP[19]), .B(Sgf_normalized_result[21]), .S0(n854), .Y(
S_A_S_Oper_A[21]) );
MX2X1TS U1253 ( .A(DMP[18]), .B(Sgf_normalized_result[20]), .S0(n854), .Y(
S_A_S_Oper_A[20]) );
MX2X1TS U1254 ( .A(DMP[17]), .B(Sgf_normalized_result[19]), .S0(n854), .Y(
S_A_S_Oper_A[19]) );
MX2X1TS U1255 ( .A(DMP[16]), .B(Sgf_normalized_result[18]), .S0(n854), .Y(
S_A_S_Oper_A[18]) );
MX2X1TS U1256 ( .A(DMP[15]), .B(Sgf_normalized_result[17]), .S0(n854), .Y(
S_A_S_Oper_A[17]) );
MX2X1TS U1257 ( .A(DMP[14]), .B(Sgf_normalized_result[16]), .S0(n854), .Y(
S_A_S_Oper_A[16]) );
MX2X1TS U1258 ( .A(DMP[13]), .B(Sgf_normalized_result[15]), .S0(n854), .Y(
S_A_S_Oper_A[15]) );
MX2X1TS U1259 ( .A(DMP[12]), .B(Sgf_normalized_result[14]), .S0(n854), .Y(
S_A_S_Oper_A[14]) );
MX2X1TS U1260 ( .A(DMP[11]), .B(Sgf_normalized_result[13]), .S0(n854), .Y(
S_A_S_Oper_A[13]) );
MX2X1TS U1261 ( .A(DMP[10]), .B(Sgf_normalized_result[12]), .S0(n854), .Y(
S_A_S_Oper_A[12]) );
MX2X1TS U1262 ( .A(DMP[9]), .B(Sgf_normalized_result[11]), .S0(n854), .Y(
S_A_S_Oper_A[11]) );
MX2X1TS U1263 ( .A(DMP[8]), .B(Sgf_normalized_result[10]), .S0(n854), .Y(
S_A_S_Oper_A[10]) );
MX2X1TS U1264 ( .A(DMP[7]), .B(Sgf_normalized_result[9]), .S0(n854), .Y(
S_A_S_Oper_A[9]) );
MX2X1TS U1265 ( .A(DMP[6]), .B(Sgf_normalized_result[8]), .S0(n854), .Y(
S_A_S_Oper_A[8]) );
MX2X1TS U1266 ( .A(DMP[5]), .B(Sgf_normalized_result[7]), .S0(n854), .Y(
S_A_S_Oper_A[7]) );
MX2X1TS U1267 ( .A(DMP[4]), .B(Sgf_normalized_result[6]), .S0(n854), .Y(
S_A_S_Oper_A[6]) );
MX2X1TS U1268 ( .A(DMP[3]), .B(Sgf_normalized_result[5]), .S0(n854), .Y(
S_A_S_Oper_A[5]) );
MX2X1TS U1269 ( .A(DMP[2]), .B(Sgf_normalized_result[4]), .S0(n854), .Y(
S_A_S_Oper_A[4]) );
MX2X1TS U1270 ( .A(DMP[1]), .B(Sgf_normalized_result[3]), .S0(n854), .Y(
S_A_S_Oper_A[3]) );
MX2X1TS U1271 ( .A(DMP[0]), .B(Sgf_normalized_result[2]), .S0(n854), .Y(
S_A_S_Oper_A[2]) );
CLKAND2X2TS U1272 ( .A(n853), .B(Sgf_normalized_result[1]), .Y(
S_A_S_Oper_A[1]) );
AOI22X1TS U1273 ( .A0(n834), .A1(n946), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[26]), .B1(n833), .Y(n837)
);
OAI21XLTS U1274 ( .A0(n835), .A1(n566), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[34]), .Y(n836) );
OAI211X1TS U1275 ( .A0(n839), .A1(n838), .B0(n837), .C0(n836), .Y(n966) );
AO22XLTS U1276 ( .A0(n966), .A1(n958), .B0(n840), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[51]), .Y(n1139) );
CLKAND2X2TS U1277 ( .A(n853), .B(Sgf_normalized_result[0]), .Y(
S_A_S_Oper_A[0]) );
AOI21X1TS U1278 ( .A0(n842), .A1(n1060), .B0(n841), .Y(n843) );
AOI31XLTS U1279 ( .A0(n845), .A1(n844), .A2(n1059), .B0(n843), .Y(n846) );
NAND3XLTS U1280 ( .A(n848), .B(n847), .C(n846), .Y(
Leading_Zero_Detector_Module_Codec_to_Reg[3]) );
AOI22X1TS U1281 ( .A0(n1029), .A1(n852), .B0(add_overflow_flag), .B1(n850),
.Y(n405) );
NOR3BX1TS U1282 ( .AN(n850), .B(FS_Module_state_reg[1]), .C(
add_overflow_flag), .Y(n851) );
AOI21X1TS U1283 ( .A0(n852), .A1(n440), .B0(n851), .Y(n404) );
MX2X1TS U1284 ( .A(DMP[30]), .B(exp_oper_result[7]), .S0(n853), .Y(
S_Oper_A_exp[7]) );
MX2X1TS U1285 ( .A(DMP[29]), .B(exp_oper_result[6]), .S0(n853), .Y(
S_Oper_A_exp[6]) );
MX2X1TS U1286 ( .A(DMP[28]), .B(exp_oper_result[5]), .S0(n853), .Y(
S_Oper_A_exp[5]) );
MX2X1TS U1287 ( .A(DMP[27]), .B(exp_oper_result[4]), .S0(n853), .Y(
S_Oper_A_exp[4]) );
MX2X1TS U1288 ( .A(DMP[26]), .B(exp_oper_result[3]), .S0(n853), .Y(
S_Oper_A_exp[3]) );
MX2X1TS U1289 ( .A(DMP[25]), .B(exp_oper_result[2]), .S0(n854), .Y(
S_Oper_A_exp[2]) );
MX2X1TS U1290 ( .A(DMP[23]), .B(exp_oper_result[0]), .S0(n854), .Y(
S_Oper_A_exp[0]) );
OAI31X1TS U1291 ( .A0(n1077), .A1(Add_Subt_result[21]), .A2(
Add_Subt_result[20]), .B0(n855), .Y(n858) );
OAI211XLTS U1292 ( .A0(Add_Subt_result[15]), .A1(Add_Subt_result[14]), .B0(
n1017), .C0(n1076), .Y(n856) );
AOI2BB2XLTS U1293 ( .B0(n859), .B1(n858), .A0N(n857), .A1N(n856), .Y(n862)
);
NAND4XLTS U1294 ( .A(n860), .B(Add_Subt_result[11]), .C(n1061), .D(n1022),
.Y(n861) );
NAND4BXLTS U1295 ( .AN(n864), .B(n863), .C(n862), .D(n861), .Y(
Leading_Zero_Detector_Module_Codec_to_Reg[1]) );
NAND2BXLTS U1296 ( .AN(exp_oper_result[7]), .B(n997), .Y(
final_result_ieee_Module_Exp_S_mux[7]) );
NAND2BXLTS U1297 ( .AN(exp_oper_result[6]), .B(n997), .Y(
final_result_ieee_Module_Exp_S_mux[6]) );
NAND2BXLTS U1298 ( .AN(exp_oper_result[5]), .B(n997), .Y(
final_result_ieee_Module_Exp_S_mux[5]) );
NAND2X1TS U1299 ( .A(n997), .B(n1044), .Y(
final_result_ieee_Module_Exp_S_mux[4]) );
NAND2X1TS U1300 ( .A(n997), .B(n1031), .Y(
final_result_ieee_Module_Exp_S_mux[3]) );
NAND2BXLTS U1301 ( .AN(exp_oper_result[2]), .B(n997), .Y(
final_result_ieee_Module_Exp_S_mux[2]) );
NAND2BXLTS U1302 ( .AN(n433), .B(n997), .Y(
final_result_ieee_Module_Exp_S_mux[1]) );
NAND2BXLTS U1303 ( .AN(exp_oper_result[0]), .B(n997), .Y(
final_result_ieee_Module_Exp_S_mux[0]) );
XNOR2X1TS U1304 ( .A(add_subt), .B(Data_Y[31]), .Y(n1095) );
NOR2X1TS U1305 ( .A(n1086), .B(intDX[25]), .Y(n924) );
NOR2XLTS U1306 ( .A(n924), .B(intDY[24]), .Y(n865) );
AOI22X1TS U1307 ( .A0(intDX[25]), .A1(n1086), .B0(intDX[24]), .B1(n865), .Y(
n869) );
OAI21X1TS U1308 ( .A0(intDX[26]), .A1(n1089), .B0(n866), .Y(n925) );
NAND2BXLTS U1309 ( .AN(intDY[27]), .B(intDX[27]), .Y(n867) );
NOR2X1TS U1310 ( .A(n1018), .B(intDX[30]), .Y(n872) );
NOR2X1TS U1311 ( .A(n1083), .B(intDX[29]), .Y(n870) );
AOI211X1TS U1312 ( .A0(intDY[28]), .A1(n1098), .B0(n872), .C0(n870), .Y(n923) );
AOI2BB2X1TS U1313 ( .B0(n874), .B1(n923), .A0N(n873), .A1N(n872), .Y(n929)
);
NOR2X1TS U1314 ( .A(n1085), .B(intDX[17]), .Y(n910) );
NAND2BXLTS U1315 ( .AN(intDX[9]), .B(intDY[9]), .Y(n891) );
OAI211XLTS U1316 ( .A0(intDX[8]), .A1(n1084), .B0(n891), .C0(n894), .Y(n905)
);
OAI2BB1X1TS U1317 ( .A0N(n1046), .A1N(intDY[5]), .B0(intDX[4]), .Y(n875) );
OAI22X1TS U1318 ( .A0(intDY[4]), .A1(n875), .B0(n1046), .B1(intDY[5]), .Y(
n886) );
OAI2BB1X1TS U1319 ( .A0N(n1099), .A1N(intDY[7]), .B0(intDX[6]), .Y(n876) );
OAI22X1TS U1320 ( .A0(intDY[6]), .A1(n876), .B0(n1099), .B1(intDY[7]), .Y(
n885) );
OAI21XLTS U1321 ( .A0(intDX[1]), .A1(n1087), .B0(intDX[0]), .Y(n877) );
OAI2BB2XLTS U1322 ( .B0(intDY[0]), .B1(n877), .A0N(intDX[1]), .A1N(n1087),
.Y(n879) );
NAND2BXLTS U1323 ( .AN(intDX[2]), .B(intDY[2]), .Y(n878) );
OAI211XLTS U1324 ( .A0(n1088), .A1(intDX[3]), .B0(n879), .C0(n878), .Y(n882)
);
OAI21XLTS U1325 ( .A0(intDX[3]), .A1(n1088), .B0(intDX[2]), .Y(n880) );
AOI2BB2XLTS U1326 ( .B0(intDX[3]), .B1(n1088), .A0N(intDY[2]), .A1N(n880),
.Y(n881) );
AOI222X1TS U1327 ( .A0(intDY[4]), .A1(n1014), .B0(n882), .B1(n881), .C0(
intDY[5]), .C1(n1046), .Y(n884) );
OAI32X1TS U1328 ( .A0(n886), .A1(n885), .A2(n884), .B0(n883), .B1(n885), .Y(
n904) );
OA22X1TS U1329 ( .A0(n1025), .A1(intDX[14]), .B0(n1090), .B1(intDX[15]), .Y(
n901) );
NAND2BXLTS U1330 ( .AN(intDX[13]), .B(intDY[13]), .Y(n887) );
OAI21XLTS U1331 ( .A0(intDX[13]), .A1(n1068), .B0(intDX[12]), .Y(n888) );
OAI2BB2XLTS U1332 ( .B0(intDY[12]), .B1(n888), .A0N(intDX[13]), .A1N(n1068),
.Y(n900) );
NOR2XLTS U1333 ( .A(n889), .B(intDY[10]), .Y(n890) );
AOI22X1TS U1334 ( .A0(intDX[11]), .A1(n1081), .B0(intDX[10]), .B1(n890), .Y(
n896) );
NAND2BXLTS U1335 ( .AN(intDY[9]), .B(intDX[9]), .Y(n893) );
NAND3XLTS U1336 ( .A(n1084), .B(n891), .C(intDX[8]), .Y(n892) );
AOI21X1TS U1337 ( .A0(n893), .A1(n892), .B0(n903), .Y(n895) );
OAI2BB2XLTS U1338 ( .B0(intDY[14]), .B1(n897), .A0N(intDX[15]), .A1N(n1090),
.Y(n898) );
AOI211X1TS U1339 ( .A0(n901), .A1(n900), .B0(n899), .C0(n898), .Y(n902) );
OAI31X1TS U1340 ( .A0(n905), .A1(n904), .A2(n903), .B0(n902), .Y(n908) );
OA22X1TS U1341 ( .A0(n1026), .A1(intDX[22]), .B0(n1091), .B1(intDX[23]), .Y(
n921) );
NAND2BXLTS U1342 ( .AN(intDX[21]), .B(intDY[21]), .Y(n906) );
NAND2BXLTS U1343 ( .AN(intDX[19]), .B(intDY[19]), .Y(n912) );
OAI21X1TS U1344 ( .A0(intDX[18]), .A1(n1082), .B0(n912), .Y(n916) );
NAND3BXLTS U1345 ( .AN(n910), .B(n908), .C(n907), .Y(n928) );
OAI21XLTS U1346 ( .A0(intDX[21]), .A1(n1069), .B0(intDX[20]), .Y(n909) );
OAI2BB2XLTS U1347 ( .B0(intDY[20]), .B1(n909), .A0N(intDX[21]), .A1N(n1069),
.Y(n920) );
AOI22X1TS U1348 ( .A0(intDX[17]), .A1(n1085), .B0(intDX[16]), .B1(n911), .Y(
n914) );
AOI32X1TS U1349 ( .A0(n1082), .A1(n912), .A2(intDX[18]), .B0(intDX[19]),
.B1(n1024), .Y(n913) );
OAI32X1TS U1350 ( .A0(n916), .A1(n915), .A2(n914), .B0(n913), .B1(n915), .Y(
n919) );
OAI2BB2XLTS U1351 ( .B0(intDY[22]), .B1(n917), .A0N(intDX[23]), .A1N(n1091),
.Y(n918) );
AOI211X1TS U1352 ( .A0(n921), .A1(n920), .B0(n919), .C0(n918), .Y(n927) );
NAND2BXLTS U1353 ( .AN(intDX[24]), .B(intDY[24]), .Y(n922) );
NAND4BBX1TS U1354 ( .AN(n925), .BN(n924), .C(n923), .D(n922), .Y(n926) );
AOI32X1TS U1355 ( .A0(n929), .A1(n928), .A2(n927), .B0(n926), .B1(n929), .Y(
n930) );
AOI21X1TS U1356 ( .A0(n931), .A1(n971), .B0(intDX[31]), .Y(n932) );
AOI21X1TS U1357 ( .A0(n1111), .A1(n972), .B0(n932), .Y(n1113) );
OAI22X1TS U1358 ( .A0(n935), .A1(n934), .B0(n1054), .B1(n933), .Y(n944) );
AOI22X1TS U1359 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[38]), .A1(
n431), .B0(n954), .B1(n937), .Y(n941) );
AOI22X1TS U1360 ( .A0(n956), .A1(n939), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[39]), .B1(n938), .Y(n940)
);
OAI211XLTS U1361 ( .A0(n961), .A1(n942), .B0(n941), .C0(n940), .Y(n943) );
OR3X1TS U1362 ( .A(n945), .B(n944), .C(n943), .Y(n1138) );
AOI22X1TS U1363 ( .A0(n956), .A1(n947), .B0(n954), .B1(n946), .Y(n952) );
AOI22X1TS U1364 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[43]), .A1(
n957), .B0(Barrel_Shifter_module_Mux_Array_Data_array[42]), .B1(n431),
.Y(n951) );
OA22X1TS U1365 ( .A0(n949), .A1(n958), .B0(n961), .B1(n948), .Y(n950) );
NAND4XLTS U1366 ( .A(n952), .B(n951), .C(n950), .D(n962), .Y(n1131) );
AOI22X1TS U1367 ( .A0(n956), .A1(n955), .B0(n954), .B1(n953), .Y(n965) );
AOI22X1TS U1368 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[43]), .A1(
n431), .B0(Barrel_Shifter_module_Mux_Array_Data_array[42]), .B1(n957),
.Y(n964) );
OA22X1TS U1369 ( .A0(n961), .A1(n960), .B0(n959), .B1(n958), .Y(n963) );
NAND4XLTS U1370 ( .A(n965), .B(n964), .C(n963), .D(n962), .Y(n1129) );
AOI22X1TS U1371 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[51]), .A1(
n968), .B0(n967), .B1(n966), .Y(n969) );
NAND2BXLTS U1372 ( .AN(n970), .B(n969), .Y(n1114) );
AOI21X1TS U1373 ( .A0(n439), .A1(n1093), .B0(overflow_flag), .Y(
final_result_ieee_Module_Sign_S_mux) );
INVX4TS U1374 ( .A(n971), .Y(n974) );
AOI22X1TS U1375 ( .A0(n974), .A1(n1092), .B0(n1015), .B1(n971), .Y(
Oper_Start_in_module_intm[0]) );
INVX4TS U1376 ( .A(n971), .Y(n976) );
AOI22X1TS U1377 ( .A0(n976), .A1(n1087), .B0(n1032), .B1(n971), .Y(
Oper_Start_in_module_intm[1]) );
AOI22X1TS U1378 ( .A0(n976), .A1(n1070), .B0(n1012), .B1(n971), .Y(
Oper_Start_in_module_intm[2]) );
AOI22X1TS U1379 ( .A0(n974), .A1(n1088), .B0(n1034), .B1(n972), .Y(
Oper_Start_in_module_intm[3]) );
BUFX3TS U1380 ( .A(n972), .Y(n978) );
AOI22X1TS U1381 ( .A0(n973), .A1(n1066), .B0(n1014), .B1(n978), .Y(
Oper_Start_in_module_intm[4]) );
AOI22X1TS U1382 ( .A0(n974), .A1(n1062), .B0(n1046), .B1(n972), .Y(
Oper_Start_in_module_intm[5]) );
AOI22X1TS U1383 ( .A0(n973), .A1(n1079), .B0(n1019), .B1(n971), .Y(
Oper_Start_in_module_intm[6]) );
AOI22X1TS U1384 ( .A0(n973), .A1(n1072), .B0(n1099), .B1(n978), .Y(
Oper_Start_in_module_intm[7]) );
AOI22X1TS U1385 ( .A0(n973), .A1(n1084), .B0(n1035), .B1(n972), .Y(
Oper_Start_in_module_intm[8]) );
AOI22X1TS U1386 ( .A0(n973), .A1(n1073), .B0(n1004), .B1(n972), .Y(
Oper_Start_in_module_intm[9]) );
AOI22X1TS U1387 ( .A0(n973), .A1(n1080), .B0(n1011), .B1(n972), .Y(
Oper_Start_in_module_intm[10]) );
AOI22X1TS U1388 ( .A0(n973), .A1(n1081), .B0(n1030), .B1(n972), .Y(
Oper_Start_in_module_intm[11]) );
AOI22X1TS U1389 ( .A0(n973), .A1(n1036), .B0(n1065), .B1(n972), .Y(
Oper_Start_in_module_intm[12]) );
AOI22X1TS U1390 ( .A0(n973), .A1(n1068), .B0(n1040), .B1(n972), .Y(
Oper_Start_in_module_intm[13]) );
AOI22X1TS U1391 ( .A0(n973), .A1(n1025), .B0(n1005), .B1(n972), .Y(
Oper_Start_in_module_intm[14]) );
AOI22X1TS U1392 ( .A0(n973), .A1(n1090), .B0(n1041), .B1(n972), .Y(
Oper_Start_in_module_intm[15]) );
AOI22X1TS U1393 ( .A0(n973), .A1(n1064), .B0(n1053), .B1(n972), .Y(
Oper_Start_in_module_intm[16]) );
AOI22X1TS U1394 ( .A0(n973), .A1(n1085), .B0(n1037), .B1(n972), .Y(
Oper_Start_in_module_intm[17]) );
AOI22X1TS U1395 ( .A0(n973), .A1(n1082), .B0(n1006), .B1(n972), .Y(
Oper_Start_in_module_intm[18]) );
AOI22X1TS U1396 ( .A0(n973), .A1(n1024), .B0(n1038), .B1(n972), .Y(
Oper_Start_in_module_intm[19]) );
AOI22X1TS U1397 ( .A0(n973), .A1(n1071), .B0(n1007), .B1(n972), .Y(
Oper_Start_in_module_intm[20]) );
AOI22X1TS U1398 ( .A0(n973), .A1(n1069), .B0(n1042), .B1(n972), .Y(
Oper_Start_in_module_intm[21]) );
AOI22X1TS U1399 ( .A0(n973), .A1(n1026), .B0(n1008), .B1(n972), .Y(
Oper_Start_in_module_intm[22]) );
AOI22X1TS U1400 ( .A0(n973), .A1(n1091), .B0(n1043), .B1(n972), .Y(
Oper_Start_in_module_intm[23]) );
AOI22X1TS U1401 ( .A0(n973), .A1(n1067), .B0(n1009), .B1(n972), .Y(
Oper_Start_in_module_intm[24]) );
AOI22X1TS U1402 ( .A0(n973), .A1(n1086), .B0(n1039), .B1(n972), .Y(
Oper_Start_in_module_intm[25]) );
AOI22X1TS U1403 ( .A0(n976), .A1(n1089), .B0(n1010), .B1(n972), .Y(
Oper_Start_in_module_intm[26]) );
AOI22X1TS U1404 ( .A0(n974), .A1(n1074), .B0(n1013), .B1(n972), .Y(
Oper_Start_in_module_intm[27]) );
AOI22X1TS U1405 ( .A0(n976), .A1(n1063), .B0(n1098), .B1(n978), .Y(
Oper_Start_in_module_intm[28]) );
AOI22X1TS U1406 ( .A0(n974), .A1(n1083), .B0(n1033), .B1(n978), .Y(
Oper_Start_in_module_intm[29]) );
AOI22X1TS U1407 ( .A0(n976), .A1(n1018), .B0(n1047), .B1(n978), .Y(
Oper_Start_in_module_intm[30]) );
AOI22X1TS U1408 ( .A0(n974), .A1(n1015), .B0(n1092), .B1(n978), .Y(
Oper_Start_in_module_intM[0]) );
AOI22X1TS U1409 ( .A0(n976), .A1(n1032), .B0(n1087), .B1(n978), .Y(
Oper_Start_in_module_intM[1]) );
AOI22X1TS U1410 ( .A0(n974), .A1(n1012), .B0(n1070), .B1(n978), .Y(
Oper_Start_in_module_intM[2]) );
AOI22X1TS U1411 ( .A0(n976), .A1(n1034), .B0(n1088), .B1(n978), .Y(
Oper_Start_in_module_intM[3]) );
AOI22X1TS U1412 ( .A0(n974), .A1(n1014), .B0(n1066), .B1(n978), .Y(
Oper_Start_in_module_intM[4]) );
AOI22X1TS U1413 ( .A0(n976), .A1(n1046), .B0(n1062), .B1(n978), .Y(
Oper_Start_in_module_intM[5]) );
AOI22X1TS U1414 ( .A0(n974), .A1(n1019), .B0(n1079), .B1(n971), .Y(
Oper_Start_in_module_intM[6]) );
AOI22X1TS U1415 ( .A0(n976), .A1(n1099), .B0(n1072), .B1(n971), .Y(
Oper_Start_in_module_intM[7]) );
AOI22X1TS U1416 ( .A0(n974), .A1(n1035), .B0(n1084), .B1(n971), .Y(
Oper_Start_in_module_intM[8]) );
AOI22X1TS U1417 ( .A0(n974), .A1(n1004), .B0(n1073), .B1(n971), .Y(
Oper_Start_in_module_intM[9]) );
AOI22X1TS U1418 ( .A0(n976), .A1(n1011), .B0(n1080), .B1(n971), .Y(
Oper_Start_in_module_intM[10]) );
AOI22X1TS U1419 ( .A0(n974), .A1(n1030), .B0(n1081), .B1(n971), .Y(
Oper_Start_in_module_intM[11]) );
AOI22X1TS U1420 ( .A0(n976), .A1(n1065), .B0(n1036), .B1(n971), .Y(
Oper_Start_in_module_intM[12]) );
AOI22X1TS U1421 ( .A0(n976), .A1(n1040), .B0(n1068), .B1(n971), .Y(
Oper_Start_in_module_intM[13]) );
AOI22X1TS U1422 ( .A0(n976), .A1(n1005), .B0(n1025), .B1(n971), .Y(
Oper_Start_in_module_intM[14]) );
AOI22X1TS U1423 ( .A0(n974), .A1(n1041), .B0(n1090), .B1(n971), .Y(
Oper_Start_in_module_intM[15]) );
BUFX3TS U1424 ( .A(n971), .Y(n977) );
AOI22X1TS U1425 ( .A0(n974), .A1(n1053), .B0(n1064), .B1(n977), .Y(
Oper_Start_in_module_intM[16]) );
AOI22X1TS U1426 ( .A0(n976), .A1(n1037), .B0(n1085), .B1(n977), .Y(
Oper_Start_in_module_intM[17]) );
AOI22X1TS U1427 ( .A0(n974), .A1(n1006), .B0(n1082), .B1(n977), .Y(
Oper_Start_in_module_intM[18]) );
AOI22X1TS U1428 ( .A0(n974), .A1(n1038), .B0(n1024), .B1(n977), .Y(
Oper_Start_in_module_intM[19]) );
AOI22X1TS U1429 ( .A0(n976), .A1(n1007), .B0(n1071), .B1(n977), .Y(
Oper_Start_in_module_intM[20]) );
INVX2TS U1430 ( .A(n971), .Y(n979) );
AOI22X1TS U1431 ( .A0(n979), .A1(n1042), .B0(n1069), .B1(n977), .Y(
Oper_Start_in_module_intM[21]) );
AOI22X1TS U1432 ( .A0(n979), .A1(n1008), .B0(n1026), .B1(n977), .Y(
Oper_Start_in_module_intM[22]) );
AOI22X1TS U1433 ( .A0(n979), .A1(n1043), .B0(n1091), .B1(n977), .Y(
Oper_Start_in_module_intM[23]) );
AOI22X1TS U1434 ( .A0(n979), .A1(n1009), .B0(n1067), .B1(n977), .Y(
Oper_Start_in_module_intM[24]) );
AOI22X1TS U1435 ( .A0(n979), .A1(n1039), .B0(n1086), .B1(n977), .Y(
Oper_Start_in_module_intM[25]) );
AOI22X1TS U1436 ( .A0(n979), .A1(n1010), .B0(n1089), .B1(n977), .Y(
Oper_Start_in_module_intM[26]) );
AOI22X1TS U1437 ( .A0(n979), .A1(n1013), .B0(n1074), .B1(n977), .Y(
Oper_Start_in_module_intM[27]) );
AOI22X1TS U1438 ( .A0(n979), .A1(n1098), .B0(n1063), .B1(n971), .Y(
Oper_Start_in_module_intM[28]) );
AOI22X1TS U1439 ( .A0(n979), .A1(n1033), .B0(n1083), .B1(n977), .Y(
Oper_Start_in_module_intM[29]) );
AOI22X1TS U1440 ( .A0(n976), .A1(n1047), .B0(n1018), .B1(n978), .Y(
Oper_Start_in_module_intM[30]) );
NOR2XLTS U1441 ( .A(n991), .B(n980), .Y(n982) );
AOI22X1TS U1442 ( .A0(n990), .A1(n985), .B0(n648), .B1(n987), .Y(n981) );
OAI22X1TS U1443 ( .A0(n992), .A1(n982), .B0(n981), .B1(n991), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[24]) );
AOI222X1TS U1444 ( .A0(n988), .A1(n990), .B0(n987), .B1(n986), .C0(n985),
.C1(n648), .Y(n983) );
OAI22X1TS U1445 ( .A0(n992), .A1(n984), .B0(n983), .B1(n991), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[23]) );
AOI22X1TS U1446 ( .A0(n661), .A1(n987), .B0(n986), .B1(n985), .Y(n994) );
AOI22X1TS U1447 ( .A0(n990), .A1(n989), .B0(n648), .B1(n988), .Y(n993) );
AOI32X1TS U1448 ( .A0(n994), .A1(n704), .A2(n993), .B0(n992), .B1(n991), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[22]) );
CLKAND2X2TS U1449 ( .A(n997), .B(Sgf_normalized_result[2]), .Y(
final_result_ieee_Module_Sgf_S_mux[0]) );
CLKAND2X2TS U1450 ( .A(n997), .B(Sgf_normalized_result[3]), .Y(
final_result_ieee_Module_Sgf_S_mux[1]) );
CLKAND2X2TS U1451 ( .A(n997), .B(Sgf_normalized_result[4]), .Y(
final_result_ieee_Module_Sgf_S_mux[2]) );
CLKAND2X2TS U1452 ( .A(n997), .B(Sgf_normalized_result[5]), .Y(
final_result_ieee_Module_Sgf_S_mux[3]) );
CLKAND2X2TS U1453 ( .A(n997), .B(Sgf_normalized_result[6]), .Y(
final_result_ieee_Module_Sgf_S_mux[4]) );
CLKAND2X2TS U1454 ( .A(n997), .B(Sgf_normalized_result[7]), .Y(
final_result_ieee_Module_Sgf_S_mux[5]) );
CLKAND2X2TS U1455 ( .A(n997), .B(Sgf_normalized_result[8]), .Y(
final_result_ieee_Module_Sgf_S_mux[6]) );
CLKAND2X2TS U1456 ( .A(n997), .B(Sgf_normalized_result[9]), .Y(
final_result_ieee_Module_Sgf_S_mux[7]) );
CLKAND2X2TS U1457 ( .A(n997), .B(Sgf_normalized_result[10]), .Y(
final_result_ieee_Module_Sgf_S_mux[8]) );
CLKAND2X2TS U1458 ( .A(n997), .B(Sgf_normalized_result[11]), .Y(
final_result_ieee_Module_Sgf_S_mux[9]) );
CLKAND2X2TS U1459 ( .A(n997), .B(Sgf_normalized_result[12]), .Y(
final_result_ieee_Module_Sgf_S_mux[10]) );
CLKAND2X2TS U1460 ( .A(n997), .B(Sgf_normalized_result[13]), .Y(
final_result_ieee_Module_Sgf_S_mux[11]) );
CLKAND2X2TS U1461 ( .A(n997), .B(Sgf_normalized_result[14]), .Y(
final_result_ieee_Module_Sgf_S_mux[12]) );
CLKAND2X2TS U1462 ( .A(n995), .B(Sgf_normalized_result[15]), .Y(
final_result_ieee_Module_Sgf_S_mux[13]) );
CLKAND2X2TS U1463 ( .A(n995), .B(Sgf_normalized_result[16]), .Y(
final_result_ieee_Module_Sgf_S_mux[14]) );
CLKAND2X2TS U1464 ( .A(n995), .B(Sgf_normalized_result[17]), .Y(
final_result_ieee_Module_Sgf_S_mux[15]) );
CLKAND2X2TS U1465 ( .A(n995), .B(Sgf_normalized_result[18]), .Y(
final_result_ieee_Module_Sgf_S_mux[16]) );
CLKAND2X2TS U1466 ( .A(n995), .B(Sgf_normalized_result[19]), .Y(
final_result_ieee_Module_Sgf_S_mux[17]) );
CLKAND2X2TS U1467 ( .A(n995), .B(Sgf_normalized_result[20]), .Y(
final_result_ieee_Module_Sgf_S_mux[18]) );
CLKAND2X2TS U1468 ( .A(n995), .B(Sgf_normalized_result[21]), .Y(
final_result_ieee_Module_Sgf_S_mux[19]) );
CLKAND2X2TS U1469 ( .A(n995), .B(Sgf_normalized_result[22]), .Y(
final_result_ieee_Module_Sgf_S_mux[20]) );
CLKAND2X2TS U1470 ( .A(n995), .B(Sgf_normalized_result[23]), .Y(
final_result_ieee_Module_Sgf_S_mux[21]) );
CLKAND2X2TS U1471 ( .A(n997), .B(Sgf_normalized_result[24]), .Y(
final_result_ieee_Module_Sgf_S_mux[22]) );
NAND2X1TS U1473 ( .A(n999), .B(n998), .Y(FSM_barrel_shifter_load) );
initial $sdf_annotate("FPU_Add_Subtract_Function_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:37:07 10/25/2015
// Design Name:
// Module Name: display
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module HexTo8SEG(input [31:0] Hexs, //¶Ë¿Ú±äÁ¿ËµÃ÷Ó붨ÒåºÏ²¢
// input [2:0] Scan,
input [7:0] points,
input [7:0] LES,
input flash,
output[63:0] SEG_TXT
);
Hex2Seg HTS0(Hexs[31:28],LES[7],points[7],flash,SEG_TXT[7:0]);
Hex2Seg HTS1(Hexs[27:24],LES[6],points[6],flash,SEG_TXT[15:8]);
Hex2Seg HTS2(Hexs[23:20],LES[5],points[5],flash,SEG_TXT[23:16]);
Hex2Seg HTS3(Hexs[19:16],LES[4],points[4],flash,SEG_TXT[31:24]);
Hex2Seg HTS4(Hexs[15:12],LES[3],points[3],flash,SEG_TXT[39:32]);
Hex2Seg HTS5(Hexs[11:8], LES[2],points[2],flash,SEG_TXT[47:40]);
Hex2Seg HTS6(Hexs[7:4], LES[1],points[1],flash,SEG_TXT[55:48]);
Hex2Seg HTS7(Hexs[3:0], LES[0],points[0],flash,SEG_TXT[63:56]);
endmodule
module Hex2Seg(input[3:0]Hex,
input LE,
input point,
input flash,
output[7:0]Segment
);
wire en = LE & flash;
MC14495_ZJU MSEG(.D3(Hex[3]),.D2(Hex[2]),.D1(Hex[1]),.D0(Hex[0]),.LE(en),.point(point),
.a(a),.b(b),.c(c),.d(d),.e(e),.f(f),.g(g),.p(p));
assign Segment = {a,b,c,d,e,f,g,p}; //p,g,f,e,d,c,b,a
endmodule
/* always @* begin //Ðźű仯´¥·¢ (×éºÏµç·²»ÓÃʱÖÓ´¥·¢)
case (Scan) //ͬ²½Êä³ö
3'b000: begin Hexo = Hexs[31:28]; SEG_TXT[7:0] = Segment;
point <= points[7]; LE <= LES[7]; end //ͬ²½Êä³ö
3'b001: begin Hexo = Hexs[27:24]; SEG_TXT[15:8] = Segment;
point <= points[6]; LE <= LES[6]; end //ͬ²½Êä³ö
3'b010: begin Hexo = Hexs[23:20]; SEG_TXT[23:16] = Segment;
point <= points[5]; LE <= LES[5]; end //ͬ²½Êä³ö
3'b011: begin Hexo = Hexs[19:16]; SEG_TXT[31:24] = Segment;
point <= points[4]; LE <= LES[4]; end //ͬ²½Êä³ö
3'b100: begin Hexo = Hexs[15:12]; SEG_TXT[39:32] = Segment;
point <= points[3]; LE <= LES[3]; end //ͬ²½Êä³ö
3'b101: begin Hexo = Hexs[11:8]; SEG_TXT[47:40] = Segment;
point <= points[2]; LE <= LES[2]; end //ͬ²½Êä³ö
3'b110: begin Hexo = Hexs[7:4]; SEG_TXT[55:48] = Segment;
point <= points[1]; LE <= LES[1]; end //ͬ²½Êä³ö
3'b111: begin Hexo = Hexs[3:0]; SEG_TXT[63:56] = Segment;
point <= points[0]; LE <= LES[0]; end //ͬ²½Êä³ö
endcase
end
*/
|
module MEMWB_Reg (
input clk,
input rst,
input flush,
input stall,
input [2-1:0] WB_ctrl_i,
output [2-1:0] WB_ctrl_o,
input [32-1:0] ALU_output_i,
output [32-1:0] ALU_output_o,
input [32-1:0] Mem_output_i,
output [32-1:0] Mem_output_o,
input [5-1:0] RegFwd_i,
output [5-1:0] RegFwd_o
);
Latch #(.width(2)) MEMWB_WB_ctrl (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (WB_ctrl_i),
.data_o (WB_ctrl_o)
);
Latch MEMWB_ALU_output (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (ALU_output_i),
.data_o (ALU_output_o)
);
Latch MEMWB_Mem_output (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (Mem_output_i),
.data_o (Mem_output_o)
);
Latch #(.width(5)) MEMWB_RegFwd (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (RegFwd_i),
.data_o (RegFwd_o)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A31OI_BEHAVIORAL_V
`define SKY130_FD_SC_LS__A31OI_BEHAVIORAL_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a31oi (
Y ,
A1,
A2,
A3,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y, B1, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A31OI_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND3B_SYMBOL_V
`define SKY130_FD_SC_HD__NAND3B_SYMBOL_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nand3b (
//# {{data|Data Signals}}
input A_N,
input B ,
input C ,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND3B_SYMBOL_V
|
/////////////////////////////////////////////////////////////////////
//// ////
//// FFT/IFFT 256 points transform ////
//// ////
//// Authors: Anatoliy Sergienko, Volodya Lepeha ////
//// Company: Unicore Systems http://unicore.co.ua ////
//// ////
//// Downloaded from: http://www.opencores.org ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2010 Unicore Systems LTD ////
//// www.unicore.co.ua ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED "AS IS" ////
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// DESCRIPTION : Normalization unit
// FUNCTION: shifting left up to 3 bits
// FILES: CNORM.v
// PROPERTIES: 1) shifting left up to 3 bits controlled by the 2-bit code SHIFT
// 2) Is registered
// 3) Overflow detector detects the overflow event
// by the given shift condition. The detector is zeroed by the START signal
// 4) RDY is the START signal delayed to a single clock cycle
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// File :
// Generated :
//
// Description :
//
//-----------------------------------------------------------------------------
`timescale 1 ns / 1 ps
`include "FFT256_CONFIG.inc"
module CNORM ( CLK ,ED ,START ,DR ,DI ,SHIFT ,OVF ,RDY ,DOR ,DOI );
`FFT256paramnb
output OVF ;
reg OVF ;
output RDY ;
reg RDY ;
output [nb+1:0] DOR ;
wire [nb+1:0] DOR ;
output [nb+1:0] DOI ;
wire [nb+1:0] DOI ;
input CLK ;
wire CLK ;
input ED ;
wire ED ;
input START ;
wire START ;
input [nb+3:0] DR ;
wire [nb+3:0] DR ;
input [nb+3:0] DI ;
wire [nb+3:0] DI ;
input [1:0] SHIFT ; //shift left code to 0,1,2,3 bits
wire [1:0] SHIFT ;
wire signed [nb+3:0] diri,diii;
assign diri = DR << SHIFT;
assign diii = DI << SHIFT;
reg [nb+3:0] dir,dii;
`ifdef FFT256round //rounding
always @( posedge CLK ) begin
if (ED) begin
dir<=diri;
dii<=diii;
end
end
`else //truncation
always @( posedge CLK ) begin
if (ED) begin
if (diri[nb+3] && ~diri[0]) // <0 with LSB=00
dir<=diri;
else dir<=diri+2;
if (diii[nb+3] && ~diii[0])
dii<=diii;
else dii<=diii+2;
end
end
`endif
always @( posedge CLK ) begin
if (ED) begin
RDY<=START;
if (START)
OVF<=0;
else
case (SHIFT)
2'b01 : OVF<= (DR[nb+3] != DR[nb+2]) || (DI[nb+3] != DI[nb+2]);
2'b10 : OVF<= (DR[nb+3] != DR[nb+2]) || (DI[nb+3] != DI[nb+2]) ||
(DR[nb+3] != DR[nb+1]) || (DI[nb+3] != DI[nb+1]);
2'b11 : OVF<= (DR[nb+3] != DR[nb+2]) || (DI[nb+3] != DI[nb+2])||
(DR[nb+3] != DR[nb]) || (DI[nb+3] != DI[nb]) ||
(DR[nb+3] != DR[nb+1]) || (DI[nb+3] != DI[nb+1]);
endcase
end
end
assign DOR= dir[nb+3:2];
assign DOI= dii[nb+3:2];
endmodule
|
/*
###############################################################################
# pyrpl - DSP servo controller for quantum optics with the RedPitaya
# Copyright (C) 2014-2016 Leonhard Neuhaus ([email protected])
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
###############################################################################
*/
/***********************************************************
DSP Module
This module hosts the different submodules used for digital signal processing.
1)
The first half of this file manages the connection between different submodules by
implementing a bus between them:
connecting the output_signal of submodule i to the input_signal of submodule j is
done by setting the register
input_select[j] <= i;
Similarly, a second, possibly different output is allowed for each module: output_direct.
This output is added to the analog output 1 and/or 2 depending on the value
of the register output_select: setting the first bit enables output1, the 2nd bit enables output 2.
Example:
output_select[i] = OUT2;
By default, all routing is done as in the original redpitaya.
2)
The second half of this file defines the different submodules. For custom submodules,
a good point to start is red_pitaya_pid_block.v.
Submodule i is assigned the address space
0x40300000 + i*0x10000 + (0x0000 to 0xFFFF), that is 2**16 bytes.
Addresses 0x403z00zz where z is an arbitrary hex character are reserved to manage
the input/output routing of the submodule and are not forwarded, and therefore
should not be used.
*************************************************************/
module red_pitaya_dsp #(
parameter MODULES = 8
)
(
// signals
input clk_i , //!< processing clock
input rstn_i , //!< processing reset - active low
input [ 14-1: 0] dat_a_i , //!< input data CHA
input [ 14-1: 0] dat_b_i , //!< input data CHB
output [ 14-1: 0] dat_a_o , //!< output data CHA
output [ 14-1: 0] dat_b_o , //!< output data CHB
output [ 14-1: 0] scope1_o,
output [ 14-1: 0] scope2_o,
input [ 14-1: 0] asg1_i,
input [ 14-1: 0] asg2_i,
input [ 14-1: 0] asg1phase_i,
// pwm outputs
output [ 14-1: 0] pwm0,
output [ 14-1: 0] pwm1,
output [ 14-1: 0] pwm2,
output [ 14-1: 0] pwm3,
// trigger outputs for the scope
output trig_o, // output from trigger dsp module
// system bus
input [ 32-1: 0] sys_addr , //!< bus address
input [ 32-1: 0] sys_wdata , //!< bus write data
input [ 4-1: 0] sys_sel , //!< bus write byte select
input sys_wen , //!< bus write enable
input sys_ren , //!< bus read enable
output reg [ 32-1: 0] sys_rdata , //!< bus read data
output reg sys_err , //!< bus error indicator
output reg sys_ack //!< bus acknowledge signal
);
localparam EXTRAMODULES = 2; //need two extra control registers for scope/asg
localparam EXTRAINPUTS = 4; //four extra input signals for dac(2)/adc(2)
localparam EXTRAOUTPUTS = 2; //two extra output signals for pwm channels
localparam LOG_MODULES = 4;// ceil(log2(EXTRAINPUTS+EXTRAOUTPUTS+MODULES))
//Module numbers
localparam PID0 = 'd0; //formerly PID11
localparam PID1 = 'd1; //formerly PID12: input2->output1
localparam PID2 = 'd2; //formerly PID21: input1->output2
localparam PID3 = 'd3; //formerly PID22
localparam TRIG = 'd3; //formerly PID3
localparam IIR = 'd4; //IIR filter to connect in series to PID module
localparam IQ0 = 'd5; //for PDH signal generation
localparam IQ1 = 'd6; //for NA functionality
localparam IQ2 = 'd7; //for PFD error signal
//localparam CUSTOM1 = 'd8; //available slots
localparam NONE = 2**LOG_MODULES-1; //code for no module; only used to switch off PWM outputs
//EXTRAMODULE numbers
localparam ASG1 = MODULES; //scope and asg can have the same number
localparam ASG2 = MODULES+1; //because one only has outputs, the other only inputs
localparam SCOPE1 = MODULES;
localparam SCOPE2 = MODULES+1;
//EXTRAINPUT numbers
localparam ADC1 = MODULES+2;
localparam ADC2 = MODULES+3;
localparam DAC1 = MODULES+4;
localparam DAC2 = MODULES+5;
//EXTRAOUTPUT numbers
localparam PWM0 = MODULES+2;
localparam PWM1 = MODULES+3;
localparam PWM3 = MODULES+4;
localparam PWM4 = MODULES+5;
//output states
localparam BOTH = 2'b11;
localparam OUT1 = 2'b01;
localparam OUT2 = 2'b10;
localparam OFF = 2'b00;
// the selected input signal of each module: modules and extramodules have inputs
// extraoutputs are treated like extramodules that do not provide their own output_signal
wire [14-1:0] input_signal [MODULES+EXTRAMODULES+EXTRAOUTPUTS-1:0];
// the selected input signal NUMBER of each module
reg [LOG_MODULES-1:0] input_select [MODULES+EXTRAMODULES+EXTRAOUTPUTS-1:0];
// the output of each module for internal routing, including 'virtual outputs' for the EXTRAINPUTS
wire [14-1:0] output_signal [MODULES+EXTRAMODULES+EXTRAINPUTS-1+1:0];
// the output of each module that is added to the chosen DAC
wire [14-1:0] output_direct [MODULES+EXTRAMODULES-1:0];
// the channel that the module's output_direct is added to (bit0: DAC1, bit 1: DAC2)
reg [2-1:0] output_select [MODULES+EXTRAMODULES-1:0];
// syncronization register to trigger simultaneous action of different dsp modules
reg [MODULES-1:0] sync;
// bus read data of individual modules (only needed for 'real' modules)
wire [ 32-1: 0] module_rdata [MODULES-1:0];
wire module_ack [MODULES-1:0];
//connect scope
assign scope1_o = input_signal[SCOPE1];
assign scope2_o = input_signal[SCOPE2];
//connect asg output
assign output_signal[ASG1] = asg1_i;
assign output_signal[ASG2] = asg2_i;
assign output_direct[ASG1] = asg1_i;
assign output_direct[ASG2] = asg2_i;
//connect dac/adc to internal signals
assign output_signal[ADC1] = dat_a_i;
assign output_signal[ADC2] = dat_b_i;
assign output_signal[DAC1] = dat_a_o;
assign output_signal[DAC2] = dat_b_o;
//connect only two pwm to internal signals (should be enough)
assign pwm0 = (input_select[PWM0] == NONE) ? 14'h0 : output_signal[input_select[PWM0]];
assign pwm1 = (input_select[PWM1] == NONE) ? 14'h0 : output_signal[input_select[PWM1]];
assign pwm2 = 14'b0;
assign pwm3 = 14'b0;
reg signed [ 14+LOG_MODULES-1: 0] sum1;
reg signed [ 14+LOG_MODULES-1: 0] sum2;
wire dac_a_saturated; //high when dac_a is saturated
wire dac_b_saturated; //high when dac_b is saturated
integer i;
genvar j;
//select inputs
generate for (j = 0; j < MODULES+EXTRAMODULES; j = j+1)
assign input_signal[j] = (input_select[j]==NONE) ? 14'b0 : output_signal[input_select[j]];
endgenerate
//sum together the direct outputs
//
//use a tree-like structure where at most 2 numbers are added per cycle (4 should be possible as well but lets go slow)
//CHANNELS is the number of numbers to add, CHANNELS-1 the number of tree nodes (represented in presum)
//presum... 0-7: sum of pairs of input signals (for 16 channels)
//presum... 8 = 0+1, 9=2+3, 10=4+5 etc... => end result in presum[CHANNELS-1-1]
//right now we have an extra delay to go into sum, just to make sure that the slack is maximally positive
localparam CHANNELS = 2**LOG_MODULES; //not the same as MODULES+EXTRAMODULES
reg signed [ 14+LOG_MODULES-1: 0] presum1 [CHANNELS-1-1:0];
reg signed [ 14+LOG_MODULES-1: 0] presum2 [CHANNELS-1-1:0];
always @(posedge clk_i) begin
if (rstn_i == 1'b0) begin
for (i=0;i<CHANNELS;i=i+1) begin
presum1[i] <= {14+LOG_MODULES{1'b0}};
presum2[i] <= {14+LOG_MODULES{1'b0}};
end
sum1 <= {14+LOG_MODULES{1'b0}};
sum2 <= {14+LOG_MODULES{1'b0}};
end
else begin
//first sum pairs if they are set to be summed
for (i=0;i<(MODULES+EXTRAMODULES)/2;i=i+1) begin
presum1[i] <= ({14+LOG_MODULES{(|(output_select[2*i]&OUT1))}} & {{LOG_MODULES{output_direct[2*i][14-1]}},output_direct[2*i]}) + ({14+LOG_MODULES{(|(output_select[2*i+1]&OUT1))}} & {{LOG_MODULES{output_direct[2*i+1][14-1]}},output_direct[2*i+1]});
presum2[i] <= ({14+LOG_MODULES{(|(output_select[2*i]&OUT2))}} & {{LOG_MODULES{output_direct[2*i][14-1]}},output_direct[2*i]}) + ({14+LOG_MODULES{(|(output_select[2*i+1]&OUT2))}} & {{LOG_MODULES{output_direct[2*i+1][14-1]}},output_direct[2*i+1]});
end
//then sum the sums of pairs to go up the tree
for (i=0;i<CHANNELS/2-1;i=i+1) begin
presum1[8+i] <= presum1[2*i]+presum1[2*i+1];
presum2[8+i] <= presum2[2*i]+presum2[2*i+1];
end
//finally add some (probably unnecessary) delay
sum1 <= presum1[CHANNELS-1-1];
sum2 <= presum2[CHANNELS-1-1];
end
end
//saturation of outputs
red_pitaya_saturate #(
.BITS_IN (14+LOG_MODULES),
.SHIFT(0),
.BITS_OUT(14)
) dac_saturate [1:0] (
.input_i({sum2,sum1}),
.output_o({dat_b_o,dat_a_o}),
.overflow ({dat_b_saturated,dac_a_saturated})
);
// System bus connection
always @(posedge clk_i) begin
if (rstn_i == 1'b0) begin
//default settings for backwards compatibility with original code
input_select [PID0] <= ADC1;
output_select[PID0] <= OFF;
input_select [PID1] <= ADC1;
output_select[PID1] <= OFF;
input_select [PID2] <= ADC1;
output_select[PID2] <= OFF;
input_select [PID3] <= ADC1;
output_select[PID3] <= OFF;
input_select [IIR] <= ADC1;
output_select[IIR] <= OFF;
input_select [IQ0] <= ADC1;
output_select[IQ0] <= OFF;
input_select [IQ1] <= ADC1;
output_select[IQ1] <= OFF;
input_select [IQ2] <= ADC1;
output_select[IQ2] <= OFF;
input_select [SCOPE1] <= ADC1;
input_select [SCOPE2] <= ADC2;
output_select[ASG1] <= OFF;
output_select[ASG2] <= OFF;
input_select [PWM0] <= NONE;
input_select [PWM1] <= NONE;
sync <= {MODULES{1'b1}} ; // all modules on by default
end
else begin
if (sys_wen) begin
if (sys_addr[16-1:0]==16'h00) input_select[sys_addr[16+LOG_MODULES-1:16]] <= sys_wdata[ LOG_MODULES-1:0];
if (sys_addr[16-1:0]==16'h04) output_select[sys_addr[16+LOG_MODULES-1:16]] <= sys_wdata[ 2-1:0];
if (sys_addr[16-1:0]==16'h0C) sync <= sys_wdata[MODULES-1:0];
end
end
end
wire sys_en;
assign sys_en = sys_wen | sys_ren;
always @(posedge clk_i)
if (rstn_i == 1'b0) begin
sys_err <= 1'b0 ;
sys_ack <= 1'b0 ;
end else begin
sys_err <= 1'b0 ;
casez (sys_addr[16-1:0])
20'h00 : begin sys_ack <= sys_en; sys_rdata <= {{32- LOG_MODULES{1'b0}},input_select[sys_addr[16+LOG_MODULES-1:16]]}; end
20'h04 : begin sys_ack <= sys_en; sys_rdata <= {{32- 2{1'b0}},output_select[sys_addr[16+LOG_MODULES-1:16]]}; end
20'h08 : begin sys_ack <= sys_en; sys_rdata <= {{32- 2{1'b0}},dat_b_saturated,dac_a_saturated}; end
20'h0C : begin sys_ack <= sys_en; sys_rdata <= {{32-MODULES{1'b0}},sync} ; end
20'h10 : begin sys_ack <= sys_en; sys_rdata <= {{32- 14{1'b0}},output_signal[sys_addr[16+LOG_MODULES-1:16]]} ; end
default : begin sys_ack <= module_ack[sys_addr[16+LOG_MODULES-1:16]]; sys_rdata <= module_rdata[sys_addr[16+LOG_MODULES-1:16]] ; end
endcase
end
/**********************************************
MODULE DEFINITIONS
*********************************************/
//PID
wire [14-1:0] diff_input_signal [3-1:0];
wire [14-1:0] diff_output_signal [3-1:0];
//assign diff_input_signal[0] = input_signal[1]; // difference input of PID0 is PID1
//assign diff_input_signal[1] = input_signal[0]; // difference input of PID1 is PID0
assign diff_input_signal[0] = diff_output_signal[1]; // difference input of PID0 is PID1
assign diff_input_signal[1] = diff_output_signal[0]; // difference input of PID1 is PID0
assign diff_input_signal[2] = {14{1'b0}}; // difference input of PID2 is zero
generate for (j = 0; j < 3; j = j+1) begin
red_pitaya_pid_block i_pid (
// data
.clk_i ( clk_i ), // clock
.rstn_i ( rstn_i ), // reset - active low
.sync_i ( sync[j] ), // syncronization of different dsp modules
.dat_i ( input_signal [j] ), // input data
.dat_o ( output_direct[j]), // output data
.diff_dat_i ( diff_input_signal[j] ), // input data for differential mode
.diff_dat_o ( diff_output_signal[j] ), // output data for differential mode
//communincation with PS
.addr ( sys_addr[16-1:0] ),
.wen ( sys_wen & (sys_addr[20-1:16]==j) ),
.ren ( sys_ren & (sys_addr[20-1:16]==j) ),
.ack ( module_ack[j] ),
.rdata (module_rdata[j]),
.wdata (sys_wdata)
);
assign output_signal[j] = output_direct[j];
end
endgenerate
wire trig_signal;
//TRIG
generate for (j = 3; j < 4; j = j+1) begin
red_pitaya_trigger_block i_trigger (
// data
.clk_i ( clk_i ), // clock
.rstn_i ( rstn_i ), // reset - active low
.dat_i ( input_signal [j] ), // input data
.dat_o ( output_direct[j]), // output data
.signal_o ( output_signal[j]), // output signal
.phase1_i ( asg1phase_i ), // phase input
.trig_o ( trig_signal ),
//communincation with PS
.addr ( sys_addr[16-1:0] ),
.wen ( sys_wen & (sys_addr[20-1:16]==j) ),
.ren ( sys_ren & (sys_addr[20-1:16]==j) ),
.ack ( module_ack[j] ),
.rdata (module_rdata[j]),
.wdata (sys_wdata)
);
end
endgenerate
assign trig_o = trig_signal;
//IIR module
generate for (j = 4; j < 5; j = j+1) begin
red_pitaya_iir_block iir (
// data
.clk_i ( clk_i ), // clock
.rstn_i ( rstn_i ), // reset - active low
.dat_i ( input_signal [j] ), // input data
.dat_o ( output_direct[j]), // output data
//communincation with PS
.addr ( sys_addr[16-1:0] ),
.wen ( sys_wen & (sys_addr[20-1:16]==j) ),
.ren ( sys_ren & (sys_addr[20-1:16]==j) ),
.ack ( module_ack[j] ),
.rdata (module_rdata[j]),
.wdata (sys_wdata)
);
assign output_signal[j] = output_direct[j];
end endgenerate
//IQ modules
generate for (j = 5; j < 7; j = j+1) begin
red_pitaya_iq_block
iq
(
// data
.clk_i ( clk_i ), // clock
.rstn_i ( rstn_i ), // reset - active low
.sync_i ( sync[j] ), // syncronization of different dsp modules
.dat_i ( input_signal [j] ), // input data
.dat_o ( output_direct[j]), // output data
.signal_o ( output_signal[j]), // output signal
// not using 2nd quadrature for most iq's: multipliers will be
// synthesized away by Vivado
//.signal2_o ( output_signal[j*2]), // output signal
//communincation with PS
.addr ( sys_addr[16-1:0] ),
.wen ( sys_wen & (sys_addr[20-1:16]==j) ),
.ren ( sys_ren & (sys_addr[20-1:16]==j) ),
.ack ( module_ack[j] ),
.rdata (module_rdata[j]),
.wdata (sys_wdata)
);
end endgenerate
// IQ with two outputs
generate for (j = 7; j < 8; j = j+1) begin
red_pitaya_iq_block #( .QUADRATUREFILTERSTAGES(4) )
iq_2_outputs
(
// data
.clk_i ( clk_i ), // clock
.rstn_i ( rstn_i ), // reset - active low
.sync_i ( sync[j] ), // syncronization of different dsp modules
.dat_i ( input_signal [j] ), // input data
.dat_o ( output_direct[j]), // output data
.signal_o ( output_signal[j]), // output signal
.signal2_o ( output_signal[j*2]), // output signal 2
//communincation with PS
.addr ( sys_addr[16-1:0] ),
.wen ( sys_wen & (sys_addr[20-1:16]==j) ),
.ren ( sys_ren & (sys_addr[20-1:16]==j) ),
.ack ( module_ack[j] ),
.rdata (module_rdata[j]),
.wdata (sys_wdata)
);
end endgenerate
endmodule
|
/* wb_arbiter. Part of wb_intercon
*
* ISC License
*
* Copyright (C) 2013-2019 Olof Kindgren <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/*
Wishbone arbiter, burst-compatible
Simple round-robin arbiter for multiple Wishbone masters
*/
module wb_arbiter
#(parameter dw = 32,
parameter aw = 32,
parameter num_masters = 0)
(
input wb_clk_i,
input wb_rst_i,
// Wishbone Master Interface
input [num_masters*aw-1:0] wbm_adr_i,
input [num_masters*dw-1:0] wbm_dat_i,
input [num_masters*4-1:0] wbm_sel_i,
input [num_masters-1:0] wbm_we_i,
input [num_masters-1:0] wbm_cyc_i,
input [num_masters-1:0] wbm_stb_i,
input [num_masters*3-1:0] wbm_cti_i,
input [num_masters*2-1:0] wbm_bte_i,
output [num_masters*dw-1:0] wbm_dat_o,
output [num_masters-1:0] wbm_ack_o,
output [num_masters-1:0] wbm_err_o,
output [num_masters-1:0] wbm_rty_o,
// Wishbone Slave interface
output [aw-1:0] wbs_adr_o,
output [dw-1:0] wbs_dat_o,
output [3:0] wbs_sel_o,
output wbs_we_o,
output wbs_cyc_o,
output wbs_stb_o,
output [2:0] wbs_cti_o,
output [1:0] wbs_bte_o,
input [dw-1:0] wbs_dat_i,
input wbs_ack_i,
input wbs_err_i,
input wbs_rty_i);
///////////////////////////////////////////////////////////////////////////////
// Parameters
///////////////////////////////////////////////////////////////////////////////
//ISim does not implement $clog2. Other tools have broken implementations
`ifdef BROKEN_CLOG2
function integer clog2;
input integer in;
begin
in = in - 1;
for (clog2 = 0; in > 0; clog2=clog2+1)
in = in >> 1;
end
endfunction
`define clog2 clog2
`else // !`ifdef BROKEN_CLOG2
`define clog2 $clog2
`endif
//Use parameter instead of localparam to work around a bug in Xilinx ISE
parameter master_sel_bits = num_masters > 1 ? `clog2(num_masters) : 1;
wire [num_masters-1:0] grant;
wire [master_sel_bits-1:0] master_sel;
wire active;
arbiter
#(.NUM_PORTS (num_masters))
arbiter0
(.clk (wb_clk_i),
.rst (wb_rst_i),
.request (wbm_cyc_i),
.grant (grant),
.select (master_sel),
.active (active));
/* verilator lint_off WIDTH */
//Mux active master
assign wbs_adr_o = wbm_adr_i[master_sel*aw+:aw];
assign wbs_dat_o = wbm_dat_i[master_sel*dw+:dw];
assign wbs_sel_o = wbm_sel_i[master_sel*4+:4];
assign wbs_we_o = wbm_we_i [master_sel];
assign wbs_cyc_o = wbm_cyc_i[master_sel] & active;
assign wbs_stb_o = wbm_stb_i[master_sel];
assign wbs_cti_o = wbm_cti_i[master_sel*3+:3];
assign wbs_bte_o = wbm_bte_i[master_sel*2+:2];
assign wbm_dat_o = {num_masters{wbs_dat_i}};
assign wbm_ack_o = ((wbs_ack_i & active) << master_sel);
assign wbm_err_o = ((wbs_err_i & active) << master_sel);
assign wbm_rty_o = ((wbs_rty_i & active) << master_sel);
/* verilator lint_on WIDTH */
endmodule // wb_arbiter
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A31OI_2_V
`define SKY130_FD_SC_HD__A31OI_2_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog wrapper for a31oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a31oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a31oi_2 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a31oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a31oi_2 (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a31oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A31OI_2_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__LSBUFISO1P_BEHAVIORAL_V
`define SKY130_FD_SC_LP__LSBUFISO1P_BEHAVIORAL_V
/**
* lsbufiso1p: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__lsbufiso1p (
X ,
A ,
SLEEP
);
// Module ports
output X ;
input A ;
input SLEEP;
// Module supplies
supply1 DESTPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 DESTVPB;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, A, SLEEP );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (X , or0_out_X, DESTPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__LSBUFISO1P_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__LSBUF_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__LSBUF_PP_BLACKBOX_V
/**
* lsbuf: ????.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__lsbuf (
X ,
A ,
DESTPWR,
VPWR ,
VGND ,
DESTVPB,
VPB ,
VNB
);
output X ;
input A ;
input DESTPWR;
input VPWR ;
input VGND ;
input DESTVPB;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__LSBUF_PP_BLACKBOX_V
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
// IP Revision: 5
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module pikachu_jump_pixel (
clka,
wea,
addra,
dina,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [0 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [12 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [11 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [11 : 0] douta;
blk_mem_gen_v8_3_5 #(
.C_FAMILY("artix7"),
.C_XDEVICEFAMILY("artix7"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(0),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("pikachu_jump_pixel.mif"),
.C_INIT_FILE("pikachu_jump_pixel.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(0),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(12),
.C_READ_WIDTH_A(12),
.C_WRITE_DEPTH_A(6804),
.C_READ_DEPTH_A(6804),
.C_ADDRA_WIDTH(13),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(12),
.C_READ_WIDTH_B(12),
.C_WRITE_DEPTH_B(6804),
.C_READ_DEPTH_B(6804),
.C_ADDRB_WIDTH(13),
.C_HAS_MEM_OUTPUT_REGS_A(1),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_EN_SAFETY_CKT(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("3"),
.C_COUNT_18K_BRAM("0"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 5.016775 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(1'D0),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(13'B0),
.dinb(12'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.rsta_busy(),
.rstb_busy(),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(12'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
// TimeHoldOver_Qsys_mm_interconnect_0_avalon_st_adapter_006.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.0 222
`timescale 1 ps / 1 ps
module TimeHoldOver_Qsys_mm_interconnect_0_avalon_st_adapter_006 #(
parameter inBitsPerSymbol = 18,
parameter inUsePackets = 0,
parameter inDataWidth = 18,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 18,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [17:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [17:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
TimeHoldOver_Qsys_mm_interconnect_0_avalon_st_adapter_006_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module generates the clocks needed for the I/O devices on *
* Altera's DE-series boards. *
* *
******************************************************************************/
module clocks (
// inputs
CLOCK_50,
reset,
address,
// bidirectional
// outputs
sys_clk,
SDRAM_CLK,
readdata
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter SYS_CLK_MULT = 1;
parameter SYS_CLK_DIV = 1;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input CLOCK_50;
input reset;
input address;
// Bidirectionals
// Outputs
output sys_clk;
output SDRAM_CLK;
output reg [ 7: 0] readdata;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire clk_locked;
wire audio_clk_locked;
wire video_in_clk;
wire VGA_CLK;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge CLOCK_50)
begin
if (reset)
readdata <= 8'h00;
else if (address)
readdata <= 8'h00;
else
readdata <= {6'h00, audio_clk_locked, clk_locked};
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altpll DE_Clock_Generator_System (
.inclk ({1'b0, CLOCK_50}),
.clk ({VGA_CLK, SDRAM_CLK, sys_clk}),
.locked (clk_locked),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.pfdena (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 ()
);
defparam
DE_Clock_Generator_System.clk0_divide_by = SYS_CLK_DIV,
DE_Clock_Generator_System.clk0_duty_cycle = 50,
DE_Clock_Generator_System.clk0_multiply_by = SYS_CLK_MULT,
DE_Clock_Generator_System.clk0_phase_shift = "0",
DE_Clock_Generator_System.clk1_divide_by = SYS_CLK_DIV,
DE_Clock_Generator_System.clk1_duty_cycle = 50,
DE_Clock_Generator_System.clk1_multiply_by = SYS_CLK_MULT,
DE_Clock_Generator_System.clk1_phase_shift = "-3000",
DE_Clock_Generator_System.clk2_divide_by = 2,
DE_Clock_Generator_System.clk2_duty_cycle = 50,
DE_Clock_Generator_System.clk2_multiply_by = 1,
DE_Clock_Generator_System.clk2_phase_shift = "20000",
DE_Clock_Generator_System.compensate_clock = "CLK0",
DE_Clock_Generator_System.gate_lock_signal = "NO",
DE_Clock_Generator_System.inclk0_input_frequency = 20000,
DE_Clock_Generator_System.intended_device_family = "Cyclone IV",
DE_Clock_Generator_System.invalid_lock_multiplier = 5,
DE_Clock_Generator_System.lpm_type = "altpll",
DE_Clock_Generator_System.operation_mode = "NORMAL",
DE_Clock_Generator_System.pll_type = "FAST",
DE_Clock_Generator_System.port_activeclock = "PORT_UNUSED",
DE_Clock_Generator_System.port_areset = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkbad0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkbad1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkloss = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkswitch = "PORT_UNUSED",
DE_Clock_Generator_System.port_fbin = "PORT_UNUSED",
DE_Clock_Generator_System.port_inclk0 = "PORT_USED",
DE_Clock_Generator_System.port_inclk1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_locked = "PORT_USED",
DE_Clock_Generator_System.port_pfdena = "PORT_UNUSED",
DE_Clock_Generator_System.port_pllena = "PORT_UNUSED",
DE_Clock_Generator_System.port_scanaclr = "PORT_UNUSED",
DE_Clock_Generator_System.port_scanclk = "PORT_UNUSED",
DE_Clock_Generator_System.port_scandata = "PORT_UNUSED",
DE_Clock_Generator_System.port_scandataout = "PORT_UNUSED",
DE_Clock_Generator_System.port_scandone = "PORT_UNUSED",
DE_Clock_Generator_System.port_scanread = "PORT_UNUSED",
DE_Clock_Generator_System.port_scanwrite = "PORT_UNUSED",
DE_Clock_Generator_System.port_clk0 = "PORT_USED",
DE_Clock_Generator_System.port_clk1 = "PORT_USED",
DE_Clock_Generator_System.port_clk2 = "PORT_USED",
DE_Clock_Generator_System.port_clk3 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clk4 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clk5 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena2 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena3 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena4 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena5 = "PORT_UNUSED",
DE_Clock_Generator_System.port_enable0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_enable1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclk0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclk1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclk2 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclk3 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclkena0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclkena1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclkena2 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclkena3 = "PORT_UNUSED",
DE_Clock_Generator_System.port_sclkout0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_sclkout1 = "PORT_UNUSED",
DE_Clock_Generator_System.valid_lock_multiplier = 1;
endmodule
|
/* ********************************************************************************************* */
/* * Top Module * */
/* * Authors: * */
/* * André Bannwart Perina * */
/* * Luciano Falqueto * */
/* * Wallison de Oliveira * */
/* ********************************************************************************************* */
/* * Copyright (c) 2016 André B. Perina, Luciano Falqueto and Wallison de Oliveira * */
/* * * */
/* * Permission is hereby granted, free of charge, to any person obtaining a copy of this * */
/* * software and associated documentation files (the "Software"), to deal in the Software * */
/* * without restriction, including without limitation the rights to use, copy, modify, * */
/* * merge, publish, distribute, sublicense, and/or sell copies of the Software, and to * */
/* * permit persons to whom the Software is furnished to do so, subject to the following * */
/* * conditions: * */
/* * * */
/* * The above copyright notice and this permission notice shall be included in all copies * */
/* * or substantial portions of the Software. * */
/* * * */
/* * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * */
/* * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR * */
/* * PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE * */
/* * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR * */
/* * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * */
/* * DEALINGS IN THE SOFTWARE. * */
/* ********************************************************************************************* */
module TOP(
SYS_CLK,
PB,
USER_LED,
I2C_SCL,
I2C_SDA,
GPIO_A
);
/* Input clock (50 Mhz) */
input SYS_CLK;
/* Push buttons */
input [4:1] PB;
/* LEDs */
output [8:1] USER_LED;
/* SPI: SCLK */
input I2C_SCL;
/* SPI: MOSI */
input I2C_SDA;
/* SPI: MISO */
output GPIO_A;
wire [255:0] wPMosi;
wire [255:0] wPMiso;
wire wPValid;
wire wShaResetN;
wire wShaInit;
wire wShaNext;
wire wShaMode;
wire [511:0] wShaBlock;
wire [255:0] wShaDigest;
wire [1:0] wUserLed;
assign USER_LED = {6'h3f, wUserLed[1], wUserLed[0]};
/* SPI Slave Module */
SPISlaveDelayedResponse#(256, 40) spiinst(
.rst_n(PB[1]),
.s_sclk(I2C_SCL),
.s_mosi(I2C_SDA),
.s_miso(GPIO_A),
.p_mosi(wPMosi),
.p_miso(wPMiso),
.p_valid(wPValid)
);
/* Communication and SHA-256 module manager */
Manager manager(
.clk(SYS_CLK),
.rst_n(PB[1]),
.p_mosi(wPMosi),
.p_miso(wPMiso),
.p_valid(wPValid),
.sha_reset_n(wShaResetN),
.sha_init(wShaInit),
.sha_next(wShaNext),
.sha_mode(wShaMode),
.sha_block(wShaBlock),
.sha_digest(wShaDigest)
);
/* SHA-256 Module */
sha256_core shainst(
.clk(SYS_CLK),
.reset_n(wShaResetN),
.init(wShaInit),
.next(wShaNext),
.mode(wShaMode),
.block(wShaBlock),
.ready(),
.digest(wShaDigest),
.digest_valid()
);
/* Activity LED for SPI */
ActivityLED act1(
.clk(SYS_CLK),
.rst_n(PB[1]),
.sig_in(I2C_SCL),
.led_out(wUserLed[0])
);
/* Activity LED for SHA-256 */
ActivityLED act2(
.clk(SYS_CLK),
.rst_n(PB[1]),
.sig_in(wShaInit),
.led_out(wUserLed[1])
);
endmodule
|
// bsg_delay_line
//
// new settings are delivered via bsg_tag_i
//
// the clock is designed to be atomically updated
// between any of its values without glitching.
//
// the order of components is:
//
// ADT, CDT, FDT --> feedback (and buffer to outside world)
//
// All three stages invert their outputs.
//
// All of the modules have delay circuits that clock their config
// flops right after the signal has passed through. All of them are
// configured to grab the new value after a negedge enters the beginning of
// of the ADT, but of course since the signal is inverted at each stage
// ADT and FDT do it on posege and CDT does it on negedge.
//
// We employ a MUXI4 that is part of the standard cell library
// that we verify to be glitch-free using spice simulation (presumably because it is based on a
// t-gate design). If the MUXI4 were made out of AND-OR circuits, care
// would have to be taken to make sure that the transitions occur when
// either all inputs are 0 or 1 to the MUXI4, depending on the implementation.
// For example, if the mux is AOI, triggered on negedge edge of input clock would
// be okay. Fortunately, we don't have to worry about this (and confirmed by spice.)
//
// We have verified this in TSMC 40 by running with sdf annotations.
//
// Gen 2 specific info (starting with 40nm) MBT 5-26-2018
//
// This Gen 2 clock generator has been slight redesigned in order to address the races
// in the gen 1 design that prevented automation.
//
// We use the bsg_tag_client_unsync implementation in order to reduce the load on
// the internally generated clock. Additionally, we separate out the we_r trigger
// signal so that it is explicitly set. This means that to set the frequency
// on average, three packets will need to be sent. First, a packet will be sent
// to set clock configuration bits. Then a packet will be sent to enable the we_r
// signal. Finally a packet will be sent to clear the we_r signal.
// This applies only for the oscillator programming.
//
// The trigger is synchronized inside the ADT; and then the synchronized signal
// is buffered and passed on to the CDT and then to the FDT, mirroring the
// flow of the clock signal through the units.
//
// The goal of this approach is to ensure that a new value is latched into the
// oscillator's configuration registers atomically, and during the first negative
// clock phase after a positive edge.
//
//
// The downsampler uses the normal interface.
//
//
// Gen 1 specific info (for reference)
//
// There is an implicit race between the bsg_tag's output fb_we_r (clocked on
// positive edge of FDT output) and these config flops that cannot be addressed
// in ICC because we cannot explicitly control timing between ICC-managed
// clocks and our internal oscillator clocks.
//
// A final check must be made on the 5 flops inside the adt / cdt / fdt
// to see that async reset drops and data inputs do not come too close
// to the appropriate clock edge. This could be verified via a script that
// processes the SDF file, but for now we pull the test trace up in DVE and
// manually check these points. Typically, the ADT is the closest
// call, where in MAX timing mode, the data changes about 481 ps before the
// positive edge of the flop's clock. With a setup time on the order of
// 261 ps, there is a slack of 220 ps. This path was originally a problem
// and it fixed by sending the clock out to the BTC at the beginning of
// the FDT as opposed to at the end. This gives more time for propagate
// through the ICC-generate clock tree for the BTC.
//
//
//
//
`timescale 1ps/1ps
`include "bsg_clk_gen.vh"
module bsg_dly_line
import bsg_tag_pkg::bsg_tag_s;
#(parameter num_adgs_p=1)
(
input bsg_tag_s bsg_tag_i
,input bsg_tag_s bsg_tag_trigger_i
,input async_reset_i
,input clk_i
,output clk_o
);
wire fb_clk;
wire async_reset_neg = ~async_reset_i;
`declare_bsg_clk_gen_osc_tag_payload_s(num_adgs_p)
bsg_clk_gen_osc_tag_payload_s tag_r_async;
wire tag_trigger_r_async;
wire adt_to_cdt_trigger_lo, cdt_to_fdt_trigger_lo;
// this is a raw interface; and wires will toggle
// as the bits shift in. the wires are also
// unsynchronized with respect to the target domain.
bsg_tag_client_unsync
#(.width_p($bits(bsg_clk_gen_osc_tag_payload_s))
,.harden_p(1)
) btc
(.bsg_tag_i(bsg_tag_i)
,.data_async_r_o(tag_r_async)
);
bsg_tag_client_unsync
#(.width_p(1)
,.harden_p(1)
) btc_trigger
(.bsg_tag_i(bsg_tag_trigger_i)
,.data_async_r_o(tag_trigger_r_async)
);
wire adt_lo, cdt_lo;
wire fb_clk_del;
// this adds some delay in the loop for RTL simulation
// should be ignored in synthesis
assign #4000 fb_clk_del = fb_clk;
wire clk_inv;
assign clk_inv = ~clk_i;
bsg_rp_clk_gen_atomic_delay_tuner adt
(.i(clk_inv)
,.we_async_i (tag_trigger_r_async )
,.we_inited_i(bsg_tag_trigger_i.en )
,.async_reset_neg_i(async_reset_neg )
,.sel_i(tag_r_async.adg[0] )
,.we_o(adt_to_cdt_trigger_lo )
,.o(adt_lo )
);
// instantatiate CDT (coarse delay tuner)
// this one inverts the output
// captures config state on negative edge of input clock
bsg_rp_clk_gen_coarse_delay_tuner cdt
(.i (adt_lo)
,.we_i (adt_to_cdt_trigger_lo)
,.async_reset_neg_i(async_reset_neg )
,.sel_i (tag_r_async.cdt )
,.we_o (cdt_to_fdt_trigger_lo)
,.o (cdt_lo)
);
// instantiate FDT (fine delay tuner)
// captures config state on positive edge of (inverted) input clk
// non-inverting
bsg_rp_clk_gen_fine_delay_tuner fdt
(.i (cdt_lo)
,.we_i (cdt_to_fdt_trigger_lo)
,.async_reset_neg_i(async_reset_neg)
,.sel_i (tag_r_async.fdt)
,.o (fb_clk) // in the actual critical loop
,.buf_o (clk_o) // outside this module
);
//always @(*)
// $display("%m async_reset_neg=%b fb_clk=%b adg_int=%b fb_tag_r=%b fb_we_r=%b",
// async_reset_neg,fb_clk,adg_int,fb_tag_r,fb_we_r);
endmodule // bsg_clk_gen_osc
`BSG_ABSTRACT_MODULE(bsg_dly_line)
|
//=======================================================
// This code is generated by Terasic System Builder
//=======================================================
module DE0_NANO(
//////////// CLOCK //////////
CLOCK_50,
//////////// LED //////////
LED,
//////////// KEY //////////
KEY,
//////////// SW //////////
SW,
//////////// SDRAM //////////
DRAM_ADDR,
DRAM_BA,
DRAM_CAS_N,
DRAM_CKE,
DRAM_CLK,
DRAM_CS_N,
DRAM_DQ,
DRAM_DQM,
DRAM_RAS_N,
DRAM_WE_N
);
//=======================================================
// PARAMETER declarations
//=======================================================
//=======================================================
// PORT declarations
//=======================================================
//////////// CLOCK //////////
input CLOCK_50;
//////////// LED //////////
output [7:0] LED;
//////////// KEY //////////
input [1:0] KEY;
//////////// SW //////////
input [3:0] SW;
//////////// SDRAM //////////
output [12:0] DRAM_ADDR;
output [1:0] DRAM_BA;
output DRAM_CAS_N;
output DRAM_CKE;
output DRAM_CLK;
output DRAM_CS_N;
inout [15:0] DRAM_DQ;
output [1:0] DRAM_DQM;
output DRAM_RAS_N;
output DRAM_WE_N;
//=======================================================
// REG/WIRE declarations
//=======================================================
//////////// AVALON CONNECTOR //////////
// Read
wire [31:0] read_base;
wire read_go;
wire read_buffer;
wire read_done;
wire read_early_done;
wire read_data_available;
wire [15:0] output_data;
reg [31:0] r_read_address = 32'b0;
reg r_read_en = 1'b0;
reg r_read_buffer;
// Write
wire [31:0] write_base;
wire write_go;
wire write_buffer;
wire write_buffer_full;
wire write_done;
wire [15:0] input_data;
reg [31:0] r_write_address = 32'b0;
reg r_write_en = 1'b0;
reg r_write_buffer;
reg [15:0] r_input_data;
reg [31:0] counter_0 = 32'b0;
reg [31:0] counter_1 = 32'b0;
reg [15:0] r_q = 16'b0;
reg [1:0] key_edge_detect = 2'b00;
reg [7:0] r_write_length = 8'd8; // 64 bit word. NB this MUST match that of the qsys sdram_write
reg [7:0] r_read_length = 8'd8; // 64 bit word. NB this MUST match that of the qsys sdram_read
wire [7:0] write_length;
wire [7:0] read_length;
reg r_reading = 1'b0;
reg r_reading_finished = 1'b1;
//=======================================================
// Structural coding
//=======================================================
qsys u0(
.clk_clk(CLOCK_50),
.reset_reset_n(1'b1),
.sdram_clock_c0_clk(DRAM_CLK),
.sdram_clock_areset_conduit_export(1'b0),
.sdram_wire_addr(DRAM_ADDR),
.sdram_wire_ba(DRAM_BA),
.sdram_wire_cas_n(DRAM_CAS_N),
.sdram_wire_cke(DRAM_CKE),
.sdram_wire_cs_n(DRAM_CS_N),
.sdram_wire_dq(DRAM_DQ),
.sdram_wire_dqm(DRAM_DQM),
.sdram_wire_ras_n(DRAM_RAS_N),
.sdram_wire_we_n(DRAM_WE_N),
.sdram_read_control_fixed_location (1'b1), // do not auto increment address
.sdram_read_control_read_base (read_base),
.sdram_read_control_read_length (read_length),
.sdram_read_control_go (read_go),
.sdram_read_control_done (read_done),
.sdram_read_control_early_done (read_early_done),
.sdram_read_user_read_buffer (read_buffer),
.sdram_read_user_buffer_output_data (output_data),
.sdram_read_user_data_available (read_data_available),
.sdram_write_user_write_buffer (write_buffer),
.sdram_write_user_buffer_input_data (input_data),
.sdram_write_user_buffer_full (write_buffer_full),
.sdram_write_control_fixed_location (1'b1), // do not auto increment address
.sdram_write_control_write_base (write_base),
.sdram_write_control_write_length (write_length),
.sdram_write_control_go (write_go),
.sdram_write_control_done (write_done)
);
assign read_base = r_read_address;
assign read_go = r_read_en;
assign read_buffer = r_read_buffer;
assign write_buffer = r_write_buffer;
assign input_data = r_input_data;
assign write_base = r_write_address;
assign write_go = r_write_en;
assign write_length = r_write_length;
assign read_length = r_read_length;
assign LED = r_q[7:0];
always @(posedge CLOCK_50) begin
key_edge_detect <= {key_edge_detect[0], KEY[1]};
end
// Put some sequencial numbers in memory.
always @(posedge CLOCK_50) begin
if (counter_0 < 32'd255) begin
if (r_write_en) begin
r_write_buffer <= 1'b0;
r_write_en = 1'b0;
r_write_address <= r_write_address + r_write_length;
end else if (write_done && !write_buffer_full) begin
r_input_data <= counter_0[15:0];
r_write_buffer <= 1'b1;
r_write_en = 1'b1;
counter_0 <= counter_0 + 32'b1;
end
end else begin
r_write_en = 1'b0;
r_write_buffer <= 1'b0;
end
end
/*
// Wait for key push to write the next memory.
always @(posedge CLOCK_50) begin
if (counter_0 <= 32'd6) begin
if (key_edge_detect == 2'b01) begin // rising edge of KEY[1]
r_input_data <= counter_0[15:0];
r_write_buffer <= 1'b1;
r_write_en = 1'b1;
end else begin
r_write_en <= 1'b0;
r_write_buffer <= 1'b0;
end
if (key_edge_detect == 2'b10) begin // falling edge of KEY[1]
// Set the address for the next read
r_write_address <= r_write_address + r_write_length;
counter_0 <= counter_0 + 32'b1;
end
end
end
// Wait for key push to read the next memory.
always @(posedge CLOCK_50) begin
if (counter_0 > 32'd6) begin
if (key_edge_detect == 2'b01) begin // rising edge of KEY[1]
// Read from memory
r_read_en <= 1'b1;
//r_reading <= 1'b1;
end else begin
r_read_en <= 1'b0;
end
//if (r_reading_finished) r_reading <= 1'b0;
if (key_edge_detect == 2'b10) begin // falling edge of KEY[1]
// Set the address for the next read
r_read_address <= r_read_address + r_read_length;
end
end
end
*/
/*
// Wait for key push to read the next memory.
always @(posedge CLOCK_50) begin
if (key_edge_detect == 2'b01) begin // rising edge of KEY[1]
// Read from memory
r_read_en <= 1'b1;
//r_reading <= 1'b1;
end else begin
r_read_en <= 1'b0;
end
//if (r_reading_finished) r_reading <= 1'b0;
if (key_edge_detect == 2'b10) begin // falling edge of KEY[1]
// Set the address for the next read
r_read_address <= r_read_address + read_length;
end
end
*/
// Loop through the memory displaying on the leds slowly.
always @(posedge CLOCK_50) begin
if (counter_0 > 32'd254) begin
if (counter_1 > 32'd25000000 && read_done) begin
counter_1 <= 32'd0;
r_read_en <= 1'b1;
end else begin
counter_1 <= counter_1 + 32'b1;
end
if (r_read_en) begin
// Ensure the request only lasts one clock cycle.
r_read_en <= 1'b0;
// Set the next read address
if (r_read_address > 32'd2040) begin
r_read_address <= 32'd0;
end else begin
r_read_address <= r_read_address + r_read_length;
end
end
end
end
/*
// Loop through the memory as fast as possible.
always @(posedge CLOCK_50) begin
if (counter_0 > 32'd254) begin
if (read_done) begin
r_read_en <= 1'b1;
end
if (r_read_en) begin
// Ensure the request only lasts one clock cycle.
r_read_en <= 1'b0;
// Set the next read address
if (r_read_address > 32'd512) begin
r_read_address <= 32'd0;
end else begin
r_read_address <= r_read_address + r_read_length;
end
end
end
end
*/
always @(posedge CLOCK_50) begin
// r_read_buffer MUST only be set for one cycle
if (read_data_available && r_read_buffer == 1'b0) begin
r_q <= output_data;
r_read_buffer <= 1'b1;
//r_reading_finished <= 1'b1;
end else begin
r_read_buffer <= 1'b0;
//r_reading_finished <= 1'b0;
end
end
endmodule
|
`timescale 1ns / 1ps
module dmix_t;
// ins
reg rst;
reg signal;
parameter TclkSPDIF = 40; // 24.576MHz == 192Khz * 32 bit * 2 (biphase)
dmix_top uut(.rst(rst), .spdif_i(signal));
task recv_rawbit;
input wire b;
begin
signal = b;
#(TclkSPDIF);//*6);
end
endtask
task recv_B;
begin
if(signal) begin
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(1);
recv_rawbit(0);
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(1);
end else begin
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(0);
recv_rawbit(1);
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(0);
end
end
endtask
task recv_M;
begin
if(signal) begin
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(0);
recv_rawbit(1);
end else begin
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(1);
recv_rawbit(0);
end
end
endtask
task recv_W;
begin
if(signal) begin
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(0);
recv_rawbit(1);
recv_rawbit(1);
end else begin
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(1);
recv_rawbit(0);
recv_rawbit(0);
end
end
endtask
task recv_bmcbit;
input wire b;
begin
if(signal) begin
if(b) begin
recv_rawbit(0);
recv_rawbit(1);
end else begin
recv_rawbit(0);
recv_rawbit(0);
end
end else begin
if(b) begin
recv_rawbit(1);
recv_rawbit(0);
end else begin
recv_rawbit(1);
recv_rawbit(1);
end
end
end
endtask
task recv_bmcbyte;
input wire [7:0] byte;
begin
recv_bmcbit(byte[0]);
recv_bmcbit(byte[1]);
recv_bmcbit(byte[2]);
recv_bmcbit(byte[3]);
recv_bmcbit(byte[4]);
recv_bmcbit(byte[5]);
recv_bmcbit(byte[6]);
recv_bmcbit(byte[7]);
end
endtask
task recv_bmcctl;
begin
recv_bmcbit(1);
recv_bmcbit(1);
recv_bmcbit(1);
recv_bmcbit(1);
end
endtask
task recv_subframe;
input wire [23:0] data;
begin
recv_bmcbyte(data[7:0]);
recv_bmcbyte(data[15:8]);
recv_bmcbyte(data[23:16]);
recv_bmcctl();
end
endtask
// `define USE_CAPTURE
reg [22:0] counter;
initial begin
$dumpfile("dmix_t.lxt");
$dumpvars(0, uut);
rst = 1'b0;
signal = 0;
counter <= 0;
#(10);
rst = 1'b1;
#(40);
rst = 1'b0;
#(50);
end
`ifndef USE_CAPTURE
always begin
recv_B();
recv_subframe(counter);
counter = counter + 1;
recv_W();
recv_subframe(counter);
counter = counter + 1;
repeat(63) begin
recv_M();
recv_subframe(counter);
counter = counter + 1;
recv_W();
recv_subframe(counter);
counter = counter + 1;
end
$finish(2);
recv_B();
recv_subframe(counter);
counter = counter + 1;
recv_W();
recv_subframe(counter);
counter = counter + 1;
repeat(63) begin
recv_M();
recv_subframe(counter);
counter = counter + 1;
recv_W();
recv_subframe(counter);
counter = counter + 1;
end
if (counter > 512)
$finish(2);
end
`else
reg [31:0] capture [262143:0];
integer capture_iter;
initial $readmemh("spdif_capture3", capture);
initial capture_iter = 0;
always begin
signal = capture[capture_iter][2];
capture_iter = capture_iter + 1;
if (capture_iter > 262143)
$finish(2);
#(5);
end
`endif
endmodule
|
(* %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% *)
(* Mainly borrowed from Sofware Foundations, v.4
$Date: 2015-12-11 17:17:29 -0500 (Fri, 11 Dec 2015) $
Last Update: Tue, 30 May 2017
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% *)
(* ***************************************************************** *)
(** * Maps: Total and Partial Maps *)
(* ***************************************************************** *)
(* ***************************************************************** *)
Require Import Identifier.
Require Import Coq.Arith.Arith.
Require Import Coq.Bool.Bool.
Require Import Coq.Logic.FunctionalExtensionality.
(* for t_update proof *)
Require Import Coq.MSets.MSets.
(** Maps (or dictionaries) are ubiquitous data structures, both in
software construction generally and in the theory of programming
languages in particular.
We'll define two flavors of maps: _total_ maps, which include a
"default" element to be returned when a key being looked up
doesn't exist, and _partial_ maps, which return an [option] to
indicate success or failure. The latter is defined in terms of
the former, using [None] as the default element. *)
(* ################################################################# *)
(** * Total Maps *)
(* ################################################################# *)
(** We build partial maps in two steps. First, we define a type of
_total maps_ that return a default value when we look up a key
that is not present in the map. *)
Definition total_map (A : Type) := id -> A.
(** Intuitively, a total map over an element type [A] _is_ just a
function that can be used to look up [id]s, yielding [A]s.
The function [t_empty] yields an empty total map, given a default
element; this map always returns the default element when applied
to any id. *)
Definition t_empty {A : Type} (v : A) : total_map A :=
(fun _ => v).
(** More interesting is the [update] function, which (as before) takes
a map [m], a key [x], and a value [v] and returns a new map that
takes [x] to [v] and takes every other key to whatever [m] does. *)
Definition t_update {A : Type} (m : total_map A)
(x : id) (v : A)
:= fun x' => if beq_id x x' then v else m x'.
(** For building examples easier, we define a function that creates
total map from a list of pairs.
[xs] : list of pairs, [dv] : default value.
*)
Definition t_from_list {A : Type} (xs : list (id * A)) (dv : A) : total_map A
:= fold_left
(fun m xv => match xv with (x, v) => t_update m x v end)
xs (t_empty dv).
(* ----------------------------------------------------------------- *)
(** ** Properties of Total Maps *)
(* ----------------------------------------------------------------- *)
(** First, the empty map returns its default element for all keys: *)
Lemma t_apply_empty: forall A x v, @t_empty A v x = v.
Proof.
intros A x v.
unfold t_empty. reflexivity.
Qed.
(** Next, if we update a map [m] at a key [x] with a new value [v]
and then look up [x] in the map resulting from the [update], we
get back [v]: *)
Lemma t_update_eq : forall A (m : total_map A) x v,
(t_update m x v) x = v.
Proof.
intros A m x v.
unfold t_update. rewrite <- beq_id_refl. reflexivity.
Qed.
(** On the other hand, if we update a map [m] at a key [x1] and then
look up a _different_ key [x2] in the resulting map, we get the
same result that [m] would have given: *)
Theorem t_update_neq : forall (X : Type) v x1 x2
(m : total_map X),
x1 <> x2 ->
(t_update m x1 v) x2 = m x2.
Proof.
intros X v x1 x2 m.
intros neq. unfold t_update.
apply false_beq_id in neq. rewrite -> neq. reflexivity.
Qed.
(** If we update a map [m] at a key [x] with a value [v1] and then
update again with the same key [x] and another value [v2], the
resulting map behaves the same (gives the same result when applied
to any key) as the simpler map obtained by performing just
the second [update] on [m]: *)
Lemma t_update_shadow : forall A (m : total_map A) v1 v2 x,
t_update (t_update m x v1) x v2
= t_update m x v2.
Proof.
intros A M v1 v2 x.
unfold t_update.
apply functional_extensionality. intros x'.
destruct (beq_id x x') eqn:H.
- (* x = x' *) reflexivity.
- (* x <> x' *) reflexivity.
Qed.
(** Using the example in chapter [IndProp] as a template, use
[beq_idP] to prove the following theorem, which states that if we
update a map to assign key [x] the same value as it already has in
[m], then the result is equal to [m]: *)
Theorem t_update_same : forall X x (m : total_map X),
t_update m x (m x) = m.
Proof.
intros X x m. unfold t_update.
apply functional_extensionality. intro x'.
destruct (beq_idP x x') as [H | H].
- rewrite H. reflexivity.
- reflexivity.
Qed.
(** Use [beq_idP] to prove one final property of the [update]
function: If we update a map [m] at two distinct keys, it doesn't
matter in which order we do the updates. *)
Theorem t_update_permute : forall (X:Type) v1 v2 x1 x2
(m : total_map X),
x2 <> x1 ->
(t_update (t_update m x2 v2) x1 v1)
= (t_update (t_update m x1 v1) x2 v2).
Proof.
intros X v1 v2 x1 x2 m.
intros H. apply beq_id_false_iff in H as H'.
unfold t_update. apply functional_extensionality.
intros x. destruct (beq_idP x1 x) as [H1 | H1].
- destruct (beq_idP x2 x) as [H2 | H2].
+ rewrite <- H1 in H2. apply H in H2. inversion H2.
+ reflexivity.
- destruct (beq_idP x2 x) as [H2 | H2].
+ reflexivity.
+ reflexivity.
Qed.
(* ################################################################# *)
(** * Partial Maps *)
(* ################################################################# *)
(** Finally, we define _partial maps_ on top of total maps. A partial
map with elements of type [A] is simply a total map with elements
of type [option A] and default element [None]. *)
Definition partial_map (A : Type) := total_map (option A).
Definition empty {A : Type} : partial_map A :=
t_empty None.
Definition update {A : Type} (m : partial_map A)
(x : id) (v : A) :=
t_update m x (Some v).
(** Similarly to total maps, we define a function for creating
maps from lists. *)
Definition from_list {A : Type} (xs : list (id * A)) : partial_map A
:= fold_left
(fun m xv => match xv with (x, v) => update m x v end)
xs empty.
(** We can now lift all of the basic lemmas about total maps to
partial maps. *)
Lemma apply_empty : forall A x, @empty A x = None.
Proof.
intros. unfold empty. rewrite t_apply_empty.
reflexivity.
Qed.
Lemma update_eq : forall A (m: partial_map A) x v,
(update m x v) x = Some v.
Proof.
intros. unfold update. rewrite t_update_eq.
reflexivity.
Qed.
Theorem update_neq : forall (X:Type) v x1 x2
(m : partial_map X),
x2 <> x1 ->
(update m x2 v) x1 = m x1.
Proof.
intros X v x1 x2 m H.
unfold update. rewrite t_update_neq. reflexivity.
apply H. Qed.
Lemma update_shadow : forall A (m: partial_map A) v1 v2 x,
update (update m x v1) x v2 = update m x v2.
Proof.
intros A m v1 v2 x1. unfold update. rewrite t_update_shadow.
reflexivity.
Qed.
Theorem update_same : forall X v x (m : partial_map X),
m x = Some v ->
update m x v = m.
Proof.
intros X v x m H. unfold update. rewrite <- H.
apply t_update_same.
Qed.
Theorem update_permute : forall (X:Type) v1 v2 x1 x2
(m : partial_map X),
x2 <> x1 ->
(update (update m x2 v2) x1 v1)
= (update (update m x1 v1) x2 v2).
Proof.
intros X v1 v2 x1 x2 m. unfold update.
apply t_update_permute.
Qed.
Theorem update_permute_get :
forall (X : Type) v1 v2 x1 x2 (m : partial_map X) z,
x2 <> x1 ->
(update (update m x2 v2) x1 v1) z
= (update (update m x1 v1) x2 v2) z.
Proof.
intros X v1 v2 x1 x2 m z.
intros Hneq.
rewrite update_permute. reflexivity. assumption.
Qed.
Theorem update_none :
forall (X : Type) x v (m : partial_map X) y,
(update m x v) y = None ->
m y = None.
Proof.
intros X x v m y H.
destruct (beq_idP x y).
+ subst. rewrite update_eq in H.
inversion H.
+ rewrite update_neq in H; assumption.
Qed.
Theorem eq_Some_not_None :
forall (X : Type) x v (m : partial_map X),
m x = Some v -> m x <> None.
Proof.
intros X x v m Heq contra.
rewrite Heq in contra.
inversion contra.
Qed. |
module Decoder#(parameter DATA_BITS = 8, PARITY_BITS = 4)(
DataParity_in_12p, DataParity_valid_12p,reset_b,clk,
Data_out_14p, EDACerr1_14p,EDACerr2_14p);
// declare the local parameters and signals
localparam k = DATA_BITS;
localparam r = PARITY_BITS;
input wire clk, reset_b, DataParity_valid_12p;
input wire [k+r:1] DataParity_in_12p;
output reg EDACerr1_14p;
output reg EDACerr2_14p;
output reg [k:1] Data_out_14p;
//intermediate signals
reg [r-1:1] syndrome; // required for single error correction
reg [k+r:1] data_in,temp_data;
reg [k:1] data_out;
reg dataparity_valid_int;
reg err1, err2; // flags to detect single/ double errors
// sequential elements
always@(posedge clk or negedge reset_b) begin
if(~reset_b) begin
data_in <= 'd0;
dataparity_valid_int <= 'd0;
err1 <= 'd0; err2 <= 'd0;
Data_out_14p <= 'd0;
EDACerr1_14p <= 1'b0;
EDACerr2_14p <= 1'b0;
end
else if(DataParity_valid_12p) begin
data_in <= DataParity_in_12p;
dataparity_valid_int <= DataParity_valid_12p;
if(dataparity_valid_int) begin
Data_out_14p <= data_out;
EDACerr1_14p <= err1;
EDACerr2_14p <= err2;
end
end
end
// combinational logic syndrome generation
integer i,j,a,l;
integer cnt;
reg P;
always @(data_in) begin
if(reset_b) begin // only if reset is de-asserted
// calculate the parity over entire codeword to detect double bit errors
P = ^(data_in);
temp_data = data_in; //temporary data_in storage
for(i=1;i<r;i=i+1) begin
cnt = 1;
a = cnt[i-1] & data_in[1];
for(cnt=2;cnt<(k+r);cnt=cnt+1) begin
a = a ^ (data_in[cnt] & cnt[i-1]);
end
syndrome[i] = a;
end
// check for errors
if(|(syndrome) && P) begin
// which means 1 bit error present
$display("Inside decoder: One bit error was present at %0d bit, and is corrected",syndrome);
temp_data[syndrome] = ~temp_data[syndrome]; // bit corrected
err1 = 1'b1; err2 = 1'b0;
end
else if(|(syndrome) && ~P) begin
// double error present
$display("Inside decoder: Double bit error was present");
err2 = 1'b1; err1 = 1'b0;
end
else if (~(|syndrome) && ~P)begin
// no error present
$display("Inside decoder: No error was found in the data received");
err1 = 1'b0; err2 = 1'b0;
end
// extract data_out from data_in
j = 1; l = 1;
while ( (l<k+r) || (j<=k)) begin
if ( l == ((~l+1)&l)) begin
l = l+1;
end
else begin
data_out[j] = temp_data[l];
j = j+1; l = l+1;
end
end
if(|(err1))
$display("Inside decoder: Data after correction: %h",data_out);
else
$display("Decoder output: Data: %h",data_out);
end
end
endmodule
|
/*
Code for Setting up ADF4158 PLL Module
By Hsiang-Yi Chung
February, 2016
*/
module PLL_ADF4158(
input clk,
input reset_n,
output reg writeData,
output reg loadEnable,
output pll_clk
);
localparam s0 = 2'b00;
localparam s1 = 2'b01;
localparam s2 = 2'b10;
localparam s3 = 2'b11;
localparam num_registers_to_set = 8;
reg [31:0] writeDataArray [num_registers_to_set - 1:0];
reg [31:0] current_register;
reg [1:0] nextState, state;
reg [4:0] bit_counter;
reg [2:0] register_counter;
reg dec_register_counter, dec_bit_counter;
assign pll_clk = clk;
initial begin
state = s0;
bit_counter = 31;
register_counter = num_registers_to_set - 1;
dec_register_counter = 0;
dec_bit_counter = 0;
loadEnable = 0;
writeDataArray[0] = 32'b1_0000_000011000110_000000000000_000; //reg 0
writeDataArray[1] = 32'b0000_0000000000000_000000000000_001; //reg 1
writeDataArray[2] = 32'b000_0_1111_0_1_1_0_00001_000000000001_010; //reg 2
writeDataArray[3] = 32'b0000000000000000_1_0_00_01_0_0_0_0_0_0_0_011; //reg 3
writeDataArray[4] = 32'b0_00000_0_11_00_11_000000000001_0000_100; //reg 4
writeDataArray[5] = 32'b00_0_0_00_0_0_0_0000_0010010101110010_101; //reg 5 DEV SEL = 0
writeDataArray[6] = 32'b00000000_0_00000011011010110000_110; //reg 6 STEP SEL = 0
writeDataArray[7] = 32'b0000_0000_0000_0000_0000_0000_0000_0_111; //reg 7
end
always @ (negedge clk) begin
if(!reset_n) begin
state <= s0;
end
else begin
state <= nextState;
end
end
always @(negedge clk) begin
if(dec_register_counter == 1) begin
register_counter <= register_counter - 1;
end
if(dec_bit_counter == 1) begin
bit_counter <= bit_counter - 1;
end
end
always @ * begin
dec_bit_counter = 0;
dec_register_counter = 0;
loadEnable = 0;
current_register = writeDataArray[register_counter];
writeData = current_register[bit_counter];
case(state)
s0: begin
dec_bit_counter = 1;
nextState = s1;
end
s1: begin
if(bit_counter == 0) begin
nextState = s2;
end else begin
nextState = s1;
dec_bit_counter = 1;
end
end
s2: begin
loadEnable = 1;
if(register_counter != 0) begin
nextState = s0;
dec_register_counter = 1;
dec_bit_counter = 1;
end else begin
nextState = s3;
end
end
s3: begin
nextState = s3;
end
endcase
end
endmodule
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: book.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module book (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../sprites/book.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../sprites/book.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../sprites/book.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL book.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL book.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL book.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL book.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL book_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL book_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.2
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module AESL_automem_d (
clk,
rst,
ce0,
we0,
address0,
din0,
dout0,
ce1,
we1,
address1,
din1,
dout1,
ready,
done
);
//------------------------Parameter----------------------
localparam
TV_IN = "../tv/cdatafile/c.array_arith.autotvin_d.dat",
TV_OUT = "../tv/rtldatafile/rtl.array_arith.autotvout_d.dat";
//------------------------Local signal-------------------
parameter DATA_WIDTH = 32'd 32;
parameter ADDR_WIDTH = 32'd 3;
parameter DEPTH = 32'd 5;
parameter DLY = 0.1;
// Input and Output
input clk;
input rst;
input ce0, ce1;
input we0, we1;
input [ADDR_WIDTH - 1 : 0] address0, address1;
input [DATA_WIDTH - 1 : 0] din0, din1;
output reg [DATA_WIDTH - 1 : 0] dout0, dout1;
input ready;
input done;
// Inner signals
reg [DATA_WIDTH - 1 : 0] mem [0 : DEPTH - 1];
initial begin : initialize_mem
integer i;
for (i = 0; i < DEPTH; i = i + 1) begin
mem[i] = 0;
end
end
reg writed_flag;
event write_process_done;
//------------------------Task and function--------------
task read_token;
input integer fp;
output reg [127 :0] token;
integer ret;
begin
token = "";
ret = 0;
ret = $fscanf(fp,"%s",token);
end
endtask
//------------------------Read array-------------------
// Read data form file to array
initial begin : read_file_process
integer fp;
integer err;
integer ret;
reg [127 : 0] token;
reg [ 8*5 : 1] str;
reg [ DATA_WIDTH - 1 : 0 ] mem_tmp;
integer transaction_idx;
integer i;
transaction_idx = 0;
wait(rst === 0);
@(write_process_done);
fp = $fopen(TV_IN,"r");
if(fp == 0) begin // Failed to open file
$display("Failed to open file \"%s\"!", TV_IN);
$finish;
end
read_token(fp, token);
if (token != "[[[runtime]]]") begin // Illegal format
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
read_token(fp, token);
while (token != "[[[/runtime]]]") begin
if (token != "[[transaction]]") begin
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
read_token(fp, token); // skip transaction number
while(ready == 0) begin
@(write_process_done);
end
for(i = 0; i < DEPTH; i = i + 1) begin
read_token(fp, token);
ret = $sscanf(token, "0x%x", mem_tmp);
mem[i] = mem_tmp;
if (ret != 1) begin
$display("Failed to parse token!");
$finish;
end
end
@(write_process_done);
read_token(fp, token);
if(token != "[[/transaction]]") begin
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
read_token(fp, token);
transaction_idx = transaction_idx + 1;
end
$fclose(fp);
end
// Read data from array to RTL
always @ (posedge clk or rst) begin
if(rst === 1) begin
dout0 <= 0;
end
else begin
if((we0 == 0) && (ce0 == 1) && (ce1 == 1) && (we1 == 1) && (address0 == address1))
dout0 <= #DLY din1;
else if(ce0 == 1)
dout0 <= #DLY mem[address0];
else ;
end
end
always @ (posedge clk or rst) begin
if(rst === 1) begin
dout1 <= 0;
end
else begin
if((we0 == 1) && (ce0 == 1) && (ce1 == 1) && (we1 == 0) && (address0 == address1))
dout1 <= #DLY din0;
else if(ce1 == 1)
dout1 <= #DLY mem[address1];
else ;
end
end
//------------------------Write array-------------------
// Write data from RTL to array
always @ (posedge clk) begin
if((we0 == 1) && (ce0 == 1) && (ce1 == 1) && (we1 == 1) && (address0 == address1))
mem[address0] <= #DLY din1;
else if ((we0 == 1) && (ce0 == 1))
mem[address0] <= #DLY din0;
end
always @ (posedge clk) begin
if((ce1 == 1) && (we1 == 1))
mem[address1] <= #DLY din1;
end
// Write data from array to file
initial begin : write_file_proc
integer fp;
integer transaction_num;
reg [ 8*5 : 1] str;
integer i;
transaction_num = 0;
writed_flag = 1;
wait(rst === 0);
@(negedge clk);
while(1) begin
while(done == 0) begin
-> write_process_done;
@(negedge clk);
end
fp = $fopen(TV_OUT, "a");
if(fp == 0) begin // Failed to open file
$display("Failed to open file \"%s\"!", TV_OUT);
$finish;
end
$fdisplay(fp, "[[transaction]] %d", transaction_num);
for (i = 0; i < DEPTH; i = i + 1) begin
$fdisplay(fp,"0x%x",mem[i]);
end
$fdisplay(fp, "[[/transaction]]");
transaction_num = transaction_num + 1;
$fclose(fp);
writed_flag = 1;
-> write_process_done;
@(negedge clk);
end
end
//------------------------conflict check-------------------
always @ (posedge clk) begin
if ((we0 == 1) && (ce0 == 1) && (ce1 == 1) && (we1 == 1) && (address0 == address1))
$display($time,"WARNING:write conflict----port0 and port1 write to the same address:%h at the same clock. Port1 has the high priority.",address0);
end
always @ (posedge clk) begin
if ((we0 == 1) && (ce0 == 1) && (ce1 == 1) && (we1 == 0) && (address0 == address1))
$display($time,"NOTE:read & write conflict----port0 write and port1 read to the same address:%h at the same clock. Write first Mode.",address0);
end
always @ (posedge clk) begin
if ((we0 == 0) && (ce0 == 1) && (ce1 == 1) && (we1 == 1) && (address0 == address1))
$display($time,"NOTE:read & write conflict----port0 read and port1 write to the same address:%h at the same clock. Write first Mode.",address0);
end
endmodule
|
//# 36 inputs
//# 39 outputs
//# 211 D-type flipflops
//# 3570 inverters
//# 2027 gates (955 ANDs + 528 NANDs + 431 ORs + 113 NORs)
module s9234(GND,VDD,CK,g102,g107,g1290,g1293,g22,g23,g2584,g301,g306,g310,
g314,g319,g32,
g3222,g36,g3600,g37,g38,g39,g40,g4098,g4099,g41,g4100,g4101,g4102,g4103,
g4104,g4105,g4106,g4107,g4108,g4109,g4110,g4112,g4121,g42,g4307,g4321,g44,
g4422,g45,g46,g47,g4809,g5137,g5468,g5469,g557,g558,g559,g560,g561,g562,g563,
g564,g567,g5692,g6282,g6284,g6360,g6362,g6364,g6366,g6368,g6370,g6372,g6374,
g639,g6728,g702,g705,g89,g94,g98);
input GND,VDD,CK,g89,g94,g98,g102,g107,g301,g306,g310,g314,g319,g557,g558,g559,
g560,g561,
g562,g563,g564,g705,g639,g567,g45,g42,g39,g702,g32,g38,g46,g36,g47,g40,g37,
g41,g22,g44,g23;
output g2584,g3222,g3600,g4307,g4321,g4422,g4809,g5137,g5468,g5469,g5692,g6282,
g6284,g6360,g6362,g6364,g6366,g6368,g6370,g6372,g6374,g6728,g1290,g4121,
g4108,g4106,g4103,g1293,g4099,g4102,g4109,g4100,g4112,g4105,g4101,g4110,
g4104,g4107,g4098;
wire g678,g4130,g332,g6823,g123,g6940,g207,g6102,g695,g4147,g461,g4841,g18,
g6725,g292,g3232,g331,g4119,g689,g4141,g24,g6726,g465,g6507,g84,g6590,g291,
g3231,g676,g5330,g622,g5147,g117,g4839,g278,g6105,g128,g5138,g598,g4122,
g554,g6827,g496,g6745,g179,g6405,g48,g6729,g590,g6595,g551,g6826,g682,
g4134,g11,g6599,g606,g4857,g188,g6406,g646,g5148,g327,g4117,g361,g6582,
g289,g3229,g398,g5700,g684,g4136,g619,g4858,g208,g5876,g248,g3239,g390,
g5698,g625,g5328,g681,g4133,g437,g4847,g276,g5877,g3,g6597,g323,g4120,g224,
g3235,g685,g4137,g43,g6407,g157,g5470,g282,g6841,g697,g4149,g206,g6101,
g449,g4844,g118,g4113,g528,g6504,g284,g3224,g426,g4855,g634,g4424,g669,
g5582,g520,g6502,g281,g6107,g175,g5472,g15,g6602,g631,g5581,g69,g6587,g693,
g4145,g337,g2585,g457,g4842,g486,g2586,g471,g1291,g328,g4118,g285,g3225,
g418,g4853,g402,g4849,g297,g6512,g212,g3233,g410,g4851,g430,g4856,g33,
g6854,g662,g1831,g453,g4843,g269,g6510,g574,g6591,g441,g4846,g664,g1288,
g349,g5478,g211,g6840,g586,g6594,g571,g5580,g29,g6853,g326,g4840,g698,
g4150,g654,g5490,g293,g6511,g690,g4142,g445,g4845,g374,g5694,g6,g6722,g687,
g4139,g357,g5480,g386,g5697,g504,g6498,g665,g4126,g166,g5471,g541,g6505,
g74,g6588,g338,g5475,g696,g4148,g516,g6501,g536,g6506,g683,g4135,g353,
g5479,g545,g6824,g254,g3240,g341,g5476,g290,g3230,g2,g6721,g287,g3227,g336,
g6925,g345,g5477,g628,g5489,g679,g4131,g28,g6727,g688,g4140,g283,g6842,
g613,g4423,g10,g6723,g14,g6724,g680,g4132,g143,g6401,g672,g5491,g667,g4127,
g366,g6278,g279,g6106,g492,g6744,g170,g6404,g686,g4138,g288,g3228,g638,
g1289,g602,g4123,g642,g4658,g280,g5878,g663,g4125,g610,g4124,g148,g5874,
g209,g6103,g675,g1294,g478,g1292,g122,g4115,g54,g6584,g594,g6596,g286,
g3226,g489,g2587,g616,g4657,g79,g6589,g218,g3234,g242,g3238,g578,g6592,
g184,g5473,g119,g4114,g668,g6800,g139,g5141,g422,g4854,g210,g6839,g394,
g5699,g230,g3236,g25,g6601,g204,g5875,g658,g4425,g650,g5329,g378,g5695,
g508,g6499,g548,g6825,g370,g5693,g406,g4850,g236,g3237,g500,g6497,g205,
g6100,g197,g6509,g666,g4128,g114,g4116,g524,g6503,g260,g3241,g111,g6277,
g131,g5139,g7,g6598,g19,g6600,g677,g4129,g582,g6593,g485,g6801,g699,g4426,
g193,g5474,g135,g5140,g382,g5696,g414,g4852,g434,g4848,g266,g4659,g49,
g6583,g152,g6402,g692,g4144,g277,g6104,g127,g6941,g161,g6403,g512,g6500,
g532,g6508,g64,g6586,g694,g4146,g691,g4143,g1,g6720,g59,g6585,I8854,g6696,
I2272,I9125,g6855,I6783,g4822,I4424,g2097,g6895,I9152,g1835,I2919,I3040,
g1770,g6837,g6822,I7466,g5624,I4809,g2974,g3537,I4757,g5457,g5304,g6062,
g5824,g4040,I5343,I6001,g4162,g5549,g5331,I4477,g3063,g3612,I7055,g5318,
g2892,g1982,I5264,g3638,I2225,I5451,g4323,g4086,g908,I1932,I5933,g4346,
I8252,g6294,I2473,g971,I7333,g5386,I8812,g6688,g1674,g985,I3528,g1422,
I8958,g6774,I5050,g3246,I4501,I2324,g1209,g2945,I4133,g5121,I6775,g1997,
g1398,g3128,I4375,I8005,g6110,g1541,g1094,g5670,g5527,g2738,g2327,I9047,
g4528,I6096,g2244,I3379,g6192,g5946,g2709,I3864,g1332,I2349,g4530,I6102,
g1680,g1011,g2078,g1345,I2215,I3010,g1504,g5813,I7612,I7509,g5587,I5379,
g3940,g3800,g3388,g2907,g1914,I9085,g2035,I3144,g2959,g1861,I9236,g4010,
g3601,I2287,g927,I4273,g2197,I8270,g6300,g5740,I7501,I5777,g3807,g2876,
g1943,g873,I6525,I5882,g3871,g2656,I3800,I8473,g6485,I2199,g900,I1927,
g6708,I8834,I2399,g729,I3278,g1695,g6520,I8476,g940,I6677,g4757,g3902,
g3575,g5687,g5567,g2915,g1931,g847,I3235,g1807,I3343,g1623,g6431,I8295,
g709,g6812,I8984,I6576,g4700,g749,I1847,g3090,I4331,I9107,g2214,I3349,
g4618,g4246,g6376,g6267,I5511,I6349,g4569,g4343,g4011,I5674,g4003,I8177,
g6173,g2110,g1381,I3134,g1336,I8229,I3334,g1330,I7197,g5431,g4566,g4198,
I7397,g5561,I4534,g2858,g1714,g1110,I4961,g3597,g2663,g2308,g3456,g2640,
I6801,g922,I1947,g4693,I6283,I5484,g5570,g5392,g5860,g5634,g4334,g3733,
I3804,g2575,I2207,I5153,g3330,g3355,g3100,g5645,g5537,g6733,I8891,g5691,
g5568,g4804,g4473,g6838,I4414,g2090,g6610,I8696,g2877,g2434,I4903,g3223,
g6796,I4288,I3313,g1337,g5879,g5770,g3463,g2682,I4513,g2765,I2578,g5358,
I7012,I3202,g1812,I5421,g1076,I2115,g6069,g5791,I7817,g5924,g6540,g6474,
I6352,g4564,I1865,g4202,I5622,I6867,g5082,g3876,I7349,I8144,g6182,g1175,
g1375,I2411,g3118,I4366,g3318,I4593,g2464,I3596,g3872,g3312,g4494,I6004,
I2870,g1161,g4518,I6066,g2215,g5615,I7372,g4567,I6139,I4382,g2265,I3776,
g2044,g3057,I4282,I5600,g3821,I3593,g1295,I2825,g1143,g1285,g852,g3457,
g2653,g5174,g5099,I6386,g4462,I3965,g2268,I8488,g6426,g6849,I9074,I6599,
g4823,I2408,g719,g3834,I5027,g2295,g1578,g1384,I2420,g1339,I2370,g5545,
I6170,I9128,g6864,g6898,I9161,g1838,g1595,g6900,I9167,g2194,I3331,g6797,
I8961,g2394,I3537,I3050,g1439,I3641,g1491,I2943,g1715,I5736,g4022,I8450,
I6280,g4430,g4933,I6625,g5420,I7086,g4521,I6075,g1672,I7058,g5281,I2887,
g1123,I2122,g1477,g952,I4495,I2228,g5794,I7593,g1643,I2608,g3022,I4437,
g2108,g2705,I3858,g3813,g3258,I8650,g6529,g1647,g2242,I3373,g1205,I2033,
I5871,g3744,g774,I1859,g6819,I8994,g6694,I8800,g4379,I5848,g5905,g5852,
g3519,g2740,I7856,g5994,g921,g1551,g1742,I2756,I4752,g2859,g6488,g6367,
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g3662,g6643,g3290,g6634,g6545,g2113,g1576,g6099,g3181,g3381,g3685,g3700,
g3421,g2846,g5569,g5348,g4597,g6613,g6554,g4739,g2850,g6269,g4937,g4668,
g4642,g4638,g3631,g2160,g4390,g3301,g4156,g3926,g4942,g5183,g5023,g3935,
g4363,g4032,g4053,g4453,g4238,g5161,g3669,g5361,g3368,g6135,g5665,g6831,
g4544,g6288,g4357,g3990,g5146,g6916,g5633,g6749,g6798,g4946,g6781,g5944,
g5778,g5240,g5043,g3941,g2307,g6302,g6719,g1570,g4683,g4585,g5681,g3688,
g4735,g2018,g6265,g4782,g4661,g4637,g4634,g4949,g3326,g6770,g6754,g3760,
g5936,g4039,g5317,g3383,g5601,g3608,g3924,g4583,g3161,g2339,g3361,g4616,
g4231,g3665,g3127,g3327,g3146,g3633,g5937,g5775,g3103,g3303,g5668,g6338,
g6251,g5190,g5501,g5156,g5356,g5265,g5942,g4789,g3316,g5954,g5163,g6098,
g3147,g5363,g3681,g5053,g4599,g3697,g5157,g5357,g4244,g4340,g3972,g3117,
g3317,g4035,g6086,g4214,g1822,g1620,g3784,g2916,g3479,g6131,g3668,g6331,
g3891,g4236,g3907,g3294,g5949,g3190,g6766,g3156,g3356,g5646,g2873,g1845,
g6748,g5603,g5504,g5484,g4928,g3704,g4464,g4272,g4785,g6091,g3810,g5952,
g5616,g5505,g6718,g6767,g3157,g3357,g4489,g2770,g5503,g3626,g4038,g5617,
g3683,g4836,g3661,g6247,g3627,g5945,g2808,g2009,g3292,g3646,g2759,g6910,
g3603,g3484,g5482,g3702,g6066,g5214,g3616,g6055,g6133,g5663,g6333,g3896,
g3764,g5402,g5236,g4708,g5556,g5015,g3277,g3617,g6093,g2897,g6256,g6816,
g4829,g6263,g4874,g3709,g5557,g5016,g3340,g6631,g3522,g4177,g3933,g5948,
g5779,g4377,g3690,g5955,g5782,g5350,g5325,g5438,g5224,g2868,g1316,g3310,
g4797,g5212,g3663,g2793,g2015,g4344,g3981,g5229,g6772,g3762,g4694,g1481,
g4578,g3657,g2721,g4488,g4701,g4596,g3928,g3899,g3464,g5620,g5507,g4870,
g4779,g3295,g2671,g2263,g3089,g3489,g2607,g5192,g5485,g5941,g5777,g4230,
g3756,g6126,g6326,g3833,g4033,g2758,g3350,g6924,g6920,g6919,g5176,g4395,
g5376,g5911,g5817,g6127,g6327,g3884,g5225,g4342,g3978,g6146,g6346,g6274,
g4354,I5352,g3529,g3531,g3535,g3538,g5177,g6240,g4205,g3620,g1027,g2685,
g2700,g6316,g3855,g5898,g5800,g4401,g1514,g5900,g5804,g2950,g2156,g5245,
g1763,g4828,g3298,g4830,g5144,g4592,g6914,g2101,g5488,g4932,g1416,g5683,
g6317,g3862,g5215,g4864,g5951,g5780,g4677,g4652,g4646,g3176,g3376,g3286,
g3765,g4349,g6060,g3518,g3521,g3526,g3530,g3610,g6739,g3324,g6079,g5122,
g3377,g4352,g3988,g4867,g4811,g6156,g3287,g5096,g4186,g3973,g5496,g5446,
g6250,g4280,g3144,g3344,g5142,g3819,g6912,g6157,g5481,g3701,g5497,g5447,
g5154,g5354,g5249,g4461,g4241,g4756,I5351,g5218,g3650,g4345,g3982,g3336,
g4359,g3806,g2024,g3905,g3887,g3276,g3122,g2435,g2732,g4047,g6646,g3433,
g905,g5953,g5781,g6084,g6603,g5677,g3195,g3337,g5349,g5324,g5198,g5398,
g6647,g1691,g3692,g3154,g4800,g5152,g6320,g3869,g5211,g4860,g5186,g5599,
g4490,g3293,g6771,g6758,g3329,g5170,g5091,g4456,g3829,g4348,g3987,g4355,
g5939,g5776,g2294,g4698,g4586,g5483,g3703,g6738,g6244,g2356,g6140,g6340,
g6257,g5187,g6082,g4057,g5904,g5812,g5200,g4457,g4261,g5241,g3349,g2053,
g5145,g6915,g4834,g4686,g4590,g5191,g3699,g4598,g5637,g5159,g5359,g3644,
g3319,g3352,g5047,g3954,g2311,g3186,g3170,g3614,g3325,g4341,g3977,g2782,
g3280,g4691,g4581,g5935,g2949,g3511,g3517,g3520,g3525,g5234,g3636,g2292,
g6089,g6731,g6717,g4427,g6557,g4358,g3991,g2084,g5213,g4862,g6254,g6150,
g5902,g5808,g3145,g3345,g6773,g3763,g3191,g4180,g3929,g5166,g3637,g4832,
g6769,g3307,g3359,g3757,g3315,g3642,g3654,g5619,I8376,I8393,I8394,I8395,
I8377,g5659,g2100,g1582,g5374,g3598,I8136,g5666,I8137,g6280,I9057,I8081,
I9064,I9065,I9066,g5372,I8129,I8367,I8368,I8369,I8370,g4243,g5202,g4000,
I8349,I8345,I8346,I8347,I8348,g6703,I8119,g5674,g6747,I8211,I8386,g5680,
g6358,I8387,g6281,I8385,I8359,g4233,g5672,g5048,I8128,I7970,I7987,I8118,
g1589,I8358,g6659,g6073,g6741,g6929,g3992,g5678,g2080,I7980,I8360,I8356,
I8357,I8379,g6357,g5066,I8209,g5662,I7972,I9059,g6279,g5669,g5368,I7979,
g4936,g6926,I8378,I8135,g3012,g6400,g6927,g6660,I8208,g3028,I8138,I9058,
g5060,g4819,I7978,I7989,I7971,g3215,I8774,g3503,I7969,g4941,I7988,I8080,
g6669,I8126,g5062,g6359,I8779,I7981,I8127,I8778,I8210,g5377,I8117,I8079,
g6335,g5065,g2995,g2095,g1573,g6683,g5676,I8773,g4432,g5068,I7990,I8120,
g2067,g4234,g5227,I8082,g5370,g3013,g6740,g6928,g2951,g6705,g6075,g5367,
I7217,I7216,I7571,I7569,I2073,I2072,I2796,I2795,g948,I2014,I2015,I4205,
I4203,I3875,I3874,g3109,I5536,I5537,I5658,g3983,I5657,I2527,I2528,I4444,
I5271,I5269,I2898,I2897,I2797,I2245,I2244,I3988,I2543,I2544,I1963,I1961,
I5209,I5207,I7562,I7231,I7232,I6744,I6745,I4182,I6186,g4301,I6185,I7441,
I7439,I6026,g4223,g4221,I2768,I2766,I3933,g2731,I3894,I3895,I7238,I7239,
I4160,I4161,I2934,I2933,I3179,I3177,I6187,g3955,I6027,I4233,g2769,I3953,
I3954,g1044,I2081,I2082,g4674,I6391,g4504,I6390,g4680,I2080,I8195,I8194,
g1534,I2498,I2499,I2497,g1042,g1036,g939,I1987,I1988,I2061,I2062,I2676,
I2674,I2767,I7528,I7529,I7434,I7432,I2074,I7210,I7208,I6964,I6962,I5208,
I5302,I5300,I7535,I7536,I6195,I6196,I2542,I1994,I4445,I2060,I5189,I5187,
I3178,I4920,I4919,I2003,I3916,I3914,I5309,I5307,I5759,I6659,g4762,I4940,
I4939,I2935,I3412,I3413,I3411,I3189,I3188,I3990,I4151,I4152,I2090,I2089,
g5862,I9050,I5766,g3961,g3957,g3968,I5227,I5228,I7527,I5226,g4049,I7224,
I7223,I5767,I5535,g2944,I4921,I6028,I7244,I5188,I5270,I9051,I9052,I5308,
I2506,g1047,I3445,I3169,I3170,g1540,I3168,I7556,I7555,I5196,I5195,I7563,
I7440,I2507,I1995,I3446,I3447,I7237,g2757,I3934,I3935,I6743,I4183,I7557,
I2300,I2299,I5197,I4159,I3741,I3739,I6660,I6661,I5257,I2526,I5301,I4204,
I7218,I6175,I3455,I6500,I6499,I3846,I4210,I6474,I6475,g2698,I3847,I3848,
g1518,I7520,I4784,I4782,I1952,I1951,I8202,I8201,I1986,I5760,I5768,I1970,
I1969,I7225,I7209,I2301,I7245,I3740,I6963,I3456,I3457,I3126,I3125,I3400,
I3398,I4526,I4527,I4528,g2795,I6176,I6177,I7230,I7433,I3127,I4234,I4235,
I5784,I5782,I7550,I7548,I4546,I4545,I5294,I5292,g937,I1979,I1980,g4472,
g1473,g1470,g1459,g928,I1962,I7097,I4547,I3697,I7312,I7311,I2109,I2110,
I2013,g2804,I4009,I4010,g5863,I2022,I2021,I7576,g5688,I3190,I3952,I7549,
I7577,I5647,g3974,I1978,I7246,I4150,g3621,I4008,I2675,g926,I1953,I3893,
I4212,I7313,I2108,I5244,I5242,I7534,I7522,I7521,I6194,I3970,I4941,g3979,
I7542,I7541,I2682,I2681,I4211,I3876,I2091,I3915,I4783,I7543,g930,I1971,
I7570,I5293,I2246,I6392,g944,I2004,I2005,I6473,g2719,I8203,I2899,g941,
I1996,I2508,g2745,g2791,I3989,I8196,I5259,g1560,g4610,I6501,I3399,I3698,
I3699,g950,I2023,I4446,I5783,g2940,I5761,I3972,I7098,I7099,g2780,I3971,
I5258,I7564,I5648,I5649,I5243,I2683,I7578,I5659,I4184,g3528,g3664,g3656,
g3647,g1449,g1418,g1879;
dff DFF_0(CK,g678,g4130);
dff DFF_1(CK,g332,g6823);
dff DFF_2(CK,g123,g6940);
dff DFF_3(CK,g207,g6102);
dff DFF_4(CK,g695,g4147);
dff DFF_5(CK,g461,g4841);
dff DFF_6(CK,g18,g6725);
dff DFF_7(CK,g292,g3232);
dff DFF_8(CK,g331,g4119);
dff DFF_9(CK,g689,g4141);
dff DFF_10(CK,g24,g6726);
dff DFF_11(CK,g465,g6507);
dff DFF_12(CK,g84,g6590);
dff DFF_13(CK,g291,g3231);
dff DFF_14(CK,g676,g5330);
dff DFF_15(CK,g622,g5147);
dff DFF_16(CK,g117,g4839);
dff DFF_17(CK,g278,g6105);
dff DFF_18(CK,g128,g5138);
dff DFF_19(CK,g598,g4122);
dff DFF_20(CK,g554,g6827);
dff DFF_21(CK,g496,g6745);
dff DFF_22(CK,g179,g6405);
dff DFF_23(CK,g48,g6729);
dff DFF_24(CK,g590,g6595);
dff DFF_25(CK,g551,g6826);
dff DFF_26(CK,g682,g4134);
dff DFF_27(CK,g11,g6599);
dff DFF_28(CK,g606,g4857);
dff DFF_29(CK,g188,g6406);
dff DFF_30(CK,g646,g5148);
dff DFF_31(CK,g327,g4117);
dff DFF_32(CK,g361,g6582);
dff DFF_33(CK,g289,g3229);
dff DFF_34(CK,g398,g5700);
dff DFF_35(CK,g684,g4136);
dff DFF_36(CK,g619,g4858);
dff DFF_37(CK,g208,g5876);
dff DFF_38(CK,g248,g3239);
dff DFF_39(CK,g390,g5698);
dff DFF_40(CK,g625,g5328);
dff DFF_41(CK,g681,g4133);
dff DFF_42(CK,g437,g4847);
dff DFF_43(CK,g276,g5877);
dff DFF_44(CK,g3,g6597);
dff DFF_45(CK,g323,g4120);
dff DFF_46(CK,g224,g3235);
dff DFF_47(CK,g685,g4137);
dff DFF_48(CK,g43,g6407);
dff DFF_49(CK,g157,g5470);
dff DFF_50(CK,g282,g6841);
dff DFF_51(CK,g697,g4149);
dff DFF_52(CK,g206,g6101);
dff DFF_53(CK,g449,g4844);
dff DFF_54(CK,g118,g4113);
dff DFF_55(CK,g528,g6504);
dff DFF_56(CK,g284,g3224);
dff DFF_57(CK,g426,g4855);
dff DFF_58(CK,g634,g4424);
dff DFF_59(CK,g669,g5582);
dff DFF_60(CK,g520,g6502);
dff DFF_61(CK,g281,g6107);
dff DFF_62(CK,g175,g5472);
dff DFF_63(CK,g15,g6602);
dff DFF_64(CK,g631,g5581);
dff DFF_65(CK,g69,g6587);
dff DFF_66(CK,g693,g4145);
dff DFF_67(CK,g337,g2585);
dff DFF_68(CK,g457,g4842);
dff DFF_69(CK,g486,g2586);
dff DFF_70(CK,g471,g1291);
dff DFF_71(CK,g328,g4118);
dff DFF_72(CK,g285,g3225);
dff DFF_73(CK,g418,g4853);
dff DFF_74(CK,g402,g4849);
dff DFF_75(CK,g297,g6512);
dff DFF_76(CK,g212,g3233);
dff DFF_77(CK,g410,g4851);
dff DFF_78(CK,g430,g4856);
dff DFF_79(CK,g33,g6854);
dff DFF_80(CK,g662,g1831);
dff DFF_81(CK,g453,g4843);
dff DFF_82(CK,g269,g6510);
dff DFF_83(CK,g574,g6591);
dff DFF_84(CK,g441,g4846);
dff DFF_85(CK,g664,g1288);
dff DFF_86(CK,g349,g5478);
dff DFF_87(CK,g211,g6840);
dff DFF_88(CK,g586,g6594);
dff DFF_89(CK,g571,g5580);
dff DFF_90(CK,g29,g6853);
dff DFF_91(CK,g326,g4840);
dff DFF_92(CK,g698,g4150);
dff DFF_93(CK,g654,g5490);
dff DFF_94(CK,g293,g6511);
dff DFF_95(CK,g690,g4142);
dff DFF_96(CK,g445,g4845);
dff DFF_97(CK,g374,g5694);
dff DFF_98(CK,g6,g6722);
dff DFF_99(CK,g687,g4139);
dff DFF_100(CK,g357,g5480);
dff DFF_101(CK,g386,g5697);
dff DFF_102(CK,g504,g6498);
dff DFF_103(CK,g665,g4126);
dff DFF_104(CK,g166,g5471);
dff DFF_105(CK,g541,g6505);
dff DFF_106(CK,g74,g6588);
dff DFF_107(CK,g338,g5475);
dff DFF_108(CK,g696,g4148);
dff DFF_109(CK,g516,g6501);
dff DFF_110(CK,g536,g6506);
dff DFF_111(CK,g683,g4135);
dff DFF_112(CK,g353,g5479);
dff DFF_113(CK,g545,g6824);
dff DFF_114(CK,g254,g3240);
dff DFF_115(CK,g341,g5476);
dff DFF_116(CK,g290,g3230);
dff DFF_117(CK,g2,g6721);
dff DFF_118(CK,g287,g3227);
dff DFF_119(CK,g336,g6925);
dff DFF_120(CK,g345,g5477);
dff DFF_121(CK,g628,g5489);
dff DFF_122(CK,g679,g4131);
dff DFF_123(CK,g28,g6727);
dff DFF_124(CK,g688,g4140);
dff DFF_125(CK,g283,g6842);
dff DFF_126(CK,g613,g4423);
dff DFF_127(CK,g10,g6723);
dff DFF_128(CK,g14,g6724);
dff DFF_129(CK,g680,g4132);
dff DFF_130(CK,g143,g6401);
dff DFF_131(CK,g672,g5491);
dff DFF_132(CK,g667,g4127);
dff DFF_133(CK,g366,g6278);
dff DFF_134(CK,g279,g6106);
dff DFF_135(CK,g492,g6744);
dff DFF_136(CK,g170,g6404);
dff DFF_137(CK,g686,g4138);
dff DFF_138(CK,g288,g3228);
dff DFF_139(CK,g638,g1289);
dff DFF_140(CK,g602,g4123);
dff DFF_141(CK,g642,g4658);
dff DFF_142(CK,g280,g5878);
dff DFF_143(CK,g663,g4125);
dff DFF_144(CK,g610,g4124);
dff DFF_145(CK,g148,g5874);
dff DFF_146(CK,g209,g6103);
dff DFF_147(CK,g675,g1294);
dff DFF_148(CK,g478,g1292);
dff DFF_149(CK,g122,g4115);
dff DFF_150(CK,g54,g6584);
dff DFF_151(CK,g594,g6596);
dff DFF_152(CK,g286,g3226);
dff DFF_153(CK,g489,g2587);
dff DFF_154(CK,g616,g4657);
dff DFF_155(CK,g79,g6589);
dff DFF_156(CK,g218,g3234);
dff DFF_157(CK,g242,g3238);
dff DFF_158(CK,g578,g6592);
dff DFF_159(CK,g184,g5473);
dff DFF_160(CK,g119,g4114);
dff DFF_161(CK,g668,g6800);
dff DFF_162(CK,g139,g5141);
dff DFF_163(CK,g422,g4854);
dff DFF_164(CK,g210,g6839);
dff DFF_165(CK,g394,g5699);
dff DFF_166(CK,g230,g3236);
dff DFF_167(CK,g25,g6601);
dff DFF_168(CK,g204,g5875);
dff DFF_169(CK,g658,g4425);
dff DFF_170(CK,g650,g5329);
dff DFF_171(CK,g378,g5695);
dff DFF_172(CK,g508,g6499);
dff DFF_173(CK,g548,g6825);
dff DFF_174(CK,g370,g5693);
dff DFF_175(CK,g406,g4850);
dff DFF_176(CK,g236,g3237);
dff DFF_177(CK,g500,g6497);
dff DFF_178(CK,g205,g6100);
dff DFF_179(CK,g197,g6509);
dff DFF_180(CK,g666,g4128);
dff DFF_181(CK,g114,g4116);
dff DFF_182(CK,g524,g6503);
dff DFF_183(CK,g260,g3241);
dff DFF_184(CK,g111,g6277);
dff DFF_185(CK,g131,g5139);
dff DFF_186(CK,g7,g6598);
dff DFF_187(CK,g19,g6600);
dff DFF_188(CK,g677,g4129);
dff DFF_189(CK,g582,g6593);
dff DFF_190(CK,g485,g6801);
dff DFF_191(CK,g699,g4426);
dff DFF_192(CK,g193,g5474);
dff DFF_193(CK,g135,g5140);
dff DFF_194(CK,g382,g5696);
dff DFF_195(CK,g414,g4852);
dff DFF_196(CK,g434,g4848);
dff DFF_197(CK,g266,g4659);
dff DFF_198(CK,g49,g6583);
dff DFF_199(CK,g152,g6402);
dff DFF_200(CK,g692,g4144);
dff DFF_201(CK,g277,g6104);
dff DFF_202(CK,g127,g6941);
dff DFF_203(CK,g161,g6403);
dff DFF_204(CK,g512,g6500);
dff DFF_205(CK,g532,g6508);
dff DFF_206(CK,g64,g6586);
dff DFF_207(CK,g694,g4146);
dff DFF_208(CK,g691,g4143);
dff DFF_209(CK,g1,g6720);
dff DFF_210(CK,g59,g6585);
not NOT_0(I8854,g6696);
not NOT_1(g1289,I2272);
not NOT_2(I9125,g6855);
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not NOT_254(I2137,g1);
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not NOT_262(g1273,g839);
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not NOT_286(I8913,g6743);
not NOT_287(I2692,g1037);
not NOT_288(g6594,I8650);
not NOT_289(g946,g361);
not NOT_290(g1729,I2731);
not NOT_291(I5551,g4059);
not NOT_292(g4802,I6470);
not NOT_293(g3962,I5214);
not NOT_294(I2154,g14);
not NOT_295(I4189,g2159);
not NOT_296(I5499,g3847);
not NOT_297(g5151,I6819);
not NOT_298(g3158,I4398);
not NOT_299(g6806,I8978);
not NOT_300(I4706,g2877);
not NOT_301(g5875,I7637);
not NOT_302(g5530,I7270);
not NOT_303(I9167,g6878);
not NOT_304(I5926,g4153);
not NOT_305(g2921,g1950);
not NOT_306(g6065,g5784);
not NOT_307(I6315,g4446);
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not NOT_309(g6887,I9128);
not NOT_310(I4429,g2102);
not NOT_311(g6122,I7838);
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not NOT_313(g6322,I8056);
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not NOT_473(I4504,g2726);
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not NOT_494(g3839,I5040);
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not NOT_498(g6624,I8730);
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not NOT_502(g2849,g2577);
not NOT_503(I3572,g1295);
not NOT_504(g1787,I2835);
not NOT_505(I5442,g3731);
not NOT_506(I4678,g2670);
not NOT_507(I6057,g4379);
not NOT_508(I8524,g6496);
not NOT_509(I4331,g2555);
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not NOT_512(I6989,g5307);
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not NOT_516(I2125,g698);
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not NOT_521(g4712,I6318);
not NOT_522(g985,g638);
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not NOT_524(I6549,g4699);
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not NOT_526(I8818,g6690);
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not NOT_529(I3729,g2436);
not NOT_530(I3961,g1835);
not NOT_531(I5454,g3874);
not NOT_532(g2291,I3434);
not NOT_533(g5997,g5854);
not NOT_534(g4534,I6114);
not NOT_535(I3927,g2245);
not NOT_536(I5532,g3861);
not NOT_537(g1684,I2668);
not NOT_538(g6699,I8815);
not NOT_539(g1639,g815);
not NOT_540(g1338,I2367);
not NOT_541(g1963,I3074);
not NOT_542(I8186,g6179);
not NOT_543(I6321,g4559);
not NOT_544(I4226,g2525);
not NOT_545(g1109,I2137);
not NOT_546(g1791,I2845);
not NOT_547(I8975,g6791);
not NOT_548(I3946,g2256);
not NOT_549(g889,g310);
not NOT_550(I2306,g896);
not NOT_551(g3792,g3388);
not NOT_552(I6625,g4745);
not NOT_553(g2819,g2467);
not NOT_554(g4014,I5316);
not NOT_555(I8426,g6424);
not NOT_556(I5412,g4034);
not NOT_557(g4660,I6253);
not NOT_558(I6253,g4608);
not NOT_559(g2088,I3202);
not NOT_560(g2923,g1969);
not NOT_561(I4173,g2408);
not NOT_562(I8614,g6537);
not NOT_563(I3513,g1450);
not NOT_564(g2488,I3617);
not NOT_565(g1759,I2782);
not NOT_566(I2756,g1175);
not NOT_567(g2701,I3855);
not NOT_568(I7190,g5432);
not NOT_569(I8821,g6691);
not NOT_570(g6524,I8488);
not NOT_571(I6740,g4781);
not NOT_572(g4513,I6051);
not NOT_573(I8984,g6794);
not NOT_574(I7501,g5596);
not NOT_575(g1957,I3068);
not NOT_576(g2215,I3352);
not NOT_577(g6119,I7829);
not NOT_578(I2904,g1256);
not NOT_579(g6319,I8051);
not NOT_580(g1049,g266);
not NOT_581(g5901,g5753);
not NOT_582(g2886,g1966);
not NOT_583(I6552,g4702);
not NOT_584(I4059,g1878);
not NOT_585(g4036,I5337);
not NOT_586(g3094,I4337);
not NOT_587(I4459,g2134);
not NOT_588(I8544,g6453);
not NOT_589(g4679,I6269);
not NOT_590(g6352,I8110);
not NOT_591(g6818,I8991);
not NOT_592(g6577,g6488);
not NOT_593(I1847,g209);
not NOT_594(I3288,g1710);
not NOT_595(g3567,g3074);
not NOT_596(I3382,g1284);
not NOT_597(g1715,I2716);
not NOT_598(g4135,I5487);
not NOT_599(I7704,g5723);
not NOT_600(g848,g594);
not NOT_601(g5092,g4753);
not NOT_602(g1498,I2479);
not NOT_603(I2763,g1236);
not NOT_604(g2870,g2296);
not NOT_605(I3022,g1426);
not NOT_606(I4261,g1857);
not NOT_607(I2391,g774);
not NOT_608(g4382,I5857);
not NOT_609(g3776,g3466);
not NOT_610(g6893,I9146);
not NOT_611(g1833,I2913);
not NOT_612(I3422,g1641);
not NOT_613(g5574,g5407);
not NOT_614(I3749,g2484);
not NOT_615(g3593,g2997);
not NOT_616(g6211,g5992);
not NOT_617(g2650,I3794);
not NOT_618(g5714,I7475);
not NOT_619(g932,g337);
not NOT_620(I8061,g6113);
not NOT_621(g4805,g4473);
not NOT_622(g4022,I5328);
not NOT_623(g1584,g743);
not NOT_624(g4422,g4111);
not NOT_625(g6599,I8665);
not NOT_626(g1539,g878);
not NOT_627(I5109,g3710);
not NOT_628(g2408,I3546);
not NOT_629(I2159,g465);
not NOT_630(I6570,g4719);
not NOT_631(g2136,g1395);
not NOT_632(I4664,g2924);
not NOT_633(I8027,g6237);
not NOT_634(I4246,g2194);
not NOT_635(g2336,I3488);
not NOT_636(g5580,I7336);
not NOT_637(g716,I1832);
not NOT_638(I3560,g1673);
not NOT_639(g736,I1841);
not NOT_640(I6525,g4770);
not NOT_641(g2768,g2367);
not NOT_642(g6370,I8174);
not NOT_643(g2594,I3723);
not NOT_644(g4798,I6464);
not NOT_645(g6325,I8061);
not NOT_646(g6821,g6785);
not NOT_647(g4560,g4188);
not NOT_648(g2806,g2446);
not NOT_649(I3632,g1295);
not NOT_650(g3450,I4688);
not NOT_651(I3037,g1769);
not NOT_652(g6939,I9230);
not NOT_653(g1052,g668);
not NOT_654(I3653,g1305);
not NOT_655(I3102,g1426);
not NOT_656(I2115,g687);
not NOT_657(I2315,g1222);
not NOT_658(I2811,g1209);
not NOT_659(g6083,g5809);
not NOT_660(g2887,g1858);
not NOT_661(I2047,g682);
not NOT_662(g6544,I8544);
not NOT_663(I6607,g4745);
not NOT_664(g4632,g4281);
not NOT_665(g5889,g5742);
not NOT_666(g5476,I7164);
not NOT_667(g2934,g2004);
not NOT_668(g2230,I3355);
not NOT_669(g4437,I5948);
not NOT_670(g4102,I5388);
not NOT_671(g4302,g4068);
not NOT_672(I5865,g3743);
not NOT_673(g6106,I7814);
not NOT_674(g4579,g4206);
not NOT_675(g4869,g4662);
not NOT_676(g6306,I8030);
not NOT_677(I3752,g2044);
not NOT_678(g5375,I7029);
not NOT_679(I8107,g6136);
not NOT_680(g4719,I6337);
not NOT_681(g1730,g1114);
not NOT_682(g3289,g3034);
not NOT_683(g1504,I2485);
not NOT_684(g3777,g3388);
not NOT_685(I6587,g4803);
not NOT_686(I8159,g6167);
not NOT_687(I6111,g4404);
not NOT_688(g3835,I5030);
not NOT_689(I6311,g4444);
not NOT_690(I8223,g6325);
not NOT_691(g2096,I3212);
not NOT_692(I9143,g6886);
not NOT_693(g3882,I5119);
not NOT_694(g1070,g94);
not NOT_695(g2550,I3665);
not NOT_696(I6615,g4745);
not NOT_697(g3271,g3042);
not NOT_698(I4671,g2928);
not NOT_699(I2880,g1143);
not NOT_700(g2845,g2565);
not NOT_701(g1897,I2992);
not NOT_702(g6622,I8724);
not NOT_703(I2537,g971);
not NOT_704(I5896,g3879);
not NOT_705(g2195,I3334);
not NOT_706(g4265,I5716);
not NOT_707(g2891,g1884);
not NOT_708(g2913,g1925);
not NOT_709(g5139,I6795);
not NOT_710(I3364,g1648);
not NOT_711(g5384,g5220);
not NOT_712(I9134,g6864);
not NOT_713(I2272,g908);
not NOT_714(g6904,I9179);
not NOT_715(g4786,I6448);
not NOT_716(g3799,g3388);
not NOT_717(g6514,I8462);
not NOT_718(g4364,I5825);
not NOT_719(I8447,g6410);
not NOT_720(I3770,g2145);
not NOT_721(I5019,g3318);
not NOT_722(I2417,g774);
not NOT_723(g6403,I8223);
not NOT_724(g5809,I7608);
not NOT_725(I7683,g5702);
not NOT_726(g6841,I9044);
not NOT_727(g3541,g2643);
not NOT_728(I2982,g1426);
not NOT_729(g1678,I2658);
not NOT_730(g4770,I6414);
not NOT_731(g1006,I2047);
not NOT_732(I2234,g697);
not NOT_733(g1331,I2346);
not NOT_734(g4296,I5753);
not NOT_735(I2128,g18);
not NOT_736(g3238,I4513);
not NOT_737(I3553,g1305);
not NOT_738(I6020,g4176);
not NOT_739(g3332,g3079);
not NOT_740(g5477,I7167);
not NOT_741(I6420,g4618);
not NOT_742(g6695,I8803);
not NOT_743(I2330,g1122);
not NOT_744(g3209,I4452);
not NOT_745(I6507,g4644);
not NOT_746(g4532,I6108);
not NOT_747(g1682,g829);
not NOT_748(g6107,I7817);
not NOT_749(I9113,g6855);
not NOT_750(I1856,g204);
not NOT_751(g1305,I2293);
not NOT_752(g6536,I8524);
not NOT_753(g3802,g3388);
not NOT_754(I5728,g4022);
not NOT_755(g2481,I3608);
not NOT_756(I7475,g5627);
not NOT_757(g931,g54);
not NOT_758(g1748,I2763);
not NOT_759(g2692,I3840);
not NOT_760(I4217,g2163);
not NOT_761(g2097,I3215);
not NOT_762(I4066,g2582);
not NOT_763(g5551,I7295);
not NOT_764(g5742,g5686);
not NOT_765(g2726,I3886);
not NOT_766(g5099,I6737);
not NOT_767(g2497,I3626);
not NOT_768(I5385,g3962);
not NOT_769(g5304,I6956);
not NOT_770(g2154,I3271);
not NOT_771(g1755,I2776);
not NOT_772(g4189,I5597);
not NOT_773(I8978,g6792);
not NOT_774(g4706,I6308);
not NOT_775(g6416,I8258);
not NOT_776(I8243,g6286);
not NOT_777(I8417,g6420);
not NOT_778(g3901,g3575);
not NOT_779(I6630,g4745);
not NOT_780(I7646,g5774);
not NOT_781(I3675,g1491);
not NOT_782(g6522,I8482);
not NOT_783(g6115,g5879);
not NOT_784(g1045,g699);
not NOT_785(I3281,g1761);
not NOT_786(I7039,g5309);
not NOT_787(I7484,g5630);
not NOT_788(g1173,I2185);
not NOT_789(I4455,g2118);
not NOT_790(I8629,g6544);
not NOT_791(g5273,I6930);
not NOT_792(I4133,g2040);
not NOT_793(g1491,I2476);
not NOT_794(g760,I1853);
not NOT_795(g2783,I3979);
not NOT_796(g4281,I5736);
not NOT_797(g3600,I4791);
not NOT_798(g2112,I3240);
not NOT_799(g1283,g853);
not NOT_800(g2312,I3462);
not NOT_801(g1369,I2405);
not NOT_802(I6750,g4771);
not NOT_803(g6654,I8758);
not NOT_804(g3714,g3041);
not NOT_805(I7583,g5605);
not NOT_806(I3684,g1733);
not NOT_807(I5006,g3604);
not NOT_808(I8800,g6684);
not NOT_809(g1059,g702);
not NOT_810(g1578,I2552);
not NOT_811(g2001,I3112);
not NOT_812(I5406,g3976);
not NOT_813(g5572,g5399);
not NOT_814(I3109,g1504);
not NOT_815(I3791,g2044);
not NOT_816(g2293,g1567);
not NOT_817(g6880,I9107);
not NOT_818(g6595,I8653);
not NOT_819(g4138,I5496);
not NOT_820(g1535,g1088);
not NOT_821(g4639,g4289);
not NOT_822(g6537,I8527);
not NOT_823(g5543,g5331);
not NOT_824(I3808,g2125);
not NOT_825(I7276,g5375);
not NOT_826(I5487,g3881);
not NOT_827(I2355,g1177);
not NOT_828(g4109,I5409);
not NOT_829(g4309,g4074);
not NOT_830(g2828,g2488);
not NOT_831(g2830,g2494);
not NOT_832(g2727,g2324);
not NOT_833(g4808,g4473);
not NOT_834(I2964,g1257);
not NOT_835(g821,I1880);
not NOT_836(g6612,I8702);
not NOT_837(g5534,I7276);
not NOT_838(g5729,I7494);
not NOT_839(I6666,g4740);
not NOT_840(I9179,g6875);
not NOT_841(g1415,g1246);
not NOT_842(g4707,I6311);
not NOT_843(g6417,I8261);
not NOT_844(I7404,g5541);
not NOT_845(g3076,I4309);
not NOT_846(I8512,g6441);
not NOT_847(g3889,g3575);
not NOT_848(I6528,g4815);
not NOT_849(g1664,I2643);
not NOT_850(g1246,I2237);
not NOT_851(g6234,g6057);
not NOT_852(I3575,g1305);
not NOT_853(g5885,g5865);
not NOT_854(g6328,I8066);
not NOT_855(g1203,I2207);
not NOT_856(I5445,g4040);
not NOT_857(g5946,g5729);
not NOT_858(g6542,I8538);
not NOT_859(g6330,I8070);
not NOT_860(g1721,I2721);
not NOT_861(I5091,g3242);
not NOT_862(I8056,g6109);
not NOT_863(g2932,g1998);
not NOT_864(I8456,g6417);
not NOT_865(g5903,g5753);
not NOT_866(I3833,g2266);
not NOT_867(I2318,g1236);
not NOT_868(g4715,I6327);
not NOT_869(I2367,g1161);
not NOT_870(I1924,g663);
not NOT_871(g6800,I8966);
not NOT_872(I5169,g3593);
not NOT_873(I6410,g4473);
not NOT_874(g4098,I5376);
not NOT_875(g3500,g2647);
not NOT_876(g4498,I6012);
not NOT_877(I2057,g685);
not NOT_878(g1502,g709);
not NOT_879(I5059,g3259);
not NOT_880(I5920,g4228);
not NOT_881(I2457,g1253);
not NOT_882(I3584,g1678);
not NOT_883(I5868,g3864);
not NOT_884(I2989,g1519);
not NOT_885(I2193,g693);
not NOT_886(g5436,I7116);
not NOT_887(g3384,g2834);
not NOT_888(g1940,I3047);
not NOT_889(g2576,I3687);
not NOT_890(g2866,g1905);
not NOT_891(g5135,I6783);
not NOT_892(g2716,I3871);
not NOT_893(g3838,I5037);
not NOT_894(I7906,g5912);
not NOT_895(I3268,g1656);
not NOT_896(I3019,g1755);
not NOT_897(g3424,I4671);
not NOT_898(g5382,I7042);
not NOT_899(I5793,g3803);
not NOT_900(I3419,g1287);
not NOT_901(g6902,I9173);
not NOT_902(I6143,g4237);
not NOT_903(I6343,g4458);
not NOT_904(g846,g586);
not NOT_905(g1671,g985);
not NOT_906(g5805,I7604);
not NOT_907(I5415,g3723);
not NOT_908(g6512,I8456);
not NOT_909(I3452,g1450);
not NOT_910(g4162,I5562);
not NOT_911(g5022,I6666);
not NOT_912(g1030,I2057);
not NOT_913(I8279,g6307);
not NOT_914(g3231,I4492);
not NOT_915(g6490,g6371);
not NOT_916(I2321,g898);
not NOT_917(g6823,I9002);
not NOT_918(g3477,g2692);
not NOT_919(g6166,I7892);
not NOT_920(g6366,I8162);
not NOT_921(I6334,g4454);
not NOT_922(I8872,g6695);
not NOT_923(g2241,I3370);
not NOT_924(g1564,g1030);
not NOT_925(I7892,g5916);
not NOT_926(I3086,g1439);
not NOT_927(g6529,I8503);
not NOT_928(I8843,g6658);
not NOT_929(g6649,I8745);
not NOT_930(I6555,g4703);
not NOT_931(g1741,I2753);
not NOT_932(I6792,g5097);
not NOT_933(g3104,I4351);
not NOT_934(I3385,g1318);
not NOT_935(g2524,I3647);
not NOT_936(g2644,I3788);
not NOT_937(I8834,g6661);
not NOT_938(g6698,I8812);
not NOT_939(g1638,g754);
not NOT_940(g839,g567);
not NOT_941(I6621,g4745);
not NOT_942(g2119,g1391);
not NOT_943(I5502,g3853);
not NOT_944(g1108,I2134);
not NOT_945(I3025,g1439);
not NOT_946(I2552,g971);
not NOT_947(g5437,I7119);
not NOT_948(g4385,I5862);
not NOT_949(I3425,g1274);
not NOT_950(I9092,g6855);
not NOT_951(I4441,g2109);
not NOT_952(g2818,g2464);
not NOT_953(g2867,g1908);
not NOT_954(g1883,g1797);
not NOT_955(g5579,I7333);
not NOT_956(I7478,g5628);
not NOT_957(g4425,I5926);
not NOT_958(I7035,g5150);
not NOT_959(I5388,g3969);
not NOT_960(I7517,g5593);
not NOT_961(g2893,g1985);
not NOT_962(g5752,I7509);
not NOT_963(I8232,g6332);
not NOT_964(g5917,I7683);
not NOT_965(I6567,g4715);
not NOT_966(g6720,I8854);
not NOT_967(I3678,g1690);
not NOT_968(g2975,I4176);
not NOT_969(I5030,g3242);
not NOT_970(I3331,g1631);
not NOT_971(g1861,I2967);
not NOT_972(g6367,I8165);
not NOT_973(g1048,g492);
not NOT_974(I5430,g3727);
not NOT_975(g2599,I3729);
not NOT_976(g5042,I6672);
not NOT_977(g1711,I2712);
not NOT_978(I3635,g1305);
not NOT_979(g6652,I8752);
not NOT_980(g5442,g5270);
not NOT_981(g1055,g269);
not NOT_982(I2570,g1222);
not NOT_983(I2860,g1177);
not NOT_984(g6057,g5824);
not NOT_985(g4131,I5475);
not NOT_986(I4743,g2594);
not NOT_987(I3105,g1439);
not NOT_988(g2170,I3301);
not NOT_989(g2370,I3522);
not NOT_990(g4406,I5913);
not NOT_991(g6193,g5957);
not NOT_992(g1333,I2352);
not NOT_993(g2125,I3255);
not NOT_994(I8552,g6455);
not NOT_995(g1774,I2817);
not NOT_996(g4766,I6406);
not NOT_997(g4105,I5397);
not NOT_998(g1846,I2940);
not NOT_999(g5054,g4816);
not NOT_1000(g4801,g4487);
not NOT_1001(g6834,g6821);
not NOT_1002(g4487,I5991);
not NOT_1003(I7110,g5291);
not NOT_1004(g3534,I4752);
not NOT_1005(I5910,g3750);
not NOT_1006(g5770,g5645);
not NOT_1007(I3755,g2125);
not NOT_1008(g5296,I6946);
not NOT_1009(I8687,g6568);
not NOT_1010(I6933,g5124);
not NOT_1011(g2544,I3662);
not NOT_1012(g6598,I8662);
not NOT_1013(I5609,g3893);
not NOT_1014(I4474,g3052);
not NOT_1015(I2358,g1176);
not NOT_1016(g3014,I4217);
not NOT_1017(g6121,I7835);
not NOT_1018(I7002,g5308);
not NOT_1019(g766,I1856);
not NOT_1020(g3885,I5124);
not NOT_1021(g4226,g4050);
not NOT_1022(g2106,g1378);
not NOT_1023(g2306,g1743);
not NOT_1024(I3373,g1320);
not NOT_1025(g2790,g2413);
not NOT_1026(g6232,g6048);
not NOT_1027(I5217,g3673);
not NOT_1028(I8570,g6433);
not NOT_1029(I8860,g6699);
not NOT_1030(I4480,g3073);
not NOT_1031(g1994,I3105);
not NOT_1032(g1290,I2275);
not NOT_1033(I2275,g909);
not NOT_1034(g6938,I9227);
not NOT_1035(I5466,g3787);
not NOT_1036(g4173,I5577);
not NOT_1037(I8710,g6517);
not NOT_1038(g2461,I3593);
not NOT_1039(I7590,g5605);
not NOT_1040(I3602,g1491);
not NOT_1041(I3007,g1439);
not NOT_1042(g2756,g2353);
not NOT_1043(g2622,I3764);
not NOT_1044(I3059,g1519);
not NOT_1045(I3578,g1484);
not NOT_1046(I3868,g2125);
not NOT_1047(g5888,g5731);
not NOT_1048(g1256,g838);
not NOT_1049(g6519,I8473);
not NOT_1050(I6289,g4433);
not NOT_1051(I9024,g6803);
not NOT_1052(I5448,g3960);
not NOT_1053(I3767,g2125);
not NOT_1054(g5787,g5685);
not NOT_1055(g2904,g1991);
not NOT_1056(g6552,I8552);
not NOT_1057(g6606,I8684);
not NOT_1058(g2446,I3581);
not NOT_1059(I5333,g3491);
not NOT_1060(I2284,g922);
not NOT_1061(g1381,I2417);
not NOT_1062(g4718,I6334);
not NOT_1063(g4767,g4601);
not NOT_1064(I3261,g1783);
not NOT_1065(g1847,I2943);
not NOT_1066(I4688,g3207);
not NOT_1067(I5774,g3807);
not NOT_1068(I9077,g6845);
not NOT_1069(I8659,g6523);
not NOT_1070(g4535,g4173);
not NOT_1071(I4976,g3575);
not NOT_1072(g1685,I2671);
not NOT_1073(g2145,I3268);
not NOT_1074(I8506,g6483);
not NOT_1075(g2841,g2541);
not NOT_1076(g4582,g4210);
not NOT_1077(g3022,I4229);
not NOT_1078(g2391,I3534);
not NOT_1079(g6586,I8626);
not NOT_1080(g952,I2029);
not NOT_1081(g1263,g846);
not NOT_1082(g964,g357);
not NOT_1083(I2420,g791);
not NOT_1084(g2695,I3843);
not NOT_1085(g2637,I3779);
not NOT_1086(g1950,I3059);
not NOT_1087(g5138,I6792);
not NOT_1088(g4227,g4059);
not NOT_1089(I7295,g5439);
not NOT_1090(g5791,I7590);
not NOT_1091(g3798,g3388);
not NOT_1092(I9104,g6864);
not NOT_1093(g5309,g5063);
not NOT_1094(g2159,I3284);
not NOT_1095(g6570,I8594);
not NOT_1096(g4246,I5692);
not NOT_1097(I6132,g4219);
not NOT_1098(I8174,g6173);
not NOT_1099(g6525,I8491);
not NOT_1100(g6710,I8840);
not NOT_1101(I5418,g4036);
not NOT_1102(I6680,g4713);
not NOT_1103(g4721,I6343);
not NOT_1104(g1631,I2588);
not NOT_1105(g2416,I3556);
not NOT_1106(g3095,I4340);
not NOT_1107(g3037,I4252);
not NOT_1108(I3502,g1295);
not NOT_1109(g1257,g845);
not NOT_1110(g1101,I2125);
not NOT_1111(I2204,g694);
not NOT_1112(I2630,g1143);
not NOT_1113(I5493,g3834);
not NOT_1114(I8180,g6176);
not NOT_1115(I4220,g2164);
not NOT_1116(I7966,g6166);
not NOT_1117(I8591,g6448);
not NOT_1118(g2315,I3465);
not NOT_1119(g5957,g5866);
not NOT_1120(g6879,I9104);
not NOT_1121(g6607,I8687);
not NOT_1122(I6558,g4705);
not NOT_1123(g4502,I6020);
not NOT_1124(g5049,I6685);
not NOT_1125(I9044,g6836);
not NOT_1126(g927,I1958);
not NOT_1127(I1942,g664);
not NOT_1128(I4023,g2315);
not NOT_1129(g3719,g3053);
not NOT_1130(g6506,I8438);
not NOT_1131(g5575,g5411);
not NOT_1132(I8420,g6422);
not NOT_1133(I3388,g1324);
not NOT_1134(g2874,g1849);
not NOT_1135(g3752,I4935);
not NOT_1136(I5397,g3932);
not NOT_1137(I3028,g1504);
not NOT_1138(g4188,I5594);
not NOT_1139(g6587,I8629);
not NOT_1140(g4388,I5871);
not NOT_1141(I5421,g3724);
not NOT_1142(I3428,g1825);
not NOT_1143(I2973,g1687);
not NOT_1144(I7254,g5458);
not NOT_1145(I7814,g5922);
not NOT_1146(I3247,g1791);
not NOT_1147(g3042,I4261);
not NOT_1148(g6615,I8707);
not NOT_1149(I7150,g5355);
not NOT_1150(I4327,g2525);
not NOT_1151(g4428,I5933);
not NOT_1152(g3786,g3388);
not NOT_1153(g5584,I7346);
not NOT_1154(g5539,g5331);
not NOT_1155(g5896,g5753);
not NOT_1156(g1673,I2653);
not NOT_1157(g6374,I8186);
not NOT_1158(I3826,g2145);
not NOT_1159(g3364,g3114);
not NOT_1160(g3233,I4498);
not NOT_1161(I8515,g6492);
not NOT_1162(g4564,g4192);
not NOT_1163(g3054,I4279);
not NOT_1164(I5562,g4002);
not NOT_1165(I4303,g1897);
not NOT_1166(g2612,I3752);
not NOT_1167(I8300,g6299);
not NOT_1168(g6284,I8002);
not NOT_1169(g2243,I3376);
not NOT_1170(g3770,I4961);
not NOT_1171(I9014,g6820);
not NOT_1172(I3638,g1484);
not NOT_1173(g1772,I2811);
not NOT_1174(I5723,g3942);
not NOT_1175(g4741,I6371);
not NOT_1176(g6591,I8641);
not NOT_1177(g5052,I6692);
not NOT_1178(g6832,I9021);
not NOT_1179(g4910,I6612);
not NOT_1180(I2648,g980);
not NOT_1181(g2234,I3367);
not NOT_1182(g6853,I9082);
not NOT_1183(g1890,g1359);
not NOT_1184(I3883,g2574);
not NOT_1185(g6420,I8270);
not NOT_1186(I4240,g2165);
not NOT_1187(g2330,g1777);
not NOT_1188(g4108,I5406);
not NOT_1189(g4609,I6182);
not NOT_1190(g6507,I8441);
not NOT_1191(g4308,I5777);
not NOT_1192(g1011,I2050);
not NOT_1193(g1734,g952);
not NOT_1194(I3758,g2041);
not NOT_1195(g5086,g4732);
not NOT_1196(g897,g41);
not NOT_1197(I8040,g6142);
not NOT_1198(g951,g84);
not NOT_1199(I8969,g6797);
not NOT_1200(g2800,g2430);
not NOT_1201(g5730,I7497);
not NOT_1202(g2554,I3669);
not NOT_1203(g4758,I6382);
not NOT_1204(I2839,g1123);
not NOT_1205(I3861,g1834);
not NOT_1206(g6905,I9182);
not NOT_1207(g3029,I4240);
not NOT_1208(I3711,g1848);
not NOT_1209(I9182,g6879);
not NOT_1210(g3787,I4986);
not NOT_1211(g2213,I3346);
not NOT_1212(g5897,g5731);
not NOT_1213(g5025,g4814);
not NOT_1214(g6515,g6408);
not NOT_1215(g4861,I6587);
not NOT_1216(g5425,I7091);
not NOT_1217(I4347,g2555);
not NOT_1218(I2172,g691);
not NOT_1219(I2278,g917);
not NOT_1220(g4711,I6315);
not NOT_1221(g6100,I7796);
not NOT_1222(I4681,g2947);
not NOT_1223(g1480,g985);
not NOT_1224(g2902,g1899);
not NOT_1225(I8875,g6697);
not NOT_1226(I2143,g2);
not NOT_1227(I2343,g1177);
not NOT_1228(I6139,g4222);
not NOT_1229(g4133,I5481);
not NOT_1230(g3297,g3046);
not NOT_1231(g2512,I3638);
not NOT_1232(g2090,I3206);
not NOT_1233(g4846,I6546);
not NOT_1234(I2134,g705);
not NOT_1235(I6795,g5022);
not NOT_1236(I6737,g4662);
not NOT_1237(I2334,g1193);
not NOT_1238(I6809,g5051);
not NOT_1239(I5743,g4022);
not NOT_1240(g5331,I6995);
not NOT_1241(I5890,g3878);
not NOT_1242(I3509,g1461);
not NOT_1243(g3963,I5217);
not NOT_1244(g3791,g3388);
not NOT_1245(I8884,g6704);
not NOT_1246(I5505,g3860);
not NOT_1247(g1688,I2688);
not NOT_1248(I6672,g4752);
not NOT_1249(g4780,I6434);
not NOT_1250(g6040,g5824);
not NOT_1251(g1857,I2961);
not NOT_1252(I6231,g4350);
not NOT_1253(I3662,g1688);
not NOT_1254(g4509,I6039);
not NOT_1255(g5087,g4736);
not NOT_1256(I9095,g6855);
not NOT_1257(g5801,I7600);
not NOT_1258(g2155,I3274);
not NOT_1259(I9208,g6922);
not NOT_1260(g4662,g4640);
not NOT_1261(I3093,g1426);
not NOT_1262(g965,I2033);
not NOT_1263(I3493,g1461);
not NOT_1264(I3816,g2580);
not NOT_1265(g1326,g894);
not NOT_1266(I8235,g6312);
not NOT_1267(I6099,g4398);
not NOT_1268(I8282,g6309);
not NOT_1269(g3049,I4270);
not NOT_1270(g6528,I8500);
not NOT_1271(g1760,I2785);
not NOT_1272(g4493,I6001);
not NOT_1273(g6351,I8107);
not NOT_1274(I1850,g210);
not NOT_1275(g6875,I9092);
not NOT_1276(g834,g341);
not NOT_1277(I8988,g6787);
not NOT_1278(g6530,I8506);
not NOT_1279(g3575,I4777);
not NOT_1280(g5045,I6677);
not NOT_1281(I8693,g6570);
not NOT_1282(g6655,I8761);
not NOT_1283(g5445,g5274);
not NOT_1284(I5713,g4022);
not NOT_1285(g3604,I4799);
not NOT_1286(I8548,g6454);
not NOT_1287(g5491,I7193);
not NOT_1288(g3498,g2634);
not NOT_1289(g4381,I5854);
not NOT_1290(g4847,I6549);
not NOT_1291(g2118,I3247);
not NOT_1292(g2619,I3761);
not NOT_1293(I8555,g6456);
not NOT_1294(g2367,I3519);
not NOT_1295(g2872,g1922);
not NOT_1296(g1608,I2570);
not NOT_1297(g1220,I2221);
not NOT_1298(g4700,I6292);
not NOT_1299(g6410,I8240);
not NOT_1300(I9164,g6885);
not NOT_1301(g4397,I5890);
not NOT_1302(I9233,g6938);
not NOT_1303(I2776,g1192);
not NOT_1304(I7640,g5773);
not NOT_1305(g5407,I7073);
not NOT_1306(g6884,I9119);
not NOT_1307(I2593,g1177);
not NOT_1308(g5059,I6697);
not NOT_1309(g5920,I7692);
not NOT_1310(g6839,I9038);
not NOT_1311(g2457,I3587);
not NOT_1312(g5578,g5425);
not NOT_1313(I6444,g4503);
not NOT_1314(I6269,g4655);
not NOT_1315(g1423,I2442);
not NOT_1316(g923,g332);
not NOT_1317(I5857,g3740);
not NOT_1318(I7176,g5437);
not NOT_1319(g1588,g798);
not NOT_1320(I8113,g6147);
not NOT_1321(g5582,I7342);
not NOT_1322(g1161,I2182);
not NOT_1323(g6278,I7966);
not NOT_1324(g2686,I3830);
not NOT_1325(g6372,I8180);
not NOT_1326(g3162,I4402);
not NOT_1327(g5261,I6918);
not NOT_1328(g3019,I4226);
not NOT_1329(I4294,g2525);
not NOT_1330(I6543,g4718);
not NOT_1331(g6618,I8716);
not NOT_1332(g1665,g985);
not NOT_1333(I7829,g5926);
not NOT_1334(I3723,g2158);
not NOT_1335(g6143,I7865);
not NOT_1336(g4562,I6132);
not NOT_1337(g6235,g6062);
not NOT_1338(g2598,I3726);
not NOT_1339(g3052,I4273);
not NOT_1340(g1327,I2334);
not NOT_1341(I2521,g1063);
not NOT_1342(I3301,g1730);
not NOT_1343(g5415,I7081);
not NOT_1344(g3452,g2625);
not NOT_1345(g6282,I7996);
not NOT_1346(I2050,g683);
not NOT_1347(I5400,g3963);
not NOT_1348(g6566,I8582);
not NOT_1349(I8494,g6428);
not NOT_1350(I4501,g2705);
not NOT_1351(I6534,g4706);
not NOT_1352(I8518,g6494);
not NOT_1353(I3605,g1681);
not NOT_1354(g4723,I6349);
not NOT_1355(I8567,g6432);
not NOT_1356(g4101,I5385);
not NOT_1357(g6134,I7852);
not NOT_1358(g5664,g5521);
not NOT_1359(g2625,I3767);
not NOT_1360(I7270,g5352);
not NOT_1361(g2232,I3361);
not NOT_1362(g6548,I8548);
not NOT_1363(I6927,g5124);
not NOT_1364(g3086,I4327);
not NOT_1365(I2724,g1220);
not NOT_1366(g2253,I3388);
not NOT_1367(I2179,g293);
not NOT_1368(g3486,g2869);
not NOT_1369(g2813,g2457);
not NOT_1370(I2379,g1123);
not NOT_1371(g1696,I2700);
not NOT_1372(I7073,g5281);
not NOT_1373(I7796,g5917);
not NOT_1374(I6885,g4872);
not NOT_1375(I6414,g4497);
not NOT_1376(g3504,g2675);
not NOT_1377(I6946,g5124);
not NOT_1378(g1732,I2738);
not NOT_1379(g3881,I5116);
not NOT_1380(g2740,I3909);
not NOT_1381(I2658,g1001);
not NOT_1382(I3441,g1502);
not NOT_1383(I7069,g5281);
not NOT_1384(g3070,I4297);
not NOT_1385(I8264,g6296);
not NOT_1386(g6621,I8721);
not NOT_1387(I2835,g1209);
not NOT_1388(I7469,g5625);
not NOT_1389(g3897,g3251);
not NOT_1390(I5023,g3263);
not NOT_1391(g1472,g952);
not NOT_1392(g1043,g486);
not NOT_1393(I5977,g4319);
not NOT_1394(I8521,g6495);
not NOT_1395(I6036,g4370);
not NOT_1396(I8641,g6524);
not NOT_1397(I2611,g1209);
not NOT_1398(g893,g23);
not NOT_1399(g2687,I3833);
not NOT_1400(I8450,g6412);
not NOT_1401(I3669,g1739);
not NOT_1402(g1116,I2154);
not NOT_1403(g2586,I3711);
not NOT_1404(I3531,g1593);
not NOT_1405(I5451,g3967);
not NOT_1406(I6182,g4249);
not NOT_1407(g6518,I8470);
not NOT_1408(g6567,I8585);
not NOT_1409(I8724,g6533);
not NOT_1410(I6382,g4460);
not NOT_1411(g996,I2041);
not NOT_1412(g3331,g3076);
not NOT_1413(I3890,g2145);
not NOT_1414(g4772,I6420);
not NOT_1415(g5247,g4900);
not NOT_1416(g4531,I6105);
not NOT_1417(I5633,g3768);
not NOT_1418(I8878,g6710);
not NOT_1419(g1681,I2663);
not NOT_1420(I3505,g1305);
not NOT_1421(g6593,I8647);
not NOT_1422(g3766,I4955);
not NOT_1423(g1533,g878);
not NOT_1424(g5564,g5382);
not NOT_1425(I5103,g3440);
not NOT_1426(g2525,I3650);
not NOT_1427(g3801,g3388);
not NOT_1428(g3487,g2622);
not NOT_1429(g1914,I3013);
not NOT_1430(I5696,g3942);
not NOT_1431(g2691,g2317);
not NOT_1432(g4011,g3486);
not NOT_1433(I6798,g5042);
not NOT_1434(g4856,I6576);
not NOT_1435(g5741,g5602);
not NOT_1436(I2802,g1204);
not NOT_1437(I3074,g1426);
not NOT_1438(I3474,g1450);
not NOT_1439(I5753,g4022);
not NOT_1440(g5638,I7397);
not NOT_1441(g6160,g5926);
not NOT_1442(g3226,I4477);
not NOT_1443(I5508,g3867);
not NOT_1444(g6360,I8144);
not NOT_1445(g6933,I9220);
not NOT_1446(I5944,g4356);
not NOT_1447(g2962,g2008);
not NOT_1448(g6521,I8479);
not NOT_1449(I9098,g6864);
not NOT_1450(g2158,I3281);
not NOT_1451(I5472,g3846);
not NOT_1452(I8981,g6793);
not NOT_1453(g2506,I3632);
not NOT_1454(I3080,g1519);
not NOT_1455(I8674,g6521);
not NOT_1456(g1820,I2880);
not NOT_1457(I5043,g3247);
not NOT_1458(I6495,g4607);
not NOT_1459(g1936,g1756);
not NOT_1460(I6437,g4501);
not NOT_1461(g3173,I4410);
not NOT_1462(I6102,g4399);
not NOT_1463(I6302,g4440);
not NOT_1464(I8997,g6790);
not NOT_1465(g1117,g32);
not NOT_1466(I8541,g6452);
not NOT_1467(g1317,I2306);
not NOT_1468(g3491,g2608);
not NOT_1469(g2587,I3714);
not NOT_1470(I6579,g4798);
not NOT_1471(I5116,g3259);
not NOT_1472(I7852,g5993);
not NOT_1473(I5316,g3557);
not NOT_1474(g6724,I8866);
not NOT_1475(I3569,g1789);
not NOT_1476(g2111,g1384);
not NOT_1477(g2275,I3422);
not NOT_1478(g5466,I7146);
not NOT_1479(I8332,g6306);
not NOT_1480(g4713,I6321);
not NOT_1481(I7701,g5720);
not NOT_1482(g3369,I4646);
not NOT_1483(I8153,g6185);
not NOT_1484(g3007,g2197);
not NOT_1485(g2615,I3755);
not NOT_1486(g6878,I9101);
not NOT_1487(I2864,g1177);
not NOT_1488(g4569,I6143);
not NOT_1489(g5571,g5395);
not NOT_1490(g5861,g5636);
not NOT_1491(g3868,g3491);
not NOT_1492(g2174,I3313);
not NOT_1493(g3459,g2664);
not NOT_1494(g815,I1877);
not NOT_1495(g1775,g952);
not NOT_1496(g5448,g5278);
not NOT_1497(g1922,I3025);
not NOT_1498(g835,g345);
not NOT_1499(g5711,I7472);
not NOT_1500(g6835,I9028);
not NOT_1501(g1581,g910);
not NOT_1502(g6882,I9113);
not NOT_1503(I6042,g4374);
not NOT_1504(g1060,g107);
not NOT_1505(g2284,I3431);
not NOT_1506(I6786,g4824);
not NOT_1507(g1460,I2457);
not NOT_1508(g5774,I7517);
not NOT_1509(g4857,I6579);
not NOT_1510(g3793,g3491);
not NOT_1511(g6611,I8699);
not NOT_1512(g2591,I3720);
not NOT_1513(g3015,I4220);
not NOT_1514(g3227,I4480);
not NOT_1515(g1739,I2749);
not NOT_1516(I6054,g4194);
not NOT_1517(g5538,g5331);
not NOT_1518(I6296,g4436);
not NOT_1519(I4646,g2602);
not NOT_1520(I2623,g1161);
not NOT_1521(g4126,I5460);
not NOT_1522(g5509,I7251);
not NOT_1523(g4400,I5899);
not NOT_1524(g1937,I3044);
not NOT_1525(g6541,I8535);
not NOT_1526(I9185,g6877);
not NOT_1527(I2476,g971);
not NOT_1528(I7336,g5534);
not NOT_1529(I8600,g6451);
not NOT_1530(g2931,g1988);
not NOT_1531(g4760,I6386);
not NOT_1532(g1294,I2287);
not NOT_1533(I1877,g283);
not NOT_1534(g6332,I8074);
not NOT_1535(g5067,g4801);
not NOT_1536(g1190,I2199);
not NOT_1537(I2175,g25);
not NOT_1538(g6353,I8113);
not NOT_1539(g5994,g5873);
not NOT_1540(I3608,g1461);
not NOT_1541(g2905,g1994);
not NOT_1542(I6012,g4167);
not NOT_1543(g6744,I8910);
not NOT_1544(I3779,g2125);
not NOT_1545(g6802,I8972);
not NOT_1546(g2628,I3770);
not NOT_1547(g1156,I2175);
not NOT_1548(g2515,I3641);
not NOT_1549(g5493,I7197);
not NOT_1550(I7065,g5281);
not NOT_1551(g5256,g5077);
not NOT_1552(I6706,g4731);
not NOT_1553(g4220,I5644);
not NOT_1554(g3940,I5177);
not NOT_1555(I6371,g4569);
not NOT_1556(I4276,g2170);
not NOT_1557(g4423,I5920);
not NOT_1558(I3161,g1270);
not NOT_1559(I3361,g1331);
not NOT_1560(g5381,I7039);
not NOT_1561(g3388,I4667);
not NOT_1562(I9131,g6855);
not NOT_1563(I6956,g5124);
not NOT_1564(g6901,I9170);
not NOT_1565(I5460,g3771);
not NOT_1566(I5597,g3821);
not NOT_1567(I8623,g6542);
not NOT_1568(g3216,I4459);
not NOT_1569(I3665,g1824);
not NOT_1570(g5685,g5552);
not NOT_1571(g6511,I8453);
not NOT_1572(I8476,g6457);
not NOT_1573(I2424,g719);
not NOT_1574(g743,I1844);
not NOT_1575(g862,g319);
not NOT_1576(g2973,I4170);
not NOT_1577(g1954,I3065);
not NOT_1578(g3030,I4243);
not NOT_1579(g1250,g123);
not NOT_1580(I5739,g3942);
not NOT_1581(g1363,I2399);
not NOT_1582(I4986,g3638);
not NOT_1583(I3999,g1837);
not NOT_1584(g3247,g2973);
not NOT_1585(g4127,I5463);
not NOT_1586(I3346,g1327);
not NOT_1587(g5950,g5730);
not NOT_1588(g1053,g197);
not NOT_1589(g2040,g1738);
not NOT_1590(g6600,I8668);
not NOT_1591(g6574,g6484);
not NOT_1592(I2231,g465);
not NOT_1593(I1844,g208);
not NOT_1594(g2440,I3575);
not NOT_1595(g3564,g2618);
not NOT_1596(g6714,g6670);
not NOT_1597(I2643,g965);
not NOT_1598(g4146,I5520);
not NOT_1599(I5668,g3828);
not NOT_1600(g4633,g4284);
not NOT_1601(I8285,g6310);
not NOT_1602(I5840,g3732);
not NOT_1603(I8500,g6431);
not NOT_1604(g791,I1865);
not NOT_1605(g4103,I5391);
not NOT_1606(g6580,g6491);
not NOT_1607(I7859,g6032);
not NOT_1608(g5631,g5536);
not NOT_1609(g3638,g3108);
not NOT_1610(g5723,I7484);
not NOT_1611(I9173,g6876);
not NOT_1612(I3240,g1460);
not NOT_1613(g4732,I6362);
not NOT_1614(g3108,I4354);
not NOT_1615(g3308,g3060);
not NOT_1616(I6759,g4778);
not NOT_1617(g2875,g1940);
not NOT_1618(g4753,I6377);
not NOT_1619(g4508,I6036);
not NOT_1620(g917,I1942);
not NOT_1621(I8809,g6687);
not NOT_1622(I7342,g5579);
not NOT_1623(g6623,I8727);
not NOT_1624(g6076,g5797);
not NOT_1625(I7081,g5281);
not NOT_1626(g6889,I9134);
not NOT_1627(g5751,I7506);
not NOT_1628(I3316,g1344);
not NOT_1629(g3589,g3094);
not NOT_1630(I7481,g5629);
not NOT_1631(I3034,g1519);
not NOT_1632(g3466,I4706);
not NOT_1633(g2410,I3550);
not NOT_1634(I7692,g5711);
not NOT_1635(I3434,g1627);
not NOT_1636(I4516,g2777);
not NOT_1637(I7497,g5687);
not NOT_1638(g4116,I5430);
not NOT_1639(g6375,I8189);
not NOT_1640(g2884,g1957);
not NOT_1641(I2044,g681);
not NOT_1642(g3571,g3084);
not NOT_1643(g2839,g2535);
not NOT_1644(g3861,I5084);
not NOT_1645(g6722,I8860);
not NOT_1646(g4034,I5333);
not NOT_1647(I7960,g5925);
not NOT_1648(g852,g634);
not NOT_1649(I2269,g899);
not NOT_1650(g6651,I8749);
not NOT_1651(g3448,I4684);
not NOT_1652(g4565,g4195);
not NOT_1653(I3681,g1821);
not NOT_1654(I5053,g3710);
not NOT_1655(g3455,g2637);
not NOT_1656(g6285,I8005);
not NOT_1657(g4147,I5523);
not NOT_1658(g6500,I8420);
not NOT_1659(g2172,I3307);
not NOT_1660(I2712,g1203);
not NOT_1661(I9227,g6937);
not NOT_1662(I5568,g3897);
not NOT_1663(g4533,I6111);
not NOT_1664(g3846,I5053);
not NOT_1665(g2618,I3758);
not NOT_1666(I3596,g1305);
not NOT_1667(g2667,I3811);
not NOT_1668(g1683,g1017);
not NOT_1669(g2343,I3493);
not NOT_1670(g5168,g5099);
not NOT_1671(I3013,g1519);
not NOT_1672(g6339,I8093);
not NOT_1673(g3196,I4433);
not NOT_1674(g4914,g4816);
not NOT_1675(g3803,I5002);
not NOT_1676(g4210,I5630);
not NOT_1677(I7267,g5458);
not NOT_1678(g1894,I2989);
not NOT_1679(I5157,g3454);
not NOT_1680(g6838,I9035);
not NOT_1681(I9203,g6921);
not NOT_1682(I2961,g1731);
not NOT_1683(g6424,I8282);
not NOT_1684(g2134,I3258);
not NOT_1685(I6362,g4569);
not NOT_1686(g1735,I2745);
not NOT_1687(I8273,g6301);
not NOT_1688(g6809,I8981);
not NOT_1689(g5890,g5753);
not NOT_1690(g1782,I2828);
not NOT_1691(I4340,g1935);
not NOT_1692(I6452,g4629);
not NOT_1693(I5929,g4152);
not NOT_1694(g1661,g1076);
not NOT_1695(I8044,g6252);
not NOT_1696(g2555,I3672);
not NOT_1697(g6231,g6044);
not NOT_1698(g5011,I6649);
not NOT_1699(I8444,g6421);
not NOT_1700(g3067,I4294);
not NOT_1701(I2414,g784);
not NOT_1702(g729,I1838);
not NOT_1703(g5411,I7077);
not NOT_1704(g6523,I8485);
not NOT_1705(g861,g179);
not NOT_1706(I2946,g1587);
not NOT_1707(g2792,g2416);
not NOT_1708(g1627,I2584);
not NOT_1709(g4117,I5433);
not NOT_1710(g1292,I2281);
not NOT_1711(I5626,g3914);
not NOT_1712(g3093,I4334);
not NOT_1713(g898,g47);
not NOT_1714(g1998,I3109);
not NOT_1715(g1646,I2617);
not NOT_1716(g5992,g5869);
not NOT_1717(g4601,g4191);
not NOT_1718(g1084,g98);
not NOT_1719(g6104,I7808);
not NOT_1720(g854,g646);
not NOT_1721(g1039,g662);
not NOT_1722(g1484,I2473);
not NOT_1723(I3581,g1491);
not NOT_1724(g6499,I8417);
not NOT_1725(g1439,I2449);
not NOT_1726(I9028,g6806);
not NOT_1727(I8961,g6778);
not NOT_1728(g4775,I6425);
not NOT_1729(I6470,g4473);
not NOT_1730(g5573,g5403);
not NOT_1731(g3847,I5056);
not NOT_1732(g5480,I7176);
not NOT_1733(I6425,g4619);
not NOT_1734(I2831,g1209);
not NOT_1735(g2494,I3623);
not NOT_1736(I2182,g692);
not NOT_1737(g2518,I3644);
not NOT_1738(g1583,g1001);
not NOT_1739(g1702,g1107);
not NOT_1740(I2382,g719);
not NOT_1741(I8414,g6418);
not NOT_1742(g3263,g3015);
not NOT_1743(I8946,g6778);
not NOT_1744(g1919,I3022);
not NOT_1745(I2805,g1205);
not NOT_1746(I2916,g1643);
not NOT_1747(g2776,g2378);
not NOT_1748(I2749,g1209);
not NOT_1749(g4784,I6444);
not NOT_1750(g6044,g5824);
not NOT_1751(g1276,g847);
not NOT_1752(I4402,g2283);
not NOT_1753(I3294,g1720);
not NOT_1754(I3840,g2125);
not NOT_1755(I6406,g4473);
not NOT_1756(I5475,g3852);
not NOT_1757(g6572,I8600);
not NOT_1758(I4762,g2862);
not NOT_1759(I7349,g5532);
not NOT_1760(I6635,g4745);
not NOT_1761(g2264,I3405);
not NOT_1762(g6712,g6676);
not NOT_1763(g851,g606);
not NOT_1764(I6766,g4783);
not NOT_1765(I6087,g4392);
not NOT_1766(I6105,g4400);
not NOT_1767(g6543,I8541);
not NOT_1768(g4840,I6528);
not NOT_1769(I6305,g4441);
not NOT_1770(I6801,g5045);
not NOT_1771(g2360,g1793);
not NOT_1772(g2933,I4123);
not NOT_1773(g3723,I4903);
not NOT_1774(g1647,I2620);
not NOT_1775(g4190,I5600);
not NOT_1776(I5526,g3848);
not NOT_1777(I5998,g4157);
not NOT_1778(I8335,g6308);
not NOT_1779(I8831,g6665);
not NOT_1780(I9217,g6931);
not NOT_1781(g1546,g1101);
not NOT_1782(I2873,g1161);
not NOT_1783(I2037,g679);
not NOT_1784(g6534,I8518);
not NOT_1785(g6729,I8881);
not NOT_1786(g3605,I4802);
not NOT_1787(I5084,g3593);
not NOT_1788(I5603,g3893);
not NOT_1789(g2996,I4189);
not NOT_1790(I2653,g996);
not NOT_1791(I5484,g3875);
not NOT_1792(I3942,g1833);
not NOT_1793(g1503,g878);
not NOT_1794(I5439,g3730);
not NOT_1795(I8916,g6742);
not NOT_1796(g1925,I3028);
not NOT_1797(I8749,g6560);
not NOT_1798(g2179,I3328);
not NOT_1799(g6014,g5824);
not NOT_1800(g6885,I9122);
not NOT_1801(I6045,g4375);
not NOT_1802(g4704,I6302);
not NOT_1803(g6414,I8252);
not NOT_1804(I5702,g3845);
not NOT_1805(g1320,I2315);
not NOT_1806(g3041,I4258);
not NOT_1807(g5383,I7045);
not NOT_1808(g5924,I7704);
not NOT_1809(g5220,g4903);
not NOT_1810(I7119,g5303);
not NOT_1811(g6903,I9176);
not NOT_1812(g2777,I3965);
not NOT_1813(g3441,I4681);
not NOT_1814(g2835,g2506);
not NOT_1815(I3053,g1407);
not NOT_1816(I1958,g702);
not NOT_1817(g4250,I5702);
not NOT_1818(g6513,I8459);
not NOT_1819(g913,g658);
not NOT_1820(I6283,g4613);
not NOT_1821(I7258,g5458);
not NOT_1822(I5952,g4367);
not NOT_1823(g4810,I6488);
not NOT_1824(g2882,g1854);
not NOT_1825(I7352,g5533);
not NOT_1826(g3673,g3075);
not NOT_1827(I2442,g872);
not NOT_1828(g1789,I2839);
not NOT_1829(g6036,g5824);
not NOT_1830(I8632,g6548);
not NOT_1831(I2364,g1143);
not NOT_1832(g980,I2037);
not NOT_1833(I8653,g6531);
not NOT_1834(g1771,I2808);
not NOT_1835(g3772,g3466);
not NOT_1836(I6582,g4765);
not NOT_1837(g5051,I6689);
not NOT_1838(g2981,g2179);
not NOT_1839(I8579,g6438);
not NOT_1840(I8869,g6694);
not NOT_1841(I4489,g2975);
not NOT_1842(g3458,g2656);
not NOT_1843(g865,g188);
not NOT_1844(I2296,g893);
not NOT_1845(g3890,g3575);
not NOT_1846(g2997,I4192);
not NOT_1847(I6015,g4170);
not NOT_1848(g2541,I3659);
not NOT_1849(I8752,g6514);
not NOT_1850(I4471,g3040);
not NOT_1851(I7170,g5435);
not NOT_1852(g6422,I8276);
not NOT_1853(g2353,I3505);
not NOT_1854(g4929,I6621);
not NOT_1855(I4955,g3673);
not NOT_1856(I3626,g1684);
not NOT_1857(g2744,g2336);
not NOT_1858(g909,I1935);
not NOT_1859(g1738,g1108);
not NOT_1860(g2802,g2437);
not NOT_1861(g3074,I4303);
not NOT_1862(g949,g79);
not NOT_1863(g1991,I3102);
not NOT_1864(g6560,I8564);
not NOT_1865(I5320,g3559);
not NOT_1866(g4626,g4270);
not NOT_1867(g1340,I2373);
not NOT_1868(I2029,g677);
not NOT_1869(I9021,g6812);
not NOT_1870(g3480,g2986);
not NOT_1871(g1690,I2692);
not NOT_1872(g6653,I8755);
not NOT_1873(g6102,I7802);
not NOT_1874(I2281,g900);
not NOT_1875(I7061,g5281);
not NOT_1876(I7187,g5387);
not NOT_1877(g6579,g6490);
not NOT_1878(g5116,g4810);
not NOT_1879(I5987,g4224);
not NOT_1880(g5316,I6976);
not NOT_1881(g1656,I2635);
not NOT_1882(I6689,g4758);
not NOT_1883(g5434,I7110);
not NOT_1884(g2574,I3681);
not NOT_1885(g2864,g1887);
not NOT_1886(g4778,I6430);
not NOT_1887(g855,g650);
not NOT_1888(g5147,I6809);
not NOT_1889(I3782,g2145);
not NOT_1890(g4894,g4813);
not NOT_1891(I2745,g1249);
not NOT_1892(I8189,g6179);
not NOT_1893(I4229,g2284);
not NOT_1894(I6430,g4620);
not NOT_1895(g3976,I5252);
not NOT_1896(I2791,g1236);
not NOT_1897(I6247,g4609);
not NOT_1898(I7514,g5590);
not NOT_1899(I2309,g1236);
not NOT_1900(I9101,g6855);
not NOT_1901(g1110,I2140);
not NOT_1902(I8888,g6708);
not NOT_1903(g2580,I3691);
not NOT_1904(g5210,I6874);
not NOT_1905(g6786,I8946);
not NOT_1906(I6564,g4712);
not NOT_1907(I8171,g6170);
not NOT_1908(I2808,g1161);
not NOT_1909(I8429,g6425);
not NOT_1910(g5596,I7358);
not NOT_1911(g6164,g5926);
not NOT_1912(g6364,I8156);
not NOT_1913(g6233,g6052);
not NOT_1914(I5991,g4226);
not NOT_1915(I2707,g1190);
not NOT_1916(g4292,g4059);
not NOT_1917(I7695,g5714);
not NOT_1918(I7637,g5751);
not NOT_1919(g2968,g2179);
not NOT_1920(I5078,g3719);
not NOT_1921(g1824,I2890);
not NOT_1922(g4526,I6090);
not NOT_1923(I5478,g3859);
not NOT_1924(g1236,I2234);
not NOT_1925(I7107,g5277);
not NOT_1926(I5907,g3883);
not NOT_1927(g6725,I8869);
not NOT_1928(g1762,I2791);
not NOT_1929(g2889,g1975);
not NOT_1930(I6108,g4403);
not NOT_1931(g4603,I6170);
not NOT_1932(g6532,I8512);
not NOT_1933(I6308,g4443);
not NOT_1934(I5517,g3885);
not NOT_1935(I9041,g6835);
not NOT_1936(I2449,g971);
not NOT_1937(g4439,I5952);
not NOT_1938(g5117,I6763);
not NOT_1939(g6553,I8555);
not NOT_1940(g4850,I6558);
not NOT_1941(I8684,g6567);
not NOT_1942(I5876,g3870);
not NOT_1943(I8745,g6513);
not NOT_1944(g2175,I3316);
not NOT_1945(g2871,g1919);
not NOT_1946(I2604,g1222);
not NOT_1947(g3183,I4420);
not NOT_1948(g2722,I3883);
not NOT_1949(I4462,g2135);
not NOT_1950(I8309,g6304);
not NOT_1951(g1556,g878);
not NOT_1952(I6066,g4382);
not NOT_1953(g3779,g3466);
not NOT_1954(g1222,I2225);
not NOT_1955(g4702,I6296);
not NOT_1956(g6412,I8246);
not NOT_1957(g896,g22);
not NOT_1958(g3023,g2215);
not NOT_1959(I7251,g5458);
not NOT_1960(g1928,I3031);
not NOT_1961(I7811,g5921);
not NOT_1962(g6706,I8828);
not NOT_1963(g5922,I7698);
not NOT_1964(I8707,g6520);
not NOT_1965(g1064,g102);
not NOT_1966(I2584,g839);
not NOT_1967(I5214,g3567);
not NOT_1968(g6888,I9131);
not NOT_1969(g1899,I2998);
not NOT_1970(I6048,g4376);
not NOT_1971(g5581,I7339);
not NOT_1972(I6448,g4626);
not NOT_1973(g6371,I8177);
not NOT_1974(g4276,I5731);
not NOT_1975(I4249,g2525);
not NOT_1976(g5597,I7361);
not NOT_1977(I3004,g1426);
not NOT_1978(I1825,g361);
not NOT_1979(g4561,g4189);
not NOT_1980(g2838,g2515);
not NOT_1981(I3647,g1747);
not NOT_1982(g3451,g2615);
not NOT_1983(I2162,g197);
not NOT_1984(g1563,g1006);
not NOT_1985(I9011,g6819);
not NOT_1986(I4192,g1847);
not NOT_1987(g2809,I4019);
not NOT_1988(I3764,g2044);
not NOT_1989(g5784,I7583);
not NOT_1990(I3546,g1586);
not NOT_1991(I5002,g3612);
not NOT_1992(g4527,I6093);
not NOT_1993(g4404,I5907);
not NOT_1994(g1295,I2290);
not NOT_1995(g4647,g4296);
not NOT_1996(g3346,I4623);
not NOT_1997(I5236,g3545);
not NOT_1998(g2672,I3816);
not NOT_1999(g2231,I3358);
not NOT_2000(g4764,I6400);
not NOT_2001(g5995,g5824);
not NOT_2002(I9074,g6844);
not NOT_2003(g5479,I7173);
not NOT_2004(g2643,I3785);
not NOT_2005(I6780,g4825);
not NOT_2006(g6745,I8913);
not NOT_2007(g1394,g1206);
not NOT_2008(g4503,I6023);
not NOT_2009(I7612,g5605);
not NOT_2010(g1731,I2735);
not NOT_2011(I2728,g1232);
not NOT_2012(g1557,g1017);
not NOT_2013(g2634,I3776);
not NOT_2014(g1966,I3077);
not NOT_2015(g4224,g4046);
not NOT_2016(I5556,g4059);
not NOT_2017(I2185,g29);
not NOT_2018(g2104,g1372);
not NOT_2019(g2099,g1366);
not NOT_2020(g3240,I4519);
not NOT_2021(I2385,g784);
not NOT_2022(g6707,I8831);
not NOT_2023(g1471,I2464);
not NOT_2024(g4120,I5442);
not NOT_2025(I4031,g1846);
not NOT_2026(g4320,g4011);
not NOT_2027(I4252,g2555);
not NOT_2028(I3617,g1305);
not NOT_2029(I3906,g2234);
not NOT_2030(I6093,g4394);
not NOT_2031(I8162,g6189);
not NOT_2032(g3043,I4264);
not NOT_2033(g971,g658);
not NOT_2034(I5899,g3748);
not NOT_2035(I4176,g2268);
not NOT_2036(I6816,g5111);
not NOT_2037(I3516,g1295);
not NOT_2038(g2754,g2347);
not NOT_2039(g4617,g4242);
not NOT_2040(g3034,I4249);
not NOT_2041(g1254,g152);
not NOT_2042(g1814,I2873);
not NOT_2043(g6575,g6486);
not NOT_2044(g4516,I6060);
not NOT_2045(g6715,g6673);
not NOT_2046(g4771,I6417);
not NOT_2047(g2044,I3161);
not NOT_2048(I6685,g4716);
not NOT_2049(g5250,g4929);
not NOT_2050(g6604,I8678);
not NOT_2051(g1038,g127);
not NOT_2052(I6397,g4473);
not NOT_2053(g6498,I8414);
not NOT_2054(g1773,I2814);
not NOT_2055(I2131,g24);
not NOT_2056(g5432,I7104);
not NOT_2057(g4299,I5756);
not NOT_2058(g6833,I9024);
not NOT_2059(I8730,g6535);
not NOT_2060(g5453,g5296);
not NOT_2061(I4270,g2555);
not NOT_2062(g2862,I4066);
not NOT_2063(I2635,g1055);
not NOT_2064(g2712,g2320);
not NOT_2065(I8881,g6711);
not NOT_2066(I5394,g4016);
not NOT_2067(g1769,I2802);
not NOT_2068(g3914,I5153);
not NOT_2069(g6584,I8620);
not NOT_2070(I1859,g277);
not NOT_2071(g6539,I8531);
not NOT_2072(g6896,I9155);
not NOT_2073(g1836,I2922);
not NOT_2074(g5568,g5423);
not NOT_2075(I8070,g6116);
not NOT_2076(I5731,g3942);
not NOT_2077(I8470,g6461);
not NOT_2078(I8897,g6707);
not NOT_2079(g1918,I3019);
not NOT_2080(I3244,g1772);
not NOT_2081(I7490,g5583);
not NOT_2082(I4980,g3546);
not NOT_2083(g5912,g5853);
not NOT_2084(I4324,g1918);
not NOT_2085(I3140,g1317);
not NOT_2086(g2961,g1861);
not NOT_2087(I5071,g3263);
not NOT_2088(I3340,g1282);
not NOT_2089(I5705,g3942);
not NOT_2090(g6162,g5926);
not NOT_2091(I3478,g1450);
not NOT_2092(g6362,I8150);
not NOT_2093(g6419,I8267);
not NOT_2094(I6723,g4761);
not NOT_2095(g4140,I5502);
not NOT_2096(g6052,g5824);
not NOT_2097(g2927,g1979);
not NOT_2098(I5948,g4360);
not NOT_2099(I9220,g6930);
not NOT_2100(g2885,g1963);
not NOT_2101(I7355,g5535);
not NOT_2102(I8678,g6565);
not NOT_2103(I2445,g971);
not NOT_2104(g2660,I3804);
not NOT_2105(g2946,g2296);
not NOT_2106(g938,g59);
not NOT_2107(g4435,I5944);
not NOT_2108(I2373,g1143);
not NOT_2109(g4517,I6063);
not NOT_2110(I7698,g5717);
not NOT_2111(I3656,g1484);
not NOT_2112(g3601,I4794);
not NOT_2113(I2491,g821);
not NOT_2114(g2903,g1902);
not NOT_2115(I8635,g6552);
not NOT_2116(g6728,I8878);
not NOT_2117(g6486,g6363);
not NOT_2118(I2169,g269);
not NOT_2119(g942,g69);
not NOT_2120(g6730,I8884);
not NOT_2121(I9161,g6880);
not NOT_2122(g3775,g3388);
not NOT_2123(g6504,I8432);
not NOT_2124(g3922,I5157);
not NOT_2125(I7463,g5622);
not NOT_2126(I2578,g1209);
not NOT_2127(g6385,g6271);
not NOT_2128(g6881,I9110);
not NOT_2129(I5409,g3980);
not NOT_2130(g2036,g1764);
not NOT_2131(g706,I1825);
not NOT_2132(I6441,g4624);
not NOT_2133(g4915,g4669);
not NOT_2134(g2178,I3325);
not NOT_2135(g2436,I3569);
not NOT_2136(g2679,I3823);
not NOT_2137(g6070,g5824);
not NOT_2138(g2378,I3525);
not NOT_2139(g3060,I4285);
not NOT_2140(I3310,g1640);
not NOT_2141(g6897,I9158);
not NOT_2142(g1837,I2925);
not NOT_2143(I8755,g6561);
not NOT_2144(g3460,g2667);
not NOT_2145(I8226,g6328);
not NOT_2146(g6425,I8285);
not NOT_2147(g2135,I3261);
not NOT_2148(I4510,g2753);
not NOT_2149(I9146,g6890);
not NOT_2150(g4110,I5412);
not NOT_2151(I7167,g5434);
not NOT_2152(I7318,g5452);
not NOT_2153(I4291,g2241);
not NOT_2154(g5894,g5731);
not NOT_2155(g2805,g2443);
not NOT_2156(g910,I1938);
not NOT_2157(g1788,g985);
not NOT_2158(g2422,I3560);
not NOT_2159(I6772,g4788);
not NOT_2160(I7193,g5466);
not NOT_2161(I8491,g6480);
not NOT_2162(g3079,I4312);
not NOT_2163(I6531,g4704);
not NOT_2164(g4402,g4017);
not NOT_2165(g784,I1862);
not NOT_2166(g1249,I2240);
not NOT_2167(g4824,g4615);
not NOT_2168(g837,g353);
not NOT_2169(g5661,g5518);
not NOT_2170(g3840,I5043);
not NOT_2171(g719,I1835);
not NOT_2172(I3590,g1781);
not NOT_2173(g6406,I8232);
not NOT_2174(g5475,I7161);
not NOT_2175(I7686,g5705);
not NOT_2176(g1842,g1612);
not NOT_2177(I2721,g1219);
not NOT_2178(g1192,g44);
not NOT_2179(I8459,g6427);
not NOT_2180(g6105,I7811);
not NOT_2181(g6087,g5813);
not NOT_2182(g6801,I8969);
not NOT_2183(g6305,I8027);
not NOT_2184(g5292,I6942);
not NOT_2185(I8767,g6619);
not NOT_2186(g6487,g6365);
not NOT_2187(I3556,g1484);
not NOT_2188(g3501,g2650);
not NOT_2189(I3222,g1790);
not NOT_2190(I8535,g6447);
not NOT_2191(g4657,I6244);
not NOT_2192(I8582,g6439);
not NOT_2193(g1854,I2958);
not NOT_2194(I9116,g6864);
not NOT_2195(I8261,g6298);
not NOT_2196(g5084,g4727);
not NOT_2197(g4222,I5654);
not NOT_2198(g2437,I3572);
not NOT_2199(g2653,I3797);
not NOT_2200(I6992,g5151);
not NOT_2201(I1932,g667);
not NOT_2202(g2102,I3222);
not NOT_2203(g5439,g5261);
not NOT_2204(I3785,g2346);
not NOT_2205(I2940,g1653);
not NOT_2206(I5837,g3850);
not NOT_2207(g2869,g2433);
not NOT_2208(I2388,g878);
not NOT_2209(I6573,g4721);
not NOT_2210(I3563,g1461);
not NOT_2211(g5702,I7463);
not NOT_2212(I8246,g6290);
not NOT_2213(g1219,I2218);
not NOT_2214(g1640,I2601);
not NOT_2215(g2752,g2343);
not NOT_2216(g6373,I8183);
not NOT_2217(g3363,g3110);
not NOT_2218(g6491,g6373);
not NOT_2219(g5919,I7689);
not NOT_2220(I2671,g1017);
not NOT_2221(g1812,I2867);
not NOT_2222(I8721,g6534);
not NOT_2223(I2428,g774);
not NOT_2224(g4563,g4190);
not NOT_2225(g3053,I4276);
not NOT_2226(g1176,I2190);
not NOT_2227(g2265,I3408);
not NOT_2228(g3453,g2628);
not NOT_2229(g6283,I7999);
not NOT_2230(g6369,I8171);
not NOT_2231(g2042,I3155);
not NOT_2232(g6602,I8674);
not NOT_2233(I5249,g3589);
not NOT_2234(g6407,I8235);
not NOT_2235(g6578,g6489);
not NOT_2236(g4844,I6540);
not NOT_2237(g2164,I3291);
not NOT_2238(g1286,g854);
not NOT_2239(g2364,I3516);
not NOT_2240(g2233,I3364);
not NOT_2241(g4194,I5612);
not NOT_2242(g1911,I3010);
not NOT_2243(g4394,I5885);
not NOT_2244(g6535,I8521);
not NOT_2245(I6976,g5136);
not NOT_2246(g3912,g3505);
not NOT_2247(I2741,g1222);
not NOT_2248(g5527,I7267);
not NOT_2249(g6582,I8614);
not NOT_2250(I8940,g6783);
not NOT_2251(g4731,I6359);
not NOT_2252(I2910,g1645);
not NOT_2253(I3071,g1504);
not NOT_2254(g5647,g5509);
not NOT_2255(I3705,g2316);
not NOT_2256(I3471,g1450);
not NOT_2257(g2296,I3441);
not NOT_2258(g1733,I2741);
not NOT_2259(I2638,g1123);
not NOT_2260(g1270,g844);
not NOT_2261(g5546,g5388);
not NOT_2262(I5854,g3857);
not NOT_2263(I4465,g2945);
not NOT_2264(g6015,g5857);
not NOT_2265(g4705,I6305);
not NOT_2266(g6415,I8255);
not NOT_2267(I6126,g4240);
not NOT_2268(I6400,g4473);
not NOT_2269(g4242,I5686);
not NOT_2270(I2883,g1143);
not NOT_2271(I8671,g6519);
not NOT_2272(g5925,I7707);
not NOT_2273(I8030,g6239);
not NOT_2274(I4433,g2103);
not NOT_2275(g1324,I2327);
not NOT_2276(I5708,g3942);
not NOT_2277(I5520,g3835);
not NOT_2278(g6721,I8857);
not NOT_2279(I5640,g3770);
not NOT_2280(g5120,I6772);
not NOT_2281(I8564,g6429);
not NOT_2282(g2706,I3861);
not NOT_2283(I5252,g3546);
not NOT_2284(I3773,g2524);
not NOT_2285(g1177,I2193);
not NOT_2286(g4150,I5532);
not NOT_2287(I2165,g690);
not NOT_2288(g1206,I2212);
not NOT_2289(g4350,g4010);
not NOT_2290(g2888,g1972);
not NOT_2291(I7358,g5565);
not NOT_2292(I4195,g2173);
not NOT_2293(g2029,I3134);
not NOT_2294(I7506,g5584);
not NOT_2295(I5376,g4014);
not NOT_2296(g2171,I3304);
not NOT_2297(I4337,g1934);
not NOT_2298(I8910,g6730);
not NOT_2299(g2787,g2405);
not NOT_2300(g6502,I8426);
not NOT_2301(g2956,g1861);
not NOT_2302(I6023,g4151);
not NOT_2303(I8638,g6553);
not NOT_2304(g1287,g855);
not NOT_2305(g2675,I3819);
not NOT_2306(I3836,g1832);
not NOT_2307(I3212,g1806);
not NOT_2308(I7587,g5605);
not NOT_2309(g6940,I9233);
not NOT_2310(g4769,g4606);
not NOT_2311(g1849,I2949);
not NOT_2312(g3778,g3388);
not NOT_2313(g6188,g5950);
not NOT_2314(I2196,g3);
not NOT_2315(g5299,I6949);
not NOT_2316(g1781,I2825);
not NOT_2317(I6051,g4185);
not NOT_2318(g1898,I2995);
not NOT_2319(g3782,g3388);
not NOT_2320(I8217,g6319);
not NOT_2321(I8758,g6562);
not NOT_2322(I8066,g6114);
not NOT_2323(g5892,g5742);
not NOT_2324(I6327,g4451);
not NOT_2325(g6428,I8290);
not NOT_2326(g3075,I4306);
not NOT_2327(g4229,g4059);
not NOT_2328(g2109,I3235);
not NOT_2329(I7284,g5383);
not NOT_2330(I4255,g2179);
not NOT_2331(I6346,g4563);
not NOT_2332(I8165,g6189);
not NOT_2333(g4822,g4614);
not NOT_2334(g1291,I2278);
not NOT_2335(I5124,g3719);
not NOT_2336(I2067,g686);
not NOT_2337(g6564,I8576);
not NOT_2338(I5324,g3466);
not NOT_2339(I7832,g5943);
not NOT_2340(g6826,I9011);
not NOT_2341(I5469,g3838);
not NOT_2342(I2290,g971);
not NOT_2343(g1344,I2379);
not NOT_2344(I4354,g1953);
not NOT_2345(g5140,I6798);
not NOT_2346(I5177,g3267);
not NOT_2347(g3084,I4321);
not NOT_2348(g5478,I7170);
not NOT_2349(g1819,I2877);
not NOT_2350(I6753,g4772);
not NOT_2351(g2957,g1861);
not NOT_2352(I8803,g6685);
not NOT_2353(g1088,I2119);
not NOT_2354(g1852,I2952);
not NOT_2355(I6072,g4385);
not NOT_2356(g6609,I8693);
not NOT_2357(g5435,I7113);
not NOT_2358(g6308,I8034);
not NOT_2359(I3062,g1776);
not NOT_2360(g5082,g4723);
not NOT_2361(g2449,I3584);
not NOT_2362(I3620,g1484);
not NOT_2363(I3462,g1450);
not NOT_2364(I8538,g6450);
not NOT_2365(g2575,I3684);
not NOT_2366(g2865,g2296);
not NOT_2367(g6883,I9116);
not NOT_2368(g5876,I7640);
not NOT_2369(g4837,g4473);
not NOT_2370(I8509,g6437);
not NOT_2371(I2700,g1173);
not NOT_2372(g2604,I3736);
not NOT_2373(I4267,g2525);
not NOT_2374(g2098,g1363);
not NOT_2375(I4312,g2555);
not NOT_2376(g4620,g4251);
not NOT_2377(g4462,I5977);
not NOT_2378(g6589,I8635);
not NOT_2379(g945,g536);
not NOT_2380(I8662,g6525);
not NOT_2381(I3788,g2554);
not NOT_2382(g6466,I8332);
not NOT_2383(g5915,I7679);
not NOT_2384(g3952,I5182);
not NOT_2385(I6434,g4622);
not NOT_2386(I8467,g6457);
not NOT_2387(I8994,g6789);
not NOT_2388(I8290,g6291);
not NOT_2389(g1114,I2150);
not NOT_2390(g6165,g5926);
not NOT_2391(g6571,I8597);
not NOT_2392(g6365,I8159);
not NOT_2393(g2584,I3705);
not NOT_2394(g4788,I6452);
not NOT_2395(g6048,g5824);
not NOT_2396(I1841,g207);
not NOT_2397(g6711,I8843);
not NOT_2398(I8093,g6122);
not NOT_2399(g5110,I6740);
not NOT_2400(g4249,I5699);
not NOT_2401(g5310,g5067);
not NOT_2402(I3298,g1725);
not NOT_2403(g1825,I2893);
not NOT_2404(g6827,I9014);
not NOT_2405(g1650,I2627);
not NOT_2406(I3485,g1450);
not NOT_2407(g3527,I4743);
not NOT_2408(g809,I1874);
not NOT_2409(I6697,g4722);
not NOT_2410(g4842,I6534);
not NOT_2411(g849,g598);
not NOT_2412(g2268,I3419);
not NOT_2413(g4192,I5606);
not NOT_2414(g4392,I5879);
not NOT_2415(g3546,g3095);
not NOT_2416(g4485,I5987);
not NOT_2417(I2817,g1222);
not NOT_2418(g5824,g5631);
not NOT_2419(g1336,I2361);
not NOT_2420(g6803,I8975);
not NOT_2421(g3970,I5236);
not NOT_2422(g1594,g1143);
not NOT_2423(g4854,I6570);
not NOT_2424(g6538,g6469);
not NOT_2425(g1972,I3083);
not NOT_2426(I5923,g4299);
not NOT_2427(g6509,I8447);
not NOT_2428(g1806,I2857);
not NOT_2429(g5877,I7643);
not NOT_2430(g5590,I7352);
not NOT_2431(g1943,I3050);
not NOT_2432(I3708,g1946);
not NOT_2433(g3224,I4471);
not NOT_2434(g2086,I3198);
not NOT_2435(g2728,I3890);
not NOT_2436(I3031,g1504);
not NOT_2437(I4468,g2583);
not NOT_2438(g3320,g3067);
not NOT_2439(g6067,g5788);
not NOT_2440(g1887,I2982);
not NOT_2441(I3431,g1275);
not NOT_2442(g1122,I2162);
not NOT_2443(g6418,I8264);
not NOT_2444(g6467,I8335);
not NOT_2445(g1322,I2321);
not NOT_2446(g4520,I6072);
not NOT_2447(g1934,I3037);
not NOT_2448(I2041,g680);
not NOT_2449(I3376,g1328);
not NOT_2450(g4431,I5938);
not NOT_2451(g4252,I5708);
not NOT_2452(I1874,g282);
not NOT_2453(I3405,g1321);
not NOT_2454(g3906,g3575);
not NOT_2455(g2470,I3602);
not NOT_2456(g3789,g3388);
not NOT_2457(g5064,I6706);
not NOT_2458(g2025,g1276);
not NOT_2459(g6493,g6375);
not NOT_2460(g5899,g5753);
not NOT_2461(I6775,g4790);
not NOT_2462(g4376,I5843);
not NOT_2463(g4405,I5910);
not NOT_2464(g3771,I4964);
not NOT_2465(I5825,g3914);
not NOT_2466(g872,g143);
not NOT_2467(g1550,g996);
not NOT_2468(I6060,g4380);
not NOT_2469(g4286,I5743);
not NOT_2470(g4765,I6403);
not NOT_2471(I1880,g276);
not NOT_2472(I4198,g2276);
not NOT_2473(g3299,g3049);
not NOT_2474(g5563,g5381);
not NOT_2475(I4398,g2086);
not NOT_2476(g4911,I6615);
not NOT_2477(I3733,g2031);
not NOT_2478(g6700,I8818);
not NOT_2479(g1395,I2428);
not NOT_2480(g1891,I2986);
not NOT_2481(g1337,I2364);
not NOT_2482(g5237,g5083);
not NOT_2483(g3892,g3575);
not NOT_2484(g2678,g2312);
not NOT_2485(I3225,g1813);
not NOT_2486(g6421,I8273);
not NOT_2487(I2890,g1123);
not NOT_2488(I8585,g6442);
not NOT_2489(I5594,g3821);
not NOT_2490(g4270,I5723);
not NOT_2491(I7372,g5493);
not NOT_2492(g1807,I2860);
not NOT_2493(g4225,g4059);
not NOT_2494(g2682,I3826);
not NOT_2495(g2766,g2361);
not NOT_2496(I6995,g5220);
not NOT_2497(I1935,g666);
not NOT_2498(g2087,g1352);
not NOT_2499(g2105,g1375);
not NOT_2500(I6937,g5124);
not NOT_2501(I7143,g5323);
not NOT_2502(I8441,g6419);
not NOT_2503(g2801,I4003);
not NOT_2504(I2411,g736);
not NOT_2505(g5089,I6723);
not NOT_2506(g5489,I7187);
not NOT_2507(I5065,g3714);
not NOT_2508(g4124,I5454);
not NOT_2509(g714,g131);
not NOT_2510(I3540,g1670);
not NOT_2511(g4980,g4678);
not NOT_2512(g2748,I3923);
not NOT_2513(g6562,I8570);
not NOT_2514(I3206,g1823);
not NOT_2515(g5705,I7466);
not NOT_2516(I2992,g1741);
not NOT_2517(g3478,g2695);
not NOT_2518(g1142,I2169);
not NOT_2519(g2755,g2350);
not NOT_2520(I4258,g2169);
not NOT_2521(g5242,g5085);
not NOT_2522(I8168,g6170);
not NOT_2523(g6723,I8863);
not NOT_2524(g1255,g161);
not NOT_2525(I5033,g3527);
not NOT_2526(g6101,I7799);
not NOT_2527(g6817,I8988);
not NOT_2528(I5433,g3728);
not NOT_2529(g4206,I5626);
not NOT_2530(g3082,I4315);
not NOT_2531(g3482,g2713);
not NOT_2532(I8531,g6444);
not NOT_2533(g1692,I2696);
not NOT_2534(g6605,I8681);
not NOT_2535(g1726,I2728);
not NOT_2536(g3876,I5109);
not NOT_2537(g2173,I3310);
not NOT_2538(I6942,g5124);
not NOT_2539(g2091,g1355);
not NOT_2540(I5496,g3839);
not NOT_2541(g1960,I3071);
not NOT_2542(g2491,I3620);
not NOT_2543(g5150,I6816);
not NOT_2544(g4849,I6555);
not NOT_2545(g2169,I3298);
not NOT_2546(g2283,I3428);
not NOT_2547(I7113,g5295);
not NOT_2548(I8411,g6415);
not NOT_2549(I5337,g3564);
not NOT_2550(I5913,g3751);
not NOT_2551(g2602,g2061);
not NOT_2552(g6585,I8623);
not NOT_2553(g2007,g1411);
not NOT_2554(g5773,I7514);
not NOT_2555(g4399,I5896);
not NOT_2556(I3797,g2125);
not NOT_2557(I6250,g4514);
not NOT_2558(g2059,g1402);
not NOT_2559(g2920,g1947);
not NOT_2560(I4170,g2157);
not NOT_2561(g4781,I6437);
not NOT_2562(g6441,I8309);
not NOT_2563(I8074,g6118);
not NOT_2564(g2767,g2364);
not NOT_2565(g4900,I6607);
not NOT_2566(g1783,I2831);
not NOT_2567(g3110,I4358);
not NOT_2568(I4821,g2877);
not NOT_2569(I2688,g1030);
not NOT_2570(I2857,g1161);
not NOT_2571(g2535,I3653);
not NOT_2572(I3291,g1714);
not NOT_2573(g1979,I3090);
not NOT_2574(g1112,g336);
not NOT_2575(g1267,g843);
not NOT_2576(I7494,g5691);
not NOT_2577(g4510,I6042);
not NOT_2578(I3144,g1319);
not NOT_2579(g5918,I7686);
not NOT_2580(g1001,I2044);
not NOT_2581(g3002,g2215);
not NOT_2582(I8573,g6435);
not NOT_2583(I8863,g6700);
not NOT_2584(I4483,g3082);
not NOT_2585(g1293,I2284);
not NOT_2586(g6368,I8168);
not NOT_2587(g4144,I5514);
not NOT_2588(I8713,g6522);
not NOT_2589(I7593,g5605);
not NOT_2590(I3819,g2044);
not NOT_2591(g3236,I4507);
not NOT_2592(g1329,I2340);
not NOT_2593(I3694,g1811);
not NOT_2594(g1761,I2788);
not NOT_2595(g857,g170);
not NOT_2596(g5993,g5872);
not NOT_2597(g6531,I8509);
not NOT_2598(I5081,g3589);
not NOT_2599(I3923,g2581);
not NOT_2600(I4306,g1898);
not NOT_2601(I2760,g1193);
not NOT_2602(g2664,I3808);
not NOT_2603(I5481,g3866);
not NOT_2604(I3488,g1295);
not NOT_2605(g6743,I8907);
not NOT_2606(g6890,I9137);
not NOT_2607(g1830,I2904);
not NOT_2608(I5692,g3942);
not NOT_2609(I7264,g5458);
not NOT_2610(g4852,I6564);
not NOT_2611(g6505,I8435);
not NOT_2612(I3215,g1820);
not NOT_2613(g1221,g46);
not NOT_2614(g6411,I8243);
not NOT_2615(g6734,I8894);
not NOT_2616(g3222,I4465);
not NOT_2617(I3886,g2215);
not NOT_2618(I8857,g6698);
not NOT_2619(g1703,I2707);
not NOT_2620(I2608,g1143);
not NOT_2621(g5921,I7695);
not NOT_2622(g4215,I5637);
not NOT_2623(I2779,g1038);
not NOT_2624(I7996,g6137);
not NOT_2625(g6074,g5794);
not NOT_2626(g3064,I4291);
not NOT_2627(g3785,g3466);
not NOT_2628(g1624,I2581);
not NOT_2629(g1953,I3062);
not NOT_2630(I4003,g2284);
not NOT_2631(g5895,g5742);
not NOT_2632(g4114,I5424);
not NOT_2633(g4314,g4080);
not NOT_2634(I2588,g1193);
not NOT_2635(I3650,g1650);
not NOT_2636(g6080,g5805);
not NOT_2637(I2361,g1075);
not NOT_2638(g6573,I8603);
not NOT_2639(I4391,g2275);
not NOT_2640(g6713,g6679);
not NOT_2641(I3408,g1644);
not NOT_2642(g3237,I4510);
not NOT_2643(I7835,g5926);
not NOT_2644(I2327,g1222);
not NOT_2645(g6569,I8591);
not NOT_2646(g2030,I3137);
not NOT_2647(g5788,I7587);
not NOT_2648(g2430,I3563);
not NOT_2649(I2346,g1193);
not NOT_2650(g4136,I5490);
not NOT_2651(I8183,g6176);
not NOT_2652(I4223,g2176);
not NOT_2653(I8220,g6322);
not NOT_2654(g4768,I6410);
not NOT_2655(g1848,I2946);
not NOT_2656(I9140,g6888);
not NOT_2657(g2826,g2481);
not NOT_2658(g1699,I2703);
not NOT_2659(g1747,I2760);
not NOT_2660(g838,g564);
not NOT_2661(I6075,g4386);
not NOT_2662(I2696,g1156);
not NOT_2663(I4757,g2861);
not NOT_2664(I7799,g5918);
not NOT_2665(I3065,g1426);
not NOT_2666(g3557,g2598);
not NOT_2667(I5746,g4022);
not NOT_2668(g4806,g4473);
not NOT_2669(g5392,I7058);
not NOT_2670(I8423,g6423);
not NOT_2671(I9035,g6812);
not NOT_2672(I6949,g5050);
not NOT_2673(g4943,I6635);
not NOT_2674(I3465,g1724);
not NOT_2675(I3322,g1333);
not NOT_2676(I9082,g6849);
not NOT_2677(g3705,g3014);
not NOT_2678(I8588,g6443);
not NOT_2679(I4522,g2801);
not NOT_2680(I2753,g1174);
not NOT_2681(g842,g571);
not NOT_2682(I6292,g4434);
not NOT_2683(I4315,g2245);
not NOT_2684(g3242,g3083);
not NOT_2685(g4122,I5448);
not NOT_2686(g4228,I5668);
not NOT_2687(g4322,I5793);
not NOT_2688(I2240,g19);
not NOT_2689(I1938,g332);
not NOT_2690(g2108,I3232);
not NOT_2691(g2609,I3749);
not NOT_2692(I6646,g4687);
not NOT_2693(g2308,I3452);
not NOT_2694(I8665,g6527);
not NOT_2695(I8051,g6108);
not NOT_2696(I7153,g5358);
not NOT_2697(g2883,g1954);
not NOT_2698(I6084,g4391);
not NOT_2699(I6039,g4182);
not NOT_2700(I5068,g3571);
not NOT_2701(I3096,g1439);
not NOT_2702(g1644,I2611);
not NOT_2703(I3496,g1326);
not NOT_2704(g715,g135);
not NOT_2705(I3550,g1295);
not NOT_2706(I7802,g5920);
not NOT_2707(g5708,I7469);
not NOT_2708(g1119,I2159);
not NOT_2709(g1319,I2312);
not NOT_2710(g2066,g1341);
not NOT_2711(g3150,I4391);
not NOT_2712(g5219,I6885);
not NOT_2713(I3137,g1315);
not NOT_2714(I8103,g6134);
not NOT_2715(I3395,g1286);
not NOT_2716(I3337,g1338);
not NOT_2717(g4496,I6008);
not NOT_2718(g1352,I2391);
not NOT_2719(I9110,g6864);
not NOT_2720(g1577,g1001);
not NOT_2721(g4550,I6126);
not NOT_2722(g3773,g3466);
not NOT_2723(g4845,I6543);
not NOT_2724(I4537,g2877);
not NOT_2725(I8696,g6569);
not NOT_2726(g2165,I3294);
not NOT_2727(g5958,g5818);
not NOT_2728(I2147,g6);
not NOT_2729(g6608,I8690);
not NOT_2730(g4195,I5615);
not NOT_2731(g4137,I5493);
not NOT_2732(g830,g338);
not NOT_2733(I5716,g3942);
not NOT_2734(g3769,g3622);
not NOT_2735(I9002,g6802);
not NOT_2736(g2827,g2485);
not NOT_2737(I6952,g5124);
not NOT_2738(I5848,g3856);
not NOT_2739(g3836,I5033);
not NOT_2740(g3212,I4455);
not NOT_2741(g6423,I8279);
not NOT_2742(I4243,g1853);
not NOT_2743(g2333,I3485);
not NOT_2744(I8240,g6287);
not NOT_2745(g1975,I3086);
not NOT_2746(I5699,g3844);
not NOT_2747(g4807,g4473);
not NOT_2748(I9236,g6939);
not NOT_2749(g3967,I5223);
not NOT_2750(I6561,g4707);
not NOT_2751(g6588,I8632);
not NOT_2752(I4935,g3369);
not NOT_2753(I2596,g985);
not NOT_2754(g6161,g5926);
not NOT_2755(g1274,g856);
not NOT_2756(g6361,I8147);
not NOT_2757(g1426,I2445);
not NOT_2758(g2196,I3337);
not NOT_2759(I7600,g5605);
not NOT_2760(g2803,g2440);
not NOT_2761(I6004,g4159);
not NOT_2762(g3229,I4486);
not NOT_2763(I6986,g5230);
not NOT_2764(g6051,g5824);
not NOT_2765(g5270,I6927);
not NOT_2766(g804,I1871);
not NOT_2767(I3255,g1650);
not NOT_2768(g2538,I3656);
not NOT_2769(g1325,I2330);
not NOT_2770(g1821,I2883);
not NOT_2771(g844,g578);
not NOT_2772(I3481,g1461);
not NOT_2773(I8034,g6242);
not NOT_2774(g4142,I5508);
not NOT_2775(g4248,I5696);
not NOT_2776(g2509,I3635);
not NOT_2777(I6546,g4692);
not NOT_2778(I3726,g2030);
not NOT_2779(g4815,I6495);
not NOT_2780(I5644,g4059);
not NOT_2781(I8147,g6182);
not NOT_2782(g5124,I6780);
not NOT_2783(g6103,I7805);
not NOT_2784(I5119,g3714);
not NOT_2785(g4692,I6280);
not NOT_2786(g2467,I3599);
not NOT_2787(I8681,g6566);
not NOT_2788(g4726,I6352);
not NOT_2789(g5469,I7153);
not NOT_2790(g4154,I5548);
not NOT_2791(I2601,g1161);
not NOT_2792(g6696,I8806);
not NOT_2793(g1636,I2593);
not NOT_2794(g3921,g3512);
not NOT_2795(g5540,I7284);
not NOT_2796(I5577,g4022);
not NOT_2797(g1106,I2128);
not NOT_2798(g6732,I8888);
not NOT_2799(g853,g642);
not NOT_2800(g2256,I3395);
not NOT_2801(g1790,I2842);
not NOT_2802(I2922,g1774);
not NOT_2803(g6508,I8444);
not NOT_2804(I5893,g3747);
not NOT_2805(I3979,g1836);
not NOT_2806(I2581,g946);
not NOT_2807(I3112,g1439);
not NOT_2808(g1461,I2460);
not NOT_2809(g3462,g2679);
not NOT_2810(g1756,I2779);
not NOT_2811(g2381,I3528);
not NOT_2812(I6789,g4871);
not NOT_2813(g4783,I6441);
not NOT_2814(g6043,g5824);
not NOT_2815(I7871,g6097);
not NOT_2816(I2460,g952);
not NOT_2817(I3001,g1267);
not NOT_2818(g4112,I5418);
not NOT_2819(g4218,I5640);
not NOT_2820(g2197,I3340);
not NOT_2821(g4267,I5720);
not NOT_2822(I4166,g2390);
not NOT_2823(g2397,I3540);
not NOT_2824(I4366,g2244);
not NOT_2825(g5199,I6867);
not NOT_2826(g5399,I7065);
not NOT_2827(g1046,g489);
not NOT_2828(I3761,g2505);
not NOT_2829(g3788,g3466);
not NOT_2830(g6034,g5824);
not NOT_2831(g6434,I8300);
not NOT_2832(g6565,I8579);
not NOT_2833(I6299,g4438);
not NOT_2834(g4293,I5750);
not NOT_2835(g4129,I5469);
not NOT_2836(g5797,I7596);
not NOT_2837(I3830,g2179);
not NOT_2838(I2995,g1742);
not NOT_2839(g6147,I7871);
not NOT_2840(g1345,I2382);
not NOT_2841(g1841,I2929);
not NOT_2842(g6347,I8103);
not NOT_2843(I1832,g143);
not NOT_2844(I2479,g1049);
not NOT_2845(I7339,g5540);
not NOT_2846(g1191,g38);
not NOT_2847(I2668,g1011);
not NOT_2848(g1391,I2424);
not NOT_2849(I1853,g211);
not NOT_2850(g3192,I4429);
not NOT_2851(g6533,I8515);
not NOT_2852(g3085,I4324);
not NOT_2853(I3746,g2035);
not NOT_2854(I7838,g5947);
not NOT_2855(g4727,I6355);
not NOT_2856(I4964,g3673);
not NOT_2857(g3485,g2986);
not NOT_2858(I2190,g297);
not NOT_2859(g1695,g1106);
not NOT_2860(g6697,I8809);
not NOT_2861(g1637,I2596);
not NOT_2862(g1107,I2131);
not NOT_2863(g2631,I3773);
not NOT_2864(g6596,I8656);
not NOT_2865(g3854,I5071);
not NOT_2866(I5106,g3247);
not NOT_2867(I8597,g6445);
not NOT_2868(g2817,g2461);
not NOT_2869(I6244,g4519);
not NOT_2870(I7077,g5281);
not NOT_2871(g4703,I6299);
not NOT_2872(g6413,I8249);
not NOT_2873(I5790,g3803);
not NOT_2874(g1858,I2964);
not NOT_2875(I6078,g4387);
not NOT_2876(I6340,g4561);
not NOT_2877(I7643,g5752);
not NOT_2878(I3068,g1439);
not NOT_2879(g5923,I7701);
not NOT_2880(I9038,g6833);
not NOT_2881(I3468,g1802);
not NOT_2882(I4279,g2230);
not NOT_2883(I5756,g3922);
not NOT_2884(g6820,I8997);
not NOT_2885(g4624,g4265);
not NOT_2886(I6959,g5089);
not NOT_2887(I5622,g3914);
not NOT_2888(g3219,I4462);
not NOT_2889(I5027,g3267);
not NOT_2890(I4318,g2171);
not NOT_2891(I7634,g5727);
not NOT_2892(I5427,g3726);
not NOT_2893(g3031,I4246);
not NOT_2894(g1115,g40);
not NOT_2895(g6117,g5880);
not NOT_2896(g1315,I2296);
not NOT_2897(g1811,I2864);
not NOT_2898(g1642,g809);
not NOT_2899(I8479,g6482);
not NOT_2900(g2585,I3708);
not NOT_2901(I7104,g5273);
not NOT_2902(I5904,g3749);
not NOT_2903(I8668,g6530);
not NOT_2904(g5886,g5753);
not NOT_2905(I8840,g6657);
not NOT_2906(g2041,I3152);
not NOT_2907(g6601,I8671);
not NOT_2908(I5514,g3882);
not NOT_2909(I3349,g1334);
not NOT_2910(I2053,g684);
not NOT_2911(g5114,I6756);
not NOT_2912(I5403,g3970);
not NOT_2913(g5314,I6972);
not NOT_2914(I2453,g952);
not NOT_2915(g1654,g878);
not NOT_2916(g4716,I6330);
not NOT_2917(g4149,I5529);
not NOT_2918(g6922,I9203);
not NOT_2919(I8156,g6167);
not NOT_2920(I3198,g1819);
not NOT_2921(I3855,g2550);
not NOT_2922(I5391,g3975);
not NOT_2923(g3911,I5148);
not NOT_2924(g6581,g6493);
not NOT_2925(g4848,I6552);
not NOT_2926(I5637,g3914);
not NOT_2927(g1880,g1603);
not NOT_2928(g4198,I5618);
not NOT_2929(g4699,I6289);
not NOT_2930(g6597,I8659);
not NOT_2931(g4855,I6573);
not NOT_2932(g4398,I5893);
not NOT_2933(g2772,I3961);
not NOT_2934(I4321,g1917);
not NOT_2935(g5136,I6786);
not NOT_2936(g3225,I4474);
not NOT_2937(I5223,g3537);
not NOT_2938(g2743,g2333);
not NOT_2939(g6784,I8940);
not NOT_2940(g2890,g1875);
not NOT_2941(g3073,I4300);
not NOT_2942(g1978,g1387);
not NOT_2943(g3796,g3388);
not NOT_2944(g1017,I2053);
not NOT_2945(I2929,g1659);
not NOT_2946(g798,I1868);
not NOT_2947(g2505,I3629);
not NOT_2948(I3644,g1685);
not NOT_2949(g3124,I4371);
not NOT_2950(g1935,I3040);
not NOT_2951(g3980,I5264);
not NOT_2952(g2856,g2010);
not NOT_2953(g2734,I3902);
not NOT_2954(I8432,g6411);
not NOT_2955(I3319,g1636);
not NOT_2956(g1982,I3093);
not NOT_2957(g754,I1850);
not NOT_2958(g4524,I6084);
not NOT_2959(g836,g349);
not NOT_2960(I8453,g6414);
not NOT_2961(g6840,I9041);
not NOT_2962(I4519,g2788);
not NOT_2963(g4644,I6231);
not NOT_2964(I3152,g1322);
not NOT_2965(I3258,g1760);
not NOT_2966(g3540,I4762);
not NOT_2967(I3352,g1285);
not NOT_2968(g1328,I2337);
not NOT_2969(g5887,g5742);
not NOT_2970(g4119,I5439);
not NOT_2971(g5465,I7143);
not NOT_2972(g1542,g878);
not NOT_2973(g1330,I2343);
not NOT_2974(g3177,I4414);
not NOT_2975(I3717,g2154);
not NOT_2976(g5230,I6895);
not NOT_2977(g845,g582);
not NOT_2978(g4152,I5542);
not NOT_2979(g6501,I8423);
not NOT_2980(g4577,g4202);
not NOT_2981(g4717,g4465);
not NOT_2982(g5433,I7107);
not NOT_2983(I5654,g3742);
not NOT_2984(I6930,g5017);
not NOT_2985(g2863,g2296);
not NOT_2986(I6464,g4562);
not NOT_2987(I3599,g1484);
not NOT_2988(g2713,I3868);
not NOT_2989(I3274,g1773);
not NOT_2990(g4386,I5865);
not NOT_2991(g3199,g1861);
not NOT_2992(g5550,g5331);
not NOT_2993(I3614,g1295);
not NOT_2994(g3781,I4976);
not NOT_2995(I3370,g1805);
not NOT_2996(g5137,I6789);
not NOT_2997(g5395,I7061);
not NOT_2998(g5891,g5731);
not NOT_2999(g3898,g3575);
not NOT_3000(g3900,g3575);
not NOT_3001(I3325,g1340);
not NOT_3002(g4426,I5929);
not NOT_3003(I2735,g1118);
not NOT_3004(g3797,g3388);
not NOT_3005(I9085,g6850);
not NOT_3006(g1902,I3001);
not NOT_3007(g6163,g5926);
not NOT_3008(g4614,g4308);
not NOT_3009(I2782,g1177);
not NOT_3010(I7679,g5726);
not NOT_3011(g6363,I8153);
not NOT_3012(g4370,I5831);
not NOT_3013(I8626,g6543);
not NOT_3014(g3510,g2709);
not NOT_3015(I5612,g3910);
not NOT_3016(g6032,g5770);
not NOT_3017(g4125,I5457);
not NOT_3018(g2688,I3836);
not NOT_3019(g2857,I4059);
not NOT_3020(g3291,g3037);
not NOT_3021(I3083,g1426);
not NOT_3022(g2976,g2197);
not NOT_3023(g1823,I2887);
not NOT_3024(I2949,g1263);
not NOT_3025(g1366,I2402);
not NOT_3026(g5266,I6923);
not NOT_3027(I2627,g1053);
not NOT_3028(g1056,g89);
not NOT_3029(g6568,I8588);
not NOT_3030(I5328,g3502);
not NOT_3031(g1529,g1076);
not NOT_3032(I7805,g5923);
not NOT_3033(I5542,g3984);
not NOT_3034(I2998,g1257);
not NOT_3035(g1649,g985);
not NOT_3036(g1348,I2385);
not NOT_3037(g3259,g2996);
not NOT_3038(I4358,g2525);
not NOT_3039(g5248,g4911);
not NOT_3040(g4636,g4286);
not NOT_3041(g1355,I2394);
not NOT_3042(g4106,I5400);
not NOT_3043(g5255,g4933);
not NOT_3044(g3852,I5065);
not NOT_3045(I9031,g6809);
not NOT_3046(g2760,I3942);
not NOT_3047(g3488,g2728);
not NOT_3048(I8894,g6709);
not NOT_3049(g4790,I6456);
not NOT_3050(g5692,I7451);
not NOT_3051(I4587,g2962);
not NOT_3052(g5097,I6733);
not NOT_3053(g5726,I7487);
not NOT_3054(g4187,I5591);
not NOT_3055(I9176,g6881);
not NOT_3056(g4387,I5868);
not NOT_3057(I9005,g6817);
not NOT_3058(g1063,g675);
not NOT_3059(g3886,g3346);
not NOT_3060(g4622,g4252);
not NOT_3061(g2608,I3746);
not NOT_3062(I2919,g1787);
not NOT_3063(g2779,g2394);
not NOT_3064(g4904,g4812);
not NOT_3065(g3114,I4362);
not NOT_3066(I2952,g1594);
not NOT_3067(g1279,g848);
not NOT_3068(g4514,I6054);
not NOT_3069(g1720,g1111);
not NOT_3070(g4003,g3441);
not NOT_3071(g1118,g36);
not NOT_3072(I3391,g1646);
not NOT_3073(g1318,I2309);
not NOT_3074(g4403,I5904);
not NOT_3075(I5490,g3832);
not NOT_3076(g5112,I6750);
not NOT_3077(g2588,I3717);
not NOT_3078(g4145,I5517);
not NOT_3079(g4841,I6531);
not NOT_3080(I8603,g6449);
not NOT_3081(g2361,I3513);
not NOT_3082(I6769,g4786);
not NOT_3083(g4763,I6397);
not NOT_3084(g4191,I5603);
not NOT_3085(g4391,I5876);
not NOT_3086(I5056,g3567);
not NOT_3087(I2986,g1504);
not NOT_3088(I3307,g1339);
not NOT_3089(g1193,I2204);
not NOT_3090(I5529,g3854);
not NOT_3091(I4420,g2096);
not NOT_3092(I5148,g3450);
not NOT_3093(g3136,I4382);
not NOT_3094(g2327,I3481);
not NOT_3095(I6918,g5124);
not NOT_3096(I4507,g2739);
not NOT_3097(g5329,I6989);
not NOT_3098(g1549,g878);
not NOT_3099(g4107,I5403);
not NOT_3100(I7042,g5310);
not NOT_3101(g947,g74);
not NOT_3102(g6894,I9149);
not NOT_3103(g1834,I2916);
not NOT_3104(I4794,g2814);
not NOT_3105(g4307,I5774);
not NOT_3106(I5851,g3739);
not NOT_3107(g4536,I6118);
not NOT_3108(I3858,g2197);
not NOT_3109(I8702,g6572);
not NOT_3110(g2346,I3496);
not NOT_3111(g6735,I8897);
not NOT_3112(I3016,g1754);
not NOT_3113(I2970,g1504);
not NOT_3114(g5727,I7490);
not NOT_3115(I7164,g5433);
not NOT_3116(g2103,I3225);
not NOT_3117(g858,g301);
not NOT_3118(I2925,g1762);
not NOT_3119(g4858,I6582);
not NOT_3120(I3522,g1664);
not NOT_3121(g4016,I5320);
not NOT_3122(I3115,g1519);
not NOT_3123(I3251,g1471);
not NOT_3124(I3811,g2145);
not NOT_3125(I8276,g6303);
not NOT_3126(g1321,I2318);
not NOT_3127(I3047,g1426);
not NOT_3128(g1670,I2648);
not NOT_3129(g3228,I4483);
not NOT_3130(g3465,g2986);
not NOT_3131(g3322,g3070);
not NOT_3132(I5463,g3783);
not NOT_3133(g3230,I4489);
not NOT_3134(g4522,I6078);
not NOT_3135(g4115,I5427);
not NOT_3136(g2753,I3927);
not NOT_3137(g4251,I5705);
not NOT_3138(g1232,I2228);
not NOT_3139(I4300,g2234);
not NOT_3140(g6526,I8494);
not NOT_3141(g1813,I2870);
not NOT_3142(I8527,g6440);
not NOT_3143(I8647,g6528);
not NOT_3144(I2617,g1193);
not NOT_3145(I5720,g4022);
not NOT_3146(g2043,I3158);
not NOT_3147(g6039,g5824);
not NOT_3148(I8764,g6564);
not NOT_3149(g2443,I3578);
not NOT_3150(g6484,g6361);
not NOT_3151(g3096,I4343);
not NOT_3152(g5468,I7150);
not NOT_3153(g1519,I2491);
not NOT_3154(g1740,g1116);
not NOT_3155(I7012,g5316);
not NOT_3156(g6850,I9077);
not NOT_3157(I6895,g5010);
not NOT_3158(I1835,g205);
not NOT_3159(g3845,I5050);
not NOT_3160(I5843,g3851);
not NOT_3161(g2316,I3468);
not NOT_3162(I3537,g1305);
not NOT_3163(I8503,g6434);
not NOT_3164(g1552,g1030);
not NOT_3165(I5457,g3766);
not NOT_3166(g2565,I3675);
not NOT_3167(g6583,I8617);
not NOT_3168(g850,g602);
not NOT_3169(g5576,g5415);
not NOT_3170(g4537,g4410);
not NOT_3171(I7029,g5149);
not NOT_3172(g2347,I3499);
not NOT_3173(I5686,g3942);
not NOT_3174(I4123,g2043);
not NOT_3175(g3807,I5006);
not NOT_3176(g1586,g1052);
not NOT_3177(g3859,I5078);
not NOT_3178(g6276,I7960);
not NOT_3179(g4612,g4320);
not NOT_3180(g2914,g1928);
not NOT_3181(g6616,I8710);
not NOT_3182(I3629,g1759);
not NOT_3183(g6561,I8567);
not NOT_3184(I3328,g1273);
not NOT_3185(I2738,g1236);
not NOT_3186(I8617,g6539);
not NOT_3187(g1341,I2376);
not NOT_3188(g2413,I3553);
not NOT_3189(I4351,g2233);
not NOT_3190(g3342,g3086);
not NOT_3191(g4128,I5466);
not NOT_3192(g1710,g1109);
not NOT_3193(g4629,g4276);
not NOT_3194(I6485,g4603);
not NOT_3195(g6527,I8497);
not NOT_3196(g6404,I8226);
not NOT_3197(g4328,g4092);
not NOT_3198(I2140,g28);
not NOT_3199(g1645,I2614);
not NOT_3200(I2340,g1142);
not NOT_3201(g4130,I5472);
not NOT_3202(I5938,g4351);
not NOT_3203(I7963,g6276);
not NOT_3204(I3800,g2145);
not NOT_3205(g3481,g2612);
not NOT_3206(I2907,g1498);
not NOT_3207(g2820,g2470);
not NOT_3208(g2936,g2026);
not NOT_3209(g5524,I7264);
not NOT_3210(g6503,I8429);
not NOT_3211(g3354,g3096);
not NOT_3212(I4410,g2088);
not NOT_3213(I7808,g5919);
not NOT_3214(g2117,I3244);
not NOT_3215(g3960,I5204);
not NOT_3216(g2317,I3471);
not NOT_3217(g5119,I6769);
not NOT_3218(g6925,I9208);
not NOT_3219(I7707,g5701);
not NOT_3220(I5606,g3821);
not NOT_3221(g1659,I2638);
not NOT_3222(g1358,g1119);
not NOT_3223(g5352,I7002);
not NOT_3224(g5577,g5420);
not NOT_3225(g4213,I5633);
not NOT_3226(g5717,I7478);
not NOT_3227(I3902,g2576);
not NOT_3228(g6120,I7832);
not NOT_3229(g2922,g1960);
not NOT_3230(g1587,g1123);
not NOT_3231(I6812,g5110);
not NOT_3232(I8991,g6788);
not NOT_3233(g3783,I4980);
not NOT_3234(g1111,I2143);
not NOT_3235(I3090,g1504);
not NOT_3236(I9008,g6818);
not NOT_3237(g5893,g5753);
not NOT_3238(g1275,g842);
not NOT_3239(g6277,I7963);
not NOT_3240(g2581,I3694);
not NOT_3241(I3823,g2125);
not NOT_3242(g3267,g3030);
not NOT_3243(I4667,g2908);
not NOT_3244(g3312,I4587);
not NOT_3245(I7865,g6095);
not NOT_3246(I4343,g2525);
not NOT_3247(g2060,g1369);
not NOT_3248(g6617,I8713);
not NOT_3249(g6906,I9185);
not NOT_3250(g5975,g5821);
not NOT_3251(g4512,I6048);
not NOT_3252(I4282,g2525);
not NOT_3253(g2460,I3590);
not NOT_3254(I7604,g5605);
not NOT_3255(I8907,g6702);
not NOT_3256(I3056,g1519);
not NOT_3257(g3001,I4198);
not NOT_3258(g1174,g37);
not NOT_3259(g4823,I6507);
not NOT_3260(I2663,g1006);
not NOT_3261(g4166,I5568);
not NOT_3262(g6516,g6409);
not NOT_3263(g5274,I6933);
not NOT_3264(I8435,g6413);
not NOT_3265(I3148,g1595);
not NOT_3266(I8690,g6571);
not NOT_3267(g1985,I3096);
not NOT_3268(I4334,g2256);
not NOT_3269(I8482,g6461);
not NOT_3270(g2739,I3906);
not NOT_3271(g3761,g3605);
not NOT_3272(I3155,g1612);
not NOT_3273(I3355,g1608);
not NOT_3274(I2402,g774);
not NOT_3275(g4529,I6099);
not NOT_3276(g1284,g851);
not NOT_3277(g4148,I5526);
not NOT_3278(I6733,g4773);
not NOT_3279(I8656,g6532);
not NOT_3280(g3830,I5019);
not NOT_3281(I9122,g6864);
not NOT_3282(g2079,g1348);
not NOT_3283(g4155,I5551);
not NOT_3284(g4851,I6561);
not NOT_3285(g6892,I9143);
not NOT_3286(g1832,I2910);
not NOT_3287(I9230,g6936);
not NOT_3288(g1853,I2955);
not NOT_3289(g2840,g2538);
not NOT_3290(I2877,g1123);
not NOT_3291(I5879,g3745);
not NOT_3292(g5544,g5331);
not NOT_3293(g2390,I3531);
not NOT_3294(I6324,g4450);
not NOT_3295(g1559,g965);
not NOT_3296(I6069,g4213);
not NOT_3297(I8110,g6143);
not NOT_3298(g4463,g4364);
not NOT_3299(g943,g496);
not NOT_3300(g1931,I3034);
not NOT_3301(g6709,I8837);
not NOT_3302(g3932,I5169);
not NOT_3303(I6540,g4714);
not NOT_3304(I3720,g2155);
not NOT_3305(g6078,g5801);
not NOT_3306(I1871,g281);
not NOT_3307(I6377,g4569);
not NOT_3308(g5061,I6701);
not NOT_3309(g6478,I8342);
not NOT_3310(I2464,g850);
not NOT_3311(I3367,g1283);
not NOT_3312(g5387,I7051);
not NOT_3313(I9137,g6864);
not NOT_3314(g1905,I3004);
not NOT_3315(I8002,g6110);
not NOT_3316(g866,g314);
not NOT_3317(I2785,g1222);
not NOT_3318(I7086,g5281);
not NOT_3319(I5615,g3914);
not NOT_3320(g6035,g5824);
not NOT_3321(g4720,I6340);
not NOT_3322(I3843,g2145);
not NOT_3323(g4118,I5436);
not NOT_3324(g4619,g4248);
not NOT_3325(g6517,I8467);
not NOT_3326(g1204,g39);
not NOT_3327(g3677,g3140);
not NOT_3328(g6876,I9095);
not NOT_3329(g4843,I6537);
not NOT_3330(g3866,I5091);
not NOT_3331(g2954,g2381);
not NOT_3332(I4593,g2966);
not NOT_3333(g5046,I6680);
not NOT_3334(g2163,I3288);
not NOT_3335(g6656,I8764);
not NOT_3336(g4193,I5609);
not NOT_3337(I2237,g465);
not NOT_3338(g2032,g1749);
not NOT_3339(g4393,I5882);
not NOT_3340(I5545,g3814);
not NOT_3341(g5403,I7069);
not NOT_3342(I1838,g206);
not NOT_3343(g3848,I5059);
not NOT_3344(I5591,g3821);
not NOT_3345(I4264,g2212);
not NOT_3346(I2394,g719);
not NOT_3347(g5391,I7055);
not NOT_3348(g2568,I3678);
not NOT_3349(I2731,g1117);
not NOT_3350(I4050,g2059);
not NOT_3351(g3241,I4522);
not NOT_3352(g2912,g2001);
not NOT_3353(g4121,I5445);
not NOT_3354(g1969,I3080);
not NOT_3355(I3232,g1782);
not NOT_3356(g4321,I5790);
not NOT_3357(g5307,I6959);
not NOT_3358(g2157,I3278);
not NOT_3359(g5536,g5467);
not NOT_3360(g2357,I3509);
not NOT_3361(g1123,I2165);
not NOT_3362(g1323,I2324);
not NOT_3363(g4625,g4267);
not NOT_3364(I3909,g2044);
not NOT_3365(g4232,I5674);
not NOT_3366(g6402,I8220);
not NOT_3367(g6824,I9005);
not NOT_3368(g1666,g1088);
not NOT_3369(g4938,I6630);
not NOT_3370(I6819,g5019);
not NOT_3371(g6236,g6070);
not NOT_3372(I3519,g1305);
not NOT_3373(I8295,g6295);
not NOT_3374(I2955,g1729);
not NOT_3375(I7487,g5684);
not NOT_3376(g856,g654);
not NOT_3377(I6923,g5124);
not NOT_3378(g1528,g878);
not NOT_3379(I5204,g3534);
not NOT_3380(I5630,g3914);
not NOT_3381(I6488,g4603);
not NOT_3382(g1351,I2388);
not NOT_3383(g1648,I2623);
not NOT_3384(I2814,g1222);
not NOT_3385(g1875,I2970);
not NOT_3386(g4519,I6069);
not NOT_3387(g5115,I6759);
not NOT_3388(g6590,I8638);
not NOT_3389(g5251,g5069);
not NOT_3390(g6877,I9098);
not NOT_3391(g3258,I4537);
not NOT_3392(I4777,g2962);
not NOT_3393(I6701,g4726);
not NOT_3394(g5315,g5116);
not NOT_3395(g3867,I5094);
not NOT_3396(I2150,g10);
not NOT_3397(g1655,g985);
not NOT_3398(g6657,I8767);
not NOT_3399(g4606,g4193);
not NOT_3400(I3687,g1814);
not NOT_3401(I8089,g6120);
not NOT_3402(I2773,g1191);
not NOT_3403(g5874,I7634);
not NOT_3404(g1410,g1233);
not NOT_3405(I8966,g6796);
not NOT_3406(I5750,g4022);
not NOT_3407(I7045,g5167);
not NOT_3408(I6114,g4405);
not NOT_3409(g3975,I5249);
not NOT_3410(I7173,g5436);
not NOT_3411(g1884,I2979);
not NOT_3412(I7091,g5281);
not NOT_3413(g6899,I9164);
not NOT_3414(I4799,g2967);
not NOT_3415(I2212,g123);
not NOT_3416(g929,g49);
not NOT_3417(g6785,I8943);
not NOT_3418(g5880,g5824);
not NOT_3419(I5040,g3271);
not NOT_3420(I2967,g1682);
not NOT_3421(g5537,g5385);
not NOT_3422(g2778,g2391);
not NOT_3423(I1862,g278);
not NOT_3424(I3525,g1461);
not NOT_3425(g3370,g3124);
not NOT_3426(g2894,g1891);
not NOT_3427(I7007,g5314);
not NOT_3428(g1372,I2408);
not NOT_3429(g4141,I5505);
not NOT_3430(g6563,I8573);
not NOT_3431(I6008,g4163);
not NOT_3432(I3691,g1732);
not NOT_3433(g4525,I6087);
not NOT_3434(g1143,I2172);
not NOT_3435(g3984,g3564);
not NOT_3436(I8150,g6185);
not NOT_3437(g1282,g849);
not NOT_3438(I8438,g6416);
not NOT_3439(g3083,I4318);
not NOT_3440(g1988,I3099);
not NOT_3441(I4802,g2877);
not NOT_3442(I6972,g5135);
not NOT_3443(g3483,g2716);
not NOT_3444(I7261,g5458);
not NOT_3445(g6194,I7906);
not NOT_3446(g1334,I2355);
not NOT_3447(I3158,g1829);
not NOT_3448(I3659,g1491);
not NOT_3449(I3358,g1323);
not NOT_3450(g5328,I6986);
not NOT_3451(I1927,g665);
not NOT_3452(g6489,g6369);
not NOT_3453(g5542,g5331);
not NOT_3454(g5330,I6992);
not NOT_3455(g3306,g3057);
not NOT_3456(g2998,I4195);
not NOT_3457(g4158,I5556);
not NOT_3458(g4659,I6250);
not NOT_3459(g1555,I2521);
not NOT_3460(g3790,g3388);
not NOT_3461(I3587,g1461);
not NOT_3462(g1792,I2848);
not NOT_3463(g2603,I3733);
not NOT_3464(g2039,I3148);
not NOT_3465(g3187,I4424);
not NOT_3466(g2484,I3611);
not NOT_3467(g3387,I4664);
not NOT_3468(g3461,g2986);
not NOT_3469(g4587,g4215);
not NOT_3470(I6033,g4179);
not NOT_3471(g5554,g5455);
not NOT_3472(g3622,I4821);
not NOT_3473(g4111,I5415);
not NOT_3474(I8229,g6330);
not NOT_3475(I9149,g6884);
not NOT_3476(I2620,g1177);
not NOT_3477(g1113,I2147);
not NOT_3478(I4492,g3001);
not NOT_3479(g4615,g4322);
not NOT_3480(g2583,g1830);
not NOT_3481(g3904,g3575);
not NOT_3482(g3200,I4437);
not NOT_3483(I6096,g4397);
not NOT_3484(g3046,I4267);
not NOT_3485(g899,I1924);
not NOT_3486(g4374,I5837);
not NOT_3487(I3284,g1702);
not NOT_3488(g2919,g1937);
not NOT_3489(g1908,I3007);
not NOT_3490(I2788,g1236);
not NOT_3491(g1094,I2122);
not NOT_3492(I5618,g3821);
not NOT_3493(g2952,g2381);
not NOT_3494(I6337,g4455);
not NOT_3495(I5343,g3599);
not NOT_3496(g2276,I3425);
not NOT_3497(g1567,I2537);
not NOT_3498(g4284,I5739);
not NOT_3499(g5512,I7254);
not NOT_3500(g4545,g4416);
not NOT_3501(g5090,g4741);
not NOT_3502(g6409,g6285);
not NOT_3503(g5490,I7190);
not NOT_3504(I7689,g5708);
not NOT_3505(g4380,I5851);
not NOT_3506(I2842,g1177);
not NOT_3507(g1776,I2821);
not NOT_3508(g1593,g1054);
not NOT_3509(g2004,I3115);
not NOT_3510(g4853,I6567);
not NOT_3511(g6836,I9031);
not NOT_3512(I2485,g766);
not NOT_3513(I3794,g2044);
not NOT_3514(g2986,g2010);
not NOT_3515(g4020,I5324);
not NOT_3516(g6212,I7910);
not NOT_3517(I5548,g4059);
not NOT_3518(g5456,g5300);
not NOT_3519(g2647,I3791);
not NOT_3520(I8837,g6665);
not NOT_3521(g5148,I6812);
not NOT_3522(g5649,I7404);
not NOT_3523(g4507,I6033);
not NOT_3524(g3223,I4468);
not NOT_3525(I4623,g2962);
not NOT_3526(I1947,g699);
not NOT_3527(g2764,g2357);
not NOT_3528(I8620,g6541);
not NOT_3529(I8462,g6430);
not NOT_3530(I9119,g6855);
not NOT_3531(I2854,g1236);
not NOT_3532(g4559,g4187);
not NOT_3533(g5155,g5099);
not NOT_3534(g5355,I7007);
not NOT_3535(I9152,g6889);
not NOT_3536(g3016,I4223);
not NOT_3537(g6229,g6036);
not NOT_3538(g1160,I2179);
not NOT_3539(g5260,g4938);
not NOT_3540(I6081,g4388);
not NOT_3541(I4375,g2254);
not NOT_3542(g6822,g6786);
not NOT_3543(g1641,I2604);
not NOT_3544(g3251,I4534);
not NOT_3545(I6692,g4720);
not NOT_3546(g1450,I2453);
not NOT_3547(g5063,g4799);
not NOT_3548(I7910,g5905);
not NOT_3549(I8249,g6289);
not NOT_3550(g4628,g4273);
not NOT_3551(g4515,I6057);
not NOT_3552(g2120,I3251);
not NOT_3553(I4285,g2555);
not NOT_3554(g2320,I3474);
not NOT_3555(g4100,I5382);
not NOT_3556(g1724,I2724);
not NOT_3557(g3874,I5103);
not NOT_3558(I2958,g1257);
not NOT_3559(I5094,g3705);
not NOT_3560(I2376,g729);
not NOT_3561(I8485,g6479);
not NOT_3562(g5720,I7481);
not NOT_3563(I2405,g1112);
not NOT_3564(g2906,g1911);
not NOT_3565(g2789,g2410);
not NOT_3566(g1878,I2973);
not NOT_3567(g5118,I6766);
not NOT_3568(I9170,g6883);
not NOT_3569(I1917,g48);
and AND2_0(g2771,g2497,g1975);
and AND2_1(g6620,g6516,g6117);
and AND2_2(g5193,g532,g4967);
and AND4_0(I5360,g3532,g3536,g3539,g3544);
and AND2_3(g5598,g5046,g5509);
and AND2_4(g6249,g1332,g5892);
and AND2_5(g4666,g4630,g4627);
and AND2_6(g3629,g2809,g2738);
and AND2_7(g3328,g2701,g1894);
and AND2_8(g6085,g1161,g5731);
and AND2_9(g4351,g166,g3776);
and AND2_10(g4648,g4407,g79);
and AND2_11(g5232,g548,g4980);
and AND2_12(g2340,g1398,g1387);
and AND2_13(g5938,g5114,g5791);
and AND2_14(g5909,g5787,g3384);
and AND2_15(g1802,g89,g1064);
and AND2_16(g3554,g2941,g179);
and AND2_17(g4410,g3903,g1474);
and AND2_18(g6640,g1612,g6549);
and AND2_19(g4172,g3930,g1366);
and AND2_20(g4372,g406,g3790);
and AND2_21(g3512,g2928,g1764);
and AND2_22(g3490,g353,g2959);
and AND2_23(g4667,g4653,g4651);
and AND2_24(g3166,g2042,g1233);
and AND2_25(g3366,g248,g2893);
and AND2_26(g6829,g6806,g5958);
and AND2_27(g3649,g3104,g2764);
and AND2_28(g6911,g6904,g6902);
and AND2_29(g3155,g248,g2461);
and AND2_30(g3698,g2284,g2835);
and AND2_31(g6270,g1726,g6062);
and AND2_32(g4792,g1417,g4471);
and AND3_0(g6473,g2036,g6397,g1628);
and AND2_33(g4621,g3953,g4364);
and AND2_34(g5158,g504,g4993);
and AND2_35(g6124,g5705,g5958);
and AND2_36(g6324,g3880,g6212);
and AND3_1(g6469,g2121,g2032,g6394);
and AND2_37(g3279,g2599,g2612);
and AND2_38(g3619,g2449,g3057);
and AND2_39(g3167,g1883,g921);
and AND2_40(g5311,g5013,g4468);
and AND2_41(g3367,g2809,g1960);
and AND2_42(g3652,g2544,g3096);
and AND3_2(g3843,g2856,g945,g3533);
and AND2_43(g4593,g4277,g947);
and AND2_44(g3686,g2256,g2819);
and AND2_45(g5180,g414,g4950);
and AND2_46(g5380,g188,g5264);
and AND2_47(g4160,g3923,g1345);
and AND2_48(g3321,g2252,g2713);
and AND2_49(g2089,g1123,g1578);
and AND2_50(g6245,g1329,g5889);
and AND2_51(g4360,g184,g3785);
and AND2_52(g3670,g2234,g2792);
and AND2_53(g3625,g2619,g2320);
and AND2_54(g6291,g5210,g6161);
and AND2_55(g4050,I5359,I5360);
and AND2_56(g5559,g5024,g5453);
and AND2_57(g6144,g3183,g5997);
and AND2_58(g6344,g6272,g6080);
and AND2_59(g2948,g2137,g1595);
and AND2_60(g6259,g1699,g6044);
and AND2_61(g4179,g390,g3902);
and AND2_62(g2955,g2381,g297);
and AND2_63(g6088,g1143,g5753);
and AND2_64(g6852,g6847,g2295);
and AND2_65(g6923,g6918,g6917);
and AND2_66(g5515,g590,g5364);
and AND2_67(g1499,g1101,g1094);
and AND2_68(g4835,g4533,g4530);
and AND2_69(g3687,g2245,g2820);
and AND3_3(g4271,g2121,g1749,g4004);
and AND3_4(g4611,g3985,g119,g4300);
and AND2_70(g3341,g2998,g2709);
and AND2_71(g6650,g6580,g6235);
and AND2_72(g4541,g631,g4199);
and AND2_73(g3645,g2497,g3090);
and AND2_74(g5123,g4670,g1936);
and AND2_75(g3691,g2268,g2828);
and AND2_76(g4209,g3816,g865);
and AND2_77(g4353,g3989,g3332);
and AND2_78(g6336,g6246,g6065);
and AND2_79(g6768,g6750,g3477);
and AND2_80(g4744,g3434,g4582);
and AND2_81(g3659,g2672,g2361);
and AND2_82(g5351,g5326,g3459);
and AND2_83(g3358,g2842,g1369);
and AND2_84(g5648,g4507,g5545);
and AND2_85(g6934,g6932,g3605);
and AND2_86(g3275,g2172,g2615);
and AND2_87(g3311,g218,g2872);
and AND2_88(g5410,g378,g5274);
and AND2_89(g3615,g2422,g3046);
and AND2_90(g2062,g1499,g1666);
and AND2_91(g3374,g2809,g1969);
and AND2_92(g4600,g4054,g4289);
and AND2_93(g6096,g1193,g5753);
and AND2_94(g1436,g834,g830);
and AND2_95(g5172,g441,g4877);
and AND2_96(g3180,g260,g2506);
and AND2_97(g5618,g5506,g4933);
and AND2_98(g5143,g157,g5099);
and AND2_99(g6913,g6900,g6898);
and AND2_100(g5235,g554,g4980);
and AND2_101(g4580,g706,g4262);
and AND2_102(g2085,g1123,g1567);
and AND2_103(g6266,g1721,g6057);
and AND2_104(g5555,g5014,g5442);
and AND2_105(g2941,g2166,g170);
and AND2_106(g6248,g465,g5894);
and AND2_107(g6342,g6264,g6076);
and AND2_108(g5621,g5508,g4943);
and AND2_109(g3628,g2449,g3070);
and AND2_110(g6255,g1335,g5895);
and AND2_111(g6081,g1177,g5731);
and AND2_112(g3630,g3167,g1756);
and AND2_113(g6692,g6616,g6615);
and AND2_114(g3300,g2232,g2682);
and AND2_115(g6154,g3219,g6015);
and AND2_116(g6354,g5866,g6193);
and AND2_117(g4184,g3934,g2136);
and AND2_118(g5494,g5443,g3455);
and AND2_119(g4384,g414,g3797);
and AND2_120(g4339,g3971,g3289);
and AND2_121(g4838,g4648,g84);
and AND2_122(g3123,g230,g2391);
and AND2_123(g3323,g2253,g2716);
and AND2_124(g4672,g4635,g4631);
and AND2_125(g2733,g2422,g1943);
and AND2_126(g3666,g3128,g2787);
and AND2_127(g6129,g5717,g5975);
and AND2_128(g6329,g3888,g6212);
and AND2_129(g2073,g1088,g1499);
and AND2_130(g5360,g4431,g5160);
and AND2_131(g6828,g6803,g5958);
and AND2_132(g5050,g4285,g4807);
and AND2_133(g3351,g2760,g1931);
and AND2_134(g6830,g6809,g5975);
and AND2_135(g3648,g2722,g2343);
and AND2_136(g3655,g2197,g2768);
and AND3_5(g1706,g766,g719,g729);
and AND2_137(g6068,g5824,g1726);
and AND2_138(g4044,g410,g3388);
and AND3_6(g6468,g2032,g6394,g1609);
and AND2_139(g3172,g2449,g2491);
and AND2_140(g3278,g2175,g2628);
and AND2_141(g3372,g254,g2905);
and AND2_142(g2781,g2544,g1982);
and AND2_143(g3618,g3016,g2712);
and AND2_144(g3667,g2245,g2789);
and AND2_145(g3143,g242,g2437);
and AND2_146(g3282,g131,g2863);
and AND2_147(g6716,g6682,g932);
and AND2_148(g6149,g3200,g5997);
and AND2_149(g3693,g2256,g2830);
and AND2_150(g3134,g230,g2413);
and AND2_151(g3334,g236,g2883);
and AND3_7(g6848,g3741,g328,g6843);
and AND2_152(g5153,g492,g4904);
and AND2_153(g5209,g560,g5025);
and AND2_154(g5353,g5327,g3463);
and AND2_155(g6241,g1325,g5887);
and AND2_156(g1808,g706,g49);
and AND2_157(g3113,g224,g2364);
and AND2_158(g5558,g5018,g5450);
and AND2_159(g6644,g6575,g6230);
and AND2_160(g6152,g3212,g6015);
and AND2_161(g6258,g512,g5899);
and AND2_162(g4178,g3959,g2110);
and AND2_163(g1575,g980,g965);
and AND2_164(g4378,g410,g3792);
and AND2_165(g4831,g4528,g4524);
and AND2_166(g4182,g394,g3904);
and AND2_167(g5492,g5441,g3452);
and AND2_168(g5600,g5502,g4900);
and AND2_169(g6614,g932,g6556);
and AND2_170(g4947,g184,g4741);
and AND2_171(g3360,g2783,g1947);
and AND2_172(g6125,g5708,g5975);
and AND2_173(g1419,g613,g918);
and AND2_174(g3641,g2644,g2333);
and AND2_175(g4873,g4838,g4173);
and AND2_176(g4037,g2896,g3388);
and AND2_177(g3724,g117,g3251);
and AND2_178(g4495,g3913,g4292);
and AND2_179(g3379,g3104,g1988);
and AND2_180(g5175,g5094,g1384);
and AND2_181(g3658,g3118,g2776);
and AND2_182(g6061,g5824,g1711);
and AND2_183(g5500,g5430,g5074);
and AND2_184(g3611,g2370,g3037);
and AND2_185(g2137,g760,g1638);
and AND2_186(g4042,g406,g3388);
and AND2_187(g5184,g453,g4877);
and AND2_188(g4442,g4239,g2882);
and AND2_189(g4164,g3958,g2091);
and AND2_190(g2807,g2568,g2001);
and AND2_191(g5424,g390,g5296);
and AND2_192(g6145,g3187,g6015);
and AND2_193(g2859,g2112,g1649);
and AND3_8(g3997,g1250,g3425,g2849);
and AND2_194(g4054,g3694,g69);
and AND2_195(g6345,g6273,g6083);
and AND2_196(g3132,g2306,g1206);
and AND2_197(g3680,g2245,g2805);
and AND2_198(g6637,g1842,g6549);
and AND2_199(g3353,g3162,g2921);
and AND2_200(g2142,g1793,g1777);
and AND2_201(g2255,g1706,g736);
and AND2_202(g6159,g3177,g6015);
and AND2_203(g2081,g1094,g1546);
and AND2_204(g3558,g338,g3199);
and AND2_205(g5499,g5451,g3462);
and AND2_206(g4389,g449,g3798);
and AND2_207(g4171,g3956,g2104);
and AND2_208(g6315,g3849,g6194);
and AND2_209(g4371,g461,g3789);
and AND3_9(g4429,g923,g4253,g2936);
and AND2_210(g4787,g2937,g4628);
and AND2_211(g6047,g5824,g1692);
and AND2_212(g6874,g6873,g2060);
and AND2_213(g2267,g1716,g791);
and AND3_10(g5444,g4545,g5256,g1574);
and AND2_214(g5269,g557,g5025);
and AND2_215(g1407,g301,g866);
and AND2_216(g4684,g4584,g1341);
and AND2_217(g4791,g3936,g4636);
and AND2_218(g6243,g500,g5890);
and AND2_219(g6935,g6933,g3622);
and AND2_220(g2746,g2473,g1954);
and AND2_221(g4759,g536,g4500);
and AND2_222(g6128,g5590,g5958);
and AND2_223(g5414,g382,g5278);
and AND2_224(g6130,g5720,g5958);
and AND2_225(g5660,g4509,g5549);
and AND2_226(g3375,g260,g2912);
and AND2_227(g4449,g4266,g2887);
and AND2_228(g3651,g3064,g2766);
and AND2_229(g4865,g4776,g1849);
and AND2_230(g2953,g2381,g293);
and AND2_231(g2068,g1541,g1546);
and AND2_232(g3285,g2195,g2653);
and AND2_233(g4833,g4521,g4516);
and AND2_234(g5178,g516,g4993);
and AND2_235(g5679,g74,g5576);
and AND2_236(g5378,g179,g5260);
and AND2_237(g3339,g2734,g1914);
and AND2_238(g1689,g766,g719);
and AND2_239(g5182,g520,g4993);
and AND2_240(g2699,g2397,g1905);
and AND2_241(g2747,g2449,g1957);
and AND2_242(g6090,g1161,g5742);
and AND2_243(g4362,g3996,g3355);
and AND2_244(g3672,g3136,g2800);
and AND2_245(g4052,g418,g3388);
and AND2_246(g3643,g2518,g3086);
and AND2_247(g4452,g3820,g4227);
and AND2_248(g6056,g5824,g1699);
and AND2_249(g1826,g714,g710);
and AND2_250(g6148,g3196,g6015);
and AND2_251(g6348,g5869,g6211);
and AND2_252(g5560,g5044,g5456);
and AND2_253(g3634,g2179,g2744);
and AND2_254(g6155,g2588,g5997);
and AND2_255(g6851,g6846,g2293);
and AND2_256(g3551,g2937,g938);
and AND2_257(g3099,g218,g2350);
and AND2_258(g3304,g2857,g1513);
and AND2_259(g4486,g716,g4195);
and AND2_260(g3499,g357,g2961);
and AND2_261(g4730,g1423,g4565);
and AND2_262(g5632,g4494,g5538);
and AND2_263(g5095,g4794,g951);
and AND2_264(g6260,g1703,g6048);
and AND2_265(g4185,g398,g3906);
and AND2_266(g1609,g760,g754);
and AND2_267(g5495,g5444,g3456);
and AND4_1(g2577,g1743,g1797,g1793,g1138);
and AND2_268(g3613,g2604,g2312);
and AND2_269(g6619,g6515,g6115);
and AND2_270(g6318,g3865,g6212);
and AND4_2(g2026,g1359,g1402,g1398,g901);
and AND2_271(g5164,g437,g4877);
and AND2_272(g5364,g574,g5194);
and AND2_273(g5233,g551,g4980);
and AND2_274(g2821,g1890,g910);
and AND2_275(g3729,g327,g3441);
and AND2_276(g5454,g5256,g4549);
and AND2_277(g5553,g5012,g5440);
and AND2_278(g6321,g3873,g6212);
and AND2_279(g3660,g2568,g3110);
and AND3_11(g6625,g2121,g1595,g6538);
and AND2_280(g4045,g3425,g123);
and AND2_281(g4445,g4235,g1854);
and AND2_282(g6253,g508,g5896);
and AND2_283(g4373,g4001,g3370);
and AND2_284(g5189,g528,g4993);
and AND2_285(g4491,g3554,g4215);
and AND2_286(g6909,g6896,g6894);
and AND2_287(g4169,g3966,g2099);
and AND2_288(g5171,g406,g4950);
and AND2_289(g4369,g3999,g3364);
and AND2_290(g3679,g2245,g2803);
and AND2_291(g4602,g4407,g4293);
and AND2_292(g5371,g152,g5248);
and AND2_293(g3378,g3136,g2932);
and AND2_294(g5429,g398,g5304);
and AND2_295(g4407,g4054,g74);
and AND2_296(g5956,g5783,g5425);
and AND2_297(g4868,g4774,g2891);
and AND2_298(g5675,g64,g5574);
and AND2_299(g3135,g2370,g2416);
and AND2_300(g4459,g4245,g1899);
and AND2_301(g3335,g230,g2884);
and AND2_302(g3831,g2330,g3425);
and AND2_303(g3182,g2473,g2512);
and AND2_304(g3288,g2631,g2634);
and AND2_305(g3382,g3136,g2934);
and AND2_306(g4793,g4277,g4639);
and AND2_307(g4015,g445,g3388);
and AND2_308(g2107,g1583,g1543);
and AND2_309(g6141,g3173,g5997);
and AND2_310(g6341,g6261,g6074);
and AND2_311(g6645,g6576,g6231);
and AND2_312(g3632,g3043,g2743);
and AND2_313(g3437,g837,g2853);
and AND2_314(g3653,g2215,g2767);
and AND2_315(g5201,g4859,g5084);
and AND2_316(g3208,g895,g2551);
and AND2_317(g3302,g212,g2867);
and AND2_318(g6158,g2594,g6015);
and AND2_319(g5449,g4545,g5246);
and AND2_320(g5604,g5059,g5521);
and AND2_321(g5098,g4021,g4837);
and AND2_322(g5498,g5449,g3460);
and AND2_323(g1585,g1017,g1011);
and AND2_324(g6275,g1735,g6070);
and AND2_325(g6311,g3837,g6194);
and AND2_326(g4671,g4645,g4641);
and AND3_12(g4247,g1764,g4007,g1628);
and AND2_327(g3454,g2933,g1660);
and AND2_328(g4826,g4209,g4463);
and AND2_329(g5162,g5088,g2105);
and AND2_330(g5362,g4437,g5174);
and AND2_331(g3296,g3054,g2650);
and AND2_332(g5419,g386,g5292);
and AND2_333(g3725,g118,g3251);
and AND2_334(g2935,g2291,g1788);
and AND2_335(g5452,g5315,g4612);
and AND2_336(g6559,g1612,g6474);
and AND2_337(g5728,g5623,g3889);
and AND2_338(g5486,g386,g5331);
and AND2_339(g5185,g524,g4993);
and AND2_340(g3171,g248,g2488);
and AND2_341(g3371,g260,g2904);
and AND3_13(g6628,g2138,g1612,g6540);
and AND2_342(g4165,g3927,g1352);
and AND2_343(g4048,g414,g3388);
and AND2_344(g4448,g3815,g4225);
and AND2_345(g3281,g2178,g2640);
and AND2_346(g4827,g4520,g4515);
and AND2_347(g4333,g3964,g3284);
and AND3_14(I2566,g749,g743,g736);
and AND2_348(g2166,g1633,g161);
and AND2_349(g3684,g2268,g2817);
and AND2_350(g4396,g422,g3801);
and AND2_351(g3338,g3162,g2914);
and AND2_352(g2056,g1672,g1675);
and AND2_353(g5406,g374,g5270);
and AND2_354(g3309,g2243,g2695);
and AND2_355(g5635,g4498,g5542);
and AND2_356(g5682,g84,g5578);
and AND2_357(g5487,g390,g5331);
and AND2_358(g6123,g5702,g5958);
and AND2_359(g6323,g3877,g6194);
and AND2_360(g3759,g2644,g3498);
and AND2_361(g5226,g672,g5054);
and AND2_362(g6151,g3209,g5997);
and AND2_363(g3449,g128,g2946);
and AND2_364(g6648,g6579,g6234);
and AND2_365(g5173,g512,g4993);
and AND2_366(g5373,g161,g5250);
and AND2_367(g4181,g3939,g1381);
and AND2_368(g2720,g2422,g1919);
and AND2_369(g4685,g4591,g2079);
and AND2_370(g5169,g5093,g1375);
and AND2_371(g5369,g143,g5247);
and AND2_372(g5602,g594,g5515);
and AND4_3(g2834,g1263,g1257,g1270,I4040);
and AND2_373(g3362,g3031,g2740);
and AND2_374(g6343,g6268,g6078);
and AND2_375(g2121,g1632,g754);
and AND2_376(g2670,g2029,g1503);
and AND2_377(g6693,g6618,g6617);
and AND2_378(g1633,g716,g152);
and AND2_379(g6334,g3858,g6212);
and AND2_380(g3728,g326,g3441);
and AND2_381(g6555,g1838,g6469);
and AND2_382(g3730,g328,g3441);
and AND2_383(g2909,g606,g2092);
and AND2_384(g4041,g461,g3388);
and AND2_385(g3425,g2296,g3208);
and AND2_386(g6313,g3841,g6194);
and AND2_387(g5940,g5115,g5794);
and AND2_388(g4673,g4656,g4654);
and AND2_389(g5188,g1043,g4894);
and AND2_390(g6908,g6907,g3886);
and AND2_391(g5216,g563,g5025);
and AND2_392(g6094,g1177,g5753);
and AND2_393(g4168,g3925,g1355);
and AND2_394(g4368,g3998,g3363);
and AND2_395(g5671,g54,g5572);
and AND2_396(g3678,g2256,g2802);
and AND2_397(g5428,g394,g5300);
and AND2_398(g4058,g3424,g1246);
and AND2_399(g3635,g2473,g3079);
and AND2_400(g2860,g710,g2296);
and AND2_401(g3682,g2772,g2430);
and AND2_402(g3305,g2960,g2296);
and AND2_403(g5910,g5816,g5667);
and AND2_404(g3755,g2604,g3481);
and AND2_405(g2659,g1686,g2296);
and AND2_406(g5883,g5824,g3752);
and AND2_407(g3373,g3118,g2927);
and AND2_408(g5217,g4866,g5092);
and AND2_409(g4863,g4777,g2874);
and AND2_410(g3283,g2609,g2622);
and AND2_411(g3602,g2688,g2663);
and AND3_15(I2574,g804,g798,g791);
and AND2_412(g5165,g508,g4993);
and AND2_413(g6777,g6762,g3488);
and AND3_16(g3718,g1743,g3140,g1157);
and AND2_414(g3767,g2706,g3504);
and AND2_415(g4688,g1474,g4568);
and AND2_416(g1784,g858,g889);
and AND2_417(g2853,g836,g2021);
and AND2_418(g6799,g4948,g6782);
and AND2_419(g2794,g2544,g1994);
and AND2_420(g3203,g2497,g2565);
and AND2_421(g6132,g3752,g5880);
and AND2_422(g6238,g528,g5886);
and AND2_423(g6153,g3216,g5997);
and AND2_424(g4183,g3965,g1391);
and AND2_425(g4383,g453,g3796);
and AND2_426(g6558,g1842,g6474);
and AND2_427(g5181,g449,g4877);
and AND2_428(g3689,g3162,g2826);
and AND2_429(g4588,g2419,g4273);
and AND2_430(g5197,g465,g4967);
and AND2_431(g4161,g3931,g2087);
and AND2_432(g4361,g3995,g3354);
and AND2_433(g3671,g2760,g2405);
and AND2_434(g4051,g449,g3388);
and AND2_435(g6092,g1123,g5731);
and AND2_436(g4346,g157,g3773);
and AND2_437(g2323,g471,g1358);
and AND2_438(g5562,g5228,g5457);
and AND2_439(g3910,g3546,g1049);
and AND2_440(g3609,g2706,g2678);
and AND2_441(g6262,g516,g5901);
and AND3_17(g6736,g6712,g754,g5237);
and AND2_442(g3758,g545,g3461);
and AND2_443(g4043,g457,g3388);
and AND2_444(g3365,g254,g2892);
and AND3_18(g5441,g4537,g5251,g1558);
and AND2_445(g5673,g59,g5573);
and AND2_446(g4347,g3986,g3320);
and AND2_447(g3133,g236,g2410);
and AND2_448(g3333,g2264,g2728);
and AND2_449(g3774,g3016,g3510);
and AND2_450(g4697,g4589,g1363);
and AND2_451(g3780,g3043,g3519);
and AND3_19(g6737,g6714,g760,g5237);
and AND2_452(g6077,g5824,g1735);
and AND2_453(g3662,g2544,g3114);
and AND2_454(g6643,g6574,g6229);
and AND2_455(g3290,g2213,g2664);
and AND2_456(g6634,g1595,g6545);
and AND2_457(g3816,g3434,g861);
and AND2_458(g2113,g1576,g1535);
and AND2_459(g6099,g1222,g5753);
and AND2_460(g6304,g5915,g6165);
and AND2_461(g3181,g254,g2509);
and AND2_462(g3381,g3128,g1998);
and AND2_463(g3685,g2256,g2818);
and AND2_464(g3700,g2276,g2837);
and AND2_465(g3421,g622,g2846);
and AND2_466(g5569,g5348,g3772);
and AND2_467(g4460,g4218,g1539);
and AND2_468(g4597,g3694,g4286);
and AND2_469(g6613,g932,g6554);
and AND2_470(g4739,g2850,g4579);
and AND2_471(g6269,g524,g5908);
and AND2_472(g4937,g166,g4732);
and AND2_473(g4668,g4642,g4638);
and AND2_474(g3631,g2631,g2324);
and AND2_475(g2160,g1624,g929);
and AND2_476(g4390,g418,g3799);
and AND2_477(g3301,g218,g2866);
and AND2_478(g4501,g4250,g1671);
and AND2_479(g4156,g3926,g2078);
and AND2_480(g4356,g175,g3779);
and AND2_481(g4942,g175,g4736);
and AND2_482(g5183,g418,g4950);
and AND2_483(g4163,g374,g3892);
and AND2_484(g5023,g3935,g4804);
and AND2_485(g4363,g402,g3786);
and AND2_486(g4032,g441,g3388);
and AND2_487(g4053,g3387,g1415);
and AND2_488(g4453,g4238,g1858);
and AND2_489(g5161,g5095,g4535);
and AND2_490(g3669,g2234,g2790);
and AND2_491(g5361,g4435,g5168);
and AND2_492(g3368,g2822,g2923);
and AND2_493(g6135,g5584,g5958);
and AND2_494(g5665,g361,g5570);
and AND2_495(g6831,g6812,g5975);
and AND2_496(g5451,g5251,g4544);
and AND2_497(g6288,g5615,g6160);
and AND2_498(g4157,g3830,g1533);
and AND2_499(g4357,g3990,g3342);
and AND2_500(g5146,g184,g5099);
and AND2_501(g6916,g6903,g6901);
and AND2_502(g5633,g4496,g5539);
and AND2_503(g3505,g2924,g1749);
and AND2_504(g6749,g6735,g6734);
and AND2_505(g6798,g4946,g6781);
and AND2_506(g5944,g5778,g5403);
and AND2_507(g5240,g293,g4915);
and AND2_508(g5043,g3941,g4805);
and AND3_20(g5443,g4537,g5251,g2307);
and AND2_509(g6302,g5740,g6164);
and AND2_510(g6719,g4518,g6665);
and AND2_511(g2092,g642,g1570);
and AND2_512(g4683,g4585,g2066);
and AND2_513(g5681,g79,g5577);
and AND2_514(g3688,g2783,g2457);
and AND2_515(g4735,g2018,g4577);
and AND2_516(g6265,g520,g5903);
and AND2_517(g4782,g1624,g4623);
and AND2_518(g4661,g4637,g4634);
and AND2_519(g4949,g193,g4753);
and AND2_520(g3326,g2734,g1891);
and AND2_521(g6770,g6754,g3482);
and AND2_522(g3760,g548,g3465);
and AND2_523(g5936,g5113,g5788);
and AND2_524(g4039,g402,g3388);
and AND2_525(g5317,g148,g4869);
and AND2_526(g3383,g3128,g2004);
and AND2_527(g5601,g5052,g5518);
and AND2_528(g3608,g2599,g2308);
and AND2_529(g3924,g3505,g471);
and AND2_530(g4583,g1808,g4267);
and AND2_531(g3161,g2397,g2470);
and AND2_532(g2339,g1603,g197);
and AND2_533(g3361,g3150,g1950);
and AND2_534(g4616,g4231,g3761);
and AND2_535(g3665,g2748,g2378);
and AND2_536(g3127,g224,g2394);
and AND2_537(g3327,g2772,g2906);
and AND2_538(g3146,g2370,g2446);
and AND2_539(g3633,g2497,g3076);
and AND2_540(g5937,g5775,g5392);
and AND2_541(g3103,g212,g2353);
and AND2_542(g3303,g2722,g2890);
and AND2_543(g5668,g49,g5571);
and AND2_544(g6338,g6251,g6067);
and AND2_545(g5190,g426,g4950);
and AND2_546(g5501,g5454,g3478);
and AND2_547(g2551,g715,g1826);
and AND2_548(g5156,g434,g4877);
and AND2_549(g5356,g5265,g1902);
and AND2_550(g4277,g3936,g942);
and AND2_551(g5942,g5117,g5797);
and AND2_552(g4789,g3551,g4632);
and AND2_553(g3316,g2748,g2894);
and AND2_554(g3434,g2850,g857);
and AND2_555(g5954,g5121,g5813);
and AND2_556(g5163,g402,g4950);
and AND2_557(g6098,g1209,g5753);
and AND2_558(g3147,g2419,g59);
and AND2_559(g5363,g4439,g5179);
and AND2_560(g3681,g2234,g2806);
and AND2_561(g5053,g4599,g4808);
and AND2_562(g3697,g2796,g2481);
and AND2_563(g5157,g496,g4904);
and AND2_564(g5357,g398,g5220);
and AND3_21(g4244,g1749,g4004,g1609);
and AND2_565(g4340,g3972,g3291);
and AND2_566(g3936,g3551,g940);
and AND2_567(g3117,g218,g2367);
and AND2_568(g3317,g2722,g2895);
and AND2_569(g4035,g437,g3388);
and AND2_570(g918,g610,g602);
and AND2_571(g6086,g1143,g5742);
and AND2_572(g4214,g1822,g4045);
and AND2_573(g1620,g1056,g1084);
and AND2_574(g3784,g114,g3251);
and AND2_575(g2916,g1030,g2113);
and AND2_576(g3479,g345,g2957);
and AND2_577(g6131,g5593,g5975);
and AND2_578(g3668,g2568,g3124);
and AND2_579(g6331,g3891,g6212);
and AND2_580(g4236,g654,g3907);
and AND2_581(g3294,g139,g2870);
and AND2_582(g5949,g5119,g5805);
and AND2_583(g3190,g260,g2535);
and AND2_584(g6766,g6750,g2986);
and AND2_585(g3156,g242,g2464);
and AND2_586(g3356,g248,g2888);
and AND2_587(g5646,g4502,g5544);
and AND2_588(g2873,g1845,g1861);
and AND2_589(g6748,g6733,g6732);
and AND2_590(g5603,g5504,g4911);
and AND2_591(g5484,g378,g5331);
and AND2_592(g4928,g148,g4723);
and AND2_593(g3704,g2276,g2841);
and AND2_594(g4464,g4272,g1937);
and AND2_595(g4785,g2160,g4625);
and AND2_596(g6091,g1161,g5753);
and AND2_597(g3810,g625,g3421);
and AND2_598(g5952,g5120,g5809);
and AND2_599(g5616,g5505,g4929);
and AND2_600(g6718,g4511,g6661);
and AND2_601(g6767,g6754,g2986);
and AND2_602(g3157,g2422,g2467);
and AND2_603(g3357,g242,g2889);
and AND2_604(g4489,g2166,g4206);
and AND2_605(g2770,g2518,g1972);
and AND2_606(g4471,g4253,g332);
and AND2_607(g5503,g366,g5384);
and AND2_608(g3626,g3031,g2727);
and AND2_609(g4038,g430,g3388);
and AND2_610(g5617,g5061,g5524);
and AND2_611(g3683,g3150,g2813);
and AND2_612(g4836,g4527,g4523);
and AND2_613(g2138,g1639,g809);
and AND2_614(g3661,g2234,g2778);
and AND2_615(g6247,g504,g5893);
and AND2_616(g3627,g2473,g3067);
and AND2_617(g5945,g5118,g5801);
and AND2_618(g2808,g2009,g1581);
and AND2_619(g3292,g2214,g2667);
and AND2_620(g3646,g2179,g2756);
and AND2_621(g2759,g2473,g1966);
and AND2_622(g6910,g6892,g6891);
and AND2_623(g3603,g2370,g3019);
and AND2_624(g3484,g349,g2958);
and AND2_625(g5482,g370,g5331);
and AND2_626(g3702,g2284,g2839);
and AND2_627(g6066,g5824,g1721);
and AND2_628(g5214,g562,g5025);
and AND2_629(g3616,g2397,g3049);
and AND2_630(g6055,g5824,g1696);
and AND2_631(g6133,g5723,g5975);
and AND2_632(g5663,g4513,g5550);
and AND2_633(g6333,g3896,g6212);
and AND2_634(g2419,g1808,g54);
and AND2_635(g3764,g551,g3480);
and AND2_636(g5402,g370,g5266);
and AND2_637(g5236,g269,g4915);
and AND2_638(g4708,g578,g4541);
and AND2_639(g5556,g5015,g5445);
and AND2_640(g4219,g3911,g1655);
and AND2_641(g3277,g2174,g2625);
and AND2_642(g3617,g2609,g2317);
and AND2_643(g6093,g1177,g5742);
and AND2_644(g2897,g1030,g2062);
and AND2_645(g6256,g1696,g6040);
and AND2_646(g4176,g386,g3901);
and AND2_647(g6816,g6784,g3346);
and AND2_648(g4829,g4526,g4522);
and AND2_649(g6263,g1711,g6052);
and AND2_650(g5194,g586,g4874);
and AND2_651(g3709,g2284,g2845);
and AND2_652(g5557,g5016,g5448);
and AND2_653(g3340,g2772,g2915);
and AND2_654(g6631,g1838,g6545);
and AND2_655(g3907,g650,g3522);
and AND2_656(g4177,g3933,g1372);
and AND2_657(g5948,g5779,g5407);
and AND2_658(g4377,g457,g3791);
and AND2_659(g3690,g2276,g2827);
and AND2_660(g5955,g5782,g5420);
and AND2_661(g5350,g5325,g3453);
and AND2_662(g4199,g628,g3810);
and AND2_663(g5438,g5224,g3769);
and AND2_664(g2868,g1316,g1861);
and AND2_665(g3310,g224,g2871);
and AND2_666(g4797,g4593,g4643);
and AND2_667(g5212,g561,g5025);
and AND2_668(g3663,g2215,g2779);
and AND2_669(g2793,g2568,g1991);
and AND2_670(g2015,g616,g1419);
and AND2_671(g4344,g3981,g3306);
and AND2_672(g5229,g545,g4980);
and AND2_673(g6772,g6746,g3312);
and AND2_674(g3762,g2672,g3500);
and AND2_675(g4694,g1481,g4578);
and AND2_676(g3657,g2734,g2357);
and AND2_677(g2721,g2397,g1922);
and AND2_678(g4488,g1633,g4202);
and AND2_679(g4701,g4596,g1378);
and AND2_680(g3928,g3512,g478);
and AND3_22(g6474,g2138,g2036,g6397);
and AND2_681(g3899,g323,g3441);
and AND2_682(g3464,g341,g2956);
and AND2_683(g5620,g5507,g4938);
and AND2_684(g4870,g4779,g1884);
and AND2_685(g3295,g2660,g2647);
and AND2_686(g2671,g2263,g2296);
and AND2_687(g1576,g1101,g1094);
and AND2_688(g3844,g3540,g1665);
and AND3_23(g1716,g821,g774,g784);
and AND2_689(g3089,g212,g2336);
and AND2_690(g3731,g331,g3441);
and AND2_691(g3489,g2607,g1861);
and AND2_692(g5192,g1046,g4894);
and AND2_693(g5485,g382,g5331);
and AND2_694(g5941,g5777,g5399);
and AND2_695(g4230,g3756,g1861);
and AND2_696(g6126,g5711,g5958);
and AND2_697(g6326,g3833,g6194);
and AND2_698(g4033,g426,g3388);
and AND2_699(g3814,g913,g3546);
and AND2_700(g2758,g2497,g1963);
and AND2_701(g3350,g3150,g1928);
and AND2_702(g2861,g2120,g1654);
and AND2_703(g6924,g6920,g6919);
and AND2_704(g5176,g410,g4950);
and AND2_705(g4395,g445,g3800);
and AND2_706(g5376,g170,g5255);
and AND2_707(g5911,g5817,g5670);
and AND2_708(g2846,g619,g2015);
and AND2_709(g6127,g5714,g5975);
and AND2_710(g6327,g3884,g6212);
and AND2_711(g5225,g669,g5054);
and AND2_712(g4342,g3978,g3299);
and AND2_713(g6146,g3192,g5997);
and AND2_714(g6346,g6274,g6087);
and AND2_715(g2018,g1423,g1254);
and AND2_716(g4354,g437,g3777);
and AND4_4(I5352,g3529,g3531,g3535,g3538);
and AND2_717(g5177,g445,g4877);
and AND2_718(g6240,g4205,g5888);
and AND2_719(g3620,g2422,g3060);
and AND2_720(g1027,g598,g567);
and AND2_721(g2685,g2370,g1887);
and AND2_722(g2700,g2370,g1908);
and AND2_723(g2021,g835,g1436);
and AND2_724(g6316,g3855,g6194);
and AND2_725(g5898,g5800,g5647);
and AND2_726(g4401,g426,g3802);
and AND2_727(g1514,g1017,g1011);
and AND2_728(g5900,g5804,g5658);
and AND2_729(g2950,g2156,g1612);
and AND2_730(g4761,g4567,g1674);
and AND2_731(g5245,g297,g4915);
and AND2_732(g1763,g478,g1119);
and AND2_733(g4828,g4510,g4508);
and AND2_734(g3298,g2231,g2679);
and AND2_735(g4830,g4529,g4525);
and AND2_736(g5144,g166,g5099);
and AND2_737(g4592,g3147,g4281);
and AND2_738(g6914,g6895,g6893);
and AND2_739(g2101,g1001,g1543);
and AND2_740(g5488,g394,g5331);
and AND2_741(g4932,g157,g4727);
and AND2_742(g1416,g913,g266);
and AND2_743(g5701,g5683,g3813);
and AND2_744(g6317,g3862,g6194);
and AND2_745(g5215,g4864,g5090);
and AND2_746(g5951,g5780,g5411);
and AND2_747(g4677,g4652,g4646);
and AND2_748(g3176,g2422,g2494);
and AND2_749(g3376,g3104,g1979);
and AND2_750(g3286,g2196,g2656);
and AND2_751(g3765,g554,g3485);
and AND2_752(g4349,g441,g3775);
and AND2_753(g6060,g5824,g1703);
and AND4_5(g1595,g729,g719,g766,I2566);
and AND4_6(I5359,g3518,g3521,g3526,g3530);
and AND2_754(g3610,g2397,g3034);
and AND3_24(g6739,g6715,g815,g5242);
and AND4_7(g1612,g784,g774,g821,I2574);
and AND2_755(g3324,g230,g2875);
and AND2_756(g6079,g1236,g5753);
and AND2_757(g5122,g193,g4662);
and AND2_758(g3377,g3118,g2931);
and AND2_759(g4352,g3988,g3331);
and AND2_760(g4867,g4811,g3872);
and AND2_761(g6156,g2591,g6015);
and AND2_762(g3287,g135,g2865);
and AND2_763(g5096,g4794,g4647);
and AND2_764(g4186,g3973,g1395);
and AND2_765(g5496,g5446,g3457);
and AND2_766(g6250,g1692,g6036);
and AND2_767(g4170,g382,g3900);
and AND3_25(g4280,g2138,g1764,g4007);
and AND2_768(g3144,g236,g2440);
and AND2_769(g3344,g242,g2885);
and AND2_770(g5142,g148,g5099);
and AND2_771(g3819,g964,g3437);
and AND2_772(g6912,g6899,g6897);
and AND2_773(g3694,g3147,g64);
and AND2_774(g6157,g3158,g5997);
and AND2_775(g5481,g366,g5331);
and AND2_776(g3701,g2268,g2838);
and AND2_777(g5497,g5447,g3458);
and AND2_778(g5154,g500,g4993);
and AND2_779(g5354,g5249,g2903);
and AND2_780(g4461,g4241,g2919);
and AND2_781(g4756,g3816,g4587);
and AND2_782(g4046,I5351,I5352);
and AND2_783(g5218,g564,g5025);
and AND2_784(g3650,g2660,g2347);
and AND2_785(g4345,g3982,g3308);
and AND2_786(g3336,g2760,g1911);
and AND2_787(g3768,g3448,g1528);
and AND2_788(g4159,g370,g3890);
and AND2_789(g4359,g434,g3782);
and AND2_790(g3806,g3384,g2024);
and AND2_791(g4416,g3905,g1481);
and AND2_792(g3887,g3276,g1861);
and AND2_793(g3122,g2435,g1394);
and AND2_794(g2732,g2449,g1940);
and AND2_795(g4047,g453,g3388);
and AND2_796(g6646,g6577,g6232);
and AND3_26(g3433,g1359,g2831,g905);
and AND2_797(g5953,g5781,g5415);
and AND2_798(g6084,g1123,g5753);
and AND2_799(g6603,g6581,g6236);
and AND2_800(g4874,g582,g4708);
and AND2_801(g5677,g69,g5575);
and AND2_802(g3195,g2473,g2541);
and AND2_803(g3337,g2796,g2913);
and AND3_27(I4040,g1279,g2025,g1267);
and AND2_804(g5149,g4910,g1480);
and AND2_805(g5349,g5324,g3451);
and AND2_806(g5198,g558,g5025);
and AND2_807(g5398,g366,g5261);
and AND2_808(g1570,g634,g1027);
and AND2_809(g6647,g6578,g6233);
and AND2_810(g1691,g821,g774);
and AND2_811(g3692,g2268,g2829);
and AND2_812(g3726,g119,g3251);
and AND2_813(g3154,g2039,g1410);
and AND2_814(g4800,g4648,g4296);
and AND2_815(g5152,g430,g4950);
and AND2_816(g6320,g3869,g6194);
and AND2_817(g5211,g4860,g5086);
and AND2_818(g5186,g422,g4950);
and AND2_819(g5599,g5049,g5512);
and AND2_820(g4490,g2941,g4210);
and AND2_821(g3293,g212,g2864);
and AND2_822(g6771,g6758,g3483);
and AND2_823(g3329,g2748,g2907);
and AND2_824(g5170,g5091,g2111);
and AND2_825(g4456,g3829,g4229);
and AND2_826(g6299,g5530,g6163);
and AND2_827(g4348,g3987,g3322);
and AND2_828(g3727,g122,g3251);
and AND2_829(g2937,g2160,g931);
and AND2_830(g4355,g430,g3778);
and AND2_831(g5939,g5776,g5395);
and AND3_28(g2294,g1716,g791,g798);
and AND2_832(g4698,g4586,g2106);
and AND2_833(g5483,g374,g5331);
and AND2_834(g3703,g2284,g2840);
and AND3_29(g6738,g6713,g809,g5242);
and AND2_835(g2156,g815,g1642);
and AND2_836(g6244,g4759,g5891);
and AND2_837(g2356,g1603,g269);
and AND2_838(g6140,g5587,g5975);
and AND2_839(g3953,g3554,g188);
and AND2_840(g6340,g6257,g6069);
and AND2_841(g5187,g457,g4877);
and AND2_842(g1628,g815,g809);
and AND2_843(g4167,g378,g3898);
and AND2_844(g6082,g1123,g5742);
and AND2_845(g4367,g193,g3788);
and AND2_846(g4872,g4760,g1549);
and AND2_847(g4057,g422,g3388);
and AND2_848(g5904,g5812,g5664);
and AND2_849(g5200,g559,g5025);
and AND2_850(g4457,g4261,g2902);
and AND2_851(g5446,g4537,g5241);
and AND2_852(g3349,g2783,g1925);
and AND2_853(g2053,g1094,g1675);
and AND2_854(g5145,g175,g5099);
and AND2_855(g6915,g6906,g6905);
and AND2_856(g4834,g4534,g4531);
and AND2_857(g4686,g4590,g1348);
and AND2_858(g5191,g461,g4877);
and AND2_859(g3699,g2276,g2836);
and AND2_860(g4598,g1978,g4253);
and AND2_861(g5637,g4499,g5543);
and AND2_862(g5159,g536,g4967);
and AND2_863(g5359,g4428,g5155);
and AND2_864(g4253,g1861,g3819);
and AND2_865(g3644,g2197,g2755);
and AND2_866(g3319,g2688,g2675);
and AND2_867(g3352,g2796,g2920);
and AND2_868(g5047,g3954,g4806);
and AND3_30(g5447,g4545,g5256,g2311);
and AND2_869(g4687,g4493,g1542);
and AND2_870(g3186,g2449,g2515);
and AND2_871(g3170,g254,g2485);
and AND2_872(g3614,g2998,g2691);
and AND2_873(g3325,g224,g2876);
and AND2_874(g4341,g3977,g3297);
and AND2_875(g2782,g2518,g1985);
and AND2_876(g6295,g5379,g6162);
and AND2_877(g3280,g2177,g2637);
and AND2_878(g5017,g4784,g1679);
and AND2_879(g4691,g4581,g2098);
and AND2_880(g5935,g5112,g5784);
and AND2_881(g2949,g830,g1861);
and AND4_8(I5351,g3511,g3517,g3520,g3525);
and AND2_882(g5234,g197,g4915);
and AND2_883(g3636,g2701,g2327);
and AND3_31(g2292,g1706,g736,g743);
and AND2_884(g6089,g1143,g5731);
and AND2_885(g6731,g6717,g4427);
and AND2_886(g6557,g1595,g6469);
and AND2_887(g4358,g3991,g3343);
and AND2_888(g2084,g1577,g1563);
and AND2_889(g2850,g2018,g1255);
and AND2_890(g5213,g4862,g5087);
and AND2_891(g6254,g532,g5897);
and AND2_892(g6150,g3204,g6015);
and AND2_893(g5902,g5808,g5661);
and AND2_894(g3145,g2397,g2443);
and AND2_895(g3345,g236,g2886);
and AND2_896(g6773,g6762,g2986);
and AND2_897(g3763,g3064,g3501);
and AND2_898(g3191,g2497,g2538);
and AND2_899(g4180,g3929,g2119);
and AND2_900(g5166,g541,g4967);
and AND2_901(g3637,g2822,g2752);
and AND2_902(g4832,g4517,g4512);
and AND2_903(g6769,g6758,g2986);
and AND2_904(g3307,g2242,g2692);
and AND2_905(g3359,g2822,g2922);
and AND2_906(g4794,g4593,g949);
and AND2_907(g3757,g2619,g3487);
and AND2_908(g3522,g646,g2909);
and AND2_909(g3315,g2701,g1875);
and AND2_910(g3642,g3054,g2754);
and AND2_911(g3654,g2518,g3100);
and AND2_912(g5619,g5064,g5527);
and AND2_913(g5167,g5011,g1556);
or OR2_0(g3880,g3658,g3665);
or OR2_1(g4440,g4371,g4038);
or OR2_2(g3978,g3655,g3117);
or OR2_3(g6788,g3760,g6767);
or OR2_4(g3935,g3464,g2868);
or OR2_5(g3982,g3663,g3127);
or OR4_0(I8376,g6315,g6126,g6129,g6146);
or OR2_6(g5625,g5495,g3281);
or OR2_7(g6298,g6255,g6093);
or OR3_0(g6485,I8393,I8394,I8395);
or OR2_8(g4655,g4368,g3660);
or OR2_9(g6252,g5905,g2381);
or OR2_10(g6176,g6068,g6033);
or OR4_1(I8377,g6150,g6324,g5180,g5181);
or OR2_11(g6286,g6238,g6079);
or OR2_12(g3851,g3681,g3146);
or OR2_13(g3964,g3634,g3089);
or OR2_14(g5659,g5551,g5398);
or OR2_15(g2928,g2100,g1582);
or OR2_16(g6287,g6241,g6082);
or OR2_17(g3989,g3679,g3144);
or OR2_18(g5374,g5215,g4947);
or OR2_19(g3971,g3644,g3099);
or OR2_20(g6781,g6718,g6748);
or OR2_21(g3598,g2808,g2821);
or OR2_22(g4641,g4347,g3627);
or OR2_23(g4450,g4389,g4047);
or OR2_24(g3740,g3335,g2747);
or OR4_2(I8136,g6015,g6212,g4950,g4877);
or OR2_25(g5628,g5498,g3292);
or OR2_26(g5630,g5501,g3309);
or OR2_27(g6114,g5904,g5604);
or OR2_28(g5323,g5098,g4802);
or OR2_29(g5666,g5555,g5406);
or OR4_3(I8137,g4894,g4904,g4993,g4967);
or OR3_1(I8395,g5182,g5200,g6280);
or OR2_30(g3879,g3704,g3195);
or OR4_4(I9057,g6320,g6828,g6830,g6153);
or OR2_31(g4092,g3311,g2721);
or OR4_5(I8081,g4894,g4904,g4993,g4967);
or OR2_32(g4864,g4744,g4490);
or OR3_2(g6845,I9064,I9065,I9066);
or OR2_33(g5372,g5213,g4942);
or OR2_34(g5693,g5632,g5481);
or OR2_35(g5804,g5371,g5603);
or OR2_36(g6142,g5909,g3806);
or OR2_37(I8129,g4915,g5025);
or OR4_6(g6481,I8367,I8368,I8369,I8370);
or OR2_38(g4651,g4357,g3643);
or OR2_39(g4285,g3490,g3887);
or OR2_40(g4500,g4243,g2010);
or OR3_3(g5202,g4904,g4914,g4894);
or OR2_41(g3750,g3372,g2794);
or OR2_42(g6267,g2953,g5884);
or OR2_43(g4231,g3997,g4000);
or OR2_44(g6676,g6631,g6555);
or OR2_45(g6293,g6244,g6085);
or OR2_46(g4205,g3843,g541);
or OR2_47(g4634,g4341,g3615);
or OR4_7(I8349,I8345,I8346,I8347,I8348);
or OR2_48(g6703,g6692,g4831);
or OR2_49(g3884,g3666,g3671);
or OR2_50(g4444,g4378,g4042);
or OR2_51(g4862,g4739,g4489);
or OR4_8(I8119,g5202,g4993,g4967,g4980);
or OR2_52(g3988,g3678,g3143);
or OR2_53(g5674,g5558,g5419);
or OR2_54(g6747,g6614,g6731);
or OR2_55(g6855,g6851,g2085);
or OR2_56(I8211,g4915,g5025);
or OR4_9(I8386,g6152,g6327,g5183,g5177);
or OR2_57(g5680,g5562,g5429);
or OR2_58(g4946,g4830,g4833);
or OR2_59(I8370,g5214,g6358);
or OR2_60(g4436,g4359,g4035);
or OR3_4(I8387,g5178,g5209,g6281);
or OR2_61(g6274,g5682,g5956);
or OR2_62(g6426,g6288,g6119);
or OR2_63(g6170,g6061,g6014);
or OR2_64(g3996,g3691,g3171);
or OR4_10(I8345,g6326,g6135,g6140,g6157);
or OR2_65(g5623,g5503,g5357);
or OR3_5(g6483,I8385,I8386,I8387);
or OR2_66(g4653,g4361,g3652);
or OR2_67(g3878,g3703,g3191);
or OR2_68(g6790,g3765,g6773);
or OR4_11(I8359,g5232,g5236,g5216,g5226);
or OR2_69(g4752,g4452,g4155);
or OR2_70(g6461,g6353,g6351);
or OR2_71(g3981,g3661,g3123);
or OR2_72(g5024,g4793,g4600);
or OR2_73(g4233,g3912,g471);
or OR2_74(g4454,g4395,g4051);
or OR2_75(g5672,g5557,g5414);
or OR2_76(g5077,g1612,g4694);
or OR2_77(g5231,g5048,g672);
or OR2_78(g6307,g6262,g6096);
or OR2_79(g3744,g3345,g2759);
or OR2_80(g6251,g5668,g5939);
or OR2_81(g6447,g6340,g5938);
or OR4_12(I8128,g5202,g4993,g4967,g4980);
or OR2_82(g3864,g3693,g3176);
or OR2_83(g5044,g4797,g4602);
or OR2_84(g4745,g4468,g4569);
or OR2_85(g6272,g5679,g5953);
or OR2_86(g5014,g4785,g4583);
or OR2_87(g3871,g3701,g3186);
or OR4_13(I7970,g6015,g6212,g4950,g4877);
or OR4_14(I8348,g5229,g5234,g5218,g5225);
or OR2_88(g6554,g6337,g6466);
or OR4_15(I7987,g6194,g5958,g5975,g5997);
or OR2_89(g5916,g5728,g3781);
or OR4_16(I8118,g6015,g6212,g4950,g4877);
or OR4_17(I8367,g6313,g6124,g6127,g6144);
or OR2_90(g6456,g6346,g5954);
or OR4_18(I8393,g6317,g6130,g6133,g6151);
or OR2_91(g4086,g3310,g2720);
or OR2_92(g1589,g1059,g1045);
or OR2_93(g6118,g5911,g5619);
or OR2_94(g6167,g6056,g6039);
or OR2_95(g3862,g3632,g3641);
or OR2_96(g6457,g6352,g6347);
or OR2_97(g4635,g4342,g3616);
or OR2_98(g6549,g6473,g4247);
or OR2_99(g6686,g6259,g6645);
or OR2_100(g5532,g5350,g3278);
or OR4_19(g6670,g6557,g6634,g4410,g2948);
or OR2_101(g5012,g4782,g4580);
or OR2_102(g4059,g3466,g3425);
or OR2_103(g5281,g5074,g5124);
or OR4_20(I8358,g5192,g5153,g5158,g5197);
or OR2_104(g6687,g6260,g6646);
or OR2_105(g3749,g3371,g2793);
or OR2_106(g5808,g5373,g5616);
or OR2_107(g6691,g6275,g6603);
or OR2_108(g3873,g3649,g3657);
or OR2_109(g3869,g3642,g3650);
or OR2_110(g6659,g6634,g6631);
or OR2_111(g4430,g4349,g4015);
or OR2_112(g6239,g2339,g6073);
or OR2_113(g6545,g6468,g4244);
or OR2_114(g4638,g4345,g3620);
or OR2_115(g6794,g6777,g3333);
or OR2_116(g6931,g6741,g6929);
or OR2_117(g3990,g3684,g3155);
or OR2_118(g5385,g3992,g5318);
or OR2_119(g3888,g3672,g3682);
or OR2_120(g5470,g5359,g5142);
or OR2_121(g6300,g6253,g6091);
or OR2_122(g4455,g4396,g4052);
or OR3_6(g6750,g6670,g6625,g6736);
or OR2_123(g5678,g5560,g5428);
or OR2_124(g3745,g3356,g2770);
or OR2_125(g6440,g6336,g5935);
or OR2_126(g3865,g3637,g3648);
or OR2_127(g3833,g3602,g3608);
or OR2_128(g4021,g3558,g2949);
or OR2_129(g3896,g3689,g3697);
or OR2_130(g5535,g5353,g3300);
or OR2_131(g5015,g4787,g4588);
or OR2_132(g4631,g4340,g3611);
or OR2_133(g5246,g5077,g2080);
or OR2_134(g6792,g6770,g3321);
or OR4_21(I7980,g5202,g4993,g4967,g4980);
or OR4_22(I8360,I8356,I8357,I8358,I8359);
or OR2_135(g4441,g4372,g4039);
or OR2_136(g6113,g5902,g5601);
or OR3_7(g5388,g5318,g1589,g3491);
or OR2_137(I8379,g5212,g6357);
or OR2_138(g5430,g5161,g4873);
or OR2_139(g4458,g4401,g4057);
or OR2_140(g3748,g3366,g2782);
or OR2_141(g6264,g5675,g5948);
or OR2_142(g4074,g3301,g2699);
or OR2_143(g6450,g6341,g5940);
or OR2_144(g4080,g3302,g2700);
or OR2_145(g5066,g4668,g4672);
or OR2_146(g6179,g6077,g6051);
or OR4_23(I8209,g6015,g6212,g4950,g4877);
or OR2_147(g6289,g6240,g6081);
or OR2_148(g6658,g6132,g6620);
or OR2_149(g6271,g2955,g5885);
or OR2_150(g5662,g5553,g5402);
or OR2_151(g5018,g4791,g4597);
or OR2_152(I7972,g4915,g5025);
or OR3_8(g5467,g3868,g5318,g3992);
or OR2_153(g5816,g5378,g5620);
or OR2_154(g5700,g5663,g5488);
or OR2_155(g4451,g4390,g4048);
or OR2_156(g6864,g6852,g2089);
or OR2_157(g5817,g5380,g5621);
or OR2_158(g3883,g3709,g3203);
or OR2_159(g5605,g3575,g5500);
or OR3_9(I9059,g5185,g5198,g6279);
or OR2_160(g4443,g4377,g4041);
or OR2_161(g4434,g4355,g4033);
or OR2_162(g5669,g5556,g5410);
or OR2_163(g5368,g5201,g4932);
or OR4_24(I7979,g6015,g6212,g4950,g4877);
or OR2_164(g5531,g5349,g3275);
or OR2_165(g5458,g3466,g5311);
or OR2_166(g6795,g4867,g6772);
or OR2_167(g4936,g4827,g4828);
or OR2_168(g5074,g4792,g4598);
or OR2_169(g5474,g5363,g5146);
or OR2_170(g6926,g6798,g6923);
or OR3_10(g6754,g6676,g6625,g6737);
or OR2_171(g6273,g5681,g5955);
or OR2_172(g6444,g6338,g5936);
or OR4_25(I8378,g5173,g5166,g5235,g5245);
or OR4_26(I8135,g6194,g5958,g5975,g5997);
or OR3_11(g5326,g5069,g4410,g3012);
or OR3_12(I9066,g5189,g5269,g6400);
or OR2_173(g6927,g6799,g6924);
or OR2_174(g3751,g3375,g2807);
or OR2_175(g6660,g6640,g6637);
or OR2_176(g6679,g6637,g6558);
or OR4_27(I8208,g6194,g5958,g5975,g5997);
or OR2_177(g6182,g6047,g6034);
or OR3_13(g5327,g5077,g4416,g3028);
or OR2_178(g3743,g3344,g2758);
or OR2_179(g3856,g3686,g3157);
or OR2_180(g5303,g5053,g4768);
or OR2_181(g5696,g5637,g5484);
or OR2_182(g3992,g1555,g3559);
or OR2_183(g5472,g5361,g5144);
or OR2_184(g3863,g3692,g3172);
or OR2_185(g6437,g6302,g6121);
or OR2_186(g6917,g6909,g6910);
or OR2_187(g3857,g3687,g3161);
or OR2_188(g5533,g5351,g3290);
or OR2_189(g5697,g5646,g5485);
or OR2_190(g5013,g4826,g4621);
or OR2_191(g4627,g4333,g3603);
or OR2_192(g6454,g6344,g5949);
or OR2_193(g6296,g6247,g6088);
or OR2_194(g4646,g4353,g3635);
or OR4_28(I8138,g4980,g4915,g5025,g5054);
or OR2_195(g6189,g6060,g6035);
or OR2_196(g3977,g3653,g3113);
or OR4_29(I9058,g6156,g6331,g5190,g5164);
or OR2_197(g6787,g3758,g6766);
or OR2_198(g5060,g3491,g4819);
or OR2_199(g6297,g6248,g6089);
or OR2_200(g3999,g3699,g3181);
or OR2_201(g6684,g6250,g6643);
or OR4_30(I7978,g6194,g5958,g5975,g5997);
or OR2_202(g6109,g5900,g5599);
or OR2_203(g6791,g6768,g3307);
or OR2_204(g6309,g6265,g6098);
or OR2_205(g3732,g3324,g2732);
or OR2_206(g3533,g3154,g3166);
or OR4_31(I8385,g6316,g6128,g6131,g6149);
or OR2_207(g6268,g5677,g5951);
or OR2_208(g3820,g3287,g2671);
or OR2_209(g6452,g6342,g5942);
or OR2_210(g5626,g5496,g3285);
or OR2_211(g4656,g4369,g3662);
or OR2_212(g6185,g6055,g5995);
or OR2_213(g3739,g3334,g2746);
or OR4_32(I7989,g5202,g4993,g4967,g4980);
or OR2_214(g3995,g3690,g3170);
or OR4_33(I8369,g5165,g5159,g5233,g5240);
or OR4_34(I7971,g5202,g4993,g4967,g4980);
or OR2_215(g5627,g5497,g3286);
or OR3_14(g6682,g6478,g6624,g6623);
or OR2_216(g3942,g3215,g3575);
or OR2_217(g5583,g5569,g4020);
or OR2_218(g6173,g6066,g6043);
or OR2_219(g3954,g3484,g3489);
or OR2_220(g6920,g6915,g6916);
or OR2_221(g6261,g5673,g5944);
or OR2_222(g6793,g6771,g3323);
or OR2_223(g4948,g4834,g4836);
or OR2_224(g6246,g5665,g5937);
or OR2_225(g5224,g5123,g3630);
or OR2_226(g5277,g5023,g4763);
or OR2_227(g4438,g4363,g4037);
or OR2_228(g4773,g4495,g4220);
or OR2_229(g6689,g6266,g6648);
or OR2_230(g3998,g3698,g3180);
or OR4_35(I8774,g6655,g6653,g6651,g6649);
or OR2_231(g3850,g3680,g3145);
or OR2_232(g6108,g5898,g5598);
or OR3_15(g6758,g6673,g6628,g6738);
or OR2_233(g2896,g2323,g1763);
or OR2_234(g6455,g6345,g5952);
or OR2_235(g3986,g3667,g3133);
or OR2_236(g6846,g5860,g6834);
or OR2_237(g3503,g3122,g3132);
or OR4_36(I7969,g6194,g5958,g5975,g5997);
or OR2_238(g4941,g4829,g4832);
or OR2_239(g6290,g6245,g6086);
or OR2_240(g3987,g3669,g3134);
or OR2_241(g6847,g5861,g6837);
or OR2_242(g6685,g6256,g6644);
or OR2_243(g5295,g5047,g4766);
or OR2_244(g4473,g3575,g4253);
or OR2_245(g3991,g3685,g3156);
or OR4_37(I7988,g6015,g6212,g4950,g4877);
or OR2_246(g5471,g5360,g5143);
or OR4_38(I8368,g6148,g6321,g5176,g5184);
or OR2_247(g6257,g5671,g5941);
or OR2_248(g6301,g6254,g6092);
or OR4_39(g6673,g6559,g6640,g4416,g2950);
or OR4_40(I8080,g6015,g6212,g4950,g4877);
or OR2_249(g6669,g6613,g4679);
or OR2_250(g3877,g3651,g3659);
or OR4_41(I8126,g6194,g5958,g5975,g5997);
or OR2_251(g5062,g4661,g4666);
or OR2_252(g6480,I8360,g6359);
or OR4_42(I8779,g6605,g6656,g6654,g6652);
or OR2_253(g6688,g6263,g6647);
or OR2_254(g5085,g4694,g4280);
or OR2_255(I7981,g4915,g5025);
or OR4_43(I8127,g6015,g6212,g4950,g4877);
or OR2_256(g4433,g4354,g4032);
or OR4_44(I8346,g6159,g6334,g5163,g5191);
or OR2_257(g5812,g5376,g5618);
or OR2_258(g4859,g4730,g4486);
or OR2_259(g6665,I8778,I8779);
or OR2_260(g5473,g5362,g5145);
or OR4_45(I8347,g5188,g5157,g5154,g5193);
or OR2_261(g6303,g6258,g6094);
or OR2_262(g5069,g1595,g4688);
or OR4_46(I9064,g6323,g6829,g6831,g6155);
or OR2_263(g4497,g4166,g3784);
or OR4_47(I8210,g5202,g4993,g4967,g4980);
or OR2_264(g5377,g5217,g4949);
or OR2_265(g3837,g3609,g3613);
or OR2_266(g6116,g5910,g5617);
or OR4_48(I8117,g6194,g5958,g5975,g5997);
or OR2_267(g4001,g3702,g3190);
or OR2_268(g3842,g3670,g3135);
or OR2_269(g5291,g5043,g4764);
or OR2_270(g3941,g3479,g2873);
or OR2_271(g5694,g5633,g5482);
or OR2_272(g6936,g5438,g6935);
or OR2_273(g4068,g3293,g2685);
or OR4_49(I8079,g6194,g5958,g5975,g5997);
or OR2_274(g4468,g4214,g3831);
or OR2_275(g4866,g4756,g4491);
or OR2_276(g3829,g3294,g3305);
or OR4_50(I8356,g6311,g6123,g6125,g6141);
or OR2_277(g3733,g3325,g2733);
or OR2_278(g6937,g4616,g6934);
or OR2_279(g6479,I8349,g6335);
or OR2_280(g6294,g6249,g6090);
or OR2_281(g5065,g4667,g4671);
or OR2_282(g5228,g5096,g4800);
or OR4_51(I8357,g6145,g6318,g5171,g5187);
or OR2_283(g3849,g3618,g3625);
or OR2_284(g6704,g6660,g492);
or OR2_285(g4599,g3499,g4230);
or OR2_286(g6453,g6343,g5945);
or OR2_287(g4544,g4410,g2995);
or OR4_52(I8778,g6612,g6611,g6609,g6607);
or OR2_288(g2924,g2095,g1573);
or OR2_289(g4427,g4373,g3668);
or OR2_290(g4446,g4383,g4043);
or OR2_291(g3870,g3700,g3182);
or OR3_16(g6683,g6465,g6622,g6621);
or OR2_292(g5676,g5559,g5424);
or OR2_293(g4637,g4344,g3619);
or OR2_294(g3972,g3646,g3103);
or OR2_295(g6782,g6719,g6749);
or OR2_296(g6661,I8773,I8774);
or OR2_297(g4757,g4456,g4158);
or OR2_298(g6292,g6243,g6084);
or OR2_299(g4811,g4429,g4432);
or OR2_300(g4642,g4348,g3628);
or OR2_301(g4447,g4384,g4044);
or OR2_302(g5624,g5494,g3280);
or OR2_303(g5068,g4673,g4677);
or OR2_304(g4654,g4362,g3654);
or OR2_305(g3891,g3683,g3688);
or OR2_306(g3913,g3449,g2860);
or OR2_307(I7990,g4915,g5025);
or OR2_308(g6702,g6659,g496);
or OR2_309(g6919,g6912,g6914);
or OR2_310(I8120,g4915,g5025);
or OR2_311(g4243,g4053,g4058);
or OR2_312(g5699,g5660,g5487);
or OR2_313(g5241,g5069,g2067);
or OR2_314(g4234,g3921,g478);
or OR2_315(g3815,g3282,g2659);
or OR2_316(g5386,g5227,g669);
or OR2_317(g6789,g3764,g6769);
or OR4_53(I8082,g4980,g4915,g5025,g5054);
or OR2_318(g5370,g5211,g4937);
or OR2_319(g3828,g3304,g1351);
or OR4_54(I9065,g6158,g6333,g5152,g5156);
or OR2_320(g3746,g3357,g2771);
or OR2_321(g5083,g4688,g4271);
or OR2_322(g6907,g6874,g3358);
or OR2_323(g5622,g5492,g3277);
or OR2_324(g6690,g6270,g6650);
or OR4_55(g6482,I8376,I8377,I8378,I8379);
or OR2_325(g4652,g4358,g3645);
or OR2_326(g4549,g4416,g3013);
or OR2_327(g3747,g3365,g2781);
or OR2_328(g3855,g3626,g3631);
or OR2_329(g5695,g5635,g5483);
or OR2_330(g6110,g5883,g5996);
or OR2_331(g6310,g6269,g6099);
or OR2_332(g5016,g4789,g4592);
or OR3_17(g6762,g6679,g6628,g6739);
or OR2_333(g4740,g4448,g4154);
or OR4_56(I8394,g6154,g6329,g5186,g5172);
or OR2_334(g6556,g6339,g6467);
or OR2_335(g6930,g6740,g6928);
or OR2_336(g3599,g2935,g1637);
or OR2_337(g3821,g2951,g3466);
or OR2_338(g4860,g4735,g4488);
or OR2_339(g6237,g5912,g2381);
or OR2_340(g4645,g4352,g3633);
or OR3_18(g6844,I9057,I9058,I9059);
or OR4_57(I8773,g6610,g6608,g6606,g6604);
or OR2_341(g5629,g5499,g3298);
or OR2_342(g4607,g4232,g3899);
or OR2_343(g6705,g6693,g4835);
or OR2_344(g5800,g5369,g5600);
or OR2_345(g6242,g2356,g6075);
or OR2_346(g3841,g3614,g3617);
or OR2_347(g6918,g6911,g6913);
or OR2_348(g5348,g5317,g5122);
or OR2_349(g3858,g3629,g3636);
or OR2_350(g5698,g5648,g5486);
or OR2_351(g4630,g4339,g3610);
or OR2_352(g6921,g6908,g6816);
or OR2_353(g5367,g5199,g4928);
nand NAND3_0(g1777,g1060,g102,g89);
nand NAND2_0(I7217,g152,I7216);
nand NAND2_1(I7571,g5678,I7569);
nand NAND4_0(g5686,g5546,g1017,g1551,g2916);
nand NAND2_2(I2073,g15,I2072);
nand NAND2_3(I2796,g804,I2795);
nand NAND2_4(g948,I2014,I2015);
nand NAND2_5(I4205,g743,I4203);
nand NAND2_6(I3875,g285,I3874);
nand NAND3_1(g3330,g1815,g1797,g3109);
nand NAND2_7(g4151,I5536,I5537);
nand NAND3_2(g2435,g1138,g1777,g1157);
nand NAND2_8(I5658,g3983,I5657);
nand NAND2_9(g1558,I2527,I2528);
nand NAND2_10(I4444,g2092,g606);
nand NAND2_11(I5271,g3710,I5269);
nand NAND2_12(I2898,g1027,I2897);
nand NAND2_13(I2797,g798,I2795);
nand NAND2_14(I2245,g567,I2244);
nand NAND2_15(I3988,g291,g2544);
nand NAND2_16(g1574,I2543,I2544);
nand NAND4_1(g3529,g3200,g2215,g2976,g2968);
nand NAND2_17(I1963,g242,I1961);
nand NAND2_18(I5209,g3271,I5207);
nand NAND2_19(I7562,g74,g5676);
nand NAND2_20(g5506,I7231,I7232);
nand NAND2_21(g5111,I6744,I6745);
nand NAND2_22(I4182,g2292,g749);
nand NAND2_23(I6186,g4301,I6185);
nand NAND2_24(I7441,g594,I7439);
nand NAND2_25(I6026,g4223,g4221);
nand NAND2_26(I2768,g743,I2766);
nand NAND2_27(I3933,g288,g2473);
nand NAND3_3(g5853,g5638,g2053,g1076);
nand NAND2_28(g2731,I3894,I3895);
nand NAND2_29(g5507,I7238,I7239);
nand NAND2_30(g2966,I4160,I4161);
nand NAND2_31(I2934,g1436,I2933);
nand NAND2_32(I3179,g736,I3177);
nand NAND2_33(I6187,g3955,I6185);
nand NAND2_34(I6027,g4223,I6026);
nand NAND3_4(g2009,g901,g1387,g905);
nand NAND2_35(I4233,g2267,g798);
nand NAND2_36(g2769,I3953,I3954);
nand NAND2_37(g1044,I2081,I2082);
nand NAND4_2(g4674,g4550,g1514,g2107,g2897);
nand NAND2_38(I7569,g79,g5678);
nand NAND2_39(I6391,g4504,I6390);
nand NAND4_3(g3525,g3192,g3002,g2197,g2179);
nand NAND4_4(g4680,g4550,g1514,g1006,g2897);
nand NAND2_40(I2081,g25,I2080);
nand NAND2_41(I8195,g471,I8194);
nand NAND2_42(g1534,I2498,I2499);
nand NAND2_43(I2497,g1042,g1036);
nand NAND2_44(g939,I1987,I1988);
nand NAND2_45(I5269,g3705,g3710);
nand NAND3_5(g3985,g1138,g3718,g2142);
nand NAND2_46(g1036,I2061,I2062);
nand NAND2_47(I2676,g131,I2674);
nand NAND2_48(g1749,I2767,I2768);
nand NAND2_49(g6097,g2954,g5857);
nand NAND3_6(g6783,g6747,g5068,g5066);
nand NAND2_50(g5776,I7528,I7529);
nand NAND2_51(I7434,g5554,I7432);
nand NAND2_52(g1042,I2073,I2074);
nand NAND2_53(I7210,g5367,I7208);
nand NAND4_5(g3530,g3204,g3023,g2197,g2179);
nand NAND2_54(I6964,g586,I6962);
nand NAND2_55(I5208,g3267,I5207);
nand NAND2_56(I5302,g3505,I5300);
nand NAND2_57(g5777,I7535,I7536);
nand NAND2_58(g4613,I6195,I6196);
nand NAND2_59(I2544,g774,I2542);
nand NAND2_60(g1138,g102,g98);
nand NAND2_61(I1994,g504,g218);
nand NAND2_62(I4445,g2092,I4444);
nand NAND2_63(I2061,g7,I2060);
nand NAND2_64(I5189,g3593,I5187);
nand NAND2_65(g4903,g4717,g858);
nand NAND2_66(I3178,g1706,I3177);
nand NAND2_67(I4920,g3522,I4919);
nand NAND2_68(g2951,g2142,g1797);
nand NAND4_6(g3518,g3177,g3023,g3007,g2981);
nand NAND2_69(I2003,g500,g212);
nand NAND3_7(g6717,g6669,g5065,g5062);
nand NAND2_70(I3916,g2449,I3914);
nand NAND4_7(g5864,g5649,g1529,g1088,g2068);
nand NAND3_8(g2008,g866,g873,g1784);
nand NAND2_71(I5309,g3512,I5307);
nand NAND2_72(I7432,g111,g5554);
nand NAND2_73(I4203,g2255,g743);
nand NAND4_8(g3521,g3187,g3023,g3007,g2179);
nand NAND2_74(I5759,g3836,g3503);
nand NAND2_75(I6962,g4874,g586);
nand NAND2_76(I6659,g4762,g3541);
nand NAND2_77(I4940,g3437,I4939);
nand NAND2_78(I2935,g345,I2933);
nand NAND2_79(g2266,I3412,I3413);
nand NAND2_80(I2542,g821,g774);
nand NAND2_81(I3412,g1419,I3411);
nand NAND2_82(I3189,g1716,I3188);
nand NAND2_83(g5634,g5563,g4767);
nand NAND2_84(I3990,g2544,I3988);
nand NAND2_85(g2960,I4151,I4152);
nand NAND2_86(g5926,g5741,g639);
nand NAND4_9(g3511,g3158,g3002,g2976,g2968);
nand NAND2_87(I7439,g5515,g594);
nand NAND2_88(I2090,g33,I2089);
nand NAND4_10(g5862,g5649,g1529,g1535,g2068);
nand NAND2_89(I9050,g6832,g3598);
nand NAND2_90(I5766,g3961,g3957);
nand NAND3_9(g1582,g784,g774,g821);
nand NAND2_91(g1793,g94,g1084);
nand NAND2_92(g3968,I5227,I5228);
nand NAND2_93(I7527,g49,g5662);
nand NAND2_94(I5226,g3259,g3263);
nand NAND2_95(g4049,g3677,g3425);
nand NAND2_96(I7224,g161,I7223);
nand NAND2_97(I5767,g3961,I5766);
nand NAND2_98(I5535,g3907,g654);
nand NAND2_99(I5227,g3259,I5226);
nand NAND2_100(g5947,g5821,g2944);
nand NAND2_101(g3742,I4920,I4921);
nand NAND4_11(g5873,g5649,g1017,g1564,g2113);
nand NAND2_102(g4504,I6027,I6028);
nand NAND2_103(I7244,g188,g5377);
nand NAND3_10(g5869,g5649,g1076,g2081);
nand NAND2_104(I5188,g3589,I5187);
nand NAND2_105(g3983,I5270,I5271);
nand NAND4_12(g4678,g2897,g2101,g1514,g4550);
nand NAND2_106(g6843,I9051,I9052);
nand NAND2_107(g3961,I5208,I5209);
nand NAND2_108(I5308,g478,I5307);
nand NAND2_109(I2506,g1047,g1044);
nand NAND2_110(I3445,g1689,g729);
nand NAND2_111(g2061,I3169,I3170);
nand NAND2_112(I3169,g1540,I3168);
nand NAND3_11(g6740,g6703,g6457,g4936);
nand NAND2_113(I7556,g69,I7555);
nand NAND2_114(g4007,I5308,I5309);
nand NAND2_115(I5196,g3567,I5195);
nand NAND2_116(I7563,g74,I7562);
nand NAND2_117(g5684,I7440,I7441);
nand NAND2_118(I2507,g1047,I2506);
nand NAND2_119(I1995,g504,I1994);
nand NAND2_120(g2307,I3446,I3447);
nand NAND2_121(I7237,g179,g5374);
nand NAND2_122(g2858,g1815,g2577);
nand NAND2_123(g2757,I3934,I3935);
nand NAND2_124(I6744,g4708,I6743);
nand NAND2_125(I4183,g2292,I4182);
nand NAND2_126(I7557,g5674,I7555);
nand NAND2_127(I2300,g830,I2299);
nand NAND2_128(I3188,g1716,g791);
nand NAND4_13(g5865,g5649,g1088,g1076,g2068);
nand NAND2_129(I5197,g3571,I5195);
nand NAND2_130(I4161,g619,I4159);
nand NAND2_131(I3741,g349,I3739);
nand NAND2_132(g5019,I6660,I6661);
nand NAND2_133(I5257,g3714,g3719);
nand NAND4_14(g3532,g3212,g2215,g3007,g2981);
nand NAND2_134(I2528,g719,I2526);
nand NAND2_135(I5301,g471,I5300);
nand NAND2_136(g1743,g1064,g94);
nand NAND2_137(g1411,g314,g873);
nand NAND2_138(g3012,I4204,I4205);
nand NAND2_139(g5504,I7217,I7218);
nand NAND2_140(I6175,g4236,g571);
nand NAND2_141(I3455,g1691,g784);
nand NAND2_142(I6500,g4504,I6499);
nand NAND3_12(g1573,g729,g719,g766);
nand NAND2_143(I3846,g284,g2370);
nand NAND2_144(I4210,g2294,g804);
nand NAND2_145(g4803,I6474,I6475);
nand NAND2_146(g3109,g2360,g1064);
nand NAND2_147(g2698,I3847,I3848);
nand NAND2_148(g3957,I5196,I5197);
nand NAND2_149(I6499,g4504,g3541);
nand NAND4_15(g4816,g996,g4550,g1518,g2073);
nand NAND2_150(I3847,g284,I3846);
nand NAND2_151(I7520,g361,g5659);
nand NAND2_152(I4784,g622,I4782);
nand NAND2_153(I1952,g524,I1951);
nand NAND4_16(g3539,g2591,g2215,g2197,g2981);
nand NAND2_154(I8202,g478,I8201);
nand NAND2_155(I1986,g508,g224);
nand NAND2_156(I2933,g1436,g345);
nand NAND2_157(I5760,g3836,I5759);
nand NAND2_158(g4301,I5767,I5768);
nand NAND2_159(I1970,g516,I1969);
nand NAND2_160(I7225,g5370,I7223);
nand NAND2_161(I6660,g4762,I6659);
nand NAND2_162(g5502,I7209,I7210);
nand NAND2_163(I3168,g1540,g1534);
nand NAND2_164(I1987,g508,I1986);
nand NAND2_165(g1316,I2300,I2301);
nand NAND2_166(I2674,g710,g131);
nand NAND4_17(g4669,g4550,g1017,g1680,g2897);
nand NAND2_167(I3411,g1419,g616);
nand NAND2_168(I7245,g188,I7244);
nand NAND2_169(g2607,I3740,I3741);
nand NAND2_170(g5308,I6963,I6964);
nand NAND2_171(g2311,I3456,I3457);
nand NAND4_18(g3535,g3216,g2215,g2197,g2968);
nand NAND2_172(g5455,g2330,g5311);
nand NAND2_173(I4782,g2846,g622);
nand NAND2_174(I9052,g3598,I9050);
nand NAND2_175(I3126,g1279,I3125);
nand NAND2_176(I3400,g135,I3398);
nand NAND2_177(I4526,g2909,g646);
nand NAND2_178(g5780,I7556,I7557);
nand NAND2_179(g3246,I4527,I4528);
nand NAND3_13(g3502,g1411,g1402,g2795);
nand NAND2_180(g4608,I6176,I6177);
nand NAND2_181(I4919,g3522,g650);
nand NAND3_14(g2100,g1588,g804,g791);
nand NAND2_182(I7230,g170,g5372);
nand NAND2_183(I7433,g111,I7432);
nand NAND2_184(I3127,g1276,I3125);
nand NAND2_185(g3028,I4234,I4235);
nand NAND2_186(I2795,g804,g798);
nand NAND2_187(I5784,g628,I5782);
nand NAND2_188(I4527,g2909,I4526);
nand NAND2_189(I7550,g5672,I7548);
nand NAND2_190(I4546,g2853,I4545);
nand NAND2_191(I6745,g582,I6743);
nand NAND2_192(I5294,g625,I5292);
nand NAND2_193(I6963,g4874,I6962);
nand NAND3_15(g3741,g901,g3433,g2340);
nand NAND2_194(g1157,g89,g107);
nand NAND2_195(I2499,g1036,I2497);
nand NAND2_196(g937,I1979,I1980);
nand NAND2_197(g4472,g3380,g4253);
nand NAND3_16(g2010,g1473,g1470,g1459);
nand NAND2_198(g928,I1962,I1963);
nand NAND2_199(I7097,g5194,g574);
nand NAND2_200(I4547,g353,I4545);
nand NAND2_201(I3697,g1570,g642);
nand NAND2_202(I3914,g287,g2449);
nand NAND2_203(I2543,g821,I2542);
nand NAND2_204(I3413,g616,I3411);
nand NAND2_205(I7218,g5368,I7216);
nand NAND2_206(I7312,g5364,I7311);
nand NAND4_19(g3538,g2588,g2215,g2197,g2179);
nand NAND2_207(g5505,I7224,I7225);
nand NAND2_208(g1075,I2109,I2110);
nand NAND2_209(I2014,g532,I2013);
nand NAND2_210(g2804,I4009,I4010);
nand NAND3_17(g6742,g6683,g932,g6716);
nand NAND2_211(I6185,g4301,g3955);
nand NAND4_20(g5863,g5649,g1076,g1535,g2068);
nand NAND2_212(I3739,g2021,g349);
nand NAND2_213(I2022,g528,I2021);
nand NAND2_214(I5782,g3810,g628);
nand NAND2_215(I7576,g84,g5680);
nand NAND4_21(g5688,g5546,g1585,g2084,g2916);
nand NAND4_22(g5857,g5638,g1552,g1017,g2062);
nand NAND2_216(I3190,g791,I3188);
nand NAND2_217(I5292,g3421,g625);
nand NAND2_218(g1764,I2796,I2797);
nand NAND2_219(I3954,g2497,I3952);
nand NAND2_220(g5779,I7549,I7550);
nand NAND2_221(I7577,g84,I7576);
nand NAND2_222(I5647,g3974,g3968);
nand NAND4_23(g3531,g3209,g2215,g2976,g2179);
nand NAND2_223(I1980,g230,I1978);
nand NAND2_224(g5508,I7245,I7246);
nand NAND2_225(I4150,g2551,g139);
nand NAND2_226(g6873,g6848,g3621);
nand NAND2_227(g6095,g2952,g5854);
nand NAND2_228(I4009,g292,I4008);
nand NAND2_229(I2675,g710,I2674);
nand NAND2_230(g926,I1952,I1953);
nand NAND2_231(I3894,g286,I3893);
nand NAND2_232(I4212,g804,I4210);
nand NAND2_233(g5565,I7312,I7313);
nand NAND2_234(I6028,g4221,I6026);
nand NAND2_235(I2109,g602,I2108);
nand NAND2_236(I5244,g3247,I5242);
nand NAND3_18(g1402,g310,g866,g873);
nand NAND2_237(I4921,g650,I4919);
nand NAND2_238(I7536,g5666,I7534);
nand NAND2_239(I7223,g161,g5370);
nand NAND2_240(I2498,g1042,I2497);
nand NAND2_241(I1951,g524,g248);
nand NAND2_242(I7522,g5659,I7520);
nand NAND2_243(I3952,g289,g2497);
nand NAND2_244(g5775,I7521,I7522);
nand NAND2_245(I8201,g478,g6192);
nand NAND2_246(g2024,I3126,I3127);
nand NAND2_247(g2795,g1997,g866);
nand NAND2_248(g4004,I5301,I5302);
nand NAND2_249(I6196,g631,I6194);
nand NAND2_250(I3970,g290,g2518);
nand NAND2_251(I4941,g357,I4939);
nand NAND2_252(I5657,g3983,g3979);
nand NAND2_253(I7542,g59,I7541);
nand NAND2_254(I2897,g1027,g634);
nand NAND2_255(I2682,g918,I2681);
nand NAND2_256(I2766,g749,g743);
nand NAND2_257(g3013,I4211,I4212);
nand NAND2_258(I5242,g3242,g3247);
nand NAND2_259(I7529,g5662,I7527);
nand NAND2_260(g1822,g1070,g1084);
nand NAND2_261(I3876,g2397,I3874);
nand NAND2_262(I2091,g29,I2089);
nand NAND2_263(I3915,g287,I3914);
nand NAND2_264(I9051,g6832,I9050);
nand NAND2_265(I2767,g749,I2766);
nand NAND2_266(I1979,g512,I1978);
nand NAND2_267(g3597,I4783,I4784);
nand NAND3_19(g2831,g2007,g862,g1784);
nand NAND2_268(g5683,I7433,I7434);
nand NAND2_269(g5778,I7542,I7543);
nand NAND2_270(I2015,g260,I2013);
nand NAND2_271(g930,I1970,I1971);
nand NAND2_272(g5782,I7570,I7571);
nand NAND2_273(g4002,I5293,I5294);
nand NAND2_274(I2246,g598,I2244);
nand NAND2_275(I6743,g4708,g582);
nand NAND2_276(I7549,g64,I7548);
nand NAND2_277(g2947,g1411,g2026);
nand NAND2_278(g4762,I6391,I6392);
nand NAND3_20(g2095,g1584,g749,g736);
nand NAND2_279(g944,I2004,I2005);
nand NAND2_280(I6474,g4541,I6473);
nand NAND2_281(I7232,g5372,I7230);
nand NAND2_282(I1953,g248,I1951);
nand NAND2_283(g2719,I3875,I3876);
nand NAND2_284(I8203,g6192,I8201);
nand NAND2_285(I4008,g292,g2568);
nand NAND2_286(g4237,g4049,g4017);
nand NAND2_287(g1829,I2898,I2899);
nand NAND2_288(g901,g314,g310);
nand NAND2_289(g941,I1995,I1996);
nand NAND2_290(I7570,g79,I7569);
nand NAND2_291(I2108,g602,g610);
nand NAND2_292(g1540,I2507,I2508);
nand NAND4_24(g4814,g4550,g1575,g1550,g2073);
nand NAND2_293(I7311,g5364,g590);
nand NAND2_294(I5270,g3705,I5269);
nand NAND2_295(g2745,I3915,I3916);
nand NAND3_21(g1797,g98,g1064,g1070);
nand NAND2_296(g2791,I3989,I3990);
nand NAND2_297(I7239,g5374,I7237);
nand NAND4_25(g3526,g3196,g3023,g2197,g2981);
nand NAND3_22(g6741,g6705,g6461,g4941);
nand NAND2_298(I8196,g6188,I8194);
nand NAND2_299(I3895,g2422,I3893);
nand NAND2_300(I4783,g2846,I4782);
nand NAND2_301(I2021,g528,g254);
nand NAND2_302(g905,g301,g319);
nand NAND2_303(g3276,I4546,I4547);
nand NAND2_304(g6774,g6754,g6750);
nand NAND2_305(I5207,g3267,g3271);
nand NAND2_306(I2301,g341,I2299);
nand NAND2_307(I5259,g3719,I5257);
nand NAND2_308(I7440,g5515,I7439);
nand NAND2_309(I7528,g49,I7527);
nand NAND2_310(g4640,g4402,g1056);
nand NAND4_26(g4812,g4550,g1560,g1559,g2073);
nand NAND2_311(g1845,I2934,I2935);
nand NAND2_312(g6397,I8202,I8203);
nand NAND2_313(I5768,g3957,I5766);
nand NAND2_314(I1978,g512,g230);
nand NAND2_315(g4610,I6186,I6187);
nand NAND2_316(I5228,g3263,I5226);
nand NAND2_317(I2074,g11,I2072);
nand NAND3_23(g3140,g2409,g1060,g1620);
nand NAND2_318(I6390,g4504,g4610);
nand NAND2_319(I3177,g1706,g736);
nand NAND2_320(I4152,g139,I4150);
nand NAND2_321(I6501,g3541,I6499);
nand NAND2_322(I7548,g64,g5672);
nand NAND2_323(g1815,g102,g1070);
nand NAND2_324(I7555,g69,g5674);
nand NAND4_27(g3517,g3173,g3002,g2976,g2179);
nand NAND2_325(I2080,g25,g19);
nand NAND2_326(I4211,g2294,I4210);
nand NAND2_327(I3399,g1826,I3398);
nand NAND2_328(I5195,g3567,g3571);
nand NAND2_329(I7313,g590,I7311);
nand NAND2_330(g2582,I3698,I3699);
nand NAND2_331(I4939,g3437,g357);
nand NAND2_332(g950,I2022,I2023);
nand NAND2_333(g4819,I6500,I6501);
nand NAND2_334(I7521,g361,I7520);
nand NAND2_335(I2023,g254,I2021);
nand NAND2_336(I4446,g606,I4444);
nand NAND2_337(I5783,g3810,I5782);
nand NAND2_338(g2940,g197,g2381);
nand NAND2_339(g4825,g4472,g4465);
nand NAND2_340(I5293,g3421,I5292);
nand NAND2_341(I5761,g3503,I5759);
nand NAND2_342(I1971,g236,I1969);
nand NAND2_343(I3972,g2518,I3970);
nand NAND2_344(I4159,g2015,g619);
nand NAND2_345(I6661,g3541,I6659);
nand NAND2_346(g1398,g306,g889);
nand NAND2_347(I6475,g578,I6473);
nand NAND2_348(I3934,g288,I3933);
nand NAND2_349(I7541,g59,g5669);
nand NAND2_350(I2508,g1044,I2506);
nand NAND4_28(g5854,g5638,g1683,g1552,g2062);
nand NAND2_351(g4465,g319,g4253);
nand NAND2_352(I2072,g15,g11);
nand NAND2_353(I7238,g179,I7237);
nand NAND2_354(g3955,I5188,I5189);
nand NAND2_355(I7209,g143,I7208);
nand NAND2_356(g5431,I7098,I7099);
nand NAND2_357(I2681,g918,g613);
nand NAND2_358(I2013,g532,g260);
nand NAND2_359(I4234,g2267,I4233);
nand NAND2_360(g2780,I3971,I3972);
nand NAND2_361(g2067,I3178,I3179);
nand NAND2_362(I1962,g520,I1961);
nand NAND2_363(I5258,g3714,I5257);
nand NAND3_24(g1387,g862,g314,g301);
nand NAND2_364(I2060,g7,g3);
nand NAND2_365(g5781,I7563,I7564);
nand NAND2_366(g2263,I3399,I3400);
nand NAND2_367(g4221,I5648,I5649);
nand NAND2_368(g1359,g866,g306);
nand NAND2_369(I7231,g170,I7230);
nand NAND2_370(I3953,g289,I3952);
nand NAND2_371(I5187,g3589,g3593);
nand NAND3_25(g5852,g5638,g2053,g1661);
nand NAND4_29(g3520,g3183,g3002,g2197,g2968);
nand NAND2_372(g1047,I2090,I2091);
nand NAND2_373(I7099,g574,I7097);
nand NAND2_374(I3848,g2370,I3846);
nand NAND2_375(I3699,g642,I3697);
nand NAND2_376(I3398,g1826,g135);
nand NAND2_377(I1969,g516,g236);
nand NAND2_378(I5307,g478,g3512);
nand NAND2_379(g3974,I5243,I5244);
nand NAND2_380(I5536,g3907,I5535);
nand NAND2_381(g1417,g873,g889);
nand NAND2_382(I7543,g5669,I7541);
nand NAND2_383(g5943,g5818,g2940);
nand NAND2_384(I7534,g54,g5666);
nand NAND2_385(g4319,I5783,I5784);
nand NAND2_386(I3893,g286,g2422);
nand NAND2_387(g2080,I3189,I3190);
nand NAND2_388(I2683,g613,I2681);
nand NAND2_389(I5537,g654,I5535);
nand NAND2_390(I3170,g1534,I3168);
nand NAND2_391(I3125,g1279,g1276);
nand NAND2_392(I5243,g3242,I5242);
nand NAND2_393(I1988,g224,I1986);
nand NAND2_394(I6194,g4199,g631);
nand NAND2_395(g3207,I4445,I4446);
nand NAND2_396(I2526,g766,g719);
nand NAND2_397(g6929,g4536,g6927);
nand NAND2_398(g3215,g2340,g1402);
nand NAND2_399(I3446,g1689,I3445);
nand NAND2_400(I7208,g143,g5367);
nand NAND2_401(g5783,I7577,I7578);
nand NAND2_402(I4545,g2853,g353);
nand NAND2_403(I2004,g500,I2003);
nand NAND2_404(I2527,g766,I2526);
nand NAND2_405(I5649,g3968,I5647);
nand NAND2_406(g6778,g6762,g6758);
nand NAND2_407(g1686,I2675,I2676);
nand NAND2_408(g4223,I5658,I5659);
nand NAND2_409(I1996,g218,I1994);
nand NAND2_410(I3447,g729,I3445);
nand NAND2_411(I4204,g2255,I4203);
nand NAND2_412(I3874,g285,g2397);
nand NAND2_413(g2944,g269,g2381);
nand NAND2_414(g1253,I2245,I2246);
nand NAND3_26(g2434,g1064,g1070,g1620);
nand NAND2_415(I2299,g830,g341);
nand NAND3_27(g5866,g5649,g1529,g2081);
nand NAND2_416(g1687,I2682,I2683);
nand NAND2_417(I3935,g2473,I3933);
nand NAND2_418(g4017,g107,g3425);
nand NAND2_419(I4528,g646,I4526);
nand NAND2_420(I2244,g567,g598);
nand NAND2_421(I4151,g2551,I4150);
nand NAND2_422(I6392,g4610,I6390);
nand NAND2_423(I4010,g2568,I4008);
nand NAND2_424(I2082,g19,I2080);
nand NAND4_30(g5818,g5638,g2056,g1666,g1661);
nand NAND2_425(g3979,I5258,I5259);
nand NAND2_426(I6176,g4236,I6175);
nand NAND2_427(I4235,g798,I4233);
nand NAND2_428(I2110,g610,I2108);
nand NAND2_429(I7098,g5194,I7097);
nand NAND2_430(I3456,g1691,I3455);
nand NAND4_31(g5821,g5638,g2056,g1076,g1666);
nand NAND2_431(I3698,g1570,I3697);
nand NAND2_432(g2995,I4183,I4184);
nand NAND2_433(I6473,g4541,g578);
nand NAND2_434(I5659,g3979,I5657);
nand NAND2_435(g5636,g5564,g4769);
nand NAND2_436(I6177,g571,I6175);
nand NAND2_437(I2899,g634,I2897);
nand NAND2_438(I3457,g784,I3455);
nand NAND2_439(I3989,g291,I3988);
nand NAND2_440(I3971,g290,I3970);
nand NAND2_441(I4160,g2015,I4159);
nand NAND2_442(I2089,g33,g29);
nand NAND2_443(g4670,g4611,g3528);
nand NAND4_32(g4813,g4550,g965,g1560,g2073);
nand NAND2_444(I3740,g2021,I3739);
nand NAND2_445(I8194,g471,g6188);
nand NAND2_446(I5300,g471,g3505);
nand NAND3_28(g3893,g3664,g3656,g3647);
nand NAND2_447(g6928,g4532,g6926);
nand NAND2_448(I7578,g5680,I7576);
nand NAND2_449(I7535,g54,I7534);
nand NAND2_450(I1961,g520,g242);
nand NAND4_33(g3544,g2594,g2215,g2197,g2179);
nand NAND2_451(g6394,I8195,I8196);
nand NAND2_452(I5648,g3974,I5647);
nand NAND2_453(I7246,g5377,I7244);
nand NAND2_454(g3756,I4940,I4941);
nand NAND2_455(I2062,g3,I2060);
nand NAND2_456(I6195,g4199,I6194);
nand NAND2_457(I7216,g152,g5368);
nand NAND4_34(g3536,g3219,g2215,g3007,g2179);
nand NAND2_458(I7564,g5676,I7562);
nand NAND2_459(g4300,I5760,I5761);
nand NAND2_460(I4184,g749,I4182);
nand NAND2_461(I2005,g212,I2003);
nand NAND2_462(g5318,g676,g5060);
nand NAND4_35(g5872,g5649,g1557,g1564,g2113);
nor NOR2_0(g5552,g5354,g5356);
nor NOR2_1(g4235,g3780,g3362);
nor NOR2_2(g6073,g197,g5862);
nor NOR2_3(g4776,g4449,g4453);
nor NOR2_4(g4777,g4457,g4459);
nor NOR2_5(g4238,g3755,g3279);
nor NOR4_0(g6433,g6385,g3733,g4092,g4314);
nor NOR2_6(g6496,g952,g6354);
nor NOR2_7(g1422,g1039,g913);
nor NOR2_8(g3931,g3353,g3361);
nor NOR2_9(g1560,g996,g980);
nor NOR2_10(g3905,g3512,g478);
nor NOR2_11(g5094,g4685,g4686);
nor NOR2_12(g3973,g3368,g3374);
nor NOR2_13(g3528,g1802,g3167);
nor NOR2_14(g5541,g5388,g1880);
nor NOR2_15(g3621,g1407,g2842);
nor NOR2_16(g1449,g489,g1048);
nor NOR2_17(g3965,g3359,g3367);
nor NOR2_18(g3933,g3327,g3336);
nor NOR4_1(g6280,I7978,I7979,I7980,I7981);
nor NOR2_19(g2433,g1418,g1449);
nor NOR3_0(g1470,g937,g930,g928);
nor NOR4_2(g6427,g6376,g4086,g4074,g4068);
nor NOR4_3(g6446,g6385,g4334,g4092,g4314);
nor NOR4_4(g6359,I8135,I8136,I8137,I8138);
nor NOR3_1(g1459,g926,g950,g948);
nor NOR2_20(g4584,g4164,g4168);
nor NOR2_21(g3926,g3338,g3350);
nor NOR4_5(g6279,I7969,I7970,I7971,I7972);
nor NOR2_22(g5265,g4863,g4865);
nor NOR2_23(g3927,g3382,g3383);
nor NOR2_24(g3903,g3505,g471);
nor NOR2_25(g1418,g486,g943);
nor NOR2_26(g4578,g4234,g3928);
nor NOR2_27(g4261,g3762,g3295);
nor NOR4_6(g6358,I8126,I8127,I8128,I8129);
nor NOR2_28(g4589,g4180,g4183);
nor NOR2_29(g1474,g760,g754);
nor NOR2_30(g3956,g3337,g3349);
nor NOR2_31(g4774,g4442,g4445);
nor NOR2_32(g5091,g4698,g4701);
nor NOR2_33(g4950,g1472,g4680);
nor NOR2_34(g5227,g5019,g3559);
nor NOR2_35(g4585,g4171,g4177);
nor NOR2_36(g6494,g952,g6348);
nor NOR3_2(g5048,g4819,g3491,g3559);
nor NOR3_3(g3664,g2804,g2791,g2780);
nor NOR2_37(g4000,g1250,g3425);
nor NOR2_38(g5418,g5162,g5169);
nor NOR2_39(g5093,g4683,g4684);
nor NOR2_40(g4779,g4461,g4464);
nor NOR2_41(g6492,g6348,g1734);
nor NOR3_4(g4240,g1589,g1879,g3793);
nor NOR2_42(g4596,g4184,g4186);
nor NOR2_43(g1603,g1039,g658);
nor NOR3_5(g2908,g536,g2010,g541);
nor NOR2_44(g4581,g4156,g4160);
nor NOR2_45(g5423,g5170,g5175);
nor NOR2_46(g4432,g923,g4253);
nor NOR4_7(g6436,g6385,g3733,g4328,g4080);
nor NOR2_47(g4568,g4233,g3924);
nor NOR4_8(g6335,I8079,I8080,I8081,I8082);
nor NOR2_48(g5753,g1477,g5688);
nor NOR2_49(g6495,g6354,g1775);
nor NOR4_9(g6442,g6376,g4323,g4074,g4302);
nor NOR4_10(g6429,g6376,g4086,g4074,g4302);
nor NOR4_11(g6281,I7987,I7988,I7989,I7990);
nor NOR4_12(g6449,g6385,g4334,g4328,g4080);
nor NOR2_50(g4590,g4169,g4172);
nor NOR2_51(g4877,g952,g4680);
nor NOR4_13(g6445,g6376,g4323,g4309,g4068);
nor NOR4_14(g5561,g5391,g1589,g3793,g1880);
nor NOR2_52(g3929,g3373,g3376);
nor NOR3_6(g1473,g944,g941,g939);
nor NOR2_53(g4967,g4674,g952);
nor NOR4_15(g6430,g6385,g3733,g4092,g4080);
nor NOR2_54(g4993,g4674,g1477);
nor NOR4_16(g6448,g6376,g4323,g4309,g4302);
nor NOR3_7(g3647,g2731,g2719,g2698);
nor NOR2_55(g3925,g3303,g3315);
nor NOR2_56(g5731,g952,g5688);
nor NOR2_57(g3959,g3352,g3360);
nor NOR2_58(g1481,g815,g809);
nor NOR3_8(g3656,g2769,g2757,g2745);
nor NOR2_59(g4245,g3759,g3288);
nor NOR2_60(g3930,g3317,g3328);
nor NOR2_61(g5249,g4868,g4870);
nor NOR2_62(g3966,g3329,g3339);
nor NOR4_17(g6400,I8208,I8209,I8210,I8211);
nor NOR2_63(g4266,g3757,g3283);
nor NOR4_18(g6451,g6385,g4334,g4328,g4314);
nor NOR3_9(g5324,g5069,g4410,g766);
nor NOR4_19(g6443,g6385,g4334,g4092,g4080);
nor NOR2_64(g5088,g4691,g4697);
nor NOR2_65(g3958,g3316,g3326);
nor NOR2_66(g4241,g3774,g3341);
nor NOR4_20(g6432,g6376,g4086,g4309,g4068);
nor NOR4_21(g6357,I8117,I8118,I8119,I8120);
nor NOR2_67(g3923,g3378,g3381);
nor NOR2_68(g6075,g269,g5863);
nor NOR2_69(g3934,g3377,g3379);
nor NOR4_22(g6439,g6385,g3733,g4328,g4314);
nor NOR2_70(g4272,g3767,g3319);
nor NOR2_71(g1879,g1603,g1416);
nor NOR3_10(g5325,g5077,g4416,g821);
nor NOR4_23(g6435,g6376,g4086,g4309,g4302);
nor NOR2_72(g4586,g4161,g4165);
nor NOR2_73(g3939,g3340,g3351);
nor NOR4_24(g6438,g6376,g4323,g4074,g4068);
nor NOR2_74(g1518,g980,g965);
nor NOR2_75(g4239,g3763,g3296);
nor NOR2_76(g4591,g4178,g4181);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND3B_2_V
`define SKY130_FD_SC_HS__NAND3B_2_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog wrapper for nand3b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nand3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nand3b_2 (
Y ,
A_N ,
B ,
C ,
VPWR,
VGND
);
output Y ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
sky130_fd_sc_hs__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nand3b_2 (
Y ,
A_N,
B ,
C
);
output Y ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND3B_2_V
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module seq_gen_blk_mem (
clka, clkb, wea, addra, dina, web, addrb, dinb, douta, doutb
);
input wire clka;
input wire clkb;
input wire [0 : 0] wea;
input wire [13 : 0] addra;
input wire [7 : 0] dina;
input wire [0 : 0] web;
input wire [12 : 0] addrb;
input wire [15 : 0] dinb;
output wire [7 : 0] douta;
output wire [15 : 0] doutb;
RAMB16_S1_S2 mem0 (
.CLKA(clka),
.CLKB(clkb),
.ENB(1'b1),
.SSRB(1'b0),
.WEA(wea[0]),
.WEB(web[0]),
.ENA(1'b1),
.SSRA(1'b0),
.ADDRA(addra[13:0]),
.ADDRB(addrb[12:0]),
.DIA({dina[7]}),
.DIB({dinb[15], dinb[7]}),
.DOA({douta[7]}),
.DOB({doutb[15], doutb[7]})
);
RAMB16_S1_S2 mem1 (
.CLKA(clka),
.CLKB(clkb),
.ENB(1'b1),
.SSRB(1'b0),
.WEA(wea[0]),
.WEB(web[0]),
.ENA(1'b1),
.SSRA(1'b0),
.ADDRA(addra[13:0]),
.ADDRB(addrb[12:0]),
.DIA({dina[6]}),
.DIB({dinb[14], dinb[6]}),
.DOA({douta[6]}),
.DOB({doutb[14], doutb[6]})
);
RAMB16_S1_S2 mem2 (
.CLKA(clka),
.CLKB(clkb),
.ENB(1'b1),
.SSRB(1'b0),
.WEA(wea[0]),
.WEB(web[0]),
.ENA(1'b1),
.SSRA(1'b0),
.ADDRA(addra[13:0]),
.ADDRB(addrb[12:0]),
.DIA({dina[5]}),
.DIB({dinb[13], dinb[5]}),
.DOA({douta[5]}),
.DOB({doutb[13], doutb[5]})
);
RAMB16_S1_S2 mem3 (
.CLKA(clka),
.CLKB(clkb),
.ENB(1'b1),
.SSRB(1'b0),
.WEA(wea[0]),
.WEB(web[0]),
.ENA(1'b1),
.SSRA(1'b0),
.ADDRA(addra[13:0]),
.ADDRB(addrb[12:0]),
.DIA({dina[4]}),
.DIB({dinb[12], dinb[4]}),
.DOA({douta[4]}),
.DOB({doutb[12], doutb[4]})
);
RAMB16_S1_S2 mem4 (
.CLKA(clka),
.CLKB(clkb),
.ENB(1'b1),
.SSRB(1'b0),
.WEA(wea[0]),
.WEB(web[0]),
.ENA(1'b1),
.SSRA(1'b0),
.ADDRA(addra[13:0]),
.ADDRB(addrb[12:0]),
.DIA({dina[3]}),
.DIB({dinb[11], dinb[3]}),
.DOA({douta[3]}),
.DOB({doutb[11], doutb[3]})
);
RAMB16_S1_S2 mem5 (
.CLKA(clka),
.CLKB(clkb),
.ENB(1'b1),
.SSRB(1'b0),
.WEA(wea[0]),
.WEB(web[0]),
.ENA(1'b1),
.SSRA(1'b0),
.ADDRA(addra[13:0]),
.ADDRB(addrb[12:0]),
.DIA({dina[2]}),
.DIB({dinb[10], dinb[2]}),
.DOA({douta[2]}),
.DOB({doutb[10], doutb[2]})
);
RAMB16_S1_S2 mem6 (
.CLKA(clka),
.CLKB(clkb),
.ENB(1'b1),
.SSRB(1'b0),
.WEA(wea[0]),
.WEB(web[0]),
.ENA(1'b1),
.SSRA(1'b0),
.ADDRA(addra[13:0]),
.ADDRB(addrb[12:0]),
.DIA({dina[1]}),
.DIB({dinb[9], dinb[1]}),
.DOA({douta[1]}),
.DOB({doutb[9], doutb[1]})
);
RAMB16_S1_S2 mem7 (
.CLKA(clka),
.CLKB(clkb),
.ENB(1'b1),
.SSRB(1'b0),
.WEA(wea[0]),
.WEB(web[0]),
.ENA(1'b1),
.SSRA(1'b0),
.ADDRA(addra[13:0]),
.ADDRB(addrb[12:0]),
.DIA({dina[0]}),
.DIB({dinb[8], dinb[0]}),
.DOA({douta[0]}),
.DOB({doutb[8], doutb[0]})
);
endmodule
|
(** * StlcProp: Properties of STLC *)
Set Warnings "-notation-overridden,-parsing".
From PLF Require Import Maps.
From PLF Require Import Types.
From PLF Require Import Stlc.
From PLF Require Import Smallstep.
Module STLCProp.
Import STLC.
(** In this chapter, we develop the fundamental theory of the Simply
Typed Lambda Calculus -- in particular, the type safety
theorem. *)
(* ################################################################# *)
(** * Canonical Forms *)
(** As we saw for the very simple language in the [Types]
chapter, the first step in establishing basic properties of
reduction and types is to identify the possible _canonical
forms_ (i.e., well-typed closed values) belonging to each type.
For [Bool], these are again the boolean values [true] and [false];
for arrow types, they are lambda-abstractions. *)
Lemma canonical_forms_bool : forall t,
empty |- t \in Bool ->
value t ->
(t = <{true}>) \/ (t = <{false}>).
Proof.
intros t HT HVal.
destruct HVal; auto.
inversion HT.
Qed.
Lemma canonical_forms_fun : forall t T1 T2,
empty |- t \in (T1 -> T2) ->
value t ->
exists x u, t = <{\x:T1, u}>.
Proof.
intros t T1 T2 HT HVal.
destruct HVal; inversion HT; subst.
exists x0, t1. reflexivity.
Qed.
(* ################################################################# *)
(** * Progress *)
(** The _progress_ theorem tells us that closed, well-typed
terms are not stuck: either a well-typed term is a value, or it
can take a reduction step. The proof is a relatively
straightforward extension of the progress proof we saw in the
[Types] chapter. We give the proof in English first, then
the formal version. *)
Theorem progress : forall t T,
empty |- t \in T ->
value t \/ exists t', t --> t'.
(** _Proof_: By induction on the derivation of [|- t \in T].
- The last rule of the derivation cannot be [T_Var], since a
variable is never well typed in an empty context.
- The [T_True], [T_False], and [T_Abs] cases are trivial, since in
each of these cases we can see by inspecting the rule that [t]
is a value.
- If the last rule of the derivation is [T_App], then [t] has the
form [t1 t2] for some [t1] and [t2], where [|- t1 \in T2 -> T]
and [|- t2 \in T2] for some type [T2]. The induction hypothesis
for the first subderivation says that either [t1] is a value or
else it can take a reduction step.
- If [t1] is a value, then consider [t2], which by the
induction hypothesis for the second subderivation must also
either be a value or take a step.
- Suppose [t2] is a value. Since [t1] is a value with an
arrow type, it must be a lambda abstraction; hence [t1
t2] can take a step by [ST_AppAbs].
- Otherwise, [t2] can take a step, and hence so can [t1
t2] by [ST_App2].
- If [t1] can take a step, then so can [t1 t2] by [ST_App1].
- If the last rule of the derivation is [T_If], then [t = if
t1 then t2 else t3], where [t1] has type [Bool]. The first IH
says that [t1] either is a value or takes a step.
- If [t1] is a value, then since it has type [Bool] it must be
either [true] or [false]. If it is [true], then [t] steps to
[t2]; otherwise it steps to [t3].
- Otherwise, [t1] takes a step, and therefore so does [t] (by
[ST_If]). *)
Proof with eauto.
intros t T Ht.
remember empty as Gamma.
induction Ht; subst Gamma; auto.
(* auto solves all three cases in which t is a value *)
- (* T_Var *)
(* contradictory: variables cannot be typed in an
empty context *)
discriminate H.
- (* T_App *)
(* [t] = [t1 t2]. Proceed by cases on whether [t1] is a
value or steps... *)
right. destruct IHHt1...
+ (* t1 is a value *)
destruct IHHt2...
* (* t2 is also a value *)
eapply canonical_forms_fun in Ht1; [|assumption].
destruct Ht1 as [x [t0 H1]]. subst.
exists (<{ [x:=t2]t0 }>)...
* (* t2 steps *)
destruct H0 as [t2' Hstp]. exists (<{t1 t2'}>)...
+ (* t1 steps *)
destruct H as [t1' Hstp]. exists (<{t1' t2}>)...
- (* T_If *)
right. destruct IHHt1...
+ (* t1 is a value *)
destruct (canonical_forms_bool t1); subst; eauto.
+ (* t1 also steps *)
destruct H as [t1' Hstp]. exists <{if t1' then t2 else t3}>...
Qed.
(** **** Exercise: 3 stars, advanced (progress_from_term_ind)
Show that progress can also be proved by induction on terms
instead of induction on typing derivations. *)
Theorem progress' : forall t T,
empty |- t \in T ->
value t \/ exists t', t --> t'.
Proof.
intros t.
induction t; intros T Ht; auto.
- (* variable *)
inversion Ht; subst; clear Ht. inversion H1.
- (* application *)
right.
inversion Ht; subst; clear Ht.
assert (Ht1: value t1 \/ (exists t' : tm, t1 --> t')) by eauto.
assert (Ht2: value t2 \/ (exists t' : tm, t2 --> t')) by eauto.
clear IHt1 IHt2.
destruct Ht2; destruct Ht1.
(* case 1: t1 is value (lambda), t2 is value *)
+ apply (canonical_forms_fun _ _ _ H2) in H0.
destruct H0 as [x [t1']]; subst.
eauto.
+ (* case 2: t1 -> t', t2 is value *)
destruct H0. eauto.
+ (* case 3: t1 is value, t2 -> t' *)
destruct H. eauto.
+ (* case 3: t1 -> t', t2 -> t' *)
destruct H0; destruct H; eauto.
- (* if *)
right.
inversion Ht; subst; clear Ht.
(* duplicate H3 *)
assert (empty |- t1 \in Bool) by assumption.
apply IHt1 in H3. destruct H3.
+ (* t1 is value *)
apply (canonical_forms_bool _ H) in H0. destruct H0; subst; eauto.
+ (* t1 -> t' *)
destruct H0. eauto.
Qed.
(** [] *)
(* ################################################################# *)
(** * Preservation *)
(** The other half of the type soundness property is the
preservation of types during reduction. For this part, we'll need
to develop some technical machinery for reasoning about variables
and substitution. Working from top to bottom (from the high-level
property we are actually interested in to the lowest-level
technical lemmas that are needed by various cases of the more
interesting proofs), the story goes like this:
- The _preservation theorem_ is proved by induction on a typing
derivation, pretty much as we did in the [Types] chapter.
The one case that is significantly different is the one for
the [ST_AppAbs] rule, whose definition uses the substitution
operation. To see that this step preserves typing, we need to
know that the substitution itself does. So we prove a...
- _substitution lemma_, stating that substituting a (closed)
term [s] for a variable [x] in a term [t] preserves the type
of [t]. The proof goes by induction on the form of [t] and
requires looking at all the different cases in the definition
of substitition. This time, for the variables case, we
discover that we need to deduce from the fact that a term
[s] has type S in the empty context the fact that [s] has
type S in every context. For this we prove a...
- _weakening_ lemma, showing that typing is preserved under
"extensions" to the context [Gamma].
To make Coq happy, of course, we need to formalize the story in the
opposite order... *)
(* ================================================================= *)
(** ** The Weakening Lemma *)
(** Typing is preserved under "extensions" to the context [Gamma].
(Recall the definition of "inclusion" from Maps.v.) *)
Print inclusion.
(*
inclusion =
fun (A : Type) (m m' : partial_map A) =>
forall (x : string) (v : A), m x = Some v -> m' x = Some v
: forall A : Type, partial_map A -> partial_map A -> Prop
*)
Lemma weakening : forall Gamma Gamma' t T,
inclusion Gamma Gamma' ->
Gamma |- t \in T ->
Gamma' |- t \in T.
Proof.
intros Gamma Gamma' t T H Ht.
generalize dependent Gamma'.
induction Ht; eauto using inclusion_update.
Qed.
(** The following simple corollary is useful below. *)
Lemma weakening_empty : forall Gamma t T,
empty |- t \in T ->
Gamma |- t \in T.
Proof.
intros Gamma t T.
eapply weakening.
discriminate.
Qed.
(* ================================================================= *)
(** ** A Substitution Lemma *)
(** Now we come to the conceptual heart of the proof that reduction
preserves types -- namely, the observation that _substitution_
preserves types. *)
(** Formally, the so-called _substitution lemma_ says this:
Suppose we have a term [t] with a free variable [x], and suppose
we've assigned a type [T] to [t] under the assumption that [x] has
some type [U]. Also, suppose that we have some other term [v] and
that we've shown that [v] has type [U]. Then, since [v] satisfies
the assumption we made about [x] when typing [t], we can
substitute [v] for each of the occurrences of [x] in [t] and
obtain a new term that still has type [T]. *)
(** _Lemma_: If [x|->U; Gamma |- t \in T] and [|- v \in U],
then [Gamma |- [x:=v]t \in T]. *)
Lemma substitution_preserves_typing : forall Gamma x U t v T,
x |-> U ; Gamma |- t \in T ->
empty |- v \in U ->
Gamma |- [x:=v]t \in T.
(** The substitution lemma can be viewed as a kind of "commutation
property." Intuitively, it says that substitution and typing can
be done in either order: we can either assign types to the terms
[t] and [v] separately (under suitable contexts) and then combine
them using substitution, or we can substitute first and then
assign a type to [ [x:=v] t ]; the result is the same either
way.
_Proof_: We show, by induction on [t], that for all [T] and
[Gamma], if [x|->U; Gamma |- t \in T] and [|- v \in U], then
[Gamma |- [x:=v]t \in T].
- If [t] is a variable there are two cases to consider,
depending on whether [t] is [x] or some other variable.
- If [t = x], then from the fact that [x|->U; Gamma |- x \in
T] we conclude that [U = T]. We must show that [[x:=v]x =
v] has type [T] under [Gamma], given the assumption that
[v] has type [U = T] under the empty context. This
follows from the weakening lemma.
- If [t] is some variable [y] that is not equal to [x], then
we need only note that [y] has the same type under [x|->U;
Gamma] as under [Gamma].
- If [t] is an abstraction [\y:S, t0], then [T = S->T1] and
the IH tells us, for all [Gamma'] and [T0], that if [x|->U;
Gamma' |- t0 \in T0], then [Gamma' |- [x:=v]t0 \in T0].
Moreover, by inspecting the typing rules we see it must be
the case that [y|->S; x|->U; Gamma |- t0 \in T1].
The substitution in the conclusion behaves differently
depending on whether [x] and [y] are the same variable.
First, suppose [x = y]. Then, by the definition of
substitution, [[x:=v]t = t], so we just need to show [Gamma |-
t \in T]. Using [T_Abs], we need to show that [y|->S; Gamma
|- t0 \in T1]. But we know [y|->S; x|->U; Gamma |- t0 \in T1],
and the claim follows since [x = y].
Second, suppose [x <> y]. Again, using [T_Abs],
we need to show that [y|->S; Gamma |- [x:=v]t0 \in T1].
Since [x <> y], we have
[y|->S; x|->U; Gamma = x|->U; y|->S; Gamma]. So,
we have [x|->U; y|->S; Gamma |- t0 \in T1]. Then, the
the IH applies (taking [Gamma' = y|->S; Gamma]), giving us
[y|->S; Gamma |- [x:=v]t0 \in T1], as required.
- If [t] is an application [t1 t2], the result follows
straightforwardly from the definition of substitution and the
induction hypotheses.
- The remaining cases are similar to the application case. *)
Proof.
intros Gamma x U t v T Ht Hv.
generalize dependent Gamma. generalize dependent T.
induction t; intros T Gamma H;
(* in each case, we'll want to get at the derivation of H *)
inversion H; clear H; subst; simpl; eauto.
- (* var *)
rename s into y. destruct (eqb_stringP x y); subst.
+ (* x=y *)
rewrite update_eq in H2.
injection H2 as H2; subst.
apply weakening_empty. assumption.
+ (* x<>y *)
apply T_Var. rewrite update_neq in H2; auto.
- (* abs *)
rename s into y, t into S.
destruct (eqb_stringP x y); subst; apply T_Abs.
+ (* x=y *)
rewrite update_shadow in H5. assumption.
+ (* x<>y *)
apply IHt.
rewrite update_permute; auto.
Qed.
(** One technical subtlety in the statement of the above lemma is that
we assume [v] has type [U] in the _empty_ context -- in other
words, we assume [v] is closed. (Since we are using a simple
definition of substition that is not capture-avoiding, it doesn't
make sense to substitute non-closed terms into other terms.
Fortunately, closed terms are all we need!)
*)
(** **** Exercise: 3 stars, advanced (substitution_preserves_typing_from_typing_ind)
Show that substitution_preserves_typing can also be
proved by induction on typing derivations instead
of induction on terms. *)
Lemma substitution_preserves_typing_from_typing_ind : forall Gamma x U t v T,
x |-> U ; Gamma |- t \in T ->
empty |- v \in U ->
Gamma |- [x:=v]t \in T.
Proof.
intros Gamma x U t v T Ht Hv.
remember (x |-> U; Gamma) as Gamma'.
generalize dependent Gamma.
induction Ht; intros Gamma' G; simpl; eauto;
unfold update in *.
- destruct (eqb_stringP x x0); subst.
+ rewrite t_update_eq in H. inversion H; subst.
apply weakening_empty. apply Hv.
+ rewrite t_update_neq in H by auto.
apply T_Var. apply H.
- destruct (eqb_stringP x x0); subst.
+ rewrite t_update_shadow in *.
constructor. apply Ht.
+ constructor. apply IHHt. unfold update in *.
rewrite t_update_permute by auto.
reflexivity.
Qed.
(** [] *)
(* ================================================================= *)
(** ** Main Theorem *)
(** We now have the ingredients we need to prove preservation: if a
closed term [t] has type [T] and takes a step to [t'], then [t']
is also a closed term with type [T]. In other words, the
small-step reduction relation preserves types. *)
Theorem preservation : forall t t' T,
empty |- t \in T ->
t --> t' ->
empty |- t' \in T.
(** _Proof_: By induction on the derivation of [|- t \in T].
- We can immediately rule out [T_Var], [T_Abs], [T_True], and
[T_False] as final rules in the derivation, since in each of these
cases [t] cannot take a step.
- If the last rule in the derivation is [T_App], then [t = t1 t2],
and there are subderivations showing that [|- t1 \in T2->T] and
[|- t2 \in T2] plus two induction hypotheses: (1) [t1 --> t1']
implies [|- t1' \in T2->T] and (2) [t2 --> t2'] implies [|- t2'
\in T2]. There are now three subcases to consider, one for
each rule that could be used to show that [t1 t2] takes a step
to [t'].
- If [t1 t2] takes a step by [ST_App1], with [t1] stepping to
[t1'], then, by the first IH, [t1'] has the same type as
[t1] ([|- t1' \in T2->T]), and hence by [T_App] [t1' t2] has
type [T].
- The [ST_App2] case is similar, using the second IH.
- If [t1 t2] takes a step by [ST_AppAbs], then [t1 =
\x:T0,t0] and [t1 t2] steps to [[x0:=t2]t0]; the desired
result now follows from the substitution lemma.
- If the last rule in the derivation is [T_If], then [t = if
t1 then t2 else t3], with [|- t1 \in Bool], [|- t2 \in T1], and
[|- t3 \in T1], and with three induction hypotheses: (1) [t1 -->
t1'] implies [|- t1' \in Bool], (2) [t2 --> t2'] implies [|- t2'
\in T1], and (3) [t3 --> t3'] implies [|- t3' \in T1].
There are again three subcases to consider, depending on how [t]
steps.
- If [t] steps to [t2] or [t3] by [ST_IfTrue] or
[ST_IfFalse], the result is immediate, since [t2] and [t3]
have the same type as [t].
- Otherwise, [t] steps by [ST_If], and the desired
conclusion follows directly from the first induction
hypothesis. *)
Proof with eauto.
intros t t' T HT. generalize dependent t'.
remember empty as Gamma.
induction HT;
intros t' HE; subst;
try solve [inversion HE; subst; auto].
- (* T_App *)
inversion HE; subst...
(* Most of the cases are immediate by induction,
and [eauto] takes care of them *)
+ (* ST_AppAbs *)
apply substitution_preserves_typing with T2...
inversion HT1...
Qed.
(** **** Exercise: 2 stars, standard, especially useful (subject_expansion_stlc)
An exercise in the [Types] chapter asked about the _subject
expansion_ property for the simple language of arithmetic and
boolean expressions. This property did not hold for that language,
and it also fails for STLC. That is, it is not always the case that,
if [t --> t'] and [has_type t' T], then [empty |- t \in T].
Show this by giving a counter-example that does _not involve
conditionals_.
You can state your counterexample informally in words, with a brief
explanation. *)
(* Here's a counter example:
[if true then true else (\x : Bool, x)].
Let me prove it. *)
Lemma subject_expansion_stlc_does_not_hold :
~(forall t t' T, t --> t' -> empty |- t' \in T -> empty |- t \in T).
Proof.
intro.
specialize H with
(t := <{ if true then true else (\x : Bool, x) }>)
(t' := <{ true }>)
(T := <{ Bool }>).
assert (<{ if true then true else \ x : Bool, x }> --> <{ true }>) by auto.
assert (empty |- true \in Bool) by auto.
apply (H H0) in H1; clear H; clear H0; rename H1 into H.
inversion H; subst.
inversion H7.
Qed.
(* Do not modify the following line: *)
Definition manual_grade_for_subject_expansion_stlc : option (nat*string) := None.
(** [] *)
(* ################################################################# *)
(** * Type Soundness *)
(** **** Exercise: 2 stars, standard, optional (type_soundness)
Put progress and preservation together and show that a well-typed
term can _never_ reach a stuck state. *)
Definition stuck (t:tm) : Prop :=
(normal_form step) t /\ ~ value t.
Corollary soundness : forall t t' T,
empty |- t \in T ->
t -->* t' ->
~(stuck t').
Proof.
intros t t' T Hhas_type Hmulti. unfold stuck.
intros [Hnf Hnot_val]. unfold normal_form in Hnf.
induction Hmulti.
- (* multi_refl *)
apply progress in Hhas_type. destruct Hhas_type; congruence.
- (* multi_step *)
apply IHHmulti; auto.
eapply preservation. apply Hhas_type. apply H.
Qed.
(** [] *)
(* ################################################################# *)
(** * Uniqueness of Types *)
(** **** Exercise: 3 stars, standard (unique_types)
Another nice property of the STLC is that types are unique: a
given term (in a given context) has at most one type. *)
Theorem unique_types : forall Gamma e T T',
Gamma |- e \in T ->
Gamma |- e \in T' ->
T = T'.
Proof.
intros Gamma e T T' HT HT'.
generalize dependent T'.
induction HT; intros T HT'; inversion HT'; subst; clear HT'; auto.
- rewrite H in H2. inversion H2. reflexivity.
- specialize IHHT with (T' := T0).
apply IHHT in H4. subst. auto.
- specialize IHHT2 with (T' := T3).
apply IHHT2 in H4. subst. clear IHHT2.
specialize IHHT1 with (T' := <{T3 -> T}>).
apply IHHT1 in H2. inversion H2; subst; clear H2; clear IHHT1.
reflexivity.
Qed.
(** [] *)
(* ################################################################# *)
(** * Context Invariance *)
(** A standard technical lemma of a type system is
_context invariance_. It states that typing is preserved
under "inessential changes" to the context [Gamma] -- in
particular, changes that do not affect any of the free
variables of the term. Next, we establish this property
for our system. *)
(** First, we need to define the _free variables_ in a term --
i.e., variables that are used in the term in positions
that are _not_ in the scope of an enclosing function
abstraction binding a variable of the same name.
More technically, a variable [x] _appears free in_ a term _t_
if [t] contains some occurrence of [x] that is not under
an abstraction labeled [x]. For example:
- [y] appears free, but [x] does not, in [\x:T->U, x y]
- both [x] and [y] appear free in [(\x:T->U, x y) x]
- no variables appear free in [\x:T->U, \y:T, x y]
Formally: *)
Inductive appears_free_in (x : string) : tm -> Prop :=
| afi_var : appears_free_in x <{x}>
| afi_app1 : forall t1 t2,
appears_free_in x t1 ->
appears_free_in x <{t1 t2}>
| afi_app2 : forall t1 t2,
appears_free_in x t2 ->
appears_free_in x <{t1 t2}>
| afi_abs : forall y T1 t1,
y <> x ->
appears_free_in x t1 ->
appears_free_in x <{\y:T1, t1}>
| afi_if1 : forall t1 t2 t3,
appears_free_in x t1 ->
appears_free_in x <{if t1 then t2 else t3}>
| afi_if2 : forall t1 t2 t3,
appears_free_in x t2 ->
appears_free_in x <{if t1 then t2 else t3}>
| afi_if3 : forall t1 t2 t3,
appears_free_in x t3 ->
appears_free_in x <{if t1 then t2 else t3}>.
Hint Constructors appears_free_in : core.
(** The _free variables_ of a term are just the variables that appear
free in it. A term with no free variables is said to be
_closed_. *)
Definition closed (t:tm) :=
forall x, ~ appears_free_in x t.
(** An _open_ term is one that may contain free variables. (I.e., every
term is an open term; the closed terms are a subset of the open ones.
"Open" precisely means "possibly containing free variables.") *)
(** **** Exercise: 1 star, standard (afi)
In the space below, write out the rules of the [appears_free_in]
relation in informal inference-rule notation. (Use whatever
notational conventions you like -- the point of the exercise is
just for you to think a bit about the meaning of each rule.)
Although this is a rather low-level, technical definition,
understanding it is crucial to understanding substitution and its
properties, which are really the crux of the lambda-calculus. *)
(*
Here it is:
|- free x x
free x t1 |- free x (t1 t2)
free x t2 |- free x (t1 t2)
free x t, x <> y |- free x (\y, t)
free x t1 |- free x (if t1 then t2 else t3)
free x t2 |- free x (if t1 then t2 else t3)
free x t3 |- free x (if t1 then t2 else t3)
*)
(* Do not modify the following line: *)
Definition manual_grade_for_afi : option (nat*string) := None.
(** [] *)
(** Next, we show that if a variable [x] appears free in a term [t],
and if we know [t] is well typed in context [Gamma], then it
must be the case that [Gamma] assigns a type to [x]. *)
Lemma free_in_context : forall x t T Gamma,
appears_free_in x t ->
Gamma |- t \in T ->
exists T', Gamma x = Some T'.
(** _Proof_: We show, by induction on the proof that [x] appears free
in [t], that, for all contexts [Gamma], if [t] is well typed under
[Gamma], then [Gamma] assigns some type to [x].
- If the last rule used is [afi_var], then [t = x], and from the
assumption that [t] is well typed under [Gamma] we have
immediately that [Gamma] assigns a type to [x].
- If the last rule used is [afi_app1], then [t = t1 t2] and [x]
appears free in [t1]. Since [t] is well typed under [Gamma], we
can see from the typing rules that [t1] must also be, and the IH
then tells us that [Gamma] assigns [x] a type.
- Almost all the other cases are similar: [x] appears free in a
subterm of [t], and since [t] is well typed under [Gamma], we
know the subterm of [t] in which [x] appears is well typed under
[Gamma] as well, and the IH gives us exactly the conclusion we
want.
- The only remaining case is [afi_abs]. In this case [t =
\y:T1,t1] and [x] appears free in [t1], and we also know that
[x] is different from [y]. The difference from the previous
cases is that, whereas [t] is well typed under [Gamma], its body
[t1] is well typed under [y|->T1; Gamma], so the IH allows us
to conclude that [x] is assigned some type by the extended
context [y|->T1; Gamma]. To conclude that [Gamma] assigns a
type to [x], we appeal to lemma [update_neq], noting that [x]
and [y] are different variables. *)
(** **** Exercise: 2 stars, standard (free_in_context)
Complete the following proof. *)
Proof.
intros x t T Gamma H H0. generalize dependent Gamma.
generalize dependent T.
induction H; intros; try solve [inversion H0; eauto].
inversion H1; subst; clear H1.
apply IHappears_free_in in H7. destruct H7 as [T2]; subst.
unfold update in H1. rewrite (t_update_neq _ _ _ _ _ H) in H1.
eauto.
Qed.
(** [] *)
(** From the [free_in_context] lemma, it immediately follows that any
term [t] that is well typed in the empty context is closed (it has
no free variables). *)
(** **** Exercise: 2 stars, standard, optional (typable_empty__closed) *)
Corollary typable_empty__closed : forall t T,
empty |- t \in T ->
closed t.
Proof.
intros. intro. intro. rename x0 into x.
eapply (free_in_context x t T empty H0) in H.
destruct H as [T']. inversion H.
Qed.
(** [] *)
(** Next, we establish _context_invariance_.
It is useful in cases when we have a proof of some typing relation
[Gamma |- t \in T], and we need to replace [Gamma] by a different
context [Gamma']. When is it safe to do this? Intuitively, it
must at least be the case that [Gamma'] assigns the same types as
[Gamma] to all the variables that appear free in [t]. In fact,
this is the only condition that is needed. *)
Lemma context_invariance : forall Gamma Gamma' t T,
Gamma |- t \in T ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
Gamma' |- t \in T.
(** _Proof_: By induction on the derivation of [Gamma |- t \in T].
- If the last rule in the derivation was [T_Var], then [t = x] and
[Gamma x = T]. By assumption, [Gamma' x = T] as well, and hence
[Gamma' |- t \in T] by [T_Var].
- If the last rule was [T_Abs], then [t = \y:T2, t1], with [T =
T2 -> T1] and [y|->T2; Gamma |- t1 \in T1]. The induction
hypothesis states that for any context [Gamma''], if [y|->T2;
Gamma] and [Gamma''] assign the same types to all the free
variables in [t1], then [t1] has type [T1] under [Gamma''].
Let [Gamma'] be a context which agrees with [Gamma] on the free
variables in [t]; we must show [Gamma' |- \y:T2, t1 \in T2 -> T1].
By [T_Abs], it suffices to show that [y|->T2; Gamma' |- t1 \in
T1]. By the IH (setting [Gamma'' = y|->T2;Gamma']), it
suffices to show that [y|->T2;Gamma] and [y|->T2;Gamma'] agree
on all the variables that appear free in [t1].
Any variable occurring free in [t1] must be either [y] or some
other variable. [y|->T2; Gamma] and [y|->T2; Gamma'] clearly
agree on [y]. Otherwise, note that any variable other than [y]
that occurs free in [t1] also occurs free in [t = \y:T2, t1],
and by assumption [Gamma] and [Gamma'] agree on all such
variables; hence so do [y|->T2; Gamma] and [y|->T2; Gamma'].
- If the last rule was [T_App], then [t = t1 t2], with [Gamma |-
t1 \in T2 -> T] and [Gamma |- t2 \in T2]. One induction
hypothesis states that for all contexts [Gamma'], if [Gamma']
agrees with [Gamma] on the free variables in [t1], then [t1] has
type [T2 -> T] under [Gamma']; there is a similar IH for [t2].
We must show that [t1 t2] also has type [T] under [Gamma'],
given the assumption that [Gamma'] agrees with [Gamma] on all
the free variables in [t1 t2]. By [T_App], it suffices to show
that [t1] and [t2] each have the same type under [Gamma'] as
under [Gamma]. But all free variables in [t1] are also free in
[t1 t2], and similarly for [t2]; hence the desired result
follows from the induction hypotheses. *)
(** **** Exercise: 3 stars, standard, optional (context_invariance)
Complete the following proof. *)
Proof.
intros.
generalize dependent Gamma'.
induction H; intros; auto.
- (* variable *)
constructor; rewrite <- H; symmetry; apply H0; constructor.
- (* abstraction *)
constructor; apply IHhas_type; intros.
destruct (eqb_stringP x0 x1).
+ (* x0 = x1 *)
subst. unfold update. rewrite t_update_eq. rewrite t_update_eq.
reflexivity.
+ (* x0 <> x1 *)
unfold update.
rewrite t_update_neq by auto. rewrite t_update_neq by auto.
apply H0. constructor; auto.
- (* application *)
econstructor; auto.
Qed.
(** [] *)
(* ################################################################# *)
(** * Additional Exercises *)
(** **** Exercise: 1 star, standard (progress_preservation_statement)
Without peeking at their statements above, write down the progress
and preservation theorems for the simply typed lambda-calculus (as
Coq theorems).
You can write [Admitted] for the proofs. *)
Lemma stlc_progress: forall t Gamma T,
(Gamma |- t \in T) ->
(value t \/ exists t', t --> t').
Admitted.
Lemma stlc_preservation: forall t t' Gamma T,
(Gamma |- t \in T) ->
t --> t' ->
(Gamma |- t' \in T).
Admitted.
(* checking my answer against the statement above. There is one
mismatch.
I wrote here any Gamma can be the context whereas the actual lemma
uses empty.
For stlc_progress I am wrong. t needs to be closed to be steppable or
value. Counter example: Gamma = (x |-> Bool), then Gamma |- x \in
Bool. But x being a variable has no way to step further, it is not a
value either.
For stlc_preservation, I am not sure. I cannot find any counterexample
intuitively, but let me try proving it.
*)
Lemma substitution_preserves_typing_for_any_context : forall Gamma x U t v T,
x |-> U ; Gamma |- t \in T ->
Gamma |- v \in U ->
Gamma |- [x:=v]t \in T.
Proof.
intros Gamma x U t v T Ht Hv.
remember (x |-> U; Gamma) as Gamma'.
generalize dependent Gamma.
generalize dependent v.
generalize dependent x.
induction Ht; intros x1 v Gamma' Gt Gv; try (simpl; eauto; fail);
unfold update in *.
- simpl. destruct (eqb_stringP x1 x0); subst.
+ rewrite t_update_eq in H. inversion H. subst. auto.
+ rewrite t_update_neq in H by auto. constructor. assumption.
- simpl. destruct (eqb_stringP x1 x0); subst.
+ constructor. rewrite t_update_shadow in *. assumption.
+ constructor. unfold update in *.
apply IHHt. rewrite t_update_permute by auto. reflexivity.
(* Here I'm stuck. There is no way to prove this theorem.
But I am lucky to find the way to construct a counterexample to
disprove it - check it out below. *)
Abort.
Lemma substitution_does_not_preserves_typing_when_not_closed :
~forall Gamma x U t v T,
x |-> U ; Gamma |- t \in T ->
Gamma |- v \in U ->
Gamma |- [x:=v]t \in T.
Proof.
intro.
specialize H with
(Gamma := y |-> <{Bool -> Bool}>)
(x := x)
(U := <{Bool -> Bool}>)
(t := <{\y: Bool, x}>)
(v := <{y}>)
(T := <{Bool -> Bool -> Bool}>)
.
(* Asserting Gamma |- [x:=v]t \in T. *)
assert (y |-> <{ Bool -> Bool }> |- [x := y] (\ y : Bool, x) \in (Bool -> Bool -> Bool)).
apply H; auto; fail. clear H.
inversion H0; subst; clear H0.
inversion H2; subst; clear H2.
inversion H1; subst; clear H1.
Qed.
Lemma stlc_preservation': forall t t' Gamma T,
(Gamma |- t \in T) ->
t --> t' ->
(Gamma |- t' \in T).
Proof with eauto.
intros t t' Gamma T HT. generalize dependent t'.
induction HT;
intros t' HE; subst;
try solve [inversion HE; subst; auto].
- (* T_App *)
inversion HE; subst...
(* Most of the cases are immediate by induction,
and [eauto] takes care of them *)
+ (* ST_AppAbs *)
apply substitution_preserves_typing with T2...
inversion HT1...
inversion H2; subst; clear H2;
inversion HT2; subst; clear HT2;
auto. constructor. unfold update.
(* By above reasoning, this theorem is not true.
Let me give a counterexample. *)
Abort.
Lemma stlc_preservation_does_not_hold_with_context : ~forall t t' Gamma T,
(Gamma |- t \in T) ->
t --> t' ->
(Gamma |- t' \in T).
Proof.
intro.
specialize H with
(t := <{(\x:Bool->Bool, \y:Bool, x) (\x: Bool, y true)}>)
(t' := <{\y:Bool, \x: Bool, y true}>)
(Gamma := y |-> <{Bool -> Bool}>)
(T := <{Bool -> (Bool -> Bool)}>).
assert (y |-> <{ Bool -> Bool }>
|- (\ x : Bool -> Bool, \ y : Bool, x) (\ x : Bool, y true) \in
(Bool -> Bool -> Bool)).
{ eapply T_App; auto. eapply T_Abs. eapply T_App; auto.
unfold update. rewrite t_update_permute. auto. easy.
}
assert (<{ (\ x : Bool -> Bool, \ y : Bool, x) (\ x : Bool, y true) }> -->
<{ \ y : Bool, \x: Bool, y true }>).
{ apply ST_AppAbs. auto.
}
apply (H H0) in H1; clear H H0.
inversion H1; subst; clear H1.
inversion H2; subst; clear H2.
inversion H1; subst; clear H1.
inversion H3; subst; clear H3.
unfold update in *.
rewrite t_update_permute in H1 by easy.
rewrite t_update_eq in H1. inversion H1.
Qed.
(* Do not modify the following line: *)
Definition manual_grade_for_progress_preservation_statement : option (nat*string) := None.
(** [] *)
(** **** Exercise: 2 stars, standard (stlc_variation1)
Suppose we add a new term [zap] with the following reduction rule
--------- (ST_Zap)
t --> zap
and the following typing rule:
------------------ (T_Zap)
Gamma |- zap \in T
Which of the following properties of the STLC remain truee in
the presence of these rules? For each property, write either
"remains true" or "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
becomes false. any reducible term can reduce normally or reduce to zap.
- Progress
remains true. now every term can reduce to zap.
- Preservation
remains true.
any typed expression can reduce to zap, which can have any type.
*)
(* Do not modify the following line: *)
Definition manual_grade_for_stlc_variation1 : option (nat*string) := None.
(** [] *)
(** **** Exercise: 2 stars, standard (stlc_variation2)
Suppose instead that we add a new term [foo] with the following
reduction rules:
----------------- (ST_Foo1)
(\x:A, x) --> foo
------------ (ST_Foo2)
foo --> true
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
remains true. we didn't add any other way to reduce already reducible
expression. (\x:A, x) is a value, thus not reducible.
- Progress
remains true. (\x:A, x) is a typed expression which both can reduce
further and is a value.
- Preservation
becomes false. (\x:A, x) is well typed, but it's reduced form [foo]
is not well typed.
*)
(* Do not modify the following line: *)
Definition manual_grade_for_stlc_variation2 : option (nat*string) := None.
(** [] *)
(** **** Exercise: 2 stars, standard (stlc_variation3)
Suppose instead that we remove the rule [ST_App1] from the [step]
relation. Which of the following properties of the STLC remain
true in the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
remains true. we didn't add any other way to reduce already reducible
expression.
- Progress
becomes false. now some expression is irreducible. counter example:
((if true then (\x:Bool, x) (\x:Bool, x)) true) is well typed
(T = Bool), but is not reducible nor is a value.
- Preservation
remains true. we didn't introduce extra non-typable or ill-typed terms.
*)
(* Do not modify the following line: *)
Definition manual_grade_for_stlc_variation3 : option (nat*string) := None.
(** [] *)
(** **** Exercise: 2 stars, standard, optional (stlc_variation4)
Suppose instead that we add the following new rule to the
reduction relation:
---------------------------------- (ST_FunnyIfTrue)
(if true then t1 else t2) --> true
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
becomes false. (if true then false else true) now can reduce to
both true and false.
- Progress
remains true. it's only making some expression more reducible.
- Preservation
becomes false. couterexample:
(if true then (\x:Bool, x) (\x: Bool, x)) has type (Bool -> Bool)
but it's reduction (true) has type Bool instead.
*)
(** [] *)
(** **** Exercise: 2 stars, standard, optional (stlc_variation5)
Suppose instead that we add the following new rule to the typing
relation:
Gamma |- t1 \in Bool->Bool->Bool
Gamma |- t2 \in Bool
------------------------------ (T_FunnyApp)
Gamma |- t1 t2 \in Bool
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
remains true. adding a typing rule doesn't affect step.
- Progress
becomes false. if ((\x, \y, x) true) then true else true is
well typed but cannot reduce further nor is a value.
- Preservation
becomes false. ((\x, \y, x) true) has type Bool, but it's reduction
(\y, true) has type (Bool->Bool)
*)
(** [] *)
(** **** Exercise: 2 stars, standard, optional (stlc_variation6)
Suppose instead that we add the following new rule to the typing
relation:
Gamma |- t1 \in Bool
Gamma |- t2 \in Bool
--------------------- (T_FunnyApp')
Gamma |- t1 t2 \in Bool
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
remains true. Adding typing rule doesn't affect reducibility.
- Progress
becomes false. counterexample: true true.
- Preservation
remains true. unlike variant 5, it doesn't introduce any
ill-typed extra reducible terms. true X and false Y are not reducible.
*)
(** [] *)
(** **** Exercise: 2 stars, standard, optional (stlc_variation7)
Suppose we add the following new rule to the typing relation
of the STLC:
------------------- (T_FunnyAbs)
|- \x:Bool,t \in Bool
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
remains true. Adding typing rule doesn't affect reducibility.
- Progress
becomes false. counterexample: [if (\x:Bool, true) then true else true]
is neither a value nor reducible.
- Preservation
remains true. I'm not sure about this one but I can't find a
counterexample either. (I may as well just prove it.)
Proved that preservation indeed remains true. That's funny -
both expected and unexpected :)
*)
Module variant7.
Reserved Notation "Gamma '|-' t '\in' T" (at level 101,
t custom stlc, T custom stlc at level 0).
Inductive has_type : context -> tm -> ty -> Prop :=
| T_Var : forall Gamma x T1,
Gamma x = Some T1 ->
Gamma |- x \in T1
| T_Abs : forall Gamma x T1 T2 t1,
x |-> T2 ; Gamma |- t1 \in T1 ->
Gamma |- \x:T2, t1 \in (T2 -> T1)
| T_App : forall T1 T2 Gamma t1 t2,
Gamma |- t1 \in (T2 -> T1) ->
Gamma |- t2 \in T2 ->
Gamma |- t1 t2 \in T1
| T_True : forall Gamma,
Gamma |- true \in Bool
| T_False : forall Gamma,
Gamma |- false \in Bool
| T_If : forall t1 t2 t3 T1 Gamma,
Gamma |- t1 \in Bool ->
Gamma |- t2 \in T1 ->
Gamma |- t3 \in T1 ->
Gamma |- if t1 then t2 else t3 \in T1
| T_FunnyAbs : forall x t Gamma,
Gamma |- \x:Bool, t \in Bool (* <-- NEW *)
where "Gamma '|-' t '\in' T" := (has_type Gamma t T).
Hint Constructors has_type : core.
Lemma weakening : forall Gamma Gamma' t T,
inclusion Gamma Gamma' ->
Gamma |- t \in T ->
Gamma' |- t \in T.
Proof.
intros Gamma Gamma' t T H Ht.
generalize dependent Gamma'.
induction Ht; eauto using inclusion_update.
Qed.
Lemma weakening_empty : forall Gamma t T,
empty |- t \in T ->
Gamma |- t \in T.
Proof.
intros Gamma t T.
eapply weakening.
discriminate.
Qed.
Lemma substitution_preserves_typing : forall Gamma x U t v T,
x |-> U ; Gamma |- t \in T ->
empty |- v \in U ->
Gamma |- [x:=v]t \in T.
Proof.
intros Gamma x U t v T Ht Hv.
generalize dependent Gamma. generalize dependent T.
induction t; intros T Gamma H;
(* in each case, we'll want to get at the derivation of H *)
inversion H; clear H; subst; simpl; eauto.
- (* var *)
rename s into y. destruct (eqb_stringP x y); subst.
+ (* x=y *)
rewrite update_eq in H2.
injection H2 as H2; subst.
apply weakening_empty. assumption.
+ (* x<>y *)
apply T_Var. rewrite update_neq in H2; auto.
- (* abs *)
rename s into y, t into S.
destruct (eqb_stringP x y); subst; apply T_Abs.
+ (* x=y *)
rewrite update_shadow in H5. assumption.
+ (* x<>y *)
apply IHt.
rewrite update_permute; auto.
- rename s into y, t0 into t.
destruct (eqb_stringP x y); subst.
+ apply T_FunnyAbs.
+ apply T_FunnyAbs.
Qed.
Theorem preservation : forall t t' T,
empty |- t \in T ->
t --> t' ->
empty |- t' \in T.
Proof with eauto.
intros t t' T HT. generalize dependent t'.
remember empty as Gamma.
induction HT;
intros t' HE; subst;
try solve [inversion HE; subst; auto].
- (* T_App *)
inversion HE; subst...
(* Most of the cases are immediate by induction,
and [eauto] takes care of them *)
+ (* ST_AppAbs *)
apply substitution_preserves_typing with T2...
inversion HT1...
Qed.
End variant7.
(** [] *)
End STLCProp.
(* ================================================================= *)
(** ** Exercise: STLC with Arithmetic *)
(** To see how the STLC might function as the core of a real
programming language, let's extend it with a concrete base
type of numbers and some constants and primitive
operators. *)
Module STLCArith.
Import STLC.
(** To types, we add a base type of natural numbers (and remove
booleans, for brevity). *)
Inductive ty : Type :=
| Ty_Arrow : ty -> ty -> ty
| Ty_Nat : ty.
(** To terms, we add natural number constants, along with
successor, predecessor, multiplication, and zero-testing. *)
Inductive tm : Type :=
| tm_var : string -> tm
| tm_app : tm -> tm -> tm
| tm_abs : string -> ty -> tm -> tm
| tm_const : nat -> tm
| tm_succ : tm -> tm
| tm_pred : tm -> tm
| tm_mult : tm -> tm -> tm
| tm_if0 : tm -> tm -> tm -> tm.
Notation "{ x }" := x (in custom stlc at level 1, x constr).
Notation "<{ e }>" := e (e custom stlc at level 99).
Notation "( x )" := x (in custom stlc, x at level 99).
Notation "x" := x (in custom stlc at level 0, x constr at level 0).
Notation "S -> T" := (Ty_Arrow S T) (in custom stlc at level 50, right associativity).
Notation "x y" := (tm_app x y) (in custom stlc at level 1, left associativity).
Notation "\ x : t , y" :=
(tm_abs x t y) (in custom stlc at level 90, x at level 99,
t custom stlc at level 99,
y custom stlc at level 99,
left associativity).
Coercion tm_var : string >-> tm.
Notation "'Nat'" := Ty_Nat (in custom stlc at level 0).
Notation "'succ' x" := (tm_succ x) (in custom stlc at level 0,
x custom stlc at level 0).
Notation "'pred' x" := (tm_pred x) (in custom stlc at level 0,
x custom stlc at level 0).
Notation "x * y" := (tm_mult x y) (in custom stlc at level 1,
left associativity).
Notation "'if0' x 'then' y 'else' z" :=
(tm_if0 x y z) (in custom stlc at level 89,
x custom stlc at level 99,
y custom stlc at level 99,
z custom stlc at level 99,
left associativity).
Coercion tm_const : nat >-> tm.
(** **** Exercise: 5 stars, standard (stlc_arith)
Finish formalizing the definition and properties of the STLC
extended with arithmetic. This is a longer exercise. Specifically:
1. Copy the core definitions for STLC that we went through,
as well as the key lemmas and theorems, and paste them
into the file at this point. Do not copy examples, exercises,
etc. (In particular, make sure you don't copy any of the []
comments at the end of exercises, to avoid confusing the
autograder.)
You should copy over five definitions:
- Fixpoint susbt
- Inductive value
- Inductive step
- Inductive has_type
- Inductive appears_free_in
And five theorems, with their proofs:
- Lemma weakening
- Lemma weakening_empty
- Lemma substitution_preserves_typing
- Theorem preservation
- Theorem progress
It will be helpful to also copy over "Reserved Notation",
"Notation", and "Hint Constructors" for these things.
2. Edit and extend the four definitions (subst, value, step,
and has_type) so they are appropriate for the new STLC
extended with arithmetic.
3. Extend the proofs of all the five properties of the original
STLC to deal with the new syntactic forms. Make sure Coq
accepts the whole file. *)
Reserved Notation "'[' x ':=' s ']' t" (in custom stlc at level 20, x constr).
Fixpoint subst (x : string) (s : tm) (t : tm) : tm :=
match t with
| tm_var y =>
if eqb_string x y then s else t
| <{\y:T, t1}> =>
if eqb_string x y then t else <{\y:T, [x:=s] t1}>
| <{t1 t2}> =>
<{([x:=s] t1) ([x:=s] t2)}>
| tm_const n => tm_const n
| <{ succ t }> => <{succ [x:=s]t}>
| <{ pred t }> => <{pred [x:=s]t}>
| <{ t1*t2 }> => <{([x:=s]t1) * ([x:=s]t2)}>
| <{if0 t1 then t2 else t3}> =>
<{if0 ([x:=s] t1) then ([x:=s] t2) else ([x:=s] t3)}>
end
where "'[' x ':=' s ']' t" := (subst x s t) (in custom stlc).
Inductive value : tm -> Prop :=
| v_abs : forall x T2 t1,
value <{\x:T2, t1}>
| v_const : forall n:nat,
value <{ n }>.
Hint Constructors value : core.
Reserved Notation "t '-->' t'" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_AppAbs : forall x T2 t1 v2,
value v2 ->
<{(\x:T2, t1) v2}> --> <{ [x:=v2]t1 }>
| ST_App1 : forall t1 t1' t2,
t1 --> t1' ->
<{t1 t2}> --> <{t1' t2}>
| ST_App2 : forall v1 t2 t2',
value v1 ->
t2 --> t2' ->
<{v1 t2}> --> <{v1 t2'}>
| ST_SuccConst : forall (n : nat),
<{succ n}> --> tm_const (S n)
| ST_Succ : forall t t',
t --> t' ->
<{succ t}> --> <{succ t'}>
| ST_PredConst : forall (n : nat),
<{pred n}> --> tm_const (PeanoNat.Nat.pred n)
| ST_Pred : forall t t',
t --> t' ->
<{pred t}> --> <{pred t'}>
| ST_MultConst : forall (a b : nat),
<{a * b}> --> tm_const (a * b)
| ST_Mult1 : forall t2 t1 t1',
t1 --> t1' ->
<{t1 * t2}> --> <{t1' * t2}>
| ST_Mult2 : forall (a : nat) t t',
t --> t' ->
<{a * t}> --> <{a * t'}>
| ST_If0 : forall t1 t2,
<{if0 0 then t1 else t2}> --> t1
| ST_IfNon0 : forall (n : nat) t1 t2,
n <> 0 ->
<{if0 n then t1 else t2}> --> t2
| ST_If : forall t1 t1' t2 t3,
t1 --> t1' ->
<{if0 t1 then t2 else t3}> --> <{if0 t1' then t2 else t3}>
where "t '-->' t'" := (step t t').
Hint Constructors step : core.
Definition context := partial_map ty.
Reserved Notation "Gamma '|-' t '\in' T"
(at level 101, t custom stlc, T custom stlc at level 0).
Inductive has_type : context -> tm -> ty -> Prop :=
| T_Var : forall Gamma x T1,
Gamma x = Some T1 ->
Gamma |- x \in T1
| T_Abs : forall Gamma x T1 T2 t1,
x |-> T2 ; Gamma |- t1 \in T1 ->
Gamma |- \x:T2, t1 \in (T2 -> T1)
| T_App : forall T1 T2 Gamma t1 t2,
Gamma |- t1 \in (T2 -> T1) ->
Gamma |- t2 \in T2 ->
Gamma |- t1 t2 \in T1
| T_Const : forall Gamma (n : nat),
Gamma |- n \in Nat
| T_Succ : forall Gamma t,
(Gamma |- t \in Nat) ->
(Gamma |- succ t \in Nat)
| T_Pred : forall Gamma t,
(Gamma |- t \in Nat) ->
(Gamma |- pred t \in Nat)
| T_Mult : forall Gamma t t',
(Gamma |- t \in Nat) ->
(Gamma |- t' \in Nat) ->
(Gamma |- t * t' \in Nat)
| T_If0 : forall t1 t2 t3 T1 Gamma,
Gamma |- t1 \in Nat ->
Gamma |- t2 \in T1 ->
Gamma |- t3 \in T1 ->
Gamma |- if0 t1 then t2 else t3 \in T1
where "Gamma '|-' t '\in' T" := (has_type Gamma t T).
Hint Constructors has_type : core.
Inductive appears_free_in (x : string) : tm -> Prop :=
| afi_var : appears_free_in x <{x}>
| afi_app1 : forall t1 t2,
appears_free_in x t1 ->
appears_free_in x <{t1 t2}>
| afi_app2 : forall t1 t2,
appears_free_in x t2 ->
appears_free_in x <{t1 t2}>
| afi_abs : forall y T1 t1,
y <> x ->
appears_free_in x t1 ->
appears_free_in x <{\y:T1, t1}>
| afi_if1 : forall t1 t2 t3,
appears_free_in x t1 ->
appears_free_in x <{if0 t1 then t2 else t3}>
| afi_if2 : forall t1 t2 t3,
appears_free_in x t2 ->
appears_free_in x <{if0 t1 then t2 else t3}>
| afi_if3 : forall t1 t2 t3,
appears_free_in x t3 ->
appears_free_in x <{if0 t1 then t2 else t3}>
| afi_succ : forall t,
appears_free_in x t ->
appears_free_in x <{succ t}>
| afi_pred : forall t,
appears_free_in x t ->
appears_free_in x <{pred t}>
| afi_mult1 : forall t t',
appears_free_in x t ->
appears_free_in x <{t * t'}>
| afi_mult2 : forall t t',
appears_free_in x t' ->
appears_free_in x <{t * t'}>
.
Hint Constructors appears_free_in : core.
Lemma weakening : forall Gamma Gamma' t T,
inclusion Gamma Gamma' ->
Gamma |- t \in T ->
Gamma' |- t \in T.
Proof.
intros Gamma Gamma' t T H Ht.
generalize dependent Gamma'.
induction Ht; eauto using inclusion_update.
Qed.
Lemma weakening_empty : forall Gamma t T,
empty |- t \in T ->
Gamma |- t \in T.
Proof.
intros Gamma t T.
eapply weakening.
discriminate.
Qed.
Lemma substitution_preserves_typing : forall Gamma x U t v T,
x |-> U ; Gamma |- t \in T ->
empty |- v \in U ->
Gamma |- [x:=v]t \in T.
Proof.
intros Gamma x U t v T Ht Hv.
generalize dependent Gamma. generalize dependent T.
induction t; intros T Gamma H;
(* in each case, we'll want to get at the derivation of H *)
inversion H; clear H; subst; simpl; eauto.
- (* var *)
rename s into y. destruct (eqb_stringP x y); subst.
+ (* x=y *)
rewrite update_eq in H2.
injection H2 as H2; subst.
apply weakening_empty. assumption.
+ (* x<>y *)
apply T_Var. rewrite update_neq in H2; auto.
- (* abs *)
rename s into y, t into S.
destruct (eqb_stringP x y); subst; apply T_Abs.
+ (* x=y *)
rewrite update_shadow in H5. assumption.
+ (* x<>y *)
apply IHt.
rewrite update_permute; auto.
Qed.
Theorem preservation : forall t t' T,
empty |- t \in T ->
t --> t' ->
empty |- t' \in T.
Proof with eauto.
intros t t' T HT. generalize dependent t'.
remember empty as Gamma.
induction HT;
intros t'' HE; subst;
try solve [inversion HE; subst; auto].
- (* T_App *)
inversion HE; subst...
(* Most of the cases are immediate by induction,
and [eauto] takes care of them *)
+ (* ST_AppAbs *)
apply substitution_preserves_typing with T2...
inversion HT1...
Qed.
Lemma canonical_forms_nat : forall t,
empty |- t \in Nat ->
value t ->
exists n, t = tm_const n.
Proof.
intros t HT HVal.
destruct HVal; eauto.
inversion HT.
Qed.
Lemma canonical_forms_fun : forall t T1 T2,
empty |- t \in (T1 -> T2) ->
value t ->
exists x u, t = <{\x:T1, u}>.
Proof.
intros t T1 T2 HT HVal.
destruct HVal; inversion HT; subst.
exists x0, t1. reflexivity.
Qed.
Theorem progress : forall t T,
empty |- t \in T ->
value t \/ exists t', t --> t'.
Proof with eauto.
intros t T Ht.
remember empty as Gamma.
induction Ht; subst Gamma; auto.
(* auto solves all three cases in which t is a value *)
- (* T_Var *)
(* contradictory: variables cannot be typed in an
empty context *)
discriminate H.
- (* T_App *)
(* [t] = [t1 t2]. Proceed by cases on whether [t1] is a
value or steps... *)
right. destruct IHHt1...
+ (* t1 is a value *)
destruct IHHt2...
* (* t2 is also a value *)
eapply canonical_forms_fun in Ht1; [|assumption].
destruct Ht1 as [x [t0 H1]]. subst.
exists (<{ [x:=t2]t0 }>)...
* (* t2 steps *)
destruct H0 as [t2' Hstp]. exists (<{t1 t2'}>)...
+ (* t1 steps *)
destruct H as [t1' Hstp]. exists (<{t1' t2}>)...
- (* T_Succ *)
destruct IHHt; auto.
+ apply canonical_forms_nat in Ht; auto. inversion Ht; subst; clear Ht.
eauto.
+ right. destruct H. eauto.
- (* T_Pred *)
destruct IHHt; auto.
+ apply canonical_forms_nat in Ht; auto. inversion Ht; subst; clear Ht.
eauto.
+ right. destruct H. eauto.
- (* T_Mult *)
destruct IHHt1; destruct IHHt2; auto.
+ apply canonical_forms_nat in H; auto;
apply canonical_forms_nat in H0; auto.
destruct H; destruct H0; subst.
eauto.
+ apply canonical_forms_nat in H; auto.
destruct H; destruct H0; subst.
eauto.
+ destruct H. eauto.
+ destruct H. destruct H0. eauto.
- (* T_If *)
right. destruct IHHt1...
+ (* t1 is a value *)
destruct (canonical_forms_nat t1 Ht1); auto; subst.
destruct x0; eauto.
+ (* t1 also steps *)
destruct H as [t1' Hstp]. exists <{if0 t1' then t2 else t3}>...
Qed.
(* Do not modify the following line: *)
Definition manual_grade_for_stlc_arith : option (nat*string) := None.
(** [] *)
End STLCArith.
(* 2020-09-09 21:08 *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2BB2A_2_V
`define SKY130_FD_SC_MS__O2BB2A_2_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog wrapper for o2bb2a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o2bb2a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o2bb2a_2 (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o2bb2a base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o2bb2a_2 (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o2bb2a base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2BB2A_2_V
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : 2D Cache Control
// File : ded_cactrl.v
// Author : Jim MacLeod
// Created : 30-Dec-2008
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module ded_cactrl
#(parameter BYTES = 4)
(
/* host bus input signals */
input de_clk, /* draw engine clock. */
input de_rstn, /* draw engine reset. */
input mc_push, // MC push to the 2d cache
input read_4,
/* memory controller input signals */
input mclock, /* Memory controller clock. */
input mc_popen, /* Memory controller pop enable.*/
input mc_acken, /* Memory controller ack enable.*/
/* execution unit input signals */
input irst_wad, // load start write address
input ld_rad, // load start read address
input ld_rad_e, // load start read address
input [9:0] x_adr, // lower seven bits from the X ALU
input [8:0] srcx, // lower five bits from the dest X
input [4:0] dsty, // lower five bits from the dest Y
input [6:0] dstx, // lower five bits from the dest Y
input lt_actv_4, // triangle active.
input [1:0] stpl_2, // stipple bit level two.
input [1:0] stpl_4, // stipple bit level three.
input [1:0] apat_2, // Area mode 01 = 8x8, 10=32x32.
input [1:0] apat_4, // Area mode level three
input [2:0] psize_4, // pixel size level three.
input ps8_2, // pixel size level two.
input ps16_2, // pixel size level two.
input ps32_2, // pixel size level two.
input eol_4, // End of line indicator
input mc_eop, // end of page one cycle early
input [2:0] ofset, // host ofset.
input [2:0] frst8_4,
input sol_3, // sol_3.
input mem_req, // mem_req.
input mem_rd, // mem_rd.
input mc_read_4,
input [4:0] xpat_ofs,
input [4:0] ypat_ofs,
input ca_src_2,
input rad_flg_3,
input [2:0] strt_wrd_3,
input [3:0] strt_byt_3,
input [2:0] strt_bit_3,
input [2:0] strt_wrd_4,
input [3:0] strt_byt_4,
input [2:0] strt_bit_4,
input rst_wad_flg_3,
output rad_flg_2,
output [2:0] strt_wrd_2,
output [3:0] strt_byt_2,
output [2:0] strt_bit_2,
output reg rst_wad_flg_2,
output [9:0] ca_rad, // cache read address.
`ifdef BYTE16 output reg [2:0] ca_mc_addr
`elsif BYTE8 output reg [3:0] ca_mc_addr
`else output reg [4:0] ca_mc_addr
`endif
);
wire [9:0] rad_cnt; /* cache read counter address. */
reg xyw_csn_d; /* delayed chip select. */
reg xyw_rdyn_d; /* delayed ready. */
reg xyw_rdyn_dd; /* delayed ready. */
wire [1:0] ca_shf_adr;
wire rstflgn; /* reset wad. */
reg irstn;
always @(posedge de_clk or negedge de_rstn) begin
if(!de_rstn) rst_wad_flg_2 <= 1'b0;
else if(irst_wad) rst_wad_flg_2 <= 1'b1;
else if(mem_req) rst_wad_flg_2 <= 1'b0;
end
assign ca_rad[9:0] = rad_cnt[9:0];
/**************************************************************************/
/* CACHE WRITE CONTROLLER */
/**************************************************************************/
always @(posedge mclock or negedge de_rstn)
begin
if(!de_rstn) ca_mc_addr <= 3'b000;
else if (mc_acken & rst_wad_flg_3) ca_mc_addr <= 3'b000;
else if (mc_push) ca_mc_addr <= ca_mc_addr + 3'b001;
end
/**************************************************************************/
/* CACHE READ CONTROLLER */
/**************************************************************************/
ded_cactrl_rd #
(
.BYTES (BYTES)
)
u_ded_cactrl_rd
(
.de_rstn (de_rstn),
.de_clk (de_clk),
.mc_read_4 (mc_read_4),
.ld_rad (ld_rad),
.ld_rad_e (ld_rad_e),
.mclock (mclock),
.mc_popen (mc_popen),
.mc_acken (mc_acken),
.din (x_adr),
.srcx (srcx),
.dsty (dsty),
.dstx (dstx),
.stpl_2 (stpl_2),
.stpl_4 (stpl_4),
.apat_2 (apat_2),
.apat_4 (apat_4),
.ps8_2 (ps8_2),
.ps16_2 (ps16_2),
.ps32_2 (ps32_2),
.psize_4 (psize_4),
.lt_actv_4 (lt_actv_4),
.eol_4 (eol_4),
.mc_eop (mc_eop),
.ofset (ofset),
.frst8_4 (frst8_4),
.sol_3 (sol_3),
.mem_req (mem_req),
.mem_rd (mem_rd),
.xpat_ofs (xpat_ofs),
.ypat_ofs (ypat_ofs),
.ca_src_2 (ca_src_2),
.rad_flg_3 (rad_flg_3),
.strt_wrd_3 (strt_wrd_3),
.strt_byt_3 (strt_byt_3),
.strt_bit_3 (strt_bit_3),
.strt_wrd_4 (strt_wrd_4),
.strt_byt_4 (strt_byt_4),
.strt_bit_4 (strt_bit_4),
.rad_flg_2 (rad_flg_2),
.strt_wrd_2 (strt_wrd_2),
.strt_byt_2 (strt_byt_2),
.strt_bit_2 (strt_bit_2),
.rad (rad_cnt)
);
endmodule
|
// Name: WcaDCOffset.v
//
// Copyright(c) 2013 Loctronix Corporation
// http://www.loctronix.com
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
module WcaDcOffset (
input clock,
input reset,
input strobe,
input iqSel,
input signed [11:0] sig_in, //signal input.
output signed [11:0] dcoffset, //DC Offset measurement / scaled to 16 bits for higher resolution.
output signed [11:0] sigout //Adjusted output signal with DC bias removed.
);
/* //Implement a scaled integrator.
reg signed [31:0] integrator[0:1];
assign dcoffset = integrator[iqSel][31:20];
assign sigout = sig_in - dcoffset;
wire [31:0] update = integrator[iqSel][31:0] + {{(20){sigout[11]}},sigout};
always @(posedge clock)
begin
if(reset)
begin
integrator[0] <= #1 32'd0;
integrator[1] <= #1 32'd0;
end
else if(strobe)
if( iqSel) integrator[1][31:0] <= #1 update;
else integrator[0][31:0] <= #1 update;
end */
/* //Implement a scaled integrator.
reg signed [25:0] integrator;
assign dcoffset = integrator[25:14];
assign sigout = (iqSel) ? (sig_in - dcoffset) : dcoffset;
wire signed [25:0] update = integrator + {{(14){sigout[11]}},sigout};
always @(posedge clock)
begin
if(reset)
begin
integrator <= #1 16'd0;
end
else if(iqSel)
integrator<= #1 update;
end
*/
//Implement a scaled integrator.
reg signed [25:0] integrator[1:0];
assign dcoffset = integrator[iqSel][25:14];
assign sigout = sig_in - dcoffset;
wire signed [25:0] update = integrator[iqSel] + {{(14){sigout[11]}},sigout};
always @(negedge clock)
begin
if(reset)
begin
integrator[0] <= #1 26'd0;
integrator[1] <= #1 26'd0;
end
else if(strobe)
integrator[iqSel] <= #1 update;
end
/* reg signed [25:0] integrator;
assign dcoffset = integrator[25:14];
assign sigout = (iqSel) ? (sig_in - dcoffset) : sig_in;
wire signed [25:0] update = integrator + {{(14){sigout[11]}},sigout};
always @(negedge clock)
begin
if(reset)
begin
integrator <= #1 16'd0;
end
else if(iqSel)
integrator<= #1 update;
end */
endmodule // WcaDcOffset
|
`timescale 1 ps / 1 ps
module ov7670_marker_tracker_ip_v1_0_S00_AXI #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Width of S_AXI data bus
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of S_AXI address bus
parameter integer C_S_AXI_ADDR_WIDTH = 4
)
(
// Users to add ports here
output intr,
input [7:0]OV7670_D,
input OV7670_HREF,
input OV7670_PCLK,
output OV7670_PWDN,
output OV7670_RESET,
output OV7670_SIOC,
inout OV7670_SIOD,
input OV7670_VSYNC,
output OV7670_XCLK,
// User ports ends
// Do not modify the ports beyond this line
// Global Clock Signal
input wire S_AXI_ACLK,
// Global Reset Signal. This Signal is Active LOW
input wire S_AXI_ARESETN,
// Write address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
// Write channel Protection type. This signal indicates the
// privilege and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_AWPROT,
// Write address valid. This signal indicates that the master signaling
// valid write address and control information.
input wire S_AXI_AWVALID,
// Write address ready. This signal indicates that the slave is ready
// to accept an address and associated control signals.
output wire S_AXI_AWREADY,
// Write data (issued by master, acceped by Slave)
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
// Write strobes. This signal indicates which byte lanes hold
// valid data. There is one write strobe bit for each eight
// bits of the write data bus.
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
// Write valid. This signal indicates that valid write
// data and strobes are available.
input wire S_AXI_WVALID,
// Write ready. This signal indicates that the slave
// can accept the write data.
output wire S_AXI_WREADY,
// Write response. This signal indicates the status
// of the write transaction.
output wire [1 : 0] S_AXI_BRESP,
// Write response valid. This signal indicates that the channel
// is signaling a valid write response.
output wire S_AXI_BVALID,
// Response ready. This signal indicates that the master
// can accept a write response.
input wire S_AXI_BREADY,
// Read address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether the
// transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_ARPROT,
// Read address valid. This signal indicates that the channel
// is signaling valid read address and control information.
input wire S_AXI_ARVALID,
// Read address ready. This signal indicates that the slave is
// ready to accept an address and associated control signals.
output wire S_AXI_ARREADY,
// Read data (issued by slave)
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
// Read response. This signal indicates the status of the
// read transfer.
output wire [1 : 0] S_AXI_RRESP,
// Read valid. This signal indicates that the channel is
// signaling the required read data.
output wire S_AXI_RVALID,
// Read ready. This signal indicates that the master can
// accept the read data and response information.
input wire S_AXI_RREADY
);
reg intr_reg;
wire [16:0] marker_x, marker_y;
wire update_tracker_pos;
// AXI4LITE signals
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [1 : 0] axi_bresp;
reg axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
reg axi_arready;
reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
reg [1 : 0] axi_rresp;
reg axi_rvalid;
// Example-specific design signals
// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
// ADDR_LSB is used for addressing 32/64 bit registers/memories
// ADDR_LSB = 2 for 32 bits (n downto 2)
// ADDR_LSB = 3 for 64 bits (n downto 3)
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
localparam integer OPT_MEM_ADDR_BITS = 1;
//----------------------------------------------
//-- Signals for user logic register space example
//------------------------------------------------
//-- Number of Slave Registers 4
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3;
wire slv_reg_rden;
wire slv_reg_wren;
reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
integer byte_index;
// I/O Connections assignments
assign intr = intr_reg;
assign S_AXI_AWREADY = axi_awready;
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BRESP = axi_bresp;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_ARREADY = axi_arready;
assign S_AXI_RDATA = axi_rdata;
assign S_AXI_RRESP = axi_rresp;
assign S_AXI_RVALID = axi_rvalid;
// Implement axi_awready generation
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awready <= 1'b0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
begin
// slave is ready to accept write address when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_awready <= 1'b1;
end
else
begin
axi_awready <= 1'b0;
end
end
end
// Implement axi_awaddr latching
// This process is used to latch the address when both
// S_AXI_AWVALID and S_AXI_WVALID are valid.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awaddr <= 0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
begin
// Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end
end
end
// Implement axi_wready generation
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_wready <= 1'b0;
end
else
begin
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID)
begin
// slave is ready to accept write data when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_wready <= 1'b1;
end
else
begin
axi_wready <= 1'b0;
end
end
end
// Implement memory mapped register select and write logic generation
// The write data is accepted and written to memory mapped registers when
// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
// select byte enables of slave registers while writing.
// These registers are cleared when reset (active low) is applied.
// Slave register write enable is asserted when valid address and data are available
// and the slave is ready to accept the write address and write data.
assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
slv_reg0 <= 0;
slv_reg1 <= 0;
slv_reg2 <= 0;
slv_reg3 <= 0;
end
else begin
if (slv_reg_wren)
begin
case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
2'h0:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 0
slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
2'h1:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 1
slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
2'h2:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 2
slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
2'h3:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 3
slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
default : begin
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
end
endcase
end
end
end
// Implement write response logic generation
// The write response and response valid signals are asserted by the slave
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
// This marks the acceptance of address and indicates the status of
// write transaction.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
end
else
begin
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
begin
// indicates a valid write response is available
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0; // 'OKAY' response
end // work error responses in future
else
begin
if (S_AXI_BREADY && axi_bvalid)
//check if bready is asserted while bvalid is high)
//(there is a possibility that bready is always asserted high)
begin
axi_bvalid <= 1'b0;
end
end
end
end
// Implement axi_arready generation
// axi_arready is asserted for one S_AXI_ACLK clock cycle when
// S_AXI_ARVALID is asserted. axi_awready is
// de-asserted when reset (active low) is asserted.
// The read address is also latched when S_AXI_ARVALID is
// asserted. axi_araddr is reset to zero on reset assertion.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_arready <= 1'b0;
axi_araddr <= 32'b0;
end
else
begin
if (~axi_arready && S_AXI_ARVALID)
begin
// indicates that the slave has acceped the valid read address
axi_arready <= 1'b1;
// Read address latching
axi_araddr <= S_AXI_ARADDR;
end
else
begin
axi_arready <= 1'b0;
end
end
end
// Implement axi_arvalid generation
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
// data are available on the axi_rdata bus at this instance. The
// assertion of axi_rvalid marks the validity of read data on the
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
// is deasserted on reset (active low). axi_rresp and axi_rdata are
// cleared to zero on reset (active low).
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rvalid <= 0;
axi_rresp <= 0;
end
else
begin
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
begin
// Valid read data is available at the read data bus
axi_rvalid <= 1'b1;
axi_rresp <= 2'b0; // 'OKAY' response
end
else if (axi_rvalid && S_AXI_RREADY)
begin
// Read data is accepted by the master
axi_rvalid <= 1'b0;
end
end
end
// Implement memory mapped register select and read logic generation
// Slave register read enable is asserted when valid address is available
// and the slave is ready to accept the read address.
assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
always @(*)
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
reg_data_out <= 0;
end
else
begin
// Address decoding for reading registers
case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
2'h0 : reg_data_out <= slv_reg0;
2'h1 : reg_data_out <= slv_reg1;
2'h2 : reg_data_out <= {15'b0, marker_x};//slv_reg2;
2'h3 : reg_data_out <= {15'b0, marker_y}; //slv_reg3;
default : reg_data_out <= 0;
endcase
end
end
// Output register or memory read data
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rdata <= 0;
end
else
begin
// When there is a valid read address (S_AXI_ARVALID) with
// acceptance of read address by the slave (axi_arready),
// output the read dada
if (slv_reg_rden)
begin
axi_rdata <= reg_data_out; // register read data
end
end
end
always@(posedge S_AXI_ACLK)
if(update_tracker_pos == 1 && slv_reg1[2])
intr_reg <= 1;
else
intr_reg <= 0;
// Add user logic here
//reg_intr
design_2_wrapper d(
.Config_Done(),
.OV7670_D,
.OV7670_HREF,
.OV7670_PCLK,
.OV7670_PWDN,
.OV7670_RESET,
.OV7670_SIOC,
.OV7670_SIOD,
.OV7670_VSYNC,
.OV7670_XCLK,
.clock_rtl(S_AXI_ACLK),
.go(slv_reg1[0]),
.marker_x(marker_x),
.marker_y(marker_y),
.resend_cam_config(slv_reg1[1]),
.reset_rtl(!S_AXI_ARESETN),
.track_clr(slv_reg0[20:0]),
.update_tracker_pos(update_tracker_pos)
);
// User logic ends
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A221OI_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__A221OI_FUNCTIONAL_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__a221oi (
Y ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Local signals
wire and0_out ;
wire and1_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
nor nor0 (nor0_out_Y, and0_out, C1, and1_out);
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A221OI_FUNCTIONAL_V |
// cog
// 2014_08_10 - added patch for reset problem - PIK33/CGRACEY
/*
-------------------------------------------------------------------------------
Copyright 2014 Parallax Inc.
This file is part of the hardware description for the Propeller 1 Design.
The Propeller 1 Design is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by the
Free Software Foundation, either version 3 of the License, or (at your option)
any later version.
The Propeller 1 Design is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
the Propeller 1 Design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
ADD
instruction mnem oper R C Z +- C D S
----------------------------------------------------------------------------
000000 ZC0ICCCC DDDDDDDDD SSSSSSSSS WRBYTE D,S _______ __________
000000 ZC1ICCCC DDDDDDDDD SSSSSSSSS RDBYTE D,S B______ __________
000001 ZC0ICCCC DDDDDDDDD SSSSSSSSS WRWORD D,S _______ __________
000001 ZC1ICCCC DDDDDDDDD SSSSSSSSS RDWORD D,S B______ __________
000010 ZC0ICCCC DDDDDDDDD SSSSSSSSS WRLONG D,S _______ __________
000010 ZC1ICCCC DDDDDDDDD SSSSSSSSS RDLONG D,S B______ __________
000011 ZCRICCCC DDDDDDDDD SSSSSSSSS SYSOP D,S B__B___ __________
000100 ZCRICCCC DDDDDDDDD SSSSSSSSS * <MUL> D,S M__M__Z __________
000101 ZCRICCCC DDDDDDDDD SSSSSSSSS * <MULS> D,S M__M__Z __________
000110 ZCRICCCC DDDDDDDDD SSSSSSSSS * <ENC> D,S E_____Z __________
000111 ZCRICCCC DDDDDDDDD SSSSSSSSS * <ONES> D,S E_____Z __________
001000 ZCRICCCC DDDDDDDDD SSSSSSSSS ROR D,S R__R__Z __________
001001 ZCRICCCC DDDDDDDDD SSSSSSSSS ROL D,S R__R__Z __________
001010 ZCRICCCC DDDDDDDDD SSSSSSSSS SHR D,S R__R__Z __________
001011 ZCRICCCC DDDDDDDDD SSSSSSSSS SHL D,S R__R__Z __________
001100 ZCRICCCC DDDDDDDDD SSSSSSSSS RCR D,S R__R__Z __________
001101 ZCRICCCC DDDDDDDDD SSSSSSSSS RCL D,S R__R__Z __________
001110 ZCRICCCC DDDDDDDDD SSSSSSSSS SAR D,S R__R__Z __________
001111 ZCRICCCC DDDDDDDDD SSSSSSSSS REV D,S R__R__Z __________
010000 ZCRICCCC DDDDDDDDD SSSSSSSSS MINS D,S L__As_Z 1__0__1__1
010001 ZCRICCCC DDDDDDDDD SSSSSSSSS MAXS D,S L__As_Z 1__0__1__1
010010 ZCRICCCC DDDDDDDDD SSSSSSSSS MIN D,S L__Au_Z 1__0__1__1
010011 ZCRICCCC DDDDDDDDD SSSSSSSSS MAX D,S L__Au_Z 1__0__1__1
010100 ZCRICCCC DDDDDDDDD SSSSSSSSS MOVS D,S L______ __________
010101 ZCRICCCC DDDDDDDDD SSSSSSSSS MOVD D,S L______ __________
010110 ZCRICCCC DDDDDDDDD SSSSSSSSS MOVI D,S L______ __________
010111 ZCRICCCC DDDDDDDDD SSSSSSSSS JMPRET D,S L______ __________
011000 ZCRICCCC DDDDDDDDD SSSSSSSSS AND D,S L__L__Z __________
011001 ZCRICCCC DDDDDDDDD SSSSSSSSS ANDN D,S L__L__Z __________
011010 ZCRICCCC DDDDDDDDD SSSSSSSSS OR D,S L__L__Z __________
011011 ZCRICCCC DDDDDDDDD SSSSSSSSS XOR D,S L__L__Z __________
011100 ZCRICCCC DDDDDDDDD SSSSSSSSS MUXC D,S L__L__Z __________
011101 ZCRICCCC DDDDDDDDD SSSSSSSSS MUXNC D,S L__L__Z __________
011110 ZCRICCCC DDDDDDDDD SSSSSSSSS MUXZ D,S L__L__Z __________
011111 ZCRICCCC DDDDDDDDD SSSSSSSSS MUXNZ D,S L__L__Z __________
100000 ZCRICCCC DDDDDDDDD SSSSSSSSS ADD D,S A__Au_Z 0__0__1__1
100001 ZCRICCCC DDDDDDDDD SSSSSSSSS SUB D,S A__Au_Z 1__0__1__1
100010 ZCRICCCC DDDDDDDDD SSSSSSSSS ADDABS D,S A__Au_Z M__0__1__1
100011 ZCRICCCC DDDDDDDDD SSSSSSSSS SUBABS D,S A__Au_Z Mn_0__1__1
100100 ZCRICCCC DDDDDDDDD SSSSSSSSS SUMC D,S A__Ao_Z C__0__1__1
100101 ZCRICCCC DDDDDDDDD SSSSSSSSS SUMNC D,S A__Ao_Z Cn_0__1__1
100110 ZCRICCCC DDDDDDDDD SSSSSSSSS SUMZ D,S A__Ao_Z Z__0__1__1
100111 ZCRICCCC DDDDDDDDD SSSSSSSSS SUMNZ D,S A__Ao_Z Zn_0__1__1
101000 ZCRICCCC DDDDDDDDD SSSSSSSSS MOV D,S A__Am_Z 0__0__0__1
101001 ZCRICCCC DDDDDDDDD SSSSSSSSS NEG D,S A__Am_Z 1__0__0__1
101010 ZCRICCCC DDDDDDDDD SSSSSSSSS ABS D,S A__Am_Z M__0__0__1
101011 ZCRICCCC DDDDDDDDD SSSSSSSSS ABSNEG D,S A__Am_Z Mn_0__0__1
101100 ZCRICCCC DDDDDDDDD SSSSSSSSS NEGC D,S A__Am_Z C__0__0__1
101101 ZCRICCCC DDDDDDDDD SSSSSSSSS NEGNC D,S A__Am_Z Cn_0__0__1
101110 ZCRICCCC DDDDDDDDD SSSSSSSSS NEGZ D,S A__Am_Z Z__0__0__1
101111 ZCRICCCC DDDDDDDDD SSSSSSSSS NEGNZ D,S A__Am_Z Zn_0__0__1
110000 ZCRICCCC DDDDDDDDD SSSSSSSSS CMPS D,S A__As_Z 1__0__1__1
110001 ZCRICCCC DDDDDDDDD SSSSSSSSS CMPSX D,S A__As_Z& 1__C__1__1
110010 ZCRICCCC DDDDDDDDD SSSSSSSSS ADDX D,S A__Au_Z& 0__C__1__1
110011 ZCRICCCC DDDDDDDDD SSSSSSSSS SUBX D,S A__Au_Z& 1__C__1__1
110100 ZCRICCCC DDDDDDDDD SSSSSSSSS ADDS D,S A__Ao_Z 0__0__1__1
110101 ZCRICCCC DDDDDDDDD SSSSSSSSS SUBS D,S A__Ao_Z 1__0__1__1
110110 ZCRICCCC DDDDDDDDD SSSSSSSSS ADDSX D,S A__Ao_Z& 0__C__1__1
110111 ZCRICCCC DDDDDDDDD SSSSSSSSS SUBSX D,S A__Ao_Z& 1__C__1__1
111000 ZCRICCCC DDDDDDDDD SSSSSSSSS CMPSUB D,S A__Ac_Z 1__0__1__1
111001 ZCRICCCC DDDDDDDDD SSSSSSSSS DJNZ D,S A__Au_Z 1__1__1__0
111010 ZCRICCCC DDDDDDDDD SSSSSSSSS TJNZ D,S A__Au_Z 1__0__1__0
111011 ZCRICCCC DDDDDDDDD SSSSSSSSS TJZ D,S A__Au_Z 1__0__1__0
111100 ZCRICCCC DDDDDDDDD SSSSSSSSS WAITPEQ D,S _______ __________
111101 ZCRICCCC DDDDDDDDD SSSSSSSSS WAITPNE D,S _______ __________
111110 ZCRICCCC DDDDDDDDD SSSSSSSSS WAITCNT D,S A__Au_Z 0__0__1__1
111111 ZCRICCCC DDDDDDDDD SSSSSSSSS WAITVID D,S _______ __________
----------------------------------------------------------------------------
* future instructions
ZCR effects
----------------------------------------------------------------------------
000 nz, nc, nr
001 nz, nc, r
010 nz, c, nr
011 nz, c, r
100 z, nc, nr
101 z, nc, r
110 z, c, nr
111 z, c, r
CCCC condition (easier-to-read list)
----------------------------------------------------------------------------
0000 never 1111 always (default)
0001 nc & nz 1100 if_c if_b
0010 nc & z 0011 if_nc if_ae
0011 nc 1010 if_z if_e
0100 c & nz 0101 if_nz if_ne
0101 nz 1000 if_c_and_z if_z_and_c
0110 c <> z 0100 if_c_and_nz if_nz_and_c
0111 nc | nz 0010 if_nc_and_z if_z_and_nc
1000 c & z 0001 if_nc_and_nz if_nz_and_nc if_a
1001 c = z 1110 if_c_or_z if_z_or_c if_be
1010 z 1101 if_c_or_nz if_nz_or_c
1011 nc | z 1011 if_nc_or_z if_z_or_nc
1100 c 0111 if_nc_or_nz if_nz_or_nc
1101 c | nz 1001 if_c_eq_z if_z_eq_c
1110 c | z 0110 if_c_ne_z if_z_ne_c
1111 always 0000 never
I SSSSSSSSS source operand
----------------------------------------------------------------------------
0 SSSSSSSSS register
1 #SSSSSSSSS immediate, zero-extended
DDDDDDDDD destination operand
----------------------------------------------------------------------------
DDDDDDDDD register
*/
`include "cog_ram.v"
`include "cog_alu.v"
`include "cog_ctr.v"
`include "cog_vid.v"
module cog
(
input nres, // reset
input clk_pll, // clocks
input clk_cog,
input ena_bus,
input ptr_w, // pointers
input [27:0] ptr_d,
input ena, // control
input bus_sel, // bus
output bus_r,
output bus_e,
output bus_w,
output [1:0] bus_s,
output [15:0] bus_a,
output [31:0] bus_d,
input [31:0] bus_q,
input bus_c,
input bus_ack,
input [31:0] cnt, // counter
input [7:0] pll_in, // pll's
output pll_out,
input [31:0] pin_in, // pins
output [31:0] pin_out,
output [31:0] pin_dir
);
parameter oh = 31;
parameter ol = 26;
parameter wz = 25;
parameter wc = 24;
parameter wr = 23;
parameter im = 22;
parameter ch = 21;
parameter cl = 18;
parameter dh = 17;
parameter dl = 9;
parameter sh = 8;
parameter sl = 0;
// pointers
reg [27:0] ptr;
always @(posedge clk_cog or negedge nres)
if (!nres)
ptr <= 27'b00000000000000_11111000000000;
else if (ena_bus && ptr_w)
ptr <= ptr_d;
// load/run
reg run;
always @(posedge clk_cog or negedge ena)
if (!ena)
run <= 1'b0;
else if (m[3] && (&px))
run <= 1'b1;
// state
reg [4:0] m;
always @(posedge clk_cog or negedge ena)
if (!ena)
m <= 5'b0;
else
m <= { (m[2] || m[4]) && waiti, // m[4] = wait
(m[2] || m[4]) && !waiti, // m[3] = write d
m[1], // m[2] = read next instruction
m[0], // m[1] = read d
!m[4] && !m[2] && !m[1] && !m[0] }; // m[0] = read s
// process
reg [8:0] p;
reg c;
reg z;
always @(posedge clk_cog or negedge ena)
if (!ena)
p <= 1'b0;
else if (m[3] && !(cond && jump_cancel))
p <= px + 1'b1;
always @(posedge clk_cog or negedge ena)
if (!ena)
c <= 1'b0;
else if (m[3] && cond && i[wc])
c <= alu_co;
always @(posedge clk_cog or negedge ena)
if (!ena)
z <= 1'b0;
else if (m[3] && cond && i[wz])
z <= alu_zo;
// addressable registers
//
// addr read write
// ------------------------
//
// 000-1EF RAM RAM
//
// 1F0 PAR RAM
// 1F1 CNT RAM
// 1F2 INA RAM
// 1F3 INB * RAM
// 1F4 RAM RAM+OUTA
// 1F5 RAM RAM+OUTB *
// 1F6 RAM RAM+DIRA
// 1F7 RAM RAM+DIRB *
// 1F8 RAM RAM+CTRA
// 1F9 RAM RAM+CTRB
// 1FA RAM RAM+FRQA
// 1FB RAM RAM+FRQB
// 1FC PHSA RAM+PHSA
// 1FD PHSB RAM+PHSB
// 1FE RAM RAM+VCFG
// 1FF RAM RAM+VSCL
//
// * future 64-pin version
wire wio = m[3] && cond && i[wr] && (&i[dh:dl+4]);
wire setouta = wio && i[dl+3:dl] == 4'h4;
wire setdira = wio && i[dl+3:dl] == 4'h6;
wire setctra = wio && i[dl+3:dl] == 4'h8;
wire setctrb = wio && i[dl+3:dl] == 4'h9;
wire setfrqa = wio && i[dl+3:dl] == 4'hA;
wire setfrqb = wio && i[dl+3:dl] == 4'hB;
wire setphsa = wio && i[dl+3:dl] == 4'hC;
wire setphsb = wio && i[dl+3:dl] == 4'hD;
wire setvid = wio && i[dl+3:dl] == 4'hE;
wire setscl = wio && i[dl+3:dl] == 4'hF;
// register ram
wire ram_ena = m[0] || m[1] || m[2] || m[3] && cond && i[wr];
wire ram_w = m[3] && alu_wr;
wire [8:0] ram_a = m[2] ? px
: m[0] ? i[sh:sl]
: i[dh:dl];
wire [31:0] ram_q;
cog_ram cog_ram_ ( .clk (clk_cog),
.ena (ram_ena),
.w (ram_w),
.a (ram_a),
.d (alu_r),
.q (ram_q) );
// outa/dira
reg [31:0] outa;
reg [31:0] dira;
always @(posedge clk_cog)
if (setouta)
outa <= alu_r;
always @(posedge clk_cog or negedge ena)
if (!ena)
dira <= 32'b0;
else if (setdira)
dira <= alu_r;
// ctra/ctrb
wire [32:0] phsa;
wire [31:0] ctra_pin_out;
wire plla;
cog_ctr cog_ctra ( .clk_cog (clk_cog),
.clk_pll (clk_pll),
.ena (ena),
.setctr (setctra),
.setfrq (setfrqa),
.setphs (setphsa),
.data (alu_r),
.pin_in (pin_in),
.phs (phsa),
.pin_out (ctra_pin_out),
.pll (plla) );
wire [32:0] phsb;
wire [31:0] ctrb_pin_out;
wire pllb;
cog_ctr cog_ctrb ( .clk_cog (clk_cog),
.clk_pll (clk_pll),
.ena (ena),
.setctr (setctrb),
.setfrq (setfrqb),
.setphs (setphsb),
.data (alu_r),
.pin_in (pin_in),
.phs (phsb),
.pin_out (ctrb_pin_out),
.pll (pllb) );
assign pll_out = plla;
// vid
wire vidack;
wire [31:0] vid_pin_out;
cog_vid cog_vid_ ( .clk_cog (clk_cog),
.clk_vid (plla),
.ena (ena),
.setvid (setvid),
.setscl (setscl),
.data (alu_r),
.pixel (s),
.color (d),
.aural (pll_in),
.carrier (pllb),
.ack (vidack),
.pin_out (vid_pin_out) );
// instruction
reg [31:0] ix;
always @(posedge clk_cog)
if (m[3])
ix <= ram_q;
wire [31:0] i = run ? ix : {14'b000010_001_0_0001, p, 9'b000000000};
// source
reg [31:0] sy;
reg [31:0] s;
always @(posedge clk_cog)
if (m[1])
sy <= ram_q;
wire [31:0] sx = i[im] ? {23'b0, i[sh:sl]}
: i[sh:sl] == 9'h1F0 ? {16'b0, ptr[27:14], 2'b0}
: i[sh:sl] == 9'h1F1 ? cnt
: i[sh:sl] == 9'h1F2 ? pin_in
: i[sh:sl] == 9'h1FC ? phsa[31:0]
: i[sh:sl] == 9'h1FD ? phsb[31:0]
: sy;
always @(posedge clk_cog)
if (m[2])
s <= sx;
// destination
reg [31:0] d;
always @(posedge clk_cog)
if (m[2])
d <= ram_q;
// condition
wire [3:0] condx = i[ch:cl];
wire cond = condx[{c, z}] && !cancel;
// jump/next
reg cancel;
wire dz = ~|d[31:1];
wire [1:0] jumpx = i[oh:ol] == 6'b010111 ? {1'b1, 1'b0} // retjmp
: i[oh:ol] == 6'b111001 ? {1'b1, dz && d[0]} // djnz
: i[oh:ol] == 6'b111010 ? {1'b1, dz && !d[0]} // tjnz
: i[oh:ol] == 6'b111011 ? {1'b1, !(dz && !d[0])} // tjz
: {1'b0, 1'b0}; // no jump
wire jump = jumpx[1];
wire jump_cancel = jumpx[0];
wire [8:0] px = cond && jump ? sx[8:0] : p;
always @(posedge clk_cog or negedge ena)
if (!ena)
cancel <= 1'b0;
else if (m[3])
cancel <= cond && jump_cancel || &px;
// bus interface
assign bus_r = !bus_sel ? 1'b0 : run;
assign bus_e = !bus_sel ? 1'b0 : i[oh:ol+2] == 4'b0000__ && m[4];
assign bus_w = !bus_sel ? 1'b0 : !i[wr];
assign bus_s = !bus_sel ? 2'b0 : i[ol+1:ol];
assign bus_a = !bus_sel ? 16'b0 : run ? s[15:0] : {ptr[13:0] + {5'b0, p}, s[1:0]};
assign bus_d = !bus_sel ? 32'b0 : d;
// alu interface
wire alu_wr;
wire [31:0] alu_r;
wire alu_co;
wire alu_zo;
cog_alu cog_alu_ ( .i (i[oh:ol]),
.s (s),
.d (d),
.p (p),
.run (run),
.ci (c),
.zi (z),
.bus_q (bus_q),
.bus_c (bus_c),
.wr (alu_wr),
.r (alu_r),
.co (alu_co),
.zo (alu_zo) );
// pin/count match
reg match;
always @(posedge clk_cog)
match <= m[4] && (i[ol+1:ol] == 2'b01 ^ (i[ol+1] ? cnt : pin_in & s) == d);
// wait
wire waitx = i[oh:ol+2] == 4'b0000__ ? !bus_ack
: i[oh:ol+1] == 5'b11110_ ? !match
: i[oh:ol+0] == 6'b111110 ? !match
: i[oh:ol+0] == 6'b111111 ? !vidack
: 1'b0;
wire waiti = cond && waitx;
// pins
assign pin_out = (outa | ctra_pin_out | ctrb_pin_out | vid_pin_out) & dira;
assign pin_dir = dira;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [4:0] din_data = crc[4:0];
wire [0:0] din_valid = crc[6];
wire [0:0] dout0_ready = crc[16];
wire [0:0] dout1_ready = crc[17];
wire [0:0] dout2_ready = crc[18];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
logic din_ready; // From test of Test.v
logic [0:0] dout0_data; // From test of Test.v
logic dout0_valid; // From test of Test.v
logic [1:0] dout1_data; // From test of Test.v
logic dout1_valid; // From test of Test.v
logic [2:0] dout2_data; // From test of Test.v
logic dout2_valid; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.din_ready (din_ready),
.dout0_valid (dout0_valid),
.dout0_data (dout0_data[0:0]),
.dout1_valid (dout1_valid),
.dout1_data (dout1_data[1:0]),
.dout2_valid (dout2_valid),
.dout2_data (dout2_data[2:0]),
// Inputs
.din_valid (din_valid),
.din_data (din_data[4:0]),
.dout0_ready (dout0_ready),
.dout1_ready (dout1_ready),
.dout2_ready (dout2_ready));
// Aggregate outputs into a single result vector
wire [63:0] result = {48'h0, din_ready,
2'd0, dout2_valid, dout2_data,
2'd0, dout1_valid, dout1_data,
2'd0, dout0_valid, dout0_data};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= '0;
end
else if (cyc<10) begin
sum <= '0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h6fd1bead9df31b07
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
interface dti
#(W_DATA = 64
)();
logic [W_DATA-1:0] data;
logic valid;
logic ready;
modport producer (output data,
output valid,
input ready);
modport consumer (input data,
input valid,
output ready);
endinterface : dti
module Test
(
output logic din_ready,
input logic din_valid,
input logic [4:0] din_data,
input logic dout0_ready,
output logic dout0_valid,
output logic [0:0] dout0_data,
input logic dout1_ready,
output logic dout1_valid,
output logic [1:0] dout1_data,
input logic dout2_ready,
output logic dout2_valid,
output logic [2:0] dout2_data
);
// Interface declarations
dti #(.W_DATA(5)) din();
dti #(.W_DATA(1)) dout0();
dti #(.W_DATA(2)) dout1();
dti #(.W_DATA(3)) dout2();
// Interface wiring to top level ports
assign din.valid = din_valid;
assign din.data = din_data;
assign din_ready = din.ready;
assign dout0_valid = dout0.valid;
assign dout0_data = dout0.data;
assign dout0.ready = dout0_ready;
assign dout1_valid = dout1.valid;
assign dout1_data = dout1.data;
assign dout1.ready = dout1_ready;
assign dout2_valid = dout2.valid;
assign dout2_data = dout2.data;
assign dout2.ready = dout2_ready;
assign din.ready = 0;
assign dout0.data = 0;
assign dout1.data = 0;
assign dout2.data = 0;
typedef struct packed {
logic [1:0] ctrl;
logic [2:0] data;
} din_t;
din_t din_s;
assign din_s = din.data;
always_comb begin
dout0.valid = 0;
dout1.valid = 0;
dout2.valid = 0;
case (din_s.ctrl)
0 : dout0.valid = din.valid;
1 : dout1.valid = din.valid;
2 : dout2.valid = din.valid;
default: ;
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFBBP_FUNCTIONAL_V
`define SKY130_FD_SC_MS__SDFBBP_FUNCTIONAL_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_nsr/sky130_fd_sc_ms__udp_dff_nsr.v"
`celldefine
module sky130_fd_sc_ms__sdfbbp (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_ms__udp_dff$NSR `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, mux_out);
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFBBP_FUNCTIONAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A21OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__A21OI_BEHAVIORAL_PP_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a21oi (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A21OI_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__XOR3_PP_SYMBOL_V
`define SKY130_FD_SC_HS__XOR3_PP_SYMBOL_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__xor3 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__XOR3_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__PROBE_P_8_V
`define SKY130_FD_SC_HD__PROBE_P_8_V
/**
* probe_p: Virtual voltage probe point.
*
* Verilog wrapper for probe_p with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__probe_p.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__probe_p_8 (
X ,
A ,
VGND,
VNB ,
VPB ,
VPWR
);
output X ;
input A ;
input VGND;
input VNB ;
input VPB ;
input VPWR;
sky130_fd_sc_hd__probe_p base (
.X(X),
.A(A),
.VGND(VGND),
.VNB(VNB),
.VPB(VPB),
.VPWR(VPWR)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__probe_p_8 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply0 VGND;
supply0 VNB ;
supply1 VPB ;
supply1 VPWR;
sky130_fd_sc_hd__probe_p base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__PROBE_P_8_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: fpu_mul_ctl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
///////////////////////////////////////////////////////////////////////////////
//
// Multiply pipeline synthesizable logic
// - special input cases
// - opcode pipeline
// - sign logic
// - exception logic
// - datapath control- select lines and control logic
//
///////////////////////////////////////////////////////////////////////////////
module fpu_mul_ctl (
inq_in1_51,
inq_in1_54,
inq_in1_53_0_neq_0,
inq_in1_50_0_neq_0,
inq_in1_53_32_neq_0,
inq_in1_exp_eq_0,
inq_in1_exp_neq_ffs,
inq_in2_51,
inq_in2_54,
inq_in2_53_0_neq_0,
inq_in2_50_0_neq_0,
inq_in2_53_32_neq_0,
inq_in2_exp_eq_0,
inq_in2_exp_neq_ffs,
inq_op,
inq_mul,
inq_rnd_mode,
inq_id,
inq_in1_63,
inq_in2_63,
mul_dest_rdy,
mul_dest_rdya,
m5stg_exp,
m5stg_fracadd_cout,
m5stg_frac_neq_0,
m5stg_frac_dbl_nx,
m5stg_frac_sng_nx,
m1stg_ld0_1,
m1stg_ld0_2,
m3stg_exp,
m3stg_expadd_eq_0,
m3stg_expadd_lte_0_inv,
m3stg_ld0_inv,
m4stg_exp,
m4stg_frac_105,
m5stg_frac,
arst_l,
grst_l,
rclk,
mul_pipe_active,
m1stg_snan_sng_in1,
m1stg_snan_dbl_in1,
m1stg_snan_sng_in2,
m1stg_snan_dbl_in2,
m1stg_step,
m1stg_sngop,
m1stg_dblop,
m1stg_dblop_inv,
m1stg_fmul,
m1stg_fsmuld,
m2stg_fmuls,
m2stg_fmuld,
m2stg_fsmuld,
m5stg_fmuls,
m5stg_fmuld,
m5stg_fmulda,
m6stg_fmul_in,
m6stg_id_in,
m6stg_fmul_dbl_dst,
m6stg_fmuls,
m6stg_step,
mul_sign_out,
m5stg_in_of,
mul_exc_out,
m2stg_frac1_dbl_norm,
m2stg_frac1_dbl_dnrm,
m2stg_frac1_sng_norm,
m2stg_frac1_sng_dnrm,
m2stg_frac1_inf,
m2stg_frac2_dbl_norm,
m2stg_frac2_dbl_dnrm,
m2stg_frac2_sng_norm,
m2stg_frac2_sng_dnrm,
m2stg_frac2_inf,
m1stg_inf_zero_in,
m1stg_inf_zero_in_dbl,
m2stg_exp_expadd,
m2stg_exp_0bff,
m2stg_exp_017f,
m2stg_exp_04ff,
m2stg_exp_zero,
m3bstg_ld0_inv,
m4stg_sh_cnt_in,
m4stg_inc_exp_54,
m4stg_inc_exp_55,
m4stg_inc_exp_105,
m4stg_left_shift_step,
m4stg_right_shift_step,
m5stg_to_0,
m5stg_to_0_inv,
mul_frac_out_fracadd,
mul_frac_out_frac,
mul_exp_out_exp_plus1,
mul_exp_out_exp,
mula_rst_l,
se,
si,
so
);
parameter
FMULS= 8'h49,
FMULD= 8'h4a,
FSMULD= 8'h69;
input inq_in1_51; // request operand 1[51]
input inq_in1_54; // request operand 1[54]
input inq_in1_53_0_neq_0; // request operand 1[53:0]!=0
input inq_in1_50_0_neq_0; // request operand 1[50:0]!=0
input inq_in1_53_32_neq_0; // request operand 1[53:32]!=0
input inq_in1_exp_eq_0; // request operand 1[62:52]==0
input inq_in1_exp_neq_ffs; // request operand 1[62:52]!=0x7ff
input inq_in2_51; // request operand 2[51]
input inq_in2_54; // request operand 2[54]
input inq_in2_53_0_neq_0; // request operand 2[53:0]!=0
input inq_in2_50_0_neq_0; // request operand 2[50:0]!=0
input inq_in2_53_32_neq_0; // request operand 2[53:32]!=0
input inq_in2_exp_eq_0; // request operand 2[62:52]==0
input inq_in2_exp_neq_ffs; // request operand 2[62:52]!=0x7ff
input [7:0] inq_op; // request opcode to op pipes
input inq_mul; // multiply pipe request
input [1:0] inq_rnd_mode; // request rounding mode to op pipes
input [4:0] inq_id; // request ID to the operation pipes
input inq_in1_63; // request[63] operand 1 to op pipes
input inq_in2_63; // request[63] operand 2 to op pipes
input mul_dest_rdy; // multiply result req accepted for CPX
input mul_dest_rdya; // multiply result req accepted for CPX
input [12:0] m5stg_exp; // exponent input- multiply 5 stage
input m5stg_fracadd_cout; // fraction rounding adder carry out
input m5stg_frac_neq_0; // fraction input to mul 5 stage != 0
input m5stg_frac_dbl_nx; // double precision inexact result
input m5stg_frac_sng_nx; // single precision inexact result
input [5:0] m1stg_ld0_1; // denorm operand 1 leading 0's
input [5:0] m1stg_ld0_2; // denorm operand 2 leading 0's
input [12:0] m3stg_exp; // exponent input- multiply 3 stage
input m3stg_expadd_eq_0; // mul stage 3 exponent adder sum == 0
input m3stg_expadd_lte_0_inv; // mul stage 3 exponent adder sum <= 0
input [5:0] m3stg_ld0_inv; // leading 0's in multiply operands
input [12:0] m4stg_exp; // exponent input- multiply 4 stage
input m4stg_frac_105; // multiply stage 4a fraction input[105]
input [32:0] m5stg_frac; // multiply stage 5 fraction input
input arst_l; // asynchronous global reset- asserted low
input grst_l; // synchronous global reset- asserted low
input rclk; // global clock
output mul_pipe_active; // mul pipe is executing a valid instr
output m1stg_snan_sng_in1; // operand 1 is single signalling NaN
output m1stg_snan_dbl_in1; // operand 1 is double signalling NaN
output m1stg_snan_sng_in2; // operand 2 is single signalling NaN
output m1stg_snan_dbl_in2; // operand 2 is double signalling NaN
output m1stg_step; // multiply pipe load
output m1stg_sngop; // single precision operation- mul 1 stg
output m1stg_dblop; // double precision operation- mul 1 stg
output m1stg_dblop_inv; // single or int operation- mul 1 stg
output m1stg_fmul; // multiply operation- mul 1 stage
output m1stg_fsmuld; // fsmuld- multiply 1 stage
output m2stg_fmuls; // fmuls- multiply 2 stage
output m2stg_fmuld; // fmuld- multiply 2 stage
output m2stg_fsmuld; // fsmuld- multiply 2 stage
output m5stg_fmuls; // fmuls- multiply 5 stage
output m5stg_fmuld; // fmuld- multiply 5 stage
output m5stg_fmulda; // fmuld- multiply 5 stage copy
output m6stg_fmul_in; // mul pipe output request next cycle
output [9:0] m6stg_id_in; // mul pipe output ID next cycle
output m6stg_fmul_dbl_dst; // double precision multiply result
output m6stg_fmuls; // fmuls- multiply 6 stage
output m6stg_step; // advance the multiply pipe
output mul_sign_out; // multiply sign output
output m5stg_in_of; // multiply overflow- select exp out
output [4:0] mul_exc_out; // multiply pipe result- exception flags
output m2stg_frac1_dbl_norm; // select line to m2stg_frac1
output m2stg_frac1_dbl_dnrm; // select line to m2stg_frac1
output m2stg_frac1_sng_norm; // select line to m2stg_frac1
output m2stg_frac1_sng_dnrm; // select line to m2stg_frac1
output m2stg_frac1_inf; // select line to m2stg_frac1
output m2stg_frac2_dbl_norm; // select line to m2stg_frac2
output m2stg_frac2_dbl_dnrm; // select line to m2stg_frac2
output m2stg_frac2_sng_norm; // select line to m2stg_frac2
output m2stg_frac2_sng_dnrm; // select line to m2stg_frac2
output m2stg_frac2_inf; // select line to m2stg_frac2
output m1stg_inf_zero_in; // 1 operand is infinity; other is 0
output m1stg_inf_zero_in_dbl; // 1 opnd is infinity; other is 0- dbl
output m2stg_exp_expadd; // select line to m2stg_exp
output m2stg_exp_0bff; // select line to m2stg_exp
output m2stg_exp_017f; // select line to m2stg_exp
output m2stg_exp_04ff; // select line to m2stg_exp
output m2stg_exp_zero; // select line to m2stg_exp
output [6:0] m3bstg_ld0_inv; // leading 0's in multiply operands
output [5:0] m4stg_sh_cnt_in; // multiply normalization shift count
output m4stg_inc_exp_54; // select line to m5stg_exp
output m4stg_inc_exp_55; // select line to m5stg_exp
output m4stg_inc_exp_105; // select line to m5stg_exp
output m4stg_left_shift_step; // select line to m5stg_frac
output m4stg_right_shift_step; // select line to m5stg_frac
output m5stg_to_0; // result to max finite on overflow
output m5stg_to_0_inv; // result to infinity on overflow
output mul_frac_out_fracadd; // select line to mul_frac_out
output mul_frac_out_frac; // select line to mul_frac_out
output mul_exp_out_exp_plus1; // select line to mul_exp_out
output mul_exp_out_exp; // select line to mul_exp_out
output mula_rst_l; // reset for mul64
input se; // scan_enable
input si; // scan in
output so; // scan out
wire reset;
wire mul_frac_in1_51;
wire mul_frac_in1_54;
wire mul_frac_in1_53_0_neq_0;
wire mul_frac_in1_50_0_neq_0;
wire mul_frac_in1_53_32_neq_0;
wire mul_exp_in1_exp_eq_0;
wire mul_exp_in1_exp_neq_ffs;
wire mul_frac_in2_51;
wire mul_frac_in2_54;
wire mul_frac_in2_53_0_neq_0;
wire mul_frac_in2_50_0_neq_0;
wire mul_frac_in2_53_32_neq_0;
wire mul_exp_in2_exp_eq_0;
wire mul_exp_in2_exp_neq_ffs;
wire m1stg_denorm_sng_in1;
wire m1stg_denorm_dbl_in1;
wire m1stg_denorm_sng_in2;
wire m1stg_denorm_dbl_in2;
wire m1stg_denorm_in1;
wire m1stg_denorm_in2;
wire m1stg_norm_sng_in1;
wire m1stg_norm_dbl_in1;
wire m1stg_norm_sng_in2;
wire m1stg_norm_dbl_in2;
wire m1stg_snan_sng_in1;
wire m1stg_snan_dbl_in1;
wire m1stg_snan_sng_in2;
wire m1stg_snan_dbl_in2;
wire m1stg_qnan_sng_in1;
wire m1stg_qnan_dbl_in1;
wire m1stg_qnan_sng_in2;
wire m1stg_qnan_dbl_in2;
wire m1stg_snan_in1;
wire m1stg_snan_in2;
wire m1stg_qnan_in1;
wire m1stg_qnan_in2;
wire m2stg_snan_in1;
wire m2stg_snan_in2;
wire m2stg_qnan_in1;
wire m2stg_qnan_in2;
wire m1stg_nan_sng_in1;
wire m1stg_nan_dbl_in1;
wire m1stg_nan_sng_in2;
wire m1stg_nan_dbl_in2;
wire m1stg_nan_in1;
wire m1stg_nan_in2;
wire m2stg_nan_in2;
wire m1stg_inf_sng_in1;
wire m1stg_inf_dbl_in1;
wire m1stg_inf_sng_in2;
wire m1stg_inf_dbl_in2;
wire m1stg_inf_in1;
wire m1stg_inf_in2;
wire m1stg_inf_in;
wire m2stg_inf_in1;
wire m2stg_inf_in2;
wire m2stg_inf_in;
wire m1stg_infnan_sng_in1;
wire m1stg_infnan_dbl_in1;
wire m1stg_infnan_sng_in2;
wire m1stg_infnan_dbl_in2;
wire m1stg_infnan_in1;
wire m1stg_infnan_in2;
wire m1stg_infnan_in;
wire m1stg_zero_in1;
wire m1stg_zero_in2;
wire m1stg_zero_in;
wire m2stg_zero_in1;
wire m2stg_zero_in2;
wire m2stg_zero_in;
wire m1stg_step;
wire [7:0] m1stg_op_in;
wire [7:0] m1stg_op;
wire m1stg_mul_in;
wire m1stg_mul;
wire m1stg_sngop;
wire [3:0] m1stg_sngopa;
wire m1stg_dblop;
wire [3:0] m1stg_dblopa;
wire m1stg_dblop_inv_in;
wire m1stg_dblop_inv;
wire [1:0] m1stg_rnd_mode;
wire [4:0] m1stg_id;
wire m1stg_fmul;
wire m1stg_fmul_dbl_dst;
wire m1stg_fmuls;
wire m1stg_fmuld;
wire m1stg_fsmuld;
wire [4:0] m1stg_opdec;
wire [4:0] m2stg_opdec;
wire [1:0] m2stg_rnd_mode;
wire [4:0] m2stg_id;
wire m2stg_fmul;
wire m2stg_fmuls;
wire m2stg_fmuld;
wire m2stg_fsmuld;
wire [4:1] m3astg_opdec;
wire [1:0] m3astg_rnd_mode;
wire [4:0] m3astg_id;
wire [4:1] m3bstg_opdec;
wire [1:0] m3bstg_rnd_mode;
wire [4:0] m3bstg_id;
wire [4:1] m3stg_opdec;
wire [1:0] m3stg_rnd_mode;
wire [4:0] m3stg_id;
wire m3stg_fmul;
wire [4:1] m4stg_opdec;
wire [1:0] m4stg_rnd_mode;
wire [4:0] m4stg_id;
wire m4stg_fmul;
wire m4stg_fmuld;
wire [4:1] m5stg_opdec;
wire [1:0] m5stg_rnd_mode;
wire [4:0] m5stg_id;
wire m5stg_fmul;
wire m5stg_fmuls;
wire m5stg_fmuld;
wire m5stg_fmulda;
wire m6stg_fmul_in;
wire [4:2] m6stg_opdec;
wire [9:0] m6stg_id_in;
wire [9:0] m6stg_id;
wire m6stg_fmul;
wire m6stg_fmul_dbl_dst;
wire m6stg_fmuls;
wire m6stg_hold;
wire m6stg_holda;
wire m6stg_step;
wire m6stg_stepa;
wire m1stg_sign1;
wire m1stg_sign2;
wire m2stg_sign1;
wire m2stg_sign2;
wire m1stg_of_mask;
wire m2stg_of_mask;
wire m2stg_sign;
wire m3astg_sign;
wire m2stg_nv;
wire m3astg_nv;
wire m3astg_of_mask;
wire m3bstg_sign;
wire m3bstg_nv;
wire m3stg_sign;
wire m3stg_nv;
wire m3stg_of_mask;
wire m4stg_sign;
wire m4stg_nv;
wire m4stg_of_mask;
wire m5stg_sign;
wire m5stg_nv;
wire m5stg_of_mask;
wire mul_sign_out;
wire mul_nv_out;
wire m5stg_in_of;
wire mul_of_out_tmp1_in;
wire mul_of_out_tmp1;
wire mul_of_out_tmp2;
wire mul_of_out_cout;
wire mul_of_out;
wire mul_uf_out_in;
wire mul_uf_out;
wire mul_nx_out_in;
wire mul_nx_out;
wire [4:0] mul_exc_out;
wire m2stg_frac1_dbl_norm;
wire m2stg_frac1_dbl_dnrm;
wire m2stg_frac1_sng_norm;
wire m2stg_frac1_sng_dnrm;
wire m2stg_frac1_inf;
wire m2stg_frac2_dbl_norm;
wire m2stg_frac2_dbl_dnrm;
wire m2stg_frac2_sng_norm;
wire m2stg_frac2_sng_dnrm;
wire m2stg_frac2_inf;
wire m1stg_inf_zero_in;
wire m1stg_inf_zero_in_dbl;
wire [5:0] m2stg_ld0_1_in;
wire [5:0] m2stg_ld0_1;
wire [5:0] m2stg_ld0_2_in;
wire [5:0] m2stg_ld0_2;
wire m2stg_exp_expadd;
wire m2stg_exp_0bff;
wire m2stg_exp_017f;
wire m2stg_exp_04ff;
wire m2stg_exp_zero;
wire [6:0] m2stg_ld0;
wire [6:0] m2stg_ld0_inv;
wire [6:0] m3astg_ld0_inv;
wire [6:0] m3bstg_ld0_inv;
wire m4stg_expadd_eq_0;
wire m3stg_exp_lte_0;
wire m4stg_right_shift_in;
wire m4stg_right_shift;
wire [5:0] m3stg_exp_minus1;
wire [5:0] m3stg_exp_inv_plus2;
wire m3stg_exp_lt_neg57;
wire [5:0] m4stg_sh_cnt_in;
wire m4stg_left_shift_step;
wire m4stg_right_shift_step;
wire m4stg_inc_exp_54;
wire m4stg_inc_exp_55;
wire m4stg_inc_exp_105;
wire m5stg_rndup;
wire m5stg_to_0;
wire m5stg_to_0_inv;
wire mul_frac_out_fracadd;
wire mul_frac_out_frac;
wire mul_exp_out_exp_plus1;
wire mul_exp_out_exp;
wire mul_pipe_active_in;
wire mul_pipe_active;
wire mula_rst_l;
dffrl_async #(1) dffrl_mul_ctl (
.din (grst_l),
.clk (rclk),
.rst_l(arst_l),
.q (mul_ctl_rst_l),
.se (se),
.si (),
.so ()
);
assign reset= (!mul_ctl_rst_l);
// 3/14/03 reset signal for mul64
assign mula_rst_l = mul_ctl_rst_l;
///////////////////////////////////////////////////////////////////////////////
//
// Multiply pipeline special input cases.
//
///////////////////////////////////////////////////////////////////////////////
dffe #(1) i_mul_frac_in1_51 (
.din (inq_in1_51),
.en (m6stg_step),
.clk (rclk),
.q (mul_frac_in1_51),
.se (se),
.si (),
.so ()
);
dffe #(1) i_mul_frac_in1_54 (
.din (inq_in1_54),
.en (m6stg_step),
.clk (rclk),
.q (mul_frac_in1_54),
.se (se),
.si (),
.so ()
);
dffe #(1) i_mul_frac_in1_53_0_neq_0 (
.din (inq_in1_53_0_neq_0),
.en (m6stg_step),
.clk (rclk),
.q (mul_frac_in1_53_0_neq_0),
.se (se),
.si (),
.so ()
);
dffe #(1) i_mul_frac_in1_50_0_neq_0 (
.din (inq_in1_50_0_neq_0),
.en (m6stg_step),
.clk (rclk),
.q (mul_frac_in1_50_0_neq_0),
.se (se),
.si (),
.so ()
);
dffe #(1) i_mul_frac_in1_53_32_neq_0 (
.din (inq_in1_53_32_neq_0),
.en (m6stg_step),
.clk (rclk),
.q (mul_frac_in1_53_32_neq_0),
.se (se),
.si (),
.so ()
);
dffe #(1) i_mul_exp_in1_exp_eq_0 (
.din (inq_in1_exp_eq_0),
.en (m6stg_step),
.clk (rclk),
.q (mul_exp_in1_exp_eq_0),
.se (se),
.si (),
.so ()
);
dffe #(1) i_mul_exp_in1_exp_neq_ffs (
.din (inq_in1_exp_neq_ffs),
.en (m6stg_step),
.clk (rclk),
.q (mul_exp_in1_exp_neq_ffs),
.se (se),
.si (),
.so ()
);
dffe #(1) i_mul_frac_in2_51 (
.din (inq_in2_51),
.en (m6stg_step),
.clk (rclk),
.q (mul_frac_in2_51),
.se (se),
.si (),
.so ()
);
dffe #(1) i_mul_frac_in2_54 (
.din (inq_in2_54),
.en (m6stg_step),
.clk (rclk),
.q (mul_frac_in2_54),
.se (se),
.si (),
.so ()
);
dffe #(1) i_mul_frac_in2_53_0_neq_0 (
.din (inq_in2_53_0_neq_0),
.en (m6stg_step),
.clk (rclk),
.q (mul_frac_in2_53_0_neq_0),
.se (se),
.si (),
.so ()
);
dffe #(1) i_mul_frac_in2_50_0_neq_0 (
.din (inq_in2_50_0_neq_0),
.en (m6stg_step),
.clk (rclk),
.q (mul_frac_in2_50_0_neq_0),
.se (se),
.si (),
.so ()
);
dffe #(1) i_mul_frac_in2_53_32_neq_0 (
.din (inq_in2_53_32_neq_0),
.en (m6stg_step),
.clk (rclk),
.q (mul_frac_in2_53_32_neq_0),
.se (se),
.si (),
.so ()
);
dffe #(1) i_mul_exp_in2_exp_eq_0 (
.din (inq_in2_exp_eq_0),
.en (m6stg_step),
.clk (rclk),
.q (mul_exp_in2_exp_eq_0),
.se (se),
.si (),
.so ()
);
dffe #(1) i_mul_exp_in2_exp_neq_ffs (
.din (inq_in2_exp_neq_ffs),
.en (m6stg_step),
.clk (rclk),
.q (mul_exp_in2_exp_neq_ffs),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Denorm multiply inputs.
//
///////////////////////////////////////////////////////////////////////////////
assign m1stg_denorm_sng_in1= mul_exp_in1_exp_eq_0 && m1stg_sngopa[0];
assign m1stg_denorm_dbl_in1= mul_exp_in1_exp_eq_0 && m1stg_dblopa[0];
assign m1stg_denorm_sng_in2= mul_exp_in2_exp_eq_0 && m1stg_sngopa[0];
assign m1stg_denorm_dbl_in2= mul_exp_in2_exp_eq_0 && m1stg_dblopa[0];
assign m1stg_denorm_in1= m1stg_denorm_sng_in1 || m1stg_denorm_dbl_in1;
assign m1stg_denorm_in2= m1stg_denorm_sng_in2 || m1stg_denorm_dbl_in2;
///////////////////////////////////////////////////////////////////////////////
//
// Non-denorm multiply inputs.
//
///////////////////////////////////////////////////////////////////////////////
assign m1stg_norm_sng_in1= (!mul_exp_in1_exp_eq_0) && m1stg_sngopa[0];
assign m1stg_norm_dbl_in1= (!mul_exp_in1_exp_eq_0) && m1stg_dblopa[0];
assign m1stg_norm_sng_in2= (!mul_exp_in2_exp_eq_0) && m1stg_sngopa[0];
assign m1stg_norm_dbl_in2= (!mul_exp_in2_exp_eq_0) && m1stg_dblopa[0];
///////////////////////////////////////////////////////////////////////////////
//
// Nan multiply inputs.
//
///////////////////////////////////////////////////////////////////////////////
assign m1stg_snan_sng_in1= (!mul_exp_in1_exp_neq_ffs) && (!mul_frac_in1_54)
&& (mul_frac_in1_53_32_neq_0) && m1stg_sngopa[1];
assign m1stg_snan_dbl_in1= (!mul_exp_in1_exp_neq_ffs)
&& (!mul_frac_in1_51) && mul_frac_in1_50_0_neq_0
&& m1stg_dblopa[1];
assign m1stg_snan_sng_in2= (!mul_exp_in2_exp_neq_ffs) && (!mul_frac_in2_54)
&& (mul_frac_in2_53_32_neq_0) && m1stg_sngopa[1];
assign m1stg_snan_dbl_in2= (!mul_exp_in2_exp_neq_ffs)
&& (!mul_frac_in2_51) && mul_frac_in2_50_0_neq_0
&& m1stg_dblopa[1];
assign m1stg_qnan_sng_in1= (!mul_exp_in1_exp_neq_ffs) && mul_frac_in1_54
&& m1stg_sngopa[1];
assign m1stg_qnan_dbl_in1= (!mul_exp_in1_exp_neq_ffs) && mul_frac_in1_51
&& m1stg_dblopa[1];
assign m1stg_qnan_sng_in2= (!mul_exp_in2_exp_neq_ffs) && mul_frac_in2_54
&& m1stg_sngopa[1];
assign m1stg_qnan_dbl_in2= (!mul_exp_in2_exp_neq_ffs) && mul_frac_in2_51
&& m1stg_dblopa[1];
assign m1stg_snan_in1= m1stg_snan_sng_in1 || m1stg_snan_dbl_in1;
assign m1stg_snan_in2= m1stg_snan_sng_in2 || m1stg_snan_dbl_in2;
assign m1stg_qnan_in1= m1stg_qnan_sng_in1 || m1stg_qnan_dbl_in1;
assign m1stg_qnan_in2= m1stg_qnan_sng_in2 || m1stg_qnan_dbl_in2;
dffe #(1) i_m2stg_snan_in1 (
.din (m1stg_snan_in1),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_snan_in1),
.se (se),
.si (),
.so ()
);
dffe #(1) i_m2stg_snan_in2 (
.din (m1stg_snan_in2),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_snan_in2),
.se (se),
.si (),
.so ()
);
dffe #(1) i_m2stg_qnan_in1 (
.din (m1stg_qnan_in1),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_qnan_in1),
.se (se),
.si (),
.so ()
);
dffe #(1) i_m2stg_qnan_in2 (
.din (m1stg_qnan_in2),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_qnan_in2),
.se (se),
.si (),
.so ()
);
assign m1stg_nan_sng_in1= (!mul_exp_in1_exp_neq_ffs)
&& (mul_frac_in1_54 || mul_frac_in1_53_32_neq_0)
&& m1stg_sngopa[2];
assign m1stg_nan_dbl_in1= (!mul_exp_in1_exp_neq_ffs)
&& (mul_frac_in1_51 || mul_frac_in1_50_0_neq_0)
&& m1stg_dblopa[2];
assign m1stg_nan_sng_in2= (!mul_exp_in2_exp_neq_ffs)
&& (mul_frac_in2_54 || mul_frac_in2_53_32_neq_0)
&& m1stg_sngopa[2];
assign m1stg_nan_dbl_in2= (!mul_exp_in2_exp_neq_ffs)
&& (mul_frac_in2_51 || mul_frac_in2_50_0_neq_0)
&& m1stg_dblopa[2];
assign m1stg_nan_in1= m1stg_nan_sng_in1 || m1stg_nan_dbl_in1;
assign m1stg_nan_in2= m1stg_nan_sng_in2 || m1stg_nan_dbl_in2;
dffe #(1) i_m2stg_nan_in2 (
.din (m1stg_nan_in2),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_nan_in2),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Infinity multiply inputs.
//
///////////////////////////////////////////////////////////////////////////////
assign m1stg_inf_sng_in1= (!mul_exp_in1_exp_neq_ffs)
&& (!mul_frac_in1_54) && (!mul_frac_in1_53_32_neq_0)
&& m1stg_sngopa[2];
assign m1stg_inf_dbl_in1= (!mul_exp_in1_exp_neq_ffs)
&& (!mul_frac_in1_51) && (!mul_frac_in1_50_0_neq_0)
&& m1stg_dblopa[2];
assign m1stg_inf_sng_in2= (!mul_exp_in2_exp_neq_ffs)
&& (!mul_frac_in2_54) && (!mul_frac_in2_53_32_neq_0)
&& m1stg_sngopa[2];
assign m1stg_inf_dbl_in2= (!mul_exp_in2_exp_neq_ffs)
&& (!mul_frac_in2_51) && (!mul_frac_in2_50_0_neq_0)
&& m1stg_dblopa[2];
assign m1stg_inf_in1= m1stg_inf_sng_in1 || m1stg_inf_dbl_in1;
assign m1stg_inf_in2= m1stg_inf_sng_in2 || m1stg_inf_dbl_in2;
assign m1stg_inf_in= m1stg_inf_in1 || m1stg_inf_in2;
dffe #(1) i_m2stg_inf_in1 (
.din (m1stg_inf_in1),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_inf_in1),
.se (se),
.si (),
.so ()
);
dffe #(1) i_m2stg_inf_in2 (
.din (m1stg_inf_in2),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_inf_in2),
.se (se),
.si (),
.so ()
);
dffe #(1) i_m2stg_inf_in (
.din (m1stg_inf_in),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_inf_in),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Infinity/Nan multiply inputs.
//
///////////////////////////////////////////////////////////////////////////////
assign m1stg_infnan_sng_in1= (!mul_exp_in1_exp_neq_ffs) && m1stg_sngopa[3];
assign m1stg_infnan_dbl_in1= (!mul_exp_in1_exp_neq_ffs) && m1stg_dblopa[3];
assign m1stg_infnan_sng_in2= (!mul_exp_in2_exp_neq_ffs) && m1stg_sngopa[3];
assign m1stg_infnan_dbl_in2= (!mul_exp_in2_exp_neq_ffs) && m1stg_dblopa[3];
assign m1stg_infnan_in1= m1stg_infnan_sng_in1 || m1stg_infnan_dbl_in1;
assign m1stg_infnan_in2= m1stg_infnan_sng_in2 || m1stg_infnan_dbl_in2;
assign m1stg_infnan_in= m1stg_infnan_in1 || m1stg_infnan_in2;
///////////////////////////////////////////////////////////////////////////////
//
// Zero multiply inputs.
//
///////////////////////////////////////////////////////////////////////////////
assign m1stg_zero_in1= mul_exp_in1_exp_eq_0
&& (!mul_frac_in1_53_0_neq_0) && (!mul_frac_in1_54);
assign m1stg_zero_in2= mul_exp_in2_exp_eq_0
&& (!mul_frac_in2_53_0_neq_0) && (!mul_frac_in2_54);
assign m1stg_zero_in= m1stg_zero_in1 || m1stg_zero_in2;
dffe #(1) i_m2stg_zero_in1 (
.din (m1stg_zero_in1),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_zero_in1),
.se (se),
.si (),
.so ()
);
dffe #(1) i_m2stg_zero_in2 (
.din (m1stg_zero_in2),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_zero_in2),
.se (se),
.si (),
.so ()
);
dffe #(1) i_m2stg_zero_in (
.din (m1stg_zero_in),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_zero_in),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Floating point multiply control pipeline.
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- multiply input stage.
//
///////////////////////////////////////////////////////////////////////////////
assign m1stg_step= m6stg_stepa && (!m1stg_mul);
assign m1stg_op_in[7:0]= ({8{(m1stg_step && (!reset))}}
& (inq_op[7:0] & {8{inq_mul}}))
| ({8{((!m6stg_step) && (!reset))}}
& m1stg_op[7:0]);
dff #(8) i_m1stg_op (
.din (m1stg_op_in[7:0]),
.clk (rclk),
.q (m1stg_op[7:0]),
.se (se),
.si (),
.so ()
);
assign m1stg_mul_in= (m1stg_step && (!reset) && inq_mul)
|| ((!m6stg_step) && (!reset) && m1stg_mul);
dff #(1) i_m1stg_mul (
.din (m1stg_mul_in),
.clk (rclk),
.q (m1stg_mul),
.se (se),
.si (),
.so ()
);
dffe #(1) i_m1stg_sngop (
.din (inq_op[0]),
.en (m6stg_step),
.clk (rclk),
.q (m1stg_sngop),
.se (se),
.si (),
.so ()
);
dffe #(4) i_m1stg_sngopa (
.din ({4{inq_op[0]}}),
.en (m6stg_step),
.clk (rclk),
.q (m1stg_sngopa[3:0]),
.se (se),
.si (),
.so ()
);
dffe #(1) i_m1stg_dblop (
.din (inq_op[1]),
.en (m6stg_step),
.clk (rclk),
.q (m1stg_dblop),
.se (se),
.si (),
.so ()
);
dffe #(4) i_m1stg_dblopa (
.din ({4{inq_op[1]}}),
.en (m6stg_step),
.clk (rclk),
.q (m1stg_dblopa[3:0]),
.se (se),
.si (),
.so ()
);
assign m1stg_dblop_inv_in= (!inq_op[1]);
dffe #(1) i_m1stg_dblop_inv (
.din (m1stg_dblop_inv_in),
.en (m6stg_step),
.clk (rclk),
.q (m1stg_dblop_inv),
.se (se),
.si (),
.so ()
);
dffe #(2) i_m1stg_rnd_mode (
.din (inq_rnd_mode[1:0]),
.en (m6stg_step),
.clk (rclk),
.q (m1stg_rnd_mode[1:0]),
.se (se),
.si (),
.so ()
);
dffe #(5) i_m1stg_id (
.din (inq_id[4:0]),
.en (m6stg_step),
.clk (rclk),
.q (m1stg_id[4:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode decode- multiply stage 1.
//
///////////////////////////////////////////////////////////////////////////////
assign m1stg_fmul= (m1stg_op[7:0]==FMULS) || (m1stg_op[7:0]==FMULD)
|| (m1stg_op[7:0]==FSMULD);
assign m1stg_fmul_dbl_dst= (m1stg_op[7:0]==FMULD) || (m1stg_op[7:0]==FSMULD);
assign m1stg_fmuls= (m1stg_op[7:0]==FMULS);
assign m1stg_fmuld= (m1stg_op[7:0]==FMULD);
assign m1stg_fsmuld= (m1stg_op[7:0]==FSMULD);
assign m1stg_opdec[4:0]= {m1stg_fmul,
m1stg_fmul_dbl_dst,
m1stg_fmuls,
m1stg_fmuld,
m1stg_fsmuld};
dffre #(5) i_m2stg_opdec (
.din (m1stg_opdec[4:0]),
.en (m6stg_step),
.rst (reset),
.clk (rclk),
.q (m2stg_opdec[4:0]),
.se (se),
.si (),
.so ()
);
dffe #(2) i_m2stg_rnd_mode (
.din (m1stg_rnd_mode[1:0]),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_rnd_mode[1:0]),
.se (se),
.si (),
.so ()
);
dffe #(5) i_m2stg_id (
.din (m1stg_id[4:0]),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_id[4:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- multiply stage 2.
//
///////////////////////////////////////////////////////////////////////////////
assign m2stg_fmul= m2stg_opdec[4];
assign m2stg_fmuls= m2stg_opdec[2];
assign m2stg_fmuld= m2stg_opdec[1];
assign m2stg_fsmuld= m2stg_opdec[0];
dffre #(4) i_m3astg_opdec (
.din (m2stg_opdec[4:1]),
.en (m6stg_step),
.rst (reset),
.clk (rclk),
.q (m3astg_opdec[4:1]),
.se (se),
.si (),
.so ()
);
dffe #(2) i_m3astg_rnd_mode (
.din (m2stg_rnd_mode[1:0]),
.en (m6stg_step),
.clk (rclk),
.q (m3astg_rnd_mode[1:0]),
.se (se),
.si (),
.so ()
);
dffe #(5) i_m3astg_id (
.din (m2stg_id[4:0]),
.en (m6stg_step),
.clk (rclk),
.q (m3astg_id[4:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- multiply stage 3a.
//
///////////////////////////////////////////////////////////////////////////////
dffre #(4) i_m3bstg_opdec (
.din (m3astg_opdec[4:1]),
.en (m6stg_step),
.rst (reset),
.clk (rclk),
.q (m3bstg_opdec[4:1]),
.se (se),
.si (),
.so ()
);
dffe #(2) i_m3bstg_rnd_mode (
.din (m3astg_rnd_mode[1:0]),
.en (m6stg_step),
.clk (rclk),
.q (m3bstg_rnd_mode[1:0]),
.se (se),
.si (),
.so ()
);
dffe #(5) i_m3bstg_id (
.din (m3astg_id[4:0]),
.en (m6stg_step),
.clk (rclk),
.q (m3bstg_id[4:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- multiply stage 3b.
//
///////////////////////////////////////////////////////////////////////////////
dffre #(4) i_m3stg_opdec (
.din (m3bstg_opdec[4:1]),
.en (m6stg_step),
.rst (reset),
.clk (rclk),
.q (m3stg_opdec[4:1]),
.se (se),
.si (),
.so ()
);
dffe #(2) i_m3stg_rnd_mode (
.din (m3bstg_rnd_mode[1:0]),
.en (m6stg_step),
.clk (rclk),
.q (m3stg_rnd_mode[1:0]),
.se (se),
.si (),
.so ()
);
dffe #(5) i_m3stg_id (
.din (m3bstg_id[4:0]),
.en (m6stg_step),
.clk (rclk),
.q (m3stg_id[4:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- multiply stage 3.
//
///////////////////////////////////////////////////////////////////////////////
assign m3stg_fmul= m3stg_opdec[4];
dffre #(4) i_m4stg_opdec (
.din (m3stg_opdec[4:1]),
.en (m6stg_step),
.rst (reset),
.clk (rclk),
.q (m4stg_opdec[4:1]),
.se (se),
.si (),
.so ()
);
dffe #(2) i_m4stg_rnd_mode (
.din (m3stg_rnd_mode[1:0]),
.en (m6stg_step),
.clk (rclk),
.q (m4stg_rnd_mode[1:0]),
.se (se),
.si (),
.so ()
);
dffe #(5) i_m4stg_id (
.din (m3stg_id[4:0]),
.en (m6stg_step),
.clk (rclk),
.q (m4stg_id[4:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- multiply stage 4.
//
///////////////////////////////////////////////////////////////////////////////
assign m4stg_fmul= m4stg_opdec[4];
assign m4stg_fmuld= m4stg_opdec[1];
dffre #(4) i_m5stg_opdec (
.din (m4stg_opdec[4:1]),
.en (m6stg_step),
.rst (reset),
.clk (rclk),
.q (m5stg_opdec[4:1]),
.se (se),
.si (),
.so ()
);
dffe #(2) i_m5stg_rnd_mode (
.din (m4stg_rnd_mode[1:0]),
.en (m6stg_step),
.clk (rclk),
.q (m5stg_rnd_mode[1:0]),
.se (se),
.si (),
.so ()
);
dffe #(5) i_m5stg_id (
.din (m4stg_id[4:0]),
.en (m6stg_step),
.clk (rclk),
.q (m5stg_id[4:0]),
.se (se),
.si (),
.so ()
);
dffre #(1) i_m5stg_fmulda (
.din (m4stg_fmuld),
.en (m6stg_step),
.rst (reset),
.clk (rclk),
.q (m5stg_fmulda),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- multiply stage 5.
//
///////////////////////////////////////////////////////////////////////////////
assign m5stg_fmul= m5stg_opdec[4];
assign m5stg_fmuls= m5stg_opdec[2];
assign m5stg_fmuld= m5stg_opdec[1];
assign m6stg_fmul_in= (m6stg_stepa && (!reset)
&& m5stg_fmul)
|| ((!m6stg_stepa) && (!reset)
&& m6stg_fmul);
dffre #(3) i_m6stg_opdec (
.din (m5stg_opdec[4:2]),
.en (m6stg_step),
.rst (reset),
.clk (rclk),
.q (m6stg_opdec[4:2]),
.se (se),
.si (),
.so ()
);
assign m6stg_id_in[9:0]= ({10{m6stg_stepa}}
& {(m5stg_id[4:2]==3'o7),
(m5stg_id[4:2]==3'o6),
(m5stg_id[4:2]==3'o5),
(m5stg_id[4:2]==3'o4),
(m5stg_id[4:2]==3'o3),
(m5stg_id[4:2]==3'o2),
(m5stg_id[4:2]==3'o1),
(m5stg_id[4:2]==3'o0),
m5stg_id[1:0]})
| ({10{(!m6stg_stepa)}}
& m6stg_id[9:0]);
dffe #(10) i_m6stg_id (
.din (m6stg_id_in[9:0]),
.en (m6stg_step),
.clk (rclk),
.q (m6stg_id[9:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- multiply pipeline output.
//
///////////////////////////////////////////////////////////////////////////////
assign m6stg_fmul= m6stg_opdec[4];
assign m6stg_fmul_dbl_dst= m6stg_opdec[3];
assign m6stg_fmuls= m6stg_opdec[2];
assign m6stg_hold= m6stg_fmul && (!mul_dest_rdy);
assign m6stg_holda= m6stg_fmul && (!mul_dest_rdya);
assign m6stg_step= (!m6stg_hold);
assign m6stg_stepa= (!m6stg_holda);
// Austin update
// Power management update
assign mul_pipe_active_in = // mul pipe is executing a valid instr
m1stg_fmul || m2stg_fmul || m3astg_opdec[4] || m3bstg_opdec[4] ||
m3stg_fmul || m4stg_fmul || m5stg_fmul || m6stg_fmul;
dffre #(1) i_mul_pipe_active (
.din (mul_pipe_active_in),
.en (1'b1),
.rst (reset),
.clk (rclk),
.q (mul_pipe_active),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Multiply sign and exception logic.
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
//
// Multiply sign inputs.
//
///////////////////////////////////////////////////////////////////////////////
dffe #(1) i_m1stg_sign1 (
.din (inq_in1_63),
.en (m6stg_step),
.clk (rclk),
.q (m1stg_sign1),
.se (se),
.si (),
.so ()
);
dffe #(1) i_m1stg_sign2 (
.din (inq_in2_63),
.en (m6stg_step),
.clk (rclk),
.q (m1stg_sign2),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Multiply sign and exceptions.
//
// Multiply stage 1.
//
///////////////////////////////////////////////////////////////////////////////
dffe #(1) i_m2stg_sign1 (
.din (m1stg_sign1),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_sign1),
.se (se),
.si (),
.so ()
);
dffe #(1) i_m2stg_sign2 (
.din (m1stg_sign2),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_sign2),
.se (se),
.si (),
.so ()
);
assign m1stg_of_mask= (!m1stg_infnan_in);
dffe #(1) i_m2stg_of_mask (
.din (m1stg_of_mask),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_of_mask),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Multiply sign and exceptions.
//
// Multiply stage 2.
//
///////////////////////////////////////////////////////////////////////////////
assign m2stg_sign= ((m2stg_sign1
&& (!m2stg_snan_in2)
&& (!(m2stg_qnan_in2 && (!m2stg_snan_in1))))
^ (m2stg_sign2
&& (!(m2stg_snan_in1 && (!m2stg_snan_in2)))
&& (!(m2stg_qnan_in1 && (!m2stg_nan_in2)))))
&& (!(m2stg_inf_in && m2stg_zero_in));
dffe #(1) i_m3astg_sign (
.din (m2stg_sign),
.en (m6stg_step),
.clk (rclk),
.q (m3astg_sign),
.se (se),
.si (),
.so ()
);
assign m2stg_nv= m2stg_snan_in1
|| m2stg_snan_in2
|| (m2stg_zero_in1 && m2stg_inf_in2)
|| (m2stg_inf_in1 && m2stg_zero_in2);
dffe #(1) i_m3astg_nv (
.din (m2stg_nv),
.en (m6stg_step),
.clk (rclk),
.q (m3astg_nv),
.se (se),
.si (),
.so ()
);
dffe #(1) i_m3astg_of_mask (
.din (m2stg_of_mask),
.en (m6stg_step),
.clk (rclk),
.q (m3astg_of_mask),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Multiply sign and exceptions.
//
// Multiply stage 3a.
//
///////////////////////////////////////////////////////////////////////////////
dffe #(1) i_m3bstg_sign (
.din (m3astg_sign),
.en (m6stg_step),
.clk (rclk),
.q (m3bstg_sign),
.se (se),
.si (),
.so ()
);
dffe #(1) i_m3bstg_nv (
.din (m3astg_nv),
.en (m6stg_step),
.clk (rclk),
.q (m3bstg_nv),
.se (se),
.si (),
.so ()
);
dffe #(1) i_m3bstg_of_mask (
.din (m3astg_of_mask),
.en (m6stg_step),
.clk (rclk),
.q (m3bstg_of_mask),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Multiply sign and exceptions.
//
// Multiply stage 3b.
//
///////////////////////////////////////////////////////////////////////////////
dffe #(1) i_m3stg_sign (
.din (m3bstg_sign),
.en (m6stg_step),
.clk (rclk),
.q (m3stg_sign),
.se (se),
.si (),
.so ()
);
dffe #(1) i_m3stg_nv (
.din (m3bstg_nv),
.en (m6stg_step),
.clk (rclk),
.q (m3stg_nv),
.se (se),
.si (),
.so ()
);
dffe #(1) i_m3stg_of_mask (
.din (m3bstg_of_mask),
.en (m6stg_step),
.clk (rclk),
.q (m3stg_of_mask),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Multiply sign and exceptions.
//
// Multiply stage 3.
//
///////////////////////////////////////////////////////////////////////////////
dffe #(1) i_m4stg_sign (
.din (m3stg_sign),
.en (m6stg_step),
.clk (rclk),
.q (m4stg_sign),
.se (se),
.si (),
.so ()
);
dffe #(1) i_m4stg_nv (
.din (m3stg_nv),
.en (m6stg_step),
.clk (rclk),
.q (m4stg_nv),
.se (se),
.si (),
.so ()
);
dffe #(1) i_m4stg_of_mask (
.din (m3stg_of_mask),
.en (m6stg_step),
.clk (rclk),
.q (m4stg_of_mask),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Multiply sign and exceptions.
//
// Multiply stage 4.
//
///////////////////////////////////////////////////////////////////////////////
dffe #(1) i_m5stg_sign (
.din (m4stg_sign),
.en (m6stg_step),
.clk (rclk),
.q (m5stg_sign),
.se (se),
.si (),
.so ()
);
dffe #(1) i_m5stg_nv (
.din (m4stg_nv),
.en (m6stg_step),
.clk (rclk),
.q (m5stg_nv),
.se (se),
.si (),
.so ()
);
dffe #(1) i_m5stg_of_mask (
.din (m4stg_of_mask),
.en (m6stg_step),
.clk (rclk),
.q (m5stg_of_mask),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Multiply sign and exceptions.
//
// Multiply stage 5.
//
///////////////////////////////////////////////////////////////////////////////
dffe #(1) i_mul_sign_out (
.din (m5stg_sign),
.en (m6stg_step),
.clk (rclk),
.q (mul_sign_out),
.se (se),
.si (),
.so ()
);
dffe #(1) i_mul_nv_out (
.din (m5stg_nv),
.en (m6stg_step),
.clk (rclk),
.q (mul_nv_out),
.se (se),
.si (),
.so ()
);
assign m5stg_in_of= ((!m5stg_exp[12])
&& m5stg_fmuld
&& (m5stg_exp[11] || (&m5stg_exp[10:0]))
&& m5stg_of_mask)
|| ((!m5stg_exp[12])
&& m5stg_fmuls
&& ((|m5stg_exp[11:8]) || (&m5stg_exp[7:0]))
&& m5stg_of_mask);
assign mul_of_out_tmp1_in= ((!m5stg_exp[12])
&& m5stg_fmuld
&& (&m5stg_exp[10:1])
&& m5stg_rndup
&& m5stg_of_mask)
|| ((!m5stg_exp[12])
&& m5stg_fmuls
&& (&m5stg_exp[7:1])
&& m5stg_rndup
&& m5stg_of_mask);
dffe #(1) i_mul_of_out_tmp1 (
.din (mul_of_out_tmp1_in),
.en (m6stg_step),
.clk (rclk),
.q (mul_of_out_tmp1),
.se (se),
.si (),
.so ()
);
dffe #(1) i_mul_of_out_tmp2 (
.din (m5stg_in_of),
.en (m6stg_step),
.clk (rclk),
.q (mul_of_out_tmp2),
.se (se),
.si (),
.so ()
);
dffe #(1) i_mul_of_out_cout (
.din (m5stg_fracadd_cout),
.en (m6stg_step),
.clk (rclk),
.q (mul_of_out_cout),
.se (se),
.si (),
.so ()
);
assign mul_of_out= mul_of_out_tmp2
|| (mul_of_out_tmp1 && mul_of_out_cout);
assign mul_uf_out_in= (m5stg_exp[12] || (!(|m5stg_exp[11:0])))
&& m5stg_frac_neq_0;
dffe #(1) i_mul_uf_out (
.din (mul_uf_out_in),
.en (m6stg_step),
.clk (rclk),
.q (mul_uf_out),
.se (se),
.si (),
.so ()
);
assign mul_nx_out_in= (m5stg_fmuld && m5stg_frac_dbl_nx)
|| (m5stg_fmuls && m5stg_frac_sng_nx);
dffe #(1) i_mul_nx_out (
.din (mul_nx_out_in),
.en (m6stg_step),
.clk (rclk),
.q (mul_nx_out),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Multiply exception output.
//
///////////////////////////////////////////////////////////////////////////////
// Austin update
// Overflow is always accompanied by inexact.
// Previously this was handled within the FFU.
// assign mul_exc_out[4:0]= {mul_nv_out, mul_of_out, mul_uf_out, 1'b0, mul_nx_out};
assign mul_exc_out[4:0] =
{mul_nv_out,
mul_of_out,
mul_uf_out,
1'b0,
(mul_nx_out || mul_of_out)}; // Overflow is always accompanied by inexact
///////////////////////////////////////////////////////////////////////////////
//
// Multiply pipeline control logic.
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
//
// Select lines- multiply normalization and special input injection.
//
// Multiply stage 1.
//
///////////////////////////////////////////////////////////////////////////////
assign m2stg_frac1_dbl_norm= m1stg_norm_dbl_in1
&& ((!(m1stg_infnan_dbl_in1 || m1stg_infnan_dbl_in2))
|| (m1stg_snan_dbl_in1 && (!m1stg_snan_dbl_in2))
|| (m1stg_qnan_dbl_in1 && (!m1stg_nan_dbl_in2)));
assign m2stg_frac1_dbl_dnrm= m1stg_denorm_dbl_in1
&& (!(m1stg_infnan_dbl_in1 || m1stg_infnan_dbl_in2));
assign m2stg_frac1_sng_norm= m1stg_norm_sng_in1
&& ((!(m1stg_infnan_sng_in1 || m1stg_infnan_sng_in2))
|| (m1stg_snan_sng_in1 && (!m1stg_snan_sng_in2))
|| (m1stg_qnan_sng_in1 && (!m1stg_nan_sng_in2)));
assign m2stg_frac1_sng_dnrm= m1stg_denorm_sng_in1
&& (!(m1stg_infnan_sng_in1 || m1stg_infnan_sng_in2));
assign m2stg_frac1_inf= (m1stg_inf_in && (!m1stg_nan_in1) && (!m1stg_nan_in2))
|| m1stg_snan_in2
|| (m1stg_qnan_in2 && (!m1stg_snan_in1));
assign m2stg_frac2_dbl_norm= m1stg_norm_dbl_in2
&& ((!(m1stg_infnan_dbl_in1 || m1stg_infnan_dbl_in2))
|| m1stg_snan_dbl_in2
|| (m1stg_qnan_dbl_in2 && (!m1stg_snan_dbl_in1)));
assign m2stg_frac2_dbl_dnrm= m1stg_denorm_dbl_in2
&& (!(m1stg_infnan_dbl_in1 || m1stg_infnan_dbl_in2));
assign m2stg_frac2_sng_norm= m1stg_norm_sng_in2
&& ((!(m1stg_infnan_sng_in1 || m1stg_infnan_sng_in2))
|| m1stg_snan_sng_in2
|| (m1stg_qnan_sng_in2 && (!m1stg_snan_sng_in1)));
assign m2stg_frac2_sng_dnrm= m1stg_denorm_sng_in2
&& (!(m1stg_infnan_sng_in1 || m1stg_infnan_sng_in2));
assign m2stg_frac2_inf= (m1stg_inf_in && (!m1stg_nan_in1) && (!m1stg_nan_in2))
|| (m1stg_snan_in1 && (!m1stg_snan_in2))
|| (m1stg_qnan_in1 && (!m1stg_nan_in2));
assign m1stg_inf_zero_in= (m1stg_inf_in1 && m1stg_zero_in2)
|| (m1stg_zero_in1 && m1stg_inf_in2);
assign m1stg_inf_zero_in_dbl= ((m1stg_inf_in1 && m1stg_zero_in2)
|| (m1stg_zero_in1 && m1stg_inf_in2))
&& m1stg_fmul_dbl_dst;
///////////////////////////////////////////////////////////////////////////////
//
// Select lines and control logic- multiply leading 0 counts.
//
// Multiply stage 1.
//
///////////////////////////////////////////////////////////////////////////////
assign m2stg_ld0_1_in[5:0]= ({6{(m1stg_denorm_in1 && (!m1stg_infnan_in))}}
& m1stg_ld0_1[5:0]);
dffe #(6) i_m2stg_ld0_1 (
.din (m2stg_ld0_1_in[5:0]),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_ld0_1[5:0]),
.se (se),
.si (),
.so ()
);
assign m2stg_ld0_2_in[5:0]= ({6{(m1stg_denorm_in2 && (!m1stg_infnan_in))}}
& m1stg_ld0_2[5:0]);
dffe #(6) i_m2stg_ld0_2 (
.din (m2stg_ld0_2_in[5:0]),
.en (m6stg_step),
.clk (rclk),
.q (m2stg_ld0_2[5:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Select lines- multiply exponent adder.
//
// Multiply stage 1.
//
///////////////////////////////////////////////////////////////////////////////
assign m2stg_exp_expadd= (!m1stg_infnan_in) && (!m1stg_zero_in);
assign m2stg_exp_0bff= m1stg_fmuld && m1stg_infnan_in;
assign m2stg_exp_017f= m1stg_fmuls && m1stg_infnan_in;
assign m2stg_exp_04ff= m1stg_fsmuld && m1stg_infnan_in;
assign m2stg_exp_zero= m1stg_zero_in && (!m1stg_infnan_in);
///////////////////////////////////////////////////////////////////////////////
//
// Total the leading 0's.
//
// Multiply stage 2.
//
///////////////////////////////////////////////////////////////////////////////
assign m2stg_ld0[6:0]= {1'b0, m2stg_ld0_1[5:0]}
+ {1'b0, m2stg_ld0_2[5:0]};
assign m2stg_ld0_inv[6:0]= (~m2stg_ld0[6:0]);
dffe #(7) i_m3astg_ld0_inv (
.din (m2stg_ld0_inv[6:0]),
.en (m6stg_step),
.clk (rclk),
.q (m3astg_ld0_inv[6:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Leading 0's.
//
// Multiply stage 3a.
//
///////////////////////////////////////////////////////////////////////////////
dffe #(7) i_m3bstg_ld0_inv (
.din (m3astg_ld0_inv[6:0]),
.en (m6stg_step),
.clk (rclk),
.q (m3bstg_ld0_inv[6:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Post-normalization/denormalization shift count and direction.
//
// Multiply stage 3.
//
///////////////////////////////////////////////////////////////////////////////
dffe #(1) i_m4stg_expadd_eq_0 (
.din (m3stg_expadd_eq_0),
.en (m6stg_step),
.clk (rclk),
.q (m4stg_expadd_eq_0),
.se (se),
.si (),
.so ()
);
assign m3stg_exp_lte_0= (!(|m3stg_exp[11:0])) || m3stg_exp[12];
assign m4stg_right_shift_in= (!m3stg_expadd_lte_0_inv) && m3stg_exp_lte_0;
dffe #(1) i_m4stg_right_shift (
.din (m4stg_right_shift_in),
.en (m6stg_step),
.clk (rclk),
.q (m4stg_right_shift),
.se (se),
.si (),
.so ()
);
assign m3stg_exp_minus1[5:0]= m3stg_exp[5:0]
+ 6'h3f;
assign m3stg_exp_inv_plus2[5:0]= (~m3stg_exp[5:0])
+ 6'h02;
assign m3stg_exp_lt_neg57= ((!(&m3stg_exp[11:6]))
|| (!(|m3stg_exp[5:3])))
&& m3stg_exp[12];
assign m4stg_sh_cnt_in[5:0]= ({6{((!m3stg_expadd_lte_0_inv)
&& (!m3stg_exp_lte_0))}}
& m3stg_exp_minus1[5:0])
| ({6{((!m3stg_expadd_lte_0_inv) && m3stg_exp_lte_0
&& m3stg_exp_lt_neg57)}}
& 6'h39)
| ({6{((!m3stg_expadd_lte_0_inv) && m3stg_exp_lte_0
&& (!m3stg_exp_lt_neg57))}}
& m3stg_exp_inv_plus2[5:0])
| ({6{m3stg_expadd_lte_0_inv}}
& (~m3stg_ld0_inv[5:0]));
///////////////////////////////////////////////////////////////////////////////
//
// Select lines and control logic- multiply shifts for
// post-normalization/denormalization.
//
// Multiply stage 4.
//
///////////////////////////////////////////////////////////////////////////////
assign m4stg_left_shift_step= (!m4stg_right_shift) && m6stg_step;
assign m4stg_right_shift_step= m4stg_right_shift && m6stg_step;
// Austin update
// uarch timing fix
// Endpoint: fpu_mul_exp_dp/i_m5stg_exp_pre2_10
// assign m4stg_inc_exp= (((!(|m4stg_exp[12:0])) && (!m4stg_right_shift)
// && m4stg_shl_54)
// || (m4stg_expadd_eq_0 && m4stg_right_shift
// && m4stg_frac_105)
// || ((!m4stg_right_shift) && m4stg_shl_55))
// && m6stg_step;
//
// assign m4stg_inc_exp_inv= (!m4stg_inc_exp) && m6stg_step;
assign m4stg_inc_exp_54 = (!(|m4stg_exp[12:0])) && (!m4stg_right_shift);
assign m4stg_inc_exp_55 = !m4stg_right_shift;
assign m4stg_inc_exp_105 = m4stg_expadd_eq_0 && m4stg_right_shift && m4stg_frac_105;
///////////////////////////////////////////////////////////////////////////////
//
// Select lines and control logic- multiply rounding.
//
// Multiply stage 5.
//
///////////////////////////////////////////////////////////////////////////////
assign m5stg_rndup= ((((m5stg_rnd_mode[1:0]==2'b10) && (!m5stg_sign)
&& (m5stg_frac[2:0]!=3'b0))
|| ((m5stg_rnd_mode[1:0]==2'b11) && m5stg_sign
&& (m5stg_frac[2:0]!=3'b0))
|| ((m5stg_rnd_mode[1:0]==2'b00)
&& m5stg_frac[2]
&& ((m5stg_frac[1:0]!=2'b0)
|| m5stg_frac[3])))
&& m5stg_fmuld)
|| ((((m5stg_rnd_mode[1:0]==2'b10) && (!m5stg_sign)
&& (m5stg_frac[31:0]!=32'b0))
|| ((m5stg_rnd_mode[1:0]==2'b11) && m5stg_sign
&& (m5stg_frac[31:0]!=32'b0))
|| ((m5stg_rnd_mode[1:0]==2'b00)
&& m5stg_frac[31]
&& ((m5stg_frac[30:0]!=31'b0)
|| m5stg_frac[32])))
&& m5stg_fmuls);
assign m5stg_to_0= (m5stg_rnd_mode[1:0]==2'b01)
|| ((m5stg_rnd_mode[1:0]==2'b10) && m5stg_sign)
|| ((m5stg_rnd_mode[1:0]==2'b11) && (!m5stg_sign));
assign m5stg_to_0_inv= (!m5stg_to_0);
assign mul_frac_out_fracadd= m5stg_rndup && (!m5stg_in_of);
assign mul_frac_out_frac= (!m5stg_rndup) && (!m5stg_in_of);
assign mul_exp_out_exp_plus1= m5stg_rndup && (!m5stg_in_of);
assign mul_exp_out_exp= (!m5stg_rndup) && (!m5stg_in_of);
endmodule
|
`timescale 1ns / 1ps
// @input
// clk_src: clock source
// switch_power: electric power
// switch_en: pause switch
// sum_count: time limit
// count_start_flag: start signal
// @output
// count_end_flag: end signal
// count: counting of timer
module timer
#(parameter WIDTH = 32, CLK_CH = 25, TIME_SCORE = 2)
( input [31:0]clk_src,
input switch_power,
input switch_en,
input [(WIDTH-1):0]sum_count,
input count_start_flag,
output reg count_end_flag,
output [(WIDTH-1):0] count
);
reg init_flag;
wire real_clk;
wire [(WIDTH-1):0] sum_count_mode;
reg [(WIDTH-1):0] count_mode;
reg [(WIDTH-1):0] reverse_count;
// if change TIME_SCORE, you can change simulate time step
assign sum_count_mode = sum_count * TIME_SCORE;
assign count = count_mode / TIME_SCORE;
initial begin
count_end_flag <= 0;
init_flag <= 1;
reverse_count <= 0;
count_mode <= 0;
end
//information: count has a second delay
assign real_clk = (switch_power & count_start_flag & !init_flag) ? clk_src[CLK_CH] : clk_src[0];
always @(posedge real_clk) begin
if (switch_power & count_start_flag) begin
if(init_flag) begin
reverse_count = 0;
count_mode = sum_count_mode;
// when fisrt enter this module, start to initiate
init_flag = 0;
end else if (switch_en) begin
//add time score
if (sum_count_mode >= reverse_count) begin
count_mode = sum_count_mode - reverse_count;
reverse_count = reverse_count + 1;
end else begin
count_end_flag = 1;
end
end
end else begin
count_end_flag <= 0;
reverse_count <= 0;
count_mode <= 0;
// when leave this module, reset init_flag to 1,
// making next time enter this module, all var of this module can be reset
init_flag <= 1;
end
end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O311A_TB_V
`define SKY130_FD_SC_HD__O311A_TB_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o311a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 B1 = 1'b1;
#280 C1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 B1 = 1'b0;
#460 C1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 C1 = 1'b1;
#660 B1 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 C1 = 1'bx;
#840 B1 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_hd__o311a dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O311A_TB_V
|
/*
Copyright (c) 2015-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* I2C master
*/
module i2c_master (
input wire clk,
input wire rst,
/*
* Host interface
*/
input wire [6:0] cmd_address,
input wire cmd_start,
input wire cmd_read,
input wire cmd_write,
input wire cmd_write_multiple,
input wire cmd_stop,
input wire cmd_valid,
output wire cmd_ready,
input wire [7:0] data_in,
input wire data_in_valid,
output wire data_in_ready,
input wire data_in_last,
output wire [7:0] data_out,
output wire data_out_valid,
input wire data_out_ready,
output wire data_out_last,
/*
* I2C interface
*/
input wire scl_i,
output wire scl_o,
output wire scl_t,
input wire sda_i,
output wire sda_o,
output wire sda_t,
/*
* Status
*/
output wire busy,
output wire bus_control,
output wire bus_active,
output wire missed_ack,
/*
* Configuration
*/
input wire [15:0] prescale,
input wire stop_on_idle
);
/*
I2C
Read
__ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ __
sda \__/_6_X_5_X_4_X_3_X_2_X_1_X_0_\_R___A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_\_A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_\_A____/
____ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____
scl ST \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ SP
Write
__ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ __
sda \__/_6_X_5_X_4_X_3_X_2_X_1_X_0_/ W \_A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_\_A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_/ N \__/
____ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____
scl ST \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ SP
Commands:
read
read data byte
set start to force generation of a start condition
start is implied when bus is inactive or active with write or different address
set stop to issue a stop condition after reading current byte
if stop is set with read command, then data_out_last will be set
write
write data byte
set start to force generation of a start condition
start is implied when bus is inactive or active with read or different address
set stop to issue a stop condition after writing current byte
write multiple
write multiple data bytes (until data_in_last)
set start to force generation of a start condition
start is implied when bus is inactive or active with read or different address
set stop to issue a stop condition after writing block
stop
issue stop condition if bus is active
Status:
busy
module is communicating over the bus
bus_control
module has control of bus in active state
bus_active
bus is active, not necessarily controlled by this module
missed_ack
strobed when a slave ack is missed
Parameters:
prescale
set prescale to 1/4 of the minimum clock period in units
of input clk cycles (prescale = Fclk / (FI2Cclk * 4))
stop_on_idle
automatically issue stop when command input is not valid
Example of interfacing with tristate pins:
(this will work for any tristate bus)
assign scl_i = scl_pin;
assign scl_pin = scl_t ? 1'bz : scl_o;
assign sda_i = sda_pin;
assign sda_pin = sda_t ? 1'bz : sda_o;
Equivalent code that does not use *_t connections:
(we can get away with this because I2C is open-drain)
assign scl_i = scl_pin;
assign scl_pin = scl_o ? 1'bz : 1'b0;
assign sda_i = sda_pin;
assign sda_pin = sda_o ? 1'bz : 1'b0;
Example of two interconnected I2C devices:
assign scl_1_i = scl_1_o & scl_2_o;
assign scl_2_i = scl_1_o & scl_2_o;
assign sda_1_i = sda_1_o & sda_2_o;
assign sda_2_i = sda_1_o & sda_2_o;
Example of two I2C devices sharing the same pins:
assign scl_1_i = scl_pin;
assign scl_2_i = scl_pin;
assign scl_pin = (scl_1_o & scl_2_o) ? 1'bz : 1'b0;
assign sda_1_i = sda_pin;
assign sda_2_i = sda_pin;
assign sda_pin = (sda_1_o & sda_2_o) ? 1'bz : 1'b0;
Notes:
scl_o should not be connected directly to scl_i, only via AND logic or a tristate
I/O pin. This would prevent devices from stretching the clock period.
*/
localparam [4:0]
STATE_IDLE = 4'd0,
STATE_ACTIVE_WRITE = 4'd1,
STATE_ACTIVE_READ = 4'd2,
STATE_START_WAIT = 4'd3,
STATE_START = 4'd4,
STATE_ADDRESS_1 = 4'd5,
STATE_ADDRESS_2 = 4'd6,
STATE_WRITE_1 = 4'd7,
STATE_WRITE_2 = 4'd8,
STATE_WRITE_3 = 4'd9,
STATE_READ = 4'd10,
STATE_STOP = 4'd11;
reg [4:0] state_reg = STATE_IDLE, state_next;
localparam [4:0]
PHY_STATE_IDLE = 5'd0,
PHY_STATE_ACTIVE = 5'd1,
PHY_STATE_REPEATED_START_1 = 5'd2,
PHY_STATE_REPEATED_START_2 = 5'd3,
PHY_STATE_START_1 = 5'd4,
PHY_STATE_START_2 = 5'd5,
PHY_STATE_WRITE_BIT_1 = 5'd6,
PHY_STATE_WRITE_BIT_2 = 5'd7,
PHY_STATE_WRITE_BIT_3 = 5'd8,
PHY_STATE_READ_BIT_1 = 5'd9,
PHY_STATE_READ_BIT_2 = 5'd10,
PHY_STATE_READ_BIT_3 = 5'd11,
PHY_STATE_READ_BIT_4 = 5'd12,
PHY_STATE_STOP_1 = 5'd13,
PHY_STATE_STOP_2 = 5'd14,
PHY_STATE_STOP_3 = 5'd15;
reg [4:0] phy_state_reg = STATE_IDLE, phy_state_next;
reg phy_start_bit;
reg phy_stop_bit;
reg phy_write_bit;
reg phy_read_bit;
reg phy_release_bus;
reg phy_tx_data;
reg phy_rx_data_reg = 1'b0, phy_rx_data_next;
reg [6:0] addr_reg = 7'd0, addr_next;
reg [7:0] data_reg = 8'd0, data_next;
reg last_reg = 1'b0, last_next;
reg mode_read_reg = 1'b0, mode_read_next;
reg mode_write_multiple_reg = 1'b0, mode_write_multiple_next;
reg mode_stop_reg = 1'b0, mode_stop_next;
reg [16:0] delay_reg = 16'd0, delay_next;
reg delay_scl_reg = 1'b0, delay_scl_next;
reg delay_sda_reg = 1'b0, delay_sda_next;
reg [3:0] bit_count_reg = 4'd0, bit_count_next;
reg cmd_ready_reg = 1'b0, cmd_ready_next;
reg data_in_ready_reg = 1'b0, data_in_ready_next;
reg [7:0] data_out_reg = 8'd0, data_out_next;
reg data_out_valid_reg = 1'b0, data_out_valid_next;
reg data_out_last_reg = 1'b0, data_out_last_next;
reg scl_i_reg = 1'b1;
reg sda_i_reg = 1'b1;
reg scl_o_reg = 1'b1, scl_o_next;
reg sda_o_reg = 1'b1, sda_o_next;
reg last_scl_i_reg = 1'b1;
reg last_sda_i_reg = 1'b1;
reg busy_reg = 1'b0;
reg bus_active_reg = 1'b0;
reg bus_control_reg = 1'b0, bus_control_next;
reg missed_ack_reg = 1'b0, missed_ack_next;
assign cmd_ready = cmd_ready_reg;
assign data_in_ready = data_in_ready_reg;
assign data_out = data_out_reg;
assign data_out_valid = data_out_valid_reg;
assign data_out_last = data_out_last_reg;
assign scl_o = scl_o_reg;
assign scl_t = scl_o_reg;
assign sda_o = sda_o_reg;
assign sda_t = sda_o_reg;
assign busy = busy_reg;
assign bus_active = bus_active_reg;
assign bus_control = bus_control_reg;
assign missed_ack = missed_ack_reg;
wire scl_posedge = scl_i_reg & ~last_scl_i_reg;
wire scl_negedge = ~scl_i_reg & last_scl_i_reg;
wire sda_posedge = sda_i_reg & ~last_sda_i_reg;
wire sda_negedge = ~sda_i_reg & last_sda_i_reg;
wire start_bit = sda_negedge & scl_i_reg;
wire stop_bit = sda_posedge & scl_i_reg;
always @* begin
state_next = STATE_IDLE;
phy_start_bit = 1'b0;
phy_stop_bit = 1'b0;
phy_write_bit = 1'b0;
phy_read_bit = 1'b0;
phy_tx_data = 1'b0;
phy_release_bus = 1'b0;
addr_next = addr_reg;
data_next = data_reg;
last_next = last_reg;
mode_read_next = mode_read_reg;
mode_write_multiple_next = mode_write_multiple_reg;
mode_stop_next = mode_stop_reg;
bit_count_next = bit_count_reg;
cmd_ready_next = 1'b0;
data_in_ready_next = 1'b0;
data_out_next = data_out_reg;
data_out_valid_next = data_out_valid_reg & ~data_out_ready;
data_out_last_next = data_out_last_reg;
missed_ack_next = 1'b0;
// generate delays
if (phy_state_reg != PHY_STATE_IDLE && phy_state_reg != PHY_STATE_ACTIVE) begin
// wait for phy operation
state_next = state_reg;
end else begin
// process states
case (state_reg)
STATE_IDLE: begin
// line idle
cmd_ready_next = 1'b1;
if (cmd_ready & cmd_valid) begin
// command valid
if (cmd_read ^ (cmd_write | cmd_write_multiple)) begin
// read or write command
addr_next = cmd_address;
mode_read_next = cmd_read;
mode_write_multiple_next = cmd_write_multiple;
mode_stop_next = cmd_stop;
cmd_ready_next = 1'b0;
// start bit
if (bus_active) begin
state_next = STATE_START_WAIT;
end else begin
phy_start_bit = 1'b1;
bit_count_next = 4'd8;
state_next = STATE_ADDRESS_1;
end
end else begin
// invalid or unspecified - ignore
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_IDLE;
end
end
STATE_ACTIVE_WRITE: begin
// line active with current address and read/write mode
cmd_ready_next = 1'b1;
if (cmd_ready & cmd_valid) begin
// command valid
if (cmd_read ^ (cmd_write | cmd_write_multiple)) begin
// read or write command
addr_next = cmd_address;
mode_read_next = cmd_read;
mode_write_multiple_next = cmd_write_multiple;
mode_stop_next = cmd_stop;
cmd_ready_next = 1'b0;
if (cmd_start || cmd_address != addr_reg || cmd_read) begin
// address or mode mismatch or forced start - repeated start
// repeated start bit
phy_start_bit = 1'b1;
bit_count_next = 4'd8;
state_next = STATE_ADDRESS_1;
end else begin
// address and mode match
// start write
data_in_ready_next = 1'b1;
state_next = STATE_WRITE_1;
end
end else if (cmd_stop && !(cmd_read || cmd_write || cmd_write_multiple)) begin
// stop command
phy_stop_bit = 1'b1;
state_next = STATE_IDLE;
end else begin
// invalid or unspecified - ignore
state_next = STATE_ACTIVE_WRITE;
end
end else begin
if (stop_on_idle & cmd_ready & ~cmd_valid) begin
// no waiting command and stop_on_idle selected, issue stop condition
phy_stop_bit = 1'b1;
state_next = STATE_IDLE;
end else begin
state_next = STATE_ACTIVE_WRITE;
end
end
end
STATE_ACTIVE_READ: begin
// line active to current address
cmd_ready_next = ~data_out_valid;
if (cmd_ready & cmd_valid) begin
// command valid
if (cmd_read ^ (cmd_write | cmd_write_multiple)) begin
// read or write command
addr_next = cmd_address;
mode_read_next = cmd_read;
mode_write_multiple_next = cmd_write_multiple;
mode_stop_next = cmd_stop;
cmd_ready_next = 1'b0;
if (cmd_start || cmd_address != addr_reg || cmd_write) begin
// address or mode mismatch or forced start - repeated start
// write nack for previous read
phy_write_bit = 1'b1;
phy_tx_data = 1'b1;
// repeated start bit
state_next = STATE_START;
end else begin
// address and mode match
// write ack for previous read
phy_write_bit = 1'b1;
phy_tx_data = 1'b0;
// start next read
bit_count_next = 4'd8;
data_next = 8'd0;
state_next = STATE_READ;
end
end else if (cmd_stop && !(cmd_read || cmd_write || cmd_write_multiple)) begin
// stop command
// write nack for previous read
phy_write_bit = 1'b1;
phy_tx_data = 1'b1;
// send stop bit
state_next = STATE_STOP;
end else begin
// invalid or unspecified - ignore
state_next = STATE_ACTIVE_READ;
end
end else begin
if (stop_on_idle & cmd_ready & ~cmd_valid) begin
// no waiting command and stop_on_idle selected, issue stop condition
// write ack for previous read
phy_write_bit = 1'b1;
phy_tx_data = 1'b1;
// send stop bit
state_next = STATE_STOP;
end else begin
state_next = STATE_ACTIVE_READ;
end
end
end
STATE_START_WAIT: begin
// wait for bus idle
if (bus_active) begin
state_next = STATE_START_WAIT;
end else begin
// bus is idle, take control
phy_start_bit = 1'b1;
bit_count_next = 4'd8;
state_next = STATE_ADDRESS_1;
end
end
STATE_START: begin
// send start bit
phy_start_bit = 1'b1;
bit_count_next = 4'd8;
state_next = STATE_ADDRESS_1;
end
STATE_ADDRESS_1: begin
// send address
bit_count_next = bit_count_reg - 1;
if (bit_count_reg > 1) begin
// send address
phy_write_bit = 1'b1;
phy_tx_data = addr_reg[bit_count_reg-2];
state_next = STATE_ADDRESS_1;
end else if (bit_count_reg > 0) begin
// send read/write bit
phy_write_bit = 1'b1;
phy_tx_data = mode_read_reg;
state_next = STATE_ADDRESS_1;
end else begin
// read ack bit
phy_read_bit = 1'b1;
state_next = STATE_ADDRESS_2;
end
end
STATE_ADDRESS_2: begin
// read ack bit
missed_ack_next = phy_rx_data_reg;
if (mode_read_reg) begin
// start read
bit_count_next = 4'd8;
data_next = 1'b0;
state_next = STATE_READ;
end else begin
// start write
data_in_ready_next = 1'b1;
state_next = STATE_WRITE_1;
end
end
STATE_WRITE_1: begin
data_in_ready_next = 1'b1;
if (data_in_ready & data_in_valid) begin
// got data, start write
data_next = data_in;
last_next = data_in_last;
bit_count_next = 4'd8;
data_in_ready_next = 1'b0;
state_next = STATE_WRITE_2;
end else begin
// wait for data
state_next = STATE_WRITE_1;
end
end
STATE_WRITE_2: begin
// send data
bit_count_next = bit_count_reg - 1;
if (bit_count_reg > 0) begin
// write data bit
phy_write_bit = 1'b1;
phy_tx_data = data_reg[bit_count_reg-1];
state_next = STATE_WRITE_2;
end else begin
// read ack bit
phy_read_bit = 1'b1;
state_next = STATE_WRITE_3;
end
end
STATE_WRITE_3: begin
// read ack bit
missed_ack_next = phy_rx_data_reg;
if (mode_write_multiple_reg && !last_reg) begin
// more to write
state_next = STATE_WRITE_1;
end else if (mode_stop_reg) begin
// last cycle and stop selected
phy_stop_bit = 1'b1;
state_next = STATE_IDLE;
end else begin
// otherwise, return to bus active state
state_next = STATE_ACTIVE_WRITE;
end
end
STATE_READ: begin
// read data
bit_count_next = bit_count_reg - 1;
data_next = {data_reg[6:0], phy_rx_data_reg};
if (bit_count_reg > 0) begin
// read next bit
phy_read_bit = 1'b1;
state_next = STATE_READ;
end else begin
// output data word
data_out_next = data_next;
data_out_valid_next = 1'b1;
data_out_last_next = 1'b0;
if (mode_stop_reg) begin
// send nack and stop
data_out_last_next = 1'b1;
phy_write_bit = 1'b1;
phy_tx_data = 1'b1;
state_next = STATE_STOP;
end else begin
// return to bus active state
state_next = STATE_ACTIVE_READ;
end
end
end
STATE_STOP: begin
// send stop bit
phy_stop_bit = 1'b1;
state_next = STATE_IDLE;
end
endcase
end
end
always @* begin
phy_state_next = PHY_STATE_IDLE;
phy_rx_data_next = phy_rx_data_reg;
delay_next = delay_reg;
delay_scl_next = delay_scl_reg;
delay_sda_next = delay_sda_reg;
scl_o_next = scl_o_reg;
sda_o_next = sda_o_reg;
bus_control_next = bus_control_reg;
if (phy_release_bus) begin
// release bus and return to idle state
sda_o_next = 1'b1;
scl_o_next = 1'b1;
delay_scl_next = 1'b0;
delay_sda_next = 1'b0;
delay_next = 1'b0;
phy_state_next = PHY_STATE_IDLE;
end else if (delay_scl_reg) begin
// wait for SCL to match command
delay_scl_next = scl_o_reg & ~scl_i_reg;
phy_state_next = phy_state_reg;
end else if (delay_sda_reg) begin
// wait for SDA to match command
delay_sda_next = sda_o_reg & ~sda_i_reg;
phy_state_next = phy_state_reg;
end else if (delay_reg > 0) begin
// time delay
delay_next = delay_reg - 1;
phy_state_next = phy_state_reg;
end else begin
case (phy_state_reg)
PHY_STATE_IDLE: begin
// bus idle - wait for start command
sda_o_next = 1'b1;
scl_o_next = 1'b1;
if (phy_start_bit) begin
sda_o_next = 1'b0;
delay_next = prescale;
phy_state_next = PHY_STATE_START_1;
end else begin
phy_state_next = PHY_STATE_IDLE;
end
end
PHY_STATE_ACTIVE: begin
// bus active
if (phy_start_bit) begin
sda_o_next = 1'b1;
delay_next = prescale;
phy_state_next = PHY_STATE_REPEATED_START_1;
end else if (phy_write_bit) begin
sda_o_next = phy_tx_data;
delay_next = prescale;
phy_state_next = PHY_STATE_WRITE_BIT_1;
end else if (phy_read_bit) begin
sda_o_next = 1'b1;
delay_next = prescale;
phy_state_next = PHY_STATE_READ_BIT_1;
end else if (phy_stop_bit) begin
sda_o_next = 1'b0;
delay_next = prescale;
phy_state_next = PHY_STATE_STOP_1;
end else begin
phy_state_next = PHY_STATE_ACTIVE;
end
end
PHY_STATE_REPEATED_START_1: begin
// generate repeated start bit
// ______
// sda XXX/ \_______
// _______
// scl ______/ \___
//
scl_o_next = 1'b1;
delay_scl_next = 1'b1;
delay_next = prescale;
phy_state_next = PHY_STATE_REPEATED_START_2;
end
PHY_STATE_REPEATED_START_2: begin
// generate repeated start bit
// ______
// sda XXX/ \_______
// _______
// scl ______/ \___
//
sda_o_next = 1'b0;
delay_next = prescale;
phy_state_next = PHY_STATE_START_1;
end
PHY_STATE_START_1: begin
// generate start bit
// ___
// sda \_______
// _______
// scl \___
//
scl_o_next = 1'b0;
delay_next = prescale;
phy_state_next = PHY_STATE_START_2;
end
PHY_STATE_START_2: begin
// generate start bit
// ___
// sda \_______
// _______
// scl \___
//
bus_control_next = 1'b1;
phy_state_next = PHY_STATE_ACTIVE;
end
PHY_STATE_WRITE_BIT_1: begin
// write bit
// ________
// sda X________X
// ____
// scl __/ \__
scl_o_next = 1'b1;
delay_scl_next = 1'b1;
delay_next = prescale << 1;
phy_state_next = PHY_STATE_WRITE_BIT_2;
end
PHY_STATE_WRITE_BIT_2: begin
// write bit
// ________
// sda X________X
// ____
// scl __/ \__
scl_o_next = 1'b0;
delay_next = prescale;
phy_state_next = PHY_STATE_WRITE_BIT_3;
end
PHY_STATE_WRITE_BIT_3: begin
// write bit
// ________
// sda X________X
// ____
// scl __/ \__
phy_state_next = PHY_STATE_ACTIVE;
end
PHY_STATE_READ_BIT_1: begin
// read bit
// ________
// sda X________X
// ____
// scl __/ \__
scl_o_next = 1'b1;
delay_scl_next = 1'b1;
delay_next = prescale;
phy_state_next = PHY_STATE_READ_BIT_2;
end
PHY_STATE_READ_BIT_2: begin
// read bit
// ________
// sda X________X
// ____
// scl __/ \__
phy_rx_data_next = sda_i_reg;
delay_next = prescale;
phy_state_next = PHY_STATE_READ_BIT_3;
end
PHY_STATE_READ_BIT_3: begin
// read bit
// ________
// sda X________X
// ____
// scl __/ \__
scl_o_next = 1'b0;
delay_next = prescale;
phy_state_next = PHY_STATE_READ_BIT_4;
end
PHY_STATE_READ_BIT_4: begin
// read bit
// ________
// sda X________X
// ____
// scl __/ \__
phy_state_next = PHY_STATE_ACTIVE;
end
PHY_STATE_STOP_1: begin
// stop bit
// ___
// sda XXX\_______/
// _______
// scl _______/
scl_o_next = 1'b1;
delay_scl_next = 1'b1;
delay_next = prescale;
phy_state_next = PHY_STATE_STOP_2;
end
PHY_STATE_STOP_2: begin
// stop bit
// ___
// sda XXX\_______/
// _______
// scl _______/
sda_o_next = 1'b1;
delay_next = prescale;
phy_state_next = PHY_STATE_STOP_3;
end
PHY_STATE_STOP_3: begin
// stop bit
// ___
// sda XXX\_______/
// _______
// scl _______/
bus_control_next = 1'b0;
phy_state_next = PHY_STATE_IDLE;
end
endcase
end
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
phy_state_reg <= PHY_STATE_IDLE;
delay_reg <= 16'd0;
delay_scl_reg <= 1'b0;
delay_sda_reg <= 1'b0;
cmd_ready_reg <= 1'b0;
data_in_ready_reg <= 1'b0;
data_out_valid_reg <= 1'b0;
scl_o_reg <= 1'b1;
sda_o_reg <= 1'b1;
busy_reg <= 1'b0;
bus_active_reg <= 1'b0;
bus_control_reg <= 1'b0;
missed_ack_reg <= 1'b0;
end else begin
state_reg <= state_next;
phy_state_reg <= phy_state_next;
delay_reg <= delay_next;
delay_scl_reg <= delay_scl_next;
delay_sda_reg <= delay_sda_next;
cmd_ready_reg <= cmd_ready_next;
data_in_ready_reg <= data_in_ready_next;
data_out_valid_reg <= data_out_valid_next;
scl_o_reg <= scl_o_next;
sda_o_reg <= sda_o_next;
busy_reg <= !(state_reg == STATE_IDLE || state_reg == STATE_ACTIVE_WRITE || state_reg == STATE_ACTIVE_READ) || !(phy_state_reg == PHY_STATE_IDLE || phy_state_reg == PHY_STATE_ACTIVE);
if (start_bit) begin
bus_active_reg <= 1'b1;
end else if (stop_bit) begin
bus_active_reg <= 1'b0;
end else begin
bus_active_reg <= bus_active_reg;
end
bus_control_reg <= bus_control_next;
missed_ack_reg <= missed_ack_next;
end
phy_rx_data_reg <= phy_rx_data_next;
addr_reg <= addr_next;
data_reg <= data_next;
last_reg <= last_next;
mode_read_reg <= mode_read_next;
mode_write_multiple_reg <= mode_write_multiple_next;
mode_stop_reg <= mode_stop_next;
bit_count_reg <= bit_count_next;
data_out_reg <= data_out_next;
data_out_last_reg <= data_out_last_next;
scl_i_reg <= scl_i;
sda_i_reg <= sda_i;
last_scl_i_reg <= scl_i_reg;
last_sda_i_reg <= sda_i_reg;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFBBN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__DFBBN_BEHAVIORAL_PP_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_ms__udp_dff_nsr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dfbbn (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire SET ;
wire CLK ;
wire buf_Q ;
wire CLK_N_delayed ;
wire RESET_B_delayed;
wire SET_B_delayed ;
reg notifier ;
wire D_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
not not2 (CLK , CLK_N_delayed );
sky130_fd_sc_ms__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK, D_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFBBN_BEHAVIORAL_PP_V |
//---------------------------------------------------------------------------
//-- Copyright 2015 - 2017 Systems Group, ETH Zurich
//--
//-- This hardware module is free software: you can redistribute it and/or
//-- modify it under the terms of the GNU General Public License as published
//-- by the Free Software Foundation, either version 3 of the License, or
//-- (at your option) any later version.
//--
//-- This program is distributed in the hope that it will be useful,
//-- but WITHOUT ANY WARRANTY; without even the implied warranty of
//-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
//-- GNU General Public License for more details.
//--
//-- You should have received a copy of the GNU General Public License
//-- along with this program. If not, see <http://www.gnu.org/licenses/>.
//---------------------------------------------------------------------------
`default_nettype none
module nukv_HT_Write_v2 #(
parameter KEY_WIDTH = 128,
parameter PLEN_WIDTH = 11,
parameter PADDR_WIDTH = 31,
parameter HEADER_WIDTH = 11+31,
parameter META_WIDTH = 96,
parameter DOUBLEHASH_WIDTH = 64,
parameter MEMORY_WIDTH = 512,
parameter FASTFORWARD_BITS = 5,
parameter MEM_WRITE_WAIT = 512,
parameter MEMADDR_WIDTH = 21,
parameter IS_SIM = 0
)
(
// Clock
input wire clk,
input wire rst,
input wire [KEY_WIDTH+META_WIDTH+DOUBLEHASH_WIDTH-1:0] input_data,
input wire input_valid,
output reg input_ready,
output reg [KEY_WIDTH+META_WIDTH-1:0] feedback_data,
output reg feedback_valid,
input wire feedback_ready,
output reg [KEY_WIDTH+META_WIDTH+HEADER_WIDTH-1:0] output_data,
output reg output_valid,
input wire output_ready,
output reg malloc_req_valid,
output reg[15:0] malloc_req_size,
input wire malloc_req_ready,
input wire [31:0] malloc_pointer,
input wire malloc_valid,
input wire malloc_failed,
output reg malloc_ready,
output reg [31:0] free_pointer,
output reg [15:0] free_size,
output reg free_valid,
input wire free_ready,
output reg free_wipe,
input wire [MEMORY_WIDTH-1:0] rd_data,
input wire rd_valid,
output reg rd_ready,
output reg [MEMORY_WIDTH-1:0] wr_data,
output reg wr_valid,
input wire wr_ready,
output reg [31:0] wrcmd_data,
output reg wrcmd_valid,
input wire wrcmd_ready
);
localparam [3:0]
ST_IDLE = 0,
ST_CHECK_FF = 1,
ST_CHECK_MEM = 2,
ST_CHECK_MEM_TWO = 3,
ST_SKIP_MEM = 4,
ST_SKIP_MEM_TWO = 5,
ST_CUR_ENTRY = 6,
ST_DECIDE = 7,
ST_WRITEDATA = 8,
ST_SENDOUT = 9,
ST_WAITFORMALLOC = 10,
ST_WIPE = 15;
reg [3:0] state;
localparam [3:0]
OP_IGNORE = 4'hF,
OP_GET = 0,
OP_DELCUR = 2,
OP_SETCUR = 1,
OP_SCAN = 12,
OP_FLUSH = 8,
OP_CONDGET = 4;
reg [3:0] opmode;
wire op_needsmalloc;
reg op_retry;
reg op_addrchoice;
reg [32-1:0] fastforward_addr [0:2**FASTFORWARD_BITS];
(* ram_style = "block" *) reg [MEMORY_WIDTH-1:0] fastforward_mem [0:2**FASTFORWARD_BITS];
reg [FASTFORWARD_BITS-1:0] ff_head;
reg [FASTFORWARD_BITS-1:0] ff_tail;
reg [FASTFORWARD_BITS-1:0] ff_cnt;
reg [FASTFORWARD_BITS-1:0] pos_ff;
(* ram_style = "block" *) reg [1+KEY_WIDTH+HEADER_WIDTH-1:0] kicked_keys [0:2**FASTFORWARD_BITS]; // the plus bit is to say whether this is a 'real kicked key' (=1) or just a regular retry for second address (=0)
reg [FASTFORWARD_BITS-1:0] kk_head;
reg [FASTFORWARD_BITS-1:0] kk_tail;
reg [FASTFORWARD_BITS-1:0] kk_cnt;
reg [FASTFORWARD_BITS-1:0] pos_kk;
reg [1:0] found_ff;
reg [1:0] found_addr_ff;
reg [1:0] empty_ff;
reg [FASTFORWARD_BITS-1:0] found_ff_pos;
reg [1:0] found_ff_idx;
reg [1:0] empty_ff_idx;
reg found_kk;
reg [FASTFORWARD_BITS-1:0] found_kk_pos;
reg [1:0] found_mem;
reg [1:0] found_mem_idx;
reg [1:0] empty_mem;
reg [1:0] empty_mem_idx;
reg [HEADER_WIDTH-1:0] oldpointer;
reg [MEMADDR_WIDTH-1:0] wipe_location;
reg wipe_start;
(* keep = "true", max_fanout = 4 *) reg[KEY_WIDTH+META_WIDTH+DOUBLEHASH_WIDTH-1:0] inputReg;
reg [MEM_WRITE_WAIT-1:0] delayer;
wire [3:0] curr_opcode;
assign curr_opcode = (state==ST_IDLE) ? input_data[KEY_WIDTH+META_WIDTH-8 +: 4] : inputReg[KEY_WIDTH+META_WIDTH-8 +: 4];
assign op_needsmalloc = (opmode==OP_SETCUR) ? 1 : 0;
wire [3:0] curr_flags;
assign curr_flags = (state==ST_IDLE) ? input_data[KEY_WIDTH+META_WIDTH-4 +: 4] : inputReg[KEY_WIDTH+META_WIDTH-4 +: 4];
wire [MEMADDR_WIDTH-1:0] curr_hash1;
wire [MEMADDR_WIDTH-1:0] curr_hash2;
assign curr_hash1 = (state==ST_IDLE) ? input_data[KEY_WIDTH+META_WIDTH +: MEMADDR_WIDTH] : inputReg[KEY_WIDTH+META_WIDTH +: MEMADDR_WIDTH];
assign curr_hash2 = (state==ST_IDLE) ? input_data[KEY_WIDTH+META_WIDTH+DOUBLEHASH_WIDTH/2 +: MEMADDR_WIDTH] : inputReg[KEY_WIDTH+META_WIDTH+DOUBLEHASH_WIDTH/2 +: MEMADDR_WIDTH];
reg [MEMADDR_WIDTH-1:0] writebackAddr;
reg [2:0] writebackIdx;
reg [1+KEY_WIDTH+HEADER_WIDTH-1:0] writebackEntry;
reg [MEMORY_WIDTH-1:0] writebackLine;
reg writebackKeyMatch;
reg writebackNeedsKick;
reg writebackToKK;
integer c;
integer x;
reg[MEMORY_WIDTH-1:0] fastforward_mem_pos_reg;
reg[MEMORY_WIDTH-1:0] fastforward_mem_found_reg [0:1];
reg [1+KEY_WIDTH+HEADER_WIDTH-1:0] kicked_keys_pos_reg;
reg [1+KEY_WIDTH+HEADER_WIDTH-1:0] kicked_keys_found_reg;
reg[MEMORY_WIDTH-1:0] fastforward_write_data;
reg[7:0] fastforward_write_addr;
reg fastforward_write_valid;
reg[1+KEY_WIDTH+HEADER_WIDTH-1:0] kicked_keys_write_data;
reg[7:0] kicked_keys_write_addr;
reg kicked_keys_write_valid;
reg[511:0] write_data_prep;
reg[MEMORY_WIDTH-1:0] rdMemWord [1:2];
reg mallocRegValid;
reg[31:0] mallocRegData;
reg mallocRegFail;
reg[15:0] inputValueSize;
reg random_ff;
reg[1:0] random_loc3;
always @(posedge clk) begin
if (rst) begin
// reset
state <= ST_IDLE;
ff_head <= 0;
ff_tail <= 0;
ff_cnt <= 0;
kk_head <= 0;
kk_tail <= 0;
kk_cnt <= 0;
delayer <= 0;
rd_ready <= 0;
wr_valid <= 0;
wrcmd_valid <= 0;
input_ready <= 0;
free_valid <= 0;
free_wipe <= 0;
malloc_ready <= 0;
output_valid <= 0;
feedback_valid <= 0;
kicked_keys_write_valid <= 0;
fastforward_write_valid <= 0;
malloc_ready <= 0;
empty_ff_idx <= 0;
empty_mem_idx <= 0;
malloc_req_valid <= 0;
mallocRegValid <= 0;
random_ff <= 0;
random_loc3 <= 0;
end
else begin
random_ff <= ~random_ff;
random_loc3 <= (random_loc3 == 2) ? 0 : (random_loc3+1);
fastforward_mem_pos_reg <= fastforward_mem[pos_ff];
kicked_keys_pos_reg <= kicked_keys[pos_kk];
kicked_keys_write_valid <= 0;
fastforward_write_valid <= 0;
if (kicked_keys_write_valid==1) begin
kicked_keys[kicked_keys_write_addr] <= kicked_keys_write_data;
end
if (fastforward_write_valid==1) begin
fastforward_mem[fastforward_write_addr] <= fastforward_write_data;
end
delayer <= {delayer[MEM_WRITE_WAIT-2:0],1'b0};
if (delayer[MEM_WRITE_WAIT-1]==1 && ff_cnt>0) begin
ff_cnt <= ff_cnt-1;
ff_tail <= ff_tail+1;
end
if (output_valid==1 && output_ready==1) begin
output_valid <= 0;
end
if (feedback_valid==1 && feedback_ready==1) begin
feedback_valid <= 0;
end
if (free_valid==1 && free_ready==1) begin
free_valid <= 0;
free_wipe <= 0;
end
if (wrcmd_valid==1 && wrcmd_ready==1) begin
wrcmd_valid <= 0;
end
if (wr_valid==1 && wr_ready==1) begin
wr_valid <= 0;
end
if (malloc_req_valid==1 && malloc_req_ready==1) begin
malloc_req_valid <= 0;
end
input_ready <= 0;
malloc_ready <= 0;
rd_ready <= 0;
case (state)
ST_WIPE: begin
if (wrcmd_ready==1 && wrcmd_valid==1) begin
wrcmd_valid <= 0;
end
if (wr_ready==1 && wr_valid==1) begin
wr_valid <= 0;
end
if (wrcmd_ready==1 && wr_ready==1 && wrcmd_valid==0 && wr_valid==0) begin
wipe_start <= 0;
wrcmd_data[31:MEMADDR_WIDTH] <= 0;
wrcmd_data[MEMADDR_WIDTH-1:0] <= wipe_location;
wrcmd_valid <= 1;
wr_data <= 0;
wr_valid <= 1;
wipe_location <= wipe_location+1;
end
if (wipe_start==0 && wipe_location== (IS_SIM==0 ? 0 : 16) ) begin // 16 for sim!
if (ff_cnt>0 || kk_cnt>0) begin
state <= ST_CHECK_FF;
pos_ff <= ff_tail;
pos_kk <= kk_tail;
end else begin
state <= ST_CHECK_MEM;
end
end
end
ST_IDLE: begin
if (input_valid==1) begin
op_retry <= curr_flags[2];
op_addrchoice <= curr_flags[3];
opmode <= curr_flags[2]==0 ? curr_opcode : OP_SETCUR;
inputReg <= input_data;
input_ready <= 1;
found_ff <= 0;
found_addr_ff <= 0;
found_kk <= 0;
found_mem <= 0;
empty_mem <= 0;
empty_ff <= 0;
inputValueSize <= input_data[KEY_WIDTH+64 +: 16];
if (curr_opcode == OP_IGNORE) begin
state <= ST_SENDOUT;
end else if (curr_opcode == OP_FLUSH) begin
state <= ST_WIPE;
free_valid <= 1;
free_wipe <= 1;
wipe_start <= 1;
wipe_location <= 0;
end else begin
if (ff_cnt>0 || kk_cnt>0) begin
state <= ST_CHECK_FF;
pos_ff <= ff_tail;
pos_kk <= kk_tail;
end else begin
state <= ST_CHECK_MEM;
end
end
end
end
ST_CHECK_FF: begin
if (pos_ff==(ff_head+1)%2**FASTFORWARD_BITS && pos_kk==(kk_head+1)%2**FASTFORWARD_BITS) begin
if (found_addr_ff!=0) begin
state <= ST_SKIP_MEM;
end else begin
state <= ST_CHECK_MEM;
end
end else begin
if (pos_ff!=(ff_head+1)%2**FASTFORWARD_BITS) begin
pos_ff <= pos_ff+1;
if (pos_ff!=ff_tail) begin
if (fastforward_addr[pos_ff-1]==curr_hash1) begin
found_addr_ff[0] <= 1;
found_ff_pos <= pos_ff-1;
fastforward_mem_found_reg[0] <= fastforward_mem_pos_reg;
found_ff_idx <= 0;
empty_ff <= 0;
// compare to this data
for (c=0; c<MEMORY_WIDTH/(KEY_WIDTH+HEADER_WIDTH); c=c+1) begin
if (fastforward_mem_pos_reg[(c)*(KEY_WIDTH+HEADER_WIDTH) +: KEY_WIDTH]==inputReg[KEY_WIDTH-1:0]) begin
found_ff <= 1;
found_ff_pos <= pos_ff-1;
found_ff_idx <= c;
end else begin
found_ff <= 0;
end
if (fastforward_mem_pos_reg[(c)*(KEY_WIDTH+HEADER_WIDTH) +: KEY_WIDTH]==0) begin
empty_ff_idx <= c;
empty_ff <= 1;
end
end
end
if (fastforward_addr[pos_ff-1]==curr_hash2) begin
found_addr_ff[1] <= 1;
found_ff_pos <= pos_ff-1;
fastforward_mem_found_reg[1] <= fastforward_mem_pos_reg;
found_ff_idx <= 0;
empty_ff <= 0;
// compare to this data
for (c=0; c<MEMORY_WIDTH/(KEY_WIDTH+HEADER_WIDTH); c=c+1) begin
if (fastforward_mem_pos_reg[(c)*(KEY_WIDTH+HEADER_WIDTH) +: KEY_WIDTH]==inputReg[KEY_WIDTH-1:0]) begin
found_ff <= 2;
found_ff_pos <= pos_ff-1;
found_ff_idx <= c;
end else begin
found_ff <= 0;
end
if (fastforward_mem_pos_reg[(c)*(KEY_WIDTH+HEADER_WIDTH) +: KEY_WIDTH]==0) begin
empty_ff_idx <= c;
empty_ff <= 2;
end
end
end
end
end
if (pos_kk!=(kk_head+1)%2**FASTFORWARD_BITS) begin
pos_kk <= pos_kk+1;
if (pos_kk!=kk_tail) begin
if (kicked_keys_pos_reg[KEY_WIDTH-1:0]==inputReg[KEY_WIDTH-1:0] && found_kk==0) begin
// this is the same, do something
found_kk <= 1;
found_kk_pos <= pos_kk-1;
kicked_keys_found_reg <= kicked_keys_pos_reg;
oldpointer <= 0;
if (op_retry==1 && (opmode==OP_SETCUR) && pos_kk-1==kk_tail) begin
oldpointer <= kicked_keys_pos_reg[KEY_WIDTH+HEADER_WIDTH-1:KEY_WIDTH];
kk_cnt <= kk_cnt-1;
kk_tail <= kk_tail +1;
found_kk <= 0;
end
end
end
end
end
end
ST_SKIP_MEM: begin
if (rd_valid==1) begin
if (found_addr_ff[1]==1) begin
state <= ST_SKIP_MEM_TWO;
end else begin
state <= ST_CHECK_MEM_TWO;
end
rd_ready <= 1;
end
end
ST_SKIP_MEM_TWO: begin
if (rd_ready==0 && rd_valid==1) begin
state <= ST_CUR_ENTRY;
rd_ready <= 1;
end
end
ST_CHECK_MEM: begin
if (rd_valid==1) begin
// compare to this data
for (x=0; x<MEMORY_WIDTH/(KEY_WIDTH+HEADER_WIDTH); x=x+1) begin
if (rd_data[(x)*(KEY_WIDTH+HEADER_WIDTH) +: KEY_WIDTH]==inputReg[KEY_WIDTH-1:0]) begin
found_mem <= 1;
found_mem_idx <= x;
end
if (rd_data[(x)*(KEY_WIDTH+HEADER_WIDTH) +: KEY_WIDTH]==0) begin
empty_mem_idx <= x;
empty_mem <= 1;
end
end
rd_ready <= 1;
rdMemWord[1] <= rd_data;
if (found_addr_ff[1]==1) begin
state <= ST_SKIP_MEM_TWO;
end else begin
state <= ST_CHECK_MEM_TWO;
end
end
end
ST_CHECK_MEM_TWO: begin
if (rd_ready==0 && rd_valid==1) begin
// compare to this data
rdMemWord[2] <= rd_data;
for (x=0; x<MEMORY_WIDTH/(KEY_WIDTH+HEADER_WIDTH); x=x+1) begin
if (rd_data[(x)*(KEY_WIDTH+HEADER_WIDTH) +: KEY_WIDTH]==inputReg[KEY_WIDTH-1:0]) begin
found_mem <= 2;
found_mem_idx <= x;
end
if (rd_data[(x)*(KEY_WIDTH+HEADER_WIDTH) +: KEY_WIDTH]==0 && empty_mem==0) begin
empty_mem_idx <= x;
empty_mem <= 2;
end
end
state <= ST_CUR_ENTRY;
rd_ready <= 1;
end
end
ST_CUR_ENTRY: begin
writebackNeedsKick <= 0;
writebackToKK <= 0;
if (found_kk!=0 && op_retry==0) begin
writebackAddr <= found_kk_pos;
writebackIdx <= 0;
writebackEntry <= kicked_keys_found_reg;
writebackKeyMatch <= 1;
writebackLine <= 0;
writebackToKK <= 1;
end else if (found_addr_ff!=0 && found_ff!=0) begin
writebackEntry <= fastforward_mem_found_reg[~found_addr_ff[0]][found_ff_idx*(KEY_WIDTH+HEADER_WIDTH) +: KEY_WIDTH+HEADER_WIDTH];
writebackLine <= fastforward_mem_found_reg[~found_addr_ff[0]];
if (found_ff==1) begin
writebackAddr <= curr_hash1;
writebackIdx <= found_ff_idx;
writebackKeyMatch <= 1;
end else if (found_ff==2) begin
writebackAddr <= curr_hash2;
writebackIdx <= found_ff_idx;
writebackKeyMatch <= 1;
end
end else if (found_mem!=0) begin
writebackAddr <= (found_mem==1) ? curr_hash1 : curr_hash2;
writebackIdx <= found_mem_idx;
writebackEntry <= rdMemWord[found_mem][found_mem_idx*(KEY_WIDTH+HEADER_WIDTH) +: KEY_WIDTH+HEADER_WIDTH];
writebackKeyMatch <= 1;
writebackLine <= rdMemWord[found_mem];
end else if (found_addr_ff[0]==1 && empty_ff==1) begin
writebackAddr <= curr_hash1;
writebackIdx <= empty_ff_idx;
writebackEntry <= 0;
writebackKeyMatch <= 0;
writebackLine <= fastforward_mem_found_reg[0];
end else if (found_addr_ff[1]==1 && empty_ff==2) begin
writebackAddr <= curr_hash2;
writebackIdx <= empty_ff_idx;
writebackEntry <= 0;
writebackKeyMatch <= 0;
writebackLine <= fastforward_mem_found_reg[1];
end else if ((found_addr_ff[0]==0 && empty_mem==1) || (found_addr_ff[1]==0 && empty_mem==2)) begin
writebackAddr <= (empty_mem==1) ? curr_hash1 : curr_hash2;
writebackIdx <= empty_mem_idx;
writebackLine <= rdMemWord[empty_mem];
writebackKeyMatch <= 0;
writebackEntry <= 0;
end else begin
if (found_addr_ff!=0) begin
writebackAddr <= found_addr_ff[0]==1 ? curr_hash1 : curr_hash2;
if (random_loc3<MEMORY_WIDTH/(KEY_WIDTH+HEADER_WIDTH)) begin
writebackIdx <= random_loc3;
writebackEntry <= fastforward_mem_found_reg[~found_addr_ff[0]][random_loc3*(KEY_WIDTH+HEADER_WIDTH) +: KEY_WIDTH+HEADER_WIDTH];
end
writebackLine <= fastforward_mem_found_reg[~found_addr_ff[0]];
writebackKeyMatch <= 0;
writebackNeedsKick <= 1;
end else begin
writebackAddr <= random_ff==0 ? curr_hash1 : curr_hash2;
if (random_loc3<MEMORY_WIDTH/(KEY_WIDTH+HEADER_WIDTH)) begin
writebackIdx <= random_loc3;
writebackEntry <= rdMemWord[random_ff][random_loc3*(KEY_WIDTH+HEADER_WIDTH) +: KEY_WIDTH+HEADER_WIDTH];
end
writebackKeyMatch <= 0;
writebackLine <= rdMemWord[random_ff];
writebackNeedsKick <= 1;
end
end
state <= ST_DECIDE;
end
ST_DECIDE : begin
case (opmode)
OP_GET, OP_CONDGET ,OP_SCAN : begin
output_valid <= 1;
output_data[0 +: KEY_WIDTH+META_WIDTH] <= inputReg[0 +: KEY_WIDTH+META_WIDTH];
output_data[KEY_WIDTH+META_WIDTH +: HEADER_WIDTH] <= writebackEntry[KEY_WIDTH +: HEADER_WIDTH];
state <= ST_IDLE;
end
OP_SETCUR : begin
if (feedback_ready==1 && free_ready==1 && kk_cnt<2**FASTFORWARD_BITS-1) begin
state <= ST_WRITEDATA;
if (writebackNeedsKick==1) begin
// kick out a key
feedback_valid <= 1;
feedback_data <= {writebackEntry[0 +: KEY_WIDTH]};
feedback_data[KEY_WIDTH+META_WIDTH-4 +: 4] <= 4'b0100;
kicked_keys_write_data <= writebackEntry;
kicked_keys_write_addr <= kk_head;
kicked_keys_write_valid <= 1;
kk_head <= kk_head+1;
kk_cnt <= kk_cnt+1;
end
if (writebackKeyMatch==1) begin
// this is the same key, look at pointers
if (writebackEntry[KEY_WIDTH +: HEADER_WIDTH]==0) begin
//nothing prepared yet, put pointer there
if (mallocRegValid==1) begin
writebackEntry[KEY_WIDTH +: HEADER_WIDTH] <= {inputValueSize[PLEN_WIDTH-1:0],mallocRegData[PADDR_WIDTH-1:0]};
mallocRegValid <= 0;
end else begin
state <= ST_WAITFORMALLOC;
malloc_req_valid <= 1;
malloc_req_size <= inputValueSize*8;
writebackNeedsKick <= 0;
end
end else if (writebackEntry[KEY_WIDTH +: HEADER_WIDTH]!=0) begin
//pointer location is taken...
if ( ((writebackEntry[KEY_WIDTH + PADDR_WIDTH +: 10]+7)/8) == ((inputValueSize+7)/8) ) begin
// everything good
end else begin
free_valid <= 1;
free_wipe <= 0;
free_pointer <= writebackEntry[KEY_WIDTH +: PADDR_WIDTH];
free_size <= writebackEntry[KEY_WIDTH+PADDR_WIDTH +: PLEN_WIDTH];
writebackEntry[KEY_WIDTH +: HEADER_WIDTH] <= 0;
state <= ST_WAITFORMALLOC;
malloc_req_valid <= 1;
malloc_req_size <= inputValueSize*8;
writebackNeedsKick <= 0;
end
end
end else begin
// this is a brand new insert
if (mallocRegValid==1) begin
writebackEntry[KEY_WIDTH +: HEADER_WIDTH] <= {inputValueSize[PLEN_WIDTH-1:0],mallocRegData[PADDR_WIDTH-1:0]};
writebackEntry[0 +: KEY_WIDTH] <= inputReg[0 +: KEY_WIDTH];
//writebackEntry[KEY_WIDTH+VALPOINTER_WIDTH +: VALPOINTER_WIDTH] <= 0;
mallocRegValid <= 0;
end else if (op_retry==1 && oldpointer!=0) begin
// this is a retry and we should have the old pointer at hand...
writebackEntry[KEY_WIDTH +: HEADER_WIDTH] <= oldpointer;
writebackEntry[0 +: KEY_WIDTH] <= inputReg[0 +: KEY_WIDTH];
end else begin
state <= ST_WAITFORMALLOC;
malloc_req_valid <= 1;
malloc_req_size <= inputValueSize*8;
writebackNeedsKick <= 0;
end
end
end
end
OP_DELCUR : begin
if (free_ready==1) begin
if (writebackKeyMatch==1) begin
// this is the same key, look at pointers
writebackEntry[KEY_WIDTH +: HEADER_WIDTH] <= 0;
free_valid <= 1;
free_wipe <= 0;
free_pointer <= writebackEntry[KEY_WIDTH +: PADDR_WIDTH];
free_size <= writebackEntry[KEY_WIDTH+PADDR_WIDTH +: PLEN_WIDTH];
state <= ST_WRITEDATA;
end else begin
output_data <= { {HEADER_WIDTH{1'b0}}, inputReg[0 +: KEY_WIDTH+META_WIDTH]};
output_valid <= 1;
state <= ST_IDLE;
end
end
end
OP_FLUSH : begin
if (output_ready==1) begin
output_data <= { {HEADER_WIDTH{1'b0}}, inputReg[0 +: KEY_WIDTH+META_WIDTH]};
output_valid <= 1;
state <= ST_IDLE;
end
end
endcase
end
ST_SENDOUT : begin
if (output_ready==1) begin
output_data <= {64'h0, inputReg[0 +: KEY_WIDTH+META_WIDTH]};
output_valid <= ~op_retry;
state <= ST_IDLE;
end
end
ST_WRITEDATA : begin
if (writebackToKK==0) begin
if (wr_ready==1 && wrcmd_ready==1 && ff_cnt<2**FASTFORWARD_BITS-1 && output_ready==1) begin
wr_data <= writebackLine;
wr_data[writebackIdx*(KEY_WIDTH+HEADER_WIDTH) +: (KEY_WIDTH+HEADER_WIDTH)] <= writebackEntry;
wr_valid <= 1;
wrcmd_data[MEMADDR_WIDTH-1:0] <= {writebackAddr[MEMADDR_WIDTH-1:0]};
wrcmd_data[31:MEMADDR_WIDTH] <= 0;
wrcmd_valid <= 1;
if (inputReg[KEY_WIDTH+META_WIDTH-4 +: 4]==0) begin
// not a kicked reinsert
output_data <= {writebackEntry[KEY_WIDTH +: HEADER_WIDTH], inputReg[0 +: KEY_WIDTH+META_WIDTH]};
output_valid <= 1;
end
fastforward_write_data <= writebackLine;
fastforward_write_data[writebackIdx*(KEY_WIDTH+HEADER_WIDTH) +: (KEY_WIDTH+HEADER_WIDTH)] <= writebackEntry;
fastforward_write_addr <= ff_head;
fastforward_write_valid <= 1;
fastforward_addr[ff_head] <= writebackAddr;
ff_head <= ff_head+1;
delayer[0] <= 1;
if (delayer[MEM_WRITE_WAIT-1]==1 && ff_cnt>0) begin
ff_cnt <= ff_cnt;
end else begin
ff_cnt <= ff_cnt+1;
end
state <= ST_IDLE;
end
end else begin
kicked_keys_write_data <= writebackEntry;
kicked_keys_write_addr <= writebackAddr;
kicked_keys_write_valid <= 1;
end
end
ST_WAITFORMALLOC : begin
if (malloc_valid==1) begin
malloc_ready <= 1;
mallocRegValid <= malloc_valid;
mallocRegData <= malloc_pointer;
state <= ST_DECIDE;
end
end
endcase
end
end
endmodule
`default_nettype wire |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_ffu.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: sparc_ffu
// Description: This is the top level for the floating point frontend unit (ffu).
// It instantiates the control (ffu_ctl), datapath (ffu_dp), and register file
// (frf).
*/
`include "iop.h"
`define FPRET_CMP 69
`define FPRET_CC_HI 68
`define FPRET_CC_LO 67
`define FPRET_EXC_HI 76
`define FPRET_EXC_LO 72
module sparc_ffu (/*AUTOARG*/
// Outputs
so, ffu_tlu_trap_ue, ffu_tlu_trap_other, ffu_tlu_trap_ieee754,
ffu_tlu_ill_inst_m, ffu_tlu_fpu_tid, ffu_tlu_fpu_cmplt,
ffu_lsu_kill_fst_w, ffu_lsu_fpop_rq_vld, ffu_lsu_blk_st_va_e,
ffu_lsu_blk_st_e, ffu_ifu_tid_w2, ffu_ifu_stallreq,
ffu_ifu_inj_ack, ffu_ifu_fst_ce_w, ffu_ifu_fpop_done_w2,
ffu_ifu_err_synd_w2, ffu_ifu_err_reg_w2, ffu_ifu_ecc_ue_w2,
ffu_ifu_ecc_ce_w2, ffu_ifu_cc_w2, ffu_ifu_cc_vld_w2, ffu_lsu_data,
short_so0, ffu_exu_rsr_data_m,
// Inputs
si, sehold, se, rclk, lsu_ffu_stb_full3, lsu_ffu_stb_full2,
lsu_ffu_stb_full1, lsu_ffu_stb_full0, lsu_ffu_ld_vld,
lsu_ffu_ld_data, lsu_ffu_flush_pipe_w, lsu_ffu_blk_asi_e,
lsu_ffu_bld_cnt_w, lsu_ffu_ack, ifu_tlu_sraddr_d,
ifu_tlu_inst_vld_w, ifu_tlu_flush_w, ifu_tlu_flsh_inst_e,
ifu_lsu_ld_inst_e, ifu_ffu_visop_d, ifu_ffu_tid_d,
ifu_ffu_stfsr_d, ifu_ffu_quad_op_e, ifu_ffu_mvcnd_m,
ifu_ffu_ldxfsr_d, ifu_ffu_ldst_single_d, ifu_ffu_ldfsr_d,
ifu_ffu_inj_frferr, ifu_ffu_fst_d, ifu_ffu_frs2_d, ifu_ffu_frs1_d,
ifu_ffu_frd_d, ifu_ffu_fpopcode_d, ifu_ffu_fpop2_d,
ifu_ffu_fpop1_d, ifu_ffu_fld_d, ifu_ffu_fcc_num_d,
ifu_exu_nceen_e, ifu_exu_ecc_mask, ifu_exu_disable_ce_e, grst_l,
exu_ffu_wsr_inst_e, exu_ffu_ist_e, exu_ffu_gsr_scale_m,
exu_ffu_gsr_rnd_m, exu_ffu_gsr_mask_m, exu_ffu_gsr_align_m,
cpx_vld, cpx_req, cpx_fpu_data, cpx_fpexc, cpx_fcmp, cpx_fccval,
arst_l, mux_drive_disable, mem_write_disable, short_si0,
//sotheas,8/17/04: eco 6529
lsu_ffu_st_dtlb_perr_g
//////////////////////////////////
) ;
output [80:0] ffu_lsu_data; // From dp of sparc_ffu_dp.v, ...
output short_so0;
input mux_drive_disable;
input mem_write_disable;
input short_si0;
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input arst_l; // To ctl of sparc_ffu_ctl.v
input [1:0] cpx_fccval; // To ctl of sparc_ffu_ctl.v
input cpx_fcmp; // To ctl of sparc_ffu_ctl.v
input [4:0] cpx_fpexc; // To ctl of sparc_ffu_ctl.v
input [63:0] cpx_fpu_data; // To dp of sparc_ffu_dp.v
input [3:0] cpx_req; // To ctl of sparc_ffu_ctl.v
input cpx_vld; // To ctl of sparc_ffu_ctl.v
input [2:0] exu_ffu_gsr_align_m; // To ctl of sparc_ffu_ctl.v
input [31:0] exu_ffu_gsr_mask_m; // To ctl of sparc_ffu_ctl.v
input [2:0] exu_ffu_gsr_rnd_m; // To ctl of sparc_ffu_ctl.v
input [4:0] exu_ffu_gsr_scale_m; // To ctl of sparc_ffu_ctl.v
input exu_ffu_ist_e; // To ctl of sparc_ffu_ctl.v
input exu_ffu_wsr_inst_e; // To ctl of sparc_ffu_ctl.v
input grst_l; // To ctl of sparc_ffu_ctl.v
input ifu_exu_disable_ce_e; // To ctl of sparc_ffu_ctl.v
input [6:0] ifu_exu_ecc_mask; // To ctl of sparc_ffu_ctl.v
input ifu_exu_nceen_e; // To ctl of sparc_ffu_ctl.v
input [1:0] ifu_ffu_fcc_num_d; // To ctl of sparc_ffu_ctl.v
input ifu_ffu_fld_d; // To ctl of sparc_ffu_ctl.v
input ifu_ffu_fpop1_d; // To ctl of sparc_ffu_ctl.v
input ifu_ffu_fpop2_d; // To ctl of sparc_ffu_ctl.v
input [8:0] ifu_ffu_fpopcode_d; // To ctl of sparc_ffu_ctl.v
input [4:0] ifu_ffu_frd_d; // To ctl of sparc_ffu_ctl.v
input [4:0] ifu_ffu_frs1_d; // To ctl of sparc_ffu_ctl.v
input [4:0] ifu_ffu_frs2_d; // To ctl of sparc_ffu_ctl.v
input ifu_ffu_fst_d; // To ctl of sparc_ffu_ctl.v
input ifu_ffu_inj_frferr; // To ctl of sparc_ffu_ctl.v
input ifu_ffu_ldfsr_d; // To ctl of sparc_ffu_ctl.v
input ifu_ffu_ldst_single_d; // To ctl of sparc_ffu_ctl.v
input ifu_ffu_ldxfsr_d; // To ctl of sparc_ffu_ctl.v
input ifu_ffu_mvcnd_m; // To ctl of sparc_ffu_ctl.v
input ifu_ffu_quad_op_e; // To ctl of sparc_ffu_ctl.v
input ifu_ffu_stfsr_d; // To ctl of sparc_ffu_ctl.v
input [1:0] ifu_ffu_tid_d; // To ctl of sparc_ffu_ctl.v
input ifu_ffu_visop_d; // To ctl of sparc_ffu_ctl.v
input ifu_lsu_ld_inst_e; // To ctl of sparc_ffu_ctl.v
input ifu_tlu_flsh_inst_e; // To ctl of sparc_ffu_ctl.v
input ifu_tlu_flush_w; // To ctl of sparc_ffu_ctl.v
input ifu_tlu_inst_vld_w; // To ctl of sparc_ffu_ctl.v
input [6:0] ifu_tlu_sraddr_d; // To ctl of sparc_ffu_ctl.v
input lsu_ffu_ack; // To ctl of sparc_ffu_ctl.v
input [2:0] lsu_ffu_bld_cnt_w; // To ctl of sparc_ffu_ctl.v
input lsu_ffu_blk_asi_e; // To ctl of sparc_ffu_ctl.v
input lsu_ffu_flush_pipe_w; // To ctl of sparc_ffu_ctl.v
input [63:0] lsu_ffu_ld_data; // To dp of sparc_ffu_dp.v
input lsu_ffu_ld_vld; // To ctl of sparc_ffu_ctl.v
input lsu_ffu_stb_full0; // To ctl of sparc_ffu_ctl.v
input lsu_ffu_stb_full1; // To ctl of sparc_ffu_ctl.v
input lsu_ffu_stb_full2; // To ctl of sparc_ffu_ctl.v
input lsu_ffu_stb_full3; // To ctl of sparc_ffu_ctl.v
input lsu_ffu_st_dtlb_perr_g; // sotheas,8/17/04: fixed eco 6529, signal to sparc_ffu_ctl.v
input rclk; // To frf of bw_r_frf.v, ...
input se; // To frf of bw_r_frf.v, ...
input sehold; // To frf of bw_r_frf.v
input si; // To dp of sparc_ffu_dp.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [3:0] ffu_ifu_cc_vld_w2; // From ctl of sparc_ffu_ctl.v
output [7:0] ffu_ifu_cc_w2; // From ctl of sparc_ffu_ctl.v
output ffu_ifu_ecc_ce_w2; // From ctl of sparc_ffu_ctl.v
output ffu_ifu_ecc_ue_w2; // From ctl of sparc_ffu_ctl.v
output [5:0] ffu_ifu_err_reg_w2; // From ctl of sparc_ffu_ctl.v
output [13:0] ffu_ifu_err_synd_w2; // From ctl of sparc_ffu_ctl.v
output ffu_ifu_fpop_done_w2; // From ctl of sparc_ffu_ctl.v
output ffu_ifu_fst_ce_w; // From ctl of sparc_ffu_ctl.v
output ffu_ifu_inj_ack; // From ctl of sparc_ffu_ctl.v
output ffu_ifu_stallreq; // From ctl of sparc_ffu_ctl.v
output [1:0] ffu_ifu_tid_w2; // From ctl of sparc_ffu_ctl.v
output ffu_lsu_blk_st_e; // From ctl of sparc_ffu_ctl.v
output [5:3] ffu_lsu_blk_st_va_e; // From ctl of sparc_ffu_ctl.v
output ffu_lsu_fpop_rq_vld; // From ctl of sparc_ffu_ctl.v
output ffu_lsu_kill_fst_w; // From ctl of sparc_ffu_ctl.v
output ffu_tlu_fpu_cmplt; // From ctl of sparc_ffu_ctl.v
output [1:0] ffu_tlu_fpu_tid; // From ctl of sparc_ffu_ctl.v
output ffu_tlu_ill_inst_m; // From ctl of sparc_ffu_ctl.v
output ffu_tlu_trap_ieee754; // From ctl of sparc_ffu_ctl.v
output ffu_tlu_trap_other; // From ctl of sparc_ffu_ctl.v
output ffu_tlu_trap_ue; // From ctl of sparc_ffu_ctl.v
output so; // From dp of sparc_ffu_dp.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire ctl_dp_ecc_sel_frf; // From ctl of sparc_ffu_ctl.v
wire [9:0] ctl_dp_exc_w2; // From ctl of sparc_ffu_ctl.v
wire [7:0] ctl_dp_fcc_w2; // From ctl of sparc_ffu_ctl.v
wire ctl_dp_flip_fpu; // From ctl of sparc_ffu_ctl.v
wire ctl_dp_flip_lsu; // From ctl of sparc_ffu_ctl.v
wire [3:0] ctl_dp_fp_thr; // From ctl of sparc_ffu_ctl.v
wire [3:0] ctl_dp_fsr_sel_fpu; // From ctl of sparc_ffu_ctl.v
wire [3:0] ctl_dp_fsr_sel_ld; // From ctl of sparc_ffu_ctl.v
wire [3:0] ctl_dp_fsr_sel_old; // From ctl of sparc_ffu_ctl.v
wire [2:0] ctl_dp_ftt_w2; // From ctl of sparc_ffu_ctl.v
wire [3:0] ctl_dp_gsr_wsr_w2; // From ctl of sparc_ffu_ctl.v
wire ctl_dp_new_rs1; // From ctl of sparc_ffu_ctl.v
wire ctl_dp_noflip_fpu; // From ctl of sparc_ffu_ctl.v
wire ctl_dp_noflip_lsu; // From ctl of sparc_ffu_ctl.v
wire ctl_dp_noshift64_frf; // From ctl of sparc_ffu_ctl.v
wire ctl_dp_output_sel_frf; // From ctl of sparc_ffu_ctl.v
wire ctl_dp_output_sel_fsr; // From ctl of sparc_ffu_ctl.v
wire ctl_dp_output_sel_rs1; // From ctl of sparc_ffu_ctl.v
wire ctl_dp_output_sel_rs2; // From ctl of sparc_ffu_ctl.v
wire ctl_dp_rd_ecc; // From ctl of sparc_ffu_ctl.v
wire ctl_dp_rs2_frf_read; // From ctl of sparc_ffu_ctl.v
wire ctl_dp_rs2_keep_data; // From ctl of sparc_ffu_ctl.v
wire ctl_dp_rs2_sel_fpu_lsu; // From ctl of sparc_ffu_ctl.v
wire ctl_dp_rs2_sel_vis; // From ctl of sparc_ffu_ctl.v
wire ctl_dp_rst_l; // From ctl of sparc_ffu_ctl.v
wire ctl_dp_shift_frf_left; // From ctl of sparc_ffu_ctl.v
wire ctl_dp_shift_frf_right; // From ctl of sparc_ffu_ctl.v
wire [1:0] ctl_dp_sign; // From ctl of sparc_ffu_ctl.v
wire [3:0] ctl_dp_thr_e; // From ctl of sparc_ffu_ctl.v
wire [36:0] ctl_dp_wsr_data_w2; // From ctl of sparc_ffu_ctl.v
wire ctl_dp_zero_low32_frf; // From ctl of sparc_ffu_ctl.v
wire [6:0] ctl_frf_addr; // From ctl of sparc_ffu_ctl.v
wire ctl_frf_ren; // From ctl of sparc_ffu_ctl.v
wire [1:0] ctl_frf_wen; // From ctl of sparc_ffu_ctl.v
wire ctl_vis_add32; // From ctl of sparc_ffu_ctl.v
wire ctl_vis_align0; // From ctl of sparc_ffu_ctl.v
wire ctl_vis_align2; // From ctl of sparc_ffu_ctl.v
wire ctl_vis_align4; // From ctl of sparc_ffu_ctl.v
wire ctl_vis_align6; // From ctl of sparc_ffu_ctl.v
wire ctl_vis_align_odd; // From ctl of sparc_ffu_ctl.v
wire ctl_vis_cin; // From ctl of sparc_ffu_ctl.v
wire ctl_vis_log_constant; // From ctl of sparc_ffu_ctl.v
wire ctl_vis_log_invert_rs1; // From ctl of sparc_ffu_ctl.v
wire ctl_vis_log_invert_rs2; // From ctl of sparc_ffu_ctl.v
wire ctl_vis_log_pass_const; // From ctl of sparc_ffu_ctl.v
wire ctl_vis_log_pass_rs1; // From ctl of sparc_ffu_ctl.v
wire ctl_vis_log_pass_rs2; // From ctl of sparc_ffu_ctl.v
wire ctl_vis_log_sel_nand; // From ctl of sparc_ffu_ctl.v
wire ctl_vis_log_sel_nor; // From ctl of sparc_ffu_ctl.v
wire ctl_vis_log_sel_pass; // From ctl of sparc_ffu_ctl.v
wire ctl_vis_log_sel_xor; // From ctl of sparc_ffu_ctl.v
wire ctl_vis_sel_add; // From ctl of sparc_ffu_ctl.v
wire ctl_vis_sel_align; // From ctl of sparc_ffu_ctl.v
wire ctl_vis_sel_log; // From ctl of sparc_ffu_ctl.v
wire ctl_vis_subtract; // From ctl of sparc_ffu_ctl.v
wire [4:0] dp_ctl_fsr_aexc; // From dp of sparc_ffu_dp.v
wire [4:0] dp_ctl_fsr_cexc; // From dp of sparc_ffu_dp.v
wire [7:0] dp_ctl_fsr_fcc; // From dp of sparc_ffu_dp.v
wire [1:0] dp_ctl_fsr_rnd; // From dp of sparc_ffu_dp.v
wire [4:0] dp_ctl_fsr_tem; // From dp of sparc_ffu_dp.v
wire [31:0] dp_ctl_gsr_mask_e; // From dp of sparc_ffu_dp.v
wire [4:0] dp_ctl_gsr_scale_e; // From dp of sparc_ffu_dp.v
wire [7:0] dp_ctl_ld_fcc; // From dp of sparc_ffu_dp.v
wire [1:0] dp_ctl_rs2_sign; // From dp of sparc_ffu_dp.v
wire [6:0] dp_ctl_synd_out_high; // From dp of sparc_ffu_dp.v
wire [6:0] dp_ctl_synd_out_low; // From dp of sparc_ffu_dp.v
wire [63:0] dp_vis_rs1_data; // From dp of sparc_ffu_dp.v
wire [63:0] dp_vis_rs2_data; // From dp of sparc_ffu_dp.v
wire [77:0] frf_dp_data; // From frf of bw_r_frf.v
wire [63:0] vis_dp_rd_data; // From vis of sparc_ffu_vis.v
// End of automatics
wire [77:0] dp_frf_data;
output [63:0] ffu_exu_rsr_data_m;
wire [31:0] ffu_exu_rsr_data_hi_m;
wire [2:0] ffu_exu_rsr_data_mid_m;
wire [7:0] ffu_exu_rsr_data_lo_m;
wire short_scan_1;
assign ffu_exu_rsr_data_m[63:0] = {ffu_exu_rsr_data_hi_m[31:0], 4'b0,
ffu_exu_rsr_data_mid_m[2:0], 17'b0,
ffu_exu_rsr_data_lo_m[7:0]};
bw_r_frf frf(
.si(short_si0),
.so(short_scan_1),
.dp_frf_data (dp_frf_data[77:0]),
.rst_tri_en (mem_write_disable),
/*AUTOINST*/
// Outputs
.frf_dp_data (frf_dp_data[77:0]),
// Inputs
.rclk (rclk),
.se (se),
.sehold (sehold),
.ctl_frf_wen (ctl_frf_wen[1:0]),
.ctl_frf_ren (ctl_frf_ren),
.ctl_frf_addr (ctl_frf_addr[6:0]));
sparc_ffu_dp dp(
.dp_frf_data ({dp_frf_data[70:39],dp_frf_data[31:0]}),
/*AUTOINST*/
// Outputs
.so (so),
.ffu_lsu_data (ffu_lsu_data[63:0]),
.dp_vis_rs1_data (dp_vis_rs1_data[63:0]),
.dp_vis_rs2_data (dp_vis_rs2_data[63:0]),
.dp_ctl_rs2_sign (dp_ctl_rs2_sign[1:0]),
.dp_ctl_fsr_fcc (dp_ctl_fsr_fcc[7:0]),
.dp_ctl_fsr_rnd (dp_ctl_fsr_rnd[1:0]),
.dp_ctl_fsr_tem (dp_ctl_fsr_tem[4:0]),
.dp_ctl_fsr_aexc (dp_ctl_fsr_aexc[4:0]),
.dp_ctl_fsr_cexc (dp_ctl_fsr_cexc[4:0]),
.dp_ctl_ld_fcc (dp_ctl_ld_fcc[7:0]),
.dp_ctl_gsr_mask_e (dp_ctl_gsr_mask_e[31:0]),
.dp_ctl_gsr_scale_e (dp_ctl_gsr_scale_e[4:0]),
.dp_ctl_synd_out_low (dp_ctl_synd_out_low[6:0]),
.dp_ctl_synd_out_high(dp_ctl_synd_out_high[6:0]),
// Inputs
.rclk (rclk),
.se (se),
.si (si),
.ctl_dp_rst_l (ctl_dp_rst_l),
.frf_dp_data (frf_dp_data[77:0]),
.cpx_fpu_data (cpx_fpu_data[63:0]),
.lsu_ffu_ld_data (lsu_ffu_ld_data[63:0]),
.vis_dp_rd_data (vis_dp_rd_data[63:0]),
.ctl_dp_wsr_data_w2 (ctl_dp_wsr_data_w2[36:0]),
.ctl_dp_sign (ctl_dp_sign[1:0]),
.ctl_dp_exc_w2 (ctl_dp_exc_w2[9:0]),
.ctl_dp_fcc_w2 (ctl_dp_fcc_w2[7:0]),
.ctl_dp_ftt_w2 (ctl_dp_ftt_w2[2:0]),
.ctl_dp_noshift64_frf(ctl_dp_noshift64_frf),
.ctl_dp_shift_frf_right(ctl_dp_shift_frf_right),
.ctl_dp_shift_frf_left(ctl_dp_shift_frf_left),
.ctl_dp_zero_low32_frf(ctl_dp_zero_low32_frf),
.ctl_dp_output_sel_rs1(ctl_dp_output_sel_rs1),
.ctl_dp_output_sel_rs2(ctl_dp_output_sel_rs2),
.ctl_dp_output_sel_frf(ctl_dp_output_sel_frf),
.ctl_dp_output_sel_fsr(ctl_dp_output_sel_fsr),
.ctl_dp_noflip_lsu (ctl_dp_noflip_lsu),
.ctl_dp_flip_lsu (ctl_dp_flip_lsu),
.ctl_dp_noflip_fpu (ctl_dp_noflip_fpu),
.ctl_dp_flip_fpu (ctl_dp_flip_fpu),
.ctl_dp_rs2_frf_read (ctl_dp_rs2_frf_read),
.ctl_dp_rs2_sel_vis (ctl_dp_rs2_sel_vis),
.ctl_dp_rs2_sel_fpu_lsu(ctl_dp_rs2_sel_fpu_lsu),
.ctl_dp_rs2_keep_data(ctl_dp_rs2_keep_data),
.ctl_dp_rd_ecc (ctl_dp_rd_ecc),
.ctl_dp_fp_thr (ctl_dp_fp_thr[3:0]),
.ctl_dp_fsr_sel_old (ctl_dp_fsr_sel_old[3:0]),
.ctl_dp_fsr_sel_ld (ctl_dp_fsr_sel_ld[3:0]),
.ctl_dp_fsr_sel_fpu (ctl_dp_fsr_sel_fpu[3:0]),
.ctl_dp_gsr_wsr_w2 (ctl_dp_gsr_wsr_w2[3:0]),
.ctl_dp_thr_e (ctl_dp_thr_e[3:0]),
.ctl_dp_new_rs1 (ctl_dp_new_rs1),
.ctl_dp_ecc_sel_frf (ctl_dp_ecc_sel_frf));
sparc_ffu_ctl ctl(
.si(short_scan_1),
.so (short_so0),
.ffu_exu_rsr_data_hi_m(ffu_exu_rsr_data_hi_m[31:0]),
.ffu_exu_rsr_data_lo_m(ffu_exu_rsr_data_lo_m[7:0]),
.ffu_exu_rsr_data_mid_m(ffu_exu_rsr_data_mid_m[2:0]),
.ctl_frf_write_synd({dp_frf_data[77:71],dp_frf_data[38:32]}),
.rst_tri_en (mux_drive_disable),
/*AUTOINST*/
// Outputs
.ctl_dp_gsr_wsr_w2 (ctl_dp_gsr_wsr_w2[3:0]),
.ctl_dp_thr_e (ctl_dp_thr_e[3:0]),
.ctl_dp_wsr_data_w2(ctl_dp_wsr_data_w2[36:0]),
.ctl_vis_add32 (ctl_vis_add32),
.ctl_vis_align0 (ctl_vis_align0),
.ctl_vis_align2 (ctl_vis_align2),
.ctl_vis_align4 (ctl_vis_align4),
.ctl_vis_align6 (ctl_vis_align6),
.ctl_vis_align_odd (ctl_vis_align_odd),
.ctl_vis_cin (ctl_vis_cin),
.ctl_vis_log_constant(ctl_vis_log_constant),
.ctl_vis_log_invert_rs1(ctl_vis_log_invert_rs1),
.ctl_vis_log_invert_rs2(ctl_vis_log_invert_rs2),
.ctl_vis_log_pass_const(ctl_vis_log_pass_const),
.ctl_vis_log_pass_rs1(ctl_vis_log_pass_rs1),
.ctl_vis_log_pass_rs2(ctl_vis_log_pass_rs2),
.ctl_vis_log_sel_nand(ctl_vis_log_sel_nand),
.ctl_vis_log_sel_nor(ctl_vis_log_sel_nor),
.ctl_vis_log_sel_pass(ctl_vis_log_sel_pass),
.ctl_vis_log_sel_xor(ctl_vis_log_sel_xor),
.ctl_vis_sel_add (ctl_vis_sel_add),
.ctl_vis_sel_align (ctl_vis_sel_align),
.ctl_vis_sel_log (ctl_vis_sel_log),
.ctl_vis_subtract (ctl_vis_subtract),
.ctl_dp_rst_l (ctl_dp_rst_l),
.ffu_ifu_fpop_done_w2(ffu_ifu_fpop_done_w2),
.ffu_ifu_cc_vld_w2 (ffu_ifu_cc_vld_w2[3:0]),
.ffu_ifu_cc_w2 (ffu_ifu_cc_w2[7:0]),
.ffu_ifu_tid_w2 (ffu_ifu_tid_w2[1:0]),
.ffu_ifu_stallreq (ffu_ifu_stallreq),
.ffu_ifu_ecc_ce_w2 (ffu_ifu_ecc_ce_w2),
.ffu_ifu_ecc_ue_w2 (ffu_ifu_ecc_ue_w2),
.ffu_ifu_err_reg_w2(ffu_ifu_err_reg_w2[5:0]),
.ffu_ifu_err_synd_w2(ffu_ifu_err_synd_w2[13:0]),
.ffu_ifu_fst_ce_w (ffu_ifu_fst_ce_w),
.ffu_lsu_kill_fst_w(ffu_lsu_kill_fst_w),
.ffu_ifu_inj_ack (ffu_ifu_inj_ack),
.ffu_lsu_data (ffu_lsu_data[80:64]),
.ffu_lsu_fpop_rq_vld(ffu_lsu_fpop_rq_vld),
.ffu_lsu_blk_st_va_e(ffu_lsu_blk_st_va_e[5:3]),
.ffu_lsu_blk_st_e (ffu_lsu_blk_st_e),
.ffu_tlu_trap_ieee754(ffu_tlu_trap_ieee754),
.ffu_tlu_trap_other(ffu_tlu_trap_other),
.ffu_tlu_trap_ue (ffu_tlu_trap_ue),
.ffu_tlu_ill_inst_m(ffu_tlu_ill_inst_m),
.ffu_tlu_fpu_tid (ffu_tlu_fpu_tid[1:0]),
.ffu_tlu_fpu_cmplt (ffu_tlu_fpu_cmplt),
.ctl_frf_ren (ctl_frf_ren),
.ctl_frf_wen (ctl_frf_wen[1:0]),
.ctl_frf_addr (ctl_frf_addr[6:0]),
.ctl_dp_fp_thr (ctl_dp_fp_thr[3:0]),
.ctl_dp_fcc_w2 (ctl_dp_fcc_w2[7:0]),
.ctl_dp_ftt_w2 (ctl_dp_ftt_w2[2:0]),
.ctl_dp_exc_w2 (ctl_dp_exc_w2[9:0]),
.ctl_dp_ecc_sel_frf(ctl_dp_ecc_sel_frf),
.ctl_dp_output_sel_rs1(ctl_dp_output_sel_rs1),
.ctl_dp_output_sel_rs2(ctl_dp_output_sel_rs2),
.ctl_dp_output_sel_frf(ctl_dp_output_sel_frf),
.ctl_dp_output_sel_fsr(ctl_dp_output_sel_fsr),
.ctl_dp_rs2_frf_read(ctl_dp_rs2_frf_read),
.ctl_dp_rs2_sel_vis(ctl_dp_rs2_sel_vis),
.ctl_dp_rs2_sel_fpu_lsu(ctl_dp_rs2_sel_fpu_lsu),
.ctl_dp_rs2_keep_data(ctl_dp_rs2_keep_data),
.ctl_dp_rd_ecc (ctl_dp_rd_ecc),
.ctl_dp_fsr_sel_ld (ctl_dp_fsr_sel_ld[3:0]),
.ctl_dp_fsr_sel_fpu(ctl_dp_fsr_sel_fpu[3:0]),
.ctl_dp_fsr_sel_old(ctl_dp_fsr_sel_old[3:0]),
.ctl_dp_noshift64_frf(ctl_dp_noshift64_frf),
.ctl_dp_shift_frf_right(ctl_dp_shift_frf_right),
.ctl_dp_shift_frf_left(ctl_dp_shift_frf_left),
.ctl_dp_zero_low32_frf(ctl_dp_zero_low32_frf),
.ctl_dp_new_rs1 (ctl_dp_new_rs1),
.ctl_dp_sign (ctl_dp_sign[1:0]),
.ctl_dp_flip_fpu (ctl_dp_flip_fpu),
.ctl_dp_flip_lsu (ctl_dp_flip_lsu),
.ctl_dp_noflip_fpu (ctl_dp_noflip_fpu),
.ctl_dp_noflip_lsu (ctl_dp_noflip_lsu),
// Inputs
.dp_ctl_gsr_mask_e (dp_ctl_gsr_mask_e[31:0]),
.dp_ctl_gsr_scale_e(dp_ctl_gsr_scale_e[4:0]),
.exu_ffu_gsr_align_m(exu_ffu_gsr_align_m[2:0]),
.exu_ffu_gsr_mask_m(exu_ffu_gsr_mask_m[31:0]),
.exu_ffu_gsr_rnd_m (exu_ffu_gsr_rnd_m[2:0]),
.exu_ffu_gsr_scale_m(exu_ffu_gsr_scale_m[4:0]),
.exu_ffu_wsr_inst_e(exu_ffu_wsr_inst_e),
.ifu_tlu_sraddr_d (ifu_tlu_sraddr_d[6:0]),
.lsu_ffu_st_dtlb_perr_g (lsu_ffu_st_dtlb_perr_g), //sotheas,8/17/04: fixed eco 6529
.rclk (rclk),
.se (se),
.grst_l (grst_l),
.arst_l (arst_l),
.dp_ctl_rs2_sign (dp_ctl_rs2_sign[1:0]),
.cpx_vld (cpx_vld),
.cpx_fcmp (cpx_fcmp),
.cpx_req (cpx_req[3:0]),
.cpx_fccval (cpx_fccval[1:0]),
.cpx_fpexc (cpx_fpexc[4:0]),
.dp_ctl_fsr_fcc (dp_ctl_fsr_fcc[7:0]),
.dp_ctl_fsr_rnd (dp_ctl_fsr_rnd[1:0]),
.dp_ctl_fsr_tem (dp_ctl_fsr_tem[4:0]),
.dp_ctl_fsr_aexc (dp_ctl_fsr_aexc[4:0]),
.dp_ctl_fsr_cexc (dp_ctl_fsr_cexc[4:0]),
.dp_ctl_synd_out_low(dp_ctl_synd_out_low[6:0]),
.dp_ctl_synd_out_high(dp_ctl_synd_out_high[6:0]),
.ifu_ffu_fpop1_d (ifu_ffu_fpop1_d),
.ifu_ffu_fpop2_d (ifu_ffu_fpop2_d),
.ifu_ffu_visop_d (ifu_ffu_visop_d),
.ifu_ffu_fpopcode_d(ifu_ffu_fpopcode_d[8:0]),
.ifu_ffu_frs1_d (ifu_ffu_frs1_d[4:0]),
.ifu_ffu_frs2_d (ifu_ffu_frs2_d[4:0]),
.ifu_ffu_frd_d (ifu_ffu_frd_d[4:0]),
.ifu_ffu_fld_d (ifu_ffu_fld_d),
.ifu_ffu_fst_d (ifu_ffu_fst_d),
.ifu_ffu_ldst_single_d(ifu_ffu_ldst_single_d),
.ifu_ffu_tid_d (ifu_ffu_tid_d[1:0]),
.ifu_ffu_fcc_num_d (ifu_ffu_fcc_num_d[1:0]),
.ifu_ffu_mvcnd_m (ifu_ffu_mvcnd_m),
.ifu_ffu_inj_frferr(ifu_ffu_inj_frferr),
.ifu_exu_ecc_mask (ifu_exu_ecc_mask[6:0]),
.ifu_ffu_ldfsr_d (ifu_ffu_ldfsr_d),
.ifu_ffu_ldxfsr_d (ifu_ffu_ldxfsr_d),
.ifu_ffu_stfsr_d (ifu_ffu_stfsr_d),
.ifu_ffu_quad_op_e (ifu_ffu_quad_op_e),
.ifu_tlu_inst_vld_w(ifu_tlu_inst_vld_w),
.lsu_ffu_flush_pipe_w(lsu_ffu_flush_pipe_w),
.ifu_tlu_flush_w (ifu_tlu_flush_w),
.lsu_ffu_ack (lsu_ffu_ack),
.lsu_ffu_ld_vld (lsu_ffu_ld_vld),
.lsu_ffu_bld_cnt_w (lsu_ffu_bld_cnt_w[2:0]),
.dp_ctl_ld_fcc (dp_ctl_ld_fcc[7:0]),
.ifu_exu_nceen_e (ifu_exu_nceen_e),
.ifu_exu_disable_ce_e(ifu_exu_disable_ce_e),
.lsu_ffu_blk_asi_e (lsu_ffu_blk_asi_e),
.exu_ffu_ist_e (exu_ffu_ist_e),
.ifu_tlu_flsh_inst_e(ifu_tlu_flsh_inst_e),
.ifu_lsu_ld_inst_e (ifu_lsu_ld_inst_e),
.lsu_ffu_stb_full0 (lsu_ffu_stb_full0),
.lsu_ffu_stb_full1 (lsu_ffu_stb_full1),
.lsu_ffu_stb_full2 (lsu_ffu_stb_full2),
.lsu_ffu_stb_full3 (lsu_ffu_stb_full3));
sparc_ffu_vis vis(/*AUTOINST*/
// Outputs
.vis_dp_rd_data (vis_dp_rd_data[63:0]),
// Inputs
.dp_vis_rs1_data (dp_vis_rs1_data[63:0]),
.dp_vis_rs2_data (dp_vis_rs2_data[63:0]),
.ctl_vis_sel_add (ctl_vis_sel_add),
.ctl_vis_sel_log (ctl_vis_sel_log),
.ctl_vis_sel_align (ctl_vis_sel_align),
.ctl_vis_add32 (ctl_vis_add32),
.ctl_vis_subtract (ctl_vis_subtract),
.ctl_vis_cin (ctl_vis_cin),
.ctl_vis_align0 (ctl_vis_align0),
.ctl_vis_align2 (ctl_vis_align2),
.ctl_vis_align4 (ctl_vis_align4),
.ctl_vis_align6 (ctl_vis_align6),
.ctl_vis_align_odd (ctl_vis_align_odd),
.ctl_vis_log_sel_pass(ctl_vis_log_sel_pass),
.ctl_vis_log_sel_nand(ctl_vis_log_sel_nand),
.ctl_vis_log_sel_nor(ctl_vis_log_sel_nor),
.ctl_vis_log_sel_xor(ctl_vis_log_sel_xor),
.ctl_vis_log_invert_rs1(ctl_vis_log_invert_rs1),
.ctl_vis_log_invert_rs2(ctl_vis_log_invert_rs2),
.ctl_vis_log_constant(ctl_vis_log_constant),
.ctl_vis_log_pass_const(ctl_vis_log_pass_const),
.ctl_vis_log_pass_rs1(ctl_vis_log_pass_rs1),
.ctl_vis_log_pass_rs2(ctl_vis_log_pass_rs2));
endmodule // sparc_ffu
// Local Variables:
// verilog-library-directories:("." "../../../srams/rtl")
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYBUF4S15KAPWR_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__DLYBUF4S15KAPWR_PP_BLACKBOX_V
/**
* dlybuf4s15kapwr: Delay Buffer 4-stage 0.15um length inner stage
* gates on keep-alive power rail.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlybuf4s15kapwr (
X ,
A ,
VPWR ,
VGND ,
KAPWR,
VPB ,
VNB
);
output X ;
input A ;
input VPWR ;
input VGND ;
input KAPWR;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYBUF4S15KAPWR_PP_BLACKBOX_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: California State University San Bernardino
// Engineer: Bogdan Kravtsov
// Tyler Clayton
//
// Create Date: 15:17:23 10/24/2016
// Module Name: ALU_MUX_tb
// Project Name: MIPS
// Description: Testing MIPS 2-to-1 32-bit MUX implementation in verilog.
//
// Dependencies: ALU_MUX.v
//
////////////////////////////////////////////////////////////////////////////////
module ALU_MUX_tb;
// Declare inputs.
reg [31:0] A, B;
reg sel;
// Declare outputs.
wire [31:0] Y;
// Instantiate the MUX module.
ALU_MUX mux(.a(A), .b(B), .sel(sel), .y(Y));
initial begin
// Initialize inputs.
A = 0;
B = 0;
sel = 0;
// Provide test values.
A = 32'hAAAAAAAA;
B = 32'h55555555;
sel = 1'b1;
#10;
A = 32'h00000000;
#10;
sel = 1'b1;
#10;
B = 32'hFFFFFFFF;
#5;
A = 32'hA5A5A5A5;
#5;
sel = 1'b0;
B = 32'hDDDDDDDD;
#5;
sel = 1'bx;
// Terminate.
$finish;
end
// Whenever a change occurs to A, B or sel, display information.
always @ (A or B or sel)
#1 $display("At t = %0d sel %b A = %h B = %h Y = %h",
$time, sel, A, B, Y);
endmodule
|
// FIXME - naming convention in this file!!
module serial_wb_io(/*AUTOARG*/
// Outputs
tx_o, data_o, parport_o, parport_readstrobe_o,
parport_writestrobe_o, wbm_dat_o, wbm_adr_o, wbm_cyc_o,
wbm_lock_o, wbm_sel_o, wbm_stb_o, wbm_we_o,
// Inputs
clk_i, rst_i, rx_i, address_i, data_i, parport_i, read_strobe_i,
write_strobe_i, wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i
);
input wire clk_i;
input wire rst_i;
input wire rx_i;
output tx_o;
input wire [7:0] address_i;
input wire [7:0] data_i;
output reg [7:0] data_o;
input wire [31:0] parport_i;
output wire [31:0] parport_o;
output parport_readstrobe_o;
output parport_writestrobe_o;
input wire read_strobe_i;
input wire write_strobe_i;
// Wishbone master interface wbm_*:
input wire [31:0] wbm_dat_i;
output [31:0] wbm_dat_o;
input wire wbm_ack_i;
output [31:0] wbm_adr_o;
output wbm_cyc_o;
input wire wbm_err_i;
output wbm_lock_o;
input wire wbm_rty_i;
output [3:0] wbm_sel_o;
output wbm_stb_o;
output wbm_we_o;
wire [7:0] uart_data;
wire [7:0] wb_data;
wire [7:0] parport_data;
// Uart on address 0 and 1
wire uart_read_strobe = (address_i[7:1] == 7'b0) && read_strobe_i;
wire uart_write_strobe = (address_i[7:1] == 7'b0) && write_strobe_i;
// Parport on address 4 to 7
wire pp_read_strobe = (address_i[7:2] == 6'b1) && read_strobe_i;
wire pp_write_strobe = (address_i[7:2] == 7'b1) && write_strobe_i;
wire wbbridge_strobe = (address_i[7:4] == 4'b1) && write_strobe_i;
always @(*) begin
data_o = uart_data;
if(address_i[7:2] == 6'b1) begin
data_o = parport_data;
end else if(address_i[7:4] == 4'b1) begin
data_o = wb_data;
end
end
serial_wb_uart uart(// Outputs
.tx_o (tx_o),
.data_o (uart_data),
// Inputs
.clk_i (clk_i),
.rst_i (rst_i),
.rx_i (rx_i),
.writestrobe_i (uart_write_strobe),
.data_i (data_i),
.address_i (address_i[0]),
.readstrobe_i (uart_read_strobe));
serial_wb_parport parport(
// Outputs
.parport_o (parport_o),
.parport_readstrobe_o (parport_readstrobe_o),
.parport_writestrobe_o (parport_writestrobe_o),
.data_o (parport_data),
// Inputs
.clk_i (clk_i),
.rst_i (rst_i),
.parport_i (parport_i[31:0]),
.writestrobe_i(pp_write_strobe),
.data_i (data_i[7:0]),
.address_i (address_i[1:0]),
.readstrobe_i(pp_read_strobe));
serial_wb_wbmaster wbmaster(
.clk_i (clk_i),
.rst_i (rst_i),
// System connect interface
.data_o (wb_data),
.data_i (data_i),
.writestrobe_i(wbbridge_strobe),
.address_i(address_i),
// Wishbone interface
.wbm_dat_o(wbm_dat_o),
.wbm_adr_o(wbm_adr_o),
.wbm_cyc_o(wbm_cyc_o),
.wbm_lock_o(wbm_lock_o),
.wbm_sel_o(wbm_sel_o),
.wbm_stb_o(wbm_stb_o),
.wbm_we_o(wbm_we_o),
.wbm_dat_i(wbm_dat_i),
.wbm_ack_i(wbm_ack_i),
.wbm_err_i(wbm_err_i),
.wbm_rty_i(wbm_rty_i));
endmodule // serial_wb_io
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module is a rom for auto initializing the on board ADV7180 video chip.*
* *
******************************************************************************/
module altera_up_av_config_auto_init_ob_adv7180 (
// Inputs
rom_address,
// Bidirectionals
// Outputs
rom_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter INPUT_CTRL = 16'h0000;
parameter VIDEO_SELECTION = 16'h01C8;
parameter OUTPUT_CTRL = 16'h030C;
parameter EXT_OUTPUT_CTRL = 16'h0445;
parameter AUTODETECT = 16'h077F;
parameter BRIGHTNESS = 16'h0A00;
parameter HUE = 16'h0B00;
parameter DEFAULT_VALUE_Y = 16'h0C36;
parameter DEFAULT_VALUE_C = 16'h0D7C;
parameter POWER_MGMT = 16'h0F00;
parameter ANALOG_CLAMP_CTRL = 16'h1412;
parameter DIGITAL_CLAMP_CTRL = 16'h1500;
parameter SHAPING_FILTER_CTRL_1 = 16'h1701;
parameter SHAPING_FILTER_CTRL_2 = 16'h1893;
parameter COMB_FILTER_CTRL_2 = 16'h19F1;
parameter PIXEL_DELAY_CTRL = 16'h2758;
parameter MISC_GAIN_CTRL = 16'h2BE1;
parameter AGC_MODE_CTRL = 16'h2CAE;
parameter CHROMA_GAIN_CTRL_1 = 16'h2DF4;
parameter CHROMA_GAIN_CTRL_2 = 16'h2E00;
parameter LUMA_GAIN_CTRL_1 = 16'h2FF0;
parameter LUMA_GAIN_CTRL_2 = 16'h3000;
parameter VSYNC_FIELD_CTRL_1 = 16'h3112;
parameter VSYNC_FIELD_CTRL_2 = 16'h3241;
parameter VSYNC_FIELD_CTRL_3 = 16'h3384;
parameter HSYNC_FIELD_CTRL_1 = 16'h3400;
parameter HSYNC_FIELD_CTRL_2 = 16'h3502;
parameter HSYNC_FIELD_CTRL_3 = 16'h3600;
parameter POLARITY = 16'h3701;
parameter NTSC_COMB_CTRL = 16'h3880;
parameter PAL_COMB_CTRL = 16'h39C0;
parameter ADC_CTRL = 16'h3A10;
parameter MANUAL_WINDOW_CTRL = 16'h3DB2;
parameter RESAMPLE_CONTROL = 16'h4101;
parameter CRC = 16'hB21C;
parameter ADC_SWITCH_1 = 16'hC300;
parameter ADC_SWITCH_2 = 16'hC400;
parameter LETTERBOX_CTRL_1 = 16'hDCAC;
parameter LETTERBOX_CTRL_2 = 16'hDD4C;
parameter NTSC_V_BIT_BEGIN = 16'hE525;
parameter NTSC_V_BIT_END = 16'hE604;
parameter NTSC_F_BIT_TOGGLE = 16'hE763;
parameter PAL_V_BIT_BEGIN = 16'hE865;
parameter PAL_V_BIT_END = 16'hE914;
parameter PAL_F_BIT_TOGGLE = 16'hEA63;
parameter VBLANK_CTRL_1 = 16'hEB55;
parameter VBLANK_CTRL_2 = 16'hEC55;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input [ 5: 0] rom_address;
// Bidirectionals
// Outputs
output [26: 0] rom_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
reg [23: 0] data;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign rom_data = {data[23:16], 1'b0,
data[15: 8], 1'b0,
data[ 7: 0], 1'b0};
// Internal Assignments
always @(*)
begin
case (rom_address)
// Video Config Data
10 : data <= {8'h40, INPUT_CTRL};
11 : data <= {8'h40, VIDEO_SELECTION};
12 : data <= {8'h40, OUTPUT_CTRL};
13 : data <= {8'h40, EXT_OUTPUT_CTRL};
14 : data <= {8'h40, AUTODETECT};
15 : data <= {8'h40, BRIGHTNESS};
16 : data <= {8'h40, HUE};
17 : data <= {8'h40, DEFAULT_VALUE_Y};
18 : data <= {8'h40, DEFAULT_VALUE_C};
19 : data <= {8'h40, POWER_MGMT};
20 : data <= {8'h40, ANALOG_CLAMP_CTRL};
21 : data <= {8'h40, DIGITAL_CLAMP_CTRL};
22 : data <= {8'h40, SHAPING_FILTER_CTRL_1};
23 : data <= {8'h40, SHAPING_FILTER_CTRL_2};
24 : data <= {8'h40, COMB_FILTER_CTRL_2};
25 : data <= {8'h40, PIXEL_DELAY_CTRL};
26 : data <= {8'h40, MISC_GAIN_CTRL};
27 : data <= {8'h40, AGC_MODE_CTRL};
28 : data <= {8'h40, CHROMA_GAIN_CTRL_1};
29 : data <= {8'h40, CHROMA_GAIN_CTRL_2};
30 : data <= {8'h40, LUMA_GAIN_CTRL_1};
31 : data <= {8'h40, LUMA_GAIN_CTRL_2};
32 : data <= {8'h40, VSYNC_FIELD_CTRL_1};
33 : data <= {8'h40, VSYNC_FIELD_CTRL_2};
34 : data <= {8'h40, VSYNC_FIELD_CTRL_3};
35 : data <= {8'h40, HSYNC_FIELD_CTRL_1};
36 : data <= {8'h40, HSYNC_FIELD_CTRL_2};
37 : data <= {8'h40, HSYNC_FIELD_CTRL_3};
38 : data <= {8'h40, POLARITY};
39 : data <= {8'h40, NTSC_COMB_CTRL};
40 : data <= {8'h40, PAL_COMB_CTRL};
41 : data <= {8'h40, ADC_CTRL};
42 : data <= {8'h40, MANUAL_WINDOW_CTRL};
43 : data <= {8'h40, RESAMPLE_CONTROL};
44 : data <= {8'h40, CRC};
45 : data <= {8'h40, ADC_SWITCH_1};
46 : data <= {8'h40, ADC_SWITCH_2};
47 : data <= {8'h40, LETTERBOX_CTRL_1};
48 : data <= {8'h40, LETTERBOX_CTRL_2};
49 : data <= {8'h40, NTSC_V_BIT_BEGIN};
50 : data <= {8'h40, NTSC_V_BIT_END};
51 : data <= {8'h40, NTSC_F_BIT_TOGGLE};
52 : data <= {8'h40, PAL_V_BIT_BEGIN};
53 : data <= {8'h40, PAL_V_BIT_END};
54 : data <= {8'h40, PAL_F_BIT_TOGGLE};
55 : data <= {8'h40, VBLANK_CTRL_1};
56 : data <= {8'h40, VBLANK_CTRL_2};
default : data <= {8'h00, 16'h0000};
endcase
end
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2015 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file TargetCmdFIFO.v when simulating
// the core, TargetCmdFIFO. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module TargetCmdFIFO(
clk,
rst,
din,
wr_en,
rd_en,
dout,
full,
almost_full,
empty
);
input clk;
input rst;
input [127 : 0] din;
input wr_en;
input rd_en;
output [127 : 0] dout;
output full;
output almost_full;
output empty;
// synthesis translate_off
FIFO_GENERATOR_V8_4 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(1),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(5),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(128),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(128),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("virtex6"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(1),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(2),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x72"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(5),
.C_PROG_EMPTY_TYPE_RACH(5),
.C_PROG_EMPTY_TYPE_RDCH(5),
.C_PROG_EMPTY_TYPE_WACH(5),
.C_PROG_EMPTY_TYPE_WDCH(5),
.C_PROG_EMPTY_TYPE_WRCH(5),
.C_PROG_FULL_THRESH_ASSERT_VAL(15),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(14),
.C_PROG_FULL_TYPE(0),
.C_PROG_FULL_TYPE_AXIS(5),
.C_PROG_FULL_TYPE_RACH(5),
.C_PROG_FULL_TYPE_RDCH(5),
.C_PROG_FULL_TYPE_WACH(5),
.C_PROG_FULL_TYPE_WDCH(5),
.C_PROG_FULL_TYPE_WRCH(5),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(5),
.C_RD_DEPTH(16),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(4),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(2),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(1),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(5),
.C_WR_DEPTH(16),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(4),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.CLK(clk),
.RST(rst),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.ALMOST_FULL(almost_full),
.EMPTY(empty),
.BACKUP(),
.BACKUP_MARKER(),
.SRST(),
.WR_CLK(),
.WR_RST(),
.RD_CLK(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.WR_ACK(),
.OVERFLOW(),
.ALMOST_EMPTY(),
.VALID(),
.UNDERFLOW(),
.DATA_COUNT(),
.RD_DATA_COUNT(),
.WR_DATA_COUNT(),
.PROG_FULL(),
.PROG_EMPTY(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW()
);
// synthesis translate_on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLCLKP_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__DLCLKP_PP_BLACKBOX_V
/**
* dlclkp: Clock gate.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlclkp (
GCLK,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
output GCLK;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLCLKP_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_DFF_P_TB_V
`define SKY130_FD_SC_LS__UDP_DFF_P_TB_V
/**
* udp_dff$P: Positive edge triggered D flip-flop (Q output UDP).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__udp_dff_p.v"
module top();
// Inputs are registered
reg D;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
#20 D = 1'b0;
#40 D = 1'b1;
#60 D = 1'b0;
#80 D = 1'b1;
#100 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_ls__udp_dff$P dut (.D(D), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_DFF_P_TB_V
|
//-------------------------------------------------------------------------
// COPYRIGHT (C) 2016 Univ. of Nebraska - Lincoln
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//-------------------------------------------------------------------------
// Title : daq_firmware
// Author : Caleb Fangmeier
// Description : This is the top-level design file for the telescope
// firmware
//
// $Id$
//-------------------------------------------------------------------------
`default_nettype none
`timescale 1ns / 1ps
module daq_firmware(
input wire [4:0] okUH,
output wire [2:0] okHU,
inout wire [31:0] okUHU,
inout wire okAA,
input wire sys_clk, // 50 MHz
output wire [1:0] led,
output wire [1:0] led_ext,
output wire [ 12: 0] mem_addr,
output wire [ 2: 0] mem_ba,
output wire mem_cas_n,
output wire [ 0: 0] mem_cke,
inout wire [ 0: 0] mem_clk,
inout wire [ 0: 0] mem_clk_n,
output wire [ 0: 0] mem_cs_n,
output wire [ 1: 0] mem_dm,
inout wire [ 15: 0] mem_dq,
inout wire [ 1: 0] mem_dqs,
output wire [ 0: 0] mem_odt,
output wire mem_ras_n,
output wire mem_we_n,
output wire rj45_led_sck,
output wire rj45_led_sin,
output wire rj45_led_lat,
output wire rj45_led_blk,
output wire sclk,
inout wire sdio,
output wire supdac_csb,
output wire rngdac_csb,
output wire [7:0] adc_csb,
output wire adc_clk, // 13.3 MHz
input wire [7:0] adc_fco,
input wire [7:0] adc_dco,
input wire [7:0] adc_dat_a,
input wire [7:0] adc_dat_b,
input wire [7:0] adc_dat_c,
input wire [7:0] adc_dat_d,
output wire flash_dq0,
input wire flash_dq1,
output wire flash_wb,
output wire flash_holdb,
output wire flash_c,
output wire flash_sb,
output wire apc_cal,
output wire apc_cs,
output wire apc_is1,
output wire apc_is2,
output wire apc_le,
output wire apc_null,
output wire apc_r12,
output wire apc_reset,
output wire apc_rphi1,
output wire apc_rphi2,
output wire apc_sbi,
output wire apc_seb,
output wire apc_sphi1,
output wire apc_sphi2,
output wire apc_sr,
output wire apc_rbo_a1,
output wire apc_rbo_b1,
output wire apc_rbo_a2,
output wire apc_rbo_b2,
output wire apc_rbo_a3,
output wire apc_rbo_b3,
output wire apc_rbo_a4,
output wire apc_rbo_b4,
input wire apc_rbi
);
wire clk;
wire reset;
wire memory_read_req;
wire memory_write_req;
wire [25:0] memory_addr;
wire [31:0] memory_data_write;
wire [31:0] memory_data_read;
wire memory_busy;
wire [24:0] pc;
wire [31:0] ir;
wire [1:0] muxMA_sel;
wire [2:0] cpu_stage;
wire [31:0] r1;
wire [31:0] r15;
wire wr_write;
wire [31:0] ry;
wire [31:0] rz;
wire [31:0] alu_inA;
wire [31:0] alu_inB;
wire [31:0] immediate;
wire [31:0] immediate_temp;
wire muxB_sel;
// High-Level Control Unit
control_unit control_unit_inst (
.clk ( clk ),
.reset ( reset ),
.memory_read_req ( memory_read_req ),
.memory_write_req ( memory_write_req ),
.memory_addr ( memory_addr ),
.memory_data_write ( memory_data_write ),
.memory_data_read ( memory_data_read ),
.memory_busy ( memory_busy ),
.pc ( pc ),
.ir ( ir ),
.muxMA_sel ( muxMA_sel ),
.cpu_stage ( cpu_stage ),
.r1 ( r1 ),
.r15 ( r15 ),
.wr_write ( wr_write ),
.rz ( rz ),
.ry ( ry ),
.alu_inA ( alu_inA ),
.alu_inB ( alu_inB ),
.immediate ( immediate ),
.immediate_temp ( immediate_temp ),
.muxB_sel ( muxB_sel )
);
hal hal_inst(
.sys_clk ( sys_clk ),
.clk ( clk ),
.reset ( reset ),
// Processor Interface
.memory_read_req ( memory_read_req ),
.memory_write_req ( memory_write_req ),
.memory_addr ( memory_addr ),
.memory_data_write ( memory_data_write ),
.memory_data_read ( memory_data_read ),
.memory_busy ( memory_busy ),
// Hardware Interface
.led ( led ),
.led_ext ( led_ext ),
.mem_addr ( mem_addr ),
.mem_ba ( mem_ba ),
.mem_cas_n ( mem_cas_n ),
.mem_cke ( mem_cke ),
.mem_clk ( mem_clk ),
.mem_clk_n ( mem_clk_n ),
.mem_cs_n ( mem_cs_n ),
.mem_dm ( mem_dm ),
.mem_dq ( mem_dq ),
.mem_dqs ( mem_dqs ),
.mem_odt ( mem_odt ),
.mem_ras_n ( mem_ras_n ),
.mem_we_n ( mem_we_n ),
.rj45_led_sck ( rj45_led_sck ),
.rj45_led_sin ( rj45_led_sin ),
.rj45_led_lat ( rj45_led_lat ),
.rj45_led_blk ( rj45_led_blk ),
.sclk ( sclk ),
.sdio ( sdio ),
.supdac_csb ( supdac_csb ),
.rngdac_csb ( rngdac_csb ),
.adc_csb ( adc_csb ),
.adc_clk ( adc_clk ), // 10 MHz
.adc_fco ( adc_fco ),
.adc_dco ( adc_dco ),
.adc_dat_a ( adc_dat_a ),
.adc_dat_b ( adc_dat_b ),
.adc_dat_c ( adc_dat_c ),
.adc_dat_d ( adc_dat_d ),
.flash_dq0 ( flash_dq0 ),
.flash_dq1 ( flash_dq1 ),
.flash_wb ( flash_wb ),
.flash_holdb ( flash_holdb ),
.flash_c ( flash_c ),
.flash_sb ( flash_sb ),
.apc_cal ( apc_cal ),
.apc_cs ( apc_cs ),
.apc_is1 ( apc_is1 ),
.apc_is2 ( apc_is2 ),
.apc_le ( apc_le ),
.apc_null ( apc_null ),
.apc_r12 ( apc_r12 ),
.apc_reset ( apc_reset ),
.apc_rphi1 ( apc_rphi1 ),
.apc_rphi2 ( apc_rphi2 ),
.apc_sbi ( apc_sbi ),
.apc_seb ( apc_seb ),
.apc_sphi1 ( apc_sphi1 ),
.apc_sphi2 ( apc_sphi2 ),
.apc_sr ( apc_sr ),
.apc_rbo_a1 ( apc_rbo_a1 ),
.apc_rbo_b1 ( apc_rbo_b1 ),
.apc_rbo_a2 ( apc_rbo_a2 ),
.apc_rbo_b2 ( apc_rbo_b2 ),
.apc_rbo_a3 ( apc_rbo_a3 ),
.apc_rbo_b3 ( apc_rbo_b3 ),
.apc_rbo_a4 ( apc_rbo_a4 ),
.apc_rbo_b4 ( apc_rbo_b4 ),
.apc_rbi ( apc_rbi ),
// FrontPanel Interface
.okUH ( okUH ),
.okHU ( okHU ),
.okUHU ( okUHU ),
.okAA ( okAA ),
.pc ( pc ),
.ir ( ir ),
.muxMA_sel ( muxMA_sel ),
.cpu_stage ( cpu_stage ),
.r1 ( r1 ),
.r15 ( r15 ),
.wr_write ( wr_write ),
.rz ( rz ),
.ry ( ry ),
.alu_inA ( alu_inA ),
.alu_inB ( alu_inB ),
.immediate ( immediate ),
.immediate_temp ( immediate_temp ),
.muxB_sel ( muxB_sel )
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFSBP_PP_SYMBOL_V
`define SKY130_FD_SC_HD__SDFSBP_PP_SYMBOL_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__sdfsbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input SET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFSBP_PP_SYMBOL_V
|
// Experiment about implementing of a 100% asynchronous "AND" function between
// request signals
// THis is just a arbitrer with the equivalent of a call function
// where xor gates have been replaced by AND gates
// using arbitrer_r1_2ph
module and_r1_2ph (/*AUTOARG*/
// Outputs
a1, a2, r,
// Inputs
r1, r2, a, rstn
);
// Input pandts
input r1;
output a1;
input r2;
output a2;
// output pandt
output r;
input a;
input rstn;
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTANDEG*/
/*AUTOWIRE*/
wire r;
wire r1,r2;
wire a1,a2;
wire g1,g2;
wire d1,d2;
arbitrer_r1_2ph U_ARBITRER(
// Input pandts
.r1 (r1),
.a1 (a1),
.r2 (r2),
.a2 (a2),
// Output pandts
.g1 (g1),
.g2 (g2),
.d1 (d1),
.d2 (d2),
.rstn (rstn));
// Structure is similar to the call block
// replacing the xor by an and
// and also inside the decision-wait element
// UPDATE : this does not work
// The following code seems to work way better
// If port #2 is zero, then the output r
// is already zero and not ready (a==1)
// else we have to wait for a
mux2 U_MUX2_1(.z(d1pre),
.s(d2),
.a0(g1),
.a1(a));
mux2 U_MUX2_2(.z(d2pre),
.s(d1),
.a0(g2),
.a1(a));
// and2 U_AND2_1(.z(d1pre), .a(a), .b(d2));
// and2 U_AND2_2(.z(d2pre), .a(d1), .b(a));
// We need some memory to keep the feedback when state change
// on the other port
muller2 U_MULLER_ACK1(.a(g1),.b(d1pre),.rstn(rstn),.z(d1));
muller2 U_MULLER_ACK2(.a(g2),.b(d2pre),.rstn(rstn),.z(d2));
and2 U_AND2_OUT(.z(r), .a(g1), .b(g2));
endmodule // and_r1_2ph
/*
Local Variables:
verilog-library-directories:(
"."
)
End:
*/
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND2_4_V
`define SKY130_FD_SC_LP__AND2_4_V
/**
* and2: 2-input AND.
*
* Verilog wrapper for and2 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__and2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and2_4 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__and2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and2_4 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__and2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND2_4_V
|
// (C) 1992-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_int_mult (
enable,
clock,
dataa,
datab,
result);
parameter INPUT1_WIDTH = 64;
parameter INPUT2_WIDTH = 64;
parameter OUTPUT_WIDTH = 64;
parameter SIGNED = 0;
parameter LATENCY = 3;
// Determine the complete size of the output.
localparam O_WIDTH = (OUTPUT_WIDTH > (INPUT1_WIDTH + INPUT2_WIDTH)) ? OUTPUT_WIDTH : (INPUT1_WIDTH + INPUT2_WIDTH);
localparam REP_STRING = (SIGNED == 0) ? "UNSIGNED" : "SIGNED";
input [INPUT1_WIDTH - 1 : 0] dataa;
input [INPUT2_WIDTH - 1 : 0] datab;
input enable;
input clock;
output [OUTPUT_WIDTH - 1 : 0] result;
generate
if ((INPUT1_WIDTH>=19) && (INPUT1_WIDTH<=27) && (INPUT2_WIDTH>=19) && (INPUT2_WIDTH<=27))
begin
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [INPUT1_WIDTH - 1 : 0] reg_dataa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [INPUT2_WIDTH - 1 : 0] reg_datab;
// Use a special WYSIWYG for the 27x27 multiplier mode
always@(posedge clock)
begin
if (enable)
begin
reg_dataa <= dataa;
reg_datab <= datab;
end
end
wire [53:0] output_wire;
wire [26:0] inp_a;
wire [26:0] inp_b;
assign inp_a = reg_dataa;
assign inp_b = reg_datab;
sv_mult27 the_multiplier(clock,enable,inp_a,inp_b, output_wire);
defparam the_multiplier.REPRESENTATION = REP_STRING;
if (SIGNED == 0)
begin
if (OUTPUT_WIDTH > 54)
assign result = {{{OUTPUT_WIDTH-54}{1'b0}}, output_wire};
else
assign result = output_wire[OUTPUT_WIDTH-1:0];
end
else
begin
if (OUTPUT_WIDTH > 54)
assign result = {{{OUTPUT_WIDTH-54}{output_wire[53]}}, output_wire};
else
assign result = output_wire[OUTPUT_WIDTH-1:0];
end
end
else if (((SIGNED == 0) && (OUTPUT_WIDTH >= 33) && (OUTPUT_WIDTH <= 64)) && ((INPUT1_WIDTH == 64) && (INPUT2_WIDTH >= 32) || (INPUT2_WIDTH == 64) && (INPUT1_WIDTH >= 32)))
begin : GEN_LONG_MUL //Karatsuba algorithm
localparam TMP1_WIDTH = (INPUT1_WIDTH > 32)? INPUT1_WIDTH : 33;
localparam TMP2_WIDTH = (INPUT2_WIDTH > 32)? INPUT2_WIDTH : 33;
reg [63:0] temp0;
reg [TMP1_WIDTH-1:0] R_a;
reg [TMP2_WIDTH-1:0] R_b;
reg [31:0] temp1, temp2;
reg [63:0] output_wire;
always@(posedge clock)
begin
if(enable)
begin
R_a <= dataa;
R_b <= datab;
temp0 <= R_a[31:0] * R_b[31:0];
temp1 <= R_a[31:0] * R_b[TMP2_WIDTH-1:32];
temp2 <= R_a[TMP1_WIDTH-1:32] * R_b[31:0];
output_wire[63:32] <= temp0[63:32] + temp1 + temp2;
output_wire[31:0] <= temp0[31:0];
end
end
assign result = output_wire[OUTPUT_WIDTH-1:0];
end
else if (LATENCY == 2)
begin
// Replacement for LPM_MULT with better QoR - uses a single input register
if (SIGNED == 0)
begin
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [O_WIDTH-1:0] output_reg;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [INPUT1_WIDTH - 1 : 0] reg_dataa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [INPUT2_WIDTH - 1 : 0] reg_datab;
always@(posedge clock)
begin
if (enable)
begin
output_reg <= reg_dataa * reg_datab;
reg_dataa <= dataa;
reg_datab <= datab;
end
end
assign result = output_reg[OUTPUT_WIDTH-1:0];
end
else
begin
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg signed [O_WIDTH-1:0] output_reg;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg signed [INPUT1_WIDTH - 1 : 0] reg_dataa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg signed [INPUT2_WIDTH - 1 : 0] reg_datab;
always@(posedge clock)
begin
if (enable)
begin
output_reg <= reg_dataa * reg_datab;
reg_dataa <= dataa;
reg_datab <= datab;
end
end
assign result = output_reg[OUTPUT_WIDTH-1:0];
end
end
else
begin
// Similar to above but uses 2 input registers to account for the pipeline register
if (SIGNED == 0)
begin
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [O_WIDTH-1:0] output_reg[LATENCY - 3 : 0];
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [INPUT1_WIDTH - 1 : 0] reg_dataa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [INPUT2_WIDTH - 1 : 0] reg_datab;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [INPUT1_WIDTH - 1 : 0] reg_dataa2;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [INPUT2_WIDTH - 1 : 0] reg_datab2;
genvar i;
for (i = 0; i < LATENCY - 3; i++) begin: postregs
always @(posedge clock)
begin
if (enable) begin
output_reg[i + 1] <= output_reg[i];
end
end
end
always@(posedge clock)
begin
if (enable)
begin
output_reg[0] <= reg_dataa2 * reg_datab2;
reg_dataa <= dataa;
reg_datab <= datab;
reg_dataa2 <= reg_dataa;
reg_datab2 <= reg_datab;
end
end
assign result = output_reg[LATENCY - 3][OUTPUT_WIDTH-1:0];
end
else
begin
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg signed [O_WIDTH-1:0] output_reg[LATENCY - 3 : 0];
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg signed [INPUT1_WIDTH - 1 : 0] reg_dataa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg signed [INPUT2_WIDTH - 1 : 0] reg_datab;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg signed [INPUT1_WIDTH - 1 : 0] reg_dataa2;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg signed [INPUT2_WIDTH - 1 : 0] reg_datab2;
genvar i;
for (i = 0; i < LATENCY - 3; i++) begin: postregs
always @(posedge clock)
begin
if (enable) begin
output_reg[i + 1] <= output_reg[i];
end
end
end
always@(posedge clock)
begin
if (enable)
begin
output_reg[0] <= reg_dataa2 * reg_datab2;
reg_dataa <= dataa;
reg_datab <= datab;
reg_dataa2 <= reg_dataa;
reg_datab2 <= reg_datab;
end
end
assign result = output_reg[LATENCY - 3][OUTPUT_WIDTH-1:0];
end
end
endgenerate
endmodule
|
`default_nettype none
module pipeline_control_hundler_read(
input wire iCLOCK,
input wire inRESET,
input wire iRESET_SYNC,
//System Register
input wire [31:0] iSYSREG_IDTR,
//Request
input wire iRD_START,
input wire [6:0] iRD_IRQ_NUM,
output wire oRD_FINISH,
output wire [31:0] oRD_HUNDLER,
//Load Store
output wire oLDST_USE,
output wire oLDST_REQ,
input wire iLDST_BUSY,
output wire [1:0] oLDST_ORDER, //00=Byte Order 01=2Byte Order 10= Word Order 11= None
output wire oLDST_RW, //0=Read 1=Write
output wire [13:0] oLDST_ASID,
output wire [1:0] oLDST_MMUMOD,
output wire [31:0] oLDST_PDT,
output wire [31:0] oLDST_ADDR,
output wire [31:0] oLDST_DATA,
input wire iLDST_REQ,
input wire [31:0] iLDST_DATA
);
localparam L_PARAM_INTHUNDLE_STT_IDLE = 1'b0;
localparam L_PARAM_INTHUNDLE_STT_LOAD = 1'b1;
reg b_inthundl_read_state;
reg b_inthundl_read;
reg b_inthundl_readend;
reg [31:0] b_inthundl_idt_data;
wire [31:0] inthundle_read_addr = iSYSREG_IDTR + {iRD_IRQ_NUM, 3'h0} + 32'h4;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_inthundl_read_state <= L_PARAM_INTHUNDLE_STT_IDLE;
b_inthundl_read <= 1'b0;
b_inthundl_readend <= 1'b0;
b_inthundl_idt_data <= 32'h0;
end
else if(iRESET_SYNC)begin
b_inthundl_read_state <= L_PARAM_INTHUNDLE_STT_IDLE;
b_inthundl_read <= 1'b0;
b_inthundl_readend <= 1'b0;
b_inthundl_idt_data <= 32'h0;
end
else begin
case(b_inthundl_read_state)
L_PARAM_INTHUNDLE_STT_IDLE:
begin
if(iRD_START)begin
b_inthundl_read_state <= L_PARAM_INTHUNDLE_STT_LOAD;
b_inthundl_read <= 1'b1;
end
else begin
b_inthundl_read <= 1'b0;
end
b_inthundl_readend <= 1'b0;
end
L_PARAM_INTHUNDLE_STT_LOAD:
begin
//Read Request
if(!iLDST_BUSY && b_inthundl_read)begin
b_inthundl_read <= 1'b0;
end
//Get Check
if(iLDST_REQ)begin
b_inthundl_readend <= 1'b1;
b_inthundl_read_state <= L_PARAM_INTHUNDLE_STT_IDLE;
b_inthundl_idt_data <= iLDST_DATA;
end
end
endcase
end
end
assign oRD_FINISH = b_inthundl_readend;
assign oRD_HUNDLER = b_inthundl_idt_data;
assign oLDST_USE = b_inthundl_read_state == L_PARAM_INTHUNDLE_STT_LOAD;
assign oLDST_REQ = b_inthundl_read;
assign oLDST_ORDER = 2'h2; //00=Byte Order 01=2Byte Order 10= Word Order 11= None
assign oLDST_RW = 1'b0; //0=Read 1=Write
assign oLDST_ASID = 14'h0;
assign oLDST_MMUMOD = 2'h0;
assign oLDST_PDT = 32'h0;
assign oLDST_ADDR = inthundle_read_addr;
assign oLDST_DATA = 32'h0;
endmodule
`default_nettype wire |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Thu Sep 14 10:33:19 2017
// Host : PC4719 running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_0_sim_netlist.v
// Design : vio_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7k325tffg676-2
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "vio_0,vio,{}" *) (* X_CORE_INFO = "vio,Vivado 2016.3" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(clk,
probe_in0,
probe_in1,
probe_in2);
input clk;
input [0:0]probe_in0;
input [0:0]probe_in1;
input [0:0]probe_in2;
wire clk;
wire [0:0]probe_in0;
wire [0:0]probe_in1;
wire [0:0]probe_in2;
wire [0:0]NLW_inst_probe_out0_UNCONNECTED;
wire [0:0]NLW_inst_probe_out1_UNCONNECTED;
wire [0:0]NLW_inst_probe_out10_UNCONNECTED;
wire [0:0]NLW_inst_probe_out100_UNCONNECTED;
wire [0:0]NLW_inst_probe_out101_UNCONNECTED;
wire [0:0]NLW_inst_probe_out102_UNCONNECTED;
wire [0:0]NLW_inst_probe_out103_UNCONNECTED;
wire [0:0]NLW_inst_probe_out104_UNCONNECTED;
wire [0:0]NLW_inst_probe_out105_UNCONNECTED;
wire [0:0]NLW_inst_probe_out106_UNCONNECTED;
wire [0:0]NLW_inst_probe_out107_UNCONNECTED;
wire [0:0]NLW_inst_probe_out108_UNCONNECTED;
wire [0:0]NLW_inst_probe_out109_UNCONNECTED;
wire [0:0]NLW_inst_probe_out11_UNCONNECTED;
wire [0:0]NLW_inst_probe_out110_UNCONNECTED;
wire [0:0]NLW_inst_probe_out111_UNCONNECTED;
wire [0:0]NLW_inst_probe_out112_UNCONNECTED;
wire [0:0]NLW_inst_probe_out113_UNCONNECTED;
wire [0:0]NLW_inst_probe_out114_UNCONNECTED;
wire [0:0]NLW_inst_probe_out115_UNCONNECTED;
wire [0:0]NLW_inst_probe_out116_UNCONNECTED;
wire [0:0]NLW_inst_probe_out117_UNCONNECTED;
wire [0:0]NLW_inst_probe_out118_UNCONNECTED;
wire [0:0]NLW_inst_probe_out119_UNCONNECTED;
wire [0:0]NLW_inst_probe_out12_UNCONNECTED;
wire [0:0]NLW_inst_probe_out120_UNCONNECTED;
wire [0:0]NLW_inst_probe_out121_UNCONNECTED;
wire [0:0]NLW_inst_probe_out122_UNCONNECTED;
wire [0:0]NLW_inst_probe_out123_UNCONNECTED;
wire [0:0]NLW_inst_probe_out124_UNCONNECTED;
wire [0:0]NLW_inst_probe_out125_UNCONNECTED;
wire [0:0]NLW_inst_probe_out126_UNCONNECTED;
wire [0:0]NLW_inst_probe_out127_UNCONNECTED;
wire [0:0]NLW_inst_probe_out128_UNCONNECTED;
wire [0:0]NLW_inst_probe_out129_UNCONNECTED;
wire [0:0]NLW_inst_probe_out13_UNCONNECTED;
wire [0:0]NLW_inst_probe_out130_UNCONNECTED;
wire [0:0]NLW_inst_probe_out131_UNCONNECTED;
wire [0:0]NLW_inst_probe_out132_UNCONNECTED;
wire [0:0]NLW_inst_probe_out133_UNCONNECTED;
wire [0:0]NLW_inst_probe_out134_UNCONNECTED;
wire [0:0]NLW_inst_probe_out135_UNCONNECTED;
wire [0:0]NLW_inst_probe_out136_UNCONNECTED;
wire [0:0]NLW_inst_probe_out137_UNCONNECTED;
wire [0:0]NLW_inst_probe_out138_UNCONNECTED;
wire [0:0]NLW_inst_probe_out139_UNCONNECTED;
wire [0:0]NLW_inst_probe_out14_UNCONNECTED;
wire [0:0]NLW_inst_probe_out140_UNCONNECTED;
wire [0:0]NLW_inst_probe_out141_UNCONNECTED;
wire [0:0]NLW_inst_probe_out142_UNCONNECTED;
wire [0:0]NLW_inst_probe_out143_UNCONNECTED;
wire [0:0]NLW_inst_probe_out144_UNCONNECTED;
wire [0:0]NLW_inst_probe_out145_UNCONNECTED;
wire [0:0]NLW_inst_probe_out146_UNCONNECTED;
wire [0:0]NLW_inst_probe_out147_UNCONNECTED;
wire [0:0]NLW_inst_probe_out148_UNCONNECTED;
wire [0:0]NLW_inst_probe_out149_UNCONNECTED;
wire [0:0]NLW_inst_probe_out15_UNCONNECTED;
wire [0:0]NLW_inst_probe_out150_UNCONNECTED;
wire [0:0]NLW_inst_probe_out151_UNCONNECTED;
wire [0:0]NLW_inst_probe_out152_UNCONNECTED;
wire [0:0]NLW_inst_probe_out153_UNCONNECTED;
wire [0:0]NLW_inst_probe_out154_UNCONNECTED;
wire [0:0]NLW_inst_probe_out155_UNCONNECTED;
wire [0:0]NLW_inst_probe_out156_UNCONNECTED;
wire [0:0]NLW_inst_probe_out157_UNCONNECTED;
wire [0:0]NLW_inst_probe_out158_UNCONNECTED;
wire [0:0]NLW_inst_probe_out159_UNCONNECTED;
wire [0:0]NLW_inst_probe_out16_UNCONNECTED;
wire [0:0]NLW_inst_probe_out160_UNCONNECTED;
wire [0:0]NLW_inst_probe_out161_UNCONNECTED;
wire [0:0]NLW_inst_probe_out162_UNCONNECTED;
wire [0:0]NLW_inst_probe_out163_UNCONNECTED;
wire [0:0]NLW_inst_probe_out164_UNCONNECTED;
wire [0:0]NLW_inst_probe_out165_UNCONNECTED;
wire [0:0]NLW_inst_probe_out166_UNCONNECTED;
wire [0:0]NLW_inst_probe_out167_UNCONNECTED;
wire [0:0]NLW_inst_probe_out168_UNCONNECTED;
wire [0:0]NLW_inst_probe_out169_UNCONNECTED;
wire [0:0]NLW_inst_probe_out17_UNCONNECTED;
wire [0:0]NLW_inst_probe_out170_UNCONNECTED;
wire [0:0]NLW_inst_probe_out171_UNCONNECTED;
wire [0:0]NLW_inst_probe_out172_UNCONNECTED;
wire [0:0]NLW_inst_probe_out173_UNCONNECTED;
wire [0:0]NLW_inst_probe_out174_UNCONNECTED;
wire [0:0]NLW_inst_probe_out175_UNCONNECTED;
wire [0:0]NLW_inst_probe_out176_UNCONNECTED;
wire [0:0]NLW_inst_probe_out177_UNCONNECTED;
wire [0:0]NLW_inst_probe_out178_UNCONNECTED;
wire [0:0]NLW_inst_probe_out179_UNCONNECTED;
wire [0:0]NLW_inst_probe_out18_UNCONNECTED;
wire [0:0]NLW_inst_probe_out180_UNCONNECTED;
wire [0:0]NLW_inst_probe_out181_UNCONNECTED;
wire [0:0]NLW_inst_probe_out182_UNCONNECTED;
wire [0:0]NLW_inst_probe_out183_UNCONNECTED;
wire [0:0]NLW_inst_probe_out184_UNCONNECTED;
wire [0:0]NLW_inst_probe_out185_UNCONNECTED;
wire [0:0]NLW_inst_probe_out186_UNCONNECTED;
wire [0:0]NLW_inst_probe_out187_UNCONNECTED;
wire [0:0]NLW_inst_probe_out188_UNCONNECTED;
wire [0:0]NLW_inst_probe_out189_UNCONNECTED;
wire [0:0]NLW_inst_probe_out19_UNCONNECTED;
wire [0:0]NLW_inst_probe_out190_UNCONNECTED;
wire [0:0]NLW_inst_probe_out191_UNCONNECTED;
wire [0:0]NLW_inst_probe_out192_UNCONNECTED;
wire [0:0]NLW_inst_probe_out193_UNCONNECTED;
wire [0:0]NLW_inst_probe_out194_UNCONNECTED;
wire [0:0]NLW_inst_probe_out195_UNCONNECTED;
wire [0:0]NLW_inst_probe_out196_UNCONNECTED;
wire [0:0]NLW_inst_probe_out197_UNCONNECTED;
wire [0:0]NLW_inst_probe_out198_UNCONNECTED;
wire [0:0]NLW_inst_probe_out199_UNCONNECTED;
wire [0:0]NLW_inst_probe_out2_UNCONNECTED;
wire [0:0]NLW_inst_probe_out20_UNCONNECTED;
wire [0:0]NLW_inst_probe_out200_UNCONNECTED;
wire [0:0]NLW_inst_probe_out201_UNCONNECTED;
wire [0:0]NLW_inst_probe_out202_UNCONNECTED;
wire [0:0]NLW_inst_probe_out203_UNCONNECTED;
wire [0:0]NLW_inst_probe_out204_UNCONNECTED;
wire [0:0]NLW_inst_probe_out205_UNCONNECTED;
wire [0:0]NLW_inst_probe_out206_UNCONNECTED;
wire [0:0]NLW_inst_probe_out207_UNCONNECTED;
wire [0:0]NLW_inst_probe_out208_UNCONNECTED;
wire [0:0]NLW_inst_probe_out209_UNCONNECTED;
wire [0:0]NLW_inst_probe_out21_UNCONNECTED;
wire [0:0]NLW_inst_probe_out210_UNCONNECTED;
wire [0:0]NLW_inst_probe_out211_UNCONNECTED;
wire [0:0]NLW_inst_probe_out212_UNCONNECTED;
wire [0:0]NLW_inst_probe_out213_UNCONNECTED;
wire [0:0]NLW_inst_probe_out214_UNCONNECTED;
wire [0:0]NLW_inst_probe_out215_UNCONNECTED;
wire [0:0]NLW_inst_probe_out216_UNCONNECTED;
wire [0:0]NLW_inst_probe_out217_UNCONNECTED;
wire [0:0]NLW_inst_probe_out218_UNCONNECTED;
wire [0:0]NLW_inst_probe_out219_UNCONNECTED;
wire [0:0]NLW_inst_probe_out22_UNCONNECTED;
wire [0:0]NLW_inst_probe_out220_UNCONNECTED;
wire [0:0]NLW_inst_probe_out221_UNCONNECTED;
wire [0:0]NLW_inst_probe_out222_UNCONNECTED;
wire [0:0]NLW_inst_probe_out223_UNCONNECTED;
wire [0:0]NLW_inst_probe_out224_UNCONNECTED;
wire [0:0]NLW_inst_probe_out225_UNCONNECTED;
wire [0:0]NLW_inst_probe_out226_UNCONNECTED;
wire [0:0]NLW_inst_probe_out227_UNCONNECTED;
wire [0:0]NLW_inst_probe_out228_UNCONNECTED;
wire [0:0]NLW_inst_probe_out229_UNCONNECTED;
wire [0:0]NLW_inst_probe_out23_UNCONNECTED;
wire [0:0]NLW_inst_probe_out230_UNCONNECTED;
wire [0:0]NLW_inst_probe_out231_UNCONNECTED;
wire [0:0]NLW_inst_probe_out232_UNCONNECTED;
wire [0:0]NLW_inst_probe_out233_UNCONNECTED;
wire [0:0]NLW_inst_probe_out234_UNCONNECTED;
wire [0:0]NLW_inst_probe_out235_UNCONNECTED;
wire [0:0]NLW_inst_probe_out236_UNCONNECTED;
wire [0:0]NLW_inst_probe_out237_UNCONNECTED;
wire [0:0]NLW_inst_probe_out238_UNCONNECTED;
wire [0:0]NLW_inst_probe_out239_UNCONNECTED;
wire [0:0]NLW_inst_probe_out24_UNCONNECTED;
wire [0:0]NLW_inst_probe_out240_UNCONNECTED;
wire [0:0]NLW_inst_probe_out241_UNCONNECTED;
wire [0:0]NLW_inst_probe_out242_UNCONNECTED;
wire [0:0]NLW_inst_probe_out243_UNCONNECTED;
wire [0:0]NLW_inst_probe_out244_UNCONNECTED;
wire [0:0]NLW_inst_probe_out245_UNCONNECTED;
wire [0:0]NLW_inst_probe_out246_UNCONNECTED;
wire [0:0]NLW_inst_probe_out247_UNCONNECTED;
wire [0:0]NLW_inst_probe_out248_UNCONNECTED;
wire [0:0]NLW_inst_probe_out249_UNCONNECTED;
wire [0:0]NLW_inst_probe_out25_UNCONNECTED;
wire [0:0]NLW_inst_probe_out250_UNCONNECTED;
wire [0:0]NLW_inst_probe_out251_UNCONNECTED;
wire [0:0]NLW_inst_probe_out252_UNCONNECTED;
wire [0:0]NLW_inst_probe_out253_UNCONNECTED;
wire [0:0]NLW_inst_probe_out254_UNCONNECTED;
wire [0:0]NLW_inst_probe_out255_UNCONNECTED;
wire [0:0]NLW_inst_probe_out26_UNCONNECTED;
wire [0:0]NLW_inst_probe_out27_UNCONNECTED;
wire [0:0]NLW_inst_probe_out28_UNCONNECTED;
wire [0:0]NLW_inst_probe_out29_UNCONNECTED;
wire [0:0]NLW_inst_probe_out3_UNCONNECTED;
wire [0:0]NLW_inst_probe_out30_UNCONNECTED;
wire [0:0]NLW_inst_probe_out31_UNCONNECTED;
wire [0:0]NLW_inst_probe_out32_UNCONNECTED;
wire [0:0]NLW_inst_probe_out33_UNCONNECTED;
wire [0:0]NLW_inst_probe_out34_UNCONNECTED;
wire [0:0]NLW_inst_probe_out35_UNCONNECTED;
wire [0:0]NLW_inst_probe_out36_UNCONNECTED;
wire [0:0]NLW_inst_probe_out37_UNCONNECTED;
wire [0:0]NLW_inst_probe_out38_UNCONNECTED;
wire [0:0]NLW_inst_probe_out39_UNCONNECTED;
wire [0:0]NLW_inst_probe_out4_UNCONNECTED;
wire [0:0]NLW_inst_probe_out40_UNCONNECTED;
wire [0:0]NLW_inst_probe_out41_UNCONNECTED;
wire [0:0]NLW_inst_probe_out42_UNCONNECTED;
wire [0:0]NLW_inst_probe_out43_UNCONNECTED;
wire [0:0]NLW_inst_probe_out44_UNCONNECTED;
wire [0:0]NLW_inst_probe_out45_UNCONNECTED;
wire [0:0]NLW_inst_probe_out46_UNCONNECTED;
wire [0:0]NLW_inst_probe_out47_UNCONNECTED;
wire [0:0]NLW_inst_probe_out48_UNCONNECTED;
wire [0:0]NLW_inst_probe_out49_UNCONNECTED;
wire [0:0]NLW_inst_probe_out5_UNCONNECTED;
wire [0:0]NLW_inst_probe_out50_UNCONNECTED;
wire [0:0]NLW_inst_probe_out51_UNCONNECTED;
wire [0:0]NLW_inst_probe_out52_UNCONNECTED;
wire [0:0]NLW_inst_probe_out53_UNCONNECTED;
wire [0:0]NLW_inst_probe_out54_UNCONNECTED;
wire [0:0]NLW_inst_probe_out55_UNCONNECTED;
wire [0:0]NLW_inst_probe_out56_UNCONNECTED;
wire [0:0]NLW_inst_probe_out57_UNCONNECTED;
wire [0:0]NLW_inst_probe_out58_UNCONNECTED;
wire [0:0]NLW_inst_probe_out59_UNCONNECTED;
wire [0:0]NLW_inst_probe_out6_UNCONNECTED;
wire [0:0]NLW_inst_probe_out60_UNCONNECTED;
wire [0:0]NLW_inst_probe_out61_UNCONNECTED;
wire [0:0]NLW_inst_probe_out62_UNCONNECTED;
wire [0:0]NLW_inst_probe_out63_UNCONNECTED;
wire [0:0]NLW_inst_probe_out64_UNCONNECTED;
wire [0:0]NLW_inst_probe_out65_UNCONNECTED;
wire [0:0]NLW_inst_probe_out66_UNCONNECTED;
wire [0:0]NLW_inst_probe_out67_UNCONNECTED;
wire [0:0]NLW_inst_probe_out68_UNCONNECTED;
wire [0:0]NLW_inst_probe_out69_UNCONNECTED;
wire [0:0]NLW_inst_probe_out7_UNCONNECTED;
wire [0:0]NLW_inst_probe_out70_UNCONNECTED;
wire [0:0]NLW_inst_probe_out71_UNCONNECTED;
wire [0:0]NLW_inst_probe_out72_UNCONNECTED;
wire [0:0]NLW_inst_probe_out73_UNCONNECTED;
wire [0:0]NLW_inst_probe_out74_UNCONNECTED;
wire [0:0]NLW_inst_probe_out75_UNCONNECTED;
wire [0:0]NLW_inst_probe_out76_UNCONNECTED;
wire [0:0]NLW_inst_probe_out77_UNCONNECTED;
wire [0:0]NLW_inst_probe_out78_UNCONNECTED;
wire [0:0]NLW_inst_probe_out79_UNCONNECTED;
wire [0:0]NLW_inst_probe_out8_UNCONNECTED;
wire [0:0]NLW_inst_probe_out80_UNCONNECTED;
wire [0:0]NLW_inst_probe_out81_UNCONNECTED;
wire [0:0]NLW_inst_probe_out82_UNCONNECTED;
wire [0:0]NLW_inst_probe_out83_UNCONNECTED;
wire [0:0]NLW_inst_probe_out84_UNCONNECTED;
wire [0:0]NLW_inst_probe_out85_UNCONNECTED;
wire [0:0]NLW_inst_probe_out86_UNCONNECTED;
wire [0:0]NLW_inst_probe_out87_UNCONNECTED;
wire [0:0]NLW_inst_probe_out88_UNCONNECTED;
wire [0:0]NLW_inst_probe_out89_UNCONNECTED;
wire [0:0]NLW_inst_probe_out9_UNCONNECTED;
wire [0:0]NLW_inst_probe_out90_UNCONNECTED;
wire [0:0]NLW_inst_probe_out91_UNCONNECTED;
wire [0:0]NLW_inst_probe_out92_UNCONNECTED;
wire [0:0]NLW_inst_probe_out93_UNCONNECTED;
wire [0:0]NLW_inst_probe_out94_UNCONNECTED;
wire [0:0]NLW_inst_probe_out95_UNCONNECTED;
wire [0:0]NLW_inst_probe_out96_UNCONNECTED;
wire [0:0]NLW_inst_probe_out97_UNCONNECTED;
wire [0:0]NLW_inst_probe_out98_UNCONNECTED;
wire [0:0]NLW_inst_probe_out99_UNCONNECTED;
wire [16:0]NLW_inst_sl_oport0_UNCONNECTED;
(* C_BUILD_REVISION = "0" *)
(* C_BUS_ADDR_WIDTH = "17" *)
(* C_BUS_DATA_WIDTH = "16" *)
(* C_CORE_INFO1 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* C_CORE_INFO2 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* C_CORE_MAJOR_VER = "2" *)
(* C_CORE_MINOR_ALPHA_VER = "97" *)
(* C_CORE_MINOR_VER = "0" *)
(* C_CORE_TYPE = "2" *)
(* C_CSE_DRV_VER = "1" *)
(* C_EN_PROBE_IN_ACTIVITY = "1" *)
(* C_EN_SYNCHRONIZATION = "1" *)
(* C_MAJOR_VERSION = "2013" *)
(* C_MAX_NUM_PROBE = "256" *)
(* C_MAX_WIDTH_PER_PROBE = "256" *)
(* C_MINOR_VERSION = "1" *)
(* C_NEXT_SLAVE = "0" *)
(* C_NUM_PROBE_IN = "3" *)
(* C_NUM_PROBE_OUT = "0" *)
(* C_PIPE_IFACE = "0" *)
(* C_PROBE_IN0_WIDTH = "1" *)
(* C_PROBE_IN100_WIDTH = "1" *)
(* C_PROBE_IN101_WIDTH = "1" *)
(* C_PROBE_IN102_WIDTH = "1" *)
(* C_PROBE_IN103_WIDTH = "1" *)
(* C_PROBE_IN104_WIDTH = "1" *)
(* C_PROBE_IN105_WIDTH = "1" *)
(* C_PROBE_IN106_WIDTH = "1" *)
(* C_PROBE_IN107_WIDTH = "1" *)
(* C_PROBE_IN108_WIDTH = "1" *)
(* C_PROBE_IN109_WIDTH = "1" *)
(* C_PROBE_IN10_WIDTH = "1" *)
(* C_PROBE_IN110_WIDTH = "1" *)
(* C_PROBE_IN111_WIDTH = "1" *)
(* C_PROBE_IN112_WIDTH = "1" *)
(* C_PROBE_IN113_WIDTH = "1" *)
(* C_PROBE_IN114_WIDTH = "1" *)
(* C_PROBE_IN115_WIDTH = "1" *)
(* C_PROBE_IN116_WIDTH = "1" *)
(* C_PROBE_IN117_WIDTH = "1" *)
(* C_PROBE_IN118_WIDTH = "1" *)
(* C_PROBE_IN119_WIDTH = "1" *)
(* C_PROBE_IN11_WIDTH = "1" *)
(* C_PROBE_IN120_WIDTH = "1" *)
(* C_PROBE_IN121_WIDTH = "1" *)
(* C_PROBE_IN122_WIDTH = "1" *)
(* C_PROBE_IN123_WIDTH = "1" *)
(* C_PROBE_IN124_WIDTH = "1" *)
(* C_PROBE_IN125_WIDTH = "1" *)
(* C_PROBE_IN126_WIDTH = "1" *)
(* C_PROBE_IN127_WIDTH = "1" *)
(* C_PROBE_IN128_WIDTH = "1" *)
(* C_PROBE_IN129_WIDTH = "1" *)
(* C_PROBE_IN12_WIDTH = "1" *)
(* C_PROBE_IN130_WIDTH = "1" *)
(* C_PROBE_IN131_WIDTH = "1" *)
(* C_PROBE_IN132_WIDTH = "1" *)
(* C_PROBE_IN133_WIDTH = "1" *)
(* C_PROBE_IN134_WIDTH = "1" *)
(* C_PROBE_IN135_WIDTH = "1" *)
(* C_PROBE_IN136_WIDTH = "1" *)
(* C_PROBE_IN137_WIDTH = "1" *)
(* C_PROBE_IN138_WIDTH = "1" *)
(* C_PROBE_IN139_WIDTH = "1" *)
(* C_PROBE_IN13_WIDTH = "1" *)
(* C_PROBE_IN140_WIDTH = "1" *)
(* C_PROBE_IN141_WIDTH = "1" *)
(* C_PROBE_IN142_WIDTH = "1" *)
(* C_PROBE_IN143_WIDTH = "1" *)
(* C_PROBE_IN144_WIDTH = "1" *)
(* C_PROBE_IN145_WIDTH = "1" *)
(* C_PROBE_IN146_WIDTH = "1" *)
(* C_PROBE_IN147_WIDTH = "1" *)
(* C_PROBE_IN148_WIDTH = "1" *)
(* C_PROBE_IN149_WIDTH = "1" *)
(* C_PROBE_IN14_WIDTH = "1" *)
(* C_PROBE_IN150_WIDTH = "1" *)
(* C_PROBE_IN151_WIDTH = "1" *)
(* C_PROBE_IN152_WIDTH = "1" *)
(* C_PROBE_IN153_WIDTH = "1" *)
(* C_PROBE_IN154_WIDTH = "1" *)
(* C_PROBE_IN155_WIDTH = "1" *)
(* C_PROBE_IN156_WIDTH = "1" *)
(* C_PROBE_IN157_WIDTH = "1" *)
(* C_PROBE_IN158_WIDTH = "1" *)
(* C_PROBE_IN159_WIDTH = "1" *)
(* C_PROBE_IN15_WIDTH = "1" *)
(* C_PROBE_IN160_WIDTH = "1" *)
(* C_PROBE_IN161_WIDTH = "1" *)
(* C_PROBE_IN162_WIDTH = "1" *)
(* C_PROBE_IN163_WIDTH = "1" *)
(* C_PROBE_IN164_WIDTH = "1" *)
(* C_PROBE_IN165_WIDTH = "1" *)
(* C_PROBE_IN166_WIDTH = "1" *)
(* C_PROBE_IN167_WIDTH = "1" *)
(* C_PROBE_IN168_WIDTH = "1" *)
(* C_PROBE_IN169_WIDTH = "1" *)
(* C_PROBE_IN16_WIDTH = "1" *)
(* C_PROBE_IN170_WIDTH = "1" *)
(* C_PROBE_IN171_WIDTH = "1" *)
(* C_PROBE_IN172_WIDTH = "1" *)
(* C_PROBE_IN173_WIDTH = "1" *)
(* C_PROBE_IN174_WIDTH = "1" *)
(* C_PROBE_IN175_WIDTH = "1" *)
(* C_PROBE_IN176_WIDTH = "1" *)
(* C_PROBE_IN177_WIDTH = "1" *)
(* C_PROBE_IN178_WIDTH = "1" *)
(* C_PROBE_IN179_WIDTH = "1" *)
(* C_PROBE_IN17_WIDTH = "1" *)
(* C_PROBE_IN180_WIDTH = "1" *)
(* C_PROBE_IN181_WIDTH = "1" *)
(* C_PROBE_IN182_WIDTH = "1" *)
(* C_PROBE_IN183_WIDTH = "1" *)
(* C_PROBE_IN184_WIDTH = "1" *)
(* C_PROBE_IN185_WIDTH = "1" *)
(* C_PROBE_IN186_WIDTH = "1" *)
(* C_PROBE_IN187_WIDTH = "1" *)
(* C_PROBE_IN188_WIDTH = "1" *)
(* C_PROBE_IN189_WIDTH = "1" *)
(* C_PROBE_IN18_WIDTH = "1" *)
(* C_PROBE_IN190_WIDTH = "1" *)
(* C_PROBE_IN191_WIDTH = "1" *)
(* C_PROBE_IN192_WIDTH = "1" *)
(* C_PROBE_IN193_WIDTH = "1" *)
(* C_PROBE_IN194_WIDTH = "1" *)
(* C_PROBE_IN195_WIDTH = "1" *)
(* C_PROBE_IN196_WIDTH = "1" *)
(* C_PROBE_IN197_WIDTH = "1" *)
(* C_PROBE_IN198_WIDTH = "1" *)
(* C_PROBE_IN199_WIDTH = "1" *)
(* C_PROBE_IN19_WIDTH = "1" *)
(* C_PROBE_IN1_WIDTH = "1" *)
(* C_PROBE_IN200_WIDTH = "1" *)
(* C_PROBE_IN201_WIDTH = "1" *)
(* C_PROBE_IN202_WIDTH = "1" *)
(* C_PROBE_IN203_WIDTH = "1" *)
(* C_PROBE_IN204_WIDTH = "1" *)
(* C_PROBE_IN205_WIDTH = "1" *)
(* C_PROBE_IN206_WIDTH = "1" *)
(* C_PROBE_IN207_WIDTH = "1" *)
(* C_PROBE_IN208_WIDTH = "1" *)
(* C_PROBE_IN209_WIDTH = "1" *)
(* C_PROBE_IN20_WIDTH = "1" *)
(* C_PROBE_IN210_WIDTH = "1" *)
(* C_PROBE_IN211_WIDTH = "1" *)
(* C_PROBE_IN212_WIDTH = "1" *)
(* C_PROBE_IN213_WIDTH = "1" *)
(* C_PROBE_IN214_WIDTH = "1" *)
(* C_PROBE_IN215_WIDTH = "1" *)
(* C_PROBE_IN216_WIDTH = "1" *)
(* C_PROBE_IN217_WIDTH = "1" *)
(* C_PROBE_IN218_WIDTH = "1" *)
(* C_PROBE_IN219_WIDTH = "1" *)
(* C_PROBE_IN21_WIDTH = "1" *)
(* C_PROBE_IN220_WIDTH = "1" *)
(* C_PROBE_IN221_WIDTH = "1" *)
(* C_PROBE_IN222_WIDTH = "1" *)
(* C_PROBE_IN223_WIDTH = "1" *)
(* C_PROBE_IN224_WIDTH = "1" *)
(* C_PROBE_IN225_WIDTH = "1" *)
(* C_PROBE_IN226_WIDTH = "1" *)
(* C_PROBE_IN227_WIDTH = "1" *)
(* C_PROBE_IN228_WIDTH = "1" *)
(* C_PROBE_IN229_WIDTH = "1" *)
(* C_PROBE_IN22_WIDTH = "1" *)
(* C_PROBE_IN230_WIDTH = "1" *)
(* C_PROBE_IN231_WIDTH = "1" *)
(* C_PROBE_IN232_WIDTH = "1" *)
(* C_PROBE_IN233_WIDTH = "1" *)
(* C_PROBE_IN234_WIDTH = "1" *)
(* C_PROBE_IN235_WIDTH = "1" *)
(* C_PROBE_IN236_WIDTH = "1" *)
(* C_PROBE_IN237_WIDTH = "1" *)
(* C_PROBE_IN238_WIDTH = "1" *)
(* C_PROBE_IN239_WIDTH = "1" *)
(* C_PROBE_IN23_WIDTH = "1" *)
(* C_PROBE_IN240_WIDTH = "1" *)
(* C_PROBE_IN241_WIDTH = "1" *)
(* C_PROBE_IN242_WIDTH = "1" *)
(* C_PROBE_IN243_WIDTH = "1" *)
(* C_PROBE_IN244_WIDTH = "1" *)
(* C_PROBE_IN245_WIDTH = "1" *)
(* C_PROBE_IN246_WIDTH = "1" *)
(* C_PROBE_IN247_WIDTH = "1" *)
(* C_PROBE_IN248_WIDTH = "1" *)
(* C_PROBE_IN249_WIDTH = "1" *)
(* C_PROBE_IN24_WIDTH = "1" *)
(* C_PROBE_IN250_WIDTH = "1" *)
(* C_PROBE_IN251_WIDTH = "1" *)
(* C_PROBE_IN252_WIDTH = "1" *)
(* C_PROBE_IN253_WIDTH = "1" *)
(* C_PROBE_IN254_WIDTH = "1" *)
(* C_PROBE_IN255_WIDTH = "1" *)
(* C_PROBE_IN25_WIDTH = "1" *)
(* C_PROBE_IN26_WIDTH = "1" *)
(* C_PROBE_IN27_WIDTH = "1" *)
(* C_PROBE_IN28_WIDTH = "1" *)
(* C_PROBE_IN29_WIDTH = "1" *)
(* C_PROBE_IN2_WIDTH = "1" *)
(* C_PROBE_IN30_WIDTH = "1" *)
(* C_PROBE_IN31_WIDTH = "1" *)
(* C_PROBE_IN32_WIDTH = "1" *)
(* C_PROBE_IN33_WIDTH = "1" *)
(* C_PROBE_IN34_WIDTH = "1" *)
(* C_PROBE_IN35_WIDTH = "1" *)
(* C_PROBE_IN36_WIDTH = "1" *)
(* C_PROBE_IN37_WIDTH = "1" *)
(* C_PROBE_IN38_WIDTH = "1" *)
(* C_PROBE_IN39_WIDTH = "1" *)
(* C_PROBE_IN3_WIDTH = "1" *)
(* C_PROBE_IN40_WIDTH = "1" *)
(* C_PROBE_IN41_WIDTH = "1" *)
(* C_PROBE_IN42_WIDTH = "1" *)
(* C_PROBE_IN43_WIDTH = "1" *)
(* C_PROBE_IN44_WIDTH = "1" *)
(* C_PROBE_IN45_WIDTH = "1" *)
(* C_PROBE_IN46_WIDTH = "1" *)
(* C_PROBE_IN47_WIDTH = "1" *)
(* C_PROBE_IN48_WIDTH = "1" *)
(* C_PROBE_IN49_WIDTH = "1" *)
(* C_PROBE_IN4_WIDTH = "1" *)
(* C_PROBE_IN50_WIDTH = "1" *)
(* C_PROBE_IN51_WIDTH = "1" *)
(* C_PROBE_IN52_WIDTH = "1" *)
(* C_PROBE_IN53_WIDTH = "1" *)
(* C_PROBE_IN54_WIDTH = "1" *)
(* C_PROBE_IN55_WIDTH = "1" *)
(* C_PROBE_IN56_WIDTH = "1" *)
(* C_PROBE_IN57_WIDTH = "1" *)
(* C_PROBE_IN58_WIDTH = "1" *)
(* C_PROBE_IN59_WIDTH = "1" *)
(* C_PROBE_IN5_WIDTH = "1" *)
(* C_PROBE_IN60_WIDTH = "1" *)
(* C_PROBE_IN61_WIDTH = "1" *)
(* C_PROBE_IN62_WIDTH = "1" *)
(* C_PROBE_IN63_WIDTH = "1" *)
(* C_PROBE_IN64_WIDTH = "1" *)
(* C_PROBE_IN65_WIDTH = "1" *)
(* C_PROBE_IN66_WIDTH = "1" *)
(* C_PROBE_IN67_WIDTH = "1" *)
(* C_PROBE_IN68_WIDTH = "1" *)
(* C_PROBE_IN69_WIDTH = "1" *)
(* C_PROBE_IN6_WIDTH = "1" *)
(* C_PROBE_IN70_WIDTH = "1" *)
(* C_PROBE_IN71_WIDTH = "1" *)
(* C_PROBE_IN72_WIDTH = "1" *)
(* C_PROBE_IN73_WIDTH = "1" *)
(* C_PROBE_IN74_WIDTH = "1" *)
(* C_PROBE_IN75_WIDTH = "1" *)
(* C_PROBE_IN76_WIDTH = "1" *)
(* C_PROBE_IN77_WIDTH = "1" *)
(* C_PROBE_IN78_WIDTH = "1" *)
(* C_PROBE_IN79_WIDTH = "1" *)
(* C_PROBE_IN7_WIDTH = "1" *)
(* C_PROBE_IN80_WIDTH = "1" *)
(* C_PROBE_IN81_WIDTH = "1" *)
(* C_PROBE_IN82_WIDTH = "1" *)
(* C_PROBE_IN83_WIDTH = "1" *)
(* C_PROBE_IN84_WIDTH = "1" *)
(* C_PROBE_IN85_WIDTH = "1" *)
(* C_PROBE_IN86_WIDTH = "1" *)
(* C_PROBE_IN87_WIDTH = "1" *)
(* C_PROBE_IN88_WIDTH = "1" *)
(* C_PROBE_IN89_WIDTH = "1" *)
(* C_PROBE_IN8_WIDTH = "1" *)
(* C_PROBE_IN90_WIDTH = "1" *)
(* C_PROBE_IN91_WIDTH = "1" *)
(* C_PROBE_IN92_WIDTH = "1" *)
(* C_PROBE_IN93_WIDTH = "1" *)
(* C_PROBE_IN94_WIDTH = "1" *)
(* C_PROBE_IN95_WIDTH = "1" *)
(* C_PROBE_IN96_WIDTH = "1" *)
(* C_PROBE_IN97_WIDTH = "1" *)
(* C_PROBE_IN98_WIDTH = "1" *)
(* C_PROBE_IN99_WIDTH = "1" *)
(* C_PROBE_IN9_WIDTH = "1" *)
(* C_PROBE_OUT0_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT0_WIDTH = "1" *)
(* C_PROBE_OUT100_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT100_WIDTH = "1" *)
(* C_PROBE_OUT101_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT101_WIDTH = "1" *)
(* C_PROBE_OUT102_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT102_WIDTH = "1" *)
(* C_PROBE_OUT103_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT103_WIDTH = "1" *)
(* C_PROBE_OUT104_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT104_WIDTH = "1" *)
(* C_PROBE_OUT105_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT105_WIDTH = "1" *)
(* C_PROBE_OUT106_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT106_WIDTH = "1" *)
(* C_PROBE_OUT107_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT107_WIDTH = "1" *)
(* C_PROBE_OUT108_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT108_WIDTH = "1" *)
(* C_PROBE_OUT109_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT109_WIDTH = "1" *)
(* C_PROBE_OUT10_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT10_WIDTH = "1" *)
(* C_PROBE_OUT110_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT110_WIDTH = "1" *)
(* C_PROBE_OUT111_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT111_WIDTH = "1" *)
(* C_PROBE_OUT112_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT112_WIDTH = "1" *)
(* C_PROBE_OUT113_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT113_WIDTH = "1" *)
(* C_PROBE_OUT114_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT114_WIDTH = "1" *)
(* C_PROBE_OUT115_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT115_WIDTH = "1" *)
(* C_PROBE_OUT116_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT116_WIDTH = "1" *)
(* C_PROBE_OUT117_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT117_WIDTH = "1" *)
(* C_PROBE_OUT118_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT118_WIDTH = "1" *)
(* C_PROBE_OUT119_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT119_WIDTH = "1" *)
(* C_PROBE_OUT11_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT11_WIDTH = "1" *)
(* C_PROBE_OUT120_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT120_WIDTH = "1" *)
(* C_PROBE_OUT121_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT121_WIDTH = "1" *)
(* C_PROBE_OUT122_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT122_WIDTH = "1" *)
(* C_PROBE_OUT123_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT123_WIDTH = "1" *)
(* C_PROBE_OUT124_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT124_WIDTH = "1" *)
(* C_PROBE_OUT125_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT125_WIDTH = "1" *)
(* C_PROBE_OUT126_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT126_WIDTH = "1" *)
(* C_PROBE_OUT127_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT127_WIDTH = "1" *)
(* C_PROBE_OUT128_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT128_WIDTH = "1" *)
(* C_PROBE_OUT129_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT129_WIDTH = "1" *)
(* C_PROBE_OUT12_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT12_WIDTH = "1" *)
(* C_PROBE_OUT130_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT130_WIDTH = "1" *)
(* C_PROBE_OUT131_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT131_WIDTH = "1" *)
(* C_PROBE_OUT132_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT132_WIDTH = "1" *)
(* C_PROBE_OUT133_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT133_WIDTH = "1" *)
(* C_PROBE_OUT134_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT134_WIDTH = "1" *)
(* C_PROBE_OUT135_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT135_WIDTH = "1" *)
(* C_PROBE_OUT136_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT136_WIDTH = "1" *)
(* C_PROBE_OUT137_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT137_WIDTH = "1" *)
(* C_PROBE_OUT138_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT138_WIDTH = "1" *)
(* C_PROBE_OUT139_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT139_WIDTH = "1" *)
(* C_PROBE_OUT13_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT13_WIDTH = "1" *)
(* C_PROBE_OUT140_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT140_WIDTH = "1" *)
(* C_PROBE_OUT141_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT141_WIDTH = "1" *)
(* C_PROBE_OUT142_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT142_WIDTH = "1" *)
(* C_PROBE_OUT143_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT143_WIDTH = "1" *)
(* C_PROBE_OUT144_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT144_WIDTH = "1" *)
(* C_PROBE_OUT145_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT145_WIDTH = "1" *)
(* C_PROBE_OUT146_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT146_WIDTH = "1" *)
(* C_PROBE_OUT147_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT147_WIDTH = "1" *)
(* C_PROBE_OUT148_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT148_WIDTH = "1" *)
(* C_PROBE_OUT149_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT149_WIDTH = "1" *)
(* C_PROBE_OUT14_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT14_WIDTH = "1" *)
(* C_PROBE_OUT150_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT150_WIDTH = "1" *)
(* C_PROBE_OUT151_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT151_WIDTH = "1" *)
(* C_PROBE_OUT152_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT152_WIDTH = "1" *)
(* C_PROBE_OUT153_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT153_WIDTH = "1" *)
(* C_PROBE_OUT154_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT154_WIDTH = "1" *)
(* C_PROBE_OUT155_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT155_WIDTH = "1" *)
(* C_PROBE_OUT156_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT156_WIDTH = "1" *)
(* C_PROBE_OUT157_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT157_WIDTH = "1" *)
(* C_PROBE_OUT158_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT158_WIDTH = "1" *)
(* C_PROBE_OUT159_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT159_WIDTH = "1" *)
(* C_PROBE_OUT15_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT15_WIDTH = "1" *)
(* C_PROBE_OUT160_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT160_WIDTH = "1" *)
(* C_PROBE_OUT161_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT161_WIDTH = "1" *)
(* C_PROBE_OUT162_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT162_WIDTH = "1" *)
(* C_PROBE_OUT163_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT163_WIDTH = "1" *)
(* C_PROBE_OUT164_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT164_WIDTH = "1" *)
(* C_PROBE_OUT165_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT165_WIDTH = "1" *)
(* C_PROBE_OUT166_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT166_WIDTH = "1" *)
(* C_PROBE_OUT167_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT167_WIDTH = "1" *)
(* C_PROBE_OUT168_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT168_WIDTH = "1" *)
(* C_PROBE_OUT169_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT169_WIDTH = "1" *)
(* C_PROBE_OUT16_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT16_WIDTH = "1" *)
(* C_PROBE_OUT170_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT170_WIDTH = "1" *)
(* C_PROBE_OUT171_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT171_WIDTH = "1" *)
(* C_PROBE_OUT172_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT172_WIDTH = "1" *)
(* C_PROBE_OUT173_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT173_WIDTH = "1" *)
(* C_PROBE_OUT174_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT174_WIDTH = "1" *)
(* C_PROBE_OUT175_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT175_WIDTH = "1" *)
(* C_PROBE_OUT176_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT176_WIDTH = "1" *)
(* C_PROBE_OUT177_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT177_WIDTH = "1" *)
(* C_PROBE_OUT178_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT178_WIDTH = "1" *)
(* C_PROBE_OUT179_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT179_WIDTH = "1" *)
(* C_PROBE_OUT17_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT17_WIDTH = "1" *)
(* C_PROBE_OUT180_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT180_WIDTH = "1" *)
(* C_PROBE_OUT181_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT181_WIDTH = "1" *)
(* C_PROBE_OUT182_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT182_WIDTH = "1" *)
(* C_PROBE_OUT183_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT183_WIDTH = "1" *)
(* C_PROBE_OUT184_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT184_WIDTH = "1" *)
(* C_PROBE_OUT185_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT185_WIDTH = "1" *)
(* C_PROBE_OUT186_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT186_WIDTH = "1" *)
(* C_PROBE_OUT187_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT187_WIDTH = "1" *)
(* C_PROBE_OUT188_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT188_WIDTH = "1" *)
(* C_PROBE_OUT189_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT189_WIDTH = "1" *)
(* C_PROBE_OUT18_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT18_WIDTH = "1" *)
(* C_PROBE_OUT190_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT190_WIDTH = "1" *)
(* C_PROBE_OUT191_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT191_WIDTH = "1" *)
(* C_PROBE_OUT192_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT192_WIDTH = "1" *)
(* C_PROBE_OUT193_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT193_WIDTH = "1" *)
(* C_PROBE_OUT194_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT194_WIDTH = "1" *)
(* C_PROBE_OUT195_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT195_WIDTH = "1" *)
(* C_PROBE_OUT196_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT196_WIDTH = "1" *)
(* C_PROBE_OUT197_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT197_WIDTH = "1" *)
(* C_PROBE_OUT198_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT198_WIDTH = "1" *)
(* C_PROBE_OUT199_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT199_WIDTH = "1" *)
(* C_PROBE_OUT19_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT19_WIDTH = "1" *)
(* C_PROBE_OUT1_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT1_WIDTH = "1" *)
(* C_PROBE_OUT200_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT200_WIDTH = "1" *)
(* C_PROBE_OUT201_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT201_WIDTH = "1" *)
(* C_PROBE_OUT202_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT202_WIDTH = "1" *)
(* C_PROBE_OUT203_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT203_WIDTH = "1" *)
(* C_PROBE_OUT204_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT204_WIDTH = "1" *)
(* C_PROBE_OUT205_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT205_WIDTH = "1" *)
(* C_PROBE_OUT206_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT206_WIDTH = "1" *)
(* C_PROBE_OUT207_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT207_WIDTH = "1" *)
(* C_PROBE_OUT208_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT208_WIDTH = "1" *)
(* C_PROBE_OUT209_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT209_WIDTH = "1" *)
(* C_PROBE_OUT20_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT20_WIDTH = "1" *)
(* C_PROBE_OUT210_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT210_WIDTH = "1" *)
(* C_PROBE_OUT211_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT211_WIDTH = "1" *)
(* C_PROBE_OUT212_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT212_WIDTH = "1" *)
(* C_PROBE_OUT213_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT213_WIDTH = "1" *)
(* C_PROBE_OUT214_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT214_WIDTH = "1" *)
(* C_PROBE_OUT215_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT215_WIDTH = "1" *)
(* C_PROBE_OUT216_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT216_WIDTH = "1" *)
(* C_PROBE_OUT217_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT217_WIDTH = "1" *)
(* C_PROBE_OUT218_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT218_WIDTH = "1" *)
(* C_PROBE_OUT219_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT219_WIDTH = "1" *)
(* C_PROBE_OUT21_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT21_WIDTH = "1" *)
(* C_PROBE_OUT220_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT220_WIDTH = "1" *)
(* C_PROBE_OUT221_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT221_WIDTH = "1" *)
(* C_PROBE_OUT222_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT222_WIDTH = "1" *)
(* C_PROBE_OUT223_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT223_WIDTH = "1" *)
(* C_PROBE_OUT224_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT224_WIDTH = "1" *)
(* C_PROBE_OUT225_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT225_WIDTH = "1" *)
(* C_PROBE_OUT226_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT226_WIDTH = "1" *)
(* C_PROBE_OUT227_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT227_WIDTH = "1" *)
(* C_PROBE_OUT228_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT228_WIDTH = "1" *)
(* C_PROBE_OUT229_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT229_WIDTH = "1" *)
(* C_PROBE_OUT22_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT22_WIDTH = "1" *)
(* C_PROBE_OUT230_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT230_WIDTH = "1" *)
(* C_PROBE_OUT231_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT231_WIDTH = "1" *)
(* C_PROBE_OUT232_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT232_WIDTH = "1" *)
(* C_PROBE_OUT233_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT233_WIDTH = "1" *)
(* C_PROBE_OUT234_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT234_WIDTH = "1" *)
(* C_PROBE_OUT235_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT235_WIDTH = "1" *)
(* C_PROBE_OUT236_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT236_WIDTH = "1" *)
(* C_PROBE_OUT237_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT237_WIDTH = "1" *)
(* C_PROBE_OUT238_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT238_WIDTH = "1" *)
(* C_PROBE_OUT239_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT239_WIDTH = "1" *)
(* C_PROBE_OUT23_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT23_WIDTH = "1" *)
(* C_PROBE_OUT240_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT240_WIDTH = "1" *)
(* C_PROBE_OUT241_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT241_WIDTH = "1" *)
(* C_PROBE_OUT242_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT242_WIDTH = "1" *)
(* C_PROBE_OUT243_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT243_WIDTH = "1" *)
(* C_PROBE_OUT244_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT244_WIDTH = "1" *)
(* C_PROBE_OUT245_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT245_WIDTH = "1" *)
(* C_PROBE_OUT246_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT246_WIDTH = "1" *)
(* C_PROBE_OUT247_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT247_WIDTH = "1" *)
(* C_PROBE_OUT248_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT248_WIDTH = "1" *)
(* C_PROBE_OUT249_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT249_WIDTH = "1" *)
(* C_PROBE_OUT24_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT24_WIDTH = "1" *)
(* C_PROBE_OUT250_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT250_WIDTH = "1" *)
(* C_PROBE_OUT251_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT251_WIDTH = "1" *)
(* C_PROBE_OUT252_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT252_WIDTH = "1" *)
(* C_PROBE_OUT253_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT253_WIDTH = "1" *)
(* C_PROBE_OUT254_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT254_WIDTH = "1" *)
(* C_PROBE_OUT255_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT255_WIDTH = "1" *)
(* C_PROBE_OUT25_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT25_WIDTH = "1" *)
(* C_PROBE_OUT26_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT26_WIDTH = "1" *)
(* C_PROBE_OUT27_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT27_WIDTH = "1" *)
(* C_PROBE_OUT28_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT28_WIDTH = "1" *)
(* C_PROBE_OUT29_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT29_WIDTH = "1" *)
(* C_PROBE_OUT2_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT2_WIDTH = "1" *)
(* C_PROBE_OUT30_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT30_WIDTH = "1" *)
(* C_PROBE_OUT31_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT31_WIDTH = "1" *)
(* C_PROBE_OUT32_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT32_WIDTH = "1" *)
(* C_PROBE_OUT33_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT33_WIDTH = "1" *)
(* C_PROBE_OUT34_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT34_WIDTH = "1" *)
(* C_PROBE_OUT35_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT35_WIDTH = "1" *)
(* C_PROBE_OUT36_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT36_WIDTH = "1" *)
(* C_PROBE_OUT37_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT37_WIDTH = "1" *)
(* C_PROBE_OUT38_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT38_WIDTH = "1" *)
(* C_PROBE_OUT39_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT39_WIDTH = "1" *)
(* C_PROBE_OUT3_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT3_WIDTH = "1" *)
(* C_PROBE_OUT40_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT40_WIDTH = "1" *)
(* C_PROBE_OUT41_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT41_WIDTH = "1" *)
(* C_PROBE_OUT42_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT42_WIDTH = "1" *)
(* C_PROBE_OUT43_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT43_WIDTH = "1" *)
(* C_PROBE_OUT44_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT44_WIDTH = "1" *)
(* C_PROBE_OUT45_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT45_WIDTH = "1" *)
(* C_PROBE_OUT46_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT46_WIDTH = "1" *)
(* C_PROBE_OUT47_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT47_WIDTH = "1" *)
(* C_PROBE_OUT48_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT48_WIDTH = "1" *)
(* C_PROBE_OUT49_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT49_WIDTH = "1" *)
(* C_PROBE_OUT4_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT4_WIDTH = "1" *)
(* C_PROBE_OUT50_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT50_WIDTH = "1" *)
(* C_PROBE_OUT51_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT51_WIDTH = "1" *)
(* C_PROBE_OUT52_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT52_WIDTH = "1" *)
(* C_PROBE_OUT53_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT53_WIDTH = "1" *)
(* C_PROBE_OUT54_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT54_WIDTH = "1" *)
(* C_PROBE_OUT55_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT55_WIDTH = "1" *)
(* C_PROBE_OUT56_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT56_WIDTH = "1" *)
(* C_PROBE_OUT57_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT57_WIDTH = "1" *)
(* C_PROBE_OUT58_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT58_WIDTH = "1" *)
(* C_PROBE_OUT59_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT59_WIDTH = "1" *)
(* C_PROBE_OUT5_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT5_WIDTH = "1" *)
(* C_PROBE_OUT60_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT60_WIDTH = "1" *)
(* C_PROBE_OUT61_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT61_WIDTH = "1" *)
(* C_PROBE_OUT62_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT62_WIDTH = "1" *)
(* C_PROBE_OUT63_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT63_WIDTH = "1" *)
(* C_PROBE_OUT64_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT64_WIDTH = "1" *)
(* C_PROBE_OUT65_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT65_WIDTH = "1" *)
(* C_PROBE_OUT66_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT66_WIDTH = "1" *)
(* C_PROBE_OUT67_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT67_WIDTH = "1" *)
(* C_PROBE_OUT68_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT68_WIDTH = "1" *)
(* C_PROBE_OUT69_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT69_WIDTH = "1" *)
(* C_PROBE_OUT6_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT6_WIDTH = "1" *)
(* C_PROBE_OUT70_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT70_WIDTH = "1" *)
(* C_PROBE_OUT71_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT71_WIDTH = "1" *)
(* C_PROBE_OUT72_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT72_WIDTH = "1" *)
(* C_PROBE_OUT73_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT73_WIDTH = "1" *)
(* C_PROBE_OUT74_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT74_WIDTH = "1" *)
(* C_PROBE_OUT75_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT75_WIDTH = "1" *)
(* C_PROBE_OUT76_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT76_WIDTH = "1" *)
(* C_PROBE_OUT77_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT77_WIDTH = "1" *)
(* C_PROBE_OUT78_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT78_WIDTH = "1" *)
(* C_PROBE_OUT79_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT79_WIDTH = "1" *)
(* C_PROBE_OUT7_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT7_WIDTH = "1" *)
(* C_PROBE_OUT80_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT80_WIDTH = "1" *)
(* C_PROBE_OUT81_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT81_WIDTH = "1" *)
(* C_PROBE_OUT82_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT82_WIDTH = "1" *)
(* C_PROBE_OUT83_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT83_WIDTH = "1" *)
(* C_PROBE_OUT84_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT84_WIDTH = "1" *)
(* C_PROBE_OUT85_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT85_WIDTH = "1" *)
(* C_PROBE_OUT86_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT86_WIDTH = "1" *)
(* C_PROBE_OUT87_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT87_WIDTH = "1" *)
(* C_PROBE_OUT88_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT88_WIDTH = "1" *)
(* C_PROBE_OUT89_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT89_WIDTH = "1" *)
(* C_PROBE_OUT8_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT8_WIDTH = "1" *)
(* C_PROBE_OUT90_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT90_WIDTH = "1" *)
(* C_PROBE_OUT91_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT91_WIDTH = "1" *)
(* C_PROBE_OUT92_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT92_WIDTH = "1" *)
(* C_PROBE_OUT93_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT93_WIDTH = "1" *)
(* C_PROBE_OUT94_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT94_WIDTH = "1" *)
(* C_PROBE_OUT95_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT95_WIDTH = "1" *)
(* C_PROBE_OUT96_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT96_WIDTH = "1" *)
(* C_PROBE_OUT97_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT97_WIDTH = "1" *)
(* C_PROBE_OUT98_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT98_WIDTH = "1" *)
(* C_PROBE_OUT99_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT99_WIDTH = "1" *)
(* C_PROBE_OUT9_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT9_WIDTH = "1" *)
(* C_USE_TEST_REG = "1" *)
(* C_XDEVICEFAMILY = "kintex7" *)
(* C_XLNX_HW_PROBE_INFO = "DEFAULT" *)
(* C_XSDB_SLAVE_TYPE = "33" *)
(* DONT_TOUCH *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
(* LC_HIGH_BIT_POS_PROBE_OUT0 = "16'b0000000000000000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT1 = "16'b0000000000000001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT10 = "16'b0000000000001010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT100 = "16'b0000000001100100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT101 = "16'b0000000001100101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT102 = "16'b0000000001100110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT103 = "16'b0000000001100111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT104 = "16'b0000000001101000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT105 = "16'b0000000001101001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT106 = "16'b0000000001101010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT107 = "16'b0000000001101011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT108 = "16'b0000000001101100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT109 = "16'b0000000001101101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT11 = "16'b0000000000001011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT110 = "16'b0000000001101110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT111 = "16'b0000000001101111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT112 = "16'b0000000001110000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT113 = "16'b0000000001110001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT114 = "16'b0000000001110010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT115 = "16'b0000000001110011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT116 = "16'b0000000001110100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT117 = "16'b0000000001110101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT118 = "16'b0000000001110110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT119 = "16'b0000000001110111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT12 = "16'b0000000000001100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT120 = "16'b0000000001111000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT121 = "16'b0000000001111001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT122 = "16'b0000000001111010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT123 = "16'b0000000001111011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT124 = "16'b0000000001111100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT125 = "16'b0000000001111101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT126 = "16'b0000000001111110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT127 = "16'b0000000001111111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT128 = "16'b0000000010000000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT129 = "16'b0000000010000001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT13 = "16'b0000000000001101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT130 = "16'b0000000010000010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT131 = "16'b0000000010000011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT132 = "16'b0000000010000100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT133 = "16'b0000000010000101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT134 = "16'b0000000010000110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT135 = "16'b0000000010000111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT136 = "16'b0000000010001000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT137 = "16'b0000000010001001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT138 = "16'b0000000010001010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT139 = "16'b0000000010001011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT14 = "16'b0000000000001110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT140 = "16'b0000000010001100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT141 = "16'b0000000010001101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT142 = "16'b0000000010001110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT143 = "16'b0000000010001111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT144 = "16'b0000000010010000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT145 = "16'b0000000010010001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT146 = "16'b0000000010010010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT147 = "16'b0000000010010011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT148 = "16'b0000000010010100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT149 = "16'b0000000010010101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT15 = "16'b0000000000001111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT150 = "16'b0000000010010110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT151 = "16'b0000000010010111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT152 = "16'b0000000010011000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT153 = "16'b0000000010011001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT154 = "16'b0000000010011010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT155 = "16'b0000000010011011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT156 = "16'b0000000010011100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT157 = "16'b0000000010011101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT158 = "16'b0000000010011110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT159 = "16'b0000000010011111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT16 = "16'b0000000000010000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT160 = "16'b0000000010100000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT161 = "16'b0000000010100001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT162 = "16'b0000000010100010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT163 = "16'b0000000010100011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT164 = "16'b0000000010100100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT165 = "16'b0000000010100101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT166 = "16'b0000000010100110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT167 = "16'b0000000010100111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT168 = "16'b0000000010101000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT169 = "16'b0000000010101001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT17 = "16'b0000000000010001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT170 = "16'b0000000010101010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT171 = "16'b0000000010101011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT172 = "16'b0000000010101100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT173 = "16'b0000000010101101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT174 = "16'b0000000010101110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT175 = "16'b0000000010101111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT176 = "16'b0000000010110000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT177 = "16'b0000000010110001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT178 = "16'b0000000010110010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT179 = "16'b0000000010110011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT18 = "16'b0000000000010010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT180 = "16'b0000000010110100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT181 = "16'b0000000010110101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT182 = "16'b0000000010110110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT183 = "16'b0000000010110111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT184 = "16'b0000000010111000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT185 = "16'b0000000010111001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT186 = "16'b0000000010111010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT187 = "16'b0000000010111011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT188 = "16'b0000000010111100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT189 = "16'b0000000010111101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT19 = "16'b0000000000010011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT190 = "16'b0000000010111110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT191 = "16'b0000000010111111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT192 = "16'b0000000011000000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT193 = "16'b0000000011000001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT194 = "16'b0000000011000010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT195 = "16'b0000000011000011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT196 = "16'b0000000011000100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT197 = "16'b0000000011000101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT198 = "16'b0000000011000110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT199 = "16'b0000000011000111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT2 = "16'b0000000000000010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT20 = "16'b0000000000010100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT200 = "16'b0000000011001000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT201 = "16'b0000000011001001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT202 = "16'b0000000011001010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT203 = "16'b0000000011001011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT204 = "16'b0000000011001100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT205 = "16'b0000000011001101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT206 = "16'b0000000011001110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT207 = "16'b0000000011001111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT208 = "16'b0000000011010000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT209 = "16'b0000000011010001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT21 = "16'b0000000000010101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT210 = "16'b0000000011010010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT211 = "16'b0000000011010011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT212 = "16'b0000000011010100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT213 = "16'b0000000011010101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT214 = "16'b0000000011010110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT215 = "16'b0000000011010111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT216 = "16'b0000000011011000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT217 = "16'b0000000011011001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT218 = "16'b0000000011011010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT219 = "16'b0000000011011011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT22 = "16'b0000000000010110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT220 = "16'b0000000011011100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT221 = "16'b0000000011011101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT222 = "16'b0000000011011110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT223 = "16'b0000000011011111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT224 = "16'b0000000011100000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT225 = "16'b0000000011100001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT226 = "16'b0000000011100010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT227 = "16'b0000000011100011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT228 = "16'b0000000011100100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT229 = "16'b0000000011100101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT23 = "16'b0000000000010111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT230 = "16'b0000000011100110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT231 = "16'b0000000011100111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT232 = "16'b0000000011101000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT233 = "16'b0000000011101001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT234 = "16'b0000000011101010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT235 = "16'b0000000011101011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT236 = "16'b0000000011101100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT237 = "16'b0000000011101101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT238 = "16'b0000000011101110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT239 = "16'b0000000011101111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT24 = "16'b0000000000011000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT240 = "16'b0000000011110000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT241 = "16'b0000000011110001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT242 = "16'b0000000011110010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT243 = "16'b0000000011110011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT244 = "16'b0000000011110100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT245 = "16'b0000000011110101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT246 = "16'b0000000011110110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT247 = "16'b0000000011110111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT248 = "16'b0000000011111000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT249 = "16'b0000000011111001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT25 = "16'b0000000000011001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT250 = "16'b0000000011111010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT251 = "16'b0000000011111011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT252 = "16'b0000000011111100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT253 = "16'b0000000011111101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT254 = "16'b0000000011111110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT255 = "16'b0000000011111111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT26 = "16'b0000000000011010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT27 = "16'b0000000000011011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT28 = "16'b0000000000011100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT29 = "16'b0000000000011101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT3 = "16'b0000000000000011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT30 = "16'b0000000000011110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT31 = "16'b0000000000011111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT32 = "16'b0000000000100000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT33 = "16'b0000000000100001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT34 = "16'b0000000000100010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT35 = "16'b0000000000100011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT36 = "16'b0000000000100100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT37 = "16'b0000000000100101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT38 = "16'b0000000000100110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT39 = "16'b0000000000100111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT4 = "16'b0000000000000100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT40 = "16'b0000000000101000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT41 = "16'b0000000000101001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT42 = "16'b0000000000101010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT43 = "16'b0000000000101011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT44 = "16'b0000000000101100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT45 = "16'b0000000000101101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT46 = "16'b0000000000101110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT47 = "16'b0000000000101111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT48 = "16'b0000000000110000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT49 = "16'b0000000000110001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT5 = "16'b0000000000000101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT50 = "16'b0000000000110010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT51 = "16'b0000000000110011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT52 = "16'b0000000000110100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT53 = "16'b0000000000110101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT54 = "16'b0000000000110110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT55 = "16'b0000000000110111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT56 = "16'b0000000000111000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT57 = "16'b0000000000111001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT58 = "16'b0000000000111010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT59 = "16'b0000000000111011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT6 = "16'b0000000000000110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT60 = "16'b0000000000111100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT61 = "16'b0000000000111101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT62 = "16'b0000000000111110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT63 = "16'b0000000000111111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT64 = "16'b0000000001000000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT65 = "16'b0000000001000001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT66 = "16'b0000000001000010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT67 = "16'b0000000001000011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT68 = "16'b0000000001000100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT69 = "16'b0000000001000101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT7 = "16'b0000000000000111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT70 = "16'b0000000001000110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT71 = "16'b0000000001000111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT72 = "16'b0000000001001000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT73 = "16'b0000000001001001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT74 = "16'b0000000001001010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT75 = "16'b0000000001001011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT76 = "16'b0000000001001100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT77 = "16'b0000000001001101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT78 = "16'b0000000001001110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT79 = "16'b0000000001001111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT8 = "16'b0000000000001000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT80 = "16'b0000000001010000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT81 = "16'b0000000001010001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT82 = "16'b0000000001010010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT83 = "16'b0000000001010011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT84 = "16'b0000000001010100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT85 = "16'b0000000001010101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT86 = "16'b0000000001010110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT87 = "16'b0000000001010111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT88 = "16'b0000000001011000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT89 = "16'b0000000001011001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT9 = "16'b0000000000001001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT90 = "16'b0000000001011010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT91 = "16'b0000000001011011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT92 = "16'b0000000001011100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT93 = "16'b0000000001011101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT94 = "16'b0000000001011110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT95 = "16'b0000000001011111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT96 = "16'b0000000001100000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT97 = "16'b0000000001100001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT98 = "16'b0000000001100010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT99 = "16'b0000000001100011" *)
(* LC_LOW_BIT_POS_PROBE_OUT0 = "16'b0000000000000000" *)
(* LC_LOW_BIT_POS_PROBE_OUT1 = "16'b0000000000000001" *)
(* LC_LOW_BIT_POS_PROBE_OUT10 = "16'b0000000000001010" *)
(* LC_LOW_BIT_POS_PROBE_OUT100 = "16'b0000000001100100" *)
(* LC_LOW_BIT_POS_PROBE_OUT101 = "16'b0000000001100101" *)
(* LC_LOW_BIT_POS_PROBE_OUT102 = "16'b0000000001100110" *)
(* LC_LOW_BIT_POS_PROBE_OUT103 = "16'b0000000001100111" *)
(* LC_LOW_BIT_POS_PROBE_OUT104 = "16'b0000000001101000" *)
(* LC_LOW_BIT_POS_PROBE_OUT105 = "16'b0000000001101001" *)
(* LC_LOW_BIT_POS_PROBE_OUT106 = "16'b0000000001101010" *)
(* LC_LOW_BIT_POS_PROBE_OUT107 = "16'b0000000001101011" *)
(* LC_LOW_BIT_POS_PROBE_OUT108 = "16'b0000000001101100" *)
(* LC_LOW_BIT_POS_PROBE_OUT109 = "16'b0000000001101101" *)
(* LC_LOW_BIT_POS_PROBE_OUT11 = "16'b0000000000001011" *)
(* LC_LOW_BIT_POS_PROBE_OUT110 = "16'b0000000001101110" *)
(* LC_LOW_BIT_POS_PROBE_OUT111 = "16'b0000000001101111" *)
(* LC_LOW_BIT_POS_PROBE_OUT112 = "16'b0000000001110000" *)
(* LC_LOW_BIT_POS_PROBE_OUT113 = "16'b0000000001110001" *)
(* LC_LOW_BIT_POS_PROBE_OUT114 = "16'b0000000001110010" *)
(* LC_LOW_BIT_POS_PROBE_OUT115 = "16'b0000000001110011" *)
(* LC_LOW_BIT_POS_PROBE_OUT116 = "16'b0000000001110100" *)
(* LC_LOW_BIT_POS_PROBE_OUT117 = "16'b0000000001110101" *)
(* LC_LOW_BIT_POS_PROBE_OUT118 = "16'b0000000001110110" *)
(* LC_LOW_BIT_POS_PROBE_OUT119 = "16'b0000000001110111" *)
(* LC_LOW_BIT_POS_PROBE_OUT12 = "16'b0000000000001100" *)
(* LC_LOW_BIT_POS_PROBE_OUT120 = "16'b0000000001111000" *)
(* LC_LOW_BIT_POS_PROBE_OUT121 = "16'b0000000001111001" *)
(* LC_LOW_BIT_POS_PROBE_OUT122 = "16'b0000000001111010" *)
(* LC_LOW_BIT_POS_PROBE_OUT123 = "16'b0000000001111011" *)
(* LC_LOW_BIT_POS_PROBE_OUT124 = "16'b0000000001111100" *)
(* LC_LOW_BIT_POS_PROBE_OUT125 = "16'b0000000001111101" *)
(* LC_LOW_BIT_POS_PROBE_OUT126 = "16'b0000000001111110" *)
(* LC_LOW_BIT_POS_PROBE_OUT127 = "16'b0000000001111111" *)
(* LC_LOW_BIT_POS_PROBE_OUT128 = "16'b0000000010000000" *)
(* LC_LOW_BIT_POS_PROBE_OUT129 = "16'b0000000010000001" *)
(* LC_LOW_BIT_POS_PROBE_OUT13 = "16'b0000000000001101" *)
(* LC_LOW_BIT_POS_PROBE_OUT130 = "16'b0000000010000010" *)
(* LC_LOW_BIT_POS_PROBE_OUT131 = "16'b0000000010000011" *)
(* LC_LOW_BIT_POS_PROBE_OUT132 = "16'b0000000010000100" *)
(* LC_LOW_BIT_POS_PROBE_OUT133 = "16'b0000000010000101" *)
(* LC_LOW_BIT_POS_PROBE_OUT134 = "16'b0000000010000110" *)
(* LC_LOW_BIT_POS_PROBE_OUT135 = "16'b0000000010000111" *)
(* LC_LOW_BIT_POS_PROBE_OUT136 = "16'b0000000010001000" *)
(* LC_LOW_BIT_POS_PROBE_OUT137 = "16'b0000000010001001" *)
(* LC_LOW_BIT_POS_PROBE_OUT138 = "16'b0000000010001010" *)
(* LC_LOW_BIT_POS_PROBE_OUT139 = "16'b0000000010001011" *)
(* LC_LOW_BIT_POS_PROBE_OUT14 = "16'b0000000000001110" *)
(* LC_LOW_BIT_POS_PROBE_OUT140 = "16'b0000000010001100" *)
(* LC_LOW_BIT_POS_PROBE_OUT141 = "16'b0000000010001101" *)
(* LC_LOW_BIT_POS_PROBE_OUT142 = "16'b0000000010001110" *)
(* LC_LOW_BIT_POS_PROBE_OUT143 = "16'b0000000010001111" *)
(* LC_LOW_BIT_POS_PROBE_OUT144 = "16'b0000000010010000" *)
(* LC_LOW_BIT_POS_PROBE_OUT145 = "16'b0000000010010001" *)
(* LC_LOW_BIT_POS_PROBE_OUT146 = "16'b0000000010010010" *)
(* LC_LOW_BIT_POS_PROBE_OUT147 = "16'b0000000010010011" *)
(* LC_LOW_BIT_POS_PROBE_OUT148 = "16'b0000000010010100" *)
(* LC_LOW_BIT_POS_PROBE_OUT149 = "16'b0000000010010101" *)
(* LC_LOW_BIT_POS_PROBE_OUT15 = "16'b0000000000001111" *)
(* LC_LOW_BIT_POS_PROBE_OUT150 = "16'b0000000010010110" *)
(* LC_LOW_BIT_POS_PROBE_OUT151 = "16'b0000000010010111" *)
(* LC_LOW_BIT_POS_PROBE_OUT152 = "16'b0000000010011000" *)
(* LC_LOW_BIT_POS_PROBE_OUT153 = "16'b0000000010011001" *)
(* LC_LOW_BIT_POS_PROBE_OUT154 = "16'b0000000010011010" *)
(* LC_LOW_BIT_POS_PROBE_OUT155 = "16'b0000000010011011" *)
(* LC_LOW_BIT_POS_PROBE_OUT156 = "16'b0000000010011100" *)
(* LC_LOW_BIT_POS_PROBE_OUT157 = "16'b0000000010011101" *)
(* LC_LOW_BIT_POS_PROBE_OUT158 = "16'b0000000010011110" *)
(* LC_LOW_BIT_POS_PROBE_OUT159 = "16'b0000000010011111" *)
(* LC_LOW_BIT_POS_PROBE_OUT16 = "16'b0000000000010000" *)
(* LC_LOW_BIT_POS_PROBE_OUT160 = "16'b0000000010100000" *)
(* LC_LOW_BIT_POS_PROBE_OUT161 = "16'b0000000010100001" *)
(* LC_LOW_BIT_POS_PROBE_OUT162 = "16'b0000000010100010" *)
(* LC_LOW_BIT_POS_PROBE_OUT163 = "16'b0000000010100011" *)
(* LC_LOW_BIT_POS_PROBE_OUT164 = "16'b0000000010100100" *)
(* LC_LOW_BIT_POS_PROBE_OUT165 = "16'b0000000010100101" *)
(* LC_LOW_BIT_POS_PROBE_OUT166 = "16'b0000000010100110" *)
(* LC_LOW_BIT_POS_PROBE_OUT167 = "16'b0000000010100111" *)
(* LC_LOW_BIT_POS_PROBE_OUT168 = "16'b0000000010101000" *)
(* LC_LOW_BIT_POS_PROBE_OUT169 = "16'b0000000010101001" *)
(* LC_LOW_BIT_POS_PROBE_OUT17 = "16'b0000000000010001" *)
(* LC_LOW_BIT_POS_PROBE_OUT170 = "16'b0000000010101010" *)
(* LC_LOW_BIT_POS_PROBE_OUT171 = "16'b0000000010101011" *)
(* LC_LOW_BIT_POS_PROBE_OUT172 = "16'b0000000010101100" *)
(* LC_LOW_BIT_POS_PROBE_OUT173 = "16'b0000000010101101" *)
(* LC_LOW_BIT_POS_PROBE_OUT174 = "16'b0000000010101110" *)
(* LC_LOW_BIT_POS_PROBE_OUT175 = "16'b0000000010101111" *)
(* LC_LOW_BIT_POS_PROBE_OUT176 = "16'b0000000010110000" *)
(* LC_LOW_BIT_POS_PROBE_OUT177 = "16'b0000000010110001" *)
(* LC_LOW_BIT_POS_PROBE_OUT178 = "16'b0000000010110010" *)
(* LC_LOW_BIT_POS_PROBE_OUT179 = "16'b0000000010110011" *)
(* LC_LOW_BIT_POS_PROBE_OUT18 = "16'b0000000000010010" *)
(* LC_LOW_BIT_POS_PROBE_OUT180 = "16'b0000000010110100" *)
(* LC_LOW_BIT_POS_PROBE_OUT181 = "16'b0000000010110101" *)
(* LC_LOW_BIT_POS_PROBE_OUT182 = "16'b0000000010110110" *)
(* LC_LOW_BIT_POS_PROBE_OUT183 = "16'b0000000010110111" *)
(* LC_LOW_BIT_POS_PROBE_OUT184 = "16'b0000000010111000" *)
(* LC_LOW_BIT_POS_PROBE_OUT185 = "16'b0000000010111001" *)
(* LC_LOW_BIT_POS_PROBE_OUT186 = "16'b0000000010111010" *)
(* LC_LOW_BIT_POS_PROBE_OUT187 = "16'b0000000010111011" *)
(* LC_LOW_BIT_POS_PROBE_OUT188 = "16'b0000000010111100" *)
(* LC_LOW_BIT_POS_PROBE_OUT189 = "16'b0000000010111101" *)
(* LC_LOW_BIT_POS_PROBE_OUT19 = "16'b0000000000010011" *)
(* LC_LOW_BIT_POS_PROBE_OUT190 = "16'b0000000010111110" *)
(* LC_LOW_BIT_POS_PROBE_OUT191 = "16'b0000000010111111" *)
(* LC_LOW_BIT_POS_PROBE_OUT192 = "16'b0000000011000000" *)
(* LC_LOW_BIT_POS_PROBE_OUT193 = "16'b0000000011000001" *)
(* LC_LOW_BIT_POS_PROBE_OUT194 = "16'b0000000011000010" *)
(* LC_LOW_BIT_POS_PROBE_OUT195 = "16'b0000000011000011" *)
(* LC_LOW_BIT_POS_PROBE_OUT196 = "16'b0000000011000100" *)
(* LC_LOW_BIT_POS_PROBE_OUT197 = "16'b0000000011000101" *)
(* LC_LOW_BIT_POS_PROBE_OUT198 = "16'b0000000011000110" *)
(* LC_LOW_BIT_POS_PROBE_OUT199 = "16'b0000000011000111" *)
(* LC_LOW_BIT_POS_PROBE_OUT2 = "16'b0000000000000010" *)
(* LC_LOW_BIT_POS_PROBE_OUT20 = "16'b0000000000010100" *)
(* LC_LOW_BIT_POS_PROBE_OUT200 = "16'b0000000011001000" *)
(* LC_LOW_BIT_POS_PROBE_OUT201 = "16'b0000000011001001" *)
(* LC_LOW_BIT_POS_PROBE_OUT202 = "16'b0000000011001010" *)
(* LC_LOW_BIT_POS_PROBE_OUT203 = "16'b0000000011001011" *)
(* LC_LOW_BIT_POS_PROBE_OUT204 = "16'b0000000011001100" *)
(* LC_LOW_BIT_POS_PROBE_OUT205 = "16'b0000000011001101" *)
(* LC_LOW_BIT_POS_PROBE_OUT206 = "16'b0000000011001110" *)
(* LC_LOW_BIT_POS_PROBE_OUT207 = "16'b0000000011001111" *)
(* LC_LOW_BIT_POS_PROBE_OUT208 = "16'b0000000011010000" *)
(* LC_LOW_BIT_POS_PROBE_OUT209 = "16'b0000000011010001" *)
(* LC_LOW_BIT_POS_PROBE_OUT21 = "16'b0000000000010101" *)
(* LC_LOW_BIT_POS_PROBE_OUT210 = "16'b0000000011010010" *)
(* LC_LOW_BIT_POS_PROBE_OUT211 = "16'b0000000011010011" *)
(* LC_LOW_BIT_POS_PROBE_OUT212 = "16'b0000000011010100" *)
(* LC_LOW_BIT_POS_PROBE_OUT213 = "16'b0000000011010101" *)
(* LC_LOW_BIT_POS_PROBE_OUT214 = "16'b0000000011010110" *)
(* LC_LOW_BIT_POS_PROBE_OUT215 = "16'b0000000011010111" *)
(* LC_LOW_BIT_POS_PROBE_OUT216 = "16'b0000000011011000" *)
(* LC_LOW_BIT_POS_PROBE_OUT217 = "16'b0000000011011001" *)
(* LC_LOW_BIT_POS_PROBE_OUT218 = "16'b0000000011011010" *)
(* LC_LOW_BIT_POS_PROBE_OUT219 = "16'b0000000011011011" *)
(* LC_LOW_BIT_POS_PROBE_OUT22 = "16'b0000000000010110" *)
(* LC_LOW_BIT_POS_PROBE_OUT220 = "16'b0000000011011100" *)
(* LC_LOW_BIT_POS_PROBE_OUT221 = "16'b0000000011011101" *)
(* LC_LOW_BIT_POS_PROBE_OUT222 = "16'b0000000011011110" *)
(* LC_LOW_BIT_POS_PROBE_OUT223 = "16'b0000000011011111" *)
(* LC_LOW_BIT_POS_PROBE_OUT224 = "16'b0000000011100000" *)
(* LC_LOW_BIT_POS_PROBE_OUT225 = "16'b0000000011100001" *)
(* LC_LOW_BIT_POS_PROBE_OUT226 = "16'b0000000011100010" *)
(* LC_LOW_BIT_POS_PROBE_OUT227 = "16'b0000000011100011" *)
(* LC_LOW_BIT_POS_PROBE_OUT228 = "16'b0000000011100100" *)
(* LC_LOW_BIT_POS_PROBE_OUT229 = "16'b0000000011100101" *)
(* LC_LOW_BIT_POS_PROBE_OUT23 = "16'b0000000000010111" *)
(* LC_LOW_BIT_POS_PROBE_OUT230 = "16'b0000000011100110" *)
(* LC_LOW_BIT_POS_PROBE_OUT231 = "16'b0000000011100111" *)
(* LC_LOW_BIT_POS_PROBE_OUT232 = "16'b0000000011101000" *)
(* LC_LOW_BIT_POS_PROBE_OUT233 = "16'b0000000011101001" *)
(* LC_LOW_BIT_POS_PROBE_OUT234 = "16'b0000000011101010" *)
(* LC_LOW_BIT_POS_PROBE_OUT235 = "16'b0000000011101011" *)
(* LC_LOW_BIT_POS_PROBE_OUT236 = "16'b0000000011101100" *)
(* LC_LOW_BIT_POS_PROBE_OUT237 = "16'b0000000011101101" *)
(* LC_LOW_BIT_POS_PROBE_OUT238 = "16'b0000000011101110" *)
(* LC_LOW_BIT_POS_PROBE_OUT239 = "16'b0000000011101111" *)
(* LC_LOW_BIT_POS_PROBE_OUT24 = "16'b0000000000011000" *)
(* LC_LOW_BIT_POS_PROBE_OUT240 = "16'b0000000011110000" *)
(* LC_LOW_BIT_POS_PROBE_OUT241 = "16'b0000000011110001" *)
(* LC_LOW_BIT_POS_PROBE_OUT242 = "16'b0000000011110010" *)
(* LC_LOW_BIT_POS_PROBE_OUT243 = "16'b0000000011110011" *)
(* LC_LOW_BIT_POS_PROBE_OUT244 = "16'b0000000011110100" *)
(* LC_LOW_BIT_POS_PROBE_OUT245 = "16'b0000000011110101" *)
(* LC_LOW_BIT_POS_PROBE_OUT246 = "16'b0000000011110110" *)
(* LC_LOW_BIT_POS_PROBE_OUT247 = "16'b0000000011110111" *)
(* LC_LOW_BIT_POS_PROBE_OUT248 = "16'b0000000011111000" *)
(* LC_LOW_BIT_POS_PROBE_OUT249 = "16'b0000000011111001" *)
(* LC_LOW_BIT_POS_PROBE_OUT25 = "16'b0000000000011001" *)
(* LC_LOW_BIT_POS_PROBE_OUT250 = "16'b0000000011111010" *)
(* LC_LOW_BIT_POS_PROBE_OUT251 = "16'b0000000011111011" *)
(* LC_LOW_BIT_POS_PROBE_OUT252 = "16'b0000000011111100" *)
(* LC_LOW_BIT_POS_PROBE_OUT253 = "16'b0000000011111101" *)
(* LC_LOW_BIT_POS_PROBE_OUT254 = "16'b0000000011111110" *)
(* LC_LOW_BIT_POS_PROBE_OUT255 = "16'b0000000011111111" *)
(* LC_LOW_BIT_POS_PROBE_OUT26 = "16'b0000000000011010" *)
(* LC_LOW_BIT_POS_PROBE_OUT27 = "16'b0000000000011011" *)
(* LC_LOW_BIT_POS_PROBE_OUT28 = "16'b0000000000011100" *)
(* LC_LOW_BIT_POS_PROBE_OUT29 = "16'b0000000000011101" *)
(* LC_LOW_BIT_POS_PROBE_OUT3 = "16'b0000000000000011" *)
(* LC_LOW_BIT_POS_PROBE_OUT30 = "16'b0000000000011110" *)
(* LC_LOW_BIT_POS_PROBE_OUT31 = "16'b0000000000011111" *)
(* LC_LOW_BIT_POS_PROBE_OUT32 = "16'b0000000000100000" *)
(* LC_LOW_BIT_POS_PROBE_OUT33 = "16'b0000000000100001" *)
(* LC_LOW_BIT_POS_PROBE_OUT34 = "16'b0000000000100010" *)
(* LC_LOW_BIT_POS_PROBE_OUT35 = "16'b0000000000100011" *)
(* LC_LOW_BIT_POS_PROBE_OUT36 = "16'b0000000000100100" *)
(* LC_LOW_BIT_POS_PROBE_OUT37 = "16'b0000000000100101" *)
(* LC_LOW_BIT_POS_PROBE_OUT38 = "16'b0000000000100110" *)
(* LC_LOW_BIT_POS_PROBE_OUT39 = "16'b0000000000100111" *)
(* LC_LOW_BIT_POS_PROBE_OUT4 = "16'b0000000000000100" *)
(* LC_LOW_BIT_POS_PROBE_OUT40 = "16'b0000000000101000" *)
(* LC_LOW_BIT_POS_PROBE_OUT41 = "16'b0000000000101001" *)
(* LC_LOW_BIT_POS_PROBE_OUT42 = "16'b0000000000101010" *)
(* LC_LOW_BIT_POS_PROBE_OUT43 = "16'b0000000000101011" *)
(* LC_LOW_BIT_POS_PROBE_OUT44 = "16'b0000000000101100" *)
(* LC_LOW_BIT_POS_PROBE_OUT45 = "16'b0000000000101101" *)
(* LC_LOW_BIT_POS_PROBE_OUT46 = "16'b0000000000101110" *)
(* LC_LOW_BIT_POS_PROBE_OUT47 = "16'b0000000000101111" *)
(* LC_LOW_BIT_POS_PROBE_OUT48 = "16'b0000000000110000" *)
(* LC_LOW_BIT_POS_PROBE_OUT49 = "16'b0000000000110001" *)
(* LC_LOW_BIT_POS_PROBE_OUT5 = "16'b0000000000000101" *)
(* LC_LOW_BIT_POS_PROBE_OUT50 = "16'b0000000000110010" *)
(* LC_LOW_BIT_POS_PROBE_OUT51 = "16'b0000000000110011" *)
(* LC_LOW_BIT_POS_PROBE_OUT52 = "16'b0000000000110100" *)
(* LC_LOW_BIT_POS_PROBE_OUT53 = "16'b0000000000110101" *)
(* LC_LOW_BIT_POS_PROBE_OUT54 = "16'b0000000000110110" *)
(* LC_LOW_BIT_POS_PROBE_OUT55 = "16'b0000000000110111" *)
(* LC_LOW_BIT_POS_PROBE_OUT56 = "16'b0000000000111000" *)
(* LC_LOW_BIT_POS_PROBE_OUT57 = "16'b0000000000111001" *)
(* LC_LOW_BIT_POS_PROBE_OUT58 = "16'b0000000000111010" *)
(* LC_LOW_BIT_POS_PROBE_OUT59 = "16'b0000000000111011" *)
(* LC_LOW_BIT_POS_PROBE_OUT6 = "16'b0000000000000110" *)
(* LC_LOW_BIT_POS_PROBE_OUT60 = "16'b0000000000111100" *)
(* LC_LOW_BIT_POS_PROBE_OUT61 = "16'b0000000000111101" *)
(* LC_LOW_BIT_POS_PROBE_OUT62 = "16'b0000000000111110" *)
(* LC_LOW_BIT_POS_PROBE_OUT63 = "16'b0000000000111111" *)
(* LC_LOW_BIT_POS_PROBE_OUT64 = "16'b0000000001000000" *)
(* LC_LOW_BIT_POS_PROBE_OUT65 = "16'b0000000001000001" *)
(* LC_LOW_BIT_POS_PROBE_OUT66 = "16'b0000000001000010" *)
(* LC_LOW_BIT_POS_PROBE_OUT67 = "16'b0000000001000011" *)
(* LC_LOW_BIT_POS_PROBE_OUT68 = "16'b0000000001000100" *)
(* LC_LOW_BIT_POS_PROBE_OUT69 = "16'b0000000001000101" *)
(* LC_LOW_BIT_POS_PROBE_OUT7 = "16'b0000000000000111" *)
(* LC_LOW_BIT_POS_PROBE_OUT70 = "16'b0000000001000110" *)
(* LC_LOW_BIT_POS_PROBE_OUT71 = "16'b0000000001000111" *)
(* LC_LOW_BIT_POS_PROBE_OUT72 = "16'b0000000001001000" *)
(* LC_LOW_BIT_POS_PROBE_OUT73 = "16'b0000000001001001" *)
(* LC_LOW_BIT_POS_PROBE_OUT74 = "16'b0000000001001010" *)
(* LC_LOW_BIT_POS_PROBE_OUT75 = "16'b0000000001001011" *)
(* LC_LOW_BIT_POS_PROBE_OUT76 = "16'b0000000001001100" *)
(* LC_LOW_BIT_POS_PROBE_OUT77 = "16'b0000000001001101" *)
(* LC_LOW_BIT_POS_PROBE_OUT78 = "16'b0000000001001110" *)
(* LC_LOW_BIT_POS_PROBE_OUT79 = "16'b0000000001001111" *)
(* LC_LOW_BIT_POS_PROBE_OUT8 = "16'b0000000000001000" *)
(* LC_LOW_BIT_POS_PROBE_OUT80 = "16'b0000000001010000" *)
(* LC_LOW_BIT_POS_PROBE_OUT81 = "16'b0000000001010001" *)
(* LC_LOW_BIT_POS_PROBE_OUT82 = "16'b0000000001010010" *)
(* LC_LOW_BIT_POS_PROBE_OUT83 = "16'b0000000001010011" *)
(* LC_LOW_BIT_POS_PROBE_OUT84 = "16'b0000000001010100" *)
(* LC_LOW_BIT_POS_PROBE_OUT85 = "16'b0000000001010101" *)
(* LC_LOW_BIT_POS_PROBE_OUT86 = "16'b0000000001010110" *)
(* LC_LOW_BIT_POS_PROBE_OUT87 = "16'b0000000001010111" *)
(* LC_LOW_BIT_POS_PROBE_OUT88 = "16'b0000000001011000" *)
(* LC_LOW_BIT_POS_PROBE_OUT89 = "16'b0000000001011001" *)
(* LC_LOW_BIT_POS_PROBE_OUT9 = "16'b0000000000001001" *)
(* LC_LOW_BIT_POS_PROBE_OUT90 = "16'b0000000001011010" *)
(* LC_LOW_BIT_POS_PROBE_OUT91 = "16'b0000000001011011" *)
(* LC_LOW_BIT_POS_PROBE_OUT92 = "16'b0000000001011100" *)
(* LC_LOW_BIT_POS_PROBE_OUT93 = "16'b0000000001011101" *)
(* LC_LOW_BIT_POS_PROBE_OUT94 = "16'b0000000001011110" *)
(* LC_LOW_BIT_POS_PROBE_OUT95 = "16'b0000000001011111" *)
(* LC_LOW_BIT_POS_PROBE_OUT96 = "16'b0000000001100000" *)
(* LC_LOW_BIT_POS_PROBE_OUT97 = "16'b0000000001100001" *)
(* LC_LOW_BIT_POS_PROBE_OUT98 = "16'b0000000001100010" *)
(* LC_LOW_BIT_POS_PROBE_OUT99 = "16'b0000000001100011" *)
(* LC_PROBE_IN_WIDTH_STRING = "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* LC_PROBE_OUT_HIGH_BIT_POS_STRING = "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000" *)
(* LC_PROBE_OUT_INIT_VAL_STRING = "256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* LC_PROBE_OUT_LOW_BIT_POS_STRING = "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000" *)
(* LC_PROBE_OUT_WIDTH_STRING = "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* LC_TOTAL_PROBE_IN_WIDTH = "3" *)
(* LC_TOTAL_PROBE_OUT_WIDTH = "0" *)
(* syn_noprune = "1" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio inst
(.clk(clk),
.probe_in0(probe_in0),
.probe_in1(probe_in1),
.probe_in10(1'b0),
.probe_in100(1'b0),
.probe_in101(1'b0),
.probe_in102(1'b0),
.probe_in103(1'b0),
.probe_in104(1'b0),
.probe_in105(1'b0),
.probe_in106(1'b0),
.probe_in107(1'b0),
.probe_in108(1'b0),
.probe_in109(1'b0),
.probe_in11(1'b0),
.probe_in110(1'b0),
.probe_in111(1'b0),
.probe_in112(1'b0),
.probe_in113(1'b0),
.probe_in114(1'b0),
.probe_in115(1'b0),
.probe_in116(1'b0),
.probe_in117(1'b0),
.probe_in118(1'b0),
.probe_in119(1'b0),
.probe_in12(1'b0),
.probe_in120(1'b0),
.probe_in121(1'b0),
.probe_in122(1'b0),
.probe_in123(1'b0),
.probe_in124(1'b0),
.probe_in125(1'b0),
.probe_in126(1'b0),
.probe_in127(1'b0),
.probe_in128(1'b0),
.probe_in129(1'b0),
.probe_in13(1'b0),
.probe_in130(1'b0),
.probe_in131(1'b0),
.probe_in132(1'b0),
.probe_in133(1'b0),
.probe_in134(1'b0),
.probe_in135(1'b0),
.probe_in136(1'b0),
.probe_in137(1'b0),
.probe_in138(1'b0),
.probe_in139(1'b0),
.probe_in14(1'b0),
.probe_in140(1'b0),
.probe_in141(1'b0),
.probe_in142(1'b0),
.probe_in143(1'b0),
.probe_in144(1'b0),
.probe_in145(1'b0),
.probe_in146(1'b0),
.probe_in147(1'b0),
.probe_in148(1'b0),
.probe_in149(1'b0),
.probe_in15(1'b0),
.probe_in150(1'b0),
.probe_in151(1'b0),
.probe_in152(1'b0),
.probe_in153(1'b0),
.probe_in154(1'b0),
.probe_in155(1'b0),
.probe_in156(1'b0),
.probe_in157(1'b0),
.probe_in158(1'b0),
.probe_in159(1'b0),
.probe_in16(1'b0),
.probe_in160(1'b0),
.probe_in161(1'b0),
.probe_in162(1'b0),
.probe_in163(1'b0),
.probe_in164(1'b0),
.probe_in165(1'b0),
.probe_in166(1'b0),
.probe_in167(1'b0),
.probe_in168(1'b0),
.probe_in169(1'b0),
.probe_in17(1'b0),
.probe_in170(1'b0),
.probe_in171(1'b0),
.probe_in172(1'b0),
.probe_in173(1'b0),
.probe_in174(1'b0),
.probe_in175(1'b0),
.probe_in176(1'b0),
.probe_in177(1'b0),
.probe_in178(1'b0),
.probe_in179(1'b0),
.probe_in18(1'b0),
.probe_in180(1'b0),
.probe_in181(1'b0),
.probe_in182(1'b0),
.probe_in183(1'b0),
.probe_in184(1'b0),
.probe_in185(1'b0),
.probe_in186(1'b0),
.probe_in187(1'b0),
.probe_in188(1'b0),
.probe_in189(1'b0),
.probe_in19(1'b0),
.probe_in190(1'b0),
.probe_in191(1'b0),
.probe_in192(1'b0),
.probe_in193(1'b0),
.probe_in194(1'b0),
.probe_in195(1'b0),
.probe_in196(1'b0),
.probe_in197(1'b0),
.probe_in198(1'b0),
.probe_in199(1'b0),
.probe_in2(probe_in2),
.probe_in20(1'b0),
.probe_in200(1'b0),
.probe_in201(1'b0),
.probe_in202(1'b0),
.probe_in203(1'b0),
.probe_in204(1'b0),
.probe_in205(1'b0),
.probe_in206(1'b0),
.probe_in207(1'b0),
.probe_in208(1'b0),
.probe_in209(1'b0),
.probe_in21(1'b0),
.probe_in210(1'b0),
.probe_in211(1'b0),
.probe_in212(1'b0),
.probe_in213(1'b0),
.probe_in214(1'b0),
.probe_in215(1'b0),
.probe_in216(1'b0),
.probe_in217(1'b0),
.probe_in218(1'b0),
.probe_in219(1'b0),
.probe_in22(1'b0),
.probe_in220(1'b0),
.probe_in221(1'b0),
.probe_in222(1'b0),
.probe_in223(1'b0),
.probe_in224(1'b0),
.probe_in225(1'b0),
.probe_in226(1'b0),
.probe_in227(1'b0),
.probe_in228(1'b0),
.probe_in229(1'b0),
.probe_in23(1'b0),
.probe_in230(1'b0),
.probe_in231(1'b0),
.probe_in232(1'b0),
.probe_in233(1'b0),
.probe_in234(1'b0),
.probe_in235(1'b0),
.probe_in236(1'b0),
.probe_in237(1'b0),
.probe_in238(1'b0),
.probe_in239(1'b0),
.probe_in24(1'b0),
.probe_in240(1'b0),
.probe_in241(1'b0),
.probe_in242(1'b0),
.probe_in243(1'b0),
.probe_in244(1'b0),
.probe_in245(1'b0),
.probe_in246(1'b0),
.probe_in247(1'b0),
.probe_in248(1'b0),
.probe_in249(1'b0),
.probe_in25(1'b0),
.probe_in250(1'b0),
.probe_in251(1'b0),
.probe_in252(1'b0),
.probe_in253(1'b0),
.probe_in254(1'b0),
.probe_in255(1'b0),
.probe_in26(1'b0),
.probe_in27(1'b0),
.probe_in28(1'b0),
.probe_in29(1'b0),
.probe_in3(1'b0),
.probe_in30(1'b0),
.probe_in31(1'b0),
.probe_in32(1'b0),
.probe_in33(1'b0),
.probe_in34(1'b0),
.probe_in35(1'b0),
.probe_in36(1'b0),
.probe_in37(1'b0),
.probe_in38(1'b0),
.probe_in39(1'b0),
.probe_in4(1'b0),
.probe_in40(1'b0),
.probe_in41(1'b0),
.probe_in42(1'b0),
.probe_in43(1'b0),
.probe_in44(1'b0),
.probe_in45(1'b0),
.probe_in46(1'b0),
.probe_in47(1'b0),
.probe_in48(1'b0),
.probe_in49(1'b0),
.probe_in5(1'b0),
.probe_in50(1'b0),
.probe_in51(1'b0),
.probe_in52(1'b0),
.probe_in53(1'b0),
.probe_in54(1'b0),
.probe_in55(1'b0),
.probe_in56(1'b0),
.probe_in57(1'b0),
.probe_in58(1'b0),
.probe_in59(1'b0),
.probe_in6(1'b0),
.probe_in60(1'b0),
.probe_in61(1'b0),
.probe_in62(1'b0),
.probe_in63(1'b0),
.probe_in64(1'b0),
.probe_in65(1'b0),
.probe_in66(1'b0),
.probe_in67(1'b0),
.probe_in68(1'b0),
.probe_in69(1'b0),
.probe_in7(1'b0),
.probe_in70(1'b0),
.probe_in71(1'b0),
.probe_in72(1'b0),
.probe_in73(1'b0),
.probe_in74(1'b0),
.probe_in75(1'b0),
.probe_in76(1'b0),
.probe_in77(1'b0),
.probe_in78(1'b0),
.probe_in79(1'b0),
.probe_in8(1'b0),
.probe_in80(1'b0),
.probe_in81(1'b0),
.probe_in82(1'b0),
.probe_in83(1'b0),
.probe_in84(1'b0),
.probe_in85(1'b0),
.probe_in86(1'b0),
.probe_in87(1'b0),
.probe_in88(1'b0),
.probe_in89(1'b0),
.probe_in9(1'b0),
.probe_in90(1'b0),
.probe_in91(1'b0),
.probe_in92(1'b0),
.probe_in93(1'b0),
.probe_in94(1'b0),
.probe_in95(1'b0),
.probe_in96(1'b0),
.probe_in97(1'b0),
.probe_in98(1'b0),
.probe_in99(1'b0),
.probe_out0(NLW_inst_probe_out0_UNCONNECTED[0]),
.probe_out1(NLW_inst_probe_out1_UNCONNECTED[0]),
.probe_out10(NLW_inst_probe_out10_UNCONNECTED[0]),
.probe_out100(NLW_inst_probe_out100_UNCONNECTED[0]),
.probe_out101(NLW_inst_probe_out101_UNCONNECTED[0]),
.probe_out102(NLW_inst_probe_out102_UNCONNECTED[0]),
.probe_out103(NLW_inst_probe_out103_UNCONNECTED[0]),
.probe_out104(NLW_inst_probe_out104_UNCONNECTED[0]),
.probe_out105(NLW_inst_probe_out105_UNCONNECTED[0]),
.probe_out106(NLW_inst_probe_out106_UNCONNECTED[0]),
.probe_out107(NLW_inst_probe_out107_UNCONNECTED[0]),
.probe_out108(NLW_inst_probe_out108_UNCONNECTED[0]),
.probe_out109(NLW_inst_probe_out109_UNCONNECTED[0]),
.probe_out11(NLW_inst_probe_out11_UNCONNECTED[0]),
.probe_out110(NLW_inst_probe_out110_UNCONNECTED[0]),
.probe_out111(NLW_inst_probe_out111_UNCONNECTED[0]),
.probe_out112(NLW_inst_probe_out112_UNCONNECTED[0]),
.probe_out113(NLW_inst_probe_out113_UNCONNECTED[0]),
.probe_out114(NLW_inst_probe_out114_UNCONNECTED[0]),
.probe_out115(NLW_inst_probe_out115_UNCONNECTED[0]),
.probe_out116(NLW_inst_probe_out116_UNCONNECTED[0]),
.probe_out117(NLW_inst_probe_out117_UNCONNECTED[0]),
.probe_out118(NLW_inst_probe_out118_UNCONNECTED[0]),
.probe_out119(NLW_inst_probe_out119_UNCONNECTED[0]),
.probe_out12(NLW_inst_probe_out12_UNCONNECTED[0]),
.probe_out120(NLW_inst_probe_out120_UNCONNECTED[0]),
.probe_out121(NLW_inst_probe_out121_UNCONNECTED[0]),
.probe_out122(NLW_inst_probe_out122_UNCONNECTED[0]),
.probe_out123(NLW_inst_probe_out123_UNCONNECTED[0]),
.probe_out124(NLW_inst_probe_out124_UNCONNECTED[0]),
.probe_out125(NLW_inst_probe_out125_UNCONNECTED[0]),
.probe_out126(NLW_inst_probe_out126_UNCONNECTED[0]),
.probe_out127(NLW_inst_probe_out127_UNCONNECTED[0]),
.probe_out128(NLW_inst_probe_out128_UNCONNECTED[0]),
.probe_out129(NLW_inst_probe_out129_UNCONNECTED[0]),
.probe_out13(NLW_inst_probe_out13_UNCONNECTED[0]),
.probe_out130(NLW_inst_probe_out130_UNCONNECTED[0]),
.probe_out131(NLW_inst_probe_out131_UNCONNECTED[0]),
.probe_out132(NLW_inst_probe_out132_UNCONNECTED[0]),
.probe_out133(NLW_inst_probe_out133_UNCONNECTED[0]),
.probe_out134(NLW_inst_probe_out134_UNCONNECTED[0]),
.probe_out135(NLW_inst_probe_out135_UNCONNECTED[0]),
.probe_out136(NLW_inst_probe_out136_UNCONNECTED[0]),
.probe_out137(NLW_inst_probe_out137_UNCONNECTED[0]),
.probe_out138(NLW_inst_probe_out138_UNCONNECTED[0]),
.probe_out139(NLW_inst_probe_out139_UNCONNECTED[0]),
.probe_out14(NLW_inst_probe_out14_UNCONNECTED[0]),
.probe_out140(NLW_inst_probe_out140_UNCONNECTED[0]),
.probe_out141(NLW_inst_probe_out141_UNCONNECTED[0]),
.probe_out142(NLW_inst_probe_out142_UNCONNECTED[0]),
.probe_out143(NLW_inst_probe_out143_UNCONNECTED[0]),
.probe_out144(NLW_inst_probe_out144_UNCONNECTED[0]),
.probe_out145(NLW_inst_probe_out145_UNCONNECTED[0]),
.probe_out146(NLW_inst_probe_out146_UNCONNECTED[0]),
.probe_out147(NLW_inst_probe_out147_UNCONNECTED[0]),
.probe_out148(NLW_inst_probe_out148_UNCONNECTED[0]),
.probe_out149(NLW_inst_probe_out149_UNCONNECTED[0]),
.probe_out15(NLW_inst_probe_out15_UNCONNECTED[0]),
.probe_out150(NLW_inst_probe_out150_UNCONNECTED[0]),
.probe_out151(NLW_inst_probe_out151_UNCONNECTED[0]),
.probe_out152(NLW_inst_probe_out152_UNCONNECTED[0]),
.probe_out153(NLW_inst_probe_out153_UNCONNECTED[0]),
.probe_out154(NLW_inst_probe_out154_UNCONNECTED[0]),
.probe_out155(NLW_inst_probe_out155_UNCONNECTED[0]),
.probe_out156(NLW_inst_probe_out156_UNCONNECTED[0]),
.probe_out157(NLW_inst_probe_out157_UNCONNECTED[0]),
.probe_out158(NLW_inst_probe_out158_UNCONNECTED[0]),
.probe_out159(NLW_inst_probe_out159_UNCONNECTED[0]),
.probe_out16(NLW_inst_probe_out16_UNCONNECTED[0]),
.probe_out160(NLW_inst_probe_out160_UNCONNECTED[0]),
.probe_out161(NLW_inst_probe_out161_UNCONNECTED[0]),
.probe_out162(NLW_inst_probe_out162_UNCONNECTED[0]),
.probe_out163(NLW_inst_probe_out163_UNCONNECTED[0]),
.probe_out164(NLW_inst_probe_out164_UNCONNECTED[0]),
.probe_out165(NLW_inst_probe_out165_UNCONNECTED[0]),
.probe_out166(NLW_inst_probe_out166_UNCONNECTED[0]),
.probe_out167(NLW_inst_probe_out167_UNCONNECTED[0]),
.probe_out168(NLW_inst_probe_out168_UNCONNECTED[0]),
.probe_out169(NLW_inst_probe_out169_UNCONNECTED[0]),
.probe_out17(NLW_inst_probe_out17_UNCONNECTED[0]),
.probe_out170(NLW_inst_probe_out170_UNCONNECTED[0]),
.probe_out171(NLW_inst_probe_out171_UNCONNECTED[0]),
.probe_out172(NLW_inst_probe_out172_UNCONNECTED[0]),
.probe_out173(NLW_inst_probe_out173_UNCONNECTED[0]),
.probe_out174(NLW_inst_probe_out174_UNCONNECTED[0]),
.probe_out175(NLW_inst_probe_out175_UNCONNECTED[0]),
.probe_out176(NLW_inst_probe_out176_UNCONNECTED[0]),
.probe_out177(NLW_inst_probe_out177_UNCONNECTED[0]),
.probe_out178(NLW_inst_probe_out178_UNCONNECTED[0]),
.probe_out179(NLW_inst_probe_out179_UNCONNECTED[0]),
.probe_out18(NLW_inst_probe_out18_UNCONNECTED[0]),
.probe_out180(NLW_inst_probe_out180_UNCONNECTED[0]),
.probe_out181(NLW_inst_probe_out181_UNCONNECTED[0]),
.probe_out182(NLW_inst_probe_out182_UNCONNECTED[0]),
.probe_out183(NLW_inst_probe_out183_UNCONNECTED[0]),
.probe_out184(NLW_inst_probe_out184_UNCONNECTED[0]),
.probe_out185(NLW_inst_probe_out185_UNCONNECTED[0]),
.probe_out186(NLW_inst_probe_out186_UNCONNECTED[0]),
.probe_out187(NLW_inst_probe_out187_UNCONNECTED[0]),
.probe_out188(NLW_inst_probe_out188_UNCONNECTED[0]),
.probe_out189(NLW_inst_probe_out189_UNCONNECTED[0]),
.probe_out19(NLW_inst_probe_out19_UNCONNECTED[0]),
.probe_out190(NLW_inst_probe_out190_UNCONNECTED[0]),
.probe_out191(NLW_inst_probe_out191_UNCONNECTED[0]),
.probe_out192(NLW_inst_probe_out192_UNCONNECTED[0]),
.probe_out193(NLW_inst_probe_out193_UNCONNECTED[0]),
.probe_out194(NLW_inst_probe_out194_UNCONNECTED[0]),
.probe_out195(NLW_inst_probe_out195_UNCONNECTED[0]),
.probe_out196(NLW_inst_probe_out196_UNCONNECTED[0]),
.probe_out197(NLW_inst_probe_out197_UNCONNECTED[0]),
.probe_out198(NLW_inst_probe_out198_UNCONNECTED[0]),
.probe_out199(NLW_inst_probe_out199_UNCONNECTED[0]),
.probe_out2(NLW_inst_probe_out2_UNCONNECTED[0]),
.probe_out20(NLW_inst_probe_out20_UNCONNECTED[0]),
.probe_out200(NLW_inst_probe_out200_UNCONNECTED[0]),
.probe_out201(NLW_inst_probe_out201_UNCONNECTED[0]),
.probe_out202(NLW_inst_probe_out202_UNCONNECTED[0]),
.probe_out203(NLW_inst_probe_out203_UNCONNECTED[0]),
.probe_out204(NLW_inst_probe_out204_UNCONNECTED[0]),
.probe_out205(NLW_inst_probe_out205_UNCONNECTED[0]),
.probe_out206(NLW_inst_probe_out206_UNCONNECTED[0]),
.probe_out207(NLW_inst_probe_out207_UNCONNECTED[0]),
.probe_out208(NLW_inst_probe_out208_UNCONNECTED[0]),
.probe_out209(NLW_inst_probe_out209_UNCONNECTED[0]),
.probe_out21(NLW_inst_probe_out21_UNCONNECTED[0]),
.probe_out210(NLW_inst_probe_out210_UNCONNECTED[0]),
.probe_out211(NLW_inst_probe_out211_UNCONNECTED[0]),
.probe_out212(NLW_inst_probe_out212_UNCONNECTED[0]),
.probe_out213(NLW_inst_probe_out213_UNCONNECTED[0]),
.probe_out214(NLW_inst_probe_out214_UNCONNECTED[0]),
.probe_out215(NLW_inst_probe_out215_UNCONNECTED[0]),
.probe_out216(NLW_inst_probe_out216_UNCONNECTED[0]),
.probe_out217(NLW_inst_probe_out217_UNCONNECTED[0]),
.probe_out218(NLW_inst_probe_out218_UNCONNECTED[0]),
.probe_out219(NLW_inst_probe_out219_UNCONNECTED[0]),
.probe_out22(NLW_inst_probe_out22_UNCONNECTED[0]),
.probe_out220(NLW_inst_probe_out220_UNCONNECTED[0]),
.probe_out221(NLW_inst_probe_out221_UNCONNECTED[0]),
.probe_out222(NLW_inst_probe_out222_UNCONNECTED[0]),
.probe_out223(NLW_inst_probe_out223_UNCONNECTED[0]),
.probe_out224(NLW_inst_probe_out224_UNCONNECTED[0]),
.probe_out225(NLW_inst_probe_out225_UNCONNECTED[0]),
.probe_out226(NLW_inst_probe_out226_UNCONNECTED[0]),
.probe_out227(NLW_inst_probe_out227_UNCONNECTED[0]),
.probe_out228(NLW_inst_probe_out228_UNCONNECTED[0]),
.probe_out229(NLW_inst_probe_out229_UNCONNECTED[0]),
.probe_out23(NLW_inst_probe_out23_UNCONNECTED[0]),
.probe_out230(NLW_inst_probe_out230_UNCONNECTED[0]),
.probe_out231(NLW_inst_probe_out231_UNCONNECTED[0]),
.probe_out232(NLW_inst_probe_out232_UNCONNECTED[0]),
.probe_out233(NLW_inst_probe_out233_UNCONNECTED[0]),
.probe_out234(NLW_inst_probe_out234_UNCONNECTED[0]),
.probe_out235(NLW_inst_probe_out235_UNCONNECTED[0]),
.probe_out236(NLW_inst_probe_out236_UNCONNECTED[0]),
.probe_out237(NLW_inst_probe_out237_UNCONNECTED[0]),
.probe_out238(NLW_inst_probe_out238_UNCONNECTED[0]),
.probe_out239(NLW_inst_probe_out239_UNCONNECTED[0]),
.probe_out24(NLW_inst_probe_out24_UNCONNECTED[0]),
.probe_out240(NLW_inst_probe_out240_UNCONNECTED[0]),
.probe_out241(NLW_inst_probe_out241_UNCONNECTED[0]),
.probe_out242(NLW_inst_probe_out242_UNCONNECTED[0]),
.probe_out243(NLW_inst_probe_out243_UNCONNECTED[0]),
.probe_out244(NLW_inst_probe_out244_UNCONNECTED[0]),
.probe_out245(NLW_inst_probe_out245_UNCONNECTED[0]),
.probe_out246(NLW_inst_probe_out246_UNCONNECTED[0]),
.probe_out247(NLW_inst_probe_out247_UNCONNECTED[0]),
.probe_out248(NLW_inst_probe_out248_UNCONNECTED[0]),
.probe_out249(NLW_inst_probe_out249_UNCONNECTED[0]),
.probe_out25(NLW_inst_probe_out25_UNCONNECTED[0]),
.probe_out250(NLW_inst_probe_out250_UNCONNECTED[0]),
.probe_out251(NLW_inst_probe_out251_UNCONNECTED[0]),
.probe_out252(NLW_inst_probe_out252_UNCONNECTED[0]),
.probe_out253(NLW_inst_probe_out253_UNCONNECTED[0]),
.probe_out254(NLW_inst_probe_out254_UNCONNECTED[0]),
.probe_out255(NLW_inst_probe_out255_UNCONNECTED[0]),
.probe_out26(NLW_inst_probe_out26_UNCONNECTED[0]),
.probe_out27(NLW_inst_probe_out27_UNCONNECTED[0]),
.probe_out28(NLW_inst_probe_out28_UNCONNECTED[0]),
.probe_out29(NLW_inst_probe_out29_UNCONNECTED[0]),
.probe_out3(NLW_inst_probe_out3_UNCONNECTED[0]),
.probe_out30(NLW_inst_probe_out30_UNCONNECTED[0]),
.probe_out31(NLW_inst_probe_out31_UNCONNECTED[0]),
.probe_out32(NLW_inst_probe_out32_UNCONNECTED[0]),
.probe_out33(NLW_inst_probe_out33_UNCONNECTED[0]),
.probe_out34(NLW_inst_probe_out34_UNCONNECTED[0]),
.probe_out35(NLW_inst_probe_out35_UNCONNECTED[0]),
.probe_out36(NLW_inst_probe_out36_UNCONNECTED[0]),
.probe_out37(NLW_inst_probe_out37_UNCONNECTED[0]),
.probe_out38(NLW_inst_probe_out38_UNCONNECTED[0]),
.probe_out39(NLW_inst_probe_out39_UNCONNECTED[0]),
.probe_out4(NLW_inst_probe_out4_UNCONNECTED[0]),
.probe_out40(NLW_inst_probe_out40_UNCONNECTED[0]),
.probe_out41(NLW_inst_probe_out41_UNCONNECTED[0]),
.probe_out42(NLW_inst_probe_out42_UNCONNECTED[0]),
.probe_out43(NLW_inst_probe_out43_UNCONNECTED[0]),
.probe_out44(NLW_inst_probe_out44_UNCONNECTED[0]),
.probe_out45(NLW_inst_probe_out45_UNCONNECTED[0]),
.probe_out46(NLW_inst_probe_out46_UNCONNECTED[0]),
.probe_out47(NLW_inst_probe_out47_UNCONNECTED[0]),
.probe_out48(NLW_inst_probe_out48_UNCONNECTED[0]),
.probe_out49(NLW_inst_probe_out49_UNCONNECTED[0]),
.probe_out5(NLW_inst_probe_out5_UNCONNECTED[0]),
.probe_out50(NLW_inst_probe_out50_UNCONNECTED[0]),
.probe_out51(NLW_inst_probe_out51_UNCONNECTED[0]),
.probe_out52(NLW_inst_probe_out52_UNCONNECTED[0]),
.probe_out53(NLW_inst_probe_out53_UNCONNECTED[0]),
.probe_out54(NLW_inst_probe_out54_UNCONNECTED[0]),
.probe_out55(NLW_inst_probe_out55_UNCONNECTED[0]),
.probe_out56(NLW_inst_probe_out56_UNCONNECTED[0]),
.probe_out57(NLW_inst_probe_out57_UNCONNECTED[0]),
.probe_out58(NLW_inst_probe_out58_UNCONNECTED[0]),
.probe_out59(NLW_inst_probe_out59_UNCONNECTED[0]),
.probe_out6(NLW_inst_probe_out6_UNCONNECTED[0]),
.probe_out60(NLW_inst_probe_out60_UNCONNECTED[0]),
.probe_out61(NLW_inst_probe_out61_UNCONNECTED[0]),
.probe_out62(NLW_inst_probe_out62_UNCONNECTED[0]),
.probe_out63(NLW_inst_probe_out63_UNCONNECTED[0]),
.probe_out64(NLW_inst_probe_out64_UNCONNECTED[0]),
.probe_out65(NLW_inst_probe_out65_UNCONNECTED[0]),
.probe_out66(NLW_inst_probe_out66_UNCONNECTED[0]),
.probe_out67(NLW_inst_probe_out67_UNCONNECTED[0]),
.probe_out68(NLW_inst_probe_out68_UNCONNECTED[0]),
.probe_out69(NLW_inst_probe_out69_UNCONNECTED[0]),
.probe_out7(NLW_inst_probe_out7_UNCONNECTED[0]),
.probe_out70(NLW_inst_probe_out70_UNCONNECTED[0]),
.probe_out71(NLW_inst_probe_out71_UNCONNECTED[0]),
.probe_out72(NLW_inst_probe_out72_UNCONNECTED[0]),
.probe_out73(NLW_inst_probe_out73_UNCONNECTED[0]),
.probe_out74(NLW_inst_probe_out74_UNCONNECTED[0]),
.probe_out75(NLW_inst_probe_out75_UNCONNECTED[0]),
.probe_out76(NLW_inst_probe_out76_UNCONNECTED[0]),
.probe_out77(NLW_inst_probe_out77_UNCONNECTED[0]),
.probe_out78(NLW_inst_probe_out78_UNCONNECTED[0]),
.probe_out79(NLW_inst_probe_out79_UNCONNECTED[0]),
.probe_out8(NLW_inst_probe_out8_UNCONNECTED[0]),
.probe_out80(NLW_inst_probe_out80_UNCONNECTED[0]),
.probe_out81(NLW_inst_probe_out81_UNCONNECTED[0]),
.probe_out82(NLW_inst_probe_out82_UNCONNECTED[0]),
.probe_out83(NLW_inst_probe_out83_UNCONNECTED[0]),
.probe_out84(NLW_inst_probe_out84_UNCONNECTED[0]),
.probe_out85(NLW_inst_probe_out85_UNCONNECTED[0]),
.probe_out86(NLW_inst_probe_out86_UNCONNECTED[0]),
.probe_out87(NLW_inst_probe_out87_UNCONNECTED[0]),
.probe_out88(NLW_inst_probe_out88_UNCONNECTED[0]),
.probe_out89(NLW_inst_probe_out89_UNCONNECTED[0]),
.probe_out9(NLW_inst_probe_out9_UNCONNECTED[0]),
.probe_out90(NLW_inst_probe_out90_UNCONNECTED[0]),
.probe_out91(NLW_inst_probe_out91_UNCONNECTED[0]),
.probe_out92(NLW_inst_probe_out92_UNCONNECTED[0]),
.probe_out93(NLW_inst_probe_out93_UNCONNECTED[0]),
.probe_out94(NLW_inst_probe_out94_UNCONNECTED[0]),
.probe_out95(NLW_inst_probe_out95_UNCONNECTED[0]),
.probe_out96(NLW_inst_probe_out96_UNCONNECTED[0]),
.probe_out97(NLW_inst_probe_out97_UNCONNECTED[0]),
.probe_out98(NLW_inst_probe_out98_UNCONNECTED[0]),
.probe_out99(NLW_inst_probe_out99_UNCONNECTED[0]),
.sl_iport0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.sl_oport0(NLW_inst_sl_oport0_UNCONNECTED[16:0]));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_decoder
(s_drdy_i,
\wr_en_reg[4]_0 ,
\wr_en_reg[4]_1 ,
\wr_en_reg[4]_2 ,
E,
s_do_i,
s_rst_o,
Q,
out,
s_daddr_o,
s_dwe_o,
s_den_o,
\Bus_Data_out_reg[8] );
output s_drdy_i;
output \wr_en_reg[4]_0 ;
output \wr_en_reg[4]_1 ;
output \wr_en_reg[4]_2 ;
output [0:0]E;
output [15:0]s_do_i;
input s_rst_o;
input [15:0]Q;
input out;
input [16:0]s_daddr_o;
input s_dwe_o;
input s_den_o;
input [8:0]\Bus_Data_out_reg[8] ;
wire [8:0]\Bus_Data_out_reg[8] ;
wire [0:0]E;
wire Hold_probe_in;
wire [15:0]Q;
wire clear_int;
wire committ_int;
wire [15:0]data_info_probe_in__64;
wire int_cnt_rst;
wire out;
wire [15:0]probe_out_modified;
wire rd_en_p1;
wire rd_en_p2;
wire [16:0]s_daddr_o;
wire s_den_o;
wire [15:0]s_do_i;
wire s_drdy_i;
wire s_dwe_o;
wire s_rst_o;
wire wr_control_reg;
wire \wr_en[2]_i_1_n_0 ;
wire \wr_en[2]_i_2_n_0 ;
wire \wr_en[4]_i_1_n_0 ;
wire \wr_en[4]_i_6_n_0 ;
wire \wr_en_reg[4]_0 ;
wire \wr_en_reg[4]_1 ;
wire \wr_en_reg[4]_2 ;
wire wr_probe_out_modified;
wire [2:0]xsdb_addr_2_0_p1;
wire [2:0]xsdb_addr_2_0_p2;
wire xsdb_addr_8_p1;
wire xsdb_addr_8_p2;
wire xsdb_drdy_i_1_n_0;
wire xsdb_rd;
wire xsdb_wr;
LUT6 #(
.INIT(64'hAFAF00000F00CFCF))
\Bus_data_out[0]_i_1
(.I0(\Bus_Data_out_reg[8] [0]),
.I1(probe_out_modified[0]),
.I2(xsdb_addr_2_0_p2[2]),
.I3(committ_int),
.I4(xsdb_addr_2_0_p2[1]),
.I5(xsdb_addr_2_0_p2[0]),
.O(data_info_probe_in__64[0]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT4 #(
.INIT(16'h0020))
\Bus_data_out[10]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[1]),
.I2(probe_out_modified[10]),
.I3(xsdb_addr_2_0_p2[0]),
.O(data_info_probe_in__64[10]));
LUT4 #(
.INIT(16'h0020))
\Bus_data_out[11]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[1]),
.I2(probe_out_modified[11]),
.I3(xsdb_addr_2_0_p2[0]),
.O(data_info_probe_in__64[11]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT4 #(
.INIT(16'h0020))
\Bus_data_out[12]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[1]),
.I2(probe_out_modified[12]),
.I3(xsdb_addr_2_0_p2[0]),
.O(data_info_probe_in__64[12]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'h0020))
\Bus_data_out[13]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[1]),
.I2(probe_out_modified[13]),
.I3(xsdb_addr_2_0_p2[0]),
.O(data_info_probe_in__64[13]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'h0020))
\Bus_data_out[14]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[1]),
.I2(probe_out_modified[14]),
.I3(xsdb_addr_2_0_p2[0]),
.O(data_info_probe_in__64[14]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h0020))
\Bus_data_out[15]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[1]),
.I2(probe_out_modified[15]),
.I3(xsdb_addr_2_0_p2[0]),
.O(data_info_probe_in__64[15]));
LUT6 #(
.INIT(64'hA0A000000F00CFCF))
\Bus_data_out[1]_i_1
(.I0(\Bus_Data_out_reg[8] [1]),
.I1(probe_out_modified[1]),
.I2(xsdb_addr_2_0_p2[2]),
.I3(clear_int),
.I4(xsdb_addr_2_0_p2[1]),
.I5(xsdb_addr_2_0_p2[0]),
.O(data_info_probe_in__64[1]));
LUT6 #(
.INIT(64'hA0000FC0A00000C0))
\Bus_data_out[2]_i_1
(.I0(\Bus_Data_out_reg[8] [2]),
.I1(probe_out_modified[2]),
.I2(xsdb_addr_2_0_p2[2]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(xsdb_addr_2_0_p2[0]),
.I5(int_cnt_rst),
.O(data_info_probe_in__64[2]));
LUT5 #(
.INIT(32'h88200020))
\Bus_data_out[3]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[0]),
.I2(probe_out_modified[3]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(\Bus_Data_out_reg[8] [3]),
.O(data_info_probe_in__64[3]));
LUT5 #(
.INIT(32'h88200020))
\Bus_data_out[4]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[0]),
.I2(probe_out_modified[4]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(\Bus_Data_out_reg[8] [4]),
.O(data_info_probe_in__64[4]));
LUT5 #(
.INIT(32'h88200020))
\Bus_data_out[5]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[0]),
.I2(probe_out_modified[5]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(\Bus_Data_out_reg[8] [5]),
.O(data_info_probe_in__64[5]));
LUT5 #(
.INIT(32'h88200020))
\Bus_data_out[6]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[0]),
.I2(probe_out_modified[6]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(\Bus_Data_out_reg[8] [6]),
.O(data_info_probe_in__64[6]));
LUT5 #(
.INIT(32'h88200020))
\Bus_data_out[7]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[0]),
.I2(probe_out_modified[7]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(\Bus_Data_out_reg[8] [7]),
.O(data_info_probe_in__64[7]));
LUT5 #(
.INIT(32'h88200020))
\Bus_data_out[8]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[0]),
.I2(probe_out_modified[8]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(\Bus_Data_out_reg[8] [8]),
.O(data_info_probe_in__64[8]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h0020))
\Bus_data_out[9]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[1]),
.I2(probe_out_modified[9]),
.I3(xsdb_addr_2_0_p2[0]),
.O(data_info_probe_in__64[9]));
FDRE \Bus_data_out_reg[0]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__64[0]),
.Q(s_do_i[0]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[10]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__64[10]),
.Q(s_do_i[10]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[11]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__64[11]),
.Q(s_do_i[11]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[12]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__64[12]),
.Q(s_do_i[12]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[13]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__64[13]),
.Q(s_do_i[13]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[14]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__64[14]),
.Q(s_do_i[14]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[15]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__64[15]),
.Q(s_do_i[15]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[1]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__64[1]),
.Q(s_do_i[1]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[2]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__64[2]),
.Q(s_do_i[2]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[3]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__64[3]),
.Q(s_do_i[3]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[4]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__64[4]),
.Q(s_do_i[4]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[5]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__64[5]),
.Q(s_do_i[5]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[6]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__64[6]),
.Q(s_do_i[6]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[7]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__64[7]),
.Q(s_do_i[7]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[8]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__64[8]),
.Q(s_do_i[8]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[9]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__64[9]),
.Q(s_do_i[9]),
.R(xsdb_addr_8_p2));
FDRE Hold_probe_in_reg
(.C(out),
.CE(wr_control_reg),
.D(Q[3]),
.Q(Hold_probe_in),
.R(s_rst_o));
FDRE clear_int_reg
(.C(out),
.CE(wr_control_reg),
.D(Q[1]),
.Q(clear_int),
.R(s_rst_o));
FDRE committ_int_reg
(.C(out),
.CE(wr_control_reg),
.D(Q[0]),
.Q(committ_int),
.R(s_rst_o));
FDRE int_cnt_rst_reg
(.C(out),
.CE(wr_control_reg),
.D(Q[2]),
.Q(int_cnt_rst),
.R(s_rst_o));
LUT1 #(
.INIT(2'h1))
\probe_in_reg[2]_i_1
(.I0(Hold_probe_in),
.O(E));
FDRE \probe_out_modified_reg[0]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[0]),
.Q(probe_out_modified[0]),
.R(clear_int));
FDRE \probe_out_modified_reg[10]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[10]),
.Q(probe_out_modified[10]),
.R(clear_int));
FDRE \probe_out_modified_reg[11]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[11]),
.Q(probe_out_modified[11]),
.R(clear_int));
FDRE \probe_out_modified_reg[12]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[12]),
.Q(probe_out_modified[12]),
.R(clear_int));
FDRE \probe_out_modified_reg[13]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[13]),
.Q(probe_out_modified[13]),
.R(clear_int));
FDRE \probe_out_modified_reg[14]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[14]),
.Q(probe_out_modified[14]),
.R(clear_int));
FDRE \probe_out_modified_reg[15]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[15]),
.Q(probe_out_modified[15]),
.R(clear_int));
FDRE \probe_out_modified_reg[1]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[1]),
.Q(probe_out_modified[1]),
.R(clear_int));
FDRE \probe_out_modified_reg[2]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[2]),
.Q(probe_out_modified[2]),
.R(clear_int));
FDRE \probe_out_modified_reg[3]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[3]),
.Q(probe_out_modified[3]),
.R(clear_int));
FDRE \probe_out_modified_reg[4]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[4]),
.Q(probe_out_modified[4]),
.R(clear_int));
FDRE \probe_out_modified_reg[5]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[5]),
.Q(probe_out_modified[5]),
.R(clear_int));
FDRE \probe_out_modified_reg[6]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[6]),
.Q(probe_out_modified[6]),
.R(clear_int));
FDRE \probe_out_modified_reg[7]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[7]),
.Q(probe_out_modified[7]),
.R(clear_int));
FDRE \probe_out_modified_reg[8]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[8]),
.Q(probe_out_modified[8]),
.R(clear_int));
FDRE \probe_out_modified_reg[9]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[9]),
.Q(probe_out_modified[9]),
.R(clear_int));
LUT2 #(
.INIT(4'h2))
rd_en_p1_i_1
(.I0(s_den_o),
.I1(s_dwe_o),
.O(xsdb_rd));
FDRE rd_en_p1_reg
(.C(out),
.CE(1'b1),
.D(xsdb_rd),
.Q(rd_en_p1),
.R(s_rst_o));
FDRE rd_en_p2_reg
(.C(out),
.CE(1'b1),
.D(rd_en_p1),
.Q(rd_en_p2),
.R(s_rst_o));
LUT6 #(
.INIT(64'h0000000000000002))
\wr_en[2]_i_1
(.I0(xsdb_wr),
.I1(s_daddr_o[2]),
.I2(\wr_en_reg[4]_0 ),
.I3(\wr_en_reg[4]_2 ),
.I4(\wr_en_reg[4]_1 ),
.I5(\wr_en[2]_i_2_n_0 ),
.O(\wr_en[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT2 #(
.INIT(4'hB))
\wr_en[2]_i_2
(.I0(s_daddr_o[0]),
.I1(s_daddr_o[1]),
.O(\wr_en[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000020000))
\wr_en[4]_i_1
(.I0(xsdb_wr),
.I1(\wr_en_reg[4]_0 ),
.I2(\wr_en_reg[4]_2 ),
.I3(\wr_en_reg[4]_1 ),
.I4(s_daddr_o[2]),
.I5(\wr_en[4]_i_6_n_0 ),
.O(\wr_en[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h8))
\wr_en[4]_i_2
(.I0(s_den_o),
.I1(s_dwe_o),
.O(xsdb_wr));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\wr_en[4]_i_3
(.I0(s_daddr_o[15]),
.I1(s_daddr_o[16]),
.I2(s_daddr_o[13]),
.I3(s_daddr_o[14]),
.I4(s_daddr_o[4]),
.I5(s_daddr_o[3]),
.O(\wr_en_reg[4]_0 ));
LUT4 #(
.INIT(16'hFFFE))
\wr_en[4]_i_4
(.I0(s_daddr_o[6]),
.I1(s_daddr_o[5]),
.I2(s_daddr_o[8]),
.I3(s_daddr_o[7]),
.O(\wr_en_reg[4]_2 ));
LUT4 #(
.INIT(16'hFFFE))
\wr_en[4]_i_5
(.I0(s_daddr_o[10]),
.I1(s_daddr_o[9]),
.I2(s_daddr_o[12]),
.I3(s_daddr_o[11]),
.O(\wr_en_reg[4]_1 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT2 #(
.INIT(4'hE))
\wr_en[4]_i_6
(.I0(s_daddr_o[0]),
.I1(s_daddr_o[1]),
.O(\wr_en[4]_i_6_n_0 ));
FDRE \wr_en_reg[2]
(.C(out),
.CE(1'b1),
.D(\wr_en[2]_i_1_n_0 ),
.Q(wr_control_reg),
.R(1'b0));
FDRE \wr_en_reg[4]
(.C(out),
.CE(1'b1),
.D(\wr_en[4]_i_1_n_0 ),
.Q(wr_probe_out_modified),
.R(1'b0));
FDRE \xsdb_addr_2_0_p1_reg[0]
(.C(out),
.CE(1'b1),
.D(s_daddr_o[0]),
.Q(xsdb_addr_2_0_p1[0]),
.R(1'b0));
FDRE \xsdb_addr_2_0_p1_reg[1]
(.C(out),
.CE(1'b1),
.D(s_daddr_o[1]),
.Q(xsdb_addr_2_0_p1[1]),
.R(1'b0));
FDRE \xsdb_addr_2_0_p1_reg[2]
(.C(out),
.CE(1'b1),
.D(s_daddr_o[2]),
.Q(xsdb_addr_2_0_p1[2]),
.R(1'b0));
FDRE \xsdb_addr_2_0_p2_reg[0]
(.C(out),
.CE(1'b1),
.D(xsdb_addr_2_0_p1[0]),
.Q(xsdb_addr_2_0_p2[0]),
.R(1'b0));
FDRE \xsdb_addr_2_0_p2_reg[1]
(.C(out),
.CE(1'b1),
.D(xsdb_addr_2_0_p1[1]),
.Q(xsdb_addr_2_0_p2[1]),
.R(1'b0));
FDRE \xsdb_addr_2_0_p2_reg[2]
(.C(out),
.CE(1'b1),
.D(xsdb_addr_2_0_p1[2]),
.Q(xsdb_addr_2_0_p2[2]),
.R(1'b0));
FDRE xsdb_addr_8_p1_reg
(.C(out),
.CE(1'b1),
.D(s_daddr_o[8]),
.Q(xsdb_addr_8_p1),
.R(1'b0));
FDRE xsdb_addr_8_p2_reg
(.C(out),
.CE(1'b1),
.D(xsdb_addr_8_p1),
.Q(xsdb_addr_8_p2),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hF8))
xsdb_drdy_i_1
(.I0(s_dwe_o),
.I1(s_den_o),
.I2(rd_en_p2),
.O(xsdb_drdy_i_1_n_0));
FDRE xsdb_drdy_reg
(.C(out),
.CE(1'b1),
.D(xsdb_drdy_i_1_n_0),
.Q(s_drdy_i),
.R(s_rst_o));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_probe_in_one
(Q,
out,
\wr_en[4]_i_3 ,
\wr_en[4]_i_4 ,
\wr_en[4]_i_5 ,
s_daddr_o,
s_dwe_o,
s_den_o,
E,
D,
clk,
s_rst_o);
output [8:0]Q;
input out;
input \wr_en[4]_i_3 ;
input \wr_en[4]_i_4 ;
input \wr_en[4]_i_5 ;
input [2:0]s_daddr_o;
input s_dwe_o;
input s_den_o;
input [0:0]E;
input [2:0]D;
input clk;
input s_rst_o;
wire [2:0]D;
wire \DECODER_INST/rd_en_int_7 ;
wire [0:0]E;
wire [8:0]Q;
wire Read_int;
wire Read_int_i_2_n_0;
wire clk;
(* async_reg = "true" *) wire [2:0]data_int_sync1;
(* async_reg = "true" *) wire [2:0]data_int_sync2;
wire \dn_activity[0]_i_1_n_0 ;
wire \dn_activity[1]_i_1_n_0 ;
wire \dn_activity[2]_i_1_n_0 ;
wire \dn_activity_reg_n_0_[0] ;
wire \dn_activity_reg_n_0_[2] ;
wire out;
wire p_6_in;
(* DONT_TOUCH *) wire [2:0]probe_in_reg;
(* MAX_FANOUT = "200" *) (* RTL_MAX_FANOUT = "found" *) wire read_done;
wire read_done_i_1_n_0;
wire [2:0]s_daddr_o;
wire s_den_o;
wire s_dwe_o;
wire s_rst_o;
wire \up_activity[0]_i_1_n_0 ;
wire \up_activity[1]_i_1_n_0 ;
wire \up_activity[2]_i_1_n_0 ;
wire \up_activity_reg_n_0_[0] ;
wire \up_activity_reg_n_0_[1] ;
wire \up_activity_reg_n_0_[2] ;
wire \wr_en[4]_i_3 ;
wire \wr_en[4]_i_4 ;
wire \wr_en[4]_i_5 ;
FDRE \Bus_Data_out_reg[0]
(.C(out),
.CE(1'b1),
.D(data_int_sync2[0]),
.Q(Q[0]),
.R(1'b0));
FDRE \Bus_Data_out_reg[1]
(.C(out),
.CE(1'b1),
.D(data_int_sync2[1]),
.Q(Q[1]),
.R(1'b0));
FDRE \Bus_Data_out_reg[2]
(.C(out),
.CE(1'b1),
.D(data_int_sync2[2]),
.Q(Q[2]),
.R(1'b0));
FDRE \Bus_Data_out_reg[3]
(.C(out),
.CE(1'b1),
.D(\up_activity_reg_n_0_[0] ),
.Q(Q[3]),
.R(1'b0));
FDRE \Bus_Data_out_reg[4]
(.C(out),
.CE(1'b1),
.D(\up_activity_reg_n_0_[1] ),
.Q(Q[4]),
.R(1'b0));
FDRE \Bus_Data_out_reg[5]
(.C(out),
.CE(1'b1),
.D(\up_activity_reg_n_0_[2] ),
.Q(Q[5]),
.R(1'b0));
FDRE \Bus_Data_out_reg[6]
(.C(out),
.CE(1'b1),
.D(\dn_activity_reg_n_0_[0] ),
.Q(Q[6]),
.R(1'b0));
FDRE \Bus_Data_out_reg[7]
(.C(out),
.CE(1'b1),
.D(p_6_in),
.Q(Q[7]),
.R(1'b0));
FDRE \Bus_Data_out_reg[8]
(.C(out),
.CE(1'b1),
.D(\dn_activity_reg_n_0_[2] ),
.Q(Q[8]),
.R(1'b0));
LUT4 #(
.INIT(16'h0002))
Read_int_i_1
(.I0(Read_int_i_2_n_0),
.I1(\wr_en[4]_i_3 ),
.I2(\wr_en[4]_i_4 ),
.I3(\wr_en[4]_i_5 ),
.O(\DECODER_INST/rd_en_int_7 ));
LUT5 #(
.INIT(32'h00800000))
Read_int_i_2
(.I0(s_daddr_o[0]),
.I1(s_daddr_o[1]),
.I2(s_daddr_o[2]),
.I3(s_dwe_o),
.I4(s_den_o),
.O(Read_int_i_2_n_0));
FDRE Read_int_reg
(.C(out),
.CE(1'b1),
.D(\DECODER_INST/rd_en_int_7 ),
.Q(Read_int),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\data_int_sync1_reg[0]
(.C(out),
.CE(1'b1),
.D(probe_in_reg[0]),
.Q(data_int_sync1[0]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\data_int_sync1_reg[1]
(.C(out),
.CE(1'b1),
.D(probe_in_reg[1]),
.Q(data_int_sync1[1]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\data_int_sync1_reg[2]
(.C(out),
.CE(1'b1),
.D(probe_in_reg[2]),
.Q(data_int_sync1[2]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\data_int_sync2_reg[0]
(.C(out),
.CE(1'b1),
.D(data_int_sync1[0]),
.Q(data_int_sync2[0]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\data_int_sync2_reg[1]
(.C(out),
.CE(1'b1),
.D(data_int_sync1[1]),
.Q(data_int_sync2[1]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\data_int_sync2_reg[2]
(.C(out),
.CE(1'b1),
.D(data_int_sync1[2]),
.Q(data_int_sync2[2]),
.R(1'b0));
LUT3 #(
.INIT(8'hBA))
\dn_activity[0]_i_1
(.I0(\dn_activity_reg_n_0_[0] ),
.I1(data_int_sync1[0]),
.I2(data_int_sync2[0]),
.O(\dn_activity[0]_i_1_n_0 ));
LUT3 #(
.INIT(8'hBA))
\dn_activity[1]_i_1
(.I0(p_6_in),
.I1(data_int_sync1[1]),
.I2(data_int_sync2[1]),
.O(\dn_activity[1]_i_1_n_0 ));
LUT3 #(
.INIT(8'hBA))
\dn_activity[2]_i_1
(.I0(\dn_activity_reg_n_0_[2] ),
.I1(data_int_sync1[2]),
.I2(data_int_sync2[2]),
.O(\dn_activity[2]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\dn_activity_reg[0]
(.C(out),
.CE(1'b1),
.D(\dn_activity[0]_i_1_n_0 ),
.Q(\dn_activity_reg_n_0_[0] ),
.R(read_done));
FDRE #(
.INIT(1'b0))
\dn_activity_reg[1]
(.C(out),
.CE(1'b1),
.D(\dn_activity[1]_i_1_n_0 ),
.Q(p_6_in),
.R(read_done));
FDRE #(
.INIT(1'b0))
\dn_activity_reg[2]
(.C(out),
.CE(1'b1),
.D(\dn_activity[2]_i_1_n_0 ),
.Q(\dn_activity_reg_n_0_[2] ),
.R(read_done));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\probe_in_reg_reg[0]
(.C(clk),
.CE(E),
.D(D[0]),
.Q(probe_in_reg[0]),
.R(1'b0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\probe_in_reg_reg[1]
(.C(clk),
.CE(E),
.D(D[1]),
.Q(probe_in_reg[1]),
.R(1'b0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\probe_in_reg_reg[2]
(.C(clk),
.CE(E),
.D(D[2]),
.Q(probe_in_reg[2]),
.R(1'b0));
LUT3 #(
.INIT(8'h02))
read_done_i_1
(.I0(Read_int),
.I1(read_done),
.I2(s_rst_o),
.O(read_done_i_1_n_0));
(* RTL_MAX_FANOUT = "found" *)
FDRE read_done_reg
(.C(out),
.CE(1'b1),
.D(read_done_i_1_n_0),
.Q(read_done),
.R(1'b0));
LUT3 #(
.INIT(8'hBA))
\up_activity[0]_i_1
(.I0(\up_activity_reg_n_0_[0] ),
.I1(data_int_sync2[0]),
.I2(data_int_sync1[0]),
.O(\up_activity[0]_i_1_n_0 ));
LUT3 #(
.INIT(8'hBA))
\up_activity[1]_i_1
(.I0(\up_activity_reg_n_0_[1] ),
.I1(data_int_sync2[1]),
.I2(data_int_sync1[1]),
.O(\up_activity[1]_i_1_n_0 ));
LUT3 #(
.INIT(8'hBA))
\up_activity[2]_i_1
(.I0(\up_activity_reg_n_0_[2] ),
.I1(data_int_sync2[2]),
.I2(data_int_sync1[2]),
.O(\up_activity[2]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\up_activity_reg[0]
(.C(out),
.CE(1'b1),
.D(\up_activity[0]_i_1_n_0 ),
.Q(\up_activity_reg_n_0_[0] ),
.R(read_done));
FDRE #(
.INIT(1'b0))
\up_activity_reg[1]
(.C(out),
.CE(1'b1),
.D(\up_activity[1]_i_1_n_0 ),
.Q(\up_activity_reg_n_0_[1] ),
.R(read_done));
FDRE #(
.INIT(1'b0))
\up_activity_reg[2]
(.C(out),
.CE(1'b1),
.D(\up_activity[2]_i_1_n_0 ),
.Q(\up_activity_reg_n_0_[2] ),
.R(read_done));
endmodule
(* C_BUILD_REVISION = "0" *) (* C_BUS_ADDR_WIDTH = "17" *) (* C_BUS_DATA_WIDTH = "16" *)
(* C_CORE_INFO1 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_CORE_INFO2 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_CORE_MAJOR_VER = "2" *)
(* C_CORE_MINOR_ALPHA_VER = "97" *) (* C_CORE_MINOR_VER = "0" *) (* C_CORE_TYPE = "2" *)
(* C_CSE_DRV_VER = "1" *) (* C_EN_PROBE_IN_ACTIVITY = "1" *) (* C_EN_SYNCHRONIZATION = "1" *)
(* C_MAJOR_VERSION = "2013" *) (* C_MAX_NUM_PROBE = "256" *) (* C_MAX_WIDTH_PER_PROBE = "256" *)
(* C_MINOR_VERSION = "1" *) (* C_NEXT_SLAVE = "0" *) (* C_NUM_PROBE_IN = "3" *)
(* C_NUM_PROBE_OUT = "0" *) (* C_PIPE_IFACE = "0" *) (* C_PROBE_IN0_WIDTH = "1" *)
(* C_PROBE_IN100_WIDTH = "1" *) (* C_PROBE_IN101_WIDTH = "1" *) (* C_PROBE_IN102_WIDTH = "1" *)
(* C_PROBE_IN103_WIDTH = "1" *) (* C_PROBE_IN104_WIDTH = "1" *) (* C_PROBE_IN105_WIDTH = "1" *)
(* C_PROBE_IN106_WIDTH = "1" *) (* C_PROBE_IN107_WIDTH = "1" *) (* C_PROBE_IN108_WIDTH = "1" *)
(* C_PROBE_IN109_WIDTH = "1" *) (* C_PROBE_IN10_WIDTH = "1" *) (* C_PROBE_IN110_WIDTH = "1" *)
(* C_PROBE_IN111_WIDTH = "1" *) (* C_PROBE_IN112_WIDTH = "1" *) (* C_PROBE_IN113_WIDTH = "1" *)
(* C_PROBE_IN114_WIDTH = "1" *) (* C_PROBE_IN115_WIDTH = "1" *) (* C_PROBE_IN116_WIDTH = "1" *)
(* C_PROBE_IN117_WIDTH = "1" *) (* C_PROBE_IN118_WIDTH = "1" *) (* C_PROBE_IN119_WIDTH = "1" *)
(* C_PROBE_IN11_WIDTH = "1" *) (* C_PROBE_IN120_WIDTH = "1" *) (* C_PROBE_IN121_WIDTH = "1" *)
(* C_PROBE_IN122_WIDTH = "1" *) (* C_PROBE_IN123_WIDTH = "1" *) (* C_PROBE_IN124_WIDTH = "1" *)
(* C_PROBE_IN125_WIDTH = "1" *) (* C_PROBE_IN126_WIDTH = "1" *) (* C_PROBE_IN127_WIDTH = "1" *)
(* C_PROBE_IN128_WIDTH = "1" *) (* C_PROBE_IN129_WIDTH = "1" *) (* C_PROBE_IN12_WIDTH = "1" *)
(* C_PROBE_IN130_WIDTH = "1" *) (* C_PROBE_IN131_WIDTH = "1" *) (* C_PROBE_IN132_WIDTH = "1" *)
(* C_PROBE_IN133_WIDTH = "1" *) (* C_PROBE_IN134_WIDTH = "1" *) (* C_PROBE_IN135_WIDTH = "1" *)
(* C_PROBE_IN136_WIDTH = "1" *) (* C_PROBE_IN137_WIDTH = "1" *) (* C_PROBE_IN138_WIDTH = "1" *)
(* C_PROBE_IN139_WIDTH = "1" *) (* C_PROBE_IN13_WIDTH = "1" *) (* C_PROBE_IN140_WIDTH = "1" *)
(* C_PROBE_IN141_WIDTH = "1" *) (* C_PROBE_IN142_WIDTH = "1" *) (* C_PROBE_IN143_WIDTH = "1" *)
(* C_PROBE_IN144_WIDTH = "1" *) (* C_PROBE_IN145_WIDTH = "1" *) (* C_PROBE_IN146_WIDTH = "1" *)
(* C_PROBE_IN147_WIDTH = "1" *) (* C_PROBE_IN148_WIDTH = "1" *) (* C_PROBE_IN149_WIDTH = "1" *)
(* C_PROBE_IN14_WIDTH = "1" *) (* C_PROBE_IN150_WIDTH = "1" *) (* C_PROBE_IN151_WIDTH = "1" *)
(* C_PROBE_IN152_WIDTH = "1" *) (* C_PROBE_IN153_WIDTH = "1" *) (* C_PROBE_IN154_WIDTH = "1" *)
(* C_PROBE_IN155_WIDTH = "1" *) (* C_PROBE_IN156_WIDTH = "1" *) (* C_PROBE_IN157_WIDTH = "1" *)
(* C_PROBE_IN158_WIDTH = "1" *) (* C_PROBE_IN159_WIDTH = "1" *) (* C_PROBE_IN15_WIDTH = "1" *)
(* C_PROBE_IN160_WIDTH = "1" *) (* C_PROBE_IN161_WIDTH = "1" *) (* C_PROBE_IN162_WIDTH = "1" *)
(* C_PROBE_IN163_WIDTH = "1" *) (* C_PROBE_IN164_WIDTH = "1" *) (* C_PROBE_IN165_WIDTH = "1" *)
(* C_PROBE_IN166_WIDTH = "1" *) (* C_PROBE_IN167_WIDTH = "1" *) (* C_PROBE_IN168_WIDTH = "1" *)
(* C_PROBE_IN169_WIDTH = "1" *) (* C_PROBE_IN16_WIDTH = "1" *) (* C_PROBE_IN170_WIDTH = "1" *)
(* C_PROBE_IN171_WIDTH = "1" *) (* C_PROBE_IN172_WIDTH = "1" *) (* C_PROBE_IN173_WIDTH = "1" *)
(* C_PROBE_IN174_WIDTH = "1" *) (* C_PROBE_IN175_WIDTH = "1" *) (* C_PROBE_IN176_WIDTH = "1" *)
(* C_PROBE_IN177_WIDTH = "1" *) (* C_PROBE_IN178_WIDTH = "1" *) (* C_PROBE_IN179_WIDTH = "1" *)
(* C_PROBE_IN17_WIDTH = "1" *) (* C_PROBE_IN180_WIDTH = "1" *) (* C_PROBE_IN181_WIDTH = "1" *)
(* C_PROBE_IN182_WIDTH = "1" *) (* C_PROBE_IN183_WIDTH = "1" *) (* C_PROBE_IN184_WIDTH = "1" *)
(* C_PROBE_IN185_WIDTH = "1" *) (* C_PROBE_IN186_WIDTH = "1" *) (* C_PROBE_IN187_WIDTH = "1" *)
(* C_PROBE_IN188_WIDTH = "1" *) (* C_PROBE_IN189_WIDTH = "1" *) (* C_PROBE_IN18_WIDTH = "1" *)
(* C_PROBE_IN190_WIDTH = "1" *) (* C_PROBE_IN191_WIDTH = "1" *) (* C_PROBE_IN192_WIDTH = "1" *)
(* C_PROBE_IN193_WIDTH = "1" *) (* C_PROBE_IN194_WIDTH = "1" *) (* C_PROBE_IN195_WIDTH = "1" *)
(* C_PROBE_IN196_WIDTH = "1" *) (* C_PROBE_IN197_WIDTH = "1" *) (* C_PROBE_IN198_WIDTH = "1" *)
(* C_PROBE_IN199_WIDTH = "1" *) (* C_PROBE_IN19_WIDTH = "1" *) (* C_PROBE_IN1_WIDTH = "1" *)
(* C_PROBE_IN200_WIDTH = "1" *) (* C_PROBE_IN201_WIDTH = "1" *) (* C_PROBE_IN202_WIDTH = "1" *)
(* C_PROBE_IN203_WIDTH = "1" *) (* C_PROBE_IN204_WIDTH = "1" *) (* C_PROBE_IN205_WIDTH = "1" *)
(* C_PROBE_IN206_WIDTH = "1" *) (* C_PROBE_IN207_WIDTH = "1" *) (* C_PROBE_IN208_WIDTH = "1" *)
(* C_PROBE_IN209_WIDTH = "1" *) (* C_PROBE_IN20_WIDTH = "1" *) (* C_PROBE_IN210_WIDTH = "1" *)
(* C_PROBE_IN211_WIDTH = "1" *) (* C_PROBE_IN212_WIDTH = "1" *) (* C_PROBE_IN213_WIDTH = "1" *)
(* C_PROBE_IN214_WIDTH = "1" *) (* C_PROBE_IN215_WIDTH = "1" *) (* C_PROBE_IN216_WIDTH = "1" *)
(* C_PROBE_IN217_WIDTH = "1" *) (* C_PROBE_IN218_WIDTH = "1" *) (* C_PROBE_IN219_WIDTH = "1" *)
(* C_PROBE_IN21_WIDTH = "1" *) (* C_PROBE_IN220_WIDTH = "1" *) (* C_PROBE_IN221_WIDTH = "1" *)
(* C_PROBE_IN222_WIDTH = "1" *) (* C_PROBE_IN223_WIDTH = "1" *) (* C_PROBE_IN224_WIDTH = "1" *)
(* C_PROBE_IN225_WIDTH = "1" *) (* C_PROBE_IN226_WIDTH = "1" *) (* C_PROBE_IN227_WIDTH = "1" *)
(* C_PROBE_IN228_WIDTH = "1" *) (* C_PROBE_IN229_WIDTH = "1" *) (* C_PROBE_IN22_WIDTH = "1" *)
(* C_PROBE_IN230_WIDTH = "1" *) (* C_PROBE_IN231_WIDTH = "1" *) (* C_PROBE_IN232_WIDTH = "1" *)
(* C_PROBE_IN233_WIDTH = "1" *) (* C_PROBE_IN234_WIDTH = "1" *) (* C_PROBE_IN235_WIDTH = "1" *)
(* C_PROBE_IN236_WIDTH = "1" *) (* C_PROBE_IN237_WIDTH = "1" *) (* C_PROBE_IN238_WIDTH = "1" *)
(* C_PROBE_IN239_WIDTH = "1" *) (* C_PROBE_IN23_WIDTH = "1" *) (* C_PROBE_IN240_WIDTH = "1" *)
(* C_PROBE_IN241_WIDTH = "1" *) (* C_PROBE_IN242_WIDTH = "1" *) (* C_PROBE_IN243_WIDTH = "1" *)
(* C_PROBE_IN244_WIDTH = "1" *) (* C_PROBE_IN245_WIDTH = "1" *) (* C_PROBE_IN246_WIDTH = "1" *)
(* C_PROBE_IN247_WIDTH = "1" *) (* C_PROBE_IN248_WIDTH = "1" *) (* C_PROBE_IN249_WIDTH = "1" *)
(* C_PROBE_IN24_WIDTH = "1" *) (* C_PROBE_IN250_WIDTH = "1" *) (* C_PROBE_IN251_WIDTH = "1" *)
(* C_PROBE_IN252_WIDTH = "1" *) (* C_PROBE_IN253_WIDTH = "1" *) (* C_PROBE_IN254_WIDTH = "1" *)
(* C_PROBE_IN255_WIDTH = "1" *) (* C_PROBE_IN25_WIDTH = "1" *) (* C_PROBE_IN26_WIDTH = "1" *)
(* C_PROBE_IN27_WIDTH = "1" *) (* C_PROBE_IN28_WIDTH = "1" *) (* C_PROBE_IN29_WIDTH = "1" *)
(* C_PROBE_IN2_WIDTH = "1" *) (* C_PROBE_IN30_WIDTH = "1" *) (* C_PROBE_IN31_WIDTH = "1" *)
(* C_PROBE_IN32_WIDTH = "1" *) (* C_PROBE_IN33_WIDTH = "1" *) (* C_PROBE_IN34_WIDTH = "1" *)
(* C_PROBE_IN35_WIDTH = "1" *) (* C_PROBE_IN36_WIDTH = "1" *) (* C_PROBE_IN37_WIDTH = "1" *)
(* C_PROBE_IN38_WIDTH = "1" *) (* C_PROBE_IN39_WIDTH = "1" *) (* C_PROBE_IN3_WIDTH = "1" *)
(* C_PROBE_IN40_WIDTH = "1" *) (* C_PROBE_IN41_WIDTH = "1" *) (* C_PROBE_IN42_WIDTH = "1" *)
(* C_PROBE_IN43_WIDTH = "1" *) (* C_PROBE_IN44_WIDTH = "1" *) (* C_PROBE_IN45_WIDTH = "1" *)
(* C_PROBE_IN46_WIDTH = "1" *) (* C_PROBE_IN47_WIDTH = "1" *) (* C_PROBE_IN48_WIDTH = "1" *)
(* C_PROBE_IN49_WIDTH = "1" *) (* C_PROBE_IN4_WIDTH = "1" *) (* C_PROBE_IN50_WIDTH = "1" *)
(* C_PROBE_IN51_WIDTH = "1" *) (* C_PROBE_IN52_WIDTH = "1" *) (* C_PROBE_IN53_WIDTH = "1" *)
(* C_PROBE_IN54_WIDTH = "1" *) (* C_PROBE_IN55_WIDTH = "1" *) (* C_PROBE_IN56_WIDTH = "1" *)
(* C_PROBE_IN57_WIDTH = "1" *) (* C_PROBE_IN58_WIDTH = "1" *) (* C_PROBE_IN59_WIDTH = "1" *)
(* C_PROBE_IN5_WIDTH = "1" *) (* C_PROBE_IN60_WIDTH = "1" *) (* C_PROBE_IN61_WIDTH = "1" *)
(* C_PROBE_IN62_WIDTH = "1" *) (* C_PROBE_IN63_WIDTH = "1" *) (* C_PROBE_IN64_WIDTH = "1" *)
(* C_PROBE_IN65_WIDTH = "1" *) (* C_PROBE_IN66_WIDTH = "1" *) (* C_PROBE_IN67_WIDTH = "1" *)
(* C_PROBE_IN68_WIDTH = "1" *) (* C_PROBE_IN69_WIDTH = "1" *) (* C_PROBE_IN6_WIDTH = "1" *)
(* C_PROBE_IN70_WIDTH = "1" *) (* C_PROBE_IN71_WIDTH = "1" *) (* C_PROBE_IN72_WIDTH = "1" *)
(* C_PROBE_IN73_WIDTH = "1" *) (* C_PROBE_IN74_WIDTH = "1" *) (* C_PROBE_IN75_WIDTH = "1" *)
(* C_PROBE_IN76_WIDTH = "1" *) (* C_PROBE_IN77_WIDTH = "1" *) (* C_PROBE_IN78_WIDTH = "1" *)
(* C_PROBE_IN79_WIDTH = "1" *) (* C_PROBE_IN7_WIDTH = "1" *) (* C_PROBE_IN80_WIDTH = "1" *)
(* C_PROBE_IN81_WIDTH = "1" *) (* C_PROBE_IN82_WIDTH = "1" *) (* C_PROBE_IN83_WIDTH = "1" *)
(* C_PROBE_IN84_WIDTH = "1" *) (* C_PROBE_IN85_WIDTH = "1" *) (* C_PROBE_IN86_WIDTH = "1" *)
(* C_PROBE_IN87_WIDTH = "1" *) (* C_PROBE_IN88_WIDTH = "1" *) (* C_PROBE_IN89_WIDTH = "1" *)
(* C_PROBE_IN8_WIDTH = "1" *) (* C_PROBE_IN90_WIDTH = "1" *) (* C_PROBE_IN91_WIDTH = "1" *)
(* C_PROBE_IN92_WIDTH = "1" *) (* C_PROBE_IN93_WIDTH = "1" *) (* C_PROBE_IN94_WIDTH = "1" *)
(* C_PROBE_IN95_WIDTH = "1" *) (* C_PROBE_IN96_WIDTH = "1" *) (* C_PROBE_IN97_WIDTH = "1" *)
(* C_PROBE_IN98_WIDTH = "1" *) (* C_PROBE_IN99_WIDTH = "1" *) (* C_PROBE_IN9_WIDTH = "1" *)
(* C_PROBE_OUT0_INIT_VAL = "1'b0" *) (* C_PROBE_OUT0_WIDTH = "1" *) (* C_PROBE_OUT100_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT100_WIDTH = "1" *) (* C_PROBE_OUT101_INIT_VAL = "1'b0" *) (* C_PROBE_OUT101_WIDTH = "1" *)
(* C_PROBE_OUT102_INIT_VAL = "1'b0" *) (* C_PROBE_OUT102_WIDTH = "1" *) (* C_PROBE_OUT103_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT103_WIDTH = "1" *) (* C_PROBE_OUT104_INIT_VAL = "1'b0" *) (* C_PROBE_OUT104_WIDTH = "1" *)
(* C_PROBE_OUT105_INIT_VAL = "1'b0" *) (* C_PROBE_OUT105_WIDTH = "1" *) (* C_PROBE_OUT106_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT106_WIDTH = "1" *) (* C_PROBE_OUT107_INIT_VAL = "1'b0" *) (* C_PROBE_OUT107_WIDTH = "1" *)
(* C_PROBE_OUT108_INIT_VAL = "1'b0" *) (* C_PROBE_OUT108_WIDTH = "1" *) (* C_PROBE_OUT109_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT109_WIDTH = "1" *) (* C_PROBE_OUT10_INIT_VAL = "1'b0" *) (* C_PROBE_OUT10_WIDTH = "1" *)
(* C_PROBE_OUT110_INIT_VAL = "1'b0" *) (* C_PROBE_OUT110_WIDTH = "1" *) (* C_PROBE_OUT111_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT111_WIDTH = "1" *) (* C_PROBE_OUT112_INIT_VAL = "1'b0" *) (* C_PROBE_OUT112_WIDTH = "1" *)
(* C_PROBE_OUT113_INIT_VAL = "1'b0" *) (* C_PROBE_OUT113_WIDTH = "1" *) (* C_PROBE_OUT114_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT114_WIDTH = "1" *) (* C_PROBE_OUT115_INIT_VAL = "1'b0" *) (* C_PROBE_OUT115_WIDTH = "1" *)
(* C_PROBE_OUT116_INIT_VAL = "1'b0" *) (* C_PROBE_OUT116_WIDTH = "1" *) (* C_PROBE_OUT117_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT117_WIDTH = "1" *) (* C_PROBE_OUT118_INIT_VAL = "1'b0" *) (* C_PROBE_OUT118_WIDTH = "1" *)
(* C_PROBE_OUT119_INIT_VAL = "1'b0" *) (* C_PROBE_OUT119_WIDTH = "1" *) (* C_PROBE_OUT11_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT11_WIDTH = "1" *) (* C_PROBE_OUT120_INIT_VAL = "1'b0" *) (* C_PROBE_OUT120_WIDTH = "1" *)
(* C_PROBE_OUT121_INIT_VAL = "1'b0" *) (* C_PROBE_OUT121_WIDTH = "1" *) (* C_PROBE_OUT122_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT122_WIDTH = "1" *) (* C_PROBE_OUT123_INIT_VAL = "1'b0" *) (* C_PROBE_OUT123_WIDTH = "1" *)
(* C_PROBE_OUT124_INIT_VAL = "1'b0" *) (* C_PROBE_OUT124_WIDTH = "1" *) (* C_PROBE_OUT125_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT125_WIDTH = "1" *) (* C_PROBE_OUT126_INIT_VAL = "1'b0" *) (* C_PROBE_OUT126_WIDTH = "1" *)
(* C_PROBE_OUT127_INIT_VAL = "1'b0" *) (* C_PROBE_OUT127_WIDTH = "1" *) (* C_PROBE_OUT128_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT128_WIDTH = "1" *) (* C_PROBE_OUT129_INIT_VAL = "1'b0" *) (* C_PROBE_OUT129_WIDTH = "1" *)
(* C_PROBE_OUT12_INIT_VAL = "1'b0" *) (* C_PROBE_OUT12_WIDTH = "1" *) (* C_PROBE_OUT130_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT130_WIDTH = "1" *) (* C_PROBE_OUT131_INIT_VAL = "1'b0" *) (* C_PROBE_OUT131_WIDTH = "1" *)
(* C_PROBE_OUT132_INIT_VAL = "1'b0" *) (* C_PROBE_OUT132_WIDTH = "1" *) (* C_PROBE_OUT133_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT133_WIDTH = "1" *) (* C_PROBE_OUT134_INIT_VAL = "1'b0" *) (* C_PROBE_OUT134_WIDTH = "1" *)
(* C_PROBE_OUT135_INIT_VAL = "1'b0" *) (* C_PROBE_OUT135_WIDTH = "1" *) (* C_PROBE_OUT136_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT136_WIDTH = "1" *) (* C_PROBE_OUT137_INIT_VAL = "1'b0" *) (* C_PROBE_OUT137_WIDTH = "1" *)
(* C_PROBE_OUT138_INIT_VAL = "1'b0" *) (* C_PROBE_OUT138_WIDTH = "1" *) (* C_PROBE_OUT139_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT139_WIDTH = "1" *) (* C_PROBE_OUT13_INIT_VAL = "1'b0" *) (* C_PROBE_OUT13_WIDTH = "1" *)
(* C_PROBE_OUT140_INIT_VAL = "1'b0" *) (* C_PROBE_OUT140_WIDTH = "1" *) (* C_PROBE_OUT141_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT141_WIDTH = "1" *) (* C_PROBE_OUT142_INIT_VAL = "1'b0" *) (* C_PROBE_OUT142_WIDTH = "1" *)
(* C_PROBE_OUT143_INIT_VAL = "1'b0" *) (* C_PROBE_OUT143_WIDTH = "1" *) (* C_PROBE_OUT144_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT144_WIDTH = "1" *) (* C_PROBE_OUT145_INIT_VAL = "1'b0" *) (* C_PROBE_OUT145_WIDTH = "1" *)
(* C_PROBE_OUT146_INIT_VAL = "1'b0" *) (* C_PROBE_OUT146_WIDTH = "1" *) (* C_PROBE_OUT147_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT147_WIDTH = "1" *) (* C_PROBE_OUT148_INIT_VAL = "1'b0" *) (* C_PROBE_OUT148_WIDTH = "1" *)
(* C_PROBE_OUT149_INIT_VAL = "1'b0" *) (* C_PROBE_OUT149_WIDTH = "1" *) (* C_PROBE_OUT14_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT14_WIDTH = "1" *) (* C_PROBE_OUT150_INIT_VAL = "1'b0" *) (* C_PROBE_OUT150_WIDTH = "1" *)
(* C_PROBE_OUT151_INIT_VAL = "1'b0" *) (* C_PROBE_OUT151_WIDTH = "1" *) (* C_PROBE_OUT152_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT152_WIDTH = "1" *) (* C_PROBE_OUT153_INIT_VAL = "1'b0" *) (* C_PROBE_OUT153_WIDTH = "1" *)
(* C_PROBE_OUT154_INIT_VAL = "1'b0" *) (* C_PROBE_OUT154_WIDTH = "1" *) (* C_PROBE_OUT155_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT155_WIDTH = "1" *) (* C_PROBE_OUT156_INIT_VAL = "1'b0" *) (* C_PROBE_OUT156_WIDTH = "1" *)
(* C_PROBE_OUT157_INIT_VAL = "1'b0" *) (* C_PROBE_OUT157_WIDTH = "1" *) (* C_PROBE_OUT158_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT158_WIDTH = "1" *) (* C_PROBE_OUT159_INIT_VAL = "1'b0" *) (* C_PROBE_OUT159_WIDTH = "1" *)
(* C_PROBE_OUT15_INIT_VAL = "1'b0" *) (* C_PROBE_OUT15_WIDTH = "1" *) (* C_PROBE_OUT160_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT160_WIDTH = "1" *) (* C_PROBE_OUT161_INIT_VAL = "1'b0" *) (* C_PROBE_OUT161_WIDTH = "1" *)
(* C_PROBE_OUT162_INIT_VAL = "1'b0" *) (* C_PROBE_OUT162_WIDTH = "1" *) (* C_PROBE_OUT163_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT163_WIDTH = "1" *) (* C_PROBE_OUT164_INIT_VAL = "1'b0" *) (* C_PROBE_OUT164_WIDTH = "1" *)
(* C_PROBE_OUT165_INIT_VAL = "1'b0" *) (* C_PROBE_OUT165_WIDTH = "1" *) (* C_PROBE_OUT166_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT166_WIDTH = "1" *) (* C_PROBE_OUT167_INIT_VAL = "1'b0" *) (* C_PROBE_OUT167_WIDTH = "1" *)
(* C_PROBE_OUT168_INIT_VAL = "1'b0" *) (* C_PROBE_OUT168_WIDTH = "1" *) (* C_PROBE_OUT169_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT169_WIDTH = "1" *) (* C_PROBE_OUT16_INIT_VAL = "1'b0" *) (* C_PROBE_OUT16_WIDTH = "1" *)
(* C_PROBE_OUT170_INIT_VAL = "1'b0" *) (* C_PROBE_OUT170_WIDTH = "1" *) (* C_PROBE_OUT171_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT171_WIDTH = "1" *) (* C_PROBE_OUT172_INIT_VAL = "1'b0" *) (* C_PROBE_OUT172_WIDTH = "1" *)
(* C_PROBE_OUT173_INIT_VAL = "1'b0" *) (* C_PROBE_OUT173_WIDTH = "1" *) (* C_PROBE_OUT174_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT174_WIDTH = "1" *) (* C_PROBE_OUT175_INIT_VAL = "1'b0" *) (* C_PROBE_OUT175_WIDTH = "1" *)
(* C_PROBE_OUT176_INIT_VAL = "1'b0" *) (* C_PROBE_OUT176_WIDTH = "1" *) (* C_PROBE_OUT177_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT177_WIDTH = "1" *) (* C_PROBE_OUT178_INIT_VAL = "1'b0" *) (* C_PROBE_OUT178_WIDTH = "1" *)
(* C_PROBE_OUT179_INIT_VAL = "1'b0" *) (* C_PROBE_OUT179_WIDTH = "1" *) (* C_PROBE_OUT17_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT17_WIDTH = "1" *) (* C_PROBE_OUT180_INIT_VAL = "1'b0" *) (* C_PROBE_OUT180_WIDTH = "1" *)
(* C_PROBE_OUT181_INIT_VAL = "1'b0" *) (* C_PROBE_OUT181_WIDTH = "1" *) (* C_PROBE_OUT182_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT182_WIDTH = "1" *) (* C_PROBE_OUT183_INIT_VAL = "1'b0" *) (* C_PROBE_OUT183_WIDTH = "1" *)
(* C_PROBE_OUT184_INIT_VAL = "1'b0" *) (* C_PROBE_OUT184_WIDTH = "1" *) (* C_PROBE_OUT185_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT185_WIDTH = "1" *) (* C_PROBE_OUT186_INIT_VAL = "1'b0" *) (* C_PROBE_OUT186_WIDTH = "1" *)
(* C_PROBE_OUT187_INIT_VAL = "1'b0" *) (* C_PROBE_OUT187_WIDTH = "1" *) (* C_PROBE_OUT188_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT188_WIDTH = "1" *) (* C_PROBE_OUT189_INIT_VAL = "1'b0" *) (* C_PROBE_OUT189_WIDTH = "1" *)
(* C_PROBE_OUT18_INIT_VAL = "1'b0" *) (* C_PROBE_OUT18_WIDTH = "1" *) (* C_PROBE_OUT190_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT190_WIDTH = "1" *) (* C_PROBE_OUT191_INIT_VAL = "1'b0" *) (* C_PROBE_OUT191_WIDTH = "1" *)
(* C_PROBE_OUT192_INIT_VAL = "1'b0" *) (* C_PROBE_OUT192_WIDTH = "1" *) (* C_PROBE_OUT193_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT193_WIDTH = "1" *) (* C_PROBE_OUT194_INIT_VAL = "1'b0" *) (* C_PROBE_OUT194_WIDTH = "1" *)
(* C_PROBE_OUT195_INIT_VAL = "1'b0" *) (* C_PROBE_OUT195_WIDTH = "1" *) (* C_PROBE_OUT196_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT196_WIDTH = "1" *) (* C_PROBE_OUT197_INIT_VAL = "1'b0" *) (* C_PROBE_OUT197_WIDTH = "1" *)
(* C_PROBE_OUT198_INIT_VAL = "1'b0" *) (* C_PROBE_OUT198_WIDTH = "1" *) (* C_PROBE_OUT199_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT199_WIDTH = "1" *) (* C_PROBE_OUT19_INIT_VAL = "1'b0" *) (* C_PROBE_OUT19_WIDTH = "1" *)
(* C_PROBE_OUT1_INIT_VAL = "1'b0" *) (* C_PROBE_OUT1_WIDTH = "1" *) (* C_PROBE_OUT200_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT200_WIDTH = "1" *) (* C_PROBE_OUT201_INIT_VAL = "1'b0" *) (* C_PROBE_OUT201_WIDTH = "1" *)
(* C_PROBE_OUT202_INIT_VAL = "1'b0" *) (* C_PROBE_OUT202_WIDTH = "1" *) (* C_PROBE_OUT203_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT203_WIDTH = "1" *) (* C_PROBE_OUT204_INIT_VAL = "1'b0" *) (* C_PROBE_OUT204_WIDTH = "1" *)
(* C_PROBE_OUT205_INIT_VAL = "1'b0" *) (* C_PROBE_OUT205_WIDTH = "1" *) (* C_PROBE_OUT206_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT206_WIDTH = "1" *) (* C_PROBE_OUT207_INIT_VAL = "1'b0" *) (* C_PROBE_OUT207_WIDTH = "1" *)
(* C_PROBE_OUT208_INIT_VAL = "1'b0" *) (* C_PROBE_OUT208_WIDTH = "1" *) (* C_PROBE_OUT209_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT209_WIDTH = "1" *) (* C_PROBE_OUT20_INIT_VAL = "1'b0" *) (* C_PROBE_OUT20_WIDTH = "1" *)
(* C_PROBE_OUT210_INIT_VAL = "1'b0" *) (* C_PROBE_OUT210_WIDTH = "1" *) (* C_PROBE_OUT211_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT211_WIDTH = "1" *) (* C_PROBE_OUT212_INIT_VAL = "1'b0" *) (* C_PROBE_OUT212_WIDTH = "1" *)
(* C_PROBE_OUT213_INIT_VAL = "1'b0" *) (* C_PROBE_OUT213_WIDTH = "1" *) (* C_PROBE_OUT214_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT214_WIDTH = "1" *) (* C_PROBE_OUT215_INIT_VAL = "1'b0" *) (* C_PROBE_OUT215_WIDTH = "1" *)
(* C_PROBE_OUT216_INIT_VAL = "1'b0" *) (* C_PROBE_OUT216_WIDTH = "1" *) (* C_PROBE_OUT217_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT217_WIDTH = "1" *) (* C_PROBE_OUT218_INIT_VAL = "1'b0" *) (* C_PROBE_OUT218_WIDTH = "1" *)
(* C_PROBE_OUT219_INIT_VAL = "1'b0" *) (* C_PROBE_OUT219_WIDTH = "1" *) (* C_PROBE_OUT21_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT21_WIDTH = "1" *) (* C_PROBE_OUT220_INIT_VAL = "1'b0" *) (* C_PROBE_OUT220_WIDTH = "1" *)
(* C_PROBE_OUT221_INIT_VAL = "1'b0" *) (* C_PROBE_OUT221_WIDTH = "1" *) (* C_PROBE_OUT222_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT222_WIDTH = "1" *) (* C_PROBE_OUT223_INIT_VAL = "1'b0" *) (* C_PROBE_OUT223_WIDTH = "1" *)
(* C_PROBE_OUT224_INIT_VAL = "1'b0" *) (* C_PROBE_OUT224_WIDTH = "1" *) (* C_PROBE_OUT225_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT225_WIDTH = "1" *) (* C_PROBE_OUT226_INIT_VAL = "1'b0" *) (* C_PROBE_OUT226_WIDTH = "1" *)
(* C_PROBE_OUT227_INIT_VAL = "1'b0" *) (* C_PROBE_OUT227_WIDTH = "1" *) (* C_PROBE_OUT228_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT228_WIDTH = "1" *) (* C_PROBE_OUT229_INIT_VAL = "1'b0" *) (* C_PROBE_OUT229_WIDTH = "1" *)
(* C_PROBE_OUT22_INIT_VAL = "1'b0" *) (* C_PROBE_OUT22_WIDTH = "1" *) (* C_PROBE_OUT230_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT230_WIDTH = "1" *) (* C_PROBE_OUT231_INIT_VAL = "1'b0" *) (* C_PROBE_OUT231_WIDTH = "1" *)
(* C_PROBE_OUT232_INIT_VAL = "1'b0" *) (* C_PROBE_OUT232_WIDTH = "1" *) (* C_PROBE_OUT233_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT233_WIDTH = "1" *) (* C_PROBE_OUT234_INIT_VAL = "1'b0" *) (* C_PROBE_OUT234_WIDTH = "1" *)
(* C_PROBE_OUT235_INIT_VAL = "1'b0" *) (* C_PROBE_OUT235_WIDTH = "1" *) (* C_PROBE_OUT236_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT236_WIDTH = "1" *) (* C_PROBE_OUT237_INIT_VAL = "1'b0" *) (* C_PROBE_OUT237_WIDTH = "1" *)
(* C_PROBE_OUT238_INIT_VAL = "1'b0" *) (* C_PROBE_OUT238_WIDTH = "1" *) (* C_PROBE_OUT239_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT239_WIDTH = "1" *) (* C_PROBE_OUT23_INIT_VAL = "1'b0" *) (* C_PROBE_OUT23_WIDTH = "1" *)
(* C_PROBE_OUT240_INIT_VAL = "1'b0" *) (* C_PROBE_OUT240_WIDTH = "1" *) (* C_PROBE_OUT241_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT241_WIDTH = "1" *) (* C_PROBE_OUT242_INIT_VAL = "1'b0" *) (* C_PROBE_OUT242_WIDTH = "1" *)
(* C_PROBE_OUT243_INIT_VAL = "1'b0" *) (* C_PROBE_OUT243_WIDTH = "1" *) (* C_PROBE_OUT244_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT244_WIDTH = "1" *) (* C_PROBE_OUT245_INIT_VAL = "1'b0" *) (* C_PROBE_OUT245_WIDTH = "1" *)
(* C_PROBE_OUT246_INIT_VAL = "1'b0" *) (* C_PROBE_OUT246_WIDTH = "1" *) (* C_PROBE_OUT247_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT247_WIDTH = "1" *) (* C_PROBE_OUT248_INIT_VAL = "1'b0" *) (* C_PROBE_OUT248_WIDTH = "1" *)
(* C_PROBE_OUT249_INIT_VAL = "1'b0" *) (* C_PROBE_OUT249_WIDTH = "1" *) (* C_PROBE_OUT24_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT24_WIDTH = "1" *) (* C_PROBE_OUT250_INIT_VAL = "1'b0" *) (* C_PROBE_OUT250_WIDTH = "1" *)
(* C_PROBE_OUT251_INIT_VAL = "1'b0" *) (* C_PROBE_OUT251_WIDTH = "1" *) (* C_PROBE_OUT252_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT252_WIDTH = "1" *) (* C_PROBE_OUT253_INIT_VAL = "1'b0" *) (* C_PROBE_OUT253_WIDTH = "1" *)
(* C_PROBE_OUT254_INIT_VAL = "1'b0" *) (* C_PROBE_OUT254_WIDTH = "1" *) (* C_PROBE_OUT255_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT255_WIDTH = "1" *) (* C_PROBE_OUT25_INIT_VAL = "1'b0" *) (* C_PROBE_OUT25_WIDTH = "1" *)
(* C_PROBE_OUT26_INIT_VAL = "1'b0" *) (* C_PROBE_OUT26_WIDTH = "1" *) (* C_PROBE_OUT27_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT27_WIDTH = "1" *) (* C_PROBE_OUT28_INIT_VAL = "1'b0" *) (* C_PROBE_OUT28_WIDTH = "1" *)
(* C_PROBE_OUT29_INIT_VAL = "1'b0" *) (* C_PROBE_OUT29_WIDTH = "1" *) (* C_PROBE_OUT2_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT2_WIDTH = "1" *) (* C_PROBE_OUT30_INIT_VAL = "1'b0" *) (* C_PROBE_OUT30_WIDTH = "1" *)
(* C_PROBE_OUT31_INIT_VAL = "1'b0" *) (* C_PROBE_OUT31_WIDTH = "1" *) (* C_PROBE_OUT32_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT32_WIDTH = "1" *) (* C_PROBE_OUT33_INIT_VAL = "1'b0" *) (* C_PROBE_OUT33_WIDTH = "1" *)
(* C_PROBE_OUT34_INIT_VAL = "1'b0" *) (* C_PROBE_OUT34_WIDTH = "1" *) (* C_PROBE_OUT35_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT35_WIDTH = "1" *) (* C_PROBE_OUT36_INIT_VAL = "1'b0" *) (* C_PROBE_OUT36_WIDTH = "1" *)
(* C_PROBE_OUT37_INIT_VAL = "1'b0" *) (* C_PROBE_OUT37_WIDTH = "1" *) (* C_PROBE_OUT38_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT38_WIDTH = "1" *) (* C_PROBE_OUT39_INIT_VAL = "1'b0" *) (* C_PROBE_OUT39_WIDTH = "1" *)
(* C_PROBE_OUT3_INIT_VAL = "1'b0" *) (* C_PROBE_OUT3_WIDTH = "1" *) (* C_PROBE_OUT40_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT40_WIDTH = "1" *) (* C_PROBE_OUT41_INIT_VAL = "1'b0" *) (* C_PROBE_OUT41_WIDTH = "1" *)
(* C_PROBE_OUT42_INIT_VAL = "1'b0" *) (* C_PROBE_OUT42_WIDTH = "1" *) (* C_PROBE_OUT43_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT43_WIDTH = "1" *) (* C_PROBE_OUT44_INIT_VAL = "1'b0" *) (* C_PROBE_OUT44_WIDTH = "1" *)
(* C_PROBE_OUT45_INIT_VAL = "1'b0" *) (* C_PROBE_OUT45_WIDTH = "1" *) (* C_PROBE_OUT46_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT46_WIDTH = "1" *) (* C_PROBE_OUT47_INIT_VAL = "1'b0" *) (* C_PROBE_OUT47_WIDTH = "1" *)
(* C_PROBE_OUT48_INIT_VAL = "1'b0" *) (* C_PROBE_OUT48_WIDTH = "1" *) (* C_PROBE_OUT49_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT49_WIDTH = "1" *) (* C_PROBE_OUT4_INIT_VAL = "1'b0" *) (* C_PROBE_OUT4_WIDTH = "1" *)
(* C_PROBE_OUT50_INIT_VAL = "1'b0" *) (* C_PROBE_OUT50_WIDTH = "1" *) (* C_PROBE_OUT51_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT51_WIDTH = "1" *) (* C_PROBE_OUT52_INIT_VAL = "1'b0" *) (* C_PROBE_OUT52_WIDTH = "1" *)
(* C_PROBE_OUT53_INIT_VAL = "1'b0" *) (* C_PROBE_OUT53_WIDTH = "1" *) (* C_PROBE_OUT54_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT54_WIDTH = "1" *) (* C_PROBE_OUT55_INIT_VAL = "1'b0" *) (* C_PROBE_OUT55_WIDTH = "1" *)
(* C_PROBE_OUT56_INIT_VAL = "1'b0" *) (* C_PROBE_OUT56_WIDTH = "1" *) (* C_PROBE_OUT57_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT57_WIDTH = "1" *) (* C_PROBE_OUT58_INIT_VAL = "1'b0" *) (* C_PROBE_OUT58_WIDTH = "1" *)
(* C_PROBE_OUT59_INIT_VAL = "1'b0" *) (* C_PROBE_OUT59_WIDTH = "1" *) (* C_PROBE_OUT5_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT5_WIDTH = "1" *) (* C_PROBE_OUT60_INIT_VAL = "1'b0" *) (* C_PROBE_OUT60_WIDTH = "1" *)
(* C_PROBE_OUT61_INIT_VAL = "1'b0" *) (* C_PROBE_OUT61_WIDTH = "1" *) (* C_PROBE_OUT62_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT62_WIDTH = "1" *) (* C_PROBE_OUT63_INIT_VAL = "1'b0" *) (* C_PROBE_OUT63_WIDTH = "1" *)
(* C_PROBE_OUT64_INIT_VAL = "1'b0" *) (* C_PROBE_OUT64_WIDTH = "1" *) (* C_PROBE_OUT65_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT65_WIDTH = "1" *) (* C_PROBE_OUT66_INIT_VAL = "1'b0" *) (* C_PROBE_OUT66_WIDTH = "1" *)
(* C_PROBE_OUT67_INIT_VAL = "1'b0" *) (* C_PROBE_OUT67_WIDTH = "1" *) (* C_PROBE_OUT68_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT68_WIDTH = "1" *) (* C_PROBE_OUT69_INIT_VAL = "1'b0" *) (* C_PROBE_OUT69_WIDTH = "1" *)
(* C_PROBE_OUT6_INIT_VAL = "1'b0" *) (* C_PROBE_OUT6_WIDTH = "1" *) (* C_PROBE_OUT70_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT70_WIDTH = "1" *) (* C_PROBE_OUT71_INIT_VAL = "1'b0" *) (* C_PROBE_OUT71_WIDTH = "1" *)
(* C_PROBE_OUT72_INIT_VAL = "1'b0" *) (* C_PROBE_OUT72_WIDTH = "1" *) (* C_PROBE_OUT73_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT73_WIDTH = "1" *) (* C_PROBE_OUT74_INIT_VAL = "1'b0" *) (* C_PROBE_OUT74_WIDTH = "1" *)
(* C_PROBE_OUT75_INIT_VAL = "1'b0" *) (* C_PROBE_OUT75_WIDTH = "1" *) (* C_PROBE_OUT76_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT76_WIDTH = "1" *) (* C_PROBE_OUT77_INIT_VAL = "1'b0" *) (* C_PROBE_OUT77_WIDTH = "1" *)
(* C_PROBE_OUT78_INIT_VAL = "1'b0" *) (* C_PROBE_OUT78_WIDTH = "1" *) (* C_PROBE_OUT79_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT79_WIDTH = "1" *) (* C_PROBE_OUT7_INIT_VAL = "1'b0" *) (* C_PROBE_OUT7_WIDTH = "1" *)
(* C_PROBE_OUT80_INIT_VAL = "1'b0" *) (* C_PROBE_OUT80_WIDTH = "1" *) (* C_PROBE_OUT81_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT81_WIDTH = "1" *) (* C_PROBE_OUT82_INIT_VAL = "1'b0" *) (* C_PROBE_OUT82_WIDTH = "1" *)
(* C_PROBE_OUT83_INIT_VAL = "1'b0" *) (* C_PROBE_OUT83_WIDTH = "1" *) (* C_PROBE_OUT84_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT84_WIDTH = "1" *) (* C_PROBE_OUT85_INIT_VAL = "1'b0" *) (* C_PROBE_OUT85_WIDTH = "1" *)
(* C_PROBE_OUT86_INIT_VAL = "1'b0" *) (* C_PROBE_OUT86_WIDTH = "1" *) (* C_PROBE_OUT87_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT87_WIDTH = "1" *) (* C_PROBE_OUT88_INIT_VAL = "1'b0" *) (* C_PROBE_OUT88_WIDTH = "1" *)
(* C_PROBE_OUT89_INIT_VAL = "1'b0" *) (* C_PROBE_OUT89_WIDTH = "1" *) (* C_PROBE_OUT8_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT8_WIDTH = "1" *) (* C_PROBE_OUT90_INIT_VAL = "1'b0" *) (* C_PROBE_OUT90_WIDTH = "1" *)
(* C_PROBE_OUT91_INIT_VAL = "1'b0" *) (* C_PROBE_OUT91_WIDTH = "1" *) (* C_PROBE_OUT92_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT92_WIDTH = "1" *) (* C_PROBE_OUT93_INIT_VAL = "1'b0" *) (* C_PROBE_OUT93_WIDTH = "1" *)
(* C_PROBE_OUT94_INIT_VAL = "1'b0" *) (* C_PROBE_OUT94_WIDTH = "1" *) (* C_PROBE_OUT95_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT95_WIDTH = "1" *) (* C_PROBE_OUT96_INIT_VAL = "1'b0" *) (* C_PROBE_OUT96_WIDTH = "1" *)
(* C_PROBE_OUT97_INIT_VAL = "1'b0" *) (* C_PROBE_OUT97_WIDTH = "1" *) (* C_PROBE_OUT98_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT98_WIDTH = "1" *) (* C_PROBE_OUT99_INIT_VAL = "1'b0" *) (* C_PROBE_OUT99_WIDTH = "1" *)
(* C_PROBE_OUT9_INIT_VAL = "1'b0" *) (* C_PROBE_OUT9_WIDTH = "1" *) (* C_USE_TEST_REG = "1" *)
(* C_XDEVICEFAMILY = "kintex7" *) (* C_XLNX_HW_PROBE_INFO = "DEFAULT" *) (* C_XSDB_SLAVE_TYPE = "33" *)
(* DowngradeIPIdentifiedWarnings = "yes" *) (* LC_HIGH_BIT_POS_PROBE_OUT0 = "16'b0000000000000000" *) (* LC_HIGH_BIT_POS_PROBE_OUT1 = "16'b0000000000000001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT10 = "16'b0000000000001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT100 = "16'b0000000001100100" *) (* LC_HIGH_BIT_POS_PROBE_OUT101 = "16'b0000000001100101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT102 = "16'b0000000001100110" *) (* LC_HIGH_BIT_POS_PROBE_OUT103 = "16'b0000000001100111" *) (* LC_HIGH_BIT_POS_PROBE_OUT104 = "16'b0000000001101000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT105 = "16'b0000000001101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT106 = "16'b0000000001101010" *) (* LC_HIGH_BIT_POS_PROBE_OUT107 = "16'b0000000001101011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT108 = "16'b0000000001101100" *) (* LC_HIGH_BIT_POS_PROBE_OUT109 = "16'b0000000001101101" *) (* LC_HIGH_BIT_POS_PROBE_OUT11 = "16'b0000000000001011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT110 = "16'b0000000001101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT111 = "16'b0000000001101111" *) (* LC_HIGH_BIT_POS_PROBE_OUT112 = "16'b0000000001110000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT113 = "16'b0000000001110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT114 = "16'b0000000001110010" *) (* LC_HIGH_BIT_POS_PROBE_OUT115 = "16'b0000000001110011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT116 = "16'b0000000001110100" *) (* LC_HIGH_BIT_POS_PROBE_OUT117 = "16'b0000000001110101" *) (* LC_HIGH_BIT_POS_PROBE_OUT118 = "16'b0000000001110110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT119 = "16'b0000000001110111" *) (* LC_HIGH_BIT_POS_PROBE_OUT12 = "16'b0000000000001100" *) (* LC_HIGH_BIT_POS_PROBE_OUT120 = "16'b0000000001111000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT121 = "16'b0000000001111001" *) (* LC_HIGH_BIT_POS_PROBE_OUT122 = "16'b0000000001111010" *) (* LC_HIGH_BIT_POS_PROBE_OUT123 = "16'b0000000001111011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT124 = "16'b0000000001111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT125 = "16'b0000000001111101" *) (* LC_HIGH_BIT_POS_PROBE_OUT126 = "16'b0000000001111110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT127 = "16'b0000000001111111" *) (* LC_HIGH_BIT_POS_PROBE_OUT128 = "16'b0000000010000000" *) (* LC_HIGH_BIT_POS_PROBE_OUT129 = "16'b0000000010000001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT13 = "16'b0000000000001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT130 = "16'b0000000010000010" *) (* LC_HIGH_BIT_POS_PROBE_OUT131 = "16'b0000000010000011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT132 = "16'b0000000010000100" *) (* LC_HIGH_BIT_POS_PROBE_OUT133 = "16'b0000000010000101" *) (* LC_HIGH_BIT_POS_PROBE_OUT134 = "16'b0000000010000110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT135 = "16'b0000000010000111" *) (* LC_HIGH_BIT_POS_PROBE_OUT136 = "16'b0000000010001000" *) (* LC_HIGH_BIT_POS_PROBE_OUT137 = "16'b0000000010001001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT138 = "16'b0000000010001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT139 = "16'b0000000010001011" *) (* LC_HIGH_BIT_POS_PROBE_OUT14 = "16'b0000000000001110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT140 = "16'b0000000010001100" *) (* LC_HIGH_BIT_POS_PROBE_OUT141 = "16'b0000000010001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT142 = "16'b0000000010001110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT143 = "16'b0000000010001111" *) (* LC_HIGH_BIT_POS_PROBE_OUT144 = "16'b0000000010010000" *) (* LC_HIGH_BIT_POS_PROBE_OUT145 = "16'b0000000010010001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT146 = "16'b0000000010010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT147 = "16'b0000000010010011" *) (* LC_HIGH_BIT_POS_PROBE_OUT148 = "16'b0000000010010100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT149 = "16'b0000000010010101" *) (* LC_HIGH_BIT_POS_PROBE_OUT15 = "16'b0000000000001111" *) (* LC_HIGH_BIT_POS_PROBE_OUT150 = "16'b0000000010010110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT151 = "16'b0000000010010111" *) (* LC_HIGH_BIT_POS_PROBE_OUT152 = "16'b0000000010011000" *) (* LC_HIGH_BIT_POS_PROBE_OUT153 = "16'b0000000010011001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT154 = "16'b0000000010011010" *) (* LC_HIGH_BIT_POS_PROBE_OUT155 = "16'b0000000010011011" *) (* LC_HIGH_BIT_POS_PROBE_OUT156 = "16'b0000000010011100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT157 = "16'b0000000010011101" *) (* LC_HIGH_BIT_POS_PROBE_OUT158 = "16'b0000000010011110" *) (* LC_HIGH_BIT_POS_PROBE_OUT159 = "16'b0000000010011111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT16 = "16'b0000000000010000" *) (* LC_HIGH_BIT_POS_PROBE_OUT160 = "16'b0000000010100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT161 = "16'b0000000010100001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT162 = "16'b0000000010100010" *) (* LC_HIGH_BIT_POS_PROBE_OUT163 = "16'b0000000010100011" *) (* LC_HIGH_BIT_POS_PROBE_OUT164 = "16'b0000000010100100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT165 = "16'b0000000010100101" *) (* LC_HIGH_BIT_POS_PROBE_OUT166 = "16'b0000000010100110" *) (* LC_HIGH_BIT_POS_PROBE_OUT167 = "16'b0000000010100111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT168 = "16'b0000000010101000" *) (* LC_HIGH_BIT_POS_PROBE_OUT169 = "16'b0000000010101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT17 = "16'b0000000000010001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT170 = "16'b0000000010101010" *) (* LC_HIGH_BIT_POS_PROBE_OUT171 = "16'b0000000010101011" *) (* LC_HIGH_BIT_POS_PROBE_OUT172 = "16'b0000000010101100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT173 = "16'b0000000010101101" *) (* LC_HIGH_BIT_POS_PROBE_OUT174 = "16'b0000000010101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT175 = "16'b0000000010101111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT176 = "16'b0000000010110000" *) (* LC_HIGH_BIT_POS_PROBE_OUT177 = "16'b0000000010110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT178 = "16'b0000000010110010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT179 = "16'b0000000010110011" *) (* LC_HIGH_BIT_POS_PROBE_OUT18 = "16'b0000000000010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT180 = "16'b0000000010110100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT181 = "16'b0000000010110101" *) (* LC_HIGH_BIT_POS_PROBE_OUT182 = "16'b0000000010110110" *) (* LC_HIGH_BIT_POS_PROBE_OUT183 = "16'b0000000010110111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT184 = "16'b0000000010111000" *) (* LC_HIGH_BIT_POS_PROBE_OUT185 = "16'b0000000010111001" *) (* LC_HIGH_BIT_POS_PROBE_OUT186 = "16'b0000000010111010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT187 = "16'b0000000010111011" *) (* LC_HIGH_BIT_POS_PROBE_OUT188 = "16'b0000000010111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT189 = "16'b0000000010111101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT19 = "16'b0000000000010011" *) (* LC_HIGH_BIT_POS_PROBE_OUT190 = "16'b0000000010111110" *) (* LC_HIGH_BIT_POS_PROBE_OUT191 = "16'b0000000010111111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT192 = "16'b0000000011000000" *) (* LC_HIGH_BIT_POS_PROBE_OUT193 = "16'b0000000011000001" *) (* LC_HIGH_BIT_POS_PROBE_OUT194 = "16'b0000000011000010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT195 = "16'b0000000011000011" *) (* LC_HIGH_BIT_POS_PROBE_OUT196 = "16'b0000000011000100" *) (* LC_HIGH_BIT_POS_PROBE_OUT197 = "16'b0000000011000101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT198 = "16'b0000000011000110" *) (* LC_HIGH_BIT_POS_PROBE_OUT199 = "16'b0000000011000111" *) (* LC_HIGH_BIT_POS_PROBE_OUT2 = "16'b0000000000000010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT20 = "16'b0000000000010100" *) (* LC_HIGH_BIT_POS_PROBE_OUT200 = "16'b0000000011001000" *) (* LC_HIGH_BIT_POS_PROBE_OUT201 = "16'b0000000011001001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT202 = "16'b0000000011001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT203 = "16'b0000000011001011" *) (* LC_HIGH_BIT_POS_PROBE_OUT204 = "16'b0000000011001100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT205 = "16'b0000000011001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT206 = "16'b0000000011001110" *) (* LC_HIGH_BIT_POS_PROBE_OUT207 = "16'b0000000011001111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT208 = "16'b0000000011010000" *) (* LC_HIGH_BIT_POS_PROBE_OUT209 = "16'b0000000011010001" *) (* LC_HIGH_BIT_POS_PROBE_OUT21 = "16'b0000000000010101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT210 = "16'b0000000011010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT211 = "16'b0000000011010011" *) (* LC_HIGH_BIT_POS_PROBE_OUT212 = "16'b0000000011010100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT213 = "16'b0000000011010101" *) (* LC_HIGH_BIT_POS_PROBE_OUT214 = "16'b0000000011010110" *) (* LC_HIGH_BIT_POS_PROBE_OUT215 = "16'b0000000011010111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT216 = "16'b0000000011011000" *) (* LC_HIGH_BIT_POS_PROBE_OUT217 = "16'b0000000011011001" *) (* LC_HIGH_BIT_POS_PROBE_OUT218 = "16'b0000000011011010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT219 = "16'b0000000011011011" *) (* LC_HIGH_BIT_POS_PROBE_OUT22 = "16'b0000000000010110" *) (* LC_HIGH_BIT_POS_PROBE_OUT220 = "16'b0000000011011100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT221 = "16'b0000000011011101" *) (* LC_HIGH_BIT_POS_PROBE_OUT222 = "16'b0000000011011110" *) (* LC_HIGH_BIT_POS_PROBE_OUT223 = "16'b0000000011011111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT224 = "16'b0000000011100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT225 = "16'b0000000011100001" *) (* LC_HIGH_BIT_POS_PROBE_OUT226 = "16'b0000000011100010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT227 = "16'b0000000011100011" *) (* LC_HIGH_BIT_POS_PROBE_OUT228 = "16'b0000000011100100" *) (* LC_HIGH_BIT_POS_PROBE_OUT229 = "16'b0000000011100101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT23 = "16'b0000000000010111" *) (* LC_HIGH_BIT_POS_PROBE_OUT230 = "16'b0000000011100110" *) (* LC_HIGH_BIT_POS_PROBE_OUT231 = "16'b0000000011100111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT232 = "16'b0000000011101000" *) (* LC_HIGH_BIT_POS_PROBE_OUT233 = "16'b0000000011101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT234 = "16'b0000000011101010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT235 = "16'b0000000011101011" *) (* LC_HIGH_BIT_POS_PROBE_OUT236 = "16'b0000000011101100" *) (* LC_HIGH_BIT_POS_PROBE_OUT237 = "16'b0000000011101101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT238 = "16'b0000000011101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT239 = "16'b0000000011101111" *) (* LC_HIGH_BIT_POS_PROBE_OUT24 = "16'b0000000000011000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT240 = "16'b0000000011110000" *) (* LC_HIGH_BIT_POS_PROBE_OUT241 = "16'b0000000011110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT242 = "16'b0000000011110010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT243 = "16'b0000000011110011" *) (* LC_HIGH_BIT_POS_PROBE_OUT244 = "16'b0000000011110100" *) (* LC_HIGH_BIT_POS_PROBE_OUT245 = "16'b0000000011110101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT246 = "16'b0000000011110110" *) (* LC_HIGH_BIT_POS_PROBE_OUT247 = "16'b0000000011110111" *) (* LC_HIGH_BIT_POS_PROBE_OUT248 = "16'b0000000011111000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT249 = "16'b0000000011111001" *) (* LC_HIGH_BIT_POS_PROBE_OUT25 = "16'b0000000000011001" *) (* LC_HIGH_BIT_POS_PROBE_OUT250 = "16'b0000000011111010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT251 = "16'b0000000011111011" *) (* LC_HIGH_BIT_POS_PROBE_OUT252 = "16'b0000000011111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT253 = "16'b0000000011111101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT254 = "16'b0000000011111110" *) (* LC_HIGH_BIT_POS_PROBE_OUT255 = "16'b0000000011111111" *) (* LC_HIGH_BIT_POS_PROBE_OUT26 = "16'b0000000000011010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT27 = "16'b0000000000011011" *) (* LC_HIGH_BIT_POS_PROBE_OUT28 = "16'b0000000000011100" *) (* LC_HIGH_BIT_POS_PROBE_OUT29 = "16'b0000000000011101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT3 = "16'b0000000000000011" *) (* LC_HIGH_BIT_POS_PROBE_OUT30 = "16'b0000000000011110" *) (* LC_HIGH_BIT_POS_PROBE_OUT31 = "16'b0000000000011111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT32 = "16'b0000000000100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT33 = "16'b0000000000100001" *) (* LC_HIGH_BIT_POS_PROBE_OUT34 = "16'b0000000000100010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT35 = "16'b0000000000100011" *) (* LC_HIGH_BIT_POS_PROBE_OUT36 = "16'b0000000000100100" *) (* LC_HIGH_BIT_POS_PROBE_OUT37 = "16'b0000000000100101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT38 = "16'b0000000000100110" *) (* LC_HIGH_BIT_POS_PROBE_OUT39 = "16'b0000000000100111" *) (* LC_HIGH_BIT_POS_PROBE_OUT4 = "16'b0000000000000100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT40 = "16'b0000000000101000" *) (* LC_HIGH_BIT_POS_PROBE_OUT41 = "16'b0000000000101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT42 = "16'b0000000000101010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT43 = "16'b0000000000101011" *) (* LC_HIGH_BIT_POS_PROBE_OUT44 = "16'b0000000000101100" *) (* LC_HIGH_BIT_POS_PROBE_OUT45 = "16'b0000000000101101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT46 = "16'b0000000000101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT47 = "16'b0000000000101111" *) (* LC_HIGH_BIT_POS_PROBE_OUT48 = "16'b0000000000110000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT49 = "16'b0000000000110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT5 = "16'b0000000000000101" *) (* LC_HIGH_BIT_POS_PROBE_OUT50 = "16'b0000000000110010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT51 = "16'b0000000000110011" *) (* LC_HIGH_BIT_POS_PROBE_OUT52 = "16'b0000000000110100" *) (* LC_HIGH_BIT_POS_PROBE_OUT53 = "16'b0000000000110101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT54 = "16'b0000000000110110" *) (* LC_HIGH_BIT_POS_PROBE_OUT55 = "16'b0000000000110111" *) (* LC_HIGH_BIT_POS_PROBE_OUT56 = "16'b0000000000111000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT57 = "16'b0000000000111001" *) (* LC_HIGH_BIT_POS_PROBE_OUT58 = "16'b0000000000111010" *) (* LC_HIGH_BIT_POS_PROBE_OUT59 = "16'b0000000000111011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT6 = "16'b0000000000000110" *) (* LC_HIGH_BIT_POS_PROBE_OUT60 = "16'b0000000000111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT61 = "16'b0000000000111101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT62 = "16'b0000000000111110" *) (* LC_HIGH_BIT_POS_PROBE_OUT63 = "16'b0000000000111111" *) (* LC_HIGH_BIT_POS_PROBE_OUT64 = "16'b0000000001000000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT65 = "16'b0000000001000001" *) (* LC_HIGH_BIT_POS_PROBE_OUT66 = "16'b0000000001000010" *) (* LC_HIGH_BIT_POS_PROBE_OUT67 = "16'b0000000001000011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT68 = "16'b0000000001000100" *) (* LC_HIGH_BIT_POS_PROBE_OUT69 = "16'b0000000001000101" *) (* LC_HIGH_BIT_POS_PROBE_OUT7 = "16'b0000000000000111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT70 = "16'b0000000001000110" *) (* LC_HIGH_BIT_POS_PROBE_OUT71 = "16'b0000000001000111" *) (* LC_HIGH_BIT_POS_PROBE_OUT72 = "16'b0000000001001000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT73 = "16'b0000000001001001" *) (* LC_HIGH_BIT_POS_PROBE_OUT74 = "16'b0000000001001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT75 = "16'b0000000001001011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT76 = "16'b0000000001001100" *) (* LC_HIGH_BIT_POS_PROBE_OUT77 = "16'b0000000001001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT78 = "16'b0000000001001110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT79 = "16'b0000000001001111" *) (* LC_HIGH_BIT_POS_PROBE_OUT8 = "16'b0000000000001000" *) (* LC_HIGH_BIT_POS_PROBE_OUT80 = "16'b0000000001010000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT81 = "16'b0000000001010001" *) (* LC_HIGH_BIT_POS_PROBE_OUT82 = "16'b0000000001010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT83 = "16'b0000000001010011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT84 = "16'b0000000001010100" *) (* LC_HIGH_BIT_POS_PROBE_OUT85 = "16'b0000000001010101" *) (* LC_HIGH_BIT_POS_PROBE_OUT86 = "16'b0000000001010110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT87 = "16'b0000000001010111" *) (* LC_HIGH_BIT_POS_PROBE_OUT88 = "16'b0000000001011000" *) (* LC_HIGH_BIT_POS_PROBE_OUT89 = "16'b0000000001011001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT9 = "16'b0000000000001001" *) (* LC_HIGH_BIT_POS_PROBE_OUT90 = "16'b0000000001011010" *) (* LC_HIGH_BIT_POS_PROBE_OUT91 = "16'b0000000001011011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT92 = "16'b0000000001011100" *) (* LC_HIGH_BIT_POS_PROBE_OUT93 = "16'b0000000001011101" *) (* LC_HIGH_BIT_POS_PROBE_OUT94 = "16'b0000000001011110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT95 = "16'b0000000001011111" *) (* LC_HIGH_BIT_POS_PROBE_OUT96 = "16'b0000000001100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT97 = "16'b0000000001100001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT98 = "16'b0000000001100010" *) (* LC_HIGH_BIT_POS_PROBE_OUT99 = "16'b0000000001100011" *) (* LC_LOW_BIT_POS_PROBE_OUT0 = "16'b0000000000000000" *)
(* LC_LOW_BIT_POS_PROBE_OUT1 = "16'b0000000000000001" *) (* LC_LOW_BIT_POS_PROBE_OUT10 = "16'b0000000000001010" *) (* LC_LOW_BIT_POS_PROBE_OUT100 = "16'b0000000001100100" *)
(* LC_LOW_BIT_POS_PROBE_OUT101 = "16'b0000000001100101" *) (* LC_LOW_BIT_POS_PROBE_OUT102 = "16'b0000000001100110" *) (* LC_LOW_BIT_POS_PROBE_OUT103 = "16'b0000000001100111" *)
(* LC_LOW_BIT_POS_PROBE_OUT104 = "16'b0000000001101000" *) (* LC_LOW_BIT_POS_PROBE_OUT105 = "16'b0000000001101001" *) (* LC_LOW_BIT_POS_PROBE_OUT106 = "16'b0000000001101010" *)
(* LC_LOW_BIT_POS_PROBE_OUT107 = "16'b0000000001101011" *) (* LC_LOW_BIT_POS_PROBE_OUT108 = "16'b0000000001101100" *) (* LC_LOW_BIT_POS_PROBE_OUT109 = "16'b0000000001101101" *)
(* LC_LOW_BIT_POS_PROBE_OUT11 = "16'b0000000000001011" *) (* LC_LOW_BIT_POS_PROBE_OUT110 = "16'b0000000001101110" *) (* LC_LOW_BIT_POS_PROBE_OUT111 = "16'b0000000001101111" *)
(* LC_LOW_BIT_POS_PROBE_OUT112 = "16'b0000000001110000" *) (* LC_LOW_BIT_POS_PROBE_OUT113 = "16'b0000000001110001" *) (* LC_LOW_BIT_POS_PROBE_OUT114 = "16'b0000000001110010" *)
(* LC_LOW_BIT_POS_PROBE_OUT115 = "16'b0000000001110011" *) (* LC_LOW_BIT_POS_PROBE_OUT116 = "16'b0000000001110100" *) (* LC_LOW_BIT_POS_PROBE_OUT117 = "16'b0000000001110101" *)
(* LC_LOW_BIT_POS_PROBE_OUT118 = "16'b0000000001110110" *) (* LC_LOW_BIT_POS_PROBE_OUT119 = "16'b0000000001110111" *) (* LC_LOW_BIT_POS_PROBE_OUT12 = "16'b0000000000001100" *)
(* LC_LOW_BIT_POS_PROBE_OUT120 = "16'b0000000001111000" *) (* LC_LOW_BIT_POS_PROBE_OUT121 = "16'b0000000001111001" *) (* LC_LOW_BIT_POS_PROBE_OUT122 = "16'b0000000001111010" *)
(* LC_LOW_BIT_POS_PROBE_OUT123 = "16'b0000000001111011" *) (* LC_LOW_BIT_POS_PROBE_OUT124 = "16'b0000000001111100" *) (* LC_LOW_BIT_POS_PROBE_OUT125 = "16'b0000000001111101" *)
(* LC_LOW_BIT_POS_PROBE_OUT126 = "16'b0000000001111110" *) (* LC_LOW_BIT_POS_PROBE_OUT127 = "16'b0000000001111111" *) (* LC_LOW_BIT_POS_PROBE_OUT128 = "16'b0000000010000000" *)
(* LC_LOW_BIT_POS_PROBE_OUT129 = "16'b0000000010000001" *) (* LC_LOW_BIT_POS_PROBE_OUT13 = "16'b0000000000001101" *) (* LC_LOW_BIT_POS_PROBE_OUT130 = "16'b0000000010000010" *)
(* LC_LOW_BIT_POS_PROBE_OUT131 = "16'b0000000010000011" *) (* LC_LOW_BIT_POS_PROBE_OUT132 = "16'b0000000010000100" *) (* LC_LOW_BIT_POS_PROBE_OUT133 = "16'b0000000010000101" *)
(* LC_LOW_BIT_POS_PROBE_OUT134 = "16'b0000000010000110" *) (* LC_LOW_BIT_POS_PROBE_OUT135 = "16'b0000000010000111" *) (* LC_LOW_BIT_POS_PROBE_OUT136 = "16'b0000000010001000" *)
(* LC_LOW_BIT_POS_PROBE_OUT137 = "16'b0000000010001001" *) (* LC_LOW_BIT_POS_PROBE_OUT138 = "16'b0000000010001010" *) (* LC_LOW_BIT_POS_PROBE_OUT139 = "16'b0000000010001011" *)
(* LC_LOW_BIT_POS_PROBE_OUT14 = "16'b0000000000001110" *) (* LC_LOW_BIT_POS_PROBE_OUT140 = "16'b0000000010001100" *) (* LC_LOW_BIT_POS_PROBE_OUT141 = "16'b0000000010001101" *)
(* LC_LOW_BIT_POS_PROBE_OUT142 = "16'b0000000010001110" *) (* LC_LOW_BIT_POS_PROBE_OUT143 = "16'b0000000010001111" *) (* LC_LOW_BIT_POS_PROBE_OUT144 = "16'b0000000010010000" *)
(* LC_LOW_BIT_POS_PROBE_OUT145 = "16'b0000000010010001" *) (* LC_LOW_BIT_POS_PROBE_OUT146 = "16'b0000000010010010" *) (* LC_LOW_BIT_POS_PROBE_OUT147 = "16'b0000000010010011" *)
(* LC_LOW_BIT_POS_PROBE_OUT148 = "16'b0000000010010100" *) (* LC_LOW_BIT_POS_PROBE_OUT149 = "16'b0000000010010101" *) (* LC_LOW_BIT_POS_PROBE_OUT15 = "16'b0000000000001111" *)
(* LC_LOW_BIT_POS_PROBE_OUT150 = "16'b0000000010010110" *) (* LC_LOW_BIT_POS_PROBE_OUT151 = "16'b0000000010010111" *) (* LC_LOW_BIT_POS_PROBE_OUT152 = "16'b0000000010011000" *)
(* LC_LOW_BIT_POS_PROBE_OUT153 = "16'b0000000010011001" *) (* LC_LOW_BIT_POS_PROBE_OUT154 = "16'b0000000010011010" *) (* LC_LOW_BIT_POS_PROBE_OUT155 = "16'b0000000010011011" *)
(* LC_LOW_BIT_POS_PROBE_OUT156 = "16'b0000000010011100" *) (* LC_LOW_BIT_POS_PROBE_OUT157 = "16'b0000000010011101" *) (* LC_LOW_BIT_POS_PROBE_OUT158 = "16'b0000000010011110" *)
(* LC_LOW_BIT_POS_PROBE_OUT159 = "16'b0000000010011111" *) (* LC_LOW_BIT_POS_PROBE_OUT16 = "16'b0000000000010000" *) (* LC_LOW_BIT_POS_PROBE_OUT160 = "16'b0000000010100000" *)
(* LC_LOW_BIT_POS_PROBE_OUT161 = "16'b0000000010100001" *) (* LC_LOW_BIT_POS_PROBE_OUT162 = "16'b0000000010100010" *) (* LC_LOW_BIT_POS_PROBE_OUT163 = "16'b0000000010100011" *)
(* LC_LOW_BIT_POS_PROBE_OUT164 = "16'b0000000010100100" *) (* LC_LOW_BIT_POS_PROBE_OUT165 = "16'b0000000010100101" *) (* LC_LOW_BIT_POS_PROBE_OUT166 = "16'b0000000010100110" *)
(* LC_LOW_BIT_POS_PROBE_OUT167 = "16'b0000000010100111" *) (* LC_LOW_BIT_POS_PROBE_OUT168 = "16'b0000000010101000" *) (* LC_LOW_BIT_POS_PROBE_OUT169 = "16'b0000000010101001" *)
(* LC_LOW_BIT_POS_PROBE_OUT17 = "16'b0000000000010001" *) (* LC_LOW_BIT_POS_PROBE_OUT170 = "16'b0000000010101010" *) (* LC_LOW_BIT_POS_PROBE_OUT171 = "16'b0000000010101011" *)
(* LC_LOW_BIT_POS_PROBE_OUT172 = "16'b0000000010101100" *) (* LC_LOW_BIT_POS_PROBE_OUT173 = "16'b0000000010101101" *) (* LC_LOW_BIT_POS_PROBE_OUT174 = "16'b0000000010101110" *)
(* LC_LOW_BIT_POS_PROBE_OUT175 = "16'b0000000010101111" *) (* LC_LOW_BIT_POS_PROBE_OUT176 = "16'b0000000010110000" *) (* LC_LOW_BIT_POS_PROBE_OUT177 = "16'b0000000010110001" *)
(* LC_LOW_BIT_POS_PROBE_OUT178 = "16'b0000000010110010" *) (* LC_LOW_BIT_POS_PROBE_OUT179 = "16'b0000000010110011" *) (* LC_LOW_BIT_POS_PROBE_OUT18 = "16'b0000000000010010" *)
(* LC_LOW_BIT_POS_PROBE_OUT180 = "16'b0000000010110100" *) (* LC_LOW_BIT_POS_PROBE_OUT181 = "16'b0000000010110101" *) (* LC_LOW_BIT_POS_PROBE_OUT182 = "16'b0000000010110110" *)
(* LC_LOW_BIT_POS_PROBE_OUT183 = "16'b0000000010110111" *) (* LC_LOW_BIT_POS_PROBE_OUT184 = "16'b0000000010111000" *) (* LC_LOW_BIT_POS_PROBE_OUT185 = "16'b0000000010111001" *)
(* LC_LOW_BIT_POS_PROBE_OUT186 = "16'b0000000010111010" *) (* LC_LOW_BIT_POS_PROBE_OUT187 = "16'b0000000010111011" *) (* LC_LOW_BIT_POS_PROBE_OUT188 = "16'b0000000010111100" *)
(* LC_LOW_BIT_POS_PROBE_OUT189 = "16'b0000000010111101" *) (* LC_LOW_BIT_POS_PROBE_OUT19 = "16'b0000000000010011" *) (* LC_LOW_BIT_POS_PROBE_OUT190 = "16'b0000000010111110" *)
(* LC_LOW_BIT_POS_PROBE_OUT191 = "16'b0000000010111111" *) (* LC_LOW_BIT_POS_PROBE_OUT192 = "16'b0000000011000000" *) (* LC_LOW_BIT_POS_PROBE_OUT193 = "16'b0000000011000001" *)
(* LC_LOW_BIT_POS_PROBE_OUT194 = "16'b0000000011000010" *) (* LC_LOW_BIT_POS_PROBE_OUT195 = "16'b0000000011000011" *) (* LC_LOW_BIT_POS_PROBE_OUT196 = "16'b0000000011000100" *)
(* LC_LOW_BIT_POS_PROBE_OUT197 = "16'b0000000011000101" *) (* LC_LOW_BIT_POS_PROBE_OUT198 = "16'b0000000011000110" *) (* LC_LOW_BIT_POS_PROBE_OUT199 = "16'b0000000011000111" *)
(* LC_LOW_BIT_POS_PROBE_OUT2 = "16'b0000000000000010" *) (* LC_LOW_BIT_POS_PROBE_OUT20 = "16'b0000000000010100" *) (* LC_LOW_BIT_POS_PROBE_OUT200 = "16'b0000000011001000" *)
(* LC_LOW_BIT_POS_PROBE_OUT201 = "16'b0000000011001001" *) (* LC_LOW_BIT_POS_PROBE_OUT202 = "16'b0000000011001010" *) (* LC_LOW_BIT_POS_PROBE_OUT203 = "16'b0000000011001011" *)
(* LC_LOW_BIT_POS_PROBE_OUT204 = "16'b0000000011001100" *) (* LC_LOW_BIT_POS_PROBE_OUT205 = "16'b0000000011001101" *) (* LC_LOW_BIT_POS_PROBE_OUT206 = "16'b0000000011001110" *)
(* LC_LOW_BIT_POS_PROBE_OUT207 = "16'b0000000011001111" *) (* LC_LOW_BIT_POS_PROBE_OUT208 = "16'b0000000011010000" *) (* LC_LOW_BIT_POS_PROBE_OUT209 = "16'b0000000011010001" *)
(* LC_LOW_BIT_POS_PROBE_OUT21 = "16'b0000000000010101" *) (* LC_LOW_BIT_POS_PROBE_OUT210 = "16'b0000000011010010" *) (* LC_LOW_BIT_POS_PROBE_OUT211 = "16'b0000000011010011" *)
(* LC_LOW_BIT_POS_PROBE_OUT212 = "16'b0000000011010100" *) (* LC_LOW_BIT_POS_PROBE_OUT213 = "16'b0000000011010101" *) (* LC_LOW_BIT_POS_PROBE_OUT214 = "16'b0000000011010110" *)
(* LC_LOW_BIT_POS_PROBE_OUT215 = "16'b0000000011010111" *) (* LC_LOW_BIT_POS_PROBE_OUT216 = "16'b0000000011011000" *) (* LC_LOW_BIT_POS_PROBE_OUT217 = "16'b0000000011011001" *)
(* LC_LOW_BIT_POS_PROBE_OUT218 = "16'b0000000011011010" *) (* LC_LOW_BIT_POS_PROBE_OUT219 = "16'b0000000011011011" *) (* LC_LOW_BIT_POS_PROBE_OUT22 = "16'b0000000000010110" *)
(* LC_LOW_BIT_POS_PROBE_OUT220 = "16'b0000000011011100" *) (* LC_LOW_BIT_POS_PROBE_OUT221 = "16'b0000000011011101" *) (* LC_LOW_BIT_POS_PROBE_OUT222 = "16'b0000000011011110" *)
(* LC_LOW_BIT_POS_PROBE_OUT223 = "16'b0000000011011111" *) (* LC_LOW_BIT_POS_PROBE_OUT224 = "16'b0000000011100000" *) (* LC_LOW_BIT_POS_PROBE_OUT225 = "16'b0000000011100001" *)
(* LC_LOW_BIT_POS_PROBE_OUT226 = "16'b0000000011100010" *) (* LC_LOW_BIT_POS_PROBE_OUT227 = "16'b0000000011100011" *) (* LC_LOW_BIT_POS_PROBE_OUT228 = "16'b0000000011100100" *)
(* LC_LOW_BIT_POS_PROBE_OUT229 = "16'b0000000011100101" *) (* LC_LOW_BIT_POS_PROBE_OUT23 = "16'b0000000000010111" *) (* LC_LOW_BIT_POS_PROBE_OUT230 = "16'b0000000011100110" *)
(* LC_LOW_BIT_POS_PROBE_OUT231 = "16'b0000000011100111" *) (* LC_LOW_BIT_POS_PROBE_OUT232 = "16'b0000000011101000" *) (* LC_LOW_BIT_POS_PROBE_OUT233 = "16'b0000000011101001" *)
(* LC_LOW_BIT_POS_PROBE_OUT234 = "16'b0000000011101010" *) (* LC_LOW_BIT_POS_PROBE_OUT235 = "16'b0000000011101011" *) (* LC_LOW_BIT_POS_PROBE_OUT236 = "16'b0000000011101100" *)
(* LC_LOW_BIT_POS_PROBE_OUT237 = "16'b0000000011101101" *) (* LC_LOW_BIT_POS_PROBE_OUT238 = "16'b0000000011101110" *) (* LC_LOW_BIT_POS_PROBE_OUT239 = "16'b0000000011101111" *)
(* LC_LOW_BIT_POS_PROBE_OUT24 = "16'b0000000000011000" *) (* LC_LOW_BIT_POS_PROBE_OUT240 = "16'b0000000011110000" *) (* LC_LOW_BIT_POS_PROBE_OUT241 = "16'b0000000011110001" *)
(* LC_LOW_BIT_POS_PROBE_OUT242 = "16'b0000000011110010" *) (* LC_LOW_BIT_POS_PROBE_OUT243 = "16'b0000000011110011" *) (* LC_LOW_BIT_POS_PROBE_OUT244 = "16'b0000000011110100" *)
(* LC_LOW_BIT_POS_PROBE_OUT245 = "16'b0000000011110101" *) (* LC_LOW_BIT_POS_PROBE_OUT246 = "16'b0000000011110110" *) (* LC_LOW_BIT_POS_PROBE_OUT247 = "16'b0000000011110111" *)
(* LC_LOW_BIT_POS_PROBE_OUT248 = "16'b0000000011111000" *) (* LC_LOW_BIT_POS_PROBE_OUT249 = "16'b0000000011111001" *) (* LC_LOW_BIT_POS_PROBE_OUT25 = "16'b0000000000011001" *)
(* LC_LOW_BIT_POS_PROBE_OUT250 = "16'b0000000011111010" *) (* LC_LOW_BIT_POS_PROBE_OUT251 = "16'b0000000011111011" *) (* LC_LOW_BIT_POS_PROBE_OUT252 = "16'b0000000011111100" *)
(* LC_LOW_BIT_POS_PROBE_OUT253 = "16'b0000000011111101" *) (* LC_LOW_BIT_POS_PROBE_OUT254 = "16'b0000000011111110" *) (* LC_LOW_BIT_POS_PROBE_OUT255 = "16'b0000000011111111" *)
(* LC_LOW_BIT_POS_PROBE_OUT26 = "16'b0000000000011010" *) (* LC_LOW_BIT_POS_PROBE_OUT27 = "16'b0000000000011011" *) (* LC_LOW_BIT_POS_PROBE_OUT28 = "16'b0000000000011100" *)
(* LC_LOW_BIT_POS_PROBE_OUT29 = "16'b0000000000011101" *) (* LC_LOW_BIT_POS_PROBE_OUT3 = "16'b0000000000000011" *) (* LC_LOW_BIT_POS_PROBE_OUT30 = "16'b0000000000011110" *)
(* LC_LOW_BIT_POS_PROBE_OUT31 = "16'b0000000000011111" *) (* LC_LOW_BIT_POS_PROBE_OUT32 = "16'b0000000000100000" *) (* LC_LOW_BIT_POS_PROBE_OUT33 = "16'b0000000000100001" *)
(* LC_LOW_BIT_POS_PROBE_OUT34 = "16'b0000000000100010" *) (* LC_LOW_BIT_POS_PROBE_OUT35 = "16'b0000000000100011" *) (* LC_LOW_BIT_POS_PROBE_OUT36 = "16'b0000000000100100" *)
(* LC_LOW_BIT_POS_PROBE_OUT37 = "16'b0000000000100101" *) (* LC_LOW_BIT_POS_PROBE_OUT38 = "16'b0000000000100110" *) (* LC_LOW_BIT_POS_PROBE_OUT39 = "16'b0000000000100111" *)
(* LC_LOW_BIT_POS_PROBE_OUT4 = "16'b0000000000000100" *) (* LC_LOW_BIT_POS_PROBE_OUT40 = "16'b0000000000101000" *) (* LC_LOW_BIT_POS_PROBE_OUT41 = "16'b0000000000101001" *)
(* LC_LOW_BIT_POS_PROBE_OUT42 = "16'b0000000000101010" *) (* LC_LOW_BIT_POS_PROBE_OUT43 = "16'b0000000000101011" *) (* LC_LOW_BIT_POS_PROBE_OUT44 = "16'b0000000000101100" *)
(* LC_LOW_BIT_POS_PROBE_OUT45 = "16'b0000000000101101" *) (* LC_LOW_BIT_POS_PROBE_OUT46 = "16'b0000000000101110" *) (* LC_LOW_BIT_POS_PROBE_OUT47 = "16'b0000000000101111" *)
(* LC_LOW_BIT_POS_PROBE_OUT48 = "16'b0000000000110000" *) (* LC_LOW_BIT_POS_PROBE_OUT49 = "16'b0000000000110001" *) (* LC_LOW_BIT_POS_PROBE_OUT5 = "16'b0000000000000101" *)
(* LC_LOW_BIT_POS_PROBE_OUT50 = "16'b0000000000110010" *) (* LC_LOW_BIT_POS_PROBE_OUT51 = "16'b0000000000110011" *) (* LC_LOW_BIT_POS_PROBE_OUT52 = "16'b0000000000110100" *)
(* LC_LOW_BIT_POS_PROBE_OUT53 = "16'b0000000000110101" *) (* LC_LOW_BIT_POS_PROBE_OUT54 = "16'b0000000000110110" *) (* LC_LOW_BIT_POS_PROBE_OUT55 = "16'b0000000000110111" *)
(* LC_LOW_BIT_POS_PROBE_OUT56 = "16'b0000000000111000" *) (* LC_LOW_BIT_POS_PROBE_OUT57 = "16'b0000000000111001" *) (* LC_LOW_BIT_POS_PROBE_OUT58 = "16'b0000000000111010" *)
(* LC_LOW_BIT_POS_PROBE_OUT59 = "16'b0000000000111011" *) (* LC_LOW_BIT_POS_PROBE_OUT6 = "16'b0000000000000110" *) (* LC_LOW_BIT_POS_PROBE_OUT60 = "16'b0000000000111100" *)
(* LC_LOW_BIT_POS_PROBE_OUT61 = "16'b0000000000111101" *) (* LC_LOW_BIT_POS_PROBE_OUT62 = "16'b0000000000111110" *) (* LC_LOW_BIT_POS_PROBE_OUT63 = "16'b0000000000111111" *)
(* LC_LOW_BIT_POS_PROBE_OUT64 = "16'b0000000001000000" *) (* LC_LOW_BIT_POS_PROBE_OUT65 = "16'b0000000001000001" *) (* LC_LOW_BIT_POS_PROBE_OUT66 = "16'b0000000001000010" *)
(* LC_LOW_BIT_POS_PROBE_OUT67 = "16'b0000000001000011" *) (* LC_LOW_BIT_POS_PROBE_OUT68 = "16'b0000000001000100" *) (* LC_LOW_BIT_POS_PROBE_OUT69 = "16'b0000000001000101" *)
(* LC_LOW_BIT_POS_PROBE_OUT7 = "16'b0000000000000111" *) (* LC_LOW_BIT_POS_PROBE_OUT70 = "16'b0000000001000110" *) (* LC_LOW_BIT_POS_PROBE_OUT71 = "16'b0000000001000111" *)
(* LC_LOW_BIT_POS_PROBE_OUT72 = "16'b0000000001001000" *) (* LC_LOW_BIT_POS_PROBE_OUT73 = "16'b0000000001001001" *) (* LC_LOW_BIT_POS_PROBE_OUT74 = "16'b0000000001001010" *)
(* LC_LOW_BIT_POS_PROBE_OUT75 = "16'b0000000001001011" *) (* LC_LOW_BIT_POS_PROBE_OUT76 = "16'b0000000001001100" *) (* LC_LOW_BIT_POS_PROBE_OUT77 = "16'b0000000001001101" *)
(* LC_LOW_BIT_POS_PROBE_OUT78 = "16'b0000000001001110" *) (* LC_LOW_BIT_POS_PROBE_OUT79 = "16'b0000000001001111" *) (* LC_LOW_BIT_POS_PROBE_OUT8 = "16'b0000000000001000" *)
(* LC_LOW_BIT_POS_PROBE_OUT80 = "16'b0000000001010000" *) (* LC_LOW_BIT_POS_PROBE_OUT81 = "16'b0000000001010001" *) (* LC_LOW_BIT_POS_PROBE_OUT82 = "16'b0000000001010010" *)
(* LC_LOW_BIT_POS_PROBE_OUT83 = "16'b0000000001010011" *) (* LC_LOW_BIT_POS_PROBE_OUT84 = "16'b0000000001010100" *) (* LC_LOW_BIT_POS_PROBE_OUT85 = "16'b0000000001010101" *)
(* LC_LOW_BIT_POS_PROBE_OUT86 = "16'b0000000001010110" *) (* LC_LOW_BIT_POS_PROBE_OUT87 = "16'b0000000001010111" *) (* LC_LOW_BIT_POS_PROBE_OUT88 = "16'b0000000001011000" *)
(* LC_LOW_BIT_POS_PROBE_OUT89 = "16'b0000000001011001" *) (* LC_LOW_BIT_POS_PROBE_OUT9 = "16'b0000000000001001" *) (* LC_LOW_BIT_POS_PROBE_OUT90 = "16'b0000000001011010" *)
(* LC_LOW_BIT_POS_PROBE_OUT91 = "16'b0000000001011011" *) (* LC_LOW_BIT_POS_PROBE_OUT92 = "16'b0000000001011100" *) (* LC_LOW_BIT_POS_PROBE_OUT93 = "16'b0000000001011101" *)
(* LC_LOW_BIT_POS_PROBE_OUT94 = "16'b0000000001011110" *) (* LC_LOW_BIT_POS_PROBE_OUT95 = "16'b0000000001011111" *) (* LC_LOW_BIT_POS_PROBE_OUT96 = "16'b0000000001100000" *)
(* LC_LOW_BIT_POS_PROBE_OUT97 = "16'b0000000001100001" *) (* LC_LOW_BIT_POS_PROBE_OUT98 = "16'b0000000001100010" *) (* LC_LOW_BIT_POS_PROBE_OUT99 = "16'b0000000001100011" *)
(* LC_PROBE_IN_WIDTH_STRING = "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* LC_PROBE_OUT_HIGH_BIT_POS_STRING = "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000" *) (* LC_PROBE_OUT_INIT_VAL_STRING = "256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* LC_PROBE_OUT_LOW_BIT_POS_STRING = "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000" *) (* LC_PROBE_OUT_WIDTH_STRING = "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* LC_TOTAL_PROBE_IN_WIDTH = "3" *)
(* LC_TOTAL_PROBE_OUT_WIDTH = "0" *) (* dont_touch = "true" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio
(clk,
probe_in0,
probe_in1,
probe_in2,
probe_in3,
probe_in4,
probe_in5,
probe_in6,
probe_in7,
probe_in8,
probe_in9,
probe_in10,
probe_in11,
probe_in12,
probe_in13,
probe_in14,
probe_in15,
probe_in16,
probe_in17,
probe_in18,
probe_in19,
probe_in20,
probe_in21,
probe_in22,
probe_in23,
probe_in24,
probe_in25,
probe_in26,
probe_in27,
probe_in28,
probe_in29,
probe_in30,
probe_in31,
probe_in32,
probe_in33,
probe_in34,
probe_in35,
probe_in36,
probe_in37,
probe_in38,
probe_in39,
probe_in40,
probe_in41,
probe_in42,
probe_in43,
probe_in44,
probe_in45,
probe_in46,
probe_in47,
probe_in48,
probe_in49,
probe_in50,
probe_in51,
probe_in52,
probe_in53,
probe_in54,
probe_in55,
probe_in56,
probe_in57,
probe_in58,
probe_in59,
probe_in60,
probe_in61,
probe_in62,
probe_in63,
probe_in64,
probe_in65,
probe_in66,
probe_in67,
probe_in68,
probe_in69,
probe_in70,
probe_in71,
probe_in72,
probe_in73,
probe_in74,
probe_in75,
probe_in76,
probe_in77,
probe_in78,
probe_in79,
probe_in80,
probe_in81,
probe_in82,
probe_in83,
probe_in84,
probe_in85,
probe_in86,
probe_in87,
probe_in88,
probe_in89,
probe_in90,
probe_in91,
probe_in92,
probe_in93,
probe_in94,
probe_in95,
probe_in96,
probe_in97,
probe_in98,
probe_in99,
probe_in100,
probe_in101,
probe_in102,
probe_in103,
probe_in104,
probe_in105,
probe_in106,
probe_in107,
probe_in108,
probe_in109,
probe_in110,
probe_in111,
probe_in112,
probe_in113,
probe_in114,
probe_in115,
probe_in116,
probe_in117,
probe_in118,
probe_in119,
probe_in120,
probe_in121,
probe_in122,
probe_in123,
probe_in124,
probe_in125,
probe_in126,
probe_in127,
probe_in128,
probe_in129,
probe_in130,
probe_in131,
probe_in132,
probe_in133,
probe_in134,
probe_in135,
probe_in136,
probe_in137,
probe_in138,
probe_in139,
probe_in140,
probe_in141,
probe_in142,
probe_in143,
probe_in144,
probe_in145,
probe_in146,
probe_in147,
probe_in148,
probe_in149,
probe_in150,
probe_in151,
probe_in152,
probe_in153,
probe_in154,
probe_in155,
probe_in156,
probe_in157,
probe_in158,
probe_in159,
probe_in160,
probe_in161,
probe_in162,
probe_in163,
probe_in164,
probe_in165,
probe_in166,
probe_in167,
probe_in168,
probe_in169,
probe_in170,
probe_in171,
probe_in172,
probe_in173,
probe_in174,
probe_in175,
probe_in176,
probe_in177,
probe_in178,
probe_in179,
probe_in180,
probe_in181,
probe_in182,
probe_in183,
probe_in184,
probe_in185,
probe_in186,
probe_in187,
probe_in188,
probe_in189,
probe_in190,
probe_in191,
probe_in192,
probe_in193,
probe_in194,
probe_in195,
probe_in196,
probe_in197,
probe_in198,
probe_in199,
probe_in200,
probe_in201,
probe_in202,
probe_in203,
probe_in204,
probe_in205,
probe_in206,
probe_in207,
probe_in208,
probe_in209,
probe_in210,
probe_in211,
probe_in212,
probe_in213,
probe_in214,
probe_in215,
probe_in216,
probe_in217,
probe_in218,
probe_in219,
probe_in220,
probe_in221,
probe_in222,
probe_in223,
probe_in224,
probe_in225,
probe_in226,
probe_in227,
probe_in228,
probe_in229,
probe_in230,
probe_in231,
probe_in232,
probe_in233,
probe_in234,
probe_in235,
probe_in236,
probe_in237,
probe_in238,
probe_in239,
probe_in240,
probe_in241,
probe_in242,
probe_in243,
probe_in244,
probe_in245,
probe_in246,
probe_in247,
probe_in248,
probe_in249,
probe_in250,
probe_in251,
probe_in252,
probe_in253,
probe_in254,
probe_in255,
sl_iport0,
sl_oport0,
probe_out0,
probe_out1,
probe_out2,
probe_out3,
probe_out4,
probe_out5,
probe_out6,
probe_out7,
probe_out8,
probe_out9,
probe_out10,
probe_out11,
probe_out12,
probe_out13,
probe_out14,
probe_out15,
probe_out16,
probe_out17,
probe_out18,
probe_out19,
probe_out20,
probe_out21,
probe_out22,
probe_out23,
probe_out24,
probe_out25,
probe_out26,
probe_out27,
probe_out28,
probe_out29,
probe_out30,
probe_out31,
probe_out32,
probe_out33,
probe_out34,
probe_out35,
probe_out36,
probe_out37,
probe_out38,
probe_out39,
probe_out40,
probe_out41,
probe_out42,
probe_out43,
probe_out44,
probe_out45,
probe_out46,
probe_out47,
probe_out48,
probe_out49,
probe_out50,
probe_out51,
probe_out52,
probe_out53,
probe_out54,
probe_out55,
probe_out56,
probe_out57,
probe_out58,
probe_out59,
probe_out60,
probe_out61,
probe_out62,
probe_out63,
probe_out64,
probe_out65,
probe_out66,
probe_out67,
probe_out68,
probe_out69,
probe_out70,
probe_out71,
probe_out72,
probe_out73,
probe_out74,
probe_out75,
probe_out76,
probe_out77,
probe_out78,
probe_out79,
probe_out80,
probe_out81,
probe_out82,
probe_out83,
probe_out84,
probe_out85,
probe_out86,
probe_out87,
probe_out88,
probe_out89,
probe_out90,
probe_out91,
probe_out92,
probe_out93,
probe_out94,
probe_out95,
probe_out96,
probe_out97,
probe_out98,
probe_out99,
probe_out100,
probe_out101,
probe_out102,
probe_out103,
probe_out104,
probe_out105,
probe_out106,
probe_out107,
probe_out108,
probe_out109,
probe_out110,
probe_out111,
probe_out112,
probe_out113,
probe_out114,
probe_out115,
probe_out116,
probe_out117,
probe_out118,
probe_out119,
probe_out120,
probe_out121,
probe_out122,
probe_out123,
probe_out124,
probe_out125,
probe_out126,
probe_out127,
probe_out128,
probe_out129,
probe_out130,
probe_out131,
probe_out132,
probe_out133,
probe_out134,
probe_out135,
probe_out136,
probe_out137,
probe_out138,
probe_out139,
probe_out140,
probe_out141,
probe_out142,
probe_out143,
probe_out144,
probe_out145,
probe_out146,
probe_out147,
probe_out148,
probe_out149,
probe_out150,
probe_out151,
probe_out152,
probe_out153,
probe_out154,
probe_out155,
probe_out156,
probe_out157,
probe_out158,
probe_out159,
probe_out160,
probe_out161,
probe_out162,
probe_out163,
probe_out164,
probe_out165,
probe_out166,
probe_out167,
probe_out168,
probe_out169,
probe_out170,
probe_out171,
probe_out172,
probe_out173,
probe_out174,
probe_out175,
probe_out176,
probe_out177,
probe_out178,
probe_out179,
probe_out180,
probe_out181,
probe_out182,
probe_out183,
probe_out184,
probe_out185,
probe_out186,
probe_out187,
probe_out188,
probe_out189,
probe_out190,
probe_out191,
probe_out192,
probe_out193,
probe_out194,
probe_out195,
probe_out196,
probe_out197,
probe_out198,
probe_out199,
probe_out200,
probe_out201,
probe_out202,
probe_out203,
probe_out204,
probe_out205,
probe_out206,
probe_out207,
probe_out208,
probe_out209,
probe_out210,
probe_out211,
probe_out212,
probe_out213,
probe_out214,
probe_out215,
probe_out216,
probe_out217,
probe_out218,
probe_out219,
probe_out220,
probe_out221,
probe_out222,
probe_out223,
probe_out224,
probe_out225,
probe_out226,
probe_out227,
probe_out228,
probe_out229,
probe_out230,
probe_out231,
probe_out232,
probe_out233,
probe_out234,
probe_out235,
probe_out236,
probe_out237,
probe_out238,
probe_out239,
probe_out240,
probe_out241,
probe_out242,
probe_out243,
probe_out244,
probe_out245,
probe_out246,
probe_out247,
probe_out248,
probe_out249,
probe_out250,
probe_out251,
probe_out252,
probe_out253,
probe_out254,
probe_out255);
input clk;
input [0:0]probe_in0;
input [0:0]probe_in1;
input [0:0]probe_in2;
input [0:0]probe_in3;
input [0:0]probe_in4;
input [0:0]probe_in5;
input [0:0]probe_in6;
input [0:0]probe_in7;
input [0:0]probe_in8;
input [0:0]probe_in9;
input [0:0]probe_in10;
input [0:0]probe_in11;
input [0:0]probe_in12;
input [0:0]probe_in13;
input [0:0]probe_in14;
input [0:0]probe_in15;
input [0:0]probe_in16;
input [0:0]probe_in17;
input [0:0]probe_in18;
input [0:0]probe_in19;
input [0:0]probe_in20;
input [0:0]probe_in21;
input [0:0]probe_in22;
input [0:0]probe_in23;
input [0:0]probe_in24;
input [0:0]probe_in25;
input [0:0]probe_in26;
input [0:0]probe_in27;
input [0:0]probe_in28;
input [0:0]probe_in29;
input [0:0]probe_in30;
input [0:0]probe_in31;
input [0:0]probe_in32;
input [0:0]probe_in33;
input [0:0]probe_in34;
input [0:0]probe_in35;
input [0:0]probe_in36;
input [0:0]probe_in37;
input [0:0]probe_in38;
input [0:0]probe_in39;
input [0:0]probe_in40;
input [0:0]probe_in41;
input [0:0]probe_in42;
input [0:0]probe_in43;
input [0:0]probe_in44;
input [0:0]probe_in45;
input [0:0]probe_in46;
input [0:0]probe_in47;
input [0:0]probe_in48;
input [0:0]probe_in49;
input [0:0]probe_in50;
input [0:0]probe_in51;
input [0:0]probe_in52;
input [0:0]probe_in53;
input [0:0]probe_in54;
input [0:0]probe_in55;
input [0:0]probe_in56;
input [0:0]probe_in57;
input [0:0]probe_in58;
input [0:0]probe_in59;
input [0:0]probe_in60;
input [0:0]probe_in61;
input [0:0]probe_in62;
input [0:0]probe_in63;
input [0:0]probe_in64;
input [0:0]probe_in65;
input [0:0]probe_in66;
input [0:0]probe_in67;
input [0:0]probe_in68;
input [0:0]probe_in69;
input [0:0]probe_in70;
input [0:0]probe_in71;
input [0:0]probe_in72;
input [0:0]probe_in73;
input [0:0]probe_in74;
input [0:0]probe_in75;
input [0:0]probe_in76;
input [0:0]probe_in77;
input [0:0]probe_in78;
input [0:0]probe_in79;
input [0:0]probe_in80;
input [0:0]probe_in81;
input [0:0]probe_in82;
input [0:0]probe_in83;
input [0:0]probe_in84;
input [0:0]probe_in85;
input [0:0]probe_in86;
input [0:0]probe_in87;
input [0:0]probe_in88;
input [0:0]probe_in89;
input [0:0]probe_in90;
input [0:0]probe_in91;
input [0:0]probe_in92;
input [0:0]probe_in93;
input [0:0]probe_in94;
input [0:0]probe_in95;
input [0:0]probe_in96;
input [0:0]probe_in97;
input [0:0]probe_in98;
input [0:0]probe_in99;
input [0:0]probe_in100;
input [0:0]probe_in101;
input [0:0]probe_in102;
input [0:0]probe_in103;
input [0:0]probe_in104;
input [0:0]probe_in105;
input [0:0]probe_in106;
input [0:0]probe_in107;
input [0:0]probe_in108;
input [0:0]probe_in109;
input [0:0]probe_in110;
input [0:0]probe_in111;
input [0:0]probe_in112;
input [0:0]probe_in113;
input [0:0]probe_in114;
input [0:0]probe_in115;
input [0:0]probe_in116;
input [0:0]probe_in117;
input [0:0]probe_in118;
input [0:0]probe_in119;
input [0:0]probe_in120;
input [0:0]probe_in121;
input [0:0]probe_in122;
input [0:0]probe_in123;
input [0:0]probe_in124;
input [0:0]probe_in125;
input [0:0]probe_in126;
input [0:0]probe_in127;
input [0:0]probe_in128;
input [0:0]probe_in129;
input [0:0]probe_in130;
input [0:0]probe_in131;
input [0:0]probe_in132;
input [0:0]probe_in133;
input [0:0]probe_in134;
input [0:0]probe_in135;
input [0:0]probe_in136;
input [0:0]probe_in137;
input [0:0]probe_in138;
input [0:0]probe_in139;
input [0:0]probe_in140;
input [0:0]probe_in141;
input [0:0]probe_in142;
input [0:0]probe_in143;
input [0:0]probe_in144;
input [0:0]probe_in145;
input [0:0]probe_in146;
input [0:0]probe_in147;
input [0:0]probe_in148;
input [0:0]probe_in149;
input [0:0]probe_in150;
input [0:0]probe_in151;
input [0:0]probe_in152;
input [0:0]probe_in153;
input [0:0]probe_in154;
input [0:0]probe_in155;
input [0:0]probe_in156;
input [0:0]probe_in157;
input [0:0]probe_in158;
input [0:0]probe_in159;
input [0:0]probe_in160;
input [0:0]probe_in161;
input [0:0]probe_in162;
input [0:0]probe_in163;
input [0:0]probe_in164;
input [0:0]probe_in165;
input [0:0]probe_in166;
input [0:0]probe_in167;
input [0:0]probe_in168;
input [0:0]probe_in169;
input [0:0]probe_in170;
input [0:0]probe_in171;
input [0:0]probe_in172;
input [0:0]probe_in173;
input [0:0]probe_in174;
input [0:0]probe_in175;
input [0:0]probe_in176;
input [0:0]probe_in177;
input [0:0]probe_in178;
input [0:0]probe_in179;
input [0:0]probe_in180;
input [0:0]probe_in181;
input [0:0]probe_in182;
input [0:0]probe_in183;
input [0:0]probe_in184;
input [0:0]probe_in185;
input [0:0]probe_in186;
input [0:0]probe_in187;
input [0:0]probe_in188;
input [0:0]probe_in189;
input [0:0]probe_in190;
input [0:0]probe_in191;
input [0:0]probe_in192;
input [0:0]probe_in193;
input [0:0]probe_in194;
input [0:0]probe_in195;
input [0:0]probe_in196;
input [0:0]probe_in197;
input [0:0]probe_in198;
input [0:0]probe_in199;
input [0:0]probe_in200;
input [0:0]probe_in201;
input [0:0]probe_in202;
input [0:0]probe_in203;
input [0:0]probe_in204;
input [0:0]probe_in205;
input [0:0]probe_in206;
input [0:0]probe_in207;
input [0:0]probe_in208;
input [0:0]probe_in209;
input [0:0]probe_in210;
input [0:0]probe_in211;
input [0:0]probe_in212;
input [0:0]probe_in213;
input [0:0]probe_in214;
input [0:0]probe_in215;
input [0:0]probe_in216;
input [0:0]probe_in217;
input [0:0]probe_in218;
input [0:0]probe_in219;
input [0:0]probe_in220;
input [0:0]probe_in221;
input [0:0]probe_in222;
input [0:0]probe_in223;
input [0:0]probe_in224;
input [0:0]probe_in225;
input [0:0]probe_in226;
input [0:0]probe_in227;
input [0:0]probe_in228;
input [0:0]probe_in229;
input [0:0]probe_in230;
input [0:0]probe_in231;
input [0:0]probe_in232;
input [0:0]probe_in233;
input [0:0]probe_in234;
input [0:0]probe_in235;
input [0:0]probe_in236;
input [0:0]probe_in237;
input [0:0]probe_in238;
input [0:0]probe_in239;
input [0:0]probe_in240;
input [0:0]probe_in241;
input [0:0]probe_in242;
input [0:0]probe_in243;
input [0:0]probe_in244;
input [0:0]probe_in245;
input [0:0]probe_in246;
input [0:0]probe_in247;
input [0:0]probe_in248;
input [0:0]probe_in249;
input [0:0]probe_in250;
input [0:0]probe_in251;
input [0:0]probe_in252;
input [0:0]probe_in253;
input [0:0]probe_in254;
input [0:0]probe_in255;
(* dont_touch = "true" *) input [36:0]sl_iport0;
(* dont_touch = "true" *) output [16:0]sl_oport0;
output [0:0]probe_out0;
output [0:0]probe_out1;
output [0:0]probe_out2;
output [0:0]probe_out3;
output [0:0]probe_out4;
output [0:0]probe_out5;
output [0:0]probe_out6;
output [0:0]probe_out7;
output [0:0]probe_out8;
output [0:0]probe_out9;
output [0:0]probe_out10;
output [0:0]probe_out11;
output [0:0]probe_out12;
output [0:0]probe_out13;
output [0:0]probe_out14;
output [0:0]probe_out15;
output [0:0]probe_out16;
output [0:0]probe_out17;
output [0:0]probe_out18;
output [0:0]probe_out19;
output [0:0]probe_out20;
output [0:0]probe_out21;
output [0:0]probe_out22;
output [0:0]probe_out23;
output [0:0]probe_out24;
output [0:0]probe_out25;
output [0:0]probe_out26;
output [0:0]probe_out27;
output [0:0]probe_out28;
output [0:0]probe_out29;
output [0:0]probe_out30;
output [0:0]probe_out31;
output [0:0]probe_out32;
output [0:0]probe_out33;
output [0:0]probe_out34;
output [0:0]probe_out35;
output [0:0]probe_out36;
output [0:0]probe_out37;
output [0:0]probe_out38;
output [0:0]probe_out39;
output [0:0]probe_out40;
output [0:0]probe_out41;
output [0:0]probe_out42;
output [0:0]probe_out43;
output [0:0]probe_out44;
output [0:0]probe_out45;
output [0:0]probe_out46;
output [0:0]probe_out47;
output [0:0]probe_out48;
output [0:0]probe_out49;
output [0:0]probe_out50;
output [0:0]probe_out51;
output [0:0]probe_out52;
output [0:0]probe_out53;
output [0:0]probe_out54;
output [0:0]probe_out55;
output [0:0]probe_out56;
output [0:0]probe_out57;
output [0:0]probe_out58;
output [0:0]probe_out59;
output [0:0]probe_out60;
output [0:0]probe_out61;
output [0:0]probe_out62;
output [0:0]probe_out63;
output [0:0]probe_out64;
output [0:0]probe_out65;
output [0:0]probe_out66;
output [0:0]probe_out67;
output [0:0]probe_out68;
output [0:0]probe_out69;
output [0:0]probe_out70;
output [0:0]probe_out71;
output [0:0]probe_out72;
output [0:0]probe_out73;
output [0:0]probe_out74;
output [0:0]probe_out75;
output [0:0]probe_out76;
output [0:0]probe_out77;
output [0:0]probe_out78;
output [0:0]probe_out79;
output [0:0]probe_out80;
output [0:0]probe_out81;
output [0:0]probe_out82;
output [0:0]probe_out83;
output [0:0]probe_out84;
output [0:0]probe_out85;
output [0:0]probe_out86;
output [0:0]probe_out87;
output [0:0]probe_out88;
output [0:0]probe_out89;
output [0:0]probe_out90;
output [0:0]probe_out91;
output [0:0]probe_out92;
output [0:0]probe_out93;
output [0:0]probe_out94;
output [0:0]probe_out95;
output [0:0]probe_out96;
output [0:0]probe_out97;
output [0:0]probe_out98;
output [0:0]probe_out99;
output [0:0]probe_out100;
output [0:0]probe_out101;
output [0:0]probe_out102;
output [0:0]probe_out103;
output [0:0]probe_out104;
output [0:0]probe_out105;
output [0:0]probe_out106;
output [0:0]probe_out107;
output [0:0]probe_out108;
output [0:0]probe_out109;
output [0:0]probe_out110;
output [0:0]probe_out111;
output [0:0]probe_out112;
output [0:0]probe_out113;
output [0:0]probe_out114;
output [0:0]probe_out115;
output [0:0]probe_out116;
output [0:0]probe_out117;
output [0:0]probe_out118;
output [0:0]probe_out119;
output [0:0]probe_out120;
output [0:0]probe_out121;
output [0:0]probe_out122;
output [0:0]probe_out123;
output [0:0]probe_out124;
output [0:0]probe_out125;
output [0:0]probe_out126;
output [0:0]probe_out127;
output [0:0]probe_out128;
output [0:0]probe_out129;
output [0:0]probe_out130;
output [0:0]probe_out131;
output [0:0]probe_out132;
output [0:0]probe_out133;
output [0:0]probe_out134;
output [0:0]probe_out135;
output [0:0]probe_out136;
output [0:0]probe_out137;
output [0:0]probe_out138;
output [0:0]probe_out139;
output [0:0]probe_out140;
output [0:0]probe_out141;
output [0:0]probe_out142;
output [0:0]probe_out143;
output [0:0]probe_out144;
output [0:0]probe_out145;
output [0:0]probe_out146;
output [0:0]probe_out147;
output [0:0]probe_out148;
output [0:0]probe_out149;
output [0:0]probe_out150;
output [0:0]probe_out151;
output [0:0]probe_out152;
output [0:0]probe_out153;
output [0:0]probe_out154;
output [0:0]probe_out155;
output [0:0]probe_out156;
output [0:0]probe_out157;
output [0:0]probe_out158;
output [0:0]probe_out159;
output [0:0]probe_out160;
output [0:0]probe_out161;
output [0:0]probe_out162;
output [0:0]probe_out163;
output [0:0]probe_out164;
output [0:0]probe_out165;
output [0:0]probe_out166;
output [0:0]probe_out167;
output [0:0]probe_out168;
output [0:0]probe_out169;
output [0:0]probe_out170;
output [0:0]probe_out171;
output [0:0]probe_out172;
output [0:0]probe_out173;
output [0:0]probe_out174;
output [0:0]probe_out175;
output [0:0]probe_out176;
output [0:0]probe_out177;
output [0:0]probe_out178;
output [0:0]probe_out179;
output [0:0]probe_out180;
output [0:0]probe_out181;
output [0:0]probe_out182;
output [0:0]probe_out183;
output [0:0]probe_out184;
output [0:0]probe_out185;
output [0:0]probe_out186;
output [0:0]probe_out187;
output [0:0]probe_out188;
output [0:0]probe_out189;
output [0:0]probe_out190;
output [0:0]probe_out191;
output [0:0]probe_out192;
output [0:0]probe_out193;
output [0:0]probe_out194;
output [0:0]probe_out195;
output [0:0]probe_out196;
output [0:0]probe_out197;
output [0:0]probe_out198;
output [0:0]probe_out199;
output [0:0]probe_out200;
output [0:0]probe_out201;
output [0:0]probe_out202;
output [0:0]probe_out203;
output [0:0]probe_out204;
output [0:0]probe_out205;
output [0:0]probe_out206;
output [0:0]probe_out207;
output [0:0]probe_out208;
output [0:0]probe_out209;
output [0:0]probe_out210;
output [0:0]probe_out211;
output [0:0]probe_out212;
output [0:0]probe_out213;
output [0:0]probe_out214;
output [0:0]probe_out215;
output [0:0]probe_out216;
output [0:0]probe_out217;
output [0:0]probe_out218;
output [0:0]probe_out219;
output [0:0]probe_out220;
output [0:0]probe_out221;
output [0:0]probe_out222;
output [0:0]probe_out223;
output [0:0]probe_out224;
output [0:0]probe_out225;
output [0:0]probe_out226;
output [0:0]probe_out227;
output [0:0]probe_out228;
output [0:0]probe_out229;
output [0:0]probe_out230;
output [0:0]probe_out231;
output [0:0]probe_out232;
output [0:0]probe_out233;
output [0:0]probe_out234;
output [0:0]probe_out235;
output [0:0]probe_out236;
output [0:0]probe_out237;
output [0:0]probe_out238;
output [0:0]probe_out239;
output [0:0]probe_out240;
output [0:0]probe_out241;
output [0:0]probe_out242;
output [0:0]probe_out243;
output [0:0]probe_out244;
output [0:0]probe_out245;
output [0:0]probe_out246;
output [0:0]probe_out247;
output [0:0]probe_out248;
output [0:0]probe_out249;
output [0:0]probe_out250;
output [0:0]probe_out251;
output [0:0]probe_out252;
output [0:0]probe_out253;
output [0:0]probe_out254;
output [0:0]probe_out255;
wire \<const0> ;
wire [8:0]Bus_Data_out;
wire DECODER_INST_n_1;
wire DECODER_INST_n_2;
wire DECODER_INST_n_3;
wire DECODER_INST_n_4;
wire [16:0]bus_addr;
(* DONT_TOUCH *) wire bus_clk;
wire \bus_data_int_reg_n_0_[0] ;
wire \bus_data_int_reg_n_0_[10] ;
wire \bus_data_int_reg_n_0_[11] ;
wire \bus_data_int_reg_n_0_[12] ;
wire \bus_data_int_reg_n_0_[13] ;
wire \bus_data_int_reg_n_0_[14] ;
wire \bus_data_int_reg_n_0_[15] ;
wire \bus_data_int_reg_n_0_[2] ;
wire \bus_data_int_reg_n_0_[3] ;
wire \bus_data_int_reg_n_0_[4] ;
wire \bus_data_int_reg_n_0_[5] ;
wire \bus_data_int_reg_n_0_[6] ;
wire \bus_data_int_reg_n_0_[7] ;
wire \bus_data_int_reg_n_0_[8] ;
wire \bus_data_int_reg_n_0_[9] ;
wire bus_den;
wire [15:0]bus_di;
wire [15:0]bus_do;
wire bus_drdy;
wire bus_dwe;
wire bus_rst;
wire clk;
wire p_0_in;
wire [0:0]probe_in0;
wire [0:0]probe_in1;
wire [0:0]probe_in2;
(* DONT_TOUCH *) wire [36:0]sl_iport0;
(* DONT_TOUCH *) wire [16:0]sl_oport0;
assign probe_out0[0] = \<const0> ;
assign probe_out1[0] = \<const0> ;
assign probe_out10[0] = \<const0> ;
assign probe_out100[0] = \<const0> ;
assign probe_out101[0] = \<const0> ;
assign probe_out102[0] = \<const0> ;
assign probe_out103[0] = \<const0> ;
assign probe_out104[0] = \<const0> ;
assign probe_out105[0] = \<const0> ;
assign probe_out106[0] = \<const0> ;
assign probe_out107[0] = \<const0> ;
assign probe_out108[0] = \<const0> ;
assign probe_out109[0] = \<const0> ;
assign probe_out11[0] = \<const0> ;
assign probe_out110[0] = \<const0> ;
assign probe_out111[0] = \<const0> ;
assign probe_out112[0] = \<const0> ;
assign probe_out113[0] = \<const0> ;
assign probe_out114[0] = \<const0> ;
assign probe_out115[0] = \<const0> ;
assign probe_out116[0] = \<const0> ;
assign probe_out117[0] = \<const0> ;
assign probe_out118[0] = \<const0> ;
assign probe_out119[0] = \<const0> ;
assign probe_out12[0] = \<const0> ;
assign probe_out120[0] = \<const0> ;
assign probe_out121[0] = \<const0> ;
assign probe_out122[0] = \<const0> ;
assign probe_out123[0] = \<const0> ;
assign probe_out124[0] = \<const0> ;
assign probe_out125[0] = \<const0> ;
assign probe_out126[0] = \<const0> ;
assign probe_out127[0] = \<const0> ;
assign probe_out128[0] = \<const0> ;
assign probe_out129[0] = \<const0> ;
assign probe_out13[0] = \<const0> ;
assign probe_out130[0] = \<const0> ;
assign probe_out131[0] = \<const0> ;
assign probe_out132[0] = \<const0> ;
assign probe_out133[0] = \<const0> ;
assign probe_out134[0] = \<const0> ;
assign probe_out135[0] = \<const0> ;
assign probe_out136[0] = \<const0> ;
assign probe_out137[0] = \<const0> ;
assign probe_out138[0] = \<const0> ;
assign probe_out139[0] = \<const0> ;
assign probe_out14[0] = \<const0> ;
assign probe_out140[0] = \<const0> ;
assign probe_out141[0] = \<const0> ;
assign probe_out142[0] = \<const0> ;
assign probe_out143[0] = \<const0> ;
assign probe_out144[0] = \<const0> ;
assign probe_out145[0] = \<const0> ;
assign probe_out146[0] = \<const0> ;
assign probe_out147[0] = \<const0> ;
assign probe_out148[0] = \<const0> ;
assign probe_out149[0] = \<const0> ;
assign probe_out15[0] = \<const0> ;
assign probe_out150[0] = \<const0> ;
assign probe_out151[0] = \<const0> ;
assign probe_out152[0] = \<const0> ;
assign probe_out153[0] = \<const0> ;
assign probe_out154[0] = \<const0> ;
assign probe_out155[0] = \<const0> ;
assign probe_out156[0] = \<const0> ;
assign probe_out157[0] = \<const0> ;
assign probe_out158[0] = \<const0> ;
assign probe_out159[0] = \<const0> ;
assign probe_out16[0] = \<const0> ;
assign probe_out160[0] = \<const0> ;
assign probe_out161[0] = \<const0> ;
assign probe_out162[0] = \<const0> ;
assign probe_out163[0] = \<const0> ;
assign probe_out164[0] = \<const0> ;
assign probe_out165[0] = \<const0> ;
assign probe_out166[0] = \<const0> ;
assign probe_out167[0] = \<const0> ;
assign probe_out168[0] = \<const0> ;
assign probe_out169[0] = \<const0> ;
assign probe_out17[0] = \<const0> ;
assign probe_out170[0] = \<const0> ;
assign probe_out171[0] = \<const0> ;
assign probe_out172[0] = \<const0> ;
assign probe_out173[0] = \<const0> ;
assign probe_out174[0] = \<const0> ;
assign probe_out175[0] = \<const0> ;
assign probe_out176[0] = \<const0> ;
assign probe_out177[0] = \<const0> ;
assign probe_out178[0] = \<const0> ;
assign probe_out179[0] = \<const0> ;
assign probe_out18[0] = \<const0> ;
assign probe_out180[0] = \<const0> ;
assign probe_out181[0] = \<const0> ;
assign probe_out182[0] = \<const0> ;
assign probe_out183[0] = \<const0> ;
assign probe_out184[0] = \<const0> ;
assign probe_out185[0] = \<const0> ;
assign probe_out186[0] = \<const0> ;
assign probe_out187[0] = \<const0> ;
assign probe_out188[0] = \<const0> ;
assign probe_out189[0] = \<const0> ;
assign probe_out19[0] = \<const0> ;
assign probe_out190[0] = \<const0> ;
assign probe_out191[0] = \<const0> ;
assign probe_out192[0] = \<const0> ;
assign probe_out193[0] = \<const0> ;
assign probe_out194[0] = \<const0> ;
assign probe_out195[0] = \<const0> ;
assign probe_out196[0] = \<const0> ;
assign probe_out197[0] = \<const0> ;
assign probe_out198[0] = \<const0> ;
assign probe_out199[0] = \<const0> ;
assign probe_out2[0] = \<const0> ;
assign probe_out20[0] = \<const0> ;
assign probe_out200[0] = \<const0> ;
assign probe_out201[0] = \<const0> ;
assign probe_out202[0] = \<const0> ;
assign probe_out203[0] = \<const0> ;
assign probe_out204[0] = \<const0> ;
assign probe_out205[0] = \<const0> ;
assign probe_out206[0] = \<const0> ;
assign probe_out207[0] = \<const0> ;
assign probe_out208[0] = \<const0> ;
assign probe_out209[0] = \<const0> ;
assign probe_out21[0] = \<const0> ;
assign probe_out210[0] = \<const0> ;
assign probe_out211[0] = \<const0> ;
assign probe_out212[0] = \<const0> ;
assign probe_out213[0] = \<const0> ;
assign probe_out214[0] = \<const0> ;
assign probe_out215[0] = \<const0> ;
assign probe_out216[0] = \<const0> ;
assign probe_out217[0] = \<const0> ;
assign probe_out218[0] = \<const0> ;
assign probe_out219[0] = \<const0> ;
assign probe_out22[0] = \<const0> ;
assign probe_out220[0] = \<const0> ;
assign probe_out221[0] = \<const0> ;
assign probe_out222[0] = \<const0> ;
assign probe_out223[0] = \<const0> ;
assign probe_out224[0] = \<const0> ;
assign probe_out225[0] = \<const0> ;
assign probe_out226[0] = \<const0> ;
assign probe_out227[0] = \<const0> ;
assign probe_out228[0] = \<const0> ;
assign probe_out229[0] = \<const0> ;
assign probe_out23[0] = \<const0> ;
assign probe_out230[0] = \<const0> ;
assign probe_out231[0] = \<const0> ;
assign probe_out232[0] = \<const0> ;
assign probe_out233[0] = \<const0> ;
assign probe_out234[0] = \<const0> ;
assign probe_out235[0] = \<const0> ;
assign probe_out236[0] = \<const0> ;
assign probe_out237[0] = \<const0> ;
assign probe_out238[0] = \<const0> ;
assign probe_out239[0] = \<const0> ;
assign probe_out24[0] = \<const0> ;
assign probe_out240[0] = \<const0> ;
assign probe_out241[0] = \<const0> ;
assign probe_out242[0] = \<const0> ;
assign probe_out243[0] = \<const0> ;
assign probe_out244[0] = \<const0> ;
assign probe_out245[0] = \<const0> ;
assign probe_out246[0] = \<const0> ;
assign probe_out247[0] = \<const0> ;
assign probe_out248[0] = \<const0> ;
assign probe_out249[0] = \<const0> ;
assign probe_out25[0] = \<const0> ;
assign probe_out250[0] = \<const0> ;
assign probe_out251[0] = \<const0> ;
assign probe_out252[0] = \<const0> ;
assign probe_out253[0] = \<const0> ;
assign probe_out254[0] = \<const0> ;
assign probe_out255[0] = \<const0> ;
assign probe_out26[0] = \<const0> ;
assign probe_out27[0] = \<const0> ;
assign probe_out28[0] = \<const0> ;
assign probe_out29[0] = \<const0> ;
assign probe_out3[0] = \<const0> ;
assign probe_out30[0] = \<const0> ;
assign probe_out31[0] = \<const0> ;
assign probe_out32[0] = \<const0> ;
assign probe_out33[0] = \<const0> ;
assign probe_out34[0] = \<const0> ;
assign probe_out35[0] = \<const0> ;
assign probe_out36[0] = \<const0> ;
assign probe_out37[0] = \<const0> ;
assign probe_out38[0] = \<const0> ;
assign probe_out39[0] = \<const0> ;
assign probe_out4[0] = \<const0> ;
assign probe_out40[0] = \<const0> ;
assign probe_out41[0] = \<const0> ;
assign probe_out42[0] = \<const0> ;
assign probe_out43[0] = \<const0> ;
assign probe_out44[0] = \<const0> ;
assign probe_out45[0] = \<const0> ;
assign probe_out46[0] = \<const0> ;
assign probe_out47[0] = \<const0> ;
assign probe_out48[0] = \<const0> ;
assign probe_out49[0] = \<const0> ;
assign probe_out5[0] = \<const0> ;
assign probe_out50[0] = \<const0> ;
assign probe_out51[0] = \<const0> ;
assign probe_out52[0] = \<const0> ;
assign probe_out53[0] = \<const0> ;
assign probe_out54[0] = \<const0> ;
assign probe_out55[0] = \<const0> ;
assign probe_out56[0] = \<const0> ;
assign probe_out57[0] = \<const0> ;
assign probe_out58[0] = \<const0> ;
assign probe_out59[0] = \<const0> ;
assign probe_out6[0] = \<const0> ;
assign probe_out60[0] = \<const0> ;
assign probe_out61[0] = \<const0> ;
assign probe_out62[0] = \<const0> ;
assign probe_out63[0] = \<const0> ;
assign probe_out64[0] = \<const0> ;
assign probe_out65[0] = \<const0> ;
assign probe_out66[0] = \<const0> ;
assign probe_out67[0] = \<const0> ;
assign probe_out68[0] = \<const0> ;
assign probe_out69[0] = \<const0> ;
assign probe_out7[0] = \<const0> ;
assign probe_out70[0] = \<const0> ;
assign probe_out71[0] = \<const0> ;
assign probe_out72[0] = \<const0> ;
assign probe_out73[0] = \<const0> ;
assign probe_out74[0] = \<const0> ;
assign probe_out75[0] = \<const0> ;
assign probe_out76[0] = \<const0> ;
assign probe_out77[0] = \<const0> ;
assign probe_out78[0] = \<const0> ;
assign probe_out79[0] = \<const0> ;
assign probe_out8[0] = \<const0> ;
assign probe_out80[0] = \<const0> ;
assign probe_out81[0] = \<const0> ;
assign probe_out82[0] = \<const0> ;
assign probe_out83[0] = \<const0> ;
assign probe_out84[0] = \<const0> ;
assign probe_out85[0] = \<const0> ;
assign probe_out86[0] = \<const0> ;
assign probe_out87[0] = \<const0> ;
assign probe_out88[0] = \<const0> ;
assign probe_out89[0] = \<const0> ;
assign probe_out9[0] = \<const0> ;
assign probe_out90[0] = \<const0> ;
assign probe_out91[0] = \<const0> ;
assign probe_out92[0] = \<const0> ;
assign probe_out93[0] = \<const0> ;
assign probe_out94[0] = \<const0> ;
assign probe_out95[0] = \<const0> ;
assign probe_out96[0] = \<const0> ;
assign probe_out97[0] = \<const0> ;
assign probe_out98[0] = \<const0> ;
assign probe_out99[0] = \<const0> ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_decoder DECODER_INST
(.\Bus_Data_out_reg[8] (Bus_Data_out),
.E(DECODER_INST_n_4),
.Q({\bus_data_int_reg_n_0_[15] ,\bus_data_int_reg_n_0_[14] ,\bus_data_int_reg_n_0_[13] ,\bus_data_int_reg_n_0_[12] ,\bus_data_int_reg_n_0_[11] ,\bus_data_int_reg_n_0_[10] ,\bus_data_int_reg_n_0_[9] ,\bus_data_int_reg_n_0_[8] ,\bus_data_int_reg_n_0_[7] ,\bus_data_int_reg_n_0_[6] ,\bus_data_int_reg_n_0_[5] ,\bus_data_int_reg_n_0_[4] ,\bus_data_int_reg_n_0_[3] ,\bus_data_int_reg_n_0_[2] ,p_0_in,\bus_data_int_reg_n_0_[0] }),
.out(bus_clk),
.s_daddr_o(bus_addr),
.s_den_o(bus_den),
.s_do_i(bus_do),
.s_drdy_i(bus_drdy),
.s_dwe_o(bus_dwe),
.s_rst_o(bus_rst),
.\wr_en_reg[4]_0 (DECODER_INST_n_1),
.\wr_en_reg[4]_1 (DECODER_INST_n_2),
.\wr_en_reg[4]_2 (DECODER_INST_n_3));
GND GND
(.G(\<const0> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_probe_in_one PROBE_IN_INST
(.D({probe_in2,probe_in1,probe_in0}),
.E(DECODER_INST_n_4),
.Q(Bus_Data_out),
.clk(clk),
.out(bus_clk),
.s_daddr_o(bus_addr[2:0]),
.s_den_o(bus_den),
.s_dwe_o(bus_dwe),
.s_rst_o(bus_rst),
.\wr_en[4]_i_3 (DECODER_INST_n_1),
.\wr_en[4]_i_4 (DECODER_INST_n_3),
.\wr_en[4]_i_5 (DECODER_INST_n_2));
(* C_BUILD_REVISION = "0" *)
(* C_CORE_INFO1 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* C_CORE_INFO2 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* C_CORE_MAJOR_VER = "2" *)
(* C_CORE_MINOR_VER = "0" *)
(* C_CORE_TYPE = "2" *)
(* C_CSE_DRV_VER = "1" *)
(* C_MAJOR_VERSION = "2013" *)
(* C_MINOR_VERSION = "1" *)
(* C_NEXT_SLAVE = "0" *)
(* C_PIPE_IFACE = "0" *)
(* C_USE_TEST_REG = "1" *)
(* C_XDEVICEFAMILY = "kintex7" *)
(* C_XSDB_SLAVE_TYPE = "33" *)
(* DONT_TOUCH *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs U_XSDB_SLAVE
(.s_daddr_o(bus_addr),
.s_dclk_o(bus_clk),
.s_den_o(bus_den),
.s_di_o(bus_di),
.s_do_i(bus_do),
.s_drdy_i(bus_drdy),
.s_dwe_o(bus_dwe),
.s_rst_o(bus_rst),
.sl_iport_i(sl_iport0),
.sl_oport_o(sl_oport0));
FDRE \bus_data_int_reg[0]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[0]),
.Q(\bus_data_int_reg_n_0_[0] ),
.R(1'b0));
FDRE \bus_data_int_reg[10]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[10]),
.Q(\bus_data_int_reg_n_0_[10] ),
.R(1'b0));
FDRE \bus_data_int_reg[11]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[11]),
.Q(\bus_data_int_reg_n_0_[11] ),
.R(1'b0));
FDRE \bus_data_int_reg[12]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[12]),
.Q(\bus_data_int_reg_n_0_[12] ),
.R(1'b0));
FDRE \bus_data_int_reg[13]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[13]),
.Q(\bus_data_int_reg_n_0_[13] ),
.R(1'b0));
FDRE \bus_data_int_reg[14]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[14]),
.Q(\bus_data_int_reg_n_0_[14] ),
.R(1'b0));
FDRE \bus_data_int_reg[15]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[15]),
.Q(\bus_data_int_reg_n_0_[15] ),
.R(1'b0));
FDRE \bus_data_int_reg[1]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[1]),
.Q(p_0_in),
.R(1'b0));
FDRE \bus_data_int_reg[2]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[2]),
.Q(\bus_data_int_reg_n_0_[2] ),
.R(1'b0));
FDRE \bus_data_int_reg[3]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[3]),
.Q(\bus_data_int_reg_n_0_[3] ),
.R(1'b0));
FDRE \bus_data_int_reg[4]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[4]),
.Q(\bus_data_int_reg_n_0_[4] ),
.R(1'b0));
FDRE \bus_data_int_reg[5]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[5]),
.Q(\bus_data_int_reg_n_0_[5] ),
.R(1'b0));
FDRE \bus_data_int_reg[6]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[6]),
.Q(\bus_data_int_reg_n_0_[6] ),
.R(1'b0));
FDRE \bus_data_int_reg[7]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[7]),
.Q(\bus_data_int_reg_n_0_[7] ),
.R(1'b0));
FDRE \bus_data_int_reg[8]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[8]),
.Q(\bus_data_int_reg_n_0_[8] ),
.R(1'b0));
FDRE \bus_data_int_reg[9]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[9]),
.Q(\bus_data_int_reg_n_0_[9] ),
.R(1'b0));
endmodule
(* C_BUILD_REVISION = "0" *) (* C_CORE_INFO1 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_CORE_INFO2 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* C_CORE_MAJOR_VER = "2" *) (* C_CORE_MINOR_VER = "0" *) (* C_CORE_TYPE = "2" *)
(* C_CSE_DRV_VER = "1" *) (* C_MAJOR_VERSION = "2013" *) (* C_MINOR_VERSION = "1" *)
(* C_NEXT_SLAVE = "0" *) (* C_PIPE_IFACE = "0" *) (* C_USE_TEST_REG = "1" *)
(* C_XDEVICEFAMILY = "kintex7" *) (* C_XSDB_SLAVE_TYPE = "33" *) (* dont_touch = "true" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs
(s_rst_o,
s_dclk_o,
s_den_o,
s_dwe_o,
s_daddr_o,
s_di_o,
sl_oport_o,
s_do_i,
sl_iport_i,
s_drdy_i);
output s_rst_o;
output s_dclk_o;
output s_den_o;
output s_dwe_o;
output [16:0]s_daddr_o;
output [15:0]s_di_o;
output [16:0]sl_oport_o;
input [15:0]s_do_i;
input [36:0]sl_iport_i;
input s_drdy_i;
wire [8:0]reg_do;
wire \reg_do[10]_i_1_n_0 ;
wire \reg_do[10]_i_2_n_0 ;
wire \reg_do[15]_i_1_n_0 ;
wire \reg_do[1]_i_2_n_0 ;
wire \reg_do[2]_i_1_n_0 ;
wire \reg_do[3]_i_1_n_0 ;
wire \reg_do[4]_i_1_n_0 ;
wire \reg_do[5]_i_2_n_0 ;
wire \reg_do[6]_i_1_n_0 ;
wire \reg_do[7]_i_1_n_0 ;
wire \reg_do[8]_i_2_n_0 ;
wire \reg_do[9]_i_1_n_0 ;
wire \reg_do_reg_n_0_[0] ;
wire \reg_do_reg_n_0_[10] ;
wire \reg_do_reg_n_0_[11] ;
wire \reg_do_reg_n_0_[12] ;
wire \reg_do_reg_n_0_[13] ;
wire \reg_do_reg_n_0_[14] ;
wire \reg_do_reg_n_0_[15] ;
wire \reg_do_reg_n_0_[1] ;
wire \reg_do_reg_n_0_[2] ;
wire \reg_do_reg_n_0_[3] ;
wire \reg_do_reg_n_0_[4] ;
wire \reg_do_reg_n_0_[5] ;
wire \reg_do_reg_n_0_[6] ;
wire \reg_do_reg_n_0_[7] ;
wire \reg_do_reg_n_0_[8] ;
wire \reg_do_reg_n_0_[9] ;
wire reg_drdy;
wire reg_drdy_i_1_n_0;
wire [15:0]reg_test;
wire reg_test0;
wire s_den_o;
wire s_den_o_INST_0_i_1_n_0;
wire [15:0]s_do_i;
wire s_drdy_i;
wire [36:0]sl_iport_i;
wire [16:0]sl_oport_o;
assign s_daddr_o[16:0] = sl_iport_i[20:4];
assign s_dclk_o = sl_iport_i[1];
assign s_di_o[15:0] = sl_iport_i[36:21];
assign s_dwe_o = sl_iport_i[3];
assign s_rst_o = sl_iport_i[0];
LUT6 #(
.INIT(64'hBAAAFFFFAAAAAAAA))
\reg_do[0]_i_1
(.I0(\reg_do[5]_i_2_n_0 ),
.I1(sl_iport_i[4]),
.I2(reg_test[0]),
.I3(sl_iport_i[6]),
.I4(sl_iport_i[5]),
.I5(sl_iport_i[8]),
.O(reg_do[0]));
LUT3 #(
.INIT(8'h40))
\reg_do[10]_i_1
(.I0(sl_iport_i[5]),
.I1(\reg_do[8]_i_2_n_0 ),
.I2(sl_iport_i[4]),
.O(\reg_do[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h0800))
\reg_do[10]_i_2
(.I0(\reg_do[8]_i_2_n_0 ),
.I1(sl_iport_i[5]),
.I2(sl_iport_i[4]),
.I3(reg_test[10]),
.O(\reg_do[10]_i_2_n_0 ));
LUT3 #(
.INIT(8'hF7))
\reg_do[15]_i_1
(.I0(\reg_do[8]_i_2_n_0 ),
.I1(sl_iport_i[5]),
.I2(sl_iport_i[4]),
.O(\reg_do[15]_i_1_n_0 ));
LUT5 #(
.INIT(32'h20220000))
\reg_do[1]_i_1
(.I0(sl_iport_i[5]),
.I1(sl_iport_i[4]),
.I2(reg_test[1]),
.I3(sl_iport_i[6]),
.I4(\reg_do[1]_i_2_n_0 ),
.O(reg_do[1]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h00800000))
\reg_do[1]_i_2
(.I0(sl_iport_i[8]),
.I1(sl_iport_i[10]),
.I2(sl_iport_i[11]),
.I3(sl_iport_i[7]),
.I4(sl_iport_i[9]),
.O(\reg_do[1]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h0800))
\reg_do[2]_i_1
(.I0(\reg_do[8]_i_2_n_0 ),
.I1(sl_iport_i[5]),
.I2(sl_iport_i[4]),
.I3(reg_test[2]),
.O(\reg_do[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h0800))
\reg_do[3]_i_1
(.I0(\reg_do[8]_i_2_n_0 ),
.I1(sl_iport_i[5]),
.I2(sl_iport_i[4]),
.I3(reg_test[3]),
.O(\reg_do[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h0800))
\reg_do[4]_i_1
(.I0(\reg_do[8]_i_2_n_0 ),
.I1(sl_iport_i[5]),
.I2(sl_iport_i[4]),
.I3(reg_test[4]),
.O(\reg_do[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF00800044))
\reg_do[5]_i_1
(.I0(sl_iport_i[6]),
.I1(sl_iport_i[8]),
.I2(reg_test[5]),
.I3(sl_iport_i[4]),
.I4(sl_iport_i[5]),
.I5(\reg_do[5]_i_2_n_0 ),
.O(reg_do[5]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hBFFFFFFC))
\reg_do[5]_i_2
(.I0(sl_iport_i[7]),
.I1(sl_iport_i[8]),
.I2(sl_iport_i[11]),
.I3(sl_iport_i[10]),
.I4(sl_iport_i[9]),
.O(\reg_do[5]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h0800))
\reg_do[6]_i_1
(.I0(\reg_do[8]_i_2_n_0 ),
.I1(sl_iport_i[5]),
.I2(sl_iport_i[4]),
.I3(reg_test[6]),
.O(\reg_do[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h0800))
\reg_do[7]_i_1
(.I0(\reg_do[8]_i_2_n_0 ),
.I1(sl_iport_i[5]),
.I2(sl_iport_i[4]),
.I3(reg_test[7]),
.O(\reg_do[7]_i_1_n_0 ));
LUT4 #(
.INIT(16'h2F00))
\reg_do[8]_i_1
(.I0(reg_test[8]),
.I1(sl_iport_i[4]),
.I2(sl_iport_i[5]),
.I3(\reg_do[8]_i_2_n_0 ),
.O(reg_do[8]));
LUT6 #(
.INIT(64'h2000000000000000))
\reg_do[8]_i_2
(.I0(sl_iport_i[9]),
.I1(sl_iport_i[7]),
.I2(sl_iport_i[11]),
.I3(sl_iport_i[10]),
.I4(sl_iport_i[8]),
.I5(sl_iport_i[6]),
.O(\reg_do[8]_i_2_n_0 ));
LUT5 #(
.INIT(32'h0C008000))
\reg_do[9]_i_1
(.I0(reg_test[9]),
.I1(\reg_do[1]_i_2_n_0 ),
.I2(sl_iport_i[6]),
.I3(sl_iport_i[5]),
.I4(sl_iport_i[4]),
.O(\reg_do[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[0]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_do[0]),
.Q(\reg_do_reg_n_0_[0] ),
.R(1'b0));
FDSE #(
.INIT(1'b0))
\reg_do_reg[10]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(\reg_do[10]_i_2_n_0 ),
.Q(\reg_do_reg_n_0_[10] ),
.S(\reg_do[10]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[11]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_test[11]),
.Q(\reg_do_reg_n_0_[11] ),
.R(\reg_do[15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[12]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_test[12]),
.Q(\reg_do_reg_n_0_[12] ),
.R(\reg_do[15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[13]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_test[13]),
.Q(\reg_do_reg_n_0_[13] ),
.R(\reg_do[15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[14]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_test[14]),
.Q(\reg_do_reg_n_0_[14] ),
.R(\reg_do[15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[15]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_test[15]),
.Q(\reg_do_reg_n_0_[15] ),
.R(\reg_do[15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[1]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_do[1]),
.Q(\reg_do_reg_n_0_[1] ),
.R(1'b0));
FDSE #(
.INIT(1'b0))
\reg_do_reg[2]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(\reg_do[2]_i_1_n_0 ),
.Q(\reg_do_reg_n_0_[2] ),
.S(\reg_do[10]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\reg_do_reg[3]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(\reg_do[3]_i_1_n_0 ),
.Q(\reg_do_reg_n_0_[3] ),
.S(\reg_do[10]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\reg_do_reg[4]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(\reg_do[4]_i_1_n_0 ),
.Q(\reg_do_reg_n_0_[4] ),
.S(\reg_do[10]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[5]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_do[5]),
.Q(\reg_do_reg_n_0_[5] ),
.R(1'b0));
FDSE #(
.INIT(1'b0))
\reg_do_reg[6]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(\reg_do[6]_i_1_n_0 ),
.Q(\reg_do_reg_n_0_[6] ),
.S(\reg_do[10]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\reg_do_reg[7]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(\reg_do[7]_i_1_n_0 ),
.Q(\reg_do_reg_n_0_[7] ),
.S(\reg_do[10]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[8]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_do[8]),
.Q(\reg_do_reg_n_0_[8] ),
.R(1'b0));
FDSE #(
.INIT(1'b0))
\reg_do_reg[9]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(\reg_do[9]_i_1_n_0 ),
.Q(\reg_do_reg_n_0_[9] ),
.S(\reg_do[10]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000080000000))
reg_drdy_i_1
(.I0(sl_iport_i[2]),
.I1(s_den_o_INST_0_i_1_n_0),
.I2(sl_iport_i[12]),
.I3(sl_iport_i[13]),
.I4(sl_iport_i[14]),
.I5(sl_iport_i[0]),
.O(reg_drdy_i_1_n_0));
FDRE #(
.INIT(1'b0))
reg_drdy_reg
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_drdy_i_1_n_0),
.Q(reg_drdy),
.R(1'b0));
LUT6 #(
.INIT(64'h8000000000000000))
\reg_test[15]_i_1
(.I0(sl_iport_i[3]),
.I1(sl_iport_i[2]),
.I2(sl_iport_i[14]),
.I3(sl_iport_i[13]),
.I4(sl_iport_i[12]),
.I5(s_den_o_INST_0_i_1_n_0),
.O(reg_test0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[0]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[21]),
.Q(reg_test[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[10]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[31]),
.Q(reg_test[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[11]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[32]),
.Q(reg_test[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[12]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[33]),
.Q(reg_test[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[13]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[34]),
.Q(reg_test[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[14]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[35]),
.Q(reg_test[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[15]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[36]),
.Q(reg_test[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[1]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[22]),
.Q(reg_test[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[2]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[23]),
.Q(reg_test[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[3]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[24]),
.Q(reg_test[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[4]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[25]),
.Q(reg_test[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[5]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[26]),
.Q(reg_test[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[6]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[27]),
.Q(reg_test[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[7]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[28]),
.Q(reg_test[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[8]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[29]),
.Q(reg_test[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[9]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[30]),
.Q(reg_test[9]),
.R(1'b0));
LUT5 #(
.INIT(32'h2AAAAAAA))
s_den_o_INST_0
(.I0(sl_iport_i[2]),
.I1(sl_iport_i[14]),
.I2(sl_iport_i[13]),
.I3(sl_iport_i[12]),
.I4(s_den_o_INST_0_i_1_n_0),
.O(s_den_o));
LUT6 #(
.INIT(64'h8000000000000000))
s_den_o_INST_0_i_1
(.I0(sl_iport_i[15]),
.I1(sl_iport_i[16]),
.I2(sl_iport_i[17]),
.I3(sl_iport_i[18]),
.I4(sl_iport_i[20]),
.I5(sl_iport_i[19]),
.O(s_den_o_INST_0_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'hE))
\sl_oport_o[0]_INST_0
(.I0(s_drdy_i),
.I1(reg_drdy),
.O(sl_oport_o[0]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[10]_INST_0
(.I0(\reg_do_reg_n_0_[9] ),
.I1(s_do_i[9]),
.I2(reg_drdy),
.O(sl_oport_o[10]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[11]_INST_0
(.I0(\reg_do_reg_n_0_[10] ),
.I1(s_do_i[10]),
.I2(reg_drdy),
.O(sl_oport_o[11]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[12]_INST_0
(.I0(\reg_do_reg_n_0_[11] ),
.I1(s_do_i[11]),
.I2(reg_drdy),
.O(sl_oport_o[12]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[13]_INST_0
(.I0(\reg_do_reg_n_0_[12] ),
.I1(s_do_i[12]),
.I2(reg_drdy),
.O(sl_oport_o[13]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[14]_INST_0
(.I0(\reg_do_reg_n_0_[13] ),
.I1(s_do_i[13]),
.I2(reg_drdy),
.O(sl_oport_o[14]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[15]_INST_0
(.I0(\reg_do_reg_n_0_[14] ),
.I1(s_do_i[14]),
.I2(reg_drdy),
.O(sl_oport_o[15]));
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[16]_INST_0
(.I0(\reg_do_reg_n_0_[15] ),
.I1(s_do_i[15]),
.I2(reg_drdy),
.O(sl_oport_o[16]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[1]_INST_0
(.I0(\reg_do_reg_n_0_[0] ),
.I1(s_do_i[0]),
.I2(reg_drdy),
.O(sl_oport_o[1]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[2]_INST_0
(.I0(\reg_do_reg_n_0_[1] ),
.I1(s_do_i[1]),
.I2(reg_drdy),
.O(sl_oport_o[2]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[3]_INST_0
(.I0(\reg_do_reg_n_0_[2] ),
.I1(s_do_i[2]),
.I2(reg_drdy),
.O(sl_oport_o[3]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[4]_INST_0
(.I0(\reg_do_reg_n_0_[3] ),
.I1(s_do_i[3]),
.I2(reg_drdy),
.O(sl_oport_o[4]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[5]_INST_0
(.I0(\reg_do_reg_n_0_[4] ),
.I1(s_do_i[4]),
.I2(reg_drdy),
.O(sl_oport_o[5]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[6]_INST_0
(.I0(\reg_do_reg_n_0_[5] ),
.I1(s_do_i[5]),
.I2(reg_drdy),
.O(sl_oport_o[6]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[7]_INST_0
(.I0(\reg_do_reg_n_0_[6] ),
.I1(s_do_i[6]),
.I2(reg_drdy),
.O(sl_oport_o[7]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[8]_INST_0
(.I0(\reg_do_reg_n_0_[7] ),
.I1(s_do_i[7]),
.I2(reg_drdy),
.O(sl_oport_o[8]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[9]_INST_0
(.I0(\reg_do_reg_n_0_[8] ),
.I1(s_do_i[8]),
.I2(reg_drdy),
.O(sl_oport_o[9]));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__ISOBUFSRC_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__ISOBUFSRC_FUNCTIONAL_V
/**
* isobufsrc: Input isolation, noninverted sleep.
*
* X = (!A | SLEEP)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__isobufsrc (
X ,
SLEEP,
A
);
// Module ports
output X ;
input SLEEP;
input A ;
// Local signals
wire not0_out ;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out , SLEEP );
and and0 (and0_out_X, not0_out, A );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__ISOBUFSRC_FUNCTIONAL_V |
`timescale 1ns/10ps
module vga_pll_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'outclk2'
output wire outclk_2,
// interface 'outclk3'
output wire outclk_3,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("normal"),
.number_of_clocks(4),
.output_clock_frequency0("25.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("40.000000 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("33.333333 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("100.000000 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_3, outclk_2, outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
`timescale 1 ns / 1 ps
//////////////////////////////////////////////////////////////////////////////////
// Company: TAMUQ University
// Engineers: Ali Aljaani
// part of this work was contributed by Ryan Kim,and Josh Sackos as a demo for the PmodOLED/Nexys3 board By Digilent Inc.
//
//
// Create Date: 06:13:25 08/18/2014
// Module Name: ZedboardOLED_v1_0_S00_AXI
// Project Name: ZedboardOLED
// Target Devices: Zynq
// Tool versions: Vivado 14.2 (64-bits)
// Description: The core is a slave AXI peripheral with 17 software-accessed registers.
// registers 0-16 are used for data, register 17 is the control register
//
// Revision: 1.0 - ZedboardOLED_v1_0_S00_AXI completed
// Revision 0.01 - File Created
//
//////////////////////////////////////////////////////////////////////////////////
module ZedboardOLED_v1_0_S00_AXI #
(
// Width of S_AXI data bus
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of S_AXI address bus
parameter integer C_S_AXI_ADDR_WIDTH = 7
)
(
// Interface with the SSD1306 starts here
//SPI Data In (MOSI)
output SDIN,
//SPI Clock
output SCLK,
//Data_Command Control
output DC,
//Power Reset
output RES,
//Battery Voltage Control - connected to field-effect transistors-active low
output VBAT,
// Logic Voltage Control - connected to field-effect transistors-active low
output VDD,
// Interface with the SSD1306 ends here
// Global Clock Signal
input wire S_AXI_ACLK,
// Global Reset Signal. This Signal is Active LOW
input wire S_AXI_ARESETN,
// Write address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
// Write channel Protection type. This signal indicates the
// privilege and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_AWPROT,
// Write address valid. This signal indicates that the master signaling
// valid write address and control information.
input wire S_AXI_AWVALID,
// Write address ready. This signal indicates that the slave is ready
// to accept an address and associated control signals.
output wire S_AXI_AWREADY,
// Write data (issued by master, acceped by Slave)
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
// Write strobes. This signal indicates which byte lanes hold
// valid data. There is one write strobe bit for each eight
// bits of the write data bus.
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
// Write valid. This signal indicates that valid write
// data and strobes are available.
input wire S_AXI_WVALID,
// Write ready. This signal indicates that the slave
// can accept the write data.
output wire S_AXI_WREADY,
// Write response. This signal indicates the status
// of the write transaction.
output wire [1 : 0] S_AXI_BRESP,
// Write response valid. This signal indicates that the channel
// is signaling a valid write response.
output wire S_AXI_BVALID,
// Response ready. This signal indicates that the master
// can accept a write response.
input wire S_AXI_BREADY,
// Read address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether the
// transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_ARPROT,
// Read address valid. This signal indicates that the channel
// is signaling valid read address and control information.
input wire S_AXI_ARVALID,
// Read address ready. This signal indicates that the slave is
// ready to accept an address and associated control signals.
output wire S_AXI_ARREADY,
// Read data (issued by slave)
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
// Read response. This signal indicates the status of the
// read transfer.
output wire [1 : 0] S_AXI_RRESP,
// Read valid. This signal indicates that the channel is
// signaling the required read data.
output wire S_AXI_RVALID,
// Read ready. This signal indicates that the master can
// accept the read data and response information.
input wire S_AXI_RREADY
);
// AXI4LITE signals
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [1 : 0] axi_bresp;
reg axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
reg axi_arready;
reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
reg [1 : 0] axi_rresp;
reg axi_rvalid;
// Example-specific design signals
// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
// ADDR_LSB is used for addressing 32/64 bit registers/memories
// ADDR_LSB = 2 for 32 bits (n downto 2)
// ADDR_LSB = 3 for 64 bits (n downto 3)
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
localparam integer OPT_MEM_ADDR_BITS = 4;
//----------------------------------------------
//-- Signals for user logic register space example
//------------------------------------------------
//-- Number of Slave Registers 17
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg4;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg5;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg6;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg7;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg8;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg9;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg10;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg11;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg12;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg13;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg14;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg15;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg16;
wire slv_reg_rden;
wire slv_reg_wren;
reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
integer byte_index;
// I/O Connections assignments
assign S_AXI_AWREADY = axi_awready;
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BRESP = axi_bresp;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_ARREADY = axi_arready;
assign S_AXI_RDATA = axi_rdata;
assign S_AXI_RRESP = axi_rresp;
assign S_AXI_RVALID = axi_rvalid;
// Implement axi_awready generation
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
// de-asserted when reset is low.
// ===========================================================================
// Parameters, Regsiters, and Wires
// ===========================================================================
//Current overall state of the state machine
reg [143:0] current_state;
//State to go to after the SPI transmission is finished
reg [111:0] after_state;
//State to go to after the set page sequence
reg [142:0] after_page_state;
//State to go to after sending the character sequence
reg [95:0] after_char_state;
//State to go to after the UpdateScreen is finished
reg [39:0] after_update_state;
//Variable that contains what the screen will be after the next UpdateScreen state
reg [7:0] current_screen[0:3][0:15];
//Variable assigned to the SSD1306 interface
reg temp_dc = 1'b0;
reg temp_res = 1'b1;
reg temp_vbat = 1'b1;
reg temp_vdd = 1'b1;
assign DC = temp_dc;
assign RES = temp_res;
assign VBAT = temp_vbat;
assign VDD = temp_vdd;
//-------------- Variables used in the Delay Controller Block --------------
wire [11:0] temp_delay_ms; //amount of ms to delay
reg temp_delay_en = 1'b0; //Enable signal for the delay block
wire temp_delay_fin; //Finish signal for the delay block
assign temp_delay_ms = (after_state == "DispContrast1") ? 12'h074 : 12'h014;
//-------------- Variables used in the SPI controller block ----------------
reg temp_spi_en = 1'b0; //Enable signal for the SPI block
reg [7:0] temp_spi_data = 8'h00; //Data to be sent out on SPI
wire temp_spi_fin; //Finish signal for the SPI block
//-------------- Variables used in the characters libtray ----------------
reg [7:0] temp_char; //Contains ASCII value for character
reg [10:0] temp_addr; //Contains address to BYTE needed in memory
wire [7:0] temp_dout; //Contains byte outputted from memory
reg [1:0] temp_page; //Current page
reg [3:0] temp_index; //Current character on page
//-------------- Variables used in the reset and synchronization circuitry ----------------
reg init_first_r = 1'b1; // Initilaize only one time
reg clear_screen_i = 1'b1; // Clear the screen on start up
reg ready = 1'b0; // Ready flag
reg RST_internal =1'b1;
reg[11:0] count =12'h000;
wire RST_IN;
wire RST=1'b0; // dummy wire - can be connected as a port to provide external reset to the circuit
integer i = 0;
integer j = 0;
assign RST_IN = (RST || RST_internal);
//-------------- Core commands assignments start ----------------
wire Display_c;
wire Clear_c;
assign Display_c = slv_reg16[0];
assign Clear_c =slv_reg16[1];
//-------------- Core commands assignments end ----------------
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awready <= 1'b0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
begin
// slave is ready to accept write address when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_awready <= 1'b1;
end
else
begin
axi_awready <= 1'b0;
end
end
end
// Implement axi_awaddr latching
// This process is used to latch the address when both
// S_AXI_AWVALID and S_AXI_WVALID are valid.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awaddr <= 0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
begin
// Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end
end
end
// Implement axi_wready generation
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_wready <= 1'b0;
end
else
begin
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID)
begin
// slave is ready to accept write data when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_wready <= 1'b1;
end
else
begin
axi_wready <= 1'b0;
end
end
end
// Implement memory mapped register select and write logic generation
// The write data is accepted and written to memory mapped registers when
// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
// select byte enables of slave registers while writing.
// These registers are cleared when reset (active low) is applied.
// Slave register write enable is asserted when valid address and data are available
// and the slave is ready to accept the write address and write data.
assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
slv_reg0 <= 0;
slv_reg1 <= 0;
slv_reg2 <= 0;
slv_reg3 <= 0;
slv_reg4 <= 0;
slv_reg5 <= 0;
slv_reg6 <= 0;
slv_reg7 <= 0;
slv_reg8 <= 0;
slv_reg9 <= 0;
slv_reg10 <= 0;
slv_reg11 <= 0;
slv_reg12 <= 0;
slv_reg13 <= 0;
slv_reg14 <= 0;
slv_reg15 <= 0;
slv_reg16 <= 0;
end
else begin
if (slv_reg_wren)
begin
case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
5'h00:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 0
slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h01:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 1
slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h02:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 2
slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h03:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 3
slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h04:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 4
slv_reg4[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h05:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 5
slv_reg5[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h06:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 6
slv_reg6[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h07:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 7
slv_reg7[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h08:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 8
slv_reg8[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h09:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 9
slv_reg9[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h0A:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 10
slv_reg10[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h0B:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 11
slv_reg11[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h0C:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 12
slv_reg12[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h0D:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 13
slv_reg13[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h0E:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 14
slv_reg14[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h0F:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 15
slv_reg15[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h10:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 16
slv_reg16[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
default : begin
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
slv_reg8 <= slv_reg8;
slv_reg9 <= slv_reg9;
slv_reg10 <= slv_reg10;
slv_reg11 <= slv_reg11;
slv_reg12 <= slv_reg12;
slv_reg13 <= slv_reg13;
slv_reg14 <= slv_reg14;
slv_reg15 <= slv_reg15;
slv_reg16 <= slv_reg16;
end
endcase
end
end
end
// Implement write response logic generation
// The write response and response valid signals are asserted by the slave
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
// This marks the acceptance of address and indicates the status of
// write transaction.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
end
else
begin
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
begin
// indicates a valid write response is available
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0; // 'OKAY' response
end // work error responses in future
else
begin
if (S_AXI_BREADY && axi_bvalid)
//check if bready is asserted while bvalid is high)
//(there is a possibility that bready is always asserted high)
begin
axi_bvalid <= 1'b0;
end
end
end
end
// Implement axi_arready generation
// axi_arready is asserted for one S_AXI_ACLK clock cycle when
// S_AXI_ARVALID is asserted. axi_awready is
// de-asserted when reset (active low) is asserted.
// The read address is also latched when S_AXI_ARVALID is
// asserted. axi_araddr is reset to zero on reset assertion.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_arready <= 1'b0;
axi_araddr <= 32'b0;
end
else
begin
if (~axi_arready && S_AXI_ARVALID)
begin
// indicates that the slave has acceped the valid read address
axi_arready <= 1'b1;
// Read address latching
axi_araddr <= S_AXI_ARADDR;
end
else
begin
axi_arready <= 1'b0;
end
end
end
// Implement axi_arvalid generation
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
// data are available on the axi_rdata bus at this instance. The
// assertion of axi_rvalid marks the validity of read data on the
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
// is deasserted on reset (active low). axi_rresp and axi_rdata are
// cleared to zero on reset (active low).
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rvalid <= 0;
axi_rresp <= 0;
end
else
begin
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
begin
// Valid read data is available at the read data bus
axi_rvalid <= 1'b1;
axi_rresp <= 2'b0; // 'OKAY' response
end
else if (axi_rvalid && S_AXI_RREADY)
begin
// Read data is accepted by the master
axi_rvalid <= 1'b0;
end
end
end
// Implement memory mapped register select and read logic generation
// Slave register read enable is asserted when valid address is available
// and the slave is ready to accept the read address.
assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
always @(*)
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
reg_data_out <= 0;
end
else
begin
// Address decoding for reading registers
case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
5'h00 : reg_data_out <= slv_reg0;
5'h01 : reg_data_out <= slv_reg1;
5'h02 : reg_data_out <= slv_reg2;
5'h03 : reg_data_out <= slv_reg3;
5'h04 : reg_data_out <= slv_reg4;
5'h05 : reg_data_out <= slv_reg5;
5'h06 : reg_data_out <= slv_reg6;
5'h07 : reg_data_out <= slv_reg7;
5'h08 : reg_data_out <= slv_reg8;
5'h09 : reg_data_out <= slv_reg9;
5'h0A : reg_data_out <= slv_reg10;
5'h0B : reg_data_out <= slv_reg11;
5'h0C : reg_data_out <= slv_reg12;
5'h0D : reg_data_out <= slv_reg13;
5'h0E : reg_data_out <= slv_reg14;
5'h0F : reg_data_out <= slv_reg15;
5'h10 : reg_data_out <= slv_reg16;
default : reg_data_out <= 0;
endcase
end
end
// Output register or memory read data
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rdata <= 0;
end
else
begin
// When there is a valid read address (S_AXI_ARVALID) with
// acceptance of read address by the slave (axi_arready),
// output the read dada
if (slv_reg_rden)
begin
axi_rdata <= reg_data_out; // register read data
end
end
end
// ===========================================================================
// Implementation
// ===========================================================================
SpiCtrl SPI_COMP(
.CLK(S_AXI_ACLK),
.RST(RST_IN),
.SPI_EN(temp_spi_en),
.SPI_DATA(temp_spi_data),
.SDO(SDIN),
.SCLK(SCLK),
.SPI_FIN(temp_spi_fin)
);
Delay DELAY_COMP(
.CLK(S_AXI_ACLK),
.RST(RST_IN),
.DELAY_MS(temp_delay_ms),
.DELAY_EN(temp_delay_en),
.DELAY_FIN(temp_delay_fin)
);
charLib CHAR_LIB_COMP(
.clka(S_AXI_ACLK),
.addra(temp_addr),
.douta(temp_dout)
);
// State Machine
always @(posedge S_AXI_ACLK) begin
if(RST_IN == 1'b1) begin
current_state <= "Idle";
temp_res <= 1'b0;
end
else begin
temp_res <= 1'b1;
case(current_state)
// Idle State
"Idle" : begin
if(init_first_r == 1'b1) begin
temp_dc <= 1'b0; // DC= 0 "Commands" , DC=1 "Data"
current_state <= "VddOn";
init_first_r <= 1'b0; // Don't go over the initialization more than once
end
else begin
current_state <="WaitRequest";
end
end
// Initialization Sequence
// This should be done only one time when Zedboard starts
"VddOn" : begin // turn the power on the logic of the display
temp_vdd <= 1'b0; // remember the power FET transistor for VDD is active low
current_state <= "Wait1";
end
// 3
"Wait1" : begin
after_state <= "DispOff";
current_state <= "Transition3";
end
// 4
"DispOff" : begin
temp_spi_data <= 8'hAE; // 0xAE= Set Display OFF
after_state <= "SetClockDiv1";
current_state <= "Transition1";
end
// 5
"SetClockDiv1" : begin
temp_spi_data <= 8'hD5; //0xD5
after_state <= "SetClockDiv2";
current_state <= "Transition1";
end
// 6
"SetClockDiv2" : begin
temp_spi_data <= 8'h80; // 0x80
after_state <= "MultiPlex1";
current_state <= "Transition1";
end
// 7
"MultiPlex1" : begin
temp_spi_data <= 8'hA8; //0xA8
after_state <= "MultiPlex2";
current_state <= "Transition1";
end
// 8
"MultiPlex2" : begin
temp_spi_data <= 8'h1F; // 0x1F
after_state <= "ChargePump1";
current_state <= "Transition1";
end
// 9
"ChargePump1" : begin // Access Charge Pump Setting
temp_spi_data <= 8'h8D; //0x8D
after_state <= "ChargePump2";
current_state <= "Transition1";
end
// 10
"ChargePump2" : begin // Enable Charge Pump
temp_spi_data <= 8'h14; // 0x14
after_state <= "PreCharge1";
current_state <= "Transition1";
end
// 11
"PreCharge1" : begin // Access Pre-charge Period Setting
temp_spi_data <= 8'hD9; // 0xD9
after_state <= "PreCharge2";
current_state <= "Transition1";
end
// 12
"PreCharge2" : begin //Set the Pre-charge Period
temp_spi_data <= 8'hFF; // 0xF1
after_state <= "VCOMH1";
current_state <= "Transition1";
end
// 13
"VCOMH1" : begin //Set the Pre-charge Period
temp_spi_data <= 8'hDB; // 0xF1
after_state <= "VCOMH2";
current_state <= "Transition1";
end
// 14
"VCOMH2" : begin //Set the Pre-charge Period
temp_spi_data <= 8'h40; // 0xF1
after_state <= "DispContrast1";
current_state <= "Transition1";
end
// 15
"DispContrast1" : begin //Set Contrast Control for BANK0
temp_spi_data <= 8'h81; // 0x81
after_state <= "DispContrast2";
current_state <= "Transition1";
end
// 16
"DispContrast2" : begin
temp_spi_data <= 8'hF1; // 0x0F
after_state <= "InvertDisp1";
current_state <= "Transition1";
end
// 17
"InvertDisp1" : begin
temp_spi_data <= 8'hA0; // 0xA1
after_state <= "InvertDisp2";
current_state <= "Transition1";
end
// 18
"InvertDisp2" : begin
temp_spi_data <= 8'hC0; // 0xC0
after_state <= "ComConfig1";
current_state <= "Transition1";
end
// 19
"ComConfig1" : begin
temp_spi_data <= 8'hDA; // 0xDA
after_state <= "ComConfig2";
current_state <= "Transition1";
end
// 20
"ComConfig2" : begin
temp_spi_data <= 8'h02; // 0x02
after_state <= "VbatOn";
current_state <= "Transition1";
end
// 21
"VbatOn" : begin
temp_vbat <= 1'b0;
current_state <= "Wait3";
end
// 22
"Wait3" : begin
after_state <= "ResetOn";
current_state <= "Transition3";
end
// 23
"ResetOn" : begin
temp_res <= 1'b0;
current_state <= "Wait2";
end
// 24
"Wait2" : begin
after_state <= "ResetOff";
current_state <= "Transition3";
end
// 25
"ResetOff" : begin
temp_res <= 1'b1;
current_state <= "WaitRequest";
end
// ************ END Initialization sequence but without turnning the dispay on ************
// Main state
"WaitRequest" : begin
if(Display_c == 1'b1) begin
current_state <= "ClearDC";
after_page_state <= "ReadRegisters";
temp_page <= 2'b00;
end
else if ((Clear_c==1'b1) || (clear_screen_i == 1'b1)) begin
current_state <= "ClearDC";
after_page_state <= "ClearScreen";
temp_page <= 2'b00;
end
else begin
current_state<="WaitRequest"; // keep looping in the WaitRequest state untill you receive a command
if ((clear_screen_i == 1'b0) && (ready ==1'b0)) begin // this part is only executed once, on start-up
temp_spi_data <= 8'hAF; // 0xAF // Dispaly ON
after_state <= "WaitRequest";
current_state <= "Transition1";
temp_dc<=1'b0;
ready <= 1'b1;
end
end
end
//Update Page states
//1. Sets DC to command mode
//2. Sends the SetPage Command
//3. Sends the Page to be set to
//4. Sets the start pixel to the left column
//5. Sets DC to data mode
"ClearDC" : begin
temp_dc <= 1'b0;
current_state <= "SetPage";
end
"SetPage" : begin
temp_spi_data <= 8'b00100010;
after_state <= "PageNum";
current_state <= "Transition1";
end
"PageNum" : begin
temp_spi_data <= {6'b000000,temp_page};
after_state <= "LeftColumn1";
current_state <= "Transition1";
end
"LeftColumn1" : begin
temp_spi_data <= 8'b00000000;
after_state <= "LeftColumn2";
current_state <= "Transition1";
end
"LeftColumn2" : begin
temp_spi_data <= 8'b00010000;
after_state <= "SetDC";
current_state <= "Transition1";
end
"SetDC" : begin
temp_dc <= 1'b1;
current_state <= after_page_state;
end
"ClearScreen" : begin
for(i = 0; i <= 3 ; i=i+1) begin
for(j = 0; j <= 15 ; j=j+1) begin
current_screen[i][j] <= 8'h20;
end
end
after_update_state <= "WaitRequest";
current_state <= "UpdateScreen";
end
"ReadRegisters" : begin
// Page0
current_screen[0][0]<=slv_reg0[7:0];
current_screen[0][1]<=slv_reg0[15:8];
current_screen[0][2]<=slv_reg0[23:16];
current_screen[0][3]<=slv_reg0[31:24];
current_screen[0][4]<=slv_reg1[7:0];
current_screen[0][5]<=slv_reg1[15:8];
current_screen[0][6]<=slv_reg1[23:16];
current_screen[0][7]<=slv_reg1[31:24];
current_screen[0][8]<=slv_reg2[7:0];
current_screen[0][9]<=slv_reg2[15:8];
current_screen[0][10]<=slv_reg2[23:16];
current_screen[0][11]<=slv_reg2[31:24];
current_screen[0][12]<=slv_reg3[7:0];
current_screen[0][13]<=slv_reg3[15:8];
current_screen[0][14]<=slv_reg3[23:16];
current_screen[0][15]<=slv_reg3[31:24];
//Page1
current_screen[1][0]<=slv_reg4[7:0];
current_screen[1][1]<=slv_reg4[15:8];
current_screen[1][2]<=slv_reg4[23:16];
current_screen[1][3]<=slv_reg4[31:24];
current_screen[1][4]<=slv_reg5[7:0];
current_screen[1][5]<=slv_reg5[15:8];
current_screen[1][6]<=slv_reg5[23:16];
current_screen[1][7]<=slv_reg5[31:24];
current_screen[1][8]<=slv_reg6[7:0];
current_screen[1][9]<=slv_reg6[15:8];
current_screen[1][10]<=slv_reg6[23:16];
current_screen[1][11]<=slv_reg6[31:24];
current_screen[1][12]<=slv_reg7[7:0];
current_screen[1][13]<=slv_reg7[15:8];
current_screen[1][14]<=slv_reg7[23:16];
current_screen[1][15]<=slv_reg7[31:24];
//Page2
current_screen[2][0]<=slv_reg8[7:0];
current_screen[2][1]<=slv_reg8[15:8];
current_screen[2][2]<=slv_reg8[23:16];
current_screen[2][3]<=slv_reg8[31:24];
current_screen[2][4]<=slv_reg9[7:0];
current_screen[2][5]<=slv_reg9[15:8];
current_screen[2][6]<=slv_reg9[23:16];
current_screen[2][7]<=slv_reg9[31:24];
current_screen[2][8]<=slv_reg10[7:0];
current_screen[2][9]<=slv_reg10[15:8];
current_screen[2][10]<=slv_reg10[23:16];
current_screen[2][11]<=slv_reg10[31:24];
current_screen[2][12]<=slv_reg11[7:0];
current_screen[2][13]<=slv_reg11[15:8];
current_screen[2][14]<=slv_reg11[23:16];
current_screen[2][15]<=slv_reg11[31:24];
//Page3
current_screen[3][0]<=slv_reg12[7:0];
current_screen[3][1]<=slv_reg12[15:8];
current_screen[3][2]<=slv_reg12[23:16];
current_screen[3][3]<=slv_reg12[31:24];
current_screen[3][4]<=slv_reg13[7:0];
current_screen[3][5]<=slv_reg13[15:8];
current_screen[3][6]<=slv_reg13[23:16];
current_screen[3][7]<=slv_reg13[31:24];
current_screen[3][8]<=slv_reg14[7:0];
current_screen[3][9]<=slv_reg14[15:8];
current_screen[3][10]<=slv_reg14[23:16];
current_screen[3][11]<=slv_reg14[31:24];
current_screen[3][12]<=slv_reg15[7:0];
current_screen[3][13]<=slv_reg15[15:8];
current_screen[3][14]<=slv_reg15[23:16];
current_screen[3][15]<=slv_reg15[31:24];
after_update_state <= "WaitRequest";
current_state <= "UpdateScreen";
end
//UpdateScreen State
//1. Gets ASCII value from current_screen at the current page and the current spot of the page
//2. If on the last character of the page transition update the page number, if on the last page(3)
// then the updateScreen go to "after_update_state" after
"UpdateScreen" : begin
temp_char <= current_screen[temp_page][temp_index];
if(temp_index == 'd15) begin
temp_index <= 'd0;
temp_page <= temp_page + 1'b1;
after_char_state <= "ClearDC";
if(temp_page == 2'b11) begin
after_page_state <= after_update_state;
clear_screen_i<=1'b0;
end
else begin
after_page_state <= "UpdateScreen";
end
end
else begin
temp_index <= temp_index + 1'b1;
after_char_state <= "UpdateScreen";
end
current_state <= "SendChar1";
end
//Send Character States
//1. Sets the Address to ASCII value of char with the counter appended to the end
//2. Waits a clock for the data to get ready by going to ReadMem and ReadMem2 states
//3. Send the byte of data given by the block Ram
//4. Repeat 7 more times for the rest of the character bytes
"SendChar1" : begin
temp_addr <= {temp_char, 3'b000};
after_state <= "SendChar2";
current_state <= "ReadMem";
end
"SendChar2" : begin
temp_addr <= {temp_char, 3'b001};
after_state <= "SendChar3";
current_state <= "ReadMem";
end
"SendChar3" : begin
temp_addr <= {temp_char, 3'b010};
after_state <= "SendChar4";
current_state <= "ReadMem";
end
"SendChar4" : begin
temp_addr <= {temp_char, 3'b011};
after_state <= "SendChar5";
current_state <= "ReadMem";
end
"SendChar5" : begin
temp_addr <= {temp_char, 3'b100};
after_state <= "SendChar6";
current_state <= "ReadMem";
end
"SendChar6" : begin
temp_addr <= {temp_char, 3'b101};
after_state <= "SendChar7";
current_state <= "ReadMem";
end
"SendChar7" : begin
temp_addr <= {temp_char, 3'b110};
after_state <= "SendChar8";
current_state <= "ReadMem";
end
"SendChar8" : begin
temp_addr <= {temp_char, 3'b111};
after_state <= after_char_state;
current_state <= "ReadMem";
end
"ReadMem" : begin
current_state <= "ReadMem2";
end
"ReadMem2" : begin
temp_spi_data <= temp_dout;
current_state <= "Transition1";
end
// SPI transitions
// 1. Set SPI_EN to 1
// 2. Waits for SpiCtrl to finish
// 3. Goes to clear state (Transition5)
"Transition1" : begin
temp_spi_en <= 1'b1;
current_state <= "Transition2";
end
"Transition2" : begin
if(temp_spi_fin == 1'b1) begin
current_state <= "Transition5";
end
end
// Delay Transitions
// 1. Set DELAY_EN to 1
// 2. Waits for Delay to finish
// 3. Goes to Clear state (Transition5)
"Transition3" : begin
temp_delay_en <= 1'b1;
current_state <= "Transition4";
end
"Transition4" : begin
if(temp_delay_fin == 1'b1) begin
current_state <= "Transition5";
end
end
// Clear transition
// 1. Sets both DELAY_EN and SPI_EN to 0
// 2. Go to after state
"Transition5" : begin
temp_spi_en <= 1'b0;
temp_delay_en <= 1'b0;
current_state <= after_state;
end
default : current_state <= "Idle";
endcase
end
end
// Internal reset generator
always @(posedge S_AXI_ACLK) begin
if (RST_IN == 1'b1)
count<=count+1'b1;
if (count == 12'hFFF) begin
RST_internal <=1'b0;
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:52:13 02/22/2015
// Design Name:
// Module Name: Pack_z
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Pack_z(
input idle_NormaliseProd,
input [32:0] zout_NormaliseProd,
input [49:0] productout_NormaliseProd,
input clock,
output reg [31:0] FinalProduct
);
parameter no_idle = 1'b0,
put_idle = 1'b1;
wire z_sign;
wire [7:0] z_exponent;
wire [26:0] z_mantissa;
assign z_sign = zout_NormaliseProd[32];
assign z_exponent = zout_NormaliseProd[31:24];
assign z_mantissa = {zout_NormaliseProd[23:0]};
always @ (posedge clock)
begin
if (idle_NormaliseProd == no_idle)
begin
FinalProduct[22 : 0] <= z_mantissa[22:0];
FinalProduct[30 : 23] <= z_exponent[7:0] + 127;
FinalProduct[31] <= z_sign;
if ($signed(z_exponent) == -126 && z_mantissa[23] == 0) begin
FinalProduct[30 : 23] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_exponent) > 127) begin
FinalProduct[22 : 0] <= 0;
FinalProduct[30 : 23] <= 255;
FinalProduct[31] <= z_sign;
end
end
else begin
FinalProduct <= zout_NormaliseProd[32:1];
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S25_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S25_FUNCTIONAL_PP_V
/**
* clkdlybuf4s25: Clock Delay Buffer 4-stage 0.25um length inner stage
* gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__clkdlybuf4s25 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S25_FUNCTIONAL_PP_V |
//
// atactrl.v -- parallel ATA controller
//
`define ADDR_ALTERNATE_STATUS 4'b0110
`define ADDR_DEVICE_CONTROL 4'b0110
`define ADDR_DEVICE_ADDRESS 4'b0111
`define ADDR_DATA 4'b1000
`define ADDR_ERROR 4'b1001
`define ADDR_FEATURES 4'b1001
`define ADDR_SECTOR_COUNT 4'b1010
`define ADDR_LBA0 4'b1011
`define ADDR_LBA1 4'b1100
`define ADDR_LBA2 4'b1101
`define ADDR_LBA3_DRV 4'b1110
`define ADDR_STATUS 4'b1111
`define ADDR_COMMAND 4'b1111
module ata_ctrl (
input clk, reset,
input bus_en, bus_wr,
input [19:2] bus_addr,
input [31:0] bus_din,
output [31:0] bus_dout,
output bus_wait,
output bus_irq,
inout [15:0] ata_d,
output [2:0] ata_a,
output ata_cs0_n, ata_cs1_n,
output ata_dior_n, ata_diow_n,
input ata_intrq,
input ata_dmarq,
output ata_dmack_n,
input ata_iordy
);
// --- ATA IRQ line debouncing
reg debounced_ata_intrq, prev_ata_intrq;
reg [3:0] ata_intrq_debounce_counter;
// --- disk buffer
// interface to the bus
wire buffer_bus_wait;
wire [31:0] buffer_bus_dout;
// interface to the state machine
wire buffer_ata_write;
wire [11:1] buffer_ata_addr;
wire [15:0] buffer_ata_din;
wire [15:0] buffer_ata_dout;
wire buffer_bus_addressed;
wire buffer_bus_write;
reg buffer_bus_second_cycle;
ata_buffer buffer1 (
.clk (clk),
.bus_write (buffer_bus_write),
.bus_addr (bus_addr [11:2]),
.bus_din (bus_din),
.bus_dout (buffer_bus_dout),
.ata_write (buffer_ata_write),
.ata_addr (buffer_ata_addr),
.ata_din (buffer_ata_din),
.ata_dout (buffer_ata_dout)
);
assign buffer_bus_addressed = bus_addr [19];
assign buffer_bus_wait = bus_en & !buffer_bus_second_cycle;
assign buffer_bus_write = bus_en & bus_wr &
buffer_bus_addressed & !buffer_bus_second_cycle;
// --- control registers
// interface to the bus
wire control_bus_wait;
wire [31:0] control_bus_dout;
// interface to the state machine
reg [31:0] capacity;
reg [27:0] requestedSectorAddress;
reg [3:0] requestedSectorCount;
wire commandUnlocked;
reg enableInterrupts, requestedWrite, errorOutput;
reg operationFinished, diskInitialized;
wire control_bus_addressed;
assign control_bus_addressed = !bus_addr[19];
assign control_bus_wait = 0;
assign control_bus_dout =
(bus_addr [3:2] == 2'b00) ? {ata_dmarq, 25'd0,
diskInitialized, operationFinished,
errorOutput, requestedWrite,
enableInterrupts, 1'b0} :
(bus_addr [3:2] == 2'b01) ? { 28'd0, requestedSectorCount } :
(bus_addr [3:2] == 2'b10) ? { 4'd0, requestedSectorAddress } :
capacity;
// --- ATA IO component
reg io_en, io_write;
wire io_wait;
reg [3:0] io_addr;
reg [15:0] io_data_out;
wire [15:0] io_data_in;
assign ata_dmack_n = 1'b1;
ata_io io (
.clk(clk),
.reset(reset),
.bus_en(io_en),
.bus_wr(io_write),
.bus_addr(io_addr),
.bus_din(io_data_out),
.bus_dout(io_data_in),
.bus_wait(io_wait),
.ata_d(ata_d),
.ata_a(ata_a),
.ata_cs0_n(ata_cs0_n),
.ata_cs1_n(ata_cs1_n),
.ata_dior_n(ata_dior_n),
.ata_diow_n(ata_diow_n),
.ata_iordy(ata_iordy)
);
// --- bus interface
assign bus_dout = bus_addr [19] ? buffer_bus_dout : control_bus_dout;
assign bus_wait = bus_addr [19] ? buffer_bus_wait : control_bus_wait;
assign bus_irq = enableInterrupts & operationFinished;
// --- state machine
reg [4:0] state;
reg [7:0] aux_counter;
reg [2:0] sector_counter;
/*
STARTUP DEBUG LOGGING
reg [15:0] debugTimer;
*/
wire startBit;
assign commandUnlocked = (state == 5'd8);
assign startBit = bus_en & bus_wr &
(!bus_addr [19]) & (bus_addr [3:2] == 2'b00) &
bus_din [0];
assign buffer_ata_write = (state == 5'd16) & (!io_wait);
assign buffer_ata_addr = {sector_counter, aux_counter [7:0]};
assign buffer_ata_din = io_data_in;
always @(posedge clk) begin
if (reset) begin
prev_ata_intrq <= 1'b0;
debounced_ata_intrq <= 1'b0;
ata_intrq_debounce_counter <= 4'b0;
buffer_bus_second_cycle <= 1'b0;
capacity <= 32'd0;
requestedSectorAddress <= 32'd0;
requestedSectorCount <= 4'b0000;
enableInterrupts <= 1'b0;
requestedWrite <= 1'b0;
errorOutput <= 1'b0;
operationFinished <= 1'b0;
diskInitialized <= 1'b0;
io_en <= 1'b0;
io_write <= 1'b0;
io_addr <= 32'd0;
io_data_out <= 16'd0;
state <= 5'd0;
aux_counter <= 8'd0;
sector_counter <= 3'd0;
/*
STARTUP DEBUG LOGGING
debugTimer <= 16'd0;
*/
end else begin
if (ata_intrq == prev_ata_intrq) begin
if (ata_intrq_debounce_counter == 4'd0) begin
debounced_ata_intrq <= ata_intrq;
end else begin
ata_intrq_debounce_counter <= ata_intrq_debounce_counter - 1;
end
end else begin
ata_intrq_debounce_counter <= 4'd10;
end
prev_ata_intrq <= ata_intrq;
/*
STARTUP DEBUG LOGGING
debugTimer <= debugTimer + 1;
*/
if (bus_en)
buffer_bus_second_cycle <= !buffer_bus_second_cycle;
else
buffer_bus_second_cycle <= 1'b0;
if (bus_en & bus_wr & control_bus_addressed) begin
if (bus_addr [3:2] == 2'b00) begin
operationFinished <= bus_din [4];
if (commandUnlocked)
requestedWrite <= bus_din [2];
enableInterrupts <= bus_din [1];
end
else if (bus_addr [3:2] == 2'b01 & commandUnlocked) begin
requestedSectorCount <= bus_din [3:0];
end
else if (bus_addr [3:2] == 2'b10 & commandUnlocked) begin
requestedSectorAddress <= bus_din [27:0];
end
end
if (!io_wait) begin
/*
STARTUP DEBUG LOGGING
buffer_ata_write <= 1;
if (buffer_ata_addr < 2000)
buffer_ata_addr <= buffer_ata_addr + 2;
buffer_ata_din <= io_data_in;
*/
case (state)
// startup sequence: ask for access to command regs
// and drive
5'd0: begin
io_en <= 1'b1;
io_write <= 1'b0;
io_addr <= `ADDR_ALTERNATE_STATUS;
state <= 5'd1;
end
// startup sequence: wait for command regs and
// drive, or select drive 0 if ready
5'd1: begin
if (io_data_in [7:6] == 2'b01) begin
// ready, so select drive 0
io_write <= 1'b1;
io_addr <= `ADDR_LBA3_DRV;
io_data_out <= 8'b11100000;
state <= 5'd2;
end else begin
// busy, so keep asking
end
end
// startup sequence: send "identify drive" command
5'd2: begin
io_write <= 1'b1;
io_addr <= `ADDR_COMMAND;
io_data_out <= 16'h00ec;
state <= 5'd3;
end
// wait for the ATA to send an IRQ, then read the status register
5'd3: begin
if (debounced_ata_intrq) begin
io_en <= 1'b1;
io_write <= 1'b0;
io_addr <= `ADDR_STATUS;
aux_counter <= 8'd60;
state <= 5'd4;
end else begin
io_en <= 1'b0;
io_write <= 1'b0;
end
end
// skip 60 words from the data buffer, then read
// the high 16 bits of the capacity
5'd4: begin
io_write <= 1'b0;
io_addr <= `ADDR_DATA;
if (aux_counter == 0) state <= 5'd5;
else aux_counter <= aux_counter - 1;
end
// store the high 16 bits of the capacity just
// read and read the low 16 bits
5'd5: begin
io_write <= 1'b0;
io_addr <= `ADDR_DATA;
capacity [15:0] <= io_data_in;
state <= 5'd6;
end
// store the low 16 bits of the capacity,
// then read another 194 words to finish the
// "identify drive" buffer
5'd6: begin
capacity [31:16] <= io_data_in;
state <= 5'd7;
io_write <= 1'b0;
io_addr <= `ADDR_DATA;
aux_counter <= 8'd193; // one is read now
end
// skip another 193 words from the buffer
5'd7: begin
if (aux_counter == 0) begin
io_en <= 1'b0;
io_write <= 1'b0;
state <= 5'd8;
diskInitialized <= 1'b1;
end else begin
aux_counter <= aux_counter - 1;
end
end
//----------------------------------------------------------
// ready and waiting for commands. Only on this
// state is write access from the on-chip bus
// allowed. When a request arrives, write the
// drive/head/lba3 register and goto state 9.
5'd8: begin
if (startBit) begin
state <= 5'd19;
io_en <= 1'b1;
io_write <= 1'b0;
io_addr <= `ADDR_STATUS;
end else begin
io_en <= 1'b0;
end
end
5'd19: begin
if (io_data_in[7] == 0) begin
state <= 5'd9;
io_en <= 1'b1;
io_write <= 1'b1;
io_addr <= `ADDR_LBA3_DRV;
io_data_out <=
{ 8'd0, 4'b1110, requestedSectorAddress [27:24] };
sector_counter <= 3'd0;
end else begin
// read status again
end
end
// next, write the lba2 register
5'd9: begin
io_addr <= `ADDR_LBA2;
io_data_out <= { 8'd0, requestedSectorAddress [23:16] };
state <= 5'd10;
end
// next, write the lba1 register
5'd10: begin
io_addr <= `ADDR_LBA1;
io_data_out <= { 8'd0, requestedSectorAddress [15:8] };
state <= 5'd11;
end
// next, write the lba0 register
5'd11: begin
io_addr <= `ADDR_LBA0;
io_data_out <= { 8'd0, requestedSectorAddress [7:0] };
state <= 5'd12;
end
// next, write the sector count register
5'd12: begin
io_addr <= `ADDR_SECTOR_COUNT;
io_data_out <= { 8'd0, 4'd0, requestedSectorCount };
state <= 5'd13;
end
// finally, write the command register
5'd13: begin
io_addr <= `ADDR_COMMAND;
io_data_out <= requestedWrite ? 16'h30 : 16'h20;
state <= 5'd14;
end
// now branch whether reading or writing.
// for reading, wait for IRQ, then read status
// for writing, wait for DRQ and simultaneously
// fetch the first word from the buffer
5'd14: begin
if (requestedWrite) begin
io_en <= 1'b1;
io_write <= 1'b0;
io_addr <= `ADDR_STATUS;
state <= 5'd17;
aux_counter <= 8'd0;
end else begin
if (debounced_ata_intrq) begin
io_en <= 1'b1;
io_write <= 1'b0;
io_addr <= `ADDR_STATUS;
state <= 5'd15;
end else begin
io_en <= 1'b0;
end
end
end
// read 256 words of data
5'd15: begin
io_en <= 1'b1;
io_write <= 1'b0;
io_addr <= `ADDR_DATA;
aux_counter <= 8'd0;
state <= 5'd16;
end
// sample data in, and read next if needed. Data sampling is
// done directly by the blockRAM, and the necessary wiring is
// defined above.
5'd16: begin
if (aux_counter == 8'd255) begin
if (requestedSectorCount == 4'b0001) begin
io_en <= 1'b0;
state <= 5'd8;
errorOutput <= 1'b0;
operationFinished <= 1'b1;
end else begin
if (debounced_ata_intrq) begin
requestedSectorCount <= requestedSectorCount - 1;
sector_counter <= sector_counter + 1;
io_en <= 1'b1;
io_write <= 1'b0;
io_addr <= `ADDR_STATUS;
state <= 5'd15;
end else begin
io_en <= 1'b0;
// last word of finished sector is sampled
// repeatedly here (harmless)
end
end
end else begin
aux_counter <= aux_counter + 1;
end
end
// if DRQ is not yet set, wait for it. Otherwise send the
// first data word to the ATA and fetch the next one
5'd17: begin
if (io_data_in[7] == 0 && io_data_in[3] == 1) begin
io_en <= 1'b1;
io_write <= 1'b1;
io_addr <= `ADDR_DATA;
io_data_out <= buffer_ata_dout;
aux_counter <= aux_counter + 1;
state <= 5'd18;
end else begin
// read status again
end
end
// write words to the buffer until finished. Note that since
// an ATA transfer cycle takes at least two clock cycles, the
// buffer is always read to buffer_ata_dout before that register
// is used. After the transfer is finished, wait for IRQ, then
// read the status register and select the correct next state
// depending on whether more sectors must follow.
5'd18: begin
// loop until done. All addressing is done automatically.
if (aux_counter == 8'd0) begin
if (debounced_ata_intrq) begin
io_en <= 1'b1;
io_write <= 1'b0;
io_addr <= `ADDR_STATUS;
if (requestedSectorCount == 4'b0001) begin
state <= 5'd8;
errorOutput <= 1'b0;
operationFinished <= 1'b1;
end else begin
requestedSectorCount <= requestedSectorCount - 1;
sector_counter <= sector_counter + 1;
state <= 5'd17;
end
end else begin
io_en <= 1'b0;
end
end else begin
io_data_out <= buffer_ata_dout;
aux_counter <= aux_counter + 1;
end
end
endcase
end else begin
/*
STARTUP DEBUG LOGGING
buffer_ata_write <= 0;
*/
end
end
end
endmodule
|
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
// Date : Tue Sep 17 19:44:37 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub
// d:/github/Digital-Hardware-Modelling/xilinx-vivado/gcd_snickerdoodle/gcd_snickerdoodle.srcs/sources_1/bd/gcd_zynq_snick/ip/gcd_zynq_snick_rst_ps7_0_49M_0/gcd_zynq_snick_rst_ps7_0_49M_0_stub.v
// Design : gcd_zynq_snick_rst_ps7_0_49M_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg400-3
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "proc_sys_reset,Vivado 2018.2" *)
module gcd_zynq_snick_rst_ps7_0_49M_0(slowest_sync_clk, ext_reset_in, aux_reset_in,
mb_debug_sys_rst, dcm_locked, mb_reset, bus_struct_reset, peripheral_reset,
interconnect_aresetn, peripheral_aresetn)
/* synthesis syn_black_box black_box_pad_pin="slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]" */;
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
output [0:0]bus_struct_reset;
output [0:0]peripheral_reset;
output [0:0]interconnect_aresetn;
output [0:0]peripheral_aresetn;
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module fifo_w16_d3_A_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd4;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module fifo_w16_d3_A (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd4;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
fifo_w16_d3_A_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_fifo_w16_d3_A_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
/* this file automatically generated by make_wp.py script
* for file rtl/ictlb.v
* for module ictlb
* with the instance name ictlb_dut
*/
`include "scmem.vh"
`define L1IT_PASSTHROUGH
module ictlb_wp(
/* verilator lint_off UNUSED */
input logic clk
,input logic reset
// core interface
,input logic coretoictlb_pc_valid
,output logic coretoictlb_pc_retry
// ,input I_coretoictlb_pc_type coretoictlb_pc
,input CORE_reqid_type coretoictlb_pc_coreid
,input SC_laddr_type coretoictlb_pc_laddr
,input SC_sptbr_type coretoictlb_pc_sptbr
// prefetch request (uses the fwd port opportunistically)
,input logic pfetol1tlb_req_valid
,output logic pfetol1tlb_req_retry
// ,input I_pfetol1tlb_req_type pfetol1tlb_req
,input logic pfetol1tlb_req_l2
,input SC_laddr_type pfetol1tlb_req_laddr
,input SC_sptbr_type pfetol1tlb_req_sptbr
// forward st core interface
,output logic l1tlbtol1_fwd_valid
,input logic l1tlbtol1_fwd_retry
// ,output I_l1tlbtol1_fwd_type l1tlbtol1_fwd
,output CORE_reqid_type l1tlbtol1_fwd_coreid
,output logic l1tlbtol1_fwd_prefetch
,output logic l1tlbtol1_fwd_l2_prefetch
,output SC_fault_type l1tlbtol1_fwd_fault
,output TLB_hpaddr_type l1tlbtol1_fwd_hpaddr
,output SC_ppaddr_type l1tlbtol1_fwd_ppaddr
// Notify the L1 that the index of the TLB is gone
,output logic l1tlbtol1_cmd_valid
,input logic l1tlbtol1_cmd_retry
// ,output I_l1tlbtol1_cmd_type l1tlbtol1_cmd
,output logic l1tlbtol1_cmd_flush
,output TLB_hpaddr_type l1tlbtol1_cmd_hpaddr
// Interface with the L2 TLB
,input logic l2tlbtol1tlb_snoop_valid
,output logic l2tlbtol1tlb_snoop_retry
// ,input I_l2tlbtol1tlb_snoop_type l2tlbtol1tlb_snoop
,input TLB_reqid_type l2tlbtol1tlb_snoop_rid
,input TLB_hpaddr_type l2tlbtol1tlb_snoop_hpaddr
,input logic l2tlbtol1tlb_ack_valid
,output logic l2tlbtol1tlb_ack_retry
// ,input I_l2tlbtol1tlb_ack_type l2tlbtol1tlb_ack
,input TLB_reqid_type l2tlbtol1tlb_ack_rid
,input TLB_hpaddr_type l2tlbtol1tlb_ack_hpaddr
,input SC_ppaddr_type l2tlbtol1tlb_ack_ppaddr
,input SC_dctlbe_type l2tlbtol1tlb_ack_dctlbe
,output logic l1tlbtol2tlb_req_valid
,input logic l1tlbtol2tlb_req_retry
// ,output I_l1tlbtol2tlb_req_type l1tlbtol2tlb_req
,output TLB_reqid_type l1tlbtol2tlb_req_rid
,output logic l1tlbtol2tlb_req_disp_req
,output logic l1tlbtol2tlb_req_disp_A
,output logic l1tlbtol2tlb_req_disp_D
,output TLB_hpaddr_type l1tlbtol2tlb_req_disp_hpaddr
,output SC_laddr_type l1tlbtol2tlb_req_laddr
,output SC_sptbr_type l1tlbtol2tlb_req_sptbr
,output logic l1tlbtol2tlb_sack_valid
,input logic l1tlbtol2tlb_sack_retry
// ,output I_l1tlbtol2tlb_sack_type l1tlbtol2tlb_sack
,output TLB_reqid_type l1tlbtol2tlb_sack_rid
/* verilator lint_on UNUSED */
);
I_coretoictlb_pc_type coretoictlb_pc;
assign coretoictlb_pc.coreid = coretoictlb_pc_coreid;
assign coretoictlb_pc.laddr = coretoictlb_pc_laddr;
assign coretoictlb_pc.sptbr = coretoictlb_pc_sptbr;
I_pfetol1tlb_req_type pfetol1tlb_req;
assign pfetol1tlb_req.l2 = pfetol1tlb_req_l2;
assign pfetol1tlb_req.laddr = pfetol1tlb_req_laddr;
assign pfetol1tlb_req.sptbr = pfetol1tlb_req_sptbr;
I_l1tlbtol1_fwd_type l1tlbtol1_fwd;
assign l1tlbtol1_fwd_coreid = l1tlbtol1_fwd.coreid;
assign l1tlbtol1_fwd_prefetch = l1tlbtol1_fwd.prefetch;
assign l1tlbtol1_fwd_l2_prefetch = l1tlbtol1_fwd.l2_prefetch;
assign l1tlbtol1_fwd_fault = l1tlbtol1_fwd.fault;
assign l1tlbtol1_fwd_hpaddr = l1tlbtol1_fwd.hpaddr;
assign l1tlbtol1_fwd_ppaddr = l1tlbtol1_fwd.ppaddr;
I_l1tlbtol1_cmd_type l1tlbtol1_cmd;
assign l1tlbtol1_cmd_flush = l1tlbtol1_cmd.flush;
assign l1tlbtol1_cmd_hpaddr = l1tlbtol1_cmd.hpaddr;
I_l2tlbtol1tlb_snoop_type l2tlbtol1tlb_snoop;
assign l2tlbtol1tlb_snoop.rid = l2tlbtol1tlb_snoop_rid;
assign l2tlbtol1tlb_snoop.hpaddr = l2tlbtol1tlb_snoop_hpaddr;
I_l2tlbtol1tlb_ack_type l2tlbtol1tlb_ack;
assign l2tlbtol1tlb_ack.rid = l2tlbtol1tlb_ack_rid;
assign l2tlbtol1tlb_ack.hpaddr = l2tlbtol1tlb_ack_hpaddr;
assign l2tlbtol1tlb_ack.ppaddr = l2tlbtol1tlb_ack_ppaddr;
assign l2tlbtol1tlb_ack.dctlbe = l2tlbtol1tlb_ack_dctlbe;
I_l1tlbtol2tlb_req_type l1tlbtol2tlb_req;
assign l1tlbtol2tlb_req_rid = l1tlbtol2tlb_req.rid;
assign l1tlbtol2tlb_req_disp_req = l1tlbtol2tlb_req.disp_req;
assign l1tlbtol2tlb_req_disp_A = l1tlbtol2tlb_req.disp_A;
assign l1tlbtol2tlb_req_disp_D = l1tlbtol2tlb_req.disp_D;
assign l1tlbtol2tlb_req_disp_hpaddr = l1tlbtol2tlb_req.disp_hpaddr;
assign l1tlbtol2tlb_req_laddr = l1tlbtol2tlb_req.laddr;
assign l1tlbtol2tlb_req_sptbr = l1tlbtol2tlb_req.sptbr;
I_l1tlbtol2tlb_sack_type l1tlbtol2tlb_sack;
assign l1tlbtol2tlb_sack_rid = l1tlbtol2tlb_sack.rid;
ictlb ictlb_dut(.*);
endmodule
|
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