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// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of avfb_chip_tb
//
// Generated
// by: wig
// on: Tue Apr 18 07:50:26 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bugver.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: avfb_chip_tb.v,v 1.1 2006/04/19 07:33:12 wig Exp $
// $Date: 2006/04/19 07:33:12 $
// $Log: avfb_chip_tb.v,v $
// Revision 1.1 2006/04/19 07:33:12 wig
// Updated/added testcase for 20060404c issue. Needs more work!
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.82 2006/04/13 13:31:52 wig Exp
//
// Generator: mix_0.pl Revision: 1.44 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of avfb_chip_tb
//
// No user `defines in this module
module avfb_chip_tb
//
// Generated module avfb_chip_tb
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for dut
avfb_chip dut (
);
// End of Generated Instance Port Map for dut
endmodule
//
// End of Generated Module rtl of avfb_chip_tb
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLRBN_TB_V
`define SKY130_FD_SC_HD__DLRBN_TB_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dlrbn.v"
module top();
// Inputs are registered
reg RESET_B;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 RESET_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 RESET_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 RESET_B = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 RESET_B = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg GATE_N;
initial
begin
GATE_N = 1'b0;
end
always
begin
#5 GATE_N = ~GATE_N;
end
sky130_fd_sc_hd__dlrbn dut (.RESET_B(RESET_B), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .GATE_N(GATE_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLRBN_TB_V
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2007 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file tcam_usr.v when simulating
// the core, tcam_usr. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module tcam_usr(
clk,
cmp_data_mask,
cmp_din,
data_mask,
din,
we,
wr_addr,
busy,
match,
match_addr);
input clk;
input [31 : 0] cmp_data_mask;
input [31 : 0] cmp_din;
input [31 : 0] data_mask;
input [31 : 0] din;
input we;
input [10 : 0] wr_addr;
output busy;
output match;
output [2047 : 0] match_addr;
// synthesis translate_off
CAM_V5_1 #(
.c_addr_type(2),
.c_cmp_data_mask_width(32),
.c_cmp_din_width(32),
.c_data_mask_width(32),
.c_depth(2048),
.c_din_width(32),
.c_enable_rlocs(0),
.c_has_cmp_data_mask(1),
.c_has_cmp_din(1),
.c_has_data_mask(1),
.c_has_en(0),
.c_has_multiple_match(0),
.c_has_read_warning(0),
.c_has_single_match(0),
.c_has_we(1),
.c_has_wr_addr(1),
.c_match_addr_width(2048),
.c_match_resolution_type(0),
.c_mem_init(0),
.c_mem_init_file("tcam_usr.mif"),
.c_mem_type(0),
.c_read_cycles(1),
.c_reg_outputs(0),
.c_ternary_mode(2),
.c_width(32),
.c_wr_addr_width(11))
inst (
.CLK(clk),
.CMP_DATA_MASK(cmp_data_mask),
.CMP_DIN(cmp_din),
.DATA_MASK(data_mask),
.DIN(din),
.WE(we),
.WR_ADDR(wr_addr),
.BUSY(busy),
.MATCH(match),
.MATCH_ADDR(match_addr),
.EN(),
.MULTIPLE_MATCH(),
.READ_WARNING(),
.SINGLE_MATCH());
// synthesis translate_on
endmodule
|
// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pix_pll_bt.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module pix_pll_bt (
areset,
inclk0,
c0,
c1,
locked);
input areset;
input inclk0;
output c0;
output c1;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "5"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "29.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "58.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "29.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "29.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "58.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pix_pll_bt.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "34482"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "Left_Right"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk6 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk7 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk8 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk9 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "7"
// Retrieval info: USED_PORT: @clk 0 0 7 0 OUTPUT_CLK_EXT VCC "@clk[6..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pix_pll_bt.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pix_pll_bt.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pix_pll_bt.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pix_pll_bt.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pix_pll_bt.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pix_pll_bt_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pix_pll_bt_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
// -*- Mode: Verilog -*-
// Filename : uart_echo.v
// Description : FPGA Top Level for UART Echo
// Author : Philip Tracton
// Created On : Wed Apr 22 12:30:26 2015
// Last Modified By: Philip Tracton
// Last Modified On: Wed Apr 22 12:30:26 2015
// Update Count : 0
// Status : Unknown, Use with caution!
module uart_echo (/*AUTOARG*/
// Outputs
TX,
// Inputs
CLK, RESET, RX
) ;
//---------------------------------------------------------------------------
//
// PARAMETERS
//
//---------------------------------------------------------------------------
//---------------------------------------------------------------------------
//
// PORTS
//
//---------------------------------------------------------------------------
input CLK;
input RESET;
input RX;
output TX;
//---------------------------------------------------------------------------
//
// Registers
//
//---------------------------------------------------------------------------
/*AUTOREG*/
reg [7:0] tx_byte;
reg transmit;
reg rx_fifo_pop;
//---------------------------------------------------------------------------
//
// WIRES
//
//---------------------------------------------------------------------------
/*AUTOWIRE*/
wire [7:0] rx_byte;
wire irq;
wire busy;
wire tx_fifo_full;
wire rx_fifo_empty;
wire is_transmitting;
//---------------------------------------------------------------------------
//
// COMBINATIONAL LOGIC
//
//---------------------------------------------------------------------------
//---------------------------------------------------------------------------
//
// SEQUENTIAL LOGIC
//
//---------------------------------------------------------------------------
uart_fifo uart_fifo(
// Outputs
.rx_byte (rx_byte[7:0]),
.tx (TX),
.irq (irq),
.busy (busy),
.tx_fifo_full (tx_fifo_full),
.rx_fifo_empty (rx_fifo_empty),
// .is_transmitting (is_transmitting),
// Inputs
.tx_byte (tx_byte[7:0]),
.clk (CLK),
.rst (RESET),
.rx (RX),
.transmit (transmit),
.rx_fifo_pop (rx_fifo_pop));
//
// If we get an interrupt and the tx fifo is not full, read the receive byte
// and send it back as the transmit byte, signal transmit and pop the byte from
// the receive FIFO.
//
always @(posedge CLK)
if (RESET) begin
tx_byte <= 8'h00;
transmit <= 1'b0;
rx_fifo_pop <= 1'b0;
end else begin
if (!rx_fifo_empty & !tx_fifo_full & !transmit /*& !is_transmitting*/) begin
tx_byte <= rx_byte;
transmit <= 1'b1;
rx_fifo_pop <= 1'b1;
end else begin
tx_byte <= 8'h00;
transmit <= 1'b0;
rx_fifo_pop <= 1'b0;
end
end // else: !if(RESET)
endmodule // uart_echo
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE Master Model ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// [email protected] ////
//// ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: wb_mast_model.v.rca 1.1.1.1 Tue Jun 7 09:38:58 2011 copew1 Experimental haskis1 haskis1 $
//
// $Date: Tue Jun 7 09:38:58 2011 $
// $Revision: 1.1.1.1 $
// $Author: copew1 $
// $Locker: haskis1 haskis1 $
// $State: Experimental $
//
// Change History:
// $Log: wb_mast_model.v.rca $
//
// Revision: 1.1.1.1 Tue Jun 7 09:38:58 2011 copew1
// first stab at merging s0903a branch.
//
// Revision: 1.1 Fri Jun 3 12:43:38 2011 tractp1
// wishbone master to control UART in test bench
// Revision 1.2 2002/10/03 05:40:03 rudi
// Fixed a minor bug in parameter passing, updated headers and specification.
//
// Revision 1.1.1.1 2001/10/19 11:04:23 rudi
// WISHBONE CONMAX IP Core
//
//
//
//
//
//`include "wb_model_defines.v"
`include "timescale.v"
module wb_mast(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty);
input clk, rst;
output [31:0] adr;
input [31:0] din;
output [31:0] dout;
output cyc, stb;
output [3:0] sel;
output we;
input ack, err, rty;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
parameter mem_size = 4096;
reg [31:0] adr;
reg [31:0] dout;
reg cyc, stb;
reg [3:0] sel;
reg we;
reg [31:0] mem[mem_size:0];
integer cnt;
////////////////////////////////////////////////////////////////////
//
// Memory Logic
//
initial
begin
//adr = 32'hxxxx_xxxx;
//adr = 0;
adr = 32'hffff_ffff;
dout = 32'hxxxx_xxxx;
cyc = 0;
stb = 0;
sel = 4'hx;
we = 1'hx;
cnt = 0;
#1;
$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
end
task mem_fill;
integer n;
begin
cnt = 0;
cnt = 0;
for(n=0;n<mem_size;n=n+1)
begin
mem[n] = $random;
end
end
endtask
////////////////////////////////////////////////////////////////////
//
// Write 1 Word Task
//
task wb_wr1;
input [31:0] a;
input [3:0] s;
input [31:0] d;
begin
//@(posedge clk);
#1;
adr = a;
dout = d;
cyc = 1;
stb = 1;
we=1;
sel = s;
@(posedge clk);
while(~ack & ~err) @(posedge clk);
#1;
cyc=0;
stb=0;
//adr = 32'hffff_ffff;
//adr = 32'hffff_ffff;
//adr = 0;
//dout = 32'hffff_ffff;
we = 1'h0;
sel = 4'h0;
adr = $random;
dout = $random;
end
endtask
////////////////////////////////////////////////////////////////////
//
// Write 4 Words Task
//
task wb_wr4;
input [31:0] a;
input [3:0] s;
input delay;
input [31:0] d1;
input [31:0] d2;
input [31:0] d3;
input [31:0] d4;
integer delay;
begin
@(posedge clk);
#1;
cyc = 1;
sel = s;
adr = $random;
repeat(delay)
begin
@(posedge clk);
#1;
end
adr = a;
dout = d1;
stb = 1;
we=1;
while(~ack & ~err) @(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;
adr = $random;
repeat(delay)
begin
@(posedge clk);
#1;
end
stb=1;
adr = a+4;
dout = d2;
we=1;
@(posedge clk);
while(~ack & ~err) @(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;
repeat(delay)
begin
@(posedge clk);
#1;
end
stb=1;
adr = a+8;
dout = d3;
we=1;
@(posedge clk);
while(~ack & ~err) @(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;
adr = $random;
repeat(delay)
begin
@(posedge clk);
#1;
end
stb=1;
adr = a+12;
dout = d4;
we=1;
@(posedge clk);
while(~ack & ~err) @(posedge clk);
#1;
stb=0;
cyc=0;
adr = 32'hxxxx_xxxx;
adr = $random;
//adr = 0;
//adr = 32'hffff_ffff;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;
end
endtask
task wb_wr_mult;
input [31:0] a;
input [3:0] s;
input delay;
input count;
integer delay;
integer count;
integer n;
begin
//@(posedge clk);
#1;
cyc = 1;
adr = $random;
for(n=0;n<count;n=n+1)
begin
repeat(delay)
begin
@(posedge clk);
#1;
end
adr = a + (n*4);
dout = mem[n + cnt];
stb = 1;
we=1;
sel = s;
if(n!=0) @(posedge clk);
while(~ack & ~err) @(posedge clk);
#2;
stb=0;
we=1'bx;
sel = 4'hx;
dout = 32'hxxxx_xxxx;
//adr = 32'hxxxx_xxxx;
adr = $random;
end
cyc=0;
adr = 32'hxxxx_xxxx;
//adr = 32'hffff_ffff;
cnt = cnt + count;
end
endtask
task wb_rmw;
input [31:0] a;
input [3:0] s;
input delay;
input rcount;
input wcount;
integer delay;
integer rcount;
integer wcount;
integer n;
begin
@(posedge clk);
#1;
cyc = 1;
we = 0;
sel = s;
repeat(delay) @(posedge clk);
for(n=0;n<rcount-1;n=n+1)
begin
adr = a + (n*4);
stb = 1;
while(~ack & ~err) @(posedge clk);
mem[n + cnt] = din;
//$display("Rd Mem[%0d]: %h", (n + cnt), mem[n + cnt] );
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hxxxx_xxxx;
repeat(delay)
begin
@(posedge clk);
#1;
end
we = 0;
sel = s;
end
adr = a+(n*4);
stb = 1;
@(posedge clk);
while(~ack & ~err) @(posedge clk);
mem[n + cnt] = din;
//$display("Rd Mem[%0d]: %h", (n + cnt), mem[n + cnt] );
#1;
stb=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hxxxx_xxxx;
cnt = cnt + rcount;
//@(posedge clk);
for(n=0;n<wcount;n=n+1)
begin
repeat(delay)
begin
@(posedge clk);
#1;
end
adr = a + (n*4);
dout = mem[n + cnt];
stb = 1;
we=1;
sel = s;
// if(n!=0)
@(posedge clk);
while(~ack & ~err) @(posedge clk);
#2;
stb=0;
we=1'bx;
sel = 4'hx;
dout = 32'hxxxx_xxxx;
adr = 32'hxxxx_xxxx;
end
cyc=0;
adr = 32'hxxxx_xxxx;
//adr = 32'hffff_ffff;
cnt = cnt + wcount;
end
endtask
task wb_wmr;
input [31:0] a;
input [3:0] s;
input delay;
input rcount;
input wcount;
integer delay;
integer rcount;
integer wcount;
integer n;
begin
@(posedge clk);
#1;
cyc = 1;
we = 1'bx;
sel = 4'hx;
sel = s;
for(n=0;n<wcount;n=n+1)
begin
repeat(delay)
begin
@(posedge clk);
#1;
end
adr = a + (n*4);
dout = mem[n + cnt];
stb = 1;
we=1;
sel = s;
@(posedge clk);
while(~ack & ~err) @(posedge clk);
#2;
stb=0;
we=1'bx;
sel = 4'hx;
dout = 32'hxxxx_xxxx;
adr = 32'hxxxx_xxxx;
end
cnt = cnt + wcount;
stb=0;
repeat(delay) @(posedge clk);
#1;
sel = s;
we = 0;
for(n=0;n<rcount-1;n=n+1)
begin
adr = a + (n*4);
stb = 1;
while(~ack & ~err) @(posedge clk);
mem[n + cnt] = din;
//$display("Rd Mem[%0d]: %h", (n + cnt), mem[n + cnt] );
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hxxxx_xxxx;
repeat(delay)
begin
@(posedge clk);
#1;
end
we = 0;
sel = s;
end
adr = a+(n*4);
stb = 1;
@(posedge clk);
while(~ack & ~err) @(posedge clk);
mem[n + cnt] = din;
cnt = cnt + rcount;
//$display("Rd Mem[%0d]: %h", (n + cnt), mem[n + cnt] );
#1;
cyc = 0;
stb = 0;
we = 1'hx;
sel = 4'hx;
adr = 32'hxxxx_xxxx;
end
endtask
////////////////////////////////////////////////////////////////////
//
// Read 1 Word Task
//
task wb_rd1;
input [31:0] a;
input [3:0] s;
output [31:0] d;
begin
//@(posedge clk);
#1;
adr = a;
cyc = 1;
stb = 1;
we = 0;
sel = s;
//@(posedge clk);
while(~ack & ~err) @(posedge clk);
d = din;
#1;
cyc=0;
stb=0;
//adr = 32'hxxxx_xxxx;
//adr = 0;
adr = 32'hffff_ffff;
//dout = 32'hxxxx_xxxx;
we = 1'h0;
sel = 4'h0;
adr = $random;
dout = $random;
end
endtask
////////////////////////////////////////////////////////////////////
//
// Read 4 Words Task
//
task wb_rd4;
input [31:0] a;
input [3:0] s;
input delay;
output [31:0] d1;
output [31:0] d2;
output [31:0] d3;
output [31:0] d4;
integer delay;
begin
@(posedge clk);
#1;
cyc = 1;
we = 0;
adr = $random;
sel = s;
repeat(delay) @(posedge clk);
adr = a;
stb = 1;
while(~ack & ~err) @(posedge clk);
d1 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
adr = $random;
repeat(delay)
begin
@(posedge clk);
#1;
end
we = 0;
sel = s;
adr = a+4;
stb = 1;
@(posedge clk);
while(~ack & ~err) @(posedge clk);
d2 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
adr = $random;
repeat(delay)
begin
@(posedge clk);
#1;
end
we = 0;
sel = s;
adr = a+8;
stb = 1;
@(posedge clk);
while(~ack & ~err) @(posedge clk);
d3 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
adr = $random;
repeat(delay)
begin
@(posedge clk);
#1;
end
we = 0;
sel = s;
adr = a+12;
stb = 1;
@(posedge clk);
while(~ack & ~err) @(posedge clk);
d4 = din;
#1;
stb=0;
cyc=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hffff_ffff;
adr = $random;
end
endtask
task wb_rd_mult;
input [31:0] a;
input [3:0] s;
input delay;
input count;
integer delay;
integer count;
integer n;
begin
//@(posedge clk);
#1;
cyc = 1;
we = 0;
sel = s;
repeat(delay) @(posedge clk);
for(n=0;n<count-1;n=n+1)
begin
adr = a + (n*4);
stb = 1;
while(~ack & ~err) @(posedge clk);
mem[n + cnt] = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
//adr = 32'hxxxx_xxxx;
adr = $random;
repeat(delay)
begin
@(posedge clk);
#1;
end
we = 0;
sel = s;
end
adr = a+(n*4);
stb = 1;
@(posedge clk);
while(~ack & ~err) @(posedge clk);
mem[n + cnt] = din;
#1;
stb=0;
cyc=0;
we = 1'hx;
sel = 4'hx;
//adr = 32'hffff_ffff;
//adr = 32'hxxxx_xxxx;
adr = $random;
cnt = cnt + count;
end
endtask
endmodule
|
module PLLE2_ADV #(
parameter BANDWIDTH = "OPTIMIZED",
parameter integer CLKFBOUT_MULT = 5,
parameter real CLKFBOUT_PHASE = 0.000,
parameter real CLKIN1_PERIOD = 0.000,
parameter real CLKIN2_PERIOD = 0.000,
parameter integer CLKOUT0_DIVIDE = 1,
parameter real CLKOUT0_DUTY_CYCLE = 0.500,
parameter real CLKOUT0_PHASE = 0.000,
parameter integer CLKOUT1_DIVIDE = 1,
parameter real CLKOUT1_DUTY_CYCLE = 0.500,
parameter real CLKOUT1_PHASE = 0.000,
parameter integer CLKOUT2_DIVIDE = 1,
parameter real CLKOUT2_DUTY_CYCLE = 0.500,
parameter real CLKOUT2_PHASE = 0.000,
parameter integer CLKOUT3_DIVIDE = 1,
parameter real CLKOUT3_DUTY_CYCLE = 0.500,
parameter real CLKOUT3_PHASE = 0.000,
parameter integer CLKOUT4_DIVIDE = 1,
parameter real CLKOUT4_DUTY_CYCLE = 0.500,
parameter real CLKOUT4_PHASE = 0.000,
parameter integer CLKOUT5_DIVIDE = 1,
parameter real CLKOUT5_DUTY_CYCLE = 0.500,
parameter real CLKOUT5_PHASE = 0.000,
parameter COMPENSATION = "ZHOLD",
parameter integer DIVCLK_DIVIDE = 1,
parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0,
parameter [0:0] IS_PWRDWN_INVERTED = 1'b0,
parameter [0:0] IS_RST_INVERTED = 1'b0,
parameter real REF_JITTER1 = 0.010,
parameter real REF_JITTER2 = 0.010,
parameter STARTUP_WAIT = "FALSE"
)(
output CLKOUT0,
output CLKOUT1,
output CLKOUT2,
output CLKOUT3,
output CLKOUT4,
output CLKOUT5,
output [15:0] DO,
output DRDY,
output LOCKED,
output CLKFBOUT,
input CLKFBIN,
input CLKIN1,
input CLKIN2,
input CLKINSEL,
input [6:0] DADDR,
input DCLK,
input DEN,
input [15:0] DI,
input DWE,
input PWRDWN,
input RST
);
//#LOCAL DERIVED PARAMETERS
localparam real VCO_PERIOD = (CLKIN1_PERIOD * DIVCLK_DIVIDE) / CLKFBOUT_MULT;
localparam real CLK0_DELAY = VCO_PERIOD * CLKOUT0_DIVIDE * (CLKOUT0_PHASE/360);
localparam real CLK1_DELAY = VCO_PERIOD * CLKOUT1_DIVIDE * (CLKOUT1_PHASE/360);
localparam real CLK2_DELAY = VCO_PERIOD * CLKOUT2_DIVIDE * (CLKOUT2_PHASE/360);
localparam real CLK3_DELAY = VCO_PERIOD * CLKOUT3_DIVIDE * (CLKOUT3_PHASE/360);
localparam real CLK4_DELAY = VCO_PERIOD * CLKOUT4_DIVIDE * (CLKOUT4_PHASE/360);
localparam real CLK5_DELAY = VCO_PERIOD * CLKOUT5_DIVIDE * (CLKOUT5_PHASE/360);
localparam phases = CLKFBOUT_MULT / DIVCLK_DIVIDE;
//########################################################################
//# POR
//########################################################################
//ugly POR reset
reg POR;
initial
begin
POR=1'b1;
#1
POR=1'b0;
end
//async reset
wire reset;
assign reset = POR | RST;
//########################################################################
//# CLOCK MULTIPLIER
//########################################################################
//TODO: implement DIVCLK_DIVIDE
//
integer j;
reg [2*phases-1:0] delay;
always @ (CLKIN1 or reset)
if(reset)
for(j=0; j<(2*phases); j=j+1)
delay[j] <= 1'b0;
else
for(j=0; j<(2*phases); j=j+1)
delay[j] <= #(CLKIN1_PERIOD*j/(2*phases)) CLKIN1;
reg [(phases)-1:0] clk_comb;
always @ (delay)
begin
for(j=0; j<(phases); j=j+1)
clk_comb[j] <= ~reset & delay[2*j] & ~delay[2*j+1];
end
reg vco_clk;
integer k;
always @*
begin
vco_clk = 1'b0;
for(k=0; k<(phases); k=k+1)
vco_clk = vco_clk | clk_comb[k];
end
//##############
//#DIVIDERS
//##############
wire [3:0] DIVCFG[5:0];
wire [5:0] CLKOUT_DIV;
assign DIVCFG[0] = $clog2(CLKOUT0_DIVIDE);
assign DIVCFG[1] = $clog2(CLKOUT1_DIVIDE);
assign DIVCFG[2] = $clog2(CLKOUT2_DIVIDE);
assign DIVCFG[3] = $clog2(CLKOUT3_DIVIDE);
assign DIVCFG[4] = $clog2(CLKOUT4_DIVIDE);
assign DIVCFG[5] = $clog2(CLKOUT5_DIVIDE);
genvar i;
generate for(i=0; i<6; i=i+1)
begin : gen_clkdiv
clock_divider clkdiv (/*AUTOINST*/
// Outputs
.clkout (CLKOUT_DIV[i]),
// Inputs
.clkin (vco_clk),
.divcfg (DIVCFG[i]),
.reset (reset));
end
endgenerate
reg [5:0] CLKOUT_DIV_LOCK;
always @ (posedge (CLKIN1&vco_clk) or negedge (CLKIN1&~vco_clk))
begin
CLKOUT_DIV_LOCK[5:0] <= CLKOUT_DIV[5:0];
end
//##############
//#SUB PHASE DELAY
//##############
reg CLKOUT0;
reg CLKOUT1;
reg CLKOUT2;
reg CLKOUT3;
reg CLKOUT4;
reg CLKOUT5;
always @ (CLKOUT_DIV_LOCK)
begin
CLKOUT0 <= #(CLK0_DELAY) ~reset & CLKOUT_DIV_LOCK[0];
CLKOUT1 <= #(CLK1_DELAY) ~reset & CLKOUT_DIV_LOCK[1];
CLKOUT2 <= #(CLK2_DELAY) ~reset & CLKOUT_DIV_LOCK[2];
CLKOUT3 <= #(CLK3_DELAY) ~reset & CLKOUT_DIV_LOCK[3];
CLKOUT4 <= #(CLK4_DELAY) ~reset & CLKOUT_DIV_LOCK[4];
CLKOUT5 <= #(CLK5_DELAY) ~reset & CLKOUT_DIV_LOCK[5];
end
//##############
//#DUMMY DRIVES
//##############
assign CLKFBOUT=CLKIN1;
//###########################
//#SANITY CHECK LOCK COUNTER
//############################
localparam LCW=4;
reg [LCW-1:0] lock_counter;
always @ (posedge CLKIN1 or posedge reset)
if(reset)
lock_counter[LCW-1:0] <= {(LCW){1'b1}};
else if(~LOCKED)
lock_counter[LCW-1:0] <= lock_counter[LCW-1:0] - 1'b1;
assign LOCKED = ~(|lock_counter[LCW-1:0]);
endmodule // PLLE2_ADV
// Local Variables:
// verilog-library-directories:("." "../../common/hdl")
// End:
|
module peripheral_bt(clk , rst , d_in , cs , addr , rd , wr, d_out, uart_tx, uart_rx );
input clk;
input rst;
input [15:0]d_in;
input cs;
input [3:0]addr; // 4 LSB from j1_io_addr
input rd;
input wr;
output reg [15:0]d_out;
output uart_rx;
output uart_tx;
//------------------------------------ regs and wires-------------------------------
reg [5:0] s; //selector mux_4 and demux_4
reg uart_enable;
reg [7:0] din_uart; // data in uart
wire [7:0] dout_uart;
wire uart_busy; // out_uart
wire uart_done;
wire uart_avail;
//------------------------------------ regs and wires-------------------------------
bluetooth bt(.rx(uart_rx), .avail(uart_avail), .clk_in(clk), .reset(rst), .dout(dout_uart), .din(din_uart), .enable(uart_enable), .busy(uart_busy), .done(uart_done), .tx(uart_tx));
always @(*) begin//----address_decoder------------------
case (addr)
4'h0:begin s = (cs && wr) ? 5'b00001 : 5'b00000 ;end //din_uart
4'h2:begin s = (cs && rd) ? 5'b00010 : 5'b00000 ;end //done
4'h4:begin s = (cs && rd) ? 5'b00100 : 5'b00000 ;end //avail
4'h6:begin s = (cs && rd) ? 5'b01000 : 5'b00000 ;end //busy
4'h8:begin s = (cs && rd) ? 5'b10000 : 5'b00000 ;end //dout_uart <asdfghjkl
default:begin s=5'b00000 ; end
endcase
end//-----------------address_decoder--------------------
wire busymachete= (uart_busy | uart_enable);
always @(negedge clk) begin//-------------------- escritura de registros
if (s[0]==1) begin
din_uart<=d_in[7:0];
uart_enable=1;
end
else begin
if (uart_busy)
uart_enable=0;
end
end//------------------------------------------- escritura de registros
always @(negedge clk) begin//-----------------------mux_4 : multiplexa salidas del periferico
case (s)
5'b01000: d_out[0]= busymachete;
5'b00010: d_out[0]= uart_done;
5'b00100: d_out[0]= uart_avail;
5'b10000: d_out[7:0] = dout_uart;
default: d_out=0;
endcase
end//----------------------------------------------mux_4
//(addr != 4'h4): se hace para evitar escrituras fantasm
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND4B_1_V
`define SKY130_FD_SC_LS__AND4B_1_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog wrapper for and4b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__and4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and4b_1 (
X ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__and4b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and4b_1 (
X ,
A_N,
B ,
C ,
D
);
output X ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__and4b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND4B_1_V
|
/*
* These source files contain a hardware description of a network
* automatically generated by CONNECT (CONfigurable NEtwork Creation Tool).
*
* This product includes a hardware design developed by Carnegie Mellon
* University.
*
* Copyright (c) 2012 by Michael K. Papamichael, Carnegie Mellon University
*
* For more information, see the CONNECT project website at:
* http://www.ece.cmu.edu/~mpapamic/connect
*
* This design is provided for internal, non-commercial research use only,
* cannot be used for, or in support of, goods or services, and is not for
* redistribution, with or without modifications.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*
*/
//
// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17)
//
// On Sat Feb 11 18:26:32 EST 2017
//
// Method conflict info:
// Method: outport_encoder
// Conflict-free: outport_encoder
//
//
// Ports:
// Name I/O size props
// outport_encoder O 4
// outport_encoder_vec I 5
//
// Combinational paths from inputs to outputs:
// outport_encoder_vec -> outport_encoder
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module module_outport_encoder(outport_encoder_vec,
outport_encoder);
// value method outport_encoder
input [4 : 0] outport_encoder_vec;
output [3 : 0] outport_encoder;
// signals for module outputs
wire [3 : 0] outport_encoder;
// value method outport_encoder
assign outport_encoder =
{ outport_encoder_vec[0] || outport_encoder_vec[1] ||
outport_encoder_vec[2] ||
outport_encoder_vec[3] ||
outport_encoder_vec[4],
outport_encoder_vec[0] ?
3'd0 :
(outport_encoder_vec[1] ?
3'd1 :
(outport_encoder_vec[2] ?
3'd2 :
(outport_encoder_vec[3] ? 3'd3 : 3'd4))) } ;
endmodule // module_outport_encoder
|
/*
* Copyright (c) 2015, Arch Laboratory
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
module to_sdram
(
input wire clk_sys,
input wire rst,
input wire ao486_rst,
// input pc_bus_sdram
input wire [31:0] pc_bus_sdram_address,
input wire [3:0] pc_bus_sdram_byteenable,
input wire pc_bus_sdram_read,
output wire [31:0] pc_bus_sdram_readdata,
input wire pc_bus_sdram_write,
input wire [31:0] pc_bus_sdram_writedata,
output wire pc_bus_sdram_waitrequest,
output wire pc_bus_sdram_readdatavalid,
input wire [2:0] pc_bus_sdram_burstcount,
// input driver_sd_avm
input wire [31:0] driver_sd_avm_address,
input wire driver_sd_avm_read,
output wire [31:0] driver_sd_avm_readdata,
input wire driver_sd_avm_write,
input wire [31:0] driver_sd_avm_writedata,
output wire driver_sd_avm_waitrequest,
output wire driver_sd_avm_readdatavalid,
// output sdram_mem
output wire [24:0] sdram_address,
output wire [3:0] sdram_byteenable,
output wire sdram_read,
input wire [31:0] sdram_readdata,
output wire sdram_write,
output wire [31:0] sdram_writedata,
input wire sdram_waitrequest,
input wire sdram_readdatavalid,
input wire sdram_chipselect
);
wire [31:0] burst_converted_address;
wire burst_converted_write;
wire [31:0] burst_converted_writedata;
wire burst_converted_read;
wire [31:0] burst_converted_readdata;
wire burst_converted_readdatavalid;
wire [3:0] burst_converted_byteenable;
wire burst_converted_waitrequest;
burst_converter #(.IADDR(32), .OADDR(27))
burst_converter (
.clk_sys (clk_sys),
.rst (rst),
.addr_in (pc_bus_sdram_address),
.write_in (pc_bus_sdram_write),
.writedata_in (pc_bus_sdram_writedata),
.read_in (pc_bus_sdram_read),
.readdata_out (pc_bus_sdram_readdata),
.readdatavalid_out (pc_bus_sdram_readdatavalid),
.byteenable_in (pc_bus_sdram_byteenable),
.burstcount_in (pc_bus_sdram_burstcount),
.waitrequest_out (pc_bus_sdram_waitrequest),
.addr_out (burst_converted_address),
.write_out (burst_converted_write),
.writedata_out (burst_converted_writedata),
.read_out (burst_converted_read),
.readdata_in (burst_converted_readdata),
.readdatavalid_in (burst_converted_readdatavalid),
.byteenable_out (burst_converted_byteenable),
.waitrequest_in (burst_converted_waitrequest)
);
assign sdram_address = (~ao486_rst) ? burst_converted_address[26:2] : driver_sd_avm_address[26:2];
assign sdram_byteenable = (~ao486_rst) ? burst_converted_byteenable : 4'b1111;
assign sdram_read = (~ao486_rst) ? burst_converted_read : (driver_sd_avm_read && driver_sd_avm_address[27]);
assign sdram_write = (~ao486_rst) ? burst_converted_write : (driver_sd_avm_write && driver_sd_avm_address[27]);
assign sdram_writedata = (~ao486_rst) ? burst_converted_writedata : driver_sd_avm_writedata;
assign burst_converted_readdata = (~ao486_rst) ? sdram_readdata : 0;
assign burst_converted_readdatavalid = (~ao486_rst) ? sdram_readdatavalid : 0;
assign burst_converted_waitrequest = (~ao486_rst) ? sdram_waitrequest : 0;
assign driver_sd_avm_readdata = (ao486_rst) ? sdram_readdata : 0;
assign driver_sd_avm_readdatavalid = (ao486_rst) ? sdram_readdatavalid : 0;
assign driver_sd_avm_waitrequest = (ao486_rst) ? sdram_waitrequest : 0;
endmodule
|
module top (
input wire clk,
output wire clk_pr1,
output wire clk_pr2,
input wire rst,
output wire rst_pr1,
output wire rst_pr2,
input wire [3:0] sw,
output wire [3:0] in_pr1,
input wire [3:0] out_pr1,
output wire [3:0] in_pr2,
input wire [3:0] out_pr2,
output wire [3:0] led,
);
// 'data' buffers
wire [3:0] inter;
genvar i;
generate
for (i=0; i < 8; i=i+1) begin
SYN_OBUF in_obuf_pr1(.I(sw[i]), .O(in_pr1[i]));
SYN_IBUF out_ibuf_pr1(.I(out_pr1[i]), .O(inter[i]));
SYN_OBUF in_obuf_pr2(.I(inter[i]), .O(in_pr2[i]));
SYN_IBUF out_ibuf2(.I(out_pr2[i]), .O(led[i]));
end
endgenerate
// clock buffers
IBUF clk_ibuf(.I(clk), .O(clk_ibuf));
BUFG clk_bufg(.I(clk_ibuf), .O(clk_b));
SYN_OBUF clk_obuf1(.I(clk_b), .O(clk_pr1));
SYN_OBUF clk_obuf2(.I(clk_b), .O(clk_pr2));
// reset buffers
SYN_OBUF rst_obuf1(.I(rst), .O(rst_pr1));
SYN_OBUF rst_obuf2(.I(rst), .O(rst_pr2));
endmodule
|
// Generator : SpinalHDL v1.6.0 git head : 73c8d8e2b86b45646e9d0b2e729291f2b65e6be3
// Component : VexRiscv
// Git hash : 22555b464a02d8b7f8ed23cbb87c57aa9acddc90
`define Input2Kind_binary_sequential_type [0:0]
`define Input2Kind_binary_sequential_RS 1'b0
`define Input2Kind_binary_sequential_IMM_I 1'b1
`define EnvCtrlEnum_binary_sequential_type [1:0]
`define EnvCtrlEnum_binary_sequential_NONE 2'b00
`define EnvCtrlEnum_binary_sequential_XRET 2'b01
`define EnvCtrlEnum_binary_sequential_WFI 2'b10
`define EnvCtrlEnum_binary_sequential_ECALL 2'b11
`define BranchCtrlEnum_binary_sequential_type [1:0]
`define BranchCtrlEnum_binary_sequential_INC 2'b00
`define BranchCtrlEnum_binary_sequential_B 2'b01
`define BranchCtrlEnum_binary_sequential_JAL 2'b10
`define BranchCtrlEnum_binary_sequential_JALR 2'b11
`define ShiftCtrlEnum_binary_sequential_type [1:0]
`define ShiftCtrlEnum_binary_sequential_DISABLE_1 2'b00
`define ShiftCtrlEnum_binary_sequential_SLL_1 2'b01
`define ShiftCtrlEnum_binary_sequential_SRL_1 2'b10
`define ShiftCtrlEnum_binary_sequential_SRA_1 2'b11
`define AluBitwiseCtrlEnum_binary_sequential_type [1:0]
`define AluBitwiseCtrlEnum_binary_sequential_XOR_1 2'b00
`define AluBitwiseCtrlEnum_binary_sequential_OR_1 2'b01
`define AluBitwiseCtrlEnum_binary_sequential_AND_1 2'b10
`define Src2CtrlEnum_binary_sequential_type [1:0]
`define Src2CtrlEnum_binary_sequential_RS 2'b00
`define Src2CtrlEnum_binary_sequential_IMI 2'b01
`define Src2CtrlEnum_binary_sequential_IMS 2'b10
`define Src2CtrlEnum_binary_sequential_PC 2'b11
`define AluCtrlEnum_binary_sequential_type [1:0]
`define AluCtrlEnum_binary_sequential_ADD_SUB 2'b00
`define AluCtrlEnum_binary_sequential_SLT_SLTU 2'b01
`define AluCtrlEnum_binary_sequential_BITWISE 2'b10
`define Src1CtrlEnum_binary_sequential_type [1:0]
`define Src1CtrlEnum_binary_sequential_RS 2'b00
`define Src1CtrlEnum_binary_sequential_IMU 2'b01
`define Src1CtrlEnum_binary_sequential_PC_INCREMENT 2'b10
`define Src1CtrlEnum_binary_sequential_URS1 2'b11
module VexRiscv (
input [31:0] externalResetVector,
input timerInterrupt,
input softwareInterrupt,
input [31:0] externalInterruptArray,
output CfuPlugin_bus_cmd_valid,
input CfuPlugin_bus_cmd_ready,
output [9:0] CfuPlugin_bus_cmd_payload_function_id,
output [31:0] CfuPlugin_bus_cmd_payload_inputs_0,
output [31:0] CfuPlugin_bus_cmd_payload_inputs_1,
input CfuPlugin_bus_rsp_valid,
output CfuPlugin_bus_rsp_ready,
input [31:0] CfuPlugin_bus_rsp_payload_outputs_0,
output reg iBusWishbone_CYC,
output reg iBusWishbone_STB,
input iBusWishbone_ACK,
output iBusWishbone_WE,
output [29:0] iBusWishbone_ADR,
input [31:0] iBusWishbone_DAT_MISO,
output [31:0] iBusWishbone_DAT_MOSI,
output [3:0] iBusWishbone_SEL,
input iBusWishbone_ERR,
output [2:0] iBusWishbone_CTI,
output [1:0] iBusWishbone_BTE,
output dBusWishbone_CYC,
output dBusWishbone_STB,
input dBusWishbone_ACK,
output dBusWishbone_WE,
output [29:0] dBusWishbone_ADR,
input [31:0] dBusWishbone_DAT_MISO,
output [31:0] dBusWishbone_DAT_MOSI,
output [3:0] dBusWishbone_SEL,
input dBusWishbone_ERR,
output [2:0] dBusWishbone_CTI,
output [1:0] dBusWishbone_BTE,
input clk,
input reset
);
wire IBusCachedPlugin_cache_io_flush;
wire IBusCachedPlugin_cache_io_cpu_prefetch_isValid;
wire IBusCachedPlugin_cache_io_cpu_fetch_isValid;
wire IBusCachedPlugin_cache_io_cpu_fetch_isStuck;
wire IBusCachedPlugin_cache_io_cpu_fetch_isRemoved;
wire IBusCachedPlugin_cache_io_cpu_decode_isValid;
wire IBusCachedPlugin_cache_io_cpu_decode_isStuck;
wire IBusCachedPlugin_cache_io_cpu_decode_isUser;
reg IBusCachedPlugin_cache_io_cpu_fill_valid;
wire dataCache_1_io_cpu_execute_isValid;
wire [31:0] dataCache_1_io_cpu_execute_address;
wire dataCache_1_io_cpu_memory_isValid;
wire [31:0] dataCache_1_io_cpu_memory_address;
reg dataCache_1_io_cpu_memory_mmuRsp_isIoAccess;
reg dataCache_1_io_cpu_writeBack_isValid;
wire dataCache_1_io_cpu_writeBack_isUser;
wire [31:0] dataCache_1_io_cpu_writeBack_storeData;
wire [31:0] dataCache_1_io_cpu_writeBack_address;
wire dataCache_1_io_cpu_writeBack_fence_SW;
wire dataCache_1_io_cpu_writeBack_fence_SR;
wire dataCache_1_io_cpu_writeBack_fence_SO;
wire dataCache_1_io_cpu_writeBack_fence_SI;
wire dataCache_1_io_cpu_writeBack_fence_PW;
wire dataCache_1_io_cpu_writeBack_fence_PR;
wire dataCache_1_io_cpu_writeBack_fence_PO;
wire dataCache_1_io_cpu_writeBack_fence_PI;
wire [3:0] dataCache_1_io_cpu_writeBack_fence_FM;
wire dataCache_1_io_cpu_flush_valid;
wire dataCache_1_io_mem_cmd_ready;
reg [31:0] _zz_RegFilePlugin_regFile_port0;
reg [31:0] _zz_RegFilePlugin_regFile_port1;
wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt;
wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data;
wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress;
wire IBusCachedPlugin_cache_io_cpu_decode_error;
wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling;
wire IBusCachedPlugin_cache_io_cpu_decode_mmuException;
wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data;
wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss;
wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress;
wire IBusCachedPlugin_cache_io_mem_cmd_valid;
wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address;
wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size;
wire dataCache_1_io_cpu_execute_haltIt;
wire dataCache_1_io_cpu_execute_refilling;
wire dataCache_1_io_cpu_memory_isWrite;
wire dataCache_1_io_cpu_writeBack_haltIt;
wire [31:0] dataCache_1_io_cpu_writeBack_data;
wire dataCache_1_io_cpu_writeBack_mmuException;
wire dataCache_1_io_cpu_writeBack_unalignedAccess;
wire dataCache_1_io_cpu_writeBack_accessError;
wire dataCache_1_io_cpu_writeBack_isWrite;
wire dataCache_1_io_cpu_writeBack_keepMemRspData;
wire dataCache_1_io_cpu_writeBack_exclusiveOk;
wire dataCache_1_io_cpu_flush_ready;
wire dataCache_1_io_cpu_redo;
wire dataCache_1_io_mem_cmd_valid;
wire dataCache_1_io_mem_cmd_payload_wr;
wire dataCache_1_io_mem_cmd_payload_uncached;
wire [31:0] dataCache_1_io_mem_cmd_payload_address;
wire [31:0] dataCache_1_io_mem_cmd_payload_data;
wire [3:0] dataCache_1_io_mem_cmd_payload_mask;
wire [2:0] dataCache_1_io_mem_cmd_payload_size;
wire dataCache_1_io_mem_cmd_payload_last;
wire [51:0] _zz_memory_MUL_LOW;
wire [51:0] _zz_memory_MUL_LOW_1;
wire [51:0] _zz_memory_MUL_LOW_2;
wire [51:0] _zz_memory_MUL_LOW_3;
wire [32:0] _zz_memory_MUL_LOW_4;
wire [51:0] _zz_memory_MUL_LOW_5;
wire [49:0] _zz_memory_MUL_LOW_6;
wire [51:0] _zz_memory_MUL_LOW_7;
wire [49:0] _zz_memory_MUL_LOW_8;
wire [31:0] _zz_execute_SHIFT_RIGHT;
wire [32:0] _zz_execute_SHIFT_RIGHT_1;
wire [32:0] _zz_execute_SHIFT_RIGHT_2;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2;
wire _zz_decode_LEGAL_INSTRUCTION_3;
wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4;
wire [14:0] _zz_decode_LEGAL_INSTRUCTION_5;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8;
wire _zz_decode_LEGAL_INSTRUCTION_9;
wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10;
wire [8:0] _zz_decode_LEGAL_INSTRUCTION_11;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_12;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_13;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_14;
wire _zz_decode_LEGAL_INSTRUCTION_15;
wire [0:0] _zz_decode_LEGAL_INSTRUCTION_16;
wire [2:0] _zz_decode_LEGAL_INSTRUCTION_17;
wire [3:0] _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1;
reg [31:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_5;
wire [1:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_6;
wire [31:0] _zz_IBusCachedPlugin_fetchPc_pc;
wire [2:0] _zz_IBusCachedPlugin_fetchPc_pc_1;
wire [11:0] _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
wire [31:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2;
wire [19:0] _zz__zz_2;
wire [11:0] _zz__zz_4;
wire [31:0] _zz__zz_6;
wire [31:0] _zz__zz_6_1;
wire [19:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload;
wire [11:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_4;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_5;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_6;
wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code;
wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code_1;
reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted;
wire [1:0] _zz_writeBack_DBusCachedPlugin_rspShifted_1;
reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted_2;
wire [0:0] _zz_writeBack_DBusCachedPlugin_rspShifted_3;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6;
wire [26:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18;
wire [22:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33;
wire [19:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45;
wire [16:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68;
wire [13:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100;
wire [10:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101;
wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114;
wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125;
wire [7:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134;
wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138;
wire [2:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166;
wire _zz_RegFilePlugin_regFile_port;
wire _zz_decode_RegFilePlugin_rs1Data;
wire _zz_RegFilePlugin_regFile_port_1;
wire _zz_decode_RegFilePlugin_rs2Data;
wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA;
wire [2:0] _zz__zz_execute_SRC1;
wire [4:0] _zz__zz_execute_SRC1_1;
wire [11:0] _zz__zz_execute_SRC2_3;
wire [31:0] _zz_execute_SrcPlugin_addSub;
wire [31:0] _zz_execute_SrcPlugin_addSub_1;
wire [31:0] _zz_execute_SrcPlugin_addSub_2;
wire [31:0] _zz_execute_SrcPlugin_addSub_3;
wire [31:0] _zz_execute_SrcPlugin_addSub_4;
wire [31:0] _zz_execute_SrcPlugin_addSub_5;
wire [31:0] _zz_execute_SrcPlugin_addSub_6;
wire [19:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_2;
wire [11:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_4;
wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6;
wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1;
wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2;
wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2_2;
wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4;
wire _zz_execute_BranchPlugin_branch_src2_6;
wire _zz_execute_BranchPlugin_branch_src2_7;
wire _zz_execute_BranchPlugin_branch_src2_8;
wire [2:0] _zz_execute_BranchPlugin_branch_src2_9;
wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1;
wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1;
wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3;
wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1;
wire _zz_when;
wire _zz_when_1;
wire [65:0] _zz_writeBack_MulPlugin_result;
wire [65:0] _zz_writeBack_MulPlugin_result_1;
wire [31:0] _zz__zz_decode_RS2_2;
wire [31:0] _zz__zz_decode_RS2_2_1;
wire [5:0] _zz_memory_DivPlugin_div_counter_valueNext;
wire [0:0] _zz_memory_DivPlugin_div_counter_valueNext_1;
wire [32:0] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator;
wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder;
wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder_1;
wire [32:0] _zz_memory_DivPlugin_div_stage_0_outNumerator;
wire [32:0] _zz_memory_DivPlugin_div_result_1;
wire [32:0] _zz_memory_DivPlugin_div_result_2;
wire [32:0] _zz_memory_DivPlugin_div_result_3;
wire [32:0] _zz_memory_DivPlugin_div_result_4;
wire [0:0] _zz_memory_DivPlugin_div_result_5;
wire [32:0] _zz_memory_DivPlugin_rs1_2;
wire [0:0] _zz_memory_DivPlugin_rs1_3;
wire [31:0] _zz_memory_DivPlugin_rs2_1;
wire [0:0] _zz_memory_DivPlugin_rs2_2;
wire [9:0] _zz_execute_CfuPlugin_functionsIds_0;
wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_41;
wire [26:0] _zz_iBusWishbone_ADR_1;
wire [51:0] memory_MUL_LOW;
wire writeBack_CfuPlugin_CFU_IN_FLIGHT;
wire execute_CfuPlugin_CFU_IN_FLIGHT;
wire [33:0] memory_MUL_HH;
wire [33:0] execute_MUL_HH;
wire [33:0] execute_MUL_HL;
wire [33:0] execute_MUL_LH;
wire [31:0] execute_MUL_LL;
wire [31:0] execute_SHIFT_RIGHT;
wire [31:0] execute_REGFILE_WRITE_DATA;
wire [31:0] memory_MEMORY_STORE_DATA_RF;
wire [31:0] execute_MEMORY_STORE_DATA_RF;
wire decode_CSR_READ_OPCODE;
wire decode_CSR_WRITE_OPCODE;
wire decode_PREDICTION_HAD_BRANCHED2;
wire decode_SRC2_FORCE_ZERO;
wire `Input2Kind_binary_sequential_type decode_CfuPlugin_CFU_INPUT_2_KIND;
wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND;
wire `Input2Kind_binary_sequential_type _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND;
wire `Input2Kind_binary_sequential_type _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1;
wire decode_CfuPlugin_CFU_ENABLE;
wire decode_IS_RS2_SIGNED;
wire decode_IS_RS1_SIGNED;
wire decode_IS_DIV;
wire memory_IS_MUL;
wire execute_IS_MUL;
wire decode_IS_MUL;
wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL_1;
wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL_1;
wire `EnvCtrlEnum_binary_sequential_type decode_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL_1;
wire decode_IS_CSR;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL_1;
wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL_1;
wire `ShiftCtrlEnum_binary_sequential_type decode_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL_1;
wire `AluBitwiseCtrlEnum_binary_sequential_type decode_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL_1;
wire decode_SRC_LESS_UNSIGNED;
wire decode_MEMORY_MANAGMENT;
wire memory_MEMORY_WR;
wire decode_MEMORY_WR;
wire execute_BYPASSABLE_MEMORY_STAGE;
wire decode_BYPASSABLE_MEMORY_STAGE;
wire decode_BYPASSABLE_EXECUTE_STAGE;
wire `Src2CtrlEnum_binary_sequential_type decode_SRC2_CTRL;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL_1;
wire `AluCtrlEnum_binary_sequential_type decode_ALU_CTRL;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL_1;
wire `Src1CtrlEnum_binary_sequential_type decode_SRC1_CTRL;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL_1;
wire decode_MEMORY_FORCE_CONSTISTENCY;
wire [31:0] writeBack_FORMAL_PC_NEXT;
wire [31:0] memory_FORMAL_PC_NEXT;
wire [31:0] execute_FORMAL_PC_NEXT;
wire [31:0] decode_FORMAL_PC_NEXT;
wire [31:0] memory_PC;
reg _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT;
reg _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT;
wire memory_CfuPlugin_CFU_IN_FLIGHT;
wire `Input2Kind_binary_sequential_type execute_CfuPlugin_CFU_INPUT_2_KIND;
wire `Input2Kind_binary_sequential_type _zz_execute_CfuPlugin_CFU_INPUT_2_KIND;
wire execute_CfuPlugin_CFU_ENABLE;
wire execute_IS_RS1_SIGNED;
wire execute_IS_DIV;
wire execute_IS_RS2_SIGNED;
wire memory_IS_DIV;
wire writeBack_IS_MUL;
wire [33:0] writeBack_MUL_HH;
wire [51:0] writeBack_MUL_LOW;
wire [33:0] memory_MUL_HL;
wire [33:0] memory_MUL_LH;
wire [31:0] memory_MUL_LL;
wire execute_CSR_READ_OPCODE;
wire execute_CSR_WRITE_OPCODE;
wire execute_IS_CSR;
wire `EnvCtrlEnum_binary_sequential_type memory_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_memory_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type execute_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_execute_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type writeBack_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_writeBack_ENV_CTRL;
wire [31:0] execute_BRANCH_CALC;
wire execute_BRANCH_DO;
wire [31:0] execute_PC;
wire execute_PREDICTION_HAD_BRANCHED2;
(* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ;
wire execute_BRANCH_COND_RESULT;
wire `BranchCtrlEnum_binary_sequential_type execute_BRANCH_CTRL;
wire `BranchCtrlEnum_binary_sequential_type _zz_execute_BRANCH_CTRL;
wire decode_RS2_USE;
wire decode_RS1_USE;
reg [31:0] _zz_decode_RS2;
wire execute_REGFILE_WRITE_VALID;
wire execute_BYPASSABLE_EXECUTE_STAGE;
wire memory_REGFILE_WRITE_VALID;
wire [31:0] memory_INSTRUCTION;
wire memory_BYPASSABLE_MEMORY_STAGE;
wire writeBack_REGFILE_WRITE_VALID;
reg [31:0] decode_RS2;
reg [31:0] decode_RS1;
wire [31:0] memory_SHIFT_RIGHT;
reg [31:0] _zz_decode_RS2_1;
wire `ShiftCtrlEnum_binary_sequential_type memory_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_memory_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type execute_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_SHIFT_CTRL;
wire execute_SRC_LESS_UNSIGNED;
wire execute_SRC2_FORCE_ZERO;
wire execute_SRC_USE_SUB_LESS;
wire [31:0] _zz_execute_SRC2;
wire `Src2CtrlEnum_binary_sequential_type execute_SRC2_CTRL;
wire `Src2CtrlEnum_binary_sequential_type _zz_execute_SRC2_CTRL;
wire `Src1CtrlEnum_binary_sequential_type execute_SRC1_CTRL;
wire `Src1CtrlEnum_binary_sequential_type _zz_execute_SRC1_CTRL;
wire decode_SRC_USE_SUB_LESS;
wire decode_SRC_ADD_ZERO;
wire [31:0] execute_SRC_ADD_SUB;
wire execute_SRC_LESS;
wire `AluCtrlEnum_binary_sequential_type execute_ALU_CTRL;
wire `AluCtrlEnum_binary_sequential_type _zz_execute_ALU_CTRL;
wire [31:0] execute_SRC2;
wire [31:0] execute_SRC1;
wire `AluBitwiseCtrlEnum_binary_sequential_type execute_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_execute_ALU_BITWISE_CTRL;
wire [31:0] _zz_lastStageRegFileWrite_payload_address;
wire _zz_lastStageRegFileWrite_valid;
reg _zz_1;
wire [31:0] decode_INSTRUCTION_ANTICIPATED;
reg decode_REGFILE_WRITE_VALID;
wire decode_LEGAL_INSTRUCTION;
wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_1;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_1;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_1;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_1;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_1;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_1;
reg [31:0] _zz_decode_RS2_2;
wire writeBack_MEMORY_WR;
wire [31:0] writeBack_MEMORY_STORE_DATA_RF;
wire [31:0] writeBack_REGFILE_WRITE_DATA;
wire writeBack_MEMORY_ENABLE;
wire [31:0] memory_REGFILE_WRITE_DATA;
wire memory_MEMORY_ENABLE;
wire execute_MEMORY_FORCE_CONSTISTENCY;
wire execute_MEMORY_MANAGMENT;
(* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ;
wire execute_MEMORY_WR;
wire [31:0] execute_SRC_ADD;
wire execute_MEMORY_ENABLE;
wire [31:0] execute_INSTRUCTION;
wire decode_MEMORY_ENABLE;
wire decode_FLUSH_ALL;
reg IBusCachedPlugin_rsp_issueDetected_4;
reg IBusCachedPlugin_rsp_issueDetected_3;
reg IBusCachedPlugin_rsp_issueDetected_2;
reg IBusCachedPlugin_rsp_issueDetected_1;
wire `BranchCtrlEnum_binary_sequential_type decode_BRANCH_CTRL;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_1;
wire [31:0] decode_INSTRUCTION;
reg [31:0] _zz_execute_to_memory_FORMAL_PC_NEXT;
reg [31:0] _zz_decode_to_execute_FORMAL_PC_NEXT;
wire [31:0] decode_PC;
wire [31:0] writeBack_PC;
wire [31:0] writeBack_INSTRUCTION;
reg decode_arbitration_haltItself;
reg decode_arbitration_haltByOther;
reg decode_arbitration_removeIt;
wire decode_arbitration_flushIt;
reg decode_arbitration_flushNext;
wire decode_arbitration_isValid;
wire decode_arbitration_isStuck;
wire decode_arbitration_isStuckByOthers;
wire decode_arbitration_isFlushed;
wire decode_arbitration_isMoving;
wire decode_arbitration_isFiring;
reg execute_arbitration_haltItself;
reg execute_arbitration_haltByOther;
reg execute_arbitration_removeIt;
wire execute_arbitration_flushIt;
reg execute_arbitration_flushNext;
reg execute_arbitration_isValid;
wire execute_arbitration_isStuck;
wire execute_arbitration_isStuckByOthers;
wire execute_arbitration_isFlushed;
wire execute_arbitration_isMoving;
wire execute_arbitration_isFiring;
reg memory_arbitration_haltItself;
wire memory_arbitration_haltByOther;
reg memory_arbitration_removeIt;
wire memory_arbitration_flushIt;
wire memory_arbitration_flushNext;
reg memory_arbitration_isValid;
wire memory_arbitration_isStuck;
wire memory_arbitration_isStuckByOthers;
wire memory_arbitration_isFlushed;
wire memory_arbitration_isMoving;
wire memory_arbitration_isFiring;
reg writeBack_arbitration_haltItself;
wire writeBack_arbitration_haltByOther;
reg writeBack_arbitration_removeIt;
reg writeBack_arbitration_flushIt;
reg writeBack_arbitration_flushNext;
reg writeBack_arbitration_isValid;
wire writeBack_arbitration_isStuck;
wire writeBack_arbitration_isStuckByOthers;
wire writeBack_arbitration_isFlushed;
wire writeBack_arbitration_isMoving;
wire writeBack_arbitration_isFiring;
wire [31:0] lastStageInstruction /* verilator public */ ;
wire [31:0] lastStagePc /* verilator public */ ;
wire lastStageIsValid /* verilator public */ ;
wire lastStageIsFiring /* verilator public */ ;
reg IBusCachedPlugin_fetcherHalt;
reg IBusCachedPlugin_incomingInstruction;
wire IBusCachedPlugin_predictionJumpInterface_valid;
(* keep , syn_keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ;
reg IBusCachedPlugin_decodePrediction_cmd_hadBranch;
wire IBusCachedPlugin_decodePrediction_rsp_wasWrong;
wire IBusCachedPlugin_pcValids_0;
wire IBusCachedPlugin_pcValids_1;
wire IBusCachedPlugin_pcValids_2;
wire IBusCachedPlugin_pcValids_3;
reg IBusCachedPlugin_decodeExceptionPort_valid;
reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code;
wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr;
wire IBusCachedPlugin_mmuBus_cmd_0_isValid;
wire IBusCachedPlugin_mmuBus_cmd_0_isStuck;
wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress;
wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation;
wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress;
wire IBusCachedPlugin_mmuBus_rsp_isIoAccess;
wire IBusCachedPlugin_mmuBus_rsp_isPaging;
wire IBusCachedPlugin_mmuBus_rsp_allowRead;
wire IBusCachedPlugin_mmuBus_rsp_allowWrite;
wire IBusCachedPlugin_mmuBus_rsp_allowExecute;
wire IBusCachedPlugin_mmuBus_rsp_exception;
wire IBusCachedPlugin_mmuBus_rsp_refilling;
wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation;
wire IBusCachedPlugin_mmuBus_end;
wire IBusCachedPlugin_mmuBus_busy;
wire dBus_cmd_valid;
wire dBus_cmd_ready;
wire dBus_cmd_payload_wr;
wire dBus_cmd_payload_uncached;
wire [31:0] dBus_cmd_payload_address;
wire [31:0] dBus_cmd_payload_data;
wire [3:0] dBus_cmd_payload_mask;
wire [2:0] dBus_cmd_payload_size;
wire dBus_cmd_payload_last;
wire dBus_rsp_valid;
wire dBus_rsp_payload_last;
wire [31:0] dBus_rsp_payload_data;
wire dBus_rsp_payload_error;
wire DBusCachedPlugin_mmuBus_cmd_0_isValid;
wire DBusCachedPlugin_mmuBus_cmd_0_isStuck;
wire [31:0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress;
wire DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation;
wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress;
wire DBusCachedPlugin_mmuBus_rsp_isIoAccess;
wire DBusCachedPlugin_mmuBus_rsp_isPaging;
wire DBusCachedPlugin_mmuBus_rsp_allowRead;
wire DBusCachedPlugin_mmuBus_rsp_allowWrite;
wire DBusCachedPlugin_mmuBus_rsp_allowExecute;
wire DBusCachedPlugin_mmuBus_rsp_exception;
wire DBusCachedPlugin_mmuBus_rsp_refilling;
wire DBusCachedPlugin_mmuBus_rsp_bypassTranslation;
wire DBusCachedPlugin_mmuBus_end;
wire DBusCachedPlugin_mmuBus_busy;
reg DBusCachedPlugin_redoBranch_valid;
wire [31:0] DBusCachedPlugin_redoBranch_payload;
reg DBusCachedPlugin_exceptionBus_valid;
reg [3:0] DBusCachedPlugin_exceptionBus_payload_code;
wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr;
wire decodeExceptionPort_valid;
wire [3:0] decodeExceptionPort_payload_code;
wire [31:0] decodeExceptionPort_payload_badAddr;
wire BranchPlugin_jumpInterface_valid;
wire [31:0] BranchPlugin_jumpInterface_payload;
reg BranchPlugin_branchExceptionPort_valid;
wire [3:0] BranchPlugin_branchExceptionPort_payload_code;
wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr;
wire [31:0] CsrPlugin_csrMapping_readDataSignal;
wire [31:0] CsrPlugin_csrMapping_readDataInit;
wire [31:0] CsrPlugin_csrMapping_writeDataSignal;
wire CsrPlugin_csrMapping_allowCsrSignal;
wire CsrPlugin_csrMapping_hazardFree;
reg CsrPlugin_inWfi /* verilator public */ ;
wire CsrPlugin_thirdPartyWake;
reg CsrPlugin_jumpInterface_valid;
reg [31:0] CsrPlugin_jumpInterface_payload;
wire CsrPlugin_exceptionPendings_0;
wire CsrPlugin_exceptionPendings_1;
wire CsrPlugin_exceptionPendings_2;
wire CsrPlugin_exceptionPendings_3;
wire externalInterrupt;
wire contextSwitching;
reg [1:0] CsrPlugin_privilege;
wire CsrPlugin_forceMachineWire;
reg CsrPlugin_selfException_valid;
reg [3:0] CsrPlugin_selfException_payload_code;
wire [31:0] CsrPlugin_selfException_payload_badAddr;
wire CsrPlugin_allowInterrupts;
wire CsrPlugin_allowException;
wire CsrPlugin_allowEbreakException;
wire IBusCachedPlugin_externalFlush;
wire IBusCachedPlugin_jump_pcLoad_valid;
wire [31:0] IBusCachedPlugin_jump_pcLoad_payload;
wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload;
wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_1;
wire _zz_IBusCachedPlugin_jump_pcLoad_payload_2;
wire _zz_IBusCachedPlugin_jump_pcLoad_payload_3;
wire _zz_IBusCachedPlugin_jump_pcLoad_payload_4;
wire IBusCachedPlugin_fetchPc_output_valid;
wire IBusCachedPlugin_fetchPc_output_ready;
wire [31:0] IBusCachedPlugin_fetchPc_output_payload;
reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ;
reg IBusCachedPlugin_fetchPc_correction;
reg IBusCachedPlugin_fetchPc_correctionReg;
wire IBusCachedPlugin_fetchPc_output_fire;
wire IBusCachedPlugin_fetchPc_corrected;
reg IBusCachedPlugin_fetchPc_pcRegPropagate;
reg IBusCachedPlugin_fetchPc_booted;
reg IBusCachedPlugin_fetchPc_inc;
wire when_Fetcher_l131;
wire IBusCachedPlugin_fetchPc_output_fire_1;
wire when_Fetcher_l131_1;
reg [31:0] IBusCachedPlugin_fetchPc_pc;
wire IBusCachedPlugin_fetchPc_redo_valid;
wire [31:0] IBusCachedPlugin_fetchPc_redo_payload;
reg IBusCachedPlugin_fetchPc_flushed;
wire when_Fetcher_l158;
reg IBusCachedPlugin_iBusRsp_redoFetch;
wire IBusCachedPlugin_iBusRsp_stages_0_input_valid;
wire IBusCachedPlugin_iBusRsp_stages_0_input_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload;
wire IBusCachedPlugin_iBusRsp_stages_0_output_valid;
wire IBusCachedPlugin_iBusRsp_stages_0_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload;
reg IBusCachedPlugin_iBusRsp_stages_0_halt;
wire IBusCachedPlugin_iBusRsp_stages_1_input_valid;
wire IBusCachedPlugin_iBusRsp_stages_1_input_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload;
wire IBusCachedPlugin_iBusRsp_stages_1_output_valid;
wire IBusCachedPlugin_iBusRsp_stages_1_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload;
reg IBusCachedPlugin_iBusRsp_stages_1_halt;
wire IBusCachedPlugin_iBusRsp_stages_2_input_valid;
wire IBusCachedPlugin_iBusRsp_stages_2_input_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload;
wire IBusCachedPlugin_iBusRsp_stages_2_output_valid;
wire IBusCachedPlugin_iBusRsp_stages_2_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload;
reg IBusCachedPlugin_iBusRsp_stages_2_halt;
wire _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready;
wire _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready;
wire _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready;
wire IBusCachedPlugin_iBusRsp_flush;
wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready;
wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1;
reg _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2;
wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid;
wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload;
reg _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid;
reg [31:0] _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload;
reg IBusCachedPlugin_iBusRsp_readyForError;
wire IBusCachedPlugin_iBusRsp_output_valid;
wire IBusCachedPlugin_iBusRsp_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc;
wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error;
wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst;
wire IBusCachedPlugin_iBusRsp_output_payload_isRvc;
wire when_Fetcher_l240;
wire when_Fetcher_l320;
reg IBusCachedPlugin_injector_nextPcCalc_valids_0;
wire when_Fetcher_l329;
reg IBusCachedPlugin_injector_nextPcCalc_valids_1;
wire when_Fetcher_l329_1;
reg IBusCachedPlugin_injector_nextPcCalc_valids_2;
wire when_Fetcher_l329_2;
reg IBusCachedPlugin_injector_nextPcCalc_valids_3;
wire when_Fetcher_l329_3;
reg IBusCachedPlugin_injector_nextPcCalc_valids_4;
wire when_Fetcher_l329_4;
wire _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
reg [18:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1;
wire _zz_2;
reg [10:0] _zz_3;
wire _zz_4;
reg [18:0] _zz_5;
reg _zz_6;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload;
reg [10:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_1;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
reg [18:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_3;
wire iBus_cmd_valid;
wire iBus_cmd_ready;
reg [31:0] iBus_cmd_payload_address;
wire [2:0] iBus_cmd_payload_size;
wire iBus_rsp_valid;
wire [31:0] iBus_rsp_payload_data;
wire iBus_rsp_payload_error;
wire [31:0] _zz_IBusCachedPlugin_rspCounter;
reg [31:0] IBusCachedPlugin_rspCounter;
wire IBusCachedPlugin_s0_tightlyCoupledHit;
reg IBusCachedPlugin_s1_tightlyCoupledHit;
reg IBusCachedPlugin_s2_tightlyCoupledHit;
wire IBusCachedPlugin_rsp_iBusRspOutputHalt;
wire IBusCachedPlugin_rsp_issueDetected;
reg IBusCachedPlugin_rsp_redoFetch;
wire when_IBusCachedPlugin_l239;
wire when_IBusCachedPlugin_l244;
wire when_IBusCachedPlugin_l250;
wire when_IBusCachedPlugin_l256;
wire when_IBusCachedPlugin_l267;
wire dataCache_1_io_mem_cmd_s2mPipe_valid;
reg dataCache_1_io_mem_cmd_s2mPipe_ready;
wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr;
wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached;
wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address;
wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data;
wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask;
wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_size;
wire dataCache_1_io_mem_cmd_s2mPipe_payload_last;
reg dataCache_1_io_mem_cmd_rValid;
reg dataCache_1_io_mem_cmd_rData_wr;
reg dataCache_1_io_mem_cmd_rData_uncached;
reg [31:0] dataCache_1_io_mem_cmd_rData_address;
reg [31:0] dataCache_1_io_mem_cmd_rData_data;
reg [3:0] dataCache_1_io_mem_cmd_rData_mask;
reg [2:0] dataCache_1_io_mem_cmd_rData_size;
reg dataCache_1_io_mem_cmd_rData_last;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached;
wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address;
wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data;
wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask;
wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last;
reg dataCache_1_io_mem_cmd_s2mPipe_rValid;
reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr;
reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached;
reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address;
reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data;
reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask;
reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_size;
reg dataCache_1_io_mem_cmd_s2mPipe_rData_last;
wire when_Stream_l342;
wire [31:0] _zz_DBusCachedPlugin_rspCounter;
reg [31:0] DBusCachedPlugin_rspCounter;
wire when_DBusCachedPlugin_l303;
wire [1:0] execute_DBusCachedPlugin_size;
reg [31:0] _zz_execute_MEMORY_STORE_DATA_RF;
wire dataCache_1_io_cpu_flush_isStall;
wire when_DBusCachedPlugin_l343;
wire when_DBusCachedPlugin_l359;
wire when_DBusCachedPlugin_l386;
wire when_DBusCachedPlugin_l438;
wire when_DBusCachedPlugin_l458;
wire [7:0] writeBack_DBusCachedPlugin_rspSplits_0;
wire [7:0] writeBack_DBusCachedPlugin_rspSplits_1;
wire [7:0] writeBack_DBusCachedPlugin_rspSplits_2;
wire [7:0] writeBack_DBusCachedPlugin_rspSplits_3;
reg [31:0] writeBack_DBusCachedPlugin_rspShifted;
wire [31:0] writeBack_DBusCachedPlugin_rspRf;
wire [1:0] switch_Misc_l200;
wire _zz_writeBack_DBusCachedPlugin_rspFormated;
reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_1;
wire _zz_writeBack_DBusCachedPlugin_rspFormated_2;
reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_3;
reg [31:0] writeBack_DBusCachedPlugin_rspFormated;
wire when_DBusCachedPlugin_l484;
wire [33:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_2;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_2;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_2;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_2;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_2;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_2;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_2;
wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8;
wire when_RegFilePlugin_l63;
wire [4:0] decode_RegFilePlugin_regFileReadAddress1;
wire [4:0] decode_RegFilePlugin_regFileReadAddress2;
wire [31:0] decode_RegFilePlugin_rs1Data;
wire [31:0] decode_RegFilePlugin_rs2Data;
reg lastStageRegFileWrite_valid /* verilator public */ ;
reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ;
reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ;
reg _zz_7;
reg [31:0] execute_IntAluPlugin_bitwise;
reg [31:0] _zz_execute_REGFILE_WRITE_DATA;
reg [31:0] _zz_execute_SRC1;
wire _zz_execute_SRC2_1;
reg [19:0] _zz_execute_SRC2_2;
wire _zz_execute_SRC2_3;
reg [19:0] _zz_execute_SRC2_4;
reg [31:0] _zz_execute_SRC2_5;
reg [31:0] execute_SrcPlugin_addSub;
wire execute_SrcPlugin_less;
wire [4:0] execute_FullBarrelShifterPlugin_amplitude;
reg [31:0] _zz_execute_FullBarrelShifterPlugin_reversed;
wire [31:0] execute_FullBarrelShifterPlugin_reversed;
reg [31:0] _zz_decode_RS2_3;
reg HazardSimplePlugin_src0Hazard;
reg HazardSimplePlugin_src1Hazard;
wire HazardSimplePlugin_writeBackWrites_valid;
wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address;
wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data;
reg HazardSimplePlugin_writeBackBuffer_valid;
reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address;
reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data;
wire HazardSimplePlugin_addr0Match;
wire HazardSimplePlugin_addr1Match;
wire when_HazardSimplePlugin_l47;
wire when_HazardSimplePlugin_l48;
wire when_HazardSimplePlugin_l51;
wire when_HazardSimplePlugin_l45;
wire when_HazardSimplePlugin_l57;
wire when_HazardSimplePlugin_l58;
wire when_HazardSimplePlugin_l48_1;
wire when_HazardSimplePlugin_l51_1;
wire when_HazardSimplePlugin_l45_1;
wire when_HazardSimplePlugin_l57_1;
wire when_HazardSimplePlugin_l58_1;
wire when_HazardSimplePlugin_l48_2;
wire when_HazardSimplePlugin_l51_2;
wire when_HazardSimplePlugin_l45_2;
wire when_HazardSimplePlugin_l57_2;
wire when_HazardSimplePlugin_l58_2;
wire when_HazardSimplePlugin_l105;
wire when_HazardSimplePlugin_l108;
wire when_HazardSimplePlugin_l113;
wire execute_BranchPlugin_eq;
wire [2:0] switch_Misc_l200_1;
reg _zz_execute_BRANCH_COND_RESULT;
reg _zz_execute_BRANCH_COND_RESULT_1;
wire _zz_execute_BranchPlugin_missAlignedTarget;
reg [19:0] _zz_execute_BranchPlugin_missAlignedTarget_1;
wire _zz_execute_BranchPlugin_missAlignedTarget_2;
reg [10:0] _zz_execute_BranchPlugin_missAlignedTarget_3;
wire _zz_execute_BranchPlugin_missAlignedTarget_4;
reg [18:0] _zz_execute_BranchPlugin_missAlignedTarget_5;
reg _zz_execute_BranchPlugin_missAlignedTarget_6;
wire execute_BranchPlugin_missAlignedTarget;
reg [31:0] execute_BranchPlugin_branch_src1;
reg [31:0] execute_BranchPlugin_branch_src2;
wire _zz_execute_BranchPlugin_branch_src2;
reg [19:0] _zz_execute_BranchPlugin_branch_src2_1;
wire _zz_execute_BranchPlugin_branch_src2_2;
reg [10:0] _zz_execute_BranchPlugin_branch_src2_3;
wire _zz_execute_BranchPlugin_branch_src2_4;
reg [18:0] _zz_execute_BranchPlugin_branch_src2_5;
wire [31:0] execute_BranchPlugin_branchAdder;
wire when_BranchPlugin_l296;
reg [1:0] CsrPlugin_misa_base;
reg [25:0] CsrPlugin_misa_extensions;
reg [1:0] CsrPlugin_mtvec_mode;
reg [29:0] CsrPlugin_mtvec_base;
reg [31:0] CsrPlugin_mepc;
reg CsrPlugin_mstatus_MIE;
reg CsrPlugin_mstatus_MPIE;
reg [1:0] CsrPlugin_mstatus_MPP;
reg CsrPlugin_mip_MEIP;
reg CsrPlugin_mip_MTIP;
reg CsrPlugin_mip_MSIP;
reg CsrPlugin_mie_MEIE;
reg CsrPlugin_mie_MTIE;
reg CsrPlugin_mie_MSIE;
reg [31:0] CsrPlugin_mscratch;
reg CsrPlugin_mcause_interrupt;
reg [3:0] CsrPlugin_mcause_exceptionCode;
reg [31:0] CsrPlugin_mtval;
reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000;
reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000;
wire _zz_when_CsrPlugin_l952;
wire _zz_when_CsrPlugin_l952_1;
wire _zz_when_CsrPlugin_l952_2;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code;
reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr;
wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped;
wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege;
wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code;
wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1;
wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2;
wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3;
wire when_CsrPlugin_l909;
wire when_CsrPlugin_l909_1;
wire when_CsrPlugin_l909_2;
wire when_CsrPlugin_l909_3;
wire when_CsrPlugin_l922;
reg CsrPlugin_interrupt_valid;
reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ;
reg [1:0] CsrPlugin_interrupt_targetPrivilege;
wire when_CsrPlugin_l946;
wire when_CsrPlugin_l952;
wire when_CsrPlugin_l952_1;
wire when_CsrPlugin_l952_2;
wire CsrPlugin_exception;
reg CsrPlugin_lastStageWasWfi;
reg CsrPlugin_pipelineLiberator_pcValids_0;
reg CsrPlugin_pipelineLiberator_pcValids_1;
reg CsrPlugin_pipelineLiberator_pcValids_2;
wire CsrPlugin_pipelineLiberator_active;
wire when_CsrPlugin_l980;
wire when_CsrPlugin_l980_1;
wire when_CsrPlugin_l980_2;
wire when_CsrPlugin_l985;
reg CsrPlugin_pipelineLiberator_done;
wire when_CsrPlugin_l991;
wire CsrPlugin_interruptJump /* verilator public */ ;
reg CsrPlugin_hadException /* verilator public */ ;
reg [1:0] CsrPlugin_targetPrivilege;
reg [3:0] CsrPlugin_trapCause;
reg [1:0] CsrPlugin_xtvec_mode;
reg [29:0] CsrPlugin_xtvec_base;
wire when_CsrPlugin_l1019;
wire when_CsrPlugin_l1064;
wire [1:0] switch_CsrPlugin_l1068;
reg execute_CsrPlugin_wfiWake;
wire when_CsrPlugin_l1108;
wire when_CsrPlugin_l1110;
wire when_CsrPlugin_l1116;
wire execute_CsrPlugin_blockedBySideEffects;
reg execute_CsrPlugin_illegalAccess;
reg execute_CsrPlugin_illegalInstruction;
wire when_CsrPlugin_l1129;
wire when_CsrPlugin_l1136;
wire when_CsrPlugin_l1137;
wire when_CsrPlugin_l1144;
reg execute_CsrPlugin_writeInstruction;
reg execute_CsrPlugin_readInstruction;
wire execute_CsrPlugin_writeEnable;
wire execute_CsrPlugin_readEnable;
wire [31:0] execute_CsrPlugin_readToWriteData;
wire switch_Misc_l200_2;
reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal;
wire when_CsrPlugin_l1176;
wire when_CsrPlugin_l1180;
wire [11:0] execute_CsrPlugin_csrAddress;
reg execute_MulPlugin_aSigned;
reg execute_MulPlugin_bSigned;
wire [31:0] execute_MulPlugin_a;
wire [31:0] execute_MulPlugin_b;
wire [1:0] switch_MulPlugin_l87;
wire [15:0] execute_MulPlugin_aULow;
wire [15:0] execute_MulPlugin_bULow;
wire [16:0] execute_MulPlugin_aSLow;
wire [16:0] execute_MulPlugin_bSLow;
wire [16:0] execute_MulPlugin_aHigh;
wire [16:0] execute_MulPlugin_bHigh;
wire [65:0] writeBack_MulPlugin_result;
wire when_MulPlugin_l147;
wire [1:0] switch_MulPlugin_l148;
reg [32:0] memory_DivPlugin_rs1;
reg [31:0] memory_DivPlugin_rs2;
reg [64:0] memory_DivPlugin_accumulator;
wire memory_DivPlugin_frontendOk;
reg memory_DivPlugin_div_needRevert;
reg memory_DivPlugin_div_counter_willIncrement;
reg memory_DivPlugin_div_counter_willClear;
reg [5:0] memory_DivPlugin_div_counter_valueNext;
reg [5:0] memory_DivPlugin_div_counter_value;
wire memory_DivPlugin_div_counter_willOverflowIfInc;
wire memory_DivPlugin_div_counter_willOverflow;
reg memory_DivPlugin_div_done;
wire when_MulDivIterativePlugin_l126;
wire when_MulDivIterativePlugin_l126_1;
reg [31:0] memory_DivPlugin_div_result;
wire when_MulDivIterativePlugin_l128;
wire when_MulDivIterativePlugin_l129;
wire when_MulDivIterativePlugin_l132;
wire [31:0] _zz_memory_DivPlugin_div_stage_0_remainderShifted;
wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted;
wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator;
wire [31:0] memory_DivPlugin_div_stage_0_outRemainder;
wire [31:0] memory_DivPlugin_div_stage_0_outNumerator;
wire when_MulDivIterativePlugin_l151;
wire [31:0] _zz_memory_DivPlugin_div_result;
wire when_MulDivIterativePlugin_l162;
wire _zz_memory_DivPlugin_rs2;
wire _zz_memory_DivPlugin_rs1;
reg [32:0] _zz_memory_DivPlugin_rs1_1;
reg [31:0] externalInterruptArray_regNext;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit;
wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1;
wire execute_CfuPlugin_schedule;
reg execute_CfuPlugin_hold;
reg execute_CfuPlugin_fired;
wire CfuPlugin_bus_cmd_fire;
wire when_CfuPlugin_l171;
wire when_CfuPlugin_l175;
wire [9:0] execute_CfuPlugin_functionsIds_0;
wire _zz_CfuPlugin_bus_cmd_payload_inputs_1;
reg [23:0] _zz_CfuPlugin_bus_cmd_payload_inputs_1_1;
reg [31:0] _zz_CfuPlugin_bus_cmd_payload_inputs_1_2;
wire CfuPlugin_bus_rsp_rsp_valid;
reg CfuPlugin_bus_rsp_rsp_ready;
wire [31:0] CfuPlugin_bus_rsp_rsp_payload_outputs_0;
reg CfuPlugin_bus_rsp_rValid;
reg [31:0] CfuPlugin_bus_rsp_rData_outputs_0;
wire when_CfuPlugin_l208;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2;
reg [31:0] _zz_when_GenCoreDefault_l367;
wire when_GenCoreDefault_l367;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3;
reg [31:0] _zz_when_GenCoreDefault_l367_1;
wire when_GenCoreDefault_l367_1;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4;
reg [31:0] _zz_when_GenCoreDefault_l367_2;
wire when_GenCoreDefault_l367_2;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5;
reg [31:0] _zz_when_GenCoreDefault_l367_3;
wire when_GenCoreDefault_l367_3;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6;
reg [31:0] _zz_when_GenCoreDefault_l367_4;
wire when_GenCoreDefault_l367_4;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7;
reg [31:0] _zz_when_GenCoreDefault_l367_5;
wire when_GenCoreDefault_l367_5;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_8;
reg [31:0] _zz_when_GenCoreDefault_l367_6;
wire when_GenCoreDefault_l367_6;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_9;
reg [31:0] _zz_when_GenCoreDefault_l367_7;
wire when_GenCoreDefault_l367_7;
wire when_Pipeline_l124;
reg [31:0] decode_to_execute_PC;
wire when_Pipeline_l124_1;
reg [31:0] execute_to_memory_PC;
wire when_Pipeline_l124_2;
reg [31:0] memory_to_writeBack_PC;
wire when_Pipeline_l124_3;
reg [31:0] decode_to_execute_INSTRUCTION;
wire when_Pipeline_l124_4;
reg [31:0] execute_to_memory_INSTRUCTION;
wire when_Pipeline_l124_5;
reg [31:0] memory_to_writeBack_INSTRUCTION;
wire when_Pipeline_l124_6;
reg [31:0] decode_to_execute_FORMAL_PC_NEXT;
wire when_Pipeline_l124_7;
reg [31:0] execute_to_memory_FORMAL_PC_NEXT;
wire when_Pipeline_l124_8;
reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT;
wire when_Pipeline_l124_9;
reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY;
wire when_Pipeline_l124_10;
reg `Src1CtrlEnum_binary_sequential_type decode_to_execute_SRC1_CTRL;
wire when_Pipeline_l124_11;
reg decode_to_execute_SRC_USE_SUB_LESS;
wire when_Pipeline_l124_12;
reg decode_to_execute_MEMORY_ENABLE;
wire when_Pipeline_l124_13;
reg execute_to_memory_MEMORY_ENABLE;
wire when_Pipeline_l124_14;
reg memory_to_writeBack_MEMORY_ENABLE;
wire when_Pipeline_l124_15;
reg `AluCtrlEnum_binary_sequential_type decode_to_execute_ALU_CTRL;
wire when_Pipeline_l124_16;
reg `Src2CtrlEnum_binary_sequential_type decode_to_execute_SRC2_CTRL;
wire when_Pipeline_l124_17;
reg decode_to_execute_REGFILE_WRITE_VALID;
wire when_Pipeline_l124_18;
reg execute_to_memory_REGFILE_WRITE_VALID;
wire when_Pipeline_l124_19;
reg memory_to_writeBack_REGFILE_WRITE_VALID;
wire when_Pipeline_l124_20;
reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE;
wire when_Pipeline_l124_21;
reg decode_to_execute_BYPASSABLE_MEMORY_STAGE;
wire when_Pipeline_l124_22;
reg execute_to_memory_BYPASSABLE_MEMORY_STAGE;
wire when_Pipeline_l124_23;
reg decode_to_execute_MEMORY_WR;
wire when_Pipeline_l124_24;
reg execute_to_memory_MEMORY_WR;
wire when_Pipeline_l124_25;
reg memory_to_writeBack_MEMORY_WR;
wire when_Pipeline_l124_26;
reg decode_to_execute_MEMORY_MANAGMENT;
wire when_Pipeline_l124_27;
reg decode_to_execute_SRC_LESS_UNSIGNED;
wire when_Pipeline_l124_28;
reg `AluBitwiseCtrlEnum_binary_sequential_type decode_to_execute_ALU_BITWISE_CTRL;
wire when_Pipeline_l124_29;
reg `ShiftCtrlEnum_binary_sequential_type decode_to_execute_SHIFT_CTRL;
wire when_Pipeline_l124_30;
reg `ShiftCtrlEnum_binary_sequential_type execute_to_memory_SHIFT_CTRL;
wire when_Pipeline_l124_31;
reg `BranchCtrlEnum_binary_sequential_type decode_to_execute_BRANCH_CTRL;
wire when_Pipeline_l124_32;
reg decode_to_execute_IS_CSR;
wire when_Pipeline_l124_33;
reg `EnvCtrlEnum_binary_sequential_type decode_to_execute_ENV_CTRL;
wire when_Pipeline_l124_34;
reg `EnvCtrlEnum_binary_sequential_type execute_to_memory_ENV_CTRL;
wire when_Pipeline_l124_35;
reg `EnvCtrlEnum_binary_sequential_type memory_to_writeBack_ENV_CTRL;
wire when_Pipeline_l124_36;
reg decode_to_execute_IS_MUL;
wire when_Pipeline_l124_37;
reg execute_to_memory_IS_MUL;
wire when_Pipeline_l124_38;
reg memory_to_writeBack_IS_MUL;
wire when_Pipeline_l124_39;
reg decode_to_execute_IS_DIV;
wire when_Pipeline_l124_40;
reg execute_to_memory_IS_DIV;
wire when_Pipeline_l124_41;
reg decode_to_execute_IS_RS1_SIGNED;
wire when_Pipeline_l124_42;
reg decode_to_execute_IS_RS2_SIGNED;
wire when_Pipeline_l124_43;
reg decode_to_execute_CfuPlugin_CFU_ENABLE;
wire when_Pipeline_l124_44;
reg `Input2Kind_binary_sequential_type decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND;
wire when_Pipeline_l124_45;
reg [31:0] decode_to_execute_RS1;
wire when_Pipeline_l124_46;
reg [31:0] decode_to_execute_RS2;
wire when_Pipeline_l124_47;
reg decode_to_execute_SRC2_FORCE_ZERO;
wire when_Pipeline_l124_48;
reg decode_to_execute_PREDICTION_HAD_BRANCHED2;
wire when_Pipeline_l124_49;
reg decode_to_execute_CSR_WRITE_OPCODE;
wire when_Pipeline_l124_50;
reg decode_to_execute_CSR_READ_OPCODE;
wire when_Pipeline_l124_51;
reg [31:0] execute_to_memory_MEMORY_STORE_DATA_RF;
wire when_Pipeline_l124_52;
reg [31:0] memory_to_writeBack_MEMORY_STORE_DATA_RF;
wire when_Pipeline_l124_53;
reg [31:0] execute_to_memory_REGFILE_WRITE_DATA;
wire when_Pipeline_l124_54;
reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA;
wire when_Pipeline_l124_55;
reg [31:0] execute_to_memory_SHIFT_RIGHT;
wire when_Pipeline_l124_56;
reg [31:0] execute_to_memory_MUL_LL;
wire when_Pipeline_l124_57;
reg [33:0] execute_to_memory_MUL_LH;
wire when_Pipeline_l124_58;
reg [33:0] execute_to_memory_MUL_HL;
wire when_Pipeline_l124_59;
reg [33:0] execute_to_memory_MUL_HH;
wire when_Pipeline_l124_60;
reg [33:0] memory_to_writeBack_MUL_HH;
wire when_Pipeline_l124_61;
reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT;
wire when_Pipeline_l124_62;
reg memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT;
wire when_Pipeline_l124_63;
reg [51:0] memory_to_writeBack_MUL_LOW;
wire when_Pipeline_l151;
wire when_Pipeline_l154;
wire when_Pipeline_l151_1;
wire when_Pipeline_l154_1;
wire when_Pipeline_l151_2;
wire when_Pipeline_l154_2;
wire when_CsrPlugin_l1264;
reg execute_CsrPlugin_csr_3264;
wire when_CsrPlugin_l1264_1;
reg execute_CsrPlugin_csr_3857;
wire when_CsrPlugin_l1264_2;
reg execute_CsrPlugin_csr_3858;
wire when_CsrPlugin_l1264_3;
reg execute_CsrPlugin_csr_3859;
wire when_CsrPlugin_l1264_4;
reg execute_CsrPlugin_csr_3860;
wire when_CsrPlugin_l1264_5;
reg execute_CsrPlugin_csr_769;
wire when_CsrPlugin_l1264_6;
reg execute_CsrPlugin_csr_768;
wire when_CsrPlugin_l1264_7;
reg execute_CsrPlugin_csr_836;
wire when_CsrPlugin_l1264_8;
reg execute_CsrPlugin_csr_772;
wire when_CsrPlugin_l1264_9;
reg execute_CsrPlugin_csr_773;
wire when_CsrPlugin_l1264_10;
reg execute_CsrPlugin_csr_833;
wire when_CsrPlugin_l1264_11;
reg execute_CsrPlugin_csr_832;
wire when_CsrPlugin_l1264_12;
reg execute_CsrPlugin_csr_834;
wire when_CsrPlugin_l1264_13;
reg execute_CsrPlugin_csr_835;
wire when_CsrPlugin_l1264_14;
reg execute_CsrPlugin_csr_2816;
wire when_CsrPlugin_l1264_15;
reg execute_CsrPlugin_csr_2944;
wire when_CsrPlugin_l1264_16;
reg execute_CsrPlugin_csr_2818;
wire when_CsrPlugin_l1264_17;
reg execute_CsrPlugin_csr_2946;
wire when_CsrPlugin_l1264_18;
reg execute_CsrPlugin_csr_3072;
wire when_CsrPlugin_l1264_19;
reg execute_CsrPlugin_csr_3200;
wire when_CsrPlugin_l1264_20;
reg execute_CsrPlugin_csr_3074;
wire when_CsrPlugin_l1264_21;
reg execute_CsrPlugin_csr_3202;
wire when_CsrPlugin_l1264_22;
reg execute_CsrPlugin_csr_3008;
wire when_CsrPlugin_l1264_23;
reg execute_CsrPlugin_csr_4032;
wire when_CsrPlugin_l1264_24;
reg execute_CsrPlugin_csr_2820;
wire when_CsrPlugin_l1264_25;
reg execute_CsrPlugin_csr_2821;
wire when_CsrPlugin_l1264_26;
reg execute_CsrPlugin_csr_2822;
wire when_CsrPlugin_l1264_27;
reg execute_CsrPlugin_csr_2823;
wire when_CsrPlugin_l1264_28;
reg execute_CsrPlugin_csr_2824;
wire when_CsrPlugin_l1264_29;
reg execute_CsrPlugin_csr_2825;
wire when_CsrPlugin_l1264_30;
reg execute_CsrPlugin_csr_2826;
wire when_CsrPlugin_l1264_31;
reg execute_CsrPlugin_csr_2827;
wire when_CsrPlugin_l1264_32;
reg execute_CsrPlugin_csr_2828;
wire when_CsrPlugin_l1264_33;
reg execute_CsrPlugin_csr_2829;
wire when_CsrPlugin_l1264_34;
reg execute_CsrPlugin_csr_2830;
wire when_CsrPlugin_l1264_35;
reg execute_CsrPlugin_csr_2831;
wire when_CsrPlugin_l1264_36;
reg execute_CsrPlugin_csr_2832;
wire when_CsrPlugin_l1264_37;
reg execute_CsrPlugin_csr_2833;
wire when_CsrPlugin_l1264_38;
reg execute_CsrPlugin_csr_2834;
wire when_CsrPlugin_l1264_39;
reg execute_CsrPlugin_csr_2835;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_10;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_11;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_12;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_13;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_14;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_15;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_16;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_17;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_18;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_19;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_20;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_21;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_22;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_23;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_24;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_25;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_26;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_27;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_28;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_29;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_30;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_31;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_32;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_33;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_34;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_35;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_36;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_37;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_38;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_39;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_40;
wire when_CsrPlugin_l1297;
wire when_CsrPlugin_l1302;
reg [2:0] _zz_iBusWishbone_ADR;
wire when_InstructionCache_l239;
reg _zz_iBus_rsp_valid;
reg [31:0] iBusWishbone_DAT_MISO_regNext;
reg [2:0] _zz_dBus_cmd_ready;
wire _zz_dBus_cmd_ready_1;
wire _zz_dBus_cmd_ready_2;
wire _zz_dBus_cmd_ready_3;
wire _zz_dBus_cmd_ready_4;
wire _zz_dBus_cmd_ready_5;
reg _zz_dBus_rsp_valid;
reg [31:0] dBusWishbone_DAT_MISO_regNext;
`ifndef SYNTHESIS
reg [39:0] decode_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string;
reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_string;
reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_1_string;
reg [39:0] _zz_execute_to_memory_ENV_CTRL_string;
reg [39:0] _zz_execute_to_memory_ENV_CTRL_1_string;
reg [39:0] decode_ENV_CTRL_string;
reg [39:0] _zz_decode_ENV_CTRL_string;
reg [39:0] _zz_decode_to_execute_ENV_CTRL_string;
reg [39:0] _zz_decode_to_execute_ENV_CTRL_1_string;
reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string;
reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string;
reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_string;
reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_1_string;
reg [71:0] decode_SHIFT_CTRL_string;
reg [71:0] _zz_decode_SHIFT_CTRL_string;
reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string;
reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string;
reg [39:0] decode_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string;
reg [23:0] decode_SRC2_CTRL_string;
reg [23:0] _zz_decode_SRC2_CTRL_string;
reg [23:0] _zz_decode_to_execute_SRC2_CTRL_string;
reg [23:0] _zz_decode_to_execute_SRC2_CTRL_1_string;
reg [63:0] decode_ALU_CTRL_string;
reg [63:0] _zz_decode_ALU_CTRL_string;
reg [63:0] _zz_decode_to_execute_ALU_CTRL_string;
reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string;
reg [95:0] decode_SRC1_CTRL_string;
reg [95:0] _zz_decode_SRC1_CTRL_string;
reg [95:0] _zz_decode_to_execute_SRC1_CTRL_string;
reg [95:0] _zz_decode_to_execute_SRC1_CTRL_1_string;
reg [39:0] execute_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] memory_ENV_CTRL_string;
reg [39:0] _zz_memory_ENV_CTRL_string;
reg [39:0] execute_ENV_CTRL_string;
reg [39:0] _zz_execute_ENV_CTRL_string;
reg [39:0] writeBack_ENV_CTRL_string;
reg [39:0] _zz_writeBack_ENV_CTRL_string;
reg [31:0] execute_BRANCH_CTRL_string;
reg [31:0] _zz_execute_BRANCH_CTRL_string;
reg [71:0] memory_SHIFT_CTRL_string;
reg [71:0] _zz_memory_SHIFT_CTRL_string;
reg [71:0] execute_SHIFT_CTRL_string;
reg [71:0] _zz_execute_SHIFT_CTRL_string;
reg [23:0] execute_SRC2_CTRL_string;
reg [23:0] _zz_execute_SRC2_CTRL_string;
reg [95:0] execute_SRC1_CTRL_string;
reg [95:0] _zz_execute_SRC1_CTRL_string;
reg [63:0] execute_ALU_CTRL_string;
reg [63:0] _zz_execute_ALU_CTRL_string;
reg [39:0] execute_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string;
reg [39:0] _zz_decode_ENV_CTRL_1_string;
reg [31:0] _zz_decode_BRANCH_CTRL_string;
reg [71:0] _zz_decode_SHIFT_CTRL_1_string;
reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string;
reg [23:0] _zz_decode_SRC2_CTRL_1_string;
reg [63:0] _zz_decode_ALU_CTRL_1_string;
reg [95:0] _zz_decode_SRC1_CTRL_1_string;
reg [31:0] decode_BRANCH_CTRL_string;
reg [31:0] _zz_decode_BRANCH_CTRL_1_string;
reg [95:0] _zz_decode_SRC1_CTRL_2_string;
reg [63:0] _zz_decode_ALU_CTRL_2_string;
reg [23:0] _zz_decode_SRC2_CTRL_2_string;
reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string;
reg [71:0] _zz_decode_SHIFT_CTRL_2_string;
reg [31:0] _zz_decode_BRANCH_CTRL_2_string;
reg [39:0] _zz_decode_ENV_CTRL_2_string;
reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string;
reg [95:0] decode_to_execute_SRC1_CTRL_string;
reg [63:0] decode_to_execute_ALU_CTRL_string;
reg [23:0] decode_to_execute_SRC2_CTRL_string;
reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string;
reg [71:0] decode_to_execute_SHIFT_CTRL_string;
reg [71:0] execute_to_memory_SHIFT_CTRL_string;
reg [31:0] decode_to_execute_BRANCH_CTRL_string;
reg [39:0] decode_to_execute_ENV_CTRL_string;
reg [39:0] execute_to_memory_ENV_CTRL_string;
reg [39:0] memory_to_writeBack_ENV_CTRL_string;
reg [39:0] decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string;
`endif
(* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ;
assign _zz_when = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00);
assign _zz_when_1 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00);
assign _zz_memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW_1) + $signed(_zz_memory_MUL_LOW_5));
assign _zz_memory_MUL_LOW_1 = ($signed(_zz_memory_MUL_LOW_2) + $signed(_zz_memory_MUL_LOW_3));
assign _zz_memory_MUL_LOW_2 = 52'h0;
assign _zz_memory_MUL_LOW_4 = {1'b0,memory_MUL_LL};
assign _zz_memory_MUL_LOW_3 = {{19{_zz_memory_MUL_LOW_4[32]}}, _zz_memory_MUL_LOW_4};
assign _zz_memory_MUL_LOW_6 = ({16'd0,memory_MUL_LH} <<< 16);
assign _zz_memory_MUL_LOW_5 = {{2{_zz_memory_MUL_LOW_6[49]}}, _zz_memory_MUL_LOW_6};
assign _zz_memory_MUL_LOW_8 = ({16'd0,memory_MUL_HL} <<< 16);
assign _zz_memory_MUL_LOW_7 = {{2{_zz_memory_MUL_LOW_8[49]}}, _zz_memory_MUL_LOW_8};
assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude);
assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0];
assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed};
assign _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload - 4'b0001);
assign _zz_IBusCachedPlugin_fetchPc_pc_1 = {IBusCachedPlugin_fetchPc_inc,2'b00};
assign _zz_IBusCachedPlugin_fetchPc_pc = {29'd0, _zz_IBusCachedPlugin_fetchPc_pc_1};
assign _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]};
assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2 = {{_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0};
assign _zz__zz_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]};
assign _zz__zz_4 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]};
assign _zz__zz_6 = {{_zz_3,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0};
assign _zz__zz_6_1 = {{_zz_5,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0};
assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]};
assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]};
assign _zz_DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 3'b111 : 3'b101);
assign _zz_DBusCachedPlugin_exceptionBus_payload_code_1 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100);
assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS;
assign _zz__zz_execute_SRC1 = 3'b100;
assign _zz__zz_execute_SRC1_1 = execute_INSTRUCTION[19 : 15];
assign _zz__zz_execute_SRC2_3 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]};
assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4));
assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3));
assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1;
assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2);
assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6);
assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001;
assign _zz_execute_SrcPlugin_addSub_6 = 32'h0;
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]};
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]};
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6 = {_zz_execute_BranchPlugin_missAlignedTarget_1,execute_INSTRUCTION[31 : 20]};
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1 = {{_zz_execute_BranchPlugin_missAlignedTarget_3,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0};
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2 = {{_zz_execute_BranchPlugin_missAlignedTarget_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0};
assign _zz__zz_execute_BranchPlugin_branch_src2_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]};
assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]};
assign _zz_execute_BranchPlugin_branch_src2_9 = 3'b100;
assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1));
assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code - 2'b01);
assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1));
assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 - 2'b01);
assign _zz_writeBack_MulPlugin_result = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW};
assign _zz_writeBack_MulPlugin_result_1 = ({32'd0,writeBack_MUL_HH} <<< 32);
assign _zz__zz_decode_RS2_2 = writeBack_MUL_LOW[31 : 0];
assign _zz__zz_decode_RS2_2_1 = writeBack_MulPlugin_result[63 : 32];
assign _zz_memory_DivPlugin_div_counter_valueNext_1 = memory_DivPlugin_div_counter_willIncrement;
assign _zz_memory_DivPlugin_div_counter_valueNext = {5'd0, _zz_memory_DivPlugin_div_counter_valueNext_1};
assign _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator = {1'd0, memory_DivPlugin_rs2};
assign _zz_memory_DivPlugin_div_stage_0_outRemainder = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0];
assign _zz_memory_DivPlugin_div_stage_0_outRemainder_1 = memory_DivPlugin_div_stage_0_remainderShifted[31:0];
assign _zz_memory_DivPlugin_div_stage_0_outNumerator = {_zz_memory_DivPlugin_div_stage_0_remainderShifted,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])};
assign _zz_memory_DivPlugin_div_result_1 = _zz_memory_DivPlugin_div_result_2;
assign _zz_memory_DivPlugin_div_result_2 = _zz_memory_DivPlugin_div_result_3;
assign _zz_memory_DivPlugin_div_result_3 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_memory_DivPlugin_div_result) : _zz_memory_DivPlugin_div_result)} + _zz_memory_DivPlugin_div_result_4);
assign _zz_memory_DivPlugin_div_result_5 = memory_DivPlugin_div_needRevert;
assign _zz_memory_DivPlugin_div_result_4 = {32'd0, _zz_memory_DivPlugin_div_result_5};
assign _zz_memory_DivPlugin_rs1_3 = _zz_memory_DivPlugin_rs1;
assign _zz_memory_DivPlugin_rs1_2 = {32'd0, _zz_memory_DivPlugin_rs1_3};
assign _zz_memory_DivPlugin_rs2_2 = _zz_memory_DivPlugin_rs2;
assign _zz_memory_DivPlugin_rs2_1 = {31'd0, _zz_memory_DivPlugin_rs2_2};
assign _zz_execute_CfuPlugin_functionsIds_0 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]};
assign _zz_iBusWishbone_ADR_1 = (iBus_cmd_payload_address >>> 5);
assign _zz_decode_RegFilePlugin_rs1Data = 1'b1;
assign _zz_decode_RegFilePlugin_rs2Data = 1'b1;
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_6 = {_zz_IBusCachedPlugin_jump_pcLoad_payload_4,_zz_IBusCachedPlugin_jump_pcLoad_payload_3};
assign _zz_writeBack_DBusCachedPlugin_rspShifted_1 = dataCache_1_io_cpu_writeBack_address[1 : 0];
assign _zz_writeBack_DBusCachedPlugin_rspShifted_3 = dataCache_1_io_cpu_writeBack_address[1 : 1];
assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000106f;
assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000107f);
assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00001073;
assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073);
assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063);
assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}};
assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000207f;
assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'h0000505f);
assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000003;
assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063);
assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f);
assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_12) == 32'h00005013),{(_zz_decode_LEGAL_INSTRUCTION_13 == _zz_decode_LEGAL_INSTRUCTION_14),{_zz_decode_LEGAL_INSTRUCTION_15,{_zz_decode_LEGAL_INSTRUCTION_16,_zz_decode_LEGAL_INSTRUCTION_17}}}}}};
assign _zz_decode_LEGAL_INSTRUCTION_12 = 32'hbc00707f;
assign _zz_decode_LEGAL_INSTRUCTION_13 = (decode_INSTRUCTION & 32'hfc00307f);
assign _zz_decode_LEGAL_INSTRUCTION_14 = 32'h00001013;
assign _zz_decode_LEGAL_INSTRUCTION_15 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033);
assign _zz_decode_LEGAL_INSTRUCTION_16 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033);
assign _zz_decode_LEGAL_INSTRUCTION_17 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}};
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_4 = decode_INSTRUCTION[31];
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_5 = decode_INSTRUCTION[31];
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 = decode_INSTRUCTION[7];
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2 = (((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3) == 32'h02000030) != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4 = ((_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6) != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8 != 1'b0),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19}}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3 = 32'h02004074;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5 = (decode_INSTRUCTION & 32'h00203050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6 = 32'h00000050;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8 = ((decode_INSTRUCTION & 32'h00403050) == 32'h00000050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13)};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14 = 2'b00;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15 = ({_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16} != 2'b00);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18 != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10 = (decode_INSTRUCTION & 32'h00001050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11 = 32'h00001050;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12 = (decode_INSTRUCTION & 32'h00002050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13 = 32'h00002050;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24)};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25 = 2'b00;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30}} != 3'b000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33 != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21 = (decode_INSTRUCTION & 32'h00007034);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22 = 32'h00005010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23 = (decode_INSTRUCTION & 32'h02007064);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24 = 32'h00005020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29) == 32'h00001010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31) == 32'h00001010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36) == 32'h00001000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38 = ((_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40) != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44} != 2'b00);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29 = 32'h00007034;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31 = 32'h02007054;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36 = 32'h00001000;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39 = (decode_INSTRUCTION & 32'h00003000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40 = 32'h00002000;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43) == 32'h00002000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45) == 32'h00001000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48) == 32'h00004004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50 = ({_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53}} != 3'b000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58} != 5'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43 = 32'h00002010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45 = 32'h00005000;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48 = 32'h00004054;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57) == 32'h00002040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79}} != 6'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90} != 5'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52 = 32'h00000034;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54 = 32'h00000064;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57 = 32'h00002040;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59 = (decode_INSTRUCTION & 32'h00001040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60 = 32'h00001040;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62) == 32'h00000040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71 = 32'h00000020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75) == 32'h00000008);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115 = 6'h0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118} != 2'b00);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62 = 32'h00000050;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64 = (decode_INSTRUCTION & 32'h00400040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65 = 32'h00000040;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67 = (decode_INSTRUCTION & 32'h00000038);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68 = 32'h0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75 = 32'h00000008;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77 = (decode_INSTRUCTION & 32'h00000040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78 = 32'h00000040;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92) == 32'h00002010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125 = 2'b00;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128 != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81 = (decode_INSTRUCTION & 32'h00004020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82 = 32'h00004020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85) == 32'h00000010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92 = 32'h00002030;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94 = (decode_INSTRUCTION & 32'h00001030);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95 = 32'h00000010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98) == 32'h00002020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104 = (decode_INSTRUCTION & 32'h00001010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105 = 32'h00001010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108) == 32'h00002010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119 = (decode_INSTRUCTION & 32'h00000070);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120 = 32'h00000020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124) == 32'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129) == 32'h00004010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139} != 4'b0000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85 = 32'h00000030;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87 = 32'h02000020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98 = 32'h02002060;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100 = 32'h02003020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108 = 32'h00002010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110 = (decode_INSTRUCTION & 32'h00000050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111 = 32'h00000010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114 = ((decode_INSTRUCTION & 32'h00000024) == 32'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124 = 32'h00000020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129 = 32'h00004014;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132 = (decode_INSTRUCTION & 32'h00006014);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133 = 32'h00002010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138) == 32'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146) == 32'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153}} != 3'b000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158} != 2'b00);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166)};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138 = 32'h00000044;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140 = (decode_INSTRUCTION & 32'h00000018);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141 = 32'h0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146 = 32'h00000058;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152) == 32'h00002010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154) == 32'h40000030);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157) == 32'h00000004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162),_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163 = 2'b00;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165) == 32'h00001004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152 = 32'h00002014;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154 = 32'h40000034;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157 = 32'h00000014;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161 = (decode_INSTRUCTION & 32'h00000044);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162 = 32'h00000004;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165 = 32'h00005054;
assign _zz_execute_BranchPlugin_branch_src2_6 = execute_INSTRUCTION[31];
assign _zz_execute_BranchPlugin_branch_src2_7 = execute_INSTRUCTION[31];
assign _zz_execute_BranchPlugin_branch_src2_8 = execute_INSTRUCTION[7];
assign _zz_CsrPlugin_csrMapping_readDataInit_41 = 32'h0;
always @(posedge clk) begin
if(_zz_decode_RegFilePlugin_rs1Data) begin
_zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1];
end
end
always @(posedge clk) begin
if(_zz_decode_RegFilePlugin_rs2Data) begin
_zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2];
end
end
always @(posedge clk) begin
if(_zz_1) begin
RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data;
end
end
InstructionCache IBusCachedPlugin_cache (
.io_flush (IBusCachedPlugin_cache_io_flush ), //i
.io_cpu_prefetch_isValid (IBusCachedPlugin_cache_io_cpu_prefetch_isValid ), //i
.io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o
.io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload ), //i
.io_cpu_fetch_isValid (IBusCachedPlugin_cache_io_cpu_fetch_isValid ), //i
.io_cpu_fetch_isStuck (IBusCachedPlugin_cache_io_cpu_fetch_isStuck ), //i
.io_cpu_fetch_isRemoved (IBusCachedPlugin_cache_io_cpu_fetch_isRemoved ), //i
.io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload ), //i
.io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data ), //o
.io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i
.io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i
.io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i
.io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i
.io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i
.io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i
.io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i
.io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i
.io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i
.io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress ), //o
.io_cpu_decode_isValid (IBusCachedPlugin_cache_io_cpu_decode_isValid ), //i
.io_cpu_decode_isStuck (IBusCachedPlugin_cache_io_cpu_decode_isStuck ), //i
.io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload ), //i
.io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //o
.io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data ), //o
.io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o
.io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o
.io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o
.io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o
.io_cpu_decode_isUser (IBusCachedPlugin_cache_io_cpu_decode_isUser ), //i
.io_cpu_fill_valid (IBusCachedPlugin_cache_io_cpu_fill_valid ), //i
.io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //i
.io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o
.io_mem_cmd_ready (iBus_cmd_ready ), //i
.io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address ), //o
.io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size ), //o
.io_mem_rsp_valid (iBus_rsp_valid ), //i
.io_mem_rsp_payload_data (iBus_rsp_payload_data ), //i
.io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i
.clk (clk ), //i
.reset (reset ) //i
);
DataCache dataCache_1 (
.io_cpu_execute_isValid (dataCache_1_io_cpu_execute_isValid ), //i
.io_cpu_execute_address (dataCache_1_io_cpu_execute_address ), //i
.io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o
.io_cpu_execute_args_wr (execute_MEMORY_WR ), //i
.io_cpu_execute_args_size (execute_DBusCachedPlugin_size ), //i
.io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i
.io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o
.io_cpu_memory_isValid (dataCache_1_io_cpu_memory_isValid ), //i
.io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i
.io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o
.io_cpu_memory_address (dataCache_1_io_cpu_memory_address ), //i
.io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i
.io_cpu_memory_mmuRsp_isIoAccess (dataCache_1_io_cpu_memory_mmuRsp_isIoAccess ), //i
.io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i
.io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i
.io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i
.io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i
.io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i
.io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i
.io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i
.io_cpu_writeBack_isValid (dataCache_1_io_cpu_writeBack_isValid ), //i
.io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i
.io_cpu_writeBack_isUser (dataCache_1_io_cpu_writeBack_isUser ), //i
.io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o
.io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o
.io_cpu_writeBack_storeData (dataCache_1_io_cpu_writeBack_storeData ), //i
.io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data ), //o
.io_cpu_writeBack_address (dataCache_1_io_cpu_writeBack_address ), //i
.io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o
.io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o
.io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o
.io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o
.io_cpu_writeBack_fence_SW (dataCache_1_io_cpu_writeBack_fence_SW ), //i
.io_cpu_writeBack_fence_SR (dataCache_1_io_cpu_writeBack_fence_SR ), //i
.io_cpu_writeBack_fence_SO (dataCache_1_io_cpu_writeBack_fence_SO ), //i
.io_cpu_writeBack_fence_SI (dataCache_1_io_cpu_writeBack_fence_SI ), //i
.io_cpu_writeBack_fence_PW (dataCache_1_io_cpu_writeBack_fence_PW ), //i
.io_cpu_writeBack_fence_PR (dataCache_1_io_cpu_writeBack_fence_PR ), //i
.io_cpu_writeBack_fence_PO (dataCache_1_io_cpu_writeBack_fence_PO ), //i
.io_cpu_writeBack_fence_PI (dataCache_1_io_cpu_writeBack_fence_PI ), //i
.io_cpu_writeBack_fence_FM (dataCache_1_io_cpu_writeBack_fence_FM ), //i
.io_cpu_writeBack_exclusiveOk (dataCache_1_io_cpu_writeBack_exclusiveOk ), //o
.io_cpu_redo (dataCache_1_io_cpu_redo ), //o
.io_cpu_flush_valid (dataCache_1_io_cpu_flush_valid ), //i
.io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o
.io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o
.io_mem_cmd_ready (dataCache_1_io_mem_cmd_ready ), //i
.io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o
.io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o
.io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address ), //o
.io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data ), //o
.io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask ), //o
.io_mem_cmd_payload_size (dataCache_1_io_mem_cmd_payload_size ), //o
.io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o
.io_mem_rsp_valid (dBus_rsp_valid ), //i
.io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i
.io_mem_rsp_payload_data (dBus_rsp_payload_data ), //i
.io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i
.clk (clk ), //i
.reset (reset ) //i
);
always @(*) begin
case(_zz_IBusCachedPlugin_jump_pcLoad_payload_6)
2'b00 : begin
_zz_IBusCachedPlugin_jump_pcLoad_payload_5 = DBusCachedPlugin_redoBranch_payload;
end
2'b01 : begin
_zz_IBusCachedPlugin_jump_pcLoad_payload_5 = CsrPlugin_jumpInterface_payload;
end
2'b10 : begin
_zz_IBusCachedPlugin_jump_pcLoad_payload_5 = BranchPlugin_jumpInterface_payload;
end
default : begin
_zz_IBusCachedPlugin_jump_pcLoad_payload_5 = IBusCachedPlugin_predictionJumpInterface_payload;
end
endcase
end
always @(*) begin
case(_zz_writeBack_DBusCachedPlugin_rspShifted_1)
2'b00 : begin
_zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_0;
end
2'b01 : begin
_zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_1;
end
2'b10 : begin
_zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_2;
end
default : begin
_zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_3;
end
endcase
end
always @(*) begin
case(_zz_writeBack_DBusCachedPlugin_rspShifted_3)
1'b0 : begin
_zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_1;
end
default : begin
_zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_3;
end
endcase
end
`ifndef SYNTHESIS
always @(*) begin
case(decode_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1)
`Input2Kind_binary_sequential_RS : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "IMM_I";
default : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_memory_to_writeBack_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_string = "ECALL";
default : _zz_memory_to_writeBack_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_memory_to_writeBack_ENV_CTRL_1)
`EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_1_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_1_string = "ECALL";
default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_to_memory_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_string = "ECALL";
default : _zz_execute_to_memory_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_to_memory_ENV_CTRL_1)
`EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_1_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_1_string = "ECALL";
default : _zz_execute_to_memory_ENV_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(decode_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : decode_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : decode_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : decode_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : decode_ENV_CTRL_string = "ECALL";
default : decode_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_string = "ECALL";
default : _zz_decode_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_string = "ECALL";
default : _zz_decode_to_execute_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ENV_CTRL_1)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_1_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_1_string = "ECALL";
default : _zz_decode_to_execute_ENV_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR";
default : _zz_decode_to_execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_BRANCH_CTRL_1)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR";
default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????";
endcase
end
always @(*) begin
case(_zz_execute_to_memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_execute_to_memory_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_execute_to_memory_SHIFT_CTRL_1)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRA_1 ";
default : _zz_execute_to_memory_SHIFT_CTRL_1_string = "?????????";
endcase
end
always @(*) begin
case(decode_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 ";
default : decode_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_decode_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SHIFT_CTRL_1)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 ";
default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????";
endcase
end
always @(*) begin
case(decode_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1";
default : decode_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1";
default : _zz_decode_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1";
default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1";
default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(decode_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : decode_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : decode_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : decode_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : decode_SRC2_CTRL_string = "PC ";
default : decode_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_string = "PC ";
default : _zz_decode_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_string = "PC ";
default : _zz_decode_to_execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SRC2_CTRL_1)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_1_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_1_string = "PC ";
default : _zz_decode_to_execute_SRC2_CTRL_1_string = "???";
endcase
end
always @(*) begin
case(decode_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : decode_ALU_CTRL_string = "BITWISE ";
default : decode_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE ";
default : _zz_decode_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE ";
default : _zz_decode_to_execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ALU_CTRL_1)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE ";
default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????";
endcase
end
always @(*) begin
case(decode_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : decode_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : decode_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : decode_SRC1_CTRL_string = "URS1 ";
default : decode_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_decode_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 ";
default : _zz_decode_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_string = "URS1 ";
default : _zz_decode_to_execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SRC1_CTRL_1)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_1_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_1_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_1_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_1_string = "URS1 ";
default : _zz_decode_to_execute_SRC1_CTRL_1_string = "????????????";
endcase
end
always @(*) begin
case(execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(memory_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : memory_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : memory_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : memory_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : memory_ENV_CTRL_string = "ECALL";
default : memory_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_memory_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_memory_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_memory_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_memory_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_ENV_CTRL_string = "ECALL";
default : _zz_memory_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(execute_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : execute_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : execute_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : execute_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : execute_ENV_CTRL_string = "ECALL";
default : execute_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_execute_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_execute_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_execute_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_ENV_CTRL_string = "ECALL";
default : _zz_execute_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(writeBack_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : writeBack_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : writeBack_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : writeBack_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : writeBack_ENV_CTRL_string = "ECALL";
default : writeBack_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_writeBack_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_writeBack_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_writeBack_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_writeBack_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_writeBack_ENV_CTRL_string = "ECALL";
default : _zz_writeBack_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : execute_BRANCH_CTRL_string = "JALR";
default : execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : _zz_execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_execute_BRANCH_CTRL_string = "JALR";
default : _zz_execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 ";
default : memory_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_memory_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_memory_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_memory_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_memory_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_memory_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(execute_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 ";
default : execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_execute_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : execute_SRC2_CTRL_string = "PC ";
default : execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : _zz_execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_execute_SRC2_CTRL_string = "PC ";
default : _zz_execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : execute_SRC1_CTRL_string = "URS1 ";
default : execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : _zz_execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_execute_SRC1_CTRL_string = "URS1 ";
default : _zz_execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : execute_ALU_CTRL_string = "BITWISE ";
default : execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE ";
default : _zz_execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1";
default : execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1";
default : _zz_execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1)
`Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "IMM_I";
default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_ENV_CTRL_1)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_1_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_1_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_1_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_1_string = "ECALL";
default : _zz_decode_ENV_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_string = "JALR";
default : _zz_decode_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_SHIFT_CTRL_1)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 ";
default : _zz_decode_SHIFT_CTRL_1_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_BITWISE_CTRL_1)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1";
default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_SRC2_CTRL_1)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_1_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_1_string = "PC ";
default : _zz_decode_SRC2_CTRL_1_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_ALU_CTRL_1)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE ";
default : _zz_decode_ALU_CTRL_1_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_SRC1_CTRL_1)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_1_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 ";
default : _zz_decode_SRC1_CTRL_1_string = "????????????";
endcase
end
always @(*) begin
case(decode_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : decode_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : decode_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : decode_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : decode_BRANCH_CTRL_string = "JALR";
default : decode_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_BRANCH_CTRL_1)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_1_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_1_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR";
default : _zz_decode_BRANCH_CTRL_1_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_SRC1_CTRL_2)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_2_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 ";
default : _zz_decode_SRC1_CTRL_2_string = "????????????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_CTRL_2)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE ";
default : _zz_decode_ALU_CTRL_2_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_SRC2_CTRL_2)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_2_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_2_string = "PC ";
default : _zz_decode_SRC2_CTRL_2_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_ALU_BITWISE_CTRL_2)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1";
default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_SHIFT_CTRL_2)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 ";
default : _zz_decode_SHIFT_CTRL_2_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_BRANCH_CTRL_2)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_2_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_2_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_2_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_2_string = "JALR";
default : _zz_decode_BRANCH_CTRL_2_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_ENV_CTRL_2)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_2_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_2_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_2_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_2_string = "ECALL";
default : _zz_decode_ENV_CTRL_2_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8)
`Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "IMM_I";
default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "?????";
endcase
end
always @(*) begin
case(decode_to_execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : decode_to_execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : decode_to_execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 ";
default : decode_to_execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(decode_to_execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE ";
default : decode_to_execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(decode_to_execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : decode_to_execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : decode_to_execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : decode_to_execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : decode_to_execute_SRC2_CTRL_string = "PC ";
default : decode_to_execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(decode_to_execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1";
default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(decode_to_execute_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 ";
default : decode_to_execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(execute_to_memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 ";
default : execute_to_memory_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(decode_to_execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : decode_to_execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : decode_to_execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR";
default : decode_to_execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(decode_to_execute_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : decode_to_execute_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : decode_to_execute_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : decode_to_execute_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL";
default : decode_to_execute_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(execute_to_memory_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : execute_to_memory_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : execute_to_memory_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : execute_to_memory_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL";
default : execute_to_memory_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(memory_to_writeBack_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL";
default : memory_to_writeBack_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
`endif
assign memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW) + $signed(_zz_memory_MUL_LOW_7));
assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT;
assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired);
assign memory_MUL_HH = execute_to_memory_MUL_HH;
assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh));
assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow));
assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh));
assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow);
assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT;
assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA;
assign memory_MEMORY_STORE_DATA_RF = execute_to_memory_MEMORY_STORE_DATA_RF;
assign execute_MEMORY_STORE_DATA_RF = _zz_execute_MEMORY_STORE_DATA_RF;
assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20);
assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0))));
assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch;
assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS));
assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND;
assign _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1;
assign decode_CfuPlugin_CFU_ENABLE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[32];
assign decode_IS_RS2_SIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[31];
assign decode_IS_RS1_SIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[30];
assign decode_IS_DIV = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[29];
assign memory_IS_MUL = execute_to_memory_IS_MUL;
assign execute_IS_MUL = decode_to_execute_IS_MUL;
assign decode_IS_MUL = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[28];
assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1;
assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1;
assign decode_ENV_CTRL = _zz_decode_ENV_CTRL;
assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1;
assign decode_IS_CSR = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[25];
assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1;
assign _zz_execute_to_memory_SHIFT_CTRL = _zz_execute_to_memory_SHIFT_CTRL_1;
assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL;
assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1;
assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL;
assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1;
assign decode_SRC_LESS_UNSIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[17];
assign decode_MEMORY_MANAGMENT = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[16];
assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR;
assign decode_MEMORY_WR = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[13];
assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE;
assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[12];
assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[11];
assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL;
assign _zz_decode_to_execute_SRC2_CTRL = _zz_decode_to_execute_SRC2_CTRL_1;
assign decode_ALU_CTRL = _zz_decode_ALU_CTRL;
assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1;
assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL;
assign _zz_decode_to_execute_SRC1_CTRL = _zz_decode_to_execute_SRC1_CTRL_1;
assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0;
assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT;
assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT;
assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT;
assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004);
assign memory_PC = execute_to_memory_PC;
always @(*) begin
_zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_CfuPlugin_CFU_IN_FLIGHT;
if(memory_arbitration_isStuck) begin
_zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT = 1'b0;
end
end
always @(*) begin
_zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT = execute_CfuPlugin_CFU_IN_FLIGHT;
if(execute_arbitration_isStuck) begin
_zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT = 1'b0;
end
end
assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT;
assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_execute_CfuPlugin_CFU_INPUT_2_KIND;
assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE;
assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED;
assign execute_IS_DIV = decode_to_execute_IS_DIV;
assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED;
assign memory_IS_DIV = execute_to_memory_IS_DIV;
assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL;
assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH;
assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW;
assign memory_MUL_HL = execute_to_memory_MUL_HL;
assign memory_MUL_LH = execute_to_memory_MUL_LH;
assign memory_MUL_LL = execute_to_memory_MUL_LL;
assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE;
assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE;
assign execute_IS_CSR = decode_to_execute_IS_CSR;
assign memory_ENV_CTRL = _zz_memory_ENV_CTRL;
assign execute_ENV_CTRL = _zz_execute_ENV_CTRL;
assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL;
assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0};
assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget);
assign execute_PC = decode_to_execute_PC;
assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2;
assign execute_RS1 = decode_to_execute_RS1;
assign execute_BRANCH_COND_RESULT = _zz_execute_BRANCH_COND_RESULT_1;
assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL;
assign decode_RS2_USE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[15];
assign decode_RS1_USE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[5];
always @(*) begin
_zz_decode_RS2 = execute_REGFILE_WRITE_DATA;
if(when_CsrPlugin_l1176) begin
_zz_decode_RS2 = CsrPlugin_csrMapping_readDataSignal;
end
end
assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID;
assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE;
assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID;
assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION;
assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE;
assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID;
always @(*) begin
decode_RS2 = decode_RegFilePlugin_rs2Data;
if(HazardSimplePlugin_writeBackBuffer_valid) begin
if(HazardSimplePlugin_addr1Match) begin
decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data;
end
end
if(when_HazardSimplePlugin_l45) begin
if(when_HazardSimplePlugin_l47) begin
if(when_HazardSimplePlugin_l51) begin
decode_RS2 = _zz_decode_RS2_2;
end
end
end
if(when_HazardSimplePlugin_l45_1) begin
if(memory_BYPASSABLE_MEMORY_STAGE) begin
if(when_HazardSimplePlugin_l51_1) begin
decode_RS2 = _zz_decode_RS2_1;
end
end
end
if(when_HazardSimplePlugin_l45_2) begin
if(execute_BYPASSABLE_EXECUTE_STAGE) begin
if(when_HazardSimplePlugin_l51_2) begin
decode_RS2 = _zz_decode_RS2;
end
end
end
end
always @(*) begin
decode_RS1 = decode_RegFilePlugin_rs1Data;
if(HazardSimplePlugin_writeBackBuffer_valid) begin
if(HazardSimplePlugin_addr0Match) begin
decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data;
end
end
if(when_HazardSimplePlugin_l45) begin
if(when_HazardSimplePlugin_l47) begin
if(when_HazardSimplePlugin_l48) begin
decode_RS1 = _zz_decode_RS2_2;
end
end
end
if(when_HazardSimplePlugin_l45_1) begin
if(memory_BYPASSABLE_MEMORY_STAGE) begin
if(when_HazardSimplePlugin_l48_1) begin
decode_RS1 = _zz_decode_RS2_1;
end
end
end
if(when_HazardSimplePlugin_l45_2) begin
if(execute_BYPASSABLE_EXECUTE_STAGE) begin
if(when_HazardSimplePlugin_l48_2) begin
decode_RS1 = _zz_decode_RS2;
end
end
end
end
assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT;
always @(*) begin
_zz_decode_RS2_1 = memory_REGFILE_WRITE_DATA;
if(memory_arbitration_isValid) begin
case(memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_SLL_1 : begin
_zz_decode_RS2_1 = _zz_decode_RS2_3;
end
`ShiftCtrlEnum_binary_sequential_SRL_1, `ShiftCtrlEnum_binary_sequential_SRA_1 : begin
_zz_decode_RS2_1 = memory_SHIFT_RIGHT;
end
default : begin
end
endcase
end
if(when_MulDivIterativePlugin_l128) begin
_zz_decode_RS2_1 = memory_DivPlugin_div_result;
end
if(memory_CfuPlugin_CFU_IN_FLIGHT) begin
_zz_decode_RS2_1 = CfuPlugin_bus_rsp_rsp_payload_outputs_0;
end
end
assign memory_SHIFT_CTRL = _zz_memory_SHIFT_CTRL;
assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL;
assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED;
assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO;
assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS;
assign _zz_execute_SRC2 = execute_PC;
assign execute_SRC2_CTRL = _zz_execute_SRC2_CTRL;
assign execute_SRC1_CTRL = _zz_execute_SRC1_CTRL;
assign decode_SRC_USE_SUB_LESS = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[3];
assign decode_SRC_ADD_ZERO = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[20];
assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub;
assign execute_SRC_LESS = execute_SrcPlugin_less;
assign execute_ALU_CTRL = _zz_execute_ALU_CTRL;
assign execute_SRC2 = _zz_execute_SRC2_5;
assign execute_SRC1 = _zz_execute_SRC1;
assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL;
assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION;
assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID;
always @(*) begin
_zz_1 = 1'b0;
if(lastStageRegFileWrite_valid) begin
_zz_1 = 1'b1;
end
end
assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data);
always @(*) begin
decode_REGFILE_WRITE_VALID = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[10];
if(when_RegFilePlugin_l63) begin
decode_REGFILE_WRITE_VALID = 1'b0;
end
end
assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}} != 22'h0);
always @(*) begin
_zz_decode_RS2_2 = writeBack_REGFILE_WRITE_DATA;
if(when_DBusCachedPlugin_l484) begin
_zz_decode_RS2_2 = writeBack_DBusCachedPlugin_rspFormated;
end
if(when_MulPlugin_l147) begin
case(switch_MulPlugin_l148)
2'b00 : begin
_zz_decode_RS2_2 = _zz__zz_decode_RS2_2;
end
default : begin
_zz_decode_RS2_2 = _zz__zz_decode_RS2_2_1;
end
endcase
end
end
assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR;
assign writeBack_MEMORY_STORE_DATA_RF = memory_to_writeBack_MEMORY_STORE_DATA_RF;
assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA;
assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE;
assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA;
assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE;
assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY;
assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT;
assign execute_RS2 = decode_to_execute_RS2;
assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR;
assign execute_SRC_ADD = execute_SrcPlugin_addSub;
assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE;
assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION;
assign decode_MEMORY_ENABLE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[4];
assign decode_FLUSH_ALL = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[0];
always @(*) begin
IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3;
if(when_IBusCachedPlugin_l256) begin
IBusCachedPlugin_rsp_issueDetected_4 = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2;
if(when_IBusCachedPlugin_l250) begin
IBusCachedPlugin_rsp_issueDetected_3 = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1;
if(when_IBusCachedPlugin_l244) begin
IBusCachedPlugin_rsp_issueDetected_2 = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected;
if(when_IBusCachedPlugin_l239) begin
IBusCachedPlugin_rsp_issueDetected_1 = 1'b1;
end
end
assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1;
assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst;
always @(*) begin
_zz_execute_to_memory_FORMAL_PC_NEXT = execute_FORMAL_PC_NEXT;
if(BranchPlugin_jumpInterface_valid) begin
_zz_execute_to_memory_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload;
end
end
always @(*) begin
_zz_decode_to_execute_FORMAL_PC_NEXT = decode_FORMAL_PC_NEXT;
if(IBusCachedPlugin_predictionJumpInterface_valid) begin
_zz_decode_to_execute_FORMAL_PC_NEXT = IBusCachedPlugin_predictionJumpInterface_payload;
end
end
assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc;
assign writeBack_PC = memory_to_writeBack_PC;
assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION;
always @(*) begin
decode_arbitration_haltItself = 1'b0;
if(when_DBusCachedPlugin_l303) begin
decode_arbitration_haltItself = 1'b1;
end
end
always @(*) begin
decode_arbitration_haltByOther = 1'b0;
if(when_HazardSimplePlugin_l113) begin
decode_arbitration_haltByOther = 1'b1;
end
if(CsrPlugin_pipelineLiberator_active) begin
decode_arbitration_haltByOther = 1'b1;
end
if(when_CsrPlugin_l1116) begin
decode_arbitration_haltByOther = 1'b1;
end
end
always @(*) begin
decode_arbitration_removeIt = 1'b0;
if(_zz_when) begin
decode_arbitration_removeIt = 1'b1;
end
if(decode_arbitration_isFlushed) begin
decode_arbitration_removeIt = 1'b1;
end
end
assign decode_arbitration_flushIt = 1'b0;
always @(*) begin
decode_arbitration_flushNext = 1'b0;
if(IBusCachedPlugin_predictionJumpInterface_valid) begin
decode_arbitration_flushNext = 1'b1;
end
if(_zz_when) begin
decode_arbitration_flushNext = 1'b1;
end
end
always @(*) begin
execute_arbitration_haltItself = 1'b0;
if(when_DBusCachedPlugin_l343) begin
execute_arbitration_haltItself = 1'b1;
end
if(when_CsrPlugin_l1108) begin
if(when_CsrPlugin_l1110) begin
execute_arbitration_haltItself = 1'b1;
end
end
if(when_CsrPlugin_l1180) begin
if(execute_CsrPlugin_blockedBySideEffects) begin
execute_arbitration_haltItself = 1'b1;
end
end
if(when_CfuPlugin_l175) begin
execute_arbitration_haltItself = 1'b1;
end
end
always @(*) begin
execute_arbitration_haltByOther = 1'b0;
if(when_DBusCachedPlugin_l359) begin
execute_arbitration_haltByOther = 1'b1;
end
end
always @(*) begin
execute_arbitration_removeIt = 1'b0;
if(_zz_when_1) begin
execute_arbitration_removeIt = 1'b1;
end
if(execute_arbitration_isFlushed) begin
execute_arbitration_removeIt = 1'b1;
end
end
assign execute_arbitration_flushIt = 1'b0;
always @(*) begin
execute_arbitration_flushNext = 1'b0;
if(BranchPlugin_jumpInterface_valid) begin
execute_arbitration_flushNext = 1'b1;
end
if(_zz_when_1) begin
execute_arbitration_flushNext = 1'b1;
end
end
always @(*) begin
memory_arbitration_haltItself = 1'b0;
if(when_MulDivIterativePlugin_l128) begin
if(when_MulDivIterativePlugin_l129) begin
memory_arbitration_haltItself = 1'b1;
end
end
if(memory_CfuPlugin_CFU_IN_FLIGHT) begin
if(when_CfuPlugin_l208) begin
memory_arbitration_haltItself = 1'b1;
end
end
end
assign memory_arbitration_haltByOther = 1'b0;
always @(*) begin
memory_arbitration_removeIt = 1'b0;
if(memory_arbitration_isFlushed) begin
memory_arbitration_removeIt = 1'b1;
end
end
assign memory_arbitration_flushIt = 1'b0;
assign memory_arbitration_flushNext = 1'b0;
always @(*) begin
writeBack_arbitration_haltItself = 1'b0;
if(when_DBusCachedPlugin_l458) begin
writeBack_arbitration_haltItself = 1'b1;
end
end
assign writeBack_arbitration_haltByOther = 1'b0;
always @(*) begin
writeBack_arbitration_removeIt = 1'b0;
if(DBusCachedPlugin_exceptionBus_valid) begin
writeBack_arbitration_removeIt = 1'b1;
end
if(writeBack_arbitration_isFlushed) begin
writeBack_arbitration_removeIt = 1'b1;
end
end
always @(*) begin
writeBack_arbitration_flushIt = 1'b0;
if(DBusCachedPlugin_redoBranch_valid) begin
writeBack_arbitration_flushIt = 1'b1;
end
end
always @(*) begin
writeBack_arbitration_flushNext = 1'b0;
if(DBusCachedPlugin_redoBranch_valid) begin
writeBack_arbitration_flushNext = 1'b1;
end
if(DBusCachedPlugin_exceptionBus_valid) begin
writeBack_arbitration_flushNext = 1'b1;
end
if(when_CsrPlugin_l1019) begin
writeBack_arbitration_flushNext = 1'b1;
end
if(when_CsrPlugin_l1064) begin
writeBack_arbitration_flushNext = 1'b1;
end
end
assign lastStageInstruction = writeBack_INSTRUCTION;
assign lastStagePc = writeBack_PC;
assign lastStageIsValid = writeBack_arbitration_isValid;
assign lastStageIsFiring = writeBack_arbitration_isFiring;
always @(*) begin
IBusCachedPlugin_fetcherHalt = 1'b0;
if(when_CsrPlugin_l922) begin
IBusCachedPlugin_fetcherHalt = 1'b1;
end
if(when_CsrPlugin_l1019) begin
IBusCachedPlugin_fetcherHalt = 1'b1;
end
if(when_CsrPlugin_l1064) begin
IBusCachedPlugin_fetcherHalt = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_incomingInstruction = 1'b0;
if(when_Fetcher_l240) begin
IBusCachedPlugin_incomingInstruction = 1'b1;
end
end
assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0;
assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit;
always @(*) begin
CsrPlugin_inWfi = 1'b0;
if(when_CsrPlugin_l1108) begin
CsrPlugin_inWfi = 1'b1;
end
end
assign CsrPlugin_thirdPartyWake = 1'b0;
always @(*) begin
CsrPlugin_jumpInterface_valid = 1'b0;
if(when_CsrPlugin_l1019) begin
CsrPlugin_jumpInterface_valid = 1'b1;
end
if(when_CsrPlugin_l1064) begin
CsrPlugin_jumpInterface_valid = 1'b1;
end
end
always @(*) begin
CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
if(when_CsrPlugin_l1019) begin
CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00};
end
if(when_CsrPlugin_l1064) begin
case(switch_CsrPlugin_l1068)
2'b11 : begin
CsrPlugin_jumpInterface_payload = CsrPlugin_mepc;
end
default : begin
end
endcase
end
end
assign CsrPlugin_forceMachineWire = 1'b0;
assign CsrPlugin_allowInterrupts = 1'b1;
assign CsrPlugin_allowException = 1'b1;
assign CsrPlugin_allowEbreakException = 1'b1;
assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000);
assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000);
assign _zz_IBusCachedPlugin_jump_pcLoad_payload = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}};
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload & (~ _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1));
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_2 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[3];
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_3 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[1] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2);
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[2] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2);
assign IBusCachedPlugin_jump_pcLoad_payload = _zz_IBusCachedPlugin_jump_pcLoad_payload_5;
always @(*) begin
IBusCachedPlugin_fetchPc_correction = 1'b0;
if(IBusCachedPlugin_fetchPc_redo_valid) begin
IBusCachedPlugin_fetchPc_correction = 1'b1;
end
if(IBusCachedPlugin_jump_pcLoad_valid) begin
IBusCachedPlugin_fetchPc_correction = 1'b1;
end
end
assign IBusCachedPlugin_fetchPc_output_fire = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready);
assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg);
always @(*) begin
IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0;
if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin
IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1;
end
end
assign when_Fetcher_l131 = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate);
assign IBusCachedPlugin_fetchPc_output_fire_1 = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready);
assign when_Fetcher_l131_1 = ((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready);
always @(*) begin
IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_IBusCachedPlugin_fetchPc_pc);
if(IBusCachedPlugin_fetchPc_redo_valid) begin
IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload;
end
if(IBusCachedPlugin_jump_pcLoad_valid) begin
IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload;
end
IBusCachedPlugin_fetchPc_pc[0] = 1'b0;
IBusCachedPlugin_fetchPc_pc[1] = 1'b0;
end
always @(*) begin
IBusCachedPlugin_fetchPc_flushed = 1'b0;
if(IBusCachedPlugin_fetchPc_redo_valid) begin
IBusCachedPlugin_fetchPc_flushed = 1'b1;
end
if(IBusCachedPlugin_jump_pcLoad_valid) begin
IBusCachedPlugin_fetchPc_flushed = 1'b1;
end
end
assign when_Fetcher_l158 = (IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate));
assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted);
assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc;
always @(*) begin
IBusCachedPlugin_iBusRsp_redoFetch = 1'b0;
if(IBusCachedPlugin_rsp_redoFetch) begin
IBusCachedPlugin_iBusRsp_redoFetch = 1'b1;
end
end
assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid;
assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready;
assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload;
always @(*) begin
IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0;
if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt) begin
IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1;
end
end
assign _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready = (! IBusCachedPlugin_iBusRsp_stages_0_halt);
assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload;
always @(*) begin
IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0;
if(IBusCachedPlugin_mmuBus_busy) begin
IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1;
end
end
assign _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready = (! IBusCachedPlugin_iBusRsp_stages_1_halt);
assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload;
always @(*) begin
IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0;
if(when_IBusCachedPlugin_l267) begin
IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1;
end
end
assign _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready = (! IBusCachedPlugin_iBusRsp_stages_2_halt);
assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload;
assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch;
assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload;
assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch);
assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready;
assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2;
assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1;
assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg;
assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid)) || IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready);
assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid;
assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload;
assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid;
assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready = IBusCachedPlugin_iBusRsp_stages_2_input_ready;
assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload;
always @(*) begin
IBusCachedPlugin_iBusRsp_readyForError = 1'b1;
if(when_Fetcher_l320) begin
IBusCachedPlugin_iBusRsp_readyForError = 1'b0;
end
end
assign when_Fetcher_l240 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid);
assign when_Fetcher_l320 = (! IBusCachedPlugin_pcValids_0);
assign when_Fetcher_l329 = (! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready));
assign when_Fetcher_l329_1 = (! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready));
assign when_Fetcher_l329_2 = (! execute_arbitration_isStuck);
assign when_Fetcher_l329_3 = (! memory_arbitration_isStuck);
assign when_Fetcher_l329_4 = (! writeBack_arbitration_isStuck);
assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1;
assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2;
assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3;
assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4;
assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck);
assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid;
assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch[11];
always @(*) begin
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[18] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[17] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[16] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[15] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[14] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[13] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[12] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[11] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[10] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[9] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[8] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[7] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[6] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[5] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[4] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[3] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[2] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[1] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[0] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
end
always @(*) begin
IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_B) && _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2[31]));
if(_zz_6) begin
IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0;
end
end
assign _zz_2 = _zz__zz_2[19];
always @(*) begin
_zz_3[10] = _zz_2;
_zz_3[9] = _zz_2;
_zz_3[8] = _zz_2;
_zz_3[7] = _zz_2;
_zz_3[6] = _zz_2;
_zz_3[5] = _zz_2;
_zz_3[4] = _zz_2;
_zz_3[3] = _zz_2;
_zz_3[2] = _zz_2;
_zz_3[1] = _zz_2;
_zz_3[0] = _zz_2;
end
assign _zz_4 = _zz__zz_4[11];
always @(*) begin
_zz_5[18] = _zz_4;
_zz_5[17] = _zz_4;
_zz_5[16] = _zz_4;
_zz_5[15] = _zz_4;
_zz_5[14] = _zz_4;
_zz_5[13] = _zz_4;
_zz_5[12] = _zz_4;
_zz_5[11] = _zz_4;
_zz_5[10] = _zz_4;
_zz_5[9] = _zz_4;
_zz_5[8] = _zz_4;
_zz_5[7] = _zz_4;
_zz_5[6] = _zz_4;
_zz_5[5] = _zz_4;
_zz_5[4] = _zz_4;
_zz_5[3] = _zz_4;
_zz_5[2] = _zz_4;
_zz_5[1] = _zz_4;
_zz_5[0] = _zz_4;
end
always @(*) begin
case(decode_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_JAL : begin
_zz_6 = _zz__zz_6[1];
end
default : begin
_zz_6 = _zz__zz_6_1[1];
end
endcase
end
assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch);
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload[19];
always @(*) begin
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
end
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2[11];
always @(*) begin
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[18] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[17] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[16] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[15] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[14] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[13] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[12] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[11] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
end
assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_1,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_4,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_3,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_5,_zz_IBusCachedPlugin_predictionJumpInterface_payload_6},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}));
assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid;
always @(*) begin
iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address;
iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address;
end
assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size;
assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0;
assign IBusCachedPlugin_cache_io_cpu_prefetch_isValid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit));
assign IBusCachedPlugin_cache_io_cpu_fetch_isValid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit));
assign IBusCachedPlugin_cache_io_cpu_fetch_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign IBusCachedPlugin_mmuBus_cmd_0_isValid = IBusCachedPlugin_cache_io_cpu_fetch_isValid;
assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload;
assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0;
assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush);
assign IBusCachedPlugin_cache_io_cpu_decode_isValid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit));
assign IBusCachedPlugin_cache_io_cpu_decode_isStuck = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready);
assign IBusCachedPlugin_cache_io_cpu_decode_isUser = (CsrPlugin_privilege == 2'b00);
assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0;
assign IBusCachedPlugin_rsp_issueDetected = 1'b0;
always @(*) begin
IBusCachedPlugin_rsp_redoFetch = 1'b0;
if(when_IBusCachedPlugin_l239) begin
IBusCachedPlugin_rsp_redoFetch = 1'b1;
end
if(when_IBusCachedPlugin_l250) begin
IBusCachedPlugin_rsp_redoFetch = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_cache_io_cpu_fill_valid = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling));
if(when_IBusCachedPlugin_l250) begin
IBusCachedPlugin_cache_io_cpu_fill_valid = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_decodeExceptionPort_valid = 1'b0;
if(when_IBusCachedPlugin_l244) begin
IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError;
end
if(when_IBusCachedPlugin_l256) begin
IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError;
end
end
always @(*) begin
IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx;
if(when_IBusCachedPlugin_l244) begin
IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100;
end
if(when_IBusCachedPlugin_l256) begin
IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001;
end
end
assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00};
assign when_IBusCachedPlugin_l239 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected));
assign when_IBusCachedPlugin_l244 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1));
assign when_IBusCachedPlugin_l250 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2));
assign when_IBusCachedPlugin_l256 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3));
assign when_IBusCachedPlugin_l267 = (IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt);
assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid;
assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready;
assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data;
assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload;
assign IBusCachedPlugin_cache_io_flush = (decode_arbitration_isValid && decode_FLUSH_ALL);
assign dataCache_1_io_mem_cmd_ready = (! dataCache_1_io_mem_cmd_rValid);
assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_rValid);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_wr : dataCache_1_io_mem_cmd_payload_wr);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_address : dataCache_1_io_mem_cmd_payload_address);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_data : dataCache_1_io_mem_cmd_payload_data);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_mask : dataCache_1_io_mem_cmd_payload_mask);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_size = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_size : dataCache_1_io_mem_cmd_payload_size);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_last : dataCache_1_io_mem_cmd_payload_last);
always @(*) begin
dataCache_1_io_mem_cmd_s2mPipe_ready = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready;
if(when_Stream_l342) begin
dataCache_1_io_mem_cmd_s2mPipe_ready = 1'b1;
end
end
assign when_Stream_l342 = (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid);
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_rValid;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_rData_wr;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_rData_uncached;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_rData_address;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_rData_data;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_rData_mask;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size = dataCache_1_io_mem_cmd_s2mPipe_rData_size;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_rData_last;
assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready;
assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr;
assign dBus_cmd_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached;
assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address;
assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data;
assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask;
assign dBus_cmd_payload_size = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size;
assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last;
assign when_DBusCachedPlugin_l303 = ((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE);
assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12];
assign dataCache_1_io_cpu_execute_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE);
assign dataCache_1_io_cpu_execute_address = execute_SRC_ADD;
always @(*) begin
case(execute_DBusCachedPlugin_size)
2'b00 : begin
_zz_execute_MEMORY_STORE_DATA_RF = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]};
end
2'b01 : begin
_zz_execute_MEMORY_STORE_DATA_RF = {execute_RS2[15 : 0],execute_RS2[15 : 0]};
end
default : begin
_zz_execute_MEMORY_STORE_DATA_RF = execute_RS2[31 : 0];
end
endcase
end
assign dataCache_1_io_cpu_flush_valid = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT);
assign dataCache_1_io_cpu_flush_isStall = (dataCache_1_io_cpu_flush_valid && (! dataCache_1_io_cpu_flush_ready));
assign when_DBusCachedPlugin_l343 = (dataCache_1_io_cpu_flush_isStall || dataCache_1_io_cpu_execute_haltIt);
assign when_DBusCachedPlugin_l359 = (dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid);
assign dataCache_1_io_cpu_memory_isValid = (memory_arbitration_isValid && memory_MEMORY_ENABLE);
assign dataCache_1_io_cpu_memory_address = memory_REGFILE_WRITE_DATA;
assign DBusCachedPlugin_mmuBus_cmd_0_isValid = dataCache_1_io_cpu_memory_isValid;
assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck;
assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = dataCache_1_io_cpu_memory_address;
assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0;
assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt);
always @(*) begin
dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_isIoAccess;
if(when_DBusCachedPlugin_l386) begin
dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = 1'b1;
end
end
assign when_DBusCachedPlugin_l386 = (1'b0 && (! dataCache_1_io_cpu_memory_isWrite));
always @(*) begin
dataCache_1_io_cpu_writeBack_isValid = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE);
if(writeBack_arbitration_haltByOther) begin
dataCache_1_io_cpu_writeBack_isValid = 1'b0;
end
end
assign dataCache_1_io_cpu_writeBack_isUser = (CsrPlugin_privilege == 2'b00);
assign dataCache_1_io_cpu_writeBack_address = writeBack_REGFILE_WRITE_DATA;
assign dataCache_1_io_cpu_writeBack_storeData[31 : 0] = writeBack_MEMORY_STORE_DATA_RF;
always @(*) begin
DBusCachedPlugin_redoBranch_valid = 1'b0;
if(when_DBusCachedPlugin_l438) begin
if(dataCache_1_io_cpu_redo) begin
DBusCachedPlugin_redoBranch_valid = 1'b1;
end
end
end
assign DBusCachedPlugin_redoBranch_payload = writeBack_PC;
always @(*) begin
DBusCachedPlugin_exceptionBus_valid = 1'b0;
if(when_DBusCachedPlugin_l438) begin
if(dataCache_1_io_cpu_writeBack_accessError) begin
DBusCachedPlugin_exceptionBus_valid = 1'b1;
end
if(dataCache_1_io_cpu_writeBack_mmuException) begin
DBusCachedPlugin_exceptionBus_valid = 1'b1;
end
if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin
DBusCachedPlugin_exceptionBus_valid = 1'b1;
end
if(dataCache_1_io_cpu_redo) begin
DBusCachedPlugin_exceptionBus_valid = 1'b0;
end
end
end
assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA;
always @(*) begin
DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx;
if(when_DBusCachedPlugin_l438) begin
if(dataCache_1_io_cpu_writeBack_accessError) begin
DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code};
end
if(dataCache_1_io_cpu_writeBack_mmuException) begin
DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101);
end
if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin
DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code_1};
end
end
end
assign when_DBusCachedPlugin_l438 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE);
assign when_DBusCachedPlugin_l458 = (dataCache_1_io_cpu_writeBack_isValid && dataCache_1_io_cpu_writeBack_haltIt);
assign writeBack_DBusCachedPlugin_rspSplits_0 = dataCache_1_io_cpu_writeBack_data[7 : 0];
assign writeBack_DBusCachedPlugin_rspSplits_1 = dataCache_1_io_cpu_writeBack_data[15 : 8];
assign writeBack_DBusCachedPlugin_rspSplits_2 = dataCache_1_io_cpu_writeBack_data[23 : 16];
assign writeBack_DBusCachedPlugin_rspSplits_3 = dataCache_1_io_cpu_writeBack_data[31 : 24];
always @(*) begin
writeBack_DBusCachedPlugin_rspShifted[7 : 0] = _zz_writeBack_DBusCachedPlugin_rspShifted;
writeBack_DBusCachedPlugin_rspShifted[15 : 8] = _zz_writeBack_DBusCachedPlugin_rspShifted_2;
writeBack_DBusCachedPlugin_rspShifted[23 : 16] = writeBack_DBusCachedPlugin_rspSplits_2;
writeBack_DBusCachedPlugin_rspShifted[31 : 24] = writeBack_DBusCachedPlugin_rspSplits_3;
end
assign writeBack_DBusCachedPlugin_rspRf = writeBack_DBusCachedPlugin_rspShifted[31 : 0];
assign switch_Misc_l200 = writeBack_INSTRUCTION[13 : 12];
assign _zz_writeBack_DBusCachedPlugin_rspFormated = (writeBack_DBusCachedPlugin_rspRf[7] && (! writeBack_INSTRUCTION[14]));
always @(*) begin
_zz_writeBack_DBusCachedPlugin_rspFormated_1[31] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[30] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[29] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[28] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[27] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[26] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[25] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[24] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[23] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[22] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[21] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[20] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[19] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[18] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[17] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[16] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[15] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[14] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[13] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[12] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[11] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[10] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[9] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[8] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[7 : 0] = writeBack_DBusCachedPlugin_rspRf[7 : 0];
end
assign _zz_writeBack_DBusCachedPlugin_rspFormated_2 = (writeBack_DBusCachedPlugin_rspRf[15] && (! writeBack_INSTRUCTION[14]));
always @(*) begin
_zz_writeBack_DBusCachedPlugin_rspFormated_3[31] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[30] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[29] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[28] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[27] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[26] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[25] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[24] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[23] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[22] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[21] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[20] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[19] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[18] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[17] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[16] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[15 : 0] = writeBack_DBusCachedPlugin_rspRf[15 : 0];
end
always @(*) begin
case(switch_Misc_l200)
2'b00 : begin
writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_1;
end
2'b01 : begin
writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_3;
end
default : begin
writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspRf;
end
endcase
end
assign when_DBusCachedPlugin_l484 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE);
assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress;
assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1;
assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1;
assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1;
assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = IBusCachedPlugin_mmuBus_rsp_physicalAddress[31];
assign IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0;
assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0;
assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0;
assign IBusCachedPlugin_mmuBus_busy = 1'b0;
assign DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress;
assign DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1;
assign DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1;
assign DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1;
assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_physicalAddress[31];
assign DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0;
assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0;
assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0;
assign DBusCachedPlugin_mmuBus_busy = 1'b0;
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 = {1'b0,{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6 != 1'b0),{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 != 1'b0),{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 != 1'b0),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7}}}}}}};
assign _zz_decode_SRC1_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[2 : 1];
assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2;
assign _zz_decode_ALU_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[7 : 6];
assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2;
assign _zz_decode_SRC2_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[9 : 8];
assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2;
assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[19 : 18];
assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2;
assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[22 : 21];
assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2;
assign _zz_decode_BRANCH_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[24 : 23];
assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_2;
assign _zz_decode_ENV_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[27 : 26];
assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_2;
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[33 : 33];
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8;
assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION));
assign decodeExceptionPort_payload_code = 4'b0010;
assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION;
assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0);
assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15];
assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20];
assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0;
assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1;
always @(*) begin
lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring);
if(_zz_7) begin
lastStageRegFileWrite_valid = 1'b1;
end
end
always @(*) begin
lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7];
if(_zz_7) begin
lastStageRegFileWrite_payload_address = 5'h0;
end
end
always @(*) begin
lastStageRegFileWrite_payload_data = _zz_decode_RS2_2;
if(_zz_7) begin
lastStageRegFileWrite_payload_data = 32'h0;
end
end
always @(*) begin
case(execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2);
end
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2);
end
default : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2);
end
endcase
end
always @(*) begin
case(execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_BITWISE : begin
_zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise;
end
`AluCtrlEnum_binary_sequential_SLT_SLTU : begin
_zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA};
end
default : begin
_zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB;
end
endcase
end
always @(*) begin
case(execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : begin
_zz_execute_SRC1 = execute_RS1;
end
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : begin
_zz_execute_SRC1 = {29'd0, _zz__zz_execute_SRC1};
end
`Src1CtrlEnum_binary_sequential_IMU : begin
_zz_execute_SRC1 = {execute_INSTRUCTION[31 : 12],12'h0};
end
default : begin
_zz_execute_SRC1 = {27'd0, _zz__zz_execute_SRC1_1};
end
endcase
end
assign _zz_execute_SRC2_1 = execute_INSTRUCTION[31];
always @(*) begin
_zz_execute_SRC2_2[19] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[18] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[17] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[16] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[15] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[14] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[13] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[12] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[11] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[10] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[9] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[8] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[7] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[6] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[5] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[4] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[3] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[2] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[1] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[0] = _zz_execute_SRC2_1;
end
assign _zz_execute_SRC2_3 = _zz__zz_execute_SRC2_3[11];
always @(*) begin
_zz_execute_SRC2_4[19] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[18] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[17] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[16] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[15] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[14] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[13] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[12] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[11] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[10] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[9] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[8] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[7] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[6] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[5] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[4] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[3] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[2] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[1] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[0] = _zz_execute_SRC2_3;
end
always @(*) begin
case(execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : begin
_zz_execute_SRC2_5 = execute_RS2;
end
`Src2CtrlEnum_binary_sequential_IMI : begin
_zz_execute_SRC2_5 = {_zz_execute_SRC2_2,execute_INSTRUCTION[31 : 20]};
end
`Src2CtrlEnum_binary_sequential_IMS : begin
_zz_execute_SRC2_5 = {_zz_execute_SRC2_4,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}};
end
default : begin
_zz_execute_SRC2_5 = _zz_execute_SRC2;
end
endcase
end
always @(*) begin
execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub;
if(execute_SRC2_FORCE_ZERO) begin
execute_SrcPlugin_addSub = execute_SRC1;
end
end
assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31]));
assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0];
always @(*) begin
_zz_execute_FullBarrelShifterPlugin_reversed[0] = execute_SRC1[31];
_zz_execute_FullBarrelShifterPlugin_reversed[1] = execute_SRC1[30];
_zz_execute_FullBarrelShifterPlugin_reversed[2] = execute_SRC1[29];
_zz_execute_FullBarrelShifterPlugin_reversed[3] = execute_SRC1[28];
_zz_execute_FullBarrelShifterPlugin_reversed[4] = execute_SRC1[27];
_zz_execute_FullBarrelShifterPlugin_reversed[5] = execute_SRC1[26];
_zz_execute_FullBarrelShifterPlugin_reversed[6] = execute_SRC1[25];
_zz_execute_FullBarrelShifterPlugin_reversed[7] = execute_SRC1[24];
_zz_execute_FullBarrelShifterPlugin_reversed[8] = execute_SRC1[23];
_zz_execute_FullBarrelShifterPlugin_reversed[9] = execute_SRC1[22];
_zz_execute_FullBarrelShifterPlugin_reversed[10] = execute_SRC1[21];
_zz_execute_FullBarrelShifterPlugin_reversed[11] = execute_SRC1[20];
_zz_execute_FullBarrelShifterPlugin_reversed[12] = execute_SRC1[19];
_zz_execute_FullBarrelShifterPlugin_reversed[13] = execute_SRC1[18];
_zz_execute_FullBarrelShifterPlugin_reversed[14] = execute_SRC1[17];
_zz_execute_FullBarrelShifterPlugin_reversed[15] = execute_SRC1[16];
_zz_execute_FullBarrelShifterPlugin_reversed[16] = execute_SRC1[15];
_zz_execute_FullBarrelShifterPlugin_reversed[17] = execute_SRC1[14];
_zz_execute_FullBarrelShifterPlugin_reversed[18] = execute_SRC1[13];
_zz_execute_FullBarrelShifterPlugin_reversed[19] = execute_SRC1[12];
_zz_execute_FullBarrelShifterPlugin_reversed[20] = execute_SRC1[11];
_zz_execute_FullBarrelShifterPlugin_reversed[21] = execute_SRC1[10];
_zz_execute_FullBarrelShifterPlugin_reversed[22] = execute_SRC1[9];
_zz_execute_FullBarrelShifterPlugin_reversed[23] = execute_SRC1[8];
_zz_execute_FullBarrelShifterPlugin_reversed[24] = execute_SRC1[7];
_zz_execute_FullBarrelShifterPlugin_reversed[25] = execute_SRC1[6];
_zz_execute_FullBarrelShifterPlugin_reversed[26] = execute_SRC1[5];
_zz_execute_FullBarrelShifterPlugin_reversed[27] = execute_SRC1[4];
_zz_execute_FullBarrelShifterPlugin_reversed[28] = execute_SRC1[3];
_zz_execute_FullBarrelShifterPlugin_reversed[29] = execute_SRC1[2];
_zz_execute_FullBarrelShifterPlugin_reversed[30] = execute_SRC1[1];
_zz_execute_FullBarrelShifterPlugin_reversed[31] = execute_SRC1[0];
end
assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SLL_1) ? _zz_execute_FullBarrelShifterPlugin_reversed : execute_SRC1);
always @(*) begin
_zz_decode_RS2_3[0] = memory_SHIFT_RIGHT[31];
_zz_decode_RS2_3[1] = memory_SHIFT_RIGHT[30];
_zz_decode_RS2_3[2] = memory_SHIFT_RIGHT[29];
_zz_decode_RS2_3[3] = memory_SHIFT_RIGHT[28];
_zz_decode_RS2_3[4] = memory_SHIFT_RIGHT[27];
_zz_decode_RS2_3[5] = memory_SHIFT_RIGHT[26];
_zz_decode_RS2_3[6] = memory_SHIFT_RIGHT[25];
_zz_decode_RS2_3[7] = memory_SHIFT_RIGHT[24];
_zz_decode_RS2_3[8] = memory_SHIFT_RIGHT[23];
_zz_decode_RS2_3[9] = memory_SHIFT_RIGHT[22];
_zz_decode_RS2_3[10] = memory_SHIFT_RIGHT[21];
_zz_decode_RS2_3[11] = memory_SHIFT_RIGHT[20];
_zz_decode_RS2_3[12] = memory_SHIFT_RIGHT[19];
_zz_decode_RS2_3[13] = memory_SHIFT_RIGHT[18];
_zz_decode_RS2_3[14] = memory_SHIFT_RIGHT[17];
_zz_decode_RS2_3[15] = memory_SHIFT_RIGHT[16];
_zz_decode_RS2_3[16] = memory_SHIFT_RIGHT[15];
_zz_decode_RS2_3[17] = memory_SHIFT_RIGHT[14];
_zz_decode_RS2_3[18] = memory_SHIFT_RIGHT[13];
_zz_decode_RS2_3[19] = memory_SHIFT_RIGHT[12];
_zz_decode_RS2_3[20] = memory_SHIFT_RIGHT[11];
_zz_decode_RS2_3[21] = memory_SHIFT_RIGHT[10];
_zz_decode_RS2_3[22] = memory_SHIFT_RIGHT[9];
_zz_decode_RS2_3[23] = memory_SHIFT_RIGHT[8];
_zz_decode_RS2_3[24] = memory_SHIFT_RIGHT[7];
_zz_decode_RS2_3[25] = memory_SHIFT_RIGHT[6];
_zz_decode_RS2_3[26] = memory_SHIFT_RIGHT[5];
_zz_decode_RS2_3[27] = memory_SHIFT_RIGHT[4];
_zz_decode_RS2_3[28] = memory_SHIFT_RIGHT[3];
_zz_decode_RS2_3[29] = memory_SHIFT_RIGHT[2];
_zz_decode_RS2_3[30] = memory_SHIFT_RIGHT[1];
_zz_decode_RS2_3[31] = memory_SHIFT_RIGHT[0];
end
always @(*) begin
HazardSimplePlugin_src0Hazard = 1'b0;
if(when_HazardSimplePlugin_l57) begin
if(when_HazardSimplePlugin_l58) begin
if(when_HazardSimplePlugin_l48) begin
HazardSimplePlugin_src0Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l57_1) begin
if(when_HazardSimplePlugin_l58_1) begin
if(when_HazardSimplePlugin_l48_1) begin
HazardSimplePlugin_src0Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l57_2) begin
if(when_HazardSimplePlugin_l58_2) begin
if(when_HazardSimplePlugin_l48_2) begin
HazardSimplePlugin_src0Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l105) begin
HazardSimplePlugin_src0Hazard = 1'b0;
end
end
always @(*) begin
HazardSimplePlugin_src1Hazard = 1'b0;
if(when_HazardSimplePlugin_l57) begin
if(when_HazardSimplePlugin_l58) begin
if(when_HazardSimplePlugin_l51) begin
HazardSimplePlugin_src1Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l57_1) begin
if(when_HazardSimplePlugin_l58_1) begin
if(when_HazardSimplePlugin_l51_1) begin
HazardSimplePlugin_src1Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l57_2) begin
if(when_HazardSimplePlugin_l58_2) begin
if(when_HazardSimplePlugin_l51_2) begin
HazardSimplePlugin_src1Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l108) begin
HazardSimplePlugin_src1Hazard = 1'b0;
end
end
assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring);
assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7];
assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_decode_RS2_2;
assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]);
assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]);
assign when_HazardSimplePlugin_l47 = 1'b1;
assign when_HazardSimplePlugin_l48 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);
assign when_HazardSimplePlugin_l51 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);
assign when_HazardSimplePlugin_l45 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l58 = (1'b0 || (! when_HazardSimplePlugin_l47));
assign when_HazardSimplePlugin_l48_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);
assign when_HazardSimplePlugin_l51_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);
assign when_HazardSimplePlugin_l45_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l58_1 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE));
assign when_HazardSimplePlugin_l48_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);
assign when_HazardSimplePlugin_l51_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);
assign when_HazardSimplePlugin_l45_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l58_2 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE));
assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE);
assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE);
assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard));
assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2);
assign switch_Misc_l200_1 = execute_INSTRUCTION[14 : 12];
always @(*) begin
casez(switch_Misc_l200_1)
3'b000 : begin
_zz_execute_BRANCH_COND_RESULT = execute_BranchPlugin_eq;
end
3'b001 : begin
_zz_execute_BRANCH_COND_RESULT = (! execute_BranchPlugin_eq);
end
3'b1?1 : begin
_zz_execute_BRANCH_COND_RESULT = (! execute_SRC_LESS);
end
default : begin
_zz_execute_BRANCH_COND_RESULT = execute_SRC_LESS;
end
endcase
end
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : begin
_zz_execute_BRANCH_COND_RESULT_1 = 1'b0;
end
`BranchCtrlEnum_binary_sequential_JAL : begin
_zz_execute_BRANCH_COND_RESULT_1 = 1'b1;
end
`BranchCtrlEnum_binary_sequential_JALR : begin
_zz_execute_BRANCH_COND_RESULT_1 = 1'b1;
end
default : begin
_zz_execute_BRANCH_COND_RESULT_1 = _zz_execute_BRANCH_COND_RESULT;
end
endcase
end
assign _zz_execute_BranchPlugin_missAlignedTarget = execute_INSTRUCTION[31];
always @(*) begin
_zz_execute_BranchPlugin_missAlignedTarget_1[19] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[18] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[17] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[16] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[15] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[14] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[13] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[12] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[11] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[10] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[9] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[8] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[7] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[6] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[5] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[4] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[3] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[2] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[1] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[0] = _zz_execute_BranchPlugin_missAlignedTarget;
end
assign _zz_execute_BranchPlugin_missAlignedTarget_2 = _zz__zz_execute_BranchPlugin_missAlignedTarget_2[19];
always @(*) begin
_zz_execute_BranchPlugin_missAlignedTarget_3[10] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[9] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[8] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[7] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[6] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[5] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[4] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[3] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[2] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[1] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[0] = _zz_execute_BranchPlugin_missAlignedTarget_2;
end
assign _zz_execute_BranchPlugin_missAlignedTarget_4 = _zz__zz_execute_BranchPlugin_missAlignedTarget_4[11];
always @(*) begin
_zz_execute_BranchPlugin_missAlignedTarget_5[18] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[17] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[16] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[15] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[14] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[13] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[12] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[11] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[10] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[9] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[8] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[7] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[6] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[5] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[4] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[3] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[2] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[1] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[0] = _zz_execute_BranchPlugin_missAlignedTarget_4;
end
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_JALR : begin
_zz_execute_BranchPlugin_missAlignedTarget_6 = (_zz__zz_execute_BranchPlugin_missAlignedTarget_6[1] ^ execute_RS1[1]);
end
`BranchCtrlEnum_binary_sequential_JAL : begin
_zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1[1];
end
default : begin
_zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2[1];
end
endcase
end
assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_execute_BranchPlugin_missAlignedTarget_6);
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_JALR : begin
execute_BranchPlugin_branch_src1 = execute_RS1;
end
default : begin
execute_BranchPlugin_branch_src1 = execute_PC;
end
endcase
end
assign _zz_execute_BranchPlugin_branch_src2 = execute_INSTRUCTION[31];
always @(*) begin
_zz_execute_BranchPlugin_branch_src2_1[19] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[18] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[17] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[16] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[15] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[14] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[13] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[12] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[11] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2;
end
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_JALR : begin
execute_BranchPlugin_branch_src2 = {_zz_execute_BranchPlugin_branch_src2_1,execute_INSTRUCTION[31 : 20]};
end
default : begin
execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_execute_BranchPlugin_branch_src2_3,{{{_zz_execute_BranchPlugin_branch_src2_6,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_execute_BranchPlugin_branch_src2_5,{{{_zz_execute_BranchPlugin_branch_src2_7,_zz_execute_BranchPlugin_branch_src2_8},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0});
if(execute_PREDICTION_HAD_BRANCHED2) begin
execute_BranchPlugin_branch_src2 = {29'd0, _zz_execute_BranchPlugin_branch_src2_9};
end
end
endcase
end
assign _zz_execute_BranchPlugin_branch_src2_2 = _zz__zz_execute_BranchPlugin_branch_src2_2[19];
always @(*) begin
_zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2;
end
assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11];
always @(*) begin
_zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4;
end
assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2);
assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && (! 1'b0));
assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC;
always @(*) begin
BranchPlugin_branchExceptionPort_valid = (execute_arbitration_isValid && (execute_BRANCH_DO && execute_BRANCH_CALC[1]));
if(when_BranchPlugin_l296) begin
BranchPlugin_branchExceptionPort_valid = 1'b0;
end
end
assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000;
assign BranchPlugin_branchExceptionPort_payload_badAddr = execute_BRANCH_CALC;
assign when_BranchPlugin_l296 = 1'b0;
assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid;
always @(*) begin
CsrPlugin_privilege = 2'b11;
if(CsrPlugin_forceMachineWire) begin
CsrPlugin_privilege = 2'b11;
end
end
assign _zz_when_CsrPlugin_l952 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE);
assign _zz_when_CsrPlugin_l952_1 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE);
assign _zz_when_CsrPlugin_l952_2 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE);
assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11;
assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege);
assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid};
assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1[0];
assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid};
assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3[0];
always @(*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
if(_zz_when) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1;
end
if(decode_arbitration_isFlushed) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0;
end
end
always @(*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
if(_zz_when_1) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1;
end
if(execute_arbitration_isFlushed) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0;
end
end
always @(*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
if(memory_arbitration_isFlushed) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0;
end
end
always @(*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
if(DBusCachedPlugin_exceptionBus_valid) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1;
end
if(writeBack_arbitration_isFlushed) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0;
end
end
assign when_CsrPlugin_l909 = (! decode_arbitration_isStuck);
assign when_CsrPlugin_l909_1 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l909_2 = (! memory_arbitration_isStuck);
assign when_CsrPlugin_l909_3 = (! writeBack_arbitration_isStuck);
assign when_CsrPlugin_l922 = ({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000);
assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
assign when_CsrPlugin_l946 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11));
assign when_CsrPlugin_l952 = ((_zz_when_CsrPlugin_l952 && 1'b1) && (! 1'b0));
assign when_CsrPlugin_l952_1 = ((_zz_when_CsrPlugin_l952_1 && 1'b1) && (! 1'b0));
assign when_CsrPlugin_l952_2 = ((_zz_when_CsrPlugin_l952_2 && 1'b1) && (! 1'b0));
assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException);
assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid);
assign when_CsrPlugin_l980 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l980_1 = (! memory_arbitration_isStuck);
assign when_CsrPlugin_l980_2 = (! writeBack_arbitration_isStuck);
assign when_CsrPlugin_l985 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt);
always @(*) begin
CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2;
if(when_CsrPlugin_l991) begin
CsrPlugin_pipelineLiberator_done = 1'b0;
end
if(CsrPlugin_hadException) begin
CsrPlugin_pipelineLiberator_done = 1'b0;
end
end
assign when_CsrPlugin_l991 = ({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000);
assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts);
always @(*) begin
CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege;
if(CsrPlugin_hadException) begin
CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege;
end
end
always @(*) begin
CsrPlugin_trapCause = CsrPlugin_interrupt_code;
if(CsrPlugin_hadException) begin
CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code;
end
end
always @(*) begin
CsrPlugin_xtvec_mode = 2'bxx;
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode;
end
default : begin
end
endcase
end
always @(*) begin
CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_xtvec_base = CsrPlugin_mtvec_base;
end
default : begin
end
endcase
end
assign when_CsrPlugin_l1019 = (CsrPlugin_hadException || CsrPlugin_interruptJump);
assign when_CsrPlugin_l1064 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET));
assign switch_CsrPlugin_l1068 = writeBack_INSTRUCTION[29 : 28];
assign contextSwitching = CsrPlugin_jumpInterface_valid;
assign when_CsrPlugin_l1108 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI));
assign when_CsrPlugin_l1110 = (! execute_CsrPlugin_wfiWake);
assign when_CsrPlugin_l1116 = ({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET))}} != 3'b000);
assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0);
always @(*) begin
execute_CsrPlugin_illegalAccess = 1'b1;
if(execute_CsrPlugin_csr_3264) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3857) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3858) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3859) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3860) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_769) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_768) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_836) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_772) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_773) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_833) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_832) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_834) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_835) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_2816) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_2944) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_2818) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_2946) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_3072) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3200) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3074) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3202) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3008) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_4032) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_2820) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_2821) begin
if(execute_CSR_WRITE_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_2822) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_2823) begin
if(execute_CSR_WRITE_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_2824) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_2825) begin
if(execute_CSR_WRITE_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_2826) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_2827) begin
if(execute_CSR_WRITE_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_2828) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_2829) begin
if(execute_CSR_WRITE_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_2830) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_2831) begin
if(execute_CSR_WRITE_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_2832) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_2833) begin
if(execute_CSR_WRITE_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_2834) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_2835) begin
if(execute_CSR_WRITE_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(CsrPlugin_csrMapping_allowCsrSignal) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(when_CsrPlugin_l1297) begin
execute_CsrPlugin_illegalAccess = 1'b1;
end
if(when_CsrPlugin_l1302) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
always @(*) begin
execute_CsrPlugin_illegalInstruction = 1'b0;
if(when_CsrPlugin_l1136) begin
if(when_CsrPlugin_l1137) begin
execute_CsrPlugin_illegalInstruction = 1'b1;
end
end
end
always @(*) begin
CsrPlugin_selfException_valid = 1'b0;
if(when_CsrPlugin_l1129) begin
CsrPlugin_selfException_valid = 1'b1;
end
if(when_CsrPlugin_l1144) begin
CsrPlugin_selfException_valid = 1'b1;
end
end
always @(*) begin
CsrPlugin_selfException_payload_code = 4'bxxxx;
if(when_CsrPlugin_l1129) begin
CsrPlugin_selfException_payload_code = 4'b0010;
end
if(when_CsrPlugin_l1144) begin
case(CsrPlugin_privilege)
2'b00 : begin
CsrPlugin_selfException_payload_code = 4'b1000;
end
default : begin
CsrPlugin_selfException_payload_code = 4'b1011;
end
endcase
end
end
assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION;
assign when_CsrPlugin_l1129 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction);
assign when_CsrPlugin_l1136 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET));
assign when_CsrPlugin_l1137 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]);
assign when_CsrPlugin_l1144 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_ECALL));
always @(*) begin
execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE);
if(when_CsrPlugin_l1297) begin
execute_CsrPlugin_writeInstruction = 1'b0;
end
end
always @(*) begin
execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE);
if(when_CsrPlugin_l1297) begin
execute_CsrPlugin_readInstruction = 1'b0;
end
end
assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck));
assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck));
assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects);
assign execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal;
assign switch_Misc_l200_2 = execute_INSTRUCTION[13];
always @(*) begin
case(switch_Misc_l200_2)
1'b0 : begin
_zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1;
end
default : begin
_zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1));
end
endcase
end
assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal;
assign when_CsrPlugin_l1176 = (execute_arbitration_isValid && execute_IS_CSR);
assign when_CsrPlugin_l1180 = (execute_arbitration_isValid && (execute_IS_CSR || 1'b0));
assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20];
assign execute_MulPlugin_a = execute_RS1;
assign execute_MulPlugin_b = execute_RS2;
assign switch_MulPlugin_l87 = execute_INSTRUCTION[13 : 12];
always @(*) begin
case(switch_MulPlugin_l87)
2'b01 : begin
execute_MulPlugin_aSigned = 1'b1;
end
2'b10 : begin
execute_MulPlugin_aSigned = 1'b1;
end
default : begin
execute_MulPlugin_aSigned = 1'b0;
end
endcase
end
always @(*) begin
case(switch_MulPlugin_l87)
2'b01 : begin
execute_MulPlugin_bSigned = 1'b1;
end
2'b10 : begin
execute_MulPlugin_bSigned = 1'b0;
end
default : begin
execute_MulPlugin_bSigned = 1'b0;
end
endcase
end
assign execute_MulPlugin_aULow = execute_MulPlugin_a[15 : 0];
assign execute_MulPlugin_bULow = execute_MulPlugin_b[15 : 0];
assign execute_MulPlugin_aSLow = {1'b0,execute_MulPlugin_a[15 : 0]};
assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]};
assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]};
assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]};
assign writeBack_MulPlugin_result = ($signed(_zz_writeBack_MulPlugin_result) + $signed(_zz_writeBack_MulPlugin_result_1));
assign when_MulPlugin_l147 = (writeBack_arbitration_isValid && writeBack_IS_MUL);
assign switch_MulPlugin_l148 = writeBack_INSTRUCTION[13 : 12];
assign memory_DivPlugin_frontendOk = 1'b1;
always @(*) begin
memory_DivPlugin_div_counter_willIncrement = 1'b0;
if(when_MulDivIterativePlugin_l128) begin
if(when_MulDivIterativePlugin_l132) begin
memory_DivPlugin_div_counter_willIncrement = 1'b1;
end
end
end
always @(*) begin
memory_DivPlugin_div_counter_willClear = 1'b0;
if(when_MulDivIterativePlugin_l162) begin
memory_DivPlugin_div_counter_willClear = 1'b1;
end
end
assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21);
assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement);
always @(*) begin
if(memory_DivPlugin_div_counter_willOverflow) begin
memory_DivPlugin_div_counter_valueNext = 6'h0;
end else begin
memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_memory_DivPlugin_div_counter_valueNext);
end
if(memory_DivPlugin_div_counter_willClear) begin
memory_DivPlugin_div_counter_valueNext = 6'h0;
end
end
assign when_MulDivIterativePlugin_l126 = (memory_DivPlugin_div_counter_value == 6'h20);
assign when_MulDivIterativePlugin_l126_1 = (! memory_arbitration_isStuck);
assign when_MulDivIterativePlugin_l128 = (memory_arbitration_isValid && memory_IS_DIV);
assign when_MulDivIterativePlugin_l129 = ((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done));
assign when_MulDivIterativePlugin_l132 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done));
assign _zz_memory_DivPlugin_div_stage_0_remainderShifted = memory_DivPlugin_rs1[31 : 0];
assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_memory_DivPlugin_div_stage_0_remainderShifted[31]};
assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator);
assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_memory_DivPlugin_div_stage_0_outRemainder : _zz_memory_DivPlugin_div_stage_0_outRemainder_1);
assign memory_DivPlugin_div_stage_0_outNumerator = _zz_memory_DivPlugin_div_stage_0_outNumerator[31:0];
assign when_MulDivIterativePlugin_l151 = (memory_DivPlugin_div_counter_value == 6'h20);
assign _zz_memory_DivPlugin_div_result = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]);
assign when_MulDivIterativePlugin_l162 = (! memory_arbitration_isStuck);
assign _zz_memory_DivPlugin_rs2 = (execute_RS2[31] && execute_IS_RS2_SIGNED);
assign _zz_memory_DivPlugin_rs1 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED));
always @(*) begin
_zz_memory_DivPlugin_rs1_1[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]);
_zz_memory_DivPlugin_rs1_1[31 : 0] = execute_RS1;
end
assign _zz_CsrPlugin_csrMapping_readDataInit_1 = (_zz_CsrPlugin_csrMapping_readDataInit & externalInterruptArray_regNext);
assign externalInterrupt = (_zz_CsrPlugin_csrMapping_readDataInit_1 != 32'h0);
assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE);
assign CfuPlugin_bus_cmd_fire = (CfuPlugin_bus_cmd_valid && CfuPlugin_bus_cmd_ready);
assign when_CfuPlugin_l171 = (! execute_arbitration_isStuckByOthers);
assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired));
assign when_CfuPlugin_l175 = (CfuPlugin_bus_cmd_valid && (! CfuPlugin_bus_cmd_ready));
assign execute_CfuPlugin_functionsIds_0 = _zz_execute_CfuPlugin_functionsIds_0;
assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0;
assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1;
assign _zz_CfuPlugin_bus_cmd_payload_inputs_1 = execute_INSTRUCTION[31];
always @(*) begin
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[23] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[22] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[21] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[20] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[19] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[18] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[17] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[16] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[15] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[14] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[13] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[12] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[11] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[10] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[9] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[8] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[7] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[6] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[5] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[4] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[3] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[2] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[1] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[0] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
end
always @(*) begin
case(execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : begin
_zz_CfuPlugin_bus_cmd_payload_inputs_1_2 = execute_RS2;
end
default : begin
_zz_CfuPlugin_bus_cmd_payload_inputs_1_2 = {_zz_CfuPlugin_bus_cmd_payload_inputs_1_1,execute_INSTRUCTION[31 : 24]};
end
endcase
end
assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_CfuPlugin_bus_cmd_payload_inputs_1_2;
assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_rValid);
assign CfuPlugin_bus_rsp_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_rValid);
assign CfuPlugin_bus_rsp_rsp_payload_outputs_0 = (CfuPlugin_bus_rsp_rValid ? CfuPlugin_bus_rsp_rData_outputs_0 : CfuPlugin_bus_rsp_payload_outputs_0);
always @(*) begin
CfuPlugin_bus_rsp_rsp_ready = 1'b0;
if(memory_CfuPlugin_CFU_IN_FLIGHT) begin
CfuPlugin_bus_rsp_rsp_ready = (! memory_arbitration_isStuckByOthers);
end
end
assign when_CfuPlugin_l208 = (! CfuPlugin_bus_rsp_rsp_valid);
assign when_GenCoreDefault_l367 = _zz_when_GenCoreDefault_l367[0];
assign when_GenCoreDefault_l367_1 = _zz_when_GenCoreDefault_l367_1[0];
assign when_GenCoreDefault_l367_2 = _zz_when_GenCoreDefault_l367_2[0];
assign when_GenCoreDefault_l367_3 = _zz_when_GenCoreDefault_l367_3[0];
assign when_GenCoreDefault_l367_4 = _zz_when_GenCoreDefault_l367_4[0];
assign when_GenCoreDefault_l367_5 = _zz_when_GenCoreDefault_l367_5[0];
assign when_GenCoreDefault_l367_6 = _zz_when_GenCoreDefault_l367_6[0];
assign when_GenCoreDefault_l367_7 = _zz_when_GenCoreDefault_l367_7[0];
assign when_Pipeline_l124 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack));
assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck);
assign _zz_decode_to_execute_SRC1_CTRL_1 = decode_SRC1_CTRL;
assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1;
assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck);
assign _zz_execute_SRC1_CTRL = decode_to_execute_SRC1_CTRL;
assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_12 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_13 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_14 = (! writeBack_arbitration_isStuck);
assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL;
assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1;
assign when_Pipeline_l124_15 = (! execute_arbitration_isStuck);
assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL;
assign _zz_decode_to_execute_SRC2_CTRL_1 = decode_SRC2_CTRL;
assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1;
assign when_Pipeline_l124_16 = (! execute_arbitration_isStuck);
assign _zz_execute_SRC2_CTRL = decode_to_execute_SRC2_CTRL;
assign when_Pipeline_l124_17 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_18 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_19 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_20 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_21 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_22 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_23 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_24 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_25 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_26 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_27 = (! execute_arbitration_isStuck);
assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL;
assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1;
assign when_Pipeline_l124_28 = (! execute_arbitration_isStuck);
assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL;
assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL;
assign _zz_execute_to_memory_SHIFT_CTRL_1 = execute_SHIFT_CTRL;
assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1;
assign when_Pipeline_l124_29 = (! execute_arbitration_isStuck);
assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL;
assign when_Pipeline_l124_30 = (! memory_arbitration_isStuck);
assign _zz_memory_SHIFT_CTRL = execute_to_memory_SHIFT_CTRL;
assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL;
assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL;
assign when_Pipeline_l124_31 = (! execute_arbitration_isStuck);
assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL;
assign when_Pipeline_l124_32 = (! execute_arbitration_isStuck);
assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL;
assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL;
assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL;
assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1;
assign when_Pipeline_l124_33 = (! execute_arbitration_isStuck);
assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL;
assign when_Pipeline_l124_34 = (! memory_arbitration_isStuck);
assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL;
assign when_Pipeline_l124_35 = (! writeBack_arbitration_isStuck);
assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL;
assign when_Pipeline_l124_36 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_37 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_38 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_39 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_40 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_41 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_42 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_43 = (! execute_arbitration_isStuck);
assign _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1 = decode_CfuPlugin_CFU_INPUT_2_KIND;
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1;
assign when_Pipeline_l124_44 = (! execute_arbitration_isStuck);
assign _zz_execute_CfuPlugin_CFU_INPUT_2_KIND = decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND;
assign when_Pipeline_l124_45 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_46 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_47 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_48 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_49 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_50 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_51 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_52 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_53 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_54 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_55 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_56 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_57 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_58 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_59 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_60 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_61 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_62 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_63 = (! writeBack_arbitration_isStuck);
assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000));
assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000));
assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00));
assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0));
assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck));
assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers);
assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt));
assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt));
assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck));
assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers);
assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt));
assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt));
assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck));
assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers);
assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt));
assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt));
assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0);
assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers);
assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt));
assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt));
assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt);
assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt));
assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt);
assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt));
assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt);
assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt));
assign when_CsrPlugin_l1264 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_1 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_2 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_3 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_4 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_5 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_6 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_7 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_8 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_9 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_10 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_11 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_12 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_13 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_14 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_15 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_16 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_17 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_18 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_19 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_20 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_21 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_22 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_23 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_24 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_25 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_26 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_27 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_28 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_29 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_30 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_31 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_32 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_33 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_34 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_35 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_36 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_37 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_38 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_39 = (! execute_arbitration_isStuck);
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_10 = 32'h0;
if(execute_CsrPlugin_csr_3264) begin
_zz_CsrPlugin_csrMapping_readDataInit_10[13 : 0] = 14'h2000;
_zz_CsrPlugin_csrMapping_readDataInit_10[25 : 20] = 6'h20;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_11 = 32'h0;
if(execute_CsrPlugin_csr_3857) begin
_zz_CsrPlugin_csrMapping_readDataInit_11[3 : 0] = 4'b1011;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_12 = 32'h0;
if(execute_CsrPlugin_csr_3858) begin
_zz_CsrPlugin_csrMapping_readDataInit_12[4 : 0] = 5'h16;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_13 = 32'h0;
if(execute_CsrPlugin_csr_3859) begin
_zz_CsrPlugin_csrMapping_readDataInit_13[5 : 0] = 6'h21;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_14 = 32'h0;
if(execute_CsrPlugin_csr_769) begin
_zz_CsrPlugin_csrMapping_readDataInit_14[31 : 30] = CsrPlugin_misa_base;
_zz_CsrPlugin_csrMapping_readDataInit_14[25 : 0] = CsrPlugin_misa_extensions;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_15 = 32'h0;
if(execute_CsrPlugin_csr_768) begin
_zz_CsrPlugin_csrMapping_readDataInit_15[12 : 11] = CsrPlugin_mstatus_MPP;
_zz_CsrPlugin_csrMapping_readDataInit_15[7 : 7] = CsrPlugin_mstatus_MPIE;
_zz_CsrPlugin_csrMapping_readDataInit_15[3 : 3] = CsrPlugin_mstatus_MIE;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_16 = 32'h0;
if(execute_CsrPlugin_csr_836) begin
_zz_CsrPlugin_csrMapping_readDataInit_16[11 : 11] = CsrPlugin_mip_MEIP;
_zz_CsrPlugin_csrMapping_readDataInit_16[7 : 7] = CsrPlugin_mip_MTIP;
_zz_CsrPlugin_csrMapping_readDataInit_16[3 : 3] = CsrPlugin_mip_MSIP;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_17 = 32'h0;
if(execute_CsrPlugin_csr_772) begin
_zz_CsrPlugin_csrMapping_readDataInit_17[11 : 11] = CsrPlugin_mie_MEIE;
_zz_CsrPlugin_csrMapping_readDataInit_17[7 : 7] = CsrPlugin_mie_MTIE;
_zz_CsrPlugin_csrMapping_readDataInit_17[3 : 3] = CsrPlugin_mie_MSIE;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_18 = 32'h0;
if(execute_CsrPlugin_csr_773) begin
_zz_CsrPlugin_csrMapping_readDataInit_18[31 : 2] = CsrPlugin_mtvec_base;
_zz_CsrPlugin_csrMapping_readDataInit_18[1 : 0] = CsrPlugin_mtvec_mode;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_19 = 32'h0;
if(execute_CsrPlugin_csr_833) begin
_zz_CsrPlugin_csrMapping_readDataInit_19[31 : 0] = CsrPlugin_mepc;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_20 = 32'h0;
if(execute_CsrPlugin_csr_832) begin
_zz_CsrPlugin_csrMapping_readDataInit_20[31 : 0] = CsrPlugin_mscratch;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_21 = 32'h0;
if(execute_CsrPlugin_csr_834) begin
_zz_CsrPlugin_csrMapping_readDataInit_21[31 : 31] = CsrPlugin_mcause_interrupt;
_zz_CsrPlugin_csrMapping_readDataInit_21[3 : 0] = CsrPlugin_mcause_exceptionCode;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_22 = 32'h0;
if(execute_CsrPlugin_csr_835) begin
_zz_CsrPlugin_csrMapping_readDataInit_22[31 : 0] = CsrPlugin_mtval;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_23 = 32'h0;
if(execute_CsrPlugin_csr_2816) begin
_zz_CsrPlugin_csrMapping_readDataInit_23[31 : 0] = CsrPlugin_mcycle[31 : 0];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_24 = 32'h0;
if(execute_CsrPlugin_csr_2944) begin
_zz_CsrPlugin_csrMapping_readDataInit_24[31 : 0] = CsrPlugin_mcycle[63 : 32];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_25 = 32'h0;
if(execute_CsrPlugin_csr_2818) begin
_zz_CsrPlugin_csrMapping_readDataInit_25[31 : 0] = CsrPlugin_minstret[31 : 0];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_26 = 32'h0;
if(execute_CsrPlugin_csr_2946) begin
_zz_CsrPlugin_csrMapping_readDataInit_26[31 : 0] = CsrPlugin_minstret[63 : 32];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_27 = 32'h0;
if(execute_CsrPlugin_csr_3072) begin
_zz_CsrPlugin_csrMapping_readDataInit_27[31 : 0] = CsrPlugin_mcycle[31 : 0];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_28 = 32'h0;
if(execute_CsrPlugin_csr_3200) begin
_zz_CsrPlugin_csrMapping_readDataInit_28[31 : 0] = CsrPlugin_mcycle[63 : 32];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_29 = 32'h0;
if(execute_CsrPlugin_csr_3074) begin
_zz_CsrPlugin_csrMapping_readDataInit_29[31 : 0] = CsrPlugin_minstret[31 : 0];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_30 = 32'h0;
if(execute_CsrPlugin_csr_3202) begin
_zz_CsrPlugin_csrMapping_readDataInit_30[31 : 0] = CsrPlugin_minstret[63 : 32];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_31 = 32'h0;
if(execute_CsrPlugin_csr_3008) begin
_zz_CsrPlugin_csrMapping_readDataInit_31[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_32 = 32'h0;
if(execute_CsrPlugin_csr_4032) begin
_zz_CsrPlugin_csrMapping_readDataInit_32[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_1;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_33 = 32'h0;
if(execute_CsrPlugin_csr_2820) begin
_zz_CsrPlugin_csrMapping_readDataInit_33[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_2;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_34 = 32'h0;
if(execute_CsrPlugin_csr_2822) begin
_zz_CsrPlugin_csrMapping_readDataInit_34[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_3;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_35 = 32'h0;
if(execute_CsrPlugin_csr_2824) begin
_zz_CsrPlugin_csrMapping_readDataInit_35[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_4;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_36 = 32'h0;
if(execute_CsrPlugin_csr_2826) begin
_zz_CsrPlugin_csrMapping_readDataInit_36[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_5;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_37 = 32'h0;
if(execute_CsrPlugin_csr_2828) begin
_zz_CsrPlugin_csrMapping_readDataInit_37[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_6;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_38 = 32'h0;
if(execute_CsrPlugin_csr_2830) begin
_zz_CsrPlugin_csrMapping_readDataInit_38[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_7;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_39 = 32'h0;
if(execute_CsrPlugin_csr_2832) begin
_zz_CsrPlugin_csrMapping_readDataInit_39[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_8;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_40 = 32'h0;
if(execute_CsrPlugin_csr_2834) begin
_zz_CsrPlugin_csrMapping_readDataInit_40[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_9;
end
end
assign CsrPlugin_csrMapping_readDataInit = (((((_zz_CsrPlugin_csrMapping_readDataInit_10 | _zz_CsrPlugin_csrMapping_readDataInit_11) | (_zz_CsrPlugin_csrMapping_readDataInit_12 | _zz_CsrPlugin_csrMapping_readDataInit_13)) | ((_zz_CsrPlugin_csrMapping_readDataInit_41 | _zz_CsrPlugin_csrMapping_readDataInit_14) | (_zz_CsrPlugin_csrMapping_readDataInit_15 | _zz_CsrPlugin_csrMapping_readDataInit_16))) | (((_zz_CsrPlugin_csrMapping_readDataInit_17 | _zz_CsrPlugin_csrMapping_readDataInit_18) | (_zz_CsrPlugin_csrMapping_readDataInit_19 | _zz_CsrPlugin_csrMapping_readDataInit_20)) | ((_zz_CsrPlugin_csrMapping_readDataInit_21 | _zz_CsrPlugin_csrMapping_readDataInit_22) | (_zz_CsrPlugin_csrMapping_readDataInit_23 | _zz_CsrPlugin_csrMapping_readDataInit_24)))) | ((((_zz_CsrPlugin_csrMapping_readDataInit_25 | _zz_CsrPlugin_csrMapping_readDataInit_26) | (_zz_CsrPlugin_csrMapping_readDataInit_27 | _zz_CsrPlugin_csrMapping_readDataInit_28)) | ((_zz_CsrPlugin_csrMapping_readDataInit_29 | _zz_CsrPlugin_csrMapping_readDataInit_30) | (_zz_CsrPlugin_csrMapping_readDataInit_31 | _zz_CsrPlugin_csrMapping_readDataInit_32))) | (((_zz_CsrPlugin_csrMapping_readDataInit_33 | _zz_CsrPlugin_csrMapping_readDataInit_34) | (_zz_CsrPlugin_csrMapping_readDataInit_35 | _zz_CsrPlugin_csrMapping_readDataInit_36)) | ((_zz_CsrPlugin_csrMapping_readDataInit_37 | _zz_CsrPlugin_csrMapping_readDataInit_38) | (_zz_CsrPlugin_csrMapping_readDataInit_39 | _zz_CsrPlugin_csrMapping_readDataInit_40)))));
assign when_CsrPlugin_l1297 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]);
assign when_CsrPlugin_l1302 = ((! execute_arbitration_isValid) || (! execute_IS_CSR));
assign iBusWishbone_ADR = {_zz_iBusWishbone_ADR_1,_zz_iBusWishbone_ADR};
assign iBusWishbone_CTI = ((_zz_iBusWishbone_ADR == 3'b111) ? 3'b111 : 3'b010);
assign iBusWishbone_BTE = 2'b00;
assign iBusWishbone_SEL = 4'b1111;
assign iBusWishbone_WE = 1'b0;
assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
always @(*) begin
iBusWishbone_CYC = 1'b0;
if(when_InstructionCache_l239) begin
iBusWishbone_CYC = 1'b1;
end
end
always @(*) begin
iBusWishbone_STB = 1'b0;
if(when_InstructionCache_l239) begin
iBusWishbone_STB = 1'b1;
end
end
assign when_InstructionCache_l239 = (iBus_cmd_valid || (_zz_iBusWishbone_ADR != 3'b000));
assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK);
assign iBus_rsp_valid = _zz_iBus_rsp_valid;
assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext;
assign iBus_rsp_payload_error = 1'b0;
assign _zz_dBus_cmd_ready_5 = (dBus_cmd_payload_size == 3'b101);
assign _zz_dBus_cmd_ready_1 = dBus_cmd_valid;
assign _zz_dBus_cmd_ready_3 = dBus_cmd_payload_wr;
assign _zz_dBus_cmd_ready_4 = ((! _zz_dBus_cmd_ready_5) || (_zz_dBus_cmd_ready == 3'b111));
assign dBus_cmd_ready = (_zz_dBus_cmd_ready_2 && (_zz_dBus_cmd_ready_3 || _zz_dBus_cmd_ready_4));
assign dBusWishbone_ADR = ((_zz_dBus_cmd_ready_5 ? {{dBus_cmd_payload_address[31 : 5],_zz_dBus_cmd_ready},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2);
assign dBusWishbone_CTI = (_zz_dBus_cmd_ready_5 ? (_zz_dBus_cmd_ready_4 ? 3'b111 : 3'b010) : 3'b000);
assign dBusWishbone_BTE = 2'b00;
assign dBusWishbone_SEL = (_zz_dBus_cmd_ready_3 ? dBus_cmd_payload_mask : 4'b1111);
assign dBusWishbone_WE = _zz_dBus_cmd_ready_3;
assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data;
assign _zz_dBus_cmd_ready_2 = (_zz_dBus_cmd_ready_1 && dBusWishbone_ACK);
assign dBusWishbone_CYC = _zz_dBus_cmd_ready_1;
assign dBusWishbone_STB = _zz_dBus_cmd_ready_1;
assign dBus_rsp_valid = _zz_dBus_rsp_valid;
assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext;
assign dBus_rsp_payload_error = 1'b0;
always @(posedge clk) begin
if(reset) begin
IBusCachedPlugin_fetchPc_pcReg <= externalResetVector;
IBusCachedPlugin_fetchPc_correctionReg <= 1'b0;
IBusCachedPlugin_fetchPc_booted <= 1'b0;
IBusCachedPlugin_fetchPc_inc <= 1'b0;
_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0;
_zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0;
IBusCachedPlugin_rspCounter <= _zz_IBusCachedPlugin_rspCounter;
IBusCachedPlugin_rspCounter <= 32'h0;
dataCache_1_io_mem_cmd_rValid <= 1'b0;
dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0;
DBusCachedPlugin_rspCounter <= _zz_DBusCachedPlugin_rspCounter;
DBusCachedPlugin_rspCounter <= 32'h0;
_zz_7 <= 1'b1;
HazardSimplePlugin_writeBackBuffer_valid <= 1'b0;
CsrPlugin_misa_base <= 2'b01;
CsrPlugin_misa_extensions <= 26'h0000042;
CsrPlugin_mstatus_MIE <= 1'b0;
CsrPlugin_mstatus_MPIE <= 1'b0;
CsrPlugin_mstatus_MPP <= 2'b11;
CsrPlugin_mie_MEIE <= 1'b0;
CsrPlugin_mie_MTIE <= 1'b0;
CsrPlugin_mie_MSIE <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0;
CsrPlugin_interrupt_valid <= 1'b0;
CsrPlugin_lastStageWasWfi <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0;
CsrPlugin_hadException <= 1'b0;
execute_CsrPlugin_wfiWake <= 1'b0;
memory_DivPlugin_div_counter_value <= 6'h0;
_zz_CsrPlugin_csrMapping_readDataInit <= 32'h0;
execute_CfuPlugin_hold <= 1'b0;
execute_CfuPlugin_fired <= 1'b0;
CfuPlugin_bus_rsp_rValid <= 1'b0;
execute_arbitration_isValid <= 1'b0;
memory_arbitration_isValid <= 1'b0;
writeBack_arbitration_isValid <= 1'b0;
execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0;
_zz_iBusWishbone_ADR <= 3'b000;
_zz_iBus_rsp_valid <= 1'b0;
_zz_dBus_cmd_ready <= 3'b000;
_zz_dBus_rsp_valid <= 1'b0;
end else begin
if(IBusCachedPlugin_fetchPc_correction) begin
IBusCachedPlugin_fetchPc_correctionReg <= 1'b1;
end
if(IBusCachedPlugin_fetchPc_output_fire) begin
IBusCachedPlugin_fetchPc_correctionReg <= 1'b0;
end
IBusCachedPlugin_fetchPc_booted <= 1'b1;
if(when_Fetcher_l131) begin
IBusCachedPlugin_fetchPc_inc <= 1'b0;
end
if(IBusCachedPlugin_fetchPc_output_fire_1) begin
IBusCachedPlugin_fetchPc_inc <= 1'b1;
end
if(when_Fetcher_l131_1) begin
IBusCachedPlugin_fetchPc_inc <= 1'b0;
end
if(when_Fetcher_l158) begin
IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc;
end
if(IBusCachedPlugin_iBusRsp_flush) begin
_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0;
end
if(_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready) begin
_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0));
end
if(IBusCachedPlugin_iBusRsp_flush) begin
_zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0;
end
if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin
_zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush));
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0;
end
if(when_Fetcher_l329) begin
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
end
if(when_Fetcher_l329_1) begin
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
end
if(when_Fetcher_l329_2) begin
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0;
end
if(when_Fetcher_l329_3) begin
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0;
end
if(when_Fetcher_l329_4) begin
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0;
end
if(iBus_rsp_valid) begin
IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001);
end
if(dataCache_1_io_mem_cmd_valid) begin
dataCache_1_io_mem_cmd_rValid <= 1'b1;
end
if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin
dataCache_1_io_mem_cmd_rValid <= 1'b0;
end
if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin
dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid;
end
if(dBus_rsp_valid) begin
DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001);
end
_zz_7 <= 1'b0;
HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid;
if(when_CsrPlugin_l909) begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0;
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode;
end
if(when_CsrPlugin_l909_1) begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck));
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute;
end
if(when_CsrPlugin_l909_2) begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck));
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory;
end
if(when_CsrPlugin_l909_3) begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck));
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0;
end
CsrPlugin_interrupt_valid <= 1'b0;
if(when_CsrPlugin_l946) begin
if(when_CsrPlugin_l952) begin
CsrPlugin_interrupt_valid <= 1'b1;
end
if(when_CsrPlugin_l952_1) begin
CsrPlugin_interrupt_valid <= 1'b1;
end
if(when_CsrPlugin_l952_2) begin
CsrPlugin_interrupt_valid <= 1'b1;
end
end
CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI));
if(CsrPlugin_pipelineLiberator_active) begin
if(when_CsrPlugin_l980) begin
CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1;
end
if(when_CsrPlugin_l980_1) begin
CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0;
end
if(when_CsrPlugin_l980_2) begin
CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1;
end
end
if(when_CsrPlugin_l985) begin
CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0;
end
if(CsrPlugin_interruptJump) begin
CsrPlugin_interrupt_valid <= 1'b0;
end
CsrPlugin_hadException <= CsrPlugin_exception;
if(when_CsrPlugin_l1019) begin
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_mstatus_MIE <= 1'b0;
CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE;
CsrPlugin_mstatus_MPP <= CsrPlugin_privilege;
end
default : begin
end
endcase
end
if(when_CsrPlugin_l1064) begin
case(switch_CsrPlugin_l1068)
2'b11 : begin
CsrPlugin_mstatus_MPP <= 2'b00;
CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE;
CsrPlugin_mstatus_MPIE <= 1'b1;
end
default : begin
end
endcase
end
execute_CsrPlugin_wfiWake <= (({_zz_when_CsrPlugin_l952_2,{_zz_when_CsrPlugin_l952_1,_zz_when_CsrPlugin_l952}} != 3'b000) || CsrPlugin_thirdPartyWake);
memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext;
if(execute_CfuPlugin_schedule) begin
execute_CfuPlugin_hold <= 1'b1;
end
if(CfuPlugin_bus_cmd_ready) begin
execute_CfuPlugin_hold <= 1'b0;
end
if(CfuPlugin_bus_cmd_fire) begin
execute_CfuPlugin_fired <= 1'b1;
end
if(when_CfuPlugin_l171) begin
execute_CfuPlugin_fired <= 1'b0;
end
if(CfuPlugin_bus_rsp_valid) begin
CfuPlugin_bus_rsp_rValid <= 1'b1;
end
if(CfuPlugin_bus_rsp_rsp_ready) begin
CfuPlugin_bus_rsp_rValid <= 1'b0;
end
if(when_Pipeline_l124_61) begin
execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT;
end
if(when_Pipeline_l151) begin
execute_arbitration_isValid <= 1'b0;
end
if(when_Pipeline_l154) begin
execute_arbitration_isValid <= decode_arbitration_isValid;
end
if(when_Pipeline_l151_1) begin
memory_arbitration_isValid <= 1'b0;
end
if(when_Pipeline_l154_1) begin
memory_arbitration_isValid <= execute_arbitration_isValid;
end
if(when_Pipeline_l151_2) begin
writeBack_arbitration_isValid <= 1'b0;
end
if(when_Pipeline_l154_2) begin
writeBack_arbitration_isValid <= memory_arbitration_isValid;
end
if(execute_CsrPlugin_csr_769) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_misa_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 30];
CsrPlugin_misa_extensions <= CsrPlugin_csrMapping_writeDataSignal[25 : 0];
end
end
if(execute_CsrPlugin_csr_768) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mstatus_MPP <= CsrPlugin_csrMapping_writeDataSignal[12 : 11];
CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7];
CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3];
end
end
if(execute_CsrPlugin_csr_772) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11];
CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7];
CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3];
end
end
if(execute_CsrPlugin_csr_3008) begin
if(execute_CsrPlugin_writeEnable) begin
_zz_CsrPlugin_csrMapping_readDataInit <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(when_InstructionCache_l239) begin
if(iBusWishbone_ACK) begin
_zz_iBusWishbone_ADR <= (_zz_iBusWishbone_ADR + 3'b001);
end
end
_zz_iBus_rsp_valid <= (iBusWishbone_CYC && iBusWishbone_ACK);
if((_zz_dBus_cmd_ready_1 && _zz_dBus_cmd_ready_2)) begin
_zz_dBus_cmd_ready <= (_zz_dBus_cmd_ready + 3'b001);
if(_zz_dBus_cmd_ready_4) begin
_zz_dBus_cmd_ready <= 3'b000;
end
end
_zz_dBus_rsp_valid <= ((_zz_dBus_cmd_ready_1 && (! dBusWishbone_WE)) && dBusWishbone_ACK);
end
end
always @(posedge clk) begin
if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin
_zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload <= IBusCachedPlugin_iBusRsp_stages_1_output_payload;
end
if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin
IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit;
end
if(IBusCachedPlugin_iBusRsp_stages_2_input_ready) begin
IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit;
end
if(dataCache_1_io_mem_cmd_ready) begin
dataCache_1_io_mem_cmd_rData_wr <= dataCache_1_io_mem_cmd_payload_wr;
dataCache_1_io_mem_cmd_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached;
dataCache_1_io_mem_cmd_rData_address <= dataCache_1_io_mem_cmd_payload_address;
dataCache_1_io_mem_cmd_rData_data <= dataCache_1_io_mem_cmd_payload_data;
dataCache_1_io_mem_cmd_rData_mask <= dataCache_1_io_mem_cmd_payload_mask;
dataCache_1_io_mem_cmd_rData_size <= dataCache_1_io_mem_cmd_payload_size;
dataCache_1_io_mem_cmd_rData_last <= dataCache_1_io_mem_cmd_payload_last;
end
if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin
dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr;
dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached;
dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address;
dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data;
dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask;
dataCache_1_io_mem_cmd_s2mPipe_rData_size <= dataCache_1_io_mem_cmd_s2mPipe_payload_size;
dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last;
end
HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address;
HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data;
CsrPlugin_mip_MEIP <= externalInterrupt;
CsrPlugin_mip_MTIP <= timerInterrupt;
CsrPlugin_mip_MSIP <= softwareInterrupt;
CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001);
if(writeBack_arbitration_isFiring) begin
CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001);
end
if(_zz_when) begin
CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code);
CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr);
end
if(_zz_when_1) begin
CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code);
CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr);
end
if(DBusCachedPlugin_exceptionBus_valid) begin
CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code;
CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr;
end
if(when_CsrPlugin_l946) begin
if(when_CsrPlugin_l952) begin
CsrPlugin_interrupt_code <= 4'b0111;
CsrPlugin_interrupt_targetPrivilege <= 2'b11;
end
if(when_CsrPlugin_l952_1) begin
CsrPlugin_interrupt_code <= 4'b0011;
CsrPlugin_interrupt_targetPrivilege <= 2'b11;
end
if(when_CsrPlugin_l952_2) begin
CsrPlugin_interrupt_code <= 4'b1011;
CsrPlugin_interrupt_targetPrivilege <= 2'b11;
end
end
if(when_CsrPlugin_l1019) begin
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException);
CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause;
CsrPlugin_mepc <= writeBack_PC;
if(CsrPlugin_hadException) begin
CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr;
end
end
default : begin
end
endcase
end
if(when_MulDivIterativePlugin_l126) begin
memory_DivPlugin_div_done <= 1'b1;
end
if(when_MulDivIterativePlugin_l126_1) begin
memory_DivPlugin_div_done <= 1'b0;
end
if(when_MulDivIterativePlugin_l128) begin
if(when_MulDivIterativePlugin_l132) begin
memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator;
memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder;
if(when_MulDivIterativePlugin_l151) begin
memory_DivPlugin_div_result <= _zz_memory_DivPlugin_div_result_1[31:0];
end
end
end
if(when_MulDivIterativePlugin_l162) begin
memory_DivPlugin_accumulator <= 65'h0;
memory_DivPlugin_rs1 <= ((_zz_memory_DivPlugin_rs1 ? (~ _zz_memory_DivPlugin_rs1_1) : _zz_memory_DivPlugin_rs1_1) + _zz_memory_DivPlugin_rs1_2);
memory_DivPlugin_rs2 <= ((_zz_memory_DivPlugin_rs2 ? (~ execute_RS2) : execute_RS2) + _zz_memory_DivPlugin_rs2_1);
memory_DivPlugin_div_needRevert <= ((_zz_memory_DivPlugin_rs1 ^ (_zz_memory_DivPlugin_rs2 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13]))));
end
externalInterruptArray_regNext <= externalInterruptArray;
if(CfuPlugin_bus_rsp_ready) begin
CfuPlugin_bus_rsp_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0;
end
if(when_GenCoreDefault_l367) begin
_zz_CsrPlugin_csrMapping_readDataInit_2 <= (_zz_CsrPlugin_csrMapping_readDataInit_2 + 32'h00000001);
end
if(when_GenCoreDefault_l367_1) begin
_zz_CsrPlugin_csrMapping_readDataInit_3 <= (_zz_CsrPlugin_csrMapping_readDataInit_3 + 32'h00000001);
end
if(when_GenCoreDefault_l367_2) begin
_zz_CsrPlugin_csrMapping_readDataInit_4 <= (_zz_CsrPlugin_csrMapping_readDataInit_4 + 32'h00000001);
end
if(when_GenCoreDefault_l367_3) begin
_zz_CsrPlugin_csrMapping_readDataInit_5 <= (_zz_CsrPlugin_csrMapping_readDataInit_5 + 32'h00000001);
end
if(when_GenCoreDefault_l367_4) begin
_zz_CsrPlugin_csrMapping_readDataInit_6 <= (_zz_CsrPlugin_csrMapping_readDataInit_6 + 32'h00000001);
end
if(when_GenCoreDefault_l367_5) begin
_zz_CsrPlugin_csrMapping_readDataInit_7 <= (_zz_CsrPlugin_csrMapping_readDataInit_7 + 32'h00000001);
end
if(when_GenCoreDefault_l367_6) begin
_zz_CsrPlugin_csrMapping_readDataInit_8 <= (_zz_CsrPlugin_csrMapping_readDataInit_8 + 32'h00000001);
end
if(when_GenCoreDefault_l367_7) begin
_zz_CsrPlugin_csrMapping_readDataInit_9 <= (_zz_CsrPlugin_csrMapping_readDataInit_9 + 32'h00000001);
end
if(when_Pipeline_l124) begin
decode_to_execute_PC <= decode_PC;
end
if(when_Pipeline_l124_1) begin
execute_to_memory_PC <= _zz_execute_SRC2;
end
if(when_Pipeline_l124_2) begin
memory_to_writeBack_PC <= memory_PC;
end
if(when_Pipeline_l124_3) begin
decode_to_execute_INSTRUCTION <= decode_INSTRUCTION;
end
if(when_Pipeline_l124_4) begin
execute_to_memory_INSTRUCTION <= execute_INSTRUCTION;
end
if(when_Pipeline_l124_5) begin
memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION;
end
if(when_Pipeline_l124_6) begin
decode_to_execute_FORMAL_PC_NEXT <= _zz_decode_to_execute_FORMAL_PC_NEXT;
end
if(when_Pipeline_l124_7) begin
execute_to_memory_FORMAL_PC_NEXT <= _zz_execute_to_memory_FORMAL_PC_NEXT;
end
if(when_Pipeline_l124_8) begin
memory_to_writeBack_FORMAL_PC_NEXT <= memory_FORMAL_PC_NEXT;
end
if(when_Pipeline_l124_9) begin
decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY;
end
if(when_Pipeline_l124_10) begin
decode_to_execute_SRC1_CTRL <= _zz_decode_to_execute_SRC1_CTRL;
end
if(when_Pipeline_l124_11) begin
decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS;
end
if(when_Pipeline_l124_12) begin
decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE;
end
if(when_Pipeline_l124_13) begin
execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE;
end
if(when_Pipeline_l124_14) begin
memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE;
end
if(when_Pipeline_l124_15) begin
decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL;
end
if(when_Pipeline_l124_16) begin
decode_to_execute_SRC2_CTRL <= _zz_decode_to_execute_SRC2_CTRL;
end
if(when_Pipeline_l124_17) begin
decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID;
end
if(when_Pipeline_l124_18) begin
execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID;
end
if(when_Pipeline_l124_19) begin
memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID;
end
if(when_Pipeline_l124_20) begin
decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE;
end
if(when_Pipeline_l124_21) begin
decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE;
end
if(when_Pipeline_l124_22) begin
execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE;
end
if(when_Pipeline_l124_23) begin
decode_to_execute_MEMORY_WR <= decode_MEMORY_WR;
end
if(when_Pipeline_l124_24) begin
execute_to_memory_MEMORY_WR <= execute_MEMORY_WR;
end
if(when_Pipeline_l124_25) begin
memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR;
end
if(when_Pipeline_l124_26) begin
decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT;
end
if(when_Pipeline_l124_27) begin
decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED;
end
if(when_Pipeline_l124_28) begin
decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL;
end
if(when_Pipeline_l124_29) begin
decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL;
end
if(when_Pipeline_l124_30) begin
execute_to_memory_SHIFT_CTRL <= _zz_execute_to_memory_SHIFT_CTRL;
end
if(when_Pipeline_l124_31) begin
decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL;
end
if(when_Pipeline_l124_32) begin
decode_to_execute_IS_CSR <= decode_IS_CSR;
end
if(when_Pipeline_l124_33) begin
decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL;
end
if(when_Pipeline_l124_34) begin
execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL;
end
if(when_Pipeline_l124_35) begin
memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL;
end
if(when_Pipeline_l124_36) begin
decode_to_execute_IS_MUL <= decode_IS_MUL;
end
if(when_Pipeline_l124_37) begin
execute_to_memory_IS_MUL <= execute_IS_MUL;
end
if(when_Pipeline_l124_38) begin
memory_to_writeBack_IS_MUL <= memory_IS_MUL;
end
if(when_Pipeline_l124_39) begin
decode_to_execute_IS_DIV <= decode_IS_DIV;
end
if(when_Pipeline_l124_40) begin
execute_to_memory_IS_DIV <= execute_IS_DIV;
end
if(when_Pipeline_l124_41) begin
decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED;
end
if(when_Pipeline_l124_42) begin
decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED;
end
if(when_Pipeline_l124_43) begin
decode_to_execute_CfuPlugin_CFU_ENABLE <= decode_CfuPlugin_CFU_ENABLE;
end
if(when_Pipeline_l124_44) begin
decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND <= _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND;
end
if(when_Pipeline_l124_45) begin
decode_to_execute_RS1 <= decode_RS1;
end
if(when_Pipeline_l124_46) begin
decode_to_execute_RS2 <= decode_RS2;
end
if(when_Pipeline_l124_47) begin
decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO;
end
if(when_Pipeline_l124_48) begin
decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2;
end
if(when_Pipeline_l124_49) begin
decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE;
end
if(when_Pipeline_l124_50) begin
decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE;
end
if(when_Pipeline_l124_51) begin
execute_to_memory_MEMORY_STORE_DATA_RF <= execute_MEMORY_STORE_DATA_RF;
end
if(when_Pipeline_l124_52) begin
memory_to_writeBack_MEMORY_STORE_DATA_RF <= memory_MEMORY_STORE_DATA_RF;
end
if(when_Pipeline_l124_53) begin
execute_to_memory_REGFILE_WRITE_DATA <= _zz_decode_RS2;
end
if(when_Pipeline_l124_54) begin
memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_decode_RS2_1;
end
if(when_Pipeline_l124_55) begin
execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT;
end
if(when_Pipeline_l124_56) begin
execute_to_memory_MUL_LL <= execute_MUL_LL;
end
if(when_Pipeline_l124_57) begin
execute_to_memory_MUL_LH <= execute_MUL_LH;
end
if(when_Pipeline_l124_58) begin
execute_to_memory_MUL_HL <= execute_MUL_HL;
end
if(when_Pipeline_l124_59) begin
execute_to_memory_MUL_HH <= execute_MUL_HH;
end
if(when_Pipeline_l124_60) begin
memory_to_writeBack_MUL_HH <= memory_MUL_HH;
end
if(when_Pipeline_l124_62) begin
memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT <= _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT;
end
if(when_Pipeline_l124_63) begin
memory_to_writeBack_MUL_LOW <= memory_MUL_LOW;
end
if(when_CsrPlugin_l1264) begin
execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0);
end
if(when_CsrPlugin_l1264_1) begin
execute_CsrPlugin_csr_3857 <= (decode_INSTRUCTION[31 : 20] == 12'hf11);
end
if(when_CsrPlugin_l1264_2) begin
execute_CsrPlugin_csr_3858 <= (decode_INSTRUCTION[31 : 20] == 12'hf12);
end
if(when_CsrPlugin_l1264_3) begin
execute_CsrPlugin_csr_3859 <= (decode_INSTRUCTION[31 : 20] == 12'hf13);
end
if(when_CsrPlugin_l1264_4) begin
execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14);
end
if(when_CsrPlugin_l1264_5) begin
execute_CsrPlugin_csr_769 <= (decode_INSTRUCTION[31 : 20] == 12'h301);
end
if(when_CsrPlugin_l1264_6) begin
execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300);
end
if(when_CsrPlugin_l1264_7) begin
execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344);
end
if(when_CsrPlugin_l1264_8) begin
execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304);
end
if(when_CsrPlugin_l1264_9) begin
execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305);
end
if(when_CsrPlugin_l1264_10) begin
execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341);
end
if(when_CsrPlugin_l1264_11) begin
execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340);
end
if(when_CsrPlugin_l1264_12) begin
execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342);
end
if(when_CsrPlugin_l1264_13) begin
execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343);
end
if(when_CsrPlugin_l1264_14) begin
execute_CsrPlugin_csr_2816 <= (decode_INSTRUCTION[31 : 20] == 12'hb00);
end
if(when_CsrPlugin_l1264_15) begin
execute_CsrPlugin_csr_2944 <= (decode_INSTRUCTION[31 : 20] == 12'hb80);
end
if(when_CsrPlugin_l1264_16) begin
execute_CsrPlugin_csr_2818 <= (decode_INSTRUCTION[31 : 20] == 12'hb02);
end
if(when_CsrPlugin_l1264_17) begin
execute_CsrPlugin_csr_2946 <= (decode_INSTRUCTION[31 : 20] == 12'hb82);
end
if(when_CsrPlugin_l1264_18) begin
execute_CsrPlugin_csr_3072 <= (decode_INSTRUCTION[31 : 20] == 12'hc00);
end
if(when_CsrPlugin_l1264_19) begin
execute_CsrPlugin_csr_3200 <= (decode_INSTRUCTION[31 : 20] == 12'hc80);
end
if(when_CsrPlugin_l1264_20) begin
execute_CsrPlugin_csr_3074 <= (decode_INSTRUCTION[31 : 20] == 12'hc02);
end
if(when_CsrPlugin_l1264_21) begin
execute_CsrPlugin_csr_3202 <= (decode_INSTRUCTION[31 : 20] == 12'hc82);
end
if(when_CsrPlugin_l1264_22) begin
execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0);
end
if(when_CsrPlugin_l1264_23) begin
execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0);
end
if(when_CsrPlugin_l1264_24) begin
execute_CsrPlugin_csr_2820 <= (decode_INSTRUCTION[31 : 20] == 12'hb04);
end
if(when_CsrPlugin_l1264_25) begin
execute_CsrPlugin_csr_2821 <= (decode_INSTRUCTION[31 : 20] == 12'hb05);
end
if(when_CsrPlugin_l1264_26) begin
execute_CsrPlugin_csr_2822 <= (decode_INSTRUCTION[31 : 20] == 12'hb06);
end
if(when_CsrPlugin_l1264_27) begin
execute_CsrPlugin_csr_2823 <= (decode_INSTRUCTION[31 : 20] == 12'hb07);
end
if(when_CsrPlugin_l1264_28) begin
execute_CsrPlugin_csr_2824 <= (decode_INSTRUCTION[31 : 20] == 12'hb08);
end
if(when_CsrPlugin_l1264_29) begin
execute_CsrPlugin_csr_2825 <= (decode_INSTRUCTION[31 : 20] == 12'hb09);
end
if(when_CsrPlugin_l1264_30) begin
execute_CsrPlugin_csr_2826 <= (decode_INSTRUCTION[31 : 20] == 12'hb0a);
end
if(when_CsrPlugin_l1264_31) begin
execute_CsrPlugin_csr_2827 <= (decode_INSTRUCTION[31 : 20] == 12'hb0b);
end
if(when_CsrPlugin_l1264_32) begin
execute_CsrPlugin_csr_2828 <= (decode_INSTRUCTION[31 : 20] == 12'hb0c);
end
if(when_CsrPlugin_l1264_33) begin
execute_CsrPlugin_csr_2829 <= (decode_INSTRUCTION[31 : 20] == 12'hb0d);
end
if(when_CsrPlugin_l1264_34) begin
execute_CsrPlugin_csr_2830 <= (decode_INSTRUCTION[31 : 20] == 12'hb0e);
end
if(when_CsrPlugin_l1264_35) begin
execute_CsrPlugin_csr_2831 <= (decode_INSTRUCTION[31 : 20] == 12'hb0f);
end
if(when_CsrPlugin_l1264_36) begin
execute_CsrPlugin_csr_2832 <= (decode_INSTRUCTION[31 : 20] == 12'hb10);
end
if(when_CsrPlugin_l1264_37) begin
execute_CsrPlugin_csr_2833 <= (decode_INSTRUCTION[31 : 20] == 12'hb11);
end
if(when_CsrPlugin_l1264_38) begin
execute_CsrPlugin_csr_2834 <= (decode_INSTRUCTION[31 : 20] == 12'hb12);
end
if(when_CsrPlugin_l1264_39) begin
execute_CsrPlugin_csr_2835 <= (decode_INSTRUCTION[31 : 20] == 12'hb13);
end
if(execute_CsrPlugin_csr_836) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3];
end
end
if(execute_CsrPlugin_csr_773) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mtvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2];
CsrPlugin_mtvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0];
end
end
if(execute_CsrPlugin_csr_833) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_832) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mscratch <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_834) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mcause_interrupt <= CsrPlugin_csrMapping_writeDataSignal[31];
CsrPlugin_mcause_exceptionCode <= CsrPlugin_csrMapping_writeDataSignal[3 : 0];
end
end
if(execute_CsrPlugin_csr_835) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mtval <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2816) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mcycle[31 : 0] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2944) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mcycle[63 : 32] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2818) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_minstret[31 : 0] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2946) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_minstret[63 : 32] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2820) begin
if(execute_CsrPlugin_writeEnable) begin
_zz_CsrPlugin_csrMapping_readDataInit_2 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2821) begin
if(execute_CsrPlugin_writeEnable) begin
_zz_when_GenCoreDefault_l367 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2822) begin
if(execute_CsrPlugin_writeEnable) begin
_zz_CsrPlugin_csrMapping_readDataInit_3 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2823) begin
if(execute_CsrPlugin_writeEnable) begin
_zz_when_GenCoreDefault_l367_1 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2824) begin
if(execute_CsrPlugin_writeEnable) begin
_zz_CsrPlugin_csrMapping_readDataInit_4 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2825) begin
if(execute_CsrPlugin_writeEnable) begin
_zz_when_GenCoreDefault_l367_2 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2826) begin
if(execute_CsrPlugin_writeEnable) begin
_zz_CsrPlugin_csrMapping_readDataInit_5 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2827) begin
if(execute_CsrPlugin_writeEnable) begin
_zz_when_GenCoreDefault_l367_3 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2828) begin
if(execute_CsrPlugin_writeEnable) begin
_zz_CsrPlugin_csrMapping_readDataInit_6 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2829) begin
if(execute_CsrPlugin_writeEnable) begin
_zz_when_GenCoreDefault_l367_4 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2830) begin
if(execute_CsrPlugin_writeEnable) begin
_zz_CsrPlugin_csrMapping_readDataInit_7 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2831) begin
if(execute_CsrPlugin_writeEnable) begin
_zz_when_GenCoreDefault_l367_5 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2832) begin
if(execute_CsrPlugin_writeEnable) begin
_zz_CsrPlugin_csrMapping_readDataInit_8 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2833) begin
if(execute_CsrPlugin_writeEnable) begin
_zz_when_GenCoreDefault_l367_6 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2834) begin
if(execute_CsrPlugin_writeEnable) begin
_zz_CsrPlugin_csrMapping_readDataInit_9 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2835) begin
if(execute_CsrPlugin_writeEnable) begin
_zz_when_GenCoreDefault_l367_7 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO;
dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO;
end
endmodule
module DataCache (
input io_cpu_execute_isValid,
input [31:0] io_cpu_execute_address,
output reg io_cpu_execute_haltIt,
input io_cpu_execute_args_wr,
input [1:0] io_cpu_execute_args_size,
input io_cpu_execute_args_totalyConsistent,
output io_cpu_execute_refilling,
input io_cpu_memory_isValid,
input io_cpu_memory_isStuck,
output io_cpu_memory_isWrite,
input [31:0] io_cpu_memory_address,
input [31:0] io_cpu_memory_mmuRsp_physicalAddress,
input io_cpu_memory_mmuRsp_isIoAccess,
input io_cpu_memory_mmuRsp_isPaging,
input io_cpu_memory_mmuRsp_allowRead,
input io_cpu_memory_mmuRsp_allowWrite,
input io_cpu_memory_mmuRsp_allowExecute,
input io_cpu_memory_mmuRsp_exception,
input io_cpu_memory_mmuRsp_refilling,
input io_cpu_memory_mmuRsp_bypassTranslation,
input io_cpu_writeBack_isValid,
input io_cpu_writeBack_isStuck,
input io_cpu_writeBack_isUser,
output reg io_cpu_writeBack_haltIt,
output io_cpu_writeBack_isWrite,
input [31:0] io_cpu_writeBack_storeData,
output reg [31:0] io_cpu_writeBack_data,
input [31:0] io_cpu_writeBack_address,
output io_cpu_writeBack_mmuException,
output io_cpu_writeBack_unalignedAccess,
output reg io_cpu_writeBack_accessError,
output io_cpu_writeBack_keepMemRspData,
input io_cpu_writeBack_fence_SW,
input io_cpu_writeBack_fence_SR,
input io_cpu_writeBack_fence_SO,
input io_cpu_writeBack_fence_SI,
input io_cpu_writeBack_fence_PW,
input io_cpu_writeBack_fence_PR,
input io_cpu_writeBack_fence_PO,
input io_cpu_writeBack_fence_PI,
input [3:0] io_cpu_writeBack_fence_FM,
output io_cpu_writeBack_exclusiveOk,
output reg io_cpu_redo,
input io_cpu_flush_valid,
output io_cpu_flush_ready,
output reg io_mem_cmd_valid,
input io_mem_cmd_ready,
output reg io_mem_cmd_payload_wr,
output io_mem_cmd_payload_uncached,
output reg [31:0] io_mem_cmd_payload_address,
output [31:0] io_mem_cmd_payload_data,
output [3:0] io_mem_cmd_payload_mask,
output reg [2:0] io_mem_cmd_payload_size,
output io_mem_cmd_payload_last,
input io_mem_rsp_valid,
input io_mem_rsp_payload_last,
input [31:0] io_mem_rsp_payload_data,
input io_mem_rsp_payload_error,
input clk,
input reset
);
reg [20:0] _zz_ways_0_tags_port0;
reg [31:0] _zz_ways_0_data_port0;
wire [20:0] _zz_ways_0_tags_port;
wire [10:0] _zz_stage0_dataColisions;
wire [10:0] _zz__zz_stageA_dataColisions;
wire [0:0] _zz_when;
wire [2:0] _zz_loader_counter_valueNext;
wire [0:0] _zz_loader_counter_valueNext_1;
wire [1:0] _zz_loader_waysAllocator;
reg _zz_1;
reg _zz_2;
wire haltCpu;
reg tagsReadCmd_valid;
reg [7:0] tagsReadCmd_payload;
reg tagsWriteCmd_valid;
reg [0:0] tagsWriteCmd_payload_way;
reg [7:0] tagsWriteCmd_payload_address;
reg tagsWriteCmd_payload_data_valid;
reg tagsWriteCmd_payload_data_error;
reg [18:0] tagsWriteCmd_payload_data_address;
reg tagsWriteLastCmd_valid;
reg [0:0] tagsWriteLastCmd_payload_way;
reg [7:0] tagsWriteLastCmd_payload_address;
reg tagsWriteLastCmd_payload_data_valid;
reg tagsWriteLastCmd_payload_data_error;
reg [18:0] tagsWriteLastCmd_payload_data_address;
reg dataReadCmd_valid;
reg [10:0] dataReadCmd_payload;
reg dataWriteCmd_valid;
reg [0:0] dataWriteCmd_payload_way;
reg [10:0] dataWriteCmd_payload_address;
reg [31:0] dataWriteCmd_payload_data;
reg [3:0] dataWriteCmd_payload_mask;
wire _zz_ways_0_tagsReadRsp_valid;
wire ways_0_tagsReadRsp_valid;
wire ways_0_tagsReadRsp_error;
wire [18:0] ways_0_tagsReadRsp_address;
wire [20:0] _zz_ways_0_tagsReadRsp_valid_1;
wire _zz_ways_0_dataReadRspMem;
wire [31:0] ways_0_dataReadRspMem;
wire [31:0] ways_0_dataReadRsp;
wire when_DataCache_l634;
wire when_DataCache_l637;
wire when_DataCache_l656;
wire rspSync;
wire rspLast;
reg memCmdSent;
wire io_mem_cmd_fire;
wire when_DataCache_l678;
reg [3:0] _zz_stage0_mask;
wire [3:0] stage0_mask;
wire [0:0] stage0_dataColisions;
wire [0:0] stage0_wayInvalidate;
wire stage0_isAmo;
wire when_DataCache_l763;
reg stageA_request_wr;
reg [1:0] stageA_request_size;
reg stageA_request_totalyConsistent;
wire when_DataCache_l763_1;
reg [3:0] stageA_mask;
wire stageA_isAmo;
wire stageA_isLrsc;
wire [0:0] stageA_wayHits;
wire when_DataCache_l763_2;
reg [0:0] stageA_wayInvalidate;
wire when_DataCache_l763_3;
reg [0:0] stage0_dataColisions_regNextWhen;
wire [0:0] _zz_stageA_dataColisions;
wire [0:0] stageA_dataColisions;
wire when_DataCache_l814;
reg stageB_request_wr;
reg [1:0] stageB_request_size;
reg stageB_request_totalyConsistent;
reg stageB_mmuRspFreeze;
wire when_DataCache_l816;
reg [31:0] stageB_mmuRsp_physicalAddress;
reg stageB_mmuRsp_isIoAccess;
reg stageB_mmuRsp_isPaging;
reg stageB_mmuRsp_allowRead;
reg stageB_mmuRsp_allowWrite;
reg stageB_mmuRsp_allowExecute;
reg stageB_mmuRsp_exception;
reg stageB_mmuRsp_refilling;
reg stageB_mmuRsp_bypassTranslation;
wire when_DataCache_l813;
reg stageB_tagsReadRsp_0_valid;
reg stageB_tagsReadRsp_0_error;
reg [18:0] stageB_tagsReadRsp_0_address;
wire when_DataCache_l813_1;
reg [31:0] stageB_dataReadRsp_0;
wire when_DataCache_l812;
reg [0:0] stageB_wayInvalidate;
wire stageB_consistancyHazard;
wire when_DataCache_l812_1;
reg [0:0] stageB_dataColisions;
wire when_DataCache_l812_2;
reg stageB_unaligned;
wire when_DataCache_l812_3;
reg [0:0] stageB_waysHitsBeforeInvalidate;
wire [0:0] stageB_waysHits;
wire stageB_waysHit;
wire [31:0] stageB_dataMux;
wire when_DataCache_l812_4;
reg [3:0] stageB_mask;
reg stageB_loaderValid;
wire [31:0] stageB_ioMemRspMuxed;
reg stageB_flusher_waitDone;
wire stageB_flusher_hold;
reg [8:0] stageB_flusher_counter;
wire when_DataCache_l842;
wire when_DataCache_l848;
reg stageB_flusher_start;
wire stageB_isAmo;
wire stageB_isAmoCached;
wire stageB_isExternalLsrc;
wire stageB_isExternalAmo;
wire [31:0] stageB_requestDataBypass;
reg stageB_cpuWriteToCache;
wire when_DataCache_l911;
wire stageB_badPermissions;
wire stageB_loadStoreFault;
wire stageB_bypassCache;
wire when_DataCache_l980;
wire when_DataCache_l989;
wire when_DataCache_l994;
wire when_DataCache_l1005;
wire when_DataCache_l1017;
wire when_DataCache_l976;
wire when_DataCache_l1051;
wire when_DataCache_l1060;
reg loader_valid;
reg loader_counter_willIncrement;
wire loader_counter_willClear;
reg [2:0] loader_counter_valueNext;
reg [2:0] loader_counter_value;
wire loader_counter_willOverflowIfInc;
wire loader_counter_willOverflow;
reg [0:0] loader_waysAllocator;
reg loader_error;
wire loader_kill;
reg loader_killReg;
wire when_DataCache_l1075;
wire loader_done;
wire when_DataCache_l1103;
reg loader_valid_regNext;
wire when_DataCache_l1107;
wire when_DataCache_l1110;
(* ram_style = "block" *) reg [20:0] ways_0_tags [0:255];
(* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:2047];
(* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:2047];
(* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:2047];
(* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:2047];
reg [7:0] _zz_ways_0_datasymbol_read;
reg [7:0] _zz_ways_0_datasymbol_read_1;
reg [7:0] _zz_ways_0_datasymbol_read_2;
reg [7:0] _zz_ways_0_datasymbol_read_3;
assign _zz_stage0_dataColisions = (io_cpu_execute_address[12 : 2] >>> 0);
assign _zz__zz_stageA_dataColisions = (io_cpu_memory_address[12 : 2] >>> 0);
assign _zz_when = 1'b1;
assign _zz_loader_counter_valueNext_1 = loader_counter_willIncrement;
assign _zz_loader_counter_valueNext = {2'd0, _zz_loader_counter_valueNext_1};
assign _zz_loader_waysAllocator = {loader_waysAllocator,loader_waysAllocator[0]};
assign _zz_ways_0_tags_port = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}};
always @(posedge clk) begin
if(_zz_ways_0_tagsReadRsp_valid) begin
_zz_ways_0_tags_port0 <= ways_0_tags[tagsReadCmd_payload];
end
end
always @(posedge clk) begin
if(_zz_2) begin
ways_0_tags[tagsWriteCmd_payload_address] <= _zz_ways_0_tags_port;
end
end
always @(*) begin
_zz_ways_0_data_port0 = {_zz_ways_0_datasymbol_read_3, _zz_ways_0_datasymbol_read_2, _zz_ways_0_datasymbol_read_1, _zz_ways_0_datasymbol_read};
end
always @(posedge clk) begin
if(_zz_ways_0_dataReadRspMem) begin
_zz_ways_0_datasymbol_read <= ways_0_data_symbol0[dataReadCmd_payload];
_zz_ways_0_datasymbol_read_1 <= ways_0_data_symbol1[dataReadCmd_payload];
_zz_ways_0_datasymbol_read_2 <= ways_0_data_symbol2[dataReadCmd_payload];
_zz_ways_0_datasymbol_read_3 <= ways_0_data_symbol3[dataReadCmd_payload];
end
end
always @(posedge clk) begin
if(dataWriteCmd_payload_mask[0] && _zz_1) begin
ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0];
end
if(dataWriteCmd_payload_mask[1] && _zz_1) begin
ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8];
end
if(dataWriteCmd_payload_mask[2] && _zz_1) begin
ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16];
end
if(dataWriteCmd_payload_mask[3] && _zz_1) begin
ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24];
end
end
always @(*) begin
_zz_1 = 1'b0;
if(when_DataCache_l637) begin
_zz_1 = 1'b1;
end
end
always @(*) begin
_zz_2 = 1'b0;
if(when_DataCache_l634) begin
_zz_2 = 1'b1;
end
end
assign haltCpu = 1'b0;
assign _zz_ways_0_tagsReadRsp_valid = (tagsReadCmd_valid && (! io_cpu_memory_isStuck));
assign _zz_ways_0_tagsReadRsp_valid_1 = _zz_ways_0_tags_port0;
assign ways_0_tagsReadRsp_valid = _zz_ways_0_tagsReadRsp_valid_1[0];
assign ways_0_tagsReadRsp_error = _zz_ways_0_tagsReadRsp_valid_1[1];
assign ways_0_tagsReadRsp_address = _zz_ways_0_tagsReadRsp_valid_1[20 : 2];
assign _zz_ways_0_dataReadRspMem = (dataReadCmd_valid && (! io_cpu_memory_isStuck));
assign ways_0_dataReadRspMem = _zz_ways_0_data_port0;
assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0];
assign when_DataCache_l634 = (tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]);
assign when_DataCache_l637 = (dataWriteCmd_valid && dataWriteCmd_payload_way[0]);
always @(*) begin
tagsReadCmd_valid = 1'b0;
if(when_DataCache_l656) begin
tagsReadCmd_valid = 1'b1;
end
end
always @(*) begin
tagsReadCmd_payload = 8'bxxxxxxxx;
if(when_DataCache_l656) begin
tagsReadCmd_payload = io_cpu_execute_address[12 : 5];
end
end
always @(*) begin
dataReadCmd_valid = 1'b0;
if(when_DataCache_l656) begin
dataReadCmd_valid = 1'b1;
end
end
always @(*) begin
dataReadCmd_payload = 11'bxxxxxxxxxxx;
if(when_DataCache_l656) begin
dataReadCmd_payload = io_cpu_execute_address[12 : 2];
end
end
always @(*) begin
tagsWriteCmd_valid = 1'b0;
if(when_DataCache_l842) begin
tagsWriteCmd_valid = 1'b1;
end
if(when_DataCache_l1051) begin
tagsWriteCmd_valid = 1'b0;
end
if(loader_done) begin
tagsWriteCmd_valid = 1'b1;
end
end
always @(*) begin
tagsWriteCmd_payload_way = 1'bx;
if(when_DataCache_l842) begin
tagsWriteCmd_payload_way = 1'b1;
end
if(loader_done) begin
tagsWriteCmd_payload_way = loader_waysAllocator;
end
end
always @(*) begin
tagsWriteCmd_payload_address = 8'bxxxxxxxx;
if(when_DataCache_l842) begin
tagsWriteCmd_payload_address = stageB_flusher_counter[7:0];
end
if(loader_done) begin
tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[12 : 5];
end
end
always @(*) begin
tagsWriteCmd_payload_data_valid = 1'bx;
if(when_DataCache_l842) begin
tagsWriteCmd_payload_data_valid = 1'b0;
end
if(loader_done) begin
tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg));
end
end
always @(*) begin
tagsWriteCmd_payload_data_error = 1'bx;
if(loader_done) begin
tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error));
end
end
always @(*) begin
tagsWriteCmd_payload_data_address = 19'bxxxxxxxxxxxxxxxxxxx;
if(loader_done) begin
tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 13];
end
end
always @(*) begin
dataWriteCmd_valid = 1'b0;
if(stageB_cpuWriteToCache) begin
if(when_DataCache_l911) begin
dataWriteCmd_valid = 1'b1;
end
end
if(when_DataCache_l1051) begin
dataWriteCmd_valid = 1'b0;
end
if(when_DataCache_l1075) begin
dataWriteCmd_valid = 1'b1;
end
end
always @(*) begin
dataWriteCmd_payload_way = 1'bx;
if(stageB_cpuWriteToCache) begin
dataWriteCmd_payload_way = stageB_waysHits;
end
if(when_DataCache_l1075) begin
dataWriteCmd_payload_way = loader_waysAllocator;
end
end
always @(*) begin
dataWriteCmd_payload_address = 11'bxxxxxxxxxxx;
if(stageB_cpuWriteToCache) begin
dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[12 : 2];
end
if(when_DataCache_l1075) begin
dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[12 : 5],loader_counter_value};
end
end
always @(*) begin
dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
if(stageB_cpuWriteToCache) begin
dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass;
end
if(when_DataCache_l1075) begin
dataWriteCmd_payload_data = io_mem_rsp_payload_data;
end
end
always @(*) begin
dataWriteCmd_payload_mask = 4'bxxxx;
if(stageB_cpuWriteToCache) begin
dataWriteCmd_payload_mask = 4'b0000;
if(_zz_when[0]) begin
dataWriteCmd_payload_mask[3 : 0] = stageB_mask;
end
end
if(when_DataCache_l1075) begin
dataWriteCmd_payload_mask = 4'b1111;
end
end
assign when_DataCache_l656 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck));
always @(*) begin
io_cpu_execute_haltIt = 1'b0;
if(when_DataCache_l842) begin
io_cpu_execute_haltIt = 1'b1;
end
end
assign rspSync = 1'b1;
assign rspLast = 1'b1;
assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready);
assign when_DataCache_l678 = (! io_cpu_writeBack_isStuck);
always @(*) begin
_zz_stage0_mask = 4'bxxxx;
case(io_cpu_execute_args_size)
2'b00 : begin
_zz_stage0_mask = 4'b0001;
end
2'b01 : begin
_zz_stage0_mask = 4'b0011;
end
2'b10 : begin
_zz_stage0_mask = 4'b1111;
end
default : begin
end
endcase
end
assign stage0_mask = (_zz_stage0_mask <<< io_cpu_execute_address[1 : 0]);
assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_stage0_dataColisions)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000));
assign stage0_wayInvalidate = 1'b0;
assign stage0_isAmo = 1'b0;
assign when_DataCache_l763 = (! io_cpu_memory_isStuck);
assign when_DataCache_l763_1 = (! io_cpu_memory_isStuck);
assign io_cpu_memory_isWrite = stageA_request_wr;
assign stageA_isAmo = 1'b0;
assign stageA_isLrsc = 1'b0;
assign stageA_wayHits = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 13] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid);
assign when_DataCache_l763_2 = (! io_cpu_memory_isStuck);
assign when_DataCache_l763_3 = (! io_cpu_memory_isStuck);
assign _zz_stageA_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz__zz_stageA_dataColisions)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000));
assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_stageA_dataColisions);
assign when_DataCache_l814 = (! io_cpu_writeBack_isStuck);
always @(*) begin
stageB_mmuRspFreeze = 1'b0;
if(when_DataCache_l1110) begin
stageB_mmuRspFreeze = 1'b1;
end
end
assign when_DataCache_l816 = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze));
assign when_DataCache_l813 = (! io_cpu_writeBack_isStuck);
assign when_DataCache_l813_1 = (! io_cpu_writeBack_isStuck);
assign when_DataCache_l812 = (! io_cpu_writeBack_isStuck);
assign stageB_consistancyHazard = 1'b0;
assign when_DataCache_l812_1 = (! io_cpu_writeBack_isStuck);
assign when_DataCache_l812_2 = (! io_cpu_writeBack_isStuck);
assign when_DataCache_l812_3 = (! io_cpu_writeBack_isStuck);
assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate));
assign stageB_waysHit = (stageB_waysHits != 1'b0);
assign stageB_dataMux = stageB_dataReadRsp_0;
assign when_DataCache_l812_4 = (! io_cpu_writeBack_isStuck);
always @(*) begin
stageB_loaderValid = 1'b0;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(!when_DataCache_l989) begin
if(io_mem_cmd_ready) begin
stageB_loaderValid = 1'b1;
end
end
end
end
end
if(when_DataCache_l1051) begin
stageB_loaderValid = 1'b0;
end
end
assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0];
always @(*) begin
io_cpu_writeBack_haltIt = 1'b1;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(when_DataCache_l976) begin
if(when_DataCache_l980) begin
io_cpu_writeBack_haltIt = 1'b0;
end
end else begin
if(when_DataCache_l989) begin
if(when_DataCache_l994) begin
io_cpu_writeBack_haltIt = 1'b0;
end
end
end
end
end
if(when_DataCache_l1051) begin
io_cpu_writeBack_haltIt = 1'b0;
end
end
assign stageB_flusher_hold = 1'b0;
assign when_DataCache_l842 = (! stageB_flusher_counter[8]);
assign when_DataCache_l848 = (! stageB_flusher_hold);
assign io_cpu_flush_ready = (stageB_flusher_waitDone && stageB_flusher_counter[8]);
assign stageB_isAmo = 1'b0;
assign stageB_isAmoCached = 1'b0;
assign stageB_isExternalLsrc = 1'b0;
assign stageB_isExternalAmo = 1'b0;
assign stageB_requestDataBypass = io_cpu_writeBack_storeData;
always @(*) begin
stageB_cpuWriteToCache = 1'b0;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(when_DataCache_l989) begin
stageB_cpuWriteToCache = 1'b1;
end
end
end
end
end
assign when_DataCache_l911 = (stageB_request_wr && stageB_waysHit);
assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo)));
assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions));
always @(*) begin
io_cpu_redo = 1'b0;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(when_DataCache_l989) begin
if(when_DataCache_l1005) begin
io_cpu_redo = 1'b1;
end
end
end
end
end
if(when_DataCache_l1060) begin
io_cpu_redo = 1'b1;
end
if(when_DataCache_l1107) begin
io_cpu_redo = 1'b1;
end
end
always @(*) begin
io_cpu_writeBack_accessError = 1'b0;
if(stageB_bypassCache) begin
io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error);
end else begin
io_cpu_writeBack_accessError = (((stageB_waysHits & stageB_tagsReadRsp_0_error) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging)));
end
end
assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging);
assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned);
assign io_cpu_writeBack_isWrite = stageB_request_wr;
always @(*) begin
io_mem_cmd_valid = 1'b0;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(when_DataCache_l976) begin
io_mem_cmd_valid = (! memCmdSent);
end else begin
if(when_DataCache_l989) begin
if(stageB_request_wr) begin
io_mem_cmd_valid = 1'b1;
end
end else begin
if(when_DataCache_l1017) begin
io_mem_cmd_valid = 1'b1;
end
end
end
end
end
if(when_DataCache_l1051) begin
io_mem_cmd_valid = 1'b0;
end
end
always @(*) begin
io_mem_cmd_payload_address = stageB_mmuRsp_physicalAddress;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(!when_DataCache_l989) begin
io_mem_cmd_payload_address[4 : 0] = 5'h0;
end
end
end
end
end
assign io_mem_cmd_payload_last = 1'b1;
always @(*) begin
io_mem_cmd_payload_wr = stageB_request_wr;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(!when_DataCache_l989) begin
io_mem_cmd_payload_wr = 1'b0;
end
end
end
end
end
assign io_mem_cmd_payload_mask = stageB_mask;
assign io_mem_cmd_payload_data = stageB_requestDataBypass;
assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess;
always @(*) begin
io_mem_cmd_payload_size = {1'd0, stageB_request_size};
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(!when_DataCache_l989) begin
io_mem_cmd_payload_size = 3'b101;
end
end
end
end
end
assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo);
assign io_cpu_writeBack_keepMemRspData = 1'b0;
assign when_DataCache_l980 = ((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready);
assign when_DataCache_l989 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached)));
assign when_DataCache_l994 = ((! stageB_request_wr) || io_mem_cmd_ready);
assign when_DataCache_l1005 = (((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0));
assign when_DataCache_l1017 = (! memCmdSent);
assign when_DataCache_l976 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc);
always @(*) begin
if(stageB_bypassCache) begin
io_cpu_writeBack_data = stageB_ioMemRspMuxed;
end else begin
io_cpu_writeBack_data = stageB_dataMux;
end
end
assign when_DataCache_l1051 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess);
assign when_DataCache_l1060 = (io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard));
always @(*) begin
loader_counter_willIncrement = 1'b0;
if(when_DataCache_l1075) begin
loader_counter_willIncrement = 1'b1;
end
end
assign loader_counter_willClear = 1'b0;
assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111);
assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement);
always @(*) begin
loader_counter_valueNext = (loader_counter_value + _zz_loader_counter_valueNext);
if(loader_counter_willClear) begin
loader_counter_valueNext = 3'b000;
end
end
assign loader_kill = 1'b0;
assign when_DataCache_l1075 = ((loader_valid && io_mem_rsp_valid) && rspLast);
assign loader_done = loader_counter_willOverflow;
assign when_DataCache_l1103 = (! loader_valid);
assign when_DataCache_l1107 = (loader_valid && (! loader_valid_regNext));
assign io_cpu_execute_refilling = loader_valid;
assign when_DataCache_l1110 = (stageB_loaderValid || loader_valid);
always @(posedge clk) begin
tagsWriteLastCmd_valid <= tagsWriteCmd_valid;
tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way;
tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address;
tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid;
tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error;
tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address;
if(when_DataCache_l763) begin
stageA_request_wr <= io_cpu_execute_args_wr;
stageA_request_size <= io_cpu_execute_args_size;
stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent;
end
if(when_DataCache_l763_1) begin
stageA_mask <= stage0_mask;
end
if(when_DataCache_l763_2) begin
stageA_wayInvalidate <= stage0_wayInvalidate;
end
if(when_DataCache_l763_3) begin
stage0_dataColisions_regNextWhen <= stage0_dataColisions;
end
if(when_DataCache_l814) begin
stageB_request_wr <= stageA_request_wr;
stageB_request_size <= stageA_request_size;
stageB_request_totalyConsistent <= stageA_request_totalyConsistent;
end
if(when_DataCache_l816) begin
stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress;
stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess;
stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging;
stageB_mmuRsp_allowRead <= io_cpu_memory_mmuRsp_allowRead;
stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuRsp_allowWrite;
stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuRsp_allowExecute;
stageB_mmuRsp_exception <= io_cpu_memory_mmuRsp_exception;
stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling;
stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation;
end
if(when_DataCache_l813) begin
stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid;
stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error;
stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address;
end
if(when_DataCache_l813_1) begin
stageB_dataReadRsp_0 <= ways_0_dataReadRsp;
end
if(when_DataCache_l812) begin
stageB_wayInvalidate <= stageA_wayInvalidate;
end
if(when_DataCache_l812_1) begin
stageB_dataColisions <= stageA_dataColisions;
end
if(when_DataCache_l812_2) begin
stageB_unaligned <= ({((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)),((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))} != 2'b00);
end
if(when_DataCache_l812_3) begin
stageB_waysHitsBeforeInvalidate <= stageA_wayHits;
end
if(when_DataCache_l812_4) begin
stageB_mask <= stageA_mask;
end
loader_valid_regNext <= loader_valid;
end
always @(posedge clk) begin
if(reset) begin
memCmdSent <= 1'b0;
stageB_flusher_waitDone <= 1'b0;
stageB_flusher_counter <= 9'h0;
stageB_flusher_start <= 1'b1;
loader_valid <= 1'b0;
loader_counter_value <= 3'b000;
loader_waysAllocator <= 1'b1;
loader_error <= 1'b0;
loader_killReg <= 1'b0;
end else begin
if(io_mem_cmd_fire) begin
memCmdSent <= 1'b1;
end
if(when_DataCache_l678) begin
memCmdSent <= 1'b0;
end
if(io_cpu_flush_ready) begin
stageB_flusher_waitDone <= 1'b0;
end
if(when_DataCache_l842) begin
if(when_DataCache_l848) begin
stageB_flusher_counter <= (stageB_flusher_counter + 9'h001);
end
end
stageB_flusher_start <= (((((((! stageB_flusher_waitDone) && (! stageB_flusher_start)) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo));
if(stageB_flusher_start) begin
stageB_flusher_waitDone <= 1'b1;
stageB_flusher_counter <= 9'h0;
end
`ifndef SYNTHESIS
`ifdef FORMAL
assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck)));
`else
if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin
$display("ERROR writeBack stuck by another plugin is not allowed");
end
`endif
`endif
if(stageB_loaderValid) begin
loader_valid <= 1'b1;
end
loader_counter_value <= loader_counter_valueNext;
if(loader_kill) begin
loader_killReg <= 1'b1;
end
if(when_DataCache_l1075) begin
loader_error <= (loader_error || io_mem_rsp_payload_error);
end
if(loader_done) begin
loader_valid <= 1'b0;
loader_error <= 1'b0;
loader_killReg <= 1'b0;
end
if(when_DataCache_l1103) begin
loader_waysAllocator <= _zz_loader_waysAllocator[0:0];
end
end
end
endmodule
module InstructionCache (
input io_flush,
input io_cpu_prefetch_isValid,
output reg io_cpu_prefetch_haltIt,
input [31:0] io_cpu_prefetch_pc,
input io_cpu_fetch_isValid,
input io_cpu_fetch_isStuck,
input io_cpu_fetch_isRemoved,
input [31:0] io_cpu_fetch_pc,
output [31:0] io_cpu_fetch_data,
input [31:0] io_cpu_fetch_mmuRsp_physicalAddress,
input io_cpu_fetch_mmuRsp_isIoAccess,
input io_cpu_fetch_mmuRsp_isPaging,
input io_cpu_fetch_mmuRsp_allowRead,
input io_cpu_fetch_mmuRsp_allowWrite,
input io_cpu_fetch_mmuRsp_allowExecute,
input io_cpu_fetch_mmuRsp_exception,
input io_cpu_fetch_mmuRsp_refilling,
input io_cpu_fetch_mmuRsp_bypassTranslation,
output [31:0] io_cpu_fetch_physicalAddress,
input io_cpu_decode_isValid,
input io_cpu_decode_isStuck,
input [31:0] io_cpu_decode_pc,
output [31:0] io_cpu_decode_physicalAddress,
output [31:0] io_cpu_decode_data,
output io_cpu_decode_cacheMiss,
output io_cpu_decode_error,
output io_cpu_decode_mmuRefilling,
output io_cpu_decode_mmuException,
input io_cpu_decode_isUser,
input io_cpu_fill_valid,
input [31:0] io_cpu_fill_payload,
output io_mem_cmd_valid,
input io_mem_cmd_ready,
output [31:0] io_mem_cmd_payload_address,
output [2:0] io_mem_cmd_payload_size,
input io_mem_rsp_valid,
input [31:0] io_mem_rsp_payload_data,
input io_mem_rsp_payload_error,
input clk,
input reset
);
reg [31:0] _zz_banks_0_port1;
reg [20:0] _zz_ways_0_tags_port1;
wire [20:0] _zz_ways_0_tags_port;
reg _zz_1;
reg _zz_2;
reg lineLoader_fire;
reg lineLoader_valid;
(* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ;
reg lineLoader_hadError;
reg lineLoader_flushPending;
reg [8:0] lineLoader_flushCounter;
wire when_InstructionCache_l338;
reg _zz_when_InstructionCache_l342;
wire when_InstructionCache_l342;
wire when_InstructionCache_l351;
reg lineLoader_cmdSent;
wire io_mem_cmd_fire;
wire when_Utils_l357;
reg lineLoader_wayToAllocate_willIncrement;
wire lineLoader_wayToAllocate_willClear;
wire lineLoader_wayToAllocate_willOverflowIfInc;
wire lineLoader_wayToAllocate_willOverflow;
(* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ;
wire lineLoader_write_tag_0_valid;
wire [7:0] lineLoader_write_tag_0_payload_address;
wire lineLoader_write_tag_0_payload_data_valid;
wire lineLoader_write_tag_0_payload_data_error;
wire [18:0] lineLoader_write_tag_0_payload_data_address;
wire lineLoader_write_data_0_valid;
wire [10:0] lineLoader_write_data_0_payload_address;
wire [31:0] lineLoader_write_data_0_payload_data;
wire when_InstructionCache_l401;
wire [10:0] _zz_fetchStage_read_banksValue_0_dataMem;
wire _zz_fetchStage_read_banksValue_0_dataMem_1;
wire [31:0] fetchStage_read_banksValue_0_dataMem;
wire [31:0] fetchStage_read_banksValue_0_data;
wire [7:0] _zz_fetchStage_read_waysValues_0_tag_valid;
wire _zz_fetchStage_read_waysValues_0_tag_valid_1;
wire fetchStage_read_waysValues_0_tag_valid;
wire fetchStage_read_waysValues_0_tag_error;
wire [18:0] fetchStage_read_waysValues_0_tag_address;
wire [20:0] _zz_fetchStage_read_waysValues_0_tag_valid_2;
wire fetchStage_hit_hits_0;
wire fetchStage_hit_valid;
wire fetchStage_hit_error;
wire [31:0] fetchStage_hit_data;
wire [31:0] fetchStage_hit_word;
wire when_InstructionCache_l435;
reg [31:0] io_cpu_fetch_data_regNextWhen;
wire when_InstructionCache_l459;
reg [31:0] decodeStage_mmuRsp_physicalAddress;
reg decodeStage_mmuRsp_isIoAccess;
reg decodeStage_mmuRsp_isPaging;
reg decodeStage_mmuRsp_allowRead;
reg decodeStage_mmuRsp_allowWrite;
reg decodeStage_mmuRsp_allowExecute;
reg decodeStage_mmuRsp_exception;
reg decodeStage_mmuRsp_refilling;
reg decodeStage_mmuRsp_bypassTranslation;
wire when_InstructionCache_l459_1;
reg decodeStage_hit_valid;
wire when_InstructionCache_l459_2;
reg decodeStage_hit_error;
(* ram_style = "block" *) reg [31:0] banks_0 [0:2047];
(* ram_style = "block" *) reg [20:0] ways_0_tags [0:255];
assign _zz_ways_0_tags_port = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}};
always @(posedge clk) begin
if(_zz_1) begin
banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data;
end
end
always @(posedge clk) begin
if(_zz_fetchStage_read_banksValue_0_dataMem_1) begin
_zz_banks_0_port1 <= banks_0[_zz_fetchStage_read_banksValue_0_dataMem];
end
end
always @(posedge clk) begin
if(_zz_2) begin
ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_ways_0_tags_port;
end
end
always @(posedge clk) begin
if(_zz_fetchStage_read_waysValues_0_tag_valid_1) begin
_zz_ways_0_tags_port1 <= ways_0_tags[_zz_fetchStage_read_waysValues_0_tag_valid];
end
end
always @(*) begin
_zz_1 = 1'b0;
if(lineLoader_write_data_0_valid) begin
_zz_1 = 1'b1;
end
end
always @(*) begin
_zz_2 = 1'b0;
if(lineLoader_write_tag_0_valid) begin
_zz_2 = 1'b1;
end
end
always @(*) begin
lineLoader_fire = 1'b0;
if(io_mem_rsp_valid) begin
if(when_InstructionCache_l401) begin
lineLoader_fire = 1'b1;
end
end
end
always @(*) begin
io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending);
if(when_InstructionCache_l338) begin
io_cpu_prefetch_haltIt = 1'b1;
end
if(when_InstructionCache_l342) begin
io_cpu_prefetch_haltIt = 1'b1;
end
if(io_flush) begin
io_cpu_prefetch_haltIt = 1'b1;
end
end
assign when_InstructionCache_l338 = (! lineLoader_flushCounter[8]);
assign when_InstructionCache_l342 = (! _zz_when_InstructionCache_l342);
assign when_InstructionCache_l351 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid)));
assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready);
assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent));
assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0};
assign io_mem_cmd_payload_size = 3'b101;
assign when_Utils_l357 = (! lineLoader_valid);
always @(*) begin
lineLoader_wayToAllocate_willIncrement = 1'b0;
if(when_Utils_l357) begin
lineLoader_wayToAllocate_willIncrement = 1'b1;
end
end
assign lineLoader_wayToAllocate_willClear = 1'b0;
assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1;
assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement);
assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[8]));
assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[8] ? lineLoader_address[12 : 5] : lineLoader_flushCounter[7 : 0]);
assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[8];
assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error);
assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 13];
assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1);
assign lineLoader_write_data_0_payload_address = {lineLoader_address[12 : 5],lineLoader_wordIndex};
assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data;
assign when_InstructionCache_l401 = (lineLoader_wordIndex == 3'b111);
assign _zz_fetchStage_read_banksValue_0_dataMem = io_cpu_prefetch_pc[12 : 2];
assign _zz_fetchStage_read_banksValue_0_dataMem_1 = (! io_cpu_fetch_isStuck);
assign fetchStage_read_banksValue_0_dataMem = _zz_banks_0_port1;
assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0];
assign _zz_fetchStage_read_waysValues_0_tag_valid = io_cpu_prefetch_pc[12 : 5];
assign _zz_fetchStage_read_waysValues_0_tag_valid_1 = (! io_cpu_fetch_isStuck);
assign _zz_fetchStage_read_waysValues_0_tag_valid_2 = _zz_ways_0_tags_port1;
assign fetchStage_read_waysValues_0_tag_valid = _zz_fetchStage_read_waysValues_0_tag_valid_2[0];
assign fetchStage_read_waysValues_0_tag_error = _zz_fetchStage_read_waysValues_0_tag_valid_2[1];
assign fetchStage_read_waysValues_0_tag_address = _zz_fetchStage_read_waysValues_0_tag_valid_2[20 : 2];
assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 13]));
assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0);
assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error;
assign fetchStage_hit_data = fetchStage_read_banksValue_0_data;
assign fetchStage_hit_word = fetchStage_hit_data;
assign io_cpu_fetch_data = fetchStage_hit_word;
assign when_InstructionCache_l435 = (! io_cpu_decode_isStuck);
assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen;
assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress;
assign when_InstructionCache_l459 = (! io_cpu_decode_isStuck);
assign when_InstructionCache_l459_1 = (! io_cpu_decode_isStuck);
assign when_InstructionCache_l459_2 = (! io_cpu_decode_isStuck);
assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid);
assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))));
assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling;
assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)));
assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress;
always @(posedge clk) begin
if(reset) begin
lineLoader_valid <= 1'b0;
lineLoader_hadError <= 1'b0;
lineLoader_flushPending <= 1'b1;
lineLoader_cmdSent <= 1'b0;
lineLoader_wordIndex <= 3'b000;
end else begin
if(lineLoader_fire) begin
lineLoader_valid <= 1'b0;
end
if(lineLoader_fire) begin
lineLoader_hadError <= 1'b0;
end
if(io_cpu_fill_valid) begin
lineLoader_valid <= 1'b1;
end
if(io_flush) begin
lineLoader_flushPending <= 1'b1;
end
if(when_InstructionCache_l351) begin
lineLoader_flushPending <= 1'b0;
end
if(io_mem_cmd_fire) begin
lineLoader_cmdSent <= 1'b1;
end
if(lineLoader_fire) begin
lineLoader_cmdSent <= 1'b0;
end
if(io_mem_rsp_valid) begin
lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001);
if(io_mem_rsp_payload_error) begin
lineLoader_hadError <= 1'b1;
end
end
end
end
always @(posedge clk) begin
if(io_cpu_fill_valid) begin
lineLoader_address <= io_cpu_fill_payload;
end
if(when_InstructionCache_l338) begin
lineLoader_flushCounter <= (lineLoader_flushCounter + 9'h001);
end
_zz_when_InstructionCache_l342 <= lineLoader_flushCounter[8];
if(when_InstructionCache_l351) begin
lineLoader_flushCounter <= 9'h0;
end
if(when_InstructionCache_l435) begin
io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data;
end
if(when_InstructionCache_l459) begin
decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress;
decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess;
decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging;
decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead;
decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite;
decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute;
decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuRsp_exception;
decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling;
decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation;
end
if(when_InstructionCache_l459_1) begin
decodeStage_hit_valid <= fetchStage_hit_valid;
end
if(when_InstructionCache_l459_2) begin
decodeStage_hit_error <= fetchStage_hit_error;
end
end
endmodule
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: COCO3GEN.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module COCO3GEN (
address,
clock,
q);
input [10:0] address;
input clock;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.clock0 (clock),
.address_a (address),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({8{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "coco3gen.mif",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.maximum_depth = 2048,
altsyncram_component.numwords_a = 2048,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.ram_block_type = "M4K",
altsyncram_component.widthad_a = 11,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "2048"
// Retrieval info: PRIVATE: MIFfilename STRING "coco3gen.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "coco3gen.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: MAXIMUM_DEPTH NUMERIC "2048"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M4K"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL address[10..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
// Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL COCO3GEN.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL COCO3GEN.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL COCO3GEN.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL COCO3GEN.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL COCO3GEN_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL COCO3GEN_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL COCO3GEN_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL COCO3GEN_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/*
L2 Data Cache
This version will use the Cache as RAM,
0C00_0000 .. 0C00_7FFF
May be accessed either as 128 bit tiles, or as 32 or 64 bit words.
MMIO may only be accessed as 32-bits.
*/
`include "CoreDefs.v"
module Dc2Tile(
/* verilator lint_off UNUSED */
clock, reset,
regInAddr, regInData,
regOutData, regOutOK,
regInOE, regInWR,
regInOp,
memInData, memOutData, memAddr,
memOE, memWR, memOK,
mmioInData, mmioOutData, mmioAddr,
mmioOE, mmioWR, mmioOK
);
input clock; //clock
input reset; //reset
input[31:0] regInAddr; //input PC address
input[127:0] regInData; //input data (store)
input regInOE; //Load
input regInWR; //Store
input[4:0] regInOp; //Operation Size/Type
output[127:0] regOutData; //output data (load)
output[1:0] regOutOK; //set if operation suceeds
input[127:0] memInData; //memory PC data
output[127:0] memOutData; //memory PC data
output[31:0] memAddr; //memory PC address
output memOE; //memory PC output-enable
output memWR; //memory PC output-enable
input[1:0] memOK; //memory PC OK
reg[127:0] tMemOutData; //memory PC data
reg[31:0] tMemAddr; //memory PC address
reg tMemOE; //memory PC output-enable
reg tMemWR; //memory PC output-enable
assign memOutData = tMemOutData;
assign memAddr = tMemAddr;
assign memOE = tMemOE;
assign memWR = tMemWR;
input[31:0] mmioInData; //mmio data in
output[31:0] mmioOutData; //mmio data out
output[31:0] mmioAddr; //mmio address
output mmioOE; //mmio read
output mmioWR; //mmio write
input[1:0] mmioOK; //mmio OK
reg[31:0] tMmioOutData; //mmio data out
reg[31:0] tMmioAddr; //mmio address
reg tMmioOE; //mmio read
reg tMmioWR; //mmio write
assign mmioOutData = tMmioOutData;
assign mmioAddr = tMmioAddr;
assign mmioOE = tMmioOE;
assign mmioWR = tMmioWR;
// (* ram_style="block" *) reg[127:0] memTile[2047:0]; //memory
(* ram_style="block" *) reg[31:0] memTileA[0:2047]; //memory
(* ram_style="block" *) reg[31:0] memTileB[0:2047]; //memory
(* ram_style="block" *) reg[31:0] memTileC[0:2047]; //memory
(* ram_style="block" *) reg[31:0] memTileD[0:2047]; //memory
(* ram_style="block" *) reg[127:0] romTile[255:0]; //ROM
// reg[127:0] tRomTile;
reg[127:0] tRamTile;
reg[10:0] tAccTileIx;
reg[127:0] tMemTile;
reg[127:0] tOutData;
reg[127:0] tNextTile;
reg[10:0] tRegTileIx;
reg[10:0] tNextTileIx;
reg tNextTileSt;
reg[1:0] tRegOutOK;
wire addrIsRam;
assign addrIsRam =
(regInAddr[28:0] >= 29'h0C00_0000) &&
(regInAddr[28:0] <= 29'h1E00_0000) ;
wire addrIsRom;
assign addrIsRom =
(regInAddr[28:0] <= 29'h0010_0000) ;
assign regOutData = tOutData;
assign regOutOK = tRegOutOK;
initial begin
$readmemh("bootrom.txt", romTile);
end
always @*
begin
tMemTile = 0;
tOutData = 0;
tNextTile = 0;
tRegTileIx = regInAddr[14:4];
tNextTileIx = tRegTileIx;
tNextTileSt = 0;
tRegOutOK = 0;
tMemOutData = 0; //memory PC data
tMemAddr = 0; //memory PC address
tMemOE = 0; //memory PC output-enable
tMemWR = 0; //memory PC output-enable
tMmioOutData = 0; //mmio data out
tMmioAddr = 0; //mmio address
tMmioOE = 0; //mmio read
tMmioWR = 0; //mmio write
if(regInOE || regInWR)
begin
$display("DcTile2 %X %d %d", regInAddr, addrIsRom, addrIsRam);
if(addrIsRom)
begin
tMemTile = romTile[tRegTileIx[7:0]];
// tMemTile = tRomTile;
tNextTile = tMemTile;
tRegOutOK = 1;
// tRegOutOK = (tAccTileIx == tRegTileIx) ?
// UMEM_OK_OK : UMEM_OK_HOLD;
$display("Rom: %X", tMemTile);
case(regInOp[1:0])
2'b00:
tOutData=tMemTile;
2'b01:
tOutData=tMemTile;
2'b10: case(regInAddr[3:2])
2'b00: tOutData={96'h0, tMemTile[ 31: 0]};
2'b01: tOutData={96'h0, tMemTile[ 63:32]};
2'b10: tOutData={96'h0, tMemTile[ 95:64]};
2'b11: tOutData={96'h0, tMemTile[127:96]};
endcase
2'b11: begin
if(regInAddr[3])
tOutData={64'h0, tMemTile[127:64]};
else
tOutData={64'h0, tMemTile[ 63: 0]};
end
endcase
$display("Rom: Out=%X", tOutData);
end
else
if(addrIsRam)
begin
// tMemTile = memTile[tRegTileIx];
// tMemTile[ 31: 0] = memTileA[tRegTileIx];
// tMemTile[ 63:32] = memTileB[tRegTileIx];
// tMemTile[ 95:64] = memTileC[tRegTileIx];
// tMemTile[127:96] = memTileD[tRegTileIx];
tMemTile = tRamTile;
tNextTile = tMemTile;
// tRegOutOK = 1;
tRegOutOK = (tAccTileIx == tRegTileIx) ?
UMEM_OK_OK : UMEM_OK_HOLD;
case(regInOp[1:0])
2'b00:
tOutData=tMemTile;
2'b01:
tOutData=tMemTile;
2'b10: case(regInAddr[3:2])
2'b00: tOutData={96'h0, tMemTile[ 31: 0]};
2'b01: tOutData={96'h0, tMemTile[ 63:32]};
2'b10: tOutData={96'h0, tMemTile[ 95:64]};
2'b11: tOutData={96'h0, tMemTile[127:96]};
endcase
2'b11: begin
if(regInAddr[3])
tOutData={64'h0, tMemTile[127:64]};
else
tOutData={64'h0, tMemTile[ 63: 0]};
end
endcase
if(regInWR)
begin
tNextTileIx = tRegTileIx;
tNextTileSt = 1;
case(regInOp[1:0])
2'b00:
tNextTile=regInData;
2'b01:
tNextTile=regInData;
2'b10: case(regInAddr[3:2])
2'b00: tNextTile[ 31: 0] = regInData[31:0];
2'b01: tNextTile[ 63:32] = regInData[31:0];
2'b10: tNextTile[ 95:64] = regInData[31:0];
2'b11: tNextTile[127:96] = regInData[31:0];
endcase
2'b11: begin
if(regInAddr[3])
tNextTile[127:64] = regInData[63:0];
else
tNextTile[ 63: 0] = regInData[63:0];
end
endcase
end
end
else
begin
tMmioOutData = regInData[31:0];
tMmioAddr = regInAddr;
tMmioOE = regInOE;
tMmioWR = regInWR;
tRegOutOK = mmioOK;
tOutData = { 96'h0, mmioInData[31:0] };
end
end
end
always @ (posedge clock)
begin
// tRomTile <= romTile[tRegTileIx[7:0]];
// tRamTile <= memTile[tRegTileIx];
tRamTile[ 31: 0] <= memTileA[tRegTileIx];
tRamTile[ 63:32] <= memTileB[tRegTileIx];
tRamTile[ 95:64] <= memTileC[tRegTileIx];
tRamTile[127:96] <= memTileD[tRegTileIx];
tAccTileIx <= tRegTileIx;
if(tNextTileSt)
begin
// memTile[tNextTileIx] <= tNextTile;
memTileA[tNextTileIx] <= tNextTile[ 31: 0];
memTileB[tNextTileIx] <= tNextTile[ 63:32];
memTileC[tNextTileIx] <= tNextTile[ 95:64];
memTileD[tNextTileIx] <= tNextTile[127:96];
end
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module cf_adc_2c (
// pcore identifier (master(0)/slave(>0) control for multiple instances)
pid,
// adc interface (clk, data, over-range)
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_data_or_p,
adc_data_or_n,
// dma interface (refer to xilinx AXI_DMA doc. for details)
dma_clk,
dma_valid,
dma_data,
dma_be,
dma_last,
dma_ready,
// processor (control) interface
up_rstn,
up_clk,
up_sel,
up_rwn,
up_addr,
up_wdata,
up_rdata,
up_ack,
up_status,
// processor master/slave controls
// master capture enable, if the pid of a instance is 0x0, these ports
// should be connected to all slaves
up_adc_capture_int,
// processor master/slave controls
// if the pid of a instance is greater than 0x0, these ports
// should be connected to the *_int signals from a master
up_adc_capture_ext,
// delay elements clock (200MHz for most devices)
delay_clk,
// dma debug and monitor signals (for chipscope)
dma_dbg_data,
dma_dbg_trigger,
// adc debug and monitor signals (for chipscope)
adc_clk,
adc_dbg_data,
adc_dbg_trigger,
adc_mon_valid,
adc_mon_data);
// This parameter controls the buffer type based on the target device.
// Refer to the adc interface, where IOBUF*s are instantiated for details.
// The default (0x0) is 7 series and covers Zynq also.
parameter C_CF_BUFTYPE = 0;
// The io delay group must be an unique string in the system, to group the
// delay control with the delay elements. If a system doesn't have enough
// control units, you could use an external common delay control
parameter C_IODELAY_GROUP = "adc_if_delay_group";
// pcore identifier (master(0)/slave(>0) control for multiple instances)
input [ 7:0] pid;
// adc interface (clk, data, over-range)
input adc_clk_in_p;
input adc_clk_in_n;
input [13:0] adc_data_in_p;
input [13:0] adc_data_in_n;
input adc_data_or_p;
input adc_data_or_n;
// dma interface (refer to xilinx AXI_DMA doc. for details)
input dma_clk;
output dma_valid;
output [63:0] dma_data;
output [ 7:0] dma_be;
output dma_last;
input dma_ready;
// processor (control) interface
input up_rstn;
input up_clk;
input up_sel;
input up_rwn;
input [ 4:0] up_addr;
input [31:0] up_wdata;
output [31:0] up_rdata;
output up_ack;
output [ 7:0] up_status;
// processor master/slave controls
output up_adc_capture_int;
input up_adc_capture_ext;
// delay elements clock (200MHz for most devices)
input delay_clk;
// dma debug and monitor signals (for chipscope)
output [63:0] dma_dbg_data;
output [ 7:0] dma_dbg_trigger;
// adc debug and monitor signals (for chipscope)
output adc_clk;
output [63:0] adc_dbg_data;
output [ 7:0] adc_dbg_trigger;
output adc_mon_valid;
output [31:0] adc_mon_data;
// internal signals
reg [ 3:0] up_usr_sel = 'd0;
reg [ 1:0] up_ch_sel = 'd0;
reg up_adc_capture_int = 'd0;
reg up_capture_stream = 'd0;
reg [29:0] up_capture_count = 'd0;
reg up_dma_unf_hold = 'd0;
reg up_dma_ovf_hold = 'd0;
reg up_dma_status = 'd0;
reg [ 1:0] up_adc_or_hold = 'd0;
reg [ 1:0] up_adc_pn_oos_hold = 'd0;
reg [ 1:0] up_adc_pn_err_hold = 'd0;
reg [ 1:0] up_dmode = 'd0;
reg up_delay_sel = 'd0;
reg up_delay_rwn = 'd0;
reg [ 3:0] up_delay_addr = 'd0;
reg [ 4:0] up_delay_wdata = 'd0;
reg [ 1:0] up_pn_type = 'd0;
reg up_muladd_offbin = 'd0;
reg up_muladd_enable = 'd0;
reg up_signext_enable = 'd0;
reg up_status_enable = 'd0;
reg [14:0] up_muladd_offset_a = 'd0;
reg [15:0] up_muladd_scale_a = 'd0;
reg [14:0] up_muladd_offset_b = 'd0;
reg [15:0] up_muladd_scale_b = 'd0;
reg [15:0] up_decimation_m = 'd0;
reg [15:0] up_decimation_n = 'd0;
reg up_data_type = 'd0;
reg [15:0] up_dcfilter_coeff_b = 'd0;
reg [15:0] up_dcfilter_coeff_a = 'd0;
reg [ 7:0] up_status = 'd0;
reg up_adc_master_capture_n = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_sel_d = 'd0;
reg up_sel_2d = 'd0;
reg up_ack = 'd0;
reg up_dma_ovf_m1 = 'd0;
reg up_dma_ovf_m2 = 'd0;
reg up_dma_ovf = 'd0;
reg up_dma_unf_m1 = 'd0;
reg up_dma_unf_m2 = 'd0;
reg up_dma_unf = 'd0;
reg up_dma_complete_m1 = 'd0;
reg up_dma_complete_m2 = 'd0;
reg up_dma_complete_m3 = 'd0;
reg up_dma_complete = 'd0;
reg [ 1:0] up_adc_or_m1 = 'd0;
reg [ 1:0] up_adc_or_m2 = 'd0;
reg [ 1:0] up_adc_or = 'd0;
reg [ 1:0] up_adc_pn_oos_m1 = 'd0;
reg [ 1:0] up_adc_pn_oos_m2 = 'd0;
reg [ 1:0] up_adc_pn_oos = 'd0;
reg [ 1:0] up_adc_pn_err_m1 = 'd0;
reg [ 1:0] up_adc_pn_err_m2 = 'd0;
reg [ 1:0] up_adc_pn_err = 'd0;
reg up_delay_ack_m1 = 'd0;
reg up_delay_ack_m2 = 'd0;
reg up_delay_ack_m3 = 'd0;
reg up_delay_ack = 'd0;
reg [ 4:0] up_delay_rdata = 'd0;
reg up_delay_locked = 'd0;
// internal signals
wire up_wr_s;
wire up_ack_s;
wire adc_master_capture_s;
wire dma_ovf_s;
wire dma_unf_s;
wire dma_complete_s;
wire adc_valid_s;
wire [63:0] adc_data_s;
wire [ 1:0] adc_or_s;
wire [ 1:0] adc_pn_oos_s;
wire [ 1:0] adc_pn_err_s;
wire [15:0] usr_decimation_m_s;
wire [15:0] usr_decimation_n_s;
wire usr_data_type_s;
wire [ 3:0] usr_max_channels_s;
wire delay_ack_s;
wire [ 4:0] delay_rdata_s;
wire delay_locked_s;
assign up_wr_s = up_sel & ~up_rwn;
assign up_ack_s = up_sel_d & ~up_sel_2d;
// Processor write interface (see regmap.txt file in the pcore root directory
// for address map and details of register functions).
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_usr_sel <= 'd0;
up_ch_sel <= 'd3;
up_adc_capture_int <= 'd0;
up_capture_stream <= 'd0;
up_capture_count <= 'd0;
up_dma_unf_hold <= 'd0;
up_dma_ovf_hold <= 'd0;
up_dma_status <= 'd0;
up_adc_or_hold <= 'd0;
up_adc_pn_oos_hold <= 'd0;
up_adc_pn_err_hold <= 'd0;
up_dmode <= 'd0;
up_delay_sel <= 'd0;
up_delay_rwn <= 'd0;
up_delay_addr <= 'd0;
up_delay_wdata <= 'd0;
up_pn_type <= 'd0;
up_muladd_offbin <= 'd0;
up_muladd_enable <= 'd0;
up_signext_enable <= 'd0;
up_status_enable <= 'd0;
up_muladd_offset_a <= 'd0;
up_muladd_scale_a <= 'd0;
up_muladd_offset_b <= 'd0;
up_muladd_scale_b <= 'd0;
up_decimation_m <= 'd0;
up_decimation_n <= 'd0;
up_data_type <= 'd0;
up_dcfilter_coeff_b <= 'd0;
up_dcfilter_coeff_a <= 'd0;
up_status <= 'd0;
up_adc_master_capture_n <= 'd1;
end else begin
if ((up_addr == 5'h02) && (up_wr_s == 1'b1)) begin
up_usr_sel <= up_wdata[5:2];
up_ch_sel <= up_wdata[1:0];
end
if ((up_addr == 5'h03) && (up_wr_s == 1'b1)) begin
up_adc_capture_int <= up_wdata[31];
up_capture_stream <= up_wdata[30];
up_capture_count <= up_wdata[29:0];
end
if (up_dma_unf == 1'b1) begin
up_dma_unf_hold <= 1'b1;
end else if ((up_addr == 5'h04) && (up_wr_s == 1'b1)) begin
up_dma_unf_hold <= up_dma_unf_hold & ~up_wdata[2];
end
if (up_dma_ovf == 1'b1) begin
up_dma_ovf_hold <= 1'b1;
end else if ((up_addr == 5'h04) && (up_wr_s == 1'b1)) begin
up_dma_ovf_hold <= up_dma_ovf_hold & ~up_wdata[2];
end
if (up_dma_complete == 1'b1) begin
up_dma_status <= 1'b0;
end else if ((up_addr == 5'h03) && (up_wr_s == 1'b1) && (up_dma_status == 1'b0)) begin
up_dma_status <= up_wdata[16];
end
if (up_adc_or[0] == 1'b1) begin
up_adc_or_hold[0] <= 1'b1;
end else if ((up_addr == 5'h05) && (up_wr_s == 1'b1)) begin
up_adc_or_hold[0] <= up_adc_or_hold[0] & ~up_wdata[0];
end
if (up_adc_or[1] == 1'b1) begin
up_adc_or_hold[1] <= 1'b1;
end else if ((up_addr == 5'h05) && (up_wr_s == 1'b1)) begin
up_adc_or_hold[1] <= up_adc_or_hold[1] & ~up_wdata[1];
end
if (up_adc_pn_oos[0] == 1'b1) begin
up_adc_pn_oos_hold[0] <= 1'b1;
end else if ((up_addr == 5'h05) && (up_wr_s == 1'b1)) begin
up_adc_pn_oos_hold[0] <= up_adc_pn_oos_hold[0] & ~up_wdata[2];
end
if (up_adc_pn_oos[1] == 1'b1) begin
up_adc_pn_oos_hold[1] <= 1'b1;
end else if ((up_addr == 5'h05) && (up_wr_s == 1'b1)) begin
up_adc_pn_oos_hold[1] <= up_adc_pn_oos_hold[1] & ~up_wdata[3];
end
if (up_adc_pn_err[0] == 1'b1) begin
up_adc_pn_err_hold[0] <= 1'b1;
end else if ((up_addr == 5'h05) && (up_wr_s == 1'b1)) begin
up_adc_pn_err_hold[0] <= up_adc_pn_err_hold[0] & ~up_wdata[4];
end
if (up_adc_pn_err[1] == 1'b1) begin
up_adc_pn_err_hold[1] <= 1'b1;
end else if ((up_addr == 5'h05) && (up_wr_s == 1'b1)) begin
up_adc_pn_err_hold[1] <= up_adc_pn_err_hold[1] & ~up_wdata[5];
end
if ((up_addr == 5'h06) && (up_wr_s == 1'b1)) begin
up_dmode <= up_wdata[1:0];
end
if ((up_addr == 5'h07) && (up_wr_s == 1'b1)) begin
up_delay_sel <= up_wdata[17];
up_delay_rwn <= up_wdata[16];
up_delay_addr <= up_wdata[11:8];
up_delay_wdata <= up_wdata[4:0];
end
if ((up_addr == 5'h09) && (up_wr_s == 1'b1)) begin
up_pn_type <= up_wdata[1:0];
end
if ((up_addr == 5'h0b) && (up_wr_s == 1'b1)) begin
up_muladd_offbin <= up_wdata[3];
up_muladd_enable <= up_wdata[2];
up_signext_enable <= up_wdata[1];
up_status_enable <= up_wdata[0];
end
if ((up_addr == 5'h10) && (up_wr_s == 1'b1)) begin
up_muladd_offset_a <= up_wdata[30:16];
up_muladd_scale_a <= up_wdata[15:0];
end
if ((up_addr == 5'h11) && (up_wr_s == 1'b1)) begin
up_muladd_offset_b <= up_wdata[30:16];
up_muladd_scale_b <= up_wdata[15:0];
end
if ((up_addr == 5'h12) && (up_wr_s == 1'b1)) begin
up_decimation_m <= up_wdata[31:16];
up_decimation_n <= up_wdata[15:0];
end
if ((up_addr == 5'h13) && (up_wr_s == 1'b1)) begin
up_data_type <= up_wdata[0];
end
if ((up_addr == 5'h15) && (up_wr_s == 1'b1)) begin
up_dcfilter_coeff_b <= up_wdata[31:16];
up_dcfilter_coeff_a <= up_wdata[15:0];
end
if (up_status_enable == 1'b1) begin
up_status <= {5'd1, up_adc_capture_int, up_dma_ovf, up_dma_status};
end else begin
up_status <= 'd0;
end
if (pid == 0) begin
up_adc_master_capture_n <= ~up_adc_capture_int;
end else begin
up_adc_master_capture_n <= ~up_adc_capture_ext;
end
end
end
// Processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_sel_d <= 'd0;
up_sel_2d <= 'd0;
up_ack <= 'd0;
end else begin
case (up_addr)
5'h00: up_rdata <= 32'h00010063;
5'h02: up_rdata <= {26'd0, up_usr_sel, up_ch_sel};
5'h03: up_rdata <= {up_adc_capture_int, up_capture_stream, up_capture_count};
5'h04: up_rdata <= {29'd0, up_dma_unf_hold, up_dma_ovf_hold, up_dma_status};
5'h05: up_rdata <= {26'd0, up_adc_pn_err_hold, up_adc_pn_oos_hold, up_adc_or_hold};
5'h06: up_rdata <= {30'd0, up_dmode};
5'h07: up_rdata <= {14'd0, up_delay_sel, up_delay_rwn, 4'd0, up_delay_addr,
3'd0, up_delay_wdata};
5'h08: up_rdata <= {23'd0, up_delay_locked, 3'd0, up_delay_rdata};
5'h09: up_rdata <= {30'd0, up_pn_type};
5'h0b: up_rdata <= {28'd0, up_muladd_offbin, up_muladd_enable,
up_signext_enable, up_status_enable};
5'h0c: up_rdata <= {24'd0, pid};
5'h10: up_rdata <= {1'b0, up_muladd_offset_a, up_muladd_scale_a};
5'h11: up_rdata <= {1'b0, up_muladd_offset_b, up_muladd_scale_b};
5'h12: up_rdata <= {usr_decimation_m_s, usr_decimation_n_s};
5'h13: up_rdata <= {31'd0, usr_data_type_s};
5'h14: up_rdata <= {28'd0, usr_max_channels_s};
5'h15: up_rdata <= {up_dcfilter_coeff_b, up_dcfilter_coeff_a};
default: up_rdata <= 0;
endcase
up_sel_d <= up_sel;
up_sel_2d <= up_sel_d;
up_ack <= up_ack_s;
end
end
// Status signals from ADC are transferred to the processor clock,
// all signals are strectched to multiple processor clocks from the adc.
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_dma_ovf_m1 <= 'd0;
up_dma_ovf_m2 <= 'd0;
up_dma_ovf <= 'd0;
up_dma_unf_m1 <= 'd0;
up_dma_unf_m2 <= 'd0;
up_dma_unf <= 'd0;
up_dma_complete_m1 <= 'd0;
up_dma_complete_m2 <= 'd0;
up_dma_complete_m3 <= 'd0;
up_dma_complete <= 'd0;
end else begin
up_dma_ovf_m1 <= dma_ovf_s;
up_dma_ovf_m2 <= up_dma_ovf_m1;
up_dma_ovf <= up_dma_ovf_m2;
up_dma_unf_m1 <= dma_unf_s;
up_dma_unf_m2 <= up_dma_unf_m1;
up_dma_unf <= up_dma_unf_m2;
up_dma_complete_m1 <= dma_complete_s;
up_dma_complete_m2 <= up_dma_complete_m1;
up_dma_complete_m3 <= up_dma_complete_m2;
up_dma_complete <= up_dma_complete_m3 ^ up_dma_complete_m2;
end
end
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_adc_or_m1 <= 'd0;
up_adc_or_m2 <= 'd0;
up_adc_or <= 'd0;
up_adc_pn_oos_m1 <= 'd0;
up_adc_pn_oos_m2 <= 'd0;
up_adc_pn_oos <= 'd0;
up_adc_pn_err_m1 <= 'd0;
up_adc_pn_err_m2 <= 'd0;
up_adc_pn_err <= 'd0;
up_delay_ack_m1 <= 'd0;
up_delay_ack_m2 <= 'd0;
up_delay_ack_m3 <= 'd0;
up_delay_ack <= 'd0;
up_delay_rdata <= 'd0;
up_delay_locked <= 'd0;
end else begin
up_adc_or_m1 <= adc_or_s;
up_adc_or_m2 <= up_adc_or_m1;
up_adc_or <= up_adc_or_m2;
up_adc_pn_oos_m1 <= adc_pn_oos_s;
up_adc_pn_oos_m2 <= up_adc_pn_oos_m1;
up_adc_pn_oos <= up_adc_pn_oos_m2;
up_adc_pn_err_m1 <= adc_pn_err_s;
up_adc_pn_err_m2 <= up_adc_pn_err_m1;
up_adc_pn_err <= up_adc_pn_err_m2;
up_delay_ack_m1 <= delay_ack_s;
up_delay_ack_m2 <= up_delay_ack_m1;
up_delay_ack_m3 <= up_delay_ack_m2;
up_delay_ack <= up_delay_ack_m3 ^ up_delay_ack_m2;
if (up_delay_ack == 1'b1) begin
up_delay_rdata <= delay_rdata_s;
up_delay_locked <= delay_locked_s;
end
end
end
// transfer the master capture to the adc clock domain.
// this is a asynchronous clear register
FDCE #(.INIT(1'b0)) i_m_capture (
.CE (1'b1),
.D (1'b1),
.CLR (up_adc_master_capture_n),
.C (adc_clk),
.Q (adc_master_capture_s));
// dma interface, this module transfers data from adc clock domain to
// dma clock domain.
cf_dma_wr i_dma_wr (
.adc_clk (adc_clk),
.adc_valid (adc_valid_s),
.adc_data (adc_data_s),
.adc_master_capture (adc_master_capture_s),
.dma_clk (dma_clk),
.dma_valid (dma_valid),
.dma_data (dma_data),
.dma_be (dma_be),
.dma_last (dma_last),
.dma_ready (dma_ready),
.dma_ovf (dma_ovf_s),
.dma_unf (dma_unf_s),
.dma_complete (dma_complete_s),
.up_capture_stream (up_capture_stream),
.up_capture_count (up_capture_count),
.dma_dbg_data (dma_dbg_data),
.dma_dbg_trigger (dma_dbg_trigger),
.adc_dbg_data (adc_dbg_data),
.adc_dbg_trigger (adc_dbg_trigger));
// adc interface, this module captures data from the adc interface,
// and transfers it to the dma interface module above.
cf_adc_wr #(.C_CF_BUFTYPE(C_CF_BUFTYPE), .C_IODELAY_GROUP(C_IODELAY_GROUP)) i_adc_wr (
.adc_clk_in_p (adc_clk_in_p),
.adc_clk_in_n (adc_clk_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_data_in_n (adc_data_in_n),
.adc_data_or_p (adc_data_or_p),
.adc_data_or_n (adc_data_or_n),
.adc_clk (adc_clk),
.adc_valid (adc_valid_s),
.adc_data (adc_data_s),
.adc_or (adc_or_s),
.adc_pn_oos (adc_pn_oos_s),
.adc_pn_err (adc_pn_err_s),
.up_signext_enable (up_signext_enable),
.up_muladd_enable (up_muladd_enable),
.up_muladd_offbin (up_muladd_offbin),
.up_muladd_scale_a (up_muladd_scale_a),
.up_muladd_offset_a (up_muladd_offset_a),
.up_muladd_scale_b (up_muladd_scale_b),
.up_muladd_offset_b (up_muladd_offset_b),
.up_pn_type (up_pn_type),
.up_dmode (up_dmode),
.up_ch_sel (up_ch_sel),
.up_usr_sel (up_usr_sel),
.up_delay_sel (up_delay_sel),
.up_delay_rwn (up_delay_rwn),
.up_delay_addr (up_delay_addr),
.up_delay_wdata (up_delay_wdata),
.up_decimation_m (up_decimation_m),
.up_decimation_n (up_decimation_n),
.up_data_type (up_data_type),
.up_dcfilter_coeff_a (up_dcfilter_coeff_a),
.up_dcfilter_coeff_b (up_dcfilter_coeff_b),
.usr_decimation_m (usr_decimation_m_s),
.usr_decimation_n (usr_decimation_n_s),
.usr_data_type (usr_data_type_s),
.usr_max_channels (usr_max_channels_s),
.delay_clk (delay_clk),
.delay_ack (delay_ack_s),
.delay_rdata (delay_rdata_s),
.delay_locked (delay_locked_s),
.debug_data (),
.debug_trigger (),
.adc_mon_valid (adc_mon_valid),
.adc_mon_data (adc_mon_data));
endmodule
// ***************************************************************************
// ***************************************************************************
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: lsu_stb_ctl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
///////////////////////////////////////////////////////////////////////
/*
// Description: Control for STB of LSU
// - Contains control for a single STB currently.
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module lsu_stb_ctl (/*AUTOARG*/
// Outputs
so, stb_clk_en_l, stb_crnt_ack_id, lsu_stb_empty, stb_l2bnk_addr,
stb_atm_rq_type, stb_wrptr, stb_rd_for_pcx, stb_pcx_rptr,
stb_wrptr_prev, stb_state_ced_mod, stb_state_vld_out,
lsu_stbcnt, stb_rmo_st_issue, stb_full, st_pcx_rq_kill_w2,
// Inputs
rclk, grst_l, arst_l, si, se, thrd_en_g, cpx_st_ack_tid,
pcx_rq_for_stb, st_ack_dq_stb, stb_flush_st_g, stb_cam_wvld_m,
lsu_blk_st_m, tlb_pgnum_g, pcx_req_squash, flshinst_rst,
lsu_stbctl_flush_pipe_w, flsh_inst_m, stb_state_si_0,
stb_state_si_1, stb_state_si_2, stb_state_si_3, stb_state_si_4,
stb_state_si_5, stb_state_si_6, stb_state_si_7, stb_state_rtype_0,
stb_state_rtype_1, stb_state_rtype_2, stb_state_rtype_3,
stb_state_rtype_4, stb_state_rtype_5, stb_state_rtype_6,
stb_state_rtype_7, stb_state_rmo, stb_alt_sel, stb_alt_addr,
lsu_dtlb_bypass_e, tlb_cam_hit, lsu_outstanding_rmo_st_max,
st_dtlb_perr_g
) ;
input rclk ;
input grst_l;
input arst_l;
input si;
input se;
output so;
input thrd_en_g ;
input cpx_st_ack_tid ; // st ack for given thread
input pcx_rq_for_stb ; // stb's st selected for read for pcx
input st_ack_dq_stb ; // store dequeued from stb
input stb_flush_st_g ; // flush stb write in cycle g
input stb_cam_wvld_m ; // stb write in cycle m
input lsu_blk_st_m ; // blk st wr
//input [7:6] lsu_ldst_va_m ; // staging purposes
//input [2:1] lsu_st_rq_type_m ; // st request type
//input lsu_st_rmo_m ; // rmo store in m-stage
input [39:37] tlb_pgnum_g ; // ldst access to io
input pcx_req_squash ; // pcx req is squashed
input flshinst_rst ; // reset by flush inst on return
input lsu_stbctl_flush_pipe_w ;
input flsh_inst_m;
//from stb_ctldp
input [3:2] stb_state_si_0;
input [3:2] stb_state_si_1;
input [3:2] stb_state_si_2;
input [3:2] stb_state_si_3;
input [3:2] stb_state_si_4;
input [3:2] stb_state_si_5;
input [3:2] stb_state_si_6;
input [3:2] stb_state_si_7;
input [2:1] stb_state_rtype_0;
input [2:1] stb_state_rtype_1;
input [2:1] stb_state_rtype_2;
input [2:1] stb_state_rtype_3;
input [2:1] stb_state_rtype_4;
input [2:1] stb_state_rtype_5;
input [2:1] stb_state_rtype_6;
input [2:1] stb_state_rtype_7;
//input [7:0] stb_state_io;
input [7:0] stb_state_rmo;
input stb_alt_sel ;
input [2:0] stb_alt_addr ;
input lsu_dtlb_bypass_e;
input tlb_cam_hit; // m-cycle
input st_dtlb_perr_g ; // enabled st dtlb parity err.
//output stb_non_l2bnk;
output [7:0] stb_clk_en_l;
output [2:0] stb_crnt_ack_id ; // ackid for current outstanding st.
output lsu_stb_empty ; // stb is empty
output [2:0] stb_l2bnk_addr ; // l2bank address.
output [2:1] stb_atm_rq_type ; // identify atomic transaction
output [2:0] stb_wrptr ; // write ptr - per thread
//output [2:0] stb_dfq_rptr ; // rptr for dfq - per thread
output stb_rd_for_pcx ; // rd vld for pcx - per thread
output [2:0] stb_pcx_rptr ; // rptr for pcx - per thread
output [2:0] stb_wrptr_prev ;
output [7:0] stb_state_ced_mod ;
output [7:0] stb_state_vld_out ;
output [3:0] lsu_stbcnt ; // # of vld entries
output stb_rmo_st_issue ; // rmo store issued from thread's stb.
output stb_full ;
output st_pcx_rq_kill_w2 ;
input lsu_outstanding_rmo_st_max;
wire [7:0] stb_state_rst;
wire [7:0] stb_state_vld;
wire [7:0] stb_state_vld_din;
wire [7:0] stb_state_vld_set;
wire [7:0] stb_state_ced;
wire [7:0] stb_state_ced_din;
wire [7:0] stb_state_ced_set;
wire [7:0] stb_state_ack;
wire [7:0] stb_state_ack_din;
wire [7:0] stb_state_ack_set;
wire [3:2] stb_state_si_0; // removed 8x4 bits
wire [3:2] stb_state_si_1;
wire [3:2] stb_state_si_2;
wire [3:2] stb_state_si_3;
wire [3:2] stb_state_si_4;
wire [3:2] stb_state_si_5;
wire [3:2] stb_state_si_6;
wire [3:2] stb_state_si_7;
/*
wire [3:2] stb_state_si_0_din;
wire [3:2] stb_state_si_1_din;
wire [3:2] stb_state_si_2_din;
wire [3:2] stb_state_si_3_din;
wire [3:2] stb_state_si_4_din;
wire [3:2] stb_state_si_5_din;
wire [3:2] stb_state_si_6_din;
wire [3:2] stb_state_si_7_din;
*/
wire [7:0] stb_state_io;
wire [7:0] stb_state_io_din;
wire [7:0] stb_state_rmo;
// wire [7:0] stb_state_rmo_din;
wire [2:1] stb_state_rtype_0; // rm 8x1 bits
wire [2:1] stb_state_rtype_1;
wire [2:1] stb_state_rtype_2;
wire [2:1] stb_state_rtype_3;
wire [2:1] stb_state_rtype_4;
wire [2:1] stb_state_rtype_5;
wire [2:1] stb_state_rtype_6;
wire [2:1] stb_state_rtype_7;
/*
wire [2:1] stb_state_rtype_0_din;
wire [2:1] stb_state_rtype_1_din;
wire [2:1] stb_state_rtype_2_din;
wire [2:1] stb_state_rtype_3_din;
wire [2:1] stb_state_rtype_4_din;
wire [2:1] stb_state_rtype_5_din;
wire [2:1] stb_state_rtype_6_din;
wire [2:1] stb_state_rtype_7_din;
*/
wire [2:0] stb_l2bnk_addr;
wire [2:1] stb_atm_rq_type;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
wire [3:0] stb_wptr_prev ;
wire stb_rptr_dfq_en ;
wire update_stb_wptr ;
//wire [1:0] st_enc_set_way ;
wire [3:0] stb_rptr_dfq_new, stb_rptr_dfq ;
wire valid_entry_for_pcx ;
wire [7:0] dec_wptr_g, dec_rptr_dfq, dec_rptr_pcx, dec_ackptr ;
wire [7:0] dec_wptr_m ;
//wire stb_wvld_g ;
//wire [5:0] stb_inv_set0,stb_inv_set1;
//wire [5:0] stb_inv_set2,stb_inv_set3;
wire ack_vld ;
wire [3:0] stb_wptr_new, stb_wptr ;
wire stb_cam_wvld_g ;
wire [7:0] inflight_vld_g ;
wire dq_vld_d1,dq_vld_d2 ;
wire [7:0] dqptr_d1,dqptr_d2;
wire pcx_rq_for_stb_d1 ;
wire pcx_rq_for_stb_d2,pcx_req_squash_d2 ;
wire clk;
assign clk = rclk;
wire rst_l;
wire stb_ctl_rst_l;
dffrl_async rstff(.din (grst_l),
.q (stb_ctl_rst_l),
.clk (clk), .se(se), .si(), .so(),
.rst_l (arst_l));
assign rst_l = stb_ctl_rst_l;
//=========================================================================================
// RESET
//=========================================================================================
// A flush will reset the vld bit in the stb - it should be the only one as
// the stb has drained.
wire reset;
//waiting int 3.0
//assign rst_l = stb_ctl_rst_l;
assign reset = ~rst_l | flshinst_rst ;
//=========================================================================================
// STB READ FOR PCX
//=========================================================================================
// Assumes that an entry can be sent to the pcx iff the next oldest
// entry has received its ack. This pointer will not look for L2Bank
// overlap as the ptr calculation is much more complicated.
// (1)--> Entry must be valid and not already sent to pcx.
// Includes squashing of speculative req
// (2)--> Previous in linked list must be valid and acked (or invalid)
// (3)--> This is to break the deadlock between oldest and youngest
// entries when queue is full. Oldest entry can always exit to pcx.
// This vector is one-hot. Assumption is that stb is a circular queue.
// deadlock has to be broken between oldest and youngest entry when the
// queue is full. The dfq ptr is used to mark oldest
dff_s #(2) rq_stgd1 (
.din ({pcx_rq_for_stb_d1,pcx_req_squash}),
.q ({pcx_rq_for_stb_d2,pcx_req_squash_d2}),
.clk (clk),
.se (se), .si (), .so ()
);
wire ffu_bst_wr_g ;
dff_s #(1) ff_bstg (
.din (lsu_blk_st_m),
.q (ffu_bst_wr_g),
.clk (clk),
.se (se), .si (), .so ()
);
wire full_flush_st_g ;
// flush_pipe does not apply to blk st wr.
assign full_flush_st_g = (stb_flush_st_g | (lsu_stbctl_flush_pipe_w & ~ffu_bst_wr_g)) & stb_cam_wvld_g ;
// timing fix: 5/6 - begin
// qual dec_rptr_pcx w/ tlb camhit and in qctl1 move kill qual after store pick
wire tlb_cam_hit_g, tlb_hit_g;
wire dtlb_bypass_m, dtlb_bypass_g ;
dff_s #(1) ff_dtlb_bypass_m (
.din (lsu_dtlb_bypass_e),
.q (dtlb_bypass_m),
.clk (clk),
.se (se), .si (), .so ()
);
dff_s #(1) ff_dtlb_bypass_g (
.din (dtlb_bypass_m),
.q (dtlb_bypass_g),
.clk (clk),
.se (se), .si (), .so ()
);
dff_s #(1) ff_tlb_cam_hit_g (
.din (tlb_cam_hit),
.q (tlb_cam_hit_g),
.clk (clk),
.se (se), .si (), .so ()
);
assign tlb_hit_g = tlb_cam_hit_g | dtlb_bypass_g | ffu_bst_wr_g; //bug6406/eco6610
// timing fix: 5/6 - end
// st rq can now speculate on flush
assign inflight_vld_g[7:0] =
dec_wptr_g[7:0] & {8{stb_cam_wvld_g & thrd_en_g}} ;
// the later term is for an inflight ld which gets squashed. It
// should not effect dec_rptr_pcx. This is related to a timing fix
// where the flush is taken out of inflight_vld_g.
//assign inflight_vld_g[7:0] = dec_wptr_g[7:0] & {8{stb_wvld_g & thrd_en_g}} ;
//timing fix: 5/6/03 - kill inflight vld if tlb_hit_g=0; dec_rptr_pcx will be 0 and hence kill_w2 will be 0
// leave inflight_vld_g as is, since it is used to set squash - which eventually reset state_vld
wire [7:0] inflight_issue_g_tmp ;
assign inflight_issue_g_tmp[7:0] = inflight_vld_g[7:0] & {8{tlb_hit_g}};
wire [7:0] inflight_issue_g ;
assign inflight_issue_g[7:0] =
inflight_issue_g_tmp[7:0] & {8{~(|(stb_state_vld[7:0] & ~stb_state_ack[7:0]))}};
//inflight_vld_g[7:0] & {8{~(|(stb_state_vld[7:0] & ~stb_state_ack[7:0]))}}; // timing fix : 5/6
// Modified state ced includes in-flight pcx sel which is not squashed.
// Timing : pcx_req_squash delayed. A st that is squashed can then make a request 3-cycles
// later.
wire skid_ced, st_vld_rq_d2 ;
assign st_vld_rq_d2 = pcx_rq_for_stb_d2 & ~pcx_req_squash_d2 ;
assign skid_ced = pcx_rq_for_stb_d1 | st_vld_rq_d2 ;
// For squashing rawp.
assign stb_state_ced_mod[7:0] =
((dec_ackptr[7:0] & {8{st_vld_rq_d2}}) | stb_state_ced[7:0]) ;
//RMO st counter satuated
wire rmo_st_satuated;
//dff #(1) rmo_st_satuated_ff (
// .din (lsu_outstanding_rmo_st_max),
// .q (rmo_st_satuated),
// .clk (clk),
// .se (se), .si (), .so ()
//);
assign rmo_st_satuated = lsu_outstanding_rmo_st_max;
wire [7:0] stb_state_ced_spec ;
assign stb_state_ced_spec[7:0] =
((dec_ackptr[7:0] & {8{skid_ced}}) | stb_state_ced[7:0]) |
(stb_state_rmo[7:0] & {8{rmo_st_satuated}});
assign dec_rptr_pcx[7:0] =
(inflight_issue_g[7:0] | stb_state_vld[7:0])
//(inflight_vld_g[7:0] | stb_state_vld[7:0])
& ~stb_state_ced_spec[7:0] & // -->(1)
(({stb_state_vld[6:0],stb_state_vld[7]} & //
{stb_state_ack[6:0],stb_state_ack[7]}) //
| ~{stb_state_vld[6:0],stb_state_vld[7]} // -->(2)
| dec_rptr_dfq[7:0]) ; // -->(3)
// There should be only one such entry i.e., the vector is 1-hot.
// Incorporate st dtlb parity error. It should not propagate to memory.
// Tracing full_flush_st_g, note that the pointers will not be restored
// correctly for timing reasons - anyway, this is considered unrecoverable.
// Monitor !
assign valid_entry_for_pcx = |dec_rptr_pcx[7:0] ;
wire any_inflight_iss_g,any_inflight_iss_w2 ;
assign any_inflight_iss_g = |inflight_vld_g[7:0] ;
wire pick_inflight_iss_g,pick_inflight_iss_w2 ;
assign pick_inflight_iss_g = |(dec_rptr_pcx[7:0] & inflight_issue_g[7:0]) ;
wire st_pcx_rq_kill_g ;
assign st_pcx_rq_kill_g = pick_inflight_iss_g & full_flush_st_g ;
//assign st_pcx_rq_kill_g = (|(dec_rptr_pcx[7:0] & inflight_issue_g[7:0])) & full_flush_st_g ;
wire st_vld_squash_g,st_vld_squash_w2 ;
assign st_vld_squash_g = any_inflight_iss_g & full_flush_st_g ;
//assign st_vld_squash_g = (|inflight_vld_g[7:0]) & full_flush_st_g ;
wire st_pcx_rq_kill_tmp,st_vld_squash_tmp ;
wire st_dtlb_perr_w2 ;
dff_s #(5) stkill_stgd1 (
.din ({st_pcx_rq_kill_g,st_vld_squash_g,
any_inflight_iss_g,pick_inflight_iss_g,st_dtlb_perr_g}),
.q ({st_pcx_rq_kill_tmp,st_vld_squash_tmp,
any_inflight_iss_w2,pick_inflight_iss_w2,st_dtlb_perr_w2}),
.clk (clk),
.se (se), .si (), .so ()
);
assign st_pcx_rq_kill_w2 =
st_pcx_rq_kill_tmp |
(pick_inflight_iss_w2 & st_dtlb_perr_w2);
assign st_vld_squash_w2 =
st_vld_squash_tmp |
(any_inflight_iss_w2 & st_dtlb_perr_w2);
// Encode pcx rptr
// ** Timing : Could put flop in rwctl.
assign stb_pcx_rptr[0] = dec_rptr_pcx[1] | dec_rptr_pcx[3] | dec_rptr_pcx[5] | dec_rptr_pcx[7] ;
assign stb_pcx_rptr[1] = dec_rptr_pcx[2] | dec_rptr_pcx[3] | dec_rptr_pcx[6] | dec_rptr_pcx[7] ;
assign stb_pcx_rptr[2] = dec_rptr_pcx[4] | dec_rptr_pcx[5] | dec_rptr_pcx[6] | dec_rptr_pcx[7] ;
// This is used in qctl.
// Timing : flopped in qctl before use.
assign stb_rd_for_pcx = valid_entry_for_pcx ;
//=========================================================================================
// STB READ FOR DFQ
//=========================================================================================
// Read Pointer to generate the next available entry for the dfq.
// Timing : This should be fine as st_ack_dq_stb is decode out of dfq byp flop.
wire incr_dfq_ptr ;
// stb_rmo_st_issue added for rmo st bug - if critical then add flop.
// bug2983: incr_dfq_ptr is set by both st_ack_dq_stb and stb_rmo_st_issue
// in the same cycle. this results in losing a dequeue.
//
// fix is to detect rmo store after regular store. issue the rmo
// store and dont reset the rmo store vld until the dequeue of the older
// regular store.
wire stb_dq_rmo ;
//assign incr_dfq_ptr = st_ack_dq_stb | stb_rmo_st_issue ; //bug 2983
assign incr_dfq_ptr = st_ack_dq_stb | stb_dq_rmo ;
assign stb_rptr_dfq_new[3:0] = stb_rptr_dfq[3:0] + {3'b0, incr_dfq_ptr} ;
//assign stb_rptr_dfq_new[3:0] = stb_rptr_dfq[3:0] + {3'b0, st_ack_dq_stb} ;
assign stb_rptr_dfq_en = st_ack_dq_stb | incr_dfq_ptr ;
dffre_s #(4) rptr_d (
.din (stb_rptr_dfq_new[3:0]),.q (stb_rptr_dfq[3:0]),
.en (stb_rptr_dfq_en), .rst (reset),
.clk (clk),
.se (se), .si (), .so ()
);
//assign stb_dfq_rptr[2:0] = stb_rptr_dfq_new[2:0] ;
// Decode Read Ptr
// Generated cycle before actual read.
assign dec_rptr_dfq[0] = ~stb_rptr_dfq[2] & ~stb_rptr_dfq[1] & ~stb_rptr_dfq[0] ;
assign dec_rptr_dfq[1] = ~stb_rptr_dfq[2] & ~stb_rptr_dfq[1] & stb_rptr_dfq[0] ;
assign dec_rptr_dfq[2] = ~stb_rptr_dfq[2] & stb_rptr_dfq[1] & ~stb_rptr_dfq[0] ;
assign dec_rptr_dfq[3] = ~stb_rptr_dfq[2] & stb_rptr_dfq[1] & stb_rptr_dfq[0] ;
assign dec_rptr_dfq[4] = stb_rptr_dfq[2] & ~stb_rptr_dfq[1] & ~stb_rptr_dfq[0] ;
assign dec_rptr_dfq[5] = stb_rptr_dfq[2] & ~stb_rptr_dfq[1] & stb_rptr_dfq[0] ;
assign dec_rptr_dfq[6] = stb_rptr_dfq[2] & stb_rptr_dfq[1] & ~stb_rptr_dfq[0] ;
assign dec_rptr_dfq[7] = stb_rptr_dfq[2] & stb_rptr_dfq[1] & stb_rptr_dfq[0] ;
// Stge dfq ptr and dq vld by 2-cycles to appropriate invalidation pt
dff_s #(9) dq_stgd1 (
.din ({dec_rptr_dfq[7:0],st_ack_dq_stb}),
.q ({dqptr_d1[7:0],dq_vld_d1}),
.clk (clk),
.se (se), .si (), .so ()
);
dff_s #(9) dq_stgd2 (
.din ({dqptr_d1[7:0],dq_vld_d1}),
.q ({dqptr_d2[7:0],dq_vld_d2}),
.clk (clk),
.se (se), .si (), .so ()
);
//=========================================================================================
// WPTR FOR STB
//=========================================================================================
// It is assumed that if there is a store in the pipe, there is a
// free entry in the corresponding stb. Otherwise, the pipe would've
// have stalled for the thread. This is maintained locally instead of in
// stb rw ctl.
// 00(flush,wr) - no update,01 - +1,10 - d1,11 - no update
// cam or data wr ptr would do.
//assign update_stb_wptr = stb_cam_wvld_m | stb_flush_st_g ;
assign update_stb_wptr = stb_cam_wvld_m ^ (full_flush_st_g | st_dtlb_perr_g);
assign stb_wptr_new[3:0] = (full_flush_st_g | st_dtlb_perr_g) ?
stb_wptr_prev[3:0] :
stb_wptr[3:0] + {3'b0, stb_cam_wvld_m} ;
dff_s wvld_stgg (
.din (stb_cam_wvld_m), .q (stb_cam_wvld_g),
.clk (clk),
.se (se), .si (), .so ()
);
//assign stb_wvld_g = stb_cam_wvld_g & ~full_flush_st_g ;
dffre_s #(4) wptr_new (
.din (stb_wptr_new[3:0]), .q (stb_wptr[3:0]),
.en (update_stb_wptr), .rst (reset),
.clk (clk),
.se (se), .si (), .so ()
);
assign stb_wrptr[2:0] = stb_wptr[2:0] ;
wire [2:0] stb_wptr_m ;
// flush should not be required. If the previous st is flushed then
// the current st should be invalid.
assign stb_wptr_m[2:0] = stb_wptr[2:0] ;
/*assign stb_wptr_m[3:0] = (full_flush_st_g) ?
stb_wptr_prev[3:0] :
stb_wptr[3:0] ;*/
// Decode wptr
assign dec_wptr_m[0] = ~stb_wptr_m[2] & ~stb_wptr_m[1] & ~stb_wptr_m[0] ;
assign dec_wptr_m[1] = ~stb_wptr_m[2] & ~stb_wptr_m[1] & stb_wptr_m[0] ;
assign dec_wptr_m[2] = ~stb_wptr_m[2] & stb_wptr_m[1] & ~stb_wptr_m[0] ;
assign dec_wptr_m[3] = ~stb_wptr_m[2] & stb_wptr_m[1] & stb_wptr_m[0] ;
assign dec_wptr_m[4] = stb_wptr_m[2] & ~stb_wptr_m[1] & ~stb_wptr_m[0] ;
assign dec_wptr_m[5] = stb_wptr_m[2] & ~stb_wptr_m[1] & stb_wptr_m[0] ;
assign dec_wptr_m[6] = stb_wptr_m[2] & stb_wptr_m[1] & ~stb_wptr_m[0] ;
assign dec_wptr_m[7] = stb_wptr_m[2] & stb_wptr_m[1] & stb_wptr_m[0] ;
dff_s #(8) dwptr_stgg (
.din (dec_wptr_m[7:0]), .q (dec_wptr_g[7:0]),
.clk (clk),
.se (se), .si (), .so ()
);
// stb_wptr_prev represents the latest valid entry in stb
/*dffre #(4) wptr_prev (
.din (stb_wptr[3:0]), .q (stb_wptr_prev[3:0]),
.en (update_stb_wptr), .rst (reset),
.clk (clk),
.se (se), .si (), .so ()
);*/
assign stb_wptr_prev[3:0] = stb_wptr[3:0] - {4'b0001} ;
// Bug 2419 - In case this is a critical path, a flop can be inserted.
assign stb_wrptr_prev[2:0] = stb_wptr_prev[2:0] ;
//=========================================================================================
// # OF STORES IN STB
//=========================================================================================
wire [3:0] stb_wptr_w2 ;
// Count should not include stores in pipe-stages 'g' or before.
dff_s #(4) wptr_stgw2 (
.din (stb_wptr[3:0]), .q (stb_wptr_w2[3:0]),
.clk (clk),
.se (se), .si (), .so ()
);
assign lsu_stbcnt[3:0] = (stb_wptr_w2[3:0] - stb_rptr_dfq[3:0]) ;
// Performance Cntr Info
wire stb_full_w2 ;
assign stb_full_w2 = lsu_stbcnt[2] & lsu_stbcnt[1] & lsu_stbcnt[0] ;
dff_s sfull (
.din (stb_full_w2), .q (stb_full),
.clk (clk),
.se (se), .si (), .so ()
);
//=========================================================================================
// CONTROL STATE
//=========================================================================================
// (V) - Valid State. Initialized by write and cleared once entry
// has written DFQ and then written the cache. If the store
// will only bypass then it still needs to enter DFQ but
// can be deallocated immediately on entry into DFQ. (1b)
// (A) - (NA) Allocate. Determined on read of cache. May be modified by
// invalidate or st mv'ing to DFQ. The load woust have to
// have same set index and same replacement way to clear A bit. (1b)
// (SI) - cache set index for invalidate/load cam'ing. (6b)
// (WY) - (NA) Allocate way for store. (2b)
// (CED) - Committed to SKB. Entry written to SKB. (1b)
// (ACK) - Ack for store received from L2. (1b)
// (UPD) - (NA) Entry mv'ed to DFQ. (1b)
// (W) - (NA) Wrap bit. (1b) <--- Not used
// * All state needs to be reset when entry is freed.
//
// Total - 14b.
// ack_id is internally tracked.
// There can only be one outstanding
dffre_s #(8) ackptr_ff (
.din (dec_rptr_pcx[7:0]), .q (dec_ackptr[7:0]),
.en (pcx_rq_for_stb), .rst (reset),
.clk (clk),
.se (se), .si (), .so ()
);
assign ack_vld = cpx_st_ack_tid ;
//assign st_dc_hit_g = lsu_st_hit_g ;
assign stb_crnt_ack_id[0] = dec_ackptr[1] | dec_ackptr[3] |
dec_ackptr[5] | dec_ackptr[7] ;
assign stb_crnt_ack_id[1] = dec_ackptr[2] | dec_ackptr[3] |
dec_ackptr[6] | dec_ackptr[7] ;
assign stb_crnt_ack_id[2] = dec_ackptr[4] | dec_ackptr[5] |
dec_ackptr[6] | dec_ackptr[7] ;
// Decode valid dequeue ids arriving from dfq.
// pa[39:36]
// 0x00-0x7f dram
// 0xa0-0xbf l2csr
// others as non l2 accsess = b39 & ~(~b38 & b37)
// timing fix: stb_non_l2bnk is delayed 1 cycle - gen in w/g cycle
//assign stb_non_l2bnk = stb_alt_sel ?
// stb_alt_addr[2] & ~(~stb_alt_addr[1] & stb_alt_addr[0]) :
// tlb_pgnum_m[39] & ~(~tlb_pgnum_m[38] & tlb_pgnum_m[37]) & ~flsh_inst_m;
wire [2:0] stb_alt_addr_g;
wire stb_alt_sel_g;
dff_s #(4) ff_alt_addr_g (
.din ({stb_alt_sel,stb_alt_addr[2:0]}),
.q ({stb_alt_sel_g,stb_alt_addr_g[2:0]}),
.clk (clk),
.se (se), .si (), .so ()
);
wire flsh_inst_g;
dff_s #(1) ff_flsh_inst_g (
.din (flsh_inst_m),
.q (flsh_inst_g),
.clk (clk),
.se (se), .si (), .so ()
);
wire stb_alt_io_g , tlb_pgnum_io_g ;
assign stb_alt_io_g =
stb_alt_addr_g[2] & ~(~stb_alt_addr_g[1] & stb_alt_addr_g[0]);
assign tlb_pgnum_io_g =
tlb_pgnum_g[39] & ~(~tlb_pgnum_g[38] & tlb_pgnum_g[37]) & ~flsh_inst_g;
// used as input to state_io in stb_ctldp
wire stb_non_l2bnk_g;
assign stb_non_l2bnk_g =
stb_alt_sel_g ? stb_alt_io_g :
tlb_pgnum_io_g ;
// used as output to qctl1 - this has to be qual'ed w/dec_rptr_pcx so no x's propagate
//alt_sel_g state_vld comment
// 0 0 select tlb_pgnum_io_g(bypass)
// 0 1 select stb_state_io
// 1 0 select stb_alt_io_g
// 1 1 select stb_alt_io_g
wire [7:0] stb_l2bnk_addr_b2;
// inflight (stb_alt / tlb)
// stb
// bug3875
assign stb_l2bnk_addr_b2[0] =
stb_state_vld[0] ? stb_state_io[0] :
stb_alt_sel_g ? stb_alt_io_g :
tlb_pgnum_io_g ;
assign stb_l2bnk_addr_b2[1] =
stb_state_vld[1] ? stb_state_io[1] :
stb_alt_sel_g ? stb_alt_io_g :
tlb_pgnum_io_g ;
assign stb_l2bnk_addr_b2[2] =
stb_state_vld[2] ? stb_state_io[2] :
stb_alt_sel_g ? stb_alt_io_g :
tlb_pgnum_io_g ;
assign stb_l2bnk_addr_b2[3] =
stb_state_vld[3] ? stb_state_io[3] :
stb_alt_sel_g ? stb_alt_io_g :
tlb_pgnum_io_g ;
assign stb_l2bnk_addr_b2[4] =
stb_state_vld[4] ? stb_state_io[4] :
stb_alt_sel_g ? stb_alt_io_g :
tlb_pgnum_io_g ;
assign stb_l2bnk_addr_b2[5] =
stb_state_vld[5] ? stb_state_io[5] :
stb_alt_sel_g ? stb_alt_io_g :
tlb_pgnum_io_g ;
assign stb_l2bnk_addr_b2[6] =
stb_state_vld[6] ? stb_state_io[6] :
stb_alt_sel_g ? stb_alt_io_g :
tlb_pgnum_io_g ;
assign stb_l2bnk_addr_b2[7] =
stb_state_vld[7] ? stb_state_io[7] :
stb_alt_sel_g ? stb_alt_io_g :
tlb_pgnum_io_g ;
dff_s rqsel_stgg (
.din (pcx_rq_for_stb), .q (pcx_rq_for_stb_d1),
.clk (clk),
.se (se), .si (), .so ()
);
// Use of tlb_pgnum_m will be critical !!!
//always @( posedge clk)
// begin
// for (i=0;i<8;i=i+1)
// begin
// if (reset // reset
// | (dqptr_d2[i] & dq_vld_d2) // dequeue from stb
// | (dec_ackptr[i] & pcx_rq_for_stb_d1 &
// ~pcx_req_squash & stb_state_rmo[i]))
// // write will be visible in cache.
// begin
// stb_state_vld[i] <= 1'b0 ;
// stb_state_ced[i] <= 1'b0 ;
// stb_state_ack[i] <= 1'b0 ;
// end
// if (dec_wptr_g[i] & stb_wvld_g & thrd_en_g )
// begin
// stb_state_vld[i] <= 1'b1 ;
// stb_state_wy[i] <= st_enc_set_way[1:0];
// end
// if (dec_wptr_m[i] & stb_cam_wvld_m) // spec. write
// begin
// stb_state_si[i] <= lsu_ldst_va_m[9:4] ;
// stb_state_rtype[i] <= lsu_st_rq_type_m[2:0] ;
// stb_state_io[i] <= non_l2bnk ;
// stb_state_rmo[i] <= lsu_st_rmo_m ;
// end
// // atomic will not write to cache even if it hits.
// // rd_for_pcx needs to be gated for a cycle.
// // This is delayed by a cycle to take into account
// // squashing of speculative requests.
// // rmo's will dequeue entry immediately.
// if (dec_ackptr[i] & pcx_rq_for_stb_d1 & ~pcx_req_squash & ~stb_state_rmo[i])
// stb_state_ced[i] = 1'b1 ;
// if (dec_ackptr[i] & ack_vld)
// stb_state_ack[i] = 1'b1 ;
// end
// end
// UNIFY : mux select destination address of pcx pkt
// always->dff translation begin
// =================================
// rst set din
// 0 0 q
// 1 0 0 (reset)
// x 1 1 (set)
// ==================================
// din = set | (~r & q)
//vld
wire [7:0] stb_issue_rmo ;
wire [7:0] flush_vld_w2 ;
// Timing
assign stb_issue_rmo[7:0] =
(dec_ackptr[7:0] & {8{st_vld_rq_d2}} & stb_state_rmo[7:0]) ;
// (dec_ackptr[7:0] & {8{pcx_rq_for_stb_d1}} &
// {8{~pcx_req_squash}} & stb_state_rmo[7:0]) ;
assign stb_rmo_st_issue = |stb_issue_rmo[7:0] ;
//bug2983 - begin
wire rmo_pend,rmo_pend_d1;
wire [7:0] rmo_pend_ackptr , stb_dq_rmo_dfq_ptr;
// this will set 1 cycle after pcx_rq_for_stb and before the corresponding ced is set(which is 2 cycles
// after pcx_rq_for_stb
//bug3249: dec_rptr_dfq catches up w/ dec_ackptr; i.e. dec_ackptr entry is the oldset. rmo_pend should not
// be set in this case based on previuos entry (since it will be the youngest)
// fix - kill pend if issue and dq ptr are same (~{8{|(dec_ackptr[7:0] & dec_rptr_dfq[7:0])}})
assign rmo_pend_ackptr[7:0] =
// is the current req RMO store
//(dec_ackptr[7:0] & stb_state_rmo[7:0]) & //bug3249
//(dec_ackptr[7:0] & stb_state_rmo[7:0] & ~dec_rptr_dfq[7:0]) & //bug7100 new fix, bug7117
(dec_ackptr[7:0] & stb_state_rmo[7:0] & ~dqptr_d2[7:0]) &
// is the older store a regular store
({stb_state_vld[6:0],stb_state_vld[7]} & ~{stb_state_rmo[6:0],stb_state_rmo[7]});
assign rmo_pend = |rmo_pend_ackptr[7:0];
wire rmo_pend_rst;
assign rmo_pend_rst = reset | stb_dq_rmo;
dffre_s #(1) ff_rmo_pend (
.din (rmo_pend),
.q (rmo_pend_d1),
.en (st_vld_rq_d2),
.rst (rmo_pend_rst),
.clk (clk),
.se (se), .si (), .so ()
);
// ok to use either dec_ackptr[7:0] OR dec_rptr_dfq[7:0] 'cos the stores younger to 1st RMO store
// are not issued ('cos vld of RMO store is not reset). Hence ackptr and rptr_dfq will be the same
// when rmo_pend=0.
//
// has to qual'ed w/ st_vld_rq_d2. otherwise can result in vld reset before ced is set. the next
// time the entry is used it will have ced=1 and not issue.
//
// cannot use rmo_pend_ackptr[7:0] instead of dec_ackptr[7:0] 'cos the former will be reset when
// rmo_pend=0 and will not dequeue the rmo stb entry. i.e if rmo_pend=1 when st_vld_rq_d2=1, use
// dec_ackptr[7:0]
//------------------------------------------------------------------------------------------------
// Case 1: NO older regular store vld dequeue pending
//------------------------------------------------------------------------------------------------
// | 1 | 2 | 3 | 4 | 5 | | |
// stb_state_vld=8'h1------------------------------------->8'h0
// stb_state_rmo=8'h1
//
// pcx_rq_for_stb=1-------->0
//
// dec_ackptr=8'h0--------->8'h1
//
// st_vld_rq_d2=0--------------------->1 0
// stb_issue_rmo=8'h0-------------->8'h1 8'h0
// stb_dq_rmo_dfq_ptr=8'h0--------->8'h1 8'h0
//
// rmo_pend=0
// rmo_pend_d1=0
//
// dq_vld_d2=0
// dqptr_d2=8'h0
//------------------------------------------------------------------------------------------------
// Case 2: older regular store vld dequeue pending(entry0-older reg store; entry1-rmo younger store)
//------------------------------------------------------------------------------------------------
// | 1 | 2 | 3 | 4 | 5 | 6 | |
// stb_state_vld=8'h3-------------------------------------->8'h2 8'h0
// stb_state_rmo=8'h2
// stb_state_ack=8'h1-------------------------------------->8'h0
//
// pcx_rq_for_stb=1-------------->0
//
// dec_ackptr=8'h1------------>8'h2
//
// st_vld_rq_d2=0-------------------------->1 0
// stb_issue_rmo=8'h0------------------->8'h1 8'h0
// stb_dq_rmo_dfq_ptr=8'h0--------------------------------->8'h2 8'h0 (dequeue rmo store)
//
// rmo_pend=0-------------------->1 0
// rmo_pend_d1=0--------------------------->1 0
//
// dq_vld_d2=0-------------------------------------->1 0
// dqptr_d2=8'h0--------------------------------->8'h1 8'h0 (dequeue regular store)
//------------------------------------------------------------------------------------------------
assign stb_dq_rmo_dfq_ptr[7:0] =
(stb_issue_rmo[7:0] & ~rmo_pend_ackptr[7:0]) | // if rmo_pend=0 when st_vld_rq_d2=1
(dec_ackptr[7:0] & {8{rmo_pend_d1 & ~rmo_pend}}); // if rmo_pend=1 when st_vld_rq_d2=1
assign stb_dq_rmo = |stb_dq_rmo_dfq_ptr[7:0];
//bug2983 - end
assign stb_state_rst[7:0] =
{8{reset}} | (dqptr_d2[7:0] & {8{dq_vld_d2}})
// reset vld,ced,ack immed. on issue to pcx for rmo store.
| stb_dq_rmo_dfq_ptr[7:0] | // fix for bug2983
// | stb_issue_rmo[7:0] | // bug2983
flush_vld_w2[7:0] ; // because of trap
// vld is now speculatively written
assign stb_state_vld_set[7:0] = dec_wptr_g[7:0] & {8{stb_cam_wvld_g & thrd_en_g}} ;
//assign stb_state_vld_set[7:0] = dec_wptr_g[7:0] & {8{stb_wvld_g & thrd_en_g}} ;
assign stb_state_vld_din[7:0] = stb_state_vld_set[7:0] |
(~stb_state_rst[7:0] & stb_state_vld[7:0]);
wire [7:0] stb_state_vld_tmp ;
dff_s #(8) ff_stb_state_vld (
.din (stb_state_vld_din[7:0]),
.q (stb_state_vld_tmp[7:0] ),
.clk (clk),
.se (se), .si (), .so ()
);
assign stb_state_vld[7:0] = stb_state_vld_tmp[7:0] & ~flush_vld_w2[7:0] ;
wire [7:0] stb_state_vld_set_w2 ;
dff_s #(8) ff_stb_state_vld_set (
.din (stb_state_vld_set[7:0]),
.q (stb_state_vld_set_w2[7:0] ),
.clk (clk),
.se (se), .si (), .so ()
);
assign flush_vld_w2[7:0] = stb_state_vld_set_w2[7:0] & {8{st_vld_squash_w2}} ;
// The stb valids for the scm need not include the intermediate flush condition
// (flush_vld_w2). It is assumed that the flush of the store will invalidate
// a subsequent ld. (8 extra flops).
// Bug 3201 - rmo st are made invisible to loads.
wire [7:0] st_scm_vld ;
assign st_scm_vld[7:0] = stb_state_vld_din[7:0] & ~stb_state_rmo[7:0] ;
dff_s #(8) ff_st_scm_vld (
.din (st_scm_vld[7:0]),
.q (stb_state_vld_out[7:0] ),
.clk (clk),
.se (se), .si (), .so ()
);
//ced
assign stb_state_ced_set[7:0] = dec_ackptr[7:0] & {8{st_vld_rq_d2}} ;
// Timing fix.
//assign stb_state_ced_set[7:0] = dec_ackptr[7:0] & {8{pcx_rq_for_stb_d1 & ~pcx_req_squash}};
// make reset dominant - specifically for coincident set and reset by rmo st.
assign stb_state_ced_din[7:0] = ~stb_state_rst[7:0] &
(stb_state_ced_set[7:0] | stb_state_ced[7:0]);
//assign stb_state_ced_din[7:0] = stb_state_ced_set[7:0] |
// (~stb_state_rst[7:0] & stb_state_ced[7:0]);
dff_s #(8) ff_stb_state_ced (
.din (stb_state_ced_din[7:0]),
.q (stb_state_ced[7:0] ),
.clk (clk),
.se (se), .si (), .so ()
);
//ack
assign stb_state_ack_set[7:0] = dec_ackptr[7:0] & {8{ack_vld}};
assign stb_state_ack_din[7:0] = stb_state_ack_set[7:0] |
(~stb_state_rst[7:0] & stb_state_ack[7:0]);
dff_s #(8) ff_stb_state_ack (
.din (stb_state_ack_din[7:0]),
.q (stb_state_ack[7:0] ),
.clk (clk),
.se (se), .si (), .so ()
);
//spec. write
wire [7:0] spec_wrt;
assign spec_wrt [7:0] = dec_wptr_m[7:0] & {8{stb_cam_wvld_m}};
assign stb_clk_en_l [7:0] = ~spec_wrt[7:0];
//spec write Ffs move to lsu_stb_ctldp to save area
// moved state_io logic from ctldp
assign stb_state_io_din[7:0] = (stb_state_vld_set[7:0] & {8{stb_non_l2bnk_g}}) |
(~stb_state_rst[7:0] & stb_state_io[7:0]);
dff_s #(8) ff_stb_state_io (
.din (stb_state_io_din[7:0]),
.q (stb_state_io[7:0] ),
.clk (clk),
.se (se), .si (), .so ()
);
// always->dff translation end
// streaming unit does not have to care about outstanding rmo sparc-stores.
// membar will take care of that. spu must insert appr. delay in sampling signal.
assign lsu_stb_empty = ~(|stb_state_vld[7:0]);
//=========================================================================================
// SELECT L2BANK ADDRESS
//=========================================================================================
//reg [5:0] temp ;
//reg [2:0] stb_l2bnk_addr ;
//// This is modelling a mux.
//always @(/*AUTOSENSE*/ /*memory or*/ dec_rptr_pcx)
// begin
// for (j=0;j<8;j=j+1)
// if (dec_rptr_pcx[j]) // 1-hot
// begin
// temp[5:0] = stb_state_si[j] ;
// stb_l2bnk_addr[2:0] = {stb_state_io[j],temp[4:3]} ;
// stb_atm_rq_type[2:0] = stb_state_rtype[j] ;
// end
// end
//always->and-or translation begin
assign stb_l2bnk_addr[2:0] = {3{dec_rptr_pcx[0]}} & {stb_l2bnk_addr_b2[0], stb_state_si_0[3:2]} |
{3{dec_rptr_pcx[1]}} & {stb_l2bnk_addr_b2[1], stb_state_si_1[3:2]} |
{3{dec_rptr_pcx[2]}} & {stb_l2bnk_addr_b2[2], stb_state_si_2[3:2]} |
{3{dec_rptr_pcx[3]}} & {stb_l2bnk_addr_b2[3], stb_state_si_3[3:2]} |
{3{dec_rptr_pcx[4]}} & {stb_l2bnk_addr_b2[4], stb_state_si_4[3:2]} |
{3{dec_rptr_pcx[5]}} & {stb_l2bnk_addr_b2[5], stb_state_si_5[3:2]} |
{3{dec_rptr_pcx[6]}} & {stb_l2bnk_addr_b2[6], stb_state_si_6[3:2]} |
{3{dec_rptr_pcx[7]}} & {stb_l2bnk_addr_b2[7], stb_state_si_7[3:2]} ;
assign stb_atm_rq_type[2:1]= {2{dec_rptr_pcx[0]}} & stb_state_rtype_0[2:1] |
{2{dec_rptr_pcx[1]}} & stb_state_rtype_1[2:1] |
{2{dec_rptr_pcx[2]}} & stb_state_rtype_2[2:1] |
{2{dec_rptr_pcx[3]}} & stb_state_rtype_3[2:1] |
{2{dec_rptr_pcx[4]}} & stb_state_rtype_4[2:1] |
{2{dec_rptr_pcx[5]}} & stb_state_rtype_5[2:1] |
{2{dec_rptr_pcx[6]}} & stb_state_rtype_6[2:1] |
{2{dec_rptr_pcx[7]}} & stb_state_rtype_7[2:1] ;
//always->and-or translation end
endmodule
|
// system_acl_iface_acl_kernel_clk_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.0 200 at 2015.04.28.12:23:19
`timescale 1 ps / 1 ps
module system_acl_iface_acl_kernel_clk_mm_interconnect_0 (
input wire clk_clk_clk, // clk_clk.clk
input wire global_routing_kernel_clk_global_clk_clk, // global_routing_kernel_clk_global_clk.clk
input wire counter_clk_reset_reset_bridge_in_reset_reset, // counter_clk_reset_reset_bridge_in_reset.reset
input wire ctrl_reset_reset_bridge_in_reset_reset, // ctrl_reset_reset_bridge_in_reset.reset
input wire [10:0] ctrl_m0_address, // ctrl_m0.address
output wire ctrl_m0_waitrequest, // .waitrequest
input wire [0:0] ctrl_m0_burstcount, // .burstcount
input wire [3:0] ctrl_m0_byteenable, // .byteenable
input wire ctrl_m0_read, // .read
output wire [31:0] ctrl_m0_readdata, // .readdata
output wire ctrl_m0_readdatavalid, // .readdatavalid
input wire ctrl_m0_write, // .write
input wire [31:0] ctrl_m0_writedata, // .writedata
input wire ctrl_m0_debugaccess, // .debugaccess
output wire [1:0] counter_s_address, // counter_s.address
output wire counter_s_write, // .write
output wire counter_s_read, // .read
input wire [31:0] counter_s_readdata, // .readdata
output wire [31:0] counter_s_writedata, // .writedata
output wire [3:0] counter_s_byteenable, // .byteenable
input wire counter_s_readdatavalid, // .readdatavalid
input wire counter_s_waitrequest, // .waitrequest
output wire pll_lock_avs_0_s_read, // pll_lock_avs_0_s.read
input wire [31:0] pll_lock_avs_0_s_readdata, // .readdata
output wire [5:0] pll_reconfig_0_mgmt_avalon_slave_address, // pll_reconfig_0_mgmt_avalon_slave.address
output wire pll_reconfig_0_mgmt_avalon_slave_write, // .write
output wire pll_reconfig_0_mgmt_avalon_slave_read, // .read
input wire [31:0] pll_reconfig_0_mgmt_avalon_slave_readdata, // .readdata
output wire [31:0] pll_reconfig_0_mgmt_avalon_slave_writedata, // .writedata
input wire pll_reconfig_0_mgmt_avalon_slave_waitrequest, // .waitrequest
output wire [7:0] pll_rom_s1_address, // pll_rom_s1.address
output wire pll_rom_s1_write, // .write
input wire [31:0] pll_rom_s1_readdata, // .readdata
output wire [31:0] pll_rom_s1_writedata, // .writedata
output wire [3:0] pll_rom_s1_byteenable, // .byteenable
output wire pll_rom_s1_chipselect, // .chipselect
output wire pll_rom_s1_clken, // .clken
output wire pll_rom_s1_debugaccess, // .debugaccess
output wire pll_sw_reset_s_write, // pll_sw_reset_s.write
output wire pll_sw_reset_s_read, // .read
input wire [31:0] pll_sw_reset_s_readdata, // .readdata
output wire [31:0] pll_sw_reset_s_writedata, // .writedata
output wire [3:0] pll_sw_reset_s_byteenable, // .byteenable
input wire pll_sw_reset_s_waitrequest, // .waitrequest
output wire version_id_0_s_read, // version_id_0_s.read
input wire [31:0] version_id_0_s_readdata // .readdata
);
wire ctrl_m0_translator_avalon_universal_master_0_waitrequest; // ctrl_m0_agent:av_waitrequest -> ctrl_m0_translator:uav_waitrequest
wire [2:0] ctrl_m0_translator_avalon_universal_master_0_burstcount; // ctrl_m0_translator:uav_burstcount -> ctrl_m0_agent:av_burstcount
wire [31:0] ctrl_m0_translator_avalon_universal_master_0_writedata; // ctrl_m0_translator:uav_writedata -> ctrl_m0_agent:av_writedata
wire [10:0] ctrl_m0_translator_avalon_universal_master_0_address; // ctrl_m0_translator:uav_address -> ctrl_m0_agent:av_address
wire ctrl_m0_translator_avalon_universal_master_0_lock; // ctrl_m0_translator:uav_lock -> ctrl_m0_agent:av_lock
wire ctrl_m0_translator_avalon_universal_master_0_write; // ctrl_m0_translator:uav_write -> ctrl_m0_agent:av_write
wire ctrl_m0_translator_avalon_universal_master_0_read; // ctrl_m0_translator:uav_read -> ctrl_m0_agent:av_read
wire [31:0] ctrl_m0_translator_avalon_universal_master_0_readdata; // ctrl_m0_agent:av_readdata -> ctrl_m0_translator:uav_readdata
wire ctrl_m0_translator_avalon_universal_master_0_debugaccess; // ctrl_m0_translator:uav_debugaccess -> ctrl_m0_agent:av_debugaccess
wire [3:0] ctrl_m0_translator_avalon_universal_master_0_byteenable; // ctrl_m0_translator:uav_byteenable -> ctrl_m0_agent:av_byteenable
wire ctrl_m0_translator_avalon_universal_master_0_readdatavalid; // ctrl_m0_agent:av_readdatavalid -> ctrl_m0_translator:uav_readdatavalid
wire pll_reconfig_0_mgmt_avalon_slave_agent_m0_waitrequest; // pll_reconfig_0_mgmt_avalon_slave_translator:uav_waitrequest -> pll_reconfig_0_mgmt_avalon_slave_agent:m0_waitrequest
wire [2:0] pll_reconfig_0_mgmt_avalon_slave_agent_m0_burstcount; // pll_reconfig_0_mgmt_avalon_slave_agent:m0_burstcount -> pll_reconfig_0_mgmt_avalon_slave_translator:uav_burstcount
wire [31:0] pll_reconfig_0_mgmt_avalon_slave_agent_m0_writedata; // pll_reconfig_0_mgmt_avalon_slave_agent:m0_writedata -> pll_reconfig_0_mgmt_avalon_slave_translator:uav_writedata
wire [10:0] pll_reconfig_0_mgmt_avalon_slave_agent_m0_address; // pll_reconfig_0_mgmt_avalon_slave_agent:m0_address -> pll_reconfig_0_mgmt_avalon_slave_translator:uav_address
wire pll_reconfig_0_mgmt_avalon_slave_agent_m0_write; // pll_reconfig_0_mgmt_avalon_slave_agent:m0_write -> pll_reconfig_0_mgmt_avalon_slave_translator:uav_write
wire pll_reconfig_0_mgmt_avalon_slave_agent_m0_lock; // pll_reconfig_0_mgmt_avalon_slave_agent:m0_lock -> pll_reconfig_0_mgmt_avalon_slave_translator:uav_lock
wire pll_reconfig_0_mgmt_avalon_slave_agent_m0_read; // pll_reconfig_0_mgmt_avalon_slave_agent:m0_read -> pll_reconfig_0_mgmt_avalon_slave_translator:uav_read
wire [31:0] pll_reconfig_0_mgmt_avalon_slave_agent_m0_readdata; // pll_reconfig_0_mgmt_avalon_slave_translator:uav_readdata -> pll_reconfig_0_mgmt_avalon_slave_agent:m0_readdata
wire pll_reconfig_0_mgmt_avalon_slave_agent_m0_readdatavalid; // pll_reconfig_0_mgmt_avalon_slave_translator:uav_readdatavalid -> pll_reconfig_0_mgmt_avalon_slave_agent:m0_readdatavalid
wire pll_reconfig_0_mgmt_avalon_slave_agent_m0_debugaccess; // pll_reconfig_0_mgmt_avalon_slave_agent:m0_debugaccess -> pll_reconfig_0_mgmt_avalon_slave_translator:uav_debugaccess
wire [3:0] pll_reconfig_0_mgmt_avalon_slave_agent_m0_byteenable; // pll_reconfig_0_mgmt_avalon_slave_agent:m0_byteenable -> pll_reconfig_0_mgmt_avalon_slave_translator:uav_byteenable
wire pll_reconfig_0_mgmt_avalon_slave_agent_rf_source_endofpacket; // pll_reconfig_0_mgmt_avalon_slave_agent:rf_source_endofpacket -> pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo:in_endofpacket
wire pll_reconfig_0_mgmt_avalon_slave_agent_rf_source_valid; // pll_reconfig_0_mgmt_avalon_slave_agent:rf_source_valid -> pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo:in_valid
wire pll_reconfig_0_mgmt_avalon_slave_agent_rf_source_startofpacket; // pll_reconfig_0_mgmt_avalon_slave_agent:rf_source_startofpacket -> pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo:in_startofpacket
wire [85:0] pll_reconfig_0_mgmt_avalon_slave_agent_rf_source_data; // pll_reconfig_0_mgmt_avalon_slave_agent:rf_source_data -> pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo:in_data
wire pll_reconfig_0_mgmt_avalon_slave_agent_rf_source_ready; // pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo:in_ready -> pll_reconfig_0_mgmt_avalon_slave_agent:rf_source_ready
wire pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo_out_endofpacket; // pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo:out_endofpacket -> pll_reconfig_0_mgmt_avalon_slave_agent:rf_sink_endofpacket
wire pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo_out_valid; // pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo:out_valid -> pll_reconfig_0_mgmt_avalon_slave_agent:rf_sink_valid
wire pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo_out_startofpacket; // pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo:out_startofpacket -> pll_reconfig_0_mgmt_avalon_slave_agent:rf_sink_startofpacket
wire [85:0] pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo_out_data; // pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo:out_data -> pll_reconfig_0_mgmt_avalon_slave_agent:rf_sink_data
wire pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo_out_ready; // pll_reconfig_0_mgmt_avalon_slave_agent:rf_sink_ready -> pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo:out_ready
wire pll_reconfig_0_mgmt_avalon_slave_agent_rdata_fifo_src_valid; // pll_reconfig_0_mgmt_avalon_slave_agent:rdata_fifo_src_valid -> pll_reconfig_0_mgmt_avalon_slave_agent:rdata_fifo_sink_valid
wire [33:0] pll_reconfig_0_mgmt_avalon_slave_agent_rdata_fifo_src_data; // pll_reconfig_0_mgmt_avalon_slave_agent:rdata_fifo_src_data -> pll_reconfig_0_mgmt_avalon_slave_agent:rdata_fifo_sink_data
wire pll_reconfig_0_mgmt_avalon_slave_agent_rdata_fifo_src_ready; // pll_reconfig_0_mgmt_avalon_slave_agent:rdata_fifo_sink_ready -> pll_reconfig_0_mgmt_avalon_slave_agent:rdata_fifo_src_ready
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> pll_reconfig_0_mgmt_avalon_slave_agent:cp_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> pll_reconfig_0_mgmt_avalon_slave_agent:cp_valid
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> pll_reconfig_0_mgmt_avalon_slave_agent:cp_startofpacket
wire [84:0] cmd_mux_src_data; // cmd_mux:src_data -> pll_reconfig_0_mgmt_avalon_slave_agent:cp_data
wire [5:0] cmd_mux_src_channel; // cmd_mux:src_channel -> pll_reconfig_0_mgmt_avalon_slave_agent:cp_channel
wire cmd_mux_src_ready; // pll_reconfig_0_mgmt_avalon_slave_agent:cp_ready -> cmd_mux:src_ready
wire pll_rom_s1_agent_m0_waitrequest; // pll_rom_s1_translator:uav_waitrequest -> pll_rom_s1_agent:m0_waitrequest
wire [2:0] pll_rom_s1_agent_m0_burstcount; // pll_rom_s1_agent:m0_burstcount -> pll_rom_s1_translator:uav_burstcount
wire [31:0] pll_rom_s1_agent_m0_writedata; // pll_rom_s1_agent:m0_writedata -> pll_rom_s1_translator:uav_writedata
wire [10:0] pll_rom_s1_agent_m0_address; // pll_rom_s1_agent:m0_address -> pll_rom_s1_translator:uav_address
wire pll_rom_s1_agent_m0_write; // pll_rom_s1_agent:m0_write -> pll_rom_s1_translator:uav_write
wire pll_rom_s1_agent_m0_lock; // pll_rom_s1_agent:m0_lock -> pll_rom_s1_translator:uav_lock
wire pll_rom_s1_agent_m0_read; // pll_rom_s1_agent:m0_read -> pll_rom_s1_translator:uav_read
wire [31:0] pll_rom_s1_agent_m0_readdata; // pll_rom_s1_translator:uav_readdata -> pll_rom_s1_agent:m0_readdata
wire pll_rom_s1_agent_m0_readdatavalid; // pll_rom_s1_translator:uav_readdatavalid -> pll_rom_s1_agent:m0_readdatavalid
wire pll_rom_s1_agent_m0_debugaccess; // pll_rom_s1_agent:m0_debugaccess -> pll_rom_s1_translator:uav_debugaccess
wire [3:0] pll_rom_s1_agent_m0_byteenable; // pll_rom_s1_agent:m0_byteenable -> pll_rom_s1_translator:uav_byteenable
wire pll_rom_s1_agent_rf_source_endofpacket; // pll_rom_s1_agent:rf_source_endofpacket -> pll_rom_s1_agent_rsp_fifo:in_endofpacket
wire pll_rom_s1_agent_rf_source_valid; // pll_rom_s1_agent:rf_source_valid -> pll_rom_s1_agent_rsp_fifo:in_valid
wire pll_rom_s1_agent_rf_source_startofpacket; // pll_rom_s1_agent:rf_source_startofpacket -> pll_rom_s1_agent_rsp_fifo:in_startofpacket
wire [85:0] pll_rom_s1_agent_rf_source_data; // pll_rom_s1_agent:rf_source_data -> pll_rom_s1_agent_rsp_fifo:in_data
wire pll_rom_s1_agent_rf_source_ready; // pll_rom_s1_agent_rsp_fifo:in_ready -> pll_rom_s1_agent:rf_source_ready
wire pll_rom_s1_agent_rsp_fifo_out_endofpacket; // pll_rom_s1_agent_rsp_fifo:out_endofpacket -> pll_rom_s1_agent:rf_sink_endofpacket
wire pll_rom_s1_agent_rsp_fifo_out_valid; // pll_rom_s1_agent_rsp_fifo:out_valid -> pll_rom_s1_agent:rf_sink_valid
wire pll_rom_s1_agent_rsp_fifo_out_startofpacket; // pll_rom_s1_agent_rsp_fifo:out_startofpacket -> pll_rom_s1_agent:rf_sink_startofpacket
wire [85:0] pll_rom_s1_agent_rsp_fifo_out_data; // pll_rom_s1_agent_rsp_fifo:out_data -> pll_rom_s1_agent:rf_sink_data
wire pll_rom_s1_agent_rsp_fifo_out_ready; // pll_rom_s1_agent:rf_sink_ready -> pll_rom_s1_agent_rsp_fifo:out_ready
wire pll_rom_s1_agent_rdata_fifo_src_valid; // pll_rom_s1_agent:rdata_fifo_src_valid -> pll_rom_s1_agent:rdata_fifo_sink_valid
wire [33:0] pll_rom_s1_agent_rdata_fifo_src_data; // pll_rom_s1_agent:rdata_fifo_src_data -> pll_rom_s1_agent:rdata_fifo_sink_data
wire pll_rom_s1_agent_rdata_fifo_src_ready; // pll_rom_s1_agent:rdata_fifo_sink_ready -> pll_rom_s1_agent:rdata_fifo_src_ready
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> pll_rom_s1_agent:cp_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> pll_rom_s1_agent:cp_valid
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> pll_rom_s1_agent:cp_startofpacket
wire [84:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> pll_rom_s1_agent:cp_data
wire [5:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> pll_rom_s1_agent:cp_channel
wire cmd_mux_001_src_ready; // pll_rom_s1_agent:cp_ready -> cmd_mux_001:src_ready
wire counter_s_agent_m0_waitrequest; // counter_s_translator:uav_waitrequest -> counter_s_agent:m0_waitrequest
wire [2:0] counter_s_agent_m0_burstcount; // counter_s_agent:m0_burstcount -> counter_s_translator:uav_burstcount
wire [31:0] counter_s_agent_m0_writedata; // counter_s_agent:m0_writedata -> counter_s_translator:uav_writedata
wire [10:0] counter_s_agent_m0_address; // counter_s_agent:m0_address -> counter_s_translator:uav_address
wire counter_s_agent_m0_write; // counter_s_agent:m0_write -> counter_s_translator:uav_write
wire counter_s_agent_m0_lock; // counter_s_agent:m0_lock -> counter_s_translator:uav_lock
wire counter_s_agent_m0_read; // counter_s_agent:m0_read -> counter_s_translator:uav_read
wire [31:0] counter_s_agent_m0_readdata; // counter_s_translator:uav_readdata -> counter_s_agent:m0_readdata
wire counter_s_agent_m0_readdatavalid; // counter_s_translator:uav_readdatavalid -> counter_s_agent:m0_readdatavalid
wire counter_s_agent_m0_debugaccess; // counter_s_agent:m0_debugaccess -> counter_s_translator:uav_debugaccess
wire [3:0] counter_s_agent_m0_byteenable; // counter_s_agent:m0_byteenable -> counter_s_translator:uav_byteenable
wire counter_s_agent_rf_source_endofpacket; // counter_s_agent:rf_source_endofpacket -> counter_s_agent_rsp_fifo:in_endofpacket
wire counter_s_agent_rf_source_valid; // counter_s_agent:rf_source_valid -> counter_s_agent_rsp_fifo:in_valid
wire counter_s_agent_rf_source_startofpacket; // counter_s_agent:rf_source_startofpacket -> counter_s_agent_rsp_fifo:in_startofpacket
wire [85:0] counter_s_agent_rf_source_data; // counter_s_agent:rf_source_data -> counter_s_agent_rsp_fifo:in_data
wire counter_s_agent_rf_source_ready; // counter_s_agent_rsp_fifo:in_ready -> counter_s_agent:rf_source_ready
wire counter_s_agent_rsp_fifo_out_endofpacket; // counter_s_agent_rsp_fifo:out_endofpacket -> counter_s_agent:rf_sink_endofpacket
wire counter_s_agent_rsp_fifo_out_valid; // counter_s_agent_rsp_fifo:out_valid -> counter_s_agent:rf_sink_valid
wire counter_s_agent_rsp_fifo_out_startofpacket; // counter_s_agent_rsp_fifo:out_startofpacket -> counter_s_agent:rf_sink_startofpacket
wire [85:0] counter_s_agent_rsp_fifo_out_data; // counter_s_agent_rsp_fifo:out_data -> counter_s_agent:rf_sink_data
wire counter_s_agent_rsp_fifo_out_ready; // counter_s_agent:rf_sink_ready -> counter_s_agent_rsp_fifo:out_ready
wire counter_s_agent_rdata_fifo_src_valid; // counter_s_agent:rdata_fifo_src_valid -> counter_s_agent_rdata_fifo:in_valid
wire [33:0] counter_s_agent_rdata_fifo_src_data; // counter_s_agent:rdata_fifo_src_data -> counter_s_agent_rdata_fifo:in_data
wire counter_s_agent_rdata_fifo_src_ready; // counter_s_agent_rdata_fifo:in_ready -> counter_s_agent:rdata_fifo_src_ready
wire counter_s_agent_rdata_fifo_out_valid; // counter_s_agent_rdata_fifo:out_valid -> counter_s_agent:rdata_fifo_sink_valid
wire [33:0] counter_s_agent_rdata_fifo_out_data; // counter_s_agent_rdata_fifo:out_data -> counter_s_agent:rdata_fifo_sink_data
wire counter_s_agent_rdata_fifo_out_ready; // counter_s_agent:rdata_fifo_sink_ready -> counter_s_agent_rdata_fifo:out_ready
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> counter_s_agent:cp_endofpacket
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> counter_s_agent:cp_valid
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> counter_s_agent:cp_startofpacket
wire [84:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> counter_s_agent:cp_data
wire [5:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> counter_s_agent:cp_channel
wire cmd_mux_002_src_ready; // counter_s_agent:cp_ready -> cmd_mux_002:src_ready
wire pll_sw_reset_s_agent_m0_waitrequest; // pll_sw_reset_s_translator:uav_waitrequest -> pll_sw_reset_s_agent:m0_waitrequest
wire [2:0] pll_sw_reset_s_agent_m0_burstcount; // pll_sw_reset_s_agent:m0_burstcount -> pll_sw_reset_s_translator:uav_burstcount
wire [31:0] pll_sw_reset_s_agent_m0_writedata; // pll_sw_reset_s_agent:m0_writedata -> pll_sw_reset_s_translator:uav_writedata
wire [10:0] pll_sw_reset_s_agent_m0_address; // pll_sw_reset_s_agent:m0_address -> pll_sw_reset_s_translator:uav_address
wire pll_sw_reset_s_agent_m0_write; // pll_sw_reset_s_agent:m0_write -> pll_sw_reset_s_translator:uav_write
wire pll_sw_reset_s_agent_m0_lock; // pll_sw_reset_s_agent:m0_lock -> pll_sw_reset_s_translator:uav_lock
wire pll_sw_reset_s_agent_m0_read; // pll_sw_reset_s_agent:m0_read -> pll_sw_reset_s_translator:uav_read
wire [31:0] pll_sw_reset_s_agent_m0_readdata; // pll_sw_reset_s_translator:uav_readdata -> pll_sw_reset_s_agent:m0_readdata
wire pll_sw_reset_s_agent_m0_readdatavalid; // pll_sw_reset_s_translator:uav_readdatavalid -> pll_sw_reset_s_agent:m0_readdatavalid
wire pll_sw_reset_s_agent_m0_debugaccess; // pll_sw_reset_s_agent:m0_debugaccess -> pll_sw_reset_s_translator:uav_debugaccess
wire [3:0] pll_sw_reset_s_agent_m0_byteenable; // pll_sw_reset_s_agent:m0_byteenable -> pll_sw_reset_s_translator:uav_byteenable
wire pll_sw_reset_s_agent_rf_source_endofpacket; // pll_sw_reset_s_agent:rf_source_endofpacket -> pll_sw_reset_s_agent_rsp_fifo:in_endofpacket
wire pll_sw_reset_s_agent_rf_source_valid; // pll_sw_reset_s_agent:rf_source_valid -> pll_sw_reset_s_agent_rsp_fifo:in_valid
wire pll_sw_reset_s_agent_rf_source_startofpacket; // pll_sw_reset_s_agent:rf_source_startofpacket -> pll_sw_reset_s_agent_rsp_fifo:in_startofpacket
wire [85:0] pll_sw_reset_s_agent_rf_source_data; // pll_sw_reset_s_agent:rf_source_data -> pll_sw_reset_s_agent_rsp_fifo:in_data
wire pll_sw_reset_s_agent_rf_source_ready; // pll_sw_reset_s_agent_rsp_fifo:in_ready -> pll_sw_reset_s_agent:rf_source_ready
wire pll_sw_reset_s_agent_rsp_fifo_out_endofpacket; // pll_sw_reset_s_agent_rsp_fifo:out_endofpacket -> pll_sw_reset_s_agent:rf_sink_endofpacket
wire pll_sw_reset_s_agent_rsp_fifo_out_valid; // pll_sw_reset_s_agent_rsp_fifo:out_valid -> pll_sw_reset_s_agent:rf_sink_valid
wire pll_sw_reset_s_agent_rsp_fifo_out_startofpacket; // pll_sw_reset_s_agent_rsp_fifo:out_startofpacket -> pll_sw_reset_s_agent:rf_sink_startofpacket
wire [85:0] pll_sw_reset_s_agent_rsp_fifo_out_data; // pll_sw_reset_s_agent_rsp_fifo:out_data -> pll_sw_reset_s_agent:rf_sink_data
wire pll_sw_reset_s_agent_rsp_fifo_out_ready; // pll_sw_reset_s_agent:rf_sink_ready -> pll_sw_reset_s_agent_rsp_fifo:out_ready
wire pll_sw_reset_s_agent_rdata_fifo_src_valid; // pll_sw_reset_s_agent:rdata_fifo_src_valid -> pll_sw_reset_s_agent:rdata_fifo_sink_valid
wire [33:0] pll_sw_reset_s_agent_rdata_fifo_src_data; // pll_sw_reset_s_agent:rdata_fifo_src_data -> pll_sw_reset_s_agent:rdata_fifo_sink_data
wire pll_sw_reset_s_agent_rdata_fifo_src_ready; // pll_sw_reset_s_agent:rdata_fifo_sink_ready -> pll_sw_reset_s_agent:rdata_fifo_src_ready
wire cmd_mux_003_src_endofpacket; // cmd_mux_003:src_endofpacket -> pll_sw_reset_s_agent:cp_endofpacket
wire cmd_mux_003_src_valid; // cmd_mux_003:src_valid -> pll_sw_reset_s_agent:cp_valid
wire cmd_mux_003_src_startofpacket; // cmd_mux_003:src_startofpacket -> pll_sw_reset_s_agent:cp_startofpacket
wire [84:0] cmd_mux_003_src_data; // cmd_mux_003:src_data -> pll_sw_reset_s_agent:cp_data
wire [5:0] cmd_mux_003_src_channel; // cmd_mux_003:src_channel -> pll_sw_reset_s_agent:cp_channel
wire cmd_mux_003_src_ready; // pll_sw_reset_s_agent:cp_ready -> cmd_mux_003:src_ready
wire pll_lock_avs_0_s_agent_m0_waitrequest; // pll_lock_avs_0_s_translator:uav_waitrequest -> pll_lock_avs_0_s_agent:m0_waitrequest
wire [2:0] pll_lock_avs_0_s_agent_m0_burstcount; // pll_lock_avs_0_s_agent:m0_burstcount -> pll_lock_avs_0_s_translator:uav_burstcount
wire [31:0] pll_lock_avs_0_s_agent_m0_writedata; // pll_lock_avs_0_s_agent:m0_writedata -> pll_lock_avs_0_s_translator:uav_writedata
wire [10:0] pll_lock_avs_0_s_agent_m0_address; // pll_lock_avs_0_s_agent:m0_address -> pll_lock_avs_0_s_translator:uav_address
wire pll_lock_avs_0_s_agent_m0_write; // pll_lock_avs_0_s_agent:m0_write -> pll_lock_avs_0_s_translator:uav_write
wire pll_lock_avs_0_s_agent_m0_lock; // pll_lock_avs_0_s_agent:m0_lock -> pll_lock_avs_0_s_translator:uav_lock
wire pll_lock_avs_0_s_agent_m0_read; // pll_lock_avs_0_s_agent:m0_read -> pll_lock_avs_0_s_translator:uav_read
wire [31:0] pll_lock_avs_0_s_agent_m0_readdata; // pll_lock_avs_0_s_translator:uav_readdata -> pll_lock_avs_0_s_agent:m0_readdata
wire pll_lock_avs_0_s_agent_m0_readdatavalid; // pll_lock_avs_0_s_translator:uav_readdatavalid -> pll_lock_avs_0_s_agent:m0_readdatavalid
wire pll_lock_avs_0_s_agent_m0_debugaccess; // pll_lock_avs_0_s_agent:m0_debugaccess -> pll_lock_avs_0_s_translator:uav_debugaccess
wire [3:0] pll_lock_avs_0_s_agent_m0_byteenable; // pll_lock_avs_0_s_agent:m0_byteenable -> pll_lock_avs_0_s_translator:uav_byteenable
wire pll_lock_avs_0_s_agent_rf_source_endofpacket; // pll_lock_avs_0_s_agent:rf_source_endofpacket -> pll_lock_avs_0_s_agent_rsp_fifo:in_endofpacket
wire pll_lock_avs_0_s_agent_rf_source_valid; // pll_lock_avs_0_s_agent:rf_source_valid -> pll_lock_avs_0_s_agent_rsp_fifo:in_valid
wire pll_lock_avs_0_s_agent_rf_source_startofpacket; // pll_lock_avs_0_s_agent:rf_source_startofpacket -> pll_lock_avs_0_s_agent_rsp_fifo:in_startofpacket
wire [85:0] pll_lock_avs_0_s_agent_rf_source_data; // pll_lock_avs_0_s_agent:rf_source_data -> pll_lock_avs_0_s_agent_rsp_fifo:in_data
wire pll_lock_avs_0_s_agent_rf_source_ready; // pll_lock_avs_0_s_agent_rsp_fifo:in_ready -> pll_lock_avs_0_s_agent:rf_source_ready
wire pll_lock_avs_0_s_agent_rsp_fifo_out_endofpacket; // pll_lock_avs_0_s_agent_rsp_fifo:out_endofpacket -> pll_lock_avs_0_s_agent:rf_sink_endofpacket
wire pll_lock_avs_0_s_agent_rsp_fifo_out_valid; // pll_lock_avs_0_s_agent_rsp_fifo:out_valid -> pll_lock_avs_0_s_agent:rf_sink_valid
wire pll_lock_avs_0_s_agent_rsp_fifo_out_startofpacket; // pll_lock_avs_0_s_agent_rsp_fifo:out_startofpacket -> pll_lock_avs_0_s_agent:rf_sink_startofpacket
wire [85:0] pll_lock_avs_0_s_agent_rsp_fifo_out_data; // pll_lock_avs_0_s_agent_rsp_fifo:out_data -> pll_lock_avs_0_s_agent:rf_sink_data
wire pll_lock_avs_0_s_agent_rsp_fifo_out_ready; // pll_lock_avs_0_s_agent:rf_sink_ready -> pll_lock_avs_0_s_agent_rsp_fifo:out_ready
wire pll_lock_avs_0_s_agent_rdata_fifo_src_valid; // pll_lock_avs_0_s_agent:rdata_fifo_src_valid -> pll_lock_avs_0_s_agent:rdata_fifo_sink_valid
wire [33:0] pll_lock_avs_0_s_agent_rdata_fifo_src_data; // pll_lock_avs_0_s_agent:rdata_fifo_src_data -> pll_lock_avs_0_s_agent:rdata_fifo_sink_data
wire pll_lock_avs_0_s_agent_rdata_fifo_src_ready; // pll_lock_avs_0_s_agent:rdata_fifo_sink_ready -> pll_lock_avs_0_s_agent:rdata_fifo_src_ready
wire cmd_mux_004_src_endofpacket; // cmd_mux_004:src_endofpacket -> pll_lock_avs_0_s_agent:cp_endofpacket
wire cmd_mux_004_src_valid; // cmd_mux_004:src_valid -> pll_lock_avs_0_s_agent:cp_valid
wire cmd_mux_004_src_startofpacket; // cmd_mux_004:src_startofpacket -> pll_lock_avs_0_s_agent:cp_startofpacket
wire [84:0] cmd_mux_004_src_data; // cmd_mux_004:src_data -> pll_lock_avs_0_s_agent:cp_data
wire [5:0] cmd_mux_004_src_channel; // cmd_mux_004:src_channel -> pll_lock_avs_0_s_agent:cp_channel
wire cmd_mux_004_src_ready; // pll_lock_avs_0_s_agent:cp_ready -> cmd_mux_004:src_ready
wire version_id_0_s_agent_m0_waitrequest; // version_id_0_s_translator:uav_waitrequest -> version_id_0_s_agent:m0_waitrequest
wire [2:0] version_id_0_s_agent_m0_burstcount; // version_id_0_s_agent:m0_burstcount -> version_id_0_s_translator:uav_burstcount
wire [31:0] version_id_0_s_agent_m0_writedata; // version_id_0_s_agent:m0_writedata -> version_id_0_s_translator:uav_writedata
wire [10:0] version_id_0_s_agent_m0_address; // version_id_0_s_agent:m0_address -> version_id_0_s_translator:uav_address
wire version_id_0_s_agent_m0_write; // version_id_0_s_agent:m0_write -> version_id_0_s_translator:uav_write
wire version_id_0_s_agent_m0_lock; // version_id_0_s_agent:m0_lock -> version_id_0_s_translator:uav_lock
wire version_id_0_s_agent_m0_read; // version_id_0_s_agent:m0_read -> version_id_0_s_translator:uav_read
wire [31:0] version_id_0_s_agent_m0_readdata; // version_id_0_s_translator:uav_readdata -> version_id_0_s_agent:m0_readdata
wire version_id_0_s_agent_m0_readdatavalid; // version_id_0_s_translator:uav_readdatavalid -> version_id_0_s_agent:m0_readdatavalid
wire version_id_0_s_agent_m0_debugaccess; // version_id_0_s_agent:m0_debugaccess -> version_id_0_s_translator:uav_debugaccess
wire [3:0] version_id_0_s_agent_m0_byteenable; // version_id_0_s_agent:m0_byteenable -> version_id_0_s_translator:uav_byteenable
wire version_id_0_s_agent_rf_source_endofpacket; // version_id_0_s_agent:rf_source_endofpacket -> version_id_0_s_agent_rsp_fifo:in_endofpacket
wire version_id_0_s_agent_rf_source_valid; // version_id_0_s_agent:rf_source_valid -> version_id_0_s_agent_rsp_fifo:in_valid
wire version_id_0_s_agent_rf_source_startofpacket; // version_id_0_s_agent:rf_source_startofpacket -> version_id_0_s_agent_rsp_fifo:in_startofpacket
wire [85:0] version_id_0_s_agent_rf_source_data; // version_id_0_s_agent:rf_source_data -> version_id_0_s_agent_rsp_fifo:in_data
wire version_id_0_s_agent_rf_source_ready; // version_id_0_s_agent_rsp_fifo:in_ready -> version_id_0_s_agent:rf_source_ready
wire version_id_0_s_agent_rsp_fifo_out_endofpacket; // version_id_0_s_agent_rsp_fifo:out_endofpacket -> version_id_0_s_agent:rf_sink_endofpacket
wire version_id_0_s_agent_rsp_fifo_out_valid; // version_id_0_s_agent_rsp_fifo:out_valid -> version_id_0_s_agent:rf_sink_valid
wire version_id_0_s_agent_rsp_fifo_out_startofpacket; // version_id_0_s_agent_rsp_fifo:out_startofpacket -> version_id_0_s_agent:rf_sink_startofpacket
wire [85:0] version_id_0_s_agent_rsp_fifo_out_data; // version_id_0_s_agent_rsp_fifo:out_data -> version_id_0_s_agent:rf_sink_data
wire version_id_0_s_agent_rsp_fifo_out_ready; // version_id_0_s_agent:rf_sink_ready -> version_id_0_s_agent_rsp_fifo:out_ready
wire version_id_0_s_agent_rdata_fifo_src_valid; // version_id_0_s_agent:rdata_fifo_src_valid -> version_id_0_s_agent:rdata_fifo_sink_valid
wire [33:0] version_id_0_s_agent_rdata_fifo_src_data; // version_id_0_s_agent:rdata_fifo_src_data -> version_id_0_s_agent:rdata_fifo_sink_data
wire version_id_0_s_agent_rdata_fifo_src_ready; // version_id_0_s_agent:rdata_fifo_sink_ready -> version_id_0_s_agent:rdata_fifo_src_ready
wire cmd_mux_005_src_endofpacket; // cmd_mux_005:src_endofpacket -> version_id_0_s_agent:cp_endofpacket
wire cmd_mux_005_src_valid; // cmd_mux_005:src_valid -> version_id_0_s_agent:cp_valid
wire cmd_mux_005_src_startofpacket; // cmd_mux_005:src_startofpacket -> version_id_0_s_agent:cp_startofpacket
wire [84:0] cmd_mux_005_src_data; // cmd_mux_005:src_data -> version_id_0_s_agent:cp_data
wire [5:0] cmd_mux_005_src_channel; // cmd_mux_005:src_channel -> version_id_0_s_agent:cp_channel
wire cmd_mux_005_src_ready; // version_id_0_s_agent:cp_ready -> cmd_mux_005:src_ready
wire ctrl_m0_agent_cp_endofpacket; // ctrl_m0_agent:cp_endofpacket -> router:sink_endofpacket
wire ctrl_m0_agent_cp_valid; // ctrl_m0_agent:cp_valid -> router:sink_valid
wire ctrl_m0_agent_cp_startofpacket; // ctrl_m0_agent:cp_startofpacket -> router:sink_startofpacket
wire [84:0] ctrl_m0_agent_cp_data; // ctrl_m0_agent:cp_data -> router:sink_data
wire ctrl_m0_agent_cp_ready; // router:sink_ready -> ctrl_m0_agent:cp_ready
wire pll_reconfig_0_mgmt_avalon_slave_agent_rp_endofpacket; // pll_reconfig_0_mgmt_avalon_slave_agent:rp_endofpacket -> router_001:sink_endofpacket
wire pll_reconfig_0_mgmt_avalon_slave_agent_rp_valid; // pll_reconfig_0_mgmt_avalon_slave_agent:rp_valid -> router_001:sink_valid
wire pll_reconfig_0_mgmt_avalon_slave_agent_rp_startofpacket; // pll_reconfig_0_mgmt_avalon_slave_agent:rp_startofpacket -> router_001:sink_startofpacket
wire [84:0] pll_reconfig_0_mgmt_avalon_slave_agent_rp_data; // pll_reconfig_0_mgmt_avalon_slave_agent:rp_data -> router_001:sink_data
wire pll_reconfig_0_mgmt_avalon_slave_agent_rp_ready; // router_001:sink_ready -> pll_reconfig_0_mgmt_avalon_slave_agent:rp_ready
wire router_001_src_endofpacket; // router_001:src_endofpacket -> rsp_demux:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> rsp_demux:sink_valid
wire router_001_src_startofpacket; // router_001:src_startofpacket -> rsp_demux:sink_startofpacket
wire [84:0] router_001_src_data; // router_001:src_data -> rsp_demux:sink_data
wire [5:0] router_001_src_channel; // router_001:src_channel -> rsp_demux:sink_channel
wire router_001_src_ready; // rsp_demux:sink_ready -> router_001:src_ready
wire pll_rom_s1_agent_rp_endofpacket; // pll_rom_s1_agent:rp_endofpacket -> router_002:sink_endofpacket
wire pll_rom_s1_agent_rp_valid; // pll_rom_s1_agent:rp_valid -> router_002:sink_valid
wire pll_rom_s1_agent_rp_startofpacket; // pll_rom_s1_agent:rp_startofpacket -> router_002:sink_startofpacket
wire [84:0] pll_rom_s1_agent_rp_data; // pll_rom_s1_agent:rp_data -> router_002:sink_data
wire pll_rom_s1_agent_rp_ready; // router_002:sink_ready -> pll_rom_s1_agent:rp_ready
wire router_002_src_endofpacket; // router_002:src_endofpacket -> rsp_demux_001:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> rsp_demux_001:sink_valid
wire router_002_src_startofpacket; // router_002:src_startofpacket -> rsp_demux_001:sink_startofpacket
wire [84:0] router_002_src_data; // router_002:src_data -> rsp_demux_001:sink_data
wire [5:0] router_002_src_channel; // router_002:src_channel -> rsp_demux_001:sink_channel
wire router_002_src_ready; // rsp_demux_001:sink_ready -> router_002:src_ready
wire counter_s_agent_rp_endofpacket; // counter_s_agent:rp_endofpacket -> router_003:sink_endofpacket
wire counter_s_agent_rp_valid; // counter_s_agent:rp_valid -> router_003:sink_valid
wire counter_s_agent_rp_startofpacket; // counter_s_agent:rp_startofpacket -> router_003:sink_startofpacket
wire [84:0] counter_s_agent_rp_data; // counter_s_agent:rp_data -> router_003:sink_data
wire counter_s_agent_rp_ready; // router_003:sink_ready -> counter_s_agent:rp_ready
wire router_003_src_endofpacket; // router_003:src_endofpacket -> rsp_demux_002:sink_endofpacket
wire router_003_src_valid; // router_003:src_valid -> rsp_demux_002:sink_valid
wire router_003_src_startofpacket; // router_003:src_startofpacket -> rsp_demux_002:sink_startofpacket
wire [84:0] router_003_src_data; // router_003:src_data -> rsp_demux_002:sink_data
wire [5:0] router_003_src_channel; // router_003:src_channel -> rsp_demux_002:sink_channel
wire router_003_src_ready; // rsp_demux_002:sink_ready -> router_003:src_ready
wire pll_sw_reset_s_agent_rp_endofpacket; // pll_sw_reset_s_agent:rp_endofpacket -> router_004:sink_endofpacket
wire pll_sw_reset_s_agent_rp_valid; // pll_sw_reset_s_agent:rp_valid -> router_004:sink_valid
wire pll_sw_reset_s_agent_rp_startofpacket; // pll_sw_reset_s_agent:rp_startofpacket -> router_004:sink_startofpacket
wire [84:0] pll_sw_reset_s_agent_rp_data; // pll_sw_reset_s_agent:rp_data -> router_004:sink_data
wire pll_sw_reset_s_agent_rp_ready; // router_004:sink_ready -> pll_sw_reset_s_agent:rp_ready
wire router_004_src_endofpacket; // router_004:src_endofpacket -> rsp_demux_003:sink_endofpacket
wire router_004_src_valid; // router_004:src_valid -> rsp_demux_003:sink_valid
wire router_004_src_startofpacket; // router_004:src_startofpacket -> rsp_demux_003:sink_startofpacket
wire [84:0] router_004_src_data; // router_004:src_data -> rsp_demux_003:sink_data
wire [5:0] router_004_src_channel; // router_004:src_channel -> rsp_demux_003:sink_channel
wire router_004_src_ready; // rsp_demux_003:sink_ready -> router_004:src_ready
wire pll_lock_avs_0_s_agent_rp_endofpacket; // pll_lock_avs_0_s_agent:rp_endofpacket -> router_005:sink_endofpacket
wire pll_lock_avs_0_s_agent_rp_valid; // pll_lock_avs_0_s_agent:rp_valid -> router_005:sink_valid
wire pll_lock_avs_0_s_agent_rp_startofpacket; // pll_lock_avs_0_s_agent:rp_startofpacket -> router_005:sink_startofpacket
wire [84:0] pll_lock_avs_0_s_agent_rp_data; // pll_lock_avs_0_s_agent:rp_data -> router_005:sink_data
wire pll_lock_avs_0_s_agent_rp_ready; // router_005:sink_ready -> pll_lock_avs_0_s_agent:rp_ready
wire router_005_src_endofpacket; // router_005:src_endofpacket -> rsp_demux_004:sink_endofpacket
wire router_005_src_valid; // router_005:src_valid -> rsp_demux_004:sink_valid
wire router_005_src_startofpacket; // router_005:src_startofpacket -> rsp_demux_004:sink_startofpacket
wire [84:0] router_005_src_data; // router_005:src_data -> rsp_demux_004:sink_data
wire [5:0] router_005_src_channel; // router_005:src_channel -> rsp_demux_004:sink_channel
wire router_005_src_ready; // rsp_demux_004:sink_ready -> router_005:src_ready
wire version_id_0_s_agent_rp_endofpacket; // version_id_0_s_agent:rp_endofpacket -> router_006:sink_endofpacket
wire version_id_0_s_agent_rp_valid; // version_id_0_s_agent:rp_valid -> router_006:sink_valid
wire version_id_0_s_agent_rp_startofpacket; // version_id_0_s_agent:rp_startofpacket -> router_006:sink_startofpacket
wire [84:0] version_id_0_s_agent_rp_data; // version_id_0_s_agent:rp_data -> router_006:sink_data
wire version_id_0_s_agent_rp_ready; // router_006:sink_ready -> version_id_0_s_agent:rp_ready
wire router_006_src_endofpacket; // router_006:src_endofpacket -> rsp_demux_005:sink_endofpacket
wire router_006_src_valid; // router_006:src_valid -> rsp_demux_005:sink_valid
wire router_006_src_startofpacket; // router_006:src_startofpacket -> rsp_demux_005:sink_startofpacket
wire [84:0] router_006_src_data; // router_006:src_data -> rsp_demux_005:sink_data
wire [5:0] router_006_src_channel; // router_006:src_channel -> rsp_demux_005:sink_channel
wire router_006_src_ready; // rsp_demux_005:sink_ready -> router_006:src_ready
wire router_src_endofpacket; // router:src_endofpacket -> ctrl_m0_limiter:cmd_sink_endofpacket
wire router_src_valid; // router:src_valid -> ctrl_m0_limiter:cmd_sink_valid
wire router_src_startofpacket; // router:src_startofpacket -> ctrl_m0_limiter:cmd_sink_startofpacket
wire [84:0] router_src_data; // router:src_data -> ctrl_m0_limiter:cmd_sink_data
wire [5:0] router_src_channel; // router:src_channel -> ctrl_m0_limiter:cmd_sink_channel
wire router_src_ready; // ctrl_m0_limiter:cmd_sink_ready -> router:src_ready
wire ctrl_m0_limiter_cmd_src_endofpacket; // ctrl_m0_limiter:cmd_src_endofpacket -> cmd_demux:sink_endofpacket
wire ctrl_m0_limiter_cmd_src_startofpacket; // ctrl_m0_limiter:cmd_src_startofpacket -> cmd_demux:sink_startofpacket
wire [84:0] ctrl_m0_limiter_cmd_src_data; // ctrl_m0_limiter:cmd_src_data -> cmd_demux:sink_data
wire [5:0] ctrl_m0_limiter_cmd_src_channel; // ctrl_m0_limiter:cmd_src_channel -> cmd_demux:sink_channel
wire ctrl_m0_limiter_cmd_src_ready; // cmd_demux:sink_ready -> ctrl_m0_limiter:cmd_src_ready
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> ctrl_m0_limiter:rsp_sink_endofpacket
wire rsp_mux_src_valid; // rsp_mux:src_valid -> ctrl_m0_limiter:rsp_sink_valid
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> ctrl_m0_limiter:rsp_sink_startofpacket
wire [84:0] rsp_mux_src_data; // rsp_mux:src_data -> ctrl_m0_limiter:rsp_sink_data
wire [5:0] rsp_mux_src_channel; // rsp_mux:src_channel -> ctrl_m0_limiter:rsp_sink_channel
wire rsp_mux_src_ready; // ctrl_m0_limiter:rsp_sink_ready -> rsp_mux:src_ready
wire ctrl_m0_limiter_rsp_src_endofpacket; // ctrl_m0_limiter:rsp_src_endofpacket -> ctrl_m0_agent:rp_endofpacket
wire ctrl_m0_limiter_rsp_src_valid; // ctrl_m0_limiter:rsp_src_valid -> ctrl_m0_agent:rp_valid
wire ctrl_m0_limiter_rsp_src_startofpacket; // ctrl_m0_limiter:rsp_src_startofpacket -> ctrl_m0_agent:rp_startofpacket
wire [84:0] ctrl_m0_limiter_rsp_src_data; // ctrl_m0_limiter:rsp_src_data -> ctrl_m0_agent:rp_data
wire [5:0] ctrl_m0_limiter_rsp_src_channel; // ctrl_m0_limiter:rsp_src_channel -> ctrl_m0_agent:rp_channel
wire ctrl_m0_limiter_rsp_src_ready; // ctrl_m0_agent:rp_ready -> ctrl_m0_limiter:rsp_src_ready
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire [84:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire [5:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
wire [84:0] cmd_demux_src1_data; // cmd_demux:src1_data -> cmd_mux_001:sink0_data
wire [5:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
wire cmd_demux_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
wire cmd_demux_src3_endofpacket; // cmd_demux:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
wire cmd_demux_src3_valid; // cmd_demux:src3_valid -> cmd_mux_003:sink0_valid
wire cmd_demux_src3_startofpacket; // cmd_demux:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
wire [84:0] cmd_demux_src3_data; // cmd_demux:src3_data -> cmd_mux_003:sink0_data
wire [5:0] cmd_demux_src3_channel; // cmd_demux:src3_channel -> cmd_mux_003:sink0_channel
wire cmd_demux_src3_ready; // cmd_mux_003:sink0_ready -> cmd_demux:src3_ready
wire cmd_demux_src4_endofpacket; // cmd_demux:src4_endofpacket -> cmd_mux_004:sink0_endofpacket
wire cmd_demux_src4_valid; // cmd_demux:src4_valid -> cmd_mux_004:sink0_valid
wire cmd_demux_src4_startofpacket; // cmd_demux:src4_startofpacket -> cmd_mux_004:sink0_startofpacket
wire [84:0] cmd_demux_src4_data; // cmd_demux:src4_data -> cmd_mux_004:sink0_data
wire [5:0] cmd_demux_src4_channel; // cmd_demux:src4_channel -> cmd_mux_004:sink0_channel
wire cmd_demux_src4_ready; // cmd_mux_004:sink0_ready -> cmd_demux:src4_ready
wire cmd_demux_src5_endofpacket; // cmd_demux:src5_endofpacket -> cmd_mux_005:sink0_endofpacket
wire cmd_demux_src5_valid; // cmd_demux:src5_valid -> cmd_mux_005:sink0_valid
wire cmd_demux_src5_startofpacket; // cmd_demux:src5_startofpacket -> cmd_mux_005:sink0_startofpacket
wire [84:0] cmd_demux_src5_data; // cmd_demux:src5_data -> cmd_mux_005:sink0_data
wire [5:0] cmd_demux_src5_channel; // cmd_demux:src5_channel -> cmd_mux_005:sink0_channel
wire cmd_demux_src5_ready; // cmd_mux_005:sink0_ready -> cmd_demux:src5_ready
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire [84:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire [5:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
wire [84:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux:sink1_data
wire [5:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
wire rsp_demux_001_src0_ready; // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
wire rsp_demux_003_src0_endofpacket; // rsp_demux_003:src0_endofpacket -> rsp_mux:sink3_endofpacket
wire rsp_demux_003_src0_valid; // rsp_demux_003:src0_valid -> rsp_mux:sink3_valid
wire rsp_demux_003_src0_startofpacket; // rsp_demux_003:src0_startofpacket -> rsp_mux:sink3_startofpacket
wire [84:0] rsp_demux_003_src0_data; // rsp_demux_003:src0_data -> rsp_mux:sink3_data
wire [5:0] rsp_demux_003_src0_channel; // rsp_demux_003:src0_channel -> rsp_mux:sink3_channel
wire rsp_demux_003_src0_ready; // rsp_mux:sink3_ready -> rsp_demux_003:src0_ready
wire rsp_demux_004_src0_endofpacket; // rsp_demux_004:src0_endofpacket -> rsp_mux:sink4_endofpacket
wire rsp_demux_004_src0_valid; // rsp_demux_004:src0_valid -> rsp_mux:sink4_valid
wire rsp_demux_004_src0_startofpacket; // rsp_demux_004:src0_startofpacket -> rsp_mux:sink4_startofpacket
wire [84:0] rsp_demux_004_src0_data; // rsp_demux_004:src0_data -> rsp_mux:sink4_data
wire [5:0] rsp_demux_004_src0_channel; // rsp_demux_004:src0_channel -> rsp_mux:sink4_channel
wire rsp_demux_004_src0_ready; // rsp_mux:sink4_ready -> rsp_demux_004:src0_ready
wire rsp_demux_005_src0_endofpacket; // rsp_demux_005:src0_endofpacket -> rsp_mux:sink5_endofpacket
wire rsp_demux_005_src0_valid; // rsp_demux_005:src0_valid -> rsp_mux:sink5_valid
wire rsp_demux_005_src0_startofpacket; // rsp_demux_005:src0_startofpacket -> rsp_mux:sink5_startofpacket
wire [84:0] rsp_demux_005_src0_data; // rsp_demux_005:src0_data -> rsp_mux:sink5_data
wire [5:0] rsp_demux_005_src0_channel; // rsp_demux_005:src0_channel -> rsp_mux:sink5_channel
wire rsp_demux_005_src0_ready; // rsp_mux:sink5_ready -> rsp_demux_005:src0_ready
wire cmd_demux_src2_endofpacket; // cmd_demux:src2_endofpacket -> crosser:in_endofpacket
wire cmd_demux_src2_valid; // cmd_demux:src2_valid -> crosser:in_valid
wire cmd_demux_src2_startofpacket; // cmd_demux:src2_startofpacket -> crosser:in_startofpacket
wire [84:0] cmd_demux_src2_data; // cmd_demux:src2_data -> crosser:in_data
wire [5:0] cmd_demux_src2_channel; // cmd_demux:src2_channel -> crosser:in_channel
wire cmd_demux_src2_ready; // crosser:in_ready -> cmd_demux:src2_ready
wire crosser_out_endofpacket; // crosser:out_endofpacket -> cmd_mux_002:sink0_endofpacket
wire crosser_out_valid; // crosser:out_valid -> cmd_mux_002:sink0_valid
wire crosser_out_startofpacket; // crosser:out_startofpacket -> cmd_mux_002:sink0_startofpacket
wire [84:0] crosser_out_data; // crosser:out_data -> cmd_mux_002:sink0_data
wire [5:0] crosser_out_channel; // crosser:out_channel -> cmd_mux_002:sink0_channel
wire crosser_out_ready; // cmd_mux_002:sink0_ready -> crosser:out_ready
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> crosser_001:in_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> crosser_001:in_valid
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> crosser_001:in_startofpacket
wire [84:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> crosser_001:in_data
wire [5:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> crosser_001:in_channel
wire rsp_demux_002_src0_ready; // crosser_001:in_ready -> rsp_demux_002:src0_ready
wire crosser_001_out_endofpacket; // crosser_001:out_endofpacket -> rsp_mux:sink2_endofpacket
wire crosser_001_out_valid; // crosser_001:out_valid -> rsp_mux:sink2_valid
wire crosser_001_out_startofpacket; // crosser_001:out_startofpacket -> rsp_mux:sink2_startofpacket
wire [84:0] crosser_001_out_data; // crosser_001:out_data -> rsp_mux:sink2_data
wire [5:0] crosser_001_out_channel; // crosser_001:out_channel -> rsp_mux:sink2_channel
wire crosser_001_out_ready; // rsp_mux:sink2_ready -> crosser_001:out_ready
wire [5:0] ctrl_m0_limiter_cmd_valid_data; // ctrl_m0_limiter:cmd_src_valid -> cmd_demux:sink_valid
altera_merlin_master_translator #(
.AV_ADDRESS_W (11),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (11),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) ctrl_m0_translator (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (ctrl_m0_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (ctrl_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (ctrl_m0_translator_avalon_universal_master_0_read), // .read
.uav_write (ctrl_m0_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (ctrl_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (ctrl_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (ctrl_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (ctrl_m0_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (ctrl_m0_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (ctrl_m0_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (ctrl_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (ctrl_m0_address), // avalon_anti_master_0.address
.av_waitrequest (ctrl_m0_waitrequest), // .waitrequest
.av_burstcount (ctrl_m0_burstcount), // .burstcount
.av_byteenable (ctrl_m0_byteenable), // .byteenable
.av_read (ctrl_m0_read), // .read
.av_readdata (ctrl_m0_readdata), // .readdata
.av_readdatavalid (ctrl_m0_readdatavalid), // .readdatavalid
.av_write (ctrl_m0_write), // .write
.av_writedata (ctrl_m0_writedata), // .writedata
.av_debugaccess (ctrl_m0_debugaccess), // .debugaccess
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (6),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (11),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (3),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) pll_reconfig_0_mgmt_avalon_slave_translator (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (pll_reconfig_0_mgmt_avalon_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (pll_reconfig_0_mgmt_avalon_slave_agent_m0_burstcount), // .burstcount
.uav_read (pll_reconfig_0_mgmt_avalon_slave_agent_m0_read), // .read
.uav_write (pll_reconfig_0_mgmt_avalon_slave_agent_m0_write), // .write
.uav_waitrequest (pll_reconfig_0_mgmt_avalon_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (pll_reconfig_0_mgmt_avalon_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (pll_reconfig_0_mgmt_avalon_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (pll_reconfig_0_mgmt_avalon_slave_agent_m0_readdata), // .readdata
.uav_writedata (pll_reconfig_0_mgmt_avalon_slave_agent_m0_writedata), // .writedata
.uav_lock (pll_reconfig_0_mgmt_avalon_slave_agent_m0_lock), // .lock
.uav_debugaccess (pll_reconfig_0_mgmt_avalon_slave_agent_m0_debugaccess), // .debugaccess
.av_address (pll_reconfig_0_mgmt_avalon_slave_address), // avalon_anti_slave_0.address
.av_write (pll_reconfig_0_mgmt_avalon_slave_write), // .write
.av_read (pll_reconfig_0_mgmt_avalon_slave_read), // .read
.av_readdata (pll_reconfig_0_mgmt_avalon_slave_readdata), // .readdata
.av_writedata (pll_reconfig_0_mgmt_avalon_slave_writedata), // .writedata
.av_waitrequest (pll_reconfig_0_mgmt_avalon_slave_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (8),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (11),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (2),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) pll_rom_s1_translator (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (pll_rom_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (pll_rom_s1_agent_m0_burstcount), // .burstcount
.uav_read (pll_rom_s1_agent_m0_read), // .read
.uav_write (pll_rom_s1_agent_m0_write), // .write
.uav_waitrequest (pll_rom_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (pll_rom_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (pll_rom_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (pll_rom_s1_agent_m0_readdata), // .readdata
.uav_writedata (pll_rom_s1_agent_m0_writedata), // .writedata
.uav_lock (pll_rom_s1_agent_m0_lock), // .lock
.uav_debugaccess (pll_rom_s1_agent_m0_debugaccess), // .debugaccess
.av_address (pll_rom_s1_address), // avalon_anti_slave_0.address
.av_write (pll_rom_s1_write), // .write
.av_readdata (pll_rom_s1_readdata), // .readdata
.av_writedata (pll_rom_s1_writedata), // .writedata
.av_byteenable (pll_rom_s1_byteenable), // .byteenable
.av_chipselect (pll_rom_s1_chipselect), // .chipselect
.av_clken (pll_rom_s1_clken), // .clken
.av_debugaccess (pll_rom_s1_debugaccess), // .debugaccess
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (11),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) counter_s_translator (
.clk (global_routing_kernel_clk_global_clk_clk), // clk.clk
.reset (counter_clk_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (counter_s_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (counter_s_agent_m0_burstcount), // .burstcount
.uav_read (counter_s_agent_m0_read), // .read
.uav_write (counter_s_agent_m0_write), // .write
.uav_waitrequest (counter_s_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (counter_s_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (counter_s_agent_m0_byteenable), // .byteenable
.uav_readdata (counter_s_agent_m0_readdata), // .readdata
.uav_writedata (counter_s_agent_m0_writedata), // .writedata
.uav_lock (counter_s_agent_m0_lock), // .lock
.uav_debugaccess (counter_s_agent_m0_debugaccess), // .debugaccess
.av_address (counter_s_address), // avalon_anti_slave_0.address
.av_write (counter_s_write), // .write
.av_read (counter_s_read), // .read
.av_readdata (counter_s_readdata), // .readdata
.av_writedata (counter_s_writedata), // .writedata
.av_byteenable (counter_s_byteenable), // .byteenable
.av_readdatavalid (counter_s_readdatavalid), // .readdatavalid
.av_waitrequest (counter_s_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (11),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) pll_sw_reset_s_translator (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (pll_sw_reset_s_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (pll_sw_reset_s_agent_m0_burstcount), // .burstcount
.uav_read (pll_sw_reset_s_agent_m0_read), // .read
.uav_write (pll_sw_reset_s_agent_m0_write), // .write
.uav_waitrequest (pll_sw_reset_s_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (pll_sw_reset_s_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (pll_sw_reset_s_agent_m0_byteenable), // .byteenable
.uav_readdata (pll_sw_reset_s_agent_m0_readdata), // .readdata
.uav_writedata (pll_sw_reset_s_agent_m0_writedata), // .writedata
.uav_lock (pll_sw_reset_s_agent_m0_lock), // .lock
.uav_debugaccess (pll_sw_reset_s_agent_m0_debugaccess), // .debugaccess
.av_write (pll_sw_reset_s_write), // avalon_anti_slave_0.write
.av_read (pll_sw_reset_s_read), // .read
.av_readdata (pll_sw_reset_s_readdata), // .readdata
.av_writedata (pll_sw_reset_s_writedata), // .writedata
.av_byteenable (pll_sw_reset_s_byteenable), // .byteenable
.av_waitrequest (pll_sw_reset_s_waitrequest), // .waitrequest
.av_address (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (11),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) pll_lock_avs_0_s_translator (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (pll_lock_avs_0_s_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (pll_lock_avs_0_s_agent_m0_burstcount), // .burstcount
.uav_read (pll_lock_avs_0_s_agent_m0_read), // .read
.uav_write (pll_lock_avs_0_s_agent_m0_write), // .write
.uav_waitrequest (pll_lock_avs_0_s_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (pll_lock_avs_0_s_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (pll_lock_avs_0_s_agent_m0_byteenable), // .byteenable
.uav_readdata (pll_lock_avs_0_s_agent_m0_readdata), // .readdata
.uav_writedata (pll_lock_avs_0_s_agent_m0_writedata), // .writedata
.uav_lock (pll_lock_avs_0_s_agent_m0_lock), // .lock
.uav_debugaccess (pll_lock_avs_0_s_agent_m0_debugaccess), // .debugaccess
.av_read (pll_lock_avs_0_s_read), // avalon_anti_slave_0.read
.av_readdata (pll_lock_avs_0_s_readdata), // .readdata
.av_address (), // (terminated)
.av_write (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (11),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) version_id_0_s_translator (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (version_id_0_s_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (version_id_0_s_agent_m0_burstcount), // .burstcount
.uav_read (version_id_0_s_agent_m0_read), // .read
.uav_write (version_id_0_s_agent_m0_write), // .write
.uav_waitrequest (version_id_0_s_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (version_id_0_s_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (version_id_0_s_agent_m0_byteenable), // .byteenable
.uav_readdata (version_id_0_s_agent_m0_readdata), // .readdata
.uav_writedata (version_id_0_s_agent_m0_writedata), // .writedata
.uav_lock (version_id_0_s_agent_m0_lock), // .lock
.uav_debugaccess (version_id_0_s_agent_m0_debugaccess), // .debugaccess
.av_read (version_id_0_s_read), // avalon_anti_slave_0.read
.av_readdata (version_id_0_s_readdata), // .readdata
.av_address (), // (terminated)
.av_write (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (75),
.PKT_PROTECTION_L (73),
.PKT_BEGIN_BURST (64),
.PKT_BURSTWRAP_H (56),
.PKT_BURSTWRAP_L (56),
.PKT_BURST_SIZE_H (59),
.PKT_BURST_SIZE_L (57),
.PKT_BURST_TYPE_H (61),
.PKT_BURST_TYPE_L (60),
.PKT_BYTE_CNT_H (55),
.PKT_BYTE_CNT_L (53),
.PKT_ADDR_H (46),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (47),
.PKT_TRANS_POSTED (48),
.PKT_TRANS_WRITE (49),
.PKT_TRANS_READ (50),
.PKT_TRANS_LOCK (51),
.PKT_TRANS_EXCLUSIVE (52),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (68),
.PKT_SRC_ID_L (66),
.PKT_DEST_ID_H (71),
.PKT_DEST_ID_L (69),
.PKT_THREAD_ID_H (72),
.PKT_THREAD_ID_L (72),
.PKT_CACHE_H (79),
.PKT_CACHE_L (76),
.PKT_DATA_SIDEBAND_H (63),
.PKT_DATA_SIDEBAND_L (63),
.PKT_QOS_H (65),
.PKT_QOS_L (65),
.PKT_ADDR_SIDEBAND_H (62),
.PKT_ADDR_SIDEBAND_L (62),
.PKT_RESPONSE_STATUS_H (81),
.PKT_RESPONSE_STATUS_L (80),
.PKT_ORI_BURST_SIZE_L (82),
.PKT_ORI_BURST_SIZE_H (84),
.ST_DATA_W (85),
.ST_CHANNEL_W (6),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (1),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) ctrl_m0_agent (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (ctrl_m0_translator_avalon_universal_master_0_address), // av.address
.av_write (ctrl_m0_translator_avalon_universal_master_0_write), // .write
.av_read (ctrl_m0_translator_avalon_universal_master_0_read), // .read
.av_writedata (ctrl_m0_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (ctrl_m0_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (ctrl_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (ctrl_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (ctrl_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (ctrl_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (ctrl_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (ctrl_m0_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (ctrl_m0_agent_cp_valid), // cp.valid
.cp_data (ctrl_m0_agent_cp_data), // .data
.cp_startofpacket (ctrl_m0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (ctrl_m0_agent_cp_endofpacket), // .endofpacket
.cp_ready (ctrl_m0_agent_cp_ready), // .ready
.rp_valid (ctrl_m0_limiter_rsp_src_valid), // rp.valid
.rp_data (ctrl_m0_limiter_rsp_src_data), // .data
.rp_channel (ctrl_m0_limiter_rsp_src_channel), // .channel
.rp_startofpacket (ctrl_m0_limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (ctrl_m0_limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (ctrl_m0_limiter_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (64),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (46),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (47),
.PKT_TRANS_POSTED (48),
.PKT_TRANS_WRITE (49),
.PKT_TRANS_READ (50),
.PKT_TRANS_LOCK (51),
.PKT_SRC_ID_H (68),
.PKT_SRC_ID_L (66),
.PKT_DEST_ID_H (71),
.PKT_DEST_ID_L (69),
.PKT_BURSTWRAP_H (56),
.PKT_BURSTWRAP_L (56),
.PKT_BYTE_CNT_H (55),
.PKT_BYTE_CNT_L (53),
.PKT_PROTECTION_H (75),
.PKT_PROTECTION_L (73),
.PKT_RESPONSE_STATUS_H (81),
.PKT_RESPONSE_STATUS_L (80),
.PKT_BURST_SIZE_H (59),
.PKT_BURST_SIZE_L (57),
.PKT_ORI_BURST_SIZE_L (82),
.PKT_ORI_BURST_SIZE_H (84),
.ST_CHANNEL_W (6),
.ST_DATA_W (85),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) pll_reconfig_0_mgmt_avalon_slave_agent (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (pll_reconfig_0_mgmt_avalon_slave_agent_m0_address), // m0.address
.m0_burstcount (pll_reconfig_0_mgmt_avalon_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (pll_reconfig_0_mgmt_avalon_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (pll_reconfig_0_mgmt_avalon_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (pll_reconfig_0_mgmt_avalon_slave_agent_m0_lock), // .lock
.m0_readdata (pll_reconfig_0_mgmt_avalon_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (pll_reconfig_0_mgmt_avalon_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (pll_reconfig_0_mgmt_avalon_slave_agent_m0_read), // .read
.m0_waitrequest (pll_reconfig_0_mgmt_avalon_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (pll_reconfig_0_mgmt_avalon_slave_agent_m0_writedata), // .writedata
.m0_write (pll_reconfig_0_mgmt_avalon_slave_agent_m0_write), // .write
.rp_endofpacket (pll_reconfig_0_mgmt_avalon_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (pll_reconfig_0_mgmt_avalon_slave_agent_rp_ready), // .ready
.rp_valid (pll_reconfig_0_mgmt_avalon_slave_agent_rp_valid), // .valid
.rp_data (pll_reconfig_0_mgmt_avalon_slave_agent_rp_data), // .data
.rp_startofpacket (pll_reconfig_0_mgmt_avalon_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_src_ready), // cp.ready
.cp_valid (cmd_mux_src_valid), // .valid
.cp_data (cmd_mux_src_data), // .data
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_src_channel), // .channel
.rf_sink_ready (pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (pll_reconfig_0_mgmt_avalon_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (pll_reconfig_0_mgmt_avalon_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (pll_reconfig_0_mgmt_avalon_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (pll_reconfig_0_mgmt_avalon_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (pll_reconfig_0_mgmt_avalon_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (pll_reconfig_0_mgmt_avalon_slave_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (pll_reconfig_0_mgmt_avalon_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (pll_reconfig_0_mgmt_avalon_slave_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (pll_reconfig_0_mgmt_avalon_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (pll_reconfig_0_mgmt_avalon_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (pll_reconfig_0_mgmt_avalon_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (86),
.FIFO_DEPTH (4),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (pll_reconfig_0_mgmt_avalon_slave_agent_rf_source_data), // in.data
.in_valid (pll_reconfig_0_mgmt_avalon_slave_agent_rf_source_valid), // .valid
.in_ready (pll_reconfig_0_mgmt_avalon_slave_agent_rf_source_ready), // .ready
.in_startofpacket (pll_reconfig_0_mgmt_avalon_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (pll_reconfig_0_mgmt_avalon_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (pll_reconfig_0_mgmt_avalon_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (64),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (46),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (47),
.PKT_TRANS_POSTED (48),
.PKT_TRANS_WRITE (49),
.PKT_TRANS_READ (50),
.PKT_TRANS_LOCK (51),
.PKT_SRC_ID_H (68),
.PKT_SRC_ID_L (66),
.PKT_DEST_ID_H (71),
.PKT_DEST_ID_L (69),
.PKT_BURSTWRAP_H (56),
.PKT_BURSTWRAP_L (56),
.PKT_BYTE_CNT_H (55),
.PKT_BYTE_CNT_L (53),
.PKT_PROTECTION_H (75),
.PKT_PROTECTION_L (73),
.PKT_RESPONSE_STATUS_H (81),
.PKT_RESPONSE_STATUS_L (80),
.PKT_BURST_SIZE_H (59),
.PKT_BURST_SIZE_L (57),
.PKT_ORI_BURST_SIZE_L (82),
.PKT_ORI_BURST_SIZE_H (84),
.ST_CHANNEL_W (6),
.ST_DATA_W (85),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) pll_rom_s1_agent (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (pll_rom_s1_agent_m0_address), // m0.address
.m0_burstcount (pll_rom_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (pll_rom_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (pll_rom_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (pll_rom_s1_agent_m0_lock), // .lock
.m0_readdata (pll_rom_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (pll_rom_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (pll_rom_s1_agent_m0_read), // .read
.m0_waitrequest (pll_rom_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (pll_rom_s1_agent_m0_writedata), // .writedata
.m0_write (pll_rom_s1_agent_m0_write), // .write
.rp_endofpacket (pll_rom_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (pll_rom_s1_agent_rp_ready), // .ready
.rp_valid (pll_rom_s1_agent_rp_valid), // .valid
.rp_data (pll_rom_s1_agent_rp_data), // .data
.rp_startofpacket (pll_rom_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_001_src_ready), // cp.ready
.cp_valid (cmd_mux_001_src_valid), // .valid
.cp_data (cmd_mux_001_src_data), // .data
.cp_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_001_src_channel), // .channel
.rf_sink_ready (pll_rom_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (pll_rom_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (pll_rom_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (pll_rom_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (pll_rom_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (pll_rom_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (pll_rom_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (pll_rom_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (pll_rom_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (pll_rom_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (pll_rom_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (pll_rom_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (pll_rom_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (pll_rom_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (pll_rom_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (pll_rom_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (86),
.FIFO_DEPTH (3),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) pll_rom_s1_agent_rsp_fifo (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (pll_rom_s1_agent_rf_source_data), // in.data
.in_valid (pll_rom_s1_agent_rf_source_valid), // .valid
.in_ready (pll_rom_s1_agent_rf_source_ready), // .ready
.in_startofpacket (pll_rom_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (pll_rom_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (pll_rom_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (pll_rom_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (pll_rom_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (pll_rom_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (pll_rom_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (64),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (46),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (47),
.PKT_TRANS_POSTED (48),
.PKT_TRANS_WRITE (49),
.PKT_TRANS_READ (50),
.PKT_TRANS_LOCK (51),
.PKT_SRC_ID_H (68),
.PKT_SRC_ID_L (66),
.PKT_DEST_ID_H (71),
.PKT_DEST_ID_L (69),
.PKT_BURSTWRAP_H (56),
.PKT_BURSTWRAP_L (56),
.PKT_BYTE_CNT_H (55),
.PKT_BYTE_CNT_L (53),
.PKT_PROTECTION_H (75),
.PKT_PROTECTION_L (73),
.PKT_RESPONSE_STATUS_H (81),
.PKT_RESPONSE_STATUS_L (80),
.PKT_BURST_SIZE_H (59),
.PKT_BURST_SIZE_L (57),
.PKT_ORI_BURST_SIZE_L (82),
.PKT_ORI_BURST_SIZE_H (84),
.ST_CHANNEL_W (6),
.ST_DATA_W (85),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) counter_s_agent (
.clk (global_routing_kernel_clk_global_clk_clk), // clk.clk
.reset (counter_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (counter_s_agent_m0_address), // m0.address
.m0_burstcount (counter_s_agent_m0_burstcount), // .burstcount
.m0_byteenable (counter_s_agent_m0_byteenable), // .byteenable
.m0_debugaccess (counter_s_agent_m0_debugaccess), // .debugaccess
.m0_lock (counter_s_agent_m0_lock), // .lock
.m0_readdata (counter_s_agent_m0_readdata), // .readdata
.m0_readdatavalid (counter_s_agent_m0_readdatavalid), // .readdatavalid
.m0_read (counter_s_agent_m0_read), // .read
.m0_waitrequest (counter_s_agent_m0_waitrequest), // .waitrequest
.m0_writedata (counter_s_agent_m0_writedata), // .writedata
.m0_write (counter_s_agent_m0_write), // .write
.rp_endofpacket (counter_s_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (counter_s_agent_rp_ready), // .ready
.rp_valid (counter_s_agent_rp_valid), // .valid
.rp_data (counter_s_agent_rp_data), // .data
.rp_startofpacket (counter_s_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_002_src_ready), // cp.ready
.cp_valid (cmd_mux_002_src_valid), // .valid
.cp_data (cmd_mux_002_src_data), // .data
.cp_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_002_src_channel), // .channel
.rf_sink_ready (counter_s_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (counter_s_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (counter_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (counter_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (counter_s_agent_rsp_fifo_out_data), // .data
.rf_source_ready (counter_s_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (counter_s_agent_rf_source_valid), // .valid
.rf_source_startofpacket (counter_s_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (counter_s_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (counter_s_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (counter_s_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (counter_s_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (counter_s_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (counter_s_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (counter_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (counter_s_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (86),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) counter_s_agent_rsp_fifo (
.clk (global_routing_kernel_clk_global_clk_clk), // clk.clk
.reset (counter_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (counter_s_agent_rf_source_data), // in.data
.in_valid (counter_s_agent_rf_source_valid), // .valid
.in_ready (counter_s_agent_rf_source_ready), // .ready
.in_startofpacket (counter_s_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (counter_s_agent_rf_source_endofpacket), // .endofpacket
.out_data (counter_s_agent_rsp_fifo_out_data), // out.data
.out_valid (counter_s_agent_rsp_fifo_out_valid), // .valid
.out_ready (counter_s_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (counter_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (counter_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) counter_s_agent_rdata_fifo (
.clk (global_routing_kernel_clk_global_clk_clk), // clk.clk
.reset (counter_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (counter_s_agent_rdata_fifo_src_data), // in.data
.in_valid (counter_s_agent_rdata_fifo_src_valid), // .valid
.in_ready (counter_s_agent_rdata_fifo_src_ready), // .ready
.out_data (counter_s_agent_rdata_fifo_out_data), // out.data
.out_valid (counter_s_agent_rdata_fifo_out_valid), // .valid
.out_ready (counter_s_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (64),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (46),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (47),
.PKT_TRANS_POSTED (48),
.PKT_TRANS_WRITE (49),
.PKT_TRANS_READ (50),
.PKT_TRANS_LOCK (51),
.PKT_SRC_ID_H (68),
.PKT_SRC_ID_L (66),
.PKT_DEST_ID_H (71),
.PKT_DEST_ID_L (69),
.PKT_BURSTWRAP_H (56),
.PKT_BURSTWRAP_L (56),
.PKT_BYTE_CNT_H (55),
.PKT_BYTE_CNT_L (53),
.PKT_PROTECTION_H (75),
.PKT_PROTECTION_L (73),
.PKT_RESPONSE_STATUS_H (81),
.PKT_RESPONSE_STATUS_L (80),
.PKT_BURST_SIZE_H (59),
.PKT_BURST_SIZE_L (57),
.PKT_ORI_BURST_SIZE_L (82),
.PKT_ORI_BURST_SIZE_H (84),
.ST_CHANNEL_W (6),
.ST_DATA_W (85),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) pll_sw_reset_s_agent (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (pll_sw_reset_s_agent_m0_address), // m0.address
.m0_burstcount (pll_sw_reset_s_agent_m0_burstcount), // .burstcount
.m0_byteenable (pll_sw_reset_s_agent_m0_byteenable), // .byteenable
.m0_debugaccess (pll_sw_reset_s_agent_m0_debugaccess), // .debugaccess
.m0_lock (pll_sw_reset_s_agent_m0_lock), // .lock
.m0_readdata (pll_sw_reset_s_agent_m0_readdata), // .readdata
.m0_readdatavalid (pll_sw_reset_s_agent_m0_readdatavalid), // .readdatavalid
.m0_read (pll_sw_reset_s_agent_m0_read), // .read
.m0_waitrequest (pll_sw_reset_s_agent_m0_waitrequest), // .waitrequest
.m0_writedata (pll_sw_reset_s_agent_m0_writedata), // .writedata
.m0_write (pll_sw_reset_s_agent_m0_write), // .write
.rp_endofpacket (pll_sw_reset_s_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (pll_sw_reset_s_agent_rp_ready), // .ready
.rp_valid (pll_sw_reset_s_agent_rp_valid), // .valid
.rp_data (pll_sw_reset_s_agent_rp_data), // .data
.rp_startofpacket (pll_sw_reset_s_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_003_src_ready), // cp.ready
.cp_valid (cmd_mux_003_src_valid), // .valid
.cp_data (cmd_mux_003_src_data), // .data
.cp_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_003_src_channel), // .channel
.rf_sink_ready (pll_sw_reset_s_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (pll_sw_reset_s_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (pll_sw_reset_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (pll_sw_reset_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (pll_sw_reset_s_agent_rsp_fifo_out_data), // .data
.rf_source_ready (pll_sw_reset_s_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (pll_sw_reset_s_agent_rf_source_valid), // .valid
.rf_source_startofpacket (pll_sw_reset_s_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (pll_sw_reset_s_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (pll_sw_reset_s_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (pll_sw_reset_s_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (pll_sw_reset_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (pll_sw_reset_s_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (pll_sw_reset_s_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (pll_sw_reset_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (pll_sw_reset_s_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (86),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) pll_sw_reset_s_agent_rsp_fifo (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (pll_sw_reset_s_agent_rf_source_data), // in.data
.in_valid (pll_sw_reset_s_agent_rf_source_valid), // .valid
.in_ready (pll_sw_reset_s_agent_rf_source_ready), // .ready
.in_startofpacket (pll_sw_reset_s_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (pll_sw_reset_s_agent_rf_source_endofpacket), // .endofpacket
.out_data (pll_sw_reset_s_agent_rsp_fifo_out_data), // out.data
.out_valid (pll_sw_reset_s_agent_rsp_fifo_out_valid), // .valid
.out_ready (pll_sw_reset_s_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (pll_sw_reset_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (pll_sw_reset_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (64),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (46),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (47),
.PKT_TRANS_POSTED (48),
.PKT_TRANS_WRITE (49),
.PKT_TRANS_READ (50),
.PKT_TRANS_LOCK (51),
.PKT_SRC_ID_H (68),
.PKT_SRC_ID_L (66),
.PKT_DEST_ID_H (71),
.PKT_DEST_ID_L (69),
.PKT_BURSTWRAP_H (56),
.PKT_BURSTWRAP_L (56),
.PKT_BYTE_CNT_H (55),
.PKT_BYTE_CNT_L (53),
.PKT_PROTECTION_H (75),
.PKT_PROTECTION_L (73),
.PKT_RESPONSE_STATUS_H (81),
.PKT_RESPONSE_STATUS_L (80),
.PKT_BURST_SIZE_H (59),
.PKT_BURST_SIZE_L (57),
.PKT_ORI_BURST_SIZE_L (82),
.PKT_ORI_BURST_SIZE_H (84),
.ST_CHANNEL_W (6),
.ST_DATA_W (85),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) pll_lock_avs_0_s_agent (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (pll_lock_avs_0_s_agent_m0_address), // m0.address
.m0_burstcount (pll_lock_avs_0_s_agent_m0_burstcount), // .burstcount
.m0_byteenable (pll_lock_avs_0_s_agent_m0_byteenable), // .byteenable
.m0_debugaccess (pll_lock_avs_0_s_agent_m0_debugaccess), // .debugaccess
.m0_lock (pll_lock_avs_0_s_agent_m0_lock), // .lock
.m0_readdata (pll_lock_avs_0_s_agent_m0_readdata), // .readdata
.m0_readdatavalid (pll_lock_avs_0_s_agent_m0_readdatavalid), // .readdatavalid
.m0_read (pll_lock_avs_0_s_agent_m0_read), // .read
.m0_waitrequest (pll_lock_avs_0_s_agent_m0_waitrequest), // .waitrequest
.m0_writedata (pll_lock_avs_0_s_agent_m0_writedata), // .writedata
.m0_write (pll_lock_avs_0_s_agent_m0_write), // .write
.rp_endofpacket (pll_lock_avs_0_s_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (pll_lock_avs_0_s_agent_rp_ready), // .ready
.rp_valid (pll_lock_avs_0_s_agent_rp_valid), // .valid
.rp_data (pll_lock_avs_0_s_agent_rp_data), // .data
.rp_startofpacket (pll_lock_avs_0_s_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_004_src_ready), // cp.ready
.cp_valid (cmd_mux_004_src_valid), // .valid
.cp_data (cmd_mux_004_src_data), // .data
.cp_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_004_src_channel), // .channel
.rf_sink_ready (pll_lock_avs_0_s_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (pll_lock_avs_0_s_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (pll_lock_avs_0_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (pll_lock_avs_0_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (pll_lock_avs_0_s_agent_rsp_fifo_out_data), // .data
.rf_source_ready (pll_lock_avs_0_s_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (pll_lock_avs_0_s_agent_rf_source_valid), // .valid
.rf_source_startofpacket (pll_lock_avs_0_s_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (pll_lock_avs_0_s_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (pll_lock_avs_0_s_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (pll_lock_avs_0_s_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (pll_lock_avs_0_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (pll_lock_avs_0_s_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (pll_lock_avs_0_s_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (pll_lock_avs_0_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (pll_lock_avs_0_s_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (86),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) pll_lock_avs_0_s_agent_rsp_fifo (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (pll_lock_avs_0_s_agent_rf_source_data), // in.data
.in_valid (pll_lock_avs_0_s_agent_rf_source_valid), // .valid
.in_ready (pll_lock_avs_0_s_agent_rf_source_ready), // .ready
.in_startofpacket (pll_lock_avs_0_s_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (pll_lock_avs_0_s_agent_rf_source_endofpacket), // .endofpacket
.out_data (pll_lock_avs_0_s_agent_rsp_fifo_out_data), // out.data
.out_valid (pll_lock_avs_0_s_agent_rsp_fifo_out_valid), // .valid
.out_ready (pll_lock_avs_0_s_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (pll_lock_avs_0_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (pll_lock_avs_0_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (64),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (46),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (47),
.PKT_TRANS_POSTED (48),
.PKT_TRANS_WRITE (49),
.PKT_TRANS_READ (50),
.PKT_TRANS_LOCK (51),
.PKT_SRC_ID_H (68),
.PKT_SRC_ID_L (66),
.PKT_DEST_ID_H (71),
.PKT_DEST_ID_L (69),
.PKT_BURSTWRAP_H (56),
.PKT_BURSTWRAP_L (56),
.PKT_BYTE_CNT_H (55),
.PKT_BYTE_CNT_L (53),
.PKT_PROTECTION_H (75),
.PKT_PROTECTION_L (73),
.PKT_RESPONSE_STATUS_H (81),
.PKT_RESPONSE_STATUS_L (80),
.PKT_BURST_SIZE_H (59),
.PKT_BURST_SIZE_L (57),
.PKT_ORI_BURST_SIZE_L (82),
.PKT_ORI_BURST_SIZE_H (84),
.ST_CHANNEL_W (6),
.ST_DATA_W (85),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) version_id_0_s_agent (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (version_id_0_s_agent_m0_address), // m0.address
.m0_burstcount (version_id_0_s_agent_m0_burstcount), // .burstcount
.m0_byteenable (version_id_0_s_agent_m0_byteenable), // .byteenable
.m0_debugaccess (version_id_0_s_agent_m0_debugaccess), // .debugaccess
.m0_lock (version_id_0_s_agent_m0_lock), // .lock
.m0_readdata (version_id_0_s_agent_m0_readdata), // .readdata
.m0_readdatavalid (version_id_0_s_agent_m0_readdatavalid), // .readdatavalid
.m0_read (version_id_0_s_agent_m0_read), // .read
.m0_waitrequest (version_id_0_s_agent_m0_waitrequest), // .waitrequest
.m0_writedata (version_id_0_s_agent_m0_writedata), // .writedata
.m0_write (version_id_0_s_agent_m0_write), // .write
.rp_endofpacket (version_id_0_s_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (version_id_0_s_agent_rp_ready), // .ready
.rp_valid (version_id_0_s_agent_rp_valid), // .valid
.rp_data (version_id_0_s_agent_rp_data), // .data
.rp_startofpacket (version_id_0_s_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_005_src_ready), // cp.ready
.cp_valid (cmd_mux_005_src_valid), // .valid
.cp_data (cmd_mux_005_src_data), // .data
.cp_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_005_src_channel), // .channel
.rf_sink_ready (version_id_0_s_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (version_id_0_s_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (version_id_0_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (version_id_0_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (version_id_0_s_agent_rsp_fifo_out_data), // .data
.rf_source_ready (version_id_0_s_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (version_id_0_s_agent_rf_source_valid), // .valid
.rf_source_startofpacket (version_id_0_s_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (version_id_0_s_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (version_id_0_s_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (version_id_0_s_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (version_id_0_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (version_id_0_s_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (version_id_0_s_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (version_id_0_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (version_id_0_s_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (86),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) version_id_0_s_agent_rsp_fifo (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (version_id_0_s_agent_rf_source_data), // in.data
.in_valid (version_id_0_s_agent_rf_source_valid), // .valid
.in_ready (version_id_0_s_agent_rf_source_ready), // .ready
.in_startofpacket (version_id_0_s_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (version_id_0_s_agent_rf_source_endofpacket), // .endofpacket
.out_data (version_id_0_s_agent_rsp_fifo_out_data), // out.data
.out_valid (version_id_0_s_agent_rsp_fifo_out_valid), // .valid
.out_ready (version_id_0_s_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (version_id_0_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (version_id_0_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0_router router (
.sink_ready (ctrl_m0_agent_cp_ready), // sink.ready
.sink_valid (ctrl_m0_agent_cp_valid), // .valid
.sink_data (ctrl_m0_agent_cp_data), // .data
.sink_startofpacket (ctrl_m0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (ctrl_m0_agent_cp_endofpacket), // .endofpacket
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_001 router_001 (
.sink_ready (pll_reconfig_0_mgmt_avalon_slave_agent_rp_ready), // sink.ready
.sink_valid (pll_reconfig_0_mgmt_avalon_slave_agent_rp_valid), // .valid
.sink_data (pll_reconfig_0_mgmt_avalon_slave_agent_rp_data), // .data
.sink_startofpacket (pll_reconfig_0_mgmt_avalon_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (pll_reconfig_0_mgmt_avalon_slave_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_001 router_002 (
.sink_ready (pll_rom_s1_agent_rp_ready), // sink.ready
.sink_valid (pll_rom_s1_agent_rp_valid), // .valid
.sink_data (pll_rom_s1_agent_rp_data), // .data
.sink_startofpacket (pll_rom_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (pll_rom_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_003 router_003 (
.sink_ready (counter_s_agent_rp_ready), // sink.ready
.sink_valid (counter_s_agent_rp_valid), // .valid
.sink_data (counter_s_agent_rp_data), // .data
.sink_startofpacket (counter_s_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (counter_s_agent_rp_endofpacket), // .endofpacket
.clk (global_routing_kernel_clk_global_clk_clk), // clk.clk
.reset (counter_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_001 router_004 (
.sink_ready (pll_sw_reset_s_agent_rp_ready), // sink.ready
.sink_valid (pll_sw_reset_s_agent_rp_valid), // .valid
.sink_data (pll_sw_reset_s_agent_rp_data), // .data
.sink_startofpacket (pll_sw_reset_s_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (pll_sw_reset_s_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_001 router_005 (
.sink_ready (pll_lock_avs_0_s_agent_rp_ready), // sink.ready
.sink_valid (pll_lock_avs_0_s_agent_rp_valid), // .valid
.sink_data (pll_lock_avs_0_s_agent_rp_data), // .data
.sink_startofpacket (pll_lock_avs_0_s_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (pll_lock_avs_0_s_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_005_src_ready), // src.ready
.src_valid (router_005_src_valid), // .valid
.src_data (router_005_src_data), // .data
.src_channel (router_005_src_channel), // .channel
.src_startofpacket (router_005_src_startofpacket), // .startofpacket
.src_endofpacket (router_005_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0_router_001 router_006 (
.sink_ready (version_id_0_s_agent_rp_ready), // sink.ready
.sink_valid (version_id_0_s_agent_rp_valid), // .valid
.sink_data (version_id_0_s_agent_rp_data), // .data
.sink_startofpacket (version_id_0_s_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (version_id_0_s_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_006_src_ready), // src.ready
.src_valid (router_006_src_valid), // .valid
.src_data (router_006_src_data), // .data
.src_channel (router_006_src_channel), // .channel
.src_startofpacket (router_006_src_startofpacket), // .startofpacket
.src_endofpacket (router_006_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (71),
.PKT_DEST_ID_L (69),
.PKT_SRC_ID_H (68),
.PKT_SRC_ID_L (66),
.PKT_TRANS_POSTED (48),
.PKT_TRANS_WRITE (49),
.MAX_OUTSTANDING_RESPONSES (5),
.PIPELINED (0),
.ST_DATA_W (85),
.ST_CHANNEL_W (6),
.VALID_WIDTH (6),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.PKT_BYTE_CNT_H (55),
.PKT_BYTE_CNT_L (53),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.REORDER (0)
) ctrl_m0_limiter (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_src_valid), // .valid
.cmd_sink_data (router_src_data), // .data
.cmd_sink_channel (router_src_channel), // .channel
.cmd_sink_startofpacket (router_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_src_endofpacket), // .endofpacket
.cmd_src_ready (ctrl_m0_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (ctrl_m0_limiter_cmd_src_data), // .data
.cmd_src_channel (ctrl_m0_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (ctrl_m0_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (ctrl_m0_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_src_valid), // .valid
.rsp_sink_channel (rsp_mux_src_channel), // .channel
.rsp_sink_data (rsp_mux_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rsp_src_ready (ctrl_m0_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (ctrl_m0_limiter_rsp_src_valid), // .valid
.rsp_src_data (ctrl_m0_limiter_rsp_src_data), // .data
.rsp_src_channel (ctrl_m0_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (ctrl_m0_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (ctrl_m0_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (ctrl_m0_limiter_cmd_valid_data) // cmd_valid.data
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0_cmd_demux cmd_demux (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (ctrl_m0_limiter_cmd_src_ready), // sink.ready
.sink_channel (ctrl_m0_limiter_cmd_src_channel), // .channel
.sink_data (ctrl_m0_limiter_cmd_src_data), // .data
.sink_startofpacket (ctrl_m0_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (ctrl_m0_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (ctrl_m0_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_src1_ready), // src1.ready
.src1_valid (cmd_demux_src1_valid), // .valid
.src1_data (cmd_demux_src1_data), // .data
.src1_channel (cmd_demux_src1_channel), // .channel
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_src2_ready), // src2.ready
.src2_valid (cmd_demux_src2_valid), // .valid
.src2_data (cmd_demux_src2_data), // .data
.src2_channel (cmd_demux_src2_channel), // .channel
.src2_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_src3_ready), // src3.ready
.src3_valid (cmd_demux_src3_valid), // .valid
.src3_data (cmd_demux_src3_data), // .data
.src3_channel (cmd_demux_src3_channel), // .channel
.src3_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_src3_endofpacket), // .endofpacket
.src4_ready (cmd_demux_src4_ready), // src4.ready
.src4_valid (cmd_demux_src4_valid), // .valid
.src4_data (cmd_demux_src4_data), // .data
.src4_channel (cmd_demux_src4_channel), // .channel
.src4_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_demux_src4_endofpacket), // .endofpacket
.src5_ready (cmd_demux_src5_ready), // src5.ready
.src5_valid (cmd_demux_src5_valid), // .valid
.src5_data (cmd_demux_src5_data), // .data
.src5_channel (cmd_demux_src5_channel), // .channel
.src5_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_demux_src5_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0_cmd_mux cmd_mux (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0_cmd_mux cmd_mux_001 (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_demux_src1_valid), // .valid
.sink0_channel (cmd_demux_src1_channel), // .channel
.sink0_data (cmd_demux_src1_data), // .data
.sink0_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src1_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0_cmd_mux_002 cmd_mux_002 (
.clk (global_routing_kernel_clk_global_clk_clk), // clk.clk
.reset (counter_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (crosser_out_ready), // sink0.ready
.sink0_valid (crosser_out_valid), // .valid
.sink0_channel (crosser_out_channel), // .channel
.sink0_data (crosser_out_data), // .data
.sink0_startofpacket (crosser_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_out_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0_cmd_mux cmd_mux_003 (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_003_src_ready), // src.ready
.src_valid (cmd_mux_003_src_valid), // .valid
.src_data (cmd_mux_003_src_data), // .data
.src_channel (cmd_mux_003_src_channel), // .channel
.src_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src3_ready), // sink0.ready
.sink0_valid (cmd_demux_src3_valid), // .valid
.sink0_channel (cmd_demux_src3_channel), // .channel
.sink0_data (cmd_demux_src3_data), // .data
.sink0_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src3_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0_cmd_mux cmd_mux_004 (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_004_src_ready), // src.ready
.src_valid (cmd_mux_004_src_valid), // .valid
.src_data (cmd_mux_004_src_data), // .data
.src_channel (cmd_mux_004_src_channel), // .channel
.src_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src4_ready), // sink0.ready
.sink0_valid (cmd_demux_src4_valid), // .valid
.sink0_channel (cmd_demux_src4_channel), // .channel
.sink0_data (cmd_demux_src4_data), // .data
.sink0_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src4_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0_cmd_mux cmd_mux_005 (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_005_src_ready), // src.ready
.src_valid (cmd_mux_005_src_valid), // .valid
.src_data (cmd_mux_005_src_data), // .data
.src_channel (cmd_mux_005_src_channel), // .channel
.src_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src5_ready), // sink0.ready
.sink0_valid (cmd_demux_src5_valid), // .valid
.sink0_channel (cmd_demux_src5_channel), // .channel
.sink0_data (cmd_demux_src5_data), // .data
.sink0_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src5_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_demux rsp_demux (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_001_src_ready), // sink.ready
.sink_channel (router_001_src_channel), // .channel
.sink_data (router_001_src_data), // .data
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.sink_valid (router_001_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_demux rsp_demux_001 (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_002_src_ready), // sink.ready
.sink_channel (router_002_src_channel), // .channel
.sink_data (router_002_src_data), // .data
.sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.sink_valid (router_002_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_demux_002 rsp_demux_002 (
.clk (global_routing_kernel_clk_global_clk_clk), // clk.clk
.reset (counter_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_003_src_ready), // sink.ready
.sink_channel (router_003_src_channel), // .channel
.sink_data (router_003_src_data), // .data
.sink_startofpacket (router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (router_003_src_endofpacket), // .endofpacket
.sink_valid (router_003_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_demux rsp_demux_003 (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_004_src_ready), // sink.ready
.sink_channel (router_004_src_channel), // .channel
.sink_data (router_004_src_data), // .data
.sink_startofpacket (router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (router_004_src_endofpacket), // .endofpacket
.sink_valid (router_004_src_valid), // .valid
.src0_ready (rsp_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_demux_003_src0_valid), // .valid
.src0_data (rsp_demux_003_src0_data), // .data
.src0_channel (rsp_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_003_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_demux rsp_demux_004 (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_005_src_ready), // sink.ready
.sink_channel (router_005_src_channel), // .channel
.sink_data (router_005_src_data), // .data
.sink_startofpacket (router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (router_005_src_endofpacket), // .endofpacket
.sink_valid (router_005_src_valid), // .valid
.src0_ready (rsp_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_demux_004_src0_valid), // .valid
.src0_data (rsp_demux_004_src0_data), // .data
.src0_channel (rsp_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_004_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_demux rsp_demux_005 (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_006_src_ready), // sink.ready
.sink_channel (router_006_src_channel), // .channel
.sink_data (router_006_src_data), // .data
.sink_startofpacket (router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (router_006_src_endofpacket), // .endofpacket
.sink_valid (router_006_src_valid), // .valid
.src0_ready (rsp_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_demux_005_src0_valid), // .valid
.src0_data (rsp_demux_005_src0_data), // .data
.src0_channel (rsp_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_005_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0_rsp_mux rsp_mux (
.clk (clk_clk_clk), // clk.clk
.reset (ctrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src0_valid), // .valid
.sink1_channel (rsp_demux_001_src0_channel), // .channel
.sink1_data (rsp_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (crosser_001_out_ready), // sink2.ready
.sink2_valid (crosser_001_out_valid), // .valid
.sink2_channel (crosser_001_out_channel), // .channel
.sink2_data (crosser_001_out_data), // .data
.sink2_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.sink2_endofpacket (crosser_001_out_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_demux_003_src0_valid), // .valid
.sink3_channel (rsp_demux_003_src0_channel), // .channel
.sink3_data (rsp_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
.sink4_ready (rsp_demux_004_src0_ready), // sink4.ready
.sink4_valid (rsp_demux_004_src0_valid), // .valid
.sink4_channel (rsp_demux_004_src0_channel), // .channel
.sink4_data (rsp_demux_004_src0_data), // .data
.sink4_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_demux_004_src0_endofpacket), // .endofpacket
.sink5_ready (rsp_demux_005_src0_ready), // sink5.ready
.sink5_valid (rsp_demux_005_src0_valid), // .valid
.sink5_channel (rsp_demux_005_src0_channel), // .channel
.sink5_data (rsp_demux_005_src0_data), // .data
.sink5_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.sink5_endofpacket (rsp_demux_005_src0_endofpacket) // .endofpacket
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (85),
.BITS_PER_SYMBOL (85),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (6),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser (
.in_clk (clk_clk_clk), // in_clk.clk
.in_reset (ctrl_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (global_routing_kernel_clk_global_clk_clk), // out_clk.clk
.out_reset (counter_clk_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_demux_src2_ready), // in.ready
.in_valid (cmd_demux_src2_valid), // .valid
.in_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.in_channel (cmd_demux_src2_channel), // .channel
.in_data (cmd_demux_src2_data), // .data
.out_ready (crosser_out_ready), // out.ready
.out_valid (crosser_out_valid), // .valid
.out_startofpacket (crosser_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_out_endofpacket), // .endofpacket
.out_channel (crosser_out_channel), // .channel
.out_data (crosser_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (85),
.BITS_PER_SYMBOL (85),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (6),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_001 (
.in_clk (global_routing_kernel_clk_global_clk_clk), // in_clk.clk
.in_reset (counter_clk_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_clk_clk), // out_clk.clk
.out_reset (ctrl_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_demux_002_src0_ready), // in.ready
.in_valid (rsp_demux_002_src0_valid), // .valid
.in_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.in_channel (rsp_demux_002_src0_channel), // .channel
.in_data (rsp_demux_002_src0_data), // .data
.out_ready (crosser_001_out_ready), // out.ready
.out_valid (crosser_001_out_valid), // .valid
.out_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_001_out_endofpacket), // .endofpacket
.out_channel (crosser_001_out_channel), // .channel
.out_data (crosser_001_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 13 12:48:47 2017
// Host : WK117 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_axi_ethernetlite_0_0/system_axi_ethernetlite_0_0_stub.v
// Design : system_axi_ethernetlite_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35ticsg324-1L
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_ethernetlite,Vivado 2016.4" *)
module system_axi_ethernetlite_0_0(s_axi_aclk, s_axi_aresetn, ip2intc_irpt,
s_axi_awaddr, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid,
s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid,
s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, phy_tx_clk, phy_rx_clk,
phy_crs, phy_dv, phy_rx_data, phy_col, phy_rx_er, phy_rst_n, phy_tx_en, phy_tx_data, phy_mdio_i,
phy_mdio_o, phy_mdio_t, phy_mdc)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,ip2intc_irpt,s_axi_awaddr[12:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[12:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,phy_tx_clk,phy_rx_clk,phy_crs,phy_dv,phy_rx_data[3:0],phy_col,phy_rx_er,phy_rst_n,phy_tx_en,phy_tx_data[3:0],phy_mdio_i,phy_mdio_o,phy_mdio_t,phy_mdc" */;
input s_axi_aclk;
input s_axi_aresetn;
output ip2intc_irpt;
input [12:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [12:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
input phy_tx_clk;
input phy_rx_clk;
input phy_crs;
input phy_dv;
input [3:0]phy_rx_data;
input phy_col;
input phy_rx_er;
output phy_rst_n;
output phy_tx_en;
output [3:0]phy_tx_data;
input phy_mdio_i;
output phy_mdio_o;
output phy_mdio_t;
output phy_mdc;
endmodule
|
`timescale 1ns/10ps
module SwcSim;
reg clock;
reg reset;
reg [11:0] inst;
reg inst_en;
wire [23:0] counter;
wire ready;
initial begin
#0 $dumpfile(`VCDFILE);
#0 $dumpvars;
#1000 $finish;
end
initial begin
#0 clock = 1;
forever #2 clock = ~clock;
end
initial begin
#0 reset = 0;
#1 reset = 1;
#4 reset = 0;
end
initial begin
#0.1 inst_en = 0;
// Test each instruction.
#8 inst = {`Swc_LD0,8'hA0};
inst_en = 1;
#4 inst = {`Swc_LD1,8'h0E};
inst_en = 1;
#4 inst = {`Swc_LD2,8'hBB};
inst_en = 1;
#4 inst = {`Swc_COU,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Swc_COD,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Swc_LD1,8'h00};
inst_en = 1;
#4 inst = {`Swc_LD2,8'h00};
inst_en = 1;
#4 inst = {`Swc_CCU,8'bxxxxxxxx};
inst_en = 1;
#16 inst = {`Swc_CCS,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Swc_CCD,8'bxxxxxxxx};
inst_en = 1;
#16 inst = {`Swc_CCS,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Swc_NOP,8'bxxxxxxxx};
inst_en = 1;
// Test disabled instruction.
#4 inst = {`Swc_LD0,8'hEE};
inst_en = 0;
#4 inst = {`Swc_LD0,8'hAE};
inst_en = 1;
// Test bad instruction.
#4 inst = {8'hF,8'h10};
inst_en = 1;
#4 inst = {`Swc_LD1,8'hAE};
inst_en = 1;
#4 reset = 1;
#8 reset = 0;
#4 inst = {`Swc_LD1,8'hB0};
inst_en = 1;
#4 inst = {`Swc_NOP,8'bxxxxxxxx};
inst_en = 1;
// Test a complete count up.
#4 inst = {`Swc_LD0,8'hF0};
inst_en = 1;
#4 inst = {`Swc_LD1,8'hFF};
inst_en = 1;
#4 inst = {`Swc_LD2,8'hFF};
inst_en = 1;
#4 inst = {`Swc_CCU,8'bxxxxxxxx};
inst_en = 1;
#4 inst_en = 0;
// Test a complete count down.
#72 inst = {`Swc_LD0,8'h0F};
inst_en = 1;
#4 inst = {`Swc_CCD,8'bxxxxxxxx};
inst_en = 1;
#4 inst_en = 0;
// Test an incomplete count up.
#72 inst = {`Swc_LD0,8'hF0};
inst_en = 1;
#4 inst = {`Swc_LD1,8'hFF};
inst_en = 1;
#4 inst = {`Swc_LD2,8'hFF};
inst_en = 1;
#4 inst = {`Swc_CCU,8'bxxxxxxxx};
inst_en = 1;
#4 inst_en = 0;
#20 inst = {`Swc_LD0,8'hF0};
inst_en = 1;
#4 inst = {`Swc_NOP,8'bxxxxxxxx};
inst_en = 1;
// Test an incomplete count down.
#4 inst = {`Swc_LD0,8'h0F};
inst_en = 1;
#4 inst = {`Swc_CCU,8'bxxxxxxxx};
inst_en = 1;
#4 inst_en = 0;
#20 inst = {`Swc_LD0,8'hF0};
inst_en = 1;
#4 inst = {`Swc_NOP,8'bxxxxxxxx};
inst_en = 1;
end
Swc
swc (.clock(clock),
.reset(reset),
.inst(inst),
.inst_en(inst_en),
.counter(counter),
.ready(ready));
endmodule // SwcSim
|
// This counter is a one hot counter; so exactly one output bit is set at all times.
// For example if the value of the counter is zero, then bit 0 will be set.
// This counter makes it extremely fast to detect whether the counter is a particular value.
// The logic is relatively expensive, since it scales with the number of values the counter can take on.
// It is most sensible when you need a decoder to select items in an array, and your access pattern through
// that array is sequential. It will minimize critical paths, and the cost is amortized because the
// alternative is a binary counter and a decoder.
//
// The interface of this counter is analogous to bsg_counter_clear_up:
//
// - the reset_i signal ensures that output to init_val_p; default is 2's complement 0 regardless of up_i or clear_i
// - the clear_i signal sets the 2's complement value to 0 (i.e. all bits except low bit are 0; low bit is 1)
// - the up_i signal increments the counter (corresponds to left rotate). it stacks on top of the clear_i
// so it is legal for the user to assert both clear_i and up_i simultaneous and the effects of both to be reflected.
//
`include "bsg_defines.v"
module bsg_counter_clear_up_one_hot
#(parameter `BSG_INV_PARAM(max_val_p), width_lp=max_val_p+1, init_val_p=(width_lp) ' (1))
(input clk_i
,input reset_i
,input clear_i
,input up_i
,output [width_lp-1:0] count_r_o
);
logic [width_lp-1:0] bits_r, bits_n;
always_comb
begin
bits_n = bits_r;
if (clear_i)
bits_n = (width_lp) ' (1);
// increment is a rotate operator
if (up_i)
bits_n = { bits_n[width_lp-2:0], bits_n[width_lp-1] };
if (reset_i)
bits_n = (width_lp) ' (init_val_p);
end
// clock gate, hopefully
always_ff @(posedge clk_i)
if (reset_i | up_i | clear_i)
bits_r <= bits_n;
assign count_r_o = bits_r;
endmodule
`BSG_ABSTRACT_MODULE(bsg_counter_clear_up_one_hot)
|
module SNPS_CLOCK_GATE_HIGH_DLX_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2 latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
endmodule
module DLX ( CLOCK, RESET, PORT_PC, PORT_INSTR_IRAM, PORT_REGB, PORT_ALU,
PORT_DATA_RAM, PORT_SIZE, PORT_R_W, PORT_EN, RF_ENABLE, RF_RD1, RF_RD2,
RF_WR, RF_ADD_WR, RF_ADD_RD1, RF_ADD_RD2, RF_DATAIN, RF_OUT1, RF_OUT2
);
output [31:0] PORT_PC;
input [31:0] PORT_INSTR_IRAM;
output [31:0] PORT_REGB;
output [31:0] PORT_ALU;
input [31:0] PORT_DATA_RAM;
output [1:0] PORT_SIZE;
output [4:0] RF_ADD_WR;
output [4:0] RF_ADD_RD1;
output [4:0] RF_ADD_RD2;
output [31:0] RF_DATAIN;
input [31:0] RF_OUT1;
input [31:0] RF_OUT2;
input CLOCK, RESET;
output PORT_R_W, PORT_EN, RF_ENABLE, RF_RD1, RF_RD2, RF_WR;
wire \EX_ALU_B[31] , EX_ADD_SUB, ID_SIGN_EXT_CONTROL, \ID_IMM16_EXT[31] ,
WB_SIGN_EXT_16_CONTROL, ID_REGA_ZERO, IF_STALL_SEL, ID_INSTR_31,
ID_INSTR_30, ID_INSTR_29, ID_INSTR_28, ID_INSTR_27, ID_INSTR_26,
WB_INSTR_31, WB_INSTR_30, WB_INSTR_29, WB_INSTR_28, WB_INSTR_27,
WB_INSTR_26, N730, N731, N732, N733, N734, N735, N736, N737, N738,
N739, N740, N741, N742, N743, N744, N745, N746, N747, N748, N749,
N750, N751, N752, N753, N754, N755, N756, N757, N758, N759, N760,
N761, N764, N765, N766, N767, N768, N769, N770, N771, N772, N773,
N774, N775, N776, N777, N778, N779, N780, N781, N782, N783, N784,
N785, N786, N787, N788, N789, N790, N791, N792, N793, N794, N795,
N4708, N4710, N4712, N4716, N4717, N4719, N4721, N4722, N4723, N4724,
N4726, N4727, N4728, N4729, N4730, N4831, N4832, N4833, N4834, N4835,
N4836, N4837, N4839, N4840, N4841, N4842, N4843, N4844, N4845, N4846,
N4847, N4848, N4849, N4850, N4851, N4852, N4853, N4854, N4855, N4856,
N4857, N4860, N4861, N4862, N4863, N4864, N4865, N4866, N4867, N4868,
N4869, N4870, N4871, N4872, N4873, N4874, N4875, N4876, N4877, N4878,
N4879, N4880, N4881, N4882, N4883, N4884, N4885, N4886, N4887, N4888,
N4889, N4890, N4891, N6243, N6244, N6245, N6246, N6247, N6248, N6249,
N6250, N6251, N6252, N6253, N6254, N6255, N6256, N6257, N6258, N6259,
N6260, N6261, N6262, N6263, N6264, N6265, N6266, N6267, N6268, N6269,
N6270, N6271, N6272, N6273, n319, n320, n321, n688, n690, n697, n1189,
n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199,
n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209,
n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220,
n1222, n1223, n1225, n1226, n1227, n1228, n1229, n1230, n1231, n1232,
n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240, n1241, n1242,
n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251, n1252,
n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260, n1261, n1262,
n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270, n1271, n1272,
n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280, n1281, n1282,
n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290, n1291, n1292,
n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300, n1301, n1302,
n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310, n1312, n1313,
n1314, n1315, n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323,
n1324, n1325, n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333,
n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343,
n1344, n1345, n1346, n1347, n1348, n1349, n1351, n1352, n1353, n1355,
n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365,
n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375,
n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385,
n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395,
n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405,
n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415,
n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425,
n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435,
n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445,
n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455,
n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465,
n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475,
n1476, n1477, n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485,
n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495,
n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505,
n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515,
n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525,
n1526, n1527, n1528, n1530, n1531, n1532, n1533, n1534, n1535, n1536,
n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545, n1546,
n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556,
n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566,
n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576,
n1577, n1578, n1580, n1581, n1582, n1583, n1584, n1585, n1587, n1588,
n1589, n1590, \ALU_instance/n39 , \ALU_instance/n38 ,
\ALU_instance/n37 , \ALU_instance/n36 , \ALU_instance/n35 ,
\ALU_instance/n34 , \ALU_instance/n33 , \ALU_instance/n32 ,
\ALU_instance/n31 , \ALU_instance/n30 , \ALU_instance/n29 ,
\ALU_instance/n28 , \ALU_instance/n27 , \ALU_instance/n26 ,
\ALU_instance/n25 , \ALU_instance/n24 , \ALU_instance/n23 ,
\ALU_instance/n22 , \ALU_instance/n21 , \ALU_instance/n20 ,
\ALU_instance/n19 , \ALU_instance/n18 , \ALU_instance/n17 ,
\ALU_instance/n16 , \ALU_instance/n15 , \ALU_instance/n14 ,
\ALU_instance/n13 , \ALU_instance/n12 , \ALU_instance/n11 ,
\ALU_instance/n10 , \ALU_instance/n9 , \ALU_instance/n8 ,
\ALU_instance/n7 , \ALU_instance/n6 , \ALU_instance/n5 ,
\ALU_instance/n4 , \ALU_instance/SHIFTER_OUT[0] ,
\ALU_instance/SHIFTER_OUT[1] , \ALU_instance/SHIFTER_OUT[2] ,
\ALU_instance/SHIFTER_OUT[3] , \ALU_instance/SHIFTER_OUT[4] ,
\ALU_instance/SHIFTER_OUT[5] , \ALU_instance/SHIFTER_OUT[6] ,
\ALU_instance/SHIFTER_OUT[7] , \ALU_instance/SHIFTER_OUT[8] ,
\ALU_instance/SHIFTER_OUT[9] , \ALU_instance/SHIFTER_OUT[10] ,
\ALU_instance/SHIFTER_OUT[11] , \ALU_instance/SHIFTER_OUT[12] ,
\ALU_instance/SHIFTER_OUT[13] , \ALU_instance/SHIFTER_OUT[14] ,
\ALU_instance/SHIFTER_OUT[15] , \ALU_instance/SHIFTER_OUT[16] ,
\ALU_instance/SHIFTER_OUT[17] , \ALU_instance/SHIFTER_OUT[18] ,
\ALU_instance/SHIFTER_OUT[19] , \ALU_instance/SHIFTER_OUT[20] ,
\ALU_instance/SHIFTER_OUT[21] , \ALU_instance/SHIFTER_OUT[22] ,
\ALU_instance/SHIFTER_OUT[23] , \ALU_instance/SHIFTER_OUT[24] ,
\ALU_instance/SHIFTER_OUT[25] , \ALU_instance/SHIFTER_OUT[26] ,
\ALU_instance/SHIFTER_OUT[27] , \ALU_instance/SHIFTER_OUT[28] ,
\ALU_instance/SHIFTER_OUT[29] , \ALU_instance/SHIFTER_OUT[30] ,
\ALU_instance/SHIFTER_OUT[31] , \ALU_instance/LOGIC_OUT[0] ,
\ALU_instance/LOGIC_OUT[1] , \ALU_instance/LOGIC_OUT[2] ,
\ALU_instance/LOGIC_OUT[3] , \ALU_instance/LOGIC_OUT[4] ,
\ALU_instance/LOGIC_OUT[5] , \ALU_instance/LOGIC_OUT[6] ,
\ALU_instance/LOGIC_OUT[7] , \ALU_instance/LOGIC_OUT[8] ,
\ALU_instance/LOGIC_OUT[9] , \ALU_instance/LOGIC_OUT[10] ,
\ALU_instance/LOGIC_OUT[11] , \ALU_instance/LOGIC_OUT[12] ,
\ALU_instance/LOGIC_OUT[13] , \ALU_instance/LOGIC_OUT[14] ,
\ALU_instance/LOGIC_OUT[15] , \ALU_instance/LOGIC_OUT[16] ,
\ALU_instance/LOGIC_OUT[17] , \ALU_instance/LOGIC_OUT[18] ,
\ALU_instance/LOGIC_OUT[19] , \ALU_instance/LOGIC_OUT[20] ,
\ALU_instance/LOGIC_OUT[21] , \ALU_instance/LOGIC_OUT[22] ,
\ALU_instance/LOGIC_OUT[23] , \ALU_instance/LOGIC_OUT[24] ,
\ALU_instance/LOGIC_OUT[25] , \ALU_instance/LOGIC_OUT[26] ,
\ALU_instance/LOGIC_OUT[27] , \ALU_instance/LOGIC_OUT[28] ,
\ALU_instance/LOGIC_OUT[29] , \ALU_instance/LOGIC_OUT[30] ,
\ALU_instance/LOGIC_OUT[31] , \ALU_instance/COMPARATOR_OUT[0] ,
\ALU_instance/ADDER_OUT[0] , \ALU_instance/ADDER_OUT[1] ,
\ALU_instance/ADDER_OUT[2] , \ALU_instance/ADDER_OUT[3] ,
\ALU_instance/ADDER_OUT[4] , \ALU_instance/ADDER_OUT[5] ,
\ALU_instance/ADDER_OUT[6] , \ALU_instance/ADDER_OUT[7] ,
\ALU_instance/ADDER_OUT[8] , \ALU_instance/ADDER_OUT[9] ,
\ALU_instance/ADDER_OUT[10] , \ALU_instance/ADDER_OUT[11] ,
\ALU_instance/ADDER_OUT[12] , \ALU_instance/ADDER_OUT[13] ,
\ALU_instance/ADDER_OUT[14] , \ALU_instance/ADDER_OUT[15] ,
\ALU_instance/ADDER_OUT[16] , \ALU_instance/ADDER_OUT[17] ,
\ALU_instance/ADDER_OUT[18] , \ALU_instance/ADDER_OUT[19] ,
\ALU_instance/ADDER_OUT[20] , \ALU_instance/ADDER_OUT[21] ,
\ALU_instance/ADDER_OUT[22] , \ALU_instance/ADDER_OUT[23] ,
\ALU_instance/ADDER_OUT[24] , \ALU_instance/ADDER_OUT[25] ,
\ALU_instance/ADDER_OUT[26] , \ALU_instance/ADDER_OUT[27] ,
\ALU_instance/ADDER_OUT[28] , \ALU_instance/ADDER_OUT[29] ,
\ALU_instance/ADDER_OUT[30] , \ALU_instance/ADDER_OUT[31] ,
\ALU_instance/INTERNAL_B[0] , \ALU_instance/INTERNAL_B[1] ,
\ALU_instance/INTERNAL_B[2] , \ALU_instance/INTERNAL_B[3] ,
\ALU_instance/INTERNAL_B[4] , \ALU_instance/INTERNAL_B[5] ,
\ALU_instance/INTERNAL_B[6] , \ALU_instance/INTERNAL_B[7] ,
\ALU_instance/INTERNAL_B[8] , \ALU_instance/INTERNAL_B[9] ,
\ALU_instance/INTERNAL_B[10] , \ALU_instance/INTERNAL_B[11] ,
\ALU_instance/INTERNAL_B[12] , \ALU_instance/INTERNAL_B[13] ,
\ALU_instance/INTERNAL_B[14] , \ALU_instance/INTERNAL_B[15] ,
\ALU_instance/INTERNAL_B[16] , \ALU_instance/INTERNAL_B[17] ,
\ALU_instance/INTERNAL_B[18] , \ALU_instance/INTERNAL_B[19] ,
\ALU_instance/INTERNAL_B[20] , \ALU_instance/INTERNAL_B[21] ,
\ALU_instance/INTERNAL_B[22] , \ALU_instance/INTERNAL_B[23] ,
\ALU_instance/INTERNAL_B[24] , \ALU_instance/INTERNAL_B[25] ,
\ALU_instance/INTERNAL_B[26] , \ALU_instance/INTERNAL_B[27] ,
\ALU_instance/INTERNAL_B[28] , \ALU_instance/INTERNAL_B[29] ,
\ALU_instance/INTERNAL_B[30] , \ALU_instance/INTERNAL_B[31] ,
\ALU_instance/OVERFLOW , \ALU_instance/ZERO , \BOOTH_instance/n461 ,
\BOOTH_instance/n460 , \BOOTH_instance/n459 , \BOOTH_instance/n458 ,
\BOOTH_instance/n457 , \BOOTH_instance/n456 , \BOOTH_instance/n455 ,
\BOOTH_instance/n454 , \BOOTH_instance/n453 , \BOOTH_instance/n452 ,
\BOOTH_instance/n451 , \BOOTH_instance/n450 , \BOOTH_instance/n449 ,
\BOOTH_instance/n448 , \BOOTH_instance/n447 , \BOOTH_instance/n445 ,
\BOOTH_instance/n443 , \BOOTH_instance/n442 , \BOOTH_instance/n441 ,
\BOOTH_instance/n440 , \BOOTH_instance/n439 , \BOOTH_instance/n438 ,
\BOOTH_instance/n437 , \BOOTH_instance/n436 , \BOOTH_instance/n435 ,
\BOOTH_instance/n434 , \BOOTH_instance/n432 , \BOOTH_instance/n431 ,
\BOOTH_instance/n430 , \BOOTH_instance/n429 , \BOOTH_instance/n428 ,
\BOOTH_instance/n427 , \BOOTH_instance/n426 , \BOOTH_instance/n425 ,
\BOOTH_instance/n424 , \BOOTH_instance/n423 , \BOOTH_instance/n422 ,
\BOOTH_instance/n421 , \BOOTH_instance/n419 , \BOOTH_instance/n418 ,
\BOOTH_instance/n417 , \BOOTH_instance/n416 , \BOOTH_instance/n415 ,
\BOOTH_instance/n414 , \BOOTH_instance/n413 , \BOOTH_instance/n412 ,
\BOOTH_instance/n411 , \BOOTH_instance/n410 , \BOOTH_instance/n409 ,
\BOOTH_instance/n408 , \BOOTH_instance/n406 , \BOOTH_instance/n405 ,
\BOOTH_instance/n404 , \BOOTH_instance/n403 , \BOOTH_instance/n402 ,
\BOOTH_instance/n401 , \BOOTH_instance/n400 , \BOOTH_instance/n399 ,
\BOOTH_instance/n398 , \BOOTH_instance/n397 , \BOOTH_instance/n396 ,
\BOOTH_instance/n395 , \BOOTH_instance/n394 , \BOOTH_instance/n393 ,
\BOOTH_instance/n392 , \BOOTH_instance/n391 , \BOOTH_instance/n390 ,
\BOOTH_instance/n389 , \BOOTH_instance/n388 , \BOOTH_instance/n387 ,
\BOOTH_instance/n386 , \BOOTH_instance/n385 , \BOOTH_instance/n384 ,
\BOOTH_instance/n383 , \BOOTH_instance/n382 , \BOOTH_instance/n380 ,
\BOOTH_instance/n379 , \BOOTH_instance/n378 , \BOOTH_instance/n377 ,
\BOOTH_instance/n376 , \BOOTH_instance/n375 , \BOOTH_instance/n374 ,
\BOOTH_instance/n373 , \BOOTH_instance/n372 , \BOOTH_instance/n371 ,
\BOOTH_instance/n370 , \BOOTH_instance/n369 , \BOOTH_instance/n368 ,
\BOOTH_instance/n367 , \BOOTH_instance/n366 , \BOOTH_instance/n365 ,
\BOOTH_instance/n364 , \BOOTH_instance/n363 , \BOOTH_instance/n362 ,
\BOOTH_instance/n361 , \BOOTH_instance/n360 , \BOOTH_instance/n359 ,
\BOOTH_instance/n358 , \BOOTH_instance/n357 , \BOOTH_instance/n356 ,
\BOOTH_instance/n355 , \BOOTH_instance/n353 , \BOOTH_instance/n352 ,
\BOOTH_instance/n351 , \BOOTH_instance/n350 , \BOOTH_instance/n349 ,
\BOOTH_instance/n348 , \BOOTH_instance/n347 , \BOOTH_instance/n346 ,
\BOOTH_instance/n345 , \BOOTH_instance/n344 , \BOOTH_instance/n343 ,
\BOOTH_instance/n342 , \BOOTH_instance/n341 , \BOOTH_instance/n340 ,
\BOOTH_instance/n339 , \BOOTH_instance/n338 , \BOOTH_instance/n337 ,
\BOOTH_instance/n336 , \BOOTH_instance/n335 , \BOOTH_instance/n334 ,
\BOOTH_instance/n333 , \BOOTH_instance/n332 , \BOOTH_instance/n331 ,
\BOOTH_instance/n330 , \BOOTH_instance/n329 , \BOOTH_instance/n328 ,
\BOOTH_instance/n327 , \BOOTH_instance/n326 , \BOOTH_instance/n323 ,
\BOOTH_instance/n322 , \BOOTH_instance/n321 , \BOOTH_instance/n320 ,
\BOOTH_instance/n319 , \BOOTH_instance/n318 , \BOOTH_instance/n317 ,
\BOOTH_instance/n316 , \BOOTH_instance/n315 , \BOOTH_instance/n314 ,
\BOOTH_instance/n313 , \BOOTH_instance/n312 , \BOOTH_instance/n311 ,
\BOOTH_instance/n310 , \BOOTH_instance/n309 , \BOOTH_instance/n308 ,
\BOOTH_instance/n307 , \BOOTH_instance/n306 , \BOOTH_instance/n305 ,
\BOOTH_instance/n304 , \BOOTH_instance/n303 , \BOOTH_instance/n302 ,
\BOOTH_instance/n301 , \BOOTH_instance/n300 , \BOOTH_instance/n299 ,
\BOOTH_instance/n297 , \BOOTH_instance/n296 , \BOOTH_instance/n295 ,
\BOOTH_instance/n294 , \BOOTH_instance/n293 , \BOOTH_instance/n292 ,
\BOOTH_instance/n291 , \BOOTH_instance/n290 , \BOOTH_instance/n288 ,
\BOOTH_instance/n287 , \BOOTH_instance/n286 , \BOOTH_instance/n285 ,
\BOOTH_instance/n284 , \BOOTH_instance/n283 , \BOOTH_instance/n282 ,
\BOOTH_instance/n281 , \BOOTH_instance/n280 , \BOOTH_instance/n278 ,
\BOOTH_instance/n277 , \BOOTH_instance/n276 , \BOOTH_instance/n275 ,
\BOOTH_instance/n274 , \BOOTH_instance/n273 , \BOOTH_instance/n272 ,
\BOOTH_instance/n271 , \BOOTH_instance/n269 , \BOOTH_instance/n268 ,
\BOOTH_instance/n267 , \BOOTH_instance/n266 , \BOOTH_instance/n265 ,
\BOOTH_instance/n264 , \BOOTH_instance/n263 , \BOOTH_instance/n261 ,
\BOOTH_instance/n260 , \BOOTH_instance/n259 , \BOOTH_instance/n258 ,
\BOOTH_instance/n257 , \BOOTH_instance/n256 , \BOOTH_instance/n255 ,
\BOOTH_instance/n254 , \BOOTH_instance/n253 , \BOOTH_instance/n252 ,
\BOOTH_instance/n251 , \BOOTH_instance/n249 , \BOOTH_instance/n248 ,
\BOOTH_instance/n247 , \BOOTH_instance/n246 , \BOOTH_instance/n245 ,
\BOOTH_instance/n244 , \BOOTH_instance/n243 , \BOOTH_instance/n242 ,
\BOOTH_instance/n241 , \BOOTH_instance/n239 , \BOOTH_instance/n238 ,
\BOOTH_instance/n237 , \BOOTH_instance/n236 , \BOOTH_instance/n235 ,
\BOOTH_instance/n234 , \BOOTH_instance/n233 , \BOOTH_instance/n232 ,
\BOOTH_instance/n231 , \BOOTH_instance/n229 , \BOOTH_instance/n228 ,
\BOOTH_instance/n227 , \BOOTH_instance/n226 , \BOOTH_instance/n225 ,
\BOOTH_instance/n224 , \BOOTH_instance/n223 , \BOOTH_instance/n222 ,
\BOOTH_instance/n221 , \BOOTH_instance/n219 , \BOOTH_instance/n218 ,
\BOOTH_instance/n217 , \BOOTH_instance/n216 , \BOOTH_instance/n215 ,
\BOOTH_instance/n214 , \BOOTH_instance/n213 , \BOOTH_instance/n212 ,
\BOOTH_instance/n211 , \BOOTH_instance/n209 , \BOOTH_instance/n208 ,
\BOOTH_instance/n207 , \BOOTH_instance/n206 , \BOOTH_instance/n205 ,
\BOOTH_instance/n204 , \BOOTH_instance/n203 , \BOOTH_instance/n202 ,
\BOOTH_instance/n201 , \BOOTH_instance/n199 , \BOOTH_instance/n198 ,
\BOOTH_instance/n197 , \BOOTH_instance/n196 , \BOOTH_instance/n195 ,
\BOOTH_instance/n194 , \BOOTH_instance/n193 , \BOOTH_instance/n192 ,
\BOOTH_instance/n191 , \BOOTH_instance/n189 , \BOOTH_instance/n188 ,
\BOOTH_instance/n187 , \BOOTH_instance/n186 , \BOOTH_instance/n185 ,
\BOOTH_instance/n184 , \BOOTH_instance/n183 , \BOOTH_instance/n182 ,
\BOOTH_instance/n181 , \BOOTH_instance/n180 , \BOOTH_instance/n179 ,
\BOOTH_instance/n177 , \BOOTH_instance/n176 , \BOOTH_instance/n175 ,
\BOOTH_instance/n174 , \BOOTH_instance/n173 , \BOOTH_instance/n172 ,
\BOOTH_instance/n171 , \BOOTH_instance/n170 , \BOOTH_instance/n169 ,
\BOOTH_instance/n168 , \BOOTH_instance/n167 , \BOOTH_instance/n166 ,
\BOOTH_instance/n163 , \BOOTH_instance/n162 , \BOOTH_instance/n161 ,
\BOOTH_instance/n160 , \BOOTH_instance/n159 , \BOOTH_instance/n158 ,
\BOOTH_instance/n157 , \BOOTH_instance/n156 , \BOOTH_instance/n155 ,
\BOOTH_instance/n152 , \BOOTH_instance/n151 , \BOOTH_instance/n150 ,
\BOOTH_instance/n149 , \BOOTH_instance/n148 , \BOOTH_instance/n147 ,
\BOOTH_instance/n146 , \BOOTH_instance/n145 ,
\BOOTH_instance/partial_products[2][16] ,
\BOOTH_instance/partial_products[2][17] ,
\BOOTH_instance/partial_products[2][18] ,
\BOOTH_instance/partial_products[2][19] ,
\BOOTH_instance/partial_products[2][20] ,
\BOOTH_instance/partial_products[2][21] ,
\BOOTH_instance/partial_products[2][22] ,
\BOOTH_instance/partial_products[2][23] ,
\BOOTH_instance/partial_products[2][24] ,
\BOOTH_instance/partial_products[2][25] ,
\BOOTH_instance/partial_products[2][26] ,
\BOOTH_instance/partial_products[2][27] ,
\BOOTH_instance/partial_products[2][28] ,
\BOOTH_instance/partial_products[2][29] ,
\BOOTH_instance/partial_products[2][30] ,
\BOOTH_instance/partial_products[2][31] ,
\BOOTH_instance/partial_products[3][10] ,
\BOOTH_instance/partial_products[3][11] ,
\BOOTH_instance/partial_products[3][12] ,
\BOOTH_instance/partial_products[3][13] ,
\BOOTH_instance/partial_products[3][14] ,
\BOOTH_instance/partial_products[3][15] ,
\BOOTH_instance/partial_products[3][16] ,
\BOOTH_instance/partial_products[3][17] ,
\BOOTH_instance/partial_products[3][18] ,
\BOOTH_instance/partial_products[3][19] ,
\BOOTH_instance/partial_products[3][20] ,
\BOOTH_instance/partial_products[3][21] ,
\BOOTH_instance/partial_products[3][22] ,
\BOOTH_instance/partial_products[3][23] ,
\BOOTH_instance/partial_products[3][24] ,
\BOOTH_instance/partial_products[3][25] ,
\BOOTH_instance/partial_products[3][26] ,
\BOOTH_instance/partial_products[3][27] ,
\BOOTH_instance/partial_products[3][28] ,
\BOOTH_instance/partial_products[3][29] ,
\BOOTH_instance/partial_products[3][30] ,
\BOOTH_instance/partial_products[3][31] ,
\BOOTH_instance/partial_products[3][8] ,
\BOOTH_instance/partial_products[3][9] ,
\BOOTH_instance/partial_products[4][10] ,
\BOOTH_instance/partial_products[4][11] ,
\BOOTH_instance/partial_products[4][12] ,
\BOOTH_instance/partial_products[4][13] ,
\BOOTH_instance/partial_products[4][14] ,
\BOOTH_instance/partial_products[4][15] ,
\BOOTH_instance/partial_products[4][16] ,
\BOOTH_instance/partial_products[4][17] ,
\BOOTH_instance/partial_products[4][18] ,
\BOOTH_instance/partial_products[4][19] ,
\BOOTH_instance/partial_products[4][20] ,
\BOOTH_instance/partial_products[4][21] ,
\BOOTH_instance/partial_products[4][22] ,
\BOOTH_instance/partial_products[4][23] ,
\BOOTH_instance/partial_products[4][24] ,
\BOOTH_instance/partial_products[4][25] ,
\BOOTH_instance/partial_products[4][26] ,
\BOOTH_instance/partial_products[4][27] ,
\BOOTH_instance/partial_products[4][28] ,
\BOOTH_instance/partial_products[4][29] ,
\BOOTH_instance/partial_products[4][30] ,
\BOOTH_instance/partial_products[4][8] ,
\BOOTH_instance/partial_products[4][9] ,
\BOOTH_instance/partial_products[6][12] ,
\BOOTH_instance/partial_products[6][13] ,
\BOOTH_instance/partial_products[6][14] ,
\BOOTH_instance/partial_products[6][15] ,
\BOOTH_instance/partial_products[6][16] ,
\BOOTH_instance/partial_products[6][17] ,
\BOOTH_instance/partial_products[6][18] ,
\BOOTH_instance/partial_products[6][19] ,
\BOOTH_instance/partial_products[6][20] ,
\BOOTH_instance/partial_products[6][21] ,
\BOOTH_instance/partial_products[6][22] ,
\BOOTH_instance/partial_products[6][23] ,
\BOOTH_instance/partial_products[6][24] ,
\BOOTH_instance/partial_products[6][25] ,
\BOOTH_instance/partial_products[6][26] ,
\BOOTH_instance/partial_products[6][27] ,
\BOOTH_instance/partial_products[6][28] ,
\BOOTH_instance/partial_products[6][29] ,
\BOOTH_instance/partial_products[6][30] ,
\BOOTH_instance/partial_products[6][31] ,
\BOOTH_instance/partial_products[7][10] ,
\BOOTH_instance/partial_products[7][11] ,
\BOOTH_instance/partial_products[7][12] ,
\BOOTH_instance/partial_products[7][13] ,
\BOOTH_instance/partial_products[7][14] ,
\BOOTH_instance/partial_products[7][15] ,
\BOOTH_instance/partial_products[7][16] ,
\BOOTH_instance/partial_products[7][17] ,
\BOOTH_instance/partial_products[7][18] ,
\BOOTH_instance/partial_products[7][19] ,
\BOOTH_instance/partial_products[7][20] ,
\BOOTH_instance/partial_products[7][21] ,
\BOOTH_instance/partial_products[7][22] ,
\BOOTH_instance/partial_products[7][23] ,
\BOOTH_instance/partial_products[7][24] ,
\BOOTH_instance/partial_products[7][25] ,
\BOOTH_instance/partial_products[7][26] ,
\BOOTH_instance/partial_products[7][27] ,
\BOOTH_instance/partial_products[7][28] ,
\BOOTH_instance/partial_products[7][29] ,
\BOOTH_instance/partial_products[7][30] ,
\BOOTH_instance/partial_products[7][31] ,
\BOOTH_instance/partial_products[7][4] ,
\BOOTH_instance/partial_products[7][5] ,
\BOOTH_instance/partial_products[7][6] ,
\BOOTH_instance/partial_products[7][7] ,
\BOOTH_instance/partial_products[7][8] ,
\BOOTH_instance/partial_products[7][9] ,
\BOOTH_instance/partial_products[8][10] ,
\BOOTH_instance/partial_products[8][11] ,
\BOOTH_instance/partial_products[8][12] ,
\BOOTH_instance/partial_products[8][13] ,
\BOOTH_instance/partial_products[8][14] ,
\BOOTH_instance/partial_products[8][15] ,
\BOOTH_instance/partial_products[8][16] ,
\BOOTH_instance/partial_products[8][17] ,
\BOOTH_instance/partial_products[8][18] ,
\BOOTH_instance/partial_products[8][19] ,
\BOOTH_instance/partial_products[8][20] ,
\BOOTH_instance/partial_products[8][21] ,
\BOOTH_instance/partial_products[8][22] ,
\BOOTH_instance/partial_products[8][23] ,
\BOOTH_instance/partial_products[8][24] ,
\BOOTH_instance/partial_products[8][25] ,
\BOOTH_instance/partial_products[8][26] ,
\BOOTH_instance/partial_products[8][27] ,
\BOOTH_instance/partial_products[8][28] ,
\BOOTH_instance/partial_products[8][29] ,
\BOOTH_instance/partial_products[8][30] ,
\BOOTH_instance/partial_products[8][31] ,
\BOOTH_instance/partial_products[8][4] ,
\BOOTH_instance/partial_products[8][5] ,
\BOOTH_instance/partial_products[8][6] ,
\BOOTH_instance/partial_products[8][7] ,
\BOOTH_instance/partial_products[8][8] ,
\BOOTH_instance/partial_products[8][9] , \BOOTH_instance/N225 ,
\BOOTH_instance/N224 , \BOOTH_instance/N223 , \BOOTH_instance/N222 ,
\BOOTH_instance/N221 , \BOOTH_instance/N220 , \BOOTH_instance/N219 ,
\BOOTH_instance/N218 , \BOOTH_instance/N217 , \BOOTH_instance/N216 ,
\BOOTH_instance/N215 , \BOOTH_instance/N214 , \BOOTH_instance/N213 ,
\BOOTH_instance/N212 , \BOOTH_instance/N211 ,
\BOOTH_instance/partial_products[5][12] ,
\BOOTH_instance/partial_products[5][13] ,
\BOOTH_instance/partial_products[5][14] ,
\BOOTH_instance/partial_products[5][15] ,
\BOOTH_instance/partial_products[5][16] ,
\BOOTH_instance/partial_products[5][17] ,
\BOOTH_instance/partial_products[5][18] ,
\BOOTH_instance/partial_products[5][19] ,
\BOOTH_instance/partial_products[5][20] ,
\BOOTH_instance/partial_products[5][21] ,
\BOOTH_instance/partial_products[5][22] ,
\BOOTH_instance/partial_products[5][23] ,
\BOOTH_instance/partial_products[5][24] ,
\BOOTH_instance/partial_products[5][25] ,
\BOOTH_instance/partial_products[5][26] ,
\BOOTH_instance/partial_products[5][27] ,
\BOOTH_instance/partial_products[5][28] ,
\BOOTH_instance/partial_products[5][29] ,
\BOOTH_instance/partial_products[5][30] ,
\BOOTH_instance/partial_products[5][31] ,
\BOOTH_instance/decoded[8][16] , \BOOTH_instance/decoded[8][17] ,
\BOOTH_instance/decoded[8][18] , \BOOTH_instance/decoded[8][19] ,
\BOOTH_instance/decoded[8][20] , \BOOTH_instance/decoded[8][21] ,
\BOOTH_instance/decoded[8][22] , \BOOTH_instance/decoded[8][23] ,
\BOOTH_instance/decoded[8][24] , \BOOTH_instance/decoded[8][25] ,
\BOOTH_instance/decoded[8][26] , \BOOTH_instance/decoded[8][27] ,
\BOOTH_instance/decoded[8][28] , \BOOTH_instance/decoded[8][29] ,
\BOOTH_instance/decoded[8][30] , \BOOTH_instance/decoded[8][31] ,
\BOOTH_instance/decoded[5][10] , \BOOTH_instance/decoded[5][11] ,
\BOOTH_instance/decoded[5][12] , \BOOTH_instance/decoded[5][13] ,
\BOOTH_instance/decoded[5][14] , \BOOTH_instance/decoded[5][15] ,
\BOOTH_instance/decoded[5][16] , \BOOTH_instance/decoded[5][17] ,
\BOOTH_instance/decoded[5][18] , \BOOTH_instance/decoded[5][19] ,
\BOOTH_instance/decoded[5][20] , \BOOTH_instance/decoded[5][21] ,
\BOOTH_instance/decoded[5][22] , \BOOTH_instance/decoded[5][23] ,
\BOOTH_instance/decoded[5][24] , \BOOTH_instance/decoded[5][25] ,
\BOOTH_instance/decoded[5][26] , \BOOTH_instance/decoded[5][31] ,
\BOOTH_instance/decoded[4][10] , \BOOTH_instance/decoded[4][11] ,
\BOOTH_instance/decoded[4][12] , \BOOTH_instance/decoded[4][13] ,
\BOOTH_instance/decoded[4][14] , \BOOTH_instance/decoded[4][15] ,
\BOOTH_instance/decoded[4][16] , \BOOTH_instance/decoded[4][17] ,
\BOOTH_instance/decoded[4][18] , \BOOTH_instance/decoded[4][19] ,
\BOOTH_instance/decoded[4][20] , \BOOTH_instance/decoded[4][21] ,
\BOOTH_instance/decoded[4][22] , \BOOTH_instance/decoded[4][23] ,
\BOOTH_instance/decoded[4][24] , \BOOTH_instance/decoded[4][31] ,
\BOOTH_instance/decoded[3][6] , \BOOTH_instance/decoded[3][7] ,
\BOOTH_instance/decoded[3][8] , \BOOTH_instance/decoded[3][9] ,
\BOOTH_instance/decoded[3][10] , \BOOTH_instance/decoded[3][11] ,
\BOOTH_instance/decoded[3][12] , \BOOTH_instance/decoded[3][13] ,
\BOOTH_instance/decoded[3][14] , \BOOTH_instance/decoded[3][15] ,
\BOOTH_instance/decoded[3][16] , \BOOTH_instance/decoded[3][17] ,
\BOOTH_instance/decoded[3][18] , \BOOTH_instance/decoded[3][19] ,
\BOOTH_instance/decoded[3][20] , \BOOTH_instance/decoded[3][21] ,
\BOOTH_instance/decoded[3][22] , \BOOTH_instance/decoded[3][31] ,
\BOOTH_instance/decoded[2][6] , \BOOTH_instance/decoded[2][7] ,
\BOOTH_instance/decoded[2][8] , \BOOTH_instance/decoded[2][9] ,
\BOOTH_instance/decoded[2][10] , \BOOTH_instance/decoded[2][11] ,
\BOOTH_instance/decoded[2][12] , \BOOTH_instance/decoded[2][13] ,
\BOOTH_instance/decoded[2][14] , \BOOTH_instance/decoded[2][15] ,
\BOOTH_instance/decoded[2][16] , \BOOTH_instance/decoded[2][17] ,
\BOOTH_instance/decoded[2][18] , \BOOTH_instance/decoded[2][19] ,
\BOOTH_instance/decoded[2][20] , \BOOTH_instance/decoded[2][31] ,
\BOOTH_instance/decoded[1][2] , \BOOTH_instance/decoded[1][3] ,
\BOOTH_instance/decoded[1][4] , \BOOTH_instance/decoded[1][5] ,
\BOOTH_instance/decoded[1][6] , \BOOTH_instance/decoded[1][7] ,
\BOOTH_instance/decoded[1][8] , \BOOTH_instance/decoded[1][9] ,
\BOOTH_instance/decoded[1][10] , \BOOTH_instance/decoded[1][11] ,
\BOOTH_instance/decoded[1][12] , \BOOTH_instance/decoded[1][13] ,
\BOOTH_instance/decoded[1][14] , \BOOTH_instance/decoded[1][15] ,
\BOOTH_instance/decoded[1][16] , \BOOTH_instance/decoded[1][17] ,
\BOOTH_instance/decoded[1][18] , \BOOTH_instance/decoded[1][31] ,
\BOOTH_instance/decoded[0][31] , \PC_instance/n33 ,
\WB_SIGN_EXT_16_instance/n34 , \WB_SIGN_EXT_16_instance/n33 ,
\WB_SIGN_EXT_16_instance/n28 , \WB_SIGN_EXT_16_instance/n27 ,
\WB_SIGN_EXT_16_instance/n25 , \WB_SIGN_EXT_16_instance/n24 ,
\WB_SIGN_EXT_16_instance/n23 , \WB_SIGN_EXT_16_instance/n22 ,
\zero_instance/n10 , \zero_instance/n9 , \zero_instance/n8 ,
\zero_instance/n7 , \zero_instance/n6 , \zero_instance/n5 ,
\zero_instance/n4 , \zero_instance/n3 , \zero_instance/n2 ,
\zero_instance/n1 , \ID_EX_REGB_REG_instance/n34 ,
\ID_EX_INSTR_REG_instance/n34 , \MEM_WB_ALU_REG_instance/n34 ,
\add_502/carry[4] , \add_502/carry[5] , \add_502/carry[6] ,
\add_502/carry[7] , \add_502/carry[8] , \add_502/carry[9] ,
\add_502/carry[10] , \add_502/carry[11] , \add_502/carry[12] ,
\add_502/carry[13] , \add_502/carry[14] , \add_502/carry[15] ,
\add_502/carry[16] , \add_502/carry[17] , \add_502/carry[18] ,
\add_502/carry[19] , \add_502/carry[20] , \add_502/carry[21] ,
\add_502/carry[22] , \add_502/carry[23] , \add_502/carry[24] ,
\add_502/carry[25] , \add_502/carry[26] , \add_502/carry[27] ,
\add_502/carry[28] , \add_502/carry[29] , \add_502/carry[30] ,
\add_502/carry[31] , \add_545/carry[3] , \add_545/carry[4] ,
\add_545/carry[5] , \add_545/carry[6] , \add_545/carry[7] ,
\add_545/carry[8] , \add_545/carry[9] , \add_545/carry[10] ,
\add_545/carry[11] , \add_545/carry[12] , \add_545/carry[13] ,
\add_545/carry[14] , \add_545/carry[15] , \add_545/carry[16] ,
\add_545/carry[17] , \add_545/carry[18] , \add_545/carry[19] ,
\add_545/carry[20] , \add_545/carry[21] , \add_545/carry[22] ,
\add_545/carry[23] , \add_545/carry[24] , \add_545/carry[25] ,
\add_545/carry[26] , \add_545/carry[27] , \add_545/carry[28] ,
\add_545/carry[29] , \add_545/carry[30] , \add_545/carry[31] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[4] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[5] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[6] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[7] ,
\ALU_instance/COMPARATOR_GENERIC_I/n19 ,
\ALU_instance/COMPARATOR_GENERIC_I/n18 ,
\ALU_instance/COMPARATOR_GENERIC_I/n17 ,
\ALU_instance/COMPARATOR_GENERIC_I/n16 ,
\ALU_instance/COMPARATOR_GENERIC_I/n15 ,
\ALU_instance/COMPARATOR_GENERIC_I/n14 ,
\ALU_instance/COMPARATOR_GENERIC_I/n13 ,
\ALU_instance/COMPARATOR_GENERIC_I/n12 ,
\ALU_instance/COMPARATOR_GENERIC_I/n11 ,
\ALU_instance/COMPARATOR_GENERIC_I/n10 ,
\ALU_instance/COMPARATOR_GENERIC_I/n9 ,
\ALU_instance/COMPARATOR_GENERIC_I/n8 ,
\ALU_instance/COMPARATOR_GENERIC_I/n7 ,
\ALU_instance/COMPARATOR_GENERIC_I/n6 ,
\ALU_instance/COMPARATOR_GENERIC_I/n5 ,
\ALU_instance/COMPARATOR_GENERIC_I/n4 ,
\ALU_instance/LOGIC_GENERIC_I/n127 ,
\ALU_instance/LOGIC_GENERIC_I/n126 ,
\ALU_instance/LOGIC_GENERIC_I/n124 ,
\ALU_instance/LOGIC_GENERIC_I/n123 ,
\ALU_instance/LOGIC_GENERIC_I/n121 ,
\ALU_instance/LOGIC_GENERIC_I/n120 ,
\ALU_instance/LOGIC_GENERIC_I/n118 ,
\ALU_instance/LOGIC_GENERIC_I/n117 ,
\ALU_instance/LOGIC_GENERIC_I/n115 ,
\ALU_instance/LOGIC_GENERIC_I/n114 ,
\ALU_instance/LOGIC_GENERIC_I/n112 ,
\ALU_instance/LOGIC_GENERIC_I/n111 ,
\ALU_instance/LOGIC_GENERIC_I/n109 ,
\ALU_instance/LOGIC_GENERIC_I/n108 ,
\ALU_instance/LOGIC_GENERIC_I/n106 ,
\ALU_instance/LOGIC_GENERIC_I/n105 ,
\ALU_instance/LOGIC_GENERIC_I/n103 ,
\ALU_instance/LOGIC_GENERIC_I/n102 ,
\ALU_instance/LOGIC_GENERIC_I/n100 ,
\ALU_instance/LOGIC_GENERIC_I/n99 ,
\ALU_instance/LOGIC_GENERIC_I/n97 ,
\ALU_instance/LOGIC_GENERIC_I/n96 ,
\ALU_instance/LOGIC_GENERIC_I/n94 ,
\ALU_instance/LOGIC_GENERIC_I/n93 ,
\ALU_instance/LOGIC_GENERIC_I/n91 ,
\ALU_instance/LOGIC_GENERIC_I/n90 ,
\ALU_instance/LOGIC_GENERIC_I/n88 ,
\ALU_instance/LOGIC_GENERIC_I/n87 ,
\ALU_instance/LOGIC_GENERIC_I/n85 ,
\ALU_instance/LOGIC_GENERIC_I/n84 ,
\ALU_instance/LOGIC_GENERIC_I/n82 ,
\ALU_instance/LOGIC_GENERIC_I/n81 ,
\ALU_instance/LOGIC_GENERIC_I/n79 ,
\ALU_instance/LOGIC_GENERIC_I/n78 ,
\ALU_instance/LOGIC_GENERIC_I/n76 ,
\ALU_instance/LOGIC_GENERIC_I/n75 ,
\ALU_instance/LOGIC_GENERIC_I/n73 ,
\ALU_instance/LOGIC_GENERIC_I/n72 ,
\ALU_instance/LOGIC_GENERIC_I/n70 ,
\ALU_instance/LOGIC_GENERIC_I/n69 ,
\ALU_instance/LOGIC_GENERIC_I/n67 ,
\ALU_instance/LOGIC_GENERIC_I/n66 ,
\ALU_instance/LOGIC_GENERIC_I/n64 ,
\ALU_instance/LOGIC_GENERIC_I/n63 ,
\ALU_instance/LOGIC_GENERIC_I/n61 ,
\ALU_instance/LOGIC_GENERIC_I/n60 ,
\ALU_instance/LOGIC_GENERIC_I/n58 ,
\ALU_instance/LOGIC_GENERIC_I/n57 ,
\ALU_instance/LOGIC_GENERIC_I/n55 ,
\ALU_instance/LOGIC_GENERIC_I/n54 ,
\ALU_instance/LOGIC_GENERIC_I/n52 ,
\ALU_instance/LOGIC_GENERIC_I/n51 ,
\ALU_instance/LOGIC_GENERIC_I/n49 ,
\ALU_instance/LOGIC_GENERIC_I/n46 ,
\ALU_instance/LOGIC_GENERIC_I/n45 ,
\ALU_instance/LOGIC_GENERIC_I/n43 ,
\ALU_instance/LOGIC_GENERIC_I/n42 ,
\ALU_instance/LOGIC_GENERIC_I/n40 ,
\ALU_instance/LOGIC_GENERIC_I/n39 ,
\ALU_instance/LOGIC_GENERIC_I/n37 ,
\ALU_instance/LOGIC_GENERIC_I/n36 ,
\ALU_instance/LOGIC_GENERIC_I/n34 ,
\ALU_instance/LOGIC_GENERIC_I/n33 ,
\ALU_instance/SHIFTER_GENERIC_I/n89 ,
\ALU_instance/SHIFTER_GENERIC_I/n88 ,
\ALU_instance/SHIFTER_GENERIC_I/n86 ,
\ALU_instance/SHIFTER_GENERIC_I/n85 ,
\ALU_instance/SHIFTER_GENERIC_I/n84 ,
\ALU_instance/SHIFTER_GENERIC_I/n83 ,
\ALU_instance/SHIFTER_GENERIC_I/n82 ,
\ALU_instance/SHIFTER_GENERIC_I/n81 ,
\ALU_instance/SHIFTER_GENERIC_I/n80 ,
\ALU_instance/SHIFTER_GENERIC_I/n79 ,
\ALU_instance/SHIFTER_GENERIC_I/n78 ,
\ALU_instance/SHIFTER_GENERIC_I/n77 ,
\ALU_instance/SHIFTER_GENERIC_I/n76 ,
\ALU_instance/SHIFTER_GENERIC_I/n75 ,
\ALU_instance/SHIFTER_GENERIC_I/n74 ,
\ALU_instance/SHIFTER_GENERIC_I/n73 ,
\ALU_instance/SHIFTER_GENERIC_I/n72 ,
\ALU_instance/SHIFTER_GENERIC_I/n71 ,
\ALU_instance/SHIFTER_GENERIC_I/n70 ,
\ALU_instance/SHIFTER_GENERIC_I/n69 ,
\ALU_instance/SHIFTER_GENERIC_I/n68 ,
\ALU_instance/SHIFTER_GENERIC_I/n67 ,
\ALU_instance/SHIFTER_GENERIC_I/n66 ,
\ALU_instance/SHIFTER_GENERIC_I/n65 ,
\ALU_instance/SHIFTER_GENERIC_I/n64 ,
\ALU_instance/SHIFTER_GENERIC_I/n63 ,
\ALU_instance/SHIFTER_GENERIC_I/n62 ,
\ALU_instance/SHIFTER_GENERIC_I/n61 ,
\ALU_instance/SHIFTER_GENERIC_I/n60 ,
\ALU_instance/SHIFTER_GENERIC_I/n59 ,
\ALU_instance/SHIFTER_GENERIC_I/n58 ,
\ALU_instance/SHIFTER_GENERIC_I/n57 ,
\ALU_instance/SHIFTER_GENERIC_I/n56 ,
\ALU_instance/SHIFTER_GENERIC_I/n55 ,
\ALU_instance/SHIFTER_GENERIC_I/n54 ,
\ALU_instance/SHIFTER_GENERIC_I/n53 ,
\ALU_instance/SHIFTER_GENERIC_I/n52 ,
\ALU_instance/SHIFTER_GENERIC_I/n51 ,
\ALU_instance/SHIFTER_GENERIC_I/n50 ,
\ALU_instance/SHIFTER_GENERIC_I/n49 ,
\ALU_instance/SHIFTER_GENERIC_I/n48 ,
\ALU_instance/SHIFTER_GENERIC_I/n47 ,
\ALU_instance/SHIFTER_GENERIC_I/n46 ,
\ALU_instance/SHIFTER_GENERIC_I/n45 ,
\ALU_instance/SHIFTER_GENERIC_I/n44 ,
\ALU_instance/SHIFTER_GENERIC_I/n43 ,
\ALU_instance/SHIFTER_GENERIC_I/n42 ,
\ALU_instance/SHIFTER_GENERIC_I/n41 ,
\ALU_instance/SHIFTER_GENERIC_I/n40 ,
\ALU_instance/SHIFTER_GENERIC_I/n39 ,
\ALU_instance/SHIFTER_GENERIC_I/n38 ,
\ALU_instance/SHIFTER_GENERIC_I/n37 ,
\ALU_instance/SHIFTER_GENERIC_I/n36 ,
\ALU_instance/SHIFTER_GENERIC_I/n35 ,
\ALU_instance/SHIFTER_GENERIC_I/n34 ,
\ALU_instance/SHIFTER_GENERIC_I/n33 ,
\ALU_instance/SHIFTER_GENERIC_I/n32 ,
\ALU_instance/SHIFTER_GENERIC_I/n31 ,
\ALU_instance/SHIFTER_GENERIC_I/n30 ,
\ALU_instance/SHIFTER_GENERIC_I/n29 ,
\ALU_instance/SHIFTER_GENERIC_I/n28 ,
\ALU_instance/SHIFTER_GENERIC_I/n27 ,
\ALU_instance/SHIFTER_GENERIC_I/n26 ,
\ALU_instance/SHIFTER_GENERIC_I/n25 ,
\ALU_instance/SHIFTER_GENERIC_I/n13 ,
\ALU_instance/SHIFTER_GENERIC_I/n12 ,
\ALU_instance/SHIFTER_GENERIC_I/n11 ,
\ALU_instance/SHIFTER_GENERIC_I/N265 ,
\ALU_instance/SHIFTER_GENERIC_I/N264 ,
\ALU_instance/SHIFTER_GENERIC_I/N263 ,
\ALU_instance/SHIFTER_GENERIC_I/N262 ,
\ALU_instance/SHIFTER_GENERIC_I/N261 ,
\ALU_instance/SHIFTER_GENERIC_I/N260 ,
\ALU_instance/SHIFTER_GENERIC_I/N259 ,
\ALU_instance/SHIFTER_GENERIC_I/N258 ,
\ALU_instance/SHIFTER_GENERIC_I/N257 ,
\ALU_instance/SHIFTER_GENERIC_I/N256 ,
\ALU_instance/SHIFTER_GENERIC_I/N255 ,
\ALU_instance/SHIFTER_GENERIC_I/N254 ,
\ALU_instance/SHIFTER_GENERIC_I/N253 ,
\ALU_instance/SHIFTER_GENERIC_I/N252 ,
\ALU_instance/SHIFTER_GENERIC_I/N251 ,
\ALU_instance/SHIFTER_GENERIC_I/N250 ,
\ALU_instance/SHIFTER_GENERIC_I/N249 ,
\ALU_instance/SHIFTER_GENERIC_I/N248 ,
\ALU_instance/SHIFTER_GENERIC_I/N247 ,
\ALU_instance/SHIFTER_GENERIC_I/N246 ,
\ALU_instance/SHIFTER_GENERIC_I/N245 ,
\ALU_instance/SHIFTER_GENERIC_I/N244 ,
\ALU_instance/SHIFTER_GENERIC_I/N243 ,
\ALU_instance/SHIFTER_GENERIC_I/N242 ,
\ALU_instance/SHIFTER_GENERIC_I/N241 ,
\ALU_instance/SHIFTER_GENERIC_I/N240 ,
\ALU_instance/SHIFTER_GENERIC_I/N239 ,
\ALU_instance/SHIFTER_GENERIC_I/N238 ,
\ALU_instance/SHIFTER_GENERIC_I/N237 ,
\ALU_instance/SHIFTER_GENERIC_I/N236 ,
\ALU_instance/SHIFTER_GENERIC_I/N235 ,
\ALU_instance/SHIFTER_GENERIC_I/N234 ,
\ALU_instance/SHIFTER_GENERIC_I/N233 ,
\ALU_instance/SHIFTER_GENERIC_I/N232 ,
\ALU_instance/SHIFTER_GENERIC_I/N231 ,
\ALU_instance/SHIFTER_GENERIC_I/N230 ,
\ALU_instance/SHIFTER_GENERIC_I/N229 ,
\ALU_instance/SHIFTER_GENERIC_I/N228 ,
\ALU_instance/SHIFTER_GENERIC_I/N227 ,
\ALU_instance/SHIFTER_GENERIC_I/N226 ,
\ALU_instance/SHIFTER_GENERIC_I/N225 ,
\ALU_instance/SHIFTER_GENERIC_I/N224 ,
\ALU_instance/SHIFTER_GENERIC_I/N223 ,
\ALU_instance/SHIFTER_GENERIC_I/N222 ,
\ALU_instance/SHIFTER_GENERIC_I/N221 ,
\ALU_instance/SHIFTER_GENERIC_I/N220 ,
\ALU_instance/SHIFTER_GENERIC_I/N219 ,
\ALU_instance/SHIFTER_GENERIC_I/N218 ,
\ALU_instance/SHIFTER_GENERIC_I/N217 ,
\ALU_instance/SHIFTER_GENERIC_I/N216 ,
\ALU_instance/SHIFTER_GENERIC_I/N215 ,
\ALU_instance/SHIFTER_GENERIC_I/N214 ,
\ALU_instance/SHIFTER_GENERIC_I/N213 ,
\ALU_instance/SHIFTER_GENERIC_I/N212 ,
\ALU_instance/SHIFTER_GENERIC_I/N211 ,
\ALU_instance/SHIFTER_GENERIC_I/N210 ,
\ALU_instance/SHIFTER_GENERIC_I/N209 ,
\ALU_instance/SHIFTER_GENERIC_I/N208 ,
\ALU_instance/SHIFTER_GENERIC_I/N207 ,
\ALU_instance/SHIFTER_GENERIC_I/N206 ,
\ALU_instance/SHIFTER_GENERIC_I/N205 ,
\ALU_instance/SHIFTER_GENERIC_I/N204 ,
\ALU_instance/SHIFTER_GENERIC_I/N203 ,
\ALU_instance/SHIFTER_GENERIC_I/N202 ,
\ALU_instance/SHIFTER_GENERIC_I/N168 ,
\ALU_instance/SHIFTER_GENERIC_I/N167 ,
\ALU_instance/SHIFTER_GENERIC_I/N166 ,
\ALU_instance/SHIFTER_GENERIC_I/N165 ,
\ALU_instance/SHIFTER_GENERIC_I/N164 ,
\ALU_instance/SHIFTER_GENERIC_I/N163 ,
\ALU_instance/SHIFTER_GENERIC_I/N162 ,
\ALU_instance/SHIFTER_GENERIC_I/N161 ,
\ALU_instance/SHIFTER_GENERIC_I/N160 ,
\ALU_instance/SHIFTER_GENERIC_I/N159 ,
\ALU_instance/SHIFTER_GENERIC_I/N158 ,
\ALU_instance/SHIFTER_GENERIC_I/N157 ,
\ALU_instance/SHIFTER_GENERIC_I/N156 ,
\ALU_instance/SHIFTER_GENERIC_I/N155 ,
\ALU_instance/SHIFTER_GENERIC_I/N154 ,
\ALU_instance/SHIFTER_GENERIC_I/N153 ,
\ALU_instance/SHIFTER_GENERIC_I/N152 ,
\ALU_instance/SHIFTER_GENERIC_I/N151 ,
\ALU_instance/SHIFTER_GENERIC_I/N150 ,
\ALU_instance/SHIFTER_GENERIC_I/N149 ,
\ALU_instance/SHIFTER_GENERIC_I/N148 ,
\ALU_instance/SHIFTER_GENERIC_I/N147 ,
\ALU_instance/SHIFTER_GENERIC_I/N146 ,
\ALU_instance/SHIFTER_GENERIC_I/N145 ,
\ALU_instance/SHIFTER_GENERIC_I/N144 ,
\ALU_instance/SHIFTER_GENERIC_I/N143 ,
\ALU_instance/SHIFTER_GENERIC_I/N142 ,
\ALU_instance/SHIFTER_GENERIC_I/N141 ,
\ALU_instance/SHIFTER_GENERIC_I/N140 ,
\ALU_instance/SHIFTER_GENERIC_I/N139 ,
\ALU_instance/SHIFTER_GENERIC_I/N138 ,
\ALU_instance/SHIFTER_GENERIC_I/N137 ,
\ALU_instance/SHIFTER_GENERIC_I/N135 ,
\ALU_instance/SHIFTER_GENERIC_I/N134 ,
\ALU_instance/SHIFTER_GENERIC_I/N133 ,
\ALU_instance/SHIFTER_GENERIC_I/N132 ,
\ALU_instance/SHIFTER_GENERIC_I/N131 ,
\ALU_instance/SHIFTER_GENERIC_I/N130 ,
\ALU_instance/SHIFTER_GENERIC_I/N129 ,
\ALU_instance/SHIFTER_GENERIC_I/N128 ,
\ALU_instance/SHIFTER_GENERIC_I/N127 ,
\ALU_instance/SHIFTER_GENERIC_I/N126 ,
\ALU_instance/SHIFTER_GENERIC_I/N125 ,
\ALU_instance/SHIFTER_GENERIC_I/N124 ,
\ALU_instance/SHIFTER_GENERIC_I/N123 ,
\ALU_instance/SHIFTER_GENERIC_I/N122 ,
\ALU_instance/SHIFTER_GENERIC_I/N121 ,
\ALU_instance/SHIFTER_GENERIC_I/N120 ,
\ALU_instance/SHIFTER_GENERIC_I/N119 ,
\ALU_instance/SHIFTER_GENERIC_I/N118 ,
\ALU_instance/SHIFTER_GENERIC_I/N117 ,
\ALU_instance/SHIFTER_GENERIC_I/N116 ,
\ALU_instance/SHIFTER_GENERIC_I/N115 ,
\ALU_instance/SHIFTER_GENERIC_I/N114 ,
\ALU_instance/SHIFTER_GENERIC_I/N113 ,
\ALU_instance/SHIFTER_GENERIC_I/N112 ,
\ALU_instance/SHIFTER_GENERIC_I/N111 ,
\ALU_instance/SHIFTER_GENERIC_I/N110 ,
\ALU_instance/SHIFTER_GENERIC_I/N109 ,
\ALU_instance/SHIFTER_GENERIC_I/N108 ,
\ALU_instance/SHIFTER_GENERIC_I/N107 ,
\ALU_instance/SHIFTER_GENERIC_I/N106 ,
\ALU_instance/SHIFTER_GENERIC_I/N105 ,
\BOOTH_instance/add_0_root_add_53_G7/carry[5] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[6] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[7] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[8] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[9] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[10] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[11] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[12] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[13] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[14] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[15] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[16] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[17] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[18] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[19] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[20] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[21] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[22] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[23] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[24] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[25] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[26] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[27] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[28] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[29] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[30] ,
\BOOTH_instance/add_0_root_add_53_G7/carry[31] ,
\BOOTH_instance/add_1_root_add_53_G7/carry[13] ,
\BOOTH_instance/add_1_root_add_53_G7/carry[14] ,
\BOOTH_instance/add_1_root_add_53_G7/carry[15] ,
\BOOTH_instance/add_1_root_add_53_G7/carry[16] ,
\BOOTH_instance/add_1_root_add_53_G7/carry[17] ,
\BOOTH_instance/add_1_root_add_53_G7/carry[18] ,
\BOOTH_instance/add_1_root_add_53_G7/carry[19] ,
\BOOTH_instance/add_1_root_add_53_G7/carry[20] ,
\BOOTH_instance/add_1_root_add_53_G7/carry[21] ,
\BOOTH_instance/add_1_root_add_53_G7/carry[22] ,
\BOOTH_instance/add_1_root_add_53_G7/carry[23] ,
\BOOTH_instance/add_1_root_add_53_G7/carry[24] ,
\BOOTH_instance/add_1_root_add_53_G7/carry[25] ,
\BOOTH_instance/add_1_root_add_53_G7/carry[26] ,
\BOOTH_instance/add_1_root_add_53_G7/carry[27] ,
\BOOTH_instance/add_1_root_add_53_G7/carry[28] ,
\BOOTH_instance/add_1_root_add_53_G7/carry[29] ,
\BOOTH_instance/add_1_root_add_53_G7/carry[30] ,
\BOOTH_instance/add_1_root_add_53_G7/carry[31] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[9] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[10] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[11] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[12] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[13] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[14] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[15] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[16] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[17] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[18] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[19] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[20] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[21] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[22] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[23] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[24] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[25] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[26] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[27] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[28] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[29] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[30] ,
\BOOTH_instance/add_2_root_add_53_G7/carry[31] ,
\BOOTH_instance/add_3_root_add_53_G7/carry[17] ,
\BOOTH_instance/add_3_root_add_53_G7/carry[18] ,
\BOOTH_instance/add_3_root_add_53_G7/carry[19] ,
\BOOTH_instance/add_3_root_add_53_G7/carry[20] ,
\BOOTH_instance/add_3_root_add_53_G7/carry[21] ,
\BOOTH_instance/add_3_root_add_53_G7/carry[22] ,
\BOOTH_instance/add_3_root_add_53_G7/carry[23] ,
\BOOTH_instance/add_3_root_add_53_G7/carry[24] ,
\BOOTH_instance/add_3_root_add_53_G7/carry[25] ,
\BOOTH_instance/add_3_root_add_53_G7/carry[26] ,
\BOOTH_instance/add_3_root_add_53_G7/carry[27] ,
\BOOTH_instance/add_3_root_add_53_G7/carry[28] ,
\BOOTH_instance/add_3_root_add_53_G7/carry[29] ,
\BOOTH_instance/add_3_root_add_53_G7/carry[30] ,
\BOOTH_instance/add_3_root_add_53_G7/carry[31] ,
\BOOTH_instance/add_5_root_add_53_G7/carry[11] ,
\BOOTH_instance/add_5_root_add_53_G7/carry[12] ,
\BOOTH_instance/add_5_root_add_53_G7/carry[13] ,
\BOOTH_instance/add_5_root_add_53_G7/carry[14] ,
\BOOTH_instance/add_5_root_add_53_G7/carry[15] ,
\BOOTH_instance/add_5_root_add_53_G7/carry[16] ,
\BOOTH_instance/add_5_root_add_53_G7/carry[17] ,
\BOOTH_instance/add_5_root_add_53_G7/carry[18] ,
\BOOTH_instance/add_5_root_add_53_G7/carry[19] ,
\BOOTH_instance/add_5_root_add_53_G7/carry[20] ,
\BOOTH_instance/add_5_root_add_53_G7/carry[21] ,
\BOOTH_instance/add_5_root_add_53_G7/carry[22] ,
\BOOTH_instance/add_5_root_add_53_G7/carry[23] ,
\BOOTH_instance/add_5_root_add_53_G7/carry[24] ,
\BOOTH_instance/add_5_root_add_53_G7/carry[25] ,
\BOOTH_instance/add_5_root_add_53_G7/carry[26] ,
\BOOTH_instance/add_5_root_add_53_G7/carry[27] ,
\BOOTH_instance/add_5_root_add_53_G7/carry[28] ,
\BOOTH_instance/add_5_root_add_53_G7/carry[29] ,
\BOOTH_instance/add_5_root_add_53_G7/carry[30] ,
\BOOTH_instance/add_5_root_add_53_G7/carry[31] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[7] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[8] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[9] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[10] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[11] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[12] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[13] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[14] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[15] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[16] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[17] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[18] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[19] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[20] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[21] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[22] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[23] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[24] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[25] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[26] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[27] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[28] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[29] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[30] ,
\BOOTH_instance/add_6_root_add_53_G7/carry[31] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[3] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[4] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[5] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[6] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[7] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[8] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[9] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[10] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[11] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[12] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[13] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[14] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[15] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[16] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[17] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[18] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[19] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[20] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[21] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[22] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[23] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[24] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[25] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[26] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[27] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[28] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[29] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[30] ,
\BOOTH_instance/add_7_root_add_53_G7/carry[31] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/C1 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S1[0] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S1[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S1[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S1[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/C0 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S0[0] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S0[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S0[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S0[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/n2 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/C1 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S1[0] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S1[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S1[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S1[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/C0 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S0[0] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S0[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S0[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S0[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/n2 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/C1 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S1[0] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S1[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S1[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S1[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/C0 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S0[0] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S0[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S0[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S0[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/n2 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/C1 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S1[0] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S1[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S1[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S1[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/C0 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S0[0] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S0[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S0[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S0[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/n2 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/C1 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S1[0] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S1[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S1[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S1[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/C0 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S0[0] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S0[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S0[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S0[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/n2 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/C1 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S1[0] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S1[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S1[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S1[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/C0 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S0[0] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S0[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S0[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S0[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/n2 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/C1 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S1[0] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S1[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S1[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S1[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/C0 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S0[0] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S0[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S0[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S0[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/n2 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/C1 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S1[0] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S1[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S1[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S1[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/C0 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S0[0] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S0[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S0[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S0[3] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/n8 ,
\ALU_instance/SHIFTER_GENERIC_I/C88/n7 ,
\ALU_instance/SHIFTER_GENERIC_I/C88/n6 ,
\ALU_instance/SHIFTER_GENERIC_I/C88/n5 ,
\ALU_instance/SHIFTER_GENERIC_I/C88/n4 ,
\ALU_instance/SHIFTER_GENERIC_I/C88/n3 ,
\ALU_instance/SHIFTER_GENERIC_I/C88/n2 ,
\ALU_instance/SHIFTER_GENERIC_I/C88/n1 ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][0] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][1] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][2] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][3] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][4] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][5] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][6] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][7] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][8] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][9] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][10] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][11] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][12] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][13] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][14] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][15] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][16] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][17] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][18] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][19] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][20] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][21] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][22] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][23] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][24] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][25] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][26] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][27] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][28] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][29] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][30] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][31] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][0] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][1] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][2] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][3] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][4] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][5] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][6] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][7] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][8] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][9] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][10] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][11] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][12] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][13] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][14] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][15] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][16] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][17] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][18] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][19] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][20] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][21] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][22] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][23] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][24] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][25] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][26] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][27] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][28] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][29] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][30] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][31] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][0] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][1] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][2] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][3] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][4] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][5] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][6] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][7] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][8] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][9] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][10] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][11] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][12] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][13] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][14] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][15] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][16] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][17] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][18] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][19] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][20] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][21] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][22] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][23] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][24] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][25] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][26] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][27] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][28] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][29] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][30] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][31] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][0] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][1] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][2] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][3] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][4] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][5] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][6] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][7] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][8] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][9] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][10] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][11] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][12] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][13] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][14] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][15] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][16] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][17] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][18] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][19] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][20] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][21] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][22] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][23] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][24] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][25] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][26] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][27] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][28] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][29] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][30] ,
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][31] ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n179 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n178 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n177 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n176 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n175 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n174 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n172 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n170 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n169 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n168 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n167 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n166 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n165 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n163 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n162 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n159 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n156 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n155 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n153 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n151 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n150 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n149 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n148 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n146 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n145 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n144 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n143 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n141 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n140 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n139 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n138 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n137 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n133 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n132 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n131 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n130 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n129 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n128 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n126 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n125 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n124 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n122 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n121 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n120 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n119 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n118 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n117 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n116 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n115 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n114 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n113 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n112 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n110 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n109 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n108 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n107 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n105 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n104 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n103 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n102 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n100 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n99 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n98 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n97 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n96 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n95 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n94 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n93 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n92 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n91 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n90 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n89 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n88 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n87 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n86 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n85 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n84 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n83 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n82 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n81 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n80 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n79 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n77 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n76 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n75 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n74 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n72 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n71 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n70 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n69 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n68 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n67 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n66 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n65 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n64 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n63 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n62 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n61 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n60 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n59 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n58 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n57 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n56 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n55 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n54 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n53 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n51 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n50 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n49 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n48 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n47 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n46 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n45 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n44 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n43 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n42 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n41 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n40 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n39 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n38 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n37 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n36 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n35 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n34 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n33 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n32 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n31 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n30 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n29 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n28 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n27 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n25 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n24 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n23 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n22 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n21 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n20 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n19 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n18 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n17 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n16 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n15 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n14 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n13 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n12 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n11 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n10 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n9 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n8 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n7 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n6 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n5 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n4 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n3 ,
\ALU_instance/SHIFTER_GENERIC_I/C86/n2 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n163 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n162 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n161 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n160 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n159 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n158 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n157 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n156 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n155 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n153 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n152 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n151 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n150 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n149 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n148 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n147 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n146 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n145 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n144 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n143 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n142 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n139 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n138 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n134 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n132 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n130 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n128 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n127 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n124 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n123 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n122 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n120 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n119 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n118 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n117 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n114 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n113 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n111 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n107 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n104 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n103 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n102 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n101 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n100 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n99 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n98 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n97 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n96 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n95 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n94 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n93 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n92 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n91 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n90 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n89 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n87 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n86 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n84 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n81 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n80 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n79 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n78 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n77 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n76 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n75 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n74 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n73 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n72 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n70 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n68 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n67 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n66 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n65 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n64 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n63 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n61 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n60 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n58 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n57 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n56 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n55 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n54 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n53 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n50 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n47 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n46 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n45 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n43 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n42 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n40 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n39 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n38 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n37 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n36 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n35 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n34 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n33 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n32 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n31 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n30 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n29 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n28 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n27 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n26 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n25 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n24 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n23 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n22 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n21 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n20 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n19 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n18 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n17 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n16 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n15 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n14 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n13 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n12 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n11 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n10 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n9 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n8 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n7 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n6 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n5 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n4 ,
\ALU_instance/SHIFTER_GENERIC_I/C50/n2 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n163 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n162 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n161 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n160 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n159 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n158 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n157 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n156 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n155 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n152 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n151 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n150 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n149 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n148 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n147 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n146 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n145 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n144 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n143 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n142 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n141 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n140 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n138 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n135 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n134 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n131 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n130 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n129 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n128 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n127 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n125 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n124 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n121 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n118 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n117 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n115 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n114 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n112 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n111 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n110 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n109 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n108 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n107 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n106 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n105 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n104 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n103 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n102 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n101 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n100 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n99 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n98 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n97 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n96 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n94 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n93 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n92 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n91 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n90 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n89 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n88 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n87 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n86 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n85 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n84 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n83 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n82 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n81 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n80 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n79 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n78 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n77 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n76 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n75 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n74 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n73 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n71 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n69 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n68 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n67 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n66 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n65 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n62 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n61 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n59 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n58 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n57 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n56 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n55 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n54 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n53 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n52 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n48 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n47 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n46 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n45 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n43 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n42 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n41 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n40 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n39 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n38 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n37 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n36 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n35 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n34 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n33 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n32 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n31 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n30 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n29 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n28 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n27 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n26 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n25 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n24 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n23 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n22 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n21 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n20 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n19 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n18 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n17 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n16 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n15 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n14 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n13 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n12 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n11 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n10 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n9 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n8 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n7 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n6 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n5 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n4 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n3 ,
\ALU_instance/SHIFTER_GENERIC_I/C48/n2 ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA0/add_1_root_add_20_2/carry[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA0/add_1_root_add_20_2/carry[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA0/add_1_root_add_20_2/carry[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA1/add_1_root_add_20_2/carry[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA1/add_1_root_add_20_2/carry[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA1/add_1_root_add_20_2/carry[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA0/add_1_root_add_20_2/carry[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA0/add_1_root_add_20_2/carry[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA0/add_1_root_add_20_2/carry[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA1/add_1_root_add_20_2/carry[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA1/add_1_root_add_20_2/carry[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA1/add_1_root_add_20_2/carry[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA0/add_1_root_add_20_2/carry[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA0/add_1_root_add_20_2/carry[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA0/add_1_root_add_20_2/carry[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA1/add_1_root_add_20_2/carry[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA1/add_1_root_add_20_2/carry[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA1/add_1_root_add_20_2/carry[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA0/add_1_root_add_20_2/carry[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA0/add_1_root_add_20_2/carry[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA0/add_1_root_add_20_2/carry[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA1/add_1_root_add_20_2/carry[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA1/add_1_root_add_20_2/carry[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA1/add_1_root_add_20_2/carry[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA0/add_1_root_add_20_2/carry[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA0/add_1_root_add_20_2/carry[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA0/add_1_root_add_20_2/carry[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA1/add_1_root_add_20_2/carry[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA1/add_1_root_add_20_2/carry[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA1/add_1_root_add_20_2/carry[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA0/add_1_root_add_20_2/carry[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA0/add_1_root_add_20_2/carry[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA0/add_1_root_add_20_2/carry[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA1/add_1_root_add_20_2/carry[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA1/add_1_root_add_20_2/carry[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA1/add_1_root_add_20_2/carry[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA0/add_1_root_add_20_2/carry[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA0/add_1_root_add_20_2/carry[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA0/add_1_root_add_20_2/carry[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA1/add_1_root_add_20_2/carry[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA1/add_1_root_add_20_2/carry[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA1/add_1_root_add_20_2/carry[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA0/add_1_root_add_20_2/carry[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA0/add_1_root_add_20_2/carry[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA0/add_1_root_add_20_2/carry[3] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA1/add_1_root_add_20_2/carry[1] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA1/add_1_root_add_20_2/carry[2] ,
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA1/add_1_root_add_20_2/carry[3] ,
\EX_MEM_OUT_REG_instance/n34 , \EX_MEM_REGB_REG_instance/n34 ,
\ID_EX_PC_REG_instance/n34 , \ID_EX_REGA_REG_instance/n34 ,
\ID_EX_IMM16_EXT_REG_instance/n34 , n1591, n1592, n1593, n1594, n1595,
n1596, n1597, n1598, n1599, n1603, n1604, n1605, n1606, n1607, n1608,
n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616, n1620, n1621,
n1623, n1625, n1626, n1627, n1628, n1629, n1630, n1631, n1632, n1633,
n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646,
n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656,
n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666,
n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676,
n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686,
n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696,
n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1718,
n1819, n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113, n2114,
n2115, n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123, n2124,
n2125, n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133, n2134,
n2135, n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2144,
n2145, n2146, n2147, n2148, n2149, n2150, n2151, n2152, n2153, n2154,
n2155, n2156, n2157, n2158, n2159, n2160, n2161, n2162, n2163, n2164,
n2165, n2166, n2167, n2168, n2169, n2170, n2171, n2172, n2173, n2174,
n2175, n2176, n2177, n2178, n2179, n2180, n2181, n2182, n2183, n2184,
n2185, n2186, n2187, n2188, n2189, n2190, n2191, n2192, n2193;
wire [1:0] EX_ALU_SEL;
wire [5:0] EX_COMPARATOR_CW;
wire [3:1] EX_LOGIC_CW;
wire [1:0] EX_SHIFTER_CW;
wire [31:0] EX_ALU_OUT;
wire [31:0] EX_MULT_OUT;
wire [31:0] ID_IMM16_SHL2;
wire [31:0] WB_DATA_EXT_16;
wire [31:0] WB_DATA_EXT_8;
wire [31:0] IF_PC_INC;
wire [31:0] ID_PC;
wire [31:0] EX_REGA;
wire [31:0] EX_REGB;
wire [31:0] EX_IMM16_EXT;
wire [31:0] EX_PC;
wire [31:0] ID_INSTR_AFTER_CU;
wire [31:0] EX_INSTR;
wire [31:0] MEM_INSTR;
wire [31:0] WB_DATA_RAM;
wire [31:0] WB_ALU;
wire [20:0] WB_INSTR;
wire [31:0] ID_PC_SUM;
assign RF_ENABLE = 1'b1;
assign PORT_PC[1] = IF_PC_INC[1];
assign PORT_PC[0] = IF_PC_INC[0];
assign RF_DATAIN[0] = N6243;
assign RF_DATAIN[1] = N6244;
assign RF_DATAIN[2] = N6245;
assign RF_DATAIN[3] = N6246;
assign RF_DATAIN[4] = N6247;
assign RF_DATAIN[5] = N6248;
assign RF_DATAIN[6] = N6249;
assign RF_DATAIN[7] = N6250;
assign RF_DATAIN[8] = N6251;
assign RF_DATAIN[9] = N6252;
assign RF_DATAIN[10] = N6253;
assign RF_DATAIN[11] = N6254;
assign RF_DATAIN[12] = N6255;
assign RF_DATAIN[13] = N6256;
assign RF_DATAIN[14] = N6257;
assign RF_DATAIN[15] = N6258;
assign RF_DATAIN[16] = N6259;
assign RF_DATAIN[17] = N6260;
assign RF_DATAIN[18] = N6261;
assign RF_DATAIN[19] = N6262;
assign RF_DATAIN[20] = N6263;
assign RF_DATAIN[21] = N6264;
assign RF_DATAIN[22] = N6265;
assign RF_DATAIN[23] = N6266;
assign RF_DATAIN[24] = N6267;
assign RF_DATAIN[25] = N6268;
assign RF_DATAIN[26] = N6269;
assign RF_DATAIN[27] = N6270;
assign RF_DATAIN[28] = N6271;
assign RF_DATAIN[29] = N6272;
assign RF_DATAIN[30] = N6273;
TLATXL ID_HAZARD_MEM_reg ( .G(N4716), .D(N4710), .QN(n319) );
TLATXL ID_HAZARD_WB_reg ( .G(N4717), .D(N4708), .QN(n320) );
TLATXL ID_HAZARD_EX_reg ( .G(N4717), .D(N4712), .QN(n321) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[16] ( .RN(
\ID_EX_PC_REG_instance/n34 ), .D(MEM_INSTR[16]), .E(1'b1), .CK(CLOCK__L3_N19),
.Q(WB_INSTR[16]) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[17] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(MEM_INSTR[17]), .E(1'b1), .CK(CLOCK__L3_N19), .Q(WB_INSTR[17]) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[18] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(MEM_INSTR[18]), .E(1'b1), .CK(CLOCK__L3_N19), .Q(WB_INSTR[18]) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[19] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(MEM_INSTR[19]), .E(1'b1), .CK(CLOCK__L3_N19), .Q(WB_INSTR[19]) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[20] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(MEM_INSTR[20]), .E(1'b1), .CK(CLOCK__L3_N17), .Q(WB_INSTR[20]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[16] ( .RN(\PC_instance/n33 ),
.D(PORT_DATA_RAM[16]), .E(1'b1), .CK(CLOCK__L3_N10), .Q(WB_DATA_RAM[16]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[17] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(PORT_DATA_RAM[17]), .E(1'b1),
.CK(CLOCK__L3_N10), .Q(WB_DATA_RAM[17]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[18] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(PORT_DATA_RAM[18]), .E(1'b1), .CK(CLOCK__L3_N10), .Q(WB_DATA_RAM[18]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[19] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(PORT_DATA_RAM[19]), .E(1'b1), .CK(CLOCK__L3_N10), .Q(WB_DATA_RAM[19]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[20] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(PORT_DATA_RAM[20]), .E(1'b1),
.CK(CLOCK__L3_N9), .Q(WB_DATA_RAM[20]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[21] ( .RN(
\ID_EX_PC_REG_instance/n34 ), .D(PORT_DATA_RAM[21]), .E(1'b1), .CK(CLOCK__L3_N10), .Q(WB_DATA_RAM[21]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[22] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(PORT_DATA_RAM[22]), .E(1'b1), .CK(CLOCK__L3_N10), .Q(WB_DATA_RAM[22]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[23] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(PORT_DATA_RAM[23]), .E(1'b1), .CK(CLOCK__L3_N10), .Q(WB_DATA_RAM[23]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[24] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_DATA_RAM[24]), .E(1'b1), .CK(CLOCK__L3_N10), .Q(WB_DATA_RAM[24]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[25] ( .RN(\PC_instance/n33 ),
.D(PORT_DATA_RAM[25]), .E(1'b1), .CK(CLOCK__L3_N10), .Q(WB_DATA_RAM[25]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[26] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_DATA_RAM[26]), .E(1'b1), .CK(CLOCK__L3_N9), .Q(WB_DATA_RAM[26]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[27] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(PORT_DATA_RAM[27]), .E(1'b1),
.CK(CLOCK__L3_N9), .Q(WB_DATA_RAM[27]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[28] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(PORT_DATA_RAM[28]), .E(1'b1), .CK(CLOCK__L3_N9), .Q(WB_DATA_RAM[28]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[29] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(PORT_DATA_RAM[29]), .E(1'b1), .CK(CLOCK__L3_N10), .Q(WB_DATA_RAM[29]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[30] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_DATA_RAM[30]), .E(1'b1), .CK(CLOCK__L3_N10), .Q(WB_DATA_RAM[30]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[31] ( .RN(
\ID_EX_PC_REG_instance/n34 ), .D(PORT_DATA_RAM[31]), .E(1'b1), .CK(CLOCK__L3_N10), .Q(WB_DATA_RAM[31]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[0] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(PORT_DATA_RAM[0]), .E(1'b1), .CK(CLOCK__L3_N11), .Q(WB_DATA_RAM[0]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[1] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(PORT_DATA_RAM[1]), .E(1'b1), .CK(CLOCK__L3_N12), .Q(WB_DATA_RAM[1]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[2] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(PORT_DATA_RAM[2]), .E(1'b1), .CK(CLOCK__L3_N12), .Q(WB_DATA_RAM[2]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[3] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(PORT_DATA_RAM[3]), .E(1'b1), .CK(CLOCK__L3_N12), .Q(WB_DATA_RAM[3]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[4] ( .RN(
\ID_EX_PC_REG_instance/n34 ), .D(PORT_DATA_RAM[4]), .E(1'b1), .CK(CLOCK__L3_N9), .Q(WB_DATA_RAM[4]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[5] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(PORT_DATA_RAM[5]), .E(1'b1), .CK(CLOCK__L3_N12), .Q(WB_DATA_RAM[5]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[6] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(PORT_DATA_RAM[6]), .E(1'b1), .CK(CLOCK__L3_N8), .Q(WB_DATA_RAM[6]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[0] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[0]), .E(1'b1), .CK(CLOCK__L3_N6),
.Q(WB_ALU[0]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[1] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[1]), .E(1'b1), .CK(CLOCK__L3_N8),
.Q(WB_ALU[1]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[2] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[2]), .E(1'b1), .CK(CLOCK__L3_N7),
.Q(WB_ALU[2]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[3] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[3]), .E(1'b1), .CK(CLOCK__L3_N5),
.Q(WB_ALU[3]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[4] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[4]), .E(1'b1), .CK(CLOCK__L3_N0),
.Q(WB_ALU[4]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[5] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[5]), .E(1'b1), .CK(CLOCK__L3_N7),
.Q(WB_ALU[5]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[6] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[6]), .E(1'b1), .CK(CLOCK__L3_N8),
.Q(WB_ALU[6]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[7] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_DATA_RAM[7]), .E(1'b1), .CK(CLOCK__L3_N10), .Q(WB_DATA_RAM[7]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[8] ( .RN(\PC_instance/n33 ),
.D(PORT_DATA_RAM[8]), .E(1'b1), .CK(CLOCK__L3_N9), .Q(WB_DATA_RAM[8]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[9] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(PORT_DATA_RAM[9]), .E(1'b1), .CK(CLOCK__L3_N11), .Q(WB_DATA_RAM[9]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[10] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(PORT_DATA_RAM[10]), .E(1'b1), .CK(CLOCK__L3_N11), .Q(WB_DATA_RAM[10]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[11] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(PORT_DATA_RAM[11]), .E(1'b1), .CK(CLOCK__L3_N11), .Q(WB_DATA_RAM[11]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[12] ( .RN(
\ID_EX_PC_REG_instance/n34 ), .D(PORT_DATA_RAM[12]), .E(1'b1), .CK(CLOCK__L3_N0), .Q(WB_DATA_RAM[12]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[13] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(PORT_DATA_RAM[13]), .E(1'b1), .CK(CLOCK__L3_N8), .Q(WB_DATA_RAM[13]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[14] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(PORT_DATA_RAM[14]), .E(1'b1), .CK(CLOCK__L3_N8), .Q(WB_DATA_RAM[14]) );
EDFFTRXL \MEM_WB_DATA_RAM_REG_instance/Q_reg[15] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_DATA_RAM[15]), .E(1'b1), .CK(CLOCK__L3_N10), .Q(WB_DATA_RAM[15]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[7] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[7]), .E(1'b1), .CK(CLOCK__L3_N0),
.Q(WB_ALU[7]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[8] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[8]), .E(1'b1), .CK(CLOCK__L3_N1),
.Q(WB_ALU[8]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[9] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[9]), .E(1'b1), .CK(CLOCK__L3_N8),
.Q(WB_ALU[9]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[10] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[10]), .E(1'b1), .CK(CLOCK__L3_N7),
.Q(WB_ALU[10]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[11] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[11]), .E(1'b1), .CK(CLOCK__L3_N8),
.Q(WB_ALU[11]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[12] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[12]), .E(1'b1), .CK(CLOCK__L3_N0),
.Q(WB_ALU[12]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[13] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[13]), .E(1'b1), .CK(CLOCK__L3_N8),
.Q(WB_ALU[13]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[14] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[14]), .E(1'b1), .CK(CLOCK__L3_N12),
.Q(WB_ALU[14]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[15] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[15]), .E(1'b1), .CK(CLOCK__L3_N0),
.Q(WB_ALU[15]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[16] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[16]), .E(1'b1), .CK(CLOCK__L3_N5),
.Q(WB_ALU[16]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[17] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[17]), .E(1'b1), .CK(CLOCK__L3_N1),
.Q(WB_ALU[17]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[18] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[18]), .E(1'b1), .CK(CLOCK__L3_N1),
.Q(WB_ALU[18]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[19] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[19]), .E(1'b1), .CK(CLOCK__L3_N5),
.Q(WB_ALU[19]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[20] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[20]), .E(1'b1), .CK(CLOCK__L3_N5),
.Q(WB_ALU[20]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[21] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[21]), .E(1'b1), .CK(CLOCK__L3_N5),
.Q(WB_ALU[21]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[22] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[22]), .E(1'b1), .CK(CLOCK__L3_N8),
.Q(WB_ALU[22]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[23] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[23]), .E(1'b1), .CK(CLOCK__L3_N0),
.Q(WB_ALU[23]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[24] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[24]), .E(1'b1), .CK(CLOCK__L3_N0),
.Q(WB_ALU[24]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[25] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[25]), .E(1'b1), .CK(CLOCK__L3_N5),
.Q(WB_ALU[25]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[26] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[26]), .E(1'b1), .CK(CLOCK__L3_N1),
.Q(WB_ALU[26]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[27] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[27]), .E(1'b1), .CK(CLOCK__L3_N5),
.Q(WB_ALU[27]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[28] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[28]), .E(1'b1), .CK(CLOCK__L3_N6),
.Q(WB_ALU[28]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[29] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[29]), .E(1'b1), .CK(CLOCK__L3_N6),
.Q(WB_ALU[29]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[30] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[30]), .E(1'b1), .CK(CLOCK__L3_N8),
.Q(WB_ALU[30]) );
EDFFTRXL \MEM_WB_ALU_REG_instance/Q_reg[31] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_ALU[31]), .E(1'b1), .CK(CLOCK__L3_N0),
.Q(WB_ALU[31]) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[4] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(MEM_INSTR[4]), .E(1'b1), .CK(CLOCK__L3_N16),
.Q(WB_INSTR[4]) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[5] ( .RN(\PC_instance/n33 ), .D(
MEM_INSTR[5]), .E(1'b1), .CK(CLOCK__L3_N16), .Q(WB_INSTR[5]) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[6] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(MEM_INSTR[6]), .E(1'b1), .CK(CLOCK__L3_N13), .Q(WB_INSTR[6]) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[9] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(MEM_INSTR[9]), .E(1'b1), .CK(CLOCK__L3_N15),
.Q(WB_INSTR[9]) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[8] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(MEM_INSTR[8]), .E(1'b1), .CK(CLOCK__L3_N15),
.Q(WB_INSTR[8]) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[10] ( .RN(
\ID_EX_PC_REG_instance/n34 ), .D(MEM_INSTR[10]), .E(1'b1), .CK(CLOCK__L3_N15),
.Q(WB_INSTR[10]) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[7] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(MEM_INSTR[7]), .E(1'b1), .CK(CLOCK__L3_N15),
.Q(WB_INSTR[7]) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[0] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(MEM_INSTR[0]), .E(1'b1), .CK(CLOCK__L3_N16),
.Q(WB_INSTR[0]) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[11] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(MEM_INSTR[11]), .E(1'b1), .CK(CLOCK__L3_N19), .Q(WB_INSTR[11]) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[12] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(MEM_INSTR[12]), .E(1'b1), .CK(CLOCK__L3_N17), .Q(WB_INSTR[12]) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[13] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(MEM_INSTR[13]), .E(1'b1), .CK(CLOCK__L3_N17), .Q(WB_INSTR[13]) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[14] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(MEM_INSTR[14]), .E(1'b1), .CK(CLOCK__L3_N19), .Q(WB_INSTR[14]) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[15] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(MEM_INSTR[15]), .E(1'b1), .CK(CLOCK__L3_N19), .Q(WB_INSTR[15]) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[1] ( .RN(
\ID_EX_PC_REG_instance/n34 ), .D(MEM_INSTR[1]), .E(1'b1), .CK(CLOCK__L3_N16),
.Q(WB_INSTR[1]) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[3] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(MEM_INSTR[3]), .E(1'b1), .CK(CLOCK__L3_N16),
.Q(WB_INSTR[3]) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[2] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(MEM_INSTR[2]), .E(1'b1), .CK(CLOCK__L3_N16), .Q(WB_INSTR[2]) );
EDFFTRXL \PC_instance/Q_reg[0] ( .RN(\PC_instance/n33 ), .D(N730), .E(n2154), .CK(n1625), .Q(IF_PC_INC[0]) );
EDFFTRXL \PC_instance/Q_reg[1] ( .RN(\PC_instance/n33 ), .D(N731), .E(n2154), .CK(n1625), .Q(IF_PC_INC[1]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[0] ( .RN(\PC_instance/n33 ), .D(
IF_PC_INC[0]), .E(n2153), .CK(n1625), .Q(ID_PC_SUM[0]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[1] ( .RN(\ID_EX_PC_REG_instance/n34 ),
.D(IF_PC_INC[1]), .E(n2153), .CK(n1625), .Q(ID_PC_SUM[1]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[14] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[14]), .E(1'b1),
.CK(CLOCK__L3_N13), .Q(EX_INSTR[14]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[11] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[11]), .E(1'b1),
.CK(CLOCK__L3_N13), .Q(EX_INSTR[11]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[16] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[16]), .E(1'b1),
.CK(CLOCK__L3_N19), .Q(EX_INSTR[16]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[14] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_INSTR[14]), .E(1'b1), .CK(CLOCK__L3_N19), .Q(MEM_INSTR[14]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[11] ( .RN(
\ID_EX_PC_REG_instance/n34 ), .D(EX_INSTR[11]), .E(1'b1), .CK(CLOCK__L3_N19),
.Q(MEM_INSTR[11]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[31] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(PORT_PC[31]), .E(n2152), .CK(n1625), .Q(ID_PC[31]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[19] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[19]), .E(1'b1),
.CK(CLOCK__L3_N19), .Q(EX_INSTR[19]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[24] ( .RN(\PC_instance/n33 ), .D(
PORT_PC[24]), .E(n2153), .CK(n1625), .Q(ID_PC[24]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[25] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(PORT_PC[25]), .E(n2153), .CK(n1625), .Q(ID_PC[25]) );
EDFFTRXL \PC_instance/Q_reg[31] ( .RN(\PC_instance/n33 ), .D(N761), .E(
n2152), .CK(n1625), .Q(PORT_PC[31]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[19] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(EX_INSTR[19]), .E(1'b1), .CK(CLOCK__L3_N19),
.Q(MEM_INSTR[19]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[16] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(EX_INSTR[16]), .E(1'b1), .CK(CLOCK__L3_N19),
.Q(MEM_INSTR[16]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[12] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[12]), .E(1'b1),
.CK(CLOCK__L3_N13), .Q(EX_INSTR[12]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[12] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(EX_INSTR[12]), .E(1'b1), .CK(CLOCK__L3_N17),
.Q(MEM_INSTR[12]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[15] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[15]), .E(1'b1),
.CK(CLOCK__L3_N13), .Q(EX_INSTR[15]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[17] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[17]), .E(1'b1),
.CK(CLOCK__L3_N19), .Q(EX_INSTR[17]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[13] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[13]), .E(1'b1),
.CK(CLOCK__L3_N13), .Q(EX_INSTR[13]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[18] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[18]), .E(1'b1),
.CK(CLOCK__L3_N17), .Q(EX_INSTR[18]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[15] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(EX_INSTR[15]), .E(1'b1), .CK(CLOCK__L3_N17),
.Q(MEM_INSTR[15]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[13] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(EX_INSTR[13]), .E(1'b1), .CK(CLOCK__L3_N17), .Q(MEM_INSTR[13]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[26] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(PORT_PC[26]), .E(n2153), .CK(n1625), .Q(ID_PC[26]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[27] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_PC[27]), .E(n2152), .CK(n1625),
.Q(ID_PC[27]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[28] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(PORT_PC[28]), .E(n2152), .CK(n1625),
.Q(ID_PC[28]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[29] ( .RN(\PC_instance/n33 ), .D(
PORT_PC[29]), .E(n2152), .CK(n1625), .Q(ID_PC[29]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[30] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(PORT_PC[30]), .E(n2152), .CK(n1625), .Q(ID_PC[30]) );
EDFFTRXL \PC_instance/Q_reg[22] ( .RN(\PC_instance/n33 ), .D(N752), .E(
n2154), .CK(n1625), .Q(PORT_PC[22]) );
EDFFTRXL \PC_instance/Q_reg[23] ( .RN(\PC_instance/n33 ), .D(N753), .E(
n2154), .CK(n1625), .Q(PORT_PC[23]) );
EDFFTRXL \PC_instance/Q_reg[24] ( .RN(\PC_instance/n33 ), .D(N754), .E(
n2154), .CK(n1625), .Q(PORT_PC[24]) );
EDFFTRXL \PC_instance/Q_reg[25] ( .RN(\PC_instance/n33 ), .D(N755), .E(
n2154), .CK(n1625), .Q(PORT_PC[25]) );
EDFFTRXL \PC_instance/Q_reg[26] ( .RN(\PC_instance/n33 ), .D(N756), .E(
n2154), .CK(n1625), .Q(PORT_PC[26]) );
EDFFTRXL \PC_instance/Q_reg[27] ( .RN(\PC_instance/n33 ), .D(N757), .E(
n2154), .CK(n1625), .Q(PORT_PC[27]) );
EDFFTRXL \PC_instance/Q_reg[28] ( .RN(\PC_instance/n33 ), .D(N758), .E(
n2154), .CK(n1625), .Q(PORT_PC[28]) );
EDFFTRXL \PC_instance/Q_reg[29] ( .RN(\PC_instance/n33 ), .D(N759), .E(
n2154), .CK(n1625), .Q(PORT_PC[29]) );
EDFFTRXL \PC_instance/Q_reg[30] ( .RN(\PC_instance/n33 ), .D(N760), .E(
n2154), .CK(n1625), .Q(PORT_PC[30]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[20] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[20]), .E(1'b1),
.CK(CLOCK__L3_N19), .Q(EX_INSTR[20]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[20] ( .RN(\PC_instance/n33 ), .D(
EX_INSTR[20]), .E(1'b1), .CK(CLOCK__L3_N17), .Q(MEM_INSTR[20]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[17] ( .RN(\PC_instance/n33 ), .D(
EX_INSTR[17]), .E(1'b1), .CK(CLOCK__L3_N19), .Q(MEM_INSTR[17]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[18] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(EX_INSTR[18]), .E(1'b1), .CK(CLOCK__L3_N19), .Q(MEM_INSTR[18]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[28] ( .RN(\PC_instance/n33 ), .D(
EX_INSTR[28]), .E(1'b1), .CK(CLOCK__L3_N15), .Q(MEM_INSTR[28]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[30] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(EX_INSTR[30]), .E(1'b1), .CK(CLOCK__L3_N17),
.Q(MEM_INSTR[30]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[21] ( .RN(\PC_instance/n33 ), .D(
N785), .E(n2153), .CK(n1625), .Q(RF_ADD_RD1[0]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[26] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_INSTR[26]), .E(1'b1), .CK(CLOCK__L3_N13), .Q(MEM_INSTR[26]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[16] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[16]), .E(1'b1), .CK(CLOCK__L3_N14),
.Q(EX_REGA[16]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[17] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[17]), .E(1'b1), .CK(CLOCK__L3_N7),
.Q(EX_REGA[17]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[18] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[18]), .E(1'b1), .CK(CLOCK__L3_N7),
.Q(EX_REGA[18]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[19] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[19]), .E(1'b1), .CK(CLOCK__L3_N7),
.Q(EX_REGA[19]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[20] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[20]), .E(1'b1), .CK(CLOCK__L3_N7),
.Q(EX_REGA[20]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[21] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[21]), .E(1'b1), .CK(CLOCK__L3_N7),
.Q(EX_REGA[21]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[22] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[22]), .E(1'b1), .CK(CLOCK__L3_N7),
.Q(EX_REGA[22]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[23] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[23]), .E(1'b1), .CK(CLOCK__L3_N7),
.Q(EX_REGA[23]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[24] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[24]), .E(1'b1), .CK(CLOCK__L3_N14),
.Q(EX_REGA[24]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[25] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[25]), .E(1'b1), .CK(CLOCK__L3_N14),
.Q(EX_REGA[25]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[26] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[26]), .E(1'b1), .CK(CLOCK__L3_N14),
.Q(EX_REGA[26]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[27] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[27]), .E(1'b1), .CK(CLOCK__L3_N7),
.Q(EX_REGA[27]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[28] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[28]), .E(1'b1), .CK(CLOCK__L3_N6),
.Q(EX_REGA[28]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[29] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[29]), .E(1'b1), .CK(CLOCK__L3_N4),
.Q(EX_REGA[29]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[30] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[30]), .E(1'b1), .CK(CLOCK__L3_N0),
.Q(EX_REGA[30]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[31] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[31]), .E(1'b1), .CK(CLOCK__L3_N4),
.Q(EX_REGA[31]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[16] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(ID_PC[16]), .E(1'b1), .CK(CLOCK__L3_N14), .Q(EX_PC[16]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[17] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(ID_PC[17]), .E(1'b1), .CK(CLOCK__L3_N14), .Q(EX_PC[17]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[18] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(ID_PC[18]), .E(1'b1), .CK(CLOCK__L3_N14), .Q(EX_PC[18]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[19] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(ID_PC[19]), .E(1'b1), .CK(CLOCK__L3_N14), .Q(EX_PC[19]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[20] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(ID_PC[20]), .E(1'b1), .CK(CLOCK__L3_N14), .Q(EX_PC[20]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[21] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(ID_PC[21]), .E(1'b1), .CK(CLOCK__L3_N18), .Q(EX_PC[21]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[22] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(ID_PC[22]), .E(1'b1), .CK(CLOCK__L3_N14), .Q(EX_PC[22]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[23] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(ID_PC[23]), .E(1'b1), .CK(CLOCK__L3_N14), .Q(EX_PC[23]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[24] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(ID_PC[24]), .E(1'b1), .CK(CLOCK__L3_N13), .Q(EX_PC[24]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[25] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(ID_PC[25]), .E(1'b1), .CK(CLOCK__L3_N14), .Q(EX_PC[25]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[26] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(ID_PC[26]), .E(1'b1), .CK(CLOCK__L3_N18), .Q(EX_PC[26]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[27] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(ID_PC[27]), .E(1'b1), .CK(CLOCK__L3_N6), .Q(EX_PC[27]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[28] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(ID_PC[28]), .E(1'b1), .CK(CLOCK__L3_N6), .Q(EX_PC[28]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[29] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(ID_PC[29]), .E(1'b1), .CK(CLOCK__L3_N5), .Q(EX_PC[29]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[30] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(ID_PC[30]), .E(1'b1), .CK(CLOCK__L3_N5), .Q(EX_PC[30]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[31] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(ID_PC[31]), .E(1'b1), .CK(CLOCK__L3_N5), .Q(EX_PC[31]) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[16] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(\ID_IMM16_EXT[31] ), .E(1'b1),
.CK(CLOCK__L3_N6), .Q(EX_IMM16_EXT[16]), .QN(n1673) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[17] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(\ID_IMM16_EXT[31] ), .E(1'b1),
.CK(CLOCK__L3_N6), .Q(EX_IMM16_EXT[17]), .QN(n1672) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[18] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(\ID_IMM16_EXT[31] ), .E(1'b1),
.CK(CLOCK__L3_N3), .Q(EX_IMM16_EXT[18]), .QN(n1671) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[19] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(\ID_IMM16_EXT[31] ), .E(1'b1),
.CK(CLOCK__L3_N2), .Q(EX_IMM16_EXT[19]), .QN(n1670) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[20] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(\ID_IMM16_EXT[31] ), .E(1'b1),
.CK(CLOCK__L3_N2), .Q(EX_IMM16_EXT[20]), .QN(n1669) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[21] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(\ID_IMM16_EXT[31] ), .E(1'b1),
.CK(CLOCK__L3_N2), .Q(EX_IMM16_EXT[21]), .QN(n1668) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[22] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(\ID_IMM16_EXT[31] ), .E(1'b1),
.CK(CLOCK__L3_N2), .Q(EX_IMM16_EXT[22]) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[23] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(\ID_IMM16_EXT[31] ), .E(1'b1),
.CK(CLOCK__L3_N2), .Q(EX_IMM16_EXT[23]) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[24] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(\ID_IMM16_EXT[31] ), .E(1'b1),
.CK(CLOCK__L3_N2), .Q(EX_IMM16_EXT[24]) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[25] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(\ID_IMM16_EXT[31] ), .E(1'b1),
.CK(CLOCK__L3_N2), .Q(EX_IMM16_EXT[25]) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[26] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(\ID_IMM16_EXT[31] ), .E(1'b1),
.CK(CLOCK__L3_N2), .Q(EX_IMM16_EXT[26]) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[27] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(\ID_IMM16_EXT[31] ), .E(1'b1),
.CK(CLOCK__L3_N2), .Q(EX_IMM16_EXT[27]) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[28] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(\ID_IMM16_EXT[31] ), .E(1'b1),
.CK(CLOCK__L3_N6), .Q(EX_IMM16_EXT[28]) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[29] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(\ID_IMM16_EXT[31] ), .E(1'b1),
.CK(CLOCK__L3_N3), .Q(EX_IMM16_EXT[29]) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[30] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(\ID_IMM16_EXT[31] ), .E(1'b1),
.CK(CLOCK__L3_N18), .Q(EX_IMM16_EXT[30]) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[31] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(\ID_IMM16_EXT[31] ), .E(1'b1),
.CK(CLOCK__L3_N3), .Q(EX_IMM16_EXT[31]), .QN(n1690) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[16] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[16]), .E(1'b1), .CK(CLOCK__L3_N9),
.Q(EX_REGB[16]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[17] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[17]), .E(1'b1), .CK(CLOCK__L3_N12),
.Q(EX_REGB[17]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[18] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[18]), .E(1'b1), .CK(CLOCK__L3_N1),
.Q(EX_REGB[18]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[19] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[19]), .E(1'b1), .CK(CLOCK__L3_N1),
.Q(EX_REGB[19]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[20] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[20]), .E(1'b1), .CK(CLOCK__L3_N9),
.Q(EX_REGB[20]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[21] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[21]), .E(1'b1), .CK(CLOCK__L3_N12),
.Q(EX_REGB[21]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[22] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[22]), .E(1'b1), .CK(CLOCK__L3_N9),
.Q(EX_REGB[22]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[23] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[23]), .E(1'b1), .CK(CLOCK__L3_N0),
.Q(EX_REGB[23]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[24] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[24]), .E(1'b1), .CK(CLOCK__L3_N11),
.Q(EX_REGB[24]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[25] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[25]), .E(1'b1), .CK(CLOCK__L3_N11),
.Q(EX_REGB[25]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[26] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[26]), .E(1'b1), .CK(CLOCK__L3_N11),
.Q(EX_REGB[26]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[27] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[27]), .E(1'b1), .CK(CLOCK__L3_N1),
.Q(EX_REGB[27]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[28] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[28]), .E(1'b1), .CK(CLOCK__L3_N11),
.Q(EX_REGB[28]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[29] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[29]), .E(1'b1), .CK(CLOCK__L3_N11),
.Q(EX_REGB[29]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[30] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[30]), .E(1'b1), .CK(CLOCK__L3_N9),
.Q(EX_REGB[30]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[31] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[31]), .E(1'b1), .CK(CLOCK__L3_N11),
.Q(EX_REGB[31]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[9] ( .RN(\ID_EX_PC_REG_instance/n34 ),
.D(PORT_PC[9]), .E(n2152), .CK(n1625), .Q(ID_PC[9]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[10] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(PORT_PC[10]), .E(n2152), .CK(n1625), .Q(ID_PC[10]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[11] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(PORT_PC[11]), .E(n2152), .CK(n1625),
.Q(ID_PC[11]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[12] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(PORT_PC[12]), .E(n2152), .CK(n1625),
.Q(ID_PC[12]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[13] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(PORT_PC[13]), .E(n2152), .CK(
n1625), .Q(ID_PC[13]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[14] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_PC[14]), .E(n2152), .CK(n1625),
.Q(ID_PC[14]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[15] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(PORT_PC[15]), .E(n2152), .CK(n1625),
.Q(ID_PC[15]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[16] ( .RN(\PC_instance/n33 ), .D(
PORT_PC[16]), .E(n2152), .CK(n1625), .Q(ID_PC[16]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[17] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(PORT_PC[17]), .E(n2152), .CK(n1625), .Q(ID_PC[17]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[18] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(PORT_PC[18]), .E(n2152), .CK(n1625), .Q(ID_PC[18]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[19] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(PORT_PC[19]), .E(n2152), .CK(n1625),
.Q(ID_PC[19]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[20] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(PORT_PC[20]), .E(n2152), .CK(n1625),
.Q(ID_PC[20]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[21] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(PORT_PC[21]), .E(n2152), .CK(
n1625), .Q(ID_PC[21]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[22] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(PORT_PC[22]), .E(n2153), .CK(n1625),
.Q(ID_PC[22]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[23] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(PORT_PC[23]), .E(n2153), .CK(n1625),
.Q(ID_PC[23]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[15] ( .RN(\PC_instance/n33 ), .D(
N779), .E(n2153), .CK(n1625), .Q(ID_IMM16_SHL2[31]) );
EDFFTRXL \PC_instance/Q_reg[3] ( .RN(\PC_instance/n33 ), .D(N733), .E(n2153), .CK(n1625), .Q(PORT_PC[3]) );
EDFFTRXL \PC_instance/Q_reg[4] ( .RN(\PC_instance/n33 ), .D(N734), .E(n2154), .CK(n1625), .Q(PORT_PC[4]) );
EDFFTRXL \PC_instance/Q_reg[6] ( .RN(\PC_instance/n33 ), .D(N736), .E(n2154), .CK(n1625), .Q(PORT_PC[6]) );
EDFFTRXL \PC_instance/Q_reg[7] ( .RN(\PC_instance/n33 ), .D(N737), .E(n2154), .CK(n1625), .Q(PORT_PC[7]) );
EDFFTRXL \PC_instance/Q_reg[8] ( .RN(\PC_instance/n33 ), .D(N738), .E(n2154), .CK(n1625), .Q(PORT_PC[8]) );
EDFFTRXL \PC_instance/Q_reg[9] ( .RN(\PC_instance/n33 ), .D(N739), .E(n2154), .CK(n1625), .Q(PORT_PC[9]) );
EDFFTRXL \PC_instance/Q_reg[10] ( .RN(\PC_instance/n33 ), .D(N740), .E(
n2154), .CK(n1625), .Q(PORT_PC[10]) );
EDFFTRXL \PC_instance/Q_reg[11] ( .RN(\PC_instance/n33 ), .D(N741), .E(
n2154), .CK(n1625), .Q(PORT_PC[11]) );
EDFFTRXL \PC_instance/Q_reg[12] ( .RN(\PC_instance/n33 ), .D(N742), .E(
n2154), .CK(n1625), .Q(PORT_PC[12]) );
EDFFTRXL \PC_instance/Q_reg[13] ( .RN(\PC_instance/n33 ), .D(N743), .E(
n2154), .CK(n1625), .Q(PORT_PC[13]) );
EDFFTRXL \PC_instance/Q_reg[14] ( .RN(\PC_instance/n33 ), .D(N744), .E(
n2154), .CK(n1625), .Q(PORT_PC[14]) );
EDFFTRXL \PC_instance/Q_reg[15] ( .RN(\PC_instance/n33 ), .D(N745), .E(
n2154), .CK(n1625), .Q(PORT_PC[15]) );
EDFFTRXL \PC_instance/Q_reg[16] ( .RN(\PC_instance/n33 ), .D(N746), .E(
n2154), .CK(n1625), .Q(PORT_PC[16]) );
EDFFTRXL \PC_instance/Q_reg[17] ( .RN(\PC_instance/n33 ), .D(N747), .E(
n2154), .CK(n1625), .Q(PORT_PC[17]) );
EDFFTRXL \PC_instance/Q_reg[18] ( .RN(\PC_instance/n33 ), .D(N748), .E(
n2154), .CK(n1625), .Q(PORT_PC[18]) );
EDFFTRXL \PC_instance/Q_reg[19] ( .RN(\PC_instance/n33 ), .D(N749), .E(
n2154), .CK(n1625), .Q(PORT_PC[19]) );
EDFFTRXL \PC_instance/Q_reg[20] ( .RN(\PC_instance/n33 ), .D(N750), .E(
n2154), .CK(n1625), .Q(PORT_PC[20]) );
EDFFTRXL \PC_instance/Q_reg[21] ( .RN(\PC_instance/n33 ), .D(N751), .E(
n2154), .CK(n1625), .Q(PORT_PC[21]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[11] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(N775), .E(n2153), .CK(n1625), .Q(
ID_IMM16_SHL2[13]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[12] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(N776), .E(n2153), .CK(n1625), .Q(
ID_IMM16_SHL2[14]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[13] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(N777), .E(n2153), .CK(n1625),
.Q(ID_IMM16_SHL2[15]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[14] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(N778), .E(n2153), .CK(n1625), .Q(
ID_IMM16_SHL2[16]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[7] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[7]), .E(1'b1), .CK(CLOCK__L3_N4),
.Q(EX_REGA[7]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[8] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[8]), .E(1'b1), .CK(CLOCK__L3_N4),
.Q(EX_REGA[8]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[9] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[9]), .E(1'b1), .CK(CLOCK__L3_N4),
.Q(EX_REGA[9]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[10] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[10]), .E(1'b1), .CK(CLOCK__L3_N4),
.Q(EX_REGA[10]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[11] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[11]), .E(1'b1), .CK(CLOCK__L3_N4),
.Q(EX_REGA[11]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[12] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[12]), .E(1'b1), .CK(CLOCK__L3_N4),
.Q(EX_REGA[12]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[13] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[13]), .E(1'b1), .CK(CLOCK__L3_N14),
.Q(EX_REGA[13]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[14] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[14]), .E(1'b1), .CK(CLOCK__L3_N7),
.Q(EX_REGA[14]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[15] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[15]), .E(1'b1), .CK(CLOCK__L3_N14),
.Q(EX_REGA[15]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[7] ( .RN(\ID_EX_PC_REG_instance/n34 ),
.D(ID_PC[7]), .E(1'b1), .CK(CLOCK__L3_N2), .Q(EX_PC[7]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[8] ( .RN(\ID_EX_PC_REG_instance/n34 ),
.D(ID_PC[8]), .E(1'b1), .CK(CLOCK__L3_N2), .Q(EX_PC[8]), .QN(n1663) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[9] ( .RN(\ID_EX_PC_REG_instance/n34 ),
.D(ID_PC[9]), .E(1'b1), .CK(CLOCK__L3_N2), .Q(EX_PC[9]), .QN(n1664) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[10] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(ID_PC[10]), .E(1'b1), .CK(CLOCK__L3_N2), .Q(EX_PC[10]), .QN(n1647) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[11] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(ID_PC[11]), .E(1'b1), .CK(CLOCK__L3_N2), .Q(EX_PC[11]), .QN(n1665) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[12] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(ID_PC[12]), .E(1'b1), .CK(CLOCK__L3_N3), .Q(EX_PC[12]), .QN(n1666) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[13] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(ID_PC[13]), .E(1'b1), .CK(CLOCK__L3_N18), .Q(EX_PC[13]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[14] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(ID_PC[14]), .E(1'b1), .CK(CLOCK__L3_N14), .Q(EX_PC[14]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[15] ( .RN(\ID_EX_PC_REG_instance/n34 ), .D(ID_PC[15]), .E(1'b1), .CK(CLOCK__L3_N18), .Q(EX_PC[15]) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[4] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(ID_IMM16_SHL2[6]), .E(1'b1),
.CK(CLOCK__L3_N3), .Q(EX_IMM16_EXT[4]), .QN(n1661) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[5] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(ID_IMM16_SHL2[7]), .E(1'b1),
.CK(CLOCK__L3_N3), .Q(EX_IMM16_EXT[5]), .QN(n1655) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[6] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(ID_IMM16_SHL2[8]), .E(1'b1),
.CK(CLOCK__L3_N3), .Q(EX_IMM16_EXT[6]), .QN(n1650) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[7] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(ID_IMM16_SHL2[9]), .E(1'b1),
.CK(CLOCK__L3_N18), .Q(EX_IMM16_EXT[7]), .QN(n1656) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[8] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(ID_IMM16_SHL2[10]), .E(1'b1),
.CK(CLOCK__L3_N18), .Q(EX_IMM16_EXT[8]), .QN(n1652) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[9] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(ID_IMM16_SHL2[11]), .E(1'b1),
.CK(CLOCK__L3_N18), .Q(EX_IMM16_EXT[9]), .QN(n1654) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[10] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(ID_IMM16_SHL2[12]), .E(1'b1),
.CK(CLOCK__L3_N18), .Q(EX_IMM16_EXT[10]), .QN(n1653) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[11] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(ID_IMM16_SHL2[13]), .E(1'b1),
.CK(CLOCK__L3_N3), .Q(EX_IMM16_EXT[11]), .QN(n1646) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[12] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(ID_IMM16_SHL2[14]), .E(1'b1),
.CK(CLOCK__L3_N6), .Q(EX_IMM16_EXT[12]), .QN(n1651) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[13] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(ID_IMM16_SHL2[15]), .E(1'b1),
.CK(CLOCK__L3_N18), .Q(EX_IMM16_EXT[13]), .QN(n1658) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[14] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(ID_IMM16_SHL2[16]), .E(1'b1),
.CK(CLOCK__L3_N18), .Q(EX_IMM16_EXT[14]), .QN(n1649) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[15] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(n2106), .E(1'b1), .CK(CLOCK__L3_N6),
.Q(EX_IMM16_EXT[15]), .QN(n1657) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[4] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[4]), .E(1'b1), .CK(CLOCK__L3_N12),
.Q(EX_REGB[4]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[5] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[5]), .E(1'b1), .CK(CLOCK__L3_N0),
.Q(EX_REGB[5]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[6] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[6]), .E(1'b1), .CK(CLOCK__L3_N0),
.Q(EX_REGB[6]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[7] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[7]), .E(1'b1), .CK(CLOCK__L3_N12),
.Q(EX_REGB[7]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[8] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[8]), .E(1'b1), .CK(CLOCK__L3_N7),
.Q(EX_REGB[8]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[9] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[9]), .E(1'b1), .CK(CLOCK__L3_N12),
.Q(EX_REGB[9]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[10] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[10]), .E(1'b1), .CK(CLOCK__L3_N12),
.Q(EX_REGB[10]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[11] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[11]), .E(1'b1), .CK(CLOCK__L3_N1),
.Q(EX_REGB[11]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[12] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[12]), .E(1'b1), .CK(CLOCK__L3_N1),
.Q(EX_REGB[12]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[13] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[13]), .E(1'b1), .CK(CLOCK__L3_N9),
.Q(EX_REGB[13]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[14] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[14]), .E(1'b1), .CK(CLOCK__L3_N8),
.Q(EX_REGB[14]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[15] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[15]), .E(1'b1), .CK(CLOCK__L3_N10),
.Q(EX_REGB[15]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[5] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[5]), .E(1'b1), .CK(CLOCK__L3_N4),
.Q(EX_REGA[5]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[6] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[6]), .E(1'b1), .CK(CLOCK__L3_N4),
.Q(EX_REGA[6]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[5] ( .RN(\ID_EX_PC_REG_instance/n34 ),
.D(ID_PC[5]), .E(1'b1), .CK(CLOCK__L3_N3), .Q(EX_PC[5]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[6] ( .RN(\ID_EX_PC_REG_instance/n34 ),
.D(ID_PC[6]), .E(1'b1), .CK(CLOCK__L3_N3), .Q(EX_PC[6]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[9] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[9]), .E(1'b1),
.CK(CLOCK__L3_N15), .Q(EX_INSTR[9]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[8] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[8]), .E(1'b1),
.CK(CLOCK__L3_N15), .Q(EX_INSTR[8]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[7] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[7]), .E(1'b1),
.CK(CLOCK__L3_N15), .Q(EX_INSTR[7]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[3] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(PORT_PC[3]), .E(n2152), .CK(n1625),
.Q(ID_PC[3]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[4] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(PORT_PC[4]), .E(n2152), .CK(n1625),
.Q(ID_PC[4]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[5] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(PORT_PC[5]), .E(n2152), .CK(
n1625), .Q(ID_PC[5]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[6] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(PORT_PC[6]), .E(n2152), .CK(n1625),
.Q(ID_PC[6]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[7] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(PORT_PC[7]), .E(n2152), .CK(n1625),
.Q(ID_PC[7]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[8] ( .RN(\PC_instance/n33 ), .D(
PORT_PC[8]), .E(n2152), .CK(n1625), .Q(ID_PC[8]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[10] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[10]), .E(1'b1),
.CK(CLOCK__L3_N18), .Q(EX_INSTR[10]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[6] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[6]), .E(1'b1),
.CK(CLOCK__L3_N15), .Q(EX_INSTR[6]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[4] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[4]), .E(1'b1),
.CK(CLOCK__L3_N16), .Q(EX_INSTR[4]) );
EDFFTRXL \IF_ID_PC_REG_instance/Q_reg[2] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(PORT_PC[2]), .E(n2153), .CK(n1625),
.Q(ID_PC[2]) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[3] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(ID_IMM16_SHL2[5]), .E(1'b1),
.CK(CLOCK__L3_N3), .Q(EX_IMM16_EXT[3]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[2] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[2]), .E(1'b1), .CK(CLOCK__L3_N0),
.Q(EX_REGA[2]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[3] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[3]), .E(1'b1), .CK(CLOCK__L3_N4),
.Q(EX_REGA[3]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[4] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[4]), .E(1'b1), .CK(CLOCK__L3_N4),
.Q(EX_REGA[4]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[2] ( .RN(\ID_EX_PC_REG_instance/n34 ),
.D(ID_PC[2]), .E(1'b1), .CK(CLOCK__L3_N3), .Q(EX_PC[2]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[3] ( .RN(\ID_EX_PC_REG_instance/n34 ),
.D(ID_PC[3]), .E(1'b1), .CK(CLOCK__L3_N2), .Q(EX_PC[3]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[4] ( .RN(\ID_EX_PC_REG_instance/n34 ),
.D(ID_PC[4]), .E(1'b1), .CK(CLOCK__L3_N3), .Q(EX_PC[4]), .QN(n1662) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[0] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(ID_IMM16_SHL2[2]), .E(1'b1),
.CK(CLOCK__L3_N2), .Q(EX_IMM16_EXT[0]), .QN(n1659) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[1] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(ID_IMM16_SHL2[3]), .E(1'b1),
.CK(CLOCK__L3_N3), .Q(EX_IMM16_EXT[1]) );
EDFFTRXL \ID_EX_IMM16_EXT_REG_instance/Q_reg[2] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(ID_IMM16_SHL2[4]), .E(1'b1),
.CK(CLOCK__L3_N3), .Q(EX_IMM16_EXT[2]), .QN(n1660) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[0] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[0]), .E(1'b1), .CK(CLOCK__L3_N9),
.Q(EX_REGB[0]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[1] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[1]), .E(1'b1), .CK(CLOCK__L3_N12),
.Q(EX_REGB[1]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[2] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[2]), .E(1'b1), .CK(CLOCK__L3_N12),
.Q(EX_REGB[2]) );
EDFFTRXL \ID_EX_REGB_REG_instance/Q_reg[3] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(RF_OUT2[3]), .E(1'b1), .CK(CLOCK__L3_N12),
.Q(EX_REGB[3]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[0] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[0]), .E(1'b1), .CK(CLOCK__L3_N4),
.Q(EX_REGA[0]) );
EDFFTRXL \ID_EX_REGA_REG_instance/Q_reg[1] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(RF_OUT1[1]), .E(1'b1), .CK(CLOCK__L3_N7),
.Q(EX_REGA[1]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[0] ( .RN(\ID_EX_PC_REG_instance/n34 ),
.D(ID_PC_SUM[0]), .E(1'b1), .CK(CLOCK__L3_N3), .Q(EX_PC[0]) );
EDFFTRXL \ID_EX_PC_REG_instance/Q_reg[1] ( .RN(\ID_EX_PC_REG_instance/n34 ),
.D(ID_PC_SUM[1]), .E(1'b1), .CK(CLOCK__L3_N18), .Q(EX_PC[1]) );
ADDFHXL \add_545/U1_30 ( .A(ID_PC[30]), .B(n2106), .CI(\add_545/carry[30] ),
.CO(\add_545/carry[31] ), .S(ID_PC_SUM[30]) );
ADDFXL \add_545/U1_3 ( .A(ID_PC[3]), .B(ID_IMM16_SHL2[3]), .CI(
\add_545/carry[3] ), .CO(\add_545/carry[4] ), .S(ID_PC_SUM[3]) );
ADDFHXL \add_545/U1_9 ( .A(ID_PC[9]), .B(ID_IMM16_SHL2[9]), .CI(
\add_545/carry[9] ), .CO(\add_545/carry[10] ), .S(ID_PC_SUM[9]) );
ADDFHXL \add_545/U1_10 ( .A(ID_PC[10]), .B(ID_IMM16_SHL2[10]), .CI(
\add_545/carry[10] ), .CO(\add_545/carry[11] ), .S(ID_PC_SUM[10]) );
ADDFHXL \add_545/U1_11 ( .A(ID_PC[11]), .B(ID_IMM16_SHL2[11]), .CI(
\add_545/carry[11] ), .CO(\add_545/carry[12] ), .S(ID_PC_SUM[11]) );
ADDFHXL \add_545/U1_12 ( .A(ID_PC[12]), .B(ID_IMM16_SHL2[12]), .CI(
\add_545/carry[12] ), .CO(\add_545/carry[13] ), .S(ID_PC_SUM[12]) );
ADDFHXL \add_545/U1_13 ( .A(ID_PC[13]), .B(ID_IMM16_SHL2[13]), .CI(
\add_545/carry[13] ), .CO(\add_545/carry[14] ), .S(ID_PC_SUM[13]) );
ADDFHXL \add_545/U1_14 ( .A(ID_PC[14]), .B(ID_IMM16_SHL2[14]), .CI(
\add_545/carry[14] ), .CO(\add_545/carry[15] ), .S(ID_PC_SUM[14]) );
ADDFHXL \add_545/U1_15 ( .A(ID_PC[15]), .B(ID_IMM16_SHL2[15]), .CI(
\add_545/carry[15] ), .CO(\add_545/carry[16] ), .S(ID_PC_SUM[15]) );
ADDFHXL \add_545/U1_16 ( .A(ID_PC[16]), .B(ID_IMM16_SHL2[16]), .CI(
\add_545/carry[16] ), .CO(\add_545/carry[17] ), .S(ID_PC_SUM[16]) );
ADDFHXL \add_545/U1_17 ( .A(ID_PC[17]), .B(n2106), .CI(\add_545/carry[17] ),
.CO(\add_545/carry[18] ), .S(ID_PC_SUM[17]) );
ADDFHXL \add_545/U1_18 ( .A(ID_PC[18]), .B(n2106), .CI(\add_545/carry[18] ),
.CO(\add_545/carry[19] ), .S(ID_PC_SUM[18]) );
ADDFHXL \add_545/U1_19 ( .A(ID_PC[19]), .B(n2106), .CI(\add_545/carry[19] ),
.CO(\add_545/carry[20] ), .S(ID_PC_SUM[19]) );
ADDFHXL \add_545/U1_20 ( .A(ID_PC[20]), .B(n2106), .CI(\add_545/carry[20] ),
.CO(\add_545/carry[21] ), .S(ID_PC_SUM[20]) );
ADDFHXL \add_545/U1_21 ( .A(ID_PC[21]), .B(n2106), .CI(\add_545/carry[21] ),
.CO(\add_545/carry[22] ), .S(ID_PC_SUM[21]) );
ADDFHXL \add_545/U1_22 ( .A(ID_PC[22]), .B(n2106), .CI(\add_545/carry[22] ),
.CO(\add_545/carry[23] ), .S(ID_PC_SUM[22]) );
ADDFHXL \add_545/U1_23 ( .A(ID_PC[23]), .B(n2106), .CI(\add_545/carry[23] ),
.CO(\add_545/carry[24] ), .S(ID_PC_SUM[23]) );
ADDFHXL \add_545/U1_24 ( .A(ID_PC[24]), .B(n2106), .CI(\add_545/carry[24] ),
.CO(\add_545/carry[25] ), .S(ID_PC_SUM[24]) );
ADDFHXL \add_545/U1_25 ( .A(ID_PC[25]), .B(n2106), .CI(\add_545/carry[25] ),
.CO(\add_545/carry[26] ), .S(ID_PC_SUM[25]) );
ADDFHXL \add_545/U1_26 ( .A(ID_PC[26]), .B(n2106), .CI(\add_545/carry[26] ),
.CO(\add_545/carry[27] ), .S(ID_PC_SUM[26]) );
ADDFHXL \add_545/U1_27 ( .A(ID_PC[27]), .B(n2106), .CI(\add_545/carry[27] ),
.CO(\add_545/carry[28] ), .S(ID_PC_SUM[27]) );
ADDFHXL \add_545/U1_28 ( .A(ID_PC[28]), .B(n2106), .CI(\add_545/carry[28] ),
.CO(\add_545/carry[29] ), .S(ID_PC_SUM[28]) );
ADDFHXL \add_545/U1_29 ( .A(ID_PC[29]), .B(n2106), .CI(\add_545/carry[29] ),
.CO(\add_545/carry[30] ), .S(ID_PC_SUM[29]) );
ADDFHXL \add_545/U1_8 ( .A(ID_PC[8]), .B(ID_IMM16_SHL2[8]), .CI(
\add_545/carry[8] ), .CO(\add_545/carry[9] ), .S(ID_PC_SUM[8]) );
ADDFHXL \add_545/U1_7 ( .A(ID_PC[7]), .B(ID_IMM16_SHL2[7]), .CI(
\add_545/carry[7] ), .CO(\add_545/carry[8] ), .S(ID_PC_SUM[7]) );
ADDFHXL \add_545/U1_6 ( .A(ID_PC[6]), .B(ID_IMM16_SHL2[6]), .CI(
\add_545/carry[6] ), .CO(\add_545/carry[7] ), .S(ID_PC_SUM[6]) );
ADDFHXL \add_545/U1_5 ( .A(ID_PC[5]), .B(ID_IMM16_SHL2[5]), .CI(
\add_545/carry[5] ), .CO(\add_545/carry[6] ), .S(ID_PC_SUM[5]) );
ADDFHXL \add_545/U1_4 ( .A(ID_PC[4]), .B(ID_IMM16_SHL2[4]), .CI(
\add_545/carry[4] ), .CO(\add_545/carry[5] ), .S(ID_PC_SUM[4]) );
XOR3XL \add_545/U1_31 ( .A(ID_PC[31]), .B(n2106), .C(\add_545/carry[31] ),
.Y(ID_PC_SUM[31]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[0] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[0]), .E(1'b1), .CK(CLOCK__L3_N1),
.Q(PORT_REGB[0]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[1] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[1]), .E(1'b1), .CK(CLOCK__L3_N12),
.Q(PORT_REGB[1]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[2] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[2]), .E(1'b1), .CK(CLOCK__L3_N11),
.Q(PORT_REGB[2]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[3] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[3]), .E(1'b1), .CK(CLOCK__L3_N12),
.Q(PORT_REGB[3]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[4] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[4]), .E(1'b1), .CK(CLOCK__L3_N11),
.Q(PORT_REGB[4]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[5] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[5]), .E(1'b1), .CK(CLOCK__L3_N0),
.Q(PORT_REGB[5]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[6] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[6]), .E(1'b1), .CK(CLOCK__L3_N9),
.Q(PORT_REGB[6]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[7] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[7]), .E(1'b1), .CK(CLOCK__L3_N8),
.Q(PORT_REGB[7]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[8] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[8]), .E(1'b1), .CK(CLOCK__L3_N7),
.Q(PORT_REGB[8]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[9] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[9]), .E(1'b1), .CK(CLOCK__L3_N7),
.Q(PORT_REGB[9]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[10] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[10]), .E(1'b1), .CK(CLOCK__L3_N8),
.Q(PORT_REGB[10]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[11] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[11]), .E(1'b1), .CK(CLOCK__L3_N1),
.Q(PORT_REGB[11]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[12] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[12]), .E(1'b1), .CK(CLOCK__L3_N9),
.Q(PORT_REGB[12]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[13] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[13]), .E(1'b1), .CK(CLOCK__L3_N9),
.Q(PORT_REGB[13]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[14] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[14]), .E(1'b1), .CK(CLOCK__L3_N12),
.Q(PORT_REGB[14]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[15] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[15]), .E(1'b1), .CK(CLOCK__L3_N10),
.Q(PORT_REGB[15]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[16] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[16]), .E(1'b1), .CK(CLOCK__L3_N1),
.Q(PORT_REGB[16]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[17] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[17]), .E(1'b1), .CK(CLOCK__L3_N12),
.Q(PORT_REGB[17]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[18] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[18]), .E(1'b1), .CK(CLOCK__L3_N1),
.Q(PORT_REGB[18]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[19] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[19]), .E(1'b1), .CK(CLOCK__L3_N9),
.Q(PORT_REGB[19]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[20] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[20]), .E(1'b1), .CK(CLOCK__L3_N10),
.Q(PORT_REGB[20]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[21] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[21]), .E(1'b1), .CK(CLOCK__L3_N12),
.Q(PORT_REGB[21]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[22] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[22]), .E(1'b1), .CK(CLOCK__L3_N10),
.Q(PORT_REGB[22]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[23] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[23]), .E(1'b1), .CK(CLOCK__L3_N1),
.Q(PORT_REGB[23]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[24] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[24]), .E(1'b1), .CK(CLOCK__L3_N11),
.Q(PORT_REGB[24]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[25] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[25]), .E(1'b1), .CK(CLOCK__L3_N11),
.Q(PORT_REGB[25]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[26] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[26]), .E(1'b1), .CK(CLOCK__L3_N11),
.Q(PORT_REGB[26]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[27] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[27]), .E(1'b1), .CK(CLOCK__L3_N9),
.Q(PORT_REGB[27]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[28] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[28]), .E(1'b1), .CK(CLOCK__L3_N11),
.Q(PORT_REGB[28]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[29] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[29]), .E(1'b1), .CK(CLOCK__L3_N11),
.Q(PORT_REGB[29]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[30] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[30]), .E(1'b1), .CK(CLOCK__L3_N10),
.Q(PORT_REGB[30]) );
EDFFTRXL \EX_MEM_REGB_REG_instance/Q_reg[31] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(EX_REGB[31]), .E(1'b1), .CK(CLOCK__L3_N11),
.Q(PORT_REGB[31]) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[26] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(MEM_INSTR[26]), .E(1'b1), .CK(CLOCK__L3_N17), .Q(WB_INSTR_26) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[31] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(MEM_INSTR[31]), .E(1'b1), .CK(CLOCK__L3_N17), .Q(WB_INSTR_31) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[28] ( .RN(
\ID_EX_PC_REG_instance/n34 ), .D(MEM_INSTR[28]), .E(1'b1), .CK(CLOCK__L3_N17),
.Q(WB_INSTR_28) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[29] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(MEM_INSTR[29]), .E(1'b1), .CK(CLOCK__L3_N16), .Q(WB_INSTR_29) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[27] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(MEM_INSTR[27]), .E(1'b1), .CK(CLOCK__L3_N16), .Q(WB_INSTR_27) );
EDFFTRXL \MEM_WB_INSTR_REG_instance/Q_reg[30] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(MEM_INSTR[30]), .E(1'b1), .CK(CLOCK__L3_N17), .Q(WB_INSTR_30) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[0] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(EX_INSTR[0]), .E(1'b1), .CK(CLOCK__L3_N16),
.Q(MEM_INSTR[0]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[1] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(EX_INSTR[1]), .E(1'b1), .CK(CLOCK__L3_N16),
.Q(MEM_INSTR[1]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[2] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(EX_INSTR[2]), .E(1'b1), .CK(CLOCK__L3_N16), .Q(MEM_INSTR[2]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[3] ( .RN(\PC_instance/n33 ), .D(
EX_INSTR[3]), .E(1'b1), .CK(CLOCK__L3_N16), .Q(MEM_INSTR[3]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[4] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(EX_INSTR[4]), .E(1'b1), .CK(CLOCK__L3_N16), .Q(MEM_INSTR[4]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[5] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(EX_INSTR[5]), .E(1'b1), .CK(CLOCK__L3_N16),
.Q(MEM_INSTR[5]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[6] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(EX_INSTR[6]), .E(1'b1), .CK(CLOCK__L3_N15),
.Q(MEM_INSTR[6]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[7] ( .RN(
\ID_EX_PC_REG_instance/n34 ), .D(EX_INSTR[7]), .E(1'b1), .CK(CLOCK__L3_N15),
.Q(MEM_INSTR[7]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[8] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(EX_INSTR[8]), .E(1'b1), .CK(CLOCK__L3_N15),
.Q(MEM_INSTR[8]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[9] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(EX_INSTR[9]), .E(1'b1), .CK(CLOCK__L3_N15),
.Q(MEM_INSTR[9]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[10] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(EX_INSTR[10]), .E(1'b1), .CK(CLOCK__L3_N13),
.Q(MEM_INSTR[10]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[0] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4860), .E(1'b1), .CK(CLOCK__L3_N8), .Q(
PORT_ALU[0]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[1] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4861), .E(1'b1), .CK(CLOCK__L3_N6), .Q(
PORT_ALU[1]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[2] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4862), .E(1'b1), .CK(CLOCK__L3_N7), .Q(
PORT_ALU[2]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[3] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4863), .E(1'b1), .CK(CLOCK__L3_N5), .Q(
PORT_ALU[3]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[4] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4864), .E(1'b1), .CK(CLOCK__L3_N0), .Q(
PORT_ALU[4]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[5] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4865), .E(1'b1), .CK(CLOCK__L3_N7), .Q(
PORT_ALU[5]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[6] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4866), .E(1'b1), .CK(CLOCK__L3_N8), .Q(
PORT_ALU[6]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[7] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4867), .E(1'b1), .CK(CLOCK__L3_N0), .Q(
PORT_ALU[7]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[8] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4868), .E(1'b1), .CK(CLOCK__L3_N1), .Q(
PORT_ALU[8]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[9] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4869), .E(1'b1), .CK(CLOCK__L3_N8), .Q(
PORT_ALU[9]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[10] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4870), .E(1'b1), .CK(CLOCK__L3_N7), .Q(
PORT_ALU[10]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[11] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4871), .E(1'b1), .CK(CLOCK__L3_N8), .Q(
PORT_ALU[11]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[12] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4872), .E(1'b1), .CK(CLOCK__L3_N0), .Q(
PORT_ALU[12]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[13] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4873), .E(1'b1), .CK(CLOCK__L3_N7), .Q(
PORT_ALU[13]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[14] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4874), .E(1'b1), .CK(CLOCK__L3_N8), .Q(
PORT_ALU[14]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[15] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4875), .E(1'b1), .CK(CLOCK__L3_N0), .Q(
PORT_ALU[15]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[16] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4876), .E(1'b1), .CK(CLOCK__L3_N4), .Q(
PORT_ALU[16]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[17] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4877), .E(1'b1), .CK(CLOCK__L3_N1), .Q(
PORT_ALU[17]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[18] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4878), .E(1'b1), .CK(CLOCK__L3_N5), .Q(
PORT_ALU[18]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[19] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4879), .E(1'b1), .CK(CLOCK__L3_N5), .Q(
PORT_ALU[19]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[20] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4880), .E(1'b1), .CK(CLOCK__L3_N5), .Q(
PORT_ALU[20]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[21] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4881), .E(1'b1), .CK(CLOCK__L3_N5), .Q(
PORT_ALU[21]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[22] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4882), .E(1'b1), .CK(CLOCK__L3_N6), .Q(
PORT_ALU[22]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[23] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4883), .E(1'b1), .CK(CLOCK__L3_N1), .Q(
PORT_ALU[23]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[24] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4884), .E(1'b1), .CK(CLOCK__L3_N0), .Q(
PORT_ALU[24]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[25] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4885), .E(1'b1), .CK(CLOCK__L3_N5), .Q(
PORT_ALU[25]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[26] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4886), .E(1'b1), .CK(CLOCK__L3_N1), .Q(
PORT_ALU[26]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[27] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4887), .E(1'b1), .CK(CLOCK__L3_N5), .Q(
PORT_ALU[27]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[28] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4888), .E(1'b1), .CK(CLOCK__L3_N6), .Q(
PORT_ALU[28]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[25] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N789), .E(n2153), .CK(n1625), .Q(
RF_ADD_RD1[4]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[27] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(EX_INSTR[27]), .E(1'b1), .CK(CLOCK__L3_N13),
.Q(MEM_INSTR[27]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[24] ( .RN(\PC_instance/n33 ), .D(
N788), .E(n2153), .CK(n1625), .Q(RF_ADD_RD1[3]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[26] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(N790), .E(n2153), .CK(n1625), .Q(
ID_INSTR_26) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[23] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(N787), .E(n2153), .CK(n1625), .Q(
RF_ADD_RD1[2]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[17] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(N781), .E(n2153), .CK(n1625), .Q(
RF_ADD_RD2[1]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[30] ( .RN(
\ID_EX_PC_REG_instance/n34 ), .D(N794), .E(n2153), .CK(n1625), .Q(
ID_INSTR_30) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[19] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(N783), .E(n2153), .CK(n1625), .Q(
RF_ADD_RD2[3]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[16] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N780), .E(n2153), .CK(n1625), .Q(
RF_ADD_RD2[0]) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[29] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(EX_INSTR[29]), .E(1'b1), .CK(CLOCK__L3_N17), .Q(MEM_INSTR[29]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[29] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(N793), .E(n2153), .CK(n1625), .Q(
ID_INSTR_29) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[22] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(N786), .E(n2153), .CK(n1625),
.Q(RF_ADD_RD1[1]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[27] ( .RN(
\ID_EX_PC_REG_instance/n34 ), .D(N791), .E(n2153), .CK(n1625), .Q(
ID_INSTR_27) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[18] ( .RN(
\ID_EX_PC_REG_instance/n34 ), .D(N782), .E(n2153), .CK(n1625), .Q(
RF_ADD_RD2[2]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[20] ( .RN(
\EX_MEM_REGB_REG_instance/n34 ), .D(N784), .E(n2153), .CK(n1625), .Q(
RF_ADD_RD2[4]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[31] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(N795), .E(n2153), .CK(n1625),
.Q(ID_INSTR_31) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[28] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(N792), .E(n2153), .CK(n1625), .Q(
ID_INSTR_28) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_30 ( .A(n1688), .B(n1679),
.S0(n2159), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][30] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_30 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][30] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][28] ), .S0(n1598), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][30] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_30 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][30] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][26] ), .S0(n1599), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][30] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_30 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][30] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][22] ), .S0(n2171), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][30] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_31 ( .A(n1689), .B(n1688),
.S0(n2159), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][31] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_31 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][31] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][29] ), .S0(n1598), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][31] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_31 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][31] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][27] ), .S0(n1599), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][31] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_31 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][31] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][23] ), .S0(n2171), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][31] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_5 ( .A(N4723), .B(n2186),
.S0(n2160), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][5] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_15 ( .A(n1648), .B(n2173),
.S0(n2160), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][15] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_17 ( .A(n1676), .B(n1681),
.S0(n2159), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][17] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_18 ( .A(n1686), .B(n1676),
.S0(n2160), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][18] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_19 ( .A(n1685), .B(n1686),
.S0(n2159), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][19] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_20 ( .A(n1680), .B(n1685),
.S0(n2160), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][20] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_21 ( .A(n1683), .B(n1680),
.S0(n2159), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][21] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_22 ( .A(n1684), .B(n1683),
.S0(n2160), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][22] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_23 ( .A(n1675), .B(n1684),
.S0(n2159), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][23] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_24 ( .A(n1682), .B(n1675),
.S0(n2160), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][24] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_25 ( .A(n1674), .B(n1682),
.S0(n2159), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][25] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_26 ( .A(n1677), .B(n1674),
.S0(n2160), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][26] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_27 ( .A(n1678), .B(n1677),
.S0(n2160), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][27] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_28 ( .A(n1687), .B(n1678),
.S0(n2160), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][28] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_29 ( .A(n1679), .B(n1687),
.S0(n2159), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][29] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_16 ( .A(n1681), .B(n1648),
.S0(n2160), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][16] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_2 ( .A(n2189), .B(n2112),
.S0(n2159), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][2] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_6 ( .A(N4724), .B(N4723),
.S0(n2160), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][6] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_7 ( .A(n2185), .B(N4724),
.S0(n2160), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][7] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_1 ( .A(n2113), .B(
\ALU_instance/SHIFTER_GENERIC_I/N202 ), .S0(n2159), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][1] ) );
EDFFTRXL \PC_instance/Q_reg[2] ( .RN(\PC_instance/n33 ), .D(N732), .E(n2153), .CK(n1625), .Q(PORT_PC[2]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[10] ( .RN(
\ID_EX_REGB_REG_instance/n34 ), .D(N774), .E(n2153), .CK(n1625), .Q(
ID_IMM16_SHL2[12]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[7] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N771), .E(n2153), .CK(n1625), .Q(
ID_IMM16_SHL2[9]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[8] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(N772), .E(n2153), .CK(n1625), .Q(
ID_IMM16_SHL2[10]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[9] ( .RN(
\ID_EX_PC_REG_instance/n34 ), .D(N773), .E(n2153), .CK(n1625), .Q(
ID_IMM16_SHL2[11]) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA0/add_1_root_add_20_2/U1_3 (
.A(n1689), .B(\ALU_instance/INTERNAL_B[31] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA0/add_1_root_add_20_2/carry[3] ), .CO(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/C0 ), .S(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S0[3] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA1/add_1_root_add_20_2/U1_3 (
.A(n1689), .B(\ALU_instance/INTERNAL_B[31] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA1/add_1_root_add_20_2/carry[3] ), .CO(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/C1 ), .S(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S1[3] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA0/add_1_root_add_20_2/U1_3 (
.A(n1678), .B(\ALU_instance/INTERNAL_B[27] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA0/add_1_root_add_20_2/carry[3] ), .CO(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/C0 ), .S(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S0[3] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA0/add_1_root_add_20_2/U1_3 (
.A(n1648), .B(\ALU_instance/INTERNAL_B[15] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA0/add_1_root_add_20_2/carry[3] ), .CO(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/C0 ), .S(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S0[3] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA0/add_1_root_add_20_2/U1_3 (
.A(n1685), .B(\ALU_instance/INTERNAL_B[19] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA0/add_1_root_add_20_2/carry[3] ), .CO(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/C0 ), .S(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S0[3] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA0/add_1_root_add_20_2/U1_3 (
.A(n1675), .B(\ALU_instance/INTERNAL_B[23] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA0/add_1_root_add_20_2/carry[3] ), .CO(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/C0 ), .S(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S0[3] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA1/add_1_root_add_20_2/U1_3 (
.A(n1678), .B(\ALU_instance/INTERNAL_B[27] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA1/add_1_root_add_20_2/carry[3] ), .CO(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/C1 ), .S(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S1[3] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA1/add_1_root_add_20_2/U1_3 (
.A(n1648), .B(\ALU_instance/INTERNAL_B[15] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA1/add_1_root_add_20_2/carry[3] ), .CO(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/C1 ), .S(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S1[3] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA1/add_1_root_add_20_2/U1_3 (
.A(n1685), .B(\ALU_instance/INTERNAL_B[19] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA1/add_1_root_add_20_2/carry[3] ), .CO(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/C1 ), .S(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S1[3] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA1/add_1_root_add_20_2/U1_3 (
.A(n1675), .B(\ALU_instance/INTERNAL_B[23] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA1/add_1_root_add_20_2/carry[3] ), .CO(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/C1 ), .S(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S1[3] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA1/add_1_root_add_20_2/U1_2 (
.A(n1688), .B(\ALU_instance/INTERNAL_B[30] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA1/add_1_root_add_20_2/carry[2] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA1/add_1_root_add_20_2/carry[3] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S1[2] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA0/add_1_root_add_20_2/U1_2 (
.A(n1688), .B(\ALU_instance/INTERNAL_B[30] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA0/add_1_root_add_20_2/carry[2] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA0/add_1_root_add_20_2/carry[3] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S0[2] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA1/add_1_root_add_20_2/U1_2 (
.A(n1677), .B(\ALU_instance/INTERNAL_B[26] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA1/add_1_root_add_20_2/carry[2] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA1/add_1_root_add_20_2/carry[3] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S1[2] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA0/add_1_root_add_20_2/U1_2 (
.A(n1677), .B(\ALU_instance/INTERNAL_B[26] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA0/add_1_root_add_20_2/carry[2] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA0/add_1_root_add_20_2/carry[3] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S0[2] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA1/add_1_root_add_20_2/U1_2 (
.A(n1686), .B(\ALU_instance/INTERNAL_B[18] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA1/add_1_root_add_20_2/carry[2] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA1/add_1_root_add_20_2/carry[3] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S1[2] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA0/add_1_root_add_20_2/U1_2 (
.A(n1686), .B(\ALU_instance/INTERNAL_B[18] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA0/add_1_root_add_20_2/carry[2] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA0/add_1_root_add_20_2/carry[3] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S0[2] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA1/add_1_root_add_20_2/U1_2 (
.A(n1684), .B(\ALU_instance/INTERNAL_B[22] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA1/add_1_root_add_20_2/carry[2] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA1/add_1_root_add_20_2/carry[3] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S1[2] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA0/add_1_root_add_20_2/U1_2 (
.A(n1684), .B(\ALU_instance/INTERNAL_B[22] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA0/add_1_root_add_20_2/carry[2] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA0/add_1_root_add_20_2/carry[3] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S0[2] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA0/add_1_root_add_20_2/U1_1 (
.A(n1674), .B(\ALU_instance/INTERNAL_B[25] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA0/add_1_root_add_20_2/carry[1] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA0/add_1_root_add_20_2/carry[2] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S0[1] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA0/add_1_root_add_20_2/U1_1 (
.A(n1676), .B(\ALU_instance/INTERNAL_B[17] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA0/add_1_root_add_20_2/carry[1] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA0/add_1_root_add_20_2/carry[2] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S0[1] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA0/add_1_root_add_20_2/U1_1 (
.A(n1683), .B(\ALU_instance/INTERNAL_B[21] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA0/add_1_root_add_20_2/carry[1] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA0/add_1_root_add_20_2/carry[2] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S0[1] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA1/add_1_root_add_20_2/U1_1 (
.A(n1679), .B(\ALU_instance/INTERNAL_B[29] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA1/add_1_root_add_20_2/carry[1] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA1/add_1_root_add_20_2/carry[2] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S1[1] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA1/add_1_root_add_20_2/U1_1 (
.A(n1674), .B(\ALU_instance/INTERNAL_B[25] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA1/add_1_root_add_20_2/carry[1] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA1/add_1_root_add_20_2/carry[2] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S1[1] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA1/add_1_root_add_20_2/U1_1 (
.A(n1676), .B(\ALU_instance/INTERNAL_B[17] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA1/add_1_root_add_20_2/carry[1] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA1/add_1_root_add_20_2/carry[2] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S1[1] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA1/add_1_root_add_20_2/U1_1 (
.A(n1683), .B(\ALU_instance/INTERNAL_B[21] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA1/add_1_root_add_20_2/carry[1] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA1/add_1_root_add_20_2/carry[2] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S1[1] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA0/add_1_root_add_20_2/U1_1 (
.A(n1679), .B(\ALU_instance/INTERNAL_B[29] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA0/add_1_root_add_20_2/carry[1] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA0/add_1_root_add_20_2/carry[2] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S0[1] ) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[0] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(N764), .E(n2153), .CK(n1625),
.Q(ID_IMM16_SHL2[2]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[5] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[5]), .E(1'b1),
.CK(CLOCK__L3_N15), .Q(EX_INSTR[5]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[2] ( .RN(\PC_instance/n33 ), .D(
N766), .E(n2153), .CK(n1625), .Q(ID_IMM16_SHL2[4]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[5] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(N769), .E(n2153), .CK(n1625), .Q(
ID_IMM16_SHL2[7]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[4] ( .RN(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .D(N768), .E(n2153), .CK(n1625),
.Q(ID_IMM16_SHL2[6]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[6] ( .RN(\PC_instance/n33 ), .D(
N770), .E(n2153), .CK(n1625), .Q(ID_IMM16_SHL2[8]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[1] ( .RN(
\MEM_WB_ALU_REG_instance/n34 ), .D(N765), .E(n2153), .CK(n1625), .Q(
ID_IMM16_SHL2[3]) );
EDFFTRXL \IF_ID_INSTR_REG_instance/Q_reg[3] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N767), .E(n2153), .CK(n1625), .Q(
ID_IMM16_SHL2[5]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[0] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[0]), .E(1'b1),
.CK(CLOCK__L3_N15), .Q(EX_INSTR[0]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[3] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[3]), .E(1'b1),
.CK(CLOCK__L3_N15), .Q(EX_INSTR[3]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[1] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[1]), .E(1'b1),
.CK(CLOCK__L3_N16), .Q(EX_INSTR[1]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[2] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[2]), .E(1'b1),
.CK(CLOCK__L3_N15), .Q(EX_INSTR[2]) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_4_31 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][31] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][15] ), .S0(N4831), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N265 ) );
ADDFHXL \BOOTH_instance/add_3_root_add_53_G7/U1_26 ( .A(
\BOOTH_instance/decoded[8][26] ), .B(
\BOOTH_instance/partial_products[2][26] ), .CI(
\BOOTH_instance/add_3_root_add_53_G7/carry[26] ), .CO(
\BOOTH_instance/add_3_root_add_53_G7/carry[27] ), .S(
\BOOTH_instance/partial_products[6][26] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA1/add_1_root_add_20_2/U1_2 (
.A(n2117), .B(\ALU_instance/INTERNAL_B[6] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA1/add_1_root_add_20_2/carry[2] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA1/add_1_root_add_20_2/carry[3] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S1[2] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA0/add_1_root_add_20_2/U1_2 (
.A(N4724), .B(\ALU_instance/INTERNAL_B[6] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA0/add_1_root_add_20_2/carry[2] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA0/add_1_root_add_20_2/carry[3] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S0[2] ) );
ADDFXL \BOOTH_instance/add_5_root_add_53_G7/U1_20 ( .A(
\BOOTH_instance/decoded[4][20] ), .B(\BOOTH_instance/decoded[5][20] ),
.CI(\BOOTH_instance/add_5_root_add_53_G7/carry[20] ), .CO(
\BOOTH_instance/add_5_root_add_53_G7/carry[21] ), .S(
\BOOTH_instance/partial_products[4][20] ) );
ADDFXL \BOOTH_instance/add_5_root_add_53_G7/U1_18 ( .A(
\BOOTH_instance/decoded[4][18] ), .B(\BOOTH_instance/decoded[5][18] ),
.CI(\BOOTH_instance/add_5_root_add_53_G7/carry[18] ), .CO(
\BOOTH_instance/add_5_root_add_53_G7/carry[19] ), .S(
\BOOTH_instance/partial_products[4][18] ) );
ADDFXL \BOOTH_instance/add_5_root_add_53_G7/U1_17 ( .A(
\BOOTH_instance/decoded[4][17] ), .B(\BOOTH_instance/decoded[5][17] ),
.CI(\BOOTH_instance/add_5_root_add_53_G7/carry[17] ), .CO(
\BOOTH_instance/add_5_root_add_53_G7/carry[18] ), .S(
\BOOTH_instance/partial_products[4][17] ) );
ADDFXL \BOOTH_instance/add_5_root_add_53_G7/U1_16 ( .A(
\BOOTH_instance/decoded[4][16] ), .B(\BOOTH_instance/decoded[5][16] ),
.CI(\BOOTH_instance/add_5_root_add_53_G7/carry[16] ), .CO(
\BOOTH_instance/add_5_root_add_53_G7/carry[17] ), .S(
\BOOTH_instance/partial_products[4][16] ) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_13 ( .A(
\BOOTH_instance/decoded[2][13] ), .B(\BOOTH_instance/decoded[3][13] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[13] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[14] ), .S(
\BOOTH_instance/partial_products[3][13] ) );
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_9 ( .A(
\BOOTH_instance/N218 ), .B(\BOOTH_instance/decoded[1][9] ), .CI(
\BOOTH_instance/add_7_root_add_53_G7/carry[9] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[10] ), .S(
\BOOTH_instance/partial_products[8][9] ) );
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_8 ( .A(
\BOOTH_instance/N217 ), .B(\BOOTH_instance/decoded[1][8] ), .CI(
\BOOTH_instance/add_7_root_add_53_G7/carry[8] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[9] ), .S(
\BOOTH_instance/partial_products[8][8] ) );
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_4 ( .A(
\BOOTH_instance/N213 ), .B(\BOOTH_instance/decoded[1][4] ), .CI(
\BOOTH_instance/add_7_root_add_53_G7/carry[4] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[5] ), .S(
\BOOTH_instance/partial_products[8][4] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA0/add_1_root_add_20_2/U1_1 (
.A(n2115), .B(\ALU_instance/INTERNAL_B[5] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA0/add_1_root_add_20_2/carry[1] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA0/add_1_root_add_20_2/carry[2] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S0[1] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA0/add_1_root_add_20_2/U1_1 (
.A(N4719), .B(\ALU_instance/INTERNAL_B[1] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA0/add_1_root_add_20_2/carry[1] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA0/add_1_root_add_20_2/carry[2] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S0[1] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA1/add_1_root_add_20_2/U1_1 (
.A(n2114), .B(\ALU_instance/INTERNAL_B[5] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA1/add_1_root_add_20_2/carry[1] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA1/add_1_root_add_20_2/carry[2] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S1[1] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA1/add_1_root_add_20_2/U1_1 (
.A(n2113), .B(\ALU_instance/INTERNAL_B[1] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA1/add_1_root_add_20_2/carry[1] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA1/add_1_root_add_20_2/carry[2] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S1[1] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_28 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][28] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][26] ), .S0(n1598), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][28] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_28 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][28] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][24] ), .S0(n2156), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][28] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_28 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][28] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][20] ), .S0(n2171), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][28] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_29 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][29] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][27] ), .S0(n1598), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][29] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_29 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][29] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][25] ), .S0(n2157), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][29] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_29 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][29] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][21] ), .S0(n2171), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][29] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_3 ( .A(N4721), .B(n2189),
.S0(n2160), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][3] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_4 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][4] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][2] ), .S0(n1598), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][4] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_5 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][5] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][3] ), .S0(n1598), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][5] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_6 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][6] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][4] ), .S0(n1598), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][6] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_7 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][7] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][5] ), .S0(n1598), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][7] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_8 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][8] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][6] ), .S0(n1598), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][8] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_9 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][9] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][7] ), .S0(n1598), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][9] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_10 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][10] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][8] ), .S0(n1598), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][10] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_11 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][11] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][9] ), .S0(n1598), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][11] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_12 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][12] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][10] ), .S0(n1598), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][12] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_13 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][13] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][11] ), .S0(n1598), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][13] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_14 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][14] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][12] ), .S0(n1598), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][14] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_15 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][15] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][13] ), .S0(n1598), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][15] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_16 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][16] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][14] ), .S0(n1598), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][16] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_17 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][17] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][15] ), .S0(n1598), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][17] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_18 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][18] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][16] ), .S0(n1598), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][18] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_19 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][19] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][17] ), .S0(n1598), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][19] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_20 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][20] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][18] ), .S0(n1598), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][20] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_21 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][21] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][19] ), .S0(n1598), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][21] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_22 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][22] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][20] ), .S0(n1598), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][22] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_23 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][23] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][21] ), .S0(n1598), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][23] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_24 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][24] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][22] ), .S0(n1598), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][24] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_25 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][25] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][23] ), .S0(n1598), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][25] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_26 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][26] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][24] ), .S0(n1598), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][26] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_27 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][27] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][25] ), .S0(n1598), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][27] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_10 ( .A(n2179), .B(n2181),
.S0(n2160), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][10] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_11 ( .A(n2177), .B(n2179),
.S0(n2160), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][11] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_2 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][2] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][0] ), .S0(n1598), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][2] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_1_3 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][3] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][1] ), .S0(n1598), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][3] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_4 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][4] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][0] ), .S0(n1599), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][4] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_5 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][5] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][1] ), .S0(n2157), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][5] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA0/add_1_root_add_20_2/U1_3 (
.A(n2177), .B(\ALU_instance/INTERNAL_B[11] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA0/add_1_root_add_20_2/carry[3] ), .CO(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/C0 ), .S(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S0[3] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA1/add_1_root_add_20_2/U1_3 (
.A(n2177), .B(\ALU_instance/INTERNAL_B[11] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA1/add_1_root_add_20_2/carry[3] ), .CO(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/C1 ), .S(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S1[3] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA1/add_1_root_add_20_2/U1_2 (
.A(n2179), .B(\ALU_instance/INTERNAL_B[10] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA1/add_1_root_add_20_2/carry[2] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA1/add_1_root_add_20_2/carry[3] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S1[2] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA0/add_1_root_add_20_2/U1_2 (
.A(n2179), .B(\ALU_instance/INTERNAL_B[10] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA0/add_1_root_add_20_2/carry[2] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA0/add_1_root_add_20_2/carry[3] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S0[2] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA1/add_1_root_add_20_2/U1_2 (
.A(n2173), .B(\ALU_instance/INTERNAL_B[14] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA1/add_1_root_add_20_2/carry[2] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA1/add_1_root_add_20_2/carry[3] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S1[2] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA0/add_1_root_add_20_2/U1_2 (
.A(n2173), .B(\ALU_instance/INTERNAL_B[14] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA0/add_1_root_add_20_2/carry[2] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA0/add_1_root_add_20_2/carry[3] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S0[2] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA0/add_1_root_add_20_2/U1_1 (
.A(n2181), .B(\ALU_instance/INTERNAL_B[9] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA0/add_1_root_add_20_2/carry[1] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA0/add_1_root_add_20_2/carry[2] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S0[1] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA1/add_1_root_add_20_2/U1_1 (
.A(n2181), .B(\ALU_instance/INTERNAL_B[9] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA1/add_1_root_add_20_2/carry[1] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA1/add_1_root_add_20_2/carry[2] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S1[1] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA1/add_1_root_add_20_2/U1_1 (
.A(n2174), .B(\ALU_instance/INTERNAL_B[13] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA1/add_1_root_add_20_2/carry[1] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA1/add_1_root_add_20_2/carry[2] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S1[1] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA0/add_1_root_add_20_2/U1_1 (
.A(n2174), .B(\ALU_instance/INTERNAL_B[13] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA0/add_1_root_add_20_2/carry[1] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA0/add_1_root_add_20_2/carry[2] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S0[1] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_4_28 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][28] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][12] ), .S0(N4831), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N262 ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_4_29 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][29] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][13] ), .S0(N4831), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N263 ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_4_30 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][30] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][14] ), .S0(n2163), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N264 ) );
XOR3XL \BOOTH_instance/add_0_root_add_53_G7/U1_31 ( .A(
\BOOTH_instance/partial_products[7][31] ), .B(
\BOOTH_instance/partial_products[8][31] ), .C(
\BOOTH_instance/add_0_root_add_53_G7/carry[31] ), .Y(EX_MULT_OUT[31])
);
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA0/add_1_root_add_20_2/U1_3 (
.A(n2185), .B(\ALU_instance/INTERNAL_B[7] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA0/add_1_root_add_20_2/carry[3] ), .CO(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/C0 ), .S(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S0[3] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA1/add_1_root_add_20_2/U1_3 (
.A(n2185), .B(\ALU_instance/INTERNAL_B[7] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA1/add_1_root_add_20_2/carry[3] ), .CO(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/C1 ), .S(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S1[3] ) );
ADDFHXL \BOOTH_instance/add_3_root_add_53_G7/U1_30 ( .A(
\BOOTH_instance/decoded[8][30] ), .B(
\BOOTH_instance/partial_products[2][30] ), .CI(
\BOOTH_instance/add_3_root_add_53_G7/carry[30] ), .CO(
\BOOTH_instance/add_3_root_add_53_G7/carry[31] ), .S(
\BOOTH_instance/partial_products[6][30] ) );
ADDFHXL \BOOTH_instance/add_1_root_add_53_G7/U1_13 ( .A(
\BOOTH_instance/partial_products[5][13] ), .B(
\BOOTH_instance/partial_products[6][13] ), .CI(
\BOOTH_instance/add_1_root_add_53_G7/carry[13] ), .CO(
\BOOTH_instance/add_1_root_add_53_G7/carry[14] ), .S(
\BOOTH_instance/partial_products[8][13] ) );
ADDFXL \BOOTH_instance/add_5_root_add_53_G7/U1_11 ( .A(
\BOOTH_instance/decoded[4][11] ), .B(\BOOTH_instance/decoded[5][11] ),
.CI(\BOOTH_instance/add_5_root_add_53_G7/carry[11] ), .CO(
\BOOTH_instance/add_5_root_add_53_G7/carry[12] ), .S(
\BOOTH_instance/partial_products[4][11] ) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_7 ( .A(
\BOOTH_instance/decoded[2][7] ), .B(\BOOTH_instance/decoded[3][7] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[7] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[8] ), .S(
\BOOTH_instance/partial_products[7][7] ) );
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_5 ( .A(
\BOOTH_instance/partial_products[7][5] ), .B(
\BOOTH_instance/partial_products[8][5] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[5] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[6] ), .S(EX_MULT_OUT[5]) );
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_3 ( .A(
\BOOTH_instance/N212 ), .B(\BOOTH_instance/decoded[1][3] ), .CI(
\BOOTH_instance/add_7_root_add_53_G7/carry[3] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[4] ), .S(EX_MULT_OUT[3]) );
ADDFHXL \BOOTH_instance/add_3_root_add_53_G7/U1_29 ( .A(
\BOOTH_instance/decoded[8][29] ), .B(
\BOOTH_instance/partial_products[2][29] ), .CI(
\BOOTH_instance/add_3_root_add_53_G7/carry[29] ), .CO(
\BOOTH_instance/add_3_root_add_53_G7/carry[30] ), .S(
\BOOTH_instance/partial_products[6][29] ) );
ADDFHXL \BOOTH_instance/add_3_root_add_53_G7/U1_28 ( .A(
\BOOTH_instance/decoded[8][28] ), .B(
\BOOTH_instance/partial_products[2][28] ), .CI(
\BOOTH_instance/add_3_root_add_53_G7/carry[28] ), .CO(
\BOOTH_instance/add_3_root_add_53_G7/carry[29] ), .S(
\BOOTH_instance/partial_products[6][28] ) );
ADDFHXL \BOOTH_instance/add_1_root_add_53_G7/U1_26 ( .A(
\BOOTH_instance/partial_products[5][26] ), .B(
\BOOTH_instance/partial_products[6][26] ), .CI(
\BOOTH_instance/add_1_root_add_53_G7/carry[26] ), .CO(
\BOOTH_instance/add_1_root_add_53_G7/carry[27] ), .S(
\BOOTH_instance/partial_products[8][26] ) );
ADDFHXL \BOOTH_instance/add_3_root_add_53_G7/U1_27 ( .A(
\BOOTH_instance/decoded[8][27] ), .B(
\BOOTH_instance/partial_products[2][27] ), .CI(
\BOOTH_instance/add_3_root_add_53_G7/carry[27] ), .CO(
\BOOTH_instance/add_3_root_add_53_G7/carry[28] ), .S(
\BOOTH_instance/partial_products[6][27] ) );
ADDFXL \BOOTH_instance/add_5_root_add_53_G7/U1_26 ( .A(
\BOOTH_instance/decoded[4][31] ), .B(\BOOTH_instance/decoded[5][26] ),
.CI(\BOOTH_instance/add_5_root_add_53_G7/carry[26] ), .CO(
\BOOTH_instance/add_5_root_add_53_G7/carry[27] ), .S(
\BOOTH_instance/partial_products[4][26] ) );
ADDFXL \BOOTH_instance/add_5_root_add_53_G7/U1_25 ( .A(
\BOOTH_instance/decoded[4][31] ), .B(\BOOTH_instance/decoded[5][25] ),
.CI(\BOOTH_instance/add_5_root_add_53_G7/carry[25] ), .CO(
\BOOTH_instance/add_5_root_add_53_G7/carry[26] ), .S(
\BOOTH_instance/partial_products[4][25] ) );
ADDFHXL \BOOTH_instance/add_1_root_add_53_G7/U1_24 ( .A(
\BOOTH_instance/partial_products[5][24] ), .B(
\BOOTH_instance/partial_products[6][24] ), .CI(
\BOOTH_instance/add_1_root_add_53_G7/carry[24] ), .CO(
\BOOTH_instance/add_1_root_add_53_G7/carry[25] ), .S(
\BOOTH_instance/partial_products[8][24] ) );
ADDFHXL \BOOTH_instance/add_3_root_add_53_G7/U1_25 ( .A(
\BOOTH_instance/decoded[8][25] ), .B(
\BOOTH_instance/partial_products[2][25] ), .CI(
\BOOTH_instance/add_3_root_add_53_G7/carry[25] ), .CO(
\BOOTH_instance/add_3_root_add_53_G7/carry[26] ), .S(
\BOOTH_instance/partial_products[6][25] ) );
ADDFXL \BOOTH_instance/add_5_root_add_53_G7/U1_24 ( .A(
\BOOTH_instance/decoded[4][24] ), .B(\BOOTH_instance/decoded[5][24] ),
.CI(\BOOTH_instance/add_5_root_add_53_G7/carry[24] ), .CO(
\BOOTH_instance/add_5_root_add_53_G7/carry[25] ), .S(
\BOOTH_instance/partial_products[4][24] ) );
ADDFHXL \BOOTH_instance/add_3_root_add_53_G7/U1_24 ( .A(
\BOOTH_instance/decoded[8][24] ), .B(
\BOOTH_instance/partial_products[2][24] ), .CI(
\BOOTH_instance/add_3_root_add_53_G7/carry[24] ), .CO(
\BOOTH_instance/add_3_root_add_53_G7/carry[25] ), .S(
\BOOTH_instance/partial_products[6][24] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA1/add_1_root_add_20_2/U1_2 (
.A(n2189), .B(\ALU_instance/INTERNAL_B[2] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA1/add_1_root_add_20_2/carry[2] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA1/add_1_root_add_20_2/carry[3] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S1[2] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA0/add_1_root_add_20_2/U1_2 (
.A(n2189), .B(\ALU_instance/INTERNAL_B[2] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA0/add_1_root_add_20_2/carry[2] ), .CO(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA0/add_1_root_add_20_2/carry[3] ), .S(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S0[2] ) );
ADDFXL \BOOTH_instance/add_5_root_add_53_G7/U1_23 ( .A(
\BOOTH_instance/decoded[4][23] ), .B(\BOOTH_instance/decoded[5][23] ),
.CI(\BOOTH_instance/add_5_root_add_53_G7/carry[23] ), .CO(
\BOOTH_instance/add_5_root_add_53_G7/carry[24] ), .S(
\BOOTH_instance/partial_products[4][23] ) );
ADDFHXL \BOOTH_instance/add_1_root_add_53_G7/U1_22 ( .A(
\BOOTH_instance/partial_products[5][22] ), .B(
\BOOTH_instance/partial_products[6][22] ), .CI(
\BOOTH_instance/add_1_root_add_53_G7/carry[22] ), .CO(
\BOOTH_instance/add_1_root_add_53_G7/carry[23] ), .S(
\BOOTH_instance/partial_products[8][22] ) );
ADDFHXL \BOOTH_instance/add_3_root_add_53_G7/U1_23 ( .A(
\BOOTH_instance/decoded[8][23] ), .B(
\BOOTH_instance/partial_products[2][23] ), .CI(
\BOOTH_instance/add_3_root_add_53_G7/carry[23] ), .CO(
\BOOTH_instance/add_3_root_add_53_G7/carry[24] ), .S(
\BOOTH_instance/partial_products[6][23] ) );
ADDFXL \BOOTH_instance/add_5_root_add_53_G7/U1_22 ( .A(
\BOOTH_instance/decoded[4][22] ), .B(\BOOTH_instance/decoded[5][22] ),
.CI(\BOOTH_instance/add_5_root_add_53_G7/carry[22] ), .CO(
\BOOTH_instance/add_5_root_add_53_G7/carry[23] ), .S(
\BOOTH_instance/partial_products[4][22] ) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_22 ( .A(
\BOOTH_instance/decoded[2][31] ), .B(\BOOTH_instance/decoded[3][22] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[22] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[23] ), .S(
\BOOTH_instance/partial_products[3][22] ) );
ADDFHXL \BOOTH_instance/add_1_root_add_53_G7/U1_21 ( .A(
\BOOTH_instance/partial_products[5][21] ), .B(
\BOOTH_instance/partial_products[6][21] ), .CI(
\BOOTH_instance/add_1_root_add_53_G7/carry[21] ), .CO(
\BOOTH_instance/add_1_root_add_53_G7/carry[22] ), .S(
\BOOTH_instance/partial_products[8][21] ) );
ADDFHXL \BOOTH_instance/add_3_root_add_53_G7/U1_22 ( .A(
\BOOTH_instance/decoded[8][22] ), .B(
\BOOTH_instance/partial_products[2][22] ), .CI(
\BOOTH_instance/add_3_root_add_53_G7/carry[22] ), .CO(
\BOOTH_instance/add_3_root_add_53_G7/carry[23] ), .S(
\BOOTH_instance/partial_products[6][22] ) );
ADDFXL \BOOTH_instance/add_5_root_add_53_G7/U1_21 ( .A(
\BOOTH_instance/decoded[4][21] ), .B(\BOOTH_instance/decoded[5][21] ),
.CI(\BOOTH_instance/add_5_root_add_53_G7/carry[21] ), .CO(
\BOOTH_instance/add_5_root_add_53_G7/carry[22] ), .S(
\BOOTH_instance/partial_products[4][21] ) );
ADDFXL \BOOTH_instance/add_2_root_add_53_G7/U1_20 ( .A(
\BOOTH_instance/partial_products[3][20] ), .B(
\BOOTH_instance/partial_products[4][20] ), .CI(
\BOOTH_instance/add_2_root_add_53_G7/carry[20] ), .CO(
\BOOTH_instance/add_2_root_add_53_G7/carry[21] ), .S(
\BOOTH_instance/partial_products[7][20] ) );
ADDFHXL \BOOTH_instance/add_1_root_add_53_G7/U1_20 ( .A(
\BOOTH_instance/partial_products[5][20] ), .B(
\BOOTH_instance/partial_products[6][20] ), .CI(
\BOOTH_instance/add_1_root_add_53_G7/carry[20] ), .CO(
\BOOTH_instance/add_1_root_add_53_G7/carry[21] ), .S(
\BOOTH_instance/partial_products[8][20] ) );
ADDFHXL \BOOTH_instance/add_3_root_add_53_G7/U1_21 ( .A(
\BOOTH_instance/decoded[8][21] ), .B(
\BOOTH_instance/partial_products[2][21] ), .CI(
\BOOTH_instance/add_3_root_add_53_G7/carry[21] ), .CO(
\BOOTH_instance/add_3_root_add_53_G7/carry[22] ), .S(
\BOOTH_instance/partial_products[6][21] ) );
ADDFXL \BOOTH_instance/add_5_root_add_53_G7/U1_19 ( .A(
\BOOTH_instance/decoded[4][19] ), .B(\BOOTH_instance/decoded[5][19] ),
.CI(\BOOTH_instance/add_5_root_add_53_G7/carry[19] ), .CO(
\BOOTH_instance/add_5_root_add_53_G7/carry[20] ), .S(
\BOOTH_instance/partial_products[4][19] ) );
ADDFXL \BOOTH_instance/add_2_root_add_53_G7/U1_18 ( .A(
\BOOTH_instance/partial_products[3][18] ), .B(
\BOOTH_instance/partial_products[4][18] ), .CI(
\BOOTH_instance/add_2_root_add_53_G7/carry[18] ), .CO(
\BOOTH_instance/add_2_root_add_53_G7/carry[19] ), .S(
\BOOTH_instance/partial_products[7][18] ) );
ADDFHXL \BOOTH_instance/add_1_root_add_53_G7/U1_18 ( .A(
\BOOTH_instance/partial_products[5][18] ), .B(
\BOOTH_instance/partial_products[6][18] ), .CI(
\BOOTH_instance/add_1_root_add_53_G7/carry[18] ), .CO(
\BOOTH_instance/add_1_root_add_53_G7/carry[19] ), .S(
\BOOTH_instance/partial_products[8][18] ) );
ADDFHXL \BOOTH_instance/add_3_root_add_53_G7/U1_19 ( .A(
\BOOTH_instance/decoded[8][19] ), .B(
\BOOTH_instance/partial_products[2][19] ), .CI(
\BOOTH_instance/add_3_root_add_53_G7/carry[19] ), .CO(
\BOOTH_instance/add_3_root_add_53_G7/carry[20] ), .S(
\BOOTH_instance/partial_products[6][19] ) );
ADDFXL \BOOTH_instance/add_2_root_add_53_G7/U1_17 ( .A(
\BOOTH_instance/partial_products[3][17] ), .B(
\BOOTH_instance/partial_products[4][17] ), .CI(
\BOOTH_instance/add_2_root_add_53_G7/carry[17] ), .CO(
\BOOTH_instance/add_2_root_add_53_G7/carry[18] ), .S(
\BOOTH_instance/partial_products[7][17] ) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_18 ( .A(
\BOOTH_instance/decoded[2][18] ), .B(\BOOTH_instance/decoded[3][18] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[18] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[19] ), .S(
\BOOTH_instance/partial_products[3][18] ) );
ADDFHXL \BOOTH_instance/add_1_root_add_53_G7/U1_15 ( .A(
\BOOTH_instance/partial_products[5][15] ), .B(
\BOOTH_instance/partial_products[6][15] ), .CI(
\BOOTH_instance/add_1_root_add_53_G7/carry[15] ), .CO(
\BOOTH_instance/add_1_root_add_53_G7/carry[16] ), .S(
\BOOTH_instance/partial_products[8][15] ) );
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_17 ( .A(
\BOOTH_instance/decoded[0][31] ), .B(\BOOTH_instance/decoded[1][17] ),
.CI(\BOOTH_instance/add_7_root_add_53_G7/carry[17] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[18] ), .S(
\BOOTH_instance/partial_products[2][17] ) );
ADDFXL \BOOTH_instance/add_5_root_add_53_G7/U1_15 ( .A(
\BOOTH_instance/decoded[4][15] ), .B(\BOOTH_instance/decoded[5][15] ),
.CI(\BOOTH_instance/add_5_root_add_53_G7/carry[15] ), .CO(
\BOOTH_instance/add_5_root_add_53_G7/carry[16] ), .S(
\BOOTH_instance/partial_products[4][15] ) );
ADDFXL \BOOTH_instance/add_2_root_add_53_G7/U1_14 ( .A(
\BOOTH_instance/partial_products[3][14] ), .B(
\BOOTH_instance/partial_products[4][14] ), .CI(
\BOOTH_instance/add_2_root_add_53_G7/carry[14] ), .CO(
\BOOTH_instance/add_2_root_add_53_G7/carry[15] ), .S(
\BOOTH_instance/partial_products[7][14] ) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_15 ( .A(
\BOOTH_instance/decoded[2][15] ), .B(\BOOTH_instance/decoded[3][15] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[15] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[16] ), .S(
\BOOTH_instance/partial_products[3][15] ) );
ADDFXL \BOOTH_instance/add_5_root_add_53_G7/U1_14 ( .A(
\BOOTH_instance/decoded[4][14] ), .B(\BOOTH_instance/decoded[5][14] ),
.CI(\BOOTH_instance/add_5_root_add_53_G7/carry[14] ), .CO(
\BOOTH_instance/add_5_root_add_53_G7/carry[15] ), .S(
\BOOTH_instance/partial_products[4][14] ) );
ADDFXL \BOOTH_instance/add_5_root_add_53_G7/U1_13 ( .A(
\BOOTH_instance/decoded[4][13] ), .B(\BOOTH_instance/decoded[5][13] ),
.CI(\BOOTH_instance/add_5_root_add_53_G7/carry[13] ), .CO(
\BOOTH_instance/add_5_root_add_53_G7/carry[14] ), .S(
\BOOTH_instance/partial_products[4][13] ) );
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_14 ( .A(
\BOOTH_instance/N223 ), .B(\BOOTH_instance/decoded[1][14] ), .CI(
\BOOTH_instance/add_7_root_add_53_G7/carry[14] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[15] ), .S(
\BOOTH_instance/partial_products[6][14] ) );
ADDFXL \BOOTH_instance/add_5_root_add_53_G7/U1_12 ( .A(
\BOOTH_instance/decoded[4][12] ), .B(\BOOTH_instance/decoded[5][12] ),
.CI(\BOOTH_instance/add_5_root_add_53_G7/carry[12] ), .CO(
\BOOTH_instance/add_5_root_add_53_G7/carry[13] ), .S(
\BOOTH_instance/partial_products[4][12] ) );
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_10 ( .A(
\BOOTH_instance/partial_products[7][10] ), .B(
\BOOTH_instance/partial_products[8][10] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[10] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[11] ), .S(EX_MULT_OUT[10])
);
ADDFXL \BOOTH_instance/add_2_root_add_53_G7/U1_10 ( .A(
\BOOTH_instance/partial_products[3][10] ), .B(
\BOOTH_instance/partial_products[4][10] ), .CI(
\BOOTH_instance/add_2_root_add_53_G7/carry[10] ), .CO(
\BOOTH_instance/add_2_root_add_53_G7/carry[11] ), .S(
\BOOTH_instance/partial_products[7][10] ) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_11 ( .A(
\BOOTH_instance/decoded[2][11] ), .B(\BOOTH_instance/decoded[3][11] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[11] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[12] ), .S(
\BOOTH_instance/partial_products[3][11] ) );
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_11 ( .A(
\BOOTH_instance/N220 ), .B(\BOOTH_instance/decoded[1][11] ), .CI(
\BOOTH_instance/add_7_root_add_53_G7/carry[11] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[12] ), .S(
\BOOTH_instance/partial_products[8][11] ) );
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_8 ( .A(
\BOOTH_instance/partial_products[7][8] ), .B(
\BOOTH_instance/partial_products[8][8] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[8] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[9] ), .S(EX_MULT_OUT[8]) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_9 ( .A(
\BOOTH_instance/decoded[2][9] ), .B(\BOOTH_instance/decoded[3][9] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[9] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[10] ), .S(
\BOOTH_instance/partial_products[3][9] ) );
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_6 ( .A(
\BOOTH_instance/partial_products[7][6] ), .B(
\BOOTH_instance/partial_products[8][6] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[6] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[7] ), .S(EX_MULT_OUT[6]) );
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_7 ( .A(
\BOOTH_instance/N216 ), .B(\BOOTH_instance/decoded[1][7] ), .CI(
\BOOTH_instance/add_7_root_add_53_G7/carry[7] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[8] ), .S(
\BOOTH_instance/partial_products[8][7] ) );
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_6 ( .A(
\BOOTH_instance/N215 ), .B(\BOOTH_instance/decoded[1][6] ), .CI(
\BOOTH_instance/add_7_root_add_53_G7/carry[6] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[7] ), .S(
\BOOTH_instance/partial_products[8][6] ) );
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_5 ( .A(
\BOOTH_instance/N214 ), .B(\BOOTH_instance/decoded[1][5] ), .CI(
\BOOTH_instance/add_7_root_add_53_G7/carry[5] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[6] ), .S(
\BOOTH_instance/partial_products[8][5] ) );
XOR3XL \BOOTH_instance/add_3_root_add_53_G7/U1_31 ( .A(
\BOOTH_instance/decoded[8][31] ), .B(
\BOOTH_instance/partial_products[2][31] ), .C(
\BOOTH_instance/add_3_root_add_53_G7/carry[31] ), .Y(
\BOOTH_instance/partial_products[6][31] ) );
XOR3XL \BOOTH_instance/add_1_root_add_53_G7/U1_31 ( .A(
\BOOTH_instance/partial_products[5][31] ), .B(
\BOOTH_instance/partial_products[6][31] ), .C(
\BOOTH_instance/add_1_root_add_53_G7/carry[31] ), .Y(
\BOOTH_instance/partial_products[8][31] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_16 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][16] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][8] ), .S0(n2171), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][16] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_17 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][17] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][9] ), .S0(n2171), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][17] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_18 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][18] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][10] ), .S0(n2171), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][18] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_19 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][19] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][11] ), .S0(n2171), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][19] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_20 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][20] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][12] ), .S0(n2171), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][20] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_21 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][21] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][13] ), .S0(n2171), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][21] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_22 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][22] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][14] ), .S0(n2171), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][22] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_23 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][23] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][15] ), .S0(n2171), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][23] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_24 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][24] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][20] ), .S0(n2156), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][24] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_24 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][24] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][16] ), .S0(n2171), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][24] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_25 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][25] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][21] ), .S0(n2157), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][25] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_25 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][25] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][17] ), .S0(n2171), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][25] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_26 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][26] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][22] ), .S0(n2157), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][26] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_26 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][26] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][18] ), .S0(n2171), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][26] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_27 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][27] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][23] ), .S0(n2156), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][27] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_27 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][27] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][19] ), .S0(n2171), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][27] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_4 ( .A(n2186), .B(N4721),
.S0(n2160), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][4] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_8 ( .A(n2183), .B(n2185),
.S0(n2160), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][8] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_9 ( .A(n2181), .B(n2183),
.S0(n2160), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][9] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_12 ( .A(n2175), .B(n2177),
.S0(n2160), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][12] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_13 ( .A(n2174), .B(n2175),
.S0(n2160), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][13] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_0_14 ( .A(n2173), .B(n2174),
.S0(n2160), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][14] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_8 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][8] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][4] ), .S0(n1599), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][8] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_9 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][9] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][5] ), .S0(n2156), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][9] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_10 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][10] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][6] ), .S0(n2157), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][10] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_11 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][11] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][7] ), .S0(n2157), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][11] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_12 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][12] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][8] ), .S0(n1599), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][12] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_13 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][13] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][9] ), .S0(n2156), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][13] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_14 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][14] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][10] ), .S0(n2156), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][14] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_15 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][15] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][11] ), .S0(n2157), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][15] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_16 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][16] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][12] ), .S0(n2156), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][16] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_17 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][17] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][13] ), .S0(n2156), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][17] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_18 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][18] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][14] ), .S0(n2157), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][18] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_19 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][19] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][15] ), .S0(n2157), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][19] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_20 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][20] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][16] ), .S0(n1599), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][20] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_21 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][21] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][17] ), .S0(n1599), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][21] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_22 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][22] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][18] ), .S0(n1599), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][22] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_23 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][23] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][19] ), .S0(n1599), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][23] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_12 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][12] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][4] ), .S0(n2171), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][12] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_13 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][13] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][5] ), .S0(n2171), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][13] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_14 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][14] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][6] ), .S0(n2171), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][14] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_15 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][15] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][7] ), .S0(n2171), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][15] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_8 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][8] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][0] ), .S0(n2171), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][8] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_9 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][9] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][1] ), .S0(n2171), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][9] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_10 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][10] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][2] ), .S0(n2171), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][10] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_3_11 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][11] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][3] ), .S0(n2171), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][11] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_6 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][6] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][2] ), .S0(n2156), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][6] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_2_7 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][7] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][3] ), .S0(n2156), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][7] ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_4_16 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][16] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][0] ), .S0(n2167), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N250 ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_4_17 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][17] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][1] ), .S0(n2167), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N251 ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_4_20 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][20] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][4] ), .S0(n2167), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N254 ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_4_18 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][18] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][2] ), .S0(n2167), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N252 ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_4_19 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][19] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][3] ), .S0(n2163), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N253 ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_4_21 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][21] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][5] ), .S0(N4831), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N255 ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_4_22 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][22] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][6] ), .S0(N4831), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N256 ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_4_23 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][23] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][7] ), .S0(N4831), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N257 ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_4_24 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][24] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][8] ), .S0(N4831), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N258 ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_4_25 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][25] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][9] ), .S0(N4831), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N259 ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_4_26 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][26] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][10] ), .S0(N4831), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N260 ) );
MX2XL \ALU_instance/SHIFTER_GENERIC_I/C88/M1_4_27 ( .A(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][27] ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][11] ), .S0(n2163), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N261 ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA0/add_1_root_add_20_2/U1_3 (
.A(N4721), .B(\ALU_instance/INTERNAL_B[3] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA0/add_1_root_add_20_2/carry[3] ), .CO(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/C0 ), .S(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S0[3] ) );
ADDFXL \ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA1/add_1_root_add_20_2/U1_3 (
.A(N4721), .B(\ALU_instance/INTERNAL_B[3] ), .CI(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA1/add_1_root_add_20_2/carry[3] ), .CO(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/C1 ), .S(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S1[3] ) );
ADDFHXL \BOOTH_instance/add_1_root_add_53_G7/U1_30 ( .A(
\BOOTH_instance/partial_products[5][30] ), .B(
\BOOTH_instance/partial_products[6][30] ), .CI(
\BOOTH_instance/add_1_root_add_53_G7/carry[30] ), .CO(
\BOOTH_instance/add_1_root_add_53_G7/carry[31] ), .S(
\BOOTH_instance/partial_products[8][30] ) );
ADDFXL \BOOTH_instance/add_5_root_add_53_G7/U1_30 ( .A(
\BOOTH_instance/decoded[4][31] ), .B(\BOOTH_instance/decoded[5][31] ),
.CI(\BOOTH_instance/add_5_root_add_53_G7/carry[30] ), .CO(
\BOOTH_instance/add_5_root_add_53_G7/carry[31] ), .S(
\BOOTH_instance/partial_products[4][30] ) );
ADDFHXL \BOOTH_instance/add_1_root_add_53_G7/U1_29 ( .A(
\BOOTH_instance/partial_products[5][29] ), .B(
\BOOTH_instance/partial_products[6][29] ), .CI(
\BOOTH_instance/add_1_root_add_53_G7/carry[29] ), .CO(
\BOOTH_instance/add_1_root_add_53_G7/carry[30] ), .S(
\BOOTH_instance/partial_products[8][29] ) );
ADDFXL \BOOTH_instance/add_5_root_add_53_G7/U1_29 ( .A(
\BOOTH_instance/decoded[4][31] ), .B(\BOOTH_instance/decoded[5][31] ),
.CI(\BOOTH_instance/add_5_root_add_53_G7/carry[29] ), .CO(
\BOOTH_instance/add_5_root_add_53_G7/carry[30] ), .S(
\BOOTH_instance/partial_products[4][29] ) );
ADDFHXL \BOOTH_instance/add_1_root_add_53_G7/U1_28 ( .A(
\BOOTH_instance/partial_products[5][28] ), .B(
\BOOTH_instance/partial_products[6][28] ), .CI(
\BOOTH_instance/add_1_root_add_53_G7/carry[28] ), .CO(
\BOOTH_instance/add_1_root_add_53_G7/carry[29] ), .S(
\BOOTH_instance/partial_products[8][28] ) );
ADDFXL \BOOTH_instance/add_5_root_add_53_G7/U1_28 ( .A(
\BOOTH_instance/decoded[4][31] ), .B(\BOOTH_instance/decoded[5][31] ),
.CI(\BOOTH_instance/add_5_root_add_53_G7/carry[28] ), .CO(
\BOOTH_instance/add_5_root_add_53_G7/carry[29] ), .S(
\BOOTH_instance/partial_products[4][28] ) );
ADDFHXL \BOOTH_instance/add_1_root_add_53_G7/U1_27 ( .A(
\BOOTH_instance/partial_products[5][27] ), .B(
\BOOTH_instance/partial_products[6][27] ), .CI(
\BOOTH_instance/add_1_root_add_53_G7/carry[27] ), .CO(
\BOOTH_instance/add_1_root_add_53_G7/carry[28] ), .S(
\BOOTH_instance/partial_products[8][27] ) );
ADDFXL \BOOTH_instance/add_5_root_add_53_G7/U1_27 ( .A(
\BOOTH_instance/decoded[4][31] ), .B(\BOOTH_instance/decoded[5][31] ),
.CI(\BOOTH_instance/add_5_root_add_53_G7/carry[27] ), .CO(
\BOOTH_instance/add_5_root_add_53_G7/carry[28] ), .S(
\BOOTH_instance/partial_products[4][27] ) );
ADDFXL \BOOTH_instance/add_2_root_add_53_G7/U1_26 ( .A(
\BOOTH_instance/partial_products[3][26] ), .B(
\BOOTH_instance/partial_products[4][26] ), .CI(
\BOOTH_instance/add_2_root_add_53_G7/carry[26] ), .CO(
\BOOTH_instance/add_2_root_add_53_G7/carry[27] ), .S(
\BOOTH_instance/partial_products[7][26] ) );
ADDFXL \BOOTH_instance/add_2_root_add_53_G7/U1_25 ( .A(
\BOOTH_instance/partial_products[3][25] ), .B(
\BOOTH_instance/partial_products[4][25] ), .CI(
\BOOTH_instance/add_2_root_add_53_G7/carry[25] ), .CO(
\BOOTH_instance/add_2_root_add_53_G7/carry[26] ), .S(
\BOOTH_instance/partial_products[7][25] ) );
ADDFHXL \BOOTH_instance/add_1_root_add_53_G7/U1_25 ( .A(
\BOOTH_instance/partial_products[5][25] ), .B(
\BOOTH_instance/partial_products[6][25] ), .CI(
\BOOTH_instance/add_1_root_add_53_G7/carry[25] ), .CO(
\BOOTH_instance/add_1_root_add_53_G7/carry[26] ), .S(
\BOOTH_instance/partial_products[8][25] ) );
ADDFXL \BOOTH_instance/add_2_root_add_53_G7/U1_24 ( .A(
\BOOTH_instance/partial_products[3][24] ), .B(
\BOOTH_instance/partial_products[4][24] ), .CI(
\BOOTH_instance/add_2_root_add_53_G7/carry[24] ), .CO(
\BOOTH_instance/add_2_root_add_53_G7/carry[25] ), .S(
\BOOTH_instance/partial_products[7][24] ) );
ADDFXL \BOOTH_instance/add_2_root_add_53_G7/U1_23 ( .A(
\BOOTH_instance/partial_products[3][23] ), .B(
\BOOTH_instance/partial_products[4][23] ), .CI(
\BOOTH_instance/add_2_root_add_53_G7/carry[23] ), .CO(
\BOOTH_instance/add_2_root_add_53_G7/carry[24] ), .S(
\BOOTH_instance/partial_products[7][23] ) );
ADDFHXL \BOOTH_instance/add_1_root_add_53_G7/U1_23 ( .A(
\BOOTH_instance/partial_products[5][23] ), .B(
\BOOTH_instance/partial_products[6][23] ), .CI(
\BOOTH_instance/add_1_root_add_53_G7/carry[23] ), .CO(
\BOOTH_instance/add_1_root_add_53_G7/carry[24] ), .S(
\BOOTH_instance/partial_products[8][23] ) );
ADDFXL \BOOTH_instance/add_2_root_add_53_G7/U1_22 ( .A(
\BOOTH_instance/partial_products[3][22] ), .B(
\BOOTH_instance/partial_products[4][22] ), .CI(
\BOOTH_instance/add_2_root_add_53_G7/carry[22] ), .CO(
\BOOTH_instance/add_2_root_add_53_G7/carry[23] ), .S(
\BOOTH_instance/partial_products[7][22] ) );
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_21 ( .A(
\BOOTH_instance/partial_products[7][21] ), .B(
\BOOTH_instance/partial_products[8][21] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[21] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[22] ), .S(EX_MULT_OUT[21])
);
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_19 ( .A(
\BOOTH_instance/partial_products[7][19] ), .B(
\BOOTH_instance/partial_products[8][19] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[19] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[20] ), .S(EX_MULT_OUT[19])
);
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_17 ( .A(
\BOOTH_instance/partial_products[7][17] ), .B(
\BOOTH_instance/partial_products[8][17] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[17] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[18] ), .S(EX_MULT_OUT[17])
);
ADDFHXL \BOOTH_instance/add_1_root_add_53_G7/U1_16 ( .A(
\BOOTH_instance/partial_products[5][16] ), .B(
\BOOTH_instance/partial_products[6][16] ), .CI(
\BOOTH_instance/add_1_root_add_53_G7/carry[16] ), .CO(
\BOOTH_instance/add_1_root_add_53_G7/carry[17] ), .S(
\BOOTH_instance/partial_products[8][16] ) );
ADDFXL \BOOTH_instance/add_2_root_add_53_G7/U1_15 ( .A(
\BOOTH_instance/partial_products[3][15] ), .B(
\BOOTH_instance/partial_products[4][15] ), .CI(
\BOOTH_instance/add_2_root_add_53_G7/carry[15] ), .CO(
\BOOTH_instance/add_2_root_add_53_G7/carry[16] ), .S(
\BOOTH_instance/partial_products[7][15] ) );
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_14 ( .A(
\BOOTH_instance/partial_products[7][14] ), .B(
\BOOTH_instance/partial_products[8][14] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[14] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[15] ), .S(EX_MULT_OUT[14])
);
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_11 ( .A(
\BOOTH_instance/partial_products[7][11] ), .B(
\BOOTH_instance/partial_products[8][11] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[11] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[12] ), .S(EX_MULT_OUT[11])
);
ADDFXL \BOOTH_instance/add_2_root_add_53_G7/U1_11 ( .A(
\BOOTH_instance/partial_products[3][11] ), .B(
\BOOTH_instance/partial_products[4][11] ), .CI(
\BOOTH_instance/add_2_root_add_53_G7/carry[11] ), .CO(
\BOOTH_instance/add_2_root_add_53_G7/carry[12] ), .S(
\BOOTH_instance/partial_products[7][11] ) );
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_7 ( .A(
\BOOTH_instance/partial_products[7][7] ), .B(
\BOOTH_instance/partial_products[8][7] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[7] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[8] ), .S(EX_MULT_OUT[7]) );
XOR3XL \BOOTH_instance/add_6_root_add_53_G7/U1_31 ( .A(
\BOOTH_instance/decoded[2][31] ), .B(\BOOTH_instance/decoded[3][31] ),
.C(\BOOTH_instance/add_6_root_add_53_G7/carry[31] ), .Y(
\BOOTH_instance/partial_products[3][31] ) );
ADDFXL \BOOTH_instance/add_2_root_add_53_G7/U1_30 ( .A(
\BOOTH_instance/partial_products[3][30] ), .B(
\BOOTH_instance/partial_products[4][30] ), .CI(
\BOOTH_instance/add_2_root_add_53_G7/carry[30] ), .CO(
\BOOTH_instance/add_2_root_add_53_G7/carry[31] ), .S(
\BOOTH_instance/partial_products[7][30] ) );
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_30 ( .A(
\BOOTH_instance/decoded[0][31] ), .B(\BOOTH_instance/decoded[1][31] ),
.CI(\BOOTH_instance/add_7_root_add_53_G7/carry[30] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[31] ), .S(
\BOOTH_instance/partial_products[2][30] ) );
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_29 ( .A(
\BOOTH_instance/decoded[0][31] ), .B(\BOOTH_instance/decoded[1][31] ),
.CI(\BOOTH_instance/add_7_root_add_53_G7/carry[29] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[30] ), .S(
\BOOTH_instance/partial_products[2][29] ) );
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_25 ( .A(
\BOOTH_instance/partial_products[7][25] ), .B(
\BOOTH_instance/partial_products[8][25] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[25] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[26] ), .S(EX_MULT_OUT[25])
);
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_28 ( .A(
\BOOTH_instance/decoded[0][31] ), .B(\BOOTH_instance/decoded[1][31] ),
.CI(\BOOTH_instance/add_7_root_add_53_G7/carry[28] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[29] ), .S(
\BOOTH_instance/partial_products[2][28] ) );
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_27 ( .A(
\BOOTH_instance/decoded[0][31] ), .B(\BOOTH_instance/decoded[1][31] ),
.CI(\BOOTH_instance/add_7_root_add_53_G7/carry[27] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[28] ), .S(
\BOOTH_instance/partial_products[2][27] ) );
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_23 ( .A(
\BOOTH_instance/partial_products[7][23] ), .B(
\BOOTH_instance/partial_products[8][23] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[23] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[24] ), .S(EX_MULT_OUT[23])
);
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_26 ( .A(
\BOOTH_instance/decoded[0][31] ), .B(\BOOTH_instance/decoded[1][31] ),
.CI(\BOOTH_instance/add_7_root_add_53_G7/carry[26] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[27] ), .S(
\BOOTH_instance/partial_products[2][26] ) );
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_25 ( .A(
\BOOTH_instance/decoded[0][31] ), .B(\BOOTH_instance/decoded[1][31] ),
.CI(\BOOTH_instance/add_7_root_add_53_G7/carry[25] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[26] ), .S(
\BOOTH_instance/partial_products[2][25] ) );
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_24 ( .A(
\BOOTH_instance/decoded[0][31] ), .B(\BOOTH_instance/decoded[1][31] ),
.CI(\BOOTH_instance/add_7_root_add_53_G7/carry[24] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[25] ), .S(
\BOOTH_instance/partial_products[2][24] ) );
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_23 ( .A(
\BOOTH_instance/decoded[0][31] ), .B(\BOOTH_instance/decoded[1][31] ),
.CI(\BOOTH_instance/add_7_root_add_53_G7/carry[23] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[24] ), .S(
\BOOTH_instance/partial_products[2][23] ) );
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_22 ( .A(
\BOOTH_instance/decoded[0][31] ), .B(\BOOTH_instance/decoded[1][31] ),
.CI(\BOOTH_instance/add_7_root_add_53_G7/carry[22] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[23] ), .S(
\BOOTH_instance/partial_products[2][22] ) );
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_20 ( .A(
\BOOTH_instance/decoded[0][31] ), .B(\BOOTH_instance/decoded[1][31] ),
.CI(\BOOTH_instance/add_7_root_add_53_G7/carry[20] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[21] ), .S(
\BOOTH_instance/partial_products[2][20] ) );
XOR3XL \BOOTH_instance/add_7_root_add_53_G7/U1_31 ( .A(
\BOOTH_instance/decoded[0][31] ), .B(\BOOTH_instance/decoded[1][31] ),
.C(\BOOTH_instance/add_7_root_add_53_G7/carry[31] ), .Y(
\BOOTH_instance/partial_products[2][31] ) );
ADDFHX2 \BOOTH_instance/add_7_root_add_53_G7/U1_10 ( .A(
\BOOTH_instance/N219 ), .B(\BOOTH_instance/decoded[1][10] ), .CI(
\BOOTH_instance/add_7_root_add_53_G7/carry[10] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[11] ), .S(
\BOOTH_instance/partial_products[8][10] ) );
ADDFHX2 \BOOTH_instance/add_7_root_add_53_G7/U1_12 ( .A(
\BOOTH_instance/N221 ), .B(\BOOTH_instance/decoded[1][12] ), .CI(
\BOOTH_instance/add_7_root_add_53_G7/carry[12] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[13] ), .S(
\BOOTH_instance/partial_products[6][12] ) );
ADDFHX1 \BOOTH_instance/add_3_root_add_53_G7/U1_17 ( .A(
\BOOTH_instance/decoded[8][17] ), .B(
\BOOTH_instance/partial_products[2][17] ), .CI(
\BOOTH_instance/add_3_root_add_53_G7/carry[17] ), .CO(
\BOOTH_instance/add_3_root_add_53_G7/carry[18] ), .S(
\BOOTH_instance/partial_products[6][17] ) );
ADDFHX2 \BOOTH_instance/add_7_root_add_53_G7/U1_16 ( .A(
\BOOTH_instance/N225 ), .B(\BOOTH_instance/decoded[1][16] ), .CI(
\BOOTH_instance/add_7_root_add_53_G7/carry[16] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[17] ), .S(
\BOOTH_instance/partial_products[2][16] ) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[29] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4889), .E(1'b1), .CK(CLOCK__L3_N6), .Q(
PORT_ALU[29]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[30] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4890), .E(1'b1), .CK(CLOCK__L3_N6), .Q(
PORT_ALU[30]) );
EDFFTRXL \EX_MEM_OUT_REG_instance/Q_reg[31] ( .RN(
\EX_MEM_OUT_REG_instance/n34 ), .D(N4891), .E(1'b1), .CK(CLOCK__L3_N4), .Q(
PORT_ALU[31]) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_12 ( .A(
\BOOTH_instance/decoded[2][12] ), .B(\BOOTH_instance/decoded[3][12] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[12] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[13] ), .S(
\BOOTH_instance/partial_products[3][12] ) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_8 ( .A(
\BOOTH_instance/decoded[2][8] ), .B(\BOOTH_instance/decoded[3][8] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[8] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[9] ), .S(
\BOOTH_instance/partial_products[3][8] ) );
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_12 ( .A(
\BOOTH_instance/partial_products[7][12] ), .B(
\BOOTH_instance/partial_products[8][12] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[12] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[13] ), .S(EX_MULT_OUT[12])
);
ADDFXL \BOOTH_instance/add_2_root_add_53_G7/U1_12 ( .A(
\BOOTH_instance/partial_products[3][12] ), .B(
\BOOTH_instance/partial_products[4][12] ), .CI(
\BOOTH_instance/add_2_root_add_53_G7/carry[12] ), .CO(
\BOOTH_instance/add_2_root_add_53_G7/carry[13] ), .S(
\BOOTH_instance/partial_products[7][12] ) );
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_9 ( .A(
\BOOTH_instance/partial_products[7][9] ), .B(
\BOOTH_instance/partial_products[8][9] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[9] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[10] ), .S(EX_MULT_OUT[9])
);
ADDFXL \BOOTH_instance/add_2_root_add_53_G7/U1_16 ( .A(
\BOOTH_instance/partial_products[3][16] ), .B(
\BOOTH_instance/partial_products[4][16] ), .CI(
\BOOTH_instance/add_2_root_add_53_G7/carry[16] ), .CO(
\BOOTH_instance/add_2_root_add_53_G7/carry[17] ), .S(
\BOOTH_instance/partial_products[7][16] ) );
ADDFHXL \BOOTH_instance/add_1_root_add_53_G7/U1_14 ( .A(
\BOOTH_instance/partial_products[5][14] ), .B(
\BOOTH_instance/partial_products[6][14] ), .CI(
\BOOTH_instance/add_1_root_add_53_G7/carry[14] ), .CO(
\BOOTH_instance/add_1_root_add_53_G7/carry[15] ), .S(
\BOOTH_instance/partial_products[8][14] ) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_20 ( .A(
\BOOTH_instance/decoded[2][20] ), .B(\BOOTH_instance/decoded[3][20] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[20] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[21] ), .S(
\BOOTH_instance/partial_products[3][20] ) );
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_15 ( .A(
\BOOTH_instance/partial_products[7][15] ), .B(
\BOOTH_instance/partial_products[8][15] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[15] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[16] ), .S(EX_MULT_OUT[15])
);
ADDFXL \BOOTH_instance/add_2_root_add_53_G7/U1_21 ( .A(
\BOOTH_instance/partial_products[3][21] ), .B(
\BOOTH_instance/partial_products[4][21] ), .CI(
\BOOTH_instance/add_2_root_add_53_G7/carry[21] ), .CO(
\BOOTH_instance/add_2_root_add_53_G7/carry[22] ), .S(
\BOOTH_instance/partial_products[7][21] ) );
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_16 ( .A(
\BOOTH_instance/partial_products[7][16] ), .B(
\BOOTH_instance/partial_products[8][16] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[16] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[17] ), .S(EX_MULT_OUT[16])
);
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_18 ( .A(
\BOOTH_instance/partial_products[7][18] ), .B(
\BOOTH_instance/partial_products[8][18] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[18] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[19] ), .S(EX_MULT_OUT[18])
);
ADDFHX1 \BOOTH_instance/add_0_root_add_53_G7/U1_27 ( .A(
\BOOTH_instance/partial_products[7][27] ), .B(
\BOOTH_instance/partial_products[8][27] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[27] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[28] ), .S(EX_MULT_OUT[27])
);
ADDFXL \BOOTH_instance/add_2_root_add_53_G7/U1_29 ( .A(
\BOOTH_instance/partial_products[3][29] ), .B(
\BOOTH_instance/partial_products[4][29] ), .CI(
\BOOTH_instance/add_2_root_add_53_G7/carry[29] ), .CO(
\BOOTH_instance/add_2_root_add_53_G7/carry[30] ), .S(
\BOOTH_instance/partial_products[7][29] ) );
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_28 ( .A(
\BOOTH_instance/partial_products[7][28] ), .B(
\BOOTH_instance/partial_products[8][28] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[28] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[29] ), .S(EX_MULT_OUT[28])
);
ADDFXL \BOOTH_instance/add_2_root_add_53_G7/U1_27 ( .A(
\BOOTH_instance/partial_products[3][27] ), .B(
\BOOTH_instance/partial_products[4][27] ), .CI(
\BOOTH_instance/add_2_root_add_53_G7/carry[27] ), .CO(
\BOOTH_instance/add_2_root_add_53_G7/carry[28] ), .S(
\BOOTH_instance/partial_products[7][27] ) );
ADDFXL \BOOTH_instance/add_2_root_add_53_G7/U1_28 ( .A(
\BOOTH_instance/partial_products[3][28] ), .B(
\BOOTH_instance/partial_products[4][28] ), .CI(
\BOOTH_instance/add_2_root_add_53_G7/carry[28] ), .CO(
\BOOTH_instance/add_2_root_add_53_G7/carry[29] ), .S(
\BOOTH_instance/partial_products[7][28] ) );
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_29 ( .A(
\BOOTH_instance/partial_products[7][29] ), .B(
\BOOTH_instance/partial_products[8][29] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[29] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[30] ), .S(EX_MULT_OUT[29])
);
ADDFXL \BOOTH_instance/add_2_root_add_53_G7/U1_9 ( .A(
\BOOTH_instance/partial_products[3][9] ), .B(
\BOOTH_instance/partial_products[4][9] ), .CI(
\BOOTH_instance/add_2_root_add_53_G7/carry[9] ), .CO(
\BOOTH_instance/add_2_root_add_53_G7/carry[10] ), .S(
\BOOTH_instance/partial_products[7][9] ) );
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_13 ( .A(
\BOOTH_instance/partial_products[7][13] ), .B(
\BOOTH_instance/partial_products[8][13] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[13] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[14] ), .S(EX_MULT_OUT[13])
);
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_16 ( .A(
\BOOTH_instance/decoded[2][16] ), .B(\BOOTH_instance/decoded[3][16] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[16] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[17] ), .S(
\BOOTH_instance/partial_products[3][16] ) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_14 ( .A(
\BOOTH_instance/decoded[2][14] ), .B(\BOOTH_instance/decoded[3][14] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[14] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[15] ), .S(
\BOOTH_instance/partial_products[3][14] ) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_17 ( .A(
\BOOTH_instance/decoded[2][17] ), .B(\BOOTH_instance/decoded[3][17] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[17] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[18] ), .S(
\BOOTH_instance/partial_products[3][17] ) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_10 ( .A(
\BOOTH_instance/decoded[2][10] ), .B(\BOOTH_instance/decoded[3][10] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[10] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[11] ), .S(
\BOOTH_instance/partial_products[3][10] ) );
ADDFXL \BOOTH_instance/add_2_root_add_53_G7/U1_13 ( .A(
\BOOTH_instance/partial_products[3][13] ), .B(
\BOOTH_instance/partial_products[4][13] ), .CI(
\BOOTH_instance/add_2_root_add_53_G7/carry[13] ), .CO(
\BOOTH_instance/add_2_root_add_53_G7/carry[14] ), .S(
\BOOTH_instance/partial_products[7][13] ) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_19 ( .A(
\BOOTH_instance/decoded[2][19] ), .B(\BOOTH_instance/decoded[3][19] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[19] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[20] ), .S(
\BOOTH_instance/partial_products[3][19] ) );
ADDFXL \BOOTH_instance/add_2_root_add_53_G7/U1_19 ( .A(
\BOOTH_instance/partial_products[3][19] ), .B(
\BOOTH_instance/partial_products[4][19] ), .CI(
\BOOTH_instance/add_2_root_add_53_G7/carry[19] ), .CO(
\BOOTH_instance/add_2_root_add_53_G7/carry[20] ), .S(
\BOOTH_instance/partial_products[7][19] ) );
SNPS_CLOCK_GATE_HIGH_DLX_0 \clk_gate_IF_ID_INSTR_REG_instance/Q_reg ( .CLK(CLOCK__L3_N17), .EN(n1623), .ENCLK(n1625), .TE(1'b0) );
DFFRQXL \IF_STALL_REG_instance/Q_reg ( .D(
\ID_EX_IMM16_EXT_REG_instance/n34 ), .CK(CLOCK__L3_N15), .RN(1'b1), .Q(
IF_STALL_SEL) );
EDFFTRXL \EX_MEM_INSTR_REG_instance/Q_reg[31] ( .RN(
\ID_EX_REGA_REG_instance/n34 ), .D(EX_INSTR[31]), .E(1'b1), .CK(CLOCK__L3_N13),
.Q(MEM_INSTR[31]), .QN(n1409) );
EDFFTRXL \PC_instance/Q_reg[5] ( .RN(\PC_instance/n33 ), .D(N735), .E(n697),
.CK(n1625), .Q(PORT_PC[5]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[26] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[26]), .E(1'b1),
.CK(CLOCK__L3_N13), .Q(EX_INSTR[26]), .QN(n1610) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[30] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[30]), .E(1'b1),
.CK(CLOCK__L3_N13), .Q(EX_INSTR[30]), .QN(n1608) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[29] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[29]), .E(1'b1),
.CK(CLOCK__L3_N17), .Q(EX_INSTR[29]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[28] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[28]), .E(1'b1),
.CK(CLOCK__L3_N13), .Q(EX_INSTR[28]) );
EDFFTRXL \ID_EX_INSTR_REG_instance/Q_reg[27] ( .RN(
\ID_EX_INSTR_REG_instance/n34 ), .D(ID_INSTR_AFTER_CU[27]), .E(1'b1),
.CK(CLOCK__L3_N13), .Q(EX_INSTR[27]) );
EDFFXL \ID_EX_INSTR_REG_instance/Q_reg[31] ( .D(n1621), .E(1'b1), .CK(CLOCK__L3_N13), .Q(EX_INSTR[31]), .QN(n1566) );
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_20 ( .A(
\BOOTH_instance/partial_products[7][20] ), .B(
\BOOTH_instance/partial_products[8][20] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[20] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[21] ), .S(EX_MULT_OUT[20])
);
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_22 ( .A(
\BOOTH_instance/partial_products[7][22] ), .B(
\BOOTH_instance/partial_products[8][22] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[22] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[23] ), .S(EX_MULT_OUT[22])
);
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_24 ( .A(
\BOOTH_instance/partial_products[7][24] ), .B(
\BOOTH_instance/partial_products[8][24] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[24] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[25] ), .S(EX_MULT_OUT[24])
);
ADDFXL \BOOTH_instance/add_0_root_add_53_G7/U1_26 ( .A(
\BOOTH_instance/partial_products[7][26] ), .B(
\BOOTH_instance/partial_products[8][26] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[26] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[27] ), .S(EX_MULT_OUT[26])
);
ADDFHX1 \BOOTH_instance/add_0_root_add_53_G7/U1_30 ( .A(
\BOOTH_instance/partial_products[7][30] ), .B(
\BOOTH_instance/partial_products[8][30] ), .CI(
\BOOTH_instance/add_0_root_add_53_G7/carry[30] ), .CO(
\BOOTH_instance/add_0_root_add_53_G7/carry[31] ), .S(EX_MULT_OUT[30])
);
ADDFHXL \BOOTH_instance/add_1_root_add_53_G7/U1_17 ( .A(
\BOOTH_instance/partial_products[5][17] ), .B(
\BOOTH_instance/partial_products[6][17] ), .CI(
\BOOTH_instance/add_1_root_add_53_G7/carry[17] ), .CO(
\BOOTH_instance/add_1_root_add_53_G7/carry[18] ), .S(
\BOOTH_instance/partial_products[8][17] ) );
ADDFHXL \BOOTH_instance/add_1_root_add_53_G7/U1_19 ( .A(
\BOOTH_instance/partial_products[5][19] ), .B(
\BOOTH_instance/partial_products[6][19] ), .CI(
\BOOTH_instance/add_1_root_add_53_G7/carry[19] ), .CO(
\BOOTH_instance/add_1_root_add_53_G7/carry[20] ), .S(
\BOOTH_instance/partial_products[8][19] ) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_30 ( .A(
\BOOTH_instance/decoded[2][31] ), .B(\BOOTH_instance/decoded[3][31] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[30] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[31] ), .S(
\BOOTH_instance/partial_products[3][30] ) );
ADDFHX1 \BOOTH_instance/add_7_root_add_53_G7/U1_13 ( .A(
\BOOTH_instance/N222 ), .B(\BOOTH_instance/decoded[1][13] ), .CI(
\BOOTH_instance/add_7_root_add_53_G7/carry[13] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[14] ), .S(
\BOOTH_instance/partial_products[6][13] ) );
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_15 ( .A(
\BOOTH_instance/N224 ), .B(\BOOTH_instance/decoded[1][15] ), .CI(
\BOOTH_instance/add_7_root_add_53_G7/carry[15] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[16] ), .S(
\BOOTH_instance/partial_products[6][15] ) );
ADDFHXL \BOOTH_instance/add_3_root_add_53_G7/U1_20 ( .A(
\BOOTH_instance/decoded[8][20] ), .B(
\BOOTH_instance/partial_products[2][20] ), .CI(
\BOOTH_instance/add_3_root_add_53_G7/carry[20] ), .CO(
\BOOTH_instance/add_3_root_add_53_G7/carry[21] ), .S(
\BOOTH_instance/partial_products[6][20] ) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_21 ( .A(
\BOOTH_instance/decoded[2][31] ), .B(\BOOTH_instance/decoded[3][21] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[21] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[22] ), .S(
\BOOTH_instance/partial_products[3][21] ) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_23 ( .A(
\BOOTH_instance/decoded[2][31] ), .B(\BOOTH_instance/decoded[3][31] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[23] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[24] ), .S(
\BOOTH_instance/partial_products[3][23] ) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_24 ( .A(
\BOOTH_instance/decoded[2][31] ), .B(\BOOTH_instance/decoded[3][31] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[24] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[25] ), .S(
\BOOTH_instance/partial_products[3][24] ) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_25 ( .A(
\BOOTH_instance/decoded[2][31] ), .B(\BOOTH_instance/decoded[3][31] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[25] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[26] ), .S(
\BOOTH_instance/partial_products[3][25] ) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_26 ( .A(
\BOOTH_instance/decoded[2][31] ), .B(\BOOTH_instance/decoded[3][31] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[26] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[27] ), .S(
\BOOTH_instance/partial_products[3][26] ) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_27 ( .A(
\BOOTH_instance/decoded[2][31] ), .B(\BOOTH_instance/decoded[3][31] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[27] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[28] ), .S(
\BOOTH_instance/partial_products[3][27] ) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_28 ( .A(
\BOOTH_instance/decoded[2][31] ), .B(\BOOTH_instance/decoded[3][31] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[28] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[29] ), .S(
\BOOTH_instance/partial_products[3][28] ) );
ADDFXL \BOOTH_instance/add_6_root_add_53_G7/U1_29 ( .A(
\BOOTH_instance/decoded[2][31] ), .B(\BOOTH_instance/decoded[3][31] ),
.CI(\BOOTH_instance/add_6_root_add_53_G7/carry[29] ), .CO(
\BOOTH_instance/add_6_root_add_53_G7/carry[30] ), .S(
\BOOTH_instance/partial_products[3][29] ) );
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_18 ( .A(
\BOOTH_instance/decoded[0][31] ), .B(\BOOTH_instance/decoded[1][18] ),
.CI(\BOOTH_instance/add_7_root_add_53_G7/carry[18] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[19] ), .S(
\BOOTH_instance/partial_products[2][18] ) );
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_21 ( .A(
\BOOTH_instance/decoded[0][31] ), .B(\BOOTH_instance/decoded[1][31] ),
.CI(\BOOTH_instance/add_7_root_add_53_G7/carry[21] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[22] ), .S(
\BOOTH_instance/partial_products[2][21] ) );
ADDFHX1 \BOOTH_instance/add_3_root_add_53_G7/U1_18 ( .A(
\BOOTH_instance/decoded[8][18] ), .B(
\BOOTH_instance/partial_products[2][18] ), .CI(
\BOOTH_instance/add_3_root_add_53_G7/carry[18] ), .CO(
\BOOTH_instance/add_3_root_add_53_G7/carry[19] ), .S(
\BOOTH_instance/partial_products[6][18] ) );
ADDFHXL \BOOTH_instance/add_7_root_add_53_G7/U1_19 ( .A(
\BOOTH_instance/decoded[0][31] ), .B(\BOOTH_instance/decoded[1][31] ),
.CI(\BOOTH_instance/add_7_root_add_53_G7/carry[19] ), .CO(
\BOOTH_instance/add_7_root_add_53_G7/carry[20] ), .S(
\BOOTH_instance/partial_products[2][19] ) );
NAND3XL U1339 ( .A(n2155), .B(n2172), .C(n690), .Y(\BOOTH_instance/n434 ) );
INVXL U1340 ( .A(\BOOTH_instance/n434 ), .Y(\BOOTH_instance/n424 ) );
XOR2X1 U1341 ( .A(N4723), .B(\BOOTH_instance/n457 ), .Y(
\BOOTH_instance/n269 ) );
AND4X1 U1342 ( .A(n1570), .B(n1377), .C(n1571), .D(n1572), .Y(n1591) );
NOR2XL U1343 ( .A(n2158), .B(n2170), .Y(n1592) );
CLKNAND2X2 U1344 ( .A(n2159), .B(n2155), .Y(\BOOTH_instance/n445 ) );
INVX1 U1345 ( .A(n1644), .Y(n2189) );
AND2X1 U1346 ( .A(n1632), .B(n1633), .Y(n1644) );
AO22X1 U1347 ( .A0(EX_PC[3]), .A1(n2139), .B0(EX_REGA[3]), .B1(n2137), .Y(
N4721) );
XOR2X1 U1348 ( .A(\BOOTH_instance/n459 ), .B(n2187), .Y(
\BOOTH_instance/n299 ) );
CLKINVX2 U1349 ( .A(n1607), .Y(n1598) );
INVXL U1350 ( .A(\BOOTH_instance/n269 ), .Y(n1593) );
AND2XL U1351 ( .A(\BOOTH_instance/decoded[2][6] ), .B(
\BOOTH_instance/decoded[3][6] ), .Y(
\BOOTH_instance/add_6_root_add_53_G7/carry[7] ) );
NAND2XL U1352 ( .A(n2188), .B(\BOOTH_instance/n460 ), .Y(n1631) );
XNOR2XL U1353 ( .A(N4831), .B(n2172), .Y(\BOOTH_instance/n419 ) );
INVXL U1354 ( .A(N4721), .Y(n2188) );
NAND2XL U1355 ( .A(n2170), .B(\BOOTH_instance/n443 ), .Y(
\BOOTH_instance/n422 ) );
INVX3 U1356 ( .A(n2162), .Y(n2159) );
NAND2XL U1357 ( .A(n1627), .B(n1628), .Y(\BOOTH_instance/n405 ) );
OAI221XL U1358 ( .A0(\BOOTH_instance/n307 ), .A1(\BOOTH_instance/n421 ),
.B0(\BOOTH_instance/n308 ), .B1(\BOOTH_instance/n422 ), .C0(
\BOOTH_instance/n432 ), .Y(\BOOTH_instance/decoded[1][3] ) );
AO22XL U1359 ( .A0(EX_PC[1]), .A1(n2139), .B0(EX_REGA[1]), .B1(n2137), .Y(
n2112) );
NOR2XL U1360 ( .A(n1599), .B(n2170), .Y(n1594) );
NOR2XL U1361 ( .A(n2158), .B(n2170), .Y(n1595) );
NOR2XL U1362 ( .A(EX_ALU_SEL[0]), .B(EX_ALU_SEL[1]), .Y(n1596) );
AOI21BXL U1363 ( .A0(EX_IMM16_EXT[3]), .A1(n2150), .B0N(n1352), .Y(n1597) );
AO2B2XL U1364 ( .B0(EX_REGB[2]), .B1(n1189), .A0(n2150), .A1N(n1660), .Y(
n690) );
OR2XL U1365 ( .A(\BOOTH_instance/n398 ), .B(\BOOTH_instance/n290 ), .Y(n1628) );
OAI222X2 U1366 ( .A0(\BOOTH_instance/n290 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n20 ), .B0(\BOOTH_instance/n280 ),
.B1(\BOOTH_instance/n445 ), .C0(n2188), .C1(\BOOTH_instance/n447 ),
.Y(\BOOTH_instance/N212 ) );
OAI222X2 U1367 ( .A0(\BOOTH_instance/n308 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n20 ), .B0(\BOOTH_instance/n290 ),
.B1(\BOOTH_instance/n445 ), .C0(n1644), .C1(\BOOTH_instance/n447 ),
.Y(\BOOTH_instance/N211 ) );
NAND2X1 U1368 ( .A(n2159), .B(n1607), .Y(\BOOTH_instance/n447 ) );
OAI222XL U1369 ( .A0(\BOOTH_instance/n280 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n20 ), .B0(\BOOTH_instance/n299 ),
.B1(\BOOTH_instance/n445 ), .C0(n2187), .C1(\BOOTH_instance/n447 ),
.Y(\BOOTH_instance/N213 ) );
OAI222XL U1370 ( .A0(\BOOTH_instance/n299 ), .A1(n2125), .B0(
\BOOTH_instance/n269 ), .B1(\BOOTH_instance/n445 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n46 ), .C1(\BOOTH_instance/n447 ),
.Y(\BOOTH_instance/N214 ) );
OAI222XL U1371 ( .A0(\BOOTH_instance/n269 ), .A1(n2124), .B0(
\BOOTH_instance/n259 ), .B1(\BOOTH_instance/n445 ), .C0(
\BOOTH_instance/n260 ), .C1(\BOOTH_instance/n447 ), .Y(
\BOOTH_instance/N215 ) );
CLKINVX1 U1372 ( .A(n2142), .Y(n2141) );
CLKINVX1 U1373 ( .A(n1351), .Y(n2142) );
INVXL U1374 ( .A(n1607), .Y(n2155) );
INVXL U1375 ( .A(n2158), .Y(n1599) );
CLKINVX1 U1376 ( .A(n2158), .Y(n2156) );
NAND2BXL U1377 ( .AN(n2159), .B(n2155), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n20 ) );
NOR2XL U1378 ( .A(n1608), .B(n1626), .Y(n1584) );
XOR2XL U1379 ( .A(\BOOTH_instance/n458 ), .B(\BOOTH_instance/n260 ), .Y(
\BOOTH_instance/n259 ) );
INVXL U1380 ( .A(n688), .Y(n2162) );
AND4XL U1381 ( .A(n1545), .B(n1541), .C(n1543), .D(n1538), .Y(n1551) );
NOR2XL U1382 ( .A(n1566), .B(n1610), .Y(n1573) );
NOR2XL U1383 ( .A(n1609), .B(EX_INSTR[27]), .Y(n1563) );
INVXL U1384 ( .A(N4728), .Y(n2180) );
AO22XL U1385 ( .A0(EX_PC[6]), .A1(n2139), .B0(EX_REGA[6]), .B1(n2137), .Y(
N4724) );
CLKBUFX1 U1386 ( .A(n1189), .Y(n2149) );
AO22XL U1387 ( .A0(EX_PC[5]), .A1(n2139), .B0(EX_REGA[5]), .B1(n2137), .Y(
N4723) );
NAND2XL U1388 ( .A(\BOOTH_instance/n419 ), .B(\BOOTH_instance/n396 ), .Y(
\BOOTH_instance/n397 ) );
NAND2XL U1389 ( .A(N4832), .B(\BOOTH_instance/n419 ), .Y(
\BOOTH_instance/n398 ) );
AO22XL U1390 ( .A0(EX_PC[1]), .A1(n2139), .B0(EX_REGA[1]), .B1(n2137), .Y(
n2113) );
AO22XL U1391 ( .A0(EX_PC[1]), .A1(n2139), .B0(EX_REGA[1]), .B1(n2137), .Y(
N4719) );
AO22XL U1392 ( .A0(EX_IMM16_EXT[30]), .A1(n2150), .B0(EX_REGB[30]), .B1(
n2148), .Y(N4857) );
AO22XL U1393 ( .A0(EX_IMM16_EXT[29]), .A1(n2150), .B0(EX_REGB[29]), .B1(
n2148), .Y(N4856) );
AO22XL U1394 ( .A0(EX_IMM16_EXT[28]), .A1(n2150), .B0(EX_REGB[28]), .B1(
n2148), .Y(N4855) );
AO22XL U1395 ( .A0(EX_IMM16_EXT[27]), .A1(n2150), .B0(EX_REGB[27]), .B1(
n2148), .Y(N4854) );
AO22XL U1396 ( .A0(EX_IMM16_EXT[26]), .A1(n2150), .B0(EX_REGB[26]), .B1(
n2148), .Y(N4853) );
AO22XL U1397 ( .A0(EX_IMM16_EXT[25]), .A1(n2150), .B0(EX_REGB[25]), .B1(
n2148), .Y(N4852) );
AO22XL U1398 ( .A0(EX_IMM16_EXT[24]), .A1(n2150), .B0(EX_REGB[24]), .B1(
n2148), .Y(N4851) );
AO22XL U1399 ( .A0(EX_IMM16_EXT[23]), .A1(n2150), .B0(EX_REGB[23]), .B1(
n2148), .Y(N4850) );
AO22XL U1400 ( .A0(EX_IMM16_EXT[22]), .A1(n2150), .B0(EX_REGB[22]), .B1(
n2148), .Y(N4849) );
NAND2BXL U1401 ( .AN(n2153), .B(\PC_instance/n33 ), .Y(n1623) );
NOR2BXL U1402 ( .AN(\ID_EX_INSTR_REG_instance/n34 ), .B(n1620), .Y(n1621) );
INVXL U1403 ( .A(ID_INSTR_AFTER_CU[31]), .Y(n1620) );
AOI221XL U1404 ( .A0(N4719), .A1(\BOOTH_instance/n400 ), .B0(
\BOOTH_instance/n320 ), .B1(\BOOTH_instance/n401 ), .C0(
\BOOTH_instance/n405 ), .Y(\BOOTH_instance/n404 ) );
NAND2XL U1405 ( .A(N4840), .B(\BOOTH_instance/n322 ), .Y(n1603) );
AOI22XL U1406 ( .A0(EX_PC[7]), .A1(n2139), .B0(EX_REGA[7]), .B1(n2137), .Y(
n1604) );
AOI22XL U1407 ( .A0(EX_PC[13]), .A1(n2140), .B0(EX_REGA[13]), .B1(n2138),
.Y(n1605) );
OAI21XL U1408 ( .A0(\BOOTH_instance/n448 ), .A1(\BOOTH_instance/n156 ), .B0(
\BOOTH_instance/n151 ), .Y(n1606) );
AOI22XL U1409 ( .A0(EX_IMM16_EXT[1]), .A1(n2150), .B0(EX_REGB[1]), .B1(n1189), .Y(n1607) );
OR2XL U1410 ( .A(EX_INSTR[30]), .B(EX_INSTR[29]), .Y(n1609) );
INVXL U1411 ( .A(n1696), .Y(\BOOTH_instance/n425 ) );
INVXL U1412 ( .A(n1695), .Y(\BOOTH_instance/n401 ) );
INVXL U1413 ( .A(n1705), .Y(n1374) );
NOR2XL U1414 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n88 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n89 ), .Y(n1611) );
NOR2XL U1415 ( .A(EX_SHIFTER_CW[1]), .B(\ALU_instance/SHIFTER_GENERIC_I/n88 ), .Y(n1612) );
NOR2XL U1416 ( .A(EX_SHIFTER_CW[1]), .B(EX_SHIFTER_CW[0]), .Y(n1613) );
INVXL U1417 ( .A(n2164), .Y(n2163) );
AO22XL U1418 ( .A0(EX_PC[5]), .A1(n2139), .B0(EX_REGA[5]), .B1(n2137), .Y(
n2114) );
AO22XL U1419 ( .A0(EX_PC[6]), .A1(n2139), .B0(EX_REGA[6]), .B1(n2137), .Y(
n2116) );
NOR2XL U1420 ( .A(n1309), .B(n1310), .Y(n1614) );
NAND3XL U1421 ( .A(n320), .B(n319), .C(n321), .Y(n1615) );
NOR2XL U1422 ( .A(n2146), .B(n1330), .Y(n1616) );
XOR2XL U1427 ( .A(n2189), .B(\BOOTH_instance/n461 ), .Y(
\BOOTH_instance/n290 ) );
NAND2XL U1428 ( .A(n1566), .B(EX_INSTR[26]), .Y(n1626) );
OR2XL U1429 ( .A(\BOOTH_instance/n397 ), .B(n1644), .Y(n1627) );
XNOR3XL U1430 ( .A(\BOOTH_instance/partial_products[3][31] ), .B(n1637), .C(
\BOOTH_instance/add_2_root_add_53_G7/carry[31] ), .Y(
\BOOTH_instance/partial_products[7][31] ) );
OAI221XL U1431 ( .A0(n2188), .A1(\BOOTH_instance/n397 ), .B0(
\BOOTH_instance/n280 ), .B1(\BOOTH_instance/n398 ), .C0(
\BOOTH_instance/n403 ), .Y(\BOOTH_instance/decoded[2][7] ) );
INVXL U1432 ( .A(n1568), .Y(n1399) );
OAI2BB2XL U1433 ( .B0(n2167), .B1(\ALU_instance/LOGIC_GENERIC_I/n49 ), .A0N(
N4831), .A1N(n1639), .Y(\ALU_instance/LOGIC_OUT[4] ) );
NOR2XL U1434 ( .A(n1398), .B(EX_INSTR[28]), .Y(n1581) );
NAND3XL U1435 ( .A(n1397), .B(EX_INSTR[27]), .C(n1399), .Y(n1525) );
NOR2XL U1436 ( .A(n1576), .B(EX_INSTR[27]), .Y(n1580) );
INVXL U1437 ( .A(EX_INSTR[27]), .Y(n1398) );
NAND2XL U1438 ( .A(\BOOTH_instance/n443 ), .B(n1597), .Y(
\BOOTH_instance/n421 ) );
INVXL U1439 ( .A(n2158), .Y(n2157) );
NOR3XL U1440 ( .A(n2113), .B(n2189), .C(n2109), .Y(\BOOTH_instance/n460 ) );
CLKBUFX1 U1441 ( .A(n1355), .Y(n2137) );
CLKBUFX1 U1442 ( .A(n1355), .Y(n2138) );
INVX4 U1443 ( .A(n1591), .Y(n2150) );
AOI211XL U1444 ( .A0(n1547), .A1(n1563), .B0(n2150), .C0(n1564), .Y(n1353)
);
AOI22XL U1445 ( .A0(\BOOTH_instance/n400 ), .A1(N4721), .B0(
\BOOTH_instance/n401 ), .B1(\BOOTH_instance/n292 ), .Y(
\BOOTH_instance/n402 ) );
NOR2XL U1446 ( .A(n2150), .B(n1353), .Y(n1189) );
AO22XL U1447 ( .A0(EX_PC[16]), .A1(n2140), .B0(EX_REGA[16]), .B1(n2138), .Y(
n1681) );
AO22XL U1448 ( .A0(EX_PC[22]), .A1(n2140), .B0(EX_REGA[22]), .B1(n2138), .Y(
n1684) );
AO22XL U1449 ( .A0(EX_PC[17]), .A1(n2140), .B0(EX_REGA[17]), .B1(n2138), .Y(
n1676) );
AO22XL U1450 ( .A0(EX_PC[23]), .A1(n2140), .B0(EX_REGA[23]), .B1(n2138), .Y(
n1675) );
AO22XL U1451 ( .A0(EX_PC[21]), .A1(n2140), .B0(EX_REGA[21]), .B1(n2138), .Y(
n1683) );
AO22XL U1452 ( .A0(EX_PC[20]), .A1(n2140), .B0(EX_REGA[20]), .B1(n2138), .Y(
n1680) );
AO22XL U1453 ( .A0(EX_PC[18]), .A1(n2140), .B0(EX_REGA[18]), .B1(n2138), .Y(
n1686) );
AO22XL U1454 ( .A0(EX_PC[19]), .A1(n2140), .B0(EX_REGA[19]), .B1(n2138), .Y(
n1685) );
NAND2XL U1455 ( .A(n1630), .B(n1631), .Y(\BOOTH_instance/n280 ) );
NAND2XL U1456 ( .A(N4721), .B(n1629), .Y(n1630) );
INVXL U1457 ( .A(\BOOTH_instance/n460 ), .Y(n1629) );
NAND2XL U1458 ( .A(EX_PC[2]), .B(n2139), .Y(n1632) );
NAND2XL U1459 ( .A(EX_REGA[2]), .B(n2137), .Y(n1633) );
INVXL U1460 ( .A(\BOOTH_instance/n408 ), .Y(\BOOTH_instance/n400 ) );
NOR2XL U1461 ( .A(\BOOTH_instance/n459 ), .B(n2186), .Y(
\BOOTH_instance/n457 ) );
INVXL U1462 ( .A(n1355), .Y(n2139) );
AOI22XL U1463 ( .A0(\BOOTH_instance/n400 ), .A1(n2189), .B0(
\BOOTH_instance/n401 ), .B1(\BOOTH_instance/n310 ), .Y(
\BOOTH_instance/n403 ) );
CLKBUFX1 U1464 ( .A(n2149), .Y(n2148) );
INVXL U1465 ( .A(n1597), .Y(n2170) );
NAND3XL U1466 ( .A(n2170), .B(\BOOTH_instance/n396 ), .C(n2163), .Y(
\BOOTH_instance/n408 ) );
INVXL U1467 ( .A(\BOOTH_instance/n320 ), .Y(\BOOTH_instance/n308 ) );
OR2XL U1468 ( .A(n2159), .B(n1598), .Y(n1640) );
AO22XL U1469 ( .A0(n2191), .A1(n2187), .B0(n2186), .B1(EX_LOGIC_CW[3]), .Y(
n1639) );
XNOR2XL U1470 ( .A(n2112), .B(\BOOTH_instance/n316 ), .Y(
\BOOTH_instance/n320 ) );
NOR2XL U1471 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N202 ), .B(n2112), .Y(
\BOOTH_instance/n461 ) );
NOR2XL U1472 ( .A(n1565), .B(n1610), .Y(n1397) );
AOI211XL U1473 ( .A0(n1569), .A1(n1573), .B0(n1574), .C0(n1558), .Y(n1572)
);
INVXL U1474 ( .A(N4832), .Y(\BOOTH_instance/n396 ) );
INVXL U1475 ( .A(n1535), .Y(n1570) );
INVXL U1476 ( .A(N4722), .Y(n2187) );
CLKBUFX1 U1477 ( .A(n1597), .Y(n2172) );
AO22XL U1478 ( .A0(EX_PC[5]), .A1(n2139), .B0(EX_REGA[5]), .B1(n2137), .Y(
n2115) );
AO22XL U1479 ( .A0(EX_PC[6]), .A1(n2139), .B0(EX_REGA[6]), .B1(n2137), .Y(
n2117) );
AO22XL U1480 ( .A0(EX_PC[0]), .A1(n2139), .B0(EX_REGA[0]), .B1(n2137), .Y(
n2109) );
NOR2XL U1481 ( .A(EX_INSTR[28]), .B(EX_INSTR[26]), .Y(n1577) );
AO22XL U1482 ( .A0(EX_PC[0]), .A1(n2139), .B0(EX_REGA[0]), .B1(n2137), .Y(
n2108) );
AO22XL U1483 ( .A0(EX_PC[0]), .A1(n2139), .B0(EX_REGA[0]), .B1(n2137), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N202 ) );
XOR2XL U1484 ( .A(n2183), .B(\BOOTH_instance/n455 ), .Y(
\BOOTH_instance/n239 ) );
XOR2XL U1485 ( .A(n2177), .B(\BOOTH_instance/n452 ), .Y(
\BOOTH_instance/n209 ) );
XOR2XL U1486 ( .A(n2174), .B(\BOOTH_instance/n449 ), .Y(
\BOOTH_instance/n189 ) );
INVXL U1487 ( .A(n2169), .Y(n2167) );
INVXL U1488 ( .A(\BOOTH_instance/n151 ), .Y(\BOOTH_instance/n157 ) );
CLKINVX2 U1489 ( .A(n1692), .Y(\BOOTH_instance/decoded[1][31] ) );
XNOR3XL U1490 ( .A(\BOOTH_instance/decoded[4][31] ), .B(
\BOOTH_instance/decoded[5][31] ), .C(
\BOOTH_instance/add_5_root_add_53_G7/carry[31] ), .Y(n1637) );
CLKINVX1 U1491 ( .A(n1693), .Y(\BOOTH_instance/decoded[0][31] ) );
INVXL U1492 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n109 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n55 ) );
INVXL U1493 ( .A(n1694), .Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n75 ) );
INVXL U1494 ( .A(n2169), .Y(n2165) );
INVXL U1495 ( .A(n2168), .Y(n2166) );
XOR2XL U1496 ( .A(\BOOTH_instance/n450 ), .B(n1667), .Y(
\BOOTH_instance/n177 ) );
XOR2XL U1497 ( .A(\BOOTH_instance/n456 ), .B(n1604), .Y(
\BOOTH_instance/n249 ) );
XOR2XL U1498 ( .A(\BOOTH_instance/n453 ), .B(n2182), .Y(
\BOOTH_instance/n229 ) );
XOR2XL U1499 ( .A(\BOOTH_instance/n451 ), .B(n2176), .Y(
\BOOTH_instance/n199 ) );
XOR2XL U1500 ( .A(n2179), .B(\BOOTH_instance/n454 ), .Y(
\BOOTH_instance/n219 ) );
NAND2XL U1501 ( .A(\BOOTH_instance/n317 ), .B(\BOOTH_instance/n315 ), .Y(
\BOOTH_instance/n166 ) );
CLKINVX1 U1502 ( .A(n1605), .Y(n2174) );
INVXL U1503 ( .A(\BOOTH_instance/n155 ), .Y(\BOOTH_instance/n168 ) );
NAND2XL U1504 ( .A(\BOOTH_instance/n448 ), .B(\BOOTH_instance/n156 ), .Y(
\BOOTH_instance/n151 ) );
AO2B2XL U1505 ( .B0(EX_ALU_OUT[0]), .B1(n2141), .A0(n2142), .A1N(n1638), .Y(
N4860) );
AO21XL U1506 ( .A0(\BOOTH_instance/n445 ), .A1(\BOOTH_instance/n447 ), .B0(
\BOOTH_instance/n316 ), .Y(n1638) );
AOI21XL U1507 ( .A0(n1703), .A1(\BOOTH_instance/n350 ), .B0(
\BOOTH_instance/n157 ), .Y(\BOOTH_instance/decoded[4][31] ) );
CLKINVX1 U1508 ( .A(n1667), .Y(n2173) );
INVXL U1509 ( .A(EX_ADD_SUB), .Y(n2134) );
XOR2XL U1510 ( .A(n2132), .B(n2170), .Y(\ALU_instance/INTERNAL_B[3] ) );
AOI21XL U1511 ( .A0(\BOOTH_instance/n323 ), .A1(n1700), .B0(
\BOOTH_instance/n157 ), .Y(\BOOTH_instance/decoded[5][31] ) );
INVXL U1512 ( .A(n1697), .Y(\BOOTH_instance/decoded[3][31] ) );
INVXL U1513 ( .A(n1698), .Y(\BOOTH_instance/decoded[2][31] ) );
NAND2XL U1514 ( .A(n2159), .B(n1598), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n46 ) );
NAND2XL U1515 ( .A(n1598), .B(n2161), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ) );
NOR2BXL U1516 ( .AN(n2171), .B(\ALU_instance/SHIFTER_GENERIC_I/C50/n139 ),
.Y(\ALU_instance/SHIFTER_GENERIC_I/C48/n73 ) );
NOR2XL U1517 ( .A(n2172), .B(n2157), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n74 ) );
AND2XL U1518 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n133 ), .B(n2158), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n18 ) );
AND2XL U1519 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n152 ), .B(n2158), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n8 ) );
AND2XL U1520 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n153 ), .B(n2158), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n8 ) );
NOR2XL U1521 ( .A(n2162), .B(n1598), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ) );
NOR2XL U1522 ( .A(n2159), .B(n1598), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ) );
NOR2XL U1523 ( .A(n2159), .B(n1598), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ) );
NAND2XL U1524 ( .A(n2159), .B(n1598), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n22 ) );
NAND2XL U1525 ( .A(n1598), .B(n2159), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n43 ) );
NOR2BXL U1526 ( .AN(n2159), .B(n1598), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n25 ) );
OR2XL U1527 ( .A(n2162), .B(n1598), .Y(n1641) );
NAND2XL U1528 ( .A(n1598), .B(n2161), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n45 ) );
AO2B2XL U1529 ( .B0(EX_ALU_OUT[2]), .B1(n2141), .A0(n2142), .A1N(n1642), .Y(
N4862) );
XNOR2XL U1530 ( .A(\BOOTH_instance/decoded[1][2] ), .B(\BOOTH_instance/N211 ), .Y(n1642) );
NOR2XL U1531 ( .A(n1597), .B(n2110), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n84 ) );
NAND2XL U1532 ( .A(n2170), .B(n2158), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n70 ) );
CLKBUFX1 U1533 ( .A(n1612), .Y(n2130) );
NOR2XL U1534 ( .A(\ALU_instance/n23 ), .B(EX_ALU_SEL[0]), .Y(
\ALU_instance/n6 ) );
INVXL U1535 ( .A(n1531), .Y(EX_LOGIC_CW[3]) );
NOR3XL U1536 ( .A(n2143), .B(n1227), .C(n2144), .Y(n1643) );
AND2XL U1537 ( .A(EX_ALU_SEL[0]), .B(EX_ALU_SEL[1]), .Y(\ALU_instance/n5 )
);
INVXL U1538 ( .A(n1699), .Y(\ALU_instance/SHIFTER_GENERIC_I/n13 ) );
CLKINVX1 U1539 ( .A(n2180), .Y(n2179) );
OAI221XL U1540 ( .A0(n1644), .A1(\BOOTH_instance/n186 ), .B0(
\BOOTH_instance/n290 ), .B1(n1603), .C0(\BOOTH_instance/n319 ), .Y(
\BOOTH_instance/n305 ) );
NAND2XL U1541 ( .A(n1645), .B(\BOOTH_instance/n348 ), .Y(
\BOOTH_instance/n323 ) );
NAND2XL U1542 ( .A(N4836), .B(\BOOTH_instance/n371 ), .Y(
\BOOTH_instance/n350 ) );
NAND2XL U1543 ( .A(N4834), .B(\BOOTH_instance/n395 ), .Y(
\BOOTH_instance/n374 ) );
NAND2XL U1544 ( .A(N4842), .B(\BOOTH_instance/n317 ), .Y(
\BOOTH_instance/n158 ) );
INVXL U1545 ( .A(n1648), .Y(\BOOTH_instance/n156 ) );
INVXL U1546 ( .A(n2117), .Y(\BOOTH_instance/n260 ) );
NAND3XL U1547 ( .A(N4841), .B(\BOOTH_instance/n315 ), .C(N4840), .Y(
\BOOTH_instance/n155 ) );
INVXL U1548 ( .A(n2113), .Y(\BOOTH_instance/n307 ) );
INVXL U1549 ( .A(N4727), .Y(n2182) );
INVXL U1550 ( .A(N4730), .Y(n2176) );
INVXL U1551 ( .A(N4726), .Y(n2184) );
INVXL U1552 ( .A(N4729), .Y(n2178) );
INVXL U1553 ( .A(N4842), .Y(\BOOTH_instance/n315 ) );
INVXL U1554 ( .A(N4836), .Y(\BOOTH_instance/n346 ) );
INVXL U1555 ( .A(N4840), .Y(\BOOTH_instance/n318 ) );
INVXL U1556 ( .A(n1703), .Y(\BOOTH_instance/n353 ) );
INVXL U1557 ( .A(n1704), .Y(\BOOTH_instance/n377 ) );
INVXL U1558 ( .A(n1701), .Y(\BOOTH_instance/n176 ) );
INVXL U1559 ( .A(n1718), .Y(\BOOTH_instance/n150 ) );
INVXL U1560 ( .A(n1702), .Y(\BOOTH_instance/n326 ) );
INVXL U1561 ( .A(n1700), .Y(\BOOTH_instance/n327 ) );
INVXL U1562 ( .A(EX_ADD_SUB), .Y(n2132) );
INVXL U1563 ( .A(EX_ADD_SUB), .Y(n2133) );
XOR2XL U1564 ( .A(n2134), .B(N4841), .Y(\ALU_instance/INTERNAL_B[14] ) );
XOR2XL U1565 ( .A(n2132), .B(N4833), .Y(\ALU_instance/INTERNAL_B[6] ) );
XOR2XL U1566 ( .A(n2134), .B(n1645), .Y(\ALU_instance/INTERNAL_B[11] ) );
XOR2XL U1567 ( .A(n2134), .B(N4837), .Y(\ALU_instance/INTERNAL_B[10] ) );
XOR2XL U1568 ( .A(n2132), .B(N4836), .Y(\ALU_instance/INTERNAL_B[9] ) );
XOR2XL U1569 ( .A(n2132), .B(N4832), .Y(\ALU_instance/INTERNAL_B[5] ) );
XOR2XL U1570 ( .A(n2132), .B(N4834), .Y(\ALU_instance/INTERNAL_B[7] ) );
XOR2XL U1571 ( .A(n2134), .B(N4840), .Y(\ALU_instance/INTERNAL_B[13] ) );
AOI222XL U1572 ( .A0(n2123), .A1(n2189), .B0(n2113), .B1(n2127), .C0(n2108),
.C1(n1598), .Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n100 ) );
AOI222XL U1573 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .A1(n1679),
.B0(n2122), .B1(n1688), .C0(n1598), .C1(n1689), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n86 ) );
OAI221XL U1574 ( .A0(n2124), .A1(n2188), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n22 ), .B1(n1644), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n159 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n74 ) );
OAI221XL U1575 ( .A0(n2124), .A1(n2187), .B0(n2188), .B1(n2126), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n179 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n99 ) );
OAI221XL U1576 ( .A0(n2125), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n166 ),
.B0(n2126), .B1(n2187), .C0(\ALU_instance/SHIFTER_GENERIC_I/C86/n174 ),
.Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n92 ) );
AOI222XL U1577 ( .A0(n2122), .A1(n1688), .B0(n2121), .B1(n1689), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .C1(n1679), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n64 ) );
AOI221XL U1578 ( .A0(n2121), .A1(n2173), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n52 ), .B1(n1648), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n156 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n129 ) );
AOI221XL U1579 ( .A0(n2121), .A1(n1681), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n52 ), .B1(n1676), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n146 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n114 ) );
AOI221XL U1580 ( .A0(n2121), .A1(n1648), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n52 ), .B1(n1681), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n128 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n97 ) );
INVXL U1581 ( .A(n690), .Y(n2158) );
INVXL U1582 ( .A(n688), .Y(n2161) );
CLKBUFX1 U1583 ( .A(EX_LOGIC_CW[2]), .Y(n2191) );
CLKBUFX1 U1584 ( .A(EX_LOGIC_CW[2]), .Y(n2190) );
NAND3XL U1585 ( .A(n1533), .B(n1531), .C(n1546), .Y(EX_ALU_SEL[1]) );
NAND2XL U1586 ( .A(n1516), .B(n1517), .Y(n1292) );
INVXL U1587 ( .A(n2118), .Y(n1310) );
INVXL U1588 ( .A(n1615), .Y(n1522) );
CLKBUFX1 U1589 ( .A(n1211), .Y(n2146) );
NOR3XL U1590 ( .A(EX_INSTR[30]), .B(EX_INSTR[31]), .C(n1576), .Y(n1535) );
AO2B2XL U1591 ( .B0(EX_REGB[11]), .B1(n2148), .A0(n2150), .A1N(n1646), .Y(
n1645) );
AO2B2XL U1592 ( .B0(EX_REGA[10]), .B1(n2138), .A0(n2139), .A1N(n1647), .Y(
N4728) );
AO22XL U1593 ( .A0(EX_PC[15]), .A1(n2140), .B0(EX_REGA[15]), .B1(n2138), .Y(
n1648) );
NOR2XL U1594 ( .A(n1608), .B(EX_INSTR[31]), .Y(n1575) );
AO2B2XL U1595 ( .B0(EX_REGB[14]), .B1(n2148), .A0(n2150), .A1N(n1649), .Y(
N4841) );
NAND2XL U1596 ( .A(EX_INSTR[26]), .B(n1356), .Y(n1355) );
AO2B2XL U1597 ( .B0(EX_REGB[6]), .B1(n2149), .A0(n2150), .A1N(n1650), .Y(
N4833) );
AO2B2XL U1598 ( .B0(EX_REGB[12]), .B1(n2148), .A0(n2150), .A1N(n1651), .Y(
N4839) );
AO2B2XL U1599 ( .B0(EX_REGB[8]), .B1(n2149), .A0(n2150), .A1N(n1652), .Y(
N4835) );
AO2B2XL U1600 ( .B0(EX_REGB[10]), .B1(n2148), .A0(n2150), .A1N(n1653), .Y(
N4837) );
AO2B2XL U1601 ( .B0(EX_REGB[9]), .B1(n2149), .A0(n2150), .A1N(n1654), .Y(
N4836) );
AO2B2XL U1602 ( .B0(EX_REGB[5]), .B1(n2149), .A0(n2150), .A1N(n1655), .Y(
N4832) );
AO2B2XL U1603 ( .B0(EX_REGB[7]), .B1(n2149), .A0(n2150), .A1N(n1656), .Y(
N4834) );
AO2B2XL U1604 ( .B0(EX_REGB[15]), .B1(n2148), .A0(n2150), .A1N(n1657), .Y(
N4842) );
AO2B2XL U1605 ( .B0(EX_REGB[13]), .B1(n2148), .A0(n2150), .A1N(n1658), .Y(
N4840) );
AO2B2XL U1606 ( .B0(EX_REGB[0]), .B1(n2149), .A0(n2150), .A1N(n1659), .Y(
n688) );
INVXL U1607 ( .A(EX_INSTR[29]), .Y(n1576) );
INVXL U1608 ( .A(EX_INSTR[28]), .Y(n1565) );
AO2B2XL U1609 ( .B0(EX_REGB[4]), .B1(n1189), .A0(n2150), .A1N(n1661), .Y(
N4831) );
AO2B2XL U1610 ( .B0(EX_REGA[4]), .B1(n2137), .A0(n2139), .A1N(n1662), .Y(
N4722) );
AO2B2XL U1611 ( .B0(EX_REGA[8]), .B1(n2138), .A0(n2139), .A1N(n1663), .Y(
N4726) );
AO2B2XL U1612 ( .B0(EX_REGA[9]), .B1(n2138), .A0(n2139), .A1N(n1664), .Y(
N4727) );
AO2B2XL U1613 ( .B0(EX_REGA[11]), .B1(n2138), .A0(n2139), .A1N(n1665), .Y(
N4729) );
AO2B2XL U1614 ( .B0(EX_REGA[12]), .B1(n2138), .A0(n2139), .A1N(n1666), .Y(
N4730) );
AOI22XL U1615 ( .A0(EX_PC[14]), .A1(n2140), .B0(EX_REGA[14]), .B1(n2138),
.Y(n1667) );
AO2B2XL U1616 ( .B0(EX_REGB[21]), .B1(n2148), .A0(n2150), .A1N(n1668), .Y(
N4848) );
AO2B2XL U1617 ( .B0(EX_REGB[20]), .B1(n2148), .A0(n2150), .A1N(n1669), .Y(
N4847) );
AO2B2XL U1618 ( .B0(EX_REGB[19]), .B1(n2148), .A0(n2150), .A1N(n1670), .Y(
N4846) );
AO2B2XL U1619 ( .B0(EX_REGB[18]), .B1(n2148), .A0(n2150), .A1N(n1671), .Y(
N4845) );
AO2B2XL U1620 ( .B0(EX_REGB[17]), .B1(n2148), .A0(n2150), .A1N(n1672), .Y(
N4844) );
AO2B2XL U1621 ( .B0(EX_REGB[16]), .B1(n2148), .A0(n2150), .A1N(n1673), .Y(
N4843) );
INVXL U1622 ( .A(EX_INSTR[1]), .Y(n1560) );
AO22XL U1623 ( .A0(EX_PC[25]), .A1(n2140), .B0(EX_REGA[25]), .B1(n2138), .Y(
n1674) );
AO22XL U1624 ( .A0(EX_PC[26]), .A1(n2140), .B0(EX_REGA[26]), .B1(n2138), .Y(
n1677) );
AO22XL U1625 ( .A0(EX_PC[27]), .A1(n2140), .B0(EX_REGA[27]), .B1(n2138), .Y(
n1678) );
AO22XL U1626 ( .A0(EX_PC[29]), .A1(n2140), .B0(EX_REGA[29]), .B1(n2138), .Y(
n1679) );
AO22XL U1627 ( .A0(EX_PC[24]), .A1(n2140), .B0(EX_REGA[24]), .B1(n2138), .Y(
n1682) );
AO22XL U1628 ( .A0(EX_PC[28]), .A1(n2140), .B0(EX_REGA[28]), .B1(n2138), .Y(
n1687) );
AO22XL U1629 ( .A0(EX_PC[30]), .A1(n2140), .B0(EX_REGA[30]), .B1(n2138), .Y(
n1688) );
AO22XL U1630 ( .A0(EX_PC[31]), .A1(n2140), .B0(EX_REGA[31]), .B1(n2138), .Y(
n1689) );
AO2B2XL U1631 ( .B0(EX_REGB[31]), .B1(n2149), .A0(n2150), .A1N(n1690), .Y(
\EX_ALU_B[31] ) );
CLKBUFX2 U1632 ( .A(ID_IMM16_SHL2[31]), .Y(n2106) );
NOR4XL U1633 ( .A(ID_INSTR_27), .B(ID_INSTR_29), .C(ID_INSTR_30), .D(
ID_INSTR_31), .Y(n1516) );
NOR3XL U1634 ( .A(n1195), .B(ID_INSTR_28), .C(n1293), .Y(n1226) );
NOR3XL U1635 ( .A(ID_INSTR_29), .B(ID_INSTR_31), .C(n1484), .Y(n1291) );
NAND2XL U1636 ( .A(n1532), .B(n1533), .Y(EX_LOGIC_CW[2]) );
INVXL U1637 ( .A(ID_INSTR_28), .Y(n1290) );
INVXL U1638 ( .A(ID_INSTR_26), .Y(n1518) );
OAI31XL U1639 ( .A0(n1196), .A1(ID_INSTR_27), .A2(n1521), .B0(n1198), .Y(
n1370) );
NAND2XL U1640 ( .A(IF_STALL_SEL), .B(n1615), .Y(n697) );
INVXL U1641 ( .A(ID_INSTR_30), .Y(n1483) );
NOR3BXL U1642 ( .AN(n1436), .B(n1213), .C(MEM_INSTR[28]), .Y(n1435) );
CLKBUFX1 U1643 ( .A(n1342), .Y(n2118) );
NAND4XL U1644 ( .A(n1215), .B(MEM_INSTR[29]), .C(n1444), .D(n1220), .Y(n1216) );
INVXL U1645 ( .A(WB_INSTR_30), .Y(n1340) );
INVXL U1646 ( .A(MEM_INSTR[28]), .Y(n1220) );
INVXL U1647 ( .A(WB_INSTR_29), .Y(n1471) );
INVXL U1648 ( .A(n1819), .Y(WB_SIGN_EXT_16_CONTROL) );
INVXL U1649 ( .A(MEM_INSTR[26]), .Y(n1445) );
INVXL U1650 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n41 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n3 ) );
NOR2XL U1651 ( .A(\ALU_instance/COMPARATOR_GENERIC_I/n9 ), .B(
\ALU_instance/ZERO ), .Y(\ALU_instance/COMPARATOR_GENERIC_I/n7 ) );
INVXL U1652 ( .A(\BOOTH_instance/n239 ), .Y(\BOOTH_instance/n232 ) );
INVXL U1653 ( .A(\BOOTH_instance/n209 ), .Y(\BOOTH_instance/n202 ) );
INVXL U1654 ( .A(\BOOTH_instance/n189 ), .Y(\BOOTH_instance/n180 ) );
INVXL U1655 ( .A(\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[3] ), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/n2 ) );
INVXL U1656 ( .A(\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[2] ), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/n2 ) );
INVXL U1657 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n43 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n21 ) );
NOR2XL U1658 ( .A(n1694), .B(n2167), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n16 ) );
NOR2XL U1659 ( .A(n1694), .B(n2167), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n41 ) );
INVXL U1660 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n132 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n3 ) );
OAI21XL U1661 ( .A0(n2166), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n8 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n3 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N206 ) );
OAI21XL U1662 ( .A0(n2166), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n9 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n3 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N205 ) );
OAI21XL U1663 ( .A0(n2166), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n115 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n3 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N203 ) );
INVXL U1664 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n122 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n10 ) );
OR2XL U1665 ( .A(n1694), .B(n2167), .Y(n1691) );
INVXL U1666 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n38 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n6 ) );
INVXL U1667 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n11 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n55 ) );
INVXL U1668 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n38 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n6 ) );
INVXL U1669 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n107 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n103 ) );
NOR4XL U1670 ( .A(\ALU_instance/ADDER_OUT[5] ), .B(
\ALU_instance/ADDER_OUT[4] ), .C(\ALU_instance/ADDER_OUT[3] ), .D(
\ALU_instance/ADDER_OUT[31] ), .Y(
\ALU_instance/COMPARATOR_GENERIC_I/n18 ) );
OAI2BB2XL U1671 ( .B0(\BOOTH_instance/n293 ), .B1(\BOOTH_instance/n294 ),
.A0N(\BOOTH_instance/n295 ), .A1N(\BOOTH_instance/n296 ), .Y(
\BOOTH_instance/n286 ) );
NOR2XL U1672 ( .A(\BOOTH_instance/n296 ), .B(\BOOTH_instance/n295 ), .Y(
\BOOTH_instance/n294 ) );
NOR2XL U1673 ( .A(\ALU_instance/COMPARATOR_GENERIC_I/n10 ), .B(
\ALU_instance/COMPARATOR_GENERIC_I/n11 ), .Y(\ALU_instance/ZERO ) );
NAND4XL U1674 ( .A(\ALU_instance/COMPARATOR_GENERIC_I/n12 ), .B(
\ALU_instance/COMPARATOR_GENERIC_I/n13 ), .C(
\ALU_instance/COMPARATOR_GENERIC_I/n14 ), .D(
\ALU_instance/COMPARATOR_GENERIC_I/n15 ), .Y(
\ALU_instance/COMPARATOR_GENERIC_I/n11 ) );
NAND4XL U1675 ( .A(\ALU_instance/COMPARATOR_GENERIC_I/n16 ), .B(
\ALU_instance/COMPARATOR_GENERIC_I/n17 ), .C(
\ALU_instance/COMPARATOR_GENERIC_I/n18 ), .D(
\ALU_instance/COMPARATOR_GENERIC_I/n19 ), .Y(
\ALU_instance/COMPARATOR_GENERIC_I/n10 ) );
NOR4XL U1676 ( .A(\ALU_instance/ADDER_OUT[12] ), .B(
\ALU_instance/ADDER_OUT[11] ), .C(\ALU_instance/ADDER_OUT[10] ), .D(
\ALU_instance/ADDER_OUT[0] ), .Y(
\ALU_instance/COMPARATOR_GENERIC_I/n12 ) );
NOR2XL U1677 ( .A(\BOOTH_instance/n451 ), .B(n2175), .Y(
\BOOTH_instance/n449 ) );
AO22XL U1678 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/C1 ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[2] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/C0 ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/n2 ), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[3] ) );
AO22XL U1679 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/C1 ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[1] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/C0 ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/n2 ), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[2] ) );
NOR2XL U1680 ( .A(\BOOTH_instance/n456 ), .B(n2185), .Y(
\BOOTH_instance/n455 ) );
AOI22XL U1681 ( .A0(\BOOTH_instance/n400 ), .A1(n2186), .B0(
\BOOTH_instance/n401 ), .B1(\BOOTH_instance/n272 ), .Y(
\BOOTH_instance/n399 ) );
AOI22XL U1682 ( .A0(\BOOTH_instance/n400 ), .A1(n2185), .B0(
\BOOTH_instance/n401 ), .B1(\BOOTH_instance/n242 ), .Y(
\BOOTH_instance/n416 ) );
AOI22XL U1683 ( .A0(\BOOTH_instance/n400 ), .A1(n2183), .B0(
\BOOTH_instance/n401 ), .B1(\BOOTH_instance/n232 ), .Y(
\BOOTH_instance/n415 ) );
AOI22XL U1684 ( .A0(\BOOTH_instance/n400 ), .A1(n2181), .B0(
\BOOTH_instance/n401 ), .B1(\BOOTH_instance/n222 ), .Y(
\BOOTH_instance/n414 ) );
AOI22XL U1685 ( .A0(\BOOTH_instance/n400 ), .A1(n2177), .B0(
\BOOTH_instance/n401 ), .B1(\BOOTH_instance/n202 ), .Y(
\BOOTH_instance/n412 ) );
AOI22XL U1686 ( .A0(\BOOTH_instance/n400 ), .A1(n2175), .B0(
\BOOTH_instance/n401 ), .B1(\BOOTH_instance/n192 ), .Y(
\BOOTH_instance/n411 ) );
AOI22XL U1687 ( .A0(\BOOTH_instance/n400 ), .A1(n2174), .B0(
\BOOTH_instance/n401 ), .B1(\BOOTH_instance/n180 ), .Y(
\BOOTH_instance/n410 ) );
AOI22XL U1688 ( .A0(\BOOTH_instance/n400 ), .A1(n2173), .B0(
\BOOTH_instance/n401 ), .B1(\BOOTH_instance/n169 ), .Y(
\BOOTH_instance/n409 ) );
AOI21XL U1689 ( .A0(\BOOTH_instance/n422 ), .A1(\BOOTH_instance/n421 ), .B0(
\BOOTH_instance/n316 ), .Y(\BOOTH_instance/decoded[1][2] ) );
INVXL U1690 ( .A(n2109), .Y(\BOOTH_instance/n316 ) );
AO2B2XL U1691 ( .B0(\BOOTH_instance/n170 ), .B1(\BOOTH_instance/n171 ), .A0(
\BOOTH_instance/n172 ), .A1N(\BOOTH_instance/n173 ), .Y(
\BOOTH_instance/n159 ) );
NOR2XL U1692 ( .A(\BOOTH_instance/n171 ), .B(\BOOTH_instance/n170 ), .Y(
\BOOTH_instance/n173 ) );
AO21XL U1693 ( .A0(\BOOTH_instance/n422 ), .A1(n1696), .B0(
\BOOTH_instance/n157 ), .Y(n1692) );
OAI21XL U1694 ( .A0(\BOOTH_instance/n424 ), .A1(\BOOTH_instance/n425 ), .B0(
n2108), .Y(\BOOTH_instance/n432 ) );
OAI2BB1XL U1695 ( .A0N(\BOOTH_instance/n159 ), .A1N(\BOOTH_instance/n160 ),
.B0(\BOOTH_instance/n161 ), .Y(\BOOTH_instance/n147 ) );
OAI21XL U1696 ( .A0(\BOOTH_instance/n160 ), .A1(\BOOTH_instance/n159 ), .B0(
\BOOTH_instance/n162 ), .Y(\BOOTH_instance/n161 ) );
AO21XL U1697 ( .A0(\BOOTH_instance/n445 ), .A1(n2124), .B0(
\BOOTH_instance/n157 ), .Y(n1693) );
INVXL U1698 ( .A(\BOOTH_instance/n299 ), .Y(\BOOTH_instance/n272 ) );
INVXL U1699 ( .A(\BOOTH_instance/n177 ), .Y(\BOOTH_instance/n169 ) );
INVXL U1700 ( .A(\BOOTH_instance/n280 ), .Y(\BOOTH_instance/n292 ) );
INVXL U1701 ( .A(\BOOTH_instance/n259 ), .Y(\BOOTH_instance/n252 ) );
INVXL U1702 ( .A(\BOOTH_instance/n199 ), .Y(\BOOTH_instance/n192 ) );
INVXL U1703 ( .A(\BOOTH_instance/n219 ), .Y(\BOOTH_instance/n212 ) );
INVXL U1704 ( .A(\BOOTH_instance/n229 ), .Y(\BOOTH_instance/n222 ) );
INVXL U1705 ( .A(\BOOTH_instance/n249 ), .Y(\BOOTH_instance/n242 ) );
INVXL U1706 ( .A(\BOOTH_instance/n166 ), .Y(\BOOTH_instance/n282 ) );
AO2B2XL U1707 ( .B0(\BOOTH_instance/n223 ), .B1(\BOOTH_instance/n224 ), .A0(
\BOOTH_instance/n225 ), .A1N(\BOOTH_instance/n226 ), .Y(
\BOOTH_instance/n215 ) );
NOR2XL U1708 ( .A(\BOOTH_instance/n224 ), .B(\BOOTH_instance/n223 ), .Y(
\BOOTH_instance/n226 ) );
AO2B2XL U1709 ( .B0(\BOOTH_instance/n203 ), .B1(\BOOTH_instance/n204 ), .A0(
\BOOTH_instance/n205 ), .A1N(\BOOTH_instance/n206 ), .Y(
\BOOTH_instance/n195 ) );
NOR2XL U1710 ( .A(\BOOTH_instance/n204 ), .B(\BOOTH_instance/n203 ), .Y(
\BOOTH_instance/n206 ) );
AO2B2XL U1711 ( .B0(\BOOTH_instance/n193 ), .B1(\BOOTH_instance/n194 ), .A0(
\BOOTH_instance/n195 ), .A1N(\BOOTH_instance/n196 ), .Y(
\BOOTH_instance/n183 ) );
NOR2XL U1712 ( .A(\BOOTH_instance/n194 ), .B(\BOOTH_instance/n193 ), .Y(
\BOOTH_instance/n196 ) );
AO2B2XL U1713 ( .B0(\BOOTH_instance/n181 ), .B1(\BOOTH_instance/n182 ), .A0(
\BOOTH_instance/n183 ), .A1N(\BOOTH_instance/n184 ), .Y(
\BOOTH_instance/n172 ) );
NOR2XL U1714 ( .A(\BOOTH_instance/n182 ), .B(\BOOTH_instance/n181 ), .Y(
\BOOTH_instance/n184 ) );
XNOR2XL U1715 ( .A(\BOOTH_instance/n297 ), .B(\BOOTH_instance/n296 ), .Y(
\BOOTH_instance/partial_products[5][16] ) );
XOR2XL U1716 ( .A(\BOOTH_instance/partial_products[2][16] ), .B(
\BOOTH_instance/decoded[8][16] ), .Y(
\BOOTH_instance/partial_products[6][16] ) );
XOR2XL U1717 ( .A(\BOOTH_instance/n295 ), .B(\BOOTH_instance/n293 ), .Y(
\BOOTH_instance/n297 ) );
XNOR2XL U1718 ( .A(\BOOTH_instance/n227 ), .B(\BOOTH_instance/n224 ), .Y(
\BOOTH_instance/partial_products[5][23] ) );
XNOR2XL U1719 ( .A(\BOOTH_instance/n225 ), .B(\BOOTH_instance/n223 ), .Y(
\BOOTH_instance/n227 ) );
XNOR2XL U1720 ( .A(\BOOTH_instance/n207 ), .B(\BOOTH_instance/n204 ), .Y(
\BOOTH_instance/partial_products[5][25] ) );
XNOR2XL U1721 ( .A(\BOOTH_instance/n205 ), .B(\BOOTH_instance/n203 ), .Y(
\BOOTH_instance/n207 ) );
XNOR2XL U1722 ( .A(\BOOTH_instance/n185 ), .B(\BOOTH_instance/n182 ), .Y(
\BOOTH_instance/partial_products[5][27] ) );
XNOR2XL U1723 ( .A(\BOOTH_instance/n183 ), .B(\BOOTH_instance/n181 ), .Y(
\BOOTH_instance/n185 ) );
XNOR2XL U1724 ( .A(\BOOTH_instance/n174 ), .B(\BOOTH_instance/n171 ), .Y(
\BOOTH_instance/partial_products[5][28] ) );
XNOR2XL U1725 ( .A(\BOOTH_instance/n172 ), .B(\BOOTH_instance/n170 ), .Y(
\BOOTH_instance/n174 ) );
XOR2XL U1726 ( .A(\BOOTH_instance/n159 ), .B(\BOOTH_instance/n163 ), .Y(
\BOOTH_instance/partial_products[5][29] ) );
XNOR2XL U1727 ( .A(\BOOTH_instance/n162 ), .B(\BOOTH_instance/n146 ), .Y(
\BOOTH_instance/n163 ) );
XOR2XL U1728 ( .A(\BOOTH_instance/n147 ), .B(\BOOTH_instance/n152 ), .Y(
\BOOTH_instance/partial_products[5][30] ) );
XNOR2XL U1729 ( .A(\BOOTH_instance/n145 ), .B(\BOOTH_instance/n146 ), .Y(
\BOOTH_instance/n152 ) );
INVXL U1730 ( .A(\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[5] ), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/n2 ) );
INVXL U1731 ( .A(\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[4] ), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/n2 ) );
INVXL U1732 ( .A(\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[1] ), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/n2 ) );
INVXL U1733 ( .A(\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[7] ), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/n2 ) );
INVXL U1734 ( .A(\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[6] ), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/n2 ) );
XOR2XL U1735 ( .A(n2134), .B(n2159), .Y(\ALU_instance/INTERNAL_B[0] ) );
INVXL U1736 ( .A(\ALU_instance/OVERFLOW ), .Y(
\ALU_instance/COMPARATOR_GENERIC_I/n9 ) );
AOI221XL U1737 ( .A0(n2121), .A1(n2174), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n52 ), .B1(n2173), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n142 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n43 ) );
AO22XL U1738 ( .A0(n2175), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ),
.B0(n2177), .B1(\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n142 ) );
NAND2XL U1739 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n47 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n48 ), .Y(
\ALU_instance/SHIFTER_OUT[27] ) );
NAND2XL U1740 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N261 ), .B(n2131), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n47 ) );
AOI222XL U1741 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N229 ), .A1(n2128),
.B0(\ALU_instance/SHIFTER_GENERIC_I/N132 ), .B1(n1613), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N164 ), .C1(n2130), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n48 ) );
NAND2XL U1742 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n49 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n50 ), .Y(
\ALU_instance/SHIFTER_OUT[26] ) );
NAND2XL U1743 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N260 ), .B(n2131), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n49 ) );
AOI222XL U1744 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N228 ), .A1(n2128),
.B0(\ALU_instance/SHIFTER_GENERIC_I/N131 ), .B1(n1613), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N163 ), .C1(n2130), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n50 ) );
NAND2XL U1745 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n51 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n52 ), .Y(
\ALU_instance/SHIFTER_OUT[25] ) );
NAND2XL U1746 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N259 ), .B(n2131), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n51 ) );
AOI222XL U1747 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N227 ), .A1(n2128),
.B0(\ALU_instance/SHIFTER_GENERIC_I/N130 ), .B1(n1613), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N162 ), .C1(n2130), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n52 ) );
NAND2XL U1748 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n53 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n54 ), .Y(
\ALU_instance/SHIFTER_OUT[24] ) );
NAND2XL U1749 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N258 ), .B(n2131), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n53 ) );
AOI222XL U1750 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N226 ), .A1(n2128),
.B0(\ALU_instance/SHIFTER_GENERIC_I/N129 ), .B1(n1613), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N161 ), .C1(n2130), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n54 ) );
NAND2XL U1751 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n55 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n56 ), .Y(
\ALU_instance/SHIFTER_OUT[23] ) );
NAND2XL U1752 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N257 ), .B(n2131), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n55 ) );
AOI222XL U1753 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N225 ), .A1(n2128),
.B0(\ALU_instance/SHIFTER_GENERIC_I/N128 ), .B1(n1613), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N160 ), .C1(n2130), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n56 ) );
NAND2XL U1754 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n57 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n58 ), .Y(
\ALU_instance/SHIFTER_OUT[22] ) );
NAND2XL U1755 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N256 ), .B(n2131), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n57 ) );
AOI222XL U1756 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N224 ), .A1(n2128),
.B0(\ALU_instance/SHIFTER_GENERIC_I/N127 ), .B1(n1613), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N159 ), .C1(n2130), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n58 ) );
NAND2XL U1757 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n59 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n60 ), .Y(
\ALU_instance/SHIFTER_OUT[21] ) );
NAND2XL U1758 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N255 ), .B(n2131), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n59 ) );
AOI222XL U1759 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N223 ), .A1(n2128),
.B0(\ALU_instance/SHIFTER_GENERIC_I/N126 ), .B1(n1613), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N158 ), .C1(n2130), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n60 ) );
NAND2XL U1760 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n65 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n66 ), .Y(
\ALU_instance/SHIFTER_OUT[19] ) );
NAND2XL U1761 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N253 ), .B(n2131), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n65 ) );
AOI222XL U1762 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N221 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/n13 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/N124 ), .B1(n2129), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N156 ), .C1(n1612), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n66 ) );
NAND2XL U1763 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n67 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n68 ), .Y(
\ALU_instance/SHIFTER_OUT[18] ) );
NAND2XL U1764 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N252 ), .B(n1611), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n67 ) );
AOI222XL U1765 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N220 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/n13 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/N123 ), .B1(n2129), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N155 ), .C1(n1612), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n68 ) );
NAND2XL U1766 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n75 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n76 ), .Y(
\ALU_instance/SHIFTER_OUT[14] ) );
NAND2XL U1767 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N248 ), .B(n1611), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n75 ) );
AOI222XL U1768 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N216 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/n13 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/N119 ), .B1(n1613), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N151 ), .C1(n1612), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n76 ) );
NOR2BXL U1769 ( .AN(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][14] ), .B(
n2163), .Y(\ALU_instance/SHIFTER_GENERIC_I/N248 ) );
NAND2XL U1770 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n77 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n78 ), .Y(
\ALU_instance/SHIFTER_OUT[13] ) );
NAND2XL U1771 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N247 ), .B(n1611), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n77 ) );
AOI222XL U1772 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N215 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/n13 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/N118 ), .B1(n1613), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N150 ), .C1(n1612), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n78 ) );
NOR2BXL U1773 ( .AN(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][13] ), .B(
n2163), .Y(\ALU_instance/SHIFTER_GENERIC_I/N247 ) );
NAND2XL U1774 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n81 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n82 ), .Y(
\ALU_instance/SHIFTER_OUT[11] ) );
NAND2XL U1775 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N245 ), .B(n1611), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n81 ) );
AOI222XL U1776 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N213 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/n13 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/N116 ), .B1(n1613), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N148 ), .C1(n1612), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n82 ) );
NOR2BXL U1777 ( .AN(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][11] ), .B(
n2163), .Y(\ALU_instance/SHIFTER_GENERIC_I/N245 ) );
NAND2XL U1778 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n83 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n84 ), .Y(
\ALU_instance/SHIFTER_OUT[10] ) );
NAND2XL U1779 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N244 ), .B(n1611), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n83 ) );
AOI222XL U1780 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N212 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/n13 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/N115 ), .B1(n1613), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N147 ), .C1(n1612), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n84 ) );
NOR2BXL U1781 ( .AN(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][10] ), .B(
n2163), .Y(\ALU_instance/SHIFTER_GENERIC_I/N244 ) );
NAND2XL U1782 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n35 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n36 ), .Y(
\ALU_instance/SHIFTER_OUT[3] ) );
NAND2XL U1783 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N237 ), .B(n1611), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n35 ) );
AOI222XL U1784 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N205 ), .A1(n2128),
.B0(\ALU_instance/SHIFTER_GENERIC_I/N108 ), .B1(n1613), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N140 ), .C1(n2130), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n36 ) );
NOR2XL U1785 ( .A(n2165), .B(\ALU_instance/SHIFTER_GENERIC_I/C88/n5 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N237 ) );
NOR4XL U1786 ( .A(\ALU_instance/ADDER_OUT[9] ), .B(
\ALU_instance/ADDER_OUT[8] ), .C(\ALU_instance/ADDER_OUT[7] ), .D(
\ALU_instance/ADDER_OUT[6] ), .Y(
\ALU_instance/COMPARATOR_GENERIC_I/n19 ) );
NOR4XL U1787 ( .A(\ALU_instance/ADDER_OUT[1] ), .B(
\ALU_instance/ADDER_OUT[19] ), .C(\ALU_instance/ADDER_OUT[18] ), .D(
\ALU_instance/ADDER_OUT[17] ), .Y(
\ALU_instance/COMPARATOR_GENERIC_I/n14 ) );
OAI21XL U1788 ( .A0(n2166), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n6 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n3 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N208 ) );
OAI21XL U1789 ( .A0(n2163), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n108 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n55 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N121 ) );
OAI21XL U1790 ( .A0(n2165), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n56 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n55 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N123 ) );
OAI21XL U1791 ( .A0(n2165), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n28 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n3 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N216 ) );
OAI21XL U1792 ( .A0(n2165), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n60 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n3 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N212 ) );
OAI21XL U1793 ( .A0(n2166), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n2 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n3 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N211 ) );
OAI21XL U1794 ( .A0(n2165), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n35 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n55 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N125 ) );
OAI21XL U1795 ( .A0(n2163), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n39 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n55 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N124 ) );
INVXL U1796 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n59 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n27 ) );
INVXL U1797 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n2 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n33 ) );
INVXL U1798 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n12 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n37 ) );
INVXL U1799 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n46 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n52 ) );
NOR2XL U1800 ( .A(n2166), .B(\ALU_instance/SHIFTER_GENERIC_I/C50/n33 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N158 ) );
NOR2XL U1801 ( .A(n2167), .B(\ALU_instance/SHIFTER_GENERIC_I/C50/n39 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N156 ) );
AO22XL U1802 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S1[3] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[1] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S0[3] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/n2 ), .Y(
\ALU_instance/ADDER_OUT[7] ) );
AO22XL U1803 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S1[2] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[3] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S0[2] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/n2 ), .Y(
\ALU_instance/ADDER_OUT[14] ) );
AO22XL U1804 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S1[2] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[2] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S0[2] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/n2 ), .Y(
\ALU_instance/ADDER_OUT[10] ) );
AO22XL U1805 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S1[0] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[1] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S0[0] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/n2 ), .Y(
\ALU_instance/ADDER_OUT[4] ) );
XNOR2XL U1806 ( .A(n2186), .B(\ALU_instance/INTERNAL_B[4] ), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S1[0] ) );
XOR2XL U1807 ( .A(\ALU_instance/INTERNAL_B[4] ), .B(n2186), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S0[0] ) );
AO22XL U1808 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S1[3] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[2] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S0[3] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/n2 ), .Y(
\ALU_instance/ADDER_OUT[11] ) );
AO22XL U1809 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S1[1] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[2] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S0[1] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/n2 ), .Y(
\ALU_instance/ADDER_OUT[9] ) );
AO22XL U1810 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S1[1] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[3] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S0[1] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/n2 ), .Y(
\ALU_instance/ADDER_OUT[13] ) );
NAND2XL U1811 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n11 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n12 ), .Y(
\ALU_instance/SHIFTER_OUT[9] ) );
NAND2XL U1812 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N243 ), .B(n1611), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n11 ) );
AOI222XL U1813 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N211 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/n13 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/N114 ), .B1(n2129), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N146 ), .C1(n1612), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n12 ) );
NOR2BXL U1814 ( .AN(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][9] ), .B(
n2163), .Y(\ALU_instance/SHIFTER_GENERIC_I/N243 ) );
NAND2XL U1815 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n25 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n26 ), .Y(
\ALU_instance/SHIFTER_OUT[8] ) );
NAND2XL U1816 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N242 ), .B(n1611), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n25 ) );
AOI222XL U1817 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N210 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/n13 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/N113 ), .B1(n2129), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N145 ), .C1(n1612), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n26 ) );
NOR2BXL U1818 ( .AN(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][8] ), .B(
n2163), .Y(\ALU_instance/SHIFTER_GENERIC_I/N242 ) );
NAND2XL U1819 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n27 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n28 ), .Y(
\ALU_instance/SHIFTER_OUT[7] ) );
NAND2XL U1820 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N241 ), .B(n1611), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n27 ) );
AOI222XL U1821 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N209 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/n13 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/N112 ), .B1(n2129), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N144 ), .C1(n1612), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n28 ) );
NOR2XL U1822 ( .A(n2165), .B(\ALU_instance/SHIFTER_GENERIC_I/C88/n1 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N241 ) );
NAND2XL U1823 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n29 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n30 ), .Y(
\ALU_instance/SHIFTER_OUT[6] ) );
NAND2XL U1824 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N240 ), .B(n1611), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n29 ) );
AOI222XL U1825 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N208 ), .A1(n2128),
.B0(\ALU_instance/SHIFTER_GENERIC_I/N111 ), .B1(n2129), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N143 ), .C1(n2130), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n30 ) );
NOR2XL U1826 ( .A(n2165), .B(\ALU_instance/SHIFTER_GENERIC_I/C88/n2 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N240 ) );
NAND2XL U1827 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n31 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n32 ), .Y(
\ALU_instance/SHIFTER_OUT[5] ) );
NAND2XL U1828 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N239 ), .B(n1611), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n31 ) );
AOI222XL U1829 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N207 ), .A1(n2128),
.B0(\ALU_instance/SHIFTER_GENERIC_I/N110 ), .B1(n2129), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N142 ), .C1(n2130), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n32 ) );
NOR2XL U1830 ( .A(n2165), .B(\ALU_instance/SHIFTER_GENERIC_I/C88/n3 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N239 ) );
NAND2XL U1831 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n33 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n34 ), .Y(
\ALU_instance/SHIFTER_OUT[4] ) );
NAND2XL U1832 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N238 ), .B(n1611), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n33 ) );
AOI222XL U1833 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N206 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/n13 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/N109 ), .B1(n2129), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N141 ), .C1(n1612), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n34 ) );
NOR2XL U1834 ( .A(n2165), .B(\ALU_instance/SHIFTER_GENERIC_I/C88/n4 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N238 ) );
NAND2XL U1835 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n61 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n62 ), .Y(
\ALU_instance/SHIFTER_OUT[20] ) );
NAND2XL U1836 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N254 ), .B(n2131), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n61 ) );
AOI222XL U1837 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N222 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/n13 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/N125 ), .B1(n2129), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N157 ), .C1(n1612), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n62 ) );
NAND2XL U1838 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n69 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n70 ), .Y(
\ALU_instance/SHIFTER_OUT[17] ) );
NAND2XL U1839 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N251 ), .B(n1611), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n69 ) );
AOI222XL U1840 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N219 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/n13 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/N122 ), .B1(n2129), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N154 ), .C1(n1612), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n70 ) );
NAND2XL U1841 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n71 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n72 ), .Y(
\ALU_instance/SHIFTER_OUT[16] ) );
NAND2XL U1842 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N250 ), .B(n1611), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n71 ) );
AOI222XL U1843 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N218 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/n13 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/N121 ), .B1(n1613), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N153 ), .C1(n1612), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n72 ) );
NAND2XL U1844 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n73 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n74 ), .Y(
\ALU_instance/SHIFTER_OUT[15] ) );
NAND2XL U1845 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N249 ), .B(n1611), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n73 ) );
AOI222XL U1846 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N217 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/n13 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/N120 ), .B1(n2129), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N152 ), .C1(n1612), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n74 ) );
NOR2BXL U1847 ( .AN(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][15] ), .B(
n2163), .Y(\ALU_instance/SHIFTER_GENERIC_I/N249 ) );
NAND2XL U1848 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n79 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n80 ), .Y(
\ALU_instance/SHIFTER_OUT[12] ) );
NAND2XL U1849 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N246 ), .B(n1611), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n79 ) );
AOI222XL U1850 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N214 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/n13 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/N117 ), .B1(n1613), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N149 ), .C1(n1612), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n80 ) );
NOR2BXL U1851 ( .AN(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][12] ), .B(
n2163), .Y(\ALU_instance/SHIFTER_GENERIC_I/N246 ) );
NAND2XL U1852 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n41 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n42 ), .Y(
\ALU_instance/SHIFTER_OUT[2] ) );
NAND2XL U1853 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N236 ), .B(n1611), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n41 ) );
AOI222XL U1854 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N204 ), .A1(n2128),
.B0(\ALU_instance/SHIFTER_GENERIC_I/N107 ), .B1(n2129), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N139 ), .C1(n2130), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n42 ) );
NOR2XL U1855 ( .A(n2166), .B(\ALU_instance/SHIFTER_GENERIC_I/C88/n6 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N236 ) );
NOR2XL U1856 ( .A(n2166), .B(\ALU_instance/SHIFTER_GENERIC_I/C50/n79 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N154 ) );
INVXL U1857 ( .A(n2121), .Y(n2120) );
INVXL U1858 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n45 ), .Y(n2121) );
INVXL U1859 ( .A(\BOOTH_instance/n160 ), .Y(\BOOTH_instance/n146 ) );
CLKBUFX1 U1860 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ), .Y(n2122) );
CLKBUFX1 U1861 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n25 ), .Y(n2127) );
CLKBUFX1 U1862 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .Y(n2123) );
CLKBUFX1 U1863 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n20 ), .Y(n2124) );
CLKBUFX1 U1864 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n43 ), .Y(n2119) );
INVXL U1865 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n66 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n90 ) );
CLKBUFX1 U1866 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n20 ), .Y(n2125) );
CLKBUFX1 U1867 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n22 ), .Y(n2126) );
NOR2XL U1868 ( .A(n2168), .B(n2110), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n132 ) );
AND2XL U1869 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n152 ), .B(n2156), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n10 ) );
AND2XL U1870 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n133 ), .B(n2156), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n14 ) );
NOR2XL U1871 ( .A(n2168), .B(n1694), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n98 ) );
NOR3XL U1872 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n66 ), .B(n2163), .C(
n2170), .Y(\ALU_instance/SHIFTER_GENERIC_I/N164 ) );
NAND2XL U1873 ( .A(n1592), .B(n2168), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n11 ) );
NAND2XL U1874 ( .A(n1595), .B(n2168), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n38 ) );
NAND2XL U1875 ( .A(n1595), .B(n2168), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n38 ) );
OAI21XL U1876 ( .A0(n2166), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n5 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n3 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N209 ) );
OAI21XL U1877 ( .A0(n2166), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n7 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n3 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N207 ) );
OAI21XL U1878 ( .A0(n2166), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n4 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n3 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N210 ) );
OAI21XL U1879 ( .A0(n2165), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n19 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n55 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N128 ) );
OAI21XL U1880 ( .A0(n2166), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n68 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n55 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N131 ) );
OAI21XL U1881 ( .A0(n2165), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n4 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n55 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N130 ) );
OAI21XL U1882 ( .A0(n2165), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n91 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n55 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N122 ) );
OAI21XL U1883 ( .A0(n2165), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n13 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n55 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N129 ) );
NAND2XL U1884 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n73 ), .B(n2156), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n81 ) );
OAI21XL U1885 ( .A0(n2166), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n35 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n3 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N204 ) );
OAI21XL U1886 ( .A0(n2166), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n12 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n3 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N217 ) );
OAI21XL U1887 ( .A0(n2166), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n37 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n3 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N215 ) );
OAI21XL U1888 ( .A0(n2166), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n45 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n3 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N214 ) );
OAI21XL U1889 ( .A0(n2166), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n53 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n3 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N213 ) );
OA21XL U1890 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n110 ), .A1(n1694),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n112 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n8 ) );
OA21XL U1891 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n118 ), .A1(n1694),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n112 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n9 ) );
OA21XL U1892 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n69 ), .A1(n1694),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n112 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n115 ) );
OAI21XL U1893 ( .A0(n2165), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n54 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n55 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N135 ) );
OAI21XL U1894 ( .A0(n2165), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n65 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n55 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N134 ) );
OAI21XL U1895 ( .A0(n2165), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n66 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n55 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N133 ) );
OAI21XL U1896 ( .A0(n2165), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n67 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n55 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N132 ) );
OAI21XL U1897 ( .A0(n2165), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n25 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n55 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N127 ) );
OAI21XL U1898 ( .A0(n2165), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n31 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n55 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N126 ) );
NOR2XL U1899 ( .A(n2166), .B(\ALU_instance/SHIFTER_GENERIC_I/C50/n21 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N160 ) );
NOR2XL U1900 ( .A(n2167), .B(\ALU_instance/SHIFTER_GENERIC_I/C50/n27 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N159 ) );
NOR2XL U1901 ( .A(n2167), .B(\ALU_instance/SHIFTER_GENERIC_I/C50/n36 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N157 ) );
NAND2XL U1902 ( .A(n2156), .B(\ALU_instance/SHIFTER_GENERIC_I/C86/n84 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n71 ) );
INVXL U1903 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n91 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n118 ) );
NAND2XL U1904 ( .A(n2156), .B(\ALU_instance/SHIFTER_GENERIC_I/C50/n153 ),
.Y(\ALU_instance/SHIFTER_GENERIC_I/C50/n122 ) );
NOR2XL U1905 ( .A(n2167), .B(\ALU_instance/SHIFTER_GENERIC_I/C50/n56 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N155 ) );
NOR2XL U1906 ( .A(n2167), .B(\ALU_instance/SHIFTER_GENERIC_I/C50/n94 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N153 ) );
NOR2XL U1907 ( .A(n2166), .B(\ALU_instance/SHIFTER_GENERIC_I/C50/n14 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N161 ) );
NOR2XL U1908 ( .A(n2166), .B(\ALU_instance/SHIFTER_GENERIC_I/C50/n4 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N162 ) );
NOR2XL U1909 ( .A(n2166), .B(\ALU_instance/SHIFTER_GENERIC_I/C50/n67 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N163 ) );
NAND2XL U1910 ( .A(n2156), .B(n2170), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n107 ) );
CLKBUFX1 U1911 ( .A(\ALU_instance/n6 ), .Y(n2136) );
OR2XL U1912 ( .A(n1599), .B(n2170), .Y(n1694) );
NAND2XL U1913 ( .A(n2156), .B(n2170), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n139 ) );
CLKBUFX1 U1914 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n13 ), .Y(n2128) );
NOR2XL U1915 ( .A(n2165), .B(\ALU_instance/SHIFTER_GENERIC_I/C88/n8 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N234 ) );
CLKBUFX1 U1916 ( .A(\ALU_instance/n5 ), .Y(n2135) );
CLKBUFX1 U1917 ( .A(EX_LOGIC_CW[3]), .Y(n2193) );
INVXL U1918 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n105 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n69 ) );
AND2XL U1919 ( .A(n2171), .B(n2168), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n152 ) );
AND2XL U1920 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n54 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C86/n16 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N168 ) );
INVXL U1921 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n80 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n104 ) );
CLKBUFX1 U1922 ( .A(n1611), .Y(n2131) );
INVXL U1923 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C88/n1 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][7] ) );
INVXL U1924 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C88/n2 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][6] ) );
INVXL U1925 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C88/n3 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][5] ) );
INVXL U1926 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C88/n4 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][4] ) );
INVXL U1927 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C88/n5 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][3] ) );
INVXL U1928 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C88/n6 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][2] ) );
INVXL U1929 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C88/n7 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][1] ) );
INVXL U1930 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C88/n8 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[4][0] ) );
CLKBUFX1 U1931 ( .A(n1643), .Y(n2145) );
INVXL U1932 ( .A(n1616), .Y(n1309) );
INVXL U1933 ( .A(n1199), .Y(n1421) );
CLKBUFX1 U1934 ( .A(n1208), .Y(n2147) );
OAI221XL U1935 ( .A0(\BOOTH_instance/n155 ), .A1(\BOOTH_instance/n307 ),
.B0(\BOOTH_instance/n308 ), .B1(n1718), .C0(\BOOTH_instance/n309 ),
.Y(\BOOTH_instance/n295 ) );
AOI22XL U1936 ( .A0(\BOOTH_instance/n310 ), .A1(\BOOTH_instance/n149 ), .B0(
n2189), .B1(\BOOTH_instance/n282 ), .Y(\BOOTH_instance/n309 ) );
OAI221XL U1937 ( .A0(\BOOTH_instance/n186 ), .A1(n2188), .B0(
\BOOTH_instance/n280 ), .B1(n1603), .C0(\BOOTH_instance/n313 ), .Y(
\BOOTH_instance/n306 ) );
AOI22XL U1938 ( .A0(n2189), .A1(\BOOTH_instance/n188 ), .B0(
\BOOTH_instance/n176 ), .B1(\BOOTH_instance/n310 ), .Y(
\BOOTH_instance/n313 ) );
OAI221XL U1939 ( .A0(\BOOTH_instance/n166 ), .A1(\BOOTH_instance/n307 ),
.B0(\BOOTH_instance/n308 ), .B1(\BOOTH_instance/n158 ), .C0(
\BOOTH_instance/n314 ), .Y(\BOOTH_instance/n302 ) );
OAI21XL U1940 ( .A0(\BOOTH_instance/n150 ), .A1(\BOOTH_instance/n168 ), .B0(
n2108), .Y(\BOOTH_instance/n314 ) );
NOR3XL U1941 ( .A(n2179), .B(n2181), .C(\BOOTH_instance/n453 ), .Y(
\BOOTH_instance/n452 ) );
AOI21XL U1942 ( .A0(\BOOTH_instance/n158 ), .A1(\BOOTH_instance/n166 ), .B0(
\BOOTH_instance/n316 ), .Y(\BOOTH_instance/n304 ) );
NOR4XL U1943 ( .A(\ALU_instance/ADDER_OUT[27] ), .B(
\ALU_instance/ADDER_OUT[26] ), .C(\ALU_instance/ADDER_OUT[25] ), .D(
\ALU_instance/ADDER_OUT[24] ), .Y(
\ALU_instance/COMPARATOR_GENERIC_I/n16 ) );
NOR4XL U1944 ( .A(\ALU_instance/ADDER_OUT[30] ), .B(
\ALU_instance/ADDER_OUT[2] ), .C(\ALU_instance/ADDER_OUT[29] ), .D(
\ALU_instance/ADDER_OUT[28] ), .Y(
\ALU_instance/COMPARATOR_GENERIC_I/n17 ) );
NAND2XL U1945 ( .A(\BOOTH_instance/n348 ), .B(\BOOTH_instance/n345 ), .Y(
\BOOTH_instance/n328 ) );
NAND2XL U1946 ( .A(\BOOTH_instance/n395 ), .B(\BOOTH_instance/n372 ), .Y(
\BOOTH_instance/n373 ) );
NAND2XL U1947 ( .A(\BOOTH_instance/n371 ), .B(\BOOTH_instance/n346 ), .Y(
\BOOTH_instance/n349 ) );
AOI2B1XL U1948 ( .A1N(\BOOTH_instance/n301 ), .A0(\BOOTH_instance/n302 ),
.B0(\BOOTH_instance/n303 ), .Y(\BOOTH_instance/n293 ) );
AOI21XL U1949 ( .A0(\BOOTH_instance/n304 ), .A1(\BOOTH_instance/n305 ), .B0(
\BOOTH_instance/n306 ), .Y(\BOOTH_instance/n301 ) );
NAND2XL U1950 ( .A(\BOOTH_instance/n322 ), .B(\BOOTH_instance/n318 ), .Y(
\BOOTH_instance/n186 ) );
AO22XL U1951 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/C1 ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[5] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/C0 ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/n2 ), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[6] ) );
AO22XL U1952 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/C1 ), .A1(n2134),
.B0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/C0 ), .B1(EX_ADD_SUB),
.Y(\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[1] ) );
AO22XL U1953 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/C1 ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[4] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/C0 ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/n2 ), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[5] ) );
AO22XL U1954 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/C1 ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[3] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/C0 ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/n2 ), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[4] ) );
AO22XL U1955 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/C1 ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[6] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/C0 ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/n2 ), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[7] ) );
AOI22XL U1956 ( .A0(\BOOTH_instance/n352 ), .A1(n2189), .B0(
\BOOTH_instance/n353 ), .B1(\BOOTH_instance/n310 ), .Y(
\BOOTH_instance/n368 ) );
AOI22XL U1957 ( .A0(\BOOTH_instance/n352 ), .A1(n2186), .B0(
\BOOTH_instance/n353 ), .B1(\BOOTH_instance/n272 ), .Y(
\BOOTH_instance/n366 ) );
AOI22XL U1958 ( .A0(\BOOTH_instance/n400 ), .A1(n2179), .B0(
\BOOTH_instance/n401 ), .B1(\BOOTH_instance/n212 ), .Y(
\BOOTH_instance/n413 ) );
AOI21XL U1959 ( .A0(\BOOTH_instance/n398 ), .A1(\BOOTH_instance/n397 ), .B0(
\BOOTH_instance/n316 ), .Y(\BOOTH_instance/partial_products[7][4] ) );
AOI21XL U1960 ( .A0(\BOOTH_instance/n323 ), .A1(\BOOTH_instance/n328 ), .B0(
\BOOTH_instance/n316 ), .Y(\BOOTH_instance/decoded[5][10] ) );
AOI21XL U1961 ( .A0(\BOOTH_instance/n374 ), .A1(\BOOTH_instance/n373 ), .B0(
\BOOTH_instance/n316 ), .Y(\BOOTH_instance/decoded[3][6] ) );
AOI21XL U1962 ( .A0(\BOOTH_instance/n350 ), .A1(\BOOTH_instance/n349 ), .B0(
\BOOTH_instance/n316 ), .Y(\BOOTH_instance/partial_products[4][8] ) );
NAND2XL U1963 ( .A(\BOOTH_instance/n449 ), .B(n1605), .Y(
\BOOTH_instance/n450 ) );
NAND2XL U1964 ( .A(\BOOTH_instance/n457 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C50/n46 ), .Y(\BOOTH_instance/n458 )
);
NOR2XL U1965 ( .A(n2181), .B(\BOOTH_instance/n453 ), .Y(
\BOOTH_instance/n454 ) );
AO22XL U1966 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/C1 ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[7] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/C0 ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/n2 ), .Y(
\ALU_instance/OVERFLOW ) );
OAI31XL U1967 ( .A0(\BOOTH_instance/n145 ), .A1(\BOOTH_instance/n146 ), .A2(
\BOOTH_instance/n147 ), .B0(\BOOTH_instance/n148 ), .Y(
\BOOTH_instance/partial_products[5][31] ) );
OAI21XL U1968 ( .A0(\BOOTH_instance/n149 ), .A1(\BOOTH_instance/n150 ), .B0(
\BOOTH_instance/n151 ), .Y(\BOOTH_instance/n148 ) );
INVXL U1969 ( .A(\BOOTH_instance/n355 ), .Y(\BOOTH_instance/n352 ) );
INVXL U1970 ( .A(\BOOTH_instance/n382 ), .Y(\BOOTH_instance/n376 ) );
NAND3XL U1971 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n46 ), .B(
\BOOTH_instance/n260 ), .C(\BOOTH_instance/n457 ), .Y(
\BOOTH_instance/n456 ) );
NAND2XL U1972 ( .A(\BOOTH_instance/n460 ), .B(n2188), .Y(
\BOOTH_instance/n459 ) );
NAND2XL U1973 ( .A(\BOOTH_instance/n452 ), .B(n2178), .Y(
\BOOTH_instance/n451 ) );
INVXL U1974 ( .A(\BOOTH_instance/n175 ), .Y(\BOOTH_instance/n188 ) );
NAND2XL U1975 ( .A(\BOOTH_instance/n455 ), .B(n2184), .Y(
\BOOTH_instance/n453 ) );
OAI21XL U1976 ( .A0(\BOOTH_instance/n376 ), .A1(\BOOTH_instance/n377 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/N202 ), .Y(\BOOTH_instance/n380 ) );
OAI21XL U1977 ( .A0(\BOOTH_instance/n326 ), .A1(\BOOTH_instance/n327 ), .B0(
n2109), .Y(\BOOTH_instance/n344 ) );
XOR2XL U1978 ( .A(n2133), .B(n1598), .Y(\ALU_instance/INTERNAL_B[1] ) );
XOR2XL U1979 ( .A(n2132), .B(n2156), .Y(\ALU_instance/INTERNAL_B[2] ) );
AO22XL U1980 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S1[1] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[7] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S0[1] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/n2 ), .Y(
\ALU_instance/ADDER_OUT[29] ) );
AO22XL U1981 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S1[1] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[6] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S0[1] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/n2 ), .Y(
\ALU_instance/ADDER_OUT[25] ) );
AO22XL U1982 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S1[2] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[6] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S0[2] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/n2 ), .Y(
\ALU_instance/ADDER_OUT[26] ) );
AO22XL U1983 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S1[2] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[7] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S0[2] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/n2 ), .Y(
\ALU_instance/ADDER_OUT[30] ) );
AO22XL U1984 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S1[3] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[6] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S0[3] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/n2 ), .Y(
\ALU_instance/ADDER_OUT[27] ) );
AO22XL U1985 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S1[3] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[7] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S0[3] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/n2 ), .Y(
\ALU_instance/ADDER_OUT[31] ) );
AND3XL U1986 ( .A(\BOOTH_instance/n449 ), .B(n1605), .C(n1667), .Y(
\BOOTH_instance/n448 ) );
INVXL U1987 ( .A(\BOOTH_instance/n158 ), .Y(\BOOTH_instance/n149 ) );
OR3XL U1988 ( .A(n2170), .B(n2163), .C(\BOOTH_instance/n396 ), .Y(n1695) );
OR3XL U1989 ( .A(n2155), .B(n690), .C(n1597), .Y(n1696) );
INVXL U1990 ( .A(\BOOTH_instance/n290 ), .Y(\BOOTH_instance/n310 ) );
CLKINVX1 U1991 ( .A(n2182), .Y(n2181) );
NAND3XL U1992 ( .A(n1555), .B(n1557), .C(n1551), .Y(n1574) );
CLKINVX1 U1993 ( .A(n2178), .Y(n2177) );
CLKINVX1 U1994 ( .A(n1604), .Y(n2185) );
AND3XL U1995 ( .A(\BOOTH_instance/n306 ), .B(\BOOTH_instance/n305 ), .C(
\BOOTH_instance/n304 ), .Y(\BOOTH_instance/n303 ) );
OAI2BB1XL U1996 ( .A0N(\BOOTH_instance/n283 ), .A1N(\BOOTH_instance/n284 ),
.B0(\BOOTH_instance/n285 ), .Y(\BOOTH_instance/n275 ) );
OAI21XL U1997 ( .A0(\BOOTH_instance/n284 ), .A1(\BOOTH_instance/n283 ), .B0(
\BOOTH_instance/n286 ), .Y(\BOOTH_instance/n285 ) );
NAND2XL U1998 ( .A(\ALU_instance/n21 ), .B(\ALU_instance/n22 ), .Y(
EX_ALU_OUT[0]) );
AOI22XL U1999 ( .A0(\ALU_instance/LOGIC_OUT[0] ), .A1(\ALU_instance/n6 ),
.B0(\ALU_instance/ADDER_OUT[0] ), .B1(n1596), .Y(\ALU_instance/n21 )
);
AO2B2XL U2000 ( .B0(\BOOTH_instance/n263 ), .B1(\BOOTH_instance/n264 ), .A0(
\BOOTH_instance/n265 ), .A1N(\BOOTH_instance/n266 ), .Y(
\BOOTH_instance/n255 ) );
NOR2XL U2001 ( .A(\BOOTH_instance/n264 ), .B(\BOOTH_instance/n263 ), .Y(
\BOOTH_instance/n266 ) );
AO2B2XL U2002 ( .B0(\BOOTH_instance/n253 ), .B1(\BOOTH_instance/n254 ), .A0(
\BOOTH_instance/n255 ), .A1N(\BOOTH_instance/n256 ), .Y(
\BOOTH_instance/n245 ) );
NOR2XL U2003 ( .A(\BOOTH_instance/n254 ), .B(\BOOTH_instance/n253 ), .Y(
\BOOTH_instance/n256 ) );
AO2B2XL U2004 ( .B0(\BOOTH_instance/n243 ), .B1(\BOOTH_instance/n244 ), .A0(
\BOOTH_instance/n245 ), .A1N(\BOOTH_instance/n246 ), .Y(
\BOOTH_instance/n235 ) );
NOR2XL U2005 ( .A(\BOOTH_instance/n244 ), .B(\BOOTH_instance/n243 ), .Y(
\BOOTH_instance/n246 ) );
AO2B2XL U2006 ( .B0(\BOOTH_instance/n233 ), .B1(\BOOTH_instance/n234 ), .A0(
\BOOTH_instance/n235 ), .A1N(\BOOTH_instance/n236 ), .Y(
\BOOTH_instance/n225 ) );
NOR2XL U2007 ( .A(\BOOTH_instance/n234 ), .B(\BOOTH_instance/n233 ), .Y(
\BOOTH_instance/n236 ) );
AO2B2XL U2008 ( .B0(\BOOTH_instance/n213 ), .B1(\BOOTH_instance/n214 ), .A0(
\BOOTH_instance/n215 ), .A1N(\BOOTH_instance/n216 ), .Y(
\BOOTH_instance/n205 ) );
NOR2XL U2009 ( .A(\BOOTH_instance/n214 ), .B(\BOOTH_instance/n213 ), .Y(
\BOOTH_instance/n216 ) );
AO2B2XL U2010 ( .B0(\BOOTH_instance/n273 ), .B1(\BOOTH_instance/n274 ), .A0(
\BOOTH_instance/n275 ), .A1N(\BOOTH_instance/n276 ), .Y(
\BOOTH_instance/n265 ) );
NOR2XL U2011 ( .A(\BOOTH_instance/n274 ), .B(\BOOTH_instance/n273 ), .Y(
\BOOTH_instance/n276 ) );
CLKINVX1 U2012 ( .A(n2176), .Y(n2175) );
CLKINVX1 U2013 ( .A(n2184), .Y(n2183) );
CLKINVX1 U2014 ( .A(n2187), .Y(n2186) );
OAI221XL U2015 ( .A0(n2188), .A1(\BOOTH_instance/n421 ), .B0(
\BOOTH_instance/n280 ), .B1(\BOOTH_instance/n422 ), .C0(
\BOOTH_instance/n429 ), .Y(\BOOTH_instance/decoded[1][5] ) );
AOI22XL U2016 ( .A0(\BOOTH_instance/n424 ), .A1(n2189), .B0(
\BOOTH_instance/n425 ), .B1(\BOOTH_instance/n310 ), .Y(
\BOOTH_instance/n429 ) );
OAI221XL U2017 ( .A0(n2187), .A1(\BOOTH_instance/n421 ), .B0(
\BOOTH_instance/n299 ), .B1(\BOOTH_instance/n422 ), .C0(
\BOOTH_instance/n428 ), .Y(\BOOTH_instance/decoded[1][6] ) );
AOI22XL U2018 ( .A0(\BOOTH_instance/n424 ), .A1(N4721), .B0(
\BOOTH_instance/n425 ), .B1(\BOOTH_instance/n292 ), .Y(
\BOOTH_instance/n428 ) );
OAI222XL U2019 ( .A0(\BOOTH_instance/n259 ), .A1(n2124), .B0(
\BOOTH_instance/n249 ), .B1(\BOOTH_instance/n445 ), .C0(n1604), .C1(
\BOOTH_instance/n447 ), .Y(\BOOTH_instance/N216 ) );
OAI221XL U2020 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n46 ), .A1(
\BOOTH_instance/n421 ), .B0(\BOOTH_instance/n269 ), .B1(
\BOOTH_instance/n422 ), .C0(\BOOTH_instance/n427 ), .Y(
\BOOTH_instance/decoded[1][7] ) );
AOI22XL U2021 ( .A0(\BOOTH_instance/n424 ), .A1(n2186), .B0(
\BOOTH_instance/n425 ), .B1(\BOOTH_instance/n272 ), .Y(
\BOOTH_instance/n427 ) );
XOR2XL U2022 ( .A(\BOOTH_instance/decoded[3][6] ), .B(
\BOOTH_instance/decoded[2][6] ), .Y(
\BOOTH_instance/partial_products[7][6] ) );
OAI221XL U2023 ( .A0(n2188), .A1(\BOOTH_instance/n373 ), .B0(
\BOOTH_instance/n280 ), .B1(\BOOTH_instance/n374 ), .C0(
\BOOTH_instance/n375 ), .Y(\BOOTH_instance/decoded[3][9] ) );
OAI221XL U2024 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n46 ), .A1(
\BOOTH_instance/n397 ), .B0(\BOOTH_instance/n269 ), .B1(
\BOOTH_instance/n398 ), .C0(\BOOTH_instance/n399 ), .Y(
\BOOTH_instance/decoded[2][9] ) );
AOI22XL U2025 ( .A0(\BOOTH_instance/n376 ), .A1(n2189), .B0(
\BOOTH_instance/n377 ), .B1(\BOOTH_instance/n310 ), .Y(
\BOOTH_instance/n375 ) );
XOR2XL U2026 ( .A(\BOOTH_instance/partial_products[4][8] ), .B(
\BOOTH_instance/partial_products[3][8] ), .Y(
\BOOTH_instance/partial_products[7][8] ) );
OAI221XL U2027 ( .A0(n2187), .A1(\BOOTH_instance/n373 ), .B0(
\BOOTH_instance/n299 ), .B1(\BOOTH_instance/n374 ), .C0(
\BOOTH_instance/n394 ), .Y(\BOOTH_instance/decoded[3][10] ) );
OAI221XL U2028 ( .A0(\BOOTH_instance/n260 ), .A1(\BOOTH_instance/n397 ),
.B0(\BOOTH_instance/n259 ), .B1(\BOOTH_instance/n398 ), .C0(
\BOOTH_instance/n418 ), .Y(\BOOTH_instance/decoded[2][10] ) );
AOI22XL U2029 ( .A0(\BOOTH_instance/n376 ), .A1(N4721), .B0(
\BOOTH_instance/n377 ), .B1(\BOOTH_instance/n292 ), .Y(
\BOOTH_instance/n394 ) );
OAI221XL U2030 ( .A0(n2182), .A1(\BOOTH_instance/n421 ), .B0(
\BOOTH_instance/n229 ), .B1(\BOOTH_instance/n422 ), .C0(
\BOOTH_instance/n441 ), .Y(\BOOTH_instance/decoded[1][11] ) );
OAI222XL U2031 ( .A0(\BOOTH_instance/n219 ), .A1(n2124), .B0(
\BOOTH_instance/n209 ), .B1(\BOOTH_instance/n445 ), .C0(n2178), .C1(
\BOOTH_instance/n447 ), .Y(\BOOTH_instance/N220 ) );
AOI22XL U2032 ( .A0(\BOOTH_instance/n424 ), .A1(n2183), .B0(
\BOOTH_instance/n425 ), .B1(\BOOTH_instance/n232 ), .Y(
\BOOTH_instance/n441 ) );
OAI221XL U2033 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n46 ), .A1(
\BOOTH_instance/n373 ), .B0(\BOOTH_instance/n269 ), .B1(
\BOOTH_instance/n374 ), .C0(\BOOTH_instance/n393 ), .Y(
\BOOTH_instance/decoded[3][11] ) );
OAI221XL U2034 ( .A0(n1604), .A1(\BOOTH_instance/n397 ), .B0(
\BOOTH_instance/n249 ), .B1(\BOOTH_instance/n398 ), .C0(
\BOOTH_instance/n417 ), .Y(\BOOTH_instance/decoded[2][11] ) );
AOI22XL U2035 ( .A0(\BOOTH_instance/n376 ), .A1(n2186), .B0(
\BOOTH_instance/n377 ), .B1(\BOOTH_instance/n272 ), .Y(
\BOOTH_instance/n393 ) );
XOR2XL U2036 ( .A(\BOOTH_instance/decoded[5][10] ), .B(
\BOOTH_instance/decoded[4][10] ), .Y(
\BOOTH_instance/partial_products[4][10] ) );
OAI221XL U2037 ( .A0(n2178), .A1(\BOOTH_instance/n421 ), .B0(
\BOOTH_instance/n209 ), .B1(\BOOTH_instance/n422 ), .C0(
\BOOTH_instance/n439 ), .Y(\BOOTH_instance/decoded[1][13] ) );
OAI222XL U2038 ( .A0(\BOOTH_instance/n199 ), .A1(n2124), .B0(
\BOOTH_instance/n189 ), .B1(\BOOTH_instance/n445 ), .C0(n1605), .C1(
\BOOTH_instance/n447 ), .Y(\BOOTH_instance/N222 ) );
AOI22XL U2039 ( .A0(\BOOTH_instance/n424 ), .A1(n2179), .B0(
\BOOTH_instance/n425 ), .B1(\BOOTH_instance/n212 ), .Y(
\BOOTH_instance/n439 ) );
OAI221XL U2040 ( .A0(n2187), .A1(\BOOTH_instance/n349 ), .B0(
\BOOTH_instance/n299 ), .B1(\BOOTH_instance/n350 ), .C0(
\BOOTH_instance/n367 ), .Y(\BOOTH_instance/decoded[4][12] ) );
INVXL U2041 ( .A(\BOOTH_instance/n342 ), .Y(\BOOTH_instance/decoded[5][12] )
);
AOI22XL U2042 ( .A0(\BOOTH_instance/n352 ), .A1(N4721), .B0(
\BOOTH_instance/n353 ), .B1(\BOOTH_instance/n292 ), .Y(
\BOOTH_instance/n367 ) );
OAI221XL U2043 ( .A0(n2176), .A1(\BOOTH_instance/n421 ), .B0(
\BOOTH_instance/n199 ), .B1(\BOOTH_instance/n422 ), .C0(
\BOOTH_instance/n438 ), .Y(\BOOTH_instance/decoded[1][14] ) );
OAI222XL U2044 ( .A0(\BOOTH_instance/n189 ), .A1(n2124), .B0(
\BOOTH_instance/n177 ), .B1(\BOOTH_instance/n445 ), .C0(n1667), .C1(
\BOOTH_instance/n447 ), .Y(\BOOTH_instance/N223 ) );
AOI22XL U2045 ( .A0(\BOOTH_instance/n424 ), .A1(n2177), .B0(
\BOOTH_instance/n425 ), .B1(\BOOTH_instance/n202 ), .Y(
\BOOTH_instance/n438 ) );
OAI221XL U2046 ( .A0(n2188), .A1(\BOOTH_instance/n328 ), .B0(
\BOOTH_instance/n280 ), .B1(\BOOTH_instance/n323 ), .C0(
\BOOTH_instance/n341 ), .Y(\BOOTH_instance/decoded[5][13] ) );
OAI221XL U2047 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n46 ), .A1(
\BOOTH_instance/n349 ), .B0(\BOOTH_instance/n269 ), .B1(
\BOOTH_instance/n350 ), .C0(\BOOTH_instance/n366 ), .Y(
\BOOTH_instance/decoded[4][13] ) );
AOI22XL U2048 ( .A0(\BOOTH_instance/n326 ), .A1(n2189), .B0(
\BOOTH_instance/n327 ), .B1(\BOOTH_instance/n310 ), .Y(
\BOOTH_instance/n341 ) );
OAI221XL U2049 ( .A0(n1605), .A1(\BOOTH_instance/n421 ), .B0(
\BOOTH_instance/n189 ), .B1(\BOOTH_instance/n422 ), .C0(
\BOOTH_instance/n437 ), .Y(\BOOTH_instance/decoded[1][15] ) );
OAI222XL U2050 ( .A0(\BOOTH_instance/n177 ), .A1(n2124), .B0(n1606), .B1(
\BOOTH_instance/n445 ), .C0(\BOOTH_instance/n156 ), .C1(
\BOOTH_instance/n447 ), .Y(\BOOTH_instance/N224 ) );
AOI22XL U2051 ( .A0(\BOOTH_instance/n424 ), .A1(n2175), .B0(
\BOOTH_instance/n425 ), .B1(\BOOTH_instance/n192 ), .Y(
\BOOTH_instance/n437 ) );
XOR2XL U2052 ( .A(\BOOTH_instance/partial_products[6][12] ), .B(
\BOOTH_instance/partial_products[5][12] ), .Y(
\BOOTH_instance/partial_products[8][12] ) );
OAI221XL U2053 ( .A0(n2187), .A1(\BOOTH_instance/n328 ), .B0(
\BOOTH_instance/n299 ), .B1(\BOOTH_instance/n323 ), .C0(
\BOOTH_instance/n340 ), .Y(\BOOTH_instance/decoded[5][14] ) );
OAI221XL U2054 ( .A0(\BOOTH_instance/n260 ), .A1(\BOOTH_instance/n349 ),
.B0(\BOOTH_instance/n259 ), .B1(\BOOTH_instance/n350 ), .C0(
\BOOTH_instance/n365 ), .Y(\BOOTH_instance/decoded[4][14] ) );
AOI22XL U2055 ( .A0(\BOOTH_instance/n326 ), .A1(N4721), .B0(
\BOOTH_instance/n327 ), .B1(\BOOTH_instance/n292 ), .Y(
\BOOTH_instance/n340 ) );
OAI22XL U2056 ( .A0(n1606), .A1(n2124), .B0(\BOOTH_instance/n157 ), .B1(
\BOOTH_instance/n445 ), .Y(\BOOTH_instance/N225 ) );
OAI221XL U2057 ( .A0(n1667), .A1(\BOOTH_instance/n421 ), .B0(
\BOOTH_instance/n177 ), .B1(\BOOTH_instance/n422 ), .C0(
\BOOTH_instance/n436 ), .Y(\BOOTH_instance/decoded[1][16] ) );
AOI22XL U2058 ( .A0(\BOOTH_instance/n424 ), .A1(n2174), .B0(
\BOOTH_instance/n425 ), .B1(\BOOTH_instance/n180 ), .Y(
\BOOTH_instance/n436 ) );
XOR2XL U2059 ( .A(\BOOTH_instance/n305 ), .B(\BOOTH_instance/n304 ), .Y(
\BOOTH_instance/partial_products[5][14] ) );
OAI221XL U2060 ( .A0(n2182), .A1(\BOOTH_instance/n373 ), .B0(
\BOOTH_instance/n229 ), .B1(\BOOTH_instance/n374 ), .C0(
\BOOTH_instance/n389 ), .Y(\BOOTH_instance/decoded[3][15] ) );
OAI221XL U2061 ( .A0(n2178), .A1(\BOOTH_instance/n397 ), .B0(
\BOOTH_instance/n209 ), .B1(\BOOTH_instance/n398 ), .C0(
\BOOTH_instance/n413 ), .Y(\BOOTH_instance/decoded[2][15] ) );
AOI22XL U2062 ( .A0(\BOOTH_instance/n376 ), .A1(n2183), .B0(
\BOOTH_instance/n377 ), .B1(\BOOTH_instance/n232 ), .Y(
\BOOTH_instance/n389 ) );
OAI221XL U2063 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n46 ), .A1(
\BOOTH_instance/n328 ), .B0(\BOOTH_instance/n269 ), .B1(
\BOOTH_instance/n323 ), .C0(\BOOTH_instance/n339 ), .Y(
\BOOTH_instance/decoded[5][15] ) );
OAI221XL U2064 ( .A0(n1604), .A1(\BOOTH_instance/n349 ), .B0(
\BOOTH_instance/n249 ), .B1(\BOOTH_instance/n350 ), .C0(
\BOOTH_instance/n364 ), .Y(\BOOTH_instance/decoded[4][15] ) );
AOI22XL U2065 ( .A0(\BOOTH_instance/n326 ), .A1(n2186), .B0(
\BOOTH_instance/n327 ), .B1(\BOOTH_instance/n272 ), .Y(
\BOOTH_instance/n339 ) );
OAI221XL U2066 ( .A0(\BOOTH_instance/n156 ), .A1(\BOOTH_instance/n421 ),
.B0(n1606), .B1(\BOOTH_instance/n422 ), .C0(\BOOTH_instance/n435 ),
.Y(\BOOTH_instance/decoded[1][17] ) );
AOI22XL U2067 ( .A0(\BOOTH_instance/n424 ), .A1(n2173), .B0(
\BOOTH_instance/n425 ), .B1(\BOOTH_instance/n169 ), .Y(
\BOOTH_instance/n435 ) );
XOR2XL U2068 ( .A(\BOOTH_instance/n302 ), .B(\BOOTH_instance/n311 ), .Y(
\BOOTH_instance/partial_products[5][15] ) );
AOI2B1XL U2069 ( .A1N(\BOOTH_instance/n306 ), .A0(\BOOTH_instance/n312 ),
.B0(\BOOTH_instance/n303 ), .Y(\BOOTH_instance/n311 ) );
NAND2XL U2070 ( .A(\BOOTH_instance/n304 ), .B(\BOOTH_instance/n305 ), .Y(
\BOOTH_instance/n312 ) );
OAI222XL U2071 ( .A0(n1606), .A1(n1696), .B0(\BOOTH_instance/n156 ), .B1(
\BOOTH_instance/n434 ), .C0(\BOOTH_instance/n157 ), .C1(
\BOOTH_instance/n422 ), .Y(\BOOTH_instance/decoded[1][18] ) );
OAI221XL U2072 ( .A0(n2178), .A1(\BOOTH_instance/n373 ), .B0(
\BOOTH_instance/n209 ), .B1(\BOOTH_instance/n374 ), .C0(
\BOOTH_instance/n387 ), .Y(\BOOTH_instance/decoded[3][17] ) );
OAI221XL U2073 ( .A0(n1605), .A1(\BOOTH_instance/n397 ), .B0(
\BOOTH_instance/n189 ), .B1(\BOOTH_instance/n398 ), .C0(
\BOOTH_instance/n411 ), .Y(\BOOTH_instance/decoded[2][17] ) );
AOI22XL U2074 ( .A0(\BOOTH_instance/n376 ), .A1(n2179), .B0(
\BOOTH_instance/n377 ), .B1(\BOOTH_instance/n212 ), .Y(
\BOOTH_instance/n387 ) );
XNOR2XL U2075 ( .A(\BOOTH_instance/n287 ), .B(\BOOTH_instance/n284 ), .Y(
\BOOTH_instance/partial_products[5][17] ) );
XNOR2XL U2076 ( .A(\BOOTH_instance/n286 ), .B(\BOOTH_instance/n283 ), .Y(
\BOOTH_instance/n287 ) );
OAI221XL U2077 ( .A0(n2176), .A1(\BOOTH_instance/n373 ), .B0(
\BOOTH_instance/n199 ), .B1(\BOOTH_instance/n374 ), .C0(
\BOOTH_instance/n386 ), .Y(\BOOTH_instance/decoded[3][18] ) );
OAI221XL U2078 ( .A0(n1667), .A1(\BOOTH_instance/n397 ), .B0(
\BOOTH_instance/n177 ), .B1(\BOOTH_instance/n398 ), .C0(
\BOOTH_instance/n410 ), .Y(\BOOTH_instance/decoded[2][18] ) );
AOI22XL U2079 ( .A0(\BOOTH_instance/n376 ), .A1(n2177), .B0(
\BOOTH_instance/n377 ), .B1(\BOOTH_instance/n202 ), .Y(
\BOOTH_instance/n386 ) );
NOR2XL U2080 ( .A(\BOOTH_instance/n315 ), .B(n2188), .Y(
\BOOTH_instance/decoded[8][19] ) );
XNOR2XL U2081 ( .A(\BOOTH_instance/n277 ), .B(\BOOTH_instance/n274 ), .Y(
\BOOTH_instance/partial_products[5][18] ) );
XNOR2XL U2082 ( .A(\BOOTH_instance/n275 ), .B(\BOOTH_instance/n273 ), .Y(
\BOOTH_instance/n277 ) );
OAI221XL U2083 ( .A0(n1605), .A1(\BOOTH_instance/n373 ), .B0(
\BOOTH_instance/n189 ), .B1(\BOOTH_instance/n374 ), .C0(
\BOOTH_instance/n385 ), .Y(\BOOTH_instance/decoded[3][19] ) );
OAI221XL U2084 ( .A0(\BOOTH_instance/n156 ), .A1(\BOOTH_instance/n397 ),
.B0(n1606), .B1(\BOOTH_instance/n398 ), .C0(\BOOTH_instance/n409 ),
.Y(\BOOTH_instance/decoded[2][19] ) );
AOI22XL U2085 ( .A0(\BOOTH_instance/n376 ), .A1(n2175), .B0(
\BOOTH_instance/n377 ), .B1(\BOOTH_instance/n192 ), .Y(
\BOOTH_instance/n385 ) );
OAI221XL U2086 ( .A0(n2182), .A1(\BOOTH_instance/n328 ), .B0(
\BOOTH_instance/n229 ), .B1(\BOOTH_instance/n323 ), .C0(
\BOOTH_instance/n335 ), .Y(\BOOTH_instance/decoded[5][19] ) );
OAI221XL U2087 ( .A0(n2178), .A1(\BOOTH_instance/n349 ), .B0(
\BOOTH_instance/n209 ), .B1(\BOOTH_instance/n350 ), .C0(
\BOOTH_instance/n360 ), .Y(\BOOTH_instance/decoded[4][19] ) );
AOI22XL U2088 ( .A0(\BOOTH_instance/n326 ), .A1(n2183), .B0(
\BOOTH_instance/n327 ), .B1(\BOOTH_instance/n232 ), .Y(
\BOOTH_instance/n335 ) );
NOR2XL U2089 ( .A(\BOOTH_instance/n315 ), .B(n2187), .Y(
\BOOTH_instance/decoded[8][20] ) );
XNOR2XL U2090 ( .A(\BOOTH_instance/n267 ), .B(\BOOTH_instance/n264 ), .Y(
\BOOTH_instance/partial_products[5][19] ) );
XNOR2XL U2091 ( .A(\BOOTH_instance/n265 ), .B(\BOOTH_instance/n263 ), .Y(
\BOOTH_instance/n267 ) );
OAI222XL U2092 ( .A0(n1606), .A1(n1695), .B0(\BOOTH_instance/n156 ), .B1(
\BOOTH_instance/n408 ), .C0(\BOOTH_instance/n157 ), .C1(
\BOOTH_instance/n398 ), .Y(\BOOTH_instance/decoded[2][20] ) );
OAI221XL U2093 ( .A0(n1667), .A1(\BOOTH_instance/n373 ), .B0(
\BOOTH_instance/n177 ), .B1(\BOOTH_instance/n374 ), .C0(
\BOOTH_instance/n384 ), .Y(\BOOTH_instance/decoded[3][20] ) );
AOI22XL U2094 ( .A0(\BOOTH_instance/n376 ), .A1(n2174), .B0(
\BOOTH_instance/n377 ), .B1(\BOOTH_instance/n180 ), .Y(
\BOOTH_instance/n384 ) );
NOR2XL U2095 ( .A(\BOOTH_instance/n315 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C50/n46 ), .Y(
\BOOTH_instance/decoded[8][21] ) );
XNOR2XL U2096 ( .A(\BOOTH_instance/n257 ), .B(\BOOTH_instance/n254 ), .Y(
\BOOTH_instance/partial_products[5][20] ) );
XNOR2XL U2097 ( .A(\BOOTH_instance/n255 ), .B(\BOOTH_instance/n253 ), .Y(
\BOOTH_instance/n257 ) );
OAI221XL U2098 ( .A0(\BOOTH_instance/n156 ), .A1(\BOOTH_instance/n373 ),
.B0(n1606), .B1(\BOOTH_instance/n374 ), .C0(\BOOTH_instance/n383 ),
.Y(\BOOTH_instance/decoded[3][21] ) );
AOI22XL U2099 ( .A0(\BOOTH_instance/n376 ), .A1(n2173), .B0(
\BOOTH_instance/n377 ), .B1(\BOOTH_instance/n169 ), .Y(
\BOOTH_instance/n383 ) );
OAI221XL U2100 ( .A0(n2178), .A1(\BOOTH_instance/n328 ), .B0(
\BOOTH_instance/n209 ), .B1(\BOOTH_instance/n323 ), .C0(
\BOOTH_instance/n333 ), .Y(\BOOTH_instance/decoded[5][21] ) );
OAI221XL U2101 ( .A0(n1605), .A1(\BOOTH_instance/n349 ), .B0(
\BOOTH_instance/n189 ), .B1(\BOOTH_instance/n350 ), .C0(
\BOOTH_instance/n358 ), .Y(\BOOTH_instance/decoded[4][21] ) );
AOI22XL U2102 ( .A0(\BOOTH_instance/n326 ), .A1(n2179), .B0(
\BOOTH_instance/n327 ), .B1(\BOOTH_instance/n212 ), .Y(
\BOOTH_instance/n333 ) );
NOR2XL U2103 ( .A(\BOOTH_instance/n315 ), .B(\BOOTH_instance/n260 ), .Y(
\BOOTH_instance/decoded[8][22] ) );
XNOR2XL U2104 ( .A(\BOOTH_instance/n247 ), .B(\BOOTH_instance/n244 ), .Y(
\BOOTH_instance/partial_products[5][21] ) );
XNOR2XL U2105 ( .A(\BOOTH_instance/n245 ), .B(\BOOTH_instance/n243 ), .Y(
\BOOTH_instance/n247 ) );
OAI222XL U2106 ( .A0(n1606), .A1(n1704), .B0(\BOOTH_instance/n156 ), .B1(
\BOOTH_instance/n382 ), .C0(\BOOTH_instance/n157 ), .C1(
\BOOTH_instance/n374 ), .Y(\BOOTH_instance/decoded[3][22] ) );
OAI221XL U2107 ( .A0(n2176), .A1(\BOOTH_instance/n328 ), .B0(
\BOOTH_instance/n199 ), .B1(\BOOTH_instance/n323 ), .C0(
\BOOTH_instance/n332 ), .Y(\BOOTH_instance/decoded[5][22] ) );
OAI221XL U2108 ( .A0(n1667), .A1(\BOOTH_instance/n349 ), .B0(
\BOOTH_instance/n177 ), .B1(\BOOTH_instance/n350 ), .C0(
\BOOTH_instance/n357 ), .Y(\BOOTH_instance/decoded[4][22] ) );
AOI22XL U2109 ( .A0(\BOOTH_instance/n326 ), .A1(n2177), .B0(
\BOOTH_instance/n327 ), .B1(\BOOTH_instance/n202 ), .Y(
\BOOTH_instance/n332 ) );
NOR2XL U2110 ( .A(\BOOTH_instance/n315 ), .B(n1604), .Y(
\BOOTH_instance/decoded[8][23] ) );
XNOR2XL U2111 ( .A(\BOOTH_instance/n237 ), .B(\BOOTH_instance/n234 ), .Y(
\BOOTH_instance/partial_products[5][22] ) );
XNOR2XL U2112 ( .A(\BOOTH_instance/n235 ), .B(\BOOTH_instance/n233 ), .Y(
\BOOTH_instance/n237 ) );
OAI221XL U2113 ( .A0(n1605), .A1(\BOOTH_instance/n328 ), .B0(
\BOOTH_instance/n189 ), .B1(\BOOTH_instance/n323 ), .C0(
\BOOTH_instance/n331 ), .Y(\BOOTH_instance/decoded[5][23] ) );
OAI221XL U2114 ( .A0(\BOOTH_instance/n156 ), .A1(\BOOTH_instance/n349 ),
.B0(n1606), .B1(\BOOTH_instance/n350 ), .C0(\BOOTH_instance/n356 ),
.Y(\BOOTH_instance/decoded[4][23] ) );
AOI22XL U2115 ( .A0(\BOOTH_instance/n326 ), .A1(n2175), .B0(
\BOOTH_instance/n327 ), .B1(\BOOTH_instance/n192 ), .Y(
\BOOTH_instance/n331 ) );
NOR2XL U2116 ( .A(\BOOTH_instance/n315 ), .B(n2184), .Y(
\BOOTH_instance/decoded[8][24] ) );
OAI222XL U2117 ( .A0(\BOOTH_instance/n156 ), .A1(\BOOTH_instance/n355 ),
.B0(\BOOTH_instance/n157 ), .B1(\BOOTH_instance/n350 ), .C0(n1606),
.C1(n1703), .Y(\BOOTH_instance/decoded[4][24] ) );
OAI221XL U2118 ( .A0(n1667), .A1(\BOOTH_instance/n328 ), .B0(
\BOOTH_instance/n177 ), .B1(\BOOTH_instance/n323 ), .C0(
\BOOTH_instance/n330 ), .Y(\BOOTH_instance/decoded[5][24] ) );
AOI22XL U2119 ( .A0(\BOOTH_instance/n326 ), .A1(n2174), .B0(
\BOOTH_instance/n327 ), .B1(\BOOTH_instance/n180 ), .Y(
\BOOTH_instance/n330 ) );
NOR2XL U2120 ( .A(\BOOTH_instance/n315 ), .B(n2182), .Y(
\BOOTH_instance/decoded[8][25] ) );
XNOR2XL U2121 ( .A(\BOOTH_instance/n217 ), .B(\BOOTH_instance/n214 ), .Y(
\BOOTH_instance/partial_products[5][24] ) );
XNOR2XL U2122 ( .A(\BOOTH_instance/n215 ), .B(\BOOTH_instance/n213 ), .Y(
\BOOTH_instance/n217 ) );
OAI221XL U2123 ( .A0(\BOOTH_instance/n156 ), .A1(\BOOTH_instance/n328 ),
.B0(n1606), .B1(\BOOTH_instance/n323 ), .C0(\BOOTH_instance/n329 ),
.Y(\BOOTH_instance/decoded[5][25] ) );
AOI22XL U2124 ( .A0(\BOOTH_instance/n326 ), .A1(n2173), .B0(
\BOOTH_instance/n327 ), .B1(\BOOTH_instance/n169 ), .Y(
\BOOTH_instance/n329 ) );
OAI222XL U2125 ( .A0(n1606), .A1(n1700), .B0(\BOOTH_instance/n156 ), .B1(
n1702), .C0(\BOOTH_instance/n157 ), .C1(\BOOTH_instance/n323 ), .Y(
\BOOTH_instance/decoded[5][26] ) );
NOR2XL U2126 ( .A(\BOOTH_instance/n315 ), .B(n2178), .Y(
\BOOTH_instance/decoded[8][27] ) );
XNOR2XL U2127 ( .A(\BOOTH_instance/n197 ), .B(\BOOTH_instance/n194 ), .Y(
\BOOTH_instance/partial_products[5][26] ) );
XNOR2XL U2128 ( .A(\BOOTH_instance/n195 ), .B(\BOOTH_instance/n193 ), .Y(
\BOOTH_instance/n197 ) );
NOR2XL U2129 ( .A(\BOOTH_instance/n315 ), .B(n2176), .Y(
\BOOTH_instance/decoded[8][28] ) );
NOR2XL U2130 ( .A(\BOOTH_instance/n315 ), .B(n1605), .Y(
\BOOTH_instance/decoded[8][29] ) );
AND2XL U2131 ( .A(\BOOTH_instance/N211 ), .B(\BOOTH_instance/decoded[1][2] ),
.Y(\BOOTH_instance/add_7_root_add_53_G7/carry[3] ) );
OAI221XL U2132 ( .A0(\BOOTH_instance/n307 ), .A1(\BOOTH_instance/n397 ),
.B0(\BOOTH_instance/n308 ), .B1(\BOOTH_instance/n398 ), .C0(
\BOOTH_instance/n406 ), .Y(\BOOTH_instance/partial_products[7][5] ) );
AND2XL U2133 ( .A(\BOOTH_instance/partial_products[7][4] ), .B(
\BOOTH_instance/partial_products[8][4] ), .Y(
\BOOTH_instance/add_0_root_add_53_G7/carry[5] ) );
OAI21XL U2134 ( .A0(\BOOTH_instance/n400 ), .A1(\BOOTH_instance/n401 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/N202 ), .Y(\BOOTH_instance/n406 ) );
OAI221XL U2135 ( .A0(\BOOTH_instance/n307 ), .A1(\BOOTH_instance/n373 ),
.B0(\BOOTH_instance/n308 ), .B1(\BOOTH_instance/n374 ), .C0(
\BOOTH_instance/n380 ), .Y(\BOOTH_instance/decoded[3][7] ) );
OAI221XL U2136 ( .A0(\BOOTH_instance/n307 ), .A1(\BOOTH_instance/n349 ),
.B0(\BOOTH_instance/n308 ), .B1(\BOOTH_instance/n350 ), .C0(
\BOOTH_instance/n351 ), .Y(\BOOTH_instance/partial_products[4][9] ) );
AND2XL U2137 ( .A(\BOOTH_instance/partial_products[3][8] ), .B(
\BOOTH_instance/partial_products[4][8] ), .Y(
\BOOTH_instance/add_2_root_add_53_G7/carry[9] ) );
OAI21XL U2138 ( .A0(\BOOTH_instance/n352 ), .A1(\BOOTH_instance/n353 ), .B0(
n2109), .Y(\BOOTH_instance/n351 ) );
OAI221XL U2139 ( .A0(\BOOTH_instance/n307 ), .A1(\BOOTH_instance/n328 ),
.B0(\BOOTH_instance/n308 ), .B1(\BOOTH_instance/n323 ), .C0(
\BOOTH_instance/n344 ), .Y(\BOOTH_instance/decoded[5][11] ) );
OAI221XL U2140 ( .A0(n2188), .A1(\BOOTH_instance/n349 ), .B0(
\BOOTH_instance/n280 ), .B1(\BOOTH_instance/n350 ), .C0(
\BOOTH_instance/n368 ), .Y(\BOOTH_instance/decoded[4][11] ) );
AND2XL U2141 ( .A(\BOOTH_instance/decoded[4][10] ), .B(
\BOOTH_instance/decoded[5][10] ), .Y(
\BOOTH_instance/add_5_root_add_53_G7/carry[11] ) );
OAI221XL U2142 ( .A0(\BOOTH_instance/n307 ), .A1(\BOOTH_instance/n186 ),
.B0(\BOOTH_instance/n308 ), .B1(n1603), .C0(\BOOTH_instance/n321 ),
.Y(\BOOTH_instance/partial_products[5][13] ) );
AND2XL U2143 ( .A(\BOOTH_instance/partial_products[5][12] ), .B(
\BOOTH_instance/partial_products[6][12] ), .Y(
\BOOTH_instance/add_1_root_add_53_G7/carry[13] ) );
OAI21XL U2144 ( .A0(\BOOTH_instance/n188 ), .A1(\BOOTH_instance/n176 ), .B0(
n2108), .Y(\BOOTH_instance/n321 ) );
NOR2XL U2145 ( .A(\BOOTH_instance/n315 ), .B(\BOOTH_instance/n307 ), .Y(
\BOOTH_instance/decoded[8][17] ) );
AND2XL U2146 ( .A(\BOOTH_instance/decoded[8][16] ), .B(
\BOOTH_instance/partial_products[2][16] ), .Y(
\BOOTH_instance/add_3_root_add_53_G7/carry[17] ) );
NOR2XL U2147 ( .A(\BOOTH_instance/n315 ), .B(n1667), .Y(
\BOOTH_instance/decoded[8][30] ) );
XOR2XL U2148 ( .A(n2132), .B(n2167), .Y(\ALU_instance/INTERNAL_B[4] ) );
AO22XL U2149 ( .A0(EX_MULT_OUT[31]), .A1(n2142), .B0(EX_ALU_OUT[31]), .B1(
n2141), .Y(N4891) );
OAI2BB1XL U2150 ( .A0N(\ALU_instance/ADDER_OUT[31] ), .A1N(n1596), .B0(
\ALU_instance/n39 ), .Y(EX_ALU_OUT[31]) );
AOI22XL U2151 ( .A0(\ALU_instance/SHIFTER_OUT[31] ), .A1(\ALU_instance/n5 ),
.B0(\ALU_instance/LOGIC_OUT[31] ), .B1(\ALU_instance/n6 ), .Y(
\ALU_instance/n39 ) );
AOI221XL U2152 ( .A0(n2121), .A1(n2175), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n52 ), .B1(n2174), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n148 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n59 ) );
AO22XL U2153 ( .A0(n2177), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ),
.B0(n2179), .B1(\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n148 ) );
AOI221XL U2154 ( .A0(n2121), .A1(n2177), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n52 ), .B1(n2175), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n94 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n2 ) );
AO22XL U2155 ( .A0(n2179), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ),
.B0(n2181), .B1(\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n94 ) );
AOI221XL U2156 ( .A0(n2121), .A1(n2179), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n52 ), .B1(n2177), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n151 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n12 ) );
AO22XL U2157 ( .A0(n2181), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ),
.B0(n2183), .B1(\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n151 ) );
AOI222XL U2158 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n76 ), .A1(n1592),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C50/n77 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n74 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n78 ), .C1(n1594), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n27 ) );
AOI222XL U2159 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n68 ), .A1(n1592),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C50/n70 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n74 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n11 ), .C1(n1594), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n33 ) );
AOI222XL U2160 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n25 ), .A1(n1594),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C50/n75 ), .B1(n1592), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n90 ), .C1(n2171), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n39 ) );
OAI222XL U2161 ( .A0(n1606), .A1(n1701), .B0(\BOOTH_instance/n156 ), .B1(
\BOOTH_instance/n175 ), .C0(\BOOTH_instance/n157 ), .C1(n1603), .Y(
\BOOTH_instance/n171 ) );
AOI222XL U2162 ( .A0(n2109), .A1(\ALU_instance/SHIFTER_GENERIC_I/n13 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/N105 ), .B1(n2129), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N137 ), .C1(n1612), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n86 ) );
OAI221XL U2163 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n35 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n38 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n94 ), .B1(n2168), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n150 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N137 ) );
OAI221XL U2164 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n34 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n38 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n108 ), .B1(n2168), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n149 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N105 ) );
AOI222XL U2165 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n10 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n16 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n16 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n151 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n8 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n19 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n150 ) );
NAND2XL U2166 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n39 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n40 ), .Y(
\ALU_instance/SHIFTER_OUT[30] ) );
NAND2XL U2167 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N264 ), .B(n2131), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n39 ) );
AOI222XL U2168 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N232 ), .A1(n2128),
.B0(\ALU_instance/SHIFTER_GENERIC_I/N135 ), .B1(n1613), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N167 ), .C1(n2130), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n40 ) );
NAND2XL U2169 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n43 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n44 ), .Y(
\ALU_instance/SHIFTER_OUT[29] ) );
NAND2XL U2170 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N263 ), .B(n2131), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n43 ) );
AOI222XL U2171 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N231 ), .A1(n2128),
.B0(\ALU_instance/SHIFTER_GENERIC_I/N134 ), .B1(n1613), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N166 ), .C1(n2130), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n44 ) );
NAND2XL U2172 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n45 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n46 ), .Y(
\ALU_instance/SHIFTER_OUT[28] ) );
NAND2XL U2173 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N262 ), .B(n2131), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n45 ) );
AOI222XL U2174 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N230 ), .A1(n2128),
.B0(\ALU_instance/SHIFTER_GENERIC_I/N133 ), .B1(n1613), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N165 ), .C1(n2130), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n46 ) );
NAND2XL U2175 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n63 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n64 ), .Y(
\ALU_instance/SHIFTER_OUT[1] ) );
NAND2XL U2176 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N235 ), .B(n1611), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n63 ) );
AOI222XL U2177 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N203 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/n13 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/N106 ), .B1(n1613), .C0(
\ALU_instance/SHIFTER_GENERIC_I/N138 ), .C1(n1612), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n64 ) );
NOR2XL U2178 ( .A(n2165), .B(\ALU_instance/SHIFTER_GENERIC_I/C88/n7 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N235 ) );
OAI221XL U2179 ( .A0(n2124), .A1(n2176), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n22 ), .B1(n2178), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n148 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n62 ) );
AOI22XL U2180 ( .A0(n2174), .A1(n2127), .B0(n2173), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n148 ) );
OAI221XL U2181 ( .A0(n2124), .A1(n1604), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n22 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n155 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n156 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n76 ) );
AOI22XL U2182 ( .A0(n2183), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n25 ),
.B0(n2181), .B1(\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n156 ) );
OAI221XL U2183 ( .A0(n2125), .A1(n2182), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n22 ), .B1(n2184), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n172 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n90 ) );
AOI22XL U2184 ( .A0(n2179), .A1(n2127), .B0(n2177), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n172 ) );
OAI221XL U2185 ( .A0(n2125), .A1(n2184), .B0(n2126), .B1(n1604), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n178 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n97 ) );
AOI22XL U2186 ( .A0(n2181), .A1(n2127), .B0(n2179), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n178 ) );
OAI221XL U2187 ( .A0(n2124), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n155 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n22 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n166 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n167 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n83 ) );
AOI22XL U2188 ( .A0(n2185), .A1(n2127), .B0(n2183), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n167 ) );
AOI221XL U2189 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n102 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n103 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n83 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n104 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n105 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n56 ) );
AO22XL U2190 ( .A0(n1595), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n84 ),
.B0(n1594), .B1(\ALU_instance/SHIFTER_GENERIC_I/C48/n29 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n105 ) );
AOI221XL U2191 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n69 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n103 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n71 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n104 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n106 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n91 ) );
AO22XL U2192 ( .A0(n1595), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n11 ),
.B0(n1594), .B1(\ALU_instance/SHIFTER_GENERIC_I/C48/n9 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n106 ) );
AOI221XL U2193 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n69 ), .A1(n1595),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n71 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n75 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n73 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n4 ) );
AOI221XL U2194 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n82 ), .A1(n1592),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n83 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n75 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n84 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n4 ) );
AOI221XL U2195 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n91 ), .A1(n1592),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n92 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n75 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n84 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n5 ) );
AOI221XL U2196 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n98 ), .A1(n1592),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n99 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n75 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n84 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n6 ) );
INVXL U2197 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n100 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n98 ) );
AOI221XL U2198 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n105 ), .A1(n1592),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n74 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n75 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n84 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n7 ) );
AOI221XL U2199 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n17 ), .A1(n1595),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n16 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n75 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n157 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n108 ) );
OAI2BB2XL U2200 ( .B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n107 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n89 ), .A0N(
\ALU_instance/SHIFTER_GENERIC_I/C48/n75 ), .A1N(
\ALU_instance/SHIFTER_GENERIC_I/C48/n104 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n157 ) );
AOI221XL U2201 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n70 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n92 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n68 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n74 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n93 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n79 ) );
AO22XL U2202 ( .A0(n1592), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n11 ),
.B0(n1594), .B1(\ALU_instance/SHIFTER_GENERIC_I/C50/n9 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n93 ) );
AOI221XL U2203 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n78 ), .A1(n1592),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C50/n31 ), .B1(n1594), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n91 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n56 ) );
AO22XL U2204 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n92 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n77 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n74 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n76 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n91 ) );
AOI221XL U2205 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n18 ), .A1(n1592),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C50/n17 ), .B1(n1594), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n157 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n94 ) );
AO22XL U2206 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n92 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n65 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n74 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n72 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n157 ) );
OAI221XL U2207 ( .A0(\BOOTH_instance/n158 ), .A1(\BOOTH_instance/n269 ),
.B0(\BOOTH_instance/n166 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n46 ), .C0(\BOOTH_instance/n271 ),
.Y(\BOOTH_instance/n263 ) );
AOI22XL U2208 ( .A0(n2186), .A1(\BOOTH_instance/n168 ), .B0(
\BOOTH_instance/n272 ), .B1(\BOOTH_instance/n150 ), .Y(
\BOOTH_instance/n271 ) );
OAI221XL U2209 ( .A0(\BOOTH_instance/n158 ), .A1(\BOOTH_instance/n239 ),
.B0(\BOOTH_instance/n166 ), .B1(n2184), .C0(\BOOTH_instance/n241 ),
.Y(\BOOTH_instance/n233 ) );
AOI22XL U2210 ( .A0(n2185), .A1(\BOOTH_instance/n168 ), .B0(
\BOOTH_instance/n242 ), .B1(\BOOTH_instance/n150 ), .Y(
\BOOTH_instance/n241 ) );
OAI221XL U2211 ( .A0(\BOOTH_instance/n158 ), .A1(\BOOTH_instance/n209 ),
.B0(\BOOTH_instance/n166 ), .B1(n2178), .C0(\BOOTH_instance/n211 ),
.Y(\BOOTH_instance/n203 ) );
AOI22XL U2212 ( .A0(n2179), .A1(\BOOTH_instance/n168 ), .B0(
\BOOTH_instance/n212 ), .B1(\BOOTH_instance/n150 ), .Y(
\BOOTH_instance/n211 ) );
OAI221XL U2213 ( .A0(\BOOTH_instance/n158 ), .A1(\BOOTH_instance/n177 ),
.B0(n1667), .B1(\BOOTH_instance/n166 ), .C0(\BOOTH_instance/n179 ),
.Y(\BOOTH_instance/n170 ) );
AOI22XL U2214 ( .A0(n2174), .A1(\BOOTH_instance/n168 ), .B0(
\BOOTH_instance/n180 ), .B1(\BOOTH_instance/n150 ), .Y(
\BOOTH_instance/n179 ) );
OAI221XL U2215 ( .A0(\BOOTH_instance/n155 ), .A1(n2188), .B0(n1718), .B1(
\BOOTH_instance/n280 ), .C0(\BOOTH_instance/n281 ), .Y(
\BOOTH_instance/n273 ) );
AOI22XL U2216 ( .A0(\BOOTH_instance/n272 ), .A1(\BOOTH_instance/n149 ), .B0(
n2186), .B1(\BOOTH_instance/n282 ), .Y(\BOOTH_instance/n281 ) );
OAI221XL U2217 ( .A0(\BOOTH_instance/n186 ), .A1(n2184), .B0(n1603), .B1(
\BOOTH_instance/n239 ), .C0(\BOOTH_instance/n258 ), .Y(
\BOOTH_instance/n254 ) );
AOI22XL U2218 ( .A0(n2185), .A1(\BOOTH_instance/n188 ), .B0(
\BOOTH_instance/n242 ), .B1(\BOOTH_instance/n176 ), .Y(
\BOOTH_instance/n258 ) );
OAI221XL U2219 ( .A0(\BOOTH_instance/n186 ), .A1(n2182), .B0(n1603), .B1(
\BOOTH_instance/n229 ), .C0(\BOOTH_instance/n248 ), .Y(
\BOOTH_instance/n244 ) );
AOI22XL U2220 ( .A0(n2183), .A1(\BOOTH_instance/n188 ), .B0(
\BOOTH_instance/n232 ), .B1(\BOOTH_instance/n176 ), .Y(
\BOOTH_instance/n248 ) );
OAI221XL U2221 ( .A0(\BOOTH_instance/n186 ), .A1(n2178), .B0(n1603), .B1(
\BOOTH_instance/n209 ), .C0(\BOOTH_instance/n228 ), .Y(
\BOOTH_instance/n224 ) );
AOI22XL U2222 ( .A0(n2179), .A1(\BOOTH_instance/n188 ), .B0(
\BOOTH_instance/n212 ), .B1(\BOOTH_instance/n176 ), .Y(
\BOOTH_instance/n228 ) );
OAI221XL U2223 ( .A0(\BOOTH_instance/n186 ), .A1(n2176), .B0(n1603), .B1(
\BOOTH_instance/n199 ), .C0(\BOOTH_instance/n218 ), .Y(
\BOOTH_instance/n214 ) );
AOI22XL U2224 ( .A0(n2177), .A1(\BOOTH_instance/n188 ), .B0(
\BOOTH_instance/n202 ), .B1(\BOOTH_instance/n176 ), .Y(
\BOOTH_instance/n218 ) );
OAI221XL U2225 ( .A0(\BOOTH_instance/n186 ), .A1(n1605), .B0(n1603), .B1(
\BOOTH_instance/n189 ), .C0(\BOOTH_instance/n208 ), .Y(
\BOOTH_instance/n204 ) );
AOI22XL U2226 ( .A0(n2175), .A1(\BOOTH_instance/n188 ), .B0(
\BOOTH_instance/n192 ), .B1(\BOOTH_instance/n176 ), .Y(
\BOOTH_instance/n208 ) );
OAI221XL U2227 ( .A0(n1667), .A1(\BOOTH_instance/n186 ), .B0(
\BOOTH_instance/n177 ), .B1(n1603), .C0(\BOOTH_instance/n198 ), .Y(
\BOOTH_instance/n194 ) );
AOI22XL U2228 ( .A0(n2174), .A1(\BOOTH_instance/n188 ), .B0(
\BOOTH_instance/n180 ), .B1(\BOOTH_instance/n176 ), .Y(
\BOOTH_instance/n198 ) );
OAI221XL U2229 ( .A0(\BOOTH_instance/n156 ), .A1(\BOOTH_instance/n186 ),
.B0(n1606), .B1(n1603), .C0(\BOOTH_instance/n187 ), .Y(
\BOOTH_instance/n182 ) );
AOI22XL U2230 ( .A0(\BOOTH_instance/n188 ), .A1(n2173), .B0(
\BOOTH_instance/n176 ), .B1(\BOOTH_instance/n169 ), .Y(
\BOOTH_instance/n187 ) );
OAI221XL U2231 ( .A0(\BOOTH_instance/n186 ), .A1(n2187), .B0(n1603), .B1(
\BOOTH_instance/n299 ), .C0(\BOOTH_instance/n300 ), .Y(
\BOOTH_instance/n296 ) );
AOI22XL U2232 ( .A0(N4721), .A1(\BOOTH_instance/n188 ), .B0(
\BOOTH_instance/n292 ), .B1(\BOOTH_instance/n176 ), .Y(
\BOOTH_instance/n300 ) );
OAI221XL U2233 ( .A0(\BOOTH_instance/n186 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n46 ), .B0(n1603), .B1(
\BOOTH_instance/n269 ), .C0(\BOOTH_instance/n288 ), .Y(
\BOOTH_instance/n284 ) );
AOI22XL U2234 ( .A0(n2186), .A1(\BOOTH_instance/n188 ), .B0(
\BOOTH_instance/n272 ), .B1(\BOOTH_instance/n176 ), .Y(
\BOOTH_instance/n288 ) );
OAI222XL U2235 ( .A0(n1718), .A1(n1606), .B0(\BOOTH_instance/n155 ), .B1(
\BOOTH_instance/n156 ), .C0(\BOOTH_instance/n157 ), .C1(
\BOOTH_instance/n158 ), .Y(\BOOTH_instance/n145 ) );
OAI221XL U2236 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n116 ), .A1(n1691),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n9 ), .B1(n2168), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n117 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N221 ) );
INVXL U2237 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n15 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n116 ) );
AOI222XL U2238 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n55 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n56 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n18 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n90 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n14 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n92 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n117 ) );
OAI221XL U2239 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n125 ), .A1(n1691),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n115 ), .B1(n2168), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n126 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N219 ) );
INVXL U2240 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n39 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n125 ) );
AOI222XL U2241 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n55 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n67 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n18 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n76 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n14 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n74 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n126 ) );
OAI221XL U2242 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n18 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n3 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n19 ), .B1(n2168), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n20 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N112 ) );
AOI222XL U2243 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n6 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n21 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n8 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n22 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n10 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n23 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n20 ) );
OAI221XL U2244 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n18 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n38 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n39 ), .B1(n2168), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n40 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N108 ) );
AOI222XL U2245 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n10 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n22 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n41 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n42 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n8 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n21 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n40 ) );
OAI221XL U2246 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n45 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n46 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n47 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n48 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n42 ) );
AOI22XL U2247 ( .A0(n2186), .A1(n2122), .B0(N4721), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n48 ) );
INVXL U2248 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n169 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n53 ) );
OAI211XL U2249 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n118 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n70 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n71 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n170 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n169 ) );
AOI22XL U2250 ( .A0(n1592), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n92 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n75 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n90 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n170 ) );
INVXL U2251 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n88 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n35 ) );
OAI211XL U2252 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n89 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n80 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n81 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n90 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n88 ) );
AOI22XL U2253 ( .A0(n1595), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n75 ),
.B0(n1594), .B1(\ALU_instance/SHIFTER_GENERIC_I/C48/n17 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n90 ) );
INVXL U2254 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n68 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n2 ) );
OAI211XL U2255 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n69 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n70 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n71 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n72 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n68 ) );
AOI22XL U2256 ( .A0(n1592), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n74 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n75 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n76 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n72 ) );
AOI22XL U2257 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n68 ), .A1(n1594),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C50/n70 ), .B1(n1592), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n4 ) );
NOR4XL U2258 ( .A(\ALU_instance/ADDER_OUT[23] ), .B(
\ALU_instance/ADDER_OUT[22] ), .C(\ALU_instance/ADDER_OUT[21] ), .D(
\ALU_instance/ADDER_OUT[20] ), .Y(
\ALU_instance/COMPARATOR_GENERIC_I/n15 ) );
NOR4XL U2259 ( .A(\ALU_instance/ADDER_OUT[16] ), .B(
\ALU_instance/ADDER_OUT[15] ), .C(\ALU_instance/ADDER_OUT[14] ), .D(
\ALU_instance/ADDER_OUT[13] ), .Y(
\ALU_instance/COMPARATOR_GENERIC_I/n13 ) );
OAI221XL U2260 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n88 ), .A1(n1691),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n5 ), .B1(n2168), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n89 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N225 ) );
INVXL U2261 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n19 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n88 ) );
AOI222XL U2262 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n55 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n15 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n18 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n56 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n14 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n90 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n89 ) );
OAI221XL U2263 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n95 ), .A1(n1691),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n6 ), .B1(n2168), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n96 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N224 ) );
INVXL U2264 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n32 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n95 ) );
AOI222XL U2265 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n55 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n30 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n18 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n62 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n14 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n97 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n96 ) );
OAI221XL U2266 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n103 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n3 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n7 ), .B1(n2168), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n104 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N223 ) );
INVXL U2267 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n41 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n103 ) );
AOI222XL U2268 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n55 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n39 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n18 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n67 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n14 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n76 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n104 ) );
OAI221XL U2269 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n26 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n3 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n27 ), .B1(n2168), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n28 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N143 ) );
AOI222XL U2270 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n6 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n29 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n8 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n30 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n10 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n31 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n28 ) );
OAI221XL U2271 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n32 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n3 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n33 ), .B1(n2168), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n34 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N142 ) );
AOI222XL U2272 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n6 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n12 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n8 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n7 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n10 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n9 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n34 ) );
OAI221XL U2273 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n10 ), .A1(n1691),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n53 ), .B1(n2168), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n54 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N229 ) );
AOI222XL U2274 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n55 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n19 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n18 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n15 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n14 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n56 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n54 ) );
OAI221XL U2275 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n27 ), .A1(n1691),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n60 ), .B1(n2168), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n61 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N228 ) );
AOI222XL U2276 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n55 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n32 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n18 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n30 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n14 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n62 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n61 ) );
OAI221XL U2277 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n36 ), .A1(n1691),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n2 ), .B1(n2168), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n66 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N227 ) );
AOI222XL U2278 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n55 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n41 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n18 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n39 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n14 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n67 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n66 ) );
OAI221XL U2279 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n44 ), .A1(n1691),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n4 ), .B1(n2168), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n80 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N226 ) );
AOI222XL U2280 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n55 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n49 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n18 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n47 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n14 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n81 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n80 ) );
OAI221XL U2281 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n121 ), .A1(n1691),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n35 ), .B1(n2168), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n122 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N220 ) );
INVXL U2282 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n30 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n121 ) );
AOI222XL U2283 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n55 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n62 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n18 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n97 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n14 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n99 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n122 ) );
OAI221XL U2284 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n129 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n3 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n66 ), .B1(n2168), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n130 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N117 ) );
AOI222XL U2285 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n6 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n16 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n8 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n17 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n10 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n75 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n130 ) );
OAI221XL U2286 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n43 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n3 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n67 ), .B1(n2168), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n131 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N116 ) );
AOI222XL U2287 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n6 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n22 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n8 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n23 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n10 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n77 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n131 ) );
OAI221XL U2288 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n59 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n3 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n68 ), .B1(n2168), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n143 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N115 ) );
AOI222XL U2289 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n6 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n28 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n8 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n29 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n10 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n84 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n143 ) );
OAI221XL U2290 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n2 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n3 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n4 ), .B1(n2169), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n5 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N114 ) );
AOI222XL U2291 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n6 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n7 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n8 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n9 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n10 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n11 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n5 ) );
OAI221XL U2292 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n12 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n3 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n13 ), .B1(n2168), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n14 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N113 ) );
AOI222XL U2293 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n6 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n15 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n8 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n16 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n10 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n17 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n14 ) );
OAI221XL U2294 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n24 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n3 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n25 ), .B1(n2168), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n26 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N111 ) );
AOI222XL U2295 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n6 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n27 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n8 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n28 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n10 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n29 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n26 ) );
OAI221XL U2296 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n30 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n3 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n31 ), .B1(n2168), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n32 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N110 ) );
AOI222XL U2297 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n6 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n33 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n8 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n7 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n10 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n9 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n32 ) );
OAI221XL U2298 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n34 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n3 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n35 ), .B1(n2168), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n36 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N109 ) );
AOI222XL U2299 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n6 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n37 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n8 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n15 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n10 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n16 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n36 ) );
OAI221XL U2300 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n24 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n38 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n56 ), .B1(n2168), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n57 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N107 ) );
AOI222XL U2301 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n10 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n28 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n41 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n58 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n8 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n27 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n57 ) );
OAI221XL U2302 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ), .A1(n2187),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n46 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n45 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n61 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n58 ) );
AOI22XL U2303 ( .A0(N4721), .A1(n2122), .B0(n2189), .B1(n2123), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n61 ) );
OAI221XL U2304 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n2 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n3 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n4 ), .B1(n2168), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n5 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N146 ) );
INVXL U2305 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n12 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n2 ) );
AOI222XL U2306 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n6 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n7 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n8 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n9 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n10 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n11 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n5 ) );
OAI221XL U2307 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n20 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n38 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n39 ), .B1(n2168), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n40 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N140 ) );
AOI222XL U2308 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n10 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n24 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n16 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n42 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n8 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n23 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n40 ) );
OAI221XL U2309 ( .A0(n2119), .A1(\BOOTH_instance/n260 ), .B0(n2120), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n46 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n47 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n42 ) );
AOI22XL U2310 ( .A0(n2186), .A1(n2122), .B0(N4721), .B1(n2123), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n47 ) );
OAI221XL U2311 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n26 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n38 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n56 ), .B1(n2168), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n57 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N139 ) );
AOI222XL U2312 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n10 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n30 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n16 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n58 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n8 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n29 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n57 ) );
OAI221XL U2313 ( .A0(n2119), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n46 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ), .B1(n2187), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n60 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n58 ) );
AOI22XL U2314 ( .A0(N4721), .A1(n2122), .B0(n2189), .B1(n2123), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n60 ) );
MXI2XL U2315 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n54 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C50/n73 ), .S0(n2158), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n66 ) );
AOI21XL U2316 ( .A0(n1701), .A1(n1603), .B0(\BOOTH_instance/n157 ), .Y(
\BOOTH_instance/n160 ) );
AO22XL U2317 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S1[0] ), .A1(
n2134), .B0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S0[0] ), .B1(
EX_ADD_SUB), .Y(\ALU_instance/ADDER_OUT[0] ) );
XNOR2XL U2318 ( .A(n2108), .B(\ALU_instance/INTERNAL_B[0] ), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S1[0] ) );
XOR2XL U2319 ( .A(\ALU_instance/INTERNAL_B[0] ), .B(n2108), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S0[0] ) );
INVXL U2320 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n138 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n12 ) );
OAI221XL U2321 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n118 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n139 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n140 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n70 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n141 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n138 ) );
INVXL U2322 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n92 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n140 ) );
AOI22XL U2323 ( .A0(n1592), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n90 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n75 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n56 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n141 ) );
INVXL U2324 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n149 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n37 ) );
OAI221XL U2325 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n69 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n139 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n150 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n70 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n151 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n149 ) );
INVXL U2326 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n74 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n150 ) );
AOI22XL U2327 ( .A0(n1592), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n76 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n75 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n67 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n151 ) );
AOI22XL U2328 ( .A0(\BOOTH_instance/n352 ), .A1(n2185), .B0(
\BOOTH_instance/n353 ), .B1(\BOOTH_instance/n242 ), .Y(
\BOOTH_instance/n363 ) );
AOI22XL U2329 ( .A0(\BOOTH_instance/n352 ), .A1(n2183), .B0(
\BOOTH_instance/n353 ), .B1(\BOOTH_instance/n232 ), .Y(
\BOOTH_instance/n362 ) );
AOI22XL U2330 ( .A0(\BOOTH_instance/n352 ), .A1(n2181), .B0(
\BOOTH_instance/n353 ), .B1(\BOOTH_instance/n222 ), .Y(
\BOOTH_instance/n361 ) );
AOI22XL U2331 ( .A0(\BOOTH_instance/n352 ), .A1(n2179), .B0(
\BOOTH_instance/n353 ), .B1(\BOOTH_instance/n212 ), .Y(
\BOOTH_instance/n360 ) );
AOI22XL U2332 ( .A0(\BOOTH_instance/n352 ), .A1(n2177), .B0(
\BOOTH_instance/n353 ), .B1(\BOOTH_instance/n202 ), .Y(
\BOOTH_instance/n359 ) );
AOI22XL U2333 ( .A0(\BOOTH_instance/n352 ), .A1(n2175), .B0(
\BOOTH_instance/n353 ), .B1(\BOOTH_instance/n192 ), .Y(
\BOOTH_instance/n358 ) );
AOI22XL U2334 ( .A0(\BOOTH_instance/n352 ), .A1(n2174), .B0(
\BOOTH_instance/n353 ), .B1(\BOOTH_instance/n180 ), .Y(
\BOOTH_instance/n357 ) );
OAI221XL U2335 ( .A0(\BOOTH_instance/n158 ), .A1(\BOOTH_instance/n229 ),
.B0(\BOOTH_instance/n166 ), .B1(n2182), .C0(\BOOTH_instance/n231 ),
.Y(\BOOTH_instance/n223 ) );
AOI22XL U2336 ( .A0(n2183), .A1(\BOOTH_instance/n168 ), .B0(
\BOOTH_instance/n232 ), .B1(\BOOTH_instance/n150 ), .Y(
\BOOTH_instance/n231 ) );
AOI22XL U2337 ( .A0(\BOOTH_instance/n352 ), .A1(n2173), .B0(
\BOOTH_instance/n353 ), .B1(\BOOTH_instance/n169 ), .Y(
\BOOTH_instance/n356 ) );
OAI221XL U2338 ( .A0(\BOOTH_instance/n158 ), .A1(\BOOTH_instance/n199 ),
.B0(\BOOTH_instance/n166 ), .B1(n2176), .C0(\BOOTH_instance/n201 ),
.Y(\BOOTH_instance/n193 ) );
AOI22XL U2339 ( .A0(n2177), .A1(\BOOTH_instance/n168 ), .B0(
\BOOTH_instance/n202 ), .B1(\BOOTH_instance/n150 ), .Y(
\BOOTH_instance/n201 ) );
OAI221XL U2340 ( .A0(\BOOTH_instance/n158 ), .A1(\BOOTH_instance/n189 ),
.B0(\BOOTH_instance/n166 ), .B1(n1605), .C0(\BOOTH_instance/n191 ),
.Y(\BOOTH_instance/n181 ) );
AOI22XL U2341 ( .A0(n2175), .A1(\BOOTH_instance/n168 ), .B0(
\BOOTH_instance/n192 ), .B1(\BOOTH_instance/n150 ), .Y(
\BOOTH_instance/n191 ) );
OAI221XL U2342 ( .A0(n1606), .A1(\BOOTH_instance/n158 ), .B0(
\BOOTH_instance/n156 ), .B1(\BOOTH_instance/n166 ), .C0(
\BOOTH_instance/n167 ), .Y(\BOOTH_instance/n162 ) );
AOI22XL U2343 ( .A0(n2173), .A1(\BOOTH_instance/n168 ), .B0(
\BOOTH_instance/n169 ), .B1(\BOOTH_instance/n150 ), .Y(
\BOOTH_instance/n167 ) );
AOI21XL U2344 ( .A0(n1603), .A1(\BOOTH_instance/n186 ), .B0(
\BOOTH_instance/n316 ), .Y(\BOOTH_instance/partial_products[5][12] )
);
INVXL U2345 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n64 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n70 ) );
NOR2XL U2346 ( .A(\BOOTH_instance/n315 ), .B(\BOOTH_instance/n316 ), .Y(
\BOOTH_instance/decoded[8][16] ) );
OA21XL U2347 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n100 ), .A1(n1694),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n112 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n35 ) );
INVXL U2348 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n86 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n69 ) );
INVXL U2349 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n114 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n28 ) );
INVXL U2350 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n97 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n7 ) );
INVXL U2351 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n129 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n15 ) );
AO21XL U2352 ( .A0(\BOOTH_instance/n374 ), .A1(n1704), .B0(
\BOOTH_instance/n157 ), .Y(n1697) );
INVXL U2353 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n55 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n77 ) );
AND2XL U2354 ( .A(\ALU_instance/INTERNAL_B[12] ), .B(n2175), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA0/add_1_root_add_20_2/carry[1] ) );
AO22XL U2355 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S1[1] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[5] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S0[1] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/n2 ), .Y(
\ALU_instance/ADDER_OUT[21] ) );
AO22XL U2356 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S1[2] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[4] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S0[2] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/n2 ), .Y(
\ALU_instance/ADDER_OUT[18] ) );
AO22XL U2357 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S1[3] ), .A1(
n2134), .B0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S0[3] ), .B1(
EX_ADD_SUB), .Y(\ALU_instance/ADDER_OUT[3] ) );
INVXL U2358 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n74 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n89 ) );
AO22XL U2359 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S1[0] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[2] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S0[0] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/n2 ), .Y(
\ALU_instance/ADDER_OUT[8] ) );
XNOR2XL U2360 ( .A(n2183), .B(\ALU_instance/INTERNAL_B[8] ), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S1[0] ) );
XOR2XL U2361 ( .A(\ALU_instance/INTERNAL_B[8] ), .B(n2183), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/S0[0] ) );
AO22XL U2362 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S1[2] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[5] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S0[2] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/n2 ), .Y(
\ALU_instance/ADDER_OUT[22] ) );
AO22XL U2363 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S1[3] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[4] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S0[3] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/n2 ), .Y(
\ALU_instance/ADDER_OUT[19] ) );
AO22XL U2364 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S1[3] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[3] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S0[3] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/n2 ), .Y(
\ALU_instance/ADDER_OUT[15] ) );
AO22XL U2365 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S1[2] ), .A1(
n2134), .B0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S0[2] ), .B1(
EX_ADD_SUB), .Y(\ALU_instance/ADDER_OUT[2] ) );
AO22XL U2366 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S1[0] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[3] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S0[0] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/n2 ), .Y(
\ALU_instance/ADDER_OUT[12] ) );
XNOR2XL U2367 ( .A(n2175), .B(\ALU_instance/INTERNAL_B[12] ), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S1[0] ) );
XOR2XL U2368 ( .A(\ALU_instance/INTERNAL_B[12] ), .B(n2175), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/S0[0] ) );
AO22XL U2369 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S1[1] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[1] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S0[1] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/n2 ), .Y(
\ALU_instance/ADDER_OUT[5] ) );
AO22XL U2370 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S1[3] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[5] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S0[3] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/n2 ), .Y(
\ALU_instance/ADDER_OUT[23] ) );
AO22XL U2371 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S1[1] ), .A1(
n2134), .B0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/S0[1] ), .B1(
EX_ADD_SUB), .Y(\ALU_instance/ADDER_OUT[1] ) );
AO22XL U2372 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S1[2] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[1] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/S0[2] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/n2 ), .Y(
\ALU_instance/ADDER_OUT[6] ) );
AO22XL U2373 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S1[1] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[4] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S0[1] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/n2 ), .Y(
\ALU_instance/ADDER_OUT[17] ) );
INVXL U2374 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n144 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n28 ) );
OAI221XL U2375 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n100 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n139 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n145 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n70 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n146 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n144 ) );
INVXL U2376 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n99 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n145 ) );
AOI22XL U2377 ( .A0(n1592), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n97 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n75 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n62 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n146 ) );
INVXL U2378 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n102 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N150 ) );
AOI221XL U2379 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n9 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n6 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n7 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n16 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n103 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n102 ) );
INVXL U2380 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n104 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n103 ) );
AOI222XL U2381 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n10 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n68 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n98 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n70 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n8 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n11 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n104 ) );
INVXL U2382 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n129 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N218 ) );
AOI221XL U2383 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n81 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n55 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n47 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n16 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n130 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n129 ) );
INVXL U2384 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n131 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n130 ) );
AOI221XL U2385 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n14 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n82 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n18 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n83 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n132 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n131 ) );
INVXL U2386 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n110 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N120 ) );
AOI221XL U2387 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n23 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n6 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n22 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n41 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n111 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n110 ) );
INVXL U2388 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n112 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n111 ) );
AOI221XL U2389 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n10 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n76 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n8 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n77 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n109 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n112 ) );
INVXL U2390 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n95 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N152 ) );
AOI221XL U2391 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n25 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n6 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n24 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n16 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n96 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n95 ) );
INVXL U2392 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n97 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n96 ) );
AOI222XL U2393 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n10 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n73 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n98 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n54 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n8 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n75 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n97 ) );
INVXL U2394 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n99 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N151 ) );
AOI221XL U2395 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n31 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n6 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n30 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n16 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n100 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n99 ) );
INVXL U2396 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n101 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n100 ) );
AOI222XL U2397 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n10 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n76 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n98 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n77 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n8 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n78 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n101 ) );
INVXL U2398 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n118 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N149 ) );
AOI221XL U2399 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n17 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n6 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n16 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n16 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n119 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n118 ) );
INVXL U2400 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n120 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n119 ) );
AOI222XL U2401 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n10 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n72 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n98 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n65 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n8 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n18 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n120 ) );
INVXL U2402 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n176 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n60 ) );
OAI211XL U2403 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n100 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n70 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n71 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n177 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n176 ) );
AOI22XL U2404 ( .A0(n1592), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n99 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n75 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n97 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n177 ) );
INVXL U2405 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n162 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n45 ) );
OAI211XL U2406 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n110 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n70 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n71 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n163 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n162 ) );
AOI22XL U2407 ( .A0(n1592), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n83 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n75 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n81 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n163 ) );
INVXL U2408 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n99 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n39 ) );
OAI211XL U2409 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n100 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n80 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n81 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n101 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n99 ) );
AOI22XL U2410 ( .A0(n1595), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n77 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n75 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n23 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n101 ) );
AO21XL U2411 ( .A0(\BOOTH_instance/n398 ), .A1(n1695), .B0(
\BOOTH_instance/n157 ), .Y(n1698) );
OR2XL U2412 ( .A(\ALU_instance/INTERNAL_B[12] ), .B(n2175), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_3/RCA1/add_1_root_add_20_2/carry[1] ) );
OR2XL U2413 ( .A(\ALU_instance/INTERNAL_B[8] ), .B(n2183), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA1/add_1_root_add_20_2/carry[1] ) );
AND2XL U2414 ( .A(\ALU_instance/INTERNAL_B[8] ), .B(n2183), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_2/RCA0/add_1_root_add_20_2/carry[1] ) );
AO22XL U2415 ( .A0(EX_MULT_OUT[1]), .A1(n2142), .B0(EX_ALU_OUT[1]), .B1(
n2141), .Y(N4861) );
OAI222XL U2416 ( .A0(\BOOTH_instance/n316 ), .A1(n2124), .B0(
\BOOTH_instance/n308 ), .B1(\BOOTH_instance/n445 ), .C0(
\BOOTH_instance/n307 ), .C1(\BOOTH_instance/n447 ), .Y(EX_MULT_OUT[1])
);
OAI2BB1XL U2417 ( .A0N(\ALU_instance/ADDER_OUT[1] ), .A1N(n1596), .B0(
\ALU_instance/n20 ), .Y(EX_ALU_OUT[1]) );
AOI22XL U2418 ( .A0(\ALU_instance/SHIFTER_OUT[1] ), .A1(\ALU_instance/n5 ),
.B0(\ALU_instance/LOGIC_OUT[1] ), .B1(\ALU_instance/n6 ), .Y(
\ALU_instance/n20 ) );
AO22XL U2419 ( .A0(EX_MULT_OUT[3]), .A1(n2142), .B0(EX_ALU_OUT[3]), .B1(
n2141), .Y(N4863) );
OAI2BB1XL U2420 ( .A0N(\ALU_instance/ADDER_OUT[3] ), .A1N(n1596), .B0(
\ALU_instance/n18 ), .Y(EX_ALU_OUT[3]) );
AOI22XL U2421 ( .A0(\ALU_instance/SHIFTER_OUT[3] ), .A1(\ALU_instance/n5 ),
.B0(\ALU_instance/LOGIC_OUT[3] ), .B1(\ALU_instance/n6 ), .Y(
\ALU_instance/n18 ) );
OAI2B2XL U2422 ( .A1N(n2171), .A0(\ALU_instance/LOGIC_GENERIC_I/n51 ), .B0(
n2171), .B1(\ALU_instance/LOGIC_GENERIC_I/n52 ), .Y(
\ALU_instance/LOGIC_OUT[3] ) );
OAI2BB1XL U2423 ( .A0N(\ALU_instance/ADDER_OUT[2] ), .A1N(n1596), .B0(
\ALU_instance/n19 ), .Y(EX_ALU_OUT[2]) );
AOI22XL U2424 ( .A0(\ALU_instance/SHIFTER_OUT[2] ), .A1(n2135), .B0(
\ALU_instance/LOGIC_OUT[2] ), .B1(\ALU_instance/n6 ), .Y(
\ALU_instance/n19 ) );
AO22XL U2425 ( .A0(EX_MULT_OUT[4]), .A1(n2142), .B0(EX_ALU_OUT[4]), .B1(
n2141), .Y(N4864) );
XOR2XL U2426 ( .A(\BOOTH_instance/partial_products[8][4] ), .B(
\BOOTH_instance/partial_products[7][4] ), .Y(EX_MULT_OUT[4]) );
OAI2BB1XL U2427 ( .A0N(\ALU_instance/ADDER_OUT[4] ), .A1N(n1596), .B0(
\ALU_instance/n17 ), .Y(EX_ALU_OUT[4]) );
AOI22XL U2428 ( .A0(\ALU_instance/SHIFTER_OUT[4] ), .A1(\ALU_instance/n5 ),
.B0(\ALU_instance/LOGIC_OUT[4] ), .B1(\ALU_instance/n6 ), .Y(
\ALU_instance/n17 ) );
INVXL U2429 ( .A(n2138), .Y(n2140) );
AOI221XL U2430 ( .A0(n1705), .A1(n1530), .B0(n1523), .B1(n1548), .C0(n1558),
.Y(n1546) );
AOI222XL U2431 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n73 ), .A1(n1592),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C50/n54 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n74 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n75 ), .C1(n1594), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n21 ) );
AOI222XL U2432 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n72 ), .A1(n1592),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C50/n65 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n74 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n18 ), .C1(n1594), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n36 ) );
AOI221XL U2433 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n102 ), .A1(n1595),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n83 ), .B1(n1594), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n73 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n68 ) );
AOI221XL U2434 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n74 ), .A1(n1595),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n75 ), .B1(n1594), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n73 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n13 ) );
AOI221XL U2435 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n76 ), .A1(n1595),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n77 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n75 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n73 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n19 ) );
OR2XL U2436 ( .A(EX_SHIFTER_CW[0]), .B(\ALU_instance/SHIFTER_GENERIC_I/n89 ),
.Y(n1699) );
OAI221XL U2437 ( .A0(n2119), .A1(n1667), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n45 ), .B1(n1605), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n127 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n23 ) );
AOI22XL U2438 ( .A0(n2175), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ),
.B0(n2177), .B1(\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n127 ) );
AOI221XL U2439 ( .A0(n2121), .A1(n2183), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n52 ), .B1(n2181), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n62 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n24 ) );
OAI2B2XL U2440 ( .A1N(n2185), .A0(n1641), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n47 ), .B1(n1640), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n62 ) );
AOI221XL U2441 ( .A0(n2121), .A1(n2185), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n52 ), .B1(n2183), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n98 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n30 ) );
OAI22XL U2442 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n47 ), .A1(n1641),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n45 ), .B1(n1640), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n98 ) );
AOI221XL U2443 ( .A0(n2121), .A1(n2181), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n52 ), .B1(n2179), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n53 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n18 ) );
AO22XL U2444 ( .A0(n2183), .A1(n2122), .B0(n2185), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n53 ) );
OAI221XL U2445 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n143 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n3 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n67 ), .B1(n2168), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n144 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N147 ) );
INVXL U2446 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n29 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n143 ) );
AOI222XL U2447 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n6 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n30 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n8 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n31 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n10 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n78 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n144 ) );
OAI221XL U2448 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n114 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n3 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n54 ), .B1(n2168), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n115 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N119 ) );
AOI222XL U2449 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n6 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n29 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n8 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n84 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n10 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n83 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n115 ) );
OAI221XL U2450 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n97 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n3 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n65 ), .B1(n2168), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n118 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N118 ) );
AOI222XL U2451 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n6 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n9 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n8 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n11 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n10 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n71 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n118 ) );
AOI22XL U2452 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n76 ), .A1(n1594),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C50/n77 ), .B1(n1595), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n67 ) );
AOI22XL U2453 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n72 ), .A1(n1594),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C50/n65 ), .B1(n1595), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n14 ) );
OAI221XL U2454 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n35 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n3 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n36 ), .B1(n2168), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n37 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N141 ) );
AOI222XL U2455 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n6 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n19 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n8 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n16 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n10 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n17 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n37 ) );
OAI221XL U2456 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n20 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n3 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n21 ), .B1(n2168), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n22 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N144 ) );
AOI222XL U2457 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n6 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n23 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n8 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n24 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n10 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n25 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n22 ) );
OAI221XL U2458 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n108 ), .A1(n1691),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n8 ), .B1(n2168), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n109 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N222 ) );
INVXL U2459 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n49 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n108 ) );
AOI222XL U2460 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n55 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n47 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n18 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n81 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n14 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n83 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n109 ) );
OAI221XL U2461 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n13 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n3 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n14 ), .B1(n2168), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n15 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N145 ) );
INVXL U2462 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n19 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n13 ) );
AOI222XL U2463 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n6 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n16 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n8 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n17 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n10 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n18 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n15 ) );
OAI2B2XL U2464 ( .A1N(n2160), .A0(\ALU_instance/LOGIC_GENERIC_I/n126 ), .B0(
n2159), .B1(\ALU_instance/LOGIC_GENERIC_I/n127 ), .Y(
\ALU_instance/LOGIC_OUT[0] ) );
NAND2XL U2465 ( .A(n2191), .B(n2109), .Y(\ALU_instance/LOGIC_GENERIC_I/n127 ) );
AOI22XL U2466 ( .A0(n2190), .A1(\BOOTH_instance/n316 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/N202 ), .B1(EX_LOGIC_CW[3]), .Y(
\ALU_instance/LOGIC_GENERIC_I/n126 ) );
NAND2XL U2467 ( .A(n2191), .B(n2186), .Y(\ALU_instance/LOGIC_GENERIC_I/n49 )
);
MXI2XL U2468 ( .A(n2110), .B(\BOOTH_instance/n307 ), .S0(n2123), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n105 ) );
NOR2BXL U2469 ( .AN(\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C50/n139 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n54 ) );
NOR2XL U2470 ( .A(n2169), .B(\ALU_instance/SHIFTER_GENERIC_I/C50/n139 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n109 ) );
OAI2B11XL U2471 ( .A1N(\ALU_instance/SHIFTER_GENERIC_I/C50/n75 ), .A0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n122 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n123 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n124 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N148 ) );
AOI22XL U2472 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n6 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n24 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n16 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n23 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n124 ) );
AOI32XL U2473 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n90 ), .A1(n1597),
.A2(n2167), .B0(\ALU_instance/SHIFTER_GENERIC_I/C50/n8 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n25 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n123 ) );
AOI22XL U2474 ( .A0(n2191), .A1(n2182), .B0(EX_LOGIC_CW[3]), .B1(n2181), .Y(
\ALU_instance/LOGIC_GENERIC_I/n33 ) );
AOI22XL U2475 ( .A0(n2190), .A1(n1667), .B0(n2173), .B1(EX_LOGIC_CW[3]), .Y(
\ALU_instance/LOGIC_GENERIC_I/n111 ) );
AOI22XL U2476 ( .A0(n2190), .A1(n1605), .B0(n2174), .B1(EX_LOGIC_CW[3]), .Y(
\ALU_instance/LOGIC_GENERIC_I/n114 ) );
AOI22XL U2477 ( .A0(n2190), .A1(n2176), .B0(n2175), .B1(EX_LOGIC_CW[3]), .Y(
\ALU_instance/LOGIC_GENERIC_I/n117 ) );
AOI22XL U2478 ( .A0(n2190), .A1(n2178), .B0(n2177), .B1(EX_LOGIC_CW[3]), .Y(
\ALU_instance/LOGIC_GENERIC_I/n120 ) );
AOI22XL U2479 ( .A0(n2191), .A1(n2184), .B0(n2183), .B1(n2193), .Y(
\ALU_instance/LOGIC_GENERIC_I/n36 ) );
AOI22XL U2480 ( .A0(n2191), .A1(n1604), .B0(n2185), .B1(EX_LOGIC_CW[3]), .Y(
\ALU_instance/LOGIC_GENERIC_I/n39 ) );
AOI22XL U2481 ( .A0(n2190), .A1(n2188), .B0(N4721), .B1(n2193), .Y(
\ALU_instance/LOGIC_GENERIC_I/n51 ) );
OAI221XL U2482 ( .A0(\BOOTH_instance/n307 ), .A1(n2125), .B0(n2110), .B1(
n2126), .C0(\ALU_instance/SHIFTER_GENERIC_I/C86/n175 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n91 ) );
AOI22XL U2483 ( .A0(n2127), .A1(n2189), .B0(N4721), .B1(n2123), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n175 ) );
OAI221XL U2484 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n43 ), .A1(n1605),
.B0(n2120), .B1(n2176), .C0(\ALU_instance/SHIFTER_GENERIC_I/C50/n149 ),
.Y(\ALU_instance/SHIFTER_GENERIC_I/C50/n29 ) );
AOI22XL U2485 ( .A0(n2177), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ),
.B0(n2179), .B1(n2123), .Y(\ALU_instance/SHIFTER_GENERIC_I/C50/n149 )
);
OAI221XL U2486 ( .A0(n2119), .A1(n2176), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ), .B1(n2178), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n84 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n12 ) );
AOI22XL U2487 ( .A0(n2179), .A1(n2122), .B0(n2181), .B1(n2123), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n84 ) );
OAI221XL U2488 ( .A0(n2119), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n119 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C50/n45 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n113 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n114 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n7 ) );
AOI22XL U2489 ( .A0(n2173), .A1(n2122), .B0(n2174), .B1(n2123), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n114 ) );
OAI221XL U2490 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n43 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n113 ), .B0(n2120), .B1(n1667),
.C0(\ALU_instance/SHIFTER_GENERIC_I/C50/n156 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n16 ) );
AOI22XL U2491 ( .A0(n2174), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ),
.B0(n2175), .B1(n2123), .Y(\ALU_instance/SHIFTER_GENERIC_I/C50/n156 )
);
NOR2XL U2492 ( .A(n2172), .B(n2167), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n153 ) );
AOI2B1XL U2493 ( .A1N(n2111), .A0(n2157), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n84 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n112 ) );
NOR2XL U2494 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n64 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C48/n3 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N166 ) );
OA21XL U2495 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n86 ), .A1(n1694),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n117 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n65 ) );
OA21XL U2496 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n79 ), .A1(n1694),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n117 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n54 ) );
OA21XL U2497 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n89 ), .A1(n1694),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n117 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n66 ) );
OA21XL U2498 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n100 ), .A1(n1694),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n117 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n67 ) );
NOR2XL U2499 ( .A(n2158), .B(n2172), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n92 ) );
NAND2XL U2500 ( .A(n2170), .B(n2158), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n80 ) );
NOR2XL U2501 ( .A(n1597), .B(n2167), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n133 ) );
INVXL U2502 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n76 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n100 ) );
INVXL U2503 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n82 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n110 ) );
NOR2XL U2504 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n55 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C48/n3 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N167 ) );
NAND2XL U2505 ( .A(n2191), .B(n2179), .Y(\ALU_instance/LOGIC_GENERIC_I/n124 ) );
NAND2XL U2506 ( .A(n2191), .B(n2181), .Y(\ALU_instance/LOGIC_GENERIC_I/n34 )
);
NAND2XL U2507 ( .A(n2191), .B(n2177), .Y(\ALU_instance/LOGIC_GENERIC_I/n121 ) );
NAND2XL U2508 ( .A(n2191), .B(n2185), .Y(\ALU_instance/LOGIC_GENERIC_I/n40 )
);
NAND2XL U2509 ( .A(n2192), .B(n2174), .Y(\ALU_instance/LOGIC_GENERIC_I/n115 ) );
NAND2XL U2510 ( .A(n2191), .B(N4721), .Y(\ALU_instance/LOGIC_GENERIC_I/n52 )
);
NAND2XL U2511 ( .A(n2192), .B(n2173), .Y(\ALU_instance/LOGIC_GENERIC_I/n112 ) );
NAND2XL U2512 ( .A(n2191), .B(n2175), .Y(\ALU_instance/LOGIC_GENERIC_I/n118 ) );
NAND2XL U2513 ( .A(n2191), .B(n2183), .Y(\ALU_instance/LOGIC_GENERIC_I/n37 )
);
NAND2XL U2514 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][7] ), .B(
n1597), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/n1 ) );
NAND2XL U2515 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][6] ), .B(
n1597), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/n2 ) );
NAND2XL U2516 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][5] ), .B(
n1597), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/n3 ) );
NAND2XL U2517 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][4] ), .B(
n1597), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/n4 ) );
NOR2XL U2518 ( .A(\BOOTH_instance/n315 ), .B(\BOOTH_instance/n156 ), .Y(
\BOOTH_instance/decoded[8][31] ) );
NAND2XL U2519 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][0] ), .B(
n1597), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/n8 ) );
NAND2XL U2520 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][3] ), .B(
n1597), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/n5 ) );
NAND2XL U2521 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][2] ), .B(
n1597), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/n6 ) );
NAND2XL U2522 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][1] ), .B(
n1597), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/n7 ) );
INVXL U2523 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n78 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n25 ) );
OAI211XL U2524 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n79 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n80 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n81 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n82 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n78 ) );
AOI22XL U2525 ( .A0(n1595), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n83 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n75 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n84 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n82 ) );
INVXL U2526 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n85 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n31 ) );
OAI211XL U2527 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n86 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n80 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n81 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n87 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n85 ) );
AOI22XL U2528 ( .A0(n1595), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n71 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n75 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n11 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n87 ) );
CLKINVX2 U2529 ( .A(n1597), .Y(n2171) );
INVXL U2530 ( .A(EX_SHIFTER_CW[0]), .Y(\ALU_instance/SHIFTER_GENERIC_I/n88 )
);
INVXL U2531 ( .A(EX_ALU_SEL[1]), .Y(\ALU_instance/n23 ) );
CLKINVX2 U2532 ( .A(n2161), .Y(n2160) );
AND2XL U2533 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][3] ), .B(
n2158), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][3] ) );
AND2XL U2534 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][2] ), .B(
n2158), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][2] ) );
AND2XL U2535 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][0] ), .B(
n2158), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][0] ) );
AND2XL U2536 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][1] ), .B(
n2158), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[3][1] ) );
CLKBUFX1 U2537 ( .A(n2169), .Y(n2168) );
AND2XL U2538 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n65 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/C86/n16 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N165 ) );
INVXL U2539 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n79 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n102 ) );
AND2XL U2540 ( .A(n2109), .B(n2162), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][0] ) );
CLKBUFX1 U2541 ( .A(n1613), .Y(n2129) );
INVXL U2542 ( .A(n1536), .Y(n1548) );
NOR2XL U2543 ( .A(n1197), .B(n1478), .Y(n1190) );
CLKINVX1 U2544 ( .A(n1292), .Y(n1227) );
CLKBUFX1 U2545 ( .A(n1225), .Y(n2144) );
INVXL U2546 ( .A(n1485), .Y(n1479) );
NAND2XL U2547 ( .A(n1616), .B(n1310), .Y(n1207) );
NOR2XL U2548 ( .A(n1440), .B(n1190), .Y(n1199) );
INVXL U2549 ( .A(n1368), .Y(n1367) );
INVXL U2550 ( .A(n1338), .Y(n1495) );
NAND2XL U2551 ( .A(WB_DATA_EXT_8[9]), .B(n1330), .Y(n1208) );
CLKBUFX1 U2552 ( .A(\WB_SIGN_EXT_16_instance/n27 ), .Y(n2107) );
INVXL U2553 ( .A(n1493), .Y(n1507) );
AOI22XL U2554 ( .A0(\BOOTH_instance/n188 ), .A1(n2113), .B0(
\BOOTH_instance/n176 ), .B1(\BOOTH_instance/n320 ), .Y(
\BOOTH_instance/n319 ) );
AOI222XL U2555 ( .A0(EX_COMPARATOR_CW[1]), .A1(
\ALU_instance/COMPARATOR_GENERIC_I/n6 ), .B0(EX_COMPARATOR_CW[2]),
.B1(\ALU_instance/COMPARATOR_GENERIC_I/n7 ), .C0(EX_COMPARATOR_CW[5]),
.C1(\ALU_instance/COMPARATOR_GENERIC_I/n8 ), .Y(
\ALU_instance/COMPARATOR_GENERIC_I/n5 ) );
OAI31XL U2556 ( .A0(n1537), .A1(n1374), .A2(n1542), .B0(n1543), .Y(
EX_COMPARATOR_CW[2]) );
INVXL U2557 ( .A(\ALU_instance/COMPARATOR_GENERIC_I/n7 ), .Y(
\ALU_instance/COMPARATOR_GENERIC_I/n8 ) );
INVXL U2558 ( .A(\ALU_instance/ZERO ), .Y(
\ALU_instance/COMPARATOR_GENERIC_I/n6 ) );
AOI221XL U2559 ( .A0(N4719), .A1(\BOOTH_instance/n326 ), .B0(
\BOOTH_instance/n320 ), .B1(\BOOTH_instance/n327 ), .C0(
\BOOTH_instance/n343 ), .Y(\BOOTH_instance/n342 ) );
OAI22XL U2560 ( .A0(\BOOTH_instance/n328 ), .A1(n1644), .B0(
\BOOTH_instance/n323 ), .B1(\BOOTH_instance/n290 ), .Y(
\BOOTH_instance/n343 ) );
INVXL U2561 ( .A(\BOOTH_instance/n404 ), .Y(\BOOTH_instance/decoded[2][6] )
);
XNOR2XL U2562 ( .A(\BOOTH_instance/n347 ), .B(N4836), .Y(
\BOOTH_instance/n348 ) );
XNOR2XL U2563 ( .A(N4841), .B(\BOOTH_instance/n318 ), .Y(
\BOOTH_instance/n317 ) );
XNOR2XL U2564 ( .A(N4833), .B(\BOOTH_instance/n396 ), .Y(
\BOOTH_instance/n395 ) );
XNOR2XL U2565 ( .A(N4835), .B(\BOOTH_instance/n372 ), .Y(
\BOOTH_instance/n371 ) );
XNOR2XL U2566 ( .A(n690), .B(n1607), .Y(\BOOTH_instance/n443 ) );
OAI22XL U2567 ( .A0(\BOOTH_instance/n373 ), .A1(n1644), .B0(
\BOOTH_instance/n374 ), .B1(\BOOTH_instance/n290 ), .Y(
\BOOTH_instance/n379 ) );
OAI22XL U2568 ( .A0(\BOOTH_instance/n421 ), .A1(n1644), .B0(
\BOOTH_instance/n422 ), .B1(\BOOTH_instance/n290 ), .Y(
\BOOTH_instance/n431 ) );
OR3XL U2569 ( .A(N4837), .B(N4836), .C(\BOOTH_instance/n345 ), .Y(n1700) );
OR3XL U2570 ( .A(n1645), .B(N4839), .C(\BOOTH_instance/n318 ), .Y(n1701) );
OR3XL U2571 ( .A(\BOOTH_instance/n346 ), .B(n1645), .C(\BOOTH_instance/n347 ), .Y(n1702) );
AOI22XL U2572 ( .A0(\BOOTH_instance/n352 ), .A1(n2115), .B0(
\BOOTH_instance/n353 ), .B1(n1593), .Y(\BOOTH_instance/n365 ) );
AOI22XL U2573 ( .A0(\BOOTH_instance/n352 ), .A1(n2117), .B0(
\BOOTH_instance/n353 ), .B1(\BOOTH_instance/n252 ), .Y(
\BOOTH_instance/n364 ) );
NAND3XL U2574 ( .A(N4834), .B(\BOOTH_instance/n346 ), .C(N4835), .Y(
\BOOTH_instance/n355 ) );
NAND3XL U2575 ( .A(N4832), .B(\BOOTH_instance/n372 ), .C(N4833), .Y(
\BOOTH_instance/n382 ) );
AOI22XL U2576 ( .A0(\BOOTH_instance/n400 ), .A1(n2114), .B0(
\BOOTH_instance/n401 ), .B1(n1593), .Y(\BOOTH_instance/n418 ) );
AOI22XL U2577 ( .A0(\BOOTH_instance/n400 ), .A1(n2116), .B0(
\BOOTH_instance/n401 ), .B1(\BOOTH_instance/n252 ), .Y(
\BOOTH_instance/n417 ) );
NAND3XL U2578 ( .A(N4839), .B(\BOOTH_instance/n318 ), .C(n1645), .Y(
\BOOTH_instance/n175 ) );
INVXL U2579 ( .A(N4834), .Y(\BOOTH_instance/n372 ) );
NAND3XL U2580 ( .A(n1580), .B(n1565), .C(n1584), .Y(n1555) );
NAND3XL U2581 ( .A(n1575), .B(n1580), .C(n1528), .Y(n1557) );
NAND3XL U2582 ( .A(n1580), .B(n1577), .C(n1575), .Y(n1545) );
NAND2XL U2583 ( .A(n1575), .B(n1576), .Y(n1568) );
AOI32XL U2584 ( .A0(EX_ALU_SEL[0]), .A1(\ALU_instance/n23 ), .A2(
\ALU_instance/COMPARATOR_OUT[0] ), .B0(\ALU_instance/SHIFTER_OUT[0] ),
.B1(n2135), .Y(\ALU_instance/n22 ) );
NAND2XL U2585 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n85 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n86 ), .Y(
\ALU_instance/SHIFTER_OUT[0] ) );
NAND2XL U2586 ( .A(\ALU_instance/COMPARATOR_GENERIC_I/n4 ), .B(
\ALU_instance/COMPARATOR_GENERIC_I/n5 ), .Y(
\ALU_instance/COMPARATOR_OUT[0] ) );
NAND2XL U2587 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N234 ), .B(n1611), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n85 ) );
OR2XL U2588 ( .A(\ALU_instance/INTERNAL_B[0] ), .B(n2108), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA1/add_1_root_add_20_2/carry[1] ) );
INVXL U2589 ( .A(\BOOTH_instance/n369 ), .Y(\BOOTH_instance/decoded[4][10] )
);
AOI221XL U2590 ( .A0(n2112), .A1(\BOOTH_instance/n352 ), .B0(
\BOOTH_instance/n320 ), .B1(\BOOTH_instance/n353 ), .C0(
\BOOTH_instance/n370 ), .Y(\BOOTH_instance/n369 ) );
OAI22XL U2591 ( .A0(\BOOTH_instance/n349 ), .A1(n1644), .B0(
\BOOTH_instance/n350 ), .B1(\BOOTH_instance/n290 ), .Y(
\BOOTH_instance/n370 ) );
AO22XL U2592 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S1[0] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[7] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S0[0] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/n2 ), .Y(
\ALU_instance/ADDER_OUT[28] ) );
XNOR2XL U2593 ( .A(n1687), .B(\ALU_instance/INTERNAL_B[28] ), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S1[0] ) );
XOR2XL U2594 ( .A(\ALU_instance/INTERNAL_B[28] ), .B(n1687), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/S0[0] ) );
AO22XL U2595 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S1[0] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[6] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S0[0] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/n2 ), .Y(
\ALU_instance/ADDER_OUT[24] ) );
XNOR2XL U2596 ( .A(n1682), .B(\ALU_instance/INTERNAL_B[24] ), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S1[0] ) );
XOR2XL U2597 ( .A(\ALU_instance/INTERNAL_B[24] ), .B(n1682), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/S0[0] ) );
OAI2BB1XL U2598 ( .A0N(n1528), .A1N(n1399), .B0(n1525), .Y(n1558) );
XOR2XL U2599 ( .A(N4839), .B(n1645), .Y(\BOOTH_instance/n322 ) );
OR3XL U2600 ( .A(N4834), .B(N4835), .C(\BOOTH_instance/n346 ), .Y(n1703) );
OR3XL U2601 ( .A(N4832), .B(N4833), .C(\BOOTH_instance/n372 ), .Y(n1704) );
AND3XL U2602 ( .A(n1577), .B(n1566), .C(n1563), .Y(n1705) );
INVXL U2603 ( .A(n1581), .Y(n1567) );
INVXL U2604 ( .A(N4837), .Y(\BOOTH_instance/n347 ) );
INVXL U2605 ( .A(n1569), .Y(n1400) );
OR2XL U2606 ( .A(n1397), .B(n1528), .Y(n1547) );
OR2XL U2607 ( .A(\ALU_instance/INTERNAL_B[4] ), .B(n2186), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA1/add_1_root_add_20_2/carry[1] ) );
AND2XL U2608 ( .A(\ALU_instance/INTERNAL_B[0] ), .B(n2108), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_0/RCA0/add_1_root_add_20_2/carry[1] ) );
AND2XL U2609 ( .A(\ALU_instance/INTERNAL_B[4] ), .B(n2186), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_1/RCA0/add_1_root_add_20_2/carry[1] ) );
INVXL U2610 ( .A(\BOOTH_instance/n430 ), .Y(\BOOTH_instance/decoded[1][4] )
);
AOI221XL U2611 ( .A0(n2112), .A1(\BOOTH_instance/n424 ), .B0(
\BOOTH_instance/n320 ), .B1(\BOOTH_instance/n425 ), .C0(
\BOOTH_instance/n431 ), .Y(\BOOTH_instance/n430 ) );
OAI221XL U2612 ( .A0(\BOOTH_instance/n260 ), .A1(\BOOTH_instance/n421 ),
.B0(\BOOTH_instance/n259 ), .B1(\BOOTH_instance/n422 ), .C0(
\BOOTH_instance/n426 ), .Y(\BOOTH_instance/decoded[1][8] ) );
OAI222XL U2613 ( .A0(\BOOTH_instance/n249 ), .A1(n2124), .B0(
\BOOTH_instance/n239 ), .B1(\BOOTH_instance/n445 ), .C0(n2184), .C1(
\BOOTH_instance/n447 ), .Y(\BOOTH_instance/N217 ) );
AOI22XL U2614 ( .A0(\BOOTH_instance/n424 ), .A1(n2115), .B0(
\BOOTH_instance/n425 ), .B1(n1593), .Y(\BOOTH_instance/n426 ) );
INVXL U2615 ( .A(\BOOTH_instance/n378 ), .Y(\BOOTH_instance/decoded[3][8] )
);
OAI221XL U2616 ( .A0(n2187), .A1(\BOOTH_instance/n397 ), .B0(
\BOOTH_instance/n299 ), .B1(\BOOTH_instance/n398 ), .C0(
\BOOTH_instance/n402 ), .Y(\BOOTH_instance/decoded[2][8] ) );
AOI221XL U2617 ( .A0(n2113), .A1(\BOOTH_instance/n376 ), .B0(
\BOOTH_instance/n320 ), .B1(\BOOTH_instance/n377 ), .C0(
\BOOTH_instance/n379 ), .Y(\BOOTH_instance/n378 ) );
OAI221XL U2618 ( .A0(n1604), .A1(\BOOTH_instance/n421 ), .B0(
\BOOTH_instance/n249 ), .B1(\BOOTH_instance/n422 ), .C0(
\BOOTH_instance/n423 ), .Y(\BOOTH_instance/decoded[1][9] ) );
OAI222XL U2619 ( .A0(\BOOTH_instance/n239 ), .A1(n2124), .B0(
\BOOTH_instance/n229 ), .B1(\BOOTH_instance/n445 ), .C0(n2182), .C1(
\BOOTH_instance/n447 ), .Y(\BOOTH_instance/N218 ) );
AOI22XL U2620 ( .A0(\BOOTH_instance/n424 ), .A1(n2117), .B0(
\BOOTH_instance/n425 ), .B1(\BOOTH_instance/n252 ), .Y(
\BOOTH_instance/n423 ) );
OAI221XL U2621 ( .A0(n2184), .A1(\BOOTH_instance/n421 ), .B0(
\BOOTH_instance/n239 ), .B1(\BOOTH_instance/n422 ), .C0(
\BOOTH_instance/n442 ), .Y(\BOOTH_instance/decoded[1][10] ) );
OAI222XL U2622 ( .A0(\BOOTH_instance/n229 ), .A1(n2124), .B0(
\BOOTH_instance/n219 ), .B1(\BOOTH_instance/n445 ), .C0(n2180), .C1(
\BOOTH_instance/n447 ), .Y(\BOOTH_instance/N219 ) );
AOI22XL U2623 ( .A0(\BOOTH_instance/n424 ), .A1(n2185), .B0(
\BOOTH_instance/n425 ), .B1(\BOOTH_instance/n242 ), .Y(
\BOOTH_instance/n442 ) );
OAI221XL U2624 ( .A0(n2180), .A1(\BOOTH_instance/n421 ), .B0(
\BOOTH_instance/n219 ), .B1(\BOOTH_instance/n422 ), .C0(
\BOOTH_instance/n440 ), .Y(\BOOTH_instance/decoded[1][12] ) );
OAI222XL U2625 ( .A0(\BOOTH_instance/n209 ), .A1(n2124), .B0(
\BOOTH_instance/n199 ), .B1(\BOOTH_instance/n445 ), .C0(n2176), .C1(
\BOOTH_instance/n447 ), .Y(\BOOTH_instance/N221 ) );
AOI22XL U2626 ( .A0(\BOOTH_instance/n424 ), .A1(n2181), .B0(
\BOOTH_instance/n425 ), .B1(\BOOTH_instance/n222 ), .Y(
\BOOTH_instance/n440 ) );
OAI221XL U2627 ( .A0(\BOOTH_instance/n260 ), .A1(\BOOTH_instance/n373 ),
.B0(\BOOTH_instance/n259 ), .B1(\BOOTH_instance/n374 ), .C0(
\BOOTH_instance/n392 ), .Y(\BOOTH_instance/decoded[3][12] ) );
OAI221XL U2628 ( .A0(n2184), .A1(\BOOTH_instance/n397 ), .B0(
\BOOTH_instance/n239 ), .B1(\BOOTH_instance/n398 ), .C0(
\BOOTH_instance/n416 ), .Y(\BOOTH_instance/decoded[2][12] ) );
AOI22XL U2629 ( .A0(\BOOTH_instance/n376 ), .A1(N4723), .B0(
\BOOTH_instance/n377 ), .B1(n1593), .Y(\BOOTH_instance/n392 ) );
OAI221XL U2630 ( .A0(n1604), .A1(\BOOTH_instance/n373 ), .B0(
\BOOTH_instance/n249 ), .B1(\BOOTH_instance/n374 ), .C0(
\BOOTH_instance/n391 ), .Y(\BOOTH_instance/decoded[3][13] ) );
OAI221XL U2631 ( .A0(n2182), .A1(\BOOTH_instance/n397 ), .B0(
\BOOTH_instance/n229 ), .B1(\BOOTH_instance/n398 ), .C0(
\BOOTH_instance/n415 ), .Y(\BOOTH_instance/decoded[2][13] ) );
AOI22XL U2632 ( .A0(\BOOTH_instance/n376 ), .A1(N4724), .B0(
\BOOTH_instance/n377 ), .B1(\BOOTH_instance/n252 ), .Y(
\BOOTH_instance/n391 ) );
OAI221XL U2633 ( .A0(n2184), .A1(\BOOTH_instance/n373 ), .B0(
\BOOTH_instance/n239 ), .B1(\BOOTH_instance/n374 ), .C0(
\BOOTH_instance/n390 ), .Y(\BOOTH_instance/decoded[3][14] ) );
OAI221XL U2634 ( .A0(n2180), .A1(\BOOTH_instance/n397 ), .B0(
\BOOTH_instance/n219 ), .B1(\BOOTH_instance/n398 ), .C0(
\BOOTH_instance/n414 ), .Y(\BOOTH_instance/decoded[2][14] ) );
AOI22XL U2635 ( .A0(\BOOTH_instance/n376 ), .A1(n2185), .B0(
\BOOTH_instance/n377 ), .B1(\BOOTH_instance/n242 ), .Y(
\BOOTH_instance/n390 ) );
OAI221XL U2636 ( .A0(n2180), .A1(\BOOTH_instance/n373 ), .B0(
\BOOTH_instance/n219 ), .B1(\BOOTH_instance/n374 ), .C0(
\BOOTH_instance/n388 ), .Y(\BOOTH_instance/decoded[3][16] ) );
OAI221XL U2637 ( .A0(n2176), .A1(\BOOTH_instance/n397 ), .B0(
\BOOTH_instance/n199 ), .B1(\BOOTH_instance/n398 ), .C0(
\BOOTH_instance/n412 ), .Y(\BOOTH_instance/decoded[2][16] ) );
AOI22XL U2638 ( .A0(\BOOTH_instance/n376 ), .A1(n2181), .B0(
\BOOTH_instance/n377 ), .B1(\BOOTH_instance/n222 ), .Y(
\BOOTH_instance/n388 ) );
OAI221XL U2639 ( .A0(\BOOTH_instance/n260 ), .A1(\BOOTH_instance/n328 ),
.B0(\BOOTH_instance/n259 ), .B1(\BOOTH_instance/n323 ), .C0(
\BOOTH_instance/n338 ), .Y(\BOOTH_instance/decoded[5][16] ) );
OAI221XL U2640 ( .A0(n2184), .A1(\BOOTH_instance/n349 ), .B0(
\BOOTH_instance/n239 ), .B1(\BOOTH_instance/n350 ), .C0(
\BOOTH_instance/n363 ), .Y(\BOOTH_instance/decoded[4][16] ) );
AOI22XL U2641 ( .A0(\BOOTH_instance/n326 ), .A1(n2114), .B0(
\BOOTH_instance/n327 ), .B1(n1593), .Y(\BOOTH_instance/n338 ) );
OAI221XL U2642 ( .A0(n1604), .A1(\BOOTH_instance/n328 ), .B0(
\BOOTH_instance/n249 ), .B1(\BOOTH_instance/n323 ), .C0(
\BOOTH_instance/n337 ), .Y(\BOOTH_instance/decoded[5][17] ) );
OAI221XL U2643 ( .A0(n2182), .A1(\BOOTH_instance/n349 ), .B0(
\BOOTH_instance/n229 ), .B1(\BOOTH_instance/n350 ), .C0(
\BOOTH_instance/n362 ), .Y(\BOOTH_instance/decoded[4][17] ) );
AOI22XL U2644 ( .A0(\BOOTH_instance/n326 ), .A1(n2116), .B0(
\BOOTH_instance/n327 ), .B1(\BOOTH_instance/n252 ), .Y(
\BOOTH_instance/n337 ) );
NOR2XL U2645 ( .A(\BOOTH_instance/n315 ), .B(n1644), .Y(
\BOOTH_instance/decoded[8][18] ) );
OAI221XL U2646 ( .A0(n2184), .A1(\BOOTH_instance/n328 ), .B0(
\BOOTH_instance/n239 ), .B1(\BOOTH_instance/n323 ), .C0(
\BOOTH_instance/n336 ), .Y(\BOOTH_instance/decoded[5][18] ) );
OAI221XL U2647 ( .A0(n2180), .A1(\BOOTH_instance/n349 ), .B0(
\BOOTH_instance/n219 ), .B1(\BOOTH_instance/n350 ), .C0(
\BOOTH_instance/n361 ), .Y(\BOOTH_instance/decoded[4][18] ) );
AOI22XL U2648 ( .A0(\BOOTH_instance/n326 ), .A1(n2185), .B0(
\BOOTH_instance/n327 ), .B1(\BOOTH_instance/n242 ), .Y(
\BOOTH_instance/n336 ) );
OAI221XL U2649 ( .A0(n2180), .A1(\BOOTH_instance/n328 ), .B0(
\BOOTH_instance/n219 ), .B1(\BOOTH_instance/n323 ), .C0(
\BOOTH_instance/n334 ), .Y(\BOOTH_instance/decoded[5][20] ) );
OAI221XL U2650 ( .A0(n2176), .A1(\BOOTH_instance/n349 ), .B0(
\BOOTH_instance/n199 ), .B1(\BOOTH_instance/n350 ), .C0(
\BOOTH_instance/n359 ), .Y(\BOOTH_instance/decoded[4][20] ) );
AOI22XL U2651 ( .A0(\BOOTH_instance/n326 ), .A1(n2181), .B0(
\BOOTH_instance/n327 ), .B1(\BOOTH_instance/n222 ), .Y(
\BOOTH_instance/n334 ) );
NOR2XL U2652 ( .A(\BOOTH_instance/n315 ), .B(n2180), .Y(
\BOOTH_instance/decoded[8][26] ) );
INVXL U2653 ( .A(n2108), .Y(n2110) );
AO22XL U2654 ( .A0(EX_MULT_OUT[30]), .A1(n2142), .B0(EX_ALU_OUT[30]), .B1(
n2141), .Y(N4890) );
OAI2BB1XL U2655 ( .A0N(\ALU_instance/ADDER_OUT[30] ), .A1N(n1596), .B0(
\ALU_instance/n24 ), .Y(EX_ALU_OUT[30]) );
AOI22XL U2656 ( .A0(\ALU_instance/SHIFTER_OUT[30] ), .A1(\ALU_instance/n5 ),
.B0(\ALU_instance/LOGIC_OUT[30] ), .B1(\ALU_instance/n6 ), .Y(
\ALU_instance/n24 ) );
OAI2B2XL U2657 ( .A1N(N4857), .A0(\ALU_instance/LOGIC_GENERIC_I/n57 ), .B0(
N4857), .B1(\ALU_instance/LOGIC_GENERIC_I/n58 ), .Y(
\ALU_instance/LOGIC_OUT[30] ) );
AO22XL U2658 ( .A0(EX_MULT_OUT[29]), .A1(n2142), .B0(EX_ALU_OUT[29]), .B1(
n2141), .Y(N4889) );
OAI2BB1XL U2659 ( .A0N(\ALU_instance/ADDER_OUT[29] ), .A1N(n1596), .B0(
\ALU_instance/n25 ), .Y(EX_ALU_OUT[29]) );
AOI22XL U2660 ( .A0(\ALU_instance/SHIFTER_OUT[29] ), .A1(\ALU_instance/n5 ),
.B0(\ALU_instance/LOGIC_OUT[29] ), .B1(\ALU_instance/n6 ), .Y(
\ALU_instance/n25 ) );
OAI2B2XL U2661 ( .A1N(N4856), .A0(\ALU_instance/LOGIC_GENERIC_I/n63 ), .B0(
N4856), .B1(\ALU_instance/LOGIC_GENERIC_I/n64 ), .Y(
\ALU_instance/LOGIC_OUT[29] ) );
AO22XL U2662 ( .A0(EX_MULT_OUT[28]), .A1(n2142), .B0(EX_ALU_OUT[28]), .B1(
n2141), .Y(N4888) );
OAI2BB1XL U2663 ( .A0N(\ALU_instance/ADDER_OUT[28] ), .A1N(n1596), .B0(
\ALU_instance/n26 ), .Y(EX_ALU_OUT[28]) );
AOI22XL U2664 ( .A0(\ALU_instance/SHIFTER_OUT[28] ), .A1(\ALU_instance/n5 ),
.B0(\ALU_instance/LOGIC_OUT[28] ), .B1(\ALU_instance/n6 ), .Y(
\ALU_instance/n26 ) );
OAI2B2XL U2665 ( .A1N(N4855), .A0(\ALU_instance/LOGIC_GENERIC_I/n66 ), .B0(
N4855), .B1(\ALU_instance/LOGIC_GENERIC_I/n67 ), .Y(
\ALU_instance/LOGIC_OUT[28] ) );
AO22XL U2666 ( .A0(EX_MULT_OUT[27]), .A1(n2142), .B0(EX_ALU_OUT[27]), .B1(
n2141), .Y(N4887) );
OAI2BB1XL U2667 ( .A0N(\ALU_instance/ADDER_OUT[27] ), .A1N(n1596), .B0(
\ALU_instance/n27 ), .Y(EX_ALU_OUT[27]) );
AOI22XL U2668 ( .A0(\ALU_instance/SHIFTER_OUT[27] ), .A1(n2135), .B0(
\ALU_instance/LOGIC_OUT[27] ), .B1(\ALU_instance/n6 ), .Y(
\ALU_instance/n27 ) );
OAI2B2XL U2669 ( .A1N(N4854), .A0(\ALU_instance/LOGIC_GENERIC_I/n69 ), .B0(
N4854), .B1(\ALU_instance/LOGIC_GENERIC_I/n70 ), .Y(
\ALU_instance/LOGIC_OUT[27] ) );
AO22XL U2670 ( .A0(EX_MULT_OUT[26]), .A1(n2142), .B0(EX_ALU_OUT[26]), .B1(
n2141), .Y(N4886) );
OAI2BB1XL U2671 ( .A0N(\ALU_instance/ADDER_OUT[26] ), .A1N(n1596), .B0(
\ALU_instance/n28 ), .Y(EX_ALU_OUT[26]) );
AOI22XL U2672 ( .A0(\ALU_instance/SHIFTER_OUT[26] ), .A1(n2135), .B0(
\ALU_instance/LOGIC_OUT[26] ), .B1(n2136), .Y(\ALU_instance/n28 ) );
OAI2B2XL U2673 ( .A1N(N4853), .A0(\ALU_instance/LOGIC_GENERIC_I/n72 ), .B0(
N4853), .B1(\ALU_instance/LOGIC_GENERIC_I/n73 ), .Y(
\ALU_instance/LOGIC_OUT[26] ) );
AO22XL U2674 ( .A0(EX_MULT_OUT[25]), .A1(n2142), .B0(EX_ALU_OUT[25]), .B1(
n2141), .Y(N4885) );
OAI2BB1XL U2675 ( .A0N(\ALU_instance/ADDER_OUT[25] ), .A1N(n1596), .B0(
\ALU_instance/n29 ), .Y(EX_ALU_OUT[25]) );
AOI22XL U2676 ( .A0(\ALU_instance/SHIFTER_OUT[25] ), .A1(n2135), .B0(
\ALU_instance/LOGIC_OUT[25] ), .B1(n2136), .Y(\ALU_instance/n29 ) );
OAI2B2XL U2677 ( .A1N(N4852), .A0(\ALU_instance/LOGIC_GENERIC_I/n75 ), .B0(
N4852), .B1(\ALU_instance/LOGIC_GENERIC_I/n76 ), .Y(
\ALU_instance/LOGIC_OUT[25] ) );
AO22XL U2678 ( .A0(EX_MULT_OUT[24]), .A1(n2142), .B0(EX_ALU_OUT[24]), .B1(
n2141), .Y(N4884) );
OAI2BB1XL U2679 ( .A0N(\ALU_instance/ADDER_OUT[24] ), .A1N(n1596), .B0(
\ALU_instance/n30 ), .Y(EX_ALU_OUT[24]) );
AOI22XL U2680 ( .A0(\ALU_instance/SHIFTER_OUT[24] ), .A1(\ALU_instance/n5 ),
.B0(\ALU_instance/LOGIC_OUT[24] ), .B1(n2136), .Y(\ALU_instance/n30 )
);
OAI2B2XL U2681 ( .A1N(N4851), .A0(\ALU_instance/LOGIC_GENERIC_I/n78 ), .B0(
N4851), .B1(\ALU_instance/LOGIC_GENERIC_I/n79 ), .Y(
\ALU_instance/LOGIC_OUT[24] ) );
AO22XL U2682 ( .A0(EX_MULT_OUT[23]), .A1(n2142), .B0(EX_ALU_OUT[23]), .B1(
n2141), .Y(N4883) );
OAI2BB1XL U2683 ( .A0N(\ALU_instance/ADDER_OUT[23] ), .A1N(n1596), .B0(
\ALU_instance/n31 ), .Y(EX_ALU_OUT[23]) );
AOI22XL U2684 ( .A0(\ALU_instance/SHIFTER_OUT[23] ), .A1(n2135), .B0(
\ALU_instance/LOGIC_OUT[23] ), .B1(n2136), .Y(\ALU_instance/n31 ) );
OAI2B2XL U2685 ( .A1N(N4850), .A0(\ALU_instance/LOGIC_GENERIC_I/n81 ), .B0(
N4850), .B1(\ALU_instance/LOGIC_GENERIC_I/n82 ), .Y(
\ALU_instance/LOGIC_OUT[23] ) );
AO22XL U2686 ( .A0(EX_MULT_OUT[22]), .A1(n2142), .B0(EX_ALU_OUT[22]), .B1(
n2141), .Y(N4882) );
OAI2BB1XL U2687 ( .A0N(\ALU_instance/ADDER_OUT[22] ), .A1N(n1596), .B0(
\ALU_instance/n32 ), .Y(EX_ALU_OUT[22]) );
AOI22XL U2688 ( .A0(\ALU_instance/SHIFTER_OUT[22] ), .A1(n2135), .B0(
\ALU_instance/LOGIC_OUT[22] ), .B1(n2136), .Y(\ALU_instance/n32 ) );
OAI2B2XL U2689 ( .A1N(N4849), .A0(\ALU_instance/LOGIC_GENERIC_I/n84 ), .B0(
N4849), .B1(\ALU_instance/LOGIC_GENERIC_I/n85 ), .Y(
\ALU_instance/LOGIC_OUT[22] ) );
AO22XL U2690 ( .A0(EX_MULT_OUT[21]), .A1(n2142), .B0(EX_ALU_OUT[21]), .B1(
n2141), .Y(N4881) );
OAI2BB1XL U2691 ( .A0N(\ALU_instance/ADDER_OUT[21] ), .A1N(n1596), .B0(
\ALU_instance/n33 ), .Y(EX_ALU_OUT[21]) );
AOI22XL U2692 ( .A0(\ALU_instance/SHIFTER_OUT[21] ), .A1(n2135), .B0(
\ALU_instance/LOGIC_OUT[21] ), .B1(n2136), .Y(\ALU_instance/n33 ) );
OAI2B2XL U2693 ( .A1N(N4848), .A0(\ALU_instance/LOGIC_GENERIC_I/n87 ), .B0(
N4848), .B1(\ALU_instance/LOGIC_GENERIC_I/n88 ), .Y(
\ALU_instance/LOGIC_OUT[21] ) );
AO22XL U2694 ( .A0(EX_MULT_OUT[20]), .A1(n2142), .B0(EX_ALU_OUT[20]), .B1(
n2141), .Y(N4880) );
OAI2BB1XL U2695 ( .A0N(\ALU_instance/ADDER_OUT[20] ), .A1N(n1596), .B0(
\ALU_instance/n34 ), .Y(EX_ALU_OUT[20]) );
AOI22XL U2696 ( .A0(\ALU_instance/SHIFTER_OUT[20] ), .A1(n2135), .B0(
\ALU_instance/LOGIC_OUT[20] ), .B1(n2136), .Y(\ALU_instance/n34 ) );
OAI2B2XL U2697 ( .A1N(N4847), .A0(\ALU_instance/LOGIC_GENERIC_I/n90 ), .B0(
N4847), .B1(\ALU_instance/LOGIC_GENERIC_I/n91 ), .Y(
\ALU_instance/LOGIC_OUT[20] ) );
AO22XL U2698 ( .A0(EX_MULT_OUT[19]), .A1(n2142), .B0(EX_ALU_OUT[19]), .B1(
n2141), .Y(N4879) );
OAI2BB1XL U2699 ( .A0N(\ALU_instance/ADDER_OUT[19] ), .A1N(n1596), .B0(
\ALU_instance/n35 ), .Y(EX_ALU_OUT[19]) );
AOI22XL U2700 ( .A0(\ALU_instance/SHIFTER_OUT[19] ), .A1(n2135), .B0(
\ALU_instance/LOGIC_OUT[19] ), .B1(n2136), .Y(\ALU_instance/n35 ) );
OAI2B2XL U2701 ( .A1N(N4846), .A0(\ALU_instance/LOGIC_GENERIC_I/n96 ), .B0(
N4846), .B1(\ALU_instance/LOGIC_GENERIC_I/n97 ), .Y(
\ALU_instance/LOGIC_OUT[19] ) );
AO22XL U2702 ( .A0(EX_MULT_OUT[18]), .A1(n2142), .B0(EX_ALU_OUT[18]), .B1(
n2141), .Y(N4878) );
OAI2BB1XL U2703 ( .A0N(\ALU_instance/ADDER_OUT[18] ), .A1N(n1596), .B0(
\ALU_instance/n36 ), .Y(EX_ALU_OUT[18]) );
AOI22XL U2704 ( .A0(\ALU_instance/SHIFTER_OUT[18] ), .A1(n2135), .B0(
\ALU_instance/LOGIC_OUT[18] ), .B1(n2136), .Y(\ALU_instance/n36 ) );
OAI2B2XL U2705 ( .A1N(N4845), .A0(\ALU_instance/LOGIC_GENERIC_I/n99 ), .B0(
N4845), .B1(\ALU_instance/LOGIC_GENERIC_I/n100 ), .Y(
\ALU_instance/LOGIC_OUT[18] ) );
INVXL U2706 ( .A(n1645), .Y(\BOOTH_instance/n345 ) );
INVXL U2707 ( .A(n2163), .Y(n2169) );
OAI221XL U2708 ( .A0(n2124), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n113 ),
.B0(n2126), .B1(\ALU_instance/SHIFTER_GENERIC_I/C86/n119 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n120 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n15 ) );
AOI22XL U2709 ( .A0(n1686), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n25 ),
.B0(n1685), .B1(n2123), .Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n120 )
);
OAI221XL U2710 ( .A0(n2124), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n119 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n22 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n113 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n124 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n30 ) );
AOI22XL U2711 ( .A0(n1676), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n25 ),
.B0(n1686), .B1(n2123), .Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n124 )
);
OAI221XL U2712 ( .A0(n2124), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n113 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n22 ), .B1(n1667), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n128 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n39 ) );
AOI22XL U2713 ( .A0(n1681), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n25 ),
.B0(n1676), .B1(n2123), .Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n128 )
);
AOI22XL U2714 ( .A0(n2186), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n25 ),
.B0(N4723), .B1(\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n159 ) );
AOI22XL U2715 ( .A0(n2116), .A1(n2127), .B0(n2185), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n174 ) );
AOI22XL U2716 ( .A0(n2114), .A1(n2127), .B0(N4724), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n179 ) );
AO22XL U2717 ( .A0(n1648), .A1(n2122), .B0(n2173), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n146 ) );
AO22XL U2718 ( .A0(n2173), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ),
.B0(n2174), .B1(\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n128 ) );
AO22XL U2719 ( .A0(n2174), .A1(n2122), .B0(n2175), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n156 ) );
OAI221XL U2720 ( .A0(n2124), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n86 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n22 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n93 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n94 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n19 ) );
AOI22XL U2721 ( .A0(n1684), .A1(n2127), .B0(n1675), .B1(n2123), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n94 ) );
OAI221XL U2722 ( .A0(n2124), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n93 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n22 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n125 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n102 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n32 ) );
AOI22XL U2723 ( .A0(n1683), .A1(n2127), .B0(n1684), .B1(n2123), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n102 ) );
OAI221XL U2724 ( .A0(n2125), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n125 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n22 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n128 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n107 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n41 ) );
AOI22XL U2725 ( .A0(n1680), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n25 ),
.B0(n1683), .B1(n2123), .Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n107 )
);
OAI221XL U2726 ( .A0(n2125), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n128 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n22 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n113 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n114 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n49 ) );
AOI22XL U2727 ( .A0(n1685), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n25 ),
.B0(n1680), .B1(n2123), .Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n114 )
);
OAI221XL U2728 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n21 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n46 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n140 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n141 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n76 ) );
AOI22XL U2729 ( .A0(n1687), .A1(n2122), .B0(n1678), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n141 ) );
OAI221XL U2730 ( .A0(n2125), .A1(n1644), .B0(\BOOTH_instance/n307 ), .B1(
n2126), .C0(\ALU_instance/SHIFTER_GENERIC_I/C86/n168 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n82 ) );
AOI22XL U2731 ( .A0(n2127), .A1(N4721), .B0(n2186), .B1(n2123), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n168 ) );
OAI221XL U2732 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n43 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n139 ), .B0(n2120), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n140 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n159 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n65 ) );
AOI22XL U2733 ( .A0(n1679), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ),
.B0(n1687), .B1(\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n159 ) );
NAND2XL U2734 ( .A(\ALU_instance/SHIFTER_GENERIC_I/n37 ), .B(
\ALU_instance/SHIFTER_GENERIC_I/n38 ), .Y(
\ALU_instance/SHIFTER_OUT[31] ) );
NAND2XL U2735 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N265 ), .B(n2131), .Y(
\ALU_instance/SHIFTER_GENERIC_I/n37 ) );
AOI222XL U2736 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/N233 ), .A1(n2128),
.B0(n1689), .B1(n1613), .C0(\ALU_instance/SHIFTER_GENERIC_I/N168 ),
.C1(n2130), .Y(\ALU_instance/SHIFTER_GENERIC_I/n38 ) );
OAI221XL U2737 ( .A0(n2124), .A1(n1605), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n22 ), .B1(n2176), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n143 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n56 ) );
AOI22XL U2738 ( .A0(n2173), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n25 ),
.B0(n1648), .B1(\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n143 ) );
OAI221XL U2739 ( .A0(n2124), .A1(n2178), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n22 ), .B1(n2180), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n153 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n67 ) );
AOI22XL U2740 ( .A0(n2175), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n25 ),
.B0(n2174), .B1(\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n153 ) );
OAI221XL U2741 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n140 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n46 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n139 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n159 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n74 ) );
AOI22XL U2742 ( .A0(n1679), .A1(n2122), .B0(n1687), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n159 ) );
OAI221XL U2743 ( .A0(n2124), .A1(n2180), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n22 ), .B1(n2182), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n165 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n81 ) );
AOI22XL U2744 ( .A0(n2177), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n25 ),
.B0(n2175), .B1(\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n165 ) );
OAI221XL U2745 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n128 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n125 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n46 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n160 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n16 ) );
AOI22XL U2746 ( .A0(n1676), .A1(n2122), .B0(n1681), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n160 ) );
OAI221XL U2747 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n50 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n46 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n42 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n134 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n77 ) );
AOI22XL U2748 ( .A0(n1682), .A1(n2122), .B0(n1675), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n134 ) );
OAI221XL U2749 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n43 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n125 ), .B0(n2120), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n128 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n160 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n17 ) );
AOI22XL U2750 ( .A0(n1676), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ),
.B0(n1681), .B1(\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n160 ) );
OAI221XL U2751 ( .A0(n2119), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n50 ),
.B0(n2120), .B1(\ALU_instance/SHIFTER_GENERIC_I/C86/n58 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n145 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n78 ) );
AOI22XL U2752 ( .A0(n1675), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ),
.B0(n1684), .B1(n2123), .Y(\ALU_instance/SHIFTER_GENERIC_I/C50/n145 )
);
OAI221XL U2753 ( .A0(n2119), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n140 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n21 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n138 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n73 ) );
AOI22XL U2754 ( .A0(n1687), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ),
.B0(n1678), .B1(n2123), .Y(\ALU_instance/SHIFTER_GENERIC_I/C50/n138 )
);
OAI221XL U2755 ( .A0(n2119), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n23 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C50/n45 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n33 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n111 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n68 ) );
AOI22XL U2756 ( .A0(n1677), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ),
.B0(n1674), .B1(\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n111 ) );
OAI221XL U2757 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n58 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n46 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n50 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n144 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n84 ) );
AOI22XL U2758 ( .A0(n1675), .A1(n2122), .B0(n1684), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n144 ) );
OAI221XL U2759 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n64 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n46 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n58 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n124 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n11 ) );
AOI22XL U2760 ( .A0(n1684), .A1(n2122), .B0(n1683), .B1(n2123), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n124 ) );
OAI221XL U2761 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n125 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n46 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n93 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n127 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n9 ) );
AOI22XL U2762 ( .A0(n1686), .A1(n2122), .B0(n1676), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n127 ) );
OAI221XL U2763 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n125 ), .A1(n1641),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C50/n128 ), .B1(n1640), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n145 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n29 ) );
AOI22XL U2764 ( .A0(n1680), .A1(n2121), .B0(n1683), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n52 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n145 ) );
OAI221XL U2765 ( .A0(n2119), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n58 ),
.B0(n2120), .B1(\ALU_instance/SHIFTER_GENERIC_I/C86/n64 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n107 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n11 ) );
AOI22XL U2766 ( .A0(n1684), .A1(n2122), .B0(n1683), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n107 ) );
OAI221XL U2767 ( .A0(\BOOTH_instance/n158 ), .A1(\BOOTH_instance/n259 ),
.B0(\BOOTH_instance/n166 ), .B1(\BOOTH_instance/n260 ), .C0(
\BOOTH_instance/n261 ), .Y(\BOOTH_instance/n253 ) );
AOI22XL U2768 ( .A0(n2115), .A1(\BOOTH_instance/n168 ), .B0(n1593), .B1(
\BOOTH_instance/n150 ), .Y(\BOOTH_instance/n261 ) );
OAI221XL U2769 ( .A0(\BOOTH_instance/n158 ), .A1(\BOOTH_instance/n249 ),
.B0(\BOOTH_instance/n166 ), .B1(n1604), .C0(\BOOTH_instance/n251 ),
.Y(\BOOTH_instance/n243 ) );
AOI22XL U2770 ( .A0(n2117), .A1(\BOOTH_instance/n168 ), .B0(
\BOOTH_instance/n252 ), .B1(\BOOTH_instance/n150 ), .Y(
\BOOTH_instance/n251 ) );
OAI221XL U2771 ( .A0(\BOOTH_instance/n158 ), .A1(\BOOTH_instance/n219 ),
.B0(\BOOTH_instance/n166 ), .B1(n2180), .C0(\BOOTH_instance/n221 ),
.Y(\BOOTH_instance/n213 ) );
AOI22XL U2772 ( .A0(n2181), .A1(\BOOTH_instance/n168 ), .B0(
\BOOTH_instance/n222 ), .B1(\BOOTH_instance/n150 ), .Y(
\BOOTH_instance/n221 ) );
OAI221XL U2773 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n43 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n21 ), .B0(n2120), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n23 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n148 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n76 ) );
AOI22XL U2774 ( .A0(n1678), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ),
.B0(n1677), .B1(n2123), .Y(\ALU_instance/SHIFTER_GENERIC_I/C50/n148 )
);
OAI221XL U2775 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n43 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n33 ), .B0(n2120), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n42 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n158 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n72 ) );
AOI22XL U2776 ( .A0(n1674), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ),
.B0(n1682), .B1(n2123), .Y(\ALU_instance/SHIFTER_GENERIC_I/C50/n158 )
);
AOI22XL U2777 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .A1(n1688),
.B0(n2122), .B1(n1689), .Y(\ALU_instance/SHIFTER_GENERIC_I/C50/n55 )
);
OAI221XL U2778 ( .A0(\BOOTH_instance/n186 ), .A1(\BOOTH_instance/n260 ),
.B0(n1603), .B1(\BOOTH_instance/n259 ), .C0(\BOOTH_instance/n278 ),
.Y(\BOOTH_instance/n274 ) );
AOI22XL U2779 ( .A0(N4723), .A1(\BOOTH_instance/n188 ), .B0(n1593), .B1(
\BOOTH_instance/n176 ), .Y(\BOOTH_instance/n278 ) );
OAI221XL U2780 ( .A0(\BOOTH_instance/n186 ), .A1(n1604), .B0(n1603), .B1(
\BOOTH_instance/n249 ), .C0(\BOOTH_instance/n268 ), .Y(
\BOOTH_instance/n264 ) );
AOI22XL U2781 ( .A0(N4724), .A1(\BOOTH_instance/n188 ), .B0(
\BOOTH_instance/n252 ), .B1(\BOOTH_instance/n176 ), .Y(
\BOOTH_instance/n268 ) );
OAI221XL U2782 ( .A0(\BOOTH_instance/n186 ), .A1(n2180), .B0(n1603), .B1(
\BOOTH_instance/n219 ), .C0(\BOOTH_instance/n238 ), .Y(
\BOOTH_instance/n234 ) );
AOI22XL U2783 ( .A0(n2181), .A1(\BOOTH_instance/n188 ), .B0(
\BOOTH_instance/n222 ), .B1(\BOOTH_instance/n176 ), .Y(
\BOOTH_instance/n238 ) );
OAI221XL U2784 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n42 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n46 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n33 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n158 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n75 ) );
AOI22XL U2785 ( .A0(n1674), .A1(n2122), .B0(n1682), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n158 ) );
OAI221XL U2786 ( .A0(\BOOTH_instance/n155 ), .A1(n1644), .B0(n1718), .B1(
\BOOTH_instance/n290 ), .C0(\BOOTH_instance/n291 ), .Y(
\BOOTH_instance/n283 ) );
AOI22XL U2787 ( .A0(\BOOTH_instance/n292 ), .A1(\BOOTH_instance/n149 ), .B0(
N4721), .B1(\BOOTH_instance/n282 ), .Y(\BOOTH_instance/n291 ) );
AOI222XL U2788 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n10 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n15 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n41 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n150 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n8 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n37 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n149 ) );
OAI221XL U2789 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ), .A1(n1644),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n46 ), .B1(n2188), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n155 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n150 ) );
AOI22XL U2790 ( .A0(N4719), .A1(n2122), .B0(n2108), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n155 ) );
OAI221XL U2791 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n30 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n38 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n91 ), .B1(n2168), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n92 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N106 ) );
AOI222XL U2792 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n10 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n7 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n41 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n93 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n8 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n33 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n92 ) );
OAI221XL U2793 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ), .A1(n2188),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n46 ), .B1(n2187), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n96 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n93 ) );
AOI22XL U2794 ( .A0(n2189), .A1(n2122), .B0(N4719), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n96 ) );
OAI221XL U2795 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n10 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n11 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n12 ), .B1(n2169), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n13 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N233 ) );
AOI222XL U2796 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n14 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n15 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n16 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n17 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n18 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n19 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n13 ) );
OAI221XL U2797 ( .A0(n2124), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n21 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n22 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n23 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n24 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n17 ) );
INVXL U2798 ( .A(n1679), .Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n21 ) );
OAI221XL U2799 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n27 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n11 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n28 ), .B1(n2168), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n29 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N232 ) );
AOI222XL U2800 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n14 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n30 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n16 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n31 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n18 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n32 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n29 ) );
OAI221XL U2801 ( .A0(n2124), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n23 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n22 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n33 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n34 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n31 ) );
AOI22XL U2802 ( .A0(n1679), .A1(n2127), .B0(n1688), .B1(n2123), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n34 ) );
OAI221XL U2803 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n36 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n11 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n37 ), .B1(n2168), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n38 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N231 ) );
AOI222XL U2804 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n14 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n39 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n16 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n40 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n18 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n41 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n38 ) );
OAI221XL U2805 ( .A0(n2125), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n33 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n22 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n42 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n43 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n40 ) );
AOI22XL U2806 ( .A0(n1687), .A1(n2127), .B0(n1679), .B1(n2123), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n43 ) );
OAI221XL U2807 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n44 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n11 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n45 ), .B1(n2168), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n46 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N230 ) );
AOI222XL U2808 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n14 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n47 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n16 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n48 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n18 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n49 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n46 ) );
OAI221XL U2809 ( .A0(n2125), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n42 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n22 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n50 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n51 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n48 ) );
AOI22XL U2810 ( .A0(n1678), .A1(n2127), .B0(n1687), .B1(n2123), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n51 ) );
OAI221XL U2811 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n32 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n38 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n79 ), .B1(n2168), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n80 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/N138 ) );
AOI222XL U2812 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n10 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n7 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n16 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n81 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n8 ), .C1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n12 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n80 ) );
OAI221XL U2813 ( .A0(n2119), .A1(n2187), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n45 ), .B1(n2188), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n86 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n81 ) );
AOI22XL U2814 ( .A0(n2189), .A1(n2122), .B0(N4719), .B1(n2123), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n86 ) );
OAI211XL U2815 ( .A0(n1540), .A1(n1539), .B0(n1537), .C0(n1544), .Y(n1553)
);
OAI221XL U2816 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C86/n93 ), .A1(n1641),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n125 ), .B1(n1640), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n135 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n23 ) );
AOI22XL U2817 ( .A0(n1683), .A1(n2121), .B0(n1684), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n52 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n135 ) );
OAI221XL U2818 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n43 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n64 ), .B0(n2120), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n132 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n161 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n18 ) );
AOI22XL U2819 ( .A0(n1683), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .B1(n1680), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n161 ) );
OAI221XL U2820 ( .A0(n2119), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n93 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n125 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n117 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n9 ) );
AOI22XL U2821 ( .A0(n1686), .A1(n2122), .B0(n1676), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n117 ) );
OAI221XL U2822 ( .A0(n2119), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n42 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C50/n45 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n50 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n142 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n75 ) );
AOI22XL U2823 ( .A0(n1682), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ),
.B0(n1675), .B1(n2123), .Y(\ALU_instance/SHIFTER_GENERIC_I/C50/n142 )
);
OAI221XL U2824 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n43 ), .A1(n2178),
.B0(n2120), .B1(n2180), .C0(\ALU_instance/SHIFTER_GENERIC_I/C50/n152 ),
.Y(\ALU_instance/SHIFTER_GENERIC_I/C50/n19 ) );
AOI22XL U2825 ( .A0(n2181), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ),
.B0(n2183), .B1(n2123), .Y(\ALU_instance/SHIFTER_GENERIC_I/C50/n152 )
);
INVXL U2826 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C48/n161 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n17 ) );
AOI221XL U2827 ( .A0(n2121), .A1(n1684), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n52 ), .B1(n1675), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n162 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n161 ) );
OAI2B2XL U2828 ( .A1N(n1683), .A0(n1641), .B0(n1640), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n93 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n162 ) );
XOR2XL U2829 ( .A(n2133), .B(N4842), .Y(\ALU_instance/INTERNAL_B[15] ) );
XOR2XL U2830 ( .A(n2133), .B(N4848), .Y(\ALU_instance/INTERNAL_B[21] ) );
XOR2XL U2831 ( .A(n2133), .B(N4844), .Y(\ALU_instance/INTERNAL_B[17] ) );
XOR2XL U2832 ( .A(n2133), .B(N4849), .Y(\ALU_instance/INTERNAL_B[22] ) );
XOR2XL U2833 ( .A(n2133), .B(N4852), .Y(\ALU_instance/INTERNAL_B[25] ) );
XOR2XL U2834 ( .A(n2133), .B(N4845), .Y(\ALU_instance/INTERNAL_B[18] ) );
XOR2XL U2835 ( .A(n2132), .B(N4856), .Y(\ALU_instance/INTERNAL_B[29] ) );
XOR2XL U2836 ( .A(n2133), .B(N4850), .Y(\ALU_instance/INTERNAL_B[23] ) );
XOR2XL U2837 ( .A(n2133), .B(N4853), .Y(\ALU_instance/INTERNAL_B[26] ) );
XOR2XL U2838 ( .A(n2133), .B(N4846), .Y(\ALU_instance/INTERNAL_B[19] ) );
XOR2XL U2839 ( .A(n2132), .B(N4857), .Y(\ALU_instance/INTERNAL_B[30] ) );
XOR2XL U2840 ( .A(n2132), .B(N4854), .Y(\ALU_instance/INTERNAL_B[27] ) );
XOR2XL U2841 ( .A(n2132), .B(\EX_ALU_B[31] ), .Y(
\ALU_instance/INTERNAL_B[31] ) );
INVXL U2842 ( .A(n1561), .Y(n1588) );
AND2XL U2843 ( .A(\ALU_instance/INTERNAL_B[28] ), .B(n1687), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA0/add_1_root_add_20_2/carry[1] ) );
AO22XL U2844 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S1[0] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[4] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S0[0] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/n2 ), .Y(
\ALU_instance/ADDER_OUT[16] ) );
XNOR2XL U2845 ( .A(n1681), .B(\ALU_instance/INTERNAL_B[16] ), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S1[0] ) );
XOR2XL U2846 ( .A(\ALU_instance/INTERNAL_B[16] ), .B(n1681), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/S0[0] ) );
AO22XL U2847 ( .A0(\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S1[0] ), .A1(
\ALU_instance/CARRY_SELECT_ADDER_I/CARRY[5] ), .B0(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S0[0] ), .B1(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/n2 ), .Y(
\ALU_instance/ADDER_OUT[20] ) );
XNOR2XL U2848 ( .A(n1680), .B(\ALU_instance/INTERNAL_B[20] ), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S1[0] ) );
XOR2XL U2849 ( .A(\ALU_instance/INTERNAL_B[20] ), .B(n1680), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/S0[0] ) );
INVXL U2850 ( .A(n1556), .Y(n1544) );
OR3XL U2851 ( .A(N4840), .B(N4841), .C(\BOOTH_instance/n315 ), .Y(n1718) );
INVXL U2852 ( .A(\ALU_instance/SHIFTER_GENERIC_I/N202 ), .Y(n2111) );
OR2XL U2853 ( .A(\ALU_instance/INTERNAL_B[20] ), .B(n1680), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA1/add_1_root_add_20_2/carry[1] ) );
OR2XL U2854 ( .A(\ALU_instance/INTERNAL_B[16] ), .B(n1681), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA1/add_1_root_add_20_2/carry[1] ) );
OR2XL U2855 ( .A(\ALU_instance/INTERNAL_B[24] ), .B(n1682), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA1/add_1_root_add_20_2/carry[1] ) );
OR2XL U2856 ( .A(\ALU_instance/INTERNAL_B[28] ), .B(n1687), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_7/RCA1/add_1_root_add_20_2/carry[1] ) );
AND2XL U2857 ( .A(\ALU_instance/INTERNAL_B[20] ), .B(n1680), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_5/RCA0/add_1_root_add_20_2/carry[1] ) );
AND2XL U2858 ( .A(\ALU_instance/INTERNAL_B[16] ), .B(n1681), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_4/RCA0/add_1_root_add_20_2/carry[1] ) );
AND2XL U2859 ( .A(\ALU_instance/INTERNAL_B[24] ), .B(n1682), .Y(
\ALU_instance/CARRY_SELECT_ADDER_I/CSB_6/RCA0/add_1_root_add_20_2/carry[1] ) );
XOR2XL U2860 ( .A(n2134), .B(N4839), .Y(\ALU_instance/INTERNAL_B[12] ) );
AO22XL U2861 ( .A0(EX_MULT_OUT[5]), .A1(n2142), .B0(EX_ALU_OUT[5]), .B1(
n2141), .Y(N4865) );
OAI2BB1XL U2862 ( .A0N(\ALU_instance/ADDER_OUT[5] ), .A1N(n1596), .B0(
\ALU_instance/n16 ), .Y(EX_ALU_OUT[5]) );
AOI22XL U2863 ( .A0(\ALU_instance/SHIFTER_OUT[5] ), .A1(\ALU_instance/n5 ),
.B0(\ALU_instance/LOGIC_OUT[5] ), .B1(\ALU_instance/n6 ), .Y(
\ALU_instance/n16 ) );
OAI2B2XL U2864 ( .A1N(N4832), .A0(\ALU_instance/LOGIC_GENERIC_I/n45 ), .B0(
N4832), .B1(\ALU_instance/LOGIC_GENERIC_I/n46 ), .Y(
\ALU_instance/LOGIC_OUT[5] ) );
XOR2XL U2865 ( .A(n2132), .B(N4835), .Y(\ALU_instance/INTERNAL_B[8] ) );
XOR2XL U2866 ( .A(n2133), .B(N4847), .Y(\ALU_instance/INTERNAL_B[20] ) );
XOR2XL U2867 ( .A(n2133), .B(N4843), .Y(\ALU_instance/INTERNAL_B[16] ) );
XOR2XL U2868 ( .A(n2133), .B(N4851), .Y(\ALU_instance/INTERNAL_B[24] ) );
XOR2XL U2869 ( .A(n2132), .B(N4855), .Y(\ALU_instance/INTERNAL_B[28] ) );
AO22XL U2870 ( .A0(EX_MULT_OUT[17]), .A1(n2142), .B0(EX_ALU_OUT[17]), .B1(
n2141), .Y(N4877) );
OAI2BB1XL U2871 ( .A0N(\ALU_instance/ADDER_OUT[17] ), .A1N(n1596), .B0(
\ALU_instance/n37 ), .Y(EX_ALU_OUT[17]) );
AOI22XL U2872 ( .A0(\ALU_instance/SHIFTER_OUT[17] ), .A1(n2135), .B0(
\ALU_instance/LOGIC_OUT[17] ), .B1(n2136), .Y(\ALU_instance/n37 ) );
OAI2B2XL U2873 ( .A1N(N4844), .A0(\ALU_instance/LOGIC_GENERIC_I/n102 ), .B0(
N4844), .B1(\ALU_instance/LOGIC_GENERIC_I/n103 ), .Y(
\ALU_instance/LOGIC_OUT[17] ) );
AO22XL U2874 ( .A0(EX_MULT_OUT[16]), .A1(n2142), .B0(EX_ALU_OUT[16]), .B1(
n2141), .Y(N4876) );
OAI2BB1XL U2875 ( .A0N(\ALU_instance/ADDER_OUT[16] ), .A1N(n1596), .B0(
\ALU_instance/n38 ), .Y(EX_ALU_OUT[16]) );
AOI22XL U2876 ( .A0(\ALU_instance/SHIFTER_OUT[16] ), .A1(n2135), .B0(
\ALU_instance/LOGIC_OUT[16] ), .B1(n2136), .Y(\ALU_instance/n38 ) );
OAI2B2XL U2877 ( .A1N(N4843), .A0(\ALU_instance/LOGIC_GENERIC_I/n105 ), .B0(
N4843), .B1(\ALU_instance/LOGIC_GENERIC_I/n106 ), .Y(
\ALU_instance/LOGIC_OUT[16] ) );
AO22XL U2878 ( .A0(EX_MULT_OUT[15]), .A1(n2142), .B0(EX_ALU_OUT[15]), .B1(
n2141), .Y(N4875) );
OAI2BB1XL U2879 ( .A0N(\ALU_instance/ADDER_OUT[15] ), .A1N(n1596), .B0(
\ALU_instance/n4 ), .Y(EX_ALU_OUT[15]) );
AOI22XL U2880 ( .A0(\ALU_instance/SHIFTER_OUT[15] ), .A1(n2135), .B0(
\ALU_instance/LOGIC_OUT[15] ), .B1(n2136), .Y(\ALU_instance/n4 ) );
OAI2B2XL U2881 ( .A1N(N4842), .A0(\ALU_instance/LOGIC_GENERIC_I/n108 ), .B0(
N4842), .B1(\ALU_instance/LOGIC_GENERIC_I/n109 ), .Y(
\ALU_instance/LOGIC_OUT[15] ) );
AO22XL U2882 ( .A0(EX_MULT_OUT[14]), .A1(n2142), .B0(EX_ALU_OUT[14]), .B1(
n2141), .Y(N4874) );
OAI2BB1XL U2883 ( .A0N(\ALU_instance/ADDER_OUT[14] ), .A1N(n1596), .B0(
\ALU_instance/n7 ), .Y(EX_ALU_OUT[14]) );
AOI22XL U2884 ( .A0(\ALU_instance/SHIFTER_OUT[14] ), .A1(\ALU_instance/n5 ),
.B0(\ALU_instance/LOGIC_OUT[14] ), .B1(\ALU_instance/n6 ), .Y(
\ALU_instance/n7 ) );
OAI2B2XL U2885 ( .A1N(N4841), .A0(\ALU_instance/LOGIC_GENERIC_I/n111 ), .B0(
N4841), .B1(\ALU_instance/LOGIC_GENERIC_I/n112 ), .Y(
\ALU_instance/LOGIC_OUT[14] ) );
AO22XL U2886 ( .A0(EX_MULT_OUT[13]), .A1(n2142), .B0(EX_ALU_OUT[13]), .B1(
n2141), .Y(N4873) );
OAI2BB1XL U2887 ( .A0N(\ALU_instance/ADDER_OUT[13] ), .A1N(n1596), .B0(
\ALU_instance/n8 ), .Y(EX_ALU_OUT[13]) );
AOI22XL U2888 ( .A0(\ALU_instance/SHIFTER_OUT[13] ), .A1(\ALU_instance/n5 ),
.B0(\ALU_instance/LOGIC_OUT[13] ), .B1(\ALU_instance/n6 ), .Y(
\ALU_instance/n8 ) );
OAI2B2XL U2889 ( .A1N(N4840), .A0(\ALU_instance/LOGIC_GENERIC_I/n114 ), .B0(
N4840), .B1(\ALU_instance/LOGIC_GENERIC_I/n115 ), .Y(
\ALU_instance/LOGIC_OUT[13] ) );
AO22XL U2890 ( .A0(EX_MULT_OUT[12]), .A1(n2142), .B0(EX_ALU_OUT[12]), .B1(
n2141), .Y(N4872) );
OAI2BB1XL U2891 ( .A0N(\ALU_instance/ADDER_OUT[12] ), .A1N(n1596), .B0(
\ALU_instance/n9 ), .Y(EX_ALU_OUT[12]) );
AOI22XL U2892 ( .A0(\ALU_instance/SHIFTER_OUT[12] ), .A1(n2135), .B0(
\ALU_instance/LOGIC_OUT[12] ), .B1(\ALU_instance/n6 ), .Y(
\ALU_instance/n9 ) );
OAI2B2XL U2893 ( .A1N(N4839), .A0(\ALU_instance/LOGIC_GENERIC_I/n117 ), .B0(
N4839), .B1(\ALU_instance/LOGIC_GENERIC_I/n118 ), .Y(
\ALU_instance/LOGIC_OUT[12] ) );
AO22XL U2894 ( .A0(EX_MULT_OUT[11]), .A1(n2142), .B0(EX_ALU_OUT[11]), .B1(
n2141), .Y(N4871) );
OAI2BB1XL U2895 ( .A0N(\ALU_instance/ADDER_OUT[11] ), .A1N(n1596), .B0(
\ALU_instance/n10 ), .Y(EX_ALU_OUT[11]) );
AOI22XL U2896 ( .A0(\ALU_instance/SHIFTER_OUT[11] ), .A1(\ALU_instance/n5 ),
.B0(\ALU_instance/LOGIC_OUT[11] ), .B1(n2136), .Y(\ALU_instance/n10 )
);
OAI2B2XL U2897 ( .A1N(n1645), .A0(\ALU_instance/LOGIC_GENERIC_I/n120 ), .B0(
n1645), .B1(\ALU_instance/LOGIC_GENERIC_I/n121 ), .Y(
\ALU_instance/LOGIC_OUT[11] ) );
AO22XL U2898 ( .A0(EX_MULT_OUT[10]), .A1(n2142), .B0(EX_ALU_OUT[10]), .B1(
n2141), .Y(N4870) );
OAI2BB1XL U2899 ( .A0N(\ALU_instance/ADDER_OUT[10] ), .A1N(n1596), .B0(
\ALU_instance/n11 ), .Y(EX_ALU_OUT[10]) );
AOI22XL U2900 ( .A0(\ALU_instance/SHIFTER_OUT[10] ), .A1(\ALU_instance/n5 ),
.B0(\ALU_instance/LOGIC_OUT[10] ), .B1(n2136), .Y(\ALU_instance/n11 )
);
OAI2B2XL U2901 ( .A1N(N4837), .A0(\ALU_instance/LOGIC_GENERIC_I/n123 ), .B0(
N4837), .B1(\ALU_instance/LOGIC_GENERIC_I/n124 ), .Y(
\ALU_instance/LOGIC_OUT[10] ) );
AO22XL U2902 ( .A0(EX_MULT_OUT[9]), .A1(n2142), .B0(EX_ALU_OUT[9]), .B1(
n2141), .Y(N4869) );
OAI2BB1XL U2903 ( .A0N(\ALU_instance/ADDER_OUT[9] ), .A1N(n1596), .B0(
\ALU_instance/n12 ), .Y(EX_ALU_OUT[9]) );
AOI22XL U2904 ( .A0(\ALU_instance/SHIFTER_OUT[9] ), .A1(\ALU_instance/n5 ),
.B0(\ALU_instance/LOGIC_OUT[9] ), .B1(\ALU_instance/n6 ), .Y(
\ALU_instance/n12 ) );
OAI2B2XL U2905 ( .A1N(N4836), .A0(\ALU_instance/LOGIC_GENERIC_I/n33 ), .B0(
N4836), .B1(\ALU_instance/LOGIC_GENERIC_I/n34 ), .Y(
\ALU_instance/LOGIC_OUT[9] ) );
AO22XL U2906 ( .A0(EX_MULT_OUT[8]), .A1(n2142), .B0(EX_ALU_OUT[8]), .B1(
n2141), .Y(N4868) );
OAI2BB1XL U2907 ( .A0N(\ALU_instance/ADDER_OUT[8] ), .A1N(n1596), .B0(
\ALU_instance/n13 ), .Y(EX_ALU_OUT[8]) );
AOI22XL U2908 ( .A0(\ALU_instance/SHIFTER_OUT[8] ), .A1(\ALU_instance/n5 ),
.B0(\ALU_instance/LOGIC_OUT[8] ), .B1(\ALU_instance/n6 ), .Y(
\ALU_instance/n13 ) );
OAI2B2XL U2909 ( .A1N(N4835), .A0(\ALU_instance/LOGIC_GENERIC_I/n36 ), .B0(
N4835), .B1(\ALU_instance/LOGIC_GENERIC_I/n37 ), .Y(
\ALU_instance/LOGIC_OUT[8] ) );
AO22XL U2910 ( .A0(EX_MULT_OUT[7]), .A1(n2142), .B0(EX_ALU_OUT[7]), .B1(
n2141), .Y(N4867) );
OAI2BB1XL U2911 ( .A0N(\ALU_instance/ADDER_OUT[7] ), .A1N(n1596), .B0(
\ALU_instance/n14 ), .Y(EX_ALU_OUT[7]) );
AOI22XL U2912 ( .A0(\ALU_instance/SHIFTER_OUT[7] ), .A1(\ALU_instance/n5 ),
.B0(\ALU_instance/LOGIC_OUT[7] ), .B1(\ALU_instance/n6 ), .Y(
\ALU_instance/n14 ) );
OAI2B2XL U2913 ( .A1N(N4834), .A0(\ALU_instance/LOGIC_GENERIC_I/n39 ), .B0(
N4834), .B1(\ALU_instance/LOGIC_GENERIC_I/n40 ), .Y(
\ALU_instance/LOGIC_OUT[7] ) );
AO22XL U2914 ( .A0(EX_MULT_OUT[6]), .A1(n2142), .B0(EX_ALU_OUT[6]), .B1(
n2141), .Y(N4866) );
OAI2BB1XL U2915 ( .A0N(\ALU_instance/ADDER_OUT[6] ), .A1N(n1596), .B0(
\ALU_instance/n15 ), .Y(EX_ALU_OUT[6]) );
AOI22XL U2916 ( .A0(\ALU_instance/SHIFTER_OUT[6] ), .A1(\ALU_instance/n5 ),
.B0(\ALU_instance/LOGIC_OUT[6] ), .B1(\ALU_instance/n6 ), .Y(
\ALU_instance/n15 ) );
OAI2B2XL U2917 ( .A1N(N4833), .A0(\ALU_instance/LOGIC_GENERIC_I/n42 ), .B0(
N4833), .B1(\ALU_instance/LOGIC_GENERIC_I/n43 ), .Y(
\ALU_instance/LOGIC_OUT[6] ) );
AOI32XL U2918 ( .A0(n1535), .A1(n1398), .A2(n1547), .B0(n1527), .B1(n1534),
.Y(n1531) );
OAI221XL U2919 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n113 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n46 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n128 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n138 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n22 ) );
AOI22XL U2920 ( .A0(n1681), .A1(n2122), .B0(n1648), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n138 ) );
OAI221XL U2921 ( .A0(n2124), .A1(n1667), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n22 ), .B1(n1605), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n137 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n47 ) );
AOI22XL U2922 ( .A0(n1648), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n25 ),
.B0(n1681), .B1(n2123), .Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n137 )
);
OAI221XL U2923 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n43 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n86 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n93 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n146 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n31 ) );
AOI22XL U2924 ( .A0(n2122), .A1(n1685), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .B1(n1686), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n146 ) );
OAI221XL U2925 ( .A0(n2119), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n132 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C50/n45 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n86 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n134 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n25 ) );
AOI22XL U2926 ( .A0(n2122), .A1(n1680), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .B1(n1685), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n134 ) );
OAI221XL U2927 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n23 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n46 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n21 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n147 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n83 ) );
AOI22XL U2928 ( .A0(n1678), .A1(n2122), .B0(n1677), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C48/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n147 ) );
OAI221XL U2929 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n33 ), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n46 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n23 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n121 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n71 ) );
AOI22XL U2930 ( .A0(n1677), .A1(n2122), .B0(n1674), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C50/n49 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n121 ) );
INVXL U2931 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n61 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n26 ) );
OAI221XL U2932 ( .A0(n2119), .A1(n2182), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ), .B1(n2184), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n63 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n61 ) );
AOI22XL U2933 ( .A0(n2185), .A1(n2122), .B0(n2116), .B1(n2123), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n63 ) );
INVXL U2934 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n87 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n32 ) );
OAI221XL U2935 ( .A0(n2119), .A1(n2184), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n45 ), .B1(n1604), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n89 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n87 ) );
AOI22XL U2936 ( .A0(N4724), .A1(n2122), .B0(n2114), .B1(n2123), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n89 ) );
OAI2B2XL U2937 ( .A1N(n1525), .A0(n1705), .B0(n1530), .B1(n1374), .Y(
EX_SHIFTER_CW[0]) );
AOI221XL U2938 ( .A0(n2121), .A1(n2116), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n52 ), .B1(n2185), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n163 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n34 ) );
OAI22XL U2939 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C48/n45 ), .A1(n1641),
.B0(n2187), .B1(n1640), .Y(\ALU_instance/SHIFTER_GENERIC_I/C48/n163 )
);
OAI31XL U2940 ( .A0(n1544), .A1(n1549), .A2(n1536), .B0(n1557), .Y(
EX_COMPARATOR_CW[5]) );
OAI221XL U2941 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n43 ), .A1(n2188),
.B0(n2120), .B1(n1644), .C0(\ALU_instance/SHIFTER_GENERIC_I/C50/n155 ),
.Y(\ALU_instance/SHIFTER_GENERIC_I/C50/n151 ) );
AOI22XL U2942 ( .A0(n2112), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/N202 ), .B1(n2123), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n155 ) );
NAND3XL U2943 ( .A(n1546), .B(n1551), .C(n1552), .Y(EX_ALU_SEL[0]) );
AOI211XL U2944 ( .A0(n1705), .A1(n1553), .B0(EX_COMPARATOR_CW[5]), .C0(
EX_COMPARATOR_CW[1]), .Y(n1552) );
MXI2XL U2945 ( .A(n1688), .B(n1689), .S0(n1640), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n79 ) );
OAI2B2XL U2946 ( .A1N(n1598), .A0(\ALU_instance/LOGIC_GENERIC_I/n93 ), .B0(
n1598), .B1(\ALU_instance/LOGIC_GENERIC_I/n94 ), .Y(
\ALU_instance/LOGIC_OUT[1] ) );
NAND2XL U2947 ( .A(n2191), .B(N4719), .Y(\ALU_instance/LOGIC_GENERIC_I/n94 )
);
AOI22XL U2948 ( .A0(n2190), .A1(\BOOTH_instance/n307 ), .B0(n2112), .B1(
EX_LOGIC_CW[3]), .Y(\ALU_instance/LOGIC_GENERIC_I/n93 ) );
OAI2B2XL U2949 ( .A1N(n2157), .A0(\ALU_instance/LOGIC_GENERIC_I/n60 ), .B0(
n1599), .B1(\ALU_instance/LOGIC_GENERIC_I/n61 ), .Y(
\ALU_instance/LOGIC_OUT[2] ) );
NAND2XL U2950 ( .A(n2191), .B(n2189), .Y(\ALU_instance/LOGIC_GENERIC_I/n61 )
);
AOI22XL U2951 ( .A0(n2190), .A1(n1644), .B0(n2189), .B1(n2193), .Y(
\ALU_instance/LOGIC_GENERIC_I/n60 ) );
OAI2B2XL U2952 ( .A1N(\EX_ALU_B[31] ), .A0(
\ALU_instance/LOGIC_GENERIC_I/n54 ), .B0(\EX_ALU_B[31] ), .B1(
\ALU_instance/LOGIC_GENERIC_I/n55 ), .Y(\ALU_instance/LOGIC_OUT[31] )
);
NAND2XL U2953 ( .A(n2192), .B(n1689), .Y(\ALU_instance/LOGIC_GENERIC_I/n55 )
);
AOI22XL U2954 ( .A0(n2190), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n139 ),
.B0(n1689), .B1(EX_LOGIC_CW[3]), .Y(\ALU_instance/LOGIC_GENERIC_I/n54 ) );
NOR3XL U2955 ( .A(n1542), .B(n1559), .C(n1560), .Y(n1530) );
AOI22XL U2956 ( .A0(n2190), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n140 ),
.B0(n1688), .B1(n2193), .Y(\ALU_instance/LOGIC_GENERIC_I/n57 ) );
AOI22XL U2957 ( .A0(n2192), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n21 ),
.B0(n1679), .B1(n2193), .Y(\ALU_instance/LOGIC_GENERIC_I/n63 ) );
AOI22XL U2958 ( .A0(n2190), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n23 ),
.B0(n1687), .B1(n2193), .Y(\ALU_instance/LOGIC_GENERIC_I/n66 ) );
AOI22XL U2959 ( .A0(n2192), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n33 ),
.B0(n1678), .B1(n2193), .Y(\ALU_instance/LOGIC_GENERIC_I/n69 ) );
AOI22XL U2960 ( .A0(n2190), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n42 ),
.B0(n1677), .B1(n2193), .Y(\ALU_instance/LOGIC_GENERIC_I/n72 ) );
AOI22XL U2961 ( .A0(n2192), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n50 ),
.B0(n1674), .B1(n2193), .Y(\ALU_instance/LOGIC_GENERIC_I/n75 ) );
AOI22XL U2962 ( .A0(n2192), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n58 ),
.B0(n1682), .B1(n2193), .Y(\ALU_instance/LOGIC_GENERIC_I/n78 ) );
AOI22XL U2963 ( .A0(n2190), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n64 ),
.B0(n1675), .B1(n2193), .Y(\ALU_instance/LOGIC_GENERIC_I/n81 ) );
AOI22XL U2964 ( .A0(n2190), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n132 ),
.B0(n1684), .B1(n2193), .Y(\ALU_instance/LOGIC_GENERIC_I/n84 ) );
AOI22XL U2965 ( .A0(n2192), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n86 ),
.B0(n1683), .B1(n2193), .Y(\ALU_instance/LOGIC_GENERIC_I/n87 ) );
AOI22XL U2966 ( .A0(n2190), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n93 ),
.B0(n1680), .B1(n2193), .Y(\ALU_instance/LOGIC_GENERIC_I/n90 ) );
AOI22XL U2967 ( .A0(n2190), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n125 ),
.B0(n1685), .B1(EX_LOGIC_CW[3]), .Y(\ALU_instance/LOGIC_GENERIC_I/n96 ) );
AOI22XL U2968 ( .A0(n2190), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n128 ),
.B0(n1686), .B1(EX_LOGIC_CW[3]), .Y(\ALU_instance/LOGIC_GENERIC_I/n99 ) );
AOI22XL U2969 ( .A0(n2190), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n113 ),
.B0(n1676), .B1(EX_LOGIC_CW[3]), .Y(
\ALU_instance/LOGIC_GENERIC_I/n102 ) );
AOI22XL U2970 ( .A0(n2190), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n119 ),
.B0(n1681), .B1(EX_LOGIC_CW[3]), .Y(
\ALU_instance/LOGIC_GENERIC_I/n105 ) );
AOI22XL U2971 ( .A0(n2190), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n113 ),
.B0(n1648), .B1(EX_LOGIC_CW[3]), .Y(
\ALU_instance/LOGIC_GENERIC_I/n108 ) );
AOI22XL U2972 ( .A0(n2190), .A1(n2180), .B0(n2179), .B1(EX_LOGIC_CW[3]), .Y(
\ALU_instance/LOGIC_GENERIC_I/n123 ) );
AOI22XL U2973 ( .A0(n2191), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n47 ),
.B0(N4724), .B1(EX_LOGIC_CW[3]), .Y(\ALU_instance/LOGIC_GENERIC_I/n42 ) );
AOI22XL U2974 ( .A0(n2191), .A1(\ALU_instance/SHIFTER_GENERIC_I/C48/n45 ),
.B0(N4723), .B1(EX_LOGIC_CW[3]), .Y(\ALU_instance/LOGIC_GENERIC_I/n45 ) );
AOI22XL U2975 ( .A0(n1688), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n25 ),
.B0(n1689), .B1(n2123), .Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n24 )
);
OAI221XL U2976 ( .A0(n2119), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n128 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C50/n45 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n113 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n130 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n24 ) );
AOI22XL U2977 ( .A0(n1681), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ),
.B0(n1648), .B1(n2123), .Y(\ALU_instance/SHIFTER_GENERIC_I/C50/n130 )
);
OAI221XL U2978 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n43 ), .A1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n113 ), .B0(n2120), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n119 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n147 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n30 ) );
AOI22XL U2979 ( .A0(n1648), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n48 ),
.B0(n2173), .B1(n2123), .Y(\ALU_instance/SHIFTER_GENERIC_I/C50/n147 )
);
NAND2XL U2980 ( .A(n2191), .B(N4723), .Y(\ALU_instance/LOGIC_GENERIC_I/n46 )
);
NAND2XL U2981 ( .A(n2191), .B(N4724), .Y(\ALU_instance/LOGIC_GENERIC_I/n43 )
);
AOI21XL U2982 ( .A0(n2156), .A1(n1689), .B0(
\ALU_instance/SHIFTER_GENERIC_I/C48/n73 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C48/n117 ) );
NAND2XL U2983 ( .A(n1705), .B(n1542), .Y(n1536) );
NAND2XL U2984 ( .A(n2192), .B(n1648), .Y(\ALU_instance/LOGIC_GENERIC_I/n109 ) );
NAND2XL U2985 ( .A(n2192), .B(n1675), .Y(\ALU_instance/LOGIC_GENERIC_I/n82 )
);
NAND2XL U2986 ( .A(n2192), .B(n1676), .Y(\ALU_instance/LOGIC_GENERIC_I/n103 ) );
NAND2XL U2987 ( .A(n2192), .B(n1679), .Y(\ALU_instance/LOGIC_GENERIC_I/n64 )
);
NAND2XL U2988 ( .A(n2192), .B(n1678), .Y(\ALU_instance/LOGIC_GENERIC_I/n70 )
);
NAND2XL U2989 ( .A(n2192), .B(n1677), .Y(\ALU_instance/LOGIC_GENERIC_I/n73 )
);
NAND2XL U2990 ( .A(n2192), .B(n1674), .Y(\ALU_instance/LOGIC_GENERIC_I/n76 )
);
NAND2XL U2991 ( .A(n2192), .B(n1686), .Y(\ALU_instance/LOGIC_GENERIC_I/n100 ) );
NAND2XL U2992 ( .A(n2192), .B(n1684), .Y(\ALU_instance/LOGIC_GENERIC_I/n85 )
);
NAND2XL U2993 ( .A(n2192), .B(n1683), .Y(\ALU_instance/LOGIC_GENERIC_I/n88 )
);
NAND2XL U2994 ( .A(n2192), .B(n1685), .Y(\ALU_instance/LOGIC_GENERIC_I/n97 )
);
NAND2XL U2995 ( .A(n2192), .B(n1688), .Y(\ALU_instance/LOGIC_GENERIC_I/n58 )
);
NAND2XL U2996 ( .A(n2192), .B(n1687), .Y(\ALU_instance/LOGIC_GENERIC_I/n67 )
);
NAND2XL U2997 ( .A(n2192), .B(n1682), .Y(\ALU_instance/LOGIC_GENERIC_I/n79 )
);
NAND2XL U2998 ( .A(n2192), .B(n1680), .Y(\ALU_instance/LOGIC_GENERIC_I/n91 )
);
NAND2XL U2999 ( .A(n2192), .B(n1681), .Y(\ALU_instance/LOGIC_GENERIC_I/n106 ) );
INVXL U3000 ( .A(n2114), .Y(\ALU_instance/SHIFTER_GENERIC_I/C48/n45 ) );
INVXL U3001 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n57 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n10 ) );
OAI221XL U3002 ( .A0(n2125), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n50 ),
.B0(n2126), .B1(\ALU_instance/SHIFTER_GENERIC_I/C86/n58 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n59 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n57 ) );
AOI22XL U3003 ( .A0(n1677), .A1(n2127), .B0(n1678), .B1(n2123), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n59 ) );
INVXL U3004 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n63 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n27 ) );
OAI221XL U3005 ( .A0(n2124), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n58 ),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C86/n22 ), .B1(
\ALU_instance/SHIFTER_GENERIC_I/C86/n64 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n65 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n63 ) );
AOI22XL U3006 ( .A0(n1674), .A1(n2127), .B0(n1677), .B1(n2123), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n65 ) );
INVXL U3007 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n77 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n36 ) );
OAI221XL U3008 ( .A0(n2124), .A1(\ALU_instance/SHIFTER_GENERIC_I/C86/n64 ),
.B0(n2126), .B1(\ALU_instance/SHIFTER_GENERIC_I/C50/n132 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n79 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n77 ) );
AOI22XL U3009 ( .A0(n1682), .A1(n2127), .B0(n1674), .B1(n2123), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n79 ) );
INVXL U3010 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C86/n85 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n44 ) );
OAI221XL U3011 ( .A0(n2125), .A1(\ALU_instance/SHIFTER_GENERIC_I/C50/n132 ),
.B0(n2126), .B1(\ALU_instance/SHIFTER_GENERIC_I/C86/n86 ), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C86/n87 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n85 ) );
AOI22XL U3012 ( .A0(n1675), .A1(n2127), .B0(n1682), .B1(n2123), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C86/n87 ) );
INVXL U3013 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n50 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n20 ) );
OAI221XL U3014 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n43 ), .A1(n2180),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C48/n44 ), .B1(n2182), .C0(
\ALU_instance/SHIFTER_GENERIC_I/C50/n53 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n50 ) );
AOI22XL U3015 ( .A0(n2183), .A1(n2122), .B0(n2185), .B1(n2123), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n53 ) );
INVXL U3016 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C50/n162 ), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n35 ) );
OAI221XL U3017 ( .A0(\ALU_instance/SHIFTER_GENERIC_I/C50/n43 ), .A1(n1604),
.B0(\ALU_instance/SHIFTER_GENERIC_I/C50/n45 ), .B1(
\BOOTH_instance/n260 ), .C0(\ALU_instance/SHIFTER_GENERIC_I/C50/n163 ),
.Y(\ALU_instance/SHIFTER_GENERIC_I/C50/n162 ) );
AOI22XL U3018 ( .A0(N4723), .A1(n2122), .B0(n2186), .B1(n2123), .Y(
\ALU_instance/SHIFTER_GENERIC_I/C50/n163 ) );
INVXL U3019 ( .A(n2116), .Y(\ALU_instance/SHIFTER_GENERIC_I/C48/n47 ) );
INVXL U3020 ( .A(n2115), .Y(\ALU_instance/SHIFTER_GENERIC_I/C50/n46 ) );
INVXL U3021 ( .A(N4723), .Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n166 ) );
INVXL U3022 ( .A(N4724), .Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n155 ) );
INVXL U3023 ( .A(n1559), .Y(n1523) );
CLKBUFX1 U3024 ( .A(EX_LOGIC_CW[2]), .Y(n2192) );
INVXL U3025 ( .A(n1685), .Y(\ALU_instance/SHIFTER_GENERIC_I/C48/n125 ) );
INVXL U3026 ( .A(EX_SHIFTER_CW[1]), .Y(\ALU_instance/SHIFTER_GENERIC_I/n89 )
);
AND2XL U3027 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][1] ), .B(
n1607), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][1] ) );
AND2XL U3028 ( .A(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[1][0] ), .B(
n1607), .Y(\ALU_instance/SHIFTER_GENERIC_I/C88/ML_int[2][0] ) );
INVXL U3029 ( .A(n1689), .Y(\ALU_instance/SHIFTER_GENERIC_I/C50/n139 ) );
INVXL U3030 ( .A(n1648), .Y(\ALU_instance/SHIFTER_GENERIC_I/C50/n113 ) );
INVXL U3031 ( .A(n1675), .Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n64 ) );
INVXL U3032 ( .A(n1676), .Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n113 ) );
INVXL U3033 ( .A(n1678), .Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n33 ) );
INVXL U3034 ( .A(n1677), .Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n42 ) );
INVXL U3035 ( .A(n1674), .Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n50 ) );
INVXL U3036 ( .A(n1686), .Y(\ALU_instance/SHIFTER_GENERIC_I/C50/n128 ) );
INVXL U3037 ( .A(n1684), .Y(\ALU_instance/SHIFTER_GENERIC_I/C50/n132 ) );
INVXL U3038 ( .A(n1683), .Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n86 ) );
INVXL U3039 ( .A(n1688), .Y(\ALU_instance/SHIFTER_GENERIC_I/C48/n140 ) );
INVXL U3040 ( .A(n1687), .Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n23 ) );
INVXL U3041 ( .A(n1682), .Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n58 ) );
INVXL U3042 ( .A(n1680), .Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n93 ) );
INVXL U3043 ( .A(n1681), .Y(\ALU_instance/SHIFTER_GENERIC_I/C86/n119 ) );
NOR2XL U3044 ( .A(n1483), .B(n1293), .Y(n1195) );
AOI21XL U3045 ( .A0(n1290), .A1(n1291), .B0(n1227), .Y(n1225) );
OAI2BB2XL U3046 ( .B0(ID_REGA_ZERO), .B1(n1479), .A0N(n1194), .A1N(
ID_REGA_ZERO), .Y(n1517) );
NOR2XL U3047 ( .A(\zero_instance/n1 ), .B(\zero_instance/n2 ), .Y(
ID_REGA_ZERO) );
NAND4XL U3048 ( .A(\zero_instance/n7 ), .B(\zero_instance/n8 ), .C(
\zero_instance/n9 ), .D(\zero_instance/n10 ), .Y(\zero_instance/n1 )
);
NOR2XL U3049 ( .A(n1290), .B(n1518), .Y(n1485) );
NOR2XL U3050 ( .A(n1370), .B(n1190), .Y(n1498) );
INVXL U3051 ( .A(n1516), .Y(n1478) );
CLKBUFX1 U3052 ( .A(n1226), .Y(n2143) );
CLKBUFX3 U3053 ( .A(n697), .Y(n2153) );
CLKBUFX1 U3054 ( .A(n697), .Y(n2151) );
BUFX2 U3055 ( .A(n697), .Y(n2152) );
INVXL U3056 ( .A(n1291), .Y(n1293) );
INVXL U3057 ( .A(n1358), .Y(N4717) );
BUFX2 U3058 ( .A(n697), .Y(n2154) );
INVXL U3059 ( .A(n1520), .Y(n1197) );
NOR2XL U3060 ( .A(n1484), .B(n1615), .Y(ID_INSTR_AFTER_CU[27]) );
NOR2XL U3061 ( .A(n1481), .B(n1615), .Y(ID_INSTR_AFTER_CU[29]) );
NOR2XL U3062 ( .A(n1488), .B(n1615), .Y(ID_INSTR_AFTER_CU[31]) );
NOR2XL U3063 ( .A(n1205), .B(n1615), .Y(ID_INSTR_AFTER_CU[7]) );
NOR2XL U3064 ( .A(n1204), .B(n1615), .Y(ID_INSTR_AFTER_CU[9]) );
NOR2XL U3065 ( .A(n1203), .B(n1615), .Y(ID_INSTR_AFTER_CU[8]) );
NOR2XL U3066 ( .A(n1433), .B(n1615), .Y(ID_INSTR_AFTER_CU[17]) );
NOR2XL U3067 ( .A(n1432), .B(n1615), .Y(ID_INSTR_AFTER_CU[16]) );
NOR2XL U3068 ( .A(n1434), .B(n1615), .Y(ID_INSTR_AFTER_CU[19]) );
NAND2XL U3069 ( .A(n1522), .B(n1290), .Y(ID_INSTR_AFTER_CU[28]) );
NAND2XL U3070 ( .A(n1522), .B(n1483), .Y(ID_INSTR_AFTER_CU[30]) );
NAND2XL U3071 ( .A(n1522), .B(n1518), .Y(ID_INSTR_AFTER_CU[26]) );
AND2XL U3072 ( .A(n2106), .B(n1522), .Y(ID_INSTR_AFTER_CU[15]) );
OAI32XL U3073 ( .A0(n1373), .A1(n1374), .A2(n1375), .B0(n1376), .B1(n1377),
.Y(n1368) );
OR2XL U3074 ( .A(n1378), .B(n1379), .Y(n1375) );
OAI32XL U3075 ( .A0(n1441), .A1(n1422), .A2(n1442), .B0(n1443), .B1(n1216),
.Y(n1439) );
OR2XL U3076 ( .A(n1446), .B(n1447), .Y(n1442) );
INVXL U3077 ( .A(n1438), .Y(n1443) );
OAI32XL U3078 ( .A0(n1359), .A1(n1360), .A2(n1361), .B0(n1357), .B1(n1362),
.Y(N4712) );
NAND2XL U3079 ( .A(n1194), .B(n1195), .Y(n1359) );
AOI21XL U3080 ( .A0(n1190), .A1(n1363), .B0(n1364), .Y(n1362) );
AOI22XL U3081 ( .A0(n1365), .A1(n1366), .B0(n1367), .B1(n1361), .Y(n1364) );
OAI2B2XL U3082 ( .A1N(n1369), .A0(n1361), .B0(n1376), .B1(n1374), .Y(n1363)
);
XNOR2XL U3083 ( .A(RF_ADD_WR[2]), .B(n1427), .Y(n1474) );
XNOR2XL U3084 ( .A(RF_ADD_WR[1]), .B(n1433), .Y(n1490) );
XNOR2XL U3085 ( .A(RF_ADD_WR[4]), .B(n1407), .Y(n1475) );
OAI2B2XL U3086 ( .A1N(n1360), .A0(n1368), .B0(n1371), .B1(n1372), .Y(n1365)
);
NAND4XL U3087 ( .A(n1343), .B(n1344), .C(n1340), .D(n1348), .Y(n1493) );
NOR3XL U3088 ( .A(n1419), .B(n1435), .C(n1417), .Y(n1413) );
NAND3XL U3089 ( .A(n1344), .B(n1471), .C(n1339), .Y(n1338) );
OAI21XL U3090 ( .A0(n1369), .A1(n1368), .B0(n1370), .Y(n1366) );
INVXL U3091 ( .A(n1435), .Y(n1422) );
OAI211XL U3092 ( .A0(n1328), .A1(n1309), .B0(n1208), .C0(n1329), .Y(N6250)
);
NAND2XL U3093 ( .A(WB_DATA_EXT_16[7]), .B(n2146), .Y(n1329) );
NOR2XL U3094 ( .A(n1819), .B(n1328), .Y(WB_DATA_EXT_16[7]) );
OAI211XL U3095 ( .A0(n1326), .A1(n1309), .B0(n1208), .C0(n1327), .Y(N6251)
);
NAND2XL U3096 ( .A(WB_DATA_EXT_16[8]), .B(n2146), .Y(n1327) );
NOR2XL U3097 ( .A(n1819), .B(n1326), .Y(WB_DATA_EXT_16[8]) );
OAI211XL U3098 ( .A0(n1324), .A1(n1309), .B0(n1208), .C0(n1325), .Y(N6252)
);
NAND2XL U3099 ( .A(WB_DATA_EXT_16[9]), .B(n2146), .Y(n1325) );
NOR2XL U3100 ( .A(n1324), .B(n1819), .Y(WB_DATA_EXT_16[9]) );
OAI211XL U3101 ( .A0(n1322), .A1(n1309), .B0(n1208), .C0(n1323), .Y(N6253)
);
NAND2XL U3102 ( .A(WB_DATA_EXT_16[10]), .B(n2146), .Y(n1323) );
NOR2XL U3103 ( .A(n1819), .B(n1322), .Y(WB_DATA_EXT_16[10]) );
OAI211XL U3104 ( .A0(n1320), .A1(n1309), .B0(n1208), .C0(n1321), .Y(N6254)
);
NAND2XL U3105 ( .A(WB_DATA_EXT_16[11]), .B(n2146), .Y(n1321) );
NOR2XL U3106 ( .A(n1819), .B(n1320), .Y(WB_DATA_EXT_16[11]) );
OAI211XL U3107 ( .A0(n1318), .A1(n1309), .B0(n1208), .C0(n1319), .Y(N6255)
);
NAND2XL U3108 ( .A(WB_DATA_EXT_16[12]), .B(n2146), .Y(n1319) );
NOR2XL U3109 ( .A(n1819), .B(n1318), .Y(WB_DATA_EXT_16[12]) );
OAI211XL U3110 ( .A0(n1316), .A1(n1309), .B0(n1208), .C0(n1317), .Y(N6256)
);
NAND2XL U3111 ( .A(WB_DATA_EXT_16[13]), .B(n2146), .Y(n1317) );
NOR2XL U3112 ( .A(n1819), .B(n1316), .Y(WB_DATA_EXT_16[13]) );
OAI211XL U3113 ( .A0(n1314), .A1(n1309), .B0(n1208), .C0(n1315), .Y(N6257)
);
NAND2XL U3114 ( .A(WB_DATA_EXT_16[14]), .B(n2146), .Y(n1315) );
NOR2XL U3115 ( .A(n1819), .B(n1314), .Y(WB_DATA_EXT_16[14]) );
OAI211XL U3116 ( .A0(n1312), .A1(n1309), .B0(n1208), .C0(n1313), .Y(N6258)
);
NAND2XL U3117 ( .A(WB_DATA_EXT_16[15]), .B(n2146), .Y(n1313) );
INVXL U3118 ( .A(n2107), .Y(WB_DATA_EXT_16[15]) );
AOI31XL U3119 ( .A0(n1194), .A1(n1195), .A2(n1357), .B0(n1358), .Y(N4716) );
INVXL U3120 ( .A(n1328), .Y(WB_DATA_EXT_8[9]) );
INVXL U3121 ( .A(n1312), .Y(WB_DATA_EXT_16[31]) );
NAND2XL U3122 ( .A(WB_DATA_EXT_16[31]), .B(WB_SIGN_EXT_16_CONTROL), .Y(
\WB_SIGN_EXT_16_instance/n27 ) );
OR3XL U3123 ( .A(n1370), .B(n1371), .C(n1372), .Y(n1440) );
NAND3XL U3124 ( .A(n1203), .B(n1204), .C(n1205), .Y(n1202) );
INVXL U3125 ( .A(n1216), .Y(n1417) );
INVXL U3126 ( .A(n1341), .Y(n1330) );
NAND2BXL U3127 ( .AN(PORT_R_W), .B(n1216), .Y(PORT_EN) );
NAND2XL U3128 ( .A(n1445), .B(n1219), .Y(n1213) );
AND3XL U3129 ( .A(n1397), .B(n1398), .C(n1399), .Y(n1357) );
INVXL U3130 ( .A(n1215), .Y(n1212) );
NAND2XL U3131 ( .A(n1199), .B(n1191), .Y(RF_RD1) );
INVXL U3132 ( .A(WB_DATA_EXT_8[0]), .Y(\WB_SIGN_EXT_16_instance/n34 ) );
INVXL U3133 ( .A(WB_DATA_EXT_8[1]), .Y(\WB_SIGN_EXT_16_instance/n33 ) );
INVXL U3134 ( .A(WB_DATA_EXT_8[2]), .Y(\WB_SIGN_EXT_16_instance/n28 ) );
INVXL U3135 ( .A(WB_DATA_EXT_8[3]), .Y(\WB_SIGN_EXT_16_instance/n25 ) );
INVXL U3136 ( .A(WB_DATA_EXT_8[4]), .Y(\WB_SIGN_EXT_16_instance/n24 ) );
INVXL U3137 ( .A(WB_DATA_EXT_8[5]), .Y(\WB_SIGN_EXT_16_instance/n23 ) );
INVXL U3138 ( .A(WB_DATA_EXT_8[6]), .Y(\WB_SIGN_EXT_16_instance/n22 ) );
AND2XL U3139 ( .A(n1214), .B(n1215), .Y(PORT_SIZE[0]) );
OAI2BB1XL U3140 ( .A0N(WB_DATA_EXT_8[0]), .A1N(n1330), .B0(n1337), .Y(N6243)
);
AOI22XL U3141 ( .A0(n1616), .A1(WB_DATA_EXT_8[0]), .B0(WB_DATA_EXT_16[0]),
.B1(n2146), .Y(n1337) );
NOR2XL U3142 ( .A(n1819), .B(\WB_SIGN_EXT_16_instance/n34 ), .Y(
WB_DATA_EXT_16[0]) );
OAI2BB1XL U3143 ( .A0N(WB_DATA_EXT_8[1]), .A1N(n1330), .B0(n1336), .Y(N6244)
);
AOI22XL U3144 ( .A0(n1616), .A1(WB_DATA_EXT_8[1]), .B0(WB_DATA_EXT_16[1]),
.B1(n1211), .Y(n1336) );
NOR2XL U3145 ( .A(n1819), .B(\WB_SIGN_EXT_16_instance/n33 ), .Y(
WB_DATA_EXT_16[1]) );
OAI2BB1XL U3146 ( .A0N(WB_DATA_EXT_8[2]), .A1N(n1330), .B0(n1335), .Y(N6245)
);
AOI22XL U3147 ( .A0(n1616), .A1(WB_DATA_EXT_8[2]), .B0(WB_DATA_EXT_16[2]),
.B1(n1211), .Y(n1335) );
NOR2XL U3148 ( .A(n1819), .B(\WB_SIGN_EXT_16_instance/n28 ), .Y(
WB_DATA_EXT_16[2]) );
OAI2BB1XL U3149 ( .A0N(WB_DATA_EXT_8[3]), .A1N(n1330), .B0(n1334), .Y(N6246)
);
AOI22XL U3150 ( .A0(n1616), .A1(WB_DATA_EXT_8[3]), .B0(WB_DATA_EXT_16[3]),
.B1(n1211), .Y(n1334) );
NOR2XL U3151 ( .A(n1819), .B(\WB_SIGN_EXT_16_instance/n25 ), .Y(
WB_DATA_EXT_16[3]) );
OAI2BB1XL U3152 ( .A0N(WB_DATA_EXT_8[4]), .A1N(n1330), .B0(n1333), .Y(N6247)
);
AOI22XL U3153 ( .A0(n1616), .A1(WB_DATA_EXT_8[4]), .B0(WB_DATA_EXT_16[4]),
.B1(n1211), .Y(n1333) );
NOR2XL U3154 ( .A(n1819), .B(\WB_SIGN_EXT_16_instance/n24 ), .Y(
WB_DATA_EXT_16[4]) );
OAI2BB1XL U3155 ( .A0N(WB_DATA_EXT_8[5]), .A1N(n1330), .B0(n1332), .Y(N6248)
);
AOI22XL U3156 ( .A0(n1616), .A1(WB_DATA_EXT_8[5]), .B0(WB_DATA_EXT_16[5]),
.B1(n1211), .Y(n1332) );
NOR2XL U3157 ( .A(n1819), .B(\WB_SIGN_EXT_16_instance/n23 ), .Y(
WB_DATA_EXT_16[5]) );
OAI2BB1XL U3158 ( .A0N(WB_DATA_EXT_8[6]), .A1N(n1330), .B0(n1331), .Y(N6249)
);
AOI22XL U3159 ( .A0(n1616), .A1(WB_DATA_EXT_8[6]), .B0(WB_DATA_EXT_16[6]),
.B1(n1211), .Y(n1331) );
NOR2XL U3160 ( .A(n1819), .B(\WB_SIGN_EXT_16_instance/n22 ), .Y(
WB_DATA_EXT_16[6]) );
AOI222XL U3161 ( .A0(EX_COMPARATOR_CW[3]), .A1(\ALU_instance/OVERFLOW ),
.B0(EX_COMPARATOR_CW[0]), .B1(\ALU_instance/ZERO ), .C0(
EX_COMPARATOR_CW[4]), .C1(\ALU_instance/COMPARATOR_GENERIC_I/n9 ), .Y(
\ALU_instance/COMPARATOR_GENERIC_I/n4 ) );
OAI31XL U3162 ( .A0(n1539), .A1(n1374), .A2(n1540), .B0(n1541), .Y(
EX_COMPARATOR_CW[3]) );
OAI21XL U3163 ( .A0(n1536), .A1(n1537), .B0(n1538), .Y(EX_COMPARATOR_CW[4])
);
OAI31XL U3164 ( .A0(n1544), .A1(EX_INSTR[2]), .A2(n1536), .B0(n1545), .Y(
EX_COMPARATOR_CW[0]) );
OAI2B11XL U3165 ( .A1N(n1356), .A0(EX_INSTR[26]), .B0(n1374), .C0(n1351),
.Y(n1564) );
OAI22XL U3166 ( .A0(n1567), .A1(n1568), .B0(EX_INSTR[31]), .B1(n1400), .Y(
n1356) );
NOR3XL U3167 ( .A(EX_INSTR[29]), .B(EX_INSTR[30]), .C(n1567), .Y(n1569) );
OAI211XL U3168 ( .A0(n1584), .A1(n1585), .B0(n1581), .C0(EX_INSTR[29]), .Y(
n1543) );
AND2XL U3169 ( .A(n1573), .B(EX_INSTR[30]), .Y(n1585) );
NOR2XL U3170 ( .A(n1565), .B(EX_INSTR[26]), .Y(n1528) );
NAND4XL U3171 ( .A(EX_INSTR[30]), .B(n1577), .C(EX_INSTR[29]), .D(
EX_INSTR[27]), .Y(n1538) );
NAND3XL U3172 ( .A(EX_INSTR[30]), .B(n1580), .C(n1397), .Y(n1541) );
NAND2BXL U3173 ( .AN(n1578), .B(n1608), .Y(n1377) );
AOI33XL U3174 ( .A0(n1580), .A1(EX_INSTR[31]), .A2(n1577), .B0(EX_INSTR[29]),
.B1(n1573), .B2(n1581), .Y(n1578) );
OAI211XL U3175 ( .A0(n1547), .A1(n1577), .B0(EX_INSTR[31]), .C0(n1563), .Y(
n1571) );
AOI2B1XL U3176 ( .A1N(n2150), .A0(EX_REGB[3]), .B0(n1353), .Y(n1352) );
INVXL U3177 ( .A(N4831), .Y(n2164) );
NAND4XL U3178 ( .A(n1563), .B(EX_INSTR[26]), .C(n1565), .D(n1566), .Y(n1351)
);
NOR3XL U3179 ( .A(EX_INSTR[6]), .B(EX_INSTR[10]), .C(n1590), .Y(n1561) );
OR3XL U3180 ( .A(EX_INSTR[9]), .B(EX_INSTR[8]), .C(EX_INSTR[7]), .Y(n1590)
);
NOR3XL U3181 ( .A(n1550), .B(EX_INSTR[1]), .C(n1540), .Y(n1556) );
NAND3BXL U3182 ( .AN(EX_INSTR[4]), .B(EX_INSTR[5]), .C(n1561), .Y(n1550) );
OAI32XL U3183 ( .A0(n1553), .A1(n1582), .A2(n1374), .B0(n1574), .B1(n1583),
.Y(EX_ADD_SUB) );
OAI21XL U3184 ( .A0(n1567), .A1(n1570), .B0(n1374), .Y(n1583) );
NOR3XL U3185 ( .A(n1550), .B(EX_INSTR[2]), .C(n1560), .Y(n1582) );
NAND3XL U3186 ( .A(EX_INSTR[3]), .B(EX_INSTR[5]), .C(n1587), .Y(n1537) );
NOR3XL U3187 ( .A(n1560), .B(EX_INSTR[2]), .C(n1588), .Y(n1587) );
INVXL U3188 ( .A(EX_INSTR[2]), .Y(n1549) );
NAND3XL U3189 ( .A(EX_INSTR[5]), .B(EX_INSTR[0]), .C(n1589), .Y(n1539) );
NOR3XL U3190 ( .A(n1549), .B(EX_INSTR[1]), .C(n1588), .Y(n1589) );
INVXL U3191 ( .A(EX_INSTR[3]), .Y(n1540) );
NAND2XL U3192 ( .A(n1228), .B(n1229), .Y(N760) );
AOI22XL U3193 ( .A0(RF_OUT1[30]), .A1(n1643), .B0(IF_PC_INC[30]), .B1(n1225),
.Y(n1229) );
AOI22XL U3194 ( .A0(ID_PC[30]), .A1(n1226), .B0(ID_PC_SUM[30]), .B1(n1227),
.Y(n1228) );
XOR2XL U3195 ( .A(PORT_PC[30]), .B(\add_502/carry[30] ), .Y(IF_PC_INC[30])
);
NAND2XL U3196 ( .A(n1230), .B(n1231), .Y(N759) );
AOI22XL U3197 ( .A0(RF_OUT1[29]), .A1(n2145), .B0(IF_PC_INC[29]), .B1(n1225),
.Y(n1231) );
AOI22XL U3198 ( .A0(ID_PC[29]), .A1(n1226), .B0(ID_PC_SUM[29]), .B1(n1227),
.Y(n1230) );
XOR2XL U3199 ( .A(PORT_PC[29]), .B(\add_502/carry[29] ), .Y(IF_PC_INC[29])
);
NAND2XL U3200 ( .A(n1232), .B(n1233), .Y(N758) );
AOI22XL U3201 ( .A0(RF_OUT1[28]), .A1(n1643), .B0(IF_PC_INC[28]), .B1(n2144),
.Y(n1233) );
AOI22XL U3202 ( .A0(ID_PC[28]), .A1(n1226), .B0(ID_PC_SUM[28]), .B1(n1227),
.Y(n1232) );
XOR2XL U3203 ( .A(PORT_PC[28]), .B(\add_502/carry[28] ), .Y(IF_PC_INC[28])
);
NAND2XL U3204 ( .A(n1234), .B(n1235), .Y(N757) );
AOI22XL U3205 ( .A0(RF_OUT1[27]), .A1(n2145), .B0(IF_PC_INC[27]), .B1(n1225),
.Y(n1235) );
AOI22XL U3206 ( .A0(ID_PC[27]), .A1(n1226), .B0(ID_PC_SUM[27]), .B1(n1227),
.Y(n1234) );
XOR2XL U3207 ( .A(PORT_PC[27]), .B(\add_502/carry[27] ), .Y(IF_PC_INC[27])
);
NAND2XL U3208 ( .A(n1236), .B(n1237), .Y(N756) );
AOI22XL U3209 ( .A0(RF_OUT1[26]), .A1(n2145), .B0(IF_PC_INC[26]), .B1(n1225),
.Y(n1237) );
AOI22XL U3210 ( .A0(ID_PC[26]), .A1(n1226), .B0(ID_PC_SUM[26]), .B1(n1227),
.Y(n1236) );
XOR2XL U3211 ( .A(PORT_PC[26]), .B(\add_502/carry[26] ), .Y(IF_PC_INC[26])
);
NAND2XL U3212 ( .A(n1238), .B(n1239), .Y(N755) );
AOI22XL U3213 ( .A0(RF_OUT1[25]), .A1(n1643), .B0(IF_PC_INC[25]), .B1(n2144),
.Y(n1239) );
AOI22XL U3214 ( .A0(RF_ADD_RD1[4]), .A1(n1226), .B0(ID_PC_SUM[25]), .B1(
n1227), .Y(n1238) );
XOR2XL U3215 ( .A(PORT_PC[25]), .B(\add_502/carry[25] ), .Y(IF_PC_INC[25])
);
NAND2XL U3216 ( .A(n1222), .B(n1223), .Y(N761) );
AOI22XL U3217 ( .A0(RF_OUT1[31]), .A1(n2145), .B0(IF_PC_INC[31]), .B1(n1225),
.Y(n1223) );
AOI22XL U3218 ( .A0(ID_PC[31]), .A1(n2143), .B0(ID_PC_SUM[31]), .B1(n1227),
.Y(n1222) );
XOR2XL U3219 ( .A(PORT_PC[31]), .B(\add_502/carry[31] ), .Y(IF_PC_INC[31])
);
AND2XL U3220 ( .A(ID_PC[2]), .B(ID_IMM16_SHL2[2]), .Y(\add_545/carry[3] ) );
AOI33XL U3221 ( .A0(n1535), .A1(EX_INSTR[27]), .A2(n1528), .B0(n1548), .B1(
EX_INSTR[1]), .B2(n1534), .Y(n1533) );
OAI31XL U3222 ( .A0(n1554), .A1(EX_INSTR[2]), .A2(n1374), .B0(n1555), .Y(
EX_COMPARATOR_CW[1]) );
NAND2XL U3223 ( .A(n1556), .B(EX_INSTR[0]), .Y(n1554) );
NOR3XL U3224 ( .A(n1549), .B(EX_INSTR[3]), .C(n1550), .Y(n1534) );
OAI21XL U3225 ( .A0(n1523), .A1(n1374), .B0(n1524), .Y(EX_SHIFTER_CW[1]) );
AOI31XL U3226 ( .A0(n1525), .A1(n1374), .A2(n1526), .B0(n1527), .Y(n1524) );
NAND3XL U3227 ( .A(n1528), .B(EX_INSTR[27]), .C(n1399), .Y(n1526) );
AOI33XL U3228 ( .A0(n1527), .A1(EX_INSTR[0]), .A2(n1534), .B0(n1397), .B1(
n1398), .B2(n1535), .Y(n1532) );
NAND3XL U3229 ( .A(EX_INSTR[2]), .B(n1561), .C(n1562), .Y(n1559) );
NOR3XL U3230 ( .A(EX_INSTR[3]), .B(EX_INSTR[5]), .C(EX_INSTR[4]), .Y(n1562)
);
NOR2XL U3231 ( .A(n1374), .B(EX_INSTR[1]), .Y(n1527) );
INVXL U3232 ( .A(EX_INSTR[0]), .Y(n1542) );
NAND2XL U3233 ( .A(n1240), .B(n1241), .Y(N754) );
AOI22XL U3234 ( .A0(RF_OUT1[24]), .A1(n1643), .B0(IF_PC_INC[24]), .B1(n1225),
.Y(n1241) );
AOI22XL U3235 ( .A0(RF_ADD_RD1[3]), .A1(n2143), .B0(ID_PC_SUM[24]), .B1(
n1227), .Y(n1240) );
XOR2XL U3236 ( .A(PORT_PC[24]), .B(\add_502/carry[24] ), .Y(IF_PC_INC[24])
);
NAND2XL U3237 ( .A(n1242), .B(n1243), .Y(N753) );
AOI22XL U3238 ( .A0(RF_OUT1[23]), .A1(n2145), .B0(IF_PC_INC[23]), .B1(n2144),
.Y(n1243) );
AOI22XL U3239 ( .A0(RF_ADD_RD1[2]), .A1(n1226), .B0(ID_PC_SUM[23]), .B1(
n1227), .Y(n1242) );
XOR2XL U3240 ( .A(PORT_PC[23]), .B(\add_502/carry[23] ), .Y(IF_PC_INC[23])
);
NAND2XL U3241 ( .A(n1244), .B(n1245), .Y(N752) );
AOI22XL U3242 ( .A0(RF_OUT1[22]), .A1(n2145), .B0(IF_PC_INC[22]), .B1(n2144),
.Y(n1245) );
AOI22XL U3243 ( .A0(RF_ADD_RD1[1]), .A1(n2143), .B0(ID_PC_SUM[22]), .B1(
n1227), .Y(n1244) );
XOR2XL U3244 ( .A(PORT_PC[22]), .B(\add_502/carry[22] ), .Y(IF_PC_INC[22])
);
NAND2XL U3245 ( .A(n1246), .B(n1247), .Y(N751) );
AOI22XL U3246 ( .A0(RF_OUT1[21]), .A1(n2145), .B0(IF_PC_INC[21]), .B1(n2144),
.Y(n1247) );
AOI22XL U3247 ( .A0(RF_ADD_RD1[0]), .A1(n2143), .B0(ID_PC_SUM[21]), .B1(
n1227), .Y(n1246) );
XOR2XL U3248 ( .A(PORT_PC[21]), .B(\add_502/carry[21] ), .Y(IF_PC_INC[21])
);
NAND2XL U3249 ( .A(n1248), .B(n1249), .Y(N750) );
AOI22XL U3250 ( .A0(RF_OUT1[20]), .A1(n2145), .B0(IF_PC_INC[20]), .B1(n2144),
.Y(n1249) );
AOI22XL U3251 ( .A0(RF_ADD_RD2[4]), .A1(n2143), .B0(ID_PC_SUM[20]), .B1(
n1227), .Y(n1248) );
XOR2XL U3252 ( .A(PORT_PC[20]), .B(\add_502/carry[20] ), .Y(IF_PC_INC[20])
);
NAND2XL U3253 ( .A(n1250), .B(n1251), .Y(N749) );
AOI22XL U3254 ( .A0(RF_OUT1[19]), .A1(n2145), .B0(IF_PC_INC[19]), .B1(n2144),
.Y(n1251) );
AOI22XL U3255 ( .A0(RF_ADD_RD2[3]), .A1(n2143), .B0(ID_PC_SUM[19]), .B1(
n1227), .Y(n1250) );
XOR2XL U3256 ( .A(PORT_PC[19]), .B(\add_502/carry[19] ), .Y(IF_PC_INC[19])
);
NAND2XL U3257 ( .A(n1252), .B(n1253), .Y(N748) );
AOI22XL U3258 ( .A0(RF_OUT1[18]), .A1(n1643), .B0(IF_PC_INC[18]), .B1(n2144),
.Y(n1253) );
AOI22XL U3259 ( .A0(RF_ADD_RD2[2]), .A1(n2143), .B0(ID_PC_SUM[18]), .B1(
n1227), .Y(n1252) );
XOR2XL U3260 ( .A(PORT_PC[18]), .B(\add_502/carry[18] ), .Y(IF_PC_INC[18])
);
NAND2XL U3261 ( .A(n1254), .B(n1255), .Y(N747) );
AOI22XL U3262 ( .A0(RF_OUT1[17]), .A1(n1643), .B0(IF_PC_INC[17]), .B1(n2144),
.Y(n1255) );
AOI22XL U3263 ( .A0(RF_ADD_RD2[1]), .A1(n2143), .B0(ID_PC_SUM[17]), .B1(
n1227), .Y(n1254) );
XOR2XL U3264 ( .A(PORT_PC[17]), .B(\add_502/carry[17] ), .Y(IF_PC_INC[17])
);
NAND2XL U3265 ( .A(n1256), .B(n1257), .Y(N746) );
AOI22XL U3266 ( .A0(RF_OUT1[16]), .A1(n1643), .B0(IF_PC_INC[16]), .B1(n2144),
.Y(n1257) );
AOI22XL U3267 ( .A0(RF_ADD_RD2[0]), .A1(n2143), .B0(ID_PC_SUM[16]), .B1(
n1227), .Y(n1256) );
XOR2XL U3268 ( .A(PORT_PC[16]), .B(\add_502/carry[16] ), .Y(IF_PC_INC[16])
);
NAND2XL U3269 ( .A(n1258), .B(n1259), .Y(N745) );
AOI22XL U3270 ( .A0(RF_OUT1[15]), .A1(n2145), .B0(IF_PC_INC[15]), .B1(n2144),
.Y(n1259) );
AOI22XL U3271 ( .A0(n2106), .A1(n2143), .B0(ID_PC_SUM[15]), .B1(n1227), .Y(
n1258) );
XOR2XL U3272 ( .A(PORT_PC[15]), .B(\add_502/carry[15] ), .Y(IF_PC_INC[15])
);
NAND2XL U3273 ( .A(n1260), .B(n1261), .Y(N744) );
AOI22XL U3274 ( .A0(RF_OUT1[14]), .A1(n1643), .B0(IF_PC_INC[14]), .B1(n2144),
.Y(n1261) );
AOI22XL U3275 ( .A0(ID_IMM16_SHL2[16]), .A1(n2143), .B0(ID_PC_SUM[14]), .B1(
n1227), .Y(n1260) );
XOR2XL U3276 ( .A(PORT_PC[14]), .B(\add_502/carry[14] ), .Y(IF_PC_INC[14])
);
NAND2XL U3277 ( .A(n1262), .B(n1263), .Y(N743) );
AOI22XL U3278 ( .A0(RF_OUT1[13]), .A1(n1643), .B0(IF_PC_INC[13]), .B1(n2144),
.Y(n1263) );
AOI22XL U3279 ( .A0(ID_IMM16_SHL2[15]), .A1(n2143), .B0(ID_PC_SUM[13]), .B1(
n1227), .Y(n1262) );
XOR2XL U3280 ( .A(PORT_PC[13]), .B(\add_502/carry[13] ), .Y(IF_PC_INC[13])
);
NAND2XL U3281 ( .A(n1264), .B(n1265), .Y(N742) );
AOI22XL U3282 ( .A0(RF_OUT1[12]), .A1(n1643), .B0(IF_PC_INC[12]), .B1(n2144),
.Y(n1265) );
AOI22XL U3283 ( .A0(ID_IMM16_SHL2[14]), .A1(n2143), .B0(ID_PC_SUM[12]), .B1(
n1227), .Y(n1264) );
XOR2XL U3284 ( .A(PORT_PC[12]), .B(\add_502/carry[12] ), .Y(IF_PC_INC[12])
);
NAND2XL U3285 ( .A(n1266), .B(n1267), .Y(N741) );
AOI22XL U3286 ( .A0(RF_OUT1[11]), .A1(n1643), .B0(IF_PC_INC[11]), .B1(n2144),
.Y(n1267) );
AOI22XL U3287 ( .A0(ID_IMM16_SHL2[13]), .A1(n2143), .B0(ID_PC_SUM[11]), .B1(
n1227), .Y(n1266) );
XOR2XL U3288 ( .A(PORT_PC[11]), .B(\add_502/carry[11] ), .Y(IF_PC_INC[11])
);
NAND2XL U3289 ( .A(n1268), .B(n1269), .Y(N740) );
AOI22XL U3290 ( .A0(RF_OUT1[10]), .A1(n1643), .B0(IF_PC_INC[10]), .B1(n2144),
.Y(n1269) );
AOI22XL U3291 ( .A0(ID_IMM16_SHL2[12]), .A1(n2143), .B0(ID_PC_SUM[10]), .B1(
n1227), .Y(n1268) );
XOR2XL U3292 ( .A(PORT_PC[10]), .B(\add_502/carry[10] ), .Y(IF_PC_INC[10])
);
AND2XL U3293 ( .A(PORT_PC[2]), .B(PORT_PC[3]), .Y(\add_502/carry[4] ) );
AND2XL U3294 ( .A(\add_502/carry[29] ), .B(PORT_PC[29]), .Y(
\add_502/carry[30] ) );
AND2XL U3295 ( .A(\add_502/carry[28] ), .B(PORT_PC[28]), .Y(
\add_502/carry[29] ) );
AND2XL U3296 ( .A(\add_502/carry[27] ), .B(PORT_PC[27]), .Y(
\add_502/carry[28] ) );
AND2XL U3297 ( .A(\add_502/carry[26] ), .B(PORT_PC[26]), .Y(
\add_502/carry[27] ) );
AND2XL U3298 ( .A(\add_502/carry[25] ), .B(PORT_PC[25]), .Y(
\add_502/carry[26] ) );
AND2XL U3299 ( .A(\add_502/carry[24] ), .B(PORT_PC[24]), .Y(
\add_502/carry[25] ) );
AND2XL U3300 ( .A(\add_502/carry[23] ), .B(PORT_PC[23]), .Y(
\add_502/carry[24] ) );
AND2XL U3301 ( .A(\add_502/carry[22] ), .B(PORT_PC[22]), .Y(
\add_502/carry[23] ) );
AND2XL U3302 ( .A(\add_502/carry[21] ), .B(PORT_PC[21]), .Y(
\add_502/carry[22] ) );
AND2XL U3303 ( .A(\add_502/carry[20] ), .B(PORT_PC[20]), .Y(
\add_502/carry[21] ) );
AND2XL U3304 ( .A(\add_502/carry[19] ), .B(PORT_PC[19]), .Y(
\add_502/carry[20] ) );
AND2XL U3305 ( .A(\add_502/carry[18] ), .B(PORT_PC[18]), .Y(
\add_502/carry[19] ) );
AND2XL U3306 ( .A(\add_502/carry[17] ), .B(PORT_PC[17]), .Y(
\add_502/carry[18] ) );
AND2XL U3307 ( .A(\add_502/carry[16] ), .B(PORT_PC[16]), .Y(
\add_502/carry[17] ) );
AND2XL U3308 ( .A(\add_502/carry[15] ), .B(PORT_PC[15]), .Y(
\add_502/carry[16] ) );
AND2XL U3309 ( .A(\add_502/carry[14] ), .B(PORT_PC[14]), .Y(
\add_502/carry[15] ) );
AND2XL U3310 ( .A(\add_502/carry[13] ), .B(PORT_PC[13]), .Y(
\add_502/carry[14] ) );
AND2XL U3311 ( .A(\add_502/carry[12] ), .B(PORT_PC[12]), .Y(
\add_502/carry[13] ) );
AND2XL U3312 ( .A(\add_502/carry[11] ), .B(PORT_PC[11]), .Y(
\add_502/carry[12] ) );
AND2XL U3313 ( .A(\add_502/carry[10] ), .B(PORT_PC[10]), .Y(
\add_502/carry[11] ) );
AND2XL U3314 ( .A(\add_502/carry[9] ), .B(PORT_PC[9]), .Y(
\add_502/carry[10] ) );
AND2XL U3315 ( .A(\add_502/carry[8] ), .B(PORT_PC[8]), .Y(\add_502/carry[9] ) );
AND2XL U3316 ( .A(\add_502/carry[7] ), .B(PORT_PC[7]), .Y(\add_502/carry[8] ) );
AND2XL U3317 ( .A(\add_502/carry[6] ), .B(PORT_PC[6]), .Y(\add_502/carry[7] ) );
AND2XL U3318 ( .A(\add_502/carry[5] ), .B(PORT_PC[5]), .Y(\add_502/carry[6] ) );
AND2XL U3319 ( .A(\add_502/carry[4] ), .B(PORT_PC[4]), .Y(\add_502/carry[5] ) );
AND2XL U3320 ( .A(\add_502/carry[30] ), .B(PORT_PC[30]), .Y(
\add_502/carry[31] ) );
AOI21XL U3321 ( .A0(ID_INSTR_28), .A1(n1481), .B0(n1520), .Y(n1521) );
NOR3XL U3322 ( .A(n1478), .B(ID_INSTR_28), .C(n1518), .Y(n1358) );
NOR4XL U3323 ( .A(RF_OUT1[27]), .B(RF_OUT1[26]), .C(RF_OUT1[25]), .D(
RF_OUT1[24]), .Y(\zero_instance/n7 ) );
NOR4XL U3324 ( .A(RF_OUT1[23]), .B(RF_OUT1[22]), .C(RF_OUT1[21]), .D(
RF_OUT1[20]), .Y(\zero_instance/n6 ) );
NOR4XL U3325 ( .A(RF_OUT1[9]), .B(RF_OUT1[8]), .C(RF_OUT1[7]), .D(RF_OUT1[6]), .Y(\zero_instance/n10 ) );
NOR4XL U3326 ( .A(RF_OUT1[30]), .B(RF_OUT1[2]), .C(RF_OUT1[29]), .D(
RF_OUT1[28]), .Y(\zero_instance/n8 ) );
NOR4XL U3327 ( .A(RF_OUT1[5]), .B(RF_OUT1[4]), .C(RF_OUT1[3]), .D(
RF_OUT1[31]), .Y(\zero_instance/n9 ) );
NOR2XL U3328 ( .A(n1290), .B(ID_INSTR_26), .Y(n1194) );
NOR2XL U3329 ( .A(ID_INSTR_26), .B(ID_INSTR_28), .Y(n1520) );
NAND4XL U3330 ( .A(\zero_instance/n3 ), .B(\zero_instance/n4 ), .C(
\zero_instance/n5 ), .D(\zero_instance/n6 ), .Y(\zero_instance/n2 ) );
NOR4XL U3331 ( .A(RF_OUT1[12]), .B(RF_OUT1[11]), .C(RF_OUT1[10]), .D(
RF_OUT1[0]), .Y(\zero_instance/n3 ) );
NOR4XL U3332 ( .A(RF_OUT1[16]), .B(RF_OUT1[15]), .C(RF_OUT1[14]), .D(
RF_OUT1[13]), .Y(\zero_instance/n4 ) );
NOR4XL U3333 ( .A(RF_OUT1[1]), .B(RF_OUT1[19]), .C(RF_OUT1[18]), .D(
RF_OUT1[17]), .Y(\zero_instance/n5 ) );
NAND2XL U3334 ( .A(ID_INSTR_31), .B(n1483), .Y(n1196) );
INVXL U3335 ( .A(ID_INSTR_27), .Y(n1484) );
INVXL U3336 ( .A(ID_INSTR_29), .Y(n1481) );
INVXL U3337 ( .A(ID_INSTR_31), .Y(n1488) );
INVXL U3338 ( .A(ID_IMM16_SHL2[9]), .Y(n1205) );
INVXL U3339 ( .A(ID_IMM16_SHL2[11]), .Y(n1204) );
INVXL U3340 ( .A(ID_IMM16_SHL2[10]), .Y(n1203) );
INVXL U3341 ( .A(RF_ADD_RD2[1]), .Y(n1433) );
AND2XL U3342 ( .A(ID_SIGN_EXT_CONTROL), .B(n2106), .Y(\ID_IMM16_EXT[31] ) );
NAND4XL U3343 ( .A(n1498), .B(n1515), .C(N4717), .D(n1292), .Y(
ID_SIGN_EXT_CONTROL) );
OAI211XL U3344 ( .A0(n1519), .A1(n1520), .B0(n1488), .C0(ID_INSTR_29), .Y(
n1515) );
AOI21XL U3345 ( .A0(ID_INSTR_28), .A1(ID_INSTR_27), .B0(n1483), .Y(n1519) );
NAND2XL U3346 ( .A(n1286), .B(n1287), .Y(N731) );
AOI22XL U3347 ( .A0(n2143), .A1(ID_IMM16_SHL2[3]), .B0(ID_PC_SUM[1]), .B1(
n1227), .Y(n1286) );
AOI22XL U3348 ( .A0(RF_OUT1[1]), .A1(n2145), .B0(IF_PC_INC[1]), .B1(n2144),
.Y(n1287) );
NAND2XL U3349 ( .A(n1288), .B(n1289), .Y(N730) );
AOI22XL U3350 ( .A0(ID_IMM16_SHL2[2]), .A1(n2143), .B0(ID_PC_SUM[0]), .B1(
n1227), .Y(n1288) );
AOI22XL U3351 ( .A0(RF_OUT1[0]), .A1(n2145), .B0(IF_PC_INC[0]), .B1(n2144),
.Y(n1289) );
NAND2XL U3352 ( .A(n1270), .B(n1271), .Y(N739) );
AOI22XL U3353 ( .A0(RF_OUT1[9]), .A1(n1643), .B0(IF_PC_INC[9]), .B1(n2144),
.Y(n1271) );
AOI22XL U3354 ( .A0(ID_IMM16_SHL2[11]), .A1(n2143), .B0(ID_PC_SUM[9]), .B1(
n1227), .Y(n1270) );
XOR2XL U3355 ( .A(PORT_PC[9]), .B(\add_502/carry[9] ), .Y(IF_PC_INC[9]) );
NAND2XL U3356 ( .A(n1272), .B(n1273), .Y(N738) );
AOI22XL U3357 ( .A0(ID_IMM16_SHL2[10]), .A1(n2143), .B0(ID_PC_SUM[8]), .B1(
n1227), .Y(n1272) );
AOI22XL U3358 ( .A0(RF_OUT1[8]), .A1(n1643), .B0(IF_PC_INC[8]), .B1(n2144),
.Y(n1273) );
XOR2XL U3359 ( .A(PORT_PC[8]), .B(\add_502/carry[8] ), .Y(IF_PC_INC[8]) );
NAND2XL U3360 ( .A(n1274), .B(n1275), .Y(N737) );
AOI22XL U3361 ( .A0(ID_IMM16_SHL2[9]), .A1(n2143), .B0(ID_PC_SUM[7]), .B1(
n1227), .Y(n1274) );
AOI22XL U3362 ( .A0(RF_OUT1[7]), .A1(n1643), .B0(IF_PC_INC[7]), .B1(n2144),
.Y(n1275) );
XOR2XL U3363 ( .A(PORT_PC[7]), .B(\add_502/carry[7] ), .Y(IF_PC_INC[7]) );
NAND2XL U3364 ( .A(n1276), .B(n1277), .Y(N736) );
AOI22XL U3365 ( .A0(ID_IMM16_SHL2[8]), .A1(n2143), .B0(ID_PC_SUM[6]), .B1(
n1227), .Y(n1276) );
AOI22XL U3366 ( .A0(RF_OUT1[6]), .A1(n2145), .B0(IF_PC_INC[6]), .B1(n2144),
.Y(n1277) );
XOR2XL U3367 ( .A(PORT_PC[6]), .B(\add_502/carry[6] ), .Y(IF_PC_INC[6]) );
NAND2XL U3368 ( .A(n1278), .B(n1279), .Y(N735) );
AOI22XL U3369 ( .A0(ID_IMM16_SHL2[7]), .A1(n2143), .B0(ID_PC_SUM[5]), .B1(
n1227), .Y(n1278) );
AOI22XL U3370 ( .A0(RF_OUT1[5]), .A1(n2145), .B0(IF_PC_INC[5]), .B1(n2144),
.Y(n1279) );
XOR2XL U3371 ( .A(PORT_PC[5]), .B(\add_502/carry[5] ), .Y(IF_PC_INC[5]) );
NAND2XL U3372 ( .A(n1280), .B(n1281), .Y(N734) );
AOI22XL U3373 ( .A0(ID_IMM16_SHL2[6]), .A1(n2143), .B0(ID_PC_SUM[4]), .B1(
n1227), .Y(n1280) );
AOI22XL U3374 ( .A0(RF_OUT1[4]), .A1(n2145), .B0(IF_PC_INC[4]), .B1(n2144),
.Y(n1281) );
XOR2XL U3375 ( .A(PORT_PC[4]), .B(\add_502/carry[4] ), .Y(IF_PC_INC[4]) );
NAND2XL U3376 ( .A(n1282), .B(n1283), .Y(N733) );
AOI22XL U3377 ( .A0(n2143), .A1(ID_IMM16_SHL2[5]), .B0(ID_PC_SUM[3]), .B1(
n1227), .Y(n1282) );
AOI22XL U3378 ( .A0(RF_OUT1[3]), .A1(n2145), .B0(IF_PC_INC[3]), .B1(n2144),
.Y(n1283) );
XOR2XL U3379 ( .A(PORT_PC[3]), .B(PORT_PC[2]), .Y(IF_PC_INC[3]) );
NAND2XL U3380 ( .A(n1284), .B(n1285), .Y(N732) );
AOI22XL U3381 ( .A0(n2143), .A1(ID_IMM16_SHL2[4]), .B0(ID_PC_SUM[2]), .B1(
n1227), .Y(n1284) );
AOI22XL U3382 ( .A0(RF_OUT1[2]), .A1(n2145), .B0(IF_PC_INC[2]), .B1(n2144),
.Y(n1285) );
XOR2XL U3383 ( .A(ID_IMM16_SHL2[2]), .B(ID_PC[2]), .Y(ID_PC_SUM[2]) );
OR4XL U3384 ( .A(n1196), .B(n1484), .C(n1518), .D(ID_INSTR_28), .Y(n1198) );
INVXL U3385 ( .A(RF_ADD_RD2[3]), .Y(n1434) );
INVXL U3386 ( .A(RF_ADD_RD2[0]), .Y(n1432) );
NOR2BXL U3387 ( .AN(RF_ADD_RD2[2]), .B(n1615), .Y(ID_INSTR_AFTER_CU[18]) );
NOR2BXL U3388 ( .AN(RF_ADD_RD2[4]), .B(n1615), .Y(ID_INSTR_AFTER_CU[20]) );
INVXL U3389 ( .A(PORT_PC[2]), .Y(IF_PC_INC[2]) );
NAND2BXL U3390 ( .AN(PORT_INSTR_IRAM[26]), .B(n2151), .Y(N790) );
NAND2BXL U3391 ( .AN(PORT_INSTR_IRAM[30]), .B(n2151), .Y(N794) );
NAND2BXL U3392 ( .AN(PORT_INSTR_IRAM[28]), .B(n2151), .Y(N792) );
AND2XL U3393 ( .A(ID_IMM16_SHL2[5]), .B(n1522), .Y(ID_INSTR_AFTER_CU[3]) );
AND2XL U3394 ( .A(ID_IMM16_SHL2[3]), .B(n1522), .Y(ID_INSTR_AFTER_CU[1]) );
AND2XL U3395 ( .A(ID_IMM16_SHL2[12]), .B(n1522), .Y(ID_INSTR_AFTER_CU[10])
);
AND2XL U3396 ( .A(ID_IMM16_SHL2[8]), .B(n1522), .Y(ID_INSTR_AFTER_CU[6]) );
AND2XL U3397 ( .A(ID_IMM16_SHL2[6]), .B(n1522), .Y(ID_INSTR_AFTER_CU[4]) );
AND2XL U3398 ( .A(ID_IMM16_SHL2[7]), .B(n1522), .Y(ID_INSTR_AFTER_CU[5]) );
AND2XL U3399 ( .A(ID_IMM16_SHL2[4]), .B(n1522), .Y(ID_INSTR_AFTER_CU[2]) );
AND2XL U3400 ( .A(ID_IMM16_SHL2[2]), .B(n1522), .Y(ID_INSTR_AFTER_CU[0]) );
AND2XL U3401 ( .A(ID_IMM16_SHL2[15]), .B(n1522), .Y(ID_INSTR_AFTER_CU[13])
);
AND2XL U3402 ( .A(ID_IMM16_SHL2[14]), .B(n1522), .Y(ID_INSTR_AFTER_CU[12])
);
AND2XL U3403 ( .A(ID_IMM16_SHL2[13]), .B(n1522), .Y(ID_INSTR_AFTER_CU[11])
);
AND2XL U3404 ( .A(ID_IMM16_SHL2[16]), .B(n1522), .Y(ID_INSTR_AFTER_CU[14])
);
AND2XL U3405 ( .A(PORT_INSTR_IRAM[25]), .B(n2151), .Y(N789) );
AND2XL U3406 ( .A(PORT_INSTR_IRAM[16]), .B(n2151), .Y(N780) );
AND2XL U3407 ( .A(PORT_INSTR_IRAM[17]), .B(n2151), .Y(N781) );
AND2XL U3408 ( .A(PORT_INSTR_IRAM[31]), .B(n2151), .Y(N795) );
AND2XL U3409 ( .A(PORT_INSTR_IRAM[27]), .B(n2151), .Y(N791) );
AND2XL U3410 ( .A(PORT_INSTR_IRAM[0]), .B(n2152), .Y(N764) );
AND2XL U3411 ( .A(PORT_INSTR_IRAM[29]), .B(n2151), .Y(N793) );
AND2XL U3412 ( .A(PORT_INSTR_IRAM[20]), .B(n2151), .Y(N784) );
AND2XL U3413 ( .A(PORT_INSTR_IRAM[21]), .B(n2151), .Y(N785) );
AND2XL U3414 ( .A(PORT_INSTR_IRAM[24]), .B(n2151), .Y(N788) );
AND2XL U3415 ( .A(PORT_INSTR_IRAM[19]), .B(n2151), .Y(N783) );
AND2XL U3416 ( .A(PORT_INSTR_IRAM[23]), .B(n2151), .Y(N787) );
AND2XL U3417 ( .A(PORT_INSTR_IRAM[22]), .B(n2151), .Y(N786) );
AND2XL U3418 ( .A(PORT_INSTR_IRAM[18]), .B(n2151), .Y(N782) );
AND2XL U3419 ( .A(PORT_INSTR_IRAM[14]), .B(n2151), .Y(N778) );
AND2XL U3420 ( .A(PORT_INSTR_IRAM[13]), .B(n2151), .Y(N777) );
AND2XL U3421 ( .A(PORT_INSTR_IRAM[12]), .B(n2151), .Y(N776) );
AND2XL U3422 ( .A(PORT_INSTR_IRAM[11]), .B(n2151), .Y(N775) );
AND2XL U3423 ( .A(PORT_INSTR_IRAM[9]), .B(n2152), .Y(N773) );
AND2XL U3424 ( .A(PORT_INSTR_IRAM[8]), .B(n2152), .Y(N772) );
AND2XL U3425 ( .A(PORT_INSTR_IRAM[7]), .B(n2152), .Y(N771) );
AND2XL U3426 ( .A(PORT_INSTR_IRAM[3]), .B(n2152), .Y(N767) );
AND2XL U3427 ( .A(PORT_INSTR_IRAM[1]), .B(n2152), .Y(N765) );
AND2XL U3428 ( .A(PORT_INSTR_IRAM[2]), .B(n2152), .Y(N766) );
AND2XL U3429 ( .A(PORT_INSTR_IRAM[5]), .B(n2152), .Y(N769) );
AND2XL U3430 ( .A(PORT_INSTR_IRAM[4]), .B(n2152), .Y(N768) );
AND2XL U3431 ( .A(PORT_INSTR_IRAM[10]), .B(n2151), .Y(N774) );
AND2XL U3432 ( .A(PORT_INSTR_IRAM[6]), .B(n2152), .Y(N770) );
AND2XL U3433 ( .A(PORT_INSTR_IRAM[15]), .B(n2151), .Y(N779) );
CLKINVX1 U3434 ( .A(RESET), .Y(\ID_EX_IMM16_EXT_REG_instance/n34 ) );
CLKINVX1 U3435 ( .A(RESET), .Y(\ID_EX_REGA_REG_instance/n34 ) );
CLKINVX1 U3436 ( .A(RESET), .Y(\ID_EX_PC_REG_instance/n34 ) );
CLKINVX1 U3437 ( .A(RESET), .Y(\EX_MEM_REGB_REG_instance/n34 ) );
CLKINVX1 U3438 ( .A(RESET), .Y(\EX_MEM_OUT_REG_instance/n34 ) );
CLKINVX1 U3439 ( .A(RESET), .Y(\MEM_WB_ALU_REG_instance/n34 ) );
CLKINVX1 U3440 ( .A(RESET), .Y(\ID_EX_REGB_REG_instance/n34 ) );
CLKINVX1 U3441 ( .A(RESET), .Y(\PC_instance/n33 ) );
INVXL U3442 ( .A(RESET), .Y(\ID_EX_INSTR_REG_instance/n34 ) );
OAI32XL U3443 ( .A0(n1503), .A1(WB_INSTR_28), .A2(n1347), .B0(n1504), .B1(
n1505), .Y(n1468) );
OR3XL U3444 ( .A(WB_INSTR[6]), .B(WB_INSTR[10]), .C(n1514), .Y(n1504) );
NAND3XL U3445 ( .A(n1340), .B(n1348), .C(n1471), .Y(n1503) );
OAI211XL U3446 ( .A0(WB_INSTR[5]), .A1(n1506), .B0(n1507), .C0(n1508), .Y(
n1505) );
OAI33XL U3447 ( .A0(n1448), .A1(n1449), .A2(n1450), .B0(n1441), .B1(n1447),
.B2(n1446), .Y(n1438) );
XOR2XL U3448 ( .A(RF_ADD_RD2[2]), .B(MEM_INSTR[13]), .Y(n1449) );
XOR2XL U3449 ( .A(RF_ADD_RD2[4]), .B(MEM_INSTR[15]), .Y(n1450) );
NAND3XL U3450 ( .A(n1454), .B(n1455), .C(n1456), .Y(n1448) );
OAI221XL U3451 ( .A0(n1478), .A1(n1479), .B0(n1480), .B1(n1481), .C0(n1482),
.Y(n1372) );
INVXL U3452 ( .A(n1195), .Y(n1482) );
AOI32XL U3453 ( .A0(n1196), .A1(n1484), .A2(n1485), .B0(n1486), .B1(n1290),
.Y(n1480) );
OAI21XL U3454 ( .A0(n1484), .A1(n1483), .B0(ID_INSTR_31), .Y(n1486) );
AOI22XL U3455 ( .A0(WB_ALU[15]), .A1(n2118), .B0(WB_DATA_RAM[15]), .B1(n1310), .Y(n1312) );
AOI22XL U3456 ( .A0(WB_ALU[7]), .A1(n2118), .B0(WB_DATA_RAM[7]), .B1(n1310),
.Y(n1328) );
AOI22XL U3457 ( .A0(WB_ALU[8]), .A1(n2118), .B0(WB_DATA_RAM[8]), .B1(n1310),
.Y(n1326) );
AOI22XL U3458 ( .A0(WB_ALU[9]), .A1(n2118), .B0(WB_DATA_RAM[9]), .B1(n1310),
.Y(n1324) );
AOI22XL U3459 ( .A0(WB_ALU[10]), .A1(n2118), .B0(WB_DATA_RAM[10]), .B1(n1310), .Y(n1322) );
AOI22XL U3460 ( .A0(WB_ALU[11]), .A1(n2118), .B0(WB_DATA_RAM[11]), .B1(n1310), .Y(n1320) );
AOI22XL U3461 ( .A0(WB_ALU[12]), .A1(n2118), .B0(WB_DATA_RAM[12]), .B1(n1310), .Y(n1318) );
AOI22XL U3462 ( .A0(WB_ALU[13]), .A1(n2118), .B0(WB_DATA_RAM[13]), .B1(n1310), .Y(n1316) );
AOI22XL U3463 ( .A0(WB_ALU[14]), .A1(n2118), .B0(WB_DATA_RAM[14]), .B1(n1310), .Y(n1314) );
OAI31XL U3464 ( .A0(n1391), .A1(n1392), .A2(n1393), .B0(n1360), .Y(n1369) );
XOR2XL U3465 ( .A(RF_ADD_RD2[2]), .B(EX_INSTR[18]), .Y(n1392) );
XOR2XL U3466 ( .A(RF_ADD_RD2[4]), .B(EX_INSTR[20]), .Y(n1393) );
NAND3XL U3467 ( .A(n1394), .B(n1395), .C(n1396), .Y(n1391) );
OAI211XL U3468 ( .A0(EX_INSTR[31]), .A1(n1400), .B0(n1377), .C0(n1374), .Y(
n1361) );
NOR3XL U3469 ( .A(n1347), .B(WB_INSTR_31), .C(n1349), .Y(n1339) );
NOR4XL U3470 ( .A(n1445), .B(n1220), .C(MEM_INSTR[27]), .D(MEM_INSTR[29]),
.Y(n1214) );
XNOR2XL U3471 ( .A(EX_INSTR[17]), .B(RF_ADD_RD2[1]), .Y(n1396) );
XNOR2XL U3472 ( .A(MEM_INSTR[12]), .B(RF_ADD_RD2[1]), .Y(n1456) );
XNOR2XL U3473 ( .A(EX_INSTR[16]), .B(RF_ADD_RD2[0]), .Y(n1395) );
XNOR2XL U3474 ( .A(MEM_INSTR[11]), .B(RF_ADD_RD2[0]), .Y(n1455) );
XNOR2XL U3475 ( .A(EX_INSTR[19]), .B(RF_ADD_RD2[3]), .Y(n1394) );
XNOR2XL U3476 ( .A(MEM_INSTR[14]), .B(RF_ADD_RD2[3]), .Y(n1454) );
XNOR2XL U3477 ( .A(EX_INSTR[11]), .B(n1384), .Y(n1378) );
XNOR2XL U3478 ( .A(MEM_INSTR[11]), .B(n1384), .Y(n1446) );
XNOR2XL U3479 ( .A(n1407), .B(EX_INSTR[20]), .Y(n1406) );
XNOR2XL U3480 ( .A(n1427), .B(MEM_INSTR[18]), .Y(n1425) );
XNOR2XL U3481 ( .A(n1408), .B(EX_INSTR[19]), .Y(n1404) );
XNOR2XL U3482 ( .A(n1433), .B(MEM_INSTR[17]), .Y(n1429) );
NOR2XL U3483 ( .A(n1409), .B(MEM_INSTR[30]), .Y(n1215) );
AOI211XL U3484 ( .A0(WB_INSTR[0]), .A1(n1512), .B0(n1513), .C0(WB_INSTR[3]),
.Y(n1506) );
INVXL U3485 ( .A(WB_INSTR[2]), .Y(n1513) );
OAI31XL U3486 ( .A0(n1464), .A1(WB_INSTR_30), .A2(WB_INSTR_29), .B0(n1341),
.Y(n1463) );
AOI22XL U3487 ( .A0(n1466), .A1(WB_INSTR_26), .B0(n1467), .B1(WB_INSTR_31),
.Y(n1464) );
OAI21XL U3488 ( .A0(WB_INSTR_30), .A1(n1338), .B0(WB_SIGN_EXT_16_CONTROL),
.Y(n1211) );
OAI21XL U3489 ( .A0(n1445), .A1(n1219), .B0(n1213), .Y(n1444) );
NOR4XL U3490 ( .A(n1428), .B(n1429), .C(n1430), .D(n1431), .Y(n1414) );
XOR2XL U3491 ( .A(RF_ADD_RD2[2]), .B(MEM_INSTR[18]), .Y(n1430) );
XNOR2XL U3492 ( .A(n1432), .B(MEM_INSTR[16]), .Y(n1431) );
XNOR2XL U3493 ( .A(n1434), .B(MEM_INSTR[19]), .Y(n1428) );
NOR4XL U3494 ( .A(n1423), .B(n1424), .C(n1425), .D(n1426), .Y(n1415) );
XOR2XL U3495 ( .A(RF_ADD_RD1[1]), .B(MEM_INSTR[17]), .Y(n1424) );
XNOR2XL U3496 ( .A(n1384), .B(MEM_INSTR[16]), .Y(n1426) );
XNOR2XL U3497 ( .A(n1408), .B(MEM_INSTR[19]), .Y(n1423) );
NOR4XL U3498 ( .A(n1417), .B(n1418), .C(n1419), .D(n1420), .Y(n1416) );
NAND2XL U3499 ( .A(n1421), .B(n1422), .Y(n1418) );
XNOR2XL U3500 ( .A(n1407), .B(MEM_INSTR[20]), .Y(n1420) );
OAI2B2XL U3501 ( .A1N(n1467), .A0(WB_INSTR_26), .B0(WB_INSTR_29), .B1(n1349),
.Y(n1469) );
NOR2XL U3502 ( .A(WB_INSTR_29), .B(WB_INSTR_27), .Y(n1343) );
AOI32XL U3503 ( .A0(WB_INSTR[1]), .A1(n1509), .A2(WB_INSTR[2]), .B0(
WB_INSTR[4]), .B1(n1510), .Y(n1508) );
NAND2XL U3504 ( .A(WB_INSTR[3]), .B(n1511), .Y(n1510) );
AO21XL U3505 ( .A0(WB_INSTR[0]), .A1(WB_INSTR[5]), .B0(WB_INSTR[3]), .Y(
n1509) );
OAI2BB1XL U3506 ( .A0N(WB_INSTR[0]), .A1N(WB_INSTR[2]), .B0(n1512), .Y(n1511) );
AOI32XL U3507 ( .A0(n1214), .A1(n1409), .A2(MEM_INSTR[30]), .B0(n1410), .B1(
n1411), .Y(N4710) );
AOI32XL U3508 ( .A0(n1412), .A1(n1413), .A2(n1414), .B0(n1415), .B1(n1416),
.Y(n1411) );
AOI32XL U3509 ( .A0(n1190), .A1(n1438), .A2(n1435), .B0(n1439), .B1(n1440),
.Y(n1410) );
AOI2BB1XL U3510 ( .A0N(n1190), .A1N(n1370), .B0(n1437), .Y(n1412) );
NOR3XL U3511 ( .A(MEM_INSTR[29]), .B(MEM_INSTR[31]), .C(MEM_INSTR[30]), .Y(
n1436) );
NOR3BXL U3512 ( .AN(n1217), .B(n1212), .C(MEM_INSTR[29]), .Y(PORT_R_W) );
XNOR2XL U3513 ( .A(n1218), .B(n1219), .Y(n1217) );
NAND2XL U3514 ( .A(MEM_INSTR[26]), .B(n1220), .Y(n1218) );
OAI211XL U3515 ( .A0(WB_INSTR_31), .A1(n1459), .B0(n1460), .C0(n1461), .Y(
RF_WR) );
AOI31XL U3516 ( .A0(WB_INSTR_29), .A1(n1462), .A2(WB_INSTR_30), .B0(n1463),
.Y(n1461) );
INVXL U3517 ( .A(n1468), .Y(n1460) );
AOI211XL U3518 ( .A0(WB_INSTR_30), .A1(n1469), .B0(n1466), .C0(n1470), .Y(
n1459) );
AO22XL U3519 ( .A0(WB_ALU[0]), .A1(n2118), .B0(WB_DATA_RAM[0]), .B1(n1310),
.Y(WB_DATA_EXT_8[0]) );
AO22XL U3520 ( .A0(WB_ALU[1]), .A1(n2118), .B0(WB_DATA_RAM[1]), .B1(n1310),
.Y(WB_DATA_EXT_8[1]) );
AO22XL U3521 ( .A0(WB_ALU[2]), .A1(n2118), .B0(WB_DATA_RAM[2]), .B1(n1310),
.Y(WB_DATA_EXT_8[2]) );
AO22XL U3522 ( .A0(WB_ALU[3]), .A1(n2118), .B0(WB_DATA_RAM[3]), .B1(n1310),
.Y(WB_DATA_EXT_8[3]) );
AO22XL U3523 ( .A0(WB_ALU[4]), .A1(n2118), .B0(WB_DATA_RAM[4]), .B1(n1310),
.Y(WB_DATA_EXT_8[4]) );
AO22XL U3524 ( .A0(WB_ALU[5]), .A1(n2118), .B0(WB_DATA_RAM[5]), .B1(n1310),
.Y(WB_DATA_EXT_8[5]) );
AO22XL U3525 ( .A0(WB_ALU[6]), .A1(n2118), .B0(WB_DATA_RAM[6]), .B1(n1310),
.Y(WB_DATA_EXT_8[6]) );
AND4XL U3526 ( .A(WB_INSTR_29), .B(WB_INSTR_28), .C(n1339), .D(n1340), .Y(
n1819) );
AOI211XL U3527 ( .A0(MEM_INSTR[29]), .A1(MEM_INSTR[28]), .B0(n1212), .C0(
n1213), .Y(PORT_SIZE[1]) );
NAND3XL U3528 ( .A(WB_INSTR_31), .B(n1343), .C(n1465), .Y(n1341) );
NOR3XL U3529 ( .A(WB_INSTR_26), .B(WB_INSTR_30), .C(WB_INSTR_28), .Y(n1465)
);
OAI2B11XL U3530 ( .A1N(WB_DATA_RAM[16]), .A0(n1207), .B0(n1208), .C0(n1308),
.Y(N6259) );
AOI22XL U3531 ( .A0(WB_ALU[16]), .A1(n1614), .B0(WB_DATA_EXT_16[16]), .B1(
n2146), .Y(n1308) );
OAI21XL U3532 ( .A0(WB_SIGN_EXT_16_CONTROL), .A1(
\WB_SIGN_EXT_16_instance/n34 ), .B0(\WB_SIGN_EXT_16_instance/n27 ),
.Y(WB_DATA_EXT_16[16]) );
OAI2B11XL U3533 ( .A1N(WB_DATA_RAM[17]), .A0(n1207), .B0(n1208), .C0(n1307),
.Y(N6260) );
AOI22XL U3534 ( .A0(WB_ALU[17]), .A1(n1614), .B0(WB_DATA_EXT_16[17]), .B1(
n2146), .Y(n1307) );
OAI21XL U3535 ( .A0(WB_SIGN_EXT_16_CONTROL), .A1(
\WB_SIGN_EXT_16_instance/n33 ), .B0(n2107), .Y(WB_DATA_EXT_16[17]) );
OAI2B11XL U3536 ( .A1N(WB_DATA_RAM[18]), .A0(n1207), .B0(n1208), .C0(n1306),
.Y(N6261) );
AOI22XL U3537 ( .A0(WB_ALU[18]), .A1(n1614), .B0(WB_DATA_EXT_16[18]), .B1(
n2146), .Y(n1306) );
OAI21XL U3538 ( .A0(WB_SIGN_EXT_16_CONTROL), .A1(
\WB_SIGN_EXT_16_instance/n28 ), .B0(\WB_SIGN_EXT_16_instance/n27 ),
.Y(WB_DATA_EXT_16[18]) );
OAI2B11XL U3539 ( .A1N(WB_DATA_RAM[19]), .A0(n1207), .B0(n2147), .C0(n1305),
.Y(N6262) );
AOI22XL U3540 ( .A0(WB_ALU[19]), .A1(n1614), .B0(WB_DATA_EXT_16[19]), .B1(
n2146), .Y(n1305) );
OAI21XL U3541 ( .A0(WB_SIGN_EXT_16_CONTROL), .A1(
\WB_SIGN_EXT_16_instance/n25 ), .B0(n2107), .Y(WB_DATA_EXT_16[19]) );
OAI2B11XL U3542 ( .A1N(WB_DATA_RAM[20]), .A0(n1207), .B0(n2147), .C0(n1304),
.Y(N6263) );
AOI22XL U3543 ( .A0(WB_ALU[20]), .A1(n1614), .B0(WB_DATA_EXT_16[20]), .B1(
n2146), .Y(n1304) );
OAI21XL U3544 ( .A0(WB_SIGN_EXT_16_CONTROL), .A1(
\WB_SIGN_EXT_16_instance/n24 ), .B0(\WB_SIGN_EXT_16_instance/n27 ),
.Y(WB_DATA_EXT_16[20]) );
OAI2B11XL U3545 ( .A1N(WB_DATA_RAM[21]), .A0(n1207), .B0(n2147), .C0(n1303),
.Y(N6264) );
AOI22XL U3546 ( .A0(WB_ALU[21]), .A1(n1614), .B0(WB_DATA_EXT_16[21]), .B1(
n2146), .Y(n1303) );
OAI21XL U3547 ( .A0(WB_SIGN_EXT_16_CONTROL), .A1(
\WB_SIGN_EXT_16_instance/n23 ), .B0(n2107), .Y(WB_DATA_EXT_16[21]) );
OAI2B11XL U3548 ( .A1N(WB_DATA_RAM[22]), .A0(n1207), .B0(n2147), .C0(n1302),
.Y(N6265) );
AOI22XL U3549 ( .A0(WB_ALU[22]), .A1(n1614), .B0(WB_DATA_EXT_16[22]), .B1(
n1211), .Y(n1302) );
OAI21XL U3550 ( .A0(WB_SIGN_EXT_16_CONTROL), .A1(
\WB_SIGN_EXT_16_instance/n22 ), .B0(\WB_SIGN_EXT_16_instance/n27 ),
.Y(WB_DATA_EXT_16[22]) );
OAI2B11XL U3551 ( .A1N(WB_DATA_RAM[23]), .A0(n1207), .B0(n2147), .C0(n1301),
.Y(N6266) );
AOI22XL U3552 ( .A0(WB_ALU[23]), .A1(n1614), .B0(WB_DATA_EXT_16[23]), .B1(
n1211), .Y(n1301) );
OAI21XL U3553 ( .A0(WB_SIGN_EXT_16_CONTROL), .A1(n1328), .B0(n2107), .Y(
WB_DATA_EXT_16[23]) );
OAI2B11XL U3554 ( .A1N(WB_DATA_RAM[24]), .A0(n1207), .B0(n2147), .C0(n1300),
.Y(N6267) );
AOI22XL U3555 ( .A0(WB_ALU[24]), .A1(n1614), .B0(WB_DATA_EXT_16[24]), .B1(
n1211), .Y(n1300) );
OAI21XL U3556 ( .A0(WB_SIGN_EXT_16_CONTROL), .A1(n1326), .B0(
\WB_SIGN_EXT_16_instance/n27 ), .Y(WB_DATA_EXT_16[24]) );
OAI2B11XL U3557 ( .A1N(WB_DATA_RAM[25]), .A0(n1207), .B0(n2147), .C0(n1299),
.Y(N6268) );
AOI22XL U3558 ( .A0(WB_ALU[25]), .A1(n1614), .B0(WB_DATA_EXT_16[25]), .B1(
n1211), .Y(n1299) );
OAI21XL U3559 ( .A0(WB_SIGN_EXT_16_CONTROL), .A1(n1324), .B0(n2107), .Y(
WB_DATA_EXT_16[25]) );
OAI2B11XL U3560 ( .A1N(WB_DATA_RAM[26]), .A0(n1207), .B0(n2147), .C0(n1298),
.Y(N6269) );
AOI22XL U3561 ( .A0(WB_ALU[26]), .A1(n1614), .B0(WB_DATA_EXT_16[26]), .B1(
n1211), .Y(n1298) );
OAI21XL U3562 ( .A0(WB_SIGN_EXT_16_CONTROL), .A1(n1322), .B0(
\WB_SIGN_EXT_16_instance/n27 ), .Y(WB_DATA_EXT_16[26]) );
OAI2B11XL U3563 ( .A1N(WB_DATA_RAM[27]), .A0(n1207), .B0(n2147), .C0(n1297),
.Y(N6270) );
AOI22XL U3564 ( .A0(WB_ALU[27]), .A1(n1614), .B0(WB_DATA_EXT_16[27]), .B1(
n1211), .Y(n1297) );
OAI21XL U3565 ( .A0(WB_SIGN_EXT_16_CONTROL), .A1(n1320), .B0(n2107), .Y(
WB_DATA_EXT_16[27]) );
OAI2B11XL U3566 ( .A1N(WB_DATA_RAM[28]), .A0(n1207), .B0(n2147), .C0(n1296),
.Y(N6271) );
AOI22XL U3567 ( .A0(WB_ALU[28]), .A1(n1614), .B0(WB_DATA_EXT_16[28]), .B1(
n1211), .Y(n1296) );
OAI21XL U3568 ( .A0(WB_SIGN_EXT_16_CONTROL), .A1(n1318), .B0(
\WB_SIGN_EXT_16_instance/n27 ), .Y(WB_DATA_EXT_16[28]) );
OAI2B11XL U3569 ( .A1N(WB_DATA_RAM[29]), .A0(n1207), .B0(n2147), .C0(n1295),
.Y(N6272) );
AOI22XL U3570 ( .A0(WB_ALU[29]), .A1(n1614), .B0(WB_DATA_EXT_16[29]), .B1(
n1211), .Y(n1295) );
OAI21XL U3571 ( .A0(WB_SIGN_EXT_16_CONTROL), .A1(n1316), .B0(n2107), .Y(
WB_DATA_EXT_16[29]) );
OAI2B11XL U3572 ( .A1N(WB_DATA_RAM[30]), .A0(n1207), .B0(n2147), .C0(n1294),
.Y(N6273) );
AOI22XL U3573 ( .A0(WB_ALU[30]), .A1(n1614), .B0(WB_DATA_EXT_16[30]), .B1(
n1211), .Y(n1294) );
OAI21XL U3574 ( .A0(WB_SIGN_EXT_16_CONTROL), .A1(n1314), .B0(n2107), .Y(
WB_DATA_EXT_16[30]) );
OAI2B11XL U3575 ( .A1N(WB_DATA_RAM[31]), .A0(n1207), .B0(n2147), .C0(n1209),
.Y(RF_DATAIN[31]) );
AOI22XL U3576 ( .A0(WB_ALU[31]), .A1(n1614), .B0(WB_DATA_EXT_16[31]), .B1(
n1211), .Y(n1209) );
NOR2XL U3577 ( .A(n1349), .B(WB_INSTR_28), .Y(n1466) );
OAI2BB1XL U3578 ( .A0N(WB_INSTR[17]), .A1N(n1493), .B0(n1497), .Y(
RF_ADD_WR[1]) );
AOI21XL U3579 ( .A0(WB_INSTR[12]), .A1(n1468), .B0(n1495), .Y(n1497) );
OAI2BB1XL U3580 ( .A0N(WB_INSTR[18]), .A1N(n1493), .B0(n1496), .Y(
RF_ADD_WR[2]) );
AOI21XL U3581 ( .A0(WB_INSTR[13]), .A1(n1468), .B0(n1495), .Y(n1496) );
OAI2BB1XL U3582 ( .A0N(WB_INSTR[20]), .A1N(n1493), .B0(n1494), .Y(
RF_ADD_WR[4]) );
AOI21XL U3583 ( .A0(WB_INSTR[15]), .A1(n1468), .B0(n1495), .Y(n1494) );
NAND3BXL U3584 ( .AN(n1498), .B(n1499), .C(n1500), .Y(n1489) );
XNOR2XL U3585 ( .A(RF_ADD_RD2[0]), .B(RF_ADD_WR[0]), .Y(n1499) );
XNOR2XL U3586 ( .A(RF_ADD_RD2[3]), .B(RF_ADD_WR[3]), .Y(n1500) );
INVXL U3587 ( .A(WB_INSTR_28), .Y(n1344) );
INVXL U3588 ( .A(n1380), .Y(n1376) );
OAI33XL U3589 ( .A0(n1381), .A1(n1382), .A2(n1383), .B0(n1373), .B1(n1379),
.B2(n1378), .Y(n1380) );
XOR2XL U3590 ( .A(RF_ADD_RD2[2]), .B(EX_INSTR[13]), .Y(n1382) );
XOR2XL U3591 ( .A(RF_ADD_RD2[4]), .B(EX_INSTR[15]), .Y(n1383) );
NOR2XL U3592 ( .A(n1344), .B(WB_INSTR_27), .Y(n1467) );
NAND2XL U3593 ( .A(n1200), .B(n1201), .Y(n1191) );
NOR4XL U3594 ( .A(n1206), .B(N4717), .C(ID_IMM16_SHL2[12]), .D(
ID_IMM16_SHL2[2]), .Y(n1200) );
NOR4XL U3595 ( .A(n1202), .B(ID_IMM16_SHL2[6]), .C(ID_IMM16_SHL2[8]), .D(
ID_IMM16_SHL2[7]), .Y(n1201) );
NAND3XL U3596 ( .A(ID_IMM16_SHL2[4]), .B(ID_IMM16_SHL2[3]), .C(
ID_IMM16_SHL2[5]), .Y(n1206) );
OAI2BB1XL U3597 ( .A0N(WB_INSTR[16]), .A1N(n1493), .B0(n1502), .Y(
RF_ADD_WR[0]) );
AOI21XL U3598 ( .A0(WB_INSTR[11]), .A1(n1468), .B0(n1495), .Y(n1502) );
OAI2BB1XL U3599 ( .A0N(WB_INSTR[19]), .A1N(n1493), .B0(n1501), .Y(
RF_ADD_WR[3]) );
AOI21XL U3600 ( .A0(WB_INSTR[14]), .A1(n1468), .B0(n1495), .Y(n1501) );
INVXL U3601 ( .A(WB_INSTR_27), .Y(n1349) );
AOI21XL U3602 ( .A0(WB_INSTR_30), .A1(WB_INSTR_27), .B0(n1471), .Y(n1470) );
NAND3XL U3603 ( .A(n1401), .B(n1402), .C(n1403), .Y(n1360) );
NOR3XL U3604 ( .A(n1404), .B(n1405), .C(n1406), .Y(n1403) );
XNOR2XL U3605 ( .A(EX_INSTR[16]), .B(RF_ADD_RD1[0]), .Y(n1401) );
XNOR2XL U3606 ( .A(EX_INSTR[18]), .B(RF_ADD_RD1[2]), .Y(n1402) );
NAND3XL U3607 ( .A(n1385), .B(n1386), .C(n1387), .Y(n1373) );
XNOR2XL U3608 ( .A(EX_INSTR[14]), .B(RF_ADD_RD1[3]), .Y(n1385) );
XNOR2XL U3609 ( .A(EX_INSTR[15]), .B(RF_ADD_RD1[4]), .Y(n1386) );
XNOR2XL U3610 ( .A(EX_INSTR[13]), .B(RF_ADD_RD1[2]), .Y(n1387) );
NAND3XL U3611 ( .A(n1451), .B(n1452), .C(n1453), .Y(n1441) );
XNOR2XL U3612 ( .A(MEM_INSTR[15]), .B(RF_ADD_RD1[4]), .Y(n1451) );
XNOR2XL U3613 ( .A(MEM_INSTR[14]), .B(RF_ADD_RD1[3]), .Y(n1452) );
XNOR2XL U3614 ( .A(MEM_INSTR[13]), .B(RF_ADD_RD1[2]), .Y(n1453) );
NAND3XL U3615 ( .A(n1476), .B(n1421), .C(n1477), .Y(n1472) );
XNOR2XL U3616 ( .A(RF_ADD_RD1[3]), .B(RF_ADD_WR[3]), .Y(n1476) );
XNOR2XL U3617 ( .A(RF_ADD_RD1[0]), .B(RF_ADD_WR[0]), .Y(n1477) );
INVXL U3618 ( .A(WB_INSTR_31), .Y(n1348) );
INVXL U3619 ( .A(WB_INSTR_26), .Y(n1347) );
NAND3XL U3620 ( .A(n1388), .B(n1389), .C(n1390), .Y(n1381) );
XNOR2XL U3621 ( .A(EX_INSTR[14]), .B(RF_ADD_RD2[3]), .Y(n1388) );
XNOR2XL U3622 ( .A(EX_INSTR[11]), .B(RF_ADD_RD2[0]), .Y(n1389) );
XNOR2XL U3623 ( .A(EX_INSTR[12]), .B(RF_ADD_RD2[1]), .Y(n1390) );
AND3XL U3624 ( .A(n1436), .B(MEM_INSTR[27]), .C(n1220), .Y(n1419) );
INVXL U3625 ( .A(MEM_INSTR[27]), .Y(n1219) );
OAI211XL U3626 ( .A0(n1343), .A1(n1344), .B0(n1345), .C0(n1346), .Y(n1342)
);
AOI21XL U3627 ( .A0(WB_INSTR_27), .A1(n1347), .B0(n1348), .Y(n1346) );
AOI31XL U3628 ( .A0(n1349), .A1(n1344), .A2(WB_INSTR_26), .B0(WB_INSTR_30),
.Y(n1345) );
OA21XL U3629 ( .A0(n1457), .A1(n1458), .B0(RF_WR), .Y(N4708) );
NOR4XL U3630 ( .A(n1472), .B(n1473), .C(n1474), .D(n1475), .Y(n1458) );
NOR4XL U3631 ( .A(n1489), .B(n1490), .C(n1491), .D(n1492), .Y(n1457) );
XOR2XL U3632 ( .A(RF_ADD_WR[1]), .B(RF_ADD_RD1[1]), .Y(n1473) );
AND3XL U3633 ( .A(n1487), .B(n1488), .C(n1194), .Y(n1371) );
OAI21XL U3634 ( .A0(ID_INSTR_30), .A1(n1481), .B0(ID_INSTR_27), .Y(n1487) );
XOR2XL U3635 ( .A(EX_INSTR[12]), .B(RF_ADD_RD1[1]), .Y(n1379) );
XOR2XL U3636 ( .A(MEM_INSTR[12]), .B(RF_ADD_RD1[1]), .Y(n1447) );
XOR2XL U3637 ( .A(RF_ADD_WR[2]), .B(RF_ADD_RD2[2]), .Y(n1491) );
XOR2XL U3638 ( .A(RF_ADD_WR[4]), .B(RF_ADD_RD2[4]), .Y(n1492) );
XOR2XL U3639 ( .A(RF_ADD_RD1[1]), .B(EX_INSTR[17]), .Y(n1405) );
AO21XL U3640 ( .A0(WB_INSTR_26), .A1(n1467), .B0(n1466), .Y(n1462) );
NAND3BXL U3641 ( .AN(n1190), .B(n1191), .C(n1192), .Y(RF_RD2) );
AOI22XL U3642 ( .A0(ID_INSTR_29), .A1(n1193), .B0(n1194), .B1(n1195), .Y(
n1192) );
OAI31XL U3643 ( .A0(n1196), .A1(ID_INSTR_27), .A2(n1197), .B0(n1198), .Y(
n1193) );
INVXL U3644 ( .A(RF_ADD_RD1[0]), .Y(n1384) );
INVXL U3645 ( .A(RF_ADD_RD1[2]), .Y(n1427) );
INVXL U3646 ( .A(RF_ADD_RD1[4]), .Y(n1407) );
INVXL U3647 ( .A(RF_ADD_RD1[3]), .Y(n1408) );
XOR2XL U3648 ( .A(RF_ADD_RD2[4]), .B(MEM_INSTR[20]), .Y(n1437) );
OR3XL U3649 ( .A(WB_INSTR[9]), .B(WB_INSTR[8]), .C(WB_INSTR[7]), .Y(n1514)
);
INVXL U3650 ( .A(WB_INSTR[1]), .Y(n1512) );
// Instances modified/inserted by SPC tool
CLKBUFX8 CLOCK__L3_I19 ( .Y (CLOCK__L3_N19),
.A (CLOCK__L2_N2) );
CLKBUFX8 CLOCK__L3_I18 ( .Y (CLOCK__L3_N18),
.A (CLOCK__L2_N2) );
CLKBUFX8 CLOCK__L3_I17 ( .Y (CLOCK__L3_N17),
.A (CLOCK__L2_N2) );
CLKBUFX8 CLOCK__L3_I16 ( .Y (CLOCK__L3_N16),
.A (CLOCK__L2_N2) );
CLKBUFX8 CLOCK__L3_I15 ( .Y (CLOCK__L3_N15),
.A (CLOCK__L2_N2) );
CLKBUFX8 CLOCK__L3_I14 ( .Y (CLOCK__L3_N14),
.A (CLOCK__L2_N2) );
CLKBUFX8 CLOCK__L3_I13 ( .Y (CLOCK__L3_N13),
.A (CLOCK__L2_N2) );
CLKBUFX8 CLOCK__L3_I12 ( .Y (CLOCK__L3_N12),
.A (CLOCK__L2_N1) );
CLKBUFX8 CLOCK__L3_I11 ( .Y (CLOCK__L3_N11),
.A (CLOCK__L2_N1) );
CLKBUFX8 CLOCK__L3_I10 ( .Y (CLOCK__L3_N10),
.A (CLOCK__L2_N1) );
CLKBUFX8 CLOCK__L3_I9 ( .Y (CLOCK__L3_N9),
.A (CLOCK__L2_N1) );
CLKBUFX8 CLOCK__L3_I8 ( .Y (CLOCK__L3_N8),
.A (CLOCK__L2_N1) );
CLKBUFX8 CLOCK__L3_I7 ( .Y (CLOCK__L3_N7),
.A (CLOCK__L2_N1) );
CLKBUFX8 CLOCK__L3_I6 ( .Y (CLOCK__L3_N6),
.A (CLOCK__L2_N0) );
CLKBUFX8 CLOCK__L3_I5 ( .Y (CLOCK__L3_N5),
.A (CLOCK__L2_N0) );
CLKBUFX8 CLOCK__L3_I4 ( .Y (CLOCK__L3_N4),
.A (CLOCK__L2_N0) );
CLKBUFX8 CLOCK__L3_I3 ( .Y (CLOCK__L3_N3),
.A (CLOCK__L2_N0) );
CLKBUFX8 CLOCK__L3_I2 ( .Y (CLOCK__L3_N2),
.A (CLOCK__L2_N0) );
CLKBUFX8 CLOCK__L3_I1 ( .Y (CLOCK__L3_N1),
.A (CLOCK__L2_N0) );
CLKBUFX8 CLOCK__L3_I0 ( .Y (CLOCK__L3_N0),
.A (CLOCK__L2_N0) );
CLKBUFX4 CLOCK__L2_I2 ( .Y (CLOCK__L2_N2),
.A (CLOCK__L1_N1) );
CLKBUFX4 CLOCK__L2_I1 ( .Y (CLOCK__L2_N1),
.A (CLOCK__L1_N1) );
CLKBUFX4 CLOCK__L2_I0 ( .Y (CLOCK__L2_N0),
.A (CLOCK__L1_N0) );
CLKBUFX1 CLOCK__L1_I1 ( .Y (CLOCK__L1_N1),
.A (CLOCK) );
CLKBUFX1 CLOCK__L1_I0 ( .Y (CLOCK__L1_N0),
.A (CLOCK) );
// End of SPC instance modification/insertion
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_ef_e
//
// Generated
// by: wig
// on: Mon Apr 10 13:27:22 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_ef_e.v,v 1.1 2006/04/10 15:42:08 wig Exp $
// $Date: 2006/04/10 15:42:08 $
// $Log: inst_ef_e.v,v $
// Revision 1.1 2006/04/10 15:42:08 wig
// Updated testcase (__TOP__)
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
//
// Generator: mix_0.pl Revision: 1.44 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of inst_ef_e
//
// No user `defines in this module
module inst_ef_e
//
// Generated module inst_ef
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of inst_ef_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A2BB2OI_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__A2BB2OI_PP_BLACKBOX_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a2bb2oi (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A2BB2OI_PP_BLACKBOX_V
|
`include "assert.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 4;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("i64.const.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
reg reset = 0;
wire [63:0] result;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("i64.const_tb.vcd");
$dumpvars(0, cpu_tb);
#12
`assert(result, 42);
`assert(result_empty, 0);
$finish;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Case Western Reserve University
// Engineer: Matt McConnell
//
// Create Date: 20:17:00 09/09/2017
// Project Name: EECS301 Digital Design
// Design Name: Lab #4 Project
// Module Name: FxP_ABS_Function
// Target Devices: Altera Cyclone V
// Tool versions: Quartus v17.0
// Description: Fixed Point Absolute Value Function
//
// Input Data in Fixed Point Two's Complement Format
// Output Data is positive value integer
//
// Dependencies:
//
//////////////////////////////////////////////////////////////////////////////////
module FxP_ABS_Function
#(
parameter DATA_WIDTH = 16
)
(
// Data Signals
input [DATA_WIDTH-1:0] DATA_IN,
output [DATA_WIDTH-1:0] DATA_ABS
);
//
// Two's Complement Absolute Function
//
// If the sign-bit (MSB) is high, then
// DATA_ABS = ~DATA_IN + 1'b1
// Else
// DATA_ABS = DATA_IN
//
assign DATA_ABS = DATA_IN[DATA_WIDTH-1] ? ~DATA_IN + 1'b1 : DATA_IN;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SLEEP_PARGATE_PLV_14_V
`define SKY130_FD_SC_LP__SLEEP_PARGATE_PLV_14_V
/**
* sleep_pargate_plv: ????.
*
* Verilog wrapper for sleep_pargate_plv with size of 14 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sleep_pargate_plv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sleep_pargate_plv_14 (
VIRTPWR,
SLEEP ,
VPWR ,
VPB ,
VNB
);
output VIRTPWR;
input SLEEP ;
input VPWR ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__sleep_pargate_plv base (
.VIRTPWR(VIRTPWR),
.SLEEP(SLEEP),
.VPWR(VPWR),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sleep_pargate_plv_14 (
VIRTPWR,
SLEEP
);
output VIRTPWR;
input SLEEP ;
// Voltage supply signals
supply1 VPWR;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__sleep_pargate_plv base (
.VIRTPWR(VIRTPWR),
.SLEEP(SLEEP)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SLEEP_PARGATE_PLV_14_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFRTN_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__SDFRTN_PP_SYMBOL_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__sdfrtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK_N ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFRTN_PP_SYMBOL_V
|
Require Import List.
Require Import Arith.
Require Import StructTact.StructTactics.
Require Import StructTact.Util.
Require Import InfSeqExt.infseq.
Import ListNotations.
Module Type DynamicSystem.
Parameter addr : Type. (* must be finite, decidable *)
Parameter client_addr : addr -> Prop.
Parameter client_addr_dec : forall a : addr, {client_addr a} + {~ client_addr a}.
Parameter addr_eq_dec : forall x y : addr, {x = y} + {x <> y}.
Parameter payload : Type. (* must be serializable *)
Parameter payload_eq_dec : forall x y : payload, {x = y} + {x <> y}.
Parameter client_payload : payload -> Prop. (* holds for payloads that clients can send *)
Parameter client_payload_dec : forall p : payload, {client_payload p} + {~ client_payload p}.
Parameter data : Type.
Parameter timeout : Type.
Parameter timeout_eq_dec : forall x y : timeout, {x = y} + {x <> y}.
Parameter label : Type.
Parameter label_eq_dec : forall x y : label, {x = y} + {x <> y}.
Parameter start_handler : addr -> list addr -> data * list (addr * payload) * list timeout.
Definition res := (data * list (addr * payload) * list timeout * list timeout)%type.
Parameter recv_handler : addr -> addr -> data -> payload -> res.
Parameter timeout_handler : addr -> data -> timeout -> res.
Parameter recv_handler_l : addr -> addr -> data -> payload -> (res * label).
Parameter timeout_handler_l : addr -> data -> timeout -> (res * label).
Parameter label_input : addr -> addr -> payload -> label.
Parameter label_output : addr -> addr -> payload -> label.
Parameter recv_handler_labeling :
forall src dst st p r,
(recv_handler src dst st p = r ->
exists l,
recv_handler_l src dst st p = (r, l)) /\
(forall l,
recv_handler_l src dst st p = (r, l) ->
recv_handler src dst st p = r).
Parameter timeout_handler_labeling :
forall h st t r,
(timeout_handler h st t = r ->
exists l,
timeout_handler_l h st t = (r, l)) /\
(forall l,
timeout_handler_l h st t = (r, l) ->
timeout_handler h st t = r).
End DynamicSystem.
Module Type ConstrainedDynamicSystem.
Include DynamicSystem.
(* msgs *)
Definition msg : Type := (addr * (addr * payload))%type.
Inductive event : Type :=
| e_send : msg -> event
| e_recv : msg -> event
| e_timeout : addr -> timeout -> event
| e_fail : addr -> event.
Record global_state :=
{ nodes : list addr;
failed_nodes : list addr;
timeouts : addr -> list timeout;
sigma : addr -> option data;
msgs : list msg;
trace : list event
}.
Parameter timeout_constraint : global_state -> addr -> timeout -> Prop.
(* failure_constraint is parametrized over an initial state, the
address of the failing node, and what the state would be after
the failure. *)
Parameter failure_constraint : global_state -> addr -> global_state -> Prop.
Parameter start_constraint : global_state -> addr -> Prop.
End ConstrainedDynamicSystem.
Module DynamicSemantics (S : ConstrainedDynamicSystem).
Include S.
Definition msg_eq_dec :
forall x y : msg, {x = y} + {x <> y}.
Proof.
repeat decide equality;
auto using addr_eq_dec, payload_eq_dec.
Defined.
Definition send (a : addr) (p : addr * payload) : msg :=
(a, p).
Definition update_msgs (gst : global_state) (ms : list msg) : global_state :=
{| nodes := nodes gst;
failed_nodes := failed_nodes gst;
timeouts := timeouts gst;
sigma := sigma gst;
msgs := ms;
trace := trace gst
|}.
Definition fail_node (gst : global_state) (h : addr) : global_state :=
{| nodes := nodes gst;
failed_nodes := h :: failed_nodes gst;
timeouts := timeouts gst;
sigma := sigma gst;
msgs := msgs gst;
trace := trace gst
|}.
Definition apply_handler_result (h : addr) (r : res) (es : list event) (gst : global_state) : global_state :=
let '(st, ms, nts, cts) := r in
let sends := map (send h) ms in
let ts' := nts ++ remove_all timeout_eq_dec cts (timeouts gst h) in
{| nodes := nodes gst;
failed_nodes := failed_nodes gst;
timeouts := update addr_eq_dec (timeouts gst) h ts';
sigma := update addr_eq_dec (sigma gst) h (Some st);
msgs := sends ++ msgs gst;
trace := trace gst ++ es
|}.
Lemma apply_handler_result_nodes :
forall h r e gst,
nodes (apply_handler_result h r e gst) = nodes gst.
Proof using.
unfold apply_handler_result.
intros.
now repeat break_let.
Qed.
Definition update_for_start
(gst : global_state) (h : addr)
(res : data * list (addr * payload) * list timeout) : global_state :=
let '(st, ms, newts) := res in
let sends := map (send h) ms in
{| nodes := h :: nodes gst;
failed_nodes := failed_nodes gst;
timeouts := update addr_eq_dec (timeouts gst) h newts;
sigma := update addr_eq_dec (sigma gst) h (Some st);
msgs := sends ++ msgs gst;
trace := trace gst ++ (map e_send sends)
|}.
Lemma update_for_start_nodes :
forall gst gst' h res,
update_for_start gst h res = gst' ->
h :: nodes gst = nodes gst'.
Proof using.
unfold update_for_start.
intros.
repeat break_let.
now repeat find_reverse_rewrite.
Qed.
Lemma update_for_start_nodes_eq :
forall gst h res,
nodes (update_for_start gst h res) = h :: nodes gst.
Proof using.
unfold update_for_start.
intros.
now repeat break_let.
Qed.
Lemma update_for_start_sigma_h_exists :
forall gst h res,
exists st,
sigma (update_for_start gst h res) h = Some st.
Proof using.
unfold update_for_start.
intros.
repeat break_let.
simpl.
eexists; eauto using update_eq.
Qed.
Lemma update_for_start_sigma_h_n :
forall gst h n res st,
h <> n ->
sigma gst n = Some st ->
sigma (update_for_start gst h res) n = Some st.
Proof using.
unfold update_for_start.
intros.
repeat break_let.
simpl.
now rewrite update_diff.
Qed.
Definition live_with_state (gst : global_state) (h : addr) (st : data) :=
In h (nodes gst) /\
~ In h (failed_nodes gst) /\
sigma gst h = Some st.
Definition update_msgs_and_trace (gst : global_state) (ms : list msg) (e : event) : global_state :=
{| nodes := nodes gst;
failed_nodes := failed_nodes gst;
timeouts := timeouts gst;
sigma := sigma gst;
msgs := ms;
trace := trace gst ++ [e] |}.
Inductive step_dynamic : global_state -> global_state -> Prop :=
| Start :
forall h gst gst' k,
~ In h (nodes gst) ->
~ client_addr h ->
start_constraint gst h ->
(* hypotheses on the list of known nodes *)
In k (nodes gst) ->
~ In k (failed_nodes gst) ->
gst' = update_for_start gst h (start_handler h (k :: nil)) ->
step_dynamic gst gst'
| Fail :
forall h gst gst',
In h (nodes gst) ->
~ In h (failed_nodes gst) ->
gst' = fail_node gst h ->
failure_constraint gst h gst' ->
step_dynamic gst gst'
| Timeout :
forall gst gst' h st t st' ms newts clearedts,
In h (nodes gst) ->
~ In h (failed_nodes gst) ->
sigma gst h = Some st ->
In t (timeouts gst h) ->
timeout_handler h st t = (st', ms, newts, clearedts) ->
gst' = (apply_handler_result
h
(st', ms, newts, t :: clearedts)
[e_timeout h t]
gst) ->
timeout_constraint gst h t ->
step_dynamic gst gst'
| Deliver_node :
forall gst gst' m h d xs ys ms st newts clearedts,
msgs gst = xs ++ m :: ys ->
h = fst (snd m) ->
In h (nodes gst) ->
~ In h (failed_nodes gst) ->
sigma gst h = Some d ->
recv_handler (fst m) h d (snd (snd m)) = (st, ms, newts, clearedts) ->
gst' = apply_handler_result
h
(st, ms, newts, clearedts)
[e_recv m]
(update_msgs gst (xs ++ ys)) ->
step_dynamic gst gst'
| Input :
forall gst gst' h i to m,
client_addr h ->
client_payload i ->
m = send h (to, i) ->
gst' = update_msgs_and_trace gst (m :: msgs gst) (e_send m) ->
step_dynamic gst gst'
| Deliver_client :
forall gst gst' h xs m ys,
client_addr h ->
msgs gst = xs ++ m :: ys ->
h = fst (snd m) ->
gst' = update_msgs_and_trace gst (xs ++ ys) (e_recv m) ->
step_dynamic gst gst'.
Inductive labeled_step_dynamic : global_state -> label -> global_state -> Prop :=
| LTimeout :
forall gst gst' h st t lb st' ms newts clearedts,
In h (nodes gst) ->
~ In h (failed_nodes gst) ->
sigma gst h = Some st ->
In t (timeouts gst h) ->
timeout_handler_l h st t = (st', ms, newts, clearedts, lb) ->
gst' = (apply_handler_result
h
(st', ms, newts, t :: clearedts)
[e_timeout h t]
gst) ->
timeout_constraint gst h t ->
labeled_step_dynamic gst lb gst'
| LDeliver_node :
forall gst gst' m h d xs ys ms lb st newts clearedts,
msgs gst = xs ++ m :: ys ->
h = fst (snd m) ->
In h (nodes gst) ->
~ In h (failed_nodes gst) ->
sigma gst h = Some d ->
recv_handler_l (fst m) h d (snd (snd m)) = (st, ms, newts, clearedts, lb) ->
gst' = apply_handler_result
h
(st, ms, newts, clearedts)
[e_recv m]
(update_msgs gst (xs ++ ys)) ->
labeled_step_dynamic gst lb gst'
| LInput :
forall gst gst' h i to m l,
client_addr h ->
client_payload i ->
m = send h (to, i) ->
l = label_input h to i ->
gst' = update_msgs_and_trace gst (m :: msgs gst) (e_send m) ->
labeled_step_dynamic gst l gst'
| LDeliver_client :
forall gst gst' h xs m ys l,
client_addr h ->
msgs gst = xs ++ m :: ys ->
h = fst (snd m) ->
l = label_output (fst m) h (snd (snd m)) ->
gst' = update_msgs_and_trace gst (xs ++ ys) (e_recv m) ->
labeled_step_dynamic gst l gst'.
Record occurrence := { occ_gst : global_state ; occ_label : label }.
Definition enabled (l : label) (gst : global_state) : Prop :=
exists gst', labeled_step_dynamic gst l gst'.
Definition l_enabled (l : label) (occ : occurrence) : Prop :=
enabled l (occ_gst occ).
Definition occurred (l : label) (occ :occurrence) : Prop := l = occ_label occ.
Definition inf_enabled (l : label) (s : infseq occurrence) : Prop :=
inf_often (now (l_enabled l)) s.
Definition cont_enabled (l : label) (s : infseq occurrence) : Prop :=
continuously (now (l_enabled l)) s.
Definition inf_occurred (l : label) (s : infseq occurrence) : Prop :=
inf_often (now (occurred l)) s.
Definition strong_local_fairness (s : infseq occurrence) : Prop :=
forall l : label, inf_enabled l s -> inf_occurred l s.
Definition weak_local_fairness (s : infseq occurrence) : Prop :=
forall l : label, cont_enabled l s -> inf_occurred l s.
Lemma strong_local_fairness_invar :
forall e s, strong_local_fairness (Cons e s) -> strong_local_fairness s.
Proof using.
unfold strong_local_fairness. unfold inf_enabled, inf_occurred, inf_often.
intros e s fair a alev.
assert (alevt_es: always (eventually (now (l_enabled a))) (Cons e s)).
constructor.
constructor 2. destruct alev; assumption.
simpl. assumption.
clear alev. generalize (fair a alevt_es); clear fair alevt_es.
intro fair; case (always_Cons fair); trivial.
Qed.
Lemma weak_local_fairness_invar :
forall e s, weak_local_fairness (Cons e s) -> weak_local_fairness s.
Proof using.
unfold weak_local_fairness. unfold cont_enabled, inf_occurred, continuously, inf_often.
intros e s fair l eval.
assert (eval_es: eventually (always (now (l_enabled l))) (Cons e s)).
apply E_next. assumption.
apply fair in eval_es.
apply always_invar in eval_es.
assumption.
Qed.
Lemma strong_local_fairness_weak :
forall s, strong_local_fairness s -> weak_local_fairness s.
Proof using.
intros [e s].
unfold strong_local_fairness, weak_local_fairness, inf_enabled, cont_enabled.
intros H_str l H_cont.
apply H_str.
apply continuously_inf_often.
assumption.
Qed.
CoInductive lb_execution : infseq occurrence -> Prop :=
Cons_lb_exec : forall (o o' : occurrence) (s : infseq occurrence),
labeled_step_dynamic (occ_gst o) (occ_label o) (occ_gst o') ->
lb_execution (Cons o' s) ->
lb_execution (Cons o (Cons o' s)).
Lemma lb_execution_invar :
forall x s, lb_execution (Cons x s) -> lb_execution s.
Proof using.
intros x s e. change (lb_execution (tl (Cons x s))).
destruct e; simpl. assumption.
Qed.
Lemma labeled_step_is_unlabeled_step :
forall gst l gst',
labeled_step_dynamic gst l gst' ->
step_dynamic gst gst'.
Proof using.
intuition.
match goal with
| H: labeled_step_dynamic _ _ _ |- _ =>
invc H
end.
- find_apply_lem_hyp timeout_handler_labeling.
eapply Timeout; eauto.
- find_apply_lem_hyp recv_handler_labeling.
eapply Deliver_node; eauto.
- eapply Input; eauto.
- eapply Deliver_client; eauto.
Qed.
Inductive churn_between (gst gst' : global_state) : Prop :=
| fail_churn : failed_nodes gst <> failed_nodes gst' -> churn_between gst gst'
| join_churn : nodes gst <> nodes gst' -> churn_between gst gst'.
Ltac invc_lstep :=
match goal with
| H: labeled_step_dynamic _ _ _ |- _ =>
invc H
end.
Lemma labeled_step_dynamic_preserves_nodes :
forall gst l gst',
labeled_step_dynamic gst l gst' ->
nodes gst = nodes gst'.
Proof.
intros.
inv_prop labeled_step_dynamic;
simpl; reflexivity.
Qed.
Lemma labeled_step_dynamic_preserves_failed_nodes :
forall gst l gst',
labeled_step_dynamic gst l gst' ->
failed_nodes gst = failed_nodes gst'.
Proof.
intros.
inv_prop labeled_step_dynamic;
simpl; reflexivity.
Qed.
Lemma labeled_step_dynamic_is_step_dynamic_without_churn :
forall gst gst',
step_dynamic gst gst' ->
((exists l, labeled_step_dynamic gst l gst') /\ ~ churn_between gst gst') \/
((~ exists l, labeled_step_dynamic gst l gst') /\ churn_between gst gst').
Proof using.
intuition.
match goal with
| H: step_dynamic _ _ |- _ =>
invc H
end.
- right.
split.
* intuition.
break_exists.
invc_lstep;
find_apply_lem_hyp update_for_start_nodes;
try find_rewrite_lem apply_handler_result_nodes;
eapply list_neq_cons; eauto.
* apply join_churn.
rewrite update_for_start_nodes_eq.
eauto using list_neq_cons.
- right.
unfold fail_node.
split.
* intuition.
break_exists.
invc_lstep;
unfold apply_handler_result, update_msgs_and_trace in *;
find_inversion;
eapply list_neq_cons; eauto.
* eauto using fail_churn, list_neq_cons.
- left.
split.
* find_apply_lem_hyp timeout_handler_labeling.
break_exists_exists.
eauto using LTimeout.
* intuition.
match goal with
| H: churn_between _ _ |- _ =>
inversion H; eauto
end.
- left.
split.
* find_apply_lem_hyp recv_handler_labeling.
break_exists_exists.
eauto using LDeliver_node.
* intuition.
match goal with
| H: churn_between _ _ |- _ =>
inversion H; eauto
end.
- left. split.
+ eauto using labeled_step_dynamic.
+ intuition.
match goal with
| H: churn_between _ _ |- _ =>
inversion H; eauto
end.
- left. split.
+ eauto using labeled_step_dynamic.
+ intuition.
match goal with
| H: churn_between _ _ |- _ =>
inversion H; eauto
end.
Qed.
Ltac break_step :=
match goal with
| [ H : step_dynamic _ _ |- _ ] =>
induction H
end; subst.
(* Predicates on global states *)
Definition gpred : Type := global_state -> Prop.
Definition gpred_and (P Q : global_state -> Prop) (gst : global_state) : Prop :=
P gst /\ Q gst.
Definition lift_gpred_to_occ (P : global_state -> Prop) (o : occurrence) : Prop :=
P (occ_gst o).
Definition lift_gpred_to_ex (P : global_state -> Prop) : infseq.infseq occurrence -> Prop :=
infseq.now (lift_gpred_to_occ P).
End DynamicSemantics.
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Mon Sep 18 12:32:27 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode funcsim
// C:/Projects/srio_test/srio_test/srio_test.srcs/sources_1/ip/vio_0/vio_0_sim_netlist.v
// Design : vio_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "vio_0,vio,{}" *) (* X_CORE_INFO = "vio,Vivado 2016.3" *)
(* NotValidForBitStream *)
module vio_0
(clk,
probe_in0,
probe_in1,
probe_in2,
probe_in3);
input clk;
input [0:0]probe_in0;
input [0:0]probe_in1;
input [0:0]probe_in2;
input [0:0]probe_in3;
wire clk;
wire [0:0]probe_in0;
wire [0:0]probe_in1;
wire [0:0]probe_in2;
wire [0:0]probe_in3;
wire [0:0]NLW_inst_probe_out0_UNCONNECTED;
wire [0:0]NLW_inst_probe_out1_UNCONNECTED;
wire [0:0]NLW_inst_probe_out10_UNCONNECTED;
wire [0:0]NLW_inst_probe_out100_UNCONNECTED;
wire [0:0]NLW_inst_probe_out101_UNCONNECTED;
wire [0:0]NLW_inst_probe_out102_UNCONNECTED;
wire [0:0]NLW_inst_probe_out103_UNCONNECTED;
wire [0:0]NLW_inst_probe_out104_UNCONNECTED;
wire [0:0]NLW_inst_probe_out105_UNCONNECTED;
wire [0:0]NLW_inst_probe_out106_UNCONNECTED;
wire [0:0]NLW_inst_probe_out107_UNCONNECTED;
wire [0:0]NLW_inst_probe_out108_UNCONNECTED;
wire [0:0]NLW_inst_probe_out109_UNCONNECTED;
wire [0:0]NLW_inst_probe_out11_UNCONNECTED;
wire [0:0]NLW_inst_probe_out110_UNCONNECTED;
wire [0:0]NLW_inst_probe_out111_UNCONNECTED;
wire [0:0]NLW_inst_probe_out112_UNCONNECTED;
wire [0:0]NLW_inst_probe_out113_UNCONNECTED;
wire [0:0]NLW_inst_probe_out114_UNCONNECTED;
wire [0:0]NLW_inst_probe_out115_UNCONNECTED;
wire [0:0]NLW_inst_probe_out116_UNCONNECTED;
wire [0:0]NLW_inst_probe_out117_UNCONNECTED;
wire [0:0]NLW_inst_probe_out118_UNCONNECTED;
wire [0:0]NLW_inst_probe_out119_UNCONNECTED;
wire [0:0]NLW_inst_probe_out12_UNCONNECTED;
wire [0:0]NLW_inst_probe_out120_UNCONNECTED;
wire [0:0]NLW_inst_probe_out121_UNCONNECTED;
wire [0:0]NLW_inst_probe_out122_UNCONNECTED;
wire [0:0]NLW_inst_probe_out123_UNCONNECTED;
wire [0:0]NLW_inst_probe_out124_UNCONNECTED;
wire [0:0]NLW_inst_probe_out125_UNCONNECTED;
wire [0:0]NLW_inst_probe_out126_UNCONNECTED;
wire [0:0]NLW_inst_probe_out127_UNCONNECTED;
wire [0:0]NLW_inst_probe_out128_UNCONNECTED;
wire [0:0]NLW_inst_probe_out129_UNCONNECTED;
wire [0:0]NLW_inst_probe_out13_UNCONNECTED;
wire [0:0]NLW_inst_probe_out130_UNCONNECTED;
wire [0:0]NLW_inst_probe_out131_UNCONNECTED;
wire [0:0]NLW_inst_probe_out132_UNCONNECTED;
wire [0:0]NLW_inst_probe_out133_UNCONNECTED;
wire [0:0]NLW_inst_probe_out134_UNCONNECTED;
wire [0:0]NLW_inst_probe_out135_UNCONNECTED;
wire [0:0]NLW_inst_probe_out136_UNCONNECTED;
wire [0:0]NLW_inst_probe_out137_UNCONNECTED;
wire [0:0]NLW_inst_probe_out138_UNCONNECTED;
wire [0:0]NLW_inst_probe_out139_UNCONNECTED;
wire [0:0]NLW_inst_probe_out14_UNCONNECTED;
wire [0:0]NLW_inst_probe_out140_UNCONNECTED;
wire [0:0]NLW_inst_probe_out141_UNCONNECTED;
wire [0:0]NLW_inst_probe_out142_UNCONNECTED;
wire [0:0]NLW_inst_probe_out143_UNCONNECTED;
wire [0:0]NLW_inst_probe_out144_UNCONNECTED;
wire [0:0]NLW_inst_probe_out145_UNCONNECTED;
wire [0:0]NLW_inst_probe_out146_UNCONNECTED;
wire [0:0]NLW_inst_probe_out147_UNCONNECTED;
wire [0:0]NLW_inst_probe_out148_UNCONNECTED;
wire [0:0]NLW_inst_probe_out149_UNCONNECTED;
wire [0:0]NLW_inst_probe_out15_UNCONNECTED;
wire [0:0]NLW_inst_probe_out150_UNCONNECTED;
wire [0:0]NLW_inst_probe_out151_UNCONNECTED;
wire [0:0]NLW_inst_probe_out152_UNCONNECTED;
wire [0:0]NLW_inst_probe_out153_UNCONNECTED;
wire [0:0]NLW_inst_probe_out154_UNCONNECTED;
wire [0:0]NLW_inst_probe_out155_UNCONNECTED;
wire [0:0]NLW_inst_probe_out156_UNCONNECTED;
wire [0:0]NLW_inst_probe_out157_UNCONNECTED;
wire [0:0]NLW_inst_probe_out158_UNCONNECTED;
wire [0:0]NLW_inst_probe_out159_UNCONNECTED;
wire [0:0]NLW_inst_probe_out16_UNCONNECTED;
wire [0:0]NLW_inst_probe_out160_UNCONNECTED;
wire [0:0]NLW_inst_probe_out161_UNCONNECTED;
wire [0:0]NLW_inst_probe_out162_UNCONNECTED;
wire [0:0]NLW_inst_probe_out163_UNCONNECTED;
wire [0:0]NLW_inst_probe_out164_UNCONNECTED;
wire [0:0]NLW_inst_probe_out165_UNCONNECTED;
wire [0:0]NLW_inst_probe_out166_UNCONNECTED;
wire [0:0]NLW_inst_probe_out167_UNCONNECTED;
wire [0:0]NLW_inst_probe_out168_UNCONNECTED;
wire [0:0]NLW_inst_probe_out169_UNCONNECTED;
wire [0:0]NLW_inst_probe_out17_UNCONNECTED;
wire [0:0]NLW_inst_probe_out170_UNCONNECTED;
wire [0:0]NLW_inst_probe_out171_UNCONNECTED;
wire [0:0]NLW_inst_probe_out172_UNCONNECTED;
wire [0:0]NLW_inst_probe_out173_UNCONNECTED;
wire [0:0]NLW_inst_probe_out174_UNCONNECTED;
wire [0:0]NLW_inst_probe_out175_UNCONNECTED;
wire [0:0]NLW_inst_probe_out176_UNCONNECTED;
wire [0:0]NLW_inst_probe_out177_UNCONNECTED;
wire [0:0]NLW_inst_probe_out178_UNCONNECTED;
wire [0:0]NLW_inst_probe_out179_UNCONNECTED;
wire [0:0]NLW_inst_probe_out18_UNCONNECTED;
wire [0:0]NLW_inst_probe_out180_UNCONNECTED;
wire [0:0]NLW_inst_probe_out181_UNCONNECTED;
wire [0:0]NLW_inst_probe_out182_UNCONNECTED;
wire [0:0]NLW_inst_probe_out183_UNCONNECTED;
wire [0:0]NLW_inst_probe_out184_UNCONNECTED;
wire [0:0]NLW_inst_probe_out185_UNCONNECTED;
wire [0:0]NLW_inst_probe_out186_UNCONNECTED;
wire [0:0]NLW_inst_probe_out187_UNCONNECTED;
wire [0:0]NLW_inst_probe_out188_UNCONNECTED;
wire [0:0]NLW_inst_probe_out189_UNCONNECTED;
wire [0:0]NLW_inst_probe_out19_UNCONNECTED;
wire [0:0]NLW_inst_probe_out190_UNCONNECTED;
wire [0:0]NLW_inst_probe_out191_UNCONNECTED;
wire [0:0]NLW_inst_probe_out192_UNCONNECTED;
wire [0:0]NLW_inst_probe_out193_UNCONNECTED;
wire [0:0]NLW_inst_probe_out194_UNCONNECTED;
wire [0:0]NLW_inst_probe_out195_UNCONNECTED;
wire [0:0]NLW_inst_probe_out196_UNCONNECTED;
wire [0:0]NLW_inst_probe_out197_UNCONNECTED;
wire [0:0]NLW_inst_probe_out198_UNCONNECTED;
wire [0:0]NLW_inst_probe_out199_UNCONNECTED;
wire [0:0]NLW_inst_probe_out2_UNCONNECTED;
wire [0:0]NLW_inst_probe_out20_UNCONNECTED;
wire [0:0]NLW_inst_probe_out200_UNCONNECTED;
wire [0:0]NLW_inst_probe_out201_UNCONNECTED;
wire [0:0]NLW_inst_probe_out202_UNCONNECTED;
wire [0:0]NLW_inst_probe_out203_UNCONNECTED;
wire [0:0]NLW_inst_probe_out204_UNCONNECTED;
wire [0:0]NLW_inst_probe_out205_UNCONNECTED;
wire [0:0]NLW_inst_probe_out206_UNCONNECTED;
wire [0:0]NLW_inst_probe_out207_UNCONNECTED;
wire [0:0]NLW_inst_probe_out208_UNCONNECTED;
wire [0:0]NLW_inst_probe_out209_UNCONNECTED;
wire [0:0]NLW_inst_probe_out21_UNCONNECTED;
wire [0:0]NLW_inst_probe_out210_UNCONNECTED;
wire [0:0]NLW_inst_probe_out211_UNCONNECTED;
wire [0:0]NLW_inst_probe_out212_UNCONNECTED;
wire [0:0]NLW_inst_probe_out213_UNCONNECTED;
wire [0:0]NLW_inst_probe_out214_UNCONNECTED;
wire [0:0]NLW_inst_probe_out215_UNCONNECTED;
wire [0:0]NLW_inst_probe_out216_UNCONNECTED;
wire [0:0]NLW_inst_probe_out217_UNCONNECTED;
wire [0:0]NLW_inst_probe_out218_UNCONNECTED;
wire [0:0]NLW_inst_probe_out219_UNCONNECTED;
wire [0:0]NLW_inst_probe_out22_UNCONNECTED;
wire [0:0]NLW_inst_probe_out220_UNCONNECTED;
wire [0:0]NLW_inst_probe_out221_UNCONNECTED;
wire [0:0]NLW_inst_probe_out222_UNCONNECTED;
wire [0:0]NLW_inst_probe_out223_UNCONNECTED;
wire [0:0]NLW_inst_probe_out224_UNCONNECTED;
wire [0:0]NLW_inst_probe_out225_UNCONNECTED;
wire [0:0]NLW_inst_probe_out226_UNCONNECTED;
wire [0:0]NLW_inst_probe_out227_UNCONNECTED;
wire [0:0]NLW_inst_probe_out228_UNCONNECTED;
wire [0:0]NLW_inst_probe_out229_UNCONNECTED;
wire [0:0]NLW_inst_probe_out23_UNCONNECTED;
wire [0:0]NLW_inst_probe_out230_UNCONNECTED;
wire [0:0]NLW_inst_probe_out231_UNCONNECTED;
wire [0:0]NLW_inst_probe_out232_UNCONNECTED;
wire [0:0]NLW_inst_probe_out233_UNCONNECTED;
wire [0:0]NLW_inst_probe_out234_UNCONNECTED;
wire [0:0]NLW_inst_probe_out235_UNCONNECTED;
wire [0:0]NLW_inst_probe_out236_UNCONNECTED;
wire [0:0]NLW_inst_probe_out237_UNCONNECTED;
wire [0:0]NLW_inst_probe_out238_UNCONNECTED;
wire [0:0]NLW_inst_probe_out239_UNCONNECTED;
wire [0:0]NLW_inst_probe_out24_UNCONNECTED;
wire [0:0]NLW_inst_probe_out240_UNCONNECTED;
wire [0:0]NLW_inst_probe_out241_UNCONNECTED;
wire [0:0]NLW_inst_probe_out242_UNCONNECTED;
wire [0:0]NLW_inst_probe_out243_UNCONNECTED;
wire [0:0]NLW_inst_probe_out244_UNCONNECTED;
wire [0:0]NLW_inst_probe_out245_UNCONNECTED;
wire [0:0]NLW_inst_probe_out246_UNCONNECTED;
wire [0:0]NLW_inst_probe_out247_UNCONNECTED;
wire [0:0]NLW_inst_probe_out248_UNCONNECTED;
wire [0:0]NLW_inst_probe_out249_UNCONNECTED;
wire [0:0]NLW_inst_probe_out25_UNCONNECTED;
wire [0:0]NLW_inst_probe_out250_UNCONNECTED;
wire [0:0]NLW_inst_probe_out251_UNCONNECTED;
wire [0:0]NLW_inst_probe_out252_UNCONNECTED;
wire [0:0]NLW_inst_probe_out253_UNCONNECTED;
wire [0:0]NLW_inst_probe_out254_UNCONNECTED;
wire [0:0]NLW_inst_probe_out255_UNCONNECTED;
wire [0:0]NLW_inst_probe_out26_UNCONNECTED;
wire [0:0]NLW_inst_probe_out27_UNCONNECTED;
wire [0:0]NLW_inst_probe_out28_UNCONNECTED;
wire [0:0]NLW_inst_probe_out29_UNCONNECTED;
wire [0:0]NLW_inst_probe_out3_UNCONNECTED;
wire [0:0]NLW_inst_probe_out30_UNCONNECTED;
wire [0:0]NLW_inst_probe_out31_UNCONNECTED;
wire [0:0]NLW_inst_probe_out32_UNCONNECTED;
wire [0:0]NLW_inst_probe_out33_UNCONNECTED;
wire [0:0]NLW_inst_probe_out34_UNCONNECTED;
wire [0:0]NLW_inst_probe_out35_UNCONNECTED;
wire [0:0]NLW_inst_probe_out36_UNCONNECTED;
wire [0:0]NLW_inst_probe_out37_UNCONNECTED;
wire [0:0]NLW_inst_probe_out38_UNCONNECTED;
wire [0:0]NLW_inst_probe_out39_UNCONNECTED;
wire [0:0]NLW_inst_probe_out4_UNCONNECTED;
wire [0:0]NLW_inst_probe_out40_UNCONNECTED;
wire [0:0]NLW_inst_probe_out41_UNCONNECTED;
wire [0:0]NLW_inst_probe_out42_UNCONNECTED;
wire [0:0]NLW_inst_probe_out43_UNCONNECTED;
wire [0:0]NLW_inst_probe_out44_UNCONNECTED;
wire [0:0]NLW_inst_probe_out45_UNCONNECTED;
wire [0:0]NLW_inst_probe_out46_UNCONNECTED;
wire [0:0]NLW_inst_probe_out47_UNCONNECTED;
wire [0:0]NLW_inst_probe_out48_UNCONNECTED;
wire [0:0]NLW_inst_probe_out49_UNCONNECTED;
wire [0:0]NLW_inst_probe_out5_UNCONNECTED;
wire [0:0]NLW_inst_probe_out50_UNCONNECTED;
wire [0:0]NLW_inst_probe_out51_UNCONNECTED;
wire [0:0]NLW_inst_probe_out52_UNCONNECTED;
wire [0:0]NLW_inst_probe_out53_UNCONNECTED;
wire [0:0]NLW_inst_probe_out54_UNCONNECTED;
wire [0:0]NLW_inst_probe_out55_UNCONNECTED;
wire [0:0]NLW_inst_probe_out56_UNCONNECTED;
wire [0:0]NLW_inst_probe_out57_UNCONNECTED;
wire [0:0]NLW_inst_probe_out58_UNCONNECTED;
wire [0:0]NLW_inst_probe_out59_UNCONNECTED;
wire [0:0]NLW_inst_probe_out6_UNCONNECTED;
wire [0:0]NLW_inst_probe_out60_UNCONNECTED;
wire [0:0]NLW_inst_probe_out61_UNCONNECTED;
wire [0:0]NLW_inst_probe_out62_UNCONNECTED;
wire [0:0]NLW_inst_probe_out63_UNCONNECTED;
wire [0:0]NLW_inst_probe_out64_UNCONNECTED;
wire [0:0]NLW_inst_probe_out65_UNCONNECTED;
wire [0:0]NLW_inst_probe_out66_UNCONNECTED;
wire [0:0]NLW_inst_probe_out67_UNCONNECTED;
wire [0:0]NLW_inst_probe_out68_UNCONNECTED;
wire [0:0]NLW_inst_probe_out69_UNCONNECTED;
wire [0:0]NLW_inst_probe_out7_UNCONNECTED;
wire [0:0]NLW_inst_probe_out70_UNCONNECTED;
wire [0:0]NLW_inst_probe_out71_UNCONNECTED;
wire [0:0]NLW_inst_probe_out72_UNCONNECTED;
wire [0:0]NLW_inst_probe_out73_UNCONNECTED;
wire [0:0]NLW_inst_probe_out74_UNCONNECTED;
wire [0:0]NLW_inst_probe_out75_UNCONNECTED;
wire [0:0]NLW_inst_probe_out76_UNCONNECTED;
wire [0:0]NLW_inst_probe_out77_UNCONNECTED;
wire [0:0]NLW_inst_probe_out78_UNCONNECTED;
wire [0:0]NLW_inst_probe_out79_UNCONNECTED;
wire [0:0]NLW_inst_probe_out8_UNCONNECTED;
wire [0:0]NLW_inst_probe_out80_UNCONNECTED;
wire [0:0]NLW_inst_probe_out81_UNCONNECTED;
wire [0:0]NLW_inst_probe_out82_UNCONNECTED;
wire [0:0]NLW_inst_probe_out83_UNCONNECTED;
wire [0:0]NLW_inst_probe_out84_UNCONNECTED;
wire [0:0]NLW_inst_probe_out85_UNCONNECTED;
wire [0:0]NLW_inst_probe_out86_UNCONNECTED;
wire [0:0]NLW_inst_probe_out87_UNCONNECTED;
wire [0:0]NLW_inst_probe_out88_UNCONNECTED;
wire [0:0]NLW_inst_probe_out89_UNCONNECTED;
wire [0:0]NLW_inst_probe_out9_UNCONNECTED;
wire [0:0]NLW_inst_probe_out90_UNCONNECTED;
wire [0:0]NLW_inst_probe_out91_UNCONNECTED;
wire [0:0]NLW_inst_probe_out92_UNCONNECTED;
wire [0:0]NLW_inst_probe_out93_UNCONNECTED;
wire [0:0]NLW_inst_probe_out94_UNCONNECTED;
wire [0:0]NLW_inst_probe_out95_UNCONNECTED;
wire [0:0]NLW_inst_probe_out96_UNCONNECTED;
wire [0:0]NLW_inst_probe_out97_UNCONNECTED;
wire [0:0]NLW_inst_probe_out98_UNCONNECTED;
wire [0:0]NLW_inst_probe_out99_UNCONNECTED;
wire [16:0]NLW_inst_sl_oport0_UNCONNECTED;
(* C_BUILD_REVISION = "0" *)
(* C_BUS_ADDR_WIDTH = "17" *)
(* C_BUS_DATA_WIDTH = "16" *)
(* C_CORE_INFO1 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* C_CORE_INFO2 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* C_CORE_MAJOR_VER = "2" *)
(* C_CORE_MINOR_ALPHA_VER = "97" *)
(* C_CORE_MINOR_VER = "0" *)
(* C_CORE_TYPE = "2" *)
(* C_CSE_DRV_VER = "1" *)
(* C_EN_PROBE_IN_ACTIVITY = "1" *)
(* C_EN_SYNCHRONIZATION = "1" *)
(* C_MAJOR_VERSION = "2013" *)
(* C_MAX_NUM_PROBE = "256" *)
(* C_MAX_WIDTH_PER_PROBE = "256" *)
(* C_MINOR_VERSION = "1" *)
(* C_NEXT_SLAVE = "0" *)
(* C_NUM_PROBE_IN = "4" *)
(* C_NUM_PROBE_OUT = "0" *)
(* C_PIPE_IFACE = "0" *)
(* C_PROBE_IN0_WIDTH = "1" *)
(* C_PROBE_IN100_WIDTH = "1" *)
(* C_PROBE_IN101_WIDTH = "1" *)
(* C_PROBE_IN102_WIDTH = "1" *)
(* C_PROBE_IN103_WIDTH = "1" *)
(* C_PROBE_IN104_WIDTH = "1" *)
(* C_PROBE_IN105_WIDTH = "1" *)
(* C_PROBE_IN106_WIDTH = "1" *)
(* C_PROBE_IN107_WIDTH = "1" *)
(* C_PROBE_IN108_WIDTH = "1" *)
(* C_PROBE_IN109_WIDTH = "1" *)
(* C_PROBE_IN10_WIDTH = "1" *)
(* C_PROBE_IN110_WIDTH = "1" *)
(* C_PROBE_IN111_WIDTH = "1" *)
(* C_PROBE_IN112_WIDTH = "1" *)
(* C_PROBE_IN113_WIDTH = "1" *)
(* C_PROBE_IN114_WIDTH = "1" *)
(* C_PROBE_IN115_WIDTH = "1" *)
(* C_PROBE_IN116_WIDTH = "1" *)
(* C_PROBE_IN117_WIDTH = "1" *)
(* C_PROBE_IN118_WIDTH = "1" *)
(* C_PROBE_IN119_WIDTH = "1" *)
(* C_PROBE_IN11_WIDTH = "1" *)
(* C_PROBE_IN120_WIDTH = "1" *)
(* C_PROBE_IN121_WIDTH = "1" *)
(* C_PROBE_IN122_WIDTH = "1" *)
(* C_PROBE_IN123_WIDTH = "1" *)
(* C_PROBE_IN124_WIDTH = "1" *)
(* C_PROBE_IN125_WIDTH = "1" *)
(* C_PROBE_IN126_WIDTH = "1" *)
(* C_PROBE_IN127_WIDTH = "1" *)
(* C_PROBE_IN128_WIDTH = "1" *)
(* C_PROBE_IN129_WIDTH = "1" *)
(* C_PROBE_IN12_WIDTH = "1" *)
(* C_PROBE_IN130_WIDTH = "1" *)
(* C_PROBE_IN131_WIDTH = "1" *)
(* C_PROBE_IN132_WIDTH = "1" *)
(* C_PROBE_IN133_WIDTH = "1" *)
(* C_PROBE_IN134_WIDTH = "1" *)
(* C_PROBE_IN135_WIDTH = "1" *)
(* C_PROBE_IN136_WIDTH = "1" *)
(* C_PROBE_IN137_WIDTH = "1" *)
(* C_PROBE_IN138_WIDTH = "1" *)
(* C_PROBE_IN139_WIDTH = "1" *)
(* C_PROBE_IN13_WIDTH = "1" *)
(* C_PROBE_IN140_WIDTH = "1" *)
(* C_PROBE_IN141_WIDTH = "1" *)
(* C_PROBE_IN142_WIDTH = "1" *)
(* C_PROBE_IN143_WIDTH = "1" *)
(* C_PROBE_IN144_WIDTH = "1" *)
(* C_PROBE_IN145_WIDTH = "1" *)
(* C_PROBE_IN146_WIDTH = "1" *)
(* C_PROBE_IN147_WIDTH = "1" *)
(* C_PROBE_IN148_WIDTH = "1" *)
(* C_PROBE_IN149_WIDTH = "1" *)
(* C_PROBE_IN14_WIDTH = "1" *)
(* C_PROBE_IN150_WIDTH = "1" *)
(* C_PROBE_IN151_WIDTH = "1" *)
(* C_PROBE_IN152_WIDTH = "1" *)
(* C_PROBE_IN153_WIDTH = "1" *)
(* C_PROBE_IN154_WIDTH = "1" *)
(* C_PROBE_IN155_WIDTH = "1" *)
(* C_PROBE_IN156_WIDTH = "1" *)
(* C_PROBE_IN157_WIDTH = "1" *)
(* C_PROBE_IN158_WIDTH = "1" *)
(* C_PROBE_IN159_WIDTH = "1" *)
(* C_PROBE_IN15_WIDTH = "1" *)
(* C_PROBE_IN160_WIDTH = "1" *)
(* C_PROBE_IN161_WIDTH = "1" *)
(* C_PROBE_IN162_WIDTH = "1" *)
(* C_PROBE_IN163_WIDTH = "1" *)
(* C_PROBE_IN164_WIDTH = "1" *)
(* C_PROBE_IN165_WIDTH = "1" *)
(* C_PROBE_IN166_WIDTH = "1" *)
(* C_PROBE_IN167_WIDTH = "1" *)
(* C_PROBE_IN168_WIDTH = "1" *)
(* C_PROBE_IN169_WIDTH = "1" *)
(* C_PROBE_IN16_WIDTH = "1" *)
(* C_PROBE_IN170_WIDTH = "1" *)
(* C_PROBE_IN171_WIDTH = "1" *)
(* C_PROBE_IN172_WIDTH = "1" *)
(* C_PROBE_IN173_WIDTH = "1" *)
(* C_PROBE_IN174_WIDTH = "1" *)
(* C_PROBE_IN175_WIDTH = "1" *)
(* C_PROBE_IN176_WIDTH = "1" *)
(* C_PROBE_IN177_WIDTH = "1" *)
(* C_PROBE_IN178_WIDTH = "1" *)
(* C_PROBE_IN179_WIDTH = "1" *)
(* C_PROBE_IN17_WIDTH = "1" *)
(* C_PROBE_IN180_WIDTH = "1" *)
(* C_PROBE_IN181_WIDTH = "1" *)
(* C_PROBE_IN182_WIDTH = "1" *)
(* C_PROBE_IN183_WIDTH = "1" *)
(* C_PROBE_IN184_WIDTH = "1" *)
(* C_PROBE_IN185_WIDTH = "1" *)
(* C_PROBE_IN186_WIDTH = "1" *)
(* C_PROBE_IN187_WIDTH = "1" *)
(* C_PROBE_IN188_WIDTH = "1" *)
(* C_PROBE_IN189_WIDTH = "1" *)
(* C_PROBE_IN18_WIDTH = "1" *)
(* C_PROBE_IN190_WIDTH = "1" *)
(* C_PROBE_IN191_WIDTH = "1" *)
(* C_PROBE_IN192_WIDTH = "1" *)
(* C_PROBE_IN193_WIDTH = "1" *)
(* C_PROBE_IN194_WIDTH = "1" *)
(* C_PROBE_IN195_WIDTH = "1" *)
(* C_PROBE_IN196_WIDTH = "1" *)
(* C_PROBE_IN197_WIDTH = "1" *)
(* C_PROBE_IN198_WIDTH = "1" *)
(* C_PROBE_IN199_WIDTH = "1" *)
(* C_PROBE_IN19_WIDTH = "1" *)
(* C_PROBE_IN1_WIDTH = "1" *)
(* C_PROBE_IN200_WIDTH = "1" *)
(* C_PROBE_IN201_WIDTH = "1" *)
(* C_PROBE_IN202_WIDTH = "1" *)
(* C_PROBE_IN203_WIDTH = "1" *)
(* C_PROBE_IN204_WIDTH = "1" *)
(* C_PROBE_IN205_WIDTH = "1" *)
(* C_PROBE_IN206_WIDTH = "1" *)
(* C_PROBE_IN207_WIDTH = "1" *)
(* C_PROBE_IN208_WIDTH = "1" *)
(* C_PROBE_IN209_WIDTH = "1" *)
(* C_PROBE_IN20_WIDTH = "1" *)
(* C_PROBE_IN210_WIDTH = "1" *)
(* C_PROBE_IN211_WIDTH = "1" *)
(* C_PROBE_IN212_WIDTH = "1" *)
(* C_PROBE_IN213_WIDTH = "1" *)
(* C_PROBE_IN214_WIDTH = "1" *)
(* C_PROBE_IN215_WIDTH = "1" *)
(* C_PROBE_IN216_WIDTH = "1" *)
(* C_PROBE_IN217_WIDTH = "1" *)
(* C_PROBE_IN218_WIDTH = "1" *)
(* C_PROBE_IN219_WIDTH = "1" *)
(* C_PROBE_IN21_WIDTH = "1" *)
(* C_PROBE_IN220_WIDTH = "1" *)
(* C_PROBE_IN221_WIDTH = "1" *)
(* C_PROBE_IN222_WIDTH = "1" *)
(* C_PROBE_IN223_WIDTH = "1" *)
(* C_PROBE_IN224_WIDTH = "1" *)
(* C_PROBE_IN225_WIDTH = "1" *)
(* C_PROBE_IN226_WIDTH = "1" *)
(* C_PROBE_IN227_WIDTH = "1" *)
(* C_PROBE_IN228_WIDTH = "1" *)
(* C_PROBE_IN229_WIDTH = "1" *)
(* C_PROBE_IN22_WIDTH = "1" *)
(* C_PROBE_IN230_WIDTH = "1" *)
(* C_PROBE_IN231_WIDTH = "1" *)
(* C_PROBE_IN232_WIDTH = "1" *)
(* C_PROBE_IN233_WIDTH = "1" *)
(* C_PROBE_IN234_WIDTH = "1" *)
(* C_PROBE_IN235_WIDTH = "1" *)
(* C_PROBE_IN236_WIDTH = "1" *)
(* C_PROBE_IN237_WIDTH = "1" *)
(* C_PROBE_IN238_WIDTH = "1" *)
(* C_PROBE_IN239_WIDTH = "1" *)
(* C_PROBE_IN23_WIDTH = "1" *)
(* C_PROBE_IN240_WIDTH = "1" *)
(* C_PROBE_IN241_WIDTH = "1" *)
(* C_PROBE_IN242_WIDTH = "1" *)
(* C_PROBE_IN243_WIDTH = "1" *)
(* C_PROBE_IN244_WIDTH = "1" *)
(* C_PROBE_IN245_WIDTH = "1" *)
(* C_PROBE_IN246_WIDTH = "1" *)
(* C_PROBE_IN247_WIDTH = "1" *)
(* C_PROBE_IN248_WIDTH = "1" *)
(* C_PROBE_IN249_WIDTH = "1" *)
(* C_PROBE_IN24_WIDTH = "1" *)
(* C_PROBE_IN250_WIDTH = "1" *)
(* C_PROBE_IN251_WIDTH = "1" *)
(* C_PROBE_IN252_WIDTH = "1" *)
(* C_PROBE_IN253_WIDTH = "1" *)
(* C_PROBE_IN254_WIDTH = "1" *)
(* C_PROBE_IN255_WIDTH = "1" *)
(* C_PROBE_IN25_WIDTH = "1" *)
(* C_PROBE_IN26_WIDTH = "1" *)
(* C_PROBE_IN27_WIDTH = "1" *)
(* C_PROBE_IN28_WIDTH = "1" *)
(* C_PROBE_IN29_WIDTH = "1" *)
(* C_PROBE_IN2_WIDTH = "1" *)
(* C_PROBE_IN30_WIDTH = "1" *)
(* C_PROBE_IN31_WIDTH = "1" *)
(* C_PROBE_IN32_WIDTH = "1" *)
(* C_PROBE_IN33_WIDTH = "1" *)
(* C_PROBE_IN34_WIDTH = "1" *)
(* C_PROBE_IN35_WIDTH = "1" *)
(* C_PROBE_IN36_WIDTH = "1" *)
(* C_PROBE_IN37_WIDTH = "1" *)
(* C_PROBE_IN38_WIDTH = "1" *)
(* C_PROBE_IN39_WIDTH = "1" *)
(* C_PROBE_IN3_WIDTH = "1" *)
(* C_PROBE_IN40_WIDTH = "1" *)
(* C_PROBE_IN41_WIDTH = "1" *)
(* C_PROBE_IN42_WIDTH = "1" *)
(* C_PROBE_IN43_WIDTH = "1" *)
(* C_PROBE_IN44_WIDTH = "1" *)
(* C_PROBE_IN45_WIDTH = "1" *)
(* C_PROBE_IN46_WIDTH = "1" *)
(* C_PROBE_IN47_WIDTH = "1" *)
(* C_PROBE_IN48_WIDTH = "1" *)
(* C_PROBE_IN49_WIDTH = "1" *)
(* C_PROBE_IN4_WIDTH = "1" *)
(* C_PROBE_IN50_WIDTH = "1" *)
(* C_PROBE_IN51_WIDTH = "1" *)
(* C_PROBE_IN52_WIDTH = "1" *)
(* C_PROBE_IN53_WIDTH = "1" *)
(* C_PROBE_IN54_WIDTH = "1" *)
(* C_PROBE_IN55_WIDTH = "1" *)
(* C_PROBE_IN56_WIDTH = "1" *)
(* C_PROBE_IN57_WIDTH = "1" *)
(* C_PROBE_IN58_WIDTH = "1" *)
(* C_PROBE_IN59_WIDTH = "1" *)
(* C_PROBE_IN5_WIDTH = "1" *)
(* C_PROBE_IN60_WIDTH = "1" *)
(* C_PROBE_IN61_WIDTH = "1" *)
(* C_PROBE_IN62_WIDTH = "1" *)
(* C_PROBE_IN63_WIDTH = "1" *)
(* C_PROBE_IN64_WIDTH = "1" *)
(* C_PROBE_IN65_WIDTH = "1" *)
(* C_PROBE_IN66_WIDTH = "1" *)
(* C_PROBE_IN67_WIDTH = "1" *)
(* C_PROBE_IN68_WIDTH = "1" *)
(* C_PROBE_IN69_WIDTH = "1" *)
(* C_PROBE_IN6_WIDTH = "1" *)
(* C_PROBE_IN70_WIDTH = "1" *)
(* C_PROBE_IN71_WIDTH = "1" *)
(* C_PROBE_IN72_WIDTH = "1" *)
(* C_PROBE_IN73_WIDTH = "1" *)
(* C_PROBE_IN74_WIDTH = "1" *)
(* C_PROBE_IN75_WIDTH = "1" *)
(* C_PROBE_IN76_WIDTH = "1" *)
(* C_PROBE_IN77_WIDTH = "1" *)
(* C_PROBE_IN78_WIDTH = "1" *)
(* C_PROBE_IN79_WIDTH = "1" *)
(* C_PROBE_IN7_WIDTH = "1" *)
(* C_PROBE_IN80_WIDTH = "1" *)
(* C_PROBE_IN81_WIDTH = "1" *)
(* C_PROBE_IN82_WIDTH = "1" *)
(* C_PROBE_IN83_WIDTH = "1" *)
(* C_PROBE_IN84_WIDTH = "1" *)
(* C_PROBE_IN85_WIDTH = "1" *)
(* C_PROBE_IN86_WIDTH = "1" *)
(* C_PROBE_IN87_WIDTH = "1" *)
(* C_PROBE_IN88_WIDTH = "1" *)
(* C_PROBE_IN89_WIDTH = "1" *)
(* C_PROBE_IN8_WIDTH = "1" *)
(* C_PROBE_IN90_WIDTH = "1" *)
(* C_PROBE_IN91_WIDTH = "1" *)
(* C_PROBE_IN92_WIDTH = "1" *)
(* C_PROBE_IN93_WIDTH = "1" *)
(* C_PROBE_IN94_WIDTH = "1" *)
(* C_PROBE_IN95_WIDTH = "1" *)
(* C_PROBE_IN96_WIDTH = "1" *)
(* C_PROBE_IN97_WIDTH = "1" *)
(* C_PROBE_IN98_WIDTH = "1" *)
(* C_PROBE_IN99_WIDTH = "1" *)
(* C_PROBE_IN9_WIDTH = "1" *)
(* C_PROBE_OUT0_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT0_WIDTH = "1" *)
(* C_PROBE_OUT100_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT100_WIDTH = "1" *)
(* C_PROBE_OUT101_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT101_WIDTH = "1" *)
(* C_PROBE_OUT102_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT102_WIDTH = "1" *)
(* C_PROBE_OUT103_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT103_WIDTH = "1" *)
(* C_PROBE_OUT104_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT104_WIDTH = "1" *)
(* C_PROBE_OUT105_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT105_WIDTH = "1" *)
(* C_PROBE_OUT106_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT106_WIDTH = "1" *)
(* C_PROBE_OUT107_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT107_WIDTH = "1" *)
(* C_PROBE_OUT108_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT108_WIDTH = "1" *)
(* C_PROBE_OUT109_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT109_WIDTH = "1" *)
(* C_PROBE_OUT10_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT10_WIDTH = "1" *)
(* C_PROBE_OUT110_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT110_WIDTH = "1" *)
(* C_PROBE_OUT111_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT111_WIDTH = "1" *)
(* C_PROBE_OUT112_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT112_WIDTH = "1" *)
(* C_PROBE_OUT113_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT113_WIDTH = "1" *)
(* C_PROBE_OUT114_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT114_WIDTH = "1" *)
(* C_PROBE_OUT115_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT115_WIDTH = "1" *)
(* C_PROBE_OUT116_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT116_WIDTH = "1" *)
(* C_PROBE_OUT117_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT117_WIDTH = "1" *)
(* C_PROBE_OUT118_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT118_WIDTH = "1" *)
(* C_PROBE_OUT119_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT119_WIDTH = "1" *)
(* C_PROBE_OUT11_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT11_WIDTH = "1" *)
(* C_PROBE_OUT120_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT120_WIDTH = "1" *)
(* C_PROBE_OUT121_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT121_WIDTH = "1" *)
(* C_PROBE_OUT122_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT122_WIDTH = "1" *)
(* C_PROBE_OUT123_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT123_WIDTH = "1" *)
(* C_PROBE_OUT124_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT124_WIDTH = "1" *)
(* C_PROBE_OUT125_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT125_WIDTH = "1" *)
(* C_PROBE_OUT126_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT126_WIDTH = "1" *)
(* C_PROBE_OUT127_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT127_WIDTH = "1" *)
(* C_PROBE_OUT128_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT128_WIDTH = "1" *)
(* C_PROBE_OUT129_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT129_WIDTH = "1" *)
(* C_PROBE_OUT12_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT12_WIDTH = "1" *)
(* C_PROBE_OUT130_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT130_WIDTH = "1" *)
(* C_PROBE_OUT131_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT131_WIDTH = "1" *)
(* C_PROBE_OUT132_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT132_WIDTH = "1" *)
(* C_PROBE_OUT133_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT133_WIDTH = "1" *)
(* C_PROBE_OUT134_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT134_WIDTH = "1" *)
(* C_PROBE_OUT135_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT135_WIDTH = "1" *)
(* C_PROBE_OUT136_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT136_WIDTH = "1" *)
(* C_PROBE_OUT137_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT137_WIDTH = "1" *)
(* C_PROBE_OUT138_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT138_WIDTH = "1" *)
(* C_PROBE_OUT139_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT139_WIDTH = "1" *)
(* C_PROBE_OUT13_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT13_WIDTH = "1" *)
(* C_PROBE_OUT140_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT140_WIDTH = "1" *)
(* C_PROBE_OUT141_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT141_WIDTH = "1" *)
(* C_PROBE_OUT142_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT142_WIDTH = "1" *)
(* C_PROBE_OUT143_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT143_WIDTH = "1" *)
(* C_PROBE_OUT144_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT144_WIDTH = "1" *)
(* C_PROBE_OUT145_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT145_WIDTH = "1" *)
(* C_PROBE_OUT146_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT146_WIDTH = "1" *)
(* C_PROBE_OUT147_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT147_WIDTH = "1" *)
(* C_PROBE_OUT148_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT148_WIDTH = "1" *)
(* C_PROBE_OUT149_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT149_WIDTH = "1" *)
(* C_PROBE_OUT14_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT14_WIDTH = "1" *)
(* C_PROBE_OUT150_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT150_WIDTH = "1" *)
(* C_PROBE_OUT151_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT151_WIDTH = "1" *)
(* C_PROBE_OUT152_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT152_WIDTH = "1" *)
(* C_PROBE_OUT153_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT153_WIDTH = "1" *)
(* C_PROBE_OUT154_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT154_WIDTH = "1" *)
(* C_PROBE_OUT155_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT155_WIDTH = "1" *)
(* C_PROBE_OUT156_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT156_WIDTH = "1" *)
(* C_PROBE_OUT157_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT157_WIDTH = "1" *)
(* C_PROBE_OUT158_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT158_WIDTH = "1" *)
(* C_PROBE_OUT159_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT159_WIDTH = "1" *)
(* C_PROBE_OUT15_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT15_WIDTH = "1" *)
(* C_PROBE_OUT160_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT160_WIDTH = "1" *)
(* C_PROBE_OUT161_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT161_WIDTH = "1" *)
(* C_PROBE_OUT162_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT162_WIDTH = "1" *)
(* C_PROBE_OUT163_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT163_WIDTH = "1" *)
(* C_PROBE_OUT164_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT164_WIDTH = "1" *)
(* C_PROBE_OUT165_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT165_WIDTH = "1" *)
(* C_PROBE_OUT166_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT166_WIDTH = "1" *)
(* C_PROBE_OUT167_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT167_WIDTH = "1" *)
(* C_PROBE_OUT168_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT168_WIDTH = "1" *)
(* C_PROBE_OUT169_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT169_WIDTH = "1" *)
(* C_PROBE_OUT16_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT16_WIDTH = "1" *)
(* C_PROBE_OUT170_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT170_WIDTH = "1" *)
(* C_PROBE_OUT171_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT171_WIDTH = "1" *)
(* C_PROBE_OUT172_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT172_WIDTH = "1" *)
(* C_PROBE_OUT173_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT173_WIDTH = "1" *)
(* C_PROBE_OUT174_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT174_WIDTH = "1" *)
(* C_PROBE_OUT175_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT175_WIDTH = "1" *)
(* C_PROBE_OUT176_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT176_WIDTH = "1" *)
(* C_PROBE_OUT177_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT177_WIDTH = "1" *)
(* C_PROBE_OUT178_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT178_WIDTH = "1" *)
(* C_PROBE_OUT179_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT179_WIDTH = "1" *)
(* C_PROBE_OUT17_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT17_WIDTH = "1" *)
(* C_PROBE_OUT180_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT180_WIDTH = "1" *)
(* C_PROBE_OUT181_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT181_WIDTH = "1" *)
(* C_PROBE_OUT182_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT182_WIDTH = "1" *)
(* C_PROBE_OUT183_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT183_WIDTH = "1" *)
(* C_PROBE_OUT184_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT184_WIDTH = "1" *)
(* C_PROBE_OUT185_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT185_WIDTH = "1" *)
(* C_PROBE_OUT186_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT186_WIDTH = "1" *)
(* C_PROBE_OUT187_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT187_WIDTH = "1" *)
(* C_PROBE_OUT188_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT188_WIDTH = "1" *)
(* C_PROBE_OUT189_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT189_WIDTH = "1" *)
(* C_PROBE_OUT18_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT18_WIDTH = "1" *)
(* C_PROBE_OUT190_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT190_WIDTH = "1" *)
(* C_PROBE_OUT191_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT191_WIDTH = "1" *)
(* C_PROBE_OUT192_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT192_WIDTH = "1" *)
(* C_PROBE_OUT193_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT193_WIDTH = "1" *)
(* C_PROBE_OUT194_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT194_WIDTH = "1" *)
(* C_PROBE_OUT195_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT195_WIDTH = "1" *)
(* C_PROBE_OUT196_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT196_WIDTH = "1" *)
(* C_PROBE_OUT197_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT197_WIDTH = "1" *)
(* C_PROBE_OUT198_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT198_WIDTH = "1" *)
(* C_PROBE_OUT199_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT199_WIDTH = "1" *)
(* C_PROBE_OUT19_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT19_WIDTH = "1" *)
(* C_PROBE_OUT1_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT1_WIDTH = "1" *)
(* C_PROBE_OUT200_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT200_WIDTH = "1" *)
(* C_PROBE_OUT201_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT201_WIDTH = "1" *)
(* C_PROBE_OUT202_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT202_WIDTH = "1" *)
(* C_PROBE_OUT203_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT203_WIDTH = "1" *)
(* C_PROBE_OUT204_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT204_WIDTH = "1" *)
(* C_PROBE_OUT205_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT205_WIDTH = "1" *)
(* C_PROBE_OUT206_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT206_WIDTH = "1" *)
(* C_PROBE_OUT207_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT207_WIDTH = "1" *)
(* C_PROBE_OUT208_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT208_WIDTH = "1" *)
(* C_PROBE_OUT209_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT209_WIDTH = "1" *)
(* C_PROBE_OUT20_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT20_WIDTH = "1" *)
(* C_PROBE_OUT210_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT210_WIDTH = "1" *)
(* C_PROBE_OUT211_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT211_WIDTH = "1" *)
(* C_PROBE_OUT212_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT212_WIDTH = "1" *)
(* C_PROBE_OUT213_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT213_WIDTH = "1" *)
(* C_PROBE_OUT214_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT214_WIDTH = "1" *)
(* C_PROBE_OUT215_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT215_WIDTH = "1" *)
(* C_PROBE_OUT216_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT216_WIDTH = "1" *)
(* C_PROBE_OUT217_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT217_WIDTH = "1" *)
(* C_PROBE_OUT218_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT218_WIDTH = "1" *)
(* C_PROBE_OUT219_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT219_WIDTH = "1" *)
(* C_PROBE_OUT21_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT21_WIDTH = "1" *)
(* C_PROBE_OUT220_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT220_WIDTH = "1" *)
(* C_PROBE_OUT221_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT221_WIDTH = "1" *)
(* C_PROBE_OUT222_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT222_WIDTH = "1" *)
(* C_PROBE_OUT223_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT223_WIDTH = "1" *)
(* C_PROBE_OUT224_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT224_WIDTH = "1" *)
(* C_PROBE_OUT225_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT225_WIDTH = "1" *)
(* C_PROBE_OUT226_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT226_WIDTH = "1" *)
(* C_PROBE_OUT227_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT227_WIDTH = "1" *)
(* C_PROBE_OUT228_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT228_WIDTH = "1" *)
(* C_PROBE_OUT229_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT229_WIDTH = "1" *)
(* C_PROBE_OUT22_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT22_WIDTH = "1" *)
(* C_PROBE_OUT230_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT230_WIDTH = "1" *)
(* C_PROBE_OUT231_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT231_WIDTH = "1" *)
(* C_PROBE_OUT232_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT232_WIDTH = "1" *)
(* C_PROBE_OUT233_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT233_WIDTH = "1" *)
(* C_PROBE_OUT234_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT234_WIDTH = "1" *)
(* C_PROBE_OUT235_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT235_WIDTH = "1" *)
(* C_PROBE_OUT236_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT236_WIDTH = "1" *)
(* C_PROBE_OUT237_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT237_WIDTH = "1" *)
(* C_PROBE_OUT238_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT238_WIDTH = "1" *)
(* C_PROBE_OUT239_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT239_WIDTH = "1" *)
(* C_PROBE_OUT23_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT23_WIDTH = "1" *)
(* C_PROBE_OUT240_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT240_WIDTH = "1" *)
(* C_PROBE_OUT241_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT241_WIDTH = "1" *)
(* C_PROBE_OUT242_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT242_WIDTH = "1" *)
(* C_PROBE_OUT243_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT243_WIDTH = "1" *)
(* C_PROBE_OUT244_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT244_WIDTH = "1" *)
(* C_PROBE_OUT245_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT245_WIDTH = "1" *)
(* C_PROBE_OUT246_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT246_WIDTH = "1" *)
(* C_PROBE_OUT247_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT247_WIDTH = "1" *)
(* C_PROBE_OUT248_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT248_WIDTH = "1" *)
(* C_PROBE_OUT249_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT249_WIDTH = "1" *)
(* C_PROBE_OUT24_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT24_WIDTH = "1" *)
(* C_PROBE_OUT250_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT250_WIDTH = "1" *)
(* C_PROBE_OUT251_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT251_WIDTH = "1" *)
(* C_PROBE_OUT252_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT252_WIDTH = "1" *)
(* C_PROBE_OUT253_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT253_WIDTH = "1" *)
(* C_PROBE_OUT254_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT254_WIDTH = "1" *)
(* C_PROBE_OUT255_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT255_WIDTH = "1" *)
(* C_PROBE_OUT25_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT25_WIDTH = "1" *)
(* C_PROBE_OUT26_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT26_WIDTH = "1" *)
(* C_PROBE_OUT27_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT27_WIDTH = "1" *)
(* C_PROBE_OUT28_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT28_WIDTH = "1" *)
(* C_PROBE_OUT29_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT29_WIDTH = "1" *)
(* C_PROBE_OUT2_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT2_WIDTH = "1" *)
(* C_PROBE_OUT30_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT30_WIDTH = "1" *)
(* C_PROBE_OUT31_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT31_WIDTH = "1" *)
(* C_PROBE_OUT32_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT32_WIDTH = "1" *)
(* C_PROBE_OUT33_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT33_WIDTH = "1" *)
(* C_PROBE_OUT34_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT34_WIDTH = "1" *)
(* C_PROBE_OUT35_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT35_WIDTH = "1" *)
(* C_PROBE_OUT36_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT36_WIDTH = "1" *)
(* C_PROBE_OUT37_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT37_WIDTH = "1" *)
(* C_PROBE_OUT38_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT38_WIDTH = "1" *)
(* C_PROBE_OUT39_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT39_WIDTH = "1" *)
(* C_PROBE_OUT3_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT3_WIDTH = "1" *)
(* C_PROBE_OUT40_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT40_WIDTH = "1" *)
(* C_PROBE_OUT41_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT41_WIDTH = "1" *)
(* C_PROBE_OUT42_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT42_WIDTH = "1" *)
(* C_PROBE_OUT43_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT43_WIDTH = "1" *)
(* C_PROBE_OUT44_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT44_WIDTH = "1" *)
(* C_PROBE_OUT45_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT45_WIDTH = "1" *)
(* C_PROBE_OUT46_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT46_WIDTH = "1" *)
(* C_PROBE_OUT47_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT47_WIDTH = "1" *)
(* C_PROBE_OUT48_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT48_WIDTH = "1" *)
(* C_PROBE_OUT49_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT49_WIDTH = "1" *)
(* C_PROBE_OUT4_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT4_WIDTH = "1" *)
(* C_PROBE_OUT50_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT50_WIDTH = "1" *)
(* C_PROBE_OUT51_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT51_WIDTH = "1" *)
(* C_PROBE_OUT52_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT52_WIDTH = "1" *)
(* C_PROBE_OUT53_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT53_WIDTH = "1" *)
(* C_PROBE_OUT54_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT54_WIDTH = "1" *)
(* C_PROBE_OUT55_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT55_WIDTH = "1" *)
(* C_PROBE_OUT56_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT56_WIDTH = "1" *)
(* C_PROBE_OUT57_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT57_WIDTH = "1" *)
(* C_PROBE_OUT58_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT58_WIDTH = "1" *)
(* C_PROBE_OUT59_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT59_WIDTH = "1" *)
(* C_PROBE_OUT5_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT5_WIDTH = "1" *)
(* C_PROBE_OUT60_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT60_WIDTH = "1" *)
(* C_PROBE_OUT61_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT61_WIDTH = "1" *)
(* C_PROBE_OUT62_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT62_WIDTH = "1" *)
(* C_PROBE_OUT63_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT63_WIDTH = "1" *)
(* C_PROBE_OUT64_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT64_WIDTH = "1" *)
(* C_PROBE_OUT65_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT65_WIDTH = "1" *)
(* C_PROBE_OUT66_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT66_WIDTH = "1" *)
(* C_PROBE_OUT67_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT67_WIDTH = "1" *)
(* C_PROBE_OUT68_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT68_WIDTH = "1" *)
(* C_PROBE_OUT69_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT69_WIDTH = "1" *)
(* C_PROBE_OUT6_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT6_WIDTH = "1" *)
(* C_PROBE_OUT70_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT70_WIDTH = "1" *)
(* C_PROBE_OUT71_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT71_WIDTH = "1" *)
(* C_PROBE_OUT72_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT72_WIDTH = "1" *)
(* C_PROBE_OUT73_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT73_WIDTH = "1" *)
(* C_PROBE_OUT74_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT74_WIDTH = "1" *)
(* C_PROBE_OUT75_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT75_WIDTH = "1" *)
(* C_PROBE_OUT76_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT76_WIDTH = "1" *)
(* C_PROBE_OUT77_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT77_WIDTH = "1" *)
(* C_PROBE_OUT78_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT78_WIDTH = "1" *)
(* C_PROBE_OUT79_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT79_WIDTH = "1" *)
(* C_PROBE_OUT7_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT7_WIDTH = "1" *)
(* C_PROBE_OUT80_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT80_WIDTH = "1" *)
(* C_PROBE_OUT81_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT81_WIDTH = "1" *)
(* C_PROBE_OUT82_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT82_WIDTH = "1" *)
(* C_PROBE_OUT83_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT83_WIDTH = "1" *)
(* C_PROBE_OUT84_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT84_WIDTH = "1" *)
(* C_PROBE_OUT85_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT85_WIDTH = "1" *)
(* C_PROBE_OUT86_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT86_WIDTH = "1" *)
(* C_PROBE_OUT87_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT87_WIDTH = "1" *)
(* C_PROBE_OUT88_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT88_WIDTH = "1" *)
(* C_PROBE_OUT89_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT89_WIDTH = "1" *)
(* C_PROBE_OUT8_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT8_WIDTH = "1" *)
(* C_PROBE_OUT90_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT90_WIDTH = "1" *)
(* C_PROBE_OUT91_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT91_WIDTH = "1" *)
(* C_PROBE_OUT92_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT92_WIDTH = "1" *)
(* C_PROBE_OUT93_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT93_WIDTH = "1" *)
(* C_PROBE_OUT94_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT94_WIDTH = "1" *)
(* C_PROBE_OUT95_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT95_WIDTH = "1" *)
(* C_PROBE_OUT96_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT96_WIDTH = "1" *)
(* C_PROBE_OUT97_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT97_WIDTH = "1" *)
(* C_PROBE_OUT98_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT98_WIDTH = "1" *)
(* C_PROBE_OUT99_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT99_WIDTH = "1" *)
(* C_PROBE_OUT9_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT9_WIDTH = "1" *)
(* C_USE_TEST_REG = "1" *)
(* C_XDEVICEFAMILY = "kintex7" *)
(* C_XLNX_HW_PROBE_INFO = "DEFAULT" *)
(* C_XSDB_SLAVE_TYPE = "33" *)
(* DONT_TOUCH *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
(* LC_HIGH_BIT_POS_PROBE_OUT0 = "16'b0000000000000000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT1 = "16'b0000000000000001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT10 = "16'b0000000000001010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT100 = "16'b0000000001100100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT101 = "16'b0000000001100101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT102 = "16'b0000000001100110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT103 = "16'b0000000001100111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT104 = "16'b0000000001101000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT105 = "16'b0000000001101001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT106 = "16'b0000000001101010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT107 = "16'b0000000001101011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT108 = "16'b0000000001101100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT109 = "16'b0000000001101101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT11 = "16'b0000000000001011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT110 = "16'b0000000001101110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT111 = "16'b0000000001101111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT112 = "16'b0000000001110000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT113 = "16'b0000000001110001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT114 = "16'b0000000001110010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT115 = "16'b0000000001110011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT116 = "16'b0000000001110100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT117 = "16'b0000000001110101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT118 = "16'b0000000001110110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT119 = "16'b0000000001110111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT12 = "16'b0000000000001100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT120 = "16'b0000000001111000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT121 = "16'b0000000001111001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT122 = "16'b0000000001111010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT123 = "16'b0000000001111011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT124 = "16'b0000000001111100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT125 = "16'b0000000001111101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT126 = "16'b0000000001111110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT127 = "16'b0000000001111111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT128 = "16'b0000000010000000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT129 = "16'b0000000010000001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT13 = "16'b0000000000001101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT130 = "16'b0000000010000010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT131 = "16'b0000000010000011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT132 = "16'b0000000010000100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT133 = "16'b0000000010000101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT134 = "16'b0000000010000110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT135 = "16'b0000000010000111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT136 = "16'b0000000010001000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT137 = "16'b0000000010001001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT138 = "16'b0000000010001010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT139 = "16'b0000000010001011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT14 = "16'b0000000000001110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT140 = "16'b0000000010001100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT141 = "16'b0000000010001101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT142 = "16'b0000000010001110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT143 = "16'b0000000010001111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT144 = "16'b0000000010010000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT145 = "16'b0000000010010001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT146 = "16'b0000000010010010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT147 = "16'b0000000010010011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT148 = "16'b0000000010010100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT149 = "16'b0000000010010101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT15 = "16'b0000000000001111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT150 = "16'b0000000010010110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT151 = "16'b0000000010010111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT152 = "16'b0000000010011000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT153 = "16'b0000000010011001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT154 = "16'b0000000010011010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT155 = "16'b0000000010011011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT156 = "16'b0000000010011100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT157 = "16'b0000000010011101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT158 = "16'b0000000010011110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT159 = "16'b0000000010011111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT16 = "16'b0000000000010000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT160 = "16'b0000000010100000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT161 = "16'b0000000010100001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT162 = "16'b0000000010100010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT163 = "16'b0000000010100011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT164 = "16'b0000000010100100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT165 = "16'b0000000010100101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT166 = "16'b0000000010100110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT167 = "16'b0000000010100111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT168 = "16'b0000000010101000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT169 = "16'b0000000010101001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT17 = "16'b0000000000010001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT170 = "16'b0000000010101010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT171 = "16'b0000000010101011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT172 = "16'b0000000010101100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT173 = "16'b0000000010101101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT174 = "16'b0000000010101110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT175 = "16'b0000000010101111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT176 = "16'b0000000010110000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT177 = "16'b0000000010110001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT178 = "16'b0000000010110010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT179 = "16'b0000000010110011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT18 = "16'b0000000000010010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT180 = "16'b0000000010110100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT181 = "16'b0000000010110101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT182 = "16'b0000000010110110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT183 = "16'b0000000010110111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT184 = "16'b0000000010111000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT185 = "16'b0000000010111001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT186 = "16'b0000000010111010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT187 = "16'b0000000010111011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT188 = "16'b0000000010111100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT189 = "16'b0000000010111101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT19 = "16'b0000000000010011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT190 = "16'b0000000010111110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT191 = "16'b0000000010111111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT192 = "16'b0000000011000000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT193 = "16'b0000000011000001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT194 = "16'b0000000011000010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT195 = "16'b0000000011000011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT196 = "16'b0000000011000100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT197 = "16'b0000000011000101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT198 = "16'b0000000011000110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT199 = "16'b0000000011000111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT2 = "16'b0000000000000010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT20 = "16'b0000000000010100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT200 = "16'b0000000011001000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT201 = "16'b0000000011001001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT202 = "16'b0000000011001010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT203 = "16'b0000000011001011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT204 = "16'b0000000011001100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT205 = "16'b0000000011001101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT206 = "16'b0000000011001110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT207 = "16'b0000000011001111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT208 = "16'b0000000011010000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT209 = "16'b0000000011010001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT21 = "16'b0000000000010101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT210 = "16'b0000000011010010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT211 = "16'b0000000011010011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT212 = "16'b0000000011010100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT213 = "16'b0000000011010101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT214 = "16'b0000000011010110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT215 = "16'b0000000011010111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT216 = "16'b0000000011011000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT217 = "16'b0000000011011001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT218 = "16'b0000000011011010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT219 = "16'b0000000011011011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT22 = "16'b0000000000010110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT220 = "16'b0000000011011100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT221 = "16'b0000000011011101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT222 = "16'b0000000011011110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT223 = "16'b0000000011011111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT224 = "16'b0000000011100000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT225 = "16'b0000000011100001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT226 = "16'b0000000011100010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT227 = "16'b0000000011100011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT228 = "16'b0000000011100100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT229 = "16'b0000000011100101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT23 = "16'b0000000000010111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT230 = "16'b0000000011100110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT231 = "16'b0000000011100111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT232 = "16'b0000000011101000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT233 = "16'b0000000011101001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT234 = "16'b0000000011101010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT235 = "16'b0000000011101011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT236 = "16'b0000000011101100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT237 = "16'b0000000011101101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT238 = "16'b0000000011101110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT239 = "16'b0000000011101111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT24 = "16'b0000000000011000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT240 = "16'b0000000011110000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT241 = "16'b0000000011110001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT242 = "16'b0000000011110010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT243 = "16'b0000000011110011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT244 = "16'b0000000011110100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT245 = "16'b0000000011110101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT246 = "16'b0000000011110110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT247 = "16'b0000000011110111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT248 = "16'b0000000011111000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT249 = "16'b0000000011111001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT25 = "16'b0000000000011001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT250 = "16'b0000000011111010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT251 = "16'b0000000011111011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT252 = "16'b0000000011111100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT253 = "16'b0000000011111101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT254 = "16'b0000000011111110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT255 = "16'b0000000011111111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT26 = "16'b0000000000011010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT27 = "16'b0000000000011011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT28 = "16'b0000000000011100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT29 = "16'b0000000000011101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT3 = "16'b0000000000000011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT30 = "16'b0000000000011110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT31 = "16'b0000000000011111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT32 = "16'b0000000000100000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT33 = "16'b0000000000100001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT34 = "16'b0000000000100010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT35 = "16'b0000000000100011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT36 = "16'b0000000000100100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT37 = "16'b0000000000100101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT38 = "16'b0000000000100110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT39 = "16'b0000000000100111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT4 = "16'b0000000000000100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT40 = "16'b0000000000101000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT41 = "16'b0000000000101001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT42 = "16'b0000000000101010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT43 = "16'b0000000000101011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT44 = "16'b0000000000101100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT45 = "16'b0000000000101101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT46 = "16'b0000000000101110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT47 = "16'b0000000000101111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT48 = "16'b0000000000110000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT49 = "16'b0000000000110001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT5 = "16'b0000000000000101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT50 = "16'b0000000000110010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT51 = "16'b0000000000110011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT52 = "16'b0000000000110100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT53 = "16'b0000000000110101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT54 = "16'b0000000000110110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT55 = "16'b0000000000110111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT56 = "16'b0000000000111000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT57 = "16'b0000000000111001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT58 = "16'b0000000000111010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT59 = "16'b0000000000111011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT6 = "16'b0000000000000110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT60 = "16'b0000000000111100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT61 = "16'b0000000000111101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT62 = "16'b0000000000111110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT63 = "16'b0000000000111111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT64 = "16'b0000000001000000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT65 = "16'b0000000001000001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT66 = "16'b0000000001000010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT67 = "16'b0000000001000011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT68 = "16'b0000000001000100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT69 = "16'b0000000001000101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT7 = "16'b0000000000000111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT70 = "16'b0000000001000110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT71 = "16'b0000000001000111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT72 = "16'b0000000001001000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT73 = "16'b0000000001001001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT74 = "16'b0000000001001010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT75 = "16'b0000000001001011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT76 = "16'b0000000001001100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT77 = "16'b0000000001001101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT78 = "16'b0000000001001110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT79 = "16'b0000000001001111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT8 = "16'b0000000000001000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT80 = "16'b0000000001010000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT81 = "16'b0000000001010001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT82 = "16'b0000000001010010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT83 = "16'b0000000001010011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT84 = "16'b0000000001010100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT85 = "16'b0000000001010101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT86 = "16'b0000000001010110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT87 = "16'b0000000001010111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT88 = "16'b0000000001011000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT89 = "16'b0000000001011001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT9 = "16'b0000000000001001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT90 = "16'b0000000001011010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT91 = "16'b0000000001011011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT92 = "16'b0000000001011100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT93 = "16'b0000000001011101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT94 = "16'b0000000001011110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT95 = "16'b0000000001011111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT96 = "16'b0000000001100000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT97 = "16'b0000000001100001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT98 = "16'b0000000001100010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT99 = "16'b0000000001100011" *)
(* LC_LOW_BIT_POS_PROBE_OUT0 = "16'b0000000000000000" *)
(* LC_LOW_BIT_POS_PROBE_OUT1 = "16'b0000000000000001" *)
(* LC_LOW_BIT_POS_PROBE_OUT10 = "16'b0000000000001010" *)
(* LC_LOW_BIT_POS_PROBE_OUT100 = "16'b0000000001100100" *)
(* LC_LOW_BIT_POS_PROBE_OUT101 = "16'b0000000001100101" *)
(* LC_LOW_BIT_POS_PROBE_OUT102 = "16'b0000000001100110" *)
(* LC_LOW_BIT_POS_PROBE_OUT103 = "16'b0000000001100111" *)
(* LC_LOW_BIT_POS_PROBE_OUT104 = "16'b0000000001101000" *)
(* LC_LOW_BIT_POS_PROBE_OUT105 = "16'b0000000001101001" *)
(* LC_LOW_BIT_POS_PROBE_OUT106 = "16'b0000000001101010" *)
(* LC_LOW_BIT_POS_PROBE_OUT107 = "16'b0000000001101011" *)
(* LC_LOW_BIT_POS_PROBE_OUT108 = "16'b0000000001101100" *)
(* LC_LOW_BIT_POS_PROBE_OUT109 = "16'b0000000001101101" *)
(* LC_LOW_BIT_POS_PROBE_OUT11 = "16'b0000000000001011" *)
(* LC_LOW_BIT_POS_PROBE_OUT110 = "16'b0000000001101110" *)
(* LC_LOW_BIT_POS_PROBE_OUT111 = "16'b0000000001101111" *)
(* LC_LOW_BIT_POS_PROBE_OUT112 = "16'b0000000001110000" *)
(* LC_LOW_BIT_POS_PROBE_OUT113 = "16'b0000000001110001" *)
(* LC_LOW_BIT_POS_PROBE_OUT114 = "16'b0000000001110010" *)
(* LC_LOW_BIT_POS_PROBE_OUT115 = "16'b0000000001110011" *)
(* LC_LOW_BIT_POS_PROBE_OUT116 = "16'b0000000001110100" *)
(* LC_LOW_BIT_POS_PROBE_OUT117 = "16'b0000000001110101" *)
(* LC_LOW_BIT_POS_PROBE_OUT118 = "16'b0000000001110110" *)
(* LC_LOW_BIT_POS_PROBE_OUT119 = "16'b0000000001110111" *)
(* LC_LOW_BIT_POS_PROBE_OUT12 = "16'b0000000000001100" *)
(* LC_LOW_BIT_POS_PROBE_OUT120 = "16'b0000000001111000" *)
(* LC_LOW_BIT_POS_PROBE_OUT121 = "16'b0000000001111001" *)
(* LC_LOW_BIT_POS_PROBE_OUT122 = "16'b0000000001111010" *)
(* LC_LOW_BIT_POS_PROBE_OUT123 = "16'b0000000001111011" *)
(* LC_LOW_BIT_POS_PROBE_OUT124 = "16'b0000000001111100" *)
(* LC_LOW_BIT_POS_PROBE_OUT125 = "16'b0000000001111101" *)
(* LC_LOW_BIT_POS_PROBE_OUT126 = "16'b0000000001111110" *)
(* LC_LOW_BIT_POS_PROBE_OUT127 = "16'b0000000001111111" *)
(* LC_LOW_BIT_POS_PROBE_OUT128 = "16'b0000000010000000" *)
(* LC_LOW_BIT_POS_PROBE_OUT129 = "16'b0000000010000001" *)
(* LC_LOW_BIT_POS_PROBE_OUT13 = "16'b0000000000001101" *)
(* LC_LOW_BIT_POS_PROBE_OUT130 = "16'b0000000010000010" *)
(* LC_LOW_BIT_POS_PROBE_OUT131 = "16'b0000000010000011" *)
(* LC_LOW_BIT_POS_PROBE_OUT132 = "16'b0000000010000100" *)
(* LC_LOW_BIT_POS_PROBE_OUT133 = "16'b0000000010000101" *)
(* LC_LOW_BIT_POS_PROBE_OUT134 = "16'b0000000010000110" *)
(* LC_LOW_BIT_POS_PROBE_OUT135 = "16'b0000000010000111" *)
(* LC_LOW_BIT_POS_PROBE_OUT136 = "16'b0000000010001000" *)
(* LC_LOW_BIT_POS_PROBE_OUT137 = "16'b0000000010001001" *)
(* LC_LOW_BIT_POS_PROBE_OUT138 = "16'b0000000010001010" *)
(* LC_LOW_BIT_POS_PROBE_OUT139 = "16'b0000000010001011" *)
(* LC_LOW_BIT_POS_PROBE_OUT14 = "16'b0000000000001110" *)
(* LC_LOW_BIT_POS_PROBE_OUT140 = "16'b0000000010001100" *)
(* LC_LOW_BIT_POS_PROBE_OUT141 = "16'b0000000010001101" *)
(* LC_LOW_BIT_POS_PROBE_OUT142 = "16'b0000000010001110" *)
(* LC_LOW_BIT_POS_PROBE_OUT143 = "16'b0000000010001111" *)
(* LC_LOW_BIT_POS_PROBE_OUT144 = "16'b0000000010010000" *)
(* LC_LOW_BIT_POS_PROBE_OUT145 = "16'b0000000010010001" *)
(* LC_LOW_BIT_POS_PROBE_OUT146 = "16'b0000000010010010" *)
(* LC_LOW_BIT_POS_PROBE_OUT147 = "16'b0000000010010011" *)
(* LC_LOW_BIT_POS_PROBE_OUT148 = "16'b0000000010010100" *)
(* LC_LOW_BIT_POS_PROBE_OUT149 = "16'b0000000010010101" *)
(* LC_LOW_BIT_POS_PROBE_OUT15 = "16'b0000000000001111" *)
(* LC_LOW_BIT_POS_PROBE_OUT150 = "16'b0000000010010110" *)
(* LC_LOW_BIT_POS_PROBE_OUT151 = "16'b0000000010010111" *)
(* LC_LOW_BIT_POS_PROBE_OUT152 = "16'b0000000010011000" *)
(* LC_LOW_BIT_POS_PROBE_OUT153 = "16'b0000000010011001" *)
(* LC_LOW_BIT_POS_PROBE_OUT154 = "16'b0000000010011010" *)
(* LC_LOW_BIT_POS_PROBE_OUT155 = "16'b0000000010011011" *)
(* LC_LOW_BIT_POS_PROBE_OUT156 = "16'b0000000010011100" *)
(* LC_LOW_BIT_POS_PROBE_OUT157 = "16'b0000000010011101" *)
(* LC_LOW_BIT_POS_PROBE_OUT158 = "16'b0000000010011110" *)
(* LC_LOW_BIT_POS_PROBE_OUT159 = "16'b0000000010011111" *)
(* LC_LOW_BIT_POS_PROBE_OUT16 = "16'b0000000000010000" *)
(* LC_LOW_BIT_POS_PROBE_OUT160 = "16'b0000000010100000" *)
(* LC_LOW_BIT_POS_PROBE_OUT161 = "16'b0000000010100001" *)
(* LC_LOW_BIT_POS_PROBE_OUT162 = "16'b0000000010100010" *)
(* LC_LOW_BIT_POS_PROBE_OUT163 = "16'b0000000010100011" *)
(* LC_LOW_BIT_POS_PROBE_OUT164 = "16'b0000000010100100" *)
(* LC_LOW_BIT_POS_PROBE_OUT165 = "16'b0000000010100101" *)
(* LC_LOW_BIT_POS_PROBE_OUT166 = "16'b0000000010100110" *)
(* LC_LOW_BIT_POS_PROBE_OUT167 = "16'b0000000010100111" *)
(* LC_LOW_BIT_POS_PROBE_OUT168 = "16'b0000000010101000" *)
(* LC_LOW_BIT_POS_PROBE_OUT169 = "16'b0000000010101001" *)
(* LC_LOW_BIT_POS_PROBE_OUT17 = "16'b0000000000010001" *)
(* LC_LOW_BIT_POS_PROBE_OUT170 = "16'b0000000010101010" *)
(* LC_LOW_BIT_POS_PROBE_OUT171 = "16'b0000000010101011" *)
(* LC_LOW_BIT_POS_PROBE_OUT172 = "16'b0000000010101100" *)
(* LC_LOW_BIT_POS_PROBE_OUT173 = "16'b0000000010101101" *)
(* LC_LOW_BIT_POS_PROBE_OUT174 = "16'b0000000010101110" *)
(* LC_LOW_BIT_POS_PROBE_OUT175 = "16'b0000000010101111" *)
(* LC_LOW_BIT_POS_PROBE_OUT176 = "16'b0000000010110000" *)
(* LC_LOW_BIT_POS_PROBE_OUT177 = "16'b0000000010110001" *)
(* LC_LOW_BIT_POS_PROBE_OUT178 = "16'b0000000010110010" *)
(* LC_LOW_BIT_POS_PROBE_OUT179 = "16'b0000000010110011" *)
(* LC_LOW_BIT_POS_PROBE_OUT18 = "16'b0000000000010010" *)
(* LC_LOW_BIT_POS_PROBE_OUT180 = "16'b0000000010110100" *)
(* LC_LOW_BIT_POS_PROBE_OUT181 = "16'b0000000010110101" *)
(* LC_LOW_BIT_POS_PROBE_OUT182 = "16'b0000000010110110" *)
(* LC_LOW_BIT_POS_PROBE_OUT183 = "16'b0000000010110111" *)
(* LC_LOW_BIT_POS_PROBE_OUT184 = "16'b0000000010111000" *)
(* LC_LOW_BIT_POS_PROBE_OUT185 = "16'b0000000010111001" *)
(* LC_LOW_BIT_POS_PROBE_OUT186 = "16'b0000000010111010" *)
(* LC_LOW_BIT_POS_PROBE_OUT187 = "16'b0000000010111011" *)
(* LC_LOW_BIT_POS_PROBE_OUT188 = "16'b0000000010111100" *)
(* LC_LOW_BIT_POS_PROBE_OUT189 = "16'b0000000010111101" *)
(* LC_LOW_BIT_POS_PROBE_OUT19 = "16'b0000000000010011" *)
(* LC_LOW_BIT_POS_PROBE_OUT190 = "16'b0000000010111110" *)
(* LC_LOW_BIT_POS_PROBE_OUT191 = "16'b0000000010111111" *)
(* LC_LOW_BIT_POS_PROBE_OUT192 = "16'b0000000011000000" *)
(* LC_LOW_BIT_POS_PROBE_OUT193 = "16'b0000000011000001" *)
(* LC_LOW_BIT_POS_PROBE_OUT194 = "16'b0000000011000010" *)
(* LC_LOW_BIT_POS_PROBE_OUT195 = "16'b0000000011000011" *)
(* LC_LOW_BIT_POS_PROBE_OUT196 = "16'b0000000011000100" *)
(* LC_LOW_BIT_POS_PROBE_OUT197 = "16'b0000000011000101" *)
(* LC_LOW_BIT_POS_PROBE_OUT198 = "16'b0000000011000110" *)
(* LC_LOW_BIT_POS_PROBE_OUT199 = "16'b0000000011000111" *)
(* LC_LOW_BIT_POS_PROBE_OUT2 = "16'b0000000000000010" *)
(* LC_LOW_BIT_POS_PROBE_OUT20 = "16'b0000000000010100" *)
(* LC_LOW_BIT_POS_PROBE_OUT200 = "16'b0000000011001000" *)
(* LC_LOW_BIT_POS_PROBE_OUT201 = "16'b0000000011001001" *)
(* LC_LOW_BIT_POS_PROBE_OUT202 = "16'b0000000011001010" *)
(* LC_LOW_BIT_POS_PROBE_OUT203 = "16'b0000000011001011" *)
(* LC_LOW_BIT_POS_PROBE_OUT204 = "16'b0000000011001100" *)
(* LC_LOW_BIT_POS_PROBE_OUT205 = "16'b0000000011001101" *)
(* LC_LOW_BIT_POS_PROBE_OUT206 = "16'b0000000011001110" *)
(* LC_LOW_BIT_POS_PROBE_OUT207 = "16'b0000000011001111" *)
(* LC_LOW_BIT_POS_PROBE_OUT208 = "16'b0000000011010000" *)
(* LC_LOW_BIT_POS_PROBE_OUT209 = "16'b0000000011010001" *)
(* LC_LOW_BIT_POS_PROBE_OUT21 = "16'b0000000000010101" *)
(* LC_LOW_BIT_POS_PROBE_OUT210 = "16'b0000000011010010" *)
(* LC_LOW_BIT_POS_PROBE_OUT211 = "16'b0000000011010011" *)
(* LC_LOW_BIT_POS_PROBE_OUT212 = "16'b0000000011010100" *)
(* LC_LOW_BIT_POS_PROBE_OUT213 = "16'b0000000011010101" *)
(* LC_LOW_BIT_POS_PROBE_OUT214 = "16'b0000000011010110" *)
(* LC_LOW_BIT_POS_PROBE_OUT215 = "16'b0000000011010111" *)
(* LC_LOW_BIT_POS_PROBE_OUT216 = "16'b0000000011011000" *)
(* LC_LOW_BIT_POS_PROBE_OUT217 = "16'b0000000011011001" *)
(* LC_LOW_BIT_POS_PROBE_OUT218 = "16'b0000000011011010" *)
(* LC_LOW_BIT_POS_PROBE_OUT219 = "16'b0000000011011011" *)
(* LC_LOW_BIT_POS_PROBE_OUT22 = "16'b0000000000010110" *)
(* LC_LOW_BIT_POS_PROBE_OUT220 = "16'b0000000011011100" *)
(* LC_LOW_BIT_POS_PROBE_OUT221 = "16'b0000000011011101" *)
(* LC_LOW_BIT_POS_PROBE_OUT222 = "16'b0000000011011110" *)
(* LC_LOW_BIT_POS_PROBE_OUT223 = "16'b0000000011011111" *)
(* LC_LOW_BIT_POS_PROBE_OUT224 = "16'b0000000011100000" *)
(* LC_LOW_BIT_POS_PROBE_OUT225 = "16'b0000000011100001" *)
(* LC_LOW_BIT_POS_PROBE_OUT226 = "16'b0000000011100010" *)
(* LC_LOW_BIT_POS_PROBE_OUT227 = "16'b0000000011100011" *)
(* LC_LOW_BIT_POS_PROBE_OUT228 = "16'b0000000011100100" *)
(* LC_LOW_BIT_POS_PROBE_OUT229 = "16'b0000000011100101" *)
(* LC_LOW_BIT_POS_PROBE_OUT23 = "16'b0000000000010111" *)
(* LC_LOW_BIT_POS_PROBE_OUT230 = "16'b0000000011100110" *)
(* LC_LOW_BIT_POS_PROBE_OUT231 = "16'b0000000011100111" *)
(* LC_LOW_BIT_POS_PROBE_OUT232 = "16'b0000000011101000" *)
(* LC_LOW_BIT_POS_PROBE_OUT233 = "16'b0000000011101001" *)
(* LC_LOW_BIT_POS_PROBE_OUT234 = "16'b0000000011101010" *)
(* LC_LOW_BIT_POS_PROBE_OUT235 = "16'b0000000011101011" *)
(* LC_LOW_BIT_POS_PROBE_OUT236 = "16'b0000000011101100" *)
(* LC_LOW_BIT_POS_PROBE_OUT237 = "16'b0000000011101101" *)
(* LC_LOW_BIT_POS_PROBE_OUT238 = "16'b0000000011101110" *)
(* LC_LOW_BIT_POS_PROBE_OUT239 = "16'b0000000011101111" *)
(* LC_LOW_BIT_POS_PROBE_OUT24 = "16'b0000000000011000" *)
(* LC_LOW_BIT_POS_PROBE_OUT240 = "16'b0000000011110000" *)
(* LC_LOW_BIT_POS_PROBE_OUT241 = "16'b0000000011110001" *)
(* LC_LOW_BIT_POS_PROBE_OUT242 = "16'b0000000011110010" *)
(* LC_LOW_BIT_POS_PROBE_OUT243 = "16'b0000000011110011" *)
(* LC_LOW_BIT_POS_PROBE_OUT244 = "16'b0000000011110100" *)
(* LC_LOW_BIT_POS_PROBE_OUT245 = "16'b0000000011110101" *)
(* LC_LOW_BIT_POS_PROBE_OUT246 = "16'b0000000011110110" *)
(* LC_LOW_BIT_POS_PROBE_OUT247 = "16'b0000000011110111" *)
(* LC_LOW_BIT_POS_PROBE_OUT248 = "16'b0000000011111000" *)
(* LC_LOW_BIT_POS_PROBE_OUT249 = "16'b0000000011111001" *)
(* LC_LOW_BIT_POS_PROBE_OUT25 = "16'b0000000000011001" *)
(* LC_LOW_BIT_POS_PROBE_OUT250 = "16'b0000000011111010" *)
(* LC_LOW_BIT_POS_PROBE_OUT251 = "16'b0000000011111011" *)
(* LC_LOW_BIT_POS_PROBE_OUT252 = "16'b0000000011111100" *)
(* LC_LOW_BIT_POS_PROBE_OUT253 = "16'b0000000011111101" *)
(* LC_LOW_BIT_POS_PROBE_OUT254 = "16'b0000000011111110" *)
(* LC_LOW_BIT_POS_PROBE_OUT255 = "16'b0000000011111111" *)
(* LC_LOW_BIT_POS_PROBE_OUT26 = "16'b0000000000011010" *)
(* LC_LOW_BIT_POS_PROBE_OUT27 = "16'b0000000000011011" *)
(* LC_LOW_BIT_POS_PROBE_OUT28 = "16'b0000000000011100" *)
(* LC_LOW_BIT_POS_PROBE_OUT29 = "16'b0000000000011101" *)
(* LC_LOW_BIT_POS_PROBE_OUT3 = "16'b0000000000000011" *)
(* LC_LOW_BIT_POS_PROBE_OUT30 = "16'b0000000000011110" *)
(* LC_LOW_BIT_POS_PROBE_OUT31 = "16'b0000000000011111" *)
(* LC_LOW_BIT_POS_PROBE_OUT32 = "16'b0000000000100000" *)
(* LC_LOW_BIT_POS_PROBE_OUT33 = "16'b0000000000100001" *)
(* LC_LOW_BIT_POS_PROBE_OUT34 = "16'b0000000000100010" *)
(* LC_LOW_BIT_POS_PROBE_OUT35 = "16'b0000000000100011" *)
(* LC_LOW_BIT_POS_PROBE_OUT36 = "16'b0000000000100100" *)
(* LC_LOW_BIT_POS_PROBE_OUT37 = "16'b0000000000100101" *)
(* LC_LOW_BIT_POS_PROBE_OUT38 = "16'b0000000000100110" *)
(* LC_LOW_BIT_POS_PROBE_OUT39 = "16'b0000000000100111" *)
(* LC_LOW_BIT_POS_PROBE_OUT4 = "16'b0000000000000100" *)
(* LC_LOW_BIT_POS_PROBE_OUT40 = "16'b0000000000101000" *)
(* LC_LOW_BIT_POS_PROBE_OUT41 = "16'b0000000000101001" *)
(* LC_LOW_BIT_POS_PROBE_OUT42 = "16'b0000000000101010" *)
(* LC_LOW_BIT_POS_PROBE_OUT43 = "16'b0000000000101011" *)
(* LC_LOW_BIT_POS_PROBE_OUT44 = "16'b0000000000101100" *)
(* LC_LOW_BIT_POS_PROBE_OUT45 = "16'b0000000000101101" *)
(* LC_LOW_BIT_POS_PROBE_OUT46 = "16'b0000000000101110" *)
(* LC_LOW_BIT_POS_PROBE_OUT47 = "16'b0000000000101111" *)
(* LC_LOW_BIT_POS_PROBE_OUT48 = "16'b0000000000110000" *)
(* LC_LOW_BIT_POS_PROBE_OUT49 = "16'b0000000000110001" *)
(* LC_LOW_BIT_POS_PROBE_OUT5 = "16'b0000000000000101" *)
(* LC_LOW_BIT_POS_PROBE_OUT50 = "16'b0000000000110010" *)
(* LC_LOW_BIT_POS_PROBE_OUT51 = "16'b0000000000110011" *)
(* LC_LOW_BIT_POS_PROBE_OUT52 = "16'b0000000000110100" *)
(* LC_LOW_BIT_POS_PROBE_OUT53 = "16'b0000000000110101" *)
(* LC_LOW_BIT_POS_PROBE_OUT54 = "16'b0000000000110110" *)
(* LC_LOW_BIT_POS_PROBE_OUT55 = "16'b0000000000110111" *)
(* LC_LOW_BIT_POS_PROBE_OUT56 = "16'b0000000000111000" *)
(* LC_LOW_BIT_POS_PROBE_OUT57 = "16'b0000000000111001" *)
(* LC_LOW_BIT_POS_PROBE_OUT58 = "16'b0000000000111010" *)
(* LC_LOW_BIT_POS_PROBE_OUT59 = "16'b0000000000111011" *)
(* LC_LOW_BIT_POS_PROBE_OUT6 = "16'b0000000000000110" *)
(* LC_LOW_BIT_POS_PROBE_OUT60 = "16'b0000000000111100" *)
(* LC_LOW_BIT_POS_PROBE_OUT61 = "16'b0000000000111101" *)
(* LC_LOW_BIT_POS_PROBE_OUT62 = "16'b0000000000111110" *)
(* LC_LOW_BIT_POS_PROBE_OUT63 = "16'b0000000000111111" *)
(* LC_LOW_BIT_POS_PROBE_OUT64 = "16'b0000000001000000" *)
(* LC_LOW_BIT_POS_PROBE_OUT65 = "16'b0000000001000001" *)
(* LC_LOW_BIT_POS_PROBE_OUT66 = "16'b0000000001000010" *)
(* LC_LOW_BIT_POS_PROBE_OUT67 = "16'b0000000001000011" *)
(* LC_LOW_BIT_POS_PROBE_OUT68 = "16'b0000000001000100" *)
(* LC_LOW_BIT_POS_PROBE_OUT69 = "16'b0000000001000101" *)
(* LC_LOW_BIT_POS_PROBE_OUT7 = "16'b0000000000000111" *)
(* LC_LOW_BIT_POS_PROBE_OUT70 = "16'b0000000001000110" *)
(* LC_LOW_BIT_POS_PROBE_OUT71 = "16'b0000000001000111" *)
(* LC_LOW_BIT_POS_PROBE_OUT72 = "16'b0000000001001000" *)
(* LC_LOW_BIT_POS_PROBE_OUT73 = "16'b0000000001001001" *)
(* LC_LOW_BIT_POS_PROBE_OUT74 = "16'b0000000001001010" *)
(* LC_LOW_BIT_POS_PROBE_OUT75 = "16'b0000000001001011" *)
(* LC_LOW_BIT_POS_PROBE_OUT76 = "16'b0000000001001100" *)
(* LC_LOW_BIT_POS_PROBE_OUT77 = "16'b0000000001001101" *)
(* LC_LOW_BIT_POS_PROBE_OUT78 = "16'b0000000001001110" *)
(* LC_LOW_BIT_POS_PROBE_OUT79 = "16'b0000000001001111" *)
(* LC_LOW_BIT_POS_PROBE_OUT8 = "16'b0000000000001000" *)
(* LC_LOW_BIT_POS_PROBE_OUT80 = "16'b0000000001010000" *)
(* LC_LOW_BIT_POS_PROBE_OUT81 = "16'b0000000001010001" *)
(* LC_LOW_BIT_POS_PROBE_OUT82 = "16'b0000000001010010" *)
(* LC_LOW_BIT_POS_PROBE_OUT83 = "16'b0000000001010011" *)
(* LC_LOW_BIT_POS_PROBE_OUT84 = "16'b0000000001010100" *)
(* LC_LOW_BIT_POS_PROBE_OUT85 = "16'b0000000001010101" *)
(* LC_LOW_BIT_POS_PROBE_OUT86 = "16'b0000000001010110" *)
(* LC_LOW_BIT_POS_PROBE_OUT87 = "16'b0000000001010111" *)
(* LC_LOW_BIT_POS_PROBE_OUT88 = "16'b0000000001011000" *)
(* LC_LOW_BIT_POS_PROBE_OUT89 = "16'b0000000001011001" *)
(* LC_LOW_BIT_POS_PROBE_OUT9 = "16'b0000000000001001" *)
(* LC_LOW_BIT_POS_PROBE_OUT90 = "16'b0000000001011010" *)
(* LC_LOW_BIT_POS_PROBE_OUT91 = "16'b0000000001011011" *)
(* LC_LOW_BIT_POS_PROBE_OUT92 = "16'b0000000001011100" *)
(* LC_LOW_BIT_POS_PROBE_OUT93 = "16'b0000000001011101" *)
(* LC_LOW_BIT_POS_PROBE_OUT94 = "16'b0000000001011110" *)
(* LC_LOW_BIT_POS_PROBE_OUT95 = "16'b0000000001011111" *)
(* LC_LOW_BIT_POS_PROBE_OUT96 = "16'b0000000001100000" *)
(* LC_LOW_BIT_POS_PROBE_OUT97 = "16'b0000000001100001" *)
(* LC_LOW_BIT_POS_PROBE_OUT98 = "16'b0000000001100010" *)
(* LC_LOW_BIT_POS_PROBE_OUT99 = "16'b0000000001100011" *)
(* LC_PROBE_IN_WIDTH_STRING = "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* LC_PROBE_OUT_HIGH_BIT_POS_STRING = "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000" *)
(* LC_PROBE_OUT_INIT_VAL_STRING = "256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* LC_PROBE_OUT_LOW_BIT_POS_STRING = "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000" *)
(* LC_PROBE_OUT_WIDTH_STRING = "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* LC_TOTAL_PROBE_IN_WIDTH = "4" *)
(* LC_TOTAL_PROBE_OUT_WIDTH = "0" *)
(* syn_noprune = "1" *)
vio_0_vio_v3_0_13_vio inst
(.clk(clk),
.probe_in0(probe_in0),
.probe_in1(probe_in1),
.probe_in10(1'b0),
.probe_in100(1'b0),
.probe_in101(1'b0),
.probe_in102(1'b0),
.probe_in103(1'b0),
.probe_in104(1'b0),
.probe_in105(1'b0),
.probe_in106(1'b0),
.probe_in107(1'b0),
.probe_in108(1'b0),
.probe_in109(1'b0),
.probe_in11(1'b0),
.probe_in110(1'b0),
.probe_in111(1'b0),
.probe_in112(1'b0),
.probe_in113(1'b0),
.probe_in114(1'b0),
.probe_in115(1'b0),
.probe_in116(1'b0),
.probe_in117(1'b0),
.probe_in118(1'b0),
.probe_in119(1'b0),
.probe_in12(1'b0),
.probe_in120(1'b0),
.probe_in121(1'b0),
.probe_in122(1'b0),
.probe_in123(1'b0),
.probe_in124(1'b0),
.probe_in125(1'b0),
.probe_in126(1'b0),
.probe_in127(1'b0),
.probe_in128(1'b0),
.probe_in129(1'b0),
.probe_in13(1'b0),
.probe_in130(1'b0),
.probe_in131(1'b0),
.probe_in132(1'b0),
.probe_in133(1'b0),
.probe_in134(1'b0),
.probe_in135(1'b0),
.probe_in136(1'b0),
.probe_in137(1'b0),
.probe_in138(1'b0),
.probe_in139(1'b0),
.probe_in14(1'b0),
.probe_in140(1'b0),
.probe_in141(1'b0),
.probe_in142(1'b0),
.probe_in143(1'b0),
.probe_in144(1'b0),
.probe_in145(1'b0),
.probe_in146(1'b0),
.probe_in147(1'b0),
.probe_in148(1'b0),
.probe_in149(1'b0),
.probe_in15(1'b0),
.probe_in150(1'b0),
.probe_in151(1'b0),
.probe_in152(1'b0),
.probe_in153(1'b0),
.probe_in154(1'b0),
.probe_in155(1'b0),
.probe_in156(1'b0),
.probe_in157(1'b0),
.probe_in158(1'b0),
.probe_in159(1'b0),
.probe_in16(1'b0),
.probe_in160(1'b0),
.probe_in161(1'b0),
.probe_in162(1'b0),
.probe_in163(1'b0),
.probe_in164(1'b0),
.probe_in165(1'b0),
.probe_in166(1'b0),
.probe_in167(1'b0),
.probe_in168(1'b0),
.probe_in169(1'b0),
.probe_in17(1'b0),
.probe_in170(1'b0),
.probe_in171(1'b0),
.probe_in172(1'b0),
.probe_in173(1'b0),
.probe_in174(1'b0),
.probe_in175(1'b0),
.probe_in176(1'b0),
.probe_in177(1'b0),
.probe_in178(1'b0),
.probe_in179(1'b0),
.probe_in18(1'b0),
.probe_in180(1'b0),
.probe_in181(1'b0),
.probe_in182(1'b0),
.probe_in183(1'b0),
.probe_in184(1'b0),
.probe_in185(1'b0),
.probe_in186(1'b0),
.probe_in187(1'b0),
.probe_in188(1'b0),
.probe_in189(1'b0),
.probe_in19(1'b0),
.probe_in190(1'b0),
.probe_in191(1'b0),
.probe_in192(1'b0),
.probe_in193(1'b0),
.probe_in194(1'b0),
.probe_in195(1'b0),
.probe_in196(1'b0),
.probe_in197(1'b0),
.probe_in198(1'b0),
.probe_in199(1'b0),
.probe_in2(probe_in2),
.probe_in20(1'b0),
.probe_in200(1'b0),
.probe_in201(1'b0),
.probe_in202(1'b0),
.probe_in203(1'b0),
.probe_in204(1'b0),
.probe_in205(1'b0),
.probe_in206(1'b0),
.probe_in207(1'b0),
.probe_in208(1'b0),
.probe_in209(1'b0),
.probe_in21(1'b0),
.probe_in210(1'b0),
.probe_in211(1'b0),
.probe_in212(1'b0),
.probe_in213(1'b0),
.probe_in214(1'b0),
.probe_in215(1'b0),
.probe_in216(1'b0),
.probe_in217(1'b0),
.probe_in218(1'b0),
.probe_in219(1'b0),
.probe_in22(1'b0),
.probe_in220(1'b0),
.probe_in221(1'b0),
.probe_in222(1'b0),
.probe_in223(1'b0),
.probe_in224(1'b0),
.probe_in225(1'b0),
.probe_in226(1'b0),
.probe_in227(1'b0),
.probe_in228(1'b0),
.probe_in229(1'b0),
.probe_in23(1'b0),
.probe_in230(1'b0),
.probe_in231(1'b0),
.probe_in232(1'b0),
.probe_in233(1'b0),
.probe_in234(1'b0),
.probe_in235(1'b0),
.probe_in236(1'b0),
.probe_in237(1'b0),
.probe_in238(1'b0),
.probe_in239(1'b0),
.probe_in24(1'b0),
.probe_in240(1'b0),
.probe_in241(1'b0),
.probe_in242(1'b0),
.probe_in243(1'b0),
.probe_in244(1'b0),
.probe_in245(1'b0),
.probe_in246(1'b0),
.probe_in247(1'b0),
.probe_in248(1'b0),
.probe_in249(1'b0),
.probe_in25(1'b0),
.probe_in250(1'b0),
.probe_in251(1'b0),
.probe_in252(1'b0),
.probe_in253(1'b0),
.probe_in254(1'b0),
.probe_in255(1'b0),
.probe_in26(1'b0),
.probe_in27(1'b0),
.probe_in28(1'b0),
.probe_in29(1'b0),
.probe_in3(probe_in3),
.probe_in30(1'b0),
.probe_in31(1'b0),
.probe_in32(1'b0),
.probe_in33(1'b0),
.probe_in34(1'b0),
.probe_in35(1'b0),
.probe_in36(1'b0),
.probe_in37(1'b0),
.probe_in38(1'b0),
.probe_in39(1'b0),
.probe_in4(1'b0),
.probe_in40(1'b0),
.probe_in41(1'b0),
.probe_in42(1'b0),
.probe_in43(1'b0),
.probe_in44(1'b0),
.probe_in45(1'b0),
.probe_in46(1'b0),
.probe_in47(1'b0),
.probe_in48(1'b0),
.probe_in49(1'b0),
.probe_in5(1'b0),
.probe_in50(1'b0),
.probe_in51(1'b0),
.probe_in52(1'b0),
.probe_in53(1'b0),
.probe_in54(1'b0),
.probe_in55(1'b0),
.probe_in56(1'b0),
.probe_in57(1'b0),
.probe_in58(1'b0),
.probe_in59(1'b0),
.probe_in6(1'b0),
.probe_in60(1'b0),
.probe_in61(1'b0),
.probe_in62(1'b0),
.probe_in63(1'b0),
.probe_in64(1'b0),
.probe_in65(1'b0),
.probe_in66(1'b0),
.probe_in67(1'b0),
.probe_in68(1'b0),
.probe_in69(1'b0),
.probe_in7(1'b0),
.probe_in70(1'b0),
.probe_in71(1'b0),
.probe_in72(1'b0),
.probe_in73(1'b0),
.probe_in74(1'b0),
.probe_in75(1'b0),
.probe_in76(1'b0),
.probe_in77(1'b0),
.probe_in78(1'b0),
.probe_in79(1'b0),
.probe_in8(1'b0),
.probe_in80(1'b0),
.probe_in81(1'b0),
.probe_in82(1'b0),
.probe_in83(1'b0),
.probe_in84(1'b0),
.probe_in85(1'b0),
.probe_in86(1'b0),
.probe_in87(1'b0),
.probe_in88(1'b0),
.probe_in89(1'b0),
.probe_in9(1'b0),
.probe_in90(1'b0),
.probe_in91(1'b0),
.probe_in92(1'b0),
.probe_in93(1'b0),
.probe_in94(1'b0),
.probe_in95(1'b0),
.probe_in96(1'b0),
.probe_in97(1'b0),
.probe_in98(1'b0),
.probe_in99(1'b0),
.probe_out0(NLW_inst_probe_out0_UNCONNECTED[0]),
.probe_out1(NLW_inst_probe_out1_UNCONNECTED[0]),
.probe_out10(NLW_inst_probe_out10_UNCONNECTED[0]),
.probe_out100(NLW_inst_probe_out100_UNCONNECTED[0]),
.probe_out101(NLW_inst_probe_out101_UNCONNECTED[0]),
.probe_out102(NLW_inst_probe_out102_UNCONNECTED[0]),
.probe_out103(NLW_inst_probe_out103_UNCONNECTED[0]),
.probe_out104(NLW_inst_probe_out104_UNCONNECTED[0]),
.probe_out105(NLW_inst_probe_out105_UNCONNECTED[0]),
.probe_out106(NLW_inst_probe_out106_UNCONNECTED[0]),
.probe_out107(NLW_inst_probe_out107_UNCONNECTED[0]),
.probe_out108(NLW_inst_probe_out108_UNCONNECTED[0]),
.probe_out109(NLW_inst_probe_out109_UNCONNECTED[0]),
.probe_out11(NLW_inst_probe_out11_UNCONNECTED[0]),
.probe_out110(NLW_inst_probe_out110_UNCONNECTED[0]),
.probe_out111(NLW_inst_probe_out111_UNCONNECTED[0]),
.probe_out112(NLW_inst_probe_out112_UNCONNECTED[0]),
.probe_out113(NLW_inst_probe_out113_UNCONNECTED[0]),
.probe_out114(NLW_inst_probe_out114_UNCONNECTED[0]),
.probe_out115(NLW_inst_probe_out115_UNCONNECTED[0]),
.probe_out116(NLW_inst_probe_out116_UNCONNECTED[0]),
.probe_out117(NLW_inst_probe_out117_UNCONNECTED[0]),
.probe_out118(NLW_inst_probe_out118_UNCONNECTED[0]),
.probe_out119(NLW_inst_probe_out119_UNCONNECTED[0]),
.probe_out12(NLW_inst_probe_out12_UNCONNECTED[0]),
.probe_out120(NLW_inst_probe_out120_UNCONNECTED[0]),
.probe_out121(NLW_inst_probe_out121_UNCONNECTED[0]),
.probe_out122(NLW_inst_probe_out122_UNCONNECTED[0]),
.probe_out123(NLW_inst_probe_out123_UNCONNECTED[0]),
.probe_out124(NLW_inst_probe_out124_UNCONNECTED[0]),
.probe_out125(NLW_inst_probe_out125_UNCONNECTED[0]),
.probe_out126(NLW_inst_probe_out126_UNCONNECTED[0]),
.probe_out127(NLW_inst_probe_out127_UNCONNECTED[0]),
.probe_out128(NLW_inst_probe_out128_UNCONNECTED[0]),
.probe_out129(NLW_inst_probe_out129_UNCONNECTED[0]),
.probe_out13(NLW_inst_probe_out13_UNCONNECTED[0]),
.probe_out130(NLW_inst_probe_out130_UNCONNECTED[0]),
.probe_out131(NLW_inst_probe_out131_UNCONNECTED[0]),
.probe_out132(NLW_inst_probe_out132_UNCONNECTED[0]),
.probe_out133(NLW_inst_probe_out133_UNCONNECTED[0]),
.probe_out134(NLW_inst_probe_out134_UNCONNECTED[0]),
.probe_out135(NLW_inst_probe_out135_UNCONNECTED[0]),
.probe_out136(NLW_inst_probe_out136_UNCONNECTED[0]),
.probe_out137(NLW_inst_probe_out137_UNCONNECTED[0]),
.probe_out138(NLW_inst_probe_out138_UNCONNECTED[0]),
.probe_out139(NLW_inst_probe_out139_UNCONNECTED[0]),
.probe_out14(NLW_inst_probe_out14_UNCONNECTED[0]),
.probe_out140(NLW_inst_probe_out140_UNCONNECTED[0]),
.probe_out141(NLW_inst_probe_out141_UNCONNECTED[0]),
.probe_out142(NLW_inst_probe_out142_UNCONNECTED[0]),
.probe_out143(NLW_inst_probe_out143_UNCONNECTED[0]),
.probe_out144(NLW_inst_probe_out144_UNCONNECTED[0]),
.probe_out145(NLW_inst_probe_out145_UNCONNECTED[0]),
.probe_out146(NLW_inst_probe_out146_UNCONNECTED[0]),
.probe_out147(NLW_inst_probe_out147_UNCONNECTED[0]),
.probe_out148(NLW_inst_probe_out148_UNCONNECTED[0]),
.probe_out149(NLW_inst_probe_out149_UNCONNECTED[0]),
.probe_out15(NLW_inst_probe_out15_UNCONNECTED[0]),
.probe_out150(NLW_inst_probe_out150_UNCONNECTED[0]),
.probe_out151(NLW_inst_probe_out151_UNCONNECTED[0]),
.probe_out152(NLW_inst_probe_out152_UNCONNECTED[0]),
.probe_out153(NLW_inst_probe_out153_UNCONNECTED[0]),
.probe_out154(NLW_inst_probe_out154_UNCONNECTED[0]),
.probe_out155(NLW_inst_probe_out155_UNCONNECTED[0]),
.probe_out156(NLW_inst_probe_out156_UNCONNECTED[0]),
.probe_out157(NLW_inst_probe_out157_UNCONNECTED[0]),
.probe_out158(NLW_inst_probe_out158_UNCONNECTED[0]),
.probe_out159(NLW_inst_probe_out159_UNCONNECTED[0]),
.probe_out16(NLW_inst_probe_out16_UNCONNECTED[0]),
.probe_out160(NLW_inst_probe_out160_UNCONNECTED[0]),
.probe_out161(NLW_inst_probe_out161_UNCONNECTED[0]),
.probe_out162(NLW_inst_probe_out162_UNCONNECTED[0]),
.probe_out163(NLW_inst_probe_out163_UNCONNECTED[0]),
.probe_out164(NLW_inst_probe_out164_UNCONNECTED[0]),
.probe_out165(NLW_inst_probe_out165_UNCONNECTED[0]),
.probe_out166(NLW_inst_probe_out166_UNCONNECTED[0]),
.probe_out167(NLW_inst_probe_out167_UNCONNECTED[0]),
.probe_out168(NLW_inst_probe_out168_UNCONNECTED[0]),
.probe_out169(NLW_inst_probe_out169_UNCONNECTED[0]),
.probe_out17(NLW_inst_probe_out17_UNCONNECTED[0]),
.probe_out170(NLW_inst_probe_out170_UNCONNECTED[0]),
.probe_out171(NLW_inst_probe_out171_UNCONNECTED[0]),
.probe_out172(NLW_inst_probe_out172_UNCONNECTED[0]),
.probe_out173(NLW_inst_probe_out173_UNCONNECTED[0]),
.probe_out174(NLW_inst_probe_out174_UNCONNECTED[0]),
.probe_out175(NLW_inst_probe_out175_UNCONNECTED[0]),
.probe_out176(NLW_inst_probe_out176_UNCONNECTED[0]),
.probe_out177(NLW_inst_probe_out177_UNCONNECTED[0]),
.probe_out178(NLW_inst_probe_out178_UNCONNECTED[0]),
.probe_out179(NLW_inst_probe_out179_UNCONNECTED[0]),
.probe_out18(NLW_inst_probe_out18_UNCONNECTED[0]),
.probe_out180(NLW_inst_probe_out180_UNCONNECTED[0]),
.probe_out181(NLW_inst_probe_out181_UNCONNECTED[0]),
.probe_out182(NLW_inst_probe_out182_UNCONNECTED[0]),
.probe_out183(NLW_inst_probe_out183_UNCONNECTED[0]),
.probe_out184(NLW_inst_probe_out184_UNCONNECTED[0]),
.probe_out185(NLW_inst_probe_out185_UNCONNECTED[0]),
.probe_out186(NLW_inst_probe_out186_UNCONNECTED[0]),
.probe_out187(NLW_inst_probe_out187_UNCONNECTED[0]),
.probe_out188(NLW_inst_probe_out188_UNCONNECTED[0]),
.probe_out189(NLW_inst_probe_out189_UNCONNECTED[0]),
.probe_out19(NLW_inst_probe_out19_UNCONNECTED[0]),
.probe_out190(NLW_inst_probe_out190_UNCONNECTED[0]),
.probe_out191(NLW_inst_probe_out191_UNCONNECTED[0]),
.probe_out192(NLW_inst_probe_out192_UNCONNECTED[0]),
.probe_out193(NLW_inst_probe_out193_UNCONNECTED[0]),
.probe_out194(NLW_inst_probe_out194_UNCONNECTED[0]),
.probe_out195(NLW_inst_probe_out195_UNCONNECTED[0]),
.probe_out196(NLW_inst_probe_out196_UNCONNECTED[0]),
.probe_out197(NLW_inst_probe_out197_UNCONNECTED[0]),
.probe_out198(NLW_inst_probe_out198_UNCONNECTED[0]),
.probe_out199(NLW_inst_probe_out199_UNCONNECTED[0]),
.probe_out2(NLW_inst_probe_out2_UNCONNECTED[0]),
.probe_out20(NLW_inst_probe_out20_UNCONNECTED[0]),
.probe_out200(NLW_inst_probe_out200_UNCONNECTED[0]),
.probe_out201(NLW_inst_probe_out201_UNCONNECTED[0]),
.probe_out202(NLW_inst_probe_out202_UNCONNECTED[0]),
.probe_out203(NLW_inst_probe_out203_UNCONNECTED[0]),
.probe_out204(NLW_inst_probe_out204_UNCONNECTED[0]),
.probe_out205(NLW_inst_probe_out205_UNCONNECTED[0]),
.probe_out206(NLW_inst_probe_out206_UNCONNECTED[0]),
.probe_out207(NLW_inst_probe_out207_UNCONNECTED[0]),
.probe_out208(NLW_inst_probe_out208_UNCONNECTED[0]),
.probe_out209(NLW_inst_probe_out209_UNCONNECTED[0]),
.probe_out21(NLW_inst_probe_out21_UNCONNECTED[0]),
.probe_out210(NLW_inst_probe_out210_UNCONNECTED[0]),
.probe_out211(NLW_inst_probe_out211_UNCONNECTED[0]),
.probe_out212(NLW_inst_probe_out212_UNCONNECTED[0]),
.probe_out213(NLW_inst_probe_out213_UNCONNECTED[0]),
.probe_out214(NLW_inst_probe_out214_UNCONNECTED[0]),
.probe_out215(NLW_inst_probe_out215_UNCONNECTED[0]),
.probe_out216(NLW_inst_probe_out216_UNCONNECTED[0]),
.probe_out217(NLW_inst_probe_out217_UNCONNECTED[0]),
.probe_out218(NLW_inst_probe_out218_UNCONNECTED[0]),
.probe_out219(NLW_inst_probe_out219_UNCONNECTED[0]),
.probe_out22(NLW_inst_probe_out22_UNCONNECTED[0]),
.probe_out220(NLW_inst_probe_out220_UNCONNECTED[0]),
.probe_out221(NLW_inst_probe_out221_UNCONNECTED[0]),
.probe_out222(NLW_inst_probe_out222_UNCONNECTED[0]),
.probe_out223(NLW_inst_probe_out223_UNCONNECTED[0]),
.probe_out224(NLW_inst_probe_out224_UNCONNECTED[0]),
.probe_out225(NLW_inst_probe_out225_UNCONNECTED[0]),
.probe_out226(NLW_inst_probe_out226_UNCONNECTED[0]),
.probe_out227(NLW_inst_probe_out227_UNCONNECTED[0]),
.probe_out228(NLW_inst_probe_out228_UNCONNECTED[0]),
.probe_out229(NLW_inst_probe_out229_UNCONNECTED[0]),
.probe_out23(NLW_inst_probe_out23_UNCONNECTED[0]),
.probe_out230(NLW_inst_probe_out230_UNCONNECTED[0]),
.probe_out231(NLW_inst_probe_out231_UNCONNECTED[0]),
.probe_out232(NLW_inst_probe_out232_UNCONNECTED[0]),
.probe_out233(NLW_inst_probe_out233_UNCONNECTED[0]),
.probe_out234(NLW_inst_probe_out234_UNCONNECTED[0]),
.probe_out235(NLW_inst_probe_out235_UNCONNECTED[0]),
.probe_out236(NLW_inst_probe_out236_UNCONNECTED[0]),
.probe_out237(NLW_inst_probe_out237_UNCONNECTED[0]),
.probe_out238(NLW_inst_probe_out238_UNCONNECTED[0]),
.probe_out239(NLW_inst_probe_out239_UNCONNECTED[0]),
.probe_out24(NLW_inst_probe_out24_UNCONNECTED[0]),
.probe_out240(NLW_inst_probe_out240_UNCONNECTED[0]),
.probe_out241(NLW_inst_probe_out241_UNCONNECTED[0]),
.probe_out242(NLW_inst_probe_out242_UNCONNECTED[0]),
.probe_out243(NLW_inst_probe_out243_UNCONNECTED[0]),
.probe_out244(NLW_inst_probe_out244_UNCONNECTED[0]),
.probe_out245(NLW_inst_probe_out245_UNCONNECTED[0]),
.probe_out246(NLW_inst_probe_out246_UNCONNECTED[0]),
.probe_out247(NLW_inst_probe_out247_UNCONNECTED[0]),
.probe_out248(NLW_inst_probe_out248_UNCONNECTED[0]),
.probe_out249(NLW_inst_probe_out249_UNCONNECTED[0]),
.probe_out25(NLW_inst_probe_out25_UNCONNECTED[0]),
.probe_out250(NLW_inst_probe_out250_UNCONNECTED[0]),
.probe_out251(NLW_inst_probe_out251_UNCONNECTED[0]),
.probe_out252(NLW_inst_probe_out252_UNCONNECTED[0]),
.probe_out253(NLW_inst_probe_out253_UNCONNECTED[0]),
.probe_out254(NLW_inst_probe_out254_UNCONNECTED[0]),
.probe_out255(NLW_inst_probe_out255_UNCONNECTED[0]),
.probe_out26(NLW_inst_probe_out26_UNCONNECTED[0]),
.probe_out27(NLW_inst_probe_out27_UNCONNECTED[0]),
.probe_out28(NLW_inst_probe_out28_UNCONNECTED[0]),
.probe_out29(NLW_inst_probe_out29_UNCONNECTED[0]),
.probe_out3(NLW_inst_probe_out3_UNCONNECTED[0]),
.probe_out30(NLW_inst_probe_out30_UNCONNECTED[0]),
.probe_out31(NLW_inst_probe_out31_UNCONNECTED[0]),
.probe_out32(NLW_inst_probe_out32_UNCONNECTED[0]),
.probe_out33(NLW_inst_probe_out33_UNCONNECTED[0]),
.probe_out34(NLW_inst_probe_out34_UNCONNECTED[0]),
.probe_out35(NLW_inst_probe_out35_UNCONNECTED[0]),
.probe_out36(NLW_inst_probe_out36_UNCONNECTED[0]),
.probe_out37(NLW_inst_probe_out37_UNCONNECTED[0]),
.probe_out38(NLW_inst_probe_out38_UNCONNECTED[0]),
.probe_out39(NLW_inst_probe_out39_UNCONNECTED[0]),
.probe_out4(NLW_inst_probe_out4_UNCONNECTED[0]),
.probe_out40(NLW_inst_probe_out40_UNCONNECTED[0]),
.probe_out41(NLW_inst_probe_out41_UNCONNECTED[0]),
.probe_out42(NLW_inst_probe_out42_UNCONNECTED[0]),
.probe_out43(NLW_inst_probe_out43_UNCONNECTED[0]),
.probe_out44(NLW_inst_probe_out44_UNCONNECTED[0]),
.probe_out45(NLW_inst_probe_out45_UNCONNECTED[0]),
.probe_out46(NLW_inst_probe_out46_UNCONNECTED[0]),
.probe_out47(NLW_inst_probe_out47_UNCONNECTED[0]),
.probe_out48(NLW_inst_probe_out48_UNCONNECTED[0]),
.probe_out49(NLW_inst_probe_out49_UNCONNECTED[0]),
.probe_out5(NLW_inst_probe_out5_UNCONNECTED[0]),
.probe_out50(NLW_inst_probe_out50_UNCONNECTED[0]),
.probe_out51(NLW_inst_probe_out51_UNCONNECTED[0]),
.probe_out52(NLW_inst_probe_out52_UNCONNECTED[0]),
.probe_out53(NLW_inst_probe_out53_UNCONNECTED[0]),
.probe_out54(NLW_inst_probe_out54_UNCONNECTED[0]),
.probe_out55(NLW_inst_probe_out55_UNCONNECTED[0]),
.probe_out56(NLW_inst_probe_out56_UNCONNECTED[0]),
.probe_out57(NLW_inst_probe_out57_UNCONNECTED[0]),
.probe_out58(NLW_inst_probe_out58_UNCONNECTED[0]),
.probe_out59(NLW_inst_probe_out59_UNCONNECTED[0]),
.probe_out6(NLW_inst_probe_out6_UNCONNECTED[0]),
.probe_out60(NLW_inst_probe_out60_UNCONNECTED[0]),
.probe_out61(NLW_inst_probe_out61_UNCONNECTED[0]),
.probe_out62(NLW_inst_probe_out62_UNCONNECTED[0]),
.probe_out63(NLW_inst_probe_out63_UNCONNECTED[0]),
.probe_out64(NLW_inst_probe_out64_UNCONNECTED[0]),
.probe_out65(NLW_inst_probe_out65_UNCONNECTED[0]),
.probe_out66(NLW_inst_probe_out66_UNCONNECTED[0]),
.probe_out67(NLW_inst_probe_out67_UNCONNECTED[0]),
.probe_out68(NLW_inst_probe_out68_UNCONNECTED[0]),
.probe_out69(NLW_inst_probe_out69_UNCONNECTED[0]),
.probe_out7(NLW_inst_probe_out7_UNCONNECTED[0]),
.probe_out70(NLW_inst_probe_out70_UNCONNECTED[0]),
.probe_out71(NLW_inst_probe_out71_UNCONNECTED[0]),
.probe_out72(NLW_inst_probe_out72_UNCONNECTED[0]),
.probe_out73(NLW_inst_probe_out73_UNCONNECTED[0]),
.probe_out74(NLW_inst_probe_out74_UNCONNECTED[0]),
.probe_out75(NLW_inst_probe_out75_UNCONNECTED[0]),
.probe_out76(NLW_inst_probe_out76_UNCONNECTED[0]),
.probe_out77(NLW_inst_probe_out77_UNCONNECTED[0]),
.probe_out78(NLW_inst_probe_out78_UNCONNECTED[0]),
.probe_out79(NLW_inst_probe_out79_UNCONNECTED[0]),
.probe_out8(NLW_inst_probe_out8_UNCONNECTED[0]),
.probe_out80(NLW_inst_probe_out80_UNCONNECTED[0]),
.probe_out81(NLW_inst_probe_out81_UNCONNECTED[0]),
.probe_out82(NLW_inst_probe_out82_UNCONNECTED[0]),
.probe_out83(NLW_inst_probe_out83_UNCONNECTED[0]),
.probe_out84(NLW_inst_probe_out84_UNCONNECTED[0]),
.probe_out85(NLW_inst_probe_out85_UNCONNECTED[0]),
.probe_out86(NLW_inst_probe_out86_UNCONNECTED[0]),
.probe_out87(NLW_inst_probe_out87_UNCONNECTED[0]),
.probe_out88(NLW_inst_probe_out88_UNCONNECTED[0]),
.probe_out89(NLW_inst_probe_out89_UNCONNECTED[0]),
.probe_out9(NLW_inst_probe_out9_UNCONNECTED[0]),
.probe_out90(NLW_inst_probe_out90_UNCONNECTED[0]),
.probe_out91(NLW_inst_probe_out91_UNCONNECTED[0]),
.probe_out92(NLW_inst_probe_out92_UNCONNECTED[0]),
.probe_out93(NLW_inst_probe_out93_UNCONNECTED[0]),
.probe_out94(NLW_inst_probe_out94_UNCONNECTED[0]),
.probe_out95(NLW_inst_probe_out95_UNCONNECTED[0]),
.probe_out96(NLW_inst_probe_out96_UNCONNECTED[0]),
.probe_out97(NLW_inst_probe_out97_UNCONNECTED[0]),
.probe_out98(NLW_inst_probe_out98_UNCONNECTED[0]),
.probe_out99(NLW_inst_probe_out99_UNCONNECTED[0]),
.sl_iport0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.sl_oport0(NLW_inst_sl_oport0_UNCONNECTED[16:0]));
endmodule
(* ORIG_REF_NAME = "vio_v3_0_13_decoder" *)
module vio_0_vio_v3_0_13_decoder
(s_drdy_i,
\wr_en_reg[4]_0 ,
\wr_en_reg[4]_1 ,
\wr_en_reg[4]_2 ,
E,
s_do_i,
s_rst_o,
Q,
out,
s_daddr_o,
s_dwe_o,
s_den_o,
\Bus_Data_out_reg[11] );
output s_drdy_i;
output \wr_en_reg[4]_0 ;
output \wr_en_reg[4]_1 ;
output \wr_en_reg[4]_2 ;
output [0:0]E;
output [15:0]s_do_i;
input s_rst_o;
input [15:0]Q;
input out;
input [16:0]s_daddr_o;
input s_dwe_o;
input s_den_o;
input [11:0]\Bus_Data_out_reg[11] ;
wire [11:0]\Bus_Data_out_reg[11] ;
wire [0:0]E;
wire Hold_probe_in;
wire [15:0]Q;
wire clear_int;
wire committ_int;
wire [15:0]data_info_probe_in__67;
wire int_cnt_rst;
wire out;
wire [15:0]probe_out_modified;
wire rd_en_p1;
wire rd_en_p2;
wire [16:0]s_daddr_o;
wire s_den_o;
wire [15:0]s_do_i;
wire s_drdy_i;
wire s_dwe_o;
wire s_rst_o;
wire wr_control_reg;
wire \wr_en[2]_i_1_n_0 ;
wire \wr_en[2]_i_2_n_0 ;
wire \wr_en[4]_i_1_n_0 ;
wire \wr_en[4]_i_6_n_0 ;
wire \wr_en_reg[4]_0 ;
wire \wr_en_reg[4]_1 ;
wire \wr_en_reg[4]_2 ;
wire wr_probe_out_modified;
wire [2:0]xsdb_addr_2_0_p1;
wire [2:0]xsdb_addr_2_0_p2;
wire xsdb_addr_8_p1;
wire xsdb_addr_8_p2;
wire xsdb_drdy_i_1_n_0;
wire xsdb_rd;
wire xsdb_wr;
LUT6 #(
.INIT(64'hAF00AF000FC000C0))
\Bus_data_out[0]_i_1
(.I0(\Bus_Data_out_reg[11] [0]),
.I1(probe_out_modified[0]),
.I2(xsdb_addr_2_0_p2[2]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(committ_int),
.I5(xsdb_addr_2_0_p2[0]),
.O(data_info_probe_in__67[0]));
LUT5 #(
.INIT(32'h88200020))
\Bus_data_out[10]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[0]),
.I2(probe_out_modified[10]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(\Bus_Data_out_reg[11] [10]),
.O(data_info_probe_in__67[10]));
LUT5 #(
.INIT(32'h88200020))
\Bus_data_out[11]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[0]),
.I2(probe_out_modified[11]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(\Bus_Data_out_reg[11] [11]),
.O(data_info_probe_in__67[11]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h0020))
\Bus_data_out[12]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[1]),
.I2(probe_out_modified[12]),
.I3(xsdb_addr_2_0_p2[0]),
.O(data_info_probe_in__67[12]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'h0020))
\Bus_data_out[13]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[1]),
.I2(probe_out_modified[13]),
.I3(xsdb_addr_2_0_p2[0]),
.O(data_info_probe_in__67[13]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'h0020))
\Bus_data_out[14]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[1]),
.I2(probe_out_modified[14]),
.I3(xsdb_addr_2_0_p2[0]),
.O(data_info_probe_in__67[14]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h0020))
\Bus_data_out[15]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[1]),
.I2(probe_out_modified[15]),
.I3(xsdb_addr_2_0_p2[0]),
.O(data_info_probe_in__67[15]));
LUT6 #(
.INIT(64'hA0000FC0A00000C0))
\Bus_data_out[1]_i_1
(.I0(\Bus_Data_out_reg[11] [1]),
.I1(probe_out_modified[1]),
.I2(xsdb_addr_2_0_p2[2]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(xsdb_addr_2_0_p2[0]),
.I5(clear_int),
.O(data_info_probe_in__67[1]));
LUT6 #(
.INIT(64'hA0A000000F00CFCF))
\Bus_data_out[2]_i_1
(.I0(\Bus_Data_out_reg[11] [2]),
.I1(probe_out_modified[2]),
.I2(xsdb_addr_2_0_p2[2]),
.I3(int_cnt_rst),
.I4(xsdb_addr_2_0_p2[1]),
.I5(xsdb_addr_2_0_p2[0]),
.O(data_info_probe_in__67[2]));
LUT5 #(
.INIT(32'h88200020))
\Bus_data_out[3]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[0]),
.I2(probe_out_modified[3]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(\Bus_Data_out_reg[11] [3]),
.O(data_info_probe_in__67[3]));
LUT5 #(
.INIT(32'h88200020))
\Bus_data_out[4]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[0]),
.I2(probe_out_modified[4]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(\Bus_Data_out_reg[11] [4]),
.O(data_info_probe_in__67[4]));
LUT5 #(
.INIT(32'h88200020))
\Bus_data_out[5]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[0]),
.I2(probe_out_modified[5]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(\Bus_Data_out_reg[11] [5]),
.O(data_info_probe_in__67[5]));
LUT5 #(
.INIT(32'h88200020))
\Bus_data_out[6]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[0]),
.I2(probe_out_modified[6]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(\Bus_Data_out_reg[11] [6]),
.O(data_info_probe_in__67[6]));
LUT5 #(
.INIT(32'h88200020))
\Bus_data_out[7]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[0]),
.I2(probe_out_modified[7]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(\Bus_Data_out_reg[11] [7]),
.O(data_info_probe_in__67[7]));
LUT5 #(
.INIT(32'h88200020))
\Bus_data_out[8]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[0]),
.I2(probe_out_modified[8]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(\Bus_Data_out_reg[11] [8]),
.O(data_info_probe_in__67[8]));
LUT5 #(
.INIT(32'h88200020))
\Bus_data_out[9]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[0]),
.I2(probe_out_modified[9]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(\Bus_Data_out_reg[11] [9]),
.O(data_info_probe_in__67[9]));
FDRE \Bus_data_out_reg[0]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[0]),
.Q(s_do_i[0]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[10]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[10]),
.Q(s_do_i[10]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[11]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[11]),
.Q(s_do_i[11]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[12]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[12]),
.Q(s_do_i[12]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[13]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[13]),
.Q(s_do_i[13]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[14]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[14]),
.Q(s_do_i[14]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[15]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[15]),
.Q(s_do_i[15]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[1]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[1]),
.Q(s_do_i[1]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[2]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[2]),
.Q(s_do_i[2]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[3]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[3]),
.Q(s_do_i[3]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[4]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[4]),
.Q(s_do_i[4]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[5]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[5]),
.Q(s_do_i[5]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[6]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[6]),
.Q(s_do_i[6]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[7]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[7]),
.Q(s_do_i[7]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[8]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[8]),
.Q(s_do_i[8]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[9]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[9]),
.Q(s_do_i[9]),
.R(xsdb_addr_8_p2));
FDRE Hold_probe_in_reg
(.C(out),
.CE(wr_control_reg),
.D(Q[3]),
.Q(Hold_probe_in),
.R(s_rst_o));
FDRE clear_int_reg
(.C(out),
.CE(wr_control_reg),
.D(Q[1]),
.Q(clear_int),
.R(s_rst_o));
FDRE committ_int_reg
(.C(out),
.CE(wr_control_reg),
.D(Q[0]),
.Q(committ_int),
.R(s_rst_o));
FDRE int_cnt_rst_reg
(.C(out),
.CE(wr_control_reg),
.D(Q[2]),
.Q(int_cnt_rst),
.R(s_rst_o));
LUT1 #(
.INIT(2'h1))
\probe_in_reg[3]_i_1
(.I0(Hold_probe_in),
.O(E));
FDRE \probe_out_modified_reg[0]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[0]),
.Q(probe_out_modified[0]),
.R(clear_int));
FDRE \probe_out_modified_reg[10]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[10]),
.Q(probe_out_modified[10]),
.R(clear_int));
FDRE \probe_out_modified_reg[11]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[11]),
.Q(probe_out_modified[11]),
.R(clear_int));
FDRE \probe_out_modified_reg[12]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[12]),
.Q(probe_out_modified[12]),
.R(clear_int));
FDRE \probe_out_modified_reg[13]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[13]),
.Q(probe_out_modified[13]),
.R(clear_int));
FDRE \probe_out_modified_reg[14]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[14]),
.Q(probe_out_modified[14]),
.R(clear_int));
FDRE \probe_out_modified_reg[15]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[15]),
.Q(probe_out_modified[15]),
.R(clear_int));
FDRE \probe_out_modified_reg[1]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[1]),
.Q(probe_out_modified[1]),
.R(clear_int));
FDRE \probe_out_modified_reg[2]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[2]),
.Q(probe_out_modified[2]),
.R(clear_int));
FDRE \probe_out_modified_reg[3]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[3]),
.Q(probe_out_modified[3]),
.R(clear_int));
FDRE \probe_out_modified_reg[4]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[4]),
.Q(probe_out_modified[4]),
.R(clear_int));
FDRE \probe_out_modified_reg[5]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[5]),
.Q(probe_out_modified[5]),
.R(clear_int));
FDRE \probe_out_modified_reg[6]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[6]),
.Q(probe_out_modified[6]),
.R(clear_int));
FDRE \probe_out_modified_reg[7]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[7]),
.Q(probe_out_modified[7]),
.R(clear_int));
FDRE \probe_out_modified_reg[8]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[8]),
.Q(probe_out_modified[8]),
.R(clear_int));
FDRE \probe_out_modified_reg[9]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[9]),
.Q(probe_out_modified[9]),
.R(clear_int));
LUT2 #(
.INIT(4'h2))
rd_en_p1_i_1
(.I0(s_den_o),
.I1(s_dwe_o),
.O(xsdb_rd));
FDRE rd_en_p1_reg
(.C(out),
.CE(1'b1),
.D(xsdb_rd),
.Q(rd_en_p1),
.R(s_rst_o));
FDRE rd_en_p2_reg
(.C(out),
.CE(1'b1),
.D(rd_en_p1),
.Q(rd_en_p2),
.R(s_rst_o));
LUT6 #(
.INIT(64'h0000000000000002))
\wr_en[2]_i_1
(.I0(xsdb_wr),
.I1(s_daddr_o[2]),
.I2(\wr_en_reg[4]_0 ),
.I3(\wr_en_reg[4]_2 ),
.I4(\wr_en_reg[4]_1 ),
.I5(\wr_en[2]_i_2_n_0 ),
.O(\wr_en[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'hB))
\wr_en[2]_i_2
(.I0(s_daddr_o[0]),
.I1(s_daddr_o[1]),
.O(\wr_en[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000020000))
\wr_en[4]_i_1
(.I0(xsdb_wr),
.I1(\wr_en_reg[4]_0 ),
.I2(\wr_en_reg[4]_2 ),
.I3(\wr_en_reg[4]_1 ),
.I4(s_daddr_o[2]),
.I5(\wr_en[4]_i_6_n_0 ),
.O(\wr_en[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h8))
\wr_en[4]_i_2
(.I0(s_den_o),
.I1(s_dwe_o),
.O(xsdb_wr));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\wr_en[4]_i_3
(.I0(s_daddr_o[15]),
.I1(s_daddr_o[16]),
.I2(s_daddr_o[13]),
.I3(s_daddr_o[14]),
.I4(s_daddr_o[4]),
.I5(s_daddr_o[3]),
.O(\wr_en_reg[4]_0 ));
LUT4 #(
.INIT(16'hFFFE))
\wr_en[4]_i_4
(.I0(s_daddr_o[6]),
.I1(s_daddr_o[5]),
.I2(s_daddr_o[8]),
.I3(s_daddr_o[7]),
.O(\wr_en_reg[4]_2 ));
LUT4 #(
.INIT(16'hFFFE))
\wr_en[4]_i_5
(.I0(s_daddr_o[10]),
.I1(s_daddr_o[9]),
.I2(s_daddr_o[12]),
.I3(s_daddr_o[11]),
.O(\wr_en_reg[4]_1 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'hE))
\wr_en[4]_i_6
(.I0(s_daddr_o[0]),
.I1(s_daddr_o[1]),
.O(\wr_en[4]_i_6_n_0 ));
FDRE \wr_en_reg[2]
(.C(out),
.CE(1'b1),
.D(\wr_en[2]_i_1_n_0 ),
.Q(wr_control_reg),
.R(1'b0));
FDRE \wr_en_reg[4]
(.C(out),
.CE(1'b1),
.D(\wr_en[4]_i_1_n_0 ),
.Q(wr_probe_out_modified),
.R(1'b0));
FDRE \xsdb_addr_2_0_p1_reg[0]
(.C(out),
.CE(1'b1),
.D(s_daddr_o[0]),
.Q(xsdb_addr_2_0_p1[0]),
.R(1'b0));
FDRE \xsdb_addr_2_0_p1_reg[1]
(.C(out),
.CE(1'b1),
.D(s_daddr_o[1]),
.Q(xsdb_addr_2_0_p1[1]),
.R(1'b0));
FDRE \xsdb_addr_2_0_p1_reg[2]
(.C(out),
.CE(1'b1),
.D(s_daddr_o[2]),
.Q(xsdb_addr_2_0_p1[2]),
.R(1'b0));
FDRE \xsdb_addr_2_0_p2_reg[0]
(.C(out),
.CE(1'b1),
.D(xsdb_addr_2_0_p1[0]),
.Q(xsdb_addr_2_0_p2[0]),
.R(1'b0));
FDRE \xsdb_addr_2_0_p2_reg[1]
(.C(out),
.CE(1'b1),
.D(xsdb_addr_2_0_p1[1]),
.Q(xsdb_addr_2_0_p2[1]),
.R(1'b0));
FDRE \xsdb_addr_2_0_p2_reg[2]
(.C(out),
.CE(1'b1),
.D(xsdb_addr_2_0_p1[2]),
.Q(xsdb_addr_2_0_p2[2]),
.R(1'b0));
FDRE xsdb_addr_8_p1_reg
(.C(out),
.CE(1'b1),
.D(s_daddr_o[8]),
.Q(xsdb_addr_8_p1),
.R(1'b0));
FDRE xsdb_addr_8_p2_reg
(.C(out),
.CE(1'b1),
.D(xsdb_addr_8_p1),
.Q(xsdb_addr_8_p2),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hF8))
xsdb_drdy_i_1
(.I0(s_dwe_o),
.I1(s_den_o),
.I2(rd_en_p2),
.O(xsdb_drdy_i_1_n_0));
FDRE xsdb_drdy_reg
(.C(out),
.CE(1'b1),
.D(xsdb_drdy_i_1_n_0),
.Q(s_drdy_i),
.R(s_rst_o));
endmodule
(* ORIG_REF_NAME = "vio_v3_0_13_probe_in_one" *)
module vio_0_vio_v3_0_13_probe_in_one
(Q,
out,
\wr_en[4]_i_3 ,
\wr_en[4]_i_4 ,
\wr_en[4]_i_5 ,
s_daddr_o,
s_dwe_o,
s_den_o,
E,
D,
clk,
s_rst_o);
output [11:0]Q;
input out;
input \wr_en[4]_i_3 ;
input \wr_en[4]_i_4 ;
input \wr_en[4]_i_5 ;
input [2:0]s_daddr_o;
input s_dwe_o;
input s_den_o;
input [0:0]E;
input [3:0]D;
input clk;
input s_rst_o;
wire [3:0]D;
wire \DECODER_INST/rd_en_int_7 ;
wire [0:0]E;
wire [11:0]Q;
wire Read_int;
wire Read_int_i_2_n_0;
wire clk;
(* async_reg = "true" *) wire [3:0]data_int_sync1;
(* async_reg = "true" *) wire [3:0]data_int_sync2;
wire \dn_activity[0]_i_1_n_0 ;
wire \dn_activity[1]_i_1_n_0 ;
wire \dn_activity[2]_i_1_n_0 ;
wire \dn_activity[3]_i_1_n_0 ;
wire \dn_activity_reg_n_0_[0] ;
wire \dn_activity_reg_n_0_[3] ;
wire out;
wire p_6_in;
wire p_9_in;
(* DONT_TOUCH *) wire [3:0]probe_in_reg;
(* MAX_FANOUT = "200" *) (* RTL_MAX_FANOUT = "found" *) wire read_done;
wire read_done_i_1_n_0;
wire [2:0]s_daddr_o;
wire s_den_o;
wire s_dwe_o;
wire s_rst_o;
wire \up_activity[0]_i_1_n_0 ;
wire \up_activity[1]_i_1_n_0 ;
wire \up_activity[2]_i_1_n_0 ;
wire \up_activity[3]_i_1_n_0 ;
wire \up_activity_reg_n_0_[0] ;
wire \up_activity_reg_n_0_[1] ;
wire \up_activity_reg_n_0_[2] ;
wire \up_activity_reg_n_0_[3] ;
wire \wr_en[4]_i_3 ;
wire \wr_en[4]_i_4 ;
wire \wr_en[4]_i_5 ;
FDRE \Bus_Data_out_reg[0]
(.C(out),
.CE(1'b1),
.D(data_int_sync2[0]),
.Q(Q[0]),
.R(1'b0));
FDRE \Bus_Data_out_reg[10]
(.C(out),
.CE(1'b1),
.D(p_9_in),
.Q(Q[10]),
.R(1'b0));
FDRE \Bus_Data_out_reg[11]
(.C(out),
.CE(1'b1),
.D(\dn_activity_reg_n_0_[3] ),
.Q(Q[11]),
.R(1'b0));
FDRE \Bus_Data_out_reg[1]
(.C(out),
.CE(1'b1),
.D(data_int_sync2[1]),
.Q(Q[1]),
.R(1'b0));
FDRE \Bus_Data_out_reg[2]
(.C(out),
.CE(1'b1),
.D(data_int_sync2[2]),
.Q(Q[2]),
.R(1'b0));
FDRE \Bus_Data_out_reg[3]
(.C(out),
.CE(1'b1),
.D(data_int_sync2[3]),
.Q(Q[3]),
.R(1'b0));
FDRE \Bus_Data_out_reg[4]
(.C(out),
.CE(1'b1),
.D(\up_activity_reg_n_0_[0] ),
.Q(Q[4]),
.R(1'b0));
FDRE \Bus_Data_out_reg[5]
(.C(out),
.CE(1'b1),
.D(\up_activity_reg_n_0_[1] ),
.Q(Q[5]),
.R(1'b0));
FDRE \Bus_Data_out_reg[6]
(.C(out),
.CE(1'b1),
.D(\up_activity_reg_n_0_[2] ),
.Q(Q[6]),
.R(1'b0));
FDRE \Bus_Data_out_reg[7]
(.C(out),
.CE(1'b1),
.D(\up_activity_reg_n_0_[3] ),
.Q(Q[7]),
.R(1'b0));
FDRE \Bus_Data_out_reg[8]
(.C(out),
.CE(1'b1),
.D(\dn_activity_reg_n_0_[0] ),
.Q(Q[8]),
.R(1'b0));
FDRE \Bus_Data_out_reg[9]
(.C(out),
.CE(1'b1),
.D(p_6_in),
.Q(Q[9]),
.R(1'b0));
LUT4 #(
.INIT(16'h0002))
Read_int_i_1
(.I0(Read_int_i_2_n_0),
.I1(\wr_en[4]_i_3 ),
.I2(\wr_en[4]_i_4 ),
.I3(\wr_en[4]_i_5 ),
.O(\DECODER_INST/rd_en_int_7 ));
LUT5 #(
.INIT(32'h00800000))
Read_int_i_2
(.I0(s_daddr_o[0]),
.I1(s_daddr_o[1]),
.I2(s_daddr_o[2]),
.I3(s_dwe_o),
.I4(s_den_o),
.O(Read_int_i_2_n_0));
FDRE Read_int_reg
(.C(out),
.CE(1'b1),
.D(\DECODER_INST/rd_en_int_7 ),
.Q(Read_int),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\data_int_sync1_reg[0]
(.C(out),
.CE(1'b1),
.D(probe_in_reg[0]),
.Q(data_int_sync1[0]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\data_int_sync1_reg[1]
(.C(out),
.CE(1'b1),
.D(probe_in_reg[1]),
.Q(data_int_sync1[1]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\data_int_sync1_reg[2]
(.C(out),
.CE(1'b1),
.D(probe_in_reg[2]),
.Q(data_int_sync1[2]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\data_int_sync1_reg[3]
(.C(out),
.CE(1'b1),
.D(probe_in_reg[3]),
.Q(data_int_sync1[3]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\data_int_sync2_reg[0]
(.C(out),
.CE(1'b1),
.D(data_int_sync1[0]),
.Q(data_int_sync2[0]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\data_int_sync2_reg[1]
(.C(out),
.CE(1'b1),
.D(data_int_sync1[1]),
.Q(data_int_sync2[1]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\data_int_sync2_reg[2]
(.C(out),
.CE(1'b1),
.D(data_int_sync1[2]),
.Q(data_int_sync2[2]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\data_int_sync2_reg[3]
(.C(out),
.CE(1'b1),
.D(data_int_sync1[3]),
.Q(data_int_sync2[3]),
.R(1'b0));
LUT3 #(
.INIT(8'hBA))
\dn_activity[0]_i_1
(.I0(\dn_activity_reg_n_0_[0] ),
.I1(data_int_sync1[0]),
.I2(data_int_sync2[0]),
.O(\dn_activity[0]_i_1_n_0 ));
LUT3 #(
.INIT(8'hBA))
\dn_activity[1]_i_1
(.I0(p_6_in),
.I1(data_int_sync1[1]),
.I2(data_int_sync2[1]),
.O(\dn_activity[1]_i_1_n_0 ));
LUT3 #(
.INIT(8'hBA))
\dn_activity[2]_i_1
(.I0(p_9_in),
.I1(data_int_sync1[2]),
.I2(data_int_sync2[2]),
.O(\dn_activity[2]_i_1_n_0 ));
LUT3 #(
.INIT(8'hBA))
\dn_activity[3]_i_1
(.I0(\dn_activity_reg_n_0_[3] ),
.I1(data_int_sync1[3]),
.I2(data_int_sync2[3]),
.O(\dn_activity[3]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\dn_activity_reg[0]
(.C(out),
.CE(1'b1),
.D(\dn_activity[0]_i_1_n_0 ),
.Q(\dn_activity_reg_n_0_[0] ),
.R(read_done));
FDRE #(
.INIT(1'b0))
\dn_activity_reg[1]
(.C(out),
.CE(1'b1),
.D(\dn_activity[1]_i_1_n_0 ),
.Q(p_6_in),
.R(read_done));
FDRE #(
.INIT(1'b0))
\dn_activity_reg[2]
(.C(out),
.CE(1'b1),
.D(\dn_activity[2]_i_1_n_0 ),
.Q(p_9_in),
.R(read_done));
FDRE #(
.INIT(1'b0))
\dn_activity_reg[3]
(.C(out),
.CE(1'b1),
.D(\dn_activity[3]_i_1_n_0 ),
.Q(\dn_activity_reg_n_0_[3] ),
.R(read_done));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\probe_in_reg_reg[0]
(.C(clk),
.CE(E),
.D(D[0]),
.Q(probe_in_reg[0]),
.R(1'b0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\probe_in_reg_reg[1]
(.C(clk),
.CE(E),
.D(D[1]),
.Q(probe_in_reg[1]),
.R(1'b0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\probe_in_reg_reg[2]
(.C(clk),
.CE(E),
.D(D[2]),
.Q(probe_in_reg[2]),
.R(1'b0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\probe_in_reg_reg[3]
(.C(clk),
.CE(E),
.D(D[3]),
.Q(probe_in_reg[3]),
.R(1'b0));
LUT3 #(
.INIT(8'h02))
read_done_i_1
(.I0(Read_int),
.I1(read_done),
.I2(s_rst_o),
.O(read_done_i_1_n_0));
(* RTL_MAX_FANOUT = "found" *)
FDRE read_done_reg
(.C(out),
.CE(1'b1),
.D(read_done_i_1_n_0),
.Q(read_done),
.R(1'b0));
LUT3 #(
.INIT(8'hBA))
\up_activity[0]_i_1
(.I0(\up_activity_reg_n_0_[0] ),
.I1(data_int_sync2[0]),
.I2(data_int_sync1[0]),
.O(\up_activity[0]_i_1_n_0 ));
LUT3 #(
.INIT(8'hBA))
\up_activity[1]_i_1
(.I0(\up_activity_reg_n_0_[1] ),
.I1(data_int_sync2[1]),
.I2(data_int_sync1[1]),
.O(\up_activity[1]_i_1_n_0 ));
LUT3 #(
.INIT(8'hBA))
\up_activity[2]_i_1
(.I0(\up_activity_reg_n_0_[2] ),
.I1(data_int_sync2[2]),
.I2(data_int_sync1[2]),
.O(\up_activity[2]_i_1_n_0 ));
LUT3 #(
.INIT(8'hBA))
\up_activity[3]_i_1
(.I0(\up_activity_reg_n_0_[3] ),
.I1(data_int_sync2[3]),
.I2(data_int_sync1[3]),
.O(\up_activity[3]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\up_activity_reg[0]
(.C(out),
.CE(1'b1),
.D(\up_activity[0]_i_1_n_0 ),
.Q(\up_activity_reg_n_0_[0] ),
.R(read_done));
FDRE #(
.INIT(1'b0))
\up_activity_reg[1]
(.C(out),
.CE(1'b1),
.D(\up_activity[1]_i_1_n_0 ),
.Q(\up_activity_reg_n_0_[1] ),
.R(read_done));
FDRE #(
.INIT(1'b0))
\up_activity_reg[2]
(.C(out),
.CE(1'b1),
.D(\up_activity[2]_i_1_n_0 ),
.Q(\up_activity_reg_n_0_[2] ),
.R(read_done));
FDRE #(
.INIT(1'b0))
\up_activity_reg[3]
(.C(out),
.CE(1'b1),
.D(\up_activity[3]_i_1_n_0 ),
.Q(\up_activity_reg_n_0_[3] ),
.R(read_done));
endmodule
(* C_BUILD_REVISION = "0" *) (* C_BUS_ADDR_WIDTH = "17" *) (* C_BUS_DATA_WIDTH = "16" *)
(* C_CORE_INFO1 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_CORE_INFO2 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_CORE_MAJOR_VER = "2" *)
(* C_CORE_MINOR_ALPHA_VER = "97" *) (* C_CORE_MINOR_VER = "0" *) (* C_CORE_TYPE = "2" *)
(* C_CSE_DRV_VER = "1" *) (* C_EN_PROBE_IN_ACTIVITY = "1" *) (* C_EN_SYNCHRONIZATION = "1" *)
(* C_MAJOR_VERSION = "2013" *) (* C_MAX_NUM_PROBE = "256" *) (* C_MAX_WIDTH_PER_PROBE = "256" *)
(* C_MINOR_VERSION = "1" *) (* C_NEXT_SLAVE = "0" *) (* C_NUM_PROBE_IN = "4" *)
(* C_NUM_PROBE_OUT = "0" *) (* C_PIPE_IFACE = "0" *) (* C_PROBE_IN0_WIDTH = "1" *)
(* C_PROBE_IN100_WIDTH = "1" *) (* C_PROBE_IN101_WIDTH = "1" *) (* C_PROBE_IN102_WIDTH = "1" *)
(* C_PROBE_IN103_WIDTH = "1" *) (* C_PROBE_IN104_WIDTH = "1" *) (* C_PROBE_IN105_WIDTH = "1" *)
(* C_PROBE_IN106_WIDTH = "1" *) (* C_PROBE_IN107_WIDTH = "1" *) (* C_PROBE_IN108_WIDTH = "1" *)
(* C_PROBE_IN109_WIDTH = "1" *) (* C_PROBE_IN10_WIDTH = "1" *) (* C_PROBE_IN110_WIDTH = "1" *)
(* C_PROBE_IN111_WIDTH = "1" *) (* C_PROBE_IN112_WIDTH = "1" *) (* C_PROBE_IN113_WIDTH = "1" *)
(* C_PROBE_IN114_WIDTH = "1" *) (* C_PROBE_IN115_WIDTH = "1" *) (* C_PROBE_IN116_WIDTH = "1" *)
(* C_PROBE_IN117_WIDTH = "1" *) (* C_PROBE_IN118_WIDTH = "1" *) (* C_PROBE_IN119_WIDTH = "1" *)
(* C_PROBE_IN11_WIDTH = "1" *) (* C_PROBE_IN120_WIDTH = "1" *) (* C_PROBE_IN121_WIDTH = "1" *)
(* C_PROBE_IN122_WIDTH = "1" *) (* C_PROBE_IN123_WIDTH = "1" *) (* C_PROBE_IN124_WIDTH = "1" *)
(* C_PROBE_IN125_WIDTH = "1" *) (* C_PROBE_IN126_WIDTH = "1" *) (* C_PROBE_IN127_WIDTH = "1" *)
(* C_PROBE_IN128_WIDTH = "1" *) (* C_PROBE_IN129_WIDTH = "1" *) (* C_PROBE_IN12_WIDTH = "1" *)
(* C_PROBE_IN130_WIDTH = "1" *) (* C_PROBE_IN131_WIDTH = "1" *) (* C_PROBE_IN132_WIDTH = "1" *)
(* C_PROBE_IN133_WIDTH = "1" *) (* C_PROBE_IN134_WIDTH = "1" *) (* C_PROBE_IN135_WIDTH = "1" *)
(* C_PROBE_IN136_WIDTH = "1" *) (* C_PROBE_IN137_WIDTH = "1" *) (* C_PROBE_IN138_WIDTH = "1" *)
(* C_PROBE_IN139_WIDTH = "1" *) (* C_PROBE_IN13_WIDTH = "1" *) (* C_PROBE_IN140_WIDTH = "1" *)
(* C_PROBE_IN141_WIDTH = "1" *) (* C_PROBE_IN142_WIDTH = "1" *) (* C_PROBE_IN143_WIDTH = "1" *)
(* C_PROBE_IN144_WIDTH = "1" *) (* C_PROBE_IN145_WIDTH = "1" *) (* C_PROBE_IN146_WIDTH = "1" *)
(* C_PROBE_IN147_WIDTH = "1" *) (* C_PROBE_IN148_WIDTH = "1" *) (* C_PROBE_IN149_WIDTH = "1" *)
(* C_PROBE_IN14_WIDTH = "1" *) (* C_PROBE_IN150_WIDTH = "1" *) (* C_PROBE_IN151_WIDTH = "1" *)
(* C_PROBE_IN152_WIDTH = "1" *) (* C_PROBE_IN153_WIDTH = "1" *) (* C_PROBE_IN154_WIDTH = "1" *)
(* C_PROBE_IN155_WIDTH = "1" *) (* C_PROBE_IN156_WIDTH = "1" *) (* C_PROBE_IN157_WIDTH = "1" *)
(* C_PROBE_IN158_WIDTH = "1" *) (* C_PROBE_IN159_WIDTH = "1" *) (* C_PROBE_IN15_WIDTH = "1" *)
(* C_PROBE_IN160_WIDTH = "1" *) (* C_PROBE_IN161_WIDTH = "1" *) (* C_PROBE_IN162_WIDTH = "1" *)
(* C_PROBE_IN163_WIDTH = "1" *) (* C_PROBE_IN164_WIDTH = "1" *) (* C_PROBE_IN165_WIDTH = "1" *)
(* C_PROBE_IN166_WIDTH = "1" *) (* C_PROBE_IN167_WIDTH = "1" *) (* C_PROBE_IN168_WIDTH = "1" *)
(* C_PROBE_IN169_WIDTH = "1" *) (* C_PROBE_IN16_WIDTH = "1" *) (* C_PROBE_IN170_WIDTH = "1" *)
(* C_PROBE_IN171_WIDTH = "1" *) (* C_PROBE_IN172_WIDTH = "1" *) (* C_PROBE_IN173_WIDTH = "1" *)
(* C_PROBE_IN174_WIDTH = "1" *) (* C_PROBE_IN175_WIDTH = "1" *) (* C_PROBE_IN176_WIDTH = "1" *)
(* C_PROBE_IN177_WIDTH = "1" *) (* C_PROBE_IN178_WIDTH = "1" *) (* C_PROBE_IN179_WIDTH = "1" *)
(* C_PROBE_IN17_WIDTH = "1" *) (* C_PROBE_IN180_WIDTH = "1" *) (* C_PROBE_IN181_WIDTH = "1" *)
(* C_PROBE_IN182_WIDTH = "1" *) (* C_PROBE_IN183_WIDTH = "1" *) (* C_PROBE_IN184_WIDTH = "1" *)
(* C_PROBE_IN185_WIDTH = "1" *) (* C_PROBE_IN186_WIDTH = "1" *) (* C_PROBE_IN187_WIDTH = "1" *)
(* C_PROBE_IN188_WIDTH = "1" *) (* C_PROBE_IN189_WIDTH = "1" *) (* C_PROBE_IN18_WIDTH = "1" *)
(* C_PROBE_IN190_WIDTH = "1" *) (* C_PROBE_IN191_WIDTH = "1" *) (* C_PROBE_IN192_WIDTH = "1" *)
(* C_PROBE_IN193_WIDTH = "1" *) (* C_PROBE_IN194_WIDTH = "1" *) (* C_PROBE_IN195_WIDTH = "1" *)
(* C_PROBE_IN196_WIDTH = "1" *) (* C_PROBE_IN197_WIDTH = "1" *) (* C_PROBE_IN198_WIDTH = "1" *)
(* C_PROBE_IN199_WIDTH = "1" *) (* C_PROBE_IN19_WIDTH = "1" *) (* C_PROBE_IN1_WIDTH = "1" *)
(* C_PROBE_IN200_WIDTH = "1" *) (* C_PROBE_IN201_WIDTH = "1" *) (* C_PROBE_IN202_WIDTH = "1" *)
(* C_PROBE_IN203_WIDTH = "1" *) (* C_PROBE_IN204_WIDTH = "1" *) (* C_PROBE_IN205_WIDTH = "1" *)
(* C_PROBE_IN206_WIDTH = "1" *) (* C_PROBE_IN207_WIDTH = "1" *) (* C_PROBE_IN208_WIDTH = "1" *)
(* C_PROBE_IN209_WIDTH = "1" *) (* C_PROBE_IN20_WIDTH = "1" *) (* C_PROBE_IN210_WIDTH = "1" *)
(* C_PROBE_IN211_WIDTH = "1" *) (* C_PROBE_IN212_WIDTH = "1" *) (* C_PROBE_IN213_WIDTH = "1" *)
(* C_PROBE_IN214_WIDTH = "1" *) (* C_PROBE_IN215_WIDTH = "1" *) (* C_PROBE_IN216_WIDTH = "1" *)
(* C_PROBE_IN217_WIDTH = "1" *) (* C_PROBE_IN218_WIDTH = "1" *) (* C_PROBE_IN219_WIDTH = "1" *)
(* C_PROBE_IN21_WIDTH = "1" *) (* C_PROBE_IN220_WIDTH = "1" *) (* C_PROBE_IN221_WIDTH = "1" *)
(* C_PROBE_IN222_WIDTH = "1" *) (* C_PROBE_IN223_WIDTH = "1" *) (* C_PROBE_IN224_WIDTH = "1" *)
(* C_PROBE_IN225_WIDTH = "1" *) (* C_PROBE_IN226_WIDTH = "1" *) (* C_PROBE_IN227_WIDTH = "1" *)
(* C_PROBE_IN228_WIDTH = "1" *) (* C_PROBE_IN229_WIDTH = "1" *) (* C_PROBE_IN22_WIDTH = "1" *)
(* C_PROBE_IN230_WIDTH = "1" *) (* C_PROBE_IN231_WIDTH = "1" *) (* C_PROBE_IN232_WIDTH = "1" *)
(* C_PROBE_IN233_WIDTH = "1" *) (* C_PROBE_IN234_WIDTH = "1" *) (* C_PROBE_IN235_WIDTH = "1" *)
(* C_PROBE_IN236_WIDTH = "1" *) (* C_PROBE_IN237_WIDTH = "1" *) (* C_PROBE_IN238_WIDTH = "1" *)
(* C_PROBE_IN239_WIDTH = "1" *) (* C_PROBE_IN23_WIDTH = "1" *) (* C_PROBE_IN240_WIDTH = "1" *)
(* C_PROBE_IN241_WIDTH = "1" *) (* C_PROBE_IN242_WIDTH = "1" *) (* C_PROBE_IN243_WIDTH = "1" *)
(* C_PROBE_IN244_WIDTH = "1" *) (* C_PROBE_IN245_WIDTH = "1" *) (* C_PROBE_IN246_WIDTH = "1" *)
(* C_PROBE_IN247_WIDTH = "1" *) (* C_PROBE_IN248_WIDTH = "1" *) (* C_PROBE_IN249_WIDTH = "1" *)
(* C_PROBE_IN24_WIDTH = "1" *) (* C_PROBE_IN250_WIDTH = "1" *) (* C_PROBE_IN251_WIDTH = "1" *)
(* C_PROBE_IN252_WIDTH = "1" *) (* C_PROBE_IN253_WIDTH = "1" *) (* C_PROBE_IN254_WIDTH = "1" *)
(* C_PROBE_IN255_WIDTH = "1" *) (* C_PROBE_IN25_WIDTH = "1" *) (* C_PROBE_IN26_WIDTH = "1" *)
(* C_PROBE_IN27_WIDTH = "1" *) (* C_PROBE_IN28_WIDTH = "1" *) (* C_PROBE_IN29_WIDTH = "1" *)
(* C_PROBE_IN2_WIDTH = "1" *) (* C_PROBE_IN30_WIDTH = "1" *) (* C_PROBE_IN31_WIDTH = "1" *)
(* C_PROBE_IN32_WIDTH = "1" *) (* C_PROBE_IN33_WIDTH = "1" *) (* C_PROBE_IN34_WIDTH = "1" *)
(* C_PROBE_IN35_WIDTH = "1" *) (* C_PROBE_IN36_WIDTH = "1" *) (* C_PROBE_IN37_WIDTH = "1" *)
(* C_PROBE_IN38_WIDTH = "1" *) (* C_PROBE_IN39_WIDTH = "1" *) (* C_PROBE_IN3_WIDTH = "1" *)
(* C_PROBE_IN40_WIDTH = "1" *) (* C_PROBE_IN41_WIDTH = "1" *) (* C_PROBE_IN42_WIDTH = "1" *)
(* C_PROBE_IN43_WIDTH = "1" *) (* C_PROBE_IN44_WIDTH = "1" *) (* C_PROBE_IN45_WIDTH = "1" *)
(* C_PROBE_IN46_WIDTH = "1" *) (* C_PROBE_IN47_WIDTH = "1" *) (* C_PROBE_IN48_WIDTH = "1" *)
(* C_PROBE_IN49_WIDTH = "1" *) (* C_PROBE_IN4_WIDTH = "1" *) (* C_PROBE_IN50_WIDTH = "1" *)
(* C_PROBE_IN51_WIDTH = "1" *) (* C_PROBE_IN52_WIDTH = "1" *) (* C_PROBE_IN53_WIDTH = "1" *)
(* C_PROBE_IN54_WIDTH = "1" *) (* C_PROBE_IN55_WIDTH = "1" *) (* C_PROBE_IN56_WIDTH = "1" *)
(* C_PROBE_IN57_WIDTH = "1" *) (* C_PROBE_IN58_WIDTH = "1" *) (* C_PROBE_IN59_WIDTH = "1" *)
(* C_PROBE_IN5_WIDTH = "1" *) (* C_PROBE_IN60_WIDTH = "1" *) (* C_PROBE_IN61_WIDTH = "1" *)
(* C_PROBE_IN62_WIDTH = "1" *) (* C_PROBE_IN63_WIDTH = "1" *) (* C_PROBE_IN64_WIDTH = "1" *)
(* C_PROBE_IN65_WIDTH = "1" *) (* C_PROBE_IN66_WIDTH = "1" *) (* C_PROBE_IN67_WIDTH = "1" *)
(* C_PROBE_IN68_WIDTH = "1" *) (* C_PROBE_IN69_WIDTH = "1" *) (* C_PROBE_IN6_WIDTH = "1" *)
(* C_PROBE_IN70_WIDTH = "1" *) (* C_PROBE_IN71_WIDTH = "1" *) (* C_PROBE_IN72_WIDTH = "1" *)
(* C_PROBE_IN73_WIDTH = "1" *) (* C_PROBE_IN74_WIDTH = "1" *) (* C_PROBE_IN75_WIDTH = "1" *)
(* C_PROBE_IN76_WIDTH = "1" *) (* C_PROBE_IN77_WIDTH = "1" *) (* C_PROBE_IN78_WIDTH = "1" *)
(* C_PROBE_IN79_WIDTH = "1" *) (* C_PROBE_IN7_WIDTH = "1" *) (* C_PROBE_IN80_WIDTH = "1" *)
(* C_PROBE_IN81_WIDTH = "1" *) (* C_PROBE_IN82_WIDTH = "1" *) (* C_PROBE_IN83_WIDTH = "1" *)
(* C_PROBE_IN84_WIDTH = "1" *) (* C_PROBE_IN85_WIDTH = "1" *) (* C_PROBE_IN86_WIDTH = "1" *)
(* C_PROBE_IN87_WIDTH = "1" *) (* C_PROBE_IN88_WIDTH = "1" *) (* C_PROBE_IN89_WIDTH = "1" *)
(* C_PROBE_IN8_WIDTH = "1" *) (* C_PROBE_IN90_WIDTH = "1" *) (* C_PROBE_IN91_WIDTH = "1" *)
(* C_PROBE_IN92_WIDTH = "1" *) (* C_PROBE_IN93_WIDTH = "1" *) (* C_PROBE_IN94_WIDTH = "1" *)
(* C_PROBE_IN95_WIDTH = "1" *) (* C_PROBE_IN96_WIDTH = "1" *) (* C_PROBE_IN97_WIDTH = "1" *)
(* C_PROBE_IN98_WIDTH = "1" *) (* C_PROBE_IN99_WIDTH = "1" *) (* C_PROBE_IN9_WIDTH = "1" *)
(* C_PROBE_OUT0_INIT_VAL = "1'b0" *) (* C_PROBE_OUT0_WIDTH = "1" *) (* C_PROBE_OUT100_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT100_WIDTH = "1" *) (* C_PROBE_OUT101_INIT_VAL = "1'b0" *) (* C_PROBE_OUT101_WIDTH = "1" *)
(* C_PROBE_OUT102_INIT_VAL = "1'b0" *) (* C_PROBE_OUT102_WIDTH = "1" *) (* C_PROBE_OUT103_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT103_WIDTH = "1" *) (* C_PROBE_OUT104_INIT_VAL = "1'b0" *) (* C_PROBE_OUT104_WIDTH = "1" *)
(* C_PROBE_OUT105_INIT_VAL = "1'b0" *) (* C_PROBE_OUT105_WIDTH = "1" *) (* C_PROBE_OUT106_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT106_WIDTH = "1" *) (* C_PROBE_OUT107_INIT_VAL = "1'b0" *) (* C_PROBE_OUT107_WIDTH = "1" *)
(* C_PROBE_OUT108_INIT_VAL = "1'b0" *) (* C_PROBE_OUT108_WIDTH = "1" *) (* C_PROBE_OUT109_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT109_WIDTH = "1" *) (* C_PROBE_OUT10_INIT_VAL = "1'b0" *) (* C_PROBE_OUT10_WIDTH = "1" *)
(* C_PROBE_OUT110_INIT_VAL = "1'b0" *) (* C_PROBE_OUT110_WIDTH = "1" *) (* C_PROBE_OUT111_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT111_WIDTH = "1" *) (* C_PROBE_OUT112_INIT_VAL = "1'b0" *) (* C_PROBE_OUT112_WIDTH = "1" *)
(* C_PROBE_OUT113_INIT_VAL = "1'b0" *) (* C_PROBE_OUT113_WIDTH = "1" *) (* C_PROBE_OUT114_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT114_WIDTH = "1" *) (* C_PROBE_OUT115_INIT_VAL = "1'b0" *) (* C_PROBE_OUT115_WIDTH = "1" *)
(* C_PROBE_OUT116_INIT_VAL = "1'b0" *) (* C_PROBE_OUT116_WIDTH = "1" *) (* C_PROBE_OUT117_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT117_WIDTH = "1" *) (* C_PROBE_OUT118_INIT_VAL = "1'b0" *) (* C_PROBE_OUT118_WIDTH = "1" *)
(* C_PROBE_OUT119_INIT_VAL = "1'b0" *) (* C_PROBE_OUT119_WIDTH = "1" *) (* C_PROBE_OUT11_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT11_WIDTH = "1" *) (* C_PROBE_OUT120_INIT_VAL = "1'b0" *) (* C_PROBE_OUT120_WIDTH = "1" *)
(* C_PROBE_OUT121_INIT_VAL = "1'b0" *) (* C_PROBE_OUT121_WIDTH = "1" *) (* C_PROBE_OUT122_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT122_WIDTH = "1" *) (* C_PROBE_OUT123_INIT_VAL = "1'b0" *) (* C_PROBE_OUT123_WIDTH = "1" *)
(* C_PROBE_OUT124_INIT_VAL = "1'b0" *) (* C_PROBE_OUT124_WIDTH = "1" *) (* C_PROBE_OUT125_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT125_WIDTH = "1" *) (* C_PROBE_OUT126_INIT_VAL = "1'b0" *) (* C_PROBE_OUT126_WIDTH = "1" *)
(* C_PROBE_OUT127_INIT_VAL = "1'b0" *) (* C_PROBE_OUT127_WIDTH = "1" *) (* C_PROBE_OUT128_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT128_WIDTH = "1" *) (* C_PROBE_OUT129_INIT_VAL = "1'b0" *) (* C_PROBE_OUT129_WIDTH = "1" *)
(* C_PROBE_OUT12_INIT_VAL = "1'b0" *) (* C_PROBE_OUT12_WIDTH = "1" *) (* C_PROBE_OUT130_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT130_WIDTH = "1" *) (* C_PROBE_OUT131_INIT_VAL = "1'b0" *) (* C_PROBE_OUT131_WIDTH = "1" *)
(* C_PROBE_OUT132_INIT_VAL = "1'b0" *) (* C_PROBE_OUT132_WIDTH = "1" *) (* C_PROBE_OUT133_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT133_WIDTH = "1" *) (* C_PROBE_OUT134_INIT_VAL = "1'b0" *) (* C_PROBE_OUT134_WIDTH = "1" *)
(* C_PROBE_OUT135_INIT_VAL = "1'b0" *) (* C_PROBE_OUT135_WIDTH = "1" *) (* C_PROBE_OUT136_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT136_WIDTH = "1" *) (* C_PROBE_OUT137_INIT_VAL = "1'b0" *) (* C_PROBE_OUT137_WIDTH = "1" *)
(* C_PROBE_OUT138_INIT_VAL = "1'b0" *) (* C_PROBE_OUT138_WIDTH = "1" *) (* C_PROBE_OUT139_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT139_WIDTH = "1" *) (* C_PROBE_OUT13_INIT_VAL = "1'b0" *) (* C_PROBE_OUT13_WIDTH = "1" *)
(* C_PROBE_OUT140_INIT_VAL = "1'b0" *) (* C_PROBE_OUT140_WIDTH = "1" *) (* C_PROBE_OUT141_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT141_WIDTH = "1" *) (* C_PROBE_OUT142_INIT_VAL = "1'b0" *) (* C_PROBE_OUT142_WIDTH = "1" *)
(* C_PROBE_OUT143_INIT_VAL = "1'b0" *) (* C_PROBE_OUT143_WIDTH = "1" *) (* C_PROBE_OUT144_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT144_WIDTH = "1" *) (* C_PROBE_OUT145_INIT_VAL = "1'b0" *) (* C_PROBE_OUT145_WIDTH = "1" *)
(* C_PROBE_OUT146_INIT_VAL = "1'b0" *) (* C_PROBE_OUT146_WIDTH = "1" *) (* C_PROBE_OUT147_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT147_WIDTH = "1" *) (* C_PROBE_OUT148_INIT_VAL = "1'b0" *) (* C_PROBE_OUT148_WIDTH = "1" *)
(* C_PROBE_OUT149_INIT_VAL = "1'b0" *) (* C_PROBE_OUT149_WIDTH = "1" *) (* C_PROBE_OUT14_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT14_WIDTH = "1" *) (* C_PROBE_OUT150_INIT_VAL = "1'b0" *) (* C_PROBE_OUT150_WIDTH = "1" *)
(* C_PROBE_OUT151_INIT_VAL = "1'b0" *) (* C_PROBE_OUT151_WIDTH = "1" *) (* C_PROBE_OUT152_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT152_WIDTH = "1" *) (* C_PROBE_OUT153_INIT_VAL = "1'b0" *) (* C_PROBE_OUT153_WIDTH = "1" *)
(* C_PROBE_OUT154_INIT_VAL = "1'b0" *) (* C_PROBE_OUT154_WIDTH = "1" *) (* C_PROBE_OUT155_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT155_WIDTH = "1" *) (* C_PROBE_OUT156_INIT_VAL = "1'b0" *) (* C_PROBE_OUT156_WIDTH = "1" *)
(* C_PROBE_OUT157_INIT_VAL = "1'b0" *) (* C_PROBE_OUT157_WIDTH = "1" *) (* C_PROBE_OUT158_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT158_WIDTH = "1" *) (* C_PROBE_OUT159_INIT_VAL = "1'b0" *) (* C_PROBE_OUT159_WIDTH = "1" *)
(* C_PROBE_OUT15_INIT_VAL = "1'b0" *) (* C_PROBE_OUT15_WIDTH = "1" *) (* C_PROBE_OUT160_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT160_WIDTH = "1" *) (* C_PROBE_OUT161_INIT_VAL = "1'b0" *) (* C_PROBE_OUT161_WIDTH = "1" *)
(* C_PROBE_OUT162_INIT_VAL = "1'b0" *) (* C_PROBE_OUT162_WIDTH = "1" *) (* C_PROBE_OUT163_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT163_WIDTH = "1" *) (* C_PROBE_OUT164_INIT_VAL = "1'b0" *) (* C_PROBE_OUT164_WIDTH = "1" *)
(* C_PROBE_OUT165_INIT_VAL = "1'b0" *) (* C_PROBE_OUT165_WIDTH = "1" *) (* C_PROBE_OUT166_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT166_WIDTH = "1" *) (* C_PROBE_OUT167_INIT_VAL = "1'b0" *) (* C_PROBE_OUT167_WIDTH = "1" *)
(* C_PROBE_OUT168_INIT_VAL = "1'b0" *) (* C_PROBE_OUT168_WIDTH = "1" *) (* C_PROBE_OUT169_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT169_WIDTH = "1" *) (* C_PROBE_OUT16_INIT_VAL = "1'b0" *) (* C_PROBE_OUT16_WIDTH = "1" *)
(* C_PROBE_OUT170_INIT_VAL = "1'b0" *) (* C_PROBE_OUT170_WIDTH = "1" *) (* C_PROBE_OUT171_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT171_WIDTH = "1" *) (* C_PROBE_OUT172_INIT_VAL = "1'b0" *) (* C_PROBE_OUT172_WIDTH = "1" *)
(* C_PROBE_OUT173_INIT_VAL = "1'b0" *) (* C_PROBE_OUT173_WIDTH = "1" *) (* C_PROBE_OUT174_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT174_WIDTH = "1" *) (* C_PROBE_OUT175_INIT_VAL = "1'b0" *) (* C_PROBE_OUT175_WIDTH = "1" *)
(* C_PROBE_OUT176_INIT_VAL = "1'b0" *) (* C_PROBE_OUT176_WIDTH = "1" *) (* C_PROBE_OUT177_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT177_WIDTH = "1" *) (* C_PROBE_OUT178_INIT_VAL = "1'b0" *) (* C_PROBE_OUT178_WIDTH = "1" *)
(* C_PROBE_OUT179_INIT_VAL = "1'b0" *) (* C_PROBE_OUT179_WIDTH = "1" *) (* C_PROBE_OUT17_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT17_WIDTH = "1" *) (* C_PROBE_OUT180_INIT_VAL = "1'b0" *) (* C_PROBE_OUT180_WIDTH = "1" *)
(* C_PROBE_OUT181_INIT_VAL = "1'b0" *) (* C_PROBE_OUT181_WIDTH = "1" *) (* C_PROBE_OUT182_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT182_WIDTH = "1" *) (* C_PROBE_OUT183_INIT_VAL = "1'b0" *) (* C_PROBE_OUT183_WIDTH = "1" *)
(* C_PROBE_OUT184_INIT_VAL = "1'b0" *) (* C_PROBE_OUT184_WIDTH = "1" *) (* C_PROBE_OUT185_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT185_WIDTH = "1" *) (* C_PROBE_OUT186_INIT_VAL = "1'b0" *) (* C_PROBE_OUT186_WIDTH = "1" *)
(* C_PROBE_OUT187_INIT_VAL = "1'b0" *) (* C_PROBE_OUT187_WIDTH = "1" *) (* C_PROBE_OUT188_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT188_WIDTH = "1" *) (* C_PROBE_OUT189_INIT_VAL = "1'b0" *) (* C_PROBE_OUT189_WIDTH = "1" *)
(* C_PROBE_OUT18_INIT_VAL = "1'b0" *) (* C_PROBE_OUT18_WIDTH = "1" *) (* C_PROBE_OUT190_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT190_WIDTH = "1" *) (* C_PROBE_OUT191_INIT_VAL = "1'b0" *) (* C_PROBE_OUT191_WIDTH = "1" *)
(* C_PROBE_OUT192_INIT_VAL = "1'b0" *) (* C_PROBE_OUT192_WIDTH = "1" *) (* C_PROBE_OUT193_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT193_WIDTH = "1" *) (* C_PROBE_OUT194_INIT_VAL = "1'b0" *) (* C_PROBE_OUT194_WIDTH = "1" *)
(* C_PROBE_OUT195_INIT_VAL = "1'b0" *) (* C_PROBE_OUT195_WIDTH = "1" *) (* C_PROBE_OUT196_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT196_WIDTH = "1" *) (* C_PROBE_OUT197_INIT_VAL = "1'b0" *) (* C_PROBE_OUT197_WIDTH = "1" *)
(* C_PROBE_OUT198_INIT_VAL = "1'b0" *) (* C_PROBE_OUT198_WIDTH = "1" *) (* C_PROBE_OUT199_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT199_WIDTH = "1" *) (* C_PROBE_OUT19_INIT_VAL = "1'b0" *) (* C_PROBE_OUT19_WIDTH = "1" *)
(* C_PROBE_OUT1_INIT_VAL = "1'b0" *) (* C_PROBE_OUT1_WIDTH = "1" *) (* C_PROBE_OUT200_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT200_WIDTH = "1" *) (* C_PROBE_OUT201_INIT_VAL = "1'b0" *) (* C_PROBE_OUT201_WIDTH = "1" *)
(* C_PROBE_OUT202_INIT_VAL = "1'b0" *) (* C_PROBE_OUT202_WIDTH = "1" *) (* C_PROBE_OUT203_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT203_WIDTH = "1" *) (* C_PROBE_OUT204_INIT_VAL = "1'b0" *) (* C_PROBE_OUT204_WIDTH = "1" *)
(* C_PROBE_OUT205_INIT_VAL = "1'b0" *) (* C_PROBE_OUT205_WIDTH = "1" *) (* C_PROBE_OUT206_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT206_WIDTH = "1" *) (* C_PROBE_OUT207_INIT_VAL = "1'b0" *) (* C_PROBE_OUT207_WIDTH = "1" *)
(* C_PROBE_OUT208_INIT_VAL = "1'b0" *) (* C_PROBE_OUT208_WIDTH = "1" *) (* C_PROBE_OUT209_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT209_WIDTH = "1" *) (* C_PROBE_OUT20_INIT_VAL = "1'b0" *) (* C_PROBE_OUT20_WIDTH = "1" *)
(* C_PROBE_OUT210_INIT_VAL = "1'b0" *) (* C_PROBE_OUT210_WIDTH = "1" *) (* C_PROBE_OUT211_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT211_WIDTH = "1" *) (* C_PROBE_OUT212_INIT_VAL = "1'b0" *) (* C_PROBE_OUT212_WIDTH = "1" *)
(* C_PROBE_OUT213_INIT_VAL = "1'b0" *) (* C_PROBE_OUT213_WIDTH = "1" *) (* C_PROBE_OUT214_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT214_WIDTH = "1" *) (* C_PROBE_OUT215_INIT_VAL = "1'b0" *) (* C_PROBE_OUT215_WIDTH = "1" *)
(* C_PROBE_OUT216_INIT_VAL = "1'b0" *) (* C_PROBE_OUT216_WIDTH = "1" *) (* C_PROBE_OUT217_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT217_WIDTH = "1" *) (* C_PROBE_OUT218_INIT_VAL = "1'b0" *) (* C_PROBE_OUT218_WIDTH = "1" *)
(* C_PROBE_OUT219_INIT_VAL = "1'b0" *) (* C_PROBE_OUT219_WIDTH = "1" *) (* C_PROBE_OUT21_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT21_WIDTH = "1" *) (* C_PROBE_OUT220_INIT_VAL = "1'b0" *) (* C_PROBE_OUT220_WIDTH = "1" *)
(* C_PROBE_OUT221_INIT_VAL = "1'b0" *) (* C_PROBE_OUT221_WIDTH = "1" *) (* C_PROBE_OUT222_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT222_WIDTH = "1" *) (* C_PROBE_OUT223_INIT_VAL = "1'b0" *) (* C_PROBE_OUT223_WIDTH = "1" *)
(* C_PROBE_OUT224_INIT_VAL = "1'b0" *) (* C_PROBE_OUT224_WIDTH = "1" *) (* C_PROBE_OUT225_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT225_WIDTH = "1" *) (* C_PROBE_OUT226_INIT_VAL = "1'b0" *) (* C_PROBE_OUT226_WIDTH = "1" *)
(* C_PROBE_OUT227_INIT_VAL = "1'b0" *) (* C_PROBE_OUT227_WIDTH = "1" *) (* C_PROBE_OUT228_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT228_WIDTH = "1" *) (* C_PROBE_OUT229_INIT_VAL = "1'b0" *) (* C_PROBE_OUT229_WIDTH = "1" *)
(* C_PROBE_OUT22_INIT_VAL = "1'b0" *) (* C_PROBE_OUT22_WIDTH = "1" *) (* C_PROBE_OUT230_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT230_WIDTH = "1" *) (* C_PROBE_OUT231_INIT_VAL = "1'b0" *) (* C_PROBE_OUT231_WIDTH = "1" *)
(* C_PROBE_OUT232_INIT_VAL = "1'b0" *) (* C_PROBE_OUT232_WIDTH = "1" *) (* C_PROBE_OUT233_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT233_WIDTH = "1" *) (* C_PROBE_OUT234_INIT_VAL = "1'b0" *) (* C_PROBE_OUT234_WIDTH = "1" *)
(* C_PROBE_OUT235_INIT_VAL = "1'b0" *) (* C_PROBE_OUT235_WIDTH = "1" *) (* C_PROBE_OUT236_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT236_WIDTH = "1" *) (* C_PROBE_OUT237_INIT_VAL = "1'b0" *) (* C_PROBE_OUT237_WIDTH = "1" *)
(* C_PROBE_OUT238_INIT_VAL = "1'b0" *) (* C_PROBE_OUT238_WIDTH = "1" *) (* C_PROBE_OUT239_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT239_WIDTH = "1" *) (* C_PROBE_OUT23_INIT_VAL = "1'b0" *) (* C_PROBE_OUT23_WIDTH = "1" *)
(* C_PROBE_OUT240_INIT_VAL = "1'b0" *) (* C_PROBE_OUT240_WIDTH = "1" *) (* C_PROBE_OUT241_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT241_WIDTH = "1" *) (* C_PROBE_OUT242_INIT_VAL = "1'b0" *) (* C_PROBE_OUT242_WIDTH = "1" *)
(* C_PROBE_OUT243_INIT_VAL = "1'b0" *) (* C_PROBE_OUT243_WIDTH = "1" *) (* C_PROBE_OUT244_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT244_WIDTH = "1" *) (* C_PROBE_OUT245_INIT_VAL = "1'b0" *) (* C_PROBE_OUT245_WIDTH = "1" *)
(* C_PROBE_OUT246_INIT_VAL = "1'b0" *) (* C_PROBE_OUT246_WIDTH = "1" *) (* C_PROBE_OUT247_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT247_WIDTH = "1" *) (* C_PROBE_OUT248_INIT_VAL = "1'b0" *) (* C_PROBE_OUT248_WIDTH = "1" *)
(* C_PROBE_OUT249_INIT_VAL = "1'b0" *) (* C_PROBE_OUT249_WIDTH = "1" *) (* C_PROBE_OUT24_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT24_WIDTH = "1" *) (* C_PROBE_OUT250_INIT_VAL = "1'b0" *) (* C_PROBE_OUT250_WIDTH = "1" *)
(* C_PROBE_OUT251_INIT_VAL = "1'b0" *) (* C_PROBE_OUT251_WIDTH = "1" *) (* C_PROBE_OUT252_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT252_WIDTH = "1" *) (* C_PROBE_OUT253_INIT_VAL = "1'b0" *) (* C_PROBE_OUT253_WIDTH = "1" *)
(* C_PROBE_OUT254_INIT_VAL = "1'b0" *) (* C_PROBE_OUT254_WIDTH = "1" *) (* C_PROBE_OUT255_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT255_WIDTH = "1" *) (* C_PROBE_OUT25_INIT_VAL = "1'b0" *) (* C_PROBE_OUT25_WIDTH = "1" *)
(* C_PROBE_OUT26_INIT_VAL = "1'b0" *) (* C_PROBE_OUT26_WIDTH = "1" *) (* C_PROBE_OUT27_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT27_WIDTH = "1" *) (* C_PROBE_OUT28_INIT_VAL = "1'b0" *) (* C_PROBE_OUT28_WIDTH = "1" *)
(* C_PROBE_OUT29_INIT_VAL = "1'b0" *) (* C_PROBE_OUT29_WIDTH = "1" *) (* C_PROBE_OUT2_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT2_WIDTH = "1" *) (* C_PROBE_OUT30_INIT_VAL = "1'b0" *) (* C_PROBE_OUT30_WIDTH = "1" *)
(* C_PROBE_OUT31_INIT_VAL = "1'b0" *) (* C_PROBE_OUT31_WIDTH = "1" *) (* C_PROBE_OUT32_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT32_WIDTH = "1" *) (* C_PROBE_OUT33_INIT_VAL = "1'b0" *) (* C_PROBE_OUT33_WIDTH = "1" *)
(* C_PROBE_OUT34_INIT_VAL = "1'b0" *) (* C_PROBE_OUT34_WIDTH = "1" *) (* C_PROBE_OUT35_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT35_WIDTH = "1" *) (* C_PROBE_OUT36_INIT_VAL = "1'b0" *) (* C_PROBE_OUT36_WIDTH = "1" *)
(* C_PROBE_OUT37_INIT_VAL = "1'b0" *) (* C_PROBE_OUT37_WIDTH = "1" *) (* C_PROBE_OUT38_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT38_WIDTH = "1" *) (* C_PROBE_OUT39_INIT_VAL = "1'b0" *) (* C_PROBE_OUT39_WIDTH = "1" *)
(* C_PROBE_OUT3_INIT_VAL = "1'b0" *) (* C_PROBE_OUT3_WIDTH = "1" *) (* C_PROBE_OUT40_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT40_WIDTH = "1" *) (* C_PROBE_OUT41_INIT_VAL = "1'b0" *) (* C_PROBE_OUT41_WIDTH = "1" *)
(* C_PROBE_OUT42_INIT_VAL = "1'b0" *) (* C_PROBE_OUT42_WIDTH = "1" *) (* C_PROBE_OUT43_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT43_WIDTH = "1" *) (* C_PROBE_OUT44_INIT_VAL = "1'b0" *) (* C_PROBE_OUT44_WIDTH = "1" *)
(* C_PROBE_OUT45_INIT_VAL = "1'b0" *) (* C_PROBE_OUT45_WIDTH = "1" *) (* C_PROBE_OUT46_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT46_WIDTH = "1" *) (* C_PROBE_OUT47_INIT_VAL = "1'b0" *) (* C_PROBE_OUT47_WIDTH = "1" *)
(* C_PROBE_OUT48_INIT_VAL = "1'b0" *) (* C_PROBE_OUT48_WIDTH = "1" *) (* C_PROBE_OUT49_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT49_WIDTH = "1" *) (* C_PROBE_OUT4_INIT_VAL = "1'b0" *) (* C_PROBE_OUT4_WIDTH = "1" *)
(* C_PROBE_OUT50_INIT_VAL = "1'b0" *) (* C_PROBE_OUT50_WIDTH = "1" *) (* C_PROBE_OUT51_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT51_WIDTH = "1" *) (* C_PROBE_OUT52_INIT_VAL = "1'b0" *) (* C_PROBE_OUT52_WIDTH = "1" *)
(* C_PROBE_OUT53_INIT_VAL = "1'b0" *) (* C_PROBE_OUT53_WIDTH = "1" *) (* C_PROBE_OUT54_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT54_WIDTH = "1" *) (* C_PROBE_OUT55_INIT_VAL = "1'b0" *) (* C_PROBE_OUT55_WIDTH = "1" *)
(* C_PROBE_OUT56_INIT_VAL = "1'b0" *) (* C_PROBE_OUT56_WIDTH = "1" *) (* C_PROBE_OUT57_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT57_WIDTH = "1" *) (* C_PROBE_OUT58_INIT_VAL = "1'b0" *) (* C_PROBE_OUT58_WIDTH = "1" *)
(* C_PROBE_OUT59_INIT_VAL = "1'b0" *) (* C_PROBE_OUT59_WIDTH = "1" *) (* C_PROBE_OUT5_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT5_WIDTH = "1" *) (* C_PROBE_OUT60_INIT_VAL = "1'b0" *) (* C_PROBE_OUT60_WIDTH = "1" *)
(* C_PROBE_OUT61_INIT_VAL = "1'b0" *) (* C_PROBE_OUT61_WIDTH = "1" *) (* C_PROBE_OUT62_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT62_WIDTH = "1" *) (* C_PROBE_OUT63_INIT_VAL = "1'b0" *) (* C_PROBE_OUT63_WIDTH = "1" *)
(* C_PROBE_OUT64_INIT_VAL = "1'b0" *) (* C_PROBE_OUT64_WIDTH = "1" *) (* C_PROBE_OUT65_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT65_WIDTH = "1" *) (* C_PROBE_OUT66_INIT_VAL = "1'b0" *) (* C_PROBE_OUT66_WIDTH = "1" *)
(* C_PROBE_OUT67_INIT_VAL = "1'b0" *) (* C_PROBE_OUT67_WIDTH = "1" *) (* C_PROBE_OUT68_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT68_WIDTH = "1" *) (* C_PROBE_OUT69_INIT_VAL = "1'b0" *) (* C_PROBE_OUT69_WIDTH = "1" *)
(* C_PROBE_OUT6_INIT_VAL = "1'b0" *) (* C_PROBE_OUT6_WIDTH = "1" *) (* C_PROBE_OUT70_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT70_WIDTH = "1" *) (* C_PROBE_OUT71_INIT_VAL = "1'b0" *) (* C_PROBE_OUT71_WIDTH = "1" *)
(* C_PROBE_OUT72_INIT_VAL = "1'b0" *) (* C_PROBE_OUT72_WIDTH = "1" *) (* C_PROBE_OUT73_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT73_WIDTH = "1" *) (* C_PROBE_OUT74_INIT_VAL = "1'b0" *) (* C_PROBE_OUT74_WIDTH = "1" *)
(* C_PROBE_OUT75_INIT_VAL = "1'b0" *) (* C_PROBE_OUT75_WIDTH = "1" *) (* C_PROBE_OUT76_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT76_WIDTH = "1" *) (* C_PROBE_OUT77_INIT_VAL = "1'b0" *) (* C_PROBE_OUT77_WIDTH = "1" *)
(* C_PROBE_OUT78_INIT_VAL = "1'b0" *) (* C_PROBE_OUT78_WIDTH = "1" *) (* C_PROBE_OUT79_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT79_WIDTH = "1" *) (* C_PROBE_OUT7_INIT_VAL = "1'b0" *) (* C_PROBE_OUT7_WIDTH = "1" *)
(* C_PROBE_OUT80_INIT_VAL = "1'b0" *) (* C_PROBE_OUT80_WIDTH = "1" *) (* C_PROBE_OUT81_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT81_WIDTH = "1" *) (* C_PROBE_OUT82_INIT_VAL = "1'b0" *) (* C_PROBE_OUT82_WIDTH = "1" *)
(* C_PROBE_OUT83_INIT_VAL = "1'b0" *) (* C_PROBE_OUT83_WIDTH = "1" *) (* C_PROBE_OUT84_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT84_WIDTH = "1" *) (* C_PROBE_OUT85_INIT_VAL = "1'b0" *) (* C_PROBE_OUT85_WIDTH = "1" *)
(* C_PROBE_OUT86_INIT_VAL = "1'b0" *) (* C_PROBE_OUT86_WIDTH = "1" *) (* C_PROBE_OUT87_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT87_WIDTH = "1" *) (* C_PROBE_OUT88_INIT_VAL = "1'b0" *) (* C_PROBE_OUT88_WIDTH = "1" *)
(* C_PROBE_OUT89_INIT_VAL = "1'b0" *) (* C_PROBE_OUT89_WIDTH = "1" *) (* C_PROBE_OUT8_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT8_WIDTH = "1" *) (* C_PROBE_OUT90_INIT_VAL = "1'b0" *) (* C_PROBE_OUT90_WIDTH = "1" *)
(* C_PROBE_OUT91_INIT_VAL = "1'b0" *) (* C_PROBE_OUT91_WIDTH = "1" *) (* C_PROBE_OUT92_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT92_WIDTH = "1" *) (* C_PROBE_OUT93_INIT_VAL = "1'b0" *) (* C_PROBE_OUT93_WIDTH = "1" *)
(* C_PROBE_OUT94_INIT_VAL = "1'b0" *) (* C_PROBE_OUT94_WIDTH = "1" *) (* C_PROBE_OUT95_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT95_WIDTH = "1" *) (* C_PROBE_OUT96_INIT_VAL = "1'b0" *) (* C_PROBE_OUT96_WIDTH = "1" *)
(* C_PROBE_OUT97_INIT_VAL = "1'b0" *) (* C_PROBE_OUT97_WIDTH = "1" *) (* C_PROBE_OUT98_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT98_WIDTH = "1" *) (* C_PROBE_OUT99_INIT_VAL = "1'b0" *) (* C_PROBE_OUT99_WIDTH = "1" *)
(* C_PROBE_OUT9_INIT_VAL = "1'b0" *) (* C_PROBE_OUT9_WIDTH = "1" *) (* C_USE_TEST_REG = "1" *)
(* C_XDEVICEFAMILY = "kintex7" *) (* C_XLNX_HW_PROBE_INFO = "DEFAULT" *) (* C_XSDB_SLAVE_TYPE = "33" *)
(* DowngradeIPIdentifiedWarnings = "yes" *) (* LC_HIGH_BIT_POS_PROBE_OUT0 = "16'b0000000000000000" *) (* LC_HIGH_BIT_POS_PROBE_OUT1 = "16'b0000000000000001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT10 = "16'b0000000000001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT100 = "16'b0000000001100100" *) (* LC_HIGH_BIT_POS_PROBE_OUT101 = "16'b0000000001100101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT102 = "16'b0000000001100110" *) (* LC_HIGH_BIT_POS_PROBE_OUT103 = "16'b0000000001100111" *) (* LC_HIGH_BIT_POS_PROBE_OUT104 = "16'b0000000001101000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT105 = "16'b0000000001101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT106 = "16'b0000000001101010" *) (* LC_HIGH_BIT_POS_PROBE_OUT107 = "16'b0000000001101011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT108 = "16'b0000000001101100" *) (* LC_HIGH_BIT_POS_PROBE_OUT109 = "16'b0000000001101101" *) (* LC_HIGH_BIT_POS_PROBE_OUT11 = "16'b0000000000001011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT110 = "16'b0000000001101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT111 = "16'b0000000001101111" *) (* LC_HIGH_BIT_POS_PROBE_OUT112 = "16'b0000000001110000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT113 = "16'b0000000001110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT114 = "16'b0000000001110010" *) (* LC_HIGH_BIT_POS_PROBE_OUT115 = "16'b0000000001110011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT116 = "16'b0000000001110100" *) (* LC_HIGH_BIT_POS_PROBE_OUT117 = "16'b0000000001110101" *) (* LC_HIGH_BIT_POS_PROBE_OUT118 = "16'b0000000001110110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT119 = "16'b0000000001110111" *) (* LC_HIGH_BIT_POS_PROBE_OUT12 = "16'b0000000000001100" *) (* LC_HIGH_BIT_POS_PROBE_OUT120 = "16'b0000000001111000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT121 = "16'b0000000001111001" *) (* LC_HIGH_BIT_POS_PROBE_OUT122 = "16'b0000000001111010" *) (* LC_HIGH_BIT_POS_PROBE_OUT123 = "16'b0000000001111011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT124 = "16'b0000000001111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT125 = "16'b0000000001111101" *) (* LC_HIGH_BIT_POS_PROBE_OUT126 = "16'b0000000001111110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT127 = "16'b0000000001111111" *) (* LC_HIGH_BIT_POS_PROBE_OUT128 = "16'b0000000010000000" *) (* LC_HIGH_BIT_POS_PROBE_OUT129 = "16'b0000000010000001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT13 = "16'b0000000000001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT130 = "16'b0000000010000010" *) (* LC_HIGH_BIT_POS_PROBE_OUT131 = "16'b0000000010000011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT132 = "16'b0000000010000100" *) (* LC_HIGH_BIT_POS_PROBE_OUT133 = "16'b0000000010000101" *) (* LC_HIGH_BIT_POS_PROBE_OUT134 = "16'b0000000010000110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT135 = "16'b0000000010000111" *) (* LC_HIGH_BIT_POS_PROBE_OUT136 = "16'b0000000010001000" *) (* LC_HIGH_BIT_POS_PROBE_OUT137 = "16'b0000000010001001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT138 = "16'b0000000010001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT139 = "16'b0000000010001011" *) (* LC_HIGH_BIT_POS_PROBE_OUT14 = "16'b0000000000001110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT140 = "16'b0000000010001100" *) (* LC_HIGH_BIT_POS_PROBE_OUT141 = "16'b0000000010001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT142 = "16'b0000000010001110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT143 = "16'b0000000010001111" *) (* LC_HIGH_BIT_POS_PROBE_OUT144 = "16'b0000000010010000" *) (* LC_HIGH_BIT_POS_PROBE_OUT145 = "16'b0000000010010001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT146 = "16'b0000000010010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT147 = "16'b0000000010010011" *) (* LC_HIGH_BIT_POS_PROBE_OUT148 = "16'b0000000010010100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT149 = "16'b0000000010010101" *) (* LC_HIGH_BIT_POS_PROBE_OUT15 = "16'b0000000000001111" *) (* LC_HIGH_BIT_POS_PROBE_OUT150 = "16'b0000000010010110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT151 = "16'b0000000010010111" *) (* LC_HIGH_BIT_POS_PROBE_OUT152 = "16'b0000000010011000" *) (* LC_HIGH_BIT_POS_PROBE_OUT153 = "16'b0000000010011001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT154 = "16'b0000000010011010" *) (* LC_HIGH_BIT_POS_PROBE_OUT155 = "16'b0000000010011011" *) (* LC_HIGH_BIT_POS_PROBE_OUT156 = "16'b0000000010011100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT157 = "16'b0000000010011101" *) (* LC_HIGH_BIT_POS_PROBE_OUT158 = "16'b0000000010011110" *) (* LC_HIGH_BIT_POS_PROBE_OUT159 = "16'b0000000010011111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT16 = "16'b0000000000010000" *) (* LC_HIGH_BIT_POS_PROBE_OUT160 = "16'b0000000010100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT161 = "16'b0000000010100001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT162 = "16'b0000000010100010" *) (* LC_HIGH_BIT_POS_PROBE_OUT163 = "16'b0000000010100011" *) (* LC_HIGH_BIT_POS_PROBE_OUT164 = "16'b0000000010100100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT165 = "16'b0000000010100101" *) (* LC_HIGH_BIT_POS_PROBE_OUT166 = "16'b0000000010100110" *) (* LC_HIGH_BIT_POS_PROBE_OUT167 = "16'b0000000010100111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT168 = "16'b0000000010101000" *) (* LC_HIGH_BIT_POS_PROBE_OUT169 = "16'b0000000010101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT17 = "16'b0000000000010001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT170 = "16'b0000000010101010" *) (* LC_HIGH_BIT_POS_PROBE_OUT171 = "16'b0000000010101011" *) (* LC_HIGH_BIT_POS_PROBE_OUT172 = "16'b0000000010101100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT173 = "16'b0000000010101101" *) (* LC_HIGH_BIT_POS_PROBE_OUT174 = "16'b0000000010101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT175 = "16'b0000000010101111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT176 = "16'b0000000010110000" *) (* LC_HIGH_BIT_POS_PROBE_OUT177 = "16'b0000000010110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT178 = "16'b0000000010110010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT179 = "16'b0000000010110011" *) (* LC_HIGH_BIT_POS_PROBE_OUT18 = "16'b0000000000010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT180 = "16'b0000000010110100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT181 = "16'b0000000010110101" *) (* LC_HIGH_BIT_POS_PROBE_OUT182 = "16'b0000000010110110" *) (* LC_HIGH_BIT_POS_PROBE_OUT183 = "16'b0000000010110111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT184 = "16'b0000000010111000" *) (* LC_HIGH_BIT_POS_PROBE_OUT185 = "16'b0000000010111001" *) (* LC_HIGH_BIT_POS_PROBE_OUT186 = "16'b0000000010111010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT187 = "16'b0000000010111011" *) (* LC_HIGH_BIT_POS_PROBE_OUT188 = "16'b0000000010111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT189 = "16'b0000000010111101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT19 = "16'b0000000000010011" *) (* LC_HIGH_BIT_POS_PROBE_OUT190 = "16'b0000000010111110" *) (* LC_HIGH_BIT_POS_PROBE_OUT191 = "16'b0000000010111111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT192 = "16'b0000000011000000" *) (* LC_HIGH_BIT_POS_PROBE_OUT193 = "16'b0000000011000001" *) (* LC_HIGH_BIT_POS_PROBE_OUT194 = "16'b0000000011000010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT195 = "16'b0000000011000011" *) (* LC_HIGH_BIT_POS_PROBE_OUT196 = "16'b0000000011000100" *) (* LC_HIGH_BIT_POS_PROBE_OUT197 = "16'b0000000011000101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT198 = "16'b0000000011000110" *) (* LC_HIGH_BIT_POS_PROBE_OUT199 = "16'b0000000011000111" *) (* LC_HIGH_BIT_POS_PROBE_OUT2 = "16'b0000000000000010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT20 = "16'b0000000000010100" *) (* LC_HIGH_BIT_POS_PROBE_OUT200 = "16'b0000000011001000" *) (* LC_HIGH_BIT_POS_PROBE_OUT201 = "16'b0000000011001001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT202 = "16'b0000000011001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT203 = "16'b0000000011001011" *) (* LC_HIGH_BIT_POS_PROBE_OUT204 = "16'b0000000011001100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT205 = "16'b0000000011001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT206 = "16'b0000000011001110" *) (* LC_HIGH_BIT_POS_PROBE_OUT207 = "16'b0000000011001111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT208 = "16'b0000000011010000" *) (* LC_HIGH_BIT_POS_PROBE_OUT209 = "16'b0000000011010001" *) (* LC_HIGH_BIT_POS_PROBE_OUT21 = "16'b0000000000010101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT210 = "16'b0000000011010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT211 = "16'b0000000011010011" *) (* LC_HIGH_BIT_POS_PROBE_OUT212 = "16'b0000000011010100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT213 = "16'b0000000011010101" *) (* LC_HIGH_BIT_POS_PROBE_OUT214 = "16'b0000000011010110" *) (* LC_HIGH_BIT_POS_PROBE_OUT215 = "16'b0000000011010111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT216 = "16'b0000000011011000" *) (* LC_HIGH_BIT_POS_PROBE_OUT217 = "16'b0000000011011001" *) (* LC_HIGH_BIT_POS_PROBE_OUT218 = "16'b0000000011011010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT219 = "16'b0000000011011011" *) (* LC_HIGH_BIT_POS_PROBE_OUT22 = "16'b0000000000010110" *) (* LC_HIGH_BIT_POS_PROBE_OUT220 = "16'b0000000011011100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT221 = "16'b0000000011011101" *) (* LC_HIGH_BIT_POS_PROBE_OUT222 = "16'b0000000011011110" *) (* LC_HIGH_BIT_POS_PROBE_OUT223 = "16'b0000000011011111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT224 = "16'b0000000011100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT225 = "16'b0000000011100001" *) (* LC_HIGH_BIT_POS_PROBE_OUT226 = "16'b0000000011100010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT227 = "16'b0000000011100011" *) (* LC_HIGH_BIT_POS_PROBE_OUT228 = "16'b0000000011100100" *) (* LC_HIGH_BIT_POS_PROBE_OUT229 = "16'b0000000011100101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT23 = "16'b0000000000010111" *) (* LC_HIGH_BIT_POS_PROBE_OUT230 = "16'b0000000011100110" *) (* LC_HIGH_BIT_POS_PROBE_OUT231 = "16'b0000000011100111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT232 = "16'b0000000011101000" *) (* LC_HIGH_BIT_POS_PROBE_OUT233 = "16'b0000000011101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT234 = "16'b0000000011101010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT235 = "16'b0000000011101011" *) (* LC_HIGH_BIT_POS_PROBE_OUT236 = "16'b0000000011101100" *) (* LC_HIGH_BIT_POS_PROBE_OUT237 = "16'b0000000011101101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT238 = "16'b0000000011101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT239 = "16'b0000000011101111" *) (* LC_HIGH_BIT_POS_PROBE_OUT24 = "16'b0000000000011000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT240 = "16'b0000000011110000" *) (* LC_HIGH_BIT_POS_PROBE_OUT241 = "16'b0000000011110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT242 = "16'b0000000011110010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT243 = "16'b0000000011110011" *) (* LC_HIGH_BIT_POS_PROBE_OUT244 = "16'b0000000011110100" *) (* LC_HIGH_BIT_POS_PROBE_OUT245 = "16'b0000000011110101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT246 = "16'b0000000011110110" *) (* LC_HIGH_BIT_POS_PROBE_OUT247 = "16'b0000000011110111" *) (* LC_HIGH_BIT_POS_PROBE_OUT248 = "16'b0000000011111000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT249 = "16'b0000000011111001" *) (* LC_HIGH_BIT_POS_PROBE_OUT25 = "16'b0000000000011001" *) (* LC_HIGH_BIT_POS_PROBE_OUT250 = "16'b0000000011111010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT251 = "16'b0000000011111011" *) (* LC_HIGH_BIT_POS_PROBE_OUT252 = "16'b0000000011111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT253 = "16'b0000000011111101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT254 = "16'b0000000011111110" *) (* LC_HIGH_BIT_POS_PROBE_OUT255 = "16'b0000000011111111" *) (* LC_HIGH_BIT_POS_PROBE_OUT26 = "16'b0000000000011010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT27 = "16'b0000000000011011" *) (* LC_HIGH_BIT_POS_PROBE_OUT28 = "16'b0000000000011100" *) (* LC_HIGH_BIT_POS_PROBE_OUT29 = "16'b0000000000011101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT3 = "16'b0000000000000011" *) (* LC_HIGH_BIT_POS_PROBE_OUT30 = "16'b0000000000011110" *) (* LC_HIGH_BIT_POS_PROBE_OUT31 = "16'b0000000000011111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT32 = "16'b0000000000100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT33 = "16'b0000000000100001" *) (* LC_HIGH_BIT_POS_PROBE_OUT34 = "16'b0000000000100010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT35 = "16'b0000000000100011" *) (* LC_HIGH_BIT_POS_PROBE_OUT36 = "16'b0000000000100100" *) (* LC_HIGH_BIT_POS_PROBE_OUT37 = "16'b0000000000100101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT38 = "16'b0000000000100110" *) (* LC_HIGH_BIT_POS_PROBE_OUT39 = "16'b0000000000100111" *) (* LC_HIGH_BIT_POS_PROBE_OUT4 = "16'b0000000000000100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT40 = "16'b0000000000101000" *) (* LC_HIGH_BIT_POS_PROBE_OUT41 = "16'b0000000000101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT42 = "16'b0000000000101010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT43 = "16'b0000000000101011" *) (* LC_HIGH_BIT_POS_PROBE_OUT44 = "16'b0000000000101100" *) (* LC_HIGH_BIT_POS_PROBE_OUT45 = "16'b0000000000101101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT46 = "16'b0000000000101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT47 = "16'b0000000000101111" *) (* LC_HIGH_BIT_POS_PROBE_OUT48 = "16'b0000000000110000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT49 = "16'b0000000000110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT5 = "16'b0000000000000101" *) (* LC_HIGH_BIT_POS_PROBE_OUT50 = "16'b0000000000110010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT51 = "16'b0000000000110011" *) (* LC_HIGH_BIT_POS_PROBE_OUT52 = "16'b0000000000110100" *) (* LC_HIGH_BIT_POS_PROBE_OUT53 = "16'b0000000000110101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT54 = "16'b0000000000110110" *) (* LC_HIGH_BIT_POS_PROBE_OUT55 = "16'b0000000000110111" *) (* LC_HIGH_BIT_POS_PROBE_OUT56 = "16'b0000000000111000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT57 = "16'b0000000000111001" *) (* LC_HIGH_BIT_POS_PROBE_OUT58 = "16'b0000000000111010" *) (* LC_HIGH_BIT_POS_PROBE_OUT59 = "16'b0000000000111011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT6 = "16'b0000000000000110" *) (* LC_HIGH_BIT_POS_PROBE_OUT60 = "16'b0000000000111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT61 = "16'b0000000000111101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT62 = "16'b0000000000111110" *) (* LC_HIGH_BIT_POS_PROBE_OUT63 = "16'b0000000000111111" *) (* LC_HIGH_BIT_POS_PROBE_OUT64 = "16'b0000000001000000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT65 = "16'b0000000001000001" *) (* LC_HIGH_BIT_POS_PROBE_OUT66 = "16'b0000000001000010" *) (* LC_HIGH_BIT_POS_PROBE_OUT67 = "16'b0000000001000011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT68 = "16'b0000000001000100" *) (* LC_HIGH_BIT_POS_PROBE_OUT69 = "16'b0000000001000101" *) (* LC_HIGH_BIT_POS_PROBE_OUT7 = "16'b0000000000000111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT70 = "16'b0000000001000110" *) (* LC_HIGH_BIT_POS_PROBE_OUT71 = "16'b0000000001000111" *) (* LC_HIGH_BIT_POS_PROBE_OUT72 = "16'b0000000001001000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT73 = "16'b0000000001001001" *) (* LC_HIGH_BIT_POS_PROBE_OUT74 = "16'b0000000001001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT75 = "16'b0000000001001011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT76 = "16'b0000000001001100" *) (* LC_HIGH_BIT_POS_PROBE_OUT77 = "16'b0000000001001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT78 = "16'b0000000001001110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT79 = "16'b0000000001001111" *) (* LC_HIGH_BIT_POS_PROBE_OUT8 = "16'b0000000000001000" *) (* LC_HIGH_BIT_POS_PROBE_OUT80 = "16'b0000000001010000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT81 = "16'b0000000001010001" *) (* LC_HIGH_BIT_POS_PROBE_OUT82 = "16'b0000000001010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT83 = "16'b0000000001010011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT84 = "16'b0000000001010100" *) (* LC_HIGH_BIT_POS_PROBE_OUT85 = "16'b0000000001010101" *) (* LC_HIGH_BIT_POS_PROBE_OUT86 = "16'b0000000001010110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT87 = "16'b0000000001010111" *) (* LC_HIGH_BIT_POS_PROBE_OUT88 = "16'b0000000001011000" *) (* LC_HIGH_BIT_POS_PROBE_OUT89 = "16'b0000000001011001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT9 = "16'b0000000000001001" *) (* LC_HIGH_BIT_POS_PROBE_OUT90 = "16'b0000000001011010" *) (* LC_HIGH_BIT_POS_PROBE_OUT91 = "16'b0000000001011011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT92 = "16'b0000000001011100" *) (* LC_HIGH_BIT_POS_PROBE_OUT93 = "16'b0000000001011101" *) (* LC_HIGH_BIT_POS_PROBE_OUT94 = "16'b0000000001011110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT95 = "16'b0000000001011111" *) (* LC_HIGH_BIT_POS_PROBE_OUT96 = "16'b0000000001100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT97 = "16'b0000000001100001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT98 = "16'b0000000001100010" *) (* LC_HIGH_BIT_POS_PROBE_OUT99 = "16'b0000000001100011" *) (* LC_LOW_BIT_POS_PROBE_OUT0 = "16'b0000000000000000" *)
(* LC_LOW_BIT_POS_PROBE_OUT1 = "16'b0000000000000001" *) (* LC_LOW_BIT_POS_PROBE_OUT10 = "16'b0000000000001010" *) (* LC_LOW_BIT_POS_PROBE_OUT100 = "16'b0000000001100100" *)
(* LC_LOW_BIT_POS_PROBE_OUT101 = "16'b0000000001100101" *) (* LC_LOW_BIT_POS_PROBE_OUT102 = "16'b0000000001100110" *) (* LC_LOW_BIT_POS_PROBE_OUT103 = "16'b0000000001100111" *)
(* LC_LOW_BIT_POS_PROBE_OUT104 = "16'b0000000001101000" *) (* LC_LOW_BIT_POS_PROBE_OUT105 = "16'b0000000001101001" *) (* LC_LOW_BIT_POS_PROBE_OUT106 = "16'b0000000001101010" *)
(* LC_LOW_BIT_POS_PROBE_OUT107 = "16'b0000000001101011" *) (* LC_LOW_BIT_POS_PROBE_OUT108 = "16'b0000000001101100" *) (* LC_LOW_BIT_POS_PROBE_OUT109 = "16'b0000000001101101" *)
(* LC_LOW_BIT_POS_PROBE_OUT11 = "16'b0000000000001011" *) (* LC_LOW_BIT_POS_PROBE_OUT110 = "16'b0000000001101110" *) (* LC_LOW_BIT_POS_PROBE_OUT111 = "16'b0000000001101111" *)
(* LC_LOW_BIT_POS_PROBE_OUT112 = "16'b0000000001110000" *) (* LC_LOW_BIT_POS_PROBE_OUT113 = "16'b0000000001110001" *) (* LC_LOW_BIT_POS_PROBE_OUT114 = "16'b0000000001110010" *)
(* LC_LOW_BIT_POS_PROBE_OUT115 = "16'b0000000001110011" *) (* LC_LOW_BIT_POS_PROBE_OUT116 = "16'b0000000001110100" *) (* LC_LOW_BIT_POS_PROBE_OUT117 = "16'b0000000001110101" *)
(* LC_LOW_BIT_POS_PROBE_OUT118 = "16'b0000000001110110" *) (* LC_LOW_BIT_POS_PROBE_OUT119 = "16'b0000000001110111" *) (* LC_LOW_BIT_POS_PROBE_OUT12 = "16'b0000000000001100" *)
(* LC_LOW_BIT_POS_PROBE_OUT120 = "16'b0000000001111000" *) (* LC_LOW_BIT_POS_PROBE_OUT121 = "16'b0000000001111001" *) (* LC_LOW_BIT_POS_PROBE_OUT122 = "16'b0000000001111010" *)
(* LC_LOW_BIT_POS_PROBE_OUT123 = "16'b0000000001111011" *) (* LC_LOW_BIT_POS_PROBE_OUT124 = "16'b0000000001111100" *) (* LC_LOW_BIT_POS_PROBE_OUT125 = "16'b0000000001111101" *)
(* LC_LOW_BIT_POS_PROBE_OUT126 = "16'b0000000001111110" *) (* LC_LOW_BIT_POS_PROBE_OUT127 = "16'b0000000001111111" *) (* LC_LOW_BIT_POS_PROBE_OUT128 = "16'b0000000010000000" *)
(* LC_LOW_BIT_POS_PROBE_OUT129 = "16'b0000000010000001" *) (* LC_LOW_BIT_POS_PROBE_OUT13 = "16'b0000000000001101" *) (* LC_LOW_BIT_POS_PROBE_OUT130 = "16'b0000000010000010" *)
(* LC_LOW_BIT_POS_PROBE_OUT131 = "16'b0000000010000011" *) (* LC_LOW_BIT_POS_PROBE_OUT132 = "16'b0000000010000100" *) (* LC_LOW_BIT_POS_PROBE_OUT133 = "16'b0000000010000101" *)
(* LC_LOW_BIT_POS_PROBE_OUT134 = "16'b0000000010000110" *) (* LC_LOW_BIT_POS_PROBE_OUT135 = "16'b0000000010000111" *) (* LC_LOW_BIT_POS_PROBE_OUT136 = "16'b0000000010001000" *)
(* LC_LOW_BIT_POS_PROBE_OUT137 = "16'b0000000010001001" *) (* LC_LOW_BIT_POS_PROBE_OUT138 = "16'b0000000010001010" *) (* LC_LOW_BIT_POS_PROBE_OUT139 = "16'b0000000010001011" *)
(* LC_LOW_BIT_POS_PROBE_OUT14 = "16'b0000000000001110" *) (* LC_LOW_BIT_POS_PROBE_OUT140 = "16'b0000000010001100" *) (* LC_LOW_BIT_POS_PROBE_OUT141 = "16'b0000000010001101" *)
(* LC_LOW_BIT_POS_PROBE_OUT142 = "16'b0000000010001110" *) (* LC_LOW_BIT_POS_PROBE_OUT143 = "16'b0000000010001111" *) (* LC_LOW_BIT_POS_PROBE_OUT144 = "16'b0000000010010000" *)
(* LC_LOW_BIT_POS_PROBE_OUT145 = "16'b0000000010010001" *) (* LC_LOW_BIT_POS_PROBE_OUT146 = "16'b0000000010010010" *) (* LC_LOW_BIT_POS_PROBE_OUT147 = "16'b0000000010010011" *)
(* LC_LOW_BIT_POS_PROBE_OUT148 = "16'b0000000010010100" *) (* LC_LOW_BIT_POS_PROBE_OUT149 = "16'b0000000010010101" *) (* LC_LOW_BIT_POS_PROBE_OUT15 = "16'b0000000000001111" *)
(* LC_LOW_BIT_POS_PROBE_OUT150 = "16'b0000000010010110" *) (* LC_LOW_BIT_POS_PROBE_OUT151 = "16'b0000000010010111" *) (* LC_LOW_BIT_POS_PROBE_OUT152 = "16'b0000000010011000" *)
(* LC_LOW_BIT_POS_PROBE_OUT153 = "16'b0000000010011001" *) (* LC_LOW_BIT_POS_PROBE_OUT154 = "16'b0000000010011010" *) (* LC_LOW_BIT_POS_PROBE_OUT155 = "16'b0000000010011011" *)
(* LC_LOW_BIT_POS_PROBE_OUT156 = "16'b0000000010011100" *) (* LC_LOW_BIT_POS_PROBE_OUT157 = "16'b0000000010011101" *) (* LC_LOW_BIT_POS_PROBE_OUT158 = "16'b0000000010011110" *)
(* LC_LOW_BIT_POS_PROBE_OUT159 = "16'b0000000010011111" *) (* LC_LOW_BIT_POS_PROBE_OUT16 = "16'b0000000000010000" *) (* LC_LOW_BIT_POS_PROBE_OUT160 = "16'b0000000010100000" *)
(* LC_LOW_BIT_POS_PROBE_OUT161 = "16'b0000000010100001" *) (* LC_LOW_BIT_POS_PROBE_OUT162 = "16'b0000000010100010" *) (* LC_LOW_BIT_POS_PROBE_OUT163 = "16'b0000000010100011" *)
(* LC_LOW_BIT_POS_PROBE_OUT164 = "16'b0000000010100100" *) (* LC_LOW_BIT_POS_PROBE_OUT165 = "16'b0000000010100101" *) (* LC_LOW_BIT_POS_PROBE_OUT166 = "16'b0000000010100110" *)
(* LC_LOW_BIT_POS_PROBE_OUT167 = "16'b0000000010100111" *) (* LC_LOW_BIT_POS_PROBE_OUT168 = "16'b0000000010101000" *) (* LC_LOW_BIT_POS_PROBE_OUT169 = "16'b0000000010101001" *)
(* LC_LOW_BIT_POS_PROBE_OUT17 = "16'b0000000000010001" *) (* LC_LOW_BIT_POS_PROBE_OUT170 = "16'b0000000010101010" *) (* LC_LOW_BIT_POS_PROBE_OUT171 = "16'b0000000010101011" *)
(* LC_LOW_BIT_POS_PROBE_OUT172 = "16'b0000000010101100" *) (* LC_LOW_BIT_POS_PROBE_OUT173 = "16'b0000000010101101" *) (* LC_LOW_BIT_POS_PROBE_OUT174 = "16'b0000000010101110" *)
(* LC_LOW_BIT_POS_PROBE_OUT175 = "16'b0000000010101111" *) (* LC_LOW_BIT_POS_PROBE_OUT176 = "16'b0000000010110000" *) (* LC_LOW_BIT_POS_PROBE_OUT177 = "16'b0000000010110001" *)
(* LC_LOW_BIT_POS_PROBE_OUT178 = "16'b0000000010110010" *) (* LC_LOW_BIT_POS_PROBE_OUT179 = "16'b0000000010110011" *) (* LC_LOW_BIT_POS_PROBE_OUT18 = "16'b0000000000010010" *)
(* LC_LOW_BIT_POS_PROBE_OUT180 = "16'b0000000010110100" *) (* LC_LOW_BIT_POS_PROBE_OUT181 = "16'b0000000010110101" *) (* LC_LOW_BIT_POS_PROBE_OUT182 = "16'b0000000010110110" *)
(* LC_LOW_BIT_POS_PROBE_OUT183 = "16'b0000000010110111" *) (* LC_LOW_BIT_POS_PROBE_OUT184 = "16'b0000000010111000" *) (* LC_LOW_BIT_POS_PROBE_OUT185 = "16'b0000000010111001" *)
(* LC_LOW_BIT_POS_PROBE_OUT186 = "16'b0000000010111010" *) (* LC_LOW_BIT_POS_PROBE_OUT187 = "16'b0000000010111011" *) (* LC_LOW_BIT_POS_PROBE_OUT188 = "16'b0000000010111100" *)
(* LC_LOW_BIT_POS_PROBE_OUT189 = "16'b0000000010111101" *) (* LC_LOW_BIT_POS_PROBE_OUT19 = "16'b0000000000010011" *) (* LC_LOW_BIT_POS_PROBE_OUT190 = "16'b0000000010111110" *)
(* LC_LOW_BIT_POS_PROBE_OUT191 = "16'b0000000010111111" *) (* LC_LOW_BIT_POS_PROBE_OUT192 = "16'b0000000011000000" *) (* LC_LOW_BIT_POS_PROBE_OUT193 = "16'b0000000011000001" *)
(* LC_LOW_BIT_POS_PROBE_OUT194 = "16'b0000000011000010" *) (* LC_LOW_BIT_POS_PROBE_OUT195 = "16'b0000000011000011" *) (* LC_LOW_BIT_POS_PROBE_OUT196 = "16'b0000000011000100" *)
(* LC_LOW_BIT_POS_PROBE_OUT197 = "16'b0000000011000101" *) (* LC_LOW_BIT_POS_PROBE_OUT198 = "16'b0000000011000110" *) (* LC_LOW_BIT_POS_PROBE_OUT199 = "16'b0000000011000111" *)
(* LC_LOW_BIT_POS_PROBE_OUT2 = "16'b0000000000000010" *) (* LC_LOW_BIT_POS_PROBE_OUT20 = "16'b0000000000010100" *) (* LC_LOW_BIT_POS_PROBE_OUT200 = "16'b0000000011001000" *)
(* LC_LOW_BIT_POS_PROBE_OUT201 = "16'b0000000011001001" *) (* LC_LOW_BIT_POS_PROBE_OUT202 = "16'b0000000011001010" *) (* LC_LOW_BIT_POS_PROBE_OUT203 = "16'b0000000011001011" *)
(* LC_LOW_BIT_POS_PROBE_OUT204 = "16'b0000000011001100" *) (* LC_LOW_BIT_POS_PROBE_OUT205 = "16'b0000000011001101" *) (* LC_LOW_BIT_POS_PROBE_OUT206 = "16'b0000000011001110" *)
(* LC_LOW_BIT_POS_PROBE_OUT207 = "16'b0000000011001111" *) (* LC_LOW_BIT_POS_PROBE_OUT208 = "16'b0000000011010000" *) (* LC_LOW_BIT_POS_PROBE_OUT209 = "16'b0000000011010001" *)
(* LC_LOW_BIT_POS_PROBE_OUT21 = "16'b0000000000010101" *) (* LC_LOW_BIT_POS_PROBE_OUT210 = "16'b0000000011010010" *) (* LC_LOW_BIT_POS_PROBE_OUT211 = "16'b0000000011010011" *)
(* LC_LOW_BIT_POS_PROBE_OUT212 = "16'b0000000011010100" *) (* LC_LOW_BIT_POS_PROBE_OUT213 = "16'b0000000011010101" *) (* LC_LOW_BIT_POS_PROBE_OUT214 = "16'b0000000011010110" *)
(* LC_LOW_BIT_POS_PROBE_OUT215 = "16'b0000000011010111" *) (* LC_LOW_BIT_POS_PROBE_OUT216 = "16'b0000000011011000" *) (* LC_LOW_BIT_POS_PROBE_OUT217 = "16'b0000000011011001" *)
(* LC_LOW_BIT_POS_PROBE_OUT218 = "16'b0000000011011010" *) (* LC_LOW_BIT_POS_PROBE_OUT219 = "16'b0000000011011011" *) (* LC_LOW_BIT_POS_PROBE_OUT22 = "16'b0000000000010110" *)
(* LC_LOW_BIT_POS_PROBE_OUT220 = "16'b0000000011011100" *) (* LC_LOW_BIT_POS_PROBE_OUT221 = "16'b0000000011011101" *) (* LC_LOW_BIT_POS_PROBE_OUT222 = "16'b0000000011011110" *)
(* LC_LOW_BIT_POS_PROBE_OUT223 = "16'b0000000011011111" *) (* LC_LOW_BIT_POS_PROBE_OUT224 = "16'b0000000011100000" *) (* LC_LOW_BIT_POS_PROBE_OUT225 = "16'b0000000011100001" *)
(* LC_LOW_BIT_POS_PROBE_OUT226 = "16'b0000000011100010" *) (* LC_LOW_BIT_POS_PROBE_OUT227 = "16'b0000000011100011" *) (* LC_LOW_BIT_POS_PROBE_OUT228 = "16'b0000000011100100" *)
(* LC_LOW_BIT_POS_PROBE_OUT229 = "16'b0000000011100101" *) (* LC_LOW_BIT_POS_PROBE_OUT23 = "16'b0000000000010111" *) (* LC_LOW_BIT_POS_PROBE_OUT230 = "16'b0000000011100110" *)
(* LC_LOW_BIT_POS_PROBE_OUT231 = "16'b0000000011100111" *) (* LC_LOW_BIT_POS_PROBE_OUT232 = "16'b0000000011101000" *) (* LC_LOW_BIT_POS_PROBE_OUT233 = "16'b0000000011101001" *)
(* LC_LOW_BIT_POS_PROBE_OUT234 = "16'b0000000011101010" *) (* LC_LOW_BIT_POS_PROBE_OUT235 = "16'b0000000011101011" *) (* LC_LOW_BIT_POS_PROBE_OUT236 = "16'b0000000011101100" *)
(* LC_LOW_BIT_POS_PROBE_OUT237 = "16'b0000000011101101" *) (* LC_LOW_BIT_POS_PROBE_OUT238 = "16'b0000000011101110" *) (* LC_LOW_BIT_POS_PROBE_OUT239 = "16'b0000000011101111" *)
(* LC_LOW_BIT_POS_PROBE_OUT24 = "16'b0000000000011000" *) (* LC_LOW_BIT_POS_PROBE_OUT240 = "16'b0000000011110000" *) (* LC_LOW_BIT_POS_PROBE_OUT241 = "16'b0000000011110001" *)
(* LC_LOW_BIT_POS_PROBE_OUT242 = "16'b0000000011110010" *) (* LC_LOW_BIT_POS_PROBE_OUT243 = "16'b0000000011110011" *) (* LC_LOW_BIT_POS_PROBE_OUT244 = "16'b0000000011110100" *)
(* LC_LOW_BIT_POS_PROBE_OUT245 = "16'b0000000011110101" *) (* LC_LOW_BIT_POS_PROBE_OUT246 = "16'b0000000011110110" *) (* LC_LOW_BIT_POS_PROBE_OUT247 = "16'b0000000011110111" *)
(* LC_LOW_BIT_POS_PROBE_OUT248 = "16'b0000000011111000" *) (* LC_LOW_BIT_POS_PROBE_OUT249 = "16'b0000000011111001" *) (* LC_LOW_BIT_POS_PROBE_OUT25 = "16'b0000000000011001" *)
(* LC_LOW_BIT_POS_PROBE_OUT250 = "16'b0000000011111010" *) (* LC_LOW_BIT_POS_PROBE_OUT251 = "16'b0000000011111011" *) (* LC_LOW_BIT_POS_PROBE_OUT252 = "16'b0000000011111100" *)
(* LC_LOW_BIT_POS_PROBE_OUT253 = "16'b0000000011111101" *) (* LC_LOW_BIT_POS_PROBE_OUT254 = "16'b0000000011111110" *) (* LC_LOW_BIT_POS_PROBE_OUT255 = "16'b0000000011111111" *)
(* LC_LOW_BIT_POS_PROBE_OUT26 = "16'b0000000000011010" *) (* LC_LOW_BIT_POS_PROBE_OUT27 = "16'b0000000000011011" *) (* LC_LOW_BIT_POS_PROBE_OUT28 = "16'b0000000000011100" *)
(* LC_LOW_BIT_POS_PROBE_OUT29 = "16'b0000000000011101" *) (* LC_LOW_BIT_POS_PROBE_OUT3 = "16'b0000000000000011" *) (* LC_LOW_BIT_POS_PROBE_OUT30 = "16'b0000000000011110" *)
(* LC_LOW_BIT_POS_PROBE_OUT31 = "16'b0000000000011111" *) (* LC_LOW_BIT_POS_PROBE_OUT32 = "16'b0000000000100000" *) (* LC_LOW_BIT_POS_PROBE_OUT33 = "16'b0000000000100001" *)
(* LC_LOW_BIT_POS_PROBE_OUT34 = "16'b0000000000100010" *) (* LC_LOW_BIT_POS_PROBE_OUT35 = "16'b0000000000100011" *) (* LC_LOW_BIT_POS_PROBE_OUT36 = "16'b0000000000100100" *)
(* LC_LOW_BIT_POS_PROBE_OUT37 = "16'b0000000000100101" *) (* LC_LOW_BIT_POS_PROBE_OUT38 = "16'b0000000000100110" *) (* LC_LOW_BIT_POS_PROBE_OUT39 = "16'b0000000000100111" *)
(* LC_LOW_BIT_POS_PROBE_OUT4 = "16'b0000000000000100" *) (* LC_LOW_BIT_POS_PROBE_OUT40 = "16'b0000000000101000" *) (* LC_LOW_BIT_POS_PROBE_OUT41 = "16'b0000000000101001" *)
(* LC_LOW_BIT_POS_PROBE_OUT42 = "16'b0000000000101010" *) (* LC_LOW_BIT_POS_PROBE_OUT43 = "16'b0000000000101011" *) (* LC_LOW_BIT_POS_PROBE_OUT44 = "16'b0000000000101100" *)
(* LC_LOW_BIT_POS_PROBE_OUT45 = "16'b0000000000101101" *) (* LC_LOW_BIT_POS_PROBE_OUT46 = "16'b0000000000101110" *) (* LC_LOW_BIT_POS_PROBE_OUT47 = "16'b0000000000101111" *)
(* LC_LOW_BIT_POS_PROBE_OUT48 = "16'b0000000000110000" *) (* LC_LOW_BIT_POS_PROBE_OUT49 = "16'b0000000000110001" *) (* LC_LOW_BIT_POS_PROBE_OUT5 = "16'b0000000000000101" *)
(* LC_LOW_BIT_POS_PROBE_OUT50 = "16'b0000000000110010" *) (* LC_LOW_BIT_POS_PROBE_OUT51 = "16'b0000000000110011" *) (* LC_LOW_BIT_POS_PROBE_OUT52 = "16'b0000000000110100" *)
(* LC_LOW_BIT_POS_PROBE_OUT53 = "16'b0000000000110101" *) (* LC_LOW_BIT_POS_PROBE_OUT54 = "16'b0000000000110110" *) (* LC_LOW_BIT_POS_PROBE_OUT55 = "16'b0000000000110111" *)
(* LC_LOW_BIT_POS_PROBE_OUT56 = "16'b0000000000111000" *) (* LC_LOW_BIT_POS_PROBE_OUT57 = "16'b0000000000111001" *) (* LC_LOW_BIT_POS_PROBE_OUT58 = "16'b0000000000111010" *)
(* LC_LOW_BIT_POS_PROBE_OUT59 = "16'b0000000000111011" *) (* LC_LOW_BIT_POS_PROBE_OUT6 = "16'b0000000000000110" *) (* LC_LOW_BIT_POS_PROBE_OUT60 = "16'b0000000000111100" *)
(* LC_LOW_BIT_POS_PROBE_OUT61 = "16'b0000000000111101" *) (* LC_LOW_BIT_POS_PROBE_OUT62 = "16'b0000000000111110" *) (* LC_LOW_BIT_POS_PROBE_OUT63 = "16'b0000000000111111" *)
(* LC_LOW_BIT_POS_PROBE_OUT64 = "16'b0000000001000000" *) (* LC_LOW_BIT_POS_PROBE_OUT65 = "16'b0000000001000001" *) (* LC_LOW_BIT_POS_PROBE_OUT66 = "16'b0000000001000010" *)
(* LC_LOW_BIT_POS_PROBE_OUT67 = "16'b0000000001000011" *) (* LC_LOW_BIT_POS_PROBE_OUT68 = "16'b0000000001000100" *) (* LC_LOW_BIT_POS_PROBE_OUT69 = "16'b0000000001000101" *)
(* LC_LOW_BIT_POS_PROBE_OUT7 = "16'b0000000000000111" *) (* LC_LOW_BIT_POS_PROBE_OUT70 = "16'b0000000001000110" *) (* LC_LOW_BIT_POS_PROBE_OUT71 = "16'b0000000001000111" *)
(* LC_LOW_BIT_POS_PROBE_OUT72 = "16'b0000000001001000" *) (* LC_LOW_BIT_POS_PROBE_OUT73 = "16'b0000000001001001" *) (* LC_LOW_BIT_POS_PROBE_OUT74 = "16'b0000000001001010" *)
(* LC_LOW_BIT_POS_PROBE_OUT75 = "16'b0000000001001011" *) (* LC_LOW_BIT_POS_PROBE_OUT76 = "16'b0000000001001100" *) (* LC_LOW_BIT_POS_PROBE_OUT77 = "16'b0000000001001101" *)
(* LC_LOW_BIT_POS_PROBE_OUT78 = "16'b0000000001001110" *) (* LC_LOW_BIT_POS_PROBE_OUT79 = "16'b0000000001001111" *) (* LC_LOW_BIT_POS_PROBE_OUT8 = "16'b0000000000001000" *)
(* LC_LOW_BIT_POS_PROBE_OUT80 = "16'b0000000001010000" *) (* LC_LOW_BIT_POS_PROBE_OUT81 = "16'b0000000001010001" *) (* LC_LOW_BIT_POS_PROBE_OUT82 = "16'b0000000001010010" *)
(* LC_LOW_BIT_POS_PROBE_OUT83 = "16'b0000000001010011" *) (* LC_LOW_BIT_POS_PROBE_OUT84 = "16'b0000000001010100" *) (* LC_LOW_BIT_POS_PROBE_OUT85 = "16'b0000000001010101" *)
(* LC_LOW_BIT_POS_PROBE_OUT86 = "16'b0000000001010110" *) (* LC_LOW_BIT_POS_PROBE_OUT87 = "16'b0000000001010111" *) (* LC_LOW_BIT_POS_PROBE_OUT88 = "16'b0000000001011000" *)
(* LC_LOW_BIT_POS_PROBE_OUT89 = "16'b0000000001011001" *) (* LC_LOW_BIT_POS_PROBE_OUT9 = "16'b0000000000001001" *) (* LC_LOW_BIT_POS_PROBE_OUT90 = "16'b0000000001011010" *)
(* LC_LOW_BIT_POS_PROBE_OUT91 = "16'b0000000001011011" *) (* LC_LOW_BIT_POS_PROBE_OUT92 = "16'b0000000001011100" *) (* LC_LOW_BIT_POS_PROBE_OUT93 = "16'b0000000001011101" *)
(* LC_LOW_BIT_POS_PROBE_OUT94 = "16'b0000000001011110" *) (* LC_LOW_BIT_POS_PROBE_OUT95 = "16'b0000000001011111" *) (* LC_LOW_BIT_POS_PROBE_OUT96 = "16'b0000000001100000" *)
(* LC_LOW_BIT_POS_PROBE_OUT97 = "16'b0000000001100001" *) (* LC_LOW_BIT_POS_PROBE_OUT98 = "16'b0000000001100010" *) (* LC_LOW_BIT_POS_PROBE_OUT99 = "16'b0000000001100011" *)
(* LC_PROBE_IN_WIDTH_STRING = "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* LC_PROBE_OUT_HIGH_BIT_POS_STRING = "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000" *) (* LC_PROBE_OUT_INIT_VAL_STRING = "256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* LC_PROBE_OUT_LOW_BIT_POS_STRING = "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000" *) (* LC_PROBE_OUT_WIDTH_STRING = "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* LC_TOTAL_PROBE_IN_WIDTH = "4" *)
(* LC_TOTAL_PROBE_OUT_WIDTH = "0" *) (* ORIG_REF_NAME = "vio_v3_0_13_vio" *) (* dont_touch = "true" *)
module vio_0_vio_v3_0_13_vio
(clk,
probe_in0,
probe_in1,
probe_in2,
probe_in3,
probe_in4,
probe_in5,
probe_in6,
probe_in7,
probe_in8,
probe_in9,
probe_in10,
probe_in11,
probe_in12,
probe_in13,
probe_in14,
probe_in15,
probe_in16,
probe_in17,
probe_in18,
probe_in19,
probe_in20,
probe_in21,
probe_in22,
probe_in23,
probe_in24,
probe_in25,
probe_in26,
probe_in27,
probe_in28,
probe_in29,
probe_in30,
probe_in31,
probe_in32,
probe_in33,
probe_in34,
probe_in35,
probe_in36,
probe_in37,
probe_in38,
probe_in39,
probe_in40,
probe_in41,
probe_in42,
probe_in43,
probe_in44,
probe_in45,
probe_in46,
probe_in47,
probe_in48,
probe_in49,
probe_in50,
probe_in51,
probe_in52,
probe_in53,
probe_in54,
probe_in55,
probe_in56,
probe_in57,
probe_in58,
probe_in59,
probe_in60,
probe_in61,
probe_in62,
probe_in63,
probe_in64,
probe_in65,
probe_in66,
probe_in67,
probe_in68,
probe_in69,
probe_in70,
probe_in71,
probe_in72,
probe_in73,
probe_in74,
probe_in75,
probe_in76,
probe_in77,
probe_in78,
probe_in79,
probe_in80,
probe_in81,
probe_in82,
probe_in83,
probe_in84,
probe_in85,
probe_in86,
probe_in87,
probe_in88,
probe_in89,
probe_in90,
probe_in91,
probe_in92,
probe_in93,
probe_in94,
probe_in95,
probe_in96,
probe_in97,
probe_in98,
probe_in99,
probe_in100,
probe_in101,
probe_in102,
probe_in103,
probe_in104,
probe_in105,
probe_in106,
probe_in107,
probe_in108,
probe_in109,
probe_in110,
probe_in111,
probe_in112,
probe_in113,
probe_in114,
probe_in115,
probe_in116,
probe_in117,
probe_in118,
probe_in119,
probe_in120,
probe_in121,
probe_in122,
probe_in123,
probe_in124,
probe_in125,
probe_in126,
probe_in127,
probe_in128,
probe_in129,
probe_in130,
probe_in131,
probe_in132,
probe_in133,
probe_in134,
probe_in135,
probe_in136,
probe_in137,
probe_in138,
probe_in139,
probe_in140,
probe_in141,
probe_in142,
probe_in143,
probe_in144,
probe_in145,
probe_in146,
probe_in147,
probe_in148,
probe_in149,
probe_in150,
probe_in151,
probe_in152,
probe_in153,
probe_in154,
probe_in155,
probe_in156,
probe_in157,
probe_in158,
probe_in159,
probe_in160,
probe_in161,
probe_in162,
probe_in163,
probe_in164,
probe_in165,
probe_in166,
probe_in167,
probe_in168,
probe_in169,
probe_in170,
probe_in171,
probe_in172,
probe_in173,
probe_in174,
probe_in175,
probe_in176,
probe_in177,
probe_in178,
probe_in179,
probe_in180,
probe_in181,
probe_in182,
probe_in183,
probe_in184,
probe_in185,
probe_in186,
probe_in187,
probe_in188,
probe_in189,
probe_in190,
probe_in191,
probe_in192,
probe_in193,
probe_in194,
probe_in195,
probe_in196,
probe_in197,
probe_in198,
probe_in199,
probe_in200,
probe_in201,
probe_in202,
probe_in203,
probe_in204,
probe_in205,
probe_in206,
probe_in207,
probe_in208,
probe_in209,
probe_in210,
probe_in211,
probe_in212,
probe_in213,
probe_in214,
probe_in215,
probe_in216,
probe_in217,
probe_in218,
probe_in219,
probe_in220,
probe_in221,
probe_in222,
probe_in223,
probe_in224,
probe_in225,
probe_in226,
probe_in227,
probe_in228,
probe_in229,
probe_in230,
probe_in231,
probe_in232,
probe_in233,
probe_in234,
probe_in235,
probe_in236,
probe_in237,
probe_in238,
probe_in239,
probe_in240,
probe_in241,
probe_in242,
probe_in243,
probe_in244,
probe_in245,
probe_in246,
probe_in247,
probe_in248,
probe_in249,
probe_in250,
probe_in251,
probe_in252,
probe_in253,
probe_in254,
probe_in255,
sl_iport0,
sl_oport0,
probe_out0,
probe_out1,
probe_out2,
probe_out3,
probe_out4,
probe_out5,
probe_out6,
probe_out7,
probe_out8,
probe_out9,
probe_out10,
probe_out11,
probe_out12,
probe_out13,
probe_out14,
probe_out15,
probe_out16,
probe_out17,
probe_out18,
probe_out19,
probe_out20,
probe_out21,
probe_out22,
probe_out23,
probe_out24,
probe_out25,
probe_out26,
probe_out27,
probe_out28,
probe_out29,
probe_out30,
probe_out31,
probe_out32,
probe_out33,
probe_out34,
probe_out35,
probe_out36,
probe_out37,
probe_out38,
probe_out39,
probe_out40,
probe_out41,
probe_out42,
probe_out43,
probe_out44,
probe_out45,
probe_out46,
probe_out47,
probe_out48,
probe_out49,
probe_out50,
probe_out51,
probe_out52,
probe_out53,
probe_out54,
probe_out55,
probe_out56,
probe_out57,
probe_out58,
probe_out59,
probe_out60,
probe_out61,
probe_out62,
probe_out63,
probe_out64,
probe_out65,
probe_out66,
probe_out67,
probe_out68,
probe_out69,
probe_out70,
probe_out71,
probe_out72,
probe_out73,
probe_out74,
probe_out75,
probe_out76,
probe_out77,
probe_out78,
probe_out79,
probe_out80,
probe_out81,
probe_out82,
probe_out83,
probe_out84,
probe_out85,
probe_out86,
probe_out87,
probe_out88,
probe_out89,
probe_out90,
probe_out91,
probe_out92,
probe_out93,
probe_out94,
probe_out95,
probe_out96,
probe_out97,
probe_out98,
probe_out99,
probe_out100,
probe_out101,
probe_out102,
probe_out103,
probe_out104,
probe_out105,
probe_out106,
probe_out107,
probe_out108,
probe_out109,
probe_out110,
probe_out111,
probe_out112,
probe_out113,
probe_out114,
probe_out115,
probe_out116,
probe_out117,
probe_out118,
probe_out119,
probe_out120,
probe_out121,
probe_out122,
probe_out123,
probe_out124,
probe_out125,
probe_out126,
probe_out127,
probe_out128,
probe_out129,
probe_out130,
probe_out131,
probe_out132,
probe_out133,
probe_out134,
probe_out135,
probe_out136,
probe_out137,
probe_out138,
probe_out139,
probe_out140,
probe_out141,
probe_out142,
probe_out143,
probe_out144,
probe_out145,
probe_out146,
probe_out147,
probe_out148,
probe_out149,
probe_out150,
probe_out151,
probe_out152,
probe_out153,
probe_out154,
probe_out155,
probe_out156,
probe_out157,
probe_out158,
probe_out159,
probe_out160,
probe_out161,
probe_out162,
probe_out163,
probe_out164,
probe_out165,
probe_out166,
probe_out167,
probe_out168,
probe_out169,
probe_out170,
probe_out171,
probe_out172,
probe_out173,
probe_out174,
probe_out175,
probe_out176,
probe_out177,
probe_out178,
probe_out179,
probe_out180,
probe_out181,
probe_out182,
probe_out183,
probe_out184,
probe_out185,
probe_out186,
probe_out187,
probe_out188,
probe_out189,
probe_out190,
probe_out191,
probe_out192,
probe_out193,
probe_out194,
probe_out195,
probe_out196,
probe_out197,
probe_out198,
probe_out199,
probe_out200,
probe_out201,
probe_out202,
probe_out203,
probe_out204,
probe_out205,
probe_out206,
probe_out207,
probe_out208,
probe_out209,
probe_out210,
probe_out211,
probe_out212,
probe_out213,
probe_out214,
probe_out215,
probe_out216,
probe_out217,
probe_out218,
probe_out219,
probe_out220,
probe_out221,
probe_out222,
probe_out223,
probe_out224,
probe_out225,
probe_out226,
probe_out227,
probe_out228,
probe_out229,
probe_out230,
probe_out231,
probe_out232,
probe_out233,
probe_out234,
probe_out235,
probe_out236,
probe_out237,
probe_out238,
probe_out239,
probe_out240,
probe_out241,
probe_out242,
probe_out243,
probe_out244,
probe_out245,
probe_out246,
probe_out247,
probe_out248,
probe_out249,
probe_out250,
probe_out251,
probe_out252,
probe_out253,
probe_out254,
probe_out255);
input clk;
input [0:0]probe_in0;
input [0:0]probe_in1;
input [0:0]probe_in2;
input [0:0]probe_in3;
input [0:0]probe_in4;
input [0:0]probe_in5;
input [0:0]probe_in6;
input [0:0]probe_in7;
input [0:0]probe_in8;
input [0:0]probe_in9;
input [0:0]probe_in10;
input [0:0]probe_in11;
input [0:0]probe_in12;
input [0:0]probe_in13;
input [0:0]probe_in14;
input [0:0]probe_in15;
input [0:0]probe_in16;
input [0:0]probe_in17;
input [0:0]probe_in18;
input [0:0]probe_in19;
input [0:0]probe_in20;
input [0:0]probe_in21;
input [0:0]probe_in22;
input [0:0]probe_in23;
input [0:0]probe_in24;
input [0:0]probe_in25;
input [0:0]probe_in26;
input [0:0]probe_in27;
input [0:0]probe_in28;
input [0:0]probe_in29;
input [0:0]probe_in30;
input [0:0]probe_in31;
input [0:0]probe_in32;
input [0:0]probe_in33;
input [0:0]probe_in34;
input [0:0]probe_in35;
input [0:0]probe_in36;
input [0:0]probe_in37;
input [0:0]probe_in38;
input [0:0]probe_in39;
input [0:0]probe_in40;
input [0:0]probe_in41;
input [0:0]probe_in42;
input [0:0]probe_in43;
input [0:0]probe_in44;
input [0:0]probe_in45;
input [0:0]probe_in46;
input [0:0]probe_in47;
input [0:0]probe_in48;
input [0:0]probe_in49;
input [0:0]probe_in50;
input [0:0]probe_in51;
input [0:0]probe_in52;
input [0:0]probe_in53;
input [0:0]probe_in54;
input [0:0]probe_in55;
input [0:0]probe_in56;
input [0:0]probe_in57;
input [0:0]probe_in58;
input [0:0]probe_in59;
input [0:0]probe_in60;
input [0:0]probe_in61;
input [0:0]probe_in62;
input [0:0]probe_in63;
input [0:0]probe_in64;
input [0:0]probe_in65;
input [0:0]probe_in66;
input [0:0]probe_in67;
input [0:0]probe_in68;
input [0:0]probe_in69;
input [0:0]probe_in70;
input [0:0]probe_in71;
input [0:0]probe_in72;
input [0:0]probe_in73;
input [0:0]probe_in74;
input [0:0]probe_in75;
input [0:0]probe_in76;
input [0:0]probe_in77;
input [0:0]probe_in78;
input [0:0]probe_in79;
input [0:0]probe_in80;
input [0:0]probe_in81;
input [0:0]probe_in82;
input [0:0]probe_in83;
input [0:0]probe_in84;
input [0:0]probe_in85;
input [0:0]probe_in86;
input [0:0]probe_in87;
input [0:0]probe_in88;
input [0:0]probe_in89;
input [0:0]probe_in90;
input [0:0]probe_in91;
input [0:0]probe_in92;
input [0:0]probe_in93;
input [0:0]probe_in94;
input [0:0]probe_in95;
input [0:0]probe_in96;
input [0:0]probe_in97;
input [0:0]probe_in98;
input [0:0]probe_in99;
input [0:0]probe_in100;
input [0:0]probe_in101;
input [0:0]probe_in102;
input [0:0]probe_in103;
input [0:0]probe_in104;
input [0:0]probe_in105;
input [0:0]probe_in106;
input [0:0]probe_in107;
input [0:0]probe_in108;
input [0:0]probe_in109;
input [0:0]probe_in110;
input [0:0]probe_in111;
input [0:0]probe_in112;
input [0:0]probe_in113;
input [0:0]probe_in114;
input [0:0]probe_in115;
input [0:0]probe_in116;
input [0:0]probe_in117;
input [0:0]probe_in118;
input [0:0]probe_in119;
input [0:0]probe_in120;
input [0:0]probe_in121;
input [0:0]probe_in122;
input [0:0]probe_in123;
input [0:0]probe_in124;
input [0:0]probe_in125;
input [0:0]probe_in126;
input [0:0]probe_in127;
input [0:0]probe_in128;
input [0:0]probe_in129;
input [0:0]probe_in130;
input [0:0]probe_in131;
input [0:0]probe_in132;
input [0:0]probe_in133;
input [0:0]probe_in134;
input [0:0]probe_in135;
input [0:0]probe_in136;
input [0:0]probe_in137;
input [0:0]probe_in138;
input [0:0]probe_in139;
input [0:0]probe_in140;
input [0:0]probe_in141;
input [0:0]probe_in142;
input [0:0]probe_in143;
input [0:0]probe_in144;
input [0:0]probe_in145;
input [0:0]probe_in146;
input [0:0]probe_in147;
input [0:0]probe_in148;
input [0:0]probe_in149;
input [0:0]probe_in150;
input [0:0]probe_in151;
input [0:0]probe_in152;
input [0:0]probe_in153;
input [0:0]probe_in154;
input [0:0]probe_in155;
input [0:0]probe_in156;
input [0:0]probe_in157;
input [0:0]probe_in158;
input [0:0]probe_in159;
input [0:0]probe_in160;
input [0:0]probe_in161;
input [0:0]probe_in162;
input [0:0]probe_in163;
input [0:0]probe_in164;
input [0:0]probe_in165;
input [0:0]probe_in166;
input [0:0]probe_in167;
input [0:0]probe_in168;
input [0:0]probe_in169;
input [0:0]probe_in170;
input [0:0]probe_in171;
input [0:0]probe_in172;
input [0:0]probe_in173;
input [0:0]probe_in174;
input [0:0]probe_in175;
input [0:0]probe_in176;
input [0:0]probe_in177;
input [0:0]probe_in178;
input [0:0]probe_in179;
input [0:0]probe_in180;
input [0:0]probe_in181;
input [0:0]probe_in182;
input [0:0]probe_in183;
input [0:0]probe_in184;
input [0:0]probe_in185;
input [0:0]probe_in186;
input [0:0]probe_in187;
input [0:0]probe_in188;
input [0:0]probe_in189;
input [0:0]probe_in190;
input [0:0]probe_in191;
input [0:0]probe_in192;
input [0:0]probe_in193;
input [0:0]probe_in194;
input [0:0]probe_in195;
input [0:0]probe_in196;
input [0:0]probe_in197;
input [0:0]probe_in198;
input [0:0]probe_in199;
input [0:0]probe_in200;
input [0:0]probe_in201;
input [0:0]probe_in202;
input [0:0]probe_in203;
input [0:0]probe_in204;
input [0:0]probe_in205;
input [0:0]probe_in206;
input [0:0]probe_in207;
input [0:0]probe_in208;
input [0:0]probe_in209;
input [0:0]probe_in210;
input [0:0]probe_in211;
input [0:0]probe_in212;
input [0:0]probe_in213;
input [0:0]probe_in214;
input [0:0]probe_in215;
input [0:0]probe_in216;
input [0:0]probe_in217;
input [0:0]probe_in218;
input [0:0]probe_in219;
input [0:0]probe_in220;
input [0:0]probe_in221;
input [0:0]probe_in222;
input [0:0]probe_in223;
input [0:0]probe_in224;
input [0:0]probe_in225;
input [0:0]probe_in226;
input [0:0]probe_in227;
input [0:0]probe_in228;
input [0:0]probe_in229;
input [0:0]probe_in230;
input [0:0]probe_in231;
input [0:0]probe_in232;
input [0:0]probe_in233;
input [0:0]probe_in234;
input [0:0]probe_in235;
input [0:0]probe_in236;
input [0:0]probe_in237;
input [0:0]probe_in238;
input [0:0]probe_in239;
input [0:0]probe_in240;
input [0:0]probe_in241;
input [0:0]probe_in242;
input [0:0]probe_in243;
input [0:0]probe_in244;
input [0:0]probe_in245;
input [0:0]probe_in246;
input [0:0]probe_in247;
input [0:0]probe_in248;
input [0:0]probe_in249;
input [0:0]probe_in250;
input [0:0]probe_in251;
input [0:0]probe_in252;
input [0:0]probe_in253;
input [0:0]probe_in254;
input [0:0]probe_in255;
(* dont_touch = "true" *) input [36:0]sl_iport0;
(* dont_touch = "true" *) output [16:0]sl_oport0;
output [0:0]probe_out0;
output [0:0]probe_out1;
output [0:0]probe_out2;
output [0:0]probe_out3;
output [0:0]probe_out4;
output [0:0]probe_out5;
output [0:0]probe_out6;
output [0:0]probe_out7;
output [0:0]probe_out8;
output [0:0]probe_out9;
output [0:0]probe_out10;
output [0:0]probe_out11;
output [0:0]probe_out12;
output [0:0]probe_out13;
output [0:0]probe_out14;
output [0:0]probe_out15;
output [0:0]probe_out16;
output [0:0]probe_out17;
output [0:0]probe_out18;
output [0:0]probe_out19;
output [0:0]probe_out20;
output [0:0]probe_out21;
output [0:0]probe_out22;
output [0:0]probe_out23;
output [0:0]probe_out24;
output [0:0]probe_out25;
output [0:0]probe_out26;
output [0:0]probe_out27;
output [0:0]probe_out28;
output [0:0]probe_out29;
output [0:0]probe_out30;
output [0:0]probe_out31;
output [0:0]probe_out32;
output [0:0]probe_out33;
output [0:0]probe_out34;
output [0:0]probe_out35;
output [0:0]probe_out36;
output [0:0]probe_out37;
output [0:0]probe_out38;
output [0:0]probe_out39;
output [0:0]probe_out40;
output [0:0]probe_out41;
output [0:0]probe_out42;
output [0:0]probe_out43;
output [0:0]probe_out44;
output [0:0]probe_out45;
output [0:0]probe_out46;
output [0:0]probe_out47;
output [0:0]probe_out48;
output [0:0]probe_out49;
output [0:0]probe_out50;
output [0:0]probe_out51;
output [0:0]probe_out52;
output [0:0]probe_out53;
output [0:0]probe_out54;
output [0:0]probe_out55;
output [0:0]probe_out56;
output [0:0]probe_out57;
output [0:0]probe_out58;
output [0:0]probe_out59;
output [0:0]probe_out60;
output [0:0]probe_out61;
output [0:0]probe_out62;
output [0:0]probe_out63;
output [0:0]probe_out64;
output [0:0]probe_out65;
output [0:0]probe_out66;
output [0:0]probe_out67;
output [0:0]probe_out68;
output [0:0]probe_out69;
output [0:0]probe_out70;
output [0:0]probe_out71;
output [0:0]probe_out72;
output [0:0]probe_out73;
output [0:0]probe_out74;
output [0:0]probe_out75;
output [0:0]probe_out76;
output [0:0]probe_out77;
output [0:0]probe_out78;
output [0:0]probe_out79;
output [0:0]probe_out80;
output [0:0]probe_out81;
output [0:0]probe_out82;
output [0:0]probe_out83;
output [0:0]probe_out84;
output [0:0]probe_out85;
output [0:0]probe_out86;
output [0:0]probe_out87;
output [0:0]probe_out88;
output [0:0]probe_out89;
output [0:0]probe_out90;
output [0:0]probe_out91;
output [0:0]probe_out92;
output [0:0]probe_out93;
output [0:0]probe_out94;
output [0:0]probe_out95;
output [0:0]probe_out96;
output [0:0]probe_out97;
output [0:0]probe_out98;
output [0:0]probe_out99;
output [0:0]probe_out100;
output [0:0]probe_out101;
output [0:0]probe_out102;
output [0:0]probe_out103;
output [0:0]probe_out104;
output [0:0]probe_out105;
output [0:0]probe_out106;
output [0:0]probe_out107;
output [0:0]probe_out108;
output [0:0]probe_out109;
output [0:0]probe_out110;
output [0:0]probe_out111;
output [0:0]probe_out112;
output [0:0]probe_out113;
output [0:0]probe_out114;
output [0:0]probe_out115;
output [0:0]probe_out116;
output [0:0]probe_out117;
output [0:0]probe_out118;
output [0:0]probe_out119;
output [0:0]probe_out120;
output [0:0]probe_out121;
output [0:0]probe_out122;
output [0:0]probe_out123;
output [0:0]probe_out124;
output [0:0]probe_out125;
output [0:0]probe_out126;
output [0:0]probe_out127;
output [0:0]probe_out128;
output [0:0]probe_out129;
output [0:0]probe_out130;
output [0:0]probe_out131;
output [0:0]probe_out132;
output [0:0]probe_out133;
output [0:0]probe_out134;
output [0:0]probe_out135;
output [0:0]probe_out136;
output [0:0]probe_out137;
output [0:0]probe_out138;
output [0:0]probe_out139;
output [0:0]probe_out140;
output [0:0]probe_out141;
output [0:0]probe_out142;
output [0:0]probe_out143;
output [0:0]probe_out144;
output [0:0]probe_out145;
output [0:0]probe_out146;
output [0:0]probe_out147;
output [0:0]probe_out148;
output [0:0]probe_out149;
output [0:0]probe_out150;
output [0:0]probe_out151;
output [0:0]probe_out152;
output [0:0]probe_out153;
output [0:0]probe_out154;
output [0:0]probe_out155;
output [0:0]probe_out156;
output [0:0]probe_out157;
output [0:0]probe_out158;
output [0:0]probe_out159;
output [0:0]probe_out160;
output [0:0]probe_out161;
output [0:0]probe_out162;
output [0:0]probe_out163;
output [0:0]probe_out164;
output [0:0]probe_out165;
output [0:0]probe_out166;
output [0:0]probe_out167;
output [0:0]probe_out168;
output [0:0]probe_out169;
output [0:0]probe_out170;
output [0:0]probe_out171;
output [0:0]probe_out172;
output [0:0]probe_out173;
output [0:0]probe_out174;
output [0:0]probe_out175;
output [0:0]probe_out176;
output [0:0]probe_out177;
output [0:0]probe_out178;
output [0:0]probe_out179;
output [0:0]probe_out180;
output [0:0]probe_out181;
output [0:0]probe_out182;
output [0:0]probe_out183;
output [0:0]probe_out184;
output [0:0]probe_out185;
output [0:0]probe_out186;
output [0:0]probe_out187;
output [0:0]probe_out188;
output [0:0]probe_out189;
output [0:0]probe_out190;
output [0:0]probe_out191;
output [0:0]probe_out192;
output [0:0]probe_out193;
output [0:0]probe_out194;
output [0:0]probe_out195;
output [0:0]probe_out196;
output [0:0]probe_out197;
output [0:0]probe_out198;
output [0:0]probe_out199;
output [0:0]probe_out200;
output [0:0]probe_out201;
output [0:0]probe_out202;
output [0:0]probe_out203;
output [0:0]probe_out204;
output [0:0]probe_out205;
output [0:0]probe_out206;
output [0:0]probe_out207;
output [0:0]probe_out208;
output [0:0]probe_out209;
output [0:0]probe_out210;
output [0:0]probe_out211;
output [0:0]probe_out212;
output [0:0]probe_out213;
output [0:0]probe_out214;
output [0:0]probe_out215;
output [0:0]probe_out216;
output [0:0]probe_out217;
output [0:0]probe_out218;
output [0:0]probe_out219;
output [0:0]probe_out220;
output [0:0]probe_out221;
output [0:0]probe_out222;
output [0:0]probe_out223;
output [0:0]probe_out224;
output [0:0]probe_out225;
output [0:0]probe_out226;
output [0:0]probe_out227;
output [0:0]probe_out228;
output [0:0]probe_out229;
output [0:0]probe_out230;
output [0:0]probe_out231;
output [0:0]probe_out232;
output [0:0]probe_out233;
output [0:0]probe_out234;
output [0:0]probe_out235;
output [0:0]probe_out236;
output [0:0]probe_out237;
output [0:0]probe_out238;
output [0:0]probe_out239;
output [0:0]probe_out240;
output [0:0]probe_out241;
output [0:0]probe_out242;
output [0:0]probe_out243;
output [0:0]probe_out244;
output [0:0]probe_out245;
output [0:0]probe_out246;
output [0:0]probe_out247;
output [0:0]probe_out248;
output [0:0]probe_out249;
output [0:0]probe_out250;
output [0:0]probe_out251;
output [0:0]probe_out252;
output [0:0]probe_out253;
output [0:0]probe_out254;
output [0:0]probe_out255;
wire \<const0> ;
wire [11:0]Bus_Data_out;
wire DECODER_INST_n_1;
wire DECODER_INST_n_2;
wire DECODER_INST_n_3;
wire DECODER_INST_n_4;
wire [16:0]bus_addr;
(* DONT_TOUCH *) wire bus_clk;
wire \bus_data_int_reg_n_0_[0] ;
wire \bus_data_int_reg_n_0_[10] ;
wire \bus_data_int_reg_n_0_[11] ;
wire \bus_data_int_reg_n_0_[12] ;
wire \bus_data_int_reg_n_0_[13] ;
wire \bus_data_int_reg_n_0_[14] ;
wire \bus_data_int_reg_n_0_[15] ;
wire \bus_data_int_reg_n_0_[2] ;
wire \bus_data_int_reg_n_0_[3] ;
wire \bus_data_int_reg_n_0_[4] ;
wire \bus_data_int_reg_n_0_[5] ;
wire \bus_data_int_reg_n_0_[6] ;
wire \bus_data_int_reg_n_0_[7] ;
wire \bus_data_int_reg_n_0_[8] ;
wire \bus_data_int_reg_n_0_[9] ;
wire bus_den;
wire [15:0]bus_di;
wire [15:0]bus_do;
wire bus_drdy;
wire bus_dwe;
wire bus_rst;
wire clk;
wire p_0_in;
wire [0:0]probe_in0;
wire [0:0]probe_in1;
wire [0:0]probe_in2;
wire [0:0]probe_in3;
(* DONT_TOUCH *) wire [36:0]sl_iport0;
(* DONT_TOUCH *) wire [16:0]sl_oport0;
assign probe_out0[0] = \<const0> ;
assign probe_out1[0] = \<const0> ;
assign probe_out10[0] = \<const0> ;
assign probe_out100[0] = \<const0> ;
assign probe_out101[0] = \<const0> ;
assign probe_out102[0] = \<const0> ;
assign probe_out103[0] = \<const0> ;
assign probe_out104[0] = \<const0> ;
assign probe_out105[0] = \<const0> ;
assign probe_out106[0] = \<const0> ;
assign probe_out107[0] = \<const0> ;
assign probe_out108[0] = \<const0> ;
assign probe_out109[0] = \<const0> ;
assign probe_out11[0] = \<const0> ;
assign probe_out110[0] = \<const0> ;
assign probe_out111[0] = \<const0> ;
assign probe_out112[0] = \<const0> ;
assign probe_out113[0] = \<const0> ;
assign probe_out114[0] = \<const0> ;
assign probe_out115[0] = \<const0> ;
assign probe_out116[0] = \<const0> ;
assign probe_out117[0] = \<const0> ;
assign probe_out118[0] = \<const0> ;
assign probe_out119[0] = \<const0> ;
assign probe_out12[0] = \<const0> ;
assign probe_out120[0] = \<const0> ;
assign probe_out121[0] = \<const0> ;
assign probe_out122[0] = \<const0> ;
assign probe_out123[0] = \<const0> ;
assign probe_out124[0] = \<const0> ;
assign probe_out125[0] = \<const0> ;
assign probe_out126[0] = \<const0> ;
assign probe_out127[0] = \<const0> ;
assign probe_out128[0] = \<const0> ;
assign probe_out129[0] = \<const0> ;
assign probe_out13[0] = \<const0> ;
assign probe_out130[0] = \<const0> ;
assign probe_out131[0] = \<const0> ;
assign probe_out132[0] = \<const0> ;
assign probe_out133[0] = \<const0> ;
assign probe_out134[0] = \<const0> ;
assign probe_out135[0] = \<const0> ;
assign probe_out136[0] = \<const0> ;
assign probe_out137[0] = \<const0> ;
assign probe_out138[0] = \<const0> ;
assign probe_out139[0] = \<const0> ;
assign probe_out14[0] = \<const0> ;
assign probe_out140[0] = \<const0> ;
assign probe_out141[0] = \<const0> ;
assign probe_out142[0] = \<const0> ;
assign probe_out143[0] = \<const0> ;
assign probe_out144[0] = \<const0> ;
assign probe_out145[0] = \<const0> ;
assign probe_out146[0] = \<const0> ;
assign probe_out147[0] = \<const0> ;
assign probe_out148[0] = \<const0> ;
assign probe_out149[0] = \<const0> ;
assign probe_out15[0] = \<const0> ;
assign probe_out150[0] = \<const0> ;
assign probe_out151[0] = \<const0> ;
assign probe_out152[0] = \<const0> ;
assign probe_out153[0] = \<const0> ;
assign probe_out154[0] = \<const0> ;
assign probe_out155[0] = \<const0> ;
assign probe_out156[0] = \<const0> ;
assign probe_out157[0] = \<const0> ;
assign probe_out158[0] = \<const0> ;
assign probe_out159[0] = \<const0> ;
assign probe_out16[0] = \<const0> ;
assign probe_out160[0] = \<const0> ;
assign probe_out161[0] = \<const0> ;
assign probe_out162[0] = \<const0> ;
assign probe_out163[0] = \<const0> ;
assign probe_out164[0] = \<const0> ;
assign probe_out165[0] = \<const0> ;
assign probe_out166[0] = \<const0> ;
assign probe_out167[0] = \<const0> ;
assign probe_out168[0] = \<const0> ;
assign probe_out169[0] = \<const0> ;
assign probe_out17[0] = \<const0> ;
assign probe_out170[0] = \<const0> ;
assign probe_out171[0] = \<const0> ;
assign probe_out172[0] = \<const0> ;
assign probe_out173[0] = \<const0> ;
assign probe_out174[0] = \<const0> ;
assign probe_out175[0] = \<const0> ;
assign probe_out176[0] = \<const0> ;
assign probe_out177[0] = \<const0> ;
assign probe_out178[0] = \<const0> ;
assign probe_out179[0] = \<const0> ;
assign probe_out18[0] = \<const0> ;
assign probe_out180[0] = \<const0> ;
assign probe_out181[0] = \<const0> ;
assign probe_out182[0] = \<const0> ;
assign probe_out183[0] = \<const0> ;
assign probe_out184[0] = \<const0> ;
assign probe_out185[0] = \<const0> ;
assign probe_out186[0] = \<const0> ;
assign probe_out187[0] = \<const0> ;
assign probe_out188[0] = \<const0> ;
assign probe_out189[0] = \<const0> ;
assign probe_out19[0] = \<const0> ;
assign probe_out190[0] = \<const0> ;
assign probe_out191[0] = \<const0> ;
assign probe_out192[0] = \<const0> ;
assign probe_out193[0] = \<const0> ;
assign probe_out194[0] = \<const0> ;
assign probe_out195[0] = \<const0> ;
assign probe_out196[0] = \<const0> ;
assign probe_out197[0] = \<const0> ;
assign probe_out198[0] = \<const0> ;
assign probe_out199[0] = \<const0> ;
assign probe_out2[0] = \<const0> ;
assign probe_out20[0] = \<const0> ;
assign probe_out200[0] = \<const0> ;
assign probe_out201[0] = \<const0> ;
assign probe_out202[0] = \<const0> ;
assign probe_out203[0] = \<const0> ;
assign probe_out204[0] = \<const0> ;
assign probe_out205[0] = \<const0> ;
assign probe_out206[0] = \<const0> ;
assign probe_out207[0] = \<const0> ;
assign probe_out208[0] = \<const0> ;
assign probe_out209[0] = \<const0> ;
assign probe_out21[0] = \<const0> ;
assign probe_out210[0] = \<const0> ;
assign probe_out211[0] = \<const0> ;
assign probe_out212[0] = \<const0> ;
assign probe_out213[0] = \<const0> ;
assign probe_out214[0] = \<const0> ;
assign probe_out215[0] = \<const0> ;
assign probe_out216[0] = \<const0> ;
assign probe_out217[0] = \<const0> ;
assign probe_out218[0] = \<const0> ;
assign probe_out219[0] = \<const0> ;
assign probe_out22[0] = \<const0> ;
assign probe_out220[0] = \<const0> ;
assign probe_out221[0] = \<const0> ;
assign probe_out222[0] = \<const0> ;
assign probe_out223[0] = \<const0> ;
assign probe_out224[0] = \<const0> ;
assign probe_out225[0] = \<const0> ;
assign probe_out226[0] = \<const0> ;
assign probe_out227[0] = \<const0> ;
assign probe_out228[0] = \<const0> ;
assign probe_out229[0] = \<const0> ;
assign probe_out23[0] = \<const0> ;
assign probe_out230[0] = \<const0> ;
assign probe_out231[0] = \<const0> ;
assign probe_out232[0] = \<const0> ;
assign probe_out233[0] = \<const0> ;
assign probe_out234[0] = \<const0> ;
assign probe_out235[0] = \<const0> ;
assign probe_out236[0] = \<const0> ;
assign probe_out237[0] = \<const0> ;
assign probe_out238[0] = \<const0> ;
assign probe_out239[0] = \<const0> ;
assign probe_out24[0] = \<const0> ;
assign probe_out240[0] = \<const0> ;
assign probe_out241[0] = \<const0> ;
assign probe_out242[0] = \<const0> ;
assign probe_out243[0] = \<const0> ;
assign probe_out244[0] = \<const0> ;
assign probe_out245[0] = \<const0> ;
assign probe_out246[0] = \<const0> ;
assign probe_out247[0] = \<const0> ;
assign probe_out248[0] = \<const0> ;
assign probe_out249[0] = \<const0> ;
assign probe_out25[0] = \<const0> ;
assign probe_out250[0] = \<const0> ;
assign probe_out251[0] = \<const0> ;
assign probe_out252[0] = \<const0> ;
assign probe_out253[0] = \<const0> ;
assign probe_out254[0] = \<const0> ;
assign probe_out255[0] = \<const0> ;
assign probe_out26[0] = \<const0> ;
assign probe_out27[0] = \<const0> ;
assign probe_out28[0] = \<const0> ;
assign probe_out29[0] = \<const0> ;
assign probe_out3[0] = \<const0> ;
assign probe_out30[0] = \<const0> ;
assign probe_out31[0] = \<const0> ;
assign probe_out32[0] = \<const0> ;
assign probe_out33[0] = \<const0> ;
assign probe_out34[0] = \<const0> ;
assign probe_out35[0] = \<const0> ;
assign probe_out36[0] = \<const0> ;
assign probe_out37[0] = \<const0> ;
assign probe_out38[0] = \<const0> ;
assign probe_out39[0] = \<const0> ;
assign probe_out4[0] = \<const0> ;
assign probe_out40[0] = \<const0> ;
assign probe_out41[0] = \<const0> ;
assign probe_out42[0] = \<const0> ;
assign probe_out43[0] = \<const0> ;
assign probe_out44[0] = \<const0> ;
assign probe_out45[0] = \<const0> ;
assign probe_out46[0] = \<const0> ;
assign probe_out47[0] = \<const0> ;
assign probe_out48[0] = \<const0> ;
assign probe_out49[0] = \<const0> ;
assign probe_out5[0] = \<const0> ;
assign probe_out50[0] = \<const0> ;
assign probe_out51[0] = \<const0> ;
assign probe_out52[0] = \<const0> ;
assign probe_out53[0] = \<const0> ;
assign probe_out54[0] = \<const0> ;
assign probe_out55[0] = \<const0> ;
assign probe_out56[0] = \<const0> ;
assign probe_out57[0] = \<const0> ;
assign probe_out58[0] = \<const0> ;
assign probe_out59[0] = \<const0> ;
assign probe_out6[0] = \<const0> ;
assign probe_out60[0] = \<const0> ;
assign probe_out61[0] = \<const0> ;
assign probe_out62[0] = \<const0> ;
assign probe_out63[0] = \<const0> ;
assign probe_out64[0] = \<const0> ;
assign probe_out65[0] = \<const0> ;
assign probe_out66[0] = \<const0> ;
assign probe_out67[0] = \<const0> ;
assign probe_out68[0] = \<const0> ;
assign probe_out69[0] = \<const0> ;
assign probe_out7[0] = \<const0> ;
assign probe_out70[0] = \<const0> ;
assign probe_out71[0] = \<const0> ;
assign probe_out72[0] = \<const0> ;
assign probe_out73[0] = \<const0> ;
assign probe_out74[0] = \<const0> ;
assign probe_out75[0] = \<const0> ;
assign probe_out76[0] = \<const0> ;
assign probe_out77[0] = \<const0> ;
assign probe_out78[0] = \<const0> ;
assign probe_out79[0] = \<const0> ;
assign probe_out8[0] = \<const0> ;
assign probe_out80[0] = \<const0> ;
assign probe_out81[0] = \<const0> ;
assign probe_out82[0] = \<const0> ;
assign probe_out83[0] = \<const0> ;
assign probe_out84[0] = \<const0> ;
assign probe_out85[0] = \<const0> ;
assign probe_out86[0] = \<const0> ;
assign probe_out87[0] = \<const0> ;
assign probe_out88[0] = \<const0> ;
assign probe_out89[0] = \<const0> ;
assign probe_out9[0] = \<const0> ;
assign probe_out90[0] = \<const0> ;
assign probe_out91[0] = \<const0> ;
assign probe_out92[0] = \<const0> ;
assign probe_out93[0] = \<const0> ;
assign probe_out94[0] = \<const0> ;
assign probe_out95[0] = \<const0> ;
assign probe_out96[0] = \<const0> ;
assign probe_out97[0] = \<const0> ;
assign probe_out98[0] = \<const0> ;
assign probe_out99[0] = \<const0> ;
vio_0_vio_v3_0_13_decoder DECODER_INST
(.\Bus_Data_out_reg[11] (Bus_Data_out),
.E(DECODER_INST_n_4),
.Q({\bus_data_int_reg_n_0_[15] ,\bus_data_int_reg_n_0_[14] ,\bus_data_int_reg_n_0_[13] ,\bus_data_int_reg_n_0_[12] ,\bus_data_int_reg_n_0_[11] ,\bus_data_int_reg_n_0_[10] ,\bus_data_int_reg_n_0_[9] ,\bus_data_int_reg_n_0_[8] ,\bus_data_int_reg_n_0_[7] ,\bus_data_int_reg_n_0_[6] ,\bus_data_int_reg_n_0_[5] ,\bus_data_int_reg_n_0_[4] ,\bus_data_int_reg_n_0_[3] ,\bus_data_int_reg_n_0_[2] ,p_0_in,\bus_data_int_reg_n_0_[0] }),
.out(bus_clk),
.s_daddr_o(bus_addr),
.s_den_o(bus_den),
.s_do_i(bus_do),
.s_drdy_i(bus_drdy),
.s_dwe_o(bus_dwe),
.s_rst_o(bus_rst),
.\wr_en_reg[4]_0 (DECODER_INST_n_1),
.\wr_en_reg[4]_1 (DECODER_INST_n_2),
.\wr_en_reg[4]_2 (DECODER_INST_n_3));
GND GND
(.G(\<const0> ));
vio_0_vio_v3_0_13_probe_in_one PROBE_IN_INST
(.D({probe_in3,probe_in2,probe_in1,probe_in0}),
.E(DECODER_INST_n_4),
.Q(Bus_Data_out),
.clk(clk),
.out(bus_clk),
.s_daddr_o(bus_addr[2:0]),
.s_den_o(bus_den),
.s_dwe_o(bus_dwe),
.s_rst_o(bus_rst),
.\wr_en[4]_i_3 (DECODER_INST_n_1),
.\wr_en[4]_i_4 (DECODER_INST_n_3),
.\wr_en[4]_i_5 (DECODER_INST_n_2));
(* C_BUILD_REVISION = "0" *)
(* C_CORE_INFO1 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* C_CORE_INFO2 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* C_CORE_MAJOR_VER = "2" *)
(* C_CORE_MINOR_VER = "0" *)
(* C_CORE_TYPE = "2" *)
(* C_CSE_DRV_VER = "1" *)
(* C_MAJOR_VERSION = "2013" *)
(* C_MINOR_VERSION = "1" *)
(* C_NEXT_SLAVE = "0" *)
(* C_PIPE_IFACE = "0" *)
(* C_USE_TEST_REG = "1" *)
(* C_XDEVICEFAMILY = "kintex7" *)
(* C_XSDB_SLAVE_TYPE = "33" *)
(* DONT_TOUCH *)
vio_0_xsdbs_v1_0_2_xsdbs U_XSDB_SLAVE
(.s_daddr_o(bus_addr),
.s_dclk_o(bus_clk),
.s_den_o(bus_den),
.s_di_o(bus_di),
.s_do_i(bus_do),
.s_drdy_i(bus_drdy),
.s_dwe_o(bus_dwe),
.s_rst_o(bus_rst),
.sl_iport_i(sl_iport0),
.sl_oport_o(sl_oport0));
FDRE \bus_data_int_reg[0]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[0]),
.Q(\bus_data_int_reg_n_0_[0] ),
.R(1'b0));
FDRE \bus_data_int_reg[10]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[10]),
.Q(\bus_data_int_reg_n_0_[10] ),
.R(1'b0));
FDRE \bus_data_int_reg[11]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[11]),
.Q(\bus_data_int_reg_n_0_[11] ),
.R(1'b0));
FDRE \bus_data_int_reg[12]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[12]),
.Q(\bus_data_int_reg_n_0_[12] ),
.R(1'b0));
FDRE \bus_data_int_reg[13]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[13]),
.Q(\bus_data_int_reg_n_0_[13] ),
.R(1'b0));
FDRE \bus_data_int_reg[14]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[14]),
.Q(\bus_data_int_reg_n_0_[14] ),
.R(1'b0));
FDRE \bus_data_int_reg[15]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[15]),
.Q(\bus_data_int_reg_n_0_[15] ),
.R(1'b0));
FDRE \bus_data_int_reg[1]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[1]),
.Q(p_0_in),
.R(1'b0));
FDRE \bus_data_int_reg[2]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[2]),
.Q(\bus_data_int_reg_n_0_[2] ),
.R(1'b0));
FDRE \bus_data_int_reg[3]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[3]),
.Q(\bus_data_int_reg_n_0_[3] ),
.R(1'b0));
FDRE \bus_data_int_reg[4]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[4]),
.Q(\bus_data_int_reg_n_0_[4] ),
.R(1'b0));
FDRE \bus_data_int_reg[5]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[5]),
.Q(\bus_data_int_reg_n_0_[5] ),
.R(1'b0));
FDRE \bus_data_int_reg[6]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[6]),
.Q(\bus_data_int_reg_n_0_[6] ),
.R(1'b0));
FDRE \bus_data_int_reg[7]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[7]),
.Q(\bus_data_int_reg_n_0_[7] ),
.R(1'b0));
FDRE \bus_data_int_reg[8]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[8]),
.Q(\bus_data_int_reg_n_0_[8] ),
.R(1'b0));
FDRE \bus_data_int_reg[9]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[9]),
.Q(\bus_data_int_reg_n_0_[9] ),
.R(1'b0));
endmodule
(* C_BUILD_REVISION = "0" *) (* C_CORE_INFO1 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_CORE_INFO2 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* C_CORE_MAJOR_VER = "2" *) (* C_CORE_MINOR_VER = "0" *) (* C_CORE_TYPE = "2" *)
(* C_CSE_DRV_VER = "1" *) (* C_MAJOR_VERSION = "2013" *) (* C_MINOR_VERSION = "1" *)
(* C_NEXT_SLAVE = "0" *) (* C_PIPE_IFACE = "0" *) (* C_USE_TEST_REG = "1" *)
(* C_XDEVICEFAMILY = "kintex7" *) (* C_XSDB_SLAVE_TYPE = "33" *) (* ORIG_REF_NAME = "xsdbs_v1_0_2_xsdbs" *)
(* dont_touch = "true" *)
module vio_0_xsdbs_v1_0_2_xsdbs
(s_rst_o,
s_dclk_o,
s_den_o,
s_dwe_o,
s_daddr_o,
s_di_o,
sl_oport_o,
s_do_i,
sl_iport_i,
s_drdy_i);
output s_rst_o;
output s_dclk_o;
output s_den_o;
output s_dwe_o;
output [16:0]s_daddr_o;
output [15:0]s_di_o;
output [16:0]sl_oport_o;
input [15:0]s_do_i;
input [36:0]sl_iport_i;
input s_drdy_i;
wire [8:0]reg_do;
wire \reg_do[10]_i_1_n_0 ;
wire \reg_do[10]_i_2_n_0 ;
wire \reg_do[15]_i_1_n_0 ;
wire \reg_do[1]_i_2_n_0 ;
wire \reg_do[2]_i_1_n_0 ;
wire \reg_do[3]_i_1_n_0 ;
wire \reg_do[4]_i_1_n_0 ;
wire \reg_do[5]_i_2_n_0 ;
wire \reg_do[6]_i_1_n_0 ;
wire \reg_do[7]_i_1_n_0 ;
wire \reg_do[8]_i_2_n_0 ;
wire \reg_do[9]_i_1_n_0 ;
wire \reg_do_reg_n_0_[0] ;
wire \reg_do_reg_n_0_[10] ;
wire \reg_do_reg_n_0_[11] ;
wire \reg_do_reg_n_0_[12] ;
wire \reg_do_reg_n_0_[13] ;
wire \reg_do_reg_n_0_[14] ;
wire \reg_do_reg_n_0_[15] ;
wire \reg_do_reg_n_0_[1] ;
wire \reg_do_reg_n_0_[2] ;
wire \reg_do_reg_n_0_[3] ;
wire \reg_do_reg_n_0_[4] ;
wire \reg_do_reg_n_0_[5] ;
wire \reg_do_reg_n_0_[6] ;
wire \reg_do_reg_n_0_[7] ;
wire \reg_do_reg_n_0_[8] ;
wire \reg_do_reg_n_0_[9] ;
wire reg_drdy;
wire reg_drdy_i_1_n_0;
wire [15:0]reg_test;
wire reg_test0;
wire s_den_o;
wire s_den_o_INST_0_i_1_n_0;
wire [15:0]s_do_i;
wire s_drdy_i;
wire [36:0]sl_iport_i;
wire [16:0]sl_oport_o;
assign s_daddr_o[16:0] = sl_iport_i[20:4];
assign s_dclk_o = sl_iport_i[1];
assign s_di_o[15:0] = sl_iport_i[36:21];
assign s_dwe_o = sl_iport_i[3];
assign s_rst_o = sl_iport_i[0];
LUT6 #(
.INIT(64'hBAAAFFFFAAAAAAAA))
\reg_do[0]_i_1
(.I0(\reg_do[5]_i_2_n_0 ),
.I1(sl_iport_i[4]),
.I2(reg_test[0]),
.I3(sl_iport_i[6]),
.I4(sl_iport_i[5]),
.I5(sl_iport_i[8]),
.O(reg_do[0]));
LUT3 #(
.INIT(8'h40))
\reg_do[10]_i_1
(.I0(sl_iport_i[5]),
.I1(\reg_do[8]_i_2_n_0 ),
.I2(sl_iport_i[4]),
.O(\reg_do[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h0800))
\reg_do[10]_i_2
(.I0(\reg_do[8]_i_2_n_0 ),
.I1(sl_iport_i[5]),
.I2(sl_iport_i[4]),
.I3(reg_test[10]),
.O(\reg_do[10]_i_2_n_0 ));
LUT3 #(
.INIT(8'hF7))
\reg_do[15]_i_1
(.I0(\reg_do[8]_i_2_n_0 ),
.I1(sl_iport_i[5]),
.I2(sl_iport_i[4]),
.O(\reg_do[15]_i_1_n_0 ));
LUT5 #(
.INIT(32'h20220000))
\reg_do[1]_i_1
(.I0(sl_iport_i[5]),
.I1(sl_iport_i[4]),
.I2(reg_test[1]),
.I3(sl_iport_i[6]),
.I4(\reg_do[1]_i_2_n_0 ),
.O(reg_do[1]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h00800000))
\reg_do[1]_i_2
(.I0(sl_iport_i[8]),
.I1(sl_iport_i[10]),
.I2(sl_iport_i[11]),
.I3(sl_iport_i[7]),
.I4(sl_iport_i[9]),
.O(\reg_do[1]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h0800))
\reg_do[2]_i_1
(.I0(\reg_do[8]_i_2_n_0 ),
.I1(sl_iport_i[5]),
.I2(sl_iport_i[4]),
.I3(reg_test[2]),
.O(\reg_do[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h0800))
\reg_do[3]_i_1
(.I0(\reg_do[8]_i_2_n_0 ),
.I1(sl_iport_i[5]),
.I2(sl_iport_i[4]),
.I3(reg_test[3]),
.O(\reg_do[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h0800))
\reg_do[4]_i_1
(.I0(\reg_do[8]_i_2_n_0 ),
.I1(sl_iport_i[5]),
.I2(sl_iport_i[4]),
.I3(reg_test[4]),
.O(\reg_do[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF00800044))
\reg_do[5]_i_1
(.I0(sl_iport_i[6]),
.I1(sl_iport_i[8]),
.I2(reg_test[5]),
.I3(sl_iport_i[4]),
.I4(sl_iport_i[5]),
.I5(\reg_do[5]_i_2_n_0 ),
.O(reg_do[5]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hBFFFFFFC))
\reg_do[5]_i_2
(.I0(sl_iport_i[7]),
.I1(sl_iport_i[8]),
.I2(sl_iport_i[11]),
.I3(sl_iport_i[10]),
.I4(sl_iport_i[9]),
.O(\reg_do[5]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h0800))
\reg_do[6]_i_1
(.I0(\reg_do[8]_i_2_n_0 ),
.I1(sl_iport_i[5]),
.I2(sl_iport_i[4]),
.I3(reg_test[6]),
.O(\reg_do[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h0800))
\reg_do[7]_i_1
(.I0(\reg_do[8]_i_2_n_0 ),
.I1(sl_iport_i[5]),
.I2(sl_iport_i[4]),
.I3(reg_test[7]),
.O(\reg_do[7]_i_1_n_0 ));
LUT4 #(
.INIT(16'h2F00))
\reg_do[8]_i_1
(.I0(reg_test[8]),
.I1(sl_iport_i[4]),
.I2(sl_iport_i[5]),
.I3(\reg_do[8]_i_2_n_0 ),
.O(reg_do[8]));
LUT6 #(
.INIT(64'h2000000000000000))
\reg_do[8]_i_2
(.I0(sl_iport_i[9]),
.I1(sl_iport_i[7]),
.I2(sl_iport_i[11]),
.I3(sl_iport_i[10]),
.I4(sl_iport_i[8]),
.I5(sl_iport_i[6]),
.O(\reg_do[8]_i_2_n_0 ));
LUT5 #(
.INIT(32'h0C008000))
\reg_do[9]_i_1
(.I0(reg_test[9]),
.I1(\reg_do[1]_i_2_n_0 ),
.I2(sl_iport_i[6]),
.I3(sl_iport_i[5]),
.I4(sl_iport_i[4]),
.O(\reg_do[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[0]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_do[0]),
.Q(\reg_do_reg_n_0_[0] ),
.R(1'b0));
FDSE #(
.INIT(1'b0))
\reg_do_reg[10]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(\reg_do[10]_i_2_n_0 ),
.Q(\reg_do_reg_n_0_[10] ),
.S(\reg_do[10]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[11]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_test[11]),
.Q(\reg_do_reg_n_0_[11] ),
.R(\reg_do[15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[12]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_test[12]),
.Q(\reg_do_reg_n_0_[12] ),
.R(\reg_do[15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[13]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_test[13]),
.Q(\reg_do_reg_n_0_[13] ),
.R(\reg_do[15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[14]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_test[14]),
.Q(\reg_do_reg_n_0_[14] ),
.R(\reg_do[15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[15]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_test[15]),
.Q(\reg_do_reg_n_0_[15] ),
.R(\reg_do[15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[1]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_do[1]),
.Q(\reg_do_reg_n_0_[1] ),
.R(1'b0));
FDSE #(
.INIT(1'b0))
\reg_do_reg[2]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(\reg_do[2]_i_1_n_0 ),
.Q(\reg_do_reg_n_0_[2] ),
.S(\reg_do[10]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\reg_do_reg[3]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(\reg_do[3]_i_1_n_0 ),
.Q(\reg_do_reg_n_0_[3] ),
.S(\reg_do[10]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\reg_do_reg[4]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(\reg_do[4]_i_1_n_0 ),
.Q(\reg_do_reg_n_0_[4] ),
.S(\reg_do[10]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[5]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_do[5]),
.Q(\reg_do_reg_n_0_[5] ),
.R(1'b0));
FDSE #(
.INIT(1'b0))
\reg_do_reg[6]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(\reg_do[6]_i_1_n_0 ),
.Q(\reg_do_reg_n_0_[6] ),
.S(\reg_do[10]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\reg_do_reg[7]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(\reg_do[7]_i_1_n_0 ),
.Q(\reg_do_reg_n_0_[7] ),
.S(\reg_do[10]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[8]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_do[8]),
.Q(\reg_do_reg_n_0_[8] ),
.R(1'b0));
FDSE #(
.INIT(1'b0))
\reg_do_reg[9]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(\reg_do[9]_i_1_n_0 ),
.Q(\reg_do_reg_n_0_[9] ),
.S(\reg_do[10]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000080000000))
reg_drdy_i_1
(.I0(sl_iport_i[2]),
.I1(s_den_o_INST_0_i_1_n_0),
.I2(sl_iport_i[12]),
.I3(sl_iport_i[13]),
.I4(sl_iport_i[14]),
.I5(sl_iport_i[0]),
.O(reg_drdy_i_1_n_0));
FDRE #(
.INIT(1'b0))
reg_drdy_reg
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_drdy_i_1_n_0),
.Q(reg_drdy),
.R(1'b0));
LUT6 #(
.INIT(64'h8000000000000000))
\reg_test[15]_i_1
(.I0(sl_iport_i[3]),
.I1(sl_iport_i[2]),
.I2(sl_iport_i[14]),
.I3(sl_iport_i[13]),
.I4(sl_iport_i[12]),
.I5(s_den_o_INST_0_i_1_n_0),
.O(reg_test0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[0]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[21]),
.Q(reg_test[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[10]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[31]),
.Q(reg_test[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[11]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[32]),
.Q(reg_test[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[12]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[33]),
.Q(reg_test[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[13]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[34]),
.Q(reg_test[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[14]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[35]),
.Q(reg_test[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[15]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[36]),
.Q(reg_test[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[1]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[22]),
.Q(reg_test[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[2]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[23]),
.Q(reg_test[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[3]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[24]),
.Q(reg_test[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[4]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[25]),
.Q(reg_test[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[5]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[26]),
.Q(reg_test[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[6]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[27]),
.Q(reg_test[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[7]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[28]),
.Q(reg_test[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[8]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[29]),
.Q(reg_test[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[9]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[30]),
.Q(reg_test[9]),
.R(1'b0));
LUT5 #(
.INIT(32'h2AAAAAAA))
s_den_o_INST_0
(.I0(sl_iport_i[2]),
.I1(sl_iport_i[14]),
.I2(sl_iport_i[13]),
.I3(sl_iport_i[12]),
.I4(s_den_o_INST_0_i_1_n_0),
.O(s_den_o));
LUT6 #(
.INIT(64'h8000000000000000))
s_den_o_INST_0_i_1
(.I0(sl_iport_i[15]),
.I1(sl_iport_i[16]),
.I2(sl_iport_i[17]),
.I3(sl_iport_i[18]),
.I4(sl_iport_i[20]),
.I5(sl_iport_i[19]),
.O(s_den_o_INST_0_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'hE))
\sl_oport_o[0]_INST_0
(.I0(s_drdy_i),
.I1(reg_drdy),
.O(sl_oport_o[0]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[10]_INST_0
(.I0(\reg_do_reg_n_0_[9] ),
.I1(s_do_i[9]),
.I2(reg_drdy),
.O(sl_oport_o[10]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[11]_INST_0
(.I0(\reg_do_reg_n_0_[10] ),
.I1(s_do_i[10]),
.I2(reg_drdy),
.O(sl_oport_o[11]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[12]_INST_0
(.I0(\reg_do_reg_n_0_[11] ),
.I1(s_do_i[11]),
.I2(reg_drdy),
.O(sl_oport_o[12]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[13]_INST_0
(.I0(\reg_do_reg_n_0_[12] ),
.I1(s_do_i[12]),
.I2(reg_drdy),
.O(sl_oport_o[13]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[14]_INST_0
(.I0(\reg_do_reg_n_0_[13] ),
.I1(s_do_i[13]),
.I2(reg_drdy),
.O(sl_oport_o[14]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[15]_INST_0
(.I0(\reg_do_reg_n_0_[14] ),
.I1(s_do_i[14]),
.I2(reg_drdy),
.O(sl_oport_o[15]));
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[16]_INST_0
(.I0(\reg_do_reg_n_0_[15] ),
.I1(s_do_i[15]),
.I2(reg_drdy),
.O(sl_oport_o[16]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[1]_INST_0
(.I0(\reg_do_reg_n_0_[0] ),
.I1(s_do_i[0]),
.I2(reg_drdy),
.O(sl_oport_o[1]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[2]_INST_0
(.I0(\reg_do_reg_n_0_[1] ),
.I1(s_do_i[1]),
.I2(reg_drdy),
.O(sl_oport_o[2]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[3]_INST_0
(.I0(\reg_do_reg_n_0_[2] ),
.I1(s_do_i[2]),
.I2(reg_drdy),
.O(sl_oport_o[3]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[4]_INST_0
(.I0(\reg_do_reg_n_0_[3] ),
.I1(s_do_i[3]),
.I2(reg_drdy),
.O(sl_oport_o[4]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[5]_INST_0
(.I0(\reg_do_reg_n_0_[4] ),
.I1(s_do_i[4]),
.I2(reg_drdy),
.O(sl_oport_o[5]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[6]_INST_0
(.I0(\reg_do_reg_n_0_[5] ),
.I1(s_do_i[5]),
.I2(reg_drdy),
.O(sl_oport_o[6]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[7]_INST_0
(.I0(\reg_do_reg_n_0_[6] ),
.I1(s_do_i[6]),
.I2(reg_drdy),
.O(sl_oport_o[7]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[8]_INST_0
(.I0(\reg_do_reg_n_0_[7] ),
.I1(s_do_i[7]),
.I2(reg_drdy),
.O(sl_oport_o[8]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[9]_INST_0
(.I0(\reg_do_reg_n_0_[8] ),
.I1(s_do_i[8]),
.I2(reg_drdy),
.O(sl_oport_o[9]));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__MUX2_PP_SYMBOL_V
`define SKY130_FD_SC_LS__MUX2_PP_SYMBOL_V
/**
* mux2: 2-input multiplexer.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__mux2 (
//# {{data|Data Signals}}
input A0 ,
input A1 ,
output X ,
//# {{control|Control Signals}}
input S ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__MUX2_PP_SYMBOL_V
|
// (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:hls:pointer_basic:1.0
// IP Revision: 1909160459
(* X_CORE_INFO = "pointer_basic,Vivado 2018.2" *)
(* CHECK_LICENSE_TYPE = "design_1_pointer_basic_0_1,pointer_basic,{}" *)
(* CORE_GENERATION_INFO = "design_1_pointer_basic_0_1,pointer_basic,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=hls,x_ipName=pointer_basic,x_ipVersion=1.0,x_ipCoreRevision=1909160459,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_S_AXI_POINTER_BASIC_IO_ADDR_WIDTH=5,C_S_AXI_POINTER_BASIC_IO_DATA_WIDTH=32}" *)
(* IP_DEFINITION_SOURCE = "HLS" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_pointer_basic_0_1 (
s_axi_pointer_basic_io_AWADDR,
s_axi_pointer_basic_io_AWVALID,
s_axi_pointer_basic_io_AWREADY,
s_axi_pointer_basic_io_WDATA,
s_axi_pointer_basic_io_WSTRB,
s_axi_pointer_basic_io_WVALID,
s_axi_pointer_basic_io_WREADY,
s_axi_pointer_basic_io_BRESP,
s_axi_pointer_basic_io_BVALID,
s_axi_pointer_basic_io_BREADY,
s_axi_pointer_basic_io_ARADDR,
s_axi_pointer_basic_io_ARVALID,
s_axi_pointer_basic_io_ARREADY,
s_axi_pointer_basic_io_RDATA,
s_axi_pointer_basic_io_RRESP,
s_axi_pointer_basic_io_RVALID,
s_axi_pointer_basic_io_RREADY,
ap_clk,
ap_rst_n,
interrupt
);
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io AWADDR" *)
input wire [4 : 0] s_axi_pointer_basic_io_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io AWVALID" *)
input wire s_axi_pointer_basic_io_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io AWREADY" *)
output wire s_axi_pointer_basic_io_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io WDATA" *)
input wire [31 : 0] s_axi_pointer_basic_io_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io WSTRB" *)
input wire [3 : 0] s_axi_pointer_basic_io_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io WVALID" *)
input wire s_axi_pointer_basic_io_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io WREADY" *)
output wire s_axi_pointer_basic_io_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io BRESP" *)
output wire [1 : 0] s_axi_pointer_basic_io_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io BVALID" *)
output wire s_axi_pointer_basic_io_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io BREADY" *)
input wire s_axi_pointer_basic_io_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io ARADDR" *)
input wire [4 : 0] s_axi_pointer_basic_io_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io ARVALID" *)
input wire s_axi_pointer_basic_io_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io ARREADY" *)
output wire s_axi_pointer_basic_io_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io RDATA" *)
output wire [31 : 0] s_axi_pointer_basic_io_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io RRESP" *)
output wire [1 : 0] s_axi_pointer_basic_io_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io RVALID" *)
output wire s_axi_pointer_basic_io_RVALID;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_pointer_basic_io, ADDR_WIDTH 5, DATA_WIDTH 32, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 50\
000000, ID_WIDTH 0, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_2_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io RREADY" *)
input wire s_axi_pointer_basic_io_RREADY;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ap_clk, ASSOCIATED_BUSIF s_axi_pointer_basic_io, ASSOCIATED_RESET ap_rst_n, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 50000000, PHASE 0.000, CLK\
_DOMAIN design_1_processing_system7_0_2_FCLK_CLK0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk CLK" *)
input wire ap_clk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ap_rst_n, POLARITY ACTIVE_LOW, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {RST {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 ap_rst_n RST" *)
input wire ap_rst_n;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME interrupt, SENSITIVITY LEVEL_HIGH, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {INTERRUPT {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, PortWidth 1" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT" *)
output wire interrupt;
pointer_basic #(
.C_S_AXI_POINTER_BASIC_IO_ADDR_WIDTH(5),
.C_S_AXI_POINTER_BASIC_IO_DATA_WIDTH(32)
) inst (
.s_axi_pointer_basic_io_AWADDR(s_axi_pointer_basic_io_AWADDR),
.s_axi_pointer_basic_io_AWVALID(s_axi_pointer_basic_io_AWVALID),
.s_axi_pointer_basic_io_AWREADY(s_axi_pointer_basic_io_AWREADY),
.s_axi_pointer_basic_io_WDATA(s_axi_pointer_basic_io_WDATA),
.s_axi_pointer_basic_io_WSTRB(s_axi_pointer_basic_io_WSTRB),
.s_axi_pointer_basic_io_WVALID(s_axi_pointer_basic_io_WVALID),
.s_axi_pointer_basic_io_WREADY(s_axi_pointer_basic_io_WREADY),
.s_axi_pointer_basic_io_BRESP(s_axi_pointer_basic_io_BRESP),
.s_axi_pointer_basic_io_BVALID(s_axi_pointer_basic_io_BVALID),
.s_axi_pointer_basic_io_BREADY(s_axi_pointer_basic_io_BREADY),
.s_axi_pointer_basic_io_ARADDR(s_axi_pointer_basic_io_ARADDR),
.s_axi_pointer_basic_io_ARVALID(s_axi_pointer_basic_io_ARVALID),
.s_axi_pointer_basic_io_ARREADY(s_axi_pointer_basic_io_ARREADY),
.s_axi_pointer_basic_io_RDATA(s_axi_pointer_basic_io_RDATA),
.s_axi_pointer_basic_io_RRESP(s_axi_pointer_basic_io_RRESP),
.s_axi_pointer_basic_io_RVALID(s_axi_pointer_basic_io_RVALID),
.s_axi_pointer_basic_io_RREADY(s_axi_pointer_basic_io_RREADY),
.ap_clk(ap_clk),
.ap_rst_n(ap_rst_n),
.interrupt(interrupt)
);
endmodule
|
/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.4.0.80 */
/* Module Version: 6.4 */
/* /usr/local/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n ram -lang verilog -synth synplify -bus_exp 7 -bb -arch xo2c00 -type bram -wp 10 -rp 0011 -rdata_width 8 -data_width 8 -num_rows 16384 -outdata REGISTERED -cascade -1 -resetmode SYNC -sync_reset -mem_init0 */
/* Thu Jun 25 22:38:12 2015 */
`timescale 1 ns / 1 ps
module ram (WrAddress, RdAddress, Data, WE, RdClock, RdClockEn, Reset,
WrClock, WrClockEn, Q)/* synthesis NGD_DRC_MASK=1 */;
input wire [13:0] WrAddress;
input wire [13:0] RdAddress;
input wire [7:0] Data;
input wire WE;
input wire RdClock;
input wire RdClockEn;
input wire Reset;
input wire WrClock;
input wire WrClockEn;
output wire [7:0] Q;
wire scuba_vhi;
wire scuba_vlo;
wire raddr13_ff;
wire mdout1_1_0;
wire mdout1_0_0;
wire mdout1_1_1;
wire mdout1_0_1;
wire mdout1_1_2;
wire mdout1_0_2;
wire mdout1_1_3;
wire mdout1_0_3;
wire mdout1_1_4;
wire mdout1_0_4;
wire mdout1_1_5;
wire mdout1_0_5;
wire mdout1_1_6;
wire mdout1_0_6;
wire raddr13_ff2;
wire mdout1_1_7;
wire mdout1_0_7;
VHI scuba_vhi_inst (.Z(scuba_vhi));
defparam ram_0_0_15.INIT_DATA = "STATIC" ;
defparam ram_0_0_15.ASYNC_RESET_RELEASE = "SYNC" ;
defparam ram_0_0_15.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_0_15.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_0_15.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_0_15.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_0_15.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_0_15.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_0_15.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_0_15.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_0_15.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_0_15.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_0_15.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_0_15.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_0_15.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_0_15.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_0_15.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_0_15.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_0_15.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_0_15.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_0_15.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_0_15.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_0_15.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_0_15.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_0_15.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_0_15.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_0_15.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_0_15.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_0_15.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_0_15.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_0_15.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_0_15.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_0_15.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_0_15.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_0_15.CSDECODE_B = "0b000" ;
defparam ram_0_0_15.CSDECODE_A = "0b000" ;
defparam ram_0_0_15.WRITEMODE_B = "NORMAL" ;
defparam ram_0_0_15.WRITEMODE_A = "NORMAL" ;
defparam ram_0_0_15.GSR = "ENABLED" ;
defparam ram_0_0_15.RESETMODE = "SYNC" ;
defparam ram_0_0_15.REGMODE_B = "OUTREG" ;
defparam ram_0_0_15.REGMODE_A = "OUTREG" ;
defparam ram_0_0_15.DATA_WIDTH_B = 1 ;
defparam ram_0_0_15.DATA_WIDTH_A = 1 ;
DP8KC ram_0_0_15 (.DIA8(scuba_vlo), .DIA7(scuba_vlo), .DIA6(scuba_vlo),
.DIA5(scuba_vlo), .DIA4(scuba_vlo), .DIA3(scuba_vlo), .DIA2(scuba_vlo),
.DIA1(Data[0]), .DIA0(scuba_vlo), .ADA12(WrAddress[12]), .ADA11(WrAddress[11]),
.ADA10(WrAddress[10]), .ADA9(WrAddress[9]), .ADA8(WrAddress[8]),
.ADA7(WrAddress[7]), .ADA6(WrAddress[6]), .ADA5(WrAddress[5]), .ADA4(WrAddress[4]),
.ADA3(WrAddress[3]), .ADA2(WrAddress[2]), .ADA1(WrAddress[1]), .ADA0(WrAddress[0]),
.CEA(WrClockEn), .OCEA(WrClockEn), .CLKA(WrClock), .WEA(WE), .CSA2(scuba_vlo),
.CSA1(scuba_vlo), .CSA0(WrAddress[13]), .RSTA(Reset), .DIB8(scuba_vlo),
.DIB7(scuba_vlo), .DIB6(scuba_vlo), .DIB5(scuba_vlo), .DIB4(scuba_vlo),
.DIB3(scuba_vlo), .DIB2(scuba_vlo), .DIB1(scuba_vlo), .DIB0(scuba_vlo),
.ADB12(RdAddress[12]), .ADB11(RdAddress[11]), .ADB10(RdAddress[10]),
.ADB9(RdAddress[9]), .ADB8(RdAddress[8]), .ADB7(RdAddress[7]), .ADB6(RdAddress[6]),
.ADB5(RdAddress[5]), .ADB4(RdAddress[4]), .ADB3(RdAddress[3]), .ADB2(RdAddress[2]),
.ADB1(RdAddress[1]), .ADB0(RdAddress[0]), .CEB(RdClockEn), .OCEB(RdClockEn),
.CLKB(RdClock), .WEB(scuba_vlo), .CSB2(scuba_vlo), .CSB1(scuba_vlo),
.CSB0(RdAddress[13]), .RSTB(Reset), .DOA8(), .DOA7(), .DOA6(), .DOA5(),
.DOA4(), .DOA3(), .DOA2(), .DOA1(), .DOA0(), .DOB8(), .DOB7(), .DOB6(),
.DOB5(), .DOB4(), .DOB3(), .DOB2(), .DOB1(), .DOB0(mdout1_0_0))
/* synthesis MEM_LPC_FILE="ram.lpc" */
/* synthesis MEM_INIT_FILE="INIT_ALL_0s" */;
defparam ram_0_1_14.INIT_DATA = "STATIC" ;
defparam ram_0_1_14.ASYNC_RESET_RELEASE = "SYNC" ;
defparam ram_0_1_14.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_1_14.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_1_14.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_1_14.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_1_14.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_1_14.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_1_14.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_1_14.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_1_14.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_1_14.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_1_14.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_1_14.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_1_14.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_1_14.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_1_14.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_1_14.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_1_14.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_1_14.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_1_14.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_1_14.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_1_14.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_1_14.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_1_14.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_1_14.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_1_14.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_1_14.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_1_14.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_1_14.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_1_14.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_1_14.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_1_14.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_1_14.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_1_14.CSDECODE_B = "0b000" ;
defparam ram_0_1_14.CSDECODE_A = "0b000" ;
defparam ram_0_1_14.WRITEMODE_B = "NORMAL" ;
defparam ram_0_1_14.WRITEMODE_A = "NORMAL" ;
defparam ram_0_1_14.GSR = "ENABLED" ;
defparam ram_0_1_14.RESETMODE = "SYNC" ;
defparam ram_0_1_14.REGMODE_B = "OUTREG" ;
defparam ram_0_1_14.REGMODE_A = "OUTREG" ;
defparam ram_0_1_14.DATA_WIDTH_B = 1 ;
defparam ram_0_1_14.DATA_WIDTH_A = 1 ;
DP8KC ram_0_1_14 (.DIA8(scuba_vlo), .DIA7(scuba_vlo), .DIA6(scuba_vlo),
.DIA5(scuba_vlo), .DIA4(scuba_vlo), .DIA3(scuba_vlo), .DIA2(scuba_vlo),
.DIA1(Data[1]), .DIA0(scuba_vlo), .ADA12(WrAddress[12]), .ADA11(WrAddress[11]),
.ADA10(WrAddress[10]), .ADA9(WrAddress[9]), .ADA8(WrAddress[8]),
.ADA7(WrAddress[7]), .ADA6(WrAddress[6]), .ADA5(WrAddress[5]), .ADA4(WrAddress[4]),
.ADA3(WrAddress[3]), .ADA2(WrAddress[2]), .ADA1(WrAddress[1]), .ADA0(WrAddress[0]),
.CEA(WrClockEn), .OCEA(WrClockEn), .CLKA(WrClock), .WEA(WE), .CSA2(scuba_vlo),
.CSA1(scuba_vlo), .CSA0(WrAddress[13]), .RSTA(Reset), .DIB8(scuba_vlo),
.DIB7(scuba_vlo), .DIB6(scuba_vlo), .DIB5(scuba_vlo), .DIB4(scuba_vlo),
.DIB3(scuba_vlo), .DIB2(scuba_vlo), .DIB1(scuba_vlo), .DIB0(scuba_vlo),
.ADB12(RdAddress[12]), .ADB11(RdAddress[11]), .ADB10(RdAddress[10]),
.ADB9(RdAddress[9]), .ADB8(RdAddress[8]), .ADB7(RdAddress[7]), .ADB6(RdAddress[6]),
.ADB5(RdAddress[5]), .ADB4(RdAddress[4]), .ADB3(RdAddress[3]), .ADB2(RdAddress[2]),
.ADB1(RdAddress[1]), .ADB0(RdAddress[0]), .CEB(RdClockEn), .OCEB(RdClockEn),
.CLKB(RdClock), .WEB(scuba_vlo), .CSB2(scuba_vlo), .CSB1(scuba_vlo),
.CSB0(RdAddress[13]), .RSTB(Reset), .DOA8(), .DOA7(), .DOA6(), .DOA5(),
.DOA4(), .DOA3(), .DOA2(), .DOA1(), .DOA0(), .DOB8(), .DOB7(), .DOB6(),
.DOB5(), .DOB4(), .DOB3(), .DOB2(), .DOB1(), .DOB0(mdout1_0_1))
/* synthesis MEM_LPC_FILE="ram.lpc" */
/* synthesis MEM_INIT_FILE="INIT_ALL_0s" */;
defparam ram_0_2_13.INIT_DATA = "STATIC" ;
defparam ram_0_2_13.ASYNC_RESET_RELEASE = "SYNC" ;
defparam ram_0_2_13.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_2_13.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_2_13.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_2_13.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_2_13.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_2_13.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_2_13.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_2_13.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_2_13.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_2_13.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_2_13.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_2_13.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_2_13.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_2_13.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_2_13.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_2_13.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_2_13.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_2_13.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_2_13.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_2_13.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_2_13.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_2_13.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_2_13.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_2_13.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_2_13.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_2_13.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_2_13.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_2_13.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_2_13.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_2_13.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_2_13.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_2_13.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_2_13.CSDECODE_B = "0b000" ;
defparam ram_0_2_13.CSDECODE_A = "0b000" ;
defparam ram_0_2_13.WRITEMODE_B = "NORMAL" ;
defparam ram_0_2_13.WRITEMODE_A = "NORMAL" ;
defparam ram_0_2_13.GSR = "ENABLED" ;
defparam ram_0_2_13.RESETMODE = "SYNC" ;
defparam ram_0_2_13.REGMODE_B = "OUTREG" ;
defparam ram_0_2_13.REGMODE_A = "OUTREG" ;
defparam ram_0_2_13.DATA_WIDTH_B = 1 ;
defparam ram_0_2_13.DATA_WIDTH_A = 1 ;
DP8KC ram_0_2_13 (.DIA8(scuba_vlo), .DIA7(scuba_vlo), .DIA6(scuba_vlo),
.DIA5(scuba_vlo), .DIA4(scuba_vlo), .DIA3(scuba_vlo), .DIA2(scuba_vlo),
.DIA1(Data[2]), .DIA0(scuba_vlo), .ADA12(WrAddress[12]), .ADA11(WrAddress[11]),
.ADA10(WrAddress[10]), .ADA9(WrAddress[9]), .ADA8(WrAddress[8]),
.ADA7(WrAddress[7]), .ADA6(WrAddress[6]), .ADA5(WrAddress[5]), .ADA4(WrAddress[4]),
.ADA3(WrAddress[3]), .ADA2(WrAddress[2]), .ADA1(WrAddress[1]), .ADA0(WrAddress[0]),
.CEA(WrClockEn), .OCEA(WrClockEn), .CLKA(WrClock), .WEA(WE), .CSA2(scuba_vlo),
.CSA1(scuba_vlo), .CSA0(WrAddress[13]), .RSTA(Reset), .DIB8(scuba_vlo),
.DIB7(scuba_vlo), .DIB6(scuba_vlo), .DIB5(scuba_vlo), .DIB4(scuba_vlo),
.DIB3(scuba_vlo), .DIB2(scuba_vlo), .DIB1(scuba_vlo), .DIB0(scuba_vlo),
.ADB12(RdAddress[12]), .ADB11(RdAddress[11]), .ADB10(RdAddress[10]),
.ADB9(RdAddress[9]), .ADB8(RdAddress[8]), .ADB7(RdAddress[7]), .ADB6(RdAddress[6]),
.ADB5(RdAddress[5]), .ADB4(RdAddress[4]), .ADB3(RdAddress[3]), .ADB2(RdAddress[2]),
.ADB1(RdAddress[1]), .ADB0(RdAddress[0]), .CEB(RdClockEn), .OCEB(RdClockEn),
.CLKB(RdClock), .WEB(scuba_vlo), .CSB2(scuba_vlo), .CSB1(scuba_vlo),
.CSB0(RdAddress[13]), .RSTB(Reset), .DOA8(), .DOA7(), .DOA6(), .DOA5(),
.DOA4(), .DOA3(), .DOA2(), .DOA1(), .DOA0(), .DOB8(), .DOB7(), .DOB6(),
.DOB5(), .DOB4(), .DOB3(), .DOB2(), .DOB1(), .DOB0(mdout1_0_2))
/* synthesis MEM_LPC_FILE="ram.lpc" */
/* synthesis MEM_INIT_FILE="INIT_ALL_0s" */;
defparam ram_0_3_12.INIT_DATA = "STATIC" ;
defparam ram_0_3_12.ASYNC_RESET_RELEASE = "SYNC" ;
defparam ram_0_3_12.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_3_12.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_3_12.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_3_12.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_3_12.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_3_12.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_3_12.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_3_12.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_3_12.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_3_12.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_3_12.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_3_12.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_3_12.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_3_12.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_3_12.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_3_12.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_3_12.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_3_12.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_3_12.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_3_12.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_3_12.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_3_12.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_3_12.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_3_12.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_3_12.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_3_12.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_3_12.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_3_12.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_3_12.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_3_12.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_3_12.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_3_12.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_3_12.CSDECODE_B = "0b000" ;
defparam ram_0_3_12.CSDECODE_A = "0b000" ;
defparam ram_0_3_12.WRITEMODE_B = "NORMAL" ;
defparam ram_0_3_12.WRITEMODE_A = "NORMAL" ;
defparam ram_0_3_12.GSR = "ENABLED" ;
defparam ram_0_3_12.RESETMODE = "SYNC" ;
defparam ram_0_3_12.REGMODE_B = "OUTREG" ;
defparam ram_0_3_12.REGMODE_A = "OUTREG" ;
defparam ram_0_3_12.DATA_WIDTH_B = 1 ;
defparam ram_0_3_12.DATA_WIDTH_A = 1 ;
DP8KC ram_0_3_12 (.DIA8(scuba_vlo), .DIA7(scuba_vlo), .DIA6(scuba_vlo),
.DIA5(scuba_vlo), .DIA4(scuba_vlo), .DIA3(scuba_vlo), .DIA2(scuba_vlo),
.DIA1(Data[3]), .DIA0(scuba_vlo), .ADA12(WrAddress[12]), .ADA11(WrAddress[11]),
.ADA10(WrAddress[10]), .ADA9(WrAddress[9]), .ADA8(WrAddress[8]),
.ADA7(WrAddress[7]), .ADA6(WrAddress[6]), .ADA5(WrAddress[5]), .ADA4(WrAddress[4]),
.ADA3(WrAddress[3]), .ADA2(WrAddress[2]), .ADA1(WrAddress[1]), .ADA0(WrAddress[0]),
.CEA(WrClockEn), .OCEA(WrClockEn), .CLKA(WrClock), .WEA(WE), .CSA2(scuba_vlo),
.CSA1(scuba_vlo), .CSA0(WrAddress[13]), .RSTA(Reset), .DIB8(scuba_vlo),
.DIB7(scuba_vlo), .DIB6(scuba_vlo), .DIB5(scuba_vlo), .DIB4(scuba_vlo),
.DIB3(scuba_vlo), .DIB2(scuba_vlo), .DIB1(scuba_vlo), .DIB0(scuba_vlo),
.ADB12(RdAddress[12]), .ADB11(RdAddress[11]), .ADB10(RdAddress[10]),
.ADB9(RdAddress[9]), .ADB8(RdAddress[8]), .ADB7(RdAddress[7]), .ADB6(RdAddress[6]),
.ADB5(RdAddress[5]), .ADB4(RdAddress[4]), .ADB3(RdAddress[3]), .ADB2(RdAddress[2]),
.ADB1(RdAddress[1]), .ADB0(RdAddress[0]), .CEB(RdClockEn), .OCEB(RdClockEn),
.CLKB(RdClock), .WEB(scuba_vlo), .CSB2(scuba_vlo), .CSB1(scuba_vlo),
.CSB0(RdAddress[13]), .RSTB(Reset), .DOA8(), .DOA7(), .DOA6(), .DOA5(),
.DOA4(), .DOA3(), .DOA2(), .DOA1(), .DOA0(), .DOB8(), .DOB7(), .DOB6(),
.DOB5(), .DOB4(), .DOB3(), .DOB2(), .DOB1(), .DOB0(mdout1_0_3))
/* synthesis MEM_LPC_FILE="ram.lpc" */
/* synthesis MEM_INIT_FILE="INIT_ALL_0s" */;
defparam ram_0_4_11.INIT_DATA = "STATIC" ;
defparam ram_0_4_11.ASYNC_RESET_RELEASE = "SYNC" ;
defparam ram_0_4_11.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_4_11.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_4_11.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_4_11.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_4_11.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_4_11.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_4_11.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_4_11.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_4_11.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_4_11.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_4_11.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_4_11.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_4_11.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_4_11.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_4_11.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_4_11.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_4_11.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_4_11.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_4_11.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_4_11.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_4_11.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_4_11.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_4_11.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_4_11.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_4_11.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_4_11.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_4_11.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_4_11.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_4_11.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_4_11.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_4_11.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_4_11.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_4_11.CSDECODE_B = "0b000" ;
defparam ram_0_4_11.CSDECODE_A = "0b000" ;
defparam ram_0_4_11.WRITEMODE_B = "NORMAL" ;
defparam ram_0_4_11.WRITEMODE_A = "NORMAL" ;
defparam ram_0_4_11.GSR = "ENABLED" ;
defparam ram_0_4_11.RESETMODE = "SYNC" ;
defparam ram_0_4_11.REGMODE_B = "OUTREG" ;
defparam ram_0_4_11.REGMODE_A = "OUTREG" ;
defparam ram_0_4_11.DATA_WIDTH_B = 1 ;
defparam ram_0_4_11.DATA_WIDTH_A = 1 ;
DP8KC ram_0_4_11 (.DIA8(scuba_vlo), .DIA7(scuba_vlo), .DIA6(scuba_vlo),
.DIA5(scuba_vlo), .DIA4(scuba_vlo), .DIA3(scuba_vlo), .DIA2(scuba_vlo),
.DIA1(Data[4]), .DIA0(scuba_vlo), .ADA12(WrAddress[12]), .ADA11(WrAddress[11]),
.ADA10(WrAddress[10]), .ADA9(WrAddress[9]), .ADA8(WrAddress[8]),
.ADA7(WrAddress[7]), .ADA6(WrAddress[6]), .ADA5(WrAddress[5]), .ADA4(WrAddress[4]),
.ADA3(WrAddress[3]), .ADA2(WrAddress[2]), .ADA1(WrAddress[1]), .ADA0(WrAddress[0]),
.CEA(WrClockEn), .OCEA(WrClockEn), .CLKA(WrClock), .WEA(WE), .CSA2(scuba_vlo),
.CSA1(scuba_vlo), .CSA0(WrAddress[13]), .RSTA(Reset), .DIB8(scuba_vlo),
.DIB7(scuba_vlo), .DIB6(scuba_vlo), .DIB5(scuba_vlo), .DIB4(scuba_vlo),
.DIB3(scuba_vlo), .DIB2(scuba_vlo), .DIB1(scuba_vlo), .DIB0(scuba_vlo),
.ADB12(RdAddress[12]), .ADB11(RdAddress[11]), .ADB10(RdAddress[10]),
.ADB9(RdAddress[9]), .ADB8(RdAddress[8]), .ADB7(RdAddress[7]), .ADB6(RdAddress[6]),
.ADB5(RdAddress[5]), .ADB4(RdAddress[4]), .ADB3(RdAddress[3]), .ADB2(RdAddress[2]),
.ADB1(RdAddress[1]), .ADB0(RdAddress[0]), .CEB(RdClockEn), .OCEB(RdClockEn),
.CLKB(RdClock), .WEB(scuba_vlo), .CSB2(scuba_vlo), .CSB1(scuba_vlo),
.CSB0(RdAddress[13]), .RSTB(Reset), .DOA8(), .DOA7(), .DOA6(), .DOA5(),
.DOA4(), .DOA3(), .DOA2(), .DOA1(), .DOA0(), .DOB8(), .DOB7(), .DOB6(),
.DOB5(), .DOB4(), .DOB3(), .DOB2(), .DOB1(), .DOB0(mdout1_0_4))
/* synthesis MEM_LPC_FILE="ram.lpc" */
/* synthesis MEM_INIT_FILE="INIT_ALL_0s" */;
defparam ram_0_5_10.INIT_DATA = "STATIC" ;
defparam ram_0_5_10.ASYNC_RESET_RELEASE = "SYNC" ;
defparam ram_0_5_10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_5_10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_5_10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_5_10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_5_10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_5_10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_5_10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_5_10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_5_10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_5_10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_5_10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_5_10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_5_10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_5_10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_5_10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_5_10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_5_10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_5_10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_5_10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_5_10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_5_10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_5_10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_5_10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_5_10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_5_10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_5_10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_5_10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_5_10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_5_10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_5_10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_5_10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_5_10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_5_10.CSDECODE_B = "0b000" ;
defparam ram_0_5_10.CSDECODE_A = "0b000" ;
defparam ram_0_5_10.WRITEMODE_B = "NORMAL" ;
defparam ram_0_5_10.WRITEMODE_A = "NORMAL" ;
defparam ram_0_5_10.GSR = "ENABLED" ;
defparam ram_0_5_10.RESETMODE = "SYNC" ;
defparam ram_0_5_10.REGMODE_B = "OUTREG" ;
defparam ram_0_5_10.REGMODE_A = "OUTREG" ;
defparam ram_0_5_10.DATA_WIDTH_B = 1 ;
defparam ram_0_5_10.DATA_WIDTH_A = 1 ;
DP8KC ram_0_5_10 (.DIA8(scuba_vlo), .DIA7(scuba_vlo), .DIA6(scuba_vlo),
.DIA5(scuba_vlo), .DIA4(scuba_vlo), .DIA3(scuba_vlo), .DIA2(scuba_vlo),
.DIA1(Data[5]), .DIA0(scuba_vlo), .ADA12(WrAddress[12]), .ADA11(WrAddress[11]),
.ADA10(WrAddress[10]), .ADA9(WrAddress[9]), .ADA8(WrAddress[8]),
.ADA7(WrAddress[7]), .ADA6(WrAddress[6]), .ADA5(WrAddress[5]), .ADA4(WrAddress[4]),
.ADA3(WrAddress[3]), .ADA2(WrAddress[2]), .ADA1(WrAddress[1]), .ADA0(WrAddress[0]),
.CEA(WrClockEn), .OCEA(WrClockEn), .CLKA(WrClock), .WEA(WE), .CSA2(scuba_vlo),
.CSA1(scuba_vlo), .CSA0(WrAddress[13]), .RSTA(Reset), .DIB8(scuba_vlo),
.DIB7(scuba_vlo), .DIB6(scuba_vlo), .DIB5(scuba_vlo), .DIB4(scuba_vlo),
.DIB3(scuba_vlo), .DIB2(scuba_vlo), .DIB1(scuba_vlo), .DIB0(scuba_vlo),
.ADB12(RdAddress[12]), .ADB11(RdAddress[11]), .ADB10(RdAddress[10]),
.ADB9(RdAddress[9]), .ADB8(RdAddress[8]), .ADB7(RdAddress[7]), .ADB6(RdAddress[6]),
.ADB5(RdAddress[5]), .ADB4(RdAddress[4]), .ADB3(RdAddress[3]), .ADB2(RdAddress[2]),
.ADB1(RdAddress[1]), .ADB0(RdAddress[0]), .CEB(RdClockEn), .OCEB(RdClockEn),
.CLKB(RdClock), .WEB(scuba_vlo), .CSB2(scuba_vlo), .CSB1(scuba_vlo),
.CSB0(RdAddress[13]), .RSTB(Reset), .DOA8(), .DOA7(), .DOA6(), .DOA5(),
.DOA4(), .DOA3(), .DOA2(), .DOA1(), .DOA0(), .DOB8(), .DOB7(), .DOB6(),
.DOB5(), .DOB4(), .DOB3(), .DOB2(), .DOB1(), .DOB0(mdout1_0_5))
/* synthesis MEM_LPC_FILE="ram.lpc" */
/* synthesis MEM_INIT_FILE="INIT_ALL_0s" */;
defparam ram_0_6_9.INIT_DATA = "STATIC" ;
defparam ram_0_6_9.ASYNC_RESET_RELEASE = "SYNC" ;
defparam ram_0_6_9.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_6_9.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_6_9.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_6_9.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_6_9.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_6_9.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_6_9.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_6_9.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_6_9.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_6_9.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_6_9.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_6_9.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_6_9.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_6_9.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_6_9.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_6_9.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_6_9.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_6_9.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_6_9.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_6_9.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_6_9.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_6_9.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_6_9.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_6_9.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_6_9.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_6_9.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_6_9.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_6_9.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_6_9.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_6_9.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_6_9.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_6_9.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_6_9.CSDECODE_B = "0b000" ;
defparam ram_0_6_9.CSDECODE_A = "0b000" ;
defparam ram_0_6_9.WRITEMODE_B = "NORMAL" ;
defparam ram_0_6_9.WRITEMODE_A = "NORMAL" ;
defparam ram_0_6_9.GSR = "ENABLED" ;
defparam ram_0_6_9.RESETMODE = "SYNC" ;
defparam ram_0_6_9.REGMODE_B = "OUTREG" ;
defparam ram_0_6_9.REGMODE_A = "OUTREG" ;
defparam ram_0_6_9.DATA_WIDTH_B = 1 ;
defparam ram_0_6_9.DATA_WIDTH_A = 1 ;
DP8KC ram_0_6_9 (.DIA8(scuba_vlo), .DIA7(scuba_vlo), .DIA6(scuba_vlo),
.DIA5(scuba_vlo), .DIA4(scuba_vlo), .DIA3(scuba_vlo), .DIA2(scuba_vlo),
.DIA1(Data[6]), .DIA0(scuba_vlo), .ADA12(WrAddress[12]), .ADA11(WrAddress[11]),
.ADA10(WrAddress[10]), .ADA9(WrAddress[9]), .ADA8(WrAddress[8]),
.ADA7(WrAddress[7]), .ADA6(WrAddress[6]), .ADA5(WrAddress[5]), .ADA4(WrAddress[4]),
.ADA3(WrAddress[3]), .ADA2(WrAddress[2]), .ADA1(WrAddress[1]), .ADA0(WrAddress[0]),
.CEA(WrClockEn), .OCEA(WrClockEn), .CLKA(WrClock), .WEA(WE), .CSA2(scuba_vlo),
.CSA1(scuba_vlo), .CSA0(WrAddress[13]), .RSTA(Reset), .DIB8(scuba_vlo),
.DIB7(scuba_vlo), .DIB6(scuba_vlo), .DIB5(scuba_vlo), .DIB4(scuba_vlo),
.DIB3(scuba_vlo), .DIB2(scuba_vlo), .DIB1(scuba_vlo), .DIB0(scuba_vlo),
.ADB12(RdAddress[12]), .ADB11(RdAddress[11]), .ADB10(RdAddress[10]),
.ADB9(RdAddress[9]), .ADB8(RdAddress[8]), .ADB7(RdAddress[7]), .ADB6(RdAddress[6]),
.ADB5(RdAddress[5]), .ADB4(RdAddress[4]), .ADB3(RdAddress[3]), .ADB2(RdAddress[2]),
.ADB1(RdAddress[1]), .ADB0(RdAddress[0]), .CEB(RdClockEn), .OCEB(RdClockEn),
.CLKB(RdClock), .WEB(scuba_vlo), .CSB2(scuba_vlo), .CSB1(scuba_vlo),
.CSB0(RdAddress[13]), .RSTB(Reset), .DOA8(), .DOA7(), .DOA6(), .DOA5(),
.DOA4(), .DOA3(), .DOA2(), .DOA1(), .DOA0(), .DOB8(), .DOB7(), .DOB6(),
.DOB5(), .DOB4(), .DOB3(), .DOB2(), .DOB1(), .DOB0(mdout1_0_6))
/* synthesis MEM_LPC_FILE="ram.lpc" */
/* synthesis MEM_INIT_FILE="INIT_ALL_0s" */;
defparam ram_0_7_8.INIT_DATA = "STATIC" ;
defparam ram_0_7_8.ASYNC_RESET_RELEASE = "SYNC" ;
defparam ram_0_7_8.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_7_8.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_7_8.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_7_8.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_7_8.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_7_8.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_7_8.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_7_8.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_7_8.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_7_8.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_7_8.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_7_8.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_7_8.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_7_8.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_7_8.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_7_8.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_7_8.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_7_8.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_7_8.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_7_8.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_7_8.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_7_8.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_7_8.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_7_8.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_7_8.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_7_8.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_7_8.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_7_8.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_7_8.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_7_8.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_7_8.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_7_8.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_0_7_8.CSDECODE_B = "0b000" ;
defparam ram_0_7_8.CSDECODE_A = "0b000" ;
defparam ram_0_7_8.WRITEMODE_B = "NORMAL" ;
defparam ram_0_7_8.WRITEMODE_A = "NORMAL" ;
defparam ram_0_7_8.GSR = "ENABLED" ;
defparam ram_0_7_8.RESETMODE = "SYNC" ;
defparam ram_0_7_8.REGMODE_B = "OUTREG" ;
defparam ram_0_7_8.REGMODE_A = "OUTREG" ;
defparam ram_0_7_8.DATA_WIDTH_B = 1 ;
defparam ram_0_7_8.DATA_WIDTH_A = 1 ;
DP8KC ram_0_7_8 (.DIA8(scuba_vlo), .DIA7(scuba_vlo), .DIA6(scuba_vlo),
.DIA5(scuba_vlo), .DIA4(scuba_vlo), .DIA3(scuba_vlo), .DIA2(scuba_vlo),
.DIA1(Data[7]), .DIA0(scuba_vlo), .ADA12(WrAddress[12]), .ADA11(WrAddress[11]),
.ADA10(WrAddress[10]), .ADA9(WrAddress[9]), .ADA8(WrAddress[8]),
.ADA7(WrAddress[7]), .ADA6(WrAddress[6]), .ADA5(WrAddress[5]), .ADA4(WrAddress[4]),
.ADA3(WrAddress[3]), .ADA2(WrAddress[2]), .ADA1(WrAddress[1]), .ADA0(WrAddress[0]),
.CEA(WrClockEn), .OCEA(WrClockEn), .CLKA(WrClock), .WEA(WE), .CSA2(scuba_vlo),
.CSA1(scuba_vlo), .CSA0(WrAddress[13]), .RSTA(Reset), .DIB8(scuba_vlo),
.DIB7(scuba_vlo), .DIB6(scuba_vlo), .DIB5(scuba_vlo), .DIB4(scuba_vlo),
.DIB3(scuba_vlo), .DIB2(scuba_vlo), .DIB1(scuba_vlo), .DIB0(scuba_vlo),
.ADB12(RdAddress[12]), .ADB11(RdAddress[11]), .ADB10(RdAddress[10]),
.ADB9(RdAddress[9]), .ADB8(RdAddress[8]), .ADB7(RdAddress[7]), .ADB6(RdAddress[6]),
.ADB5(RdAddress[5]), .ADB4(RdAddress[4]), .ADB3(RdAddress[3]), .ADB2(RdAddress[2]),
.ADB1(RdAddress[1]), .ADB0(RdAddress[0]), .CEB(RdClockEn), .OCEB(RdClockEn),
.CLKB(RdClock), .WEB(scuba_vlo), .CSB2(scuba_vlo), .CSB1(scuba_vlo),
.CSB0(RdAddress[13]), .RSTB(Reset), .DOA8(), .DOA7(), .DOA6(), .DOA5(),
.DOA4(), .DOA3(), .DOA2(), .DOA1(), .DOA0(), .DOB8(), .DOB7(), .DOB6(),
.DOB5(), .DOB4(), .DOB3(), .DOB2(), .DOB1(), .DOB0(mdout1_0_7))
/* synthesis MEM_LPC_FILE="ram.lpc" */
/* synthesis MEM_INIT_FILE="INIT_ALL_0s" */;
defparam ram_1_0_7.INIT_DATA = "STATIC" ;
defparam ram_1_0_7.ASYNC_RESET_RELEASE = "SYNC" ;
defparam ram_1_0_7.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_0_7.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_0_7.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_0_7.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_0_7.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_0_7.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_0_7.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_0_7.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_0_7.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_0_7.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_0_7.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_0_7.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_0_7.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_0_7.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_0_7.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_0_7.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_0_7.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_0_7.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_0_7.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_0_7.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_0_7.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_0_7.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_0_7.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_0_7.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_0_7.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_0_7.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_0_7.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_0_7.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_0_7.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_0_7.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_0_7.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_0_7.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_0_7.CSDECODE_B = "0b001" ;
defparam ram_1_0_7.CSDECODE_A = "0b001" ;
defparam ram_1_0_7.WRITEMODE_B = "NORMAL" ;
defparam ram_1_0_7.WRITEMODE_A = "NORMAL" ;
defparam ram_1_0_7.GSR = "ENABLED" ;
defparam ram_1_0_7.RESETMODE = "SYNC" ;
defparam ram_1_0_7.REGMODE_B = "OUTREG" ;
defparam ram_1_0_7.REGMODE_A = "OUTREG" ;
defparam ram_1_0_7.DATA_WIDTH_B = 1 ;
defparam ram_1_0_7.DATA_WIDTH_A = 1 ;
DP8KC ram_1_0_7 (.DIA8(scuba_vlo), .DIA7(scuba_vlo), .DIA6(scuba_vlo),
.DIA5(scuba_vlo), .DIA4(scuba_vlo), .DIA3(scuba_vlo), .DIA2(scuba_vlo),
.DIA1(Data[0]), .DIA0(scuba_vlo), .ADA12(WrAddress[12]), .ADA11(WrAddress[11]),
.ADA10(WrAddress[10]), .ADA9(WrAddress[9]), .ADA8(WrAddress[8]),
.ADA7(WrAddress[7]), .ADA6(WrAddress[6]), .ADA5(WrAddress[5]), .ADA4(WrAddress[4]),
.ADA3(WrAddress[3]), .ADA2(WrAddress[2]), .ADA1(WrAddress[1]), .ADA0(WrAddress[0]),
.CEA(WrClockEn), .OCEA(WrClockEn), .CLKA(WrClock), .WEA(WE), .CSA2(scuba_vlo),
.CSA1(scuba_vlo), .CSA0(WrAddress[13]), .RSTA(Reset), .DIB8(scuba_vlo),
.DIB7(scuba_vlo), .DIB6(scuba_vlo), .DIB5(scuba_vlo), .DIB4(scuba_vlo),
.DIB3(scuba_vlo), .DIB2(scuba_vlo), .DIB1(scuba_vlo), .DIB0(scuba_vlo),
.ADB12(RdAddress[12]), .ADB11(RdAddress[11]), .ADB10(RdAddress[10]),
.ADB9(RdAddress[9]), .ADB8(RdAddress[8]), .ADB7(RdAddress[7]), .ADB6(RdAddress[6]),
.ADB5(RdAddress[5]), .ADB4(RdAddress[4]), .ADB3(RdAddress[3]), .ADB2(RdAddress[2]),
.ADB1(RdAddress[1]), .ADB0(RdAddress[0]), .CEB(RdClockEn), .OCEB(RdClockEn),
.CLKB(RdClock), .WEB(scuba_vlo), .CSB2(scuba_vlo), .CSB1(scuba_vlo),
.CSB0(RdAddress[13]), .RSTB(Reset), .DOA8(), .DOA7(), .DOA6(), .DOA5(),
.DOA4(), .DOA3(), .DOA2(), .DOA1(), .DOA0(), .DOB8(), .DOB7(), .DOB6(),
.DOB5(), .DOB4(), .DOB3(), .DOB2(), .DOB1(), .DOB0(mdout1_1_0))
/* synthesis MEM_LPC_FILE="ram.lpc" */
/* synthesis MEM_INIT_FILE="INIT_ALL_0s" */;
defparam ram_1_1_6.INIT_DATA = "STATIC" ;
defparam ram_1_1_6.ASYNC_RESET_RELEASE = "SYNC" ;
defparam ram_1_1_6.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_1_6.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_1_6.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_1_6.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_1_6.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_1_6.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_1_6.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_1_6.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_1_6.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_1_6.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_1_6.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_1_6.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_1_6.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_1_6.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_1_6.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_1_6.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_1_6.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_1_6.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_1_6.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_1_6.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_1_6.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_1_6.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_1_6.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_1_6.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_1_6.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_1_6.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_1_6.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_1_6.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_1_6.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_1_6.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_1_6.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_1_6.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_1_6.CSDECODE_B = "0b001" ;
defparam ram_1_1_6.CSDECODE_A = "0b001" ;
defparam ram_1_1_6.WRITEMODE_B = "NORMAL" ;
defparam ram_1_1_6.WRITEMODE_A = "NORMAL" ;
defparam ram_1_1_6.GSR = "ENABLED" ;
defparam ram_1_1_6.RESETMODE = "SYNC" ;
defparam ram_1_1_6.REGMODE_B = "OUTREG" ;
defparam ram_1_1_6.REGMODE_A = "OUTREG" ;
defparam ram_1_1_6.DATA_WIDTH_B = 1 ;
defparam ram_1_1_6.DATA_WIDTH_A = 1 ;
DP8KC ram_1_1_6 (.DIA8(scuba_vlo), .DIA7(scuba_vlo), .DIA6(scuba_vlo),
.DIA5(scuba_vlo), .DIA4(scuba_vlo), .DIA3(scuba_vlo), .DIA2(scuba_vlo),
.DIA1(Data[1]), .DIA0(scuba_vlo), .ADA12(WrAddress[12]), .ADA11(WrAddress[11]),
.ADA10(WrAddress[10]), .ADA9(WrAddress[9]), .ADA8(WrAddress[8]),
.ADA7(WrAddress[7]), .ADA6(WrAddress[6]), .ADA5(WrAddress[5]), .ADA4(WrAddress[4]),
.ADA3(WrAddress[3]), .ADA2(WrAddress[2]), .ADA1(WrAddress[1]), .ADA0(WrAddress[0]),
.CEA(WrClockEn), .OCEA(WrClockEn), .CLKA(WrClock), .WEA(WE), .CSA2(scuba_vlo),
.CSA1(scuba_vlo), .CSA0(WrAddress[13]), .RSTA(Reset), .DIB8(scuba_vlo),
.DIB7(scuba_vlo), .DIB6(scuba_vlo), .DIB5(scuba_vlo), .DIB4(scuba_vlo),
.DIB3(scuba_vlo), .DIB2(scuba_vlo), .DIB1(scuba_vlo), .DIB0(scuba_vlo),
.ADB12(RdAddress[12]), .ADB11(RdAddress[11]), .ADB10(RdAddress[10]),
.ADB9(RdAddress[9]), .ADB8(RdAddress[8]), .ADB7(RdAddress[7]), .ADB6(RdAddress[6]),
.ADB5(RdAddress[5]), .ADB4(RdAddress[4]), .ADB3(RdAddress[3]), .ADB2(RdAddress[2]),
.ADB1(RdAddress[1]), .ADB0(RdAddress[0]), .CEB(RdClockEn), .OCEB(RdClockEn),
.CLKB(RdClock), .WEB(scuba_vlo), .CSB2(scuba_vlo), .CSB1(scuba_vlo),
.CSB0(RdAddress[13]), .RSTB(Reset), .DOA8(), .DOA7(), .DOA6(), .DOA5(),
.DOA4(), .DOA3(), .DOA2(), .DOA1(), .DOA0(), .DOB8(), .DOB7(), .DOB6(),
.DOB5(), .DOB4(), .DOB3(), .DOB2(), .DOB1(), .DOB0(mdout1_1_1))
/* synthesis MEM_LPC_FILE="ram.lpc" */
/* synthesis MEM_INIT_FILE="INIT_ALL_0s" */;
defparam ram_1_2_5.INIT_DATA = "STATIC" ;
defparam ram_1_2_5.ASYNC_RESET_RELEASE = "SYNC" ;
defparam ram_1_2_5.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_2_5.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_2_5.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_2_5.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_2_5.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_2_5.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_2_5.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_2_5.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_2_5.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_2_5.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_2_5.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_2_5.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_2_5.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_2_5.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_2_5.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_2_5.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_2_5.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_2_5.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_2_5.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_2_5.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_2_5.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_2_5.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_2_5.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_2_5.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_2_5.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_2_5.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_2_5.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_2_5.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_2_5.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_2_5.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_2_5.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_2_5.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_2_5.CSDECODE_B = "0b001" ;
defparam ram_1_2_5.CSDECODE_A = "0b001" ;
defparam ram_1_2_5.WRITEMODE_B = "NORMAL" ;
defparam ram_1_2_5.WRITEMODE_A = "NORMAL" ;
defparam ram_1_2_5.GSR = "ENABLED" ;
defparam ram_1_2_5.RESETMODE = "SYNC" ;
defparam ram_1_2_5.REGMODE_B = "OUTREG" ;
defparam ram_1_2_5.REGMODE_A = "OUTREG" ;
defparam ram_1_2_5.DATA_WIDTH_B = 1 ;
defparam ram_1_2_5.DATA_WIDTH_A = 1 ;
DP8KC ram_1_2_5 (.DIA8(scuba_vlo), .DIA7(scuba_vlo), .DIA6(scuba_vlo),
.DIA5(scuba_vlo), .DIA4(scuba_vlo), .DIA3(scuba_vlo), .DIA2(scuba_vlo),
.DIA1(Data[2]), .DIA0(scuba_vlo), .ADA12(WrAddress[12]), .ADA11(WrAddress[11]),
.ADA10(WrAddress[10]), .ADA9(WrAddress[9]), .ADA8(WrAddress[8]),
.ADA7(WrAddress[7]), .ADA6(WrAddress[6]), .ADA5(WrAddress[5]), .ADA4(WrAddress[4]),
.ADA3(WrAddress[3]), .ADA2(WrAddress[2]), .ADA1(WrAddress[1]), .ADA0(WrAddress[0]),
.CEA(WrClockEn), .OCEA(WrClockEn), .CLKA(WrClock), .WEA(WE), .CSA2(scuba_vlo),
.CSA1(scuba_vlo), .CSA0(WrAddress[13]), .RSTA(Reset), .DIB8(scuba_vlo),
.DIB7(scuba_vlo), .DIB6(scuba_vlo), .DIB5(scuba_vlo), .DIB4(scuba_vlo),
.DIB3(scuba_vlo), .DIB2(scuba_vlo), .DIB1(scuba_vlo), .DIB0(scuba_vlo),
.ADB12(RdAddress[12]), .ADB11(RdAddress[11]), .ADB10(RdAddress[10]),
.ADB9(RdAddress[9]), .ADB8(RdAddress[8]), .ADB7(RdAddress[7]), .ADB6(RdAddress[6]),
.ADB5(RdAddress[5]), .ADB4(RdAddress[4]), .ADB3(RdAddress[3]), .ADB2(RdAddress[2]),
.ADB1(RdAddress[1]), .ADB0(RdAddress[0]), .CEB(RdClockEn), .OCEB(RdClockEn),
.CLKB(RdClock), .WEB(scuba_vlo), .CSB2(scuba_vlo), .CSB1(scuba_vlo),
.CSB0(RdAddress[13]), .RSTB(Reset), .DOA8(), .DOA7(), .DOA6(), .DOA5(),
.DOA4(), .DOA3(), .DOA2(), .DOA1(), .DOA0(), .DOB8(), .DOB7(), .DOB6(),
.DOB5(), .DOB4(), .DOB3(), .DOB2(), .DOB1(), .DOB0(mdout1_1_2))
/* synthesis MEM_LPC_FILE="ram.lpc" */
/* synthesis MEM_INIT_FILE="INIT_ALL_0s" */;
defparam ram_1_3_4.INIT_DATA = "STATIC" ;
defparam ram_1_3_4.ASYNC_RESET_RELEASE = "SYNC" ;
defparam ram_1_3_4.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_3_4.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_3_4.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_3_4.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_3_4.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_3_4.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_3_4.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_3_4.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_3_4.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_3_4.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_3_4.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_3_4.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_3_4.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_3_4.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_3_4.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_3_4.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_3_4.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_3_4.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_3_4.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_3_4.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_3_4.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_3_4.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_3_4.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_3_4.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_3_4.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_3_4.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_3_4.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_3_4.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_3_4.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_3_4.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_3_4.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_3_4.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_3_4.CSDECODE_B = "0b001" ;
defparam ram_1_3_4.CSDECODE_A = "0b001" ;
defparam ram_1_3_4.WRITEMODE_B = "NORMAL" ;
defparam ram_1_3_4.WRITEMODE_A = "NORMAL" ;
defparam ram_1_3_4.GSR = "ENABLED" ;
defparam ram_1_3_4.RESETMODE = "SYNC" ;
defparam ram_1_3_4.REGMODE_B = "OUTREG" ;
defparam ram_1_3_4.REGMODE_A = "OUTREG" ;
defparam ram_1_3_4.DATA_WIDTH_B = 1 ;
defparam ram_1_3_4.DATA_WIDTH_A = 1 ;
DP8KC ram_1_3_4 (.DIA8(scuba_vlo), .DIA7(scuba_vlo), .DIA6(scuba_vlo),
.DIA5(scuba_vlo), .DIA4(scuba_vlo), .DIA3(scuba_vlo), .DIA2(scuba_vlo),
.DIA1(Data[3]), .DIA0(scuba_vlo), .ADA12(WrAddress[12]), .ADA11(WrAddress[11]),
.ADA10(WrAddress[10]), .ADA9(WrAddress[9]), .ADA8(WrAddress[8]),
.ADA7(WrAddress[7]), .ADA6(WrAddress[6]), .ADA5(WrAddress[5]), .ADA4(WrAddress[4]),
.ADA3(WrAddress[3]), .ADA2(WrAddress[2]), .ADA1(WrAddress[1]), .ADA0(WrAddress[0]),
.CEA(WrClockEn), .OCEA(WrClockEn), .CLKA(WrClock), .WEA(WE), .CSA2(scuba_vlo),
.CSA1(scuba_vlo), .CSA0(WrAddress[13]), .RSTA(Reset), .DIB8(scuba_vlo),
.DIB7(scuba_vlo), .DIB6(scuba_vlo), .DIB5(scuba_vlo), .DIB4(scuba_vlo),
.DIB3(scuba_vlo), .DIB2(scuba_vlo), .DIB1(scuba_vlo), .DIB0(scuba_vlo),
.ADB12(RdAddress[12]), .ADB11(RdAddress[11]), .ADB10(RdAddress[10]),
.ADB9(RdAddress[9]), .ADB8(RdAddress[8]), .ADB7(RdAddress[7]), .ADB6(RdAddress[6]),
.ADB5(RdAddress[5]), .ADB4(RdAddress[4]), .ADB3(RdAddress[3]), .ADB2(RdAddress[2]),
.ADB1(RdAddress[1]), .ADB0(RdAddress[0]), .CEB(RdClockEn), .OCEB(RdClockEn),
.CLKB(RdClock), .WEB(scuba_vlo), .CSB2(scuba_vlo), .CSB1(scuba_vlo),
.CSB0(RdAddress[13]), .RSTB(Reset), .DOA8(), .DOA7(), .DOA6(), .DOA5(),
.DOA4(), .DOA3(), .DOA2(), .DOA1(), .DOA0(), .DOB8(), .DOB7(), .DOB6(),
.DOB5(), .DOB4(), .DOB3(), .DOB2(), .DOB1(), .DOB0(mdout1_1_3))
/* synthesis MEM_LPC_FILE="ram.lpc" */
/* synthesis MEM_INIT_FILE="INIT_ALL_0s" */;
defparam ram_1_4_3.INIT_DATA = "STATIC" ;
defparam ram_1_4_3.ASYNC_RESET_RELEASE = "SYNC" ;
defparam ram_1_4_3.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_4_3.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_4_3.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_4_3.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_4_3.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_4_3.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_4_3.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_4_3.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_4_3.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_4_3.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_4_3.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_4_3.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_4_3.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_4_3.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_4_3.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_4_3.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_4_3.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_4_3.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_4_3.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_4_3.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_4_3.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_4_3.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_4_3.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_4_3.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_4_3.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_4_3.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_4_3.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_4_3.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_4_3.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_4_3.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_4_3.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_4_3.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_4_3.CSDECODE_B = "0b001" ;
defparam ram_1_4_3.CSDECODE_A = "0b001" ;
defparam ram_1_4_3.WRITEMODE_B = "NORMAL" ;
defparam ram_1_4_3.WRITEMODE_A = "NORMAL" ;
defparam ram_1_4_3.GSR = "ENABLED" ;
defparam ram_1_4_3.RESETMODE = "SYNC" ;
defparam ram_1_4_3.REGMODE_B = "OUTREG" ;
defparam ram_1_4_3.REGMODE_A = "OUTREG" ;
defparam ram_1_4_3.DATA_WIDTH_B = 1 ;
defparam ram_1_4_3.DATA_WIDTH_A = 1 ;
DP8KC ram_1_4_3 (.DIA8(scuba_vlo), .DIA7(scuba_vlo), .DIA6(scuba_vlo),
.DIA5(scuba_vlo), .DIA4(scuba_vlo), .DIA3(scuba_vlo), .DIA2(scuba_vlo),
.DIA1(Data[4]), .DIA0(scuba_vlo), .ADA12(WrAddress[12]), .ADA11(WrAddress[11]),
.ADA10(WrAddress[10]), .ADA9(WrAddress[9]), .ADA8(WrAddress[8]),
.ADA7(WrAddress[7]), .ADA6(WrAddress[6]), .ADA5(WrAddress[5]), .ADA4(WrAddress[4]),
.ADA3(WrAddress[3]), .ADA2(WrAddress[2]), .ADA1(WrAddress[1]), .ADA0(WrAddress[0]),
.CEA(WrClockEn), .OCEA(WrClockEn), .CLKA(WrClock), .WEA(WE), .CSA2(scuba_vlo),
.CSA1(scuba_vlo), .CSA0(WrAddress[13]), .RSTA(Reset), .DIB8(scuba_vlo),
.DIB7(scuba_vlo), .DIB6(scuba_vlo), .DIB5(scuba_vlo), .DIB4(scuba_vlo),
.DIB3(scuba_vlo), .DIB2(scuba_vlo), .DIB1(scuba_vlo), .DIB0(scuba_vlo),
.ADB12(RdAddress[12]), .ADB11(RdAddress[11]), .ADB10(RdAddress[10]),
.ADB9(RdAddress[9]), .ADB8(RdAddress[8]), .ADB7(RdAddress[7]), .ADB6(RdAddress[6]),
.ADB5(RdAddress[5]), .ADB4(RdAddress[4]), .ADB3(RdAddress[3]), .ADB2(RdAddress[2]),
.ADB1(RdAddress[1]), .ADB0(RdAddress[0]), .CEB(RdClockEn), .OCEB(RdClockEn),
.CLKB(RdClock), .WEB(scuba_vlo), .CSB2(scuba_vlo), .CSB1(scuba_vlo),
.CSB0(RdAddress[13]), .RSTB(Reset), .DOA8(), .DOA7(), .DOA6(), .DOA5(),
.DOA4(), .DOA3(), .DOA2(), .DOA1(), .DOA0(), .DOB8(), .DOB7(), .DOB6(),
.DOB5(), .DOB4(), .DOB3(), .DOB2(), .DOB1(), .DOB0(mdout1_1_4))
/* synthesis MEM_LPC_FILE="ram.lpc" */
/* synthesis MEM_INIT_FILE="INIT_ALL_0s" */;
defparam ram_1_5_2.INIT_DATA = "STATIC" ;
defparam ram_1_5_2.ASYNC_RESET_RELEASE = "SYNC" ;
defparam ram_1_5_2.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_5_2.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_5_2.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_5_2.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_5_2.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_5_2.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_5_2.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_5_2.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_5_2.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_5_2.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_5_2.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_5_2.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_5_2.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_5_2.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_5_2.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_5_2.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_5_2.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_5_2.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_5_2.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_5_2.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_5_2.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_5_2.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_5_2.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_5_2.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_5_2.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_5_2.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_5_2.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_5_2.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_5_2.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_5_2.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_5_2.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_5_2.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_5_2.CSDECODE_B = "0b001" ;
defparam ram_1_5_2.CSDECODE_A = "0b001" ;
defparam ram_1_5_2.WRITEMODE_B = "NORMAL" ;
defparam ram_1_5_2.WRITEMODE_A = "NORMAL" ;
defparam ram_1_5_2.GSR = "ENABLED" ;
defparam ram_1_5_2.RESETMODE = "SYNC" ;
defparam ram_1_5_2.REGMODE_B = "OUTREG" ;
defparam ram_1_5_2.REGMODE_A = "OUTREG" ;
defparam ram_1_5_2.DATA_WIDTH_B = 1 ;
defparam ram_1_5_2.DATA_WIDTH_A = 1 ;
DP8KC ram_1_5_2 (.DIA8(scuba_vlo), .DIA7(scuba_vlo), .DIA6(scuba_vlo),
.DIA5(scuba_vlo), .DIA4(scuba_vlo), .DIA3(scuba_vlo), .DIA2(scuba_vlo),
.DIA1(Data[5]), .DIA0(scuba_vlo), .ADA12(WrAddress[12]), .ADA11(WrAddress[11]),
.ADA10(WrAddress[10]), .ADA9(WrAddress[9]), .ADA8(WrAddress[8]),
.ADA7(WrAddress[7]), .ADA6(WrAddress[6]), .ADA5(WrAddress[5]), .ADA4(WrAddress[4]),
.ADA3(WrAddress[3]), .ADA2(WrAddress[2]), .ADA1(WrAddress[1]), .ADA0(WrAddress[0]),
.CEA(WrClockEn), .OCEA(WrClockEn), .CLKA(WrClock), .WEA(WE), .CSA2(scuba_vlo),
.CSA1(scuba_vlo), .CSA0(WrAddress[13]), .RSTA(Reset), .DIB8(scuba_vlo),
.DIB7(scuba_vlo), .DIB6(scuba_vlo), .DIB5(scuba_vlo), .DIB4(scuba_vlo),
.DIB3(scuba_vlo), .DIB2(scuba_vlo), .DIB1(scuba_vlo), .DIB0(scuba_vlo),
.ADB12(RdAddress[12]), .ADB11(RdAddress[11]), .ADB10(RdAddress[10]),
.ADB9(RdAddress[9]), .ADB8(RdAddress[8]), .ADB7(RdAddress[7]), .ADB6(RdAddress[6]),
.ADB5(RdAddress[5]), .ADB4(RdAddress[4]), .ADB3(RdAddress[3]), .ADB2(RdAddress[2]),
.ADB1(RdAddress[1]), .ADB0(RdAddress[0]), .CEB(RdClockEn), .OCEB(RdClockEn),
.CLKB(RdClock), .WEB(scuba_vlo), .CSB2(scuba_vlo), .CSB1(scuba_vlo),
.CSB0(RdAddress[13]), .RSTB(Reset), .DOA8(), .DOA7(), .DOA6(), .DOA5(),
.DOA4(), .DOA3(), .DOA2(), .DOA1(), .DOA0(), .DOB8(), .DOB7(), .DOB6(),
.DOB5(), .DOB4(), .DOB3(), .DOB2(), .DOB1(), .DOB0(mdout1_1_5))
/* synthesis MEM_LPC_FILE="ram.lpc" */
/* synthesis MEM_INIT_FILE="INIT_ALL_0s" */;
defparam ram_1_6_1.INIT_DATA = "STATIC" ;
defparam ram_1_6_1.ASYNC_RESET_RELEASE = "SYNC" ;
defparam ram_1_6_1.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_6_1.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_6_1.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_6_1.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_6_1.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_6_1.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_6_1.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_6_1.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_6_1.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_6_1.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_6_1.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_6_1.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_6_1.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_6_1.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_6_1.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_6_1.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_6_1.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_6_1.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_6_1.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_6_1.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_6_1.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_6_1.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_6_1.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_6_1.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_6_1.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_6_1.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_6_1.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_6_1.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_6_1.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_6_1.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_6_1.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_6_1.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_6_1.CSDECODE_B = "0b001" ;
defparam ram_1_6_1.CSDECODE_A = "0b001" ;
defparam ram_1_6_1.WRITEMODE_B = "NORMAL" ;
defparam ram_1_6_1.WRITEMODE_A = "NORMAL" ;
defparam ram_1_6_1.GSR = "ENABLED" ;
defparam ram_1_6_1.RESETMODE = "SYNC" ;
defparam ram_1_6_1.REGMODE_B = "OUTREG" ;
defparam ram_1_6_1.REGMODE_A = "OUTREG" ;
defparam ram_1_6_1.DATA_WIDTH_B = 1 ;
defparam ram_1_6_1.DATA_WIDTH_A = 1 ;
DP8KC ram_1_6_1 (.DIA8(scuba_vlo), .DIA7(scuba_vlo), .DIA6(scuba_vlo),
.DIA5(scuba_vlo), .DIA4(scuba_vlo), .DIA3(scuba_vlo), .DIA2(scuba_vlo),
.DIA1(Data[6]), .DIA0(scuba_vlo), .ADA12(WrAddress[12]), .ADA11(WrAddress[11]),
.ADA10(WrAddress[10]), .ADA9(WrAddress[9]), .ADA8(WrAddress[8]),
.ADA7(WrAddress[7]), .ADA6(WrAddress[6]), .ADA5(WrAddress[5]), .ADA4(WrAddress[4]),
.ADA3(WrAddress[3]), .ADA2(WrAddress[2]), .ADA1(WrAddress[1]), .ADA0(WrAddress[0]),
.CEA(WrClockEn), .OCEA(WrClockEn), .CLKA(WrClock), .WEA(WE), .CSA2(scuba_vlo),
.CSA1(scuba_vlo), .CSA0(WrAddress[13]), .RSTA(Reset), .DIB8(scuba_vlo),
.DIB7(scuba_vlo), .DIB6(scuba_vlo), .DIB5(scuba_vlo), .DIB4(scuba_vlo),
.DIB3(scuba_vlo), .DIB2(scuba_vlo), .DIB1(scuba_vlo), .DIB0(scuba_vlo),
.ADB12(RdAddress[12]), .ADB11(RdAddress[11]), .ADB10(RdAddress[10]),
.ADB9(RdAddress[9]), .ADB8(RdAddress[8]), .ADB7(RdAddress[7]), .ADB6(RdAddress[6]),
.ADB5(RdAddress[5]), .ADB4(RdAddress[4]), .ADB3(RdAddress[3]), .ADB2(RdAddress[2]),
.ADB1(RdAddress[1]), .ADB0(RdAddress[0]), .CEB(RdClockEn), .OCEB(RdClockEn),
.CLKB(RdClock), .WEB(scuba_vlo), .CSB2(scuba_vlo), .CSB1(scuba_vlo),
.CSB0(RdAddress[13]), .RSTB(Reset), .DOA8(), .DOA7(), .DOA6(), .DOA5(),
.DOA4(), .DOA3(), .DOA2(), .DOA1(), .DOA0(), .DOB8(), .DOB7(), .DOB6(),
.DOB5(), .DOB4(), .DOB3(), .DOB2(), .DOB1(), .DOB0(mdout1_1_6))
/* synthesis MEM_LPC_FILE="ram.lpc" */
/* synthesis MEM_INIT_FILE="INIT_ALL_0s" */;
defparam ram_1_7_0.INIT_DATA = "STATIC" ;
defparam ram_1_7_0.ASYNC_RESET_RELEASE = "SYNC" ;
defparam ram_1_7_0.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_7_0.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_7_0.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_7_0.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_7_0.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_7_0.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_7_0.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_7_0.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_7_0.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_7_0.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_7_0.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_7_0.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_7_0.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_7_0.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_7_0.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_7_0.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_7_0.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_7_0.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_7_0.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_7_0.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_7_0.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_7_0.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_7_0.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_7_0.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_7_0.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_7_0.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_7_0.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_7_0.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_7_0.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_7_0.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_7_0.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_7_0.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam ram_1_7_0.CSDECODE_B = "0b001" ;
defparam ram_1_7_0.CSDECODE_A = "0b001" ;
defparam ram_1_7_0.WRITEMODE_B = "NORMAL" ;
defparam ram_1_7_0.WRITEMODE_A = "NORMAL" ;
defparam ram_1_7_0.GSR = "ENABLED" ;
defparam ram_1_7_0.RESETMODE = "SYNC" ;
defparam ram_1_7_0.REGMODE_B = "OUTREG" ;
defparam ram_1_7_0.REGMODE_A = "OUTREG" ;
defparam ram_1_7_0.DATA_WIDTH_B = 1 ;
defparam ram_1_7_0.DATA_WIDTH_A = 1 ;
DP8KC ram_1_7_0 (.DIA8(scuba_vlo), .DIA7(scuba_vlo), .DIA6(scuba_vlo),
.DIA5(scuba_vlo), .DIA4(scuba_vlo), .DIA3(scuba_vlo), .DIA2(scuba_vlo),
.DIA1(Data[7]), .DIA0(scuba_vlo), .ADA12(WrAddress[12]), .ADA11(WrAddress[11]),
.ADA10(WrAddress[10]), .ADA9(WrAddress[9]), .ADA8(WrAddress[8]),
.ADA7(WrAddress[7]), .ADA6(WrAddress[6]), .ADA5(WrAddress[5]), .ADA4(WrAddress[4]),
.ADA3(WrAddress[3]), .ADA2(WrAddress[2]), .ADA1(WrAddress[1]), .ADA0(WrAddress[0]),
.CEA(WrClockEn), .OCEA(WrClockEn), .CLKA(WrClock), .WEA(WE), .CSA2(scuba_vlo),
.CSA1(scuba_vlo), .CSA0(WrAddress[13]), .RSTA(Reset), .DIB8(scuba_vlo),
.DIB7(scuba_vlo), .DIB6(scuba_vlo), .DIB5(scuba_vlo), .DIB4(scuba_vlo),
.DIB3(scuba_vlo), .DIB2(scuba_vlo), .DIB1(scuba_vlo), .DIB0(scuba_vlo),
.ADB12(RdAddress[12]), .ADB11(RdAddress[11]), .ADB10(RdAddress[10]),
.ADB9(RdAddress[9]), .ADB8(RdAddress[8]), .ADB7(RdAddress[7]), .ADB6(RdAddress[6]),
.ADB5(RdAddress[5]), .ADB4(RdAddress[4]), .ADB3(RdAddress[3]), .ADB2(RdAddress[2]),
.ADB1(RdAddress[1]), .ADB0(RdAddress[0]), .CEB(RdClockEn), .OCEB(RdClockEn),
.CLKB(RdClock), .WEB(scuba_vlo), .CSB2(scuba_vlo), .CSB1(scuba_vlo),
.CSB0(RdAddress[13]), .RSTB(Reset), .DOA8(), .DOA7(), .DOA6(), .DOA5(),
.DOA4(), .DOA3(), .DOA2(), .DOA1(), .DOA0(), .DOB8(), .DOB7(), .DOB6(),
.DOB5(), .DOB4(), .DOB3(), .DOB2(), .DOB1(), .DOB0(mdout1_1_7))
/* synthesis MEM_LPC_FILE="ram.lpc" */
/* synthesis MEM_INIT_FILE="INIT_ALL_0s" */;
FD1P3DX FF_1 (.D(RdAddress[13]), .SP(RdClockEn), .CK(RdClock), .CD(scuba_vlo),
.Q(raddr13_ff))
/* synthesis GSR="ENABLED" */;
VLO scuba_vlo_inst (.Z(scuba_vlo));
FD1P3DX FF_0 (.D(raddr13_ff), .SP(RdClockEn), .CK(RdClock), .CD(scuba_vlo),
.Q(raddr13_ff2))
/* synthesis GSR="ENABLED" */;
MUX21 mux_7 (.D0(mdout1_0_0), .D1(mdout1_1_0), .SD(raddr13_ff2), .Z(Q[0]));
MUX21 mux_6 (.D0(mdout1_0_1), .D1(mdout1_1_1), .SD(raddr13_ff2), .Z(Q[1]));
MUX21 mux_5 (.D0(mdout1_0_2), .D1(mdout1_1_2), .SD(raddr13_ff2), .Z(Q[2]));
MUX21 mux_4 (.D0(mdout1_0_3), .D1(mdout1_1_3), .SD(raddr13_ff2), .Z(Q[3]));
MUX21 mux_3 (.D0(mdout1_0_4), .D1(mdout1_1_4), .SD(raddr13_ff2), .Z(Q[4]));
MUX21 mux_2 (.D0(mdout1_0_5), .D1(mdout1_1_5), .SD(raddr13_ff2), .Z(Q[5]));
MUX21 mux_1 (.D0(mdout1_0_6), .D1(mdout1_1_6), .SD(raddr13_ff2), .Z(Q[6]));
MUX21 mux_0 (.D0(mdout1_0_7), .D1(mdout1_1_7), .SD(raddr13_ff2), .Z(Q[7]));
// exemplar begin
// exemplar attribute ram_0_0_15 MEM_LPC_FILE ram.lpc
// exemplar attribute ram_0_0_15 MEM_INIT_FILE INIT_ALL_0s
// exemplar attribute ram_0_1_14 MEM_LPC_FILE ram.lpc
// exemplar attribute ram_0_1_14 MEM_INIT_FILE INIT_ALL_0s
// exemplar attribute ram_0_2_13 MEM_LPC_FILE ram.lpc
// exemplar attribute ram_0_2_13 MEM_INIT_FILE INIT_ALL_0s
// exemplar attribute ram_0_3_12 MEM_LPC_FILE ram.lpc
// exemplar attribute ram_0_3_12 MEM_INIT_FILE INIT_ALL_0s
// exemplar attribute ram_0_4_11 MEM_LPC_FILE ram.lpc
// exemplar attribute ram_0_4_11 MEM_INIT_FILE INIT_ALL_0s
// exemplar attribute ram_0_5_10 MEM_LPC_FILE ram.lpc
// exemplar attribute ram_0_5_10 MEM_INIT_FILE INIT_ALL_0s
// exemplar attribute ram_0_6_9 MEM_LPC_FILE ram.lpc
// exemplar attribute ram_0_6_9 MEM_INIT_FILE INIT_ALL_0s
// exemplar attribute ram_0_7_8 MEM_LPC_FILE ram.lpc
// exemplar attribute ram_0_7_8 MEM_INIT_FILE INIT_ALL_0s
// exemplar attribute ram_1_0_7 MEM_LPC_FILE ram.lpc
// exemplar attribute ram_1_0_7 MEM_INIT_FILE INIT_ALL_0s
// exemplar attribute ram_1_1_6 MEM_LPC_FILE ram.lpc
// exemplar attribute ram_1_1_6 MEM_INIT_FILE INIT_ALL_0s
// exemplar attribute ram_1_2_5 MEM_LPC_FILE ram.lpc
// exemplar attribute ram_1_2_5 MEM_INIT_FILE INIT_ALL_0s
// exemplar attribute ram_1_3_4 MEM_LPC_FILE ram.lpc
// exemplar attribute ram_1_3_4 MEM_INIT_FILE INIT_ALL_0s
// exemplar attribute ram_1_4_3 MEM_LPC_FILE ram.lpc
// exemplar attribute ram_1_4_3 MEM_INIT_FILE INIT_ALL_0s
// exemplar attribute ram_1_5_2 MEM_LPC_FILE ram.lpc
// exemplar attribute ram_1_5_2 MEM_INIT_FILE INIT_ALL_0s
// exemplar attribute ram_1_6_1 MEM_LPC_FILE ram.lpc
// exemplar attribute ram_1_6_1 MEM_INIT_FILE INIT_ALL_0s
// exemplar attribute ram_1_7_0 MEM_LPC_FILE ram.lpc
// exemplar attribute ram_1_7_0 MEM_INIT_FILE INIT_ALL_0s
// exemplar attribute FF_1 GSR ENABLED
// exemplar attribute FF_0 GSR ENABLED
// exemplar end
endmodule
|
/*
* These source files contain a hardware description of a network
* automatically generated by CONNECT (CONfigurable NEtwork Creation Tool).
*
* This product includes a hardware design developed by Carnegie Mellon
* University.
*
* Copyright (c) 2012 by Michael K. Papamichael, Carnegie Mellon University
*
* For more information, see the CONNECT project website at:
* http://www.ece.cmu.edu/~mpapamic/connect
*
* This design is provided for internal, non-commercial research use only,
* cannot be used for, or in support of, goods or services, and is not for
* redistribution, with or without modifications.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*
*/
//
// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17)
//
// On Mon Oct 26 08:39:05 EDT 2015
//
// Method conflict info:
// Method: output_arbs_0_select
// Conflict-free: output_arbs_0_select,
// output_arbs_1_select,
// output_arbs_1_next,
// output_arbs_2_select,
// output_arbs_2_next,
// output_arbs_3_select,
// output_arbs_3_next,
// output_arbs_4_select,
// output_arbs_4_next
// Sequenced before: output_arbs_0_next
//
// Method: output_arbs_0_next
// Conflict-free: output_arbs_1_select,
// output_arbs_1_next,
// output_arbs_2_select,
// output_arbs_2_next,
// output_arbs_3_select,
// output_arbs_3_next,
// output_arbs_4_select,
// output_arbs_4_next
// Sequenced after: output_arbs_0_select
// Conflicts: output_arbs_0_next
//
// Method: output_arbs_1_select
// Conflict-free: output_arbs_0_select,
// output_arbs_0_next,
// output_arbs_1_select,
// output_arbs_2_select,
// output_arbs_2_next,
// output_arbs_3_select,
// output_arbs_3_next,
// output_arbs_4_select,
// output_arbs_4_next
// Sequenced before: output_arbs_1_next
//
// Method: output_arbs_1_next
// Conflict-free: output_arbs_0_select,
// output_arbs_0_next,
// output_arbs_2_select,
// output_arbs_2_next,
// output_arbs_3_select,
// output_arbs_3_next,
// output_arbs_4_select,
// output_arbs_4_next
// Sequenced after: output_arbs_1_select
// Conflicts: output_arbs_1_next
//
// Method: output_arbs_2_select
// Conflict-free: output_arbs_0_select,
// output_arbs_0_next,
// output_arbs_1_select,
// output_arbs_1_next,
// output_arbs_2_select,
// output_arbs_3_select,
// output_arbs_3_next,
// output_arbs_4_select,
// output_arbs_4_next
// Sequenced before: output_arbs_2_next
//
// Method: output_arbs_2_next
// Conflict-free: output_arbs_0_select,
// output_arbs_0_next,
// output_arbs_1_select,
// output_arbs_1_next,
// output_arbs_3_select,
// output_arbs_3_next,
// output_arbs_4_select,
// output_arbs_4_next
// Sequenced after: output_arbs_2_select
// Conflicts: output_arbs_2_next
//
// Method: output_arbs_3_select
// Conflict-free: output_arbs_0_select,
// output_arbs_0_next,
// output_arbs_1_select,
// output_arbs_1_next,
// output_arbs_2_select,
// output_arbs_2_next,
// output_arbs_3_select,
// output_arbs_4_select,
// output_arbs_4_next
// Sequenced before: output_arbs_3_next
//
// Method: output_arbs_3_next
// Conflict-free: output_arbs_0_select,
// output_arbs_0_next,
// output_arbs_1_select,
// output_arbs_1_next,
// output_arbs_2_select,
// output_arbs_2_next,
// output_arbs_4_select,
// output_arbs_4_next
// Sequenced after: output_arbs_3_select
// Conflicts: output_arbs_3_next
//
// Method: output_arbs_4_select
// Conflict-free: output_arbs_0_select,
// output_arbs_0_next,
// output_arbs_1_select,
// output_arbs_1_next,
// output_arbs_2_select,
// output_arbs_2_next,
// output_arbs_3_select,
// output_arbs_3_next,
// output_arbs_4_select
// Sequenced before: output_arbs_4_next
//
// Method: output_arbs_4_next
// Conflict-free: output_arbs_0_select,
// output_arbs_0_next,
// output_arbs_1_select,
// output_arbs_1_next,
// output_arbs_2_select,
// output_arbs_2_next,
// output_arbs_3_select,
// output_arbs_3_next
// Sequenced after: output_arbs_4_select
// Conflicts: output_arbs_4_next
//
//
// Ports:
// Name I/O size props
// output_arbs_0_select O 5
// output_arbs_1_select O 5
// output_arbs_2_select O 5
// output_arbs_3_select O 5
// output_arbs_4_select O 5
// CLK I 1 clock
// RST_N I 1 reset
// output_arbs_0_select_requests I 5
// output_arbs_1_select_requests I 5
// output_arbs_2_select_requests I 5
// output_arbs_3_select_requests I 5
// output_arbs_4_select_requests I 5
// EN_output_arbs_0_next I 1
// EN_output_arbs_1_next I 1
// EN_output_arbs_2_next I 1
// EN_output_arbs_3_next I 1
// EN_output_arbs_4_next I 1
//
// Combinational paths from inputs to outputs:
// output_arbs_0_select_requests -> output_arbs_0_select
// output_arbs_1_select_requests -> output_arbs_1_select
// output_arbs_2_select_requests -> output_arbs_2_select
// output_arbs_3_select_requests -> output_arbs_3_select
// output_arbs_4_select_requests -> output_arbs_4_select
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module mkRouterOutputArbitersRoundRobin(CLK,
RST_N,
output_arbs_0_select_requests,
output_arbs_0_select,
EN_output_arbs_0_next,
output_arbs_1_select_requests,
output_arbs_1_select,
EN_output_arbs_1_next,
output_arbs_2_select_requests,
output_arbs_2_select,
EN_output_arbs_2_next,
output_arbs_3_select_requests,
output_arbs_3_select,
EN_output_arbs_3_next,
output_arbs_4_select_requests,
output_arbs_4_select,
EN_output_arbs_4_next);
input CLK;
input RST_N;
// value method output_arbs_0_select
input [4 : 0] output_arbs_0_select_requests;
output [4 : 0] output_arbs_0_select;
// action method output_arbs_0_next
input EN_output_arbs_0_next;
// value method output_arbs_1_select
input [4 : 0] output_arbs_1_select_requests;
output [4 : 0] output_arbs_1_select;
// action method output_arbs_1_next
input EN_output_arbs_1_next;
// value method output_arbs_2_select
input [4 : 0] output_arbs_2_select_requests;
output [4 : 0] output_arbs_2_select;
// action method output_arbs_2_next
input EN_output_arbs_2_next;
// value method output_arbs_3_select
input [4 : 0] output_arbs_3_select_requests;
output [4 : 0] output_arbs_3_select;
// action method output_arbs_3_next
input EN_output_arbs_3_next;
// value method output_arbs_4_select
input [4 : 0] output_arbs_4_select_requests;
output [4 : 0] output_arbs_4_select;
// action method output_arbs_4_next
input EN_output_arbs_4_next;
// signals for module outputs
wire [4 : 0] output_arbs_0_select,
output_arbs_1_select,
output_arbs_2_select,
output_arbs_3_select,
output_arbs_4_select;
// register oas_0_token
reg [4 : 0] oas_0_token;
wire [4 : 0] oas_0_token$D_IN;
wire oas_0_token$EN;
// register oas_1_token
reg [4 : 0] oas_1_token;
wire [4 : 0] oas_1_token$D_IN;
wire oas_1_token$EN;
// register oas_2_token
reg [4 : 0] oas_2_token;
wire [4 : 0] oas_2_token$D_IN;
wire oas_2_token$EN;
// register oas_3_token
reg [4 : 0] oas_3_token;
wire [4 : 0] oas_3_token$D_IN;
wire oas_3_token$EN;
// register oas_4_token
reg [4 : 0] oas_4_token;
wire [4 : 0] oas_4_token$D_IN;
wire oas_4_token$EN;
// remaining internal signals
wire [1 : 0] ab__h12572,
ab__h12587,
ab__h12602,
ab__h12617,
ab__h12632,
ab__h14013,
ab__h14460,
ab__h14853,
ab__h15197,
ab__h15492,
ab__h19612,
ab__h19627,
ab__h19642,
ab__h19657,
ab__h19672,
ab__h21053,
ab__h21500,
ab__h21893,
ab__h22237,
ab__h22532,
ab__h26652,
ab__h26667,
ab__h26682,
ab__h26697,
ab__h26712,
ab__h28093,
ab__h28540,
ab__h28933,
ab__h29277,
ab__h29572,
ab__h33692,
ab__h33707,
ab__h33722,
ab__h33737,
ab__h33752,
ab__h35133,
ab__h35580,
ab__h35973,
ab__h36317,
ab__h36612,
ab__h5532,
ab__h5547,
ab__h5562,
ab__h5577,
ab__h5592,
ab__h6973,
ab__h7420,
ab__h7813,
ab__h8157,
ab__h8452;
wire NOT_gen_grant_carry_00_BIT_1_01_14_AND_NOT_gen_ETC___d328,
NOT_gen_grant_carry_00_BIT_1_01_14_AND_NOT_gen_ETC___d348,
NOT_gen_grant_carry_0_BIT_1_1_04_AND_NOT_gen_g_ETC___d118,
NOT_gen_grant_carry_0_BIT_1_1_04_AND_NOT_gen_g_ETC___d138,
NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d48,
NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d68,
NOT_gen_grant_carry_22_BIT_1_54_60_AND_NOT_gen_ETC___d276,
NOT_gen_grant_carry_26_BIT_1_47_51_AND_NOT_gen_ETC___d267,
NOT_gen_grant_carry_2_BIT_1_14_20_AND_NOT_gen__ETC___d136,
NOT_gen_grant_carry_2_BIT_1_4_0_AND_NOT_gen_gr_ETC___d66,
NOT_gen_grant_carry_30_BIT_1_31_44_AND_NOT_gen_ETC___d258,
NOT_gen_grant_carry_30_BIT_1_31_44_AND_NOT_gen_ETC___d278,
NOT_gen_grant_carry_52_BIT_1_84_90_AND_NOT_gen_ETC___d206,
NOT_gen_grant_carry_56_BIT_1_77_81_AND_NOT_gen_ETC___d197,
NOT_gen_grant_carry_60_BIT_1_61_74_AND_NOT_gen_ETC___d188,
NOT_gen_grant_carry_60_BIT_1_61_74_AND_NOT_gen_ETC___d208,
NOT_gen_grant_carry_6_BIT_1_07_11_AND_NOT_gen__ETC___d127,
NOT_gen_grant_carry_6_BIT_1_7_1_AND_NOT_gen_gr_ETC___d57,
NOT_gen_grant_carry_92_BIT_1_24_30_AND_NOT_gen_ETC___d346,
NOT_gen_grant_carry_96_BIT_1_17_21_AND_NOT_gen_ETC___d337,
ab_BIT_0___h13184,
ab_BIT_0___h13291,
ab_BIT_0___h13398,
ab_BIT_0___h13505,
ab_BIT_0___h14084,
ab_BIT_0___h14220,
ab_BIT_0___h14613,
ab_BIT_0___h14957,
ab_BIT_0___h15252,
ab_BIT_0___h20224,
ab_BIT_0___h20331,
ab_BIT_0___h20438,
ab_BIT_0___h20545,
ab_BIT_0___h21124,
ab_BIT_0___h21260,
ab_BIT_0___h21653,
ab_BIT_0___h21997,
ab_BIT_0___h22292,
ab_BIT_0___h27264,
ab_BIT_0___h27371,
ab_BIT_0___h27478,
ab_BIT_0___h27585,
ab_BIT_0___h28164,
ab_BIT_0___h28300,
ab_BIT_0___h28693,
ab_BIT_0___h29037,
ab_BIT_0___h29332,
ab_BIT_0___h34304,
ab_BIT_0___h34411,
ab_BIT_0___h34518,
ab_BIT_0___h34625,
ab_BIT_0___h35204,
ab_BIT_0___h35340,
ab_BIT_0___h35733,
ab_BIT_0___h36077,
ab_BIT_0___h36372,
ab_BIT_0___h6144,
ab_BIT_0___h6251,
ab_BIT_0___h6358,
ab_BIT_0___h6465,
ab_BIT_0___h7044,
ab_BIT_0___h7180,
ab_BIT_0___h7573,
ab_BIT_0___h7917,
ab_BIT_0___h8212,
oas_0_token_BIT_0___h6142,
oas_0_token_BIT_1___h6249,
oas_0_token_BIT_2___h6356,
oas_0_token_BIT_3___h6463,
oas_0_token_BIT_4___h6570,
oas_1_token_BIT_0___h13182,
oas_1_token_BIT_1___h13289,
oas_1_token_BIT_2___h13396,
oas_1_token_BIT_3___h13503,
oas_1_token_BIT_4___h13610,
oas_2_token_BIT_0___h20222,
oas_2_token_BIT_1___h20329,
oas_2_token_BIT_2___h20436,
oas_2_token_BIT_3___h20543,
oas_2_token_BIT_4___h20650,
oas_3_token_BIT_0___h27262,
oas_3_token_BIT_1___h27369,
oas_3_token_BIT_2___h27476,
oas_3_token_BIT_3___h27583,
oas_3_token_BIT_4___h27690,
oas_4_token_BIT_0___h34302,
oas_4_token_BIT_1___h34409,
oas_4_token_BIT_2___h34516,
oas_4_token_BIT_3___h34623,
oas_4_token_BIT_4___h34730;
// value method output_arbs_0_select
assign output_arbs_0_select =
{ ab__h5532[1] || ab__h6973[1],
!ab__h5532[1] && !ab__h6973[1] &&
(ab__h5547[1] || ab__h7420[1]),
NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d48,
!ab__h5532[1] && !ab__h6973[1] &&
NOT_gen_grant_carry_6_BIT_1_7_1_AND_NOT_gen_gr_ETC___d57,
NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d68 } ;
// value method output_arbs_1_select
assign output_arbs_1_select =
{ ab__h12572[1] || ab__h14013[1],
!ab__h12572[1] && !ab__h14013[1] &&
(ab__h12587[1] || ab__h14460[1]),
NOT_gen_grant_carry_0_BIT_1_1_04_AND_NOT_gen_g_ETC___d118,
!ab__h12572[1] && !ab__h14013[1] &&
NOT_gen_grant_carry_6_BIT_1_07_11_AND_NOT_gen__ETC___d127,
NOT_gen_grant_carry_0_BIT_1_1_04_AND_NOT_gen_g_ETC___d138 } ;
// value method output_arbs_2_select
assign output_arbs_2_select =
{ ab__h19612[1] || ab__h21053[1],
!ab__h19612[1] && !ab__h21053[1] &&
(ab__h19627[1] || ab__h21500[1]),
NOT_gen_grant_carry_60_BIT_1_61_74_AND_NOT_gen_ETC___d188,
!ab__h19612[1] && !ab__h21053[1] &&
NOT_gen_grant_carry_56_BIT_1_77_81_AND_NOT_gen_ETC___d197,
NOT_gen_grant_carry_60_BIT_1_61_74_AND_NOT_gen_ETC___d208 } ;
// value method output_arbs_3_select
assign output_arbs_3_select =
{ ab__h26652[1] || ab__h28093[1],
!ab__h26652[1] && !ab__h28093[1] &&
(ab__h26667[1] || ab__h28540[1]),
NOT_gen_grant_carry_30_BIT_1_31_44_AND_NOT_gen_ETC___d258,
!ab__h26652[1] && !ab__h28093[1] &&
NOT_gen_grant_carry_26_BIT_1_47_51_AND_NOT_gen_ETC___d267,
NOT_gen_grant_carry_30_BIT_1_31_44_AND_NOT_gen_ETC___d278 } ;
// value method output_arbs_4_select
assign output_arbs_4_select =
{ ab__h33692[1] || ab__h35133[1],
!ab__h33692[1] && !ab__h35133[1] &&
(ab__h33707[1] || ab__h35580[1]),
NOT_gen_grant_carry_00_BIT_1_01_14_AND_NOT_gen_ETC___d328,
!ab__h33692[1] && !ab__h35133[1] &&
NOT_gen_grant_carry_96_BIT_1_17_21_AND_NOT_gen_ETC___d337,
NOT_gen_grant_carry_00_BIT_1_01_14_AND_NOT_gen_ETC___d348 } ;
// register oas_0_token
assign oas_0_token$D_IN = { oas_0_token[0], oas_0_token[4:1] } ;
assign oas_0_token$EN = EN_output_arbs_0_next ;
// register oas_1_token
assign oas_1_token$D_IN = { oas_1_token[0], oas_1_token[4:1] } ;
assign oas_1_token$EN = EN_output_arbs_1_next ;
// register oas_2_token
assign oas_2_token$D_IN = { oas_2_token[0], oas_2_token[4:1] } ;
assign oas_2_token$EN = EN_output_arbs_2_next ;
// register oas_3_token
assign oas_3_token$D_IN = { oas_3_token[0], oas_3_token[4:1] } ;
assign oas_3_token$EN = EN_output_arbs_3_next ;
// register oas_4_token
assign oas_4_token$D_IN = { oas_4_token[0], oas_4_token[4:1] } ;
assign oas_4_token$EN = EN_output_arbs_4_next ;
// remaining internal signals
module_gen_grant_carry instance_gen_grant_carry_45(.gen_grant_carry_c(1'd0),
.gen_grant_carry_r(output_arbs_0_select_requests[0]),
.gen_grant_carry_p(oas_0_token_BIT_0___h6142),
.gen_grant_carry(ab__h5592));
module_gen_grant_carry instance_gen_grant_carry_1(.gen_grant_carry_c(ab_BIT_0___h6144),
.gen_grant_carry_r(output_arbs_0_select_requests[1]),
.gen_grant_carry_p(oas_0_token_BIT_1___h6249),
.gen_grant_carry(ab__h5577));
module_gen_grant_carry instance_gen_grant_carry_0(.gen_grant_carry_c(ab_BIT_0___h6251),
.gen_grant_carry_r(output_arbs_0_select_requests[2]),
.gen_grant_carry_p(oas_0_token_BIT_2___h6356),
.gen_grant_carry(ab__h5562));
module_gen_grant_carry instance_gen_grant_carry_2(.gen_grant_carry_c(ab_BIT_0___h6358),
.gen_grant_carry_r(output_arbs_0_select_requests[3]),
.gen_grant_carry_p(oas_0_token_BIT_3___h6463),
.gen_grant_carry(ab__h5547));
module_gen_grant_carry instance_gen_grant_carry_3(.gen_grant_carry_c(ab_BIT_0___h6465),
.gen_grant_carry_r(output_arbs_0_select_requests[4]),
.gen_grant_carry_p(oas_0_token_BIT_4___h6570),
.gen_grant_carry(ab__h5532));
module_gen_grant_carry instance_gen_grant_carry_4(.gen_grant_carry_c(ab_BIT_0___h7044),
.gen_grant_carry_r(output_arbs_0_select_requests[0]),
.gen_grant_carry_p(oas_0_token_BIT_0___h6142),
.gen_grant_carry(ab__h8452));
module_gen_grant_carry instance_gen_grant_carry_5(.gen_grant_carry_c(ab_BIT_0___h8212),
.gen_grant_carry_r(output_arbs_0_select_requests[1]),
.gen_grant_carry_p(oas_0_token_BIT_1___h6249),
.gen_grant_carry(ab__h8157));
module_gen_grant_carry instance_gen_grant_carry_6(.gen_grant_carry_c(ab_BIT_0___h7917),
.gen_grant_carry_r(output_arbs_0_select_requests[2]),
.gen_grant_carry_p(oas_0_token_BIT_2___h6356),
.gen_grant_carry(ab__h7813));
module_gen_grant_carry instance_gen_grant_carry_7(.gen_grant_carry_c(ab_BIT_0___h7573),
.gen_grant_carry_r(output_arbs_0_select_requests[3]),
.gen_grant_carry_p(oas_0_token_BIT_3___h6463),
.gen_grant_carry(ab__h7420));
module_gen_grant_carry instance_gen_grant_carry_8(.gen_grant_carry_c(ab_BIT_0___h7180),
.gen_grant_carry_r(output_arbs_0_select_requests[4]),
.gen_grant_carry_p(oas_0_token_BIT_4___h6570),
.gen_grant_carry(ab__h6973));
module_gen_grant_carry instance_gen_grant_carry_46(.gen_grant_carry_c(1'd0),
.gen_grant_carry_r(output_arbs_1_select_requests[0]),
.gen_grant_carry_p(oas_1_token_BIT_0___h13182),
.gen_grant_carry(ab__h12632));
module_gen_grant_carry instance_gen_grant_carry_9(.gen_grant_carry_c(ab_BIT_0___h13184),
.gen_grant_carry_r(output_arbs_1_select_requests[1]),
.gen_grant_carry_p(oas_1_token_BIT_1___h13289),
.gen_grant_carry(ab__h12617));
module_gen_grant_carry instance_gen_grant_carry_10(.gen_grant_carry_c(ab_BIT_0___h13291),
.gen_grant_carry_r(output_arbs_1_select_requests[2]),
.gen_grant_carry_p(oas_1_token_BIT_2___h13396),
.gen_grant_carry(ab__h12602));
module_gen_grant_carry instance_gen_grant_carry_11(.gen_grant_carry_c(ab_BIT_0___h13398),
.gen_grant_carry_r(output_arbs_1_select_requests[3]),
.gen_grant_carry_p(oas_1_token_BIT_3___h13503),
.gen_grant_carry(ab__h12587));
module_gen_grant_carry instance_gen_grant_carry_12(.gen_grant_carry_c(ab_BIT_0___h13505),
.gen_grant_carry_r(output_arbs_1_select_requests[4]),
.gen_grant_carry_p(oas_1_token_BIT_4___h13610),
.gen_grant_carry(ab__h12572));
module_gen_grant_carry instance_gen_grant_carry_13(.gen_grant_carry_c(ab_BIT_0___h14084),
.gen_grant_carry_r(output_arbs_1_select_requests[0]),
.gen_grant_carry_p(oas_1_token_BIT_0___h13182),
.gen_grant_carry(ab__h15492));
module_gen_grant_carry instance_gen_grant_carry_14(.gen_grant_carry_c(ab_BIT_0___h15252),
.gen_grant_carry_r(output_arbs_1_select_requests[1]),
.gen_grant_carry_p(oas_1_token_BIT_1___h13289),
.gen_grant_carry(ab__h15197));
module_gen_grant_carry instance_gen_grant_carry_15(.gen_grant_carry_c(ab_BIT_0___h14957),
.gen_grant_carry_r(output_arbs_1_select_requests[2]),
.gen_grant_carry_p(oas_1_token_BIT_2___h13396),
.gen_grant_carry(ab__h14853));
module_gen_grant_carry instance_gen_grant_carry_16(.gen_grant_carry_c(ab_BIT_0___h14613),
.gen_grant_carry_r(output_arbs_1_select_requests[3]),
.gen_grant_carry_p(oas_1_token_BIT_3___h13503),
.gen_grant_carry(ab__h14460));
module_gen_grant_carry instance_gen_grant_carry_17(.gen_grant_carry_c(ab_BIT_0___h14220),
.gen_grant_carry_r(output_arbs_1_select_requests[4]),
.gen_grant_carry_p(oas_1_token_BIT_4___h13610),
.gen_grant_carry(ab__h14013));
module_gen_grant_carry instance_gen_grant_carry_47(.gen_grant_carry_c(1'd0),
.gen_grant_carry_r(output_arbs_2_select_requests[0]),
.gen_grant_carry_p(oas_2_token_BIT_0___h20222),
.gen_grant_carry(ab__h19672));
module_gen_grant_carry instance_gen_grant_carry_18(.gen_grant_carry_c(ab_BIT_0___h20224),
.gen_grant_carry_r(output_arbs_2_select_requests[1]),
.gen_grant_carry_p(oas_2_token_BIT_1___h20329),
.gen_grant_carry(ab__h19657));
module_gen_grant_carry instance_gen_grant_carry_19(.gen_grant_carry_c(ab_BIT_0___h20331),
.gen_grant_carry_r(output_arbs_2_select_requests[2]),
.gen_grant_carry_p(oas_2_token_BIT_2___h20436),
.gen_grant_carry(ab__h19642));
module_gen_grant_carry instance_gen_grant_carry_20(.gen_grant_carry_c(ab_BIT_0___h20438),
.gen_grant_carry_r(output_arbs_2_select_requests[3]),
.gen_grant_carry_p(oas_2_token_BIT_3___h20543),
.gen_grant_carry(ab__h19627));
module_gen_grant_carry instance_gen_grant_carry_21(.gen_grant_carry_c(ab_BIT_0___h20545),
.gen_grant_carry_r(output_arbs_2_select_requests[4]),
.gen_grant_carry_p(oas_2_token_BIT_4___h20650),
.gen_grant_carry(ab__h19612));
module_gen_grant_carry instance_gen_grant_carry_22(.gen_grant_carry_c(ab_BIT_0___h21124),
.gen_grant_carry_r(output_arbs_2_select_requests[0]),
.gen_grant_carry_p(oas_2_token_BIT_0___h20222),
.gen_grant_carry(ab__h22532));
module_gen_grant_carry instance_gen_grant_carry_23(.gen_grant_carry_c(ab_BIT_0___h22292),
.gen_grant_carry_r(output_arbs_2_select_requests[1]),
.gen_grant_carry_p(oas_2_token_BIT_1___h20329),
.gen_grant_carry(ab__h22237));
module_gen_grant_carry instance_gen_grant_carry_24(.gen_grant_carry_c(ab_BIT_0___h21997),
.gen_grant_carry_r(output_arbs_2_select_requests[2]),
.gen_grant_carry_p(oas_2_token_BIT_2___h20436),
.gen_grant_carry(ab__h21893));
module_gen_grant_carry instance_gen_grant_carry_25(.gen_grant_carry_c(ab_BIT_0___h21653),
.gen_grant_carry_r(output_arbs_2_select_requests[3]),
.gen_grant_carry_p(oas_2_token_BIT_3___h20543),
.gen_grant_carry(ab__h21500));
module_gen_grant_carry instance_gen_grant_carry_26(.gen_grant_carry_c(ab_BIT_0___h21260),
.gen_grant_carry_r(output_arbs_2_select_requests[4]),
.gen_grant_carry_p(oas_2_token_BIT_4___h20650),
.gen_grant_carry(ab__h21053));
module_gen_grant_carry instance_gen_grant_carry_48(.gen_grant_carry_c(1'd0),
.gen_grant_carry_r(output_arbs_3_select_requests[0]),
.gen_grant_carry_p(oas_3_token_BIT_0___h27262),
.gen_grant_carry(ab__h26712));
module_gen_grant_carry instance_gen_grant_carry_27(.gen_grant_carry_c(ab_BIT_0___h27264),
.gen_grant_carry_r(output_arbs_3_select_requests[1]),
.gen_grant_carry_p(oas_3_token_BIT_1___h27369),
.gen_grant_carry(ab__h26697));
module_gen_grant_carry instance_gen_grant_carry_28(.gen_grant_carry_c(ab_BIT_0___h27371),
.gen_grant_carry_r(output_arbs_3_select_requests[2]),
.gen_grant_carry_p(oas_3_token_BIT_2___h27476),
.gen_grant_carry(ab__h26682));
module_gen_grant_carry instance_gen_grant_carry_29(.gen_grant_carry_c(ab_BIT_0___h27478),
.gen_grant_carry_r(output_arbs_3_select_requests[3]),
.gen_grant_carry_p(oas_3_token_BIT_3___h27583),
.gen_grant_carry(ab__h26667));
module_gen_grant_carry instance_gen_grant_carry_30(.gen_grant_carry_c(ab_BIT_0___h27585),
.gen_grant_carry_r(output_arbs_3_select_requests[4]),
.gen_grant_carry_p(oas_3_token_BIT_4___h27690),
.gen_grant_carry(ab__h26652));
module_gen_grant_carry instance_gen_grant_carry_31(.gen_grant_carry_c(ab_BIT_0___h28164),
.gen_grant_carry_r(output_arbs_3_select_requests[0]),
.gen_grant_carry_p(oas_3_token_BIT_0___h27262),
.gen_grant_carry(ab__h29572));
module_gen_grant_carry instance_gen_grant_carry_32(.gen_grant_carry_c(ab_BIT_0___h29332),
.gen_grant_carry_r(output_arbs_3_select_requests[1]),
.gen_grant_carry_p(oas_3_token_BIT_1___h27369),
.gen_grant_carry(ab__h29277));
module_gen_grant_carry instance_gen_grant_carry_33(.gen_grant_carry_c(ab_BIT_0___h29037),
.gen_grant_carry_r(output_arbs_3_select_requests[2]),
.gen_grant_carry_p(oas_3_token_BIT_2___h27476),
.gen_grant_carry(ab__h28933));
module_gen_grant_carry instance_gen_grant_carry_34(.gen_grant_carry_c(ab_BIT_0___h28693),
.gen_grant_carry_r(output_arbs_3_select_requests[3]),
.gen_grant_carry_p(oas_3_token_BIT_3___h27583),
.gen_grant_carry(ab__h28540));
module_gen_grant_carry instance_gen_grant_carry_35(.gen_grant_carry_c(ab_BIT_0___h28300),
.gen_grant_carry_r(output_arbs_3_select_requests[4]),
.gen_grant_carry_p(oas_3_token_BIT_4___h27690),
.gen_grant_carry(ab__h28093));
module_gen_grant_carry instance_gen_grant_carry_49(.gen_grant_carry_c(1'd0),
.gen_grant_carry_r(output_arbs_4_select_requests[0]),
.gen_grant_carry_p(oas_4_token_BIT_0___h34302),
.gen_grant_carry(ab__h33752));
module_gen_grant_carry instance_gen_grant_carry_36(.gen_grant_carry_c(ab_BIT_0___h34304),
.gen_grant_carry_r(output_arbs_4_select_requests[1]),
.gen_grant_carry_p(oas_4_token_BIT_1___h34409),
.gen_grant_carry(ab__h33737));
module_gen_grant_carry instance_gen_grant_carry_37(.gen_grant_carry_c(ab_BIT_0___h34411),
.gen_grant_carry_r(output_arbs_4_select_requests[2]),
.gen_grant_carry_p(oas_4_token_BIT_2___h34516),
.gen_grant_carry(ab__h33722));
module_gen_grant_carry instance_gen_grant_carry_38(.gen_grant_carry_c(ab_BIT_0___h34518),
.gen_grant_carry_r(output_arbs_4_select_requests[3]),
.gen_grant_carry_p(oas_4_token_BIT_3___h34623),
.gen_grant_carry(ab__h33707));
module_gen_grant_carry instance_gen_grant_carry_39(.gen_grant_carry_c(ab_BIT_0___h34625),
.gen_grant_carry_r(output_arbs_4_select_requests[4]),
.gen_grant_carry_p(oas_4_token_BIT_4___h34730),
.gen_grant_carry(ab__h33692));
module_gen_grant_carry instance_gen_grant_carry_40(.gen_grant_carry_c(ab_BIT_0___h35204),
.gen_grant_carry_r(output_arbs_4_select_requests[0]),
.gen_grant_carry_p(oas_4_token_BIT_0___h34302),
.gen_grant_carry(ab__h36612));
module_gen_grant_carry instance_gen_grant_carry_41(.gen_grant_carry_c(ab_BIT_0___h36372),
.gen_grant_carry_r(output_arbs_4_select_requests[1]),
.gen_grant_carry_p(oas_4_token_BIT_1___h34409),
.gen_grant_carry(ab__h36317));
module_gen_grant_carry instance_gen_grant_carry_42(.gen_grant_carry_c(ab_BIT_0___h36077),
.gen_grant_carry_r(output_arbs_4_select_requests[2]),
.gen_grant_carry_p(oas_4_token_BIT_2___h34516),
.gen_grant_carry(ab__h35973));
module_gen_grant_carry instance_gen_grant_carry_43(.gen_grant_carry_c(ab_BIT_0___h35733),
.gen_grant_carry_r(output_arbs_4_select_requests[3]),
.gen_grant_carry_p(oas_4_token_BIT_3___h34623),
.gen_grant_carry(ab__h35580));
module_gen_grant_carry instance_gen_grant_carry_44(.gen_grant_carry_c(ab_BIT_0___h35340),
.gen_grant_carry_r(output_arbs_4_select_requests[4]),
.gen_grant_carry_p(oas_4_token_BIT_4___h34730),
.gen_grant_carry(ab__h35133));
assign NOT_gen_grant_carry_00_BIT_1_01_14_AND_NOT_gen_ETC___d328 =
!ab__h33692[1] && !ab__h35133[1] && !ab__h33707[1] &&
!ab__h35580[1] &&
(ab__h33722[1] || ab__h35973[1]) ;
assign NOT_gen_grant_carry_00_BIT_1_01_14_AND_NOT_gen_ETC___d348 =
!ab__h33692[1] && !ab__h35133[1] && !ab__h33707[1] &&
!ab__h35580[1] &&
NOT_gen_grant_carry_92_BIT_1_24_30_AND_NOT_gen_ETC___d346 ;
assign NOT_gen_grant_carry_0_BIT_1_1_04_AND_NOT_gen_g_ETC___d118 =
!ab__h12572[1] && !ab__h14013[1] && !ab__h12587[1] &&
!ab__h14460[1] &&
(ab__h12602[1] || ab__h14853[1]) ;
assign NOT_gen_grant_carry_0_BIT_1_1_04_AND_NOT_gen_g_ETC___d138 =
!ab__h12572[1] && !ab__h14013[1] && !ab__h12587[1] &&
!ab__h14460[1] &&
NOT_gen_grant_carry_2_BIT_1_14_20_AND_NOT_gen__ETC___d136 ;
assign NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d48 =
!ab__h5532[1] && !ab__h6973[1] && !ab__h5547[1] &&
!ab__h7420[1] &&
(ab__h5562[1] || ab__h7813[1]) ;
assign NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d68 =
!ab__h5532[1] && !ab__h6973[1] && !ab__h5547[1] &&
!ab__h7420[1] &&
NOT_gen_grant_carry_2_BIT_1_4_0_AND_NOT_gen_gr_ETC___d66 ;
assign NOT_gen_grant_carry_22_BIT_1_54_60_AND_NOT_gen_ETC___d276 =
!ab__h26682[1] && !ab__h28933[1] && !ab__h26697[1] &&
!ab__h29277[1] &&
(ab__h26712[1] || ab__h29572[1]) ;
assign NOT_gen_grant_carry_26_BIT_1_47_51_AND_NOT_gen_ETC___d267 =
!ab__h26667[1] && !ab__h28540[1] && !ab__h26682[1] &&
!ab__h28933[1] &&
(ab__h26697[1] || ab__h29277[1]) ;
assign NOT_gen_grant_carry_2_BIT_1_14_20_AND_NOT_gen__ETC___d136 =
!ab__h12602[1] && !ab__h14853[1] && !ab__h12617[1] &&
!ab__h15197[1] &&
(ab__h12632[1] || ab__h15492[1]) ;
assign NOT_gen_grant_carry_2_BIT_1_4_0_AND_NOT_gen_gr_ETC___d66 =
!ab__h5562[1] && !ab__h7813[1] && !ab__h5577[1] &&
!ab__h8157[1] &&
(ab__h5592[1] || ab__h8452[1]) ;
assign NOT_gen_grant_carry_30_BIT_1_31_44_AND_NOT_gen_ETC___d258 =
!ab__h26652[1] && !ab__h28093[1] && !ab__h26667[1] &&
!ab__h28540[1] &&
(ab__h26682[1] || ab__h28933[1]) ;
assign NOT_gen_grant_carry_30_BIT_1_31_44_AND_NOT_gen_ETC___d278 =
!ab__h26652[1] && !ab__h28093[1] && !ab__h26667[1] &&
!ab__h28540[1] &&
NOT_gen_grant_carry_22_BIT_1_54_60_AND_NOT_gen_ETC___d276 ;
assign NOT_gen_grant_carry_52_BIT_1_84_90_AND_NOT_gen_ETC___d206 =
!ab__h19642[1] && !ab__h21893[1] && !ab__h19657[1] &&
!ab__h22237[1] &&
(ab__h19672[1] || ab__h22532[1]) ;
assign NOT_gen_grant_carry_56_BIT_1_77_81_AND_NOT_gen_ETC___d197 =
!ab__h19627[1] && !ab__h21500[1] && !ab__h19642[1] &&
!ab__h21893[1] &&
(ab__h19657[1] || ab__h22237[1]) ;
assign NOT_gen_grant_carry_60_BIT_1_61_74_AND_NOT_gen_ETC___d188 =
!ab__h19612[1] && !ab__h21053[1] && !ab__h19627[1] &&
!ab__h21500[1] &&
(ab__h19642[1] || ab__h21893[1]) ;
assign NOT_gen_grant_carry_60_BIT_1_61_74_AND_NOT_gen_ETC___d208 =
!ab__h19612[1] && !ab__h21053[1] && !ab__h19627[1] &&
!ab__h21500[1] &&
NOT_gen_grant_carry_52_BIT_1_84_90_AND_NOT_gen_ETC___d206 ;
assign NOT_gen_grant_carry_6_BIT_1_07_11_AND_NOT_gen__ETC___d127 =
!ab__h12587[1] && !ab__h14460[1] && !ab__h12602[1] &&
!ab__h14853[1] &&
(ab__h12617[1] || ab__h15197[1]) ;
assign NOT_gen_grant_carry_6_BIT_1_7_1_AND_NOT_gen_gr_ETC___d57 =
!ab__h5547[1] && !ab__h7420[1] && !ab__h5562[1] &&
!ab__h7813[1] &&
(ab__h5577[1] || ab__h8157[1]) ;
assign NOT_gen_grant_carry_92_BIT_1_24_30_AND_NOT_gen_ETC___d346 =
!ab__h33722[1] && !ab__h35973[1] && !ab__h33737[1] &&
!ab__h36317[1] &&
(ab__h33752[1] || ab__h36612[1]) ;
assign NOT_gen_grant_carry_96_BIT_1_17_21_AND_NOT_gen_ETC___d337 =
!ab__h33707[1] && !ab__h35580[1] && !ab__h33722[1] &&
!ab__h35973[1] &&
(ab__h33737[1] || ab__h36317[1]) ;
assign ab_BIT_0___h13184 = ab__h12632[0] ;
assign ab_BIT_0___h13291 = ab__h12617[0] ;
assign ab_BIT_0___h13398 = ab__h12602[0] ;
assign ab_BIT_0___h13505 = ab__h12587[0] ;
assign ab_BIT_0___h14084 = ab__h12572[0] ;
assign ab_BIT_0___h14220 = ab__h14460[0] ;
assign ab_BIT_0___h14613 = ab__h14853[0] ;
assign ab_BIT_0___h14957 = ab__h15197[0] ;
assign ab_BIT_0___h15252 = ab__h15492[0] ;
assign ab_BIT_0___h20224 = ab__h19672[0] ;
assign ab_BIT_0___h20331 = ab__h19657[0] ;
assign ab_BIT_0___h20438 = ab__h19642[0] ;
assign ab_BIT_0___h20545 = ab__h19627[0] ;
assign ab_BIT_0___h21124 = ab__h19612[0] ;
assign ab_BIT_0___h21260 = ab__h21500[0] ;
assign ab_BIT_0___h21653 = ab__h21893[0] ;
assign ab_BIT_0___h21997 = ab__h22237[0] ;
assign ab_BIT_0___h22292 = ab__h22532[0] ;
assign ab_BIT_0___h27264 = ab__h26712[0] ;
assign ab_BIT_0___h27371 = ab__h26697[0] ;
assign ab_BIT_0___h27478 = ab__h26682[0] ;
assign ab_BIT_0___h27585 = ab__h26667[0] ;
assign ab_BIT_0___h28164 = ab__h26652[0] ;
assign ab_BIT_0___h28300 = ab__h28540[0] ;
assign ab_BIT_0___h28693 = ab__h28933[0] ;
assign ab_BIT_0___h29037 = ab__h29277[0] ;
assign ab_BIT_0___h29332 = ab__h29572[0] ;
assign ab_BIT_0___h34304 = ab__h33752[0] ;
assign ab_BIT_0___h34411 = ab__h33737[0] ;
assign ab_BIT_0___h34518 = ab__h33722[0] ;
assign ab_BIT_0___h34625 = ab__h33707[0] ;
assign ab_BIT_0___h35204 = ab__h33692[0] ;
assign ab_BIT_0___h35340 = ab__h35580[0] ;
assign ab_BIT_0___h35733 = ab__h35973[0] ;
assign ab_BIT_0___h36077 = ab__h36317[0] ;
assign ab_BIT_0___h36372 = ab__h36612[0] ;
assign ab_BIT_0___h6144 = ab__h5592[0] ;
assign ab_BIT_0___h6251 = ab__h5577[0] ;
assign ab_BIT_0___h6358 = ab__h5562[0] ;
assign ab_BIT_0___h6465 = ab__h5547[0] ;
assign ab_BIT_0___h7044 = ab__h5532[0] ;
assign ab_BIT_0___h7180 = ab__h7420[0] ;
assign ab_BIT_0___h7573 = ab__h7813[0] ;
assign ab_BIT_0___h7917 = ab__h8157[0] ;
assign ab_BIT_0___h8212 = ab__h8452[0] ;
assign oas_0_token_BIT_0___h6142 = oas_0_token[0] ;
assign oas_0_token_BIT_1___h6249 = oas_0_token[1] ;
assign oas_0_token_BIT_2___h6356 = oas_0_token[2] ;
assign oas_0_token_BIT_3___h6463 = oas_0_token[3] ;
assign oas_0_token_BIT_4___h6570 = oas_0_token[4] ;
assign oas_1_token_BIT_0___h13182 = oas_1_token[0] ;
assign oas_1_token_BIT_1___h13289 = oas_1_token[1] ;
assign oas_1_token_BIT_2___h13396 = oas_1_token[2] ;
assign oas_1_token_BIT_3___h13503 = oas_1_token[3] ;
assign oas_1_token_BIT_4___h13610 = oas_1_token[4] ;
assign oas_2_token_BIT_0___h20222 = oas_2_token[0] ;
assign oas_2_token_BIT_1___h20329 = oas_2_token[1] ;
assign oas_2_token_BIT_2___h20436 = oas_2_token[2] ;
assign oas_2_token_BIT_3___h20543 = oas_2_token[3] ;
assign oas_2_token_BIT_4___h20650 = oas_2_token[4] ;
assign oas_3_token_BIT_0___h27262 = oas_3_token[0] ;
assign oas_3_token_BIT_1___h27369 = oas_3_token[1] ;
assign oas_3_token_BIT_2___h27476 = oas_3_token[2] ;
assign oas_3_token_BIT_3___h27583 = oas_3_token[3] ;
assign oas_3_token_BIT_4___h27690 = oas_3_token[4] ;
assign oas_4_token_BIT_0___h34302 = oas_4_token[0] ;
assign oas_4_token_BIT_1___h34409 = oas_4_token[1] ;
assign oas_4_token_BIT_2___h34516 = oas_4_token[2] ;
assign oas_4_token_BIT_3___h34623 = oas_4_token[3] ;
assign oas_4_token_BIT_4___h34730 = oas_4_token[4] ;
// handling of inlined registers
always@(posedge CLK)
begin
if (!RST_N)
begin
oas_0_token <= `BSV_ASSIGNMENT_DELAY 5'd1;
oas_1_token <= `BSV_ASSIGNMENT_DELAY 5'd2;
oas_2_token <= `BSV_ASSIGNMENT_DELAY 5'd4;
oas_3_token <= `BSV_ASSIGNMENT_DELAY 5'd8;
oas_4_token <= `BSV_ASSIGNMENT_DELAY 5'd16;
end
else
begin
if (oas_0_token$EN)
oas_0_token <= `BSV_ASSIGNMENT_DELAY oas_0_token$D_IN;
if (oas_1_token$EN)
oas_1_token <= `BSV_ASSIGNMENT_DELAY oas_1_token$D_IN;
if (oas_2_token$EN)
oas_2_token <= `BSV_ASSIGNMENT_DELAY oas_2_token$D_IN;
if (oas_3_token$EN)
oas_3_token <= `BSV_ASSIGNMENT_DELAY oas_3_token$D_IN;
if (oas_4_token$EN)
oas_4_token <= `BSV_ASSIGNMENT_DELAY oas_4_token$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
oas_0_token = 5'h0A;
oas_1_token = 5'h0A;
oas_2_token = 5'h0A;
oas_3_token = 5'h0A;
oas_4_token = 5'h0A;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkRouterOutputArbitersRoundRobin
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR4B_4_V
`define SKY130_FD_SC_LP__NOR4B_4_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog wrapper for nor4b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nor4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor4b_4 (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor4b_4 (
Y ,
A ,
B ,
C ,
D_N
);
output Y ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR4B_4_V
|
`timescale 1ns/1ps
module SensorFSM #(
parameter DataWidth = 8
) (
input Reset_n_i,
input Clk_i,
// top level
input Enable_i,
output reg CpuIntr_o,
output [2*DataWidth-1:0] SensorValue_o,
// to/from Measure-FSM
output reg MeasureFSM_Start_o,
input MeasureFSM_Done_i,
input MeasureFSM_Error_i,
input [DataWidth-1:0] MeasureFSM_Byte0_i,
input [DataWidth-1:0] MeasureFSM_Byte1_i,
// parameters
input [2*DataWidth-1:0] ParamThreshold_i,
input [2*DataWidth-1:0] ParamCounterPresetH_i,
input [2*DataWidth-1:0] ParamCounterPresetL_i
);
// Sensor FSM
localparam stDisabled = 3'b000;
localparam stIdle = 3'b001;
localparam stXfer = 3'b010;
localparam stNotify = 3'b011;
localparam stError = 3'b100;
reg [2:0] SensorFSM_State;
reg [2:0] SensorFSM_NextState;
wire SensorFSM_TimerOvfl;
reg SensorFSM_TimerPreset;
reg SensorFSM_TimerEnable;
wire SensorFSM_DiffTooLarge;
reg SensorFSM_StoreNewValue;
/////////////////////////////////////////////////////////////////////////////
// Word Arithmetic
// interconnecting signals
wire [2*DataWidth-1:0] SensorValue;
reg [2*DataWidth-1:0] Word0;
wire [2*DataWidth-1:0] AbsDiffResult;
/////////////////////////////////////////////////////////////////////////////
// FSM //////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
SensorFSM_State <= stDisabled;
end
else
begin
SensorFSM_State <= SensorFSM_NextState;
end
end
always @(SensorFSM_State, Enable_i, SensorFSM_TimerOvfl, MeasureFSM_Done_i, MeasureFSM_Error_i, SensorFSM_DiffTooLarge)
begin // process SensorFSM_CombProc
SensorFSM_NextState = SensorFSM_State;
// control signal default values
SensorFSM_TimerPreset = 1'b1;
SensorFSM_TimerEnable = 1'b0;
MeasureFSM_Start_o = 1'b0;
SensorFSM_StoreNewValue = 1'b0;
CpuIntr_o = 1'b0;
// next state and output logic
case (SensorFSM_State)
stDisabled: begin
if (Enable_i == 1'b1)
begin
SensorFSM_NextState = stIdle;
SensorFSM_TimerPreset = 1'b0;
SensorFSM_TimerEnable = 1'b1; // start timer
end
end
stIdle: begin
SensorFSM_TimerPreset = 1'b0;
SensorFSM_TimerEnable = 1'b1; // timer running
if (Enable_i == 1'b0)
begin
SensorFSM_NextState = stDisabled;
end
else
if (SensorFSM_TimerOvfl == 1'b1)
begin
SensorFSM_NextState = stXfer;
MeasureFSM_Start_o = 1'b1;
end
end
stXfer: begin
if (MeasureFSM_Error_i == 1'b1)
begin
// on I2C Error go to state "stError" and notify the CPU
SensorFSM_NextState = stError;
CpuIntr_o = 1'b1; // notify CPU
end
else if (MeasureFSM_Done_i == 1'b1)
begin
if (SensorFSM_DiffTooLarge == 1'b1)
begin
SensorFSM_NextState = stNotify;
SensorFSM_TimerPreset = 1'b0;
SensorFSM_TimerEnable = 1'b1; // timer running
SensorFSM_StoreNewValue = 1'b1; // store new value
end
else
begin
SensorFSM_NextState = stIdle;
end
end
end
stNotify: begin
SensorFSM_TimerPreset = 1'b1;
SensorFSM_TimerEnable = 1'b0; // preset timer
SensorFSM_NextState = stIdle;
CpuIntr_o = 1'b1; // notify CPU
end
stError: begin
// stay in this error state until the FSM is disabled
if (Enable_i == 1'b0)
begin
SensorFSM_NextState = stDisabled;
end
end
default: begin
end
endcase
end
/////////////////////////////////////////////////////////////////////////////
// Word Arithmetic //////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
reg [31:0] SensorFSM_Timer;
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
SensorFSM_Timer <= 32'd0;
end
else
begin
if (SensorFSM_TimerPreset)
begin
SensorFSM_Timer <= {ParamCounterPresetH_i, ParamCounterPresetL_i};
end
else if (SensorFSM_TimerEnable)
begin
SensorFSM_Timer <= SensorFSM_Timer - 1'b1;
end
end
end
assign SensorFSM_TimerOvfl = (SensorFSM_Timer == 0) ? 1'b1 : 1'b0;
assign SensorValue = {MeasureFSM_Byte1_i, MeasureFSM_Byte0_i};
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
Word0 <= 16'd0;
end
else
begin
if (SensorFSM_StoreNewValue)
begin
Word0 <= SensorValue;
end
end
end
wire [2*DataWidth : 0] DiffAB;
wire [2*DataWidth-1 : 0] DiffBA;
assign DiffAB = {1'b0, SensorValue} - {1'b0, Word0};
assign DiffBA = Word0 - SensorValue;
assign AbsDiffResult = DiffAB[2*DataWidth] ? DiffBA : DiffAB[2*DataWidth-1 : 0];
assign SensorFSM_DiffTooLarge = (AbsDiffResult > ParamThreshold_i) ? 1'b1 : 1'b0;
assign SensorValue_o = Word0;
endmodule // SensorFSM
|
(** * Poly: Polymorphism and Higher-Order Functions *)
(** In this chapter we continue our development of basic
concepts of functional programming. The critical new ideas are
_polymorphism_ (abstracting functions over the types of the data
they manipulate) and _higher-order functions_ (treating functions
as data).
*)
Require Export Lists.
(* ###################################################### *)
(** * Polymorphism *)
(* ###################################################### *)
(** ** Polymorphic Lists *)
(** For the last couple of chapters, we've been working just
with lists of numbers. Obviously, interesting programs also need
to be able to manipulate lists with elements from other types --
lists of strings, lists of booleans, lists of lists, etc. We
_could_ just define a new inductive datatype for each of these,
for example... *)
Inductive boollist : Type :=
| bool_nil : boollist
| bool_cons : bool -> boollist -> boollist.
(** ... but this would quickly become tedious, partly because we
have to make up different constructor names for each datatype, but
mostly because we would also need to define new versions of all
our list manipulating functions ([length], [rev], etc.) for each
new datatype definition. *)
(** *** *)
(** To avoid all this repetition, Coq supports _polymorphic_
inductive type definitions. For example, here is a _polymorphic
list_ datatype. *)
Inductive list (X:Type) : Type :=
| nil : list X
| cons : X -> list X -> list X.
(** This is exactly like the definition of [natlist] from the
previous chapter, except that the [nat] argument to the [cons]
constructor has been replaced by an arbitrary type [X], a binding
for [X] has been added to the header, and the occurrences of
[natlist] in the types of the constructors have been replaced by
[list X]. (We can re-use the constructor names [nil] and [cons]
because the earlier definition of [natlist] was inside of a
[Module] definition that is now out of scope.) *)
(** What sort of thing is [list] itself? One good way to think
about it is that [list] is a _function_ from [Type]s to
[Inductive] definitions; or, to put it another way, [list] is a
function from [Type]s to [Type]s. For any particular type [X],
the type [list X] is an [Inductive]ly defined set of lists whose
elements are things of type [X]. *)
(** With this definition, when we use the constructors [nil] and
[cons] to build lists, we need to tell Coq the type of the
elements in the lists we are building -- that is, [nil] and [cons]
are now _polymorphic constructors_. Observe the types of these
constructors: *)
Check nil.
(* ===> nil : forall X : Type, list X *)
Check cons.
(* ===> cons : forall X : Type, X -> list X -> list X *)
(** The "[forall X]" in these types can be read as an additional
argument to the constructors that determines the expected types of
the arguments that follow. When [nil] and [cons] are used, these
arguments are supplied in the same way as the others. For
example, the list containing [2] and [1] is written like this: *)
Check (cons nat 2 (cons nat 1 (nil nat))).
(** (We've gone back to writing [nil] and [cons] explicitly here
because we haven't yet defined the [ [] ] and [::] notations for
the new version of lists. We'll do that in a bit.) *)
(** We can now go back and make polymorphic (or "generic")
versions of all the list-processing functions that we wrote
before. Here is [length], for example: *)
(** *** *)
Fixpoint length (X:Type) (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length X t)
end.
(** Note that the uses of [nil] and [cons] in [match] patterns
do not require any type annotations: Coq already knows that the list
[l] contains elements of type [X], so there's no reason to include
[X] in the pattern. (More precisely, the type [X] is a parameter
of the whole definition of [list], not of the individual
constructors. We'll come back to this point later.)
As with [nil] and [cons], we can use [length] by applying it first
to a type and then to its list argument: *)
Example test_length1 :
length nat (cons nat 1 (cons nat 2 (nil nat))) = 2.
Proof. reflexivity. Qed.
(** To use our length with other kinds of lists, we simply
instantiate it with an appropriate type parameter: *)
Example test_length2 :
length bool (cons bool true (nil bool)) = 1.
Proof. reflexivity. Qed.
(** *** *)
(** Let's close this subsection by re-implementing a few other
standard list functions on our new polymorphic lists: *)
Fixpoint app (X : Type) (l1 l2 : list X)
: (list X) :=
match l1 with
| nil => l2
| cons h t => cons X h (app X t l2)
end.
Fixpoint snoc (X:Type) (l:list X) (v:X) : (list X) :=
match l with
| nil => cons X v (nil X)
| cons h t => cons X h (snoc X t v)
end.
Fixpoint rev (X:Type) (l:list X) : list X :=
match l with
| nil => nil X
| cons h t => snoc X (rev X t) h
end.
Example test_rev1 :
rev nat (cons nat 1 (cons nat 2 (nil nat)))
= (cons nat 2 (cons nat 1 (nil nat))).
Proof. reflexivity. Qed.
Example test_rev2:
rev bool (nil bool) = nil bool.
Proof. reflexivity. Qed.
Module MumbleBaz.
(** **** Exercise: 2 stars (mumble_grumble) *)
(** Consider the following two inductively defined types. *)
Inductive mumble : Type :=
| a : mumble
| b : mumble -> nat -> mumble
| c : mumble.
Inductive grumble (X:Type) : Type :=
| d : mumble -> grumble X
| e : X -> grumble X.
(** Which of the following are well-typed elements of [grumble X] for
some type [X]?
- [d (b a 5)]
- [d mumble (b a 5)]
- [d bool (b a 5)]
- [e bool true]
- [e mumble (b c 0)]
- [e bool (b c 0)]
- [c]
(* FILL IN HERE *)
*)
(** [] *)
(** **** Exercise: 2 stars (baz_num_elts) *)
(** Consider the following inductive definition: *)
Inductive baz : Type :=
| x : baz -> baz
| y : baz -> bool -> baz.
(** How _many_ elements does the type [baz] have?
(* None. I mean, good luck constructing one! *)
*)
(** [] *)
End MumbleBaz.
(* ###################################################### *)
(** *** Type Annotation Inference *)
(** Let's write the definition of [app] again, but this time we won't
specify the types of any of the arguments. Will Coq still accept
it? *)
Fixpoint app' X l1 l2 : list X :=
match l1 with
| nil => l2
| cons h t => cons X h (app' X t l2)
end.
(** Indeed it will. Let's see what type Coq has assigned to [app']: *)
Check app'.
(* ===> forall X : Type, list X -> list X -> list X *)
Check app.
(* ===> forall X : Type, list X -> list X -> list X *)
(** It has exactly the same type type as [app]. Coq was able to
use a process called _type inference_ to deduce what the types of
[X], [l1], and [l2] must be, based on how they are used. For
example, since [X] is used as an argument to [cons], it must be a
[Type], since [cons] expects a [Type] as its first argument;
matching [l1] with [nil] and [cons] means it must be a [list]; and
so on.
This powerful facility means we don't always have to write
explicit type annotations everywhere, although explicit type
annotations are still quite useful as documentation and sanity
checks. You should try to find a balance in your own code between
too many type annotations (so many that they clutter and distract)
and too few (which forces readers to perform type inference in
their heads in order to understand your code). *)
(* ###################################################### *)
(** *** Type Argument Synthesis *)
(** Whenever we use a polymorphic function, we need to pass it
one or more types in addition to its other arguments. For
example, the recursive call in the body of the [length] function
above must pass along the type [X]. But just like providing
explicit type annotations everywhere, this is heavy and verbose.
Since the second argument to [length] is a list of [X]s, it seems
entirely obvious that the first argument can only be [X] -- why
should we have to write it explicitly?
Fortunately, Coq permits us to avoid this kind of redundancy. In
place of any type argument we can write the "implicit argument"
[_], which can be read as "Please figure out for yourself what
type belongs here." More precisely, when Coq encounters a [_], it
will attempt to _unify_ all locally available information -- the
type of the function being applied, the types of the other
arguments, and the type expected by the context in which the
application appears -- to determine what concrete type should
replace the [_].
This may sound similar to type annotation inference -- and,
indeed, the two procedures rely on the same underlying mechanisms.
Instead of simply omitting the types of some arguments to a
function, like
app' X l1 l2 : list X :=
we can also replace the types with [_], like
app' (X : _) (l1 l2 : _) : list X :=
which tells Coq to attempt to infer the missing information, just
as with argument synthesis.
Using implicit arguments, the [length] function can be written
like this: *)
Fixpoint length' (X:Type) (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length' _ t)
end.
(** In this instance, we don't save much by writing [_] instead of
[X]. But in many cases the difference can be significant. For
example, suppose we want to write down a list containing the
numbers [1], [2], and [3]. Instead of writing this... *)
Definition list123 :=
cons nat 1 (cons nat 2 (cons nat 3 (nil nat))).
(** ...we can use argument synthesis to write this: *)
Definition list123' := cons _ 1 (cons _ 2 (cons _ 3 (nil _))).
(* ###################################################### *)
(** *** Implicit Arguments *)
(** In fact, we can go further. To avoid having to sprinkle [_]'s
throughout our programs, we can tell Coq _always_ to infer the
type argument(s) of a given function. The [Arguments] directive
specifies the name of the function or constructor, and then lists
its argument names, with curly braces around any arguments to be
treated as implicit.
*)
Arguments nil {X}.
Arguments cons {X} _ _. (* use underscore for argument position that has no name *)
Arguments length {X} l.
Arguments app {X} l1 l2.
Arguments rev {X} l.
Arguments snoc {X} l v.
(* note: no _ arguments required... *)
Definition list123'' := cons 1 (cons 2 (cons 3 nil)).
Check (length list123'').
(** *** *)
(** Alternatively, we can declare an argument to be implicit while
defining the function itself, by surrounding the argument in curly
braces. For example: *)
Fixpoint length'' {X:Type} (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length'' t)
end.
(** (Note that we didn't even have to provide a type argument to
the recursive call to [length'']; indeed, it is invalid to provide
one.) We will use this style whenever possible, although we will
continue to use use explicit [Argument] declarations for
[Inductive] constructors. *)
(** *** *)
(** One small problem with declaring arguments [Implicit] is
that, occasionally, Coq does not have enough local information to
determine a type argument; in such cases, we need to tell Coq that
we want to give the argument explicitly this time, even though
we've globally declared it to be [Implicit]. For example, suppose we
write this: *)
(* Definition mynil := nil. *)
(** If we uncomment this definition, Coq will give us an error,
because it doesn't know what type argument to supply to [nil]. We
can help it by providing an explicit type declaration (so that Coq
has more information available when it gets to the "application"
of [nil]): *)
Definition mynil : list nat := nil.
(** Alternatively, we can force the implicit arguments to be explicit by
prefixing the function name with [@]. *)
Check @nil.
Definition mynil' := @nil nat.
(** *** *)
(** Using argument synthesis and implicit arguments, we can
define convenient notation for lists, as before. Since we have
made the constructor type arguments implicit, Coq will know to
automatically infer these when we use the notations. *)
Notation "x :: y" := (cons x y)
(at level 60, right associativity).
Notation "[ ]" := nil.
Notation "[ x ; .. ; y ]" := (cons x .. (cons y []) ..).
Notation "x ++ y" := (app x y)
(at level 60, right associativity).
(** Now lists can be written just the way we'd hope: *)
Definition list123''' := [1; 2; 3].
(* ###################################################### *)
(** *** Exercises: Polymorphic Lists *)
(** **** Exercise: 2 stars, optional (poly_exercises) *)
(** Here are a few simple exercises, just like ones in the [Lists]
chapter, for practice with polymorphism. Fill in the definitions
and complete the proofs below. *)
Fixpoint repeat {X : Type} (n : X) (count : nat) : list X :=
match count with
| 0 => []
| (S c') => n :: (repeat n c')
end.
Example test_repeat1:
repeat true 2 = cons true (cons true nil).
Proof. reflexivity. Qed.
Theorem nil_app : forall X:Type, forall l:list X,
app [] l = l.
Proof.
intros. simpl. reflexivity.
Qed.
Theorem rev_snoc : forall X : Type,
forall v : X,
forall s : list X,
rev (snoc s v) = v :: (rev s).
Proof.
intros.
induction s.
Case "Base". simpl. reflexivity.
Case "Ind". simpl. rewrite IHs. reflexivity.
Qed.
Theorem rev_involutive : forall X : Type, forall l : list X,
rev (rev l) = l.
Proof.
intros.
induction l.
Case "Base". simpl. reflexivity.
Case "Ind". simpl. rewrite rev_snoc. rewrite IHl. reflexivity.
Qed.
Theorem snoc_with_append : forall X : Type,
forall l1 l2 : list X,
forall v : X,
snoc (l1 ++ l2) v = l1 ++ (snoc l2 v).
Proof.
intros. simpl.
induction l1.
Case "Base". simpl. reflexivity.
Case "Ind". simpl. rewrite IHl1. reflexivity.
Qed.
(** [] *)
(* ###################################################### *)
(** ** Polymorphic Pairs *)
(** Following the same pattern, the type definition we gave in
the last chapter for pairs of numbers can be generalized to
_polymorphic pairs_ (or _products_): *)
Inductive prod (X Y : Type) : Type :=
pair : X -> Y -> prod X Y.
Arguments pair {X} {Y} _ _.
(** As with lists, we make the type arguments implicit and define the
familiar concrete notation. *)
Notation "( x , y )" := (pair x y).
(** We can also use the [Notation] mechanism to define the standard
notation for pair _types_: *)
Notation "X * Y" := (prod X Y) : type_scope.
(** (The annotation [: type_scope] tells Coq that this abbreviation
should be used when parsing types. This avoids a clash with the
multiplication symbol.) *)
(** *** *)
(** A note of caution: it is easy at first to get [(x,y)] and
[X*Y] confused. Remember that [(x,y)] is a _value_ built from two
other values; [X*Y] is a _type_ built from two other types. If
[x] has type [X] and [y] has type [Y], then [(x,y)] has type
[X*Y]. *)
(** The first and second projection functions now look pretty
much as they would in any functional programming language. *)
Definition fst {X Y : Type} (p : X * Y) : X :=
match p with (x,y) => x end.
Definition snd {X Y : Type} (p : X * Y) : Y :=
match p with (x,y) => y end.
(** The following function takes two lists and combines them
into a list of pairs. In many functional programming languages,
it is called [zip]. We call it [combine] for consistency with
Coq's standard library. *)
(** Note that the pair notation can be used both in expressions and in
patterns... *)
Fixpoint combine {X Y : Type} (lx : list X) (ly : list Y)
: list (X*Y) :=
match (lx,ly) with
| ([],_) => []
| (_,[]) => []
| (x::tx, y::ty) => (x,y) :: (combine tx ty)
end.
(** **** Exercise: 1 star, optional (combine_checks) *)
(** Try answering the following questions on paper and
checking your answers in coq:
- What is the type of [combine] (i.e., what does [Check
@combine] print?)
- What does
Eval compute in (combine [1;2] [false;false;true;true]).
print? []
*)
(** **** Exercise: 2 stars (split) *)
(** The function [split] is the right inverse of combine: it takes a
list of pairs and returns a pair of lists. In many functional
programing languages, this function is called [unzip].
Uncomment the material below and fill in the definition of
[split]. Make sure it passes the given unit tests. *)
Fixpoint split
{X Y : Type} (l : list (X*Y))
: (list X) * (list Y) :=
match l with
| [] => ([], [])
| (l, r) :: t => match split t with
| (ls, rs) => (l :: ls, r :: rs)
end
end.
Example test_split:
split [(1,false);(2,false)] = ([1;2],[false;false]).
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################### *)
(** ** Polymorphic Options *)
(** One last polymorphic type for now: _polymorphic options_.
The type declaration generalizes the one for [natoption] in the
previous chapter: *)
Inductive option (X:Type) : Type :=
| Some : X -> option X
| None : option X.
Arguments Some {X} _.
Arguments None {X}.
(** *** *)
(** We can now rewrite the [index] function so that it works
with any type of lists. *)
Fixpoint index {X : Type} (n : nat)
(l : list X) : option X :=
match l with
| [] => None
| a :: l' => if beq_nat n O then Some a else index (pred n) l'
end.
Example test_index1 : index 0 [4;5;6;7] = Some 4.
Proof. reflexivity. Qed.
Example test_index2 : index 1 [[1];[2]] = Some [2].
Proof. reflexivity. Qed.
Example test_index3 : index 2 [true] = None.
Proof. reflexivity. Qed.
(** **** Exercise: 1 star, optional (hd_opt_poly) *)
(** Complete the definition of a polymorphic version of the
[hd_opt] function from the last chapter. Be sure that it
passes the unit tests below. *)
Definition hd_opt {X : Type} (l : list X) : option X :=
match l with
| [] => None
| h :: t => Some h
end.
(** Once again, to force the implicit arguments to be explicit,
we can use [@] before the name of the function. *)
Check @hd_opt.
Example test_hd_opt1 : hd_opt [1;2] = Some 1.
Proof. reflexivity. Qed.
Example test_hd_opt2 : hd_opt [[1];[2]] = Some [1].
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################### *)
(** * Functions as Data *)
(* ###################################################### *)
(** ** Higher-Order Functions *)
(** Like many other modern programming languages -- including
all _functional languages_ (ML, Haskell, Scheme, etc.) -- Coq
treats functions as first-class citizens, allowing functions to be
passed as arguments to other functions, returned as results,
stored in data structures, etc.
Functions that manipulate other functions are often called
_higher-order_ functions. Here's a simple one: *)
Definition doit3times {X:Type} (f:X->X) (n:X) : X :=
f (f (f n)).
(** The argument [f] here is itself a function (from [X] to
[X]); the body of [doit3times] applies [f] three times to some
value [n]. *)
Check @doit3times.
(* ===> doit3times : forall X : Type, (X -> X) -> X -> X *)
Example test_doit3times: doit3times minustwo 9 = 3.
Proof. reflexivity. Qed.
Example test_doit3times': doit3times negb true = false.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Partial Application *)
(** In fact, the multiple-argument functions we have already
seen are also examples of passing functions as data. To see why,
recall the type of [plus]. *)
Check plus.
(* ==> nat -> nat -> nat *)
(** Each [->] in this expression is actually a _binary_ operator
on types. (This is the same as saying that Coq primitively
supports only one-argument functions -- do you see why?) This
operator is _right-associative_, so the type of [plus] is really a
shorthand for [nat -> (nat -> nat)] -- i.e., it can be read as
saying that "[plus] is a one-argument function that takes a [nat]
and returns a one-argument function that takes another [nat] and
returns a [nat]." In the examples above, we have always applied
[plus] to both of its arguments at once, but if we like we can
supply just the first. This is called _partial application_. *)
Definition plus3 := plus 3.
Check plus3.
Example test_plus3 : plus3 4 = 7.
Proof. reflexivity. Qed.
Example test_plus3' : doit3times plus3 0 = 9.
Proof. reflexivity. Qed.
Example test_plus3'' : doit3times (plus 3) 0 = 9.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Digression: Currying *)
(** **** Exercise: 2 stars, advanced (currying) *)
(** In Coq, a function [f : A -> B -> C] really has the type [A
-> (B -> C)]. That is, if you give [f] a value of type [A], it
will give you function [f' : B -> C]. If you then give [f'] a
value of type [B], it will return a value of type [C]. This
allows for partial application, as in [plus3]. Processing a list
of arguments with functions that return functions is called
_currying_, in honor of the logician Haskell Curry.
Conversely, we can reinterpret the type [A -> B -> C] as [(A *
B) -> C]. This is called _uncurrying_. With an uncurried binary
function, both arguments must be given at once as a pair; there is
no partial application. *)
(** We can define currying as follows: *)
Definition prod_curry {X Y Z : Type}
(f : X * Y -> Z) (x : X) (y : Y) : Z := f (x, y).
(** As an exercise, define its inverse, [prod_uncurry]. Then prove
the theorems below to show that the two are inverses. *)
Definition prod_uncurry {X Y Z : Type}
(f : X -> Y -> Z) (p : X * Y) : Z :=
match p with
| (x, y) => f x y
end.
(** (Thought exercise: before running these commands, can you
calculate the types of [prod_curry] and [prod_uncurry]?) *)
Check @prod_curry.
Check @prod_uncurry.
Theorem uncurry_curry : forall (X Y Z : Type) (f : X -> Y -> Z) x y,
prod_curry (prod_uncurry f) x y = f x y.
Proof.
intros.
unfold prod_curry.
unfold prod_uncurry.
reflexivity.
Qed.
Theorem curry_uncurry : forall (X Y Z : Type)
(f : (X * Y) -> Z) (p : X * Y),
prod_uncurry (prod_curry f) p = f p.
Proof.
intros.
destruct p.
reflexivity.
Qed.
(** [] *)
(* ###################################################### *)
(** ** Filter *)
(** Here is a useful higher-order function, which takes a list
of [X]s and a _predicate_ on [X] (a function from [X] to [bool])
and "filters" the list, returning a new list containing just those
elements for which the predicate returns [true]. *)
Fixpoint filter {X:Type} (test: X->bool) (l:list X)
: (list X) :=
match l with
| [] => []
| h :: t => if test h then h :: (filter test t)
else filter test t
end.
(** For example, if we apply [filter] to the predicate [evenb]
and a list of numbers [l], it returns a list containing just the
even members of [l]. *)
Example test_filter1: filter evenb [1;2;3;4] = [2;4].
Proof. reflexivity. Qed.
(** *** *)
Definition length_is_1 {X : Type} (l : list X) : bool :=
beq_nat (length l) 1.
Example test_filter2:
filter length_is_1
[ [1; 2]; [3]; [4]; [5;6;7]; []; [8] ]
= [ [3]; [4]; [8] ].
Proof. reflexivity. Qed.
(** *** *)
(** We can use [filter] to give a concise version of the
[countoddmembers] function from the [Lists] chapter. *)
Definition countoddmembers' (l:list nat) : nat :=
length (filter oddb l).
Example test_countoddmembers'1: countoddmembers' [1;0;3;1;4;5] = 4.
Proof. reflexivity. Qed.
Example test_countoddmembers'2: countoddmembers' [0;2;4] = 0.
Proof. reflexivity. Qed.
Example test_countoddmembers'3: countoddmembers' nil = 0.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Anonymous Functions *)
(** It is a little annoying to be forced to define the function
[length_is_1] and give it a name just to be able to pass it as an
argument to [filter], since we will probably never use it again.
Moreover, this is not an isolated example. When using
higher-order functions, we often want to pass as arguments
"one-off" functions that we will never use again; having to give
each of these functions a name would be tedious.
Fortunately, there is a better way. It is also possible to
construct a function "on the fly" without declaring it at the top
level or giving it a name; this is analogous to the notation we've
been using for writing down constant lists, natural numbers, and
so on. *)
Example test_anon_fun':
doit3times (fun n => n * n) 2 = 256.
Proof. reflexivity. Qed.
(** Here is the motivating example from before, rewritten to use
an anonymous function. *)
Example test_filter2':
filter (fun l => beq_nat (length l) 1)
[ [1; 2]; [3]; [4]; [5;6;7]; []; [8] ]
= [ [3]; [4]; [8] ].
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars (filter_even_gt7) *)
(** Use [filter] (instead of [Fixpoint]) to write a Coq function
[filter_even_gt7] that takes a list of natural numbers as input
and returns a list of just those that are even and greater than
7. *)
Definition filter_even_gt7 (l : list nat) : list nat :=
filter (fun n => andb (evenb n) (blt_nat 7 n)) l.
Example test_filter_even_gt7_1 :
filter_even_gt7 [1;2;6;9;10;3;12;8] = [10;12;8].
Proof. reflexivity. Qed.
Example test_filter_even_gt7_2 :
filter_even_gt7 [5;2;6;19;129] = [].
Proof. reflexivity. Qed.
(** [] *)
(** **** Exercise: 3 stars (partition) *)
(** Use [filter] to write a Coq function [partition]:
partition : forall X : Type,
(X -> bool) -> list X -> list X * list X
Given a set [X], a test function of type [X -> bool] and a [list
X], [partition] should return a pair of lists. The first member of
the pair is the sublist of the original list containing the
elements that satisfy the test, and the second is the sublist
containing those that fail the test. The order of elements in the
two sublists should be the same as their order in the original
list.
*)
Definition partition {X : Type} (test : X -> bool) (l : list X)
: list X * list X :=
(filter test l, filter (fun n => negb (test n)) l).
Example test_partition1: partition oddb [1;2;3;4;5] = ([1;3;5], [2;4]).
Proof. reflexivity. Qed.
Example test_partition2: partition (fun x => false) [5;9;0] = ([], [5;9;0]).
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################### *)
(** ** Map *)
(** Another handy higher-order function is called [map]. *)
Fixpoint map {X Y:Type} (f:X->Y) (l:list X)
: (list Y) :=
match l with
| [] => []
| h :: t => (f h) :: (map f t)
end.
(** *** *)
(** It takes a function [f] and a list [ l = [n1, n2, n3, ...] ]
and returns the list [ [f n1, f n2, f n3,...] ], where [f] has
been applied to each element of [l] in turn. For example: *)
Example test_map1: map (plus 3) [2;0;2] = [5;3;5].
Proof. reflexivity. Qed.
(** The element types of the input and output lists need not be
the same ([map] takes _two_ type arguments, [X] and [Y]). This
version of [map] can thus be applied to a list of numbers and a
function from numbers to booleans to yield a list of booleans: *)
Example test_map2: map oddb [2;1;2;5] = [false;true;false;true].
Proof. reflexivity. Qed.
(** It can even be applied to a list of numbers and
a function from numbers to _lists_ of booleans to
yield a list of lists of booleans: *)
Example test_map3:
map (fun n => [evenb n;oddb n]) [2;1;2;5]
= [[true;false];[false;true];[true;false];[false;true]].
Proof. reflexivity. Qed.
(** ** Map for options *)
(** **** Exercise: 3 stars (map_rev) *)
(** Show that [map] and [rev] commute. You may need to define an
auxiliary lemma. *)
Lemma snoc_map : forall (X Y : Type) (f : X -> Y) (l : list X) (x : X),
snoc (map f l) (f x) = map f (snoc l x).
Proof.
intros.
induction l.
Case "Base". simpl. reflexivity.
Case "Ind". simpl. rewrite IHl. reflexivity.
Qed.
Theorem map_rev : forall (X Y : Type) (f : X -> Y) (l : list X),
map f (rev l) = rev (map f l).
Proof.
intros.
induction l.
Case "Base". simpl. reflexivity.
Case "Ind".
simpl. rewrite <- IHl.
rewrite snoc_map.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars (flat_map) *)
(** The function [map] maps a [list X] to a [list Y] using a function
of type [X -> Y]. We can define a similar function, [flat_map],
which maps a [list X] to a [list Y] using a function [f] of type
[X -> list Y]. Your definition should work by 'flattening' the
results of [f], like so:
flat_map (fun n => [n;n+1;n+2]) [1;5;10]
= [1; 2; 3; 5; 6; 7; 10; 11; 12].
*)
Fixpoint flat_map {X Y:Type} (f:X -> list Y) (l:list X)
: (list Y) :=
match l with
| [] => []
| h :: t => (f h) ++ flat_map f t
end.
Example test_flat_map1:
flat_map (fun n => [n;n;n]) [1;5;4]
= [1; 1; 1; 5; 5; 5; 4; 4; 4].
Proof. reflexivity. Qed.
(** [] *)
(** Lists are not the only inductive type that we can write a
[map] function for. Here is the definition of [map] for the
[option] type: *)
Definition option_map {X Y : Type} (f : X -> Y) (xo : option X)
: option Y :=
match xo with
| None => None
| Some x => Some (f x)
end.
(** **** Exercise: 2 stars, optional (implicit_args) *)
(** The definitions and uses of [filter] and [map] use implicit
arguments in many places. Replace the curly braces around the
implicit arguments with parentheses, and then fill in explicit
type parameters where necessary and use Coq to check that you've
done so correctly. (This exercise is not to be turned in; it is
probably easiest to do it on a _copy_ of this file that you can
throw away afterwards.) [] *)
(* ###################################################### *)
(** ** Fold *)
(** An even more powerful higher-order function is called
[fold]. This function is the inspiration for the "[reduce]"
operation that lies at the heart of Google's map/reduce
distributed programming framework. *)
Fixpoint fold {X Y:Type} (f: X->Y->Y) (l:list X) (b:Y) : Y :=
match l with
| nil => b
| h :: t => f h (fold f t b)
end.
(** *** *)
(** Intuitively, the behavior of the [fold] operation is to
insert a given binary operator [f] between every pair of elements
in a given list. For example, [ fold plus [1;2;3;4] ] intuitively
means [1+2+3+4]. To make this precise, we also need a "starting
element" that serves as the initial second input to [f]. So, for
example,
fold plus [1;2;3;4] 0
yields
1 + (2 + (3 + (4 + 0))).
Here are some more examples:
*)
Check (fold andb).
(* ===> fold andb : list bool -> bool -> bool *)
Example fold_example1 : fold mult [1;2;3;4] 1 = 24.
Proof. reflexivity. Qed.
Example fold_example2 : fold andb [true;true;false;true] true = false.
Proof. reflexivity. Qed.
Example fold_example3 : fold app [[1];[];[2;3];[4]] [] = [1;2;3;4].
Proof. reflexivity. Qed.
(** **** Exercise: 1 star, advanced (fold_types_different) *)
(** Observe that the type of [fold] is parameterized by _two_ type
variables, [X] and [Y], and the parameter [f] is a binary operator
that takes an [X] and a [Y] and returns a [Y]. Can you think of a
situation where it would be useful for [X] and [Y] to be
different? *)
(* ###################################################### *)
(** ** Functions For Constructing Functions *)
(** Most of the higher-order functions we have talked about so
far take functions as _arguments_. Now let's look at some
examples involving _returning_ functions as the results of other
functions.
To begin, here is a function that takes a value [x] (drawn from
some type [X]) and returns a function from [nat] to [X] that
yields [x] whenever it is called, ignoring its [nat] argument. *)
Definition constfun {X: Type} (x: X) : nat->X :=
fun (k:nat) => x.
Definition ftrue := constfun true.
Example constfun_example1 : ftrue 0 = true.
Proof. reflexivity. Qed.
Example constfun_example2 : (constfun 5) 99 = 5.
Proof. reflexivity. Qed.
(** *** *)
(** Similarly, but a bit more interestingly, here is a function
that takes a function [f] from numbers to some type [X], a number
[k], and a value [x], and constructs a function that behaves
exactly like [f] except that, when called with the argument [k],
it returns [x]. *)
Definition override {X: Type} (f: nat->X) (k:nat) (x:X) : nat->X:=
fun (k':nat) => if beq_nat k k' then x else f k'.
(** For example, we can apply [override] twice to obtain a
function from numbers to booleans that returns [false] on [1] and
[3] and returns [true] on all other arguments. *)
Definition fmostlytrue := override (override ftrue 1 false) 3 false.
(** *** *)
Example override_example1 : fmostlytrue 0 = true.
Proof. reflexivity. Qed.
Example override_example2 : fmostlytrue 1 = false.
Proof. reflexivity. Qed.
Example override_example3 : fmostlytrue 2 = true.
Proof. reflexivity. Qed.
Example override_example4 : fmostlytrue 3 = false.
Proof. reflexivity. Qed.
(** *** *)
(** **** Exercise: 1 star (override_example) *)
(** Before starting to work on the following proof, make sure you
understand exactly what the theorem is saying and can paraphrase
it in your own words. The proof itself is straightforward. *)
Theorem override_example : forall (b:bool),
(override (constfun b) 3 true) 2 = b.
Proof.
intros. reflexivity.
Qed.
(** [] *)
(** We'll use function overriding heavily in parts of the rest of the
course, and we will end up needing to know quite a bit about its
properties. To prove these properties, though, we need to know
about a few more of Coq's tactics; developing these is the main
topic of the next chapter. For now, though, let's introduce just
one very useful tactic that will also help us with proving
properties of some of the other functions we have introduced in
this chapter. *)
(* ###################################################### *)
(* ###################################################### *)
(** * The [unfold] Tactic *)
(** Sometimes, a proof will get stuck because Coq doesn't
automatically expand a function call into its definition. (This
is a feature, not a bug: if Coq automatically expanded everything
possible, our proof goals would quickly become enormous -- hard to
read and slow for Coq to manipulate!) *)
Theorem unfold_example_bad : forall m n,
3 + n = m ->
plus3 n + 1 = m + 1.
Proof.
intros m n H.
(* At this point, we'd like to do [rewrite -> H], since
[plus3 n] is definitionally equal to [3 + n]. However,
Coq doesn't automatically expand [plus3 n] to its
definition. *)
Abort.
(** The [unfold] tactic can be used to explicitly replace a
defined name by the right-hand side of its definition. *)
Theorem unfold_example : forall m n,
3 + n = m ->
plus3 n + 1 = m + 1.
Proof.
intros m n H.
unfold plus3.
rewrite -> H.
reflexivity. Qed.
(** Now we can prove a first property of [override]: If we
override a function at some argument [k] and then look up [k], we
get back the overridden value. *)
Theorem override_eq : forall {X:Type} x k (f:nat->X),
(override f k x) k = x.
Proof.
intros X x k f.
unfold override.
rewrite <- beq_nat_refl.
reflexivity. Qed.
(** This proof was straightforward, but note that it requires
[unfold] to expand the definition of [override]. *)
(** **** Exercise: 2 stars (override_neq) *)
Theorem override_neq : forall (X:Type) x1 x2 k1 k2 (f : nat->X),
f k1 = x1 ->
beq_nat k2 k1 = false ->
(override f k2 x2) k1 = x1.
Proof.
intros.
unfold override.
rewrite H0.
rewrite H.
reflexivity.
Qed.
(** [] *)
(** As the inverse of [unfold], Coq also provides a tactic
[fold], which can be used to "unexpand" a definition. It is used
much less often. *)
(* ##################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 2 stars (fold_length) *)
(** Many common functions on lists can be implemented in terms of
[fold]. For example, here is an alternative definition of [length]: *)
Definition fold_length {X : Type} (l : list X) : nat :=
fold (fun _ n => S n) l 0.
Example test_fold_length1 : fold_length [4;7;0] = 3.
Proof. reflexivity. Qed.
(** Prove the correctness of [fold_length]. *)
Theorem fold_length_correct : forall X (l : list X),
fold_length l = length l.
Proof.
intros.
induction l.
Case "Empty". simpl. unfold fold_length. simpl. reflexivity.
Case "Ind".
simpl. rewrite <- IHl. unfold fold_length.
simpl. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars (fold_map) *)
(** We can also define [map] in terms of [fold]. Finish [fold_map]
below. *)
Definition fold_map {X Y:Type} (f : X -> Y) (l : list X) : list Y :=
fold (fun x t => (f x) :: t) l [].
(** Write down a theorem [fold_map_correct] in Coq stating that
[fold_map] is correct, and prove it. *)
Theorem fold_map_correct : forall (X Y : Type) (f : X -> Y) (l : list X),
fold_map f l = map f l.
Proof.
intros.
induction l.
Case "Base". simpl. unfold fold_map. simpl. reflexivity.
Case "Ind.". simpl. rewrite <- IHl. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars, advanced (index_informal) *)
(** Recall the definition of the [index] function:
Fixpoint index {X : Type} (n : nat) (l : list X) : option X :=
match l with
| [] => None
| a :: l' => if beq_nat n O then Some a else index (pred n) l'
end.
Write an informal proof of the following theorem:
forall X n l, length l = n -> @index X n l = None.
(* FILL IN HERE *)
*)
(** [] *)
(** **** Exercise: 4 stars, advanced (church_numerals) *)
Module Church.
(** In this exercise, we will explore an alternative way of defining
natural numbers, using the so-called _Church numerals_, named
after mathematician Alonzo Church. We can represent a natural
number [n] as a function that takes a function [f] as a parameter
and returns [f] iterated [n] times. More formally, *)
Definition nat := forall X : Type, (X -> X) -> X -> X.
(** Let's see how to write some numbers with this notation. Any
function [f] iterated once shouldn't change. Thus, *)
Definition one : nat :=
fun (X : Type) (f : X -> X) (x : X) => f x.
(** [two] should apply [f] twice to its argument: *)
Definition two : nat :=
fun (X : Type) (f : X -> X) (x : X) => f (f x).
(** [zero] is somewhat trickier: how can we apply a function zero
times? The answer is simple: just leave the argument untouched. *)
Definition zero : nat :=
fun (X : Type) (f : X -> X) (x : X) => x.
(** More generally, a number [n] will be written as [fun X f x => f (f
... (f x) ...)], with [n] occurrences of [f]. Notice in particular
how the [doit3times] function we've defined previously is actually
just the representation of [3]. *)
Definition three : nat := @doit3times.
(** Complete the definitions of the following functions. Make sure
that the corresponding unit tests pass by proving them with
[reflexivity]. *)
(** Successor of a natural number *)
Definition succ (n : nat) : nat :=
fun (X : Type) (f : X -> X) (x : X) => f (n X f x).
Example succ_1 : succ zero = one.
Proof. reflexivity. Qed.
Example succ_2 : succ one = two.
Proof. reflexivity. Qed.
Example succ_3 : succ two = three.
Proof. reflexivity. Qed.
(** Addition of two natural numbers *)
Definition plus (n m : nat) : nat :=
fun (X : Type) (f : X -> X) (x : X) => m X f (n X f x).
Example plus_1 : plus zero one = one.
Proof. reflexivity. Qed.
Example plus_2 : plus two three = plus three two.
Proof. reflexivity. Qed.
Example plus_3 :
plus (plus two two) three = plus one (plus three three).
Proof. reflexivity. Qed.
(** Multiplication *)
Definition mult (n m : nat) : nat :=
fun (X : Type) (f : X -> X) (x : X) => m X (n X f) x.
Example mult_1 : mult one one = one.
Proof. reflexivity. Qed.
Example mult_2 : mult zero (plus three three) = zero.
Proof. reflexivity. Qed.
Example mult_3 : mult two three = plus three three.
Proof. reflexivity. Qed.
(** Exponentiation *)
(** Hint: Polymorphism plays a crucial role here. However, choosing
the right type to iterate over can be tricky. If you hit a
"Universe inconsistency" error, try iterating over a different
type: [nat] itself is usually problematic. *)
(**
Definition exp (n m : nat) : nat :=
(* FILL IN HERE *) Admitted.
Example exp_1 : exp two two = plus two two.
Proof. (* FILL IN HERE *) Admitted.
Example exp_2 : exp three two = plus (mult two (mult two two)) one.
Proof. (* FILL IN HERE *) Admitted.
Example exp_3 : exp three zero = one.
Proof. (* FILL IN HERE *) Admitted.
**)
End Church.
(** [] *)
(** $Date: 2014-12-31 11:17:56 -0500 (Wed, 31 Dec 2014) $ *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND2B_1_V
`define SKY130_FD_SC_HS__NAND2B_1_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog wrapper for nand2b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nand2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nand2b_1 (
Y ,
A_N ,
B ,
VPWR,
VGND
);
output Y ;
input A_N ;
input B ;
input VPWR;
input VGND;
sky130_fd_sc_hs__nand2b base (
.Y(Y),
.A_N(A_N),
.B(B),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nand2b_1 (
Y ,
A_N,
B
);
output Y ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__nand2b base (
.Y(Y),
.A_N(A_N),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND2B_1_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module convolve_kernel_fbkb
#(parameter
ID = 0,
NUM_STAGE = 9,
din0_WIDTH = 32,
din1_WIDTH = 32,
dout_WIDTH = 32
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [31:0] a_tdata;
wire b_tvalid;
wire [31:0] b_tdata;
wire r_tvalid;
wire [31:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
convolve_kernel_ap_fadd_7_full_dsp_32 convolve_kernel_ap_fadd_7_full_dsp_32_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
endmodule
|
//-----------------------------------------------------
// Design Name : hw2_B
// File Name : hw2_B.v
// Function : This program designs a Stream Filter.
// Coder : hydai
//-----------------------------------------------------
`timescale 1 ns/1 ns
module hw2_B (
input in,
input clk,
input rst_n,
output reg out
);
reg [1:0]state, nextState;
reg nextOut;
parameter S0 = 0;
parameter S1 = 1;
parameter S2 = 2;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
out <= 0;
state <= 0;
end else begin
state <= nextState;
out <= nextOut;
end // end of if-else block
end // end of always
always @(state or in) begin
case (state)
S0: begin // previous input is 0
if (in == 0) begin // 0 -> 0 => 0
nextState <= S0;
end else begin // 0 -> 1 => 0
nextState <= S1;
end
end
S1: begin // previous input is 1
if (in == 0) begin // 1 -> 0 => 1
nextState <= S0;
end else begin // 1 -> 1 => 0
nextState <= S2;
end
end
S2: begin
if (in == 0) begin // 1 -> 1 -> 0 => 1
nextState <= S0;
end else begin // 1 -> 1 -> 1 => 1
nextState <= S2;
end
end
endcase
end
always @(state or in) begin
case (state)
S0: begin // previous input is 0
nextOut <= 0;
end
S1: begin // previous input is 1
if (in == 0) begin // 1 -> 0 => 1
nextOut <= 1;
end else begin // 1 -> 1 => 0
nextOut <= 0;
end
end
S2: begin
nextOut <= 1;
end
endcase
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
out <= 0;
end else begin
out <= nextOut;
end // end of if-else block
end // end of always
endmodule // endmodule of hw2_B
|
module i2c_control (
input res,
input clk,
input ioclk,
input write_req,
input delete_req,
input [7:0] inbyte,
output i2c_clk,
inout i2c_sda
);
parameter LCD_ADDR = 8'h7c;
parameter TRANSMIT = 12'h4_00;
parameter START = 12'h2_00;
parameter END = 12'h1_00;
parameter WAITSTABLE = 3'h0,
LCDSETUP = 3'h1,
LCDSETUP_WAIT = 3'h2,
CAMERA_SETUP = 3'h3,
CAMERA_SETUP_WAIT = 3'h4,
WRITE_CHAR = 3'h5;
parameter CAMERA_MAX = 8'h71;
reg [2:0] state;
reg [7:0] programcount;
reg [17:0] waitcount;
wire [7:0] byte;
reg [11:0] inst;
wire write;
wire send;
wire start;
wire endcomm;
wire done;
assign write = inst[11];
assign send = inst[10];
assign start = inst[9];
assign endcomm = inst[8];
assign byte = inst[7:0];
wire [7:0] dataindex;
reg [7:0] inbyte_buf;
reg delete_buf;
reg write_buf;
assign dataindex = programcount[7:3];
always @(posedge ioclk or posedge res)
begin
if (res) begin
programcount <= 8'h00;
waitcount <= 18'h00000;
state <= WAITSTABLE;
delete_buf <= 0;
write_buf <= 0;
end else begin
case (state)
WAITSTABLE: begin
waitcount <= waitcount + 1'b1;
//if (waitcount == 18'h1_0000) begin
if (waitcount == 18'h0_0100) begin
state <= CAMERA_SETUP;
end
end
CAMERA_SETUP: begin
inst <= cameramem(programcount[2:0], addr_dict(dataindex), data_dict(dataindex));
waitcount <= 18'h00000;
if (dataindex != CAMERA_MAX) begin
state <= CAMERA_SETUP_WAIT;
programcount <= programcount + 1'b1;
end else begin
state <= LCDSETUP;
programcount <= 8'h0;
end
end
CAMERA_SETUP_WAIT: begin
inst <= 12'h0_00;
waitcount <= waitcount + 1'b1;
if (done && waitcount > 18'h0_0018) begin
state <= CAMERA_SETUP;
end
end
LCDSETUP: begin
inst <= instmem(programcount, inbyte_buf);
waitcount <= 18'h00000;
state <= instmem(programcount, inbyte_buf) ? LCDSETUP_WAIT : WRITE_CHAR;
programcount <= programcount + 1'b1;
end
LCDSETUP_WAIT: begin
inst <= 12'h0_00;
waitcount <= waitcount + 1'b1;
if ((programcount != 8'h30) && done && waitcount > 18'h0_0018) begin
state <= LCDSETUP;
end
//if ((programcount == 8'h30) && (waitcount == 18'h3_ffff)) begin
if ((programcount == 8'h30) && (waitcount == 18'h0_0800)) begin
state <= LCDSETUP;
end
end
WRITE_CHAR: begin
if (write_req ^ write_buf) begin
write_buf <= write_req;
programcount <= 8'h40;
state <= LCDSETUP;
end else if (delete_req ^ delete_buf) begin
delete_buf <= delete_req;
programcount <= 8'h60;
state <= LCDSETUP;
end
end
endcase
end
end
/*
* Instractions:
* 1xxx = set data
* 01xx = transmit data
* 001x = make start condition
* 0001 = make end condition
* 0000 = stop
*/
function [11:0] instmem;
input [7:0] pc;
input [7:0] data;
case (pc)
8'h0: instmem = START;
8'h1: instmem = {4'h8, LCD_ADDR};
8'h2: instmem = TRANSMIT;
8'h3: instmem = {4'h8, 8'h80};
8'h4: instmem = TRANSMIT;
8'h5: instmem = {4'h8, 8'h38};
8'h6: instmem = TRANSMIT;
8'h7: instmem = END;
8'h8: instmem = START;
8'h9: instmem = {4'h8, LCD_ADDR};
8'ha: instmem = TRANSMIT;
8'hb: instmem = {4'h8, 8'h80};
8'hc: instmem = TRANSMIT;
8'hd: instmem = {4'h8, 8'h39};
8'he: instmem = TRANSMIT;
8'hf: instmem = END;
8'h10: instmem = START;
8'h11: instmem = {4'h8, LCD_ADDR};
8'h12: instmem = TRANSMIT;
8'h13: instmem = {4'h8, 8'h80};
8'h14: instmem = TRANSMIT;
8'h15: instmem = {4'h8, 8'h14};
8'h16: instmem = TRANSMIT;
8'h17: instmem = END;
8'h18: instmem = START;
8'h19: instmem = {4'h8, LCD_ADDR};
8'h1a: instmem = TRANSMIT;
8'h1b: instmem = {4'h8, 8'h80};
8'h1c: instmem = TRANSMIT;
8'h1d: instmem = {4'h8, 8'h74};
8'h1e: instmem = TRANSMIT;
8'h1f: instmem = END;
8'h20: instmem = START;
8'h21: instmem = {4'h8, LCD_ADDR};
8'h22: instmem = TRANSMIT;
8'h23: instmem = {4'h8, 8'h80};
8'h24: instmem = TRANSMIT;
8'h25: instmem = {4'h8, 8'h56};
8'h26: instmem = TRANSMIT;
8'h27: instmem = END;
8'h28: instmem = START;
8'h29: instmem = {4'h8, LCD_ADDR};
8'h2a: instmem = TRANSMIT;
8'h2b: instmem = {4'h8, 8'h80};
8'h2c: instmem = TRANSMIT;
8'h2d: instmem = {4'h8, 8'h6c};
8'h2e: instmem = TRANSMIT;
8'h2f: instmem = END;
//wait here
//
8'h30: instmem = START;
8'h31: instmem = {4'h8, LCD_ADDR};
8'h32: instmem = TRANSMIT;
8'h33: instmem = {4'h8, 8'h80};
8'h34: instmem = TRANSMIT;
8'h35: instmem = {4'h8, 8'h38};
8'h36: instmem = TRANSMIT;
8'h37: instmem = END;
8'h38: instmem = START;
8'h39: instmem = {4'h8, LCD_ADDR};
8'h3a: instmem = TRANSMIT;
8'h3b: instmem = {4'h8, 8'h80};
8'h3c: instmem = TRANSMIT;
8'h3d: instmem = {4'h8, 8'h0c};
8'h3e: instmem = TRANSMIT;
8'h3f: instmem = END;
8'h40: instmem = START;
8'h41: instmem = {4'h8, LCD_ADDR};
8'h42: instmem = TRANSMIT;
8'h43: instmem = {4'h8, 8'h80};
8'h44: instmem = TRANSMIT;
8'h45: instmem = {4'h8, 8'h01};
8'h46: instmem = TRANSMIT;
8'h47: instmem = END;
8'h48: instmem = START;
8'h49: instmem = {4'h8, LCD_ADDR};
8'h4a: instmem = TRANSMIT;
8'h4b: instmem = {4'h8, 8'hc0};
8'h4c: instmem = TRANSMIT;
8'h4d: instmem = {4'h8, data};
8'h4e: instmem = TRANSMIT;
8'h53: instmem = END;
8'h54: instmem = 0;
8'h60: instmem = START;
8'h61: instmem = {4'h8, LCD_ADDR};
8'h62: instmem = TRANSMIT;
8'h63: instmem = {4'h8, 8'h80};
8'h64: instmem = TRANSMIT;
8'h65: instmem = {4'h8, 8'h01};
8'h66: instmem = TRANSMIT;
8'h67: instmem = END;
8'h68: instmem = 0;
default:
instmem = 0;
endcase
endfunction
parameter CAM_ADDR = 8'h42;
function [11:0] cameramem;
input [2:0] pc;
input [7:0] addr;
input [7:0] data;
case (pc)
3'h0: cameramem = START;
3'h1: cameramem = {4'h8, CAM_ADDR};
3'h2: cameramem = TRANSMIT;
3'h3: cameramem = {4'h8, addr};
3'h4: cameramem = TRANSMIT;
3'h5: cameramem = {4'h8, data};
3'h6: cameramem = TRANSMIT;
3'h7: cameramem = END;
endcase
endfunction
i2c_master im0 (
.clk(clk),
.write(write),
.send(send),
.start(start),
.endcomm(endcomm),
.ioclk(ioclk),
.byte(byte),
.i2c_clk(i2c_clk),
.i2c_sda(i2c_sda),
.done(done)
);
function [7:0] addr_dict;
input [7:0] index;
case (index)
8'h00: addr_dict = 8'h01;
8'h01: addr_dict = 8'h02;
8'h02: addr_dict = 8'h03;
8'h03: addr_dict = 8'h0c;
8'h04: addr_dict = 8'h0e;
8'h05: addr_dict = 8'h0f;
8'h06: addr_dict = 8'h15;
8'h07: addr_dict = 8'h16;
8'h08: addr_dict = 8'h17;
8'h09: addr_dict = 8'h18;
8'h0a: addr_dict = 8'h19;
8'h0b: addr_dict = 8'h1a;
8'h0c: addr_dict = 8'h1e;
8'h0d: addr_dict = 8'h21;
8'h0e: addr_dict = 8'h22;
8'h0f: addr_dict = 8'h29;
8'h10: addr_dict = 8'h32;
8'h11: addr_dict = 8'h33;
8'h12: addr_dict = 8'h34;
8'h13: addr_dict = 8'h35;
8'h14: addr_dict = 8'h37;
8'h15: addr_dict = 8'h38;
8'h16: addr_dict = 8'h39;
8'h17: addr_dict = 8'h3b;
8'h18: addr_dict = 8'h3c;
8'h19: addr_dict = 8'h3d;
8'h1a: addr_dict = 8'h3e;
8'h1b: addr_dict = 8'h3f;
8'h1c: addr_dict = 8'h41;
8'h1d: addr_dict = 8'h41; //????
8'h1e: addr_dict = 8'h43;
8'h1f: addr_dict = 8'h44;
8'h20: addr_dict = 8'h45;
8'h21: addr_dict = 8'h46;
8'h22: addr_dict = 8'h47;
8'h23: addr_dict = 8'h48;
8'h24: addr_dict = 8'h4b;
8'h25: addr_dict = 8'h4c;
8'h26: addr_dict = 8'h4d;
8'h27: addr_dict = 8'h4e;
8'h28: addr_dict = 8'h4f;
8'h29: addr_dict = 8'h50;
8'h2a: addr_dict = 8'h51;
8'h2b: addr_dict = 8'h52;
8'h2c: addr_dict = 8'h53;
8'h2d: addr_dict = 8'h54;
8'h2e: addr_dict = 8'h56;
8'h2f: addr_dict = 8'h58;
8'h30: addr_dict = 8'h59;
8'h31: addr_dict = 8'h5a;
8'h32: addr_dict = 8'h5b;
8'h33: addr_dict = 8'h5c;
8'h34: addr_dict = 8'h5d;
8'h35: addr_dict = 8'h5e;
8'h36: addr_dict = 8'h69;
8'h37: addr_dict = 8'h6a;
8'h38: addr_dict = 8'h6b;
8'h39: addr_dict = 8'h6c;
8'h3a: addr_dict = 8'h6d;
8'h3b: addr_dict = 8'h6e;
8'h3c: addr_dict = 8'h6f;
8'h3d: addr_dict = 8'h70;
8'h3e: addr_dict = 8'h71;
8'h3f: addr_dict = 8'h72;
8'h40: addr_dict = 8'h73;
8'h41: addr_dict = 8'h74;
8'h42: addr_dict = 8'h75;
8'h43: addr_dict = 8'h76;
8'h44: addr_dict = 8'h77;
8'h45: addr_dict = 8'h78;
8'h46: addr_dict = 8'h79;
8'h47: addr_dict = 8'h8d;
8'h48: addr_dict = 8'h8e;
8'h49: addr_dict = 8'h8f;
8'h4a: addr_dict = 8'h90;
8'h4b: addr_dict = 8'h91;
8'h4c: addr_dict = 8'h96;
8'h4d: addr_dict = 8'h96;
8'h4e: addr_dict = 8'h97;
8'h4f: addr_dict = 8'h98;
8'h50: addr_dict = 8'h99;
8'h51: addr_dict = 8'h9a;
8'h52: addr_dict = 8'h9a;
8'h53: addr_dict = 8'h9b;
8'h54: addr_dict = 8'h9c;
8'h55: addr_dict = 8'h9d;
8'h56: addr_dict = 8'h9e;
8'h57: addr_dict = 8'ha2;
8'h58: addr_dict = 8'ha4;
8'h59: addr_dict = 8'hb0;
8'h5a: addr_dict = 8'hb1;
8'h5b: addr_dict = 8'hb2;
8'h5c: addr_dict = 8'hb3;
8'h5d: addr_dict = 8'hb8;
8'h5e: addr_dict = 8'hc8;
8'h5f: addr_dict = 8'hc9;
8'h60: addr_dict = 8'h12;
8'h61: addr_dict = 8'h40;
endcase
endfunction
function [7:0] data_dict;
input [7:0] index;
case (index)
8'h00: data_dict = 8'h40;
8'h01: data_dict = 8'h60;
8'h02: data_dict = 8'h0a;
8'h03: data_dict = 8'h00;
8'h04: data_dict = 8'h61;
8'h05: data_dict = 8'h4b;
8'h06: data_dict = 8'h00;
8'h07: data_dict = 8'h02;
8'h08: data_dict = 8'h13;
8'h09: data_dict = 8'h01;
8'h0a: data_dict = 8'h02;
8'h0b: data_dict = 8'h7a;
8'h0c: data_dict = 8'h07;
8'h0d: data_dict = 8'h02;
8'h0e: data_dict = 8'h91;
8'h0f: data_dict = 8'h07;
8'h10: data_dict = 8'hb6;
8'h11: data_dict = 8'h0b;
8'h12: data_dict = 8'h11;
8'h13: data_dict = 8'h0b;
8'h14: data_dict = 8'h1d;
8'h15: data_dict = 8'h71;
8'h16: data_dict = 8'h2a;
8'h17: data_dict = 8'h12;
8'h18: data_dict = 8'h78;
8'h19: data_dict = 8'hc3;
8'h1a: data_dict = 8'h00;
8'h1b: data_dict = 8'h00;
8'h1c: data_dict = 8'h08;
8'h1d: data_dict = 8'h38; //????
8'h1e: data_dict = 8'h0a;
8'h1f: data_dict = 8'hf0;
8'h20: data_dict = 8'h34;
8'h21: data_dict = 8'h58;
8'h22: data_dict = 8'h28;
8'h23: data_dict = 8'h3a;
8'h24: data_dict = 8'h09;
8'h25: data_dict = 8'h00;
8'h26: data_dict = 8'h40;
8'h27: data_dict = 8'h20;
8'h28: data_dict = 8'h80;
8'h29: data_dict = 8'h80;
8'h2a: data_dict = 8'h00;
8'h2b: data_dict = 8'h22;
8'h2c: data_dict = 8'h5e;
8'h2d: data_dict = 8'h80;
8'h2e: data_dict = 8'h40;
8'h2f: data_dict = 8'h9e;
8'h30: data_dict = 8'h88;
8'h31: data_dict = 8'h88;
8'h32: data_dict = 8'h44;
8'h33: data_dict = 8'h67;
8'h34: data_dict = 8'h49;
8'h35: data_dict = 8'h0e;
8'h36: data_dict = 8'h00;
8'h37: data_dict = 8'h40;
8'h38: data_dict = 8'h0a;
8'h39: data_dict = 8'h0a;
8'h3a: data_dict = 8'h55;
8'h3b: data_dict = 8'h11;
8'h3c: data_dict = 8'h9f;
8'h3d: data_dict = 8'h3a;
8'h3e: data_dict = 8'h35;
8'h3f: data_dict = 8'h11;
8'h40: data_dict = 8'hf0;
8'h41: data_dict = 8'h10;
8'h42: data_dict = 8'h05;
8'h43: data_dict = 8'he1;
8'h44: data_dict = 8'h01;
8'h45: data_dict = 8'h04;
8'h46: data_dict = 8'h01;
8'h47: data_dict = 8'h4f;
8'h48: data_dict = 8'h00;
8'h49: data_dict = 8'h00;
8'h4a: data_dict = 8'h00;
8'h4b: data_dict = 8'h00;
8'h4c: data_dict = 8'h00;
8'h4d: data_dict = 8'h00;
8'h4e: data_dict = 8'h30;
8'h4f: data_dict = 8'h20;
8'h50: data_dict = 8'h30;
8'h51: data_dict = 8'h00;
8'h52: data_dict = 8'h84;
8'h53: data_dict = 8'h29;
8'h54: data_dict = 8'h03;
8'h55: data_dict = 8'h4c;
8'h56: data_dict = 8'h3f;
8'h57: data_dict = 8'h02;
8'h58: data_dict = 8'h88;
8'h59: data_dict = 8'h84;
8'h5a: data_dict = 8'h0c;
8'h5b: data_dict = 8'h0e;
8'h5c: data_dict = 8'h82;
8'h5d: data_dict = 8'h0a;
8'h5e: data_dict = 8'hf0;
8'h5f: data_dict = 8'h60;
8'h60: data_dict = 8'h04;
8'h61: data_dict = 8'hf0;
endcase
endfunction
endmodule
module i2c_master (
input clk,
input write,
input send,
input start,
input endcomm,
input ioclk,
input [7:0] byte,
output reg i2c_clk,
inout i2c_sda,
output reg done
);
reg sda_out;
reg sda_oe;
assign i2c_sda = sda_oe ? sda_out : 1'bz;
reg [3:0] sendcount;
reg [7:0] byte_buf;
reg [1:0] phase;
reg sending;
reg starting;
reg ending;
reg ioclk_now;
reg ioclk_prev;
always @(posedge ioclk)
begin
if (write) begin
byte_buf <= byte;
end
if (send) begin
sda_oe <= 1'b1;
sending <= 1'b1;
starting <= 1'b0;
ending <= 1'b0;
phase <= 1'b0;
done <= 0;
sendcount <= 4'h0;
end else if (start) begin
sda_oe <= 1'b1;
starting <= 1'b1;
sending <= 1'b0;
ending <= 1'b0;
phase <= 1'b0;
done <= 0;
i2c_clk <= 1'b1;
end else if (endcomm) begin
starting <= 1'b0;
sending <= 1'b0;
ending <= 1'b1;
phase <= 1'b0;
done <= 0;
end
if (sending) begin
case (phase)
0:
begin
i2c_clk <= 1'b0;
phase <= 2'h1;
end
1:
begin
if (sendcount == 8) begin
sda_oe <= 1'b0;
end
if (sendcount == 9) begin
sending <= 1'b0;
done <= 1;
sda_oe <= 1'b1;
phase <= 2'h0;
end
sda_out <= byte_buf[7];
byte_buf[7:1] <= byte_buf[6:0];
phase <= 2'h2;
end
2:
begin
i2c_clk <= 1'b1;
phase <= 2'h3;
end
3:
begin
phase <= 2'h0;
sendcount <= sendcount + 1'b1;
end
endcase
end else if (starting) begin
case (phase)
0:
begin
i2c_clk <= 1'b1;
sda_out <= 1'b1;
phase <= 2'h1;
end
1:
begin
sda_out <= 1'b0;
starting <= 1'b0;
phase <= 2'b0;
done <= 1'b1;
end
endcase
end else if (ending) begin
case (phase)
0:
begin
phase <= 2'h1;
i2c_clk <= 1'b0;
phase <= 2'h1;
end
1:
begin
sda_oe <= 1'b1;
sda_out <= 1'b0;
phase <= 2'h2;
end
2:
begin
i2c_clk <= 1'b1;
phase <= 2'h3;
end
3:
begin
sda_out <= 1'b1;
ending <= 1'b0;
phase <= 2'b0;
done <= 1'b1;
end
endcase
end
end
endmodule
|
module usb_sequencer
(
input clk,
input reset_n,
input rxf_n,
input txe_n,
input panel_select_request,
input [15:0] panel_switches,
output reg [7:0] data_out,
output rd_n,
output wr_n,
output data_out_enable,
output command_write_enable,
output clear_psr,
output [4:0] state_out
);
reg [4:0] state, next_state, output_bits;
assign state_out = state;
assign rd_n = output_bits[4];
assign wr_n = output_bits[3];
assign data_out_enable = output_bits[2];
assign command_write_enable = output_bits[1];
assign clear_psr = output_bits[0];
// Labeled states
localparam [4:0]
start_read = 5'd0,
end_read = 5'd7,
start_write = 5'd8,
write_p1 = 5'd13,
write_p2 = 5'd18,
write_p3 = 5'd23,
end_write = 5'd28;
// State register
always @(posedge clk, negedge reset_n)
if (!reset_n)
state <= start_read;
else
state <= next_state;
// Next state logic
always @(*)
case (state)
start_read:
if (panel_select_request)
next_state = start_write;
else
if (rxf_n)
next_state = start_read;
else
next_state = state + 1'b1;
end_read:
if (panel_select_request)
next_state = start_write;
else
next_state = start_read;
start_write:
if (txe_n)
next_state = start_write;
else
next_state = state + 1'b1;
write_p1:
if (txe_n)
next_state = write_p1;
else
next_state = state + 1'b1;
write_p2:
if (txe_n)
next_state = write_p2;
else
next_state = state + 1'b1;
write_p3:
if (txe_n)
next_state = write_p3;
else
next_state = state + 1'b1;
end_write:
next_state = start_read;
default:
next_state = state + 1'b1;
endcase // case (state)
// Output logic
always @(*)
if (!reset_n)
begin
data_out = 8'hzz;
output_bits = 4'b1100;
end
else
case (state)
0: // start_read
begin
data_out = 8'hzz;
output_bits = 5'b11000;
end
1: //
begin
data_out = 8'hzz;
output_bits = 5'b01000;
end
2: //
begin
data_out = 8'hzz;
output_bits = 5'b01000;
end
3: //
begin
data_out = 8'hzz;
output_bits = 5'b01000;
end
4: //
begin
data_out = 8'hzz;
output_bits = 5'b11010;
end
5: //
begin
data_out = 8'hzz;
output_bits = 5'b11000;
end
6: //
begin
data_out = 8'hzz;
output_bits = 5'b11000;
end
7: // end_read
begin
data_out = 8'hzz;
output_bits = 5'b11000;
end
8: // start_write
begin
data_out = 8'hzz;
output_bits = 5'b11000;
end
9: //
begin
data_out = {4'h1, panel_switches[3:0]};
output_bits = 5'b11100;
end
10: //
begin
data_out = {4'h1, panel_switches[3:0]};
output_bits = 5'b10100;
end
11: //
begin
data_out = {4'h1, panel_switches[3:0]};
output_bits = 5'b10100;
end
12: //
begin
data_out = {4'h1, panel_switches[3:0]};
output_bits = 5'b11100;
end
13: // write_p1
begin
data_out = {4'h1, panel_switches[3:0]};
output_bits = 5'b11100;
end
14: //
begin
data_out = {4'h2, panel_switches[7:4]};
output_bits = 5'b11100;
end
15: //
begin
data_out = {4'h2, panel_switches[7:4]};
output_bits = 5'b10100;
end
16: //
begin
data_out = {4'h2, panel_switches[7:4]};
output_bits = 5'b10100;
end
17: //
begin
data_out = {4'h2, panel_switches[7:4]};
output_bits = 5'b11100;
end
18: // write_p2
begin
data_out = {4'h2, panel_switches[7:4]};
output_bits = 5'b11100;
end
19: //
begin
data_out = {4'h3, panel_switches[11:8]};
output_bits = 5'b11100;
end
20: //
begin
data_out = {4'h3, panel_switches[11:8]};
output_bits = 5'b10100;
end
21: //
begin
data_out = {4'h3, panel_switches[11:8]};
output_bits = 5'b10100;
end
22: //
begin
data_out = {4'h3, panel_switches[11:8]};
output_bits = 5'b11100;
end
23: // write_p3
begin
data_out = {4'h3, panel_switches[11:8]};
output_bits = 5'b11100;
end
24: //
begin
data_out = {4'h4, panel_switches[15:12]};
output_bits = 5'b11100;
end
25: //
begin
data_out = {4'h4, panel_switches[15:12]};
output_bits = 5'b10100;
end
26: //
begin
data_out = {4'h4, panel_switches[15:12]};
output_bits = 5'b10100;
end
27: //
begin
data_out = {4'h4, panel_switches[15:12]};
output_bits = 5'b11101;
end
28: // end_write
begin
data_out = {4'h4, panel_switches[15:12]};
output_bits = 5'b11100;
end
default: // default
begin
data_out = 8'hzz;
output_bits = 5'b11000;
end
endcase // case (state)
endmodule // usb_sequencer
|
// ddr3_s4_uniphy_example_if0_c0.v
// This file was auto-generated from alt_mem_if_nextgen_ddr3_controller_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using SOPC Builder version 11.0sp1 208 at 2011.09.28.12:48:49
`timescale 1 ps / 1 ps
module ddr3_s4_uniphy_example_if0_c0 (
input wire afi_reset_n, // afi_reset.reset_n
input wire afi_clk, // afi_clk.clk
input wire afi_half_clk, // afi_half_clk.clk
output wire local_init_done, // status.local_init_done
output wire local_cal_success, // .local_cal_success
output wire local_cal_fail, // .local_cal_fail
output wire [25:0] afi_addr, // afi.afi_addr
output wire [5:0] afi_ba, // .afi_ba
output wire [1:0] afi_cke, // .afi_cke
output wire [1:0] afi_cs_n, // .afi_cs_n
output wire [1:0] afi_ras_n, // .afi_ras_n
output wire [1:0] afi_we_n, // .afi_we_n
output wire [1:0] afi_cas_n, // .afi_cas_n
output wire [1:0] afi_rst_n, // .afi_rst_n
output wire [1:0] afi_odt, // .afi_odt
output wire [3:0] afi_dqs_burst, // .afi_dqs_burst
output wire [3:0] afi_wdata_valid, // .afi_wdata_valid
output wire [63:0] afi_wdata, // .afi_wdata
output wire [7:0] afi_dm, // .afi_dm
input wire [63:0] afi_rdata, // .afi_rdata
output wire [1:0] afi_rdata_en, // .afi_rdata_en
output wire [1:0] afi_rdata_en_full, // .afi_rdata_en_full
input wire [1:0] afi_rdata_valid, // .afi_rdata_valid
input wire afi_cal_success, // .afi_cal_success
input wire afi_cal_fail, // .afi_cal_fail
output wire afi_cal_req, // .afi_cal_req
input wire [5:0] afi_wlat, // .afi_wlat
input wire [5:0] afi_rlat, // .afi_rlat
output wire local_powerdn_ack, // local_powerdown.local_powerdn_ack
input wire local_powerdn_req, // .local_powerdn_req
output wire avl_ready, // avl.waitrequest_n
input wire avl_burstbegin, // .beginbursttransfer
input wire [23:0] avl_addr, // .address
output wire avl_rdata_valid, // .readdatavalid
output wire [63:0] avl_rdata, // .readdata
input wire [63:0] avl_wdata, // .writedata
input wire [7:0] avl_be, // .byteenable
input wire avl_read_req, // .read
input wire avl_write_req, // .write
input wire [2:0] avl_size // .burstcount
);
wire a0_native_st_itf_wr_data_begin; // a0:itf_wr_data_begin -> ng0:itf_wr_data_begin
wire a0_native_st_itf_rd_data_ready; // a0:itf_rd_data_ready -> ng0:itf_rd_data_ready
wire [63:0] a0_native_st_itf_wr_data; // a0:itf_wr_data -> ng0:itf_wr_data
wire ng0_native_st_itf_rd_data_error; // ng0:itf_rd_data_error -> a0:itf_rd_data_error
wire ng0_native_st_itf_rd_data_begin; // ng0:itf_rd_data_begin -> a0:itf_rd_data_begin
wire [7:0] a0_native_st_itf_wr_data_id; // a0:itf_wr_data_id -> ng0:itf_wr_data_id
wire ng0_native_st_itf_cmd_ready; // ng0:itf_cmd_ready -> a0:itf_cmd_ready
wire a0_native_st_itf_wr_data_last; // a0:itf_wr_data_last -> ng0:itf_wr_data_last
wire [7:0] a0_native_st_itf_wr_data_byte_en; // a0:itf_wr_data_byte_en -> ng0:itf_wr_data_byte_en
wire [23:0] a0_native_st_itf_cmd_address; // a0:itf_cmd_address -> ng0:itf_cmd_address
wire a0_native_st_itf_cmd_valid; // a0:itf_cmd_valid -> ng0:itf_cmd_valid
wire a0_native_st_itf_wr_data_valid; // a0:itf_wr_data_valid -> ng0:itf_wr_data_valid
wire a0_native_st_itf_cmd_autopercharge; // a0:itf_cmd_autopercharge -> ng0:itf_cmd_autopercharge
wire ng0_native_st_itf_rd_data_last; // ng0:itf_rd_data_last -> a0:itf_rd_data_last
wire [63:0] ng0_native_st_itf_rd_data; // ng0:itf_rd_data -> a0:itf_rd_data
wire [2:0] a0_native_st_itf_cmd_burstlen; // a0:itf_cmd_burstlen -> ng0:itf_cmd_burstlen
wire ng0_native_st_itf_rd_data_valid; // ng0:itf_rd_data_valid -> a0:itf_rd_data_valid
wire a0_native_st_itf_cmd_multicast; // a0:itf_cmd_multicast -> ng0:itf_cmd_multicast
wire [7:0] a0_native_st_itf_cmd_id; // a0:itf_cmd_id -> ng0:itf_cmd_id
wire ng0_native_st_itf_wr_data_ready; // ng0:itf_wr_data_ready -> a0:itf_wr_data_ready
wire [7:0] ng0_native_st_itf_rd_data_id; // ng0:itf_rd_data_id -> a0:itf_rd_data_id
wire a0_native_st_itf_cmd; // a0:itf_cmd -> ng0:itf_cmd
wire a0_native_st_itf_cmd_priority; // a0:itf_cmd_priority -> ng0:itf_cmd_priority
alt_mem_if_nextgen_ddr3_controller_core #(
.MEM_IF_ADDR_WIDTH (13),
.MEM_IF_ROW_ADDR_WIDTH (13),
.MEM_IF_COL_ADDR_WIDTH (10),
.MEM_IF_DM_WIDTH (2),
.MEM_IF_DQS_WIDTH (2),
.MEM_IF_CS_WIDTH (1),
.MEM_IF_CHIP_BITS (1),
.MEM_IF_BANKADDR_WIDTH (3),
.MEM_IF_DQ_WIDTH (16),
.MEM_IF_CLK_PAIR_COUNT (1),
.MEM_TRC (27),
.MEM_TRAS (20),
.MEM_TRCD (8),
.MEM_TRP (8),
.MEM_TREFI (4158),
.MEM_TRFC (59),
.MEM_TWR (8),
.MEM_TFAW (16),
.MEM_TRRD (4),
.MEM_TRTP (4),
.MEM_IF_ODT_WIDTH (1),
.MEM_WTCL_INT (6),
.MEM_IF_RD_TO_WR_TURNAROUND_OCT (2),
.MEM_IF_WR_TO_RD_TURNAROUND_OCT (3),
.MEM_TCL (7),
.MEM_TMRD_CK (4),
.MEM_TWTR (4),
.CSR_ADDR_WIDTH (8),
.CSR_DATA_WIDTH (32),
.CSR_BE_WIDTH (4),
.CTL_CS_WIDTH (1),
.AVL_ADDR_WIDTH (24),
.AVL_BE_WIDTH (8),
.AVL_DATA_WIDTH (64),
.AVL_SIZE_WIDTH (3),
.DWIDTH_RATIO (4),
.CTL_ODT_ENABLED (0),
.CTL_OUTPUT_REGD (0),
.CTL_ECC_MULTIPLES_16_24_40_72 (1),
.CTL_REGDIMM_ENABLED (0),
.CTL_TBP_NUM (4),
.CTL_USR_REFRESH (0),
.CFG_TYPE (2),
.CFG_INTERFACE_WIDTH (16),
.CFG_BURST_LENGTH (8),
.CFG_ADDR_ORDER (0),
.CFG_PDN_EXIT_CYCLES (3),
.CFG_SELF_RFSH_EXIT_CYCLES (512),
.CFG_PORT_WIDTH_WRITE_ODT_CHIP (1),
.CFG_PORT_WIDTH_READ_ODT_CHIP (1),
.CFG_WRITE_ODT_CHIP (1),
.CFG_READ_ODT_CHIP (0),
.LOCAL_CS_WIDTH (0),
.CFG_CLR_INTR (0),
.CFG_ENABLE_NO_DM (0),
.MEM_ADD_LAT (0),
.MEM_AUTO_PD_CYCLES (0),
.CFG_REORDER_DATA (1),
.CFG_STARVE_LIMIT (10),
.CTL_CSR_ENABLED (0),
.CTL_ECC_ENABLED (0),
.CTL_ECC_AUTO_CORRECTION_ENABLED (0),
.LOCAL_ID_WIDTH (8),
.RDBUFFER_ADDR_WIDTH (7),
.WRBUFFER_ADDR_WIDTH (6),
.CFG_DATA_REORDERING_TYPE ("INTER_BANK"),
.DQS_TRK_ENABLED (0),
.AFI_RATE_RATIO (2),
.AFI_ADDR_WIDTH (26),
.AFI_BANKADDR_WIDTH (6),
.AFI_CONTROL_WIDTH (2),
.AFI_CS_WIDTH (2),
.AFI_DM_WIDTH (8),
.AFI_DQ_WIDTH (64),
.AFI_WRITE_DQS_WIDTH (4),
.AFI_RLAT_WIDTH (6),
.AFI_WLAT_WIDTH (6)
) ng0 (
.afi_reset_n (afi_reset_n), // afi_reset.reset_n
.afi_half_clk (afi_half_clk), // afi_half_clk.clk
.afi_clk (afi_clk), // afi_clk.clk
.local_init_done (local_init_done), // status.local_init_done
.local_cal_success (local_cal_success), // .local_cal_success
.local_cal_fail (local_cal_fail), // .local_cal_fail
.itf_cmd_ready (ng0_native_st_itf_cmd_ready), // native_st.itf_cmd_ready
.itf_cmd_valid (a0_native_st_itf_cmd_valid), // .itf_cmd_valid
.itf_cmd (a0_native_st_itf_cmd), // .itf_cmd
.itf_cmd_address (a0_native_st_itf_cmd_address), // .itf_cmd_address
.itf_cmd_burstlen (a0_native_st_itf_cmd_burstlen), // .itf_cmd_burstlen
.itf_cmd_id (a0_native_st_itf_cmd_id), // .itf_cmd_id
.itf_cmd_priority (a0_native_st_itf_cmd_priority), // .itf_cmd_priority
.itf_cmd_autopercharge (a0_native_st_itf_cmd_autopercharge), // .itf_cmd_autopercharge
.itf_cmd_multicast (a0_native_st_itf_cmd_multicast), // .itf_cmd_multicast
.itf_wr_data_ready (ng0_native_st_itf_wr_data_ready), // .itf_wr_data_ready
.itf_wr_data_valid (a0_native_st_itf_wr_data_valid), // .itf_wr_data_valid
.itf_wr_data (a0_native_st_itf_wr_data), // .itf_wr_data
.itf_wr_data_byte_en (a0_native_st_itf_wr_data_byte_en), // .itf_wr_data_byte_en
.itf_wr_data_begin (a0_native_st_itf_wr_data_begin), // .itf_wr_data_begin
.itf_wr_data_last (a0_native_st_itf_wr_data_last), // .itf_wr_data_last
.itf_wr_data_id (a0_native_st_itf_wr_data_id), // .itf_wr_data_id
.itf_rd_data_ready (a0_native_st_itf_rd_data_ready), // .itf_rd_data_ready
.itf_rd_data_valid (ng0_native_st_itf_rd_data_valid), // .itf_rd_data_valid
.itf_rd_data (ng0_native_st_itf_rd_data), // .itf_rd_data
.itf_rd_data_error (ng0_native_st_itf_rd_data_error), // .itf_rd_data_error
.itf_rd_data_begin (ng0_native_st_itf_rd_data_begin), // .itf_rd_data_begin
.itf_rd_data_last (ng0_native_st_itf_rd_data_last), // .itf_rd_data_last
.itf_rd_data_id (ng0_native_st_itf_rd_data_id), // .itf_rd_data_id
.afi_addr (afi_addr), // afi.afi_addr
.afi_ba (afi_ba), // .afi_ba
.afi_cke (afi_cke), // .afi_cke
.afi_cs_n (afi_cs_n), // .afi_cs_n
.afi_ras_n (afi_ras_n), // .afi_ras_n
.afi_we_n (afi_we_n), // .afi_we_n
.afi_cas_n (afi_cas_n), // .afi_cas_n
.afi_rst_n (afi_rst_n), // .afi_rst_n
.afi_odt (afi_odt), // .afi_odt
.afi_dqs_burst (afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (afi_wdata), // .afi_wdata
.afi_dm (afi_dm), // .afi_dm
.afi_rdata (afi_rdata), // .afi_rdata
.afi_rdata_en (afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (afi_rdata_valid), // .afi_rdata_valid
.afi_cal_success (afi_cal_success), // .afi_cal_success
.afi_cal_fail (afi_cal_fail), // .afi_cal_fail
.afi_cal_req (afi_cal_req), // .afi_cal_req
.afi_wlat (afi_wlat), // .afi_wlat
.afi_rlat (afi_rlat), // .afi_rlat
.local_powerdn_ack (local_powerdn_ack), // local_powerdown.local_powerdn_ack
.local_powerdn_req (local_powerdn_req), // .local_powerdn_req
.csr_write_req (1'b0), // (terminated)
.csr_read_req (1'b0), // (terminated)
.csr_waitrequest (), // (terminated)
.csr_addr (8'b00000000), // (terminated)
.csr_be (4'b0000), // (terminated)
.csr_wdata (32'b00000000000000000000000000000000), // (terminated)
.csr_rdata (), // (terminated)
.csr_rdata_valid (), // (terminated)
.csr_beginbursttransfer (1'b0), // (terminated)
.csr_burst_count (1'b0), // (terminated)
.local_multicast (1'b0), // (terminated)
.local_autopch_req (1'b0), // (terminated)
.local_refresh_req (1'b0), // (terminated)
.local_refresh_chip (1'b0), // (terminated)
.local_refresh_ack (), // (terminated)
.local_self_rfsh_req (1'b0), // (terminated)
.local_self_rfsh_chip (1'b0), // (terminated)
.local_self_rfsh_ack (), // (terminated)
.local_priority (1'b0), // (terminated)
.afi_seq_busy (1'b0), // (terminated)
.afi_ctl_refresh_done (), // (terminated)
.afi_ctl_long_idle () // (terminated)
);
alt_mem_ddrx_mm_st_converter #(
.AVL_SIZE_WIDTH (3),
.AVL_ADDR_WIDTH (24),
.AVL_DATA_WIDTH (64),
.LOCAL_ID_WIDTH (8),
.CFG_DWIDTH_RATIO (4)
) a0 (
.ctl_clk (afi_clk), // afi_clk.clk
.ctl_reset_n (afi_reset_n), // afi_reset.reset_n
.ctl_half_clk (afi_half_clk), // afi_half_clk.clk
.ctl_half_clk_reset_n (afi_reset_n), // afi_half_reset.reset_n
.avl_ready (avl_ready), // avl.waitrequest_n
.avl_burstbegin (avl_burstbegin), // .beginbursttransfer
.avl_addr (avl_addr), // .address
.avl_rdata_valid (avl_rdata_valid), // .readdatavalid
.avl_rdata (avl_rdata), // .readdata
.avl_wdata (avl_wdata), // .writedata
.avl_be (avl_be), // .byteenable
.avl_read_req (avl_read_req), // .read
.avl_write_req (avl_write_req), // .write
.avl_size (avl_size), // .burstcount
.itf_cmd_ready (ng0_native_st_itf_cmd_ready), // native_st.itf_cmd_ready
.itf_cmd_valid (a0_native_st_itf_cmd_valid), // .itf_cmd_valid
.itf_cmd (a0_native_st_itf_cmd), // .itf_cmd
.itf_cmd_address (a0_native_st_itf_cmd_address), // .itf_cmd_address
.itf_cmd_burstlen (a0_native_st_itf_cmd_burstlen), // .itf_cmd_burstlen
.itf_cmd_id (a0_native_st_itf_cmd_id), // .itf_cmd_id
.itf_cmd_priority (a0_native_st_itf_cmd_priority), // .itf_cmd_priority
.itf_cmd_autopercharge (a0_native_st_itf_cmd_autopercharge), // .itf_cmd_autopercharge
.itf_cmd_multicast (a0_native_st_itf_cmd_multicast), // .itf_cmd_multicast
.itf_wr_data_ready (ng0_native_st_itf_wr_data_ready), // .itf_wr_data_ready
.itf_wr_data_valid (a0_native_st_itf_wr_data_valid), // .itf_wr_data_valid
.itf_wr_data (a0_native_st_itf_wr_data), // .itf_wr_data
.itf_wr_data_byte_en (a0_native_st_itf_wr_data_byte_en), // .itf_wr_data_byte_en
.itf_wr_data_begin (a0_native_st_itf_wr_data_begin), // .itf_wr_data_begin
.itf_wr_data_last (a0_native_st_itf_wr_data_last), // .itf_wr_data_last
.itf_wr_data_id (a0_native_st_itf_wr_data_id), // .itf_wr_data_id
.itf_rd_data_ready (a0_native_st_itf_rd_data_ready), // .itf_rd_data_ready
.itf_rd_data_valid (ng0_native_st_itf_rd_data_valid), // .itf_rd_data_valid
.itf_rd_data (ng0_native_st_itf_rd_data), // .itf_rd_data
.itf_rd_data_error (ng0_native_st_itf_rd_data_error), // .itf_rd_data_error
.itf_rd_data_begin (ng0_native_st_itf_rd_data_begin), // .itf_rd_data_begin
.itf_rd_data_last (ng0_native_st_itf_rd_data_last), // .itf_rd_data_last
.itf_rd_data_id (ng0_native_st_itf_rd_data_id), // .itf_rd_data_id
.local_multicast (1'b0), // (terminated)
.local_autopch_req (1'b0), // (terminated)
.local_priority (1'b0) // (terminated)
);
endmodule
|
`include "../../include/incparams.vh"
////////////////////////////////////////////////////////////////////////////
// MODULE: sp_sync_fifo
////////////////////////////////////////////////////////////////////////////
module sp_sync_fifo #(
parameter WIDTH = 8,
parameter DEPTH = 256,
parameter AWIDTH = `CLOG2(DEPTH)
)(
input rst,
input clk,
input wr,
input rd,
input [WIDTH-1:0] din,
output [WIDTH-1:0] dout,
output empty,
output full
);
reg [AWIDTH:0] rd_ptr, wr_ptr;
wire [WIDTH-1:0] ram_dout;
wire [AWIDTH-1:0] ram_addr;
reg wr1;
initial begin
wr1 <= 1'b0;
wr_ptr <= 0;
rd_ptr <= 0;
end
////////////////////////////////////////////////////////////////////////////
// FIFO STATUS
////////////////////////////////////////////////////////////////////////////
assign empty = (wr_ptr == rd_ptr);
assign full = ( (wr_ptr[AWIDTH] != rd_ptr[AWIDTH]) &&
(wr_ptr[AWIDTH-1:0] == rd_ptr[AWIDTH-1:0]) );
////////////////////////////////////////////////////////////////////////////
// FIFO POINTERS
////////////////////////////////////////////////////////////////////////////
always@(posedge clk or posedge rst) begin
if(rst) begin
wr1 <= 1'b0;
wr_ptr <= {1'b0,{(AWIDTH-1){1'b0}}};
rd_ptr <= {1'b0,{(AWIDTH-1){1'b0}}};
end
else begin
wr1 <= 1'b0;
if(!full && wr) begin
wr1 <= 1'b1;
wr_ptr <= wr_ptr + 1;
if(wr_ptr[AWIDTH-1:0] == DEPTH)
wr_ptr <= {1'b1,{(AWIDTH-1){1'b0}}};
end
if(!empty && rd) begin
rd_ptr <= rd_ptr + 1;
if(rd_ptr[AWIDTH-1:0] == DEPTH)
rd_ptr <= {1'b1,{(AWIDTH-1){1'b0}}};
end
end
end
////////////////////////////////////////////////////////////////////////////
// RAM INTERFACE
////////////////////////////////////////////////////////////////////////////
assign dout = rst ? 0 : ((!empty && rd) ? ram_dout : dout);
assign ram_addr = wr1 ? wr_ptr : (rd ? rd_ptr[AWIDTH-1:0] : 0);
spram fifomem (
.clk (clk),
.we (wr),
.addr (ram_addr),
.din (din),
.dout (ram_dout)
);
defparam fifomem.DATA = WIDTH;
defparam fifomem.ADDR = AWIDTH;
dump dumpsim();
endmodule
|
// Permutation Network
`include "global.vh"
`ifdef BLESS
module permutationNetwork (
time0,
time1,
time2,
time3,
ppv0,
ppv1,
ppv2,
ppv3,
rank0_dir,
rank1_dir,
rank2_dir,
rank3_dir,
rank0_ppv,
rank1_ppv,
rank2_ppv,
rank3_ppv
);
output [1:0] rank0_dir, rank1_dir, rank2_dir, rank3_dir;
input [`TIME_WIDTH-1:0] time0, time1, time2, time3;
input [`NUM_PORT-2:0] ppv0, ppv1, ppv2, ppv3;
output [`NUM_PORT-2:0] rank0_ppv, rank1_ppv, rank2_ppv, rank3_ppv;
wire [`PERM_WIDTH-1:0] swapFlit [1:0];
wire [`PERM_WIDTH-1:0] straightFlit [1:0];
wire swap [0:3];
wire [`PERM_WIDTH-1:0] w_out [3:0];
// (1: downward sort; 0: upward sort)
arbiterPN arbiterPN00 (time0, time1, 1'b0, swap[0]);
arbiterPN arbiterPN01 (time2, time3, 1'b1, swap[1]);
arbiterPN arbiterPN10 (straightFlit[0][`PERM_WIDTH-2-`TIME_WIDTH+:`TIME_WIDTH], swapFlit[1][`PERM_WIDTH-2-`TIME_WIDTH+:`TIME_WIDTH], 1'b0, swap[2]);
arbiterPN arbiterPN11 (swapFlit[0][`PERM_WIDTH-2-`TIME_WIDTH+:`TIME_WIDTH], straightFlit[1][`PERM_WIDTH-2-`TIME_WIDTH+:`TIME_WIDTH], 1'b0, swap[3]);
permuterBlock # (`PERM_WIDTH) PN00({2'd0,time0,ppv0}, {2'd1,time1,ppv1}, swap[0], straightFlit[0], swapFlit[0]);
permuterBlock # (`PERM_WIDTH) PN01({2'd2,time2,ppv2}, {2'd3,time3,ppv3}, swap[1], swapFlit[1], straightFlit[1]);
permuterBlock # (`PERM_WIDTH) PN10(straightFlit[0], swapFlit[1], swap[2], w_out[0], w_out[1]);
permuterBlock # (`PERM_WIDTH) PN11 (swapFlit[0], straightFlit[1], swap[3], w_out[2], w_out[3]);
assign rank0_dir = w_out[0][`PERM_WIDTH-1:`PERM_WIDTH-2];
assign rank1_dir = w_out[1][`PERM_WIDTH-1:`PERM_WIDTH-2];
assign rank2_dir = w_out[2][`PERM_WIDTH-1:`PERM_WIDTH-2];
assign rank3_dir = w_out[3][`PERM_WIDTH-1:`PERM_WIDTH-2];
assign rank0_ppv = w_out[0][`NUM_PORT-2:0];
assign rank1_ppv = w_out[1][`NUM_PORT-2:0];
assign rank2_ppv = w_out[2][`NUM_PORT-2:0];
assign rank3_ppv = w_out[3][`NUM_PORT-2:0];
endmodule
`endif // BLESS
`ifdef CARPOOL
module permutationNetwork (
time0,
time1,
time2,
time3,
ppv0,
ppv1,
ppv2,
ppv3,
rank0_dir,
rank1_dir,
rank2_dir,
rank3_dir,
rank0_ppv,
rank1_ppv,
rank2_ppv,
rank3_ppv,
eject,
v_mc,
sorted_eject,
sorted_mc
);
output [1:0] rank0_dir, rank1_dir, rank2_dir, rank3_dir;
input [`TIME_WIDTH-1:0] time0, time1, time2, time3;
input [`NUM_PORT-2:0] ppv0, ppv1, ppv2, ppv3;
output [`NUM_PORT-2:0] rank0_ppv, rank1_ppv, rank2_ppv, rank3_ppv;
input [3:0] eject, v_mc;
output [3:0] sorted_eject, sorted_mc;
wire [`PERM_WIDTH-1:0] swapFlit [1:0];
wire [`PERM_WIDTH-1:0] straightFlit [1:0];
wire swap [0:3];
wire [`PERM_WIDTH-1:0] w_out [3:0];
// (1: downward sort; 0: upward sort)
arbiterPN arbiterPN00 (time0, time1, 1'b0, swap[0]);
arbiterPN arbiterPN01 (time2, time3, 1'b1, swap[1]);
arbiterPN arbiterPN10 (straightFlit[0][`PERM_WIDTH-2-`TIME_WIDTH+:`TIME_WIDTH], swapFlit[1][`PERM_WIDTH-2-`TIME_WIDTH+:`TIME_WIDTH], 1'b0, swap[2]);
arbiterPN arbiterPN11 (swapFlit[0][`PERM_WIDTH-2-`TIME_WIDTH+:`TIME_WIDTH], straightFlit[1][`PERM_WIDTH-2-`TIME_WIDTH+:`TIME_WIDTH], 1'b0, swap[3]);
permuterBlock # (`PERM_WIDTH) PN00({2'd0,time0,v_mc[0],eject[0],ppv0}, {2'd1,time1,v_mc[1],eject[1],ppv1}, swap[0], straightFlit[0], swapFlit[0]);
permuterBlock # (`PERM_WIDTH) PN01({2'd2,time2,v_mc[2],eject[2],ppv2}, {2'd3,time3,v_mc[2],eject[3],ppv3}, swap[1], swapFlit[1], straightFlit[1]);
permuterBlock # (`PERM_WIDTH) PN10(straightFlit[0], swapFlit[1], swap[2], w_out[0], w_out[1]);
permuterBlock # (`PERM_WIDTH) PN11 (swapFlit[0], straightFlit[1], swap[3], w_out[2], w_out[3]);
assign rank0_dir = w_out[0][`PERM_WIDTH-1:`PERM_WIDTH-2];
assign rank1_dir = w_out[1][`PERM_WIDTH-1:`PERM_WIDTH-2];
assign rank2_dir = w_out[2][`PERM_WIDTH-1:`PERM_WIDTH-2];
assign rank3_dir = w_out[3][`PERM_WIDTH-1:`PERM_WIDTH-2];
assign rank0_ppv = w_out[0][`NUM_PORT-2:0];
assign rank1_ppv = w_out[1][`NUM_PORT-2:0];
assign rank2_ppv = w_out[2][`NUM_PORT-2:0];
assign rank3_ppv = w_out[3][`NUM_PORT-2:0];
assign sorted_eject = {w_out[3][`NUM_PORT-1],w_out[2][`NUM_PORT-1],w_out[1][`NUM_PORT-1],w_out[0][`NUM_PORT-1]};
assign sorted_mc = {w_out[3][`NUM_PORT],w_out[2][`NUM_PORT],w_out[1][`NUM_PORT],w_out[0][`NUM_PORT]};
endmodule
`endif // CARPOOL |
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's DC RAMs ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Instatiation of DC RAM blocks. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_dc_ram.v,v $
// Revision 1.1 2006-12-21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.6 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.5 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.2.4.2 2003/12/10 15:28:28 simons
// Support for ram with byte selects added.
//
// Revision 1.2.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.2 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_dc_ram(
// Reset and clock
clk, rst,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Internal i/f
addr, en, we, datain, dataout
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_DCINDX;
//
// I/O
//
input clk;
input rst;
input [aw-1:0] addr;
input en;
input [3:0] we;
input [dw-1:0] datain;
output [dw-1:0] dataout;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
output mbist_so_o;
`endif
`ifdef OR1200_NO_DC
//
// Data cache not implemented
//
assign dataout = {dw{1'b0}};
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`else
//
// Instantiation of RAM block
//
`ifdef OR1200_DC_1W_4KB
or1200_spram_1024x32_bw dc_ram(
`endif
`ifdef OR1200_DC_1W_8KB
or1200_spram_2048x32_bw dc_ram(
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.clk(clk),
.rst(rst),
.ce(en),
.we(we),
.oe(1'b1),
.addr(addr),
.di(datain),
.doq(dataout)
);
`endif
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="adders,hls_ip_2017_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7a75tlftg256-2l,HLS_INPUT_CLOCK=3.250000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.365667,HLS_SYN_LAT=1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=236,HLS_SYN_LUT=87}" *)
module adders (
ap_clk,
ap_rst,
in1,
in2,
in3,
ap_return
);
parameter ap_ST_fsm_state1 = 2'd1;
parameter ap_ST_fsm_state2 = 2'd2;
input ap_clk;
input ap_rst;
input [31:0] in1;
input [31:0] in2;
input [31:0] in3;
output [31:0] ap_return;
wire [31:0] tmp1_fu_42_p2;
reg [31:0] tmp1_reg_53;
(* fsm_encoding = "none" *) reg [1:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
wire ap_CS_fsm_state2;
reg [1:0] ap_NS_fsm;
// power-on initialization
initial begin
#0 ap_CS_fsm = 2'd1;
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
tmp1_reg_53 <= tmp1_fu_42_p2;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1 : begin
ap_NS_fsm = ap_ST_fsm_state2;
end
ap_ST_fsm_state2 : begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
assign ap_return = (tmp1_reg_53 + in2);
assign tmp1_fu_42_p2 = (in1 + in3);
endmodule //adders
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: openMSP430_defines.v
//
// *Module Description:
// openMSP430 Configuration file
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 200 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2015-01-21 23:01:31 +0100 (Wed, 21 Jan 2015) $
//----------------------------------------------------------------------------
//`define OMSP_NO_INCLUDE
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
//============================================================================
//============================================================================
// BASIC SYSTEM CONFIGURATION
//============================================================================
//============================================================================
//
// Note: the sum of program, data and peripheral memory spaces must not
// exceed 64 kB
//
// Program Memory Size:
// Uncomment the required memory size
//-------------------------------------------------------
//`define PMEM_SIZE_CUSTOM
//`define PMEM_SIZE_59_KB
//`define PMEM_SIZE_55_KB
//`define PMEM_SIZE_54_KB
//`define PMEM_SIZE_51_KB
//`define PMEM_SIZE_48_KB
//`define PMEM_SIZE_41_KB
//`define PMEM_SIZE_32_KB
//`define PMEM_SIZE_24_KB
//`define PMEM_SIZE_16_KB
//`define PMEM_SIZE_12_KB
//`define PMEM_SIZE_8_KB
//`define PMEM_SIZE_4_KB
`define PMEM_SIZE_2_KB
//`define PMEM_SIZE_1_KB
// Data Memory Size:
// Uncomment the required memory size
//-------------------------------------------------------
//`define DMEM_SIZE_CUSTOM
//`define DMEM_SIZE_32_KB
//`define DMEM_SIZE_24_KB
//`define DMEM_SIZE_16_KB
//`define DMEM_SIZE_10_KB
//`define DMEM_SIZE_8_KB
//`define DMEM_SIZE_5_KB
//`define DMEM_SIZE_4_KB
//`define DMEM_SIZE_2p5_KB
//`define DMEM_SIZE_2_KB
//`define DMEM_SIZE_1_KB
//`define DMEM_SIZE_512_B
//`define DMEM_SIZE_256_B
`define DMEM_SIZE_128_B
// Include/Exclude Hardware Multiplier
`define MULTIPLIER
// Include/Exclude Serial Debug interface
`define DBG_EN
//============================================================================
//============================================================================
// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
//============================================================================
//============================================================================
//-------------------------------------------------------
// Custom user version number
//-------------------------------------------------------
// This 5 bit field can be freely used in order to allow
// custom identification of the system through the debug
// interface.
// (see CPU_ID.USER_VERSION field in the documentation)
//-------------------------------------------------------
`define USER_VERSION 5'b00000
//-------------------------------------------------------
// Include/Exclude Watchdog timer
//-------------------------------------------------------
// When excluded, the following functionality will be
// lost:
// - Watchog (both interval and watchdog modes)
// - NMI interrupt edge selection
// - Possibility to generate a software PUC reset
//-------------------------------------------------------
`define WATCHDOG
//-------------------------------------------------------
// Include/Exclude Non-Maskable-Interrupt support
//-------------------------------------------------------
`define NMI
//-------------------------------------------------------
// Number of available IRQs
//-------------------------------------------------------
// Indicates the number of interrupt vectors supported
// (16, 32 or 64).
//-------------------------------------------------------
`define IRQ_16
//`define IRQ_32
//`define IRQ_64
//-------------------------------------------------------
// Input synchronizers
//-------------------------------------------------------
// In some cases, the asynchronous input ports might
// already be synchronized externally.
// If an extensive CDC design review showed that this
// is really the case, the individual synchronizers
// can be disabled with the following defines.
//
// Notes:
// - all three signals are all sampled in the MCLK domain
//
// - the dbg_en signal reset the debug interface
// when 0. Therefore make sure it is glitch free.
//
//-------------------------------------------------------
`define SYNC_NMI
//`define SYNC_CPU_EN
//`define SYNC_DBG_EN
//-------------------------------------------------------
// Peripheral Memory Space:
//-------------------------------------------------------
// The original MSP430 architecture map the peripherals
// from 0x0000 to 0x01FF (i.e. 512B of the memory space).
// The following defines allow you to expand this space
// up to 32 kB (i.e. from 0x0000 to 0x7fff).
// As a consequence, the data memory mapping will be
// shifted up and a custom linker script will therefore
// be required by the GCC compiler.
//-------------------------------------------------------
//`define PER_SIZE_CUSTOM
//`define PER_SIZE_32_KB
//`define PER_SIZE_16_KB
//`define PER_SIZE_8_KB
//`define PER_SIZE_4_KB
//`define PER_SIZE_2_KB
//`define PER_SIZE_1_KB
`define PER_SIZE_512_B
//-------------------------------------------------------
// Defines the debugger CPU_CTL.RST_BRK_EN reset value
// (CPU break on PUC reset)
//-------------------------------------------------------
// When defined, the CPU will automatically break after
// a PUC occurrence by default. This is typically useful
// when the program memory can only be initialized through
// the serial debug interface.
//-------------------------------------------------------
`define DBG_RST_BRK_EN
//============================================================================
//============================================================================
// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
//============================================================================
//============================================================================
//
// IMPORTANT NOTE: Please update following configuration options ONLY if
// you have a good reason to do so... and if you know what
// you are doing :-P
//
//============================================================================
//-------------------------------------------------------
// Select serial debug interface protocol
//-------------------------------------------------------
// DBG_UART -> Enable UART (8N1) debug interface
// DBG_I2C -> Enable I2C debug interface
//-------------------------------------------------------
`define DBG_UART
//`define DBG_I2C
//-------------------------------------------------------
// Enable the I2C broadcast address
//-------------------------------------------------------
// For multicore systems, a common I2C broadcast address
// can be given to all oMSP cores in order to
// synchronously RESET, START, STOP, or STEP all CPUs
// at once with a single I2C command.
// If you have a single openMSP430 in your system,
// this option can stay commented-out.
//-------------------------------------------------------
//`define DBG_I2C_BROADCAST
//-------------------------------------------------------
// Number of hardware breakpoint/watchpoint units
// (each unit contains two hardware addresses available
// for breakpoints or watchpoints):
// - DBG_HWBRK_0 -> Include hardware breakpoints unit 0
// - DBG_HWBRK_1 -> Include hardware breakpoints unit 1
// - DBG_HWBRK_2 -> Include hardware breakpoints unit 2
// - DBG_HWBRK_3 -> Include hardware breakpoints unit 3
//-------------------------------------------------------
// Please keep in mind that hardware breakpoints only
// make sense whenever the program memory is not an SRAM
// (i.e. Flash/OTP/ROM/...) or when you are interested
// in data breakpoints.
//-------------------------------------------------------
//`define DBG_HWBRK_0
//`define DBG_HWBRK_1
//`define DBG_HWBRK_2
//`define DBG_HWBRK_3
//-------------------------------------------------------
// Enable/Disable the hardware breakpoint RANGE mode
//-------------------------------------------------------
// When enabled this feature allows the hardware breakpoint
// units to stop the cpu whenever an instruction or data
// access lays within an address range.
// Note that this feature is not supported by GDB.
//-------------------------------------------------------
//`define DBG_HWBRK_RANGE
//-------------------------------------------------------
// Custom Program/Data and Peripheral Memory Spaces
//-------------------------------------------------------
// The following values are valid only if the
// corresponding *_SIZE_CUSTOM defines are uncommented:
//
// - *_SIZE : size of the section in bytes.
// - *_AWIDTH : address port width, this value must allow
// to address all WORDS of the section
// (i.e. the *_SIZE divided by 2)
//-------------------------------------------------------
// Custom Program memory (enabled with PMEM_SIZE_CUSTOM)
`define PMEM_CUSTOM_AWIDTH 10
`define PMEM_CUSTOM_SIZE 2048
// Custom Data memory (enabled with DMEM_SIZE_CUSTOM)
`define DMEM_CUSTOM_AWIDTH 6
`define DMEM_CUSTOM_SIZE 128
// Custom Peripheral memory (enabled with PER_SIZE_CUSTOM)
`define PER_CUSTOM_AWIDTH 8
`define PER_CUSTOM_SIZE 512
//-------------------------------------------------------
// ASIC version
//-------------------------------------------------------
// When uncommented, this define will enable the
// ASIC system configuration section (see below) and
// will activate scan support for production test.
//
// WARNING: if you target an FPGA, leave this define
// commented.
//-------------------------------------------------------
`define ASIC
//============================================================================
//============================================================================
// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS/PROFESSIONALS ONLY !!!! )
//============================================================================
//============================================================================
`ifdef ASIC
//===============================================================
// FINE GRAINED CLOCK GATING
//===============================================================
//-------------------------------------------------------
// When uncommented, this define will enable the fine
// grained clock gating of all registers in the core.
//-------------------------------------------------------
`define CLOCK_GATING
//===============================================================
// ASIC CLOCKING
//===============================================================
//-------------------------------------------------------
// When uncommented, this define will enable the ASIC
// architectural clock gating as well as the advanced low
// power modes support (most common).
// Comment this out in order to get FPGA-like clocking.
//-------------------------------------------------------
`define ASIC_CLOCKING
`ifdef ASIC_CLOCKING
//===============================================================
// LFXT CLOCK DOMAIN
//===============================================================
//-------------------------------------------------------
// When uncommented, this define will enable the lfxt_clk
// clock domain.
// When commented out, the whole chip is clocked with dco_clk.
//-------------------------------------------------------
`define LFXT_DOMAIN
//===============================================================
// CLOCK MUXES
//===============================================================
//-------------------------------------------------------
// MCLK: Clock Mux
//-------------------------------------------------------
// When uncommented, this define will enable the
// MCLK clock MUX allowing the selection between
// DCO_CLK and LFXT_CLK with the BCSCTL2.SELMx register.
// When commented, DCO_CLK is selected.
//-------------------------------------------------------
`define MCLK_MUX
//-------------------------------------------------------
// SMCLK: Clock Mux
//-------------------------------------------------------
// When uncommented, this define will enable the
// SMCLK clock MUX allowing the selection between
// DCO_CLK and LFXT_CLK with the BCSCTL2.SELS register.
// When commented, DCO_CLK is selected.
//-------------------------------------------------------
`define SMCLK_MUX
//-------------------------------------------------------
// WATCHDOG: Clock Mux
//-------------------------------------------------------
// When uncommented, this define will enable the
// Watchdog clock MUX allowing the selection between
// ACLK and SMCLK with the WDTCTL.WDTSSEL register.
// When commented out, ACLK is selected if the
// WATCHDOG_NOMUX_ACLK define is uncommented, SMCLK is
// selected otherwise.
//-------------------------------------------------------
`define WATCHDOG_MUX
//`define WATCHDOG_NOMUX_ACLK
//===============================================================
// CLOCK DIVIDERS
//===============================================================
//-------------------------------------------------------
// MCLK: Clock divider
//-------------------------------------------------------
// When uncommented, this define will enable the
// MCLK clock divider (/1/2/4/8)
//-------------------------------------------------------
`define MCLK_DIVIDER
//-------------------------------------------------------
// SMCLK: Clock divider (/1/2/4/8)
//-------------------------------------------------------
// When uncommented, this define will enable the
// SMCLK clock divider
//-------------------------------------------------------
`define SMCLK_DIVIDER
//-------------------------------------------------------
// ACLK: Clock divider (/1/2/4/8)
//-------------------------------------------------------
// When uncommented, this define will enable the
// ACLK clock divider
//-------------------------------------------------------
`define ACLK_DIVIDER
//===============================================================
// LOW POWER MODES
//===============================================================
//-------------------------------------------------------
// LOW POWER MODE: CPUOFF
//-------------------------------------------------------
// When uncommented, this define will include the
// clock gate allowing to switch off MCLK in
// all low power modes: LPM0, LPM1, LPM2, LPM3, LPM4
//-------------------------------------------------------
`define CPUOFF_EN
//-------------------------------------------------------
// LOW POWER MODE: SCG0
//-------------------------------------------------------
// When uncommented, this define will enable the
// DCO_ENABLE/WKUP port control (always 1 when commented).
// This allows to switch off the DCO oscillator in the
// following low power modes: LPM1, LPM3, LPM4
//-------------------------------------------------------
`define SCG0_EN
//-------------------------------------------------------
// LOW POWER MODE: SCG1
//-------------------------------------------------------
// When uncommented, this define will include the
// clock gate allowing to switch off SMCLK in
// the following low power modes: LPM2, LPM3, LPM4
//-------------------------------------------------------
`define SCG1_EN
//-------------------------------------------------------
// LOW POWER MODE: OSCOFF
//-------------------------------------------------------
// When uncommented, this define will include the
// LFXT_CLK clock gate and enable the LFXT_ENABLE/WKUP
// port control (always 1 when commented).
// This allows to switch off the low frequency oscillator
// in the following low power modes: LPM4
//-------------------------------------------------------
`define OSCOFF_EN
`endif
`endif
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//===== SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!! =====//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//
// PROGRAM, DATA & PERIPHERAL MEMORY CONFIGURATION
//==================================================
// Program Memory Size
`ifdef PMEM_SIZE_59_KB
`define PMEM_AWIDTH 15
`define PMEM_SIZE 60416
`endif
`ifdef PMEM_SIZE_55_KB
`define PMEM_AWIDTH 15
`define PMEM_SIZE 56320
`endif
`ifdef PMEM_SIZE_54_KB
`define PMEM_AWIDTH 15
`define PMEM_SIZE 55296
`endif
`ifdef PMEM_SIZE_51_KB
`define PMEM_AWIDTH 15
`define PMEM_SIZE 52224
`endif
`ifdef PMEM_SIZE_48_KB
`define PMEM_AWIDTH 15
`define PMEM_SIZE 49152
`endif
`ifdef PMEM_SIZE_41_KB
`define PMEM_AWIDTH 15
`define PMEM_SIZE 41984
`endif
`ifdef PMEM_SIZE_32_KB
`define PMEM_AWIDTH 14
`define PMEM_SIZE 32768
`endif
`ifdef PMEM_SIZE_24_KB
`define PMEM_AWIDTH 14
`define PMEM_SIZE 24576
`endif
`ifdef PMEM_SIZE_16_KB
`define PMEM_AWIDTH 13
`define PMEM_SIZE 16384
`endif
`ifdef PMEM_SIZE_12_KB
`define PMEM_AWIDTH 13
`define PMEM_SIZE 12288
`endif
`ifdef PMEM_SIZE_8_KB
`define PMEM_AWIDTH 12
`define PMEM_SIZE 8192
`endif
`ifdef PMEM_SIZE_4_KB
`define PMEM_AWIDTH 11
`define PMEM_SIZE 4096
`endif
`ifdef PMEM_SIZE_2_KB
`define PMEM_AWIDTH 10
`define PMEM_SIZE 2048
`endif
`ifdef PMEM_SIZE_1_KB
`define PMEM_AWIDTH 9
`define PMEM_SIZE 1024
`endif
`ifdef PMEM_SIZE_CUSTOM
`define PMEM_AWIDTH `PMEM_CUSTOM_AWIDTH
`define PMEM_SIZE `PMEM_CUSTOM_SIZE
`endif
// Data Memory Size
`ifdef DMEM_SIZE_32_KB
`define DMEM_AWIDTH 14
`define DMEM_SIZE 32768
`endif
`ifdef DMEM_SIZE_24_KB
`define DMEM_AWIDTH 14
`define DMEM_SIZE 24576
`endif
`ifdef DMEM_SIZE_16_KB
`define DMEM_AWIDTH 13
`define DMEM_SIZE 16384
`endif
`ifdef DMEM_SIZE_10_KB
`define DMEM_AWIDTH 13
`define DMEM_SIZE 10240
`endif
`ifdef DMEM_SIZE_8_KB
`define DMEM_AWIDTH 12
`define DMEM_SIZE 8192
`endif
`ifdef DMEM_SIZE_5_KB
`define DMEM_AWIDTH 12
`define DMEM_SIZE 5120
`endif
`ifdef DMEM_SIZE_4_KB
`define DMEM_AWIDTH 11
`define DMEM_SIZE 4096
`endif
`ifdef DMEM_SIZE_2p5_KB
`define DMEM_AWIDTH 11
`define DMEM_SIZE 2560
`endif
`ifdef DMEM_SIZE_2_KB
`define DMEM_AWIDTH 10
`define DMEM_SIZE 2048
`endif
`ifdef DMEM_SIZE_1_KB
`define DMEM_AWIDTH 9
`define DMEM_SIZE 1024
`endif
`ifdef DMEM_SIZE_512_B
`define DMEM_AWIDTH 8
`define DMEM_SIZE 512
`endif
`ifdef DMEM_SIZE_256_B
`define DMEM_AWIDTH 7
`define DMEM_SIZE 256
`endif
`ifdef DMEM_SIZE_128_B
`define DMEM_AWIDTH 6
`define DMEM_SIZE 128
`endif
`ifdef DMEM_SIZE_CUSTOM
`define DMEM_AWIDTH `DMEM_CUSTOM_AWIDTH
`define DMEM_SIZE `DMEM_CUSTOM_SIZE
`endif
// Peripheral Memory Size
`ifdef PER_SIZE_32_KB
`define PER_AWIDTH 14
`define PER_SIZE 32768
`endif
`ifdef PER_SIZE_16_KB
`define PER_AWIDTH 13
`define PER_SIZE 16384
`endif
`ifdef PER_SIZE_8_KB
`define PER_AWIDTH 12
`define PER_SIZE 8192
`endif
`ifdef PER_SIZE_4_KB
`define PER_AWIDTH 11
`define PER_SIZE 4096
`endif
`ifdef PER_SIZE_2_KB
`define PER_AWIDTH 10
`define PER_SIZE 2048
`endif
`ifdef PER_SIZE_1_KB
`define PER_AWIDTH 9
`define PER_SIZE 1024
`endif
`ifdef PER_SIZE_512_B
`define PER_AWIDTH 8
`define PER_SIZE 512
`endif
`ifdef PER_SIZE_CUSTOM
`define PER_AWIDTH `PER_CUSTOM_AWIDTH
`define PER_SIZE `PER_CUSTOM_SIZE
`endif
// Data Memory Base Adresses
`define DMEM_BASE `PER_SIZE
// Program & Data Memory most significant address bit (for 16 bit words)
`define PMEM_MSB `PMEM_AWIDTH-1
`define DMEM_MSB `DMEM_AWIDTH-1
`define PER_MSB `PER_AWIDTH-1
// Number of available IRQs
`ifdef IRQ_16
`define IRQ_NR 16
`endif
`ifdef IRQ_32
`define IRQ_NR 32
`define IRQ_NR_GE_32
`endif
`ifdef IRQ_64
`define IRQ_NR 64
`define IRQ_NR_GE_32
`endif
//
// STATES, REGISTER FIELDS, ...
//======================================
// Instructions type
`define INST_SO 0
`define INST_JMP 1
`define INST_TO 2
// Single-operand arithmetic
`define RRC 0
`define SWPB 1
`define RRA 2
`define SXT 3
`define PUSH 4
`define CALL 5
`define RETI 6
`define IRQ 7
// Conditional jump
`define JNE 0
`define JEQ 1
`define JNC 2
`define JC 3
`define JN 4
`define JGE 5
`define JL 6
`define JMP 7
// Two-operand arithmetic
`define MOV 0
`define ADD 1
`define ADDC 2
`define SUBC 3
`define SUB 4
`define CMP 5
`define DADD 6
`define BIT 7
`define BIC 8
`define BIS 9
`define XOR 10
`define AND 11
// Addressing modes
`define DIR 0
`define IDX 1
`define INDIR 2
`define INDIR_I 3
`define SYMB 4
`define IMM 5
`define ABS 6
`define CONST 7
// Instruction state machine
`define I_IRQ_FETCH 3'h0
`define I_IRQ_DONE 3'h1
`define I_DEC 3'h2
`define I_EXT1 3'h3
`define I_EXT2 3'h4
`define I_IDLE 3'h5
// Execution state machine
// (swapped E_IRQ_0 and E_IRQ_2 values to suppress glitch generation warning from lint tool)
`define E_IRQ_0 4'h2
`define E_IRQ_1 4'h1
`define E_IRQ_2 4'h0
`define E_IRQ_3 4'h3
`define E_IRQ_4 4'h4
`define E_SRC_AD 4'h5
`define E_SRC_RD 4'h6
`define E_SRC_WR 4'h7
`define E_DST_AD 4'h8
`define E_DST_RD 4'h9
`define E_DST_WR 4'hA
`define E_EXEC 4'hB
`define E_JUMP 4'hC
`define E_IDLE 4'hD
// ALU control signals
`define ALU_SRC_INV 0
`define ALU_INC 1
`define ALU_INC_C 2
`define ALU_ADD 3
`define ALU_AND 4
`define ALU_OR 5
`define ALU_XOR 6
`define ALU_DADD 7
`define ALU_STAT_7 8
`define ALU_STAT_F 9
`define ALU_SHIFT 10
`define EXEC_NO_WR 11
// Debug interface
`define DBG_UART_WR 18
`define DBG_UART_BW 17
`define DBG_UART_ADDR 16:11
// Debug interface CPU_CTL register
`define HALT 0
`define RUN 1
`define ISTEP 2
`define SW_BRK_EN 3
`define FRZ_BRK_EN 4
`define RST_BRK_EN 5
`define CPU_RST 6
// Debug interface CPU_STAT register
`define HALT_RUN 0
`define PUC_PND 1
`define SWBRK_PND 3
`define HWBRK0_PND 4
`define HWBRK1_PND 5
// Debug interface BRKx_CTL register
`define BRK_MODE_RD 0
`define BRK_MODE_WR 1
`define BRK_MODE 1:0
`define BRK_EN 2
`define BRK_I_EN 3
`define BRK_RANGE 4
// Basic clock module: BCSCTL1 Control Register
`define DIVAx 5:4
// Basic clock module: BCSCTL2 Control Register
`define SELMx 7
`define DIVMx 5:4
`define SELS 3
`define DIVSx 2:1
// MCLK Clock gate
`ifdef CPUOFF_EN
`define MCLK_CGATE
`else
`ifdef MCLK_DIVIDER
`define MCLK_CGATE
`endif
`endif
// SMCLK Clock gate
`ifdef SCG1_EN
`define SMCLK_CGATE
`else
`ifdef SMCLK_DIVIDER
`define SMCLK_CGATE
`endif
`endif
//
// DEBUG INTERFACE EXTRA CONFIGURATION
//======================================
// Debug interface: CPU version
`define CPU_VERSION 3'h2
// Debug interface: Software breakpoint opcode
`define DBG_SWBRK_OP 16'h4343
// Debug UART interface auto data synchronization
// If the following define is commented out, then
// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly
// defined.
`define DBG_UART_AUTO_SYNC
// Debug UART interface data rate
// In order to properly setup the UART debug interface, you
// need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and
// the chosen BAUD rate from the UART interface.
//
//`define DBG_UART_BAUD 9600
//`define DBG_UART_BAUD 19200
//`define DBG_UART_BAUD 38400
//`define DBG_UART_BAUD 57600
//`define DBG_UART_BAUD 115200
//`define DBG_UART_BAUD 230400
//`define DBG_UART_BAUD 460800
//`define DBG_UART_BAUD 576000
//`define DBG_UART_BAUD 921600
`define DBG_UART_BAUD 2000000
`define DBG_DCO_FREQ 20000000
`define DBG_UART_CNT ((`DBG_DCO_FREQ/`DBG_UART_BAUD)-1)
// Debug interface input synchronizer
`define SYNC_DBG_UART_RXD
// Enable/Disable the hardware breakpoint RANGE mode
`ifdef DBG_HWBRK_RANGE
`define HWBRK_RANGE 1'b1
`else
`define HWBRK_RANGE 1'b0
`endif
// Counter width for the debug interface UART
`define DBG_UART_XFER_CNT_W 16
// Check configuration
`ifdef DBG_EN
`ifdef DBG_UART
`ifdef DBG_I2C
CONFIGURATION ERROR: I2C AND UART DEBUG INTERFACE ARE BOTH ENABLED
`endif
`else
`ifdef DBG_I2C
`else
CONFIGURATION ERROR: I2C OR UART DEBUG INTERFACE SHOULD BE ENABLED
`endif
`endif
`endif
//
// MULTIPLIER CONFIGURATION
//======================================
// If uncommented, the following define selects
// the 16x16 multiplier (1 cycle) instead of the
// default 16x8 multplier (2 cycles)
//`define MPY_16x16
//======================================
// CONFIGURATION CHECKS
//======================================
`ifdef IRQ_16
`ifdef IRQ_32
CONFIGURATION ERROR: ONLY ONE OF THE IRQ NUMBER OPTION CAN BE SELECTED
`endif
`ifdef IRQ_64
CONFIGURATION ERROR: ONLY ONE OF THE IRQ NUMBER OPTION CAN BE SELECTED
`endif
`endif
`ifdef IRQ_32
`ifdef IRQ_64
CONFIGURATION ERROR: ONLY ONE OF THE IRQ NUMBER OPTION CAN BE SELECTED
`endif
`endif
`ifdef LFXT_DOMAIN
`else
`ifdef MCLK_MUX
CONFIGURATION ERROR: THE MCLK_MUX CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
`endif
`ifdef SMCLK_MUX
CONFIGURATION ERROR: THE SMCLK_MUX CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
`endif
`ifdef WATCHDOG_MUX
CONFIGURATION ERROR: THE WATCHDOG_MUX CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
`else
`ifdef WATCHDOG_NOMUX_ACLK
CONFIGURATION ERROR: THE WATCHDOG_NOMUX_ACLK CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
`endif
`endif
`ifdef OSCOFF_EN
CONFIGURATION ERROR: THE OSCOFF LOW POWER MODE CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
`endif
`endif
|
module system_bus(
input wire clk,
input wire rst,
// MEMORY
output reg [ 7:0] cpu_data_i,
input wire [ 7:0] cpu_data_o,
input wire cpu_rw,
input wire cpu_vma,
// input wire cpu_oe_o,
input wire [ 7:0] memory_data_o,
input wire [15:0] address,
output wire ram_cs,
// UART
input wire [ 7:0] uart_rx_byte,
output reg uart_transmit,
output reg [ 7:0] uart_tx_byte,
input uart_speed,
// IRQ handling
output reg rx_status_clear,
output reg tx_status_clear,
input wire rx_status,
input wire tx_status,
// YM2151 pins
inout wire [ 7:0] ym_d,
output reg ym_a0,
output reg ym_wr_n,
output reg ym_rd_n,
output reg ym_cs_n,
output reg ym_ic_n,
input wire ym_irq_n,
input wire ym_ct1,
input wire ym_ct2,
input wire ym_so,
input wire ym_sh1,
input wire ym_sh2,
output wire ym_pm, // system clock
input wire ym_p1, // DAC clock
// JT51 pins
output jt51_cs_n, // chip select
input [7:0] jt51_do, // data out
input jt51_ct1,
input wire jt51_ct2,
input wire jt51_irq_n,
input wire jt51_sh1,
input wire jt51_sh2,
input wire signed [15:0] jt51_left,
input wire signed [15:0] jt51_right,
// level shifters
output reg dir, // 0 means FPGA writes on YM, 1 means FPGA reads from YM
// LED
output reg [ 7:0] led,
output reg [ 7:0] led_alt
);
parameter version_number = 8'hff;
parameter UART_DATA = 16'h800;
parameter UART_RXSTATUS= 16'h801;
parameter UART_TXSTATUS= 16'h802;
parameter LED = 16'h810;
parameter LED_ALT = 16'h811;
parameter VERSION = 16'h820;
parameter YMCTRL = 16'hA00;
parameter YMSIGNALS = 16'hA01;
parameter YMDATA = 16'hA02;
parameter YMPM = 16'hA03;
parameter YMICN = 16'hA04;
parameter YMA0 = 16'hA05;
parameter YMSPEED = 16'hA06;
parameter YMDATA_SYNC = 16'hA08;
parameter YMLEFT = 16'hA0A;
parameter YMRIGHT = 16'hA0C;
parameter YMCNT = 16'hA10; // 4 bytes
parameter YMLEFT_EXP = 16'hA1A; // 2 bytes
parameter YMRIGHT_EXP = 16'hA1C;
parameter YMCNT_CLR = 16'hA20; // cualquier escritura borra los cuatro byes de YMCNT
// JT51
parameter JTSIGNALS = 16'hB01;
parameter JTDATA0 = 16'hB02;
parameter JTDATA1 = 16'hB03;
parameter JTLEFT = 16'hB0A;
parameter JTRIGHT = 16'hB0C;
parameter WRITE=1'b0, READ=1'b1;
assign ram_cs = cpu_vma && (address >= 16'h8000 ); // last 32 kbytes
assign jt51_cs_n = cpu_vma && (address == 16'hB02 || address == 16'hB03 );
wire cpu_rd, cpu_wr;
reg [7:0] ym_din;
reg rst_counter;
wire [31:0] pm_counter;
reg ym_real_speed;
assign cpu_rd = cpu_rw & cpu_vma;
assign cpu_wr = ~cpu_rw & cpu_vma;
assign ym_d = dir==WRITE ? ym_din : 8'bZZZZZZZZ;
wire ym_p1_sync, ym_so_sync, ym_sh1_sync, ym_sh2_sync, ym_irq_n_sync;
wire [7:0] ym_data_sync;
pm_clk_real u_pm(
.clk ( clk ),
.rst ( rst ),
.real_speed ( ym_real_speed ),
.irq_n ( ym_irq_n_sync ),
.rst_counter( rst_counter ),
.ym_pm ( ym_pm ),
.pm_counter ( pm_counter ),
.uart_speed ( uart_speed )
);
ym_sync u_synchronizer(
.clk ( clk ),
.rst ( rst ),
// YM2151 pins
.ym_p1 ( ym_p1 ),
.ym_so ( ym_so ),
.ym_sh1 ( ym_sh1 ),
.ym_sh2 ( ym_sh2 ),
.ym_irq_n ( ym_irq_n ),
.ym_data ( ym_d ),
//
.ym_p1_sync ( ym_p1_sync ),
.ym_so_sync ( ym_so_sync ),
.ym_sh1_sync ( ym_sh1_sync ),
.ym_sh2_sync ( ym_sh2_sync ),
.ym_irq_n_sync( ym_irq_n_sync ),
.ym_data_sync ( ym_data_sync )
);
wire [15:0] left, right, left_exp, right_exp;
wire so_update_left, so_update_right;
so2par u_so2par(
.clk ( clk ),
.ym_so ( ym_so ),
.ym_sh1 ( ym_sh1 ),
.ym_sh2 ( ym_sh2 ),
.ym_p1 ( ym_p1 ),
.left ( left ),
.right ( right ),
.left_exp ( left_exp ),
.right_exp( right_exp ),
.update_left ( so_update_left ),
.update_right( so_update_right )
);
// DATA WRITE
always @(posedge clk or posedge rst) begin : ym_control
if( rst ) begin
// YM signals
ym_a0 <= 1'b0;
ym_wr_n <= 1'b0;
ym_rd_n <= 1'b0;
ym_cs_n <= 1'b0;
ym_ic_n <= 1'b0;
dir <= 1'b0;
ym_real_speed <= 1'b1;
// UART
uart_transmit <= 1'b0;
uart_tx_byte <= 8'h0;
rx_status_clear <= 1'b0;
tx_status_clear <= 1'b0;
// other
led <= 8'h0;
led_alt <= 8'h0;
end
else begin
if( cpu_wr )
case( address )
YMCTRL: begin
ym_wr_n <= cpu_data_o[0];
ym_rd_n <= cpu_data_o[1];
dir <= cpu_data_o[2];
ym_cs_n <= cpu_data_o[7];
end
UART_DATA: begin
uart_tx_byte <= cpu_data_o;
uart_transmit <= 1'b1;
end
// write to single registers with no other effect:
YMSPEED: ym_real_speed <= cpu_data_o[0];
YMICN: ym_ic_n <= cpu_data_o[0];
YMDATA: ym_din <= cpu_data_o;
YMA0: ym_a0 <= cpu_data_o[0];
YMCNT_CLR: rst_counter <= 1'b1;
LED: led <= cpu_data_o;
LED_ALT: led_alt <= cpu_data_o;
UART_RXSTATUS: rx_status_clear <= 1'b1;
UART_TXSTATUS: tx_status_clear <= 1'b1;
endcase
else begin
// these signals are only allowed to be 1 for one clock cycle
uart_transmit <= 1'b0;
rx_status_clear <= 1'b0;
tx_status_clear <= 1'b0;
rst_counter <= 1'b0;
end
end
end
// DATA READ
always @(*) begin : data_read
if( cpu_rd )
case( address )
UART_RXSTATUS:cpu_data_i <= { 7'b0, rx_status };
UART_TXSTATUS:cpu_data_i <= { 7'b0, tx_status };
UART_DATA: cpu_data_i <= uart_rx_byte;
YMCTRL: cpu_data_i <= { ym_cs_n, 5'b0, ym_rd_n, ym_wr_n };
YMSIGNALS: cpu_data_i <= { ym_irq_n_sync, ym_ct2, ym_ct1, ym_pm,
ym_p1_sync, ym_sh2_sync, ym_sh1_sync, ym_so_sync };
YMICN: cpu_data_i <= { 7'h0, ym_ic_n };
YMPM: cpu_data_i <= { 7'h0, ym_pm };
YMDATA: cpu_data_i <= ym_d;
YMDATA_SYNC: cpu_data_i <= ym_data_sync;
YMA0: cpu_data_i <= ym_a0;
LED: cpu_data_i <= led;
LED_ALT: cpu_data_i <= led_alt;
YMSPEED: cpu_data_i <= ym_real_speed;
// JT51
JTSIGNALS: cpu_data_i <= { jt51_irq_n, jt51_ct2, jt51_ct1, 2'b0,
jt51_sh2, jt51_sh1, 1'b0 };
JTDATA0: cpu_data_i <= jt51_do;
// audio data
JTLEFT: cpu_data_i <= jt51_left[15:8];
JTLEFT+16'h1: cpu_data_i <= jt51_left[ 7:0];
JTRIGHT: cpu_data_i <= jt51_right[15:8];
JTRIGHT+16'h1: cpu_data_i <= jt51_right[ 7:0];
YMLEFT: cpu_data_i <= left [15:8];
YMLEFT+16'h1: cpu_data_i <= left [ 7:0];
YMRIGHT: cpu_data_i <= right[15:8];
YMRIGHT+16'h1:cpu_data_i <= right[ 7:0];
YMLEFT_EXP: cpu_data_i <= left_exp [15:8];
YMLEFT_EXP+16'h1: cpu_data_i <= left_exp [ 7:0];
YMRIGHT_EXP: cpu_data_i <= right_exp[15:8];
YMRIGHT_EXP+16'h1:cpu_data_i <= right_exp[ 7:0];
// counter
YMCNT: cpu_data_i <= pm_counter[31:24];
YMCNT+16'h1: cpu_data_i <= pm_counter[23:16];
YMCNT+16'h2: cpu_data_i <= pm_counter[15:08];
YMCNT+16'h3: cpu_data_i <= pm_counter[ 7:0 ];
VERSION: cpu_data_i <= version_number;
default: cpu_data_i <= ram_cs ? memory_data_o : 8'h0;
endcase
else
cpu_data_i <= 8'h0;
end
endmodule
|
module lcd (clk, lcd_rs, lcd_rw, lcd_e, lcd_0, lcd_1, lcd_2, lcd_3, lcd_4, lcd_5, lcd_6, lcd_7);
parameter k = 18;
// (* LOC="E12" *) input clk; // synthesis attribute PERIOD clk "50 MHz"
// reg [k+8-1:0] count=0;
// (* LOC="W20" *) output reg NF_CEn; // high for full LCD access
// reg lcd_busy=1;
// reg lcd_stb;
// reg [5:0] lcd_code;
// reg [6:0] lcd_stuff;
// (* LOC="Y14" *) output reg lcd_rs;
// (* LOC="W13" *) output reg lcd_rw;
// (* LOC="Y15" *) output reg lcd_7;
// (* LOC="AB16" *) output reg lcd_6;
// (* LOC="Y16" *) output reg lcd_5;
// (* LOC="AA12" *) output reg lcd_4;
input clk; // synthesis attribute PERIOD clk "50 MHz"
reg [k+8-1:0] count=0;
reg lcd_busy=1;
reg lcd_stb;
reg [5:0] lcd_code;
reg [6:0] lcd_stuff;
output reg lcd_rs;
output reg lcd_rw;
output reg lcd_7;
output reg lcd_6;
output reg lcd_5;
output reg lcd_4;
output reg lcd_3;
output reg lcd_2;
output reg lcd_1;
output reg lcd_0;
output reg lcd_e;
always @ (posedge clk) begin
count <= count + 1;
lcd_0 <= 0;
lcd_1 <= 0;
lcd_2 <= 0;
lcd_3 <= 0;
case (count[k+7:k+2])
0: lcd_code <= 6'h03; // power-on initialization
1: lcd_code <= 6'h03;
2: lcd_code <= 6'h03;
3: lcd_code <= 6'h02;
4: lcd_code <= 6'h02; // function set
5: lcd_code <= 6'h08;
6: lcd_code <= 6'h00; // entry mode set
7: lcd_code <= 6'h06;
8: lcd_code <= 6'h00; // display on/off control
9: lcd_code <= 6'h0C;
10: lcd_code <= 6'h00; // display clear
11: lcd_code <= 6'h01;
12: lcd_code <= 6'h22; // *
13: lcd_code <= 6'h2A;
14: lcd_code <= 6'h22; // SPC
15: lcd_code <= 6'h20;
16: lcd_code <= 6'h24; // C
17: lcd_code <= 6'h23;
18: lcd_code <= 6'h24; // O
19: lcd_code <= 6'h2F;
20: lcd_code <= 6'h24; // L
21: lcd_code <= 6'h2C;
22: lcd_code <= 6'h24; // E
23: lcd_code <= 6'h25;
24: lcd_code <= 6'h24; // C
25: lcd_code <= 6'h23;
26: lcd_code <= 6'h24; // O
27: lcd_code <= 6'h2F;
28: lcd_code <= 6'h25; // V
29: lcd_code <= 6'h26;
30: lcd_code <= 6'h24; // I
31: lcd_code <= 6'h29;
32: lcd_code <= 6'h25; // S
33: lcd_code <= 6'h23;
34: lcd_code <= 6'h24; // I
35: lcd_code <= 6'h29;
36: lcd_code <= 6'h24; // O
37: lcd_code <= 6'h2F;
38: lcd_code <= 6'h24; // N
39: lcd_code <= 6'h2E;
40: lcd_code <= 6'h22; // SPC
41: lcd_code <= 6'h20;
42: lcd_code <= 6'h22; // *
43: lcd_code <= 6'h2A;
default: lcd_code <= 6'h10;
endcase
if (lcd_rw) // comment-out for repeating display
lcd_busy <= 0; // comment-out for repeating display
lcd_stb <= ^count[k+1:k+0] & ~lcd_rw & lcd_busy; // clkrate / 2^(k+2)
lcd_stuff <= {lcd_stb,lcd_code};
{lcd_e,lcd_rs,lcd_rw,lcd_7,lcd_6,lcd_5,lcd_4} <= lcd_stuff;
end
endmodule |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: cpx_buf_top.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////////////////
/*
// Module Name: pcx_buf_top
// Description: file containing all buffering and flopping in the
// pcx.
//
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module cpx_buf_top(/*AUTOARG*/
// Outputs
sctag3_cpx_data_buf_ca, sctag2_cpx_data_buf_ca,
sctag1_cpx_data_buf_ca, sctag0_cpx_data_buf_ca,
scache3_cpx_req_bufp3_cq, scache3_cpx_atom_bufp3_cq,
scache2_cpx_req_bufpm_cq, scache2_cpx_atom_bufpm_cq,
scache1_cpx_req_bufpm_cq, scache1_cpx_atom_bufpm_cq,
scache0_cpx_req_bufp1_cq, scache0_cpx_atom_bufp1_cq, pt1_so_1,
io_cpx_req_bufp3_cq, io_cpx_req_buf1_io_cq, io_cpx_data_buf1_ca2,
fp_cpx_req_bufp1_cq, fp_cpx_data_buf_ca, cpx_spc7_data_rdy_cx2,
cpx_spc7_data_cx2, cpx_spc6_data_rdy_cx2, cpx_spc6_data_cx2,
cpx_spc5_data_rdy_cx2, cpx_spc5_data_cx2, cpx_spc4_data_rdy_cx2,
cpx_spc4_data_cx2, cpx_spc3_data_rdy_cx2, cpx_spc3_data_cx2,
cpx_spc2_data_rdy_cx2, cpx_spc2_data_cx2, cpx_spc1_data_rdy_cx2,
cpx_spc1_data_cx2, cpx_spc0_data_rdy_cx2, cpx_spc0_data_cx2,
cpx_scache3_grant_cx, cpx_scache2_grant_cx, cpx_scache1_grant_cx,
cpx_scache0_grant_cx, cpx_io_grant_cx2, cpx_buf_top_pt0_so_1,
arbcp7_cpxdp_shift_cx, arbcp7_cpxdp_qsel1_ca_l,
arbcp7_cpxdp_qsel0_ca, arbcp7_cpxdp_q0_hold_ca_l,
arbcp7_cpxdp_grant_ca, arbcp6_cpxdp_shift_cx,
arbcp6_cpxdp_qsel1_ca_l, arbcp6_cpxdp_qsel0_ca,
arbcp6_cpxdp_q0_hold_ca_l, arbcp6_cpxdp_grant_ca,
arbcp5_cpxdp_shift_cx, arbcp5_cpxdp_qsel1_ca_l,
arbcp5_cpxdp_qsel0_ca, arbcp5_cpxdp_q0_hold_ca_l,
arbcp5_cpxdp_grant_ca, arbcp4_cpxdp_shift_cx,
arbcp4_cpxdp_qsel1_ca_l, arbcp4_cpxdp_qsel0_ca,
arbcp4_cpxdp_q0_hold_ca_l, arbcp4_cpxdp_grant_ca,
arbcp3_cpxdp_shift_cx, arbcp3_cpxdp_qsel1_ca_l,
arbcp3_cpxdp_qsel0_ca, arbcp3_cpxdp_q0_hold_ca_l,
arbcp3_cpxdp_grant_ca, arbcp2_cpxdp_shift_cx,
arbcp2_cpxdp_qsel1_ca_l, arbcp2_cpxdp_qsel0_ca,
arbcp2_cpxdp_q0_hold_ca_l, arbcp2_cpxdp_grant_ca,
arbcp1_cpxdp_shift_cx, arbcp1_cpxdp_qsel1_ca_l,
arbcp1_cpxdp_qsel0_ca, arbcp1_cpxdp_q0_hold_ca_l,
arbcp1_cpxdp_grant_ca, arbcp0_cpxdp_shift_cx,
arbcp0_cpxdp_qsel1_ca_l, arbcp0_cpxdp_qsel0_ca,
arbcp0_cpxdp_q0_hold_ca_l, arbcp0_cpxdp_grant_ca,
// Inputs
si_1, se_buf4_top, se_buf4_bottom, se_buf3_top, se_buf2_top,
se_buf2_bottom, se_buf0_middle, sctag3_cpx_data_ca,
sctag2_cpx_data_ca, sctag1_cpx_data_ca, sctag0_cpx_data_ca,
scache3_cpx_req_cq, scache3_cpx_atom_cq, scache2_cpx_req_cq,
scache2_cpx_atom_cq, scache1_cpx_req_cq, scache1_cpx_atom_cq,
scache0_cpx_req_cq, scache0_cpx_atom_cq, rclk,
pcx_scache2_dat_px2_so_1, io_cpx_req_cq, io_cpx_data_ca,
fp_cpx_req_cq, fp_cpx_data_ca, cpx_spc7_data_rdy_cx,
cpx_spc7_data_cx_l, cpx_spc6_data_rdy_cx, cpx_spc6_data_cx_l,
cpx_spc5_data_rdy_cx, cpx_spc5_data_cx_l, cpx_spc4_data_rdy_cx,
cpx_spc4_data_cx_l, cpx_spc3_data_rdy_cx, cpx_spc3_data_cx_l,
cpx_spc2_data_rdy_cx, cpx_spc2_data_cx_l, cpx_spc1_data_rdy_cx,
cpx_spc1_data_cx_l, cpx_spc0_data_rdy_cx, cpx_spc0_data_cx_l,
cpx_scache3_grant_ca, cpx_scache2_grant_ca, cpx_scache1_grant_ca,
cpx_scache0_grant_ca, cpx_io_grant_ca,
arbcp7_cpxdp_shift_arbbf_cx, arbcp7_cpxdp_qsel1_arbbf_ca_l,
arbcp7_cpxdp_qsel0_arbbf_ca, arbcp7_cpxdp_q0_hold_arbbf_ca_l,
arbcp7_cpxdp_grant_arbbf_ca, arbcp6_cpxdp_shift_arbbf_cx,
arbcp6_cpxdp_qsel1_arbbf_ca_l, arbcp6_cpxdp_qsel0_arbbf_ca,
arbcp6_cpxdp_q0_hold_arbbf_ca_l, arbcp6_cpxdp_grant_arbbf_ca,
arbcp5_cpxdp_shift_arbbf_cx, arbcp5_cpxdp_qsel1_arbbf_ca_l,
arbcp5_cpxdp_qsel0_arbbf_ca, arbcp5_cpxdp_q0_hold_arbbf_ca_l,
arbcp5_cpxdp_grant_arbbf_ca, arbcp4_cpxdp_shift_arbbf_cx,
arbcp4_cpxdp_qsel1_arbbf_ca_l, arbcp4_cpxdp_qsel0_arbbf_ca,
arbcp4_cpxdp_q0_hold_arbbf_ca_l, arbcp4_cpxdp_grant_arbbf_ca,
arbcp3_cpxdp_shift_arbbf_cx, arbcp3_cpxdp_qsel1_arbbf_ca_l,
arbcp3_cpxdp_qsel0_arbbf_ca, arbcp3_cpxdp_q0_hold_arbbf_ca_l,
arbcp3_cpxdp_grant_arbbf_ca, arbcp2_cpxdp_shift_arbbf_cx,
arbcp2_cpxdp_qsel1_arbbf_ca_l, arbcp2_cpxdp_qsel0_arbbf_ca,
arbcp2_cpxdp_q0_hold_arbbf_ca_l, arbcp2_cpxdp_grant_arbbf_ca,
arbcp1_cpxdp_shift_arbbf_cx, arbcp1_cpxdp_qsel1_arbbf_ca_l,
arbcp1_cpxdp_qsel0_arbbf_ca, arbcp1_cpxdp_q0_hold_arbbf_ca_l,
arbcp1_cpxdp_grant_arbbf_ca, arbcp0_cpxdp_shift_arbbf_cx,
arbcp0_cpxdp_qsel1_arbbf_ca_l, arbcp0_cpxdp_qsel0_arbbf_ca,
arbcp0_cpxdp_q0_hold_arbbf_ca_l, arbcp0_cpxdp_grant_arbbf_ca
);
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [5:0] arbcp0_cpxdp_grant_ca; // From pm1_even of cpx_buf_pm_even.v, ...
output [5:0] arbcp0_cpxdp_q0_hold_ca_l;// From pm1_even of cpx_buf_pm_even.v, ...
output [5:0] arbcp0_cpxdp_qsel0_ca; // From pm1_even of cpx_buf_pm_even.v, ...
output [5:0] arbcp0_cpxdp_qsel1_ca_l;// From pm1_even of cpx_buf_pm_even.v, ...
output [5:0] arbcp0_cpxdp_shift_cx; // From pm1_even of cpx_buf_pm_even.v, ...
output [5:0] arbcp1_cpxdp_grant_ca; // From pm1_odd of cpx_buf_pm_even.v, ...
output [5:0] arbcp1_cpxdp_q0_hold_ca_l;// From pm1_odd of cpx_buf_pm_even.v, ...
output [5:0] arbcp1_cpxdp_qsel0_ca; // From pm1_odd of cpx_buf_pm_even.v, ...
output [5:0] arbcp1_cpxdp_qsel1_ca_l;// From pm1_odd of cpx_buf_pm_even.v, ...
output [5:0] arbcp1_cpxdp_shift_cx; // From pm1_odd of cpx_buf_pm_even.v, ...
output [5:0] arbcp2_cpxdp_grant_ca; // From pm1_even of cpx_buf_pm_even.v, ...
output [5:0] arbcp2_cpxdp_q0_hold_ca_l;// From pm1_even of cpx_buf_pm_even.v, ...
output [5:0] arbcp2_cpxdp_qsel0_ca; // From pm1_even of cpx_buf_pm_even.v, ...
output [5:0] arbcp2_cpxdp_qsel1_ca_l;// From pm1_even of cpx_buf_pm_even.v, ...
output [5:0] arbcp2_cpxdp_shift_cx; // From pm1_even of cpx_buf_pm_even.v, ...
output [5:0] arbcp3_cpxdp_grant_ca; // From pm1_odd of cpx_buf_pm_even.v, ...
output [5:0] arbcp3_cpxdp_q0_hold_ca_l;// From pm1_odd of cpx_buf_pm_even.v, ...
output [5:0] arbcp3_cpxdp_qsel0_ca; // From pm1_odd of cpx_buf_pm_even.v, ...
output [5:0] arbcp3_cpxdp_qsel1_ca_l;// From pm1_odd of cpx_buf_pm_even.v, ...
output [5:0] arbcp3_cpxdp_shift_cx; // From pm1_odd of cpx_buf_pm_even.v, ...
output [5:0] arbcp4_cpxdp_grant_ca; // From pm1_even of cpx_buf_pm_even.v, ...
output [5:0] arbcp4_cpxdp_q0_hold_ca_l;// From pm1_even of cpx_buf_pm_even.v, ...
output [5:0] arbcp4_cpxdp_qsel0_ca; // From pm1_even of cpx_buf_pm_even.v, ...
output [5:0] arbcp4_cpxdp_qsel1_ca_l;// From pm1_even of cpx_buf_pm_even.v, ...
output [5:0] arbcp4_cpxdp_shift_cx; // From pm1_even of cpx_buf_pm_even.v, ...
output [5:0] arbcp5_cpxdp_grant_ca; // From pm1_odd of cpx_buf_pm_even.v, ...
output [5:0] arbcp5_cpxdp_q0_hold_ca_l;// From pm1_odd of cpx_buf_pm_even.v, ...
output [5:0] arbcp5_cpxdp_qsel0_ca; // From pm1_odd of cpx_buf_pm_even.v, ...
output [5:0] arbcp5_cpxdp_qsel1_ca_l;// From pm1_odd of cpx_buf_pm_even.v, ...
output [5:0] arbcp5_cpxdp_shift_cx; // From pm1_odd of cpx_buf_pm_even.v, ...
output [5:0] arbcp6_cpxdp_grant_ca; // From pm1_even of cpx_buf_pm_even.v, ...
output [5:0] arbcp6_cpxdp_q0_hold_ca_l;// From pm1_even of cpx_buf_pm_even.v, ...
output [5:0] arbcp6_cpxdp_qsel0_ca; // From pm1_even of cpx_buf_pm_even.v, ...
output [5:0] arbcp6_cpxdp_qsel1_ca_l;// From pm1_even of cpx_buf_pm_even.v, ...
output [5:0] arbcp6_cpxdp_shift_cx; // From pm1_even of cpx_buf_pm_even.v, ...
output [5:0] arbcp7_cpxdp_grant_ca; // From pm1_odd of cpx_buf_pm_even.v, ...
output [5:0] arbcp7_cpxdp_q0_hold_ca_l;// From pm1_odd of cpx_buf_pm_even.v, ...
output [5:0] arbcp7_cpxdp_qsel0_ca; // From pm1_odd of cpx_buf_pm_even.v, ...
output [5:0] arbcp7_cpxdp_qsel1_ca_l;// From pm1_odd of cpx_buf_pm_even.v, ...
output [5:0] arbcp7_cpxdp_shift_cx; // From pm1_odd of cpx_buf_pm_even.v, ...
output cpx_buf_top_pt0_so_1; // From pt0 of cpx_buf_pt.v
output [7:0] cpx_io_grant_cx2; // From ff_io_grant of cpx_io_grant_ff.v
output [7:0] cpx_scache0_grant_cx; // From pt0 of cpx_buf_pt.v
output [7:0] cpx_scache1_grant_cx; // From pt1 of cpx_buf_pt.v
output [7:0] cpx_scache2_grant_cx; // From pt2 of cpx_buf_pt.v
output [7:0] cpx_scache3_grant_cx; // From pt3 of cpx_buf_pt.v
output [`CPX_WIDTH-1:0]cpx_spc0_data_cx2; // From ff0 of cpx_datacx2_ff.v
output cpx_spc0_data_rdy_cx2; // From ff0 of cpx_datacx2_ff.v
output [`CPX_WIDTH-1:0]cpx_spc1_data_cx2; // From ff1 of cpx_datacx2_ff.v
output cpx_spc1_data_rdy_cx2; // From ff1 of cpx_datacx2_ff.v
output [`CPX_WIDTH-1:0]cpx_spc2_data_cx2; // From ff2 of cpx_datacx2_ff.v
output cpx_spc2_data_rdy_cx2; // From ff2 of cpx_datacx2_ff.v
output [`CPX_WIDTH-1:0]cpx_spc3_data_cx2; // From ff3 of cpx_datacx2_ff.v
output cpx_spc3_data_rdy_cx2; // From ff3 of cpx_datacx2_ff.v
output [`CPX_WIDTH-1:0]cpx_spc4_data_cx2; // From ff4 of cpx_datacx2_ff.v
output cpx_spc4_data_rdy_cx2; // From ff4 of cpx_datacx2_ff.v
output [`CPX_WIDTH-1:0]cpx_spc5_data_cx2; // From ff5 of cpx_datacx2_ff.v
output cpx_spc5_data_rdy_cx2; // From ff5 of cpx_datacx2_ff.v
output [`CPX_WIDTH-1:0]cpx_spc6_data_cx2; // From ff6 of cpx_datacx2_ff.v
output cpx_spc6_data_rdy_cx2; // From ff6 of cpx_datacx2_ff.v
output [`CPX_WIDTH-1:0]cpx_spc7_data_cx2; // From ff7 of cpx_datacx2_ff.v
output cpx_spc7_data_rdy_cx2; // From ff7 of cpx_datacx2_ff.v
output [`CPX_WIDTH-1:0]fp_cpx_data_buf_ca; // From buf_fp_cpx_data of cpx_databuf_ca.v
output [7:0] fp_cpx_req_bufp1_cq; // From fpbuf_p1 of cpx_fpbuf_p1.v
output [`CPX_WIDTH-1:0]io_cpx_data_buf1_ca2; // From buf1_io_cpx_data of cpx_databuf_ca.v
output [7:0] io_cpx_req_buf1_io_cq; // From buf1_io of cpx_buf_io.v
output [7:0] io_cpx_req_bufp3_cq; // From p3 of cpx_buf_p3.v
output pt1_so_1; // From pt1 of cpx_buf_pt.v
output scache0_cpx_atom_bufp1_cq;// From p1 of cpx_buf_p1.v
output [7:0] scache0_cpx_req_bufp1_cq;// From p1 of cpx_buf_p1.v
output scache1_cpx_atom_bufpm_cq;// From pm1 of cpx_buf_pm.v
output [7:0] scache1_cpx_req_bufpm_cq;// From pm1 of cpx_buf_pm.v
output scache2_cpx_atom_bufpm_cq;// From pm2 of cpx_buf_pm.v
output [7:0] scache2_cpx_req_bufpm_cq;// From pm2 of cpx_buf_pm.v
output scache3_cpx_atom_bufp3_cq;// From p3 of cpx_buf_p3.v
output [7:0] scache3_cpx_req_bufp3_cq;// From p3 of cpx_buf_p3.v
output [`CPX_WIDTH-1:0]sctag0_cpx_data_buf_ca;// From buf_sctag0_cpx_data of cpx_databuf_ca.v
output [`CPX_WIDTH-1:0]sctag1_cpx_data_buf_ca;// From buf_sctag1_cpx_data of cpx_databuf_ca.v
output [`CPX_WIDTH-1:0]sctag2_cpx_data_buf_ca;// From buf_sctag2_cpx_data of cpx_databuf_ca.v
output [`CPX_WIDTH-1:0]sctag3_cpx_data_buf_ca;// From buf_sctag3_cpx_data of cpx_databuf_ca.v
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [5:0] arbcp0_cpxdp_grant_arbbf_ca;// To p1 of cpx_buf_p1.v, ...
input [5:0] arbcp0_cpxdp_q0_hold_arbbf_ca_l;// To p1 of cpx_buf_p1.v, ...
input [5:0] arbcp0_cpxdp_qsel0_arbbf_ca;// To p1 of cpx_buf_p1.v, ...
input [5:0] arbcp0_cpxdp_qsel1_arbbf_ca_l;// To p1 of cpx_buf_p1.v, ...
input [5:0] arbcp0_cpxdp_shift_arbbf_cx;// To p1 of cpx_buf_p1.v, ...
input [5:0] arbcp1_cpxdp_grant_arbbf_ca;// To p1 of cpx_buf_p1.v, ...
input [5:0] arbcp1_cpxdp_q0_hold_arbbf_ca_l;// To p1 of cpx_buf_p1.v, ...
input [5:0] arbcp1_cpxdp_qsel0_arbbf_ca;// To p1 of cpx_buf_p1.v, ...
input [5:0] arbcp1_cpxdp_qsel1_arbbf_ca_l;// To p1 of cpx_buf_p1.v, ...
input [5:0] arbcp1_cpxdp_shift_arbbf_cx;// To p1 of cpx_buf_p1.v, ...
input [5:0] arbcp2_cpxdp_grant_arbbf_ca;// To p1 of cpx_buf_p1.v, ...
input [5:0] arbcp2_cpxdp_q0_hold_arbbf_ca_l;// To p1 of cpx_buf_p1.v, ...
input [5:0] arbcp2_cpxdp_qsel0_arbbf_ca;// To p1 of cpx_buf_p1.v, ...
input [5:0] arbcp2_cpxdp_qsel1_arbbf_ca_l;// To p1 of cpx_buf_p1.v, ...
input [5:0] arbcp2_cpxdp_shift_arbbf_cx;// To p1 of cpx_buf_p1.v, ...
input [5:0] arbcp3_cpxdp_grant_arbbf_ca;// To p1 of cpx_buf_p1.v, ...
input [5:0] arbcp3_cpxdp_q0_hold_arbbf_ca_l;// To p1 of cpx_buf_p1.v, ...
input [5:0] arbcp3_cpxdp_qsel0_arbbf_ca;// To p1 of cpx_buf_p1.v, ...
input [5:0] arbcp3_cpxdp_qsel1_arbbf_ca_l;// To p1 of cpx_buf_p1.v, ...
input [5:0] arbcp3_cpxdp_shift_arbbf_cx;// To p1 of cpx_buf_p1.v, ...
input [5:0] arbcp4_cpxdp_grant_arbbf_ca;// To p1 of cpx_buf_p1.v, ...
input [5:0] arbcp4_cpxdp_q0_hold_arbbf_ca_l;// To p1 of cpx_buf_p1.v, ...
input [5:0] arbcp4_cpxdp_qsel0_arbbf_ca;// To p1 of cpx_buf_p1.v, ...
input [5:0] arbcp4_cpxdp_qsel1_arbbf_ca_l;// To p1 of cpx_buf_p1.v, ...
input [5:0] arbcp4_cpxdp_shift_arbbf_cx;// To p1 of cpx_buf_p1.v, ...
input [5:0] arbcp5_cpxdp_grant_arbbf_ca;// To p1 of cpx_buf_p1.v, ...
input [5:0] arbcp5_cpxdp_q0_hold_arbbf_ca_l;// To p1 of cpx_buf_p1.v, ...
input [5:0] arbcp5_cpxdp_qsel0_arbbf_ca;// To p1 of cpx_buf_p1.v, ...
input [5:0] arbcp5_cpxdp_qsel1_arbbf_ca_l;// To p1 of cpx_buf_p1.v, ...
input [5:0] arbcp5_cpxdp_shift_arbbf_cx;// To p1 of cpx_buf_p1.v, ...
input [5:0] arbcp6_cpxdp_grant_arbbf_ca;// To p1 of cpx_buf_p1.v, ...
input [5:0] arbcp6_cpxdp_q0_hold_arbbf_ca_l;// To p1 of cpx_buf_p1.v, ...
input [5:0] arbcp6_cpxdp_qsel0_arbbf_ca;// To p1 of cpx_buf_p1.v, ...
input [5:0] arbcp6_cpxdp_qsel1_arbbf_ca_l;// To p1 of cpx_buf_p1.v, ...
input [5:0] arbcp6_cpxdp_shift_arbbf_cx;// To p1 of cpx_buf_p1.v, ...
input [5:0] arbcp7_cpxdp_grant_arbbf_ca;// To p1 of cpx_buf_p1.v, ...
input [5:0] arbcp7_cpxdp_q0_hold_arbbf_ca_l;// To p1 of cpx_buf_p1.v, ...
input [5:0] arbcp7_cpxdp_qsel0_arbbf_ca;// To p1 of cpx_buf_p1.v, ...
input [5:0] arbcp7_cpxdp_qsel1_arbbf_ca_l;// To p1 of cpx_buf_p1.v, ...
input [5:0] arbcp7_cpxdp_shift_arbbf_cx;// To p1 of cpx_buf_p1.v, ...
input [7:0] cpx_io_grant_ca; // To buf1_io of cpx_buf_io.v
input [7:0] cpx_scache0_grant_ca; // To p1 of cpx_buf_p1.v
input [7:0] cpx_scache1_grant_ca; // To pm1 of cpx_buf_pm.v
input [7:0] cpx_scache2_grant_ca; // To pm2 of cpx_buf_pm.v
input [7:0] cpx_scache3_grant_ca; // To p3 of cpx_buf_p3.v
input [`CPX_WIDTH-1:0]cpx_spc0_data_cx_l; // To ff0 of cpx_datacx2_ff.v
input cpx_spc0_data_rdy_cx; // To p1 of cpx_buf_p1.v
input [`CPX_WIDTH-1:0]cpx_spc1_data_cx_l; // To ff1 of cpx_datacx2_ff.v
input cpx_spc1_data_rdy_cx; // To p1 of cpx_buf_p1.v
input [`CPX_WIDTH-1:0]cpx_spc2_data_cx_l; // To ff2 of cpx_datacx2_ff.v
input cpx_spc2_data_rdy_cx; // To p1 of cpx_buf_p1.v
input [`CPX_WIDTH-1:0]cpx_spc3_data_cx_l; // To ff3 of cpx_datacx2_ff.v
input cpx_spc3_data_rdy_cx; // To ff3 of cpx_datacx2_ff.v
input [`CPX_WIDTH-1:0]cpx_spc4_data_cx_l; // To ff4 of cpx_datacx2_ff.v
input cpx_spc4_data_rdy_cx; // To ff4 of cpx_datacx2_ff.v
input [`CPX_WIDTH-1:0]cpx_spc5_data_cx_l; // To ff5 of cpx_datacx2_ff.v
input cpx_spc5_data_rdy_cx; // To p3 of cpx_buf_p3.v
input [`CPX_WIDTH-1:0]cpx_spc6_data_cx_l; // To ff6 of cpx_datacx2_ff.v
input cpx_spc6_data_rdy_cx; // To p3 of cpx_buf_p3.v
input [`CPX_WIDTH-1:0]cpx_spc7_data_cx_l; // To ff7 of cpx_datacx2_ff.v
input cpx_spc7_data_rdy_cx; // To p3 of cpx_buf_p3.v
input [`CPX_WIDTH-1:0]fp_cpx_data_ca; // To buf2_fp_cpx_data of cpx_databuf_ca2.v
input [7:0] fp_cpx_req_cq; // To fp of cpx_buf_pt.v
input [`CPX_WIDTH-1:0]io_cpx_data_ca; // To ff_io of io_cpx_reqdata_ff.v
input [7:0] io_cpx_req_cq; // To ff_io of io_cpx_reqdata_ff.v
input pcx_scache2_dat_px2_so_1;// To pt2 of cpx_buf_pt.v
input rclk; // To pt0 of cpx_buf_pt.v, ...
input scache0_cpx_atom_cq; // To pt0 of cpx_buf_pt.v
input [7:0] scache0_cpx_req_cq; // To pt0 of cpx_buf_pt.v
input scache1_cpx_atom_cq; // To pt1 of cpx_buf_pt.v
input [7:0] scache1_cpx_req_cq; // To pt1 of cpx_buf_pt.v
input scache2_cpx_atom_cq; // To pt2 of cpx_buf_pt.v
input [7:0] scache2_cpx_req_cq; // To pt2 of cpx_buf_pt.v
input scache3_cpx_atom_cq; // To pt3 of cpx_buf_pt.v
input [7:0] scache3_cpx_req_cq; // To pt3 of cpx_buf_pt.v
input [`CPX_WIDTH-1:0]sctag0_cpx_data_ca; // To buf_sctag0_cpx_data of cpx_databuf_ca.v
input [`CPX_WIDTH-1:0]sctag1_cpx_data_ca; // To buf_sctag1_cpx_data of cpx_databuf_ca.v
input [`CPX_WIDTH-1:0]sctag2_cpx_data_ca; // To buf_sctag2_cpx_data of cpx_databuf_ca.v
input [`CPX_WIDTH-1:0]sctag3_cpx_data_ca; // To buf_sctag3_cpx_data of cpx_databuf_ca.v
input se_buf0_middle; // To fp of cpx_buf_pt.v
input se_buf2_bottom; // To pt3 of cpx_buf_pt.v, ...
input se_buf2_top; // To pt2 of cpx_buf_pt.v, ...
input se_buf3_top; // To io of cpx_buf_pt.v, ...
input se_buf4_bottom; // To pt1 of cpx_buf_pt.v, ...
input se_buf4_top; // To pt0 of cpx_buf_pt.v, ...
input si_1; // To ff7 of cpx_datacx2_ff.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [3:0] arbcp0_cpxdp_grant_bufp1_ca_l;// From p1 of cpx_buf_p1.v, ...
wire [5:2] arbcp0_cpxdp_grant_bufp3_ca_l;// From p3 of cpx_buf_p3.v, ...
wire [3:0] arbcp0_cpxdp_q0_hold_bufp1_ca;// From p1 of cpx_buf_p1.v, ...
wire [5:2] arbcp0_cpxdp_q0_hold_bufp3_ca;// From p3 of cpx_buf_p3.v, ...
wire [3:0] arbcp0_cpxdp_qsel0_bufp1_ca_l;// From p1 of cpx_buf_p1.v, ...
wire [5:2] arbcp0_cpxdp_qsel0_bufp3_ca_l;// From p3 of cpx_buf_p3.v, ...
wire [3:0] arbcp0_cpxdp_qsel1_bufp1_ca;// From p1 of cpx_buf_p1.v, ...
wire [5:2] arbcp0_cpxdp_qsel1_bufp3_ca;// From p3 of cpx_buf_p3.v, ...
wire [3:0] arbcp0_cpxdp_shift_bufp1_cx_l;// From p1 of cpx_buf_p1.v, ...
wire [5:2] arbcp0_cpxdp_shift_bufp3_cx_l;// From p3 of cpx_buf_p3.v, ...
wire [3:0] arbcp1_cpxdp_grant_bufp1_ca_l;// From p1 of cpx_buf_p1.v, ...
wire [5:2] arbcp1_cpxdp_grant_bufp3_ca_l;// From p3 of cpx_buf_p3.v, ...
wire [3:0] arbcp1_cpxdp_q0_hold_bufp1_ca;// From p1 of cpx_buf_p1.v, ...
wire [5:2] arbcp1_cpxdp_q0_hold_bufp3_ca;// From p3 of cpx_buf_p3.v, ...
wire [3:0] arbcp1_cpxdp_qsel0_bufp1_ca_l;// From p1 of cpx_buf_p1.v, ...
wire [5:2] arbcp1_cpxdp_qsel0_bufp3_ca_l;// From p3 of cpx_buf_p3.v, ...
wire [3:0] arbcp1_cpxdp_qsel1_bufp1_ca;// From p1 of cpx_buf_p1.v, ...
wire [5:2] arbcp1_cpxdp_qsel1_bufp3_ca;// From p3 of cpx_buf_p3.v, ...
wire [3:0] arbcp1_cpxdp_shift_bufp1_cx_l;// From p1 of cpx_buf_p1.v, ...
wire [5:2] arbcp1_cpxdp_shift_bufp3_cx_l;// From p3 of cpx_buf_p3.v, ...
wire [3:0] arbcp2_cpxdp_grant_bufp1_ca_l;// From p1 of cpx_buf_p1.v, ...
wire [5:2] arbcp2_cpxdp_grant_bufp3_ca_l;// From p3 of cpx_buf_p3.v, ...
wire [3:0] arbcp2_cpxdp_q0_hold_bufp1_ca;// From p1 of cpx_buf_p1.v, ...
wire [5:2] arbcp2_cpxdp_q0_hold_bufp3_ca;// From p3 of cpx_buf_p3.v, ...
wire [3:0] arbcp2_cpxdp_qsel0_bufp1_ca_l;// From p1 of cpx_buf_p1.v, ...
wire [5:2] arbcp2_cpxdp_qsel0_bufp3_ca_l;// From p3 of cpx_buf_p3.v, ...
wire [3:0] arbcp2_cpxdp_qsel1_bufp1_ca;// From p1 of cpx_buf_p1.v, ...
wire [5:2] arbcp2_cpxdp_qsel1_bufp3_ca;// From p3 of cpx_buf_p3.v, ...
wire [3:0] arbcp2_cpxdp_shift_bufp1_cx_l;// From p1 of cpx_buf_p1.v, ...
wire [5:2] arbcp2_cpxdp_shift_bufp3_cx_l;// From p3 of cpx_buf_p3.v, ...
wire [3:0] arbcp3_cpxdp_grant_bufp1_ca_l;// From p1 of cpx_buf_p1.v, ...
wire [5:2] arbcp3_cpxdp_grant_bufp3_ca_l;// From p3 of cpx_buf_p3.v, ...
wire [3:0] arbcp3_cpxdp_q0_hold_bufp1_ca;// From p1 of cpx_buf_p1.v, ...
wire [5:2] arbcp3_cpxdp_q0_hold_bufp3_ca;// From p3 of cpx_buf_p3.v, ...
wire [3:0] arbcp3_cpxdp_qsel0_bufp1_ca_l;// From p1 of cpx_buf_p1.v, ...
wire [5:2] arbcp3_cpxdp_qsel0_bufp3_ca_l;// From p3 of cpx_buf_p3.v, ...
wire [3:0] arbcp3_cpxdp_qsel1_bufp1_ca;// From p1 of cpx_buf_p1.v, ...
wire [5:2] arbcp3_cpxdp_qsel1_bufp3_ca;// From p3 of cpx_buf_p3.v, ...
wire [3:0] arbcp3_cpxdp_shift_bufp1_cx_l;// From p1 of cpx_buf_p1.v, ...
wire [5:2] arbcp3_cpxdp_shift_bufp3_cx_l;// From p3 of cpx_buf_p3.v, ...
wire [3:0] arbcp4_cpxdp_grant_bufp1_ca_l;// From p1 of cpx_buf_p1.v, ...
wire [5:2] arbcp4_cpxdp_grant_bufp3_ca_l;// From p3 of cpx_buf_p3.v, ...
wire [3:0] arbcp4_cpxdp_q0_hold_bufp1_ca;// From p1 of cpx_buf_p1.v, ...
wire [5:2] arbcp4_cpxdp_q0_hold_bufp3_ca;// From p3 of cpx_buf_p3.v, ...
wire [3:0] arbcp4_cpxdp_qsel0_bufp1_ca_l;// From p1 of cpx_buf_p1.v, ...
wire [5:2] arbcp4_cpxdp_qsel0_bufp3_ca_l;// From p3 of cpx_buf_p3.v, ...
wire [3:0] arbcp4_cpxdp_qsel1_bufp1_ca;// From p1 of cpx_buf_p1.v, ...
wire [5:2] arbcp4_cpxdp_qsel1_bufp3_ca;// From p3 of cpx_buf_p3.v, ...
wire [3:0] arbcp4_cpxdp_shift_bufp1_cx_l;// From p1 of cpx_buf_p1.v, ...
wire [5:2] arbcp4_cpxdp_shift_bufp3_cx_l;// From p3 of cpx_buf_p3.v, ...
wire [3:0] arbcp5_cpxdp_grant_bufp1_ca_l;// From p1 of cpx_buf_p1.v, ...
wire [5:2] arbcp5_cpxdp_grant_bufp3_ca_l;// From p3 of cpx_buf_p3.v, ...
wire [3:0] arbcp5_cpxdp_q0_hold_bufp1_ca;// From p1 of cpx_buf_p1.v, ...
wire [5:2] arbcp5_cpxdp_q0_hold_bufp3_ca;// From p3 of cpx_buf_p3.v, ...
wire [3:0] arbcp5_cpxdp_qsel0_bufp1_ca_l;// From p1 of cpx_buf_p1.v, ...
wire [5:2] arbcp5_cpxdp_qsel0_bufp3_ca_l;// From p3 of cpx_buf_p3.v, ...
wire [3:0] arbcp5_cpxdp_qsel1_bufp1_ca;// From p1 of cpx_buf_p1.v, ...
wire [5:2] arbcp5_cpxdp_qsel1_bufp3_ca;// From p3 of cpx_buf_p3.v, ...
wire [3:0] arbcp5_cpxdp_shift_bufp1_cx_l;// From p1 of cpx_buf_p1.v, ...
wire [5:2] arbcp5_cpxdp_shift_bufp3_cx_l;// From p3 of cpx_buf_p3.v, ...
wire [3:0] arbcp6_cpxdp_grant_bufp1_ca_l;// From p1 of cpx_buf_p1.v, ...
wire [5:2] arbcp6_cpxdp_grant_bufp3_ca_l;// From p3 of cpx_buf_p3.v, ...
wire [3:0] arbcp6_cpxdp_q0_hold_bufp1_ca;// From p1 of cpx_buf_p1.v, ...
wire [5:2] arbcp6_cpxdp_q0_hold_bufp3_ca;// From p3 of cpx_buf_p3.v, ...
wire [3:0] arbcp6_cpxdp_qsel0_bufp1_ca_l;// From p1 of cpx_buf_p1.v, ...
wire [5:2] arbcp6_cpxdp_qsel0_bufp3_ca_l;// From p3 of cpx_buf_p3.v, ...
wire [3:0] arbcp6_cpxdp_qsel1_bufp1_ca;// From p1 of cpx_buf_p1.v, ...
wire [5:2] arbcp6_cpxdp_qsel1_bufp3_ca;// From p3 of cpx_buf_p3.v, ...
wire [3:0] arbcp6_cpxdp_shift_bufp1_cx_l;// From p1 of cpx_buf_p1.v, ...
wire [5:2] arbcp6_cpxdp_shift_bufp3_cx_l;// From p3 of cpx_buf_p3.v, ...
wire [3:0] arbcp7_cpxdp_grant_bufp1_ca_l;// From p1 of cpx_buf_p1.v, ...
wire [5:2] arbcp7_cpxdp_grant_bufp3_ca_l;// From p3 of cpx_buf_p3.v, ...
wire [3:0] arbcp7_cpxdp_q0_hold_bufp1_ca;// From p1 of cpx_buf_p1.v, ...
wire [5:2] arbcp7_cpxdp_q0_hold_bufp3_ca;// From p3 of cpx_buf_p3.v, ...
wire [3:0] arbcp7_cpxdp_qsel0_bufp1_ca_l;// From p1 of cpx_buf_p1.v, ...
wire [5:2] arbcp7_cpxdp_qsel0_bufp3_ca_l;// From p3 of cpx_buf_p3.v, ...
wire [3:0] arbcp7_cpxdp_qsel1_bufp1_ca;// From p1 of cpx_buf_p1.v, ...
wire [5:2] arbcp7_cpxdp_qsel1_bufp3_ca;// From p3 of cpx_buf_p3.v, ...
wire [3:0] arbcp7_cpxdp_shift_bufp1_cx_l;// From p1 of cpx_buf_p1.v, ...
wire [5:2] arbcp7_cpxdp_shift_bufp3_cx_l;// From p3 of cpx_buf_p3.v, ...
wire [7:0] cpx_io_grant_buf1_io_ca;// From buf1_io of cpx_buf_io.v
wire [7:0] cpx_io_grant_cx; // From io of cpx_buf_pt.v
wire [7:0] cpx_scache0_grant_bufp0_ca;// From p0 of cpx_buf_p0.v
wire [7:0] cpx_scache0_grant_bufp1_ca_l;// From p1 of cpx_buf_p1.v
wire [7:0] cpx_scache1_grant_bufpm_ca;// From pm1 of cpx_buf_pm.v
wire [7:0] cpx_scache2_grant_bufpm_ca;// From pm2 of cpx_buf_pm.v
wire [7:0] cpx_scache3_grant_bufp3_ca_l;// From p3 of cpx_buf_p3.v
wire [7:0] cpx_scache3_grant_bufp4_ca;// From p4 of cpx_buf_p4.v
wire cpx_spc0_data_rdy_bufp0_cx;// From p0 of cpx_buf_p0.v
wire cpx_spc0_data_rdy_bufp1_cx;// From p1 of cpx_buf_p1.v
wire cpx_spc1_data_rdy_bufp1_cx;// From p1 of cpx_buf_p1.v
wire cpx_spc2_data_rdy_bufp1_cx;// From p1 of cpx_buf_p1.v
wire cpx_spc5_data_rdy_bufp3_cx;// From p3 of cpx_buf_p3.v
wire cpx_spc6_data_rdy_bufp3_cx;// From p3 of cpx_buf_p3.v
wire cpx_spc7_data_rdy_bufp3_cx;// From p3 of cpx_buf_p3.v
wire cpx_spc7_data_rdy_bufp4_cx;// From p4 of cpx_buf_p4.v
wire ff0_so_1; // From ff0 of cpx_datacx2_ff.v
wire ff1_so_1; // From ff1 of cpx_datacx2_ff.v
wire ff2_so_1; // From ff2 of cpx_datacx2_ff.v
wire ff3_so_1; // From ff3 of cpx_datacx2_ff.v
wire ff4_so_1; // From ff4 of cpx_datacx2_ff.v
wire ff5_so_1; // From ff5 of cpx_datacx2_ff.v
wire ff6_so_1; // From ff6 of cpx_datacx2_ff.v
wire ff7_so_1; // From ff7 of cpx_datacx2_ff.v
wire ff_io_grant_so_1; // From ff_io_grant of cpx_io_grant_ff.v
wire [`CPX_WIDTH-1:0]fp_cpx_data_buf1_ca; // From buf2_fp_cpx_data of cpx_databuf_ca2.v
wire [7:0] fp_cpx_req_bufp0_cq; // From fpbuf_p0 of cpx_fpbuf_p0.v
wire [7:0] fp_cpx_req_bufpt_cq_l; // From fp of cpx_buf_pt.v
wire fp_so_1; // From fp of cpx_buf_pt.v
wire [`CPX_WIDTH-1:0]io_cpx_data_ca2; // From ff_io of io_cpx_reqdata_ff.v
wire [7:0] io_cpx_req_bufp4_cq; // From p4 of cpx_buf_p4.v
wire [7:0] io_cpx_req_bufpt_cq_l; // From io of cpx_buf_pt.v
wire [7:0] io_cpx_req_cq2; // From ff_io of io_cpx_reqdata_ff.v
wire io_cpx_reqdata_ff_so_1; // From ff_io of io_cpx_reqdata_ff.v
wire io_so_1; // From io of cpx_buf_pt.v
wire pt2_so_1; // From pt2 of cpx_buf_pt.v
wire pt3_so_1; // From pt3 of cpx_buf_pt.v
wire scache0_cpx_atom_bufp0_cq;// From p0 of cpx_buf_p0.v
wire scache0_cpx_atom_bufpt_cq_l;// From pt0 of cpx_buf_pt.v
wire [7:0] scache0_cpx_req_bufp0_cq;// From p0 of cpx_buf_p0.v
wire [7:0] scache0_cpx_req_bufpt_cq_l;// From pt0 of cpx_buf_pt.v
wire scache1_cpx_atom_bufpt_cq_l;// From pt1 of cpx_buf_pt.v
wire [7:0] scache1_cpx_req_bufpt_cq_l;// From pt1 of cpx_buf_pt.v
wire scache2_cpx_atom_bufpt_cq_l;// From pt2 of cpx_buf_pt.v
wire [7:0] scache2_cpx_req_bufpt_cq_l;// From pt2 of cpx_buf_pt.v
wire scache3_cpx_atom_bufp4_cq;// From p4 of cpx_buf_p4.v
wire scache3_cpx_atom_bufpt_cq_l;// From pt3 of cpx_buf_pt.v
wire [7:0] scache3_cpx_req_bufp4_cq;// From p4 of cpx_buf_p4.v
wire [7:0] scache3_cpx_req_bufpt_cq_l;// From pt3 of cpx_buf_pt.v
// End of automatics
/* cpx_buf_pm AUTO_TEMPLATE(
// Outputs
.cpx_scache_grant_bufpm_ca(cpx_scache@_grant_bufpm_ca[7:0]),
.scache_cpx_req_bufpm_cq(scache@_cpx_req_bufpm_cq[7:0]),
.scache_cpx_atom_bufpm_cq(scache@_cpx_atom_bufpm_cq),
// Inputs
.cpx_scache_grant_ca (cpx_scache@_grant_ca[7:0]),
.scache_cpx_req_bufpt_cq_l(scache@_cpx_req_bufpt_cq_l[7:0]),
.scache_cpx_atom_bufpt_cq_l(scache@_cpx_atom_bufpt_cq_l));
*/
cpx_buf_pm pm1(/*AUTOINST*/
// Outputs
.cpx_scache_grant_bufpm_ca(cpx_scache1_grant_bufpm_ca[7:0]), // Templated
.scache_cpx_req_bufpm_cq(scache1_cpx_req_bufpm_cq[7:0]), // Templated
.scache_cpx_atom_bufpm_cq(scache1_cpx_atom_bufpm_cq), // Templated
// Inputs
.cpx_scache_grant_ca (cpx_scache1_grant_ca[7:0]), // Templated
.scache_cpx_req_bufpt_cq_l(scache1_cpx_req_bufpt_cq_l[7:0]), // Templated
.scache_cpx_atom_bufpt_cq_l(scache1_cpx_atom_bufpt_cq_l)); // Templated
cpx_buf_pm pm2(/*AUTOINST*/
// Outputs
.cpx_scache_grant_bufpm_ca(cpx_scache2_grant_bufpm_ca[7:0]), // Templated
.scache_cpx_req_bufpm_cq(scache2_cpx_req_bufpm_cq[7:0]), // Templated
.scache_cpx_atom_bufpm_cq(scache2_cpx_atom_bufpm_cq), // Templated
// Inputs
.cpx_scache_grant_ca (cpx_scache2_grant_ca[7:0]), // Templated
.scache_cpx_req_bufpt_cq_l(scache2_cpx_req_bufpt_cq_l[7:0]), // Templated
.scache_cpx_atom_bufpt_cq_l(scache2_cpx_atom_bufpt_cq_l)); // Templated
/* cpx_buf_pm_even AUTO_TEMPLATE(
// Outputs
.arbcp0_cpxdp_grant_ca(arbcp0_cpxdp_grant_ca[@]),
.arbcp0_cpxdp_q0_hold_ca_l(arbcp0_cpxdp_q0_hold_ca_l[@]),
.arbcp0_cpxdp_qsel0_ca(arbcp0_cpxdp_qsel0_ca[@]),
.arbcp0_cpxdp_qsel1_ca_l(arbcp0_cpxdp_qsel1_ca_l[@]),
.arbcp0_cpxdp_shift_cx(arbcp0_cpxdp_shift_cx[@]),
.arbcp2_cpxdp_grant_ca(arbcp2_cpxdp_grant_ca[@]),
.arbcp2_cpxdp_q0_hold_ca_l(arbcp2_cpxdp_q0_hold_ca_l[@]),
.arbcp2_cpxdp_qsel0_ca(arbcp2_cpxdp_qsel0_ca[@]),
.arbcp2_cpxdp_qsel1_ca_l(arbcp2_cpxdp_qsel1_ca_l[@]),
.arbcp2_cpxdp_shift_cx(arbcp2_cpxdp_shift_cx[@]),
.arbcp4_cpxdp_grant_ca(arbcp4_cpxdp_grant_ca[@]),
.arbcp4_cpxdp_q0_hold_ca_l(arbcp4_cpxdp_q0_hold_ca_l[@]),
.arbcp4_cpxdp_qsel0_ca(arbcp4_cpxdp_qsel0_ca[@]),
.arbcp4_cpxdp_qsel1_ca_l(arbcp4_cpxdp_qsel1_ca_l[@]),
.arbcp4_cpxdp_shift_cx(arbcp4_cpxdp_shift_cx[@]),
.arbcp6_cpxdp_grant_ca(arbcp6_cpxdp_grant_ca[@]),
.arbcp6_cpxdp_q0_hold_ca_l(arbcp6_cpxdp_q0_hold_ca_l[@]),
.arbcp6_cpxdp_qsel0_ca(arbcp6_cpxdp_qsel0_ca[@]),
.arbcp6_cpxdp_qsel1_ca_l(arbcp6_cpxdp_qsel1_ca_l[@]),
.arbcp6_cpxdp_shift_cx(arbcp6_cpxdp_shift_cx[@]),
// Inputs
.arbcp0_cpxdp_grant_arbbf_ca_l(arbcp0_cpxdp_grant_bufp1_ca_l[@]),
.arbcp0_cpxdp_q0_hold_arbbf_ca(arbcp0_cpxdp_q0_hold_bufp1_ca[@]),
.arbcp0_cpxdp_qsel0_arbbf_ca_l(arbcp0_cpxdp_qsel0_bufp1_ca_l[@]),
.arbcp0_cpxdp_qsel1_arbbf_ca(arbcp0_cpxdp_qsel1_bufp1_ca[@]),
.arbcp0_cpxdp_shift_arbbf_cx_l(arbcp0_cpxdp_shift_bufp1_cx_l[@]),
.arbcp2_cpxdp_grant_arbbf_ca_l(arbcp2_cpxdp_grant_bufp1_ca_l[@]),
.arbcp2_cpxdp_q0_hold_arbbf_ca(arbcp2_cpxdp_q0_hold_bufp1_ca[@]),
.arbcp2_cpxdp_qsel0_arbbf_ca_l(arbcp2_cpxdp_qsel0_bufp1_ca_l[@]),
.arbcp2_cpxdp_qsel1_arbbf_ca(arbcp2_cpxdp_qsel1_bufp1_ca[@]),
.arbcp2_cpxdp_shift_arbbf_cx_l(arbcp2_cpxdp_shift_bufp1_cx_l[@]),
.arbcp4_cpxdp_grant_arbbf_ca_l(arbcp4_cpxdp_grant_bufp1_ca_l[@]),
.arbcp4_cpxdp_q0_hold_arbbf_ca(arbcp4_cpxdp_q0_hold_bufp1_ca[@]),
.arbcp4_cpxdp_qsel0_arbbf_ca_l(arbcp4_cpxdp_qsel0_bufp1_ca_l[@]),
.arbcp4_cpxdp_qsel1_arbbf_ca(arbcp4_cpxdp_qsel1_bufp1_ca[@]),
.arbcp4_cpxdp_shift_arbbf_cx_l(arbcp4_cpxdp_shift_bufp1_cx_l[@]),
.arbcp6_cpxdp_grant_arbbf_ca_l(arbcp6_cpxdp_grant_bufp1_ca_l[@]),
.arbcp6_cpxdp_q0_hold_arbbf_ca(arbcp6_cpxdp_q0_hold_bufp1_ca[@]),
.arbcp6_cpxdp_qsel0_arbbf_ca_l(arbcp6_cpxdp_qsel0_bufp1_ca_l[@]),
.arbcp6_cpxdp_qsel1_arbbf_ca(arbcp6_cpxdp_qsel1_bufp1_ca[@]),
.arbcp6_cpxdp_shift_arbbf_cx_l(arbcp6_cpxdp_shift_bufp1_cx_l[@]));
*/
cpx_buf_pm_even pm1_even(/*AUTOINST*/
// Outputs
.arbcp0_cpxdp_grant_ca(arbcp0_cpxdp_grant_ca[1]), // Templated
.arbcp0_cpxdp_q0_hold_ca_l(arbcp0_cpxdp_q0_hold_ca_l[1]), // Templated
.arbcp0_cpxdp_qsel0_ca(arbcp0_cpxdp_qsel0_ca[1]), // Templated
.arbcp0_cpxdp_qsel1_ca_l(arbcp0_cpxdp_qsel1_ca_l[1]), // Templated
.arbcp0_cpxdp_shift_cx(arbcp0_cpxdp_shift_cx[1]), // Templated
.arbcp2_cpxdp_grant_ca(arbcp2_cpxdp_grant_ca[1]), // Templated
.arbcp2_cpxdp_q0_hold_ca_l(arbcp2_cpxdp_q0_hold_ca_l[1]), // Templated
.arbcp2_cpxdp_qsel0_ca(arbcp2_cpxdp_qsel0_ca[1]), // Templated
.arbcp2_cpxdp_qsel1_ca_l(arbcp2_cpxdp_qsel1_ca_l[1]), // Templated
.arbcp2_cpxdp_shift_cx(arbcp2_cpxdp_shift_cx[1]), // Templated
.arbcp4_cpxdp_grant_ca(arbcp4_cpxdp_grant_ca[1]), // Templated
.arbcp4_cpxdp_q0_hold_ca_l(arbcp4_cpxdp_q0_hold_ca_l[1]), // Templated
.arbcp4_cpxdp_qsel0_ca(arbcp4_cpxdp_qsel0_ca[1]), // Templated
.arbcp4_cpxdp_qsel1_ca_l(arbcp4_cpxdp_qsel1_ca_l[1]), // Templated
.arbcp4_cpxdp_shift_cx(arbcp4_cpxdp_shift_cx[1]), // Templated
.arbcp6_cpxdp_grant_ca(arbcp6_cpxdp_grant_ca[1]), // Templated
.arbcp6_cpxdp_q0_hold_ca_l(arbcp6_cpxdp_q0_hold_ca_l[1]), // Templated
.arbcp6_cpxdp_qsel0_ca(arbcp6_cpxdp_qsel0_ca[1]), // Templated
.arbcp6_cpxdp_qsel1_ca_l(arbcp6_cpxdp_qsel1_ca_l[1]), // Templated
.arbcp6_cpxdp_shift_cx(arbcp6_cpxdp_shift_cx[1]), // Templated
// Inputs
.arbcp0_cpxdp_grant_arbbf_ca_l(arbcp0_cpxdp_grant_bufp1_ca_l[1]), // Templated
.arbcp0_cpxdp_q0_hold_arbbf_ca(arbcp0_cpxdp_q0_hold_bufp1_ca[1]), // Templated
.arbcp0_cpxdp_qsel0_arbbf_ca_l(arbcp0_cpxdp_qsel0_bufp1_ca_l[1]), // Templated
.arbcp0_cpxdp_qsel1_arbbf_ca(arbcp0_cpxdp_qsel1_bufp1_ca[1]), // Templated
.arbcp0_cpxdp_shift_arbbf_cx_l(arbcp0_cpxdp_shift_bufp1_cx_l[1]), // Templated
.arbcp2_cpxdp_grant_arbbf_ca_l(arbcp2_cpxdp_grant_bufp1_ca_l[1]), // Templated
.arbcp2_cpxdp_q0_hold_arbbf_ca(arbcp2_cpxdp_q0_hold_bufp1_ca[1]), // Templated
.arbcp2_cpxdp_qsel0_arbbf_ca_l(arbcp2_cpxdp_qsel0_bufp1_ca_l[1]), // Templated
.arbcp2_cpxdp_qsel1_arbbf_ca(arbcp2_cpxdp_qsel1_bufp1_ca[1]), // Templated
.arbcp2_cpxdp_shift_arbbf_cx_l(arbcp2_cpxdp_shift_bufp1_cx_l[1]), // Templated
.arbcp4_cpxdp_grant_arbbf_ca_l(arbcp4_cpxdp_grant_bufp1_ca_l[1]), // Templated
.arbcp4_cpxdp_q0_hold_arbbf_ca(arbcp4_cpxdp_q0_hold_bufp1_ca[1]), // Templated
.arbcp4_cpxdp_qsel0_arbbf_ca_l(arbcp4_cpxdp_qsel0_bufp1_ca_l[1]), // Templated
.arbcp4_cpxdp_qsel1_arbbf_ca(arbcp4_cpxdp_qsel1_bufp1_ca[1]), // Templated
.arbcp4_cpxdp_shift_arbbf_cx_l(arbcp4_cpxdp_shift_bufp1_cx_l[1]), // Templated
.arbcp6_cpxdp_grant_arbbf_ca_l(arbcp6_cpxdp_grant_bufp1_ca_l[1]), // Templated
.arbcp6_cpxdp_q0_hold_arbbf_ca(arbcp6_cpxdp_q0_hold_bufp1_ca[1]), // Templated
.arbcp6_cpxdp_qsel0_arbbf_ca_l(arbcp6_cpxdp_qsel0_bufp1_ca_l[1]), // Templated
.arbcp6_cpxdp_qsel1_arbbf_ca(arbcp6_cpxdp_qsel1_bufp1_ca[1]), // Templated
.arbcp6_cpxdp_shift_arbbf_cx_l(arbcp6_cpxdp_shift_bufp1_cx_l[1])); // Templated
/* cpx_buf_pm_even AUTO_TEMPLATE(
// Outputs
.arbcp0_cpxdp_grant_ca(arbcp0_cpxdp_grant_ca[@]),
.arbcp0_cpxdp_q0_hold_ca_l(arbcp0_cpxdp_q0_hold_ca_l[@]),
.arbcp0_cpxdp_qsel0_ca(arbcp0_cpxdp_qsel0_ca[@]),
.arbcp0_cpxdp_qsel1_ca_l(arbcp0_cpxdp_qsel1_ca_l[@]),
.arbcp0_cpxdp_shift_cx(arbcp0_cpxdp_shift_cx[@]),
.arbcp2_cpxdp_grant_ca(arbcp2_cpxdp_grant_ca[@]),
.arbcp2_cpxdp_q0_hold_ca_l(arbcp2_cpxdp_q0_hold_ca_l[@]),
.arbcp2_cpxdp_qsel0_ca(arbcp2_cpxdp_qsel0_ca[@]),
.arbcp2_cpxdp_qsel1_ca_l(arbcp2_cpxdp_qsel1_ca_l[@]),
.arbcp2_cpxdp_shift_cx(arbcp2_cpxdp_shift_cx[@]),
.arbcp4_cpxdp_grant_ca(arbcp4_cpxdp_grant_ca[@]),
.arbcp4_cpxdp_q0_hold_ca_l(arbcp4_cpxdp_q0_hold_ca_l[@]),
.arbcp4_cpxdp_qsel0_ca(arbcp4_cpxdp_qsel0_ca[@]),
.arbcp4_cpxdp_qsel1_ca_l(arbcp4_cpxdp_qsel1_ca_l[@]),
.arbcp4_cpxdp_shift_cx(arbcp4_cpxdp_shift_cx[@]),
.arbcp6_cpxdp_grant_ca(arbcp6_cpxdp_grant_ca[@]),
.arbcp6_cpxdp_q0_hold_ca_l(arbcp6_cpxdp_q0_hold_ca_l[@]),
.arbcp6_cpxdp_qsel0_ca(arbcp6_cpxdp_qsel0_ca[@]),
.arbcp6_cpxdp_qsel1_ca_l(arbcp6_cpxdp_qsel1_ca_l[@]),
.arbcp6_cpxdp_shift_cx(arbcp6_cpxdp_shift_cx[@]),
// Inputs
.arbcp0_cpxdp_grant_arbbf_ca_l(arbcp0_cpxdp_grant_bufp3_ca_l[@]),
.arbcp0_cpxdp_q0_hold_arbbf_ca(arbcp0_cpxdp_q0_hold_bufp3_ca[@]),
.arbcp0_cpxdp_qsel0_arbbf_ca_l(arbcp0_cpxdp_qsel0_bufp3_ca_l[@]),
.arbcp0_cpxdp_qsel1_arbbf_ca(arbcp0_cpxdp_qsel1_bufp3_ca[@]),
.arbcp0_cpxdp_shift_arbbf_cx_l(arbcp0_cpxdp_shift_bufp3_cx_l[@]),
.arbcp2_cpxdp_grant_arbbf_ca_l(arbcp2_cpxdp_grant_bufp3_ca_l[@]),
.arbcp2_cpxdp_q0_hold_arbbf_ca(arbcp2_cpxdp_q0_hold_bufp3_ca[@]),
.arbcp2_cpxdp_qsel0_arbbf_ca_l(arbcp2_cpxdp_qsel0_bufp3_ca_l[@]),
.arbcp2_cpxdp_qsel1_arbbf_ca(arbcp2_cpxdp_qsel1_bufp3_ca[@]),
.arbcp2_cpxdp_shift_arbbf_cx_l(arbcp2_cpxdp_shift_bufp3_cx_l[@]),
.arbcp4_cpxdp_grant_arbbf_ca_l(arbcp4_cpxdp_grant_bufp3_ca_l[@]),
.arbcp4_cpxdp_q0_hold_arbbf_ca(arbcp4_cpxdp_q0_hold_bufp3_ca[@]),
.arbcp4_cpxdp_qsel0_arbbf_ca_l(arbcp4_cpxdp_qsel0_bufp3_ca_l[@]),
.arbcp4_cpxdp_qsel1_arbbf_ca(arbcp4_cpxdp_qsel1_bufp3_ca[@]),
.arbcp4_cpxdp_shift_arbbf_cx_l(arbcp4_cpxdp_shift_bufp3_cx_l[@]),
.arbcp6_cpxdp_grant_arbbf_ca_l(arbcp6_cpxdp_grant_bufp3_ca_l[@]),
.arbcp6_cpxdp_q0_hold_arbbf_ca(arbcp6_cpxdp_q0_hold_bufp3_ca[@]),
.arbcp6_cpxdp_qsel0_arbbf_ca_l(arbcp6_cpxdp_qsel0_bufp3_ca_l[@]),
.arbcp6_cpxdp_qsel1_arbbf_ca(arbcp6_cpxdp_qsel1_bufp3_ca[@]),
.arbcp6_cpxdp_shift_arbbf_cx_l(arbcp6_cpxdp_shift_bufp3_cx_l[@]));
*/
cpx_buf_pm_even pm2_even(/*AUTOINST*/
// Outputs
.arbcp0_cpxdp_grant_ca(arbcp0_cpxdp_grant_ca[2]), // Templated
.arbcp0_cpxdp_q0_hold_ca_l(arbcp0_cpxdp_q0_hold_ca_l[2]), // Templated
.arbcp0_cpxdp_qsel0_ca(arbcp0_cpxdp_qsel0_ca[2]), // Templated
.arbcp0_cpxdp_qsel1_ca_l(arbcp0_cpxdp_qsel1_ca_l[2]), // Templated
.arbcp0_cpxdp_shift_cx(arbcp0_cpxdp_shift_cx[2]), // Templated
.arbcp2_cpxdp_grant_ca(arbcp2_cpxdp_grant_ca[2]), // Templated
.arbcp2_cpxdp_q0_hold_ca_l(arbcp2_cpxdp_q0_hold_ca_l[2]), // Templated
.arbcp2_cpxdp_qsel0_ca(arbcp2_cpxdp_qsel0_ca[2]), // Templated
.arbcp2_cpxdp_qsel1_ca_l(arbcp2_cpxdp_qsel1_ca_l[2]), // Templated
.arbcp2_cpxdp_shift_cx(arbcp2_cpxdp_shift_cx[2]), // Templated
.arbcp4_cpxdp_grant_ca(arbcp4_cpxdp_grant_ca[2]), // Templated
.arbcp4_cpxdp_q0_hold_ca_l(arbcp4_cpxdp_q0_hold_ca_l[2]), // Templated
.arbcp4_cpxdp_qsel0_ca(arbcp4_cpxdp_qsel0_ca[2]), // Templated
.arbcp4_cpxdp_qsel1_ca_l(arbcp4_cpxdp_qsel1_ca_l[2]), // Templated
.arbcp4_cpxdp_shift_cx(arbcp4_cpxdp_shift_cx[2]), // Templated
.arbcp6_cpxdp_grant_ca(arbcp6_cpxdp_grant_ca[2]), // Templated
.arbcp6_cpxdp_q0_hold_ca_l(arbcp6_cpxdp_q0_hold_ca_l[2]), // Templated
.arbcp6_cpxdp_qsel0_ca(arbcp6_cpxdp_qsel0_ca[2]), // Templated
.arbcp6_cpxdp_qsel1_ca_l(arbcp6_cpxdp_qsel1_ca_l[2]), // Templated
.arbcp6_cpxdp_shift_cx(arbcp6_cpxdp_shift_cx[2]), // Templated
// Inputs
.arbcp0_cpxdp_grant_arbbf_ca_l(arbcp0_cpxdp_grant_bufp3_ca_l[2]), // Templated
.arbcp0_cpxdp_q0_hold_arbbf_ca(arbcp0_cpxdp_q0_hold_bufp3_ca[2]), // Templated
.arbcp0_cpxdp_qsel0_arbbf_ca_l(arbcp0_cpxdp_qsel0_bufp3_ca_l[2]), // Templated
.arbcp0_cpxdp_qsel1_arbbf_ca(arbcp0_cpxdp_qsel1_bufp3_ca[2]), // Templated
.arbcp0_cpxdp_shift_arbbf_cx_l(arbcp0_cpxdp_shift_bufp3_cx_l[2]), // Templated
.arbcp2_cpxdp_grant_arbbf_ca_l(arbcp2_cpxdp_grant_bufp3_ca_l[2]), // Templated
.arbcp2_cpxdp_q0_hold_arbbf_ca(arbcp2_cpxdp_q0_hold_bufp3_ca[2]), // Templated
.arbcp2_cpxdp_qsel0_arbbf_ca_l(arbcp2_cpxdp_qsel0_bufp3_ca_l[2]), // Templated
.arbcp2_cpxdp_qsel1_arbbf_ca(arbcp2_cpxdp_qsel1_bufp3_ca[2]), // Templated
.arbcp2_cpxdp_shift_arbbf_cx_l(arbcp2_cpxdp_shift_bufp3_cx_l[2]), // Templated
.arbcp4_cpxdp_grant_arbbf_ca_l(arbcp4_cpxdp_grant_bufp3_ca_l[2]), // Templated
.arbcp4_cpxdp_q0_hold_arbbf_ca(arbcp4_cpxdp_q0_hold_bufp3_ca[2]), // Templated
.arbcp4_cpxdp_qsel0_arbbf_ca_l(arbcp4_cpxdp_qsel0_bufp3_ca_l[2]), // Templated
.arbcp4_cpxdp_qsel1_arbbf_ca(arbcp4_cpxdp_qsel1_bufp3_ca[2]), // Templated
.arbcp4_cpxdp_shift_arbbf_cx_l(arbcp4_cpxdp_shift_bufp3_cx_l[2]), // Templated
.arbcp6_cpxdp_grant_arbbf_ca_l(arbcp6_cpxdp_grant_bufp3_ca_l[2]), // Templated
.arbcp6_cpxdp_q0_hold_arbbf_ca(arbcp6_cpxdp_q0_hold_bufp3_ca[2]), // Templated
.arbcp6_cpxdp_qsel0_arbbf_ca_l(arbcp6_cpxdp_qsel0_bufp3_ca_l[2]), // Templated
.arbcp6_cpxdp_qsel1_arbbf_ca(arbcp6_cpxdp_qsel1_bufp3_ca[2]), // Templated
.arbcp6_cpxdp_shift_arbbf_cx_l(arbcp6_cpxdp_shift_bufp3_cx_l[2])); // Templated
/* cpx_buf_pm_even AUTO_TEMPLATE(
// Outputs
.arbcp0_cpxdp_grant_ca(arbcp1_cpxdp_grant_ca[@]),
.arbcp0_cpxdp_q0_hold_ca_l(arbcp1_cpxdp_q0_hold_ca_l[@]),
.arbcp0_cpxdp_qsel0_ca(arbcp1_cpxdp_qsel0_ca[@]),
.arbcp0_cpxdp_qsel1_ca_l(arbcp1_cpxdp_qsel1_ca_l[@]),
.arbcp0_cpxdp_shift_cx(arbcp1_cpxdp_shift_cx[@]),
.arbcp2_cpxdp_grant_ca(arbcp3_cpxdp_grant_ca[@]),
.arbcp2_cpxdp_q0_hold_ca_l(arbcp3_cpxdp_q0_hold_ca_l[@]),
.arbcp2_cpxdp_qsel0_ca(arbcp3_cpxdp_qsel0_ca[@]),
.arbcp2_cpxdp_qsel1_ca_l(arbcp3_cpxdp_qsel1_ca_l[@]),
.arbcp2_cpxdp_shift_cx(arbcp3_cpxdp_shift_cx[@]),
.arbcp4_cpxdp_grant_ca(arbcp5_cpxdp_grant_ca[@]),
.arbcp4_cpxdp_q0_hold_ca_l(arbcp5_cpxdp_q0_hold_ca_l[@]),
.arbcp4_cpxdp_qsel0_ca(arbcp5_cpxdp_qsel0_ca[@]),
.arbcp4_cpxdp_qsel1_ca_l(arbcp5_cpxdp_qsel1_ca_l[@]),
.arbcp4_cpxdp_shift_cx(arbcp5_cpxdp_shift_cx[@]),
.arbcp6_cpxdp_grant_ca(arbcp7_cpxdp_grant_ca[@]),
.arbcp6_cpxdp_q0_hold_ca_l(arbcp7_cpxdp_q0_hold_ca_l[@]),
.arbcp6_cpxdp_qsel0_ca(arbcp7_cpxdp_qsel0_ca[@]),
.arbcp6_cpxdp_qsel1_ca_l(arbcp7_cpxdp_qsel1_ca_l[@]),
.arbcp6_cpxdp_shift_cx(arbcp7_cpxdp_shift_cx[@]),
// Inputs
.arbcp0_cpxdp_grant_arbbf_ca_l(arbcp1_cpxdp_grant_bufp1_ca_l[@]),
.arbcp0_cpxdp_q0_hold_arbbf_ca(arbcp1_cpxdp_q0_hold_bufp1_ca[@]),
.arbcp0_cpxdp_qsel0_arbbf_ca_l(arbcp1_cpxdp_qsel0_bufp1_ca_l[@]),
.arbcp0_cpxdp_qsel1_arbbf_ca(arbcp1_cpxdp_qsel1_bufp1_ca[@]),
.arbcp0_cpxdp_shift_arbbf_cx_l(arbcp1_cpxdp_shift_bufp1_cx_l[@]),
.arbcp2_cpxdp_grant_arbbf_ca_l(arbcp3_cpxdp_grant_bufp1_ca_l[@]),
.arbcp2_cpxdp_q0_hold_arbbf_ca(arbcp3_cpxdp_q0_hold_bufp1_ca[@]),
.arbcp2_cpxdp_qsel0_arbbf_ca_l(arbcp3_cpxdp_qsel0_bufp1_ca_l[@]),
.arbcp2_cpxdp_qsel1_arbbf_ca(arbcp3_cpxdp_qsel1_bufp1_ca[@]),
.arbcp2_cpxdp_shift_arbbf_cx_l(arbcp3_cpxdp_shift_bufp1_cx_l[@]),
.arbcp4_cpxdp_grant_arbbf_ca_l(arbcp5_cpxdp_grant_bufp1_ca_l[@]),
.arbcp4_cpxdp_q0_hold_arbbf_ca(arbcp5_cpxdp_q0_hold_bufp1_ca[@]),
.arbcp4_cpxdp_qsel0_arbbf_ca_l(arbcp5_cpxdp_qsel0_bufp1_ca_l[@]),
.arbcp4_cpxdp_qsel1_arbbf_ca(arbcp5_cpxdp_qsel1_bufp1_ca[@]),
.arbcp4_cpxdp_shift_arbbf_cx_l(arbcp5_cpxdp_shift_bufp1_cx_l[@]),
.arbcp6_cpxdp_grant_arbbf_ca_l(arbcp7_cpxdp_grant_bufp1_ca_l[@]),
.arbcp6_cpxdp_q0_hold_arbbf_ca(arbcp7_cpxdp_q0_hold_bufp1_ca[@]),
.arbcp6_cpxdp_qsel0_arbbf_ca_l(arbcp7_cpxdp_qsel0_bufp1_ca_l[@]),
.arbcp6_cpxdp_qsel1_arbbf_ca(arbcp7_cpxdp_qsel1_bufp1_ca[@]),
.arbcp6_cpxdp_shift_arbbf_cx_l(arbcp7_cpxdp_shift_bufp1_cx_l[@]));
*/
cpx_buf_pm_even pm1_odd(/*AUTOINST*/
// Outputs
.arbcp0_cpxdp_grant_ca(arbcp1_cpxdp_grant_ca[1]), // Templated
.arbcp0_cpxdp_q0_hold_ca_l(arbcp1_cpxdp_q0_hold_ca_l[1]), // Templated
.arbcp0_cpxdp_qsel0_ca(arbcp1_cpxdp_qsel0_ca[1]), // Templated
.arbcp0_cpxdp_qsel1_ca_l(arbcp1_cpxdp_qsel1_ca_l[1]), // Templated
.arbcp0_cpxdp_shift_cx(arbcp1_cpxdp_shift_cx[1]), // Templated
.arbcp2_cpxdp_grant_ca(arbcp3_cpxdp_grant_ca[1]), // Templated
.arbcp2_cpxdp_q0_hold_ca_l(arbcp3_cpxdp_q0_hold_ca_l[1]), // Templated
.arbcp2_cpxdp_qsel0_ca(arbcp3_cpxdp_qsel0_ca[1]), // Templated
.arbcp2_cpxdp_qsel1_ca_l(arbcp3_cpxdp_qsel1_ca_l[1]), // Templated
.arbcp2_cpxdp_shift_cx(arbcp3_cpxdp_shift_cx[1]), // Templated
.arbcp4_cpxdp_grant_ca(arbcp5_cpxdp_grant_ca[1]), // Templated
.arbcp4_cpxdp_q0_hold_ca_l(arbcp5_cpxdp_q0_hold_ca_l[1]), // Templated
.arbcp4_cpxdp_qsel0_ca(arbcp5_cpxdp_qsel0_ca[1]), // Templated
.arbcp4_cpxdp_qsel1_ca_l(arbcp5_cpxdp_qsel1_ca_l[1]), // Templated
.arbcp4_cpxdp_shift_cx(arbcp5_cpxdp_shift_cx[1]), // Templated
.arbcp6_cpxdp_grant_ca(arbcp7_cpxdp_grant_ca[1]), // Templated
.arbcp6_cpxdp_q0_hold_ca_l(arbcp7_cpxdp_q0_hold_ca_l[1]), // Templated
.arbcp6_cpxdp_qsel0_ca(arbcp7_cpxdp_qsel0_ca[1]), // Templated
.arbcp6_cpxdp_qsel1_ca_l(arbcp7_cpxdp_qsel1_ca_l[1]), // Templated
.arbcp6_cpxdp_shift_cx(arbcp7_cpxdp_shift_cx[1]), // Templated
// Inputs
.arbcp0_cpxdp_grant_arbbf_ca_l(arbcp1_cpxdp_grant_bufp1_ca_l[1]), // Templated
.arbcp0_cpxdp_q0_hold_arbbf_ca(arbcp1_cpxdp_q0_hold_bufp1_ca[1]), // Templated
.arbcp0_cpxdp_qsel0_arbbf_ca_l(arbcp1_cpxdp_qsel0_bufp1_ca_l[1]), // Templated
.arbcp0_cpxdp_qsel1_arbbf_ca(arbcp1_cpxdp_qsel1_bufp1_ca[1]), // Templated
.arbcp0_cpxdp_shift_arbbf_cx_l(arbcp1_cpxdp_shift_bufp1_cx_l[1]), // Templated
.arbcp2_cpxdp_grant_arbbf_ca_l(arbcp3_cpxdp_grant_bufp1_ca_l[1]), // Templated
.arbcp2_cpxdp_q0_hold_arbbf_ca(arbcp3_cpxdp_q0_hold_bufp1_ca[1]), // Templated
.arbcp2_cpxdp_qsel0_arbbf_ca_l(arbcp3_cpxdp_qsel0_bufp1_ca_l[1]), // Templated
.arbcp2_cpxdp_qsel1_arbbf_ca(arbcp3_cpxdp_qsel1_bufp1_ca[1]), // Templated
.arbcp2_cpxdp_shift_arbbf_cx_l(arbcp3_cpxdp_shift_bufp1_cx_l[1]), // Templated
.arbcp4_cpxdp_grant_arbbf_ca_l(arbcp5_cpxdp_grant_bufp1_ca_l[1]), // Templated
.arbcp4_cpxdp_q0_hold_arbbf_ca(arbcp5_cpxdp_q0_hold_bufp1_ca[1]), // Templated
.arbcp4_cpxdp_qsel0_arbbf_ca_l(arbcp5_cpxdp_qsel0_bufp1_ca_l[1]), // Templated
.arbcp4_cpxdp_qsel1_arbbf_ca(arbcp5_cpxdp_qsel1_bufp1_ca[1]), // Templated
.arbcp4_cpxdp_shift_arbbf_cx_l(arbcp5_cpxdp_shift_bufp1_cx_l[1]), // Templated
.arbcp6_cpxdp_grant_arbbf_ca_l(arbcp7_cpxdp_grant_bufp1_ca_l[1]), // Templated
.arbcp6_cpxdp_q0_hold_arbbf_ca(arbcp7_cpxdp_q0_hold_bufp1_ca[1]), // Templated
.arbcp6_cpxdp_qsel0_arbbf_ca_l(arbcp7_cpxdp_qsel0_bufp1_ca_l[1]), // Templated
.arbcp6_cpxdp_qsel1_arbbf_ca(arbcp7_cpxdp_qsel1_bufp1_ca[1]), // Templated
.arbcp6_cpxdp_shift_arbbf_cx_l(arbcp7_cpxdp_shift_bufp1_cx_l[1])); // Templated
/* cpx_buf_pm_even AUTO_TEMPLATE(
// Outputs
.arbcp0_cpxdp_grant_ca(arbcp1_cpxdp_grant_ca[@]),
.arbcp0_cpxdp_q0_hold_ca_l(arbcp1_cpxdp_q0_hold_ca_l[@]),
.arbcp0_cpxdp_qsel0_ca(arbcp1_cpxdp_qsel0_ca[@]),
.arbcp0_cpxdp_qsel1_ca_l(arbcp1_cpxdp_qsel1_ca_l[@]),
.arbcp0_cpxdp_shift_cx(arbcp1_cpxdp_shift_cx[@]),
.arbcp2_cpxdp_grant_ca(arbcp3_cpxdp_grant_ca[@]),
.arbcp2_cpxdp_q0_hold_ca_l(arbcp3_cpxdp_q0_hold_ca_l[@]),
.arbcp2_cpxdp_qsel0_ca(arbcp3_cpxdp_qsel0_ca[@]),
.arbcp2_cpxdp_qsel1_ca_l(arbcp3_cpxdp_qsel1_ca_l[@]),
.arbcp2_cpxdp_shift_cx(arbcp3_cpxdp_shift_cx[@]),
.arbcp4_cpxdp_grant_ca(arbcp5_cpxdp_grant_ca[@]),
.arbcp4_cpxdp_q0_hold_ca_l(arbcp5_cpxdp_q0_hold_ca_l[@]),
.arbcp4_cpxdp_qsel0_ca(arbcp5_cpxdp_qsel0_ca[@]),
.arbcp4_cpxdp_qsel1_ca_l(arbcp5_cpxdp_qsel1_ca_l[@]),
.arbcp4_cpxdp_shift_cx(arbcp5_cpxdp_shift_cx[@]),
.arbcp6_cpxdp_grant_ca(arbcp7_cpxdp_grant_ca[@]),
.arbcp6_cpxdp_q0_hold_ca_l(arbcp7_cpxdp_q0_hold_ca_l[@]),
.arbcp6_cpxdp_qsel0_ca(arbcp7_cpxdp_qsel0_ca[@]),
.arbcp6_cpxdp_qsel1_ca_l(arbcp7_cpxdp_qsel1_ca_l[@]),
.arbcp6_cpxdp_shift_cx(arbcp7_cpxdp_shift_cx[@]),
// Inputs
.arbcp0_cpxdp_grant_arbbf_ca_l(arbcp1_cpxdp_grant_bufp3_ca_l[@]),
.arbcp0_cpxdp_q0_hold_arbbf_ca(arbcp1_cpxdp_q0_hold_bufp3_ca[@]),
.arbcp0_cpxdp_qsel0_arbbf_ca_l(arbcp1_cpxdp_qsel0_bufp3_ca_l[@]),
.arbcp0_cpxdp_qsel1_arbbf_ca(arbcp1_cpxdp_qsel1_bufp3_ca[@]),
.arbcp0_cpxdp_shift_arbbf_cx_l(arbcp1_cpxdp_shift_bufp3_cx_l[@]),
.arbcp2_cpxdp_grant_arbbf_ca_l(arbcp3_cpxdp_grant_bufp3_ca_l[@]),
.arbcp2_cpxdp_q0_hold_arbbf_ca(arbcp3_cpxdp_q0_hold_bufp3_ca[@]),
.arbcp2_cpxdp_qsel0_arbbf_ca_l(arbcp3_cpxdp_qsel0_bufp3_ca_l[@]),
.arbcp2_cpxdp_qsel1_arbbf_ca(arbcp3_cpxdp_qsel1_bufp3_ca[@]),
.arbcp2_cpxdp_shift_arbbf_cx_l(arbcp3_cpxdp_shift_bufp3_cx_l[@]),
.arbcp4_cpxdp_grant_arbbf_ca_l(arbcp5_cpxdp_grant_bufp3_ca_l[@]),
.arbcp4_cpxdp_q0_hold_arbbf_ca(arbcp5_cpxdp_q0_hold_bufp3_ca[@]),
.arbcp4_cpxdp_qsel0_arbbf_ca_l(arbcp5_cpxdp_qsel0_bufp3_ca_l[@]),
.arbcp4_cpxdp_qsel1_arbbf_ca(arbcp5_cpxdp_qsel1_bufp3_ca[@]),
.arbcp4_cpxdp_shift_arbbf_cx_l(arbcp5_cpxdp_shift_bufp3_cx_l[@]),
.arbcp6_cpxdp_grant_arbbf_ca_l(arbcp7_cpxdp_grant_bufp3_ca_l[@]),
.arbcp6_cpxdp_q0_hold_arbbf_ca(arbcp7_cpxdp_q0_hold_bufp3_ca[@]),
.arbcp6_cpxdp_qsel0_arbbf_ca_l(arbcp7_cpxdp_qsel0_bufp3_ca_l[@]),
.arbcp6_cpxdp_qsel1_arbbf_ca(arbcp7_cpxdp_qsel1_bufp3_ca[@]),
.arbcp6_cpxdp_shift_arbbf_cx_l(arbcp7_cpxdp_shift_bufp3_cx_l[@]));
*/
cpx_buf_pm_even pm2_odd(/*AUTOINST*/
// Outputs
.arbcp0_cpxdp_grant_ca(arbcp1_cpxdp_grant_ca[2]), // Templated
.arbcp0_cpxdp_q0_hold_ca_l(arbcp1_cpxdp_q0_hold_ca_l[2]), // Templated
.arbcp0_cpxdp_qsel0_ca(arbcp1_cpxdp_qsel0_ca[2]), // Templated
.arbcp0_cpxdp_qsel1_ca_l(arbcp1_cpxdp_qsel1_ca_l[2]), // Templated
.arbcp0_cpxdp_shift_cx(arbcp1_cpxdp_shift_cx[2]), // Templated
.arbcp2_cpxdp_grant_ca(arbcp3_cpxdp_grant_ca[2]), // Templated
.arbcp2_cpxdp_q0_hold_ca_l(arbcp3_cpxdp_q0_hold_ca_l[2]), // Templated
.arbcp2_cpxdp_qsel0_ca(arbcp3_cpxdp_qsel0_ca[2]), // Templated
.arbcp2_cpxdp_qsel1_ca_l(arbcp3_cpxdp_qsel1_ca_l[2]), // Templated
.arbcp2_cpxdp_shift_cx(arbcp3_cpxdp_shift_cx[2]), // Templated
.arbcp4_cpxdp_grant_ca(arbcp5_cpxdp_grant_ca[2]), // Templated
.arbcp4_cpxdp_q0_hold_ca_l(arbcp5_cpxdp_q0_hold_ca_l[2]), // Templated
.arbcp4_cpxdp_qsel0_ca(arbcp5_cpxdp_qsel0_ca[2]), // Templated
.arbcp4_cpxdp_qsel1_ca_l(arbcp5_cpxdp_qsel1_ca_l[2]), // Templated
.arbcp4_cpxdp_shift_cx(arbcp5_cpxdp_shift_cx[2]), // Templated
.arbcp6_cpxdp_grant_ca(arbcp7_cpxdp_grant_ca[2]), // Templated
.arbcp6_cpxdp_q0_hold_ca_l(arbcp7_cpxdp_q0_hold_ca_l[2]), // Templated
.arbcp6_cpxdp_qsel0_ca(arbcp7_cpxdp_qsel0_ca[2]), // Templated
.arbcp6_cpxdp_qsel1_ca_l(arbcp7_cpxdp_qsel1_ca_l[2]), // Templated
.arbcp6_cpxdp_shift_cx(arbcp7_cpxdp_shift_cx[2]), // Templated
// Inputs
.arbcp0_cpxdp_grant_arbbf_ca_l(arbcp1_cpxdp_grant_bufp3_ca_l[2]), // Templated
.arbcp0_cpxdp_q0_hold_arbbf_ca(arbcp1_cpxdp_q0_hold_bufp3_ca[2]), // Templated
.arbcp0_cpxdp_qsel0_arbbf_ca_l(arbcp1_cpxdp_qsel0_bufp3_ca_l[2]), // Templated
.arbcp0_cpxdp_qsel1_arbbf_ca(arbcp1_cpxdp_qsel1_bufp3_ca[2]), // Templated
.arbcp0_cpxdp_shift_arbbf_cx_l(arbcp1_cpxdp_shift_bufp3_cx_l[2]), // Templated
.arbcp2_cpxdp_grant_arbbf_ca_l(arbcp3_cpxdp_grant_bufp3_ca_l[2]), // Templated
.arbcp2_cpxdp_q0_hold_arbbf_ca(arbcp3_cpxdp_q0_hold_bufp3_ca[2]), // Templated
.arbcp2_cpxdp_qsel0_arbbf_ca_l(arbcp3_cpxdp_qsel0_bufp3_ca_l[2]), // Templated
.arbcp2_cpxdp_qsel1_arbbf_ca(arbcp3_cpxdp_qsel1_bufp3_ca[2]), // Templated
.arbcp2_cpxdp_shift_arbbf_cx_l(arbcp3_cpxdp_shift_bufp3_cx_l[2]), // Templated
.arbcp4_cpxdp_grant_arbbf_ca_l(arbcp5_cpxdp_grant_bufp3_ca_l[2]), // Templated
.arbcp4_cpxdp_q0_hold_arbbf_ca(arbcp5_cpxdp_q0_hold_bufp3_ca[2]), // Templated
.arbcp4_cpxdp_qsel0_arbbf_ca_l(arbcp5_cpxdp_qsel0_bufp3_ca_l[2]), // Templated
.arbcp4_cpxdp_qsel1_arbbf_ca(arbcp5_cpxdp_qsel1_bufp3_ca[2]), // Templated
.arbcp4_cpxdp_shift_arbbf_cx_l(arbcp5_cpxdp_shift_bufp3_cx_l[2]), // Templated
.arbcp6_cpxdp_grant_arbbf_ca_l(arbcp7_cpxdp_grant_bufp3_ca_l[2]), // Templated
.arbcp6_cpxdp_q0_hold_arbbf_ca(arbcp7_cpxdp_q0_hold_bufp3_ca[2]), // Templated
.arbcp6_cpxdp_qsel0_arbbf_ca_l(arbcp7_cpxdp_qsel0_bufp3_ca_l[2]), // Templated
.arbcp6_cpxdp_qsel1_arbbf_ca(arbcp7_cpxdp_qsel1_bufp3_ca[2]), // Templated
.arbcp6_cpxdp_shift_arbbf_cx_l(arbcp7_cpxdp_shift_bufp3_cx_l[2])); // Templated
/*
cpx_buf_pt AUTO_TEMPLATE(
// Outputs
.out0_l (scache@_cpx_req_bufpt_cq_l[7:0]),
.out1_l (scache@_cpx_atom_bufpt_cq_l),
.cpx_src_grant_cx (cpx_scache@_grant_cx[7:0]),
.so (cpx_buf_top_pt0_so_1),
// Inputs
.se (se_buf4_top),
.in0 (scache@_cpx_req_cq[7:0]),
.in1 (scache@_cpx_atom_cq),
.cpx_src_grant_ca (cpx_scache@_grant_bufp0_ca[7:0]),
.clk (clk),
.si (pt2_so_1));
*/
cpx_buf_pt pt0(/*AUTOINST*/
// Outputs
.out0_l (scache0_cpx_req_bufpt_cq_l[7:0]), // Templated
.out1_l (scache0_cpx_atom_bufpt_cq_l), // Templated
.cpx_src_grant_cx (cpx_scache0_grant_cx[7:0]), // Templated
.so (cpx_buf_top_pt0_so_1), // Templated
// Inputs
.in0 (scache0_cpx_req_cq[7:0]), // Templated
.in1 (scache0_cpx_atom_cq), // Templated
.cpx_src_grant_ca (cpx_scache0_grant_bufp0_ca[7:0]), // Templated
.rclk (rclk),
.si (pt2_so_1), // Templated
.se (se_buf4_top)); // Templated
/*
cpx_buf_pt AUTO_TEMPLATE(
// Outputs
.out0_l (scache@_cpx_req_bufpt_cq_l[7:0]),
.out1_l (scache@_cpx_atom_bufpt_cq_l),
.cpx_src_grant_cx (cpx_scache@_grant_cx[7:0]),
.so (pt3_so_1),
// Inputs
.se (se_buf2_bottom),
.in0 (scache@_cpx_req_cq[7:0]),
.in1 (scache@_cpx_atom_cq),
.cpx_src_grant_ca (cpx_scache@_grant_bufp4_ca[7:0]),
.clk (clk),
.si (fp_so_1));
*/
cpx_buf_pt pt3(/*AUTOINST*/
// Outputs
.out0_l (scache3_cpx_req_bufpt_cq_l[7:0]), // Templated
.out1_l (scache3_cpx_atom_bufpt_cq_l), // Templated
.cpx_src_grant_cx (cpx_scache3_grant_cx[7:0]), // Templated
.so (pt3_so_1), // Templated
// Inputs
.in0 (scache3_cpx_req_cq[7:0]), // Templated
.in1 (scache3_cpx_atom_cq), // Templated
.cpx_src_grant_ca (cpx_scache3_grant_bufp4_ca[7:0]), // Templated
.rclk (rclk),
.si (fp_so_1), // Templated
.se (se_buf2_bottom)); // Templated
/*
cpx_buf_pt AUTO_TEMPLATE(
// Outputs
.out0_l (scache@_cpx_req_bufpt_cq_l[7:0]),
.out1_l (scache@_cpx_atom_bufpt_cq_l),
.cpx_src_grant_cx (cpx_scache@_grant_cx[7:0]),
.so (pt1_so_1),
// Inputs
.se (se_buf4_bottom),
.in0 (scache@_cpx_req_cq[7:0]),
.in1 (scache@_cpx_atom_cq),
.cpx_src_grant_ca (cpx_scache@_grant_bufpm_ca[7:0]),
.clk (clk),
.si (pt3_so_1));
*/
cpx_buf_pt pt1(/*AUTOINST*/
// Outputs
.out0_l (scache1_cpx_req_bufpt_cq_l[7:0]), // Templated
.out1_l (scache1_cpx_atom_bufpt_cq_l), // Templated
.cpx_src_grant_cx (cpx_scache1_grant_cx[7:0]), // Templated
.so (pt1_so_1), // Templated
// Inputs
.in0 (scache1_cpx_req_cq[7:0]), // Templated
.in1 (scache1_cpx_atom_cq), // Templated
.cpx_src_grant_ca (cpx_scache1_grant_bufpm_ca[7:0]), // Templated
.rclk (rclk),
.si (pt3_so_1), // Templated
.se (se_buf4_bottom)); // Templated
/*
cpx_buf_pt AUTO_TEMPLATE(
// Outputs
.out0_l (scache@_cpx_req_bufpt_cq_l[7:0]),
.out1_l (scache@_cpx_atom_bufpt_cq_l),
.cpx_src_grant_cx (cpx_scache@_grant_cx[7:0]),
.so (pt2_so_1),
// Inputs
.se (se_buf2_top),
.in0 (scache@_cpx_req_cq[7:0]),
.in1 (scache@_cpx_atom_cq),
.cpx_src_grant_ca (cpx_scache@_grant_bufpm_ca[7:0]),
.clk (clk),
.si (pcx_scache2_dat_px2_so_1));
*/
cpx_buf_pt pt2(/*AUTOINST*/
// Outputs
.out0_l (scache2_cpx_req_bufpt_cq_l[7:0]), // Templated
.out1_l (scache2_cpx_atom_bufpt_cq_l), // Templated
.cpx_src_grant_cx (cpx_scache2_grant_cx[7:0]), // Templated
.so (pt2_so_1), // Templated
// Inputs
.in0 (scache2_cpx_req_cq[7:0]), // Templated
.in1 (scache2_cpx_atom_cq), // Templated
.cpx_src_grant_ca (cpx_scache2_grant_bufpm_ca[7:0]), // Templated
.rclk (rclk),
.si (pcx_scache2_dat_px2_so_1), // Templated
.se (se_buf2_top)); // Templated
/*
cpx_buf_pt AUTO_TEMPLATE(
// Outputs
.out0_l (fp_cpx_req_bufpt_cq_l[7:0]),
.out1_l (),
.cpx_src_grant_cx (),
.so (fp_so_1),
// Inputs
.se (se_buf0_middle),
.in0 (fp_cpx_req_cq[7:0]),
.in1 (1'b0),
.cpx_src_grant_ca (8'h0),
.clk (clk),
.si (io_so_1));
*/
cpx_buf_pt fp(/*AUTOINST*/
// Outputs
.out0_l (fp_cpx_req_bufpt_cq_l[7:0]), // Templated
.out1_l (), // Templated
.cpx_src_grant_cx (), // Templated
.so (fp_so_1), // Templated
// Inputs
.in0 (fp_cpx_req_cq[7:0]), // Templated
.in1 (1'b0), // Templated
.cpx_src_grant_ca (8'h0), // Templated
.rclk (rclk),
.si (io_so_1), // Templated
.se (se_buf0_middle)); // Templated
/*
cpx_buf_pt AUTO_TEMPLATE(
// Outputs
.out0_l (io_cpx_req_bufpt_cq_l[7:0]),
.out1_l (),
.cpx_src_grant_cx (cpx_io_grant_cx[7:0]),
.so (io_so_1),
// Inputs
.se (se_buf3_top),
.in0 (io_cpx_req_cq2[7:0]),
.in1 (1'b0),
.cpx_src_grant_ca (cpx_io_grant_buf1_io_ca[7:0]),
.clk (clk),
.si (io_cpx_reqdata_ff_so_1));
*/
cpx_buf_pt io(/*AUTOINST*/
// Outputs
.out0_l (io_cpx_req_bufpt_cq_l[7:0]), // Templated
.out1_l (), // Templated
.cpx_src_grant_cx (cpx_io_grant_cx[7:0]), // Templated
.so (io_so_1), // Templated
// Inputs
.in0 (io_cpx_req_cq2[7:0]), // Templated
.in1 (1'b0), // Templated
.cpx_src_grant_ca (cpx_io_grant_buf1_io_ca[7:0]), // Templated
.rclk (rclk),
.si (io_cpx_reqdata_ff_so_1), // Templated
.se (se_buf3_top)); // Templated
cpx_buf_p0 p0(/*AUTOINST*/
// Outputs
.scache0_cpx_req_bufp0_cq(scache0_cpx_req_bufp0_cq[7:0]),
.scache0_cpx_atom_bufp0_cq(scache0_cpx_atom_bufp0_cq),
.cpx_scache0_grant_bufp0_ca(cpx_scache0_grant_bufp0_ca[7:0]),
.cpx_spc0_data_rdy_bufp0_cx(cpx_spc0_data_rdy_bufp0_cx),
// Inputs
.scache0_cpx_req_bufpt_cq_l(scache0_cpx_req_bufpt_cq_l[7:0]),
.scache0_cpx_atom_bufpt_cq_l(scache0_cpx_atom_bufpt_cq_l),
.cpx_scache0_grant_bufp1_ca_l(cpx_scache0_grant_bufp1_ca_l[7:0]),
.cpx_spc0_data_rdy_bufp1_cx(cpx_spc0_data_rdy_bufp1_cx));
/* cpx_buf_p0_even AUTO_TEMPLATE(
// Outputs
.arbcp0_cpxdp_grant_ca (arbcp0_cpxdp_grant_ca[0]),
.arbcp0_cpxdp_q0_hold_ca_l(arbcp0_cpxdp_q0_hold_ca_l[0]),
.arbcp0_cpxdp_qsel0_ca (arbcp0_cpxdp_qsel0_ca[0]),
.arbcp0_cpxdp_qsel1_ca_l(arbcp0_cpxdp_qsel1_ca_l[0]),
.arbcp0_cpxdp_shift_cx (arbcp0_cpxdp_shift_cx[0]),
.arbcp2_cpxdp_grant_ca (arbcp2_cpxdp_grant_ca[0]),
.arbcp2_cpxdp_q0_hold_ca_l(arbcp2_cpxdp_q0_hold_ca_l[0]),
.arbcp2_cpxdp_qsel0_ca (arbcp2_cpxdp_qsel0_ca[0]),
.arbcp2_cpxdp_qsel1_ca_l(arbcp2_cpxdp_qsel1_ca_l[0]),
.arbcp2_cpxdp_shift_cx (arbcp2_cpxdp_shift_cx[0]),
.arbcp4_cpxdp_grant_ca (arbcp4_cpxdp_grant_ca[0]),
.arbcp4_cpxdp_q0_hold_ca_l(arbcp4_cpxdp_q0_hold_ca_l[0]),
.arbcp4_cpxdp_qsel0_ca (arbcp4_cpxdp_qsel0_ca[0]),
.arbcp4_cpxdp_qsel1_ca_l(arbcp4_cpxdp_qsel1_ca_l[0]),
.arbcp4_cpxdp_shift_cx (arbcp4_cpxdp_shift_cx[0]),
.arbcp6_cpxdp_grant_ca (arbcp6_cpxdp_grant_ca[0]),
.arbcp6_cpxdp_q0_hold_ca_l(arbcp6_cpxdp_q0_hold_ca_l[0]),
.arbcp6_cpxdp_qsel0_ca (arbcp6_cpxdp_qsel0_ca[0]),
.arbcp6_cpxdp_qsel1_ca_l(arbcp6_cpxdp_qsel1_ca_l[0]),
.arbcp6_cpxdp_shift_cx (arbcp6_cpxdp_shift_cx[0]),
// Inputs
.arbcp0_cpxdp_grant_bufp1_ca_l(arbcp0_cpxdp_grant_bufp1_ca_l[0]),
.arbcp0_cpxdp_q0_hold_bufp1_ca(arbcp0_cpxdp_q0_hold_bufp1_ca[0]),
.arbcp0_cpxdp_qsel0_bufp1_ca_l(arbcp0_cpxdp_qsel0_bufp1_ca_l[0]),
.arbcp0_cpxdp_qsel1_bufp1_ca(arbcp0_cpxdp_qsel1_bufp1_ca[0]),
.arbcp0_cpxdp_shift_bufp1_cx_l(arbcp0_cpxdp_shift_bufp1_cx_l[0]),
.arbcp2_cpxdp_grant_bufp1_ca_l(arbcp2_cpxdp_grant_bufp1_ca_l[0]),
.arbcp2_cpxdp_q0_hold_bufp1_ca(arbcp2_cpxdp_q0_hold_bufp1_ca[0]),
.arbcp2_cpxdp_qsel0_bufp1_ca_l(arbcp2_cpxdp_qsel0_bufp1_ca_l[0]),
.arbcp2_cpxdp_qsel1_bufp1_ca(arbcp2_cpxdp_qsel1_bufp1_ca[0]),
.arbcp2_cpxdp_shift_bufp1_cx_l(arbcp2_cpxdp_shift_bufp1_cx_l[0]),
.arbcp4_cpxdp_grant_bufp1_ca_l(arbcp4_cpxdp_grant_bufp1_ca_l[0]),
.arbcp4_cpxdp_q0_hold_bufp1_ca(arbcp4_cpxdp_q0_hold_bufp1_ca[0]),
.arbcp4_cpxdp_qsel0_bufp1_ca_l(arbcp4_cpxdp_qsel0_bufp1_ca_l[0]),
.arbcp4_cpxdp_qsel1_bufp1_ca(arbcp4_cpxdp_qsel1_bufp1_ca[0]),
.arbcp4_cpxdp_shift_bufp1_cx_l(arbcp4_cpxdp_shift_bufp1_cx_l[0]),
.arbcp6_cpxdp_grant_bufp1_ca_l(arbcp6_cpxdp_grant_bufp1_ca_l[0]),
.arbcp6_cpxdp_q0_hold_bufp1_ca(arbcp6_cpxdp_q0_hold_bufp1_ca[0]),
.arbcp6_cpxdp_qsel0_bufp1_ca_l(arbcp6_cpxdp_qsel0_bufp1_ca_l[0]),
.arbcp6_cpxdp_qsel1_bufp1_ca(arbcp6_cpxdp_qsel1_bufp1_ca[0]),
.arbcp6_cpxdp_shift_bufp1_cx_l(arbcp6_cpxdp_shift_bufp1_cx_l[0]));
*/
cpx_buf_p0_even p0_even(/*AUTOINST*/
// Outputs
.arbcp0_cpxdp_grant_ca(arbcp0_cpxdp_grant_ca[0]), // Templated
.arbcp0_cpxdp_q0_hold_ca_l(arbcp0_cpxdp_q0_hold_ca_l[0]), // Templated
.arbcp0_cpxdp_qsel0_ca(arbcp0_cpxdp_qsel0_ca[0]), // Templated
.arbcp0_cpxdp_qsel1_ca_l(arbcp0_cpxdp_qsel1_ca_l[0]), // Templated
.arbcp0_cpxdp_shift_cx(arbcp0_cpxdp_shift_cx[0]), // Templated
.arbcp2_cpxdp_grant_ca(arbcp2_cpxdp_grant_ca[0]), // Templated
.arbcp2_cpxdp_q0_hold_ca_l(arbcp2_cpxdp_q0_hold_ca_l[0]), // Templated
.arbcp2_cpxdp_qsel0_ca(arbcp2_cpxdp_qsel0_ca[0]), // Templated
.arbcp2_cpxdp_qsel1_ca_l(arbcp2_cpxdp_qsel1_ca_l[0]), // Templated
.arbcp2_cpxdp_shift_cx(arbcp2_cpxdp_shift_cx[0]), // Templated
.arbcp4_cpxdp_grant_ca(arbcp4_cpxdp_grant_ca[0]), // Templated
.arbcp4_cpxdp_q0_hold_ca_l(arbcp4_cpxdp_q0_hold_ca_l[0]), // Templated
.arbcp4_cpxdp_qsel0_ca(arbcp4_cpxdp_qsel0_ca[0]), // Templated
.arbcp4_cpxdp_qsel1_ca_l(arbcp4_cpxdp_qsel1_ca_l[0]), // Templated
.arbcp4_cpxdp_shift_cx(arbcp4_cpxdp_shift_cx[0]), // Templated
.arbcp6_cpxdp_grant_ca(arbcp6_cpxdp_grant_ca[0]), // Templated
.arbcp6_cpxdp_q0_hold_ca_l(arbcp6_cpxdp_q0_hold_ca_l[0]), // Templated
.arbcp6_cpxdp_qsel0_ca(arbcp6_cpxdp_qsel0_ca[0]), // Templated
.arbcp6_cpxdp_qsel1_ca_l(arbcp6_cpxdp_qsel1_ca_l[0]), // Templated
.arbcp6_cpxdp_shift_cx(arbcp6_cpxdp_shift_cx[0]), // Templated
// Inputs
.arbcp0_cpxdp_grant_bufp1_ca_l(arbcp0_cpxdp_grant_bufp1_ca_l[0]), // Templated
.arbcp0_cpxdp_q0_hold_bufp1_ca(arbcp0_cpxdp_q0_hold_bufp1_ca[0]), // Templated
.arbcp0_cpxdp_qsel0_bufp1_ca_l(arbcp0_cpxdp_qsel0_bufp1_ca_l[0]), // Templated
.arbcp0_cpxdp_qsel1_bufp1_ca(arbcp0_cpxdp_qsel1_bufp1_ca[0]), // Templated
.arbcp0_cpxdp_shift_bufp1_cx_l(arbcp0_cpxdp_shift_bufp1_cx_l[0]), // Templated
.arbcp2_cpxdp_grant_bufp1_ca_l(arbcp2_cpxdp_grant_bufp1_ca_l[0]), // Templated
.arbcp2_cpxdp_q0_hold_bufp1_ca(arbcp2_cpxdp_q0_hold_bufp1_ca[0]), // Templated
.arbcp2_cpxdp_qsel0_bufp1_ca_l(arbcp2_cpxdp_qsel0_bufp1_ca_l[0]), // Templated
.arbcp2_cpxdp_qsel1_bufp1_ca(arbcp2_cpxdp_qsel1_bufp1_ca[0]), // Templated
.arbcp2_cpxdp_shift_bufp1_cx_l(arbcp2_cpxdp_shift_bufp1_cx_l[0]), // Templated
.arbcp4_cpxdp_grant_bufp1_ca_l(arbcp4_cpxdp_grant_bufp1_ca_l[0]), // Templated
.arbcp4_cpxdp_q0_hold_bufp1_ca(arbcp4_cpxdp_q0_hold_bufp1_ca[0]), // Templated
.arbcp4_cpxdp_qsel0_bufp1_ca_l(arbcp4_cpxdp_qsel0_bufp1_ca_l[0]), // Templated
.arbcp4_cpxdp_qsel1_bufp1_ca(arbcp4_cpxdp_qsel1_bufp1_ca[0]), // Templated
.arbcp4_cpxdp_shift_bufp1_cx_l(arbcp4_cpxdp_shift_bufp1_cx_l[0]), // Templated
.arbcp6_cpxdp_grant_bufp1_ca_l(arbcp6_cpxdp_grant_bufp1_ca_l[0]), // Templated
.arbcp6_cpxdp_q0_hold_bufp1_ca(arbcp6_cpxdp_q0_hold_bufp1_ca[0]), // Templated
.arbcp6_cpxdp_qsel0_bufp1_ca_l(arbcp6_cpxdp_qsel0_bufp1_ca_l[0]), // Templated
.arbcp6_cpxdp_qsel1_bufp1_ca(arbcp6_cpxdp_qsel1_bufp1_ca[0]), // Templated
.arbcp6_cpxdp_shift_bufp1_cx_l(arbcp6_cpxdp_shift_bufp1_cx_l[0])); // Templated
/* cpx_buf_p0_even AUTO_TEMPLATE(
// Outputs
.arbcp0_cpxdp_grant_ca (arbcp1_cpxdp_grant_ca[0]),
.arbcp0_cpxdp_q0_hold_ca_l(arbcp1_cpxdp_q0_hold_ca_l[0]),
.arbcp0_cpxdp_qsel0_ca (arbcp1_cpxdp_qsel0_ca[0]),
.arbcp0_cpxdp_qsel1_ca_l(arbcp1_cpxdp_qsel1_ca_l[0]),
.arbcp0_cpxdp_shift_cx (arbcp1_cpxdp_shift_cx[0]),
.arbcp2_cpxdp_grant_ca (arbcp3_cpxdp_grant_ca[0]),
.arbcp2_cpxdp_q0_hold_ca_l(arbcp3_cpxdp_q0_hold_ca_l[0]),
.arbcp2_cpxdp_qsel0_ca (arbcp3_cpxdp_qsel0_ca[0]),
.arbcp2_cpxdp_qsel1_ca_l(arbcp3_cpxdp_qsel1_ca_l[0]),
.arbcp2_cpxdp_shift_cx (arbcp3_cpxdp_shift_cx[0]),
.arbcp4_cpxdp_grant_ca (arbcp5_cpxdp_grant_ca[0]),
.arbcp4_cpxdp_q0_hold_ca_l(arbcp5_cpxdp_q0_hold_ca_l[0]),
.arbcp4_cpxdp_qsel0_ca (arbcp5_cpxdp_qsel0_ca[0]),
.arbcp4_cpxdp_qsel1_ca_l(arbcp5_cpxdp_qsel1_ca_l[0]),
.arbcp4_cpxdp_shift_cx (arbcp5_cpxdp_shift_cx[0]),
.arbcp6_cpxdp_grant_ca (arbcp7_cpxdp_grant_ca[0]),
.arbcp6_cpxdp_q0_hold_ca_l(arbcp7_cpxdp_q0_hold_ca_l[0]),
.arbcp6_cpxdp_qsel0_ca (arbcp7_cpxdp_qsel0_ca[0]),
.arbcp6_cpxdp_qsel1_ca_l(arbcp7_cpxdp_qsel1_ca_l[0]),
.arbcp6_cpxdp_shift_cx (arbcp7_cpxdp_shift_cx[0]),
// Inputs
.arbcp0_cpxdp_grant_bufp1_ca_l(arbcp1_cpxdp_grant_bufp1_ca_l[0]),
.arbcp0_cpxdp_q0_hold_bufp1_ca(arbcp1_cpxdp_q0_hold_bufp1_ca[0]),
.arbcp0_cpxdp_qsel0_bufp1_ca_l(arbcp1_cpxdp_qsel0_bufp1_ca_l[0]),
.arbcp0_cpxdp_qsel1_bufp1_ca(arbcp1_cpxdp_qsel1_bufp1_ca[0]),
.arbcp0_cpxdp_shift_bufp1_cx_l(arbcp1_cpxdp_shift_bufp1_cx_l[0]),
.arbcp2_cpxdp_grant_bufp1_ca_l(arbcp3_cpxdp_grant_bufp1_ca_l[0]),
.arbcp2_cpxdp_q0_hold_bufp1_ca(arbcp3_cpxdp_q0_hold_bufp1_ca[0]),
.arbcp2_cpxdp_qsel0_bufp1_ca_l(arbcp3_cpxdp_qsel0_bufp1_ca_l[0]),
.arbcp2_cpxdp_qsel1_bufp1_ca(arbcp3_cpxdp_qsel1_bufp1_ca[0]),
.arbcp2_cpxdp_shift_bufp1_cx_l(arbcp3_cpxdp_shift_bufp1_cx_l[0]),
.arbcp4_cpxdp_grant_bufp1_ca_l(arbcp5_cpxdp_grant_bufp1_ca_l[0]),
.arbcp4_cpxdp_q0_hold_bufp1_ca(arbcp5_cpxdp_q0_hold_bufp1_ca[0]),
.arbcp4_cpxdp_qsel0_bufp1_ca_l(arbcp5_cpxdp_qsel0_bufp1_ca_l[0]),
.arbcp4_cpxdp_qsel1_bufp1_ca(arbcp5_cpxdp_qsel1_bufp1_ca[0]),
.arbcp4_cpxdp_shift_bufp1_cx_l(arbcp5_cpxdp_shift_bufp1_cx_l[0]),
.arbcp6_cpxdp_grant_bufp1_ca_l(arbcp7_cpxdp_grant_bufp1_ca_l[0]),
.arbcp6_cpxdp_q0_hold_bufp1_ca(arbcp7_cpxdp_q0_hold_bufp1_ca[0]),
.arbcp6_cpxdp_qsel0_bufp1_ca_l(arbcp7_cpxdp_qsel0_bufp1_ca_l[0]),
.arbcp6_cpxdp_qsel1_bufp1_ca(arbcp7_cpxdp_qsel1_bufp1_ca[0]),
.arbcp6_cpxdp_shift_bufp1_cx_l(arbcp7_cpxdp_shift_bufp1_cx_l[0]));
*/
cpx_buf_p0_even p0_odd(/*AUTOINST*/
// Outputs
.arbcp0_cpxdp_grant_ca(arbcp1_cpxdp_grant_ca[0]), // Templated
.arbcp0_cpxdp_q0_hold_ca_l(arbcp1_cpxdp_q0_hold_ca_l[0]), // Templated
.arbcp0_cpxdp_qsel0_ca(arbcp1_cpxdp_qsel0_ca[0]), // Templated
.arbcp0_cpxdp_qsel1_ca_l(arbcp1_cpxdp_qsel1_ca_l[0]), // Templated
.arbcp0_cpxdp_shift_cx(arbcp1_cpxdp_shift_cx[0]), // Templated
.arbcp2_cpxdp_grant_ca(arbcp3_cpxdp_grant_ca[0]), // Templated
.arbcp2_cpxdp_q0_hold_ca_l(arbcp3_cpxdp_q0_hold_ca_l[0]), // Templated
.arbcp2_cpxdp_qsel0_ca(arbcp3_cpxdp_qsel0_ca[0]), // Templated
.arbcp2_cpxdp_qsel1_ca_l(arbcp3_cpxdp_qsel1_ca_l[0]), // Templated
.arbcp2_cpxdp_shift_cx(arbcp3_cpxdp_shift_cx[0]), // Templated
.arbcp4_cpxdp_grant_ca(arbcp5_cpxdp_grant_ca[0]), // Templated
.arbcp4_cpxdp_q0_hold_ca_l(arbcp5_cpxdp_q0_hold_ca_l[0]), // Templated
.arbcp4_cpxdp_qsel0_ca(arbcp5_cpxdp_qsel0_ca[0]), // Templated
.arbcp4_cpxdp_qsel1_ca_l(arbcp5_cpxdp_qsel1_ca_l[0]), // Templated
.arbcp4_cpxdp_shift_cx(arbcp5_cpxdp_shift_cx[0]), // Templated
.arbcp6_cpxdp_grant_ca(arbcp7_cpxdp_grant_ca[0]), // Templated
.arbcp6_cpxdp_q0_hold_ca_l(arbcp7_cpxdp_q0_hold_ca_l[0]), // Templated
.arbcp6_cpxdp_qsel0_ca(arbcp7_cpxdp_qsel0_ca[0]), // Templated
.arbcp6_cpxdp_qsel1_ca_l(arbcp7_cpxdp_qsel1_ca_l[0]), // Templated
.arbcp6_cpxdp_shift_cx(arbcp7_cpxdp_shift_cx[0]), // Templated
// Inputs
.arbcp0_cpxdp_grant_bufp1_ca_l(arbcp1_cpxdp_grant_bufp1_ca_l[0]), // Templated
.arbcp0_cpxdp_q0_hold_bufp1_ca(arbcp1_cpxdp_q0_hold_bufp1_ca[0]), // Templated
.arbcp0_cpxdp_qsel0_bufp1_ca_l(arbcp1_cpxdp_qsel0_bufp1_ca_l[0]), // Templated
.arbcp0_cpxdp_qsel1_bufp1_ca(arbcp1_cpxdp_qsel1_bufp1_ca[0]), // Templated
.arbcp0_cpxdp_shift_bufp1_cx_l(arbcp1_cpxdp_shift_bufp1_cx_l[0]), // Templated
.arbcp2_cpxdp_grant_bufp1_ca_l(arbcp3_cpxdp_grant_bufp1_ca_l[0]), // Templated
.arbcp2_cpxdp_q0_hold_bufp1_ca(arbcp3_cpxdp_q0_hold_bufp1_ca[0]), // Templated
.arbcp2_cpxdp_qsel0_bufp1_ca_l(arbcp3_cpxdp_qsel0_bufp1_ca_l[0]), // Templated
.arbcp2_cpxdp_qsel1_bufp1_ca(arbcp3_cpxdp_qsel1_bufp1_ca[0]), // Templated
.arbcp2_cpxdp_shift_bufp1_cx_l(arbcp3_cpxdp_shift_bufp1_cx_l[0]), // Templated
.arbcp4_cpxdp_grant_bufp1_ca_l(arbcp5_cpxdp_grant_bufp1_ca_l[0]), // Templated
.arbcp4_cpxdp_q0_hold_bufp1_ca(arbcp5_cpxdp_q0_hold_bufp1_ca[0]), // Templated
.arbcp4_cpxdp_qsel0_bufp1_ca_l(arbcp5_cpxdp_qsel0_bufp1_ca_l[0]), // Templated
.arbcp4_cpxdp_qsel1_bufp1_ca(arbcp5_cpxdp_qsel1_bufp1_ca[0]), // Templated
.arbcp4_cpxdp_shift_bufp1_cx_l(arbcp5_cpxdp_shift_bufp1_cx_l[0]), // Templated
.arbcp6_cpxdp_grant_bufp1_ca_l(arbcp7_cpxdp_grant_bufp1_ca_l[0]), // Templated
.arbcp6_cpxdp_q0_hold_bufp1_ca(arbcp7_cpxdp_q0_hold_bufp1_ca[0]), // Templated
.arbcp6_cpxdp_qsel0_bufp1_ca_l(arbcp7_cpxdp_qsel0_bufp1_ca_l[0]), // Templated
.arbcp6_cpxdp_qsel1_bufp1_ca(arbcp7_cpxdp_qsel1_bufp1_ca[0]), // Templated
.arbcp6_cpxdp_shift_bufp1_cx_l(arbcp7_cpxdp_shift_bufp1_cx_l[0])); // Templated
/* cpx_buf_p1 AUTO_TEMPLATE(
// Outputs
.arbcp0_cpxdp_grant_bufp1_ca_l_0(arbcp0_cpxdp_grant_bufp1_ca_l[0]),
.arbcp0_cpxdp_q0_hold_bufp1_ca_0(arbcp0_cpxdp_q0_hold_bufp1_ca[0]),
.arbcp0_cpxdp_qsel0_bufp1_ca_l_0(arbcp0_cpxdp_qsel0_bufp1_ca_l[0]),
.arbcp0_cpxdp_qsel1_bufp1_ca_0(arbcp0_cpxdp_qsel1_bufp1_ca[0]),
.arbcp0_cpxdp_shift_bufp1_cx_l_0(arbcp0_cpxdp_shift_bufp1_cx_l[0]),
.arbcp1_cpxdp_grant_bufp1_ca_l_0(arbcp1_cpxdp_grant_bufp1_ca_l[0]),
.arbcp1_cpxdp_q0_hold_bufp1_ca_0(arbcp1_cpxdp_q0_hold_bufp1_ca[0]),
.arbcp1_cpxdp_qsel0_bufp1_ca_l_0(arbcp1_cpxdp_qsel0_bufp1_ca_l[0]),
.arbcp1_cpxdp_qsel1_bufp1_ca_0(arbcp1_cpxdp_qsel1_bufp1_ca[0]),
.arbcp1_cpxdp_shift_bufp1_cx_l_0(arbcp1_cpxdp_shift_bufp1_cx_l[0]),
.arbcp2_cpxdp_grant_bufp1_ca_l_0(arbcp2_cpxdp_grant_bufp1_ca_l[0]),
.arbcp2_cpxdp_q0_hold_bufp1_ca_0(arbcp2_cpxdp_q0_hold_bufp1_ca[0]),
.arbcp2_cpxdp_qsel0_bufp1_ca_l_0(arbcp2_cpxdp_qsel0_bufp1_ca_l[0]),
.arbcp2_cpxdp_qsel1_bufp1_ca_0(arbcp2_cpxdp_qsel1_bufp1_ca[0]),
.arbcp2_cpxdp_shift_bufp1_cx_l_0(arbcp2_cpxdp_shift_bufp1_cx_l[0]),
.arbcp3_cpxdp_grant_bufp1_ca_l_0(arbcp3_cpxdp_grant_bufp1_ca_l[0]),
.arbcp3_cpxdp_q0_hold_bufp1_ca_0(arbcp3_cpxdp_q0_hold_bufp1_ca[0]),
.arbcp3_cpxdp_qsel0_bufp1_ca_l_0(arbcp3_cpxdp_qsel0_bufp1_ca_l[0]),
.arbcp3_cpxdp_qsel1_bufp1_ca_0(arbcp3_cpxdp_qsel1_bufp1_ca[0]),
.arbcp3_cpxdp_shift_bufp1_cx_l_0(arbcp3_cpxdp_shift_bufp1_cx_l[0]),
.arbcp4_cpxdp_grant_bufp1_ca_l_0(arbcp4_cpxdp_grant_bufp1_ca_l[0]),
.arbcp4_cpxdp_q0_hold_bufp1_ca_0(arbcp4_cpxdp_q0_hold_bufp1_ca[0]),
.arbcp4_cpxdp_qsel0_bufp1_ca_l_0(arbcp4_cpxdp_qsel0_bufp1_ca_l[0]),
.arbcp4_cpxdp_qsel1_bufp1_ca_0(arbcp4_cpxdp_qsel1_bufp1_ca[0]),
.arbcp4_cpxdp_shift_bufp1_cx_l_0(arbcp4_cpxdp_shift_bufp1_cx_l[0]),
.arbcp5_cpxdp_grant_bufp1_ca_l_0(arbcp5_cpxdp_grant_bufp1_ca_l[0]),
.arbcp5_cpxdp_q0_hold_bufp1_ca_0(arbcp5_cpxdp_q0_hold_bufp1_ca[0]),
.arbcp5_cpxdp_qsel0_bufp1_ca_l_0(arbcp5_cpxdp_qsel0_bufp1_ca_l[0]),
.arbcp5_cpxdp_qsel1_bufp1_ca_0(arbcp5_cpxdp_qsel1_bufp1_ca[0]),
.arbcp5_cpxdp_shift_bufp1_cx_l_0(arbcp5_cpxdp_shift_bufp1_cx_l[0]),
.arbcp6_cpxdp_grant_bufp1_ca_l_0(arbcp6_cpxdp_grant_bufp1_ca_l[0]),
.arbcp6_cpxdp_q0_hold_bufp1_ca_0(arbcp6_cpxdp_q0_hold_bufp1_ca[0]),
.arbcp6_cpxdp_qsel0_bufp1_ca_l_0(arbcp6_cpxdp_qsel0_bufp1_ca_l[0]),
.arbcp6_cpxdp_qsel1_bufp1_ca_0(arbcp6_cpxdp_qsel1_bufp1_ca[0]),
.arbcp6_cpxdp_shift_bufp1_cx_l_0(arbcp6_cpxdp_shift_bufp1_cx_l[0]),
.arbcp7_cpxdp_grant_bufp1_ca_l_0(arbcp7_cpxdp_grant_bufp1_ca_l[0]),
.arbcp7_cpxdp_q0_hold_bufp1_ca_0(arbcp7_cpxdp_q0_hold_bufp1_ca[0]),
.arbcp7_cpxdp_qsel0_bufp1_ca_l_0(arbcp7_cpxdp_qsel0_bufp1_ca_l[0]),
.arbcp7_cpxdp_qsel1_bufp1_ca_0(arbcp7_cpxdp_qsel1_bufp1_ca[0]),
.arbcp7_cpxdp_shift_bufp1_cx_l_0(arbcp7_cpxdp_shift_bufp1_cx_l[0]),
.arbcp0_cpxdp_grant_bufp1_ca_l_1(arbcp0_cpxdp_grant_bufp1_ca_l[1]),
.arbcp0_cpxdp_q0_hold_bufp1_ca_1(arbcp0_cpxdp_q0_hold_bufp1_ca[1]),
.arbcp0_cpxdp_qsel0_bufp1_ca_l_1(arbcp0_cpxdp_qsel0_bufp1_ca_l[1]),
.arbcp0_cpxdp_qsel1_bufp1_ca_1(arbcp0_cpxdp_qsel1_bufp1_ca[1]),
.arbcp0_cpxdp_shift_bufp1_cx_l_1(arbcp0_cpxdp_shift_bufp1_cx_l[1]),
.arbcp1_cpxdp_grant_bufp1_ca_l_1(arbcp1_cpxdp_grant_bufp1_ca_l[1]),
.arbcp1_cpxdp_q0_hold_bufp1_ca_1(arbcp1_cpxdp_q0_hold_bufp1_ca[1]),
.arbcp1_cpxdp_qsel0_bufp1_ca_l_1(arbcp1_cpxdp_qsel0_bufp1_ca_l[1]),
.arbcp1_cpxdp_qsel1_bufp1_ca_1(arbcp1_cpxdp_qsel1_bufp1_ca[1]),
.arbcp1_cpxdp_shift_bufp1_cx_l_1(arbcp1_cpxdp_shift_bufp1_cx_l[1]),
.arbcp2_cpxdp_grant_bufp1_ca_l_1(arbcp2_cpxdp_grant_bufp1_ca_l[1]),
.arbcp2_cpxdp_q0_hold_bufp1_ca_1(arbcp2_cpxdp_q0_hold_bufp1_ca[1]),
.arbcp2_cpxdp_qsel0_bufp1_ca_l_1(arbcp2_cpxdp_qsel0_bufp1_ca_l[1]),
.arbcp2_cpxdp_qsel1_bufp1_ca_1(arbcp2_cpxdp_qsel1_bufp1_ca[1]),
.arbcp2_cpxdp_shift_bufp1_cx_l_1(arbcp2_cpxdp_shift_bufp1_cx_l[1]),
.arbcp3_cpxdp_grant_bufp1_ca_l_1(arbcp3_cpxdp_grant_bufp1_ca_l[1]),
.arbcp3_cpxdp_q0_hold_bufp1_ca_1(arbcp3_cpxdp_q0_hold_bufp1_ca[1]),
.arbcp3_cpxdp_qsel0_bufp1_ca_l_1(arbcp3_cpxdp_qsel0_bufp1_ca_l[1]),
.arbcp3_cpxdp_qsel1_bufp1_ca_1(arbcp3_cpxdp_qsel1_bufp1_ca[1]),
.arbcp3_cpxdp_shift_bufp1_cx_l_1(arbcp3_cpxdp_shift_bufp1_cx_l[1]),
.arbcp4_cpxdp_grant_bufp1_ca_l_1(arbcp4_cpxdp_grant_bufp1_ca_l[1]),
.arbcp4_cpxdp_q0_hold_bufp1_ca_1(arbcp4_cpxdp_q0_hold_bufp1_ca[1]),
.arbcp4_cpxdp_qsel0_bufp1_ca_l_1(arbcp4_cpxdp_qsel0_bufp1_ca_l[1]),
.arbcp4_cpxdp_qsel1_bufp1_ca_1(arbcp4_cpxdp_qsel1_bufp1_ca[1]),
.arbcp4_cpxdp_shift_bufp1_cx_l_1(arbcp4_cpxdp_shift_bufp1_cx_l[1]),
.arbcp5_cpxdp_grant_bufp1_ca_l_1(arbcp5_cpxdp_grant_bufp1_ca_l[1]),
.arbcp5_cpxdp_q0_hold_bufp1_ca_1(arbcp5_cpxdp_q0_hold_bufp1_ca[1]),
.arbcp5_cpxdp_qsel0_bufp1_ca_l_1(arbcp5_cpxdp_qsel0_bufp1_ca_l[1]),
.arbcp5_cpxdp_qsel1_bufp1_ca_1(arbcp5_cpxdp_qsel1_bufp1_ca[1]),
.arbcp5_cpxdp_shift_bufp1_cx_l_1(arbcp5_cpxdp_shift_bufp1_cx_l[1]),
.arbcp6_cpxdp_grant_bufp1_ca_l_1(arbcp6_cpxdp_grant_bufp1_ca_l[1]),
.arbcp6_cpxdp_q0_hold_bufp1_ca_1(arbcp6_cpxdp_q0_hold_bufp1_ca[1]),
.arbcp6_cpxdp_qsel0_bufp1_ca_l_1(arbcp6_cpxdp_qsel0_bufp1_ca_l[1]),
.arbcp6_cpxdp_qsel1_bufp1_ca_1(arbcp6_cpxdp_qsel1_bufp1_ca[1]),
.arbcp6_cpxdp_shift_bufp1_cx_l_1(arbcp6_cpxdp_shift_bufp1_cx_l[1]),
.arbcp7_cpxdp_grant_bufp1_ca_l_1(arbcp7_cpxdp_grant_bufp1_ca_l[1]),
.arbcp7_cpxdp_q0_hold_bufp1_ca_1(arbcp7_cpxdp_q0_hold_bufp1_ca[1]),
.arbcp7_cpxdp_qsel0_bufp1_ca_l_1(arbcp7_cpxdp_qsel0_bufp1_ca_l[1]),
.arbcp7_cpxdp_qsel1_bufp1_ca_1(arbcp7_cpxdp_qsel1_bufp1_ca[1]),
.arbcp7_cpxdp_shift_bufp1_cx_l_1(arbcp7_cpxdp_shift_bufp1_cx_l[1]),
// Inputs
.arbcp0_cpxdp_grant_arbbf_ca_0(arbcp0_cpxdp_grant_arbbf_ca[0]),
.arbcp0_cpxdp_q0_hold_arbbf_ca_l_0(arbcp0_cpxdp_q0_hold_arbbf_ca_l[0]),
.arbcp0_cpxdp_qsel0_arbbf_ca_0(arbcp0_cpxdp_qsel0_arbbf_ca[0]),
.arbcp0_cpxdp_qsel1_arbbf_ca_l_0(arbcp0_cpxdp_qsel1_arbbf_ca_l[0]),
.arbcp0_cpxdp_shift_arbbf_cx_0(arbcp0_cpxdp_shift_arbbf_cx[0]),
.arbcp1_cpxdp_grant_arbbf_ca_0(arbcp1_cpxdp_grant_arbbf_ca[0]),
.arbcp1_cpxdp_q0_hold_arbbf_ca_l_0(arbcp1_cpxdp_q0_hold_arbbf_ca_l[0]),
.arbcp1_cpxdp_qsel0_arbbf_ca_0(arbcp1_cpxdp_qsel0_arbbf_ca[0]),
.arbcp1_cpxdp_qsel1_arbbf_ca_l_0(arbcp1_cpxdp_qsel1_arbbf_ca_l[0]),
.arbcp1_cpxdp_shift_arbbf_cx_0(arbcp1_cpxdp_shift_arbbf_cx[0]),
.arbcp2_cpxdp_grant_arbbf_ca_0(arbcp2_cpxdp_grant_arbbf_ca[0]),
.arbcp2_cpxdp_q0_hold_arbbf_ca_l_0(arbcp2_cpxdp_q0_hold_arbbf_ca_l[0]),
.arbcp2_cpxdp_qsel0_arbbf_ca_0(arbcp2_cpxdp_qsel0_arbbf_ca[0]),
.arbcp2_cpxdp_qsel1_arbbf_ca_l_0(arbcp2_cpxdp_qsel1_arbbf_ca_l[0]),
.arbcp2_cpxdp_shift_arbbf_cx_0(arbcp2_cpxdp_shift_arbbf_cx[0]),
.arbcp3_cpxdp_grant_arbbf_ca_0(arbcp3_cpxdp_grant_arbbf_ca[0]),
.arbcp3_cpxdp_q0_hold_arbbf_ca_l_0(arbcp3_cpxdp_q0_hold_arbbf_ca_l[0]),
.arbcp3_cpxdp_qsel0_arbbf_ca_0(arbcp3_cpxdp_qsel0_arbbf_ca[0]),
.arbcp3_cpxdp_qsel1_arbbf_ca_l_0(arbcp3_cpxdp_qsel1_arbbf_ca_l[0]),
.arbcp3_cpxdp_shift_arbbf_cx_0(arbcp3_cpxdp_shift_arbbf_cx[0]),
.arbcp4_cpxdp_grant_arbbf_ca_0(arbcp4_cpxdp_grant_arbbf_ca[0]),
.arbcp4_cpxdp_q0_hold_arbbf_ca_l_0(arbcp4_cpxdp_q0_hold_arbbf_ca_l[0]),
.arbcp4_cpxdp_qsel0_arbbf_ca_0(arbcp4_cpxdp_qsel0_arbbf_ca[0]),
.arbcp4_cpxdp_qsel1_arbbf_ca_l_0(arbcp4_cpxdp_qsel1_arbbf_ca_l[0]),
.arbcp4_cpxdp_shift_arbbf_cx_0(arbcp4_cpxdp_shift_arbbf_cx[0]),
.arbcp5_cpxdp_grant_arbbf_ca_0(arbcp5_cpxdp_grant_arbbf_ca[0]),
.arbcp5_cpxdp_q0_hold_arbbf_ca_l_0(arbcp5_cpxdp_q0_hold_arbbf_ca_l[0]),
.arbcp5_cpxdp_qsel0_arbbf_ca_0(arbcp5_cpxdp_qsel0_arbbf_ca[0]),
.arbcp5_cpxdp_qsel1_arbbf_ca_l_0(arbcp5_cpxdp_qsel1_arbbf_ca_l[0]),
.arbcp5_cpxdp_shift_arbbf_cx_0(arbcp5_cpxdp_shift_arbbf_cx[0]),
.arbcp6_cpxdp_grant_arbbf_ca_0(arbcp6_cpxdp_grant_arbbf_ca[0]),
.arbcp6_cpxdp_q0_hold_arbbf_ca_l_0(arbcp6_cpxdp_q0_hold_arbbf_ca_l[0]),
.arbcp6_cpxdp_qsel0_arbbf_ca_0(arbcp6_cpxdp_qsel0_arbbf_ca[0]),
.arbcp6_cpxdp_qsel1_arbbf_ca_l_0(arbcp6_cpxdp_qsel1_arbbf_ca_l[0]),
.arbcp6_cpxdp_shift_arbbf_cx_0(arbcp6_cpxdp_shift_arbbf_cx[0]),
.arbcp7_cpxdp_grant_arbbf_ca_0(arbcp7_cpxdp_grant_arbbf_ca[0]),
.arbcp7_cpxdp_q0_hold_arbbf_ca_l_0(arbcp7_cpxdp_q0_hold_arbbf_ca_l[0]),
.arbcp7_cpxdp_qsel0_arbbf_ca_0(arbcp7_cpxdp_qsel0_arbbf_ca[0]),
.arbcp7_cpxdp_qsel1_arbbf_ca_l_0(arbcp7_cpxdp_qsel1_arbbf_ca_l[0]),
.arbcp7_cpxdp_shift_arbbf_cx_0(arbcp7_cpxdp_shift_arbbf_cx[0]),
.arbcp0_cpxdp_grant_arbbf_ca_1(arbcp0_cpxdp_grant_arbbf_ca[1]),
.arbcp0_cpxdp_q0_hold_arbbf_ca_l_1(arbcp0_cpxdp_q0_hold_arbbf_ca_l[1]),
.arbcp0_cpxdp_qsel0_arbbf_ca_1(arbcp0_cpxdp_qsel0_arbbf_ca[1]),
.arbcp0_cpxdp_qsel1_arbbf_ca_l_1(arbcp0_cpxdp_qsel1_arbbf_ca_l[1]),
.arbcp0_cpxdp_shift_arbbf_cx_1(arbcp0_cpxdp_shift_arbbf_cx[1]),
.arbcp1_cpxdp_grant_arbbf_ca_1(arbcp1_cpxdp_grant_arbbf_ca[1]),
.arbcp1_cpxdp_q0_hold_arbbf_ca_l_1(arbcp1_cpxdp_q0_hold_arbbf_ca_l[1]),
.arbcp1_cpxdp_qsel0_arbbf_ca_1(arbcp1_cpxdp_qsel0_arbbf_ca[1]),
.arbcp1_cpxdp_qsel1_arbbf_ca_l_1(arbcp1_cpxdp_qsel1_arbbf_ca_l[1]),
.arbcp1_cpxdp_shift_arbbf_cx_1(arbcp1_cpxdp_shift_arbbf_cx[1]),
.arbcp2_cpxdp_grant_arbbf_ca_1(arbcp2_cpxdp_grant_arbbf_ca[1]),
.arbcp2_cpxdp_q0_hold_arbbf_ca_l_1(arbcp2_cpxdp_q0_hold_arbbf_ca_l[1]),
.arbcp2_cpxdp_qsel0_arbbf_ca_1(arbcp2_cpxdp_qsel0_arbbf_ca[1]),
.arbcp2_cpxdp_qsel1_arbbf_ca_l_1(arbcp2_cpxdp_qsel1_arbbf_ca_l[1]),
.arbcp2_cpxdp_shift_arbbf_cx_1(arbcp2_cpxdp_shift_arbbf_cx[1]),
.arbcp3_cpxdp_grant_arbbf_ca_1(arbcp3_cpxdp_grant_arbbf_ca[1]),
.arbcp3_cpxdp_q0_hold_arbbf_ca_l_1(arbcp3_cpxdp_q0_hold_arbbf_ca_l[1]),
.arbcp3_cpxdp_qsel0_arbbf_ca_1(arbcp3_cpxdp_qsel0_arbbf_ca[1]),
.arbcp3_cpxdp_qsel1_arbbf_ca_l_1(arbcp3_cpxdp_qsel1_arbbf_ca_l[1]),
.arbcp3_cpxdp_shift_arbbf_cx_1(arbcp3_cpxdp_shift_arbbf_cx[1]),
.arbcp4_cpxdp_grant_arbbf_ca_1(arbcp4_cpxdp_grant_arbbf_ca[1]),
.arbcp4_cpxdp_q0_hold_arbbf_ca_l_1(arbcp4_cpxdp_q0_hold_arbbf_ca_l[1]),
.arbcp4_cpxdp_qsel0_arbbf_ca_1(arbcp4_cpxdp_qsel0_arbbf_ca[1]),
.arbcp4_cpxdp_qsel1_arbbf_ca_l_1(arbcp4_cpxdp_qsel1_arbbf_ca_l[1]),
.arbcp4_cpxdp_shift_arbbf_cx_1(arbcp4_cpxdp_shift_arbbf_cx[1]),
.arbcp5_cpxdp_grant_arbbf_ca_1(arbcp5_cpxdp_grant_arbbf_ca[1]),
.arbcp5_cpxdp_q0_hold_arbbf_ca_l_1(arbcp5_cpxdp_q0_hold_arbbf_ca_l[1]),
.arbcp5_cpxdp_qsel0_arbbf_ca_1(arbcp5_cpxdp_qsel0_arbbf_ca[1]),
.arbcp5_cpxdp_qsel1_arbbf_ca_l_1(arbcp5_cpxdp_qsel1_arbbf_ca_l[1]),
.arbcp5_cpxdp_shift_arbbf_cx_1(arbcp5_cpxdp_shift_arbbf_cx[1]),
.arbcp6_cpxdp_grant_arbbf_ca_1(arbcp6_cpxdp_grant_arbbf_ca[1]),
.arbcp6_cpxdp_q0_hold_arbbf_ca_l_1(arbcp6_cpxdp_q0_hold_arbbf_ca_l[1]),
.arbcp6_cpxdp_qsel0_arbbf_ca_1(arbcp6_cpxdp_qsel0_arbbf_ca[1]),
.arbcp6_cpxdp_qsel1_arbbf_ca_l_1(arbcp6_cpxdp_qsel1_arbbf_ca_l[1]),
.arbcp6_cpxdp_shift_arbbf_cx_1(arbcp6_cpxdp_shift_arbbf_cx[1]),
.arbcp7_cpxdp_grant_arbbf_ca_1(arbcp7_cpxdp_grant_arbbf_ca[1]),
.arbcp7_cpxdp_q0_hold_arbbf_ca_l_1(arbcp7_cpxdp_q0_hold_arbbf_ca_l[1]),
.arbcp7_cpxdp_qsel0_arbbf_ca_1(arbcp7_cpxdp_qsel0_arbbf_ca[1]),
.arbcp7_cpxdp_qsel1_arbbf_ca_l_1(arbcp7_cpxdp_qsel1_arbbf_ca_l[1]),
.arbcp7_cpxdp_shift_arbbf_cx_1(arbcp7_cpxdp_shift_arbbf_cx[1]));
*/
cpx_buf_p1 p1(/*AUTOINST*/
// Outputs
.scache0_cpx_req_bufp1_cq(scache0_cpx_req_bufp1_cq[7:0]),
.scache0_cpx_atom_bufp1_cq(scache0_cpx_atom_bufp1_cq),
.cpx_scache0_grant_bufp1_ca_l(cpx_scache0_grant_bufp1_ca_l[7:0]),
.cpx_spc0_data_rdy_bufp1_cx(cpx_spc0_data_rdy_bufp1_cx),
.cpx_spc1_data_rdy_bufp1_cx(cpx_spc1_data_rdy_bufp1_cx),
.cpx_spc2_data_rdy_bufp1_cx(cpx_spc2_data_rdy_bufp1_cx),
.arbcp0_cpxdp_grant_bufp1_ca_l_0(arbcp0_cpxdp_grant_bufp1_ca_l[0]), // Templated
.arbcp0_cpxdp_q0_hold_bufp1_ca_0(arbcp0_cpxdp_q0_hold_bufp1_ca[0]), // Templated
.arbcp0_cpxdp_qsel0_bufp1_ca_l_0(arbcp0_cpxdp_qsel0_bufp1_ca_l[0]), // Templated
.arbcp0_cpxdp_qsel1_bufp1_ca_0(arbcp0_cpxdp_qsel1_bufp1_ca[0]), // Templated
.arbcp0_cpxdp_shift_bufp1_cx_l_0(arbcp0_cpxdp_shift_bufp1_cx_l[0]), // Templated
.arbcp1_cpxdp_grant_bufp1_ca_l_0(arbcp1_cpxdp_grant_bufp1_ca_l[0]), // Templated
.arbcp1_cpxdp_q0_hold_bufp1_ca_0(arbcp1_cpxdp_q0_hold_bufp1_ca[0]), // Templated
.arbcp1_cpxdp_qsel0_bufp1_ca_l_0(arbcp1_cpxdp_qsel0_bufp1_ca_l[0]), // Templated
.arbcp1_cpxdp_qsel1_bufp1_ca_0(arbcp1_cpxdp_qsel1_bufp1_ca[0]), // Templated
.arbcp1_cpxdp_shift_bufp1_cx_l_0(arbcp1_cpxdp_shift_bufp1_cx_l[0]), // Templated
.arbcp2_cpxdp_grant_bufp1_ca_l_0(arbcp2_cpxdp_grant_bufp1_ca_l[0]), // Templated
.arbcp2_cpxdp_q0_hold_bufp1_ca_0(arbcp2_cpxdp_q0_hold_bufp1_ca[0]), // Templated
.arbcp2_cpxdp_qsel0_bufp1_ca_l_0(arbcp2_cpxdp_qsel0_bufp1_ca_l[0]), // Templated
.arbcp2_cpxdp_qsel1_bufp1_ca_0(arbcp2_cpxdp_qsel1_bufp1_ca[0]), // Templated
.arbcp2_cpxdp_shift_bufp1_cx_l_0(arbcp2_cpxdp_shift_bufp1_cx_l[0]), // Templated
.arbcp3_cpxdp_grant_bufp1_ca_l_0(arbcp3_cpxdp_grant_bufp1_ca_l[0]), // Templated
.arbcp3_cpxdp_q0_hold_bufp1_ca_0(arbcp3_cpxdp_q0_hold_bufp1_ca[0]), // Templated
.arbcp3_cpxdp_qsel0_bufp1_ca_l_0(arbcp3_cpxdp_qsel0_bufp1_ca_l[0]), // Templated
.arbcp3_cpxdp_qsel1_bufp1_ca_0(arbcp3_cpxdp_qsel1_bufp1_ca[0]), // Templated
.arbcp3_cpxdp_shift_bufp1_cx_l_0(arbcp3_cpxdp_shift_bufp1_cx_l[0]), // Templated
.arbcp4_cpxdp_grant_bufp1_ca_l_0(arbcp4_cpxdp_grant_bufp1_ca_l[0]), // Templated
.arbcp4_cpxdp_q0_hold_bufp1_ca_0(arbcp4_cpxdp_q0_hold_bufp1_ca[0]), // Templated
.arbcp4_cpxdp_qsel0_bufp1_ca_l_0(arbcp4_cpxdp_qsel0_bufp1_ca_l[0]), // Templated
.arbcp4_cpxdp_qsel1_bufp1_ca_0(arbcp4_cpxdp_qsel1_bufp1_ca[0]), // Templated
.arbcp4_cpxdp_shift_bufp1_cx_l_0(arbcp4_cpxdp_shift_bufp1_cx_l[0]), // Templated
.arbcp5_cpxdp_grant_bufp1_ca_l_0(arbcp5_cpxdp_grant_bufp1_ca_l[0]), // Templated
.arbcp5_cpxdp_q0_hold_bufp1_ca_0(arbcp5_cpxdp_q0_hold_bufp1_ca[0]), // Templated
.arbcp5_cpxdp_qsel0_bufp1_ca_l_0(arbcp5_cpxdp_qsel0_bufp1_ca_l[0]), // Templated
.arbcp5_cpxdp_qsel1_bufp1_ca_0(arbcp5_cpxdp_qsel1_bufp1_ca[0]), // Templated
.arbcp5_cpxdp_shift_bufp1_cx_l_0(arbcp5_cpxdp_shift_bufp1_cx_l[0]), // Templated
.arbcp6_cpxdp_grant_bufp1_ca_l_0(arbcp6_cpxdp_grant_bufp1_ca_l[0]), // Templated
.arbcp6_cpxdp_q0_hold_bufp1_ca_0(arbcp6_cpxdp_q0_hold_bufp1_ca[0]), // Templated
.arbcp6_cpxdp_qsel0_bufp1_ca_l_0(arbcp6_cpxdp_qsel0_bufp1_ca_l[0]), // Templated
.arbcp6_cpxdp_qsel1_bufp1_ca_0(arbcp6_cpxdp_qsel1_bufp1_ca[0]), // Templated
.arbcp6_cpxdp_shift_bufp1_cx_l_0(arbcp6_cpxdp_shift_bufp1_cx_l[0]), // Templated
.arbcp7_cpxdp_grant_bufp1_ca_l_0(arbcp7_cpxdp_grant_bufp1_ca_l[0]), // Templated
.arbcp7_cpxdp_q0_hold_bufp1_ca_0(arbcp7_cpxdp_q0_hold_bufp1_ca[0]), // Templated
.arbcp7_cpxdp_qsel0_bufp1_ca_l_0(arbcp7_cpxdp_qsel0_bufp1_ca_l[0]), // Templated
.arbcp7_cpxdp_qsel1_bufp1_ca_0(arbcp7_cpxdp_qsel1_bufp1_ca[0]), // Templated
.arbcp7_cpxdp_shift_bufp1_cx_l_0(arbcp7_cpxdp_shift_bufp1_cx_l[0]), // Templated
.arbcp0_cpxdp_grant_bufp1_ca_l_1(arbcp0_cpxdp_grant_bufp1_ca_l[1]), // Templated
.arbcp0_cpxdp_q0_hold_bufp1_ca_1(arbcp0_cpxdp_q0_hold_bufp1_ca[1]), // Templated
.arbcp0_cpxdp_qsel0_bufp1_ca_l_1(arbcp0_cpxdp_qsel0_bufp1_ca_l[1]), // Templated
.arbcp0_cpxdp_qsel1_bufp1_ca_1(arbcp0_cpxdp_qsel1_bufp1_ca[1]), // Templated
.arbcp0_cpxdp_shift_bufp1_cx_l_1(arbcp0_cpxdp_shift_bufp1_cx_l[1]), // Templated
.arbcp1_cpxdp_grant_bufp1_ca_l_1(arbcp1_cpxdp_grant_bufp1_ca_l[1]), // Templated
.arbcp1_cpxdp_q0_hold_bufp1_ca_1(arbcp1_cpxdp_q0_hold_bufp1_ca[1]), // Templated
.arbcp1_cpxdp_qsel0_bufp1_ca_l_1(arbcp1_cpxdp_qsel0_bufp1_ca_l[1]), // Templated
.arbcp1_cpxdp_qsel1_bufp1_ca_1(arbcp1_cpxdp_qsel1_bufp1_ca[1]), // Templated
.arbcp1_cpxdp_shift_bufp1_cx_l_1(arbcp1_cpxdp_shift_bufp1_cx_l[1]), // Templated
.arbcp2_cpxdp_grant_bufp1_ca_l_1(arbcp2_cpxdp_grant_bufp1_ca_l[1]), // Templated
.arbcp2_cpxdp_q0_hold_bufp1_ca_1(arbcp2_cpxdp_q0_hold_bufp1_ca[1]), // Templated
.arbcp2_cpxdp_qsel0_bufp1_ca_l_1(arbcp2_cpxdp_qsel0_bufp1_ca_l[1]), // Templated
.arbcp2_cpxdp_qsel1_bufp1_ca_1(arbcp2_cpxdp_qsel1_bufp1_ca[1]), // Templated
.arbcp2_cpxdp_shift_bufp1_cx_l_1(arbcp2_cpxdp_shift_bufp1_cx_l[1]), // Templated
.arbcp3_cpxdp_grant_bufp1_ca_l_1(arbcp3_cpxdp_grant_bufp1_ca_l[1]), // Templated
.arbcp3_cpxdp_q0_hold_bufp1_ca_1(arbcp3_cpxdp_q0_hold_bufp1_ca[1]), // Templated
.arbcp3_cpxdp_qsel0_bufp1_ca_l_1(arbcp3_cpxdp_qsel0_bufp1_ca_l[1]), // Templated
.arbcp3_cpxdp_qsel1_bufp1_ca_1(arbcp3_cpxdp_qsel1_bufp1_ca[1]), // Templated
.arbcp3_cpxdp_shift_bufp1_cx_l_1(arbcp3_cpxdp_shift_bufp1_cx_l[1]), // Templated
.arbcp4_cpxdp_grant_bufp1_ca_l_1(arbcp4_cpxdp_grant_bufp1_ca_l[1]), // Templated
.arbcp4_cpxdp_q0_hold_bufp1_ca_1(arbcp4_cpxdp_q0_hold_bufp1_ca[1]), // Templated
.arbcp4_cpxdp_qsel0_bufp1_ca_l_1(arbcp4_cpxdp_qsel0_bufp1_ca_l[1]), // Templated
.arbcp4_cpxdp_qsel1_bufp1_ca_1(arbcp4_cpxdp_qsel1_bufp1_ca[1]), // Templated
.arbcp4_cpxdp_shift_bufp1_cx_l_1(arbcp4_cpxdp_shift_bufp1_cx_l[1]), // Templated
.arbcp5_cpxdp_grant_bufp1_ca_l_1(arbcp5_cpxdp_grant_bufp1_ca_l[1]), // Templated
.arbcp5_cpxdp_q0_hold_bufp1_ca_1(arbcp5_cpxdp_q0_hold_bufp1_ca[1]), // Templated
.arbcp5_cpxdp_qsel0_bufp1_ca_l_1(arbcp5_cpxdp_qsel0_bufp1_ca_l[1]), // Templated
.arbcp5_cpxdp_qsel1_bufp1_ca_1(arbcp5_cpxdp_qsel1_bufp1_ca[1]), // Templated
.arbcp5_cpxdp_shift_bufp1_cx_l_1(arbcp5_cpxdp_shift_bufp1_cx_l[1]), // Templated
.arbcp6_cpxdp_grant_bufp1_ca_l_1(arbcp6_cpxdp_grant_bufp1_ca_l[1]), // Templated
.arbcp6_cpxdp_q0_hold_bufp1_ca_1(arbcp6_cpxdp_q0_hold_bufp1_ca[1]), // Templated
.arbcp6_cpxdp_qsel0_bufp1_ca_l_1(arbcp6_cpxdp_qsel0_bufp1_ca_l[1]), // Templated
.arbcp6_cpxdp_qsel1_bufp1_ca_1(arbcp6_cpxdp_qsel1_bufp1_ca[1]), // Templated
.arbcp6_cpxdp_shift_bufp1_cx_l_1(arbcp6_cpxdp_shift_bufp1_cx_l[1]), // Templated
.arbcp7_cpxdp_grant_bufp1_ca_l_1(arbcp7_cpxdp_grant_bufp1_ca_l[1]), // Templated
.arbcp7_cpxdp_q0_hold_bufp1_ca_1(arbcp7_cpxdp_q0_hold_bufp1_ca[1]), // Templated
.arbcp7_cpxdp_qsel0_bufp1_ca_l_1(arbcp7_cpxdp_qsel0_bufp1_ca_l[1]), // Templated
.arbcp7_cpxdp_qsel1_bufp1_ca_1(arbcp7_cpxdp_qsel1_bufp1_ca[1]), // Templated
.arbcp7_cpxdp_shift_bufp1_cx_l_1(arbcp7_cpxdp_shift_bufp1_cx_l[1]), // Templated
// Inputs
.scache0_cpx_req_bufp0_cq(scache0_cpx_req_bufp0_cq[7:0]),
.scache0_cpx_atom_bufp0_cq(scache0_cpx_atom_bufp0_cq),
.cpx_scache0_grant_ca (cpx_scache0_grant_ca[7:0]),
.cpx_spc0_data_rdy_cx (cpx_spc0_data_rdy_cx),
.cpx_spc1_data_rdy_cx (cpx_spc1_data_rdy_cx),
.cpx_spc2_data_rdy_cx (cpx_spc2_data_rdy_cx),
.arbcp0_cpxdp_grant_arbbf_ca_0(arbcp0_cpxdp_grant_arbbf_ca[0]), // Templated
.arbcp0_cpxdp_q0_hold_arbbf_ca_l_0(arbcp0_cpxdp_q0_hold_arbbf_ca_l[0]), // Templated
.arbcp0_cpxdp_qsel0_arbbf_ca_0(arbcp0_cpxdp_qsel0_arbbf_ca[0]), // Templated
.arbcp0_cpxdp_qsel1_arbbf_ca_l_0(arbcp0_cpxdp_qsel1_arbbf_ca_l[0]), // Templated
.arbcp0_cpxdp_shift_arbbf_cx_0(arbcp0_cpxdp_shift_arbbf_cx[0]), // Templated
.arbcp1_cpxdp_grant_arbbf_ca_0(arbcp1_cpxdp_grant_arbbf_ca[0]), // Templated
.arbcp1_cpxdp_q0_hold_arbbf_ca_l_0(arbcp1_cpxdp_q0_hold_arbbf_ca_l[0]), // Templated
.arbcp1_cpxdp_qsel0_arbbf_ca_0(arbcp1_cpxdp_qsel0_arbbf_ca[0]), // Templated
.arbcp1_cpxdp_qsel1_arbbf_ca_l_0(arbcp1_cpxdp_qsel1_arbbf_ca_l[0]), // Templated
.arbcp1_cpxdp_shift_arbbf_cx_0(arbcp1_cpxdp_shift_arbbf_cx[0]), // Templated
.arbcp2_cpxdp_grant_arbbf_ca_0(arbcp2_cpxdp_grant_arbbf_ca[0]), // Templated
.arbcp2_cpxdp_q0_hold_arbbf_ca_l_0(arbcp2_cpxdp_q0_hold_arbbf_ca_l[0]), // Templated
.arbcp2_cpxdp_qsel0_arbbf_ca_0(arbcp2_cpxdp_qsel0_arbbf_ca[0]), // Templated
.arbcp2_cpxdp_qsel1_arbbf_ca_l_0(arbcp2_cpxdp_qsel1_arbbf_ca_l[0]), // Templated
.arbcp2_cpxdp_shift_arbbf_cx_0(arbcp2_cpxdp_shift_arbbf_cx[0]), // Templated
.arbcp3_cpxdp_grant_arbbf_ca_0(arbcp3_cpxdp_grant_arbbf_ca[0]), // Templated
.arbcp3_cpxdp_q0_hold_arbbf_ca_l_0(arbcp3_cpxdp_q0_hold_arbbf_ca_l[0]), // Templated
.arbcp3_cpxdp_qsel0_arbbf_ca_0(arbcp3_cpxdp_qsel0_arbbf_ca[0]), // Templated
.arbcp3_cpxdp_qsel1_arbbf_ca_l_0(arbcp3_cpxdp_qsel1_arbbf_ca_l[0]), // Templated
.arbcp3_cpxdp_shift_arbbf_cx_0(arbcp3_cpxdp_shift_arbbf_cx[0]), // Templated
.arbcp4_cpxdp_grant_arbbf_ca_0(arbcp4_cpxdp_grant_arbbf_ca[0]), // Templated
.arbcp4_cpxdp_q0_hold_arbbf_ca_l_0(arbcp4_cpxdp_q0_hold_arbbf_ca_l[0]), // Templated
.arbcp4_cpxdp_qsel0_arbbf_ca_0(arbcp4_cpxdp_qsel0_arbbf_ca[0]), // Templated
.arbcp4_cpxdp_qsel1_arbbf_ca_l_0(arbcp4_cpxdp_qsel1_arbbf_ca_l[0]), // Templated
.arbcp4_cpxdp_shift_arbbf_cx_0(arbcp4_cpxdp_shift_arbbf_cx[0]), // Templated
.arbcp5_cpxdp_grant_arbbf_ca_0(arbcp5_cpxdp_grant_arbbf_ca[0]), // Templated
.arbcp5_cpxdp_q0_hold_arbbf_ca_l_0(arbcp5_cpxdp_q0_hold_arbbf_ca_l[0]), // Templated
.arbcp5_cpxdp_qsel0_arbbf_ca_0(arbcp5_cpxdp_qsel0_arbbf_ca[0]), // Templated
.arbcp5_cpxdp_qsel1_arbbf_ca_l_0(arbcp5_cpxdp_qsel1_arbbf_ca_l[0]), // Templated
.arbcp5_cpxdp_shift_arbbf_cx_0(arbcp5_cpxdp_shift_arbbf_cx[0]), // Templated
.arbcp6_cpxdp_grant_arbbf_ca_0(arbcp6_cpxdp_grant_arbbf_ca[0]), // Templated
.arbcp6_cpxdp_q0_hold_arbbf_ca_l_0(arbcp6_cpxdp_q0_hold_arbbf_ca_l[0]), // Templated
.arbcp6_cpxdp_qsel0_arbbf_ca_0(arbcp6_cpxdp_qsel0_arbbf_ca[0]), // Templated
.arbcp6_cpxdp_qsel1_arbbf_ca_l_0(arbcp6_cpxdp_qsel1_arbbf_ca_l[0]), // Templated
.arbcp6_cpxdp_shift_arbbf_cx_0(arbcp6_cpxdp_shift_arbbf_cx[0]), // Templated
.arbcp7_cpxdp_grant_arbbf_ca_0(arbcp7_cpxdp_grant_arbbf_ca[0]), // Templated
.arbcp7_cpxdp_q0_hold_arbbf_ca_l_0(arbcp7_cpxdp_q0_hold_arbbf_ca_l[0]), // Templated
.arbcp7_cpxdp_qsel0_arbbf_ca_0(arbcp7_cpxdp_qsel0_arbbf_ca[0]), // Templated
.arbcp7_cpxdp_qsel1_arbbf_ca_l_0(arbcp7_cpxdp_qsel1_arbbf_ca_l[0]), // Templated
.arbcp7_cpxdp_shift_arbbf_cx_0(arbcp7_cpxdp_shift_arbbf_cx[0]), // Templated
.arbcp0_cpxdp_grant_arbbf_ca_1(arbcp0_cpxdp_grant_arbbf_ca[1]), // Templated
.arbcp0_cpxdp_q0_hold_arbbf_ca_l_1(arbcp0_cpxdp_q0_hold_arbbf_ca_l[1]), // Templated
.arbcp0_cpxdp_qsel0_arbbf_ca_1(arbcp0_cpxdp_qsel0_arbbf_ca[1]), // Templated
.arbcp0_cpxdp_qsel1_arbbf_ca_l_1(arbcp0_cpxdp_qsel1_arbbf_ca_l[1]), // Templated
.arbcp0_cpxdp_shift_arbbf_cx_1(arbcp0_cpxdp_shift_arbbf_cx[1]), // Templated
.arbcp1_cpxdp_grant_arbbf_ca_1(arbcp1_cpxdp_grant_arbbf_ca[1]), // Templated
.arbcp1_cpxdp_q0_hold_arbbf_ca_l_1(arbcp1_cpxdp_q0_hold_arbbf_ca_l[1]), // Templated
.arbcp1_cpxdp_qsel0_arbbf_ca_1(arbcp1_cpxdp_qsel0_arbbf_ca[1]), // Templated
.arbcp1_cpxdp_qsel1_arbbf_ca_l_1(arbcp1_cpxdp_qsel1_arbbf_ca_l[1]), // Templated
.arbcp1_cpxdp_shift_arbbf_cx_1(arbcp1_cpxdp_shift_arbbf_cx[1]), // Templated
.arbcp2_cpxdp_grant_arbbf_ca_1(arbcp2_cpxdp_grant_arbbf_ca[1]), // Templated
.arbcp2_cpxdp_q0_hold_arbbf_ca_l_1(arbcp2_cpxdp_q0_hold_arbbf_ca_l[1]), // Templated
.arbcp2_cpxdp_qsel0_arbbf_ca_1(arbcp2_cpxdp_qsel0_arbbf_ca[1]), // Templated
.arbcp2_cpxdp_qsel1_arbbf_ca_l_1(arbcp2_cpxdp_qsel1_arbbf_ca_l[1]), // Templated
.arbcp2_cpxdp_shift_arbbf_cx_1(arbcp2_cpxdp_shift_arbbf_cx[1]), // Templated
.arbcp3_cpxdp_grant_arbbf_ca_1(arbcp3_cpxdp_grant_arbbf_ca[1]), // Templated
.arbcp3_cpxdp_q0_hold_arbbf_ca_l_1(arbcp3_cpxdp_q0_hold_arbbf_ca_l[1]), // Templated
.arbcp3_cpxdp_qsel0_arbbf_ca_1(arbcp3_cpxdp_qsel0_arbbf_ca[1]), // Templated
.arbcp3_cpxdp_qsel1_arbbf_ca_l_1(arbcp3_cpxdp_qsel1_arbbf_ca_l[1]), // Templated
.arbcp3_cpxdp_shift_arbbf_cx_1(arbcp3_cpxdp_shift_arbbf_cx[1]), // Templated
.arbcp4_cpxdp_grant_arbbf_ca_1(arbcp4_cpxdp_grant_arbbf_ca[1]), // Templated
.arbcp4_cpxdp_q0_hold_arbbf_ca_l_1(arbcp4_cpxdp_q0_hold_arbbf_ca_l[1]), // Templated
.arbcp4_cpxdp_qsel0_arbbf_ca_1(arbcp4_cpxdp_qsel0_arbbf_ca[1]), // Templated
.arbcp4_cpxdp_qsel1_arbbf_ca_l_1(arbcp4_cpxdp_qsel1_arbbf_ca_l[1]), // Templated
.arbcp4_cpxdp_shift_arbbf_cx_1(arbcp4_cpxdp_shift_arbbf_cx[1]), // Templated
.arbcp5_cpxdp_grant_arbbf_ca_1(arbcp5_cpxdp_grant_arbbf_ca[1]), // Templated
.arbcp5_cpxdp_q0_hold_arbbf_ca_l_1(arbcp5_cpxdp_q0_hold_arbbf_ca_l[1]), // Templated
.arbcp5_cpxdp_qsel0_arbbf_ca_1(arbcp5_cpxdp_qsel0_arbbf_ca[1]), // Templated
.arbcp5_cpxdp_qsel1_arbbf_ca_l_1(arbcp5_cpxdp_qsel1_arbbf_ca_l[1]), // Templated
.arbcp5_cpxdp_shift_arbbf_cx_1(arbcp5_cpxdp_shift_arbbf_cx[1]), // Templated
.arbcp6_cpxdp_grant_arbbf_ca_1(arbcp6_cpxdp_grant_arbbf_ca[1]), // Templated
.arbcp6_cpxdp_q0_hold_arbbf_ca_l_1(arbcp6_cpxdp_q0_hold_arbbf_ca_l[1]), // Templated
.arbcp6_cpxdp_qsel0_arbbf_ca_1(arbcp6_cpxdp_qsel0_arbbf_ca[1]), // Templated
.arbcp6_cpxdp_qsel1_arbbf_ca_l_1(arbcp6_cpxdp_qsel1_arbbf_ca_l[1]), // Templated
.arbcp6_cpxdp_shift_arbbf_cx_1(arbcp6_cpxdp_shift_arbbf_cx[1]), // Templated
.arbcp7_cpxdp_grant_arbbf_ca_1(arbcp7_cpxdp_grant_arbbf_ca[1]), // Templated
.arbcp7_cpxdp_q0_hold_arbbf_ca_l_1(arbcp7_cpxdp_q0_hold_arbbf_ca_l[1]), // Templated
.arbcp7_cpxdp_qsel0_arbbf_ca_1(arbcp7_cpxdp_qsel0_arbbf_ca[1]), // Templated
.arbcp7_cpxdp_qsel1_arbbf_ca_l_1(arbcp7_cpxdp_qsel1_arbbf_ca_l[1]), // Templated
.arbcp7_cpxdp_shift_arbbf_cx_1(arbcp7_cpxdp_shift_arbbf_cx[1])); // Templated
cpx_fpbuf_p0 fpbuf_p0(/*AUTOINST*/
// Outputs
.fp_cpx_req_bufp0_cq(fp_cpx_req_bufp0_cq[7:0]),
// Inputs
.fp_cpx_req_bufpt_cq_l(fp_cpx_req_bufpt_cq_l[7:0]));
/* cpx_fpbuf_p1 AUTO_TEMPLATE(
// Outputs
.arbcp0_cpxdp_grant_bufp1_ca_l_1(arbcp0_cpxdp_grant_bufp1_ca_l[3]),
.arbcp0_cpxdp_q0_hold_bufp1_ca_1(arbcp0_cpxdp_q0_hold_bufp1_ca[3]),
.arbcp0_cpxdp_qsel0_bufp1_ca_l_1(arbcp0_cpxdp_qsel0_bufp1_ca_l[3]),
.arbcp0_cpxdp_qsel1_bufp1_ca_1(arbcp0_cpxdp_qsel1_bufp1_ca[3]),
.arbcp0_cpxdp_shift_bufp1_cx_l_1(arbcp0_cpxdp_shift_bufp1_cx_l[3]),
.arbcp1_cpxdp_grant_bufp1_ca_l_1(arbcp1_cpxdp_grant_bufp1_ca_l[3]),
.arbcp1_cpxdp_q0_hold_bufp1_ca_1(arbcp1_cpxdp_q0_hold_bufp1_ca[3]),
.arbcp1_cpxdp_qsel0_bufp1_ca_l_1(arbcp1_cpxdp_qsel0_bufp1_ca_l[3]),
.arbcp1_cpxdp_qsel1_bufp1_ca_1(arbcp1_cpxdp_qsel1_bufp1_ca[3]),
.arbcp1_cpxdp_shift_bufp1_cx_l_1(arbcp1_cpxdp_shift_bufp1_cx_l[3]),
.arbcp2_cpxdp_grant_bufp1_ca_l_1(arbcp2_cpxdp_grant_bufp1_ca_l[3]),
.arbcp2_cpxdp_q0_hold_bufp1_ca_1(arbcp2_cpxdp_q0_hold_bufp1_ca[3]),
.arbcp2_cpxdp_qsel0_bufp1_ca_l_1(arbcp2_cpxdp_qsel0_bufp1_ca_l[3]),
.arbcp2_cpxdp_qsel1_bufp1_ca_1(arbcp2_cpxdp_qsel1_bufp1_ca[3]),
.arbcp2_cpxdp_shift_bufp1_cx_l_1(arbcp2_cpxdp_shift_bufp1_cx_l[3]),
.arbcp3_cpxdp_grant_bufp1_ca_l_1(arbcp3_cpxdp_grant_bufp1_ca_l[3]),
.arbcp3_cpxdp_q0_hold_bufp1_ca_1(arbcp3_cpxdp_q0_hold_bufp1_ca[3]),
.arbcp3_cpxdp_qsel0_bufp1_ca_l_1(arbcp3_cpxdp_qsel0_bufp1_ca_l[3]),
.arbcp3_cpxdp_qsel1_bufp1_ca_1(arbcp3_cpxdp_qsel1_bufp1_ca[3]),
.arbcp3_cpxdp_shift_bufp1_cx_l_1(arbcp3_cpxdp_shift_bufp1_cx_l[3]),
.arbcp4_cpxdp_grant_bufp1_ca_l_1(arbcp4_cpxdp_grant_bufp1_ca_l[3]),
.arbcp4_cpxdp_q0_hold_bufp1_ca_1(arbcp4_cpxdp_q0_hold_bufp1_ca[3]),
.arbcp4_cpxdp_qsel0_bufp1_ca_l_1(arbcp4_cpxdp_qsel0_bufp1_ca_l[3]),
.arbcp4_cpxdp_qsel1_bufp1_ca_1(arbcp4_cpxdp_qsel1_bufp1_ca[3]),
.arbcp4_cpxdp_shift_bufp1_cx_l_1(arbcp4_cpxdp_shift_bufp1_cx_l[3]),
.arbcp5_cpxdp_grant_bufp1_ca_l_1(arbcp5_cpxdp_grant_bufp1_ca_l[3]),
.arbcp5_cpxdp_q0_hold_bufp1_ca_1(arbcp5_cpxdp_q0_hold_bufp1_ca[3]),
.arbcp5_cpxdp_qsel0_bufp1_ca_l_1(arbcp5_cpxdp_qsel0_bufp1_ca_l[3]),
.arbcp5_cpxdp_qsel1_bufp1_ca_1(arbcp5_cpxdp_qsel1_bufp1_ca[3]),
.arbcp5_cpxdp_shift_bufp1_cx_l_1(arbcp5_cpxdp_shift_bufp1_cx_l[3]),
.arbcp6_cpxdp_grant_bufp1_ca_l_1(arbcp6_cpxdp_grant_bufp1_ca_l[3]),
.arbcp6_cpxdp_q0_hold_bufp1_ca_1(arbcp6_cpxdp_q0_hold_bufp1_ca[3]),
.arbcp6_cpxdp_qsel0_bufp1_ca_l_1(arbcp6_cpxdp_qsel0_bufp1_ca_l[3]),
.arbcp6_cpxdp_qsel1_bufp1_ca_1(arbcp6_cpxdp_qsel1_bufp1_ca[3]),
.arbcp6_cpxdp_shift_bufp1_cx_l_1(arbcp6_cpxdp_shift_bufp1_cx_l[3]),
.arbcp7_cpxdp_grant_bufp1_ca_l_1(arbcp7_cpxdp_grant_bufp1_ca_l[3]),
.arbcp7_cpxdp_q0_hold_bufp1_ca_1(arbcp7_cpxdp_q0_hold_bufp1_ca[3]),
.arbcp7_cpxdp_qsel0_bufp1_ca_l_1(arbcp7_cpxdp_qsel0_bufp1_ca_l[3]),
.arbcp7_cpxdp_qsel1_bufp1_ca_1(arbcp7_cpxdp_qsel1_bufp1_ca[3]),
.arbcp7_cpxdp_shift_bufp1_cx_l_1(arbcp7_cpxdp_shift_bufp1_cx_l[3]),
// Inputs
.arbcp0_cpxdp_grant_arbbf_ca_1(arbcp0_cpxdp_grant_arbbf_ca[3]),
.arbcp0_cpxdp_q0_hold_arbbf_ca_l_1(arbcp0_cpxdp_q0_hold_arbbf_ca_l[3]),
.arbcp0_cpxdp_qsel0_arbbf_ca_1(arbcp0_cpxdp_qsel0_arbbf_ca[3]),
.arbcp0_cpxdp_qsel1_arbbf_ca_l_1(arbcp0_cpxdp_qsel1_arbbf_ca_l[3]),
.arbcp0_cpxdp_shift_arbbf_cx_1(arbcp0_cpxdp_shift_arbbf_cx[3]),
.arbcp1_cpxdp_grant_arbbf_ca_1(arbcp1_cpxdp_grant_arbbf_ca[3]),
.arbcp1_cpxdp_q0_hold_arbbf_ca_l_1(arbcp1_cpxdp_q0_hold_arbbf_ca_l[3]),
.arbcp1_cpxdp_qsel0_arbbf_ca_1(arbcp1_cpxdp_qsel0_arbbf_ca[3]),
.arbcp1_cpxdp_qsel1_arbbf_ca_l_1(arbcp1_cpxdp_qsel1_arbbf_ca_l[3]),
.arbcp1_cpxdp_shift_arbbf_cx_1(arbcp1_cpxdp_shift_arbbf_cx[3]),
.arbcp2_cpxdp_grant_arbbf_ca_1(arbcp2_cpxdp_grant_arbbf_ca[3]),
.arbcp2_cpxdp_q0_hold_arbbf_ca_l_1(arbcp2_cpxdp_q0_hold_arbbf_ca_l[3]),
.arbcp2_cpxdp_qsel0_arbbf_ca_1(arbcp2_cpxdp_qsel0_arbbf_ca[3]),
.arbcp2_cpxdp_qsel1_arbbf_ca_l_1(arbcp2_cpxdp_qsel1_arbbf_ca_l[3]),
.arbcp2_cpxdp_shift_arbbf_cx_1(arbcp2_cpxdp_shift_arbbf_cx[3]),
.arbcp3_cpxdp_grant_arbbf_ca_1(arbcp3_cpxdp_grant_arbbf_ca[3]),
.arbcp3_cpxdp_q0_hold_arbbf_ca_l_1(arbcp3_cpxdp_q0_hold_arbbf_ca_l[3]),
.arbcp3_cpxdp_qsel0_arbbf_ca_1(arbcp3_cpxdp_qsel0_arbbf_ca[3]),
.arbcp3_cpxdp_qsel1_arbbf_ca_l_1(arbcp3_cpxdp_qsel1_arbbf_ca_l[3]),
.arbcp3_cpxdp_shift_arbbf_cx_1(arbcp3_cpxdp_shift_arbbf_cx[3]),
.arbcp4_cpxdp_grant_arbbf_ca_1(arbcp4_cpxdp_grant_arbbf_ca[3]),
.arbcp4_cpxdp_q0_hold_arbbf_ca_l_1(arbcp4_cpxdp_q0_hold_arbbf_ca_l[3]),
.arbcp4_cpxdp_qsel0_arbbf_ca_1(arbcp4_cpxdp_qsel0_arbbf_ca[3]),
.arbcp4_cpxdp_qsel1_arbbf_ca_l_1(arbcp4_cpxdp_qsel1_arbbf_ca_l[3]),
.arbcp4_cpxdp_shift_arbbf_cx_1(arbcp4_cpxdp_shift_arbbf_cx[3]),
.arbcp5_cpxdp_grant_arbbf_ca_1(arbcp5_cpxdp_grant_arbbf_ca[3]),
.arbcp5_cpxdp_q0_hold_arbbf_ca_l_1(arbcp5_cpxdp_q0_hold_arbbf_ca_l[3]),
.arbcp5_cpxdp_qsel0_arbbf_ca_1(arbcp5_cpxdp_qsel0_arbbf_ca[3]),
.arbcp5_cpxdp_qsel1_arbbf_ca_l_1(arbcp5_cpxdp_qsel1_arbbf_ca_l[3]),
.arbcp5_cpxdp_shift_arbbf_cx_1(arbcp5_cpxdp_shift_arbbf_cx[3]),
.arbcp6_cpxdp_grant_arbbf_ca_1(arbcp6_cpxdp_grant_arbbf_ca[3]),
.arbcp6_cpxdp_q0_hold_arbbf_ca_l_1(arbcp6_cpxdp_q0_hold_arbbf_ca_l[3]),
.arbcp6_cpxdp_qsel0_arbbf_ca_1(arbcp6_cpxdp_qsel0_arbbf_ca[3]),
.arbcp6_cpxdp_qsel1_arbbf_ca_l_1(arbcp6_cpxdp_qsel1_arbbf_ca_l[3]),
.arbcp6_cpxdp_shift_arbbf_cx_1(arbcp6_cpxdp_shift_arbbf_cx[3]),
.arbcp7_cpxdp_grant_arbbf_ca_1(arbcp7_cpxdp_grant_arbbf_ca[3]),
.arbcp7_cpxdp_q0_hold_arbbf_ca_l_1(arbcp7_cpxdp_q0_hold_arbbf_ca_l[3]),
.arbcp7_cpxdp_qsel0_arbbf_ca_1(arbcp7_cpxdp_qsel0_arbbf_ca[3]),
.arbcp7_cpxdp_qsel1_arbbf_ca_l_1(arbcp7_cpxdp_qsel1_arbbf_ca_l[3]),
.arbcp7_cpxdp_shift_arbbf_cx_1(arbcp7_cpxdp_shift_arbbf_cx[3]));
*/
cpx_fpbuf_p1 fpbuf_p1(/*AUTOINST*/
// Outputs
.fp_cpx_req_bufp1_cq(fp_cpx_req_bufp1_cq[7:0]),
.arbcp0_cpxdp_grant_bufp1_ca_l_1(arbcp0_cpxdp_grant_bufp1_ca_l[3]), // Templated
.arbcp0_cpxdp_q0_hold_bufp1_ca_1(arbcp0_cpxdp_q0_hold_bufp1_ca[3]), // Templated
.arbcp0_cpxdp_qsel0_bufp1_ca_l_1(arbcp0_cpxdp_qsel0_bufp1_ca_l[3]), // Templated
.arbcp0_cpxdp_qsel1_bufp1_ca_1(arbcp0_cpxdp_qsel1_bufp1_ca[3]), // Templated
.arbcp0_cpxdp_shift_bufp1_cx_l_1(arbcp0_cpxdp_shift_bufp1_cx_l[3]), // Templated
.arbcp1_cpxdp_grant_bufp1_ca_l_1(arbcp1_cpxdp_grant_bufp1_ca_l[3]), // Templated
.arbcp1_cpxdp_q0_hold_bufp1_ca_1(arbcp1_cpxdp_q0_hold_bufp1_ca[3]), // Templated
.arbcp1_cpxdp_qsel0_bufp1_ca_l_1(arbcp1_cpxdp_qsel0_bufp1_ca_l[3]), // Templated
.arbcp1_cpxdp_qsel1_bufp1_ca_1(arbcp1_cpxdp_qsel1_bufp1_ca[3]), // Templated
.arbcp1_cpxdp_shift_bufp1_cx_l_1(arbcp1_cpxdp_shift_bufp1_cx_l[3]), // Templated
.arbcp2_cpxdp_grant_bufp1_ca_l_1(arbcp2_cpxdp_grant_bufp1_ca_l[3]), // Templated
.arbcp2_cpxdp_q0_hold_bufp1_ca_1(arbcp2_cpxdp_q0_hold_bufp1_ca[3]), // Templated
.arbcp2_cpxdp_qsel0_bufp1_ca_l_1(arbcp2_cpxdp_qsel0_bufp1_ca_l[3]), // Templated
.arbcp2_cpxdp_qsel1_bufp1_ca_1(arbcp2_cpxdp_qsel1_bufp1_ca[3]), // Templated
.arbcp2_cpxdp_shift_bufp1_cx_l_1(arbcp2_cpxdp_shift_bufp1_cx_l[3]), // Templated
.arbcp3_cpxdp_grant_bufp1_ca_l_1(arbcp3_cpxdp_grant_bufp1_ca_l[3]), // Templated
.arbcp3_cpxdp_q0_hold_bufp1_ca_1(arbcp3_cpxdp_q0_hold_bufp1_ca[3]), // Templated
.arbcp3_cpxdp_qsel0_bufp1_ca_l_1(arbcp3_cpxdp_qsel0_bufp1_ca_l[3]), // Templated
.arbcp3_cpxdp_qsel1_bufp1_ca_1(arbcp3_cpxdp_qsel1_bufp1_ca[3]), // Templated
.arbcp3_cpxdp_shift_bufp1_cx_l_1(arbcp3_cpxdp_shift_bufp1_cx_l[3]), // Templated
.arbcp4_cpxdp_grant_bufp1_ca_l_1(arbcp4_cpxdp_grant_bufp1_ca_l[3]), // Templated
.arbcp4_cpxdp_q0_hold_bufp1_ca_1(arbcp4_cpxdp_q0_hold_bufp1_ca[3]), // Templated
.arbcp4_cpxdp_qsel0_bufp1_ca_l_1(arbcp4_cpxdp_qsel0_bufp1_ca_l[3]), // Templated
.arbcp4_cpxdp_qsel1_bufp1_ca_1(arbcp4_cpxdp_qsel1_bufp1_ca[3]), // Templated
.arbcp4_cpxdp_shift_bufp1_cx_l_1(arbcp4_cpxdp_shift_bufp1_cx_l[3]), // Templated
.arbcp5_cpxdp_grant_bufp1_ca_l_1(arbcp5_cpxdp_grant_bufp1_ca_l[3]), // Templated
.arbcp5_cpxdp_q0_hold_bufp1_ca_1(arbcp5_cpxdp_q0_hold_bufp1_ca[3]), // Templated
.arbcp5_cpxdp_qsel0_bufp1_ca_l_1(arbcp5_cpxdp_qsel0_bufp1_ca_l[3]), // Templated
.arbcp5_cpxdp_qsel1_bufp1_ca_1(arbcp5_cpxdp_qsel1_bufp1_ca[3]), // Templated
.arbcp5_cpxdp_shift_bufp1_cx_l_1(arbcp5_cpxdp_shift_bufp1_cx_l[3]), // Templated
.arbcp6_cpxdp_grant_bufp1_ca_l_1(arbcp6_cpxdp_grant_bufp1_ca_l[3]), // Templated
.arbcp6_cpxdp_q0_hold_bufp1_ca_1(arbcp6_cpxdp_q0_hold_bufp1_ca[3]), // Templated
.arbcp6_cpxdp_qsel0_bufp1_ca_l_1(arbcp6_cpxdp_qsel0_bufp1_ca_l[3]), // Templated
.arbcp6_cpxdp_qsel1_bufp1_ca_1(arbcp6_cpxdp_qsel1_bufp1_ca[3]), // Templated
.arbcp6_cpxdp_shift_bufp1_cx_l_1(arbcp6_cpxdp_shift_bufp1_cx_l[3]), // Templated
.arbcp7_cpxdp_grant_bufp1_ca_l_1(arbcp7_cpxdp_grant_bufp1_ca_l[3]), // Templated
.arbcp7_cpxdp_q0_hold_bufp1_ca_1(arbcp7_cpxdp_q0_hold_bufp1_ca[3]), // Templated
.arbcp7_cpxdp_qsel0_bufp1_ca_l_1(arbcp7_cpxdp_qsel0_bufp1_ca_l[3]), // Templated
.arbcp7_cpxdp_qsel1_bufp1_ca_1(arbcp7_cpxdp_qsel1_bufp1_ca[3]), // Templated
.arbcp7_cpxdp_shift_bufp1_cx_l_1(arbcp7_cpxdp_shift_bufp1_cx_l[3]), // Templated
// Inputs
.fp_cpx_req_bufp0_cq(fp_cpx_req_bufp0_cq[7:0]),
.arbcp0_cpxdp_grant_arbbf_ca_1(arbcp0_cpxdp_grant_arbbf_ca[3]), // Templated
.arbcp0_cpxdp_q0_hold_arbbf_ca_l_1(arbcp0_cpxdp_q0_hold_arbbf_ca_l[3]), // Templated
.arbcp0_cpxdp_qsel0_arbbf_ca_1(arbcp0_cpxdp_qsel0_arbbf_ca[3]), // Templated
.arbcp0_cpxdp_qsel1_arbbf_ca_l_1(arbcp0_cpxdp_qsel1_arbbf_ca_l[3]), // Templated
.arbcp0_cpxdp_shift_arbbf_cx_1(arbcp0_cpxdp_shift_arbbf_cx[3]), // Templated
.arbcp1_cpxdp_grant_arbbf_ca_1(arbcp1_cpxdp_grant_arbbf_ca[3]), // Templated
.arbcp1_cpxdp_q0_hold_arbbf_ca_l_1(arbcp1_cpxdp_q0_hold_arbbf_ca_l[3]), // Templated
.arbcp1_cpxdp_qsel0_arbbf_ca_1(arbcp1_cpxdp_qsel0_arbbf_ca[3]), // Templated
.arbcp1_cpxdp_qsel1_arbbf_ca_l_1(arbcp1_cpxdp_qsel1_arbbf_ca_l[3]), // Templated
.arbcp1_cpxdp_shift_arbbf_cx_1(arbcp1_cpxdp_shift_arbbf_cx[3]), // Templated
.arbcp2_cpxdp_grant_arbbf_ca_1(arbcp2_cpxdp_grant_arbbf_ca[3]), // Templated
.arbcp2_cpxdp_q0_hold_arbbf_ca_l_1(arbcp2_cpxdp_q0_hold_arbbf_ca_l[3]), // Templated
.arbcp2_cpxdp_qsel0_arbbf_ca_1(arbcp2_cpxdp_qsel0_arbbf_ca[3]), // Templated
.arbcp2_cpxdp_qsel1_arbbf_ca_l_1(arbcp2_cpxdp_qsel1_arbbf_ca_l[3]), // Templated
.arbcp2_cpxdp_shift_arbbf_cx_1(arbcp2_cpxdp_shift_arbbf_cx[3]), // Templated
.arbcp3_cpxdp_grant_arbbf_ca_1(arbcp3_cpxdp_grant_arbbf_ca[3]), // Templated
.arbcp3_cpxdp_q0_hold_arbbf_ca_l_1(arbcp3_cpxdp_q0_hold_arbbf_ca_l[3]), // Templated
.arbcp3_cpxdp_qsel0_arbbf_ca_1(arbcp3_cpxdp_qsel0_arbbf_ca[3]), // Templated
.arbcp3_cpxdp_qsel1_arbbf_ca_l_1(arbcp3_cpxdp_qsel1_arbbf_ca_l[3]), // Templated
.arbcp3_cpxdp_shift_arbbf_cx_1(arbcp3_cpxdp_shift_arbbf_cx[3]), // Templated
.arbcp4_cpxdp_grant_arbbf_ca_1(arbcp4_cpxdp_grant_arbbf_ca[3]), // Templated
.arbcp4_cpxdp_q0_hold_arbbf_ca_l_1(arbcp4_cpxdp_q0_hold_arbbf_ca_l[3]), // Templated
.arbcp4_cpxdp_qsel0_arbbf_ca_1(arbcp4_cpxdp_qsel0_arbbf_ca[3]), // Templated
.arbcp4_cpxdp_qsel1_arbbf_ca_l_1(arbcp4_cpxdp_qsel1_arbbf_ca_l[3]), // Templated
.arbcp4_cpxdp_shift_arbbf_cx_1(arbcp4_cpxdp_shift_arbbf_cx[3]), // Templated
.arbcp5_cpxdp_grant_arbbf_ca_1(arbcp5_cpxdp_grant_arbbf_ca[3]), // Templated
.arbcp5_cpxdp_q0_hold_arbbf_ca_l_1(arbcp5_cpxdp_q0_hold_arbbf_ca_l[3]), // Templated
.arbcp5_cpxdp_qsel0_arbbf_ca_1(arbcp5_cpxdp_qsel0_arbbf_ca[3]), // Templated
.arbcp5_cpxdp_qsel1_arbbf_ca_l_1(arbcp5_cpxdp_qsel1_arbbf_ca_l[3]), // Templated
.arbcp5_cpxdp_shift_arbbf_cx_1(arbcp5_cpxdp_shift_arbbf_cx[3]), // Templated
.arbcp6_cpxdp_grant_arbbf_ca_1(arbcp6_cpxdp_grant_arbbf_ca[3]), // Templated
.arbcp6_cpxdp_q0_hold_arbbf_ca_l_1(arbcp6_cpxdp_q0_hold_arbbf_ca_l[3]), // Templated
.arbcp6_cpxdp_qsel0_arbbf_ca_1(arbcp6_cpxdp_qsel0_arbbf_ca[3]), // Templated
.arbcp6_cpxdp_qsel1_arbbf_ca_l_1(arbcp6_cpxdp_qsel1_arbbf_ca_l[3]), // Templated
.arbcp6_cpxdp_shift_arbbf_cx_1(arbcp6_cpxdp_shift_arbbf_cx[3]), // Templated
.arbcp7_cpxdp_grant_arbbf_ca_1(arbcp7_cpxdp_grant_arbbf_ca[3]), // Templated
.arbcp7_cpxdp_q0_hold_arbbf_ca_l_1(arbcp7_cpxdp_q0_hold_arbbf_ca_l[3]), // Templated
.arbcp7_cpxdp_qsel0_arbbf_ca_1(arbcp7_cpxdp_qsel0_arbbf_ca[3]), // Templated
.arbcp7_cpxdp_qsel1_arbbf_ca_l_1(arbcp7_cpxdp_qsel1_arbbf_ca_l[3]), // Templated
.arbcp7_cpxdp_shift_arbbf_cx_1(arbcp7_cpxdp_shift_arbbf_cx[3])); // Templated
/* cpx_buf_pdl_even AUTO_TEMPLATE(
// Outputs
.arbcp0_cpxdp_grant_ca(arbcp0_cpxdp_grant_ca[5]),
.arbcp0_cpxdp_q0_hold_ca_l(arbcp0_cpxdp_q0_hold_ca_l[5]),
.arbcp0_cpxdp_qsel0_ca(arbcp0_cpxdp_qsel0_ca[5]),
.arbcp0_cpxdp_qsel1_ca_l(arbcp0_cpxdp_qsel1_ca_l[5]),
.arbcp0_cpxdp_shift_cx(arbcp0_cpxdp_shift_cx[5]),
.arbcp2_cpxdp_grant_ca(arbcp2_cpxdp_grant_ca[5]),
.arbcp2_cpxdp_q0_hold_ca_l(arbcp2_cpxdp_q0_hold_ca_l[5]),
.arbcp2_cpxdp_qsel0_ca(arbcp2_cpxdp_qsel0_ca[5]),
.arbcp2_cpxdp_qsel1_ca_l(arbcp2_cpxdp_qsel1_ca_l[5]),
.arbcp2_cpxdp_shift_cx(arbcp2_cpxdp_shift_cx[5]),
.arbcp4_cpxdp_grant_ca(arbcp4_cpxdp_grant_ca[5]),
.arbcp4_cpxdp_q0_hold_ca_l(arbcp4_cpxdp_q0_hold_ca_l[5]),
.arbcp4_cpxdp_qsel0_ca(arbcp4_cpxdp_qsel0_ca[5]),
.arbcp4_cpxdp_qsel1_ca_l(arbcp4_cpxdp_qsel1_ca_l[5]),
.arbcp4_cpxdp_shift_cx(arbcp4_cpxdp_shift_cx[5]),
.arbcp6_cpxdp_grant_ca(arbcp6_cpxdp_grant_ca[5]),
.arbcp6_cpxdp_q0_hold_ca_l(arbcp6_cpxdp_q0_hold_ca_l[5]),
.arbcp6_cpxdp_qsel0_ca(arbcp6_cpxdp_qsel0_ca[5]),
.arbcp6_cpxdp_qsel1_ca_l(arbcp6_cpxdp_qsel1_ca_l[5]),
.arbcp6_cpxdp_shift_cx(arbcp6_cpxdp_shift_cx[5]),
// Inputs
.arbcp0_cpxdp_grant_bufp1_ca_l(arbcp0_cpxdp_grant_bufp3_ca_l[5]),
.arbcp0_cpxdp_q0_hold_bufp1_ca(arbcp0_cpxdp_q0_hold_bufp3_ca[5]),
.arbcp0_cpxdp_qsel0_bufp1_ca_l(arbcp0_cpxdp_qsel0_bufp3_ca_l[5]),
.arbcp0_cpxdp_qsel1_bufp1_ca(arbcp0_cpxdp_qsel1_bufp3_ca[5]),
.arbcp0_cpxdp_shift_bufp1_cx_l(arbcp0_cpxdp_shift_bufp3_cx_l[5]),
.arbcp2_cpxdp_grant_bufp1_ca_l(arbcp2_cpxdp_grant_bufp3_ca_l[5]),
.arbcp2_cpxdp_q0_hold_bufp1_ca(arbcp2_cpxdp_q0_hold_bufp3_ca[5]),
.arbcp2_cpxdp_qsel0_bufp1_ca_l(arbcp2_cpxdp_qsel0_bufp3_ca_l[5]),
.arbcp2_cpxdp_qsel1_bufp1_ca(arbcp2_cpxdp_qsel1_bufp3_ca[5]),
.arbcp2_cpxdp_shift_bufp1_cx_l(arbcp2_cpxdp_shift_bufp3_cx_l[5]),
.arbcp4_cpxdp_grant_bufp1_ca_l(arbcp4_cpxdp_grant_bufp3_ca_l[5]),
.arbcp4_cpxdp_q0_hold_bufp1_ca(arbcp4_cpxdp_q0_hold_bufp3_ca[5]),
.arbcp4_cpxdp_qsel0_bufp1_ca_l(arbcp4_cpxdp_qsel0_bufp3_ca_l[5]),
.arbcp4_cpxdp_qsel1_bufp1_ca(arbcp4_cpxdp_qsel1_bufp3_ca[5]),
.arbcp4_cpxdp_shift_bufp1_cx_l(arbcp4_cpxdp_shift_bufp3_cx_l[5]),
.arbcp6_cpxdp_grant_bufp1_ca_l(arbcp6_cpxdp_grant_bufp3_ca_l[5]),
.arbcp6_cpxdp_q0_hold_bufp1_ca(arbcp6_cpxdp_q0_hold_bufp3_ca[5]),
.arbcp6_cpxdp_qsel0_bufp1_ca_l(arbcp6_cpxdp_qsel0_bufp3_ca_l[5]),
.arbcp6_cpxdp_qsel1_bufp1_ca(arbcp6_cpxdp_qsel1_bufp3_ca[5]),
.arbcp6_cpxdp_shift_bufp1_cx_l(arbcp6_cpxdp_shift_bufp3_cx_l[5]));
*/
cpx_buf_pdl_even pdl_even(/*AUTOINST*/
// Outputs
.arbcp0_cpxdp_grant_ca(arbcp0_cpxdp_grant_ca[5]), // Templated
.arbcp0_cpxdp_q0_hold_ca_l(arbcp0_cpxdp_q0_hold_ca_l[5]), // Templated
.arbcp0_cpxdp_qsel0_ca(arbcp0_cpxdp_qsel0_ca[5]), // Templated
.arbcp0_cpxdp_qsel1_ca_l(arbcp0_cpxdp_qsel1_ca_l[5]), // Templated
.arbcp0_cpxdp_shift_cx(arbcp0_cpxdp_shift_cx[5]), // Templated
.arbcp2_cpxdp_grant_ca(arbcp2_cpxdp_grant_ca[5]), // Templated
.arbcp2_cpxdp_q0_hold_ca_l(arbcp2_cpxdp_q0_hold_ca_l[5]), // Templated
.arbcp2_cpxdp_qsel0_ca(arbcp2_cpxdp_qsel0_ca[5]), // Templated
.arbcp2_cpxdp_qsel1_ca_l(arbcp2_cpxdp_qsel1_ca_l[5]), // Templated
.arbcp2_cpxdp_shift_cx(arbcp2_cpxdp_shift_cx[5]), // Templated
.arbcp4_cpxdp_grant_ca(arbcp4_cpxdp_grant_ca[5]), // Templated
.arbcp4_cpxdp_q0_hold_ca_l(arbcp4_cpxdp_q0_hold_ca_l[5]), // Templated
.arbcp4_cpxdp_qsel0_ca(arbcp4_cpxdp_qsel0_ca[5]), // Templated
.arbcp4_cpxdp_qsel1_ca_l(arbcp4_cpxdp_qsel1_ca_l[5]), // Templated
.arbcp4_cpxdp_shift_cx(arbcp4_cpxdp_shift_cx[5]), // Templated
.arbcp6_cpxdp_grant_ca(arbcp6_cpxdp_grant_ca[5]), // Templated
.arbcp6_cpxdp_q0_hold_ca_l(arbcp6_cpxdp_q0_hold_ca_l[5]), // Templated
.arbcp6_cpxdp_qsel0_ca(arbcp6_cpxdp_qsel0_ca[5]), // Templated
.arbcp6_cpxdp_qsel1_ca_l(arbcp6_cpxdp_qsel1_ca_l[5]), // Templated
.arbcp6_cpxdp_shift_cx(arbcp6_cpxdp_shift_cx[5]), // Templated
// Inputs
.arbcp0_cpxdp_grant_bufp1_ca_l(arbcp0_cpxdp_grant_bufp3_ca_l[5]), // Templated
.arbcp0_cpxdp_q0_hold_bufp1_ca(arbcp0_cpxdp_q0_hold_bufp3_ca[5]), // Templated
.arbcp0_cpxdp_qsel0_bufp1_ca_l(arbcp0_cpxdp_qsel0_bufp3_ca_l[5]), // Templated
.arbcp0_cpxdp_qsel1_bufp1_ca(arbcp0_cpxdp_qsel1_bufp3_ca[5]), // Templated
.arbcp0_cpxdp_shift_bufp1_cx_l(arbcp0_cpxdp_shift_bufp3_cx_l[5]), // Templated
.arbcp2_cpxdp_grant_bufp1_ca_l(arbcp2_cpxdp_grant_bufp3_ca_l[5]), // Templated
.arbcp2_cpxdp_q0_hold_bufp1_ca(arbcp2_cpxdp_q0_hold_bufp3_ca[5]), // Templated
.arbcp2_cpxdp_qsel0_bufp1_ca_l(arbcp2_cpxdp_qsel0_bufp3_ca_l[5]), // Templated
.arbcp2_cpxdp_qsel1_bufp1_ca(arbcp2_cpxdp_qsel1_bufp3_ca[5]), // Templated
.arbcp2_cpxdp_shift_bufp1_cx_l(arbcp2_cpxdp_shift_bufp3_cx_l[5]), // Templated
.arbcp4_cpxdp_grant_bufp1_ca_l(arbcp4_cpxdp_grant_bufp3_ca_l[5]), // Templated
.arbcp4_cpxdp_q0_hold_bufp1_ca(arbcp4_cpxdp_q0_hold_bufp3_ca[5]), // Templated
.arbcp4_cpxdp_qsel0_bufp1_ca_l(arbcp4_cpxdp_qsel0_bufp3_ca_l[5]), // Templated
.arbcp4_cpxdp_qsel1_bufp1_ca(arbcp4_cpxdp_qsel1_bufp3_ca[5]), // Templated
.arbcp4_cpxdp_shift_bufp1_cx_l(arbcp4_cpxdp_shift_bufp3_cx_l[5]), // Templated
.arbcp6_cpxdp_grant_bufp1_ca_l(arbcp6_cpxdp_grant_bufp3_ca_l[5]), // Templated
.arbcp6_cpxdp_q0_hold_bufp1_ca(arbcp6_cpxdp_q0_hold_bufp3_ca[5]), // Templated
.arbcp6_cpxdp_qsel0_bufp1_ca_l(arbcp6_cpxdp_qsel0_bufp3_ca_l[5]), // Templated
.arbcp6_cpxdp_qsel1_bufp1_ca(arbcp6_cpxdp_qsel1_bufp3_ca[5]), // Templated
.arbcp6_cpxdp_shift_bufp1_cx_l(arbcp6_cpxdp_shift_bufp3_cx_l[5])); // Templated
/* cpx_buf_pdl_even AUTO_TEMPLATE(
// Outputs
.arbcp0_cpxdp_grant_ca(arbcp1_cpxdp_grant_ca[5]),
.arbcp0_cpxdp_q0_hold_ca_l(arbcp1_cpxdp_q0_hold_ca_l[5]),
.arbcp0_cpxdp_qsel0_ca(arbcp1_cpxdp_qsel0_ca[5]),
.arbcp0_cpxdp_qsel1_ca_l(arbcp1_cpxdp_qsel1_ca_l[5]),
.arbcp0_cpxdp_shift_cx(arbcp1_cpxdp_shift_cx[5]),
.arbcp2_cpxdp_grant_ca(arbcp3_cpxdp_grant_ca[5]),
.arbcp2_cpxdp_q0_hold_ca_l(arbcp3_cpxdp_q0_hold_ca_l[5]),
.arbcp2_cpxdp_qsel0_ca(arbcp3_cpxdp_qsel0_ca[5]),
.arbcp2_cpxdp_qsel1_ca_l(arbcp3_cpxdp_qsel1_ca_l[5]),
.arbcp2_cpxdp_shift_cx(arbcp3_cpxdp_shift_cx[5]),
.arbcp4_cpxdp_grant_ca(arbcp5_cpxdp_grant_ca[5]),
.arbcp4_cpxdp_q0_hold_ca_l(arbcp5_cpxdp_q0_hold_ca_l[5]),
.arbcp4_cpxdp_qsel0_ca(arbcp5_cpxdp_qsel0_ca[5]),
.arbcp4_cpxdp_qsel1_ca_l(arbcp5_cpxdp_qsel1_ca_l[5]),
.arbcp4_cpxdp_shift_cx(arbcp5_cpxdp_shift_cx[5]),
.arbcp6_cpxdp_grant_ca(arbcp7_cpxdp_grant_ca[5]),
.arbcp6_cpxdp_q0_hold_ca_l(arbcp7_cpxdp_q0_hold_ca_l[5]),
.arbcp6_cpxdp_qsel0_ca(arbcp7_cpxdp_qsel0_ca[5]),
.arbcp6_cpxdp_qsel1_ca_l(arbcp7_cpxdp_qsel1_ca_l[5]),
.arbcp6_cpxdp_shift_cx(arbcp7_cpxdp_shift_cx[5]),
// Inputs
.arbcp0_cpxdp_grant_bufp1_ca_l(arbcp1_cpxdp_grant_bufp3_ca_l[5]),
.arbcp0_cpxdp_q0_hold_bufp1_ca(arbcp1_cpxdp_q0_hold_bufp3_ca[5]),
.arbcp0_cpxdp_qsel0_bufp1_ca_l(arbcp1_cpxdp_qsel0_bufp3_ca_l[5]),
.arbcp0_cpxdp_qsel1_bufp1_ca(arbcp1_cpxdp_qsel1_bufp3_ca[5]),
.arbcp0_cpxdp_shift_bufp1_cx_l(arbcp1_cpxdp_shift_bufp3_cx_l[5]),
.arbcp2_cpxdp_grant_bufp1_ca_l(arbcp3_cpxdp_grant_bufp3_ca_l[5]),
.arbcp2_cpxdp_q0_hold_bufp1_ca(arbcp3_cpxdp_q0_hold_bufp3_ca[5]),
.arbcp2_cpxdp_qsel0_bufp1_ca_l(arbcp3_cpxdp_qsel0_bufp3_ca_l[5]),
.arbcp2_cpxdp_qsel1_bufp1_ca(arbcp3_cpxdp_qsel1_bufp3_ca[5]),
.arbcp2_cpxdp_shift_bufp1_cx_l(arbcp3_cpxdp_shift_bufp3_cx_l[5]),
.arbcp4_cpxdp_grant_bufp1_ca_l(arbcp5_cpxdp_grant_bufp3_ca_l[5]),
.arbcp4_cpxdp_q0_hold_bufp1_ca(arbcp5_cpxdp_q0_hold_bufp3_ca[5]),
.arbcp4_cpxdp_qsel0_bufp1_ca_l(arbcp5_cpxdp_qsel0_bufp3_ca_l[5]),
.arbcp4_cpxdp_qsel1_bufp1_ca(arbcp5_cpxdp_qsel1_bufp3_ca[5]),
.arbcp4_cpxdp_shift_bufp1_cx_l(arbcp5_cpxdp_shift_bufp3_cx_l[5]),
.arbcp6_cpxdp_grant_bufp1_ca_l(arbcp7_cpxdp_grant_bufp3_ca_l[5]),
.arbcp6_cpxdp_q0_hold_bufp1_ca(arbcp7_cpxdp_q0_hold_bufp3_ca[5]),
.arbcp6_cpxdp_qsel0_bufp1_ca_l(arbcp7_cpxdp_qsel0_bufp3_ca_l[5]),
.arbcp6_cpxdp_qsel1_bufp1_ca(arbcp7_cpxdp_qsel1_bufp3_ca[5]),
.arbcp6_cpxdp_shift_bufp1_cx_l(arbcp7_cpxdp_shift_bufp3_cx_l[5]));
*/
cpx_buf_pdl_even pdl_odd(/*AUTOINST*/
// Outputs
.arbcp0_cpxdp_grant_ca(arbcp1_cpxdp_grant_ca[5]), // Templated
.arbcp0_cpxdp_q0_hold_ca_l(arbcp1_cpxdp_q0_hold_ca_l[5]), // Templated
.arbcp0_cpxdp_qsel0_ca(arbcp1_cpxdp_qsel0_ca[5]), // Templated
.arbcp0_cpxdp_qsel1_ca_l(arbcp1_cpxdp_qsel1_ca_l[5]), // Templated
.arbcp0_cpxdp_shift_cx(arbcp1_cpxdp_shift_cx[5]), // Templated
.arbcp2_cpxdp_grant_ca(arbcp3_cpxdp_grant_ca[5]), // Templated
.arbcp2_cpxdp_q0_hold_ca_l(arbcp3_cpxdp_q0_hold_ca_l[5]), // Templated
.arbcp2_cpxdp_qsel0_ca(arbcp3_cpxdp_qsel0_ca[5]), // Templated
.arbcp2_cpxdp_qsel1_ca_l(arbcp3_cpxdp_qsel1_ca_l[5]), // Templated
.arbcp2_cpxdp_shift_cx(arbcp3_cpxdp_shift_cx[5]), // Templated
.arbcp4_cpxdp_grant_ca(arbcp5_cpxdp_grant_ca[5]), // Templated
.arbcp4_cpxdp_q0_hold_ca_l(arbcp5_cpxdp_q0_hold_ca_l[5]), // Templated
.arbcp4_cpxdp_qsel0_ca(arbcp5_cpxdp_qsel0_ca[5]), // Templated
.arbcp4_cpxdp_qsel1_ca_l(arbcp5_cpxdp_qsel1_ca_l[5]), // Templated
.arbcp4_cpxdp_shift_cx(arbcp5_cpxdp_shift_cx[5]), // Templated
.arbcp6_cpxdp_grant_ca(arbcp7_cpxdp_grant_ca[5]), // Templated
.arbcp6_cpxdp_q0_hold_ca_l(arbcp7_cpxdp_q0_hold_ca_l[5]), // Templated
.arbcp6_cpxdp_qsel0_ca(arbcp7_cpxdp_qsel0_ca[5]), // Templated
.arbcp6_cpxdp_qsel1_ca_l(arbcp7_cpxdp_qsel1_ca_l[5]), // Templated
.arbcp6_cpxdp_shift_cx(arbcp7_cpxdp_shift_cx[5]), // Templated
// Inputs
.arbcp0_cpxdp_grant_bufp1_ca_l(arbcp1_cpxdp_grant_bufp3_ca_l[5]), // Templated
.arbcp0_cpxdp_q0_hold_bufp1_ca(arbcp1_cpxdp_q0_hold_bufp3_ca[5]), // Templated
.arbcp0_cpxdp_qsel0_bufp1_ca_l(arbcp1_cpxdp_qsel0_bufp3_ca_l[5]), // Templated
.arbcp0_cpxdp_qsel1_bufp1_ca(arbcp1_cpxdp_qsel1_bufp3_ca[5]), // Templated
.arbcp0_cpxdp_shift_bufp1_cx_l(arbcp1_cpxdp_shift_bufp3_cx_l[5]), // Templated
.arbcp2_cpxdp_grant_bufp1_ca_l(arbcp3_cpxdp_grant_bufp3_ca_l[5]), // Templated
.arbcp2_cpxdp_q0_hold_bufp1_ca(arbcp3_cpxdp_q0_hold_bufp3_ca[5]), // Templated
.arbcp2_cpxdp_qsel0_bufp1_ca_l(arbcp3_cpxdp_qsel0_bufp3_ca_l[5]), // Templated
.arbcp2_cpxdp_qsel1_bufp1_ca(arbcp3_cpxdp_qsel1_bufp3_ca[5]), // Templated
.arbcp2_cpxdp_shift_bufp1_cx_l(arbcp3_cpxdp_shift_bufp3_cx_l[5]), // Templated
.arbcp4_cpxdp_grant_bufp1_ca_l(arbcp5_cpxdp_grant_bufp3_ca_l[5]), // Templated
.arbcp4_cpxdp_q0_hold_bufp1_ca(arbcp5_cpxdp_q0_hold_bufp3_ca[5]), // Templated
.arbcp4_cpxdp_qsel0_bufp1_ca_l(arbcp5_cpxdp_qsel0_bufp3_ca_l[5]), // Templated
.arbcp4_cpxdp_qsel1_bufp1_ca(arbcp5_cpxdp_qsel1_bufp3_ca[5]), // Templated
.arbcp4_cpxdp_shift_bufp1_cx_l(arbcp5_cpxdp_shift_bufp3_cx_l[5]), // Templated
.arbcp6_cpxdp_grant_bufp1_ca_l(arbcp7_cpxdp_grant_bufp3_ca_l[5]), // Templated
.arbcp6_cpxdp_q0_hold_bufp1_ca(arbcp7_cpxdp_q0_hold_bufp3_ca[5]), // Templated
.arbcp6_cpxdp_qsel0_bufp1_ca_l(arbcp7_cpxdp_qsel0_bufp3_ca_l[5]), // Templated
.arbcp6_cpxdp_qsel1_bufp1_ca(arbcp7_cpxdp_qsel1_bufp3_ca[5]), // Templated
.arbcp6_cpxdp_shift_bufp1_cx_l(arbcp7_cpxdp_shift_bufp3_cx_l[5])); // Templated
/* cpx_buf_p3 AUTO_TEMPLATE(
//Outputs
.arbcp0_cpxdp_grant_bufp3_ca_l_5(arbcp0_cpxdp_grant_bufp3_ca_l[5]),
.arbcp0_cpxdp_q0_hold_bufp3_ca_5(arbcp0_cpxdp_q0_hold_bufp3_ca[5]),
.arbcp0_cpxdp_qsel0_bufp3_ca_l_5(arbcp0_cpxdp_qsel0_bufp3_ca_l[5]),
.arbcp0_cpxdp_qsel1_bufp3_ca_5(arbcp0_cpxdp_qsel1_bufp3_ca[5]),
.arbcp0_cpxdp_shift_bufp3_cx_l_5(arbcp0_cpxdp_shift_bufp3_cx_l[5]),
.arbcp1_cpxdp_grant_bufp3_ca_l_5(arbcp1_cpxdp_grant_bufp3_ca_l[5]),
.arbcp1_cpxdp_q0_hold_bufp3_ca_5(arbcp1_cpxdp_q0_hold_bufp3_ca[5]),
.arbcp1_cpxdp_qsel0_bufp3_ca_l_5(arbcp1_cpxdp_qsel0_bufp3_ca_l[5]),
.arbcp1_cpxdp_qsel1_bufp3_ca_5(arbcp1_cpxdp_qsel1_bufp3_ca[5]),
.arbcp1_cpxdp_shift_bufp3_cx_l_5(arbcp1_cpxdp_shift_bufp3_cx_l[5]),
.arbcp2_cpxdp_grant_bufp3_ca_l_5(arbcp2_cpxdp_grant_bufp3_ca_l[5]),
.arbcp2_cpxdp_q0_hold_bufp3_ca_5(arbcp2_cpxdp_q0_hold_bufp3_ca[5]),
.arbcp2_cpxdp_qsel0_bufp3_ca_l_5(arbcp2_cpxdp_qsel0_bufp3_ca_l[5]),
.arbcp2_cpxdp_qsel1_bufp3_ca_5(arbcp2_cpxdp_qsel1_bufp3_ca[5]),
.arbcp2_cpxdp_shift_bufp3_cx_l_5(arbcp2_cpxdp_shift_bufp3_cx_l[5]),
.arbcp3_cpxdp_grant_bufp3_ca_l_5(arbcp3_cpxdp_grant_bufp3_ca_l[5]),
.arbcp3_cpxdp_q0_hold_bufp3_ca_5(arbcp3_cpxdp_q0_hold_bufp3_ca[5]),
.arbcp3_cpxdp_qsel0_bufp3_ca_l_5(arbcp3_cpxdp_qsel0_bufp3_ca_l[5]),
.arbcp3_cpxdp_qsel1_bufp3_ca_5(arbcp3_cpxdp_qsel1_bufp3_ca[5]),
.arbcp3_cpxdp_shift_bufp3_cx_l_5(arbcp3_cpxdp_shift_bufp3_cx_l[5]),
.arbcp4_cpxdp_grant_bufp3_ca_l_5(arbcp4_cpxdp_grant_bufp3_ca_l[5]),
.arbcp4_cpxdp_q0_hold_bufp3_ca_5(arbcp4_cpxdp_q0_hold_bufp3_ca[5]),
.arbcp4_cpxdp_qsel0_bufp3_ca_l_5(arbcp4_cpxdp_qsel0_bufp3_ca_l[5]),
.arbcp4_cpxdp_qsel1_bufp3_ca_5(arbcp4_cpxdp_qsel1_bufp3_ca[5]),
.arbcp4_cpxdp_shift_bufp3_cx_l_5(arbcp4_cpxdp_shift_bufp3_cx_l[5]),
.arbcp5_cpxdp_grant_bufp3_ca_l_5(arbcp5_cpxdp_grant_bufp3_ca_l[5]),
.arbcp5_cpxdp_q0_hold_bufp3_ca_5(arbcp5_cpxdp_q0_hold_bufp3_ca[5]),
.arbcp5_cpxdp_qsel0_bufp3_ca_l_5(arbcp5_cpxdp_qsel0_bufp3_ca_l[5]),
.arbcp5_cpxdp_qsel1_bufp3_ca_5(arbcp5_cpxdp_qsel1_bufp3_ca[5]),
.arbcp5_cpxdp_shift_bufp3_cx_l_5(arbcp5_cpxdp_shift_bufp3_cx_l[5]),
.arbcp6_cpxdp_grant_bufp3_ca_l_5(arbcp6_cpxdp_grant_bufp3_ca_l[5]),
.arbcp6_cpxdp_q0_hold_bufp3_ca_5(arbcp6_cpxdp_q0_hold_bufp3_ca[5]),
.arbcp6_cpxdp_qsel0_bufp3_ca_l_5(arbcp6_cpxdp_qsel0_bufp3_ca_l[5]),
.arbcp6_cpxdp_qsel1_bufp3_ca_5(arbcp6_cpxdp_qsel1_bufp3_ca[5]),
.arbcp6_cpxdp_shift_bufp3_cx_l_5(arbcp6_cpxdp_shift_bufp3_cx_l[5]),
.arbcp7_cpxdp_grant_bufp3_ca_l_5(arbcp7_cpxdp_grant_bufp3_ca_l[5]),
.arbcp7_cpxdp_q0_hold_bufp3_ca_5(arbcp7_cpxdp_q0_hold_bufp3_ca[5]),
.arbcp7_cpxdp_qsel0_bufp3_ca_l_5(arbcp7_cpxdp_qsel0_bufp3_ca_l[5]),
.arbcp7_cpxdp_qsel1_bufp3_ca_5(arbcp7_cpxdp_qsel1_bufp3_ca[5]),
.arbcp7_cpxdp_shift_bufp3_cx_l_5(arbcp7_cpxdp_shift_bufp3_cx_l[5]),
.arbcp0_cpxdp_grant_bufp3_ca_l_2(arbcp0_cpxdp_grant_bufp3_ca_l[2]),
.arbcp0_cpxdp_q0_hold_bufp3_ca_2(arbcp0_cpxdp_q0_hold_bufp3_ca[2]),
.arbcp0_cpxdp_qsel0_bufp3_ca_l_2(arbcp0_cpxdp_qsel0_bufp3_ca_l[2]),
.arbcp0_cpxdp_qsel1_bufp3_ca_2(arbcp0_cpxdp_qsel1_bufp3_ca[2]),
.arbcp0_cpxdp_shift_bufp3_cx_l_2(arbcp0_cpxdp_shift_bufp3_cx_l[2]),
.arbcp1_cpxdp_grant_bufp3_ca_l_2(arbcp1_cpxdp_grant_bufp3_ca_l[2]),
.arbcp1_cpxdp_q0_hold_bufp3_ca_2(arbcp1_cpxdp_q0_hold_bufp3_ca[2]),
.arbcp1_cpxdp_qsel0_bufp3_ca_l_2(arbcp1_cpxdp_qsel0_bufp3_ca_l[2]),
.arbcp1_cpxdp_qsel1_bufp3_ca_2(arbcp1_cpxdp_qsel1_bufp3_ca[2]),
.arbcp1_cpxdp_shift_bufp3_cx_l_2(arbcp1_cpxdp_shift_bufp3_cx_l[2]),
.arbcp2_cpxdp_grant_bufp3_ca_l_2(arbcp2_cpxdp_grant_bufp3_ca_l[2]),
.arbcp2_cpxdp_q0_hold_bufp3_ca_2(arbcp2_cpxdp_q0_hold_bufp3_ca[2]),
.arbcp2_cpxdp_qsel0_bufp3_ca_l_2(arbcp2_cpxdp_qsel0_bufp3_ca_l[2]),
.arbcp2_cpxdp_qsel1_bufp3_ca_2(arbcp2_cpxdp_qsel1_bufp3_ca[2]),
.arbcp2_cpxdp_shift_bufp3_cx_l_2(arbcp2_cpxdp_shift_bufp3_cx_l[2]),
.arbcp3_cpxdp_grant_bufp3_ca_l_2(arbcp3_cpxdp_grant_bufp3_ca_l[2]),
.arbcp3_cpxdp_q0_hold_bufp3_ca_2(arbcp3_cpxdp_q0_hold_bufp3_ca[2]),
.arbcp3_cpxdp_qsel0_bufp3_ca_l_2(arbcp3_cpxdp_qsel0_bufp3_ca_l[2]),
.arbcp3_cpxdp_qsel1_bufp3_ca_2(arbcp3_cpxdp_qsel1_bufp3_ca[2]),
.arbcp3_cpxdp_shift_bufp3_cx_l_2(arbcp3_cpxdp_shift_bufp3_cx_l[2]),
.arbcp4_cpxdp_grant_bufp3_ca_l_2(arbcp4_cpxdp_grant_bufp3_ca_l[2]),
.arbcp4_cpxdp_q0_hold_bufp3_ca_2(arbcp4_cpxdp_q0_hold_bufp3_ca[2]),
.arbcp4_cpxdp_qsel0_bufp3_ca_l_2(arbcp4_cpxdp_qsel0_bufp3_ca_l[2]),
.arbcp4_cpxdp_qsel1_bufp3_ca_2(arbcp4_cpxdp_qsel1_bufp3_ca[2]),
.arbcp4_cpxdp_shift_bufp3_cx_l_2(arbcp4_cpxdp_shift_bufp3_cx_l[2]),
.arbcp5_cpxdp_grant_bufp3_ca_l_2(arbcp5_cpxdp_grant_bufp3_ca_l[2]),
.arbcp5_cpxdp_q0_hold_bufp3_ca_2(arbcp5_cpxdp_q0_hold_bufp3_ca[2]),
.arbcp5_cpxdp_qsel0_bufp3_ca_l_2(arbcp5_cpxdp_qsel0_bufp3_ca_l[2]),
.arbcp5_cpxdp_qsel1_bufp3_ca_2(arbcp5_cpxdp_qsel1_bufp3_ca[2]),
.arbcp5_cpxdp_shift_bufp3_cx_l_2(arbcp5_cpxdp_shift_bufp3_cx_l[2]),
.arbcp6_cpxdp_grant_bufp3_ca_l_2(arbcp6_cpxdp_grant_bufp3_ca_l[2]),
.arbcp6_cpxdp_q0_hold_bufp3_ca_2(arbcp6_cpxdp_q0_hold_bufp3_ca[2]),
.arbcp6_cpxdp_qsel0_bufp3_ca_l_2(arbcp6_cpxdp_qsel0_bufp3_ca_l[2]),
.arbcp6_cpxdp_qsel1_bufp3_ca_2(arbcp6_cpxdp_qsel1_bufp3_ca[2]),
.arbcp6_cpxdp_shift_bufp3_cx_l_2(arbcp6_cpxdp_shift_bufp3_cx_l[2]),
.arbcp7_cpxdp_grant_bufp3_ca_l_2(arbcp7_cpxdp_grant_bufp3_ca_l[2]),
.arbcp7_cpxdp_q0_hold_bufp3_ca_2(arbcp7_cpxdp_q0_hold_bufp3_ca[2]),
.arbcp7_cpxdp_qsel0_bufp3_ca_l_2(arbcp7_cpxdp_qsel0_bufp3_ca_l[2]),
.arbcp7_cpxdp_qsel1_bufp3_ca_2(arbcp7_cpxdp_qsel1_bufp3_ca[2]),
.arbcp7_cpxdp_shift_bufp3_cx_l_2(arbcp7_cpxdp_shift_bufp3_cx_l[2]),
//Inputs
.arbcp0_cpxdp_grant_arbbf_ca_5(arbcp0_cpxdp_grant_arbbf_ca[5]),
.arbcp0_cpxdp_q0_hold_arbbf_ca_l_5(arbcp0_cpxdp_q0_hold_arbbf_ca_l[5]),
.arbcp0_cpxdp_qsel0_arbbf_ca_5(arbcp0_cpxdp_qsel0_arbbf_ca[5]),
.arbcp0_cpxdp_qsel1_arbbf_ca_l_5(arbcp0_cpxdp_qsel1_arbbf_ca_l[5]),
.arbcp0_cpxdp_shift_arbbf_cx_5(arbcp0_cpxdp_shift_arbbf_cx[5]),
.arbcp1_cpxdp_grant_arbbf_ca_5(arbcp1_cpxdp_grant_arbbf_ca[5]),
.arbcp1_cpxdp_q0_hold_arbbf_ca_l_5(arbcp1_cpxdp_q0_hold_arbbf_ca_l[5]),
.arbcp1_cpxdp_qsel0_arbbf_ca_5(arbcp1_cpxdp_qsel0_arbbf_ca[5]),
.arbcp1_cpxdp_qsel1_arbbf_ca_l_5(arbcp1_cpxdp_qsel1_arbbf_ca_l[5]),
.arbcp1_cpxdp_shift_arbbf_cx_5(arbcp1_cpxdp_shift_arbbf_cx[5]),
.arbcp2_cpxdp_grant_arbbf_ca_5(arbcp2_cpxdp_grant_arbbf_ca[5]),
.arbcp2_cpxdp_q0_hold_arbbf_ca_l_5(arbcp2_cpxdp_q0_hold_arbbf_ca_l[5]),
.arbcp2_cpxdp_qsel0_arbbf_ca_5(arbcp2_cpxdp_qsel0_arbbf_ca[5]),
.arbcp2_cpxdp_qsel1_arbbf_ca_l_5(arbcp2_cpxdp_qsel1_arbbf_ca_l[5]),
.arbcp2_cpxdp_shift_arbbf_cx_5(arbcp2_cpxdp_shift_arbbf_cx[5]),
.arbcp3_cpxdp_grant_arbbf_ca_5(arbcp3_cpxdp_grant_arbbf_ca[5]),
.arbcp3_cpxdp_q0_hold_arbbf_ca_l_5(arbcp3_cpxdp_q0_hold_arbbf_ca_l[5]),
.arbcp3_cpxdp_qsel0_arbbf_ca_5(arbcp3_cpxdp_qsel0_arbbf_ca[5]),
.arbcp3_cpxdp_qsel1_arbbf_ca_l_5(arbcp3_cpxdp_qsel1_arbbf_ca_l[5]),
.arbcp3_cpxdp_shift_arbbf_cx_5(arbcp3_cpxdp_shift_arbbf_cx[5]),
.arbcp4_cpxdp_grant_arbbf_ca_5(arbcp4_cpxdp_grant_arbbf_ca[5]),
.arbcp4_cpxdp_q0_hold_arbbf_ca_l_5(arbcp4_cpxdp_q0_hold_arbbf_ca_l[5]),
.arbcp4_cpxdp_qsel0_arbbf_ca_5(arbcp4_cpxdp_qsel0_arbbf_ca[5]),
.arbcp4_cpxdp_qsel1_arbbf_ca_l_5(arbcp4_cpxdp_qsel1_arbbf_ca_l[5]),
.arbcp4_cpxdp_shift_arbbf_cx_5(arbcp4_cpxdp_shift_arbbf_cx[5]),
.arbcp5_cpxdp_grant_arbbf_ca_5(arbcp5_cpxdp_grant_arbbf_ca[5]),
.arbcp5_cpxdp_q0_hold_arbbf_ca_l_5(arbcp5_cpxdp_q0_hold_arbbf_ca_l[5]),
.arbcp5_cpxdp_qsel0_arbbf_ca_5(arbcp5_cpxdp_qsel0_arbbf_ca[5]),
.arbcp5_cpxdp_qsel1_arbbf_ca_l_5(arbcp5_cpxdp_qsel1_arbbf_ca_l[5]),
.arbcp5_cpxdp_shift_arbbf_cx_5(arbcp5_cpxdp_shift_arbbf_cx[5]),
.arbcp6_cpxdp_grant_arbbf_ca_5(arbcp6_cpxdp_grant_arbbf_ca[5]),
.arbcp6_cpxdp_q0_hold_arbbf_ca_l_5(arbcp6_cpxdp_q0_hold_arbbf_ca_l[5]),
.arbcp6_cpxdp_qsel0_arbbf_ca_5(arbcp6_cpxdp_qsel0_arbbf_ca[5]),
.arbcp6_cpxdp_qsel1_arbbf_ca_l_5(arbcp6_cpxdp_qsel1_arbbf_ca_l[5]),
.arbcp6_cpxdp_shift_arbbf_cx_5(arbcp6_cpxdp_shift_arbbf_cx[5]),
.arbcp7_cpxdp_grant_arbbf_ca_5(arbcp7_cpxdp_grant_arbbf_ca[5]),
.arbcp7_cpxdp_q0_hold_arbbf_ca_l_5(arbcp7_cpxdp_q0_hold_arbbf_ca_l[5]),
.arbcp7_cpxdp_qsel0_arbbf_ca_5(arbcp7_cpxdp_qsel0_arbbf_ca[5]),
.arbcp7_cpxdp_qsel1_arbbf_ca_l_5(arbcp7_cpxdp_qsel1_arbbf_ca_l[5]),
.arbcp7_cpxdp_shift_arbbf_cx_5(arbcp7_cpxdp_shift_arbbf_cx[5]),
.arbcp0_cpxdp_grant_arbbf_ca_2(arbcp0_cpxdp_grant_arbbf_ca[2]),
.arbcp0_cpxdp_q0_hold_arbbf_ca_l_2(arbcp0_cpxdp_q0_hold_arbbf_ca_l[2]),
.arbcp0_cpxdp_qsel0_arbbf_ca_2(arbcp0_cpxdp_qsel0_arbbf_ca[2]),
.arbcp0_cpxdp_qsel1_arbbf_ca_l_2(arbcp0_cpxdp_qsel1_arbbf_ca_l[2]),
.arbcp0_cpxdp_shift_arbbf_cx_2(arbcp0_cpxdp_shift_arbbf_cx[2]),
.arbcp1_cpxdp_grant_arbbf_ca_2(arbcp1_cpxdp_grant_arbbf_ca[2]),
.arbcp1_cpxdp_q0_hold_arbbf_ca_l_2(arbcp1_cpxdp_q0_hold_arbbf_ca_l[2]),
.arbcp1_cpxdp_qsel0_arbbf_ca_2(arbcp1_cpxdp_qsel0_arbbf_ca[2]),
.arbcp1_cpxdp_qsel1_arbbf_ca_l_2(arbcp1_cpxdp_qsel1_arbbf_ca_l[2]),
.arbcp1_cpxdp_shift_arbbf_cx_2(arbcp1_cpxdp_shift_arbbf_cx[2]),
.arbcp2_cpxdp_grant_arbbf_ca_2(arbcp2_cpxdp_grant_arbbf_ca[2]),
.arbcp2_cpxdp_q0_hold_arbbf_ca_l_2(arbcp2_cpxdp_q0_hold_arbbf_ca_l[2]),
.arbcp2_cpxdp_qsel0_arbbf_ca_2(arbcp2_cpxdp_qsel0_arbbf_ca[2]),
.arbcp2_cpxdp_qsel1_arbbf_ca_l_2(arbcp2_cpxdp_qsel1_arbbf_ca_l[2]),
.arbcp2_cpxdp_shift_arbbf_cx_2(arbcp2_cpxdp_shift_arbbf_cx[2]),
.arbcp3_cpxdp_grant_arbbf_ca_2(arbcp3_cpxdp_grant_arbbf_ca[2]),
.arbcp3_cpxdp_q0_hold_arbbf_ca_l_2(arbcp3_cpxdp_q0_hold_arbbf_ca_l[2]),
.arbcp3_cpxdp_qsel0_arbbf_ca_2(arbcp3_cpxdp_qsel0_arbbf_ca[2]),
.arbcp3_cpxdp_qsel1_arbbf_ca_l_2(arbcp3_cpxdp_qsel1_arbbf_ca_l[2]),
.arbcp3_cpxdp_shift_arbbf_cx_2(arbcp3_cpxdp_shift_arbbf_cx[2]),
.arbcp4_cpxdp_grant_arbbf_ca_2(arbcp4_cpxdp_grant_arbbf_ca[2]),
.arbcp4_cpxdp_q0_hold_arbbf_ca_l_2(arbcp4_cpxdp_q0_hold_arbbf_ca_l[2]),
.arbcp4_cpxdp_qsel0_arbbf_ca_2(arbcp4_cpxdp_qsel0_arbbf_ca[2]),
.arbcp4_cpxdp_qsel1_arbbf_ca_l_2(arbcp4_cpxdp_qsel1_arbbf_ca_l[2]),
.arbcp4_cpxdp_shift_arbbf_cx_2(arbcp4_cpxdp_shift_arbbf_cx[2]),
.arbcp5_cpxdp_grant_arbbf_ca_2(arbcp5_cpxdp_grant_arbbf_ca[2]),
.arbcp5_cpxdp_q0_hold_arbbf_ca_l_2(arbcp5_cpxdp_q0_hold_arbbf_ca_l[2]),
.arbcp5_cpxdp_qsel0_arbbf_ca_2(arbcp5_cpxdp_qsel0_arbbf_ca[2]),
.arbcp5_cpxdp_qsel1_arbbf_ca_l_2(arbcp5_cpxdp_qsel1_arbbf_ca_l[2]),
.arbcp5_cpxdp_shift_arbbf_cx_2(arbcp5_cpxdp_shift_arbbf_cx[2]),
.arbcp6_cpxdp_grant_arbbf_ca_2(arbcp6_cpxdp_grant_arbbf_ca[2]),
.arbcp6_cpxdp_q0_hold_arbbf_ca_l_2(arbcp6_cpxdp_q0_hold_arbbf_ca_l[2]),
.arbcp6_cpxdp_qsel0_arbbf_ca_2(arbcp6_cpxdp_qsel0_arbbf_ca[2]),
.arbcp6_cpxdp_qsel1_arbbf_ca_l_2(arbcp6_cpxdp_qsel1_arbbf_ca_l[2]),
.arbcp6_cpxdp_shift_arbbf_cx_2(arbcp6_cpxdp_shift_arbbf_cx[2]),
.arbcp7_cpxdp_grant_arbbf_ca_2(arbcp7_cpxdp_grant_arbbf_ca[2]),
.arbcp7_cpxdp_q0_hold_arbbf_ca_l_2(arbcp7_cpxdp_q0_hold_arbbf_ca_l[2]),
.arbcp7_cpxdp_qsel0_arbbf_ca_2(arbcp7_cpxdp_qsel0_arbbf_ca[2]),
.arbcp7_cpxdp_qsel1_arbbf_ca_l_2(arbcp7_cpxdp_qsel1_arbbf_ca_l[2]),
.arbcp7_cpxdp_shift_arbbf_cx_2(arbcp7_cpxdp_shift_arbbf_cx[2]));
*/
cpx_buf_p3 p3(/*AUTOINST*/
// Outputs
.scache3_cpx_req_bufp3_cq (scache3_cpx_req_bufp3_cq[7:0]),
.scache3_cpx_atom_bufp3_cq(scache3_cpx_atom_bufp3_cq),
.io_cpx_req_bufp3_cq (io_cpx_req_bufp3_cq[7:0]),
.cpx_scache3_grant_bufp3_ca_l(cpx_scache3_grant_bufp3_ca_l[7:0]),
.cpx_spc5_data_rdy_bufp3_cx(cpx_spc5_data_rdy_bufp3_cx),
.cpx_spc6_data_rdy_bufp3_cx(cpx_spc6_data_rdy_bufp3_cx),
.cpx_spc7_data_rdy_bufp3_cx(cpx_spc7_data_rdy_bufp3_cx),
.arbcp0_cpxdp_grant_bufp3_ca_l_5(arbcp0_cpxdp_grant_bufp3_ca_l[5]), // Templated
.arbcp0_cpxdp_q0_hold_bufp3_ca_5(arbcp0_cpxdp_q0_hold_bufp3_ca[5]), // Templated
.arbcp0_cpxdp_qsel0_bufp3_ca_l_5(arbcp0_cpxdp_qsel0_bufp3_ca_l[5]), // Templated
.arbcp0_cpxdp_qsel1_bufp3_ca_5(arbcp0_cpxdp_qsel1_bufp3_ca[5]), // Templated
.arbcp0_cpxdp_shift_bufp3_cx_l_5(arbcp0_cpxdp_shift_bufp3_cx_l[5]), // Templated
.arbcp1_cpxdp_grant_bufp3_ca_l_5(arbcp1_cpxdp_grant_bufp3_ca_l[5]), // Templated
.arbcp1_cpxdp_q0_hold_bufp3_ca_5(arbcp1_cpxdp_q0_hold_bufp3_ca[5]), // Templated
.arbcp1_cpxdp_qsel0_bufp3_ca_l_5(arbcp1_cpxdp_qsel0_bufp3_ca_l[5]), // Templated
.arbcp1_cpxdp_qsel1_bufp3_ca_5(arbcp1_cpxdp_qsel1_bufp3_ca[5]), // Templated
.arbcp1_cpxdp_shift_bufp3_cx_l_5(arbcp1_cpxdp_shift_bufp3_cx_l[5]), // Templated
.arbcp2_cpxdp_grant_bufp3_ca_l_5(arbcp2_cpxdp_grant_bufp3_ca_l[5]), // Templated
.arbcp2_cpxdp_q0_hold_bufp3_ca_5(arbcp2_cpxdp_q0_hold_bufp3_ca[5]), // Templated
.arbcp2_cpxdp_qsel0_bufp3_ca_l_5(arbcp2_cpxdp_qsel0_bufp3_ca_l[5]), // Templated
.arbcp2_cpxdp_qsel1_bufp3_ca_5(arbcp2_cpxdp_qsel1_bufp3_ca[5]), // Templated
.arbcp2_cpxdp_shift_bufp3_cx_l_5(arbcp2_cpxdp_shift_bufp3_cx_l[5]), // Templated
.arbcp3_cpxdp_grant_bufp3_ca_l_5(arbcp3_cpxdp_grant_bufp3_ca_l[5]), // Templated
.arbcp3_cpxdp_q0_hold_bufp3_ca_5(arbcp3_cpxdp_q0_hold_bufp3_ca[5]), // Templated
.arbcp3_cpxdp_qsel0_bufp3_ca_l_5(arbcp3_cpxdp_qsel0_bufp3_ca_l[5]), // Templated
.arbcp3_cpxdp_qsel1_bufp3_ca_5(arbcp3_cpxdp_qsel1_bufp3_ca[5]), // Templated
.arbcp3_cpxdp_shift_bufp3_cx_l_5(arbcp3_cpxdp_shift_bufp3_cx_l[5]), // Templated
.arbcp4_cpxdp_grant_bufp3_ca_l_5(arbcp4_cpxdp_grant_bufp3_ca_l[5]), // Templated
.arbcp4_cpxdp_q0_hold_bufp3_ca_5(arbcp4_cpxdp_q0_hold_bufp3_ca[5]), // Templated
.arbcp4_cpxdp_qsel0_bufp3_ca_l_5(arbcp4_cpxdp_qsel0_bufp3_ca_l[5]), // Templated
.arbcp4_cpxdp_qsel1_bufp3_ca_5(arbcp4_cpxdp_qsel1_bufp3_ca[5]), // Templated
.arbcp4_cpxdp_shift_bufp3_cx_l_5(arbcp4_cpxdp_shift_bufp3_cx_l[5]), // Templated
.arbcp5_cpxdp_grant_bufp3_ca_l_5(arbcp5_cpxdp_grant_bufp3_ca_l[5]), // Templated
.arbcp5_cpxdp_q0_hold_bufp3_ca_5(arbcp5_cpxdp_q0_hold_bufp3_ca[5]), // Templated
.arbcp5_cpxdp_qsel0_bufp3_ca_l_5(arbcp5_cpxdp_qsel0_bufp3_ca_l[5]), // Templated
.arbcp5_cpxdp_qsel1_bufp3_ca_5(arbcp5_cpxdp_qsel1_bufp3_ca[5]), // Templated
.arbcp5_cpxdp_shift_bufp3_cx_l_5(arbcp5_cpxdp_shift_bufp3_cx_l[5]), // Templated
.arbcp6_cpxdp_grant_bufp3_ca_l_5(arbcp6_cpxdp_grant_bufp3_ca_l[5]), // Templated
.arbcp6_cpxdp_q0_hold_bufp3_ca_5(arbcp6_cpxdp_q0_hold_bufp3_ca[5]), // Templated
.arbcp6_cpxdp_qsel0_bufp3_ca_l_5(arbcp6_cpxdp_qsel0_bufp3_ca_l[5]), // Templated
.arbcp6_cpxdp_qsel1_bufp3_ca_5(arbcp6_cpxdp_qsel1_bufp3_ca[5]), // Templated
.arbcp6_cpxdp_shift_bufp3_cx_l_5(arbcp6_cpxdp_shift_bufp3_cx_l[5]), // Templated
.arbcp7_cpxdp_grant_bufp3_ca_l_5(arbcp7_cpxdp_grant_bufp3_ca_l[5]), // Templated
.arbcp7_cpxdp_q0_hold_bufp3_ca_5(arbcp7_cpxdp_q0_hold_bufp3_ca[5]), // Templated
.arbcp7_cpxdp_qsel0_bufp3_ca_l_5(arbcp7_cpxdp_qsel0_bufp3_ca_l[5]), // Templated
.arbcp7_cpxdp_qsel1_bufp3_ca_5(arbcp7_cpxdp_qsel1_bufp3_ca[5]), // Templated
.arbcp7_cpxdp_shift_bufp3_cx_l_5(arbcp7_cpxdp_shift_bufp3_cx_l[5]), // Templated
.arbcp0_cpxdp_grant_bufp3_ca_l_2(arbcp0_cpxdp_grant_bufp3_ca_l[2]), // Templated
.arbcp0_cpxdp_q0_hold_bufp3_ca_2(arbcp0_cpxdp_q0_hold_bufp3_ca[2]), // Templated
.arbcp0_cpxdp_qsel0_bufp3_ca_l_2(arbcp0_cpxdp_qsel0_bufp3_ca_l[2]), // Templated
.arbcp0_cpxdp_qsel1_bufp3_ca_2(arbcp0_cpxdp_qsel1_bufp3_ca[2]), // Templated
.arbcp0_cpxdp_shift_bufp3_cx_l_2(arbcp0_cpxdp_shift_bufp3_cx_l[2]), // Templated
.arbcp1_cpxdp_grant_bufp3_ca_l_2(arbcp1_cpxdp_grant_bufp3_ca_l[2]), // Templated
.arbcp1_cpxdp_q0_hold_bufp3_ca_2(arbcp1_cpxdp_q0_hold_bufp3_ca[2]), // Templated
.arbcp1_cpxdp_qsel0_bufp3_ca_l_2(arbcp1_cpxdp_qsel0_bufp3_ca_l[2]), // Templated
.arbcp1_cpxdp_qsel1_bufp3_ca_2(arbcp1_cpxdp_qsel1_bufp3_ca[2]), // Templated
.arbcp1_cpxdp_shift_bufp3_cx_l_2(arbcp1_cpxdp_shift_bufp3_cx_l[2]), // Templated
.arbcp2_cpxdp_grant_bufp3_ca_l_2(arbcp2_cpxdp_grant_bufp3_ca_l[2]), // Templated
.arbcp2_cpxdp_q0_hold_bufp3_ca_2(arbcp2_cpxdp_q0_hold_bufp3_ca[2]), // Templated
.arbcp2_cpxdp_qsel0_bufp3_ca_l_2(arbcp2_cpxdp_qsel0_bufp3_ca_l[2]), // Templated
.arbcp2_cpxdp_qsel1_bufp3_ca_2(arbcp2_cpxdp_qsel1_bufp3_ca[2]), // Templated
.arbcp2_cpxdp_shift_bufp3_cx_l_2(arbcp2_cpxdp_shift_bufp3_cx_l[2]), // Templated
.arbcp3_cpxdp_grant_bufp3_ca_l_2(arbcp3_cpxdp_grant_bufp3_ca_l[2]), // Templated
.arbcp3_cpxdp_q0_hold_bufp3_ca_2(arbcp3_cpxdp_q0_hold_bufp3_ca[2]), // Templated
.arbcp3_cpxdp_qsel0_bufp3_ca_l_2(arbcp3_cpxdp_qsel0_bufp3_ca_l[2]), // Templated
.arbcp3_cpxdp_qsel1_bufp3_ca_2(arbcp3_cpxdp_qsel1_bufp3_ca[2]), // Templated
.arbcp3_cpxdp_shift_bufp3_cx_l_2(arbcp3_cpxdp_shift_bufp3_cx_l[2]), // Templated
.arbcp4_cpxdp_grant_bufp3_ca_l_2(arbcp4_cpxdp_grant_bufp3_ca_l[2]), // Templated
.arbcp4_cpxdp_q0_hold_bufp3_ca_2(arbcp4_cpxdp_q0_hold_bufp3_ca[2]), // Templated
.arbcp4_cpxdp_qsel0_bufp3_ca_l_2(arbcp4_cpxdp_qsel0_bufp3_ca_l[2]), // Templated
.arbcp4_cpxdp_qsel1_bufp3_ca_2(arbcp4_cpxdp_qsel1_bufp3_ca[2]), // Templated
.arbcp4_cpxdp_shift_bufp3_cx_l_2(arbcp4_cpxdp_shift_bufp3_cx_l[2]), // Templated
.arbcp5_cpxdp_grant_bufp3_ca_l_2(arbcp5_cpxdp_grant_bufp3_ca_l[2]), // Templated
.arbcp5_cpxdp_q0_hold_bufp3_ca_2(arbcp5_cpxdp_q0_hold_bufp3_ca[2]), // Templated
.arbcp5_cpxdp_qsel0_bufp3_ca_l_2(arbcp5_cpxdp_qsel0_bufp3_ca_l[2]), // Templated
.arbcp5_cpxdp_qsel1_bufp3_ca_2(arbcp5_cpxdp_qsel1_bufp3_ca[2]), // Templated
.arbcp5_cpxdp_shift_bufp3_cx_l_2(arbcp5_cpxdp_shift_bufp3_cx_l[2]), // Templated
.arbcp6_cpxdp_grant_bufp3_ca_l_2(arbcp6_cpxdp_grant_bufp3_ca_l[2]), // Templated
.arbcp6_cpxdp_q0_hold_bufp3_ca_2(arbcp6_cpxdp_q0_hold_bufp3_ca[2]), // Templated
.arbcp6_cpxdp_qsel0_bufp3_ca_l_2(arbcp6_cpxdp_qsel0_bufp3_ca_l[2]), // Templated
.arbcp6_cpxdp_qsel1_bufp3_ca_2(arbcp6_cpxdp_qsel1_bufp3_ca[2]), // Templated
.arbcp6_cpxdp_shift_bufp3_cx_l_2(arbcp6_cpxdp_shift_bufp3_cx_l[2]), // Templated
.arbcp7_cpxdp_grant_bufp3_ca_l_2(arbcp7_cpxdp_grant_bufp3_ca_l[2]), // Templated
.arbcp7_cpxdp_q0_hold_bufp3_ca_2(arbcp7_cpxdp_q0_hold_bufp3_ca[2]), // Templated
.arbcp7_cpxdp_qsel0_bufp3_ca_l_2(arbcp7_cpxdp_qsel0_bufp3_ca_l[2]), // Templated
.arbcp7_cpxdp_qsel1_bufp3_ca_2(arbcp7_cpxdp_qsel1_bufp3_ca[2]), // Templated
.arbcp7_cpxdp_shift_bufp3_cx_l_2(arbcp7_cpxdp_shift_bufp3_cx_l[2]), // Templated
// Inputs
.scache3_cpx_req_bufp4_cq (scache3_cpx_req_bufp4_cq[7:0]),
.scache3_cpx_atom_bufp4_cq(scache3_cpx_atom_bufp4_cq),
.io_cpx_req_bufp4_cq (io_cpx_req_bufp4_cq[7:0]),
.cpx_scache3_grant_ca (cpx_scache3_grant_ca[7:0]),
.cpx_spc5_data_rdy_cx (cpx_spc5_data_rdy_cx),
.cpx_spc6_data_rdy_cx (cpx_spc6_data_rdy_cx),
.cpx_spc7_data_rdy_cx (cpx_spc7_data_rdy_cx),
.arbcp0_cpxdp_grant_arbbf_ca_5(arbcp0_cpxdp_grant_arbbf_ca[5]), // Templated
.arbcp0_cpxdp_q0_hold_arbbf_ca_l_5(arbcp0_cpxdp_q0_hold_arbbf_ca_l[5]), // Templated
.arbcp0_cpxdp_qsel0_arbbf_ca_5(arbcp0_cpxdp_qsel0_arbbf_ca[5]), // Templated
.arbcp0_cpxdp_qsel1_arbbf_ca_l_5(arbcp0_cpxdp_qsel1_arbbf_ca_l[5]), // Templated
.arbcp0_cpxdp_shift_arbbf_cx_5(arbcp0_cpxdp_shift_arbbf_cx[5]), // Templated
.arbcp1_cpxdp_grant_arbbf_ca_5(arbcp1_cpxdp_grant_arbbf_ca[5]), // Templated
.arbcp1_cpxdp_q0_hold_arbbf_ca_l_5(arbcp1_cpxdp_q0_hold_arbbf_ca_l[5]), // Templated
.arbcp1_cpxdp_qsel0_arbbf_ca_5(arbcp1_cpxdp_qsel0_arbbf_ca[5]), // Templated
.arbcp1_cpxdp_qsel1_arbbf_ca_l_5(arbcp1_cpxdp_qsel1_arbbf_ca_l[5]), // Templated
.arbcp1_cpxdp_shift_arbbf_cx_5(arbcp1_cpxdp_shift_arbbf_cx[5]), // Templated
.arbcp2_cpxdp_grant_arbbf_ca_5(arbcp2_cpxdp_grant_arbbf_ca[5]), // Templated
.arbcp2_cpxdp_q0_hold_arbbf_ca_l_5(arbcp2_cpxdp_q0_hold_arbbf_ca_l[5]), // Templated
.arbcp2_cpxdp_qsel0_arbbf_ca_5(arbcp2_cpxdp_qsel0_arbbf_ca[5]), // Templated
.arbcp2_cpxdp_qsel1_arbbf_ca_l_5(arbcp2_cpxdp_qsel1_arbbf_ca_l[5]), // Templated
.arbcp2_cpxdp_shift_arbbf_cx_5(arbcp2_cpxdp_shift_arbbf_cx[5]), // Templated
.arbcp3_cpxdp_grant_arbbf_ca_5(arbcp3_cpxdp_grant_arbbf_ca[5]), // Templated
.arbcp3_cpxdp_q0_hold_arbbf_ca_l_5(arbcp3_cpxdp_q0_hold_arbbf_ca_l[5]), // Templated
.arbcp3_cpxdp_qsel0_arbbf_ca_5(arbcp3_cpxdp_qsel0_arbbf_ca[5]), // Templated
.arbcp3_cpxdp_qsel1_arbbf_ca_l_5(arbcp3_cpxdp_qsel1_arbbf_ca_l[5]), // Templated
.arbcp3_cpxdp_shift_arbbf_cx_5(arbcp3_cpxdp_shift_arbbf_cx[5]), // Templated
.arbcp4_cpxdp_grant_arbbf_ca_5(arbcp4_cpxdp_grant_arbbf_ca[5]), // Templated
.arbcp4_cpxdp_q0_hold_arbbf_ca_l_5(arbcp4_cpxdp_q0_hold_arbbf_ca_l[5]), // Templated
.arbcp4_cpxdp_qsel0_arbbf_ca_5(arbcp4_cpxdp_qsel0_arbbf_ca[5]), // Templated
.arbcp4_cpxdp_qsel1_arbbf_ca_l_5(arbcp4_cpxdp_qsel1_arbbf_ca_l[5]), // Templated
.arbcp4_cpxdp_shift_arbbf_cx_5(arbcp4_cpxdp_shift_arbbf_cx[5]), // Templated
.arbcp5_cpxdp_grant_arbbf_ca_5(arbcp5_cpxdp_grant_arbbf_ca[5]), // Templated
.arbcp5_cpxdp_q0_hold_arbbf_ca_l_5(arbcp5_cpxdp_q0_hold_arbbf_ca_l[5]), // Templated
.arbcp5_cpxdp_qsel0_arbbf_ca_5(arbcp5_cpxdp_qsel0_arbbf_ca[5]), // Templated
.arbcp5_cpxdp_qsel1_arbbf_ca_l_5(arbcp5_cpxdp_qsel1_arbbf_ca_l[5]), // Templated
.arbcp5_cpxdp_shift_arbbf_cx_5(arbcp5_cpxdp_shift_arbbf_cx[5]), // Templated
.arbcp6_cpxdp_grant_arbbf_ca_5(arbcp6_cpxdp_grant_arbbf_ca[5]), // Templated
.arbcp6_cpxdp_q0_hold_arbbf_ca_l_5(arbcp6_cpxdp_q0_hold_arbbf_ca_l[5]), // Templated
.arbcp6_cpxdp_qsel0_arbbf_ca_5(arbcp6_cpxdp_qsel0_arbbf_ca[5]), // Templated
.arbcp6_cpxdp_qsel1_arbbf_ca_l_5(arbcp6_cpxdp_qsel1_arbbf_ca_l[5]), // Templated
.arbcp6_cpxdp_shift_arbbf_cx_5(arbcp6_cpxdp_shift_arbbf_cx[5]), // Templated
.arbcp7_cpxdp_grant_arbbf_ca_5(arbcp7_cpxdp_grant_arbbf_ca[5]), // Templated
.arbcp7_cpxdp_q0_hold_arbbf_ca_l_5(arbcp7_cpxdp_q0_hold_arbbf_ca_l[5]), // Templated
.arbcp7_cpxdp_qsel0_arbbf_ca_5(arbcp7_cpxdp_qsel0_arbbf_ca[5]), // Templated
.arbcp7_cpxdp_qsel1_arbbf_ca_l_5(arbcp7_cpxdp_qsel1_arbbf_ca_l[5]), // Templated
.arbcp7_cpxdp_shift_arbbf_cx_5(arbcp7_cpxdp_shift_arbbf_cx[5]), // Templated
.arbcp0_cpxdp_grant_arbbf_ca_2(arbcp0_cpxdp_grant_arbbf_ca[2]), // Templated
.arbcp0_cpxdp_q0_hold_arbbf_ca_l_2(arbcp0_cpxdp_q0_hold_arbbf_ca_l[2]), // Templated
.arbcp0_cpxdp_qsel0_arbbf_ca_2(arbcp0_cpxdp_qsel0_arbbf_ca[2]), // Templated
.arbcp0_cpxdp_qsel1_arbbf_ca_l_2(arbcp0_cpxdp_qsel1_arbbf_ca_l[2]), // Templated
.arbcp0_cpxdp_shift_arbbf_cx_2(arbcp0_cpxdp_shift_arbbf_cx[2]), // Templated
.arbcp1_cpxdp_grant_arbbf_ca_2(arbcp1_cpxdp_grant_arbbf_ca[2]), // Templated
.arbcp1_cpxdp_q0_hold_arbbf_ca_l_2(arbcp1_cpxdp_q0_hold_arbbf_ca_l[2]), // Templated
.arbcp1_cpxdp_qsel0_arbbf_ca_2(arbcp1_cpxdp_qsel0_arbbf_ca[2]), // Templated
.arbcp1_cpxdp_qsel1_arbbf_ca_l_2(arbcp1_cpxdp_qsel1_arbbf_ca_l[2]), // Templated
.arbcp1_cpxdp_shift_arbbf_cx_2(arbcp1_cpxdp_shift_arbbf_cx[2]), // Templated
.arbcp2_cpxdp_grant_arbbf_ca_2(arbcp2_cpxdp_grant_arbbf_ca[2]), // Templated
.arbcp2_cpxdp_q0_hold_arbbf_ca_l_2(arbcp2_cpxdp_q0_hold_arbbf_ca_l[2]), // Templated
.arbcp2_cpxdp_qsel0_arbbf_ca_2(arbcp2_cpxdp_qsel0_arbbf_ca[2]), // Templated
.arbcp2_cpxdp_qsel1_arbbf_ca_l_2(arbcp2_cpxdp_qsel1_arbbf_ca_l[2]), // Templated
.arbcp2_cpxdp_shift_arbbf_cx_2(arbcp2_cpxdp_shift_arbbf_cx[2]), // Templated
.arbcp3_cpxdp_grant_arbbf_ca_2(arbcp3_cpxdp_grant_arbbf_ca[2]), // Templated
.arbcp3_cpxdp_q0_hold_arbbf_ca_l_2(arbcp3_cpxdp_q0_hold_arbbf_ca_l[2]), // Templated
.arbcp3_cpxdp_qsel0_arbbf_ca_2(arbcp3_cpxdp_qsel0_arbbf_ca[2]), // Templated
.arbcp3_cpxdp_qsel1_arbbf_ca_l_2(arbcp3_cpxdp_qsel1_arbbf_ca_l[2]), // Templated
.arbcp3_cpxdp_shift_arbbf_cx_2(arbcp3_cpxdp_shift_arbbf_cx[2]), // Templated
.arbcp4_cpxdp_grant_arbbf_ca_2(arbcp4_cpxdp_grant_arbbf_ca[2]), // Templated
.arbcp4_cpxdp_q0_hold_arbbf_ca_l_2(arbcp4_cpxdp_q0_hold_arbbf_ca_l[2]), // Templated
.arbcp4_cpxdp_qsel0_arbbf_ca_2(arbcp4_cpxdp_qsel0_arbbf_ca[2]), // Templated
.arbcp4_cpxdp_qsel1_arbbf_ca_l_2(arbcp4_cpxdp_qsel1_arbbf_ca_l[2]), // Templated
.arbcp4_cpxdp_shift_arbbf_cx_2(arbcp4_cpxdp_shift_arbbf_cx[2]), // Templated
.arbcp5_cpxdp_grant_arbbf_ca_2(arbcp5_cpxdp_grant_arbbf_ca[2]), // Templated
.arbcp5_cpxdp_q0_hold_arbbf_ca_l_2(arbcp5_cpxdp_q0_hold_arbbf_ca_l[2]), // Templated
.arbcp5_cpxdp_qsel0_arbbf_ca_2(arbcp5_cpxdp_qsel0_arbbf_ca[2]), // Templated
.arbcp5_cpxdp_qsel1_arbbf_ca_l_2(arbcp5_cpxdp_qsel1_arbbf_ca_l[2]), // Templated
.arbcp5_cpxdp_shift_arbbf_cx_2(arbcp5_cpxdp_shift_arbbf_cx[2]), // Templated
.arbcp6_cpxdp_grant_arbbf_ca_2(arbcp6_cpxdp_grant_arbbf_ca[2]), // Templated
.arbcp6_cpxdp_q0_hold_arbbf_ca_l_2(arbcp6_cpxdp_q0_hold_arbbf_ca_l[2]), // Templated
.arbcp6_cpxdp_qsel0_arbbf_ca_2(arbcp6_cpxdp_qsel0_arbbf_ca[2]), // Templated
.arbcp6_cpxdp_qsel1_arbbf_ca_l_2(arbcp6_cpxdp_qsel1_arbbf_ca_l[2]), // Templated
.arbcp6_cpxdp_shift_arbbf_cx_2(arbcp6_cpxdp_shift_arbbf_cx[2]), // Templated
.arbcp7_cpxdp_grant_arbbf_ca_2(arbcp7_cpxdp_grant_arbbf_ca[2]), // Templated
.arbcp7_cpxdp_q0_hold_arbbf_ca_l_2(arbcp7_cpxdp_q0_hold_arbbf_ca_l[2]), // Templated
.arbcp7_cpxdp_qsel0_arbbf_ca_2(arbcp7_cpxdp_qsel0_arbbf_ca[2]), // Templated
.arbcp7_cpxdp_qsel1_arbbf_ca_l_2(arbcp7_cpxdp_qsel1_arbbf_ca_l[2]), // Templated
.arbcp7_cpxdp_shift_arbbf_cx_2(arbcp7_cpxdp_shift_arbbf_cx[2])); // Templated
/* cpx_buf_pdr_even AUTO_TEMPLATE(
// Outputs
.arbcp0_cpxdp_grant_ca(arbcp0_cpxdp_grant_ca[4]),
.arbcp0_cpxdp_q0_hold_ca_l(arbcp0_cpxdp_q0_hold_ca_l[4]),
.arbcp0_cpxdp_qsel0_ca(arbcp0_cpxdp_qsel0_ca[4]),
.arbcp0_cpxdp_qsel1_ca_l(arbcp0_cpxdp_qsel1_ca_l[4]),
.arbcp0_cpxdp_shift_cx(arbcp0_cpxdp_shift_cx[4]),
.arbcp2_cpxdp_grant_ca(arbcp2_cpxdp_grant_ca[4]),
.arbcp2_cpxdp_q0_hold_ca_l(arbcp2_cpxdp_q0_hold_ca_l[4]),
.arbcp2_cpxdp_qsel0_ca(arbcp2_cpxdp_qsel0_ca[4]),
.arbcp2_cpxdp_qsel1_ca_l(arbcp2_cpxdp_qsel1_ca_l[4]),
.arbcp2_cpxdp_shift_cx(arbcp2_cpxdp_shift_cx[4]),
.arbcp4_cpxdp_grant_ca(arbcp4_cpxdp_grant_ca[4]),
.arbcp4_cpxdp_q0_hold_ca_l(arbcp4_cpxdp_q0_hold_ca_l[4]),
.arbcp4_cpxdp_qsel0_ca(arbcp4_cpxdp_qsel0_ca[4]),
.arbcp4_cpxdp_qsel1_ca_l(arbcp4_cpxdp_qsel1_ca_l[4]),
.arbcp4_cpxdp_shift_cx(arbcp4_cpxdp_shift_cx[4]),
.arbcp6_cpxdp_grant_ca(arbcp6_cpxdp_grant_ca[4]),
.arbcp6_cpxdp_q0_hold_ca_l(arbcp6_cpxdp_q0_hold_ca_l[4]),
.arbcp6_cpxdp_qsel0_ca(arbcp6_cpxdp_qsel0_ca[4]),
.arbcp6_cpxdp_qsel1_ca_l(arbcp6_cpxdp_qsel1_ca_l[4]),
.arbcp6_cpxdp_shift_cx(arbcp6_cpxdp_shift_cx[4]),
// Inputs
.arbcp0_cpxdp_grant_bufp3_ca(arbcp0_cpxdp_grant_arbbf_ca[4]),
.arbcp0_cpxdp_q0_hold_bufp3_ca_l(arbcp0_cpxdp_q0_hold_arbbf_ca_l[4]),
.arbcp0_cpxdp_qsel0_bufp3_ca(arbcp0_cpxdp_qsel0_arbbf_ca[4]),
.arbcp0_cpxdp_qsel1_bufp3_ca_l(arbcp0_cpxdp_qsel1_arbbf_ca_l[4]),
.arbcp0_cpxdp_shift_bufp3_cx(arbcp0_cpxdp_shift_arbbf_cx[4]),
.arbcp2_cpxdp_grant_bufp3_ca(arbcp2_cpxdp_grant_arbbf_ca[4]),
.arbcp2_cpxdp_q0_hold_bufp3_ca_l(arbcp2_cpxdp_q0_hold_arbbf_ca_l[4]),
.arbcp2_cpxdp_qsel0_bufp3_ca(arbcp2_cpxdp_qsel0_arbbf_ca[4]),
.arbcp2_cpxdp_qsel1_bufp3_ca_l(arbcp2_cpxdp_qsel1_arbbf_ca_l[4]),
.arbcp2_cpxdp_shift_bufp3_cx(arbcp2_cpxdp_shift_arbbf_cx[4]),
.arbcp4_cpxdp_grant_bufp3_ca(arbcp4_cpxdp_grant_arbbf_ca[4]),
.arbcp4_cpxdp_q0_hold_bufp3_ca_l(arbcp4_cpxdp_q0_hold_arbbf_ca_l[4]),
.arbcp4_cpxdp_qsel0_bufp3_ca(arbcp4_cpxdp_qsel0_arbbf_ca[4]),
.arbcp4_cpxdp_qsel1_bufp3_ca_l(arbcp4_cpxdp_qsel1_arbbf_ca_l[4]),
.arbcp4_cpxdp_shift_bufp3_cx(arbcp4_cpxdp_shift_arbbf_cx[4]),
.arbcp6_cpxdp_grant_bufp3_ca(arbcp6_cpxdp_grant_arbbf_ca[4]),
.arbcp6_cpxdp_q0_hold_bufp3_ca_l(arbcp6_cpxdp_q0_hold_arbbf_ca_l[4]),
.arbcp6_cpxdp_qsel0_bufp3_ca(arbcp6_cpxdp_qsel0_arbbf_ca[4]),
.arbcp6_cpxdp_qsel1_bufp3_ca_l(arbcp6_cpxdp_qsel1_arbbf_ca_l[4]),
.arbcp6_cpxdp_shift_bufp3_cx(arbcp6_cpxdp_shift_arbbf_cx[4]));
*/
cpx_buf_pdr_even pdr_even(/*AUTOINST*/
// Outputs
.arbcp0_cpxdp_grant_ca(arbcp0_cpxdp_grant_ca[4]), // Templated
.arbcp0_cpxdp_q0_hold_ca_l(arbcp0_cpxdp_q0_hold_ca_l[4]), // Templated
.arbcp0_cpxdp_qsel0_ca(arbcp0_cpxdp_qsel0_ca[4]), // Templated
.arbcp0_cpxdp_qsel1_ca_l(arbcp0_cpxdp_qsel1_ca_l[4]), // Templated
.arbcp0_cpxdp_shift_cx(arbcp0_cpxdp_shift_cx[4]), // Templated
.arbcp2_cpxdp_grant_ca(arbcp2_cpxdp_grant_ca[4]), // Templated
.arbcp2_cpxdp_q0_hold_ca_l(arbcp2_cpxdp_q0_hold_ca_l[4]), // Templated
.arbcp2_cpxdp_qsel0_ca(arbcp2_cpxdp_qsel0_ca[4]), // Templated
.arbcp2_cpxdp_qsel1_ca_l(arbcp2_cpxdp_qsel1_ca_l[4]), // Templated
.arbcp2_cpxdp_shift_cx(arbcp2_cpxdp_shift_cx[4]), // Templated
.arbcp4_cpxdp_grant_ca(arbcp4_cpxdp_grant_ca[4]), // Templated
.arbcp4_cpxdp_q0_hold_ca_l(arbcp4_cpxdp_q0_hold_ca_l[4]), // Templated
.arbcp4_cpxdp_qsel0_ca(arbcp4_cpxdp_qsel0_ca[4]), // Templated
.arbcp4_cpxdp_qsel1_ca_l(arbcp4_cpxdp_qsel1_ca_l[4]), // Templated
.arbcp4_cpxdp_shift_cx(arbcp4_cpxdp_shift_cx[4]), // Templated
.arbcp6_cpxdp_grant_ca(arbcp6_cpxdp_grant_ca[4]), // Templated
.arbcp6_cpxdp_q0_hold_ca_l(arbcp6_cpxdp_q0_hold_ca_l[4]), // Templated
.arbcp6_cpxdp_qsel0_ca(arbcp6_cpxdp_qsel0_ca[4]), // Templated
.arbcp6_cpxdp_qsel1_ca_l(arbcp6_cpxdp_qsel1_ca_l[4]), // Templated
.arbcp6_cpxdp_shift_cx(arbcp6_cpxdp_shift_cx[4]), // Templated
// Inputs
.arbcp0_cpxdp_grant_bufp3_ca(arbcp0_cpxdp_grant_arbbf_ca[4]), // Templated
.arbcp0_cpxdp_q0_hold_bufp3_ca_l(arbcp0_cpxdp_q0_hold_arbbf_ca_l[4]), // Templated
.arbcp0_cpxdp_qsel0_bufp3_ca(arbcp0_cpxdp_qsel0_arbbf_ca[4]), // Templated
.arbcp0_cpxdp_qsel1_bufp3_ca_l(arbcp0_cpxdp_qsel1_arbbf_ca_l[4]), // Templated
.arbcp0_cpxdp_shift_bufp3_cx(arbcp0_cpxdp_shift_arbbf_cx[4]), // Templated
.arbcp2_cpxdp_grant_bufp3_ca(arbcp2_cpxdp_grant_arbbf_ca[4]), // Templated
.arbcp2_cpxdp_q0_hold_bufp3_ca_l(arbcp2_cpxdp_q0_hold_arbbf_ca_l[4]), // Templated
.arbcp2_cpxdp_qsel0_bufp3_ca(arbcp2_cpxdp_qsel0_arbbf_ca[4]), // Templated
.arbcp2_cpxdp_qsel1_bufp3_ca_l(arbcp2_cpxdp_qsel1_arbbf_ca_l[4]), // Templated
.arbcp2_cpxdp_shift_bufp3_cx(arbcp2_cpxdp_shift_arbbf_cx[4]), // Templated
.arbcp4_cpxdp_grant_bufp3_ca(arbcp4_cpxdp_grant_arbbf_ca[4]), // Templated
.arbcp4_cpxdp_q0_hold_bufp3_ca_l(arbcp4_cpxdp_q0_hold_arbbf_ca_l[4]), // Templated
.arbcp4_cpxdp_qsel0_bufp3_ca(arbcp4_cpxdp_qsel0_arbbf_ca[4]), // Templated
.arbcp4_cpxdp_qsel1_bufp3_ca_l(arbcp4_cpxdp_qsel1_arbbf_ca_l[4]), // Templated
.arbcp4_cpxdp_shift_bufp3_cx(arbcp4_cpxdp_shift_arbbf_cx[4]), // Templated
.arbcp6_cpxdp_grant_bufp3_ca(arbcp6_cpxdp_grant_arbbf_ca[4]), // Templated
.arbcp6_cpxdp_q0_hold_bufp3_ca_l(arbcp6_cpxdp_q0_hold_arbbf_ca_l[4]), // Templated
.arbcp6_cpxdp_qsel0_bufp3_ca(arbcp6_cpxdp_qsel0_arbbf_ca[4]), // Templated
.arbcp6_cpxdp_qsel1_bufp3_ca_l(arbcp6_cpxdp_qsel1_arbbf_ca_l[4]), // Templated
.arbcp6_cpxdp_shift_bufp3_cx(arbcp6_cpxdp_shift_arbbf_cx[4])); // Templated
/* cpx_buf_pdr_even AUTO_TEMPLATE(
// Outputs
.arbcp0_cpxdp_grant_ca(arbcp1_cpxdp_grant_ca[4]),
.arbcp0_cpxdp_q0_hold_ca_l(arbcp1_cpxdp_q0_hold_ca_l[4]),
.arbcp0_cpxdp_qsel0_ca(arbcp1_cpxdp_qsel0_ca[4]),
.arbcp0_cpxdp_qsel1_ca_l(arbcp1_cpxdp_qsel1_ca_l[4]),
.arbcp0_cpxdp_shift_cx(arbcp1_cpxdp_shift_cx[4]),
.arbcp2_cpxdp_grant_ca(arbcp3_cpxdp_grant_ca[4]),
.arbcp2_cpxdp_q0_hold_ca_l(arbcp3_cpxdp_q0_hold_ca_l[4]),
.arbcp2_cpxdp_qsel0_ca(arbcp3_cpxdp_qsel0_ca[4]),
.arbcp2_cpxdp_qsel1_ca_l(arbcp3_cpxdp_qsel1_ca_l[4]),
.arbcp2_cpxdp_shift_cx(arbcp3_cpxdp_shift_cx[4]),
.arbcp4_cpxdp_grant_ca(arbcp5_cpxdp_grant_ca[4]),
.arbcp4_cpxdp_q0_hold_ca_l(arbcp5_cpxdp_q0_hold_ca_l[4]),
.arbcp4_cpxdp_qsel0_ca(arbcp5_cpxdp_qsel0_ca[4]),
.arbcp4_cpxdp_qsel1_ca_l(arbcp5_cpxdp_qsel1_ca_l[4]),
.arbcp4_cpxdp_shift_cx(arbcp5_cpxdp_shift_cx[4]),
.arbcp6_cpxdp_grant_ca(arbcp7_cpxdp_grant_ca[4]),
.arbcp6_cpxdp_q0_hold_ca_l(arbcp7_cpxdp_q0_hold_ca_l[4]),
.arbcp6_cpxdp_qsel0_ca(arbcp7_cpxdp_qsel0_ca[4]),
.arbcp6_cpxdp_qsel1_ca_l(arbcp7_cpxdp_qsel1_ca_l[4]),
.arbcp6_cpxdp_shift_cx(arbcp7_cpxdp_shift_cx[4]),
// Inputs
.arbcp0_cpxdp_grant_bufp3_ca(arbcp1_cpxdp_grant_arbbf_ca[4]),
.arbcp0_cpxdp_q0_hold_bufp3_ca_l(arbcp1_cpxdp_q0_hold_arbbf_ca_l[4]),
.arbcp0_cpxdp_qsel0_bufp3_ca(arbcp1_cpxdp_qsel0_arbbf_ca[4]),
.arbcp0_cpxdp_qsel1_bufp3_ca_l(arbcp1_cpxdp_qsel1_arbbf_ca_l[4]),
.arbcp0_cpxdp_shift_bufp3_cx(arbcp1_cpxdp_shift_arbbf_cx[4]),
.arbcp2_cpxdp_grant_bufp3_ca(arbcp3_cpxdp_grant_arbbf_ca[4]),
.arbcp2_cpxdp_q0_hold_bufp3_ca_l(arbcp3_cpxdp_q0_hold_arbbf_ca_l[4]),
.arbcp2_cpxdp_qsel0_bufp3_ca(arbcp3_cpxdp_qsel0_arbbf_ca[4]),
.arbcp2_cpxdp_qsel1_bufp3_ca_l(arbcp3_cpxdp_qsel1_arbbf_ca_l[4]),
.arbcp2_cpxdp_shift_bufp3_cx(arbcp3_cpxdp_shift_arbbf_cx[4]),
.arbcp4_cpxdp_grant_bufp3_ca(arbcp5_cpxdp_grant_arbbf_ca[4]),
.arbcp4_cpxdp_q0_hold_bufp3_ca_l(arbcp5_cpxdp_q0_hold_arbbf_ca_l[4]),
.arbcp4_cpxdp_qsel0_bufp3_ca(arbcp5_cpxdp_qsel0_arbbf_ca[4]),
.arbcp4_cpxdp_qsel1_bufp3_ca_l(arbcp5_cpxdp_qsel1_arbbf_ca_l[4]),
.arbcp4_cpxdp_shift_bufp3_cx(arbcp5_cpxdp_shift_arbbf_cx[4]),
.arbcp6_cpxdp_grant_bufp3_ca(arbcp7_cpxdp_grant_arbbf_ca[4]),
.arbcp6_cpxdp_q0_hold_bufp3_ca_l(arbcp7_cpxdp_q0_hold_arbbf_ca_l[4]),
.arbcp6_cpxdp_qsel0_bufp3_ca(arbcp7_cpxdp_qsel0_arbbf_ca[4]),
.arbcp6_cpxdp_qsel1_bufp3_ca_l(arbcp7_cpxdp_qsel1_arbbf_ca_l[4]),
.arbcp6_cpxdp_shift_bufp3_cx(arbcp7_cpxdp_shift_arbbf_cx[4]));
*/
cpx_buf_pdr_even pdr_odd(/*AUTOINST*/
// Outputs
.arbcp0_cpxdp_grant_ca(arbcp1_cpxdp_grant_ca[4]), // Templated
.arbcp0_cpxdp_q0_hold_ca_l(arbcp1_cpxdp_q0_hold_ca_l[4]), // Templated
.arbcp0_cpxdp_qsel0_ca(arbcp1_cpxdp_qsel0_ca[4]), // Templated
.arbcp0_cpxdp_qsel1_ca_l(arbcp1_cpxdp_qsel1_ca_l[4]), // Templated
.arbcp0_cpxdp_shift_cx(arbcp1_cpxdp_shift_cx[4]), // Templated
.arbcp2_cpxdp_grant_ca(arbcp3_cpxdp_grant_ca[4]), // Templated
.arbcp2_cpxdp_q0_hold_ca_l(arbcp3_cpxdp_q0_hold_ca_l[4]), // Templated
.arbcp2_cpxdp_qsel0_ca(arbcp3_cpxdp_qsel0_ca[4]), // Templated
.arbcp2_cpxdp_qsel1_ca_l(arbcp3_cpxdp_qsel1_ca_l[4]), // Templated
.arbcp2_cpxdp_shift_cx(arbcp3_cpxdp_shift_cx[4]), // Templated
.arbcp4_cpxdp_grant_ca(arbcp5_cpxdp_grant_ca[4]), // Templated
.arbcp4_cpxdp_q0_hold_ca_l(arbcp5_cpxdp_q0_hold_ca_l[4]), // Templated
.arbcp4_cpxdp_qsel0_ca(arbcp5_cpxdp_qsel0_ca[4]), // Templated
.arbcp4_cpxdp_qsel1_ca_l(arbcp5_cpxdp_qsel1_ca_l[4]), // Templated
.arbcp4_cpxdp_shift_cx(arbcp5_cpxdp_shift_cx[4]), // Templated
.arbcp6_cpxdp_grant_ca(arbcp7_cpxdp_grant_ca[4]), // Templated
.arbcp6_cpxdp_q0_hold_ca_l(arbcp7_cpxdp_q0_hold_ca_l[4]), // Templated
.arbcp6_cpxdp_qsel0_ca(arbcp7_cpxdp_qsel0_ca[4]), // Templated
.arbcp6_cpxdp_qsel1_ca_l(arbcp7_cpxdp_qsel1_ca_l[4]), // Templated
.arbcp6_cpxdp_shift_cx(arbcp7_cpxdp_shift_cx[4]), // Templated
// Inputs
.arbcp0_cpxdp_grant_bufp3_ca(arbcp1_cpxdp_grant_arbbf_ca[4]), // Templated
.arbcp0_cpxdp_q0_hold_bufp3_ca_l(arbcp1_cpxdp_q0_hold_arbbf_ca_l[4]), // Templated
.arbcp0_cpxdp_qsel0_bufp3_ca(arbcp1_cpxdp_qsel0_arbbf_ca[4]), // Templated
.arbcp0_cpxdp_qsel1_bufp3_ca_l(arbcp1_cpxdp_qsel1_arbbf_ca_l[4]), // Templated
.arbcp0_cpxdp_shift_bufp3_cx(arbcp1_cpxdp_shift_arbbf_cx[4]), // Templated
.arbcp2_cpxdp_grant_bufp3_ca(arbcp3_cpxdp_grant_arbbf_ca[4]), // Templated
.arbcp2_cpxdp_q0_hold_bufp3_ca_l(arbcp3_cpxdp_q0_hold_arbbf_ca_l[4]), // Templated
.arbcp2_cpxdp_qsel0_bufp3_ca(arbcp3_cpxdp_qsel0_arbbf_ca[4]), // Templated
.arbcp2_cpxdp_qsel1_bufp3_ca_l(arbcp3_cpxdp_qsel1_arbbf_ca_l[4]), // Templated
.arbcp2_cpxdp_shift_bufp3_cx(arbcp3_cpxdp_shift_arbbf_cx[4]), // Templated
.arbcp4_cpxdp_grant_bufp3_ca(arbcp5_cpxdp_grant_arbbf_ca[4]), // Templated
.arbcp4_cpxdp_q0_hold_bufp3_ca_l(arbcp5_cpxdp_q0_hold_arbbf_ca_l[4]), // Templated
.arbcp4_cpxdp_qsel0_bufp3_ca(arbcp5_cpxdp_qsel0_arbbf_ca[4]), // Templated
.arbcp4_cpxdp_qsel1_bufp3_ca_l(arbcp5_cpxdp_qsel1_arbbf_ca_l[4]), // Templated
.arbcp4_cpxdp_shift_bufp3_cx(arbcp5_cpxdp_shift_arbbf_cx[4]), // Templated
.arbcp6_cpxdp_grant_bufp3_ca(arbcp7_cpxdp_grant_arbbf_ca[4]), // Templated
.arbcp6_cpxdp_q0_hold_bufp3_ca_l(arbcp7_cpxdp_q0_hold_arbbf_ca_l[4]), // Templated
.arbcp6_cpxdp_qsel0_bufp3_ca(arbcp7_cpxdp_qsel0_arbbf_ca[4]), // Templated
.arbcp6_cpxdp_qsel1_bufp3_ca_l(arbcp7_cpxdp_qsel1_arbbf_ca_l[4]), // Templated
.arbcp6_cpxdp_shift_bufp3_cx(arbcp7_cpxdp_shift_arbbf_cx[4])); // Templated
cpx_buf_p4 p4(/*AUTOINST*/
// Outputs
.scache3_cpx_req_bufp4_cq(scache3_cpx_req_bufp4_cq[7:0]),
.scache3_cpx_atom_bufp4_cq(scache3_cpx_atom_bufp4_cq),
.io_cpx_req_bufp4_cq (io_cpx_req_bufp4_cq[7:0]),
.cpx_scache3_grant_bufp4_ca(cpx_scache3_grant_bufp4_ca[7:0]),
.cpx_spc7_data_rdy_bufp4_cx(cpx_spc7_data_rdy_bufp4_cx),
// Inputs
.scache3_cpx_req_bufpt_cq_l(scache3_cpx_req_bufpt_cq_l[7:0]),
.scache3_cpx_atom_bufpt_cq_l(scache3_cpx_atom_bufpt_cq_l),
.io_cpx_req_bufpt_cq_l (io_cpx_req_bufpt_cq_l[7:0]),
.cpx_scache3_grant_bufp3_ca_l(cpx_scache3_grant_bufp3_ca_l[7:0]),
.cpx_spc7_data_rdy_bufp3_cx(cpx_spc7_data_rdy_bufp3_cx));
/* cpx_buf_p4_even AUTO_TEMPLATE(
// Outputs
.arbcp0_cpxdp_grant_ca (arbcp0_cpxdp_grant_ca[3]),
.arbcp0_cpxdp_q0_hold_ca_l(arbcp0_cpxdp_q0_hold_ca_l[3]),
.arbcp0_cpxdp_qsel0_ca (arbcp0_cpxdp_qsel0_ca[3]),
.arbcp0_cpxdp_qsel1_ca_l(arbcp0_cpxdp_qsel1_ca_l[3]),
.arbcp0_cpxdp_shift_cx (arbcp0_cpxdp_shift_cx[3]),
.arbcp2_cpxdp_grant_ca (arbcp2_cpxdp_grant_ca[3]),
.arbcp2_cpxdp_q0_hold_ca_l(arbcp2_cpxdp_q0_hold_ca_l[3]),
.arbcp2_cpxdp_qsel0_ca (arbcp2_cpxdp_qsel0_ca[3]),
.arbcp2_cpxdp_qsel1_ca_l(arbcp2_cpxdp_qsel1_ca_l[3]),
.arbcp2_cpxdp_shift_cx (arbcp2_cpxdp_shift_cx[3]),
.arbcp4_cpxdp_grant_ca (arbcp4_cpxdp_grant_ca[3]),
.arbcp4_cpxdp_q0_hold_ca_l(arbcp4_cpxdp_q0_hold_ca_l[3]),
.arbcp4_cpxdp_qsel0_ca (arbcp4_cpxdp_qsel0_ca[3]),
.arbcp4_cpxdp_qsel1_ca_l(arbcp4_cpxdp_qsel1_ca_l[3]),
.arbcp4_cpxdp_shift_cx (arbcp4_cpxdp_shift_cx[3]),
.arbcp6_cpxdp_grant_ca (arbcp6_cpxdp_grant_ca[3]),
.arbcp6_cpxdp_q0_hold_ca_l(arbcp6_cpxdp_q0_hold_ca_l[3]),
.arbcp6_cpxdp_qsel0_ca (arbcp6_cpxdp_qsel0_ca[3]),
.arbcp6_cpxdp_qsel1_ca_l(arbcp6_cpxdp_qsel1_ca_l[3]),
.arbcp6_cpxdp_shift_cx (arbcp6_cpxdp_shift_cx[3]),
// Inputs
.arbcp0_cpxdp_grant_bufp3_ca_l(arbcp0_cpxdp_grant_bufp1_ca_l[3]),
.arbcp0_cpxdp_q0_hold_bufp3_ca(arbcp0_cpxdp_q0_hold_bufp1_ca[3]),
.arbcp0_cpxdp_qsel0_bufp3_ca_l(arbcp0_cpxdp_qsel0_bufp1_ca_l[3]),
.arbcp0_cpxdp_qsel1_bufp3_ca(arbcp0_cpxdp_qsel1_bufp1_ca[3]),
.arbcp0_cpxdp_shift_bufp3_cx_l(arbcp0_cpxdp_shift_bufp1_cx_l[3]),
.arbcp2_cpxdp_grant_bufp3_ca_l(arbcp2_cpxdp_grant_bufp1_ca_l[3]),
.arbcp2_cpxdp_q0_hold_bufp3_ca(arbcp2_cpxdp_q0_hold_bufp1_ca[3]),
.arbcp2_cpxdp_qsel0_bufp3_ca_l(arbcp2_cpxdp_qsel0_bufp1_ca_l[3]),
.arbcp2_cpxdp_qsel1_bufp3_ca(arbcp2_cpxdp_qsel1_bufp1_ca[3]),
.arbcp2_cpxdp_shift_bufp3_cx_l(arbcp2_cpxdp_shift_bufp1_cx_l[3]),
.arbcp4_cpxdp_grant_bufp3_ca_l(arbcp4_cpxdp_grant_bufp1_ca_l[3]),
.arbcp4_cpxdp_q0_hold_bufp3_ca(arbcp4_cpxdp_q0_hold_bufp1_ca[3]),
.arbcp4_cpxdp_qsel0_bufp3_ca_l(arbcp4_cpxdp_qsel0_bufp1_ca_l[3]),
.arbcp4_cpxdp_qsel1_bufp3_ca(arbcp4_cpxdp_qsel1_bufp1_ca[3]),
.arbcp4_cpxdp_shift_bufp3_cx_l(arbcp4_cpxdp_shift_bufp1_cx_l[3]),
.arbcp6_cpxdp_grant_bufp3_ca_l(arbcp6_cpxdp_grant_bufp1_ca_l[3]),
.arbcp6_cpxdp_q0_hold_bufp3_ca(arbcp6_cpxdp_q0_hold_bufp1_ca[3]),
.arbcp6_cpxdp_qsel0_bufp3_ca_l(arbcp6_cpxdp_qsel0_bufp1_ca_l[3]),
.arbcp6_cpxdp_qsel1_bufp3_ca(arbcp6_cpxdp_qsel1_bufp1_ca[3]),
.arbcp6_cpxdp_shift_bufp3_cx_l(arbcp6_cpxdp_shift_bufp1_cx_l[3]));
*/
cpx_buf_p4_even p4_even(/*AUTOINST*/
// Outputs
.arbcp0_cpxdp_grant_ca(arbcp0_cpxdp_grant_ca[3]), // Templated
.arbcp0_cpxdp_q0_hold_ca_l(arbcp0_cpxdp_q0_hold_ca_l[3]), // Templated
.arbcp0_cpxdp_qsel0_ca(arbcp0_cpxdp_qsel0_ca[3]), // Templated
.arbcp0_cpxdp_qsel1_ca_l(arbcp0_cpxdp_qsel1_ca_l[3]), // Templated
.arbcp0_cpxdp_shift_cx(arbcp0_cpxdp_shift_cx[3]), // Templated
.arbcp2_cpxdp_grant_ca(arbcp2_cpxdp_grant_ca[3]), // Templated
.arbcp2_cpxdp_q0_hold_ca_l(arbcp2_cpxdp_q0_hold_ca_l[3]), // Templated
.arbcp2_cpxdp_qsel0_ca(arbcp2_cpxdp_qsel0_ca[3]), // Templated
.arbcp2_cpxdp_qsel1_ca_l(arbcp2_cpxdp_qsel1_ca_l[3]), // Templated
.arbcp2_cpxdp_shift_cx(arbcp2_cpxdp_shift_cx[3]), // Templated
.arbcp4_cpxdp_grant_ca(arbcp4_cpxdp_grant_ca[3]), // Templated
.arbcp4_cpxdp_q0_hold_ca_l(arbcp4_cpxdp_q0_hold_ca_l[3]), // Templated
.arbcp4_cpxdp_qsel0_ca(arbcp4_cpxdp_qsel0_ca[3]), // Templated
.arbcp4_cpxdp_qsel1_ca_l(arbcp4_cpxdp_qsel1_ca_l[3]), // Templated
.arbcp4_cpxdp_shift_cx(arbcp4_cpxdp_shift_cx[3]), // Templated
.arbcp6_cpxdp_grant_ca(arbcp6_cpxdp_grant_ca[3]), // Templated
.arbcp6_cpxdp_q0_hold_ca_l(arbcp6_cpxdp_q0_hold_ca_l[3]), // Templated
.arbcp6_cpxdp_qsel0_ca(arbcp6_cpxdp_qsel0_ca[3]), // Templated
.arbcp6_cpxdp_qsel1_ca_l(arbcp6_cpxdp_qsel1_ca_l[3]), // Templated
.arbcp6_cpxdp_shift_cx(arbcp6_cpxdp_shift_cx[3]), // Templated
// Inputs
.arbcp0_cpxdp_grant_bufp3_ca_l(arbcp0_cpxdp_grant_bufp1_ca_l[3]), // Templated
.arbcp0_cpxdp_q0_hold_bufp3_ca(arbcp0_cpxdp_q0_hold_bufp1_ca[3]), // Templated
.arbcp0_cpxdp_qsel0_bufp3_ca_l(arbcp0_cpxdp_qsel0_bufp1_ca_l[3]), // Templated
.arbcp0_cpxdp_qsel1_bufp3_ca(arbcp0_cpxdp_qsel1_bufp1_ca[3]), // Templated
.arbcp0_cpxdp_shift_bufp3_cx_l(arbcp0_cpxdp_shift_bufp1_cx_l[3]), // Templated
.arbcp2_cpxdp_grant_bufp3_ca_l(arbcp2_cpxdp_grant_bufp1_ca_l[3]), // Templated
.arbcp2_cpxdp_q0_hold_bufp3_ca(arbcp2_cpxdp_q0_hold_bufp1_ca[3]), // Templated
.arbcp2_cpxdp_qsel0_bufp3_ca_l(arbcp2_cpxdp_qsel0_bufp1_ca_l[3]), // Templated
.arbcp2_cpxdp_qsel1_bufp3_ca(arbcp2_cpxdp_qsel1_bufp1_ca[3]), // Templated
.arbcp2_cpxdp_shift_bufp3_cx_l(arbcp2_cpxdp_shift_bufp1_cx_l[3]), // Templated
.arbcp4_cpxdp_grant_bufp3_ca_l(arbcp4_cpxdp_grant_bufp1_ca_l[3]), // Templated
.arbcp4_cpxdp_q0_hold_bufp3_ca(arbcp4_cpxdp_q0_hold_bufp1_ca[3]), // Templated
.arbcp4_cpxdp_qsel0_bufp3_ca_l(arbcp4_cpxdp_qsel0_bufp1_ca_l[3]), // Templated
.arbcp4_cpxdp_qsel1_bufp3_ca(arbcp4_cpxdp_qsel1_bufp1_ca[3]), // Templated
.arbcp4_cpxdp_shift_bufp3_cx_l(arbcp4_cpxdp_shift_bufp1_cx_l[3]), // Templated
.arbcp6_cpxdp_grant_bufp3_ca_l(arbcp6_cpxdp_grant_bufp1_ca_l[3]), // Templated
.arbcp6_cpxdp_q0_hold_bufp3_ca(arbcp6_cpxdp_q0_hold_bufp1_ca[3]), // Templated
.arbcp6_cpxdp_qsel0_bufp3_ca_l(arbcp6_cpxdp_qsel0_bufp1_ca_l[3]), // Templated
.arbcp6_cpxdp_qsel1_bufp3_ca(arbcp6_cpxdp_qsel1_bufp1_ca[3]), // Templated
.arbcp6_cpxdp_shift_bufp3_cx_l(arbcp6_cpxdp_shift_bufp1_cx_l[3])); // Templated
/* cpx_buf_p4_even AUTO_TEMPLATE(
// Outputs
.arbcp0_cpxdp_grant_ca (arbcp1_cpxdp_grant_ca[3]),
.arbcp0_cpxdp_q0_hold_ca_l(arbcp1_cpxdp_q0_hold_ca_l[3]),
.arbcp0_cpxdp_qsel0_ca (arbcp1_cpxdp_qsel0_ca[3]),
.arbcp0_cpxdp_qsel1_ca_l(arbcp1_cpxdp_qsel1_ca_l[3]),
.arbcp0_cpxdp_shift_cx (arbcp1_cpxdp_shift_cx[3]),
.arbcp2_cpxdp_grant_ca (arbcp3_cpxdp_grant_ca[3]),
.arbcp2_cpxdp_q0_hold_ca_l(arbcp3_cpxdp_q0_hold_ca_l[3]),
.arbcp2_cpxdp_qsel0_ca (arbcp3_cpxdp_qsel0_ca[3]),
.arbcp2_cpxdp_qsel1_ca_l(arbcp3_cpxdp_qsel1_ca_l[3]),
.arbcp2_cpxdp_shift_cx (arbcp3_cpxdp_shift_cx[3]),
.arbcp4_cpxdp_grant_ca (arbcp5_cpxdp_grant_ca[3]),
.arbcp4_cpxdp_q0_hold_ca_l(arbcp5_cpxdp_q0_hold_ca_l[3]),
.arbcp4_cpxdp_qsel0_ca (arbcp5_cpxdp_qsel0_ca[3]),
.arbcp4_cpxdp_qsel1_ca_l(arbcp5_cpxdp_qsel1_ca_l[3]),
.arbcp4_cpxdp_shift_cx (arbcp5_cpxdp_shift_cx[3]),
.arbcp6_cpxdp_grant_ca (arbcp7_cpxdp_grant_ca[3]),
.arbcp6_cpxdp_q0_hold_ca_l(arbcp7_cpxdp_q0_hold_ca_l[3]),
.arbcp6_cpxdp_qsel0_ca (arbcp7_cpxdp_qsel0_ca[3]),
.arbcp6_cpxdp_qsel1_ca_l(arbcp7_cpxdp_qsel1_ca_l[3]),
.arbcp6_cpxdp_shift_cx (arbcp7_cpxdp_shift_cx[3]),
// Inputs
.arbcp0_cpxdp_grant_bufp3_ca_l(arbcp1_cpxdp_grant_bufp1_ca_l[3]),
.arbcp0_cpxdp_q0_hold_bufp3_ca(arbcp1_cpxdp_q0_hold_bufp1_ca[3]),
.arbcp0_cpxdp_qsel0_bufp3_ca_l(arbcp1_cpxdp_qsel0_bufp1_ca_l[3]),
.arbcp0_cpxdp_qsel1_bufp3_ca(arbcp1_cpxdp_qsel1_bufp1_ca[3]),
.arbcp0_cpxdp_shift_bufp3_cx_l(arbcp1_cpxdp_shift_bufp1_cx_l[3]),
.arbcp2_cpxdp_grant_bufp3_ca_l(arbcp3_cpxdp_grant_bufp1_ca_l[3]),
.arbcp2_cpxdp_q0_hold_bufp3_ca(arbcp3_cpxdp_q0_hold_bufp1_ca[3]),
.arbcp2_cpxdp_qsel0_bufp3_ca_l(arbcp3_cpxdp_qsel0_bufp1_ca_l[3]),
.arbcp2_cpxdp_qsel1_bufp3_ca(arbcp3_cpxdp_qsel1_bufp1_ca[3]),
.arbcp2_cpxdp_shift_bufp3_cx_l(arbcp3_cpxdp_shift_bufp1_cx_l[3]),
.arbcp4_cpxdp_grant_bufp3_ca_l(arbcp5_cpxdp_grant_bufp1_ca_l[3]),
.arbcp4_cpxdp_q0_hold_bufp3_ca(arbcp5_cpxdp_q0_hold_bufp1_ca[3]),
.arbcp4_cpxdp_qsel0_bufp3_ca_l(arbcp5_cpxdp_qsel0_bufp1_ca_l[3]),
.arbcp4_cpxdp_qsel1_bufp3_ca(arbcp5_cpxdp_qsel1_bufp1_ca[3]),
.arbcp4_cpxdp_shift_bufp3_cx_l(arbcp5_cpxdp_shift_bufp1_cx_l[3]),
.arbcp6_cpxdp_grant_bufp3_ca_l(arbcp7_cpxdp_grant_bufp1_ca_l[3]),
.arbcp6_cpxdp_q0_hold_bufp3_ca(arbcp7_cpxdp_q0_hold_bufp1_ca[3]),
.arbcp6_cpxdp_qsel0_bufp3_ca_l(arbcp7_cpxdp_qsel0_bufp1_ca_l[3]),
.arbcp6_cpxdp_qsel1_bufp3_ca(arbcp7_cpxdp_qsel1_bufp1_ca[3]),
.arbcp6_cpxdp_shift_bufp3_cx_l(arbcp7_cpxdp_shift_bufp1_cx_l[3]));
*/
cpx_buf_p4_even p4_odd(/*AUTOINST*/
// Outputs
.arbcp0_cpxdp_grant_ca(arbcp1_cpxdp_grant_ca[3]), // Templated
.arbcp0_cpxdp_q0_hold_ca_l(arbcp1_cpxdp_q0_hold_ca_l[3]), // Templated
.arbcp0_cpxdp_qsel0_ca(arbcp1_cpxdp_qsel0_ca[3]), // Templated
.arbcp0_cpxdp_qsel1_ca_l(arbcp1_cpxdp_qsel1_ca_l[3]), // Templated
.arbcp0_cpxdp_shift_cx(arbcp1_cpxdp_shift_cx[3]), // Templated
.arbcp2_cpxdp_grant_ca(arbcp3_cpxdp_grant_ca[3]), // Templated
.arbcp2_cpxdp_q0_hold_ca_l(arbcp3_cpxdp_q0_hold_ca_l[3]), // Templated
.arbcp2_cpxdp_qsel0_ca(arbcp3_cpxdp_qsel0_ca[3]), // Templated
.arbcp2_cpxdp_qsel1_ca_l(arbcp3_cpxdp_qsel1_ca_l[3]), // Templated
.arbcp2_cpxdp_shift_cx(arbcp3_cpxdp_shift_cx[3]), // Templated
.arbcp4_cpxdp_grant_ca(arbcp5_cpxdp_grant_ca[3]), // Templated
.arbcp4_cpxdp_q0_hold_ca_l(arbcp5_cpxdp_q0_hold_ca_l[3]), // Templated
.arbcp4_cpxdp_qsel0_ca(arbcp5_cpxdp_qsel0_ca[3]), // Templated
.arbcp4_cpxdp_qsel1_ca_l(arbcp5_cpxdp_qsel1_ca_l[3]), // Templated
.arbcp4_cpxdp_shift_cx(arbcp5_cpxdp_shift_cx[3]), // Templated
.arbcp6_cpxdp_grant_ca(arbcp7_cpxdp_grant_ca[3]), // Templated
.arbcp6_cpxdp_q0_hold_ca_l(arbcp7_cpxdp_q0_hold_ca_l[3]), // Templated
.arbcp6_cpxdp_qsel0_ca(arbcp7_cpxdp_qsel0_ca[3]), // Templated
.arbcp6_cpxdp_qsel1_ca_l(arbcp7_cpxdp_qsel1_ca_l[3]), // Templated
.arbcp6_cpxdp_shift_cx(arbcp7_cpxdp_shift_cx[3]), // Templated
// Inputs
.arbcp0_cpxdp_grant_bufp3_ca_l(arbcp1_cpxdp_grant_bufp1_ca_l[3]), // Templated
.arbcp0_cpxdp_q0_hold_bufp3_ca(arbcp1_cpxdp_q0_hold_bufp1_ca[3]), // Templated
.arbcp0_cpxdp_qsel0_bufp3_ca_l(arbcp1_cpxdp_qsel0_bufp1_ca_l[3]), // Templated
.arbcp0_cpxdp_qsel1_bufp3_ca(arbcp1_cpxdp_qsel1_bufp1_ca[3]), // Templated
.arbcp0_cpxdp_shift_bufp3_cx_l(arbcp1_cpxdp_shift_bufp1_cx_l[3]), // Templated
.arbcp2_cpxdp_grant_bufp3_ca_l(arbcp3_cpxdp_grant_bufp1_ca_l[3]), // Templated
.arbcp2_cpxdp_q0_hold_bufp3_ca(arbcp3_cpxdp_q0_hold_bufp1_ca[3]), // Templated
.arbcp2_cpxdp_qsel0_bufp3_ca_l(arbcp3_cpxdp_qsel0_bufp1_ca_l[3]), // Templated
.arbcp2_cpxdp_qsel1_bufp3_ca(arbcp3_cpxdp_qsel1_bufp1_ca[3]), // Templated
.arbcp2_cpxdp_shift_bufp3_cx_l(arbcp3_cpxdp_shift_bufp1_cx_l[3]), // Templated
.arbcp4_cpxdp_grant_bufp3_ca_l(arbcp5_cpxdp_grant_bufp1_ca_l[3]), // Templated
.arbcp4_cpxdp_q0_hold_bufp3_ca(arbcp5_cpxdp_q0_hold_bufp1_ca[3]), // Templated
.arbcp4_cpxdp_qsel0_bufp3_ca_l(arbcp5_cpxdp_qsel0_bufp1_ca_l[3]), // Templated
.arbcp4_cpxdp_qsel1_bufp3_ca(arbcp5_cpxdp_qsel1_bufp1_ca[3]), // Templated
.arbcp4_cpxdp_shift_bufp3_cx_l(arbcp5_cpxdp_shift_bufp1_cx_l[3]), // Templated
.arbcp6_cpxdp_grant_bufp3_ca_l(arbcp7_cpxdp_grant_bufp1_ca_l[3]), // Templated
.arbcp6_cpxdp_q0_hold_bufp3_ca(arbcp7_cpxdp_q0_hold_bufp1_ca[3]), // Templated
.arbcp6_cpxdp_qsel0_bufp3_ca_l(arbcp7_cpxdp_qsel0_bufp1_ca_l[3]), // Templated
.arbcp6_cpxdp_qsel1_bufp3_ca(arbcp7_cpxdp_qsel1_bufp1_ca[3]), // Templated
.arbcp6_cpxdp_shift_bufp3_cx_l(arbcp7_cpxdp_shift_bufp1_cx_l[3])); // Templated
/*
cpx_datacx2_ff AUTO_TEMPLATE(
// Outputs
.cpx_spc_data_cx2 (cpx_spc@_data_cx2[`CPX_WIDTH-1:0]),
.cpx_spc_data_rdy_cx2(cpx_spc@_data_rdy_cx2),
.so (ff0_so_1),
// Inputs
.se(se_buf4_top),
.cpx_spc_data_cx_l(cpx_spc@_data_cx_l[`CPX_WIDTH-1:0]),
.cpx_spc_data_rdy_cx(cpx_spc@_data_rdy_bufp0_cx),
.clk (clk),
.si (ff1_so_1));
*/
cpx_datacx2_ff ff0(/*AUTOINST*/
// Outputs
.cpx_spc_data_cx2 (cpx_spc0_data_cx2[`CPX_WIDTH-1:0]), // Templated
.cpx_spc_data_rdy_cx2(cpx_spc0_data_rdy_cx2), // Templated
.so (ff0_so_1), // Templated
// Inputs
.cpx_spc_data_cx_l(cpx_spc0_data_cx_l[`CPX_WIDTH-1:0]), // Templated
.cpx_spc_data_rdy_cx(cpx_spc0_data_rdy_bufp0_cx), // Templated
.rclk (rclk),
.si (ff1_so_1), // Templated
.se (se_buf4_top)); // Templated
/*
cpx_datacx2_ff AUTO_TEMPLATE(
// Outputs
.cpx_spc_data_cx2 (cpx_spc@_data_cx2[`CPX_WIDTH-1:0]),
.cpx_spc_data_rdy_cx2(cpx_spc@_data_rdy_cx2),
.so (ff1_so_1),
// Inputs
.se(se_buf4_bottom),
.cpx_spc_data_cx_l(cpx_spc@_data_cx_l[`CPX_WIDTH-1:0]),
.cpx_spc_data_rdy_cx(cpx_spc@_data_rdy_bufp1_cx),
.clk (clk),
.si (ff3_so_1));
*/
cpx_datacx2_ff ff1(/*AUTOINST*/
// Outputs
.cpx_spc_data_cx2 (cpx_spc1_data_cx2[`CPX_WIDTH-1:0]), // Templated
.cpx_spc_data_rdy_cx2(cpx_spc1_data_rdy_cx2), // Templated
.so (ff1_so_1), // Templated
// Inputs
.cpx_spc_data_cx_l(cpx_spc1_data_cx_l[`CPX_WIDTH-1:0]), // Templated
.cpx_spc_data_rdy_cx(cpx_spc1_data_rdy_bufp1_cx), // Templated
.rclk (rclk),
.si (ff3_so_1), // Templated
.se (se_buf4_bottom)); // Templated
/*
cpx_datacx2_ff AUTO_TEMPLATE(
// Outputs
.cpx_spc_data_cx2 (cpx_spc@_data_cx2[`CPX_WIDTH-1:0]),
.cpx_spc_data_rdy_cx2(cpx_spc@_data_rdy_cx2),
.so (ff2_so_1),
// Inputs
.se(se_buf4_top),
.cpx_spc_data_cx_l(cpx_spc@_data_cx_l[`CPX_WIDTH-1:0]),
.cpx_spc_data_rdy_cx(cpx_spc@_data_rdy_bufp1_cx),
.clk (clk),
.si (ff4_so_1));
*/
cpx_datacx2_ff ff2(/*AUTOINST*/
// Outputs
.cpx_spc_data_cx2 (cpx_spc2_data_cx2[`CPX_WIDTH-1:0]), // Templated
.cpx_spc_data_rdy_cx2(cpx_spc2_data_rdy_cx2), // Templated
.so (ff2_so_1), // Templated
// Inputs
.cpx_spc_data_cx_l(cpx_spc2_data_cx_l[`CPX_WIDTH-1:0]), // Templated
.cpx_spc_data_rdy_cx(cpx_spc2_data_rdy_bufp1_cx), // Templated
.rclk (rclk),
.si (ff4_so_1), // Templated
.se (se_buf4_top)); // Templated
/*
cpx_datacx2_ff AUTO_TEMPLATE(
// Outputs
.cpx_spc_data_cx2 (cpx_spc@_data_cx2[`CPX_WIDTH-1:0]),
.cpx_spc_data_rdy_cx2(cpx_spc@_data_rdy_cx2),
.so (ff3_so_1),
// Inputs
.se(se_buf4_bottom),
.cpx_spc_data_cx_l(cpx_spc@_data_cx_l[`CPX_WIDTH-1:0]),
.cpx_spc_data_rdy_cx(cpx_spc@_data_rdy_cx),
.clk (clk),
.si (ff2_so_1));
*/
cpx_datacx2_ff ff3(/*AUTOINST*/
// Outputs
.cpx_spc_data_cx2 (cpx_spc3_data_cx2[`CPX_WIDTH-1:0]), // Templated
.cpx_spc_data_rdy_cx2(cpx_spc3_data_rdy_cx2), // Templated
.so (ff3_so_1), // Templated
// Inputs
.cpx_spc_data_cx_l(cpx_spc3_data_cx_l[`CPX_WIDTH-1:0]), // Templated
.cpx_spc_data_rdy_cx(cpx_spc3_data_rdy_cx), // Templated
.rclk (rclk),
.si (ff2_so_1), // Templated
.se (se_buf4_bottom)); // Templated
/*
cpx_datacx2_ff AUTO_TEMPLATE(
// Outputs
.cpx_spc_data_cx2 (cpx_spc@_data_cx2[`CPX_WIDTH-1:0]),
.cpx_spc_data_rdy_cx2(cpx_spc@_data_rdy_cx2),
.so (ff4_so_1),
// Inputs
.se(se_buf2_top),
.cpx_spc_data_cx_l(cpx_spc@_data_cx_l[`CPX_WIDTH-1:0]),
.cpx_spc_data_rdy_cx(cpx_spc@_data_rdy_cx),
.clk (clk),
.si (ff5_so_1));
*/
cpx_datacx2_ff ff4(/*AUTOINST*/
// Outputs
.cpx_spc_data_cx2 (cpx_spc4_data_cx2[`CPX_WIDTH-1:0]), // Templated
.cpx_spc_data_rdy_cx2(cpx_spc4_data_rdy_cx2), // Templated
.so (ff4_so_1), // Templated
// Inputs
.cpx_spc_data_cx_l(cpx_spc4_data_cx_l[`CPX_WIDTH-1:0]), // Templated
.cpx_spc_data_rdy_cx(cpx_spc4_data_rdy_cx), // Templated
.rclk (rclk),
.si (ff5_so_1), // Templated
.se (se_buf2_top)); // Templated
/*
cpx_datacx2_ff AUTO_TEMPLATE(
// Outputs
.cpx_spc_data_cx2 (cpx_spc@_data_cx2[`CPX_WIDTH-1:0]),
.cpx_spc_data_rdy_cx2(cpx_spc@_data_rdy_cx2),
.so (ff5_so_1),
// Inputs
.se(se_buf2_bottom),
.cpx_spc_data_cx_l(cpx_spc@_data_cx_l[`CPX_WIDTH-1:0]),
.cpx_spc_data_rdy_cx(cpx_spc@_data_rdy_bufp3_cx),
.clk (clk),
.si (ff6_so_1));
*/
cpx_datacx2_ff ff5(/*AUTOINST*/
// Outputs
.cpx_spc_data_cx2 (cpx_spc5_data_cx2[`CPX_WIDTH-1:0]), // Templated
.cpx_spc_data_rdy_cx2(cpx_spc5_data_rdy_cx2), // Templated
.so (ff5_so_1), // Templated
// Inputs
.cpx_spc_data_cx_l(cpx_spc5_data_cx_l[`CPX_WIDTH-1:0]), // Templated
.cpx_spc_data_rdy_cx(cpx_spc5_data_rdy_bufp3_cx), // Templated
.rclk (rclk),
.si (ff6_so_1), // Templated
.se (se_buf2_bottom)); // Templated
/*
cpx_datacx2_ff AUTO_TEMPLATE(
// Outputs
.cpx_spc_data_cx2 (cpx_spc@_data_cx2[`CPX_WIDTH-1:0]),
.cpx_spc_data_rdy_cx2(cpx_spc@_data_rdy_cx2),
.so (ff6_so_1),
// Inputs
.se(se_buf2_top),
.cpx_spc_data_cx_l(cpx_spc@_data_cx_l[`CPX_WIDTH-1:0]),
.cpx_spc_data_rdy_cx(cpx_spc@_data_rdy_bufp3_cx),
.clk (clk),
.si (ff7_so_1));
*/
cpx_datacx2_ff ff6(/*AUTOINST*/
// Outputs
.cpx_spc_data_cx2 (cpx_spc6_data_cx2[`CPX_WIDTH-1:0]), // Templated
.cpx_spc_data_rdy_cx2(cpx_spc6_data_rdy_cx2), // Templated
.so (ff6_so_1), // Templated
// Inputs
.cpx_spc_data_cx_l(cpx_spc6_data_cx_l[`CPX_WIDTH-1:0]), // Templated
.cpx_spc_data_rdy_cx(cpx_spc6_data_rdy_bufp3_cx), // Templated
.rclk (rclk),
.si (ff7_so_1), // Templated
.se (se_buf2_top)); // Templated
/*
cpx_datacx2_ff AUTO_TEMPLATE(
// Outputs
.cpx_spc_data_cx2 (cpx_spc@_data_cx2[`CPX_WIDTH-1:0]),
.cpx_spc_data_rdy_cx2(cpx_spc@_data_rdy_cx2),
.so (ff7_so_1),
// Inputs
.se(se_buf2_bottom),
.cpx_spc_data_cx_l(cpx_spc@_data_cx_l[`CPX_WIDTH-1:0]),
.cpx_spc_data_rdy_cx(cpx_spc@_data_rdy_bufp4_cx),
.clk (clk),
.si (si_1));
*/
cpx_datacx2_ff ff7(/*AUTOINST*/
// Outputs
.cpx_spc_data_cx2 (cpx_spc7_data_cx2[`CPX_WIDTH-1:0]), // Templated
.cpx_spc_data_rdy_cx2(cpx_spc7_data_rdy_cx2), // Templated
.so (ff7_so_1), // Templated
// Inputs
.cpx_spc_data_cx_l(cpx_spc7_data_cx_l[`CPX_WIDTH-1:0]), // Templated
.cpx_spc_data_rdy_cx(cpx_spc7_data_rdy_bufp4_cx), // Templated
.rclk (rclk),
.si (si_1), // Templated
.se (se_buf2_bottom)); // Templated
/*
io_cpx_reqdata_ff AUTO_TEMPLATE(
// Outputs
.scan_out (io_cpx_reqdata_ff_so_1),
// Inputs
.se(se_buf3_top),
.scan_in (ff_io_grant_so_1));
*/
io_cpx_reqdata_ff ff_io(/*AUTOINST*/
// Outputs
.io_cpx_data_ca2(io_cpx_data_ca2[`CPX_WIDTH-1:0]),
.io_cpx_req_cq2(io_cpx_req_cq2[7:0]),
.scan_out (io_cpx_reqdata_ff_so_1), // Templated
// Inputs
.io_cpx_data_ca(io_cpx_data_ca[`CPX_WIDTH-1:0]),
.io_cpx_req_cq(io_cpx_req_cq[7:0]),
.rclk (rclk),
.scan_in (ff_io_grant_so_1), // Templated
.se (se_buf3_top)); // Templated
/*
cpx_io_grant_ff AUTO_TEMPLATE(
// Outputs
.so (ff_io_grant_so_1),
// Inputs
.se(se_buf3_top),
.si (ff0_so_1));
*/
cpx_io_grant_ff ff_io_grant(/*AUTOINST*/
// Outputs
.cpx_io_grant_cx2(cpx_io_grant_cx2[7:0]),
.so (ff_io_grant_so_1), // Templated
// Inputs
.cpx_io_grant_cx(cpx_io_grant_cx[7:0]),
.rclk (rclk),
.si (ff0_so_1), // Templated
.se (se_buf3_top)); // Templated
/*
cpx_databuf_ca AUTO_TEMPLATE(
.sctag_cpx_data_buf_pa(fp_cpx_data_buf_ca[`CPX_WIDTH-1:0]),
.sctag_cpx_data_pa(fp_cpx_data_buf1_ca[`CPX_WIDTH-1:0]));
*/
cpx_databuf_ca buf_fp_cpx_data(/*AUTOINST*/
// Outputs
.sctag_cpx_data_buf_pa(fp_cpx_data_buf_ca[`CPX_WIDTH-1:0]), // Templated
// Inputs
.sctag_cpx_data_pa(fp_cpx_data_buf1_ca[`CPX_WIDTH-1:0])); // Templated
/*
cpx_databuf_ca2 AUTO_TEMPLATE(
.sctag_cpx_data_buf_pa(fp_cpx_data_buf1_ca[`CPX_WIDTH-1:0]),
.sctag_cpx_data_pa(fp_cpx_data_ca[`CPX_WIDTH-1:0]));
*/
cpx_databuf_ca2 buf2_fp_cpx_data(/*AUTOINST*/
// Outputs
.sctag_cpx_data_buf_pa(fp_cpx_data_buf1_ca[`CPX_WIDTH-1:0]), // Templated
// Inputs
.sctag_cpx_data_pa(fp_cpx_data_ca[`CPX_WIDTH-1:0])); // Templated
/*
cpx_databuf_ca AUTO_TEMPLATE(
.sctag_cpx_data_buf_pa(sctag@_cpx_data_buf_ca[`CPX_WIDTH-1:0]),
.sctag_cpx_data_pa(sctag@_cpx_data_ca[`CPX_WIDTH-1:0]));
*/
cpx_databuf_ca buf_sctag0_cpx_data(/*AUTOINST*/
// Outputs
.sctag_cpx_data_buf_pa(sctag0_cpx_data_buf_ca[`CPX_WIDTH-1:0]), // Templated
// Inputs
.sctag_cpx_data_pa(sctag0_cpx_data_ca[`CPX_WIDTH-1:0])); // Templated
cpx_databuf_ca buf_sctag1_cpx_data(/*AUTOINST*/
// Outputs
.sctag_cpx_data_buf_pa(sctag1_cpx_data_buf_ca[`CPX_WIDTH-1:0]), // Templated
// Inputs
.sctag_cpx_data_pa(sctag1_cpx_data_ca[`CPX_WIDTH-1:0])); // Templated
cpx_databuf_ca buf_sctag2_cpx_data(/*AUTOINST*/
// Outputs
.sctag_cpx_data_buf_pa(sctag2_cpx_data_buf_ca[`CPX_WIDTH-1:0]), // Templated
// Inputs
.sctag_cpx_data_pa(sctag2_cpx_data_ca[`CPX_WIDTH-1:0])); // Templated
cpx_databuf_ca buf_sctag3_cpx_data(/*AUTOINST*/
// Outputs
.sctag_cpx_data_buf_pa(sctag3_cpx_data_buf_ca[`CPX_WIDTH-1:0]), // Templated
// Inputs
.sctag_cpx_data_pa(sctag3_cpx_data_ca[`CPX_WIDTH-1:0])); // Templated
/*
cpx_databuf_ca AUTO_TEMPLATE(
.sctag_cpx_data_buf_pa(io_cpx_data_buf1_ca2[`CPX_WIDTH-1:0]),
.sctag_cpx_data_pa(io_cpx_data_ca2[`CPX_WIDTH-1:0]));
*/
cpx_databuf_ca buf1_io_cpx_data(/*AUTOINST*/
// Outputs
.sctag_cpx_data_buf_pa(io_cpx_data_buf1_ca2[`CPX_WIDTH-1:0]), // Templated
// Inputs
.sctag_cpx_data_pa(io_cpx_data_ca2[`CPX_WIDTH-1:0])); // Templated
/* cpx_buf_io AUTO_TEMPLATE(
// Outputs
.cpx_io_grant_bufio_ca(cpx_io_grant_buf1_io_ca[7:0]),
.io_cpx_req_bufio_cq_l(io_cpx_req_buf1_io_cq[7:0]),
// Inputs
.cpx_io_grant_ca(cpx_io_grant_ca[7:0]),
.io_cpx_req_cq(io_cpx_req_bufpt_cq_l[7:0]));
*/
cpx_buf_io buf1_io(/*AUTOINST*/
// Outputs
.cpx_io_grant_bufio_ca(cpx_io_grant_buf1_io_ca[7:0]), // Templated
.io_cpx_req_bufio_cq_l(io_cpx_req_buf1_io_cq[7:0]), // Templated
// Inputs
.cpx_io_grant_ca(cpx_io_grant_ca[7:0]), // Templated
.io_cpx_req_cq(io_cpx_req_bufpt_cq_l[7:0])); // Templated
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../../../common/rtl" "../../common/rtl")
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV3SD2_1_V
`define SKY130_FD_SC_HS__CLKDLYINV3SD2_1_V
/**
* clkdlyinv3sd2: Clock Delay Inverter 3-stage 0.25um length inner
* stage gate.
*
* Verilog wrapper for clkdlyinv3sd2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__clkdlyinv3sd2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__clkdlyinv3sd2_1 (
Y ,
A ,
VPWR,
VGND
);
output Y ;
input A ;
input VPWR;
input VGND;
sky130_fd_sc_hs__clkdlyinv3sd2 base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__clkdlyinv3sd2_1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__clkdlyinv3sd2 base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV3SD2_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND2_PP_SYMBOL_V
`define SKY130_FD_SC_LP__NAND2_PP_SYMBOL_V
/**
* nand2: 2-input NAND.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nand2 (
//# {{data|Data Signals}}
input A ,
input B ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND2_PP_SYMBOL_V
|
//----------------------------------------------------------------------------
// Copyright (C) 2014 , Atsushi Sasaki
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: i2s_to_tdm_converter.v
//
// *Module Description:
// I2S to TDM Converter
//
// *Author(s):
// - Atsushi Sasaki, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 1.00 $
// $LastChangedBy: Atsushi Sasaki $
// $LastChangedDate: 2014-06-06 $
//----------------------------------------------------------------------------
module i2s_to_tdm_comverter(
rst_i,
mck_i,
bck_i,
lrck_i,
dat_i,
sck_o,
fsync_o,
dat_o
);
//
// Parameters
//
//
// I/O Ports
//
input rst_i; // reset
input mck_i; // 256fs
input bck_i; // 64fs
input lrck_i; // fs
input [3:0] dat_i;
output sck_o; // 256fs
output fsync_o; // fs
output reg dat_o; // multi ch output
//
// Wires, Registers
//
reg rst_int;
wire rst = rst_i | rst_int;
reg [8:0] bit_cnt; // input data bit counter
wire bank = bit_cnt[8];
// reg bank; // FIFO Buffer Bank
wire sck = mck_i; // internal system clock
assign sck_o = sck;
wire [5:0] inbit_cnt = bit_cnt[7:2];
//
// module
//
// LRCK Negedge Detector
reg d_lrck_1, d_lrck_2, d_lrck_3, d_lrck_4, d_lrck_5, d_lrck_6; // Delayed LRCK
wire lrck_negedge_flag; // Frame Sync for LRCK Falling Edge
assign lrck_negedge_flag = (d_lrck_4 ^ d_lrck_6) & ~d_lrck_4;
always @ (posedge sck or posedge rst_i) begin
if(rst_i) begin
d_lrck_1 <= 1'b0;
d_lrck_2 <= 1'b0;
d_lrck_3 <= 1'b0;
d_lrck_5 <= 1'b0;
end
else begin
d_lrck_1 <= lrck_i;
d_lrck_2 <= d_lrck_1;
d_lrck_3 <= d_lrck_2;
d_lrck_5 <= d_lrck_4;
end
end
always @ (negedge sck or posedge rst_i) begin
if(rst_i) begin
d_lrck_4 <= 1'b0;
d_lrck_6 <= 1'b0;
end
else begin
d_lrck_4 <= d_lrck_3;
d_lrck_6 <= d_lrck_5;
end
end
// Internal Async Reset
always @ (negedge d_lrck_4 or posedge rst_i) begin
if(rst_i) begin
rst_int <= 1'b1;
end
else begin
if(&bit_cnt[7:0]) begin
rst_int <= 1'b0;
end
else begin
rst_int <= 1'b1;
end
end
end
// Bit counter
always @ (negedge sck or posedge rst) begin
if(rst) begin
bit_cnt <= 9'b111111111;
end
else begin
bit_cnt <= bit_cnt + 1'b1;
end
end
// Input Buffer
reg [255:0] fifo_a;
reg [255:0] fifo_b;
always @ (posedge bck_i or posedge rst) begin
if(rst) begin
fifo_a <= 256'b0;
fifo_b <= 256'b0;
end
else begin
if(!bank) begin
fifo_a[255-bit_cnt[7:2]] <= dat_i[0];
fifo_a[191-bit_cnt[7:2]] <= dat_i[1];
fifo_a[127-bit_cnt[7:2]] <= dat_i[2];
fifo_a[63-bit_cnt[7:2]] <= dat_i[3];
end
else begin
fifo_b[255-bit_cnt[7:2]] <= dat_i[0];
fifo_b[191-bit_cnt[7:2]] <= dat_i[1];
fifo_b[127-bit_cnt[7:2]] <= dat_i[2];
fifo_b[63-bit_cnt[7:2]] <= dat_i[3];
end
end
end
// TDM Generator
always @ (posedge sck or posedge rst) begin
if(rst) begin
dat_o <= 1'b0;
end
else begin
if(!bank) begin
dat_o <= fifo_b[255-bit_cnt[7:0]];
end
else begin
dat_o <= fifo_a[255-bit_cnt[7:0]];
end
end
end
assign fsync_o = &bit_cnt[7:0];
endmodule
|
/*
RC4 PRGA module implementation
Copyright 2012 - Alfredo Ortega
[email protected]
[email protected]
This library is free software: you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation, either
version 3 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
`include "rc4.inc"
module rc4(clk,rst,output_ready,password_input,K);
input clk; // Clock
input rst; // Reset
input [7:0] password_input; // Password input
output output_ready; // Output valid
output [7:0] K; // Output port
wire clk, rst; // clock, reset
reg output_ready;
wire [7:0] password_input;
/* RC4 PRGA */
// Key
reg [7:0] key[0:`KEY_SIZE-1];
// S array
reg [7:0] S[0:256];
reg [10:0] discardCount;
// Key-scheduling state
`define KSS_KEYREAD 4'h0
`define KSS_KEYSCHED1 4'h1
`define KSS_KEYSCHED2 4'h2
`define KSS_KEYSCHED3 4'h3
`define KSS_CRYPTO 4'h4
// Variable names from http://en.wikipedia.org/wiki/RC4
reg [3:0] KSState;
reg [7:0] i; // Counter
reg [7:0] j;
reg [7:0] K;
always @ (posedge clk or posedge rst)
begin
if (rst)
begin
i <= 8'h0;
KSState <= `KSS_KEYREAD;
output_ready <= 0;
j <= 0;
end
else
case (KSState)
`KSS_KEYREAD: begin // KSS_KEYREAD state: Read key from input
if (i == `KEY_SIZE)
begin
KSState <= `KSS_KEYSCHED1;
i<=8'h00;
end
else begin
i <= i+1;
key[i] <= password_input;
$display ("rc4: key[%d] = %08X",i,password_input);
end
end
/*
for i from 0 to 255
S[i] := i
endfor
*/
`KSS_KEYSCHED1: begin // KSS_KEYSCHED1: Increment counter for S initialization
S[i] <= i;
if (i == 8'hFF)
begin
KSState <= `KSS_KEYSCHED2;
i <= 8'h00;
end
else i <= i +1;
end
/*
j := 0
for i from 0 to 255
j := (j + S[i] + key[i mod keylength]) mod 256
swap values of S[i] and S[j]
endfor
*/
`KSS_KEYSCHED2: begin // KSS_KEYSCHED2: Initialize S array
j <= (j + S[i] + key[i % `KEY_SIZE]);
KSState <= `KSS_KEYSCHED3;
end
`KSS_KEYSCHED3: begin // KSS_KEYSCHED3: S array permutation
S[i]<=S[j];
S[j]<=S[i];
if (i == 8'hFF)
begin
KSState <= `KSS_CRYPTO;
i <= 8'h01;
j <= S[1];
discardCount <= 11'h0;
output_ready <= 0; // K not valid yet
end
else begin
i <= i + 1;
KSState <= `KSS_KEYSCHED2;
end
end
/*
i := 0
j := 0
while GeneratingOutput:
i := (i + 1) mod 256
j := (j + S[i]) mod 256
swap values of S[i] and S[j]
K := S[(S[i] + S[j]) mod 256]
output K
endwhile
*/
`KSS_CRYPTO: begin
S[i] <= S[j];
S[j] <= S[i]; // We can do this because of verilog.
K <= S[ S[i]+S[j] ];
if (discardCount<11'h600) // discard first 1536 values / RFC 4345
discardCount<=discardCount+1;
else output_ready <= 1; // Valid K at output
i <= i+1;
// Here is the secret of 1-clock: we develop all possible values of j in the future
if (j==i+1)
j <= (j + S[i]);
else
if (i==255) j <= (j + S[0]);
else j <= (j + S[i+1]);
//$display ("rc4: output = %08X",K);
end
default: begin
end
endcase
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sat Nov 19 19:32:57 2016
/////////////////////////////////////////////////////////////
module FPU_PIPELINED_FPADDSUB_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
output [31:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire Shift_reg_FLAGS_7_6, Shift_reg_FLAGS_7_5, intAS, SIGN_FLAG_EXP,
OP_FLAG_EXP, ZERO_FLAG_EXP, SIGN_FLAG_SHT1, OP_FLAG_SHT1,
ZERO_FLAG_SHT1, left_right_SHT2, SIGN_FLAG_SHT2, OP_FLAG_SHT2,
ZERO_FLAG_SHT2, SIGN_FLAG_SHT1SHT2, ZERO_FLAG_SHT1SHT2, SIGN_FLAG_NRM,
ZERO_FLAG_NRM, SIGN_FLAG_SFG, OP_FLAG_SFG, ZERO_FLAG_SFG,
inst_FSM_INPUT_ENABLE_state_next_1_, n524, n525, n526, n527, n528,
n529, n530, n531, n532, n533, n534, n535, n536, n537, n538, n539,
n540, n541, n542, n543, n544, n545, n546, n547, n548, n549, n550,
n551, n552, n553, n554, n555, n556, n557, n558, n559, n560, n561,
n562, n563, n564, n565, n566, n567, n568, n569, n570, n571, n572,
n573, n574, n575, n576, n577, n578, n579, n580, n581, n582, n583,
n584, n585, n586, n587, n588, n589, n590, n591, n592, n593, n594,
n595, n596, n597, n598, n599, n600, n601, n602, n603, n604, n605,
n606, n607, n608, n609, n610, n611, n612, n613, n614, n615, n616,
n617, n618, n619, n620, n621, n622, n623, n624, n625, n626, n627,
n628, n629, n630, n631, n632, n633, n634, n635, n636, n637, n638,
n639, n640, n641, n642, n643, n644, n645, n646, n647, n648, n649,
n650, n651, n652, n653, n654, n655, n656, n657, n658, n659, n660,
n661, n662, n663, n664, n665, n666, n667, n668, n669, n670, n671,
n672, n673, n674, n675, n676, n677, n678, n679, n680, n681, n682,
n683, n684, n685, n686, n687, n688, n689, n690, n691, n692, n693,
n694, n695, n696, n697, n698, n699, n700, n701, n702, n703, n704,
n705, n706, n707, n708, n709, n710, n711, n712, n713, n714, n715,
n716, n717, n718, n719, n720, n721, n722, n723, n724, n725, n726,
n727, n728, n729, n730, n731, n732, n733, n734, n735, n736, n737,
n738, n739, n740, n741, n742, n743, n744, n745, n746, n747, n748,
n749, n750, n751, n752, n753, n754, n755, n756, n757, n758, n759,
n760, n761, n762, n763, n764, n765, n766, n767, n768, n769, n770,
n771, n772, n773, n774, n775, n776, n777, n778, n779, n780, n781,
n782, n783, n784, n785, n786, n787, n788, n789, n790, n791, n792,
n793, n794, n795, n796, n797, n798, n799, n800, n801, n802, n803,
n804, n805, n806, n807, n808, n809, n810, n811, n812, n813, n814,
n815, n816, n817, n818, n819, n820, n821, n822, n823, n824, n825,
n826, n827, n828, n830, n831, n832, n833, n834, n835, n836, n837,
n838, n839, n840, n841, n842, n843, n844, n845, n846, n847, n848,
n849, n850, n851, n852, n853, n854, n855, n856, n857, n858, n859,
n860, n861, n862, n863, n864, n865, n866, n867, n868, n869, n870,
n871, n872, n873, n874, n875, n876, n877, n878, n879, n880, n881,
n882, n883, n884, n885, n886, n887, n888, n889, n890, n891, n892,
n893, n894, n895, n896, n897, n898, n899, n900, n901, n902, n903,
n904, n905, n906, n907, n908, n909, n910, n911, n912, n913, n914,
n915, n916, n917, n918, n919, n920, n921, n922, n923, n925, n926,
n927, n928, n929, n930, n931, n932, DP_OP_15J41_125_2314_n8,
DP_OP_15J41_125_2314_n7, DP_OP_15J41_125_2314_n6,
DP_OP_15J41_125_2314_n5, DP_OP_15J41_125_2314_n4, intadd_46_A_12_,
intadd_46_A_11_, intadd_46_A_10_, intadd_46_A_9_, intadd_46_A_8_,
intadd_46_A_7_, intadd_46_A_6_, intadd_46_A_5_, intadd_46_A_4_,
intadd_46_A_3_, intadd_46_A_2_, intadd_46_A_0_, intadd_46_B_12_,
intadd_46_B_11_, intadd_46_B_10_, intadd_46_B_9_, intadd_46_B_8_,
intadd_46_B_7_, intadd_46_B_6_, intadd_46_B_5_, intadd_46_B_4_,
intadd_46_B_3_, intadd_46_B_2_, intadd_46_B_1_, intadd_46_B_0_,
intadd_46_CI, intadd_46_SUM_12_, intadd_46_SUM_11_, intadd_46_SUM_10_,
intadd_46_SUM_9_, intadd_46_SUM_8_, intadd_46_SUM_7_,
intadd_46_SUM_6_, intadd_46_SUM_5_, intadd_46_SUM_4_,
intadd_46_SUM_3_, intadd_46_SUM_2_, intadd_46_SUM_1_,
intadd_46_SUM_0_, intadd_46_n13, intadd_46_n12, intadd_46_n11,
intadd_46_n10, intadd_46_n9, intadd_46_n8, intadd_46_n7, intadd_46_n6,
intadd_46_n5, intadd_46_n4, intadd_46_n3, intadd_46_n2, intadd_46_n1,
n933, n934, n935, n936, n937, n938, n939, n940, n941, n942, n943,
n944, n945, n946, n947, n948, n949, n950, n951, n952, n953, n955,
n956, n957, n958, n959, n960, n961, n962, n963, n964, n965, n966,
n967, n968, n969, n970, n971, n972, n973, n974, n975, n976, n977,
n978, n979, n980, n981, n982, n983, n984, n985, n986, n987, n988,
n989, n990, n991, n992, n993, n994, n995, n996, n998, n999, n1000,
n1001, n1002, n1003, n1004, n1005, n1006, n1007, n1008, n1009, n1010,
n1011, n1012, n1013, n1014, n1015, n1016, n1017, n1018, n1019, n1020,
n1021, n1022, n1023, n1024, n1025, n1026, n1027, n1028, n1029, n1030,
n1031, n1032, n1033, n1034, n1035, n1036, n1037, n1038, n1039, n1040,
n1041, n1042, n1043, n1044, n1045, n1046, n1047, n1048, n1049, n1050,
n1051, n1052, n1053, n1054, n1055, n1056, n1057, n1058, n1059, n1060,
n1061, n1062, n1063, n1064, n1065, n1066, n1067, n1068, n1069, n1070,
n1071, n1072, n1073, n1074, n1075, n1076, n1077, n1078, n1079, n1080,
n1081, n1082, n1083, n1084, n1085, n1086, n1087, n1088, n1089, n1090,
n1091, n1092, n1093, n1094, n1095, n1096, n1097, n1098, n1099, n1100,
n1101, n1102, n1103, n1104, n1105, n1106, n1107, n1108, n1109, n1110,
n1111, n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119, n1120,
n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129, n1130,
n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139, n1140,
n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149, n1150,
n1151, n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159, n1160,
n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170,
n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179, n1180,
n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1190,
n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200,
n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210,
n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220,
n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230,
n1231, n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240,
n1241, n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250,
n1251, n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260,
n1261, n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270,
n1271, n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280,
n1281, n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290,
n1291, n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300,
n1301, n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310,
n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320,
n1321, n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330,
n1331, n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340,
n1341, n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350,
n1351, n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360,
n1361, n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370,
n1371, n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380,
n1381, n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390,
n1391, n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400,
n1401, n1402, n1403, n1404, n1405, n1406, n1408, n1409, n1410, n1411,
n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421,
n1422, n1423, n1425, n1426, n1427, n1428, n1429, n1430, n1431, n1432,
n1433, n1434, n1435, n1436, n1437, n1439, n1440, n1441, n1442, n1443,
n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453,
n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463,
n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473,
n1474, n1475, n1476, n1477, n1478, n1479, n1480, n1481, n1482, n1483,
n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491, n1493, n1494,
n1495, n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504,
n1505, n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514,
n1515, n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524,
n1525, n1526, n1527, n1528, n1529, n1530, n1532, n1533, n1534, n1535,
n1536, n1537, n1538, n1540, n1541, n1542, n1543, n1544, n1545, n1546,
n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556,
n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566,
n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576,
n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586,
n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596,
n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606,
n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616,
n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626,
n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636,
n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646,
n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656,
n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666,
n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676,
n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686,
n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696,
n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706,
n1707, n1708, n1709, n1710, n1711, n1712, n1714, n1715, n1716, n1718;
wire [1:0] Shift_reg_FLAGS_7;
wire [31:0] intDX_EWSW;
wire [31:0] intDY_EWSW;
wire [30:0] DMP_EXP_EWSW;
wire [27:0] DmP_EXP_EWSW;
wire [30:0] DMP_SHT1_EWSW;
wire [14:2] DmP_mant_SHT1_SW;
wire [4:0] Shift_amount_SHT1_EWR;
wire [25:1] Raw_mant_NRM_SWR;
wire [22:0] Data_array_SWR;
wire [30:0] DMP_SHT2_EWSW;
wire [4:2] shift_value_SHT2_EWR;
wire [7:0] DMP_exp_NRM2_EW;
wire [7:0] DMP_exp_NRM_EW;
wire [4:0] LZD_output_NRM2_EW;
wire [4:1] exp_rslt_NRM2_EW1;
wire [30:0] DMP_SFG;
wire [25:0] DmP_mant_SFG_SWR;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS inst_ShiftRegister_Q_reg_3_ ( .D(n927), .CK(clk), .RN(n1702), .QN(
n971) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n904), .CK(clk), .RN(n1699),
.QN(n962) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n901), .CK(clk), .RN(n1705),
.QN(n958) );
DFFRXLTS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n890), .CK(clk), .RN(n1702), .Q(
left_right_SHT2) );
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(Shift_reg_FLAGS_7[0]), .CK(clk), .RN(n1700),
.Q(ready) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n865), .CK(clk), .RN(n943), .Q(
intDY_EWSW[24]), .QN(n964) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n843), .CK(clk), .RN(n1704), .QN(
n965) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n853), .CK(clk), .RN(n943), .QN(n945) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n849), .CK(clk), .RN(n941), .QN(n966) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n826), .CK(clk), .RN(n943), .Q(
Shift_amount_SHT1_EWR[1]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n825), .CK(clk), .RN(n1704),
.Q(Shift_amount_SHT1_EWR[2]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n824), .CK(clk), .RN(n944), .Q(
Shift_amount_SHT1_EWR[3]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n823), .CK(clk), .RN(n943), .Q(
Shift_amount_SHT1_EWR[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n822), .CK(clk), .RN(n937), .Q(
final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n821), .CK(clk), .RN(n1708), .Q(
final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n820), .CK(clk), .RN(n943), .Q(
final_result_ieee[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n819), .CK(clk), .RN(n940), .Q(
final_result_ieee[26]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n818), .CK(clk), .RN(n1702), .Q(
final_result_ieee[27]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n817), .CK(clk), .RN(n1703), .Q(
final_result_ieee[28]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n816), .CK(clk), .RN(n1707), .Q(
final_result_ieee[29]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n815), .CK(clk), .RN(n1702), .Q(
final_result_ieee[30]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(n814), .CK(clk), .RN(n1040), .Q(
DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(n813), .CK(clk), .RN(n941), .Q(
DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(n812), .CK(clk), .RN(n1040), .Q(
DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(n811), .CK(clk), .RN(n1704), .Q(
DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(n810), .CK(clk), .RN(n944), .Q(
DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(n809), .CK(clk), .RN(n943), .Q(
DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(n808), .CK(clk), .RN(n941), .Q(
DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(n807), .CK(clk), .RN(n1040), .Q(
DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(n806), .CK(clk), .RN(n942), .Q(
DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(n805), .CK(clk), .RN(n1701), .Q(
DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(n804), .CK(clk), .RN(n1703), .Q(
DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(n803), .CK(clk), .RN(n1699), .Q(
DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(n802), .CK(clk), .RN(n1705), .Q(
DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(n801), .CK(clk), .RN(n1700), .Q(
DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(n800), .CK(clk), .RN(n1702), .Q(
DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(n799), .CK(clk), .RN(n1701), .Q(
DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(n798), .CK(clk), .RN(n1703), .Q(
DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(n797), .CK(clk), .RN(n1699), .Q(
DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(n796), .CK(clk), .RN(n1705), .Q(
DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(n795), .CK(clk), .RN(n1702), .Q(
DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(n794), .CK(clk), .RN(n1700), .Q(
DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(n793), .CK(clk), .RN(n1706), .Q(
DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(n792), .CK(clk), .RN(n1706), .Q(
DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_27_ ( .D(n787), .CK(clk), .RN(n1706), .QN(n976)
);
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(n786), .CK(clk), .RN(n1706), .Q(
DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(n785), .CK(clk), .RN(n1706), .Q(
DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(n784), .CK(clk), .RN(n1706), .Q(
DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n783), .CK(clk), .RN(n1706), .Q(
OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n782), .CK(clk), .RN(n1706), .Q(
ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n781), .CK(clk), .RN(n1707), .Q(
SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n780), .CK(clk), .RN(n1703), .Q(
DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n779), .CK(clk), .RN(n1702), .Q(
DMP_SHT2_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n777), .CK(clk), .RN(n1707), .Q(
DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n776), .CK(clk), .RN(n1703), .Q(
DMP_SHT2_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n774), .CK(clk), .RN(n1702), .Q(
DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n773), .CK(clk), .RN(n1707), .Q(
DMP_SHT2_EWSW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n771), .CK(clk), .RN(n940), .Q(
DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n770), .CK(clk), .RN(n940), .Q(
DMP_SHT2_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n768), .CK(clk), .RN(n1708), .Q(
DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n767), .CK(clk), .RN(n1042), .Q(
DMP_SHT2_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n765), .CK(clk), .RN(n1700), .Q(
DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n764), .CK(clk), .RN(n1706), .Q(
DMP_SHT2_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n762), .CK(clk), .RN(n1708), .Q(
DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n761), .CK(clk), .RN(n940), .Q(
DMP_SHT2_EWSW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n759), .CK(clk), .RN(n937), .Q(
DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n758), .CK(clk), .RN(n940), .Q(
DMP_SHT2_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n756), .CK(clk), .RN(n1700), .Q(
DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n755), .CK(clk), .RN(n1705), .Q(
DMP_SHT2_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n753), .CK(clk), .RN(n1708), .Q(
DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n752), .CK(clk), .RN(n940), .Q(
DMP_SHT2_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n750), .CK(clk), .RN(n1041), .Q(
DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n749), .CK(clk), .RN(n940), .Q(
DMP_SHT2_EWSW[10]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_10_ ( .D(n748), .CK(clk), .RN(n1701), .Q(
DMP_SFG[10]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n747), .CK(clk), .RN(n1705), .Q(
DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n746), .CK(clk), .RN(n940), .Q(
DMP_SHT2_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n744), .CK(clk), .RN(n1707), .Q(
DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n743), .CK(clk), .RN(n1707), .Q(
DMP_SHT2_EWSW[12]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_12_ ( .D(n742), .CK(clk), .RN(n1707), .Q(
DMP_SFG[12]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n741), .CK(clk), .RN(n1707), .Q(
DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n740), .CK(clk), .RN(n1707), .Q(
DMP_SHT2_EWSW[13]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_13_ ( .D(n739), .CK(clk), .RN(n1707), .Q(
DMP_SFG[13]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n738), .CK(clk), .RN(n1707), .Q(
DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n737), .CK(clk), .RN(n1707), .Q(
DMP_SHT2_EWSW[14]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_14_ ( .D(n736), .CK(clk), .RN(n1707), .Q(
DMP_SFG[14]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n735), .CK(clk), .RN(n1707), .Q(
DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n734), .CK(clk), .RN(n1707), .Q(
DMP_SHT2_EWSW[15]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_15_ ( .D(n733), .CK(clk), .RN(n1042), .Q(
DMP_SFG[15]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n732), .CK(clk), .RN(n1042), .Q(
DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n731), .CK(clk), .RN(n1042), .Q(
DMP_SHT2_EWSW[16]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_16_ ( .D(n730), .CK(clk), .RN(n1042), .Q(
DMP_SFG[16]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n729), .CK(clk), .RN(n1042), .Q(
DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n728), .CK(clk), .RN(n1042), .Q(
DMP_SHT2_EWSW[17]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_17_ ( .D(n727), .CK(clk), .RN(n1042), .Q(
DMP_SFG[17]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n726), .CK(clk), .RN(n1042), .Q(
DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n725), .CK(clk), .RN(n1042), .Q(
DMP_SHT2_EWSW[18]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_18_ ( .D(n724), .CK(clk), .RN(n1042), .Q(
DMP_SFG[18]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n723), .CK(clk), .RN(n1042), .Q(
DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n722), .CK(clk), .RN(n1042), .Q(
DMP_SHT2_EWSW[19]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_19_ ( .D(n721), .CK(clk), .RN(n1708), .Q(
DMP_SFG[19]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n720), .CK(clk), .RN(n940), .Q(
DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n719), .CK(clk), .RN(n937), .Q(
DMP_SHT2_EWSW[20]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_20_ ( .D(n718), .CK(clk), .RN(n940), .Q(
DMP_SFG[20]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n717), .CK(clk), .RN(n1042), .Q(
DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n716), .CK(clk), .RN(n1700), .Q(
DMP_SHT2_EWSW[21]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_21_ ( .D(n715), .CK(clk), .RN(n940), .Q(
DMP_SFG[21]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n714), .CK(clk), .RN(n1708), .Q(
DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n713), .CK(clk), .RN(n1042), .Q(
DMP_SHT2_EWSW[22]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_22_ ( .D(n712), .CK(clk), .RN(n1708), .Q(
DMP_SFG[22]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n711), .CK(clk), .RN(n1700), .Q(
DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n710), .CK(clk), .RN(n940), .Q(
DMP_SHT2_EWSW[23]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_23_ ( .D(n709), .CK(clk), .RN(n1699), .Q(
DMP_SFG[23]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n708), .CK(clk), .RN(n1706), .Q(
DMP_exp_NRM_EW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n706), .CK(clk), .RN(n1710), .Q(
DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n705), .CK(clk), .RN(n1708), .Q(
DMP_SHT2_EWSW[24]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_24_ ( .D(n704), .CK(clk), .RN(n937), .Q(
DMP_SFG[24]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n703), .CK(clk), .RN(n940), .Q(
DMP_exp_NRM_EW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n701), .CK(clk), .RN(n1041), .Q(
DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n700), .CK(clk), .RN(n940), .Q(
DMP_SHT2_EWSW[25]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_25_ ( .D(n699), .CK(clk), .RN(n1705), .Q(
DMP_SFG[25]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n698), .CK(clk), .RN(n1708), .Q(
DMP_exp_NRM_EW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n696), .CK(clk), .RN(n1708), .Q(
DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n695), .CK(clk), .RN(n1041), .Q(
DMP_SHT2_EWSW[26]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_26_ ( .D(n694), .CK(clk), .RN(n943), .Q(
DMP_SFG[26]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n693), .CK(clk), .RN(n1042), .Q(
DMP_exp_NRM_EW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n691), .CK(clk), .RN(n941), .Q(
DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n690), .CK(clk), .RN(n937), .Q(
DMP_SHT2_EWSW[27]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_27_ ( .D(n689), .CK(clk), .RN(n937), .Q(
DMP_SFG[27]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n688), .CK(clk), .RN(n1712), .Q(
DMP_exp_NRM_EW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n686), .CK(clk), .RN(n941), .Q(
DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n685), .CK(clk), .RN(n1041), .Q(
DMP_SHT2_EWSW[28]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_28_ ( .D(n684), .CK(clk), .RN(n943), .Q(
DMP_SFG[28]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n683), .CK(clk), .RN(n1042), .Q(
DMP_exp_NRM_EW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n681), .CK(clk), .RN(n942), .Q(
DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n680), .CK(clk), .RN(n937), .Q(
DMP_SHT2_EWSW[29]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_29_ ( .D(n679), .CK(clk), .RN(n1709), .Q(
DMP_SFG[29]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n678), .CK(clk), .RN(n1709), .Q(
DMP_exp_NRM_EW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n676), .CK(clk), .RN(n1709), .Q(
DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n675), .CK(clk), .RN(n1709), .Q(
DMP_SHT2_EWSW[30]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_30_ ( .D(n674), .CK(clk), .RN(n1709), .Q(
DMP_SFG[30]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n673), .CK(clk), .RN(n1709), .Q(
DMP_exp_NRM_EW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(n671), .CK(clk), .RN(n1709), .Q(
DmP_EXP_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n670), .CK(clk), .RN(n1709), .QN(
n977) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(n669), .CK(clk), .RN(n1709), .Q(
DmP_EXP_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n668), .CK(clk), .RN(n1709), .QN(
n978) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(n667), .CK(clk), .RN(n1709), .Q(
DmP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(n665), .CK(clk), .RN(n1709), .Q(
DmP_EXP_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n664), .CK(clk), .RN(n1711), .QN(
n984) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(n663), .CK(clk), .RN(n1710), .Q(
DmP_EXP_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n662), .CK(clk), .RN(n942), .QN(
n951) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(n661), .CK(clk), .RN(n944), .Q(
DmP_EXP_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n660), .CK(clk), .RN(n1040), .QN(
n979) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(n659), .CK(clk), .RN(n942), .Q(
DmP_EXP_EWSW[6]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n658), .CK(clk), .RN(n1711), .QN(
n982) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(n657), .CK(clk), .RN(n942), .Q(
DmP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(n655), .CK(clk), .RN(n1710), .Q(
DmP_EXP_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n654), .CK(clk), .RN(n944), .QN(
n947) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(n653), .CK(clk), .RN(n942), .Q(
DmP_EXP_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n652), .CK(clk), .RN(n1710), .QN(
n970) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(n651), .CK(clk), .RN(n1711), .Q(
DmP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(n649), .CK(clk), .RN(n944), .Q(
DmP_EXP_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n648), .CK(clk), .RN(n1041),
.QN(n983) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(n647), .CK(clk), .RN(n944), .Q(
DmP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(n645), .CK(clk), .RN(n944), .Q(
DmP_EXP_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n644), .CK(clk), .RN(n1040),
.QN(n980) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(n643), .CK(clk), .RN(n1042), .Q(
DmP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(n641), .CK(clk), .RN(n937), .Q(
DmP_EXP_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n640), .CK(clk), .RN(n937), .QN(
n948) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(n639), .CK(clk), .RN(n1712), .Q(
DmP_EXP_EWSW[16]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n638), .CK(clk), .RN(n941), .QN(
n972) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(n637), .CK(clk), .RN(n1041), .Q(
DmP_EXP_EWSW[17]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n636), .CK(clk), .RN(n943), .QN(
n950) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(n635), .CK(clk), .RN(n942), .Q(
DmP_EXP_EWSW[18]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n634), .CK(clk), .RN(n937), .QN(
n968) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(n633), .CK(clk), .RN(n937), .Q(
DmP_EXP_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n632), .CK(clk), .RN(n1712),
.QN(n949) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(n631), .CK(clk), .RN(n941), .Q(
DmP_EXP_EWSW[20]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n630), .CK(clk), .RN(n1041),
.QN(n981) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(n629), .CK(clk), .RN(n942), .Q(
DmP_EXP_EWSW[21]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n628), .CK(clk), .RN(n937), .QN(
n969) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(n627), .CK(clk), .RN(n937), .Q(
DmP_EXP_EWSW[22]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n626), .CK(clk), .RN(n1712),
.QN(n946) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n620), .CK(clk), .RN(n943), .Q(
underflow_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n619), .CK(clk), .RN(n1709), .Q(
overflow_flag) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n618), .CK(clk), .RN(n937), .Q(
ZERO_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n617), .CK(clk), .RN(n1712), .Q(
ZERO_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n616), .CK(clk), .RN(n941), .Q(
ZERO_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n615), .CK(clk), .RN(n1042), .Q(
ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n614), .CK(clk), .RN(n1711), .Q(
ZERO_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n613), .CK(clk), .RN(n942), .Q(
zero_flag) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n612), .CK(clk), .RN(n1710), .Q(
OP_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n611), .CK(clk), .RN(n944), .Q(
OP_FLAG_SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n609), .CK(clk), .RN(n943), .Q(
SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n608), .CK(clk), .RN(n944), .Q(
SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n607), .CK(clk), .RN(n1711), .Q(
SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n606), .CK(clk), .RN(n942), .Q(
SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n605), .CK(clk), .RN(n1710), .Q(
SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n604), .CK(clk), .RN(n1703), .Q(
final_result_ieee[31]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n587), .CK(clk), .RN(n1714), .Q(
LZD_output_NRM2_EW[4]), .QN(n1661) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n584), .CK(clk), .RN(n1042), .Q(
LZD_output_NRM2_EW[2]), .QN(n1658) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n579), .CK(clk), .RN(n1708), .Q(
LZD_output_NRM2_EW[0]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n577), .CK(clk), .RN(n943), .QN(
n963) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n576), .CK(clk), .RN(n937), .Q(
DmP_mant_SFG_SWR[2]), .QN(n1025) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n573), .CK(clk), .RN(n1706), .Q(
LZD_output_NRM2_EW[3]), .QN(n1662) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n572), .CK(clk), .RN(n940), .Q(
LZD_output_NRM2_EW[1]), .QN(n1657) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n571), .CK(clk), .RN(n1712), .Q(
DmP_mant_SFG_SWR[3]), .QN(n1026) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n566), .CK(clk), .RN(n941), .Q(
DmP_mant_SFG_SWR[6]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n565), .CK(clk), .RN(n1041), .Q(
final_result_ieee[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n564), .CK(clk), .RN(n943), .Q(
final_result_ieee[17]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n563), .CK(clk), .RN(n1042), .Q(
DmP_mant_SFG_SWR[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n562), .CK(clk), .RN(n944), .Q(
final_result_ieee[2]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n561), .CK(clk), .RN(n1040), .Q(
final_result_ieee[19]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n560), .CK(clk), .RN(n942), .Q(
final_result_ieee[10]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n559), .CK(clk), .RN(n1711), .Q(
final_result_ieee[11]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n557), .CK(clk), .RN(n1710), .Q(
final_result_ieee[7]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n556), .CK(clk), .RN(n944), .Q(
final_result_ieee[14]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n555), .CK(clk), .RN(n1041), .Q(
DmP_mant_SFG_SWR[5]), .QN(n1037) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n554), .CK(clk), .RN(n942), .Q(
final_result_ieee[3]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n553), .CK(clk), .RN(n1711), .Q(
final_result_ieee[18]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n552), .CK(clk), .RN(n942), .Q(
final_result_ieee[9]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n551), .CK(clk), .RN(n1710), .Q(
final_result_ieee[12]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n549), .CK(clk), .RN(n944), .Q(
final_result_ieee[8]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n548), .CK(clk), .RN(n1041), .Q(
final_result_ieee[13]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n547), .CK(clk), .RN(n942), .QN(
n953) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n546), .CK(clk), .RN(n1711), .Q(
final_result_ieee[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n545), .CK(clk), .RN(n1710), .Q(
final_result_ieee[16]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n544), .CK(clk), .RN(n942), .Q(
final_result_ieee[1]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n543), .CK(clk), .RN(n944), .Q(
final_result_ieee[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n542), .CK(clk), .RN(n1040), .Q(
final_result_ieee[6]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n541), .CK(clk), .RN(n942), .Q(
final_result_ieee[15]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n540), .CK(clk), .RN(n1710), .Q(
final_result_ieee[20]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n539), .CK(clk), .RN(n942), .Q(
final_result_ieee[21]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n538), .CK(clk), .RN(n1714), .Q(
final_result_ieee[22]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n537), .CK(clk), .RN(n1714), .QN(
n956) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n536), .CK(clk), .RN(n1714), .QN(
n955) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n535), .CK(clk), .RN(n1714), .QN(
n959) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n534), .CK(clk), .RN(n1714), .QN(
n960) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n531), .CK(clk), .RN(n1714), .Q(
DmP_mant_SFG_SWR[18]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n530), .CK(clk), .RN(n1714), .Q(
DmP_mant_SFG_SWR[19]) );
CMPR32X2TS intadd_46_U14 ( .A(intadd_46_A_0_), .B(intadd_46_B_0_), .C(
intadd_46_CI), .CO(intadd_46_n13), .S(intadd_46_SUM_0_) );
CMPR32X2TS intadd_46_U12 ( .A(intadd_46_A_2_), .B(intadd_46_B_2_), .C(
intadd_46_n12), .CO(intadd_46_n11), .S(intadd_46_SUM_2_) );
CMPR32X2TS intadd_46_U11 ( .A(intadd_46_A_3_), .B(intadd_46_B_3_), .C(
intadd_46_n11), .CO(intadd_46_n10), .S(intadd_46_SUM_3_) );
CMPR32X2TS intadd_46_U10 ( .A(intadd_46_A_4_), .B(intadd_46_B_4_), .C(
intadd_46_n10), .CO(intadd_46_n9), .S(intadd_46_SUM_4_) );
CMPR32X2TS intadd_46_U9 ( .A(intadd_46_A_5_), .B(intadd_46_B_5_), .C(
intadd_46_n9), .CO(intadd_46_n8), .S(intadd_46_SUM_5_) );
CMPR32X2TS intadd_46_U8 ( .A(intadd_46_A_6_), .B(intadd_46_B_6_), .C(
intadd_46_n8), .CO(intadd_46_n7), .S(intadd_46_SUM_6_) );
CMPR32X2TS intadd_46_U7 ( .A(intadd_46_A_7_), .B(intadd_46_B_7_), .C(
intadd_46_n7), .CO(intadd_46_n6), .S(intadd_46_SUM_7_) );
CMPR32X2TS intadd_46_U6 ( .A(intadd_46_A_8_), .B(intadd_46_B_8_), .C(
intadd_46_n6), .CO(intadd_46_n5), .S(intadd_46_SUM_8_) );
CMPR32X2TS intadd_46_U5 ( .A(intadd_46_A_9_), .B(intadd_46_B_9_), .C(
intadd_46_n5), .CO(intadd_46_n4), .S(intadd_46_SUM_9_) );
CMPR32X2TS intadd_46_U4 ( .A(intadd_46_A_10_), .B(intadd_46_B_10_), .C(
intadd_46_n4), .CO(intadd_46_n3), .S(intadd_46_SUM_10_) );
CMPR32X2TS intadd_46_U3 ( .A(intadd_46_A_11_), .B(intadd_46_B_11_), .C(
intadd_46_n3), .CO(intadd_46_n2), .S(intadd_46_SUM_11_) );
CMPR32X2TS intadd_46_U2 ( .A(intadd_46_A_12_), .B(intadd_46_B_12_), .C(
intadd_46_n2), .CO(intadd_46_n1), .S(intadd_46_SUM_12_) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n846), .CK(clk), .RN(n1704), .Q(
Data_array_SWR[13]), .QN(n1690) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n844), .CK(clk), .RN(n944), .Q(
Data_array_SWR[11]), .QN(n1689) );
DFFRX2TS inst_ShiftRegister_Q_reg_5_ ( .D(n929), .CK(clk), .RN(n1702), .Q(
Shift_reg_FLAGS_7_5), .QN(n1645) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n854), .CK(clk), .RN(n1699), .Q(
Data_array_SWR[19]), .QN(n1684) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n870), .CK(clk), .RN(n941), .Q(
intDY_EWSW[19]), .QN(n1680) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n866), .CK(clk), .RN(n944), .Q(
intDY_EWSW[23]), .QN(n1678) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n895), .CK(clk), .RN(n1705),
.QN(n1677) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n881), .CK(clk), .RN(n942), .QN(
n1676) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n888), .CK(clk), .RN(n1700),
.QN(n1675) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n872), .CK(clk), .RN(n943),
.QN(n1674) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n874), .CK(clk), .RN(n1704),
.QN(n1673) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n886), .CK(clk), .RN(n943), .QN(
n1672) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n889), .CK(clk), .RN(n1702), .Q(
intDY_EWSW[0]), .QN(n1671) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n864), .CK(clk), .RN(n1040),
.QN(n1670) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n882), .CK(clk), .RN(n944), .Q(
intDY_EWSW[7]), .QN(n1668) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n862), .CK(clk), .RN(n1705),
.Q(intDY_EWSW[27]), .QN(n1667) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n877), .CK(clk), .RN(n1704),
.Q(intDY_EWSW[12]), .QN(n1665) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n885), .CK(clk), .RN(n1040), .Q(
intDY_EWSW[4]), .QN(n1664) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n887), .CK(clk), .RN(n1701), .Q(
intDY_EWSW[2]), .QN(n1663) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n828), .CK(clk), .RN(n1700), .Q(
shift_value_SHT2_EWR[4]), .QN(n1660) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n1701), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n1659) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n907), .CK(clk), .RN(n1705),
.Q(intDX_EWSW[16]), .QN(n1655) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n917), .CK(clk), .RN(n1701), .Q(
intDX_EWSW[6]), .QN(n1652) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n918), .CK(clk), .RN(n1705), .Q(
intDX_EWSW[5]), .QN(n1651) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n568), .CK(clk), .RN(n937), .Q(
Raw_mant_NRM_SWR[6]), .QN(n1650) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n884), .CK(clk), .RN(n941), .Q(
intDY_EWSW[5]), .QN(n1639) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n916), .CK(clk), .RN(n1703), .Q(
intDX_EWSW[7]), .QN(n1637) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n919), .CK(clk), .RN(n1699), .Q(
intDX_EWSW[4]), .QN(n1635) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n599), .CK(clk), .RN(n1714), .Q(
Raw_mant_NRM_SWR[16]), .QN(n1631) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n601), .CK(clk), .RN(n1708), .Q(
Raw_mant_NRM_SWR[14]), .QN(n1625) );
DFFRX2TS inst_ShiftRegister_Q_reg_6_ ( .D(n930), .CK(clk), .RN(n1701), .Q(
Shift_reg_FLAGS_7_6), .QN(n1629) );
DFFSX4TS inst_ShiftRegister_Q_reg_0_ ( .D(n1024), .CK(clk), .SN(n1705), .Q(
n1715), .QN(Shift_reg_FLAGS_7[0]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n672), .CK(clk), .RN(n1040), .Q(
DMP_exp_NRM2_EW[7]), .QN(n1685) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n677), .CK(clk), .RN(n1711), .Q(
DMP_exp_NRM2_EW[6]), .QN(n1681) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n682), .CK(clk), .RN(n1708), .Q(
DMP_exp_NRM2_EW[5]), .QN(n1669) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n707), .CK(clk), .RN(n1712), .Q(
DMP_exp_NRM2_EW[0]), .QN(n1654) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n575), .CK(clk), .RN(n1042), .Q(
Raw_mant_NRM_SWR[2]), .QN(n1648) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n574), .CK(clk), .RN(n937), .Q(
Raw_mant_NRM_SWR[3]), .QN(n1683) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n570), .CK(clk), .RN(n941), .Q(
Raw_mant_NRM_SWR[4]), .QN(n1634) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n567), .CK(clk), .RN(n1041), .Q(
Raw_mant_NRM_SWR[7]), .QN(n1633) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n581), .CK(clk), .RN(n937), .Q(
Raw_mant_NRM_SWR[9]), .QN(n1649) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n580), .CK(clk), .RN(n1712), .Q(
Raw_mant_NRM_SWR[10]), .QN(n1647) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n603), .CK(clk), .RN(n940), .Q(
Raw_mant_NRM_SWR[12]), .QN(n1626) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n588), .CK(clk), .RN(n944), .Q(
Raw_mant_NRM_SWR[11]), .QN(n1646) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_26_ ( .D(n788), .CK(clk), .RN(n1706), .Q(
DMP_EXP_EWSW[26]), .QN(n1688) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_24_ ( .D(n790), .CK(clk), .RN(n1706), .Q(
DMP_EXP_EWSW[24]), .QN(n1630) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_25_ ( .D(n789), .CK(clk), .RN(n1706), .Q(
DMP_EXP_EWSW[25]), .QN(n1682) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_26_ ( .D(n622), .CK(clk), .RN(n943), .Q(
DmP_EXP_EWSW[26]), .QN(n1686) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_25_ ( .D(n623), .CK(clk), .RN(n1042), .Q(
DmP_EXP_EWSW[25]), .QN(n1691) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_24_ ( .D(n624), .CK(clk), .RN(n941), .Q(
DmP_EXP_EWSW[24]), .QN(n1642) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n598), .CK(clk), .RN(n937), .Q(
Raw_mant_NRM_SWR[17]), .QN(n1628) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n931), .CK(clk), .RN(
n1699), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n1640) );
DFFRX1TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n830), .CK(clk), .RN(n1699), .Q(
shift_value_SHT2_EWR[3]), .QN(n1653) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n594), .CK(clk), .RN(n940), .Q(
Raw_mant_NRM_SWR[21]), .QN(n1627) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n593), .CK(clk), .RN(n940), .Q(
Raw_mant_NRM_SWR[22]), .QN(n1624) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n893), .CK(clk), .RN(n1701),
.Q(intDX_EWSW[30]), .QN(n1641) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n894), .CK(clk), .RN(n1703),
.Q(intDX_EWSW[29]), .QN(n1679) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n897), .CK(clk), .RN(n1705),
.Q(intDX_EWSW[26]), .QN(n1644) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n898), .CK(clk), .RN(n1701),
.Q(intDX_EWSW[25]), .QN(n1643) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n899), .CK(clk), .RN(n1703),
.Q(intDX_EWSW[24]), .QN(n1687) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n859), .CK(clk), .RN(n1701),
.Q(intDY_EWSW[30]), .QN(n1656) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n860), .CK(clk), .RN(n1703),
.Q(intDY_EWSW[29]), .QN(n1638) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n591), .CK(clk), .RN(n937), .Q(
Raw_mant_NRM_SWR[24]), .QN(n1623) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n590), .CK(clk), .RN(n943), .Q(
Raw_mant_NRM_SWR[25]), .QN(n1632) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n842), .CK(clk), .RN(n942), .Q(
Data_array_SWR[10]), .QN(n1692) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n852), .CK(clk), .RN(n941), .Q(
Data_array_SWR[18]), .QN(n1693) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n920), .CK(clk), .RN(n1700), .Q(
intDX_EWSW[3]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n910), .CK(clk), .RN(n1702),
.Q(intDX_EWSW[13]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n900), .CK(clk), .RN(n1700),
.Q(intDX_EWSW[23]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n908), .CK(clk), .RN(n1702),
.Q(intDX_EWSW[15]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n902), .CK(clk), .RN(n1699),
.Q(intDX_EWSW[21]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n855), .CK(clk), .RN(n941), .Q(
Data_array_SWR[20]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n856), .CK(clk), .RN(n1702), .Q(
Data_array_SWR[21]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n595), .CK(clk), .RN(n1709), .Q(
Raw_mant_NRM_SWR[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n906), .CK(clk), .RN(n1701),
.Q(intDX_EWSW[17]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_3_ ( .D(n769), .CK(clk), .RN(n944), .Q(
DMP_SFG[3]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n857), .CK(clk), .RN(n1699), .Q(
Data_array_SWR[22]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n912), .CK(clk), .RN(n1701),
.Q(intDX_EWSW[11]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n915), .CK(clk), .RN(n1703), .Q(
intDX_EWSW[8]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n896), .CK(clk), .RN(n1703),
.Q(intDX_EWSW[27]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n914), .CK(clk), .RN(n1701), .Q(
intDX_EWSW[9]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n847), .CK(clk), .RN(n944), .Q(
Data_array_SWR[14]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n845), .CK(clk), .RN(n1040), .Q(
Data_array_SWR[12]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n596), .CK(clk), .RN(n940), .Q(
Raw_mant_NRM_SWR[19]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n923), .CK(clk), .RN(n1703), .Q(
intDX_EWSW[0]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n905), .CK(clk), .RN(n1703),
.Q(intDX_EWSW[18]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n600), .CK(clk), .RN(n1708), .Q(
Raw_mant_NRM_SWR[15]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n582), .CK(clk), .RN(n940), .Q(
Raw_mant_NRM_SWR[8]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n602), .CK(clk), .RN(n1706), .Q(
Raw_mant_NRM_SWR[13]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n585), .CK(clk), .RN(n937), .Q(
Raw_mant_NRM_SWR[1]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n569), .CK(clk), .RN(n1712), .Q(
Raw_mant_NRM_SWR[5]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n932), .CK(clk), .RN(
n1705), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n831), .CK(clk), .RN(n1701), .Q(
shift_value_SHT2_EWR[2]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n840), .CK(clk), .RN(n943), .Q(
Data_array_SWR[8]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n850), .CK(clk), .RN(n1040), .Q(
Data_array_SWR[16]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n848), .CK(clk), .RN(n941), .Q(
Data_array_SWR[15]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n597), .CK(clk), .RN(n1708), .Q(
Raw_mant_NRM_SWR[18]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n836), .CK(clk), .RN(n1040), .Q(
Data_array_SWR[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n837), .CK(clk), .RN(n943), .Q(
Data_array_SWR[5]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n838), .CK(clk), .RN(n1704), .Q(
Data_array_SWR[6]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n839), .CK(clk), .RN(n944), .Q(
Data_array_SWR[7]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n592), .CK(clk), .RN(n1701), .Q(
Raw_mant_NRM_SWR[23]), .QN(n952) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_5_ ( .D(n763), .CK(clk), .RN(n940), .Q(
DMP_SFG[5]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_1_ ( .D(n775), .CK(clk), .RN(n942), .Q(
DMP_SFG[1]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_6_ ( .D(n760), .CK(clk), .RN(n940), .Q(
DMP_SFG[6]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_7_ ( .D(n757), .CK(clk), .RN(n1712), .Q(
DMP_SFG[7]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n892), .CK(clk), .RN(n1700),
.Q(intDX_EWSW[31]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_9_ ( .D(n751), .CK(clk), .RN(n1705), .Q(
DMP_SFG[9]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n883), .CK(clk), .RN(n1704), .Q(
intDY_EWSW[6]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n656), .CK(clk), .RN(n944), .Q(
DmP_mant_SHT1_SW[7]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n646), .CK(clk), .RN(n1710), .Q(
DmP_mant_SHT1_SW[12]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n650), .CK(clk), .RN(n942), .Q(
DmP_mant_SHT1_SW[10]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n642), .CK(clk), .RN(n1711), .Q(
DmP_mant_SHT1_SW[14]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n666), .CK(clk), .RN(n1709), .Q(
DmP_mant_SHT1_SW[2]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_4_ ( .D(n766), .CK(clk), .RN(n940), .Q(
DMP_SFG[4]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_2_ ( .D(n772), .CK(clk), .RN(n943), .Q(
DMP_SFG[2]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n550), .CK(clk), .RN(n1042), .Q(
DmP_mant_SFG_SWR[10]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n589), .CK(clk), .RN(n1041), .Q(
DmP_mant_SFG_SWR[11]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_8_ ( .D(n754), .CK(clk), .RN(n943), .Q(
DMP_SFG[8]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_0_ ( .D(n778), .CK(clk), .RN(n941), .Q(
DMP_SFG[0]) );
DFFRX1TS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n891), .CK(clk), .RN(n1702), .Q(
intAS) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n880), .CK(clk), .RN(n941), .Q(
intDY_EWSW[9]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n879), .CK(clk), .RN(n944), .Q(
intDY_EWSW[10]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n875), .CK(clk), .RN(n943), .Q(
intDY_EWSW[14]), .QN(n1694) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n876), .CK(clk), .RN(n942), .Q(
intDY_EWSW[13]), .QN(n1695) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n878), .CK(clk), .RN(n1040),
.QN(n1696) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_23_ ( .D(n791), .CK(clk), .RN(n1706), .Q(
DMP_EXP_EWSW[23]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n692), .CK(clk), .RN(n1040), .Q(
DMP_exp_NRM2_EW[3]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n697), .CK(clk), .RN(n940), .Q(
DMP_exp_NRM2_EW[2]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n702), .CK(clk), .RN(n940), .Q(
DMP_exp_NRM2_EW[1]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_11_ ( .D(n745), .CK(clk), .RN(n1707), .QN(n1029) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n911), .CK(clk), .RN(n1705),
.Q(intDX_EWSW[12]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n903), .CK(clk), .RN(n1705),
.Q(intDX_EWSW[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n909), .CK(clk), .RN(n1700),
.Q(intDX_EWSW[14]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n922), .CK(clk), .RN(n1702), .Q(
intDX_EWSW[1]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n921), .CK(clk), .RN(n1700), .Q(
intDX_EWSW[2]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n868), .CK(clk), .RN(n1040),
.Q(intDY_EWSW[21]), .QN(n1718) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n913), .CK(clk), .RN(n1702),
.Q(intDX_EWSW[10]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n861), .CK(clk), .RN(n1703),
.Q(intDY_EWSW[28]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n867), .CK(clk), .RN(n942), .Q(
intDY_EWSW[22]), .QN(n1697) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n871), .CK(clk), .RN(n941),
.QN(n1698) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n841), .CK(clk), .RN(n1704), .Q(
Data_array_SWR[9]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n851), .CK(clk), .RN(n942), .Q(
Data_array_SWR[17]) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n863), .CK(clk), .RN(n1704),
.Q(n957) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n869), .CK(clk), .RN(n944), .Q(
intDY_EWSW[20]), .QN(n1666) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n873), .CK(clk), .RN(n1040),
.Q(intDY_EWSW[16]) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n827), .CK(clk), .RN(n1040),
.Q(Shift_amount_SHT1_EWR[0]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n578), .CK(clk), .RN(n941), .Q(
DmP_mant_SFG_SWR[0]), .QN(n1035) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n583), .CK(clk), .RN(n1042), .Q(
DmP_mant_SFG_SWR[8]), .QN(n1032) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n586), .CK(clk), .RN(n1041), .Q(
DmP_mant_SFG_SWR[1]), .QN(n974) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n524), .CK(clk), .RN(n1714), .Q(
DmP_mant_SFG_SWR[25]), .QN(n1034) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n525), .CK(clk), .RN(n941), .Q(
DmP_mant_SFG_SWR[24]), .QN(n975) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n526), .CK(clk), .RN(n1714), .Q(
DmP_mant_SFG_SWR[23]), .QN(n967) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n558), .CK(clk), .RN(n942), .Q(
DmP_mant_SFG_SWR[9]), .QN(n1027) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_23_ ( .D(n625), .CK(clk), .RN(n941), .Q(
DmP_EXP_EWSW[23]), .QN(n1033) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n687), .CK(clk), .RN(n1708), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n858), .CK(clk), .RN(n1701),
.Q(intDY_EWSW[31]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n832), .CK(clk), .RN(n1703), .Q(
Data_array_SWR[0]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n835), .CK(clk), .RN(n944), .Q(
Data_array_SWR[3]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n834), .CK(clk), .RN(n1040), .Q(
Data_array_SWR[2]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n833), .CK(clk), .RN(n1040), .Q(
Data_array_SWR[1]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_27_ ( .D(n621), .CK(clk), .RN(n1041), .Q(
DmP_EXP_EWSW[27]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n533), .CK(clk), .RN(n1714), .Q(
DmP_mant_SFG_SWR[16]), .QN(n1030) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n532), .CK(clk), .RN(n1714), .Q(
DmP_mant_SFG_SWR[17]), .QN(n1031) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n529), .CK(clk), .RN(n1714), .Q(
DmP_mant_SFG_SWR[20]), .QN(n1038) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n528), .CK(clk), .RN(n1714), .Q(
DmP_mant_SFG_SWR[21]), .QN(n1036) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n527), .CK(clk), .RN(n1714), .Q(
DmP_mant_SFG_SWR[22]), .QN(n1028) );
ADDFX1TS DP_OP_15J41_125_2314_U5 ( .A(n1661), .B(DMP_exp_NRM2_EW[4]), .CI(
DP_OP_15J41_125_2314_n5), .CO(DP_OP_15J41_125_2314_n4), .S(
exp_rslt_NRM2_EW1[4]) );
DFFRX4TS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n610), .CK(clk), .RN(n1040), .Q(
OP_FLAG_SFG), .QN(n1636) );
CMPR32X2TS DP_OP_15J41_125_2314_U8 ( .A(n1657), .B(DMP_exp_NRM2_EW[1]), .C(
DP_OP_15J41_125_2314_n8), .CO(DP_OP_15J41_125_2314_n7), .S(
exp_rslt_NRM2_EW1[1]) );
CMPR32X2TS DP_OP_15J41_125_2314_U7 ( .A(n1658), .B(DMP_exp_NRM2_EW[2]), .C(
DP_OP_15J41_125_2314_n7), .CO(DP_OP_15J41_125_2314_n6), .S(
exp_rslt_NRM2_EW1[2]) );
CMPR32X2TS intadd_46_U13 ( .A(n1029), .B(intadd_46_B_1_), .C(intadd_46_n13),
.CO(intadd_46_n12), .S(intadd_46_SUM_1_) );
CMPR32X2TS DP_OP_15J41_125_2314_U6 ( .A(n1662), .B(DMP_exp_NRM2_EW[3]), .C(
DP_OP_15J41_125_2314_n6), .CO(DP_OP_15J41_125_2314_n5), .S(
exp_rslt_NRM2_EW1[3]) );
DFFRX4TS inst_ShiftRegister_Q_reg_1_ ( .D(n925), .CK(clk), .RN(n1699), .Q(
Shift_reg_FLAGS_7[1]), .QN(n933) );
DFFRX4TS inst_ShiftRegister_Q_reg_4_ ( .D(n928), .CK(clk), .RN(n1700), .Q(
busy), .QN(n934) );
DFFRX4TS inst_ShiftRegister_Q_reg_2_ ( .D(n926), .CK(clk), .RN(n1700), .Q(
n973), .QN(n1716) );
BUFX6TS U940 ( .A(n1040), .Y(n1041) );
NAND2X6TS U941 ( .A(beg_OP), .B(n1422), .Y(n1423) );
CMPR32X2TS U942 ( .A(DMP_SFG[7]), .B(n1522), .C(n1521), .CO(n1524), .S(n1523) );
CMPR32X2TS U943 ( .A(DMP_SFG[6]), .B(n1519), .C(n1518), .CO(n1522), .S(n1520) );
INVX4TS U944 ( .A(n1277), .Y(n935) );
INVX6TS U945 ( .A(n1455), .Y(n936) );
NAND2X6TS U946 ( .A(n996), .B(n1715), .Y(n1466) );
CLKBUFX2TS U947 ( .A(n1666), .Y(n1015) );
BUFX6TS U948 ( .A(n1041), .Y(n937) );
NOR2XLTS U949 ( .A(n1353), .B(n1452), .Y(n1333) );
CLKINVX6TS U950 ( .A(n1461), .Y(n1327) );
INVX6TS U951 ( .A(n1441), .Y(n938) );
AOI31XLTS U952 ( .A0(n1321), .A1(Raw_mant_NRM_SWR[8]), .A2(n1649), .B0(n1320), .Y(n1322) );
AND2X4TS U953 ( .A(Shift_reg_FLAGS_7_6), .B(n1240), .Y(n1277) );
BUFX4TS U954 ( .A(n1243), .Y(n939) );
OR2X4TS U955 ( .A(Shift_reg_FLAGS_7[1]), .B(n1480), .Y(n1455) );
NOR2X6TS U956 ( .A(n1591), .B(n1509), .Y(n1064) );
AND2X6TS U957 ( .A(Shift_amount_SHT1_EWR[0]), .B(n933), .Y(n1449) );
NOR2X6TS U958 ( .A(shift_value_SHT2_EWR[4]), .B(n1105), .Y(n1062) );
BUFX6TS U959 ( .A(n1041), .Y(n1042) );
BUFX6TS U960 ( .A(n1711), .Y(n940) );
BUFX6TS U961 ( .A(n937), .Y(n941) );
BUFX6TS U962 ( .A(n937), .Y(n942) );
BUFX6TS U963 ( .A(n1041), .Y(n943) );
CLKBUFX2TS U964 ( .A(n1037), .Y(n987) );
BUFX6TS U965 ( .A(n1041), .Y(n944) );
INVX6TS U966 ( .A(rst), .Y(n1040) );
NAND2BXLTS U967 ( .AN(intDX_EWSW[2]), .B(intDY_EWSW[2]), .Y(n1188) );
NAND2BXLTS U968 ( .AN(n1021), .B(intDY_EWSW[19]), .Y(n1222) );
NAND2BXLTS U969 ( .AN(intDX_EWSW[27]), .B(intDY_EWSW[27]), .Y(n1175) );
NAND2BXLTS U970 ( .AN(intDX_EWSW[13]), .B(intDY_EWSW[13]), .Y(n1197) );
NAND2BXLTS U971 ( .AN(intDX_EWSW[21]), .B(intDY_EWSW[21]), .Y(n1216) );
AOI222X4TS U972 ( .A0(n1018), .A1(n1139), .B0(n1019), .B1(n1138), .C0(
Data_array_SWR[22]), .C1(n1137), .Y(n1512) );
AOI222X1TS U973 ( .A0(n1554), .A1(n1483), .B0(n1554), .B1(DMP_SFG[3]), .C0(
n1483), .C1(DMP_SFG[3]), .Y(n1487) );
AOI222X1TS U974 ( .A0(n1518), .A1(DMP_SFG[6]), .B0(n1518), .B1(n1500), .C0(
DMP_SFG[6]), .C1(n1500), .Y(n1488) );
AOI222X4TS U975 ( .A0(Data_array_SWR[19]), .A1(n1542), .B0(
Data_array_SWR[13]), .B1(n1062), .C0(Data_array_SWR[16]), .C1(n1541),
.Y(n1068) );
AOI222X4TS U976 ( .A0(Data_array_SWR[20]), .A1(n1542), .B0(
Data_array_SWR[17]), .B1(n1541), .C0(Data_array_SWR[14]), .C1(n1062),
.Y(n1497) );
AOI222X4TS U977 ( .A0(n1018), .A1(n1541), .B0(n1019), .B1(n1062), .C0(
Data_array_SWR[22]), .C1(n1542), .Y(n1575) );
AOI221X1TS U978 ( .A0(n1015), .A1(intDX_EWSW[20]), .B0(intDX_EWSW[21]), .B1(
n1718), .C0(n1079), .Y(n1082) );
AOI222X1TS U979 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n938), .B0(n1450), .B1(
DmP_mant_SHT1_SW[7]), .C0(n1449), .C1(n1007), .Y(n1393) );
AOI222X1TS U980 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n938), .B0(n1450), .B1(n994), .C0(n1449), .C1(n998), .Y(n1397) );
AOI222X1TS U981 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n938), .B0(n1450), .B1(
DmP_mant_SHT1_SW[2]), .C0(n1449), .C1(n994), .Y(n1401) );
AOI222X1TS U982 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n938), .B0(n1450), .B1(n993),
.C0(n1449), .C1(n992), .Y(n1371) );
OAI21X2TS U983 ( .A0(n1550), .A1(n1549), .B0(n1548), .Y(n1553) );
AOI222X1TS U984 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n938), .B0(n1450), .B1(
n1005), .C0(n1449), .C1(DmP_mant_SHT1_SW[14]), .Y(n1360) );
AO22XLTS U985 ( .A0(OP_FLAG_SFG), .A1(DmP_mant_SFG_SWR[3]), .B0(n1514), .B1(
n1026), .Y(n961) );
AOI222X1TS U986 ( .A0(n1517), .A1(n1618), .B0(Data_array_SWR[8]), .B1(n1064),
.C0(n1516), .C1(n1140), .Y(n1606) );
AOI222X1TS U987 ( .A0(n1517), .A1(n1591), .B0(n1619), .B1(Data_array_SWR[8]),
.C0(n1516), .C1(n1589), .Y(n1598) );
INVX2TS U988 ( .A(n985), .Y(n1594) );
AOI222X1TS U989 ( .A0(n1579), .A1(n1618), .B0(Data_array_SWR[9]), .B1(n1064),
.C0(n1578), .C1(n1140), .Y(n1605) );
AOI222X1TS U990 ( .A0(n1579), .A1(n1591), .B0(n1619), .B1(Data_array_SWR[9]),
.C0(n1578), .C1(n1589), .Y(n1580) );
NAND2BXLTS U991 ( .AN(n1413), .B(n1113), .Y(n1116) );
AOI222X1TS U992 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n938), .B0(n1450), .B1(n1004), .C0(n1449), .C1(n993), .Y(n1363) );
AOI222X1TS U993 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n938), .B0(n1450), .B1(n992),
.C0(n1449), .C1(n1008), .Y(n1385) );
AOI222X1TS U994 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n938), .B0(n1450), .B1(n1006), .C0(n1449), .C1(n995), .Y(n1375) );
AOI222X1TS U995 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n938), .B0(n1003), .B1(n1449), .C0(n1450), .C1(n999), .Y(n1382) );
AOI222X1TS U996 ( .A0(Raw_mant_NRM_SWR[14]), .A1(n938), .B0(n1450), .B1(
n1001), .C0(n1449), .C1(DmP_mant_SHT1_SW[10]), .Y(n1390) );
AOI222X1TS U997 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n938), .B0(n1450), .B1(
n1000), .C0(n1449), .C1(DmP_mant_SHT1_SW[12]), .Y(n1386) );
AO22XLTS U998 ( .A0(n1432), .A1(Data_Y[28]), .B0(n1434), .B1(intDY_EWSW[28]),
.Y(n861) );
AO22XLTS U999 ( .A0(n1433), .A1(Data_X[10]), .B0(n1423), .B1(intDX_EWSW[10]),
.Y(n913) );
AO22XLTS U1000 ( .A0(n1435), .A1(Data_X[2]), .B0(n1423), .B1(intDX_EWSW[2]),
.Y(n921) );
AO22XLTS U1001 ( .A0(n1432), .A1(Data_X[1]), .B0(n1423), .B1(intDX_EWSW[1]),
.Y(n922) );
AO22XLTS U1002 ( .A0(n1435), .A1(Data_X[14]), .B0(n1423), .B1(intDX_EWSW[14]), .Y(n909) );
AO22XLTS U1003 ( .A0(n1432), .A1(Data_X[20]), .B0(n1434), .B1(intDX_EWSW[20]), .Y(n903) );
AO22XLTS U1004 ( .A0(n1433), .A1(Data_X[12]), .B0(n1423), .B1(intDX_EWSW[12]), .Y(n911) );
AO22XLTS U1005 ( .A0(n1622), .A1(DMP_SHT2_EWSW[0]), .B0(n1620), .B1(
DMP_SFG[0]), .Y(n778) );
AO22XLTS U1006 ( .A0(n1604), .A1(DMP_SHT2_EWSW[8]), .B0(n1466), .B1(
DMP_SFG[8]), .Y(n754) );
AO22XLTS U1007 ( .A0(n1604), .A1(n1584), .B0(n1620), .B1(
DmP_mant_SFG_SWR[11]), .Y(n589) );
AO22XLTS U1008 ( .A0(n1616), .A1(DMP_SHT2_EWSW[2]), .B0(n1466), .B1(
DMP_SFG[2]), .Y(n772) );
AO22XLTS U1009 ( .A0(n1477), .A1(DMP_SHT2_EWSW[4]), .B0(n1466), .B1(
DMP_SFG[4]), .Y(n766) );
AO22XLTS U1010 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[2]), .B0(n1645),
.B1(DmP_mant_SHT1_SW[2]), .Y(n666) );
AO22XLTS U1011 ( .A0(n1473), .A1(DmP_EXP_EWSW[10]), .B0(n1645), .B1(
DmP_mant_SHT1_SW[10]), .Y(n650) );
AO22XLTS U1012 ( .A0(n1479), .A1(DmP_EXP_EWSW[12]), .B0(n1645), .B1(
DmP_mant_SHT1_SW[12]), .Y(n646) );
AO22XLTS U1013 ( .A0(n1476), .A1(DmP_EXP_EWSW[7]), .B0(n1645), .B1(
DmP_mant_SHT1_SW[7]), .Y(n656) );
AO22XLTS U1014 ( .A0(n1604), .A1(DMP_SHT2_EWSW[9]), .B0(n1466), .B1(
DMP_SFG[9]), .Y(n751) );
AO22XLTS U1015 ( .A0(n1432), .A1(Data_X[31]), .B0(n1434), .B1(intDX_EWSW[31]), .Y(n892) );
AO22XLTS U1016 ( .A0(n1622), .A1(DMP_SHT2_EWSW[7]), .B0(n1466), .B1(
DMP_SFG[7]), .Y(n757) );
AO22XLTS U1017 ( .A0(n1622), .A1(DMP_SHT2_EWSW[1]), .B0(n1593), .B1(
DMP_SFG[1]), .Y(n775) );
AO22XLTS U1018 ( .A0(n1616), .A1(DMP_SHT2_EWSW[5]), .B0(n1466), .B1(
DMP_SFG[5]), .Y(n763) );
AOI32X1TS U1019 ( .A0(Shift_amount_SHT1_EWR[2]), .A1(n1455), .A2(n933), .B0(
shift_value_SHT2_EWR[2]), .B1(n936), .Y(n1171) );
AO22XLTS U1020 ( .A0(n973), .A1(n1520), .B0(n1563), .B1(Raw_mant_NRM_SWR[8]),
.Y(n582) );
AO22XLTS U1021 ( .A0(n1432), .A1(Data_X[18]), .B0(n1434), .B1(intDX_EWSW[18]), .Y(n905) );
AO22XLTS U1022 ( .A0(n1432), .A1(Data_X[0]), .B0(n1434), .B1(intDX_EWSW[0]),
.Y(n923) );
AO22XLTS U1023 ( .A0(n1435), .A1(Data_X[9]), .B0(n1423), .B1(intDX_EWSW[9]),
.Y(n914) );
AO22XLTS U1024 ( .A0(n1432), .A1(Data_X[27]), .B0(n1434), .B1(intDX_EWSW[27]), .Y(n896) );
AO22XLTS U1025 ( .A0(n1432), .A1(Data_X[8]), .B0(n1423), .B1(intDX_EWSW[8]),
.Y(n915) );
AO22XLTS U1026 ( .A0(n1435), .A1(Data_X[11]), .B0(n1423), .B1(intDX_EWSW[11]), .Y(n912) );
AO22XLTS U1027 ( .A0(n1622), .A1(DMP_SHT2_EWSW[3]), .B0(n1466), .B1(
DMP_SFG[3]), .Y(n769) );
AO22XLTS U1028 ( .A0(n1435), .A1(Data_X[17]), .B0(n1434), .B1(intDX_EWSW[17]), .Y(n906) );
AO22XLTS U1029 ( .A0(n1435), .A1(Data_X[15]), .B0(n1423), .B1(intDX_EWSW[15]), .Y(n908) );
AO22XLTS U1030 ( .A0(n1432), .A1(Data_X[13]), .B0(n1423), .B1(intDX_EWSW[13]), .Y(n910) );
AO22XLTS U1031 ( .A0(n1432), .A1(Data_X[3]), .B0(n1423), .B1(intDX_EWSW[3]),
.Y(n920) );
AO22XLTS U1032 ( .A0(n1473), .A1(DmP_EXP_EWSW[22]), .B0(n1475), .B1(n995),
.Y(n626) );
AO22XLTS U1033 ( .A0(n1479), .A1(DmP_EXP_EWSW[21]), .B0(n1475), .B1(n1006),
.Y(n628) );
AO22XLTS U1034 ( .A0(n1473), .A1(DmP_EXP_EWSW[17]), .B0(n1475), .B1(n992),
.Y(n636) );
AO22XLTS U1035 ( .A0(n1476), .A1(DmP_EXP_EWSW[16]), .B0(n1475), .B1(n993),
.Y(n638) );
AO22XLTS U1036 ( .A0(n1476), .A1(DmP_EXP_EWSW[11]), .B0(n1645), .B1(n1000),
.Y(n648) );
AO22XLTS U1037 ( .A0(n1473), .A1(DmP_EXP_EWSW[9]), .B0(n1645), .B1(n1001),
.Y(n652) );
AO22XLTS U1038 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[8]), .B0(n1472),
.B1(n1007), .Y(n654) );
AO22XLTS U1039 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[6]), .B0(n1645),
.B1(n1002), .Y(n658) );
AO22XLTS U1040 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[5]), .B0(n1645),
.B1(n1009), .Y(n660) );
AO22XLTS U1041 ( .A0(Shift_reg_FLAGS_7_5), .A1(DmP_EXP_EWSW[4]), .B0(n1645),
.B1(n998), .Y(n662) );
AO22XLTS U1042 ( .A0(n1479), .A1(DmP_EXP_EWSW[3]), .B0(n1645), .B1(n994),
.Y(n664) );
AO22XLTS U1043 ( .A0(n1479), .A1(DmP_EXP_EWSW[1]), .B0(n1472), .B1(n1010),
.Y(n668) );
AO22XLTS U1044 ( .A0(n1476), .A1(DmP_EXP_EWSW[0]), .B0(n1472), .B1(n1011),
.Y(n670) );
AO22XLTS U1045 ( .A0(n1432), .A1(Data_X[22]), .B0(n1434), .B1(n1022), .Y(
n901) );
AO22XLTS U1046 ( .A0(n1435), .A1(Data_X[19]), .B0(n1434), .B1(n1021), .Y(
n904) );
AOI31X1TS U1047 ( .A0(n1314), .A1(n1313), .A2(n1312), .B0(n933), .Y(n1408)
);
AOI211X1TS U1048 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n1311), .B0(n1310), .C0(
n1309), .Y(n1314) );
XOR2X1TS U1049 ( .A(n1560), .B(n1555), .Y(n1556) );
AOI222X1TS U1050 ( .A0(n1554), .A1(DMP_SFG[3]), .B0(n1554), .B1(n1553), .C0(
DMP_SFG[3]), .C1(n1553), .Y(n1560) );
OAI31XLTS U1051 ( .A0(n1276), .A1(n1275), .A2(n1469), .B0(n1274), .Y(n781)
);
NOR2BX2TS U1052 ( .AN(n1162), .B(n1161), .Y(n1319) );
NAND4XLTS U1053 ( .A(n952), .B(n1624), .C(n1632), .D(n1623), .Y(n1161) );
BUFX4TS U1054 ( .A(n1041), .Y(n1714) );
BUFX4TS U1055 ( .A(n943), .Y(n1707) );
BUFX4TS U1056 ( .A(n943), .Y(n1709) );
INVX2TS U1057 ( .A(n953), .Y(n985) );
OAI21X2TS U1058 ( .A0(n1499), .A1(n1487), .B0(n1486), .Y(n1500) );
BUFX4TS U1059 ( .A(n1712), .Y(n1706) );
BUFX4TS U1060 ( .A(n1704), .Y(n1705) );
INVX4TS U1061 ( .A(n1466), .Y(n1622) );
BUFX4TS U1062 ( .A(n1466), .Y(n1620) );
BUFX4TS U1063 ( .A(n1423), .Y(n1434) );
INVX2TS U1064 ( .A(n961), .Y(n986) );
BUFX4TS U1065 ( .A(n937), .Y(n1708) );
BUFX4TS U1066 ( .A(n944), .Y(n1700) );
BUFX4TS U1067 ( .A(n943), .Y(n1702) );
BUFX4TS U1068 ( .A(n941), .Y(n1703) );
BUFX4TS U1069 ( .A(n1040), .Y(n1701) );
NOR2X4TS U1070 ( .A(shift_value_SHT2_EWR[4]), .B(n1618), .Y(n1140) );
BUFX6TS U1071 ( .A(left_right_SHT2), .Y(n1618) );
OR2X1TS U1072 ( .A(n933), .B(n1330), .Y(n1441) );
AOI211X1TS U1073 ( .A0(n995), .A1(n933), .B0(n1449), .C0(n1437), .Y(n1443)
);
AOI22X4TS U1074 ( .A0(DmP_mant_SFG_SWR[5]), .A1(n1532), .B0(n1514), .B1(n987), .Y(n1554) );
AOI22X2TS U1075 ( .A0(n1532), .A1(DmP_mant_SFG_SWR[8]), .B0(n1032), .B1(
n1636), .Y(n1518) );
AOI22X2TS U1076 ( .A0(n1532), .A1(DmP_mant_SFG_SWR[9]), .B0(n1027), .B1(
n1636), .Y(n1521) );
BUFX4TS U1077 ( .A(OP_FLAG_SFG), .Y(n1532) );
INVX2TS U1078 ( .A(n960), .Y(n988) );
INVX2TS U1079 ( .A(n959), .Y(n989) );
INVX2TS U1080 ( .A(n955), .Y(n990) );
INVX2TS U1081 ( .A(n956), .Y(n991) );
NOR2XLTS U1082 ( .A(Shift_reg_FLAGS_7[1]), .B(Shift_amount_SHT1_EWR[0]), .Y(
n1325) );
INVX2TS U1083 ( .A(n950), .Y(n992) );
INVX2TS U1084 ( .A(n972), .Y(n993) );
INVX2TS U1085 ( .A(n984), .Y(n994) );
INVX2TS U1086 ( .A(n946), .Y(n995) );
INVX2TS U1087 ( .A(n971), .Y(n996) );
INVX2TS U1088 ( .A(n951), .Y(n998) );
INVX2TS U1089 ( .A(n949), .Y(n999) );
INVX2TS U1090 ( .A(n983), .Y(n1000) );
INVX2TS U1091 ( .A(n970), .Y(n1001) );
INVX2TS U1092 ( .A(n982), .Y(n1002) );
INVX2TS U1093 ( .A(n981), .Y(n1003) );
INVX2TS U1094 ( .A(n948), .Y(n1004) );
INVX2TS U1095 ( .A(n980), .Y(n1005) );
INVX2TS U1096 ( .A(n969), .Y(n1006) );
INVX2TS U1097 ( .A(n947), .Y(n1007) );
INVX2TS U1098 ( .A(n968), .Y(n1008) );
INVX2TS U1099 ( .A(n979), .Y(n1009) );
INVX2TS U1100 ( .A(n978), .Y(n1010) );
INVX2TS U1101 ( .A(n977), .Y(n1011) );
INVX2TS U1102 ( .A(n976), .Y(n1012) );
INVX2TS U1103 ( .A(intDY_EWSW[24]), .Y(n1013) );
INVX2TS U1104 ( .A(n1013), .Y(n1014) );
AOI211XLTS U1105 ( .A0(intDY_EWSW[16]), .A1(n1655), .B0(n1225), .C0(n1226),
.Y(n1217) );
NOR2X4TS U1106 ( .A(n1403), .B(n1415), .Y(n1588) );
OAI2BB1X2TS U1107 ( .A0N(n1124), .A1N(n1123), .B0(Shift_reg_FLAGS_7[0]), .Y(
n1415) );
CLKINVX6TS U1108 ( .A(n1467), .Y(n1478) );
CLKINVX6TS U1109 ( .A(n1467), .Y(n1472) );
BUFX6TS U1110 ( .A(n1329), .Y(n1457) );
BUFX4TS U1111 ( .A(n1063), .Y(n1619) );
BUFX4TS U1112 ( .A(n1061), .Y(n1541) );
BUFX6TS U1113 ( .A(n1325), .Y(n1450) );
BUFX6TS U1114 ( .A(n1299), .Y(n1419) );
CLKINVX6TS U1115 ( .A(n1716), .Y(n1557) );
INVX4TS U1116 ( .A(n1716), .Y(n1565) );
CLKINVX6TS U1117 ( .A(n1466), .Y(n1616) );
CLKINVX6TS U1118 ( .A(n1466), .Y(n1604) );
INVX4TS U1119 ( .A(n1466), .Y(n1477) );
INVX2TS U1120 ( .A(n957), .Y(n1016) );
INVX2TS U1121 ( .A(n963), .Y(n1017) );
INVX2TS U1122 ( .A(n945), .Y(n1018) );
INVX2TS U1123 ( .A(n966), .Y(n1019) );
INVX2TS U1124 ( .A(n965), .Y(n1020) );
AOI32X1TS U1125 ( .A0(n1698), .A1(n1222), .A2(intDX_EWSW[18]), .B0(n1021),
.B1(n1680), .Y(n1223) );
OAI21X2TS U1126 ( .A0(intDX_EWSW[18]), .A1(n1698), .B0(n1222), .Y(n1226) );
AOI221X1TS U1127 ( .A0(n1698), .A1(intDX_EWSW[18]), .B0(n1021), .B1(n1680),
.C0(n1226), .Y(n1083) );
AOI221X1TS U1128 ( .A0(n1697), .A1(n1022), .B0(intDX_EWSW[23]), .B1(n1678),
.C0(n1080), .Y(n1081) );
INVX2TS U1129 ( .A(n962), .Y(n1021) );
AOI221X1TS U1130 ( .A0(n1667), .A1(intDX_EWSW[27]), .B0(intDY_EWSW[28]),
.B1(n1677), .C0(n1072), .Y(n1076) );
AOI221X1TS U1131 ( .A0(n1427), .A1(intDX_EWSW[10]), .B0(intDX_EWSW[11]),
.B1(n1696), .C0(n1184), .Y(n1090) );
OAI2BB2XLTS U1132 ( .B0(intDY_EWSW[20]), .B1(n1219), .A0N(intDX_EWSW[21]),
.A1N(n1718), .Y(n1230) );
AOI221X1TS U1133 ( .A0(n1663), .A1(intDX_EWSW[2]), .B0(intDX_EWSW[3]), .B1(
n1672), .C0(n1093), .Y(n1098) );
AOI221X1TS U1134 ( .A0(n1675), .A1(intDX_EWSW[1]), .B0(intDX_EWSW[17]), .B1(
n1674), .C0(n1078), .Y(n1084) );
INVX2TS U1135 ( .A(n958), .Y(n1022) );
AOI221X1TS U1136 ( .A0(n1694), .A1(intDX_EWSW[14]), .B0(intDX_EWSW[15]),
.B1(n1673), .C0(n1087), .Y(n1088) );
OAI211X2TS U1137 ( .A0(intDX_EWSW[20]), .A1(n1015), .B0(n1231), .C0(n1216),
.Y(n1225) );
OAI211X2TS U1138 ( .A0(intDX_EWSW[12]), .A1(n1665), .B0(n1211), .C0(n1197),
.Y(n1213) );
AOI221X1TS U1139 ( .A0(n1665), .A1(intDX_EWSW[12]), .B0(intDX_EWSW[13]),
.B1(n1695), .C0(n1086), .Y(n1089) );
NOR2X2TS U1140 ( .A(n1033), .B(DMP_EXP_EWSW[23]), .Y(n1464) );
XNOR2X2TS U1141 ( .A(DMP_exp_NRM2_EW[6]), .B(n1114), .Y(n1413) );
XNOR2X2TS U1142 ( .A(DMP_exp_NRM2_EW[0]), .B(n1405), .Y(n1411) );
XNOR2X2TS U1143 ( .A(DMP_exp_NRM2_EW[5]), .B(DP_OP_15J41_125_2314_n4), .Y(
n1412) );
NOR2X4TS U1144 ( .A(shift_value_SHT2_EWR[4]), .B(n1591), .Y(n1589) );
CLKINVX6TS U1145 ( .A(n1618), .Y(n1591) );
XNOR2X2TS U1146 ( .A(intDY_EWSW[31]), .B(intAS), .Y(n1275) );
AOI2BB2X2TS U1147 ( .B0(OP_FLAG_SFG), .B1(DmP_mant_SFG_SWR[11]), .A0N(
DmP_mant_SFG_SWR[11]), .A1N(OP_FLAG_SFG), .Y(n1498) );
NOR2X2TS U1148 ( .A(DMP_SFG[2]), .B(n1059), .Y(n1550) );
NOR4BBX2TS U1149 ( .AN(n1317), .BN(n1151), .C(n1310), .D(n1150), .Y(n1353)
);
AOI222X1TS U1150 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n938), .B0(n1450), .B1(
n1002), .C0(n1449), .C1(DmP_mant_SHT1_SW[7]), .Y(n1366) );
AOI222X4TS U1151 ( .A0(DMP_SFG[1]), .A1(n1537), .B0(DMP_SFG[1]), .B1(n986),
.C0(n1537), .C1(n986), .Y(n1549) );
XOR2XLTS U1152 ( .A(DMP_SFG[1]), .B(n1537), .Y(n1538) );
INVX4TS U1153 ( .A(n1277), .Y(n1468) );
AOI222X1TS U1154 ( .A0(n1592), .A1(n1618), .B0(Data_array_SWR[7]), .B1(n1064), .C0(n1590), .C1(n1140), .Y(n1608) );
AOI222X1TS U1155 ( .A0(n1592), .A1(n1591), .B0(n1619), .B1(Data_array_SWR[7]), .C0(n1590), .C1(n1589), .Y(n1595) );
AOI222X1TS U1156 ( .A0(n1567), .A1(n1618), .B0(Data_array_SWR[6]), .B1(n1064), .C0(n1566), .C1(n1140), .Y(n1610) );
AOI222X1TS U1157 ( .A0(n1567), .A1(n1591), .B0(n1619), .B1(Data_array_SWR[6]), .C0(n1566), .C1(n1589), .Y(n1569) );
AOI222X1TS U1158 ( .A0(n1582), .A1(n1618), .B0(Data_array_SWR[5]), .B1(n1064), .C0(n1581), .C1(n1140), .Y(n1611) );
AOI222X1TS U1159 ( .A0(n1582), .A1(n1591), .B0(n1619), .B1(Data_array_SWR[5]), .C0(n1581), .C1(n1589), .Y(n1583) );
AOI222X1TS U1160 ( .A0(n1571), .A1(n1618), .B0(Data_array_SWR[4]), .B1(n1064), .C0(n1570), .C1(n1140), .Y(n1612) );
AOI222X1TS U1161 ( .A0(n1571), .A1(n1591), .B0(n1619), .B1(Data_array_SWR[4]), .C0(n1570), .C1(n1589), .Y(n1573) );
INVX3TS U1162 ( .A(n1423), .Y(n1430) );
OAI22X2TS U1163 ( .A0(n1514), .A1(n985), .B0(n1594), .B1(OP_FLAG_SFG), .Y(
n1484) );
INVX3TS U1164 ( .A(OP_FLAG_SFG), .Y(n1514) );
INVX3TS U1165 ( .A(n1467), .Y(n1475) );
BUFX3TS U1166 ( .A(Shift_reg_FLAGS_7_5), .Y(n1473) );
CLKINVX6TS U1167 ( .A(n934), .Y(n1480) );
AOI222X4TS U1168 ( .A0(Data_array_SWR[18]), .A1(n1541), .B0(
Data_array_SWR[21]), .B1(n1542), .C0(Data_array_SWR[15]), .C1(n1062),
.Y(n1576) );
AOI222X4TS U1169 ( .A0(Data_array_SWR[18]), .A1(n1139), .B0(
Data_array_SWR[21]), .B1(n1137), .C0(Data_array_SWR[15]), .C1(n1138),
.Y(n1529) );
NOR2X2TS U1170 ( .A(shift_value_SHT2_EWR[2]), .B(n1653), .Y(n1137) );
NOR2X4TS U1171 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n1138) );
NOR2X2TS U1172 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1640), .Y(n1416) );
NOR3X2TS U1173 ( .A(Raw_mant_NRM_SWR[6]), .B(Raw_mant_NRM_SWR[5]), .C(n1324),
.Y(n1311) );
NOR2X2TS U1174 ( .A(Raw_mant_NRM_SWR[13]), .B(n1141), .Y(n1152) );
AOI32X1TS U1175 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n1147), .A2(n1146), .B0(
Raw_mant_NRM_SWR[19]), .B1(n1147), .Y(n1148) );
NOR3X1TS U1176 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[19]), .C(
Raw_mant_NRM_SWR[20]), .Y(n1162) );
CLKINVX3TS U1177 ( .A(Shift_reg_FLAGS_7[0]), .Y(n1023) );
AOI221X1TS U1178 ( .A0(n1013), .A1(intDX_EWSW[24]), .B0(intDX_EWSW[9]), .B1(
n1426), .C0(n1085), .Y(n1091) );
AO22XLTS U1179 ( .A0(n1421), .A1(n933), .B0(n1023), .B1(n1420), .Y(n1024) );
NOR2XLTS U1180 ( .A(n1696), .B(intDX_EWSW[11]), .Y(n1199) );
OAI21XLTS U1181 ( .A0(intDX_EWSW[15]), .A1(n1673), .B0(intDX_EWSW[14]), .Y(
n1207) );
NOR2XLTS U1182 ( .A(n1220), .B(intDY_EWSW[16]), .Y(n1221) );
OAI21XLTS U1183 ( .A0(intDX_EWSW[21]), .A1(n1718), .B0(intDX_EWSW[20]), .Y(
n1219) );
NOR2XLTS U1184 ( .A(Raw_mant_NRM_SWR[17]), .B(Raw_mant_NRM_SWR[16]), .Y(
n1146) );
OAI211XLTS U1185 ( .A0(DMP_SFG[7]), .A1(n1521), .B0(n1525), .C0(n1489), .Y(
n1490) );
NOR2XLTS U1186 ( .A(Raw_mant_NRM_SWR[23]), .B(Raw_mant_NRM_SWR[22]), .Y(
n1149) );
OAI21XLTS U1187 ( .A0(Raw_mant_NRM_SWR[7]), .A1(Raw_mant_NRM_SWR[6]), .B0(
n1143), .Y(n1144) );
OAI21XLTS U1188 ( .A0(n1649), .A1(n1441), .B0(n1344), .Y(n1345) );
NOR2XLTS U1189 ( .A(n1172), .B(DMP_SFG[0]), .Y(n1173) );
AOI31XLTS U1190 ( .A0(n1480), .A1(Shift_amount_SHT1_EWR[4]), .A2(n933), .B0(
n1408), .Y(n1315) );
NOR2XLTS U1191 ( .A(n1470), .B(n1715), .Y(n1471) );
OAI21XLTS U1192 ( .A0(n1416), .A1(n1305), .B0(n1417), .Y(n931) );
OAI21XLTS U1193 ( .A0(n1428), .A1(n935), .B0(n1266), .Y(n639) );
OAI21XLTS U1194 ( .A0(n1428), .A1(n1304), .B0(n1289), .Y(n798) );
OAI21XLTS U1195 ( .A0(n1663), .A1(n1469), .B0(n1283), .Y(n812) );
OAI211XLTS U1196 ( .A0(n1397), .A1(n1457), .B0(n1396), .C0(n1395), .Y(n837)
);
NOR2XLTS U1197 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n1039) );
AOI32X4TS U1198 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n1039), .B1(n1640), .Y(n1421)
);
INVX2TS U1199 ( .A(n1421), .Y(n1420) );
BUFX4TS U1200 ( .A(n1629), .Y(n1299) );
AOI22X1TS U1201 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n1416), .B0(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n1659), .Y(n1422) );
OAI2BB2XLTS U1202 ( .B0(n1421), .B1(n1419), .A0N(n1421), .A1N(n1422), .Y(
n930) );
BUFX3TS U1203 ( .A(n937), .Y(n1710) );
BUFX3TS U1204 ( .A(n1041), .Y(n1711) );
BUFX3TS U1205 ( .A(n1040), .Y(n1699) );
BUFX3TS U1206 ( .A(n1041), .Y(n1712) );
BUFX3TS U1207 ( .A(n1041), .Y(n1704) );
AO22XLTS U1208 ( .A0(Shift_reg_FLAGS_7[1]), .A1(ZERO_FLAG_NRM), .B0(n933),
.B1(ZERO_FLAG_SHT1SHT2), .Y(n614) );
AO22XLTS U1209 ( .A0(Shift_reg_FLAGS_7[1]), .A1(SIGN_FLAG_NRM), .B0(n933),
.B1(SIGN_FLAG_SHT1SHT2), .Y(n605) );
BUFX4TS U1210 ( .A(Shift_reg_FLAGS_7_5), .Y(n1467) );
AO22XLTS U1211 ( .A0(n1467), .A1(DmP_EXP_EWSW[19]), .B0(n1475), .B1(n999),
.Y(n632) );
AO22XLTS U1212 ( .A0(n1467), .A1(DmP_EXP_EWSW[20]), .B0(n1475), .B1(n1003),
.Y(n630) );
AO22XLTS U1213 ( .A0(n1467), .A1(DmP_EXP_EWSW[18]), .B0(n1475), .B1(n1008),
.Y(n634) );
BUFX3TS U1214 ( .A(Shift_reg_FLAGS_7_5), .Y(n1476) );
NOR2X1TS U1215 ( .A(n1642), .B(DMP_EXP_EWSW[24]), .Y(n1047) );
AOI21X1TS U1216 ( .A0(DMP_EXP_EWSW[24]), .A1(n1642), .B0(n1047), .Y(n1043)
);
XNOR2X1TS U1217 ( .A(n1464), .B(n1043), .Y(n1044) );
AO22XLTS U1218 ( .A0(n1467), .A1(n1044), .B0(n1475), .B1(
Shift_amount_SHT1_EWR[1]), .Y(n826) );
INVX2TS U1219 ( .A(n1275), .Y(n1046) );
OAI21XLTS U1220 ( .A0(n1046), .A1(intDX_EWSW[31]), .B0(Shift_reg_FLAGS_7_6),
.Y(n1045) );
AOI21X1TS U1221 ( .A0(n1046), .A1(intDX_EWSW[31]), .B0(n1045), .Y(n1104) );
AO21XLTS U1222 ( .A0(OP_FLAG_EXP), .A1(n1419), .B0(n1104), .Y(n783) );
OAI22X1TS U1223 ( .A0(n1464), .A1(n1047), .B0(DmP_EXP_EWSW[24]), .B1(n1630),
.Y(n1050) );
NAND2X1TS U1224 ( .A(DmP_EXP_EWSW[25]), .B(n1682), .Y(n1051) );
OAI21XLTS U1225 ( .A0(DmP_EXP_EWSW[25]), .A1(n1682), .B0(n1051), .Y(n1048)
);
XNOR2X1TS U1226 ( .A(n1050), .B(n1048), .Y(n1049) );
AO22XLTS U1227 ( .A0(n1473), .A1(n1049), .B0(n1478), .B1(
Shift_amount_SHT1_EWR[2]), .Y(n825) );
BUFX4TS U1228 ( .A(n1716), .Y(n1563) );
OAI2BB2XLTS U1229 ( .B0(n1421), .B1(n1563), .A0N(n1421), .A1N(n996), .Y(n926) );
AOI22X1TS U1230 ( .A0(DMP_EXP_EWSW[25]), .A1(n1691), .B0(n1051), .B1(n1050),
.Y(n1054) );
NOR2X1TS U1231 ( .A(n1686), .B(DMP_EXP_EWSW[26]), .Y(n1055) );
AOI21X1TS U1232 ( .A0(DMP_EXP_EWSW[26]), .A1(n1686), .B0(n1055), .Y(n1052)
);
XNOR2X1TS U1233 ( .A(n1054), .B(n1052), .Y(n1053) );
AO22XLTS U1234 ( .A0(n1467), .A1(n1053), .B0(n1472), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n824) );
OAI22X1TS U1235 ( .A0(n1055), .A1(n1054), .B0(DmP_EXP_EWSW[26]), .B1(n1688),
.Y(n1057) );
XNOR2X1TS U1236 ( .A(DmP_EXP_EWSW[27]), .B(n1012), .Y(n1056) );
XOR2XLTS U1237 ( .A(n1057), .B(n1056), .Y(n1058) );
AO22XLTS U1238 ( .A0(n1467), .A1(n1058), .B0(n1472), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n823) );
INVX1TS U1239 ( .A(DmP_mant_SFG_SWR[4]), .Y(n1572) );
AOI22X1TS U1240 ( .A0(n1532), .A1(DmP_mant_SFG_SWR[4]), .B0(n1572), .B1(
n1636), .Y(n1059) );
NAND2X1TS U1241 ( .A(DMP_SFG[2]), .B(n1059), .Y(n1548) );
INVX2TS U1242 ( .A(n1548), .Y(n1483) );
AOI22X1TS U1243 ( .A0(OP_FLAG_SFG), .A1(DmP_mant_SFG_SWR[2]), .B0(n1514),
.B1(n1025), .Y(n1172) );
CLKAND2X2TS U1244 ( .A(n1172), .B(DMP_SFG[0]), .Y(n1537) );
NOR3X1TS U1245 ( .A(n1550), .B(n1483), .C(n1549), .Y(n1501) );
OA21XLTS U1246 ( .A0(n1550), .A1(n1483), .B0(n1549), .Y(n1060) );
OAI32X1TS U1247 ( .A0(n1716), .A1(n1501), .A2(n1060), .B0(n1565), .B1(n1634),
.Y(n570) );
BUFX3TS U1248 ( .A(n1466), .Y(n1593) );
NOR2BX1TS U1249 ( .AN(n1137), .B(shift_value_SHT2_EWR[4]), .Y(n1061) );
NAND2X1TS U1250 ( .A(n1653), .B(shift_value_SHT2_EWR[2]), .Y(n1105) );
AOI22X1TS U1251 ( .A0(Data_array_SWR[19]), .A1(n1541), .B0(
Data_array_SWR[16]), .B1(n1062), .Y(n1496) );
AND3X4TS U1252 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.C(n1660), .Y(n1542) );
NAND2X1TS U1253 ( .A(n1138), .B(n1660), .Y(n1509) );
NOR2XLTS U1254 ( .A(n1618), .B(n1509), .Y(n1063) );
AOI22X1TS U1255 ( .A0(Data_array_SWR[13]), .A1(n1619), .B0(n1020), .B1(n1064), .Y(n1065) );
OAI221X1TS U1256 ( .A0(n1618), .A1(n1496), .B0(n1591), .B1(n1497), .C0(n1065), .Y(n1585) );
AO22XLTS U1257 ( .A0(n1593), .A1(n989), .B0(n1616), .B1(n1585), .Y(n535) );
AOI22X1TS U1258 ( .A0(Data_array_SWR[20]), .A1(n1541), .B0(
Data_array_SWR[17]), .B1(n1062), .Y(n1069) );
AOI22X1TS U1259 ( .A0(Data_array_SWR[10]), .A1(n1619), .B0(
Data_array_SWR[14]), .B1(n1064), .Y(n1066) );
OAI221X1TS U1260 ( .A0(n1618), .A1(n1068), .B0(n1591), .B1(n1069), .C0(n1066), .Y(n1586) );
AO22XLTS U1261 ( .A0(n1620), .A1(DmP_mant_SFG_SWR[10]), .B0(n1604), .B1(
n1586), .Y(n550) );
AOI22X1TS U1262 ( .A0(Data_array_SWR[10]), .A1(n1064), .B0(
Data_array_SWR[14]), .B1(n1619), .Y(n1067) );
OAI221X1TS U1263 ( .A0(n1618), .A1(n1069), .B0(n1591), .B1(n1068), .C0(n1067), .Y(n1587) );
AO22XLTS U1264 ( .A0(n1620), .A1(n988), .B0(n1477), .B1(n1587), .Y(n534) );
AOI22X1TS U1265 ( .A0(Data_array_SWR[11]), .A1(n1064), .B0(
Data_array_SWR[12]), .B1(n1619), .Y(n1070) );
OAI221X1TS U1266 ( .A0(n1618), .A1(n1575), .B0(n1591), .B1(n1576), .C0(n1070), .Y(n1577) );
AO22XLTS U1267 ( .A0(n1620), .A1(n990), .B0(n1622), .B1(n1577), .Y(n536) );
OAI22X1TS U1268 ( .A0(n1670), .A1(intDX_EWSW[25]), .B0(n1016), .B1(
intDX_EWSW[26]), .Y(n1071) );
AOI221X1TS U1269 ( .A0(n1670), .A1(intDX_EWSW[25]), .B0(intDX_EWSW[26]),
.B1(n1016), .C0(n1071), .Y(n1077) );
OAI22X1TS U1270 ( .A0(n1667), .A1(intDX_EWSW[27]), .B0(n1677), .B1(
intDY_EWSW[28]), .Y(n1072) );
OAI22X1TS U1271 ( .A0(n1679), .A1(intDY_EWSW[29]), .B0(n1641), .B1(
intDY_EWSW[30]), .Y(n1073) );
AOI221X1TS U1272 ( .A0(n1679), .A1(intDY_EWSW[29]), .B0(intDY_EWSW[30]),
.B1(n1641), .C0(n1073), .Y(n1075) );
AOI2BB2XLTS U1273 ( .B0(intDX_EWSW[7]), .B1(n1668), .A0N(n1668), .A1N(
intDX_EWSW[7]), .Y(n1074) );
NAND4XLTS U1274 ( .A(n1077), .B(n1076), .C(n1075), .D(n1074), .Y(n1103) );
OAI22X1TS U1275 ( .A0(n1675), .A1(intDX_EWSW[1]), .B0(n1674), .B1(
intDX_EWSW[17]), .Y(n1078) );
OAI22X1TS U1276 ( .A0(n1015), .A1(intDX_EWSW[20]), .B0(n1718), .B1(
intDX_EWSW[21]), .Y(n1079) );
OAI22X1TS U1277 ( .A0(n1697), .A1(n1022), .B0(n1678), .B1(intDX_EWSW[23]),
.Y(n1080) );
NAND4XLTS U1278 ( .A(n1084), .B(n1083), .C(n1082), .D(n1081), .Y(n1102) );
INVX2TS U1279 ( .A(intDY_EWSW[9]), .Y(n1426) );
OAI22X1TS U1280 ( .A0(n964), .A1(intDX_EWSW[24]), .B0(n1426), .B1(
intDX_EWSW[9]), .Y(n1085) );
INVX2TS U1281 ( .A(intDY_EWSW[10]), .Y(n1427) );
OAI22X1TS U1282 ( .A0(n1427), .A1(intDX_EWSW[10]), .B0(n1696), .B1(
intDX_EWSW[11]), .Y(n1184) );
OAI22X1TS U1283 ( .A0(n1665), .A1(intDX_EWSW[12]), .B0(n1695), .B1(
intDX_EWSW[13]), .Y(n1086) );
OAI22X1TS U1284 ( .A0(n1694), .A1(intDX_EWSW[14]), .B0(n1673), .B1(
intDX_EWSW[15]), .Y(n1087) );
NAND4XLTS U1285 ( .A(n1091), .B(n1090), .C(n1089), .D(n1088), .Y(n1101) );
INVX2TS U1286 ( .A(intDY_EWSW[16]), .Y(n1428) );
OAI22X1TS U1287 ( .A0(n1428), .A1(intDX_EWSW[16]), .B0(n1671), .B1(
intDX_EWSW[0]), .Y(n1092) );
AOI221X1TS U1288 ( .A0(n1428), .A1(intDX_EWSW[16]), .B0(intDX_EWSW[0]), .B1(
n1671), .C0(n1092), .Y(n1099) );
OAI22X1TS U1289 ( .A0(n1663), .A1(intDX_EWSW[2]), .B0(n1672), .B1(
intDX_EWSW[3]), .Y(n1093) );
OAI22X1TS U1290 ( .A0(n1664), .A1(intDX_EWSW[4]), .B0(n1639), .B1(
intDX_EWSW[5]), .Y(n1094) );
AOI221X1TS U1291 ( .A0(n1664), .A1(intDX_EWSW[4]), .B0(intDX_EWSW[5]), .B1(
n1639), .C0(n1094), .Y(n1097) );
INVX2TS U1292 ( .A(intDY_EWSW[6]), .Y(n1425) );
OAI22X1TS U1293 ( .A0(n1676), .A1(intDX_EWSW[8]), .B0(n1425), .B1(
intDX_EWSW[6]), .Y(n1095) );
AOI221X1TS U1294 ( .A0(n1676), .A1(intDX_EWSW[8]), .B0(intDX_EWSW[6]), .B1(
n1425), .C0(n1095), .Y(n1096) );
NAND4XLTS U1295 ( .A(n1099), .B(n1098), .C(n1097), .D(n1096), .Y(n1100) );
NOR4X1TS U1296 ( .A(n1103), .B(n1102), .C(n1101), .D(n1100), .Y(n1276) );
BUFX4TS U1297 ( .A(n1299), .Y(n1301) );
AO22XLTS U1298 ( .A0(n1276), .A1(n1104), .B0(ZERO_FLAG_EXP), .B1(n1301), .Y(
n782) );
INVX2TS U1299 ( .A(n1105), .Y(n1139) );
AOI22X1TS U1300 ( .A0(Data_array_SWR[18]), .A1(n1138), .B0(
Data_array_SWR[21]), .B1(n1139), .Y(n1127) );
AOI22X1TS U1301 ( .A0(Data_array_SWR[11]), .A1(n1541), .B0(Data_array_SWR[8]), .B1(n1062), .Y(n1107) );
NAND2X1TS U1302 ( .A(Data_array_SWR[15]), .B(n1542), .Y(n1106) );
OAI211X1TS U1303 ( .A0(n1127), .A1(n1660), .B0(n1107), .C0(n1106), .Y(n1571)
);
AO22X1TS U1304 ( .A0(Data_array_SWR[22]), .A1(n1139), .B0(n1018), .B1(n1138),
.Y(n1570) );
INVX2TS U1305 ( .A(DP_OP_15J41_125_2314_n4), .Y(n1108) );
NAND2X1TS U1306 ( .A(n1669), .B(n1108), .Y(n1114) );
INVX1TS U1307 ( .A(LZD_output_NRM2_EW[0]), .Y(n1405) );
NOR2XLTS U1308 ( .A(n1411), .B(exp_rslt_NRM2_EW1[1]), .Y(n1111) );
INVX2TS U1309 ( .A(exp_rslt_NRM2_EW1[3]), .Y(n1110) );
INVX2TS U1310 ( .A(exp_rslt_NRM2_EW1[2]), .Y(n1109) );
NAND4BXLTS U1311 ( .AN(exp_rslt_NRM2_EW1[4]), .B(n1111), .C(n1110), .D(n1109), .Y(n1112) );
NOR2XLTS U1312 ( .A(n1112), .B(n1412), .Y(n1113) );
INVX2TS U1313 ( .A(n1114), .Y(n1115) );
NAND2X1TS U1314 ( .A(n1681), .B(n1115), .Y(n1121) );
XNOR2X1TS U1315 ( .A(DMP_exp_NRM2_EW[7]), .B(n1121), .Y(n1117) );
OR2X1TS U1316 ( .A(n1116), .B(n1117), .Y(n1470) );
INVX2TS U1317 ( .A(n1470), .Y(n1403) );
INVX2TS U1318 ( .A(n1117), .Y(n1402) );
AND4X1TS U1319 ( .A(exp_rslt_NRM2_EW1[3]), .B(n1411), .C(
exp_rslt_NRM2_EW1[2]), .D(exp_rslt_NRM2_EW1[1]), .Y(n1118) );
NAND3XLTS U1320 ( .A(n1412), .B(exp_rslt_NRM2_EW1[4]), .C(n1118), .Y(n1119)
);
NAND2BXLTS U1321 ( .AN(n1119), .B(n1413), .Y(n1120) );
NOR2XLTS U1322 ( .A(n1402), .B(n1120), .Y(n1124) );
INVX2TS U1323 ( .A(n1121), .Y(n1122) );
CLKAND2X2TS U1324 ( .A(n1685), .B(n1122), .Y(n1123) );
INVX4TS U1325 ( .A(n1588), .Y(n1602) );
OAI2BB2XLTS U1326 ( .B0(n1612), .B1(n1602), .A0N(final_result_ieee[19]),
.A1N(n1715), .Y(n561) );
AOI22X1TS U1327 ( .A0(Data_array_SWR[12]), .A1(n1541), .B0(Data_array_SWR[9]), .B1(n1062), .Y(n1126) );
AOI22X1TS U1328 ( .A0(n1019), .A1(n1542), .B0(shift_value_SHT2_EWR[4]), .B1(
n1570), .Y(n1125) );
NAND2X1TS U1329 ( .A(n1126), .B(n1125), .Y(n1582) );
INVX2TS U1330 ( .A(n1127), .Y(n1581) );
OAI2BB2XLTS U1331 ( .B0(n1611), .B1(n1602), .A0N(final_result_ieee[18]),
.A1N(n1715), .Y(n553) );
AOI22X1TS U1332 ( .A0(Data_array_SWR[14]), .A1(n1541), .B0(n1020), .B1(n1062), .Y(n1129) );
NOR2BX2TS U1333 ( .AN(n1138), .B(n1660), .Y(n1134) );
AOI22X1TS U1334 ( .A0(Data_array_SWR[20]), .A1(n1134), .B0(
Data_array_SWR[17]), .B1(n1542), .Y(n1128) );
NAND2X1TS U1335 ( .A(n1129), .B(n1128), .Y(n1592) );
AOI22X1TS U1336 ( .A0(Data_array_SWR[19]), .A1(n1139), .B0(
Data_array_SWR[16]), .B1(n1138), .Y(n1536) );
INVX2TS U1337 ( .A(n1536), .Y(n1590) );
OAI2BB2XLTS U1338 ( .B0(n1608), .B1(n1602), .A0N(final_result_ieee[16]),
.A1N(n1715), .Y(n545) );
AOI22X1TS U1339 ( .A0(Data_array_SWR[13]), .A1(n1541), .B0(
Data_array_SWR[10]), .B1(n1062), .Y(n1131) );
AOI22X1TS U1340 ( .A0(Data_array_SWR[19]), .A1(n1134), .B0(
Data_array_SWR[16]), .B1(n1542), .Y(n1130) );
NAND2X1TS U1341 ( .A(n1131), .B(n1130), .Y(n1567) );
AOI22X1TS U1342 ( .A0(Data_array_SWR[20]), .A1(n1139), .B0(
Data_array_SWR[17]), .B1(n1138), .Y(n1546) );
INVX2TS U1343 ( .A(n1546), .Y(n1566) );
OAI2BB2XLTS U1344 ( .B0(n1610), .B1(n1602), .A0N(final_result_ieee[17]),
.A1N(n1715), .Y(n564) );
AOI22X1TS U1345 ( .A0(n1019), .A1(n1541), .B0(Data_array_SWR[12]), .B1(n1062), .Y(n1133) );
AOI22X1TS U1346 ( .A0(n1018), .A1(n1542), .B0(Data_array_SWR[22]), .B1(n1134), .Y(n1132) );
NAND2X1TS U1347 ( .A(n1133), .B(n1132), .Y(n1579) );
INVX2TS U1348 ( .A(n1529), .Y(n1578) );
OAI2BB2XLTS U1349 ( .B0(n1605), .B1(n1602), .A0N(final_result_ieee[14]),
.A1N(n1715), .Y(n556) );
AOI22X1TS U1350 ( .A0(Data_array_SWR[11]), .A1(n1062), .B0(
Data_array_SWR[15]), .B1(n1541), .Y(n1136) );
AOI22X1TS U1351 ( .A0(Data_array_SWR[18]), .A1(n1542), .B0(
Data_array_SWR[21]), .B1(n1134), .Y(n1135) );
NAND2X1TS U1352 ( .A(n1136), .B(n1135), .Y(n1517) );
INVX2TS U1353 ( .A(n1512), .Y(n1516) );
OAI2BB2XLTS U1354 ( .B0(n1606), .B1(n1602), .A0N(final_result_ieee[15]),
.A1N(n1715), .Y(n541) );
NOR2BX1TS U1355 ( .AN(n1319), .B(Raw_mant_NRM_SWR[18]), .Y(n1154) );
NOR3X1TS U1356 ( .A(Raw_mant_NRM_SWR[15]), .B(Raw_mant_NRM_SWR[17]), .C(
Raw_mant_NRM_SWR[16]), .Y(n1155) );
CLKAND2X2TS U1357 ( .A(n1154), .B(n1155), .Y(n1153) );
NAND2X1TS U1358 ( .A(Raw_mant_NRM_SWR[14]), .B(n1153), .Y(n1317) );
NAND2X1TS U1359 ( .A(n1153), .B(n1625), .Y(n1141) );
NAND2X1TS U1360 ( .A(n1152), .B(n1646), .Y(n1142) );
NOR3X1TS U1361 ( .A(Raw_mant_NRM_SWR[12]), .B(n1647), .C(n1142), .Y(n1158)
);
AO21XLTS U1362 ( .A0(n1319), .A1(Raw_mant_NRM_SWR[18]), .B0(n1158), .Y(n1164) );
AOI31XLTS U1363 ( .A0(n1626), .A1(Raw_mant_NRM_SWR[11]), .A2(n1152), .B0(
n1164), .Y(n1151) );
NOR2XLTS U1364 ( .A(Raw_mant_NRM_SWR[2]), .B(Raw_mant_NRM_SWR[3]), .Y(n1145)
);
NOR2X1TS U1365 ( .A(Raw_mant_NRM_SWR[10]), .B(n1142), .Y(n1321) );
NAND2X1TS U1366 ( .A(n1321), .B(n1626), .Y(n1307) );
NOR3X1TS U1367 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[9]), .C(n1307),
.Y(n1143) );
NAND2X1TS U1368 ( .A(n1143), .B(n1633), .Y(n1324) );
NAND2X1TS U1369 ( .A(n1311), .B(n1634), .Y(n1168) );
OAI21X1TS U1370 ( .A0(n1145), .A1(n1168), .B0(n1144), .Y(n1310) );
NOR2X1TS U1371 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[20]), .Y(
n1147) );
AOI211X1TS U1372 ( .A0(n1149), .A1(n1148), .B0(Raw_mant_NRM_SWR[25]), .C0(
Raw_mant_NRM_SWR[24]), .Y(n1150) );
NOR2X1TS U1373 ( .A(n1353), .B(n933), .Y(n1326) );
AO21XLTS U1374 ( .A0(LZD_output_NRM2_EW[1]), .A1(n933), .B0(n1326), .Y(n572)
);
AOI32X1TS U1375 ( .A0(Shift_amount_SHT1_EWR[3]), .A1(n1455), .A2(n933), .B0(
shift_value_SHT2_EWR[3]), .B1(n936), .Y(n1159) );
NAND2X1TS U1376 ( .A(Raw_mant_NRM_SWR[12]), .B(n1152), .Y(n1166) );
OAI211X1TS U1377 ( .A0(Raw_mant_NRM_SWR[11]), .A1(Raw_mant_NRM_SWR[13]),
.B0(n1153), .C0(n1625), .Y(n1160) );
NOR3X1TS U1378 ( .A(Raw_mant_NRM_SWR[2]), .B(Raw_mant_NRM_SWR[3]), .C(n1168),
.Y(n1163) );
NAND2X1TS U1379 ( .A(Raw_mant_NRM_SWR[1]), .B(n1163), .Y(n1312) );
OAI2BB1X1TS U1380 ( .A0N(n1155), .A1N(n1625), .B0(n1154), .Y(n1156) );
NAND4XLTS U1381 ( .A(n1166), .B(n1160), .C(n1312), .D(n1156), .Y(n1157) );
OAI21X1TS U1382 ( .A0(n1158), .A1(n1157), .B0(Shift_reg_FLAGS_7[1]), .Y(
n1409) );
NAND2X1TS U1383 ( .A(n1159), .B(n1409), .Y(n830) );
OAI21XLTS U1384 ( .A0(n1162), .A1(n1161), .B0(n1160), .Y(n1170) );
NAND2X1TS U1385 ( .A(n1163), .B(n1017), .Y(n1313) );
OAI21XLTS U1386 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n1648), .B0(n1634), .Y(n1165) );
AOI21X1TS U1387 ( .A0(n1311), .A1(n1165), .B0(n1164), .Y(n1167) );
OAI211X1TS U1388 ( .A0(Raw_mant_NRM_SWR[1]), .A1(n1313), .B0(n1167), .C0(
n1166), .Y(n1320) );
NAND2BXLTS U1389 ( .AN(n1324), .B(Raw_mant_NRM_SWR[5]), .Y(n1306) );
OAI22X1TS U1390 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n1306), .B0(n1168), .B1(
n1683), .Y(n1169) );
OAI31X1TS U1391 ( .A0(n1170), .A1(n1320), .A2(n1169), .B0(
Shift_reg_FLAGS_7[1]), .Y(n1410) );
NAND2X1TS U1392 ( .A(n1171), .B(n1410), .Y(n831) );
OAI21XLTS U1393 ( .A0(n1480), .A1(n1591), .B0(n933), .Y(n890) );
OAI32X1TS U1394 ( .A0(n1716), .A1(n1537), .A2(n1173), .B0(n1565), .B1(n1648),
.Y(n575) );
NOR2X1TS U1395 ( .A(n1670), .B(intDX_EWSW[25]), .Y(n1234) );
NOR2XLTS U1396 ( .A(n1234), .B(n1014), .Y(n1174) );
AOI22X1TS U1397 ( .A0(intDX_EWSW[25]), .A1(n1670), .B0(intDX_EWSW[24]), .B1(
n1174), .Y(n1178) );
OAI21X1TS U1398 ( .A0(intDX_EWSW[26]), .A1(n1016), .B0(n1175), .Y(n1235) );
NAND3XLTS U1399 ( .A(n1016), .B(n1175), .C(intDX_EWSW[26]), .Y(n1177) );
NAND2BXLTS U1400 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n1176) );
OAI211XLTS U1401 ( .A0(n1178), .A1(n1235), .B0(n1177), .C0(n1176), .Y(n1183)
);
NOR2X1TS U1402 ( .A(n1656), .B(intDX_EWSW[30]), .Y(n1181) );
NOR2X1TS U1403 ( .A(n1638), .B(intDX_EWSW[29]), .Y(n1179) );
AOI211X1TS U1404 ( .A0(intDY_EWSW[28]), .A1(n1677), .B0(n1181), .C0(n1179),
.Y(n1233) );
NOR3X1TS U1405 ( .A(n1677), .B(n1179), .C(intDY_EWSW[28]), .Y(n1180) );
AOI221X1TS U1406 ( .A0(intDX_EWSW[30]), .A1(n1656), .B0(intDX_EWSW[29]),
.B1(n1638), .C0(n1180), .Y(n1182) );
AOI2BB2X1TS U1407 ( .B0(n1183), .B1(n1233), .A0N(n1182), .A1N(n1181), .Y(
n1239) );
NOR2X1TS U1408 ( .A(n1674), .B(intDX_EWSW[17]), .Y(n1220) );
NAND2BXLTS U1409 ( .AN(intDX_EWSW[9]), .B(intDY_EWSW[9]), .Y(n1201) );
INVX2TS U1410 ( .A(n1184), .Y(n1204) );
OAI211XLTS U1411 ( .A0(intDX_EWSW[8]), .A1(n1676), .B0(n1201), .C0(n1204),
.Y(n1215) );
OAI2BB1X1TS U1412 ( .A0N(n1651), .A1N(intDY_EWSW[5]), .B0(intDX_EWSW[4]),
.Y(n1185) );
OAI22X1TS U1413 ( .A0(intDY_EWSW[4]), .A1(n1185), .B0(n1651), .B1(
intDY_EWSW[5]), .Y(n1196) );
OAI2BB1X1TS U1414 ( .A0N(n1637), .A1N(intDY_EWSW[7]), .B0(intDX_EWSW[6]),
.Y(n1186) );
OAI22X1TS U1415 ( .A0(intDY_EWSW[6]), .A1(n1186), .B0(n1637), .B1(
intDY_EWSW[7]), .Y(n1195) );
OAI21XLTS U1416 ( .A0(intDX_EWSW[1]), .A1(n1675), .B0(intDX_EWSW[0]), .Y(
n1187) );
OAI2BB2XLTS U1417 ( .B0(intDY_EWSW[0]), .B1(n1187), .A0N(intDX_EWSW[1]),
.A1N(n1675), .Y(n1189) );
OAI211XLTS U1418 ( .A0(n1672), .A1(intDX_EWSW[3]), .B0(n1189), .C0(n1188),
.Y(n1192) );
OAI21XLTS U1419 ( .A0(intDX_EWSW[3]), .A1(n1672), .B0(intDX_EWSW[2]), .Y(
n1190) );
AOI2BB2XLTS U1420 ( .B0(intDX_EWSW[3]), .B1(n1672), .A0N(intDY_EWSW[2]),
.A1N(n1190), .Y(n1191) );
AOI222X1TS U1421 ( .A0(intDY_EWSW[4]), .A1(n1635), .B0(n1192), .B1(n1191),
.C0(intDY_EWSW[5]), .C1(n1651), .Y(n1194) );
AOI22X1TS U1422 ( .A0(intDY_EWSW[7]), .A1(n1637), .B0(intDY_EWSW[6]), .B1(
n1652), .Y(n1193) );
OAI32X1TS U1423 ( .A0(n1196), .A1(n1195), .A2(n1194), .B0(n1193), .B1(n1195),
.Y(n1214) );
OA22X1TS U1424 ( .A0(n1694), .A1(intDX_EWSW[14]), .B0(n1673), .B1(
intDX_EWSW[15]), .Y(n1211) );
OAI21XLTS U1425 ( .A0(intDX_EWSW[13]), .A1(n1695), .B0(intDX_EWSW[12]), .Y(
n1198) );
OAI2BB2XLTS U1426 ( .B0(intDY_EWSW[12]), .B1(n1198), .A0N(intDX_EWSW[13]),
.A1N(n1695), .Y(n1210) );
NOR2XLTS U1427 ( .A(n1199), .B(intDY_EWSW[10]), .Y(n1200) );
AOI22X1TS U1428 ( .A0(intDX_EWSW[11]), .A1(n1696), .B0(intDX_EWSW[10]), .B1(
n1200), .Y(n1206) );
NAND2BXLTS U1429 ( .AN(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n1203) );
NAND3XLTS U1430 ( .A(n1676), .B(n1201), .C(intDX_EWSW[8]), .Y(n1202) );
AOI21X1TS U1431 ( .A0(n1203), .A1(n1202), .B0(n1213), .Y(n1205) );
OAI2BB2XLTS U1432 ( .B0(n1206), .B1(n1213), .A0N(n1205), .A1N(n1204), .Y(
n1209) );
OAI2BB2XLTS U1433 ( .B0(intDY_EWSW[14]), .B1(n1207), .A0N(intDX_EWSW[15]),
.A1N(n1673), .Y(n1208) );
AOI211X1TS U1434 ( .A0(n1211), .A1(n1210), .B0(n1209), .C0(n1208), .Y(n1212)
);
OAI31X1TS U1435 ( .A0(n1215), .A1(n1214), .A2(n1213), .B0(n1212), .Y(n1218)
);
OA22X1TS U1436 ( .A0(n1697), .A1(n1022), .B0(n1678), .B1(intDX_EWSW[23]),
.Y(n1231) );
NAND3BXLTS U1437 ( .AN(n1220), .B(n1218), .C(n1217), .Y(n1238) );
AOI22X1TS U1438 ( .A0(intDX_EWSW[17]), .A1(n1674), .B0(intDX_EWSW[16]), .B1(
n1221), .Y(n1224) );
OAI32X1TS U1439 ( .A0(n1226), .A1(n1225), .A2(n1224), .B0(n1223), .B1(n1225),
.Y(n1229) );
OAI21XLTS U1440 ( .A0(intDX_EWSW[23]), .A1(n1678), .B0(n1022), .Y(n1227) );
OAI2BB2XLTS U1441 ( .B0(intDY_EWSW[22]), .B1(n1227), .A0N(intDX_EWSW[23]),
.A1N(n1678), .Y(n1228) );
AOI211X1TS U1442 ( .A0(n1231), .A1(n1230), .B0(n1229), .C0(n1228), .Y(n1237)
);
NAND2BXLTS U1443 ( .AN(intDX_EWSW[24]), .B(n1014), .Y(n1232) );
NAND4BBX1TS U1444 ( .AN(n1235), .BN(n1234), .C(n1233), .D(n1232), .Y(n1236)
);
AOI32X1TS U1445 ( .A0(n1239), .A1(n1238), .A2(n1237), .B0(n1236), .B1(n1239),
.Y(n1240) );
NOR2XLTS U1446 ( .A(n1240), .B(n1629), .Y(n1243) );
AOI22X1TS U1447 ( .A0(intDX_EWSW[1]), .A1(n939), .B0(DmP_EXP_EWSW[1]), .B1(
n1301), .Y(n1241) );
OAI21XLTS U1448 ( .A0(n1675), .A1(n935), .B0(n1241), .Y(n669) );
AOI22X1TS U1449 ( .A0(intDX_EWSW[0]), .A1(n939), .B0(DmP_EXP_EWSW[0]), .B1(
n1301), .Y(n1242) );
OAI21XLTS U1450 ( .A0(n1671), .A1(n1468), .B0(n1242), .Y(n671) );
AOI22X1TS U1451 ( .A0(intDX_EWSW[4]), .A1(n939), .B0(DmP_EXP_EWSW[4]), .B1(
n1419), .Y(n1244) );
OAI21XLTS U1452 ( .A0(n1664), .A1(n935), .B0(n1244), .Y(n663) );
AOI22X1TS U1453 ( .A0(intDX_EWSW[2]), .A1(n939), .B0(DmP_EXP_EWSW[2]), .B1(
n1419), .Y(n1245) );
OAI21XLTS U1454 ( .A0(n1663), .A1(n1468), .B0(n1245), .Y(n667) );
AOI22X1TS U1455 ( .A0(intDX_EWSW[3]), .A1(n939), .B0(DmP_EXP_EWSW[3]), .B1(
n1419), .Y(n1246) );
OAI21XLTS U1456 ( .A0(n1672), .A1(n1468), .B0(n1246), .Y(n665) );
AOI22X1TS U1457 ( .A0(intDY_EWSW[30]), .A1(n1269), .B0(DMP_EXP_EWSW[30]),
.B1(n1301), .Y(n1247) );
OAI21XLTS U1458 ( .A0(n1641), .A1(n1468), .B0(n1247), .Y(n784) );
AOI22X1TS U1459 ( .A0(intDY_EWSW[29]), .A1(n1269), .B0(DMP_EXP_EWSW[29]),
.B1(n1301), .Y(n1248) );
OAI21XLTS U1460 ( .A0(n1679), .A1(n935), .B0(n1248), .Y(n785) );
INVX4TS U1461 ( .A(n939), .Y(n1304) );
AOI22X1TS U1462 ( .A0(DMP_EXP_EWSW[23]), .A1(n1419), .B0(intDX_EWSW[23]),
.B1(n1277), .Y(n1249) );
OAI21XLTS U1463 ( .A0(n1678), .A1(n1304), .B0(n1249), .Y(n791) );
AOI22X1TS U1464 ( .A0(intDX_EWSW[7]), .A1(n939), .B0(DmP_EXP_EWSW[7]), .B1(
n1419), .Y(n1250) );
OAI21XLTS U1465 ( .A0(n1668), .A1(n935), .B0(n1250), .Y(n657) );
AOI22X1TS U1466 ( .A0(intDX_EWSW[12]), .A1(n939), .B0(DmP_EXP_EWSW[12]),
.B1(n1419), .Y(n1251) );
OAI21XLTS U1467 ( .A0(n1665), .A1(n935), .B0(n1251), .Y(n647) );
AOI22X1TS U1468 ( .A0(intDX_EWSW[5]), .A1(n939), .B0(DmP_EXP_EWSW[5]), .B1(
n1301), .Y(n1252) );
OAI21XLTS U1469 ( .A0(n1639), .A1(n935), .B0(n1252), .Y(n661) );
AOI22X1TS U1470 ( .A0(intDX_EWSW[8]), .A1(n939), .B0(DmP_EXP_EWSW[8]), .B1(
n1299), .Y(n1253) );
OAI21XLTS U1471 ( .A0(n1676), .A1(n935), .B0(n1253), .Y(n655) );
AOI22X1TS U1472 ( .A0(DmP_EXP_EWSW[27]), .A1(n1419), .B0(intDX_EWSW[27]),
.B1(n939), .Y(n1254) );
OAI21XLTS U1473 ( .A0(n1667), .A1(n935), .B0(n1254), .Y(n621) );
BUFX3TS U1474 ( .A(n939), .Y(n1269) );
AOI22X1TS U1475 ( .A0(intDX_EWSW[13]), .A1(n1269), .B0(DmP_EXP_EWSW[13]),
.B1(n1301), .Y(n1255) );
OAI21XLTS U1476 ( .A0(n1695), .A1(n935), .B0(n1255), .Y(n645) );
AOI22X1TS U1477 ( .A0(intDX_EWSW[15]), .A1(n1269), .B0(DmP_EXP_EWSW[15]),
.B1(n1419), .Y(n1256) );
OAI21XLTS U1478 ( .A0(n1673), .A1(n935), .B0(n1256), .Y(n641) );
AOI22X1TS U1479 ( .A0(intDX_EWSW[11]), .A1(n939), .B0(DmP_EXP_EWSW[11]),
.B1(n1299), .Y(n1257) );
OAI21XLTS U1480 ( .A0(n1696), .A1(n1468), .B0(n1257), .Y(n649) );
AOI22X1TS U1481 ( .A0(intDX_EWSW[14]), .A1(n1269), .B0(DmP_EXP_EWSW[14]),
.B1(n1419), .Y(n1258) );
OAI21XLTS U1482 ( .A0(n1694), .A1(n1468), .B0(n1258), .Y(n643) );
AOI22X1TS U1483 ( .A0(intDX_EWSW[18]), .A1(n939), .B0(DmP_EXP_EWSW[18]),
.B1(n1419), .Y(n1259) );
OAI21XLTS U1484 ( .A0(n1698), .A1(n1468), .B0(n1259), .Y(n635) );
AOI22X1TS U1485 ( .A0(n1021), .A1(n1269), .B0(DmP_EXP_EWSW[19]), .B1(n1419),
.Y(n1260) );
OAI21XLTS U1486 ( .A0(n1680), .A1(n1468), .B0(n1260), .Y(n633) );
AOI22X1TS U1487 ( .A0(intDY_EWSW[28]), .A1(n1269), .B0(DMP_EXP_EWSW[28]),
.B1(n1301), .Y(n1261) );
OAI21XLTS U1488 ( .A0(n1677), .A1(n935), .B0(n1261), .Y(n786) );
AOI22X1TS U1489 ( .A0(intDX_EWSW[17]), .A1(n1269), .B0(DmP_EXP_EWSW[17]),
.B1(n1419), .Y(n1262) );
OAI21XLTS U1490 ( .A0(n1674), .A1(n1468), .B0(n1262), .Y(n637) );
AOI22X1TS U1491 ( .A0(n1022), .A1(n1269), .B0(DmP_EXP_EWSW[22]), .B1(n1419),
.Y(n1263) );
OAI21XLTS U1492 ( .A0(n1697), .A1(n1468), .B0(n1263), .Y(n627) );
AOI22X1TS U1493 ( .A0(intDX_EWSW[20]), .A1(n1269), .B0(DmP_EXP_EWSW[20]),
.B1(n1419), .Y(n1264) );
OAI21XLTS U1494 ( .A0(n1015), .A1(n1468), .B0(n1264), .Y(n631) );
AOI22X1TS U1495 ( .A0(intDX_EWSW[9]), .A1(n939), .B0(DmP_EXP_EWSW[9]), .B1(
n1299), .Y(n1265) );
OAI21XLTS U1496 ( .A0(n1426), .A1(n935), .B0(n1265), .Y(n653) );
AOI22X1TS U1497 ( .A0(intDX_EWSW[16]), .A1(n1269), .B0(DmP_EXP_EWSW[16]),
.B1(n1419), .Y(n1266) );
AOI22X1TS U1498 ( .A0(intDX_EWSW[10]), .A1(n939), .B0(DmP_EXP_EWSW[10]),
.B1(n1301), .Y(n1267) );
OAI21XLTS U1499 ( .A0(n1427), .A1(n1468), .B0(n1267), .Y(n651) );
AOI22X1TS U1500 ( .A0(intDX_EWSW[6]), .A1(n939), .B0(DmP_EXP_EWSW[6]), .B1(
n1419), .Y(n1268) );
OAI21XLTS U1501 ( .A0(n1425), .A1(n1468), .B0(n1268), .Y(n659) );
AOI22X1TS U1502 ( .A0(intDX_EWSW[21]), .A1(n1269), .B0(DmP_EXP_EWSW[21]),
.B1(n1419), .Y(n1270) );
OAI21XLTS U1503 ( .A0(n1718), .A1(n935), .B0(n1270), .Y(n629) );
INVX4TS U1504 ( .A(n939), .Y(n1469) );
AOI22X1TS U1505 ( .A0(intDX_EWSW[20]), .A1(n1277), .B0(DMP_EXP_EWSW[20]),
.B1(n1301), .Y(n1271) );
OAI21XLTS U1506 ( .A0(n1015), .A1(n1469), .B0(n1271), .Y(n794) );
AOI22X1TS U1507 ( .A0(n1022), .A1(n1277), .B0(DMP_EXP_EWSW[22]), .B1(n1301),
.Y(n1272) );
OAI21XLTS U1508 ( .A0(n1697), .A1(n1469), .B0(n1272), .Y(n792) );
OAI21XLTS U1509 ( .A0(n1275), .A1(n1629), .B0(n935), .Y(n1273) );
AOI22X1TS U1510 ( .A0(intDX_EWSW[31]), .A1(n1273), .B0(SIGN_FLAG_EXP), .B1(
n1301), .Y(n1274) );
AOI22X1TS U1511 ( .A0(intDX_EWSW[5]), .A1(n1277), .B0(DMP_EXP_EWSW[5]), .B1(
n1299), .Y(n1278) );
OAI21XLTS U1512 ( .A0(n1639), .A1(n1469), .B0(n1278), .Y(n809) );
AOI22X1TS U1513 ( .A0(intDX_EWSW[4]), .A1(n1277), .B0(DMP_EXP_EWSW[4]), .B1(
n1299), .Y(n1279) );
OAI21XLTS U1514 ( .A0(n1664), .A1(n1304), .B0(n1279), .Y(n810) );
AOI22X1TS U1515 ( .A0(intDX_EWSW[7]), .A1(n1277), .B0(DMP_EXP_EWSW[7]), .B1(
n1299), .Y(n1280) );
OAI21XLTS U1516 ( .A0(n1668), .A1(n1304), .B0(n1280), .Y(n807) );
AOI22X1TS U1517 ( .A0(intDX_EWSW[6]), .A1(n1277), .B0(DMP_EXP_EWSW[6]), .B1(
n1299), .Y(n1281) );
OAI21XLTS U1518 ( .A0(n1425), .A1(n1304), .B0(n1281), .Y(n808) );
AOI22X1TS U1519 ( .A0(intDX_EWSW[0]), .A1(n1277), .B0(DMP_EXP_EWSW[0]), .B1(
n1419), .Y(n1282) );
OAI21XLTS U1520 ( .A0(n1671), .A1(n1469), .B0(n1282), .Y(n814) );
AOI22X1TS U1521 ( .A0(intDX_EWSW[2]), .A1(n1277), .B0(DMP_EXP_EWSW[2]), .B1(
n1419), .Y(n1283) );
AOI22X1TS U1522 ( .A0(intDX_EWSW[1]), .A1(n1277), .B0(DMP_EXP_EWSW[1]), .B1(
n1299), .Y(n1284) );
OAI21XLTS U1523 ( .A0(n1675), .A1(n1304), .B0(n1284), .Y(n813) );
AOI22X1TS U1524 ( .A0(intDX_EWSW[8]), .A1(n1277), .B0(DMP_EXP_EWSW[8]), .B1(
n1299), .Y(n1285) );
OAI21XLTS U1525 ( .A0(n1676), .A1(n1304), .B0(n1285), .Y(n806) );
AOI22X1TS U1526 ( .A0(intDX_EWSW[9]), .A1(n1277), .B0(DMP_EXP_EWSW[9]), .B1(
n1299), .Y(n1286) );
OAI21XLTS U1527 ( .A0(n1426), .A1(n1304), .B0(n1286), .Y(n805) );
AOI22X1TS U1528 ( .A0(intDX_EWSW[3]), .A1(n1277), .B0(DMP_EXP_EWSW[3]), .B1(
n1299), .Y(n1287) );
OAI21XLTS U1529 ( .A0(n1672), .A1(n1304), .B0(n1287), .Y(n811) );
AOI22X1TS U1530 ( .A0(intDX_EWSW[21]), .A1(n1277), .B0(DMP_EXP_EWSW[21]),
.B1(n1301), .Y(n1288) );
OAI21XLTS U1531 ( .A0(n1718), .A1(n1469), .B0(n1288), .Y(n793) );
BUFX3TS U1532 ( .A(n1277), .Y(n1302) );
AOI22X1TS U1533 ( .A0(intDX_EWSW[16]), .A1(n1302), .B0(DMP_EXP_EWSW[16]),
.B1(n1299), .Y(n1289) );
AOI22X1TS U1534 ( .A0(n1021), .A1(n1302), .B0(DMP_EXP_EWSW[19]), .B1(n1301),
.Y(n1290) );
OAI21XLTS U1535 ( .A0(n1680), .A1(n1469), .B0(n1290), .Y(n795) );
AOI22X1TS U1536 ( .A0(intDX_EWSW[18]), .A1(n1302), .B0(DMP_EXP_EWSW[18]),
.B1(n1301), .Y(n1291) );
OAI21XLTS U1537 ( .A0(n1698), .A1(n1304), .B0(n1291), .Y(n796) );
AOI22X1TS U1538 ( .A0(intDX_EWSW[10]), .A1(n1302), .B0(DMP_EXP_EWSW[10]),
.B1(n1301), .Y(n1292) );
OAI21XLTS U1539 ( .A0(n1427), .A1(n1304), .B0(n1292), .Y(n804) );
AOI222X1TS U1540 ( .A0(n1269), .A1(intDX_EWSW[23]), .B0(DmP_EXP_EWSW[23]),
.B1(n1629), .C0(intDY_EWSW[23]), .C1(n1302), .Y(n1293) );
INVX2TS U1541 ( .A(n1293), .Y(n625) );
AOI22X1TS U1542 ( .A0(intDX_EWSW[14]), .A1(n1302), .B0(DMP_EXP_EWSW[14]),
.B1(n1299), .Y(n1294) );
OAI21XLTS U1543 ( .A0(n1694), .A1(n1304), .B0(n1294), .Y(n800) );
AOI22X1TS U1544 ( .A0(intDX_EWSW[11]), .A1(n1302), .B0(DMP_EXP_EWSW[11]),
.B1(n1299), .Y(n1295) );
OAI21XLTS U1545 ( .A0(n1696), .A1(n1304), .B0(n1295), .Y(n803) );
AOI22X1TS U1546 ( .A0(intDX_EWSW[17]), .A1(n1302), .B0(DMP_EXP_EWSW[17]),
.B1(n1301), .Y(n1296) );
OAI21XLTS U1547 ( .A0(n1674), .A1(n1304), .B0(n1296), .Y(n797) );
AOI22X1TS U1548 ( .A0(intDX_EWSW[12]), .A1(n1302), .B0(DMP_EXP_EWSW[12]),
.B1(n1299), .Y(n1297) );
OAI21XLTS U1549 ( .A0(n1665), .A1(n1304), .B0(n1297), .Y(n802) );
AOI22X1TS U1550 ( .A0(n1012), .A1(n1419), .B0(intDX_EWSW[27]), .B1(n1302),
.Y(n1298) );
OAI21XLTS U1551 ( .A0(n1667), .A1(n1469), .B0(n1298), .Y(n787) );
AOI22X1TS U1552 ( .A0(intDX_EWSW[13]), .A1(n1302), .B0(DMP_EXP_EWSW[13]),
.B1(n1299), .Y(n1300) );
OAI21XLTS U1553 ( .A0(n1695), .A1(n1304), .B0(n1300), .Y(n801) );
AOI22X1TS U1554 ( .A0(intDX_EWSW[15]), .A1(n1302), .B0(DMP_EXP_EWSW[15]),
.B1(n1301), .Y(n1303) );
OAI21XLTS U1555 ( .A0(n1673), .A1(n1304), .B0(n1303), .Y(n799) );
AOI2BB2XLTS U1556 ( .B0(beg_OP), .B1(n1659), .A0N(n1659), .A1N(
inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n1305) );
NAND3XLTS U1557 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1659), .C(
n1640), .Y(n1417) );
NOR2XLTS U1558 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[9]), .Y(n1308)
);
OAI21XLTS U1559 ( .A0(n1308), .A1(n1307), .B0(n1306), .Y(n1309) );
OAI21XLTS U1560 ( .A0(n1455), .A1(n1660), .B0(n1315), .Y(n828) );
INVX2TS U1561 ( .A(DMP_SFG[10]), .Y(intadd_46_A_0_) );
INVX2TS U1562 ( .A(DMP_SFG[12]), .Y(intadd_46_A_2_) );
INVX2TS U1563 ( .A(DMP_SFG[13]), .Y(intadd_46_A_3_) );
INVX2TS U1564 ( .A(DMP_SFG[14]), .Y(intadd_46_A_4_) );
INVX2TS U1565 ( .A(DMP_SFG[15]), .Y(intadd_46_A_5_) );
INVX2TS U1566 ( .A(DMP_SFG[16]), .Y(intadd_46_A_6_) );
INVX2TS U1567 ( .A(DMP_SFG[17]), .Y(intadd_46_A_7_) );
INVX2TS U1568 ( .A(DMP_SFG[18]), .Y(intadd_46_A_8_) );
INVX2TS U1569 ( .A(DMP_SFG[19]), .Y(intadd_46_A_9_) );
INVX2TS U1570 ( .A(DMP_SFG[20]), .Y(intadd_46_A_10_) );
INVX2TS U1571 ( .A(DMP_SFG[21]), .Y(intadd_46_A_11_) );
INVX2TS U1572 ( .A(DMP_SFG[22]), .Y(intadd_46_A_12_) );
AOI32X1TS U1573 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n952), .A2(n1627), .B0(
Raw_mant_NRM_SWR[22]), .B1(n952), .Y(n1316) );
AOI32X1TS U1574 ( .A0(n1623), .A1(n1317), .A2(n1316), .B0(
Raw_mant_NRM_SWR[25]), .B1(n1317), .Y(n1318) );
AOI31XLTS U1575 ( .A0(n1319), .A1(Raw_mant_NRM_SWR[16]), .A2(n1628), .B0(
n1318), .Y(n1323) );
OAI211X1TS U1576 ( .A0(n1650), .A1(n1324), .B0(n1323), .C0(n1322), .Y(n1330)
);
AOI21X1TS U1577 ( .A0(Shift_amount_SHT1_EWR[1]), .A1(n933), .B0(n1326), .Y(
n1328) );
NOR2X2TS U1578 ( .A(n936), .B(n1328), .Y(n1461) );
NAND2X1TS U1579 ( .A(n1328), .B(n1455), .Y(n1329) );
INVX2TS U1580 ( .A(n1457), .Y(n1350) );
NAND2X2TS U1581 ( .A(n1330), .B(Shift_reg_FLAGS_7[1]), .Y(n1452) );
INVX2TS U1582 ( .A(n1452), .Y(n1439) );
AOI22X1TS U1583 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n1439), .B0(n1449), .B1(
DmP_mant_SHT1_SW[2]), .Y(n1332) );
AOI22X1TS U1584 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n938), .B0(n1450), .B1(
n1010), .Y(n1331) );
NAND2X1TS U1585 ( .A(n1332), .B(n1331), .Y(n1378) );
AOI22X1TS U1586 ( .A0(n936), .A1(Data_array_SWR[3]), .B0(n1350), .B1(n1378),
.Y(n1335) );
BUFX3TS U1587 ( .A(n1333), .Y(n1389) );
NAND2X1TS U1588 ( .A(Raw_mant_NRM_SWR[19]), .B(n1389), .Y(n1334) );
OAI211XLTS U1589 ( .A0(n1397), .A1(n1327), .B0(n1335), .C0(n1334), .Y(n835)
);
AOI22X1TS U1590 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n1439), .B0(n1449), .B1(
n1010), .Y(n1337) );
AOI22X1TS U1591 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n938), .B0(n1450), .B1(
n1011), .Y(n1336) );
NAND2X1TS U1592 ( .A(n1337), .B(n1336), .Y(n1460) );
AOI22X1TS U1593 ( .A0(n936), .A1(Data_array_SWR[2]), .B0(n1350), .B1(n1460),
.Y(n1339) );
NAND2X1TS U1594 ( .A(Raw_mant_NRM_SWR[20]), .B(n1389), .Y(n1338) );
OAI211XLTS U1595 ( .A0(n1401), .A1(n1327), .B0(n1339), .C0(n1338), .Y(n834)
);
AOI22X1TS U1596 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n1439), .B0(n1449), .B1(
n1002), .Y(n1341) );
AOI22X1TS U1597 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n938), .B0(n1450), .B1(
n1009), .Y(n1340) );
NAND2X1TS U1598 ( .A(n1341), .B(n1340), .Y(n1394) );
AOI22X1TS U1599 ( .A0(n936), .A1(Data_array_SWR[7]), .B0(n1350), .B1(n1394),
.Y(n1343) );
NAND2X1TS U1600 ( .A(Raw_mant_NRM_SWR[15]), .B(n1389), .Y(n1342) );
OAI211XLTS U1601 ( .A0(n1393), .A1(n1327), .B0(n1343), .C0(n1342), .Y(n839)
);
AOI22X1TS U1602 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n1439), .B0(n1449), .B1(
n1004), .Y(n1344) );
AOI21X1TS U1603 ( .A0(n1450), .A1(DmP_mant_SHT1_SW[14]), .B0(n1345), .Y(
n1448) );
OAI2BB2XLTS U1604 ( .B0(n1371), .B1(n1327), .A0N(Raw_mant_NRM_SWR[6]), .A1N(
n1389), .Y(n1346) );
AOI21X1TS U1605 ( .A0(n936), .A1(Data_array_SWR[15]), .B0(n1346), .Y(n1347)
);
OAI21XLTS U1606 ( .A0(n1448), .A1(n1457), .B0(n1347), .Y(n848) );
AOI22X1TS U1607 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n1439), .B0(n1449), .B1(
n1009), .Y(n1349) );
AOI22X1TS U1608 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n938), .B0(n1450), .B1(n998), .Y(n1348) );
NAND2X1TS U1609 ( .A(n1349), .B(n1348), .Y(n1398) );
AOI22X1TS U1610 ( .A0(n936), .A1(Data_array_SWR[6]), .B0(n1350), .B1(n1398),
.Y(n1352) );
NAND2X1TS U1611 ( .A(Raw_mant_NRM_SWR[16]), .B(n1389), .Y(n1351) );
OAI211XLTS U1612 ( .A0(n1366), .A1(n1327), .B0(n1352), .C0(n1351), .Y(n838)
);
AOI22X1TS U1613 ( .A0(n936), .A1(n1018), .B0(Raw_mant_NRM_SWR[1]), .B1(n1389), .Y(n1355) );
NAND2X2TS U1614 ( .A(n1353), .B(n1439), .Y(n1374) );
OA22X1TS U1615 ( .A0(n1683), .A1(n1374), .B0(n1375), .B1(n1327), .Y(n1354)
);
OAI211XLTS U1616 ( .A0(n1382), .A1(n1457), .B0(n1355), .C0(n1354), .Y(n853)
);
AOI22X1TS U1617 ( .A0(n936), .A1(Data_array_SWR[12]), .B0(
Raw_mant_NRM_SWR[9]), .B1(n1389), .Y(n1357) );
OA22X1TS U1618 ( .A0(n1646), .A1(n1374), .B0(n1360), .B1(n1327), .Y(n1356)
);
OAI211XLTS U1619 ( .A0(n1386), .A1(n1457), .B0(n1357), .C0(n1356), .Y(n845)
);
AOI22X1TS U1620 ( .A0(n936), .A1(Data_array_SWR[14]), .B0(
Raw_mant_NRM_SWR[7]), .B1(n1389), .Y(n1359) );
OA22X1TS U1621 ( .A0(n1649), .A1(n1374), .B0(n1363), .B1(n1327), .Y(n1358)
);
OAI211XLTS U1622 ( .A0(n1360), .A1(n1457), .B0(n1359), .C0(n1358), .Y(n847)
);
AOI22X1TS U1623 ( .A0(n936), .A1(n1019), .B0(Raw_mant_NRM_SWR[5]), .B1(n1389), .Y(n1362) );
OA22X1TS U1624 ( .A0(n1633), .A1(n1374), .B0(n1385), .B1(n1327), .Y(n1361)
);
OAI211XLTS U1625 ( .A0(n1363), .A1(n1457), .B0(n1362), .C0(n1361), .Y(n849)
);
AOI22X1TS U1626 ( .A0(n1450), .A1(n1007), .B0(n1449), .B1(n1001), .Y(n1364)
);
OAI21XLTS U1627 ( .A0(n1625), .A1(n1452), .B0(n1364), .Y(n1365) );
AOI21X1TS U1628 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n938), .B0(n1365), .Y(n1456) );
OAI22X1TS U1629 ( .A0(n1366), .A1(n1457), .B0(n1631), .B1(n1374), .Y(n1367)
);
AOI21X1TS U1630 ( .A0(n936), .A1(Data_array_SWR[8]), .B0(n1367), .Y(n1368)
);
OAI21XLTS U1631 ( .A0(n1456), .A1(n1327), .B0(n1368), .Y(n840) );
AOI22X1TS U1632 ( .A0(n1450), .A1(n1008), .B0(n1449), .B1(n999), .Y(n1369)
);
OAI21XLTS U1633 ( .A0(n1634), .A1(n1452), .B0(n1369), .Y(n1370) );
AOI21X1TS U1634 ( .A0(Raw_mant_NRM_SWR[5]), .A1(n938), .B0(n1370), .Y(n1444)
);
OAI22X1TS U1635 ( .A0(n1371), .A1(n1457), .B0(n1650), .B1(n1374), .Y(n1372)
);
AOI21X1TS U1636 ( .A0(n936), .A1(Data_array_SWR[16]), .B0(n1372), .Y(n1373)
);
OAI21XLTS U1637 ( .A0(n1444), .A1(n1327), .B0(n1373), .Y(n850) );
AOI21X1TS U1638 ( .A0(n938), .A1(n1017), .B0(n1450), .Y(n1436) );
INVX2TS U1639 ( .A(n1374), .Y(n1459) );
OAI2BB2XLTS U1640 ( .B0(n1375), .B1(n1457), .A0N(n936), .A1N(
Data_array_SWR[20]), .Y(n1376) );
AOI21X1TS U1641 ( .A0(Raw_mant_NRM_SWR[1]), .A1(n1459), .B0(n1376), .Y(n1377) );
OAI21XLTS U1642 ( .A0(n1436), .A1(n1327), .B0(n1377), .Y(n855) );
AOI22X1TS U1643 ( .A0(Raw_mant_NRM_SWR[24]), .A1(n938), .B0(n1449), .B1(
n1011), .Y(n1381) );
AOI22X1TS U1644 ( .A0(n936), .A1(Data_array_SWR[1]), .B0(
Raw_mant_NRM_SWR[23]), .B1(n1459), .Y(n1380) );
NAND2X1TS U1645 ( .A(n1461), .B(n1378), .Y(n1379) );
OAI211XLTS U1646 ( .A0(n1381), .A1(n1457), .B0(n1380), .C0(n1379), .Y(n833)
);
AOI22X1TS U1647 ( .A0(n936), .A1(Data_array_SWR[17]), .B0(
Raw_mant_NRM_SWR[3]), .B1(n1389), .Y(n1384) );
AOI2BB2XLTS U1648 ( .B0(Raw_mant_NRM_SWR[5]), .B1(n1459), .A0N(n1382), .A1N(
n1327), .Y(n1383) );
OAI211XLTS U1649 ( .A0(n1385), .A1(n1457), .B0(n1384), .C0(n1383), .Y(n851)
);
AOI22X1TS U1650 ( .A0(n936), .A1(n1020), .B0(Raw_mant_NRM_SWR[11]), .B1(
n1389), .Y(n1388) );
AOI2BB2XLTS U1651 ( .B0(Raw_mant_NRM_SWR[13]), .B1(n1459), .A0N(n1386),
.A1N(n1327), .Y(n1387) );
OAI211XLTS U1652 ( .A0(n1390), .A1(n1457), .B0(n1388), .C0(n1387), .Y(n843)
);
AOI22X1TS U1653 ( .A0(n936), .A1(Data_array_SWR[9]), .B0(
Raw_mant_NRM_SWR[13]), .B1(n1389), .Y(n1392) );
AOI2BB2XLTS U1654 ( .B0(Raw_mant_NRM_SWR[15]), .B1(n1459), .A0N(n1390),
.A1N(n1327), .Y(n1391) );
OAI211XLTS U1655 ( .A0(n1393), .A1(n1457), .B0(n1392), .C0(n1391), .Y(n841)
);
AOI22X1TS U1656 ( .A0(n936), .A1(Data_array_SWR[5]), .B0(n1461), .B1(n1394),
.Y(n1396) );
NAND2X1TS U1657 ( .A(Raw_mant_NRM_SWR[19]), .B(n1459), .Y(n1395) );
AOI22X1TS U1658 ( .A0(n936), .A1(Data_array_SWR[4]), .B0(n1461), .B1(n1398),
.Y(n1400) );
NAND2X1TS U1659 ( .A(Raw_mant_NRM_SWR[20]), .B(n1459), .Y(n1399) );
OAI211XLTS U1660 ( .A0(n1401), .A1(n1457), .B0(n1400), .C0(n1399), .Y(n836)
);
OAI2BB2XLTS U1661 ( .B0(n1415), .B1(n1402), .A0N(final_result_ieee[30]),
.A1N(n1715), .Y(n815) );
NOR2XLTS U1662 ( .A(n1403), .B(SIGN_FLAG_SHT1SHT2), .Y(n1404) );
OAI2BB2XLTS U1663 ( .B0(n1404), .B1(n1415), .A0N(n1715), .A1N(
final_result_ieee[31]), .Y(n604) );
INVX2TS U1664 ( .A(n1405), .Y(n1406) );
NAND2X1TS U1665 ( .A(n1654), .B(n1406), .Y(DP_OP_15J41_125_2314_n8) );
MX2X1TS U1666 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n672) );
MX2X1TS U1667 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n677) );
MX2X1TS U1668 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n682) );
MX2X1TS U1669 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n687) );
MX2X1TS U1670 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n692) );
MX2X1TS U1671 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n697) );
MX2X1TS U1672 ( .A(DMP_exp_NRM2_EW[1]), .B(DMP_exp_NRM_EW[1]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n702) );
MX2X1TS U1673 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n707) );
AO21XLTS U1674 ( .A0(LZD_output_NRM2_EW[4]), .A1(n933), .B0(n1408), .Y(n587)
);
OAI2BB1X1TS U1675 ( .A0N(LZD_output_NRM2_EW[3]), .A1N(n933), .B0(n1409), .Y(
n573) );
OAI2BB1X1TS U1676 ( .A0N(LZD_output_NRM2_EW[2]), .A1N(n933), .B0(n1410), .Y(
n584) );
OAI2BB1X1TS U1677 ( .A0N(LZD_output_NRM2_EW[0]), .A1N(n933), .B0(n1452), .Y(
n579) );
NAND2X2TS U1678 ( .A(n1470), .B(Shift_reg_FLAGS_7[0]), .Y(n1414) );
OA22X1TS U1679 ( .A0(n1414), .A1(n1411), .B0(final_result_ieee[23]), .B1(
Shift_reg_FLAGS_7[0]), .Y(n822) );
OA22X1TS U1680 ( .A0(n1414), .A1(exp_rslt_NRM2_EW1[1]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[24]), .Y(n821) );
OA22X1TS U1681 ( .A0(n1414), .A1(exp_rslt_NRM2_EW1[2]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[25]), .Y(n820) );
OA22X1TS U1682 ( .A0(n1414), .A1(exp_rslt_NRM2_EW1[3]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[26]), .Y(n819) );
OA22X1TS U1683 ( .A0(n1414), .A1(exp_rslt_NRM2_EW1[4]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[27]), .Y(n818) );
OA22X1TS U1684 ( .A0(n1414), .A1(n1412), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[28]), .Y(n817) );
OA22X1TS U1685 ( .A0(n1414), .A1(n1413), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[29]), .Y(n816) );
OA21XLTS U1686 ( .A0(Shift_reg_FLAGS_7[0]), .A1(overflow_flag), .B0(n1415),
.Y(n619) );
INVX2TS U1687 ( .A(n1416), .Y(n1418) );
AOI22X1TS U1688 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n1418), .B1(n1659), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
NAND2X1TS U1689 ( .A(n1418), .B(n1417), .Y(n932) );
AOI22X1TS U1690 ( .A0(n1421), .A1(n1419), .B0(n1475), .B1(n1420), .Y(n929)
);
AOI22X1TS U1691 ( .A0(n1421), .A1(n1475), .B0(n934), .B1(n1420), .Y(n928) );
OAI2BB2XLTS U1692 ( .B0(n1420), .B1(n934), .A0N(n1420), .A1N(n996), .Y(n927)
);
AOI22X1TS U1693 ( .A0(n1421), .A1(n1716), .B0(n933), .B1(n1420), .Y(n925) );
INVX4TS U1694 ( .A(n1423), .Y(n1432) );
INVX4TS U1695 ( .A(n1423), .Y(n1435) );
AO22XLTS U1696 ( .A0(n1435), .A1(Data_X[4]), .B0(n1423), .B1(intDX_EWSW[4]),
.Y(n919) );
INVX4TS U1697 ( .A(n1423), .Y(n1433) );
AO22XLTS U1698 ( .A0(n1433), .A1(Data_X[5]), .B0(n1423), .B1(intDX_EWSW[5]),
.Y(n918) );
AO22XLTS U1699 ( .A0(n1435), .A1(Data_X[6]), .B0(n1423), .B1(intDX_EWSW[6]),
.Y(n917) );
AO22XLTS U1700 ( .A0(n1435), .A1(Data_X[7]), .B0(n1423), .B1(intDX_EWSW[7]),
.Y(n916) );
AO22XLTS U1701 ( .A0(n1435), .A1(Data_X[16]), .B0(n1423), .B1(intDX_EWSW[16]), .Y(n907) );
AO22XLTS U1702 ( .A0(n1432), .A1(Data_X[21]), .B0(n1434), .B1(intDX_EWSW[21]), .Y(n902) );
AO22XLTS U1703 ( .A0(n1433), .A1(Data_X[23]), .B0(n1434), .B1(intDX_EWSW[23]), .Y(n900) );
INVX4TS U1704 ( .A(n1423), .Y(n1429) );
OAI2BB2XLTS U1705 ( .B0(n1429), .B1(n1687), .A0N(n1430), .A1N(Data_X[24]),
.Y(n899) );
OAI2BB2XLTS U1706 ( .B0(n1433), .B1(n1643), .A0N(n1430), .A1N(Data_X[25]),
.Y(n898) );
INVX4TS U1707 ( .A(n1423), .Y(n1431) );
OAI2BB2XLTS U1708 ( .B0(n1433), .B1(n1644), .A0N(n1431), .A1N(Data_X[26]),
.Y(n897) );
OAI2BB2XLTS U1709 ( .B0(n1433), .B1(n1677), .A0N(n1430), .A1N(Data_X[28]),
.Y(n895) );
OAI2BB2XLTS U1710 ( .B0(n1433), .B1(n1679), .A0N(n1429), .A1N(Data_X[29]),
.Y(n894) );
OAI2BB2XLTS U1711 ( .B0(n1433), .B1(n1641), .A0N(n1435), .A1N(Data_X[30]),
.Y(n893) );
AO22XLTS U1712 ( .A0(n1432), .A1(add_subt), .B0(n1434), .B1(intAS), .Y(n891)
);
OAI2BB2XLTS U1713 ( .B0(n1433), .B1(n1671), .A0N(n1431), .A1N(Data_Y[0]),
.Y(n889) );
OAI2BB2XLTS U1714 ( .B0(n1433), .B1(n1675), .A0N(n1432), .A1N(Data_Y[1]),
.Y(n888) );
OAI2BB2XLTS U1715 ( .B0(n1433), .B1(n1663), .A0N(n1431), .A1N(Data_Y[2]),
.Y(n887) );
OAI2BB2XLTS U1716 ( .B0(n1433), .B1(n1672), .A0N(n1429), .A1N(Data_Y[3]),
.Y(n886) );
OAI2BB2XLTS U1717 ( .B0(n1429), .B1(n1664), .A0N(n1429), .A1N(Data_Y[4]),
.Y(n885) );
OAI2BB2XLTS U1718 ( .B0(n1429), .B1(n1639), .A0N(n1431), .A1N(Data_Y[5]),
.Y(n884) );
OAI2BB2XLTS U1719 ( .B0(n1433), .B1(n1425), .A0N(n1435), .A1N(Data_Y[6]),
.Y(n883) );
OAI2BB2XLTS U1720 ( .B0(n1429), .B1(n1668), .A0N(n1430), .A1N(Data_Y[7]),
.Y(n882) );
OAI2BB2XLTS U1721 ( .B0(n1431), .B1(n1676), .A0N(n1429), .A1N(Data_Y[8]),
.Y(n881) );
OAI2BB2XLTS U1722 ( .B0(n1429), .B1(n1426), .A0N(n1430), .A1N(Data_Y[9]),
.Y(n880) );
OAI2BB2XLTS U1723 ( .B0(n1429), .B1(n1427), .A0N(n1430), .A1N(Data_Y[10]),
.Y(n879) );
OAI2BB2XLTS U1724 ( .B0(n1429), .B1(n1696), .A0N(n1430), .A1N(Data_Y[11]),
.Y(n878) );
OAI2BB2XLTS U1725 ( .B0(n1429), .B1(n1665), .A0N(n1430), .A1N(Data_Y[12]),
.Y(n877) );
OAI2BB2XLTS U1726 ( .B0(n1429), .B1(n1695), .A0N(n1432), .A1N(Data_Y[13]),
.Y(n876) );
OAI2BB2XLTS U1727 ( .B0(n1429), .B1(n1694), .A0N(n1431), .A1N(Data_Y[14]),
.Y(n875) );
OAI2BB2XLTS U1728 ( .B0(n1431), .B1(n1673), .A0N(n1435), .A1N(Data_Y[15]),
.Y(n874) );
OAI2BB2XLTS U1729 ( .B0(n1429), .B1(n1428), .A0N(n1430), .A1N(Data_Y[16]),
.Y(n873) );
OAI2BB2XLTS U1730 ( .B0(n1429), .B1(n1674), .A0N(n1432), .A1N(Data_Y[17]),
.Y(n872) );
OAI2BB2XLTS U1731 ( .B0(n1431), .B1(n1698), .A0N(n1435), .A1N(Data_Y[18]),
.Y(n871) );
OAI2BB2XLTS U1732 ( .B0(n1431), .B1(n1680), .A0N(n1429), .A1N(Data_Y[19]),
.Y(n870) );
OAI2BB2XLTS U1733 ( .B0(n1431), .B1(n1015), .A0N(n1432), .A1N(Data_Y[20]),
.Y(n869) );
OAI2BB2XLTS U1734 ( .B0(n1431), .B1(n1718), .A0N(n1435), .A1N(Data_Y[21]),
.Y(n868) );
OAI2BB2XLTS U1735 ( .B0(n1431), .B1(n1697), .A0N(n1430), .A1N(Data_Y[22]),
.Y(n867) );
OAI2BB2XLTS U1736 ( .B0(n1431), .B1(n1678), .A0N(n1432), .A1N(Data_Y[23]),
.Y(n866) );
OAI2BB2XLTS U1737 ( .B0(n1431), .B1(n964), .A0N(n1430), .A1N(Data_Y[24]),
.Y(n865) );
OAI2BB2XLTS U1738 ( .B0(n1431), .B1(n1670), .A0N(n1430), .A1N(Data_Y[25]),
.Y(n864) );
OAI2BB2XLTS U1739 ( .B0(n1431), .B1(n1016), .A0N(n1430), .A1N(Data_Y[26]),
.Y(n863) );
OAI2BB2XLTS U1740 ( .B0(n1431), .B1(n1667), .A0N(n1430), .A1N(Data_Y[27]),
.Y(n862) );
AO22XLTS U1741 ( .A0(n1433), .A1(Data_Y[29]), .B0(n1434), .B1(intDY_EWSW[29]), .Y(n860) );
AO22XLTS U1742 ( .A0(n1435), .A1(Data_Y[30]), .B0(n1434), .B1(intDY_EWSW[30]), .Y(n859) );
AO22XLTS U1743 ( .A0(n1435), .A1(Data_Y[31]), .B0(n1434), .B1(intDY_EWSW[31]), .Y(n858) );
OAI2BB2XLTS U1744 ( .B0(n1436), .B1(n1457), .A0N(n936), .A1N(
Data_array_SWR[22]), .Y(n857) );
AO22XLTS U1745 ( .A0(Raw_mant_NRM_SWR[1]), .A1(n938), .B0(n1017), .B1(n1439),
.Y(n1437) );
OAI2BB2XLTS U1746 ( .B0(n1443), .B1(n1457), .A0N(n936), .A1N(
Data_array_SWR[21]), .Y(n856) );
AOI22X1TS U1747 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n1439), .B0(n1006), .B1(
n1449), .Y(n1440) );
OAI21XLTS U1748 ( .A0(n1683), .A1(n1441), .B0(n1440), .Y(n1442) );
AOI21X1TS U1749 ( .A0(n1003), .A1(n1450), .B0(n1442), .Y(n1445) );
OAI222X1TS U1750 ( .A0(n1455), .A1(n1684), .B0(n1327), .B1(n1443), .C0(n1457), .C1(n1445), .Y(n854) );
OAI222X1TS U1751 ( .A0(n1693), .A1(n1455), .B0(n1327), .B1(n1445), .C0(n1457), .C1(n1444), .Y(n852) );
AOI22X1TS U1752 ( .A0(n1450), .A1(DmP_mant_SHT1_SW[12]), .B0(n1449), .B1(
n1005), .Y(n1446) );
OAI21XLTS U1753 ( .A0(n1647), .A1(n1452), .B0(n1446), .Y(n1447) );
AOI21X1TS U1754 ( .A0(Raw_mant_NRM_SWR[11]), .A1(n938), .B0(n1447), .Y(n1454) );
OAI222X1TS U1755 ( .A0(n1690), .A1(n1455), .B0(n1327), .B1(n1448), .C0(n1457), .C1(n1454), .Y(n846) );
AOI22X1TS U1756 ( .A0(n1450), .A1(DmP_mant_SHT1_SW[10]), .B0(n1449), .B1(
n1000), .Y(n1451) );
OAI21XLTS U1757 ( .A0(n1626), .A1(n1452), .B0(n1451), .Y(n1453) );
AOI21X1TS U1758 ( .A0(Raw_mant_NRM_SWR[13]), .A1(n938), .B0(n1453), .Y(n1458) );
OAI222X1TS U1759 ( .A0(n1689), .A1(n1455), .B0(n1327), .B1(n1454), .C0(n1457), .C1(n1458), .Y(n844) );
OAI222X1TS U1760 ( .A0(n1692), .A1(n1455), .B0(n1327), .B1(n1458), .C0(n1457), .C1(n1456), .Y(n842) );
AOI22X1TS U1761 ( .A0(n936), .A1(Data_array_SWR[0]), .B0(
Raw_mant_NRM_SWR[24]), .B1(n1459), .Y(n1463) );
AOI22X1TS U1762 ( .A0(Raw_mant_NRM_SWR[25]), .A1(n938), .B0(n1461), .B1(
n1460), .Y(n1462) );
NAND2X1TS U1763 ( .A(n1463), .B(n1462), .Y(n832) );
AOI21X1TS U1764 ( .A0(DMP_EXP_EWSW[23]), .A1(n1033), .B0(n1464), .Y(n1465)
);
AOI2BB2XLTS U1765 ( .B0(n1467), .B1(n1465), .A0N(Shift_amount_SHT1_EWR[0]),
.A1N(n1467), .Y(n827) );
OAI222X1TS U1766 ( .A0(n1468), .A1(n1687), .B0(n1630), .B1(
Shift_reg_FLAGS_7_6), .C0(n1013), .C1(n1469), .Y(n790) );
OAI222X1TS U1767 ( .A0(n935), .A1(n1643), .B0(n1682), .B1(
Shift_reg_FLAGS_7_6), .C0(n1670), .C1(n1469), .Y(n789) );
OAI222X1TS U1768 ( .A0(n1468), .A1(n1644), .B0(n1688), .B1(
Shift_reg_FLAGS_7_6), .C0(n1016), .C1(n1469), .Y(n788) );
AO22XLTS U1769 ( .A0(n1476), .A1(DMP_EXP_EWSW[0]), .B0(n1478), .B1(
DMP_SHT1_EWSW[0]), .Y(n780) );
AO22XLTS U1770 ( .A0(n1480), .A1(DMP_SHT1_EWSW[0]), .B0(n934), .B1(
DMP_SHT2_EWSW[0]), .Y(n779) );
AO22XLTS U1771 ( .A0(n1479), .A1(DMP_EXP_EWSW[1]), .B0(n1478), .B1(
DMP_SHT1_EWSW[1]), .Y(n777) );
AO22XLTS U1772 ( .A0(busy), .A1(DMP_SHT1_EWSW[1]), .B0(n934), .B1(
DMP_SHT2_EWSW[1]), .Y(n776) );
AO22XLTS U1773 ( .A0(n1467), .A1(DMP_EXP_EWSW[2]), .B0(n1472), .B1(
DMP_SHT1_EWSW[2]), .Y(n774) );
AO22XLTS U1774 ( .A0(busy), .A1(DMP_SHT1_EWSW[2]), .B0(n934), .B1(
DMP_SHT2_EWSW[2]), .Y(n773) );
AO22XLTS U1775 ( .A0(n1467), .A1(DMP_EXP_EWSW[3]), .B0(n1472), .B1(
DMP_SHT1_EWSW[3]), .Y(n771) );
AO22XLTS U1776 ( .A0(busy), .A1(DMP_SHT1_EWSW[3]), .B0(n934), .B1(
DMP_SHT2_EWSW[3]), .Y(n770) );
AO22XLTS U1777 ( .A0(n1467), .A1(DMP_EXP_EWSW[4]), .B0(n1472), .B1(
DMP_SHT1_EWSW[4]), .Y(n768) );
AO22XLTS U1778 ( .A0(busy), .A1(DMP_SHT1_EWSW[4]), .B0(n934), .B1(
DMP_SHT2_EWSW[4]), .Y(n767) );
AO22XLTS U1779 ( .A0(n1467), .A1(DMP_EXP_EWSW[5]), .B0(n1472), .B1(
DMP_SHT1_EWSW[5]), .Y(n765) );
AO22XLTS U1780 ( .A0(busy), .A1(DMP_SHT1_EWSW[5]), .B0(n934), .B1(
DMP_SHT2_EWSW[5]), .Y(n764) );
AO22XLTS U1781 ( .A0(n1479), .A1(DMP_EXP_EWSW[6]), .B0(n1472), .B1(
DMP_SHT1_EWSW[6]), .Y(n762) );
AO22XLTS U1782 ( .A0(busy), .A1(DMP_SHT1_EWSW[6]), .B0(n934), .B1(
DMP_SHT2_EWSW[6]), .Y(n761) );
AO22XLTS U1783 ( .A0(n1616), .A1(DMP_SHT2_EWSW[6]), .B0(n1620), .B1(
DMP_SFG[6]), .Y(n760) );
AO22XLTS U1784 ( .A0(n1476), .A1(DMP_EXP_EWSW[7]), .B0(n1472), .B1(
DMP_SHT1_EWSW[7]), .Y(n759) );
AO22XLTS U1785 ( .A0(busy), .A1(DMP_SHT1_EWSW[7]), .B0(n934), .B1(
DMP_SHT2_EWSW[7]), .Y(n758) );
BUFX3TS U1786 ( .A(Shift_reg_FLAGS_7_5), .Y(n1479) );
AO22XLTS U1787 ( .A0(n1476), .A1(DMP_EXP_EWSW[8]), .B0(n1472), .B1(
DMP_SHT1_EWSW[8]), .Y(n756) );
AO22XLTS U1788 ( .A0(busy), .A1(DMP_SHT1_EWSW[8]), .B0(n934), .B1(
DMP_SHT2_EWSW[8]), .Y(n755) );
AO22XLTS U1789 ( .A0(n1473), .A1(DMP_EXP_EWSW[9]), .B0(n1472), .B1(
DMP_SHT1_EWSW[9]), .Y(n753) );
AO22XLTS U1790 ( .A0(busy), .A1(DMP_SHT1_EWSW[9]), .B0(n934), .B1(
DMP_SHT2_EWSW[9]), .Y(n752) );
AO22XLTS U1791 ( .A0(n1479), .A1(DMP_EXP_EWSW[10]), .B0(n1472), .B1(
DMP_SHT1_EWSW[10]), .Y(n750) );
BUFX4TS U1792 ( .A(n934), .Y(n1474) );
AO22XLTS U1793 ( .A0(busy), .A1(DMP_SHT1_EWSW[10]), .B0(n1474), .B1(
DMP_SHT2_EWSW[10]), .Y(n749) );
OAI2BB2XLTS U1794 ( .B0(n1622), .B1(intadd_46_A_0_), .A0N(n1622), .A1N(
DMP_SHT2_EWSW[10]), .Y(n748) );
AO22XLTS U1795 ( .A0(n1479), .A1(DMP_EXP_EWSW[11]), .B0(n1472), .B1(
DMP_SHT1_EWSW[11]), .Y(n747) );
AO22XLTS U1796 ( .A0(n1480), .A1(DMP_SHT1_EWSW[11]), .B0(n1474), .B1(
DMP_SHT2_EWSW[11]), .Y(n746) );
OAI2BB2XLTS U1797 ( .B0(n1622), .B1(n1029), .A0N(n1604), .A1N(
DMP_SHT2_EWSW[11]), .Y(n745) );
AO22XLTS U1798 ( .A0(n1479), .A1(DMP_EXP_EWSW[12]), .B0(n1472), .B1(
DMP_SHT1_EWSW[12]), .Y(n744) );
AO22XLTS U1799 ( .A0(n1480), .A1(DMP_SHT1_EWSW[12]), .B0(n1474), .B1(
DMP_SHT2_EWSW[12]), .Y(n743) );
OAI2BB2XLTS U1800 ( .B0(n1604), .B1(intadd_46_A_2_), .A0N(n1616), .A1N(
DMP_SHT2_EWSW[12]), .Y(n742) );
AO22XLTS U1801 ( .A0(n1473), .A1(DMP_EXP_EWSW[13]), .B0(n1472), .B1(
DMP_SHT1_EWSW[13]), .Y(n741) );
AO22XLTS U1802 ( .A0(n1480), .A1(DMP_SHT1_EWSW[13]), .B0(n1474), .B1(
DMP_SHT2_EWSW[13]), .Y(n740) );
OAI2BB2XLTS U1803 ( .B0(n1622), .B1(intadd_46_A_3_), .A0N(n1604), .A1N(
DMP_SHT2_EWSW[13]), .Y(n739) );
AO22XLTS U1804 ( .A0(n1479), .A1(DMP_EXP_EWSW[14]), .B0(n1472), .B1(
DMP_SHT1_EWSW[14]), .Y(n738) );
AO22XLTS U1805 ( .A0(n1480), .A1(DMP_SHT1_EWSW[14]), .B0(n1474), .B1(
DMP_SHT2_EWSW[14]), .Y(n737) );
OAI2BB2XLTS U1806 ( .B0(n1604), .B1(intadd_46_A_4_), .A0N(n1477), .A1N(
DMP_SHT2_EWSW[14]), .Y(n736) );
AO22XLTS U1807 ( .A0(n1473), .A1(DMP_EXP_EWSW[15]), .B0(n1472), .B1(
DMP_SHT1_EWSW[15]), .Y(n735) );
AO22XLTS U1808 ( .A0(n1480), .A1(DMP_SHT1_EWSW[15]), .B0(n1474), .B1(
DMP_SHT2_EWSW[15]), .Y(n734) );
OAI2BB2XLTS U1809 ( .B0(n1616), .B1(intadd_46_A_5_), .A0N(n1604), .A1N(
DMP_SHT2_EWSW[15]), .Y(n733) );
AO22XLTS U1810 ( .A0(n1476), .A1(DMP_EXP_EWSW[16]), .B0(n1472), .B1(
DMP_SHT1_EWSW[16]), .Y(n732) );
AO22XLTS U1811 ( .A0(n1480), .A1(DMP_SHT1_EWSW[16]), .B0(n1474), .B1(
DMP_SHT2_EWSW[16]), .Y(n731) );
OAI2BB2XLTS U1812 ( .B0(n1477), .B1(intadd_46_A_6_), .A0N(n1477), .A1N(
DMP_SHT2_EWSW[16]), .Y(n730) );
AO22XLTS U1813 ( .A0(n1473), .A1(DMP_EXP_EWSW[17]), .B0(n1478), .B1(
DMP_SHT1_EWSW[17]), .Y(n729) );
AO22XLTS U1814 ( .A0(n1480), .A1(DMP_SHT1_EWSW[17]), .B0(n1474), .B1(
DMP_SHT2_EWSW[17]), .Y(n728) );
OAI2BB2XLTS U1815 ( .B0(n1616), .B1(intadd_46_A_7_), .A0N(n1622), .A1N(
DMP_SHT2_EWSW[17]), .Y(n727) );
AO22XLTS U1816 ( .A0(n1476), .A1(DMP_EXP_EWSW[18]), .B0(n1472), .B1(
DMP_SHT1_EWSW[18]), .Y(n726) );
AO22XLTS U1817 ( .A0(n1480), .A1(DMP_SHT1_EWSW[18]), .B0(n1474), .B1(
DMP_SHT2_EWSW[18]), .Y(n725) );
OAI2BB2XLTS U1818 ( .B0(n1477), .B1(intadd_46_A_8_), .A0N(n1616), .A1N(
DMP_SHT2_EWSW[18]), .Y(n724) );
AO22XLTS U1819 ( .A0(n1473), .A1(DMP_EXP_EWSW[19]), .B0(n1478), .B1(
DMP_SHT1_EWSW[19]), .Y(n723) );
AO22XLTS U1820 ( .A0(n1480), .A1(DMP_SHT1_EWSW[19]), .B0(n1474), .B1(
DMP_SHT2_EWSW[19]), .Y(n722) );
OAI2BB2XLTS U1821 ( .B0(n1622), .B1(intadd_46_A_9_), .A0N(n1622), .A1N(
DMP_SHT2_EWSW[19]), .Y(n721) );
AO22XLTS U1822 ( .A0(n1479), .A1(DMP_EXP_EWSW[20]), .B0(n1478), .B1(
DMP_SHT1_EWSW[20]), .Y(n720) );
AO22XLTS U1823 ( .A0(n1480), .A1(DMP_SHT1_EWSW[20]), .B0(n1474), .B1(
DMP_SHT2_EWSW[20]), .Y(n719) );
OAI2BB2XLTS U1824 ( .B0(n1604), .B1(intadd_46_A_10_), .A0N(n1616), .A1N(
DMP_SHT2_EWSW[20]), .Y(n718) );
AO22XLTS U1825 ( .A0(n1476), .A1(DMP_EXP_EWSW[21]), .B0(n1478), .B1(
DMP_SHT1_EWSW[21]), .Y(n717) );
AO22XLTS U1826 ( .A0(busy), .A1(DMP_SHT1_EWSW[21]), .B0(n1474), .B1(
DMP_SHT2_EWSW[21]), .Y(n716) );
OAI2BB2XLTS U1827 ( .B0(n1616), .B1(intadd_46_A_11_), .A0N(n1604), .A1N(
DMP_SHT2_EWSW[21]), .Y(n715) );
AO22XLTS U1828 ( .A0(n1473), .A1(DMP_EXP_EWSW[22]), .B0(n1478), .B1(
DMP_SHT1_EWSW[22]), .Y(n714) );
AO22XLTS U1829 ( .A0(busy), .A1(DMP_SHT1_EWSW[22]), .B0(n1474), .B1(
DMP_SHT2_EWSW[22]), .Y(n713) );
OAI2BB2XLTS U1830 ( .B0(n1477), .B1(intadd_46_A_12_), .A0N(n1616), .A1N(
DMP_SHT2_EWSW[22]), .Y(n712) );
AO22XLTS U1831 ( .A0(n1479), .A1(DMP_EXP_EWSW[23]), .B0(n1478), .B1(
DMP_SHT1_EWSW[23]), .Y(n711) );
AO22XLTS U1832 ( .A0(busy), .A1(DMP_SHT1_EWSW[23]), .B0(n1474), .B1(
DMP_SHT2_EWSW[23]), .Y(n710) );
AO22XLTS U1833 ( .A0(n1477), .A1(DMP_SHT2_EWSW[23]), .B0(n1466), .B1(
DMP_SFG[23]), .Y(n709) );
AO22XLTS U1834 ( .A0(n973), .A1(DMP_SFG[23]), .B0(n1563), .B1(
DMP_exp_NRM_EW[0]), .Y(n708) );
OAI2BB2XLTS U1835 ( .B0(n1475), .B1(n1630), .A0N(n1478), .A1N(
DMP_SHT1_EWSW[24]), .Y(n706) );
AO22XLTS U1836 ( .A0(n1480), .A1(DMP_SHT1_EWSW[24]), .B0(n934), .B1(
DMP_SHT2_EWSW[24]), .Y(n705) );
AO22XLTS U1837 ( .A0(n1477), .A1(DMP_SHT2_EWSW[24]), .B0(n1593), .B1(
DMP_SFG[24]), .Y(n704) );
AO22XLTS U1838 ( .A0(n1565), .A1(DMP_SFG[24]), .B0(n1563), .B1(
DMP_exp_NRM_EW[1]), .Y(n703) );
OAI2BB2XLTS U1839 ( .B0(n1475), .B1(n1682), .A0N(n1478), .A1N(
DMP_SHT1_EWSW[25]), .Y(n701) );
AO22XLTS U1840 ( .A0(n1480), .A1(DMP_SHT1_EWSW[25]), .B0(n934), .B1(
DMP_SHT2_EWSW[25]), .Y(n700) );
AO22XLTS U1841 ( .A0(n1477), .A1(DMP_SHT2_EWSW[25]), .B0(n1620), .B1(
DMP_SFG[25]), .Y(n699) );
AO22XLTS U1842 ( .A0(n1565), .A1(DMP_SFG[25]), .B0(n1563), .B1(
DMP_exp_NRM_EW[2]), .Y(n698) );
OAI2BB2XLTS U1843 ( .B0(n1475), .B1(n1688), .A0N(n1478), .A1N(
DMP_SHT1_EWSW[26]), .Y(n696) );
AO22XLTS U1844 ( .A0(busy), .A1(DMP_SHT1_EWSW[26]), .B0(n1474), .B1(
DMP_SHT2_EWSW[26]), .Y(n695) );
AO22XLTS U1845 ( .A0(n1616), .A1(DMP_SHT2_EWSW[26]), .B0(n1466), .B1(
DMP_SFG[26]), .Y(n694) );
AO22XLTS U1846 ( .A0(n973), .A1(DMP_SFG[26]), .B0(n1563), .B1(
DMP_exp_NRM_EW[3]), .Y(n693) );
AO22XLTS U1847 ( .A0(n1476), .A1(n1012), .B0(n1478), .B1(DMP_SHT1_EWSW[27]),
.Y(n691) );
AO22XLTS U1848 ( .A0(n1480), .A1(DMP_SHT1_EWSW[27]), .B0(n1474), .B1(
DMP_SHT2_EWSW[27]), .Y(n690) );
AO22XLTS U1849 ( .A0(n1604), .A1(DMP_SHT2_EWSW[27]), .B0(n1466), .B1(
DMP_SFG[27]), .Y(n689) );
AO22XLTS U1850 ( .A0(n1565), .A1(DMP_SFG[27]), .B0(n1563), .B1(
DMP_exp_NRM_EW[4]), .Y(n688) );
AO22XLTS U1851 ( .A0(n1473), .A1(DMP_EXP_EWSW[28]), .B0(n1478), .B1(
DMP_SHT1_EWSW[28]), .Y(n686) );
AO22XLTS U1852 ( .A0(n1480), .A1(DMP_SHT1_EWSW[28]), .B0(n1474), .B1(
DMP_SHT2_EWSW[28]), .Y(n685) );
AO22XLTS U1853 ( .A0(n1622), .A1(DMP_SHT2_EWSW[28]), .B0(n1620), .B1(
DMP_SFG[28]), .Y(n684) );
AO22XLTS U1854 ( .A0(n973), .A1(DMP_SFG[28]), .B0(n1563), .B1(
DMP_exp_NRM_EW[5]), .Y(n683) );
AO22XLTS U1855 ( .A0(n1479), .A1(DMP_EXP_EWSW[29]), .B0(n1478), .B1(
DMP_SHT1_EWSW[29]), .Y(n681) );
AO22XLTS U1856 ( .A0(n1480), .A1(DMP_SHT1_EWSW[29]), .B0(n1474), .B1(
DMP_SHT2_EWSW[29]), .Y(n680) );
AO22XLTS U1857 ( .A0(n1622), .A1(DMP_SHT2_EWSW[29]), .B0(n1620), .B1(
DMP_SFG[29]), .Y(n679) );
AO22XLTS U1858 ( .A0(n1565), .A1(DMP_SFG[29]), .B0(n1563), .B1(
DMP_exp_NRM_EW[6]), .Y(n678) );
AO22XLTS U1859 ( .A0(n1479), .A1(DMP_EXP_EWSW[30]), .B0(n1478), .B1(
DMP_SHT1_EWSW[30]), .Y(n676) );
AO22XLTS U1860 ( .A0(n1480), .A1(DMP_SHT1_EWSW[30]), .B0(n1474), .B1(
DMP_SHT2_EWSW[30]), .Y(n675) );
AO22XLTS U1861 ( .A0(n1616), .A1(DMP_SHT2_EWSW[30]), .B0(n1620), .B1(
DMP_SFG[30]), .Y(n674) );
AO22XLTS U1862 ( .A0(n1565), .A1(DMP_SFG[30]), .B0(n1563), .B1(
DMP_exp_NRM_EW[7]), .Y(n673) );
AO22XLTS U1863 ( .A0(n1476), .A1(DmP_EXP_EWSW[13]), .B0(n1478), .B1(n1005),
.Y(n644) );
AO22XLTS U1864 ( .A0(n1467), .A1(DmP_EXP_EWSW[14]), .B0(n1478), .B1(
DmP_mant_SHT1_SW[14]), .Y(n642) );
AO22XLTS U1865 ( .A0(n1473), .A1(DmP_EXP_EWSW[15]), .B0(n1478), .B1(n1004),
.Y(n640) );
OAI222X1TS U1866 ( .A0(n1469), .A1(n1687), .B0(n1642), .B1(
Shift_reg_FLAGS_7_6), .C0(n1013), .C1(n935), .Y(n624) );
OAI222X1TS U1867 ( .A0(n1469), .A1(n1643), .B0(n1691), .B1(
Shift_reg_FLAGS_7_6), .C0(n1670), .C1(n1468), .Y(n623) );
OAI222X1TS U1868 ( .A0(n1469), .A1(n1644), .B0(n1686), .B1(
Shift_reg_FLAGS_7_6), .C0(n1016), .C1(n1468), .Y(n622) );
AO21XLTS U1869 ( .A0(underflow_flag), .A1(n1023), .B0(n1471), .Y(n620) );
AO22XLTS U1870 ( .A0(n1476), .A1(ZERO_FLAG_EXP), .B0(n1472), .B1(
ZERO_FLAG_SHT1), .Y(n618) );
AO22XLTS U1871 ( .A0(n1480), .A1(ZERO_FLAG_SHT1), .B0(n1474), .B1(
ZERO_FLAG_SHT2), .Y(n617) );
AO22XLTS U1872 ( .A0(n1604), .A1(ZERO_FLAG_SHT2), .B0(n1620), .B1(
ZERO_FLAG_SFG), .Y(n616) );
AO22XLTS U1873 ( .A0(n973), .A1(ZERO_FLAG_SFG), .B0(n1563), .B1(
ZERO_FLAG_NRM), .Y(n615) );
AO22XLTS U1874 ( .A0(Shift_reg_FLAGS_7[0]), .A1(ZERO_FLAG_SHT1SHT2), .B0(
n1023), .B1(zero_flag), .Y(n613) );
AO22XLTS U1875 ( .A0(n1473), .A1(OP_FLAG_EXP), .B0(n1475), .B1(OP_FLAG_SHT1),
.Y(n612) );
AO22XLTS U1876 ( .A0(n1480), .A1(OP_FLAG_SHT1), .B0(n934), .B1(OP_FLAG_SHT2),
.Y(n611) );
OAI2BB2XLTS U1877 ( .B0(n1477), .B1(n1636), .A0N(n1477), .A1N(OP_FLAG_SHT2),
.Y(n610) );
AO22XLTS U1878 ( .A0(n1476), .A1(SIGN_FLAG_EXP), .B0(n1472), .B1(
SIGN_FLAG_SHT1), .Y(n609) );
AO22XLTS U1879 ( .A0(n1480), .A1(SIGN_FLAG_SHT1), .B0(n934), .B1(
SIGN_FLAG_SHT2), .Y(n608) );
AO22XLTS U1880 ( .A0(n1604), .A1(SIGN_FLAG_SHT2), .B0(n1620), .B1(
SIGN_FLAG_SFG), .Y(n607) );
AO22XLTS U1881 ( .A0(n1565), .A1(SIGN_FLAG_SFG), .B0(n1716), .B1(
SIGN_FLAG_NRM), .Y(n606) );
AOI2BB2X1TS U1882 ( .B0(n1532), .B1(DmP_mant_SFG_SWR[10]), .A0N(
DmP_mant_SFG_SWR[10]), .A1N(OP_FLAG_SFG), .Y(n1481) );
CLKAND2X2TS U1883 ( .A(n1481), .B(DMP_SFG[8]), .Y(n1505) );
NOR2X1TS U1884 ( .A(n1481), .B(DMP_SFG[8]), .Y(n1504) );
NOR2X1TS U1885 ( .A(n1505), .B(n1504), .Y(n1525) );
XOR2X1TS U1886 ( .A(DMP_SFG[5]), .B(n1484), .Y(n1562) );
INVX1TS U1887 ( .A(DmP_mant_SFG_SWR[6]), .Y(n1568) );
AOI22X1TS U1888 ( .A0(n1532), .A1(DmP_mant_SFG_SWR[6]), .B0(n1568), .B1(
n1636), .Y(n1482) );
NOR2X1TS U1889 ( .A(DMP_SFG[4]), .B(n1482), .Y(n1559) );
NAND2X1TS U1890 ( .A(DMP_SFG[4]), .B(n1482), .Y(n1558) );
INVX2TS U1891 ( .A(n1558), .Y(n1485) );
NOR2X1TS U1892 ( .A(n1559), .B(n1485), .Y(n1555) );
NAND2X1TS U1893 ( .A(n1562), .B(n1555), .Y(n1499) );
AOI222X1TS U1894 ( .A0(n1485), .A1(DMP_SFG[5]), .B0(n1485), .B1(n1484), .C0(
DMP_SFG[5]), .C1(n1484), .Y(n1486) );
OAI2BB1X1TS U1895 ( .A0N(DMP_SFG[7]), .A1N(n1521), .B0(n1488), .Y(n1489) );
OAI2BB1X1TS U1896 ( .A0N(n1498), .A1N(DMP_SFG[9]), .B0(n1490), .Y(n1491) );
OAI22X1TS U1897 ( .A0(n1491), .A1(n1505), .B0(n1498), .B1(DMP_SFG[9]), .Y(
intadd_46_B_0_) );
AOI2BB2XLTS U1898 ( .B0(n991), .B1(n1514), .A0N(n1636), .A1N(n991), .Y(
intadd_46_CI) );
AOI22X1TS U1899 ( .A0(n1565), .A1(intadd_46_SUM_0_), .B0(n1626), .B1(n1563),
.Y(n603) );
AOI2BB2XLTS U1900 ( .B0(n990), .B1(n1514), .A0N(n1636), .A1N(n990), .Y(
intadd_46_B_1_) );
AOI2BB2XLTS U1901 ( .B0(n1557), .B1(intadd_46_SUM_1_), .A0N(
Raw_mant_NRM_SWR[13]), .A1N(n1557), .Y(n602) );
AOI2BB2XLTS U1902 ( .B0(n989), .B1(n1514), .A0N(n1636), .A1N(n989), .Y(
intadd_46_B_2_) );
AOI22X1TS U1903 ( .A0(n973), .A1(intadd_46_SUM_2_), .B0(n1625), .B1(n1563),
.Y(n601) );
AOI2BB2XLTS U1904 ( .B0(n988), .B1(n1514), .A0N(n1636), .A1N(n988), .Y(
intadd_46_B_3_) );
AOI2BB2XLTS U1905 ( .B0(n1557), .B1(intadd_46_SUM_3_), .A0N(
Raw_mant_NRM_SWR[15]), .A1N(n1557), .Y(n600) );
AOI22X1TS U1906 ( .A0(n1532), .A1(n1030), .B0(DmP_mant_SFG_SWR[16]), .B1(
n1636), .Y(intadd_46_B_4_) );
AOI22X1TS U1907 ( .A0(n1565), .A1(intadd_46_SUM_4_), .B0(n1631), .B1(n1563),
.Y(n599) );
AOI22X1TS U1908 ( .A0(n1532), .A1(n1031), .B0(DmP_mant_SFG_SWR[17]), .B1(
n1636), .Y(intadd_46_B_5_) );
AOI22X1TS U1909 ( .A0(n1565), .A1(intadd_46_SUM_5_), .B0(n1628), .B1(n1716),
.Y(n598) );
INVX1TS U1910 ( .A(DmP_mant_SFG_SWR[18]), .Y(n1607) );
AOI22X1TS U1911 ( .A0(n1532), .A1(n1607), .B0(DmP_mant_SFG_SWR[18]), .B1(
n1636), .Y(intadd_46_B_6_) );
AOI2BB2XLTS U1912 ( .B0(n1557), .B1(intadd_46_SUM_6_), .A0N(
Raw_mant_NRM_SWR[18]), .A1N(n1557), .Y(n597) );
INVX1TS U1913 ( .A(DmP_mant_SFG_SWR[19]), .Y(n1609) );
AOI22X1TS U1914 ( .A0(OP_FLAG_SFG), .A1(n1609), .B0(DmP_mant_SFG_SWR[19]),
.B1(n1636), .Y(intadd_46_B_7_) );
AOI2BB2XLTS U1915 ( .B0(n1557), .B1(intadd_46_SUM_7_), .A0N(
Raw_mant_NRM_SWR[19]), .A1N(n1557), .Y(n596) );
AOI22X1TS U1916 ( .A0(OP_FLAG_SFG), .A1(n1038), .B0(DmP_mant_SFG_SWR[20]),
.B1(n1636), .Y(intadd_46_B_8_) );
AOI2BB2XLTS U1917 ( .B0(n1557), .B1(intadd_46_SUM_8_), .A0N(
Raw_mant_NRM_SWR[20]), .A1N(n1557), .Y(n595) );
AOI22X1TS U1918 ( .A0(n1532), .A1(n1036), .B0(DmP_mant_SFG_SWR[21]), .B1(
n1636), .Y(intadd_46_B_9_) );
AOI22X1TS U1919 ( .A0(n1565), .A1(intadd_46_SUM_9_), .B0(n1627), .B1(n1716),
.Y(n594) );
AOI22X1TS U1920 ( .A0(n1532), .A1(n1028), .B0(DmP_mant_SFG_SWR[22]), .B1(
n1514), .Y(intadd_46_B_10_) );
AOI22X1TS U1921 ( .A0(n973), .A1(intadd_46_SUM_10_), .B0(n1624), .B1(n1716),
.Y(n593) );
AOI22X1TS U1922 ( .A0(OP_FLAG_SFG), .A1(n967), .B0(DmP_mant_SFG_SWR[23]),
.B1(n1514), .Y(intadd_46_B_11_) );
AOI22X1TS U1923 ( .A0(n1557), .A1(intadd_46_SUM_11_), .B0(n952), .B1(n1563),
.Y(n592) );
AOI22X1TS U1924 ( .A0(n1532), .A1(n975), .B0(DmP_mant_SFG_SWR[24]), .B1(
n1514), .Y(intadd_46_B_12_) );
AOI22X1TS U1925 ( .A0(n973), .A1(intadd_46_SUM_12_), .B0(n1623), .B1(n1563),
.Y(n591) );
AOI22X1TS U1926 ( .A0(OP_FLAG_SFG), .A1(DmP_mant_SFG_SWR[25]), .B0(n1034),
.B1(n1514), .Y(n1493) );
XNOR2X1TS U1927 ( .A(intadd_46_n1), .B(n1493), .Y(n1494) );
AOI22X1TS U1928 ( .A0(n1565), .A1(n1494), .B0(n1632), .B1(n1563), .Y(n590)
);
AOI22X1TS U1929 ( .A0(Data_array_SWR[13]), .A1(n1064), .B0(n1020), .B1(n1619), .Y(n1495) );
OAI221X1TS U1930 ( .A0(n1618), .A1(n1497), .B0(n1591), .B1(n1496), .C0(n1495), .Y(n1584) );
XOR2XLTS U1931 ( .A(DMP_SFG[9]), .B(n1498), .Y(n1507) );
INVX2TS U1932 ( .A(n1499), .Y(n1502) );
AOI2BB2X1TS U1933 ( .B0(n1554), .B1(DMP_SFG[3]), .A0N(DMP_SFG[3]), .A1N(
n1554), .Y(n1547) );
AOI31XLTS U1934 ( .A0(n1502), .A1(n1547), .A2(n1501), .B0(n1500), .Y(n1503)
);
INVX2TS U1935 ( .A(n1503), .Y(n1519) );
AOI2BB1XLTS U1936 ( .A0N(n1505), .A1N(n1524), .B0(n1504), .Y(n1506) );
XNOR2X1TS U1937 ( .A(n1507), .B(n1506), .Y(n1508) );
AOI22X1TS U1938 ( .A0(n1557), .A1(n1508), .B0(n1646), .B1(n1716), .Y(n588)
);
AOI22X1TS U1939 ( .A0(Data_array_SWR[12]), .A1(n1542), .B0(Data_array_SWR[9]), .B1(n1541), .Y(n1511) );
INVX2TS U1940 ( .A(n1509), .Y(n1543) );
AOI22X1TS U1941 ( .A0(Data_array_SWR[5]), .A1(n1062), .B0(Data_array_SWR[1]),
.B1(n1543), .Y(n1510) );
OAI211X1TS U1942 ( .A0(n1512), .A1(n1660), .B0(n1511), .C0(n1510), .Y(n1601)
);
AOI22X1TS U1943 ( .A0(Data_array_SWR[21]), .A1(n1064), .B0(n1591), .B1(n1601), .Y(n1513) );
AOI22X1TS U1944 ( .A0(n1477), .A1(n1513), .B0(n974), .B1(n1593), .Y(n586) );
AOI22X1TS U1945 ( .A0(n1532), .A1(n974), .B0(DmP_mant_SFG_SWR[1]), .B1(n1514), .Y(n1515) );
AOI2BB2XLTS U1946 ( .B0(n1557), .B1(n1515), .A0N(Raw_mant_NRM_SWR[1]), .A1N(
n1557), .Y(n585) );
AOI22X1TS U1947 ( .A0(n1622), .A1(n1598), .B0(n1032), .B1(n1593), .Y(n583)
);
OAI2BB2XLTS U1948 ( .B0(n1557), .B1(n1649), .A0N(n1557), .A1N(n1523), .Y(
n581) );
XNOR2X1TS U1949 ( .A(n1525), .B(n1524), .Y(n1526) );
AOI22X1TS U1950 ( .A0(n1565), .A1(n1526), .B0(n1647), .B1(n1716), .Y(n580)
);
AOI22X1TS U1951 ( .A0(Data_array_SWR[11]), .A1(n1542), .B0(Data_array_SWR[8]), .B1(n1541), .Y(n1528) );
AOI22X1TS U1952 ( .A0(Data_array_SWR[4]), .A1(n1062), .B0(Data_array_SWR[0]),
.B1(n1543), .Y(n1527) );
OAI211X1TS U1953 ( .A0(n1529), .A1(n1660), .B0(n1528), .C0(n1527), .Y(n1617)
);
AOI22X1TS U1954 ( .A0(Data_array_SWR[22]), .A1(n1064), .B0(n1591), .B1(n1617), .Y(n1530) );
AOI22X1TS U1955 ( .A0(n1616), .A1(n1530), .B0(n1035), .B1(n1593), .Y(n578)
);
AOI22X1TS U1956 ( .A0(n1532), .A1(n1035), .B0(DmP_mant_SFG_SWR[0]), .B1(
n1636), .Y(n1533) );
AOI2BB2XLTS U1957 ( .B0(n1557), .B1(n1533), .A0N(n1017), .A1N(n1557), .Y(
n577) );
AOI22X1TS U1958 ( .A0(Data_array_SWR[13]), .A1(n1542), .B0(
Data_array_SWR[10]), .B1(n1541), .Y(n1535) );
AOI22X1TS U1959 ( .A0(Data_array_SWR[6]), .A1(n1062), .B0(Data_array_SWR[2]),
.B1(n1543), .Y(n1534) );
OAI211X1TS U1960 ( .A0(n1536), .A1(n1660), .B0(n1535), .C0(n1534), .Y(n1600)
);
AOI22X1TS U1961 ( .A0(Data_array_SWR[20]), .A1(n1064), .B0(n1591), .B1(n1600), .Y(n1597) );
AOI22X1TS U1962 ( .A0(n1604), .A1(n1597), .B0(n1593), .B1(n1025), .Y(n576)
);
XNOR2X1TS U1963 ( .A(n986), .B(n1538), .Y(n1540) );
AOI22X1TS U1964 ( .A0(n1565), .A1(n1540), .B0(n1683), .B1(n1716), .Y(n574)
);
AOI22X1TS U1965 ( .A0(Data_array_SWR[14]), .A1(n1542), .B0(n1020), .B1(n1541), .Y(n1545) );
AOI22X1TS U1966 ( .A0(Data_array_SWR[7]), .A1(n1062), .B0(Data_array_SWR[3]),
.B1(n1543), .Y(n1544) );
OAI211X1TS U1967 ( .A0(n1546), .A1(n1660), .B0(n1545), .C0(n1544), .Y(n1599)
);
AOI22X1TS U1968 ( .A0(Data_array_SWR[19]), .A1(n1064), .B0(n1591), .B1(n1599), .Y(n1596) );
AOI22X1TS U1969 ( .A0(n1477), .A1(n1596), .B0(n1593), .B1(n1026), .Y(n571)
);
INVX2TS U1970 ( .A(n1547), .Y(n1551) );
XOR2XLTS U1971 ( .A(n1551), .B(n1553), .Y(n1552) );
AOI2BB2XLTS U1972 ( .B0(n1557), .B1(n1552), .A0N(Raw_mant_NRM_SWR[5]), .A1N(
n1557), .Y(n569) );
AOI22X1TS U1973 ( .A0(n973), .A1(n1556), .B0(n1650), .B1(n1716), .Y(n568) );
OAI21XLTS U1974 ( .A0(n1560), .A1(n1559), .B0(n1558), .Y(n1561) );
XNOR2X1TS U1975 ( .A(n1562), .B(n1561), .Y(n1564) );
AOI22X1TS U1976 ( .A0(n1565), .A1(n1564), .B0(n1633), .B1(n1563), .Y(n567)
);
AOI22X1TS U1977 ( .A0(n1622), .A1(n1569), .B0(n1568), .B1(n1593), .Y(n566)
);
OAI2BB2XLTS U1978 ( .B0(n1569), .B1(n1602), .A0N(final_result_ieee[4]),
.A1N(n1715), .Y(n565) );
AOI22X1TS U1979 ( .A0(n1616), .A1(n1573), .B0(n1572), .B1(n1593), .Y(n563)
);
OAI2BB2XLTS U1980 ( .B0(n1573), .B1(n1602), .A0N(final_result_ieee[2]),
.A1N(n1715), .Y(n562) );
AOI22X1TS U1981 ( .A0(Data_array_SWR[11]), .A1(n1619), .B0(
Data_array_SWR[12]), .B1(n1064), .Y(n1574) );
OAI221X1TS U1982 ( .A0(n1618), .A1(n1576), .B0(n1591), .B1(n1575), .C0(n1574), .Y(n1603) );
AO22XLTS U1983 ( .A0(n1588), .A1(n1603), .B0(final_result_ieee[10]), .B1(
n1023), .Y(n560) );
AO22XLTS U1984 ( .A0(n1588), .A1(n1577), .B0(final_result_ieee[11]), .B1(
n1023), .Y(n559) );
AOI22X1TS U1985 ( .A0(n1477), .A1(n1580), .B0(n1027), .B1(n1593), .Y(n558)
);
OAI2BB2XLTS U1986 ( .B0(n1580), .B1(n1602), .A0N(final_result_ieee[7]),
.A1N(n1715), .Y(n557) );
AOI22X1TS U1987 ( .A0(n1616), .A1(n1583), .B0(n987), .B1(n1593), .Y(n555) );
OAI2BB2XLTS U1988 ( .B0(n1583), .B1(n1602), .A0N(final_result_ieee[3]),
.A1N(n1715), .Y(n554) );
AO22XLTS U1989 ( .A0(n1588), .A1(n1584), .B0(final_result_ieee[9]), .B1(
n1023), .Y(n552) );
AO22XLTS U1990 ( .A0(n1588), .A1(n1585), .B0(final_result_ieee[12]), .B1(
n1023), .Y(n551) );
AO22XLTS U1991 ( .A0(n1588), .A1(n1586), .B0(final_result_ieee[8]), .B1(
n1023), .Y(n549) );
AO22XLTS U1992 ( .A0(n1588), .A1(n1587), .B0(final_result_ieee[13]), .B1(
n1023), .Y(n548) );
AOI22X1TS U1993 ( .A0(n1604), .A1(n1595), .B0(n1594), .B1(n1593), .Y(n547)
);
OAI2BB2XLTS U1994 ( .B0(n1595), .B1(n1602), .A0N(final_result_ieee[5]),
.A1N(n1715), .Y(n546) );
OAI2BB2XLTS U1995 ( .B0(n1596), .B1(n1602), .A0N(final_result_ieee[1]),
.A1N(n1715), .Y(n544) );
OAI2BB2XLTS U1996 ( .B0(n1597), .B1(n1602), .A0N(final_result_ieee[0]),
.A1N(n1715), .Y(n543) );
OAI2BB2XLTS U1997 ( .B0(n1598), .B1(n1602), .A0N(final_result_ieee[6]),
.A1N(n1715), .Y(n542) );
AOI22X1TS U1998 ( .A0(Data_array_SWR[19]), .A1(n1619), .B0(n1618), .B1(n1599), .Y(n1613) );
OAI2BB2XLTS U1999 ( .B0(n1613), .B1(n1602), .A0N(final_result_ieee[20]),
.A1N(n1023), .Y(n540) );
AOI22X1TS U2000 ( .A0(Data_array_SWR[20]), .A1(n1619), .B0(n1618), .B1(n1600), .Y(n1614) );
OAI2BB2XLTS U2001 ( .B0(n1614), .B1(n1602), .A0N(final_result_ieee[21]),
.A1N(n1023), .Y(n539) );
AOI22X1TS U2002 ( .A0(Data_array_SWR[21]), .A1(n1619), .B0(n1618), .B1(n1601), .Y(n1615) );
OAI2BB2XLTS U2003 ( .B0(n1615), .B1(n1602), .A0N(final_result_ieee[22]),
.A1N(n1023), .Y(n538) );
AO22XLTS U2004 ( .A0(n1466), .A1(n991), .B0(n1616), .B1(n1603), .Y(n537) );
AOI22X1TS U2005 ( .A0(n1477), .A1(n1605), .B0(n1030), .B1(n1620), .Y(n533)
);
AOI22X1TS U2006 ( .A0(n1604), .A1(n1606), .B0(n1031), .B1(n1620), .Y(n532)
);
AOI22X1TS U2007 ( .A0(n1477), .A1(n1608), .B0(n1607), .B1(n1620), .Y(n531)
);
AOI22X1TS U2008 ( .A0(n1616), .A1(n1610), .B0(n1609), .B1(n1620), .Y(n530)
);
AOI22X1TS U2009 ( .A0(n1604), .A1(n1611), .B0(n1038), .B1(n1620), .Y(n529)
);
AOI22X1TS U2010 ( .A0(n1622), .A1(n1612), .B0(n1036), .B1(n1466), .Y(n528)
);
AOI22X1TS U2011 ( .A0(n1616), .A1(n1613), .B0(n1028), .B1(n1466), .Y(n527)
);
AOI22X1TS U2012 ( .A0(n1604), .A1(n1614), .B0(n967), .B1(n1620), .Y(n526) );
AOI22X1TS U2013 ( .A0(n1477), .A1(n1615), .B0(n975), .B1(n1620), .Y(n525) );
AOI22X1TS U2014 ( .A0(Data_array_SWR[22]), .A1(n1619), .B0(n1618), .B1(n1617), .Y(n1621) );
AOI22X1TS U2015 ( .A0(n1622), .A1(n1621), .B0(n1034), .B1(n1620), .Y(n524)
);
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpadd_approx_syn_constraints_clk40.tcl_GDAN16M4P8_syn.sdf");
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 07.01.2017 17:22:31
// Design Name:
// Module Name: freq_count_sim
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module freq_count_sim();
reg clk = 0;
reg [31:0] Ncycles = 2;
reg [31:0] data_in = 0;
wire [31:0] out;
wire [31:0] data_out;
wire valid_out;
frequency_counter fc (.S_AXIS_IN_tdata(data_in),
.S_AXIS_IN_tvalid(1'b1),
.clk(clk),
.rst(1'b1),
.Ncycles(Ncycles),
.M_AXIS_OUT_tdata(data_out),
.M_AXIS_OUT_tvalid(valid_out),
.counter_output(out)
);
initial begin
clk = 0;
forever #1 clk = ~clk;
end
//declare the sine ROM - 30 registers each 8 bit wide.
reg signed [31:0] sine [0:29];
//Internal signals
integer i;
//Initialize the sine rom with samples.
initial begin
i = 0;
sine[0] = 0;
sine[1] = 16;
sine[2] = 31;
sine[3] = 45;
sine[4] = 58;
sine[5] = 67;
sine[6] = 74;
sine[7] = 77;
sine[8] = 77;
sine[9] = 74;
sine[10] = 67;
sine[11] = 58;
sine[12] = 45;
sine[13] = 31;
sine[14] = 16;
sine[15] = 0;
sine[16] = -16;
sine[17] = -31;
sine[18] = -45;
sine[19] = -58;
sine[20] = -67;
sine[21] = -74;
sine[22] = -77;
sine[23] = -77;
sine[24] = -74;
sine[25] = -67;
sine[26] = -58;
sine[27] = -45;
sine[28] = -31;
sine[29] = -16;
end
//At every positive edge of the clock, output a sine wave sample.
always@ (posedge(clk))
begin
data_in = 10*sine[i];
i = i + 1;
if(i == 30)
i = 0;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR3B_SYMBOL_V
`define SKY130_FD_SC_HDLL__OR3B_SYMBOL_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__or3b (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR3B_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A221O_TB_V
`define SKY130_FD_SC_MS__A221O_TB_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a221o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 B1 = 1'b1;
#260 B2 = 1'b1;
#280 C1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 B1 = 1'b0;
#440 B2 = 1'b0;
#460 C1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 C1 = 1'b1;
#660 B2 = 1'b1;
#680 B1 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 C1 = 1'bx;
#840 B2 = 1'bx;
#860 B1 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_ms__a221o dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A221O_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2BB2A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__O2BB2A_BEHAVIORAL_PP_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o2bb2a (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
and and0 (and0_out_X , nand0_out, or0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2BB2A_BEHAVIORAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FILL_DIODE_FUNCTIONAL_V
`define SKY130_FD_SC_MS__FILL_DIODE_FUNCTIONAL_V
/**
* fill_diode: Fill diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__fill_diode ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__FILL_DIODE_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAPMET1_2_V
`define SKY130_FD_SC_MS__TAPMET1_2_V
/**
* tapmet1: Tap cell with isolated power and ground connections.
*
* Verilog wrapper for tapmet1 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__tapmet1.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__tapmet1_2 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__tapmet1 base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__tapmet1_2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__tapmet1 base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAPMET1_2_V
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 14:42:35 2016
/////////////////////////////////////////////////////////////
module SNPS_CLOCK_GATE_HIGH_Up_counter_COUNTER_WIDTH4 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_FSM_Mult_Function ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_ShiftRegister_W7 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W13 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterMult_W9 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W48 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterMult_W24 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W24 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterMult_W32_0_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_3 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_3 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_4 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_6 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_9 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_FPU_Interface2_W32_EW8_SW23_SWR26_EWR5_1 ( CLK, EN,
ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module FPU_Interface2_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, begin_operation,
ack_operation, operation, region_flag, Data_1, Data_2, r_mode,
overflow_flag, underflow_flag, NaN_flag, operation_ready, op_result,
busy );
input [2:0] operation;
input [1:0] region_flag;
input [31:0] Data_1;
input [31:0] Data_2;
input [1:0] r_mode;
output [31:0] op_result;
input clk, rst, begin_operation, ack_operation;
output overflow_flag, underflow_flag, NaN_flag, operation_ready, busy;
wire NaN_reg, ready_add_subt, enab_cont_iter, underflow_flag_mult,
overflow_flag_addsubt, underflow_flag_addsubt,
FPSENCOS_fmtted_Result_31_, FPSENCOS_enab_d_ff4_Xn,
FPSENCOS_enab_d_ff4_Yn, FPSENCOS_d_ff3_sign_out,
FPSENCOS_d_ff1_operation_out, FPSENCOS_cont_var_out_1_,
FPSENCOS_enab_d_ff5_data_out, FPSENCOS_enab_RB3,
FPSENCOS_enab_d_ff_RB1, FPSENCOS_enab_d_ff4_Zn, FPMULT_FSM_selector_C,
FPMULT_FSM_selector_A, FPMULT_FSM_exp_operation_A_S,
FPMULT_FSM_barrel_shifter_load, FPMULT_FSM_final_result_load,
FPMULT_FSM_adder_round_norm_load, FPMULT_FSM_load_second_step,
FPMULT_FSM_exp_operation_load_result, FPMULT_FSM_first_phase_load,
FPMULT_FSM_add_overflow_flag, FPMULT_zero_flag, FPADDSUB_N60,
FPADDSUB_N59, FPADDSUB_OP_FLAG_SFG, FPADDSUB_SIGN_FLAG_SFG,
FPADDSUB__19_net_, FPADDSUB_SIGN_FLAG_NRM,
FPADDSUB_SIGN_FLAG_SHT1SHT2, FPADDSUB_ADD_OVRFLW_NRM2,
FPADDSUB_OP_FLAG_SHT2, FPADDSUB_SIGN_FLAG_SHT2,
FPADDSUB_left_right_SHT2, FPADDSUB__6_net_, FPADDSUB_ADD_OVRFLW_NRM,
FPADDSUB_OP_FLAG_SHT1, FPADDSUB_SIGN_FLAG_SHT1, FPADDSUB_OP_FLAG_EXP,
FPADDSUB_SIGN_FLAG_EXP, FPADDSUB_Shift_reg_FLAGS_7_5,
FPADDSUB_Shift_reg_FLAGS_7_6, FPADDSUB_enable_Pipeline_input,
FPSENCOS_ITER_CONT_net8354499, FPSENCOS_ITER_CONT_N5,
FPSENCOS_ITER_CONT_N4, FPSENCOS_ITER_CONT_N3,
FPMULT_FS_Module_net8354445, FPMULT_Exp_module_Overflow_flag_A,
FPMULT_Exp_module_Overflow_A,
FPMULT_final_result_ieee_Module_Sign_S_mux,
FPADDSUB_inst_ShiftRegister_net8354337,
FPADDSUB_SFT2FRMT_STAGE_VARS_net8354247,
FPSENCOS_d_ff5_data_out_net8354463,
FPADDSUB_FRMT_STAGE_DATAOUT_net8354175,
FPADDSUB_SGF_STAGE_DMP_net8354229,
FPADDSUB_NRM_STAGE_Raw_mant_net8354211, FPSENCOS_reg_Z0_net8354463,
FPSENCOS_reg_val_muxZ_2stage_net8354463,
FPSENCOS_reg_shift_y_net8354463, FPSENCOS_d_ff4_Xn_net8354463,
FPSENCOS_d_ff4_Yn_net8354463, FPSENCOS_d_ff4_Zn_net8354463,
FPADDSUB_INPUT_STAGE_OPERANDY_net8354175,
FPADDSUB_EXP_STAGE_DMP_net8354229, FPADDSUB_SHT1_STAGE_DMP_net8354229,
FPADDSUB_SHT2_STAGE_DMP_net8354229,
FPADDSUB_SHT2_SHIFT_DATA_net8354211,
FPMULT_Exp_module_exp_result_m_net8354409,
FPMULT_Sgf_operation_EVEN1_finalreg_net8354391,
FPMULT_Barrel_Shifter_module_Output_Reg_net8354373,
FPMULT_Adder_M_Add_Subt_Result_net8354355,
FPMULT_Operands_load_reg_XMRegister_net8354427,
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8354175,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N11,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N1,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N1,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N0,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N14,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N13,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N12,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N11,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N1,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N0,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N1,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N0,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N1,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N0,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N1,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N0,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N1,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N0,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N13,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N12,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N11,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N1,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N0,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N1,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N0,
n30, n115, n808, n811, n814, n817, n825, n829, n830, n840, n841, n842,
n844, n846, n847, n848, n849, n850, n851, n852, n853, n854, n855,
n857, n858, n859, n860, n861, n862, n863, n872, n873,
DP_OP_502J326_128_4510_n76, DP_OP_502J326_128_4510_n75,
DP_OP_502J326_128_4510_n70, DP_OP_502J326_128_4510_n69,
DP_OP_502J326_128_4510_n68, DP_OP_502J326_128_4510_n67,
DP_OP_502J326_128_4510_n66, DP_OP_502J326_128_4510_n63,
DP_OP_502J326_128_4510_n62, DP_OP_502J326_128_4510_n61,
DP_OP_502J326_128_4510_n60, DP_OP_502J326_128_4510_n59,
DP_OP_502J326_128_4510_n57, DP_OP_502J326_128_4510_n56,
DP_OP_502J326_128_4510_n55, DP_OP_502J326_128_4510_n54,
DP_OP_502J326_128_4510_n53, DP_OP_502J326_128_4510_n41,
DP_OP_502J326_128_4510_n38, DP_OP_502J326_128_4510_n37,
DP_OP_502J326_128_4510_n36, DP_OP_502J326_128_4510_n35,
DP_OP_502J326_128_4510_n34, DP_OP_502J326_128_4510_n33,
DP_OP_502J326_128_4510_n32, DP_OP_502J326_128_4510_n31,
DP_OP_502J326_128_4510_n30, DP_OP_502J326_128_4510_n29,
DP_OP_502J326_128_4510_n27, DP_OP_502J326_128_4510_n26,
DP_OP_502J326_128_4510_n25, DP_OP_502J326_128_4510_n24,
DP_OP_502J326_128_4510_n23, DP_OP_502J326_128_4510_n22,
DP_OP_502J326_128_4510_n21, DP_OP_501J326_127_5235_n236,
DP_OP_501J326_127_5235_n235, DP_OP_501J326_127_5235_n234,
DP_OP_501J326_127_5235_n233, DP_OP_501J326_127_5235_n229,
DP_OP_501J326_127_5235_n227, DP_OP_501J326_127_5235_n226,
DP_OP_501J326_127_5235_n220, DP_OP_501J326_127_5235_n218,
DP_OP_501J326_127_5235_n215, DP_OP_501J326_127_5235_n210,
DP_OP_501J326_127_5235_n209, DP_OP_501J326_127_5235_n207,
DP_OP_501J326_127_5235_n206, DP_OP_501J326_127_5235_n202,
DP_OP_501J326_127_5235_n200, DP_OP_501J326_127_5235_n199,
DP_OP_501J326_127_5235_n195, DP_OP_501J326_127_5235_n194,
DP_OP_501J326_127_5235_n193, DP_OP_501J326_127_5235_n192,
DP_OP_501J326_127_5235_n191, DP_OP_501J326_127_5235_n190,
DP_OP_501J326_127_5235_n189, DP_OP_501J326_127_5235_n188,
DP_OP_501J326_127_5235_n186, DP_OP_501J326_127_5235_n184,
DP_OP_501J326_127_5235_n183, DP_OP_501J326_127_5235_n182,
DP_OP_501J326_127_5235_n181, DP_OP_501J326_127_5235_n179,
DP_OP_501J326_127_5235_n171, DP_OP_501J326_127_5235_n170,
DP_OP_501J326_127_5235_n168, DP_OP_501J326_127_5235_n167,
DP_OP_501J326_127_5235_n166, DP_OP_501J326_127_5235_n163,
DP_OP_501J326_127_5235_n162, DP_OP_501J326_127_5235_n161,
DP_OP_501J326_127_5235_n160, DP_OP_501J326_127_5235_n159,
DP_OP_501J326_127_5235_n158, DP_OP_501J326_127_5235_n156,
DP_OP_501J326_127_5235_n155, DP_OP_501J326_127_5235_n154,
DP_OP_501J326_127_5235_n153, DP_OP_501J326_127_5235_n152,
DP_OP_501J326_127_5235_n151, DP_OP_501J326_127_5235_n150,
DP_OP_501J326_127_5235_n148, DP_OP_501J326_127_5235_n147,
DP_OP_501J326_127_5235_n146, DP_OP_501J326_127_5235_n145,
DP_OP_501J326_127_5235_n144, DP_OP_501J326_127_5235_n143,
DP_OP_501J326_127_5235_n142, DP_OP_501J326_127_5235_n141,
DP_OP_501J326_127_5235_n140, DP_OP_501J326_127_5235_n139,
DP_OP_501J326_127_5235_n138, DP_OP_501J326_127_5235_n137,
DP_OP_501J326_127_5235_n136, DP_OP_501J326_127_5235_n135,
DP_OP_501J326_127_5235_n134, DP_OP_501J326_127_5235_n133,
DP_OP_501J326_127_5235_n132, DP_OP_501J326_127_5235_n131,
DP_OP_501J326_127_5235_n130, DP_OP_501J326_127_5235_n129,
DP_OP_501J326_127_5235_n128, DP_OP_501J326_127_5235_n127,
DP_OP_501J326_127_5235_n126, DP_OP_501J326_127_5235_n125,
DP_OP_501J326_127_5235_n124, DP_OP_501J326_127_5235_n123,
DP_OP_501J326_127_5235_n122, DP_OP_501J326_127_5235_n121,
DP_OP_501J326_127_5235_n120, DP_OP_501J326_127_5235_n119,
DP_OP_501J326_127_5235_n118, DP_OP_501J326_127_5235_n117,
DP_OP_501J326_127_5235_n116, DP_OP_501J326_127_5235_n115,
DP_OP_501J326_127_5235_n114, DP_OP_501J326_127_5235_n113,
DP_OP_501J326_127_5235_n112, DP_OP_501J326_127_5235_n111,
DP_OP_501J326_127_5235_n110, DP_OP_501J326_127_5235_n109,
DP_OP_501J326_127_5235_n77, DP_OP_501J326_127_5235_n72,
DP_OP_501J326_127_5235_n71, DP_OP_501J326_127_5235_n62,
DP_OP_501J326_127_5235_n59, DP_OP_501J326_127_5235_n56,
DP_OP_501J326_127_5235_n55, DP_OP_501J326_127_5235_n54,
DP_OP_501J326_127_5235_n53, DP_OP_501J326_127_5235_n48,
DP_OP_501J326_127_5235_n40, DP_OP_501J326_127_5235_n39,
DP_OP_501J326_127_5235_n37, DP_OP_501J326_127_5235_n36,
DP_OP_501J326_127_5235_n35, DP_OP_501J326_127_5235_n34,
DP_OP_501J326_127_5235_n32, DP_OP_501J326_127_5235_n31,
DP_OP_501J326_127_5235_n30, DP_OP_501J326_127_5235_n29,
DP_OP_501J326_127_5235_n28, DP_OP_501J326_127_5235_n27,
DP_OP_501J326_127_5235_n25, DP_OP_501J326_127_5235_n24,
DP_OP_501J326_127_5235_n23, DP_OP_501J326_127_5235_n22,
DP_OP_501J326_127_5235_n21, DP_OP_501J326_127_5235_n20,
DP_OP_501J326_127_5235_n19, DP_OP_501J326_127_5235_n18,
DP_OP_501J326_127_5235_n17, DP_OP_501J326_127_5235_n16,
DP_OP_501J326_127_5235_n15, DP_OP_501J326_127_5235_n14,
DP_OP_501J326_127_5235_n13, DP_OP_500J326_126_4510_n76,
DP_OP_500J326_126_4510_n75, DP_OP_500J326_126_4510_n70,
DP_OP_500J326_126_4510_n69, DP_OP_500J326_126_4510_n68,
DP_OP_500J326_126_4510_n67, DP_OP_500J326_126_4510_n66,
DP_OP_500J326_126_4510_n63, DP_OP_500J326_126_4510_n62,
DP_OP_500J326_126_4510_n61, DP_OP_500J326_126_4510_n60,
DP_OP_500J326_126_4510_n59, DP_OP_500J326_126_4510_n56,
DP_OP_500J326_126_4510_n55, DP_OP_500J326_126_4510_n54,
DP_OP_500J326_126_4510_n53, DP_OP_500J326_126_4510_n52,
DP_OP_500J326_126_4510_n41, DP_OP_500J326_126_4510_n38,
DP_OP_500J326_126_4510_n37, DP_OP_500J326_126_4510_n36,
DP_OP_500J326_126_4510_n35, DP_OP_500J326_126_4510_n34,
DP_OP_500J326_126_4510_n33, DP_OP_500J326_126_4510_n32,
DP_OP_500J326_126_4510_n31, DP_OP_500J326_126_4510_n30,
DP_OP_500J326_126_4510_n29, DP_OP_500J326_126_4510_n27,
DP_OP_500J326_126_4510_n26, DP_OP_500J326_126_4510_n25,
DP_OP_500J326_126_4510_n24, DP_OP_500J326_126_4510_n23,
DP_OP_500J326_126_4510_n22, DP_OP_500J326_126_4510_n21,
DP_OP_499J326_125_1651_n133, DP_OP_499J326_125_1651_n132,
DP_OP_499J326_125_1651_n131, DP_OP_499J326_125_1651_n130,
DP_OP_499J326_125_1651_n129, DP_OP_499J326_125_1651_n128,
DP_OP_499J326_125_1651_n127, DP_OP_499J326_125_1651_n126,
DP_OP_499J326_125_1651_n125, DP_OP_499J326_125_1651_n124,
DP_OP_499J326_125_1651_n123, DP_OP_499J326_125_1651_n122,
DP_OP_499J326_125_1651_n121, DP_OP_499J326_125_1651_n120,
DP_OP_499J326_125_1651_n119, DP_OP_499J326_125_1651_n118,
DP_OP_499J326_125_1651_n110, DP_OP_499J326_125_1651_n109,
DP_OP_499J326_125_1651_n108, DP_OP_499J326_125_1651_n107,
DP_OP_499J326_125_1651_n106, DP_OP_499J326_125_1651_n105,
DP_OP_499J326_125_1651_n104, DP_OP_499J326_125_1651_n103,
DP_OP_499J326_125_1651_n102, DP_OP_499J326_125_1651_n101,
DP_OP_499J326_125_1651_n100, DP_OP_499J326_125_1651_n99,
DP_OP_499J326_125_1651_n98, DP_OP_499J326_125_1651_n97,
DP_OP_499J326_125_1651_n96, DP_OP_499J326_125_1651_n95,
DP_OP_499J326_125_1651_n81, DP_OP_499J326_125_1651_n78,
DP_OP_499J326_125_1651_n77, DP_OP_499J326_125_1651_n76,
DP_OP_499J326_125_1651_n75, DP_OP_499J326_125_1651_n74,
DP_OP_499J326_125_1651_n73, DP_OP_499J326_125_1651_n72,
DP_OP_499J326_125_1651_n71, DP_OP_499J326_125_1651_n70,
DP_OP_499J326_125_1651_n69, DP_OP_499J326_125_1651_n68,
DP_OP_499J326_125_1651_n67, DP_OP_499J326_125_1651_n66,
DP_OP_499J326_125_1651_n65, DP_OP_499J326_125_1651_n64,
DP_OP_499J326_125_1651_n63, DP_OP_499J326_125_1651_n62,
DP_OP_499J326_125_1651_n61, DP_OP_499J326_125_1651_n60,
DP_OP_499J326_125_1651_n59, DP_OP_499J326_125_1651_n58,
DP_OP_499J326_125_1651_n57, DP_OP_499J326_125_1651_n56,
DP_OP_499J326_125_1651_n55, DP_OP_499J326_125_1651_n54,
DP_OP_499J326_125_1651_n53, DP_OP_499J326_125_1651_n52,
DP_OP_499J326_125_1651_n51, DP_OP_499J326_125_1651_n50,
DP_OP_499J326_125_1651_n49, DP_OP_499J326_125_1651_n48,
DP_OP_499J326_125_1651_n47, DP_OP_499J326_125_1651_n46,
DP_OP_499J326_125_1651_n45, DP_OP_499J326_125_1651_n44,
DP_OP_499J326_125_1651_n43, DP_OP_499J326_125_1651_n42,
DP_OP_499J326_125_1651_n41, DP_OP_499J326_125_1651_n40,
DP_OP_499J326_125_1651_n39, DP_OP_499J326_125_1651_n38,
DP_OP_499J326_125_1651_n37, DP_OP_499J326_125_1651_n36,
DP_OP_499J326_125_1651_n35, DP_OP_499J326_125_1651_n34,
DP_OP_499J326_125_1651_n33, DP_OP_499J326_125_1651_n32,
DP_OP_499J326_125_1651_n31, mult_x_313_n76, mult_x_313_n75,
mult_x_313_n74, mult_x_313_n69, mult_x_313_n68, mult_x_313_n67,
mult_x_313_n66, mult_x_313_n65, mult_x_313_n62, mult_x_313_n61,
mult_x_313_n60, mult_x_313_n59, mult_x_313_n58, mult_x_313_n56,
mult_x_313_n55, mult_x_313_n54, mult_x_313_n42, mult_x_313_n39,
mult_x_313_n38, mult_x_313_n37, mult_x_313_n36, mult_x_313_n35,
mult_x_313_n34, mult_x_313_n33, mult_x_313_n32, mult_x_313_n31,
mult_x_313_n30, mult_x_313_n29, mult_x_313_n28, mult_x_313_n27,
mult_x_313_n26, mult_x_313_n25, mult_x_313_n24, mult_x_313_n23,
mult_x_313_n22, mult_x_313_n21, mult_x_312_n77, mult_x_312_n72,
mult_x_312_n71, mult_x_312_n67, mult_x_312_n59, mult_x_312_n58,
mult_x_312_n53, mult_x_312_n48, mult_x_312_n42, mult_x_312_n39,
mult_x_312_n38, mult_x_312_n37, mult_x_312_n36, mult_x_312_n35,
mult_x_312_n34, mult_x_312_n33, mult_x_312_n32, mult_x_312_n31,
mult_x_312_n30, mult_x_312_n29, mult_x_312_n28, mult_x_312_n27,
mult_x_312_n26, mult_x_312_n25, mult_x_312_n24, mult_x_312_n23,
mult_x_312_n22, mult_x_312_n21, mult_x_312_n20, mult_x_312_n19,
mult_x_312_n18, mult_x_312_n17, mult_x_312_n16, mult_x_312_n15,
mult_x_312_n14, mult_x_312_n13, mult_x_311_n77, mult_x_311_n72,
mult_x_311_n71, mult_x_311_n67, mult_x_311_n59, mult_x_311_n58,
mult_x_311_n53, mult_x_311_n48, mult_x_311_n42, mult_x_311_n39,
mult_x_311_n38, mult_x_311_n37, mult_x_311_n36, mult_x_311_n35,
mult_x_311_n34, mult_x_311_n33, mult_x_311_n32, mult_x_311_n31,
mult_x_311_n30, mult_x_311_n29, mult_x_311_n28, mult_x_311_n27,
mult_x_311_n26, mult_x_311_n25, mult_x_311_n24, mult_x_311_n23,
mult_x_311_n22, mult_x_311_n21, mult_x_311_n20, mult_x_311_n19,
mult_x_311_n18, mult_x_311_n17, mult_x_311_n16, mult_x_311_n15,
mult_x_311_n14, mult_x_311_n13, mult_x_310_n77, mult_x_310_n72,
mult_x_310_n71, mult_x_310_n67, mult_x_310_n59, mult_x_310_n58,
mult_x_310_n53, mult_x_310_n48, mult_x_310_n42, mult_x_310_n39,
mult_x_310_n38, mult_x_310_n37, mult_x_310_n36, mult_x_310_n35,
mult_x_310_n34, mult_x_310_n33, mult_x_310_n32, mult_x_310_n31,
mult_x_310_n30, mult_x_310_n29, mult_x_310_n28, mult_x_310_n27,
mult_x_310_n26, mult_x_310_n25, mult_x_310_n24, mult_x_310_n23,
mult_x_310_n22, mult_x_310_n21, mult_x_310_n20, mult_x_310_n19,
mult_x_310_n18, mult_x_310_n17, mult_x_310_n16, mult_x_310_n15,
mult_x_310_n14, mult_x_310_n13, mult_x_309_n76, mult_x_309_n71,
mult_x_309_n66, mult_x_309_n65, mult_x_309_n58, mult_x_309_n52,
mult_x_309_n42, mult_x_309_n39, mult_x_309_n38, mult_x_309_n37,
mult_x_309_n36, mult_x_309_n35, mult_x_309_n34, mult_x_309_n33,
mult_x_309_n32, mult_x_309_n31, mult_x_309_n30, mult_x_309_n29,
mult_x_309_n28, mult_x_309_n27, mult_x_309_n26, mult_x_309_n25,
mult_x_309_n24, mult_x_309_n23, mult_x_309_n22, mult_x_309_n21,
mult_x_309_n20, mult_x_309_n19, mult_x_309_n18, mult_x_309_n17,
mult_x_309_n16, mult_x_309_n15, mult_x_309_n14, mult_x_309_n13,
DP_OP_26J326_129_1325_n18, DP_OP_26J326_129_1325_n17,
DP_OP_26J326_129_1325_n16, DP_OP_26J326_129_1325_n15,
DP_OP_26J326_129_1325_n14, DP_OP_26J326_129_1325_n8,
DP_OP_26J326_129_1325_n7, DP_OP_26J326_129_1325_n6,
DP_OP_26J326_129_1325_n5, DP_OP_26J326_129_1325_n4,
DP_OP_26J326_129_1325_n3, DP_OP_26J326_129_1325_n2,
DP_OP_26J326_129_1325_n1, DP_OP_234J326_132_4955_n22,
DP_OP_234J326_132_4955_n21, DP_OP_234J326_132_4955_n20,
DP_OP_234J326_132_4955_n19, DP_OP_234J326_132_4955_n18,
DP_OP_234J326_132_4955_n17, DP_OP_234J326_132_4955_n16,
DP_OP_234J326_132_4955_n15, DP_OP_234J326_132_4955_n9,
DP_OP_234J326_132_4955_n8, DP_OP_234J326_132_4955_n7,
DP_OP_234J326_132_4955_n6, DP_OP_234J326_132_4955_n5,
DP_OP_234J326_132_4955_n4, DP_OP_234J326_132_4955_n3,
DP_OP_234J326_132_4955_n2, DP_OP_234J326_132_4955_n1,
intadd_1139_A_24_, intadd_1139_A_23_, intadd_1139_A_22_,
intadd_1139_A_21_, intadd_1139_A_20_, intadd_1139_A_19_,
intadd_1139_A_18_, intadd_1139_A_17_, intadd_1139_A_10_,
intadd_1139_A_9_, intadd_1139_A_8_, intadd_1139_A_7_,
intadd_1139_A_6_, intadd_1139_A_5_, intadd_1139_A_4_,
intadd_1139_A_3_, intadd_1139_A_2_, intadd_1139_A_1_,
intadd_1139_A_0_, intadd_1139_B_24_, intadd_1139_B_23_,
intadd_1139_B_22_, intadd_1139_B_21_, intadd_1139_B_20_,
intadd_1139_B_19_, intadd_1139_B_18_, intadd_1139_B_17_,
intadd_1139_B_16_, intadd_1139_B_15_, intadd_1139_B_14_,
intadd_1139_B_13_, intadd_1139_B_12_, intadd_1139_B_11_,
intadd_1139_B_10_, intadd_1139_B_9_, intadd_1139_B_8_,
intadd_1139_B_7_, intadd_1139_B_6_, intadd_1139_B_5_,
intadd_1139_B_4_, intadd_1139_B_3_, intadd_1139_B_2_,
intadd_1139_B_1_, intadd_1139_B_0_, intadd_1139_CI, intadd_1139_n25,
intadd_1139_n24, intadd_1139_n23, intadd_1139_n22, intadd_1139_n21,
intadd_1139_n20, intadd_1139_n19, intadd_1139_n18, intadd_1139_n17,
intadd_1139_n16, intadd_1139_n15, intadd_1139_n14, intadd_1139_n13,
intadd_1139_n12, intadd_1139_n11, intadd_1139_n10, intadd_1139_n9,
intadd_1139_n8, intadd_1139_n7, intadd_1139_n6, intadd_1139_n5,
intadd_1139_n4, intadd_1139_n3, intadd_1139_n2, intadd_1139_n1,
intadd_1140_A_16_, intadd_1140_A_15_, intadd_1140_A_14_,
intadd_1140_A_13_, intadd_1140_A_12_, intadd_1140_A_11_,
intadd_1140_A_10_, intadd_1140_A_9_, intadd_1140_A_8_,
intadd_1140_A_7_, intadd_1140_A_6_, intadd_1140_A_5_,
intadd_1140_A_4_, intadd_1140_A_3_, intadd_1140_A_2_,
intadd_1140_A_1_, intadd_1140_B_16_, intadd_1140_B_15_,
intadd_1140_B_14_, intadd_1140_B_13_, intadd_1140_B_12_,
intadd_1140_B_11_, intadd_1140_B_10_, intadd_1140_B_9_,
intadd_1140_B_8_, intadd_1140_B_7_, intadd_1140_B_6_,
intadd_1140_B_5_, intadd_1140_B_4_, intadd_1140_B_3_,
intadd_1140_B_2_, intadd_1140_B_1_, intadd_1140_B_0_,
intadd_1140_SUM_16_, intadd_1140_SUM_15_, intadd_1140_SUM_14_,
intadd_1140_SUM_13_, intadd_1140_SUM_12_, intadd_1140_SUM_11_,
intadd_1140_SUM_10_, intadd_1140_SUM_9_, intadd_1140_SUM_8_,
intadd_1140_SUM_7_, intadd_1140_SUM_6_, intadd_1140_SUM_5_,
intadd_1140_SUM_4_, intadd_1140_SUM_3_, intadd_1140_SUM_2_,
intadd_1140_SUM_1_, intadd_1140_SUM_0_, intadd_1140_n17,
intadd_1140_n16, intadd_1140_n15, intadd_1140_n14, intadd_1140_n13,
intadd_1140_n12, intadd_1140_n11, intadd_1140_n10, intadd_1140_n9,
intadd_1140_n8, intadd_1140_n7, intadd_1140_n6, intadd_1140_n5,
intadd_1140_n4, intadd_1140_n3, intadd_1140_n2, intadd_1140_n1,
intadd_1141_A_12_, intadd_1141_A_1_, intadd_1141_A_0_,
intadd_1141_B_12_, intadd_1141_B_11_, intadd_1141_B_2_,
intadd_1141_B_1_, intadd_1141_B_0_, intadd_1141_CI, intadd_1141_n13,
intadd_1141_n12, intadd_1141_n11, intadd_1141_n10, intadd_1141_n9,
intadd_1141_n8, intadd_1141_n7, intadd_1141_n6, intadd_1141_n5,
intadd_1141_n4, intadd_1141_n3, intadd_1141_n2, intadd_1141_n1,
intadd_1142_B_12_, intadd_1142_B_11_, intadd_1142_B_10_,
intadd_1142_B_9_, intadd_1142_B_8_, intadd_1142_B_7_,
intadd_1142_B_6_, intadd_1142_B_5_, intadd_1142_B_4_,
intadd_1142_B_3_, intadd_1142_B_2_, intadd_1142_B_1_,
intadd_1142_B_0_, intadd_1142_CI, intadd_1142_SUM_5_, intadd_1142_n13,
intadd_1142_n12, intadd_1142_n11, intadd_1142_n10, intadd_1142_n9,
intadd_1142_n8, intadd_1142_n7, intadd_1142_n6, intadd_1142_n5,
intadd_1142_n4, intadd_1142_n3, intadd_1142_n2, intadd_1142_n1,
intadd_1143_A_12_, intadd_1143_A_11_, intadd_1143_A_10_,
intadd_1143_A_9_, intadd_1143_A_8_, intadd_1143_A_7_,
intadd_1143_A_6_, intadd_1143_A_5_, intadd_1143_A_4_,
intadd_1143_A_3_, intadd_1143_A_2_, intadd_1143_B_12_,
intadd_1143_B_11_, intadd_1143_B_10_, intadd_1143_B_9_,
intadd_1143_B_8_, intadd_1143_B_7_, intadd_1143_B_6_,
intadd_1143_B_5_, intadd_1143_B_4_, intadd_1143_B_3_,
intadd_1143_B_2_, intadd_1143_B_1_, intadd_1143_B_0_,
intadd_1143_SUM_12_, intadd_1143_SUM_11_, intadd_1143_SUM_10_,
intadd_1143_SUM_9_, intadd_1143_SUM_8_, intadd_1143_SUM_7_,
intadd_1143_SUM_6_, intadd_1143_SUM_5_, intadd_1143_SUM_4_,
intadd_1143_SUM_3_, intadd_1143_SUM_2_, intadd_1143_SUM_1_,
intadd_1143_SUM_0_, intadd_1143_n13, intadd_1143_n12, intadd_1143_n11,
intadd_1143_n10, intadd_1143_n9, intadd_1143_n8, intadd_1143_n7,
intadd_1143_n6, intadd_1143_n5, intadd_1143_n4, intadd_1143_n3,
intadd_1143_n2, intadd_1143_n1, intadd_1144_B_12_, intadd_1144_B_11_,
intadd_1144_B_10_, intadd_1144_B_9_, intadd_1144_B_8_,
intadd_1144_B_7_, intadd_1144_B_6_, intadd_1144_B_5_,
intadd_1144_B_4_, intadd_1144_B_3_, intadd_1144_B_2_,
intadd_1144_B_1_, intadd_1144_B_0_, intadd_1144_CI,
intadd_1144_SUM_12_, intadd_1144_SUM_11_, intadd_1144_SUM_10_,
intadd_1144_SUM_9_, intadd_1144_SUM_8_, intadd_1144_SUM_7_,
intadd_1144_n13, intadd_1144_n12, intadd_1144_n11, intadd_1144_n10,
intadd_1144_n9, intadd_1144_n8, intadd_1144_n7, intadd_1144_n6,
intadd_1144_n5, intadd_1144_n4, intadd_1144_n3, intadd_1144_n2,
intadd_1144_n1, intadd_1145_A_11_, intadd_1145_A_10_,
intadd_1145_A_9_, intadd_1145_A_8_, intadd_1145_A_7_,
intadd_1145_A_6_, intadd_1145_A_5_, intadd_1145_A_4_,
intadd_1145_A_3_, intadd_1145_A_2_, intadd_1145_B_11_,
intadd_1145_B_10_, intadd_1145_B_9_, intadd_1145_B_8_,
intadd_1145_B_7_, intadd_1145_B_6_, intadd_1145_B_5_,
intadd_1145_B_4_, intadd_1145_B_3_, intadd_1145_B_2_,
intadd_1145_B_1_, intadd_1145_CI, intadd_1145_SUM_11_,
intadd_1145_SUM_10_, intadd_1145_SUM_9_, intadd_1145_SUM_8_,
intadd_1145_SUM_7_, intadd_1145_SUM_6_, intadd_1145_SUM_5_,
intadd_1145_SUM_4_, intadd_1145_SUM_3_, intadd_1145_SUM_2_,
intadd_1145_SUM_1_, intadd_1145_SUM_0_, intadd_1145_n12,
intadd_1145_n11, intadd_1145_n10, intadd_1145_n9, intadd_1145_n8,
intadd_1145_n7, intadd_1145_n6, intadd_1145_n5, intadd_1145_n4,
intadd_1145_n3, intadd_1145_n2, intadd_1145_n1, intadd_1146_A_9_,
intadd_1146_A_8_, intadd_1146_A_7_, intadd_1146_A_6_,
intadd_1146_A_5_, intadd_1146_A_4_, intadd_1146_A_3_,
intadd_1146_A_2_, intadd_1146_A_1_, intadd_1146_B_10_,
intadd_1146_B_9_, intadd_1146_B_8_, intadd_1146_B_7_,
intadd_1146_B_6_, intadd_1146_B_5_, intadd_1146_B_4_,
intadd_1146_B_3_, intadd_1146_B_2_, intadd_1146_B_1_,
intadd_1146_B_0_, intadd_1146_CI, intadd_1146_SUM_0_, intadd_1146_n11,
intadd_1146_n10, intadd_1146_n9, intadd_1146_n8, intadd_1146_n7,
intadd_1146_n6, intadd_1146_n5, intadd_1146_n4, intadd_1146_n3,
intadd_1146_n2, intadd_1146_n1, intadd_1147_CI, intadd_1147_SUM_9_,
intadd_1147_SUM_8_, intadd_1147_SUM_7_, intadd_1147_SUM_6_,
intadd_1147_SUM_5_, intadd_1147_SUM_4_, intadd_1147_SUM_3_,
intadd_1147_SUM_2_, intadd_1147_SUM_1_, intadd_1147_SUM_0_,
intadd_1147_n10, intadd_1147_n9, intadd_1147_n8, intadd_1147_n7,
intadd_1147_n6, intadd_1147_n5, intadd_1147_n4, intadd_1147_n3,
intadd_1147_n2, intadd_1147_n1, intadd_1148_CI, intadd_1148_SUM_9_,
intadd_1148_SUM_8_, intadd_1148_SUM_7_, intadd_1148_SUM_6_,
intadd_1148_SUM_5_, intadd_1148_SUM_4_, intadd_1148_SUM_3_,
intadd_1148_SUM_2_, intadd_1148_SUM_1_, intadd_1148_SUM_0_,
intadd_1148_n10, intadd_1148_n9, intadd_1148_n8, intadd_1148_n7,
intadd_1148_n6, intadd_1148_n5, intadd_1148_n4, intadd_1148_n3,
intadd_1148_n2, intadd_1148_n1, intadd_1149_A_8_, intadd_1149_A_1_,
intadd_1149_A_0_, intadd_1149_B_8_, intadd_1149_B_7_,
intadd_1149_B_2_, intadd_1149_B_1_, intadd_1149_B_0_, intadd_1149_CI,
intadd_1149_n9, intadd_1149_n8, intadd_1149_n7, intadd_1149_n6,
intadd_1149_n5, intadd_1149_n4, intadd_1149_n3, intadd_1149_n2,
intadd_1149_n1, intadd_1150_A_8_, intadd_1150_A_1_, intadd_1150_A_0_,
intadd_1150_B_8_, intadd_1150_B_7_, intadd_1150_B_2_,
intadd_1150_B_1_, intadd_1150_B_0_, intadd_1150_CI,
intadd_1150_SUM_1_, intadd_1150_SUM_0_, intadd_1150_n9,
intadd_1150_n8, intadd_1150_n7, intadd_1150_n6, intadd_1150_n5,
intadd_1150_n4, intadd_1150_n3, intadd_1150_n2, intadd_1150_n1,
intadd_1151_A_7_, intadd_1151_A_0_, intadd_1151_B_7_,
intadd_1151_B_6_, intadd_1151_B_1_, intadd_1151_B_0_, intadd_1151_CI,
intadd_1151_n8, intadd_1151_n7, intadd_1151_n6, intadd_1151_n5,
intadd_1151_n4, intadd_1151_n3, intadd_1151_n2, intadd_1151_n1,
intadd_1152_A_7_, intadd_1152_A_6_, intadd_1152_A_5_,
intadd_1152_A_4_, intadd_1152_A_3_, intadd_1152_A_2_,
intadd_1152_A_1_, intadd_1152_A_0_, intadd_1152_B_7_,
intadd_1152_B_6_, intadd_1152_B_5_, intadd_1152_B_4_,
intadd_1152_B_3_, intadd_1152_B_2_, intadd_1152_B_1_,
intadd_1152_B_0_, intadd_1152_CI, intadd_1152_SUM_7_,
intadd_1152_SUM_6_, intadd_1152_SUM_5_, intadd_1152_SUM_4_,
intadd_1152_SUM_3_, intadd_1152_SUM_2_, intadd_1152_SUM_1_,
intadd_1152_SUM_0_, intadd_1152_n8, intadd_1152_n7, intadd_1152_n6,
intadd_1152_n5, intadd_1152_n4, intadd_1152_n3, intadd_1152_n2,
intadd_1152_n1, intadd_1153_A_7_, intadd_1153_A_0_, intadd_1153_B_7_,
intadd_1153_B_6_, intadd_1153_B_1_, intadd_1153_B_0_, intadd_1153_CI,
intadd_1153_n8, intadd_1153_n7, intadd_1153_n6, intadd_1153_n5,
intadd_1153_n4, intadd_1153_n3, intadd_1153_n2, intadd_1153_n1,
intadd_1154_A_7_, intadd_1154_A_0_, intadd_1154_B_7_,
intadd_1154_B_6_, intadd_1154_B_1_, intadd_1154_B_0_, intadd_1154_CI,
intadd_1154_n8, intadd_1154_n7, intadd_1154_n6, intadd_1154_n5,
intadd_1154_n4, intadd_1154_n3, intadd_1154_n2, intadd_1154_n1,
intadd_1155_A_7_, intadd_1155_A_0_, intadd_1155_B_7_,
intadd_1155_B_6_, intadd_1155_B_1_, intadd_1155_B_0_, intadd_1155_CI,
intadd_1155_n8, intadd_1155_n7, intadd_1155_n6, intadd_1155_n5,
intadd_1155_n4, intadd_1155_n3, intadd_1155_n2, intadd_1155_n1,
intadd_1156_A_7_, intadd_1156_A_6_, intadd_1156_A_5_,
intadd_1156_A_4_, intadd_1156_A_3_, intadd_1156_A_2_,
intadd_1156_A_1_, intadd_1156_A_0_, intadd_1156_B_7_,
intadd_1156_B_6_, intadd_1156_B_5_, intadd_1156_B_4_,
intadd_1156_B_3_, intadd_1156_B_2_, intadd_1156_B_1_, intadd_1156_CI,
intadd_1156_SUM_0_, intadd_1156_n8, intadd_1156_n7, intadd_1156_n6,
intadd_1156_n5, intadd_1156_n4, intadd_1156_n3, intadd_1156_n2,
intadd_1156_n1, intadd_1157_A_0_, intadd_1157_B_6_, intadd_1157_B_1_,
intadd_1157_B_0_, intadd_1157_CI, intadd_1157_n7, intadd_1157_n6,
intadd_1157_n5, intadd_1157_n4, intadd_1157_n3, intadd_1157_n2,
intadd_1157_n1, intadd_1158_CI, intadd_1158_SUM_4_,
intadd_1158_SUM_3_, intadd_1158_SUM_2_, intadd_1158_SUM_1_,
intadd_1158_SUM_0_, intadd_1158_n5, intadd_1158_n4, intadd_1158_n3,
intadd_1158_n2, intadd_1158_n1, intadd_1159_A_4_, intadd_1159_A_3_,
intadd_1159_B_0_, intadd_1159_SUM_4_, intadd_1159_SUM_3_,
intadd_1159_SUM_2_, intadd_1159_SUM_1_, intadd_1159_SUM_0_,
intadd_1159_n5, intadd_1159_n4, intadd_1159_n3, intadd_1159_n2,
intadd_1159_n1, intadd_1160_A_4_, intadd_1160_A_3_, intadd_1160_B_0_,
intadd_1160_SUM_4_, intadd_1160_SUM_3_, intadd_1160_SUM_2_,
intadd_1160_SUM_1_, intadd_1160_SUM_0_, intadd_1160_n5,
intadd_1160_n4, intadd_1160_n3, intadd_1160_n2, intadd_1160_n1,
intadd_1161_CI, intadd_1161_SUM_3_, intadd_1161_SUM_2_,
intadd_1161_SUM_1_, intadd_1161_n4, intadd_1161_n3, intadd_1161_n2,
intadd_1161_n1, intadd_1162_CI, intadd_1162_SUM_3_,
intadd_1162_SUM_2_, intadd_1162_SUM_1_, intadd_1162_SUM_0_,
intadd_1162_n4, intadd_1162_n3, intadd_1162_n2, intadd_1162_n1,
intadd_1163_CI, intadd_1163_SUM_3_, intadd_1163_SUM_2_,
intadd_1163_SUM_1_, intadd_1163_n4, intadd_1163_n3, intadd_1163_n2,
intadd_1163_n1, intadd_1164_CI, intadd_1164_n3, intadd_1164_n2,
intadd_1164_n1, intadd_1165_CI, intadd_1165_n3, intadd_1165_n2,
intadd_1165_n1, intadd_1166_CI, intadd_1166_n3, intadd_1166_n2,
intadd_1166_n1, n908, n910, n911, n912, n913, n914, n916, n917, n918,
n919, n920, n921, n922, n923, n924, n925, n926, n927, n928, n929,
n930, n931, n932, n933, n934, n935, n936, n937, n938, n939, n940,
n941, n942, n943, n944, n945, n946, n947, n948, n949, n950, n951,
n952, n953, n954, n955, n956, n957, n958, n959, n960, n961, n962,
n963, n964, n965, n966, n967, n968, n969, n970, n971, n972, n973,
n974, n975, n976, n977, n978, n979, n980, n981, n982, n983, n984,
n985, n986, n987, n988, n989, n990, n991, n992, n993, n994, n995,
n996, n997, n998, n999, n1000, n1001, n1002, n1003, n1004, n1005,
n1006, n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015,
n1016, n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025,
n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035,
n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045,
n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055,
n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065,
n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075,
n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085,
n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095,
n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105,
n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115,
n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125,
n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135,
n1136, n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145,
n1146, n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155,
n1156, n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165,
n1166, n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175,
n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185,
n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195,
n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205,
n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215,
n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225,
n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235,
n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245,
n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255,
n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265,
n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275,
n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285,
n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295,
n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305,
n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315,
n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325,
n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335,
n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345,
n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355,
n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365,
n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375,
n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385,
n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395,
n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405,
n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415,
n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425,
n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435,
n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445,
n1446, n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455, n1456,
n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465, n1466,
n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475, n1476,
n1477, n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485, n1486,
n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496,
n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506,
n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516,
n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526,
n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535, n1536,
n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545, n1546,
n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556,
n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566,
n1567, n1568, n1569, n1570, n1571, n1572, n1574, n1575, n1576, n1577,
n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586, n1587,
n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596, n1597,
n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606, n1607,
n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616, n1617,
n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626, n1627,
n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636, n1637,
n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646, n1647,
n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656, n1657,
n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666, n1667,
n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676, n1677,
n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686, n1687,
n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696, n1697,
n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706, n1707,
n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716, n1717,
n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725, n1726, n1727,
n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736, n1737,
n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745, n1746, n1747,
n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755, n1756, n1757,
n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765, n1766, n1767,
n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775, n1776, n1777,
n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785, n1786, n1787,
n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795, n1796, n1797,
n1798, n1799, n1800, n1801, n1802, n1803, n1804, n1805, n1806, n1807,
n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815, n1816, n1817,
n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825, n1826, n1827,
n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835, n1836, n1837,
n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845, n1846, n1847,
n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855, n1856, n1857,
n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865, n1866, n1867,
n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875, n1876, n1877,
n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885, n1886, n1887,
n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895, n1896, n1897,
n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905, n1906, n1907,
n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915, n1916, n1917,
n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925, n1926, n1927,
n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935, n1936, n1937,
n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945, n1946, n1947,
n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955, n1956, n1957,
n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965, n1966, n1967,
n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975, n1976, n1977,
n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985, n1986, n1987,
n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995, n1996, n1997,
n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005, n2006, n2007,
n2008, n2009, n2010, n2011, n2012, n2013, n2014, n2015, n2016, n2017,
n2018, n2019, n2020, n2021, n2022, n2023, n2024, n2025, n2026, n2027,
n2028, n2029, n2030, n2031, n2032, n2033, n2034, n2035, n2036, n2037,
n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045, n2046, n2047,
n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055, n2056, n2057,
n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065, n2066, n2067,
n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075, n2076, n2077,
n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085, n2086, n2087,
n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095, n2096, n2097,
n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105, n2106, n2107,
n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115, n2116, n2117,
n2118, n2119, n2120, n2121, n2122, n2123, n2124, n2125, n2126, n2127,
n2128, n2129, n2130, n2131, n2132, n2133, n2134, n2135, n2136, n2137,
n2138, n2139, n2140, n2141, n2142, n2143, n2144, n2145, n2146, n2147,
n2148, n2149, n2150, n2151, n2152, n2153, n2154, n2155, n2156, n2157,
n2158, n2159, n2160, n2161, n2162, n2163, n2164, n2165, n2166, n2167,
n2168, n2169, n2170, n2171, n2172, n2173, n2174, n2175, n2176, n2177,
n2178, n2179, n2180, n2181, n2182, n2183, n2184, n2185, n2186, n2187,
n2188, n2189, n2190, n2191, n2192, n2193, n2194, n2195, n2196, n2197,
n2198, n2199, n2200, n2201, n2202, n2203, n2204, n2205, n2206, n2207,
n2208, n2209, n2210, n2211, n2212, n2213, n2214, n2215, n2216, n2217,
n2218, n2219, n2220, n2221, n2222, n2223, n2224, n2225, n2226, n2227,
n2228, n2229, n2230, n2231, n2232, n2233, n2234, n2235, n2236, n2237,
n2238, n2239, n2240, n2241, n2242, n2243, n2244, n2245, n2246, n2247,
n2248, n2249, n2250, n2251, n2252, n2253, n2254, n2255, n2256, n2257,
n2258, n2259, n2260, n2261, n2262, n2263, n2264, n2265, n2266, n2267,
n2268, n2269, n2270, n2271, n2272, n2273, n2274, n2275, n2276, n2277,
n2278, n2279, n2280, n2281, n2282, n2283, n2284, n2285, n2286, n2287,
n2288, n2289, n2290, n2291, n2292, n2293, n2294, n2295, n2296, n2297,
n2298, n2299, n2300, n2301, n2302, n2303, n2304, n2305, n2306, n2307,
n2308, n2309, n2311, n2312, n2313, n2314, n2315, n2316, n2317, n2318,
n2319, n2320, n2321, n2322, n2323, n2324, n2325, n2326, n2327, n2328,
n2329, n2330, n2331, n2332, n2333, n2334, n2335, n2336, n2337, n2338,
n2339, n2340, n2341, n2342, n2343, n2344, n2345, n2346, n2347, n2348,
n2349, n2350, n2351, n2352, n2353, n2354, n2355, n2356, n2357, n2358,
n2359, n2360, n2361, n2362, n2363, n2364, n2365, n2366, n2367, n2368,
n2369, n2370, n2371, n2372, n2373, n2374, n2375, n2376, n2377, n2378,
n2379, n2380, n2381, n2382, n2383, n2384, n2385, n2386, n2387, n2388,
n2389, n2390, n2391, n2392, n2393, n2394, n2395, n2396, n2397, n2398,
n2399, n2400, n2401, n2402, n2403, n2404, n2405, n2406, n2407, n2408,
n2409, n2410, n2411, n2412, n2413, n2414, n2415, n2416, n2417, n2418,
n2419, n2420, n2421, n2422, n2423, n2424, n2425, n2426, n2427, n2428,
n2429, n2430, n2431, n2432, n2434, n2435, n2436, n2437, n2438, n2439,
n2440, n2441, n2442, n2443, n2444, n2445, n2446, n2447, n2448, n2449,
n2450, n2451, n2452, n2453, n2454, n2455, n2456, n2457, n2458, n2459,
n2460, n2461, n2462, n2463, n2464, n2465, n2466, n2467, n2468, n2469,
n2470, n2471, n2472, n2473, n2474, n2475, n2476, n2477, n2478, n2479,
n2480, n2481, n2482, n2483, n2484, n2485, n2486, n2487, n2488, n2489,
n2490, n2491, n2492, n2493, n2494, n2495, n2496, n2497, n2498, n2499,
n2500, n2501, n2502, n2503, n2504, n2505, n2506, n2507, n2508, n2509,
n2510, n2511, n2512, n2513, n2514, n2515, n2516, n2517, n2518, n2519,
n2520, n2521, n2522, n2523, n2524, n2525, n2526, n2527, n2528, n2529,
n2530, n2531, n2532, n2533, n2534, n2535, n2536, n2537, n2538, n2539,
n2540, n2541, n2542, n2543, n2544, n2545, n2546, n2547, n2548, n2549,
n2550, n2551, n2552, n2553, n2554, n2555, n2556, n2557, n2558, n2559,
n2560, n2561, n2562, n2563, n2564, n2565, n2566, n2567, n2568, n2569,
n2570, n2571, n2572, n2573, n2574, n2575, n2576, n2577, n2578, n2579,
n2580, n2581, n2582, n2583, n2584, n2585, n2586, n2587, n2588, n2589,
n2590, n2591, n2592, n2593, n2594, n2595, n2596, n2597, n2598, n2599,
n2600, n2601, n2602, n2603, n2604, n2605, n2606, n2607, n2608, n2609,
n2610, n2611, n2612, n2613, n2614, n2615, n2616, n2617, n2618, n2619,
n2620, n2621, n2622, n2623, n2624, n2625, n2626, n2627, n2628, n2629,
n2630, n2631, n2632, n2633, n2634, n2635, n2636, n2637, n2638, n2639,
n2640, n2641, n2642, n2643, n2644, n2645, n2646, n2647, n2648, n2649,
n2650, n2651, n2652, n2653, n2654, n2655, n2656, n2657, n2658, n2659,
n2660, n2661, n2662, n2663, n2664, n2665, n2666, n2667, n2668, n2669,
n2670, n2671, n2673, n2674, n2675, n2676, n2677, n2678, n2679, n2680,
n2681, n2682, n2683, n2684, n2685, n2686, n2687, n2688, n2689, n2690,
n2691, n2692, n2693, n2694, n2695, n2696, n2697, n2698, n2699, n2700,
n2701, n2702, n2703, n2704, n2705, n2706, n2707, n2708, n2709, n2710,
n2711, n2712, n2713, n2715, n2716, n2717, n2718, n2719, n2720, n2721,
n2722, n2723, n2724, n2725, n2726, n2727, n2728, n2729, n2730, n2731,
n2732, n2733, n2734, n2735, n2736, n2737, n2738, n2739, n2740, n2741,
n2742, n2743, n2744, n2745, n2746, n2747, n2748, n2749, n2750, n2751,
n2752, n2753, n2754, n2755, n2756, n2757, n2758, n2759, n2760, n2761,
n2762, n2763, n2764, n2765, n2766, n2767, n2768, n2769, n2770, n2771,
n2772, n2773, n2774, n2775, n2776, n2777, n2778, n2779, n2780, n2781,
n2782, n2783, n2784, n2785, n2787, n2788, n2790, n2791, n2792, n2793,
n2794, n2795, n2796, n2797, n2798, n2799, n2800, n2801, n2802, n2803,
n2804, n2805, n2806, n2807, n2808, n2809, n2810, n2811, n2812, n2813,
n2814, n2815, n2816;
wire [1:0] operation_reg;
wire [31:23] dataA;
wire [31:23] dataB;
wire [31:0] add_subt_data1;
wire [30:0] add_subt_data2;
wire [31:0] cordic_result;
wire [31:0] result_add_subt;
wire [31:0] mult_result;
wire [30:0] FPSENCOS_mux_sal;
wire [27:0] FPSENCOS_d_ff3_LUT_out;
wire [31:0] FPSENCOS_d_ff3_sh_y_out;
wire [31:0] FPSENCOS_d_ff3_sh_x_out;
wire [25:4] FPSENCOS_data_out_LUT;
wire [7:0] FPSENCOS_sh_exp_y;
wire [7:0] FPSENCOS_sh_exp_x;
wire [31:0] FPSENCOS_d_ff2_Z;
wire [31:0] FPSENCOS_d_ff2_Y;
wire [31:0] FPSENCOS_d_ff2_X;
wire [31:0] FPSENCOS_first_mux_Z;
wire [31:0] FPSENCOS_d_ff_Zn;
wire [31:0] FPSENCOS_first_mux_Y;
wire [31:0] FPSENCOS_d_ff_Yn;
wire [31:0] FPSENCOS_first_mux_X;
wire [31:0] FPSENCOS_d_ff_Xn;
wire [31:0] FPSENCOS_d_ff1_Z;
wire [1:0] FPSENCOS_d_ff1_shift_region_flag_out;
wire [3:0] FPSENCOS_cont_iter_out;
wire [23:0] FPMULT_Sgf_normalized_result;
wire [23:0] FPMULT_Add_result;
wire [8:0] FPMULT_S_Oper_A_exp;
wire [8:0] FPMULT_exp_oper_result;
wire [30:1] FPMULT_Op_MY;
wire [30:0] FPMULT_Op_MX;
wire [1:0] FPMULT_FSM_selector_B;
wire [47:23] FPMULT_P_Sgf;
wire [31:0] FPADDSUB_formatted_number_W;
wire [25:1] FPADDSUB_Raw_mant_SGF;
wire [25:2] FPADDSUB_DmP_mant_SFG_SWR;
wire [30:0] FPADDSUB_DMP_SFG;
wire [7:0] FPADDSUB_exp_rslt_NRM2_EW1;
wire [4:0] FPADDSUB_LZD_output_NRM2_EW;
wire [25:0] FPADDSUB_sftr_odat_SHT2_SWR;
wire [7:0] FPADDSUB_DMP_exp_NRM_EW;
wire [7:0] FPADDSUB_DMP_exp_NRM2_EW;
wire [4:2] FPADDSUB_shift_value_SHT2_EWR;
wire [30:0] FPADDSUB_DMP_SHT2_EWSW;
wire [50:0] FPADDSUB_Data_array_SWR;
wire [25:0] FPADDSUB_Raw_mant_NRM_SWR;
wire [4:2] FPADDSUB_shft_value_mux_o_EWR;
wire [4:0] FPADDSUB_LZD_raw_out_EWR;
wire [4:0] FPADDSUB_Shift_amount_SHT1_EWR;
wire [22:0] FPADDSUB_DmP_mant_SHT1_SW;
wire [30:0] FPADDSUB_DMP_SHT1_EWSW;
wire [4:0] FPADDSUB_Shift_amount_EXP_EW;
wire [27:0] FPADDSUB_DmP_EXP_EWSW;
wire [30:0] FPADDSUB_DMP_EXP_EWSW;
wire [27:0] FPADDSUB_DmP_INIT_EWSW;
wire [30:0] FPADDSUB_DMP_INIT_EWSW;
wire [30:0] FPADDSUB_intDY_EWSW;
wire [31:0] FPADDSUB_intDX_EWSW;
wire [3:0] FPADDSUB_Shift_reg_FLAGS_7;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_next;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_reg;
wire [3:0] FPMULT_FS_Module_state_next;
wire [3:0] FPMULT_FS_Module_state_reg;
wire [8:0] FPMULT_Exp_module_Data_S;
wire [47:0] FPMULT_Sgf_operation_Result;
wire [5:0] FPMULT_Sgf_operation_EVEN1_Q_left;
wire [24:1] FPMULT_Adder_M_result_A_adder;
wire [22:0] FPMULT_final_result_ieee_Module_Sgf_S_mux;
wire [7:0] FPMULT_final_result_ieee_Module_Exp_S_mux;
wire [2:0] FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg;
wire [13:0] FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle;
wire [11:6] FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right;
wire [11:0] FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left;
wire [16:1] FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B;
wire [15:0] FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle;
wire [13:0] FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right;
wire [11:0] FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left;
wire [13:1] FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle;
wire [11:7] FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right;
wire [11:0] FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left;
SNPS_CLOCK_GATE_HIGH_Up_counter_COUNTER_WIDTH4 FPSENCOS_ITER_CONT_clk_gate_temp_reg (
.CLK(clk), .EN(enab_cont_iter), .ENCLK(FPSENCOS_ITER_CONT_net8354499),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_FSM_Mult_Function FPMULT_FS_Module_clk_gate_state_reg_reg (
.CLK(clk), .EN(n844), .ENCLK(FPMULT_FS_Module_net8354445), .TE(1'b0)
);
SNPS_CLOCK_GATE_HIGH_ShiftRegister_W7 FPADDSUB_inst_ShiftRegister_clk_gate_Q_reg (
.CLK(clk), .EN(n873), .ENCLK(FPADDSUB_inst_ShiftRegister_net8354337),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W13 FPADDSUB_SFT2FRMT_STAGE_VARS_clk_gate_Q_reg (
.CLK(clk), .EN(n2674), .ENCLK(FPADDSUB_SFT2FRMT_STAGE_VARS_net8354247),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_0 FPSENCOS_d_ff5_data_out_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_enab_d_ff5_data_out), .ENCLK(
FPSENCOS_d_ff5_data_out_net8354463), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_0 FPADDSUB_FRMT_STAGE_DATAOUT_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_Shift_reg_FLAGS_7[0]), .ENCLK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8354175), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_0 FPADDSUB_SGF_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB__19_net_), .ENCLK(
FPADDSUB_SGF_STAGE_DMP_net8354229), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_0 FPADDSUB_NRM_STAGE_Raw_mant_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_Shift_reg_FLAGS_7[2]), .ENCLK(
FPADDSUB_NRM_STAGE_Raw_mant_net8354211), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_9 FPSENCOS_reg_Z0_clk_gate_Q_reg ( .CLK(
clk), .EN(FPSENCOS_enab_d_ff_RB1), .ENCLK(FPSENCOS_reg_Z0_net8354463),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_6 FPSENCOS_reg_val_muxZ_2stage_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_inst_CORDIC_FSM_v3_state_next[3]), .ENCLK(
FPSENCOS_reg_val_muxZ_2stage_net8354463), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_4 FPSENCOS_reg_shift_y_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_enab_RB3), .ENCLK(
FPSENCOS_reg_shift_y_net8354463), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_3 FPSENCOS_d_ff4_Xn_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_enab_d_ff4_Xn), .ENCLK(
FPSENCOS_d_ff4_Xn_net8354463), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_2 FPSENCOS_d_ff4_Yn_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_enab_d_ff4_Yn), .ENCLK(
FPSENCOS_d_ff4_Yn_net8354463), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_1 FPSENCOS_d_ff4_Zn_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_enab_d_ff4_Zn), .ENCLK(
FPSENCOS_d_ff4_Zn_net8354463), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_2 FPADDSUB_INPUT_STAGE_OPERANDY_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_enable_Pipeline_input), .ENCLK(
FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_3 FPADDSUB_EXP_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_Shift_reg_FLAGS_7_6), .ENCLK(
FPADDSUB_EXP_STAGE_DMP_net8354229), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_2 FPADDSUB_SHT1_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_Shift_reg_FLAGS_7_5), .ENCLK(
FPADDSUB_SHT1_STAGE_DMP_net8354229), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_1 FPADDSUB_SHT2_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(busy), .ENCLK(FPADDSUB_SHT2_STAGE_DMP_net8354229), .TE(
1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_2 FPADDSUB_SHT2_SHIFT_DATA_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB__6_net_), .ENCLK(
FPADDSUB_SHT2_SHIFT_DATA_net8354211), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterMult_W9 FPMULT_Exp_module_exp_result_m_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_exp_operation_load_result), .ENCLK(
FPMULT_Exp_module_exp_result_m_net8354409), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W48 FPMULT_Sgf_operation_EVEN1_finalreg_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_load_second_step), .ENCLK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8354391), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterMult_W24 FPMULT_Barrel_Shifter_module_Output_Reg_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_barrel_shifter_load), .ENCLK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8354373), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W24 FPMULT_Adder_M_Add_Subt_Result_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_adder_round_norm_load), .ENCLK(
FPMULT_Adder_M_Add_Subt_Result_net8354355), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterMult_W32_0_1 FPMULT_Operands_load_reg_XMRegister_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_first_phase_load), .ENCLK(
FPMULT_Operands_load_reg_XMRegister_net8354427), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_1 FPMULT_final_result_ieee_Module_Final_Result_IEEE_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_final_result_load), .ENCLK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8354175), .TE(
1'b0) );
DFFRXLTS reg_dataA_Q_reg_24_ ( .D(Data_1[24]), .CK(clk), .RN(n2711), .Q(
dataA[24]) );
DFFRXLTS reg_dataA_Q_reg_26_ ( .D(Data_1[26]), .CK(clk), .RN(n917), .Q(
dataA[26]) );
DFFRXLTS reg_dataA_Q_reg_31_ ( .D(Data_1[31]), .CK(clk), .RN(n2711), .Q(
dataA[31]) );
DFFRXLTS reg_dataB_Q_reg_23_ ( .D(Data_2[23]), .CK(clk), .RN(n1104), .Q(
dataB[23]) );
DFFRXLTS reg_dataB_Q_reg_25_ ( .D(Data_2[25]), .CK(clk), .RN(n2709), .Q(
dataB[25]) );
DFFRXLTS reg_dataB_Q_reg_27_ ( .D(Data_2[27]), .CK(clk), .RN(n2709), .Q(
dataB[27]) );
DFFRXLTS reg_dataB_Q_reg_29_ ( .D(Data_2[29]), .CK(clk), .RN(n2709), .Q(
dataB[29]) );
DFFRXLTS reg_dataB_Q_reg_31_ ( .D(Data_2[31]), .CK(clk), .RN(n2709), .Q(
dataB[31]) );
DFFRXLTS NaN_dff_Q_reg_0_ ( .D(NaN_reg), .CK(clk), .RN(n2709), .Q(NaN_flag)
);
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_6_ ( .D(n2792), .CK(
FPADDSUB_inst_ShiftRegister_net8354337), .RN(n2684), .Q(
FPADDSUB_Shift_reg_FLAGS_7_6) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_5_ ( .D(
FPADDSUB_Shift_reg_FLAGS_7_6), .CK(
FPADDSUB_inst_ShiftRegister_net8354337), .RN(n2691), .Q(
FPADDSUB_Shift_reg_FLAGS_7_5) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_3_ ( .D(busy), .CK(
FPADDSUB_inst_ShiftRegister_net8354337), .RN(n2696), .Q(
FPADDSUB_Shift_reg_FLAGS_7[3]) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_2_ ( .D(
FPADDSUB_Shift_reg_FLAGS_7[3]), .CK(
FPADDSUB_inst_ShiftRegister_net8354337), .RN(n2687), .Q(
FPADDSUB_Shift_reg_FLAGS_7[2]) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_1_ ( .D(
FPADDSUB_Shift_reg_FLAGS_7[2]), .CK(
FPADDSUB_inst_ShiftRegister_net8354337), .RN(n2687), .Q(
FPADDSUB_Shift_reg_FLAGS_7[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[4]), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n913), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[3]), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n2694), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[2]), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n2680), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[1]), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n2695), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[0]), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n2682), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[0]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_0_ ( .D(n850), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2717), .Q(
FPSENCOS_d_ff3_LUT_out[0]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_1_ ( .D(n860), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2701), .Q(
FPSENCOS_d_ff3_LUT_out[1]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_2_ ( .D(n854), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2728), .Q(
FPSENCOS_d_ff3_LUT_out[2]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_3_ ( .D(n862), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2704), .Q(
FPSENCOS_d_ff3_LUT_out[3]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_4_ ( .D(FPSENCOS_data_out_LUT[4]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2712), .Q(
FPSENCOS_d_ff3_LUT_out[4]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_5_ ( .D(n851), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2703), .Q(
FPSENCOS_d_ff3_LUT_out[5]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_6_ ( .D(n853), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n919), .Q(
FPSENCOS_d_ff3_LUT_out[6]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_7_ ( .D(n857), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n1102), .Q(
FPSENCOS_d_ff3_LUT_out[7]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_8_ ( .D(n908), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2702), .Q(
FPSENCOS_d_ff3_LUT_out[8]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_9_ ( .D(n859), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n916), .Q(
FPSENCOS_d_ff3_LUT_out[9]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_10_ ( .D(n852), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2706), .Q(
FPSENCOS_d_ff3_LUT_out[10]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_12_ ( .D(n858), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2709), .Q(
FPSENCOS_d_ff3_LUT_out[12]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_13_ ( .D(n849), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2708), .Q(
FPSENCOS_d_ff3_LUT_out[13]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_15_ ( .D(n861), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2708), .Q(
FPSENCOS_d_ff3_LUT_out[15]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_19_ ( .D(n863), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2708), .Q(
FPSENCOS_d_ff3_LUT_out[19]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_21_ ( .D(n848), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2708), .Q(
FPSENCOS_d_ff3_LUT_out[21]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_23_ ( .D(n847), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2708), .Q(
FPSENCOS_d_ff3_LUT_out[23]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_24_ ( .D(n846), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2708), .Q(
FPSENCOS_d_ff3_LUT_out[24]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_25_ ( .D(FPSENCOS_data_out_LUT[25]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2708), .Q(
FPSENCOS_d_ff3_LUT_out[25]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_26_ ( .D(n855), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2708), .Q(
FPSENCOS_d_ff3_LUT_out[26]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_0_ ( .D(Data_1[0]), .CK(
FPSENCOS_reg_Z0_net8354463), .RN(n2708), .Q(FPSENCOS_d_ff1_Z[0]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_1_ ( .D(Data_1[1]), .CK(
FPSENCOS_reg_Z0_net8354463), .RN(n2708), .Q(FPSENCOS_d_ff1_Z[1]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_2_ ( .D(Data_1[2]), .CK(
FPSENCOS_reg_Z0_net8354463), .RN(n2708), .Q(FPSENCOS_d_ff1_Z[2]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_3_ ( .D(Data_1[3]), .CK(
FPSENCOS_reg_Z0_net8354463), .RN(n2717), .Q(FPSENCOS_d_ff1_Z[3]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_4_ ( .D(Data_1[4]), .CK(
FPSENCOS_reg_Z0_net8354463), .RN(n2717), .Q(FPSENCOS_d_ff1_Z[4]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_5_ ( .D(Data_1[5]), .CK(
FPSENCOS_reg_Z0_net8354463), .RN(n2717), .Q(FPSENCOS_d_ff1_Z[5]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_6_ ( .D(Data_1[6]), .CK(
FPSENCOS_reg_Z0_net8354463), .RN(n2717), .Q(FPSENCOS_d_ff1_Z[6]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_7_ ( .D(Data_1[7]), .CK(
FPSENCOS_reg_Z0_net8354463), .RN(n2717), .Q(FPSENCOS_d_ff1_Z[7]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_8_ ( .D(Data_1[8]), .CK(
FPSENCOS_reg_Z0_net8354463), .RN(n2717), .Q(FPSENCOS_d_ff1_Z[8]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_9_ ( .D(Data_1[9]), .CK(
FPSENCOS_reg_Z0_net8354463), .RN(n2717), .Q(FPSENCOS_d_ff1_Z[9]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_10_ ( .D(Data_1[10]), .CK(
FPSENCOS_reg_Z0_net8354463), .RN(n2717), .Q(FPSENCOS_d_ff1_Z[10]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_11_ ( .D(Data_1[11]), .CK(
FPSENCOS_reg_Z0_net8354463), .RN(n2717), .Q(FPSENCOS_d_ff1_Z[11]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_12_ ( .D(Data_1[12]), .CK(
FPSENCOS_reg_Z0_net8354463), .RN(n2717), .Q(FPSENCOS_d_ff1_Z[12]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_13_ ( .D(Data_1[13]), .CK(
FPSENCOS_reg_Z0_net8354463), .RN(n918), .Q(FPSENCOS_d_ff1_Z[13]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_14_ ( .D(Data_1[14]), .CK(
FPSENCOS_reg_Z0_net8354463), .RN(n918), .Q(FPSENCOS_d_ff1_Z[14]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_15_ ( .D(Data_1[15]), .CK(
FPSENCOS_reg_Z0_net8354463), .RN(n2705), .Q(FPSENCOS_d_ff1_Z[15]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_17_ ( .D(Data_1[17]), .CK(
FPSENCOS_reg_Z0_net8354463), .RN(n919), .Q(FPSENCOS_d_ff1_Z[17]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_18_ ( .D(Data_1[18]), .CK(
FPSENCOS_reg_Z0_net8354463), .RN(n919), .Q(FPSENCOS_d_ff1_Z[18]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_19_ ( .D(Data_1[19]), .CK(
FPSENCOS_reg_Z0_net8354463), .RN(n919), .Q(FPSENCOS_d_ff1_Z[19]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_20_ ( .D(Data_1[20]), .CK(
FPSENCOS_reg_Z0_net8354463), .RN(n919), .Q(FPSENCOS_d_ff1_Z[20]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_21_ ( .D(Data_1[21]), .CK(
FPSENCOS_reg_Z0_net8354463), .RN(n919), .Q(FPSENCOS_d_ff1_Z[21]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_22_ ( .D(Data_1[22]), .CK(
FPSENCOS_reg_Z0_net8354463), .RN(n919), .Q(FPSENCOS_d_ff1_Z[22]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_23_ ( .D(Data_1[23]), .CK(
FPSENCOS_reg_Z0_net8354463), .RN(n919), .Q(FPSENCOS_d_ff1_Z[23]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_24_ ( .D(Data_1[24]), .CK(
FPSENCOS_reg_Z0_net8354463), .RN(n2717), .Q(FPSENCOS_d_ff1_Z[24]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_25_ ( .D(Data_1[25]), .CK(
FPSENCOS_reg_Z0_net8354463), .RN(n2717), .Q(FPSENCOS_d_ff1_Z[25]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_26_ ( .D(Data_1[26]), .CK(
FPSENCOS_reg_Z0_net8354463), .RN(n947), .Q(FPSENCOS_d_ff1_Z[26]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_27_ ( .D(Data_1[27]), .CK(
FPSENCOS_reg_Z0_net8354463), .RN(n2709), .Q(FPSENCOS_d_ff1_Z[27]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_28_ ( .D(Data_1[28]), .CK(
FPSENCOS_reg_Z0_net8354463), .RN(n949), .Q(FPSENCOS_d_ff1_Z[28]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_29_ ( .D(Data_1[29]), .CK(
FPSENCOS_reg_Z0_net8354463), .RN(n2702), .Q(FPSENCOS_d_ff1_Z[29]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_30_ ( .D(Data_1[30]), .CK(
FPSENCOS_reg_Z0_net8354463), .RN(n916), .Q(FPSENCOS_d_ff1_Z[30]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_31_ ( .D(Data_1[31]), .CK(
FPSENCOS_reg_Z0_net8354463), .RN(n2706), .Q(FPSENCOS_d_ff1_Z[31]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_23_ ( .D(FPSENCOS_sh_exp_x[0]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2712), .Q(
FPSENCOS_d_ff3_sh_x_out[23]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_24_ ( .D(FPSENCOS_sh_exp_x[1]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2703), .Q(
FPSENCOS_d_ff3_sh_x_out[24]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_25_ ( .D(FPSENCOS_sh_exp_x[2]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n947), .Q(
FPSENCOS_d_ff3_sh_x_out[25]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_26_ ( .D(FPSENCOS_sh_exp_x[3]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2708), .Q(
FPSENCOS_d_ff3_sh_x_out[26]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_27_ ( .D(FPSENCOS_sh_exp_x[4]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2715), .Q(
FPSENCOS_d_ff3_sh_x_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_28_ ( .D(FPSENCOS_sh_exp_x[5]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2709), .Q(
FPSENCOS_d_ff3_sh_x_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_29_ ( .D(FPSENCOS_sh_exp_x[6]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2717), .Q(
FPSENCOS_d_ff3_sh_x_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_30_ ( .D(FPSENCOS_sh_exp_x[7]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2728), .Q(
FPSENCOS_d_ff3_sh_x_out[30]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_23_ ( .D(FPSENCOS_sh_exp_y[0]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2707), .Q(
FPSENCOS_d_ff3_sh_y_out[23]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_24_ ( .D(FPSENCOS_sh_exp_y[1]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n919), .Q(
FPSENCOS_d_ff3_sh_y_out[24]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_25_ ( .D(FPSENCOS_sh_exp_y[2]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n1104), .Q(
FPSENCOS_d_ff3_sh_y_out[25]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_26_ ( .D(FPSENCOS_sh_exp_y[3]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n919), .Q(
FPSENCOS_d_ff3_sh_y_out[26]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_27_ ( .D(FPSENCOS_sh_exp_y[4]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2716), .Q(
FPSENCOS_d_ff3_sh_y_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_28_ ( .D(FPSENCOS_sh_exp_y[5]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2717), .Q(
FPSENCOS_d_ff3_sh_y_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_29_ ( .D(FPSENCOS_sh_exp_y[6]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2728), .Q(
FPSENCOS_d_ff3_sh_y_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_30_ ( .D(FPSENCOS_sh_exp_y[7]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2707), .Q(
FPSENCOS_d_ff3_sh_y_out[30]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
FPSENCOS_d_ff4_Xn_net8354463), .RN(n919), .Q(FPSENCOS_d_ff_Xn[23]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
FPSENCOS_d_ff4_Xn_net8354463), .RN(n2716), .Q(FPSENCOS_d_ff_Xn[24]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
FPSENCOS_d_ff4_Xn_net8354463), .RN(n2728), .Q(FPSENCOS_d_ff_Xn[25]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
FPSENCOS_d_ff4_Xn_net8354463), .RN(n2707), .Q(FPSENCOS_d_ff_Xn[26]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
FPSENCOS_d_ff4_Xn_net8354463), .RN(n2717), .Q(FPSENCOS_d_ff_Xn[27]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
FPSENCOS_d_ff4_Xn_net8354463), .RN(n2716), .Q(FPSENCOS_d_ff_Xn[28]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
FPSENCOS_d_ff4_Xn_net8354463), .RN(n2716), .Q(FPSENCOS_d_ff_Xn[29]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
FPSENCOS_d_ff4_Xn_net8354463), .RN(n2715), .Q(FPSENCOS_d_ff_Xn[30]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
FPSENCOS_d_ff4_Yn_net8354463), .RN(n2715), .Q(FPSENCOS_d_ff_Yn[23]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_23_ ( .D(FPSENCOS_mux_sal[23]), .CK(
FPSENCOS_d_ff5_data_out_net8354463), .RN(n2715), .Q(cordic_result[23])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
FPSENCOS_d_ff4_Yn_net8354463), .RN(n2715), .Q(FPSENCOS_d_ff_Yn[24]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_24_ ( .D(FPSENCOS_mux_sal[24]), .CK(
FPSENCOS_d_ff5_data_out_net8354463), .RN(n2715), .Q(cordic_result[24])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
FPSENCOS_d_ff4_Yn_net8354463), .RN(n2715), .Q(FPSENCOS_d_ff_Yn[25]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_25_ ( .D(FPSENCOS_mux_sal[25]), .CK(
FPSENCOS_d_ff5_data_out_net8354463), .RN(n2715), .Q(cordic_result[25])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
FPSENCOS_d_ff4_Yn_net8354463), .RN(n2715), .Q(FPSENCOS_d_ff_Yn[26]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_26_ ( .D(FPSENCOS_mux_sal[26]), .CK(
FPSENCOS_d_ff5_data_out_net8354463), .RN(n918), .Q(cordic_result[26])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
FPSENCOS_d_ff4_Yn_net8354463), .RN(n917), .Q(FPSENCOS_d_ff_Yn[27]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_27_ ( .D(
FPSENCOS_first_mux_Y[27]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n918), .QN(n940) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_27_ ( .D(FPSENCOS_mux_sal[27]), .CK(
FPSENCOS_d_ff5_data_out_net8354463), .RN(n2711), .Q(cordic_result[27])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
FPSENCOS_d_ff4_Yn_net8354463), .RN(n917), .Q(FPSENCOS_d_ff_Yn[28]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_28_ ( .D(FPSENCOS_mux_sal[28]), .CK(
FPSENCOS_d_ff5_data_out_net8354463), .RN(n918), .Q(cordic_result[28])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
FPSENCOS_d_ff4_Yn_net8354463), .RN(n2711), .Q(FPSENCOS_d_ff_Yn[29]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_29_ ( .D(
FPSENCOS_first_mux_Y[29]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n918), .QN(n944) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_29_ ( .D(FPSENCOS_mux_sal[29]), .CK(
FPSENCOS_d_ff5_data_out_net8354463), .RN(n916), .Q(cordic_result[29])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
FPSENCOS_d_ff4_Yn_net8354463), .RN(n2728), .Q(FPSENCOS_d_ff_Yn[30]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_30_ ( .D(
FPSENCOS_first_mux_Y[30]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2707), .Q(FPSENCOS_d_ff2_Y[30]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_30_ ( .D(FPSENCOS_mux_sal[30]), .CK(
FPSENCOS_d_ff5_data_out_net8354463), .RN(n919), .Q(cordic_result[30])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
FPSENCOS_d_ff4_Zn_net8354463), .RN(n2716), .Q(FPSENCOS_d_ff_Zn[23]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_23_ ( .D(
FPSENCOS_first_mux_Z[23]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2728), .Q(FPSENCOS_d_ff2_Z[23]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
FPSENCOS_d_ff4_Zn_net8354463), .RN(n2707), .Q(FPSENCOS_d_ff_Zn[24]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_24_ ( .D(
FPSENCOS_first_mux_Z[24]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n919), .Q(FPSENCOS_d_ff2_Z[24]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
FPSENCOS_d_ff4_Zn_net8354463), .RN(n2717), .Q(FPSENCOS_d_ff_Zn[25]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_25_ ( .D(
FPSENCOS_first_mux_Z[25]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n1104), .Q(FPSENCOS_d_ff2_Z[25]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
FPSENCOS_d_ff4_Zn_net8354463), .RN(n919), .Q(FPSENCOS_d_ff_Zn[26]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_26_ ( .D(
FPSENCOS_first_mux_Z[26]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2716), .Q(FPSENCOS_d_ff2_Z[26]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
FPSENCOS_d_ff4_Zn_net8354463), .RN(n2716), .Q(FPSENCOS_d_ff_Zn[27]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_27_ ( .D(
FPSENCOS_first_mux_Z[27]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2728), .Q(FPSENCOS_d_ff2_Z[27]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
FPSENCOS_d_ff4_Zn_net8354463), .RN(n2707), .Q(FPSENCOS_d_ff_Zn[28]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_28_ ( .D(
FPSENCOS_first_mux_Z[28]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n919), .Q(FPSENCOS_d_ff2_Z[28]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
FPSENCOS_d_ff4_Zn_net8354463), .RN(n2717), .Q(FPSENCOS_d_ff_Zn[29]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_29_ ( .D(
FPSENCOS_first_mux_Z[29]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2716), .Q(FPSENCOS_d_ff2_Z[29]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
FPSENCOS_d_ff4_Zn_net8354463), .RN(n2716), .Q(FPSENCOS_d_ff_Zn[30]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_30_ ( .D(
FPSENCOS_first_mux_Z[30]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2728), .Q(FPSENCOS_d_ff2_Z[30]) );
DFFRXLTS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(add_subt_data1[24]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2689), .QN(n932)
);
DFFRXLTS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(add_subt_data1[28]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2676), .Q(
FPADDSUB_intDX_EWSW[28]), .QN(n2628) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_23_ ( .D(FPADDSUB_DmP_INIT_EWSW[23]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2686), .Q(
FPADDSUB_DmP_EXP_EWSW[23]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_24_ ( .D(FPADDSUB_DmP_INIT_EWSW[24]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2678), .QN(n2646) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_25_ ( .D(FPADDSUB_DmP_INIT_EWSW[25]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2681), .QN(n2661) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_26_ ( .D(FPADDSUB_DmP_INIT_EWSW[26]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2683), .QN(n2660) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_27_ ( .D(FPADDSUB_DmP_INIT_EWSW[27]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2688), .Q(
FPADDSUB_DmP_EXP_EWSW[27]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_23_ ( .D(FPADDSUB_DMP_INIT_EWSW[23]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2686), .Q(
FPADDSUB_DMP_EXP_EWSW[23]), .QN(n966) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_27_ ( .D(FPADDSUB_DMP_INIT_EWSW[27]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n1105), .Q(
FPADDSUB_DMP_EXP_EWSW[27]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_28_ ( .D(FPADDSUB_DMP_INIT_EWSW[28]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2685), .Q(
FPADDSUB_DMP_EXP_EWSW[28]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_29_ ( .D(FPADDSUB_DMP_INIT_EWSW[29]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2689), .Q(
FPADDSUB_DMP_EXP_EWSW[29]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_30_ ( .D(FPADDSUB_DMP_INIT_EWSW[30]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n913), .Q(
FPADDSUB_DMP_EXP_EWSW[30]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_23_ ( .D(FPADDSUB_DMP_EXP_EWSW[23]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n2689), .Q(
FPADDSUB_DMP_SHT1_EWSW[23]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_24_ ( .D(FPADDSUB_DMP_EXP_EWSW[24]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n2693), .Q(
FPADDSUB_DMP_SHT1_EWSW[24]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_25_ ( .D(FPADDSUB_DMP_EXP_EWSW[25]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n2678), .Q(
FPADDSUB_DMP_SHT1_EWSW[25]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_26_ ( .D(FPADDSUB_DMP_EXP_EWSW[26]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n2681), .Q(
FPADDSUB_DMP_SHT1_EWSW[26]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_27_ ( .D(FPADDSUB_DMP_EXP_EWSW[27]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n2685), .Q(
FPADDSUB_DMP_SHT1_EWSW[27]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_28_ ( .D(FPADDSUB_DMP_EXP_EWSW[28]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n2683), .Q(
FPADDSUB_DMP_SHT1_EWSW[28]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_29_ ( .D(FPADDSUB_DMP_EXP_EWSW[29]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n2688), .Q(
FPADDSUB_DMP_SHT1_EWSW[29]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_30_ ( .D(FPADDSUB_DMP_EXP_EWSW[30]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n2693), .Q(
FPADDSUB_DMP_SHT1_EWSW[30]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_23_ ( .D(FPADDSUB_DMP_SHT1_EWSW[23]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8354229), .RN(n2679), .Q(
FPADDSUB_DMP_SHT2_EWSW[23]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_23_ ( .D(FPADDSUB_DMP_SHT2_EWSW[23]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2697), .Q(
FPADDSUB_DMP_SFG[23]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(FPADDSUB_DMP_SFG[23]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8354211), .RN(n2697), .Q(
FPADDSUB_DMP_exp_NRM_EW[0]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[0]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8354247), .RN(n2697), .Q(
FPADDSUB_DMP_exp_NRM2_EW[0]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_24_ ( .D(FPADDSUB_DMP_SHT1_EWSW[24]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8354229), .RN(n2679), .Q(
FPADDSUB_DMP_SHT2_EWSW[24]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_24_ ( .D(FPADDSUB_DMP_SHT2_EWSW[24]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2687), .Q(
FPADDSUB_DMP_SFG[24]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(FPADDSUB_DMP_SFG[24]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8354211), .RN(n2690), .Q(
FPADDSUB_DMP_exp_NRM_EW[1]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[1]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8354247), .RN(n2696), .Q(
FPADDSUB_DMP_exp_NRM2_EW[1]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_25_ ( .D(FPADDSUB_DMP_SHT1_EWSW[25]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8354229), .RN(n913), .Q(
FPADDSUB_DMP_SHT2_EWSW[25]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_25_ ( .D(FPADDSUB_DMP_SHT2_EWSW[25]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2684), .Q(
FPADDSUB_DMP_SFG[25]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(FPADDSUB_DMP_SFG[25]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8354211), .RN(n2694), .Q(
FPADDSUB_DMP_exp_NRM_EW[2]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[2]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8354247), .RN(n913), .Q(
FPADDSUB_DMP_exp_NRM2_EW[2]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_26_ ( .D(FPADDSUB_DMP_SHT1_EWSW[26]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8354229), .RN(n2695), .Q(
FPADDSUB_DMP_SHT2_EWSW[26]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_26_ ( .D(FPADDSUB_DMP_SHT2_EWSW[26]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2695), .Q(
FPADDSUB_DMP_SFG[26]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(FPADDSUB_DMP_SFG[26]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8354211), .RN(n2682), .Q(
FPADDSUB_DMP_exp_NRM_EW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[3]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8354247), .RN(n2680), .Q(
FPADDSUB_DMP_exp_NRM2_EW[3]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_27_ ( .D(FPADDSUB_DMP_SHT1_EWSW[27]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8354229), .RN(n2689), .Q(
FPADDSUB_DMP_SHT2_EWSW[27]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_27_ ( .D(FPADDSUB_DMP_SHT2_EWSW[27]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2684), .Q(
FPADDSUB_DMP_SFG[27]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(FPADDSUB_DMP_SFG[27]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8354211), .RN(n2676), .Q(
FPADDSUB_DMP_exp_NRM_EW[4]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[4]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8354247), .RN(n2689), .Q(
FPADDSUB_DMP_exp_NRM2_EW[4]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_28_ ( .D(FPADDSUB_DMP_SHT1_EWSW[28]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8354229), .RN(n1105), .Q(
FPADDSUB_DMP_SHT2_EWSW[28]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_28_ ( .D(FPADDSUB_DMP_SHT2_EWSW[28]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2687), .Q(
FPADDSUB_DMP_SFG[28]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(FPADDSUB_DMP_SFG[28]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8354211), .RN(n2687), .Q(
FPADDSUB_DMP_exp_NRM_EW[5]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[5]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8354247), .RN(n2687), .Q(
FPADDSUB_DMP_exp_NRM2_EW[5]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_29_ ( .D(FPADDSUB_DMP_SHT1_EWSW[29]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8354229), .RN(n2686), .Q(
FPADDSUB_DMP_SHT2_EWSW[29]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_29_ ( .D(FPADDSUB_DMP_SHT2_EWSW[29]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2687), .Q(
FPADDSUB_DMP_SFG[29]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(FPADDSUB_DMP_SFG[29]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8354211), .RN(n2687), .Q(
FPADDSUB_DMP_exp_NRM_EW[6]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[6]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8354247), .RN(n2687), .Q(
FPADDSUB_DMP_exp_NRM2_EW[6]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_30_ ( .D(FPADDSUB_DMP_SHT1_EWSW[30]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8354229), .RN(n2685), .Q(
FPADDSUB_DMP_SHT2_EWSW[30]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_30_ ( .D(FPADDSUB_DMP_SHT2_EWSW[30]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2687), .Q(
FPADDSUB_DMP_SFG[30]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(FPADDSUB_DMP_SFG[30]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8354211), .RN(n2687), .Q(
FPADDSUB_DMP_exp_NRM_EW[7]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[7]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8354247), .RN(n2687), .Q(
FPADDSUB_DMP_exp_NRM2_EW[7]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_25_ ( .D(FPADDSUB_Data_array_SWR[25]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8354211), .RN(n2684), .Q(
FPADDSUB_Data_array_SWR[50]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
FPSENCOS_d_ff4_Xn_net8354463), .RN(n2707), .Q(FPSENCOS_d_ff_Xn[22]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_22_ ( .D(
FPSENCOS_first_mux_X[22]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n919), .Q(FPSENCOS_d_ff2_X[22]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_22_ ( .D(FPSENCOS_d_ff2_X[22]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2717), .Q(
FPSENCOS_d_ff3_sh_x_out[22]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
FPSENCOS_d_ff4_Yn_net8354463), .RN(n1104), .Q(FPSENCOS_d_ff_Yn[22]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_22_ ( .D(
FPSENCOS_first_mux_Y[22]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n919), .Q(FPSENCOS_d_ff2_Y[22]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_22_ ( .D(FPSENCOS_d_ff2_Y[22]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2713), .Q(
FPSENCOS_d_ff3_sh_y_out[22]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_22_ ( .D(FPSENCOS_mux_sal[22]), .CK(
FPSENCOS_d_ff5_data_out_net8354463), .RN(n2713), .Q(cordic_result[22])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
FPSENCOS_d_ff4_Zn_net8354463), .RN(n2713), .Q(FPSENCOS_d_ff_Zn[22]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_22_ ( .D(
FPSENCOS_first_mux_Z[22]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2713), .Q(FPSENCOS_d_ff2_Z[22]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_22_ ( .D(FPADDSUB_DmP_INIT_EWSW[22]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2682), .Q(
FPADDSUB_DmP_EXP_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(
FPADDSUB_DmP_EXP_EWSW[22]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8354229),
.RN(n2695), .Q(FPADDSUB_DmP_mant_SHT1_SW[22]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
FPSENCOS_d_ff4_Xn_net8354463), .RN(n2713), .Q(FPSENCOS_d_ff_Xn[19]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_19_ ( .D(
FPSENCOS_first_mux_X[19]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2713), .Q(FPSENCOS_d_ff2_X[19]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_19_ ( .D(FPSENCOS_d_ff2_X[19]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2713), .Q(
FPSENCOS_d_ff3_sh_x_out[19]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
FPSENCOS_d_ff4_Yn_net8354463), .RN(n2713), .Q(FPSENCOS_d_ff_Yn[19]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_19_ ( .D(
FPSENCOS_first_mux_Y[19]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2713), .Q(FPSENCOS_d_ff2_Y[19]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_19_ ( .D(FPSENCOS_d_ff2_Y[19]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2713), .Q(
FPSENCOS_d_ff3_sh_y_out[19]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_19_ ( .D(FPSENCOS_mux_sal[19]), .CK(
FPSENCOS_d_ff5_data_out_net8354463), .RN(n2713), .Q(cordic_result[19])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
FPSENCOS_d_ff4_Zn_net8354463), .RN(n1102), .Q(FPSENCOS_d_ff_Zn[19]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_19_ ( .D(
FPSENCOS_first_mux_Z[19]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2712), .Q(FPSENCOS_d_ff2_Z[19]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_19_ ( .D(FPADDSUB_DmP_INIT_EWSW[19]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2676), .Q(
FPADDSUB_DmP_EXP_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(
FPADDSUB_DmP_EXP_EWSW[19]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8354229),
.RN(n2691), .Q(FPADDSUB_DmP_mant_SHT1_SW[19]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_2_ ( .D(FPADDSUB_Data_array_SWR[2]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8354211), .RN(n2678), .Q(
FPADDSUB_Data_array_SWR[28]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
FPSENCOS_d_ff4_Xn_net8354463), .RN(n2712), .Q(FPSENCOS_d_ff_Xn[21]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_21_ ( .D(
FPSENCOS_first_mux_X[21]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2712), .Q(FPSENCOS_d_ff2_X[21]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_21_ ( .D(FPSENCOS_d_ff2_X[21]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2712), .Q(
FPSENCOS_d_ff3_sh_x_out[21]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
FPSENCOS_d_ff4_Yn_net8354463), .RN(n2712), .Q(FPSENCOS_d_ff_Yn[21]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_21_ ( .D(
FPSENCOS_first_mux_Y[21]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2712), .Q(FPSENCOS_d_ff2_Y[21]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_21_ ( .D(FPSENCOS_d_ff2_Y[21]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2712), .Q(
FPSENCOS_d_ff3_sh_y_out[21]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_21_ ( .D(FPSENCOS_mux_sal[21]), .CK(
FPSENCOS_d_ff5_data_out_net8354463), .RN(n2712), .Q(cordic_result[21])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
FPSENCOS_d_ff4_Zn_net8354463), .RN(n2712), .Q(FPSENCOS_d_ff_Zn[21]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_21_ ( .D(
FPSENCOS_first_mux_Z[21]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2712), .Q(FPSENCOS_d_ff2_Z[21]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_21_ ( .D(FPADDSUB_DmP_INIT_EWSW[21]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2685), .Q(
FPADDSUB_DmP_EXP_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(
FPADDSUB_DmP_EXP_EWSW[21]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8354229),
.RN(n1105), .Q(FPADDSUB_DmP_mant_SHT1_SW[21]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(
FPSENCOS_d_ff4_Xn_net8354463), .RN(n2712), .Q(FPSENCOS_d_ff_Xn[2]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_2_ ( .D(FPSENCOS_first_mux_X[2]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2712), .Q(
FPSENCOS_d_ff2_X[2]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_2_ ( .D(FPSENCOS_d_ff2_X[2]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2699), .Q(
FPSENCOS_d_ff3_sh_x_out[2]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(
FPSENCOS_d_ff4_Yn_net8354463), .RN(n2700), .Q(FPSENCOS_d_ff_Yn[2]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_2_ ( .D(FPSENCOS_first_mux_Y[2]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2711), .Q(
FPSENCOS_d_ff2_Y[2]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_2_ ( .D(FPSENCOS_d_ff2_Y[2]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n1102), .Q(
FPSENCOS_d_ff3_sh_y_out[2]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_2_ ( .D(FPSENCOS_mux_sal[2]), .CK(
FPSENCOS_d_ff5_data_out_net8354463), .RN(n2704), .Q(cordic_result[2])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(
FPSENCOS_d_ff4_Zn_net8354463), .RN(n2704), .Q(FPSENCOS_d_ff_Zn[2]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_2_ ( .D(FPSENCOS_first_mux_Z[2]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2704), .Q(
FPSENCOS_d_ff2_Z[2]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_2_ ( .D(FPADDSUB_DmP_INIT_EWSW[2]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2688), .Q(
FPADDSUB_DmP_EXP_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(FPADDSUB_DmP_EXP_EWSW[2]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n913), .Q(
FPADDSUB_DmP_mant_SHT1_SW[2]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
FPSENCOS_d_ff4_Xn_net8354463), .RN(n2704), .Q(FPSENCOS_d_ff_Xn[16]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_16_ ( .D(
FPSENCOS_first_mux_X[16]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2704), .Q(FPSENCOS_d_ff2_X[16]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_16_ ( .D(FPSENCOS_d_ff2_X[16]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2704), .Q(
FPSENCOS_d_ff3_sh_x_out[16]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
FPSENCOS_d_ff4_Yn_net8354463), .RN(n2704), .Q(FPSENCOS_d_ff_Yn[16]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_16_ ( .D(
FPSENCOS_first_mux_Y[16]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n1102), .Q(FPSENCOS_d_ff2_Y[16]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_16_ ( .D(FPSENCOS_d_ff2_Y[16]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2704), .Q(
FPSENCOS_d_ff3_sh_y_out[16]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_16_ ( .D(FPSENCOS_mux_sal[16]), .CK(
FPSENCOS_d_ff5_data_out_net8354463), .RN(n1102), .Q(cordic_result[16])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
FPSENCOS_d_ff4_Zn_net8354463), .RN(n2704), .Q(FPSENCOS_d_ff_Zn[16]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_16_ ( .D(
FPSENCOS_first_mux_Z[16]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2703), .Q(FPSENCOS_d_ff2_Z[16]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_16_ ( .D(FPADDSUB_DmP_INIT_EWSW[16]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2695), .Q(
FPADDSUB_DmP_EXP_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(
FPADDSUB_DmP_EXP_EWSW[16]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8354229),
.RN(n2689), .Q(FPADDSUB_DmP_mant_SHT1_SW[16]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
FPSENCOS_d_ff4_Xn_net8354463), .RN(n2703), .Q(FPSENCOS_d_ff_Xn[18]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_18_ ( .D(
FPSENCOS_first_mux_X[18]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2703), .Q(FPSENCOS_d_ff2_X[18]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_18_ ( .D(FPSENCOS_d_ff2_X[18]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2703), .Q(
FPSENCOS_d_ff3_sh_x_out[18]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
FPSENCOS_d_ff4_Yn_net8354463), .RN(n2703), .Q(FPSENCOS_d_ff_Yn[18]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_18_ ( .D(
FPSENCOS_first_mux_Y[18]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2703), .Q(FPSENCOS_d_ff2_Y[18]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_18_ ( .D(FPSENCOS_d_ff2_Y[18]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2703), .Q(
FPSENCOS_d_ff3_sh_y_out[18]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_18_ ( .D(FPSENCOS_mux_sal[18]), .CK(
FPSENCOS_d_ff5_data_out_net8354463), .RN(n2703), .Q(cordic_result[18])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
FPSENCOS_d_ff4_Zn_net8354463), .RN(n2703), .Q(FPSENCOS_d_ff_Zn[18]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_18_ ( .D(
FPSENCOS_first_mux_Z[18]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2703), .Q(FPSENCOS_d_ff2_Z[18]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_18_ ( .D(FPADDSUB_DmP_INIT_EWSW[18]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2676), .Q(
FPADDSUB_DmP_EXP_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(
FPADDSUB_DmP_EXP_EWSW[18]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8354229),
.RN(n2691), .Q(FPADDSUB_DmP_mant_SHT1_SW[18]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_3_ ( .D(FPADDSUB_Data_array_SWR[3]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8354211), .RN(n913), .Q(
FPADDSUB_Data_array_SWR[29]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
FPSENCOS_d_ff4_Xn_net8354463), .RN(n2703), .Q(FPSENCOS_d_ff_Xn[20]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_20_ ( .D(
FPSENCOS_first_mux_X[20]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2703), .Q(FPSENCOS_d_ff2_X[20]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_20_ ( .D(FPSENCOS_d_ff2_X[20]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2702), .Q(
FPSENCOS_d_ff3_sh_x_out[20]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
FPSENCOS_d_ff4_Yn_net8354463), .RN(n2702), .Q(FPSENCOS_d_ff_Yn[20]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_20_ ( .D(
FPSENCOS_first_mux_Y[20]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2702), .Q(FPSENCOS_d_ff2_Y[20]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_20_ ( .D(FPSENCOS_d_ff2_Y[20]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2702), .Q(
FPSENCOS_d_ff3_sh_y_out[20]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_20_ ( .D(FPSENCOS_mux_sal[20]), .CK(
FPSENCOS_d_ff5_data_out_net8354463), .RN(n2702), .Q(cordic_result[20])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
FPSENCOS_d_ff4_Zn_net8354463), .RN(n2702), .Q(FPSENCOS_d_ff_Zn[20]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_20_ ( .D(
FPSENCOS_first_mux_Z[20]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2702), .Q(FPSENCOS_d_ff2_Z[20]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_20_ ( .D(FPADDSUB_DmP_INIT_EWSW[20]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2689), .Q(
FPADDSUB_DmP_EXP_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(
FPADDSUB_DmP_EXP_EWSW[20]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8354229),
.RN(n2685), .Q(FPADDSUB_DmP_mant_SHT1_SW[20]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
FPSENCOS_d_ff4_Xn_net8354463), .RN(n2702), .Q(FPSENCOS_d_ff_Xn[17]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_17_ ( .D(
FPSENCOS_first_mux_X[17]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2702), .Q(FPSENCOS_d_ff2_X[17]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_17_ ( .D(FPSENCOS_d_ff2_X[17]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2702), .Q(
FPSENCOS_d_ff3_sh_x_out[17]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
FPSENCOS_d_ff4_Yn_net8354463), .RN(n2702), .Q(FPSENCOS_d_ff_Yn[17]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_17_ ( .D(
FPSENCOS_first_mux_Y[17]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2702), .Q(FPSENCOS_d_ff2_Y[17]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_17_ ( .D(FPSENCOS_d_ff2_Y[17]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2700), .Q(
FPSENCOS_d_ff3_sh_y_out[17]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_17_ ( .D(FPSENCOS_mux_sal[17]), .CK(
FPSENCOS_d_ff5_data_out_net8354463), .RN(n2698), .Q(cordic_result[17])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
FPSENCOS_d_ff4_Zn_net8354463), .RN(n2701), .Q(FPSENCOS_d_ff_Zn[17]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_17_ ( .D(
FPSENCOS_first_mux_Z[17]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2699), .Q(FPSENCOS_d_ff2_Z[17]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_17_ ( .D(FPADDSUB_DmP_INIT_EWSW[17]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2693), .Q(
FPADDSUB_DmP_EXP_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(
FPADDSUB_DmP_EXP_EWSW[17]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8354229),
.RN(n2681), .Q(FPADDSUB_DmP_mant_SHT1_SW[17]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(
FPSENCOS_d_ff4_Xn_net8354463), .RN(n916), .Q(FPSENCOS_d_ff_Xn[4]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_4_ ( .D(FPSENCOS_first_mux_X[4]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2700), .Q(
FPSENCOS_d_ff2_X[4]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_4_ ( .D(FPSENCOS_d_ff2_X[4]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2698), .Q(
FPSENCOS_d_ff3_sh_x_out[4]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(
FPSENCOS_d_ff4_Yn_net8354463), .RN(n2701), .Q(FPSENCOS_d_ff_Yn[4]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_4_ ( .D(FPSENCOS_first_mux_Y[4]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2699), .Q(
FPSENCOS_d_ff2_Y[4]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_4_ ( .D(FPSENCOS_d_ff2_Y[4]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n916), .Q(
FPSENCOS_d_ff3_sh_y_out[4]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_4_ ( .D(FPSENCOS_mux_sal[4]), .CK(
FPSENCOS_d_ff5_data_out_net8354463), .RN(n2700), .Q(cordic_result[4])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(
FPSENCOS_d_ff4_Zn_net8354463), .RN(n2698), .Q(FPSENCOS_d_ff_Zn[4]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_4_ ( .D(FPSENCOS_first_mux_Z[4]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n916), .Q(
FPSENCOS_d_ff2_Z[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_4_ ( .D(FPADDSUB_DmP_INIT_EWSW[4]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2687), .Q(
FPADDSUB_DmP_EXP_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(FPADDSUB_DmP_EXP_EWSW[4]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n913), .Q(
FPADDSUB_DmP_mant_SHT1_SW[4]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
FPSENCOS_d_ff4_Xn_net8354463), .RN(n916), .Q(FPSENCOS_d_ff_Xn[15]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_15_ ( .D(
FPSENCOS_first_mux_X[15]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n916), .Q(FPSENCOS_d_ff2_X[15]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_15_ ( .D(FPSENCOS_d_ff2_X[15]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n916), .Q(
FPSENCOS_d_ff3_sh_x_out[15]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
FPSENCOS_d_ff4_Yn_net8354463), .RN(n916), .Q(FPSENCOS_d_ff_Yn[15]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_15_ ( .D(
FPSENCOS_first_mux_Y[15]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n916), .Q(FPSENCOS_d_ff2_Y[15]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_15_ ( .D(FPSENCOS_d_ff2_Y[15]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n916), .Q(
FPSENCOS_d_ff3_sh_y_out[15]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_15_ ( .D(FPSENCOS_mux_sal[15]), .CK(
FPSENCOS_d_ff5_data_out_net8354463), .RN(n916), .Q(cordic_result[15])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
FPSENCOS_d_ff4_Zn_net8354463), .RN(n916), .Q(FPSENCOS_d_ff_Zn[15]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_15_ ( .D(
FPSENCOS_first_mux_Z[15]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n916), .Q(FPSENCOS_d_ff2_Z[15]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_15_ ( .D(FPADDSUB_DmP_INIT_EWSW[15]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2694), .Q(
FPADDSUB_DmP_EXP_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(
FPADDSUB_DmP_EXP_EWSW[15]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8354229),
.RN(n2690), .Q(FPADDSUB_DmP_mant_SHT1_SW[15]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(
FPSENCOS_d_ff4_Xn_net8354463), .RN(n916), .Q(FPSENCOS_d_ff_Xn[5]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_5_ ( .D(FPSENCOS_first_mux_X[5]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n916), .Q(
FPSENCOS_d_ff2_X[5]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_5_ ( .D(FPSENCOS_d_ff2_X[5]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2699), .Q(
FPSENCOS_d_ff3_sh_x_out[5]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(
FPSENCOS_d_ff4_Yn_net8354463), .RN(n2700), .Q(FPSENCOS_d_ff_Yn[5]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_5_ ( .D(FPSENCOS_first_mux_Y[5]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2701), .Q(
FPSENCOS_d_ff2_Y[5]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_5_ ( .D(FPSENCOS_d_ff2_Y[5]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2699), .Q(
FPSENCOS_d_ff3_sh_y_out[5]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_5_ ( .D(FPSENCOS_mux_sal[5]), .CK(
FPSENCOS_d_ff5_data_out_net8354463), .RN(n2700), .Q(cordic_result[5])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(
FPSENCOS_d_ff4_Zn_net8354463), .RN(n2701), .Q(FPSENCOS_d_ff_Zn[5]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_5_ ( .D(FPSENCOS_first_mux_Z[5]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2699), .Q(
FPSENCOS_d_ff2_Z[5]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_5_ ( .D(FPADDSUB_DmP_INIT_EWSW[5]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n1105), .Q(
FPADDSUB_DmP_EXP_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(FPADDSUB_DmP_EXP_EWSW[5]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n2693), .Q(
FPADDSUB_DmP_mant_SHT1_SW[5]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
FPSENCOS_d_ff4_Xn_net8354463), .RN(n2700), .Q(FPSENCOS_d_ff_Xn[13]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_13_ ( .D(
FPSENCOS_first_mux_X[13]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2701), .Q(FPSENCOS_d_ff2_X[13]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_13_ ( .D(FPSENCOS_d_ff2_X[13]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2699), .Q(
FPSENCOS_d_ff3_sh_x_out[13]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
FPSENCOS_d_ff4_Yn_net8354463), .RN(n916), .Q(FPSENCOS_d_ff_Yn[13]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_13_ ( .D(
FPSENCOS_first_mux_Y[13]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2704), .Q(FPSENCOS_d_ff2_Y[13]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_13_ ( .D(FPSENCOS_d_ff2_Y[13]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n1102), .Q(
FPSENCOS_d_ff3_sh_y_out[13]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_13_ ( .D(FPSENCOS_mux_sal[13]), .CK(
FPSENCOS_d_ff5_data_out_net8354463), .RN(n1102), .Q(cordic_result[13])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
FPSENCOS_d_ff4_Zn_net8354463), .RN(n1102), .Q(FPSENCOS_d_ff_Zn[13]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_13_ ( .D(
FPSENCOS_first_mux_Z[13]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2707), .Q(FPSENCOS_d_ff2_Z[13]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_13_ ( .D(FPADDSUB_DmP_INIT_EWSW[13]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2682), .Q(
FPADDSUB_DmP_EXP_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(
FPADDSUB_DmP_EXP_EWSW[13]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8354229),
.RN(n913), .Q(FPADDSUB_DmP_mant_SHT1_SW[13]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_9_ ( .D(FPADDSUB_Data_array_SWR[9]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8354211), .RN(n2686), .QN(n941) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
FPSENCOS_d_ff4_Xn_net8354463), .RN(n2728), .Q(FPSENCOS_d_ff_Xn[14]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_14_ ( .D(
FPSENCOS_first_mux_X[14]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2707), .Q(FPSENCOS_d_ff2_X[14]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_14_ ( .D(FPSENCOS_d_ff2_X[14]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2707), .Q(
FPSENCOS_d_ff3_sh_x_out[14]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
FPSENCOS_d_ff4_Yn_net8354463), .RN(n2708), .Q(FPSENCOS_d_ff_Yn[14]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_14_ ( .D(
FPSENCOS_first_mux_Y[14]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2707), .Q(FPSENCOS_d_ff2_Y[14]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_14_ ( .D(FPSENCOS_d_ff2_Y[14]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2715), .Q(
FPSENCOS_d_ff3_sh_y_out[14]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_14_ ( .D(FPSENCOS_mux_sal[14]), .CK(
FPSENCOS_d_ff5_data_out_net8354463), .RN(n2707), .Q(cordic_result[14])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
FPSENCOS_d_ff4_Zn_net8354463), .RN(n2711), .Q(FPSENCOS_d_ff_Zn[14]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_14_ ( .D(
FPSENCOS_first_mux_Z[14]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2711), .Q(FPSENCOS_d_ff2_Z[14]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_14_ ( .D(FPADDSUB_DmP_INIT_EWSW[14]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2688), .Q(
FPADDSUB_DmP_EXP_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(
FPADDSUB_DmP_EXP_EWSW[14]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8354229),
.RN(n1105), .Q(FPADDSUB_DmP_mant_SHT1_SW[14]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
FPSENCOS_d_ff4_Xn_net8354463), .RN(n2711), .Q(FPSENCOS_d_ff_Xn[11]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_11_ ( .D(
FPSENCOS_first_mux_X[11]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2711), .Q(FPSENCOS_d_ff2_X[11]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_11_ ( .D(FPSENCOS_d_ff2_X[11]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2711), .Q(
FPSENCOS_d_ff3_sh_x_out[11]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
FPSENCOS_d_ff4_Yn_net8354463), .RN(n2711), .Q(FPSENCOS_d_ff_Yn[11]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_11_ ( .D(
FPSENCOS_first_mux_Y[11]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2711), .Q(FPSENCOS_d_ff2_Y[11]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_11_ ( .D(FPSENCOS_d_ff2_Y[11]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2711), .Q(
FPSENCOS_d_ff3_sh_y_out[11]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_11_ ( .D(FPSENCOS_mux_sal[11]), .CK(
FPSENCOS_d_ff5_data_out_net8354463), .RN(n2711), .Q(cordic_result[11])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
FPSENCOS_d_ff4_Zn_net8354463), .RN(n2711), .Q(FPSENCOS_d_ff_Zn[11]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_11_ ( .D(
FPSENCOS_first_mux_Z[11]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2711), .Q(FPSENCOS_d_ff2_Z[11]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_11_ ( .D(FPADDSUB_DmP_INIT_EWSW[11]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2681), .Q(
FPADDSUB_DmP_EXP_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(
FPADDSUB_DmP_EXP_EWSW[11]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8354229),
.RN(n2686), .Q(FPADDSUB_DmP_mant_SHT1_SW[11]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(
FPSENCOS_d_ff4_Xn_net8354463), .RN(n2699), .Q(FPSENCOS_d_ff_Xn[8]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_8_ ( .D(FPSENCOS_first_mux_X[8]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2701), .Q(
FPSENCOS_d_ff2_X[8]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_8_ ( .D(FPSENCOS_d_ff2_X[8]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2699), .Q(
FPSENCOS_d_ff3_sh_x_out[8]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(
FPSENCOS_d_ff4_Yn_net8354463), .RN(n916), .Q(FPSENCOS_d_ff_Yn[8]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_8_ ( .D(FPSENCOS_first_mux_Y[8]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2700), .Q(
FPSENCOS_d_ff2_Y[8]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_8_ ( .D(FPSENCOS_d_ff2_Y[8]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2698), .Q(
FPSENCOS_d_ff3_sh_y_out[8]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_8_ ( .D(FPSENCOS_mux_sal[8]), .CK(
FPSENCOS_d_ff5_data_out_net8354463), .RN(n2701), .Q(cordic_result[8])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(
FPSENCOS_d_ff4_Zn_net8354463), .RN(n2699), .Q(FPSENCOS_d_ff_Zn[8]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_8_ ( .D(FPSENCOS_first_mux_Z[8]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n916), .Q(
FPSENCOS_d_ff2_Z[8]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_8_ ( .D(FPADDSUB_DmP_INIT_EWSW[8]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2690), .Q(
FPADDSUB_DmP_EXP_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(FPADDSUB_DmP_EXP_EWSW[8]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n2687), .Q(
FPADDSUB_DmP_mant_SHT1_SW[8]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
FPSENCOS_d_ff4_Xn_net8354463), .RN(n2700), .Q(FPSENCOS_d_ff_Xn[10]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_10_ ( .D(
FPSENCOS_first_mux_X[10]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2698), .Q(FPSENCOS_d_ff2_X[10]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_10_ ( .D(FPSENCOS_d_ff2_X[10]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2701), .Q(
FPSENCOS_d_ff3_sh_x_out[10]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
FPSENCOS_d_ff4_Yn_net8354463), .RN(n2699), .Q(FPSENCOS_d_ff_Yn[10]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_10_ ( .D(
FPSENCOS_first_mux_Y[10]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n947), .Q(FPSENCOS_d_ff2_Y[10]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_10_ ( .D(FPSENCOS_d_ff2_Y[10]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n947), .Q(
FPSENCOS_d_ff3_sh_y_out[10]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_10_ ( .D(FPSENCOS_mux_sal[10]), .CK(
FPSENCOS_d_ff5_data_out_net8354463), .RN(n947), .Q(cordic_result[10])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
FPSENCOS_d_ff4_Zn_net8354463), .RN(n947), .Q(FPSENCOS_d_ff_Zn[10]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_10_ ( .D(
FPSENCOS_first_mux_Z[10]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n947), .Q(FPSENCOS_d_ff2_Z[10]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_10_ ( .D(FPADDSUB_DmP_INIT_EWSW[10]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2682), .Q(
FPADDSUB_DmP_EXP_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(
FPADDSUB_DmP_EXP_EWSW[10]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8354229),
.RN(n2694), .Q(FPADDSUB_DmP_mant_SHT1_SW[10]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
FPSENCOS_d_ff4_Xn_net8354463), .RN(n947), .Q(FPSENCOS_d_ff_Xn[12]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_12_ ( .D(
FPSENCOS_first_mux_X[12]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n947), .Q(FPSENCOS_d_ff2_X[12]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_12_ ( .D(FPSENCOS_d_ff2_X[12]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n947), .Q(
FPSENCOS_d_ff3_sh_x_out[12]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
FPSENCOS_d_ff4_Yn_net8354463), .RN(n947), .Q(FPSENCOS_d_ff_Yn[12]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_12_ ( .D(
FPSENCOS_first_mux_Y[12]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n947), .Q(FPSENCOS_d_ff2_Y[12]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_12_ ( .D(FPSENCOS_d_ff2_Y[12]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n947), .Q(
FPSENCOS_d_ff3_sh_y_out[12]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_12_ ( .D(FPSENCOS_mux_sal[12]), .CK(
FPSENCOS_d_ff5_data_out_net8354463), .RN(n2701), .Q(cordic_result[12])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
FPSENCOS_d_ff4_Zn_net8354463), .RN(n918), .Q(FPSENCOS_d_ff_Zn[12]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_12_ ( .D(
FPSENCOS_first_mux_Z[12]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n917), .Q(FPSENCOS_d_ff2_Z[12]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_12_ ( .D(FPADDSUB_DmP_INIT_EWSW[12]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2680), .Q(
FPADDSUB_DmP_EXP_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(
FPADDSUB_DmP_EXP_EWSW[12]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8354229),
.RN(n2682), .Q(FPADDSUB_DmP_mant_SHT1_SW[12]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(
FPSENCOS_d_ff4_Xn_net8354463), .RN(n917), .Q(FPSENCOS_d_ff_Xn[9]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_9_ ( .D(FPSENCOS_first_mux_X[9]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n918), .Q(
FPSENCOS_d_ff2_X[9]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_9_ ( .D(FPSENCOS_d_ff2_X[9]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2711), .Q(
FPSENCOS_d_ff3_sh_x_out[9]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(
FPSENCOS_d_ff4_Yn_net8354463), .RN(n2705), .Q(FPSENCOS_d_ff_Yn[9]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_9_ ( .D(FPSENCOS_first_mux_Y[9]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n918), .Q(
FPSENCOS_d_ff2_Y[9]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_9_ ( .D(FPSENCOS_d_ff2_Y[9]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2710), .Q(
FPSENCOS_d_ff3_sh_y_out[9]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_9_ ( .D(FPSENCOS_mux_sal[9]), .CK(
FPSENCOS_d_ff5_data_out_net8354463), .RN(n917), .Q(cordic_result[9])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(
FPSENCOS_d_ff4_Zn_net8354463), .RN(n917), .Q(FPSENCOS_d_ff_Zn[9]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_9_ ( .D(FPSENCOS_first_mux_Z[9]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n919), .Q(
FPSENCOS_d_ff2_Z[9]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
FPSENCOS_d_ff4_Xn_net8354463), .RN(n2712), .Q(FPSENCOS_d_ff_Xn[31]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_31_ ( .D(
FPSENCOS_first_mux_X[31]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2708), .Q(FPSENCOS_d_ff2_X[31]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_31_ ( .D(FPSENCOS_d_ff2_X[31]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2704), .Q(
FPSENCOS_d_ff3_sh_x_out[31]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
FPSENCOS_d_ff4_Yn_net8354463), .RN(n2712), .Q(FPSENCOS_d_ff_Yn[31]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_31_ ( .D(FPSENCOS_fmtted_Result_31_),
.CK(FPSENCOS_d_ff5_data_out_net8354463), .RN(n2708), .Q(
cordic_result[31]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_31_ ( .D(
FPSENCOS_first_mux_Y[31]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n918), .Q(FPSENCOS_d_ff2_Y[31]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_31_ ( .D(FPSENCOS_d_ff2_Y[31]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2703), .Q(
FPSENCOS_d_ff3_sh_y_out[31]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
FPSENCOS_d_ff4_Zn_net8354463), .RN(n2704), .Q(FPSENCOS_d_ff_Zn[31]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_31_ ( .D(
FPSENCOS_first_mux_Z[31]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n918), .Q(FPSENCOS_d_ff2_Z[31]) );
DFFRXLTS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(add_subt_data1[31]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2688), .Q(
FPADDSUB_intDX_EWSW[31]) );
DFFRXLTS FPSENCOS_reg_sign_Q_reg_0_ ( .D(FPSENCOS_d_ff2_Z[31]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2703), .Q(
FPSENCOS_d_ff3_sign_out) );
DFFRXLTS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(n969), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8354211), .RN(n2683), .QN(n937) );
DFFRXLTS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n2673), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8354211), .RN(n1105), .Q(
FPADDSUB_left_right_SHT2) );
DFFRXLTS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(FPADDSUB_Raw_mant_SGF[1]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8354211), .RN(n2682), .Q(
FPADDSUB_Raw_mant_NRM_SWR[1]), .QN(n2557) );
DFFRXLTS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(
FPADDSUB_Raw_mant_SGF[12]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8354211), .RN(n2684), .QN(n931) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(
FPADDSUB_LZD_raw_out_EWR[3]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8354247), .RN(n2697), .Q(
FPADDSUB_LZD_output_NRM2_EW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(
FPADDSUB_LZD_raw_out_EWR[0]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8354247), .RN(n2697), .Q(
FPADDSUB_LZD_output_NRM2_EW[0]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(
FPADDSUB_LZD_raw_out_EWR[2]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8354247), .RN(n2697), .Q(
FPADDSUB_LZD_output_NRM2_EW[2]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(
FPADDSUB_LZD_raw_out_EWR[1]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8354247), .RN(n2697), .Q(
FPADDSUB_LZD_output_NRM2_EW[1]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(
FPADDSUB_LZD_raw_out_EWR[4]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8354247), .RN(n2697), .Q(
FPADDSUB_LZD_output_NRM2_EW[4]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(
FPSENCOS_d_ff4_Xn_net8354463), .RN(n2704), .Q(FPSENCOS_d_ff_Xn[0]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_0_ ( .D(FPSENCOS_first_mux_X[0]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2728), .Q(
FPSENCOS_d_ff2_X[0]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_0_ ( .D(FPSENCOS_d_ff2_X[0]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2707), .Q(
FPSENCOS_d_ff3_sh_x_out[0]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(
FPSENCOS_d_ff4_Yn_net8354463), .RN(n919), .Q(FPSENCOS_d_ff_Yn[0]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_0_ ( .D(FPSENCOS_first_mux_Y[0]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2717), .Q(
FPSENCOS_d_ff2_Y[0]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_0_ ( .D(FPSENCOS_d_ff2_Y[0]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n1104), .Q(
FPSENCOS_d_ff3_sh_y_out[0]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_0_ ( .D(FPSENCOS_mux_sal[0]), .CK(
FPSENCOS_d_ff5_data_out_net8354463), .RN(n919), .Q(cordic_result[0])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(
FPSENCOS_d_ff4_Zn_net8354463), .RN(n2716), .Q(FPSENCOS_d_ff_Zn[0]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_0_ ( .D(FPSENCOS_first_mux_Z[0]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2728), .Q(
FPSENCOS_d_ff2_Z[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_0_ ( .D(FPADDSUB_DmP_INIT_EWSW[0]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2690), .Q(
FPADDSUB_DmP_EXP_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(FPADDSUB_DmP_EXP_EWSW[0]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n2684), .Q(
FPADDSUB_DmP_mant_SHT1_SW[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_0_ ( .D(FPADDSUB_DMP_INIT_EWSW[0]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2680), .Q(
FPADDSUB_DMP_EXP_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_0_ ( .D(FPADDSUB_DMP_EXP_EWSW[0]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n2682), .Q(
FPADDSUB_DMP_SHT1_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_0_ ( .D(FPADDSUB_DMP_SHT1_EWSW[0]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8354229), .RN(n2695), .Q(
FPADDSUB_DMP_SHT2_EWSW[0]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(
FPSENCOS_d_ff4_Xn_net8354463), .RN(n2707), .Q(FPSENCOS_d_ff_Xn[1]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_1_ ( .D(FPSENCOS_first_mux_X[1]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n919), .Q(
FPSENCOS_d_ff2_X[1]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_1_ ( .D(FPSENCOS_d_ff2_X[1]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2717), .Q(
FPSENCOS_d_ff3_sh_x_out[1]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(
FPSENCOS_d_ff4_Yn_net8354463), .RN(n2716), .Q(FPSENCOS_d_ff_Yn[1]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_1_ ( .D(FPSENCOS_first_mux_Y[1]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2706), .Q(
FPSENCOS_d_ff2_Y[1]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_1_ ( .D(FPSENCOS_d_ff2_Y[1]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2706), .Q(
FPSENCOS_d_ff3_sh_y_out[1]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_1_ ( .D(FPSENCOS_mux_sal[1]), .CK(
FPSENCOS_d_ff5_data_out_net8354463), .RN(n2706), .Q(cordic_result[1])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(
FPSENCOS_d_ff4_Zn_net8354463), .RN(n2706), .Q(FPSENCOS_d_ff_Zn[1]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_1_ ( .D(FPSENCOS_first_mux_Z[1]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2706), .Q(
FPSENCOS_d_ff2_Z[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_1_ ( .D(FPADDSUB_DmP_INIT_EWSW[1]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2689), .Q(
FPADDSUB_DmP_EXP_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(FPADDSUB_DmP_EXP_EWSW[1]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n2683), .Q(
FPADDSUB_DmP_mant_SHT1_SW[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_1_ ( .D(FPADDSUB_DMP_INIT_EWSW[1]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2682), .Q(
FPADDSUB_DMP_EXP_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_1_ ( .D(FPADDSUB_DMP_EXP_EWSW[1]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n2683), .Q(
FPADDSUB_DMP_SHT1_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_1_ ( .D(FPADDSUB_DMP_SHT1_EWSW[1]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8354229), .RN(n913), .Q(
FPADDSUB_DMP_SHT2_EWSW[1]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(
FPSENCOS_d_ff4_Xn_net8354463), .RN(n2706), .Q(FPSENCOS_d_ff_Xn[3]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_3_ ( .D(FPSENCOS_first_mux_X[3]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2706), .Q(
FPSENCOS_d_ff2_X[3]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_3_ ( .D(FPSENCOS_d_ff2_X[3]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2706), .Q(
FPSENCOS_d_ff3_sh_x_out[3]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(
FPSENCOS_d_ff4_Yn_net8354463), .RN(n2706), .Q(FPSENCOS_d_ff_Yn[3]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_3_ ( .D(FPSENCOS_first_mux_Y[3]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2706), .Q(
FPSENCOS_d_ff2_Y[3]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_3_ ( .D(FPSENCOS_d_ff2_Y[3]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2706), .Q(
FPSENCOS_d_ff3_sh_y_out[3]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_3_ ( .D(FPSENCOS_mux_sal[3]), .CK(
FPSENCOS_d_ff5_data_out_net8354463), .RN(n2706), .Q(cordic_result[3])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(
FPSENCOS_d_ff4_Zn_net8354463), .RN(n918), .Q(FPSENCOS_d_ff_Zn[3]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_3_ ( .D(FPSENCOS_first_mux_Z[3]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2711), .Q(
FPSENCOS_d_ff2_Z[3]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_3_ ( .D(FPADDSUB_DmP_INIT_EWSW[3]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2682), .Q(
FPADDSUB_DmP_EXP_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(FPADDSUB_DmP_EXP_EWSW[3]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n2677), .Q(
FPADDSUB_DmP_mant_SHT1_SW[3]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_3_ ( .D(FPADDSUB_DMP_INIT_EWSW[3]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2681), .Q(
FPADDSUB_DMP_EXP_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_3_ ( .D(FPADDSUB_DMP_EXP_EWSW[3]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n2681), .Q(
FPADDSUB_DMP_SHT1_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_3_ ( .D(FPADDSUB_DMP_SHT1_EWSW[3]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8354229), .RN(n2678), .Q(
FPADDSUB_DMP_SHT2_EWSW[3]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(
FPSENCOS_d_ff4_Xn_net8354463), .RN(n2705), .Q(FPSENCOS_d_ff_Xn[6]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_6_ ( .D(FPSENCOS_first_mux_X[6]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n918), .Q(
FPSENCOS_d_ff2_X[6]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_6_ ( .D(FPSENCOS_d_ff2_X[6]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2710), .Q(
FPSENCOS_d_ff3_sh_x_out[6]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(
FPSENCOS_d_ff4_Yn_net8354463), .RN(n917), .Q(FPSENCOS_d_ff_Yn[6]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_6_ ( .D(FPSENCOS_first_mux_Y[6]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n917), .Q(
FPSENCOS_d_ff2_Y[6]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_6_ ( .D(FPSENCOS_d_ff2_Y[6]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n918), .Q(
FPSENCOS_d_ff3_sh_y_out[6]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_6_ ( .D(FPSENCOS_mux_sal[6]), .CK(
FPSENCOS_d_ff5_data_out_net8354463), .RN(n2711), .Q(cordic_result[6])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(
FPSENCOS_d_ff4_Zn_net8354463), .RN(n2705), .Q(FPSENCOS_d_ff_Zn[6]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_6_ ( .D(FPSENCOS_first_mux_Z[6]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n917), .Q(
FPSENCOS_d_ff2_Z[6]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_6_ ( .D(FPADDSUB_DmP_INIT_EWSW[6]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2693), .Q(
FPADDSUB_DmP_EXP_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(FPADDSUB_DmP_EXP_EWSW[6]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n2682), .Q(
FPADDSUB_DmP_mant_SHT1_SW[6]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_6_ ( .D(FPADDSUB_DMP_INIT_EWSW[6]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2677), .Q(
FPADDSUB_DMP_EXP_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_6_ ( .D(FPADDSUB_DMP_EXP_EWSW[6]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n1105), .Q(
FPADDSUB_DMP_SHT1_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_6_ ( .D(FPADDSUB_DMP_SHT1_EWSW[6]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8354229), .RN(n2695), .Q(
FPADDSUB_DMP_SHT2_EWSW[6]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(
FPSENCOS_d_ff4_Xn_net8354463), .RN(n917), .Q(FPSENCOS_d_ff_Xn[7]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_7_ ( .D(FPSENCOS_first_mux_X[7]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n917), .Q(
FPSENCOS_d_ff2_X[7]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_7_ ( .D(FPSENCOS_d_ff2_X[7]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n918), .Q(
FPSENCOS_d_ff3_sh_x_out[7]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(
FPSENCOS_d_ff4_Yn_net8354463), .RN(n917), .Q(FPSENCOS_d_ff_Yn[7]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_7_ ( .D(FPSENCOS_first_mux_Y[7]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2711), .Q(
FPSENCOS_d_ff2_Y[7]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_7_ ( .D(FPSENCOS_d_ff2_Y[7]), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2710), .Q(
FPSENCOS_d_ff3_sh_y_out[7]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_7_ ( .D(FPSENCOS_mux_sal[7]), .CK(
FPSENCOS_d_ff5_data_out_net8354463), .RN(n918), .Q(cordic_result[7])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(
FPSENCOS_d_ff4_Zn_net8354463), .RN(n917), .Q(FPSENCOS_d_ff_Zn[7]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_7_ ( .D(FPSENCOS_first_mux_Z[7]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n918), .Q(
FPSENCOS_d_ff2_Z[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_7_ ( .D(FPADDSUB_DmP_INIT_EWSW[7]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n913), .Q(
FPADDSUB_DmP_EXP_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(FPADDSUB_DmP_EXP_EWSW[7]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n2678), .Q(
FPADDSUB_DmP_mant_SHT1_SW[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_7_ ( .D(FPADDSUB_DMP_INIT_EWSW[7]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2695), .Q(
FPADDSUB_DMP_EXP_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_7_ ( .D(FPADDSUB_DMP_EXP_EWSW[7]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n1105), .Q(
FPADDSUB_DMP_SHT1_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_7_ ( .D(FPADDSUB_DMP_SHT1_EWSW[7]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8354229), .RN(n2686), .Q(
FPADDSUB_DMP_SHT2_EWSW[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_9_ ( .D(FPADDSUB_DmP_INIT_EWSW[9]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2677), .Q(
FPADDSUB_DmP_EXP_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(FPADDSUB_DmP_EXP_EWSW[9]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n2695), .Q(
FPADDSUB_DmP_mant_SHT1_SW[9]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_9_ ( .D(FPADDSUB_DMP_INIT_EWSW[9]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2690), .Q(
FPADDSUB_DMP_EXP_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_9_ ( .D(FPADDSUB_DMP_EXP_EWSW[9]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n2684), .Q(
FPADDSUB_DMP_SHT1_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_9_ ( .D(FPADDSUB_DMP_SHT1_EWSW[9]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8354229), .RN(n2680), .Q(
FPADDSUB_DMP_SHT2_EWSW[9]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_12_ ( .D(FPADDSUB_DMP_INIT_EWSW[12]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2682), .Q(
FPADDSUB_DMP_EXP_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_12_ ( .D(FPADDSUB_DMP_EXP_EWSW[12]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n2695), .Q(
FPADDSUB_DMP_SHT1_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_12_ ( .D(FPADDSUB_DMP_SHT1_EWSW[12]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8354229), .RN(n2689), .Q(
FPADDSUB_DMP_SHT2_EWSW[12]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_10_ ( .D(FPADDSUB_DMP_INIT_EWSW[10]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2676), .Q(
FPADDSUB_DMP_EXP_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_10_ ( .D(FPADDSUB_DMP_EXP_EWSW[10]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n2696), .Q(
FPADDSUB_DMP_SHT1_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_10_ ( .D(FPADDSUB_DMP_SHT1_EWSW[10]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8354229), .RN(n2690), .Q(
FPADDSUB_DMP_SHT2_EWSW[10]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_8_ ( .D(FPADDSUB_DMP_INIT_EWSW[8]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2694), .Q(
FPADDSUB_DMP_EXP_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_8_ ( .D(FPADDSUB_DMP_EXP_EWSW[8]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n2690), .Q(
FPADDSUB_DMP_SHT1_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_8_ ( .D(FPADDSUB_DMP_SHT1_EWSW[8]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8354229), .RN(n2691), .Q(
FPADDSUB_DMP_SHT2_EWSW[8]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_11_ ( .D(FPADDSUB_DMP_INIT_EWSW[11]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2684), .Q(
FPADDSUB_DMP_EXP_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_11_ ( .D(FPADDSUB_DMP_EXP_EWSW[11]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n2696), .Q(
FPADDSUB_DMP_SHT1_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_11_ ( .D(FPADDSUB_DMP_SHT1_EWSW[11]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8354229), .RN(n2690), .Q(
FPADDSUB_DMP_SHT2_EWSW[11]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_14_ ( .D(FPADDSUB_DMP_INIT_EWSW[14]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2687), .Q(
FPADDSUB_DMP_EXP_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_14_ ( .D(FPADDSUB_DMP_EXP_EWSW[14]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n913), .Q(
FPADDSUB_DMP_SHT1_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_14_ ( .D(FPADDSUB_DMP_SHT1_EWSW[14]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8354229), .RN(n2694), .Q(
FPADDSUB_DMP_SHT2_EWSW[14]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_13_ ( .D(FPADDSUB_DMP_INIT_EWSW[13]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2684), .Q(
FPADDSUB_DMP_EXP_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_13_ ( .D(FPADDSUB_DMP_EXP_EWSW[13]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n2680), .Q(
FPADDSUB_DMP_SHT1_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_13_ ( .D(FPADDSUB_DMP_SHT1_EWSW[13]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8354229), .RN(n2682), .Q(
FPADDSUB_DMP_SHT2_EWSW[13]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_5_ ( .D(FPADDSUB_DMP_INIT_EWSW[5]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2695), .Q(
FPADDSUB_DMP_EXP_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_5_ ( .D(FPADDSUB_DMP_EXP_EWSW[5]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n2689), .Q(
FPADDSUB_DMP_SHT1_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_5_ ( .D(FPADDSUB_DMP_SHT1_EWSW[5]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8354229), .RN(n2676), .Q(
FPADDSUB_DMP_SHT2_EWSW[5]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_15_ ( .D(FPADDSUB_DMP_INIT_EWSW[15]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2696), .Q(
FPADDSUB_DMP_EXP_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_15_ ( .D(FPADDSUB_DMP_EXP_EWSW[15]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n2687), .Q(
FPADDSUB_DMP_SHT1_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_15_ ( .D(FPADDSUB_DMP_SHT1_EWSW[15]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8354229), .RN(n2695), .Q(
FPADDSUB_DMP_SHT2_EWSW[15]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_4_ ( .D(FPADDSUB_DMP_INIT_EWSW[4]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2687), .Q(
FPADDSUB_DMP_EXP_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_4_ ( .D(FPADDSUB_DMP_EXP_EWSW[4]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n2695), .Q(
FPADDSUB_DMP_SHT1_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_4_ ( .D(FPADDSUB_DMP_SHT1_EWSW[4]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8354229), .RN(n2680), .Q(
FPADDSUB_DMP_SHT2_EWSW[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_17_ ( .D(FPADDSUB_DMP_INIT_EWSW[17]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2682), .Q(
FPADDSUB_DMP_EXP_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_17_ ( .D(FPADDSUB_DMP_EXP_EWSW[17]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n2697), .Q(
FPADDSUB_DMP_SHT1_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_17_ ( .D(FPADDSUB_DMP_SHT1_EWSW[17]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8354229), .RN(n2696), .Q(
FPADDSUB_DMP_SHT2_EWSW[17]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_20_ ( .D(FPADDSUB_DMP_INIT_EWSW[20]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2697), .Q(
FPADDSUB_DMP_EXP_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_20_ ( .D(FPADDSUB_DMP_EXP_EWSW[20]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n2697), .Q(
FPADDSUB_DMP_SHT1_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_20_ ( .D(FPADDSUB_DMP_SHT1_EWSW[20]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8354229), .RN(n2689), .Q(
FPADDSUB_DMP_SHT2_EWSW[20]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_18_ ( .D(FPADDSUB_DMP_INIT_EWSW[18]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2686), .Q(
FPADDSUB_DMP_EXP_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_18_ ( .D(FPADDSUB_DMP_EXP_EWSW[18]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n913), .Q(
FPADDSUB_DMP_SHT1_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_18_ ( .D(FPADDSUB_DMP_SHT1_EWSW[18]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8354229), .RN(n2677), .Q(
FPADDSUB_DMP_SHT2_EWSW[18]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_16_ ( .D(FPADDSUB_DMP_INIT_EWSW[16]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2685), .Q(
FPADDSUB_DMP_EXP_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_16_ ( .D(FPADDSUB_DMP_EXP_EWSW[16]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n1105), .Q(
FPADDSUB_DMP_SHT1_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_16_ ( .D(FPADDSUB_DMP_SHT1_EWSW[16]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8354229), .RN(n913), .Q(
FPADDSUB_DMP_SHT2_EWSW[16]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_2_ ( .D(FPADDSUB_DMP_INIT_EWSW[2]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2677), .Q(
FPADDSUB_DMP_EXP_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_2_ ( .D(FPADDSUB_DMP_EXP_EWSW[2]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n1105), .Q(
FPADDSUB_DMP_SHT1_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_2_ ( .D(FPADDSUB_DMP_SHT1_EWSW[2]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8354229), .RN(n2681), .Q(
FPADDSUB_DMP_SHT2_EWSW[2]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_21_ ( .D(FPADDSUB_DMP_INIT_EWSW[21]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2685), .Q(
FPADDSUB_DMP_EXP_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_21_ ( .D(FPADDSUB_DMP_EXP_EWSW[21]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n2678), .Q(
FPADDSUB_DMP_SHT1_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_21_ ( .D(FPADDSUB_DMP_SHT1_EWSW[21]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8354229), .RN(n2679), .Q(
FPADDSUB_DMP_SHT2_EWSW[21]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_19_ ( .D(FPADDSUB_DMP_INIT_EWSW[19]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2688), .Q(
FPADDSUB_DMP_EXP_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_19_ ( .D(FPADDSUB_DMP_EXP_EWSW[19]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n2683), .Q(
FPADDSUB_DMP_SHT1_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_19_ ( .D(FPADDSUB_DMP_SHT1_EWSW[19]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8354229), .RN(n2693), .Q(
FPADDSUB_DMP_SHT2_EWSW[19]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_19_ ( .D(FPADDSUB_DMP_SHT2_EWSW[19]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2677), .QN(n923) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_1_ ( .D(FPADDSUB_Data_array_SWR[1]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8354211), .RN(n913), .Q(
FPADDSUB_Data_array_SWR[27]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_0_ ( .D(FPADDSUB_Data_array_SWR[0]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8354211), .RN(n913), .Q(
FPADDSUB_Data_array_SWR[26]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_22_ ( .D(FPADDSUB_DMP_INIT_EWSW[22]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2687), .Q(
FPADDSUB_DMP_EXP_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_22_ ( .D(FPADDSUB_DMP_EXP_EWSW[22]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n1105), .Q(
FPADDSUB_DMP_SHT1_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_22_ ( .D(FPADDSUB_DMP_SHT1_EWSW[22]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8354229), .RN(n2694), .Q(
FPADDSUB_DMP_SHT2_EWSW[22]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[22]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n910), .QN(n925) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[25]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2689), .Q(
FPADDSUB_DmP_mant_SFG_SWR[25]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_47_ ( .D(
FPMULT_Sgf_operation_Result[47]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8354391), .RN(n917), .Q(
FPMULT_P_Sgf[47]) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n927), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8354355), .RN(n2721), .Q(
FPMULT_Add_result[0]) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(
FPMULT_Adder_M_result_A_adder[23]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8354355), .RN(n2725), .Q(
FPMULT_Add_result[23]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_28_ ( .D(Data_2[28]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2726), .Q(
FPMULT_Op_MY[28]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_27_ ( .D(Data_2[27]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2726), .Q(
FPMULT_Op_MY[27]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_26_ ( .D(Data_2[26]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2726), .Q(
FPMULT_Op_MY[26]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_25_ ( .D(Data_2[25]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2723), .Q(
FPMULT_Op_MY[25]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_24_ ( .D(Data_2[24]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2719), .Q(
FPMULT_Op_MY[24]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_23_ ( .D(Data_2[23]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2722), .Q(
FPMULT_Op_MY[23]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_0_ ( .D(Data_2[0]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2727), .QN(n920)
);
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_30_ ( .D(Data_1[30]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2727), .Q(
FPMULT_Op_MX[30]) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_29_ ( .D(Data_1[29]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2727), .Q(
FPMULT_Op_MX[29]) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_25_ ( .D(Data_1[25]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2724), .Q(
FPMULT_Op_MX[25]) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_23_ ( .D(Data_1[23]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2723), .Q(
FPMULT_Op_MX[23]) );
DFFRXLTS FPMULT_Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n115), .CK(
n2788), .RN(n2721), .Q(FPMULT_zero_flag), .QN(n2662) );
DFFRXLTS FPMULT_Exp_module_Underflow_m_Q_reg_0_ ( .D(n2787), .CK(n2788),
.RN(n2721), .Q(underflow_flag_mult), .QN(n2645) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_46_ ( .D(
FPMULT_Sgf_operation_Result[46]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8354391), .RN(n918), .Q(
FPMULT_P_Sgf[46]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_23_ ( .D(
FPMULT_Sgf_operation_Result[23]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8354391), .RN(n2709), .Q(
FPMULT_P_Sgf[23]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_8_ ( .D(
FPMULT_Exp_module_Data_S[8]), .CK(
FPMULT_Exp_module_exp_result_m_net8354409), .RN(n2721), .Q(
FPMULT_exp_oper_result[8]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_7_ ( .D(
FPMULT_Exp_module_Data_S[7]), .CK(
FPMULT_Exp_module_exp_result_m_net8354409), .RN(n2721), .Q(
FPMULT_exp_oper_result[7]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_6_ ( .D(
FPMULT_Exp_module_Data_S[6]), .CK(
FPMULT_Exp_module_exp_result_m_net8354409), .RN(n2724), .Q(
FPMULT_exp_oper_result[6]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_5_ ( .D(
FPMULT_Exp_module_Data_S[5]), .CK(
FPMULT_Exp_module_exp_result_m_net8354409), .RN(n2722), .Q(
FPMULT_exp_oper_result[5]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_4_ ( .D(
FPMULT_Exp_module_Data_S[4]), .CK(
FPMULT_Exp_module_exp_result_m_net8354409), .RN(n2723), .Q(
FPMULT_exp_oper_result[4]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_3_ ( .D(
FPMULT_Exp_module_Data_S[3]), .CK(
FPMULT_Exp_module_exp_result_m_net8354409), .RN(n2726), .Q(
FPMULT_exp_oper_result[3]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_2_ ( .D(
FPMULT_Exp_module_Data_S[2]), .CK(
FPMULT_Exp_module_exp_result_m_net8354409), .RN(n2719), .Q(
FPMULT_exp_oper_result[2]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_1_ ( .D(
FPMULT_Exp_module_Data_S[1]), .CK(
FPMULT_Exp_module_exp_result_m_net8354409), .RN(n2720), .Q(
FPMULT_exp_oper_result[1]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_0_ ( .D(
FPMULT_Exp_module_Data_S[0]), .CK(
FPMULT_Exp_module_exp_result_m_net8354409), .RN(n2725), .Q(
FPMULT_exp_oper_result[0]) );
DFFRXLTS FPMULT_Exp_module_Oflow_A_m_Q_reg_0_ ( .D(
FPMULT_Exp_module_Overflow_A), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8354391), .RN(n2724), .Q(
FPMULT_Exp_module_Overflow_flag_A) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n2816), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8354373), .RN(n2722), .Q(
FPMULT_Sgf_normalized_result[23]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n2814), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8354373), .RN(n2723), .Q(
FPMULT_Sgf_normalized_result[21]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n2812), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8354373), .RN(n2719), .Q(
FPMULT_Sgf_normalized_result[19]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n2810), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8354373), .RN(n2720), .Q(
FPMULT_Sgf_normalized_result[17]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n2808), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8354373), .RN(n2725), .Q(
FPMULT_Sgf_normalized_result[15]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n2806), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8354373), .RN(n2724), .Q(
FPMULT_Sgf_normalized_result[13]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n2804), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8354373), .RN(n2722), .Q(
FPMULT_Sgf_normalized_result[11]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n2802), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8354373), .RN(n2723), .Q(
FPMULT_Sgf_normalized_result[9]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n2800), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8354373), .RN(n2722), .Q(
FPMULT_Sgf_normalized_result[7]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n2798), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8354373), .RN(n2725), .Q(
FPMULT_Sgf_normalized_result[5]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n2796), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8354373), .RN(n2720), .Q(
FPMULT_Sgf_normalized_result[3]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[0]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8354175), .RN(
n2723), .Q(mult_result[0]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[1]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8354175), .RN(
n2724), .Q(mult_result[1]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[2]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8354175), .RN(
n2722), .Q(mult_result[2]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[3]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8354175), .RN(
n2724), .Q(mult_result[3]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[4]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8354175), .RN(
n2722), .Q(mult_result[4]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[5]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8354175), .RN(
n2723), .Q(mult_result[5]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[6]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8354175), .RN(
n2726), .Q(mult_result[6]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[7]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8354175), .RN(
n2719), .Q(mult_result[7]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[8]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8354175), .RN(
n2720), .Q(mult_result[8]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[9]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8354175), .RN(
n2725), .Q(mult_result[9]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[10]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8354175), .RN(
n2724), .Q(mult_result[10]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[11]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8354175), .RN(
n2722), .Q(mult_result[11]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[12]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8354175), .RN(
n2723), .Q(mult_result[12]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[13]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8354175), .RN(
n2726), .Q(mult_result[13]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[14]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8354175), .RN(
n2720), .Q(mult_result[14]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[15]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8354175), .RN(
n2720), .Q(mult_result[15]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[16]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8354175), .RN(
n2725), .Q(mult_result[16]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[17]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8354175), .RN(
n2719), .Q(mult_result[17]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[18]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8354175), .RN(
n2724), .Q(mult_result[18]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[19]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8354175), .RN(
n2722), .Q(mult_result[19]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[20]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8354175), .RN(
n2723), .Q(mult_result[20]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[21]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8354175), .RN(
n2726), .Q(mult_result[21]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[22]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8354175), .RN(
n2719), .Q(mult_result[22]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[0]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8354175), .RN(
n2720), .Q(mult_result[23]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[1]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8354175), .RN(
n2725), .Q(mult_result[24]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[2]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8354175), .RN(
n2724), .Q(mult_result[25]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[3]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8354175), .RN(
n2722), .Q(mult_result[26]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[4]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8354175), .RN(
n2727), .Q(mult_result[27]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[5]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8354175), .RN(
n2727), .Q(mult_result[28]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[6]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8354175), .RN(
n2727), .Q(mult_result[29]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[7]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8354175), .RN(
n2727), .Q(mult_result[30]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(
FPMULT_final_result_ieee_Module_Sign_S_mux), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8354175), .RN(
n2727), .Q(mult_result[31]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n2783), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8354175), .RN(n2697), .Q(
underflow_flag_addsubt) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n2784), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8354175), .RN(n2697), .Q(
overflow_flag_addsubt) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n2782), .CK(
FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2694), .Q(
FPADDSUB_SIGN_FLAG_EXP) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(FPADDSUB_SIGN_FLAG_EXP),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n2697), .Q(
FPADDSUB_SIGN_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n817), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8354211), .RN(n2691), .Q(
FPADDSUB_SIGN_FLAG_SHT2) );
DFFRXLTS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_2_ ( .D(FPADDSUB_SIGN_FLAG_SHT2),
.CK(FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2676), .Q(
FPADDSUB_SIGN_FLAG_SFG) );
DFFRXLTS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_1_ ( .D(FPADDSUB_SIGN_FLAG_SFG),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8354211), .RN(n2696), .Q(
FPADDSUB_SIGN_FLAG_NRM) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n814), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8354211), .RN(n2696), .Q(
FPADDSUB_SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n30), .CK(
FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2690), .Q(
FPADDSUB_OP_FLAG_EXP) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(FPADDSUB_OP_FLAG_EXP), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8354229), .RN(n2689), .Q(
FPADDSUB_OP_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n811), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8354211), .RN(n2676), .Q(
FPADDSUB_OP_FLAG_SHT2) );
DFFRXLTS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_2_ ( .D(n2785), .CK(
FPADDSUB_NRM_STAGE_Raw_mant_net8354211), .RN(n2691), .Q(
FPADDSUB_ADD_OVRFLW_NRM) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[4]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[5]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[6]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[7]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[8]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[9]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[10])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[11])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_12_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[12])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_13_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[13])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N0), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[0])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N1), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[1])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[2])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[3])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[4])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[5])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[6])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[7])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[8])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[9])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[10])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N11), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[11])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_12_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N12), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[12])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_13_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N13), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[13])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_14_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N14), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[14])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_15_ (
.D(intadd_1141_n1), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[15]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[3]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[4]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[5]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[6]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[7]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[8]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[9]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[10]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(intadd_1149_n1), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[11]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[4]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[5]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[6]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[7]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[8]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[9]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[10])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N11), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[11])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_12_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N12), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[12])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_13_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N13), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[13])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[6])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[7])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[8])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[9])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[10])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[11])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_12_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[12])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_13_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[13])
);
SNPS_CLOCK_GATE_HIGH_FPU_Interface2_W32_EW8_SW23_SWR26_EWR5_1 clk_gate_FPMULT_Exp_module_Underflow_m_Q_reg (
.CLK(clk), .EN(n2790), .ENCLK(n2788), .TE(1'b0) );
CMPR42X1TS DP_OP_502J326_128_4510_U25 ( .A(DP_OP_502J326_128_4510_n70), .B(
DP_OP_502J326_128_4510_n76), .C(DP_OP_502J326_128_4510_n57), .D(
DP_OP_502J326_128_4510_n63), .ICI(DP_OP_502J326_128_4510_n41), .S(
DP_OP_502J326_128_4510_n38), .ICO(DP_OP_502J326_128_4510_n36), .CO(
DP_OP_502J326_128_4510_n37) );
CMPR42X1TS DP_OP_502J326_128_4510_U24 ( .A(DP_OP_502J326_128_4510_n75), .B(
DP_OP_502J326_128_4510_n69), .C(DP_OP_502J326_128_4510_n62), .D(
DP_OP_502J326_128_4510_n56), .ICI(DP_OP_502J326_128_4510_n36), .S(
DP_OP_502J326_128_4510_n35), .ICO(DP_OP_502J326_128_4510_n33), .CO(
DP_OP_502J326_128_4510_n34) );
CMPR42X1TS DP_OP_502J326_128_4510_U22 ( .A(DP_OP_502J326_128_4510_n32), .B(
DP_OP_502J326_128_4510_n68), .C(DP_OP_502J326_128_4510_n61), .D(
DP_OP_502J326_128_4510_n55), .ICI(DP_OP_502J326_128_4510_n33), .S(
DP_OP_502J326_128_4510_n31), .ICO(DP_OP_502J326_128_4510_n29), .CO(
DP_OP_502J326_128_4510_n30) );
CMPR42X1TS DP_OP_502J326_128_4510_U20 ( .A(DP_OP_502J326_128_4510_n32), .B(
DP_OP_502J326_128_4510_n67), .C(DP_OP_502J326_128_4510_n60), .D(
DP_OP_502J326_128_4510_n54), .ICI(DP_OP_502J326_128_4510_n29), .S(
DP_OP_502J326_128_4510_n26), .ICO(DP_OP_502J326_128_4510_n24), .CO(
DP_OP_502J326_128_4510_n25) );
CMPR42X1TS DP_OP_502J326_128_4510_U19 ( .A(DP_OP_502J326_128_4510_n27), .B(
DP_OP_502J326_128_4510_n66), .C(DP_OP_502J326_128_4510_n59), .D(
DP_OP_502J326_128_4510_n53), .ICI(DP_OP_502J326_128_4510_n24), .S(
DP_OP_502J326_128_4510_n23), .ICO(DP_OP_502J326_128_4510_n21), .CO(
DP_OP_502J326_128_4510_n22) );
CMPR42X1TS DP_OP_501J326_127_5235_U113 ( .A(DP_OP_501J326_127_5235_n229),
.B(DP_OP_501J326_127_5235_n215), .C(DP_OP_501J326_127_5235_n171), .D(
DP_OP_501J326_127_5235_n170), .ICI(DP_OP_501J326_127_5235_n236), .S(
DP_OP_501J326_127_5235_n168), .ICO(DP_OP_501J326_127_5235_n166), .CO(
DP_OP_501J326_127_5235_n167) );
CMPR42X1TS DP_OP_501J326_127_5235_U110 ( .A(DP_OP_501J326_127_5235_n207),
.B(DP_OP_501J326_127_5235_n166), .C(DP_OP_501J326_127_5235_n235), .D(
DP_OP_501J326_127_5235_n200), .ICI(DP_OP_501J326_127_5235_n163), .S(
DP_OP_501J326_127_5235_n161), .ICO(DP_OP_501J326_127_5235_n159), .CO(
DP_OP_501J326_127_5235_n160) );
CMPR42X1TS DP_OP_501J326_127_5235_U108 ( .A(DP_OP_501J326_127_5235_n220),
.B(DP_OP_501J326_127_5235_n206), .C(DP_OP_501J326_127_5235_n158), .D(
DP_OP_501J326_127_5235_n227), .ICI(DP_OP_501J326_127_5235_n162), .S(
DP_OP_501J326_127_5235_n156), .ICO(DP_OP_501J326_127_5235_n154), .CO(
DP_OP_501J326_127_5235_n155) );
CMPR42X1TS DP_OP_501J326_127_5235_U107 ( .A(DP_OP_501J326_127_5235_n199),
.B(DP_OP_501J326_127_5235_n159), .C(DP_OP_501J326_127_5235_n234), .D(
DP_OP_501J326_127_5235_n192), .ICI(DP_OP_501J326_127_5235_n160), .S(
DP_OP_501J326_127_5235_n153), .ICO(DP_OP_501J326_127_5235_n151), .CO(
DP_OP_501J326_127_5235_n152) );
CMPR42X1TS DP_OP_501J326_127_5235_U104 ( .A(DP_OP_501J326_127_5235_n150),
.B(DP_OP_501J326_127_5235_n154), .C(DP_OP_501J326_127_5235_n233), .D(
DP_OP_501J326_127_5235_n184), .ICI(DP_OP_501J326_127_5235_n155), .S(
DP_OP_501J326_127_5235_n146), .ICO(DP_OP_501J326_127_5235_n144), .CO(
DP_OP_501J326_127_5235_n145) );
CMPR42X1TS DP_OP_501J326_127_5235_U103 ( .A(DP_OP_501J326_127_5235_n191),
.B(DP_OP_501J326_127_5235_n226), .C(DP_OP_501J326_127_5235_n148), .D(
DP_OP_501J326_127_5235_n151), .ICI(DP_OP_501J326_127_5235_n146), .S(
DP_OP_501J326_127_5235_n143), .ICO(DP_OP_501J326_127_5235_n141), .CO(
DP_OP_501J326_127_5235_n142) );
CMPR42X1TS DP_OP_501J326_127_5235_U100 ( .A(DP_OP_501J326_127_5235_n183),
.B(DP_OP_501J326_127_5235_n218), .C(DP_OP_501J326_127_5235_n190), .D(
DP_OP_501J326_127_5235_n140), .ICI(DP_OP_501J326_127_5235_n141), .S(
DP_OP_501J326_127_5235_n136), .ICO(DP_OP_501J326_127_5235_n134), .CO(
DP_OP_501J326_127_5235_n135) );
CMPR42X1TS DP_OP_501J326_127_5235_U99 ( .A(DP_OP_501J326_127_5235_n147), .B(
DP_OP_501J326_127_5235_n144), .C(DP_OP_501J326_127_5235_n138), .D(
DP_OP_501J326_127_5235_n145), .ICI(DP_OP_501J326_127_5235_n136), .S(
DP_OP_501J326_127_5235_n133), .ICO(DP_OP_501J326_127_5235_n131), .CO(
DP_OP_501J326_127_5235_n132) );
CMPR42X1TS DP_OP_501J326_127_5235_U97 ( .A(DP_OP_501J326_127_5235_n182), .B(
DP_OP_501J326_127_5235_n139), .C(DP_OP_501J326_127_5235_n189), .D(
DP_OP_501J326_127_5235_n210), .ICI(DP_OP_501J326_127_5235_n134), .S(
DP_OP_501J326_127_5235_n128), .ICO(DP_OP_501J326_127_5235_n126), .CO(
DP_OP_501J326_127_5235_n127) );
CMPR42X1TS DP_OP_501J326_127_5235_U96 ( .A(DP_OP_501J326_127_5235_n137), .B(
DP_OP_501J326_127_5235_n130), .C(DP_OP_501J326_127_5235_n131), .D(
DP_OP_501J326_127_5235_n135), .ICI(DP_OP_501J326_127_5235_n128), .S(
DP_OP_501J326_127_5235_n125), .ICO(DP_OP_501J326_127_5235_n123), .CO(
DP_OP_501J326_127_5235_n124) );
CMPR42X1TS DP_OP_501J326_127_5235_U95 ( .A(DP_OP_501J326_127_5235_n195), .B(
DP_OP_501J326_127_5235_n209), .C(DP_OP_501J326_127_5235_n181), .D(
DP_OP_501J326_127_5235_n188), .ICI(DP_OP_501J326_127_5235_n202), .S(
DP_OP_501J326_127_5235_n122), .ICO(DP_OP_501J326_127_5235_n120), .CO(
DP_OP_501J326_127_5235_n121) );
CMPR42X1TS DP_OP_501J326_127_5235_U94 ( .A(DP_OP_501J326_127_5235_n129), .B(
DP_OP_501J326_127_5235_n126), .C(DP_OP_501J326_127_5235_n127), .D(
DP_OP_501J326_127_5235_n122), .ICI(DP_OP_501J326_127_5235_n123), .S(
DP_OP_501J326_127_5235_n119), .ICO(DP_OP_501J326_127_5235_n117), .CO(
DP_OP_501J326_127_5235_n118) );
CMPR42X1TS DP_OP_501J326_127_5235_U92 ( .A(DP_OP_501J326_127_5235_n194), .B(
DP_OP_501J326_127_5235_n120), .C(DP_OP_501J326_127_5235_n116), .D(
DP_OP_501J326_127_5235_n121), .ICI(DP_OP_501J326_127_5235_n117), .S(
DP_OP_501J326_127_5235_n114), .ICO(DP_OP_501J326_127_5235_n112), .CO(
DP_OP_501J326_127_5235_n113) );
CMPR42X1TS DP_OP_501J326_127_5235_U91 ( .A(DP_OP_501J326_127_5235_n193), .B(
DP_OP_501J326_127_5235_n179), .C(DP_OP_501J326_127_5235_n186), .D(
DP_OP_501J326_127_5235_n115), .ICI(DP_OP_501J326_127_5235_n112), .S(
DP_OP_501J326_127_5235_n111), .ICO(DP_OP_501J326_127_5235_n109), .CO(
DP_OP_501J326_127_5235_n110) );
CMPR42X1TS DP_OP_501J326_127_5235_U22 ( .A(DP_OP_501J326_127_5235_n72), .B(
DP_OP_501J326_127_5235_n62), .C(DP_OP_501J326_127_5235_n40), .D(
DP_OP_501J326_127_5235_n39), .ICI(DP_OP_501J326_127_5235_n77), .S(
DP_OP_501J326_127_5235_n37), .ICO(DP_OP_501J326_127_5235_n35), .CO(
DP_OP_501J326_127_5235_n36) );
CMPR42X1TS DP_OP_501J326_127_5235_U19 ( .A(DP_OP_501J326_127_5235_n34), .B(
DP_OP_501J326_127_5235_n71), .C(DP_OP_501J326_127_5235_n56), .D(
DP_OP_501J326_127_5235_n32), .ICI(DP_OP_501J326_127_5235_n35), .S(
DP_OP_501J326_127_5235_n30), .ICO(DP_OP_501J326_127_5235_n28), .CO(
DP_OP_501J326_127_5235_n29) );
CMPR42X1TS DP_OP_501J326_127_5235_U16 ( .A(DP_OP_501J326_127_5235_n55), .B(
DP_OP_501J326_127_5235_n31), .C(DP_OP_501J326_127_5235_n27), .D(
DP_OP_501J326_127_5235_n28), .ICI(DP_OP_501J326_127_5235_n25), .S(
DP_OP_501J326_127_5235_n23), .ICO(DP_OP_501J326_127_5235_n21), .CO(
DP_OP_501J326_127_5235_n22) );
CMPR42X1TS DP_OP_501J326_127_5235_U14 ( .A(DP_OP_501J326_127_5235_n59), .B(
DP_OP_501J326_127_5235_n54), .C(DP_OP_501J326_127_5235_n20), .D(
DP_OP_501J326_127_5235_n24), .ICI(DP_OP_501J326_127_5235_n21), .S(
DP_OP_501J326_127_5235_n18), .ICO(DP_OP_501J326_127_5235_n16), .CO(
DP_OP_501J326_127_5235_n17) );
CMPR42X1TS DP_OP_501J326_127_5235_U13 ( .A(n929), .B(
DP_OP_501J326_127_5235_n48), .C(DP_OP_501J326_127_5235_n53), .D(
DP_OP_501J326_127_5235_n19), .ICI(DP_OP_501J326_127_5235_n16), .S(
DP_OP_501J326_127_5235_n15), .ICO(DP_OP_501J326_127_5235_n13), .CO(
DP_OP_501J326_127_5235_n14) );
CMPR42X1TS DP_OP_500J326_126_4510_U25 ( .A(DP_OP_500J326_126_4510_n70), .B(
DP_OP_500J326_126_4510_n56), .C(DP_OP_500J326_126_4510_n76), .D(
DP_OP_500J326_126_4510_n41), .ICI(DP_OP_500J326_126_4510_n63), .S(
DP_OP_500J326_126_4510_n38), .ICO(DP_OP_500J326_126_4510_n36), .CO(
DP_OP_500J326_126_4510_n37) );
CMPR42X1TS DP_OP_500J326_126_4510_U24 ( .A(DP_OP_500J326_126_4510_n75), .B(
DP_OP_500J326_126_4510_n69), .C(DP_OP_500J326_126_4510_n55), .D(
DP_OP_500J326_126_4510_n62), .ICI(DP_OP_500J326_126_4510_n36), .S(
DP_OP_500J326_126_4510_n35), .ICO(DP_OP_500J326_126_4510_n33), .CO(
DP_OP_500J326_126_4510_n34) );
CMPR42X1TS DP_OP_500J326_126_4510_U22 ( .A(DP_OP_500J326_126_4510_n32), .B(
DP_OP_500J326_126_4510_n68), .C(DP_OP_500J326_126_4510_n54), .D(
DP_OP_500J326_126_4510_n61), .ICI(DP_OP_500J326_126_4510_n33), .S(
DP_OP_500J326_126_4510_n31), .ICO(DP_OP_500J326_126_4510_n29), .CO(
DP_OP_500J326_126_4510_n30) );
CMPR42X1TS DP_OP_500J326_126_4510_U20 ( .A(DP_OP_500J326_126_4510_n32), .B(
DP_OP_500J326_126_4510_n67), .C(DP_OP_500J326_126_4510_n53), .D(
DP_OP_500J326_126_4510_n60), .ICI(DP_OP_500J326_126_4510_n29), .S(
DP_OP_500J326_126_4510_n26), .ICO(DP_OP_500J326_126_4510_n24), .CO(
DP_OP_500J326_126_4510_n25) );
CMPR42X1TS DP_OP_500J326_126_4510_U19 ( .A(DP_OP_500J326_126_4510_n27), .B(
DP_OP_500J326_126_4510_n66), .C(DP_OP_500J326_126_4510_n52), .D(
DP_OP_500J326_126_4510_n59), .ICI(DP_OP_500J326_126_4510_n24), .S(
DP_OP_500J326_126_4510_n23), .ICO(DP_OP_500J326_126_4510_n21), .CO(
DP_OP_500J326_126_4510_n22) );
CMPR42X1TS DP_OP_499J326_125_1651_U46 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[8]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[1]), .C(
DP_OP_499J326_125_1651_n110), .D(DP_OP_499J326_125_1651_n133), .ICI(
DP_OP_499J326_125_1651_n81), .S(DP_OP_499J326_125_1651_n78), .ICO(
DP_OP_499J326_125_1651_n76), .CO(DP_OP_499J326_125_1651_n77) );
CMPR42X1TS DP_OP_499J326_125_1651_U45 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[9]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[2]), .C(
DP_OP_499J326_125_1651_n109), .D(DP_OP_499J326_125_1651_n132), .ICI(
DP_OP_499J326_125_1651_n76), .S(DP_OP_499J326_125_1651_n75), .ICO(
DP_OP_499J326_125_1651_n73), .CO(DP_OP_499J326_125_1651_n74) );
CMPR42X1TS DP_OP_499J326_125_1651_U44 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[10]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[3]), .C(
DP_OP_499J326_125_1651_n108), .D(DP_OP_499J326_125_1651_n131), .ICI(
DP_OP_499J326_125_1651_n73), .S(DP_OP_499J326_125_1651_n72), .ICO(
DP_OP_499J326_125_1651_n70), .CO(DP_OP_499J326_125_1651_n71) );
CMPR42X1TS DP_OP_499J326_125_1651_U43 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[11]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[4]), .C(
DP_OP_499J326_125_1651_n107), .D(DP_OP_499J326_125_1651_n130), .ICI(
DP_OP_499J326_125_1651_n70), .S(DP_OP_499J326_125_1651_n69), .ICO(
DP_OP_499J326_125_1651_n67), .CO(DP_OP_499J326_125_1651_n68) );
CMPR42X1TS DP_OP_499J326_125_1651_U42 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[12]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[5]), .C(
DP_OP_499J326_125_1651_n106), .D(DP_OP_499J326_125_1651_n129), .ICI(
DP_OP_499J326_125_1651_n67), .S(DP_OP_499J326_125_1651_n66), .ICO(
DP_OP_499J326_125_1651_n64), .CO(DP_OP_499J326_125_1651_n65) );
CMPR42X1TS DP_OP_499J326_125_1651_U41 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[13]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[6]), .C(
DP_OP_499J326_125_1651_n105), .D(DP_OP_499J326_125_1651_n128), .ICI(
DP_OP_499J326_125_1651_n64), .S(DP_OP_499J326_125_1651_n63), .ICO(
DP_OP_499J326_125_1651_n61), .CO(DP_OP_499J326_125_1651_n62) );
CMPR42X1TS DP_OP_499J326_125_1651_U40 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[0]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[7]), .C(
DP_OP_499J326_125_1651_n104), .D(DP_OP_499J326_125_1651_n127), .ICI(
DP_OP_499J326_125_1651_n61), .S(DP_OP_499J326_125_1651_n60), .ICO(
DP_OP_499J326_125_1651_n58), .CO(DP_OP_499J326_125_1651_n59) );
CMPR42X1TS DP_OP_499J326_125_1651_U39 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[1]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[8]), .C(
DP_OP_499J326_125_1651_n103), .D(DP_OP_499J326_125_1651_n126), .ICI(
DP_OP_499J326_125_1651_n58), .S(DP_OP_499J326_125_1651_n57), .ICO(
DP_OP_499J326_125_1651_n55), .CO(DP_OP_499J326_125_1651_n56) );
CMPR42X1TS DP_OP_499J326_125_1651_U38 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[2]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[9]), .C(
DP_OP_499J326_125_1651_n102), .D(DP_OP_499J326_125_1651_n125), .ICI(
DP_OP_499J326_125_1651_n55), .S(DP_OP_499J326_125_1651_n54), .ICO(
DP_OP_499J326_125_1651_n52), .CO(DP_OP_499J326_125_1651_n53) );
CMPR42X1TS DP_OP_499J326_125_1651_U37 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[3]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[10]), .C(
DP_OP_499J326_125_1651_n101), .D(DP_OP_499J326_125_1651_n124), .ICI(
DP_OP_499J326_125_1651_n52), .S(DP_OP_499J326_125_1651_n51), .ICO(
DP_OP_499J326_125_1651_n49), .CO(DP_OP_499J326_125_1651_n50) );
CMPR42X1TS DP_OP_499J326_125_1651_U36 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[4]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[11]), .C(
DP_OP_499J326_125_1651_n100), .D(DP_OP_499J326_125_1651_n123), .ICI(
DP_OP_499J326_125_1651_n49), .S(DP_OP_499J326_125_1651_n48), .ICO(
DP_OP_499J326_125_1651_n46), .CO(DP_OP_499J326_125_1651_n47) );
CMPR42X1TS DP_OP_499J326_125_1651_U35 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[5]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[12]), .C(
DP_OP_499J326_125_1651_n99), .D(DP_OP_499J326_125_1651_n122), .ICI(
DP_OP_499J326_125_1651_n46), .S(DP_OP_499J326_125_1651_n45), .ICO(
DP_OP_499J326_125_1651_n43), .CO(DP_OP_499J326_125_1651_n44) );
CMPR42X1TS DP_OP_499J326_125_1651_U34 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[6]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[13]), .C(
DP_OP_499J326_125_1651_n98), .D(DP_OP_499J326_125_1651_n121), .ICI(
DP_OP_499J326_125_1651_n43), .S(DP_OP_499J326_125_1651_n42), .ICO(
DP_OP_499J326_125_1651_n40), .CO(DP_OP_499J326_125_1651_n41) );
CMPR42X1TS DP_OP_499J326_125_1651_U33 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[7]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[14]), .C(
DP_OP_499J326_125_1651_n97), .D(DP_OP_499J326_125_1651_n120), .ICI(
DP_OP_499J326_125_1651_n40), .S(DP_OP_499J326_125_1651_n39), .ICO(
DP_OP_499J326_125_1651_n37), .CO(DP_OP_499J326_125_1651_n38) );
CMPR42X1TS DP_OP_499J326_125_1651_U32 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[8]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[15]), .C(
DP_OP_499J326_125_1651_n96), .D(DP_OP_499J326_125_1651_n119), .ICI(
DP_OP_499J326_125_1651_n37), .S(DP_OP_499J326_125_1651_n36), .ICO(
DP_OP_499J326_125_1651_n34), .CO(DP_OP_499J326_125_1651_n35) );
CMPR42X1TS DP_OP_499J326_125_1651_U31 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[9]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[16]), .C(
DP_OP_499J326_125_1651_n95), .D(DP_OP_499J326_125_1651_n118), .ICI(
DP_OP_499J326_125_1651_n34), .S(DP_OP_499J326_125_1651_n33), .ICO(
DP_OP_499J326_125_1651_n31), .CO(DP_OP_499J326_125_1651_n32) );
CMPR42X1TS mult_x_313_U25 ( .A(mult_x_313_n56), .B(mult_x_313_n76), .C(
mult_x_313_n69), .D(mult_x_313_n62), .ICI(mult_x_313_n42), .S(
mult_x_313_n39), .ICO(mult_x_313_n37), .CO(mult_x_313_n38) );
CMPR42X1TS mult_x_313_U24 ( .A(mult_x_313_n75), .B(mult_x_313_n55), .C(
mult_x_313_n61), .D(mult_x_313_n68), .ICI(mult_x_313_n37), .S(
mult_x_313_n36), .ICO(mult_x_313_n34), .CO(mult_x_313_n35) );
CMPR42X1TS mult_x_313_U22 ( .A(mult_x_313_n67), .B(mult_x_313_n60), .C(
mult_x_313_n74), .D(mult_x_313_n33), .ICI(mult_x_313_n34), .S(
mult_x_313_n31), .ICO(mult_x_313_n29), .CO(mult_x_313_n30) );
CMPR42X1TS mult_x_313_U20 ( .A(mult_x_313_n66), .B(mult_x_313_n32), .C(
mult_x_313_n59), .D(mult_x_313_n28), .ICI(mult_x_313_n29), .S(
mult_x_313_n26), .ICO(mult_x_313_n24), .CO(mult_x_313_n25) );
CMPR42X1TS mult_x_313_U19 ( .A(mult_x_313_n27), .B(mult_x_313_n58), .C(
mult_x_313_n54), .D(mult_x_313_n65), .ICI(mult_x_313_n24), .S(
mult_x_313_n23), .ICO(mult_x_313_n21), .CO(mult_x_313_n22) );
CMPR42X1TS mult_x_312_U22 ( .A(mult_x_312_n77), .B(mult_x_312_n67), .C(
mult_x_312_n72), .D(mult_x_312_n42), .ICI(mult_x_312_n39), .S(
mult_x_312_n37), .ICO(mult_x_312_n35), .CO(mult_x_312_n36) );
CMPR42X1TS mult_x_312_U19 ( .A(mult_x_312_n71), .B(mult_x_312_n38), .C(
mult_x_312_n35), .D(mult_x_312_n34), .ICI(mult_x_312_n32), .S(
mult_x_312_n30), .ICO(mult_x_312_n28), .CO(mult_x_312_n29) );
CMPR42X1TS mult_x_312_U16 ( .A(mult_x_312_n33), .B(mult_x_312_n31), .C(
mult_x_312_n27), .D(mult_x_312_n25), .ICI(mult_x_312_n28), .S(
mult_x_312_n23), .ICO(mult_x_312_n21), .CO(mult_x_312_n22) );
CMPR42X1TS mult_x_312_U14 ( .A(mult_x_312_n59), .B(mult_x_312_n26), .C(
mult_x_312_n24), .D(mult_x_312_n20), .ICI(mult_x_312_n21), .S(
mult_x_312_n18), .ICO(mult_x_312_n16), .CO(mult_x_312_n17) );
CMPR42X1TS mult_x_312_U13 ( .A(mult_x_312_n58), .B(mult_x_312_n48), .C(
mult_x_312_n53), .D(mult_x_312_n19), .ICI(mult_x_312_n16), .S(
mult_x_312_n15), .ICO(mult_x_312_n13), .CO(mult_x_312_n14) );
CMPR42X1TS mult_x_311_U22 ( .A(mult_x_311_n77), .B(mult_x_311_n67), .C(
mult_x_311_n72), .D(mult_x_311_n42), .ICI(mult_x_311_n39), .S(
mult_x_311_n37), .ICO(mult_x_311_n35), .CO(mult_x_311_n36) );
CMPR42X1TS mult_x_311_U19 ( .A(mult_x_311_n71), .B(mult_x_311_n38), .C(
mult_x_311_n35), .D(mult_x_311_n34), .ICI(mult_x_311_n32), .S(
mult_x_311_n30), .ICO(mult_x_311_n28), .CO(mult_x_311_n29) );
CMPR42X1TS mult_x_311_U16 ( .A(mult_x_311_n33), .B(mult_x_311_n31), .C(
mult_x_311_n27), .D(mult_x_311_n25), .ICI(mult_x_311_n28), .S(
mult_x_311_n23), .ICO(mult_x_311_n21), .CO(mult_x_311_n22) );
CMPR42X1TS mult_x_311_U14 ( .A(mult_x_311_n59), .B(mult_x_311_n26), .C(
mult_x_311_n24), .D(mult_x_311_n20), .ICI(mult_x_311_n21), .S(
mult_x_311_n18), .ICO(mult_x_311_n16), .CO(mult_x_311_n17) );
CMPR42X1TS mult_x_311_U13 ( .A(mult_x_311_n58), .B(mult_x_311_n48), .C(
mult_x_311_n53), .D(mult_x_311_n19), .ICI(mult_x_311_n16), .S(
mult_x_311_n15), .ICO(mult_x_311_n13), .CO(mult_x_311_n14) );
CMPR42X1TS mult_x_310_U22 ( .A(mult_x_310_n77), .B(mult_x_310_n67), .C(
mult_x_310_n72), .D(mult_x_310_n42), .ICI(mult_x_310_n39), .S(
mult_x_310_n37), .ICO(mult_x_310_n35), .CO(mult_x_310_n36) );
CMPR42X1TS mult_x_310_U19 ( .A(mult_x_310_n71), .B(mult_x_310_n38), .C(
mult_x_310_n35), .D(mult_x_310_n34), .ICI(mult_x_310_n32), .S(
mult_x_310_n30), .ICO(mult_x_310_n28), .CO(mult_x_310_n29) );
CMPR42X1TS mult_x_310_U16 ( .A(mult_x_310_n33), .B(mult_x_310_n31), .C(
mult_x_310_n27), .D(mult_x_310_n25), .ICI(mult_x_310_n28), .S(
mult_x_310_n23), .ICO(mult_x_310_n21), .CO(mult_x_310_n22) );
CMPR42X1TS mult_x_310_U14 ( .A(mult_x_310_n59), .B(mult_x_310_n26), .C(
mult_x_310_n24), .D(mult_x_310_n20), .ICI(mult_x_310_n21), .S(
mult_x_310_n18), .ICO(mult_x_310_n16), .CO(mult_x_310_n17) );
CMPR42X1TS mult_x_310_U13 ( .A(mult_x_310_n58), .B(mult_x_310_n48), .C(
mult_x_310_n53), .D(mult_x_310_n19), .ICI(mult_x_310_n16), .S(
mult_x_310_n15), .ICO(mult_x_310_n13), .CO(mult_x_310_n14) );
CMPR42X1TS mult_x_309_U23 ( .A(mult_x_309_n76), .B(mult_x_309_n66), .C(
mult_x_309_n71), .D(mult_x_309_n42), .ICI(mult_x_309_n39), .S(
mult_x_309_n37), .ICO(mult_x_309_n35), .CO(mult_x_309_n36) );
CMPR42X1TS mult_x_309_U20 ( .A(mult_x_309_n65), .B(mult_x_309_n38), .C(
mult_x_309_n35), .D(mult_x_309_n34), .ICI(mult_x_309_n32), .S(
mult_x_309_n30), .ICO(mult_x_309_n28), .CO(mult_x_309_n29) );
CMPR42X1TS mult_x_309_U17 ( .A(mult_x_309_n33), .B(mult_x_309_n27), .C(
mult_x_309_n31), .D(mult_x_309_n25), .ICI(mult_x_309_n28), .S(
mult_x_309_n23), .ICO(mult_x_309_n21), .CO(mult_x_309_n22) );
CMPR42X1TS mult_x_309_U15 ( .A(mult_x_309_n58), .B(mult_x_309_n26), .C(
mult_x_309_n20), .D(mult_x_309_n24), .ICI(mult_x_309_n21), .S(
mult_x_309_n18), .ICO(mult_x_309_n16), .CO(mult_x_309_n17) );
CMPR42X1TS mult_x_309_U14 ( .A(FPMULT_Op_MX[21]), .B(FPMULT_Op_MY[21]), .C(
mult_x_309_n52), .D(mult_x_309_n19), .ICI(mult_x_309_n16), .S(
mult_x_309_n15), .ICO(mult_x_309_n13), .CO(mult_x_309_n14) );
CMPR32X2TS DP_OP_26J326_129_1325_U9 ( .A(FPADDSUB_DMP_exp_NRM2_EW[0]), .B(
n951), .C(DP_OP_26J326_129_1325_n18), .CO(DP_OP_26J326_129_1325_n8),
.S(FPADDSUB_exp_rslt_NRM2_EW1[0]) );
CMPR32X2TS DP_OP_26J326_129_1325_U8 ( .A(DP_OP_26J326_129_1325_n17), .B(
FPADDSUB_DMP_exp_NRM2_EW[1]), .C(DP_OP_26J326_129_1325_n8), .CO(
DP_OP_26J326_129_1325_n7), .S(FPADDSUB_exp_rslt_NRM2_EW1[1]) );
CMPR32X2TS DP_OP_26J326_129_1325_U7 ( .A(DP_OP_26J326_129_1325_n16), .B(
FPADDSUB_DMP_exp_NRM2_EW[2]), .C(DP_OP_26J326_129_1325_n7), .CO(
DP_OP_26J326_129_1325_n6), .S(FPADDSUB_exp_rslt_NRM2_EW1[2]) );
CMPR32X2TS DP_OP_26J326_129_1325_U6 ( .A(DP_OP_26J326_129_1325_n15), .B(
FPADDSUB_DMP_exp_NRM2_EW[3]), .C(DP_OP_26J326_129_1325_n6), .CO(
DP_OP_26J326_129_1325_n5), .S(FPADDSUB_exp_rslt_NRM2_EW1[3]) );
CMPR32X2TS intadd_1139_U26 ( .A(intadd_1139_A_0_), .B(intadd_1139_B_0_), .C(
intadd_1139_CI), .CO(intadd_1139_n25), .S(
FPMULT_Sgf_operation_Result[13]) );
CMPR32X2TS intadd_1139_U24 ( .A(intadd_1139_A_2_), .B(intadd_1139_B_2_), .C(
intadd_1139_n24), .CO(intadd_1139_n23), .S(
FPMULT_Sgf_operation_Result[15]) );
CMPR32X2TS intadd_1139_U23 ( .A(intadd_1139_A_3_), .B(intadd_1139_B_3_), .C(
intadd_1139_n23), .CO(intadd_1139_n22), .S(
FPMULT_Sgf_operation_Result[16]) );
CMPR32X2TS intadd_1139_U22 ( .A(intadd_1139_A_4_), .B(intadd_1139_B_4_), .C(
intadd_1139_n22), .CO(intadd_1139_n21), .S(
FPMULT_Sgf_operation_Result[17]) );
CMPR32X2TS intadd_1139_U21 ( .A(intadd_1139_A_5_), .B(intadd_1139_B_5_), .C(
intadd_1139_n21), .CO(intadd_1139_n20), .S(
FPMULT_Sgf_operation_Result[18]) );
CMPR32X2TS intadd_1139_U20 ( .A(intadd_1139_A_6_), .B(intadd_1139_B_6_), .C(
intadd_1139_n20), .CO(intadd_1139_n19), .S(
FPMULT_Sgf_operation_Result[19]) );
CMPR32X2TS intadd_1139_U19 ( .A(intadd_1139_A_7_), .B(intadd_1139_B_7_), .C(
intadd_1139_n19), .CO(intadd_1139_n18), .S(
FPMULT_Sgf_operation_Result[20]) );
CMPR32X2TS intadd_1139_U18 ( .A(intadd_1139_A_8_), .B(intadd_1139_B_8_), .C(
intadd_1139_n18), .CO(intadd_1139_n17), .S(
FPMULT_Sgf_operation_Result[21]) );
CMPR32X2TS intadd_1139_U17 ( .A(intadd_1139_A_9_), .B(intadd_1139_B_9_), .C(
intadd_1139_n17), .CO(intadd_1139_n16), .S(
FPMULT_Sgf_operation_Result[22]) );
CMPR32X2TS intadd_1139_U16 ( .A(intadd_1139_A_10_), .B(intadd_1139_B_10_),
.C(intadd_1139_n16), .CO(intadd_1139_n15), .S(
FPMULT_Sgf_operation_Result[23]) );
CMPR32X2TS intadd_1139_U6 ( .A(intadd_1139_A_20_), .B(intadd_1139_B_20_),
.C(intadd_1139_n6), .CO(intadd_1139_n5), .S(
FPMULT_Sgf_operation_Result[33]) );
CMPR32X2TS intadd_1140_U18 ( .A(FPMULT_Sgf_operation_Result[7]), .B(
intadd_1140_B_0_), .C(intadd_1139_A_18_), .CO(intadd_1140_n17), .S(
intadd_1140_SUM_0_) );
CMPR32X2TS intadd_1140_U17 ( .A(intadd_1140_A_1_), .B(intadd_1140_B_1_), .C(
intadd_1140_n17), .CO(intadd_1140_n16), .S(intadd_1140_SUM_1_) );
CMPR32X2TS intadd_1140_U16 ( .A(intadd_1140_A_2_), .B(intadd_1140_B_2_), .C(
intadd_1140_n16), .CO(intadd_1140_n15), .S(intadd_1140_SUM_2_) );
CMPR32X2TS intadd_1140_U15 ( .A(intadd_1140_A_3_), .B(intadd_1140_B_3_), .C(
intadd_1140_n15), .CO(intadd_1140_n14), .S(intadd_1140_SUM_3_) );
CMPR32X2TS intadd_1140_U14 ( .A(intadd_1140_A_4_), .B(intadd_1140_B_4_), .C(
intadd_1140_n14), .CO(intadd_1140_n13), .S(intadd_1140_SUM_4_) );
CMPR32X2TS intadd_1140_U13 ( .A(intadd_1140_A_5_), .B(intadd_1140_B_5_), .C(
intadd_1140_n13), .CO(intadd_1140_n12), .S(intadd_1140_SUM_5_) );
CMPR32X2TS intadd_1140_U12 ( .A(intadd_1140_A_6_), .B(intadd_1140_B_6_), .C(
intadd_1140_n12), .CO(intadd_1140_n11), .S(intadd_1140_SUM_6_) );
CMPR32X2TS intadd_1140_U11 ( .A(intadd_1140_A_7_), .B(intadd_1140_B_7_), .C(
intadd_1140_n11), .CO(intadd_1140_n10), .S(intadd_1140_SUM_7_) );
CMPR32X2TS intadd_1140_U10 ( .A(intadd_1140_A_8_), .B(intadd_1140_B_8_), .C(
intadd_1140_n10), .CO(intadd_1140_n9), .S(intadd_1140_SUM_8_) );
CMPR32X2TS intadd_1140_U9 ( .A(intadd_1140_A_9_), .B(intadd_1140_B_9_), .C(
intadd_1140_n9), .CO(intadd_1140_n8), .S(intadd_1140_SUM_9_) );
CMPR32X2TS intadd_1140_U8 ( .A(intadd_1140_A_10_), .B(intadd_1140_B_10_),
.C(intadd_1140_n8), .CO(intadd_1140_n7), .S(intadd_1140_SUM_10_) );
CMPR32X2TS intadd_1140_U7 ( .A(intadd_1140_A_11_), .B(intadd_1140_B_11_),
.C(intadd_1140_n7), .CO(intadd_1140_n6), .S(intadd_1140_SUM_11_) );
CMPR32X2TS intadd_1140_U6 ( .A(intadd_1140_A_12_), .B(intadd_1140_B_12_),
.C(intadd_1140_n6), .CO(intadd_1140_n5), .S(intadd_1140_SUM_12_) );
CMPR32X2TS intadd_1140_U5 ( .A(intadd_1140_A_13_), .B(intadd_1140_B_13_),
.C(intadd_1140_n5), .CO(intadd_1140_n4), .S(intadd_1140_SUM_13_) );
CMPR32X2TS intadd_1140_U4 ( .A(intadd_1140_A_14_), .B(intadd_1140_B_14_),
.C(intadd_1140_n4), .CO(intadd_1140_n3), .S(intadd_1140_SUM_14_) );
CMPR32X2TS intadd_1140_U3 ( .A(intadd_1140_A_15_), .B(intadd_1140_B_15_),
.C(intadd_1140_n3), .CO(intadd_1140_n2), .S(intadd_1140_SUM_15_) );
CMPR32X2TS intadd_1141_U13 ( .A(intadd_1141_A_1_), .B(intadd_1141_B_1_), .C(
intadd_1141_n13), .CO(intadd_1141_n12), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N3) );
CMPR32X2TS intadd_1141_U12 ( .A(DP_OP_501J326_127_5235_n168), .B(
intadd_1141_B_2_), .C(intadd_1141_n12), .CO(intadd_1141_n11), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N4) );
CMPR32X2TS intadd_1141_U11 ( .A(DP_OP_501J326_127_5235_n161), .B(
DP_OP_501J326_127_5235_n167), .C(intadd_1141_n11), .CO(intadd_1141_n10), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N5) );
CMPR32X2TS intadd_1141_U10 ( .A(DP_OP_501J326_127_5235_n153), .B(
DP_OP_501J326_127_5235_n156), .C(intadd_1141_n10), .CO(intadd_1141_n9),
.S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N6) );
CMPR32X2TS intadd_1141_U9 ( .A(DP_OP_501J326_127_5235_n152), .B(
DP_OP_501J326_127_5235_n143), .C(intadd_1141_n9), .CO(intadd_1141_n8),
.S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N7) );
CMPR32X2TS intadd_1141_U8 ( .A(DP_OP_501J326_127_5235_n142), .B(
DP_OP_501J326_127_5235_n133), .C(intadd_1141_n8), .CO(intadd_1141_n7),
.S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N8) );
CMPR32X2TS intadd_1141_U7 ( .A(DP_OP_501J326_127_5235_n132), .B(
DP_OP_501J326_127_5235_n125), .C(intadd_1141_n7), .CO(intadd_1141_n6),
.S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N9) );
CMPR32X2TS intadd_1141_U6 ( .A(DP_OP_501J326_127_5235_n124), .B(
DP_OP_501J326_127_5235_n119), .C(intadd_1141_n6), .CO(intadd_1141_n5),
.S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N10) );
CMPR32X2TS intadd_1141_U5 ( .A(DP_OP_501J326_127_5235_n118), .B(
DP_OP_501J326_127_5235_n114), .C(intadd_1141_n5), .CO(intadd_1141_n4),
.S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N11) );
CMPR32X2TS intadd_1141_U4 ( .A(DP_OP_501J326_127_5235_n111), .B(
DP_OP_501J326_127_5235_n113), .C(intadd_1141_n4), .CO(intadd_1141_n3),
.S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N12) );
CMPR32X2TS intadd_1141_U3 ( .A(DP_OP_501J326_127_5235_n110), .B(
intadd_1141_B_11_), .C(intadd_1141_n3), .CO(intadd_1141_n2), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N13) );
CMPR32X2TS intadd_1141_U2 ( .A(intadd_1141_A_12_), .B(intadd_1141_B_12_),
.C(intadd_1141_n2), .CO(intadd_1141_n1), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N14) );
CMPR32X2TS intadd_1142_U14 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[7]), .B(
intadd_1142_B_0_), .C(intadd_1142_CI), .CO(intadd_1142_n13), .S(
FPMULT_Sgf_operation_Result[7]) );
CMPR32X2TS intadd_1142_U13 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[8]), .B(
intadd_1142_B_1_), .C(intadd_1142_n13), .CO(intadd_1142_n12), .S(
FPMULT_Sgf_operation_Result[8]) );
CMPR32X2TS intadd_1142_U12 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[9]), .B(
intadd_1142_B_2_), .C(intadd_1142_n12), .CO(intadd_1142_n11), .S(
FPMULT_Sgf_operation_Result[9]) );
CMPR32X2TS intadd_1142_U11 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[10]), .B(
intadd_1142_B_3_), .C(intadd_1142_n11), .CO(intadd_1142_n10), .S(
FPMULT_Sgf_operation_Result[10]) );
CMPR32X2TS intadd_1142_U8 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[1]), .B(
intadd_1142_B_6_), .C(intadd_1142_n8), .CO(intadd_1142_n7), .S(
intadd_1139_A_0_) );
CMPR32X2TS intadd_1142_U7 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[2]), .B(
intadd_1142_B_7_), .C(intadd_1142_n7), .CO(intadd_1142_n6), .S(
intadd_1139_A_1_) );
CMPR32X2TS intadd_1142_U6 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[3]), .B(
intadd_1142_B_8_), .C(intadd_1142_n6), .CO(intadd_1142_n5), .S(
intadd_1139_A_2_) );
CMPR32X2TS intadd_1142_U5 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[4]), .B(
intadd_1142_B_9_), .C(intadd_1142_n5), .CO(intadd_1142_n4), .S(
intadd_1139_A_3_) );
CMPR32X2TS intadd_1142_U4 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[5]), .B(
intadd_1142_B_10_), .C(intadd_1142_n4), .CO(intadd_1142_n3), .S(
intadd_1139_A_4_) );
CMPR32X2TS intadd_1142_U3 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[6]), .B(
intadd_1142_B_11_), .C(intadd_1142_n3), .CO(intadd_1142_n2), .S(
intadd_1139_A_5_) );
CMPR32X2TS intadd_1142_U2 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[7]), .B(
intadd_1142_B_12_), .C(intadd_1142_n2), .CO(intadd_1142_n1), .S(
intadd_1139_A_6_) );
CMPR32X2TS intadd_1143_U12 ( .A(intadd_1143_A_2_), .B(intadd_1143_B_2_), .C(
intadd_1143_n12), .CO(intadd_1143_n11), .S(intadd_1143_SUM_2_) );
CMPR32X2TS intadd_1143_U11 ( .A(intadd_1143_A_3_), .B(intadd_1143_B_3_), .C(
intadd_1143_n11), .CO(intadd_1143_n10), .S(intadd_1143_SUM_3_) );
CMPR32X2TS intadd_1143_U10 ( .A(intadd_1143_A_4_), .B(intadd_1143_B_4_), .C(
intadd_1143_n10), .CO(intadd_1143_n9), .S(intadd_1143_SUM_4_) );
CMPR32X2TS intadd_1143_U9 ( .A(intadd_1143_A_5_), .B(intadd_1143_B_5_), .C(
intadd_1143_n9), .CO(intadd_1143_n8), .S(intadd_1143_SUM_5_) );
CMPR32X2TS intadd_1143_U8 ( .A(intadd_1143_A_6_), .B(intadd_1143_B_6_), .C(
intadd_1143_n8), .CO(intadd_1143_n7), .S(intadd_1143_SUM_6_) );
CMPR32X2TS intadd_1143_U7 ( .A(intadd_1143_A_7_), .B(intadd_1143_B_7_), .C(
intadd_1143_n7), .CO(intadd_1143_n6), .S(intadd_1143_SUM_7_) );
CMPR32X2TS intadd_1143_U6 ( .A(intadd_1143_A_8_), .B(intadd_1143_B_8_), .C(
intadd_1143_n6), .CO(intadd_1143_n5), .S(intadd_1143_SUM_8_) );
CMPR32X2TS intadd_1143_U5 ( .A(intadd_1143_A_9_), .B(intadd_1143_B_9_), .C(
intadd_1143_n5), .CO(intadd_1143_n4), .S(intadd_1143_SUM_9_) );
CMPR32X2TS intadd_1143_U4 ( .A(intadd_1143_A_10_), .B(intadd_1143_B_10_),
.C(intadd_1143_n4), .CO(intadd_1143_n3), .S(intadd_1143_SUM_10_) );
CMPR32X2TS intadd_1143_U3 ( .A(intadd_1143_A_11_), .B(intadd_1143_B_11_),
.C(intadd_1143_n3), .CO(intadd_1143_n2), .S(intadd_1143_SUM_11_) );
CMPR32X2TS intadd_1143_U2 ( .A(intadd_1143_A_12_), .B(intadd_1143_B_12_),
.C(intadd_1143_n2), .CO(intadd_1143_n1), .S(intadd_1143_SUM_12_) );
CMPR32X2TS intadd_1144_U14 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[7]), .B(
intadd_1144_B_0_), .C(intadd_1144_CI), .CO(intadd_1144_n13), .S(
intadd_1139_A_18_) );
CMPR32X2TS intadd_1144_U13 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[8]), .B(
intadd_1144_B_1_), .C(intadd_1144_n13), .CO(intadd_1144_n12), .S(
intadd_1139_A_19_) );
CMPR32X2TS intadd_1144_U12 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[9]), .B(
intadd_1144_B_2_), .C(intadd_1144_n12), .CO(intadd_1144_n11), .S(
intadd_1139_A_20_) );
CMPR32X2TS intadd_1144_U11 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[10]), .B(
intadd_1144_B_3_), .C(intadd_1144_n11), .CO(intadd_1144_n10), .S(
intadd_1139_A_21_) );
CMPR32X2TS intadd_1144_U10 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[11]), .B(
intadd_1144_B_4_), .C(intadd_1144_n10), .CO(intadd_1144_n9), .S(
intadd_1139_A_22_) );
CMPR32X2TS intadd_1144_U9 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[0]), .B(
intadd_1144_B_5_), .C(intadd_1144_n9), .CO(intadd_1144_n8), .S(
intadd_1139_A_23_) );
CMPR32X2TS intadd_1144_U8 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[1]), .B(
intadd_1144_B_6_), .C(intadd_1144_n8), .CO(intadd_1144_n7), .S(
intadd_1139_A_24_) );
CMPR32X2TS intadd_1144_U6 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[3]), .B(
intadd_1144_B_8_), .C(intadd_1144_n6), .CO(intadd_1144_n5), .S(
intadd_1144_SUM_8_) );
CMPR32X2TS intadd_1144_U5 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[4]), .B(
intadd_1144_B_9_), .C(intadd_1144_n5), .CO(intadd_1144_n4), .S(
intadd_1144_SUM_9_) );
CMPR32X2TS intadd_1145_U12 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[1]), .B(
intadd_1145_B_1_), .C(intadd_1145_n12), .CO(intadd_1145_n11), .S(
intadd_1145_SUM_1_) );
CMPR32X2TS intadd_1145_U11 ( .A(intadd_1145_A_2_), .B(intadd_1145_B_2_), .C(
intadd_1145_n11), .CO(intadd_1145_n10), .S(intadd_1145_SUM_2_) );
CMPR32X2TS intadd_1145_U10 ( .A(intadd_1145_A_3_), .B(intadd_1145_B_3_), .C(
intadd_1145_n10), .CO(intadd_1145_n9), .S(intadd_1145_SUM_3_) );
CMPR32X2TS intadd_1145_U9 ( .A(intadd_1145_A_4_), .B(intadd_1145_B_4_), .C(
intadd_1145_n9), .CO(intadd_1145_n8), .S(intadd_1145_SUM_4_) );
CMPR32X2TS intadd_1145_U8 ( .A(intadd_1145_A_5_), .B(intadd_1145_B_5_), .C(
intadd_1145_n8), .CO(intadd_1145_n7), .S(intadd_1145_SUM_5_) );
CMPR32X2TS intadd_1145_U7 ( .A(intadd_1145_A_6_), .B(intadd_1145_B_6_), .C(
intadd_1145_n7), .CO(intadd_1145_n6), .S(intadd_1145_SUM_6_) );
CMPR32X2TS intadd_1145_U6 ( .A(intadd_1145_A_7_), .B(intadd_1145_B_7_), .C(
intadd_1145_n6), .CO(intadd_1145_n5), .S(intadd_1145_SUM_7_) );
CMPR32X2TS intadd_1145_U5 ( .A(intadd_1145_A_8_), .B(intadd_1145_B_8_), .C(
intadd_1145_n5), .CO(intadd_1145_n4), .S(intadd_1145_SUM_8_) );
CMPR32X2TS intadd_1145_U4 ( .A(intadd_1145_A_9_), .B(intadd_1145_B_9_), .C(
intadd_1145_n4), .CO(intadd_1145_n3), .S(intadd_1145_SUM_9_) );
CMPR32X2TS intadd_1145_U3 ( .A(intadd_1145_A_10_), .B(intadd_1145_B_10_),
.C(intadd_1145_n3), .CO(intadd_1145_n2), .S(intadd_1145_SUM_10_) );
CMPR32X2TS intadd_1145_U2 ( .A(intadd_1145_A_11_), .B(intadd_1145_B_11_),
.C(intadd_1145_n2), .CO(intadd_1145_n1), .S(intadd_1145_SUM_11_) );
CMPR32X2TS intadd_1146_U11 ( .A(intadd_1146_A_1_), .B(intadd_1146_B_1_), .C(
intadd_1146_n11), .CO(intadd_1146_n10), .S(intadd_1144_B_2_) );
CMPR32X2TS intadd_1146_U10 ( .A(intadd_1146_A_2_), .B(intadd_1146_B_2_), .C(
intadd_1146_n10), .CO(intadd_1146_n9), .S(intadd_1144_B_3_) );
CMPR32X2TS intadd_1146_U9 ( .A(intadd_1146_A_3_), .B(intadd_1146_B_3_), .C(
intadd_1146_n9), .CO(intadd_1146_n8), .S(intadd_1144_B_4_) );
CMPR32X2TS intadd_1146_U8 ( .A(intadd_1146_A_4_), .B(intadd_1146_B_4_), .C(
intadd_1146_n8), .CO(intadd_1146_n7), .S(intadd_1144_B_5_) );
CMPR32X2TS intadd_1146_U7 ( .A(intadd_1146_A_5_), .B(intadd_1146_B_5_), .C(
intadd_1146_n7), .CO(intadd_1146_n6), .S(intadd_1144_B_6_) );
CMPR32X2TS intadd_1146_U6 ( .A(intadd_1146_A_6_), .B(intadd_1146_B_6_), .C(
intadd_1146_n6), .CO(intadd_1146_n5), .S(intadd_1144_B_7_) );
CMPR32X2TS intadd_1146_U5 ( .A(intadd_1146_A_7_), .B(intadd_1146_B_7_), .C(
intadd_1146_n5), .CO(intadd_1146_n4), .S(intadd_1144_B_8_) );
CMPR32X2TS intadd_1146_U4 ( .A(intadd_1146_A_8_), .B(intadd_1146_B_8_), .C(
intadd_1146_n4), .CO(intadd_1146_n3), .S(intadd_1144_B_9_) );
CMPR32X2TS intadd_1146_U3 ( .A(intadd_1146_A_9_), .B(intadd_1146_B_9_), .C(
intadd_1146_n3), .CO(intadd_1146_n2), .S(intadd_1144_B_10_) );
CMPR32X2TS intadd_1146_U2 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[12]), .B(
intadd_1146_B_10_), .C(intadd_1146_n2), .CO(intadd_1146_n1), .S(
intadd_1144_B_11_) );
CMPR32X2TS intadd_1148_U4 ( .A(FPMULT_Op_MY[8]), .B(FPMULT_Op_MY[20]), .C(
intadd_1148_n4), .CO(intadd_1148_n3), .S(intadd_1148_SUM_7_) );
CMPR32X2TS intadd_1149_U9 ( .A(intadd_1149_A_1_), .B(intadd_1149_B_1_), .C(
intadd_1149_n9), .CO(intadd_1149_n8), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N3) );
CMPR32X2TS intadd_1149_U8 ( .A(DP_OP_501J326_127_5235_n37), .B(
intadd_1149_B_2_), .C(intadd_1149_n8), .CO(intadd_1149_n7), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N4) );
CMPR32X2TS intadd_1149_U7 ( .A(DP_OP_501J326_127_5235_n36), .B(
DP_OP_501J326_127_5235_n30), .C(intadd_1149_n7), .CO(intadd_1149_n6),
.S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N5) );
CMPR32X2TS intadd_1149_U6 ( .A(DP_OP_501J326_127_5235_n29), .B(
DP_OP_501J326_127_5235_n23), .C(intadd_1149_n6), .CO(intadd_1149_n5),
.S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N6) );
CMPR32X2TS intadd_1149_U5 ( .A(DP_OP_501J326_127_5235_n22), .B(
DP_OP_501J326_127_5235_n18), .C(intadd_1149_n5), .CO(intadd_1149_n4),
.S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N7) );
CMPR32X2TS intadd_1149_U4 ( .A(DP_OP_501J326_127_5235_n17), .B(
DP_OP_501J326_127_5235_n15), .C(intadd_1149_n4), .CO(intadd_1149_n3),
.S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N8) );
CMPR32X2TS intadd_1149_U3 ( .A(DP_OP_501J326_127_5235_n14), .B(
intadd_1149_B_7_), .C(intadd_1149_n3), .CO(intadd_1149_n2), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N9) );
CMPR32X2TS intadd_1149_U2 ( .A(intadd_1149_A_8_), .B(intadd_1149_B_8_), .C(
intadd_1149_n2), .CO(intadd_1149_n1), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N10) );
CMPR32X2TS intadd_1150_U10 ( .A(intadd_1150_A_0_), .B(intadd_1150_B_0_), .C(
intadd_1150_CI), .CO(intadd_1150_n9), .S(intadd_1150_SUM_0_) );
CMPR32X2TS intadd_1150_U9 ( .A(intadd_1150_A_1_), .B(intadd_1150_B_1_), .C(
intadd_1150_n9), .CO(intadd_1150_n8), .S(intadd_1150_SUM_1_) );
CMPR32X2TS intadd_1150_U8 ( .A(mult_x_313_n39), .B(intadd_1150_B_2_), .C(
intadd_1150_n8), .CO(intadd_1150_n7), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N6) );
CMPR32X2TS intadd_1150_U7 ( .A(mult_x_313_n38), .B(mult_x_313_n36), .C(
intadd_1150_n7), .CO(intadd_1150_n6), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N7) );
CMPR32X2TS intadd_1150_U6 ( .A(mult_x_313_n35), .B(mult_x_313_n31), .C(
intadd_1150_n6), .CO(intadd_1150_n5), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N8) );
CMPR32X2TS intadd_1150_U5 ( .A(mult_x_313_n30), .B(mult_x_313_n26), .C(
intadd_1150_n5), .CO(intadd_1150_n4), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N9) );
CMPR32X2TS intadd_1150_U4 ( .A(mult_x_313_n25), .B(mult_x_313_n23), .C(
intadd_1150_n4), .CO(intadd_1150_n3), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N10) );
CMPR32X2TS intadd_1150_U3 ( .A(mult_x_313_n22), .B(intadd_1150_B_7_), .C(
intadd_1150_n3), .CO(intadd_1150_n2), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N11) );
CMPR32X2TS intadd_1150_U2 ( .A(intadd_1150_A_8_), .B(intadd_1150_B_8_), .C(
intadd_1150_n2), .CO(intadd_1150_n1), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N12) );
CMPR32X2TS intadd_1151_U9 ( .A(intadd_1151_A_0_), .B(intadd_1151_B_0_), .C(
intadd_1151_CI), .CO(intadd_1151_n8), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N5) );
CMPR32X2TS intadd_1151_U8 ( .A(DP_OP_502J326_128_4510_n38), .B(
intadd_1151_B_1_), .C(intadd_1151_n8), .CO(intadd_1151_n7), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N6) );
CMPR32X2TS intadd_1151_U7 ( .A(DP_OP_502J326_128_4510_n37), .B(
DP_OP_502J326_128_4510_n35), .C(intadd_1151_n7), .CO(intadd_1151_n6),
.S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N7) );
CMPR32X2TS intadd_1151_U6 ( .A(DP_OP_502J326_128_4510_n34), .B(
DP_OP_502J326_128_4510_n31), .C(intadd_1151_n6), .CO(intadd_1151_n5),
.S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8) );
CMPR32X2TS intadd_1151_U5 ( .A(DP_OP_502J326_128_4510_n30), .B(
DP_OP_502J326_128_4510_n26), .C(intadd_1151_n5), .CO(intadd_1151_n4),
.S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9) );
CMPR32X2TS intadd_1151_U4 ( .A(DP_OP_502J326_128_4510_n25), .B(
DP_OP_502J326_128_4510_n23), .C(intadd_1151_n4), .CO(intadd_1151_n3),
.S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10) );
CMPR32X2TS intadd_1151_U3 ( .A(DP_OP_502J326_128_4510_n22), .B(
intadd_1151_B_6_), .C(intadd_1151_n3), .CO(intadd_1151_n2), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11) );
CMPR32X2TS intadd_1151_U2 ( .A(intadd_1151_A_7_), .B(intadd_1151_B_7_), .C(
intadd_1151_n2), .CO(intadd_1151_n1), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12) );
CMPR32X2TS intadd_1152_U9 ( .A(intadd_1152_A_0_), .B(intadd_1152_B_0_), .C(
intadd_1152_CI), .CO(intadd_1152_n8), .S(intadd_1152_SUM_0_) );
CMPR32X2TS intadd_1152_U8 ( .A(intadd_1152_A_1_), .B(intadd_1152_B_1_), .C(
intadd_1152_n8), .CO(intadd_1152_n7), .S(intadd_1152_SUM_1_) );
CMPR32X2TS intadd_1152_U7 ( .A(intadd_1152_A_2_), .B(intadd_1152_B_2_), .C(
intadd_1152_n7), .CO(intadd_1152_n6), .S(intadd_1152_SUM_2_) );
CMPR32X2TS intadd_1152_U6 ( .A(intadd_1152_A_3_), .B(intadd_1152_B_3_), .C(
intadd_1152_n6), .CO(intadd_1152_n5), .S(intadd_1152_SUM_3_) );
CMPR32X2TS intadd_1152_U5 ( .A(intadd_1152_A_4_), .B(intadd_1152_B_4_), .C(
intadd_1152_n5), .CO(intadd_1152_n4), .S(intadd_1152_SUM_4_) );
CMPR32X2TS intadd_1152_U4 ( .A(intadd_1152_A_5_), .B(intadd_1152_B_5_), .C(
intadd_1152_n4), .CO(intadd_1152_n3), .S(intadd_1152_SUM_5_) );
CMPR32X2TS intadd_1152_U3 ( .A(intadd_1152_A_6_), .B(intadd_1152_B_6_), .C(
intadd_1152_n3), .CO(intadd_1152_n2), .S(intadd_1152_SUM_6_) );
CMPR32X2TS intadd_1152_U2 ( .A(intadd_1152_A_7_), .B(intadd_1152_B_7_), .C(
intadd_1152_n2), .CO(intadd_1152_n1), .S(intadd_1152_SUM_7_) );
CMPR32X2TS intadd_1153_U9 ( .A(intadd_1153_A_0_), .B(intadd_1153_B_0_), .C(
intadd_1153_CI), .CO(intadd_1153_n8), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3) );
CMPR32X2TS intadd_1153_U8 ( .A(mult_x_312_n37), .B(intadd_1153_B_1_), .C(
intadd_1153_n8), .CO(intadd_1153_n7), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4) );
CMPR32X2TS intadd_1153_U7 ( .A(mult_x_312_n36), .B(mult_x_312_n30), .C(
intadd_1153_n7), .CO(intadd_1153_n6), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5) );
CMPR32X2TS intadd_1153_U5 ( .A(mult_x_312_n22), .B(mult_x_312_n18), .C(
intadd_1153_n5), .CO(intadd_1153_n4), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7) );
CMPR32X2TS intadd_1153_U4 ( .A(mult_x_312_n17), .B(mult_x_312_n15), .C(
intadd_1153_n4), .CO(intadd_1153_n3), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8) );
CMPR32X2TS intadd_1153_U3 ( .A(mult_x_312_n14), .B(intadd_1153_B_6_), .C(
intadd_1153_n3), .CO(intadd_1153_n2), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9) );
CMPR32X2TS intadd_1154_U9 ( .A(intadd_1154_A_0_), .B(intadd_1154_B_0_), .C(
intadd_1154_CI), .CO(intadd_1154_n8), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3) );
CMPR32X2TS intadd_1154_U8 ( .A(mult_x_311_n37), .B(intadd_1154_B_1_), .C(
intadd_1154_n8), .CO(intadd_1154_n7), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4) );
CMPR32X2TS intadd_1154_U7 ( .A(mult_x_311_n36), .B(mult_x_311_n30), .C(
intadd_1154_n7), .CO(intadd_1154_n6), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5) );
CMPR32X2TS intadd_1154_U6 ( .A(mult_x_311_n29), .B(mult_x_311_n23), .C(
intadd_1154_n6), .CO(intadd_1154_n5), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6) );
CMPR32X2TS intadd_1154_U5 ( .A(mult_x_311_n22), .B(mult_x_311_n18), .C(
intadd_1154_n5), .CO(intadd_1154_n4), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7) );
CMPR32X2TS intadd_1154_U3 ( .A(mult_x_311_n14), .B(intadd_1154_B_6_), .C(
intadd_1154_n3), .CO(intadd_1154_n2), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9) );
CMPR32X2TS intadd_1155_U9 ( .A(intadd_1155_A_0_), .B(intadd_1155_B_0_), .C(
intadd_1155_CI), .CO(intadd_1155_n8), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3) );
CMPR32X2TS intadd_1155_U8 ( .A(mult_x_310_n37), .B(intadd_1155_B_1_), .C(
intadd_1155_n8), .CO(intadd_1155_n7), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4) );
CMPR32X2TS intadd_1155_U7 ( .A(mult_x_310_n36), .B(mult_x_310_n30), .C(
intadd_1155_n7), .CO(intadd_1155_n6), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5) );
CMPR32X2TS intadd_1155_U5 ( .A(mult_x_310_n22), .B(mult_x_310_n18), .C(
intadd_1155_n5), .CO(intadd_1155_n4), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7) );
CMPR32X2TS intadd_1155_U4 ( .A(mult_x_310_n17), .B(mult_x_310_n15), .C(
intadd_1155_n4), .CO(intadd_1155_n3), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8) );
CMPR32X2TS intadd_1155_U3 ( .A(mult_x_310_n14), .B(intadd_1155_B_6_), .C(
intadd_1155_n3), .CO(intadd_1155_n2), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9) );
CMPR32X2TS intadd_1156_U8 ( .A(intadd_1156_A_1_), .B(intadd_1156_B_1_), .C(
intadd_1156_n8), .CO(intadd_1156_n7), .S(intadd_1139_CI) );
CMPR32X2TS intadd_1156_U7 ( .A(intadd_1156_A_2_), .B(intadd_1156_B_2_), .C(
intadd_1156_n7), .CO(intadd_1156_n6), .S(intadd_1139_B_1_) );
CMPR32X2TS intadd_1156_U6 ( .A(intadd_1156_A_3_), .B(intadd_1156_B_3_), .C(
intadd_1156_n6), .CO(intadd_1156_n5), .S(intadd_1139_B_2_) );
CMPR32X2TS intadd_1156_U5 ( .A(intadd_1156_A_4_), .B(intadd_1156_B_4_), .C(
intadd_1156_n5), .CO(intadd_1156_n4), .S(intadd_1139_B_3_) );
CMPR32X2TS intadd_1156_U4 ( .A(intadd_1156_A_5_), .B(intadd_1156_B_5_), .C(
intadd_1156_n4), .CO(intadd_1156_n3), .S(intadd_1139_B_4_) );
CMPR32X2TS intadd_1156_U3 ( .A(intadd_1156_A_6_), .B(intadd_1156_B_6_), .C(
intadd_1156_n3), .CO(intadd_1156_n2), .S(intadd_1139_B_5_) );
CMPR32X2TS intadd_1156_U2 ( .A(intadd_1156_A_7_), .B(intadd_1156_B_7_), .C(
intadd_1156_n2), .CO(intadd_1156_n1), .S(intadd_1139_B_6_) );
CMPR32X2TS intadd_1157_U8 ( .A(intadd_1157_A_0_), .B(intadd_1157_B_0_), .C(
intadd_1157_CI), .CO(intadd_1157_n7), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3) );
CMPR32X2TS intadd_1157_U7 ( .A(mult_x_309_n37), .B(intadd_1157_B_1_), .C(
intadd_1157_n7), .CO(intadd_1157_n6), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4) );
CMPR32X2TS intadd_1157_U6 ( .A(mult_x_309_n36), .B(mult_x_309_n30), .C(
intadd_1157_n6), .CO(intadd_1157_n5), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5) );
CMPR32X2TS intadd_1157_U5 ( .A(mult_x_309_n29), .B(mult_x_309_n23), .C(
intadd_1157_n5), .CO(intadd_1157_n4), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6) );
CMPR32X2TS intadd_1157_U4 ( .A(mult_x_309_n22), .B(mult_x_309_n18), .C(
intadd_1157_n4), .CO(intadd_1157_n3), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7) );
CMPR32X2TS intadd_1157_U3 ( .A(mult_x_309_n17), .B(mult_x_309_n15), .C(
intadd_1157_n3), .CO(intadd_1157_n2), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8) );
CMPR32X2TS intadd_1158_U5 ( .A(FPMULT_Op_MY[8]), .B(FPMULT_Op_MY[2]), .C(
intadd_1158_n5), .CO(intadd_1158_n4), .S(intadd_1158_SUM_1_) );
CMPR32X2TS intadd_1158_U4 ( .A(FPMULT_Op_MY[9]), .B(FPMULT_Op_MY[3]), .C(
intadd_1158_n4), .CO(intadd_1158_n3), .S(intadd_1158_SUM_2_) );
CMPR32X2TS intadd_1158_U3 ( .A(FPMULT_Op_MY[10]), .B(FPMULT_Op_MY[4]), .C(
intadd_1158_n3), .CO(intadd_1158_n2), .S(intadd_1158_SUM_3_) );
CMPR32X2TS intadd_1158_U2 ( .A(FPMULT_Op_MY[11]), .B(FPMULT_Op_MY[5]), .C(
intadd_1158_n2), .CO(intadd_1158_n1), .S(intadd_1158_SUM_4_) );
CMPR32X2TS intadd_1159_U6 ( .A(intadd_1148_SUM_7_), .B(intadd_1159_B_0_),
.C(intadd_1148_SUM_0_), .CO(intadd_1159_n5), .S(intadd_1159_SUM_0_) );
CMPR32X2TS intadd_1159_U5 ( .A(intadd_1148_SUM_8_), .B(intadd_1148_SUM_1_),
.C(intadd_1159_n5), .CO(intadd_1159_n4), .S(intadd_1159_SUM_1_) );
CMPR32X2TS intadd_1159_U3 ( .A(intadd_1159_A_3_), .B(intadd_1148_SUM_3_),
.C(intadd_1159_n3), .CO(intadd_1159_n2), .S(intadd_1159_SUM_3_) );
CMPR32X2TS intadd_1160_U6 ( .A(intadd_1147_SUM_7_), .B(intadd_1160_B_0_),
.C(intadd_1147_SUM_0_), .CO(intadd_1160_n5), .S(intadd_1160_SUM_0_) );
CMPR32X2TS intadd_1160_U3 ( .A(intadd_1160_A_3_), .B(intadd_1147_SUM_3_),
.C(intadd_1160_n3), .CO(intadd_1160_n2), .S(intadd_1160_SUM_3_) );
CMPR32X2TS intadd_1160_U2 ( .A(intadd_1160_A_4_), .B(intadd_1147_SUM_4_),
.C(intadd_1160_n2), .CO(intadd_1160_n1), .S(intadd_1160_SUM_4_) );
CMPR32X2TS intadd_1161_U4 ( .A(FPMULT_Op_MX[8]), .B(FPMULT_Op_MX[2]), .C(
intadd_1161_n4), .CO(intadd_1161_n3), .S(intadd_1161_SUM_1_) );
CMPR32X2TS intadd_1161_U2 ( .A(FPMULT_Op_MX[10]), .B(FPMULT_Op_MX[4]), .C(
intadd_1161_n2), .CO(intadd_1161_n1), .S(intadd_1161_SUM_3_) );
CMPR32X2TS intadd_1162_U5 ( .A(n959), .B(FPMULT_Op_MY[19]), .C(
intadd_1162_CI), .CO(intadd_1162_n4), .S(intadd_1162_SUM_0_) );
CMPR32X2TS intadd_1162_U4 ( .A(FPMULT_Op_MY[14]), .B(FPMULT_Op_MY[20]), .C(
intadd_1162_n4), .CO(intadd_1162_n3), .S(intadd_1162_SUM_1_) );
CMPR32X2TS intadd_1162_U3 ( .A(FPMULT_Op_MY[15]), .B(FPMULT_Op_MY[21]), .C(
intadd_1162_n3), .CO(intadd_1162_n2), .S(intadd_1162_SUM_2_) );
CMPR32X2TS intadd_1163_U4 ( .A(FPMULT_Op_MX[14]), .B(FPMULT_Op_MX[20]), .C(
intadd_1163_n4), .CO(intadd_1163_n3), .S(intadd_1163_SUM_1_) );
CMPR32X2TS intadd_1164_U4 ( .A(n2482), .B(FPSENCOS_d_ff2_X[24]), .C(
intadd_1164_CI), .CO(intadd_1164_n3), .S(FPSENCOS_sh_exp_x[1]) );
CMPR32X2TS intadd_1164_U3 ( .A(FPSENCOS_d_ff2_X[25]), .B(n908), .C(
intadd_1164_n3), .CO(intadd_1164_n2), .S(FPSENCOS_sh_exp_x[2]) );
DFFSX2TS R_10 ( .D(n2668), .CK(clk), .SN(n2711), .Q(n2776) );
DFFSX2TS R_18 ( .D(n2666), .CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175),
.SN(n2689), .Q(n2781) );
DFFSX2TS R_21 ( .D(n2663), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8354391), .SN(n2705), .Q(n2778)
);
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_27_ ( .D(1'b1), .CK(
FPSENCOS_reg_shift_y_net8354463), .RN(n2728), .Q(
FPSENCOS_d_ff3_LUT_out[27]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(add_subt_data2[0]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2695), .Q(
FPADDSUB_intDY_EWSW[0]), .QN(n2656) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(add_subt_data2[26]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n1105), .Q(
FPADDSUB_intDY_EWSW[26]), .QN(n2655) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(add_subt_data2[25]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2683), .Q(
FPADDSUB_intDY_EWSW[25]), .QN(n2652) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(add_subt_data2[17]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2678), .Q(
FPADDSUB_intDY_EWSW[17]), .QN(n2651) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(add_subt_data2[11]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2679), .Q(
FPADDSUB_intDY_EWSW[11]), .QN(n2650) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(add_subt_data2[1]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2680), .Q(
FPADDSUB_intDY_EWSW[1]), .QN(n2649) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(add_subt_data2[18]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2695), .Q(
FPADDSUB_intDY_EWSW[18]), .QN(n2648) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(add_subt_data2[8]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2689), .Q(
FPADDSUB_intDY_EWSW[8]), .QN(n2647) );
DFFRX1TS FPSENCOS_reg_operation_Q_reg_0_ ( .D(n2791), .CK(
FPSENCOS_reg_Z0_net8354463), .RN(n2708), .Q(
FPSENCOS_d_ff1_operation_out), .QN(n2644) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(add_subt_data2[9]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2676), .Q(
FPADDSUB_intDY_EWSW[9]), .QN(n2643) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(add_subt_data2[20]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2685), .Q(
FPADDSUB_intDY_EWSW[20]), .QN(n2642) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(add_subt_data2[13]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2678), .Q(
FPADDSUB_intDY_EWSW[13]), .QN(n2641) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(add_subt_data2[21]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2679), .Q(
FPADDSUB_intDY_EWSW[21]), .QN(n2640) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(add_subt_data2[24]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n913), .Q(
FPADDSUB_intDY_EWSW[24]), .QN(n2639) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(add_subt_data2[27]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2689), .Q(
FPADDSUB_intDY_EWSW[27]), .QN(n2638) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(add_subt_data2[2]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2686), .Q(
FPADDSUB_intDY_EWSW[2]), .QN(n2637) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(add_subt_data2[4]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2692), .Q(
FPADDSUB_intDY_EWSW[4]), .QN(n2636) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(add_subt_data2[16]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2687), .Q(
FPADDSUB_intDY_EWSW[16]), .QN(n2635) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(add_subt_data2[6]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2678), .Q(
FPADDSUB_intDY_EWSW[6]), .QN(n2634) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(add_subt_data2[10]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2695), .Q(
FPADDSUB_intDY_EWSW[10]), .QN(n2633) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(add_subt_data1[12]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2689), .Q(
FPADDSUB_intDX_EWSW[12]), .QN(n2632) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_20_ ( .D(FPADDSUB_Data_array_SWR[20]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8354211), .RN(n913), .Q(
FPADDSUB_Data_array_SWR[45]), .QN(n2629) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[23]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2684), .Q(
FPADDSUB_DmP_mant_SFG_SWR[23]), .QN(n2627) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_1_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]), .CK(clk), .RN(n949), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .QN(n2626) );
DFFRX1TS FPMULT_Sel_C_Q_reg_0_ ( .D(n825), .CK(FPMULT_FS_Module_net8354445),
.RN(n2720), .Q(FPMULT_FSM_selector_C), .QN(n2624) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_23_ ( .D(FPADDSUB_Data_array_SWR[23]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8354211), .RN(n2693), .Q(
FPADDSUB_Data_array_SWR[48]), .QN(n2619) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[24]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2694), .Q(
FPADDSUB_DmP_mant_SFG_SWR[24]), .QN(n2618) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_22_ ( .D(FPADDSUB_Data_array_SWR[22]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8354211), .RN(n1105), .Q(
FPADDSUB_Data_array_SWR[47]), .QN(n2617) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n872), .CK(clk), .RN(n2691), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .QN(n2614) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(add_subt_data2[7]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2686), .Q(
FPADDSUB_intDY_EWSW[7]), .QN(n2612) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(add_subt_data1[13]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2677), .Q(
FPADDSUB_intDX_EWSW[13]), .QN(n2611) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(add_subt_data1[3]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2689), .Q(
FPADDSUB_intDX_EWSW[3]), .QN(n2610) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(add_subt_data1[17]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n1105), .Q(
FPADDSUB_intDX_EWSW[17]), .QN(n2609) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(add_subt_data1[11]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n913), .Q(
FPADDSUB_intDX_EWSW[11]), .QN(n2608) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(add_subt_data1[21]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2685), .Q(
FPADDSUB_intDX_EWSW[21]), .QN(n2607) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(add_subt_data1[15]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n912), .Q(
FPADDSUB_intDX_EWSW[15]), .QN(n2606) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(add_subt_data1[18]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2694), .Q(
FPADDSUB_intDX_EWSW[18]), .QN(n2604) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(add_subt_data1[14]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n913), .Q(
FPADDSUB_intDX_EWSW[14]), .QN(n2603) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(add_subt_data1[8]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2682), .Q(
FPADDSUB_intDX_EWSW[8]), .QN(n2602) );
DFFRX1TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(
FPADDSUB_shft_value_mux_o_EWR[2]), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8354211), .RN(n2682), .Q(
FPADDSUB_shift_value_SHT2_EWR[2]), .QN(n2599) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(add_subt_data2[30]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2678), .Q(
FPADDSUB_intDY_EWSW[30]), .QN(n2598) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(
FPADDSUB_Raw_mant_SGF[16]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8354211), .RN(n2684), .Q(FPADDSUB_Raw_mant_NRM_SWR[16]), .QN(n2596) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(
FPADDSUB_Raw_mant_SGF[20]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8354211), .RN(n2693), .Q(FPADDSUB_Raw_mant_NRM_SWR[20]), .QN(n2591) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[19]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2685), .Q(
FPADDSUB_DmP_mant_SFG_SWR[19]), .QN(n2590) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(
FPADDSUB_formatted_number_W[23]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8354175), .RN(n2676), .Q(
result_add_subt[23]), .QN(n2589) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(
FPADDSUB_formatted_number_W[24]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8354175), .RN(n2691), .Q(
result_add_subt[24]), .QN(n2588) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(
FPADDSUB_formatted_number_W[25]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8354175), .RN(n2684), .Q(
result_add_subt[25]), .QN(n2587) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(
FPADDSUB_formatted_number_W[26]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8354175), .RN(n2696), .Q(
result_add_subt[26]), .QN(n2586) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(
FPADDSUB_formatted_number_W[27]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8354175), .RN(n2690), .Q(
result_add_subt[27]), .QN(n2585) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(
FPADDSUB_formatted_number_W[28]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8354175), .RN(n2687), .Q(
result_add_subt[28]), .QN(n2584) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(
FPADDSUB_formatted_number_W[29]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8354175), .RN(n2695), .Q(
result_add_subt[29]), .QN(n2583) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(
FPADDSUB_formatted_number_W[30]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8354175), .RN(n2697), .Q(
result_add_subt[30]), .QN(n2582) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(
FPADDSUB_formatted_number_W[0]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8354175), .RN(n2682), .Q(
result_add_subt[0]), .QN(n2581) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(
FPADDSUB_formatted_number_W[1]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8354175), .RN(n2690), .Q(
result_add_subt[1]), .QN(n2580) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(
FPADDSUB_formatted_number_W[2]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8354175), .RN(n2689), .Q(
result_add_subt[2]), .QN(n2579) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(
FPADDSUB_formatted_number_W[3]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8354175), .RN(n2683), .Q(
result_add_subt[3]), .QN(n2578) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(
FPADDSUB_formatted_number_W[4]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8354175), .RN(n2692), .Q(
result_add_subt[4]), .QN(n2577) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(
FPADDSUB_formatted_number_W[5]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8354175), .RN(n2695), .Q(
result_add_subt[5]), .QN(n2576) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(
FPADDSUB_formatted_number_W[6]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8354175), .RN(n2681), .Q(
result_add_subt[6]), .QN(n2575) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(
FPADDSUB_formatted_number_W[7]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8354175), .RN(n2688), .Q(
result_add_subt[7]), .QN(n2574) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(
FPADDSUB_formatted_number_W[8]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8354175), .RN(n2694), .Q(
result_add_subt[8]), .QN(n2573) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(
FPADDSUB_formatted_number_W[9]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8354175), .RN(n2694), .Q(
result_add_subt[9]), .QN(n2572) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(
FPADDSUB_formatted_number_W[10]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8354175), .RN(n2680), .Q(
result_add_subt[10]), .QN(n2571) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(
FPADDSUB_formatted_number_W[11]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8354175), .RN(n2693), .Q(
result_add_subt[11]), .QN(n2570) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(
FPADDSUB_formatted_number_W[12]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8354175), .RN(n2680), .Q(
result_add_subt[12]), .QN(n2569) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(
FPADDSUB_formatted_number_W[13]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8354175), .RN(n913), .Q(
result_add_subt[13]), .QN(n2568) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(
FPADDSUB_formatted_number_W[14]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8354175), .RN(n1105), .Q(
result_add_subt[14]), .QN(n2567) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(
FPADDSUB_formatted_number_W[15]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8354175), .RN(n912), .Q(
result_add_subt[15]), .QN(n2566) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(
FPADDSUB_formatted_number_W[16]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8354175), .RN(n2696), .Q(
result_add_subt[16]), .QN(n2565) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(
FPADDSUB_formatted_number_W[17]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8354175), .RN(n1105), .Q(
result_add_subt[17]), .QN(n2564) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(
FPADDSUB_formatted_number_W[18]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8354175), .RN(n2690), .Q(
result_add_subt[18]), .QN(n2563) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(
FPADDSUB_formatted_number_W[20]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8354175), .RN(n2681), .Q(
result_add_subt[20]), .QN(n2561) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(
FPADDSUB_formatted_number_W[21]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8354175), .RN(n2688), .Q(
result_add_subt[21]), .QN(n2560) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(
FPADDSUB_formatted_number_W[31]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8354175), .RN(n2695), .Q(
result_add_subt[31]), .QN(n2558) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[20]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2695), .Q(
FPADDSUB_DmP_mant_SFG_SWR[20]), .QN(n2556) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(
FPADDSUB_Raw_mant_SGF[25]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8354211), .RN(n2677), .Q(FPADDSUB_Raw_mant_NRM_SWR[25]), .QN(n2555) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(FPADDSUB_Raw_mant_SGF[4]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8354211), .RN(n1105), .Q(
FPADDSUB_Raw_mant_NRM_SWR[4]), .QN(n2554) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(
FPADDSUB_Raw_mant_SGF[10]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8354211), .RN(n2691), .Q(FPADDSUB_Raw_mant_NRM_SWR[10]), .QN(n2544) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(
FPADDSUB_Raw_mant_SGF[14]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8354211), .RN(n2696), .Q(FPADDSUB_Raw_mant_NRM_SWR[14]), .QN(n2543) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[18]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2681), .Q(
FPADDSUB_DmP_mant_SFG_SWR[18]), .QN(n2539) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_15_ ( .D(FPADDSUB_DMP_SHT2_EWSW[15]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n1105), .Q(
FPADDSUB_DMP_SFG[15]), .QN(n2537) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_14_ ( .D(FPADDSUB_DMP_SHT2_EWSW[14]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2694), .Q(
FPADDSUB_DMP_SFG[14]), .QN(n2536) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_13_ ( .D(FPADDSUB_DMP_SHT2_EWSW[13]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2690), .Q(
FPADDSUB_DMP_SFG[13]), .QN(n2535) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_11_ ( .D(FPADDSUB_DMP_SHT2_EWSW[11]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2689), .Q(
FPADDSUB_DMP_SFG[11]), .QN(n2534) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_12_ ( .D(FPADDSUB_DMP_SHT2_EWSW[12]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2696), .Q(
FPADDSUB_DMP_SFG[12]), .QN(n2533) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[12]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n913), .Q(
FPADDSUB_DmP_mant_SFG_SWR[12]), .QN(n2531) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[11]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2681), .Q(
FPADDSUB_DmP_mant_SFG_SWR[11]), .QN(n2530) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[10]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2685), .Q(
FPADDSUB_DmP_mant_SFG_SWR[10]), .QN(n2529) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[9]), .CK(FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2686), .Q(FPADDSUB_DmP_mant_SFG_SWR[9]), .QN(n2528) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[8]), .CK(FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2677), .Q(FPADDSUB_DmP_mant_SFG_SWR[8]), .QN(n2527) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_5_ ( .D(FPADDSUB_DMP_SHT2_EWSW[5]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2696), .Q(
FPADDSUB_DMP_SFG[5]), .QN(n2526) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[5]), .CK(FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2690), .Q(FPADDSUB_DmP_mant_SFG_SWR[5]), .QN(n2525) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_4_ ( .D(FPADDSUB_DMP_SHT2_EWSW[4]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2686), .Q(
FPADDSUB_DMP_SFG[4]), .QN(n2524) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_2_ ( .D(FPADDSUB_DMP_SHT2_EWSW[2]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2695), .Q(
FPADDSUB_DMP_SFG[2]), .QN(n2523) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_1_ ( .D(FPADDSUB_DMP_SHT2_EWSW[1]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n913), .Q(
FPADDSUB_DMP_SFG[1]), .QN(n2522) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_0_ ( .D(FPADDSUB_DMP_SHT2_EWSW[0]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2694), .Q(
FPADDSUB_DMP_SFG[0]), .QN(n2521) );
DFFRX1TS FPSENCOS_reg_region_flag_Q_reg_0_ ( .D(region_flag[0]), .CK(
FPSENCOS_reg_Z0_net8354463), .RN(n949), .Q(
FPSENCOS_d_ff1_shift_region_flag_out[0]), .QN(n2520) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(add_subt_data2[19]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n912), .Q(
FPADDSUB_intDY_EWSW[19]), .QN(n2519) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(add_subt_data2[22]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2692), .Q(
FPADDSUB_intDY_EWSW[22]), .QN(n2518) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(add_subt_data2[14]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2683), .Q(
FPADDSUB_intDY_EWSW[14]), .QN(n2517) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_24_ ( .D(FPADDSUB_Data_array_SWR[24]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8354211), .RN(n2682), .Q(
FPADDSUB_Data_array_SWR[49]), .QN(n2516) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(add_subt_data1[0]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2689), .Q(
FPADDSUB_intDX_EWSW[0]), .QN(n2515) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_22_ ( .D(FPADDSUB_DMP_SHT2_EWSW[22]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2687), .Q(
FPADDSUB_DMP_SFG[22]), .QN(n2514) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(add_subt_data1[9]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2682), .Q(
FPADDSUB_intDX_EWSW[9]), .QN(n2513) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(add_subt_data1[23]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2684), .Q(
FPADDSUB_intDX_EWSW[23]), .QN(n2512) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(add_subt_data1[20]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2678), .Q(
FPADDSUB_intDX_EWSW[20]), .QN(n2511) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(add_subt_data1[2]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2688), .Q(
FPADDSUB_intDX_EWSW[2]), .QN(n2509) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(add_subt_data1[1]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2682), .Q(
FPADDSUB_intDX_EWSW[1]), .QN(n2508) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(add_subt_data1[5]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2682), .QN(n2507)
);
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(add_subt_data2[29]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2681), .Q(
FPADDSUB_intDY_EWSW[29]), .QN(n2505) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(
FPADDSUB_Raw_mant_SGF[22]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8354211), .RN(n1105), .Q(FPADDSUB_Raw_mant_NRM_SWR[22]), .QN(n2504) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_17_ ( .D(FPADDSUB_DMP_SHT2_EWSW[17]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2679), .Q(
FPADDSUB_DMP_SFG[17]), .QN(n2502) );
DFFRX1TS FPMULT_FS_Module_state_reg_reg_2_ ( .D(
FPMULT_FS_Module_state_next[2]), .CK(FPMULT_FS_Module_net8354445),
.RN(n2705), .Q(FPMULT_FS_Module_state_reg[2]), .QN(n2497) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[13]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2695), .Q(
FPADDSUB_DmP_mant_SFG_SWR[13]), .QN(n2486) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_6_ ( .D(FPADDSUB_DMP_SHT2_EWSW[6]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n1105), .Q(
FPADDSUB_DMP_SFG[6]), .QN(n2485) );
DFFRX1TS FPSENCOS_reg_region_flag_Q_reg_1_ ( .D(region_flag[1]), .CK(
FPSENCOS_reg_Z0_net8354463), .RN(n949), .Q(
FPSENCOS_d_ff1_shift_region_flag_out[1]), .QN(n2483) );
CMPR32X2TS intadd_1148_U2 ( .A(FPMULT_Op_MY[10]), .B(FPMULT_Op_MY[22]), .C(
intadd_1148_n2), .CO(intadd_1148_n1), .S(intadd_1148_SUM_9_) );
CMPR32X2TS intadd_1159_U4 ( .A(intadd_1148_SUM_9_), .B(intadd_1148_SUM_2_),
.C(intadd_1159_n4), .CO(intadd_1159_n3), .S(intadd_1159_SUM_2_) );
CMPR32X2TS intadd_1147_U2 ( .A(FPMULT_Op_MX[10]), .B(FPMULT_Op_MX[22]), .C(
intadd_1147_n2), .CO(intadd_1147_n1), .S(intadd_1147_SUM_9_) );
CMPR32X2TS intadd_1160_U4 ( .A(intadd_1147_SUM_9_), .B(intadd_1147_SUM_2_),
.C(intadd_1160_n4), .CO(intadd_1160_n3), .S(intadd_1160_SUM_2_) );
CMPR32X2TS DP_OP_234J326_132_4955_U2 ( .A(FPMULT_FSM_exp_operation_A_S), .B(
FPMULT_S_Oper_A_exp[8]), .C(DP_OP_234J326_132_4955_n2), .CO(
DP_OP_234J326_132_4955_n1), .S(FPMULT_Exp_module_Data_S[8]) );
CMPR32X2TS intadd_1144_U7 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[2]), .B(
intadd_1144_B_7_), .C(intadd_1144_n7), .CO(intadd_1144_n6), .S(
intadd_1144_SUM_7_) );
CMPR32X2TS intadd_1144_U4 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[5]), .B(
intadd_1144_B_10_), .C(intadd_1144_n4), .CO(intadd_1144_n3), .S(
intadd_1144_SUM_10_) );
CMPR32X2TS intadd_1144_U3 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[6]), .B(
intadd_1144_B_11_), .C(intadd_1144_n3), .CO(intadd_1144_n2), .S(
intadd_1144_SUM_11_) );
CMPR32X2TS intadd_1144_U2 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[7]), .B(
intadd_1144_B_12_), .C(intadd_1144_n2), .CO(intadd_1144_n1), .S(
intadd_1144_SUM_12_) );
CMPR32X2TS intadd_1148_U10 ( .A(FPMULT_Op_MY[14]), .B(FPMULT_Op_MY[2]), .C(
intadd_1148_n10), .CO(intadd_1148_n9), .S(intadd_1148_SUM_1_) );
CMPR32X2TS intadd_1148_U9 ( .A(FPMULT_Op_MY[15]), .B(FPMULT_Op_MY[3]), .C(
intadd_1148_n9), .CO(intadd_1148_n8), .S(intadd_1148_SUM_2_) );
CMPR32X2TS intadd_1148_U8 ( .A(FPMULT_Op_MY[16]), .B(FPMULT_Op_MY[4]), .C(
intadd_1148_n8), .CO(intadd_1148_n7), .S(intadd_1148_SUM_3_) );
CMPR32X2TS intadd_1148_U7 ( .A(FPMULT_Op_MY[17]), .B(FPMULT_Op_MY[5]), .C(
intadd_1148_n7), .CO(intadd_1148_n6), .S(intadd_1148_SUM_4_) );
CMPR32X2TS intadd_1148_U6 ( .A(FPMULT_Op_MY[6]), .B(FPMULT_Op_MY[18]), .C(
intadd_1148_n6), .CO(intadd_1148_n5), .S(intadd_1148_SUM_5_) );
CMPR32X2TS intadd_1148_U3 ( .A(FPMULT_Op_MY[9]), .B(FPMULT_Op_MY[21]), .C(
intadd_1148_n3), .CO(intadd_1148_n2), .S(intadd_1148_SUM_8_) );
CMPR32X2TS intadd_1147_U10 ( .A(FPMULT_Op_MX[14]), .B(FPMULT_Op_MX[2]), .C(
intadd_1147_n10), .CO(intadd_1147_n9), .S(intadd_1147_SUM_1_) );
CMPR32X2TS intadd_1147_U8 ( .A(FPMULT_Op_MX[16]), .B(FPMULT_Op_MX[4]), .C(
intadd_1147_n8), .CO(intadd_1147_n7), .S(intadd_1147_SUM_3_) );
CMPR32X2TS intadd_1147_U6 ( .A(FPMULT_Op_MX[6]), .B(FPMULT_Op_MX[18]), .C(
intadd_1147_n6), .CO(intadd_1147_n5), .S(intadd_1147_SUM_5_) );
CMPR32X2TS intadd_1147_U5 ( .A(FPMULT_Op_MX[7]), .B(FPMULT_Op_MX[19]), .C(
intadd_1147_n5), .CO(intadd_1147_n4), .S(intadd_1147_SUM_6_) );
CMPR32X2TS intadd_1147_U4 ( .A(FPMULT_Op_MX[8]), .B(FPMULT_Op_MX[20]), .C(
intadd_1147_n4), .CO(intadd_1147_n3), .S(intadd_1147_SUM_7_) );
CMPR32X2TS intadd_1147_U3 ( .A(FPMULT_Op_MX[9]), .B(FPMULT_Op_MX[21]), .C(
intadd_1147_n3), .CO(intadd_1147_n2), .S(intadd_1147_SUM_8_) );
CMPR32X2TS intadd_1160_U5 ( .A(intadd_1147_SUM_1_), .B(intadd_1147_SUM_8_),
.C(intadd_1160_n5), .CO(intadd_1160_n4), .S(intadd_1160_SUM_1_) );
CMPR32X2TS intadd_1159_U2 ( .A(intadd_1159_A_4_), .B(intadd_1148_SUM_4_),
.C(intadd_1159_n2), .CO(intadd_1159_n1), .S(intadd_1159_SUM_4_) );
CMPR32X2TS DP_OP_234J326_132_4955_U9 ( .A(DP_OP_234J326_132_4955_n21), .B(
FPMULT_S_Oper_A_exp[1]), .C(DP_OP_234J326_132_4955_n9), .CO(
DP_OP_234J326_132_4955_n8), .S(FPMULT_Exp_module_Data_S[1]) );
CMPR32X2TS DP_OP_234J326_132_4955_U8 ( .A(DP_OP_234J326_132_4955_n20), .B(
FPMULT_S_Oper_A_exp[2]), .C(DP_OP_234J326_132_4955_n8), .CO(
DP_OP_234J326_132_4955_n7), .S(FPMULT_Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_234J326_132_4955_U7 ( .A(DP_OP_234J326_132_4955_n19), .B(
FPMULT_S_Oper_A_exp[3]), .C(DP_OP_234J326_132_4955_n7), .CO(
DP_OP_234J326_132_4955_n6), .S(FPMULT_Exp_module_Data_S[3]) );
CMPR32X2TS DP_OP_234J326_132_4955_U6 ( .A(DP_OP_234J326_132_4955_n18), .B(
FPMULT_S_Oper_A_exp[4]), .C(DP_OP_234J326_132_4955_n6), .CO(
DP_OP_234J326_132_4955_n5), .S(FPMULT_Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_234J326_132_4955_U5 ( .A(DP_OP_234J326_132_4955_n17), .B(
FPMULT_S_Oper_A_exp[5]), .C(DP_OP_234J326_132_4955_n5), .CO(
DP_OP_234J326_132_4955_n4), .S(FPMULT_Exp_module_Data_S[5]) );
CMPR32X2TS DP_OP_234J326_132_4955_U4 ( .A(DP_OP_234J326_132_4955_n16), .B(
FPMULT_S_Oper_A_exp[6]), .C(DP_OP_234J326_132_4955_n4), .CO(
DP_OP_234J326_132_4955_n3), .S(FPMULT_Exp_module_Data_S[6]) );
CMPR32X2TS DP_OP_234J326_132_4955_U3 ( .A(DP_OP_234J326_132_4955_n15), .B(
FPMULT_S_Oper_A_exp[7]), .C(DP_OP_234J326_132_4955_n3), .CO(
DP_OP_234J326_132_4955_n2), .S(FPMULT_Exp_module_Data_S[7]) );
CMPR32X2TS DP_OP_26J326_129_1325_U5 ( .A(DP_OP_26J326_129_1325_n14), .B(
FPADDSUB_DMP_exp_NRM2_EW[4]), .C(DP_OP_26J326_129_1325_n5), .CO(
DP_OP_26J326_129_1325_n4), .S(FPADDSUB_exp_rslt_NRM2_EW1[4]) );
CMPR32X2TS DP_OP_26J326_129_1325_U4 ( .A(n951), .B(
FPADDSUB_DMP_exp_NRM2_EW[5]), .C(DP_OP_26J326_129_1325_n4), .CO(
DP_OP_26J326_129_1325_n3), .S(FPADDSUB_exp_rslt_NRM2_EW1[5]) );
CMPR32X2TS DP_OP_26J326_129_1325_U3 ( .A(n951), .B(
FPADDSUB_DMP_exp_NRM2_EW[6]), .C(DP_OP_26J326_129_1325_n3), .CO(
DP_OP_26J326_129_1325_n2), .S(FPADDSUB_exp_rslt_NRM2_EW1[6]) );
CMPR32X2TS DP_OP_26J326_129_1325_U2 ( .A(n951), .B(
FPADDSUB_DMP_exp_NRM2_EW[7]), .C(DP_OP_26J326_129_1325_n2), .CO(
DP_OP_26J326_129_1325_n1), .S(FPADDSUB_exp_rslt_NRM2_EW1[7]) );
DFFRHQX2TS FPSENCOS_VAR_CONT_temp_reg_0_ ( .D(n841), .CK(clk), .RN(n2709),
.Q(n2675) );
DFFSXLTS R_4 ( .D(n2671), .CK(FPMULT_Sgf_operation_EVEN1_finalreg_net8354391), .SN(n2717), .Q(n2779) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_0_ ( .D(n2503), .CK(
FPSENCOS_ITER_CONT_net8354499), .RN(n949), .Q(
FPSENCOS_cont_iter_out[0]), .QN(n2503) );
DFFRX2TS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_1_ ( .D(FPADDSUB_OP_FLAG_SHT2), .CK(
FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n912), .Q(FPADDSUB_OP_FLAG_SFG), .QN(n922) );
DFFRX2TS FPADDSUB_inst_ShiftRegister_Q_reg_4_ ( .D(
FPADDSUB_Shift_reg_FLAGS_7_5), .CK(
FPADDSUB_inst_ShiftRegister_net8354337), .RN(n912), .Q(busy), .QN(
n2630) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_1_ ( .D(FPSENCOS_ITER_CONT_N3), .CK(
FPSENCOS_ITER_CONT_net8354499), .RN(n949), .Q(
FPSENCOS_cont_iter_out[1]), .QN(n2482) );
DFFRX2TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(n2792), .CK(
clk), .RN(n2692), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]),
.QN(n2613) );
DFFRX2TS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n808), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8354211), .RN(n2697), .Q(
FPADDSUB_ADD_OVRFLW_NRM2) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_3_ ( .D(
FPMULT_FS_Module_state_next[3]), .CK(FPMULT_FS_Module_net8354445),
.RN(n2705), .Q(FPMULT_FS_Module_state_reg[3]), .QN(n2593) );
DFFRX2TS FPMULT_Sel_B_Q_reg_1_ ( .D(n830), .CK(FPMULT_FS_Module_net8354445),
.RN(n2721), .Q(FPMULT_FSM_selector_B[1]), .QN(n2595) );
DFFRX2TS FPSENCOS_VAR_CONT_temp_reg_1_ ( .D(n840), .CK(clk), .RN(n2709), .Q(
FPSENCOS_cont_var_out_1_), .QN(n2506) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_8_ ( .D(Data_2[8]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2727), .Q(
FPMULT_Op_MY[8]), .QN(n2545) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_10_ ( .D(Data_2[10]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2721), .Q(
FPMULT_Op_MY[10]), .QN(n2552) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_9_ ( .D(Data_2[9]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2720), .Q(
FPMULT_Op_MY[9]), .QN(n2470) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_2_ ( .D(Data_2[2]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2724), .Q(
FPMULT_Op_MY[2]), .QN(n2499) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_21_ ( .D(Data_2[21]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2726), .Q(
FPMULT_Op_MY[21]), .QN(n2550) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_11_ ( .D(Data_2[11]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2720), .Q(
FPMULT_Op_MY[11]), .QN(n2542) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_16_ ( .D(Data_2[16]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2727), .Q(
FPMULT_Op_MY[16]), .QN(n2553) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_4_ ( .D(Data_2[4]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2727), .Q(
FPMULT_Op_MY[4]), .QN(n2551) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_14_ ( .D(Data_2[14]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2722), .Q(
FPMULT_Op_MY[14]), .QN(n2500) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_17_ ( .D(Data_2[17]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2719), .Q(
FPMULT_Op_MY[17]), .QN(n2495) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_19_ ( .D(Data_2[19]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2725), .Q(
FPMULT_Op_MY[19]), .QN(n2469) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_18_ ( .D(Data_2[18]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2720), .Q(
FPMULT_Op_MY[18]), .QN(n2532) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_5_ ( .D(Data_2[5]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2723), .Q(
FPMULT_Op_MY[5]), .QN(n2496) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_22_ ( .D(Data_2[22]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2727), .Q(
FPMULT_Op_MY[22]), .QN(n2548) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_20_ ( .D(Data_2[20]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2721), .Q(
FPMULT_Op_MY[20]), .QN(n2549) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_15_ ( .D(Data_2[15]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2724), .Q(
FPMULT_Op_MY[15]), .QN(n2471) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_3_ ( .D(Data_2[3]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2726), .Q(
FPMULT_Op_MY[3]), .QN(n2472) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_5_ ( .D(Data_1[5]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2719), .Q(
FPMULT_Op_MX[5]), .QN(n2546) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_4_ ( .D(Data_1[4]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2721), .Q(
FPMULT_Op_MX[4]), .QN(n2475) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_22_ ( .D(Data_1[22]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2726), .Q(
FPMULT_Op_MX[22]), .QN(n2501) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_20_ ( .D(Data_1[20]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2725), .Q(
FPMULT_Op_MX[20]), .QN(n2492) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_9_ ( .D(Data_1[9]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2726), .Q(
FPMULT_Op_MX[9]), .QN(n2493) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_0_ ( .D(Data_1[0]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2721), .Q(
FPMULT_Op_MX[0]), .QN(n2473) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_2_ ( .D(Data_1[2]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2721), .Q(
FPMULT_Op_MX[2]), .QN(n2540) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_19_ ( .D(Data_1[19]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2722), .Q(
FPMULT_Op_MX[19]), .QN(n2494) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_16_ ( .D(Data_1[16]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2724), .Q(
FPMULT_Op_MX[16]), .QN(n2476) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_15_ ( .D(Data_1[15]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2722), .Q(
FPMULT_Op_MX[15]), .QN(n2479) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_7_ ( .D(Data_1[7]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2719), .Q(
FPMULT_Op_MX[7]), .QN(n2498) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_17_ ( .D(Data_1[17]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2725), .Q(
FPMULT_Op_MX[17]), .QN(n2547) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_14_ ( .D(Data_1[14]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2720), .Q(
FPMULT_Op_MX[14]), .QN(n2541) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_10_ ( .D(Data_1[10]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2726), .Q(
FPMULT_Op_MX[10]), .QN(n2491) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_6_ ( .D(Data_1[6]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2725), .Q(
FPMULT_Op_MX[6]), .QN(n2484) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_1_ ( .D(Data_1[1]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2721), .Q(
FPMULT_Op_MX[1]), .QN(n2480) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_21_ ( .D(Data_1[21]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2719), .Q(
FPMULT_Op_MX[21]), .QN(n2474) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_13_ ( .D(Data_1[13]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2724), .Q(
FPMULT_Op_MX[13]), .QN(n2481) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_8_ ( .D(Data_1[8]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2722), .Q(
FPMULT_Op_MX[8]), .QN(n2477) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_3_ ( .D(Data_1[3]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2721), .Q(
FPMULT_Op_MX[3]), .QN(n2478) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(add_subt_data2[12]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2692), .Q(
FPADDSUB_intDY_EWSW[12]), .QN(n2601) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(add_subt_data2[3]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2688), .Q(
FPADDSUB_intDY_EWSW[3]), .QN(n2657) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(add_subt_data1[4]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n912), .Q(
FPADDSUB_intDX_EWSW[4]), .QN(n2605) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(add_subt_data2[23]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2691), .Q(
FPADDSUB_intDY_EWSW[23]), .QN(n2654) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(add_subt_data1[7]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2689), .Q(
FPADDSUB_intDX_EWSW[7]), .QN(n2625) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(add_subt_data1[6]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2679), .Q(
FPADDSUB_intDX_EWSW[6]), .QN(n2510) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(add_subt_data1[10]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n912), .Q(
FPADDSUB_intDX_EWSW[10]), .QN(n2600) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(add_subt_data1[16]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n912), .Q(
FPADDSUB_intDX_EWSW[16]), .QN(n2623) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(add_subt_data2[15]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2692), .Q(
FPADDSUB_intDY_EWSW[15]), .QN(n2653) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(add_subt_data2[5]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2678), .Q(
FPADDSUB_intDY_EWSW[5]), .QN(n2631) );
DFFXLTS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(mult_x_309_n33), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[0]), .QN(n2744)
);
DFFXLTS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[2]),
.QN(intadd_1146_B_0_) );
DFFXLTS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N1), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[1]),
.QN(n2746) );
DFFXLTS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N0), .CK(clk), .QN(intadd_1143_B_0_) );
DFFXLTS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[3]),
.QN(n2735) );
DFFXLTS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[4]),
.QN(n2733) );
DFFXLTS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[2]),
.QN(n2751) );
DFFXLTS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[5]),
.QN(n2732) );
DFFXLTS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[3]),
.QN(n2753) );
DFFXLTS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N0), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[0]) );
DFFXLTS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[6]),
.QN(n2736) );
DFFXLTS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[4]),
.QN(n2755) );
DFFXLTS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[7]),
.QN(n2730) );
DFFXLTS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[2])
);
DFFXLTS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N1), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[1]),
.QN(n2747) );
DFFXLTS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[5]),
.QN(n2757) );
DFFXLTS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[6]),
.QN(n2759) );
DFFXLTS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[7]),
.QN(n2762) );
DFFXLTS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[7]),
.QN(n2761) );
DFFXLTS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[8]),
.QN(n2764) );
DFFXLTS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[3])
);
DFFXLTS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[9]),
.QN(n2765) );
DFFXLTS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[2]) );
DFFXLTS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(intadd_1155_n1), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[11]), .QN(
n2767) );
DFFXLTS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[10]),
.QN(n2766) );
DFFXLTS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[7]),
.QN(n2731) );
DFFXLTS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[4])
);
DFFXLTS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(intadd_1154_n1), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[11]), .QN(
n2768) );
DFFXLTS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[8]),
.QN(n2739) );
DFFXLTS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[3]) );
DFFXLTS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[9]),
.QN(n2740) );
DFFXLTS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N1), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[1]),
.QN(n2772) );
DFFXLTS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(intadd_1153_n1), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[11]), .QN(
n2741) );
DFFXLTS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[5])
);
DFFXLTS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[10]),
.QN(n2729) );
DFFSX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_0_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]), .CK(clk), .SN(n2717), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]) );
DFFRX4TS FPMULT_Sel_A_Q_reg_0_ ( .D(1'b1), .CK(n2788), .RN(n2721), .Q(
FPMULT_FSM_selector_A) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_1_ ( .D(
FPMULT_FS_Module_state_next[1]), .CK(FPMULT_FS_Module_net8354445),
.RN(n2711), .Q(FPMULT_FS_Module_state_reg[1]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_12_ ( .D(Data_1[12]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2723), .Q(
FPMULT_Op_MX[12]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(
FPADDSUB_Raw_mant_SGF[23]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8354211), .RN(n1105), .Q(FPADDSUB_Raw_mant_NRM_SWR[23]) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_5_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]), .CK(clk), .RN(n949), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_7_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]), .CK(clk), .RN(n949), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_6_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]), .CK(clk), .RN(n2709), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .QN(n943) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_10_ ( .D(FPADDSUB_DMP_SHT2_EWSW[10]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n912), .Q(
FPADDSUB_DMP_SFG[10]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[7]), .CK(FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2692), .Q(FPADDSUB_DmP_mant_SFG_SWR[7]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_9_ ( .D(FPADDSUB_DMP_SHT2_EWSW[9]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n912), .Q(
FPADDSUB_DMP_SFG[9]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_7_ ( .D(FPADDSUB_DMP_SHT2_EWSW[7]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2695), .Q(
FPADDSUB_DMP_SFG[7]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_8_ ( .D(FPADDSUB_DMP_SHT2_EWSW[8]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2692), .Q(
FPADDSUB_DMP_SFG[8]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[4]), .CK(FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n912), .Q(FPADDSUB_DmP_mant_SFG_SWR[4]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(
FPADDSUB_Raw_mant_SGF[24]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8354211), .RN(n2686), .Q(FPADDSUB_Raw_mant_NRM_SWR[24]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[15]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2681), .Q(
FPADDSUB_DmP_mant_SFG_SWR[15]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[3]), .CK(FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n912), .Q(FPADDSUB_DmP_mant_SFG_SWR[3]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[17]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n1105), .Q(
FPADDSUB_DmP_mant_SFG_SWR[17]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[6]), .CK(FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2692), .Q(FPADDSUB_DmP_mant_SFG_SWR[6]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(
FPADDSUB_Raw_mant_SGF[11]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8354211), .RN(n912), .Q(FPADDSUB_Raw_mant_NRM_SWR[11]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(
FPADDSUB_Raw_mant_SGF[18]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8354211), .RN(n912), .Q(FPADDSUB_Raw_mant_NRM_SWR[18]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[2]), .CK(FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n912), .Q(FPADDSUB_DmP_mant_SFG_SWR[2]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(FPADDSUB_Raw_mant_SGF[9]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8354211), .RN(n2692), .Q(
FPADDSUB_Raw_mant_NRM_SWR[9]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[16]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2685), .Q(
FPADDSUB_DmP_mant_SFG_SWR[16]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[14]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2678), .Q(
FPADDSUB_DmP_mant_SFG_SWR[14]) );
DFFRX2TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(
FPADDSUB_shft_value_mux_o_EWR[3]), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8354211), .RN(n2678), .Q(
FPADDSUB_shift_value_SHT2_EWR[3]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(
FPADDSUB_Raw_mant_SGF[17]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8354211), .RN(n912), .Q(FPADDSUB_Raw_mant_NRM_SWR[17]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_16_ ( .D(FPADDSUB_DMP_SHT2_EWSW[16]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2681), .Q(
FPADDSUB_DMP_SFG[16]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(
FPADDSUB_Raw_mant_SGF[21]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8354211), .RN(n1105), .Q(FPADDSUB_Raw_mant_NRM_SWR[21]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_3_ ( .D(FPADDSUB_DMP_SHT2_EWSW[3]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2685), .Q(
FPADDSUB_DMP_SFG[3]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(FPADDSUB_Raw_mant_SGF[5]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8354211), .RN(n2681), .Q(
FPADDSUB_Raw_mant_NRM_SWR[5]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(add_subt_data2[28]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2693), .Q(
FPADDSUB_intDY_EWSW[28]) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_2_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]), .CK(clk), .RN(n949), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_18_ ( .D(FPADDSUB_DMP_SHT2_EWSW[18]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2683), .Q(
FPADDSUB_DMP_SFG[18]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_17_ ( .D(FPADDSUB_Data_array_SWR[17]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8354211), .RN(n2677), .Q(
FPADDSUB_Data_array_SWR[42]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_16_ ( .D(FPADDSUB_Data_array_SWR[16]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8354211), .RN(n912), .Q(
FPADDSUB_Data_array_SWR[41]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(FPADDSUB_N59), .CK(
FPADDSUB_NRM_STAGE_Raw_mant_net8354211), .RN(n1105), .Q(
FPADDSUB_Raw_mant_NRM_SWR[0]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[0]), .CK(FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2689), .Q(FPADDSUB_N59) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(
FPADDSUB_Raw_mant_SGF[15]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8354211), .RN(n2690), .Q(FPADDSUB_Raw_mant_NRM_SWR[15]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_20_ ( .D(FPADDSUB_DMP_SHT2_EWSW[20]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n913), .Q(
FPADDSUB_DMP_SFG[20]) );
DFFRX2TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(
FPADDSUB_shft_value_mux_o_EWR[4]), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8354211), .RN(n2686), .Q(
FPADDSUB_shift_value_SHT2_EWR[4]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_14_ ( .D(FPADDSUB_Data_array_SWR[14]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8354211), .RN(n2691), .Q(
FPADDSUB_Data_array_SWR[39]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_15_ ( .D(FPADDSUB_Data_array_SWR[15]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8354211), .RN(n2695), .Q(
FPADDSUB_Data_array_SWR[40]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_21_ ( .D(FPADDSUB_DMP_SHT2_EWSW[21]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2682), .Q(
FPADDSUB_DMP_SFG[21]) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n842), .CK(clk), .RN(n2684), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_27_ ( .D(
FPSENCOS_first_mux_X[27]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2716), .Q(FPSENCOS_d_ff2_X[27]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(
FPADDSUB_Raw_mant_SGF[13]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8354211), .RN(n2687), .Q(FPADDSUB_Raw_mant_NRM_SWR[13]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[21]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2682), .Q(
FPADDSUB_DmP_mant_SFG_SWR[21]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(
FPMULT_Adder_M_result_A_adder[17]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8354355), .RN(n2718), .Q(
FPMULT_Add_result[17]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(
FPMULT_Adder_M_result_A_adder[16]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8354355), .RN(n2718), .Q(
FPMULT_Add_result[16]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(
FPMULT_Adder_M_result_A_adder[15]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8354355), .RN(n2718), .Q(
FPMULT_Add_result[15]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(
FPMULT_Adder_M_result_A_adder[14]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8354355), .RN(n2718), .Q(
FPMULT_Add_result[14]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(
FPMULT_Adder_M_result_A_adder[13]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8354355), .RN(n2718), .Q(
FPMULT_Add_result[13]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(
FPMULT_Adder_M_result_A_adder[12]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8354355), .RN(n2718), .Q(
FPMULT_Add_result[12]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_6_ ( .D(Data_2[6]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2725), .Q(
FPMULT_Op_MY[6]) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_7_ ( .D(Data_2[7]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2727), .Q(
FPMULT_Op_MY[7]), .QN(n2538) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(add_subt_data1[25]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2696), .Q(
FPADDSUB_intDX_EWSW[25]), .QN(n938) );
DFFX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6), .CK(clk), .QN(n2760) );
DFFX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9), .CK(clk), .QN(n2770) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(add_subt_data1[26]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2690), .Q(
FPADDSUB_intDX_EWSW[26]), .QN(n926) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_8_ ( .D(FPADDSUB_Data_array_SWR[8]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8354211), .RN(n2687), .Q(
FPADDSUB_Data_array_SWR[34]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_10_ ( .D(FPADDSUB_Data_array_SWR[10]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8354211), .RN(n2676), .Q(
FPADDSUB_Data_array_SWR[35]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(add_subt_data1[19]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n912), .Q(
FPADDSUB_intDX_EWSW[19]), .QN(n939) );
DFFX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]),
.QN(n2738) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_21_ ( .D(FPADDSUB_Data_array_SWR[21]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8354211), .RN(n912), .Q(
FPADDSUB_Data_array_SWR[46]), .QN(n2622) );
DFFRX1TS operation_dff_Q_reg_0_ ( .D(operation[1]), .CK(clk), .RN(n947), .Q(
operation_reg[0]) );
DFFX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10), .CK(clk), .QN(n2745) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(add_subt_data1[22]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2692), .Q(
FPADDSUB_intDX_EWSW[22]), .QN(n934) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_29_ ( .D(
FPSENCOS_first_mux_X[29]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n919), .Q(FPSENCOS_d_ff2_X[29]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(add_subt_data1[27]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2687), .Q(
FPADDSUB_intDX_EWSW[27]), .QN(n935) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_4_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]), .CK(clk), .RN(n949), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(add_subt_data1[30]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2689), .Q(
FPADDSUB_intDX_EWSW[30]), .QN(n2615) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n2795), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8354373), .RN(n2725), .Q(
FPMULT_Sgf_normalized_result[2]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(add_subt_data1[29]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8354175), .RN(n2694), .Q(
FPADDSUB_intDX_EWSW[29]), .QN(n2616) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n2797), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8354373), .RN(n2719), .Q(
FPMULT_Sgf_normalized_result[4]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n2799), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8354373), .RN(n2720), .Q(
FPMULT_Sgf_normalized_result[6]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n2801), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8354373), .RN(n2726), .Q(
FPMULT_Sgf_normalized_result[8]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n2803), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8354373), .RN(n2724), .Q(
FPMULT_Sgf_normalized_result[10]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n2805), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8354373), .RN(n2722), .Q(
FPMULT_Sgf_normalized_result[12]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n2807), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8354373), .RN(n2723), .Q(
FPMULT_Sgf_normalized_result[14]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n2809), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8354373), .RN(n2719), .Q(
FPMULT_Sgf_normalized_result[16]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n2811), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8354373), .RN(n2720), .Q(
FPMULT_Sgf_normalized_result[18]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n2813), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8354373), .RN(n2725), .Q(
FPMULT_Sgf_normalized_result[20]) );
DFFRX1TS FPADDSUB_inst_ShiftRegister_Q_reg_0_ ( .D(n2674), .CK(
FPADDSUB_inst_ShiftRegister_net8354337), .RN(n2687), .Q(
FPADDSUB_Shift_reg_FLAGS_7[0]) );
DFFRX1TS FPADDSUB_Ready_reg_Q_reg_0_ ( .D(FPADDSUB_Shift_reg_FLAGS_7[0]),
.CK(clk), .RN(n2696), .Q(ready_add_subt), .QN(n930) );
DFFRX1TS FPMULT_Sel_B_Q_reg_0_ ( .D(n829), .CK(FPMULT_FS_Module_net8354445),
.RN(n2721), .Q(FPMULT_FSM_selector_B[0]), .QN(n2592) );
DFFX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[2]) );
DFFX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N0), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[0]) );
DFFX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[3]) );
DFFX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N0), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[0]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[1]), .CK(FPADDSUB_SGF_STAGE_DMP_net8354229), .RN(n2694), .Q(FPADDSUB_N60) );
DFFX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N1), .CK(clk), .Q(FPMULT_Sgf_operation_Result[1]), .QN(intadd_1156_A_1_) );
DFFX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N0), .CK(clk), .Q(FPMULT_Sgf_operation_Result[0]), .QN(intadd_1156_A_0_) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_25_ ( .D(
FPSENCOS_first_mux_X[25]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2716), .Q(FPSENCOS_d_ff2_X[25]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_24_ ( .D(
FPSENCOS_first_mux_X[24]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n1104), .Q(FPSENCOS_d_ff2_X[24]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_24_ ( .D(
FPSENCOS_first_mux_Y[24]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2715), .Q(FPSENCOS_d_ff2_Y[24]) );
DFFSX1TS R_19 ( .D(n2665), .CK(clk), .SN(n2728), .Q(n2774) );
DFFRX1TS reg_dataB_Q_reg_30_ ( .D(Data_2[30]), .CK(clk), .RN(n2709), .Q(
dataB[30]) );
DFFRX1TS reg_dataA_Q_reg_30_ ( .D(Data_1[30]), .CK(clk), .RN(n918), .Q(
dataA[30]) );
DFFRX1TS reg_dataA_Q_reg_29_ ( .D(Data_1[29]), .CK(clk), .RN(n2710), .Q(
dataA[29]) );
DFFX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[6]),
.QN(n2737) );
DFFX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[8]),
.QN(n2763) );
DFFX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N1), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[1])
);
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_24_ ( .D(
FPMULT_Sgf_operation_Result[24]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8354391), .RN(n947), .Q(
FPMULT_P_Sgf[24]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_26_ ( .D(
FPMULT_Sgf_operation_Result[26]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8354391), .RN(n2706), .Q(
FPMULT_P_Sgf[26]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_30_ ( .D(
FPMULT_Sgf_operation_Result[30]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8354391), .RN(n2706), .Q(
FPMULT_P_Sgf[30]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_32_ ( .D(
FPMULT_Sgf_operation_Result[32]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8354391), .RN(n919), .Q(
FPMULT_P_Sgf[32]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_34_ ( .D(
FPMULT_Sgf_operation_Result[34]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8354391), .RN(n949), .Q(
FPMULT_P_Sgf[34]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_37_ ( .D(
FPMULT_Sgf_operation_Result[37]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8354391), .RN(n918), .Q(
FPMULT_P_Sgf[37]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_40_ ( .D(
FPMULT_Sgf_operation_Result[40]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8354391), .RN(n917), .Q(
FPMULT_P_Sgf[40]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_26_ ( .D(FPADDSUB_DMP_INIT_EWSW[26]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2679), .Q(
FPADDSUB_DMP_EXP_EWSW[26]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_25_ ( .D(FPADDSUB_DMP_INIT_EWSW[25]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2679), .Q(
FPADDSUB_DMP_EXP_EWSW[25]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_24_ ( .D(FPADDSUB_DMP_INIT_EWSW[24]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8354229), .RN(n2679), .Q(
FPADDSUB_DMP_EXP_EWSW[24]) );
DFFX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N11), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[11]),
.QN(n2742) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_3_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[3]), .CK(clk), .RN(n949), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .QN(n967) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_5_ ( .D(FPADDSUB_Data_array_SWR[5]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8354211), .RN(n912), .Q(
FPADDSUB_Data_array_SWR[31]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(FPADDSUB_Raw_mant_SGF[8]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8354211), .RN(n912), .Q(
FPADDSUB_Raw_mant_NRM_SWR[8]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_13_ ( .D(FPADDSUB_Data_array_SWR[13]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8354211), .RN(n2686), .Q(
FPADDSUB_Data_array_SWR[38]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_12_ ( .D(FPADDSUB_Data_array_SWR[12]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8354211), .RN(n2684), .Q(
FPADDSUB_Data_array_SWR[37]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(FPADDSUB_Raw_mant_SGF[7]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8354211), .RN(n2685), .Q(
FPADDSUB_Raw_mant_NRM_SWR[7]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_18_ ( .D(FPADDSUB_Data_array_SWR[18]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8354211), .RN(n912), .Q(
FPADDSUB_Data_array_SWR[43]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_19_ ( .D(FPADDSUB_Data_array_SWR[19]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8354211), .RN(n2682), .Q(
FPADDSUB_Data_array_SWR[44]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(
FPADDSUB_Raw_mant_SGF[19]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8354211), .RN(n2682), .Q(FPADDSUB_Raw_mant_NRM_SWR[19]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(FPADDSUB_Raw_mant_SGF[2]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8354211), .RN(n2686), .Q(
FPADDSUB_Raw_mant_NRM_SWR[2]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(FPADDSUB_Raw_mant_SGF[3]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8354211), .RN(n913), .Q(
FPADDSUB_Raw_mant_NRM_SWR[3]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_12_ ( .D(Data_2[12]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2723), .Q(
FPMULT_Op_MY[12]) );
DFFX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[10]),
.QN(n2769) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_13_ ( .D(Data_2[13]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2726), .QN(
n2490) );
DFFX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N1), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_Q_left[1]), .QN(n2743) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_1_ ( .D(Data_2[1]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2723), .Q(
FPMULT_Op_MY[1]), .QN(n2489) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_11_ ( .D(FPADDSUB_Data_array_SWR[11]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8354211), .RN(n2684), .Q(
FPADDSUB_Data_array_SWR[36]) );
DFFRX1TS operation_dff_Q_reg_1_ ( .D(operation[2]), .CK(clk), .RN(n2701),
.Q(operation_reg[1]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n2815), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8354373), .RN(n2719), .Q(
FPMULT_Sgf_normalized_result[22]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(
FPADDSUB_formatted_number_W[22]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8354175), .RN(n2680), .Q(
result_add_subt[22]), .QN(n2559) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(
FPADDSUB_formatted_number_W[19]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8354175), .RN(n2689), .Q(
result_add_subt[19]), .QN(n2562) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_11_ ( .D(Data_1[11]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2723), .Q(
FPMULT_Op_MX[11]), .QN(n2488) );
DFFX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N0), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[0]) );
DFFX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[2]) );
DFFRX4TS FPSENCOS_ITER_CONT_temp_reg_3_ ( .D(FPSENCOS_ITER_CONT_N5), .CK(
FPSENCOS_ITER_CONT_net8354499), .RN(n949), .Q(
FPSENCOS_cont_iter_out[3]), .QN(n2594) );
DFFX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_Result[4]), .QN(n2756) );
DFFX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_Result[5]), .QN(n2758) );
DFFX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_Result[2]), .QN(n2752) );
DFFX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_Sgf_operation_Result[3]), .QN(n2754) );
DFFX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N0), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_Q_left[0]), .QN(intadd_1156_CI) );
DFFX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_Q_left[2]), .QN(intadd_1146_CI) );
DFFX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_Q_left[3]), .QN(n2748) );
DFFX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_Q_left[4]), .QN(n2749) );
DFFX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_Q_left[5]), .QN(n2750) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_33_ ( .D(
FPMULT_Sgf_operation_Result[33]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8354391), .RN(n2702), .Q(
FPMULT_P_Sgf[33]) );
DFFRX1TS reg_dataB_Q_reg_28_ ( .D(Data_2[28]), .CK(clk), .RN(n2709), .Q(
dataB[28]) );
DFFRX1TS FPSENCOS_reg_Z0_Q_reg_16_ ( .D(Data_1[16]), .CK(
FPSENCOS_reg_Z0_net8354463), .RN(n2709), .Q(FPSENCOS_d_ff1_Z[16]) );
DFFRX1TS reg_dataB_Q_reg_26_ ( .D(Data_2[26]), .CK(clk), .RN(n2709), .Q(
dataB[26]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_30_ ( .D(
FPSENCOS_first_mux_X[30]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2715), .Q(FPSENCOS_d_ff2_X[30]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_23_ ( .D(
FPSENCOS_first_mux_Y[23]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2715), .Q(FPSENCOS_d_ff2_Y[23]), .QN(n2621) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_26_ ( .D(
FPSENCOS_first_mux_Y[26]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2717), .Q(FPSENCOS_d_ff2_Y[26]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_28_ ( .D(
FPSENCOS_first_mux_Y[28]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n917), .Q(FPSENCOS_d_ff2_Y[28]), .QN(n2659) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n2793), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8354373), .RN(n2726), .Q(
FPMULT_Sgf_normalized_result[0]), .QN(n927) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_26_ ( .D(
FPSENCOS_first_mux_X[26]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n919), .Q(FPSENCOS_d_ff2_X[26]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n2794), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8354373), .RN(n2719), .Q(
FPMULT_Sgf_normalized_result[1]), .QN(n945) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(FPADDSUB_Raw_mant_SGF[6]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8354211), .RN(n2679), .Q(
FPADDSUB_Raw_mant_NRM_SWR[6]), .QN(n2597) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_25_ ( .D(
FPSENCOS_first_mux_Y[25]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2715), .Q(FPSENCOS_d_ff2_Y[25]) );
DFFRX1TS FPMULT_Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(
FPMULT_Adder_M_result_A_adder[24]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8354355), .RN(n2724), .Q(
FPMULT_FSM_add_overflow_flag) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_18_ ( .D(Data_1[18]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2724), .Q(
FPMULT_Op_MX[18]), .QN(n2487) );
DFFX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N1), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[1]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_29_ ( .D(Data_2[29]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2721), .Q(
FPMULT_Op_MY[29]) );
DFFX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N1), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[1]),
.QN(n2734) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(
FPMULT_Adder_M_result_A_adder[22]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8354355), .RN(n2718), .Q(
FPMULT_Add_result[22]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(
FPMULT_Adder_M_result_A_adder[20]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8354355), .RN(n2718), .Q(
FPMULT_Add_result[20]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(
FPMULT_Adder_M_result_A_adder[11]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8354355), .RN(n2723), .Q(
FPMULT_Add_result[11]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(
FPMULT_Adder_M_result_A_adder[9]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8354355), .RN(n2724), .Q(
FPMULT_Add_result[9]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(
FPMULT_Adder_M_result_A_adder[7]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8354355), .RN(n2726), .Q(
FPMULT_Add_result[7]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(
FPMULT_Adder_M_result_A_adder[6]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8354355), .RN(n2722), .Q(
FPMULT_Add_result[6]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(
FPMULT_Adder_M_result_A_adder[3]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8354355), .RN(n2721), .Q(
FPMULT_Add_result[3]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(
FPMULT_Adder_M_result_A_adder[1]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8354355), .RN(n2723), .Q(
FPMULT_Add_result[1]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_44_ ( .D(
FPMULT_Sgf_operation_Result[44]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8354391), .RN(n2705), .Q(
FPMULT_P_Sgf[44]) );
DFFX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]),
.QN(n2771) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_4_ ( .D(FPADDSUB_Data_array_SWR[4]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8354211), .RN(n2695), .Q(
FPADDSUB_Data_array_SWR[30]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(
FPMULT_Adder_M_result_A_adder[21]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8354355), .RN(n2718), .Q(
FPMULT_Add_result[21]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(
FPMULT_Adder_M_result_A_adder[19]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8354355), .RN(n2718), .Q(
FPMULT_Add_result[19]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(
FPMULT_Adder_M_result_A_adder[18]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8354355), .RN(n2718), .Q(
FPMULT_Add_result[18]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(
FPMULT_Adder_M_result_A_adder[10]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8354355), .RN(n2726), .Q(
FPMULT_Add_result[10]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(
FPMULT_Adder_M_result_A_adder[8]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8354355), .RN(n2718), .Q(
FPMULT_Add_result[8]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(
FPMULT_Adder_M_result_A_adder[5]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8354355), .RN(n2718), .Q(
FPMULT_Add_result[5]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(
FPMULT_Adder_M_result_A_adder[4]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8354355), .RN(n2718), .Q(
FPMULT_Add_result[4]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(
FPMULT_Adder_M_result_A_adder[2]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8354355), .RN(n2718), .Q(
FPMULT_Add_result[2]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_41_ ( .D(
FPMULT_Sgf_operation_Result[41]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8354391), .RN(n917), .Q(
FPMULT_P_Sgf[41]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_38_ ( .D(
FPMULT_Sgf_operation_Result[38]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8354391), .RN(n918), .Q(
FPMULT_P_Sgf[38]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_35_ ( .D(
FPMULT_Sgf_operation_Result[35]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8354391), .RN(n2705), .Q(
FPMULT_P_Sgf[35]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_27_ ( .D(
FPMULT_Sgf_operation_Result[27]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8354391), .RN(n916), .Q(
FPMULT_P_Sgf[27]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_28_ ( .D(Data_1[28]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2720), .Q(
FPMULT_Op_MX[28]) );
DFFRX1TS reg_dataA_Q_reg_25_ ( .D(Data_1[25]), .CK(clk), .RN(n2705), .Q(
dataA[25]) );
DFFRX1TS reg_dataA_Q_reg_28_ ( .D(Data_1[28]), .CK(clk), .RN(n918), .Q(
dataA[28]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_6_ ( .D(FPADDSUB_Data_array_SWR[6]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8354211), .RN(n2696), .Q(
FPADDSUB_Data_array_SWR[32]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_45_ ( .D(
FPMULT_Sgf_operation_Result[45]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8354391), .RN(n2711), .Q(
FPMULT_P_Sgf[45]) );
DFFRX1TS reg_dataA_Q_reg_23_ ( .D(Data_1[23]), .CK(clk), .RN(n917), .Q(
dataA[23]) );
DFFRX1TS reg_dataA_Q_reg_27_ ( .D(Data_1[27]), .CK(clk), .RN(n917), .Q(
dataA[27]) );
DFFRX1TS reg_dataB_Q_reg_24_ ( .D(Data_2[24]), .CK(clk), .RN(n919), .Q(
dataB[24]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_26_ ( .D(Data_1[26]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2719), .Q(
FPMULT_Op_MX[26]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_27_ ( .D(Data_1[27]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2725), .Q(
FPMULT_Op_MX[27]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_24_ ( .D(Data_1[24]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2722), .Q(
FPMULT_Op_MX[24]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_7_ ( .D(FPADDSUB_Data_array_SWR[7]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8354211), .RN(n2685), .Q(
FPADDSUB_Data_array_SWR[33]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_43_ ( .D(
FPMULT_Sgf_operation_Result[43]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8354391), .RN(n918), .Q(
FPMULT_P_Sgf[43]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_42_ ( .D(
FPMULT_Sgf_operation_Result[42]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8354391), .RN(n2710), .Q(
FPMULT_P_Sgf[42]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_39_ ( .D(
FPMULT_Sgf_operation_Result[39]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8354391), .RN(n917), .Q(
FPMULT_P_Sgf[39]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_36_ ( .D(
FPMULT_Sgf_operation_Result[36]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8354391), .RN(n2711), .Q(
FPMULT_P_Sgf[36]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_31_ ( .D(
FPMULT_Sgf_operation_Result[31]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8354391), .RN(n2715), .Q(
FPMULT_P_Sgf[31]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_29_ ( .D(
FPMULT_Sgf_operation_Result[29]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8354391), .RN(n2702), .Q(
FPMULT_P_Sgf[29]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_28_ ( .D(
FPMULT_Sgf_operation_Result[28]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8354391), .RN(n916), .Q(
FPMULT_P_Sgf[28]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_25_ ( .D(
FPMULT_Sgf_operation_Result[25]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8354391), .RN(n2715), .Q(
FPMULT_P_Sgf[25]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_30_ ( .D(Data_2[30]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2727), .Q(
FPMULT_Op_MY[30]) );
DFFSXLTS R_5 ( .D(n2670), .CK(FPMULT_Sgf_operation_EVEN1_finalreg_net8354391), .SN(n949), .Q(n2780) );
DFFSX1TS R_9 ( .D(n2669), .CK(clk), .SN(n917), .Q(n2775) );
DFFRX1TS R_17 ( .D(n2667), .CK(
FPMULT_Operands_load_reg_XMRegister_net8354427), .RN(n2727), .Q(n2777)
);
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_23_ ( .D(
FPSENCOS_first_mux_X[23]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2716), .Q(FPSENCOS_d_ff2_X[23]), .QN(n2620) );
ADDFX1TS intadd_1156_U9 ( .A(intadd_1156_A_0_), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[0]), .CI(
intadd_1156_CI), .CO(intadd_1156_n8), .S(intadd_1156_SUM_0_) );
ADDFX1TS intadd_1146_U12 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[2]), .B(
intadd_1146_B_0_), .CI(intadd_1146_CI), .CO(intadd_1146_n11), .S(
intadd_1146_SUM_0_) );
ADDFX1TS intadd_1143_U14 ( .A(FPMULT_Sgf_operation_Result[0]), .B(
intadd_1143_B_0_), .CI(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[0]), .CO(
intadd_1143_n13), .S(intadd_1143_SUM_0_) );
ADDFX1TS intadd_1145_U13 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[0]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[0]), .CI(
intadd_1145_CI), .CO(intadd_1145_n12), .S(intadd_1145_SUM_0_) );
ADDFX1TS intadd_1165_U4 ( .A(n2482), .B(FPSENCOS_d_ff2_Y[24]), .CI(
intadd_1165_CI), .CO(intadd_1165_n3), .S(FPSENCOS_sh_exp_y[1]) );
ADDFX1TS intadd_1143_U13 ( .A(FPMULT_Sgf_operation_Result[1]), .B(
intadd_1143_B_1_), .CI(intadd_1143_n13), .CO(intadd_1143_n12), .S(
intadd_1143_SUM_1_) );
ADDFX1TS DP_OP_234J326_132_4955_U10 ( .A(FPMULT_S_Oper_A_exp[0]), .B(
FPMULT_FSM_exp_operation_A_S), .CI(DP_OP_234J326_132_4955_n22), .CO(
DP_OP_234J326_132_4955_n9), .S(FPMULT_Exp_module_Data_S[0]) );
ADDFX1TS intadd_1142_U10 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[11]), .B(
intadd_1142_B_4_), .CI(intadd_1142_n10), .CO(intadd_1142_n9), .S(
FPMULT_Sgf_operation_Result[11]) );
ADDFX1TS intadd_1142_U9 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[0]), .B(
intadd_1142_B_5_), .CI(intadd_1142_n9), .CO(intadd_1142_n8), .S(
intadd_1142_SUM_5_) );
ADDFX1TS intadd_1148_U5 ( .A(FPMULT_Op_MY[7]), .B(FPMULT_Op_MY[19]), .CI(
intadd_1148_n5), .CO(intadd_1148_n4), .S(intadd_1148_SUM_6_) );
ADDFX1TS intadd_1139_U25 ( .A(intadd_1139_A_1_), .B(intadd_1139_B_1_), .CI(
intadd_1139_n25), .CO(intadd_1139_n24), .S(
FPMULT_Sgf_operation_Result[14]) );
ADDFX1TS intadd_1149_U10 ( .A(intadd_1149_A_0_), .B(intadd_1149_B_0_), .CI(
intadd_1149_CI), .CO(intadd_1149_n9), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N2) );
ADDFX1TS intadd_1141_U14 ( .A(intadd_1141_A_0_), .B(intadd_1141_B_0_), .CI(
intadd_1141_CI), .CO(intadd_1141_n13), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N2) );
ADDFX1TS intadd_1139_U15 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[0]), .B(
intadd_1139_B_11_), .CI(intadd_1139_n15), .CO(intadd_1139_n14), .S(
FPMULT_Sgf_operation_Result[24]) );
ADDFX1TS intadd_1139_U14 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[1]), .B(
intadd_1139_B_12_), .CI(intadd_1139_n14), .CO(intadd_1139_n13), .S(
FPMULT_Sgf_operation_Result[25]) );
ADDFX1TS intadd_1140_U2 ( .A(intadd_1140_A_16_), .B(intadd_1140_B_16_), .CI(
intadd_1140_n2), .CO(intadd_1140_n1), .S(intadd_1140_SUM_16_) );
ADDFX1TS intadd_1139_U13 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[2]), .B(
intadd_1139_B_13_), .CI(intadd_1139_n13), .CO(intadd_1139_n12), .S(
FPMULT_Sgf_operation_Result[26]) );
ADDFX1TS intadd_1139_U12 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[3]), .B(
intadd_1139_B_14_), .CI(intadd_1139_n12), .CO(intadd_1139_n11), .S(
FPMULT_Sgf_operation_Result[27]) );
ADDFX1TS intadd_1139_U10 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[5]), .B(
intadd_1139_B_16_), .CI(intadd_1139_n10), .CO(intadd_1139_n9), .S(
FPMULT_Sgf_operation_Result[29]) );
ADDFX1TS intadd_1139_U9 ( .A(intadd_1139_A_17_), .B(intadd_1139_B_17_), .CI(
intadd_1139_n9), .CO(intadd_1139_n8), .S(
FPMULT_Sgf_operation_Result[30]) );
ADDFX1TS intadd_1139_U8 ( .A(intadd_1139_A_18_), .B(intadd_1139_B_18_), .CI(
intadd_1139_n8), .CO(intadd_1139_n7), .S(
FPMULT_Sgf_operation_Result[31]) );
ADDFX1TS intadd_1139_U5 ( .A(intadd_1139_A_21_), .B(intadd_1139_B_21_), .CI(
intadd_1139_n5), .CO(intadd_1139_n4), .S(
FPMULT_Sgf_operation_Result[34]) );
ADDFX1TS intadd_1139_U4 ( .A(intadd_1139_A_22_), .B(intadd_1139_B_22_), .CI(
intadd_1139_n4), .CO(intadd_1139_n3), .S(
FPMULT_Sgf_operation_Result[35]) );
ADDFX1TS intadd_1139_U3 ( .A(intadd_1139_A_23_), .B(intadd_1139_B_23_), .CI(
intadd_1139_n3), .CO(intadd_1139_n2), .S(
FPMULT_Sgf_operation_Result[36]) );
ADDFX1TS intadd_1139_U2 ( .A(intadd_1139_A_24_), .B(intadd_1139_B_24_), .CI(
intadd_1139_n2), .CO(intadd_1139_n1), .S(
FPMULT_Sgf_operation_Result[37]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_28_ ( .D(
FPSENCOS_first_mux_X[28]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8354463), .RN(n2717), .Q(FPSENCOS_d_ff2_X[28]), .QN(n2658) );
DFFRXLTS R_20 ( .D(n2664), .CK(clk), .RN(n2700), .Q(n2773) );
CMPR32X2TS intadd_1148_U11 ( .A(n959), .B(FPMULT_Op_MY[1]), .C(
intadd_1148_CI), .CO(intadd_1148_n10), .S(intadd_1148_SUM_0_) );
CMPR32X2TS intadd_1158_U6 ( .A(FPMULT_Op_MY[7]), .B(FPMULT_Op_MY[1]), .C(
intadd_1158_CI), .CO(intadd_1158_n5), .S(intadd_1158_SUM_0_) );
CMPR32X2TS intadd_1163_U2 ( .A(FPMULT_Op_MX[16]), .B(FPMULT_Op_MX[22]), .C(
intadd_1163_n2), .CO(intadd_1163_n1), .S(intadd_1163_SUM_3_) );
CMPR32X2TS intadd_1162_U2 ( .A(FPMULT_Op_MY[16]), .B(FPMULT_Op_MY[22]), .C(
intadd_1162_n2), .CO(intadd_1162_n1), .S(intadd_1162_SUM_3_) );
CMPR32X2TS intadd_1139_U11 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[4]), .B(
intadd_1139_B_15_), .C(intadd_1139_n11), .CO(intadd_1139_n10), .S(
FPMULT_Sgf_operation_Result[28]) );
DFFRX4TS FPMULT_FS_Module_state_reg_reg_0_ ( .D(
FPMULT_FS_Module_state_next[0]), .CK(FPMULT_FS_Module_net8354445),
.RN(n2710), .Q(FPMULT_FS_Module_state_reg[0]) );
CMPR32X2TS intadd_1139_U7 ( .A(intadd_1139_A_19_), .B(intadd_1139_B_19_),
.C(intadd_1139_n7), .CO(intadd_1139_n6), .S(
FPMULT_Sgf_operation_Result[32]) );
DFFRX4TS FPSENCOS_ITER_CONT_temp_reg_2_ ( .D(FPSENCOS_ITER_CONT_N4), .CK(
FPSENCOS_ITER_CONT_net8354499), .RN(n949), .Q(
FPSENCOS_cont_iter_out[2]), .QN(n908) );
CMPR32X2TS intadd_1153_U6 ( .A(mult_x_312_n29), .B(mult_x_312_n23), .C(
intadd_1153_n6), .CO(intadd_1153_n5), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6) );
CMPR32X2TS intadd_1155_U6 ( .A(mult_x_310_n29), .B(mult_x_310_n23), .C(
intadd_1155_n6), .CO(intadd_1155_n5), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6) );
CMPR32X2TS intadd_1165_U3 ( .A(FPSENCOS_d_ff2_Y[25]), .B(n908), .C(
intadd_1165_n3), .CO(intadd_1165_n2), .S(FPSENCOS_sh_exp_y[2]) );
CMPR32X2TS intadd_1164_U2 ( .A(FPSENCOS_d_ff2_X[26]), .B(n2594), .C(
intadd_1164_n2), .CO(intadd_1164_n1), .S(FPSENCOS_sh_exp_x[3]) );
CMPR32X2TS intadd_1165_U2 ( .A(FPSENCOS_d_ff2_Y[26]), .B(n2594), .C(
intadd_1165_n2), .CO(intadd_1165_n1), .S(FPSENCOS_sh_exp_y[3]) );
CMPR32X2TS intadd_1166_U4 ( .A(n2646), .B(FPADDSUB_DMP_EXP_EWSW[24]), .C(
intadd_1166_CI), .CO(intadd_1166_n3), .S(
FPADDSUB_Shift_amount_EXP_EW[1]) );
CMPR32X2TS intadd_1157_U2 ( .A(mult_x_309_n14), .B(intadd_1157_B_6_), .C(
intadd_1157_n2), .CO(intadd_1157_n1), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9) );
CMPR32X2TS intadd_1154_U4 ( .A(mult_x_311_n17), .B(mult_x_311_n15), .C(
intadd_1154_n4), .CO(intadd_1154_n3), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8) );
CMPR32X2TS intadd_1166_U3 ( .A(n2661), .B(FPADDSUB_DMP_EXP_EWSW[25]), .C(
intadd_1166_n3), .CO(intadd_1166_n2), .S(
FPADDSUB_Shift_amount_EXP_EW[2]) );
CMPR32X2TS intadd_1166_U2 ( .A(n2660), .B(FPADDSUB_DMP_EXP_EWSW[26]), .C(
intadd_1166_n2), .CO(intadd_1166_n1), .S(
FPADDSUB_Shift_amount_EXP_EW[3]) );
CMPR32X2TS intadd_1153_U2 ( .A(intadd_1153_A_7_), .B(intadd_1153_B_7_), .C(
intadd_1153_n2), .CO(intadd_1153_n1), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10) );
CMPR32X2TS intadd_1155_U2 ( .A(intadd_1155_A_7_), .B(intadd_1155_B_7_), .C(
intadd_1155_n2), .CO(intadd_1155_n1), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10) );
CMPR32X2TS intadd_1154_U2 ( .A(intadd_1154_A_7_), .B(intadd_1154_B_7_), .C(
intadd_1154_n2), .CO(intadd_1154_n1), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10) );
CLKINVX6TS U1397 ( .A(rst), .Y(n2728) );
NAND2X4TS U1398 ( .A(n921), .B(n1358), .Y(n1359) );
NAND2X4TS U1399 ( .A(n2330), .B(n2353), .Y(n1083) );
AOI211X2TS U1400 ( .A0(FPADDSUB_Data_array_SWR[41]), .A1(n1139), .B0(n1165),
.C0(n1155), .Y(n1271) );
AOI211X2TS U1401 ( .A0(FPADDSUB_Data_array_SWR[42]), .A1(n1139), .B0(n1165),
.C0(n1141), .Y(n1207) );
INVX3TS U1402 ( .A(n1360), .Y(n969) );
CMPR32X2TS U1403 ( .A(n1936), .B(n1505), .C(n1959), .CO(n1501), .S(n1506) );
NAND2X4TS U1404 ( .A(FPADDSUB_ADD_OVRFLW_NRM), .B(n2674), .Y(n1360) );
NOR2XLTS U1405 ( .A(n1099), .B(n1839), .Y(n1842) );
NOR2X8TS U1406 ( .A(enab_cont_iter), .B(rst), .Y(n910) );
INVX1TS U1407 ( .A(n1672), .Y(n1673) );
OAI21X1TS U1408 ( .A0(n1663), .A1(n1599), .B0(DP_OP_499J326_125_1651_n32),
.Y(n1598) );
NOR2X1TS U1409 ( .A(n1575), .B(n2769), .Y(n1101) );
ADDFX1TS U1410 ( .A(n1904), .B(n1903), .CI(n1902), .CO(
DP_OP_501J326_127_5235_n31), .S(DP_OP_501J326_127_5235_n32) );
OAI21X1TS U1411 ( .A0(n1097), .A1(n1519), .B0(n1521), .Y(n1096) );
NAND2X4TS U1412 ( .A(n1358), .B(n962), .Y(n1357) );
NAND2X6TS U1413 ( .A(n2289), .B(n921), .Y(n1364) );
BUFX6TS U1414 ( .A(n2284), .Y(n2278) );
CLKINVX6TS U1415 ( .A(n2284), .Y(n911) );
CLKINVX3TS U1416 ( .A(n1860), .Y(n1478) );
BUFX6TS U1417 ( .A(n2677), .Y(n2687) );
BUFX6TS U1418 ( .A(n910), .Y(n2689) );
BUFX6TS U1419 ( .A(n910), .Y(n2695) );
BUFX6TS U1420 ( .A(n910), .Y(n2682) );
BUFX6TS U1421 ( .A(n1105), .Y(n912) );
BUFX6TS U1422 ( .A(n910), .Y(n913) );
BUFX4TS U1423 ( .A(n2300), .Y(n914) );
INVX4TS U1424 ( .A(n1527), .Y(n1456) );
NOR2X4TS U1425 ( .A(n1300), .B(n1170), .Y(n1171) );
AND2X4TS U1426 ( .A(n2306), .B(n1391), .Y(n1103) );
NAND2X4TS U1427 ( .A(n1300), .B(n1293), .Y(n1140) );
CLKINVX3TS U1428 ( .A(n1198), .Y(n1144) );
NAND2X4TS U1429 ( .A(n1305), .B(n1293), .Y(n1169) );
NOR2X6TS U1430 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(n1189), .Y(n1143)
);
NAND2X4TS U1431 ( .A(n2645), .B(n2152), .Y(n1245) );
NOR2X6TS U1432 ( .A(n2330), .B(n2316), .Y(n2323) );
BUFX6TS U1433 ( .A(n1102), .Y(n2711) );
BUFX6TS U1434 ( .A(n2705), .Y(n916) );
NOR2X6TS U1435 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_shift_value_SHT2_EWR[2]), .Y(n1139) );
ADDFX1TS U1436 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[3]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[3]), .CI(
n1830), .CO(intadd_1145_A_4_), .S(intadd_1145_B_3_) );
ADDFX1TS U1437 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[1]), .B(n2734), .CI(n1242), .CO(n1651), .S(n1654) );
CLKBUFX2TS U1438 ( .A(FPADDSUB_Raw_mant_NRM_SWR[1]), .Y(n956) );
ADDFX1TS U1439 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[2]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[2]), .CI(
n1829), .CO(intadd_1145_A_3_), .S(intadd_1145_B_2_) );
BUFX6TS U1440 ( .A(n1102), .Y(n917) );
BUFX4TS U1441 ( .A(n2370), .Y(n2330) );
BUFX6TS U1442 ( .A(n2704), .Y(n918) );
ADDFX1TS U1443 ( .A(n2758), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[5]), .CI(
n2757), .CO(n1585), .S(n1582) );
ADDFX1TS U1444 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[9]), .B(
n2765), .CI(n2770), .CO(n1593), .S(n1590) );
ADDFX1TS U1445 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[10]), .B(
n2729), .CI(n2745), .CO(intadd_1146_A_9_), .S(intadd_1146_A_8_) );
ADDFX1TS U1446 ( .A(n2752), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[2]), .CI(
n2751), .CO(n1579), .S(n1577) );
ADDFX1TS U1447 ( .A(n2756), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[4]), .CI(
n2755), .CO(n1583), .S(n1580) );
ADDFX1TS U1448 ( .A(n2754), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[3]), .CI(
n2753), .CO(n1581), .S(n1578) );
ADDFX1TS U1449 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[0]), .B(n2744), .CI(intadd_1156_CI), .CO(n1242), .S(n1633) );
ADDFX1TS U1450 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[3]), .B(n2735), .CI(n2748), .CO(intadd_1146_B_2_), .S(intadd_1146_B_1_) );
ADDFX1TS U1451 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[4]), .B(n2733), .CI(n2749), .CO(intadd_1146_B_3_), .S(intadd_1146_A_2_) );
ADDFX1TS U1452 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[5]), .B(n2732), .CI(n2750), .CO(intadd_1146_A_4_), .S(intadd_1146_A_3_) );
ADDFX1TS U1453 ( .A(n2752), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[2]), .CI(
intadd_1146_CI), .CO(intadd_1156_A_3_), .S(intadd_1156_B_2_) );
ADDFX1TS U1454 ( .A(n2754), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[3]), .CI(
n2748), .CO(intadd_1156_A_4_), .S(intadd_1156_B_3_) );
ADDFX1TS U1455 ( .A(n2756), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[4]), .CI(
n2749), .CO(intadd_1156_A_5_), .S(intadd_1156_B_4_) );
ADDFX1TS U1456 ( .A(n2758), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[5]), .CI(
n2750), .CO(intadd_1156_A_6_), .S(intadd_1156_B_5_) );
BUFX6TS U1457 ( .A(n2728), .Y(n2717) );
CLKINVX6TS U1458 ( .A(operation[1]), .Y(n2370) );
BUFX6TS U1459 ( .A(n2728), .Y(n919) );
NAND2BXLTS U1460 ( .AN(FPADDSUB_intDX_EWSW[19]), .B(FPADDSUB_intDY_EWSW[19]),
.Y(n2044) );
NAND2BXLTS U1461 ( .AN(FPADDSUB_intDX_EWSW[27]), .B(FPADDSUB_intDY_EWSW[27]),
.Y(n1998) );
OAI21XLTS U1462 ( .A0(n1654), .A1(n2743), .B0(n1651), .Y(n1653) );
AO21XLTS U1463 ( .A0(n1100), .A1(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[15]), .B0(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[16]), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[15]) );
AO21XLTS U1464 ( .A0(n1841), .A1(n1840), .B0(n1839), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[13]) );
OAI32X1TS U1465 ( .A0(n1127), .A1(n2496), .A2(n2473), .B0(n1126), .B1(n1127),
.Y(n1128) );
NAND3XLTS U1466 ( .A(intadd_1159_SUM_4_), .B(intadd_1160_SUM_1_), .C(n1047),
.Y(n1235) );
CLKINVX3TS U1467 ( .A(intadd_1163_SUM_2_), .Y(n1871) );
NAND2BXLTS U1468 ( .AN(n957), .B(FPADDSUB_intDY_EWSW[24]), .Y(n2054) );
AOI222X1TS U1469 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[6]), .A1(
FPADDSUB_DMP_SFG[4]), .B0(FPADDSUB_DmP_mant_SFG_SWR[6]), .B1(n2193),
.C0(FPADDSUB_DMP_SFG[4]), .C1(n2193), .Y(n2198) );
NAND2BXLTS U1470 ( .AN(n1752), .B(n1751), .Y(mult_x_311_n19) );
AOI222X1TS U1471 ( .A0(FPADDSUB_DMP_SFG[10]), .A1(n2531), .B0(
FPADDSUB_DMP_SFG[10]), .B1(n2219), .C0(n2531), .C1(n2219), .Y(n2223)
);
AOI222X4TS U1472 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[4]), .A1(
FPADDSUB_DMP_SFG[2]), .B0(FPADDSUB_DmP_mant_SFG_SWR[4]), .B1(n2184),
.C0(FPADDSUB_DMP_SFG[2]), .C1(n2184), .Y(n2187) );
AOI222X4TS U1473 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[17]), .A1(n2244), .B0(
FPADDSUB_DmP_mant_SFG_SWR[17]), .B1(n2537), .C0(n2244), .C1(n2537),
.Y(n2249) );
NAND2BXLTS U1474 ( .AN(n1771), .B(n1770), .Y(mult_x_312_n19) );
NAND2BXLTS U1475 ( .AN(n1734), .B(n1733), .Y(mult_x_310_n19) );
OAI31X1TS U1476 ( .A0(n2472), .A1(n2473), .A2(n1738), .B0(n1737), .Y(
mult_x_310_n31) );
AOI211X1TS U1477 ( .A0(n1143), .A1(FPADDSUB_Data_array_SWR[39]), .B0(n1200),
.C0(n1177), .Y(n1184) );
AOI211X1TS U1478 ( .A0(n1290), .A1(FPADDSUB_Data_array_SWR[44]), .B0(n1200),
.C0(n1164), .Y(n1167) );
AOI211X1TS U1479 ( .A0(n1143), .A1(FPADDSUB_Data_array_SWR[41]), .B0(n1200),
.C0(n1195), .Y(n1201) );
AOI211X1TS U1480 ( .A0(n1143), .A1(FPADDSUB_Data_array_SWR[42]), .B0(n1200),
.C0(n1199), .Y(n1202) );
AOI222X1TS U1481 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[3]), .A1(n2178), .B0(
FPADDSUB_DmP_mant_SFG_SWR[3]), .B1(n2522), .C0(n2178), .C1(n2522), .Y(
n2183) );
AOI222X4TS U1482 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[15]), .A1(n2234), .B0(
FPADDSUB_DmP_mant_SFG_SWR[15]), .B1(n2535), .C0(n2234), .C1(n2535),
.Y(n2238) );
AO21XLTS U1483 ( .A0(n1139), .A1(FPADDSUB_Data_array_SWR[50]), .B0(n1187),
.Y(n933) );
AOI222X1TS U1484 ( .A0(FPADDSUB_DMP_SFG[9]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[11]), .B0(FPADDSUB_DMP_SFG[9]), .B1(n2213),
.C0(FPADDSUB_DmP_mant_SFG_SWR[11]), .C1(n2213), .Y(n2218) );
AOI2BB2XLTS U1485 ( .B0(n2311), .B1(n1571), .A0N(n1083), .A1N(n930), .Y(
n1525) );
NOR3BXLTS U1486 ( .AN(n2306), .B(FPMULT_FS_Module_state_reg[2]), .C(n2305),
.Y(FPMULT_FSM_first_phase_load) );
NAND2BXLTS U1487 ( .AN(n2792), .B(n2439), .Y(n873) );
INVX2TS U1488 ( .A(enab_cont_iter), .Y(n1276) );
AOI211X1TS U1489 ( .A0(n2550), .A1(n2469), .B0(n2487), .C0(n1725), .Y(
intadd_1157_B_1_) );
OAI31X1TS U1490 ( .A0(enab_cont_iter), .A1(n2437), .A2(ready_add_subt), .B0(
n2675), .Y(n2438) );
NAND2BXLTS U1491 ( .AN(intadd_1150_B_0_), .B(n1794), .Y(n1795) );
AO22XLTS U1492 ( .A0(n911), .A1(FPADDSUB_intDX_EWSW[28]), .B0(n2280), .B1(
FPADDSUB_intDY_EWSW[28]), .Y(FPADDSUB_DMP_INIT_EWSW[28]) );
OAI31X1TS U1493 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(
FPSENCOS_cont_iter_out[1]), .A2(n908), .B0(n1246), .Y(n854) );
OA22X1TS U1494 ( .A0(n2674), .A1(FPADDSUB_Shift_amount_SHT1_EWR[0]), .B0(
FPADDSUB_LZD_raw_out_EWR[0]), .B1(n1397), .Y(n921) );
BUFX4TS U1495 ( .A(FPADDSUB_OP_FLAG_SFG), .Y(n2269) );
OR2X1TS U1496 ( .A(n1524), .B(n943), .Y(n924) );
NOR2X2TS U1497 ( .A(n1654), .B(n2743), .Y(n928) );
NOR2X1TS U1498 ( .A(n1901), .B(n1906), .Y(n929) );
NOR2X2TS U1499 ( .A(n2594), .B(n1262), .Y(n936) );
OR2X1TS U1500 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .Y(n942) );
OAI221X1TS U1501 ( .A0(n2511), .A1(FPADDSUB_intDY_EWSW[20]), .B0(n2615),
.B1(FPADDSUB_intDY_EWSW[30]), .C0(n2066), .Y(n2069) );
OAI221X1TS U1502 ( .A0(n2512), .A1(FPADDSUB_intDY_EWSW[23]), .B0(n2616),
.B1(FPADDSUB_intDY_EWSW[29]), .C0(n2074), .Y(n2077) );
CLKINVX6TS U1503 ( .A(n1103), .Y(n2727) );
OAI221X1TS U1504 ( .A0(n926), .A1(FPADDSUB_intDY_EWSW[26]), .B0(n938), .B1(
FPADDSUB_intDY_EWSW[25]), .C0(n2072), .Y(n2079) );
OAI21X1TS U1505 ( .A0(n1189), .A1(n1197), .B0(n1188), .Y(n1150) );
INVX1TS U1506 ( .A(FPADDSUB_Data_array_SWR[50]), .Y(n1197) );
OAI21X1TS U1507 ( .A0(n1189), .A1(n2617), .B0(n1188), .Y(n1159) );
OAI21X1TS U1508 ( .A0(n1189), .A1(n2619), .B0(n1188), .Y(n1190) );
NOR2X1TS U1509 ( .A(n1924), .B(n1630), .Y(DP_OP_501J326_127_5235_n181) );
NAND2X2TS U1510 ( .A(intadd_1160_n1), .B(intadd_1147_SUM_5_), .Y(n1630) );
NOR3X1TS U1511 ( .A(enab_cont_iter), .B(n2437), .C(ready_add_subt), .Y(n2436) );
OAI2BB2X1TS U1512 ( .B0(n1878), .B1(n1877), .A0N(n1876), .A1N(n1875), .Y(
DP_OP_500J326_126_4510_n70) );
INVX2TS U1513 ( .A(FPMULT_Op_MX[0]), .Y(n946) );
NOR2X1TS U1514 ( .A(n2473), .B(n2551), .Y(mult_x_310_n77) );
CLKINVX6TS U1515 ( .A(n1103), .Y(n2721) );
OAI31X1TS U1516 ( .A0(n1988), .A1(n1620), .A2(n1990), .B0(n1619), .Y(
FPADDSUB_Raw_mant_SGF[24]) );
NOR2X2TS U1517 ( .A(n2514), .B(n2618), .Y(n1988) );
NOR2X4TS U1518 ( .A(n2503), .B(n2482), .Y(n2435) );
NOR4X4TS U1519 ( .A(n1906), .B(n1450), .C(n1907), .D(n1627), .Y(n1908) );
NOR2X1TS U1520 ( .A(n2487), .B(n2548), .Y(mult_x_309_n76) );
NOR4X1TS U1521 ( .A(FPMULT_Sgf_operation_Result[7]), .B(
FPMULT_Sgf_operation_Result[9]), .C(FPMULT_Sgf_operation_Result[11]),
.D(n1656), .Y(n2671) );
NOR3X1TS U1522 ( .A(FPMULT_FS_Module_state_reg[0]), .B(
FPMULT_FSM_add_overflow_flag), .C(n2593), .Y(n1248) );
OAI31X1TS U1523 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[7]), .A1(n2597), .A2(n1041),
.B0(n1040), .Y(FPADDSUB_LZD_raw_out_EWR[0]) );
NOR2X2TS U1524 ( .A(n1704), .B(n1708), .Y(n1703) );
NOR2X2TS U1525 ( .A(n1701), .B(n1702), .Y(n1700) );
NOR2X2TS U1526 ( .A(n1698), .B(n1699), .Y(n1697) );
NOR2X2TS U1527 ( .A(n1695), .B(n1696), .Y(n1694) );
NOR2X2TS U1528 ( .A(n1692), .B(n1693), .Y(n1691) );
NOR2X2TS U1529 ( .A(n1689), .B(n1690), .Y(n1688) );
NOR2X2TS U1530 ( .A(n1686), .B(n1687), .Y(n1685) );
NOR2X2TS U1531 ( .A(n1683), .B(n1684), .Y(n1682) );
NOR2X2TS U1532 ( .A(n1680), .B(n1681), .Y(n1679) );
BUFX4TS U1533 ( .A(n2698), .Y(n2706) );
BUFX3TS U1534 ( .A(n2707), .Y(n1102) );
BUFX4TS U1535 ( .A(n2707), .Y(n2704) );
BUFX4TS U1536 ( .A(n2728), .Y(n2703) );
BUFX4TS U1537 ( .A(n918), .Y(n2702) );
INVX4TS U1538 ( .A(rst), .Y(n947) );
CLKBUFX2TS U1539 ( .A(n917), .Y(n2698) );
BUFX4TS U1540 ( .A(n2716), .Y(n2708) );
BUFX4TS U1541 ( .A(n2716), .Y(n2712) );
BUFX4TS U1542 ( .A(n2728), .Y(n2707) );
AOI32X1TS U1543 ( .A0(n1891), .A1(intadd_1148_SUM_8_), .A2(
intadd_1147_SUM_6_), .B0(n1460), .B1(n1891), .Y(n1461) );
NOR2X2TS U1544 ( .A(n1896), .B(n1462), .Y(n1460) );
BUFX4TS U1545 ( .A(n2711), .Y(n2715) );
BUFX4TS U1546 ( .A(n2686), .Y(n2697) );
BUFX4TS U1547 ( .A(n2700), .Y(n2709) );
NOR2X2TS U1548 ( .A(n1924), .B(n1535), .Y(n1926) );
NOR2X2TS U1549 ( .A(FPMULT_FS_Module_state_reg[0]), .B(
FPMULT_FS_Module_state_reg[2]), .Y(n1391) );
NOR2X2TS U1550 ( .A(n1332), .B(n1331), .Y(n1946) );
INVX2TS U1551 ( .A(n933), .Y(n948) );
NOR2X2TS U1552 ( .A(n1629), .B(n1917), .Y(DP_OP_501J326_127_5235_n227) );
NOR2X2TS U1553 ( .A(n2488), .B(n2542), .Y(intadd_1154_A_7_) );
NOR2X2TS U1554 ( .A(n2547), .B(n2495), .Y(intadd_1153_A_7_) );
NOR2X2TS U1555 ( .A(n2546), .B(n2496), .Y(intadd_1155_A_7_) );
OAI21XLTS U1556 ( .A0(n1988), .A1(n1990), .B0(n1620), .Y(n1619) );
NOR2X2TS U1557 ( .A(FPADDSUB_DMP_SFG[22]), .B(FPADDSUB_DmP_mant_SFG_SWR[24]),
.Y(n1990) );
AOI21X2TS U1558 ( .A0(n1139), .A1(FPADDSUB_Data_array_SWR[49]), .B0(n1187),
.Y(n1268) );
NOR2X2TS U1559 ( .A(n1705), .B(n1706), .Y(n1709) );
INVX4TS U1560 ( .A(rst), .Y(n949) );
INVX2TS U1561 ( .A(n920), .Y(n950) );
AOI21X2TS U1562 ( .A0(n1139), .A1(FPADDSUB_Data_array_SWR[47]), .B0(n1187),
.Y(n1287) );
AOI21X2TS U1563 ( .A0(n1139), .A1(FPADDSUB_Data_array_SWR[48]), .B0(n1187),
.Y(n1294) );
NOR2X2TS U1564 ( .A(n2491), .B(n2552), .Y(mult_x_311_n53) );
NOR3XLTS U1565 ( .A(n2440), .B(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]),
.C(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n1084) );
OAI22X2TS U1566 ( .A0(n2313), .A1(n2370), .B0(n1457), .B1(n1083), .Y(n2440)
);
AOI211XLTS U1567 ( .A0(FPADDSUB_intDY_EWSW[16]), .A1(n2623), .B0(n2047),
.C0(n2048), .Y(n2039) );
OAI211X2TS U1568 ( .A0(FPADDSUB_intDX_EWSW[20]), .A1(n2642), .B0(n2053),
.C0(n2038), .Y(n2047) );
NOR2X2TS U1569 ( .A(n2492), .B(n2549), .Y(mult_x_309_n66) );
NOR2X2TS U1570 ( .A(n1226), .B(n1462), .Y(DP_OP_501J326_127_5235_n71) );
NAND3X4TS U1571 ( .A(FPMULT_Op_MX[11]), .B(FPMULT_Op_MX[5]), .C(
intadd_1161_n1), .Y(n1972) );
OAI22X2TS U1572 ( .A0(n1611), .A1(n1610), .B0(n2269), .B1(n1609), .Y(n1615)
);
NOR2X2TS U1573 ( .A(n1901), .B(n1627), .Y(n1228) );
NOR2X4TS U1574 ( .A(FPMULT_Op_MY[11]), .B(intadd_1148_n1), .Y(n1901) );
NOR2X2TS U1575 ( .A(n1896), .B(n1906), .Y(DP_OP_501J326_127_5235_n62) );
AOI21X4TS U1576 ( .A0(n1740), .A1(n1762), .B0(intadd_1158_CI), .Y(n2449) );
NOR2X2TS U1577 ( .A(n1740), .B(n1762), .Y(intadd_1158_CI) );
NOR2X2TS U1578 ( .A(n1747), .B(n1761), .Y(mult_x_311_n38) );
NOR2X2TS U1579 ( .A(n1769), .B(n1781), .Y(mult_x_312_n38) );
CLKINVX3TS U1580 ( .A(FPADDSUB_ADD_OVRFLW_NRM2), .Y(n951) );
INVX2TS U1581 ( .A(n1091), .Y(n952) );
INVX2TS U1582 ( .A(n952), .Y(n953) );
XOR2X1TS U1583 ( .A(FPMULT_Op_MX[11]), .B(n1086), .Y(n1091) );
CLKINVX6TS U1584 ( .A(n1103), .Y(n2724) );
CLKINVX6TS U1585 ( .A(n1103), .Y(n2722) );
CLKINVX6TS U1586 ( .A(n1103), .Y(n2723) );
CLKINVX6TS U1587 ( .A(n1103), .Y(n2726) );
CLKINVX6TS U1588 ( .A(n1305), .Y(n1300) );
BUFX6TS U1589 ( .A(FPADDSUB_left_right_SHT2), .Y(n1305) );
BUFX6TS U1590 ( .A(n1362), .Y(n2287) );
BUFX4TS U1591 ( .A(n910), .Y(n2685) );
BUFX4TS U1592 ( .A(n910), .Y(n2686) );
BUFX4TS U1593 ( .A(n910), .Y(n2678) );
BUFX4TS U1594 ( .A(n910), .Y(n2681) );
INVX2TS U1595 ( .A(n923), .Y(n954) );
BUFX6TS U1596 ( .A(n2396), .Y(n2419) );
NOR3X1TS U1597 ( .A(n1777), .B(n2471), .C(n1776), .Y(n1775) );
OAI32X1TS U1598 ( .A0(n1771), .A1(n2471), .A2(n2476), .B0(n1776), .B1(n1771),
.Y(n1135) );
NAND2X2TS U1599 ( .A(FPMULT_Op_MY[17]), .B(FPMULT_Op_MX[14]), .Y(n1776) );
OAI32X1TS U1600 ( .A0(n1752), .A1(n2470), .A2(n2491), .B0(n1757), .B1(n1752),
.Y(n1137) );
NAND2X2TS U1601 ( .A(FPMULT_Op_MY[11]), .B(FPMULT_Op_MX[8]), .Y(n1757) );
OAI32X1TS U1602 ( .A0(n1734), .A1(n2472), .A2(n2475), .B0(n1738), .B1(n1734),
.Y(n1133) );
NAND2X2TS U1603 ( .A(FPMULT_Op_MX[2]), .B(FPMULT_Op_MY[5]), .Y(n1738) );
NAND3X2TS U1604 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_shift_value_SHT2_EWR[2]), .C(n1293), .Y(n1198) );
NOR4BX2TS U1605 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .D(n1524), .Y(n2311) );
NOR4BX2TS U1606 ( .AN(n1452), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]),
.C(n967), .D(n1076), .Y(FPSENCOS_enab_RB3) );
INVX2TS U1607 ( .A(n944), .Y(n955) );
NAND2X4TS U1608 ( .A(FPMULT_Op_MX[17]), .B(intadd_1163_n1), .Y(n1851) );
NOR4X2TS U1609 ( .A(n2495), .B(n2541), .C(n2476), .D(n2471), .Y(n1771) );
NOR4X2TS U1610 ( .A(n2540), .B(n2475), .C(n2472), .D(n2496), .Y(n1734) );
NOR2X2TS U1611 ( .A(FPMULT_FS_Module_state_reg[3]), .B(n2307), .Y(n2790) );
INVX2TS U1612 ( .A(n932), .Y(n957) );
INVX2TS U1613 ( .A(n941), .Y(n958) );
BUFX4TS U1614 ( .A(n914), .Y(n2296) );
OAI21XLTS U1615 ( .A0(FPMULT_Sgf_operation_EVEN1_Q_left[1]), .A1(n2747),
.B0(intadd_1156_A_2_), .Y(intadd_1156_B_1_) );
NOR4BX2TS U1616 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .D(n1524), .Y(n2319) );
CLKINVX3TS U1617 ( .A(n2490), .Y(n959) );
INVX2TS U1618 ( .A(n925), .Y(n960) );
NOR4X2TS U1619 ( .A(n1762), .B(n2477), .C(n2493), .D(n2538), .Y(
mult_x_311_n42) );
CLKINVX3TS U1620 ( .A(FPMULT_Op_MY[6]), .Y(n1762) );
BUFX6TS U1621 ( .A(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(n2674) );
AOI21X2TS U1622 ( .A0(n969), .A1(n2543), .B0(n1373), .Y(n1429) );
OAI21X2TS U1623 ( .A0(n2544), .A1(n1360), .B0(n1370), .Y(n1414) );
BUFX4TS U1624 ( .A(n2683), .Y(n2684) );
BUFX4TS U1625 ( .A(n2693), .Y(n2696) );
BUFX4TS U1626 ( .A(n2678), .Y(n2694) );
BUFX4TS U1627 ( .A(n2688), .Y(n2690) );
BUFX6TS U1628 ( .A(n910), .Y(n1105) );
INVX2TS U1629 ( .A(n937), .Y(n961) );
NOR4X1TS U1630 ( .A(FPMULT_Op_MY[12]), .B(n959), .C(FPMULT_Op_MY[14]), .D(
FPMULT_Op_MY[15]), .Y(n2454) );
BUFX6TS U1631 ( .A(n2370), .Y(n2406) );
INVX2TS U1632 ( .A(n921), .Y(n962) );
INVX4TS U1633 ( .A(n914), .Y(n2293) );
BUFX4TS U1634 ( .A(n1142), .Y(n1290) );
BUFX6TS U1635 ( .A(n2101), .Y(n2146) );
BUFX6TS U1636 ( .A(n2103), .Y(n2147) );
CLKINVX6TS U1637 ( .A(n914), .Y(n2299) );
INVX6TS U1638 ( .A(n914), .Y(n2294) );
CLKINVX6TS U1639 ( .A(n914), .Y(n2297) );
INVX4TS U1640 ( .A(n2303), .Y(n2304) );
CLKINVX6TS U1641 ( .A(n2274), .Y(n2303) );
INVX3TS U1642 ( .A(n2278), .Y(n2283) );
INVX3TS U1643 ( .A(n2278), .Y(n2277) );
BUFX4TS U1644 ( .A(n2281), .Y(n2284) );
BUFX6TS U1645 ( .A(n1251), .Y(n2148) );
INVX4TS U1646 ( .A(FPADDSUB_OP_FLAG_SFG), .Y(n963) );
NOR2X1TS U1647 ( .A(FPADDSUB_Raw_mant_NRM_SWR[2]), .B(
FPADDSUB_Raw_mant_NRM_SWR[3]), .Y(n1216) );
INVX2TS U1648 ( .A(n940), .Y(n964) );
INVX2TS U1649 ( .A(n931), .Y(n965) );
AOI222X4TS U1650 ( .A0(n2462), .A1(FPADDSUB_DmP_mant_SHT1_SW[0]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[2]), .B1(n969), .C0(
FPADDSUB_Raw_mant_NRM_SWR[23]), .C1(n2673), .Y(n1422) );
AOI211X1TS U1651 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[0]), .A1(n2557), .B0(
FPADDSUB_Raw_mant_NRM_SWR[2]), .C0(FPADDSUB_Raw_mant_NRM_SWR[4]), .Y(
n1033) );
NOR3X1TS U1652 ( .A(FPADDSUB_Raw_mant_NRM_SWR[19]), .B(
FPADDSUB_Raw_mant_NRM_SWR[20]), .C(FPADDSUB_Raw_mant_NRM_SWR[21]), .Y(
n1316) );
AOI211X1TS U1653 ( .A0(n1022), .A1(FPADDSUB_Raw_mant_NRM_SWR[19]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[22]), .C0(FPADDSUB_Raw_mant_NRM_SWR[23]),
.Y(n1025) );
AOI21X2TS U1654 ( .A0(n1139), .A1(FPADDSUB_Data_array_SWR[44]), .B0(n1190),
.Y(n1302) );
AOI21X2TS U1655 ( .A0(n1139), .A1(FPADDSUB_Data_array_SWR[43]), .B0(n1159),
.Y(n1307) );
OAI31X1TS U1656 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[5]), .A1(
FPADDSUB_Raw_mant_NRM_SWR[9]), .A2(FPADDSUB_Raw_mant_NRM_SWR[8]), .B0(
n1215), .Y(n1220) );
NOR4BBX1TS U1657 ( .AN(n1028), .BN(FPADDSUB_Raw_mant_NRM_SWR[8]), .C(
FPADDSUB_Raw_mant_NRM_SWR[9]), .D(n1029), .Y(n1038) );
OAI221X1TS U1658 ( .A0(n2510), .A1(FPADDSUB_intDY_EWSW[6]), .B0(n2610), .B1(
FPADDSUB_intDY_EWSW[3]), .C0(n2080), .Y(n2095) );
NOR4X2TS U1659 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .Y(n1451) );
NOR2X1TS U1660 ( .A(n2484), .B(n2552), .Y(mult_x_311_n77) );
NAND2X2TS U1661 ( .A(FPMULT_Op_MX[19]), .B(FPMULT_Op_MY[20]), .Y(n1725) );
INVX1TS U1662 ( .A(n1866), .Y(n1868) );
NOR4X1TS U1663 ( .A(FPMULT_Sgf_operation_Result[2]), .B(
FPMULT_Sgf_operation_Result[10]), .C(n968), .D(
FPMULT_Sgf_operation_Result[14]), .Y(n2670) );
NOR4X1TS U1664 ( .A(Data_2[2]), .B(Data_2[10]), .C(Data_2[12]), .D(
Data_2[14]), .Y(n2669) );
NOR4X1TS U1665 ( .A(Data_2[7]), .B(Data_2[9]), .C(Data_2[11]), .D(Data_2[6]),
.Y(n2668) );
NOR4X1TS U1666 ( .A(Data_2[17]), .B(Data_2[16]), .C(Data_2[8]), .D(n974),
.Y(n2665) );
NOR3X6TS U1667 ( .A(n1045), .B(FPADDSUB_exp_rslt_NRM2_EW1[7]), .C(n1016),
.Y(n2783) );
XNOR2X2TS U1668 ( .A(DP_OP_26J326_129_1325_n1), .B(FPADDSUB_ADD_OVRFLW_NRM2),
.Y(n1045) );
NOR2X2TS U1669 ( .A(DP_OP_499J326_125_1651_n121), .B(n1668), .Y(n1667) );
BUFX4TS U1670 ( .A(n2728), .Y(n2716) );
OAI33X1TS U1671 ( .A0(FPSENCOS_d_ff1_shift_region_flag_out[0]), .A1(n2483),
.A2(n2644), .B0(n2520), .B1(FPSENCOS_d_ff1_shift_region_flag_out[1]),
.B2(FPSENCOS_d_ff1_operation_out), .Y(n2276) );
NOR2X2TS U1672 ( .A(n1188), .B(n2599), .Y(n1165) );
NOR2X2TS U1673 ( .A(FPADDSUB_N60), .B(FPADDSUB_N59), .Y(n1347) );
NOR2X2TS U1674 ( .A(n1880), .B(n1852), .Y(n1280) );
NOR2X2TS U1675 ( .A(n1964), .B(n1965), .Y(n1963) );
NOR2X2TS U1676 ( .A(n1805), .B(n1788), .Y(intadd_1150_B_0_) );
OAI21X2TS U1677 ( .A0(intadd_1147_SUM_2_), .A1(intadd_1147_SUM_3_), .B0(
n1093), .Y(n1788) );
NOR2X2TS U1678 ( .A(intadd_1140_n1), .B(n1597), .Y(n1663) );
AOI21X2TS U1679 ( .A0(n1139), .A1(FPADDSUB_Data_array_SWR[45]), .B0(n1149),
.Y(n1283) );
OAI21X1TS U1680 ( .A0(n1189), .A1(n2516), .B0(n1188), .Y(n1149) );
NOR2X2TS U1681 ( .A(n2475), .B(n2551), .Y(mult_x_310_n53) );
NOR2X2TS U1682 ( .A(n2476), .B(n2553), .Y(mult_x_312_n53) );
NOR2X2TS U1683 ( .A(n2501), .B(n2548), .Y(mult_x_309_n52) );
OAI211X2TS U1684 ( .A0(FPADDSUB_intDX_EWSW[12]), .A1(n2601), .B0(n2033),
.C0(n2019), .Y(n2035) );
AOI21X2TS U1685 ( .A0(intadd_1161_SUM_2_), .A1(intadd_1161_SUM_3_), .B0(n952), .Y(n1936) );
NOR2X2TS U1686 ( .A(n1535), .B(n1919), .Y(DP_OP_501J326_127_5235_n209) );
NOR2BX2TS U1687 ( .AN(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N0), .B(n1528), .Y(intadd_1141_A_0_) );
OAI2BB2X1TS U1688 ( .B0(n1985), .B1(n1984), .A0N(n1983), .A1N(n1982), .Y(
DP_OP_502J326_128_4510_n70) );
OAI21X4TS U1689 ( .A0(DP_OP_502J326_128_4510_n32), .A1(intadd_1161_SUM_1_),
.B0(n1328), .Y(n1984) );
AOI21X4TS U1690 ( .A0(intadd_1147_n1), .A1(FPMULT_Op_MX[11]), .B0(n1899),
.Y(n1631) );
NOR2X2TS U1691 ( .A(n1899), .B(n1450), .Y(DP_OP_501J326_127_5235_n48) );
NOR2X4TS U1692 ( .A(FPMULT_Op_MX[11]), .B(intadd_1147_n1), .Y(n1899) );
NOR2X2TS U1693 ( .A(n1731), .B(n1739), .Y(mult_x_310_n38) );
CLKINVX3TS U1694 ( .A(n1635), .Y(FPMULT_FSM_exp_operation_A_S) );
NOR2BX2TS U1695 ( .AN(n1132), .B(n1715), .Y(mult_x_309_n38) );
NAND4X2TS U1696 ( .A(intadd_1147_SUM_6_), .B(intadd_1148_SUM_7_), .C(
intadd_1148_SUM_8_), .D(intadd_1147_SUM_7_), .Y(n1891) );
NOR3X2TS U1697 ( .A(n2675), .B(n930), .C(n2506), .Y(FPSENCOS_enab_d_ff4_Zn)
);
OAI22X4TS U1698 ( .A0(n1478), .A1(n1871), .B0(n1484), .B1(n1483), .Y(n1862)
);
NOR3BX1TS U1699 ( .AN(FPMULT_Op_MY[30]), .B(FPMULT_FSM_selector_B[1]), .C(
FPMULT_FSM_selector_B[0]), .Y(n1636) );
NOR2X2TS U1700 ( .A(FPMULT_Sgf_normalized_result[4]), .B(n1709), .Y(n1708)
);
AOI221X1TS U1701 ( .A0(FPADDSUB_intDX_EWSW[30]), .A1(n2598), .B0(
FPADDSUB_intDX_EWSW[29]), .B1(n2505), .C0(n2003), .Y(n2005) );
NOR3X2TS U1702 ( .A(FPMULT_Sgf_normalized_result[2]), .B(
FPMULT_Sgf_normalized_result[1]), .C(FPMULT_Sgf_normalized_result[0]),
.Y(n1706) );
NOR4X2TS U1703 ( .A(n2542), .B(n2477), .C(n2491), .D(n2470), .Y(n1752) );
AOI21X2TS U1704 ( .A0(n1139), .A1(FPADDSUB_Data_array_SWR[46]), .B0(n1150),
.Y(n1298) );
OAI21X2TS U1705 ( .A0(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]), .A1(
intadd_1144_n1), .B0(n1241), .Y(DP_OP_499J326_125_1651_n121) );
NOR2X2TS U1706 ( .A(n1574), .B(n2770), .Y(n1576) );
OAI21X4TS U1707 ( .A0(intadd_1147_SUM_4_), .A1(intadd_1147_SUM_5_), .B0(
n1804), .Y(n1806) );
NAND2X4TS U1708 ( .A(intadd_1147_SUM_4_), .B(intadd_1147_SUM_5_), .Y(n1804)
);
NOR4X2TS U1709 ( .A(n2532), .B(n2492), .C(n2474), .D(n2469), .Y(
mult_x_309_n42) );
NOR4X2TS U1710 ( .A(n1740), .B(n2540), .C(n2478), .D(n2489), .Y(
mult_x_310_n42) );
INVX3TS U1711 ( .A(n950), .Y(n1740) );
NOR4X2TS U1712 ( .A(n1896), .B(n1907), .C(n1627), .D(n1462), .Y(n1903) );
AOI21X2TS U1713 ( .A0(n969), .A1(n2504), .B0(n1384), .Y(n1445) );
OAI21X2TS U1714 ( .A0(n2597), .A1(n1360), .B0(n1363), .Y(n1406) );
AOI21X2TS U1715 ( .A0(n1828), .A1(n1900), .B0(intadd_1160_B_0_), .Y(n1495)
);
BUFX4TS U1716 ( .A(n1536), .Y(n1551) );
OAI21X2TS U1717 ( .A0(mult_x_313_n74), .A1(n1066), .B0(intadd_1147_SUM_2_),
.Y(mult_x_313_n65) );
AOI22X2TS U1718 ( .A0(n2673), .A1(FPADDSUB_LZD_raw_out_EWR[1]), .B0(
FPADDSUB_Shift_amount_SHT1_EWR[1]), .B1(n2462), .Y(n2289) );
OAI31X1TS U1719 ( .A0(n965), .A1(n1028), .A2(n1029), .B0(n1027), .Y(
FPADDSUB_LZD_raw_out_EWR[1]) );
NOR2X1TS U1720 ( .A(n1782), .B(n2532), .Y(intadd_1162_CI) );
AOI21X4TS U1721 ( .A0(n1782), .A1(n1740), .B0(intadd_1148_CI), .Y(n1069) );
AOI21X4TS U1722 ( .A0(n1782), .A1(n2532), .B0(intadd_1162_CI), .Y(n1479) );
NOR4X2TS U1723 ( .A(n1782), .B(n2541), .C(n2479), .D(n2490), .Y(
mult_x_312_n42) );
INVX3TS U1724 ( .A(FPMULT_Op_MY[12]), .Y(n1782) );
BUFX6TS U1725 ( .A(n2323), .Y(n2425) );
INVX3TS U1726 ( .A(intadd_1161_SUM_2_), .Y(n1978) );
CMPR32X4TS U1727 ( .A(FPMULT_Op_MX[9]), .B(FPMULT_Op_MX[3]), .C(
intadd_1161_n3), .CO(intadd_1161_n2), .S(intadd_1161_SUM_2_) );
BUFX6TS U1728 ( .A(n1148), .Y(n2291) );
INVX4TS U1729 ( .A(n1103), .Y(n2718) );
OAI211X2TS U1730 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[21]), .A1(n2263), .B0(n2269), .C0(n1603), .Y(n1608) );
NOR2X1TS U1731 ( .A(FPADDSUB_Raw_mant_NRM_SWR[11]), .B(
FPADDSUB_Raw_mant_NRM_SWR[13]), .Y(n1324) );
OAI21X2TS U1732 ( .A0(FPMULT_FSM_add_overflow_flag), .A1(n2593), .B0(n2305),
.Y(n2102) );
AOI22X2TS U1733 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n2428), .B1(n2613),
.Y(n2792) );
OAI31X1TS U1734 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .A2(n2614), .B0(n2428),
.Y(n872) );
NOR2X4TS U1735 ( .A(FPMULT_Op_MY[17]), .B(intadd_1162_n1), .Y(n1881) );
INVX4TS U1736 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .Y(n1293) );
NAND2X2TS U1737 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(n961), .Y(n1170)
);
NOR2X2TS U1738 ( .A(FPADDSUB_DMP_SFG[20]), .B(n960), .Y(n1611) );
OAI21XLTS U1739 ( .A0(FPADDSUB_DMP_SFG[20]), .A1(n922), .B0(n1608), .Y(n1607) );
OAI2BB2X2TS U1740 ( .B0(n1608), .B1(FPADDSUB_DMP_SFG[20]), .A0N(n960), .A1N(
n1607), .Y(n1617) );
NOR3X1TS U1741 ( .A(FPADDSUB_Raw_mant_NRM_SWR[15]), .B(
FPADDSUB_Raw_mant_NRM_SWR[16]), .C(FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(
n1019) );
AOI32X1TS U1742 ( .A0(n1023), .A1(n1031), .A2(FPADDSUB_Raw_mant_NRM_SWR[15]),
.B0(FPADDSUB_Raw_mant_NRM_SWR[18]), .B1(n1031), .Y(n1024) );
INVX3TS U1743 ( .A(n2303), .Y(n2302) );
INVX3TS U1744 ( .A(n2278), .Y(n2279) );
BUFX6TS U1745 ( .A(n1249), .Y(n2149) );
BUFX6TS U1746 ( .A(n2381), .Y(n2420) );
AOI222X4TS U1747 ( .A0(FPADDSUB_DMP_SFG[18]), .A1(n2556), .B0(
FPADDSUB_DMP_SFG[18]), .B1(n2258), .C0(n2556), .C1(n2258), .Y(n2263)
);
NOR3X2TS U1748 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .Y(n1452) );
NOR3BX2TS U1749 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .C(n1634), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[3]) );
NOR3X1TS U1750 ( .A(n2064), .B(n2002), .C(FPADDSUB_intDY_EWSW[28]), .Y(n2003) );
OAI221X1TS U1751 ( .A0(n2515), .A1(FPADDSUB_intDY_EWSW[0]), .B0(n2064), .B1(
FPADDSUB_intDY_EWSW[28]), .C0(n2063), .Y(n2071) );
AOI2BB2X2TS U1752 ( .B0(n2189), .B1(n2187), .A0N(
FPADDSUB_DmP_mant_SFG_SWR[5]), .A1N(FPADDSUB_DMP_SFG[3]), .Y(n2193) );
OAI32X1TS U1753 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[23]), .A1(
FPADDSUB_Raw_mant_NRM_SWR[21]), .A2(n2591), .B0(n2504), .B1(
FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n1034) );
AOI222X4TS U1754 ( .A0(FPADDSUB_DMP_SFG[16]), .A1(n2539), .B0(
FPADDSUB_DMP_SFG[16]), .B1(n2249), .C0(n2539), .C1(n2249), .Y(n2254)
);
NAND2X2TS U1755 ( .A(n961), .B(FPADDSUB_shift_value_SHT2_EWR[3]), .Y(n1188)
);
AOI222X4TS U1756 ( .A0(FPADDSUB_DMP_SFG[12]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[14]), .B0(FPADDSUB_DMP_SFG[12]), .B1(n2228),
.C0(FPADDSUB_DmP_mant_SFG_SWR[14]), .C1(n2228), .Y(n2233) );
AOI2BB2X2TS U1757 ( .B0(n2229), .B1(n2227), .A0N(n2533), .A1N(
FPADDSUB_DmP_mant_SFG_SWR[14]), .Y(n2234) );
AOI2BB2X2TS U1758 ( .B0(n2237), .B1(n2238), .A0N(n2536), .A1N(
FPADDSUB_DmP_mant_SFG_SWR[16]), .Y(n2244) );
AOI2BB2X2TS U1759 ( .B0(n1347), .B1(n1346), .A0N(n2521), .A1N(
FPADDSUB_DmP_mant_SFG_SWR[2]), .Y(n2178) );
AOI32X1TS U1760 ( .A0(FPADDSUB_DMP_SFG[0]), .A1(n963), .A2(
FPADDSUB_DmP_mant_SFG_SWR[2]), .B0(n2178), .B1(n2269), .Y(n2181) );
NOR2X2TS U1761 ( .A(FPADDSUB_Raw_mant_NRM_SWR[18]), .B(n1036), .Y(n1341) );
AOI2BB2X2TS U1762 ( .B0(n2179), .B1(n1349), .A0N(
FPADDSUB_DmP_mant_SFG_SWR[3]), .A1N(FPADDSUB_DMP_SFG[1]), .Y(n2184) );
OAI2BB2X2TS U1763 ( .B0(n2232), .B1(n2233), .A0N(FPADDSUB_DMP_SFG[13]),
.A1N(FPADDSUB_DmP_mant_SFG_SWR[15]), .Y(n2239) );
NOR4X2TS U1764 ( .A(FPADDSUB_Raw_mant_NRM_SWR[24]), .B(
FPADDSUB_Raw_mant_NRM_SWR[25]), .C(FPADDSUB_Raw_mant_NRM_SWR[22]), .D(
FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n1318) );
OAI31X1TS U1765 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[24]), .A1(
FPADDSUB_Raw_mant_NRM_SWR[25]), .A2(n1025), .B0(n1024), .Y(n1026) );
OAI2BB2X2TS U1766 ( .B0(n2523), .B1(FPADDSUB_DmP_mant_SFG_SWR[4]), .A0N(
n2182), .A1N(n2183), .Y(n2188) );
OAI2BB2X2TS U1767 ( .B0(n2207), .B1(n2208), .A0N(FPADDSUB_DMP_SFG[8]), .A1N(
FPADDSUB_DmP_mant_SFG_SWR[10]), .Y(n2213) );
AOI222X4TS U1768 ( .A0(FPADDSUB_DMP_SFG[8]), .A1(n2529), .B0(
FPADDSUB_DMP_SFG[8]), .B1(n2209), .C0(n2529), .C1(n2209), .Y(n2214) );
AOI222X4TS U1769 ( .A0(FPADDSUB_DMP_SFG[7]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[9]), .B0(FPADDSUB_DMP_SFG[7]), .B1(n2203),
.C0(FPADDSUB_DmP_mant_SFG_SWR[9]), .C1(n2203), .Y(n2208) );
OAI2BB2X2TS U1770 ( .B0(n2202), .B1(n2204), .A0N(n2528), .A1N(
FPADDSUB_DMP_SFG[7]), .Y(n2209) );
OAI2BB2X2TS U1771 ( .B0(n2212), .B1(n2214), .A0N(n2530), .A1N(
FPADDSUB_DMP_SFG[9]), .Y(n2219) );
AOI222X4TS U1772 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[7]), .A1(n2199), .B0(
FPADDSUB_DmP_mant_SFG_SWR[7]), .B1(n2526), .C0(n2199), .C1(n2526), .Y(
n1601) );
AOI2BB2X2TS U1773 ( .B0(FPADDSUB_DMP_SFG[5]), .B1(
FPADDSUB_DmP_mant_SFG_SWR[7]), .A0N(n2197), .A1N(n2198), .Y(n1600) );
AOI2BB2X2TS U1774 ( .B0(FPADDSUB_DMP_SFG[10]), .B1(
FPADDSUB_DmP_mant_SFG_SWR[12]), .A0N(n2217), .A1N(n2218), .Y(n2224) );
NOR2X4TS U1775 ( .A(n942), .B(n924), .Y(enab_cont_iter) );
NOR4X1TS U1776 ( .A(FPMULT_Op_MX[12]), .B(FPMULT_Op_MX[24]), .C(
FPMULT_Op_MX[13]), .D(FPMULT_Op_MX[23]), .Y(n2445) );
AOI211X1TS U1777 ( .A0(FPMULT_Op_MX[12]), .A1(n959), .B0(n2481), .C0(n2500),
.Y(n1767) );
CLKINVX3TS U1778 ( .A(FPMULT_Op_MX[12]), .Y(n1777) );
NOR2X2TS U1779 ( .A(FPMULT_FS_Module_state_reg[1]), .B(
FPMULT_FS_Module_state_reg[3]), .Y(n2306) );
OAI21XLTS U1780 ( .A0(FPADDSUB_intDX_EWSW[1]), .A1(n2649), .B0(
FPADDSUB_intDX_EWSW[0]), .Y(n2009) );
NOR2XLTS U1781 ( .A(n2042), .B(FPADDSUB_intDY_EWSW[16]), .Y(n2043) );
OAI21XLTS U1782 ( .A0(DP_OP_500J326_126_4510_n32), .A1(intadd_1163_SUM_1_),
.B0(intadd_1163_SUM_2_), .Y(n1867) );
OAI21XLTS U1783 ( .A0(FPADDSUB_intDX_EWSW[23]), .A1(n2654), .B0(
FPADDSUB_intDX_EWSW[22]), .Y(n2049) );
NOR2XLTS U1784 ( .A(DP_OP_502J326_128_4510_n32), .B(intadd_1161_SUM_1_), .Y(
n1327) );
OAI21XLTS U1785 ( .A0(n2734), .A1(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[1]), .B0(n928), .Y(n1243) );
NOR2XLTS U1786 ( .A(n2479), .B(n2471), .Y(n1121) );
OR2X1TS U1787 ( .A(FPADDSUB_ADD_OVRFLW_NRM2), .B(
FPADDSUB_LZD_output_NRM2_EW[0]), .Y(n1648) );
OAI211XLTS U1788 ( .A0(n1976), .A1(n1932), .B0(n1626), .C0(
DP_OP_502J326_128_4510_n32), .Y(n1625) );
NOR2XLTS U1789 ( .A(n1924), .B(n1915), .Y(n1233) );
OAI211XLTS U1790 ( .A0(n1857), .A1(n1883), .B0(n1052), .C0(
DP_OP_500J326_126_4510_n32), .Y(n1051) );
INVX2TS U1791 ( .A(DP_OP_500J326_126_4510_n37), .Y(intadd_1152_A_2_) );
OAI21XLTS U1792 ( .A0(n1355), .A1(n1354), .B0(n1766), .Y(intadd_1153_B_1_)
);
OAI21XLTS U1793 ( .A0(n1313), .A1(n1312), .B0(n1728), .Y(intadd_1155_B_1_)
);
OAI21XLTS U1794 ( .A0(n1606), .A1(n1611), .B0(n1605), .Y(n1604) );
NOR2XLTS U1795 ( .A(n1631), .B(n1898), .Y(intadd_1149_B_2_) );
NOR2XLTS U1796 ( .A(n1911), .B(n1925), .Y(intadd_1141_B_2_) );
OAI211XLTS U1797 ( .A0(n1635), .A1(n2662), .B0(n1393), .C0(n2309), .Y(
FPMULT_FS_Module_state_next[3]) );
NOR2XLTS U1798 ( .A(n1680), .B(n1245), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[21]) );
NOR2XLTS U1799 ( .A(n1695), .B(n2292), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[11]) );
NOR3XLTS U1800 ( .A(FPMULT_Exp_module_Data_S[8]), .B(
FPMULT_Exp_module_Data_S[7]), .C(n1345), .Y(n2787) );
OR2X1TS U1801 ( .A(n1391), .B(n1261), .Y(FPMULT_FS_Module_state_next[0]) );
OAI211XLTS U1802 ( .A0(n1422), .A1(n1357), .B0(n1409), .C0(n1361), .Y(
FPADDSUB_Data_array_SWR[0]) );
OAI21XLTS U1803 ( .A0(n1359), .A1(n1432), .B0(n1383), .Y(
FPADDSUB_Data_array_SWR[13]) );
OAI21XLTS U1804 ( .A0(n1364), .A1(n1432), .B0(n1403), .Y(
FPADDSUB_Data_array_SWR[15]) );
OAI21XLTS U1805 ( .A0(n1569), .A1(n2581), .B0(n1546), .Y(op_result[0]) );
OAI21XLTS U1806 ( .A0(n1569), .A1(n2576), .B0(n1563), .Y(op_result[5]) );
OAI21XLTS U1807 ( .A0(n1569), .A1(n2561), .B0(n1538), .Y(op_result[20]) );
NOR2X1TS U1808 ( .A(n1777), .B(n2553), .Y(mult_x_312_n77) );
INVX2TS U1809 ( .A(DP_OP_500J326_126_4510_n22), .Y(intadd_1152_A_6_) );
NAND2X1TS U1810 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]), .B(
intadd_1144_n1), .Y(n1241) );
NOR2X1TS U1811 ( .A(intadd_1143_SUM_0_), .B(n2760), .Y(intadd_1142_CI) );
AOI21X1TS U1812 ( .A0(intadd_1143_SUM_0_), .A1(n2760), .B0(intadd_1142_CI),
.Y(n1656) );
INVX2TS U1813 ( .A(DP_OP_500J326_126_4510_n34), .Y(intadd_1152_A_3_) );
INVX2TS U1814 ( .A(DP_OP_500J326_126_4510_n30), .Y(intadd_1152_A_4_) );
INVX2TS U1815 ( .A(DP_OP_500J326_126_4510_n25), .Y(intadd_1152_A_5_) );
NAND3X1TS U1816 ( .A(FPMULT_FS_Module_state_reg[0]), .B(
FPMULT_FS_Module_state_reg[1]), .C(n2497), .Y(n2307) );
CLKAND2X2TS U1817 ( .A(intadd_1156_SUM_0_), .B(intadd_1142_SUM_5_), .Y(
intadd_1139_B_0_) );
AOI2BB1XLTS U1818 ( .A0N(intadd_1142_SUM_5_), .A1N(intadd_1156_SUM_0_), .B0(
intadd_1139_B_0_), .Y(n968) );
INVX4TS U1819 ( .A(n2674), .Y(n2462) );
NOR2XLTS U1820 ( .A(FPADDSUB_ADD_OVRFLW_NRM), .B(n2462), .Y(n970) );
BUFX4TS U1821 ( .A(n970), .Y(n2673) );
NOR4X1TS U1822 ( .A(Data_2[15]), .B(Data_2[19]), .C(Data_2[13]), .D(
Data_2[21]), .Y(n973) );
NOR4X1TS U1823 ( .A(Data_2[4]), .B(Data_2[18]), .C(Data_2[20]), .D(Data_2[1]), .Y(n972) );
NOR4X1TS U1824 ( .A(Data_2[3]), .B(Data_2[5]), .C(Data_2[22]), .D(Data_2[0]),
.Y(n971) );
NAND3XLTS U1825 ( .A(n973), .B(n972), .C(n971), .Y(n974) );
INVX2TS U1826 ( .A(Data_2[7]), .Y(n976) );
INVX2TS U1827 ( .A(n2675), .Y(n1106) );
NOR3X1TS U1828 ( .A(FPSENCOS_cont_var_out_1_), .B(n1106), .C(n2330), .Y(
n1993) );
BUFX4TS U1829 ( .A(n1993), .Y(n2381) );
NOR3X1TS U1830 ( .A(n2675), .B(n2330), .C(n2506), .Y(n979) );
BUFX3TS U1831 ( .A(n979), .Y(n2339) );
AOI22X1TS U1832 ( .A0(n2381), .A1(FPSENCOS_d_ff3_sh_y_out[7]), .B0(n2339),
.B1(FPSENCOS_d_ff3_sh_x_out[7]), .Y(n975) );
NAND2X1TS U1833 ( .A(n2675), .B(FPSENCOS_cont_var_out_1_), .Y(n2316) );
NAND2X1TS U1834 ( .A(n2323), .B(FPSENCOS_d_ff3_LUT_out[7]), .Y(n982) );
OAI211XLTS U1835 ( .A0(operation[1]), .A1(n976), .B0(n975), .C0(n982), .Y(
add_subt_data2[7]) );
INVX2TS U1836 ( .A(Data_2[3]), .Y(n978) );
AOI22X1TS U1837 ( .A0(n2381), .A1(FPSENCOS_d_ff3_sh_y_out[3]), .B0(n2339),
.B1(FPSENCOS_d_ff3_sh_x_out[3]), .Y(n977) );
NAND2X1TS U1838 ( .A(n2323), .B(FPSENCOS_d_ff3_LUT_out[3]), .Y(n1009) );
OAI211XLTS U1839 ( .A0(operation[1]), .A1(n978), .B0(n977), .C0(n1009), .Y(
add_subt_data2[3]) );
INVX2TS U1840 ( .A(Data_2[14]), .Y(n981) );
BUFX4TS U1841 ( .A(n979), .Y(n2396) );
AOI22X1TS U1842 ( .A0(n2381), .A1(FPSENCOS_d_ff3_sh_y_out[14]), .B0(n2396),
.B1(FPSENCOS_d_ff3_sh_x_out[14]), .Y(n980) );
NAND2X1TS U1843 ( .A(n2323), .B(FPSENCOS_d_ff3_LUT_out[5]), .Y(n987) );
OAI211XLTS U1844 ( .A0(operation[1]), .A1(n981), .B0(n980), .C0(n987), .Y(
add_subt_data2[14]) );
INVX2TS U1845 ( .A(Data_2[11]), .Y(n984) );
AOI22X1TS U1846 ( .A0(n2420), .A1(FPSENCOS_d_ff3_sh_y_out[11]), .B0(n2339),
.B1(FPSENCOS_d_ff3_sh_x_out[11]), .Y(n983) );
OAI211XLTS U1847 ( .A0(operation[1]), .A1(n984), .B0(n983), .C0(n982), .Y(
add_subt_data2[11]) );
INVX2TS U1848 ( .A(Data_2[13]), .Y(n986) );
AOI22X1TS U1849 ( .A0(n2420), .A1(FPSENCOS_d_ff3_sh_y_out[13]), .B0(n2339),
.B1(FPSENCOS_d_ff3_sh_x_out[13]), .Y(n985) );
NAND2X1TS U1850 ( .A(n2323), .B(FPSENCOS_d_ff3_LUT_out[13]), .Y(n990) );
OAI211XLTS U1851 ( .A0(operation[1]), .A1(n986), .B0(n985), .C0(n990), .Y(
add_subt_data2[13]) );
INVX2TS U1852 ( .A(Data_2[5]), .Y(n989) );
AOI22X1TS U1853 ( .A0(n2420), .A1(FPSENCOS_d_ff3_sh_y_out[5]), .B0(n2339),
.B1(FPSENCOS_d_ff3_sh_x_out[5]), .Y(n988) );
OAI211XLTS U1854 ( .A0(operation[1]), .A1(n989), .B0(n988), .C0(n987), .Y(
add_subt_data2[5]) );
INVX2TS U1855 ( .A(Data_2[18]), .Y(n992) );
AOI22X1TS U1856 ( .A0(n2420), .A1(FPSENCOS_d_ff3_sh_y_out[18]), .B0(n2396),
.B1(FPSENCOS_d_ff3_sh_x_out[18]), .Y(n991) );
OAI211XLTS U1857 ( .A0(operation[1]), .A1(n992), .B0(n991), .C0(n990), .Y(
add_subt_data2[18]) );
INVX2TS U1858 ( .A(Data_2[20]), .Y(n994) );
AOI22X1TS U1859 ( .A0(n2420), .A1(FPSENCOS_d_ff3_sh_y_out[20]), .B0(n2396),
.B1(FPSENCOS_d_ff3_sh_x_out[20]), .Y(n993) );
NAND2X1TS U1860 ( .A(n2323), .B(FPSENCOS_d_ff3_LUT_out[15]), .Y(n1002) );
OAI211XLTS U1861 ( .A0(operation[1]), .A1(n994), .B0(n993), .C0(n1002), .Y(
add_subt_data2[20]) );
INVX2TS U1862 ( .A(Data_2[22]), .Y(n996) );
AOI22X1TS U1863 ( .A0(n2420), .A1(FPSENCOS_d_ff3_sh_y_out[22]), .B0(n2396),
.B1(FPSENCOS_d_ff3_sh_x_out[22]), .Y(n995) );
NAND2X1TS U1864 ( .A(n2323), .B(FPSENCOS_d_ff3_LUT_out[19]), .Y(n997) );
OAI211XLTS U1865 ( .A0(operation[1]), .A1(n996), .B0(n995), .C0(n997), .Y(
add_subt_data2[22]) );
INVX2TS U1866 ( .A(Data_2[19]), .Y(n999) );
AOI22X1TS U1867 ( .A0(n2420), .A1(FPSENCOS_d_ff3_sh_y_out[19]), .B0(n2396),
.B1(FPSENCOS_d_ff3_sh_x_out[19]), .Y(n998) );
OAI211XLTS U1868 ( .A0(operation[1]), .A1(n999), .B0(n998), .C0(n997), .Y(
add_subt_data2[19]) );
INVX2TS U1869 ( .A(Data_2[17]), .Y(n1001) );
AOI22X1TS U1870 ( .A0(n2420), .A1(FPSENCOS_d_ff3_sh_y_out[17]), .B0(n2396),
.B1(FPSENCOS_d_ff3_sh_x_out[17]), .Y(n1000) );
OAI211XLTS U1871 ( .A0(operation[1]), .A1(n1001), .B0(n1000), .C0(n1002),
.Y(add_subt_data2[17]) );
INVX2TS U1872 ( .A(Data_2[15]), .Y(n1004) );
AOI22X1TS U1873 ( .A0(n2420), .A1(FPSENCOS_d_ff3_sh_y_out[15]), .B0(n2396),
.B1(FPSENCOS_d_ff3_sh_x_out[15]), .Y(n1003) );
OAI211XLTS U1874 ( .A0(operation[1]), .A1(n1004), .B0(n1003), .C0(n1002),
.Y(add_subt_data2[15]) );
INVX2TS U1875 ( .A(Data_2[27]), .Y(n1006) );
BUFX6TS U1876 ( .A(n2381), .Y(n2424) );
AOI22X1TS U1877 ( .A0(n2424), .A1(FPSENCOS_d_ff3_sh_y_out[27]), .B0(n2396),
.B1(FPSENCOS_d_ff3_sh_x_out[27]), .Y(n1005) );
NAND2X1TS U1878 ( .A(n2323), .B(FPSENCOS_d_ff3_LUT_out[27]), .Y(n1012) );
OAI211XLTS U1879 ( .A0(operation[1]), .A1(n1006), .B0(n1005), .C0(n1012),
.Y(add_subt_data2[27]) );
INVX2TS U1880 ( .A(Data_2[28]), .Y(n1008) );
BUFX4TS U1881 ( .A(n2396), .Y(n2423) );
AOI22X1TS U1882 ( .A0(n2424), .A1(FPSENCOS_d_ff3_sh_y_out[28]), .B0(n2423),
.B1(FPSENCOS_d_ff3_sh_x_out[28]), .Y(n1007) );
OAI211XLTS U1883 ( .A0(operation[1]), .A1(n1008), .B0(n1007), .C0(n1012),
.Y(add_subt_data2[28]) );
INVX2TS U1884 ( .A(Data_2[16]), .Y(n1011) );
AOI22X1TS U1885 ( .A0(n2420), .A1(FPSENCOS_d_ff3_sh_y_out[16]), .B0(n2423),
.B1(FPSENCOS_d_ff3_sh_x_out[16]), .Y(n1010) );
OAI211XLTS U1886 ( .A0(operation[1]), .A1(n1011), .B0(n1010), .C0(n1009),
.Y(add_subt_data2[16]) );
INVX2TS U1887 ( .A(Data_2[29]), .Y(n1014) );
AOI22X1TS U1888 ( .A0(n2424), .A1(FPSENCOS_d_ff3_sh_y_out[29]), .B0(n2423),
.B1(FPSENCOS_d_ff3_sh_x_out[29]), .Y(n1013) );
OAI211XLTS U1889 ( .A0(operation[1]), .A1(n1014), .B0(n1013), .C0(n1012),
.Y(add_subt_data2[29]) );
INVX2TS U1890 ( .A(DP_OP_500J326_126_4510_n38), .Y(intadd_1152_A_1_) );
INVX2TS U1891 ( .A(DP_OP_500J326_126_4510_n35), .Y(intadd_1152_B_2_) );
INVX2TS U1892 ( .A(DP_OP_500J326_126_4510_n31), .Y(intadd_1152_B_3_) );
INVX2TS U1893 ( .A(DP_OP_500J326_126_4510_n26), .Y(intadd_1152_B_4_) );
INVX2TS U1894 ( .A(DP_OP_500J326_126_4510_n23), .Y(intadd_1152_B_5_) );
INVX2TS U1895 ( .A(intadd_1160_SUM_2_), .Y(n1535) );
NAND2X2TS U1896 ( .A(intadd_1159_n1), .B(intadd_1148_SUM_5_), .Y(n1919) );
OR4X2TS U1897 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[2]), .C(FPADDSUB_exp_rslt_NRM2_EW1[1]), .D(
FPADDSUB_exp_rslt_NRM2_EW1[0]), .Y(n1015) );
OR4X2TS U1898 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[6]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[5]), .C(FPADDSUB_exp_rslt_NRM2_EW1[4]), .D(
n1015), .Y(n1016) );
NOR2X2TS U1899 ( .A(n2497), .B(FPMULT_FS_Module_state_reg[1]), .Y(n2308) );
NOR2XLTS U1900 ( .A(FPMULT_FS_Module_state_reg[0]), .B(
FPMULT_FS_Module_state_reg[3]), .Y(n1017) );
NAND2X2TS U1901 ( .A(n2308), .B(n1017), .Y(n1635) );
NOR2X1TS U1902 ( .A(FPADDSUB_Raw_mant_NRM_SWR[11]), .B(
FPADDSUB_Raw_mant_NRM_SWR[10]), .Y(n1028) );
NAND2X1TS U1903 ( .A(n1316), .B(n1318), .Y(n1036) );
NAND2X1TS U1904 ( .A(n1019), .B(n1341), .Y(n1018) );
OR2X1TS U1905 ( .A(n1018), .B(FPADDSUB_Raw_mant_NRM_SWR[14]), .Y(n1323) );
OR2X1TS U1906 ( .A(FPADDSUB_Raw_mant_NRM_SWR[13]), .B(n1323), .Y(n1029) );
NOR2X1TS U1907 ( .A(n2543), .B(n1018), .Y(n1039) );
NOR2X1TS U1908 ( .A(FPADDSUB_Raw_mant_NRM_SWR[7]), .B(
FPADDSUB_Raw_mant_NRM_SWR[6]), .Y(n1021) );
NOR2XLTS U1909 ( .A(FPADDSUB_Raw_mant_NRM_SWR[9]), .B(
FPADDSUB_Raw_mant_NRM_SWR[8]), .Y(n1020) );
AOI2BB1X1TS U1910 ( .A0N(n2544), .A1N(FPADDSUB_Raw_mant_NRM_SWR[11]), .B0(
n965), .Y(n1030) );
NAND4XLTS U1911 ( .A(n1030), .B(n1324), .C(n1019), .D(n2543), .Y(n1340) );
NOR2BX1TS U1912 ( .AN(n1341), .B(n1340), .Y(n1215) );
NAND2X1TS U1913 ( .A(n1020), .B(n1215), .Y(n1041) );
NAND2BX1TS U1914 ( .AN(n1041), .B(n1021), .Y(n1315) );
NOR2X1TS U1915 ( .A(FPADDSUB_Raw_mant_NRM_SWR[5]), .B(n1315), .Y(n1217) );
NAND2X1TS U1916 ( .A(n1217), .B(n2554), .Y(n1342) );
OAI22X1TS U1917 ( .A0(n1021), .A1(n1041), .B0(n1216), .B1(n1342), .Y(n1221)
);
NOR2XLTS U1918 ( .A(FPADDSUB_Raw_mant_NRM_SWR[20]), .B(
FPADDSUB_Raw_mant_NRM_SWR[21]), .Y(n1022) );
NOR2XLTS U1919 ( .A(FPADDSUB_Raw_mant_NRM_SWR[16]), .B(
FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(n1023) );
INVX2TS U1920 ( .A(n1036), .Y(n1031) );
NOR3X1TS U1921 ( .A(n1039), .B(n1221), .C(n1026), .Y(n1027) );
AO21XLTS U1922 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[3]), .A1(n2554), .B0(
FPADDSUB_Raw_mant_NRM_SWR[5]), .Y(n1319) );
AOI2BB2XLTS U1923 ( .B0(n1031), .B1(FPADDSUB_Raw_mant_NRM_SWR[18]), .A0N(
n1030), .A1N(n1029), .Y(n1032) );
OAI31X1TS U1924 ( .A0(n1033), .A1(n1315), .A2(n1319), .B0(n1032), .Y(n1314)
);
OAI21XLTS U1925 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[24]), .A1(n1034), .B0(n2555),
.Y(n1035) );
OAI31X1TS U1926 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[17]), .A1(n2596), .A2(n1036),
.B0(n1035), .Y(n1037) );
NOR4X1TS U1927 ( .A(n1039), .B(n1038), .C(n1037), .D(n1314), .Y(n1040) );
INVX2TS U1928 ( .A(intadd_1148_SUM_9_), .Y(n1450) );
INVX2TS U1929 ( .A(intadd_1148_SUM_7_), .Y(n1896) );
INVX2TS U1930 ( .A(intadd_1147_SUM_9_), .Y(n1906) );
AOI21X2TS U1931 ( .A0(intadd_1148_n1), .A1(FPMULT_Op_MY[11]), .B0(n1901),
.Y(n1226) );
INVX2TS U1932 ( .A(intadd_1147_SUM_7_), .Y(n1462) );
INVX2TS U1933 ( .A(intadd_1160_SUM_0_), .Y(n1629) );
INVX2TS U1934 ( .A(intadd_1159_SUM_4_), .Y(n1917) );
INVX2TS U1935 ( .A(intadd_1147_SUM_0_), .Y(mult_x_313_n74) );
INVX2TS U1936 ( .A(intadd_1147_SUM_1_), .Y(n1066) );
NAND2X1TS U1937 ( .A(intadd_1144_SUM_7_), .B(intadd_1139_n1), .Y(n1674) );
OA21XLTS U1938 ( .A0(intadd_1144_SUM_7_), .A1(intadd_1139_n1), .B0(n1674),
.Y(FPMULT_Sgf_operation_Result[38]) );
NOR2X1TS U1939 ( .A(n1777), .B(n946), .Y(intadd_1147_CI) );
AOI21X1TS U1940 ( .A0(n1777), .A1(n2473), .B0(intadd_1147_CI), .Y(n1042) );
BUFX3TS U1941 ( .A(n1042), .Y(n1510) );
INVX2TS U1942 ( .A(n1510), .Y(n1828) );
INVX2TS U1943 ( .A(intadd_1147_SUM_6_), .Y(n1900) );
NOR2X1TS U1944 ( .A(n1828), .B(n1900), .Y(intadd_1160_B_0_) );
NAND2X1TS U1945 ( .A(n2620), .B(FPSENCOS_cont_iter_out[0]), .Y(
intadd_1164_CI) );
OAI21XLTS U1946 ( .A0(FPSENCOS_cont_iter_out[0]), .A1(n2620), .B0(
intadd_1164_CI), .Y(FPSENCOS_sh_exp_x[0]) );
NAND2X1TS U1947 ( .A(n2621), .B(FPSENCOS_cont_iter_out[0]), .Y(
intadd_1165_CI) );
OAI21XLTS U1948 ( .A0(FPSENCOS_cont_iter_out[0]), .A1(n2621), .B0(
intadd_1165_CI), .Y(FPSENCOS_sh_exp_y[0]) );
NOR2X1TS U1949 ( .A(FPMULT_FS_Module_state_reg[1]), .B(
FPMULT_FS_Module_state_reg[2]), .Y(n1049) );
NAND2X1TS U1950 ( .A(FPMULT_FS_Module_state_reg[3]), .B(n1049), .Y(n1393) );
OAI221X2TS U1951 ( .A0(FPMULT_FS_Module_state_reg[3]), .A1(
FPMULT_FS_Module_state_reg[2]), .B0(n2593), .B1(n2497), .C0(
FPMULT_FS_Module_state_reg[1]), .Y(n2309) );
NOR2X1TS U1952 ( .A(n2547), .B(n2500), .Y(n1136) );
AND3X1TS U1953 ( .A(n1136), .B(FPMULT_Op_MX[16]), .C(n959), .Y(
mult_x_312_n26) );
NOR2X1TS U1954 ( .A(n2546), .B(n2499), .Y(n1134) );
AND3X1TS U1955 ( .A(n1134), .B(FPMULT_Op_MX[4]), .C(FPMULT_Op_MY[1]), .Y(
mult_x_310_n26) );
NAND2X1TS U1956 ( .A(FPMULT_Op_MY[6]), .B(FPMULT_Op_MX[9]), .Y(n1747) );
NAND2X1TS U1957 ( .A(FPMULT_Op_MX[10]), .B(FPMULT_Op_MY[7]), .Y(n1761) );
AND4X1TS U1958 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[2]), .C(FPADDSUB_exp_rslt_NRM2_EW1[1]), .D(
FPADDSUB_exp_rslt_NRM2_EW1[0]), .Y(n1043) );
AND4X1TS U1959 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[6]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[5]), .C(FPADDSUB_exp_rslt_NRM2_EW1[4]), .D(
n1043), .Y(n1044) );
AND3X1TS U1960 ( .A(n1045), .B(FPADDSUB_exp_rslt_NRM2_EW1[7]), .C(n1044),
.Y(n2784) );
NAND3BX1TS U1961 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .B(n1452),
.C(n967), .Y(n1524) );
NOR2X1TS U1962 ( .A(n1782), .B(n1740), .Y(intadd_1148_CI) );
INVX2TS U1963 ( .A(n1069), .Y(n1805) );
NAND2X1TS U1964 ( .A(intadd_1147_SUM_2_), .B(intadd_1147_SUM_3_), .Y(n1093)
);
INVX2TS U1965 ( .A(intadd_1160_SUM_1_), .Y(n1918) );
NOR2XLTS U1966 ( .A(n1917), .B(n1918), .Y(n1048) );
INVX2TS U1967 ( .A(intadd_1159_SUM_2_), .Y(n1924) );
NAND2X2TS U1968 ( .A(intadd_1159_SUM_1_), .B(intadd_1160_SUM_1_), .Y(n1927)
);
NOR2BX2TS U1969 ( .AN(n1926), .B(n1927), .Y(n1517) );
INVX2TS U1970 ( .A(intadd_1160_SUM_4_), .Y(n1915) );
INVX2TS U1971 ( .A(intadd_1159_SUM_1_), .Y(n1530) );
INVX2TS U1972 ( .A(n1517), .Y(n1046) );
OAI32X1TS U1973 ( .A0(n1517), .A1(n1915), .A2(n1530), .B0(intadd_1160_SUM_4_), .B1(n1046), .Y(n1047) );
OA21XLTS U1974 ( .A0(n1048), .A1(n1047), .B0(n1235), .Y(
DP_OP_501J326_127_5235_n148) );
INVX2TS U1975 ( .A(intadd_1144_SUM_11_), .Y(DP_OP_499J326_125_1651_n123) );
INVX2TS U1976 ( .A(intadd_1144_SUM_9_), .Y(DP_OP_499J326_125_1651_n125) );
NAND3X1TS U1977 ( .A(intadd_1144_SUM_8_), .B(intadd_1144_SUM_7_), .C(
intadd_1139_n1), .Y(n1672) );
NOR2X2TS U1978 ( .A(DP_OP_499J326_125_1651_n125), .B(n1672), .Y(n1671) );
NAND2X1TS U1979 ( .A(intadd_1144_SUM_10_), .B(n1671), .Y(n1670) );
NOR2X2TS U1980 ( .A(DP_OP_499J326_125_1651_n123), .B(n1670), .Y(n1669) );
NAND2X1TS U1981 ( .A(intadd_1144_SUM_12_), .B(n1669), .Y(n1668) );
OA21XLTS U1982 ( .A0(intadd_1144_SUM_12_), .A1(n1669), .B0(n1668), .Y(
FPMULT_Sgf_operation_Result[43]) );
NOR2XLTS U1983 ( .A(n2593), .B(n2307), .Y(FPMULT_FSM_final_result_load) );
AND3X1TS U1984 ( .A(n1049), .B(FPMULT_FS_Module_state_reg[0]), .C(
FPMULT_FS_Module_state_reg[3]), .Y(FPMULT_FSM_adder_round_norm_load)
);
NOR2X1TS U1985 ( .A(n2488), .B(n2545), .Y(n1138) );
AND3X1TS U1986 ( .A(n1138), .B(FPMULT_Op_MX[10]), .C(FPMULT_Op_MY[7]), .Y(
mult_x_311_n26) );
NAND2X1TS U1987 ( .A(n950), .B(FPMULT_Op_MX[3]), .Y(n1731) );
NAND2X1TS U1988 ( .A(FPMULT_Op_MX[4]), .B(FPMULT_Op_MY[1]), .Y(n1739) );
NOR2X1TS U1989 ( .A(n2501), .B(n2469), .Y(n1132) );
NAND2X1TS U1990 ( .A(FPMULT_Op_MY[18]), .B(FPMULT_Op_MX[21]), .Y(n1715) );
NAND2X1TS U1991 ( .A(FPMULT_Op_MY[12]), .B(FPMULT_Op_MX[15]), .Y(n1769) );
NAND2X1TS U1992 ( .A(FPMULT_Op_MX[16]), .B(n959), .Y(n1781) );
NOR2X1TS U1993 ( .A(n1777), .B(n2487), .Y(intadd_1163_CI) );
INVX2TS U1994 ( .A(DP_OP_500J326_126_4510_n32), .Y(
DP_OP_500J326_126_4510_n27) );
NAND2X1TS U1995 ( .A(DP_OP_500J326_126_4510_n32), .B(intadd_1163_SUM_1_),
.Y(n1866) );
NAND2X1TS U1996 ( .A(intadd_1163_SUM_2_), .B(n1866), .Y(
DP_OP_500J326_126_4510_n66) );
INVX2TS U1997 ( .A(n1479), .Y(n1853) );
NAND2X1TS U1998 ( .A(intadd_1163_SUM_2_), .B(intadd_1163_SUM_3_), .Y(n1482)
);
OAI21X4TS U1999 ( .A0(intadd_1163_SUM_2_), .A1(intadd_1163_SUM_3_), .B0(
n1482), .Y(n1864) );
NOR2X1TS U2000 ( .A(n1853), .B(n1864), .Y(n1469) );
OAI21X2TS U2001 ( .A0(DP_OP_500J326_126_4510_n32), .A1(intadd_1163_SUM_1_),
.B0(n1866), .Y(n1878) );
INVX2TS U2002 ( .A(n1878), .Y(n1472) );
INVX2TS U2003 ( .A(intadd_1162_SUM_1_), .Y(n1859) );
AOI22X1TS U2004 ( .A0(intadd_1162_SUM_1_), .A1(intadd_1163_SUM_2_), .B0(
n1871), .B1(n1859), .Y(n1471) );
INVX2TS U2005 ( .A(intadd_1162_SUM_0_), .Y(n1852) );
AOI22X1TS U2006 ( .A0(intadd_1162_SUM_0_), .A1(intadd_1163_SUM_2_), .B0(
n1871), .B1(n1852), .Y(n1055) );
OAI32X4TS U2007 ( .A0(n1871), .A1(DP_OP_500J326_126_4510_n32), .A2(
intadd_1163_SUM_1_), .B0(intadd_1163_SUM_2_), .B1(n1866), .Y(n1876) );
AO22XLTS U2008 ( .A0(n1472), .A1(n1471), .B0(n1055), .B1(n1876), .Y(n1468)
);
AOI21X1TS U2009 ( .A0(n1777), .A1(n2487), .B0(intadd_1163_CI), .Y(n1050) );
CLKBUFX3TS U2010 ( .A(n1050), .Y(n1883) );
NAND2X1TS U2011 ( .A(n1883), .B(intadd_1162_SUM_3_), .Y(n1052) );
INVX2TS U2012 ( .A(intadd_1162_SUM_2_), .Y(n1857) );
OAI21XLTS U2013 ( .A0(DP_OP_500J326_126_4510_n32), .A1(n1052), .B0(n1051),
.Y(n1467) );
INVX2TS U2014 ( .A(n1883), .Y(n1880) );
AOI22X1TS U2015 ( .A0(n1883), .A1(intadd_1162_SUM_2_), .B0(
intadd_1162_SUM_1_), .B1(n1880), .Y(n1053) );
AOI32X1TS U2016 ( .A0(n1883), .A1(DP_OP_500J326_126_4510_n27), .A2(
intadd_1162_SUM_2_), .B0(n1053), .B1(DP_OP_500J326_126_4510_n32), .Y(
n1059) );
AOI22X1TS U2017 ( .A0(n1479), .A1(intadd_1163_SUM_2_), .B0(n1871), .B1(n1853), .Y(n1054) );
AOI22X1TS U2018 ( .A0(n1472), .A1(n1055), .B0(n1876), .B1(n1054), .Y(n1060)
);
NOR2X1TS U2019 ( .A(n1059), .B(n1060), .Y(n1062) );
NAND2X1TS U2020 ( .A(n1883), .B(intadd_1162_SUM_1_), .Y(n1057) );
OAI211XLTS U2021 ( .A0(n1852), .A1(n1883), .B0(n1057), .C0(
DP_OP_500J326_126_4510_n32), .Y(n1056) );
OAI21X1TS U2022 ( .A0(DP_OP_500J326_126_4510_n32), .A1(n1057), .B0(n1056),
.Y(n1213) );
OAI32X1TS U2023 ( .A0(n1479), .A1(n1280), .A2(DP_OP_500J326_126_4510_n27),
.B0(n1878), .B1(n1853), .Y(n1214) );
NAND2X1TS U2024 ( .A(n1213), .B(n1214), .Y(n1212) );
NOR3X1TS U2025 ( .A(DP_OP_500J326_126_4510_n66), .B(n1479), .C(n1212), .Y(
n1061) );
AOI21X1TS U2026 ( .A0(n1472), .A1(n1479), .B0(DP_OP_500J326_126_4510_n66),
.Y(n1058) );
XOR2X1TS U2027 ( .A(n1058), .B(n1212), .Y(n1850) );
XNOR2X1TS U2028 ( .A(n1060), .B(n1059), .Y(n1849) );
NOR2X1TS U2029 ( .A(n1850), .B(n1849), .Y(n1848) );
NOR3X1TS U2030 ( .A(n1061), .B(n1062), .C(n1848), .Y(n1476) );
AO21XLTS U2031 ( .A0(n1062), .A1(n1061), .B0(n1476), .Y(n1063) );
NOR2X1TS U2032 ( .A(n1064), .B(n1063), .Y(n1475) );
AO21XLTS U2033 ( .A0(n1064), .A1(n1063), .B0(n1475), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N4) );
AOI22X1TS U2034 ( .A0(n1510), .A1(intadd_1148_SUM_2_), .B0(
intadd_1148_SUM_1_), .B1(n1828), .Y(n1065) );
AOI32X1TS U2035 ( .A0(n1510), .A1(mult_x_313_n74), .A2(intadd_1148_SUM_2_),
.B0(n1065), .B1(intadd_1147_SUM_0_), .Y(n1071) );
NOR2X1TS U2036 ( .A(intadd_1147_SUM_0_), .B(intadd_1147_SUM_1_), .Y(n1818)
);
AOI21X2TS U2037 ( .A0(intadd_1147_SUM_1_), .A1(intadd_1147_SUM_0_), .B0(
n1818), .Y(n1783) );
INVX2TS U2038 ( .A(intadd_1147_SUM_2_), .Y(n1821) );
INVX2TS U2039 ( .A(intadd_1148_SUM_0_), .Y(n1807) );
AOI22X1TS U2040 ( .A0(intadd_1148_SUM_0_), .A1(intadd_1147_SUM_2_), .B0(
n1821), .B1(n1807), .Y(n1785) );
OAI33X4TS U2041 ( .A0(intadd_1147_SUM_0_), .A1(intadd_1147_SUM_1_), .A2(
n1821), .B0(mult_x_313_n74), .B1(n1066), .B2(intadd_1147_SUM_2_), .Y(
n1786) );
AOI22X1TS U2042 ( .A0(n1069), .A1(intadd_1147_SUM_2_), .B0(n1821), .B1(n1805), .Y(n1791) );
AOI22X1TS U2043 ( .A0(n1783), .A1(n1785), .B0(n1786), .B1(n1791), .Y(n1072)
);
NOR2X1TS U2044 ( .A(n1071), .B(n1072), .Y(n1074) );
NAND2X1TS U2045 ( .A(n1510), .B(intadd_1148_SUM_1_), .Y(n1068) );
OAI211XLTS U2046 ( .A0(n1807), .A1(n1510), .B0(n1068), .C0(
intadd_1147_SUM_0_), .Y(n1067) );
OAI21X1TS U2047 ( .A0(intadd_1147_SUM_0_), .A1(n1068), .B0(n1067), .Y(n1209)
);
AOI22X1TS U2048 ( .A0(intadd_1147_SUM_0_), .A1(n1069), .B0(n1510), .B1(
intadd_1148_SUM_0_), .Y(n1277) );
AO22XLTS U2049 ( .A0(n1069), .A1(n1783), .B0(intadd_1147_SUM_0_), .B1(n1277),
.Y(n1210) );
NAND2X1TS U2050 ( .A(n1209), .B(n1210), .Y(n1208) );
NOR3X1TS U2051 ( .A(mult_x_313_n65), .B(n1069), .C(n1208), .Y(n1073) );
AOI21X1TS U2052 ( .A0(n1069), .A1(n1783), .B0(mult_x_313_n65), .Y(n1070) );
XOR2X1TS U2053 ( .A(n1208), .B(n1070), .Y(n1803) );
XNOR2X1TS U2054 ( .A(n1072), .B(n1071), .Y(n1802) );
NOR2X1TS U2055 ( .A(n1803), .B(n1802), .Y(n1801) );
NOR3X1TS U2056 ( .A(n1073), .B(n1074), .C(n1801), .Y(n1798) );
AO21XLTS U2057 ( .A0(n1074), .A1(n1073), .B0(n1798), .Y(n1075) );
NOR2X1TS U2058 ( .A(intadd_1150_SUM_0_), .B(n1075), .Y(n1797) );
AO21XLTS U2059 ( .A0(intadd_1150_SUM_0_), .A1(n1075), .B0(n1797), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N4) );
OR3X1TS U2060 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .Y(n1076) );
NOR2BX1TS U2061 ( .AN(n1451), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]),
.Y(n1081) );
NAND2BX1TS U2062 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .B(n1081),
.Y(n1634) );
INVX2TS U2063 ( .A(FPMULT_FS_Module_state_reg[0]), .Y(n2305) );
MXI2X1TS U2064 ( .A(r_mode[0]), .B(r_mode[1]), .S0(n2777), .Y(n1077) );
OAI211XLTS U2065 ( .A0(r_mode[0]), .A1(r_mode[1]), .B0(n2305), .C0(n1077),
.Y(n1078) );
AOI31X1TS U2066 ( .A0(n2780), .A1(n2779), .A2(n2778), .B0(n1078), .Y(n1394)
);
INVX2TS U2067 ( .A(n1394), .Y(n1079) );
OAI21XLTS U2068 ( .A0(n1393), .A1(n1079), .B0(n2624), .Y(n825) );
INVX2TS U2069 ( .A(n1899), .Y(intadd_1160_A_4_) );
INVX2TS U2070 ( .A(n1901), .Y(intadd_1159_A_4_) );
INVX2TS U2071 ( .A(intadd_1147_SUM_8_), .Y(n1627) );
CLKAND2X2TS U2072 ( .A(DP_OP_501J326_127_5235_n62), .B(
DP_OP_501J326_127_5235_n48), .Y(n1897) );
AOI22X1TS U2073 ( .A0(DP_OP_501J326_127_5235_n48), .A1(
DP_OP_501J326_127_5235_n62), .B0(intadd_1148_SUM_8_), .B1(
intadd_1160_A_4_), .Y(n1455) );
AO21XLTS U2074 ( .A0(intadd_1148_SUM_8_), .A1(n1897), .B0(n1455), .Y(n1080)
);
AOI21X1TS U2075 ( .A0(intadd_1147_SUM_8_), .A1(intadd_1159_A_4_), .B0(n1080),
.Y(n1454) );
AO21XLTS U2076 ( .A0(n1228), .A1(n1080), .B0(n1454), .Y(
DP_OP_501J326_127_5235_n20) );
NOR2XLTS U2077 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .Y(n1082) );
NAND3XLTS U2078 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .B(n1082),
.C(n1081), .Y(n2317) );
INVX2TS U2079 ( .A(n2317), .Y(n2437) );
NOR2X1TS U2080 ( .A(n2437), .B(n2319), .Y(n2313) );
INVX2TS U2081 ( .A(begin_operation), .Y(n1457) );
INVX2TS U2082 ( .A(operation[2]), .Y(n2353) );
NAND2X1TS U2083 ( .A(n2440), .B(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]),
.Y(n1085) );
AOI221XLTS U2084 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .A1(
n1085), .B0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .B1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .C0(n1084), .Y(n842) );
INVX2TS U2085 ( .A(intadd_1161_SUM_3_), .Y(n1087) );
NAND2X1TS U2086 ( .A(n1978), .B(n1087), .Y(n1499) );
OA21X2TS U2087 ( .A0(n1087), .A1(n1978), .B0(n1499), .Y(n1941) );
NOR2X1TS U2088 ( .A(FPMULT_Op_MX[5]), .B(intadd_1161_n1), .Y(n1449) );
AOI21X1TS U2089 ( .A0(intadd_1161_n1), .A1(FPMULT_Op_MX[5]), .B0(n1449), .Y(
n1086) );
INVX2TS U2090 ( .A(intadd_1158_n1), .Y(n1974) );
AOI22X1TS U2091 ( .A0(n953), .A1(intadd_1158_n1), .B0(n1974), .B1(n952), .Y(
n1500) );
OAI33X4TS U2092 ( .A0(intadd_1161_SUM_2_), .A1(intadd_1161_SUM_3_), .A2(n952), .B0(n1978), .B1(n1087), .B2(n953), .Y(n1940) );
INVX2TS U2093 ( .A(intadd_1158_SUM_4_), .Y(n1976) );
AOI22X1TS U2094 ( .A0(n953), .A1(intadd_1158_SUM_4_), .B0(n1976), .B1(n952),
.Y(n1088) );
AO22XLTS U2095 ( .A0(n1941), .A1(n1500), .B0(n1940), .B1(n1088), .Y(
DP_OP_502J326_128_4510_n59) );
INVX2TS U2096 ( .A(intadd_1158_SUM_3_), .Y(n1979) );
AOI22X1TS U2097 ( .A0(intadd_1158_SUM_3_), .A1(n953), .B0(n952), .B1(n1979),
.Y(n1089) );
AO22XLTS U2098 ( .A0(n1941), .A1(n1088), .B0(n1940), .B1(n1089), .Y(
DP_OP_502J326_128_4510_n60) );
INVX2TS U2099 ( .A(intadd_1158_SUM_2_), .Y(n1968) );
AOI22X1TS U2100 ( .A0(intadd_1158_SUM_2_), .A1(n953), .B0(n952), .B1(n1968),
.Y(n1090) );
AO22XLTS U2101 ( .A0(n1941), .A1(n1089), .B0(n1940), .B1(n1090), .Y(
DP_OP_502J326_128_4510_n61) );
INVX2TS U2102 ( .A(intadd_1158_SUM_1_), .Y(n1969) );
AOI22X1TS U2103 ( .A0(intadd_1158_SUM_1_), .A1(n953), .B0(n952), .B1(n1969),
.Y(n1092) );
AO22XLTS U2104 ( .A0(n1941), .A1(n1090), .B0(n1940), .B1(n1092), .Y(
DP_OP_502J326_128_4510_n62) );
INVX2TS U2105 ( .A(intadd_1158_SUM_0_), .Y(n1971) );
AOI22X1TS U2106 ( .A0(intadd_1158_SUM_0_), .A1(n953), .B0(n952), .B1(n1971),
.Y(n1942) );
AO22XLTS U2107 ( .A0(n1941), .A1(n1092), .B0(n1942), .B1(n1940), .Y(
DP_OP_502J326_128_4510_n63) );
NAND2X1TS U2108 ( .A(DP_OP_502J326_128_4510_n32), .B(intadd_1161_SUM_1_),
.Y(n1328) );
NAND2X1TS U2109 ( .A(intadd_1161_SUM_2_), .B(n1328), .Y(
DP_OP_502J326_128_4510_n66) );
CLKAND2X2TS U2110 ( .A(n1093), .B(intadd_1147_SUM_4_), .Y(n1794) );
AOI22X1TS U2111 ( .A0(n1510), .A1(intadd_1148_SUM_4_), .B0(
intadd_1148_SUM_3_), .B1(n1828), .Y(n1094) );
AOI32X1TS U2112 ( .A0(n1510), .A1(mult_x_313_n74), .A2(intadd_1148_SUM_4_),
.B0(n1094), .B1(intadd_1147_SUM_0_), .Y(n1796) );
NOR3BX1TS U2113 ( .AN(n1794), .B(n1796), .C(intadd_1150_B_0_), .Y(
mult_x_313_n42) );
OAI21X4TS U2114 ( .A0(intadd_1160_n1), .A1(intadd_1147_SUM_5_), .B0(n1630),
.Y(n1518) );
OR2X1TS U2115 ( .A(n1518), .B(n1917), .Y(n1237) );
NAND2BXLTS U2116 ( .AN(n1630), .B(intadd_1159_SUM_3_), .Y(n1239) );
INVX2TS U2117 ( .A(n1919), .Y(n1229) );
NAND2X1TS U2118 ( .A(n1229), .B(intadd_1160_SUM_3_), .Y(n1238) );
AOI21X1TS U2119 ( .A0(n1237), .A1(n1239), .B0(n1238), .Y(
DP_OP_501J326_127_5235_n115) );
OA21XLTS U2120 ( .A0(intadd_1144_SUM_10_), .A1(n1671), .B0(n1670), .Y(
FPMULT_Sgf_operation_Result[41]) );
INVX2TS U2121 ( .A(intadd_1148_SUM_6_), .Y(n1898) );
NOR2X1TS U2122 ( .A(n1805), .B(n1898), .Y(intadd_1159_B_0_) );
AOI21X1TS U2123 ( .A0(n1805), .A1(n1898), .B0(intadd_1159_B_0_), .Y(n1494)
);
INVX2TS U2124 ( .A(n1494), .Y(n1911) );
INVX2TS U2125 ( .A(n1495), .Y(n1529) );
NOR2X2TS U2126 ( .A(n1911), .B(n1529), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N0) );
NAND2X2TS U2127 ( .A(intadd_1159_SUM_0_), .B(intadd_1160_SUM_0_), .Y(n1528)
);
INVX2TS U2128 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[13]), .Y(
n1098) );
NAND2X1TS U2129 ( .A(n1098), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[13]), .Y(
n1843) );
INVX2TS U2130 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[12]), .Y(
n1095) );
NOR2X2TS U2131 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[12]), .B(
n1095), .Y(n1097) );
INVX2TS U2132 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[11]), .Y(
n1838) );
NAND2X2TS U2133 ( .A(intadd_1145_n1), .B(n1520), .Y(n1519) );
NOR2BX1TS U2134 ( .AN(n1097), .B(n1519), .Y(n1099) );
AOI21X1TS U2135 ( .A0(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[12]), .A1(
n1095), .B0(n1097), .Y(n1522) );
OAI211X1TS U2136 ( .A0(intadd_1145_n1), .A1(n1520), .B0(n1522), .C0(n1519),
.Y(n1521) );
AOI21X1TS U2137 ( .A0(n1097), .A1(n1519), .B0(n1096), .Y(n1841) );
OAI21X1TS U2138 ( .A0(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[13]), .A1(
n1098), .B0(n1843), .Y(n1840) );
NOR2X1TS U2139 ( .A(n1841), .B(n1840), .Y(n1839) );
NOR2X1TS U2140 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[15]), .B(
n1100), .Y(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[16])
);
NAND2X1TS U2141 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[8]), .B(
intadd_1142_n1), .Y(n1574) );
INVX2TS U2142 ( .A(n1576), .Y(n1575) );
XOR2X1TS U2143 ( .A(n1101), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[11]), .Y(
intadd_1139_A_10_) );
INVX2TS U2144 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[7]), .Y(n1655) );
NOR2X1TS U2145 ( .A(n1655), .B(intadd_1145_SUM_0_), .Y(
DP_OP_499J326_125_1651_n81) );
NAND3X1TS U2146 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]), .B(
intadd_1144_n1), .C(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]), .Y(n1240)
);
NOR2X1TS U2147 ( .A(n1240), .B(n2745), .Y(n1675) );
AO21X1TS U2148 ( .A0(n1240), .A1(n2745), .B0(n1675), .Y(
DP_OP_499J326_125_1651_n119) );
CLKBUFX2TS U2149 ( .A(n2728), .Y(n1104) );
CLKBUFX2TS U2150 ( .A(n1102), .Y(n2710) );
BUFX3TS U2151 ( .A(n917), .Y(n2699) );
BUFX3TS U2152 ( .A(n918), .Y(n2701) );
BUFX3TS U2153 ( .A(n917), .Y(n2700) );
INVX4TS U2154 ( .A(n1103), .Y(n2725) );
BUFX3TS U2155 ( .A(n2704), .Y(n2705) );
BUFX3TS U2156 ( .A(n2685), .Y(n2692) );
BUFX3TS U2157 ( .A(n2681), .Y(n2691) );
BUFX3TS U2158 ( .A(n2678), .Y(n2676) );
BUFX3TS U2159 ( .A(n2707), .Y(n2713) );
BUFX3TS U2160 ( .A(n910), .Y(n2679) );
BUFX3TS U2161 ( .A(n913), .Y(n2680) );
NAND2X1TS U2162 ( .A(n2462), .B(n2630), .Y(FPADDSUB__6_net_) );
NOR2X1TS U2163 ( .A(FPMULT_Exp_module_Overflow_flag_A), .B(
FPMULT_exp_oper_result[8]), .Y(n2152) );
OR2X1TS U2164 ( .A(n1245), .B(FPMULT_exp_oper_result[5]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[5]) );
OR2X1TS U2165 ( .A(n1245), .B(FPMULT_exp_oper_result[7]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[7]) );
OR2X1TS U2166 ( .A(n1245), .B(FPMULT_exp_oper_result[1]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[1]) );
OR2X1TS U2167 ( .A(n1245), .B(FPMULT_exp_oper_result[3]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[3]) );
OR2X1TS U2168 ( .A(n1245), .B(FPMULT_exp_oper_result[2]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[2]) );
OR2X1TS U2169 ( .A(n1245), .B(FPMULT_exp_oper_result[6]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[6]) );
OR2X1TS U2170 ( .A(n1245), .B(FPMULT_exp_oper_result[0]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[0]) );
OR2X1TS U2171 ( .A(n1245), .B(FPMULT_exp_oper_result[4]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[4]) );
NOR3XLTS U2172 ( .A(FPSENCOS_cont_var_out_1_), .B(n1106), .C(n930), .Y(
FPSENCOS_enab_d_ff4_Yn) );
NAND2X1TS U2173 ( .A(n2435), .B(n908), .Y(n1246) );
NAND2X1TS U2174 ( .A(FPSENCOS_cont_iter_out[2]), .B(n2435), .Y(n1262) );
OA21XLTS U2175 ( .A0(FPSENCOS_cont_iter_out[2]), .A1(n2435), .B0(n1262), .Y(
FPSENCOS_ITER_CONT_N4) );
NAND2X2TS U2176 ( .A(FPSENCOS_cont_iter_out[3]), .B(
FPSENCOS_cont_iter_out[2]), .Y(n863) );
NOR2X1TS U2177 ( .A(n2473), .B(n1740), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N0) );
NAND3X1TS U2178 ( .A(FPMULT_Op_MX[1]), .B(FPMULT_Op_MY[1]), .C(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N0), .Y(n1311) );
INVX2TS U2179 ( .A(n1311), .Y(n1254) );
OAI32X1TS U2180 ( .A0(n1254), .A1(n2540), .A2(n1740), .B0(FPMULT_Op_MX[2]),
.B1(n1311), .Y(n1108) );
NAND2X1TS U2181 ( .A(FPMULT_Op_MX[1]), .B(FPMULT_Op_MY[1]), .Y(n1312) );
NAND2X1TS U2182 ( .A(FPMULT_Op_MX[0]), .B(FPMULT_Op_MY[2]), .Y(n1313) );
XOR2X1TS U2183 ( .A(n1312), .B(n1313), .Y(n1107) );
NAND2X1TS U2184 ( .A(n1108), .B(n1107), .Y(n1310) );
OA21XLTS U2185 ( .A0(n1108), .A1(n1107), .B0(n1310), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2) );
OAI21X1TS U2186 ( .A0(n2102), .A1(n2309), .B0(n1635), .Y(
FPMULT_FSM_load_second_step) );
OR2X1TS U2187 ( .A(n2790), .B(FPMULT_FSM_load_second_step), .Y(
FPMULT_FSM_exp_operation_load_result) );
INVX2TS U2188 ( .A(DP_OP_502J326_128_4510_n32), .Y(
DP_OP_502J326_128_4510_n27) );
NOR2X1TS U2189 ( .A(n1777), .B(n1782), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N0) );
NAND3X1TS U2190 ( .A(FPMULT_Op_MX[13]), .B(n959), .C(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N0), .Y(n1353) );
INVX2TS U2191 ( .A(n1353), .Y(n1264) );
OAI32X1TS U2192 ( .A0(n1264), .A1(n2541), .A2(n1782), .B0(FPMULT_Op_MX[14]),
.B1(n1353), .Y(n1110) );
NAND2X1TS U2193 ( .A(FPMULT_Op_MX[13]), .B(n959), .Y(n1354) );
NAND2X1TS U2194 ( .A(FPMULT_Op_MX[12]), .B(FPMULT_Op_MY[14]), .Y(n1355) );
XOR2X1TS U2195 ( .A(n1354), .B(n1355), .Y(n1109) );
NAND2X1TS U2196 ( .A(n1110), .B(n1109), .Y(n1352) );
OA21XLTS U2197 ( .A0(n1110), .A1(n1109), .B0(n1352), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2) );
NOR2XLTS U2198 ( .A(n2474), .B(n2550), .Y(n1113) );
AOI22X1TS U2199 ( .A0(FPMULT_Op_MX[20]), .A1(FPMULT_Op_MY[22]), .B0(
FPMULT_Op_MX[22]), .B1(FPMULT_Op_MY[20]), .Y(n1111) );
AOI21X1TS U2200 ( .A0(mult_x_309_n52), .A1(mult_x_309_n66), .B0(n1111), .Y(
n1112) );
NAND3XLTS U2201 ( .A(FPMULT_Op_MX[21]), .B(FPMULT_Op_MY[21]), .C(n1112), .Y(
n1723) );
OA21XLTS U2202 ( .A0(n1113), .A1(n1112), .B0(n1723), .Y(mult_x_309_n25) );
NOR2X1TS U2203 ( .A(n2480), .B(n2551), .Y(mult_x_310_n71) );
NOR2XLTS U2204 ( .A(n2478), .B(n2472), .Y(n1117) );
INVX2TS U2205 ( .A(n1738), .Y(n1115) );
AOI22X1TS U2206 ( .A0(FPMULT_Op_MX[1]), .A1(FPMULT_Op_MY[5]), .B0(
FPMULT_Op_MX[2]), .B1(FPMULT_Op_MY[4]), .Y(n1114) );
AOI21X1TS U2207 ( .A0(mult_x_310_n71), .A1(n1115), .B0(n1114), .Y(n1116) );
NAND3XLTS U2208 ( .A(FPMULT_Op_MX[3]), .B(FPMULT_Op_MY[3]), .C(n1116), .Y(
n1735) );
OA21XLTS U2209 ( .A0(n1117), .A1(n1116), .B0(n1735), .Y(mult_x_310_n25) );
NOR2X1TS U2210 ( .A(n2481), .B(n2553), .Y(mult_x_312_n71) );
INVX2TS U2211 ( .A(n1776), .Y(n1119) );
AOI22X1TS U2212 ( .A0(FPMULT_Op_MY[17]), .A1(FPMULT_Op_MX[13]), .B0(
FPMULT_Op_MX[14]), .B1(FPMULT_Op_MY[16]), .Y(n1118) );
AOI21X1TS U2213 ( .A0(mult_x_312_n71), .A1(n1119), .B0(n1118), .Y(n1120) );
NAND3XLTS U2214 ( .A(FPMULT_Op_MX[15]), .B(FPMULT_Op_MY[15]), .C(n1120), .Y(
n1772) );
OA21XLTS U2215 ( .A0(n1121), .A1(n1120), .B0(n1772), .Y(mult_x_312_n25) );
NOR2X1TS U2216 ( .A(n2498), .B(n2552), .Y(mult_x_311_n71) );
NOR2XLTS U2217 ( .A(n2493), .B(n2470), .Y(n1125) );
INVX2TS U2218 ( .A(n1757), .Y(n1123) );
AOI22X1TS U2219 ( .A0(FPMULT_Op_MY[11]), .A1(FPMULT_Op_MX[7]), .B0(
FPMULT_Op_MX[8]), .B1(FPMULT_Op_MY[10]), .Y(n1122) );
AOI21X1TS U2220 ( .A0(mult_x_311_n71), .A1(n1123), .B0(n1122), .Y(n1124) );
NAND3XLTS U2221 ( .A(FPMULT_Op_MX[9]), .B(FPMULT_Op_MY[9]), .C(n1124), .Y(
n1753) );
OA21XLTS U2222 ( .A0(n1125), .A1(n1124), .B0(n1753), .Y(mult_x_311_n25) );
NOR2XLTS U2223 ( .A(n2478), .B(n2499), .Y(n1129) );
NOR3X1TS U2224 ( .A(n2473), .B(n2472), .C(n1738), .Y(n1127) );
NAND2X1TS U2225 ( .A(FPMULT_Op_MX[2]), .B(FPMULT_Op_MY[3]), .Y(n1126) );
NAND3XLTS U2226 ( .A(FPMULT_Op_MX[3]), .B(FPMULT_Op_MY[2]), .C(n1128), .Y(
n1737) );
OA21XLTS U2227 ( .A0(n1129), .A1(n1128), .B0(n1737), .Y(mult_x_310_n32) );
NOR2X1TS U2228 ( .A(n2474), .B(n2548), .Y(mult_x_309_n58) );
INVX2TS U2229 ( .A(n1725), .Y(n1716) );
AOI22X1TS U2230 ( .A0(FPMULT_Op_MX[21]), .A1(FPMULT_Op_MY[20]), .B0(
FPMULT_Op_MX[19]), .B1(FPMULT_Op_MY[22]), .Y(n1130) );
AOI21X1TS U2231 ( .A0(mult_x_309_n58), .A1(n1716), .B0(n1130), .Y(n1131) );
NAND3XLTS U2232 ( .A(FPMULT_Op_MX[22]), .B(FPMULT_Op_MY[19]), .C(n1131), .Y(
n1724) );
OA21XLTS U2233 ( .A0(n1132), .A1(n1131), .B0(n1724), .Y(mult_x_309_n32) );
NAND3XLTS U2234 ( .A(FPMULT_Op_MX[5]), .B(FPMULT_Op_MY[2]), .C(n1133), .Y(
n1733) );
OA21XLTS U2235 ( .A0(n1134), .A1(n1133), .B0(n1733), .Y(mult_x_310_n20) );
NAND3XLTS U2236 ( .A(FPMULT_Op_MX[17]), .B(FPMULT_Op_MY[14]), .C(n1135), .Y(
n1770) );
OA21XLTS U2237 ( .A0(n1136), .A1(n1135), .B0(n1770), .Y(mult_x_312_n20) );
NAND3XLTS U2238 ( .A(FPMULT_Op_MX[11]), .B(FPMULT_Op_MY[8]), .C(n1137), .Y(
n1751) );
OA21XLTS U2239 ( .A0(n1138), .A1(n1137), .B0(n1751), .Y(mult_x_311_n20) );
NOR2BX2TS U2240 ( .AN(n961), .B(n1139), .Y(n1187) );
OR2X2TS U2241 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(n2599), .Y(n1189)
);
NAND2X1TS U2242 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(n2599), .Y(n1154)
);
OAI22X1TS U2243 ( .A0(n1189), .A1(n2622), .B0(n1154), .B1(n1197), .Y(n1141)
);
NOR2XLTS U2244 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(n1154), .Y(n1142)
);
AOI22X1TS U2245 ( .A0(n1290), .A1(n958), .B0(n1143), .B1(
FPADDSUB_Data_array_SWR[31]), .Y(n1146) );
AND2X4TS U2246 ( .A(n1139), .B(n1293), .Y(n1289) );
AOI22X1TS U2247 ( .A0(n1144), .A1(FPADDSUB_Data_array_SWR[38]), .B0(n1289),
.B1(FPADDSUB_Data_array_SWR[27]), .Y(n1145) );
OAI211X1TS U2248 ( .A0(n1207), .A1(n1293), .B0(n1146), .C0(n1145), .Y(n1266)
);
NOR2X4TS U2249 ( .A(n1305), .B(n1170), .Y(n1303) );
AOI21X1TS U2250 ( .A0(n1305), .A1(n1266), .B0(n1303), .Y(n1147) );
OAI21X1TS U2251 ( .A0(n1268), .A1(n1140), .B0(n1147), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[24]) );
NOR2XLTS U2252 ( .A(n2783), .B(n2784), .Y(n1148) );
CLKAND2X2TS U2253 ( .A(n2291), .B(FPADDSUB_sftr_odat_SHT2_SWR[24]), .Y(
FPADDSUB_formatted_number_W[22]) );
AOI22X1TS U2254 ( .A0(n1290), .A1(FPADDSUB_Data_array_SWR[38]), .B0(n1144),
.B1(FPADDSUB_Data_array_SWR[42]), .Y(n1152) );
AOI22X1TS U2255 ( .A0(n1143), .A1(n958), .B0(n1289), .B1(
FPADDSUB_Data_array_SWR[31]), .Y(n1151) );
OAI211X1TS U2256 ( .A0(n1298), .A1(n1293), .B0(n1152), .C0(n1151), .Y(n1185)
);
AOI21X1TS U2257 ( .A0(n1305), .A1(n1185), .B0(n1303), .Y(n1153) );
OAI21X1TS U2258 ( .A0(n1283), .A1(n1140), .B0(n1153), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[20]) );
CLKAND2X2TS U2259 ( .A(n2291), .B(FPADDSUB_sftr_odat_SHT2_SWR[20]), .Y(
FPADDSUB_formatted_number_W[18]) );
OAI22X1TS U2260 ( .A0(n1189), .A1(n2629), .B0(n1154), .B1(n2516), .Y(n1155)
);
AOI22X1TS U2261 ( .A0(n1143), .A1(FPADDSUB_Data_array_SWR[38]), .B0(n1144),
.B1(FPADDSUB_Data_array_SWR[46]), .Y(n1157) );
AOI22X1TS U2262 ( .A0(n1290), .A1(FPADDSUB_Data_array_SWR[42]), .B0(n1289),
.B1(n958), .Y(n1156) );
OAI211X1TS U2263 ( .A0(n948), .A1(n1293), .B0(n1157), .C0(n1156), .Y(n1172)
);
AOI21X1TS U2264 ( .A0(n1305), .A1(n1172), .B0(n1303), .Y(n1158) );
OAI21X1TS U2265 ( .A0(n1271), .A1(n1140), .B0(n1158), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[16]) );
CLKAND2X2TS U2266 ( .A(n2291), .B(FPADDSUB_sftr_odat_SHT2_SWR[16]), .Y(
FPADDSUB_formatted_number_W[14]) );
AOI22X1TS U2267 ( .A0(n1144), .A1(FPADDSUB_Data_array_SWR[39]), .B0(n1289),
.B1(FPADDSUB_Data_array_SWR[28]), .Y(n1161) );
AOI22X1TS U2268 ( .A0(n1290), .A1(FPADDSUB_Data_array_SWR[35]), .B0(n1143),
.B1(FPADDSUB_Data_array_SWR[32]), .Y(n1160) );
OAI211X1TS U2269 ( .A0(n1307), .A1(n1293), .B0(n1161), .C0(n1160), .Y(n1181)
);
AOI21X1TS U2270 ( .A0(n1305), .A1(n1181), .B0(n1303), .Y(n1162) );
OAI21X1TS U2271 ( .A0(n1294), .A1(n1140), .B0(n1162), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[23]) );
CLKAND2X2TS U2272 ( .A(n2291), .B(FPADDSUB_sftr_odat_SHT2_SWR[23]), .Y(
FPADDSUB_formatted_number_W[21]) );
INVX2TS U2273 ( .A(n1170), .Y(n1200) );
AOI22X1TS U2274 ( .A0(n1143), .A1(FPADDSUB_Data_array_SWR[40]), .B0(n1289),
.B1(FPADDSUB_Data_array_SWR[36]), .Y(n1163) );
OAI21XLTS U2275 ( .A0(n1198), .A1(n2619), .B0(n1163), .Y(n1164) );
NAND2BXLTS U2276 ( .AN(n1165), .B(n1170), .Y(n1175) );
AO22XLTS U2277 ( .A0(FPADDSUB_Data_array_SWR[43]), .A1(n1143), .B0(
FPADDSUB_Data_array_SWR[39]), .B1(n1289), .Y(n1166) );
AOI211X1TS U2278 ( .A0(FPADDSUB_Data_array_SWR[47]), .A1(n1290), .B0(n1175),
.C0(n1166), .Y(n1168) );
AOI22X1TS U2279 ( .A0(n1305), .A1(n1167), .B0(n1168), .B1(n1300), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[14]) );
CLKAND2X2TS U2280 ( .A(n2291), .B(FPADDSUB_sftr_odat_SHT2_SWR[14]), .Y(
FPADDSUB_formatted_number_W[12]) );
AOI22X1TS U2281 ( .A0(n1305), .A1(n1168), .B0(n1167), .B1(n1300), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[11]) );
CLKAND2X2TS U2282 ( .A(n2291), .B(FPADDSUB_sftr_odat_SHT2_SWR[11]), .Y(
FPADDSUB_formatted_number_W[9]) );
AOI21X1TS U2283 ( .A0(n1300), .A1(n1172), .B0(n1171), .Y(n1173) );
OAI21X1TS U2284 ( .A0(n1271), .A1(n1169), .B0(n1173), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[9]) );
CLKAND2X2TS U2285 ( .A(n2291), .B(FPADDSUB_sftr_odat_SHT2_SWR[9]), .Y(
FPADDSUB_formatted_number_W[7]) );
AO22XLTS U2286 ( .A0(n1143), .A1(FPADDSUB_Data_array_SWR[44]), .B0(n1289),
.B1(FPADDSUB_Data_array_SWR[40]), .Y(n1174) );
AOI211X1TS U2287 ( .A0(n1290), .A1(FPADDSUB_Data_array_SWR[48]), .B0(n1175),
.C0(n1174), .Y(n1183) );
AOI22X1TS U2288 ( .A0(FPADDSUB_Data_array_SWR[43]), .A1(n1290), .B0(
FPADDSUB_Data_array_SWR[35]), .B1(n1289), .Y(n1176) );
OAI21XLTS U2289 ( .A0(n2617), .A1(n1198), .B0(n1176), .Y(n1177) );
AOI22X1TS U2290 ( .A0(n1305), .A1(n1183), .B0(n1184), .B1(n1300), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[10]) );
CLKAND2X2TS U2291 ( .A(n2291), .B(FPADDSUB_sftr_odat_SHT2_SWR[10]), .Y(
FPADDSUB_formatted_number_W[8]) );
AOI22X1TS U2292 ( .A0(n1290), .A1(FPADDSUB_Data_array_SWR[41]), .B0(n1144),
.B1(FPADDSUB_Data_array_SWR[45]), .Y(n1179) );
AOI22X1TS U2293 ( .A0(n1143), .A1(FPADDSUB_Data_array_SWR[37]), .B0(n1289),
.B1(FPADDSUB_Data_array_SWR[34]), .Y(n1178) );
OAI211X1TS U2294 ( .A0(n1268), .A1(n1293), .B0(n1179), .C0(n1178), .Y(n1205)
);
AOI21X1TS U2295 ( .A0(n1305), .A1(n1205), .B0(n1303), .Y(n1180) );
OAI21X1TS U2296 ( .A0(n1207), .A1(n1140), .B0(n1180), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[17]) );
CLKAND2X2TS U2297 ( .A(n2291), .B(FPADDSUB_sftr_odat_SHT2_SWR[17]), .Y(
FPADDSUB_formatted_number_W[15]) );
AOI21X1TS U2298 ( .A0(n1300), .A1(n1181), .B0(n1171), .Y(n1182) );
OAI21X1TS U2299 ( .A0(n1294), .A1(n1169), .B0(n1182), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[2]) );
CLKAND2X2TS U2300 ( .A(n2291), .B(FPADDSUB_sftr_odat_SHT2_SWR[2]), .Y(
FPADDSUB_formatted_number_W[0]) );
AOI22X1TS U2301 ( .A0(n1305), .A1(n1184), .B0(n1183), .B1(n1300), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[15]) );
CLKAND2X2TS U2302 ( .A(n2291), .B(FPADDSUB_sftr_odat_SHT2_SWR[15]), .Y(
FPADDSUB_formatted_number_W[13]) );
AOI21X1TS U2303 ( .A0(n1300), .A1(n1185), .B0(n1171), .Y(n1186) );
OAI21X1TS U2304 ( .A0(n1283), .A1(n1169), .B0(n1186), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[5]) );
CLKAND2X2TS U2305 ( .A(n2291), .B(FPADDSUB_sftr_odat_SHT2_SWR[5]), .Y(
FPADDSUB_formatted_number_W[3]) );
AOI22X1TS U2306 ( .A0(n1144), .A1(FPADDSUB_Data_array_SWR[40]), .B0(n1289),
.B1(FPADDSUB_Data_array_SWR[29]), .Y(n1192) );
AOI22X1TS U2307 ( .A0(n1290), .A1(FPADDSUB_Data_array_SWR[36]), .B0(n1143),
.B1(FPADDSUB_Data_array_SWR[33]), .Y(n1191) );
OAI211X1TS U2308 ( .A0(n1302), .A1(n1293), .B0(n1192), .C0(n1191), .Y(n1203)
);
AOI21X1TS U2309 ( .A0(n1305), .A1(n1203), .B0(n1303), .Y(n1193) );
OAI21X1TS U2310 ( .A0(n1287), .A1(n1140), .B0(n1193), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[22]) );
CLKAND2X2TS U2311 ( .A(n2291), .B(FPADDSUB_sftr_odat_SHT2_SWR[22]), .Y(
FPADDSUB_formatted_number_W[20]) );
AOI22X1TS U2312 ( .A0(n1290), .A1(FPADDSUB_Data_array_SWR[45]), .B0(n1289),
.B1(FPADDSUB_Data_array_SWR[37]), .Y(n1194) );
OAI21XLTS U2313 ( .A0(n1198), .A1(n2516), .B0(n1194), .Y(n1195) );
AOI22X1TS U2314 ( .A0(n1290), .A1(FPADDSUB_Data_array_SWR[46]), .B0(n1289),
.B1(FPADDSUB_Data_array_SWR[38]), .Y(n1196) );
OAI21XLTS U2315 ( .A0(n1198), .A1(n1197), .B0(n1196), .Y(n1199) );
AOI22X1TS U2316 ( .A0(n1305), .A1(n1201), .B0(n1202), .B1(n1300), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[13]) );
CLKAND2X2TS U2317 ( .A(n2291), .B(FPADDSUB_sftr_odat_SHT2_SWR[13]), .Y(
FPADDSUB_formatted_number_W[11]) );
AOI22X1TS U2318 ( .A0(n1305), .A1(n1202), .B0(n1201), .B1(n1300), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[12]) );
CLKAND2X2TS U2319 ( .A(n2291), .B(FPADDSUB_sftr_odat_SHT2_SWR[12]), .Y(
FPADDSUB_formatted_number_W[10]) );
AOI21X1TS U2320 ( .A0(n1300), .A1(n1203), .B0(n1171), .Y(n1204) );
OAI21X1TS U2321 ( .A0(n1287), .A1(n1169), .B0(n1204), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[3]) );
CLKAND2X2TS U2322 ( .A(n2291), .B(FPADDSUB_sftr_odat_SHT2_SWR[3]), .Y(
FPADDSUB_formatted_number_W[1]) );
AOI21X1TS U2323 ( .A0(n1300), .A1(n1205), .B0(n1171), .Y(n1206) );
OAI21X1TS U2324 ( .A0(n1207), .A1(n1169), .B0(n1206), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[8]) );
CLKAND2X2TS U2325 ( .A(n2291), .B(FPADDSUB_sftr_odat_SHT2_SWR[8]), .Y(
FPADDSUB_formatted_number_W[6]) );
OA21XLTS U2326 ( .A0(n1210), .A1(n1209), .B0(n1208), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N2) );
OR2X1TS U2327 ( .A(n1211), .B(intadd_1157_n1), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N11) );
OAI2BB1X1TS U2328 ( .A0N(intadd_1157_n1), .A1N(n1211), .B0(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N11), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10) );
OA21XLTS U2329 ( .A0(n1214), .A1(n1213), .B0(n1212), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N2) );
NAND2X1TS U2330 ( .A(n1216), .B(n956), .Y(n1343) );
INVX2TS U2331 ( .A(n1343), .Y(n1218) );
OAI31X1TS U2332 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[4]), .A1(
FPADDSUB_Raw_mant_NRM_SWR[0]), .A2(n1218), .B0(n1217), .Y(n1219) );
NAND3BXLTS U2333 ( .AN(n1221), .B(n1220), .C(n1219), .Y(
FPADDSUB_LZD_raw_out_EWR[4]) );
NOR2X1TS U2334 ( .A(n1226), .B(n1906), .Y(DP_OP_501J326_127_5235_n59) );
NOR2XLTS U2335 ( .A(n1226), .B(n1900), .Y(DP_OP_501J326_127_5235_n77) );
NOR2X1TS U2336 ( .A(n1226), .B(n1631), .Y(DP_OP_501J326_127_5235_n53) );
NOR4X1TS U2337 ( .A(FPMULT_Sgf_operation_Result[15]), .B(
FPMULT_Sgf_operation_Result[19]), .C(FPMULT_Sgf_operation_Result[13]),
.D(FPMULT_Sgf_operation_Result[22]), .Y(n1225) );
NOR3XLTS U2338 ( .A(FPMULT_Sgf_operation_Result[8]), .B(
FPMULT_Sgf_operation_Result[17]), .C(FPMULT_Sgf_operation_Result[16]),
.Y(n1224) );
NOR4X1TS U2339 ( .A(FPMULT_Sgf_operation_Result[3]), .B(
FPMULT_Sgf_operation_Result[5]), .C(FPMULT_Sgf_operation_Result[21]),
.D(FPMULT_Sgf_operation_Result[0]), .Y(n1223) );
NOR4X1TS U2340 ( .A(FPMULT_Sgf_operation_Result[4]), .B(
FPMULT_Sgf_operation_Result[18]), .C(FPMULT_Sgf_operation_Result[20]),
.D(FPMULT_Sgf_operation_Result[1]), .Y(n1222) );
AND4X1TS U2341 ( .A(n1225), .B(n1224), .C(n1223), .D(n1222), .Y(n2663) );
NOR2X1TS U2342 ( .A(n1805), .B(n1806), .Y(mult_x_313_n56) );
INVX2TS U2343 ( .A(n1226), .Y(intadd_1159_A_3_) );
INVX2TS U2344 ( .A(intadd_1148_SUM_8_), .Y(n1907) );
AOI22X1TS U2345 ( .A0(intadd_1147_SUM_8_), .A1(intadd_1159_A_3_), .B0(
intadd_1147_SUM_7_), .B1(intadd_1159_A_4_), .Y(n1227) );
AOI21X1TS U2346 ( .A0(DP_OP_501J326_127_5235_n71), .A1(n1228), .B0(n1227),
.Y(n1894) );
NAND2X1TS U2347 ( .A(n1908), .B(n1894), .Y(n1893) );
OAI2BB1X1TS U2348 ( .A0N(DP_OP_501J326_127_5235_n71), .A1N(n1228), .B0(n1893), .Y(DP_OP_501J326_127_5235_n24) );
NOR2XLTS U2349 ( .A(n1901), .B(n1899), .Y(intadd_1149_B_8_) );
OAI21X4TS U2350 ( .A0(FPMULT_Op_MX[17]), .A1(intadd_1163_n1), .B0(n1851),
.Y(n1860) );
NAND2X1TS U2351 ( .A(n1860), .B(n1482), .Y(n1491) );
OR2X1TS U2352 ( .A(n1469), .B(n1491), .Y(intadd_1152_A_0_) );
AOI22X1TS U2353 ( .A0(intadd_1160_SUM_2_), .A1(intadd_1159_SUM_4_), .B0(
intadd_1160_SUM_0_), .B1(n1229), .Y(n1230) );
AOI21X1TS U2354 ( .A0(DP_OP_501J326_127_5235_n209), .A1(
DP_OP_501J326_127_5235_n227), .B0(n1230), .Y(n1232) );
NAND3XLTS U2355 ( .A(intadd_1159_SUM_2_), .B(intadd_1160_SUM_4_), .C(n1232),
.Y(n1231) );
OAI2BB1X1TS U2356 ( .A0N(DP_OP_501J326_127_5235_n209), .A1N(
DP_OP_501J326_127_5235_n227), .B0(n1231), .Y(
DP_OP_501J326_127_5235_n137) );
NOR2X1TS U2357 ( .A(n2473), .B(n2484), .Y(intadd_1161_CI) );
OA21XLTS U2358 ( .A0(n1233), .A1(n1232), .B0(n1231), .Y(
DP_OP_501J326_127_5235_n138) );
INVX2TS U2359 ( .A(intadd_1147_SUM_4_), .Y(n1811) );
AOI22X1TS U2360 ( .A0(intadd_1148_SUM_0_), .A1(n1811), .B0(
intadd_1147_SUM_4_), .B1(n1807), .Y(n1789) );
INVX2TS U2361 ( .A(intadd_1147_SUM_3_), .Y(n1234) );
OAI33X4TS U2362 ( .A0(n1821), .A1(n1234), .A2(intadd_1147_SUM_4_), .B0(n1811), .B1(intadd_1147_SUM_3_), .B2(intadd_1147_SUM_2_), .Y(n1814) );
INVX2TS U2363 ( .A(n1814), .Y(n1790) );
INVX2TS U2364 ( .A(n1788), .Y(n1816) );
INVX2TS U2365 ( .A(intadd_1148_SUM_1_), .Y(n1784) );
AOI22X1TS U2366 ( .A0(intadd_1148_SUM_1_), .A1(intadd_1147_SUM_4_), .B0(
n1811), .B1(n1784), .Y(n1813) );
OAI2BB2XLTS U2367 ( .B0(n1789), .B1(n1790), .A0N(n1816), .A1N(n1813), .Y(
mult_x_313_n62) );
NAND2X1TS U2368 ( .A(intadd_1160_SUM_4_), .B(n1517), .Y(n1236) );
NAND2X1TS U2369 ( .A(n1236), .B(n1235), .Y(DP_OP_501J326_127_5235_n147) );
AOI31X1TS U2370 ( .A0(n1239), .A1(n1238), .A2(n1237), .B0(
DP_OP_501J326_127_5235_n115), .Y(DP_OP_501J326_127_5235_n116) );
INVX2TS U2371 ( .A(DP_OP_501J326_127_5235_n109), .Y(n1909) );
OAI21X4TS U2372 ( .A0(intadd_1159_n1), .A1(intadd_1148_SUM_5_), .B0(n1919),
.Y(n1628) );
OA22X1TS U2373 ( .A0(n1919), .A1(n1518), .B0(n1630), .B1(n1628), .Y(n1910)
);
NOR2X1TS U2374 ( .A(n1909), .B(n1910), .Y(intadd_1141_A_12_) );
NOR2X1TS U2375 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[1]), .B(
n2772), .Y(intadd_1145_A_2_) );
OAI2BB1X1TS U2376 ( .A0N(n1241), .A1N(n2771), .B0(n1240), .Y(
DP_OP_499J326_125_1651_n120) );
OAI21X1TS U2377 ( .A0(n1651), .A1(n928), .B0(n1243), .Y(n1244) );
NAND2X1TS U2378 ( .A(intadd_1146_SUM_0_), .B(n1244), .Y(n1652) );
OA21XLTS U2379 ( .A0(intadd_1146_SUM_0_), .A1(n1244), .B0(n1652), .Y(
intadd_1144_B_1_) );
BUFX3TS U2380 ( .A(n910), .Y(n2693) );
BUFX3TS U2381 ( .A(n910), .Y(n2683) );
BUFX3TS U2382 ( .A(n910), .Y(n2688) );
INVX4TS U2383 ( .A(n1103), .Y(n2720) );
INVX4TS U2384 ( .A(n1103), .Y(n2719) );
BUFX3TS U2385 ( .A(n910), .Y(n2677) );
NAND2X1TS U2386 ( .A(n966), .B(FPADDSUB_DmP_EXP_EWSW[23]), .Y(intadd_1166_CI) );
OAI21XLTS U2387 ( .A0(FPADDSUB_DmP_EXP_EWSW[23]), .A1(n966), .B0(
intadd_1166_CI), .Y(FPADDSUB_Shift_amount_EXP_EW[0]) );
NOR2XLTS U2388 ( .A(n945), .B(n1245), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[1]) );
INVX2TS U2389 ( .A(FPMULT_Sgf_normalized_result[21]), .Y(n1680) );
INVX2TS U2390 ( .A(FPMULT_Sgf_normalized_result[5]), .Y(n1704) );
NOR2XLTS U2391 ( .A(n1704), .B(n1245), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[5]) );
INVX2TS U2392 ( .A(FPMULT_Sgf_normalized_result[7]), .Y(n1701) );
NOR2XLTS U2393 ( .A(n1701), .B(n1245), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[7]) );
INVX2TS U2394 ( .A(FPMULT_Sgf_normalized_result[3]), .Y(n1705) );
NOR2XLTS U2395 ( .A(n1705), .B(n1245), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[3]) );
NOR2XLTS U2396 ( .A(n927), .B(n1245), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[0]) );
INVX2TS U2397 ( .A(FPMULT_Sgf_normalized_result[15]), .Y(n1689) );
BUFX4TS U2398 ( .A(n1245), .Y(n2292) );
NOR2XLTS U2399 ( .A(n1689), .B(n2292), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[15]) );
INVX2TS U2400 ( .A(FPMULT_Sgf_normalized_result[17]), .Y(n1686) );
NOR2XLTS U2401 ( .A(n1686), .B(n2292), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[17]) );
INVX2TS U2402 ( .A(FPMULT_Sgf_normalized_result[13]), .Y(n1692) );
NOR2XLTS U2403 ( .A(n1692), .B(n2292), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[13]) );
INVX2TS U2404 ( .A(FPMULT_Sgf_normalized_result[11]), .Y(n1695) );
INVX2TS U2405 ( .A(FPMULT_Sgf_normalized_result[19]), .Y(n1683) );
NOR2XLTS U2406 ( .A(n1683), .B(n2292), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[19]) );
INVX2TS U2407 ( .A(FPMULT_Sgf_normalized_result[9]), .Y(n1698) );
NOR2XLTS U2408 ( .A(n1698), .B(n2292), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[9]) );
NAND2X1TS U2409 ( .A(n945), .B(n927), .Y(n1707) );
OAI21XLTS U2410 ( .A0(n927), .A1(n945), .B0(n1707), .Y(
FPMULT_Adder_M_result_A_adder[1]) );
NOR2X2TS U2411 ( .A(FPSENCOS_cont_iter_out[0]), .B(FPSENCOS_cont_iter_out[1]), .Y(n2153) );
NOR2XLTS U2412 ( .A(n2435), .B(n2153), .Y(FPSENCOS_ITER_CONT_N3) );
NAND2X1TS U2413 ( .A(n863), .B(FPSENCOS_cont_iter_out[0]), .Y(n2434) );
OAI21XLTS U2414 ( .A0(FPSENCOS_cont_iter_out[0]), .A1(n863), .B0(n2434), .Y(
n847) );
NAND2X1TS U2415 ( .A(FPSENCOS_cont_iter_out[3]), .B(n908), .Y(n1247) );
NAND2X1TS U2416 ( .A(n2153), .B(n2594), .Y(n2432) );
OAI211XLTS U2417 ( .A0(n2153), .A1(n1247), .B0(n2432), .C0(n1246), .Y(n853)
);
AOI22X1TS U2418 ( .A0(FPMULT_FSM_selector_C), .A1(FPMULT_Add_result[23]),
.B0(FPMULT_P_Sgf[46]), .B1(n2624), .Y(n2100) );
AOI21X1TS U2419 ( .A0(FPMULT_FS_Module_state_reg[0]), .A1(n2593), .B0(n1248),
.Y(n1250) );
NOR2XLTS U2420 ( .A(n1250), .B(n2624), .Y(n1249) );
NOR2XLTS U2421 ( .A(FPMULT_FSM_selector_C), .B(n1250), .Y(n1251) );
AOI22X1TS U2422 ( .A0(n2149), .A1(FPMULT_Add_result[22]), .B0(n2148), .B1(
FPMULT_P_Sgf[45]), .Y(n1252) );
OAI21XLTS U2423 ( .A0(n2100), .A1(n2102), .B0(n1252), .Y(n2815) );
NAND2X1TS U2424 ( .A(FPMULT_Op_MX[0]), .B(FPMULT_Op_MY[1]), .Y(n1253) );
OAI32X1TS U2425 ( .A0(n1254), .A1(n2480), .A2(n1740), .B0(n1253), .B1(n1254),
.Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N1) );
INVX2TS U2426 ( .A(n863), .Y(n2430) );
AOI22X1TS U2427 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(n908), .B0(
FPSENCOS_cont_iter_out[2]), .B1(n2594), .Y(n1255) );
OAI21XLTS U2428 ( .A0(n2430), .A1(n2482), .B0(n1255), .Y(n861) );
NOR2X2TS U2429 ( .A(n2487), .B(n2532), .Y(mult_x_309_n33) );
NOR2X2TS U2430 ( .A(n2494), .B(n2469), .Y(mult_x_309_n26) );
NAND2X1TS U2431 ( .A(mult_x_309_n33), .B(mult_x_309_n26), .Y(n1712) );
INVX2TS U2432 ( .A(n1712), .Y(n1713) );
NAND2X1TS U2433 ( .A(FPMULT_Op_MX[18]), .B(FPMULT_Op_MY[19]), .Y(n1256) );
OAI32X1TS U2434 ( .A0(n1713), .A1(n2494), .A2(n2532), .B0(n1256), .B1(n1713),
.Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N1) );
NOR2X1TS U2435 ( .A(n2478), .B(n2496), .Y(mult_x_310_n58) );
NOR2X1TS U2436 ( .A(n2495), .B(n2479), .Y(mult_x_312_n58) );
NOR2X1TS U2437 ( .A(n2542), .B(n2493), .Y(mult_x_311_n58) );
NAND2X1TS U2438 ( .A(n2521), .B(FPADDSUB_DmP_mant_SFG_SWR[2]), .Y(n1346) );
OAI21X1TS U2439 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[2]), .A1(n2521), .B0(n1346),
.Y(n1258) );
OAI21XLTS U2440 ( .A0(n1347), .A1(n963), .B0(n1258), .Y(n1257) );
OAI31X1TS U2441 ( .A0(n1347), .A1(n1258), .A2(n963), .B0(n1257), .Y(
FPADDSUB_Raw_mant_SGF[2]) );
NOR2X1TS U2442 ( .A(n2546), .B(n2472), .Y(mult_x_310_n48) );
NOR2X1TS U2443 ( .A(n2488), .B(n2470), .Y(mult_x_311_n48) );
NOR2X1TS U2444 ( .A(n2547), .B(n2471), .Y(mult_x_312_n48) );
NOR2X1TS U2445 ( .A(n2484), .B(n1762), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N0) );
NAND3X1TS U2446 ( .A(FPMULT_Op_MX[7]), .B(FPMULT_Op_MY[7]), .C(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N0), .Y(n1337) );
INVX2TS U2447 ( .A(n1337), .Y(n1336) );
NAND2X1TS U2448 ( .A(FPMULT_Op_MX[6]), .B(FPMULT_Op_MY[7]), .Y(n1259) );
OAI32X1TS U2449 ( .A0(n1336), .A1(n2498), .A2(n1762), .B0(n1259), .B1(n1336),
.Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N1) );
NOR2X1TS U2450 ( .A(FPSENCOS_d_ff2_X[27]), .B(intadd_1164_n1), .Y(n2468) );
OR3X1TS U2451 ( .A(FPSENCOS_d_ff2_X[27]), .B(FPSENCOS_d_ff2_X[28]), .C(
intadd_1164_n1), .Y(n2467) );
OAI21XLTS U2452 ( .A0(n2468), .A1(n2658), .B0(n2467), .Y(
FPSENCOS_sh_exp_x[5]) );
NOR2X1TS U2453 ( .A(n964), .B(intadd_1165_n1), .Y(n2465) );
OR3X1TS U2454 ( .A(n964), .B(FPSENCOS_d_ff2_Y[28]), .C(intadd_1165_n1), .Y(
n2464) );
OAI21XLTS U2455 ( .A0(n2465), .A1(n2659), .B0(n2464), .Y(
FPSENCOS_sh_exp_y[5]) );
NOR2XLTS U2456 ( .A(n2430), .B(FPSENCOS_ITER_CONT_N4), .Y(
FPSENCOS_data_out_LUT[25]) );
NAND3XLTS U2457 ( .A(FPMULT_FS_Module_state_reg[0]), .B(n2308), .C(n2593),
.Y(n1260) );
OAI22X1TS U2458 ( .A0(FPMULT_P_Sgf[47]), .A1(n1260), .B0(FPMULT_zero_flag),
.B1(n1635), .Y(n1261) );
NOR2X1TS U2459 ( .A(n2478), .B(n2551), .Y(mult_x_310_n59) );
NOR2X1TS U2460 ( .A(n2479), .B(n2553), .Y(mult_x_312_n59) );
NOR2X1TS U2461 ( .A(n2493), .B(n2552), .Y(mult_x_311_n59) );
CLKAND2X2TS U2462 ( .A(n1262), .B(n2594), .Y(n855) );
NOR2XLTS U2463 ( .A(n936), .B(n855), .Y(FPSENCOS_ITER_CONT_N5) );
NOR2X1TS U2464 ( .A(FPSENCOS_cont_iter_out[2]), .B(n2432), .Y(n2295) );
CLKBUFX2TS U2465 ( .A(n2295), .Y(n2300) );
NOR2XLTS U2466 ( .A(n2430), .B(n914), .Y(n848) );
NAND4XLTS U2467 ( .A(FPMULT_FS_Module_state_reg[0]), .B(n2308), .C(
FPMULT_P_Sgf[47]), .D(n2593), .Y(n1650) );
OAI31X1TS U2468 ( .A0(n2790), .A1(FPMULT_FSM_adder_round_norm_load), .A2(
n2595), .B0(n1650), .Y(n830) );
NAND2X1TS U2469 ( .A(FPMULT_Op_MX[12]), .B(n959), .Y(n1263) );
OAI32X1TS U2470 ( .A0(n1264), .A1(n2481), .A2(n1782), .B0(n1263), .B1(n1264),
.Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N1) );
AOI21X1TS U2471 ( .A0(n2473), .A1(n2484), .B0(intadd_1161_CI), .Y(n1265) );
BUFX3TS U2472 ( .A(n1265), .Y(n1932) );
INVX2TS U2473 ( .A(n1932), .Y(n1986) );
INVX2TS U2474 ( .A(n2449), .Y(n1973) );
NOR2XLTS U2475 ( .A(n1986), .B(n1973), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N0) );
NOR2X1TS U2476 ( .A(n2477), .B(n2545), .Y(mult_x_311_n67) );
NOR2X1TS U2477 ( .A(n2541), .B(n2500), .Y(mult_x_312_n67) );
NOR2X1TS U2478 ( .A(n2540), .B(n2499), .Y(mult_x_310_n67) );
NOR2X1TS U2479 ( .A(n2492), .B(n2550), .Y(mult_x_309_n65) );
NOR2XLTS U2480 ( .A(n1880), .B(n1853), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N0) );
NOR2XLTS U2481 ( .A(n1828), .B(n1805), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N0) );
NOR2X1TS U2482 ( .A(n2480), .B(n2472), .Y(mult_x_310_n72) );
NOR2X1TS U2483 ( .A(n2481), .B(n2471), .Y(mult_x_312_n72) );
NOR2X1TS U2484 ( .A(n2498), .B(n2470), .Y(mult_x_311_n72) );
NOR2X1TS U2485 ( .A(n2494), .B(n2550), .Y(mult_x_309_n71) );
AOI21X1TS U2486 ( .A0(n1300), .A1(n1266), .B0(n1171), .Y(n1267) );
OAI21XLTS U2487 ( .A0(n1268), .A1(n1169), .B0(n1267), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[1]) );
AOI22X1TS U2488 ( .A0(n1143), .A1(FPADDSUB_Data_array_SWR[30]), .B0(n1144),
.B1(FPADDSUB_Data_array_SWR[37]), .Y(n1270) );
AOI22X1TS U2489 ( .A0(n1290), .A1(FPADDSUB_Data_array_SWR[34]), .B0(n1289),
.B1(FPADDSUB_Data_array_SWR[26]), .Y(n1269) );
OAI211X1TS U2490 ( .A0(n1271), .A1(n1293), .B0(n1270), .C0(n1269), .Y(n1273)
);
AOI21X1TS U2491 ( .A0(n1300), .A1(n1273), .B0(n1171), .Y(n1272) );
OAI21XLTS U2492 ( .A0(n948), .A1(n1169), .B0(n1272), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[0]) );
AOI21X1TS U2493 ( .A0(n1305), .A1(n1273), .B0(n1303), .Y(n1274) );
OAI21XLTS U2494 ( .A0(n948), .A1(n1140), .B0(n1274), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[25]) );
OR3X1TS U2495 ( .A(n1634), .B(n2626), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .Y(n1275) );
OAI21XLTS U2496 ( .A0(n936), .A1(n1276), .B0(n1275), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]) );
NAND2X1TS U2497 ( .A(FPMULT_Op_MX[5]), .B(FPMULT_Op_MY[1]), .Y(n1736) );
NOR3X2TS U2498 ( .A(n1740), .B(n2475), .C(n1736), .Y(mult_x_310_n33) );
OR2X1TS U2499 ( .A(n2783), .B(FPADDSUB_exp_rslt_NRM2_EW1[1]), .Y(
FPADDSUB_formatted_number_W[24]) );
OR2X1TS U2500 ( .A(n2783), .B(FPADDSUB_exp_rslt_NRM2_EW1[0]), .Y(
FPADDSUB_formatted_number_W[23]) );
OR2X1TS U2501 ( .A(n2783), .B(FPADDSUB_exp_rslt_NRM2_EW1[5]), .Y(
FPADDSUB_formatted_number_W[28]) );
OR2X1TS U2502 ( .A(n2783), .B(FPADDSUB_exp_rslt_NRM2_EW1[6]), .Y(
FPADDSUB_formatted_number_W[29]) );
OR2X1TS U2503 ( .A(n2783), .B(FPADDSUB_exp_rslt_NRM2_EW1[2]), .Y(
FPADDSUB_formatted_number_W[25]) );
OR2X1TS U2504 ( .A(n2783), .B(FPADDSUB_exp_rslt_NRM2_EW1[3]), .Y(
FPADDSUB_formatted_number_W[26]) );
OR2X1TS U2505 ( .A(n2783), .B(FPADDSUB_exp_rslt_NRM2_EW1[4]), .Y(
FPADDSUB_formatted_number_W[27]) );
NAND2X1TS U2506 ( .A(FPMULT_Op_MX[17]), .B(n959), .Y(n1773) );
NOR3X2TS U2507 ( .A(n1782), .B(n2476), .C(n1773), .Y(mult_x_312_n33) );
NAND2X1TS U2508 ( .A(FPMULT_Op_MX[11]), .B(FPMULT_Op_MY[7]), .Y(n1754) );
NOR3X2TS U2509 ( .A(n1762), .B(n2491), .C(n1754), .Y(mult_x_311_n33) );
NOR2XLTS U2510 ( .A(mult_x_313_n74), .B(n1805), .Y(n1278) );
AOI31XLTS U2511 ( .A0(intadd_1148_SUM_0_), .A1(n1510), .A2(n1278), .B0(n1277), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N1) );
OAI21XLTS U2512 ( .A0(DP_OP_500J326_126_4510_n27), .A1(n1853), .B0(n1280),
.Y(n1279) );
OAI31X1TS U2513 ( .A0(DP_OP_500J326_126_4510_n27), .A1(n1280), .A2(n1853),
.B0(n1279), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N1) );
AOI22X1TS U2514 ( .A0(n1290), .A1(FPADDSUB_Data_array_SWR[37]), .B0(n1144),
.B1(FPADDSUB_Data_array_SWR[41]), .Y(n1282) );
AOI22X1TS U2515 ( .A0(n1143), .A1(FPADDSUB_Data_array_SWR[34]), .B0(n1289),
.B1(FPADDSUB_Data_array_SWR[30]), .Y(n1281) );
OAI211X1TS U2516 ( .A0(n1283), .A1(n1293), .B0(n1282), .C0(n1281), .Y(n1296)
);
AOI21X1TS U2517 ( .A0(n1305), .A1(n1296), .B0(n1303), .Y(n1284) );
OAI21X1TS U2518 ( .A0(n1298), .A1(n1140), .B0(n1284), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[21]) );
AOI22X1TS U2519 ( .A0(n1290), .A1(FPADDSUB_Data_array_SWR[39]), .B0(
FPADDSUB_Data_array_SWR[32]), .B1(n1289), .Y(n1286) );
AOI22X1TS U2520 ( .A0(FPADDSUB_Data_array_SWR[43]), .A1(n1144), .B0(
FPADDSUB_Data_array_SWR[35]), .B1(n1143), .Y(n1285) );
OAI211X1TS U2521 ( .A0(n1287), .A1(n1293), .B0(n1286), .C0(n1285), .Y(n1299)
);
AOI21X1TS U2522 ( .A0(n1305), .A1(n1299), .B0(n1303), .Y(n1288) );
OAI21X1TS U2523 ( .A0(n1302), .A1(n1140), .B0(n1288), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[19]) );
AOI22X1TS U2524 ( .A0(n1143), .A1(FPADDSUB_Data_array_SWR[36]), .B0(n1144),
.B1(FPADDSUB_Data_array_SWR[44]), .Y(n1292) );
AOI22X1TS U2525 ( .A0(n1290), .A1(FPADDSUB_Data_array_SWR[40]), .B0(n1289),
.B1(FPADDSUB_Data_array_SWR[33]), .Y(n1291) );
OAI211X1TS U2526 ( .A0(n1294), .A1(n1293), .B0(n1292), .C0(n1291), .Y(n1304)
);
AOI21X1TS U2527 ( .A0(n1300), .A1(n1304), .B0(n1171), .Y(n1295) );
OAI21X1TS U2528 ( .A0(n1307), .A1(n1169), .B0(n1295), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[7]) );
AOI21X1TS U2529 ( .A0(n1300), .A1(n1296), .B0(n1171), .Y(n1297) );
OAI21X1TS U2530 ( .A0(n1298), .A1(n1169), .B0(n1297), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[4]) );
AOI21X1TS U2531 ( .A0(n1300), .A1(n1299), .B0(n1171), .Y(n1301) );
OAI21X1TS U2532 ( .A0(n1302), .A1(n1169), .B0(n1301), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[6]) );
AOI21X1TS U2533 ( .A0(n1305), .A1(n1304), .B0(n1303), .Y(n1306) );
OAI21X1TS U2534 ( .A0(n1307), .A1(n1140), .B0(n1306), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[18]) );
NOR2BX1TS U2535 ( .AN(FPADDSUB_LZD_output_NRM2_EW[3]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n1308) );
XOR2X1TS U2536 ( .A(n951), .B(n1308), .Y(DP_OP_26J326_129_1325_n15) );
NOR2BX1TS U2537 ( .AN(FPADDSUB_LZD_output_NRM2_EW[4]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n1309) );
XOR2X1TS U2538 ( .A(n951), .B(n1309), .Y(DP_OP_26J326_129_1325_n14) );
OAI21XLTS U2539 ( .A0(n1311), .A1(n2540), .B0(n1310), .Y(intadd_1155_CI) );
AOI211X1TS U2540 ( .A0(FPMULT_Op_MX[0]), .A1(FPMULT_Op_MY[1]), .B0(n2480),
.C0(n2499), .Y(n1729) );
NAND3XLTS U2541 ( .A(FPMULT_Op_MX[0]), .B(FPMULT_Op_MY[3]), .C(n1729), .Y(
n1728) );
INVX2TS U2542 ( .A(n1314), .Y(n1322) );
INVX2TS U2543 ( .A(n1315), .Y(n1320) );
INVX2TS U2544 ( .A(n1316), .Y(n1317) );
AOI22X1TS U2545 ( .A0(n1320), .A1(n1319), .B0(n1318), .B1(n1317), .Y(n1321)
);
OAI211X1TS U2546 ( .A0(n1324), .A1(n1323), .B0(n1322), .C0(n1321), .Y(
FPADDSUB_LZD_raw_out_EWR[2]) );
NAND2X1TS U2547 ( .A(n1932), .B(intadd_1158_SUM_2_), .Y(n1326) );
OAI211XLTS U2548 ( .A0(n1969), .A1(n1932), .B0(n1326), .C0(
DP_OP_502J326_128_4510_n32), .Y(n1325) );
OAI21X1TS U2549 ( .A0(DP_OP_502J326_128_4510_n32), .A1(n1326), .B0(n1325),
.Y(n1332) );
AOI32X4TS U2550 ( .A0(DP_OP_502J326_128_4510_n32), .A1(n1978), .A2(
intadd_1161_SUM_1_), .B0(n1327), .B1(intadd_1161_SUM_2_), .Y(n1981) );
AOI22X1TS U2551 ( .A0(intadd_1161_SUM_2_), .A1(n1973), .B0(n2449), .B1(n1978), .Y(n1939) );
AOI22X1TS U2552 ( .A0(intadd_1161_SUM_2_), .A1(n1971), .B0(
intadd_1158_SUM_0_), .B1(n1978), .Y(n1933) );
OAI22X1TS U2553 ( .A0(n1981), .A1(n1939), .B0(n1933), .B1(n1984), .Y(n1331)
);
AOI22X1TS U2554 ( .A0(n1932), .A1(intadd_1158_SUM_1_), .B0(
intadd_1158_SUM_0_), .B1(n1986), .Y(n1329) );
AOI32X1TS U2555 ( .A0(n1932), .A1(DP_OP_502J326_128_4510_n27), .A2(
intadd_1158_SUM_1_), .B0(n1329), .B1(DP_OP_502J326_128_4510_n32), .Y(
n1964) );
NAND2X1TS U2556 ( .A(n1932), .B(intadd_1158_SUM_0_), .Y(n1966) );
INVX2TS U2557 ( .A(n1984), .Y(n1934) );
AOI32X1TS U2558 ( .A0(DP_OP_502J326_128_4510_n32), .A1(n1973), .A2(n1966),
.B0(n1934), .B1(n2449), .Y(n1965) );
AOI21X1TS U2559 ( .A0(n2449), .A1(n1934), .B0(DP_OP_502J326_128_4510_n66),
.Y(n1330) );
NAND2X1TS U2560 ( .A(n1963), .B(n1330), .Y(n1952) );
NOR2X1TS U2561 ( .A(n1963), .B(n1330), .Y(n1947) );
NOR2BX1TS U2562 ( .AN(n1952), .B(n1947), .Y(n1335) );
NAND2X1TS U2563 ( .A(n1332), .B(n1331), .Y(n1953) );
INVX2TS U2564 ( .A(n1953), .Y(n1334) );
OAI21XLTS U2565 ( .A0(n1946), .A1(n1334), .B0(n1335), .Y(n1333) );
OAI31X1TS U2566 ( .A0(n1946), .A1(n1335), .A2(n1334), .B0(n1333), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N3) );
CMPR32X2TS U2567 ( .A(mult_x_309_n13), .B(FPMULT_Op_MX[22]), .C(
FPMULT_Op_MY[22]), .CO(n1211), .S(intadd_1157_B_6_) );
NAND2X1TS U2568 ( .A(FPMULT_Op_MX[7]), .B(FPMULT_Op_MY[7]), .Y(n1338) );
NAND2X1TS U2569 ( .A(FPMULT_Op_MX[6]), .B(FPMULT_Op_MY[8]), .Y(n1339) );
XOR2X1TS U2570 ( .A(n1338), .B(n1339), .Y(n1750) );
OAI32X1TS U2571 ( .A0(n1336), .A1(n2477), .A2(n1762), .B0(FPMULT_Op_MX[8]),
.B1(n1337), .Y(n1749) );
NAND2X1TS U2572 ( .A(n1750), .B(n1749), .Y(n1748) );
OAI21XLTS U2573 ( .A0(n1337), .A1(n2477), .B0(n1748), .Y(intadd_1154_CI) );
AOI211X1TS U2574 ( .A0(FPMULT_Op_MX[6]), .A1(FPMULT_Op_MY[7]), .B0(n2498),
.C0(n2545), .Y(n1745) );
NAND3XLTS U2575 ( .A(FPMULT_Op_MX[6]), .B(FPMULT_Op_MY[9]), .C(n1745), .Y(
n1744) );
OAI21XLTS U2576 ( .A0(n1339), .A1(n1338), .B0(n1744), .Y(intadd_1154_B_1_)
);
OAI2BB2X1TS U2577 ( .B0(n1343), .B1(n1342), .A0N(n1341), .A1N(n1340), .Y(
FPADDSUB_LZD_raw_out_EWR[3]) );
AND4X1TS U2578 ( .A(FPMULT_Exp_module_Data_S[3]), .B(
FPMULT_Exp_module_Data_S[2]), .C(FPMULT_Exp_module_Data_S[0]), .D(
FPMULT_Exp_module_Data_S[1]), .Y(n1344) );
AND4X1TS U2579 ( .A(FPMULT_Exp_module_Data_S[6]), .B(
FPMULT_Exp_module_Data_S[5]), .C(FPMULT_Exp_module_Data_S[4]), .D(
n1344), .Y(n1345) );
MX2X1TS U2580 ( .A(FPMULT_Op_MX[23]), .B(FPMULT_exp_oper_result[0]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[0]) );
MX2X1TS U2581 ( .A(FPMULT_Op_MX[24]), .B(FPMULT_exp_oper_result[1]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[1]) );
MX2X1TS U2582 ( .A(FPMULT_Op_MX[25]), .B(FPMULT_exp_oper_result[2]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[2]) );
MX2X1TS U2583 ( .A(FPMULT_Op_MX[26]), .B(FPMULT_exp_oper_result[3]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[3]) );
MX2X1TS U2584 ( .A(FPMULT_Op_MX[27]), .B(FPMULT_exp_oper_result[4]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[4]) );
MX2X1TS U2585 ( .A(FPMULT_Op_MX[28]), .B(FPMULT_exp_oper_result[5]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[5]) );
MX2X1TS U2586 ( .A(FPMULT_Op_MX[29]), .B(FPMULT_exp_oper_result[6]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[6]) );
MX2X1TS U2587 ( .A(FPMULT_Op_MX[30]), .B(FPMULT_exp_oper_result[7]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[7]) );
CLKAND2X2TS U2588 ( .A(FPMULT_FSM_selector_A), .B(FPMULT_exp_oper_result[8]),
.Y(FPMULT_S_Oper_A_exp[8]) );
NAND2X1TS U2589 ( .A(FPADDSUB_DmP_mant_SFG_SWR[6]), .B(n2524), .Y(n2192) );
INVX2TS U2590 ( .A(n2192), .Y(n1348) );
NAND2X1TS U2591 ( .A(FPADDSUB_DmP_mant_SFG_SWR[4]), .B(n2523), .Y(n2182) );
OAI222X1TS U2592 ( .A0(n2525), .A1(n2188), .B0(n2525), .B1(
FPADDSUB_DMP_SFG[3]), .C0(n2188), .C1(FPADDSUB_DMP_SFG[3]), .Y(n2194)
);
OA22X1TS U2593 ( .A0(n1348), .A1(n2194), .B0(n2524), .B1(
FPADDSUB_DmP_mant_SFG_SWR[6]), .Y(n2199) );
NOR2X1TS U2594 ( .A(FPADDSUB_DMP_SFG[5]), .B(FPADDSUB_DmP_mant_SFG_SWR[7]),
.Y(n2197) );
NAND2X1TS U2595 ( .A(FPADDSUB_DmP_mant_SFG_SWR[5]), .B(FPADDSUB_DMP_SFG[3]),
.Y(n2189) );
NAND2X1TS U2596 ( .A(FPADDSUB_DmP_mant_SFG_SWR[3]), .B(FPADDSUB_DMP_SFG[1]),
.Y(n2179) );
NAND2X1TS U2597 ( .A(FPADDSUB_DMP_SFG[0]), .B(FPADDSUB_DmP_mant_SFG_SWR[2]),
.Y(n1349) );
AOI22X1TS U2598 ( .A0(FPADDSUB_OP_FLAG_SFG), .A1(n1601), .B0(n1600), .B1(
n922), .Y(n1351) );
NAND2X1TS U2599 ( .A(FPADDSUB_DmP_mant_SFG_SWR[8]), .B(n2485), .Y(n1602) );
OAI21XLTS U2600 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[8]), .A1(n2485), .B0(n1602),
.Y(n1350) );
XOR2XLTS U2601 ( .A(n1351), .B(n1350), .Y(FPADDSUB_Raw_mant_SGF[8]) );
OAI21XLTS U2602 ( .A0(n1353), .A1(n2541), .B0(n1352), .Y(intadd_1153_CI) );
NAND3XLTS U2603 ( .A(FPMULT_Op_MX[12]), .B(FPMULT_Op_MY[15]), .C(n1767), .Y(
n1766) );
NOR2X2TS U2604 ( .A(n1898), .B(n1900), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N0) );
CLKAND2X2TS U2605 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N0), .B(n1460), .Y(intadd_1149_A_0_) );
NAND2X1TS U2606 ( .A(intadd_1147_SUM_6_), .B(intadd_1148_SUM_7_), .Y(n1356)
);
OAI32X1TS U2607 ( .A0(intadd_1149_A_0_), .A1(n1462), .A2(n1898), .B0(n1356),
.B1(intadd_1149_A_0_), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N1) );
INVX4TS U2608 ( .A(n2673), .Y(n1397) );
OAI22X1TS U2609 ( .A0(n962), .A1(n969), .B0(FPADDSUB_Raw_mant_NRM_SWR[0]),
.B1(n1397), .Y(n2288) );
INVX2TS U2610 ( .A(n2289), .Y(n1358) );
NOR2XLTS U2611 ( .A(n2288), .B(n1358), .Y(FPADDSUB_Data_array_SWR[25]) );
AOI22X1TS U2612 ( .A0(n2673), .A1(FPADDSUB_Raw_mant_NRM_SWR[24]), .B0(n969),
.B1(n956), .Y(n1409) );
OAI222X4TS U2613 ( .A0(n1360), .A1(FPADDSUB_Raw_mant_NRM_SWR[3]), .B0(n1397),
.B1(FPADDSUB_Raw_mant_NRM_SWR[22]), .C0(FPADDSUB_DmP_mant_SHT1_SW[1]),
.C1(n2674), .Y(n1418) );
AOI2BB2XLTS U2614 ( .B0(n2673), .B1(FPADDSUB_Raw_mant_NRM_SWR[25]), .A0N(
n1359), .A1N(n1418), .Y(n1361) );
OAI222X4TS U2615 ( .A0(n1360), .A1(FPADDSUB_Raw_mant_NRM_SWR[8]), .B0(n1397),
.B1(FPADDSUB_Raw_mant_NRM_SWR[17]), .C0(FPADDSUB_DmP_mant_SHT1_SW[6]),
.C1(n2674), .Y(n1412) );
NAND2X1TS U2616 ( .A(n2289), .B(n962), .Y(n1362) );
INVX2TS U2617 ( .A(n2287), .Y(n1386) );
AOI22X1TS U2618 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[19]), .A1(n2673), .B0(
FPADDSUB_DmP_mant_SHT1_SW[4]), .B1(n2462), .Y(n1363) );
AOI222X4TS U2619 ( .A0(n2462), .A1(FPADDSUB_DmP_mant_SHT1_SW[5]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[7]), .B1(n969), .C0(
FPADDSUB_Raw_mant_NRM_SWR[18]), .C1(n2673), .Y(n1404) );
OAI222X4TS U2620 ( .A0(n1360), .A1(FPADDSUB_Raw_mant_NRM_SWR[9]), .B0(n1397),
.B1(FPADDSUB_Raw_mant_NRM_SWR[16]), .C0(FPADDSUB_DmP_mant_SHT1_SW[7]),
.C1(n2674), .Y(n1416) );
OAI22X1TS U2621 ( .A0(n1404), .A1(n1364), .B0(n1359), .B1(n1416), .Y(n1365)
);
AOI21X1TS U2622 ( .A0(n1386), .A1(n1406), .B0(n1365), .Y(n1366) );
OAI21XLTS U2623 ( .A0(n1357), .A1(n1412), .B0(n1366), .Y(
FPADDSUB_Data_array_SWR[6]) );
OAI222X4TS U2624 ( .A0(n1360), .A1(FPADDSUB_Raw_mant_NRM_SWR[21]), .B0(n1397), .B1(FPADDSUB_Raw_mant_NRM_SWR[4]), .C0(FPADDSUB_DmP_mant_SHT1_SW[19]), .C1(
n2674), .Y(n1442) );
OAI22X1TS U2625 ( .A0(n2674), .A1(FPADDSUB_DmP_mant_SHT1_SW[16]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[7]), .B1(n1397), .Y(n1367) );
AOI2BB1X2TS U2626 ( .A0N(n1360), .A1N(FPADDSUB_Raw_mant_NRM_SWR[18]), .B0(
n1367), .Y(n1435) );
AOI222X4TS U2627 ( .A0(n2462), .A1(FPADDSUB_DmP_mant_SHT1_SW[17]), .B0(n2673), .B1(FPADDSUB_Raw_mant_NRM_SWR[6]), .C0(FPADDSUB_Raw_mant_NRM_SWR[19]), .C1(
n969), .Y(n1440) );
OAI222X4TS U2628 ( .A0(n1360), .A1(FPADDSUB_Raw_mant_NRM_SWR[20]), .B0(n1397), .B1(FPADDSUB_Raw_mant_NRM_SWR[5]), .C0(FPADDSUB_DmP_mant_SHT1_SW[18]), .C1(
n2674), .Y(n1441) );
OAI22X1TS U2629 ( .A0(n1440), .A1(n1364), .B0(n1357), .B1(n1441), .Y(n1368)
);
AOI21X1TS U2630 ( .A0(n1386), .A1(n1435), .B0(n1368), .Y(n1369) );
OAI21XLTS U2631 ( .A0(n1359), .A1(n1442), .B0(n1369), .Y(
FPADDSUB_Data_array_SWR[18]) );
OAI222X4TS U2632 ( .A0(n1360), .A1(n965), .B0(n1397), .B1(
FPADDSUB_Raw_mant_NRM_SWR[13]), .C0(FPADDSUB_DmP_mant_SHT1_SW[10]),
.C1(n2674), .Y(n1426) );
AOI22X1TS U2633 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[15]), .A1(n2673), .B0(
FPADDSUB_DmP_mant_SHT1_SW[8]), .B1(n2462), .Y(n1370) );
AOI222X4TS U2634 ( .A0(n2462), .A1(FPADDSUB_DmP_mant_SHT1_SW[11]), .B0(n2673), .B1(n965), .C0(FPADDSUB_Raw_mant_NRM_SWR[13]), .C1(n969), .Y(n1427) );
AOI222X4TS U2635 ( .A0(n2462), .A1(FPADDSUB_DmP_mant_SHT1_SW[9]), .B0(n2673),
.B1(FPADDSUB_Raw_mant_NRM_SWR[14]), .C0(FPADDSUB_Raw_mant_NRM_SWR[11]),
.C1(n969), .Y(n1425) );
OAI22X1TS U2636 ( .A0(n1427), .A1(n1359), .B0(n1425), .B1(n1364), .Y(n1371)
);
AOI21X1TS U2637 ( .A0(n1386), .A1(n1414), .B0(n1371), .Y(n1372) );
OAI21XLTS U2638 ( .A0(n1357), .A1(n1426), .B0(n1372), .Y(
FPADDSUB_Data_array_SWR[10]) );
OAI222X4TS U2639 ( .A0(n1360), .A1(FPADDSUB_Raw_mant_NRM_SWR[17]), .B0(n1397), .B1(FPADDSUB_Raw_mant_NRM_SWR[8]), .C0(FPADDSUB_DmP_mant_SHT1_SW[15]), .C1(
n2674), .Y(n1433) );
OAI22X1TS U2640 ( .A0(n2674), .A1(FPADDSUB_DmP_mant_SHT1_SW[12]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[11]), .B1(n1397), .Y(n1373) );
AOI222X4TS U2641 ( .A0(n2462), .A1(FPADDSUB_DmP_mant_SHT1_SW[13]), .B0(n2673), .B1(FPADDSUB_Raw_mant_NRM_SWR[10]), .C0(FPADDSUB_Raw_mant_NRM_SWR[15]), .C1(
n969), .Y(n1431) );
OAI222X4TS U2642 ( .A0(n1360), .A1(FPADDSUB_Raw_mant_NRM_SWR[16]), .B0(n1397), .B1(FPADDSUB_Raw_mant_NRM_SWR[9]), .C0(FPADDSUB_DmP_mant_SHT1_SW[14]), .C1(
n2674), .Y(n1432) );
OAI22X1TS U2643 ( .A0(n1431), .A1(n1364), .B0(n1357), .B1(n1432), .Y(n1374)
);
AOI21X1TS U2644 ( .A0(n1386), .A1(n1429), .B0(n1374), .Y(n1375) );
OAI21XLTS U2645 ( .A0(n1359), .A1(n1433), .B0(n1375), .Y(
FPADDSUB_Data_array_SWR[14]) );
INVX2TS U2646 ( .A(n1364), .Y(n1389) );
OAI22X1TS U2647 ( .A0(n1425), .A1(n1357), .B0(n2287), .B1(n1416), .Y(n1376)
);
AOI21X1TS U2648 ( .A0(n1389), .A1(n1414), .B0(n1376), .Y(n1377) );
OAI21XLTS U2649 ( .A0(n1359), .A1(n1426), .B0(n1377), .Y(
FPADDSUB_Data_array_SWR[9]) );
OAI22X1TS U2650 ( .A0(n1440), .A1(n1357), .B0(n2287), .B1(n1433), .Y(n1378)
);
AOI21X1TS U2651 ( .A0(n1389), .A1(n1435), .B0(n1378), .Y(n1379) );
OAI21XLTS U2652 ( .A0(n1359), .A1(n1441), .B0(n1379), .Y(
FPADDSUB_Data_array_SWR[17]) );
OAI222X4TS U2653 ( .A0(n1360), .A1(FPADDSUB_Raw_mant_NRM_SWR[5]), .B0(n1397),
.B1(FPADDSUB_Raw_mant_NRM_SWR[20]), .C0(FPADDSUB_DmP_mant_SHT1_SW[3]),
.C1(n2674), .Y(n1417) );
OAI22X1TS U2654 ( .A0(n1404), .A1(n1357), .B0(n1359), .B1(n1412), .Y(n1380)
);
AOI21X1TS U2655 ( .A0(n1389), .A1(n1406), .B0(n1380), .Y(n1381) );
OAI21XLTS U2656 ( .A0(n2287), .A1(n1417), .B0(n1381), .Y(
FPADDSUB_Data_array_SWR[5]) );
OAI22X1TS U2657 ( .A0(n1431), .A1(n1357), .B0(n1427), .B1(n2287), .Y(n1382)
);
AOI21X1TS U2658 ( .A0(n1389), .A1(n1429), .B0(n1382), .Y(n1383) );
AOI222X4TS U2659 ( .A0(n2462), .A1(FPADDSUB_DmP_mant_SHT1_SW[21]), .B0(n2673), .B1(FPADDSUB_Raw_mant_NRM_SWR[2]), .C0(FPADDSUB_Raw_mant_NRM_SWR[23]), .C1(
n969), .Y(n2286) );
OAI22X1TS U2660 ( .A0(n2674), .A1(FPADDSUB_DmP_mant_SHT1_SW[20]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[3]), .B1(n1397), .Y(n1384) );
OAI222X4TS U2661 ( .A0(n1360), .A1(FPADDSUB_Raw_mant_NRM_SWR[24]), .B0(n1397), .B1(n956), .C0(FPADDSUB_DmP_mant_SHT1_SW[22]), .C1(n2674), .Y(n2290) );
OAI22X1TS U2662 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[25]), .A1(n1360), .B0(
FPADDSUB_Raw_mant_NRM_SWR[0]), .B1(n1397), .Y(n2285) );
OAI22X1TS U2663 ( .A0(n2290), .A1(n1357), .B0(n1359), .B1(n2285), .Y(n1385)
);
AOI21X1TS U2664 ( .A0(n1386), .A1(n1445), .B0(n1385), .Y(n1387) );
OAI21XLTS U2665 ( .A0(n2286), .A1(n1364), .B0(n1387), .Y(
FPADDSUB_Data_array_SWR[22]) );
OAI22X1TS U2666 ( .A0(n2290), .A1(n1359), .B0(n2287), .B1(n1442), .Y(n1388)
);
AOI21X1TS U2667 ( .A0(n1389), .A1(n1445), .B0(n1388), .Y(n1390) );
OAI21XLTS U2668 ( .A0(n2286), .A1(n1357), .B0(n1390), .Y(
FPADDSUB_Data_array_SWR[21]) );
OAI22X1TS U2669 ( .A0(FPMULT_FS_Module_state_reg[1]), .A1(
FPMULT_FS_Module_state_reg[0]), .B0(n2306), .B1(n1391), .Y(n1392) );
OAI21XLTS U2670 ( .A0(n1394), .A1(n1393), .B0(n1392), .Y(
FPMULT_FS_Module_state_next[1]) );
NAND2X1TS U2671 ( .A(n1510), .B(intadd_1148_SUM_5_), .Y(n1396) );
INVX2TS U2672 ( .A(intadd_1148_SUM_4_), .Y(n1819) );
OAI211XLTS U2673 ( .A0(n1819), .A1(n1510), .B0(n1396), .C0(
intadd_1147_SUM_0_), .Y(n1395) );
OAI21X1TS U2674 ( .A0(intadd_1147_SUM_0_), .A1(n1396), .B0(n1395), .Y(
mult_x_313_n76) );
OAI222X4TS U2675 ( .A0(n1360), .A1(FPADDSUB_Raw_mant_NRM_SWR[4]), .B0(n1397),
.B1(FPADDSUB_Raw_mant_NRM_SWR[21]), .C0(FPADDSUB_DmP_mant_SHT1_SW[2]),
.C1(n2674), .Y(n1408) );
INVX2TS U2676 ( .A(n1359), .Y(n1438) );
OAI22X1TS U2677 ( .A0(n2287), .A1(n1418), .B0(n1357), .B1(n1417), .Y(n1398)
);
AOI21X1TS U2678 ( .A0(n1438), .A1(n1406), .B0(n1398), .Y(n1399) );
OAI21XLTS U2679 ( .A0(n1364), .A1(n1408), .B0(n1399), .Y(
FPADDSUB_Data_array_SWR[3]) );
OAI22X1TS U2680 ( .A0(n1404), .A1(n2287), .B0(n1357), .B1(n1416), .Y(n1400)
);
AOI21X1TS U2681 ( .A0(n1438), .A1(n1414), .B0(n1400), .Y(n1401) );
OAI21XLTS U2682 ( .A0(n1364), .A1(n1412), .B0(n1401), .Y(
FPADDSUB_Data_array_SWR[7]) );
OAI22X1TS U2683 ( .A0(n1431), .A1(n2287), .B0(n1357), .B1(n1433), .Y(n1402)
);
AOI21X1TS U2684 ( .A0(n1438), .A1(n1435), .B0(n1402), .Y(n1403) );
INVX2TS U2685 ( .A(n1357), .Y(n1444) );
OAI22X1TS U2686 ( .A0(n1404), .A1(n1359), .B0(n1364), .B1(n1417), .Y(n1405)
);
AOI21X1TS U2687 ( .A0(n1444), .A1(n1406), .B0(n1405), .Y(n1407) );
OAI21XLTS U2688 ( .A0(n2287), .A1(n1408), .B0(n1407), .Y(
FPADDSUB_Data_array_SWR[4]) );
INVX2TS U2689 ( .A(n1408), .Y(n1420) );
OAI22X1TS U2690 ( .A0(n1409), .A1(n2287), .B0(n1357), .B1(n1418), .Y(n1410)
);
AOI21X1TS U2691 ( .A0(n1438), .A1(n1420), .B0(n1410), .Y(n1411) );
OAI21XLTS U2692 ( .A0(n1422), .A1(n1364), .B0(n1411), .Y(
FPADDSUB_Data_array_SWR[1]) );
OAI22X1TS U2693 ( .A0(n1425), .A1(n1359), .B0(n2287), .B1(n1412), .Y(n1413)
);
AOI21X1TS U2694 ( .A0(n1444), .A1(n1414), .B0(n1413), .Y(n1415) );
OAI21XLTS U2695 ( .A0(n1364), .A1(n1416), .B0(n1415), .Y(
FPADDSUB_Data_array_SWR[8]) );
OAI22X1TS U2696 ( .A0(n1364), .A1(n1418), .B0(n1359), .B1(n1417), .Y(n1419)
);
AOI21X1TS U2697 ( .A0(n1444), .A1(n1420), .B0(n1419), .Y(n1421) );
OAI21XLTS U2698 ( .A0(n1422), .A1(n2287), .B0(n1421), .Y(
FPADDSUB_Data_array_SWR[2]) );
OAI22X1TS U2699 ( .A0(n1427), .A1(n1357), .B0(n1364), .B1(n1426), .Y(n1423)
);
AOI21X1TS U2700 ( .A0(n1438), .A1(n1429), .B0(n1423), .Y(n1424) );
OAI21XLTS U2701 ( .A0(n1425), .A1(n2287), .B0(n1424), .Y(
FPADDSUB_Data_array_SWR[11]) );
OAI22X1TS U2702 ( .A0(n1427), .A1(n1364), .B0(n2287), .B1(n1426), .Y(n1428)
);
AOI21X1TS U2703 ( .A0(n1444), .A1(n1429), .B0(n1428), .Y(n1430) );
OAI21XLTS U2704 ( .A0(n1431), .A1(n1359), .B0(n1430), .Y(
FPADDSUB_Data_array_SWR[12]) );
OAI22X1TS U2705 ( .A0(n1364), .A1(n1433), .B0(n2287), .B1(n1432), .Y(n1434)
);
AOI21X1TS U2706 ( .A0(n1444), .A1(n1435), .B0(n1434), .Y(n1436) );
OAI21XLTS U2707 ( .A0(n1440), .A1(n1359), .B0(n1436), .Y(
FPADDSUB_Data_array_SWR[16]) );
OAI22X1TS U2708 ( .A0(n1364), .A1(n1441), .B0(n1357), .B1(n1442), .Y(n1437)
);
AOI21X1TS U2709 ( .A0(n1445), .A1(n1438), .B0(n1437), .Y(n1439) );
OAI21XLTS U2710 ( .A0(n1440), .A1(n2287), .B0(n1439), .Y(
FPADDSUB_Data_array_SWR[19]) );
OAI22X1TS U2711 ( .A0(n1364), .A1(n1442), .B0(n2287), .B1(n1441), .Y(n1443)
);
AOI21X1TS U2712 ( .A0(n1445), .A1(n1444), .B0(n1443), .Y(n1446) );
OAI21XLTS U2713 ( .A0(n2286), .A1(n1359), .B0(n1446), .Y(
FPADDSUB_Data_array_SWR[20]) );
NAND2X1TS U2714 ( .A(n1495), .B(intadd_1159_SUM_0_), .Y(n1448) );
OAI32X1TS U2715 ( .A0(intadd_1141_A_0_), .A1(n1911), .A2(n1629), .B0(n1448),
.B1(intadd_1141_A_0_), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N1) );
NOR2X1TS U2716 ( .A(n1450), .B(n1462), .Y(DP_OP_501J326_127_5235_n72) );
INVX2TS U2717 ( .A(n1851), .Y(n1854) );
NOR2X1TS U2718 ( .A(n1854), .B(n1853), .Y(DP_OP_500J326_126_4510_n56) );
INVX2TS U2719 ( .A(n1972), .Y(n1498) );
AOI21X1TS U2720 ( .A0(n1449), .A1(n2488), .B0(n1498), .Y(n1497) );
INVX2TS U2721 ( .A(n1497), .Y(n1970) );
NOR2X1TS U2722 ( .A(n1973), .B(n1970), .Y(DP_OP_502J326_128_4510_n57) );
INVX2TS U2723 ( .A(intadd_1152_SUM_1_), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N6) );
INVX2TS U2724 ( .A(intadd_1148_SUM_2_), .Y(n1810) );
OAI22X1TS U2725 ( .A0(n1784), .A1(n1804), .B0(n1810), .B1(n1806), .Y(
mult_x_313_n27) );
INVX2TS U2726 ( .A(mult_x_313_n27), .Y(mult_x_313_n28) );
NOR3X1TS U2727 ( .A(n1460), .B(n1627), .C(n1907), .Y(
DP_OP_501J326_127_5235_n39) );
NOR2X1TS U2728 ( .A(n1631), .B(n1450), .Y(DP_OP_501J326_127_5235_n54) );
INVX2TS U2729 ( .A(intadd_1152_SUM_2_), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N7) );
NAND3X1TS U2730 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .B(n1452),
.C(n1451), .Y(n2314) );
NOR3XLTS U2731 ( .A(n1457), .B(n2330), .C(n2314), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]) );
AOI22X1TS U2732 ( .A0(intadd_1148_SUM_6_), .A1(intadd_1147_SUM_9_), .B0(
intadd_1147_SUM_6_), .B1(intadd_1148_SUM_9_), .Y(n1890) );
NAND3XLTS U2733 ( .A(intadd_1147_SUM_9_), .B(intadd_1148_SUM_9_), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N0), .Y(n1453) );
OAI21X1TS U2734 ( .A0(n1890), .A1(n1891), .B0(n1453), .Y(
DP_OP_501J326_127_5235_n40) );
OAI22X1TS U2735 ( .A0(n1784), .A1(n1806), .B0(n1807), .B1(n1804), .Y(
mult_x_313_n32) );
INVX2TS U2736 ( .A(mult_x_313_n32), .Y(mult_x_313_n33) );
NOR2X1TS U2737 ( .A(n1631), .B(n1907), .Y(DP_OP_501J326_127_5235_n55) );
INVX2TS U2738 ( .A(intadd_1152_SUM_3_), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8) );
NOR2XLTS U2739 ( .A(n1455), .B(n1454), .Y(DP_OP_501J326_127_5235_n19) );
NOR2X1TS U2740 ( .A(n1631), .B(n1896), .Y(DP_OP_501J326_127_5235_n56) );
INVX2TS U2741 ( .A(intadd_1152_SUM_4_), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9) );
INVX2TS U2742 ( .A(intadd_1152_SUM_5_), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10) );
NOR2X1TS U2743 ( .A(n1630), .B(n1917), .Y(DP_OP_501J326_127_5235_n179) );
NAND2X1TS U2744 ( .A(operation[2]), .B(n2330), .Y(n1527) );
NAND3XLTS U2745 ( .A(FPMULT_FS_Module_state_reg[3]), .B(n2308), .C(n2305),
.Y(n1526) );
AOI21X1TS U2746 ( .A0(ack_operation), .A1(n1456), .B0(n1526), .Y(n1458) );
OAI32X1TS U2747 ( .A0(n1458), .A1(n1527), .A2(n1457), .B0(n1103), .B1(n1458),
.Y(n844) );
INVX2TS U2748 ( .A(intadd_1152_SUM_6_), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11) );
INVX2TS U2749 ( .A(intadd_1152_SUM_7_), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12) );
AOI222X1TS U2750 ( .A0(n2330), .A1(Data_2[30]), .B0(n2339), .B1(
FPSENCOS_d_ff3_sh_x_out[30]), .C0(FPSENCOS_d_ff3_sh_y_out[30]), .C1(
n2420), .Y(n1459) );
INVX2TS U2751 ( .A(n1459), .Y(add_subt_data2[30]) );
INVX2TS U2752 ( .A(FPMULT_Sgf_normalized_result[23]), .Y(n1677) );
NAND2X1TS U2753 ( .A(FPMULT_Sgf_normalized_result[6]), .B(n1703), .Y(n1702)
);
NAND2X1TS U2754 ( .A(FPMULT_Sgf_normalized_result[8]), .B(n1700), .Y(n1699)
);
NAND2X1TS U2755 ( .A(FPMULT_Sgf_normalized_result[10]), .B(n1697), .Y(n1696)
);
NAND2X1TS U2756 ( .A(FPMULT_Sgf_normalized_result[12]), .B(n1694), .Y(n1693)
);
NAND2X1TS U2757 ( .A(FPMULT_Sgf_normalized_result[14]), .B(n1691), .Y(n1690)
);
NAND2X1TS U2758 ( .A(FPMULT_Sgf_normalized_result[16]), .B(n1688), .Y(n1687)
);
NAND2X1TS U2759 ( .A(FPMULT_Sgf_normalized_result[18]), .B(n1685), .Y(n1684)
);
NAND2X1TS U2760 ( .A(FPMULT_Sgf_normalized_result[20]), .B(n1682), .Y(n1681)
);
NAND2X1TS U2761 ( .A(FPMULT_Sgf_normalized_result[22]), .B(n1679), .Y(n1678)
);
NOR2X1TS U2762 ( .A(n1677), .B(n1678), .Y(FPMULT_Adder_M_result_A_adder[24])
);
NOR2X1TS U2763 ( .A(n1919), .B(n1915), .Y(DP_OP_501J326_127_5235_n193) );
INVX2TS U2764 ( .A(n1461), .Y(intadd_1149_CI) );
NAND2X1TS U2765 ( .A(intadd_1148_SUM_8_), .B(intadd_1147_SUM_7_), .Y(n1463)
);
OAI32X1TS U2766 ( .A0(n1903), .A1(n1627), .A2(n1896), .B0(n1463), .B1(n1903),
.Y(intadd_1149_A_1_) );
AOI21X2TS U2767 ( .A0(intadd_1162_n1), .A1(FPMULT_Op_MY[17]), .B0(n1881),
.Y(n1882) );
AOI22X1TS U2768 ( .A0(n1854), .A1(n1882), .B0(n1881), .B1(n1851), .Y(n1490)
);
INVX2TS U2769 ( .A(n1882), .Y(n1869) );
AOI22X1TS U2770 ( .A0(n1854), .A1(intadd_1162_SUM_3_), .B0(n1869), .B1(n1851), .Y(n1487) );
INVX2TS U2771 ( .A(n1487), .Y(n1489) );
XOR2X1TS U2772 ( .A(n1464), .B(intadd_1152_n1), .Y(n1466) );
OAI21XLTS U2773 ( .A0(n1881), .A1(n1851), .B0(n1466), .Y(n1465) );
OAI31X1TS U2774 ( .A0(n1466), .A1(n1881), .A2(n1851), .B0(n1465), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13) );
CMPR32X2TS U2775 ( .A(n1469), .B(n1468), .C(n1467), .CO(n1470), .S(n1064) );
INVX2TS U2776 ( .A(n1470), .Y(n1473) );
AOI22X1TS U2777 ( .A0(intadd_1163_SUM_2_), .A1(intadd_1162_SUM_2_), .B0(
n1857), .B1(n1871), .Y(n1875) );
AOI22X1TS U2778 ( .A0(n1472), .A1(n1875), .B0(n1876), .B1(n1471), .Y(n1474)
);
NOR2X1TS U2779 ( .A(n1473), .B(n1474), .Y(DP_OP_500J326_126_4510_n41) );
AOI21X1TS U2780 ( .A0(n1474), .A1(n1473), .B0(DP_OP_500J326_126_4510_n41),
.Y(n1847) );
NOR2XLTS U2781 ( .A(n1476), .B(n1475), .Y(n1846) );
INVX2TS U2782 ( .A(intadd_1152_SUM_0_), .Y(n1845) );
INVX2TS U2783 ( .A(n1477), .Y(intadd_1152_B_1_) );
NOR2X1TS U2784 ( .A(n1478), .B(intadd_1163_SUM_3_), .Y(n1483) );
AOI22X1TS U2785 ( .A0(intadd_1162_SUM_0_), .A1(n1478), .B0(n1860), .B1(n1852), .Y(n1863) );
NAND4XLTS U2786 ( .A(n1479), .B(intadd_1163_SUM_2_), .C(n1478), .D(
intadd_1163_SUM_3_), .Y(n1480) );
OAI21XLTS U2787 ( .A0(n1863), .A1(n1864), .B0(n1480), .Y(n1481) );
AOI31XLTS U2788 ( .A0(n1483), .A1(n1853), .A2(n1871), .B0(n1481), .Y(
intadd_1152_CI) );
INVX2TS U2789 ( .A(n1881), .Y(n1879) );
AOI22X1TS U2790 ( .A0(n1478), .A1(n1879), .B0(n1881), .B1(n1860), .Y(n1855)
);
INVX2TS U2791 ( .A(n1482), .Y(n1484) );
OAI22X1TS U2792 ( .A0(n1478), .A1(n1864), .B0(n1855), .B1(n1862), .Y(n1486)
);
INVX2TS U2793 ( .A(n1485), .Y(intadd_1152_B_6_) );
CMPR32X2TS U2794 ( .A(DP_OP_500J326_126_4510_n21), .B(n1487), .C(n1486),
.CO(n1488), .S(n1485) );
INVX2TS U2795 ( .A(n1488), .Y(intadd_1152_B_7_) );
CMPR32X2TS U2796 ( .A(n1491), .B(n1490), .C(n1489), .CO(n1464), .S(n1492) );
INVX2TS U2797 ( .A(n1492), .Y(intadd_1152_A_7_) );
INVX2TS U2798 ( .A(n1528), .Y(n1493) );
NOR2XLTS U2799 ( .A(n1493), .B(n1927), .Y(DP_OP_501J326_127_5235_n170) );
NOR2X1TS U2800 ( .A(n1628), .B(n1915), .Y(DP_OP_501J326_127_5235_n194) );
NOR2X1TS U2801 ( .A(n1518), .B(n1628), .Y(DP_OP_501J326_127_5235_n186) );
NOR2X1TS U2802 ( .A(n1924), .B(n1629), .Y(DP_OP_501J326_127_5235_n229) );
NOR2X1TS U2803 ( .A(n1530), .B(n1630), .Y(DP_OP_501J326_127_5235_n182) );
INVX2TS U2804 ( .A(intadd_1159_SUM_3_), .Y(n1916) );
NOR2XLTS U2805 ( .A(n1529), .B(n1916), .Y(DP_OP_501J326_127_5235_n236) );
INVX2TS U2806 ( .A(intadd_1159_SUM_0_), .Y(n1533) );
NOR2X1TS U2807 ( .A(n1533), .B(n1630), .Y(DP_OP_501J326_127_5235_n183) );
NOR2X1TS U2808 ( .A(n1529), .B(n1919), .Y(DP_OP_501J326_127_5235_n233) );
INVX2TS U2809 ( .A(intadd_1160_SUM_3_), .Y(n1925) );
NOR2XLTS U2810 ( .A(n1925), .B(n1628), .Y(DP_OP_501J326_127_5235_n202) );
NOR2X1TS U2811 ( .A(n1535), .B(n1533), .Y(DP_OP_501J326_127_5235_n215) );
NOR2XLTS U2812 ( .A(n1911), .B(n1630), .Y(DP_OP_501J326_127_5235_n184) );
NOR2X1TS U2813 ( .A(n1529), .B(n1917), .Y(DP_OP_501J326_127_5235_n235) );
NOR2X1TS U2814 ( .A(n1916), .B(n1918), .Y(DP_OP_501J326_127_5235_n220) );
NOR3X1TS U2815 ( .A(n1926), .B(n1916), .C(n1925), .Y(
DP_OP_501J326_127_5235_n140) );
NOR2XLTS U2816 ( .A(n1535), .B(n1628), .Y(DP_OP_501J326_127_5235_n210) );
AOI22X1TS U2817 ( .A0(n1494), .A1(intadd_1160_SUM_2_), .B0(n1495), .B1(
intadd_1159_SUM_2_), .Y(n1912) );
NAND4X1TS U2818 ( .A(n1495), .B(intadd_1159_SUM_0_), .C(intadd_1160_SUM_0_),
.D(intadd_1159_SUM_1_), .Y(n1913) );
NAND3XLTS U2819 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N0), .B(intadd_1159_SUM_2_), .C(intadd_1160_SUM_2_), .Y(n1496) );
OAI21X1TS U2820 ( .A0(n1912), .A1(n1913), .B0(n1496), .Y(
DP_OP_501J326_127_5235_n171) );
NOR2X1TS U2821 ( .A(n1917), .B(n1915), .Y(DP_OP_501J326_127_5235_n195) );
AOI22X1TS U2822 ( .A0(intadd_1158_SUM_4_), .A1(n1498), .B0(intadd_1158_n1),
.B1(n1497), .Y(n1505) );
AOI22X1TS U2823 ( .A0(n1500), .A1(n1940), .B0(n1936), .B1(n1499), .Y(n1959)
);
XOR2X1TS U2824 ( .A(n1501), .B(intadd_1151_n1), .Y(n1503) );
OAI21XLTS U2825 ( .A0(n1972), .A1(n1974), .B0(n1503), .Y(n1502) );
OAI31X1TS U2826 ( .A0(n1503), .A1(n1972), .A2(n1974), .B0(n1502), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13) );
AOI22X1TS U2827 ( .A0(n1932), .A1(intadd_1158_SUM_4_), .B0(
intadd_1158_SUM_3_), .B1(n1986), .Y(n1504) );
AOI32X1TS U2828 ( .A0(n1932), .A1(DP_OP_502J326_128_4510_n27), .A2(
intadd_1158_SUM_4_), .B0(n1504), .B1(DP_OP_502J326_128_4510_n32), .Y(
n1944) );
AOI22X1TS U2829 ( .A0(intadd_1158_SUM_2_), .A1(intadd_1161_SUM_2_), .B0(
n1978), .B1(n1968), .Y(n1983) );
AOI22X1TS U2830 ( .A0(intadd_1158_SUM_1_), .A1(intadd_1161_SUM_2_), .B0(
n1978), .B1(n1969), .Y(n1935) );
INVX2TS U2831 ( .A(n1981), .Y(n1982) );
AOI22X1TS U2832 ( .A0(n1983), .A1(n1934), .B0(n1935), .B1(n1982), .Y(n1945)
);
NOR2X1TS U2833 ( .A(n1944), .B(n1945), .Y(DP_OP_502J326_128_4510_n41) );
INVX2TS U2834 ( .A(n1506), .Y(intadd_1151_A_7_) );
NOR2X1TS U2835 ( .A(n1628), .B(n1918), .Y(DP_OP_501J326_127_5235_n218) );
NOR2XLTS U2836 ( .A(n1916), .B(n1518), .Y(DP_OP_501J326_127_5235_n188) );
INVX2TS U2837 ( .A(intadd_1148_SUM_5_), .Y(n1817) );
AOI22X1TS U2838 ( .A0(intadd_1147_SUM_4_), .A1(intadd_1148_SUM_5_), .B0(
n1817), .B1(n1811), .Y(n1808) );
AOI22X1TS U2839 ( .A0(n1816), .A1(intadd_1147_SUM_4_), .B0(n1814), .B1(n1808), .Y(n1792) );
OA22X1TS U2840 ( .A0(n1819), .A1(n1804), .B0(n1817), .B1(n1806), .Y(n1513)
);
XOR2X1TS U2841 ( .A(intadd_1150_n1), .B(n1507), .Y(n1509) );
OAI21XLTS U2842 ( .A0(n1804), .A1(n1817), .B0(n1509), .Y(n1508) );
OAI31X1TS U2843 ( .A0(n1509), .A1(n1804), .A2(n1817), .B0(n1508), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N13) );
NAND2X1TS U2844 ( .A(n1510), .B(intadd_1148_SUM_3_), .Y(n1512) );
OAI211XLTS U2845 ( .A0(n1810), .A1(n1510), .B0(n1512), .C0(
intadd_1147_SUM_0_), .Y(n1511) );
OAI21XLTS U2846 ( .A0(intadd_1147_SUM_0_), .A1(n1512), .B0(n1511), .Y(
intadd_1150_CI) );
CMPR32X2TS U2847 ( .A(n1792), .B(n1794), .C(n1513), .CO(n1507), .S(n1514) );
INVX2TS U2848 ( .A(n1514), .Y(intadd_1150_A_8_) );
NOR2X1TS U2849 ( .A(n1530), .B(n1925), .Y(DP_OP_501J326_127_5235_n206) );
NOR2X1TS U2850 ( .A(n1924), .B(n1518), .Y(DP_OP_501J326_127_5235_n189) );
NOR2X1TS U2851 ( .A(n1533), .B(n1925), .Y(DP_OP_501J326_127_5235_n207) );
NOR2X1TS U2852 ( .A(n1529), .B(n1628), .Y(DP_OP_501J326_127_5235_n234) );
NOR2X1TS U2853 ( .A(n1533), .B(n1915), .Y(DP_OP_501J326_127_5235_n199) );
NOR2XLTS U2854 ( .A(n1911), .B(n1915), .Y(DP_OP_501J326_127_5235_n200) );
NOR2X1TS U2855 ( .A(n1530), .B(n1518), .Y(DP_OP_501J326_127_5235_n190) );
NOR2X2TS U2856 ( .A(n1528), .B(n1927), .Y(n1534) );
INVX2TS U2857 ( .A(n1534), .Y(n1515) );
OAI32X1TS U2858 ( .A0(n1534), .A1(n1916), .A2(n1629), .B0(intadd_1159_SUM_3_), .B1(n1515), .Y(n1930) );
AOI22X1TS U2859 ( .A0(intadd_1159_SUM_2_), .A1(intadd_1160_SUM_1_), .B0(
intadd_1160_SUM_2_), .B1(intadd_1159_SUM_1_), .Y(n1516) );
NOR2X1TS U2860 ( .A(n1517), .B(n1516), .Y(n1929) );
NAND2X1TS U2861 ( .A(n1930), .B(n1929), .Y(n1928) );
OAI31X1TS U2862 ( .A0(n1916), .A1(n1528), .A2(n1927), .B0(n1928), .Y(
DP_OP_501J326_127_5235_n162) );
NOR2X1TS U2863 ( .A(n1533), .B(n1518), .Y(DP_OP_501J326_127_5235_n191) );
NOR2XLTS U2864 ( .A(n1911), .B(n1518), .Y(DP_OP_501J326_127_5235_n192) );
INVX2TS U2865 ( .A(intadd_1145_SUM_8_), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[8]) );
INVX2TS U2866 ( .A(intadd_1145_SUM_11_), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[11]) );
INVX2TS U2867 ( .A(intadd_1145_SUM_9_), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[9]) );
INVX2TS U2868 ( .A(intadd_1145_SUM_4_), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[4]) );
INVX2TS U2869 ( .A(intadd_1145_SUM_6_), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[6]) );
INVX2TS U2870 ( .A(intadd_1145_SUM_7_), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[7]) );
INVX2TS U2871 ( .A(intadd_1145_SUM_5_), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[5]) );
INVX2TS U2872 ( .A(intadd_1145_SUM_10_), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[10]) );
INVX2TS U2873 ( .A(intadd_1145_SUM_3_), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[3]) );
INVX2TS U2874 ( .A(intadd_1145_SUM_2_), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[2]) );
INVX2TS U2875 ( .A(intadd_1145_SUM_1_), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[1]) );
OA21XLTS U2876 ( .A0(intadd_1145_n1), .A1(n1520), .B0(n1519), .Y(n1523) );
OAI21X1TS U2877 ( .A0(n1523), .A1(n1522), .B0(n1521), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[12]) );
INVX2TS U2878 ( .A(intadd_1139_A_6_), .Y(DP_OP_499J326_125_1651_n99) );
INVX2TS U2879 ( .A(FPMULT_Sgf_operation_Result[8]), .Y(
DP_OP_499J326_125_1651_n110) );
NOR2X1TS U2880 ( .A(operation[2]), .B(n2330), .Y(n1536) );
BUFX4TS U2881 ( .A(n1536), .Y(n1571) );
OAI21XLTS U2882 ( .A0(n1527), .A1(n1526), .B0(n1525), .Y(operation_ready) );
INVX2TS U2883 ( .A(FPMULT_Sgf_operation_Result[11]), .Y(
DP_OP_499J326_125_1651_n107) );
INVX2TS U2884 ( .A(FPMULT_Sgf_operation_Result[10]), .Y(
DP_OP_499J326_125_1651_n108) );
INVX2TS U2885 ( .A(FPMULT_Sgf_operation_Result[9]), .Y(
DP_OP_499J326_125_1651_n109) );
INVX2TS U2886 ( .A(intadd_1139_A_5_), .Y(DP_OP_499J326_125_1651_n100) );
INVX2TS U2887 ( .A(intadd_1139_A_1_), .Y(DP_OP_499J326_125_1651_n104) );
INVX2TS U2888 ( .A(intadd_1139_A_4_), .Y(DP_OP_499J326_125_1651_n101) );
INVX2TS U2889 ( .A(intadd_1139_A_2_), .Y(DP_OP_499J326_125_1651_n103) );
INVX2TS U2890 ( .A(intadd_1139_A_3_), .Y(DP_OP_499J326_125_1651_n102) );
INVX2TS U2891 ( .A(intadd_1139_A_0_), .Y(DP_OP_499J326_125_1651_n105) );
INVX2TS U2892 ( .A(intadd_1142_SUM_5_), .Y(DP_OP_499J326_125_1651_n106) );
INVX2TS U2893 ( .A(n1913), .Y(n1531) );
OAI32X1TS U2894 ( .A0(n1531), .A1(n1530), .A2(n1529), .B0(n1528), .B1(n1531),
.Y(intadd_1141_CI) );
NAND2X1TS U2895 ( .A(intadd_1160_SUM_0_), .B(intadd_1159_SUM_1_), .Y(n1532)
);
OAI32X1TS U2896 ( .A0(n1534), .A1(n1533), .A2(n1918), .B0(n1532), .B1(n1534),
.Y(intadd_1141_A_1_) );
NOR4X2TS U2897 ( .A(n1924), .B(n1535), .C(n1916), .D(n1925), .Y(
DP_OP_501J326_127_5235_n139) );
AOI22X1TS U2898 ( .A0(n1551), .A1(cordic_result[29]), .B0(n1456), .B1(
mult_result[29]), .Y(n1537) );
OAI21XLTS U2899 ( .A0(n1083), .A1(n2583), .B0(n1537), .Y(op_result[29]) );
BUFX4TS U2900 ( .A(n1083), .Y(n1569) );
AOI22X1TS U2901 ( .A0(n1551), .A1(cordic_result[20]), .B0(n1456), .B1(
mult_result[20]), .Y(n1538) );
AOI22X1TS U2902 ( .A0(n1551), .A1(cordic_result[26]), .B0(n1456), .B1(
mult_result[26]), .Y(n1539) );
OAI21XLTS U2903 ( .A0(n1083), .A1(n2586), .B0(n1539), .Y(op_result[26]) );
AOI22X1TS U2904 ( .A0(n1551), .A1(cordic_result[27]), .B0(n1456), .B1(
mult_result[27]), .Y(n1540) );
OAI21XLTS U2905 ( .A0(n1083), .A1(n2585), .B0(n1540), .Y(op_result[27]) );
AOI22X1TS U2906 ( .A0(n1551), .A1(cordic_result[28]), .B0(n1456), .B1(
mult_result[28]), .Y(n1541) );
OAI21XLTS U2907 ( .A0(n1083), .A1(n2584), .B0(n1541), .Y(op_result[28]) );
AOI22X1TS U2908 ( .A0(n1551), .A1(cordic_result[25]), .B0(n1456), .B1(
mult_result[25]), .Y(n1542) );
OAI21XLTS U2909 ( .A0(n1083), .A1(n2587), .B0(n1542), .Y(op_result[25]) );
AOI22X1TS U2910 ( .A0(n1551), .A1(cordic_result[30]), .B0(n1456), .B1(
mult_result[30]), .Y(n1543) );
OAI21XLTS U2911 ( .A0(n1083), .A1(n2582), .B0(n1543), .Y(op_result[30]) );
AOI22X1TS U2912 ( .A0(n1551), .A1(cordic_result[24]), .B0(n1456), .B1(
mult_result[24]), .Y(n1544) );
OAI21XLTS U2913 ( .A0(n1083), .A1(n2588), .B0(n1544), .Y(op_result[24]) );
AOI22X1TS U2914 ( .A0(n1551), .A1(cordic_result[23]), .B0(n1456), .B1(
mult_result[23]), .Y(n1545) );
OAI21XLTS U2915 ( .A0(n1083), .A1(n2589), .B0(n1545), .Y(op_result[23]) );
AOI22X1TS U2916 ( .A0(n1551), .A1(cordic_result[0]), .B0(n1456), .B1(
mult_result[0]), .Y(n1546) );
AOI22X1TS U2917 ( .A0(n1551), .A1(cordic_result[22]), .B0(n1456), .B1(
mult_result[22]), .Y(n1547) );
OAI21XLTS U2918 ( .A0(n1569), .A1(n2559), .B0(n1547), .Y(op_result[22]) );
AOI22X1TS U2919 ( .A0(n1551), .A1(cordic_result[1]), .B0(n1456), .B1(
mult_result[1]), .Y(n1548) );
OAI21XLTS U2920 ( .A0(n1569), .A1(n2580), .B0(n1548), .Y(op_result[1]) );
AOI22X1TS U2921 ( .A0(n1551), .A1(cordic_result[21]), .B0(n1456), .B1(
mult_result[21]), .Y(n1549) );
OAI21XLTS U2922 ( .A0(n1569), .A1(n2560), .B0(n1549), .Y(op_result[21]) );
AOI22X1TS U2923 ( .A0(n1551), .A1(cordic_result[31]), .B0(n1456), .B1(
mult_result[31]), .Y(n1550) );
OAI21XLTS U2924 ( .A0(n1569), .A1(n2558), .B0(n1550), .Y(op_result[31]) );
AOI22X1TS U2925 ( .A0(n1551), .A1(cordic_result[19]), .B0(n1456), .B1(
mult_result[19]), .Y(n1552) );
OAI21XLTS U2926 ( .A0(n1569), .A1(n2562), .B0(n1552), .Y(op_result[19]) );
AOI21X1TS U2927 ( .A0(n1574), .A1(n2770), .B0(n1576), .Y(intadd_1139_A_8_)
);
INVX2TS U2928 ( .A(intadd_1139_A_8_), .Y(DP_OP_499J326_125_1651_n97) );
BUFX4TS U2929 ( .A(n1456), .Y(n1570) );
AOI22X1TS U2930 ( .A0(n1571), .A1(cordic_result[8]), .B0(n1570), .B1(
mult_result[8]), .Y(n1553) );
OAI21XLTS U2931 ( .A0(n1569), .A1(n2573), .B0(n1553), .Y(op_result[8]) );
AOI22X1TS U2932 ( .A0(n1571), .A1(cordic_result[4]), .B0(n1570), .B1(
mult_result[4]), .Y(n1554) );
OAI21XLTS U2933 ( .A0(n1569), .A1(n2577), .B0(n1554), .Y(op_result[4]) );
AOI22X1TS U2934 ( .A0(n1571), .A1(cordic_result[14]), .B0(n1570), .B1(
mult_result[14]), .Y(n1555) );
OAI21XLTS U2935 ( .A0(n1083), .A1(n2567), .B0(n1555), .Y(op_result[14]) );
AOI22X1TS U2936 ( .A0(n1571), .A1(cordic_result[7]), .B0(n1570), .B1(
mult_result[7]), .Y(n1556) );
OAI21XLTS U2937 ( .A0(n1569), .A1(n2574), .B0(n1556), .Y(op_result[7]) );
AOI22X1TS U2938 ( .A0(n1571), .A1(cordic_result[17]), .B0(n1570), .B1(
mult_result[17]), .Y(n1557) );
OAI21XLTS U2939 ( .A0(n1569), .A1(n2564), .B0(n1557), .Y(op_result[17]) );
AOI22X1TS U2940 ( .A0(n1571), .A1(cordic_result[12]), .B0(n1570), .B1(
mult_result[12]), .Y(n1558) );
OAI21XLTS U2941 ( .A0(n1083), .A1(n2569), .B0(n1558), .Y(op_result[12]) );
AOI22X1TS U2942 ( .A0(n1571), .A1(cordic_result[10]), .B0(n1570), .B1(
mult_result[10]), .Y(n1559) );
OAI21XLTS U2943 ( .A0(n1569), .A1(n2571), .B0(n1559), .Y(op_result[10]) );
AOI22X1TS U2944 ( .A0(n1571), .A1(cordic_result[3]), .B0(n1570), .B1(
mult_result[3]), .Y(n1560) );
OAI21XLTS U2945 ( .A0(n1569), .A1(n2578), .B0(n1560), .Y(op_result[3]) );
AOI22X1TS U2946 ( .A0(n1571), .A1(cordic_result[15]), .B0(n1570), .B1(
mult_result[15]), .Y(n1561) );
OAI21XLTS U2947 ( .A0(n1083), .A1(n2566), .B0(n1561), .Y(op_result[15]) );
AOI22X1TS U2948 ( .A0(n1571), .A1(cordic_result[2]), .B0(n1570), .B1(
mult_result[2]), .Y(n1562) );
OAI21XLTS U2949 ( .A0(n1569), .A1(n2579), .B0(n1562), .Y(op_result[2]) );
AOI22X1TS U2950 ( .A0(n1571), .A1(cordic_result[5]), .B0(n1570), .B1(
mult_result[5]), .Y(n1563) );
AOI22X1TS U2951 ( .A0(n1571), .A1(cordic_result[18]), .B0(n1570), .B1(
mult_result[18]), .Y(n1564) );
OAI21XLTS U2952 ( .A0(n1569), .A1(n2563), .B0(n1564), .Y(op_result[18]) );
AOI22X1TS U2953 ( .A0(n1571), .A1(cordic_result[16]), .B0(n1570), .B1(
mult_result[16]), .Y(n1565) );
OAI21XLTS U2954 ( .A0(n1083), .A1(n2565), .B0(n1565), .Y(op_result[16]) );
AOI22X1TS U2955 ( .A0(n1571), .A1(cordic_result[6]), .B0(n1570), .B1(
mult_result[6]), .Y(n1566) );
OAI21XLTS U2956 ( .A0(n1083), .A1(n2575), .B0(n1566), .Y(op_result[6]) );
AOI22X1TS U2957 ( .A0(n1571), .A1(cordic_result[11]), .B0(n1570), .B1(
mult_result[11]), .Y(n1567) );
OAI21XLTS U2958 ( .A0(n1569), .A1(n2570), .B0(n1567), .Y(op_result[11]) );
AOI22X1TS U2959 ( .A0(n1571), .A1(cordic_result[9]), .B0(n1570), .B1(
mult_result[9]), .Y(n1568) );
OAI21XLTS U2960 ( .A0(n1569), .A1(n2572), .B0(n1568), .Y(op_result[9]) );
AOI22X1TS U2961 ( .A0(n1571), .A1(cordic_result[13]), .B0(n1570), .B1(
mult_result[13]), .Y(n1572) );
OAI21XLTS U2962 ( .A0(n1083), .A1(n2568), .B0(n1572), .Y(op_result[13]) );
INVX2TS U2963 ( .A(intadd_1139_A_10_), .Y(DP_OP_499J326_125_1651_n95) );
INVX2TS U2964 ( .A(intadd_1139_A_19_), .Y(DP_OP_499J326_125_1651_n133) );
INVX2TS U2965 ( .A(intadd_1139_A_22_), .Y(DP_OP_499J326_125_1651_n130) );
INVX2TS U2966 ( .A(intadd_1139_A_23_), .Y(DP_OP_499J326_125_1651_n129) );
INVX2TS U2967 ( .A(intadd_1139_A_24_), .Y(DP_OP_499J326_125_1651_n128) );
INVX2TS U2968 ( .A(intadd_1139_A_21_), .Y(DP_OP_499J326_125_1651_n131) );
INVX2TS U2969 ( .A(intadd_1139_A_20_), .Y(DP_OP_499J326_125_1651_n132) );
INVX2TS U2970 ( .A(intadd_1144_SUM_12_), .Y(DP_OP_499J326_125_1651_n122) );
INVX2TS U2971 ( .A(intadd_1144_SUM_10_), .Y(DP_OP_499J326_125_1651_n124) );
INVX2TS U2972 ( .A(intadd_1144_SUM_7_), .Y(DP_OP_499J326_125_1651_n127) );
INVX2TS U2973 ( .A(intadd_1144_SUM_8_), .Y(DP_OP_499J326_125_1651_n126) );
INVX2TS U2974 ( .A(intadd_1140_SUM_1_), .Y(intadd_1139_B_7_) );
OAI21X1TS U2975 ( .A0(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[8]), .A1(
intadd_1142_n1), .B0(n1574), .Y(DP_OP_499J326_125_1651_n98) );
INVX2TS U2976 ( .A(DP_OP_499J326_125_1651_n98), .Y(intadd_1139_A_7_) );
INVX2TS U2977 ( .A(intadd_1140_SUM_2_), .Y(intadd_1139_B_8_) );
INVX2TS U2978 ( .A(intadd_1140_SUM_3_), .Y(intadd_1139_B_9_) );
AOI22X1TS U2979 ( .A0(n1576), .A1(n2769), .B0(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[10]), .B1(
n1575), .Y(DP_OP_499J326_125_1651_n96) );
INVX2TS U2980 ( .A(DP_OP_499J326_125_1651_n96), .Y(intadd_1139_A_9_) );
INVX2TS U2981 ( .A(intadd_1140_SUM_4_), .Y(intadd_1139_B_10_) );
INVX2TS U2982 ( .A(intadd_1143_SUM_2_), .Y(intadd_1142_B_1_) );
INVX2TS U2983 ( .A(intadd_1143_SUM_3_), .Y(intadd_1142_B_2_) );
INVX2TS U2984 ( .A(intadd_1143_SUM_4_), .Y(intadd_1142_B_3_) );
INVX2TS U2985 ( .A(intadd_1143_SUM_5_), .Y(intadd_1142_B_4_) );
INVX2TS U2986 ( .A(intadd_1143_SUM_6_), .Y(intadd_1142_B_5_) );
INVX2TS U2987 ( .A(intadd_1143_SUM_7_), .Y(intadd_1142_B_6_) );
INVX2TS U2988 ( .A(intadd_1143_SUM_8_), .Y(intadd_1142_B_7_) );
INVX2TS U2989 ( .A(intadd_1143_SUM_9_), .Y(intadd_1142_B_8_) );
INVX2TS U2990 ( .A(intadd_1143_SUM_10_), .Y(intadd_1142_B_9_) );
INVX2TS U2991 ( .A(intadd_1143_SUM_11_), .Y(intadd_1142_B_10_) );
INVX2TS U2992 ( .A(intadd_1143_SUM_12_), .Y(intadd_1142_B_11_) );
INVX2TS U2993 ( .A(n1577), .Y(intadd_1143_B_2_) );
INVX2TS U2994 ( .A(n1578), .Y(intadd_1143_B_3_) );
INVX2TS U2995 ( .A(n1579), .Y(intadd_1143_A_3_) );
INVX2TS U2996 ( .A(n1580), .Y(intadd_1143_B_4_) );
INVX2TS U2997 ( .A(n1581), .Y(intadd_1143_A_4_) );
INVX2TS U2998 ( .A(n1582), .Y(intadd_1143_B_5_) );
INVX2TS U2999 ( .A(n1583), .Y(intadd_1143_A_5_) );
INVX2TS U3000 ( .A(n1584), .Y(intadd_1143_B_6_) );
INVX2TS U3001 ( .A(n1585), .Y(intadd_1143_A_6_) );
INVX2TS U3002 ( .A(n1586), .Y(intadd_1143_B_7_) );
CMPR32X2TS U3003 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[6]), .B(
n2760), .C(n2759), .CO(n1587), .S(n1584) );
INVX2TS U3004 ( .A(n1587), .Y(intadd_1143_A_7_) );
INVX2TS U3005 ( .A(n1588), .Y(intadd_1143_B_8_) );
CMPR32X2TS U3006 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[7]), .B(
n2762), .C(n2761), .CO(n1589), .S(n1586) );
INVX2TS U3007 ( .A(n1589), .Y(intadd_1143_A_8_) );
INVX2TS U3008 ( .A(n1590), .Y(intadd_1143_B_9_) );
CMPR32X2TS U3009 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[8]), .B(
n2764), .C(n2763), .CO(n1591), .S(n1588) );
INVX2TS U3010 ( .A(n1591), .Y(intadd_1143_A_9_) );
INVX2TS U3011 ( .A(n1592), .Y(intadd_1143_B_10_) );
INVX2TS U3012 ( .A(n1593), .Y(intadd_1143_A_10_) );
INVX2TS U3013 ( .A(n1594), .Y(intadd_1143_B_11_) );
CMPR32X2TS U3014 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[10]), .B(
n2766), .C(n2769), .CO(n1595), .S(n1592) );
INVX2TS U3015 ( .A(n1595), .Y(intadd_1143_A_11_) );
CMPR32X2TS U3016 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[11]), .B(
n2768), .C(n2767), .CO(n1596), .S(n1594) );
INVX2TS U3017 ( .A(n1596), .Y(intadd_1143_B_12_) );
INVX2TS U3018 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[12]), .Y(
intadd_1143_A_12_) );
INVX2TS U3019 ( .A(intadd_1140_SUM_5_), .Y(intadd_1139_B_11_) );
INVX2TS U3020 ( .A(intadd_1140_SUM_6_), .Y(intadd_1139_B_12_) );
INVX2TS U3021 ( .A(intadd_1140_SUM_7_), .Y(intadd_1139_B_13_) );
INVX2TS U3022 ( .A(intadd_1140_SUM_8_), .Y(intadd_1139_B_14_) );
INVX2TS U3023 ( .A(intadd_1140_SUM_9_), .Y(intadd_1139_B_15_) );
INVX2TS U3024 ( .A(intadd_1140_SUM_10_), .Y(intadd_1139_B_16_) );
INVX2TS U3025 ( .A(intadd_1140_SUM_11_), .Y(intadd_1139_B_17_) );
INVX2TS U3026 ( .A(intadd_1140_SUM_12_), .Y(intadd_1139_B_18_) );
INVX2TS U3027 ( .A(intadd_1140_SUM_13_), .Y(intadd_1139_B_19_) );
INVX2TS U3028 ( .A(intadd_1140_SUM_14_), .Y(intadd_1139_B_20_) );
INVX2TS U3029 ( .A(intadd_1140_SUM_15_), .Y(intadd_1139_B_21_) );
INVX2TS U3030 ( .A(intadd_1140_SUM_16_), .Y(intadd_1139_B_22_) );
NAND2X1TS U3031 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[10]), .B(
DP_OP_499J326_125_1651_n31), .Y(n1660) );
OAI21X1TS U3032 ( .A0(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[10]), .A1(
DP_OP_499J326_125_1651_n31), .B0(n1660), .Y(n1597) );
NAND2X1TS U3033 ( .A(intadd_1140_n1), .B(n1597), .Y(n1659) );
INVX2TS U3034 ( .A(n1659), .Y(n1599) );
OAI31X1TS U3035 ( .A0(n1663), .A1(DP_OP_499J326_125_1651_n32), .A2(n1599),
.B0(n1598), .Y(intadd_1139_B_23_) );
INVX2TS U3036 ( .A(intadd_1156_n1), .Y(intadd_1140_B_1_) );
NAND2X1TS U3037 ( .A(n2747), .B(FPMULT_Sgf_operation_EVEN1_Q_left[1]), .Y(
intadd_1156_A_2_) );
INVX2TS U3038 ( .A(intadd_1140_SUM_0_), .Y(intadd_1156_B_7_) );
INVX2TS U3039 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[0]), .Y(
intadd_1145_CI) );
INVX2TS U3040 ( .A(intadd_1143_SUM_1_), .Y(intadd_1142_B_0_) );
NOR2X1TS U3041 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[1]), .B(
n2746), .Y(intadd_1143_A_2_) );
INVX2TS U3042 ( .A(DP_OP_499J326_125_1651_n78), .Y(intadd_1140_A_1_) );
INVX2TS U3043 ( .A(DP_OP_499J326_125_1651_n75), .Y(intadd_1140_B_2_) );
INVX2TS U3044 ( .A(DP_OP_499J326_125_1651_n77), .Y(intadd_1140_A_2_) );
INVX2TS U3045 ( .A(DP_OP_499J326_125_1651_n72), .Y(intadd_1140_B_3_) );
INVX2TS U3046 ( .A(DP_OP_499J326_125_1651_n74), .Y(intadd_1140_A_3_) );
INVX2TS U3047 ( .A(DP_OP_499J326_125_1651_n69), .Y(intadd_1140_B_4_) );
INVX2TS U3048 ( .A(DP_OP_499J326_125_1651_n71), .Y(intadd_1140_A_4_) );
INVX2TS U3049 ( .A(DP_OP_499J326_125_1651_n66), .Y(intadd_1140_B_5_) );
INVX2TS U3050 ( .A(DP_OP_499J326_125_1651_n68), .Y(intadd_1140_A_5_) );
INVX2TS U3051 ( .A(DP_OP_499J326_125_1651_n63), .Y(intadd_1140_B_6_) );
INVX2TS U3052 ( .A(DP_OP_499J326_125_1651_n65), .Y(intadd_1140_A_6_) );
INVX2TS U3053 ( .A(DP_OP_499J326_125_1651_n60), .Y(intadd_1140_B_7_) );
INVX2TS U3054 ( .A(DP_OP_499J326_125_1651_n62), .Y(intadd_1140_A_7_) );
INVX2TS U3055 ( .A(DP_OP_499J326_125_1651_n57), .Y(intadd_1140_B_8_) );
INVX2TS U3056 ( .A(DP_OP_499J326_125_1651_n59), .Y(intadd_1140_A_8_) );
INVX2TS U3057 ( .A(DP_OP_499J326_125_1651_n54), .Y(intadd_1140_B_9_) );
INVX2TS U3058 ( .A(DP_OP_499J326_125_1651_n56), .Y(intadd_1140_A_9_) );
INVX2TS U3059 ( .A(DP_OP_499J326_125_1651_n51), .Y(intadd_1140_B_10_) );
INVX2TS U3060 ( .A(DP_OP_499J326_125_1651_n53), .Y(intadd_1140_A_10_) );
INVX2TS U3061 ( .A(DP_OP_499J326_125_1651_n48), .Y(intadd_1140_B_11_) );
INVX2TS U3062 ( .A(DP_OP_499J326_125_1651_n50), .Y(intadd_1140_A_11_) );
INVX2TS U3063 ( .A(DP_OP_499J326_125_1651_n45), .Y(intadd_1140_B_12_) );
INVX2TS U3064 ( .A(DP_OP_499J326_125_1651_n47), .Y(intadd_1140_A_12_) );
INVX2TS U3065 ( .A(DP_OP_499J326_125_1651_n42), .Y(intadd_1140_B_13_) );
INVX2TS U3066 ( .A(DP_OP_499J326_125_1651_n44), .Y(intadd_1140_A_13_) );
INVX2TS U3067 ( .A(DP_OP_499J326_125_1651_n39), .Y(intadd_1140_B_14_) );
INVX2TS U3068 ( .A(DP_OP_499J326_125_1651_n41), .Y(intadd_1140_A_14_) );
INVX2TS U3069 ( .A(DP_OP_499J326_125_1651_n36), .Y(intadd_1140_B_15_) );
INVX2TS U3070 ( .A(DP_OP_499J326_125_1651_n38), .Y(intadd_1140_A_15_) );
INVX2TS U3071 ( .A(DP_OP_499J326_125_1651_n33), .Y(intadd_1140_B_16_) );
INVX2TS U3072 ( .A(DP_OP_499J326_125_1651_n35), .Y(intadd_1140_A_16_) );
NAND2X1TS U3073 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[6]), .B(n1633),
.Y(n1632) );
INVX2TS U3074 ( .A(n1632), .Y(intadd_1144_CI) );
NAND2X1TS U3075 ( .A(FPADDSUB_DMP_SFG[20]), .B(n960), .Y(n1609) );
INVX2TS U3076 ( .A(n1609), .Y(n1606) );
CLKAND2X2TS U3077 ( .A(n954), .B(FPADDSUB_DmP_mant_SFG_SWR[21]), .Y(n2265)
);
NAND2X1TS U3078 ( .A(FPADDSUB_DmP_mant_SFG_SWR[20]), .B(FPADDSUB_DMP_SFG[18]), .Y(n2259) );
NOR2X1TS U3079 ( .A(n2590), .B(n2502), .Y(n2252) );
NOR2X1TS U3080 ( .A(FPADDSUB_DMP_SFG[16]), .B(FPADDSUB_DmP_mant_SFG_SWR[18]),
.Y(n2247) );
NOR2X1TS U3081 ( .A(FPADDSUB_DMP_SFG[15]), .B(FPADDSUB_DmP_mant_SFG_SWR[17]),
.Y(n2242) );
NOR2X1TS U3082 ( .A(FPADDSUB_DMP_SFG[13]), .B(FPADDSUB_DmP_mant_SFG_SWR[15]),
.Y(n2232) );
NOR2X1TS U3083 ( .A(FPADDSUB_DMP_SFG[10]), .B(FPADDSUB_DmP_mant_SFG_SWR[12]),
.Y(n2217) );
NOR2X1TS U3084 ( .A(FPADDSUB_DMP_SFG[8]), .B(FPADDSUB_DmP_mant_SFG_SWR[10]),
.Y(n2207) );
AOI222X4TS U3085 ( .A0(n1600), .A1(n2485), .B0(n1600), .B1(n2527), .C0(n2485), .C1(n2527), .Y(n2203) );
AOI222X4TS U3086 ( .A0(n2224), .A1(n2534), .B0(n2224), .B1(n2486), .C0(n2534), .C1(n2486), .Y(n2228) );
AOI222X1TS U3087 ( .A0(FPADDSUB_DMP_SFG[14]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[16]), .B0(FPADDSUB_DMP_SFG[14]), .B1(n2239),
.C0(FPADDSUB_DmP_mant_SFG_SWR[16]), .C1(n2239), .Y(n2243) );
AOI2BB2X1TS U3088 ( .B0(FPADDSUB_DMP_SFG[15]), .B1(
FPADDSUB_DmP_mant_SFG_SWR[17]), .A0N(n2242), .A1N(n2243), .Y(n2248) );
OAI2BB2X1TS U3089 ( .B0(n2247), .B1(n2248), .A0N(FPADDSUB_DMP_SFG[16]),
.A1N(FPADDSUB_DmP_mant_SFG_SWR[18]), .Y(n2253) );
OAI22X1TS U3090 ( .A0(n2252), .A1(n2253), .B0(FPADDSUB_DmP_mant_SFG_SWR[19]),
.B1(FPADDSUB_DMP_SFG[17]), .Y(n2257) );
AOI2BB2X1TS U3091 ( .B0(n2259), .B1(n2257), .A0N(
FPADDSUB_DmP_mant_SFG_SWR[20]), .A1N(FPADDSUB_DMP_SFG[18]), .Y(n2262)
);
OR2X1TS U3092 ( .A(n954), .B(FPADDSUB_DmP_mant_SFG_SWR[21]), .Y(n2264) );
OAI211X1TS U3093 ( .A0(n2265), .A1(n2262), .B0(n963), .C0(n2264), .Y(n1610)
);
NAND2X1TS U3094 ( .A(FPADDSUB_DmP_mant_SFG_SWR[16]), .B(n2536), .Y(n2237) );
NAND2X1TS U3095 ( .A(FPADDSUB_DmP_mant_SFG_SWR[14]), .B(n2533), .Y(n2229) );
NOR2X1TS U3096 ( .A(FPADDSUB_DMP_SFG[11]), .B(n2486), .Y(n2222) );
NOR2X1TS U3097 ( .A(FPADDSUB_DMP_SFG[9]), .B(n2530), .Y(n2212) );
NOR2X1TS U3098 ( .A(FPADDSUB_DMP_SFG[7]), .B(n2528), .Y(n2202) );
AOI22X1TS U3099 ( .A0(FPADDSUB_DMP_SFG[6]), .A1(n2527), .B0(n1602), .B1(
n1601), .Y(n2204) );
OAI22X1TS U3100 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[13]), .A1(n2534), .B0(n2222),
.B1(n2223), .Y(n2227) );
AOI222X4TS U3101 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[19]), .A1(n2254), .B0(
FPADDSUB_DmP_mant_SFG_SWR[19]), .B1(n2502), .C0(n2254), .C1(n2502),
.Y(n2258) );
OAI2BB1X1TS U3102 ( .A0N(FPADDSUB_DmP_mant_SFG_SWR[21]), .A1N(n2263), .B0(
n954), .Y(n1603) );
NAND2X1TS U3103 ( .A(n1610), .B(n1608), .Y(n1605) );
OAI31X1TS U3104 ( .A0(n1606), .A1(n1605), .A2(n1611), .B0(n1604), .Y(
FPADDSUB_Raw_mant_SGF[22]) );
NAND2X1TS U3105 ( .A(FPADDSUB_DMP_SFG[21]), .B(n2627), .Y(n1616) );
NOR2X1TS U3106 ( .A(FPADDSUB_DMP_SFG[21]), .B(n2627), .Y(n1618) );
NOR2BX1TS U3107 ( .AN(n1616), .B(n1618), .Y(n1613) );
OAI21XLTS U3108 ( .A0(n1617), .A1(n1615), .B0(n1613), .Y(n1612) );
OAI31X1TS U3109 ( .A0(n1617), .A1(n1613), .A2(n1615), .B0(n1612), .Y(
FPADDSUB_Raw_mant_SGF[23]) );
AND3X1TS U3110 ( .A(FPADDSUB_DMP_SFG[21]), .B(n922), .C(
FPADDSUB_DmP_mant_SFG_SWR[23]), .Y(n1614) );
OAI22X1TS U3111 ( .A0(FPADDSUB_DMP_SFG[21]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[23]), .B0(n1615), .B1(n1614), .Y(n1989) );
AOI22X1TS U3112 ( .A0(n2269), .A1(n1618), .B0(n1617), .B1(n1616), .Y(n2270)
);
NAND2X1TS U3113 ( .A(n1989), .B(n2270), .Y(n1620) );
NAND2X1TS U3114 ( .A(FPMULT_Op_MX[3]), .B(FPMULT_Op_MY[1]), .Y(n1621) );
OAI32X1TS U3115 ( .A0(mult_x_310_n38), .A1(n2475), .A2(n1740), .B0(n1621),
.B1(mult_x_310_n38), .Y(mult_x_310_n39) );
NAND2X1TS U3116 ( .A(FPMULT_Op_MX[21]), .B(FPMULT_Op_MY[19]), .Y(n1622) );
OAI32X1TS U3117 ( .A0(mult_x_309_n38), .A1(n2501), .A2(n2532), .B0(n1622),
.B1(mult_x_309_n38), .Y(mult_x_309_n39) );
NAND2X1TS U3118 ( .A(FPMULT_Op_MX[15]), .B(n959), .Y(n1623) );
OAI32X1TS U3119 ( .A0(mult_x_312_n38), .A1(n2476), .A2(n1782), .B0(n1623),
.B1(mult_x_312_n38), .Y(mult_x_312_n39) );
NAND2X1TS U3120 ( .A(FPMULT_Op_MX[9]), .B(FPMULT_Op_MY[7]), .Y(n1624) );
OAI32X1TS U3121 ( .A0(mult_x_311_n38), .A1(n2491), .A2(n1762), .B0(n1624),
.B1(mult_x_311_n38), .Y(mult_x_311_n39) );
NAND2X1TS U3122 ( .A(n1932), .B(intadd_1158_n1), .Y(n1626) );
OAI21X1TS U3123 ( .A0(DP_OP_502J326_128_4510_n32), .A1(n1626), .B0(n1625),
.Y(DP_OP_502J326_128_4510_n76) );
NOR2XLTS U3124 ( .A(n1898), .B(n1627), .Y(intadd_1149_B_0_) );
NOR2X1TS U3125 ( .A(n1629), .B(n1628), .Y(DP_OP_501J326_127_5235_n226) );
NOR2XLTS U3126 ( .A(n1630), .B(n1919), .Y(intadd_1141_B_12_) );
INVX2TS U3127 ( .A(n1631), .Y(intadd_1160_A_3_) );
OAI21X1TS U3128 ( .A0(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[6]), .A1(n1633), .B0(n1632), .Y(n1657) );
INVX2TS U3129 ( .A(n1657), .Y(intadd_1139_A_17_) );
OAI21XLTS U3130 ( .A0(n2674), .A1(n951), .B0(n1360), .Y(n808) );
NOR3X2TS U3131 ( .A(n2503), .B(FPSENCOS_cont_iter_out[3]), .C(
FPSENCOS_cont_iter_out[2]), .Y(n2431) );
OAI32X1TS U3132 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(n2431), .A2(n2482),
.B0(FPSENCOS_cont_iter_out[2]), .B1(n2594), .Y(n858) );
NAND2X1TS U3133 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B(n2614),
.Y(n2428) );
NOR3XLTS U3134 ( .A(n2675), .B(FPSENCOS_cont_var_out_1_), .C(n930), .Y(
FPSENCOS_enab_d_ff4_Xn) );
OAI31X1TS U3135 ( .A0(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .A1(n2626),
.A2(n1634), .B0(n2314), .Y(FPSENCOS_enab_d_ff_RB1) );
XNOR2X1TS U3136 ( .A(DP_OP_234J326_132_4955_n1), .B(n1635), .Y(
FPMULT_Exp_module_Overflow_A) );
XOR2X1TS U3137 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n1636), .Y(
DP_OP_234J326_132_4955_n15) );
OR2X2TS U3138 ( .A(FPMULT_FSM_selector_B[1]), .B(n2592), .Y(n1643) );
OAI2BB1X1TS U3139 ( .A0N(FPMULT_Op_MY[29]), .A1N(n2595), .B0(n1643), .Y(
n1637) );
XOR2X1TS U3140 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n1637), .Y(
DP_OP_234J326_132_4955_n16) );
OAI2BB1X1TS U3141 ( .A0N(FPMULT_Op_MY[28]), .A1N(n2595), .B0(n1643), .Y(
n1638) );
XOR2X1TS U3142 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n1638), .Y(
DP_OP_234J326_132_4955_n17) );
OAI2BB1X1TS U3143 ( .A0N(FPMULT_Op_MY[27]), .A1N(n2595), .B0(n1643), .Y(
n1639) );
XOR2X1TS U3144 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n1639), .Y(
DP_OP_234J326_132_4955_n18) );
OAI2BB1X1TS U3145 ( .A0N(FPMULT_Op_MY[26]), .A1N(n2595), .B0(n1643), .Y(
n1640) );
XOR2X1TS U3146 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n1640), .Y(
DP_OP_234J326_132_4955_n19) );
OAI2BB1X1TS U3147 ( .A0N(FPMULT_Op_MY[25]), .A1N(n2595), .B0(n1643), .Y(
n1641) );
XOR2X1TS U3148 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n1641), .Y(
DP_OP_234J326_132_4955_n20) );
OAI2BB1X1TS U3149 ( .A0N(FPMULT_Op_MY[24]), .A1N(n2595), .B0(n1643), .Y(
n1642) );
XOR2X1TS U3150 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n1642), .Y(
DP_OP_234J326_132_4955_n21) );
NOR2XLTS U3151 ( .A(FPMULT_FSM_selector_B[1]), .B(FPMULT_Op_MY[23]), .Y(
n1644) );
OAI21XLTS U3152 ( .A0(FPMULT_FSM_selector_B[0]), .A1(n1644), .B0(n1643), .Y(
n1645) );
XOR2X1TS U3153 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n1645), .Y(
DP_OP_234J326_132_4955_n22) );
NOR2BX1TS U3154 ( .AN(FPADDSUB_LZD_output_NRM2_EW[2]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n1646) );
XOR2X1TS U3155 ( .A(n951), .B(n1646), .Y(DP_OP_26J326_129_1325_n16) );
NOR2BX1TS U3156 ( .AN(FPADDSUB_LZD_output_NRM2_EW[1]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n1647) );
XOR2X1TS U3157 ( .A(n951), .B(n1647), .Y(DP_OP_26J326_129_1325_n17) );
XOR2X1TS U3158 ( .A(n951), .B(n1648), .Y(DP_OP_26J326_129_1325_n18) );
NOR2XLTS U3159 ( .A(n2790), .B(FPMULT_FSM_adder_round_norm_load), .Y(n1649)
);
OAI2BB1X1TS U3160 ( .A0N(FPMULT_FSM_selector_B[0]), .A1N(n1650), .B0(n1649),
.Y(n829) );
NOR2BX1TS U3161 ( .AN(FPADDSUB_exp_rslt_NRM2_EW1[7]), .B(n2784), .Y(
FPADDSUB_formatted_number_W[30]) );
AOI2BB1XLTS U3162 ( .A0N(n2783), .A1N(FPADDSUB_SIGN_FLAG_SHT1SHT2), .B0(
n2784), .Y(FPADDSUB_formatted_number_W[31]) );
CMPR32X2TS U3163 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[7]), .B(n2731), .C(n2730), .CO(intadd_1146_A_6_), .S(intadd_1146_A_5_) );
NAND2X1TS U3164 ( .A(n1653), .B(n1652), .Y(intadd_1146_A_1_) );
CMPR32X2TS U3165 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[6]), .B(n2737), .C(n2736), .CO(intadd_1146_B_5_), .S(intadd_1146_B_4_) );
CMPR32X2TS U3166 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[8]), .B(n2739), .C(n2738), .CO(intadd_1146_A_7_), .S(intadd_1146_B_6_) );
CMPR32X2TS U3167 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[9]), .B(n2740), .C(n2771), .CO(intadd_1146_B_8_), .S(intadd_1146_B_7_) );
CMPR32X2TS U3168 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[11]), .B(
n2742), .C(n2741), .CO(intadd_1146_B_10_), .S(intadd_1146_B_9_) );
XNOR2X1TS U3169 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[13]), .B(
intadd_1146_n1), .Y(intadd_1144_B_12_) );
AO21XLTS U3170 ( .A0(n1654), .A1(n2743), .B0(n928), .Y(intadd_1144_B_0_) );
AOI21X1TS U3171 ( .A0(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[1]), .A1(
n2746), .B0(intadd_1143_A_2_), .Y(intadd_1143_B_1_) );
AO21XLTS U3172 ( .A0(intadd_1145_SUM_0_), .A1(n1655), .B0(
DP_OP_499J326_125_1651_n81), .Y(intadd_1140_B_0_) );
INVX2TS U3173 ( .A(n1656), .Y(n1658) );
CMPR32X2TS U3174 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[6]), .B(n1658), .C(n1657), .CO(intadd_1156_A_7_), .S(intadd_1156_B_6_) );
NAND2X1TS U3175 ( .A(DP_OP_499J326_125_1651_n32), .B(n1659), .Y(n1661) );
NAND2X1TS U3176 ( .A(n1661), .B(n1660), .Y(n1662) );
OAI22X1TS U3177 ( .A0(n1663), .A1(n1662), .B0(n1661), .B1(n1660), .Y(n1664)
);
XOR2X1TS U3178 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[11]), .B(n1664), .Y(intadd_1139_B_24_) );
XOR2X1TS U3179 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[13]), .B(
intadd_1143_n1), .Y(intadd_1142_B_12_) );
NAND2X1TS U3180 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]), .B(n1667),
.Y(n1665) );
NOR2X1TS U3181 ( .A(DP_OP_499J326_125_1651_n119), .B(n1665), .Y(n1676) );
AOI21X1TS U3182 ( .A0(DP_OP_499J326_125_1651_n119), .A1(n1665), .B0(n1676),
.Y(FPMULT_Sgf_operation_Result[46]) );
INVX2TS U3183 ( .A(DP_OP_499J326_125_1651_n120), .Y(n1666) );
OA21XLTS U3184 ( .A0(n1667), .A1(n1666), .B0(n1665), .Y(
FPMULT_Sgf_operation_Result[45]) );
AOI21X1TS U3185 ( .A0(DP_OP_499J326_125_1651_n121), .A1(n1668), .B0(n1667),
.Y(FPMULT_Sgf_operation_Result[44]) );
AOI21X1TS U3186 ( .A0(DP_OP_499J326_125_1651_n123), .A1(n1670), .B0(n1669),
.Y(FPMULT_Sgf_operation_Result[42]) );
AOI21X1TS U3187 ( .A0(DP_OP_499J326_125_1651_n125), .A1(n1672), .B0(n1671),
.Y(FPMULT_Sgf_operation_Result[40]) );
AOI21X1TS U3188 ( .A0(DP_OP_499J326_125_1651_n126), .A1(n1674), .B0(n1673),
.Y(FPMULT_Sgf_operation_Result[39]) );
XNOR2X1TS U3189 ( .A(n1675), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[11]), .Y(
DP_OP_499J326_125_1651_n118) );
MXI2X1TS U3190 ( .A(DP_OP_499J326_125_1651_n118), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[11]), .S0(n1676), .Y(FPMULT_Sgf_operation_Result[47]) );
AOI21X1TS U3191 ( .A0(n1678), .A1(n1677), .B0(
FPMULT_Adder_M_result_A_adder[24]), .Y(
FPMULT_Adder_M_result_A_adder[23]) );
OA21XLTS U3192 ( .A0(FPMULT_Sgf_normalized_result[22]), .A1(n1679), .B0(
n1678), .Y(FPMULT_Adder_M_result_A_adder[22]) );
AOI21X1TS U3193 ( .A0(n1680), .A1(n1681), .B0(n1679), .Y(
FPMULT_Adder_M_result_A_adder[21]) );
OA21XLTS U3194 ( .A0(FPMULT_Sgf_normalized_result[20]), .A1(n1682), .B0(
n1681), .Y(FPMULT_Adder_M_result_A_adder[20]) );
AOI21X1TS U3195 ( .A0(n1683), .A1(n1684), .B0(n1682), .Y(
FPMULT_Adder_M_result_A_adder[19]) );
OA21XLTS U3196 ( .A0(FPMULT_Sgf_normalized_result[18]), .A1(n1685), .B0(
n1684), .Y(FPMULT_Adder_M_result_A_adder[18]) );
AOI21X1TS U3197 ( .A0(n1686), .A1(n1687), .B0(n1685), .Y(
FPMULT_Adder_M_result_A_adder[17]) );
OA21XLTS U3198 ( .A0(FPMULT_Sgf_normalized_result[16]), .A1(n1688), .B0(
n1687), .Y(FPMULT_Adder_M_result_A_adder[16]) );
AOI21X1TS U3199 ( .A0(n1689), .A1(n1690), .B0(n1688), .Y(
FPMULT_Adder_M_result_A_adder[15]) );
OA21XLTS U3200 ( .A0(FPMULT_Sgf_normalized_result[14]), .A1(n1691), .B0(
n1690), .Y(FPMULT_Adder_M_result_A_adder[14]) );
AOI21X1TS U3201 ( .A0(n1692), .A1(n1693), .B0(n1691), .Y(
FPMULT_Adder_M_result_A_adder[13]) );
OA21XLTS U3202 ( .A0(FPMULT_Sgf_normalized_result[12]), .A1(n1694), .B0(
n1693), .Y(FPMULT_Adder_M_result_A_adder[12]) );
AOI21X1TS U3203 ( .A0(n1695), .A1(n1696), .B0(n1694), .Y(
FPMULT_Adder_M_result_A_adder[11]) );
OA21XLTS U3204 ( .A0(FPMULT_Sgf_normalized_result[10]), .A1(n1697), .B0(
n1696), .Y(FPMULT_Adder_M_result_A_adder[10]) );
AOI21X1TS U3205 ( .A0(n1698), .A1(n1699), .B0(n1697), .Y(
FPMULT_Adder_M_result_A_adder[9]) );
OA21XLTS U3206 ( .A0(FPMULT_Sgf_normalized_result[8]), .A1(n1700), .B0(n1699), .Y(FPMULT_Adder_M_result_A_adder[8]) );
AOI21X1TS U3207 ( .A0(n1701), .A1(n1702), .B0(n1700), .Y(
FPMULT_Adder_M_result_A_adder[7]) );
OA21XLTS U3208 ( .A0(FPMULT_Sgf_normalized_result[6]), .A1(n1703), .B0(n1702), .Y(FPMULT_Adder_M_result_A_adder[6]) );
AOI21X1TS U3209 ( .A0(n1708), .A1(n1704), .B0(n1703), .Y(
FPMULT_Adder_M_result_A_adder[5]) );
AOI21X1TS U3210 ( .A0(n1706), .A1(n1705), .B0(n1709), .Y(
FPMULT_Adder_M_result_A_adder[3]) );
AO21XLTS U3211 ( .A0(FPMULT_Sgf_normalized_result[2]), .A1(n1707), .B0(n1706), .Y(FPMULT_Adder_M_result_A_adder[2]) );
AO21XLTS U3212 ( .A0(n1709), .A1(FPMULT_Sgf_normalized_result[4]), .B0(n1708), .Y(FPMULT_Adder_M_result_A_adder[4]) );
NAND3XLTS U3213 ( .A(FPMULT_Op_MX[20]), .B(mult_x_309_n33), .C(
mult_x_309_n26), .Y(n1714) );
NOR3X1TS U3214 ( .A(n2487), .B(n2469), .C(n1725), .Y(n1711) );
INVX2TS U3215 ( .A(mult_x_309_n26), .Y(n1710) );
OAI32X1TS U3216 ( .A0(n1711), .A1(n2549), .A2(n2487), .B0(n1710), .B1(n1711),
.Y(n1721) );
OAI32X1TS U3217 ( .A0(n1713), .A1(n2492), .A2(n2532), .B0(FPMULT_Op_MX[20]),
.B1(n1712), .Y(n1720) );
NAND2X1TS U3218 ( .A(n1721), .B(n1720), .Y(n1719) );
NAND2X1TS U3219 ( .A(n1714), .B(n1719), .Y(intadd_1157_A_0_) );
OAI32X1TS U3220 ( .A0(mult_x_309_n42), .A1(n2469), .A2(n2492), .B0(n1715),
.B1(mult_x_309_n42), .Y(intadd_1157_B_0_) );
NOR2XLTS U3221 ( .A(n2487), .B(n2550), .Y(n1718) );
OAI21XLTS U3222 ( .A0(n2487), .A1(n2469), .B0(n1716), .Y(n1717) );
XNOR2X1TS U3223 ( .A(n1718), .B(n1717), .Y(intadd_1157_CI) );
OA21XLTS U3224 ( .A0(n1721), .A1(n1720), .B0(n1719), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2) );
NOR2XLTS U3225 ( .A(n2501), .B(n2550), .Y(n1722) );
CMPR32X2TS U3226 ( .A(FPMULT_Op_MX[20]), .B(FPMULT_Op_MY[20]), .C(n1722),
.CO(mult_x_309_n19), .S(mult_x_309_n20) );
OAI2BB1X1TS U3227 ( .A0N(mult_x_309_n52), .A1N(mult_x_309_n66), .B0(n1723),
.Y(mult_x_309_n24) );
AOI21X1TS U3228 ( .A0(n2494), .A1(n2469), .B0(mult_x_309_n26), .Y(
mult_x_309_n27) );
OAI31X1TS U3229 ( .A0(n2548), .A1(n2474), .A2(n1725), .B0(n1724), .Y(
mult_x_309_n31) );
AOI21X1TS U3230 ( .A0(n2487), .A1(n2532), .B0(mult_x_309_n33), .Y(
mult_x_309_n34) );
AOI22X1TS U3231 ( .A0(FPMULT_Op_MX[5]), .A1(FPMULT_Op_MY[4]), .B0(
FPMULT_Op_MX[4]), .B1(FPMULT_Op_MY[5]), .Y(n1726) );
AOI21X1TS U3232 ( .A0(intadd_1155_A_7_), .A1(mult_x_310_n53), .B0(n1726),
.Y(n1727) );
NAND2X1TS U3233 ( .A(n1727), .B(mult_x_310_n13), .Y(n1732) );
OA21XLTS U3234 ( .A0(n1727), .A1(mult_x_310_n13), .B0(n1732), .Y(
intadd_1155_B_6_) );
NOR2XLTS U3235 ( .A(n2473), .B(n2472), .Y(n1730) );
OA21XLTS U3236 ( .A0(n1730), .A1(n1729), .B0(n1728), .Y(intadd_1155_A_0_) );
OAI32X1TS U3237 ( .A0(mult_x_310_n42), .A1(n2489), .A2(n2540), .B0(n1731),
.B1(mult_x_310_n42), .Y(intadd_1155_B_0_) );
OAI2BB1X1TS U3238 ( .A0N(intadd_1155_A_7_), .A1N(mult_x_310_n53), .B0(n1732),
.Y(intadd_1155_B_7_) );
OAI31X1TS U3239 ( .A0(n2551), .A1(n2480), .A2(n1738), .B0(n1735), .Y(
mult_x_310_n24) );
OAI32X1TS U3240 ( .A0(mult_x_310_n26), .A1(n2499), .A2(n2475), .B0(n1736),
.B1(mult_x_310_n26), .Y(mult_x_310_n27) );
OAI32X1TS U3241 ( .A0(mult_x_310_n33), .A1(n2546), .A2(n1740), .B0(n1739),
.B1(mult_x_310_n33), .Y(mult_x_310_n34) );
AOI22X1TS U3242 ( .A0(FPMULT_Op_MX[11]), .A1(FPMULT_Op_MY[10]), .B0(
FPMULT_Op_MY[11]), .B1(FPMULT_Op_MX[10]), .Y(n1741) );
AOI21X1TS U3243 ( .A0(intadd_1154_A_7_), .A1(mult_x_311_n53), .B0(n1741),
.Y(n1743) );
NAND2X1TS U3244 ( .A(n1743), .B(mult_x_311_n13), .Y(n1742) );
OAI2BB1X1TS U3245 ( .A0N(intadd_1154_A_7_), .A1N(mult_x_311_n53), .B0(n1742),
.Y(intadd_1154_B_7_) );
OA21XLTS U3246 ( .A0(n1743), .A1(mult_x_311_n13), .B0(n1742), .Y(
intadd_1154_B_6_) );
NOR2XLTS U3247 ( .A(n2484), .B(n2470), .Y(n1746) );
OA21XLTS U3248 ( .A0(n1746), .A1(n1745), .B0(n1744), .Y(intadd_1154_A_0_) );
OAI32X1TS U3249 ( .A0(mult_x_311_n42), .A1(n2538), .A2(n2477), .B0(n1747),
.B1(mult_x_311_n42), .Y(intadd_1154_B_0_) );
OA21XLTS U3250 ( .A0(n1750), .A1(n1749), .B0(n1748), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2) );
OAI31X1TS U3251 ( .A0(n2552), .A1(n2498), .A2(n1757), .B0(n1753), .Y(
mult_x_311_n24) );
OAI32X1TS U3252 ( .A0(mult_x_311_n26), .A1(n2545), .A2(n2491), .B0(n1754),
.B1(mult_x_311_n26), .Y(mult_x_311_n27) );
NOR3X1TS U3253 ( .A(n2484), .B(n2470), .C(n1757), .Y(n1756) );
NAND2X1TS U3254 ( .A(FPMULT_Op_MX[8]), .B(FPMULT_Op_MY[9]), .Y(n1755) );
OAI32X1TS U3255 ( .A0(n1756), .A1(n2542), .A2(n2484), .B0(n1755), .B1(n1756),
.Y(n1759) );
NAND3XLTS U3256 ( .A(FPMULT_Op_MX[9]), .B(FPMULT_Op_MY[8]), .C(n1759), .Y(
n1758) );
OAI31X1TS U3257 ( .A0(n2470), .A1(n2484), .A2(n1757), .B0(n1758), .Y(
mult_x_311_n31) );
NOR2XLTS U3258 ( .A(n2493), .B(n2545), .Y(n1760) );
OA21XLTS U3259 ( .A0(n1760), .A1(n1759), .B0(n1758), .Y(mult_x_311_n32) );
OAI32X1TS U3260 ( .A0(mult_x_311_n33), .A1(n2488), .A2(n1762), .B0(n1761),
.B1(mult_x_311_n33), .Y(mult_x_311_n34) );
AOI22X1TS U3261 ( .A0(FPMULT_Op_MX[17]), .A1(FPMULT_Op_MY[16]), .B0(
FPMULT_Op_MY[17]), .B1(FPMULT_Op_MX[16]), .Y(n1763) );
AOI21X1TS U3262 ( .A0(intadd_1153_A_7_), .A1(mult_x_312_n53), .B0(n1763),
.Y(n1765) );
NAND2X1TS U3263 ( .A(n1765), .B(mult_x_312_n13), .Y(n1764) );
OAI2BB1X1TS U3264 ( .A0N(intadd_1153_A_7_), .A1N(mult_x_312_n53), .B0(n1764),
.Y(intadd_1153_B_7_) );
OA21XLTS U3265 ( .A0(n1765), .A1(mult_x_312_n13), .B0(n1764), .Y(
intadd_1153_B_6_) );
NOR2XLTS U3266 ( .A(n1777), .B(n2471), .Y(n1768) );
OA21XLTS U3267 ( .A0(n1768), .A1(n1767), .B0(n1766), .Y(intadd_1153_A_0_) );
OAI32X1TS U3268 ( .A0(mult_x_312_n42), .A1(n2490), .A2(n2541), .B0(n1769),
.B1(mult_x_312_n42), .Y(intadd_1153_B_0_) );
OAI31X1TS U3269 ( .A0(n2553), .A1(n2481), .A2(n1776), .B0(n1772), .Y(
mult_x_312_n24) );
OAI32X1TS U3270 ( .A0(mult_x_312_n26), .A1(n2500), .A2(n2476), .B0(n1773),
.B1(mult_x_312_n26), .Y(mult_x_312_n27) );
NAND2X1TS U3271 ( .A(FPMULT_Op_MX[14]), .B(FPMULT_Op_MY[15]), .Y(n1774) );
OAI32X1TS U3272 ( .A0(n1775), .A1(n2495), .A2(n1777), .B0(n1774), .B1(n1775),
.Y(n1779) );
NAND3XLTS U3273 ( .A(FPMULT_Op_MX[15]), .B(FPMULT_Op_MY[14]), .C(n1779), .Y(
n1778) );
OAI31X1TS U3274 ( .A0(n2471), .A1(n1777), .A2(n1776), .B0(n1778), .Y(
mult_x_312_n31) );
NOR2XLTS U3275 ( .A(n2479), .B(n2500), .Y(n1780) );
OA21XLTS U3276 ( .A0(n1780), .A1(n1779), .B0(n1778), .Y(mult_x_312_n32) );
OAI32X1TS U3277 ( .A0(mult_x_312_n33), .A1(n2547), .A2(n1782), .B0(n1781),
.B1(mult_x_312_n33), .Y(mult_x_312_n34) );
INVX2TS U3278 ( .A(n1783), .Y(n1827) );
AOI22X1TS U3279 ( .A0(intadd_1147_SUM_2_), .A1(n1810), .B0(
intadd_1148_SUM_2_), .B1(n1821), .Y(n1824) );
INVX2TS U3280 ( .A(n1786), .Y(n1825) );
AOI22X1TS U3281 ( .A0(intadd_1148_SUM_1_), .A1(n1821), .B0(
intadd_1147_SUM_2_), .B1(n1784), .Y(n1787) );
OAI22X1TS U3282 ( .A0(n1827), .A1(n1824), .B0(n1825), .B1(n1787), .Y(
intadd_1150_A_1_) );
OAI2BB2XLTS U3283 ( .B0(n1827), .B1(n1787), .A0N(n1786), .A1N(n1785), .Y(
intadd_1150_A_0_) );
OAI22X1TS U3284 ( .A0(n1791), .A1(n1790), .B0(n1789), .B1(n1788), .Y(
intadd_1150_B_1_) );
INVX2TS U3285 ( .A(intadd_1148_SUM_3_), .Y(n1822) );
OAI22X1TS U3286 ( .A0(n1819), .A1(n1806), .B0(n1822), .B1(n1804), .Y(n1793)
);
CMPR32X2TS U3287 ( .A(mult_x_313_n21), .B(n1793), .C(n1792), .CO(
intadd_1150_B_8_), .S(intadd_1150_B_7_) );
AOI21X1TS U3288 ( .A0(n1796), .A1(n1795), .B0(mult_x_313_n42), .Y(n1800) );
NOR2XLTS U3289 ( .A(n1798), .B(n1797), .Y(n1799) );
CMPR32X2TS U3290 ( .A(n1800), .B(n1799), .C(intadd_1150_SUM_1_), .CO(
intadd_1150_B_2_), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N5) );
AOI21X1TS U3291 ( .A0(n1803), .A1(n1802), .B0(n1801), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N3) );
OAI22X1TS U3292 ( .A0(n1810), .A1(n1804), .B0(n1822), .B1(n1806), .Y(
mult_x_313_n54) );
OAI22X1TS U3293 ( .A0(n1807), .A1(n1806), .B0(n1805), .B1(n1804), .Y(
mult_x_313_n55) );
AOI22X1TS U3294 ( .A0(intadd_1148_SUM_4_), .A1(intadd_1147_SUM_4_), .B0(
n1811), .B1(n1819), .Y(n1809) );
AO22XLTS U3295 ( .A0(n1816), .A1(n1808), .B0(n1814), .B1(n1809), .Y(
mult_x_313_n58) );
AOI22X1TS U3296 ( .A0(intadd_1148_SUM_3_), .A1(intadd_1147_SUM_4_), .B0(
n1811), .B1(n1822), .Y(n1812) );
AO22XLTS U3297 ( .A0(n1816), .A1(n1809), .B0(n1814), .B1(n1812), .Y(
mult_x_313_n59) );
AOI22X1TS U3298 ( .A0(intadd_1148_SUM_2_), .A1(intadd_1147_SUM_4_), .B0(
n1811), .B1(n1810), .Y(n1815) );
AO22XLTS U3299 ( .A0(n1816), .A1(n1812), .B0(n1814), .B1(n1815), .Y(
mult_x_313_n60) );
AO22XLTS U3300 ( .A0(n1816), .A1(n1815), .B0(n1814), .B1(n1813), .Y(
mult_x_313_n61) );
AOI22X1TS U3301 ( .A0(intadd_1147_SUM_2_), .A1(n1817), .B0(
intadd_1148_SUM_5_), .B1(n1821), .Y(n1820) );
OAI22X1TS U3302 ( .A0(n1818), .A1(mult_x_313_n65), .B0(n1820), .B1(n1825),
.Y(mult_x_313_n66) );
AOI22X1TS U3303 ( .A0(intadd_1147_SUM_2_), .A1(n1819), .B0(
intadd_1148_SUM_4_), .B1(n1821), .Y(n1823) );
OAI22X1TS U3304 ( .A0(n1827), .A1(n1820), .B0(n1825), .B1(n1823), .Y(
mult_x_313_n67) );
AOI22X1TS U3305 ( .A0(intadd_1147_SUM_2_), .A1(n1822), .B0(
intadd_1148_SUM_3_), .B1(n1821), .Y(n1826) );
OAI22X1TS U3306 ( .A0(n1827), .A1(n1823), .B0(n1825), .B1(n1826), .Y(
mult_x_313_n68) );
OAI22X1TS U3307 ( .A0(n1827), .A1(n1826), .B0(n1825), .B1(n1824), .Y(
mult_x_313_n69) );
AOI21X1TS U3308 ( .A0(intadd_1148_SUM_5_), .A1(n1828), .B0(mult_x_313_n74),
.Y(mult_x_313_n75) );
AOI21X1TS U3309 ( .A0(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[1]), .A1(
n2772), .B0(intadd_1145_A_2_), .Y(intadd_1145_B_1_) );
INVX2TS U3310 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[2]), .Y(
n1829) );
INVX2TS U3311 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[3]), .Y(
n1830) );
INVX2TS U3312 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[4]), .Y(
n1831) );
CMPR32X2TS U3313 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[4]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[4]), .C(n1831), .CO(intadd_1145_A_5_), .S(intadd_1145_B_4_) );
INVX2TS U3314 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[5]), .Y(
n1832) );
CMPR32X2TS U3315 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[5]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[5]), .C(n1832), .CO(intadd_1145_A_6_), .S(intadd_1145_B_5_) );
INVX2TS U3316 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[6]), .Y(
n1833) );
CMPR32X2TS U3317 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[6]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[6]), .C(n1833), .CO(intadd_1145_A_7_), .S(intadd_1145_B_6_) );
INVX2TS U3318 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[7]), .Y(
n1834) );
CMPR32X2TS U3319 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[7]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[7]), .C(n1834), .CO(intadd_1145_A_8_), .S(intadd_1145_B_7_) );
INVX2TS U3320 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[8]), .Y(
n1835) );
CMPR32X2TS U3321 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[8]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[8]), .C(n1835), .CO(intadd_1145_A_9_), .S(intadd_1145_B_8_) );
INVX2TS U3322 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[9]), .Y(
n1836) );
CMPR32X2TS U3323 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[9]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[9]), .C(n1836), .CO(intadd_1145_A_10_), .S(intadd_1145_B_9_) );
INVX2TS U3324 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[10]), .Y(
n1837) );
CMPR32X2TS U3325 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[10]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[10]), .C(
n1837), .CO(intadd_1145_A_11_), .S(intadd_1145_B_10_) );
CMPR32X2TS U3326 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[11]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[11]), .C(
n1838), .CO(n1520), .S(intadd_1145_B_11_) );
CMPR32X2TS U3327 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[14]), .B(
n1843), .C(n1842), .CO(n1100), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[14]) );
AOI22X1TS U3328 ( .A0(n1883), .A1(n1869), .B0(intadd_1162_SUM_3_), .B1(n1880), .Y(n1844) );
AOI32X1TS U3329 ( .A0(n1883), .A1(DP_OP_500J326_126_4510_n27), .A2(n1869),
.B0(DP_OP_500J326_126_4510_n32), .B1(n1844), .Y(intadd_1152_B_0_) );
CMPR32X2TS U3330 ( .A(n1847), .B(n1846), .C(n1845), .CO(n1477), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N5) );
AOI21X1TS U3331 ( .A0(n1850), .A1(n1849), .B0(n1848), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N3) );
INVX2TS U3332 ( .A(intadd_1162_SUM_3_), .Y(n1872) );
AOI22X1TS U3333 ( .A0(n1854), .A1(n1857), .B0(n1872), .B1(n1851), .Y(
DP_OP_500J326_126_4510_n52) );
AOI22X1TS U3334 ( .A0(n1854), .A1(n1859), .B0(n1857), .B1(n1851), .Y(
DP_OP_500J326_126_4510_n53) );
AOI22X1TS U3335 ( .A0(n1854), .A1(n1852), .B0(n1859), .B1(n1851), .Y(
DP_OP_500J326_126_4510_n54) );
AOI22X1TS U3336 ( .A0(n1854), .A1(n1853), .B0(n1852), .B1(n1851), .Y(
DP_OP_500J326_126_4510_n55) );
AOI22X1TS U3337 ( .A0(n1478), .A1(n1869), .B0(n1882), .B1(n1860), .Y(n1856)
);
OAI22X1TS U3338 ( .A0(n1862), .A1(n1856), .B0(n1855), .B1(n1864), .Y(
DP_OP_500J326_126_4510_n59) );
AOI22X1TS U3339 ( .A0(n1478), .A1(intadd_1162_SUM_3_), .B0(n1872), .B1(n1860), .Y(n1858) );
OAI22X1TS U3340 ( .A0(n1858), .A1(n1862), .B0(n1864), .B1(n1856), .Y(
DP_OP_500J326_126_4510_n60) );
AOI22X1TS U3341 ( .A0(intadd_1162_SUM_2_), .A1(n1478), .B0(n1860), .B1(n1857), .Y(n1861) );
OAI22X1TS U3342 ( .A0(n1858), .A1(n1864), .B0(n1861), .B1(n1862), .Y(
DP_OP_500J326_126_4510_n61) );
AOI22X1TS U3343 ( .A0(intadd_1162_SUM_1_), .A1(n1478), .B0(n1860), .B1(n1859), .Y(n1865) );
OAI22X1TS U3344 ( .A0(n1861), .A1(n1864), .B0(n1865), .B1(n1862), .Y(
DP_OP_500J326_126_4510_n62) );
OAI22X1TS U3345 ( .A0(n1865), .A1(n1864), .B0(n1863), .B1(n1862), .Y(
DP_OP_500J326_126_4510_n63) );
AOI22X1TS U3346 ( .A0(intadd_1163_SUM_2_), .A1(n1881), .B0(n1879), .B1(n1871), .Y(n1870) );
INVX2TS U3347 ( .A(n1876), .Y(n1873) );
OAI22X1TS U3348 ( .A0(n1868), .A1(n1867), .B0(n1870), .B1(n1873), .Y(
DP_OP_500J326_126_4510_n67) );
AOI22X1TS U3349 ( .A0(intadd_1163_SUM_2_), .A1(n1882), .B0(n1869), .B1(n1871), .Y(n1874) );
OAI22X1TS U3350 ( .A0(n1870), .A1(n1878), .B0(n1874), .B1(n1873), .Y(
DP_OP_500J326_126_4510_n68) );
AOI22X1TS U3351 ( .A0(intadd_1163_SUM_2_), .A1(n1872), .B0(
intadd_1162_SUM_3_), .B1(n1871), .Y(n1877) );
OAI22X1TS U3352 ( .A0(n1874), .A1(n1878), .B0(n1873), .B1(n1877), .Y(
DP_OP_500J326_126_4510_n69) );
AOI21X1TS U3353 ( .A0(n1880), .A1(n1879), .B0(DP_OP_500J326_126_4510_n27),
.Y(DP_OP_500J326_126_4510_n75) );
NOR2X1TS U3354 ( .A(n1881), .B(n1880), .Y(n1885) );
OAI22X1TS U3355 ( .A0(n1883), .A1(n1882), .B0(DP_OP_500J326_126_4510_n32),
.B1(n1885), .Y(n1884) );
AOI21X1TS U3356 ( .A0(DP_OP_500J326_126_4510_n32), .A1(n1885), .B0(n1884),
.Y(DP_OP_500J326_126_4510_n76) );
NAND4XLTS U3357 ( .A(FPMULT_Op_MX[11]), .B(FPMULT_Op_MY[11]), .C(
intadd_1148_n1), .D(intadd_1147_n1), .Y(n1887) );
AOI22X1TS U3358 ( .A0(intadd_1159_A_4_), .A1(intadd_1160_A_3_), .B0(
intadd_1159_A_3_), .B1(intadd_1160_A_4_), .Y(n1886) );
NOR2BX1TS U3359 ( .AN(n1887), .B(n1886), .Y(n1889) );
NAND2X1TS U3360 ( .A(n1889), .B(DP_OP_501J326_127_5235_n13), .Y(n1888) );
NAND2X1TS U3361 ( .A(n1887), .B(n1888), .Y(intadd_1149_A_8_) );
OA21XLTS U3362 ( .A0(n1889), .A1(DP_OP_501J326_127_5235_n13), .B0(n1888),
.Y(intadd_1149_B_7_) );
AOI31XLTS U3363 ( .A0(intadd_1148_SUM_9_), .A1(intadd_1147_SUM_9_), .A2(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N0), .B0(n1890), .Y(n1892) );
XNOR2X1TS U3364 ( .A(n1892), .B(n1891), .Y(intadd_1149_B_1_) );
OA21XLTS U3365 ( .A0(n1908), .A1(n1894), .B0(n1893), .Y(
DP_OP_501J326_127_5235_n25) );
NAND2X1TS U3366 ( .A(intadd_1147_SUM_9_), .B(intadd_1148_SUM_9_), .Y(n1895)
);
OAI32X1TS U3367 ( .A0(n1897), .A1(n1899), .A2(n1896), .B0(n1895), .B1(n1897),
.Y(DP_OP_501J326_127_5235_n27) );
NOR2XLTS U3368 ( .A(n1899), .B(n1898), .Y(n1904) );
NOR2XLTS U3369 ( .A(n1901), .B(n1900), .Y(n1902) );
NAND2X1TS U3370 ( .A(intadd_1148_SUM_9_), .B(intadd_1147_SUM_8_), .Y(n1905)
);
OAI32X1TS U3371 ( .A0(n1908), .A1(n1907), .A2(n1906), .B0(n1905), .B1(n1908),
.Y(DP_OP_501J326_127_5235_n34) );
AOI21X1TS U3372 ( .A0(n1910), .A1(n1909), .B0(intadd_1141_A_12_), .Y(
intadd_1141_B_11_) );
NOR2XLTS U3373 ( .A(n1911), .B(n1918), .Y(intadd_1141_B_0_) );
AOI31XLTS U3374 ( .A0(intadd_1159_SUM_2_), .A1(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N0), .A2(intadd_1160_SUM_2_), .B0(n1912), .Y(n1914) );
XNOR2X1TS U3375 ( .A(n1914), .B(n1913), .Y(intadd_1141_B_1_) );
NOR2XLTS U3376 ( .A(n1916), .B(n1915), .Y(n1922) );
NOR2XLTS U3377 ( .A(n1925), .B(n1917), .Y(n1921) );
NOR2XLTS U3378 ( .A(n1919), .B(n1918), .Y(n1920) );
CMPR32X2TS U3379 ( .A(n1922), .B(n1921), .C(n1920), .CO(
DP_OP_501J326_127_5235_n129), .S(DP_OP_501J326_127_5235_n130) );
NAND2X1TS U3380 ( .A(intadd_1160_SUM_2_), .B(intadd_1159_SUM_3_), .Y(n1923)
);
OAI32X1TS U3381 ( .A0(DP_OP_501J326_127_5235_n139), .A1(n1925), .A2(n1924),
.B0(n1923), .B1(DP_OP_501J326_127_5235_n139), .Y(
DP_OP_501J326_127_5235_n150) );
CLKAND2X2TS U3382 ( .A(n1927), .B(n1926), .Y(DP_OP_501J326_127_5235_n158) );
OA21XLTS U3383 ( .A0(n1930), .A1(n1929), .B0(n1928), .Y(
DP_OP_501J326_127_5235_n163) );
AOI22X1TS U3384 ( .A0(n1932), .A1(intadd_1158_SUM_3_), .B0(
intadd_1158_SUM_2_), .B1(n1986), .Y(n1931) );
AOI32X1TS U3385 ( .A0(n1932), .A1(DP_OP_502J326_128_4510_n27), .A2(
intadd_1158_SUM_3_), .B0(n1931), .B1(DP_OP_502J326_128_4510_n32), .Y(
n1950) );
AOI2BB2X1TS U3386 ( .B0(n1935), .B1(n1934), .A0N(n1981), .A1N(n1933), .Y(
n1949) );
NAND2X1TS U3387 ( .A(n2449), .B(n1941), .Y(n1948) );
NAND2X1TS U3388 ( .A(n1936), .B(n1948), .Y(n1937) );
NOR3X1TS U3389 ( .A(n1950), .B(n1949), .C(n1937), .Y(n1943) );
AOI21X1TS U3390 ( .A0(n1938), .A1(n1937), .B0(n1943), .Y(n1957) );
AO22XLTS U3391 ( .A0(n1942), .A1(n1941), .B0(n1940), .B1(n1939), .Y(n1956)
);
NAND2X1TS U3392 ( .A(n1957), .B(n1956), .Y(n1955) );
NAND2BXLTS U3393 ( .AN(n1943), .B(n1955), .Y(intadd_1151_B_1_) );
AOI21X1TS U3394 ( .A0(n1945), .A1(n1944), .B0(DP_OP_502J326_128_4510_n41),
.Y(intadd_1151_A_0_) );
AOI21X1TS U3395 ( .A0(n1947), .A1(n1953), .B0(n1946), .Y(n1954) );
CMPR32X2TS U3396 ( .A(n1950), .B(n1949), .C(n1948), .CO(n1938), .S(n1951) );
INVX2TS U3397 ( .A(n1951), .Y(n1962) );
OAI21X1TS U3398 ( .A0(n1953), .A1(n1952), .B0(n1954), .Y(n1961) );
NOR2X1TS U3399 ( .A(n1962), .B(n1961), .Y(n1960) );
NOR2BX1TS U3400 ( .AN(n1954), .B(n1960), .Y(intadd_1151_B_0_) );
OA21XLTS U3401 ( .A0(n1957), .A1(n1956), .B0(n1955), .Y(intadd_1151_CI) );
OAI22X1TS U3402 ( .A0(n1979), .A1(n1972), .B0(n1976), .B1(n1970), .Y(n1958)
);
CMPR32X2TS U3403 ( .A(DP_OP_502J326_128_4510_n21), .B(n1959), .C(n1958),
.CO(intadd_1151_B_7_), .S(intadd_1151_B_6_) );
AO21XLTS U3404 ( .A0(n1962), .A1(n1961), .B0(n1960), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N4) );
AOI21X1TS U3405 ( .A0(n1965), .A1(n1964), .B0(n1963), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N2) );
NOR2XLTS U3406 ( .A(n1973), .B(DP_OP_502J326_128_4510_n27), .Y(n1967) );
XNOR2X1TS U3407 ( .A(n1967), .B(n1966), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N1) );
OAI22X1TS U3408 ( .A0(n1968), .A1(n1972), .B0(n1979), .B1(n1970), .Y(
DP_OP_502J326_128_4510_n53) );
OAI22X1TS U3409 ( .A0(n1968), .A1(n1970), .B0(n1969), .B1(n1972), .Y(
DP_OP_502J326_128_4510_n54) );
OAI22X1TS U3410 ( .A0(n1969), .A1(n1970), .B0(n1971), .B1(n1972), .Y(
DP_OP_502J326_128_4510_n55) );
OAI22X1TS U3411 ( .A0(n1973), .A1(n1972), .B0(n1971), .B1(n1970), .Y(
DP_OP_502J326_128_4510_n56) );
NAND3XLTS U3412 ( .A(DP_OP_502J326_128_4510_n32), .B(intadd_1161_SUM_1_),
.C(n1978), .Y(n1975) );
AOI22X1TS U3413 ( .A0(intadd_1161_SUM_2_), .A1(n1974), .B0(intadd_1158_n1),
.B1(n1978), .Y(n1977) );
AOI22X1TS U3414 ( .A0(n1975), .A1(DP_OP_502J326_128_4510_n66), .B0(n1984),
.B1(n1977), .Y(DP_OP_502J326_128_4510_n67) );
AOI22X1TS U3415 ( .A0(intadd_1161_SUM_2_), .A1(n1976), .B0(
intadd_1158_SUM_4_), .B1(n1978), .Y(n1980) );
OAI22X1TS U3416 ( .A0(n1981), .A1(n1980), .B0(n1977), .B1(n1984), .Y(
DP_OP_502J326_128_4510_n68) );
AOI22X1TS U3417 ( .A0(intadd_1161_SUM_2_), .A1(n1979), .B0(
intadd_1158_SUM_3_), .B1(n1978), .Y(n1985) );
OAI22X1TS U3418 ( .A0(n1981), .A1(n1985), .B0(n1980), .B1(n1984), .Y(
DP_OP_502J326_128_4510_n69) );
AOI21X1TS U3419 ( .A0(intadd_1158_n1), .A1(n1986), .B0(
DP_OP_502J326_128_4510_n27), .Y(DP_OP_502J326_128_4510_n75) );
XNOR2X1TS U3420 ( .A(FPADDSUB_DMP_EXP_EWSW[27]), .B(
FPADDSUB_DmP_EXP_EWSW[27]), .Y(n1987) );
XOR2XLTS U3421 ( .A(intadd_1166_n1), .B(n1987), .Y(
FPADDSUB_Shift_amount_EXP_EW[4]) );
OAI2BB2X1TS U3422 ( .B0(n1990), .B1(n1989), .A0N(n922), .A1N(n1988), .Y(
n2268) );
AO21XLTS U3423 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[25]), .A1(n963), .B0(n2268),
.Y(n2785) );
CLKAND2X2TS U3424 ( .A(operation[0]), .B(operation[1]), .Y(n2791) );
NOR2XLTS U3425 ( .A(n2675), .B(FPSENCOS_d_ff3_sign_out), .Y(n1991) );
AOI211XLTS U3426 ( .A0(n2675), .A1(FPSENCOS_d_ff3_sign_out), .B0(n2370),
.C0(n1991), .Y(n1992) );
AO21XLTS U3427 ( .A0(n2330), .A1(operation[0]), .B0(n1992), .Y(n1996) );
AOI222X1TS U3428 ( .A0(n2330), .A1(Data_2[31]), .B0(n2339), .B1(
FPSENCOS_d_ff3_sh_x_out[31]), .C0(FPSENCOS_d_ff3_sh_y_out[31]), .C1(
n1993), .Y(n1994) );
INVX2TS U3429 ( .A(n1994), .Y(n1995) );
XNOR2X1TS U3430 ( .A(n1996), .B(n1995), .Y(n2666) );
NOR2X1TS U3431 ( .A(n2652), .B(FPADDSUB_intDX_EWSW[25]), .Y(n2056) );
NOR2XLTS U3432 ( .A(n2056), .B(FPADDSUB_intDY_EWSW[24]), .Y(n1997) );
AOI22X1TS U3433 ( .A0(FPADDSUB_intDX_EWSW[25]), .A1(n2652), .B0(n957), .B1(
n1997), .Y(n2001) );
OAI21X1TS U3434 ( .A0(FPADDSUB_intDX_EWSW[26]), .A1(n2655), .B0(n1998), .Y(
n2057) );
NAND3XLTS U3435 ( .A(n2655), .B(n1998), .C(FPADDSUB_intDX_EWSW[26]), .Y(
n2000) );
NAND2BXLTS U3436 ( .AN(FPADDSUB_intDY_EWSW[27]), .B(FPADDSUB_intDX_EWSW[27]),
.Y(n1999) );
OAI211XLTS U3437 ( .A0(n2001), .A1(n2057), .B0(n2000), .C0(n1999), .Y(n2006)
);
INVX1TS U3438 ( .A(FPADDSUB_intDX_EWSW[28]), .Y(n2064) );
NOR2X1TS U3439 ( .A(n2598), .B(FPADDSUB_intDX_EWSW[30]), .Y(n2004) );
NOR2X1TS U3440 ( .A(n2505), .B(FPADDSUB_intDX_EWSW[29]), .Y(n2002) );
AOI211X1TS U3441 ( .A0(FPADDSUB_intDY_EWSW[28]), .A1(n2064), .B0(n2004),
.C0(n2002), .Y(n2055) );
AOI2BB2X1TS U3442 ( .B0(n2006), .B1(n2055), .A0N(n2005), .A1N(n2004), .Y(
n2061) );
NOR2X1TS U3443 ( .A(n2651), .B(FPADDSUB_intDX_EWSW[17]), .Y(n2042) );
NAND2BXLTS U3444 ( .AN(FPADDSUB_intDX_EWSW[9]), .B(FPADDSUB_intDY_EWSW[9]),
.Y(n2023) );
NOR2X1TS U3445 ( .A(n2650), .B(FPADDSUB_intDX_EWSW[11]), .Y(n2021) );
AOI21X1TS U3446 ( .A0(FPADDSUB_intDY_EWSW[10]), .A1(n2600), .B0(n2021), .Y(
n2026) );
OAI211XLTS U3447 ( .A0(FPADDSUB_intDX_EWSW[8]), .A1(n2647), .B0(n2023), .C0(
n2026), .Y(n2037) );
OAI2BB1X1TS U3448 ( .A0N(n2507), .A1N(FPADDSUB_intDY_EWSW[5]), .B0(
FPADDSUB_intDX_EWSW[4]), .Y(n2007) );
OAI22X1TS U3449 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n2007), .B0(n2507), .B1(
FPADDSUB_intDY_EWSW[5]), .Y(n2018) );
OAI2BB1X1TS U3450 ( .A0N(n2625), .A1N(FPADDSUB_intDY_EWSW[7]), .B0(
FPADDSUB_intDX_EWSW[6]), .Y(n2008) );
OAI22X1TS U3451 ( .A0(FPADDSUB_intDY_EWSW[6]), .A1(n2008), .B0(n2625), .B1(
FPADDSUB_intDY_EWSW[7]), .Y(n2017) );
OAI2BB2XLTS U3452 ( .B0(FPADDSUB_intDY_EWSW[0]), .B1(n2009), .A0N(
FPADDSUB_intDX_EWSW[1]), .A1N(n2649), .Y(n2011) );
NAND2BXLTS U3453 ( .AN(FPADDSUB_intDX_EWSW[2]), .B(FPADDSUB_intDY_EWSW[2]),
.Y(n2010) );
OAI211XLTS U3454 ( .A0(n2657), .A1(FPADDSUB_intDX_EWSW[3]), .B0(n2011), .C0(
n2010), .Y(n2014) );
OAI21XLTS U3455 ( .A0(FPADDSUB_intDX_EWSW[3]), .A1(n2657), .B0(
FPADDSUB_intDX_EWSW[2]), .Y(n2012) );
AOI2BB2XLTS U3456 ( .B0(FPADDSUB_intDX_EWSW[3]), .B1(n2657), .A0N(
FPADDSUB_intDY_EWSW[2]), .A1N(n2012), .Y(n2013) );
AOI222X1TS U3457 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n2605), .B0(n2014), .B1(
n2013), .C0(FPADDSUB_intDY_EWSW[5]), .C1(n2507), .Y(n2016) );
AOI22X1TS U3458 ( .A0(FPADDSUB_intDY_EWSW[7]), .A1(n2625), .B0(
FPADDSUB_intDY_EWSW[6]), .B1(n2510), .Y(n2015) );
OAI32X1TS U3459 ( .A0(n2018), .A1(n2017), .A2(n2016), .B0(n2015), .B1(n2017),
.Y(n2036) );
OA22X1TS U3460 ( .A0(n2517), .A1(FPADDSUB_intDX_EWSW[14]), .B0(n2653), .B1(
FPADDSUB_intDX_EWSW[15]), .Y(n2033) );
NAND2BXLTS U3461 ( .AN(FPADDSUB_intDX_EWSW[13]), .B(FPADDSUB_intDY_EWSW[13]),
.Y(n2019) );
OAI21XLTS U3462 ( .A0(FPADDSUB_intDX_EWSW[13]), .A1(n2641), .B0(
FPADDSUB_intDX_EWSW[12]), .Y(n2020) );
OAI2BB2XLTS U3463 ( .B0(FPADDSUB_intDY_EWSW[12]), .B1(n2020), .A0N(
FPADDSUB_intDX_EWSW[13]), .A1N(n2641), .Y(n2032) );
NOR2XLTS U3464 ( .A(n2021), .B(FPADDSUB_intDY_EWSW[10]), .Y(n2022) );
AOI22X1TS U3465 ( .A0(FPADDSUB_intDX_EWSW[11]), .A1(n2650), .B0(
FPADDSUB_intDX_EWSW[10]), .B1(n2022), .Y(n2028) );
NAND2BXLTS U3466 ( .AN(FPADDSUB_intDY_EWSW[9]), .B(FPADDSUB_intDX_EWSW[9]),
.Y(n2025) );
NAND3XLTS U3467 ( .A(n2647), .B(n2023), .C(FPADDSUB_intDX_EWSW[8]), .Y(n2024) );
AOI21X1TS U3468 ( .A0(n2025), .A1(n2024), .B0(n2035), .Y(n2027) );
OAI2BB2XLTS U3469 ( .B0(n2028), .B1(n2035), .A0N(n2027), .A1N(n2026), .Y(
n2031) );
OAI21XLTS U3470 ( .A0(FPADDSUB_intDX_EWSW[15]), .A1(n2653), .B0(
FPADDSUB_intDX_EWSW[14]), .Y(n2029) );
OAI2BB2XLTS U3471 ( .B0(FPADDSUB_intDY_EWSW[14]), .B1(n2029), .A0N(
FPADDSUB_intDX_EWSW[15]), .A1N(n2653), .Y(n2030) );
AOI211X1TS U3472 ( .A0(n2033), .A1(n2032), .B0(n2031), .C0(n2030), .Y(n2034)
);
OAI31X1TS U3473 ( .A0(n2037), .A1(n2036), .A2(n2035), .B0(n2034), .Y(n2040)
);
OA22X1TS U3474 ( .A0(n2518), .A1(FPADDSUB_intDX_EWSW[22]), .B0(n2654), .B1(
FPADDSUB_intDX_EWSW[23]), .Y(n2053) );
NAND2BXLTS U3475 ( .AN(FPADDSUB_intDX_EWSW[21]), .B(FPADDSUB_intDY_EWSW[21]),
.Y(n2038) );
OAI21X1TS U3476 ( .A0(FPADDSUB_intDX_EWSW[18]), .A1(n2648), .B0(n2044), .Y(
n2048) );
NAND3BXLTS U3477 ( .AN(n2042), .B(n2040), .C(n2039), .Y(n2060) );
OAI21XLTS U3478 ( .A0(FPADDSUB_intDX_EWSW[21]), .A1(n2640), .B0(
FPADDSUB_intDX_EWSW[20]), .Y(n2041) );
OAI2BB2XLTS U3479 ( .B0(FPADDSUB_intDY_EWSW[20]), .B1(n2041), .A0N(
FPADDSUB_intDX_EWSW[21]), .A1N(n2640), .Y(n2052) );
AOI22X1TS U3480 ( .A0(FPADDSUB_intDX_EWSW[17]), .A1(n2651), .B0(
FPADDSUB_intDX_EWSW[16]), .B1(n2043), .Y(n2046) );
AOI32X1TS U3481 ( .A0(n2648), .A1(n2044), .A2(FPADDSUB_intDX_EWSW[18]), .B0(
FPADDSUB_intDX_EWSW[19]), .B1(n2519), .Y(n2045) );
OAI32X1TS U3482 ( .A0(n2048), .A1(n2047), .A2(n2046), .B0(n2045), .B1(n2047),
.Y(n2051) );
OAI2BB2XLTS U3483 ( .B0(FPADDSUB_intDY_EWSW[22]), .B1(n2049), .A0N(
FPADDSUB_intDX_EWSW[23]), .A1N(n2654), .Y(n2050) );
AOI211X1TS U3484 ( .A0(n2053), .A1(n2052), .B0(n2051), .C0(n2050), .Y(n2059)
);
NAND4BBX1TS U3485 ( .AN(n2057), .BN(n2056), .C(n2055), .D(n2054), .Y(n2058)
);
AOI32X1TS U3486 ( .A0(n2061), .A1(n2060), .A2(n2059), .B0(n2058), .B1(n2061),
.Y(n2062) );
INVX2TS U3487 ( .A(n2062), .Y(n2281) );
AOI22X1TS U3488 ( .A0(n2515), .A1(FPADDSUB_intDY_EWSW[0]), .B0(n2628), .B1(
FPADDSUB_intDY_EWSW[28]), .Y(n2063) );
AOI22X1TS U3489 ( .A0(n939), .A1(FPADDSUB_intDY_EWSW[19]), .B0(n2608), .B1(
FPADDSUB_intDY_EWSW[11]), .Y(n2065) );
OAI221XLTS U3490 ( .A0(n939), .A1(FPADDSUB_intDY_EWSW[19]), .B0(n2608), .B1(
FPADDSUB_intDY_EWSW[11]), .C0(n2065), .Y(n2070) );
AOI22X1TS U3491 ( .A0(n2511), .A1(FPADDSUB_intDY_EWSW[20]), .B0(n2615), .B1(
FPADDSUB_intDY_EWSW[30]), .Y(n2066) );
AOI22X1TS U3492 ( .A0(n2606), .A1(FPADDSUB_intDY_EWSW[15]), .B0(n2513), .B1(
FPADDSUB_intDY_EWSW[9]), .Y(n2067) );
OAI221XLTS U3493 ( .A0(n2606), .A1(FPADDSUB_intDY_EWSW[15]), .B0(n2513),
.B1(FPADDSUB_intDY_EWSW[9]), .C0(n2067), .Y(n2068) );
NOR4X1TS U3494 ( .A(n2071), .B(n2070), .C(n2069), .D(n2068), .Y(n2098) );
AOI22X1TS U3495 ( .A0(n926), .A1(FPADDSUB_intDY_EWSW[26]), .B0(n938), .B1(
FPADDSUB_intDY_EWSW[25]), .Y(n2072) );
AOI22X1TS U3496 ( .A0(n2623), .A1(FPADDSUB_intDY_EWSW[16]), .B0(n2611), .B1(
FPADDSUB_intDY_EWSW[13]), .Y(n2073) );
OAI221XLTS U3497 ( .A0(n2623), .A1(FPADDSUB_intDY_EWSW[16]), .B0(n2611),
.B1(FPADDSUB_intDY_EWSW[13]), .C0(n2073), .Y(n2078) );
AOI22X1TS U3498 ( .A0(n2512), .A1(FPADDSUB_intDY_EWSW[23]), .B0(n2616), .B1(
FPADDSUB_intDY_EWSW[29]), .Y(n2074) );
INVX2TS U3499 ( .A(n957), .Y(n2282) );
AOI22X1TS U3500 ( .A0(n2607), .A1(FPADDSUB_intDY_EWSW[21]), .B0(n2282), .B1(
FPADDSUB_intDY_EWSW[24]), .Y(n2075) );
OAI221XLTS U3501 ( .A0(n2607), .A1(FPADDSUB_intDY_EWSW[21]), .B0(n2282),
.B1(FPADDSUB_intDY_EWSW[24]), .C0(n2075), .Y(n2076) );
NOR4X1TS U3502 ( .A(n2079), .B(n2078), .C(n2077), .D(n2076), .Y(n2097) );
AOI22X1TS U3503 ( .A0(n2510), .A1(FPADDSUB_intDY_EWSW[6]), .B0(n2610), .B1(
FPADDSUB_intDY_EWSW[3]), .Y(n2080) );
AOI22X1TS U3504 ( .A0(n2605), .A1(FPADDSUB_intDY_EWSW[4]), .B0(n2609), .B1(
FPADDSUB_intDY_EWSW[17]), .Y(n2081) );
OAI221XLTS U3505 ( .A0(n2605), .A1(FPADDSUB_intDY_EWSW[4]), .B0(n2609), .B1(
FPADDSUB_intDY_EWSW[17]), .C0(n2081), .Y(n2094) );
OAI22X1TS U3506 ( .A0(n2603), .A1(FPADDSUB_intDY_EWSW[14]), .B0(n2600), .B1(
FPADDSUB_intDY_EWSW[10]), .Y(n2082) );
AOI221X1TS U3507 ( .A0(n2603), .A1(FPADDSUB_intDY_EWSW[14]), .B0(
FPADDSUB_intDY_EWSW[10]), .B1(n2600), .C0(n2082), .Y(n2083) );
OAI221XLTS U3508 ( .A0(FPADDSUB_intDX_EWSW[7]), .A1(n2612), .B0(n2625), .B1(
FPADDSUB_intDY_EWSW[7]), .C0(n2083), .Y(n2093) );
OAI22X1TS U3509 ( .A0(n2602), .A1(FPADDSUB_intDY_EWSW[8]), .B0(n2507), .B1(
FPADDSUB_intDY_EWSW[5]), .Y(n2084) );
AOI221X1TS U3510 ( .A0(n2602), .A1(FPADDSUB_intDY_EWSW[8]), .B0(
FPADDSUB_intDY_EWSW[5]), .B1(n2507), .C0(n2084), .Y(n2091) );
OAI22X1TS U3511 ( .A0(n935), .A1(FPADDSUB_intDY_EWSW[27]), .B0(n2509), .B1(
FPADDSUB_intDY_EWSW[2]), .Y(n2085) );
AOI221X1TS U3512 ( .A0(n935), .A1(FPADDSUB_intDY_EWSW[27]), .B0(
FPADDSUB_intDY_EWSW[2]), .B1(n2509), .C0(n2085), .Y(n2090) );
OAI22X1TS U3513 ( .A0(n2604), .A1(FPADDSUB_intDY_EWSW[18]), .B0(n2508), .B1(
FPADDSUB_intDY_EWSW[1]), .Y(n2086) );
AOI221X1TS U3514 ( .A0(n2604), .A1(FPADDSUB_intDY_EWSW[18]), .B0(
FPADDSUB_intDY_EWSW[1]), .B1(n2508), .C0(n2086), .Y(n2089) );
OAI22X1TS U3515 ( .A0(n934), .A1(FPADDSUB_intDY_EWSW[22]), .B0(n2601), .B1(
FPADDSUB_intDX_EWSW[12]), .Y(n2087) );
AOI221X1TS U3516 ( .A0(n934), .A1(FPADDSUB_intDY_EWSW[22]), .B0(
FPADDSUB_intDX_EWSW[12]), .B1(n2601), .C0(n2087), .Y(n2088) );
NAND4XLTS U3517 ( .A(n2091), .B(n2090), .C(n2089), .D(n2088), .Y(n2092) );
NOR4X1TS U3518 ( .A(n2095), .B(n2094), .C(n2092), .D(n2093), .Y(n2096) );
AOI31XLTS U3519 ( .A0(n2098), .A1(n2097), .A2(n2096), .B0(n911), .Y(n2099)
);
AOI2BB2XLTS U3520 ( .B0(n2781), .B1(n2278), .A0N(FPADDSUB_intDX_EWSW[31]),
.A1N(n2099), .Y(n2782) );
AOI22X1TS U3523 ( .A0(FPMULT_FS_Module_state_reg[0]), .A1(
FPMULT_FS_Module_state_reg[3]), .B0(n2100), .B1(n2102), .Y(n2816) );
NOR2XLTS U3524 ( .A(FPMULT_FSM_selector_C), .B(n2102), .Y(n2101) );
AOI22X1TS U3525 ( .A0(n2149), .A1(FPMULT_Add_result[21]), .B0(
FPMULT_P_Sgf[45]), .B1(n2146), .Y(n2105) );
NOR2XLTS U3526 ( .A(n2624), .B(n2102), .Y(n2103) );
AOI22X1TS U3527 ( .A0(FPMULT_Add_result[22]), .A1(n2147), .B0(n2148), .B1(
FPMULT_P_Sgf[44]), .Y(n2104) );
NAND2X1TS U3528 ( .A(n2105), .B(n2104), .Y(n2814) );
AOI22X1TS U3529 ( .A0(n2149), .A1(FPMULT_Add_result[20]), .B0(n2148), .B1(
FPMULT_P_Sgf[43]), .Y(n2107) );
AOI22X1TS U3530 ( .A0(FPMULT_P_Sgf[44]), .A1(n2146), .B0(n2147), .B1(
FPMULT_Add_result[21]), .Y(n2106) );
NAND2X1TS U3531 ( .A(n2107), .B(n2106), .Y(n2813) );
AOI22X1TS U3532 ( .A0(n2149), .A1(FPMULT_Add_result[19]), .B0(n2148), .B1(
FPMULT_P_Sgf[42]), .Y(n2109) );
AOI22X1TS U3533 ( .A0(n2147), .A1(FPMULT_Add_result[20]), .B0(n2146), .B1(
FPMULT_P_Sgf[43]), .Y(n2108) );
NAND2X1TS U3534 ( .A(n2109), .B(n2108), .Y(n2812) );
AOI22X1TS U3535 ( .A0(n2149), .A1(FPMULT_Add_result[18]), .B0(n2147), .B1(
FPMULT_Add_result[19]), .Y(n2111) );
AOI22X1TS U3536 ( .A0(n2148), .A1(FPMULT_P_Sgf[41]), .B0(n2146), .B1(
FPMULT_P_Sgf[42]), .Y(n2110) );
NAND2X1TS U3537 ( .A(n2111), .B(n2110), .Y(n2811) );
AOI22X1TS U3538 ( .A0(n2148), .A1(FPMULT_P_Sgf[40]), .B0(n2146), .B1(
FPMULT_P_Sgf[41]), .Y(n2113) );
AOI22X1TS U3539 ( .A0(n2149), .A1(FPMULT_Add_result[17]), .B0(n2147), .B1(
FPMULT_Add_result[18]), .Y(n2112) );
NAND2X1TS U3540 ( .A(n2113), .B(n2112), .Y(n2810) );
AOI22X1TS U3541 ( .A0(n2147), .A1(FPMULT_Add_result[17]), .B0(n2146), .B1(
FPMULT_P_Sgf[40]), .Y(n2115) );
AOI22X1TS U3542 ( .A0(n2149), .A1(FPMULT_Add_result[16]), .B0(n2148), .B1(
FPMULT_P_Sgf[39]), .Y(n2114) );
NAND2X1TS U3543 ( .A(n2115), .B(n2114), .Y(n2809) );
AOI22X1TS U3544 ( .A0(n2149), .A1(FPMULT_Add_result[15]), .B0(n2147), .B1(
FPMULT_Add_result[16]), .Y(n2117) );
AOI22X1TS U3545 ( .A0(n2148), .A1(FPMULT_P_Sgf[38]), .B0(n2146), .B1(
FPMULT_P_Sgf[39]), .Y(n2116) );
NAND2X1TS U3546 ( .A(n2117), .B(n2116), .Y(n2808) );
AOI22X1TS U3547 ( .A0(n2148), .A1(FPMULT_P_Sgf[37]), .B0(n2146), .B1(
FPMULT_P_Sgf[38]), .Y(n2119) );
AOI22X1TS U3548 ( .A0(n2149), .A1(FPMULT_Add_result[14]), .B0(n2147), .B1(
FPMULT_Add_result[15]), .Y(n2118) );
NAND2X1TS U3549 ( .A(n2119), .B(n2118), .Y(n2807) );
AOI22X1TS U3550 ( .A0(n2147), .A1(FPMULT_Add_result[14]), .B0(n2146), .B1(
FPMULT_P_Sgf[37]), .Y(n2121) );
AOI22X1TS U3551 ( .A0(n2149), .A1(FPMULT_Add_result[13]), .B0(n2148), .B1(
FPMULT_P_Sgf[36]), .Y(n2120) );
NAND2X1TS U3552 ( .A(n2121), .B(n2120), .Y(n2806) );
AOI22X1TS U3553 ( .A0(n2149), .A1(FPMULT_Add_result[12]), .B0(n2147), .B1(
FPMULT_Add_result[13]), .Y(n2123) );
AOI22X1TS U3554 ( .A0(n2148), .A1(FPMULT_P_Sgf[35]), .B0(n2146), .B1(
FPMULT_P_Sgf[36]), .Y(n2122) );
NAND2X1TS U3555 ( .A(n2123), .B(n2122), .Y(n2805) );
AOI22X1TS U3556 ( .A0(n2148), .A1(FPMULT_P_Sgf[34]), .B0(n2147), .B1(
FPMULT_Add_result[12]), .Y(n2125) );
AOI22X1TS U3557 ( .A0(n2149), .A1(FPMULT_Add_result[11]), .B0(n2146), .B1(
FPMULT_P_Sgf[35]), .Y(n2124) );
NAND2X1TS U3558 ( .A(n2125), .B(n2124), .Y(n2804) );
AOI22X1TS U3559 ( .A0(n2147), .A1(FPMULT_Add_result[11]), .B0(n2146), .B1(
FPMULT_P_Sgf[34]), .Y(n2127) );
AOI22X1TS U3560 ( .A0(n2149), .A1(FPMULT_Add_result[10]), .B0(n2148), .B1(
FPMULT_P_Sgf[33]), .Y(n2126) );
NAND2X1TS U3561 ( .A(n2127), .B(n2126), .Y(n2803) );
AOI22X1TS U3562 ( .A0(n2148), .A1(FPMULT_P_Sgf[32]), .B0(n2147), .B1(
FPMULT_Add_result[10]), .Y(n2129) );
AOI22X1TS U3563 ( .A0(n2149), .A1(FPMULT_Add_result[9]), .B0(n2146), .B1(
FPMULT_P_Sgf[33]), .Y(n2128) );
NAND2X1TS U3564 ( .A(n2129), .B(n2128), .Y(n2802) );
AOI22X1TS U3565 ( .A0(n2147), .A1(FPMULT_Add_result[9]), .B0(n2146), .B1(
FPMULT_P_Sgf[32]), .Y(n2131) );
AOI22X1TS U3566 ( .A0(n2149), .A1(FPMULT_Add_result[8]), .B0(n2148), .B1(
FPMULT_P_Sgf[31]), .Y(n2130) );
NAND2X1TS U3567 ( .A(n2131), .B(n2130), .Y(n2801) );
AOI22X1TS U3568 ( .A0(n2148), .A1(FPMULT_P_Sgf[30]), .B0(n2146), .B1(
FPMULT_P_Sgf[31]), .Y(n2133) );
AOI22X1TS U3569 ( .A0(n2149), .A1(FPMULT_Add_result[7]), .B0(n2147), .B1(
FPMULT_Add_result[8]), .Y(n2132) );
NAND2X1TS U3570 ( .A(n2133), .B(n2132), .Y(n2800) );
AOI22X1TS U3571 ( .A0(n2147), .A1(FPMULT_Add_result[7]), .B0(n2146), .B1(
FPMULT_P_Sgf[30]), .Y(n2135) );
AOI22X1TS U3572 ( .A0(n2149), .A1(FPMULT_Add_result[6]), .B0(n2148), .B1(
FPMULT_P_Sgf[29]), .Y(n2134) );
NAND2X1TS U3573 ( .A(n2135), .B(n2134), .Y(n2799) );
AOI22X1TS U3574 ( .A0(n2149), .A1(FPMULT_Add_result[5]), .B0(n2148), .B1(
FPMULT_P_Sgf[28]), .Y(n2137) );
AOI22X1TS U3575 ( .A0(n2147), .A1(FPMULT_Add_result[6]), .B0(n2146), .B1(
FPMULT_P_Sgf[29]), .Y(n2136) );
NAND2X1TS U3576 ( .A(n2137), .B(n2136), .Y(n2798) );
AOI22X1TS U3577 ( .A0(n2148), .A1(FPMULT_P_Sgf[27]), .B0(n2147), .B1(
FPMULT_Add_result[5]), .Y(n2139) );
AOI22X1TS U3578 ( .A0(n2149), .A1(FPMULT_Add_result[4]), .B0(n2146), .B1(
FPMULT_P_Sgf[28]), .Y(n2138) );
NAND2X1TS U3579 ( .A(n2139), .B(n2138), .Y(n2797) );
AOI22X1TS U3580 ( .A0(n2148), .A1(FPMULT_P_Sgf[26]), .B0(n2146), .B1(
FPMULT_P_Sgf[27]), .Y(n2141) );
AOI22X1TS U3581 ( .A0(n2149), .A1(FPMULT_Add_result[3]), .B0(n2147), .B1(
FPMULT_Add_result[4]), .Y(n2140) );
NAND2X1TS U3582 ( .A(n2141), .B(n2140), .Y(n2796) );
AOI22X1TS U3583 ( .A0(n2147), .A1(FPMULT_Add_result[3]), .B0(n2146), .B1(
FPMULT_P_Sgf[26]), .Y(n2143) );
AOI22X1TS U3584 ( .A0(n2149), .A1(FPMULT_Add_result[2]), .B0(n2148), .B1(
FPMULT_P_Sgf[25]), .Y(n2142) );
NAND2X1TS U3585 ( .A(n2143), .B(n2142), .Y(n2795) );
AOI22X1TS U3586 ( .A0(n2148), .A1(FPMULT_P_Sgf[24]), .B0(n2147), .B1(
FPMULT_Add_result[2]), .Y(n2145) );
AOI22X1TS U3587 ( .A0(n2149), .A1(FPMULT_Add_result[1]), .B0(n2146), .B1(
FPMULT_P_Sgf[25]), .Y(n2144) );
NAND2X1TS U3588 ( .A(n2145), .B(n2144), .Y(n2794) );
AOI22X1TS U3589 ( .A0(n2147), .A1(FPMULT_Add_result[1]), .B0(n2146), .B1(
FPMULT_P_Sgf[24]), .Y(n2151) );
AOI22X1TS U3590 ( .A0(n2149), .A1(FPMULT_Add_result[0]), .B0(n2148), .B1(
FPMULT_P_Sgf[23]), .Y(n2150) );
NAND2X1TS U3591 ( .A(n2151), .B(n2150), .Y(n2793) );
XOR2XLTS U3592 ( .A(Data_2[31]), .B(Data_1[31]), .Y(n2667) );
INVX2TS U3593 ( .A(n2152), .Y(n2352) );
AOI2BB1XLTS U3594 ( .A0N(n2777), .A1N(underflow_flag_mult), .B0(n2352), .Y(
FPMULT_final_result_ieee_Module_Sign_S_mux) );
OA22X1TS U3595 ( .A0(n2594), .A1(FPSENCOS_cont_iter_out[1]), .B0(n908), .B1(
n2153), .Y(FPSENCOS_data_out_LUT[4]) );
NOR4X1TS U3596 ( .A(Data_1[12]), .B(Data_1[11]), .C(Data_1[10]), .D(
Data_1[9]), .Y(n2160) );
NOR4X1TS U3597 ( .A(Data_1[8]), .B(Data_1[7]), .C(Data_1[6]), .D(Data_1[0]),
.Y(n2159) );
NOR4X1TS U3598 ( .A(Data_1[3]), .B(Data_1[16]), .C(Data_1[1]), .D(Data_1[22]), .Y(n2157) );
NOR3XLTS U3599 ( .A(Data_1[2]), .B(Data_1[5]), .C(Data_1[4]), .Y(n2156) );
NOR4X1TS U3600 ( .A(Data_1[21]), .B(Data_1[19]), .C(Data_1[14]), .D(
Data_1[20]), .Y(n2155) );
NOR4X1TS U3601 ( .A(Data_1[13]), .B(Data_1[15]), .C(Data_1[17]), .D(
Data_1[18]), .Y(n2154) );
AND4X1TS U3602 ( .A(n2157), .B(n2156), .C(n2155), .D(n2154), .Y(n2158) );
NAND3XLTS U3603 ( .A(n2160), .B(n2159), .C(n2158), .Y(n2664) );
NOR4BX1TS U3604 ( .AN(operation_reg[1]), .B(dataB[28]), .C(operation_reg[0]),
.D(dataB[23]), .Y(n2165) );
NOR4X1TS U3605 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[26]), .D(dataB[29]),
.Y(n2164) );
NAND4XLTS U3606 ( .A(dataA[30]), .B(dataA[27]), .C(dataA[28]), .D(dataA[26]),
.Y(n2162) );
NAND4XLTS U3607 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[25]), .D(dataA[24]),
.Y(n2161) );
OR3X1TS U3608 ( .A(n2773), .B(n2162), .C(n2161), .Y(n2166) );
NOR3XLTS U3609 ( .A(dataB[25]), .B(dataB[31]), .C(n2166), .Y(n2163) );
AOI31XLTS U3610 ( .A0(n2165), .A1(n2164), .A2(n2163), .B0(dataB[27]), .Y(
n2176) );
NOR4X1TS U3611 ( .A(dataA[30]), .B(dataA[27]), .C(dataA[28]), .D(dataA[26]),
.Y(n2169) );
NOR4X1TS U3612 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[25]), .D(dataA[24]),
.Y(n2168) );
NOR4BX1TS U3613 ( .AN(operation_reg[1]), .B(operation_reg[0]), .C(dataA[31]),
.D(n2773), .Y(n2167) );
NOR2X1TS U3614 ( .A(operation_reg[1]), .B(n2166), .Y(n2174) );
AOI31XLTS U3615 ( .A0(n2169), .A1(n2168), .A2(n2167), .B0(n2174), .Y(n2172)
);
NAND3XLTS U3616 ( .A(dataB[28]), .B(dataB[23]), .C(dataB[25]), .Y(n2171) );
NAND4XLTS U3617 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[26]), .D(dataB[29]),
.Y(n2170) );
OAI31X1TS U3618 ( .A0(n2172), .A1(n2171), .A2(n2170), .B0(dataB[27]), .Y(
n2173) );
NAND4XLTS U3619 ( .A(n2776), .B(n2775), .C(n2774), .D(n2173), .Y(n2175) );
OAI2BB2XLTS U3620 ( .B0(n2176), .B1(n2175), .A0N(n2174), .A1N(
operation_reg[0]), .Y(NaN_reg) );
NAND2X1TS U3621 ( .A(FPADDSUB_N59), .B(FPADDSUB_OP_FLAG_SFG), .Y(n2177) );
XNOR2X1TS U3622 ( .A(n2177), .B(FPADDSUB_N60), .Y(FPADDSUB_Raw_mant_SGF[1])
);
OAI21XLTS U3623 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[3]), .A1(FPADDSUB_DMP_SFG[1]), .B0(n2179), .Y(n2180) );
XOR2XLTS U3624 ( .A(n2181), .B(n2180), .Y(FPADDSUB_Raw_mant_SGF[3]) );
OAI21XLTS U3625 ( .A0(n2523), .A1(FPADDSUB_DmP_mant_SFG_SWR[4]), .B0(n2182),
.Y(n2186) );
AOI2BB2XLTS U3626 ( .B0(n2184), .B1(n963), .A0N(n922), .A1N(n2183), .Y(n2185) );
XNOR2X1TS U3627 ( .A(n2186), .B(n2185), .Y(FPADDSUB_Raw_mant_SGF[4]) );
AOI22X1TS U3628 ( .A0(FPADDSUB_OP_FLAG_SFG), .A1(n2188), .B0(n2187), .B1(
n963), .Y(n2191) );
OAI21XLTS U3629 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[5]), .A1(FPADDSUB_DMP_SFG[3]), .B0(n2189), .Y(n2190) );
XNOR2X1TS U3630 ( .A(n2191), .B(n2190), .Y(FPADDSUB_Raw_mant_SGF[5]) );
OAI21XLTS U3631 ( .A0(n2524), .A1(FPADDSUB_DmP_mant_SFG_SWR[6]), .B0(n2192),
.Y(n2196) );
AOI22X1TS U3632 ( .A0(n2269), .A1(n2194), .B0(n2193), .B1(n963), .Y(n2195)
);
XNOR2X1TS U3633 ( .A(n2196), .B(n2195), .Y(FPADDSUB_Raw_mant_SGF[6]) );
AOI21X1TS U3634 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[7]), .A1(FPADDSUB_DMP_SFG[5]), .B0(n2197), .Y(n2201) );
AOI2BB2XLTS U3635 ( .B0(n2269), .B1(n2199), .A0N(n2198), .A1N(
FPADDSUB_OP_FLAG_SFG), .Y(n2200) );
XNOR2X1TS U3636 ( .A(n2201), .B(n2200), .Y(FPADDSUB_Raw_mant_SGF[7]) );
AOI21X1TS U3637 ( .A0(FPADDSUB_DMP_SFG[7]), .A1(n2528), .B0(n2202), .Y(n2206) );
AOI22X1TS U3638 ( .A0(FPADDSUB_OP_FLAG_SFG), .A1(n2204), .B0(n2203), .B1(
n922), .Y(n2205) );
XOR2XLTS U3639 ( .A(n2206), .B(n2205), .Y(FPADDSUB_Raw_mant_SGF[9]) );
AOI21X1TS U3640 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[10]), .A1(
FPADDSUB_DMP_SFG[8]), .B0(n2207), .Y(n2211) );
AOI22X1TS U3641 ( .A0(n2269), .A1(n2209), .B0(n2208), .B1(n922), .Y(n2210)
);
XOR2XLTS U3642 ( .A(n2211), .B(n2210), .Y(FPADDSUB_Raw_mant_SGF[10]) );
AOI21X1TS U3643 ( .A0(FPADDSUB_DMP_SFG[9]), .A1(n2530), .B0(n2212), .Y(n2216) );
AOI22X1TS U3644 ( .A0(n2269), .A1(n2214), .B0(n2213), .B1(n963), .Y(n2215)
);
XOR2XLTS U3645 ( .A(n2216), .B(n2215), .Y(FPADDSUB_Raw_mant_SGF[11]) );
AOI21X1TS U3646 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[12]), .A1(
FPADDSUB_DMP_SFG[10]), .B0(n2217), .Y(n2221) );
AOI22X1TS U3647 ( .A0(n2269), .A1(n2219), .B0(n2218), .B1(n963), .Y(n2220)
);
XOR2XLTS U3648 ( .A(n2221), .B(n2220), .Y(FPADDSUB_Raw_mant_SGF[12]) );
AOI21X1TS U3649 ( .A0(n2486), .A1(FPADDSUB_DMP_SFG[11]), .B0(n2222), .Y(
n2226) );
AOI2BB2XLTS U3650 ( .B0(n2224), .B1(n963), .A0N(n922), .A1N(n2223), .Y(n2225) );
XNOR2X1TS U3651 ( .A(n2226), .B(n2225), .Y(FPADDSUB_Raw_mant_SGF[13]) );
AOI2BB2XLTS U3652 ( .B0(n2228), .B1(n963), .A0N(n922), .A1N(n2227), .Y(n2231) );
OAI21XLTS U3653 ( .A0(n2533), .A1(FPADDSUB_DmP_mant_SFG_SWR[14]), .B0(n2229),
.Y(n2230) );
XNOR2X1TS U3654 ( .A(n2231), .B(n2230), .Y(FPADDSUB_Raw_mant_SGF[14]) );
AOI21X1TS U3655 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[15]), .A1(
FPADDSUB_DMP_SFG[13]), .B0(n2232), .Y(n2236) );
AOI2BB2XLTS U3656 ( .B0(n2269), .B1(n2234), .A0N(n2233), .A1N(n2269), .Y(
n2235) );
XNOR2X1TS U3657 ( .A(n2236), .B(n2235), .Y(FPADDSUB_Raw_mant_SGF[15]) );
OAI21XLTS U3658 ( .A0(n2536), .A1(FPADDSUB_DmP_mant_SFG_SWR[16]), .B0(n2237),
.Y(n2241) );
AOI2BB2XLTS U3659 ( .B0(n2239), .B1(n963), .A0N(n922), .A1N(n2238), .Y(n2240) );
XNOR2X1TS U3660 ( .A(n2241), .B(n2240), .Y(FPADDSUB_Raw_mant_SGF[16]) );
AOI21X1TS U3661 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[17]), .A1(
FPADDSUB_DMP_SFG[15]), .B0(n2242), .Y(n2246) );
AOI2BB2XLTS U3662 ( .B0(n2269), .B1(n2244), .A0N(n2243), .A1N(n2269), .Y(
n2245) );
XNOR2X1TS U3663 ( .A(n2246), .B(n2245), .Y(FPADDSUB_Raw_mant_SGF[17]) );
AOI21X1TS U3664 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[18]), .A1(
FPADDSUB_DMP_SFG[16]), .B0(n2247), .Y(n2251) );
AOI22X1TS U3665 ( .A0(n2269), .A1(n2249), .B0(n2248), .B1(n963), .Y(n2250)
);
XOR2XLTS U3666 ( .A(n2251), .B(n2250), .Y(FPADDSUB_Raw_mant_SGF[18]) );
AOI21X1TS U3667 ( .A0(n2590), .A1(n2502), .B0(n2252), .Y(n2256) );
AOI22X1TS U3668 ( .A0(n2269), .A1(n2254), .B0(n2253), .B1(n963), .Y(n2255)
);
XNOR2X1TS U3669 ( .A(n2256), .B(n2255), .Y(FPADDSUB_Raw_mant_SGF[19]) );
AOI22X1TS U3670 ( .A0(n2269), .A1(n2258), .B0(n2257), .B1(n963), .Y(n2261)
);
OAI21XLTS U3671 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[20]), .A1(
FPADDSUB_DMP_SFG[18]), .B0(n2259), .Y(n2260) );
XNOR2X1TS U3672 ( .A(n2261), .B(n2260), .Y(FPADDSUB_Raw_mant_SGF[20]) );
AOI22X1TS U3673 ( .A0(n2269), .A1(n2263), .B0(n2262), .B1(n963), .Y(n2267)
);
NAND2BXLTS U3674 ( .AN(n2265), .B(n2264), .Y(n2266) );
XOR2XLTS U3675 ( .A(n2267), .B(n2266), .Y(FPADDSUB_Raw_mant_SGF[21]) );
AOI31X1TS U3676 ( .A0(n2269), .A1(FPADDSUB_DmP_mant_SFG_SWR[24]), .A2(n2514),
.B0(n2268), .Y(n2271) );
AOI32X1TS U3677 ( .A0(FPADDSUB_DMP_SFG[22]), .A1(n2271), .A2(n2618), .B0(
n2270), .B1(n2271), .Y(n2272) );
XNOR2X1TS U3678 ( .A(FPADDSUB_DmP_mant_SFG_SWR[25]), .B(n2272), .Y(
FPADDSUB_Raw_mant_SGF[25]) );
XNOR2X1TS U3679 ( .A(FPSENCOS_d_ff1_shift_region_flag_out[0]), .B(
FPSENCOS_d_ff1_shift_region_flag_out[1]), .Y(n2273) );
XOR2X1TS U3680 ( .A(FPSENCOS_d_ff1_operation_out), .B(n2273), .Y(n2274) );
BUFX3TS U3681 ( .A(n2303), .Y(n2301) );
AOI22X1TS U3682 ( .A0(n2302), .A1(FPSENCOS_d_ff_Xn[31]), .B0(
FPSENCOS_d_ff_Yn[31]), .B1(n2301), .Y(n2275) );
XNOR2X1TS U3683 ( .A(n2276), .B(n2275), .Y(FPSENCOS_fmtted_Result_31_) );
AOI22X1TS U3684 ( .A0(n911), .A1(n2656), .B0(n2515), .B1(n2278), .Y(
FPADDSUB_DmP_INIT_EWSW[0]) );
AOI22X1TS U3685 ( .A0(n911), .A1(n2649), .B0(n2508), .B1(n2278), .Y(
FPADDSUB_DmP_INIT_EWSW[1]) );
AOI22X1TS U3686 ( .A0(n911), .A1(n2637), .B0(n2509), .B1(n2278), .Y(
FPADDSUB_DmP_INIT_EWSW[2]) );
AOI22X1TS U3687 ( .A0(n911), .A1(n2657), .B0(n2610), .B1(n2278), .Y(
FPADDSUB_DmP_INIT_EWSW[3]) );
AOI22X1TS U3688 ( .A0(n911), .A1(n2636), .B0(n2605), .B1(n2278), .Y(
FPADDSUB_DmP_INIT_EWSW[4]) );
AOI22X1TS U3689 ( .A0(n911), .A1(n2631), .B0(n2507), .B1(n2278), .Y(
FPADDSUB_DmP_INIT_EWSW[5]) );
AOI22X1TS U3690 ( .A0(n911), .A1(n2634), .B0(n2510), .B1(n2278), .Y(
FPADDSUB_DmP_INIT_EWSW[6]) );
AOI22X1TS U3691 ( .A0(n911), .A1(n2612), .B0(n2625), .B1(n2278), .Y(
FPADDSUB_DmP_INIT_EWSW[7]) );
AOI22X1TS U3692 ( .A0(n911), .A1(n2647), .B0(n2602), .B1(n2278), .Y(
FPADDSUB_DmP_INIT_EWSW[8]) );
AOI22X1TS U3693 ( .A0(n911), .A1(n2643), .B0(n2513), .B1(n2278), .Y(
FPADDSUB_DmP_INIT_EWSW[9]) );
AOI22X1TS U3694 ( .A0(n911), .A1(n2633), .B0(n2600), .B1(n2278), .Y(
FPADDSUB_DmP_INIT_EWSW[10]) );
AOI22X1TS U3695 ( .A0(n911), .A1(n2650), .B0(n2608), .B1(n2278), .Y(
FPADDSUB_DmP_INIT_EWSW[11]) );
AOI22X1TS U3696 ( .A0(n911), .A1(n2601), .B0(n2632), .B1(n2278), .Y(
FPADDSUB_DmP_INIT_EWSW[12]) );
AOI22X1TS U3697 ( .A0(n911), .A1(n2641), .B0(n2611), .B1(n2284), .Y(
FPADDSUB_DmP_INIT_EWSW[13]) );
AOI22X1TS U3698 ( .A0(n911), .A1(n2517), .B0(n2603), .B1(n2284), .Y(
FPADDSUB_DmP_INIT_EWSW[14]) );
AOI22X1TS U3699 ( .A0(n911), .A1(n2653), .B0(n2606), .B1(n2284), .Y(
FPADDSUB_DmP_INIT_EWSW[15]) );
AOI22X1TS U3700 ( .A0(n911), .A1(n2635), .B0(n2623), .B1(n2284), .Y(
FPADDSUB_DmP_INIT_EWSW[16]) );
AOI22X1TS U3701 ( .A0(n2279), .A1(n2651), .B0(n2609), .B1(n2284), .Y(
FPADDSUB_DmP_INIT_EWSW[17]) );
AOI22X1TS U3702 ( .A0(n2279), .A1(n2648), .B0(n2604), .B1(n2278), .Y(
FPADDSUB_DmP_INIT_EWSW[18]) );
AOI22X1TS U3703 ( .A0(n2279), .A1(n2519), .B0(n939), .B1(n2278), .Y(
FPADDSUB_DmP_INIT_EWSW[19]) );
AOI22X1TS U3704 ( .A0(n2279), .A1(n2642), .B0(n2511), .B1(n2278), .Y(
FPADDSUB_DmP_INIT_EWSW[20]) );
AOI22X1TS U3705 ( .A0(n2279), .A1(n2640), .B0(n2607), .B1(n2278), .Y(
FPADDSUB_DmP_INIT_EWSW[21]) );
AOI22X1TS U3706 ( .A0(n2279), .A1(n2518), .B0(n934), .B1(n2278), .Y(
FPADDSUB_DmP_INIT_EWSW[22]) );
BUFX4TS U3707 ( .A(n2281), .Y(n2280) );
AOI22X1TS U3708 ( .A0(n2279), .A1(n2654), .B0(n2512), .B1(n2280), .Y(
FPADDSUB_DmP_INIT_EWSW[23]) );
AOI22X1TS U3709 ( .A0(n2279), .A1(n2639), .B0(n2282), .B1(n2280), .Y(
FPADDSUB_DmP_INIT_EWSW[24]) );
AOI22X1TS U3710 ( .A0(n2279), .A1(n2652), .B0(n938), .B1(n2280), .Y(
FPADDSUB_DmP_INIT_EWSW[25]) );
AOI22X1TS U3711 ( .A0(n2279), .A1(n2655), .B0(n926), .B1(n2280), .Y(
FPADDSUB_DmP_INIT_EWSW[26]) );
AOI22X1TS U3712 ( .A0(n2279), .A1(n2638), .B0(n935), .B1(n2280), .Y(
FPADDSUB_DmP_INIT_EWSW[27]) );
AOI22X1TS U3713 ( .A0(n2279), .A1(n2515), .B0(n2656), .B1(n2280), .Y(
FPADDSUB_DMP_INIT_EWSW[0]) );
AOI22X1TS U3714 ( .A0(n2277), .A1(n2508), .B0(n2649), .B1(n2280), .Y(
FPADDSUB_DMP_INIT_EWSW[1]) );
AOI22X1TS U3715 ( .A0(n2277), .A1(n2509), .B0(n2637), .B1(n2280), .Y(
FPADDSUB_DMP_INIT_EWSW[2]) );
AOI22X1TS U3716 ( .A0(n2277), .A1(n2610), .B0(n2657), .B1(n2280), .Y(
FPADDSUB_DMP_INIT_EWSW[3]) );
AOI22X1TS U3717 ( .A0(n2277), .A1(n2605), .B0(n2636), .B1(n2280), .Y(
FPADDSUB_DMP_INIT_EWSW[4]) );
AOI22X1TS U3718 ( .A0(n2277), .A1(n2507), .B0(n2631), .B1(n2280), .Y(
FPADDSUB_DMP_INIT_EWSW[5]) );
AOI22X1TS U3719 ( .A0(n2277), .A1(n2510), .B0(n2634), .B1(n2280), .Y(
FPADDSUB_DMP_INIT_EWSW[6]) );
AOI22X1TS U3720 ( .A0(n2277), .A1(n2625), .B0(n2612), .B1(n2280), .Y(
FPADDSUB_DMP_INIT_EWSW[7]) );
AOI22X1TS U3721 ( .A0(n2277), .A1(n2602), .B0(n2647), .B1(n2281), .Y(
FPADDSUB_DMP_INIT_EWSW[8]) );
AOI22X1TS U3722 ( .A0(n2277), .A1(n2513), .B0(n2643), .B1(n2281), .Y(
FPADDSUB_DMP_INIT_EWSW[9]) );
AOI22X1TS U3723 ( .A0(n2277), .A1(n2600), .B0(n2633), .B1(n2280), .Y(
FPADDSUB_DMP_INIT_EWSW[10]) );
AOI22X1TS U3724 ( .A0(n2277), .A1(n2608), .B0(n2650), .B1(n2281), .Y(
FPADDSUB_DMP_INIT_EWSW[11]) );
AOI22X1TS U3725 ( .A0(n2277), .A1(n2632), .B0(n2601), .B1(n2280), .Y(
FPADDSUB_DMP_INIT_EWSW[12]) );
AOI22X1TS U3726 ( .A0(n2277), .A1(n2611), .B0(n2641), .B1(n2281), .Y(
FPADDSUB_DMP_INIT_EWSW[13]) );
AOI22X1TS U3727 ( .A0(n2283), .A1(n2603), .B0(n2517), .B1(n2280), .Y(
FPADDSUB_DMP_INIT_EWSW[14]) );
AOI22X1TS U3728 ( .A0(n2283), .A1(n2606), .B0(n2653), .B1(n2284), .Y(
FPADDSUB_DMP_INIT_EWSW[15]) );
AOI22X1TS U3729 ( .A0(n2279), .A1(n2623), .B0(n2635), .B1(n2284), .Y(
FPADDSUB_DMP_INIT_EWSW[16]) );
AOI22X1TS U3730 ( .A0(n2283), .A1(n2609), .B0(n2651), .B1(n2284), .Y(
FPADDSUB_DMP_INIT_EWSW[17]) );
AOI22X1TS U3731 ( .A0(n2283), .A1(n2604), .B0(n2648), .B1(n2284), .Y(
FPADDSUB_DMP_INIT_EWSW[18]) );
AOI22X1TS U3732 ( .A0(n2283), .A1(n939), .B0(n2519), .B1(n2281), .Y(
FPADDSUB_DMP_INIT_EWSW[19]) );
AOI22X1TS U3733 ( .A0(n2283), .A1(n2511), .B0(n2642), .B1(n2280), .Y(
FPADDSUB_DMP_INIT_EWSW[20]) );
AOI22X1TS U3734 ( .A0(n2283), .A1(n2607), .B0(n2640), .B1(n2280), .Y(
FPADDSUB_DMP_INIT_EWSW[21]) );
AOI22X1TS U3735 ( .A0(n2283), .A1(n934), .B0(n2518), .B1(n2284), .Y(
FPADDSUB_DMP_INIT_EWSW[22]) );
AOI22X1TS U3736 ( .A0(n2283), .A1(n2512), .B0(n2654), .B1(n2281), .Y(
FPADDSUB_DMP_INIT_EWSW[23]) );
AOI22X1TS U3737 ( .A0(n2283), .A1(n2282), .B0(n2639), .B1(n2281), .Y(
FPADDSUB_DMP_INIT_EWSW[24]) );
AOI22X1TS U3738 ( .A0(n2283), .A1(n938), .B0(n2652), .B1(n2284), .Y(
FPADDSUB_DMP_INIT_EWSW[25]) );
AOI22X1TS U3739 ( .A0(n2283), .A1(n926), .B0(n2655), .B1(n2284), .Y(
FPADDSUB_DMP_INIT_EWSW[26]) );
AOI22X1TS U3740 ( .A0(n2283), .A1(n935), .B0(n2638), .B1(n2284), .Y(
FPADDSUB_DMP_INIT_EWSW[27]) );
AO22XLTS U3741 ( .A0(n911), .A1(FPADDSUB_intDX_EWSW[29]), .B0(n2284), .B1(
FPADDSUB_intDY_EWSW[29]), .Y(FPADDSUB_DMP_INIT_EWSW[29]) );
AO22XLTS U3742 ( .A0(n911), .A1(FPADDSUB_intDX_EWSW[30]), .B0(n2284), .B1(
FPADDSUB_intDY_EWSW[30]), .Y(FPADDSUB_DMP_INIT_EWSW[30]) );
OAI22X1TS U3743 ( .A0(n1364), .A1(n2285), .B0(n2290), .B1(n2287), .Y(
FPADDSUB_Data_array_SWR[24]) );
OAI222X1TS U3744 ( .A0(n2290), .A1(n1364), .B0(n2289), .B1(n2288), .C0(n2287), .C1(n2286), .Y(FPADDSUB_Data_array_SWR[23]) );
AO21XLTS U3745 ( .A0(enab_cont_iter), .A1(n936), .B0(n2311), .Y(
FPSENCOS_enab_d_ff5_data_out) );
CLKAND2X2TS U3746 ( .A(n2291), .B(FPADDSUB_sftr_odat_SHT2_SWR[4]), .Y(
FPADDSUB_formatted_number_W[2]) );
CLKAND2X2TS U3747 ( .A(n2291), .B(FPADDSUB_sftr_odat_SHT2_SWR[6]), .Y(
FPADDSUB_formatted_number_W[4]) );
CLKAND2X2TS U3748 ( .A(n2291), .B(FPADDSUB_sftr_odat_SHT2_SWR[7]), .Y(
FPADDSUB_formatted_number_W[5]) );
CLKAND2X2TS U3749 ( .A(n2291), .B(FPADDSUB_sftr_odat_SHT2_SWR[18]), .Y(
FPADDSUB_formatted_number_W[16]) );
CLKAND2X2TS U3750 ( .A(n2291), .B(FPADDSUB_sftr_odat_SHT2_SWR[19]), .Y(
FPADDSUB_formatted_number_W[17]) );
CLKAND2X2TS U3751 ( .A(n2291), .B(FPADDSUB_sftr_odat_SHT2_SWR[21]), .Y(
FPADDSUB_formatted_number_W[19]) );
NOR2BX1TS U3752 ( .AN(FPMULT_Sgf_normalized_result[2]), .B(n2292), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[2]) );
NOR2BX1TS U3753 ( .AN(FPMULT_Sgf_normalized_result[4]), .B(n2292), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[4]) );
NOR2BX1TS U3754 ( .AN(FPMULT_Sgf_normalized_result[6]), .B(n2292), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[6]) );
NOR2BX1TS U3755 ( .AN(FPMULT_Sgf_normalized_result[8]), .B(n2292), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[8]) );
NOR2BX1TS U3756 ( .AN(FPMULT_Sgf_normalized_result[10]), .B(n2292), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[10]) );
NOR2BX1TS U3757 ( .AN(FPMULT_Sgf_normalized_result[12]), .B(n2292), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[12]) );
NOR2BX1TS U3758 ( .AN(FPMULT_Sgf_normalized_result[14]), .B(n2292), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[14]) );
NOR2BX1TS U3759 ( .AN(FPMULT_Sgf_normalized_result[16]), .B(n2292), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[16]) );
NOR2BX1TS U3760 ( .AN(FPMULT_Sgf_normalized_result[18]), .B(n2292), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[18]) );
NOR2BX1TS U3761 ( .AN(FPMULT_Sgf_normalized_result[20]), .B(n2292), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[20]) );
NOR2BX1TS U3762 ( .AN(FPMULT_Sgf_normalized_result[22]), .B(n2292), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[22]) );
CLKAND2X2TS U3763 ( .A(FPSENCOS_d_ff_Xn[0]), .B(n2293), .Y(
FPSENCOS_first_mux_X[0]) );
NAND2BXLTS U3764 ( .AN(FPSENCOS_d_ff_Xn[1]), .B(n2299), .Y(
FPSENCOS_first_mux_X[1]) );
NAND2BXLTS U3765 ( .AN(FPSENCOS_d_ff_Xn[2]), .B(n2297), .Y(
FPSENCOS_first_mux_X[2]) );
NAND2BXLTS U3766 ( .AN(FPSENCOS_d_ff_Xn[3]), .B(n2297), .Y(
FPSENCOS_first_mux_X[3]) );
CLKAND2X2TS U3767 ( .A(FPSENCOS_d_ff_Xn[4]), .B(n2299), .Y(
FPSENCOS_first_mux_X[4]) );
NAND2BXLTS U3768 ( .AN(FPSENCOS_d_ff_Xn[5]), .B(n2293), .Y(
FPSENCOS_first_mux_X[5]) );
NAND2BXLTS U3769 ( .AN(FPSENCOS_d_ff_Xn[6]), .B(n2293), .Y(
FPSENCOS_first_mux_X[6]) );
NAND2BXLTS U3770 ( .AN(FPSENCOS_d_ff_Xn[7]), .B(n2293), .Y(
FPSENCOS_first_mux_X[7]) );
CLKAND2X2TS U3771 ( .A(FPSENCOS_d_ff_Xn[8]), .B(n2299), .Y(
FPSENCOS_first_mux_X[8]) );
CLKAND2X2TS U3772 ( .A(FPSENCOS_d_ff_Xn[9]), .B(n2294), .Y(
FPSENCOS_first_mux_X[9]) );
NAND2BXLTS U3773 ( .AN(FPSENCOS_d_ff_Xn[10]), .B(n2293), .Y(
FPSENCOS_first_mux_X[10]) );
CLKAND2X2TS U3774 ( .A(FPSENCOS_d_ff_Xn[11]), .B(n2297), .Y(
FPSENCOS_first_mux_X[11]) );
NAND2BXLTS U3775 ( .AN(FPSENCOS_d_ff_Xn[12]), .B(n2293), .Y(
FPSENCOS_first_mux_X[12]) );
NAND2BXLTS U3776 ( .AN(FPSENCOS_d_ff_Xn[13]), .B(n2293), .Y(
FPSENCOS_first_mux_X[13]) );
NAND2BXLTS U3777 ( .AN(FPSENCOS_d_ff_Xn[14]), .B(n2293), .Y(
FPSENCOS_first_mux_X[14]) );
CLKAND2X2TS U3778 ( .A(FPSENCOS_d_ff_Xn[15]), .B(n2299), .Y(
FPSENCOS_first_mux_X[15]) );
NAND2BXLTS U3779 ( .AN(FPSENCOS_d_ff_Xn[16]), .B(n2299), .Y(
FPSENCOS_first_mux_X[16]) );
NAND2BXLTS U3780 ( .AN(FPSENCOS_d_ff_Xn[17]), .B(n2293), .Y(
FPSENCOS_first_mux_X[17]) );
CLKAND2X2TS U3781 ( .A(FPSENCOS_d_ff_Xn[18]), .B(n2298), .Y(
FPSENCOS_first_mux_X[18]) );
NAND2BXLTS U3782 ( .AN(FPSENCOS_d_ff_Xn[19]), .B(n2297), .Y(
FPSENCOS_first_mux_X[19]) );
NAND2BXLTS U3783 ( .AN(FPSENCOS_d_ff_Xn[20]), .B(n2299), .Y(
FPSENCOS_first_mux_X[20]) );
CLKAND2X2TS U3784 ( .A(FPSENCOS_d_ff_Xn[21]), .B(n2297), .Y(
FPSENCOS_first_mux_X[21]) );
CLKAND2X2TS U3785 ( .A(FPSENCOS_d_ff_Xn[22]), .B(n2299), .Y(
FPSENCOS_first_mux_X[22]) );
CLKAND2X2TS U3786 ( .A(FPSENCOS_d_ff_Xn[23]), .B(n2294), .Y(
FPSENCOS_first_mux_X[23]) );
NAND2BXLTS U3787 ( .AN(FPSENCOS_d_ff_Xn[24]), .B(n2293), .Y(
FPSENCOS_first_mux_X[24]) );
NAND2BXLTS U3788 ( .AN(FPSENCOS_d_ff_Xn[25]), .B(n2293), .Y(
FPSENCOS_first_mux_X[25]) );
NAND2BXLTS U3789 ( .AN(FPSENCOS_d_ff_Xn[26]), .B(n2293), .Y(
FPSENCOS_first_mux_X[26]) );
NAND2BXLTS U3790 ( .AN(FPSENCOS_d_ff_Xn[27]), .B(n2293), .Y(
FPSENCOS_first_mux_X[27]) );
NAND2BXLTS U3791 ( .AN(FPSENCOS_d_ff_Xn[28]), .B(n2294), .Y(
FPSENCOS_first_mux_X[28]) );
NAND2BXLTS U3792 ( .AN(FPSENCOS_d_ff_Xn[29]), .B(n2294), .Y(
FPSENCOS_first_mux_X[29]) );
CLKAND2X2TS U3793 ( .A(FPSENCOS_d_ff_Xn[30]), .B(n2294), .Y(
FPSENCOS_first_mux_X[30]) );
CLKAND2X2TS U3794 ( .A(FPSENCOS_d_ff_Xn[31]), .B(n2297), .Y(
FPSENCOS_first_mux_X[31]) );
CLKAND2X2TS U3795 ( .A(FPSENCOS_d_ff_Yn[0]), .B(n2294), .Y(
FPSENCOS_first_mux_Y[0]) );
CLKAND2X2TS U3796 ( .A(FPSENCOS_d_ff_Yn[1]), .B(n2298), .Y(
FPSENCOS_first_mux_Y[1]) );
CLKAND2X2TS U3797 ( .A(FPSENCOS_d_ff_Yn[2]), .B(n2294), .Y(
FPSENCOS_first_mux_Y[2]) );
CLKAND2X2TS U3798 ( .A(FPSENCOS_d_ff_Yn[3]), .B(n2294), .Y(
FPSENCOS_first_mux_Y[3]) );
CLKAND2X2TS U3799 ( .A(FPSENCOS_d_ff_Yn[4]), .B(n2294), .Y(
FPSENCOS_first_mux_Y[4]) );
CLKAND2X2TS U3800 ( .A(FPSENCOS_d_ff_Yn[5]), .B(n2294), .Y(
FPSENCOS_first_mux_Y[5]) );
CLKAND2X2TS U3801 ( .A(FPSENCOS_d_ff_Yn[6]), .B(n2294), .Y(
FPSENCOS_first_mux_Y[6]) );
CLKAND2X2TS U3802 ( .A(FPSENCOS_d_ff_Yn[7]), .B(n2294), .Y(
FPSENCOS_first_mux_Y[7]) );
CLKAND2X2TS U3803 ( .A(FPSENCOS_d_ff_Yn[8]), .B(n2294), .Y(
FPSENCOS_first_mux_Y[8]) );
CLKAND2X2TS U3804 ( .A(FPSENCOS_d_ff_Yn[9]), .B(n2294), .Y(
FPSENCOS_first_mux_Y[9]) );
CLKAND2X2TS U3805 ( .A(FPSENCOS_d_ff_Yn[10]), .B(n2294), .Y(
FPSENCOS_first_mux_Y[10]) );
CLKAND2X2TS U3806 ( .A(FPSENCOS_d_ff_Yn[11]), .B(n2299), .Y(
FPSENCOS_first_mux_Y[11]) );
CLKAND2X2TS U3807 ( .A(FPSENCOS_d_ff_Yn[12]), .B(n2297), .Y(
FPSENCOS_first_mux_Y[12]) );
CLKAND2X2TS U3808 ( .A(FPSENCOS_d_ff_Yn[13]), .B(n2298), .Y(
FPSENCOS_first_mux_Y[13]) );
CLKAND2X2TS U3809 ( .A(FPSENCOS_d_ff_Yn[14]), .B(n2298), .Y(
FPSENCOS_first_mux_Y[14]) );
CLKAND2X2TS U3810 ( .A(FPSENCOS_d_ff_Yn[15]), .B(n2299), .Y(
FPSENCOS_first_mux_Y[15]) );
CLKAND2X2TS U3811 ( .A(FPSENCOS_d_ff_Yn[16]), .B(n2297), .Y(
FPSENCOS_first_mux_Y[16]) );
CLKAND2X2TS U3812 ( .A(FPSENCOS_d_ff_Yn[17]), .B(n2297), .Y(
FPSENCOS_first_mux_Y[17]) );
CLKAND2X2TS U3813 ( .A(FPSENCOS_d_ff_Yn[18]), .B(n2299), .Y(
FPSENCOS_first_mux_Y[18]) );
CLKAND2X2TS U3814 ( .A(FPSENCOS_d_ff_Yn[19]), .B(n2299), .Y(
FPSENCOS_first_mux_Y[19]) );
CLKAND2X2TS U3815 ( .A(FPSENCOS_d_ff_Yn[20]), .B(n2294), .Y(
FPSENCOS_first_mux_Y[20]) );
CLKAND2X2TS U3816 ( .A(FPSENCOS_d_ff_Yn[21]), .B(n2294), .Y(
FPSENCOS_first_mux_Y[21]) );
CLKAND2X2TS U3817 ( .A(FPSENCOS_d_ff_Yn[22]), .B(n2297), .Y(
FPSENCOS_first_mux_Y[22]) );
CLKAND2X2TS U3818 ( .A(FPSENCOS_d_ff_Yn[23]), .B(n2298), .Y(
FPSENCOS_first_mux_Y[23]) );
CLKAND2X2TS U3819 ( .A(FPSENCOS_d_ff_Yn[24]), .B(n2299), .Y(
FPSENCOS_first_mux_Y[24]) );
CLKAND2X2TS U3820 ( .A(FPSENCOS_d_ff_Yn[25]), .B(n2293), .Y(
FPSENCOS_first_mux_Y[25]) );
CLKAND2X2TS U3821 ( .A(FPSENCOS_d_ff_Yn[26]), .B(n2293), .Y(
FPSENCOS_first_mux_Y[26]) );
CLKAND2X2TS U3822 ( .A(FPSENCOS_d_ff_Yn[27]), .B(n2293), .Y(
FPSENCOS_first_mux_Y[27]) );
CLKAND2X2TS U3823 ( .A(FPSENCOS_d_ff_Yn[28]), .B(n2297), .Y(
FPSENCOS_first_mux_Y[28]) );
CLKAND2X2TS U3824 ( .A(FPSENCOS_d_ff_Yn[29]), .B(n2297), .Y(
FPSENCOS_first_mux_Y[29]) );
CLKAND2X2TS U3825 ( .A(FPSENCOS_d_ff_Yn[30]), .B(n2299), .Y(
FPSENCOS_first_mux_Y[30]) );
CLKAND2X2TS U3826 ( .A(FPSENCOS_d_ff_Yn[31]), .B(n2293), .Y(
FPSENCOS_first_mux_Y[31]) );
AO22XLTS U3827 ( .A0(n914), .A1(FPSENCOS_d_ff1_Z[0]), .B0(n2297), .B1(
FPSENCOS_d_ff_Zn[0]), .Y(FPSENCOS_first_mux_Z[0]) );
AO22XLTS U3828 ( .A0(n2300), .A1(FPSENCOS_d_ff1_Z[1]), .B0(n2299), .B1(
FPSENCOS_d_ff_Zn[1]), .Y(FPSENCOS_first_mux_Z[1]) );
AO22XLTS U3829 ( .A0(n914), .A1(FPSENCOS_d_ff1_Z[2]), .B0(n2294), .B1(
FPSENCOS_d_ff_Zn[2]), .Y(FPSENCOS_first_mux_Z[2]) );
AO22XLTS U3830 ( .A0(n2295), .A1(FPSENCOS_d_ff1_Z[3]), .B0(n2297), .B1(
FPSENCOS_d_ff_Zn[3]), .Y(FPSENCOS_first_mux_Z[3]) );
AO22XLTS U3831 ( .A0(n914), .A1(FPSENCOS_d_ff1_Z[4]), .B0(n2299), .B1(
FPSENCOS_d_ff_Zn[4]), .Y(FPSENCOS_first_mux_Z[4]) );
AO22XLTS U3832 ( .A0(n914), .A1(FPSENCOS_d_ff1_Z[5]), .B0(n2298), .B1(
FPSENCOS_d_ff_Zn[5]), .Y(FPSENCOS_first_mux_Z[5]) );
AO22XLTS U3833 ( .A0(n2296), .A1(FPSENCOS_d_ff1_Z[6]), .B0(n2294), .B1(
FPSENCOS_d_ff_Zn[6]), .Y(FPSENCOS_first_mux_Z[6]) );
INVX2TS U3834 ( .A(n914), .Y(n2298) );
AO22XLTS U3835 ( .A0(n2296), .A1(FPSENCOS_d_ff1_Z[7]), .B0(n2294), .B1(
FPSENCOS_d_ff_Zn[7]), .Y(FPSENCOS_first_mux_Z[7]) );
AO22XLTS U3836 ( .A0(n2296), .A1(FPSENCOS_d_ff1_Z[8]), .B0(n2297), .B1(
FPSENCOS_d_ff_Zn[8]), .Y(FPSENCOS_first_mux_Z[8]) );
AO22XLTS U3837 ( .A0(n2296), .A1(FPSENCOS_d_ff1_Z[9]), .B0(n2299), .B1(
FPSENCOS_d_ff_Zn[9]), .Y(FPSENCOS_first_mux_Z[9]) );
AO22XLTS U3838 ( .A0(n2296), .A1(FPSENCOS_d_ff1_Z[10]), .B0(n2294), .B1(
FPSENCOS_d_ff_Zn[10]), .Y(FPSENCOS_first_mux_Z[10]) );
AO22XLTS U3839 ( .A0(n2296), .A1(FPSENCOS_d_ff1_Z[11]), .B0(n2297), .B1(
FPSENCOS_d_ff_Zn[11]), .Y(FPSENCOS_first_mux_Z[11]) );
AO22XLTS U3840 ( .A0(n2296), .A1(FPSENCOS_d_ff1_Z[12]), .B0(n2299), .B1(
FPSENCOS_d_ff_Zn[12]), .Y(FPSENCOS_first_mux_Z[12]) );
AO22XLTS U3841 ( .A0(n2296), .A1(FPSENCOS_d_ff1_Z[13]), .B0(n2297), .B1(
FPSENCOS_d_ff_Zn[13]), .Y(FPSENCOS_first_mux_Z[13]) );
AO22XLTS U3842 ( .A0(n2296), .A1(FPSENCOS_d_ff1_Z[14]), .B0(n2299), .B1(
FPSENCOS_d_ff_Zn[14]), .Y(FPSENCOS_first_mux_Z[14]) );
AO22XLTS U3843 ( .A0(n2296), .A1(FPSENCOS_d_ff1_Z[15]), .B0(n2294), .B1(
FPSENCOS_d_ff_Zn[15]), .Y(FPSENCOS_first_mux_Z[15]) );
AO22XLTS U3844 ( .A0(n2296), .A1(FPSENCOS_d_ff1_Z[16]), .B0(n2297), .B1(
FPSENCOS_d_ff_Zn[16]), .Y(FPSENCOS_first_mux_Z[16]) );
AO22XLTS U3845 ( .A0(n2296), .A1(FPSENCOS_d_ff1_Z[17]), .B0(n2299), .B1(
FPSENCOS_d_ff_Zn[17]), .Y(FPSENCOS_first_mux_Z[17]) );
AO22XLTS U3846 ( .A0(n2296), .A1(FPSENCOS_d_ff1_Z[18]), .B0(n2298), .B1(
FPSENCOS_d_ff_Zn[18]), .Y(FPSENCOS_first_mux_Z[18]) );
AO22XLTS U3847 ( .A0(n2296), .A1(FPSENCOS_d_ff1_Z[19]), .B0(n2294), .B1(
FPSENCOS_d_ff_Zn[19]), .Y(FPSENCOS_first_mux_Z[19]) );
AO22XLTS U3848 ( .A0(n2296), .A1(FPSENCOS_d_ff1_Z[20]), .B0(n2297), .B1(
FPSENCOS_d_ff_Zn[20]), .Y(FPSENCOS_first_mux_Z[20]) );
AO22XLTS U3849 ( .A0(n2296), .A1(FPSENCOS_d_ff1_Z[21]), .B0(n2299), .B1(
FPSENCOS_d_ff_Zn[21]), .Y(FPSENCOS_first_mux_Z[21]) );
AO22XLTS U3850 ( .A0(n914), .A1(FPSENCOS_d_ff1_Z[22]), .B0(n2294), .B1(
FPSENCOS_d_ff_Zn[22]), .Y(FPSENCOS_first_mux_Z[22]) );
AO22XLTS U3851 ( .A0(n2300), .A1(FPSENCOS_d_ff1_Z[23]), .B0(n2297), .B1(
FPSENCOS_d_ff_Zn[23]), .Y(FPSENCOS_first_mux_Z[23]) );
AO22XLTS U3852 ( .A0(n2300), .A1(FPSENCOS_d_ff1_Z[24]), .B0(n2299), .B1(
FPSENCOS_d_ff_Zn[24]), .Y(FPSENCOS_first_mux_Z[24]) );
AO22XLTS U3853 ( .A0(n2300), .A1(FPSENCOS_d_ff1_Z[25]), .B0(n2298), .B1(
FPSENCOS_d_ff_Zn[25]), .Y(FPSENCOS_first_mux_Z[25]) );
AO22XLTS U3854 ( .A0(n914), .A1(FPSENCOS_d_ff1_Z[26]), .B0(n2297), .B1(
FPSENCOS_d_ff_Zn[26]), .Y(FPSENCOS_first_mux_Z[26]) );
AO22XLTS U3855 ( .A0(n914), .A1(FPSENCOS_d_ff1_Z[27]), .B0(n2299), .B1(
FPSENCOS_d_ff_Zn[27]), .Y(FPSENCOS_first_mux_Z[27]) );
AO22XLTS U3856 ( .A0(n914), .A1(FPSENCOS_d_ff1_Z[28]), .B0(n2294), .B1(
FPSENCOS_d_ff_Zn[28]), .Y(FPSENCOS_first_mux_Z[28]) );
AO22XLTS U3857 ( .A0(n914), .A1(FPSENCOS_d_ff1_Z[29]), .B0(n2298), .B1(
FPSENCOS_d_ff_Zn[29]), .Y(FPSENCOS_first_mux_Z[29]) );
AO22XLTS U3858 ( .A0(n914), .A1(FPSENCOS_d_ff1_Z[30]), .B0(n2297), .B1(
FPSENCOS_d_ff_Zn[30]), .Y(FPSENCOS_first_mux_Z[30]) );
AO22XLTS U3859 ( .A0(n2300), .A1(FPSENCOS_d_ff1_Z[31]), .B0(n2298), .B1(
FPSENCOS_d_ff_Zn[31]), .Y(FPSENCOS_first_mux_Z[31]) );
AO22XLTS U3860 ( .A0(n2302), .A1(FPSENCOS_d_ff_Xn[0]), .B0(n2303), .B1(
FPSENCOS_d_ff_Yn[0]), .Y(FPSENCOS_mux_sal[0]) );
AO22XLTS U3861 ( .A0(n2302), .A1(FPSENCOS_d_ff_Xn[1]), .B0(n2301), .B1(
FPSENCOS_d_ff_Yn[1]), .Y(FPSENCOS_mux_sal[1]) );
AO22XLTS U3862 ( .A0(n2302), .A1(FPSENCOS_d_ff_Xn[2]), .B0(n2301), .B1(
FPSENCOS_d_ff_Yn[2]), .Y(FPSENCOS_mux_sal[2]) );
AO22XLTS U3863 ( .A0(n2302), .A1(FPSENCOS_d_ff_Xn[3]), .B0(n2301), .B1(
FPSENCOS_d_ff_Yn[3]), .Y(FPSENCOS_mux_sal[3]) );
AO22XLTS U3864 ( .A0(n2302), .A1(FPSENCOS_d_ff_Xn[4]), .B0(n2301), .B1(
FPSENCOS_d_ff_Yn[4]), .Y(FPSENCOS_mux_sal[4]) );
AO22XLTS U3865 ( .A0(n2302), .A1(FPSENCOS_d_ff_Xn[5]), .B0(n2301), .B1(
FPSENCOS_d_ff_Yn[5]), .Y(FPSENCOS_mux_sal[5]) );
AO22XLTS U3866 ( .A0(n2302), .A1(FPSENCOS_d_ff_Xn[6]), .B0(n2301), .B1(
FPSENCOS_d_ff_Yn[6]), .Y(FPSENCOS_mux_sal[6]) );
AO22XLTS U3867 ( .A0(n2302), .A1(FPSENCOS_d_ff_Xn[7]), .B0(n2301), .B1(
FPSENCOS_d_ff_Yn[7]), .Y(FPSENCOS_mux_sal[7]) );
AO22XLTS U3868 ( .A0(n2302), .A1(FPSENCOS_d_ff_Xn[8]), .B0(n2301), .B1(
FPSENCOS_d_ff_Yn[8]), .Y(FPSENCOS_mux_sal[8]) );
AO22XLTS U3869 ( .A0(n2302), .A1(FPSENCOS_d_ff_Xn[9]), .B0(n2301), .B1(
FPSENCOS_d_ff_Yn[9]), .Y(FPSENCOS_mux_sal[9]) );
AO22XLTS U3870 ( .A0(n2302), .A1(FPSENCOS_d_ff_Xn[10]), .B0(n2301), .B1(
FPSENCOS_d_ff_Yn[10]), .Y(FPSENCOS_mux_sal[10]) );
AO22XLTS U3871 ( .A0(n2302), .A1(FPSENCOS_d_ff_Xn[11]), .B0(n2301), .B1(
FPSENCOS_d_ff_Yn[11]), .Y(FPSENCOS_mux_sal[11]) );
AO22XLTS U3872 ( .A0(n2302), .A1(FPSENCOS_d_ff_Xn[12]), .B0(n2303), .B1(
FPSENCOS_d_ff_Yn[12]), .Y(FPSENCOS_mux_sal[12]) );
AO22XLTS U3873 ( .A0(n2304), .A1(FPSENCOS_d_ff_Xn[13]), .B0(n2303), .B1(
FPSENCOS_d_ff_Yn[13]), .Y(FPSENCOS_mux_sal[13]) );
AO22XLTS U3874 ( .A0(n2304), .A1(FPSENCOS_d_ff_Xn[14]), .B0(n2303), .B1(
FPSENCOS_d_ff_Yn[14]), .Y(FPSENCOS_mux_sal[14]) );
AO22XLTS U3875 ( .A0(n2304), .A1(FPSENCOS_d_ff_Xn[15]), .B0(n2303), .B1(
FPSENCOS_d_ff_Yn[15]), .Y(FPSENCOS_mux_sal[15]) );
AO22XLTS U3876 ( .A0(n2304), .A1(FPSENCOS_d_ff_Xn[16]), .B0(n2303), .B1(
FPSENCOS_d_ff_Yn[16]), .Y(FPSENCOS_mux_sal[16]) );
AO22XLTS U3877 ( .A0(n2304), .A1(FPSENCOS_d_ff_Xn[17]), .B0(n2303), .B1(
FPSENCOS_d_ff_Yn[17]), .Y(FPSENCOS_mux_sal[17]) );
AO22XLTS U3878 ( .A0(n2304), .A1(FPSENCOS_d_ff_Xn[18]), .B0(n2303), .B1(
FPSENCOS_d_ff_Yn[18]), .Y(FPSENCOS_mux_sal[18]) );
AO22XLTS U3879 ( .A0(n2304), .A1(FPSENCOS_d_ff_Xn[19]), .B0(n2303), .B1(
FPSENCOS_d_ff_Yn[19]), .Y(FPSENCOS_mux_sal[19]) );
AO22XLTS U3880 ( .A0(n2304), .A1(FPSENCOS_d_ff_Xn[20]), .B0(n2303), .B1(
FPSENCOS_d_ff_Yn[20]), .Y(FPSENCOS_mux_sal[20]) );
AO22XLTS U3881 ( .A0(n2304), .A1(FPSENCOS_d_ff_Xn[21]), .B0(n2303), .B1(
FPSENCOS_d_ff_Yn[21]), .Y(FPSENCOS_mux_sal[21]) );
AO22XLTS U3882 ( .A0(n2304), .A1(FPSENCOS_d_ff_Xn[22]), .B0(n2303), .B1(
FPSENCOS_d_ff_Yn[22]), .Y(FPSENCOS_mux_sal[22]) );
AO22XLTS U3883 ( .A0(n2304), .A1(FPSENCOS_d_ff_Xn[23]), .B0(n2303), .B1(
FPSENCOS_d_ff_Yn[23]), .Y(FPSENCOS_mux_sal[23]) );
AO22XLTS U3884 ( .A0(n2304), .A1(FPSENCOS_d_ff_Xn[24]), .B0(n2303), .B1(
FPSENCOS_d_ff_Yn[24]), .Y(FPSENCOS_mux_sal[24]) );
AO22XLTS U3885 ( .A0(n2304), .A1(FPSENCOS_d_ff_Xn[25]), .B0(n2303), .B1(
FPSENCOS_d_ff_Yn[25]), .Y(FPSENCOS_mux_sal[25]) );
AO22XLTS U3886 ( .A0(n2304), .A1(FPSENCOS_d_ff_Xn[26]), .B0(n2303), .B1(
FPSENCOS_d_ff_Yn[26]), .Y(FPSENCOS_mux_sal[26]) );
AO22XLTS U3887 ( .A0(n2304), .A1(FPSENCOS_d_ff_Xn[27]), .B0(n2303), .B1(
FPSENCOS_d_ff_Yn[27]), .Y(FPSENCOS_mux_sal[27]) );
AO22XLTS U3888 ( .A0(n2304), .A1(FPSENCOS_d_ff_Xn[28]), .B0(n2303), .B1(
FPSENCOS_d_ff_Yn[28]), .Y(FPSENCOS_mux_sal[28]) );
AO22XLTS U3889 ( .A0(n2304), .A1(FPSENCOS_d_ff_Xn[29]), .B0(n2303), .B1(
FPSENCOS_d_ff_Yn[29]), .Y(FPSENCOS_mux_sal[29]) );
AO22XLTS U3890 ( .A0(n2304), .A1(FPSENCOS_d_ff_Xn[30]), .B0(n2301), .B1(
FPSENCOS_d_ff_Yn[30]), .Y(FPSENCOS_mux_sal[30]) );
OAI2BB1X1TS U3891 ( .A0N(n2308), .A1N(n2593), .B0(n2307), .Y(
FPMULT_FS_Module_state_next[2]) );
AOI21X1TS U3892 ( .A0(FPMULT_FS_Module_state_reg[0]), .A1(
FPMULT_FS_Module_state_reg[3]), .B0(n2309), .Y(
FPMULT_FSM_barrel_shifter_load) );
NOR4X1TS U3893 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_next[3]), .B(
enab_cont_iter), .C(FPSENCOS_enab_RB3), .D(FPSENCOS_enab_d_ff_RB1),
.Y(n2312) );
OAI2BB1X1TS U3894 ( .A0N(operation[1]), .A1N(ack_operation), .B0(n2311), .Y(
n2320) );
NAND3XLTS U3895 ( .A(n2313), .B(n2312), .C(n2320), .Y(n2315) );
AOI32X1TS U3896 ( .A0(begin_operation), .A1(n2315), .A2(operation[1]), .B0(
n2314), .B1(n2315), .Y(FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]) );
AO21XLTS U3897 ( .A0(n2437), .A1(n2316), .B0(FPSENCOS_enab_RB3), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]) );
INVX2TS U3898 ( .A(n2319), .Y(n2318) );
OAI22X1TS U3899 ( .A0(FPSENCOS_enab_d_ff4_Zn), .A1(n2318), .B0(n2317), .B1(
n2316), .Y(FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]) );
CLKAND2X2TS U3900 ( .A(FPSENCOS_enab_d_ff4_Zn), .B(n2319), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]) );
OAI2BB1X1TS U3901 ( .A0N(enab_cont_iter), .A1N(n936), .B0(n2320), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]) );
AOI22X1TS U3902 ( .A0(FPSENCOS_d_ff3_sh_x_out[0]), .A1(n2419), .B0(Data_2[0]), .B1(n2370), .Y(n2322) );
AOI22X1TS U3903 ( .A0(n2381), .A1(FPSENCOS_d_ff3_sh_y_out[0]), .B0(n2323),
.B1(FPSENCOS_d_ff3_LUT_out[0]), .Y(n2321) );
NAND2X1TS U3904 ( .A(n2322), .B(n2321), .Y(add_subt_data2[0]) );
AOI22X1TS U3905 ( .A0(n2381), .A1(FPSENCOS_d_ff3_sh_y_out[1]), .B0(n2419),
.B1(FPSENCOS_d_ff3_sh_x_out[1]), .Y(n2325) );
BUFX4TS U3906 ( .A(n2323), .Y(n2401) );
AOI22X1TS U3907 ( .A0(FPSENCOS_d_ff3_LUT_out[1]), .A1(n2401), .B0(Data_2[1]),
.B1(n2330), .Y(n2324) );
NAND2X1TS U3908 ( .A(n2325), .B(n2324), .Y(add_subt_data2[1]) );
AOI22X1TS U3909 ( .A0(n2381), .A1(FPSENCOS_d_ff3_sh_y_out[2]), .B0(n2396),
.B1(FPSENCOS_d_ff3_sh_x_out[2]), .Y(n2327) );
AOI22X1TS U3910 ( .A0(FPSENCOS_d_ff3_LUT_out[2]), .A1(n2401), .B0(Data_2[2]),
.B1(n2330), .Y(n2326) );
NAND2X1TS U3911 ( .A(n2327), .B(n2326), .Y(add_subt_data2[2]) );
AOI22X1TS U3912 ( .A0(n2381), .A1(FPSENCOS_d_ff3_sh_y_out[4]), .B0(n2339),
.B1(FPSENCOS_d_ff3_sh_x_out[4]), .Y(n2329) );
AOI22X1TS U3913 ( .A0(FPSENCOS_d_ff3_LUT_out[4]), .A1(n2401), .B0(Data_2[4]),
.B1(n2330), .Y(n2328) );
NAND2X1TS U3914 ( .A(n2329), .B(n2328), .Y(add_subt_data2[4]) );
AOI22X1TS U3915 ( .A0(n2420), .A1(FPSENCOS_d_ff3_sh_y_out[6]), .B0(n2339),
.B1(FPSENCOS_d_ff3_sh_x_out[6]), .Y(n2332) );
AOI22X1TS U3916 ( .A0(FPSENCOS_d_ff3_LUT_out[6]), .A1(n2401), .B0(Data_2[6]),
.B1(n2330), .Y(n2331) );
NAND2X1TS U3917 ( .A(n2332), .B(n2331), .Y(add_subt_data2[6]) );
AOI22X1TS U3918 ( .A0(FPSENCOS_d_ff3_sh_x_out[8]), .A1(n2419), .B0(Data_2[8]), .B1(n2370), .Y(n2334) );
AOI22X1TS U3919 ( .A0(n2381), .A1(FPSENCOS_d_ff3_sh_y_out[8]), .B0(n2323),
.B1(FPSENCOS_d_ff3_LUT_out[8]), .Y(n2333) );
NAND2X1TS U3920 ( .A(n2334), .B(n2333), .Y(add_subt_data2[8]) );
AOI22X1TS U3921 ( .A0(n2381), .A1(FPSENCOS_d_ff3_sh_y_out[9]), .B0(n2339),
.B1(FPSENCOS_d_ff3_sh_x_out[9]), .Y(n2336) );
AOI22X1TS U3922 ( .A0(FPSENCOS_d_ff3_LUT_out[9]), .A1(n2401), .B0(Data_2[9]),
.B1(n2370), .Y(n2335) );
NAND2X1TS U3923 ( .A(n2336), .B(n2335), .Y(add_subt_data2[9]) );
AOI22X1TS U3924 ( .A0(n2401), .A1(FPSENCOS_d_ff3_LUT_out[10]), .B0(n2339),
.B1(FPSENCOS_d_ff3_sh_x_out[10]), .Y(n2338) );
AOI22X1TS U3925 ( .A0(FPSENCOS_d_ff3_sh_y_out[10]), .A1(n2420), .B0(
Data_2[10]), .B1(n2370), .Y(n2337) );
NAND2X1TS U3926 ( .A(n2338), .B(n2337), .Y(add_subt_data2[10]) );
AOI22X1TS U3927 ( .A0(n2381), .A1(FPSENCOS_d_ff3_sh_y_out[12]), .B0(n2339),
.B1(FPSENCOS_d_ff3_sh_x_out[12]), .Y(n2341) );
AOI22X1TS U3928 ( .A0(FPSENCOS_d_ff3_LUT_out[12]), .A1(n2401), .B0(
Data_2[12]), .B1(n2370), .Y(n2340) );
NAND2X1TS U3929 ( .A(n2341), .B(n2340), .Y(add_subt_data2[12]) );
AOI22X1TS U3930 ( .A0(n2420), .A1(FPSENCOS_d_ff3_sh_y_out[21]), .B0(n2396),
.B1(FPSENCOS_d_ff3_sh_x_out[21]), .Y(n2343) );
AOI22X1TS U3931 ( .A0(FPSENCOS_d_ff3_LUT_out[21]), .A1(n2401), .B0(
Data_2[21]), .B1(n2370), .Y(n2342) );
NAND2X1TS U3932 ( .A(n2343), .B(n2342), .Y(add_subt_data2[21]) );
AOI22X1TS U3933 ( .A0(n2425), .A1(FPSENCOS_d_ff3_LUT_out[23]), .B0(n2396),
.B1(FPSENCOS_d_ff3_sh_x_out[23]), .Y(n2345) );
AOI22X1TS U3934 ( .A0(FPSENCOS_d_ff3_sh_y_out[23]), .A1(n2424), .B0(
Data_2[23]), .B1(n2370), .Y(n2344) );
NAND2X1TS U3935 ( .A(n2345), .B(n2344), .Y(add_subt_data2[23]) );
AOI22X1TS U3936 ( .A0(FPSENCOS_d_ff3_LUT_out[24]), .A1(n2401), .B0(
Data_2[24]), .B1(n2370), .Y(n2347) );
AOI22X1TS U3937 ( .A0(n2420), .A1(FPSENCOS_d_ff3_sh_y_out[24]), .B0(n2396),
.B1(FPSENCOS_d_ff3_sh_x_out[24]), .Y(n2346) );
NAND2X1TS U3938 ( .A(n2347), .B(n2346), .Y(add_subt_data2[24]) );
AOI22X1TS U3939 ( .A0(FPSENCOS_d_ff3_sh_x_out[25]), .A1(n2419), .B0(
Data_2[25]), .B1(n2406), .Y(n2349) );
AOI22X1TS U3940 ( .A0(n2424), .A1(FPSENCOS_d_ff3_sh_y_out[25]), .B0(n2323),
.B1(FPSENCOS_d_ff3_LUT_out[25]), .Y(n2348) );
NAND2X1TS U3941 ( .A(n2349), .B(n2348), .Y(add_subt_data2[25]) );
AOI22X1TS U3942 ( .A0(n2425), .A1(FPSENCOS_d_ff3_LUT_out[26]), .B0(n2396),
.B1(FPSENCOS_d_ff3_sh_x_out[26]), .Y(n2351) );
AOI22X1TS U3943 ( .A0(FPSENCOS_d_ff3_sh_y_out[26]), .A1(n2381), .B0(
Data_2[26]), .B1(n2370), .Y(n2350) );
NAND2X1TS U3944 ( .A(n2351), .B(n2350), .Y(add_subt_data2[26]) );
AO22XLTS U3945 ( .A0(operation[2]), .A1(n2352), .B0(n2353), .B1(
overflow_flag_addsubt), .Y(overflow_flag) );
AO22XLTS U3946 ( .A0(operation[2]), .A1(underflow_flag_mult), .B0(n2353),
.B1(underflow_flag_addsubt), .Y(underflow_flag) );
AO22XLTS U3947 ( .A0(n2673), .A1(FPADDSUB_LZD_raw_out_EWR[2]), .B0(
FPADDSUB_Shift_amount_SHT1_EWR[2]), .B1(n2462), .Y(
FPADDSUB_shft_value_mux_o_EWR[2]) );
AO22XLTS U3948 ( .A0(n2673), .A1(FPADDSUB_LZD_raw_out_EWR[3]), .B0(
FPADDSUB_Shift_amount_SHT1_EWR[3]), .B1(n2462), .Y(
FPADDSUB_shft_value_mux_o_EWR[3]) );
AO22XLTS U3949 ( .A0(n2673), .A1(FPADDSUB_LZD_raw_out_EWR[4]), .B0(
FPADDSUB_Shift_amount_SHT1_EWR[4]), .B1(n2462), .Y(
FPADDSUB_shft_value_mux_o_EWR[4]) );
AOI22X1TS U3950 ( .A0(n2424), .A1(FPSENCOS_d_ff2_X[0]), .B0(n2423), .B1(
FPSENCOS_d_ff2_Y[0]), .Y(n2355) );
AOI22X1TS U3951 ( .A0(FPSENCOS_d_ff2_Z[0]), .A1(n2401), .B0(Data_1[0]), .B1(
n2330), .Y(n2354) );
NAND2X1TS U3952 ( .A(n2355), .B(n2354), .Y(add_subt_data1[0]) );
AOI22X1TS U3953 ( .A0(n2424), .A1(FPSENCOS_d_ff2_X[1]), .B0(n2423), .B1(
FPSENCOS_d_ff2_Y[1]), .Y(n2357) );
AOI22X1TS U3954 ( .A0(FPSENCOS_d_ff2_Z[1]), .A1(n2401), .B0(Data_1[1]), .B1(
n2406), .Y(n2356) );
NAND2X1TS U3955 ( .A(n2357), .B(n2356), .Y(add_subt_data1[1]) );
AOI22X1TS U3956 ( .A0(n2424), .A1(FPSENCOS_d_ff2_X[2]), .B0(n2423), .B1(
FPSENCOS_d_ff2_Y[2]), .Y(n2359) );
AOI22X1TS U3957 ( .A0(FPSENCOS_d_ff2_Z[2]), .A1(n2401), .B0(Data_1[2]), .B1(
n2406), .Y(n2358) );
NAND2X1TS U3958 ( .A(n2359), .B(n2358), .Y(add_subt_data1[2]) );
AOI22X1TS U3959 ( .A0(n2425), .A1(FPSENCOS_d_ff2_Z[3]), .B0(n2423), .B1(
FPSENCOS_d_ff2_Y[3]), .Y(n2361) );
AOI22X1TS U3960 ( .A0(FPSENCOS_d_ff2_X[3]), .A1(n2420), .B0(Data_1[3]), .B1(
n2406), .Y(n2360) );
NAND2X1TS U3961 ( .A(n2361), .B(n2360), .Y(add_subt_data1[3]) );
AOI22X1TS U3962 ( .A0(FPSENCOS_d_ff2_Y[4]), .A1(n2419), .B0(Data_1[4]), .B1(
n2370), .Y(n2363) );
AOI22X1TS U3963 ( .A0(n2424), .A1(FPSENCOS_d_ff2_X[4]), .B0(n2401), .B1(
FPSENCOS_d_ff2_Z[4]), .Y(n2362) );
NAND2X1TS U3964 ( .A(n2363), .B(n2362), .Y(add_subt_data1[4]) );
AOI22X1TS U3965 ( .A0(n2424), .A1(FPSENCOS_d_ff2_X[5]), .B0(n2423), .B1(
FPSENCOS_d_ff2_Y[5]), .Y(n2365) );
AOI22X1TS U3966 ( .A0(FPSENCOS_d_ff2_Z[5]), .A1(n2425), .B0(Data_1[5]), .B1(
n2406), .Y(n2364) );
NAND2X1TS U3967 ( .A(n2365), .B(n2364), .Y(add_subt_data1[5]) );
AOI22X1TS U3968 ( .A0(n2425), .A1(FPSENCOS_d_ff2_Z[6]), .B0(n2423), .B1(
FPSENCOS_d_ff2_Y[6]), .Y(n2367) );
AOI22X1TS U3969 ( .A0(FPSENCOS_d_ff2_X[6]), .A1(n2381), .B0(Data_1[6]), .B1(
n2406), .Y(n2366) );
NAND2X1TS U3970 ( .A(n2367), .B(n2366), .Y(add_subt_data1[6]) );
AOI22X1TS U3971 ( .A0(n2425), .A1(FPSENCOS_d_ff2_Z[7]), .B0(n2423), .B1(
FPSENCOS_d_ff2_Y[7]), .Y(n2369) );
AOI22X1TS U3972 ( .A0(FPSENCOS_d_ff2_X[7]), .A1(n2424), .B0(Data_1[7]), .B1(
n2370), .Y(n2368) );
NAND2X1TS U3973 ( .A(n2369), .B(n2368), .Y(add_subt_data1[7]) );
AOI22X1TS U3974 ( .A0(FPSENCOS_d_ff2_Y[8]), .A1(n2419), .B0(Data_1[8]), .B1(
n2370), .Y(n2372) );
AOI22X1TS U3975 ( .A0(n2424), .A1(FPSENCOS_d_ff2_X[8]), .B0(n2401), .B1(
FPSENCOS_d_ff2_Z[8]), .Y(n2371) );
NAND2X1TS U3976 ( .A(n2372), .B(n2371), .Y(add_subt_data1[8]) );
AOI22X1TS U3977 ( .A0(n2425), .A1(FPSENCOS_d_ff2_Z[9]), .B0(n2423), .B1(
FPSENCOS_d_ff2_Y[9]), .Y(n2374) );
AOI22X1TS U3978 ( .A0(FPSENCOS_d_ff2_X[9]), .A1(n2381), .B0(Data_1[9]), .B1(
n2370), .Y(n2373) );
NAND2X1TS U3979 ( .A(n2374), .B(n2373), .Y(add_subt_data1[9]) );
AOI22X1TS U3980 ( .A0(n2424), .A1(FPSENCOS_d_ff2_X[10]), .B0(n2419), .B1(
FPSENCOS_d_ff2_Y[10]), .Y(n2376) );
AOI22X1TS U3981 ( .A0(FPSENCOS_d_ff2_Z[10]), .A1(n2425), .B0(Data_1[10]),
.B1(n2406), .Y(n2375) );
NAND2X1TS U3982 ( .A(n2376), .B(n2375), .Y(add_subt_data1[10]) );
AOI22X1TS U3983 ( .A0(n2424), .A1(FPSENCOS_d_ff2_X[11]), .B0(n2423), .B1(
FPSENCOS_d_ff2_Y[11]), .Y(n2378) );
AOI22X1TS U3984 ( .A0(FPSENCOS_d_ff2_Z[11]), .A1(n2425), .B0(Data_1[11]),
.B1(n2406), .Y(n2377) );
NAND2X1TS U3985 ( .A(n2378), .B(n2377), .Y(add_subt_data1[11]) );
AOI22X1TS U3986 ( .A0(n2401), .A1(FPSENCOS_d_ff2_Z[12]), .B0(n2423), .B1(
FPSENCOS_d_ff2_Y[12]), .Y(n2380) );
AOI22X1TS U3987 ( .A0(FPSENCOS_d_ff2_X[12]), .A1(n2381), .B0(Data_1[12]),
.B1(n2406), .Y(n2379) );
NAND2X1TS U3988 ( .A(n2380), .B(n2379), .Y(add_subt_data1[12]) );
AOI22X1TS U3989 ( .A0(FPSENCOS_d_ff2_Y[13]), .A1(n2419), .B0(Data_1[13]),
.B1(n2406), .Y(n2383) );
AOI22X1TS U3990 ( .A0(n2381), .A1(FPSENCOS_d_ff2_X[13]), .B0(n2323), .B1(
FPSENCOS_d_ff2_Z[13]), .Y(n2382) );
NAND2X1TS U3991 ( .A(n2383), .B(n2382), .Y(add_subt_data1[13]) );
AOI22X1TS U3992 ( .A0(n2401), .A1(FPSENCOS_d_ff2_Z[14]), .B0(n2396), .B1(
FPSENCOS_d_ff2_Y[14]), .Y(n2385) );
AOI22X1TS U3993 ( .A0(FPSENCOS_d_ff2_X[14]), .A1(n2424), .B0(Data_1[14]),
.B1(n2406), .Y(n2384) );
NAND2X1TS U3994 ( .A(n2385), .B(n2384), .Y(add_subt_data1[14]) );
AOI22X1TS U3995 ( .A0(n2420), .A1(FPSENCOS_d_ff2_X[15]), .B0(n2419), .B1(
FPSENCOS_d_ff2_Y[15]), .Y(n2387) );
AOI22X1TS U3996 ( .A0(FPSENCOS_d_ff2_Z[15]), .A1(n2425), .B0(Data_1[15]),
.B1(n2406), .Y(n2386) );
NAND2X1TS U3997 ( .A(n2387), .B(n2386), .Y(add_subt_data1[15]) );
AOI22X1TS U3998 ( .A0(n2420), .A1(FPSENCOS_d_ff2_X[16]), .B0(n2419), .B1(
FPSENCOS_d_ff2_Y[16]), .Y(n2389) );
AOI22X1TS U3999 ( .A0(FPSENCOS_d_ff2_Z[16]), .A1(n2425), .B0(Data_1[16]),
.B1(n2406), .Y(n2388) );
NAND2X1TS U4000 ( .A(n2389), .B(n2388), .Y(add_subt_data1[16]) );
AOI22X1TS U4001 ( .A0(n2401), .A1(FPSENCOS_d_ff2_Z[17]), .B0(n2419), .B1(
FPSENCOS_d_ff2_Y[17]), .Y(n2391) );
AOI22X1TS U4002 ( .A0(FPSENCOS_d_ff2_X[17]), .A1(n2424), .B0(Data_1[17]),
.B1(n2406), .Y(n2390) );
NAND2X1TS U4003 ( .A(n2391), .B(n2390), .Y(add_subt_data1[17]) );
AOI22X1TS U4004 ( .A0(n2425), .A1(FPSENCOS_d_ff2_Z[18]), .B0(n2423), .B1(
FPSENCOS_d_ff2_Y[18]), .Y(n2393) );
AOI22X1TS U4005 ( .A0(FPSENCOS_d_ff2_X[18]), .A1(n2420), .B0(Data_1[18]),
.B1(n2406), .Y(n2392) );
NAND2X1TS U4006 ( .A(n2393), .B(n2392), .Y(add_subt_data1[18]) );
AOI22X1TS U4007 ( .A0(FPSENCOS_d_ff2_Y[19]), .A1(n2419), .B0(Data_1[19]),
.B1(n2406), .Y(n2395) );
AOI22X1TS U4008 ( .A0(n2424), .A1(FPSENCOS_d_ff2_X[19]), .B0(n2323), .B1(
FPSENCOS_d_ff2_Z[19]), .Y(n2394) );
NAND2X1TS U4009 ( .A(n2395), .B(n2394), .Y(add_subt_data1[19]) );
AOI22X1TS U4010 ( .A0(FPSENCOS_d_ff2_Z[20]), .A1(n2425), .B0(Data_1[20]),
.B1(n2406), .Y(n2398) );
AOI22X1TS U4011 ( .A0(n2424), .A1(FPSENCOS_d_ff2_X[20]), .B0(n2396), .B1(
FPSENCOS_d_ff2_Y[20]), .Y(n2397) );
NAND2X1TS U4012 ( .A(n2398), .B(n2397), .Y(add_subt_data1[20]) );
AOI22X1TS U4013 ( .A0(n2424), .A1(FPSENCOS_d_ff2_X[21]), .B0(n2423), .B1(
FPSENCOS_d_ff2_Y[21]), .Y(n2400) );
AOI22X1TS U4014 ( .A0(FPSENCOS_d_ff2_Z[21]), .A1(n2425), .B0(Data_1[21]),
.B1(n2406), .Y(n2399) );
NAND2X1TS U4015 ( .A(n2400), .B(n2399), .Y(add_subt_data1[21]) );
AOI22X1TS U4016 ( .A0(n2401), .A1(FPSENCOS_d_ff2_Z[22]), .B0(n2419), .B1(
FPSENCOS_d_ff2_Y[22]), .Y(n2403) );
AOI22X1TS U4017 ( .A0(FPSENCOS_d_ff2_X[22]), .A1(n2420), .B0(Data_1[22]),
.B1(n2406), .Y(n2402) );
NAND2X1TS U4018 ( .A(n2403), .B(n2402), .Y(add_subt_data1[22]) );
AOI22X1TS U4019 ( .A0(n2420), .A1(FPSENCOS_d_ff2_X[23]), .B0(n2423), .B1(
FPSENCOS_d_ff2_Y[23]), .Y(n2405) );
AOI22X1TS U4020 ( .A0(FPSENCOS_d_ff2_Z[23]), .A1(n2425), .B0(Data_1[23]),
.B1(n2406), .Y(n2404) );
NAND2X1TS U4021 ( .A(n2405), .B(n2404), .Y(add_subt_data1[23]) );
AOI22X1TS U4022 ( .A0(FPSENCOS_d_ff2_Y[24]), .A1(n2419), .B0(Data_1[24]),
.B1(n2406), .Y(n2408) );
AOI22X1TS U4023 ( .A0(n2424), .A1(FPSENCOS_d_ff2_X[24]), .B0(n2323), .B1(
FPSENCOS_d_ff2_Z[24]), .Y(n2407) );
NAND2X1TS U4024 ( .A(n2408), .B(n2407), .Y(add_subt_data1[24]) );
AOI22X1TS U4025 ( .A0(FPSENCOS_d_ff2_Z[25]), .A1(n2425), .B0(Data_1[25]),
.B1(n2330), .Y(n2410) );
AOI22X1TS U4026 ( .A0(n2420), .A1(FPSENCOS_d_ff2_X[25]), .B0(n2419), .B1(
FPSENCOS_d_ff2_Y[25]), .Y(n2409) );
NAND2X1TS U4027 ( .A(n2410), .B(n2409), .Y(add_subt_data1[25]) );
AOI22X1TS U4028 ( .A0(n2425), .A1(FPSENCOS_d_ff2_Z[26]), .B0(n2419), .B1(
FPSENCOS_d_ff2_Y[26]), .Y(n2412) );
AOI22X1TS U4029 ( .A0(FPSENCOS_d_ff2_X[26]), .A1(n2424), .B0(Data_1[26]),
.B1(n2370), .Y(n2411) );
NAND2X1TS U4030 ( .A(n2412), .B(n2411), .Y(add_subt_data1[26]) );
AOI22X1TS U4031 ( .A0(n2424), .A1(FPSENCOS_d_ff2_X[27]), .B0(n2419), .B1(
n964), .Y(n2414) );
AOI22X1TS U4032 ( .A0(FPSENCOS_d_ff2_Z[27]), .A1(n2425), .B0(Data_1[27]),
.B1(n2330), .Y(n2413) );
NAND2X1TS U4033 ( .A(n2414), .B(n2413), .Y(add_subt_data1[27]) );
AOI22X1TS U4034 ( .A0(n2424), .A1(FPSENCOS_d_ff2_X[28]), .B0(n2419), .B1(
FPSENCOS_d_ff2_Y[28]), .Y(n2416) );
AOI22X1TS U4035 ( .A0(FPSENCOS_d_ff2_Z[28]), .A1(n2425), .B0(Data_1[28]),
.B1(n2330), .Y(n2415) );
NAND2X1TS U4036 ( .A(n2416), .B(n2415), .Y(add_subt_data1[28]) );
AOI22X1TS U4037 ( .A0(n2425), .A1(FPSENCOS_d_ff2_Z[29]), .B0(n2419), .B1(
n955), .Y(n2418) );
AOI22X1TS U4038 ( .A0(FPSENCOS_d_ff2_X[29]), .A1(n2424), .B0(Data_1[29]),
.B1(n2370), .Y(n2417) );
NAND2X1TS U4039 ( .A(n2418), .B(n2417), .Y(add_subt_data1[29]) );
AOI22X1TS U4040 ( .A0(FPSENCOS_d_ff2_Y[30]), .A1(n2419), .B0(Data_1[30]),
.B1(n2370), .Y(n2422) );
AOI22X1TS U4041 ( .A0(n2420), .A1(FPSENCOS_d_ff2_X[30]), .B0(n2323), .B1(
FPSENCOS_d_ff2_Z[30]), .Y(n2421) );
NAND2X1TS U4042 ( .A(n2422), .B(n2421), .Y(add_subt_data1[30]) );
AOI22X1TS U4043 ( .A0(n2424), .A1(FPSENCOS_d_ff2_X[31]), .B0(n2423), .B1(
FPSENCOS_d_ff2_Y[31]), .Y(n2427) );
AOI22X1TS U4044 ( .A0(FPSENCOS_d_ff2_Z[31]), .A1(n2425), .B0(Data_1[31]),
.B1(n2370), .Y(n2426) );
NAND2X1TS U4045 ( .A(n2427), .B(n2426), .Y(add_subt_data1[31]) );
NAND2X1TS U4046 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .B(n2428),
.Y(n2429) );
OAI21X1TS U4047 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n2429), .Y(n2439) );
AOI32X1TS U4048 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(n2594), .A2(n908),
.B0(FPSENCOS_cont_iter_out[2]), .B1(FPSENCOS_cont_iter_out[3]), .Y(
n862) );
NOR2BX1TS U4049 ( .AN(n862), .B(n2431), .Y(n860) );
AOI21X1TS U4050 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(n2431), .B0(n2430),
.Y(n859) );
AOI21X1TS U4051 ( .A0(n2431), .A1(n2482), .B0(n2430), .Y(n857) );
AO22XLTS U4052 ( .A0(n2435), .A1(n863), .B0(n908), .B1(n860), .Y(n852) );
CLKAND2X2TS U4053 ( .A(n2432), .B(n859), .Y(n851) );
AOI32X1TS U4054 ( .A0(n2503), .A1(n908), .A2(n2594), .B0(
FPSENCOS_cont_iter_out[3]), .B1(FPSENCOS_cont_iter_out[2]), .Y(n849)
);
AO22XLTS U4055 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(n849), .B0(n860), .B1(
n908), .Y(n850) );
AO22XLTS U4056 ( .A0(n863), .A1(n2435), .B0(n2482), .B1(n2434), .Y(n846) );
XNOR2X1TS U4057 ( .A(n2436), .B(n2675), .Y(n841) );
XNOR2X1TS U4058 ( .A(FPSENCOS_cont_var_out_1_), .B(n2438), .Y(n840) );
CLKAND2X2TS U4059 ( .A(n2440), .B(n2439), .Y(FPADDSUB_enable_Pipeline_input)
);
NOR4X1TS U4060 ( .A(FPMULT_Op_MX[0]), .B(FPMULT_Op_MX[11]), .C(
FPMULT_Op_MX[10]), .D(FPMULT_Op_MX[1]), .Y(n2444) );
NOR4X1TS U4061 ( .A(FPMULT_Op_MX[6]), .B(FPMULT_Op_MX[7]), .C(
FPMULT_Op_MX[8]), .D(FPMULT_Op_MX[9]), .Y(n2443) );
NOR4X1TS U4062 ( .A(FPMULT_Op_MX[18]), .B(FPMULT_Op_MX[21]), .C(
FPMULT_Op_MX[22]), .D(FPMULT_Op_MX[19]), .Y(n2442) );
NOR4X1TS U4063 ( .A(FPMULT_Op_MX[5]), .B(FPMULT_Op_MX[2]), .C(
FPMULT_Op_MX[3]), .D(FPMULT_Op_MX[4]), .Y(n2441) );
NAND4XLTS U4064 ( .A(n2444), .B(n2443), .C(n2442), .D(n2441), .Y(n2461) );
NOR4X1TS U4065 ( .A(FPMULT_Op_MX[28]), .B(FPMULT_Op_MX[27]), .C(
FPMULT_Op_MX[26]), .D(FPMULT_Op_MX[25]), .Y(n2448) );
NOR3XLTS U4066 ( .A(FPMULT_Op_MX[20]), .B(FPMULT_Op_MX[30]), .C(
FPMULT_Op_MX[29]), .Y(n2447) );
NOR4X1TS U4067 ( .A(FPMULT_Op_MX[17]), .B(FPMULT_Op_MX[14]), .C(
FPMULT_Op_MX[15]), .D(FPMULT_Op_MX[16]), .Y(n2446) );
NAND4XLTS U4068 ( .A(n2448), .B(n2447), .C(n2446), .D(n2445), .Y(n2460) );
NOR4X1TS U4069 ( .A(FPMULT_Op_MY[11]), .B(FPMULT_Op_MY[22]), .C(
FPMULT_Op_MY[9]), .D(FPMULT_Op_MY[10]), .Y(n2453) );
NOR4X1TS U4070 ( .A(FPMULT_Op_MY[18]), .B(FPMULT_Op_MY[21]), .C(
FPMULT_Op_MY[19]), .D(FPMULT_Op_MY[20]), .Y(n2452) );
NOR4X1TS U4071 ( .A(intadd_1158_CI), .B(FPMULT_Op_MY[3]), .C(FPMULT_Op_MY[4]), .D(FPMULT_Op_MY[5]), .Y(n2451) );
NOR3XLTS U4072 ( .A(n2449), .B(FPMULT_Op_MY[1]), .C(FPMULT_Op_MY[2]), .Y(
n2450) );
NAND4XLTS U4073 ( .A(n2453), .B(n2452), .C(n2451), .D(n2450), .Y(n2459) );
NOR4X1TS U4074 ( .A(FPMULT_Op_MY[25]), .B(FPMULT_Op_MY[24]), .C(
FPMULT_Op_MY[23]), .D(FPMULT_Op_MY[30]), .Y(n2457) );
NOR4X1TS U4075 ( .A(FPMULT_Op_MY[29]), .B(FPMULT_Op_MY[28]), .C(
FPMULT_Op_MY[27]), .D(FPMULT_Op_MY[26]), .Y(n2456) );
NOR4X1TS U4076 ( .A(FPMULT_Op_MY[17]), .B(FPMULT_Op_MY[16]), .C(
FPMULT_Op_MY[7]), .D(FPMULT_Op_MY[8]), .Y(n2455) );
NAND4XLTS U4077 ( .A(n2457), .B(n2456), .C(n2455), .D(n2454), .Y(n2458) );
OAI22X1TS U4078 ( .A0(n2461), .A1(n2460), .B0(n2459), .B1(n2458), .Y(n115)
);
AO22XLTS U4079 ( .A0(busy), .A1(FPADDSUB_SIGN_FLAG_SHT1), .B0(n2630), .B1(
FPADDSUB_SIGN_FLAG_SHT2), .Y(n817) );
AO22XLTS U4080 ( .A0(n2674), .A1(FPADDSUB_SIGN_FLAG_NRM), .B0(n2462), .B1(
FPADDSUB_SIGN_FLAG_SHT1SHT2), .Y(n814) );
XNOR2X1TS U4081 ( .A(FPADDSUB_intDX_EWSW[31]), .B(n2781), .Y(n30) );
AO22XLTS U4082 ( .A0(busy), .A1(FPADDSUB_OP_FLAG_SHT1), .B0(n2630), .B1(
FPADDSUB_OP_FLAG_SHT2), .Y(n811) );
NOR2BX1TS U4083 ( .AN(FPADDSUB_Shift_reg_FLAGS_7[3]), .B(
FPADDSUB_Shift_reg_FLAGS_7[0]), .Y(FPADDSUB__19_net_) );
NOR2XLTS U4084 ( .A(n955), .B(n2464), .Y(n2463) );
XOR2XLTS U4085 ( .A(n2463), .B(FPSENCOS_d_ff2_Y[30]), .Y(
FPSENCOS_sh_exp_y[7]) );
XNOR2X1TS U4086 ( .A(n955), .B(n2464), .Y(FPSENCOS_sh_exp_y[6]) );
AO21XLTS U4087 ( .A0(intadd_1165_n1), .A1(n964), .B0(n2465), .Y(
FPSENCOS_sh_exp_y[4]) );
NOR2XLTS U4088 ( .A(FPSENCOS_d_ff2_X[29]), .B(n2467), .Y(n2466) );
XOR2XLTS U4089 ( .A(FPSENCOS_d_ff2_X[30]), .B(n2466), .Y(
FPSENCOS_sh_exp_x[7]) );
XNOR2X1TS U4090 ( .A(FPSENCOS_d_ff2_X[29]), .B(n2467), .Y(
FPSENCOS_sh_exp_x[6]) );
AO21XLTS U4091 ( .A0(intadd_1164_n1), .A1(FPSENCOS_d_ff2_X[27]), .B0(n2468),
.Y(FPSENCOS_sh_exp_x[4]) );
CMPR32X4TS U4092 ( .A(FPMULT_Op_MX[13]), .B(FPMULT_Op_MX[19]), .C(
intadd_1163_CI), .CO(intadd_1163_n4), .S(DP_OP_500J326_126_4510_n32)
);
CMPR32X4TS U4093 ( .A(FPMULT_Op_MX[15]), .B(FPMULT_Op_MX[21]), .C(
intadd_1163_n3), .CO(intadd_1163_n2), .S(intadd_1163_SUM_2_) );
CMPR32X4TS U4094 ( .A(FPMULT_Op_MX[7]), .B(FPMULT_Op_MX[1]), .C(
intadd_1161_CI), .CO(intadd_1161_n4), .S(DP_OP_502J326_128_4510_n32)
);
CMPR32X4TS U4095 ( .A(FPMULT_Op_MX[17]), .B(FPMULT_Op_MX[5]), .C(
intadd_1147_n7), .CO(intadd_1147_n6), .S(intadd_1147_SUM_4_) );
CMPR32X4TS U4096 ( .A(FPMULT_Op_MX[13]), .B(FPMULT_Op_MX[1]), .C(
intadd_1147_CI), .CO(intadd_1147_n10), .S(intadd_1147_SUM_0_) );
CMPR32X4TS U4097 ( .A(FPMULT_Op_MX[15]), .B(FPMULT_Op_MX[3]), .C(
intadd_1147_n9), .CO(intadd_1147_n8), .S(intadd_1147_SUM_2_) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
|
/******************************************************************************
* (C) Copyright 2019 AMIQ Consulting
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* MODULE: BLOG
* PROJECT: How To Connect e-Language with Python
* Description: This is a code snippet from the Blog article mentioned on PROJECT
* Link: https://www.amiq.com/consulting/2019/04/25/how-to-connect-e-language-with-python/
*******************************************************************************/
module amiq_mux2_1(input clk, input sel, input in0, input in1, output reg out);
initial out=0;
always@(posedge clk) begin
out<=sel?in1:in0;
end
endmodule
|
/*
-- ============================================================================
-- FILE NAME : gpio.v
-- DESCRIPTION : General Purpose I/O
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito VKì¬
-- ============================================================================
*/
/********** ¤Êwb_t@C **********/
`include "nettype.h"
`include "stddef.h"
`include "global_config.h"
/********** ÂÊwb_t@C **********/
`include "gpio.h"
/********** W
[ **********/
module gpio (
/********** NbN & Zbg **********/
input wire clk, // NbN
input wire reset, // Zbg
/********** oXC^tF[X **********/
input wire cs_, // `bvZNg
input wire as_, // AhXXg[u
input wire rw, // Read / Write
input wire [`GpioAddrBus] addr, // AhX
input wire [`WordDataBus] wr_data, // «Ýf[^
output reg [`WordDataBus] rd_data, // ÇÝoµf[^
output reg rdy_ // fB
/********** ÄpüoÍ|[g **********/
`ifdef GPIO_IN_CH // üÍ|[gÌÀ
, input wire [`GPIO_IN_CH-1:0] gpio_in // üÍ|[gi§äWX^0j
`endif
`ifdef GPIO_OUT_CH // oÍ|[gÌÀ
, output reg [`GPIO_OUT_CH-1:0] gpio_out // oÍ|[gi§äWX^1j
`endif
`ifdef GPIO_IO_CH // üoÍ|[gÌÀ
, inout wire [`GPIO_IO_CH-1:0] gpio_io // üoÍ|[gi§äWX^2j
`endif
);
`ifdef GPIO_IO_CH // üoÍ|[ģä
/********** üoÍM **********/
wire [`GPIO_IO_CH-1:0] io_in; // üÍf[^
reg [`GPIO_IO_CH-1:0] io_out; // oÍf[^
reg [`GPIO_IO_CH-1:0] io_dir; // üoÍûüi§äWX^3j
reg [`GPIO_IO_CH-1:0] io; // üoÍ
integer i; // Ce[^
/********** üoÍMÌp±ãü **********/
assign io_in = gpio_io; // üÍf[^
assign gpio_io = io; // üoÍ
/********** üoÍûü̧ä **********/
always @(*) begin
for (i = 0; i < `GPIO_IO_CH; i = i + 1) begin : IO_DIR
io[i] = (io_dir[i] == `GPIO_DIR_IN) ? 1'bz : io_out[i];
end
end
`endif
/********** GPIO̧ä **********/
always @(posedge clk or `RESET_EDGE reset) begin
if (reset == `RESET_ENABLE) begin
/* ñ¯úZbg */
rd_data <= #1 `WORD_DATA_W'h0;
rdy_ <= #1 `DISABLE_;
`ifdef GPIO_OUT_CH // oÍ|[gÌZbg
gpio_out <= #1 {`GPIO_OUT_CH{`LOW}};
`endif
`ifdef GPIO_IO_CH // üoÍ|[gÌZbg
io_out <= #1 {`GPIO_IO_CH{`LOW}};
io_dir <= #1 {`GPIO_IO_CH{`GPIO_DIR_IN}};
`endif
end else begin
/* fB̶¬ */
if ((cs_ == `ENABLE_) && (as_ == `ENABLE_)) begin
rdy_ <= #1 `ENABLE_;
end else begin
rdy_ <= #1 `DISABLE_;
end
/* ÇÝoµANZX */
if ((cs_ == `ENABLE_) && (as_ == `ENABLE_) && (rw == `READ)) begin
case (addr)
`ifdef GPIO_IN_CH // üÍ|[gÌÇÝoµ
`GPIO_ADDR_IN_DATA : begin // §äWX^ 0
rd_data <= #1 {{`WORD_DATA_W-`GPIO_IN_CH{1'b0}},
gpio_in};
end
`endif
`ifdef GPIO_OUT_CH // oÍ|[gÌÇÝoµ
`GPIO_ADDR_OUT_DATA : begin // §äWX^ 1
rd_data <= #1 {{`WORD_DATA_W-`GPIO_OUT_CH{1'b0}},
gpio_out};
end
`endif
`ifdef GPIO_IO_CH // üoÍ|[gÌÇÝoµ
`GPIO_ADDR_IO_DATA : begin // §äWX^ 2
rd_data <= #1 {{`WORD_DATA_W-`GPIO_IO_CH{1'b0}},
io_in};
end
`GPIO_ADDR_IO_DIR : begin // §äWX^ 3
rd_data <= #1 {{`WORD_DATA_W-`GPIO_IO_CH{1'b0}},
io_dir};
end
`endif
endcase
end else begin
rd_data <= #1 `WORD_DATA_W'h0;
end
/* «ÝANZX */
if ((cs_ == `ENABLE_) && (as_ == `ENABLE_) && (rw == `WRITE)) begin
case (addr)
`ifdef GPIO_OUT_CH // oÍ|[gÖÌ«±Ý
`GPIO_ADDR_OUT_DATA : begin // §äWX^ 1
gpio_out <= #1 wr_data[`GPIO_OUT_CH-1:0];
end
`endif
`ifdef GPIO_IO_CH // üoÍ|[gÖÌ«±Ý
`GPIO_ADDR_IO_DATA : begin // §äWX^ 2
io_out <= #1 wr_data[`GPIO_IO_CH-1:0];
end
`GPIO_ADDR_IO_DIR : begin // §äWX^ 3
io_dir <= #1 wr_data[`GPIO_IO_CH-1:0];
end
`endif
endcase
end
end
end
endmodule
|
`ifndef __XC3S_RAM16X233_D_V__
`define __XC3S_RAM16X233_D_V__
//`include "RAM16X1D.v"
module XC3S_RAM16X233_D (DIN, ADDR1, ADDR2, WE, WCLK, O_DOUT1, O_DOUT2);
parameter data_width = 233;//Replace with desired data-bus width
input wire [232:0]DIN;
input wire [3:0] ADDR1, ADDR2;
input wire WE;
input wire WCLK;
output wire [232:0]O_DOUT1, O_DOUT2;
wire [232:0]DOUT1, DOUT2;
/*Remember to Instantiate a Distributed SelectRAM block for each Data port
and to give each instance a unique name...The following is an example of instantiation
for a 16 X 8-bit RAM. */
RAM16X1D U_RAM16X1D_0(DOUT2[0], DOUT1[0], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[0], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_1(DOUT2[1], DOUT1[1], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[1], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_2(DOUT2[2], DOUT1[2], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[2], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_3(DOUT2[3], DOUT1[3], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[3], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_4(DOUT2[4], DOUT1[4], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[4], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_5(DOUT2[5], DOUT1[5], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[5], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_6(DOUT2[6], DOUT1[6], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[6], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_7(DOUT2[7], DOUT1[7], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[7], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_8(DOUT2[8], DOUT1[8], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[8], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_9(DOUT2[9], DOUT1[9], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[9], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_10(DOUT2[10], DOUT1[10], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[10], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_11(DOUT2[11], DOUT1[11], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[11], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_12(DOUT2[12], DOUT1[12], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[12], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_13(DOUT2[13], DOUT1[13], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[13], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_14(DOUT2[14], DOUT1[14], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[14], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_15(DOUT2[15], DOUT1[15], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[15], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_16(DOUT2[16], DOUT1[16], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[16], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_17(DOUT2[17], DOUT1[17], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[17], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_18(DOUT2[18], DOUT1[18], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[18], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_19(DOUT2[19], DOUT1[19], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[19], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_20(DOUT2[20], DOUT1[20], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[20], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_21(DOUT2[21], DOUT1[21], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[21], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_22(DOUT2[22], DOUT1[22], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[22], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_23(DOUT2[23], DOUT1[23], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[23], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_24(DOUT2[24], DOUT1[24], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[24], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_25(DOUT2[25], DOUT1[25], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[25], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_26(DOUT2[26], DOUT1[26], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[26], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_27(DOUT2[27], DOUT1[27], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[27], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_28(DOUT2[28], DOUT1[28], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[28], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_29(DOUT2[29], DOUT1[29], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[29], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_30(DOUT2[30], DOUT1[30], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[30], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_31(DOUT2[31], DOUT1[31], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[31], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_32(DOUT2[32], DOUT1[32], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[32], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_33(DOUT2[33], DOUT1[33], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[33], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_34(DOUT2[34], DOUT1[34], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[34], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_35(DOUT2[35], DOUT1[35], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[35], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_36(DOUT2[36], DOUT1[36], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[36], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_37(DOUT2[37], DOUT1[37], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[37], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_38(DOUT2[38], DOUT1[38], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[38], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_39(DOUT2[39], DOUT1[39], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[39], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_40(DOUT2[40], DOUT1[40], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[40], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_41(DOUT2[41], DOUT1[41], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[41], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_42(DOUT2[42], DOUT1[42], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[42], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_43(DOUT2[43], DOUT1[43], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[43], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_44(DOUT2[44], DOUT1[44], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[44], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_45(DOUT2[45], DOUT1[45], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[45], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_46(DOUT2[46], DOUT1[46], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[46], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_47(DOUT2[47], DOUT1[47], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[47], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_48(DOUT2[48], DOUT1[48], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[48], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_49(DOUT2[49], DOUT1[49], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[49], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_50(DOUT2[50], DOUT1[50], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[50], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_51(DOUT2[51], DOUT1[51], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[51], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_52(DOUT2[52], DOUT1[52], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[52], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_53(DOUT2[53], DOUT1[53], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[53], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_54(DOUT2[54], DOUT1[54], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[54], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_55(DOUT2[55], DOUT1[55], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[55], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_56(DOUT2[56], DOUT1[56], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[56], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_57(DOUT2[57], DOUT1[57], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[57], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_58(DOUT2[58], DOUT1[58], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[58], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_59(DOUT2[59], DOUT1[59], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[59], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_60(DOUT2[60], DOUT1[60], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[60], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_61(DOUT2[61], DOUT1[61], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[61], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_62(DOUT2[62], DOUT1[62], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[62], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_63(DOUT2[63], DOUT1[63], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[63], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_64(DOUT2[64], DOUT1[64], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[64], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_65(DOUT2[65], DOUT1[65], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[65], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_66(DOUT2[66], DOUT1[66], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[66], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_67(DOUT2[67], DOUT1[67], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[67], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_68(DOUT2[68], DOUT1[68], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[68], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_69(DOUT2[69], DOUT1[69], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[69], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_70(DOUT2[70], DOUT1[70], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[70], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_71(DOUT2[71], DOUT1[71], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[71], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_72(DOUT2[72], DOUT1[72], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[72], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_73(DOUT2[73], DOUT1[73], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[73], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_74(DOUT2[74], DOUT1[74], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[74], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_75(DOUT2[75], DOUT1[75], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[75], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_76(DOUT2[76], DOUT1[76], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[76], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_77(DOUT2[77], DOUT1[77], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[77], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_78(DOUT2[78], DOUT1[78], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[78], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_79(DOUT2[79], DOUT1[79], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[79], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_80(DOUT2[80], DOUT1[80], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[80], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_81(DOUT2[81], DOUT1[81], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[81], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_82(DOUT2[82], DOUT1[82], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[82], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_83(DOUT2[83], DOUT1[83], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[83], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_84(DOUT2[84], DOUT1[84], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[84], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_85(DOUT2[85], DOUT1[85], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[85], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_86(DOUT2[86], DOUT1[86], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[86], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_87(DOUT2[87], DOUT1[87], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[87], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_88(DOUT2[88], DOUT1[88], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[88], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_89(DOUT2[89], DOUT1[89], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[89], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_90(DOUT2[90], DOUT1[90], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[90], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_91(DOUT2[91], DOUT1[91], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[91], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_92(DOUT2[92], DOUT1[92], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[92], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_93(DOUT2[93], DOUT1[93], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[93], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_94(DOUT2[94], DOUT1[94], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[94], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_95(DOUT2[95], DOUT1[95], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[95], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_96(DOUT2[96], DOUT1[96], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[96], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_97(DOUT2[97], DOUT1[97], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[97], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_98(DOUT2[98], DOUT1[98], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[98], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_99(DOUT2[99], DOUT1[99], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[99], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_100(DOUT2[100], DOUT1[100], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[100], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_101(DOUT2[101], DOUT1[101], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[101], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_102(DOUT2[102], DOUT1[102], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[102], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_103(DOUT2[103], DOUT1[103], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[103], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_104(DOUT2[104], DOUT1[104], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[104], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_105(DOUT2[105], DOUT1[105], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[105], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_106(DOUT2[106], DOUT1[106], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[106], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_107(DOUT2[107], DOUT1[107], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[107], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_108(DOUT2[108], DOUT1[108], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[108], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_109(DOUT2[109], DOUT1[109], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[109], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_110(DOUT2[110], DOUT1[110], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[110], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_111(DOUT2[111], DOUT1[111], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[111], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_112(DOUT2[112], DOUT1[112], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[112], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_113(DOUT2[113], DOUT1[113], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[113], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_114(DOUT2[114], DOUT1[114], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[114], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_115(DOUT2[115], DOUT1[115], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[115], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_116(DOUT2[116], DOUT1[116], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[116], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_117(DOUT2[117], DOUT1[117], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[117], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_118(DOUT2[118], DOUT1[118], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[118], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_119(DOUT2[119], DOUT1[119], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[119], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_120(DOUT2[120], DOUT1[120], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[120], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_121(DOUT2[121], DOUT1[121], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[121], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_122(DOUT2[122], DOUT1[122], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[122], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_123(DOUT2[123], DOUT1[123], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[123], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_124(DOUT2[124], DOUT1[124], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[124], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_125(DOUT2[125], DOUT1[125], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[125], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_126(DOUT2[126], DOUT1[126], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[126], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_127(DOUT2[127], DOUT1[127], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[127], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_128(DOUT2[128], DOUT1[128], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[128], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_129(DOUT2[129], DOUT1[129], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[129], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_130(DOUT2[130], DOUT1[130], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[130], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_131(DOUT2[131], DOUT1[131], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[131], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_132(DOUT2[132], DOUT1[132], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[132], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_133(DOUT2[133], DOUT1[133], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[133], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_134(DOUT2[134], DOUT1[134], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[134], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_135(DOUT2[135], DOUT1[135], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[135], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_136(DOUT2[136], DOUT1[136], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[136], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_137(DOUT2[137], DOUT1[137], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[137], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_138(DOUT2[138], DOUT1[138], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[138], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_139(DOUT2[139], DOUT1[139], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[139], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_140(DOUT2[140], DOUT1[140], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[140], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_141(DOUT2[141], DOUT1[141], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[141], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_142(DOUT2[142], DOUT1[142], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[142], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_143(DOUT2[143], DOUT1[143], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[143], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_144(DOUT2[144], DOUT1[144], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[144], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_145(DOUT2[145], DOUT1[145], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[145], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_146(DOUT2[146], DOUT1[146], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[146], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_147(DOUT2[147], DOUT1[147], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[147], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_148(DOUT2[148], DOUT1[148], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[148], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_149(DOUT2[149], DOUT1[149], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[149], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_150(DOUT2[150], DOUT1[150], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[150], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_151(DOUT2[151], DOUT1[151], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[151], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_152(DOUT2[152], DOUT1[152], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[152], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_153(DOUT2[153], DOUT1[153], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[153], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_154(DOUT2[154], DOUT1[154], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[154], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_155(DOUT2[155], DOUT1[155], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[155], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_156(DOUT2[156], DOUT1[156], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[156], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_157(DOUT2[157], DOUT1[157], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[157], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_158(DOUT2[158], DOUT1[158], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[158], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_159(DOUT2[159], DOUT1[159], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[159], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_160(DOUT2[160], DOUT1[160], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[160], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_161(DOUT2[161], DOUT1[161], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[161], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_162(DOUT2[162], DOUT1[162], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[162], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_163(DOUT2[163], DOUT1[163], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[163], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_164(DOUT2[164], DOUT1[164], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[164], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_165(DOUT2[165], DOUT1[165], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[165], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_166(DOUT2[166], DOUT1[166], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[166], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_167(DOUT2[167], DOUT1[167], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[167], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_168(DOUT2[168], DOUT1[168], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[168], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_169(DOUT2[169], DOUT1[169], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[169], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_170(DOUT2[170], DOUT1[170], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[170], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_171(DOUT2[171], DOUT1[171], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[171], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_172(DOUT2[172], DOUT1[172], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[172], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_173(DOUT2[173], DOUT1[173], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[173], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_174(DOUT2[174], DOUT1[174], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[174], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_175(DOUT2[175], DOUT1[175], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[175], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_176(DOUT2[176], DOUT1[176], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[176], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_177(DOUT2[177], DOUT1[177], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[177], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_178(DOUT2[178], DOUT1[178], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[178], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_179(DOUT2[179], DOUT1[179], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[179], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_180(DOUT2[180], DOUT1[180], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[180], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_181(DOUT2[181], DOUT1[181], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[181], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_182(DOUT2[182], DOUT1[182], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[182], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_183(DOUT2[183], DOUT1[183], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[183], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_184(DOUT2[184], DOUT1[184], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[184], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_185(DOUT2[185], DOUT1[185], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[185], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_186(DOUT2[186], DOUT1[186], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[186], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_187(DOUT2[187], DOUT1[187], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[187], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_188(DOUT2[188], DOUT1[188], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[188], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_189(DOUT2[189], DOUT1[189], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[189], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_190(DOUT2[190], DOUT1[190], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[190], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_191(DOUT2[191], DOUT1[191], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[191], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_192(DOUT2[192], DOUT1[192], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[192], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_193(DOUT2[193], DOUT1[193], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[193], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_194(DOUT2[194], DOUT1[194], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[194], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_195(DOUT2[195], DOUT1[195], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[195], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_196(DOUT2[196], DOUT1[196], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[196], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_197(DOUT2[197], DOUT1[197], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[197], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_198(DOUT2[198], DOUT1[198], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[198], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_199(DOUT2[199], DOUT1[199], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[199], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_200(DOUT2[200], DOUT1[200], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[200], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_201(DOUT2[201], DOUT1[201], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[201], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_202(DOUT2[202], DOUT1[202], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[202], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_203(DOUT2[203], DOUT1[203], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[203], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_204(DOUT2[204], DOUT1[204], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[204], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_205(DOUT2[205], DOUT1[205], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[205], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_206(DOUT2[206], DOUT1[206], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[206], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_207(DOUT2[207], DOUT1[207], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[207], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_208(DOUT2[208], DOUT1[208], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[208], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_209(DOUT2[209], DOUT1[209], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[209], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_210(DOUT2[210], DOUT1[210], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[210], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_211(DOUT2[211], DOUT1[211], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[211], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_212(DOUT2[212], DOUT1[212], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[212], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_213(DOUT2[213], DOUT1[213], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[213], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_214(DOUT2[214], DOUT1[214], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[214], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_215(DOUT2[215], DOUT1[215], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[215], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_216(DOUT2[216], DOUT1[216], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[216], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_217(DOUT2[217], DOUT1[217], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[217], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_218(DOUT2[218], DOUT1[218], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[218], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_219(DOUT2[219], DOUT1[219], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[219], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_220(DOUT2[220], DOUT1[220], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[220], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_221(DOUT2[221], DOUT1[221], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[221], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_222(DOUT2[222], DOUT1[222], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[222], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_223(DOUT2[223], DOUT1[223], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[223], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_224(DOUT2[224], DOUT1[224], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[224], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_225(DOUT2[225], DOUT1[225], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[225], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_226(DOUT2[226], DOUT1[226], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[226], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_227(DOUT2[227], DOUT1[227], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[227], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_228(DOUT2[228], DOUT1[228], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[228], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_229(DOUT2[229], DOUT1[229], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[229], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_230(DOUT2[230], DOUT1[230], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[230], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_231(DOUT2[231], DOUT1[231], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[231], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
RAM16X1D U_RAM16X1D_232(DOUT2[232], DOUT1[232], ADDR1[0], ADDR1[1], ADDR1[2], ADDR1[3], DIN[232], ADDR2[0], ADDR2[1], ADDR2[2], ADDR2[3], WCLK, WE);
//always @(posedge WCLK)
//begin
assign O_DOUT1 = DOUT1;
assign O_DOUT2 = DOUT2;
//end
endmodule
`endif
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21BO_FUNCTIONAL_V
`define SKY130_FD_SC_HD__A21BO_FUNCTIONAL_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__a21bo (
X ,
A1 ,
A2 ,
B1_N
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1_N;
// Local signals
wire nand0_out ;
wire nand1_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out_X, B1_N, nand0_out);
buf buf0 (X , nand1_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21BO_FUNCTIONAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Case Western Reserve University
// Engineer: Matt McConnell
//
// Create Date: 22:29:00 09/09/2017
// Project Name: EECS301 Digital Design
// Design Name: Lab #4 Project
// Module Name: TF_BCD_Segment_Decoder
// Target Devices: Altera Cyclone V
// Tool versions: Quartus v17.0
// Description: BCD to Seven Segment Decoder Test Bench
//
// Dependencies:
//
//////////////////////////////////////////////////////////////////////////////////
module TF_BCD_Segment_Decoder();
//
// System Clock Emulation
//
localparam CLK_RATE_HZ = 500000000; // 500 MHz
localparam CLK_HALF_PER = ((1.0 / CLK_RATE_HZ) * 1000000000.0) / 2.0; // ns
reg CLK;
initial
begin
CLK = 1'b0;
forever #(CLK_HALF_PER) CLK = ~CLK;
end
//
// Unit Under Test: BCD_Segment_Decoder
//
localparam BCD_DIGITS = 5;
localparam BCD_WIDTH = 4; // 4-bits per digit
localparam SEG_WIDTH = 7; // 7-bits per segment
reg [BCD_WIDTH-1:0] bcd_reg_0;
reg [BCD_WIDTH-1:0] bcd_reg_1;
reg [BCD_WIDTH-1:0] bcd_reg_2;
reg [BCD_WIDTH-1:0] bcd_reg_3;
reg [BCD_WIDTH-1:0] bcd_reg_4;
wire [SEG_WIDTH-1:0] seg_out_0;
wire [SEG_WIDTH-1:0] seg_out_1;
wire [SEG_WIDTH-1:0] seg_out_2;
wire [SEG_WIDTH-1:0] seg_out_3;
wire [SEG_WIDTH-1:0] seg_out_4;
BCD_Segment_Decoder
#(
.BCD_DIGITS( BCD_DIGITS )
)
uut
(
// BCD Input (Packed Array)
.BCD_IN( { bcd_reg_4, bcd_reg_3, bcd_reg_2, bcd_reg_1, bcd_reg_0 } ),
// Seven-Segment Output (Packed Array)
.SEG_OUT( { seg_out_4, seg_out_3, seg_out_2, seg_out_1, seg_out_0 } ),
// System Signals
.CLK( CLK )
);
//
// Expected Segment Output Patterns
//
wire [6:0] Expected_Segment_Output [15:0];
assign Expected_Segment_Output[ 0] = 7'b0111111; // 0
assign Expected_Segment_Output[ 1] = 7'b0000110; // 1
assign Expected_Segment_Output[ 2] = 7'b1011011; // 2
assign Expected_Segment_Output[ 3] = 7'b1001111; // 3
assign Expected_Segment_Output[ 4] = 7'b1100110; // 4
assign Expected_Segment_Output[ 5] = 7'b1101101; // 5
assign Expected_Segment_Output[ 6] = 7'b1111101; // 6
assign Expected_Segment_Output[ 7] = 7'b0000111; // 7
assign Expected_Segment_Output[ 8] = 7'b1111111; // 8
assign Expected_Segment_Output[ 9] = 7'b1100111; // 9
assign Expected_Segment_Output[10] = 7'b0000000; // Blank
assign Expected_Segment_Output[11] = 7'b0000000; // Blank
assign Expected_Segment_Output[12] = 7'b0000000; // Blank
assign Expected_Segment_Output[13] = 7'b0000000; // Blank
assign Expected_Segment_Output[14] = 7'b0000000; // Blank
assign Expected_Segment_Output[15] = 7'b0000000; // Blank
//
// Testing Procedure
//
integer test_digit_0;
integer test_digit_1;
integer test_digit_2;
integer test_digit_3;
integer test_digit_4;
reg [4:0] test_output_errors;
integer total_errors;
initial
begin
// Initialize signals
bcd_reg_0 = {BCD_WIDTH{1'b0}};
bcd_reg_1 = {BCD_WIDTH{1'b0}};
bcd_reg_2 = {BCD_WIDTH{1'b0}};
bcd_reg_3 = {BCD_WIDTH{1'b0}};
bcd_reg_4 = {BCD_WIDTH{1'b0}};
test_digit_0 = 0;
test_digit_1 = 0;
test_digit_2 = 0;
test_digit_3 = 0;
test_digit_4 = 0;
test_output_errors = 5'b00000;
total_errors = 0;
// Wait for system to stabilize
#500;
//
// Generate full coverage test vectors for every possible input combination
//
for (test_digit_4 = 0; test_digit_4 < 16; test_digit_4 = test_digit_4 + 1)
begin
for (test_digit_3 = 0; test_digit_3 < 16; test_digit_3 = test_digit_3 + 1)
begin
for (test_digit_2 = 0; test_digit_2 < 16; test_digit_2 = test_digit_2 + 1)
begin
for (test_digit_1 = 0; test_digit_1 < 16; test_digit_1 = test_digit_1 + 1)
begin
for (test_digit_0 = 0; test_digit_0 < 16; test_digit_0 = test_digit_0 + 1)
begin
// Set the BCD Input Values on the Rising Clock Edge
@(posedge CLK);
bcd_reg_0 = test_digit_0[3:0];
bcd_reg_1 = test_digit_1[3:0];
bcd_reg_2 = test_digit_2[3:0];
bcd_reg_3 = test_digit_3[3:0];
bcd_reg_4 = test_digit_4[3:0];
// Wait a clock cycle for the inputs to be registered
@(posedge CLK);
// Wait another clock cycle for the outputs to update
@(posedge CLK);
// Check the output results
test_output_errors[0] = (seg_out_0 != Expected_Segment_Output[test_digit_0]) ? 1'b1 : 1'b0;
test_output_errors[1] = (seg_out_1 != Expected_Segment_Output[test_digit_1]) ? 1'b1 : 1'b0;
test_output_errors[2] = (seg_out_2 != Expected_Segment_Output[test_digit_2]) ? 1'b1 : 1'b0;
test_output_errors[3] = (seg_out_3 != Expected_Segment_Output[test_digit_3]) ? 1'b1 : 1'b0;
test_output_errors[4] = (seg_out_4 != Expected_Segment_Output[test_digit_4]) ? 1'b1 : 1'b0;
// Output Testing Message
$display("Test: %02d %02d %02d %02d %02d : %s %s %s %s %s : %s ",
bcd_reg_4, bcd_reg_3, bcd_reg_2, bcd_reg_1, bcd_reg_0,
test_output_errors[4] ? "X" : ".",
test_output_errors[3] ? "X" : ".",
test_output_errors[2] ? "X" : ".",
test_output_errors[1] ? "X" : ".",
test_output_errors[0] ? "X" : ".",
|test_output_errors ? "FAILURE!!!" : "Pass "
);
// Increment the Total Errors count if there was an error
if (|test_output_errors)
total_errors = total_errors + 1;
end
end
end
end
end
$display("Testing Complete: %d Total Errors", total_errors);
end
endmodule
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: sprite_ram_2Kx16.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.1 Build 243 01/31/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sprite_ram_2Kx16 (
address_a,
address_b,
byteena_a,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [10:0] address_a;
input [7:0] address_b;
input [1:0] byteena_a;
input clock_a;
input clock_b;
input [15:0] data_a;
input [127:0] data_b;
input wren_a;
input wren_b;
output [15:0] q_a;
output [127:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [1:0] byteena_a;
tri1 clock_a;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [127:0] sub_wire1;
wire [15:0] q_a = sub_wire0[15:0];
wire [127:0] q_b = sub_wire1[127:0];
altsyncram altsyncram_component (
.byteena_a (byteena_a),
.clock0 (clock_a),
.wren_a (wren_a),
.address_b (address_b),
.clock1 (clock_b),
.data_b (data_b),
.wren_b (wren_b),
.address_a (address_a),
.data_a (data_a),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK1",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2048,
altsyncram_component.numwords_b = 256,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 11,
altsyncram_component.widthad_b = 8,
altsyncram_component.width_a = 16,
altsyncram_component.width_b = 128,
altsyncram_component.width_byteena_a = 2,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "5"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "32768"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "128"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "128"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "128"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: USED_PORT: address_a 0 0 11 0 INPUT NODEFVAL "address_a[10..0]"
// Retrieval info: USED_PORT: address_b 0 0 8 0 INPUT NODEFVAL "address_b[7..0]"
// Retrieval info: USED_PORT: byteena_a 0 0 2 0 INPUT VCC "byteena_a[1..0]"
// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
// Retrieval info: USED_PORT: data_a 0 0 16 0 INPUT NODEFVAL "data_a[15..0]"
// Retrieval info: USED_PORT: data_b 0 0 128 0 INPUT NODEFVAL "data_b[127..0]"
// Retrieval info: USED_PORT: q_a 0 0 16 0 OUTPUT NODEFVAL "q_a[15..0]"
// Retrieval info: USED_PORT: q_b 0 0 128 0 OUTPUT NODEFVAL "q_b[127..0]"
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
// Retrieval info: CONNECT: @address_a 0 0 11 0 address_a 0 0 11 0
// Retrieval info: CONNECT: @address_b 0 0 8 0 address_b 0 0 8 0
// Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena_a 0 0 2 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 data_a 0 0 16 0
// Retrieval info: CONNECT: @data_b 0 0 128 0 data_b 0 0 128 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: CONNECT: q_b 0 0 128 0 @q_b 0 0 128 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sprite_ram_2Kx16.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sprite_ram_2Kx16.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sprite_ram_2Kx16.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sprite_ram_2Kx16.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sprite_ram_2Kx16_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sprite_ram_2Kx16_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLXBN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__DLXBN_BEHAVIORAL_PP_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_hd__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dlxbn (
Q ,
Q_N ,
D ,
GATE_N,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire GATE ;
wire buf_Q ;
wire GATE_N_delayed;
wire D_delayed ;
reg notifier ;
wire awake ;
wire 1 ;
// Name Output Other arguments
not not0 (GATE , GATE_N_delayed );
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE, notifier, VPWR, VGND);
assign awake = ( VPWR === 1 );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLXBN_BEHAVIORAL_PP_V |
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
//`include "mono_data_rx/mono_data_rx_core.v"
module mono_data_rx
#(
parameter BASEADDR = 16'h0000,
parameter HIGHADDR = 16'h0000,
parameter ABUSWIDTH = 16,
parameter IDENTYFIER = 2'b00
)(
input wire BUS_CLK,
input wire [ABUSWIDTH-1:0] BUS_ADD,
inout wire [7:0] BUS_DATA,
input wire BUS_RST,
input wire BUS_WR,
input wire BUS_RD,
input wire [63:0] TIMESTAMP,
input wire CLK_BX,
input wire RX_TOKEN, RX_DATA, RX_CLK,
output wire RX_READ, RX_FREEZE,
input wire FIFO_READ,
output wire FIFO_EMPTY,
output wire [31:0] FIFO_DATA,
output wire LOST_ERROR
);
wire IP_RD, IP_WR;
wire [ABUSWIDTH-1:0] IP_ADD;
wire [7:0] IP_DATA_IN;
wire [7:0] IP_DATA_OUT;
bus_to_ip #( .BASEADDR(BASEADDR), .HIGHADDR(HIGHADDR), .ABUSWIDTH(ABUSWIDTH) ) i_bus_to_ip
(
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.IP_RD(IP_RD),
.IP_WR(IP_WR),
.IP_ADD(IP_ADD),
.IP_DATA_IN(IP_DATA_IN),
.IP_DATA_OUT(IP_DATA_OUT)
);
mono_data_rx_core
#(
.ABUSWIDTH(ABUSWIDTH),
.IDENTYFIER(IDENTYFIER)
) mono_data_rx_core
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(IP_ADD),
.BUS_DATA_IN(IP_DATA_IN),
.BUS_RD(IP_RD),
.BUS_WR(IP_WR),
.BUS_DATA_OUT(IP_DATA_OUT),
.CLK_BX(CLK_BX),
.RX_TOKEN(RX_TOKEN),
.RX_DATA(RX_DATA),
.RX_CLK(RX_CLK),
.RX_READ(RX_READ),
.RX_FREEZE(RX_FREEZE),
.TIMESTAMP(TIMESTAMP),
.FIFO_READ(FIFO_READ),
.FIFO_EMPTY(FIFO_EMPTY),
.FIFO_DATA(FIFO_DATA),
.LOST_ERROR(LOST_ERROR)
);
endmodule
|
// soft_tbm.v
`timescale 1 ns / 1 ps
module soft_tbm
(
input clk,
input sync,
input reset,
input [4:0]trg_in_tbm,
input [4:0]trg_in_ctr,
input [3:0]trg_pos,
output tin,
input tout,
output deser_ena,
output ctr,
output daq_write,
output reg [15:0]daq_data,
input [15:0]token_timeout,
input enable_tout_delay
);
wire ro_enable; // a readout can be started
wire trg_pass; // trigger sent to ROC/TBM
wire queue_read;
wire queue_clear;
wire queue_clear_token;
wire queue_empty;
wire queue_full;
wire [3:0]queue_size;
wire queue_tok;
wire [7:0]queue_trigger_counter;
wire [3:0]queue_trg_pos;
wire [5:0]queue_flags;
wire tout_int;
wire tout_missing;
wire syn; // sync event
wire trg; // trigger event
wire rsr; // ROC reset event
wire rst; // TBM reset event
wire cal; // calibrate
reg set_rsr;
wire rsr_int = rsr || set_rsr;
assign queue_clear = rst;
assign queue_clear_token = rsr_int;
assign trg_pass = trg && !queue_full;
// === tout delay for ADC ===========================================
reg [15:0]tout_delay;
always @(posedge clk or posedge reset)
begin
if (reset) tout_delay <= 0;
else if (sync) tout_delay <= {tout_delay[14:0], tout};
end
assign tout_int = enable_tout_delay ? tout_delay[15] : tout;
// === receive and decode events ====================================
assign syn = trg_in_tbm[0];
assign trg = trg_in_tbm[1];
assign rsr = trg_in_tbm[2];
assign rst = trg_in_tbm[3];
assign cal = trg_in_tbm[4];
wire trg_dir = trg_in_ctr[1];
wire rsr_dir = trg_in_ctr[2];
wire rst_dir = trg_in_ctr[3];
wire cal_dir = trg_in_ctr[4];
/* commands
* cal
send cal to ROC
set(flag_cal)
* syn
clear(trigger_counter)
set(flag_sync)
* rsr
queue_clear_token
reset ROC
set flag_resr
if (read_in_progress)
{
stop running readout
add trailer
}
* rst
queue_clear
reset ROC
set flag_resr
set flag_rest
if (read_in_progress)
{
stop running readout
}
* trg
queue_write
if (!queue_full)
{
send ROC trigger
}
else set flag_stkf
*/
// === Send Event to ROC/MODULE (CTR Generator) =====================
ctr_encoder ctr_enc
(
.clk(clk),
.sync(sync),
.reset(reset),
.cal(cal || cal_dir),
.trg(trg_pass || trg_dir),
.res_roc(rsr_int || rst || rsr_dir),
.res_tbm(rst || rst_dir),
.res_req(1'b0),
.nmr_req(1'b0),
.trg_veto(1'b0),
.res_veto(1'b0),
.running(),
.ctr_out(ctr),
.trg_out(),
.res_out()
);
// === Flags ========================================================
reg flag_rest; // TBM reset occured
reg flag_resr; // ROC reset occured
reg flag_cal; // calibrate received
reg flag_sync; // sync signal received
reg flag_stkf; // stack full
reg flag_ares; // auto reset sent
reg flag_pkam; // PKAM reset (not queued)
wire [5:0]flags = {flag_ares, flag_stkf, flag_sync, flag_cal, flag_resr, flag_rest};
always @(posedge clk or posedge reset)
begin
if (reset)
begin
flag_cal <= 0;
flag_sync <= 0;
flag_resr <= 0;
flag_rest <= 0;
flag_stkf <= 0;
flag_ares <= 0;
// flag_pkam <= 0;
end
else if (sync)
begin
if (trg_pass)
begin
flag_cal <= 0;
flag_sync <= 0;
flag_resr <= 0;
flag_rest <= 0;
flag_stkf <= 0;
flag_ares <= 0;
// flag_pkam <= 0;
end
else
if (cal) flag_cal <= 1;
if (syn) flag_sync <= 1;
if (rsr_int || rst) flag_resr <= 1;
if (rst) flag_rest <= 1;
if (trg && queue_full) flag_stkf <= 1;
end
end
// === Trigger Counter ==============================================
reg [7:0]trigger_counter;
always @(posedge clk or posedge reset) begin
if (reset) trigger_counter <= 0;
else if (sync) begin
if (syn) trigger_counter <= 0;
else if (trg_pass) trigger_counter <= trigger_counter + 8'd1;
end
end
// === enables start of a new readout id data in trigger stack
// first readout after buffer empty must be delayed
reg [4:0]ro_delay;
wire ro_veto = !ro_delay[4];
always @(posedge clk or posedge reset) begin
if (reset) begin
ro_delay <= 5'd0;
end
else if (sync) begin
if (trg_pass && (queue_size <= 1)) ro_delay = 5'd10;
else if (ro_veto) ro_delay = ro_delay - 5'd1;
end
end
assign ro_enable = !queue_empty && !ro_veto;
// === header/trailer generator =====================================
/*
** header format **
A | 0 | ev7 ev6 ev5 ev4 ev3 ev2 ev1 ev0
8 | 0 | 0 0 0 0 pos3 pos2 pos1 pos0
** trailer format **
E | 0 | ntok rest resr 0 sync clt cal stkf
C | 0 | ares pkam 0 0 stk3 stk2 stk1 stk0
*/
reg [16:0]token_timeout_counter;
assign tout_missing = token_timeout_counter[16];
reg [5:0]sm_readout;
localparam SM_IDLE = 6'b00_0000;
localparam SM_HDR1 = 6'b00_0010;
localparam SM_HDR2 = 6'b01_0010;
localparam SM_TOUT = 6'b00_1100;
localparam SM_WAIT = 6'b00_1000;
localparam SM_PCAM1 = 6'b01_1000;
localparam SM_PCAM2 = 6'b01_0000;
localparam SM_TRL0 = 6'b11_1000;
localparam SM_TRL1 = 6'b10_0010;
localparam SM_TRL2 = 6'b00_0011;
localparam SM_TRL3 = 6'b10_0000;
assign queue_read = sm_readout[0];
assign daq_write = sm_readout[1] && sync;
assign tin = sm_readout[2];
assign deser_ena = sm_readout[3];
// trailer delay counter
reg [2:0]trldel;
wire trl_start = trldel[2];
always @(posedge clk or posedge reset)
begin
if (reset) trldel <= 0;
else if (sync)
begin
if (~&sm_readout[5:4]) trldel <= 0;
else if (!trl_start) trldel <= trldel + 3'd1;
end
end
always @(posedge clk or posedge reset)
begin
if (reset)
begin
sm_readout <= SM_IDLE;
token_timeout_counter <= 0;
set_rsr <= 0;
flag_pkam <= 0;
end
else if (sync)
begin
case (sm_readout)
SM_IDLE:
if (ro_enable) sm_readout <= SM_HDR1;
SM_HDR1:
sm_readout <= SM_HDR2;
SM_HDR2:
sm_readout <= queue_tok ? SM_TOUT : SM_TRL1;
SM_TOUT:
begin
token_timeout_counter <= {1'b0, token_timeout};
sm_readout <= SM_WAIT;
end
SM_WAIT:
begin
token_timeout_counter <= token_timeout_counter - 17'd1;
if (tout_missing) sm_readout <= SM_PCAM1;
else if (tout_int || flag_resr) sm_readout <= SM_TRL0;
end
SM_PCAM1:
begin
flag_pkam <= 1;
set_rsr <= 1;
sm_readout <= SM_PCAM2;
end
SM_PCAM2:
begin
set_rsr <= 0;
sm_readout <= SM_TRL0;
end
SM_TRL0:
if (trl_start) sm_readout <= SM_TRL1;
SM_TRL1:
sm_readout <= SM_TRL2;
SM_TRL2:
sm_readout <= SM_TRL3;
SM_TRL3:
begin
flag_pkam <= 0;
sm_readout <= SM_IDLE;
end
default: sm_readout <= SM_IDLE;
endcase
end
end
always @(*)
begin
if (sm_readout == SM_HDR1)
daq_data <= {8'ha0, queue_trigger_counter};
else if (sm_readout == SM_HDR2)
daq_data <= {8'h80, 4'b0000, queue_trg_pos};
else if (sm_readout == SM_TRL1)
daq_data <= {8'he0, ~queue_tok, queue_flags[0],
queue_flags[1], 1'b0, queue_flags[3], queue_flags[3], queue_flags[2], queue_flags[4]};
else if (sm_readout == SM_TRL2)
daq_data <= {8'hc0, queue_flags[5], flag_pkam, 2'b00, queue_size};
else daq_data <= 16'd0;
end
soft_tbm_queue #(18) stack
(
.clk(clk),
.sync(sync),
.reset(reset),
.write(trg_pass),
.read(queue_read),
.clear(queue_clear),
.clear_token(queue_clear_token),
.empty(queue_empty),
.full(queue_full),
.size(queue_size),
.din({flags, trg_pos, trigger_counter, 1'b1}),
.dout({queue_flags, queue_trg_pos, queue_trigger_counter, queue_tok})
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND3B_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__AND3B_PP_BLACKBOX_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__and3b (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND3B_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND4BB_FUNCTIONAL_V
`define SKY130_FD_SC_HD__AND4BB_FUNCTIONAL_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__and4bb (
X ,
A_N,
B_N,
C ,
D
);
// Module ports
output X ;
input A_N;
input B_N;
input C ;
input D ;
// Local signals
wire nor0_out ;
wire and0_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A_N, B_N );
and and0 (and0_out_X, nor0_out, C, D );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND4BB_FUNCTIONAL_V |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: rep_jbi_sc1_2.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module rep_jbi_sc1_2(/*AUTOARG*/
// Outputs
jbi_sctag_req_buf, scbuf_jbi_data_buf, jbi_scbuf_ecc_buf,
jbi_sctag_req_vld_buf, scbuf_jbi_ctag_vld_buf,
scbuf_jbi_ue_err_buf, sctag_jbi_iq_dequeue_buf,
sctag_jbi_wib_dequeue_buf, sctag_jbi_por_req_buf,
// Inputs
jbi_sctag_req, scbuf_jbi_data, jbi_scbuf_ecc, jbi_sctag_req_vld,
scbuf_jbi_ctag_vld, scbuf_jbi_ue_err, sctag_jbi_iq_dequeue,
sctag_jbi_wib_dequeue, sctag_jbi_por_req
);
output [31:0] jbi_sctag_req_buf;
output [31:0] scbuf_jbi_data_buf;
output [6:0] jbi_scbuf_ecc_buf;
output jbi_sctag_req_vld_buf;
output scbuf_jbi_ctag_vld_buf;
output scbuf_jbi_ue_err_buf;
output sctag_jbi_iq_dequeue_buf;
output sctag_jbi_wib_dequeue_buf;
output sctag_jbi_por_req_buf;
input [31:0] jbi_sctag_req;
input [31:0] scbuf_jbi_data;
input [6:0] jbi_scbuf_ecc;
input jbi_sctag_req_vld;
input scbuf_jbi_ctag_vld;
input scbuf_jbi_ue_err;
input sctag_jbi_iq_dequeue;
input sctag_jbi_wib_dequeue;
input sctag_jbi_por_req;
// This repeater bank is a row of flops
// There are a maximum of 10 flops per row.
assign jbi_sctag_req_buf = jbi_sctag_req ;
assign scbuf_jbi_data_buf = scbuf_jbi_data ;
assign jbi_scbuf_ecc_buf[6:0] = jbi_scbuf_ecc[6:0] ;
assign jbi_sctag_req_vld_buf = jbi_sctag_req_vld ;
assign scbuf_jbi_ctag_vld_buf = scbuf_jbi_ctag_vld ;
assign scbuf_jbi_ue_err_buf = scbuf_jbi_ue_err ;
assign sctag_jbi_iq_dequeue_buf = sctag_jbi_iq_dequeue ;
assign sctag_jbi_wib_dequeue_buf = sctag_jbi_wib_dequeue;
assign sctag_jbi_por_req_buf = sctag_jbi_por_req ;
endmodule
|
// soc_system.v
// Generated using ACDS version 14.1 188 at 2015.01.20.10:17:47
`timescale 1 ps / 1 ps
module soc_system (
input wire [3:0] button_pio_external_connection_export, // button_pio_external_connection.export
input wire clk_clk, // clk.clk
input wire [3:0] dipsw_pio_external_connection_export, // dipsw_pio_external_connection.export
input wire hps_0_f2h_cold_reset_req_reset_n, // hps_0_f2h_cold_reset_req.reset_n
input wire hps_0_f2h_debug_reset_req_reset_n, // hps_0_f2h_debug_reset_req.reset_n
input wire [27:0] hps_0_f2h_stm_hw_events_stm_hwevents, // hps_0_f2h_stm_hw_events.stm_hwevents
input wire hps_0_f2h_warm_reset_req_reset_n, // hps_0_f2h_warm_reset_req.reset_n
output wire hps_0_h2f_reset_reset_n, // hps_0_h2f_reset.reset_n
output wire hps_0_hps_io_hps_io_emac1_inst_TX_CLK, // hps_0_hps_io.hps_io_emac1_inst_TX_CLK
output wire hps_0_hps_io_hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire hps_0_hps_io_hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire hps_0_hps_io_hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire hps_0_hps_io_hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire hps_0_hps_io_hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire hps_0_hps_io_hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire hps_0_hps_io_hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire hps_0_hps_io_hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire hps_0_hps_io_hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire hps_0_hps_io_hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire hps_0_hps_io_hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire hps_0_hps_io_hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire hps_0_hps_io_hps_io_emac1_inst_RXD3, // .hps_io_emac1_inst_RXD3
inout wire hps_0_hps_io_hps_io_sdio_inst_CMD, // .hps_io_sdio_inst_CMD
inout wire hps_0_hps_io_hps_io_sdio_inst_D0, // .hps_io_sdio_inst_D0
inout wire hps_0_hps_io_hps_io_sdio_inst_D1, // .hps_io_sdio_inst_D1
output wire hps_0_hps_io_hps_io_sdio_inst_CLK, // .hps_io_sdio_inst_CLK
inout wire hps_0_hps_io_hps_io_sdio_inst_D2, // .hps_io_sdio_inst_D2
inout wire hps_0_hps_io_hps_io_sdio_inst_D3, // .hps_io_sdio_inst_D3
inout wire hps_0_hps_io_hps_io_usb1_inst_D0, // .hps_io_usb1_inst_D0
inout wire hps_0_hps_io_hps_io_usb1_inst_D1, // .hps_io_usb1_inst_D1
inout wire hps_0_hps_io_hps_io_usb1_inst_D2, // .hps_io_usb1_inst_D2
inout wire hps_0_hps_io_hps_io_usb1_inst_D3, // .hps_io_usb1_inst_D3
inout wire hps_0_hps_io_hps_io_usb1_inst_D4, // .hps_io_usb1_inst_D4
inout wire hps_0_hps_io_hps_io_usb1_inst_D5, // .hps_io_usb1_inst_D5
inout wire hps_0_hps_io_hps_io_usb1_inst_D6, // .hps_io_usb1_inst_D6
inout wire hps_0_hps_io_hps_io_usb1_inst_D7, // .hps_io_usb1_inst_D7
input wire hps_0_hps_io_hps_io_usb1_inst_CLK, // .hps_io_usb1_inst_CLK
output wire hps_0_hps_io_hps_io_usb1_inst_STP, // .hps_io_usb1_inst_STP
input wire hps_0_hps_io_hps_io_usb1_inst_DIR, // .hps_io_usb1_inst_DIR
input wire hps_0_hps_io_hps_io_usb1_inst_NXT, // .hps_io_usb1_inst_NXT
output wire hps_0_hps_io_hps_io_spim1_inst_CLK, // .hps_io_spim1_inst_CLK
output wire hps_0_hps_io_hps_io_spim1_inst_MOSI, // .hps_io_spim1_inst_MOSI
input wire hps_0_hps_io_hps_io_spim1_inst_MISO, // .hps_io_spim1_inst_MISO
output wire hps_0_hps_io_hps_io_spim1_inst_SS0, // .hps_io_spim1_inst_SS0
input wire hps_0_hps_io_hps_io_uart0_inst_RX, // .hps_io_uart0_inst_RX
output wire hps_0_hps_io_hps_io_uart0_inst_TX, // .hps_io_uart0_inst_TX
inout wire hps_0_hps_io_hps_io_i2c0_inst_SDA, // .hps_io_i2c0_inst_SDA
inout wire hps_0_hps_io_hps_io_i2c0_inst_SCL, // .hps_io_i2c0_inst_SCL
inout wire hps_0_hps_io_hps_io_i2c1_inst_SDA, // .hps_io_i2c1_inst_SDA
inout wire hps_0_hps_io_hps_io_i2c1_inst_SCL, // .hps_io_i2c1_inst_SCL
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO09, // .hps_io_gpio_inst_GPIO09
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO35, // .hps_io_gpio_inst_GPIO35
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO40, // .hps_io_gpio_inst_GPIO40
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO53, // .hps_io_gpio_inst_GPIO53
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO54, // .hps_io_gpio_inst_GPIO54
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO61, // .hps_io_gpio_inst_GPIO61
output wire [7:0] led_pio_external_connection_export, // led_pio_external_connection.export
output wire [14:0] memory_mem_a, // memory.mem_a
output wire [2:0] memory_mem_ba, // .mem_ba
output wire memory_mem_ck, // .mem_ck
output wire memory_mem_ck_n, // .mem_ck_n
output wire memory_mem_cke, // .mem_cke
output wire memory_mem_cs_n, // .mem_cs_n
output wire memory_mem_ras_n, // .mem_ras_n
output wire memory_mem_cas_n, // .mem_cas_n
output wire memory_mem_we_n, // .mem_we_n
output wire memory_mem_reset_n, // .mem_reset_n
inout wire [31:0] memory_mem_dq, // .mem_dq
inout wire [3:0] memory_mem_dqs, // .mem_dqs
inout wire [3:0] memory_mem_dqs_n, // .mem_dqs_n
output wire memory_mem_odt, // .mem_odt
output wire [3:0] memory_mem_dm, // .mem_dm
input wire memory_oct_rzqin, // .oct_rzqin
input wire reset_reset_n // reset.reset_n
);
wire [1:0] hps_0_h2f_axi_master_awburst; // hps_0:h2f_AWBURST -> mm_interconnect_0:hps_0_h2f_axi_master_awburst
wire [3:0] hps_0_h2f_axi_master_arlen; // hps_0:h2f_ARLEN -> mm_interconnect_0:hps_0_h2f_axi_master_arlen
wire [7:0] hps_0_h2f_axi_master_wstrb; // hps_0:h2f_WSTRB -> mm_interconnect_0:hps_0_h2f_axi_master_wstrb
wire hps_0_h2f_axi_master_wready; // mm_interconnect_0:hps_0_h2f_axi_master_wready -> hps_0:h2f_WREADY
wire [11:0] hps_0_h2f_axi_master_rid; // mm_interconnect_0:hps_0_h2f_axi_master_rid -> hps_0:h2f_RID
wire hps_0_h2f_axi_master_rready; // hps_0:h2f_RREADY -> mm_interconnect_0:hps_0_h2f_axi_master_rready
wire [3:0] hps_0_h2f_axi_master_awlen; // hps_0:h2f_AWLEN -> mm_interconnect_0:hps_0_h2f_axi_master_awlen
wire [11:0] hps_0_h2f_axi_master_wid; // hps_0:h2f_WID -> mm_interconnect_0:hps_0_h2f_axi_master_wid
wire [3:0] hps_0_h2f_axi_master_arcache; // hps_0:h2f_ARCACHE -> mm_interconnect_0:hps_0_h2f_axi_master_arcache
wire hps_0_h2f_axi_master_wvalid; // hps_0:h2f_WVALID -> mm_interconnect_0:hps_0_h2f_axi_master_wvalid
wire [29:0] hps_0_h2f_axi_master_araddr; // hps_0:h2f_ARADDR -> mm_interconnect_0:hps_0_h2f_axi_master_araddr
wire [2:0] hps_0_h2f_axi_master_arprot; // hps_0:h2f_ARPROT -> mm_interconnect_0:hps_0_h2f_axi_master_arprot
wire [2:0] hps_0_h2f_axi_master_awprot; // hps_0:h2f_AWPROT -> mm_interconnect_0:hps_0_h2f_axi_master_awprot
wire [63:0] hps_0_h2f_axi_master_wdata; // hps_0:h2f_WDATA -> mm_interconnect_0:hps_0_h2f_axi_master_wdata
wire hps_0_h2f_axi_master_arvalid; // hps_0:h2f_ARVALID -> mm_interconnect_0:hps_0_h2f_axi_master_arvalid
wire [3:0] hps_0_h2f_axi_master_awcache; // hps_0:h2f_AWCACHE -> mm_interconnect_0:hps_0_h2f_axi_master_awcache
wire [11:0] hps_0_h2f_axi_master_arid; // hps_0:h2f_ARID -> mm_interconnect_0:hps_0_h2f_axi_master_arid
wire [1:0] hps_0_h2f_axi_master_arlock; // hps_0:h2f_ARLOCK -> mm_interconnect_0:hps_0_h2f_axi_master_arlock
wire [1:0] hps_0_h2f_axi_master_awlock; // hps_0:h2f_AWLOCK -> mm_interconnect_0:hps_0_h2f_axi_master_awlock
wire [29:0] hps_0_h2f_axi_master_awaddr; // hps_0:h2f_AWADDR -> mm_interconnect_0:hps_0_h2f_axi_master_awaddr
wire [1:0] hps_0_h2f_axi_master_bresp; // mm_interconnect_0:hps_0_h2f_axi_master_bresp -> hps_0:h2f_BRESP
wire hps_0_h2f_axi_master_arready; // mm_interconnect_0:hps_0_h2f_axi_master_arready -> hps_0:h2f_ARREADY
wire [63:0] hps_0_h2f_axi_master_rdata; // mm_interconnect_0:hps_0_h2f_axi_master_rdata -> hps_0:h2f_RDATA
wire hps_0_h2f_axi_master_awready; // mm_interconnect_0:hps_0_h2f_axi_master_awready -> hps_0:h2f_AWREADY
wire [1:0] hps_0_h2f_axi_master_arburst; // hps_0:h2f_ARBURST -> mm_interconnect_0:hps_0_h2f_axi_master_arburst
wire [2:0] hps_0_h2f_axi_master_arsize; // hps_0:h2f_ARSIZE -> mm_interconnect_0:hps_0_h2f_axi_master_arsize
wire hps_0_h2f_axi_master_bready; // hps_0:h2f_BREADY -> mm_interconnect_0:hps_0_h2f_axi_master_bready
wire hps_0_h2f_axi_master_rlast; // mm_interconnect_0:hps_0_h2f_axi_master_rlast -> hps_0:h2f_RLAST
wire hps_0_h2f_axi_master_wlast; // hps_0:h2f_WLAST -> mm_interconnect_0:hps_0_h2f_axi_master_wlast
wire [1:0] hps_0_h2f_axi_master_rresp; // mm_interconnect_0:hps_0_h2f_axi_master_rresp -> hps_0:h2f_RRESP
wire [11:0] hps_0_h2f_axi_master_awid; // hps_0:h2f_AWID -> mm_interconnect_0:hps_0_h2f_axi_master_awid
wire [11:0] hps_0_h2f_axi_master_bid; // mm_interconnect_0:hps_0_h2f_axi_master_bid -> hps_0:h2f_BID
wire hps_0_h2f_axi_master_bvalid; // mm_interconnect_0:hps_0_h2f_axi_master_bvalid -> hps_0:h2f_BVALID
wire [2:0] hps_0_h2f_axi_master_awsize; // hps_0:h2f_AWSIZE -> mm_interconnect_0:hps_0_h2f_axi_master_awsize
wire hps_0_h2f_axi_master_awvalid; // hps_0:h2f_AWVALID -> mm_interconnect_0:hps_0_h2f_axi_master_awvalid
wire hps_0_h2f_axi_master_rvalid; // mm_interconnect_0:hps_0_h2f_axi_master_rvalid -> hps_0:h2f_RVALID
wire [31:0] fpga_only_master_master_readdata; // mm_interconnect_0:fpga_only_master_master_readdata -> fpga_only_master:master_readdata
wire fpga_only_master_master_waitrequest; // mm_interconnect_0:fpga_only_master_master_waitrequest -> fpga_only_master:master_waitrequest
wire [31:0] fpga_only_master_master_address; // fpga_only_master:master_address -> mm_interconnect_0:fpga_only_master_master_address
wire fpga_only_master_master_read; // fpga_only_master:master_read -> mm_interconnect_0:fpga_only_master_master_read
wire [3:0] fpga_only_master_master_byteenable; // fpga_only_master:master_byteenable -> mm_interconnect_0:fpga_only_master_master_byteenable
wire fpga_only_master_master_readdatavalid; // mm_interconnect_0:fpga_only_master_master_readdatavalid -> fpga_only_master:master_readdatavalid
wire fpga_only_master_master_write; // fpga_only_master:master_write -> mm_interconnect_0:fpga_only_master_master_write
wire [31:0] fpga_only_master_master_writedata; // fpga_only_master:master_writedata -> mm_interconnect_0:fpga_only_master_master_writedata
wire [1:0] hps_0_h2f_lw_axi_master_awburst; // hps_0:h2f_lw_AWBURST -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awburst
wire [3:0] hps_0_h2f_lw_axi_master_arlen; // hps_0:h2f_lw_ARLEN -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arlen
wire [3:0] hps_0_h2f_lw_axi_master_wstrb; // hps_0:h2f_lw_WSTRB -> mm_interconnect_0:hps_0_h2f_lw_axi_master_wstrb
wire hps_0_h2f_lw_axi_master_wready; // mm_interconnect_0:hps_0_h2f_lw_axi_master_wready -> hps_0:h2f_lw_WREADY
wire [11:0] hps_0_h2f_lw_axi_master_rid; // mm_interconnect_0:hps_0_h2f_lw_axi_master_rid -> hps_0:h2f_lw_RID
wire hps_0_h2f_lw_axi_master_rready; // hps_0:h2f_lw_RREADY -> mm_interconnect_0:hps_0_h2f_lw_axi_master_rready
wire [3:0] hps_0_h2f_lw_axi_master_awlen; // hps_0:h2f_lw_AWLEN -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awlen
wire [11:0] hps_0_h2f_lw_axi_master_wid; // hps_0:h2f_lw_WID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_wid
wire [3:0] hps_0_h2f_lw_axi_master_arcache; // hps_0:h2f_lw_ARCACHE -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arcache
wire hps_0_h2f_lw_axi_master_wvalid; // hps_0:h2f_lw_WVALID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_wvalid
wire [20:0] hps_0_h2f_lw_axi_master_araddr; // hps_0:h2f_lw_ARADDR -> mm_interconnect_0:hps_0_h2f_lw_axi_master_araddr
wire [2:0] hps_0_h2f_lw_axi_master_arprot; // hps_0:h2f_lw_ARPROT -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arprot
wire [2:0] hps_0_h2f_lw_axi_master_awprot; // hps_0:h2f_lw_AWPROT -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awprot
wire [31:0] hps_0_h2f_lw_axi_master_wdata; // hps_0:h2f_lw_WDATA -> mm_interconnect_0:hps_0_h2f_lw_axi_master_wdata
wire hps_0_h2f_lw_axi_master_arvalid; // hps_0:h2f_lw_ARVALID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arvalid
wire [3:0] hps_0_h2f_lw_axi_master_awcache; // hps_0:h2f_lw_AWCACHE -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awcache
wire [11:0] hps_0_h2f_lw_axi_master_arid; // hps_0:h2f_lw_ARID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arid
wire [1:0] hps_0_h2f_lw_axi_master_arlock; // hps_0:h2f_lw_ARLOCK -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arlock
wire [1:0] hps_0_h2f_lw_axi_master_awlock; // hps_0:h2f_lw_AWLOCK -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awlock
wire [20:0] hps_0_h2f_lw_axi_master_awaddr; // hps_0:h2f_lw_AWADDR -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awaddr
wire [1:0] hps_0_h2f_lw_axi_master_bresp; // mm_interconnect_0:hps_0_h2f_lw_axi_master_bresp -> hps_0:h2f_lw_BRESP
wire hps_0_h2f_lw_axi_master_arready; // mm_interconnect_0:hps_0_h2f_lw_axi_master_arready -> hps_0:h2f_lw_ARREADY
wire [31:0] hps_0_h2f_lw_axi_master_rdata; // mm_interconnect_0:hps_0_h2f_lw_axi_master_rdata -> hps_0:h2f_lw_RDATA
wire hps_0_h2f_lw_axi_master_awready; // mm_interconnect_0:hps_0_h2f_lw_axi_master_awready -> hps_0:h2f_lw_AWREADY
wire [1:0] hps_0_h2f_lw_axi_master_arburst; // hps_0:h2f_lw_ARBURST -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arburst
wire [2:0] hps_0_h2f_lw_axi_master_arsize; // hps_0:h2f_lw_ARSIZE -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arsize
wire hps_0_h2f_lw_axi_master_bready; // hps_0:h2f_lw_BREADY -> mm_interconnect_0:hps_0_h2f_lw_axi_master_bready
wire hps_0_h2f_lw_axi_master_rlast; // mm_interconnect_0:hps_0_h2f_lw_axi_master_rlast -> hps_0:h2f_lw_RLAST
wire hps_0_h2f_lw_axi_master_wlast; // hps_0:h2f_lw_WLAST -> mm_interconnect_0:hps_0_h2f_lw_axi_master_wlast
wire [1:0] hps_0_h2f_lw_axi_master_rresp; // mm_interconnect_0:hps_0_h2f_lw_axi_master_rresp -> hps_0:h2f_lw_RRESP
wire [11:0] hps_0_h2f_lw_axi_master_awid; // hps_0:h2f_lw_AWID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awid
wire [11:0] hps_0_h2f_lw_axi_master_bid; // mm_interconnect_0:hps_0_h2f_lw_axi_master_bid -> hps_0:h2f_lw_BID
wire hps_0_h2f_lw_axi_master_bvalid; // mm_interconnect_0:hps_0_h2f_lw_axi_master_bvalid -> hps_0:h2f_lw_BVALID
wire [2:0] hps_0_h2f_lw_axi_master_awsize; // hps_0:h2f_lw_AWSIZE -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awsize
wire hps_0_h2f_lw_axi_master_awvalid; // hps_0:h2f_lw_AWVALID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awvalid
wire hps_0_h2f_lw_axi_master_rvalid; // mm_interconnect_0:hps_0_h2f_lw_axi_master_rvalid -> hps_0:h2f_lw_RVALID
wire mm_interconnect_0_onchip_memory2_0_s1_chipselect; // mm_interconnect_0:onchip_memory2_0_s1_chipselect -> onchip_memory2_0:chipselect
wire [63:0] mm_interconnect_0_onchip_memory2_0_s1_readdata; // onchip_memory2_0:readdata -> mm_interconnect_0:onchip_memory2_0_s1_readdata
wire [12:0] mm_interconnect_0_onchip_memory2_0_s1_address; // mm_interconnect_0:onchip_memory2_0_s1_address -> onchip_memory2_0:address
wire [7:0] mm_interconnect_0_onchip_memory2_0_s1_byteenable; // mm_interconnect_0:onchip_memory2_0_s1_byteenable -> onchip_memory2_0:byteenable
wire mm_interconnect_0_onchip_memory2_0_s1_write; // mm_interconnect_0:onchip_memory2_0_s1_write -> onchip_memory2_0:write
wire [63:0] mm_interconnect_0_onchip_memory2_0_s1_writedata; // mm_interconnect_0:onchip_memory2_0_s1_writedata -> onchip_memory2_0:writedata
wire mm_interconnect_0_onchip_memory2_0_s1_clken; // mm_interconnect_0:onchip_memory2_0_s1_clken -> onchip_memory2_0:clken
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_chipselect -> jtag_uart:av_chipselect
wire [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata; // jtag_uart:av_readdata -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_readdata
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest; // jtag_uart:av_waitrequest -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_waitrequest
wire [0:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_address; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_address -> jtag_uart:av_address
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_read; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_read -> jtag_uart:av_read_n
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_write; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_write -> jtag_uart:av_write_n
wire [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_writedata -> jtag_uart:av_writedata
wire [31:0] mm_interconnect_0_intr_capturer_0_avalon_slave_0_readdata; // intr_capturer_0:rddata -> mm_interconnect_0:intr_capturer_0_avalon_slave_0_readdata
wire [0:0] mm_interconnect_0_intr_capturer_0_avalon_slave_0_address; // mm_interconnect_0:intr_capturer_0_avalon_slave_0_address -> intr_capturer_0:addr
wire mm_interconnect_0_intr_capturer_0_avalon_slave_0_read; // mm_interconnect_0:intr_capturer_0_avalon_slave_0_read -> intr_capturer_0:read
wire [31:0] mm_interconnect_0_sysid_qsys_control_slave_readdata; // sysid_qsys:readdata -> mm_interconnect_0:sysid_qsys_control_slave_readdata
wire [0:0] mm_interconnect_0_sysid_qsys_control_slave_address; // mm_interconnect_0:sysid_qsys_control_slave_address -> sysid_qsys:address
wire mm_interconnect_0_led_pio_s1_chipselect; // mm_interconnect_0:led_pio_s1_chipselect -> led_pio:chipselect
wire [31:0] mm_interconnect_0_led_pio_s1_readdata; // led_pio:readdata -> mm_interconnect_0:led_pio_s1_readdata
wire [1:0] mm_interconnect_0_led_pio_s1_address; // mm_interconnect_0:led_pio_s1_address -> led_pio:address
wire mm_interconnect_0_led_pio_s1_write; // mm_interconnect_0:led_pio_s1_write -> led_pio:write_n
wire [31:0] mm_interconnect_0_led_pio_s1_writedata; // mm_interconnect_0:led_pio_s1_writedata -> led_pio:writedata
wire mm_interconnect_0_dipsw_pio_s1_chipselect; // mm_interconnect_0:dipsw_pio_s1_chipselect -> dipsw_pio:chipselect
wire [31:0] mm_interconnect_0_dipsw_pio_s1_readdata; // dipsw_pio:readdata -> mm_interconnect_0:dipsw_pio_s1_readdata
wire [1:0] mm_interconnect_0_dipsw_pio_s1_address; // mm_interconnect_0:dipsw_pio_s1_address -> dipsw_pio:address
wire mm_interconnect_0_dipsw_pio_s1_write; // mm_interconnect_0:dipsw_pio_s1_write -> dipsw_pio:write_n
wire [31:0] mm_interconnect_0_dipsw_pio_s1_writedata; // mm_interconnect_0:dipsw_pio_s1_writedata -> dipsw_pio:writedata
wire mm_interconnect_0_button_pio_s1_chipselect; // mm_interconnect_0:button_pio_s1_chipselect -> button_pio:chipselect
wire [31:0] mm_interconnect_0_button_pio_s1_readdata; // button_pio:readdata -> mm_interconnect_0:button_pio_s1_readdata
wire [1:0] mm_interconnect_0_button_pio_s1_address; // mm_interconnect_0:button_pio_s1_address -> button_pio:address
wire mm_interconnect_0_button_pio_s1_write; // mm_interconnect_0:button_pio_s1_write -> button_pio:write_n
wire [31:0] mm_interconnect_0_button_pio_s1_writedata; // mm_interconnect_0:button_pio_s1_writedata -> button_pio:writedata
wire [31:0] hps_only_master_master_readdata; // mm_interconnect_1:hps_only_master_master_readdata -> hps_only_master:master_readdata
wire hps_only_master_master_waitrequest; // mm_interconnect_1:hps_only_master_master_waitrequest -> hps_only_master:master_waitrequest
wire [31:0] hps_only_master_master_address; // hps_only_master:master_address -> mm_interconnect_1:hps_only_master_master_address
wire hps_only_master_master_read; // hps_only_master:master_read -> mm_interconnect_1:hps_only_master_master_read
wire [3:0] hps_only_master_master_byteenable; // hps_only_master:master_byteenable -> mm_interconnect_1:hps_only_master_master_byteenable
wire hps_only_master_master_readdatavalid; // mm_interconnect_1:hps_only_master_master_readdatavalid -> hps_only_master:master_readdatavalid
wire hps_only_master_master_write; // hps_only_master:master_write -> mm_interconnect_1:hps_only_master_master_write
wire [31:0] hps_only_master_master_writedata; // hps_only_master:master_writedata -> mm_interconnect_1:hps_only_master_master_writedata
wire [1:0] mm_interconnect_1_hps_0_f2h_axi_slave_awburst; // mm_interconnect_1:hps_0_f2h_axi_slave_awburst -> hps_0:f2h_AWBURST
wire [4:0] mm_interconnect_1_hps_0_f2h_axi_slave_awuser; // mm_interconnect_1:hps_0_f2h_axi_slave_awuser -> hps_0:f2h_AWUSER
wire [3:0] mm_interconnect_1_hps_0_f2h_axi_slave_arlen; // mm_interconnect_1:hps_0_f2h_axi_slave_arlen -> hps_0:f2h_ARLEN
wire [15:0] mm_interconnect_1_hps_0_f2h_axi_slave_wstrb; // mm_interconnect_1:hps_0_f2h_axi_slave_wstrb -> hps_0:f2h_WSTRB
wire mm_interconnect_1_hps_0_f2h_axi_slave_wready; // hps_0:f2h_WREADY -> mm_interconnect_1:hps_0_f2h_axi_slave_wready
wire [7:0] mm_interconnect_1_hps_0_f2h_axi_slave_rid; // hps_0:f2h_RID -> mm_interconnect_1:hps_0_f2h_axi_slave_rid
wire mm_interconnect_1_hps_0_f2h_axi_slave_rready; // mm_interconnect_1:hps_0_f2h_axi_slave_rready -> hps_0:f2h_RREADY
wire [3:0] mm_interconnect_1_hps_0_f2h_axi_slave_awlen; // mm_interconnect_1:hps_0_f2h_axi_slave_awlen -> hps_0:f2h_AWLEN
wire [7:0] mm_interconnect_1_hps_0_f2h_axi_slave_wid; // mm_interconnect_1:hps_0_f2h_axi_slave_wid -> hps_0:f2h_WID
wire [3:0] mm_interconnect_1_hps_0_f2h_axi_slave_arcache; // mm_interconnect_1:hps_0_f2h_axi_slave_arcache -> hps_0:f2h_ARCACHE
wire mm_interconnect_1_hps_0_f2h_axi_slave_wvalid; // mm_interconnect_1:hps_0_f2h_axi_slave_wvalid -> hps_0:f2h_WVALID
wire [31:0] mm_interconnect_1_hps_0_f2h_axi_slave_araddr; // mm_interconnect_1:hps_0_f2h_axi_slave_araddr -> hps_0:f2h_ARADDR
wire [2:0] mm_interconnect_1_hps_0_f2h_axi_slave_arprot; // mm_interconnect_1:hps_0_f2h_axi_slave_arprot -> hps_0:f2h_ARPROT
wire [2:0] mm_interconnect_1_hps_0_f2h_axi_slave_awprot; // mm_interconnect_1:hps_0_f2h_axi_slave_awprot -> hps_0:f2h_AWPROT
wire [127:0] mm_interconnect_1_hps_0_f2h_axi_slave_wdata; // mm_interconnect_1:hps_0_f2h_axi_slave_wdata -> hps_0:f2h_WDATA
wire mm_interconnect_1_hps_0_f2h_axi_slave_arvalid; // mm_interconnect_1:hps_0_f2h_axi_slave_arvalid -> hps_0:f2h_ARVALID
wire [3:0] mm_interconnect_1_hps_0_f2h_axi_slave_awcache; // mm_interconnect_1:hps_0_f2h_axi_slave_awcache -> hps_0:f2h_AWCACHE
wire [7:0] mm_interconnect_1_hps_0_f2h_axi_slave_arid; // mm_interconnect_1:hps_0_f2h_axi_slave_arid -> hps_0:f2h_ARID
wire [1:0] mm_interconnect_1_hps_0_f2h_axi_slave_arlock; // mm_interconnect_1:hps_0_f2h_axi_slave_arlock -> hps_0:f2h_ARLOCK
wire [1:0] mm_interconnect_1_hps_0_f2h_axi_slave_awlock; // mm_interconnect_1:hps_0_f2h_axi_slave_awlock -> hps_0:f2h_AWLOCK
wire [31:0] mm_interconnect_1_hps_0_f2h_axi_slave_awaddr; // mm_interconnect_1:hps_0_f2h_axi_slave_awaddr -> hps_0:f2h_AWADDR
wire [1:0] mm_interconnect_1_hps_0_f2h_axi_slave_bresp; // hps_0:f2h_BRESP -> mm_interconnect_1:hps_0_f2h_axi_slave_bresp
wire mm_interconnect_1_hps_0_f2h_axi_slave_arready; // hps_0:f2h_ARREADY -> mm_interconnect_1:hps_0_f2h_axi_slave_arready
wire [127:0] mm_interconnect_1_hps_0_f2h_axi_slave_rdata; // hps_0:f2h_RDATA -> mm_interconnect_1:hps_0_f2h_axi_slave_rdata
wire mm_interconnect_1_hps_0_f2h_axi_slave_awready; // hps_0:f2h_AWREADY -> mm_interconnect_1:hps_0_f2h_axi_slave_awready
wire [1:0] mm_interconnect_1_hps_0_f2h_axi_slave_arburst; // mm_interconnect_1:hps_0_f2h_axi_slave_arburst -> hps_0:f2h_ARBURST
wire [2:0] mm_interconnect_1_hps_0_f2h_axi_slave_arsize; // mm_interconnect_1:hps_0_f2h_axi_slave_arsize -> hps_0:f2h_ARSIZE
wire mm_interconnect_1_hps_0_f2h_axi_slave_bready; // mm_interconnect_1:hps_0_f2h_axi_slave_bready -> hps_0:f2h_BREADY
wire mm_interconnect_1_hps_0_f2h_axi_slave_rlast; // hps_0:f2h_RLAST -> mm_interconnect_1:hps_0_f2h_axi_slave_rlast
wire mm_interconnect_1_hps_0_f2h_axi_slave_wlast; // mm_interconnect_1:hps_0_f2h_axi_slave_wlast -> hps_0:f2h_WLAST
wire [1:0] mm_interconnect_1_hps_0_f2h_axi_slave_rresp; // hps_0:f2h_RRESP -> mm_interconnect_1:hps_0_f2h_axi_slave_rresp
wire [7:0] mm_interconnect_1_hps_0_f2h_axi_slave_awid; // mm_interconnect_1:hps_0_f2h_axi_slave_awid -> hps_0:f2h_AWID
wire [7:0] mm_interconnect_1_hps_0_f2h_axi_slave_bid; // hps_0:f2h_BID -> mm_interconnect_1:hps_0_f2h_axi_slave_bid
wire mm_interconnect_1_hps_0_f2h_axi_slave_bvalid; // hps_0:f2h_BVALID -> mm_interconnect_1:hps_0_f2h_axi_slave_bvalid
wire [2:0] mm_interconnect_1_hps_0_f2h_axi_slave_awsize; // mm_interconnect_1:hps_0_f2h_axi_slave_awsize -> hps_0:f2h_AWSIZE
wire mm_interconnect_1_hps_0_f2h_axi_slave_awvalid; // mm_interconnect_1:hps_0_f2h_axi_slave_awvalid -> hps_0:f2h_AWVALID
wire [4:0] mm_interconnect_1_hps_0_f2h_axi_slave_aruser; // mm_interconnect_1:hps_0_f2h_axi_slave_aruser -> hps_0:f2h_ARUSER
wire mm_interconnect_1_hps_0_f2h_axi_slave_rvalid; // hps_0:f2h_RVALID -> mm_interconnect_1:hps_0_f2h_axi_slave_rvalid
wire [31:0] hps_0_f2h_irq0_irq; // irq_mapper:sender_irq -> hps_0:f2h_irq_p0
wire [31:0] hps_0_f2h_irq1_irq; // irq_mapper_001:sender_irq -> hps_0:f2h_irq_p1
wire [31:0] intr_capturer_0_interrupt_receiver_irq; // irq_mapper_002:sender_irq -> intr_capturer_0:interrupt_in
wire irq_mapper_receiver1_irq; // button_pio:irq -> [irq_mapper:receiver1_irq, irq_mapper_002:receiver1_irq]
wire irq_mapper_receiver2_irq; // dipsw_pio:irq -> [irq_mapper:receiver2_irq, irq_mapper_002:receiver2_irq]
wire irq_mapper_receiver0_irq; // jtag_uart:av_irq -> [irq_mapper:receiver0_irq, irq_mapper_002:receiver0_irq]
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [button_pio:reset_n, dipsw_pio:reset_n, intr_capturer_0:rst_n, irq_mapper_002:reset, jtag_uart:rst_n, led_pio:reset_n, mm_interconnect_0:fpga_only_master_clk_reset_reset_bridge_in_reset_reset, mm_interconnect_0:onchip_memory2_0_reset1_reset_bridge_in_reset_reset, mm_interconnect_1:hps_only_master_clk_reset_reset_bridge_in_reset_reset, mm_interconnect_1:hps_only_master_master_translator_reset_reset_bridge_in_reset_reset, onchip_memory2_0:reset, rst_translator:in_reset, sysid_qsys:reset_n]
wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> [onchip_memory2_0:reset_req, rst_translator:reset_req_in]
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [mm_interconnect_0:hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset, mm_interconnect_1:hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset]
soc_system_button_pio button_pio (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_button_pio_s1_address), // s1.address
.write_n (~mm_interconnect_0_button_pio_s1_write), // .write_n
.writedata (mm_interconnect_0_button_pio_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_button_pio_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_button_pio_s1_readdata), // .readdata
.in_port (button_pio_external_connection_export), // external_connection.export
.irq (irq_mapper_receiver1_irq) // irq.irq
);
soc_system_dipsw_pio dipsw_pio (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_dipsw_pio_s1_address), // s1.address
.write_n (~mm_interconnect_0_dipsw_pio_s1_write), // .write_n
.writedata (mm_interconnect_0_dipsw_pio_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_dipsw_pio_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_dipsw_pio_s1_readdata), // .readdata
.in_port (dipsw_pio_external_connection_export), // external_connection.export
.irq (irq_mapper_receiver2_irq) // irq.irq
);
soc_system_fpga_only_master #(
.USE_PLI (0),
.PLI_PORT (50000),
.FIFO_DEPTHS (2)
) fpga_only_master (
.clk_clk (clk_clk), // clk.clk
.clk_reset_reset (~reset_reset_n), // clk_reset.reset
.master_address (fpga_only_master_master_address), // master.address
.master_readdata (fpga_only_master_master_readdata), // .readdata
.master_read (fpga_only_master_master_read), // .read
.master_write (fpga_only_master_master_write), // .write
.master_writedata (fpga_only_master_master_writedata), // .writedata
.master_waitrequest (fpga_only_master_master_waitrequest), // .waitrequest
.master_readdatavalid (fpga_only_master_master_readdatavalid), // .readdatavalid
.master_byteenable (fpga_only_master_master_byteenable), // .byteenable
.master_reset_reset () // master_reset.reset
);
soc_system_hps_0 #(
.F2S_Width (3),
.S2F_Width (2)
) hps_0 (
.f2h_cold_rst_req_n (hps_0_f2h_cold_reset_req_reset_n), // f2h_cold_reset_req.reset_n
.f2h_dbg_rst_req_n (hps_0_f2h_debug_reset_req_reset_n), // f2h_debug_reset_req.reset_n
.f2h_warm_rst_req_n (hps_0_f2h_warm_reset_req_reset_n), // f2h_warm_reset_req.reset_n
.f2h_stm_hwevents (hps_0_f2h_stm_hw_events_stm_hwevents), // f2h_stm_hw_events.stm_hwevents
.mem_a (memory_mem_a), // memory.mem_a
.mem_ba (memory_mem_ba), // .mem_ba
.mem_ck (memory_mem_ck), // .mem_ck
.mem_ck_n (memory_mem_ck_n), // .mem_ck_n
.mem_cke (memory_mem_cke), // .mem_cke
.mem_cs_n (memory_mem_cs_n), // .mem_cs_n
.mem_ras_n (memory_mem_ras_n), // .mem_ras_n
.mem_cas_n (memory_mem_cas_n), // .mem_cas_n
.mem_we_n (memory_mem_we_n), // .mem_we_n
.mem_reset_n (memory_mem_reset_n), // .mem_reset_n
.mem_dq (memory_mem_dq), // .mem_dq
.mem_dqs (memory_mem_dqs), // .mem_dqs
.mem_dqs_n (memory_mem_dqs_n), // .mem_dqs_n
.mem_odt (memory_mem_odt), // .mem_odt
.mem_dm (memory_mem_dm), // .mem_dm
.oct_rzqin (memory_oct_rzqin), // .oct_rzqin
.hps_io_emac1_inst_TX_CLK (hps_0_hps_io_hps_io_emac1_inst_TX_CLK), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_emac1_inst_TXD0 (hps_0_hps_io_hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_emac1_inst_TXD1 (hps_0_hps_io_hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_emac1_inst_TXD2 (hps_0_hps_io_hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_emac1_inst_TXD3 (hps_0_hps_io_hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_emac1_inst_RXD0 (hps_0_hps_io_hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_emac1_inst_MDIO (hps_0_hps_io_hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_emac1_inst_MDC (hps_0_hps_io_hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_emac1_inst_RX_CTL (hps_0_hps_io_hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_emac1_inst_TX_CTL (hps_0_hps_io_hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_emac1_inst_RX_CLK (hps_0_hps_io_hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_emac1_inst_RXD1 (hps_0_hps_io_hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_emac1_inst_RXD2 (hps_0_hps_io_hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_emac1_inst_RXD3 (hps_0_hps_io_hps_io_emac1_inst_RXD3), // .hps_io_emac1_inst_RXD3
.hps_io_sdio_inst_CMD (hps_0_hps_io_hps_io_sdio_inst_CMD), // .hps_io_sdio_inst_CMD
.hps_io_sdio_inst_D0 (hps_0_hps_io_hps_io_sdio_inst_D0), // .hps_io_sdio_inst_D0
.hps_io_sdio_inst_D1 (hps_0_hps_io_hps_io_sdio_inst_D1), // .hps_io_sdio_inst_D1
.hps_io_sdio_inst_CLK (hps_0_hps_io_hps_io_sdio_inst_CLK), // .hps_io_sdio_inst_CLK
.hps_io_sdio_inst_D2 (hps_0_hps_io_hps_io_sdio_inst_D2), // .hps_io_sdio_inst_D2
.hps_io_sdio_inst_D3 (hps_0_hps_io_hps_io_sdio_inst_D3), // .hps_io_sdio_inst_D3
.hps_io_usb1_inst_D0 (hps_0_hps_io_hps_io_usb1_inst_D0), // .hps_io_usb1_inst_D0
.hps_io_usb1_inst_D1 (hps_0_hps_io_hps_io_usb1_inst_D1), // .hps_io_usb1_inst_D1
.hps_io_usb1_inst_D2 (hps_0_hps_io_hps_io_usb1_inst_D2), // .hps_io_usb1_inst_D2
.hps_io_usb1_inst_D3 (hps_0_hps_io_hps_io_usb1_inst_D3), // .hps_io_usb1_inst_D3
.hps_io_usb1_inst_D4 (hps_0_hps_io_hps_io_usb1_inst_D4), // .hps_io_usb1_inst_D4
.hps_io_usb1_inst_D5 (hps_0_hps_io_hps_io_usb1_inst_D5), // .hps_io_usb1_inst_D5
.hps_io_usb1_inst_D6 (hps_0_hps_io_hps_io_usb1_inst_D6), // .hps_io_usb1_inst_D6
.hps_io_usb1_inst_D7 (hps_0_hps_io_hps_io_usb1_inst_D7), // .hps_io_usb1_inst_D7
.hps_io_usb1_inst_CLK (hps_0_hps_io_hps_io_usb1_inst_CLK), // .hps_io_usb1_inst_CLK
.hps_io_usb1_inst_STP (hps_0_hps_io_hps_io_usb1_inst_STP), // .hps_io_usb1_inst_STP
.hps_io_usb1_inst_DIR (hps_0_hps_io_hps_io_usb1_inst_DIR), // .hps_io_usb1_inst_DIR
.hps_io_usb1_inst_NXT (hps_0_hps_io_hps_io_usb1_inst_NXT), // .hps_io_usb1_inst_NXT
.hps_io_spim1_inst_CLK (hps_0_hps_io_hps_io_spim1_inst_CLK), // .hps_io_spim1_inst_CLK
.hps_io_spim1_inst_MOSI (hps_0_hps_io_hps_io_spim1_inst_MOSI), // .hps_io_spim1_inst_MOSI
.hps_io_spim1_inst_MISO (hps_0_hps_io_hps_io_spim1_inst_MISO), // .hps_io_spim1_inst_MISO
.hps_io_spim1_inst_SS0 (hps_0_hps_io_hps_io_spim1_inst_SS0), // .hps_io_spim1_inst_SS0
.hps_io_uart0_inst_RX (hps_0_hps_io_hps_io_uart0_inst_RX), // .hps_io_uart0_inst_RX
.hps_io_uart0_inst_TX (hps_0_hps_io_hps_io_uart0_inst_TX), // .hps_io_uart0_inst_TX
.hps_io_i2c0_inst_SDA (hps_0_hps_io_hps_io_i2c0_inst_SDA), // .hps_io_i2c0_inst_SDA
.hps_io_i2c0_inst_SCL (hps_0_hps_io_hps_io_i2c0_inst_SCL), // .hps_io_i2c0_inst_SCL
.hps_io_i2c1_inst_SDA (hps_0_hps_io_hps_io_i2c1_inst_SDA), // .hps_io_i2c1_inst_SDA
.hps_io_i2c1_inst_SCL (hps_0_hps_io_hps_io_i2c1_inst_SCL), // .hps_io_i2c1_inst_SCL
.hps_io_gpio_inst_GPIO09 (hps_0_hps_io_hps_io_gpio_inst_GPIO09), // .hps_io_gpio_inst_GPIO09
.hps_io_gpio_inst_GPIO35 (hps_0_hps_io_hps_io_gpio_inst_GPIO35), // .hps_io_gpio_inst_GPIO35
.hps_io_gpio_inst_GPIO40 (hps_0_hps_io_hps_io_gpio_inst_GPIO40), // .hps_io_gpio_inst_GPIO40
.hps_io_gpio_inst_GPIO53 (hps_0_hps_io_hps_io_gpio_inst_GPIO53), // .hps_io_gpio_inst_GPIO53
.hps_io_gpio_inst_GPIO54 (hps_0_hps_io_hps_io_gpio_inst_GPIO54), // .hps_io_gpio_inst_GPIO54
.hps_io_gpio_inst_GPIO61 (hps_0_hps_io_hps_io_gpio_inst_GPIO61), // .hps_io_gpio_inst_GPIO61
.h2f_rst_n (hps_0_h2f_reset_reset_n), // h2f_reset.reset_n
.h2f_axi_clk (clk_clk), // h2f_axi_clock.clk
.h2f_AWID (hps_0_h2f_axi_master_awid), // h2f_axi_master.awid
.h2f_AWADDR (hps_0_h2f_axi_master_awaddr), // .awaddr
.h2f_AWLEN (hps_0_h2f_axi_master_awlen), // .awlen
.h2f_AWSIZE (hps_0_h2f_axi_master_awsize), // .awsize
.h2f_AWBURST (hps_0_h2f_axi_master_awburst), // .awburst
.h2f_AWLOCK (hps_0_h2f_axi_master_awlock), // .awlock
.h2f_AWCACHE (hps_0_h2f_axi_master_awcache), // .awcache
.h2f_AWPROT (hps_0_h2f_axi_master_awprot), // .awprot
.h2f_AWVALID (hps_0_h2f_axi_master_awvalid), // .awvalid
.h2f_AWREADY (hps_0_h2f_axi_master_awready), // .awready
.h2f_WID (hps_0_h2f_axi_master_wid), // .wid
.h2f_WDATA (hps_0_h2f_axi_master_wdata), // .wdata
.h2f_WSTRB (hps_0_h2f_axi_master_wstrb), // .wstrb
.h2f_WLAST (hps_0_h2f_axi_master_wlast), // .wlast
.h2f_WVALID (hps_0_h2f_axi_master_wvalid), // .wvalid
.h2f_WREADY (hps_0_h2f_axi_master_wready), // .wready
.h2f_BID (hps_0_h2f_axi_master_bid), // .bid
.h2f_BRESP (hps_0_h2f_axi_master_bresp), // .bresp
.h2f_BVALID (hps_0_h2f_axi_master_bvalid), // .bvalid
.h2f_BREADY (hps_0_h2f_axi_master_bready), // .bready
.h2f_ARID (hps_0_h2f_axi_master_arid), // .arid
.h2f_ARADDR (hps_0_h2f_axi_master_araddr), // .araddr
.h2f_ARLEN (hps_0_h2f_axi_master_arlen), // .arlen
.h2f_ARSIZE (hps_0_h2f_axi_master_arsize), // .arsize
.h2f_ARBURST (hps_0_h2f_axi_master_arburst), // .arburst
.h2f_ARLOCK (hps_0_h2f_axi_master_arlock), // .arlock
.h2f_ARCACHE (hps_0_h2f_axi_master_arcache), // .arcache
.h2f_ARPROT (hps_0_h2f_axi_master_arprot), // .arprot
.h2f_ARVALID (hps_0_h2f_axi_master_arvalid), // .arvalid
.h2f_ARREADY (hps_0_h2f_axi_master_arready), // .arready
.h2f_RID (hps_0_h2f_axi_master_rid), // .rid
.h2f_RDATA (hps_0_h2f_axi_master_rdata), // .rdata
.h2f_RRESP (hps_0_h2f_axi_master_rresp), // .rresp
.h2f_RLAST (hps_0_h2f_axi_master_rlast), // .rlast
.h2f_RVALID (hps_0_h2f_axi_master_rvalid), // .rvalid
.h2f_RREADY (hps_0_h2f_axi_master_rready), // .rready
.f2h_axi_clk (clk_clk), // f2h_axi_clock.clk
.f2h_AWID (mm_interconnect_1_hps_0_f2h_axi_slave_awid), // f2h_axi_slave.awid
.f2h_AWADDR (mm_interconnect_1_hps_0_f2h_axi_slave_awaddr), // .awaddr
.f2h_AWLEN (mm_interconnect_1_hps_0_f2h_axi_slave_awlen), // .awlen
.f2h_AWSIZE (mm_interconnect_1_hps_0_f2h_axi_slave_awsize), // .awsize
.f2h_AWBURST (mm_interconnect_1_hps_0_f2h_axi_slave_awburst), // .awburst
.f2h_AWLOCK (mm_interconnect_1_hps_0_f2h_axi_slave_awlock), // .awlock
.f2h_AWCACHE (mm_interconnect_1_hps_0_f2h_axi_slave_awcache), // .awcache
.f2h_AWPROT (mm_interconnect_1_hps_0_f2h_axi_slave_awprot), // .awprot
.f2h_AWVALID (mm_interconnect_1_hps_0_f2h_axi_slave_awvalid), // .awvalid
.f2h_AWREADY (mm_interconnect_1_hps_0_f2h_axi_slave_awready), // .awready
.f2h_AWUSER (mm_interconnect_1_hps_0_f2h_axi_slave_awuser), // .awuser
.f2h_WID (mm_interconnect_1_hps_0_f2h_axi_slave_wid), // .wid
.f2h_WDATA (mm_interconnect_1_hps_0_f2h_axi_slave_wdata), // .wdata
.f2h_WSTRB (mm_interconnect_1_hps_0_f2h_axi_slave_wstrb), // .wstrb
.f2h_WLAST (mm_interconnect_1_hps_0_f2h_axi_slave_wlast), // .wlast
.f2h_WVALID (mm_interconnect_1_hps_0_f2h_axi_slave_wvalid), // .wvalid
.f2h_WREADY (mm_interconnect_1_hps_0_f2h_axi_slave_wready), // .wready
.f2h_BID (mm_interconnect_1_hps_0_f2h_axi_slave_bid), // .bid
.f2h_BRESP (mm_interconnect_1_hps_0_f2h_axi_slave_bresp), // .bresp
.f2h_BVALID (mm_interconnect_1_hps_0_f2h_axi_slave_bvalid), // .bvalid
.f2h_BREADY (mm_interconnect_1_hps_0_f2h_axi_slave_bready), // .bready
.f2h_ARID (mm_interconnect_1_hps_0_f2h_axi_slave_arid), // .arid
.f2h_ARADDR (mm_interconnect_1_hps_0_f2h_axi_slave_araddr), // .araddr
.f2h_ARLEN (mm_interconnect_1_hps_0_f2h_axi_slave_arlen), // .arlen
.f2h_ARSIZE (mm_interconnect_1_hps_0_f2h_axi_slave_arsize), // .arsize
.f2h_ARBURST (mm_interconnect_1_hps_0_f2h_axi_slave_arburst), // .arburst
.f2h_ARLOCK (mm_interconnect_1_hps_0_f2h_axi_slave_arlock), // .arlock
.f2h_ARCACHE (mm_interconnect_1_hps_0_f2h_axi_slave_arcache), // .arcache
.f2h_ARPROT (mm_interconnect_1_hps_0_f2h_axi_slave_arprot), // .arprot
.f2h_ARVALID (mm_interconnect_1_hps_0_f2h_axi_slave_arvalid), // .arvalid
.f2h_ARREADY (mm_interconnect_1_hps_0_f2h_axi_slave_arready), // .arready
.f2h_ARUSER (mm_interconnect_1_hps_0_f2h_axi_slave_aruser), // .aruser
.f2h_RID (mm_interconnect_1_hps_0_f2h_axi_slave_rid), // .rid
.f2h_RDATA (mm_interconnect_1_hps_0_f2h_axi_slave_rdata), // .rdata
.f2h_RRESP (mm_interconnect_1_hps_0_f2h_axi_slave_rresp), // .rresp
.f2h_RLAST (mm_interconnect_1_hps_0_f2h_axi_slave_rlast), // .rlast
.f2h_RVALID (mm_interconnect_1_hps_0_f2h_axi_slave_rvalid), // .rvalid
.f2h_RREADY (mm_interconnect_1_hps_0_f2h_axi_slave_rready), // .rready
.h2f_lw_axi_clk (clk_clk), // h2f_lw_axi_clock.clk
.h2f_lw_AWID (hps_0_h2f_lw_axi_master_awid), // h2f_lw_axi_master.awid
.h2f_lw_AWADDR (hps_0_h2f_lw_axi_master_awaddr), // .awaddr
.h2f_lw_AWLEN (hps_0_h2f_lw_axi_master_awlen), // .awlen
.h2f_lw_AWSIZE (hps_0_h2f_lw_axi_master_awsize), // .awsize
.h2f_lw_AWBURST (hps_0_h2f_lw_axi_master_awburst), // .awburst
.h2f_lw_AWLOCK (hps_0_h2f_lw_axi_master_awlock), // .awlock
.h2f_lw_AWCACHE (hps_0_h2f_lw_axi_master_awcache), // .awcache
.h2f_lw_AWPROT (hps_0_h2f_lw_axi_master_awprot), // .awprot
.h2f_lw_AWVALID (hps_0_h2f_lw_axi_master_awvalid), // .awvalid
.h2f_lw_AWREADY (hps_0_h2f_lw_axi_master_awready), // .awready
.h2f_lw_WID (hps_0_h2f_lw_axi_master_wid), // .wid
.h2f_lw_WDATA (hps_0_h2f_lw_axi_master_wdata), // .wdata
.h2f_lw_WSTRB (hps_0_h2f_lw_axi_master_wstrb), // .wstrb
.h2f_lw_WLAST (hps_0_h2f_lw_axi_master_wlast), // .wlast
.h2f_lw_WVALID (hps_0_h2f_lw_axi_master_wvalid), // .wvalid
.h2f_lw_WREADY (hps_0_h2f_lw_axi_master_wready), // .wready
.h2f_lw_BID (hps_0_h2f_lw_axi_master_bid), // .bid
.h2f_lw_BRESP (hps_0_h2f_lw_axi_master_bresp), // .bresp
.h2f_lw_BVALID (hps_0_h2f_lw_axi_master_bvalid), // .bvalid
.h2f_lw_BREADY (hps_0_h2f_lw_axi_master_bready), // .bready
.h2f_lw_ARID (hps_0_h2f_lw_axi_master_arid), // .arid
.h2f_lw_ARADDR (hps_0_h2f_lw_axi_master_araddr), // .araddr
.h2f_lw_ARLEN (hps_0_h2f_lw_axi_master_arlen), // .arlen
.h2f_lw_ARSIZE (hps_0_h2f_lw_axi_master_arsize), // .arsize
.h2f_lw_ARBURST (hps_0_h2f_lw_axi_master_arburst), // .arburst
.h2f_lw_ARLOCK (hps_0_h2f_lw_axi_master_arlock), // .arlock
.h2f_lw_ARCACHE (hps_0_h2f_lw_axi_master_arcache), // .arcache
.h2f_lw_ARPROT (hps_0_h2f_lw_axi_master_arprot), // .arprot
.h2f_lw_ARVALID (hps_0_h2f_lw_axi_master_arvalid), // .arvalid
.h2f_lw_ARREADY (hps_0_h2f_lw_axi_master_arready), // .arready
.h2f_lw_RID (hps_0_h2f_lw_axi_master_rid), // .rid
.h2f_lw_RDATA (hps_0_h2f_lw_axi_master_rdata), // .rdata
.h2f_lw_RRESP (hps_0_h2f_lw_axi_master_rresp), // .rresp
.h2f_lw_RLAST (hps_0_h2f_lw_axi_master_rlast), // .rlast
.h2f_lw_RVALID (hps_0_h2f_lw_axi_master_rvalid), // .rvalid
.h2f_lw_RREADY (hps_0_h2f_lw_axi_master_rready), // .rready
.f2h_irq_p0 (hps_0_f2h_irq0_irq), // f2h_irq0.irq
.f2h_irq_p1 (hps_0_f2h_irq1_irq) // f2h_irq1.irq
);
soc_system_fpga_only_master #(
.USE_PLI (0),
.PLI_PORT (50000),
.FIFO_DEPTHS (2)
) hps_only_master (
.clk_clk (clk_clk), // clk.clk
.clk_reset_reset (~reset_reset_n), // clk_reset.reset
.master_address (hps_only_master_master_address), // master.address
.master_readdata (hps_only_master_master_readdata), // .readdata
.master_read (hps_only_master_master_read), // .read
.master_write (hps_only_master_master_write), // .write
.master_writedata (hps_only_master_master_writedata), // .writedata
.master_waitrequest (hps_only_master_master_waitrequest), // .waitrequest
.master_readdatavalid (hps_only_master_master_readdatavalid), // .readdatavalid
.master_byteenable (hps_only_master_master_byteenable), // .byteenable
.master_reset_reset () // master_reset.reset
);
intr_capturer #(
.NUM_INTR (32)
) intr_capturer_0 (
.clk (clk_clk), // clock.clk
.rst_n (~rst_controller_reset_out_reset), // reset_sink.reset_n
.addr (mm_interconnect_0_intr_capturer_0_avalon_slave_0_address), // avalon_slave_0.address
.read (mm_interconnect_0_intr_capturer_0_avalon_slave_0_read), // .read
.rddata (mm_interconnect_0_intr_capturer_0_avalon_slave_0_readdata), // .readdata
.interrupt_in (intr_capturer_0_interrupt_receiver_irq) // interrupt_receiver.irq
);
soc_system_jtag_uart jtag_uart (
.clk (clk_clk), // clk.clk
.rst_n (~rst_controller_reset_out_reset), // reset.reset_n
.av_chipselect (mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect), // avalon_jtag_slave.chipselect
.av_address (mm_interconnect_0_jtag_uart_avalon_jtag_slave_address), // .address
.av_read_n (~mm_interconnect_0_jtag_uart_avalon_jtag_slave_read), // .read_n
.av_readdata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata), // .readdata
.av_write_n (~mm_interconnect_0_jtag_uart_avalon_jtag_slave_write), // .write_n
.av_writedata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata), // .writedata
.av_waitrequest (mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest), // .waitrequest
.av_irq (irq_mapper_receiver0_irq) // irq.irq
);
soc_system_led_pio led_pio (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_led_pio_s1_address), // s1.address
.write_n (~mm_interconnect_0_led_pio_s1_write), // .write_n
.writedata (mm_interconnect_0_led_pio_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_led_pio_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_led_pio_s1_readdata), // .readdata
.out_port (led_pio_external_connection_export) // external_connection.export
);
soc_system_onchip_memory2_0 onchip_memory2_0 (
.clk (clk_clk), // clk1.clk
.address (mm_interconnect_0_onchip_memory2_0_s1_address), // s1.address
.clken (mm_interconnect_0_onchip_memory2_0_s1_clken), // .clken
.chipselect (mm_interconnect_0_onchip_memory2_0_s1_chipselect), // .chipselect
.write (mm_interconnect_0_onchip_memory2_0_s1_write), // .write
.readdata (mm_interconnect_0_onchip_memory2_0_s1_readdata), // .readdata
.writedata (mm_interconnect_0_onchip_memory2_0_s1_writedata), // .writedata
.byteenable (mm_interconnect_0_onchip_memory2_0_s1_byteenable), // .byteenable
.reset (rst_controller_reset_out_reset), // reset1.reset
.reset_req (rst_controller_reset_out_reset_req) // .reset_req
);
soc_system_sysid_qsys sysid_qsys (
.clock (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.readdata (mm_interconnect_0_sysid_qsys_control_slave_readdata), // control_slave.readdata
.address (mm_interconnect_0_sysid_qsys_control_slave_address) // .address
);
soc_system_mm_interconnect_0 mm_interconnect_0 (
.hps_0_h2f_axi_master_awid (hps_0_h2f_axi_master_awid), // hps_0_h2f_axi_master.awid
.hps_0_h2f_axi_master_awaddr (hps_0_h2f_axi_master_awaddr), // .awaddr
.hps_0_h2f_axi_master_awlen (hps_0_h2f_axi_master_awlen), // .awlen
.hps_0_h2f_axi_master_awsize (hps_0_h2f_axi_master_awsize), // .awsize
.hps_0_h2f_axi_master_awburst (hps_0_h2f_axi_master_awburst), // .awburst
.hps_0_h2f_axi_master_awlock (hps_0_h2f_axi_master_awlock), // .awlock
.hps_0_h2f_axi_master_awcache (hps_0_h2f_axi_master_awcache), // .awcache
.hps_0_h2f_axi_master_awprot (hps_0_h2f_axi_master_awprot), // .awprot
.hps_0_h2f_axi_master_awvalid (hps_0_h2f_axi_master_awvalid), // .awvalid
.hps_0_h2f_axi_master_awready (hps_0_h2f_axi_master_awready), // .awready
.hps_0_h2f_axi_master_wid (hps_0_h2f_axi_master_wid), // .wid
.hps_0_h2f_axi_master_wdata (hps_0_h2f_axi_master_wdata), // .wdata
.hps_0_h2f_axi_master_wstrb (hps_0_h2f_axi_master_wstrb), // .wstrb
.hps_0_h2f_axi_master_wlast (hps_0_h2f_axi_master_wlast), // .wlast
.hps_0_h2f_axi_master_wvalid (hps_0_h2f_axi_master_wvalid), // .wvalid
.hps_0_h2f_axi_master_wready (hps_0_h2f_axi_master_wready), // .wready
.hps_0_h2f_axi_master_bid (hps_0_h2f_axi_master_bid), // .bid
.hps_0_h2f_axi_master_bresp (hps_0_h2f_axi_master_bresp), // .bresp
.hps_0_h2f_axi_master_bvalid (hps_0_h2f_axi_master_bvalid), // .bvalid
.hps_0_h2f_axi_master_bready (hps_0_h2f_axi_master_bready), // .bready
.hps_0_h2f_axi_master_arid (hps_0_h2f_axi_master_arid), // .arid
.hps_0_h2f_axi_master_araddr (hps_0_h2f_axi_master_araddr), // .araddr
.hps_0_h2f_axi_master_arlen (hps_0_h2f_axi_master_arlen), // .arlen
.hps_0_h2f_axi_master_arsize (hps_0_h2f_axi_master_arsize), // .arsize
.hps_0_h2f_axi_master_arburst (hps_0_h2f_axi_master_arburst), // .arburst
.hps_0_h2f_axi_master_arlock (hps_0_h2f_axi_master_arlock), // .arlock
.hps_0_h2f_axi_master_arcache (hps_0_h2f_axi_master_arcache), // .arcache
.hps_0_h2f_axi_master_arprot (hps_0_h2f_axi_master_arprot), // .arprot
.hps_0_h2f_axi_master_arvalid (hps_0_h2f_axi_master_arvalid), // .arvalid
.hps_0_h2f_axi_master_arready (hps_0_h2f_axi_master_arready), // .arready
.hps_0_h2f_axi_master_rid (hps_0_h2f_axi_master_rid), // .rid
.hps_0_h2f_axi_master_rdata (hps_0_h2f_axi_master_rdata), // .rdata
.hps_0_h2f_axi_master_rresp (hps_0_h2f_axi_master_rresp), // .rresp
.hps_0_h2f_axi_master_rlast (hps_0_h2f_axi_master_rlast), // .rlast
.hps_0_h2f_axi_master_rvalid (hps_0_h2f_axi_master_rvalid), // .rvalid
.hps_0_h2f_axi_master_rready (hps_0_h2f_axi_master_rready), // .rready
.hps_0_h2f_lw_axi_master_awid (hps_0_h2f_lw_axi_master_awid), // hps_0_h2f_lw_axi_master.awid
.hps_0_h2f_lw_axi_master_awaddr (hps_0_h2f_lw_axi_master_awaddr), // .awaddr
.hps_0_h2f_lw_axi_master_awlen (hps_0_h2f_lw_axi_master_awlen), // .awlen
.hps_0_h2f_lw_axi_master_awsize (hps_0_h2f_lw_axi_master_awsize), // .awsize
.hps_0_h2f_lw_axi_master_awburst (hps_0_h2f_lw_axi_master_awburst), // .awburst
.hps_0_h2f_lw_axi_master_awlock (hps_0_h2f_lw_axi_master_awlock), // .awlock
.hps_0_h2f_lw_axi_master_awcache (hps_0_h2f_lw_axi_master_awcache), // .awcache
.hps_0_h2f_lw_axi_master_awprot (hps_0_h2f_lw_axi_master_awprot), // .awprot
.hps_0_h2f_lw_axi_master_awvalid (hps_0_h2f_lw_axi_master_awvalid), // .awvalid
.hps_0_h2f_lw_axi_master_awready (hps_0_h2f_lw_axi_master_awready), // .awready
.hps_0_h2f_lw_axi_master_wid (hps_0_h2f_lw_axi_master_wid), // .wid
.hps_0_h2f_lw_axi_master_wdata (hps_0_h2f_lw_axi_master_wdata), // .wdata
.hps_0_h2f_lw_axi_master_wstrb (hps_0_h2f_lw_axi_master_wstrb), // .wstrb
.hps_0_h2f_lw_axi_master_wlast (hps_0_h2f_lw_axi_master_wlast), // .wlast
.hps_0_h2f_lw_axi_master_wvalid (hps_0_h2f_lw_axi_master_wvalid), // .wvalid
.hps_0_h2f_lw_axi_master_wready (hps_0_h2f_lw_axi_master_wready), // .wready
.hps_0_h2f_lw_axi_master_bid (hps_0_h2f_lw_axi_master_bid), // .bid
.hps_0_h2f_lw_axi_master_bresp (hps_0_h2f_lw_axi_master_bresp), // .bresp
.hps_0_h2f_lw_axi_master_bvalid (hps_0_h2f_lw_axi_master_bvalid), // .bvalid
.hps_0_h2f_lw_axi_master_bready (hps_0_h2f_lw_axi_master_bready), // .bready
.hps_0_h2f_lw_axi_master_arid (hps_0_h2f_lw_axi_master_arid), // .arid
.hps_0_h2f_lw_axi_master_araddr (hps_0_h2f_lw_axi_master_araddr), // .araddr
.hps_0_h2f_lw_axi_master_arlen (hps_0_h2f_lw_axi_master_arlen), // .arlen
.hps_0_h2f_lw_axi_master_arsize (hps_0_h2f_lw_axi_master_arsize), // .arsize
.hps_0_h2f_lw_axi_master_arburst (hps_0_h2f_lw_axi_master_arburst), // .arburst
.hps_0_h2f_lw_axi_master_arlock (hps_0_h2f_lw_axi_master_arlock), // .arlock
.hps_0_h2f_lw_axi_master_arcache (hps_0_h2f_lw_axi_master_arcache), // .arcache
.hps_0_h2f_lw_axi_master_arprot (hps_0_h2f_lw_axi_master_arprot), // .arprot
.hps_0_h2f_lw_axi_master_arvalid (hps_0_h2f_lw_axi_master_arvalid), // .arvalid
.hps_0_h2f_lw_axi_master_arready (hps_0_h2f_lw_axi_master_arready), // .arready
.hps_0_h2f_lw_axi_master_rid (hps_0_h2f_lw_axi_master_rid), // .rid
.hps_0_h2f_lw_axi_master_rdata (hps_0_h2f_lw_axi_master_rdata), // .rdata
.hps_0_h2f_lw_axi_master_rresp (hps_0_h2f_lw_axi_master_rresp), // .rresp
.hps_0_h2f_lw_axi_master_rlast (hps_0_h2f_lw_axi_master_rlast), // .rlast
.hps_0_h2f_lw_axi_master_rvalid (hps_0_h2f_lw_axi_master_rvalid), // .rvalid
.hps_0_h2f_lw_axi_master_rready (hps_0_h2f_lw_axi_master_rready), // .rready
.clk_0_clk_clk (clk_clk), // clk_0_clk.clk
.fpga_only_master_clk_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // fpga_only_master_clk_reset_reset_bridge_in_reset.reset
.hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
.onchip_memory2_0_reset1_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // onchip_memory2_0_reset1_reset_bridge_in_reset.reset
.fpga_only_master_master_address (fpga_only_master_master_address), // fpga_only_master_master.address
.fpga_only_master_master_waitrequest (fpga_only_master_master_waitrequest), // .waitrequest
.fpga_only_master_master_byteenable (fpga_only_master_master_byteenable), // .byteenable
.fpga_only_master_master_read (fpga_only_master_master_read), // .read
.fpga_only_master_master_readdata (fpga_only_master_master_readdata), // .readdata
.fpga_only_master_master_readdatavalid (fpga_only_master_master_readdatavalid), // .readdatavalid
.fpga_only_master_master_write (fpga_only_master_master_write), // .write
.fpga_only_master_master_writedata (fpga_only_master_master_writedata), // .writedata
.button_pio_s1_address (mm_interconnect_0_button_pio_s1_address), // button_pio_s1.address
.button_pio_s1_write (mm_interconnect_0_button_pio_s1_write), // .write
.button_pio_s1_readdata (mm_interconnect_0_button_pio_s1_readdata), // .readdata
.button_pio_s1_writedata (mm_interconnect_0_button_pio_s1_writedata), // .writedata
.button_pio_s1_chipselect (mm_interconnect_0_button_pio_s1_chipselect), // .chipselect
.dipsw_pio_s1_address (mm_interconnect_0_dipsw_pio_s1_address), // dipsw_pio_s1.address
.dipsw_pio_s1_write (mm_interconnect_0_dipsw_pio_s1_write), // .write
.dipsw_pio_s1_readdata (mm_interconnect_0_dipsw_pio_s1_readdata), // .readdata
.dipsw_pio_s1_writedata (mm_interconnect_0_dipsw_pio_s1_writedata), // .writedata
.dipsw_pio_s1_chipselect (mm_interconnect_0_dipsw_pio_s1_chipselect), // .chipselect
.intr_capturer_0_avalon_slave_0_address (mm_interconnect_0_intr_capturer_0_avalon_slave_0_address), // intr_capturer_0_avalon_slave_0.address
.intr_capturer_0_avalon_slave_0_read (mm_interconnect_0_intr_capturer_0_avalon_slave_0_read), // .read
.intr_capturer_0_avalon_slave_0_readdata (mm_interconnect_0_intr_capturer_0_avalon_slave_0_readdata), // .readdata
.jtag_uart_avalon_jtag_slave_address (mm_interconnect_0_jtag_uart_avalon_jtag_slave_address), // jtag_uart_avalon_jtag_slave.address
.jtag_uart_avalon_jtag_slave_write (mm_interconnect_0_jtag_uart_avalon_jtag_slave_write), // .write
.jtag_uart_avalon_jtag_slave_read (mm_interconnect_0_jtag_uart_avalon_jtag_slave_read), // .read
.jtag_uart_avalon_jtag_slave_readdata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata), // .readdata
.jtag_uart_avalon_jtag_slave_writedata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata), // .writedata
.jtag_uart_avalon_jtag_slave_waitrequest (mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest), // .waitrequest
.jtag_uart_avalon_jtag_slave_chipselect (mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect), // .chipselect
.led_pio_s1_address (mm_interconnect_0_led_pio_s1_address), // led_pio_s1.address
.led_pio_s1_write (mm_interconnect_0_led_pio_s1_write), // .write
.led_pio_s1_readdata (mm_interconnect_0_led_pio_s1_readdata), // .readdata
.led_pio_s1_writedata (mm_interconnect_0_led_pio_s1_writedata), // .writedata
.led_pio_s1_chipselect (mm_interconnect_0_led_pio_s1_chipselect), // .chipselect
.onchip_memory2_0_s1_address (mm_interconnect_0_onchip_memory2_0_s1_address), // onchip_memory2_0_s1.address
.onchip_memory2_0_s1_write (mm_interconnect_0_onchip_memory2_0_s1_write), // .write
.onchip_memory2_0_s1_readdata (mm_interconnect_0_onchip_memory2_0_s1_readdata), // .readdata
.onchip_memory2_0_s1_writedata (mm_interconnect_0_onchip_memory2_0_s1_writedata), // .writedata
.onchip_memory2_0_s1_byteenable (mm_interconnect_0_onchip_memory2_0_s1_byteenable), // .byteenable
.onchip_memory2_0_s1_chipselect (mm_interconnect_0_onchip_memory2_0_s1_chipselect), // .chipselect
.onchip_memory2_0_s1_clken (mm_interconnect_0_onchip_memory2_0_s1_clken), // .clken
.sysid_qsys_control_slave_address (mm_interconnect_0_sysid_qsys_control_slave_address), // sysid_qsys_control_slave.address
.sysid_qsys_control_slave_readdata (mm_interconnect_0_sysid_qsys_control_slave_readdata) // .readdata
);
soc_system_mm_interconnect_1 mm_interconnect_1 (
.hps_0_f2h_axi_slave_awid (mm_interconnect_1_hps_0_f2h_axi_slave_awid), // hps_0_f2h_axi_slave.awid
.hps_0_f2h_axi_slave_awaddr (mm_interconnect_1_hps_0_f2h_axi_slave_awaddr), // .awaddr
.hps_0_f2h_axi_slave_awlen (mm_interconnect_1_hps_0_f2h_axi_slave_awlen), // .awlen
.hps_0_f2h_axi_slave_awsize (mm_interconnect_1_hps_0_f2h_axi_slave_awsize), // .awsize
.hps_0_f2h_axi_slave_awburst (mm_interconnect_1_hps_0_f2h_axi_slave_awburst), // .awburst
.hps_0_f2h_axi_slave_awlock (mm_interconnect_1_hps_0_f2h_axi_slave_awlock), // .awlock
.hps_0_f2h_axi_slave_awcache (mm_interconnect_1_hps_0_f2h_axi_slave_awcache), // .awcache
.hps_0_f2h_axi_slave_awprot (mm_interconnect_1_hps_0_f2h_axi_slave_awprot), // .awprot
.hps_0_f2h_axi_slave_awuser (mm_interconnect_1_hps_0_f2h_axi_slave_awuser), // .awuser
.hps_0_f2h_axi_slave_awvalid (mm_interconnect_1_hps_0_f2h_axi_slave_awvalid), // .awvalid
.hps_0_f2h_axi_slave_awready (mm_interconnect_1_hps_0_f2h_axi_slave_awready), // .awready
.hps_0_f2h_axi_slave_wid (mm_interconnect_1_hps_0_f2h_axi_slave_wid), // .wid
.hps_0_f2h_axi_slave_wdata (mm_interconnect_1_hps_0_f2h_axi_slave_wdata), // .wdata
.hps_0_f2h_axi_slave_wstrb (mm_interconnect_1_hps_0_f2h_axi_slave_wstrb), // .wstrb
.hps_0_f2h_axi_slave_wlast (mm_interconnect_1_hps_0_f2h_axi_slave_wlast), // .wlast
.hps_0_f2h_axi_slave_wvalid (mm_interconnect_1_hps_0_f2h_axi_slave_wvalid), // .wvalid
.hps_0_f2h_axi_slave_wready (mm_interconnect_1_hps_0_f2h_axi_slave_wready), // .wready
.hps_0_f2h_axi_slave_bid (mm_interconnect_1_hps_0_f2h_axi_slave_bid), // .bid
.hps_0_f2h_axi_slave_bresp (mm_interconnect_1_hps_0_f2h_axi_slave_bresp), // .bresp
.hps_0_f2h_axi_slave_bvalid (mm_interconnect_1_hps_0_f2h_axi_slave_bvalid), // .bvalid
.hps_0_f2h_axi_slave_bready (mm_interconnect_1_hps_0_f2h_axi_slave_bready), // .bready
.hps_0_f2h_axi_slave_arid (mm_interconnect_1_hps_0_f2h_axi_slave_arid), // .arid
.hps_0_f2h_axi_slave_araddr (mm_interconnect_1_hps_0_f2h_axi_slave_araddr), // .araddr
.hps_0_f2h_axi_slave_arlen (mm_interconnect_1_hps_0_f2h_axi_slave_arlen), // .arlen
.hps_0_f2h_axi_slave_arsize (mm_interconnect_1_hps_0_f2h_axi_slave_arsize), // .arsize
.hps_0_f2h_axi_slave_arburst (mm_interconnect_1_hps_0_f2h_axi_slave_arburst), // .arburst
.hps_0_f2h_axi_slave_arlock (mm_interconnect_1_hps_0_f2h_axi_slave_arlock), // .arlock
.hps_0_f2h_axi_slave_arcache (mm_interconnect_1_hps_0_f2h_axi_slave_arcache), // .arcache
.hps_0_f2h_axi_slave_arprot (mm_interconnect_1_hps_0_f2h_axi_slave_arprot), // .arprot
.hps_0_f2h_axi_slave_aruser (mm_interconnect_1_hps_0_f2h_axi_slave_aruser), // .aruser
.hps_0_f2h_axi_slave_arvalid (mm_interconnect_1_hps_0_f2h_axi_slave_arvalid), // .arvalid
.hps_0_f2h_axi_slave_arready (mm_interconnect_1_hps_0_f2h_axi_slave_arready), // .arready
.hps_0_f2h_axi_slave_rid (mm_interconnect_1_hps_0_f2h_axi_slave_rid), // .rid
.hps_0_f2h_axi_slave_rdata (mm_interconnect_1_hps_0_f2h_axi_slave_rdata), // .rdata
.hps_0_f2h_axi_slave_rresp (mm_interconnect_1_hps_0_f2h_axi_slave_rresp), // .rresp
.hps_0_f2h_axi_slave_rlast (mm_interconnect_1_hps_0_f2h_axi_slave_rlast), // .rlast
.hps_0_f2h_axi_slave_rvalid (mm_interconnect_1_hps_0_f2h_axi_slave_rvalid), // .rvalid
.hps_0_f2h_axi_slave_rready (mm_interconnect_1_hps_0_f2h_axi_slave_rready), // .rready
.clk_0_clk_clk (clk_clk), // clk_0_clk.clk
.hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset.reset
.hps_only_master_clk_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // hps_only_master_clk_reset_reset_bridge_in_reset.reset
.hps_only_master_master_translator_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // hps_only_master_master_translator_reset_reset_bridge_in_reset.reset
.hps_only_master_master_address (hps_only_master_master_address), // hps_only_master_master.address
.hps_only_master_master_waitrequest (hps_only_master_master_waitrequest), // .waitrequest
.hps_only_master_master_byteenable (hps_only_master_master_byteenable), // .byteenable
.hps_only_master_master_read (hps_only_master_master_read), // .read
.hps_only_master_master_readdata (hps_only_master_master_readdata), // .readdata
.hps_only_master_master_readdatavalid (hps_only_master_master_readdatavalid), // .readdatavalid
.hps_only_master_master_write (hps_only_master_master_write), // .write
.hps_only_master_master_writedata (hps_only_master_master_writedata) // .writedata
);
soc_system_irq_mapper irq_mapper (
.clk (), // clk.clk
.reset (), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.receiver1_irq (irq_mapper_receiver1_irq), // receiver1.irq
.receiver2_irq (irq_mapper_receiver2_irq), // receiver2.irq
.sender_irq (hps_0_f2h_irq0_irq) // sender.irq
);
soc_system_irq_mapper_001 irq_mapper_001 (
.clk (), // clk.clk
.reset (), // clk_reset.reset
.sender_irq (hps_0_f2h_irq1_irq) // sender.irq
);
soc_system_irq_mapper irq_mapper_002 (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.receiver1_irq (irq_mapper_receiver1_irq), // receiver1.irq
.receiver2_irq (irq_mapper_receiver2_irq), // receiver2.irq
.sender_irq (intr_capturer_0_interrupt_receiver_irq) // sender.irq
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (1),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (~hps_0_h2f_reset_reset_n), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
// sprite priority logic module
// this module checks the playfields and sprites video status and
// determines if playfield or sprite data must be sent to the video output
// sprite/playfield priority is configurable through the bplcon2 bits
module denise_spritepriority
(
input [5:0] bplcon2, // playfields vs sprites priority setting
input [2:1] nplayfield, // playfields video status
input [7:0] nsprite, // sprites video status
output reg sprsel // sprites select signal output
);
// local signals
reg [2:0] sprcode; // sprite code
wire [3:0] sprgroup; // grouped sprites
wire pf1front; // playfield 1 is on front of sprites
wire pf2front; // playfield 2 is on front of sprites
// group sprites together
assign sprgroup[0] = (nsprite[1:0]==2'd0) ? 1'b0 : 1'b1;
assign sprgroup[1] = (nsprite[3:2]==2'd0) ? 1'b0 : 1'b1;
assign sprgroup[2] = (nsprite[5:4]==2'd0) ? 1'b0 : 1'b1;
assign sprgroup[3] = (nsprite[7:6]==2'd0) ? 1'b0 : 1'b1;
// sprites priority encoder
always @(*)
if (sprgroup[0])
sprcode = 3'd1;
else if (sprgroup[1])
sprcode = 3'd2;
else if (sprgroup[2])
sprcode = 3'd3;
else if (sprgroup[3])
sprcode = 3'd4;
else
sprcode = 3'd7;
// check if playfields are in front of sprites
assign pf1front = sprcode[2:0]>bplcon2[2:0] ? 1'b1 : 1'b0;
assign pf2front = sprcode[2:0]>bplcon2[5:3] ? 1'b1 : 1'b0;
// generate final playfield/sprite select signal
always @(*)
begin
if (sprcode[2:0]==3'd7) // if no valid sprite data, always select playfields
sprsel = 1'b0;
else if (pf1front && nplayfield[1]) // else if pf1 in front and valid data, select playfields
sprsel = 1'b0;
else if (pf2front && nplayfield[2]) // else if pf2 in front and valid data, select playfields
sprsel = 1'b0;
else // else select sprites
sprsel = 1'b1;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__XOR3_FUNCTIONAL_V
`define SKY130_FD_SC_HS__XOR3_FUNCTIONAL_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__xor3 (
X ,
A ,
B ,
C ,
VPWR,
VGND
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
// Local signals
wire xor0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X , A, B, C );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, xor0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__XOR3_FUNCTIONAL_V |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dram_sc_2_rep2.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module dram_sc_2_rep2(/*AUTOARG*/
// Outputs
dram_scbuf_data_r2_buf, dram_scbuf_ecc_r2_buf,
scbuf_dram_wr_data_r5_buf, scbuf_dram_data_vld_r5_buf,
scbuf_dram_data_mecc_r5_buf, sctag_dram_rd_req_buf,
sctag_dram_rd_dummy_req_buf, sctag_dram_rd_req_id_buf,
sctag_dram_addr_buf, sctag_dram_wr_req_buf, dram_sctag_rd_ack_buf,
dram_sctag_wr_ack_buf, dram_sctag_chunk_id_r0_buf,
dram_sctag_data_vld_r0_buf, dram_sctag_rd_req_id_r0_buf,
dram_sctag_secc_err_r2_buf, dram_sctag_mecc_err_r2_buf,
dram_sctag_scb_mecc_err_buf, dram_sctag_scb_secc_err_buf,
// Inputs
dram_scbuf_data_r2, dram_scbuf_ecc_r2, scbuf_dram_wr_data_r5,
scbuf_dram_data_vld_r5, scbuf_dram_data_mecc_r5,
sctag_dram_rd_req, sctag_dram_rd_dummy_req, sctag_dram_rd_req_id,
sctag_dram_addr, sctag_dram_wr_req, dram_sctag_rd_ack,
dram_sctag_wr_ack, dram_sctag_chunk_id_r0, dram_sctag_data_vld_r0,
dram_sctag_rd_req_id_r0, dram_sctag_secc_err_r2,
dram_sctag_mecc_err_r2, dram_sctag_scb_mecc_err,
dram_sctag_scb_secc_err
);
// dram-scbuf TOP
input [127:0] dram_scbuf_data_r2;
input [27:0] dram_scbuf_ecc_r2;
// BOTTOM
output [127:0] dram_scbuf_data_r2_buf;
output [27:0] dram_scbuf_ecc_r2_buf;
// scbuf to dram TOp
input [63:0] scbuf_dram_wr_data_r5;
input scbuf_dram_data_vld_r5;
input scbuf_dram_data_mecc_r5;
// BOTTOM
output [63:0] scbuf_dram_wr_data_r5_buf;
output scbuf_dram_data_vld_r5_buf;
output scbuf_dram_data_mecc_r5_buf;
// sctag_dramsctag signals INputs
// @ the TOp.
input sctag_dram_rd_req;
input sctag_dram_rd_dummy_req;
input [2:0] sctag_dram_rd_req_id;
input [39:5] sctag_dram_addr;
input sctag_dram_wr_req;
// sctag_dram BOTTOM
output sctag_dram_rd_req_buf;
output sctag_dram_rd_dummy_req_buf;
output [2:0] sctag_dram_rd_req_id_buf;
output [39:5] sctag_dram_addr_buf;
output sctag_dram_wr_req_buf;
// Input pins on top.
input dram_sctag_rd_ack;
input dram_sctag_wr_ack;
input [1:0] dram_sctag_chunk_id_r0;
input dram_sctag_data_vld_r0;
input [2:0] dram_sctag_rd_req_id_r0;
input dram_sctag_secc_err_r2 ;
input dram_sctag_mecc_err_r2 ;
input dram_sctag_scb_mecc_err;
input dram_sctag_scb_secc_err;
// outputs BOTTOM
output dram_sctag_rd_ack_buf;
output dram_sctag_wr_ack_buf;
output [1:0] dram_sctag_chunk_id_r0_buf;
output dram_sctag_data_vld_r0_buf;
output [2:0] dram_sctag_rd_req_id_r0_buf;
output dram_sctag_secc_err_r2_buf ;
output dram_sctag_mecc_err_r2_buf ;
output dram_sctag_scb_mecc_err_buf;
output dram_sctag_scb_secc_err_buf;
// The placement of pins on the top and bottom should be identical to
// the placement of the data column of pins in dram_l2_buf1.v
assign dram_scbuf_data_r2_buf = dram_scbuf_data_r2 ;
assign dram_scbuf_ecc_r2_buf = dram_scbuf_ecc_r2 ;
assign scbuf_dram_wr_data_r5_buf = scbuf_dram_wr_data_r5 ;
assign scbuf_dram_data_vld_r5_buf = scbuf_dram_data_vld_r5 ;
assign scbuf_dram_data_mecc_r5_buf = scbuf_dram_data_mecc_r5 ;
assign dram_sctag_rd_ack_buf = dram_sctag_rd_ack ;
assign dram_sctag_wr_ack_buf = dram_sctag_wr_ack ;
assign dram_sctag_chunk_id_r0_buf = dram_sctag_chunk_id_r0 ;
assign dram_sctag_data_vld_r0_buf = dram_sctag_data_vld_r0;
assign dram_sctag_rd_req_id_r0_buf = dram_sctag_rd_req_id_r0;
assign dram_sctag_secc_err_r2_buf = dram_sctag_secc_err_r2;
assign dram_sctag_mecc_err_r2_buf = dram_sctag_mecc_err_r2;
assign dram_sctag_scb_mecc_err_buf = dram_sctag_scb_mecc_err;
assign dram_sctag_scb_secc_err_buf = dram_sctag_scb_secc_err;
assign sctag_dram_rd_req_buf = sctag_dram_rd_req ;
assign sctag_dram_rd_dummy_req_buf = sctag_dram_rd_dummy_req ;
assign sctag_dram_rd_req_id_buf = sctag_dram_rd_req_id ;
assign sctag_dram_addr_buf = sctag_dram_addr ;
assign sctag_dram_wr_req_buf = sctag_dram_wr_req ;
endmodule
|
/*
* <file> <desc>
*
* <fulldesc>
*
* Part of the CPC2 project: http://intelligenttoasters.blog
*
* Copyright (C)2017 [email protected]
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you can find a copy here:
* https://www.gnu.org/licenses/gpl-3.0.en.html
*
*/
`timescale 1ns/1ns
`default_nettype none
module name (
);
// Wire definitions ===========================================================================
// Registers ==================================================================================
// Assignments ================================================================================
// Module connections =========================================================================
// Simulation branches and control ============================================================
// Other logic ================================================================================
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD1_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__CLKDLYINV5SD1_PP_BLACKBOX_V
/**
* clkdlyinv5sd1: Clock Delay Inverter 5-stage 0.15um length inner
* stage gate.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__clkdlyinv5sd1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV5SD1_PP_BLACKBOX_V
|
module ioddr_tester (
input wire CLK,
input wire CLKB,
output wire ERR,
output wire Q,
input wire D
);
parameter USE_PHY_ODDR = 1;
parameter USE_PHY_IDDR = 1;
parameter USE_IDELAY = 0;
parameter DDR_CLK_EDGE = "SAME_EDGE";
// Data generator
wire [1:0] g_dat;
data_generator gen (
.CLK (CLK),
.CE (1'b1),
.D1 (g_dat[0]),
.D2 (g_dat[1])
);
// Data delay
wire [1:0] d_dat;
reg [1:0] d_d1;
reg [1:0] d_d2;
always @(posedge CLK) begin
d_d1 <= {g_dat[0], d_d1[1]};
d_d2 <= {g_dat[1], d_d2[1]};
end
assign d_dat = {d_d2[0], d_d1[0]};
// ODDR
oddr_wrapper # (
.USE_PHY_ODDR (USE_PHY_ODDR),
.DDR_CLK_EDGE (DDR_CLK_EDGE)
) oddr_wrapper (
.C (CLK),
.OCE (1'b1),
.S (0),
.R (0),
.D1 (g_dat[0]),
.D2 (g_dat[1]),
.OQ (Q)
);
// IDDR
wire [1:0] r_dat;
iddr_wrapper # (
.USE_IDELAY (USE_IDELAY),
.USE_PHY_IDDR (USE_PHY_IDDR),
.DDR_CLK_EDGE (DDR_CLK_EDGE)
) iddr_wrapper (
.C (CLK),
.CB (CLKB),
.CE (1'b1),
.S (0),
.R (0),
.D (D),
.Q1 (r_dat[1]),
.Q2 (r_dat[0])
);
// Re-clock received data in OPPOSITE_EDGE MODE
wire [1:0] r_dat2;
generate if(DDR_CLK_EDGE == "OPPOSITE_EDGE") begin
reg tmp;
always @(posedge CLK)
tmp <= r_dat[0];
assign r_dat2 = {r_dat[1], tmp};
end else begin
assign r_dat2 = r_dat;
end endgenerate
// Data comparator
reg err_r;
always @(posedge CLK)
err_r <= r_dat2 != d_dat;
// Error pulse prolonger
reg [20:0] cnt;
wire err = !cnt[20];
always @(posedge CLK)
if (err_r) cnt <= 1 << 24;
else if (err) cnt <= cnt - 1;
else cnt <= cnt;
assign ERR = err;
endmodule
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2014, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//
//-------------------------------------------------------------------
//
// Filename : fetch_ref_luma.v
// Author : Yufeng Bai
// Email : [email protected]
//
//-------------------------------------------------------------------
//
// Modified : 2015-08-20 by HLL
// Description : fme_ref_x and fime_ref_x logic corrected
// Modified : 2015-09-02 by HLL
// Description : rotate by sys_start_i
//
//-------------------------------------------------------------------
`include "enc_defines.v"
module fetch_ref_luma (
clk ,
rstn ,
sysif_start_i ,
sysif_total_y_i ,
fime_cur_y_i ,
fime_ref_x_i ,
fime_ref_y_i ,
fime_ref_rden_i ,
fime_ref_pel_o ,
fme_cur_y_i ,
fme_ref_x_i ,
fme_ref_y_i ,
fme_ref_rden_i ,
fme_ref_pel_o ,
ext_load_done_i ,
ext_load_data_i ,
ext_load_addr_i ,
ext_load_valid_i
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input [1-1:0] clk ; // clk signal
input [1-1:0] rstn ; // asynchronous reset
input sysif_start_i ;
input [`PIC_Y_WIDTH-1:0] sysif_total_y_i ;
input [`PIC_Y_WIDTH-1:0] fime_cur_y_i ;
input [8-1:0] fime_ref_x_i ; // fime ref x
input [8-1:0] fime_ref_y_i ; // fime ref y
input [1-1:0] fime_ref_rden_i ; // fime ref read enable
output [64*`PIXEL_WIDTH-1:0] fime_ref_pel_o ; // fime ref pixel
input [`PIC_Y_WIDTH-1:0] fme_cur_y_i ;
input [7-1:0] fme_ref_x_i ; // fme ref x
input [7-1:0] fme_ref_y_i ; // fme ref y
input [1-1:0] fme_ref_rden_i ; // fme ref read enable
output [64*`PIXEL_WIDTH-1:0] fme_ref_pel_o ; // fme ref pixel
input [1-1:0] ext_load_done_i ; // load current lcu done
input [96*`PIXEL_WIDTH-1:0] ext_load_data_i ; // load current lcu data
input [7-1:0] ext_load_addr_i ;
input [1-1:0] ext_load_valid_i ; // load current lcu data valid
// ********************************************
//
// WIRE / REG DECLARATION
//
// ********************************************
reg [2-1:0] rotate_cnt ;
//reg [7-1:0] ext_load_addr_i ;
reg [1-1:0] ref_luma_00_wen ;
reg [7-1:0] ref_luma_00_waddr ;
reg [96*`PIXEL_WIDTH-1:0] ref_luma_00_wdata ;
reg [1-1:0] ref_luma_00_rden ;
reg [7-1:0] ref_luma_00_raddr ;
wire [96*`PIXEL_WIDTH-1:0] ref_luma_00_rdata ;
reg [1-1:0] ref_luma_01_wen ;
reg [7-1:0] ref_luma_01_waddr ;
reg [96*`PIXEL_WIDTH-1:0] ref_luma_01_wdata ;
reg [1-1:0] ref_luma_01_rden ;
reg [7-1:0] ref_luma_01_raddr ;
wire [96*`PIXEL_WIDTH-1:0] ref_luma_01_rdata ;
reg [1-1:0] ref_luma_02_wen ;
reg [7-1:0] ref_luma_02_waddr ;
reg [96*`PIXEL_WIDTH-1:0] ref_luma_02_wdata ;
reg [1-1:0] ref_luma_02_rden ;
reg [7-1:0] ref_luma_02_raddr ;
wire [96*`PIXEL_WIDTH-1:0] ref_luma_02_rdata ;
reg [96*`PIXEL_WIDTH-1:0] fime_ref_pel ;
reg [96*`PIXEL_WIDTH-1:0] fme_ref_pel ;
reg [7-1:0] fime_ref_y ; // fime ref y
reg [7-1:0] fme_ref_y ; // fme ref y
reg [8-1:0] fime_ref_x ; // fime ref x
reg [8-1:0] fme_ref_x ; // fime ref x
// ********************************************
//
// Alias Logic
//
// ********************************************
assign fime_ref_pel_o = fime_ref_pel[92*`PIXEL_WIDTH-1 : 28*`PIXEL_WIDTH];
assign fme_ref_pel_o = fme_ref_pel [96*`PIXEL_WIDTH-1 : 32*`PIXEL_WIDTH];
// ********************************************
//
// Sequential Logic
//
// ********************************************
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
fime_ref_x <= 'd0;
fme_ref_x <= 'd0;
end
else begin
fime_ref_x <= fime_ref_x_i;
fme_ref_x <= fme_ref_x_i;
end
end
always @ (posedge clk or negedge rstn) begin
if( !rstn )
rotate_cnt <= 0 ;
else if( sysif_start_i ) begin
if( rotate_cnt == 2 )
rotate_cnt <= 0 ;
else begin
rotate_cnt <= rotate_cnt + 1 ;
end
end
end
/*
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
ext_load_addr <= 'd0;
end
else if (ext_load_done_i) begin
ext_load_addr <= 'd0;
end
else if (ext_load_valid_i) begin
ext_load_addr <= ext_load_addr + 'd1;
end
end
*/
// ********************************************
//
// Sel Logic
//
// ********************************************
always @ (*) begin
if(fime_cur_y_i == 'd0)
fime_ref_y = (fime_ref_y_i < 'd12) ? 'd0 : (fime_ref_y_i - 12);
else if(fime_cur_y_i == sysif_total_y_i)
fime_ref_y = (fime_ref_y_i >= 'd76) ? 'd79 : (fime_ref_y_i + 4);
else
fime_ref_y = fime_ref_y_i + 4;
end
always @ (*) begin
if(fme_cur_y_i == 'd0)
fme_ref_y = (fme_ref_y_i < 'd16) ? 'd0 : (fme_ref_y_i - 16);
else if(fme_cur_y_i == sysif_total_y_i)
fme_ref_y = (fme_ref_y_i >= 'd80) ? 'd79 : fme_ref_y_i;
else
fme_ref_y = fme_ref_y_i;
end
always @ (*) begin
case(rotate_cnt)
'd0: begin
ref_luma_00_wen = ext_load_valid_i;
ref_luma_00_waddr = ext_load_addr_i;
ref_luma_00_wdata = ext_load_data_i;
ref_luma_00_rden = 'b0;
ref_luma_00_raddr = 'b0;
ref_luma_01_wen = 'b0;
ref_luma_01_waddr = 'b0;
ref_luma_01_wdata = 'b0;
ref_luma_01_rden = fme_ref_rden_i;
ref_luma_01_raddr = fme_ref_y;
ref_luma_02_wen = 'b0;
ref_luma_02_waddr = 'b0;
ref_luma_02_wdata = 'b0;
ref_luma_02_rden = fime_ref_rden_i;
ref_luma_02_raddr = fime_ref_y;
fime_ref_pel = ref_luma_02_rdata << ({fime_ref_x,3'b0});
fme_ref_pel = ref_luma_01_rdata << ({fme_ref_x,3'b0} );
end
'd1: begin
ref_luma_00_wen = 'b0;
ref_luma_00_waddr = 'b0;
ref_luma_00_wdata = 'b0;
ref_luma_00_rden = fime_ref_rden_i;
ref_luma_00_raddr = fime_ref_y;
ref_luma_01_wen = ext_load_valid_i;
ref_luma_01_waddr = ext_load_addr_i;
ref_luma_01_wdata = ext_load_data_i;
ref_luma_01_rden = 'b0;
ref_luma_01_raddr = 'b0;
ref_luma_02_wen = 'b0;
ref_luma_02_waddr = 'b0;
ref_luma_02_wdata = 'b0;
ref_luma_02_rden = fme_ref_rden_i;
ref_luma_02_raddr = fme_ref_y;
fime_ref_pel = ref_luma_00_rdata << ({fime_ref_x,3'b0});
fme_ref_pel = ref_luma_02_rdata << ({fme_ref_x,3'b0} );
end
'd2: begin
ref_luma_00_wen = 'b0;
ref_luma_00_waddr = 'b0;
ref_luma_00_wdata = 'b0;
ref_luma_00_rden = fme_ref_rden_i;
ref_luma_00_raddr = fme_ref_y;
ref_luma_01_wen = 'b0;
ref_luma_01_waddr = 'b0;
ref_luma_01_wdata = 'b0;
ref_luma_01_rden = fime_ref_rden_i;
ref_luma_01_raddr = fime_ref_y;
ref_luma_02_wen = ext_load_valid_i;
ref_luma_02_waddr = ext_load_addr_i;
ref_luma_02_wdata = ext_load_data_i;
ref_luma_02_rden = 'b0;
ref_luma_02_raddr = 'b0;
fime_ref_pel = ref_luma_01_rdata << ({fime_ref_x,3'b0});
fme_ref_pel = ref_luma_00_rdata << ({fme_ref_x,3'b0} );
end
default: begin
ref_luma_00_wen = 'b0;
ref_luma_00_waddr = 'b0;
ref_luma_00_wdata = 'b0;
ref_luma_00_rden = 'b0;
ref_luma_00_raddr = 'b0;
ref_luma_01_wen = 'b0;
ref_luma_01_waddr = 'b0;
ref_luma_01_wdata = 'b0;
ref_luma_01_rden = 'b0;
ref_luma_01_raddr = 'b0;
ref_luma_02_wen = 'b0;
ref_luma_02_waddr = 'b0;
ref_luma_02_wdata = 'b0;
ref_luma_02_rden = 'b0;
ref_luma_02_raddr = 'b0;
fime_ref_pel = 'b0;
fme_ref_pel = 'b0;
end
endcase
end
// ********************************************
//
// mem wrapper
//
// ********************************************
wrap_ref_luma ref_luma_00(
.clk (clk ),
.rstn (rstn ),
.wrif_en_i (ref_luma_00_wen ),
.wrif_addr_i (ref_luma_00_waddr ),
.wrif_data_i (ref_luma_00_wdata ),
.rdif_en_i (ref_luma_00_rden ),
.rdif_addr_i (ref_luma_00_raddr ),
.rdif_pdata_o (ref_luma_00_rdata )
);
wrap_ref_luma ref_luma_01(
.clk (clk ),
.rstn (rstn ),
.wrif_en_i (ref_luma_01_wen ),
.wrif_addr_i (ref_luma_01_waddr ),
.wrif_data_i (ref_luma_01_wdata ),
.rdif_en_i (ref_luma_01_rden ),
.rdif_addr_i (ref_luma_01_raddr ),
.rdif_pdata_o (ref_luma_01_rdata )
);
wrap_ref_luma ref_luma_02(
.clk (clk ),
.rstn (rstn ),
.wrif_en_i (ref_luma_02_wen ),
.wrif_addr_i (ref_luma_02_waddr ),
.wrif_data_i (ref_luma_02_wdata ),
.rdif_en_i (ref_luma_02_rden ),
.rdif_addr_i (ref_luma_02_raddr ),
.rdif_pdata_o (ref_luma_02_rdata )
);
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 5
(* X_CORE_INFO = "axi_protocol_converter_v2_1_axi_protocol_converter,Vivado 2015.1" *)
(* CHECK_LICENSE_TYPE = "week1_auto_pc_0,axi_protocol_converter_v2_1_axi_protocol_converter,{}" *)
(* CORE_GENERATION_INFO = "week1_auto_pc_0,axi_protocol_converter_v2_1_axi_protocol_converter,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=2,C_S_AXI_PROTOCOL=1,C_IGNORE_ID=0,C_AXI_ID_WIDTH=12,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module week1_auto_pc_0 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [3 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
input wire [11 : 0] s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [3 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(1),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(s_axi_wid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(12'H000),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(12'H000),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/*
* Copyright 2017 Google Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
module pcounter(
input rst,
input clk,
input enable,
input jump,
input out_enable,
input [ADDRESS_WIDTH-1 : 0] bus_in,
output [ADDRESS_WIDTH-1 : 0] bus_out);
parameter ADDRESS_WIDTH = 4;
reg [ADDRESS_WIDTH-1 : 0] counter;
assign bus_out = (out_enable) ? counter : 0;
always @(posedge clk) begin
if (rst) begin
counter <= 0;
end else begin
if (enable) begin
counter <= counter + 1;
end else if (jump) begin
counter <= bus_in;
end
end
end
endmodule
|
`timescale 1ns/10ps // THIS DEFINES A UNIT TIME FOR THE TEST BENCH AND ITS PRECISION //
module alu32_testbench();
reg [31:0] a, b; // DECLARING I/O PORTS AND ALSO INTERNAL WIRES //
wire [31:0] d;
reg [2:0] S, Stm[0:31];
reg Cin;
reg [31:0] dontcare, str[0:31], ref[0:31], stma[0:31], stmb[0:31];
reg Vstr[0:31], Vref[0:31], Coutstm[0:31], Coutstr[0:31], Coutref[0:31], Cinstm[0:31];
integer ntests, error, k, i; // VARIABLES NOT RELATED TO ALU I/O , BUT REQUIRED FOR TESTBENCH //
alu32 dut(.a(a), .b(b), .d(d), .Cin(Cin), .Cout(Cout), .V(V), .S(S)); // DECLARES THE MODULE BEING TESTED ALONG WITH ITS I/O PORTS //
////////////////////////////////////////// //////////////////////////////////////////
///////// EXPECTED VALUES //////////////// ////////// INPUTS TO ALU /////////
////////////////////////////////////////// //////////////////////////////////////////
initial begin //LOADING THE TEST REGISTERS WITH INPUTS AND EXPECTED VALUES//
ref[0] = 32'h00000000; Vref[0] = 0; Coutref[0] = 0; Stm[0] = 3'b100; stma[0] = 32'h00000000; stmb[0] = 32'h00000000; Cinstm[0] = 0; // Test or //
ref[1] = 32'h00000000; Vref[1] = 0; Coutref[1] = 0; Stm[1] = 3'b100; stma[1] = 32'h00000000; stmb[1] = 32'h00000000; Cinstm[1] = 0;
ref[2] = 32'hFFFFFFFF; Vref[2] = 0; Coutref[2] = 0; Stm[2] = 3'b010; stma[2] = 32'hFFFFFFFF; stmb[2] = 32'h00000000; Cinstm[2] = 0; // Test Carry //
ref[3] = 32'h00000000; Vref[3] = 0; Coutref[3] = 1; Stm[3] = 3'b010; stma[3] = 32'hFFFFFFFF; stmb[3] = 32'h00000000; Cinstm[3] = 1;
ref[4] = 32'h7FFFFFFF; Vref[4] = 0; Coutref[4] = 0; Stm[4] = 3'b010; stma[4] = 32'h7FFFFFFF; stmb[4] = 32'h00000000; Cinstm[4] = 0;
ref[5] = 32'h80000000; Vref[5] = 1; Coutref[5] = 0; Stm[5] = 3'b010; stma[5] = 32'h7FFFFFFF; stmb[5] = 32'h00000000; Cinstm[5] = 1;
ref[6] = 32'h00100166; Vref[6] = 1'bx; Coutref[6] = 1'bx; Stm[6] = 3'b000; stma[6] = 32'hF01010CA; stmb[6] = 32'hF00011AC; Cinstm[6] = 0; // Test xor //
ref[7] = 32'h0EEF9997; Vref[7] = 1'bx; Coutref[7] = 1'bx; Stm[7] = 3'b001; stma[7] = 32'hF101CBA9; stmb[7] = 32'h0011ADC1; Cinstm[7] = 0; // Test xnor //
ref[8] = 32'h0000FFFF; Vref[8] = 1'bx; Coutref[8] = 1'bx; Stm[8] = 3'b110; stma[8] = 32'hFFFFFFFF; stmb[8] = 32'h0000FFFF; Cinstm[8] = 0; // Test and //
ref[9] = 32'hF111EFE9; Vref[9] = 1'bx; Coutref[9] = 1'bx; Stm[9] = 3'b100; stma[9] = 32'hF101CBA9; stmb[9] = 32'h0011ADC1; Cinstm[9] = 0; // Test or //
ref[10] = 32'h64424220; Vref[10] = 1'bx; Coutref[10] = 1'bx; Stm[10] = 3'b010; stma[10] = 32'h31312020; stmb[10] = 32'h33112200; Cinstm[10] = 0; // Test add //
ref[11] = 32'h64424221; Vref[11] = 1'bx; Coutref[11] = 1'bx; Stm[11] = 3'b011; stma[11] = 32'h31312020; stmb[11] = 32'hCCEEDDFF; Cinstm[11] = 1; // Test sub //
ref[12] = 32'h00000001; Vref[12] = 1'bx; Coutref[12] = 1'bx; Stm[12] = 3'b010; stma[12] = 32'h00000000; stmb[12] = 32'h00000000; Cinstm[12] = 1; // Test Carry //
ref[13] = 32'h0000000F; Vref[13] = 1'bx; Coutref[13] = 1'bx; Stm[13] = 3'b010; stma[13] = 32'h0000000F; stmb[13] = 32'h00000000; Cinstm[13] = 0;
ref[14] = 32'h00000010; Vref[14] = 1'bx; Coutref[14] = 1'bx; Stm[14] = 3'b010; stma[14] = 32'h0000000F; stmb[14] = 32'h00000000; Cinstm[14] = 1;
ref[15] = 32'h000000FF; Vref[15] = 1'bx; Coutref[15] = 1'bx; Stm[15] = 3'b010; stma[15] = 32'h000000FF; stmb[15] = 32'h00000000; Cinstm[15] = 0;
ref[16] = 32'h00000100; Vref[16] = 1'bx; Coutref[16] = 1'bx; Stm[16] = 3'b010; stma[16] = 32'h000000FF; stmb[16] = 32'h00000000; Cinstm[16] = 1;
ref[17] = 32'h00000FFF; Vref[17] = 1'bx; Coutref[17] = 1'bx; Stm[17] = 3'b010; stma[17] = 32'h00000FFF; stmb[17] = 32'h00000000; Cinstm[17] = 0;
ref[18] = 32'h00001000; Vref[18] = 1'bx; Coutref[18] = 1'bx; Stm[18] = 3'b010; stma[18] = 32'h00000FFF; stmb[18] = 32'h00000000; Cinstm[18] = 1;
ref[19] = 32'h0000FFFF; Vref[19] = 1'bx; Coutref[19] = 1'bx; Stm[19] = 3'b010; stma[19] = 32'h0000FFFF; stmb[19] = 32'h00000000; Cinstm[19] = 0;
ref[20] = 32'h00010000; Vref[20] = 1'bx; Coutref[20] = 1'bx; Stm[20] = 3'b010; stma[20] = 32'h0000FFFF; stmb[20] = 32'h00000000; Cinstm[20] = 1;
ref[21] = 32'h000FFFFF; Vref[21] = 1'bx; Coutref[21] = 1'bx; Stm[21] = 3'b010; stma[21] = 32'h000FFFFF; stmb[21] = 32'h00000000; Cinstm[21] = 0;
ref[22] = 32'h00100000; Vref[22] = 1'bx; Coutref[22] = 1'bx; Stm[22] = 3'b010; stma[22] = 32'h000FFFFF; stmb[22] = 32'h00000000; Cinstm[22] = 1;
ref[23] = 32'h00FFFFFF; Vref[23] = 1'bx; Coutref[23] = 1'bx; Stm[23] = 3'b010; stma[23] = 32'h00FFFFFF; stmb[23] = 32'h00000000; Cinstm[23] = 0;
ref[24] = 32'h01000000; Vref[24] = 1'bx; Coutref[24] = 1'bx; Stm[24] = 3'b010; stma[24] = 32'h00FFFFFF; stmb[24] = 32'h00000000; Cinstm[24] = 1;
ref[25] = 32'h0FFFFFFF; Vref[25] = 1'bx; Coutref[25] = 1'bx; Stm[25] = 3'b010; stma[25] = 32'h0FFFFFFF; stmb[25] = 32'h00000000; Cinstm[25] = 0;
ref[26] = 32'h10000000; Vref[26] = 1'bx; Coutref[26] = 1'bx; Stm[26] = 3'b010; stma[26] = 32'h0FFFFFFF; stmb[26] = 32'h00000000; Cinstm[26] = 1;
ref[27] = 32'h00000000; Vref[27] = 1'bx; Coutref[27] = 1'bx; Stm[27] = 3'b101; stma[27] = 32'hFFFFFFFF; stmb[27] = 32'h0000FFFF; Cinstm[27] = 0; // Test nor //
ref[28] = 32'hx; Vref[28] = 0; Coutref[28] = 0; Stm[28] = 3'b010; stma[28] = 32'h00000000; stmb[28] = 32'h00000000; Cinstm[28] = 0; // Test Cout, V //
ref[29] = 32'hx; Vref[29] = 0; Coutref[29] = 1; Stm[29] = 3'b010; stma[29] = 32'hFFFFFFFF; stmb[29] = 32'hFFFFFFFF; Cinstm[29] = 0;
ref[30] = 32'hx; Vref[30] = 1; Coutref[30] = 1; Stm[30] = 3'b010; stma[30] = 32'h80000000; stmb[30] = 32'h80000000; Cinstm[30] = 0;
ref[31] = 32'hx; Vref[31] = 1; Coutref[31] = 0; Stm[31] = 3'b010; stma[31] = 32'h40000000; stmb[31] = 32'h40000000; Cinstm[31] = 0;
dontcare = 32'hx;
ntests = 32;
$timeformat(-9,1,"ns",12);
end
initial begin
error = 0;
for (k=0; k<= ntests; k=k+1) // LOOPING THROUGH ALL THE TEST VECTORS AND ASSIGNING IT TO THE ALU INPUTS EVERY 8ns //
begin
S = Stm[k]; a = stma[k] ; b = stmb[k]; Cin = Cinstm[k];
#20 str[k] = d; Vstr[k] = V; Coutstr[k] = Cout; // #20 IS 8 ns DELAY FOR ASSIGNING THE OUTPUT TO THE REFERENCE REGISTERS //
if ( S == 3'b000 )
$display ("----- TEST FOR A XOR B -----");
if ( S == 3'b001 )
$display ("----- TEST FOR A XNOR B -----");
if ( S == 3'b010 )
$display ("----- TEST FOR A + B/ CARRY CHAIN -----");
if ( S == 3'b011 )
$display ("----- TEST FOR A - B -----");
if ( S == 3'b100 )
$display ("----- TEST FOR A OR B -----");
if ( S == 3'b101 )
$display ("----- TEST FOR A NOR B -----");
if ( S == 3'b110 )
$display ("----- TEST FOR A AND B -----");
$display ("Time=%t \n S=%b \n Cin=%b \n a=%b \n b=%b \n d=%b \n ref=%b \n Cout=%b \n CoutRef=%b \n V=%b \n Vref=%b \n",$realtime, S, Cin, a, b, d, ref[k], Cout, Coutref[k], V, Vref[k]);
// THIS CONTROL BLOCK CHECKS FOR ERRORS BY COMPARING YOUR OUTPUT WITH THE EXPECTED OUTPUTS AND INCREMENTS "error" IN CASE OF ERROR //
if (( (ref[k] !== str[k]) && (ref[k] !== dontcare) ) || ( (Vref[k] !== Vstr[k]) && (Vref[k] !== 1'bx) ) || ( (Coutref[k] !== Coutstr[k]) && (Coutref[k] !== 1'bx) ) )
begin
$display ("-------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
if ( error == 0)
$display("---------YOU DID IT!! SIMULATION SUCCESFULLY FINISHED----------");
if ( error != 0)
$display("---------------ERRORS. Mismatches Have Occured, sorry------------------");
$display(" Number Of Errors = %d", error);
$display(" Total Test numbers = %d", ntests);
$display(" Total number of correct operations = %d", (ntests-error));
end
endmodule
|
`timescale 1ns/10ps
`include "defines.v"
module pc_trace (
`ifdef DEBUG
output reg [ 2:0] old_zet_st,
output reg [19:0] dat,
output reg new_pc,
output reg st,
output reg stb,
output ack,
output [ 4:0] pack,
output addr_st,
`endif
// PAD signals
output trx_,
input clk,
input rst,
input [19:0] pc,
input [ 2:0] zet_st,
output reg block
);
`ifndef DEBUG
// Registers and nets
reg [19:0] dat;
reg [ 2:0] old_zet_st;
reg new_pc;
reg st;
reg stb;
wire ack;
`endif
wire op_st;
wire rom;
// Module instantiations
send_addr ser0 (
`ifdef DEBUG
.pack (pack),
.st (addr_st),
`endif
.trx_ (trx_),
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_dat_i (dat),
.wb_we_i (stb),
.wb_stb_i (stb),
.wb_cyc_i (stb),
.wb_ack_o (ack)
);
// Continous assignments
assign op_st = (zet_st == 3'b0);
assign rom = pc[19:16]==4'hf || pc[19:16]==4'hc;
// Behaviour
// old_zet_st
always @(posedge clk)
old_zet_st <= rst ? 3'b0 : zet_st;
// new_pc
always @(posedge clk)
new_pc <= rst ? 1'b0
: (op_st ? (zet_st!=old_zet_st && !rom) : 1'b0);
// block
always @(posedge clk)
block <= rst ? 1'b0
: (new_pc ? (st & !ack) : (ack ? 1'b0 : block));
// dat
always @(posedge clk)
dat <= rst ? 20'h0
: ((new_pc & !st) ? pc : (ack ? pc : dat));
// stb
always @(posedge clk)
stb <= rst ? 1'b0 : (ack ? 1'b0 : (st | new_pc));
// st
always @(posedge clk)
st <= rst ? 1'b0
: (st ? (ack ? (new_pc | block) : 1'b1) : new_pc);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFXTP_BEHAVIORAL_V
`define SKY130_FD_SC_MS__DFXTP_BEHAVIORAL_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ms__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dfxtp (
Q ,
CLK,
D
);
// Module ports
output Q ;
input CLK;
input D ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire CLK_delayed;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_ms__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFXTP_BEHAVIORAL_V |
`timescale 1ns/1ps
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2003 Xilinx, Inc.
// All Rights Reserved
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 12.2
// \ \
// / / Filename: async_fifo.v
// /___/ /\ Orig Date: 07/20/2004
// \ \ / \ Author: Brian Philofsky
// \___\/\___\ Last Updated: 07/19/10
//
// Device: All FPGA
// Supported Synthesis Tools: Synplicity or XST
// Design Name: async_fifo
// Purpose:
// The following is paramatizable RTL code for an asynchronous FIFO
// which can be simulated in any Verilog 2001 compliant simulator and
// implemented in XST or Synplicity synthesis tools targeting Xilinx FPGAs.
// This code is provided as a reference for a possible FIFO implementation and
// should be properly validated by the end user before using in any FPGA design.
// In other words, use at your own risk.
//
// Version: 0.6
//
// Version 0.1 - Initial Code Created
// Version 0.2 - Redesigned addressing and flags
// Version 0.3 - Fixed Dist RAM issues and made almost flags active when empty/full
// Version 0.4 - Added `define and `ifdef for Synplicity added
// Version 0.5 - Added wr_ack output
// Version 0.6 - Removed Synplicity `ifdef since it seems it is no longer needed.
// Updated port declarations to ANSI style.
////////////////////////////////////////////////////////////////////////////////
module async_fifo #(
parameter DEVICE = "7SERIES", // "SPARTAN6", "VIRTEX5","VIRTEX6" or "7SERIES"
FIFO_WIDTH = 144, // Set the FIFO data width (number of bits)
FIFO_DEPTH = 12, // Express FIFO depth by power of 2 or number of address bits for the FIFO RAM
// i.e. 9 -> 2**9 -> 512 words
FIRST_WORD_FALL_THROUGH = "FALSE",
ALMOST_EMPTY_OFFSET = 9'd32,
ALMOST_FULL_OFFSET = 9'd121,
USE_PROG_FULL_EMPTY = "FALSE", // "TRUE"/"FALSE" Using the programmable full/empty feature can have
// a negative affect on performnace and area.
FLAG_GENERATION = "FAST", // "FAST" or "SAFE"
// OPTIMIZE = "PERFORMANCE", // "PERFORMANCE" or "POWER"
FIFO_RAM_TYPE = "BLOCK_RAM") // "AUTO", "HARDFIFO", "BLOCKRAM" or "DISTRIBUTED_RAM"
( input [FIFO_WIDTH-1:0] din,
input rd_clk,
input rd_en,
input rst,
input wr_clk,
input wr_en,
output [FIFO_WIDTH-1:0] dout,
output empty,
output full,
// output almost_empty,
// output almost_full,
output reg wr_ack,
output prog_empty,
output prog_full
);
initial begin // Note: In XST will error if depth violated. In Synplify, will be ignored with a warning. xilinx-brianp
if (FIFO_RAM_TYPE=="HARDFIFO" && DEVICE=="SPARTAN6") begin
$display("Error: Instance %m FIFO_RAM_TYPE set to %s and DEVICE set to %s. Spartan-6 does not support a HARDFIFO option..", FIFO_RAM_TYPE, DEVICE);
$finish;
end
end
genvar i;
generate
if ((FIFO_RAM_TYPE=="HARDFIFO") || (FIFO_RAM_TYPE=="AUTO" && DEVICE!="SPARTAN6" && (FIFO_DEPTH<14) && (FIFO_DEPTH>5 || (FIFO_DEPTH<=6 && FIFO_WIDTH<=8)))) begin: hard_fifo
initial begin // Note: In XST will error if depth violated. In Synplify, will be ignored with a warning. xilinx-brianp
if (FIFO_DEPTH > 13) begin
$display("Attribute Out of Range Error: Instance %m FIFO_DEPTH must be limited to less than 8192. Currently set to %d.", FIFO_DEPTH);
$finish;
end
end
localparam sub_fifo_width = (FIFO_DEPTH<=9) ? 72 :
(FIFO_DEPTH<=10) ? 36 :
(FIFO_DEPTH<=11) ? 18 :
(FIFO_DEPTH<=12) ? 9 :
4;
localparam num_FIFO_blocks = ((FIFO_WIDTH%sub_fifo_width)==0) ? FIFO_WIDTH/sub_fifo_width :
(FIFO_WIDTH/sub_fifo_width)+1;
wire [num_FIFO_blocks-1:0] almostempties, almostfulls, empties, fulls;
wire [num_FIFO_blocks-1:0] wrerrs, rderrs;
for (i=FIFO_WIDTH; i > 0; i=i-sub_fifo_width)
begin: fifo_gen
if ((i <= (sub_fifo_width/2)) && (sub_fifo_width != 4)) begin: fifo18_inst
// FIFO_DUALCLOCK_MACRO: Dual Clock First-In, First-Out (FIFO) RAM Buffer
// Virtex-6
// Xilinx HDL Language Template, version 12.1
FIFO_DUALCLOCK_MACRO #(
.ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET), // Sets the almost empty threshold
.ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET), // Sets almost full threshold
.DATA_WIDTH(i), // Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb")
.DEVICE(DEVICE), // Target device: "VIRTEX5", "VIRTEX6"
.FIFO_SIZE ("18Kb"), // Target BRAM: "18Kb" or "36Kb"
.FIRST_WORD_FALL_THROUGH (FIRST_WORD_FALL_THROUGH) // Sets the FIFO FWFT to "TRUE" or "FALSE"
) FIFO_DUALCLOCK_MACRO_inst (
.ALMOSTEMPTY(almostempties[0]), // Output almost empty
.ALMOSTFULL(almostfulls[0]), // Output almost full
.DO(dout[i-1:0]), // Output data
.EMPTY(empties[0]), // Output empty
.FULL(fulls[0]), // Output full
.RDCOUNT(), // Output read count
.RDERR(rderrs[0]), // Output read error
.WRCOUNT(), // Output write count
.WRERR(wrerrs[0]), // Output write error
.DI(din[i-1:0]), // Input data
.RDCLK(rd_clk), // Input read clock
.RDEN(rd_en), // Input read enable
.RST(rst), // Input reset
.WRCLK(wr_clk), // Input write clock
.WREN(wr_en) // Input write enable
);
// End of FIFO_DUALCLOCK_MACRO_inst instantiation
end else if (i > sub_fifo_width) begin: fifo36_1_inst
// FIFO_DUALCLOCK_MACRO: Dual Clock First-In, First-Out (FIFO) RAM Buffer
// Virtex-6
// Xilinx HDL Language Template, version 12.1
FIFO_DUALCLOCK_MACRO #(
.ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET), // Sets the almost empty threshold
.ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET), // Sets almost full threshold
.DATA_WIDTH(sub_fifo_width), // Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb")
.DEVICE(DEVICE), // Target device: "VIRTEX5", "VIRTEX6"
.FIFO_SIZE ("36Kb"), // Target BRAM: "18Kb" or "36Kb"
.FIRST_WORD_FALL_THROUGH (FIRST_WORD_FALL_THROUGH) // Sets the FIFO FWFT to "TRUE" or "FALSE"
) FIFO_DUALCLOCK_MACRO_inst (
.ALMOSTEMPTY(almostempties[(i/sub_fifo_width)-1]), // Output almost empty
.ALMOSTFULL(almostfulls[(i/sub_fifo_width)-1]), // Output almost full
.DO(dout[i-1:i-sub_fifo_width]), // Output data
.EMPTY(empties[(i/sub_fifo_width)-1]), // Output empty
.FULL(fulls[(i/sub_fifo_width)-1]), // Output full
.RDCOUNT(), // Output read count
.RDERR(rderrs[(i/sub_fifo_width)-1]), // Output read error
.WRCOUNT(), // Output write count
.WRERR(wrerrs[(i/sub_fifo_width)-1]), // Output write error
.DI(din[i-1:i-sub_fifo_width]), // Input data
.RDCLK(rd_clk), // Input read clock
.RDEN(rd_en), // Input read enable
.RST(rst), // Input reset
.WRCLK(wr_clk), // Input write clock
.WREN(wr_en) // Input write enable
);
// End of FIFO_DUALCLOCK_MACRO_inst instantiation
end else begin: fifo36_2_inst
// FIFO_DUALCLOCK_MACRO: Dual Clock First-In, First-Out (FIFO) RAM Buffer
// Virtex-6
// Xilinx HDL Language Template, version 12.1
FIFO_DUALCLOCK_MACRO #(
.ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET), // Sets the almost empty threshold
.ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET), // Sets almost full threshold
.DATA_WIDTH(i), // Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb")
.DEVICE(DEVICE), // Target device: "VIRTEX5", "VIRTEX6"
.FIFO_SIZE ("36Kb"), // Target BRAM: "18Kb" or "36Kb"
.FIRST_WORD_FALL_THROUGH (FIRST_WORD_FALL_THROUGH) // Sets the FIFO FWFT to "TRUE" or "FALSE"
) FIFO_DUALCLOCK_MACRO_inst (
.ALMOSTEMPTY(almostempties[0]), // Output almost empty
.ALMOSTFULL(almostfulls[0]), // Output almost full
.DO(dout[i-1:0]), // Output data
.EMPTY(empties[0]), // Output empty
.FULL(fulls[0]), // Output full
.RDCOUNT(), // Output read count
.RDERR(rderrs[0]), // Output read error
.WRCOUNT(), // Output write count
.WRERR(wrerrs[0]), // Output write error
.DI(din[i-1:0]), // Input data
.RDCLK(rd_clk), // Input read clock
.RDEN(rd_en), // Input read enable
.RST(rst), // Input reset
.WRCLK(wr_clk), // Input write clock
.WREN(wr_en) // Input write enable
);
// End of FIFO_DUALCLOCK_MACRO_inst instantiation
end
end
if (FLAG_GENERATION == "SAFE") begin
assign full = |fulls;
assign empty = |empties;
assign prog_full = |almostfulls;
assign prog_empty = |almostempties;
assign RDERR = |rderrs;
assign WRER = |wrerrs;
end else begin
assign full = fulls[num_FIFO_blocks-1];
assign empty = empties[num_FIFO_blocks-1];
assign prog_full = almostfulls[num_FIFO_blocks-1];
assign prog_empty = almostempties[num_FIFO_blocks-1];
assign RDERR = rderrs[num_FIFO_blocks-1];
assign WRER = wrerrs[num_FIFO_blocks-1];
end
always @(posedge wr_clk or posedge rst)
if (rst) begin
wr_ack <= 1'b0;
end
else begin
wr_ack <= (|wrerrs) & wr_en;
end
end
else begin: infer_fifo
(* ASYNC_REG="TRUE" *) reg empty_reg = 1'b1,
full_reg =1'b0,
almost_empty_reg = 1'b1,
almost_full_reg = 1'b0;
reg [FIFO_DEPTH-1:0] wr_addr = {FIFO_DEPTH{1'b0}},
rd_addr = {FIFO_DEPTH{1'b0}},
next_wr_addr = {{FIFO_DEPTH-1{1'b0}}, 1'b1},
next_rd_addr = {{FIFO_DEPTH-1{1'b0}}, 1'b1};
reg [FIFO_DEPTH:0] wr_addr_tmp = {{FIFO_DEPTH-1{1'b0}}, 2'b11},
rd_addr_tmp = {{FIFO_DEPTH-1{1'b0}}, 2'b11};
reg [FIFO_DEPTH-1:0] two_wr_addr = {{FIFO_DEPTH-2{1'b0}}, 2'b11},
two_rd_addr = {{FIFO_DEPTH-2{1'b0}}, 2'b11};
wire do_read, do_write;
// Create FIFO Flags
always @(posedge rd_clk or posedge rst)
if (rst) begin
empty_reg <= 1'b1;
almost_empty_reg <= 1'b1;
end
else begin
empty_reg <= (rd_en & (next_rd_addr==wr_addr)) | (empty_reg & (wr_addr==rd_addr));
almost_empty_reg <= empty_reg | (rd_en & (two_rd_addr==wr_addr)) | (next_rd_addr==wr_addr);
end
always @(posedge wr_clk or posedge rst)
if (rst) begin
full_reg <= 1'b0;
almost_full_reg <= 1'b0;
wr_ack <= 1'b0;
end
else begin
full_reg <= (wr_en & (next_wr_addr==rd_addr)) | (full_reg & (wr_addr==rd_addr));
almost_full_reg <= full_reg | (wr_en & (two_wr_addr==rd_addr)) | (next_wr_addr==rd_addr);
wr_ack <= do_write;
end
if (USE_PROG_FULL_EMPTY=="TRUE") begin: prog_full_empty
(* ASYNC_REG="TRUE" *) reg prog_empty_reg = 1'b1,
prog_full_reg = 1'b0;
always @(posedge rd_clk or posedge rst)
if (rst)
prog_empty_reg <= 1'b0;
else
case ({wr_addr_tmp[FIFO_DEPTH], rd_addr_tmp[FIFO_DEPTH]})
2'b00 : prog_empty_reg <= (wr_addr_tmp[FIFO_DEPTH-1:0]-rd_addr_tmp[FIFO_DEPTH-1:0])<ALMOST_EMPTY_OFFSET;
2'b01 : prog_empty_reg <= (({1'b1,{FIFO_DEPTH-2{1'b0}}}-wr_addr_tmp[FIFO_DEPTH-1:0])+rd_addr_tmp[FIFO_DEPTH-1:0])<ALMOST_EMPTY_OFFSET;
2'b10 : prog_empty_reg <= (wr_addr_tmp[FIFO_DEPTH-1:0]+({1'b1,{FIFO_DEPTH-2{1'b0}}}-rd_addr_tmp[FIFO_DEPTH-1:0]))<ALMOST_EMPTY_OFFSET;
2'b11 : prog_empty_reg <= (wr_addr_tmp[FIFO_DEPTH-1:0]-rd_addr_tmp[FIFO_DEPTH-1:0])<ALMOST_EMPTY_OFFSET;
endcase
always @(posedge wr_clk or posedge rst)
if (rst)
prog_full_reg <= 1'b0;
else
case ({wr_addr_tmp[FIFO_DEPTH], rd_addr_tmp[FIFO_DEPTH]})
2'b00 : prog_full_reg <= (wr_addr_tmp[FIFO_DEPTH-1:0]-rd_addr_tmp[FIFO_DEPTH-1:0])>ALMOST_FULL_OFFSET;
2'b01 : prog_full_reg <= (({1'b1,{FIFO_DEPTH-2{1'b0}}}-wr_addr_tmp[FIFO_DEPTH-1:0])+rd_addr_tmp[FIFO_DEPTH-1:0])>ALMOST_FULL_OFFSET;
2'b10 : prog_full_reg <= (wr_addr_tmp[FIFO_DEPTH-1:0]+({1'b1,{FIFO_DEPTH-2{1'b0}}}-rd_addr_tmp[FIFO_DEPTH-1:0]))>ALMOST_FULL_OFFSET;
2'b11 : prog_full_reg <= (wr_addr_tmp[FIFO_DEPTH-1:0]-rd_addr_tmp[FIFO_DEPTH-1:0])>ALMOST_FULL_OFFSET;
endcase
assign prog_empty = prog_empty_reg;
assign prog_full = prog_full_reg;
end else begin: no_prog_full_empty
assign prog_empty = 1'b0;
assign prog_full = 1'b0;
end
if (FIRST_WORD_FALL_THROUGH=="TRUE") begin: FWFT
reg fwft_reg = 1'b1;
always @(posedge rd_clk or posedge rst)
if (rst)
fwft_reg <= 1'b1;
else if (empty)
fwft_reg <= 1'b1;
else
fwft_reg <= 1'b0;
assign do_read = (rd_en & ~empty_reg) | (fwft_reg & ~empty_reg);
end else begin: no_FWFT
assign do_read = rd_en & ~empty_reg;
end
assign do_write = wr_en & ~full_reg;
assign empty = empty_reg;
assign full = full_reg;
// assign almost_empty = almost_empty_reg;
// assign almost_full = almost_full_reg;
// Write Address Generation
always @(posedge wr_clk or posedge rst)
if (rst) begin
wr_addr <= {FIFO_DEPTH{1'b0}};
next_wr_addr <= {{FIFO_DEPTH-1{1'b0}}, 1'b1};
two_wr_addr <= {{FIFO_DEPTH-2{1'b0}}, 2'b11};
wr_addr_tmp <= {{FIFO_DEPTH-1{1'b0}}, 2'b11};
end
else if (do_write) begin
wr_addr <= next_wr_addr;
next_wr_addr <= two_wr_addr;
two_wr_addr <= (wr_addr_tmp[FIFO_DEPTH-1:0] >> 1) ^ wr_addr_tmp[FIFO_DEPTH-1:0];
wr_addr_tmp <= wr_addr_tmp + 1'b1;
end
// Read Address Generation
always @(posedge rd_clk or posedge rst)
if (rst) begin
rd_addr <= {FIFO_DEPTH{1'b0}};
next_rd_addr <= {{FIFO_DEPTH-1{1'b0}}, 1'b1};
two_rd_addr <= {{FIFO_DEPTH-2{1'b0}}, 2'b11};
rd_addr_tmp <= {{FIFO_DEPTH-1{1'b0}}, 2'b11};
end
else if (do_read) begin
rd_addr <= next_rd_addr;
next_rd_addr <= two_rd_addr;
two_rd_addr <= (rd_addr_tmp[FIFO_DEPTH-1:0] >> 1) ^ rd_addr_tmp[FIFO_DEPTH-1:0];
rd_addr_tmp <= rd_addr_tmp + 1'b1;
end
// RAM Inference Code
if (FIFO_RAM_TYPE=="DISTRIBUTED_RAM") begin: dist_ram
(* RAM_STYLE="PIPE_DISTRIBUTED" *)
reg [FIFO_WIDTH-1:0] fifo_ram [(2**FIFO_DEPTH)-1:0];
reg [FIFO_WIDTH-1:0] ram_out, fifo_out;
always @(posedge wr_clk)
if (do_write)
fifo_ram[wr_addr] <= din;
always @(posedge rd_clk or posedge rst)
if (rst)
fifo_out <= {FIFO_WIDTH{1'b0}};
else if (do_read)
fifo_out <= ram_out;
always @*
ram_out = fifo_ram[rd_addr];
assign dout = fifo_out;
// end else if (OPTIMIZE=="POWER") begin: block_ram_power
//
// (* RAM_STYLE="BLOCK_POWER2" *)
// reg [FIFO_WIDTH-1:0] fifo_ram [(2**FIFO_DEPTH)-1:0];
// reg [FIFO_WIDTH-1:0] fifo_out;
//
// always @(posedge wr_clk)
// if (do_write)
// fifo_ram[wr_addr] <= din;
//
// always @(posedge rd_clk)
// if (rst)
// fifo_out <= {FIFO_WIDTH{1'b0}};
// else if (do_read)
// fifo_out <= fifo_ram[rd_addr];
//
// assign dout = fifo_out;
end else begin: block_ram_performance
//(* RAM_STYLE="BLOCK" *)
reg [FIFO_WIDTH-1:0] fifo_ram [(2**FIFO_DEPTH)-1:0];
reg [FIFO_WIDTH-1:0] fifo_out;
always @(posedge wr_clk)
if (do_write)
fifo_ram[wr_addr] <= din;
always @(posedge rd_clk)
if (rst)
fifo_out <= {FIFO_WIDTH{1'b0}};
else if (do_read)
fifo_out <= fifo_ram[rd_addr];
assign dout = fifo_out;
end
end
endgenerate
endmodule
|
module reg_bank (
read,
byteenable,
address,
write,
rst,
clk,
writedata,
leds,
readdata,
waitrequest,
readdatavalid
);
input read;
input [3:0] byteenable;
input [31:0] address;
input write;
input rst;
input clk;
input [31:0] writedata;
output [7:0] leds;
output [31:0] readdata;
output waitrequest;
output readdatavalid;
/* signal declarations */
wire gnd = 1'b0;
wire _112;
wire _113;
wire _114;
wire [7:0] _115 = 8'b00000000;
wire [7:0] _116 = 8'b00000000;
wire [7:0] _111;
reg [7:0] _117;
wire _119;
wire _120;
wire _121;
wire [7:0] _122 = 8'b00000000;
wire [7:0] _123 = 8'b00000000;
wire [7:0] _118;
reg [7:0] _124;
wire _126;
wire _127;
wire _128;
wire [7:0] _129 = 8'b00000000;
wire [7:0] _130 = 8'b00000000;
wire [7:0] _125;
reg [7:0] _131;
wire _133;
wire [31:0] _49 = 32'b00000000000000000000000000001000;
wire _50;
wire _134;
wire _135;
wire [7:0] _136 = 8'b00000000;
wire [7:0] _137 = 8'b00000000;
wire [7:0] _132;
reg [7:0] _138;
wire [31:0] _139;
wire _83;
wire _84;
wire _85;
wire [7:0] _86 = 8'b00000000;
wire [7:0] _87 = 8'b00000000;
wire [7:0] _82;
reg [7:0] _88;
wire _90;
wire _91;
wire _92;
wire [7:0] _93 = 8'b00000000;
wire [7:0] _94 = 8'b00000000;
wire [7:0] _89;
reg [7:0] _95;
wire _97;
wire _98;
wire _99;
wire [7:0] _100 = 8'b00000000;
wire [7:0] _101 = 8'b00000000;
wire [7:0] _96;
reg [7:0] _102;
wire _104;
wire [31:0] _47 = 32'b00000000000000000000000000000100;
wire _48;
wire _105;
wire _106;
wire [7:0] _107 = 8'b00000000;
wire [7:0] _108 = 8'b00000000;
wire [7:0] _103;
reg [7:0] _109;
wire [31:0] _110;
wire _54;
wire _55;
wire _56;
wire [7:0] _57 = 8'b00000000;
wire [7:0] _58 = 8'b00000000;
wire [7:0] _53;
reg [7:0] _59;
wire _61;
wire _62;
wire _63;
wire [7:0] _64 = 8'b00000000;
wire [7:0] _65 = 8'b00000000;
wire [7:0] _60;
reg [7:0] _66;
wire _68;
wire _69;
wire _70;
wire [7:0] _71 = 8'b00000000;
wire [7:0] _72 = 8'b00000000;
wire [7:0] _67;
reg [7:0] _73;
wire _75;
wire [31:0] _45 = 32'b00000000000000000000000000000000;
wire _46;
wire _76;
wire _77;
wire [7:0] _78 = 8'b00000000;
wire [7:0] _79 = 8'b00000000;
wire [7:0] _74;
reg [7:0] _80;
wire [31:0] _81;
wire [29:0] _170;
reg [31:0] _171;
wire [31:0] _169 = 32'b11011110101011011011111011101111;
wire [31:0] _172;
wire _141;
wire _142;
wire _143;
wire [7:0] _144 = 8'b00000000;
wire [7:0] _145 = 8'b00000000;
wire [7:0] _140;
reg [7:0] _146;
wire _148;
wire _149;
wire _150;
wire [7:0] _151 = 8'b00000000;
wire [7:0] _152 = 8'b00000000;
wire [7:0] _147;
reg [7:0] _153;
wire _155;
wire _156;
wire _157;
wire [7:0] _158 = 8'b00000000;
wire [7:0] _159 = 8'b00000000;
wire [7:0] _154;
reg [7:0] _160;
wire _162;
wire [31:0] _51 = 32'b00000000000000000000000000001100;
wire _52;
wire _163;
wire _164;
wire [7:0] _165 = 8'b00000000;
wire _44;
wire vdd = 1'b1;
wire [7:0] _166 = 8'b00000000;
wire [7:0] _161;
reg [7:0] _167;
wire [31:0] _168;
wire [7:0] _173;
/* logic */
assign _112 = byteenable[0:0];
assign _113 = write & _50;
assign _114 = _113 & _112;
assign _111 = writedata[7:0];
always @(posedge clk) begin
if (_44)
_117 <= _115;
else
if (_114)
_117 <= _111;
end
assign _119 = byteenable[1:1];
assign _120 = write & _50;
assign _121 = _120 & _119;
assign _118 = writedata[15:8];
always @(posedge clk) begin
if (_44)
_124 <= _122;
else
if (_121)
_124 <= _118;
end
assign _126 = byteenable[2:2];
assign _127 = write & _50;
assign _128 = _127 & _126;
assign _125 = writedata[23:16];
always @(posedge clk) begin
if (_44)
_131 <= _129;
else
if (_128)
_131 <= _125;
end
assign _133 = byteenable[3:3];
assign _50 = address == _49;
assign _134 = write & _50;
assign _135 = _134 & _133;
assign _132 = writedata[31:24];
always @(posedge clk) begin
if (_44)
_138 <= _136;
else
if (_135)
_138 <= _132;
end
assign _139 = { _138, _131, _124, _117 };
assign _83 = byteenable[0:0];
assign _84 = write & _48;
assign _85 = _84 & _83;
assign _82 = writedata[7:0];
always @(posedge clk) begin
if (_44)
_88 <= _86;
else
if (_85)
_88 <= _82;
end
assign _90 = byteenable[1:1];
assign _91 = write & _48;
assign _92 = _91 & _90;
assign _89 = writedata[15:8];
always @(posedge clk) begin
if (_44)
_95 <= _93;
else
if (_92)
_95 <= _89;
end
assign _97 = byteenable[2:2];
assign _98 = write & _48;
assign _99 = _98 & _97;
assign _96 = writedata[23:16];
always @(posedge clk) begin
if (_44)
_102 <= _100;
else
if (_99)
_102 <= _96;
end
assign _104 = byteenable[3:3];
assign _48 = address == _47;
assign _105 = write & _48;
assign _106 = _105 & _104;
assign _103 = writedata[31:24];
always @(posedge clk) begin
if (_44)
_109 <= _107;
else
if (_106)
_109 <= _103;
end
assign _110 = { _109, _102, _95, _88 };
assign _54 = byteenable[0:0];
assign _55 = write & _46;
assign _56 = _55 & _54;
assign _53 = writedata[7:0];
always @(posedge clk) begin
if (_44)
_59 <= _57;
else
if (_56)
_59 <= _53;
end
assign _61 = byteenable[1:1];
assign _62 = write & _46;
assign _63 = _62 & _61;
assign _60 = writedata[15:8];
always @(posedge clk) begin
if (_44)
_66 <= _64;
else
if (_63)
_66 <= _60;
end
assign _68 = byteenable[2:2];
assign _69 = write & _46;
assign _70 = _69 & _68;
assign _67 = writedata[23:16];
always @(posedge clk) begin
if (_44)
_73 <= _71;
else
if (_70)
_73 <= _67;
end
assign _75 = byteenable[3:3];
assign _46 = address == _45;
assign _76 = write & _46;
assign _77 = _76 & _75;
assign _74 = writedata[31:24];
always @(posedge clk) begin
if (_44)
_80 <= _78;
else
if (_77)
_80 <= _74;
end
assign _81 = { _80, _73, _66, _59 };
assign _170 = address[31:2];
always @* begin
case (_170)
0: _171 <= _81;
1: _171 <= _110;
2: _171 <= _139;
3: _171 <= _168;
default: _171 <= _169;
endcase
end
assign _172 = read ? _171 : _169;
assign _141 = byteenable[0:0];
assign _142 = write & _52;
assign _143 = _142 & _141;
assign _140 = writedata[7:0];
always @(posedge clk) begin
if (_44)
_146 <= _144;
else
if (_143)
_146 <= _140;
end
assign _148 = byteenable[1:1];
assign _149 = write & _52;
assign _150 = _149 & _148;
assign _147 = writedata[15:8];
always @(posedge clk) begin
if (_44)
_153 <= _151;
else
if (_150)
_153 <= _147;
end
assign _155 = byteenable[2:2];
assign _156 = write & _52;
assign _157 = _156 & _155;
assign _154 = writedata[23:16];
always @(posedge clk) begin
if (_44)
_160 <= _158;
else
if (_157)
_160 <= _154;
end
assign _162 = byteenable[3:3];
assign _52 = address == _51;
assign _163 = write & _52;
assign _164 = _163 & _162;
assign _44 = ~ rst;
assign _161 = writedata[31:24];
always @(posedge clk) begin
if (_44)
_167 <= _165;
else
if (_164)
_167 <= _161;
end
assign _168 = { _167, _160, _153, _146 };
assign _173 = _168[7:0];
/* aliases */
/* output assignments */
assign leds = _173;
assign readdata = _172;
assign waitrequest = gnd;
assign readdatavalid = vdd;
endmodule
module de0_nano_simple
(
input [1:0] GPIO_1_IN,
input [1:0] GPIO_0_IN,
input [2:0] GPIO_2_IN,
input ADC_SDAT,
input G_SENSOR_INT,
input EPCS_DATA0,
input [3:0] SW,
input [1:0] KEY,
input CLOCK_50,
output ADC_SCLK,
output ADC_SADDR,
output ADC_CS_N,
output I2C_SCLK,
output G_SENSOR_CS_N,
output EPCS_NCSO,
output EPCS_DCLK,
output EPCS_ASDO,
output DRAM_WE_N,
output DRAM_RAS_N,
output [1:0] DRAM_DQM,
output DRAM_CS_N,
output DRAM_CLK,
output DRAM_CKE,
output DRAM_CAS_N,
output [1:0] DRAM_BA,
output [12:0] DRAM_ADDR,
output [7:0] LED,
inout [33:0] GPIO_1,
inout [33:0] GPIO_0,
inout [12:0] GPIO_2,
inout I2C_SDAT,
inout [15:0] DRAM_DQ
);
wire _1;
wire _2;
wire _3;
wire _4;
wire _5;
wire _6;
wire _39;
wire _40;
wire _41;
wire _43;
wire _44;
wire [31:0] _45;
wire _46;
wire _47;
wire [3:0] _48;
wire [31:0] _49;
wire _50;
wire _51;
wire [31:0] _52;
wire _54;
wire _55;
wire [31:0] _56;
wire [7:0] _57;
wire [1:0] _59;
wire [12:0] _60;
wire [33:0] _61;
wire [12:0] _62;
wire _63;
wire [15:0] _64;
assign _1 = 1'b1;
assign _2 = 1'b0;
assign _43 = _54;
assign _44 = _55;
assign _45 = _56;
assign _46 = _39;
assign _47 = _41;
assign _59 = 2'b00;
assign _60 = 13'b0000000000000;
assign _61 = 34'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
assign _62 = 13'bzzzzzzzzzzzzz;
assign _63 = 1'bz;
assign _64 = 16'bzzzzzzzzzzzzzzzz;
assign ADC_SCLK = _2;
assign ADC_SADDR = _2;
assign ADC_CS_N = _1;
assign I2C_SCLK = _2;
assign G_SENSOR_CS_N = _1;
assign EPCS_NCSO = _2;
assign EPCS_DCLK = _2;
assign EPCS_ASDO = _2;
assign DRAM_WE_N = _2;
assign DRAM_RAS_N = _2;
assign DRAM_DQM = _59;
assign DRAM_CS_N = _2;
assign DRAM_CLK = _2;
assign DRAM_CKE = _2;
assign DRAM_CAS_N = _2;
assign DRAM_BA = _59;
assign DRAM_ADDR = _60;
assign LED = _57;
assign GPIO_1 = _61;
assign GPIO_0 = _61;
assign GPIO_2 = _62;
assign I2C_SDAT = _63;
assign DRAM_DQ = _64;
pll50 _42
(
.inclk0(CLOCK_50),
.c0(_41),
.c1(_40),
.locked(_39)
);
vjtag_mm _53
(
.clk_clk(_47),
.reset_reset_n(_46),
.vjtag_mm_readdata(_45),
.vjtag_mm_waitrequest(_44),
.vjtag_mm_readdatavalid(_43),
.vjtag_mm_address(_52),
.vjtag_mm_read(_51),
.vjtag_mm_write(_50),
.vjtag_mm_writedata(_49),
.vjtag_mm_byteenable(_48)
);
reg_bank _58
(
.clk(_41),
.rst(_39),
.address(_52),
.read(_51),
.write(_50),
.writedata(_49),
.byteenable(_48),
.leds(_57),
.readdata(_56),
.waitrequest(_55),
.readdatavalid(_54)
);
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 14:20:41 2016
/////////////////////////////////////////////////////////////
module FPU_Interface_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, begin_operation,
ack_operation, operation, region_flag, Data_1, Data_2, r_mode,
overflow_flag, underflow_flag, NaN_flag, operation_ready, op_result );
input [2:0] operation;
input [1:0] region_flag;
input [31:0] Data_1;
input [31:0] Data_2;
input [1:0] r_mode;
output [31:0] op_result;
input clk, rst, begin_operation, ack_operation;
output overflow_flag, underflow_flag, NaN_flag, operation_ready;
wire operation_reg_0_, NaN_reg, overflow_flag_addsubt,
FPSENCOS_data_output2_31_, FPSENCOS_sel_mux_3_reg,
FPSENCOS_d_ff3_sign_out, FPSENCOS_sel_mux_1_reg,
FPSENCOS_d_ff1_operation_out, FPMULT_FSM_selector_C,
FPMULT_FSM_selector_A, FPMULT_FSM_add_overflow_flag, FPMULT_zero_flag,
FPADDSUB_sign_final_result, FPADDSUB_intAS, FPADDSUB_FSM_selector_A,
FPADDSUB_add_overflow_flag, FPADDSUB_FSM_selector_C,
FPSENCOS_cordic_FSM_state_next_1_, FPMULT_Exp_module_Overflow_A,
n1215, n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224,
n1225, n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234,
n1235, n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244,
n1245, n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254,
n1255, n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264,
n1265, n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274,
n1275, n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284,
n1285, n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294,
n1295, n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304,
n1305, n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314,
n1315, n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324,
n1325, n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334,
n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1346,
n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356, n1357,
n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366, n1367,
n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377,
n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386, n1387,
n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1396, n1397,
n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406, n1407,
n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415, n1416, n1417,
n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425, n1426, n1427,
n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435, n1436, n1437,
n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445, n1446, n1447,
n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455, n1456, n1457,
n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465, n1466, n1467,
n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475, n1476, n1477,
n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485, n1486, n1487,
n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497,
n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507,
n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517,
n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526, n1527,
n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535, n1536, n1537,
n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545, n1546, n1547,
n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556, n1557,
n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566, n1567,
n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576, n1577,
n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586, n1587,
n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596, n1597,
n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606, n1607,
n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616, n1617,
n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626, n1627,
n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636, n1637,
n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646, n1647,
n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656, n1657,
n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666, n1667,
n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676, n1677,
n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686, n1687,
n1688, n1690, n1691, n1692, n1693, n1694, n1695, n1696, n1697, n1698,
n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706, n1707, n1708,
n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716, n1717, n1718,
n1719, n1720, n1721, n1722, n1723, n1724, n1725, n1726, n1727, n1728,
n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736, n1737, n1738,
n1739, n1740, n1741, n1742, n1743, n1744, n1745, n1746, n1747, n1748,
n1749, n1750, n1751, n1752, n1753, n1754, n1755, n1756, n1757, n1758,
n1759, n1760, n1761, n1762, n1763, n1764, n1765, n1766, n1767, n1768,
n1769, n1770, n1771, n1772, n1773, n1774, n1775, n1776, n1777, n1778,
n1779, n1780, n1781, n1782, n1783, n1784, n1785, n1786, n1787, n1788,
n1789, n1790, n1791, n1792, n1793, n1794, n1795, n1796, n1797, n1798,
n1799, n1800, n1801, n1802, n1803, n1804, n1805, n1806, n1807, n1808,
n1809, n1810, n1811, n1812, n1813, n1814, n1815, n1816, n1817, n1818,
n1819, n1820, n1821, n1822, n1823, n1824, n1825, n1826, n1827, n1828,
n1829, n1830, n1831, n1832, n1833, n1834, n1835, n1836, n1837, n1838,
n1839, n1840, n1841, n1842, n1843, n1844, n1845, n1846, n1848, n1849,
n1850, n1851, n1852, n1853, n1854, n1855, n1856, n1857, n1858, n1859,
n1860, n1861, n1862, n1863, n1864, n1865, n1866, n1867, n1868, n1869,
n1870, n1871, n1872, n1873, n1874, n1875, n1876, n1877, n1878, n1879,
n1880, n1882, n1883, n1884, n1885, n1886, n1887, n1888, n1889, n1890,
n1891, n1892, n1893, n1894, n1895, n1896, n1897, n1898, n1899, n1900,
n1901, n1902, n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910,
n1911, n1912, n1913, n1914, n1915, n1916, n1917, n1918, n1919, n1920,
n1921, n1922, n1923, n1924, n1925, n1926, n1927, n1928, n1929, n1930,
n1931, n1932, n1933, n1934, n1935, n1936, n1937, n1938, n1939, n1940,
n1941, n1942, n1943, n1944, n1945, n1946, n1947, n1948, n1949, n1950,
n1951, n1952, n1953, n1954, n1955, n1956, n1957, n1958, n1959, n1960,
n1961, n1962, n1963, n1964, n1965, n1966, n1967, n1968, n1969, n1970,
n1971, n1972, n1973, n1974, n1975, n1976, n1977, n1978, n1979, n1980,
n1981, n1982, n1983, n1984, n1985, n1986, n1987, n1988, n1989, n1990,
n1991, n1992, n1993, n1994, n1995, n1996, n1997, n1998, n1999, n2000,
n2001, n2002, n2003, n2004, n2005, n2006, n2008, n2009, n2010, n2012,
n2013, n2014, n2015, n2016, n2017, n2018, n2019, n2020, n2021, n2022,
n2023, n2024, n2025, n2026, n2027, n2028, n2030, n2031, n2032, n2033,
n2034, n2035, n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043,
n2044, n2045, n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053,
n2054, n2055, n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063,
n2064, DP_OP_134J305_123_859_n22, DP_OP_134J305_123_859_n21,
DP_OP_134J305_123_859_n20, DP_OP_134J305_123_859_n19,
DP_OP_134J305_123_859_n18, DP_OP_134J305_123_859_n17,
DP_OP_134J305_123_859_n16, DP_OP_134J305_123_859_n15,
DP_OP_134J305_123_859_n9, DP_OP_134J305_123_859_n8,
DP_OP_134J305_123_859_n7, DP_OP_134J305_123_859_n6,
DP_OP_134J305_123_859_n5, DP_OP_134J305_123_859_n4,
DP_OP_134J305_123_859_n3, DP_OP_134J305_123_859_n2,
DP_OP_134J305_123_859_n1, n2114, n2115, n2116, n2118, n2119, n2120,
n2121, n2122, n2123, n2124, n2125, n2127, n2128, n2129, n2130, n2131,
n2132, n2133, n2134, n2135, n2136, n2137, n2138, n2139, n2140, n2141,
n2142, n2143, n2144, n2145, n2146, n2147, n2148, n2149, n2150, n2151,
n2152, n2153, n2154, n2155, n2156, n2157, n2158, n2159, n2160, n2161,
n2162, n2163, n2164, n2165, n2166, n2167, n2168, n2169, n2170, n2171,
n2172, n2173, n2174, n2175, n2176, n2177, n2178, n2179, n2180, n2181,
n2182, n2183, n2184, n2185, n2186, n2187, n2188, n2189, n2190, n2191,
n2192, n2193, n2194, n2195, n2196, n2197, n2198, n2199, n2200, n2201,
n2202, n2203, n2204, n2205, n2206, n2207, n2208, n2209, n2210, n2211,
n2212, n2213, n2214, n2215, n2216, n2217, n2218, n2219, n2220, n2221,
n2222, n2223, n2224, n2225, n2226, n2227, n2228, n2229, n2230, n2231,
n2232, n2233, n2234, n2235, n2236, n2237, n2238, n2239, n2240, n2241,
n2242, n2243, n2244, n2245, n2246, n2247, n2248, n2249, n2251, n2252,
n2253, n2254, n2255, n2256, n2257, n2258, n2259, n2260, n2261, n2262,
n2263, n2264, n2265, n2266, n2267, n2268, n2269, n2270, n2271, n2272,
n2273, n2274, n2275, n2276, n2277, n2278, n2279, n2280, n2281, n2282,
n2283, n2284, n2285, n2286, n2287, n2288, n2289, n2290, n2291, n2292,
n2293, n2294, n2295, n2296, n2297, n2298, n2299, n2300, n2301, n2302,
n2303, n2304, n2305, n2306, n2307, n2308, n2309, n2310, n2311, n2312,
n2313, n2314, n2315, n2316, n2317, n2318, n2319, n2320, n2321, n2322,
n2323, n2324, n2325, n2326, n2327, n2328, n2329, n2330, n2331, n2333,
n2334, n2335, n2336, n2337, n2338, n2339, n2340, n2341, n2342, n2343,
n2344, n2345, n2346, n2347, n2348, n2349, n2350, n2351, n2352, n2353,
n2354, n2355, n2356, n2357, n2358, n2359, n2360, n2361, n2362, n2363,
n2364, n2365, n2366, n2367, n2368, n2369, n2370, n2371, n2372, n2373,
n2374, n2375, n2376, n2377, n2378, n2379, n2380, n2381, n2382, n2383,
n2384, n2385, n2386, n2387, n2388, n2389, n2390, n2391, n2392, n2393,
n2394, n2395, n2396, n2397, n2398, n2399, n2400, n2401, n2402, n2403,
n2404, n2405, n2406, n2407, n2408, n2409, n2410, n2411, n2412, n2413,
n2414, n2415, n2416, n2417, n2418, n2419, n2420, n2421, n2422, n2423,
n2424, n2425, n2426, n2427, n2428, n2429, n2430, n2431, n2432, n2433,
n2434, n2435, n2436, n2437, n2438, n2439, n2440, n2441, n2442, n2443,
n2444, n2445, n2446, n2447, n2448, n2449, n2450, n2451, n2452, n2453,
n2454, n2455, n2456, n2457, n2458, n2459, n2460, n2461, n2462, n2463,
n2464, n2465, n2466, n2467, n2468, n2469, n2470, n2471, n2472, n2473,
n2474, n2475, n2476, n2477, n2478, n2479, n2480, n2481, n2482, n2483,
n2484, n2485, n2486, n2487, n2488, n2489, n2490, n2491, n2492, n2493,
n2494, n2495, n2496, n2497, n2498, n2499, n2500, n2501, n2502, n2503,
n2504, n2505, n2506, n2507, n2508, n2509, n2510, n2511, n2512, n2513,
n2514, n2515, n2516, n2517, n2518, n2519, n2520, n2521, n2522, n2523,
n2524, n2525, n2526, n2527, n2528, n2529, n2530, n2531, n2532, n2533,
n2534, n2535, n2536, n2538, n2539, n2540, n2541, n2542, n2543, n2544,
n2545, n2546, n2547, n2548, n2549, n2550, n2551, n2552, n2553, n2554,
n2555, n2556, n2557, n2558, n2559, n2560, n2561, n2562, n2563, n2564,
n2565, n2566, n2567, n2568, n2569, n2570, n2571, n2572, n2573, n2574,
n2575, n2576, n2577, n2578, n2579, n2580, n2581, n2582, n2583, n2584,
n2585, n2586, n2587, n2588, n2589, n2590, n2591, n2592, n2593, n2594,
n2595, n2596, n2597, n2598, n2599, n2600, n2601, n2602, n2603, n2604,
n2605, n2606, n2607, n2608, n2609, n2610, n2611, n2612, n2613, n2614,
n2615, n2616, n2617, n2618, n2619, n2620, n2621, n2622, n2623, n2624,
n2625, n2626, n2627, n2628, n2629, n2630, n2631, n2632, n2633, n2634,
n2635, n2636, n2637, n2638, n2639, n2640, n2641, n2642, n2643, n2644,
n2645, n2646, n2647, n2648, n2649, n2650, n2651, n2652, n2653, n2654,
n2655, n2656, n2657, n2658, n2659, n2660, n2661, n2662, n2663, n2664,
n2665, n2666, n2667, n2668, n2669, n2670, n2671, n2672, n2673, n2674,
n2675, n2676, n2677, n2678, n2679, n2680, n2681, n2682, n2683, n2684,
n2685, n2686, n2687, n2688, n2689, n2690, n2691, n2692, n2693, n2694,
n2695, n2696, n2697, n2698, n2699, n2700, n2701, n2702, n2703, n2704,
n2705, n2706, n2707, n2708, n2709, n2710, n2711, n2712, n2713, n2714,
n2715, n2716, n2717, n2718, n2719, n2720, n2721, n2722, n2723, n2724,
n2725, n2726, n2727, n2728, n2729, n2730, n2731, n2732, n2733, n2734,
n2735, n2736, n2737, n2738, n2739, n2740, n2741, n2742, n2743, n2744,
n2745, n2746, n2747, n2748, n2749, n2750, n2751, n2752, n2753, n2754,
n2755, n2756, n2757, n2758, n2759, n2760, n2761, n2762, n2763, n2764,
n2765, n2766, n2767, n2768, n2769, n2770, n2771, n2772, n2773, n2774,
n2775, n2776, n2777, n2778, n2779, n2780, n2781, n2782, n2783, n2784,
n2785, n2786, n2787, n2788, n2789, n2790, n2791, n2792, n2793, n2794,
n2795, n2796, n2797, n2798, n2799, n2800, n2801, n2802, n2803, n2804,
n2805, n2806, n2807, n2808, n2809, n2810, n2811, n2812, n2813, n2814,
n2815, n2816, n2817, n2818, n2819, n2820, n2821, n2822, n2823, n2824,
n2825, n2826, n2827, n2828, n2829, n2830, n2831, n2832, n2833, n2834,
n2835, n2836, n2837, n2838, n2839, n2840, n2841, n2842, n2843, n2844,
n2845, n2846, n2847, n2848, n2849, n2850, n2851, n2852, n2853, n2854,
n2855, n2856, n2857, n2858, n2859, n2860, n2861, n2862, n2863, n2864,
n2865, n2866, n2867, n2868, n2869, n2870, n2871, n2872, n2873, n2874,
n2875, n2876, n2877, n2878, n2879, n2880, n2881, n2882, n2883, n2884,
n2885, n2886, n2887, n2888, n2889, n2890, n2891, n2892, n2893, n2894,
n2895, n2896, n2897, n2898, n2899, n2900, n2901, n2902, n2903, n2904,
n2905, n2906, n2907, n2908, n2909, n2910, n2911, n2912, n2913, n2914,
n2915, n2916, n2917, n2918, n2919, n2920, n2921, n2922, n2923, n2924,
n2925, n2926, n2927, n2928, n2929, n2930, n2931, n2932, n2933, n2934,
n2935, n2936, n2937, n2938, n2939, n2940, n2941, n2942, n2943, n2944,
n2945, n2946, n2947, n2948, n2949, n2950, n2951, n2952, n2953, n2954,
n2955, n2956, n2957, n2958, n2959, n2960, n2961, n2962, n2963, n2964,
n2965, n2966, n2967, n2968, n2969, n2970, n2971, n2972, n2973, n2974,
n2975, n2976, n2977, n2978, n2979, n2980, n2981, n2982, n2983, n2984,
n2985, n2986, n2987, n2988, n2989, n2990, n2991, n2992, n2993, n2994,
n2995, n2996, n2997, n2998, n2999, n3000, n3001, n3002, n3003, n3004,
n3005, n3006, n3007, n3008, n3009, n3010, n3011, n3012, n3013, n3014,
n3015, n3016, n3017, n3018, n3019, n3020, n3021, n3022, n3023, n3024,
n3025, n3026, n3027, n3028, n3029, n3030, n3031, n3032, n3033, n3034,
n3035, n3036, n3037, n3038, n3039, n3040, n3041, n3042, n3043, n3044,
n3045, n3046, n3047, n3048, n3049, n3050, n3051, n3052, n3053, n3054,
n3055, n3056, n3057, n3058, n3059, n3060, n3061, n3062, n3063, n3064,
n3065, n3066, n3067, n3068, n3069, n3070, n3071, n3072, n3073, n3074,
n3075, n3076, n3077, n3078, n3079, n3080, n3081, n3082, n3083, n3084,
n3085, n3086, n3087, n3088, n3089, n3090, n3091, n3092, n3093, n3094,
n3095, n3096, n3097, n3098, n3099, n3100, n3101, n3102, n3103, n3104,
n3105, n3106, n3107, n3108, n3109, n3110, n3111, n3112, n3113, n3114,
n3115, n3116, n3117, n3118, n3119, n3120, n3121, n3122, n3123, n3124,
n3125, n3126, n3127, n3128, n3129, n3130, n3131, n3132, n3133, n3134,
n3135, n3136, n3137, n3138, n3139, n3140, n3141, n3142, n3143, n3144,
n3145, n3146, n3147, n3148, n3149, n3150, n3151, n3152, n3153, n3154,
n3155, n3156, n3157, n3158, n3159, n3160, n3161, n3162, n3163, n3164,
n3165, n3166, n3167, n3168, n3169, n3170, n3171, n3172, n3173, n3174,
n3175, n3176, n3177, n3178, n3179, n3180, n3181, n3182, n3183, n3184,
n3185, n3186, n3187, n3188, n3189, n3190, n3191, n3192, n3193, n3194,
n3195, n3196, n3197, n3198, n3199, n3200, n3201, n3202, n3203, n3204,
n3205, n3206, n3207, n3208, n3209, n3210, n3211, n3212, n3213, n3214,
n3215, n3216, n3217, n3218, n3219, n3220, n3221, n3222, n3223, n3224,
n3225, n3226, n3227, n3228, n3229, n3230, n3231, n3232, n3233, n3234,
n3235, n3236, n3237, n3238, n3239, n3240, n3241, n3242, n3243, n3244,
n3245, n3246, n3247, n3248, n3249, n3250, n3251, n3252, n3253, n3254,
n3255, n3256, n3257, n3258, n3259, n3260, n3261, n3262, n3263, n3264,
n3265, n3266, n3267, n3268, n3269, n3270, n3271, n3272, n3273, n3274,
n3275, n3276, n3277, n3278, n3279, n3280, n3281, n3282, n3283, n3284,
n3285, n3286, n3287, n3288, n3289, n3290, n3291, n3292, n3293, n3294,
n3295, n3296, n3297, n3298, n3299, n3300, n3301, n3302, n3303, n3304,
n3305, n3306, n3307, n3308, n3309, n3310, n3311, n3312, n3313, n3314,
n3315, n3316, n3317, n3318, n3319, n3320, n3321, n3322, n3323, n3324,
n3325, n3326, n3327, n3328, n3329, n3330, n3331, n3332, n3333, n3334,
n3335, n3336, n3337, n3338, n3339, n3340, n3341, n3342, n3343, n3344,
n3345, n3346, n3347, n3348, n3349, n3350, n3351, n3352, n3353, n3354,
n3355, n3356, n3357, n3358, n3359, n3360, n3361, n3362, n3363, n3364,
n3365, n3366, n3367, n3368, n3369, n3370, n3371, n3372, n3373, n3374,
n3375, n3376, n3377, n3378, n3379, n3380, n3381, n3382, n3383, n3384,
n3385, n3386, n3387, n3388, n3389, n3390, n3391, n3392, n3393, n3394,
n3395, n3396, n3397, n3398, n3399, n3400, n3401, n3402, n3403, n3404,
n3405, n3406, n3407, n3408, n3409, n3410, n3411, n3412, n3413, n3414,
n3415, n3416, n3417, n3418, n3419, n3420, n3421, n3422, n3423, n3424,
n3425, n3426, n3427, n3428, n3429, n3430, n3431, n3432, n3433, n3434,
n3435, n3436, n3437, n3438, n3439, n3440, n3441, n3442, n3443, n3444,
n3445, n3446, n3447, n3448, n3449, n3450, n3451, n3452, n3453, n3454,
n3455, n3456, n3457, n3458, n3459, n3460, n3461, n3462, n3463, n3464,
n3465, n3466, n3467, n3468, n3469, n3470, n3471, n3472, n3473, n3474,
n3475, n3476, n3477, n3478, n3479, n3480, n3481, n3482, n3483, n3484,
n3485, n3486, n3487, n3488, n3489, n3490, n3491, n3492, n3493, n3494,
n3495, n3496, n3497, n3498, n3499, n3500, n3501, n3502, n3503, n3504,
n3505, n3506, n3507, n3508, n3509, n3510, n3511, n3512, n3513, n3514,
n3515, n3516, n3517, n3518, n3519, n3520, n3521, n3522, n3523, n3524,
n3525, n3526, n3527, n3528, n3529, n3530, n3531, n3532, n3533, n3534,
n3535, n3536, n3537, n3538, n3539, n3540, n3541, n3542, n3543, n3544,
n3545, n3546, n3547, n3548, n3549, n3550, n3551, n3552, n3553, n3554,
n3555, n3556, n3557, n3558, n3559, n3560, n3561, n3562, n3563, n3564,
n3565, n3566, n3567, n3568, n3569, n3570, n3571, n3572, n3573, n3574,
n3575, n3576, n3577, n3578, n3579, n3580, n3581, n3582, n3583, n3584,
n3585, n3586, n3587, n3588, n3589, n3590, n3591, n3592, n3593, n3594,
n3595, n3596, n3597, n3598, n3599, n3600, n3601, n3602, n3603, n3604,
n3605, n3606, n3607, n3608, n3609, n3610, n3611, n3612, n3613, n3614,
n3615, n3616, n3617, n3618, n3619, n3620, n3621, n3622, n3623, n3624,
n3625, n3626, n3627, n3628, n3629, n3630, n3631, n3632, n3633, n3634,
n3635, n3636, n3637, n3638, n3639, n3640, n3641, n3642, n3643, n3644,
n3645, n3646, n3647, n3648, n3649, n3650, n3651, n3652, n3653, n3654,
n3655, n3656, n3657, n3658, n3659, n3660, n3661, n3662, n3663, n3664,
n3665, n3666, n3667, n3668, n3669, n3670, n3671, n3672, n3673, n3674,
n3675, n3676, n3677, n3678, n3679, n3680, n3681, n3682, n3683, n3684,
n3685, n3686, n3687, n3688, n3689, n3690, n3691, n3692, n3693, n3694,
n3695, n3696, n3697, n3698, n3699, n3700, n3701, n3702, n3703, n3704,
n3705, n3706, n3707, n3708, n3709, n3710, n3711, n3712, n3713, n3714,
n3715, n3716, n3717, n3718, n3719, n3720, n3721, n3722, n3723, n3724,
n3725, n3726, n3727, n3728, n3729, n3730, n3731, n3732, n3733, n3734,
n3735, n3736, n3737, n3738, n3739, n3740, n3741, n3742, n3743, n3744,
n3745, n3746, n3747, n3748, n3749, n3750, n3751, n3752, n3753, n3754,
n3755, n3756, n3757, n3758, n3759, n3760, n3761, n3762, n3763, n3764,
n3765, n3766, n3767, n3768, n3769, n3770, n3771, n3772, n3773, n3774,
n3775, n3776, n3777, n3778, n3779, n3780, n3781, n3782, n3783, n3784,
n3785, n3786, n3787, n3788, n3789, n3790, n3791, n3792, n3793, n3794,
n3795, n3796, n3797, n3798, n3799, n3800, n3801, n3802, n3803, n3804,
n3805, n3806, n3807, n3808, n3809, n3810, n3811, n3812, n3813, n3814,
n3815, n3816, n3817, n3818, n3819, n3820, n3821, n3822, n3823, n3824,
n3825, n3826, n3827, n3828, n3829, n3830, n3831, n3832, n3833, n3834,
n3835, n3836, n3837, n3838, n3839, n3840, n3841, n3842, n3843, n3844,
n3845, n3846, n3847, n3848, n3849, n3850, n3851, n3852, n3853, n3854,
n3855, n3856, n3857, n3858, n3859, n3860, n3861, n3862, n3863, n3864,
n3865, n3866, n3867, n3868, n3869, n3870, n3871, n3872, n3873, n3874,
n3875, n3876, n3877, n3878, n3879, n3880, n3881, n3882, n3883, n3884,
n3885, n3886, n3887, n3888, n3889, n3890, n3891, n3892, n3893, n3894,
n3895, n3896, n3897, n3898, n3899, n3900, n3901, n3902, n3903, n3904,
n3905, n3906, n3907, n3908, n3909, n3910, n3911, n3912, n3913, n3914,
n3915, n3916, n3917, n3918, n3919, n3920, n3921, n3922, n3923, n3924,
n3925, n3927, n3928, n3929, n3930, n3931, n3932, n3933, n3934, n3935,
n3936, n3937, n3938, n3939, n3940, n3941, n3942, n3943, n3944, n3945,
n3946, n3947, n3948, n3949, n3950, n3951, n3952, n3953, n3954, n3955,
n3956, n3957, n3958, n3959, n3960, n3961, n3962, n3963, n3964, n3965,
n3966, n3967, n3968, n3969, n3970, n3971, n3972, n3973, n3974, n3975,
n3976, n3977, n3978, n3979, n3980, n3981, n3982, n3983, n3984, n3985,
n3986, n3987, n3988, n3989, n3990, n3991, n3992, n3993, n3994, n3995,
n3996, n3997, n3998, n3999, n4000, n4001, n4002, n4003, n4004, n4005,
n4006, n4007, n4008, n4009, n4010, n4011, n4012, n4013, n4014, n4015,
n4016, n4017, n4018, n4019, n4020, n4021, n4022, n4023, n4024, n4025,
n4026, n4027, n4028, n4029, n4030, n4031, n4032, n4033, n4034, n4035,
n4036, n4037, n4038, n4039, n4040, n4041, n4042, n4043, n4044, n4045,
n4046, n4047, n4048, n4049, n4050, n4051, n4052, n4053, n4054, n4055,
n4056, n4057, n4058, n4059, n4060, n4061, n4062, n4063, n4064, n4065,
n4066, n4067, n4068, n4069, n4070, n4071, n4072, n4073, n4074, n4075,
n4076, n4077, n4078, n4079, n4080, n4081, n4082, n4083, n4084, n4085,
n4086, n4087, n4088, n4089, n4090, n4091, n4092, n4093, n4094, n4095,
n4096, n4097, n4098, n4099, n4100, n4101, n4102, n4103, n4104, n4105,
n4106, n4107, n4108, n4109, n4110, n4111, n4112, n4113, n4114, n4115,
n4116, n4117, n4118, n4119, n4120, n4121, n4122, n4123, n4124, n4125,
n4126, n4127, n4128, n4129, n4130, n4131, n4132, n4133, n4134, n4135,
n4136, n4137, n4138, n4139, n4140, n4141, n4142, n4143, n4144, n4145,
n4146, n4147, n4148, n4149, n4150, n4151, n4152, n4153, n4154, n4155,
n4156, n4157, n4158, n4159, n4160, n4161, n4162, n4163, n4164, n4165,
n4166, n4167, n4168, n4169, n4170, n4171, n4172, n4173, n4174, n4175,
n4176, n4177, n4178, n4179, n4180, n4181, n4182, n4183, n4184, n4185,
n4186, n4187, n4188, n4189, n4190, n4191, n4192, n4193, n4194, n4195,
n4196, n4197, n4198, n4199, n4200, n4201, n4202, n4203, n4204, n4205,
n4206, n4207, n4208, n4209, n4210, n4211, n4212, n4213, n4214, n4215,
n4216, n4217, n4218, n4219, n4220, n4221, n4222, n4223, n4224, n4225,
n4226, n4227, n4228, n4229, n4230, n4231, n4232, n4233, n4234, n4235,
n4236, n4237, n4238, n4239, n4240, n4241, n4242, n4243, n4244, n4245,
n4246, n4247, n4248, n4249, n4250, n4251, n4252, n4253, n4254, n4255,
n4256, n4257, n4258, n4259, n4260, n4261, n4262, n4263, n4264, n4265,
n4266, n4267, n4268, n4269, n4270, n4271, n4272, n4273, n4274, n4275,
n4276, n4277, n4278, n4279, n4280, n4281, n4282, n4283, n4284, n4285,
n4286, n4287, n4288, n4289, n4290, n4291, n4292, n4293, n4294, n4295,
n4296, n4297, n4298, n4299, n4300, n4301, n4302, n4303, n4304, n4305,
n4306, n4307, n4308, n4309, n4310, n4311, n4312, n4313, n4314, n4315,
n4316, n4317, n4318, n4319, n4320, n4321, n4322, n4323, n4324, n4325,
n4326, n4327, n4328, n4329, n4330, n4331, n4332, n4333, n4334, n4335,
n4336, n4337, n4338, n4339, n4340, n4341, n4342, n4343, n4344, n4345,
n4346, n4347, n4348, n4349, n4350, n4351, n4352, n4353, n4354, n4355,
n4356, n4357, n4358, n4359, n4360, n4361, n4362, n4363, n4364, n4365,
n4366, n4367, n4368, n4369, n4370, n4371, n4372, n4373, n4374, n4375,
n4376, n4377, n4378, n4379, n4380, n4381, n4382, n4383, n4384, n4385,
n4386, n4387, n4388, n4389, n4390, n4391, n4392, n4393, n4394, n4395,
n4396, n4397, n4398, n4399, n4400, n4401, n4402, n4403, n4404, n4405,
n4406, n4407, n4408, n4409, n4410, n4411, n4412, n4413, n4414, n4415,
n4416, n4417, n4418, n4419, n4420, n4421, n4422, n4423, n4424, n4425,
n4426, n4427, n4428, n4429, n4430, n4431, n4432, n4433, n4434, n4435,
n4436, n4437, n4438, n4439, n4440, n4441, n4442, n4443, n4444, n4445,
n4446, n4447, n4448, n4449, n4450, n4451, n4452, n4453, n4454, n4455,
n4456, n4457, n4458, n4459, n4460, n4461, n4462, n4463, n4464, n4465,
n4466, n4467, n4468, n4469, n4470, n4471, n4472, n4473, n4474, n4475,
n4476, n4477, n4478, n4479, n4480, n4481, n4482, n4483, n4484, n4485,
n4486, n4487, n4488, n4489, n4490, n4491, n4492, n4493, n4494, n4495,
n4496, n4497, n4498, n4499, n4500, n4501, n4502, n4503, n4504, n4505,
n4506, n4507, n4508, n4509, n4510, n4511, n4512, n4513, n4514, n4515,
n4516, n4517, n4518, n4519, n4520, n4521, n4522, n4523, n4524, n4525,
n4526, n4527, n4528, n4529, n4530, n4531, n4532, n4533, n4534, n4535,
n4536, n4537, n4538, n4539, n4540, n4541, n4542, n4543, n4544, n4545,
n4546, n4547, n4548, n4549, n4550, n4551, n4552, n4553, n4554, n4555,
n4556, n4557, n4558, n4559, n4560, n4561, n4562, n4563, n4564, n4565,
n4566, n4567, n4568, n4569, n4570, n4571, n4572, n4573, n4574, n4575,
n4576, n4577, n4578, n4579, n4580, n4581, n4582, n4583, n4584, n4585,
n4586, n4587, n4588, n4589, n4590, n4591, n4592, n4593, n4594, n4595,
n4596, n4597, n4598, n4599, n4600, n4601, n4602, n4603, n4604, n4605,
n4606, n4607, n4608, n4609, n4610, n4611, n4612, n4613, n4614, n4615,
n4616, n4617, n4618, n4619, n4620, n4621, n4622, n4623, n4624, n4625,
n4626, n4627, n4628, n4629, n4630, n4631, n4632, n4633, n4634, n4635,
n4636, n4637, n4638, n4639, n4640, n4641, n4642, n4643, n4644, n4645,
n4646, n4647, n4648, n4649, n4650, n4651, n4652, n4653, n4654, n4655,
n4656, n4657, n4658, n4659, n4660, n4661, n4662, n4663, n4664, n4665,
n4666, n4667, n4668, n4669, n4670, n4671, n4672, n4673, n4674, n4675,
n4676, n4677, n4678, n4679, n4680, n4681, n4682, n4683, n4684, n4685,
n4686, n4687, n4688, n4689, n4690, n4691, n4692, n4693, n4694, n4695,
n4696, n4697, n4698, n4699, n4700, n4701, n4702, n4703, n4704, n4705,
n4706, n4707, n4708, n4709, n4710, n4711, n4712, n4713, n4714, n4715,
n4716, n4717, n4718, n4719, n4720, n4721, n4722, n4723, n4724, n4725,
n4726, n4727, n4728, n4729, n4730, n4731, n4732, n4733, n4734, n4735,
n4736, n4737, n4738, n4739, n4740, n4741, n4742, n4743, n4744, n4745,
n4746, n4747, n4748, n4749, n4750, n4751, n4752, n4753, n4754, n4755,
n4756, n4757, n4758, n4759, n4760, n4761, n4762, n4763, n4764, n4765,
n4766, n4767, n4768, n4769, n4770, n4771, n4772, n4773, n4774, n4775,
n4776, n4777, n4778, n4779, n4780, n4781, n4782, n4783, n4784, n4785,
n4786, n4787, n4788, n4789, n4790, n4791, n4792, n4793, n4794, n4795,
n4796, n4797, n4798, n4799, n4800, n4801, n4802, n4803, n4804, n4805,
n4806, n4807, n4808, n4809, n4810, n4811, n4812, n4813, n4814, n4815,
n4816, n4817, n4818, n4819, n4820, n4821, n4822, n4823, n4824, n4825,
n4826, n4827, n4828, n4829, n4830, n4831, n4832, n4833, n4834, n4835,
n4836, n4837, n4838, n4839, n4840, n4841, n4842, n4843, n4844, n4845,
n4846, n4847, n4848, n4849, n4850, n4851, n4852, n4853, n4854, n4855,
n4856, n4857, n4858, n4859, n4860, n4861, n4862, n4863, n4864, n4865,
n4866, n4867, n4868, n4869, n4870, n4871, n4872, n4873, n4874, n4875,
n4876, n4877, n4878, n4879, n4880, n4881, n4882, n4883, n4884, n4885,
n4886, n4887, n4888, n4889, n4890, n4891, n4892, n4893, n4894, n4895,
n4896, n4897, n4898, n4899, n4900, n4901, n4902, n4903, n4904, n4905,
n4906, n4907, n4908, n4909, n4910, n4911, n4912, n4913, n4914, n4915,
n4916, n4917, n4918, n4919, n4920, n4921, n4922, n4923, n4924, n4925,
n4926, n4927, n4928, n4929, n4930, n4931, n4932, n4933, n4934, n4935,
n4936, n4937, n4938, n4939, n4940, n4941, n4942, n4943, n4944, n4945,
n4946, n4947, n4948, n4949, n4950, n4951, n4952, n4953, n4954, n4955,
n4956, n4957, n4958, n4959, n4960, n4961, n4962, n4963, n4964, n4965,
n4966, n4967, n4968, n4969, n4970, n4971, n4972, n4973, n4974, n4975,
n4976, n4977, n4978, n4979, n4980, n4981, n4982, n4983, n4984, n4985,
n4986, n4987, n4988, n4989, n4990, n4991, n4992, n4993, n4994, n4995,
n4996, n4997, n4998, n4999, n5000, n5001, n5002, n5003, n5004, n5005,
n5006, n5007, n5008, n5009, n5010, n5011, n5012, n5013, n5014, n5015,
n5016, n5017, n5018, n5019, n5020, n5021, n5022, n5023, n5024, n5025,
n5026, n5027, n5028, n5029, n5030, n5031, n5032, n5033, n5034, n5035,
n5036, n5037, n5038, n5039, n5040, n5041, n5042, n5043, n5044, n5045,
n5046, n5047, n5048, n5049, n5050, n5051, n5052, n5053, n5054, n5055,
n5056, n5057, n5058, n5059, n5060, n5061, n5062, n5063, n5064, n5065,
n5066, n5067, n5068, n5069, n5070, n5071, n5072, n5073, n5074, n5075,
n5076, n5077, n5078, n5079, n5080, n5081, n5082, n5083, n5084, n5085,
n5086, n5087, n5088, n5089, n5090, n5091, n5092, n5093, n5094, n5095,
n5096, n5097, n5098, n5099, n5100, n5101, n5102, n5103, n5104, n5105,
n5106, n5107, n5108, n5109, n5110, n5111, n5112, n5113, n5114, n5115,
n5116, n5117, n5118, n5119, n5120, n5121, n5122, n5123, n5124, n5125,
n5126, n5127, n5128, n5129, n5130, n5131, n5132, n5133, n5134, n5135,
n5136, n5137, n5138, n5139, n5140, n5141, n5142, n5143, n5144, n5145,
n5146, n5147, n5148, n5149, n5150, n5151, n5152, n5153, n5154, n5155,
n5156, n5157, n5158, n5159, n5160, n5161, n5162, n5163, n5164, n5165,
n5166, n5167, n5168, n5169, n5170, n5171, n5172, n5173, n5174, n5175,
n5176, n5177, n5178, n5179, n5180, n5181, n5182, n5183, n5184, n5185,
n5186, n5187, n5188, n5189, n5190, n5191, n5192, n5193, n5194, n5195,
n5196, n5197, n5198, n5199, n5200, n5201, n5202, n5203, n5204, n5205,
n5206, n5207, n5208, n5209, n5210, n5211, n5212, n5213, n5214, n5215,
n5216, n5217, n5218, n5219, n5220, n5221, n5222, n5223, n5224, n5225,
n5226, n5227, n5228, n5229, n5230, n5231, n5232, n5233, n5234, n5235,
n5236, n5237, n5238, n5239, n5240, n5241, n5242, n5243, n5244, n5245,
n5246, n5247, n5248, n5249, n5250, n5251, n5252, n5253, n5254, n5255,
n5256, n5257, n5258, n5259, n5260, n5261, n5262, n5263, n5264, n5265,
n5266, n5267, n5268, n5269, n5270, n5271, n5272, n5273, n5274, n5275,
n5276, n5277, n5278, n5279, n5280, n5281, n5282, n5283, n5284, n5285,
n5286, n5287, n5288, n5289, n5290, n5291, n5292, n5293, n5294, n5295,
n5296, n5297, n5298, n5299, n5300, n5301, n5302, n5303, n5304, n5305,
n5306, n5307, n5308, n5309, n5310, n5311, n5312, n5313, n5314, n5315,
n5316, n5317, n5318, n5319, n5320, n5321, n5322, n5323, n5324, n5325,
n5326, n5327, n5328, n5329, n5330, n5331, n5332, n5333, n5334, n5335,
n5336, n5337, n5338, n5339, n5340, n5341, n5342, n5343, n5344, n5345,
n5346, n5347, n5348, n5349, n5350, n5351, n5352, n5353, n5354, n5355,
n5356, n5357, n5358, n5359, n5360, n5361, n5362, n5363, n5364, n5365,
n5366, n5367, n5368, n5369, n5370, n5371, n5372, n5373, n5374, n5375,
n5376, n5377, n5378, n5379, n5380, n5381, n5382, n5383, n5384, n5385,
n5386, n5387, n5388, n5389, n5390, n5391, n5392, n5393, n5394, n5395,
n5396, n5397, n5398, n5399, n5400, n5401, n5402, n5403, n5404, n5405,
n5406, n5407, n5408, n5409, n5410, n5411, n5412, n5413, n5414, n5415,
n5416, n5417, n5418, n5419, n5420, n5421, n5422, n5423, n5424, n5425,
n5426, n5427, n5428, n5429, n5430, n5431, n5432, n5433, n5434, n5435,
n5436, n5437, n5438, n5439, n5440, n5441, n5442, n5443, n5444, n5445,
n5446, n5447, n5448, n5449, n5450, n5451, n5452, n5453, n5454, n5455,
n5456, n5457, n5458, n5459, n5460, n5461, n5462, n5463, n5464, n5465,
n5466, n5467, n5468, n5469, n5470, n5471, n5472, n5473, n5474, n5475,
n5476, n5477, n5478, n5479, n5480, n5481, n5482, n5483, n5484, n5485,
n5486, n5487, n5488, n5489, n5490, n5491, n5492, n5493, n5494, n5495,
n5496, n5497, n5498, n5499, n5500, n5501, n5502, n5503, n5504, n5505,
n5506, n5507, n5508, n5509, n5510, n5511, n5512, n5513, n5514, n5515,
n5516, n5517, n5518, n5519, n5520, n5521, n5522, n5523, n5524, n5525,
n5526, n5527, n5528, n5529, n5530, n5531, n5532, n5533, n5534, n5535,
n5536, n5537, n5538, n5539, n5540, n5541, n5542, n5543, n5544, n5545,
n5546, n5547, n5548, n5549, n5550, n5551, n5552, n5553, n5554, n5555,
n5556, n5557, n5558, n5559, n5560, n5561, n5562, n5563, n5564, n5565,
n5566, n5567, n5568, n5569, n5570, n5571, n5572, n5573, n5574, n5575,
n5576, n5577, n5578, n5579, n5580, n5581, n5582, n5583, n5584, n5585,
n5586, n5587, n5588, n5589, n5590, n5591, n5592, n5593, n5594, n5595,
n5596, n5597, n5598, n5599, n5600, n5601, n5602, n5603, n5604, n5605,
n5606, n5607, n5608, n5609, n5610, n5611, n5612, n5613, n5614, n5615,
n5616, n5617, n5618, n5619, n5620, n5621, n5622, n5623, n5624, n5625,
n5626, n5627, n5628, n5629, n5630, n5631, n5632, n5633, n5634, n5635,
n5636, n5637, n5638, n5639, n5640, n5641, n5642, n5643, n5644, n5645,
n5646, n5647, n5648, n5649, n5650, n5651, n5652, n5653, n5654, n5655,
n5656, n5657, n5658, n5659, n5660, n5661, n5662, n5663, n5664, n5665,
n5666, n5667, n5668, n5669, n5670, n5671, n5672, n5673, n5674, n5675,
n5676, n5677, n5678, n5679, n5680, n5681, n5682, n5683, n5684, n5685,
n5686, n5687, n5688, n5689, n5690, n5691, n5692, n5693, n5694, n5695,
n5696, n5697, n5698, n5699, n5700, n5701, n5702, n5703, n5704, n5705,
n5706, n5707, n5708, n5709, n5710, n5711, n5712, n5713, n5714, n5715,
n5716, n5717, n5718, n5719, n5720, n5721, n5722, n5723, n5724, n5725,
n5726, n5727, n5728, n5729, n5730, n5731, n5732, n5733, n5734, n5735,
n5736, n5737, n5738, n5739, n5740, n5741, n5742, n5743, n5744, n5745,
n5746, n5747, n5748, n5749, n5750, n5751, n5752, n5753, n5754, n5755,
n5756, n5757, n5758, n5759, n5760, n5761, n5762, n5763, n5764, n5765,
n5766, n5767, n5768, n5769, n5770, n5771, n5772, n5773, n5774, n5775,
n5776, n5777, n5778, n5779, n5780, n5781, n5782, n5783, n5784, n5785,
n5786, n5787, n5788, n5789, n5790, n5791, n5792, n5793, n5794, n5795,
n5796, n5797, n5798, n5799, n5800, n5801, n5802, n5803, n5804, n5805,
n5806, n5807, n5808, n5809, n5810, n5811, n5812, n5813, n5814, n5815,
n5816, n5817, n5818, n5819, n5820, n5821, n5822, n5823, n5824, n5825,
n5826, n5827, n5828, n5829, n5830, n5831, n5832, n5833, n5834, n5835,
n5836, n5837, n5838, n5839, n5840, n5841, n5842, n5843, n5844, n5845,
n5846, n5847, n5848, n5849, n5850, n5851, n5852, n5853, n5854, n5855,
n5856, n5857, n5858, n5859, n5860, n5861, n5862, n5863, n5864, n5865,
n5866, n5867, n5868, n5869, n5870, n5871, n5872, n5873, n5874, n5875,
n5876, n5877, n5878, n5879, n5880, n5881, n5882, n5883, n5884, n5885,
n5886, n5887, n5888, n5889, n5890, n5891, n5892, n5893, n5894, n5895,
n5896, n5897, n5898, n5899, n5900, n5901, n5902, n5903, n5904, n5905,
n5906, n5907, n5908, n5909, n5910, n5911, n5912, n5913, n5914, n5915,
n5916, n5917, n5918, n5919, n5920, n5921, n5922, n5923, n5924, n5925,
n5926, n5927, n5928, n5929, n5930, n5931, n5932, n5933, n5934, n5935,
n5936, n5937, n5938, n5939, n5940, n5941, n5942, n5943, n5944, n5945,
n5946, n5947, n5948, n5949, n5950, n5951, n5952, n5953, n5954, n5955,
n5956, n5957, n5958, n5959, n5960, n5961, n5962, n5963, n5964, n5965,
n5966, n5967, n5968, n5969, n5970, n5971, n5972, n5973, n5974, n5975,
n5976, n5977, n5978, n5979, n5980, n5981, n5982, n5983, n5984, n5985,
n5986, n5987, n5988, n5989, n5990, n5991, n5992, n5993, n5994, n5995,
n5996, n5997, n5998, n5999, n6000, n6001, n6002, n6003, n6004, n6005,
n6006, n6007, n6008, n6009, n6010, n6011, n6012, n6013, n6014, n6015,
n6016, n6017, n6018, n6019, n6020, n6021, n6022, n6023, n6024, n6025,
n6026, n6027, n6028, n6029, n6030, n6031, n6032, n6033, n6034, n6035,
n6036, n6037, n6038, n6039, n6040, n6041, n6042, n6043, n6044, n6045,
n6046, n6047, n6048, n6049, n6050, n6051, n6052, n6053, n6054, n6055,
n6056, n6057, n6058, n6059, n6060, n6061, n6062, n6063, n6064, n6065,
n6066, n6067, n6068, n6069, n6070, n6071, n6072, n6073, n6074, n6075,
n6076, n6077, n6078, n6079, n6080, n6081, n6082, n6083, n6084, n6085,
n6086, n6087, n6088, n6089, n6090, n6091, n6093, n6094, n6095, n6096,
n6097, n6098, n6099, n6100, n6101, n6102, n6103, n6104, n6105, n6106,
n6107, n6108, n6109, n6110, n6111, n6112, n6113, n6114, n6115, n6116,
n6117, n6118, n6119, n6120, n6121, n6122, n6123, n6124, n6125, n6126,
n6127, n6128, n6129, n6130, n6131, n6132, n6133, n6134, n6135, n6136,
n6137, n6138, n6139, n6140, n6141, n6142, n6143, n6144, n6145, n6146,
n6147, n6148, n6149, n6150, n6151, n6152, n6153, n6154, n6155, n6156,
n6157, n6158, n6159, n6160, n6161, n6162, n6163, n6164, n6165, n6166,
n6167, n6168, n6169, n6170, n6171, n6172, n6173, n6174, n6175, n6176,
n6177, n6178, n6179, n6180, n6181, n6182, n6183, n6184, n6185, n6186,
n6187, n6188, n6189, n6190, n6191, n6192, n6193, n6194, n6195, n6196,
n6197, n6198, n6199, n6200, n6201, n6202, n6203, n6204, n6205, n6206,
n6207, n6208, n6209, n6210, n6211, n6212, n6213, n6214, n6215, n6216,
n6217, n6218, n6219, n6220, n6221, n6222, n6223, n6224, n6225, n6226,
n6227, n6228, n6229, n6230, n6231, n6232, n6233, n6234, n6235, n6236,
n6237, n6238, n6239, n6240, n6241, n6242, n6243, n6244, n6245, n6246,
n6247, n6248, n6249, n6250, n6251, n6252, n6253, n6254, n6255, n6256,
n6257, n6258, n6259, n6260, n6261, n6262, n6263, n6264, n6265, n6266,
n6267, n6268, n6269, n6270, n6271, n6272, n6273, n6274, n6275, n6276,
n6277, n6278, n6279, n6280, n6281, n6282, n6283, n6284, n6285, n6286,
n6287, n6288, n6289, n6290, n6291, n6292, n6293, n6294, n6295, n6296,
n6297, n6298, n6299, n6300, n6301, n6302, n6303, n6304, n6305, n6306,
n6307, n6308, n6309, n6310, n6311, n6312, n6313, n6314, n6315, n6316,
n6317, n6318, n6319, n6320, n6321, n6322, n6323, n6324, n6325, n6326,
n6327, n6328, n6329, n6330, n6331, n6332, n6333, n6334, n6335, n6336,
n6337, n6338, n6339, n6340, n6341, n6342, n6343, n6344, n6345, n6346,
n6347, n6348, n6349, n6350, n6351, n6352, n6353, n6354, n6355, n6356,
n6357, n6358, n6359, n6360, n6361, n6362, n6363, n6364, n6365, n6366,
n6367, n6368, n6369, n6370, n6371, n6372, n6373, n6374, n6375, n6376,
n6377, n6378, n6379, n6380, n6381, n6382, n6383, n6384, n6385, n6386,
n6387, n6388, n6389, n6390, n6391, n6392, n6393, n6394, n6395, n6396,
n6397, n6398, n6399, n6400, n6401, n6402, n6403, n6404, n6405, n6406,
n6407, n6408, n6409, n6410, n6411, n6412, n6413, n6414, n6415, n6416,
n6417, n6418, n6419, n6420, n6421, n6422, n6423, n6424, n6425, n6426,
n6427, n6428, n6429, n6430, n6431, n6432, n6433, n6434, n6435, n6436,
n6437, n6438, n6439, n6440, n6441, n6442, n6443, n6444, n6445, n6446,
n6447, n6448, n6449, n6450, n6451, n6452, n6453, n6454, n6455, n6456,
n6457, n6458, n6459, n6460, n6461, n6462, n6463, n6464, n6465, n6466,
n6467, n6468, n6469, n6470, n6471, n6472, n6473, n6474, n6475, n6476,
n6477, n6478, n6479, n6480, n6481, n6482, n6483, n6484, n6485, n6486,
n6487, n6488, n6489, n6490, n6491, n6492, n6493, n6494, n6495, n6496,
n6497, n6498, n6499, n6500, n6501, n6502, n6503, n6504, n6505, n6506,
n6507, n6508, n6509, n6510, n6511, n6512, n6513, n6514, n6515, n6516,
n6517, n6518, n6519, n6520, n6521, n6522, n6523, n6524, n6525, n6526,
n6527, n6528, n6529, n6530, n6531, n6532, n6533, n6534, n6535, n6536,
n6537, n6538, n6539, n6540, n6541, n6542, n6543, n6544, n6545, n6546,
n6547, n6548, n6549, n6550, n6551, n6552, n6553, n6554, n6555, n6556,
n6557, n6558, n6559, n6560, n6561, n6562, n6563, n6564, n6565, n6566,
n6567, n6568, n6569, n6570, n6571, n6572, n6573, n6574, n6575, n6576,
n6577, n6578, n6579, n6580, n6581, n6582, n6583, n6584, n6585, n6586,
n6587, n6588, n6589, n6590, n6591, n6592, n6593, n6594, n6595, n6596,
n6597, n6598, n6599, n6600, n6601, n6602, n6603, n6604, n6605, n6606,
n6607, n6608, n6609, n6610, n6611, n6612, n6613, n6614, n6615, n6616,
n6617, n6618, n6619, n6620, n6621, n6622, n6623, n6624, n6625, n6626,
n6627, n6628, n6629, n6630, n6631, n6632, n6633, n6634, n6635, n6636,
n6637, n6638, n6639, n6640, n6641, n6642, n6659, n6660, n6661, n6662,
n6663, n6664, n6665, n6666, n6667, n6668, n6669, n6670, n6671, n6672,
n6673, n6674, n6675, n6676, n6677, n6678, n6679, n6680, n6681, n6682,
n6683, n6684, n6685, n6686, n6687, n6688, n6689, n6690, n6691, n6692,
n6693, n6694, n6695, n6696, n6697, n6698, n6699, n6700, n6701, n6702,
n6703, n6704, n6705, n6706, n6707, n6708, n6709, n6710, n6711, n6712,
n6713, n6714, n6715, n6716, n6717, n6718, n6719, n6720, n6721, n6722,
n6723, n6724, n6725, n6726, n6727, n6728, n6729, n6730, n6731, n6732,
n6733, n6734, n6735, n6736, n6737, n6738, n6739, n6740, n6741, n6742,
n6743, n6744, n6745, n6746, n6747, n6748, n6749, n6750, n6751, n6752,
n6753, n6754, n6755, n6756, n6757, n6758, n6759, n6760, n6761, n6762,
n6763, n6764, n6765, n6766, n6767, n6768, n6769, n6770, n6771, n6772,
n6773, n6774, n6775, n6776, n6777, n6778, n6779, n6780, n6781, n6782,
n6783, n6784, n6785, n6786, n6787, n6788, n6789, n6790, n6791, n6792,
n6793, n6794, n6795, n6796, n6797, n6798, n6799, n6800, n6801, n6802,
n6803, n6804, n6805, n6806, n6807, n6808, n6809, n6810, n6811, n6812,
n6813, n6814, n6815, n6816, n6817, n6818, n6819, n6820, n6821, n6822,
n6823, n6824, n6825, n6826, n6827, n6828, n6829, n6830, n6831, n6832,
n6833, n6834, n6835, n6836, n6837, n6838, n6839, n6840, n6841, n6842,
n6843, n6844, n6845, n6846, n6847, n6848, n6849, n6850, n6851, n6852,
n6853, n6854, n6855, n6856, n6857, n6858, n6859, n6860, n6861, n6862,
n6863, n6864, n6865, n6866, n6867, n6868, n6869, n6870, n6871, n6872,
n6873, n6874, n6875, n6876, n6877, n6878, n6879, n6880, n6881, n6882,
n6883, n6884, n6885, n6886, n6887, n6888, n6889, n6890, n6891, n6892,
n6893, n6894, n6895, n6896, n6897, n6898, n6899, n6900, n6901, n6902,
n6903, n6904, n6905, n6906, n6907, n6908, n6909, n6910, n6911, n6912,
n6913, n6914, n6915, n6916, n6917, n6918, n6919, n6920, n6921, n6922,
n6923, n6924, n6925, n6926, n6927, n6928, n6929, n6930, n6931, n6932,
n6933, n6934, n6935, n6936, n6937, n6938, n6939, n6940, n6941, n6942,
n6943, n6944, n6945, n6946, n6947, n6948, n6949, n6950, n6951, n6952,
n6953, n6954, n6955, n6956, n6957, n6958, n6959, n6960, n6961, n6962,
n6963, n6964, n6965, n6966, n6967, n6968, n6969, n6970, n6971, n6972,
n6973, n6974, n6975, n6976, n6977, n6978, n6979, n6980, n6981, n6982,
n6983, n6984, n6985, n6986, n6987, n6988, n6989, n6990, n6991, n6992,
n6993, n6994, n6995, n6996, n6997, n6998, n6999, n7000, n7001, n7002,
n7003, n7004, n7005, n7006, n7007, n7008, n7009, n7010, n7011, n7012;
wire [31:23] dataA;
wire [31:23] dataB;
wire [31:0] cordic_result;
wire [30:0] result_add_subt;
wire [31:0] mult_result;
wire [30:0] FPSENCOS_sign_inv_out;
wire [1:0] FPSENCOS_sel_mux_2_reg;
wire [27:0] FPSENCOS_d_ff3_LUT_out;
wire [31:0] FPSENCOS_d_ff3_sh_y_out;
wire [31:0] FPSENCOS_d_ff3_sh_x_out;
wire [31:0] FPSENCOS_d_ff2_Z;
wire [31:0] FPSENCOS_d_ff2_Y;
wire [31:0] FPSENCOS_d_ff2_X;
wire [31:0] FPSENCOS_d_ff_Zn;
wire [31:0] FPSENCOS_d_ff_Yn;
wire [31:0] FPSENCOS_d_ff_Xn;
wire [31:0] FPSENCOS_d_ff1_Z;
wire [3:0] FPSENCOS_cont_iter_out;
wire [1:0] FPSENCOS_cont_var_out;
wire [1:0] FPSENCOS_d_ff1_shift_region_flag_out;
wire [23:0] FPMULT_Sgf_normalized_result;
wire [23:0] FPMULT_Add_result;
wire [8:0] FPMULT_S_Oper_A_exp;
wire [7:0] FPMULT_exp_oper_result;
wire [31:0] FPMULT_Op_MY;
wire [31:0] FPMULT_Op_MX;
wire [1:0] FPMULT_FSM_selector_B;
wire [30:0] FPMULT_P_Sgf;
wire [25:0] FPADDSUB_Sgf_normalized_result;
wire [25:0] FPADDSUB_Add_Subt_result;
wire [4:0] FPADDSUB_LZA_output;
wire [7:0] FPADDSUB_exp_oper_result;
wire [30:0] FPADDSUB_DmP;
wire [30:0] FPADDSUB_DMP;
wire [31:0] FPADDSUB_intDY;
wire [31:0] FPADDSUB_intDX;
wire [1:0] FPADDSUB_FSM_selector_B;
wire [3:0] FPSENCOS_cordic_FSM_state_reg;
wire [3:0] FPMULT_FS_Module_state_reg;
wire [8:0] FPMULT_Exp_module_Data_S;
wire [47:31] FPMULT_Sgf_operation_Result;
wire [3:0] FPADDSUB_FS_Module_state_reg;
wire [51:0] FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array;
DFFRXLTS operation_dff_Q_reg_1_ ( .D(operation[2]), .CK(clk), .RN(n6921),
.QN(n2203) );
DFFRXLTS reg_dataA_Q_reg_24_ ( .D(Data_1[24]), .CK(clk), .RN(n6914), .Q(
dataA[24]) );
DFFRXLTS reg_dataA_Q_reg_26_ ( .D(Data_1[26]), .CK(clk), .RN(n6942), .Q(
dataA[26]) );
DFFRXLTS reg_dataA_Q_reg_31_ ( .D(Data_1[31]), .CK(clk), .RN(n6912), .Q(
dataA[31]) );
DFFRXLTS reg_dataB_Q_reg_29_ ( .D(Data_2[29]), .CK(clk), .RN(n6915), .Q(
dataB[29]) );
DFFRXLTS reg_dataB_Q_reg_31_ ( .D(Data_2[31]), .CK(clk), .RN(n6915), .Q(
dataB[31]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n2061), .CK(clk),
.RN(n6988), .Q(FPMULT_Op_MY[31]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_22_ ( .D(n2046), .CK(clk),
.RN(n6997), .Q(FPMULT_Op_MX[22]), .QN(n2829) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_21_ ( .D(n2045), .CK(clk),
.RN(n6997), .Q(FPMULT_Op_MX[21]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_19_ ( .D(n2043), .CK(clk),
.RN(n2215), .Q(FPMULT_Op_MX[19]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_18_ ( .D(n2042), .CK(clk),
.RN(n6988), .Q(FPMULT_Op_MX[18]), .QN(n2812) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_17_ ( .D(n2041), .CK(clk),
.RN(n6987), .Q(FPMULT_Op_MX[17]), .QN(n2824) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_16_ ( .D(n2040), .CK(clk),
.RN(n6990), .Q(FPMULT_Op_MX[16]), .QN(n2799) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_15_ ( .D(n2039), .CK(clk),
.RN(n6988), .Q(FPMULT_Op_MX[15]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_14_ ( .D(n2038), .CK(clk),
.RN(n6989), .Q(FPMULT_Op_MX[14]), .QN(n2186) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_13_ ( .D(n2037), .CK(clk),
.RN(n6989), .Q(FPMULT_Op_MX[13]), .QN(n2818) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_12_ ( .D(n2036), .CK(clk),
.RN(n2215), .Q(FPMULT_Op_MX[12]), .QN(n2173) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_11_ ( .D(n2035), .CK(clk),
.RN(n6987), .Q(FPMULT_Op_MX[11]), .QN(n2827) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_10_ ( .D(n2034), .CK(clk),
.RN(n6995), .Q(FPMULT_Op_MX[10]), .QN(n2811) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_9_ ( .D(n2033), .CK(clk),
.RN(n6995), .Q(FPMULT_Op_MX[9]), .QN(n2810) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_8_ ( .D(n2032), .CK(clk),
.RN(n6995), .Q(FPMULT_Op_MX[8]), .QN(n2808) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_7_ ( .D(n2031), .CK(clk),
.RN(n6995), .Q(FPMULT_Op_MX[7]), .QN(n2813) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_6_ ( .D(n2030), .CK(clk),
.RN(n6995), .Q(FPMULT_Op_MX[6]), .QN(n2174) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_5_ ( .D(n2201), .CK(clk),
.RN(n6995), .Q(FPMULT_Op_MX[5]), .QN(n2820) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_3_ ( .D(n2027), .CK(clk),
.RN(n6995), .Q(FPMULT_Op_MX[3]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_2_ ( .D(n2026), .CK(clk),
.RN(n6995), .Q(FPMULT_Op_MX[2]), .QN(n2804) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_1_ ( .D(n2025), .CK(clk),
.RN(n6995), .Q(FPMULT_Op_MX[1]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_0_ ( .D(n2024), .CK(clk),
.RN(n6994), .Q(FPMULT_Op_MX[0]), .QN(n2164) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n1989), .CK(clk), .RN(
n6992), .Q(FPMULT_Add_result[0]) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_22_ ( .D(n2014), .CK(clk),
.RN(n6996), .Q(FPMULT_Op_MY[22]), .QN(n2828) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_21_ ( .D(n2013), .CK(clk),
.RN(n6985), .Q(FPMULT_Op_MY[21]), .QN(n2803) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_20_ ( .D(n2012), .CK(clk),
.RN(n6996), .Q(FPMULT_Op_MY[20]) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_19_ ( .D(n2200), .CK(clk),
.RN(n6991), .Q(FPMULT_Op_MY[19]), .QN(n2819) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_18_ ( .D(n2010), .CK(clk),
.RN(n6991), .Q(FPMULT_Op_MY[18]) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_17_ ( .D(n2009), .CK(clk),
.RN(n6989), .Q(FPMULT_Op_MY[17]), .QN(n2806) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_16_ ( .D(n2008), .CK(clk),
.RN(n2215), .Q(FPMULT_Op_MY[16]) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_14_ ( .D(n2006), .CK(clk),
.RN(n6989), .Q(FPMULT_Op_MY[14]) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_12_ ( .D(n2004), .CK(clk),
.RN(n6985), .Q(FPMULT_Op_MY[12]), .QN(n2816) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_11_ ( .D(n2003), .CK(clk),
.RN(n6987), .Q(FPMULT_Op_MY[11]), .QN(n2163) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_10_ ( .D(n2002), .CK(clk),
.RN(n6991), .Q(FPMULT_Op_MY[10]), .QN(n2809) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_9_ ( .D(n2001), .CK(clk),
.RN(n6996), .Q(FPMULT_Op_MY[9]), .QN(n2814) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_8_ ( .D(n2000), .CK(clk),
.RN(n6990), .Q(FPMULT_Op_MY[8]) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_7_ ( .D(n1999), .CK(clk),
.RN(n6996), .Q(FPMULT_Op_MY[7]), .QN(n2815) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_6_ ( .D(n1998), .CK(clk),
.RN(n2215), .Q(FPMULT_Op_MY[6]), .QN(n2123) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_5_ ( .D(n1997), .CK(clk),
.RN(n6991), .Q(FPMULT_Op_MY[5]), .QN(n2817) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_4_ ( .D(n1996), .CK(clk),
.RN(n6990), .Q(FPMULT_Op_MY[4]) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_3_ ( .D(n1995), .CK(clk),
.RN(n6988), .Q(FPMULT_Op_MY[3]), .QN(n2801) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_1_ ( .D(n1993), .CK(clk),
.RN(n6989), .Q(FPMULT_Op_MY[1]), .QN(n2807) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_0_ ( .D(n1992), .CK(clk),
.RN(n6985), .Q(FPMULT_Op_MY[0]), .QN(n2166) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_23_ ( .D(n1941), .CK(clk),
.RN(n6929), .Q(FPMULT_P_Sgf[23]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_1_ ( .D(n1919), .CK(clk),
.RN(n6926), .Q(FPMULT_P_Sgf[1]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_0_ ( .D(n1918), .CK(clk),
.RN(n6927), .Q(FPMULT_P_Sgf[0]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n1990), .CK(
clk), .RN(n6996), .Q(FPMULT_Sgf_normalized_result[23]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(
n1880), .CK(clk), .RN(n6990), .Q(mult_result[23]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(
n1879), .CK(clk), .RN(n6985), .Q(mult_result[24]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(
n1878), .CK(clk), .RN(n6991), .Q(mult_result[25]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(
n1877), .CK(clk), .RN(n6986), .Q(mult_result[26]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(
n1876), .CK(clk), .RN(n6986), .Q(mult_result[27]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(
n1875), .CK(clk), .RN(n6986), .Q(mult_result[28]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(
n1874), .CK(clk), .RN(n6986), .Q(mult_result[29]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(
n1873), .CK(clk), .RN(n6986), .Q(mult_result[30]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(
n1872), .CK(clk), .RN(n6986), .Q(mult_result[0]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(
n1871), .CK(clk), .RN(n6986), .Q(mult_result[1]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(
n1870), .CK(clk), .RN(n6986), .Q(mult_result[2]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(
n1869), .CK(clk), .RN(n6986), .Q(mult_result[3]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(
n1868), .CK(clk), .RN(n6986), .Q(mult_result[4]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(
n1867), .CK(clk), .RN(n6989), .Q(mult_result[5]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(
n1866), .CK(clk), .RN(n2216), .Q(mult_result[6]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(
n1865), .CK(clk), .RN(n6987), .Q(mult_result[7]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(
n1864), .CK(clk), .RN(n6996), .Q(mult_result[8]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(
n1863), .CK(clk), .RN(n6988), .Q(mult_result[9]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(
n1862), .CK(clk), .RN(n6989), .Q(mult_result[10]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(
n1861), .CK(clk), .RN(n6988), .Q(mult_result[11]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(
n1860), .CK(clk), .RN(n6991), .Q(mult_result[12]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(
n1859), .CK(clk), .RN(n2216), .Q(mult_result[13]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(
n1858), .CK(clk), .RN(n6996), .Q(mult_result[14]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(
n1857), .CK(clk), .RN(n6984), .Q(mult_result[15]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(
n1856), .CK(clk), .RN(n6984), .Q(mult_result[16]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(
n1855), .CK(clk), .RN(n6984), .Q(mult_result[17]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(
n1854), .CK(clk), .RN(n6984), .Q(mult_result[18]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(
n1853), .CK(clk), .RN(n6984), .Q(mult_result[19]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(
n1852), .CK(clk), .RN(n6984), .Q(mult_result[20]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(
n1851), .CK(clk), .RN(n6984), .Q(mult_result[21]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(
n1850), .CK(clk), .RN(n6984), .Q(mult_result[22]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(
n1849), .CK(clk), .RN(n6984), .Q(mult_result[31]) );
DFFRXLTS FPSENCOS_cont_iter_count_reg_2_ ( .D(n1832), .CK(clk), .RN(n6963),
.Q(FPSENCOS_cont_iter_out[2]), .QN(n2800) );
DFFRXLTS FPSENCOS_cont_iter_count_reg_1_ ( .D(n1833), .CK(clk), .RN(n6963),
.Q(FPSENCOS_cont_iter_out[1]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_27_ ( .D(n1829), .CK(clk), .RN(n6964), .Q(
FPSENCOS_d_ff3_LUT_out[27]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_26_ ( .D(n1828), .CK(clk), .RN(n6964), .Q(
FPSENCOS_d_ff3_LUT_out[26]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_25_ ( .D(n1827), .CK(clk), .RN(n6964), .Q(
FPSENCOS_d_ff3_LUT_out[25]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_24_ ( .D(n1826), .CK(clk), .RN(n6964), .QN(
n6832) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_23_ ( .D(n1825), .CK(clk), .RN(n6964), .Q(
FPSENCOS_d_ff3_LUT_out[23]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_22_ ( .D(n1824), .CK(clk), .RN(n6964), .Q(
FPSENCOS_d_ff3_LUT_out[22]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_21_ ( .D(n1823), .CK(clk), .RN(n6964), .Q(
FPSENCOS_d_ff3_LUT_out[21]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_20_ ( .D(n1822), .CK(clk), .RN(n6965), .Q(
FPSENCOS_d_ff3_LUT_out[20]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_19_ ( .D(n1821), .CK(clk), .RN(n6965), .Q(
FPSENCOS_d_ff3_LUT_out[19]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_18_ ( .D(n1820), .CK(clk), .RN(n6965), .Q(
FPSENCOS_d_ff3_LUT_out[18]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_17_ ( .D(n1819), .CK(clk), .RN(n6965), .Q(
FPSENCOS_d_ff3_LUT_out[17]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_16_ ( .D(n1818), .CK(clk), .RN(n6965), .Q(
FPSENCOS_d_ff3_LUT_out[16]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_15_ ( .D(n1817), .CK(clk), .RN(n6965), .Q(
FPSENCOS_d_ff3_LUT_out[15]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_14_ ( .D(n1816), .CK(clk), .RN(n6965), .Q(
FPSENCOS_d_ff3_LUT_out[14]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_13_ ( .D(n1815), .CK(clk), .RN(n6965), .Q(
FPSENCOS_d_ff3_LUT_out[13]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_12_ ( .D(n1814), .CK(clk), .RN(n6965), .Q(
FPSENCOS_d_ff3_LUT_out[12]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_11_ ( .D(n1813), .CK(clk), .RN(n6965), .Q(
FPSENCOS_d_ff3_LUT_out[11]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_10_ ( .D(n1812), .CK(clk), .RN(n6966), .Q(
FPSENCOS_d_ff3_LUT_out[10]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_8_ ( .D(n1810), .CK(clk), .RN(n6966), .Q(
FPSENCOS_d_ff3_LUT_out[8]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_7_ ( .D(n1809), .CK(clk), .RN(n6966), .Q(
FPSENCOS_d_ff3_LUT_out[7]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_6_ ( .D(n1808), .CK(clk), .RN(n6966), .QN(
n2795) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_5_ ( .D(n1807), .CK(clk), .RN(n6966), .Q(
FPSENCOS_d_ff3_LUT_out[5]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_4_ ( .D(n1806), .CK(clk), .RN(n6966), .Q(
FPSENCOS_d_ff3_LUT_out[4]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_3_ ( .D(n1805), .CK(clk), .RN(n6966), .Q(
FPSENCOS_d_ff3_LUT_out[3]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_1_ ( .D(n1803), .CK(clk), .RN(n6966), .Q(
FPSENCOS_d_ff3_LUT_out[1]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_0_ ( .D(n1802), .CK(clk), .RN(n6967), .Q(
FPSENCOS_d_ff3_LUT_out[0]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_30_ ( .D(n1414), .CK(clk), .RN(n6967),
.Q(FPSENCOS_d_ff3_sh_y_out[30]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_29_ ( .D(n1415), .CK(clk), .RN(n6967),
.Q(FPSENCOS_d_ff3_sh_y_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_28_ ( .D(n1416), .CK(clk), .RN(n6967),
.Q(FPSENCOS_d_ff3_sh_y_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_27_ ( .D(n1417), .CK(clk), .RN(n6967),
.Q(FPSENCOS_d_ff3_sh_y_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_26_ ( .D(n1418), .CK(clk), .RN(n6967),
.Q(FPSENCOS_d_ff3_sh_y_out[26]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_25_ ( .D(n1419), .CK(clk), .RN(n6967),
.Q(FPSENCOS_d_ff3_sh_y_out[25]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_24_ ( .D(n1420), .CK(clk), .RN(n6967),
.Q(FPSENCOS_d_ff3_sh_y_out[24]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_30_ ( .D(n1785), .CK(clk), .RN(n6967),
.Q(FPSENCOS_d_ff3_sh_x_out[30]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_29_ ( .D(n1786), .CK(clk), .RN(n6968),
.Q(FPSENCOS_d_ff3_sh_x_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_28_ ( .D(n1787), .CK(clk), .RN(n6968),
.Q(FPSENCOS_d_ff3_sh_x_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_27_ ( .D(n1788), .CK(clk), .RN(n6968),
.Q(FPSENCOS_d_ff3_sh_x_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_26_ ( .D(n1789), .CK(clk), .RN(n6968),
.Q(FPSENCOS_d_ff3_sh_x_out[26]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_25_ ( .D(n1790), .CK(clk), .RN(n6968),
.Q(FPSENCOS_d_ff3_sh_x_out[25]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_24_ ( .D(n1791), .CK(clk), .RN(n6968),
.Q(FPSENCOS_d_ff3_sh_x_out[24]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_30_ ( .D(n1738), .CK(clk), .RN(n6968), .Q(
FPSENCOS_d_ff1_Z[30]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_29_ ( .D(n1737), .CK(clk), .RN(n6968), .Q(
FPSENCOS_d_ff1_Z[29]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_28_ ( .D(n1736), .CK(clk), .RN(n6968), .Q(
FPSENCOS_d_ff1_Z[28]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_27_ ( .D(n1735), .CK(clk), .RN(n6969), .Q(
FPSENCOS_d_ff1_Z[27]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_26_ ( .D(n1734), .CK(clk), .RN(n6969), .Q(
FPSENCOS_d_ff1_Z[26]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_25_ ( .D(n1733), .CK(clk), .RN(n6969), .Q(
FPSENCOS_d_ff1_Z[25]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_24_ ( .D(n1732), .CK(clk), .RN(n6969), .Q(
FPSENCOS_d_ff1_Z[24]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_23_ ( .D(n1731), .CK(clk), .RN(n6969), .Q(
FPSENCOS_d_ff1_Z[23]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_22_ ( .D(n1730), .CK(clk), .RN(n6969), .Q(
FPSENCOS_d_ff1_Z[22]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_21_ ( .D(n1729), .CK(clk), .RN(n6969), .Q(
FPSENCOS_d_ff1_Z[21]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_20_ ( .D(n1728), .CK(clk), .RN(n6969), .Q(
FPSENCOS_d_ff1_Z[20]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_19_ ( .D(n1727), .CK(clk), .RN(n6969), .Q(
FPSENCOS_d_ff1_Z[19]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_18_ ( .D(n1726), .CK(clk), .RN(n6969), .Q(
FPSENCOS_d_ff1_Z[18]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_17_ ( .D(n1725), .CK(clk), .RN(n6970), .Q(
FPSENCOS_d_ff1_Z[17]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_16_ ( .D(n1724), .CK(clk), .RN(n6970), .Q(
FPSENCOS_d_ff1_Z[16]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_15_ ( .D(n1723), .CK(clk), .RN(n6970), .Q(
FPSENCOS_d_ff1_Z[15]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_14_ ( .D(n1722), .CK(clk), .RN(n6970), .Q(
FPSENCOS_d_ff1_Z[14]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_13_ ( .D(n1721), .CK(clk), .RN(n6970), .Q(
FPSENCOS_d_ff1_Z[13]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_12_ ( .D(n1720), .CK(clk), .RN(n6970), .Q(
FPSENCOS_d_ff1_Z[12]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_11_ ( .D(n1719), .CK(clk), .RN(n6970), .Q(
FPSENCOS_d_ff1_Z[11]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_10_ ( .D(n1718), .CK(clk), .RN(n6970), .Q(
FPSENCOS_d_ff1_Z[10]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_9_ ( .D(n1717), .CK(clk), .RN(n6970), .Q(
FPSENCOS_d_ff1_Z[9]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_8_ ( .D(n1716), .CK(clk), .RN(n6970), .Q(
FPSENCOS_d_ff1_Z[8]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_7_ ( .D(n1715), .CK(clk), .RN(n6971), .Q(
FPSENCOS_d_ff1_Z[7]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_6_ ( .D(n1714), .CK(clk), .RN(n6971), .Q(
FPSENCOS_d_ff1_Z[6]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_5_ ( .D(n1713), .CK(clk), .RN(n6971), .Q(
FPSENCOS_d_ff1_Z[5]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_4_ ( .D(n1712), .CK(clk), .RN(n6971), .Q(
FPSENCOS_d_ff1_Z[4]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_3_ ( .D(n1711), .CK(clk), .RN(n6971), .Q(
FPSENCOS_d_ff1_Z[3]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_2_ ( .D(n1710), .CK(clk), .RN(n6971), .Q(
FPSENCOS_d_ff1_Z[2]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_1_ ( .D(n1709), .CK(clk), .RN(n6971), .Q(
FPSENCOS_d_ff1_Z[1]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_0_ ( .D(n1708), .CK(clk), .RN(n6971), .Q(
FPSENCOS_d_ff1_Z[0]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_31_ ( .D(n1707), .CK(clk), .RN(n6971), .Q(
FPSENCOS_d_ff1_Z[31]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_0_ ( .D(n1740), .CK(clk), .RN(
n6972), .Q(FPSENCOS_d_ff2_X[0]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_0_ ( .D(n1739), .CK(clk), .RN(n6972),
.Q(FPSENCOS_d_ff3_sh_x_out[0]) );
DFFRX2TS FPADDSUB_FS_Module_state_reg_reg_3_ ( .D(n1841), .CK(clk), .RN(
n6936), .Q(FPADDSUB_FS_Module_state_reg[3]), .QN(n6737) );
DFFRXLTS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_6_ ( .D(n1669),
.CK(clk), .RN(n2218), .Q(FPADDSUB_Add_Subt_result[6]), .QN(n2349) );
DFFRXLTS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_1_ ( .D(n1664),
.CK(clk), .RN(n6933), .Q(FPADDSUB_Add_Subt_result[1]), .QN(n2347) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_31_ ( .D(n1801), .CK(clk), .RN(n6972),
.Q(FPSENCOS_d_ff3_sh_x_out[31]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_31_ ( .D(n1701), .CK(clk), .RN(n6973), .Q(
FPSENCOS_d_ff_Yn[31]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_31_ ( .D(n1412), .CK(clk), .RN(n6973),
.Q(FPSENCOS_d_ff3_sh_y_out[31]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_31_ ( .D(n1346), .CK(clk), .RN(n6973),
.Q(cordic_result[31]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_31_ ( .D(n1700), .CK(clk), .RN(n5026), .Q(
FPSENCOS_d_ff_Zn[31]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_30_ ( .D(n1630), .CK(clk), .RN(n5024), .Q(
FPSENCOS_d_ff_Zn[30]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_30_ ( .D(n1479), .CK(clk), .RN(
n5025), .Q(FPSENCOS_d_ff2_Z[30]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_30_ ( .D(n1800), .CK(clk), .RN(
n5027), .Q(FPSENCOS_d_ff2_X[30]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_30_ ( .D(n1350), .CK(clk), .RN(n6982), .Q(
FPSENCOS_sign_inv_out[30]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_30_ ( .D(n1349), .CK(clk), .RN(n6981),
.Q(cordic_result[30]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_29_ ( .D(n1626), .CK(clk), .RN(n5027), .Q(
FPSENCOS_d_ff_Zn[29]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_29_ ( .D(n1480), .CK(clk), .RN(
n6982), .Q(FPSENCOS_d_ff2_Z[29]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_29_ ( .D(n1625), .CK(clk), .RN(n6981), .Q(
FPSENCOS_d_ff_Yn[29]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_29_ ( .D(n1352), .CK(clk), .RN(n5027), .Q(
FPSENCOS_sign_inv_out[29]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_29_ ( .D(n1351), .CK(clk), .RN(n6982),
.Q(cordic_result[29]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_28_ ( .D(n1622), .CK(clk), .RN(n6981), .Q(
FPSENCOS_d_ff_Zn[28]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_28_ ( .D(n1481), .CK(clk), .RN(
n5027), .Q(FPSENCOS_d_ff2_Z[28]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_28_ ( .D(n1621), .CK(clk), .RN(n6982), .Q(
FPSENCOS_d_ff_Yn[28]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_28_ ( .D(n1354), .CK(clk), .RN(n6981), .Q(
FPSENCOS_sign_inv_out[28]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_28_ ( .D(n1353), .CK(clk), .RN(n6980),
.Q(cordic_result[28]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_27_ ( .D(n1618), .CK(clk), .RN(n6980), .Q(
FPSENCOS_d_ff_Zn[27]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_27_ ( .D(n1482), .CK(clk), .RN(
n6980), .Q(FPSENCOS_d_ff2_Z[27]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_27_ ( .D(n1356), .CK(clk), .RN(n6980), .Q(
FPSENCOS_sign_inv_out[27]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_27_ ( .D(n1355), .CK(clk), .RN(n6980),
.Q(cordic_result[27]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_26_ ( .D(n1614), .CK(clk), .RN(n6980), .Q(
FPSENCOS_d_ff_Zn[26]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_26_ ( .D(n1483), .CK(clk), .RN(
n6979), .Q(FPSENCOS_d_ff2_Z[26]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_26_ ( .D(n1613), .CK(clk), .RN(n6979), .Q(
FPSENCOS_d_ff_Yn[26]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_26_ ( .D(n1358), .CK(clk), .RN(n6979), .Q(
FPSENCOS_sign_inv_out[26]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_26_ ( .D(n1357), .CK(clk), .RN(n6979),
.Q(cordic_result[26]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_25_ ( .D(n1610), .CK(clk), .RN(n6979), .Q(
FPSENCOS_d_ff_Zn[25]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_25_ ( .D(n1484), .CK(clk), .RN(
n6979), .Q(FPSENCOS_d_ff2_Z[25]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_25_ ( .D(n1609), .CK(clk), .RN(n6979), .Q(
FPSENCOS_d_ff_Yn[25]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_25_ ( .D(n1360), .CK(clk), .RN(n6978), .Q(
FPSENCOS_sign_inv_out[25]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_25_ ( .D(n1359), .CK(clk), .RN(n6978),
.Q(cordic_result[25]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_24_ ( .D(n1606), .CK(clk), .RN(n6978), .Q(
FPSENCOS_d_ff_Zn[24]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_24_ ( .D(n1485), .CK(clk), .RN(
n6978), .Q(FPSENCOS_d_ff2_Z[24]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_24_ ( .D(n1605), .CK(clk), .RN(n6978), .Q(
FPSENCOS_d_ff_Yn[24]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_24_ ( .D(n1362), .CK(clk), .RN(n6977), .Q(
FPSENCOS_sign_inv_out[24]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_24_ ( .D(n1361), .CK(clk), .RN(n6977),
.Q(cordic_result[24]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_23_ ( .D(n1602), .CK(clk), .RN(n6977), .Q(
FPSENCOS_d_ff_Zn[23]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_23_ ( .D(n1486), .CK(clk), .RN(
n6977), .Q(FPSENCOS_d_ff2_Z[23]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_23_ ( .D(n1601), .CK(clk), .RN(n6977), .Q(
FPSENCOS_d_ff_Yn[23]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_23_ ( .D(n1364), .CK(clk), .RN(n6976), .Q(
FPSENCOS_sign_inv_out[23]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_23_ ( .D(n1363), .CK(clk), .RN(n6976),
.Q(cordic_result[23]) );
DFFRXLTS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(
n1511), .CK(clk), .RN(n6927), .Q(result_add_subt[0]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_0_ ( .D(n1510), .CK(clk), .RN(n6976), .Q(
FPSENCOS_d_ff_Zn[0]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_0_ ( .D(n1509), .CK(clk), .RN(
n6976), .Q(FPSENCOS_d_ff2_Z[0]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_0_ ( .D(n1476), .CK(clk), .RN(n6976), .Q(
FPSENCOS_d_ff_Yn[0]) );
DFFRXLTS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_1_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[1]), .CK(clk),
.RN(n6917), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[27]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_22_ ( .D(n1598), .CK(clk), .RN(n6976), .Q(
FPSENCOS_d_ff_Zn[22]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_22_ ( .D(n1487), .CK(clk), .RN(
n6976), .Q(FPSENCOS_d_ff2_Z[22]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_22_ ( .D(n1597), .CK(clk), .RN(n6976), .Q(
FPSENCOS_d_ff_Yn[22]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_22_ ( .D(n1430), .CK(clk), .RN(n6975),
.QN(n6833) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_22_ ( .D(n1784), .CK(clk), .RN(
n6975), .Q(FPSENCOS_d_ff2_X[22]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_22_ ( .D(n1783), .CK(clk), .RN(n6975),
.Q(FPSENCOS_d_ff3_sh_x_out[22]) );
DFFRXLTS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(
n1535), .CK(clk), .RN(n2225), .Q(result_add_subt[6]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_6_ ( .D(n1534), .CK(clk), .RN(n6975), .Q(
FPSENCOS_d_ff_Zn[6]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_6_ ( .D(n1503), .CK(clk), .RN(
n6975), .Q(FPSENCOS_d_ff2_Z[6]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_6_ ( .D(n1533), .CK(clk), .RN(n6975), .Q(
FPSENCOS_d_ff_Yn[6]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_6_ ( .D(n1462), .CK(clk), .RN(n6975),
.Q(FPSENCOS_d_ff3_sh_y_out[6]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_6_ ( .D(n1752), .CK(clk), .RN(
n6974), .Q(FPSENCOS_d_ff2_X[6]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_6_ ( .D(n1751), .CK(clk), .RN(n6974),
.Q(FPSENCOS_d_ff3_sh_x_out[6]) );
DFFRXLTS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(
n1523), .CK(clk), .RN(n2225), .Q(result_add_subt[3]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_3_ ( .D(n1522), .CK(clk), .RN(n6974), .Q(
FPSENCOS_d_ff_Zn[3]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_3_ ( .D(n1506), .CK(clk), .RN(
n6974), .Q(FPSENCOS_d_ff2_Z[3]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_3_ ( .D(n1521), .CK(clk), .RN(n6974), .Q(
FPSENCOS_d_ff_Yn[3]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_3_ ( .D(n1468), .CK(clk), .RN(n6974),
.QN(n6834) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_3_ ( .D(n1746), .CK(clk), .RN(
n6974), .Q(FPSENCOS_d_ff2_X[3]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_3_ ( .D(n1745), .CK(clk), .RN(n6974),
.Q(FPSENCOS_d_ff3_sh_x_out[3]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_19_ ( .D(n1586), .CK(clk), .RN(n6973), .Q(
FPSENCOS_d_ff_Zn[19]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_19_ ( .D(n1490), .CK(clk), .RN(
n6973), .Q(FPSENCOS_d_ff2_Z[19]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_19_ ( .D(n1585), .CK(clk), .RN(n6973), .Q(
FPSENCOS_d_ff_Yn[19]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_19_ ( .D(n1436), .CK(clk), .RN(n6978),
.QN(n6835) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_19_ ( .D(n1778), .CK(clk), .RN(
n6944), .Q(FPSENCOS_d_ff2_X[19]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_19_ ( .D(n1777), .CK(clk), .RN(n6944),
.Q(FPSENCOS_d_ff3_sh_x_out[19]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_19_ ( .D(n1372), .CK(clk), .RN(n6944), .Q(
FPSENCOS_sign_inv_out[19]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_19_ ( .D(n1371), .CK(clk), .RN(n6944),
.Q(cordic_result[19]) );
DFFRXLTS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(
n1519), .CK(clk), .RN(n6931), .Q(result_add_subt[2]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_2_ ( .D(n1518), .CK(clk), .RN(n6944), .Q(
FPSENCOS_d_ff_Zn[2]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_2_ ( .D(n1507), .CK(clk), .RN(
n6944), .Q(FPSENCOS_d_ff2_Z[2]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_2_ ( .D(n1517), .CK(clk), .RN(n6944), .Q(
FPSENCOS_d_ff_Yn[2]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_2_ ( .D(n1470), .CK(clk), .RN(n6944),
.QN(n6836) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_2_ ( .D(n1744), .CK(clk), .RN(
n6945), .Q(FPSENCOS_d_ff2_X[2]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_2_ ( .D(n1743), .CK(clk), .RN(n6945),
.Q(FPSENCOS_d_ff3_sh_x_out[2]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_21_ ( .D(n1594), .CK(clk), .RN(n6945), .Q(
FPSENCOS_d_ff_Zn[21]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_21_ ( .D(n1488), .CK(clk), .RN(
n6945), .Q(FPSENCOS_d_ff2_Z[21]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_21_ ( .D(n1593), .CK(clk), .RN(n6945), .Q(
FPSENCOS_d_ff_Yn[21]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_21_ ( .D(n1432), .CK(clk), .RN(n6945),
.Q(FPSENCOS_d_ff3_sh_y_out[21]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_21_ ( .D(n1782), .CK(clk), .RN(
n6945), .Q(FPSENCOS_d_ff2_X[21]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_21_ ( .D(n1781), .CK(clk), .RN(n6946),
.Q(FPSENCOS_d_ff3_sh_x_out[21]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_18_ ( .D(n1582), .CK(clk), .RN(n6946), .Q(
FPSENCOS_d_ff_Zn[18]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_18_ ( .D(n1491), .CK(clk), .RN(
n6946), .Q(FPSENCOS_d_ff2_Z[18]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_18_ ( .D(n1581), .CK(clk), .RN(n6946), .Q(
FPSENCOS_d_ff_Yn[18]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_18_ ( .D(n1438), .CK(clk), .RN(n6946),
.QN(n6837) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_18_ ( .D(n1776), .CK(clk), .RN(
n6946), .Q(FPSENCOS_d_ff2_X[18]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_18_ ( .D(n1775), .CK(clk), .RN(n6946),
.Q(FPSENCOS_d_ff3_sh_x_out[18]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_18_ ( .D(n1374), .CK(clk), .RN(n6946), .Q(
FPSENCOS_sign_inv_out[18]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_18_ ( .D(n1373), .CK(clk), .RN(n6947),
.Q(cordic_result[18]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_15_ ( .D(n1570), .CK(clk), .RN(n6947), .Q(
FPSENCOS_d_ff_Zn[15]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_15_ ( .D(n1494), .CK(clk), .RN(
n6947), .Q(FPSENCOS_d_ff2_Z[15]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_15_ ( .D(n1569), .CK(clk), .RN(n6947), .Q(
FPSENCOS_d_ff_Yn[15]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_15_ ( .D(n1444), .CK(clk), .RN(n6947),
.QN(n6838) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_15_ ( .D(n1770), .CK(clk), .RN(
n6947), .Q(FPSENCOS_d_ff2_X[15]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_15_ ( .D(n1769), .CK(clk), .RN(n6947),
.Q(FPSENCOS_d_ff3_sh_x_out[15]) );
DFFRXLTS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(
n1543), .CK(clk), .RN(n6931), .Q(result_add_subt[8]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_8_ ( .D(n1542), .CK(clk), .RN(n6947), .Q(
FPSENCOS_d_ff_Zn[8]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_8_ ( .D(n1501), .CK(clk), .RN(
n6948), .Q(FPSENCOS_d_ff2_Z[8]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_8_ ( .D(n1541), .CK(clk), .RN(n6948), .Q(
FPSENCOS_d_ff_Yn[8]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_8_ ( .D(n1458), .CK(clk), .RN(n6948),
.QN(n6839) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_8_ ( .D(n1756), .CK(clk), .RN(
n6948), .Q(FPSENCOS_d_ff2_X[8]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_8_ ( .D(n1755), .CK(clk), .RN(n6948),
.Q(FPSENCOS_d_ff3_sh_x_out[8]) );
DFFRXLTS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(
n1515), .CK(clk), .RN(n6924), .Q(result_add_subt[1]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_1_ ( .D(n1514), .CK(clk), .RN(n6948), .Q(
FPSENCOS_d_ff_Zn[1]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_1_ ( .D(n1508), .CK(clk), .RN(
n6948), .Q(FPSENCOS_d_ff2_Z[1]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_1_ ( .D(n1513), .CK(clk), .RN(n6948), .Q(
FPSENCOS_d_ff_Yn[1]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_1_ ( .D(n1472), .CK(clk), .RN(n6949),
.Q(FPSENCOS_d_ff3_sh_y_out[1]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_1_ ( .D(n1742), .CK(clk), .RN(
n6949), .Q(FPSENCOS_d_ff2_X[1]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_1_ ( .D(n1741), .CK(clk), .RN(n6949),
.Q(FPSENCOS_d_ff3_sh_x_out[1]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_20_ ( .D(n1590), .CK(clk), .RN(n6949), .Q(
FPSENCOS_d_ff_Zn[20]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_20_ ( .D(n1489), .CK(clk), .RN(
n6949), .Q(FPSENCOS_d_ff2_Z[20]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_20_ ( .D(n1589), .CK(clk), .RN(n6949), .Q(
FPSENCOS_d_ff_Yn[20]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_20_ ( .D(n1434), .CK(clk), .RN(n6949),
.QN(n6840) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_20_ ( .D(n1780), .CK(clk), .RN(
n6950), .Q(FPSENCOS_d_ff2_X[20]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_20_ ( .D(n1779), .CK(clk), .RN(n6950),
.Q(FPSENCOS_d_ff3_sh_x_out[20]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_20_ ( .D(n1370), .CK(clk), .RN(n6950), .Q(
FPSENCOS_sign_inv_out[20]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_20_ ( .D(n1369), .CK(clk), .RN(n6950),
.Q(cordic_result[20]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_13_ ( .D(n1562), .CK(clk), .RN(n6950), .Q(
FPSENCOS_d_ff_Zn[13]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_13_ ( .D(n1496), .CK(clk), .RN(
n6950), .Q(FPSENCOS_d_ff2_Z[13]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_13_ ( .D(n1561), .CK(clk), .RN(n6950), .Q(
FPSENCOS_d_ff_Yn[13]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_13_ ( .D(n1448), .CK(clk), .RN(n6950),
.QN(n6841) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_13_ ( .D(n1766), .CK(clk), .RN(
n6951), .Q(FPSENCOS_d_ff2_X[13]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_13_ ( .D(n1765), .CK(clk), .RN(n6951),
.Q(FPSENCOS_d_ff3_sh_x_out[13]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_13_ ( .D(n1384), .CK(clk), .RN(n6951), .Q(
FPSENCOS_sign_inv_out[13]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_13_ ( .D(n1383), .CK(clk), .RN(n6951),
.Q(cordic_result[13]) );
DFFRXLTS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(
n1531), .CK(clk), .RN(n6931), .Q(result_add_subt[5]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_5_ ( .D(n1530), .CK(clk), .RN(n6951), .Q(
FPSENCOS_d_ff_Zn[5]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_5_ ( .D(n1504), .CK(clk), .RN(
n6951), .Q(FPSENCOS_d_ff2_Z[5]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_5_ ( .D(n1529), .CK(clk), .RN(n6951), .Q(
FPSENCOS_d_ff_Yn[5]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_5_ ( .D(n1464), .CK(clk), .RN(n6951),
.QN(n6842) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_5_ ( .D(n1750), .CK(clk), .RN(
n6952), .Q(FPSENCOS_d_ff2_X[5]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_5_ ( .D(n1749), .CK(clk), .RN(n6952),
.Q(FPSENCOS_d_ff3_sh_x_out[5]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_17_ ( .D(n1578), .CK(clk), .RN(n6952), .Q(
FPSENCOS_d_ff_Zn[17]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_17_ ( .D(n1492), .CK(clk), .RN(
n6952), .Q(FPSENCOS_d_ff2_Z[17]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_17_ ( .D(n1577), .CK(clk), .RN(n6952), .Q(
FPSENCOS_d_ff_Yn[17]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_17_ ( .D(n1440), .CK(clk), .RN(n6952),
.QN(n6843) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_17_ ( .D(n1774), .CK(clk), .RN(
n6952), .Q(FPSENCOS_d_ff2_X[17]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_17_ ( .D(n1773), .CK(clk), .RN(n6953),
.Q(FPSENCOS_d_ff3_sh_x_out[17]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_17_ ( .D(n1376), .CK(clk), .RN(n6953), .Q(
FPSENCOS_sign_inv_out[17]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_17_ ( .D(n1375), .CK(clk), .RN(n6953),
.Q(cordic_result[17]) );
DFFRXLTS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(
n1527), .CK(clk), .RN(n6928), .Q(result_add_subt[4]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_4_ ( .D(n1526), .CK(clk), .RN(n6953), .Q(
FPSENCOS_d_ff_Zn[4]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_4_ ( .D(n1505), .CK(clk), .RN(
n6953), .Q(FPSENCOS_d_ff2_Z[4]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_4_ ( .D(n1525), .CK(clk), .RN(n6953), .Q(
FPSENCOS_d_ff_Yn[4]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_4_ ( .D(n1466), .CK(clk), .RN(n6953),
.QN(n6844) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_4_ ( .D(n1748), .CK(clk), .RN(
n6954), .Q(FPSENCOS_d_ff2_X[4]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_4_ ( .D(n1747), .CK(clk), .RN(n6954),
.Q(FPSENCOS_d_ff3_sh_x_out[4]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_16_ ( .D(n1574), .CK(clk), .RN(n6954), .Q(
FPSENCOS_d_ff_Zn[16]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_16_ ( .D(n1493), .CK(clk), .RN(
n6954), .Q(FPSENCOS_d_ff2_Z[16]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_16_ ( .D(n1573), .CK(clk), .RN(n6954), .Q(
FPSENCOS_d_ff_Yn[16]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_16_ ( .D(n1442), .CK(clk), .RN(n6954),
.QN(n6845) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_16_ ( .D(n1772), .CK(clk), .RN(
n6954), .Q(FPSENCOS_d_ff2_X[16]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_16_ ( .D(n1771), .CK(clk), .RN(n6954),
.Q(FPSENCOS_d_ff3_sh_x_out[16]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_16_ ( .D(n1378), .CK(clk), .RN(n6955), .Q(
FPSENCOS_sign_inv_out[16]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_16_ ( .D(n1377), .CK(clk), .RN(n6955),
.Q(cordic_result[16]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_10_ ( .D(n1550), .CK(clk), .RN(n6955), .Q(
FPSENCOS_d_ff_Zn[10]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_10_ ( .D(n1499), .CK(clk), .RN(
n6955), .Q(FPSENCOS_d_ff2_Z[10]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_10_ ( .D(n1549), .CK(clk), .RN(n6955), .Q(
FPSENCOS_d_ff_Yn[10]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_10_ ( .D(n1454), .CK(clk), .RN(n6955),
.QN(n6846) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_10_ ( .D(n1760), .CK(clk), .RN(
n6955), .Q(FPSENCOS_d_ff2_X[10]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_10_ ( .D(n1759), .CK(clk), .RN(n6955),
.Q(FPSENCOS_d_ff3_sh_x_out[10]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_14_ ( .D(n1566), .CK(clk), .RN(n6956), .Q(
FPSENCOS_d_ff_Zn[14]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_14_ ( .D(n1495), .CK(clk), .RN(
n6956), .Q(FPSENCOS_d_ff2_Z[14]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_14_ ( .D(n1565), .CK(clk), .RN(n6956), .Q(
FPSENCOS_d_ff_Yn[14]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_14_ ( .D(n1446), .CK(clk), .RN(n6956),
.QN(n6847) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_14_ ( .D(n1768), .CK(clk), .RN(
n6956), .Q(FPSENCOS_d_ff2_X[14]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_14_ ( .D(n1767), .CK(clk), .RN(n6956),
.Q(FPSENCOS_d_ff3_sh_x_out[14]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_14_ ( .D(n1382), .CK(clk), .RN(n6956), .Q(
FPSENCOS_sign_inv_out[14]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_14_ ( .D(n1381), .CK(clk), .RN(n6956),
.Q(cordic_result[14]) );
DFFRXLTS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(
n1539), .CK(clk), .RN(n5030), .Q(result_add_subt[7]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_7_ ( .D(n1538), .CK(clk), .RN(n6957), .Q(
FPSENCOS_d_ff_Zn[7]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_7_ ( .D(n1502), .CK(clk), .RN(
n6957), .Q(FPSENCOS_d_ff2_Z[7]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_7_ ( .D(n1537), .CK(clk), .RN(n6957), .Q(
FPSENCOS_d_ff_Yn[7]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_7_ ( .D(n1460), .CK(clk), .RN(n6957),
.QN(n6848) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_7_ ( .D(n1754), .CK(clk), .RN(
n6957), .Q(FPSENCOS_d_ff2_X[7]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_7_ ( .D(n1753), .CK(clk), .RN(n6957),
.Q(FPSENCOS_d_ff3_sh_x_out[7]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_11_ ( .D(n1554), .CK(clk), .RN(n6957), .Q(
FPSENCOS_d_ff_Zn[11]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_11_ ( .D(n1498), .CK(clk), .RN(
n6957), .Q(FPSENCOS_d_ff2_Z[11]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_11_ ( .D(n1553), .CK(clk), .RN(n6958), .Q(
FPSENCOS_d_ff_Yn[11]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_11_ ( .D(n1452), .CK(clk), .RN(n6958),
.QN(n6849) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_11_ ( .D(n1762), .CK(clk), .RN(
n6958), .Q(FPSENCOS_d_ff2_X[11]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_11_ ( .D(n1761), .CK(clk), .RN(n6958),
.Q(FPSENCOS_d_ff3_sh_x_out[11]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_12_ ( .D(n1558), .CK(clk), .RN(n6958), .Q(
FPSENCOS_d_ff_Zn[12]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_12_ ( .D(n1497), .CK(clk), .RN(
n6958), .Q(FPSENCOS_d_ff2_Z[12]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_12_ ( .D(n1557), .CK(clk), .RN(n6958), .Q(
FPSENCOS_d_ff_Yn[12]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_12_ ( .D(n1450), .CK(clk), .RN(n6959),
.QN(n6850) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_12_ ( .D(n1764), .CK(clk), .RN(
n6959), .Q(FPSENCOS_d_ff2_X[12]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_12_ ( .D(n1763), .CK(clk), .RN(n6959),
.Q(FPSENCOS_d_ff3_sh_x_out[12]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_12_ ( .D(n1386), .CK(clk), .RN(n6959), .Q(
FPSENCOS_sign_inv_out[12]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_12_ ( .D(n1385), .CK(clk), .RN(n6959),
.Q(cordic_result[12]) );
DFFRXLTS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(
n1547), .CK(clk), .RN(n2225), .Q(result_add_subt[9]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_9_ ( .D(n1546), .CK(clk), .RN(n6959), .Q(
FPSENCOS_d_ff_Zn[9]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_9_ ( .D(n1500), .CK(clk), .RN(
n6959), .Q(FPSENCOS_d_ff2_Z[9]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_9_ ( .D(n1545), .CK(clk), .RN(n6959), .Q(
FPSENCOS_d_ff_Yn[9]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_9_ ( .D(n1456), .CK(clk), .RN(n6960),
.QN(n6851) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_9_ ( .D(n1758), .CK(clk), .RN(
n6960), .Q(FPSENCOS_d_ff2_X[9]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_9_ ( .D(n1757), .CK(clk), .RN(n6960),
.Q(FPSENCOS_d_ff3_sh_x_out[9]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_9_ ( .D(n1392), .CK(clk), .RN(n6960), .Q(
FPSENCOS_sign_inv_out[9]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_9_ ( .D(n1391), .CK(clk), .RN(n6960),
.Q(cordic_result[9]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_11_ ( .D(n1388), .CK(clk), .RN(n6960), .Q(
FPSENCOS_sign_inv_out[11]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_11_ ( .D(n1387), .CK(clk), .RN(n6960),
.Q(cordic_result[11]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_7_ ( .D(n1396), .CK(clk), .RN(n6960), .Q(
FPSENCOS_sign_inv_out[7]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_7_ ( .D(n1395), .CK(clk), .RN(n6960),
.Q(cordic_result[7]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_10_ ( .D(n1390), .CK(clk), .RN(n6961), .Q(
FPSENCOS_sign_inv_out[10]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_10_ ( .D(n1389), .CK(clk), .RN(n6961),
.Q(cordic_result[10]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_4_ ( .D(n1402), .CK(clk), .RN(n6961), .Q(
FPSENCOS_sign_inv_out[4]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_4_ ( .D(n1401), .CK(clk), .RN(n6961),
.Q(cordic_result[4]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_5_ ( .D(n1400), .CK(clk), .RN(n6961), .Q(
FPSENCOS_sign_inv_out[5]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_5_ ( .D(n1399), .CK(clk), .RN(n6961),
.Q(cordic_result[5]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_1_ ( .D(n1408), .CK(clk), .RN(n6961), .Q(
FPSENCOS_sign_inv_out[1]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_1_ ( .D(n1407), .CK(clk), .RN(n6961),
.Q(cordic_result[1]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_8_ ( .D(n1394), .CK(clk), .RN(n6961), .Q(
FPSENCOS_sign_inv_out[8]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_8_ ( .D(n1393), .CK(clk), .RN(n6961),
.Q(cordic_result[8]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_15_ ( .D(n1380), .CK(clk), .RN(n6962), .Q(
FPSENCOS_sign_inv_out[15]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_15_ ( .D(n1379), .CK(clk), .RN(n6962),
.Q(cordic_result[15]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_21_ ( .D(n1368), .CK(clk), .RN(n6962), .Q(
FPSENCOS_sign_inv_out[21]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_21_ ( .D(n1367), .CK(clk), .RN(n6962),
.Q(cordic_result[21]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_2_ ( .D(n1406), .CK(clk), .RN(n6962), .Q(
FPSENCOS_sign_inv_out[2]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_2_ ( .D(n1405), .CK(clk), .RN(n6962),
.Q(cordic_result[2]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_3_ ( .D(n1404), .CK(clk), .RN(n6962), .Q(
FPSENCOS_sign_inv_out[3]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_3_ ( .D(n1403), .CK(clk), .RN(n6962),
.Q(cordic_result[3]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_6_ ( .D(n1398), .CK(clk), .RN(n6962), .Q(
FPSENCOS_sign_inv_out[6]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_6_ ( .D(n1397), .CK(clk), .RN(n6962),
.Q(cordic_result[6]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_22_ ( .D(n1366), .CK(clk), .RN(n6963), .Q(
FPSENCOS_sign_inv_out[22]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_22_ ( .D(n1365), .CK(clk), .RN(n6963),
.Q(cordic_result[22]) );
DFFRXLTS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_0_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[0]), .CK(clk),
.RN(n2286), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[26]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_0_ ( .D(n1474), .CK(clk), .RN(n6963),
.Q(FPSENCOS_d_ff3_sh_y_out[0]) );
DFFRXLTS FPSENCOS_d_ff5_Q_reg_0_ ( .D(n1410), .CK(clk), .RN(n6963), .Q(
FPSENCOS_sign_inv_out[0]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_0_ ( .D(n1409), .CK(clk), .RN(n6963),
.Q(cordic_result[0]) );
DFFRXLTS FPADDSUB_XRegister_Q_reg_30_ ( .D(n1329), .CK(clk), .RN(n6930), .Q(
FPADDSUB_intDX[30]), .QN(n2351) );
DFFRXLTS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_30_ ( .D(n1328), .CK(
clk), .RN(n6934), .Q(FPADDSUB_DmP[30]) );
DFFRXLTS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_29_ ( .D(n1325), .CK(
clk), .RN(n6934), .Q(FPADDSUB_DmP[29]) );
DFFRXLTS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_28_ ( .D(n1322), .CK(
clk), .RN(n6934), .Q(FPADDSUB_DmP[28]) );
DFFRXLTS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_27_ ( .D(n1319), .CK(
clk), .RN(n6934), .Q(FPADDSUB_DmP[27]) );
DFFRXLTS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_26_ ( .D(n1316), .CK(
clk), .RN(n6933), .Q(FPADDSUB_DmP[26]) );
DFFRXLTS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_25_ ( .D(n1313), .CK(
clk), .RN(n6933), .Q(FPADDSUB_DmP[25]) );
DFFRXLTS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_24_ ( .D(n1310), .CK(
clk), .RN(n6933), .Q(FPADDSUB_DmP[24]) );
DFFRXLTS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_23_ ( .D(n1307), .CK(
clk), .RN(n6933), .Q(FPADDSUB_DmP[23]) );
DFFRXLTS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_6_ ( .D(n1298), .CK(
clk), .RN(n6913), .Q(FPADDSUB_DmP[6]) );
DFFRXLTS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_19_ ( .D(n1292), .CK(
clk), .RN(n6941), .Q(FPADDSUB_DmP[19]) );
DFFRXLTS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_2_ ( .D(n1288), .CK(
clk), .RN(n6922), .Q(FPADDSUB_DmP[2]) );
DFFRXLTS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_18_ ( .D(n1282), .CK(
clk), .RN(n6922), .Q(FPADDSUB_DmP[18]) );
DFFRXLTS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_15_ ( .D(n1278), .CK(
clk), .RN(n6922), .Q(FPADDSUB_DmP[15]) );
DFFRXLTS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_8_ ( .D(n1275), .CK(
clk), .RN(n6923), .Q(FPADDSUB_DmP[8]) );
DFFRXLTS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_4_ ( .D(n1254), .CK(
clk), .RN(n6943), .Q(FPADDSUB_DmP[4]) );
DFFRXLTS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_16_ ( .D(n1251), .CK(
clk), .RN(n6942), .Q(FPADDSUB_DmP[16]) );
DFFRXLTS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_10_ ( .D(n1247), .CK(
clk), .RN(n2225), .Q(FPADDSUB_DmP[10]) );
DFFRXLTS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_14_ ( .D(n1244), .CK(
clk), .RN(n6931), .Q(FPADDSUB_DmP[14]) );
DFFRXLTS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_7_ ( .D(n1240), .CK(
clk), .RN(n6924), .Q(FPADDSUB_DmP[7]) );
DFFRXLTS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_11_ ( .D(n1237), .CK(
clk), .RN(n6925), .Q(FPADDSUB_DmP[11]) );
DFFRXLTS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_12_ ( .D(n1234), .CK(
clk), .RN(n6925), .Q(FPADDSUB_DmP[12]) );
DFFSX1TS R_6 ( .D(FPMULT_Sgf_operation_Result[35]), .CK(clk), .SN(n2288),
.Q(n6902) );
DFFSX1TS R_9 ( .D(FPMULT_Sgf_operation_Result[36]), .CK(clk), .SN(n2287),
.Q(n6900) );
DFFSX1TS R_12 ( .D(FPMULT_Sgf_operation_Result[46]), .CK(clk), .SN(n6924),
.Q(n6898) );
DFFSX1TS R_16 ( .D(FPMULT_Sgf_operation_Result[47]), .CK(clk), .SN(n6929),
.Q(n6894) );
DFFSX1TS R_18 ( .D(FPMULT_Sgf_operation_Result[40]), .CK(clk), .SN(n2226),
.Q(n6892) );
DFFSX1TS R_21 ( .D(FPMULT_Sgf_operation_Result[45]), .CK(clk), .SN(n2226),
.Q(n6890) );
DFFSX1TS R_24 ( .D(FPMULT_Sgf_operation_Result[44]), .CK(clk), .SN(n6931),
.Q(n6888) );
DFFSX1TS R_27 ( .D(FPMULT_Sgf_operation_Result[42]), .CK(clk), .SN(n6924),
.Q(n6886) );
DFFSX1TS R_30 ( .D(FPMULT_Sgf_operation_Result[43]), .CK(clk), .SN(n2226),
.Q(n6884) );
DFFSX1TS R_33 ( .D(FPMULT_Sgf_operation_Result[41]), .CK(clk), .SN(n6928),
.Q(n6882) );
DFFSX1TS R_36 ( .D(FPMULT_Sgf_operation_Result[39]), .CK(clk), .SN(n2288),
.Q(n6880) );
DFFSX1TS R_39 ( .D(FPMULT_Sgf_operation_Result[34]), .CK(clk), .SN(n2288),
.Q(n6878) );
DFFSX1TS R_45 ( .D(FPMULT_Sgf_operation_Result[38]), .CK(clk), .SN(n2287),
.Q(n6874) );
DFFSX1TS R_48 ( .D(FPMULT_Sgf_operation_Result[37]), .CK(clk), .SN(n2287),
.Q(n6872) );
DFFSX2TS R_57 ( .D(n7002), .CK(clk), .SN(n2226), .Q(n6868) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_30_ ( .D(n1629), .CK(clk), .RN(n6981), .Q(
FPSENCOS_d_ff_Yn[30]), .QN(n6831) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_29_ ( .D(n1624), .CK(clk), .RN(n6983), .Q(
FPSENCOS_d_ff_Xn[29]), .QN(n6829) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_1_ ( .D(n1512), .CK(clk), .RN(n6949), .Q(
FPSENCOS_d_ff_Xn[1]), .QN(n6828) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_2_ ( .D(n1516), .CK(clk), .RN(n6945), .Q(
FPSENCOS_d_ff_Xn[2]), .QN(n6827) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_3_ ( .D(n1520), .CK(clk), .RN(n6974), .Q(
FPSENCOS_d_ff_Xn[3]), .QN(n6826) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_5_ ( .D(n1528), .CK(clk), .RN(n6952), .Q(
FPSENCOS_d_ff_Xn[5]), .QN(n6825) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_6_ ( .D(n1532), .CK(clk), .RN(n6975), .Q(
FPSENCOS_d_ff_Xn[6]), .QN(n6824) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_7_ ( .D(n1536), .CK(clk), .RN(n6957), .Q(
FPSENCOS_d_ff_Xn[7]), .QN(n6823) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_10_ ( .D(n1548), .CK(clk), .RN(n6955), .Q(
FPSENCOS_d_ff_Xn[10]), .QN(n6822) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_12_ ( .D(n1556), .CK(clk), .RN(n6959), .Q(
FPSENCOS_d_ff_Xn[12]), .QN(n6821) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_13_ ( .D(n1560), .CK(clk), .RN(n6951), .Q(
FPSENCOS_d_ff_Xn[13]), .QN(n6820) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_14_ ( .D(n1564), .CK(clk), .RN(n6956), .Q(
FPSENCOS_d_ff_Xn[14]), .QN(n6819) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_16_ ( .D(n1572), .CK(clk), .RN(n6954), .Q(
FPSENCOS_d_ff_Xn[16]), .QN(n6818) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_17_ ( .D(n1576), .CK(clk), .RN(n6952), .Q(
FPSENCOS_d_ff_Xn[17]), .QN(n6817) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_19_ ( .D(n1584), .CK(clk), .RN(n6953), .Q(
FPSENCOS_d_ff_Xn[19]), .QN(n6816) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_20_ ( .D(n1588), .CK(clk), .RN(n6950), .Q(
FPSENCOS_d_ff_Xn[20]), .QN(n6815) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_24_ ( .D(n1604), .CK(clk), .RN(n6977), .Q(
FPSENCOS_d_ff_Xn[24]), .QN(n6814) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_25_ ( .D(n1608), .CK(clk), .RN(n6978), .Q(
FPSENCOS_d_ff_Xn[25]), .QN(n6813) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_26_ ( .D(n1612), .CK(clk), .RN(n6979), .Q(
FPSENCOS_d_ff_Xn[26]), .QN(n6812) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_27_ ( .D(n1616), .CK(clk), .RN(n6980), .Q(
FPSENCOS_d_ff_Xn[27]), .QN(n6811) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_28_ ( .D(n1620), .CK(clk), .RN(n6983), .Q(
FPSENCOS_d_ff_Xn[28]), .QN(n6810) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_23_ ( .D(n1429), .CK(clk), .RN(
n6977), .Q(FPSENCOS_d_ff2_Y[23]), .QN(n6809) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_9_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[9]), .CK(clk),
.RN(n6920), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[35]), .QN(n6808) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_8_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[8]), .CK(clk),
.RN(n6920), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[34]), .QN(n6807) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n1889), .CK(
clk), .RN(n6990), .Q(FPMULT_Sgf_normalized_result[7]), .QN(n6806) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n1892), .CK(
clk), .RN(n5023), .Q(FPMULT_Sgf_normalized_result[10]), .QN(n6805) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_23_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[23]), .CK(clk),
.RN(n6918), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[49]), .QN(n6801) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_22_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[22]), .CK(clk),
.RN(n6919), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[48]), .QN(n6800) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_21_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[21]), .CK(clk),
.RN(n6917), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[47]), .QN(n6799) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_18_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[18]), .CK(clk),
.RN(n6919), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[44]), .QN(n6798) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_19_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[19]), .CK(clk),
.RN(n6919), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[45]), .QN(n6797) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_28_ ( .D(n1424), .CK(clk), .RN(
n6983), .Q(FPSENCOS_d_ff2_Y[28]), .QN(n6796) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_23_ ( .D(n1793), .CK(clk), .RN(
n6977), .Q(FPSENCOS_d_ff2_X[23]), .QN(n6795) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_25_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[25]), .CK(clk),
.RN(n6941), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[51]), .QN(n6794) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n1888), .CK(
clk), .RN(n6987), .Q(FPMULT_Sgf_normalized_result[6]), .QN(n6793) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n1886), .CK(
clk), .RN(n6987), .Q(FPMULT_Sgf_normalized_result[4]), .QN(n6792) );
DFFRX1TS FPSENCOS_reg_region_flag_Q_reg_1_ ( .D(n1830), .CK(clk), .RN(n6964),
.Q(FPSENCOS_d_ff1_shift_region_flag_out[1]), .QN(n6791) );
DFFRX1TS FPADDSUB_YRegister_Q_reg_3_ ( .D(n1296), .CK(clk), .RN(n6941), .Q(
FPADDSUB_intDY[3]), .QN(n6789) );
DFFRX1TS FPADDSUB_YRegister_Q_reg_8_ ( .D(n1276), .CK(clk), .RN(n6923), .Q(
FPADDSUB_intDY[8]), .QN(n6788) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_9_ ( .D(n1231), .CK(clk), .RN(n6925), .Q(
FPADDSUB_intDY[9]), .QN(n6786) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_2_ ( .D(n1289), .CK(clk), .RN(n6921), .Q(
FPADDSUB_intDY[2]), .QN(n6785) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_10_ ( .D(n1248), .CK(clk), .RN(n5030), .Q(
FPADDSUB_intDY[10]), .QN(n6784) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_4_ ( .D(n1255), .CK(clk), .RN(n6914), .Q(
FPADDSUB_intDY[4]), .QN(n6783) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_6_ ( .D(n1299), .CK(clk), .RN(n6940), .Q(
FPADDSUB_intDY[6]), .QN(n6782) );
DFFRX1TS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(
n1603), .CK(clk), .RN(n6917), .Q(result_add_subt[23]), .QN(n6781) );
DFFRX2TS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(
n1844), .CK(clk), .RN(n6916), .QN(n6780) );
DFFRX2TS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(
n1555), .CK(clk), .RN(n6920), .QN(n6779) );
DFFRX2TS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(
n1571), .CK(clk), .RN(n6918), .QN(n6778) );
DFFRX2TS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(
n1583), .CK(clk), .RN(n6918), .QN(n6777) );
DFFRX2TS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(
n1595), .CK(clk), .RN(n6918), .QN(n6776) );
DFFRX2TS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(
n1599), .CK(clk), .RN(n6917), .QN(n6775) );
DFFRX1TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_5_ ( .D(n1668),
.CK(clk), .RN(n2218), .Q(FPADDSUB_Add_Subt_result[5]), .QN(n6771) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_5_ ( .D(n1262), .CK(clk), .RN(n6943), .Q(
FPADDSUB_intDY[5]), .QN(n6770) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_7_ ( .D(n1241), .CK(clk), .RN(n6931), .Q(
FPADDSUB_intDY[7]), .QN(n6769) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n1653),
.CK(clk), .RN(n6921), .Q(FPADDSUB_Sgf_normalized_result[21]), .QN(
n6768) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n1654),
.CK(clk), .RN(n6941), .Q(FPADDSUB_Sgf_normalized_result[22]), .QN(
n6767) );
DFFRX1TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_7_ ( .D(n1670),
.CK(clk), .RN(n2218), .Q(FPADDSUB_Add_Subt_result[7]), .QN(n6766) );
DFFRX1TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_2_ ( .D(n1665),
.CK(clk), .RN(n6933), .Q(FPADDSUB_Add_Subt_result[2]), .QN(n6765) );
DFFRX1TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_11_ ( .D(n1674),
.CK(clk), .RN(n6932), .Q(FPADDSUB_Add_Subt_result[11]), .QN(n6764) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_23_ ( .D(n1334), .CK(clk), .RN(n6930), .Q(
FPADDSUB_intDY[23]), .QN(n6762) );
DFFRX2TS FPADDSUB_XRegister_Q_reg_16_ ( .D(n1253), .CK(clk), .RN(n2225), .Q(
FPADDSUB_intDX[16]), .QN(n6761) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_29_ ( .D(n1340), .CK(clk), .RN(n2226), .Q(
FPADDSUB_intDY[29]), .QN(n6760) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n1650),
.CK(clk), .RN(n6939), .Q(FPADDSUB_Sgf_normalized_result[18]), .QN(
n6759) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n1651),
.CK(clk), .RN(n6913), .Q(FPADDSUB_Sgf_normalized_result[19]), .QN(
n6758) );
DFFRX1TS FPADDSUB_XRegister_Q_reg_10_ ( .D(n1249), .CK(clk), .RN(n6931), .Q(
FPADDSUB_intDX[10]), .QN(n6755) );
DFFRX2TS FPMULT_Sel_A_Q_reg_0_ ( .D(n2056), .CK(clk), .RN(n6998), .Q(
FPMULT_FSM_selector_A), .QN(n6803) );
DFFRX2TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_3_ ( .D(n1666),
.CK(clk), .RN(n2217), .Q(FPADDSUB_Add_Subt_result[3]), .QN(n6754) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_26_ ( .D(n1337), .CK(clk), .RN(n2225), .Q(
FPADDSUB_intDY[26]), .QN(n6753) );
DFFRX2TS FPADDSUB_XRegister_Q_reg_23_ ( .D(n1308), .CK(clk), .RN(n6926), .Q(
FPADDSUB_intDX[23]), .QN(n6751) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_24_ ( .D(n1428), .CK(clk), .RN(
n6978), .Q(FPSENCOS_d_ff2_Y[24]), .QN(n6750) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_12_ ( .D(n1235), .CK(clk), .RN(n6925), .Q(
FPADDSUB_intDY[12]), .QN(n6749) );
DFFRX1TS FPADDSUB_XRegister_Q_reg_11_ ( .D(n1239), .CK(clk), .RN(n2225), .Q(
FPADDSUB_intDX[11]), .QN(n6748) );
DFFRX1TS FPADDSUB_XRegister_Q_reg_14_ ( .D(n1246), .CK(clk), .RN(n5030), .Q(
FPADDSUB_intDX[14]), .QN(n6747) );
DFFRX1TS FPADDSUB_XRegister_Q_reg_19_ ( .D(n1294), .CK(clk), .RN(n6940), .Q(
FPADDSUB_intDX[19]), .QN(n6746) );
DFFRX1TS FPADDSUB_YRegister_Q_reg_24_ ( .D(n1335), .CK(clk), .RN(n6930), .Q(
FPADDSUB_intDY[24]), .QN(n6745) );
DFFRX1TS FPADDSUB_XRegister_Q_reg_17_ ( .D(n1260), .CK(clk), .RN(n6914), .Q(
FPADDSUB_intDX[17]), .QN(n6744) );
DFFRX1TS FPADDSUB_XRegister_Q_reg_20_ ( .D(n1271), .CK(clk), .RN(n6923), .Q(
FPADDSUB_intDX[20]), .QN(n6743) );
DFFRX1TS FPADDSUB_XRegister_Q_reg_18_ ( .D(n1284), .CK(clk), .RN(n6922), .Q(
FPADDSUB_intDX[18]), .QN(n6742) );
DFFRX1TS FPADDSUB_XRegister_Q_reg_22_ ( .D(n1303), .CK(clk), .RN(n6929), .Q(
FPADDSUB_intDX[22]), .QN(n6741) );
DFFRX1TS FPADDSUB_YRegister_Q_reg_28_ ( .D(n1339), .CK(clk), .RN(n6930), .Q(
FPADDSUB_intDY[28]), .QN(n6740) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_25_ ( .D(n1336), .CK(clk), .RN(n6912), .Q(
FPADDSUB_intDY[25]), .QN(n6739) );
DFFRX1TS FPMULT_Sel_B_Q_reg_0_ ( .D(n1916), .CK(clk), .RN(n7007), .Q(
FPMULT_FSM_selector_B[0]), .QN(n6738) );
DFFRX1TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_19_ ( .D(n1682),
.CK(clk), .RN(n2218), .Q(FPADDSUB_Add_Subt_result[19]), .QN(n6736) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n1647),
.CK(clk), .RN(n6939), .Q(FPADDSUB_Sgf_normalized_result[15]), .QN(
n6735) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n1648),
.CK(clk), .RN(n6939), .Q(FPADDSUB_Sgf_normalized_result[16]), .QN(
n6734) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_3_ ( .D(n2060), .CK(clk), .RN(n6924),
.Q(FPMULT_FS_Module_state_reg[3]), .QN(n6730) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_18_ ( .D(n1283), .CK(clk), .RN(n6922), .Q(
FPADDSUB_intDY[18]), .QN(n6729) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_17_ ( .D(n1259), .CK(clk), .RN(n2226), .Q(
FPADDSUB_intDY[17]), .QN(n6728) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_21_ ( .D(n1286), .CK(clk), .RN(n6922), .Q(
FPADDSUB_intDY[21]), .QN(n6726) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_13_ ( .D(n1266), .CK(clk), .RN(n6923), .Q(
FPADDSUB_intDY[13]), .QN(n6725) );
DFFRX2TS FPADDSUB_XRegister_Q_reg_28_ ( .D(n1323), .CK(clk), .RN(n6925), .Q(
FPADDSUB_intDX[28]), .QN(n6724) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_20_ ( .D(n1270), .CK(clk), .RN(n6923), .Q(
FPADDSUB_intDY[20]), .QN(n6723) );
DFFRX1TS FPADDSUB_XRegister_Q_reg_13_ ( .D(n1267), .CK(clk), .RN(n6923), .Q(
FPADDSUB_intDX[13]), .QN(n6722) );
DFFRX1TS FPADDSUB_XRegister_Q_reg_21_ ( .D(n1287), .CK(clk), .RN(n6922), .Q(
FPADDSUB_intDX[21]), .QN(n6721) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n1644),
.CK(clk), .RN(n6938), .Q(FPADDSUB_Sgf_normalized_result[12]), .QN(
n6718) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n1646),
.CK(clk), .RN(n6939), .Q(FPADDSUB_Sgf_normalized_result[14]), .QN(
n6717) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_11_ ( .D(n1238), .CK(clk), .RN(n2225), .Q(
FPADDSUB_intDY[11]), .QN(n6714) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_14_ ( .D(n1245), .CK(clk), .RN(n6924), .Q(
FPADDSUB_intDY[14]), .QN(n6712) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_25_ ( .D(n1795), .CK(clk), .RN(
n6978), .Q(FPSENCOS_d_ff2_X[25]), .QN(n6710) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_26_ ( .D(n1796), .CK(clk), .RN(
n6979), .Q(FPSENCOS_d_ff2_X[26]), .QN(n6709) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_29_ ( .D(n1799), .CK(clk), .RN(
n6983), .Q(FPSENCOS_d_ff2_X[29]), .QN(n6708) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_24_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[24]), .CK(clk),
.RN(n6943), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[50]), .QN(n6707) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_27_ ( .D(n1797), .CK(clk), .RN(
n6980), .Q(FPSENCOS_d_ff2_X[27]), .QN(n6706) );
DFFRX1TS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(
n1631), .CK(clk), .RN(n6916), .Q(result_add_subt[30]), .QN(n6705) );
DFFRX2TS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(
n1551), .CK(clk), .RN(n6920), .QN(n6698) );
DFFRX2TS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(
n1559), .CK(clk), .RN(n6920), .QN(n6697) );
DFFRX2TS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(
n1563), .CK(clk), .RN(n6919), .QN(n6696) );
DFFRX2TS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(
n1567), .CK(clk), .RN(n6920), .QN(n6695) );
DFFRX2TS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(
n1575), .CK(clk), .RN(n6919), .QN(n6694) );
DFFRX2TS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(
n1579), .CK(clk), .RN(n6919), .QN(n6693) );
DFFRX2TS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(
n1587), .CK(clk), .RN(n6918), .QN(n6692) );
DFFRX2TS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(
n1591), .CK(clk), .RN(n6919), .QN(n6691) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_24_ ( .D(n1656),
.CK(clk), .RN(n6940), .Q(FPADDSUB_Sgf_normalized_result[24]), .QN(
n6690) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n1655),
.CK(clk), .RN(n6940), .Q(FPADDSUB_Sgf_normalized_result[23]), .QN(
n6689) );
DFFRX2TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_16_ ( .D(n1679),
.CK(clk), .RN(n6932), .Q(FPADDSUB_Add_Subt_result[16]), .QN(n6688) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_24_ ( .D(n1794), .CK(clk), .RN(
n6977), .Q(FPSENCOS_d_ff2_X[24]), .QN(n6687) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n1652),
.CK(clk), .RN(n6941), .Q(FPADDSUB_Sgf_normalized_result[20]), .QN(
n6686) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_30_ ( .D(n1341), .CK(clk), .RN(n6930), .Q(
FPADDSUB_intDY[30]), .QN(n6685) );
DFFRX2TS FPADDSUB_XRegister_Q_reg_7_ ( .D(n1242), .CK(clk), .RN(n5028), .Q(
FPADDSUB_intDX[7]), .QN(n6684) );
DFFRX2TS FPADDSUB_XRegister_Q_reg_5_ ( .D(n1263), .CK(clk), .RN(n6930), .Q(
FPADDSUB_intDX[5]), .QN(n6683) );
DFFRX1TS FPADDSUB_XRegister_Q_reg_9_ ( .D(n1232), .CK(clk), .RN(n6931), .Q(
FPADDSUB_intDX[9]), .QN(n6682) );
DFFRX1TS FPADDSUB_XRegister_Q_reg_8_ ( .D(n1277), .CK(clk), .RN(n6921), .Q(
FPADDSUB_intDX[8]), .QN(n6681) );
DFFRX1TS FPSENCOS_reg_operation_Q_reg_0_ ( .D(n1705), .CK(clk), .RN(n6971),
.Q(FPSENCOS_d_ff1_operation_out), .QN(n6680) );
DFFRX1TS FPADDSUB_YRegister_Q_reg_0_ ( .D(n1342), .CK(clk), .RN(n6913), .Q(
FPADDSUB_intDY[0]), .QN(n6679) );
DFFRX1TS FPADDSUB_YRegister_Q_reg_27_ ( .D(n1338), .CK(clk), .RN(n6930), .Q(
FPADDSUB_intDY[27]), .QN(n6678) );
DFFRX2TS FPSENCOS_cont_var_count_reg_1_ ( .D(n1836), .CK(clk), .RN(n6944),
.Q(FPSENCOS_cont_var_out[1]), .QN(n6677) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n1645),
.CK(clk), .RN(n6938), .Q(FPADDSUB_Sgf_normalized_result[13]), .QN(
n6676) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n1649),
.CK(clk), .RN(n6939), .Q(FPADDSUB_Sgf_normalized_result[17]), .QN(
n6675) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n1890), .CK(
clk), .RN(n5023), .Q(FPMULT_Sgf_normalized_result[8]), .QN(n6673) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_0_ ( .D(n2059), .CK(clk), .RN(n6929),
.Q(FPMULT_FS_Module_state_reg[0]), .QN(n6672) );
DFFRX2TS FPMULT_Sel_B_Q_reg_1_ ( .D(n1915), .CK(clk), .RN(n6996), .Q(
FPMULT_FSM_selector_B[1]), .QN(n6671) );
DFFRX2TS FPSENCOS_cordic_FSM_state_reg_reg_2_ ( .D(n2063), .CK(clk), .RN(
n6915), .Q(FPSENCOS_cordic_FSM_state_reg[2]), .QN(n6670) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_19_ ( .D(n1293), .CK(clk), .RN(n6913), .Q(
FPADDSUB_intDY[19]), .QN(n6669) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_22_ ( .D(n1302), .CK(clk), .RN(n6941), .Q(
FPADDSUB_intDY[22]), .QN(n6668) );
DFFRX2TS FPSENCOS_cordic_FSM_state_reg_reg_3_ ( .D(n2064), .CK(clk), .RN(
n6916), .Q(FPSENCOS_cordic_FSM_state_reg[3]), .QN(n6667) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_15_ ( .D(n1279), .CK(clk), .RN(n6922), .Q(
FPADDSUB_intDY[15]), .QN(n6666) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_28_ ( .D(n1798), .CK(clk), .RN(
n6982), .QN(n6665) );
DFFRX1TS FPADDSUB_XRegister_Q_reg_4_ ( .D(n1256), .CK(clk), .RN(n6940), .Q(
FPADDSUB_intDX[4]), .QN(n6664) );
DFFRX1TS FPADDSUB_XRegister_Q_reg_6_ ( .D(n1300), .CK(clk), .RN(n5030), .Q(
FPADDSUB_intDX[6]), .QN(n6663) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_1_ ( .D(n2058), .CK(clk), .RN(n6928),
.Q(FPMULT_FS_Module_state_reg[1]), .QN(n6662) );
DFFRX1TS FPADDSUB_XRegister_Q_reg_15_ ( .D(n1280), .CK(clk), .RN(n6922), .Q(
FPADDSUB_intDX[15]), .QN(n6661) );
DFFRX2TS FPSENCOS_cordic_FSM_state_reg_reg_0_ ( .D(n2062), .CK(clk), .RN(
n6915), .Q(FPSENCOS_cordic_FSM_state_reg[0]), .QN(n6660) );
DFFRXLTS NaN_dff_Q_reg_0_ ( .D(NaN_reg), .CK(clk), .RN(n6915), .Q(NaN_flag)
);
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_20_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[20]), .CK(clk),
.RN(n6918), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[46]), .QN(n6802) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_SignRegister_Q_reg_0_ ( .D(n1330),
.CK(clk), .RN(n6936), .Q(FPADDSUB_sign_final_result), .QN(n6804) );
DFFRX2TS FPSENCOS_cont_var_count_reg_0_ ( .D(n1837), .CK(clk), .RN(n6963),
.Q(FPSENCOS_cont_var_out[0]), .QN(n6752) );
DFFRX1TS FPADDSUB_XRegister_Q_reg_2_ ( .D(n1290), .CK(clk), .RN(n6913), .Q(
FPADDSUB_intDX[2]), .QN(n6757) );
DFFRX2TS FPADDSUB_XRegister_Q_reg_3_ ( .D(n1297), .CK(clk), .RN(n6921), .Q(
FPADDSUB_intDX[3]), .QN(n6731) );
DFFRX2TS FPSENCOS_cont_iter_count_reg_3_ ( .D(n1835), .CK(clk), .RN(n6964),
.Q(FPSENCOS_cont_iter_out[3]), .QN(n6711) );
DFFRX1TS FPADDSUB_YRegister_Q_reg_1_ ( .D(n1273), .CK(clk), .RN(n6923), .Q(
FPADDSUB_intDY[1]), .QN(n6790) );
DFFRX1TS FPADDSUB_Sel_C_Q_reg_0_ ( .D(n1688), .CK(clk), .RN(n1343), .Q(
FPADDSUB_FSM_selector_C), .QN(n6716) );
DFFRX1TS FPADDSUB_XRegister_Q_reg_1_ ( .D(n1274), .CK(clk), .RN(n6921), .Q(
FPADDSUB_intDX[1]), .QN(n6756) );
CMPR32X2TS DP_OP_134J305_123_859_U10 ( .A(FPMULT_S_Oper_A_exp[0]), .B(n5013),
.C(DP_OP_134J305_123_859_n22), .CO(DP_OP_134J305_123_859_n9), .S(
FPMULT_Exp_module_Data_S[0]) );
CMPR32X2TS DP_OP_134J305_123_859_U9 ( .A(DP_OP_134J305_123_859_n21), .B(
FPMULT_S_Oper_A_exp[1]), .C(DP_OP_134J305_123_859_n9), .CO(
DP_OP_134J305_123_859_n8), .S(FPMULT_Exp_module_Data_S[1]) );
CMPR32X2TS DP_OP_134J305_123_859_U8 ( .A(DP_OP_134J305_123_859_n20), .B(
FPMULT_S_Oper_A_exp[2]), .C(DP_OP_134J305_123_859_n8), .CO(
DP_OP_134J305_123_859_n7), .S(FPMULT_Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_134J305_123_859_U7 ( .A(DP_OP_134J305_123_859_n19), .B(
FPMULT_S_Oper_A_exp[3]), .C(DP_OP_134J305_123_859_n7), .CO(
DP_OP_134J305_123_859_n6), .S(FPMULT_Exp_module_Data_S[3]) );
CMPR32X2TS DP_OP_134J305_123_859_U6 ( .A(DP_OP_134J305_123_859_n18), .B(
FPMULT_S_Oper_A_exp[4]), .C(DP_OP_134J305_123_859_n6), .CO(
DP_OP_134J305_123_859_n5), .S(FPMULT_Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_134J305_123_859_U5 ( .A(DP_OP_134J305_123_859_n17), .B(
FPMULT_S_Oper_A_exp[5]), .C(DP_OP_134J305_123_859_n5), .CO(
DP_OP_134J305_123_859_n4), .S(FPMULT_Exp_module_Data_S[5]) );
CMPR32X2TS DP_OP_134J305_123_859_U4 ( .A(DP_OP_134J305_123_859_n16), .B(
FPMULT_S_Oper_A_exp[6]), .C(DP_OP_134J305_123_859_n4), .CO(
DP_OP_134J305_123_859_n3), .S(FPMULT_Exp_module_Data_S[6]) );
CMPR32X2TS DP_OP_134J305_123_859_U3 ( .A(DP_OP_134J305_123_859_n15), .B(
FPMULT_S_Oper_A_exp[7]), .C(DP_OP_134J305_123_859_n3), .CO(
DP_OP_134J305_123_859_n2), .S(FPMULT_Exp_module_Data_S[7]) );
CMPR32X2TS DP_OP_134J305_123_859_U2 ( .A(n2323), .B(FPMULT_S_Oper_A_exp[8]),
.C(DP_OP_134J305_123_859_n2), .CO(DP_OP_134J305_123_859_n1), .S(
FPMULT_Exp_module_Data_S[8]) );
DFFRX2TS FPADDSUB_Sel_B_Q_reg_0_ ( .D(n1698), .CK(clk), .RN(n1343), .Q(
FPADDSUB_FSM_selector_B[0]), .QN(n6715) );
DFFRX2TS FPADDSUB_FS_Module_state_reg_reg_2_ ( .D(n1838), .CK(clk), .RN(
n6916), .Q(FPADDSUB_FS_Module_state_reg[2]), .QN(n6719) );
DFFRX2TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_21_ ( .D(n1684),
.CK(clk), .RN(n2217), .Q(FPADDSUB_Add_Subt_result[21]), .QN(n6773) );
DFFRXLTS R_13 ( .D(n1964), .CK(clk), .RN(n6928), .Q(n6897) );
DFFSRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n1640),
.CK(clk), .SN(1'b1), .RN(n7006), .Q(FPADDSUB_Sgf_normalized_result[8])
);
DFFSRHQX2TS FPADDSUB_FS_Module_state_reg_reg_0_ ( .D(n1840), .CK(clk), .SN(
1'b1), .RN(n2286), .Q(FPADDSUB_FS_Module_state_reg[0]) );
DFFSX1TS R_60 ( .D(FPMULT_Sgf_operation_Result[31]), .CK(clk), .SN(n2288),
.Q(n6865) );
DFFSX1TS R_42 ( .D(FPMULT_Sgf_operation_Result[32]), .CK(clk), .SN(n2287),
.Q(n6876) );
DFFSX1TS R_63 ( .D(FPMULT_Sgf_operation_Result[33]), .CK(clk), .SN(n2288),
.Q(n6863) );
DFFSX1TS FPADDSUB_Exp_Operation_Module_Overflow_Q_reg_0_ ( .D(n2835), .CK(
clk), .SN(n7006), .Q(n6787), .QN(overflow_flag_addsubt) );
DFFRX1TS FPADDSUB_ASRegister_Q_reg_0_ ( .D(n1331), .CK(clk), .RN(n6943), .Q(
FPADDSUB_intAS) );
DFFRXLTS R_17 ( .D(n6908), .CK(clk), .RN(n6929), .Q(n6893) );
DFFRXLTS R_37 ( .D(n1957), .CK(clk), .RN(n2286), .Q(n6879) );
DFFRXLTS R_61 ( .D(n1949), .CK(clk), .RN(n2286), .Q(n6864) );
DFFRX1TS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(
n1611), .CK(clk), .RN(n6917), .Q(result_add_subt[25]), .QN(n6703) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n1885), .CK(
clk), .RN(n2216), .Q(FPMULT_Sgf_normalized_result[3]), .QN(n6727) );
DFFRX2TS FPADDSUB_Sel_A_Q_reg_0_ ( .D(n1699), .CK(clk), .RN(n1343), .Q(
FPADDSUB_FSM_selector_A) );
DFFRX2TS FPADDSUB_Sel_B_Q_reg_1_ ( .D(n1846), .CK(clk), .RN(n1343), .Q(
FPADDSUB_FSM_selector_B[1]) );
DFFRX2TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_20_ ( .D(n1683),
.CK(clk), .RN(n2217), .Q(FPADDSUB_Add_Subt_result[20]) );
DFFRX2TS FPADDSUB_XRegister_Q_reg_29_ ( .D(n1326), .CK(clk), .RN(n6937), .Q(
FPADDSUB_intDX[29]) );
DFFRX2TS FPADDSUB_XRegister_Q_reg_25_ ( .D(n1314), .CK(clk), .RN(n6936), .Q(
FPADDSUB_intDX[25]) );
DFFRX2TS FPADDSUB_YRegister_Q_reg_16_ ( .D(n1252), .CK(clk), .RN(n2218), .Q(
FPADDSUB_intDY[16]) );
DFFRX2TS FPADDSUB_XRegister_Q_reg_26_ ( .D(n1317), .CK(clk), .RN(n6929), .Q(
FPADDSUB_intDX[26]) );
DFFRX2TS FPADDSUB_XRegister_Q_reg_12_ ( .D(n1236), .CK(clk), .RN(n6925), .Q(
FPADDSUB_intDX[12]) );
DFFRX2TS FPADDSUB_XRegister_Q_reg_27_ ( .D(n1320), .CK(clk), .RN(n6916), .Q(
FPADDSUB_intDX[27]) );
DFFRX4TS FPSENCOS_cordic_FSM_state_reg_reg_1_ ( .D(
FPSENCOS_cordic_FSM_state_next_1_), .CK(clk), .RN(n6916), .Q(
FPSENCOS_cordic_FSM_state_reg[1]), .QN(n6720) );
DFFRX2TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_10_ ( .D(n1673),
.CK(clk), .RN(n6932), .Q(FPADDSUB_Add_Subt_result[10]) );
DFFRX2TS FPADDSUB_XRegister_Q_reg_0_ ( .D(n1305), .CK(clk), .RN(n6929), .Q(
FPADDSUB_intDX[0]) );
DFFRX2TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n1882), .CK(
clk), .RN(n6991), .Q(FPMULT_Sgf_normalized_result[0]) );
DFFRX2TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_13_ ( .D(n1676),
.CK(clk), .RN(n6932), .Q(FPADDSUB_Add_Subt_result[13]) );
DFFRX2TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_14_ ( .D(n1677),
.CK(clk), .RN(n6932), .Q(FPADDSUB_Add_Subt_result[14]) );
DFFRX2TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n1884), .CK(
clk), .RN(n6987), .Q(FPMULT_Sgf_normalized_result[2]) );
DFFRX2TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_15_ ( .D(n1678),
.CK(clk), .RN(n6932), .Q(FPADDSUB_Add_Subt_result[15]) );
DFFRX2TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_8_ ( .D(n1671),
.CK(clk), .RN(n6932), .Q(FPADDSUB_Add_Subt_result[8]) );
DFFRX2TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_12_ ( .D(n1675),
.CK(clk), .RN(n6932), .Q(FPADDSUB_Add_Subt_result[12]) );
DFFRX2TS FPSENCOS_reg_val_muxY_2stage_Q_reg_27_ ( .D(n1425), .CK(clk), .RN(
n6980), .Q(FPSENCOS_d_ff2_Y[27]) );
DFFRX2TS FPADDSUB_Exp_Operation_Module_exp_result_Q_reg_3_ ( .D(n1694), .CK(
clk), .RN(n6935), .Q(FPADDSUB_exp_oper_result[3]) );
DFFRX1TS FPADDSUB_Exp_Operation_Module_exp_result_Q_reg_0_ ( .D(n1691), .CK(
clk), .RN(n6934), .Q(FPADDSUB_exp_oper_result[0]) );
DFFRX1TS FPADDSUB_Exp_Operation_Module_exp_result_Q_reg_1_ ( .D(n1692), .CK(
clk), .RN(n6934), .Q(FPADDSUB_exp_oper_result[1]) );
DFFRX1TS FPADDSUB_Exp_Operation_Module_exp_result_Q_reg_4_ ( .D(n1695), .CK(
clk), .RN(n6935), .Q(FPADDSUB_exp_oper_result[4]) );
DFFRX1TS FPSENCOS_reg_ch_mux_2_Q_reg_1_ ( .D(n1703), .CK(clk), .RN(n6972),
.Q(FPSENCOS_sel_mux_2_reg[1]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_16_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[16]), .CK(clk),
.RN(n6918), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[42]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_17_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[17]), .CK(clk),
.RN(n6917), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[43]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_29_ ( .D(n1423), .CK(clk), .RN(
n6983), .Q(FPSENCOS_d_ff2_Y[29]) );
DFFRX1TS FPSENCOS_reg_ch_mux_1_Q_reg_0_ ( .D(n1706), .CK(clk), .RN(n6972),
.Q(FPSENCOS_sel_mux_1_reg) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_11_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[11]), .CK(clk),
.RN(n6920), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[37]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_10_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[10]), .CK(clk),
.RN(n6918), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[36]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_12_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[12]), .CK(clk),
.RN(n6920), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[38]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n1633),
.CK(clk), .RN(n6936), .Q(FPADDSUB_Sgf_normalized_result[1]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n1641),
.CK(clk), .RN(n6938), .Q(FPADDSUB_Sgf_normalized_result[9]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n1634),
.CK(clk), .RN(n6936), .Q(FPADDSUB_Sgf_normalized_result[2]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n1643),
.CK(clk), .RN(n6938), .Q(FPADDSUB_Sgf_normalized_result[11]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n1642),
.CK(clk), .RN(n6938), .Q(FPADDSUB_Sgf_normalized_result[10]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n1638),
.CK(clk), .RN(n6937), .Q(FPADDSUB_Sgf_normalized_result[6]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n1639),
.CK(clk), .RN(n6937), .Q(FPADDSUB_Sgf_normalized_result[7]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n1635),
.CK(clk), .RN(n6936), .Q(FPADDSUB_Sgf_normalized_result[3]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n1636),
.CK(clk), .RN(n6937), .Q(FPADDSUB_Sgf_normalized_result[4]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n1637),
.CK(clk), .RN(n6937), .Q(FPADDSUB_Sgf_normalized_result[5]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n1893), .CK(
clk), .RN(n2216), .Q(FPMULT_Sgf_normalized_result[11]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n1895), .CK(
clk), .RN(n2215), .Q(FPMULT_Sgf_normalized_result[13]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n1897), .CK(
clk), .RN(n5023), .Q(FPMULT_Sgf_normalized_result[15]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n1899), .CK(
clk), .RN(n6988), .Q(FPMULT_Sgf_normalized_result[17]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n1901), .CK(
clk), .RN(n6990), .Q(FPMULT_Sgf_normalized_result[19]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n1903), .CK(
clk), .RN(n6985), .Q(FPMULT_Sgf_normalized_result[21]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n1894), .CK(
clk), .RN(n2216), .Q(FPMULT_Sgf_normalized_result[12]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n1896), .CK(
clk), .RN(n2215), .Q(FPMULT_Sgf_normalized_result[14]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n1898), .CK(
clk), .RN(n6987), .Q(FPMULT_Sgf_normalized_result[16]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n1900), .CK(
clk), .RN(n6990), .Q(FPMULT_Sgf_normalized_result[18]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n1902), .CK(
clk), .RN(n6989), .Q(FPMULT_Sgf_normalized_result[20]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n1904), .CK(
clk), .RN(n2216), .Q(FPMULT_Sgf_normalized_result[22]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n2051), .CK(clk),
.RN(n6997), .Q(FPMULT_Op_MX[27]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n2053), .CK(clk),
.RN(n6997), .Q(FPMULT_Op_MX[29]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_25_ ( .D(n1427), .CK(clk), .RN(
n6978), .Q(FPSENCOS_d_ff2_Y[25]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_26_ ( .D(n1426), .CK(clk), .RN(
n6979), .Q(FPSENCOS_d_ff2_Y[26]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n1987), .CK(clk), .RN(
n6992), .Q(FPMULT_Add_result[2]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n1985), .CK(clk), .RN(
n6992), .Q(FPMULT_Add_result[4]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n1984), .CK(clk), .RN(
n6993), .Q(FPMULT_Add_result[5]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n1983), .CK(clk), .RN(
n6993), .Q(FPMULT_Add_result[6]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n1982), .CK(clk), .RN(
n6993), .Q(FPMULT_Add_result[7]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n1981), .CK(clk), .RN(
n6993), .Q(FPMULT_Add_result[8]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n1980), .CK(clk), .RN(
n6993), .Q(FPMULT_Add_result[9]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n1979), .CK(clk),
.RN(n6993), .Q(FPMULT_Add_result[10]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n1978), .CK(clk),
.RN(n6993), .Q(FPMULT_Add_result[11]) );
DFFRX1TS operation_dff_Q_reg_0_ ( .D(operation[1]), .CK(clk), .RN(n6940),
.Q(operation_reg_0_) );
DFFRX1TS FPSENCOS_reg_ch_mux_3_Q_reg_0_ ( .D(n1702), .CK(clk), .RN(n6972),
.Q(FPSENCOS_sel_mux_3_reg) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n2022), .CK(clk),
.RN(n6992), .Q(FPMULT_Op_MY[30]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n2048), .CK(clk),
.RN(n6997), .Q(FPMULT_Op_MX[24]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_7_ ( .D(n1907), .CK(clk), .RN(
n7007), .Q(FPMULT_exp_oper_result[7]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_5_ ( .D(n1909), .CK(clk), .RN(
n7007), .Q(FPMULT_exp_oper_result[5]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_3_ ( .D(n1911), .CK(clk), .RN(
n7007), .Q(FPMULT_exp_oper_result[3]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_2_ ( .D(n1912), .CK(clk), .RN(
n7007), .Q(FPMULT_exp_oper_result[2]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_0_ ( .D(n1914), .CK(clk), .RN(
n5022), .Q(FPMULT_exp_oper_result[0]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_30_ ( .D(n1422), .CK(clk), .RN(
n6983), .Q(FPSENCOS_d_ff2_Y[30]) );
DFFRX1TS FPADDSUB_Exp_Operation_Module_exp_result_Q_reg_7_ ( .D(n1690), .CK(
clk), .RN(n6935), .Q(FPADDSUB_exp_oper_result[7]) );
DFFRX1TS FPADDSUB_Exp_Operation_Module_exp_result_Q_reg_5_ ( .D(n1696), .CK(
clk), .RN(n6935), .Q(FPADDSUB_exp_oper_result[5]) );
DFFRX1TS FPADDSUB_Exp_Operation_Module_exp_result_Q_reg_6_ ( .D(n1697), .CK(
clk), .RN(n6935), .Q(FPADDSUB_exp_oper_result[6]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n2015), .CK(clk),
.RN(n6987), .Q(FPMULT_Op_MY[23]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_13_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[13]), .CK(clk),
.RN(n6920), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[39]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_14_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[14]), .CK(clk),
.RN(n6919), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[40]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_15_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[15]), .CK(clk),
.RN(n6919), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[41]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_31_ ( .D(n1843), .CK(clk), .RN(n6972), .Q(
FPSENCOS_d_ff_Xn[31]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n2019), .CK(clk),
.RN(n6996), .Q(FPMULT_Op_MY[27]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_9_ ( .D(n1544), .CK(clk), .RN(n6960), .Q(
FPSENCOS_d_ff_Xn[9]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_11_ ( .D(n1552), .CK(clk), .RN(n6958), .Q(
FPSENCOS_d_ff_Xn[11]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_4_ ( .D(n1524), .CK(clk), .RN(n6953), .Q(
FPSENCOS_d_ff_Xn[4]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_8_ ( .D(n1540), .CK(clk), .RN(n6948), .Q(
FPSENCOS_d_ff_Xn[8]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_15_ ( .D(n1568), .CK(clk), .RN(n6947), .Q(
FPSENCOS_d_ff_Xn[15]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_18_ ( .D(n1580), .CK(clk), .RN(n6946), .Q(
FPSENCOS_d_ff_Xn[18]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_21_ ( .D(n1592), .CK(clk), .RN(n6945), .Q(
FPSENCOS_d_ff_Xn[21]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_22_ ( .D(n1596), .CK(clk), .RN(n6975), .Q(
FPSENCOS_d_ff_Xn[22]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_23_ ( .D(n1600), .CK(clk), .RN(n6977), .Q(
FPSENCOS_d_ff_Xn[23]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_30_ ( .D(n1628), .CK(clk), .RN(n6983), .Q(
FPSENCOS_d_ff_Xn[30]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_0_ ( .D(n1411), .CK(clk), .RN(n6972), .Q(
FPSENCOS_d_ff_Xn[0]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_9_ ( .D(n1457), .CK(clk), .RN(
n6959), .Q(FPSENCOS_d_ff2_Y[9]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_12_ ( .D(n1451), .CK(clk), .RN(
n6958), .Q(FPSENCOS_d_ff2_Y[12]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_11_ ( .D(n1453), .CK(clk), .RN(
n6958), .Q(FPSENCOS_d_ff2_Y[11]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_7_ ( .D(n1461), .CK(clk), .RN(
n6957), .Q(FPSENCOS_d_ff2_Y[7]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_14_ ( .D(n1447), .CK(clk), .RN(
n6956), .Q(FPSENCOS_d_ff2_Y[14]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_10_ ( .D(n1455), .CK(clk), .RN(
n6955), .Q(FPSENCOS_d_ff2_Y[10]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_16_ ( .D(n1443), .CK(clk), .RN(
n6954), .Q(FPSENCOS_d_ff2_Y[16]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_4_ ( .D(n1467), .CK(clk), .RN(
n6953), .Q(FPSENCOS_d_ff2_Y[4]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_17_ ( .D(n1441), .CK(clk), .RN(
n6952), .Q(FPSENCOS_d_ff2_Y[17]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_5_ ( .D(n1465), .CK(clk), .RN(
n6951), .Q(FPSENCOS_d_ff2_Y[5]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_13_ ( .D(n1449), .CK(clk), .RN(
n6950), .Q(FPSENCOS_d_ff2_Y[13]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_20_ ( .D(n1435), .CK(clk), .RN(
n6949), .Q(FPSENCOS_d_ff2_Y[20]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_8_ ( .D(n1459), .CK(clk), .RN(
n6948), .Q(FPSENCOS_d_ff2_Y[8]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_15_ ( .D(n1445), .CK(clk), .RN(
n6947), .Q(FPSENCOS_d_ff2_Y[15]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_18_ ( .D(n1439), .CK(clk), .RN(
n6946), .Q(FPSENCOS_d_ff2_Y[18]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_2_ ( .D(n1471), .CK(clk), .RN(
n6944), .Q(FPSENCOS_d_ff2_Y[2]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_19_ ( .D(n1437), .CK(clk), .RN(
n6973), .Q(FPSENCOS_d_ff2_Y[19]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_3_ ( .D(n1469), .CK(clk), .RN(
n6974), .Q(FPSENCOS_d_ff2_Y[3]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_22_ ( .D(n1431), .CK(clk), .RN(
n6976), .Q(FPSENCOS_d_ff2_Y[22]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_1_ ( .D(n1473), .CK(clk), .RN(
n6949), .Q(FPSENCOS_d_ff2_Y[1]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_21_ ( .D(n1433), .CK(clk), .RN(
n6945), .Q(FPSENCOS_d_ff2_Y[21]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_6_ ( .D(n1463), .CK(clk), .RN(
n6975), .Q(FPSENCOS_d_ff2_Y[6]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_0_ ( .D(n1475), .CK(clk), .RN(
n6976), .Q(FPSENCOS_d_ff2_Y[0]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_25_ ( .D(n1848),
.CK(clk), .RN(n6943), .Q(FPADDSUB_Sgf_normalized_result[25]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_31_ ( .D(n1413), .CK(clk), .RN(
n6973), .Q(FPSENCOS_d_ff2_Y[31]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_31_ ( .D(n1478), .CK(clk), .RN(
n6963), .Q(FPSENCOS_d_ff2_Z[31]) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_2_ ( .D(n2057), .CK(clk), .RN(n6928),
.Q(FPMULT_FS_Module_state_reg[2]), .QN(n6659) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_5_ ( .D(n1923), .CK(clk),
.RN(n6927), .Q(FPMULT_P_Sgf[5]) );
DFFRX1TS FPSENCOS_reg_region_flag_Q_reg_0_ ( .D(n1831), .CK(clk), .RN(n6964),
.Q(FPSENCOS_d_ff1_shift_region_flag_out[0]), .QN(n2198) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_17_ ( .D(n1935), .CK(clk),
.RN(n6926), .Q(FPMULT_P_Sgf[17]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_20_ ( .D(n1938), .CK(clk),
.RN(n6925), .Q(FPMULT_P_Sgf[20]) );
DFFRX1TS reg_dataB_Q_reg_30_ ( .D(Data_2[30]), .CK(clk), .RN(n6915), .Q(
dataB[30]) );
DFFRX1TS reg_dataA_Q_reg_30_ ( .D(Data_1[30]), .CK(clk), .RN(n6912), .Q(
dataA[30]) );
DFFRX1TS reg_dataA_Q_reg_29_ ( .D(Data_1[29]), .CK(clk), .RN(n6912), .Q(
dataA[29]) );
DFFRX1TS reg_dataB_Q_reg_25_ ( .D(Data_2[25]), .CK(clk), .RN(n6914), .Q(
dataB[25]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_5_ ( .D(n1261), .CK(
clk), .RN(n6930), .Q(FPADDSUB_DmP[5]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_20_ ( .D(n1269), .CK(
clk), .RN(n6923), .Q(FPADDSUB_DmP[20]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_1_ ( .D(n1272), .CK(
clk), .RN(n6923), .Q(FPADDSUB_DmP[1]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_21_ ( .D(n1285), .CK(
clk), .RN(n6922), .Q(FPADDSUB_DmP[21]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_3_ ( .D(n1295), .CK(
clk), .RN(n6921), .Q(FPADDSUB_DmP[3]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_22_ ( .D(n1216), .CK(
clk), .RN(n6941), .Q(FPADDSUB_DMP[22]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_21_ ( .D(n1220), .CK(
clk), .RN(n6940), .Q(FPADDSUB_DMP[21]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_15_ ( .D(n1221), .CK(
clk), .RN(n6939), .Q(FPADDSUB_DMP[15]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_11_ ( .D(n1228), .CK(
clk), .RN(n6939), .Q(FPADDSUB_DMP[11]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_14_ ( .D(n1243), .CK(
clk), .RN(n6939), .Q(FPADDSUB_DMP[14]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_17_ ( .D(n1257), .CK(
clk), .RN(n6940), .Q(FPADDSUB_DMP[17]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_13_ ( .D(n1264), .CK(
clk), .RN(n6939), .Q(FPADDSUB_DMP[13]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_20_ ( .D(n1268), .CK(
clk), .RN(n6921), .Q(FPADDSUB_DMP[20]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_18_ ( .D(n1281), .CK(
clk), .RN(n6913), .Q(FPADDSUB_DMP[18]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_19_ ( .D(n1291), .CK(
clk), .RN(n6941), .Q(FPADDSUB_DMP[19]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_2_ ( .D(n1804), .CK(clk), .RN(n6966), .Q(
FPSENCOS_d_ff3_LUT_out[2]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_9_ ( .D(n1811), .CK(clk), .RN(n6966), .Q(
FPSENCOS_d_ff3_LUT_out[9]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_7_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[7]), .CK(clk),
.RN(n6920), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[33]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n2023), .CK(clk),
.RN(n6994), .Q(FPMULT_Op_MX[31]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_6_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[6]), .CK(clk),
.RN(n6919), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[32]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_3_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[3]), .CK(clk),
.RN(n6918), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[29]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_2_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[2]), .CK(clk),
.RN(n6918), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[28]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_4_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[4]), .CK(clk),
.RN(n6917), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[30]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_5_ ( .D(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[5]), .CK(clk),
.RN(n6917), .Q(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[31]) );
DFFRX1TS reg_dataB_Q_reg_27_ ( .D(Data_2[27]), .CK(clk), .RN(n6915), .Q(
dataB[27]) );
DFFRX1TS FPMULT_Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(n1965), .CK(clk),
.RN(n6992), .Q(FPMULT_FSM_add_overflow_flag) );
DFFRX2TS FPADDSUB_XRegister_Q_reg_24_ ( .D(n1311), .CK(clk), .RN(n6916), .Q(
FPADDSUB_intDX[24]) );
DFFRX2TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_0_ ( .D(n1663),
.CK(clk), .RN(n6941), .Q(FPADDSUB_Add_Subt_result[0]) );
DFFRX2TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_9_ ( .D(n1672),
.CK(clk), .RN(n6932), .Q(FPADDSUB_Add_Subt_result[9]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n1883), .CK(
clk), .RN(n6985), .Q(FPMULT_Sgf_normalized_result[1]) );
DFFRX1TS FPADDSUB_Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n1632),
.CK(clk), .RN(n6936), .Q(FPADDSUB_Sgf_normalized_result[0]) );
DFFSX2TS FPADDSUB_Add_Subt_Sgf_module_Add_overflow_Result_Q_reg_0_ ( .D(
n2836), .CK(clk), .SN(n6931), .QN(FPADDSUB_add_overflow_flag) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n2049), .CK(clk),
.RN(n6997), .Q(FPMULT_Op_MX[25]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n2054), .CK(clk),
.RN(n6997), .Q(FPMULT_Op_MX[30]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n2050), .CK(clk),
.RN(n6997), .Q(FPMULT_Op_MX[26]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n2052), .CK(clk),
.RN(n6997), .Q(FPMULT_Op_MX[28]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n2047), .CK(clk),
.RN(n6997), .Q(FPMULT_Op_MX[23]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(n1967), .CK(clk),
.RN(n6994), .Q(FPMULT_Add_result[22]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n1968), .CK(clk),
.RN(n6994), .Q(FPMULT_Add_result[21]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n1969), .CK(clk),
.RN(n6994), .Q(FPMULT_Add_result[20]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(n1970), .CK(clk),
.RN(n6994), .Q(FPMULT_Add_result[19]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n1971), .CK(clk),
.RN(n6994), .Q(FPMULT_Add_result[18]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n1972), .CK(clk),
.RN(n6994), .Q(FPMULT_Add_result[17]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n1973), .CK(clk),
.RN(n6994), .Q(FPMULT_Add_result[16]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n1974), .CK(clk),
.RN(n6994), .Q(FPMULT_Add_result[15]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n1975), .CK(clk),
.RN(n6993), .Q(FPMULT_Add_result[14]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n1976), .CK(clk),
.RN(n6993), .Q(FPMULT_Add_result[13]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n1977), .CK(clk),
.RN(n6993), .Q(FPMULT_Add_result[12]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n1986), .CK(clk), .RN(
n6992), .Q(FPMULT_Add_result[3]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n1988), .CK(clk), .RN(
n6992), .Q(FPMULT_Add_result[1]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(n1966), .CK(clk),
.RN(n6992), .Q(FPMULT_Add_result[23]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_1_ ( .D(n1913), .CK(clk), .RN(
n5022), .Q(FPMULT_exp_oper_result[1]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_4_ ( .D(n1910), .CK(clk), .RN(
n6989), .Q(FPMULT_exp_oper_result[4]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_6_ ( .D(n1908), .CK(clk), .RN(
n6991), .Q(FPMULT_exp_oper_result[6]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n2021), .CK(clk),
.RN(n6992), .Q(FPMULT_Op_MY[29]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n2020), .CK(clk),
.RN(n6992), .Q(FPMULT_Op_MY[28]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_25_ ( .D(n1943), .CK(clk),
.RN(n6929), .Q(FPMULT_P_Sgf[25]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n2016), .CK(clk),
.RN(n6985), .Q(FPMULT_Op_MY[24]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n2017), .CK(clk),
.RN(n6991), .Q(FPMULT_Op_MY[25]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n2018), .CK(clk),
.RN(n2215), .Q(FPMULT_Op_MY[26]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_31_ ( .D(n1842), .CK(clk), .RN(
n6972), .Q(FPSENCOS_d_ff2_X[31]) );
DFFRX1TS FPADDSUB_XRegister_Q_reg_31_ ( .D(n1332), .CK(clk), .RN(n6943), .Q(
FPADDSUB_intDX[31]) );
DFFRX1TS FPADDSUB_YRegister_Q_reg_31_ ( .D(n1333), .CK(clk), .RN(n6943), .Q(
FPADDSUB_intDY[31]) );
DFFSX1TS R_74 ( .D(n6857), .CK(clk), .SN(n6940), .Q(n7011) );
DFFSX1TS R_81 ( .D(n6856), .CK(clk), .SN(n6941), .Q(n7009) );
DFFRX1TS reg_dataA_Q_reg_27_ ( .D(Data_1[27]), .CK(clk), .RN(n6913), .Q(
dataA[27]) );
DFFRX1TS R_82 ( .D(n6855), .CK(clk), .RN(n6921), .Q(n7008) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_2_ ( .D(n1920), .CK(clk),
.RN(n6927), .Q(FPMULT_P_Sgf[2]) );
DFFRX1TS reg_dataB_Q_reg_28_ ( .D(Data_2[28]), .CK(clk), .RN(n6915), .Q(
dataB[28]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_18_ ( .D(n1936), .CK(clk),
.RN(n6925), .Q(FPMULT_P_Sgf[18]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_14_ ( .D(n1932), .CK(clk),
.RN(n6926), .Q(FPMULT_P_Sgf[14]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_4_ ( .D(n1922), .CK(clk),
.RN(n6927), .Q(FPMULT_P_Sgf[4]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_16_ ( .D(n1934), .CK(clk),
.RN(n6926), .Q(FPMULT_P_Sgf[16]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_3_ ( .D(n1921), .CK(clk),
.RN(n6927), .Q(FPMULT_P_Sgf[3]) );
DFFRX1TS FPSENCOS_reg_ch_mux_2_Q_reg_0_ ( .D(n1704), .CK(clk), .RN(n6972),
.Q(FPSENCOS_sel_mux_2_reg[0]), .QN(n6772) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_19_ ( .D(n1937), .CK(clk),
.RN(n6925), .Q(FPMULT_P_Sgf[19]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_15_ ( .D(n1933), .CK(clk),
.RN(n6926), .Q(FPMULT_P_Sgf[15]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_0_ ( .D(n1304), .CK(
clk), .RN(n6929), .Q(FPADDSUB_DmP[0]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_22_ ( .D(n1301), .CK(
clk), .RN(n6913), .Q(FPADDSUB_DmP[22]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_13_ ( .D(n1265), .CK(
clk), .RN(n6923), .Q(FPADDSUB_DmP[13]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_17_ ( .D(n1258), .CK(
clk), .RN(n6931), .Q(FPADDSUB_DmP[17]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_mRegister_Q_reg_9_ ( .D(n1230), .CK(
clk), .RN(n6925), .Q(FPADDSUB_DmP[9]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_30_ ( .D(n1327), .CK(
clk), .RN(n6936), .Q(FPADDSUB_DMP[30]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_29_ ( .D(n1324), .CK(
clk), .RN(n6935), .Q(FPADDSUB_DMP[29]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_28_ ( .D(n1321), .CK(
clk), .RN(n6935), .Q(FPADDSUB_DMP[28]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_27_ ( .D(n1318), .CK(
clk), .RN(n6935), .Q(FPADDSUB_DMP[27]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_26_ ( .D(n1315), .CK(
clk), .RN(n6935), .Q(FPADDSUB_DMP[26]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_25_ ( .D(n1312), .CK(
clk), .RN(n6935), .Q(FPADDSUB_DMP[25]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_24_ ( .D(n1309), .CK(
clk), .RN(n6934), .Q(FPADDSUB_DMP[24]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_23_ ( .D(n1306), .CK(
clk), .RN(n6934), .Q(FPADDSUB_DMP[23]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_16_ ( .D(n1250), .CK(
clk), .RN(n6940), .Q(FPADDSUB_DMP[16]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_12_ ( .D(n1233), .CK(
clk), .RN(n6939), .Q(FPADDSUB_DMP[12]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_9_ ( .D(n1229), .CK(
clk), .RN(n6938), .Q(FPADDSUB_DMP[9]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_7_ ( .D(n1227), .CK(
clk), .RN(n6938), .Q(FPADDSUB_DMP[7]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_10_ ( .D(n1226), .CK(
clk), .RN(n6938), .Q(FPADDSUB_DMP[10]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_4_ ( .D(n1225), .CK(
clk), .RN(n6937), .Q(FPADDSUB_DMP[4]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_5_ ( .D(n1224), .CK(
clk), .RN(n6937), .Q(FPADDSUB_DMP[5]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_1_ ( .D(n1223), .CK(
clk), .RN(n6937), .Q(FPADDSUB_DMP[1]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_8_ ( .D(n1222), .CK(
clk), .RN(n6938), .Q(FPADDSUB_DMP[8]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_2_ ( .D(n1219), .CK(
clk), .RN(n6937), .Q(FPADDSUB_DMP[2]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_3_ ( .D(n1218), .CK(
clk), .RN(n6937), .Q(FPADDSUB_DMP[3]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_6_ ( .D(n1217), .CK(
clk), .RN(n6938), .Q(FPADDSUB_DMP[6]) );
DFFRX1TS FPADDSUB_Oper_Start_in_module_MRegister_Q_reg_0_ ( .D(n1215), .CK(
clk), .RN(n6936), .Q(FPADDSUB_DMP[0]) );
DFFRX1TS FPSENCOS_reg_shift_y_Q_reg_23_ ( .D(n1421), .CK(clk), .RN(n6967),
.Q(FPSENCOS_d_ff3_sh_y_out[23]) );
DFFRX1TS FPSENCOS_d_ff5_Q_reg_31_ ( .D(n1348), .CK(clk), .RN(n6973), .Q(
FPSENCOS_data_output2_31_) );
DFFRX1TS reg_dataB_Q_reg_23_ ( .D(Data_2[23]), .CK(clk), .RN(n6914), .Q(
dataB[23]) );
DFFRX1TS reg_dataA_Q_reg_25_ ( .D(Data_1[25]), .CK(clk), .RN(n6942), .Q(
dataA[25]) );
DFFRX1TS reg_dataA_Q_reg_28_ ( .D(Data_1[28]), .CK(clk), .RN(n6912), .Q(
dataA[28]) );
DFFRX1TS reg_dataB_Q_reg_26_ ( .D(Data_2[26]), .CK(clk), .RN(n6915), .Q(
dataB[26]) );
DFFRX1TS FPSENCOS_reg_shift_x_Q_reg_23_ ( .D(n1792), .CK(clk), .RN(n6968),
.Q(FPSENCOS_d_ff3_sh_x_out[23]) );
DFFRX1TS reg_dataA_Q_reg_23_ ( .D(Data_1[23]), .CK(clk), .RN(n6942), .Q(
dataA[23]) );
DFFRX1TS reg_dataB_Q_reg_24_ ( .D(Data_2[24]), .CK(clk), .RN(n6914), .Q(
dataB[24]) );
DFFRX1TS FPSENCOS_reg_sign_Q_reg_0_ ( .D(n1477), .CK(clk), .RN(n6963), .Q(
FPSENCOS_d_ff3_sign_out) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_10_ ( .D(n1928), .CK(clk),
.RN(n6926), .Q(FPMULT_P_Sgf[10]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_13_ ( .D(n1931), .CK(clk),
.RN(n6926), .Q(FPMULT_P_Sgf[13]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_6_ ( .D(n1924), .CK(clk),
.RN(n6927), .Q(FPMULT_P_Sgf[6]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_11_ ( .D(n1929), .CK(clk),
.RN(n6926), .Q(FPMULT_P_Sgf[11]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_8_ ( .D(n1926), .CK(clk),
.RN(n6927), .Q(FPMULT_P_Sgf[8]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_12_ ( .D(n1930), .CK(clk),
.RN(n6926), .Q(FPMULT_P_Sgf[12]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_7_ ( .D(n1925), .CK(clk),
.RN(n6927), .Q(FPMULT_P_Sgf[7]) );
DFFRX2TS FPSENCOS_cont_iter_count_reg_0_ ( .D(n1834), .CK(clk), .RN(n6973),
.Q(FPSENCOS_cont_iter_out[0]), .QN(n6713) );
DFFSRHQX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_2_ ( .D(n1994), .CK(
clk), .SN(1'b1), .RN(n2216), .Q(FPMULT_Op_MY[2]) );
DFFSRHQX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_4_ ( .D(n2028), .CK(
clk), .SN(1'b1), .RN(n6995), .Q(FPMULT_Op_MX[4]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_20_ ( .D(n2044), .CK(clk),
.RN(n6991), .Q(FPMULT_Op_MX[20]), .QN(n2805) );
DFFRXLTS R_1 ( .D(n1905), .CK(clk), .RN(n6988), .Q(n6906) );
DFFSX1TS R_2 ( .D(n6911), .CK(clk), .SN(n6990), .Q(n6905) );
DFFSX1TS R_0 ( .D(FPMULT_Exp_module_Overflow_A), .CK(clk), .SN(n6988), .Q(
n6907) );
DFFRXLTS R_3 ( .D(n1906), .CK(clk), .RN(n6989), .Q(n6904) );
DFFRXLTS R_5 ( .D(n6999), .CK(clk), .RN(n6990), .Q(n6903) );
DFFRXLTS R_7 ( .D(n1953), .CK(clk), .RN(n2286), .Q(n6901) );
DFFRXLTS R_10 ( .D(n1954), .CK(clk), .RN(n2288), .Q(n6899) );
DFFSX1TS R_14 ( .D(n6910), .CK(clk), .SN(n5030), .Q(n6896) );
DFFRXLTS R_15 ( .D(n1917), .CK(clk), .RN(n6929), .Q(n6895) );
DFFRXLTS R_19 ( .D(n1958), .CK(clk), .RN(n5030), .Q(n6891) );
DFFRXLTS R_22 ( .D(n1963), .CK(clk), .RN(n6924), .Q(n6889) );
DFFRXLTS R_25 ( .D(n1962), .CK(clk), .RN(n6924), .Q(n6887) );
DFFRXLTS R_28 ( .D(n1960), .CK(clk), .RN(n6928), .Q(n6885) );
DFFRXLTS R_31 ( .D(n1961), .CK(clk), .RN(n6928), .Q(n6883) );
DFFRXLTS R_34 ( .D(n1959), .CK(clk), .RN(n5030), .Q(n6881) );
DFFRXLTS R_40 ( .D(n1952), .CK(clk), .RN(n2286), .Q(n6877) );
DFFRXLTS R_43 ( .D(n1950), .CK(clk), .RN(n2286), .Q(n6875) );
DFFRXLTS R_46 ( .D(n1956), .CK(clk), .RN(n2287), .Q(n6873) );
DFFRXLTS R_49 ( .D(n1955), .CK(clk), .RN(n2288), .Q(n6871) );
DFFRX1TS R_52 ( .D(n1686), .CK(clk), .RN(n6933), .Q(
FPADDSUB_Add_Subt_result[23]) );
DFFRX1TS R_51 ( .D(n1685), .CK(clk), .RN(n2217), .Q(
FPADDSUB_Add_Subt_result[22]) );
DFFRX1TS R_55 ( .D(n1687), .CK(clk), .RN(n6933), .Q(
FPADDSUB_Add_Subt_result[24]) );
DFFRX1TS R_54 ( .D(n1662), .CK(clk), .RN(n6913), .Q(
FPADDSUB_Add_Subt_result[25]) );
DFFSX1TS R_56 ( .D(n6869), .CK(clk), .SN(n6921), .Q(n7004) );
DFFRXLTS R_58 ( .D(n1845), .CK(clk), .RN(n5030), .Q(n6867) );
DFFRXLTS R_64 ( .D(n1951), .CK(clk), .RN(n2286), .Q(n6862) );
DFFSX1TS R_67 ( .D(n7000), .CK(clk), .SN(n6985), .Q(n6861) );
DFFSX1TS R_68 ( .D(n7012), .CK(clk), .SN(n2216), .Q(n6860) );
DFFSX1TS R_69 ( .D(n7005), .CK(clk), .SN(n6988), .Q(n6859) );
DFFSX1TS R_73 ( .D(n6858), .CK(clk), .SN(n6912), .Q(n7010) );
DFFSX1TS R_85 ( .D(FPMULT_Exp_module_Data_S[8]), .CK(clk), .SN(n6985), .Q(
n6854) );
DFFRX1TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_17_ ( .D(n1680),
.CK(clk), .RN(n6932), .Q(FPADDSUB_Add_Subt_result[17]), .QN(n6774) );
DFFRX1TS FPMULT_Sel_C_Q_reg_0_ ( .D(n2055), .CK(clk), .RN(n6996), .Q(
FPMULT_FSM_selector_C), .QN(n6763) );
DFFRX1TS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(
n1607), .CK(clk), .RN(n6917), .Q(result_add_subt[24]), .QN(n6704) );
DFFRX1TS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(
n1615), .CK(clk), .RN(n6917), .Q(result_add_subt[26]), .QN(n6702) );
DFFRX1TS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(
n1619), .CK(clk), .RN(n6916), .Q(result_add_subt[27]), .QN(n6701) );
DFFRX1TS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(
n1623), .CK(clk), .RN(n6916), .Q(result_add_subt[28]), .QN(n6700) );
DFFRX1TS FPADDSUB_final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(
n1627), .CK(clk), .RN(n6916), .Q(result_add_subt[29]), .QN(n6699) );
DFFRX1TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_18_ ( .D(n1681),
.CK(clk), .RN(n2218), .Q(FPADDSUB_Add_Subt_result[18]), .QN(n6674) );
DFFRX2TS FPADDSUB_FS_Module_state_reg_reg_1_ ( .D(n1839), .CK(clk), .RN(
n6915), .Q(FPADDSUB_FS_Module_state_reg[1]) );
DFFRXLTS FPMULT_Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n1991), .CK(
clk), .RN(n6984), .Q(FPMULT_zero_flag), .QN(n6852) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n1887), .CK(
clk), .RN(n6990), .Q(FPMULT_Sgf_normalized_result[5]), .QN(n6733) );
DFFSX1TS R_53 ( .D(n6870), .CK(clk), .SN(n2218), .Q(n7003), .QN(n6853) );
DFFRHQX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_27_ ( .D(n1945), .CK(
clk), .RN(n6942), .Q(FPMULT_P_Sgf[27]) );
DFFSRHQX2TS FPADDSUB_Leading_Zero_Detector_Module_Output_Reg_Q_reg_1_ ( .D(
n1660), .CK(clk), .SN(1'b1), .RN(n7006), .Q(FPADDSUB_LZA_output[1]) );
DFFSRHQX2TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_22_ ( .D(n1940), .CK(
clk), .SN(1'b1), .RN(n2218), .Q(FPMULT_P_Sgf[22]) );
DFFSRHQX2TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_21_ ( .D(n1939), .CK(
clk), .SN(1'b1), .RN(n6943), .Q(FPMULT_P_Sgf[21]) );
DFFSRHQX2TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_24_ ( .D(n1942), .CK(
clk), .SN(1'b1), .RN(n7006), .Q(FPMULT_P_Sgf[24]) );
DFFSRHQX2TS FPADDSUB_Leading_Zero_Detector_Module_Output_Reg_Q_reg_2_ ( .D(
n1659), .CK(clk), .SN(1'b1), .RN(n2217), .Q(FPADDSUB_LZA_output[2]) );
DFFSRHQX2TS FPADDSUB_Leading_Zero_Detector_Module_Output_Reg_Q_reg_0_ ( .D(
n1661), .CK(clk), .SN(1'b1), .RN(n2287), .Q(FPADDSUB_LZA_output[0]) );
DFFSRHQX2TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_29_ ( .D(n1947), .CK(
clk), .SN(1'b1), .RN(n5028), .Q(FPMULT_P_Sgf[29]) );
DFFSRHQX2TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_28_ ( .D(n1946), .CK(
clk), .SN(1'b1), .RN(n7006), .Q(FPMULT_P_Sgf[28]) );
DFFSRHQX2TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_26_ ( .D(n1944), .CK(
clk), .SN(1'b1), .RN(n2226), .Q(FPMULT_P_Sgf[26]) );
DFFSRHQX2TS FPADDSUB_Leading_Zero_Detector_Module_Output_Reg_Q_reg_3_ ( .D(
n1658), .CK(clk), .SN(1'b1), .RN(n6930), .Q(FPADDSUB_LZA_output[3]) );
DFFSRHQX2TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_30_ ( .D(n1948), .CK(
clk), .SN(1'b1), .RN(n7006), .Q(FPMULT_P_Sgf[30]) );
DFFRXLTS R_59 ( .D(n7001), .CK(clk), .RN(n6928), .Q(n6866) );
DFFSHQX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_15_ ( .D(n2796), .CK(
clk), .SN(n7007), .Q(n6909) );
DFFRX2TS FPADDSUB_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_4_ ( .D(n1667),
.CK(clk), .RN(n2217), .Q(FPADDSUB_Add_Subt_result[4]) );
DFFRX1TS FPADDSUB_Exp_Operation_Module_exp_result_Q_reg_2_ ( .D(n1693), .CK(
clk), .RN(n6933), .Q(FPADDSUB_exp_oper_result[2]) );
DFFRX1TS FPADDSUB_Leading_Zero_Detector_Module_Output_Reg_Q_reg_4_ ( .D(
n1657), .CK(clk), .RN(n6934), .Q(FPADDSUB_LZA_output[4]) );
DFFSRHQX8TS FPMULT_Operands_load_reg_YMRegister_Q_reg_13_ ( .D(n2005), .CK(
clk), .SN(1'b1), .RN(n6985), .Q(FPMULT_Op_MY[13]) );
DFFSX2TS R_86 ( .D(n4922), .CK(clk), .SN(n2287), .Q(n2143) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n1891), .CK(
clk), .RN(n2215), .Q(FPMULT_Sgf_normalized_result[9]), .QN(n6732) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_9_ ( .D(n1927), .CK(clk),
.RN(n6927), .Q(FPMULT_P_Sgf[9]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_27_ ( .D(n1617), .CK(clk), .RN(n6980), .Q(
FPSENCOS_d_ff_Yn[27]), .QN(n6830) );
XOR2X1TS U2215 ( .A(n4771), .B(n4770), .Y(FPMULT_Sgf_operation_Result[32])
);
XOR2X2TS U2216 ( .A(n4822), .B(n4821), .Y(FPMULT_Sgf_operation_Result[33])
);
INVX2TS U2217 ( .A(n6472), .Y(n6581) );
INVX2TS U2218 ( .A(n2881), .Y(n2213) );
INVX2TS U2219 ( .A(n6396), .Y(n6398) );
INVX2TS U2220 ( .A(n6396), .Y(n6400) );
INVX2TS U2221 ( .A(n2304), .Y(n6208) );
CLKBUFX2TS U2222 ( .A(n5870), .Y(n6564) );
INVX2TS U2223 ( .A(n6550), .Y(n6553) );
INVX2TS U2224 ( .A(n6550), .Y(n6548) );
INVX2TS U2225 ( .A(n5743), .Y(n5746) );
CLKMX2X2TS U2226 ( .A(FPADDSUB_Add_Subt_result[24]), .B(n4901), .S0(n5969),
.Y(n1687) );
AOI21X2TS U2227 ( .A0(n2669), .A1(n4818), .B0(n4817), .Y(n4822) );
AOI21X2TS U2228 ( .A0(n2669), .A1(n4811), .B0(n4768), .Y(n4771) );
AOI222X1TS U2229 ( .A0(n6613), .A1(FPSENCOS_d_ff2_Z[0]), .B0(n5458), .B1(
FPSENCOS_d_ff1_Z[0]), .C0(FPSENCOS_d_ff_Zn[0]), .C1(n6494), .Y(n5430)
);
XOR2X1TS U2230 ( .A(n4941), .B(n4940), .Y(n4942) );
AOI222X1TS U2231 ( .A0(n5428), .A1(FPSENCOS_d_ff2_Z[9]), .B0(n5456), .B1(
FPSENCOS_d_ff1_Z[9]), .C0(FPSENCOS_d_ff_Zn[9]), .C1(n5455), .Y(n5457)
);
AOI222X1TS U2232 ( .A0(n5453), .A1(FPSENCOS_d_ff2_Z[12]), .B0(n5452), .B1(
FPSENCOS_d_ff1_Z[12]), .C0(FPSENCOS_d_ff_Zn[12]), .C1(n5451), .Y(n5450) );
AOI222X1TS U2233 ( .A0(n5453), .A1(FPSENCOS_d_ff2_Z[11]), .B0(n5456), .B1(
FPSENCOS_d_ff1_Z[11]), .C0(FPSENCOS_d_ff_Zn[11]), .C1(n5451), .Y(n5449) );
AOI222X1TS U2234 ( .A0(n6588), .A1(FPSENCOS_d_ff2_Z[7]), .B0(n5456), .B1(
FPSENCOS_d_ff1_Z[7]), .C0(FPSENCOS_d_ff_Zn[7]), .C1(n5455), .Y(n5446)
);
AOI222X1TS U2235 ( .A0(n5453), .A1(FPSENCOS_d_ff2_Z[14]), .B0(n5452), .B1(
FPSENCOS_d_ff1_Z[14]), .C0(FPSENCOS_d_ff_Zn[14]), .C1(n5451), .Y(n5454) );
AOI222X1TS U2236 ( .A0(n5428), .A1(FPSENCOS_d_ff2_Z[10]), .B0(n5456), .B1(
FPSENCOS_d_ff1_Z[10]), .C0(FPSENCOS_d_ff_Zn[10]), .C1(n5455), .Y(n5447) );
AOI222X1TS U2237 ( .A0(n5453), .A1(FPSENCOS_d_ff2_Z[16]), .B0(n5452), .B1(
FPSENCOS_d_ff1_Z[16]), .C0(FPSENCOS_d_ff_Zn[16]), .C1(n5451), .Y(n5448) );
AOI222X1TS U2238 ( .A0(n6588), .A1(FPSENCOS_d_ff2_Z[4]), .B0(n5456), .B1(
FPSENCOS_d_ff1_Z[4]), .C0(FPSENCOS_d_ff_Zn[4]), .C1(n5455), .Y(n5444)
);
AOI222X1TS U2239 ( .A0(n5453), .A1(FPSENCOS_d_ff2_Z[17]), .B0(n5452), .B1(
FPSENCOS_d_ff1_Z[17]), .C0(FPSENCOS_d_ff_Zn[17]), .C1(n5451), .Y(n5441) );
AOI222X1TS U2240 ( .A0(n5428), .A1(FPSENCOS_d_ff2_Z[5]), .B0(n5456), .B1(
FPSENCOS_d_ff1_Z[5]), .C0(FPSENCOS_d_ff_Zn[5]), .C1(n5455), .Y(n5439)
);
AOI222X1TS U2241 ( .A0(n5453), .A1(FPSENCOS_d_ff2_Z[13]), .B0(n5452), .B1(
FPSENCOS_d_ff1_Z[13]), .C0(FPSENCOS_d_ff_Zn[13]), .C1(n5451), .Y(n5434) );
AOI222X1TS U2242 ( .A0(n5453), .A1(FPSENCOS_d_ff2_Z[20]), .B0(n5452), .B1(
FPSENCOS_d_ff1_Z[20]), .C0(FPSENCOS_d_ff_Zn[20]), .C1(n5451), .Y(n5443) );
AOI222X1TS U2243 ( .A0(n5428), .A1(FPSENCOS_d_ff2_Z[8]), .B0(n5456), .B1(
FPSENCOS_d_ff1_Z[8]), .C0(FPSENCOS_d_ff_Zn[8]), .C1(n5455), .Y(n5432)
);
AOI222X1TS U2244 ( .A0(n5453), .A1(FPSENCOS_d_ff2_Z[15]), .B0(n5452), .B1(
FPSENCOS_d_ff1_Z[15]), .C0(FPSENCOS_d_ff_Zn[15]), .C1(n5451), .Y(n5437) );
AOI222X1TS U2245 ( .A0(n5453), .A1(FPSENCOS_d_ff2_Z[18]), .B0(n5452), .B1(
FPSENCOS_d_ff1_Z[18]), .C0(FPSENCOS_d_ff_Zn[18]), .C1(n5451), .Y(n5435) );
AOI222X1TS U2246 ( .A0(n5468), .A1(FPSENCOS_d_ff2_Z[21]), .B0(n5452), .B1(
FPSENCOS_d_ff1_Z[21]), .C0(FPSENCOS_d_ff_Zn[21]), .C1(n5467), .Y(n5436) );
AOI222X1TS U2247 ( .A0(n5428), .A1(FPSENCOS_d_ff2_Z[2]), .B0(n5456), .B1(
FPSENCOS_d_ff1_Z[2]), .C0(FPSENCOS_d_ff_Zn[2]), .C1(n5455), .Y(n5440)
);
AOI222X1TS U2248 ( .A0(n5453), .A1(FPSENCOS_d_ff2_Z[19]), .B0(n5452), .B1(
FPSENCOS_d_ff1_Z[19]), .C0(FPSENCOS_d_ff_Zn[19]), .C1(n5451), .Y(n5445) );
AOI222X1TS U2249 ( .A0(n5428), .A1(FPSENCOS_d_ff2_Z[3]), .B0(n5456), .B1(
FPSENCOS_d_ff1_Z[3]), .C0(FPSENCOS_d_ff_Zn[3]), .C1(n5455), .Y(n5442)
);
AOI222X1TS U2250 ( .A0(n5428), .A1(FPSENCOS_d_ff2_Z[6]), .B0(n5456), .B1(
FPSENCOS_d_ff1_Z[6]), .C0(FPSENCOS_d_ff_Zn[6]), .C1(n5455), .Y(n5438)
);
AOI222X1TS U2251 ( .A0(n5468), .A1(FPSENCOS_d_ff2_Z[27]), .B0(n5871), .B1(
FPSENCOS_d_ff1_Z[27]), .C0(FPSENCOS_d_ff_Zn[27]), .C1(n5467), .Y(n5462) );
AOI222X1TS U2252 ( .A0(n5468), .A1(FPSENCOS_d_ff2_Z[29]), .B0(n5871), .B1(
FPSENCOS_d_ff1_Z[29]), .C0(FPSENCOS_d_ff_Zn[29]), .C1(n5467), .Y(n5466) );
AOI222X1TS U2253 ( .A0(n5468), .A1(FPSENCOS_d_ff2_Z[30]), .B0(n5871), .B1(
FPSENCOS_d_ff1_Z[30]), .C0(FPSENCOS_d_ff_Zn[30]), .C1(n5467), .Y(n5469) );
AOI222X1TS U2254 ( .A0(n5468), .A1(FPSENCOS_d_ff2_Z[22]), .B0(n5871), .B1(
FPSENCOS_d_ff1_Z[22]), .C0(FPSENCOS_d_ff_Zn[22]), .C1(n5467), .Y(n5463) );
AOI222X1TS U2255 ( .A0(n5468), .A1(FPSENCOS_d_ff2_Z[25]), .B0(n5871), .B1(
FPSENCOS_d_ff1_Z[25]), .C0(FPSENCOS_d_ff_Zn[25]), .C1(n5467), .Y(n5464) );
AOI222X1TS U2256 ( .A0(n5468), .A1(FPSENCOS_d_ff2_Z[26]), .B0(n5871), .B1(
FPSENCOS_d_ff1_Z[26]), .C0(FPSENCOS_d_ff_Zn[26]), .C1(n5467), .Y(n5460) );
AOI222X1TS U2257 ( .A0(n5468), .A1(FPSENCOS_d_ff2_Z[28]), .B0(n5871), .B1(
FPSENCOS_d_ff1_Z[28]), .C0(FPSENCOS_d_ff_Zn[28]), .C1(n5467), .Y(n5465) );
AOI222X1TS U2258 ( .A0(n5468), .A1(FPSENCOS_d_ff2_Z[24]), .B0(n5871), .B1(
FPSENCOS_d_ff1_Z[24]), .C0(FPSENCOS_d_ff_Zn[24]), .C1(n5467), .Y(n5459) );
AOI222X1TS U2259 ( .A0(n5468), .A1(FPSENCOS_d_ff2_Z[23]), .B0(n5871), .B1(
FPSENCOS_d_ff1_Z[23]), .C0(FPSENCOS_d_ff_Zn[23]), .C1(n5467), .Y(n5461) );
BUFX3TS U2260 ( .A(n5979), .Y(n5969) );
INVX2TS U2261 ( .A(n5870), .Y(n5451) );
INVX2TS U2262 ( .A(n5870), .Y(n5467) );
INVX2TS U2263 ( .A(n6593), .Y(n5455) );
NOR2X4TS U2264 ( .A(n5416), .B(FPADDSUB_FS_Module_state_reg[3]), .Y(n5979)
);
BUFX8TS U2265 ( .A(n2713), .Y(n2669) );
INVX6TS U2266 ( .A(n2506), .Y(n4808) );
BUFX3TS U2267 ( .A(n4922), .Y(n6910) );
BUFX3TS U2268 ( .A(n6558), .Y(n6464) );
INVX2TS U2269 ( .A(n6413), .Y(n6618) );
BUFX3TS U2270 ( .A(n6504), .Y(n6499) );
BUFX3TS U2271 ( .A(n6625), .Y(n6624) );
AND2X4TS U2272 ( .A(n2505), .B(n2472), .Y(n2190) );
CLKBUFX2TS U2273 ( .A(n6394), .Y(n6396) );
BUFX3TS U2274 ( .A(n6558), .Y(n6472) );
NAND2X1TS U2275 ( .A(n4959), .B(n4958), .Y(n4960) );
CLKBUFX2TS U2276 ( .A(n5743), .Y(n5726) );
AOI21X1TS U2277 ( .A0(n4938), .A1(n4937), .B0(n4936), .Y(n4941) );
BUFX3TS U2278 ( .A(n6528), .Y(n6550) );
BUFX3TS U2279 ( .A(n5174), .Y(n5179) );
BUFX3TS U2280 ( .A(n5174), .Y(n5188) );
INVX2TS U2281 ( .A(n2610), .Y(n4804) );
CLKBUFX2TS U2282 ( .A(n5018), .Y(n5922) );
INVX2TS U2283 ( .A(n5873), .Y(n5371) );
CLKBUFX2TS U2284 ( .A(n5431), .Y(n5458) );
INVX3TS U2285 ( .A(n4923), .Y(n4952) );
INVX1TS U2286 ( .A(n4935), .Y(n4936) );
BUFX6TS U2287 ( .A(n5921), .Y(n2312) );
CLKBUFX2TS U2288 ( .A(n5098), .Y(n6631) );
INVX12TS U2289 ( .A(n2505), .Y(n2506) );
BUFX3TS U2290 ( .A(n5433), .Y(n6593) );
CLKINVX1TS U2291 ( .A(n2157), .Y(n4953) );
BUFX3TS U2292 ( .A(n5433), .Y(n5870) );
BUFX3TS U2293 ( .A(n2825), .Y(n5749) );
BUFX3TS U2294 ( .A(n6616), .Y(n6558) );
OR4X2TS U2295 ( .A(n6401), .B(n1905), .C(n1906), .D(n6403), .Y(n6394) );
OR2X2TS U2296 ( .A(n5132), .B(operation[2]), .Y(n5133) );
BUFX3TS U2297 ( .A(n5174), .Y(n5298) );
CMPR32X2TS U2298 ( .A(FPSENCOS_d_ff2_Y[26]), .B(n6711), .C(n6601), .CO(n6605), .S(n6603) );
NAND2X1TS U2299 ( .A(FPSENCOS_cont_iter_out[3]), .B(n5483), .Y(n6435) );
BUFX3TS U2300 ( .A(n4911), .Y(n5921) );
INVX4TS U2301 ( .A(n5778), .Y(n2141) );
OR3X2TS U2302 ( .A(FPSENCOS_cordic_FSM_state_reg[1]), .B(
FPSENCOS_cordic_FSM_state_reg[0]), .C(n5243), .Y(n6626) );
NAND2X1TS U2303 ( .A(n2880), .B(n2879), .Y(n2881) );
NAND2X4TS U2304 ( .A(n5685), .B(n2142), .Y(n2825) );
INVX2TS U2305 ( .A(n6592), .Y(n5428) );
OR2X2TS U2306 ( .A(n5102), .B(n5426), .Y(n6504) );
INVX2TS U2307 ( .A(n5104), .Y(n5222) );
BUFX3TS U2308 ( .A(n2831), .Y(n6616) );
OR2X2TS U2309 ( .A(n5685), .B(n5765), .Y(n5706) );
CMPR32X2TS U2310 ( .A(FPSENCOS_d_ff2_Y[25]), .B(n5483), .C(n5048), .CO(n6601), .S(n5049) );
CMPR32X2TS U2311 ( .A(FPSENCOS_d_ff2_X[25]), .B(n5483), .C(n5046), .CO(n6455), .S(n5043) );
OR4X4TS U2312 ( .A(n6670), .B(n6660), .C(FPSENCOS_cordic_FSM_state_reg[1]),
.D(FPSENCOS_cordic_FSM_state_reg[3]), .Y(n2831) );
NAND2X1TS U2313 ( .A(n4849), .B(FPMULT_FS_Module_state_reg[0]), .Y(n5778) );
CLKBUFX2TS U2314 ( .A(n5264), .Y(n5277) );
INVX2TS U2315 ( .A(n2833), .Y(n6534) );
NOR2X1TS U2316 ( .A(n5537), .B(n5533), .Y(n4911) );
NOR2X1TS U2317 ( .A(n5102), .B(n5780), .Y(n5104) );
NOR2X1TS U2318 ( .A(n5069), .B(n5050), .Y(n6412) );
BUFX3TS U2319 ( .A(n2279), .Y(n6613) );
INVX2TS U2320 ( .A(n4782), .Y(n4797) );
INVX4TS U2321 ( .A(n5117), .Y(n5410) );
CLKBUFX2TS U2322 ( .A(n6393), .Y(n6397) );
CMPR32X2TS U2323 ( .A(n2860), .B(n2859), .C(n2858), .CO(n2855), .S(n5930) );
NAND2X1TS U2324 ( .A(n6670), .B(FPSENCOS_cordic_FSM_state_reg[1]), .Y(n5102)
);
NAND2X1TS U2325 ( .A(FPSENCOS_cordic_FSM_state_reg[0]), .B(
FPSENCOS_cordic_FSM_state_reg[3]), .Y(n5780) );
AO22X2TS U2326 ( .A0(FPADDSUB_LZA_output[2]), .A1(n5248), .B0(
FPADDSUB_exp_oper_result[2]), .B1(n5247), .Y(n5264) );
AO21X1TS U2327 ( .A0(n5808), .A1(n5807), .B0(n6662), .Y(n6108) );
AND2X2TS U2328 ( .A(n4852), .B(FPMULT_FS_Module_state_reg[3]), .Y(n6393) );
INVX2TS U2329 ( .A(n5577), .Y(n5537) );
INVX2TS U2330 ( .A(n6410), .Y(n5050) );
NOR2X1TS U2331 ( .A(n6349), .B(n5007), .Y(n5009) );
NAND2X1TS U2332 ( .A(n5132), .B(operation[2]), .Y(n4850) );
OR2X2TS U2333 ( .A(n5060), .B(n5059), .Y(n2833) );
INVX4TS U2334 ( .A(n5754), .Y(n2142) );
AND2X2TS U2335 ( .A(n5132), .B(n6355), .Y(n4962) );
OAI2BB2XLTS U2336 ( .B0(FPADDSUB_intDY[22]), .B1(n5672), .A0N(
FPADDSUB_intDX[23]), .A1N(n6762), .Y(n5673) );
NOR2X1TS U2337 ( .A(n2884), .B(FPMULT_FS_Module_state_reg[3]), .Y(n4849) );
NOR2X6TS U2338 ( .A(n4823), .B(n4825), .Y(n4811) );
NOR2X4TS U2339 ( .A(n5484), .B(n6428), .Y(n6410) );
CLKXOR2X2TS U2340 ( .A(n4354), .B(n4353), .Y(n4355) );
NAND2X2TS U2341 ( .A(n5005), .B(n5422), .Y(n5754) );
NOR3XLTS U2342 ( .A(FPSENCOS_sel_mux_2_reg[0]), .B(n6637), .C(n5132), .Y(
n5116) );
CLKINVX6TS U2343 ( .A(n2565), .Y(n2613) );
BUFX3TS U2344 ( .A(n5558), .Y(n5573) );
NAND2X4TS U2345 ( .A(n2528), .B(n4296), .Y(n2740) );
NAND2X1TS U2346 ( .A(n6442), .B(FPSENCOS_cont_iter_out[3]), .Y(n6428) );
INVX2TS U2347 ( .A(n5393), .Y(n5422) );
NAND2X2TS U2348 ( .A(n2239), .B(FPSENCOS_cont_iter_out[0]), .Y(n5484) );
INVX4TS U2349 ( .A(n4772), .Y(n4799) );
INVX2TS U2350 ( .A(operation[1]), .Y(n5132) );
OA22X1TS U2351 ( .A0(n6668), .A1(FPADDSUB_intDX[22]), .B0(n6762), .B1(
FPADDSUB_intDX[23]), .Y(n5676) );
CMPR32X2TS U2352 ( .A(n2871), .B(n2870), .C(n2869), .CO(n2864), .S(n5932) );
NOR2X1TS U2353 ( .A(n6760), .B(FPADDSUB_intDX[29]), .Y(n5625) );
NOR2X1TS U2354 ( .A(FPMULT_FS_Module_state_reg[1]), .B(
FPMULT_FS_Module_state_reg[2]), .Y(n5053) );
INVX6TS U2355 ( .A(n2636), .Y(n2635) );
BUFX3TS U2356 ( .A(FPSENCOS_cont_iter_out[2]), .Y(n6442) );
NAND2X2TS U2357 ( .A(n6660), .B(n6667), .Y(n5426) );
BUFX3TS U2358 ( .A(n5013), .Y(n2323) );
INVX2TS U2359 ( .A(n2238), .Y(n2239) );
NAND2X1TS U2360 ( .A(n4907), .B(n4912), .Y(n5558) );
NAND2X2TS U2361 ( .A(n4673), .B(n4672), .Y(n4939) );
NAND2X4TS U2362 ( .A(n2548), .B(n2566), .Y(n2565) );
AND2X4TS U2363 ( .A(n5097), .B(n5096), .Y(n2196) );
NAND2X1TS U2364 ( .A(FPADDSUB_FS_Module_state_reg[0]), .B(
FPADDSUB_FS_Module_state_reg[3]), .Y(n5059) );
OR2X6TS U2365 ( .A(n2486), .B(n2689), .Y(n2394) );
NAND2X1TS U2366 ( .A(n4728), .B(n4727), .Y(n4729) );
NOR2X4TS U2367 ( .A(n4673), .B(n4672), .Y(n4674) );
INVX4TS U2368 ( .A(n2699), .Y(n2657) );
BUFX3TS U2369 ( .A(n2840), .Y(n5247) );
NOR2X6TS U2370 ( .A(n2709), .B(n4655), .Y(n4929) );
NAND2X2TS U2371 ( .A(n2709), .B(n4655), .Y(n4930) );
NAND2X6TS U2372 ( .A(n2655), .B(n2697), .Y(n2636) );
INVX2TS U2373 ( .A(n4293), .Y(n2658) );
AOI21X1TS U2374 ( .A0(n4409), .A1(n4365), .B0(n4364), .Y(n4370) );
CLKXOR2X2TS U2375 ( .A(n4292), .B(n4291), .Y(n4752) );
INVX4TS U2376 ( .A(n5511), .Y(n5500) );
CLKXOR2X2TS U2377 ( .A(n4373), .B(n4372), .Y(n4777) );
NAND2X1TS U2378 ( .A(n4371), .B(n4377), .Y(n4372) );
INVX6TS U2379 ( .A(n2395), .Y(n2363) );
AND2X2TS U2380 ( .A(n2136), .B(n4706), .Y(n2798) );
NAND2X4TS U2381 ( .A(n6737), .B(n4908), .Y(n5511) );
INVX2TS U2382 ( .A(n4884), .Y(n4623) );
BUFX8TS U2383 ( .A(n2585), .Y(n2527) );
INVX4TS U2384 ( .A(n2392), .Y(n2484) );
NOR2X6TS U2385 ( .A(n4873), .B(n4875), .Y(n4882) );
NAND2X2TS U2386 ( .A(FPADDSUB_FS_Module_state_reg[3]), .B(n5411), .Y(n5616)
);
AOI21X1TS U2387 ( .A0(n4310), .A1(n4312), .B0(n4317), .Y(n4292) );
NOR2X2TS U2388 ( .A(n5807), .B(FPMULT_FS_Module_state_reg[1]), .Y(n5013) );
AOI21X1TS U2389 ( .A0(n4281), .A1(n4310), .B0(n4280), .Y(n4286) );
NAND2X1TS U2390 ( .A(n4333), .B(n4332), .Y(n4367) );
INVX6TS U2391 ( .A(n2585), .Y(n2520) );
CLKINVX6TS U2392 ( .A(n4228), .Y(n2545) );
INVX4TS U2393 ( .A(n4704), .Y(n2134) );
NOR2BX1TS U2394 ( .AN(n2834), .B(FPADDSUB_add_overflow_flag), .Y(n4908) );
NAND2X6TS U2395 ( .A(n2369), .B(n2370), .Y(n2395) );
NOR2X2TS U2396 ( .A(n4677), .B(n2504), .Y(n2753) );
NAND2X2TS U2397 ( .A(n4195), .B(n4652), .Y(n2501) );
NAND2X6TS U2398 ( .A(n2383), .B(n2382), .Y(n2392) );
NAND2X2TS U2399 ( .A(n2542), .B(n2136), .Y(n2539) );
NAND2X1TS U2400 ( .A(n6672), .B(n5804), .Y(n5807) );
NOR2X1TS U2401 ( .A(n5060), .B(n5270), .Y(n2834) );
CLKINVX1TS U2402 ( .A(n3538), .Y(n4340) );
OR2X2TS U2403 ( .A(n4526), .B(n4525), .Y(n2168) );
NOR2X2TS U2404 ( .A(n6659), .B(FPMULT_FS_Module_state_reg[3]), .Y(n5804) );
OR2X4TS U2405 ( .A(n4528), .B(n4527), .Y(n2794) );
INVX2TS U2406 ( .A(n6303), .Y(n4529) );
INVX2TS U2407 ( .A(n2485), .Y(n2382) );
INVX1TS U2408 ( .A(n4287), .Y(n2762) );
NOR2X2TS U2409 ( .A(n4378), .B(n4382), .Y(n4331) );
NAND2X2TS U2410 ( .A(n4293), .B(n4295), .Y(n2761) );
NAND2X2TS U2411 ( .A(n6512), .B(n6674), .Y(n5938) );
NOR2X1TS U2412 ( .A(n4324), .B(n4322), .Y(n4386) );
BUFX3TS U2413 ( .A(n2695), .Y(n4686) );
CLKBUFX2TS U2414 ( .A(n6716), .Y(n5270) );
NAND2X1TS U2415 ( .A(n4534), .B(n4533), .Y(n4536) );
INVX2TS U2416 ( .A(n4294), .Y(n4287) );
NOR2X6TS U2417 ( .A(n2353), .B(n4497), .Y(n6291) );
NAND2X1TS U2418 ( .A(n4327), .B(n4326), .Y(n4377) );
NAND2X1TS U2419 ( .A(n6038), .B(n2930), .Y(n6060) );
NAND2X6TS U2420 ( .A(n2510), .B(n2509), .Y(n2508) );
INVX2TS U2421 ( .A(n4734), .Y(n2485) );
NOR2X6TS U2422 ( .A(n4209), .B(n4210), .Y(n4705) );
INVX2TS U2423 ( .A(n4688), .Y(n2137) );
INVX2TS U2424 ( .A(n4677), .Y(n4687) );
NOR2X1TS U2425 ( .A(n4315), .B(n4311), .Y(n4318) );
NOR2X1TS U2426 ( .A(n5994), .B(n5996), .Y(n2908) );
NOR2X1TS U2427 ( .A(n6066), .B(n6068), .Y(n2940) );
NOR2X1TS U2428 ( .A(n5962), .B(n5974), .Y(n5988) );
INVX3TS U2429 ( .A(n2468), .Y(n2509) );
NAND2X2TS U2430 ( .A(n6737), .B(FPADDSUB_FS_Module_state_reg[0]), .Y(n5417)
);
OAI21X1TS U2431 ( .A0(n4638), .A1(n4628), .B0(n4635), .Y(n4593) );
NOR2X2TS U2432 ( .A(n4275), .B(n4276), .Y(n4299) );
INVX2TS U2433 ( .A(n4638), .Y(n4557) );
NOR2X2TS U2434 ( .A(n4282), .B(n4283), .Y(n4315) );
NOR2X1TS U2435 ( .A(n2900), .B(n2899), .Y(n5962) );
NAND2XLTS U2436 ( .A(n2823), .B(n2822), .Y(n4266) );
NOR2X1TS U2437 ( .A(n2926), .B(n2925), .Y(n6042) );
INVX6TS U2438 ( .A(n2426), .Y(n2422) );
NAND2X1TS U2439 ( .A(n4509), .B(n4508), .Y(n4511) );
CLKINVX6TS U2440 ( .A(n2504), .Y(n2135) );
NOR2X1TS U2441 ( .A(n2932), .B(n2931), .Y(n6074) );
NOR2X6TS U2442 ( .A(n2396), .B(n4688), .Y(n2424) );
NAND2X6TS U2443 ( .A(n4728), .B(n2621), .Y(n2620) );
OAI21X1TS U2444 ( .A0(n6173), .A1(n6727), .B0(n6101), .Y(n6145) );
NAND2X4TS U2445 ( .A(n4206), .B(n4205), .Y(n4688) );
NAND2X4TS U2446 ( .A(n4221), .B(n4222), .Y(n4727) );
NAND2X2TS U2447 ( .A(n4208), .B(n4207), .Y(n4679) );
CLKINVX6TS U2448 ( .A(n2622), .Y(n4728) );
XOR2X1TS U2449 ( .A(n2913), .B(n2911), .Y(n2922) );
XOR2X1TS U2450 ( .A(n2969), .B(n2916), .Y(n2932) );
NOR2X4TS U2451 ( .A(n4512), .B(n4515), .Y(n4550) );
XOR2X1TS U2452 ( .A(n2913), .B(n2897), .Y(n2904) );
XOR2X1TS U2453 ( .A(n2969), .B(n2919), .Y(n2936) );
OR2X6TS U2454 ( .A(n4201), .B(n4200), .Y(n4665) );
NAND2X4TS U2455 ( .A(n4220), .B(n4219), .Y(n4725) );
NOR2X2TS U2456 ( .A(n4452), .B(n4451), .Y(n4512) );
INVX4TS U2457 ( .A(n4204), .Y(n2632) );
NOR2X2TS U2458 ( .A(n4549), .B(n4552), .Y(n4555) );
INVX4TS U2459 ( .A(n4652), .Y(n2757) );
AOI21X2TS U2460 ( .A0(n4592), .A1(n4591), .B0(n4590), .Y(n4635) );
INVX4TS U2461 ( .A(n2989), .Y(n2988) );
CMPR32X2TS U2462 ( .A(n3600), .B(n3599), .C(n3598), .CO(n3622), .S(n3601) );
NOR2X6TS U2463 ( .A(n4202), .B(n4203), .Y(n4204) );
NAND2X2TS U2464 ( .A(n4517), .B(n4516), .Y(n4553) );
NAND2X4TS U2465 ( .A(n2119), .B(n4601), .Y(n4175) );
NAND2X2TS U2466 ( .A(n4587), .B(n4592), .Y(n4628) );
AND2X6TS U2467 ( .A(n4173), .B(n4172), .Y(n2146) );
NOR2X4TS U2468 ( .A(n4415), .B(n4445), .Y(n4474) );
OAI2BB1X2TS U2469 ( .A0N(n3544), .A1N(n3543), .B0(n2576), .Y(n3593) );
OR2X2TS U2470 ( .A(n4581), .B(n4580), .Y(n4592) );
NAND2X1TS U2471 ( .A(n4253), .B(n4252), .Y(n4689) );
NAND2X1TS U2472 ( .A(n4668), .B(n4667), .Y(n4669) );
NAND2X1TS U2473 ( .A(n4444), .B(n4443), .Y(n4486) );
BUFX4TS U2474 ( .A(FPADDSUB_FSM_selector_A), .Y(n2981) );
INVX2TS U2475 ( .A(n2674), .Y(n2672) );
NAND2X1TS U2476 ( .A(n6247), .B(n6244), .Y(n4435) );
CLKXOR2X2TS U2477 ( .A(n3544), .B(n3543), .Y(n2577) );
ADDFX2TS U2478 ( .A(n3613), .B(n3612), .CI(n3611), .CO(n3630), .S(n3615) );
XOR2X2TS U2479 ( .A(n4232), .B(n2737), .Y(n2736) );
CMPR32X2TS U2480 ( .A(n3434), .B(n3433), .C(n3432), .CO(n3442), .S(n3386) );
AO21X1TS U2481 ( .A0(n3725), .A1(n3831), .B0(n2140), .Y(n3612) );
NOR2X1TS U2482 ( .A(n6233), .B(n6231), .Y(n4428) );
ADDFHX2TS U2483 ( .A(n4121), .B(n4120), .CI(n4119), .CO(n4127), .S(n4126) );
NAND2X1TS U2484 ( .A(n4424), .B(n4423), .Y(n6230) );
INVX4TS U2485 ( .A(n4541), .Y(n3458) );
NOR2X4TS U2486 ( .A(n4104), .B(n4103), .Y(n4507) );
NAND2BXLTS U2487 ( .AN(n4351), .B(n4350), .Y(n2675) );
NAND2X1TS U2488 ( .A(n3563), .B(n3561), .Y(n2416) );
CLKXOR2X2TS U2489 ( .A(n3607), .B(n2734), .Y(n4410) );
XNOR2X1TS U2490 ( .A(n3783), .B(n2262), .Y(n3541) );
XNOR2X1TS U2491 ( .A(n3836), .B(n2131), .Y(n3495) );
INVX6TS U2492 ( .A(n4438), .Y(n4144) );
INVX6TS U2493 ( .A(n4444), .Y(n3716) );
INVX6TS U2494 ( .A(n4415), .Y(n3766) );
INVX2TS U2495 ( .A(n4278), .Y(n3715) );
INVX2TS U2496 ( .A(n4329), .Y(n3411) );
AO22X2TS U2497 ( .A0(n4140), .A1(n2561), .B0(n4141), .B1(n4142), .Y(n4161)
);
NOR2X1TS U2498 ( .A(n4422), .B(n4421), .Y(n6220) );
NAND2X1TS U2499 ( .A(n3546), .B(n3547), .Y(n2764) );
INVX3TS U2500 ( .A(n4282), .Y(n3685) );
CLKINVX3TS U2501 ( .A(n4452), .Y(n3294) );
OAI21X2TS U2502 ( .A0(n3818), .A1(n3817), .B0(n3816), .Y(n2721) );
NAND2X2TS U2503 ( .A(n4157), .B(n2773), .Y(n2769) );
XNOR2X1TS U2504 ( .A(n3751), .B(n2253), .Y(n3419) );
CMPR32X2TS U2505 ( .A(n3131), .B(n2222), .C(n3130), .CO(n3140), .S(n3240) );
INVX4TS U2506 ( .A(n4437), .Y(n4136) );
OAI2BB1X2TS U2507 ( .A0N(n4106), .A1N(n4107), .B0(n2682), .Y(n4124) );
INVX2TS U2508 ( .A(n4277), .Y(n2744) );
INVX3TS U2509 ( .A(n4325), .Y(n3374) );
XOR2X2TS U2510 ( .A(n4155), .B(n4154), .Y(n2153) );
INVX2TS U2511 ( .A(n2429), .Y(n2434) );
OAI2BB1X2TS U2512 ( .A0N(n4003), .A1N(n2666), .B0(n2664), .Y(n4134) );
NAND2X2TS U2513 ( .A(n4094), .B(n4093), .Y(n4468) );
OAI22X2TS U2514 ( .A0(n3848), .A1(n4051), .B0(n3788), .B1(n2334), .Y(n3868)
);
OAI22X1TS U2515 ( .A0(n3664), .A1(n2165), .B0(n3233), .B1(n2335), .Y(n3237)
);
OAI22X1TS U2516 ( .A0(n3302), .A1(n2258), .B0(n3328), .B1(n2271), .Y(n3360)
);
NOR2X1TS U2517 ( .A(n3608), .B(n2811), .Y(n3626) );
NAND3X4TS U2518 ( .A(n2155), .B(n2154), .C(n2156), .Y(n4156) );
OAI22X1TS U2519 ( .A0(n3519), .A1(n2325), .B0(n3537), .B1(n2237), .Y(n3539)
);
XNOR2X1TS U2520 ( .A(n3327), .B(n2255), .Y(n3225) );
XNOR2X1TS U2521 ( .A(n3783), .B(n2224), .Y(n3837) );
XNOR2X1TS U2522 ( .A(n3327), .B(n2253), .Y(n3303) );
XOR2X2TS U2523 ( .A(n2512), .B(n2513), .Y(n3466) );
INVX2TS U2524 ( .A(n4273), .Y(n3838) );
XOR2X2TS U2525 ( .A(n4270), .B(n3873), .Y(n2650) );
CMPR32X2TS U2526 ( .A(n3500), .B(n3499), .C(n3498), .CO(n3547), .S(n3503) );
OR2X6TS U2527 ( .A(n4152), .B(n2139), .Y(n2145) );
INVX3TS U2528 ( .A(n4439), .Y(n3839) );
NAND2X1TS U2529 ( .A(n2408), .B(n2406), .Y(n3505) );
NAND2X1TS U2530 ( .A(n4154), .B(n4155), .Y(n2156) );
NOR2X1TS U2531 ( .A(n4417), .B(n4416), .Y(n6210) );
AO21X1TS U2532 ( .A0(n2235), .A1(n2326), .B0(n2815), .Y(n3504) );
CLKXOR2X2TS U2533 ( .A(n3551), .B(n3553), .Y(n2614) );
INVX4TS U2534 ( .A(n4141), .Y(n2785) );
OR2X2TS U2535 ( .A(n3524), .B(n2258), .Y(n2631) );
NAND2X2TS U2536 ( .A(n4155), .B(n4153), .Y(n2154) );
OAI21X2TS U2537 ( .A0(n3873), .A1(n3872), .B0(n2648), .Y(n2649) );
OAI21X2TS U2538 ( .A0(n4003), .A1(n2666), .B0(n2665), .Y(n2664) );
NAND2BX2TS U2539 ( .AN(n3548), .B(n2754), .Y(n2630) );
XNOR2X1TS U2540 ( .A(n3836), .B(n2224), .Y(n3874) );
XNOR2X1TS U2541 ( .A(n4001), .B(n2131), .Y(n3144) );
XNOR2X1TS U2542 ( .A(n3933), .B(n2224), .Y(n2652) );
XNOR2X2TS U2543 ( .A(n3977), .B(n3723), .Y(n3302) );
XNOR2X2TS U2544 ( .A(n3933), .B(n2256), .Y(n3096) );
XNOR2X2TS U2545 ( .A(n3977), .B(n2262), .Y(n3425) );
CMPR32X2TS U2546 ( .A(n4081), .B(n4080), .C(n4079), .CO(n4097), .S(n4093) );
CMPR32X2TS U2547 ( .A(n2805), .B(n3550), .C(n3549), .CO(n3574), .S(n3552) );
BUFX6TS U2548 ( .A(n3847), .Y(n3933) );
INVX4TS U2549 ( .A(n4432), .Y(n4150) );
NAND2X4TS U2550 ( .A(n2534), .B(n2533), .Y(n2536) );
BUFX3TS U2551 ( .A(n3518), .Y(n2512) );
BUFX8TS U2552 ( .A(n3327), .Y(n3836) );
OAI22X1TS U2553 ( .A0(n3688), .A1(n2335), .B0(n3789), .B1(n2165), .Y(n3785)
);
NAND2BX1TS U2554 ( .AN(n3501), .B(n2407), .Y(n2406) );
XNOR2X2TS U2555 ( .A(n3751), .B(n2256), .Y(n3524) );
INVX2TS U2556 ( .A(n4256), .Y(n4056) );
OR2X6TS U2557 ( .A(n2738), .B(n2182), .Y(n3255) );
NOR2X1TS U2558 ( .A(n2163), .B(n2808), .Y(n3580) );
NOR2X1TS U2559 ( .A(n3608), .B(n2820), .Y(n3401) );
INVX6TS U2560 ( .A(n2140), .Y(n2256) );
INVX3TS U2561 ( .A(n4261), .Y(n3997) );
INVX2TS U2562 ( .A(n2255), .Y(n3944) );
BUFX8TS U2563 ( .A(n3216), .Y(n3751) );
OAI22X1TS U2564 ( .A0(n2718), .A1(n3090), .B0(n3081), .B1(n2451), .Y(n3160)
);
OAI22X2TS U2565 ( .A0(n2235), .A1(n3014), .B0(n2326), .B1(n3044), .Y(n3043)
);
NOR2X2TS U2566 ( .A(n2219), .B(n2704), .Y(n3572) );
XNOR2X1TS U2567 ( .A(n2118), .B(n3136), .Y(n4002) );
XNOR2X1TS U2568 ( .A(n6368), .B(FPMULT_Op_MX[10]), .Y(n3554) );
XNOR2X1TS U2569 ( .A(n4037), .B(n3136), .Y(n3935) );
XNOR2X2TS U2570 ( .A(n2276), .B(FPMULT_Op_MX[11]), .Y(n3577) );
XNOR2X2TS U2571 ( .A(n2118), .B(n2223), .Y(n2715) );
INVX2TS U2572 ( .A(n2415), .Y(n2253) );
NOR2X1TS U2573 ( .A(n2163), .B(n2174), .Y(n3500) );
INVX2TS U2574 ( .A(n3323), .Y(n3048) );
INVX6TS U2575 ( .A(n2494), .Y(n2500) );
INVX6TS U2576 ( .A(n2641), .Y(n4060) );
INVX6TS U2577 ( .A(n3723), .Y(n2140) );
BUFX6TS U2578 ( .A(n4048), .Y(n2263) );
INVX4TS U2579 ( .A(n2124), .Y(n2255) );
CLKBUFX2TS U2580 ( .A(n3150), .Y(n2726) );
OAI22X1TS U2581 ( .A0(n2718), .A1(n3671), .B0(n3261), .B1(n2451), .Y(n3705)
);
NAND2X4TS U2582 ( .A(n3194), .B(n3193), .Y(n2594) );
NAND2BX2TS U2583 ( .AN(n2481), .B(n3698), .Y(n2478) );
INVX4TS U2584 ( .A(n2641), .Y(n2334) );
BUFX16TS U2585 ( .A(n4051), .Y(n2251) );
INVX4TS U2586 ( .A(n2261), .Y(n2262) );
OAI22X1TS U2587 ( .A0(n3274), .A1(n2242), .B0(n2270), .B1(n3206), .Y(n3652)
);
XNOR2X1TS U2588 ( .A(n6365), .B(FPMULT_Op_MX[9]), .Y(n3320) );
XNOR2X2TS U2589 ( .A(n4070), .B(n4048), .Y(n4049) );
XNOR2X2TS U2590 ( .A(n2118), .B(n2254), .Y(n3870) );
XNOR2X2TS U2591 ( .A(n4037), .B(n2223), .Y(n4071) );
ADDFHX2TS U2592 ( .A(n3692), .B(n3691), .CI(n3690), .CO(n3654), .S(n3812) );
CMPR32X2TS U2593 ( .A(n6379), .B(n6099), .C(n3157), .CO(n3334), .S(n3148) );
BUFX6TS U2594 ( .A(n3136), .Y(n4048) );
OR2X6TS U2595 ( .A(n2641), .B(n2181), .Y(n4051) );
INVX2TS U2596 ( .A(n3699), .Y(n2481) );
INVX8TS U2597 ( .A(n2633), .Y(n3723) );
INVX6TS U2598 ( .A(n3752), .Y(n4085) );
NOR2X2TS U2599 ( .A(n2163), .B(n3010), .Y(n3323) );
INVX3TS U2600 ( .A(n3058), .Y(n2261) );
OAI22X1TS U2601 ( .A0(n2466), .A1(n6373), .B0(n2448), .B1(n3792), .Y(n3333)
);
ADDHX1TS U2602 ( .A(n3703), .B(n3702), .CO(n3710), .S(n3749) );
CLKXOR2X2TS U2603 ( .A(n6373), .B(n2747), .Y(n3168) );
XNOR2X1TS U2604 ( .A(n2563), .B(FPMULT_Op_MX[9]), .Y(n3017) );
OAI22X2TS U2605 ( .A0(n2233), .A1(n4062), .B0(n4046), .B1(n2244), .Y(n4417)
);
OAI22X2TS U2606 ( .A0(n2766), .A1(n3608), .B0(n2231), .B1(n3002), .Y(n3209)
);
NOR2X2TS U2607 ( .A(n2731), .B(n2687), .Y(n2686) );
XOR2X2TS U2608 ( .A(n3900), .B(n2747), .Y(n3258) );
XNOR2X2TS U2609 ( .A(n2492), .B(n3573), .Y(n3169) );
CLKINVX6TS U2610 ( .A(n2124), .Y(n2254) );
BUFX8TS U2611 ( .A(n3925), .Y(n2260) );
NAND2X1TS U2612 ( .A(n3053), .B(n3064), .Y(n3054) );
INVX6TS U2613 ( .A(n2272), .Y(n2273) );
CLKXOR2X4TS U2614 ( .A(n3123), .B(n3115), .Y(n4037) );
INVX4TS U2615 ( .A(n2222), .Y(n2223) );
BUFX6TS U2616 ( .A(n3113), .Y(n3899) );
OAI22X1TS U2617 ( .A0(n4072), .A1(n4047), .B0(n3918), .B1(n2816), .Y(n4044)
);
OAI22X1TS U2618 ( .A0(n2451), .A1(n3673), .B0(n3674), .B1(n2803), .Y(n3702)
);
OR2X2TS U2619 ( .A(n3155), .B(n3674), .Y(n3156) );
OAI22X2TS U2620 ( .A0(n2718), .A1(n3672), .B0(n3671), .B1(n2688), .Y(n3703)
);
OAI22X2TS U2621 ( .A0(n3696), .A1(n2269), .B0(n3827), .B1(n2549), .Y(n3823)
);
OAI22X1TS U2622 ( .A0(n2233), .A1(n4046), .B0(n3915), .B1(n2166), .Y(n3930)
);
XNOR2X1TS U2623 ( .A(n2221), .B(n2818), .Y(n2372) );
XNOR2X2TS U2624 ( .A(n2252), .B(n4070), .Y(n3851) );
OAI22X1TS U2625 ( .A0(n3257), .A1(n3793), .B0(n2816), .B1(n2651), .Y(n3796)
);
XNOR2X2TS U2626 ( .A(n2492), .B(n6374), .Y(n3679) );
XOR2X2TS U2627 ( .A(FPMULT_Op_MX[22]), .B(n2747), .Y(n3337) );
INVX4TS U2628 ( .A(n6368), .Y(n3608) );
XOR2X2TS U2629 ( .A(n3573), .B(n2747), .Y(n3154) );
BUFX6TS U2630 ( .A(n2120), .Y(n2328) );
INVX6TS U2631 ( .A(n3198), .Y(n4088) );
NOR2X1TS U2632 ( .A(n2282), .B(n6359), .Y(n3059) );
NOR2BX1TS U2633 ( .AN(n2341), .B(n2268), .Y(n3941) );
INVX12TS U2634 ( .A(n2702), .Y(n2219) );
INVX3TS U2635 ( .A(n2742), .Y(n2245) );
INVX4TS U2636 ( .A(n4069), .Y(n2222) );
NAND3X4TS U2637 ( .A(n2592), .B(n3111), .C(n2387), .Y(n2420) );
OAI22X1TS U2638 ( .A0(n3922), .A1(n3085), .B0(n2492), .B1(n2643), .Y(n3087)
);
OAI22X2TS U2639 ( .A0(n2549), .A1(n2817), .B0(n2269), .B1(n2169), .Y(n3962)
);
XNOR2X1TS U2640 ( .A(n2563), .B(FPMULT_Op_MX[5]), .Y(n3648) );
OAI22X1TS U2641 ( .A0(n2211), .A1(n2814), .B0(n3695), .B1(n3642), .Y(n3693)
);
BUFX8TS U2642 ( .A(n2688), .Y(n2451) );
XOR2X2TS U2643 ( .A(n2278), .B(n2811), .Y(n2469) );
XOR2X2TS U2644 ( .A(n6379), .B(n2747), .Y(n3741) );
XOR2X2TS U2645 ( .A(n2278), .B(n2810), .Y(n2482) );
XOR2X2TS U2646 ( .A(FPMULT_Op_MY[2]), .B(FPMULT_Op_MY[14]), .Y(n3138) );
NAND2X1TS U2647 ( .A(FPMULT_Op_MX[22]), .B(FPMULT_Op_MX[10]), .Y(n3191) );
INVX6TS U2648 ( .A(n2232), .Y(n2233) );
NAND2X1TS U2649 ( .A(FPMULT_Op_MY[10]), .B(FPMULT_Op_MY[22]), .Y(n3056) );
NAND2XLTS U2650 ( .A(FPMULT_Op_MY[8]), .B(FPMULT_Op_MY[20]), .Y(n3060) );
BUFX6TS U2651 ( .A(n2993), .Y(n3695) );
INVX2TS U2652 ( .A(n2775), .Y(n3643) );
BUFX16TS U2653 ( .A(n2355), .Y(n3734) );
BUFX12TS U2654 ( .A(FPMULT_Op_MY[11]), .Y(n6368) );
NOR2X4TS U2655 ( .A(n3107), .B(n2503), .Y(n2592) );
BUFX16TS U2656 ( .A(n2997), .Y(n3735) );
BUFX4TS U2657 ( .A(n2993), .Y(n2259) );
NAND2X2TS U2658 ( .A(n3701), .B(FPMULT_Op_MX[8]), .Y(n3173) );
NAND2X2TS U2659 ( .A(n3118), .B(n3117), .Y(n3120) );
XNOR2X1TS U2660 ( .A(n5857), .B(FPMULT_Op_MX[17]), .Y(n3901) );
XNOR2X2TS U2661 ( .A(n2748), .B(FPMULT_Op_MX[19]), .Y(n3028) );
NOR2X2TS U2662 ( .A(n3109), .B(n2503), .Y(n2591) );
INVX12TS U2663 ( .A(n2530), .Y(n2731) );
XNOR2X1TS U2664 ( .A(n5857), .B(n3792), .Y(n3855) );
XNOR2X2TS U2665 ( .A(n2278), .B(n6382), .Y(n3915) );
XOR2X2TS U2666 ( .A(n3792), .B(n2747), .Y(n3084) );
BUFX8TS U2667 ( .A(n2996), .Y(n3925) );
BUFX6TS U2668 ( .A(FPMULT_Op_MX[2]), .Y(n6380) );
AND2X6TS U2669 ( .A(n2992), .B(n2993), .Y(n2775) );
BUFX8TS U2670 ( .A(FPMULT_Op_MY[7]), .Y(n2277) );
INVX8TS U2671 ( .A(n2801), .Y(n2281) );
BUFX16TS U2672 ( .A(n2749), .Y(n2747) );
BUFX8TS U2673 ( .A(FPMULT_Op_MX[1]), .Y(n6381) );
BUFX6TS U2674 ( .A(FPMULT_Op_MX[3]), .Y(n6382) );
INVX4TS U2675 ( .A(n6366), .Y(n2284) );
BUFX6TS U2676 ( .A(FPMULT_Op_MX[15]), .Y(n6099) );
CLKINVX6TS U2677 ( .A(n3004), .Y(n2232) );
BUFX6TS U2678 ( .A(FPMULT_Op_MX[21]), .Y(n3573) );
BUFX4TS U2679 ( .A(n2432), .Y(n2355) );
INVX12TS U2680 ( .A(n2461), .Y(n2688) );
CLKINVX12TS U2681 ( .A(n2374), .Y(n2702) );
INVX6TS U2682 ( .A(n3001), .Y(n3609) );
NAND2X2TS U2683 ( .A(n3185), .B(n3186), .Y(n2791) );
NAND2X2TS U2684 ( .A(n3100), .B(n3099), .Y(n3183) );
INVX8TS U2685 ( .A(n2491), .Y(n2668) );
INVX8TS U2686 ( .A(n2995), .Y(n2246) );
CLKINVX6TS U2687 ( .A(FPMULT_Op_MY[12]), .Y(n2249) );
NAND2X1TS U2688 ( .A(FPMULT_Op_MY[4]), .B(FPMULT_Op_MY[16]), .Y(n3099) );
BUFX8TS U2689 ( .A(FPMULT_Op_MY[21]), .Y(n6359) );
BUFX8TS U2690 ( .A(FPMULT_Op_MX[18]), .Y(n3792) );
BUFX8TS U2691 ( .A(FPMULT_Op_MY[13]), .Y(n5857) );
NAND2X2TS U2692 ( .A(FPMULT_Op_MY[6]), .B(n6357), .Y(n3070) );
NOR2X2TS U2693 ( .A(n2586), .B(n3124), .Y(n2388) );
XOR2X2TS U2694 ( .A(FPMULT_Op_MY[18]), .B(FPMULT_Op_MY[19]), .Y(n2427) );
BUFX8TS U2695 ( .A(FPMULT_Op_MY[12]), .Y(n6367) );
CLKXOR2X2TS U2696 ( .A(FPMULT_Op_MY[4]), .B(FPMULT_Op_MY[5]), .Y(n3000) );
NAND2X6TS U2697 ( .A(n2994), .B(n2996), .Y(n2995) );
NAND2X1TS U2698 ( .A(FPMULT_Op_MY[2]), .B(FPMULT_Op_MY[14]), .Y(n3134) );
INVX6TS U2699 ( .A(n6366), .Y(n2282) );
INVX6TS U2700 ( .A(n2807), .Y(n2278) );
BUFX8TS U2701 ( .A(FPMULT_Op_MX[16]), .Y(n3900) );
BUFX8TS U2702 ( .A(FPMULT_Op_MX[17]), .Y(n6373) );
NOR2X6TS U2703 ( .A(FPMULT_Op_MX[14]), .B(FPMULT_Op_MX[2]), .Y(n2586) );
NOR2X6TS U2704 ( .A(FPMULT_Op_MX[15]), .B(FPMULT_Op_MX[3]), .Y(n3124) );
CLKINVX6TS U2705 ( .A(FPMULT_Op_MX[12]), .Y(n5858) );
CLKINVX6TS U2706 ( .A(FPMULT_Op_MY[0]), .Y(n2244) );
CLKINVX6TS U2707 ( .A(FPMULT_Op_MX[0]), .Y(n6098) );
BUFX16TS U2708 ( .A(FPMULT_Op_MY[7]), .Y(n6365) );
CLKXOR2X2TS U2709 ( .A(n6360), .B(FPMULT_Op_MY[16]), .Y(n3021) );
INVX8TS U2710 ( .A(n2364), .Y(n2643) );
BUFX8TS U2711 ( .A(FPMULT_Op_MY[17]), .Y(n6360) );
INVX6TS U2712 ( .A(FPMULT_Op_MY[9]), .Y(n6366) );
CLKXOR2X2TS U2713 ( .A(FPMULT_Op_MY[2]), .B(n2129), .Y(n2994) );
INVX2TS U2714 ( .A(FPMULT_Op_MY[13]), .Y(n2787) );
INVX2TS U2715 ( .A(n2143), .Y(n2114) );
INVX2TS U2716 ( .A(n2114), .Y(n2115) );
INVX2TS U2717 ( .A(n2114), .Y(n2116) );
NAND2X2TS U2718 ( .A(n6373), .B(FPMULT_Op_MX[5]), .Y(n3064) );
NAND2X2TS U2719 ( .A(FPMULT_Op_MX[15]), .B(FPMULT_Op_MX[3]), .Y(n3125) );
OAI22X1TS U2720 ( .A0(n3255), .A1(n3254), .B0(n3253), .B1(n2330), .Y(n3657)
);
XNOR2X2TS U2721 ( .A(n4070), .B(n3723), .Y(n3721) );
NAND2X1TS U2722 ( .A(n3126), .B(n3125), .Y(n3127) );
INVX6TS U2723 ( .A(n2619), .Y(n3977) );
OAI22X1TS U2724 ( .A0(n3128), .A1(n2330), .B0(n3197), .B1(n3255), .Y(n3130)
);
OAI22X2TS U2725 ( .A0(n3225), .A1(n2327), .B0(n3218), .B1(n2275), .Y(n3223)
);
INVX2TS U2726 ( .A(n4426), .Y(n3994) );
XNOR2X1TS U2727 ( .A(n3923), .B(n3136), .Y(n3936) );
OAI22X2TS U2728 ( .A0(n2766), .A1(n3020), .B0(n2231), .B1(n3051), .Y(n3047)
);
BUFX4TS U2729 ( .A(n3113), .Y(n2335) );
INVX2TS U2730 ( .A(n4559), .Y(n3515) );
CLKINVX3TS U2731 ( .A(n3231), .Y(n2264) );
OAI21X2TS U2732 ( .A0(n4107), .A1(n4106), .B0(n4105), .Y(n2682) );
XNOR2X1TS U2733 ( .A(n6359), .B(n6374), .Y(n3155) );
XNOR2X1TS U2734 ( .A(n3751), .B(n2131), .Y(n3588) );
XNOR2X1TS U2735 ( .A(n2563), .B(FPMULT_Op_MX[7]), .Y(n3206) );
XNOR2X1TS U2736 ( .A(n2285), .B(FPMULT_Op_MX[22]), .Y(n3025) );
XNOR2X2TS U2737 ( .A(n2373), .B(n2372), .Y(n3033) );
INVX2TS U2738 ( .A(n2135), .Y(n2440) );
BUFX8TS U2739 ( .A(n3735), .Y(n2235) );
BUFX8TS U2740 ( .A(FPMULT_Op_MY[3]), .Y(n2129) );
CLKBUFX2TS U2741 ( .A(n4725), .Y(n4726) );
NOR2X4TS U2742 ( .A(n2440), .B(n2137), .Y(n2443) );
OR2X1TS U2743 ( .A(n4596), .B(n4597), .Y(n4595) );
NAND2X1TS U2744 ( .A(n4090), .B(n4089), .Y(n4479) );
OAI21X2TS U2745 ( .A0(n3551), .A1(n3553), .B0(n3552), .Y(n2617) );
OAI21XLTS U2746 ( .A0(n4400), .A1(n4399), .B0(n4398), .Y(n4401) );
AOI21X1TS U2747 ( .A0(n4540), .A1(n4641), .B0(n4539), .Y(n4545) );
NAND2X1TS U2748 ( .A(n4574), .B(n4573), .Y(n4575) );
OAI22X1TS U2749 ( .A0(n3905), .A1(n2166), .B0(n2234), .B1(n2600), .Y(n3913)
);
NAND2X1TS U2750 ( .A(n4269), .B(n4268), .Y(n4721) );
NOR2XLTS U2751 ( .A(n6734), .B(n2986), .Y(n2946) );
NOR2XLTS U2752 ( .A(n6759), .B(n2986), .Y(n2958) );
NOR2X6TS U2753 ( .A(n2523), .B(n2522), .Y(n2521) );
INVX4TS U2754 ( .A(n2637), .Y(n2572) );
NOR3BX1TS U2755 ( .AN(n5939), .B(n5938), .C(FPADDSUB_Add_Subt_result[14]),
.Y(n5795) );
NOR2X1TS U2756 ( .A(n2936), .B(n2935), .Y(n6066) );
NAND2X2TS U2757 ( .A(n2392), .B(n4719), .Y(n2391) );
NOR2XLTS U2758 ( .A(n4397), .B(n4366), .Y(n4357) );
AOI21X1TS U2759 ( .A0(n4310), .A1(n4308), .B0(n4298), .Y(n4303) );
OAI211XLTS U2760 ( .A0(n5624), .A1(n5680), .B0(n5623), .C0(n5622), .Y(n5629)
);
NOR2XLTS U2761 ( .A(FPADDSUB_Add_Subt_result[3]), .B(
FPADDSUB_Add_Subt_result[2]), .Y(n5612) );
INVX2TS U2762 ( .A(n6513), .Y(n6515) );
OR2X1TS U2763 ( .A(n4419), .B(n4418), .Y(n6216) );
NAND2X1TS U2764 ( .A(n5535), .B(n5007), .Y(n5533) );
INVX2TS U2765 ( .A(n5417), .Y(n5097) );
OR2X1TS U2766 ( .A(n2972), .B(n2971), .Y(n5966) );
NOR2XLTS U2767 ( .A(n5088), .B(r_mode[1]), .Y(n5080) );
NOR2XLTS U2768 ( .A(n5511), .B(FPADDSUB_Add_Subt_result[0]), .Y(n5504) );
NAND3X4TS U2769 ( .A(n2623), .B(n2187), .C(n2418), .Y(n2741) );
NAND2X1TS U2770 ( .A(n2850), .B(n2849), .Y(n5249) );
NOR3X1TS U2771 ( .A(FPADDSUB_Add_Subt_result[3]), .B(
FPADDSUB_Add_Subt_result[2]), .C(n5791), .Y(n5936) );
NAND2X1TS U2772 ( .A(n5610), .B(n6771), .Y(n5614) );
AOI21X2TS U2773 ( .A0(n6020), .A1(n6018), .B0(n2957), .Y(n6011) );
OAI21XLTS U2774 ( .A0(n6290), .A1(n6289), .B0(n6288), .Y(n6295) );
INVX2TS U2775 ( .A(n4872), .Y(n6317) );
OAI21XLTS U2776 ( .A0(n6061), .A1(n6023), .B0(n6022), .Y(n6028) );
AOI21X2TS U2777 ( .A0(n6005), .A1(n6003), .B0(n2964), .Y(n5985) );
INVX2TS U2778 ( .A(n4823), .Y(n4959) );
OAI21X2TS U2779 ( .A0(n6011), .A1(n6007), .B0(n6008), .Y(n6005) );
NOR2XLTS U2780 ( .A(n5954), .B(n5953), .Y(n5959) );
AND2X2TS U2781 ( .A(n5116), .B(FPSENCOS_sel_mux_2_reg[1]), .Y(n5117) );
CLKINVX3TS U2782 ( .A(n5252), .Y(n2289) );
BUFX4TS U2783 ( .A(n4803), .Y(n4835) );
INVX2TS U2784 ( .A(n4850), .Y(n5174) );
NOR2XLTS U2785 ( .A(FPADDSUB_LZA_output[4]), .B(n6524), .Y(n5617) );
NOR2XLTS U2786 ( .A(n6803), .B(n6354), .Y(FPMULT_S_Oper_A_exp[8]) );
AOI21X1TS U2787 ( .A0(FPSENCOS_cont_var_out[0]), .A1(n5050), .B0(n6412), .Y(
n6507) );
AOI211XLTS U2788 ( .A0(n5921), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[36]), .B0(n5914),
.C0(n5015), .Y(n5016) );
AOI211XLTS U2789 ( .A0(n4911), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[37]), .B0(n5914),
.C0(n5019), .Y(n5020) );
AOI21X2TS U2790 ( .A0(n2669), .A1(n4959), .B0(n4824), .Y(n4829) );
INVX2TS U2791 ( .A(n5005), .Y(n5418) );
OAI211XLTS U2792 ( .A0(n5911), .A1(n6799), .B0(n5903), .C0(n5902), .Y(n5904)
);
NOR2XLTS U2793 ( .A(n6348), .B(n5882), .Y(n5883) );
CLKBUFX2TS U2794 ( .A(n5410), .Y(n5873) );
NOR2XLTS U2795 ( .A(n6348), .B(n5252), .Y(n5889) );
CLKINVX3TS U2796 ( .A(n5743), .Y(n5777) );
BUFX3TS U2797 ( .A(n5428), .Y(n6588) );
BUFX3TS U2798 ( .A(n6626), .Y(n6625) );
OAI21XLTS U2799 ( .A0(n6604), .A1(n6796), .B0(n6607), .Y(n5038) );
INVX2TS U2800 ( .A(n6472), .Y(n6612) );
INVX2TS U2801 ( .A(n6397), .Y(n6401) );
CLKINVX3TS U2802 ( .A(n2141), .Y(n6097) );
INVX2TS U2803 ( .A(n4962), .Y(n5300) );
INVX2TS U2804 ( .A(n4962), .Y(n5181) );
INVX2TS U2805 ( .A(n4962), .Y(n5190) );
AOI31XLTS U2806 ( .A0(n5619), .A1(n6524), .A2(n5618), .B0(n5617), .Y(n1657)
);
CLKMX2X2TS U2807 ( .A(n4949), .B(FPMULT_P_Sgf[29]), .S0(n4922), .Y(n1947) );
OAI21XLTS U2808 ( .A0(n6795), .A1(n6429), .B0(n5114), .Y(n1792) );
OAI21XLTS U2809 ( .A0(n5746), .A1(n6784), .B0(n5719), .Y(n1226) );
OAI21XLTS U2810 ( .A0(n6722), .A1(n5773), .B0(n5760), .Y(n1265) );
OAI211XLTS U2811 ( .A0(n5523), .A1(n2199), .B0(n5471), .C0(n5470), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[6]) );
OAI21XLTS U2812 ( .A0(n6731), .A1(n5777), .B0(n5751), .Y(n1295) );
OAI211XLTS U2813 ( .A0(n5592), .A1(n6802), .B0(n5545), .C0(n5544), .Y(n1637)
);
OAI211XLTS U2814 ( .A0(n5891), .A1(n6707), .B0(n5567), .C0(n5566), .Y(n1641)
);
OAI211XLTS U2815 ( .A0(n5406), .A1(n6710), .B0(n5131), .C0(n5130), .Y(n1314)
);
XOR2X1TS U2816 ( .A(n4829), .B(n4828), .Y(FPMULT_Sgf_operation_Result[31])
);
OAI211XLTS U2817 ( .A0(n5352), .A1(n6488), .B0(n5351), .C0(n5350), .Y(n1297)
);
OAI211XLTS U2818 ( .A0(n5352), .A1(n6835), .B0(n5324), .C0(n5323), .Y(n1293)
);
OAI211XLTS U2819 ( .A0(n5380), .A1(n6483), .B0(n5364), .C0(n5363), .Y(n1242)
);
OAI211XLTS U2820 ( .A0(n5380), .A1(n6847), .B0(n5358), .C0(n5357), .Y(n1245)
);
OAI211XLTS U2821 ( .A0(n5374), .A1(n6841), .B0(n5373), .C0(n5372), .Y(n1266)
);
OAI211XLTS U2822 ( .A0(n5374), .A1(n6467), .B0(n5341), .C0(n5340), .Y(n1271)
);
OAI211XLTS U2823 ( .A0(n5352), .A1(n6834), .B0(n5304), .C0(n5303), .Y(n1296)
);
OAI211XLTS U2824 ( .A0(n5518), .A1(n5257), .B0(n5490), .C0(n5489), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[8]) );
OAI21XLTS U2825 ( .A0(n6757), .A1(n5777), .B0(n5758), .Y(n1288) );
OAI211XLTS U2826 ( .A0(n6454), .A1(n5406), .B0(n5347), .C0(n5346), .Y(n1329)
);
OAI21XLTS U2827 ( .A0(n6582), .A1(n5240), .B0(n5232), .Y(n1368) );
OAI21XLTS U2828 ( .A0(n6570), .A1(n5236), .B0(n5201), .Y(n1386) );
OAI21XLTS U2829 ( .A0(n6571), .A1(n5236), .B0(n5195), .Y(n1384) );
OAI21XLTS U2830 ( .A0(n6586), .A1(n5240), .B0(n5239), .Y(n1364) );
OAI211XLTS U2831 ( .A0(n6585), .A1(n5162), .B0(n6431), .C0(n6440), .Y(n1823)
);
XNOR2X4TS U2832 ( .A(n2714), .B(n2387), .Y(n2118) );
OR2X8TS U2833 ( .A(n4172), .B(n4173), .Y(n2119) );
BUFX3TS U2834 ( .A(n5051), .Y(n6526) );
XNOR2X4TS U2835 ( .A(FPMULT_Op_MY[18]), .B(FPMULT_Op_MY[17]), .Y(n2120) );
BUFX3TS U2836 ( .A(n5119), .Y(n5210) );
BUFX3TS U2837 ( .A(n5210), .Y(n5402) );
OR2X4TS U2838 ( .A(n2527), .B(n2798), .Y(n2121) );
NAND2X4TS U2839 ( .A(n5857), .B(n2249), .Y(n3257) );
AND2X8TS U2840 ( .A(n2268), .B(n3000), .Y(n2122) );
INVX6TS U2841 ( .A(n2178), .Y(n2272) );
INVX2TS U2842 ( .A(n4424), .Y(n3932) );
INVX2TS U2843 ( .A(n6639), .Y(n2265) );
CLKBUFX2TS U2844 ( .A(n5118), .Y(n6639) );
CLKXOR2X4TS U2845 ( .A(n3183), .B(n3189), .Y(n2124) );
INVX2TS U2846 ( .A(n3423), .Y(n3969) );
AND2X2TS U2847 ( .A(n4680), .B(n4679), .Y(n2125) );
INVX4TS U2848 ( .A(n4692), .Y(n2621) );
INVX2TS U2849 ( .A(n6592), .Y(n2279) );
BUFX3TS U2850 ( .A(n5427), .Y(n6592) );
INVX8TS U2851 ( .A(n3953), .Y(n2127) );
INVX16TS U2852 ( .A(n2127), .Y(n2128) );
NAND2X6TS U2853 ( .A(n3021), .B(n3187), .Y(n3953) );
NOR2X6TS U2854 ( .A(n4651), .B(n4648), .Y(n2758) );
NAND2X4TS U2855 ( .A(n4703), .B(n4923), .Y(n2694) );
XNOR2X2TS U2856 ( .A(n4956), .B(n4955), .Y(n4957) );
NAND2X6TS U2857 ( .A(n2615), .B(n4752), .Y(n4836) );
NAND3X6TS U2858 ( .A(n2613), .B(n2740), .C(n2741), .Y(n2739) );
NAND4X6TS U2859 ( .A(n2635), .B(n2656), .C(n2611), .D(n2698), .Y(n2610) );
NAND2X1TS U2860 ( .A(n4954), .B(n4953), .Y(n4955) );
NAND2X4TS U2861 ( .A(n2623), .B(n2658), .Y(n2528) );
NOR2X4TS U2862 ( .A(n4797), .B(n4784), .Y(n4789) );
INVX6TS U2863 ( .A(n2208), .Y(n4801) );
CLKMX2X2TS U2864 ( .A(n6313), .B(FPMULT_P_Sgf[18]), .S0(n6910), .Y(n1936) );
INVX6TS U2865 ( .A(n4704), .Y(n2130) );
CLKMX2X2TS U2866 ( .A(n6300), .B(FPMULT_P_Sgf[16]), .S0(n6910), .Y(n1934) );
NAND2X4TS U2867 ( .A(n2366), .B(n4735), .Y(n2383) );
NAND2X4TS U2868 ( .A(n2761), .B(n2762), .Y(n2699) );
INVX4TS U2869 ( .A(n2443), .Y(n2438) );
CLKMX2X2TS U2870 ( .A(n6287), .B(FPMULT_P_Sgf[14]), .S0(n6910), .Y(n1932) );
NAND2X4TS U2871 ( .A(n4618), .B(n4617), .Y(n6314) );
NAND2X6TS U2872 ( .A(n2662), .B(n2660), .Y(n4293) );
CLKMX2X2TS U2873 ( .A(n6283), .B(FPMULT_P_Sgf[13]), .S0(n6910), .Y(n1931) );
INVX3TS U2874 ( .A(n4679), .Y(n2423) );
INVX6TS U2875 ( .A(n4705), .Y(n2136) );
NOR2X4TS U2876 ( .A(n4564), .B(n4563), .Y(n6308) );
XOR2X1TS U2877 ( .A(n2990), .B(n2989), .Y(n2991) );
BUFX16TS U2878 ( .A(n4678), .Y(n2504) );
CLKMX2X2TS U2879 ( .A(n6277), .B(FPMULT_P_Sgf[12]), .S0(n6910), .Y(n1930) );
INVX2TS U2880 ( .A(n4750), .Y(n2609) );
ADDFHX2TS U2881 ( .A(n3597), .B(n3596), .CI(n3595), .CO(n4214), .S(n4211) );
OR2X2TS U2882 ( .A(n4246), .B(n4245), .Y(n4248) );
CLKMX2X2TS U2883 ( .A(n6273), .B(FPMULT_P_Sgf[11]), .S0(n6306), .Y(n1929) );
CLKMX2X2TS U2884 ( .A(n6200), .B(FPMULT_FSM_add_overflow_flag), .S0(n6122),
.Y(n1965) );
CLKMX2X2TS U2885 ( .A(n6106), .B(FPMULT_Add_result[23]), .S0(n6179), .Y(
n1966) );
ADDFHX2TS U2886 ( .A(n3594), .B(n3593), .CI(n3592), .CO(n3595), .S(n3568) );
CLKMX2X2TS U2887 ( .A(n6268), .B(FPMULT_P_Sgf[10]), .S0(n6306), .Y(n1928) );
INVX4TS U2888 ( .A(n4522), .Y(n2710) );
OAI2BB1X2TS U2889 ( .A0N(n3615), .A1N(n2672), .B0(n2671), .Y(n3638) );
CLKMX2X2TS U2890 ( .A(n6250), .B(FPMULT_P_Sgf[8]), .S0(n6306), .Y(n1926) );
NAND2X4TS U2891 ( .A(n4118), .B(n4117), .Y(n4522) );
XOR3X2TS U2892 ( .A(n4244), .B(n4243), .C(n4242), .Y(n4245) );
INVX2TS U2893 ( .A(n4117), .Y(n2711) );
ADDFHX2TS U2894 ( .A(n3437), .B(n3436), .CI(n3435), .CO(n3441), .S(n3387) );
CLKMX2X2TS U2895 ( .A(FPADDSUB_Add_Subt_result[18]), .B(n6012), .S0(n6036),
.Y(n1681) );
XOR2X2TS U2896 ( .A(n3563), .B(n2138), .Y(n2629) );
INVX2TS U2897 ( .A(n5799), .Y(n5791) );
NAND2X4TS U2898 ( .A(n4550), .B(n4555), .Y(n4629) );
CLKMX2X2TS U2899 ( .A(FPADDSUB_Add_Subt_result[16]), .B(n6037), .S0(n6036),
.Y(n1679) );
CLKMX2X2TS U2900 ( .A(FPADDSUB_Add_Subt_result[17]), .B(n6021), .S0(n6036),
.Y(n1680) );
CLKMX2X2TS U2901 ( .A(FPMULT_exp_oper_result[7]), .B(
FPMULT_Exp_module_Data_S[7]), .S0(n6999), .Y(n1907) );
OAI211X1TS U2902 ( .A0(n2142), .A1(n6804), .B0(n5710), .C0(n5709), .Y(n1330)
);
AND2X4TS U2903 ( .A(n2676), .B(n2675), .Y(n2674) );
NOR2X2TS U2904 ( .A(n5611), .B(FPADDSUB_Add_Subt_result[4]), .Y(n5799) );
CLKMX2X2TS U2905 ( .A(FPADDSUB_Add_Subt_result[15]), .B(n6058), .S0(n5979),
.Y(n1678) );
INVX6TS U2906 ( .A(n2150), .Y(n4322) );
INVX2TS U2907 ( .A(n4101), .Y(n2778) );
INVX2TS U2908 ( .A(n4512), .Y(n4501) );
CLKMX2X2TS U2909 ( .A(FPADDSUB_Add_Subt_result[7]), .B(n6016), .S0(n6036),
.Y(n1670) );
NAND2X4TS U2910 ( .A(n2631), .B(n2630), .Y(n3561) );
CLKMX2X2TS U2911 ( .A(FPADDSUB_Add_Subt_result[4]), .B(n5980), .S0(n6036),
.Y(n1667) );
CLKMX2X2TS U2912 ( .A(n5930), .B(FPADDSUB_exp_oper_result[4]), .S0(n2213),
.Y(n1695) );
CLKMX2X2TS U2913 ( .A(FPADDSUB_Add_Subt_result[5]), .B(n5992), .S0(n6036),
.Y(n1668) );
OAI21X1TS U2914 ( .A0(n5706), .A1(n6790), .B0(n5724), .Y(n1223) );
CLKMX2X2TS U2915 ( .A(n6123), .B(FPMULT_Add_result[17]), .S0(n6199), .Y(
n1972) );
AND2X6TS U2916 ( .A(n2457), .B(n2456), .Y(n2150) );
XNOR2X2TS U2917 ( .A(n2767), .B(n4597), .Y(n3589) );
NAND2X4TS U2918 ( .A(n3093), .B(n2535), .Y(n2534) );
OAI21X1TS U2919 ( .A0(n5708), .A1(n5765), .B0(n5749), .Y(n5705) );
INVX4TS U2920 ( .A(n6508), .Y(n6527) );
INVX4TS U2921 ( .A(n5749), .Y(n5755) );
INVX4TS U2922 ( .A(n5749), .Y(n5774) );
CLKMX2X2TS U2923 ( .A(FPADDSUB_Add_Subt_result[3]), .B(n5964), .S0(n5969),
.Y(n1666) );
NAND2X4TS U2924 ( .A(n2765), .B(n2764), .Y(n4596) );
INVX4TS U2925 ( .A(n5749), .Y(n5770) );
INVX3TS U2926 ( .A(n4560), .Y(n3496) );
CLKMX2X2TS U2927 ( .A(n6126), .B(FPMULT_Add_result[16]), .S0(n6199), .Y(
n1973) );
INVX4TS U2928 ( .A(n2825), .Y(n5729) );
CLKMX2X2TS U2929 ( .A(FPMULT_exp_oper_result[4]), .B(
FPMULT_Exp_module_Data_S[4]), .S0(n6999), .Y(n1910) );
CLKMX2X2TS U2930 ( .A(n6128), .B(FPMULT_Add_result[15]), .S0(n6199), .Y(
n1974) );
INVX4TS U2931 ( .A(n5706), .Y(n5743) );
INVX4TS U2932 ( .A(n5706), .Y(n5694) );
OAI21X1TS U2933 ( .A0(n6205), .A1(n6659), .B0(n4853), .Y(n2057) );
CLKMX2X2TS U2934 ( .A(FPMULT_exp_oper_result[3]), .B(
FPMULT_Exp_module_Data_S[3]), .S0(n6999), .Y(n1911) );
INVX4TS U2935 ( .A(n5873), .Y(n5390) );
INVX4TS U2936 ( .A(n5873), .Y(n6632) );
AND2X2TS U2937 ( .A(n4670), .B(n4669), .Y(n4671) );
INVX4TS U2938 ( .A(n6593), .Y(n6485) );
INVX4TS U2939 ( .A(n5870), .Y(n6492) );
INVX4TS U2940 ( .A(n5410), .Y(n5339) );
NAND2X1TS U2941 ( .A(n5988), .B(n2908), .Y(n2910) );
CLKMX2X2TS U2942 ( .A(n6132), .B(FPMULT_Add_result[13]), .S0(n6199), .Y(
n1976) );
NAND4BX1TS U2943 ( .AN(FPADDSUB_Add_Subt_result[9]), .B(n6517), .C(
FPADDSUB_Add_Subt_result[8]), .D(n6516), .Y(n6518) );
INVX4TS U2944 ( .A(n5410), .Y(n5403) );
CLKMX2X2TS U2945 ( .A(Data_1[27]), .B(FPMULT_Op_MX[27]), .S0(n6097), .Y(
n2051) );
CLKMX2X2TS U2946 ( .A(Data_1[7]), .B(FPMULT_Op_MX[7]), .S0(n6207), .Y(n2031)
);
CLKMX2X2TS U2947 ( .A(FPMULT_exp_oper_result[1]), .B(
FPMULT_Exp_module_Data_S[1]), .S0(n6999), .Y(n1913) );
CLKMX2X2TS U2948 ( .A(Data_1[8]), .B(FPMULT_Op_MX[8]), .S0(n2322), .Y(n2032)
);
AND2X6TS U2949 ( .A(n3077), .B(n3831), .Y(n2755) );
CLKMX2X2TS U2950 ( .A(Data_1[2]), .B(n6380), .S0(n2322), .Y(n2026) );
CLKMX2X2TS U2951 ( .A(Data_1[9]), .B(FPMULT_Op_MX[9]), .S0(n6097), .Y(n2033)
);
CLKMX2X2TS U2952 ( .A(Data_1[6]), .B(FPMULT_Op_MX[6]), .S0(n6206), .Y(n2030)
);
CLKMX2X2TS U2953 ( .A(Data_1[4]), .B(FPMULT_Op_MX[4]), .S0(n6206), .Y(n2028)
);
NAND2BX1TS U2954 ( .AN(n6256), .B(n4075), .Y(n6258) );
CLKMX2X2TS U2955 ( .A(Data_2[12]), .B(n6367), .S0(n2322), .Y(n2004) );
CLKMX2X2TS U2956 ( .A(Data_2[28]), .B(FPMULT_Op_MY[28]), .S0(n6206), .Y(
n2020) );
CLKMX2X2TS U2957 ( .A(Data_1[11]), .B(FPMULT_Op_MX[11]), .S0(n6207), .Y(
n2035) );
CLKMX2X2TS U2958 ( .A(Data_2[27]), .B(FPMULT_Op_MY[27]), .S0(n6097), .Y(
n2019) );
INVX4TS U2959 ( .A(n5585), .Y(n2315) );
CLKMX2X2TS U2960 ( .A(Data_2[25]), .B(FPMULT_Op_MY[25]), .S0(n6207), .Y(
n2017) );
CLKMX2X2TS U2961 ( .A(Data_1[25]), .B(FPMULT_Op_MX[25]), .S0(n2322), .Y(
n2049) );
CLKMX2X2TS U2962 ( .A(Data_1[30]), .B(FPMULT_Op_MX[30]), .S0(n6206), .Y(
n2054) );
CLKMX2X2TS U2963 ( .A(Data_1[23]), .B(FPMULT_Op_MX[23]), .S0(n6206), .Y(
n2047) );
CLKMX2X2TS U2964 ( .A(Data_1[26]), .B(FPMULT_Op_MX[26]), .S0(n6207), .Y(
n2050) );
CLKMX2X2TS U2965 ( .A(Data_1[28]), .B(FPMULT_Op_MX[28]), .S0(n6207), .Y(
n2052) );
CLKMX2X2TS U2966 ( .A(Data_2[26]), .B(FPMULT_Op_MY[26]), .S0(n6206), .Y(
n2018) );
CLKMX2X2TS U2967 ( .A(Data_2[17]), .B(n2285), .S0(n6207), .Y(n2009) );
CLKMX2X2TS U2968 ( .A(Data_1[10]), .B(FPMULT_Op_MX[10]), .S0(n6206), .Y(
n2034) );
CLKMX2X2TS U2969 ( .A(Data_2[16]), .B(FPMULT_Op_MY[16]), .S0(n6206), .Y(
n2008) );
CLKMX2X2TS U2970 ( .A(Data_2[1]), .B(n2278), .S0(n2322), .Y(n1993) );
CLKMX2X2TS U2971 ( .A(Data_2[30]), .B(FPMULT_Op_MY[30]), .S0(n2322), .Y(
n2022) );
CLKMX2X2TS U2972 ( .A(Data_2[3]), .B(n2281), .S0(n6207), .Y(n1995) );
CLKMX2X2TS U2973 ( .A(Data_1[24]), .B(FPMULT_Op_MX[24]), .S0(n6097), .Y(
n2048) );
CLKMX2X2TS U2974 ( .A(Data_2[4]), .B(FPMULT_Op_MY[4]), .S0(n6097), .Y(n1996)
);
CLKMX2X2TS U2975 ( .A(FPMULT_exp_oper_result[0]), .B(
FPMULT_Exp_module_Data_S[0]), .S0(n6999), .Y(n1914) );
CLKMX2X2TS U2976 ( .A(Data_2[29]), .B(FPMULT_Op_MY[29]), .S0(n6207), .Y(
n2021) );
INVX4TS U2977 ( .A(n5252), .Y(n2290) );
CLKMX2X2TS U2978 ( .A(Data_2[14]), .B(n6358), .S0(n6097), .Y(n2006) );
AO21X1TS U2979 ( .A0(FPSENCOS_d_ff3_LUT_out[16]), .A1(n6445), .B0(n6446),
.Y(n1818) );
BUFX6TS U2980 ( .A(n2738), .Y(n3659) );
OR2X2TS U2981 ( .A(FPSENCOS_d_ff3_LUT_out[27]), .B(n6612), .Y(n1829) );
INVX12TS U2982 ( .A(n2261), .Y(n2131) );
INVX3TS U2983 ( .A(n2141), .Y(n2322) );
INVX4TS U2984 ( .A(n2303), .Y(n2305) );
AO22X1TS U2985 ( .A0(n5500), .A1(FPADDSUB_Add_Subt_result[4]), .B0(
FPADDSUB_DmP[19]), .B1(n5472), .Y(n5473) );
INVX12TS U2986 ( .A(n2211), .Y(n2774) );
AO21X1TS U2987 ( .A0(FPMULT_Sgf_normalized_result[23]), .A1(n6110), .B0(
n6109), .Y(n1990) );
AO22X1TS U2988 ( .A0(n2141), .A1(Data_1[31]), .B0(n5778), .B1(
FPMULT_Op_MX[31]), .Y(n2023) );
AO22X1TS U2989 ( .A0(n5500), .A1(FPADDSUB_Add_Subt_result[17]), .B0(
FPADDSUB_DmP[6]), .B1(n5472), .Y(n5269) );
AO21X1TS U2990 ( .A0(FPSENCOS_d_ff3_LUT_out[3]), .A1(n6469), .B0(n6446), .Y(
n1805) );
NAND4X1TS U2991 ( .A(n7011), .B(n7010), .C(n7009), .D(n6338), .Y(n6340) );
NAND2BX1TS U2992 ( .AN(n4088), .B(n2254), .Y(n3943) );
AO22X1TS U2993 ( .A0(n2141), .A1(Data_2[31]), .B0(n5778), .B1(
FPMULT_Op_MY[31]), .Y(n2061) );
OR2X2TS U2994 ( .A(n2956), .B(n2955), .Y(n6018) );
NAND2X4TS U2995 ( .A(n6910), .B(n6391), .Y(n6999) );
INVX3TS U2996 ( .A(n2142), .Y(n5765) );
INVX4TS U2997 ( .A(n2141), .Y(n2132) );
AOI31X1TS U2998 ( .A0(n6512), .A1(FPADDSUB_Add_Subt_result[16]), .A2(n6774),
.B0(n6511), .Y(n6520) );
INVX3TS U2999 ( .A(n2142), .Y(n5737) );
INVX3TS U3000 ( .A(n2142), .Y(n5771) );
INVX3TS U3001 ( .A(n2142), .Y(n5728) );
INVX3TS U3002 ( .A(n2142), .Y(n5775) );
OAI31X1TS U3003 ( .A0(n5244), .A1(n5243), .A2(n5133), .B0(n5242), .Y(
operation_ready) );
NAND2X4TS U3004 ( .A(n2786), .B(n6368), .Y(n3121) );
INVX3TS U3005 ( .A(n2142), .Y(n5740) );
INVX2TS U3006 ( .A(n3190), .Y(n2377) );
NAND2X1TS U3007 ( .A(n3674), .B(n2688), .Y(n2453) );
NOR2X1TS U3008 ( .A(n6442), .B(n5484), .Y(n5039) );
AOI31X1TS U3009 ( .A0(n6330), .A1(n6329), .A2(n6328), .B0(dataB[27]), .Y(
n6341) );
AOI211X1TS U3010 ( .A0(n5804), .A1(n6662), .B0(n6397), .C0(n7012), .Y(n4853)
);
BUFX16TS U3011 ( .A(n3674), .Y(n2718) );
INVX4TS U3012 ( .A(n2196), .Y(n5877) );
INVX4TS U3013 ( .A(n2196), .Y(n6637) );
INVX4TS U3014 ( .A(n2196), .Y(n5407) );
INVX4TS U3015 ( .A(n2196), .Y(n5382) );
INVX4TS U3016 ( .A(n2196), .Y(n5326) );
NAND2X4TS U3017 ( .A(n3057), .B(n3056), .Y(n2786) );
INVX4TS U3018 ( .A(n2196), .Y(n5370) );
INVX4TS U3019 ( .A(n2196), .Y(n5401) );
NAND2BX1TS U3020 ( .AN(n2341), .B(n2283), .Y(n3642) );
INVX4TS U3021 ( .A(n2239), .Y(n6597) );
AO22X1TS U3022 ( .A0(FPADDSUB_LZA_output[3]), .A1(n5248), .B0(n5247), .B1(
FPADDSUB_DmP[26]), .Y(n2846) );
INVX4TS U3023 ( .A(n6125), .Y(n6199) );
AO22X1TS U3024 ( .A0(FPADDSUB_LZA_output[2]), .A1(n5248), .B0(n2840), .B1(
FPADDSUB_DmP[25]), .Y(n2847) );
AO22X1TS U3025 ( .A0(FPADDSUB_LZA_output[1]), .A1(n5248), .B0(n2840), .B1(
FPADDSUB_DmP[24]), .Y(n2848) );
INVX4TS U3026 ( .A(n2833), .Y(n6532) );
INVX2TS U3027 ( .A(n2703), .Y(n2687) );
OAI211XLTS U3028 ( .A0(n6789), .A1(FPADDSUB_intDX[3]), .B0(n5634), .C0(n5633), .Y(n5637) );
CLKMX2X2TS U3029 ( .A(FPADDSUB_DMP[0]), .B(FPADDSUB_Sgf_normalized_result[2]), .S0(n2917), .Y(n2891) );
INVX4TS U3030 ( .A(n6442), .Y(n5483) );
INVX4TS U3031 ( .A(n2831), .Y(n6609) );
NOR2X1TS U3032 ( .A(n5665), .B(FPADDSUB_intDY[16]), .Y(n5666) );
CLKMX2X2TS U3033 ( .A(FPADDSUB_DMP[26]), .B(FPADDSUB_exp_oper_result[3]),
.S0(n2983), .Y(n2862) );
CLKMX2X2TS U3034 ( .A(FPADDSUB_DMP[27]), .B(FPADDSUB_exp_oper_result[4]),
.S0(n2983), .Y(n2859) );
CLKMX2X2TS U3035 ( .A(FPADDSUB_DMP[28]), .B(FPADDSUB_exp_oper_result[5]),
.S0(n2983), .Y(n2856) );
CLKMX2X2TS U3036 ( .A(FPADDSUB_DMP[30]), .B(FPADDSUB_exp_oper_result[7]),
.S0(n2983), .Y(n2874) );
NAND2X2TS U3037 ( .A(n4852), .B(n6730), .Y(n6391) );
CLKMX2X2TS U3038 ( .A(FPADDSUB_DMP[12]), .B(
FPADDSUB_Sgf_normalized_result[14]), .S0(n2970), .Y(n2937) );
CLKMX2X2TS U3039 ( .A(FPADDSUB_DMP[13]), .B(
FPADDSUB_Sgf_normalized_result[15]), .S0(n2970), .Y(n2947) );
CLKMX2X2TS U3040 ( .A(FPADDSUB_DMP[14]), .B(
FPADDSUB_Sgf_normalized_result[16]), .S0(n2970), .Y(n2949) );
CLKMX2X2TS U3041 ( .A(FPADDSUB_DMP[15]), .B(
FPADDSUB_Sgf_normalized_result[17]), .S0(n2970), .Y(n2955) );
CLKINVX1TS U3042 ( .A(n5805), .Y(n5087) );
INVX4TS U3043 ( .A(n5133), .Y(n5183) );
INVX4TS U3044 ( .A(n5133), .Y(n5218) );
INVX4TS U3045 ( .A(n5133), .Y(n5297) );
CLKMX2X2TS U3046 ( .A(n6898), .B(n6897), .S0(n6896), .Y(n1964) );
AO21X2TS U3047 ( .A0(n6868), .A1(n6867), .B0(n6866), .Y(n1845) );
BUFX12TS U3048 ( .A(FPMULT_Op_MX[20]), .Y(n3701) );
NAND2BX1TS U3049 ( .AN(FPADDSUB_intDY[9]), .B(FPADDSUB_intDX[9]), .Y(n5648)
);
CLKMX2X2TS U3050 ( .A(FPMULT_Op_MX[27]), .B(FPMULT_exp_oper_result[4]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[4]) );
CLKMX2X2TS U3051 ( .A(FPMULT_Op_MX[30]), .B(FPMULT_exp_oper_result[7]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[7]) );
NAND2X6TS U3052 ( .A(FPMULT_Op_MX[0]), .B(FPMULT_Op_MX[12]), .Y(n3119) );
BUFX12TS U3053 ( .A(FPMULT_Op_MX[13]), .Y(n6379) );
CLKMX2X2TS U3054 ( .A(FPMULT_Op_MX[29]), .B(FPMULT_exp_oper_result[6]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[6]) );
CLKMX2X2TS U3055 ( .A(FPMULT_Op_MX[28]), .B(FPMULT_exp_oper_result[5]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[5]) );
CLKINVX6TS U3056 ( .A(n4702), .Y(n2161) );
XNOR2X2TS U3057 ( .A(n4948), .B(n4947), .Y(n4949) );
INVX8TS U3058 ( .A(n2684), .Y(n2410) );
MX2X2TS U3059 ( .A(n4957), .B(FPMULT_P_Sgf[28]), .S0(n4922), .Y(n1946) );
INVX8TS U3060 ( .A(n2459), .Y(n4754) );
INVX12TS U3061 ( .A(n4831), .Y(n2133) );
MX2X2TS U3062 ( .A(n4942), .B(FPMULT_P_Sgf[26]), .S0(n4922), .Y(n1944) );
NAND2X1TS U3063 ( .A(n4827), .B(n4826), .Y(n4828) );
NAND2X4TS U3064 ( .A(n2515), .B(n4751), .Y(n4833) );
CLKMX2X2TS U3065 ( .A(n6191), .B(FPMULT_P_Sgf[23]), .S0(n6911), .Y(n1941) );
NAND2X6TS U3066 ( .A(n2439), .B(n2438), .Y(n2442) );
CLKMX2X2TS U3067 ( .A(n4887), .B(FPMULT_P_Sgf[22]), .S0(n6306), .Y(n1940) );
NAND3X4TS U3068 ( .A(n2520), .B(n4289), .C(n2572), .Y(n2655) );
CLKMX2X2TS U3069 ( .A(n4880), .B(FPMULT_P_Sgf[21]), .S0(n6911), .Y(n1939) );
NAND2X6TS U3070 ( .A(n2520), .B(n2450), .Y(n2623) );
CLKMX2X2TS U3071 ( .A(n6318), .B(FPMULT_P_Sgf[20]), .S0(n6910), .Y(n1938) );
CLKMX2X2TS U3072 ( .A(n4871), .B(FPMULT_P_Sgf[19]), .S0(n6910), .Y(n1937) );
NAND2X4TS U3073 ( .A(n2699), .B(n4289), .Y(n2697) );
CLKMX2X2TS U3074 ( .A(n6307), .B(FPMULT_P_Sgf[17]), .S0(n6306), .Y(n1935) );
NAND2X6TS U3075 ( .A(n2422), .B(n2695), .Y(n2618) );
OAI21X1TS U3076 ( .A0(n6312), .A1(n6308), .B0(n6309), .Y(n4870) );
NAND2X4TS U3077 ( .A(n2525), .B(n2524), .Y(n2523) );
INVX12TS U3078 ( .A(n2620), .Y(n4733) );
CLKMX2X2TS U3079 ( .A(n6296), .B(FPMULT_P_Sgf[15]), .S0(n6910), .Y(n1933) );
OR2X4TS U3080 ( .A(n4795), .B(n2206), .Y(n4394) );
NAND2X4TS U3081 ( .A(n2661), .B(n4212), .Y(n2660) );
NAND2X4TS U3082 ( .A(n4295), .B(n2450), .Y(n2637) );
BUFX16TS U3083 ( .A(n2421), .Y(n2396) );
MXI2X2TS U3084 ( .A(FPADDSUB_add_overflow_flag), .B(n2991), .S0(n5969), .Y(
n2836) );
OAI21X1TS U3085 ( .A0(n4757), .A1(n4756), .B0(n4755), .Y(n4763) );
XOR2X2TS U3086 ( .A(n4370), .B(n4369), .Y(n4772) );
NOR2X2TS U3087 ( .A(n1662), .B(n1687), .Y(n6869) );
INVX4TS U3088 ( .A(n4295), .Y(n2670) );
MX2X2TS U3089 ( .A(FPADDSUB_Add_Subt_result[25]), .B(n4864), .S0(n5969), .Y(
n1662) );
XOR2X2TS U3090 ( .A(n4616), .B(n4615), .Y(n4621) );
XNOR2X1TS U3091 ( .A(n4863), .B(n4862), .Y(n4864) );
OAI21X1TS U3092 ( .A0(n4406), .A1(n4347), .B0(n4346), .Y(n4348) );
OAI21X1TS U3093 ( .A0(n4379), .A1(n4378), .B0(n4377), .Y(n4380) );
NOR2X1TS U3094 ( .A(n4397), .B(n4347), .Y(n4349) );
NOR2X1TS U3095 ( .A(n4397), .B(n4405), .Y(n4408) );
INVX6TS U3096 ( .A(n4585), .Y(n4600) );
INVX4TS U3097 ( .A(n2176), .Y(n2511) );
NAND2X6TS U3098 ( .A(n4201), .B(n4200), .Y(n2781) );
NOR2X1TS U3099 ( .A(n4397), .B(n4337), .Y(n4339) );
NOR2X6TS U3100 ( .A(n4496), .B(n4495), .Y(n6289) );
XOR2X1TS U3101 ( .A(n4286), .B(n4285), .Y(n4753) );
XOR2X2TS U3102 ( .A(n4599), .B(n4598), .Y(n4620) );
NOR2X1TS U3103 ( .A(n4375), .B(n4378), .Y(n4381) );
XOR2X2TS U3104 ( .A(n4583), .B(n4582), .Y(n4617) );
AO22X1TS U3105 ( .A0(n5940), .A1(n6524), .B0(n6522), .B1(
FPADDSUB_LZA_output[3]), .Y(n1658) );
AO22X1TS U3106 ( .A0(n5949), .A1(n6524), .B0(n6522), .B1(
FPADDSUB_LZA_output[1]), .Y(n1660) );
CLKMX2X2TS U3107 ( .A(FPADDSUB_Add_Subt_result[22]), .B(n4895), .S0(n5969),
.Y(n1685) );
AO22X1TS U3108 ( .A0(n6524), .A1(n6523), .B0(n6522), .B1(
FPADDSUB_LZA_output[0]), .Y(n1661) );
NAND2X6TS U3109 ( .A(n4128), .B(n4127), .Y(n4569) );
AO22X1TS U3110 ( .A0(n5803), .A1(n6524), .B0(FPADDSUB_LZA_output[2]), .B1(
n6522), .Y(n1659) );
CLKMX2X2TS U3111 ( .A(n6112), .B(FPMULT_Add_result[22]), .S0(n6122), .Y(
n1967) );
OAI21X1TS U3112 ( .A0(n4638), .A1(n4637), .B0(n4636), .Y(n4639) );
NAND4X1TS U3113 ( .A(n6521), .B(n5802), .C(n5801), .D(n5934), .Y(n5803) );
NAND2X6TS U3114 ( .A(n2712), .B(n2711), .Y(n4521) );
NAND2X4TS U3115 ( .A(n2770), .B(n2769), .Y(n4182) );
NAND2X4TS U3116 ( .A(n4126), .B(n4125), .Y(n4533) );
OAI21X1TS U3117 ( .A0(n5939), .A1(n5938), .B0(n5937), .Y(n5940) );
NOR2X1TS U3118 ( .A(n4629), .B(n4637), .Y(n4640) );
NAND4X1TS U3119 ( .A(n6521), .B(n6520), .C(n6519), .D(n6518), .Y(n6523) );
CLKMX2X2TS U3120 ( .A(FPADDSUB_Add_Subt_result[21]), .B(n5970), .S0(n5969),
.Y(n1684) );
AO21X1TS U3121 ( .A0(n5913), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[39]), .B0(n5904),
.Y(n1652) );
BUFX3TS U3122 ( .A(n4323), .Y(n4327) );
OAI21X1TS U3123 ( .A0(n2348), .A1(FPADDSUB_Add_Subt_result[0]), .B0(n5936),
.Y(n5618) );
AO21X1TS U3124 ( .A0(n5549), .A1(n4909), .B0(n4916), .Y(n1848) );
AO21X1TS U3125 ( .A0(n5913), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[40]), .B0(n5907),
.Y(n1651) );
AO21X1TS U3126 ( .A0(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[37]), .A1(n5913), .B0(n5898), .Y(n1654) );
XNOR2X2TS U3127 ( .A(n2608), .B(n3570), .Y(n2607) );
AO21X1TS U3128 ( .A0(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[36]), .A1(n5913), .B0(n5895), .Y(n1655) );
AO21X1TS U3129 ( .A0(n5913), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[38]), .B0(n5901),
.Y(n1653) );
AO21X1TS U3130 ( .A0(n5913), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[41]), .B0(n5912),
.Y(n1650) );
ADDFHX2TS U3131 ( .A(n3603), .B(n3602), .CI(n3601), .CO(n3621), .S(n3596) );
CLKMX2X2TS U3132 ( .A(n6114), .B(FPMULT_Add_result[21]), .S0(n6199), .Y(
n1968) );
CLKINVX6TS U3133 ( .A(n4118), .Y(n2712) );
AOI211X1TS U3134 ( .A0(n2348), .A1(n5936), .B0(n5935), .C0(n6514), .Y(n5937)
);
OAI21X1TS U3135 ( .A0(n6262), .A1(n6261), .B0(n6260), .Y(n6267) );
AO21X1TS U3136 ( .A0(n5546), .A1(n4909), .B0(n4921), .Y(n1656) );
CLKMX2X2TS U3137 ( .A(FPADDSUB_Add_Subt_result[14]), .B(n6073), .S0(n5979),
.Y(n1677) );
CLKMX2X2TS U3138 ( .A(FPADDSUB_Add_Subt_result[20]), .B(n5986), .S0(n6036),
.Y(n1683) );
AO21X1TS U3139 ( .A0(n5576), .A1(n4909), .B0(n5012), .Y(n1644) );
CLKMX2X2TS U3140 ( .A(FPADDSUB_Add_Subt_result[19]), .B(n6006), .S0(n6036),
.Y(n1682) );
OAI211X1TS U3141 ( .A0(n5911), .A1(n6800), .B0(n5906), .C0(n5905), .Y(n5907)
);
OAI211X1TS U3142 ( .A0(n5911), .A1(n6797), .B0(n5897), .C0(n5896), .Y(n5898)
);
CLKMX2X2TS U3143 ( .A(n6116), .B(FPMULT_Add_result[20]), .S0(n6122), .Y(
n1969) );
CLKMX2X2TS U3144 ( .A(n5927), .B(FPADDSUB_exp_oper_result[7]), .S0(n2213),
.Y(n1690) );
OAI211X1TS U3145 ( .A0(n5911), .A1(n6802), .B0(n5900), .C0(n5899), .Y(n5901)
);
OAI211X1TS U3146 ( .A0(n5911), .A1(n6798), .B0(n5894), .C0(n5893), .Y(n5895)
);
OAI211X1TS U3147 ( .A0(n5891), .A1(n6808), .B0(n4920), .C0(n4919), .Y(n4921)
);
XNOR2X1TS U3148 ( .A(DP_OP_134J305_123_859_n1), .B(n5859), .Y(
FPMULT_Exp_module_Overflow_A) );
OAI211X1TS U3149 ( .A0(n5537), .A1(n5580), .B0(n5011), .C0(n5010), .Y(n5012)
);
NAND2X1TS U3150 ( .A(n4284), .B(n4313), .Y(n4285) );
NAND2X2TS U3151 ( .A(n2562), .B(n2785), .Y(n2561) );
CLKMX2X2TS U3152 ( .A(FPADDSUB_Add_Subt_result[13]), .B(n6082), .S0(n5979),
.Y(n1676) );
OAI211X1TS U3153 ( .A0(n5891), .A1(n6807), .B0(n4915), .C0(n4919), .Y(n4916)
);
NAND2X4TS U3154 ( .A(n2417), .B(n2416), .Y(n2608) );
CLKMX2X2TS U3155 ( .A(FPADDSUB_Add_Subt_result[12]), .B(n6093), .S0(n5979),
.Y(n1675) );
NAND2X1TS U3156 ( .A(n4518), .B(n4553), .Y(n4519) );
CLKMX2X2TS U3157 ( .A(FPADDSUB_Add_Subt_result[10]), .B(n6054), .S0(n5979),
.Y(n1673) );
INVX4TS U3158 ( .A(n4453), .Y(n2685) );
NAND3BX1TS U3159 ( .AN(FPMULT_Exp_module_Data_S[7]), .B(n7012), .C(n4889),
.Y(n7000) );
CLKMX2X2TS U3160 ( .A(n5928), .B(FPADDSUB_exp_oper_result[6]), .S0(n2213),
.Y(n1697) );
OAI21X1TS U3161 ( .A0(n6232), .A1(n6231), .B0(n6230), .Y(n6237) );
CLKMX2X2TS U3162 ( .A(FPADDSUB_Add_Subt_result[11]), .B(n6077), .S0(n5979),
.Y(n1674) );
ADDFHX2TS U3163 ( .A(n3989), .B(n3988), .CI(n3987), .CO(n4030), .S(n4119) );
CLKMX2X2TS U3164 ( .A(n6118), .B(FPMULT_Add_result[19]), .S0(n6199), .Y(
n1970) );
NAND2X4TS U3165 ( .A(n2499), .B(n2497), .Y(n3991) );
NAND4BX1TS U3166 ( .AN(n4888), .B(FPMULT_Exp_module_Data_S[6]), .C(
FPMULT_Exp_module_Data_S[5]), .D(FPMULT_Exp_module_Data_S[4]), .Y(
n4889) );
CLKMX2X2TS U3167 ( .A(FPMULT_exp_oper_result[6]), .B(
FPMULT_Exp_module_Data_S[6]), .S0(n6999), .Y(n1908) );
CLKMX2X2TS U3168 ( .A(n6120), .B(FPMULT_Add_result[18]), .S0(n6122), .Y(
n1971) );
CLKMX2X2TS U3169 ( .A(FPADDSUB_Add_Subt_result[9]), .B(n6044), .S0(n5979),
.Y(n1672) );
OAI211X1TS U3170 ( .A0(n5252), .A1(n5523), .B0(n5522), .C0(n5521), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[7]) );
OAI21X1TS U3171 ( .A0(n6741), .A1(n5777), .B0(n5776), .Y(n1301) );
OAI21X1TS U3172 ( .A0(n6682), .A1(n5777), .B0(n5748), .Y(n1230) );
OAI21X1TS U3173 ( .A0(n6685), .A1(n5777), .B0(n5756), .Y(n1327) );
OAI21X1TS U3174 ( .A0(n6748), .A1(n5713), .B0(n5698), .Y(n1228) );
OAI21X1TS U3175 ( .A0(n6760), .A1(n5742), .B0(n5734), .Y(n1324) );
OAI21X1TS U3176 ( .A0(n6741), .A1(n2825), .B0(n5711), .Y(n1216) );
OAI21X1TS U3177 ( .A0(n6740), .A1(n5742), .B0(n5739), .Y(n1321) );
OAI21X1TS U3178 ( .A0(n6721), .A1(n5777), .B0(n5764), .Y(n1285) );
OAI21X1TS U3179 ( .A0(n6756), .A1(n5746), .B0(n5744), .Y(n1272) );
OAI21X1TS U3180 ( .A0(n6743), .A1(n5773), .B0(n5772), .Y(n1269) );
OAI21X1TS U3181 ( .A0(n6683), .A1(n5773), .B0(n5757), .Y(n1261) );
OAI21X1TS U3182 ( .A0(n6678), .A1(n5742), .B0(n5741), .Y(n1318) );
NAND4X1TS U3183 ( .A(n5926), .B(n5918), .C(n5917), .D(n5916), .Y(n1649) );
OAI21X1TS U3184 ( .A0(n6753), .A1(n5742), .B0(n5736), .Y(n1315) );
OAI21X1TS U3185 ( .A0(n6739), .A1(n5742), .B0(n5731), .Y(n1312) );
OAI21X1TS U3186 ( .A0(n6745), .A1(n5742), .B0(n5738), .Y(n1309) );
OAI21X1TS U3187 ( .A0(n6762), .A1(n5742), .B0(n5732), .Y(n1306) );
OAI21X1TS U3188 ( .A0(n6760), .A1(n5713), .B0(n5712), .Y(n1325) );
OAI21X1TS U3189 ( .A0(n6749), .A1(n5742), .B0(n5733), .Y(n1233) );
OAI211X1TS U3190 ( .A0(n5595), .A1(n5585), .B0(n5261), .C0(n5260), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[13]) );
CLKMX2X2TS U3191 ( .A(n5929), .B(FPADDSUB_exp_oper_result[5]), .S0(n2213),
.Y(n1696) );
OAI21X2TS U3192 ( .A0(n4553), .A1(n4552), .B0(n4551), .Y(n4554) );
OAI21X1TS U3193 ( .A0(n6751), .A1(n5742), .B0(n5735), .Y(n1307) );
OAI211X1TS U3194 ( .A0(n5523), .A1(n5585), .B0(n5273), .C0(n5272), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[5]) );
OAI21X1TS U3195 ( .A0(n6663), .A1(n5777), .B0(n5762), .Y(n1298) );
NAND4X1TS U3196 ( .A(n5926), .B(n5925), .C(n5924), .D(n5923), .Y(n1648) );
OAI21X1TS U3197 ( .A0(n6746), .A1(n5777), .B0(n5761), .Y(n1292) );
OAI211X1TS U3198 ( .A0(n6797), .A1(n5592), .B0(n5539), .C0(n5538), .Y(n1638)
);
OAI211X1TS U3199 ( .A0(n5252), .A1(n5518), .B0(n5517), .C0(n5516), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[11]) );
OAI21X1TS U3200 ( .A0(n6744), .A1(n5773), .B0(n5767), .Y(n1258) );
OAI211X1TS U3201 ( .A0(n5592), .A1(n6799), .B0(n5554), .C0(n5553), .Y(n1636)
);
CLKMX2X2TS U3202 ( .A(n2350), .B(n6001), .S0(n6036), .Y(n1669) );
OAI211X1TS U3203 ( .A0(n5592), .A1(n6800), .B0(n5591), .C0(n5590), .Y(n1635)
);
OAI211X1TS U3204 ( .A0(n6798), .A1(n5592), .B0(n5542), .C0(n5541), .Y(n1639)
);
OAI211X1TS U3205 ( .A0(n5592), .A1(n6801), .B0(n5557), .C0(n5556), .Y(n1634)
);
OAI21X1TS U3206 ( .A0(n5742), .A1(n6679), .B0(n5727), .Y(n1215) );
OAI21X1TS U3207 ( .A0(n6748), .A1(n5746), .B0(n5745), .Y(n1237) );
OAI211X1TS U3208 ( .A0(n5595), .A1(n5257), .B0(n5488), .C0(n5487), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[12]) );
OAI211X1TS U3209 ( .A0(n5518), .A1(n2199), .B0(n5478), .C0(n5477), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[10]) );
OAI21X1TS U3210 ( .A0(n6684), .A1(n5773), .B0(n5750), .Y(n1240) );
OAI21X1TS U3211 ( .A0(n6747), .A1(n5773), .B0(n5763), .Y(n1244) );
OAI21X1TS U3212 ( .A0(n6755), .A1(n5773), .B0(n5766), .Y(n1247) );
OAI21X1TS U3213 ( .A0(n6761), .A1(n5773), .B0(n5752), .Y(n1251) );
ADDFHX2TS U3214 ( .A(n4110), .B(n4109), .CI(n4108), .CO(n3988), .S(n4123) );
CLKMX2X2TS U3215 ( .A(FPADDSUB_Add_Subt_result[8]), .B(n6029), .S0(n6036),
.Y(n1671) );
OAI21X1TS U3216 ( .A0(n6664), .A1(n5773), .B0(n5759), .Y(n1254) );
OAI21X1TS U3217 ( .A0(n6681), .A1(n5773), .B0(n5753), .Y(n1275) );
OAI21X1TS U3218 ( .A0(n6742), .A1(n5777), .B0(n5769), .Y(n1282) );
OAI21X1TS U3219 ( .A0(n6661), .A1(n5777), .B0(n5768), .Y(n1278) );
CLKMX2X2TS U3220 ( .A(FPMULT_exp_oper_result[5]), .B(
FPMULT_Exp_module_Data_S[5]), .S0(n6999), .Y(n1909) );
OAI21X1TS U3221 ( .A0(n6721), .A1(n5749), .B0(n5697), .Y(n1220) );
OAI21X1TS U3222 ( .A0(n5746), .A1(n6769), .B0(n5717), .Y(n1227) );
OAI211X1TS U3223 ( .A0(n5603), .A1(n5257), .B0(n5598), .C0(n5597), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[16]) );
OAI211X1TS U3224 ( .A0(n5523), .A1(n5257), .B0(n5486), .C0(n5485), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[4]) );
OAI21X1TS U3225 ( .A0(n6745), .A1(n2825), .B0(n5693), .Y(n1310) );
NAND2X2TS U3226 ( .A(n2678), .B(n2677), .Y(n2676) );
INVX6TS U3227 ( .A(n4447), .Y(n3222) );
INVX4TS U3228 ( .A(n5726), .Y(n5742) );
OAI21X1TS U3229 ( .A0(n6739), .A1(n5713), .B0(n5692), .Y(n1313) );
OAI21X1TS U3230 ( .A0(n6753), .A1(n5713), .B0(n5691), .Y(n1316) );
OAI211X1TS U3231 ( .A0(n5595), .A1(n2199), .B0(n5476), .C0(n5475), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[14]) );
OAI211X1TS U3232 ( .A0(n5529), .A1(n5585), .B0(n5286), .C0(n5285), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[1]) );
OAI211X1TS U3233 ( .A0(n5252), .A1(n5595), .B0(n5594), .C0(n5593), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[15]) );
OAI21X1TS U3234 ( .A0(n6678), .A1(n5713), .B0(n5702), .Y(n1319) );
OAI21X1TS U3235 ( .A0(n5746), .A1(n6786), .B0(n5723), .Y(n1229) );
OAI21X1TS U3236 ( .A0(n6740), .A1(n5713), .B0(n5690), .Y(n1322) );
OAI21X1TS U3237 ( .A0(n6761), .A1(n2825), .B0(n5700), .Y(n1250) );
OAI21X1TS U3238 ( .A0(n5746), .A1(n6783), .B0(n5718), .Y(n1225) );
INVX4TS U3239 ( .A(n3561), .Y(n2138) );
INVX4TS U3240 ( .A(n5726), .Y(n5773) );
OAI21X1TS U3241 ( .A0(n5746), .A1(n6770), .B0(n5722), .Y(n1224) );
AOI31X1TS U3242 ( .A0(n2350), .A1(n6515), .A2(n6766), .B0(n6514), .Y(n6519)
);
OAI21X1TS U3243 ( .A0(n5706), .A1(n6788), .B0(n5725), .Y(n1222) );
OAI21X1TS U3244 ( .A0(n5746), .A1(n6785), .B0(n5720), .Y(n1219) );
OAI211X1TS U3245 ( .A0(n5603), .A1(n5585), .B0(n5584), .C0(n5583), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[17]) );
OAI21X1TS U3246 ( .A0(n5706), .A1(n6789), .B0(n5730), .Y(n1218) );
OAI211X1TS U3247 ( .A0(n5529), .A1(n5257), .B0(n5497), .C0(n5496), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[0]) );
OAI21X1TS U3248 ( .A0(n5746), .A1(n6782), .B0(n5721), .Y(n1217) );
OAI211X1TS U3249 ( .A0(n5592), .A1(n6707), .B0(n5548), .C0(n5547), .Y(n1633)
);
OAI21X1TS U3250 ( .A0(n6749), .A1(n2825), .B0(n5703), .Y(n1234) );
OAI21X1TS U3251 ( .A0(n4708), .A1(n4721), .B0(n4709), .Y(n4271) );
NOR2X1TS U3252 ( .A(n4708), .B(n4720), .Y(n4272) );
ADDFHX2TS U3253 ( .A(n4100), .B(n4099), .CI(n4098), .CO(n4116), .S(n4101) );
XOR2X2TS U3254 ( .A(n3631), .B(n2465), .Y(n3639) );
OAI21X1TS U3255 ( .A0(n6747), .A1(n2825), .B0(n5695), .Y(n1243) );
INVX6TS U3256 ( .A(n4516), .Y(n3412) );
OAI21X1TS U3257 ( .A0(n6744), .A1(n5749), .B0(n5696), .Y(n1257) );
OAI211X1TS U3258 ( .A0(n5518), .A1(n5585), .B0(n5296), .C0(n5295), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[9]) );
OAI21X1TS U3259 ( .A0(n6722), .A1(n2825), .B0(n5686), .Y(n1264) );
NAND3BX1TS U3260 ( .AN(n5708), .B(n5726), .C(n5707), .Y(n5709) );
OAI21X1TS U3261 ( .A0(n6743), .A1(n2825), .B0(n5689), .Y(n1268) );
OAI21X1TS U3262 ( .A0(n6742), .A1(n5713), .B0(n5688), .Y(n1281) );
OAI21X1TS U3263 ( .A0(n6746), .A1(n5749), .B0(n5687), .Y(n1291) );
OAI21X1TS U3264 ( .A0(n6661), .A1(n5713), .B0(n5699), .Y(n1221) );
OAI21X1TS U3265 ( .A0(n6679), .A1(n5713), .B0(n5704), .Y(n1304) );
OAI211X1TS U3266 ( .A0(n5252), .A1(n5529), .B0(n5528), .C0(n5527), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[3]) );
OAI21X1TS U3267 ( .A0(n6685), .A1(n5713), .B0(n5701), .Y(n1328) );
OAI211X1TS U3268 ( .A0(n6794), .A1(n5891), .B0(n5575), .C0(n5574), .Y(n1640)
);
OAI211X1TS U3269 ( .A0(n5529), .A1(n2199), .B0(n5480), .C0(n5479), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[2]) );
AO21X1TS U3270 ( .A0(FPADDSUB_Sgf_normalized_result[3]), .A1(n5587), .B0(
n5586), .Y(n5588) );
XOR2X2TS U3271 ( .A(n3630), .B(n3632), .Y(n2465) );
OAI211X1TS U3272 ( .A0(n5891), .A1(n6797), .B0(n5564), .C0(n5563), .Y(n1646)
);
OAI211X1TS U3273 ( .A0(n5532), .A1(n6348), .B0(n5531), .C0(n5530), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[20]) );
AOI2BB2X1TS U3274 ( .B0(n6609), .B1(n6608), .A0N(FPSENCOS_d_ff3_sh_y_out[29]), .A1N(n6612), .Y(n1415) );
NAND3X1TS U3275 ( .A(n6636), .B(n6635), .C(n6640), .Y(n1339) );
OAI211X1TS U3276 ( .A0(n5374), .A1(n6837), .B0(n5151), .C0(n5150), .Y(n1283)
);
OAI211X1TS U3277 ( .A0(n5386), .A1(n6844), .B0(n5385), .C0(n5384), .Y(n1255)
);
OAI211X1TS U3278 ( .A0(n5380), .A1(n6851), .B0(n5153), .C0(n5152), .Y(n1231)
);
OR2X2TS U3279 ( .A(n4263), .B(n4262), .Y(n2823) );
AO22X1TS U3280 ( .A0(n5922), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[45]), .B0(
FPADDSUB_Sgf_normalized_result[11]), .B1(n5573), .Y(n5019) );
OR2X2TS U3281 ( .A(n4260), .B(n4261), .Y(n2822) );
OR2X2TS U3282 ( .A(n4257), .B(n4258), .Y(n2821) );
OAI211X1TS U3283 ( .A0(n5386), .A1(n6843), .B0(n5354), .C0(n5353), .Y(n1259)
);
OAI211X1TS U3284 ( .A0(n5380), .A1(n6481), .B0(n5320), .C0(n5319), .Y(n1232)
);
OAI211X1TS U3285 ( .A0(n5386), .A1(n6486), .B0(n5362), .C0(n5361), .Y(n1263)
);
AO22X1TS U3286 ( .A0(n5922), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[44]), .B0(
FPADDSUB_Sgf_normalized_result[10]), .B1(n5573), .Y(n5015) );
AO22X1TS U3287 ( .A0(n6563), .A1(n5047), .B0(n6472), .B1(
FPSENCOS_d_ff3_sh_x_out[30]), .Y(n1785) );
OAI211X1TS U3288 ( .A0(n5252), .A1(n5603), .B0(n5513), .C0(n5512), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[19]) );
OAI211X1TS U3289 ( .A0(n6665), .A1(n5406), .B0(n5302), .C0(n5301), .Y(n1323)
);
OAI211X1TS U3290 ( .A0(n5374), .A1(n6840), .B0(n5356), .C0(n5355), .Y(n1270)
);
OAI211X1TS U3291 ( .A0(n5603), .A1(n2199), .B0(n5602), .C0(n5601), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[18]) );
XOR2X2TS U3292 ( .A(n4233), .B(n2736), .Y(n4237) );
OAI21X1TS U3293 ( .A0(n5608), .A1(n5607), .B0(n5606), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[21]) );
OAI211X1TS U3294 ( .A0(n6794), .A1(n5592), .B0(n5551), .C0(n5550), .Y(n1632)
);
OAI211X1TS U3295 ( .A0(n5386), .A1(n6846), .B0(n5349), .C0(n5348), .Y(n1248)
);
OAI211X1TS U3296 ( .A0(n5380), .A1(n6849), .B0(n5376), .C0(n5375), .Y(n1238)
);
OAI211X1TS U3297 ( .A0(n6708), .A1(n5406), .B0(n5388), .C0(n5387), .Y(n1326)
);
OAI211X1TS U3298 ( .A0(n5352), .A1(n6484), .B0(n5312), .C0(n5311), .Y(n1300)
);
OAI211X1TS U3299 ( .A0(n5386), .A1(n6480), .B0(n5338), .C0(n5337), .Y(n1249)
);
OAI211X1TS U3300 ( .A0(n5380), .A1(n6848), .B0(n5379), .C0(n5378), .Y(n1241)
);
OAI211X1TS U3301 ( .A0(n5581), .A1(n5580), .B0(n5579), .C0(n5578), .Y(n1645)
);
OAI211X1TS U3302 ( .A0(n5386), .A1(n6842), .B0(n5360), .C0(n5359), .Y(n1262)
);
AO21X1TS U3303 ( .A0(FPADDSUB_Sgf_normalized_result[6]), .A1(n5587), .B0(
n5586), .Y(n5536) );
OAI211X1TS U3304 ( .A0(n5380), .A1(n6478), .B0(n5308), .C0(n5307), .Y(n1236)
);
AO21X1TS U3305 ( .A0(FPADDSUB_Sgf_normalized_result[7]), .A1(n5587), .B0(
n5586), .Y(n5540) );
OAI211X1TS U3306 ( .A0(n6706), .A1(n5406), .B0(n5392), .C0(n5391), .Y(n1320)
);
ADDFHX2TS U3307 ( .A(n3147), .B(n3146), .CI(n3145), .CO(n3356), .S(n3307) );
AO21X1TS U3308 ( .A0(FPADDSUB_Sgf_normalized_result[5]), .A1(n5587), .B0(
n5586), .Y(n5543) );
ADDFHX2TS U3309 ( .A(n4057), .B(n4056), .CI(n4055), .CO(n4109), .S(n4105) );
OAI211X1TS U3310 ( .A0(n5380), .A1(n6850), .B0(n5368), .C0(n5367), .Y(n1235)
);
NAND3X1TS U3311 ( .A(n6634), .B(n6633), .C(n6640), .Y(n1340) );
OAI211X1TS U3312 ( .A0(n5380), .A1(n6479), .B0(n5318), .C0(n5317), .Y(n1239)
);
AOI2BB2X1TS U3313 ( .B0(n6609), .B1(n6463), .A0N(FPSENCOS_d_ff3_sh_x_out[29]), .A1N(n6612), .Y(n1786) );
OAI21X2TS U3314 ( .A0(n3340), .A1(n3339), .B0(n3338), .Y(n2367) );
AO22X1TS U3315 ( .A0(n6612), .A1(n6611), .B0(n6616), .B1(
FPSENCOS_d_ff3_sh_y_out[30]), .Y(n1414) );
NAND3X1TS U3316 ( .A(n6642), .B(n6641), .C(n6640), .Y(n1338) );
OAI211X1TS U3317 ( .A0(n5386), .A1(n6473), .B0(n5345), .C0(n5344), .Y(n1260)
);
AO21X1TS U3318 ( .A0(FPADDSUB_Sgf_normalized_result[2]), .A1(n5587), .B0(
n5586), .Y(n5555) );
INVX2TS U3319 ( .A(n4597), .Y(n2677) );
CLKMX2X2TS U3320 ( .A(n5931), .B(FPADDSUB_exp_oper_result[3]), .S0(n2212),
.Y(n1694) );
OAI211X1TS U3321 ( .A0(n5374), .A1(n6838), .B0(n5155), .C0(n5154), .Y(n1279)
);
OAI21X1TS U3322 ( .A0(n5995), .A1(n5994), .B0(n5993), .Y(n6000) );
OAI211X1TS U3323 ( .A0(n5386), .A1(n6474), .B0(n5366), .C0(n5365), .Y(n1253)
);
AO21X1TS U3324 ( .A0(FPADDSUB_Sgf_normalized_result[4]), .A1(n5587), .B0(
n5586), .Y(n5552) );
OAI211X1TS U3325 ( .A0(n5891), .A1(n6798), .B0(n5561), .C0(n5560), .Y(n1647)
);
OAI211X1TS U3326 ( .A0(n5380), .A1(n6476), .B0(n5336), .C0(n5335), .Y(n1246)
);
AO22X1TS U3327 ( .A0(n6617), .A1(n5038), .B0(n6558), .B1(
FPSENCOS_d_ff3_sh_y_out[28]), .Y(n1416) );
AOI2BB2X1TS U3328 ( .B0(n6609), .B1(n6458), .A0N(FPSENCOS_d_ff3_sh_x_out[27]), .A1N(n6612), .Y(n1788) );
AO22X1TS U3329 ( .A0(n6617), .A1(n6460), .B0(n6562), .B1(
FPSENCOS_d_ff3_sh_x_out[28]), .Y(n1787) );
NAND2X6TS U3330 ( .A(n2479), .B(n2478), .Y(n2436) );
OAI211X1TS U3331 ( .A0(n5374), .A1(n6839), .B0(n5159), .C0(n5158), .Y(n1276)
);
OAI211X1TS U3332 ( .A0(n2795), .A1(n5410), .B0(n5330), .C0(n5329), .Y(n1299)
);
AOI2BB2X1TS U3333 ( .B0(n6609), .B1(n6606), .A0N(FPSENCOS_d_ff3_sh_y_out[27]), .A1N(n6612), .Y(n1417) );
AO22X1TS U3334 ( .A0(n5888), .A1(n5282), .B0(n5294), .B1(n5277), .Y(n2193)
);
OAI211X1TS U3335 ( .A0(n5352), .A1(n6836), .B0(n5328), .C0(n5327), .Y(n1289)
);
OAI211X1TS U3336 ( .A0(n5374), .A1(n6482), .B0(n5169), .C0(n5168), .Y(n1277)
);
OAI211X1TS U3337 ( .A0(n6451), .A1(n5410), .B0(n5332), .C0(n5331), .Y(n1342)
);
OAI211X1TS U3338 ( .A0(n5406), .A1(n6465), .B0(n5147), .C0(n5146), .Y(n1303)
);
OAI211X1TS U3339 ( .A0(n5352), .A1(n6470), .B0(n5149), .C0(n5148), .Y(n1284)
);
OAI211X1TS U3340 ( .A0(n6832), .A1(n5410), .B0(n5121), .C0(n5120), .Y(n1335)
);
OAI211X1TS U3341 ( .A0(n5352), .A1(n6468), .B0(n5316), .C0(n5315), .Y(n1294)
);
OAI211X1TS U3342 ( .A0(n5406), .A1(n6687), .B0(n5127), .C0(n5126), .Y(n1311)
);
OAI211X1TS U3343 ( .A0(n5352), .A1(n6466), .B0(n5310), .C0(n5309), .Y(n1287)
);
OAI211X1TS U3344 ( .A0(n5406), .A1(n6495), .B0(n5212), .C0(n5211), .Y(n1305)
);
OAI211X1TS U3345 ( .A0(n5374), .A1(n6477), .B0(n5343), .C0(n5342), .Y(n1267)
);
OAI211X1TS U3346 ( .A0(n5406), .A1(n6795), .B0(n5405), .C0(n5404), .Y(n1308)
);
ADDFHX2TS U3347 ( .A(n3787), .B(n3786), .CI(n3785), .CO(n3718), .S(n3869) );
OAI211X1TS U3348 ( .A0(n6422), .A1(n5410), .B0(n5409), .C0(n5408), .Y(n1337)
);
OAI211X1TS U3349 ( .A0(n5410), .A1(n6425), .B0(n5123), .C0(n5122), .Y(n1336)
);
OAI211X1TS U3350 ( .A0(n5406), .A1(n6709), .B0(n5129), .C0(n5128), .Y(n1317)
);
OAI211X1TS U3351 ( .A0(n5386), .A1(n6845), .B0(n5306), .C0(n5305), .Y(n1252)
);
OAI211X1TS U3352 ( .A0(n5162), .A1(n5873), .B0(n5161), .C0(n5160), .Y(n1286)
);
AOI32X2TS U3353 ( .A0(n5280), .A1(n6351), .A2(n5279), .B0(n5278), .B1(n6348),
.Y(n5491) );
OAI21X1TS U3354 ( .A0(n4233), .A1(n2737), .B0(n4232), .Y(n2735) );
OAI211X1TS U3355 ( .A0(n5873), .A1(n6427), .B0(n5125), .C0(n5124), .Y(n1334)
);
ADDFHX2TS U3356 ( .A(n3710), .B(n3709), .CI(n3708), .CO(n3713), .S(n3813) );
OAI211X1TS U3357 ( .A0(n5352), .A1(n6833), .B0(n5322), .C0(n5321), .Y(n1302)
);
AO22X1TS U3358 ( .A0(n5508), .A1(n5291), .B0(n5474), .B1(n5277), .Y(n2195)
);
OAI211X1TS U3359 ( .A0(n5386), .A1(n6487), .B0(n5334), .C0(n5333), .Y(n1256)
);
ADDFHX2TS U3360 ( .A(n3583), .B(n3582), .CI(n3581), .CO(n4614), .S(n4597) );
OAI211X1TS U3361 ( .A0(n5374), .A1(n6475), .B0(n5157), .C0(n5156), .Y(n1280)
);
INVX6TS U3362 ( .A(n4335), .Y(n3516) );
OAI211X1TS U3363 ( .A0(n5374), .A1(n6493), .B0(n5164), .C0(n5163), .Y(n1274)
);
OAI211X1TS U3364 ( .A0(n6447), .A1(n5410), .B0(n5166), .C0(n5165), .Y(n1273)
);
OAI211X1TS U3365 ( .A0(n5352), .A1(n6489), .B0(n5314), .C0(n5313), .Y(n1290)
);
BUFX3TS U3366 ( .A(n6528), .Y(n6508) );
OAI21X2TS U3367 ( .A0(n6210), .A1(n6257), .B0(n6211), .Y(n6217) );
AO21X1TS U3368 ( .A0(FPSENCOS_d_ff3_LUT_out[11]), .A1(n6469), .B0(n6443),
.Y(n1813) );
AO21X1TS U3369 ( .A0(FPSENCOS_d_ff3_LUT_out[7]), .A1(n6469), .B0(n6443), .Y(
n1809) );
OAI31XLTS U3370 ( .A0(n5132), .A1(n5100), .A2(n6637), .B0(n5099), .Y(n1331)
);
OAI21X1TS U3371 ( .A0(n6459), .A1(n6665), .B0(n6462), .Y(n6460) );
OAI21X2TS U3372 ( .A0(n5961), .A1(n2910), .B0(n2909), .Y(n6013) );
AOI32X1TS U3373 ( .A0(n6351), .A1(n2300), .A2(n6346), .B0(n5604), .B1(n2300),
.Y(n5512) );
NOR2X1TS U3374 ( .A(n6348), .B(n2301), .Y(n6343) );
CLKAND2X2TS U3375 ( .A(n3229), .B(n2236), .Y(n4235) );
AND2X2TS U3376 ( .A(n5577), .B(n5568), .Y(n5018) );
AO22X1TS U3377 ( .A0(FPSENCOS_d_ff_Yn[30]), .A1(n6596), .B0(n6595), .B1(
FPSENCOS_d_ff2_Y[30]), .Y(n1422) );
OR2X2TS U3378 ( .A(n5535), .B(n5534), .Y(n5571) );
ADDFHX2TS U3379 ( .A(n4084), .B(n4083), .CI(n4082), .CO(n4076), .S(n4090) );
ADDFHX2TS U3380 ( .A(n3505), .B(n3504), .CI(n3503), .CO(n3545), .S(n3511) );
AOI31X1TS U3381 ( .A0(n5425), .A1(n5424), .A2(n6408), .B0(n5423), .Y(n1840)
);
INVX6TS U3382 ( .A(n4436), .Y(n2139) );
AO22X1TS U3383 ( .A0(FPSENCOS_d_ff_Xn[31]), .A1(n6596), .B0(
FPSENCOS_d_ff2_X[31]), .B1(n6595), .Y(n1842) );
AO22X1TS U3384 ( .A0(FPSENCOS_d_ff_Yn[27]), .A1(n6596), .B0(n6595), .B1(
FPSENCOS_d_ff2_Y[27]), .Y(n1425) );
AO22X1TS U3385 ( .A0(n2293), .A1(FPADDSUB_Add_Subt_result[19]), .B0(
FPADDSUB_DmP[4]), .B1(n5472), .Y(n5265) );
AO22X1TS U3386 ( .A0(FPMULT_Sgf_normalized_result[19]), .A1(n6400), .B0(
mult_result[19]), .B1(n6401), .Y(n1853) );
AO22X1TS U3387 ( .A0(n2292), .A1(FPADDSUB_Add_Subt_result[12]), .B0(
FPADDSUB_DmP[11]), .B1(n5270), .Y(n5253) );
AO22X1TS U3388 ( .A0(n6617), .A1(n6603), .B0(n6602), .B1(
FPSENCOS_d_ff3_sh_y_out[26]), .Y(n1418) );
OAI32X4TS U3389 ( .A0(n4851), .A1(n4850), .A2(n4963), .B0(n5241), .B1(n4851),
.Y(n6205) );
NAND2X4TS U3390 ( .A(n2378), .B(n2377), .Y(n2376) );
AO22X1TS U3391 ( .A0(FPMULT_Sgf_normalized_result[20]), .A1(n6400), .B0(
mult_result[20]), .B1(n6401), .Y(n1852) );
AO22X1TS U3392 ( .A0(n2293), .A1(FPADDSUB_Add_Subt_result[21]), .B0(
FPADDSUB_DmP[2]), .B1(n5472), .Y(n5281) );
INVX2TS U3393 ( .A(n6039), .Y(n6040) );
AO22X1TS U3394 ( .A0(n6617), .A1(n6456), .B0(n6602), .B1(
FPSENCOS_d_ff3_sh_x_out[26]), .Y(n1789) );
AO22X1TS U3395 ( .A0(FPMULT_Sgf_normalized_result[21]), .A1(n6400), .B0(
mult_result[21]), .B1(n6401), .Y(n1851) );
INVX2TS U3396 ( .A(n2263), .Y(n2514) );
AO22X1TS U3397 ( .A0(FPMULT_Sgf_normalized_result[22]), .A1(n6400), .B0(
mult_result[22]), .B1(n6401), .Y(n1850) );
AO22X1TS U3398 ( .A0(FPMULT_Sgf_normalized_result[6]), .A1(n6398), .B0(
mult_result[6]), .B1(n6406), .Y(n1866) );
AO22X1TS U3399 ( .A0(FPMULT_Sgf_normalized_result[5]), .A1(n6395), .B0(
mult_result[5]), .B1(n6406), .Y(n1867) );
AO22X1TS U3400 ( .A0(FPMULT_Sgf_normalized_result[7]), .A1(n6398), .B0(
mult_result[7]), .B1(n6406), .Y(n1865) );
OAI32X1TS U3401 ( .A0(n5074), .A1(n5021), .A2(n6772), .B0(n6507), .B1(n5075),
.Y(n1704) );
AO22X1TS U3402 ( .A0(FPMULT_Sgf_normalized_result[8]), .A1(n6398), .B0(
mult_result[8]), .B1(n6399), .Y(n1864) );
AO22X1TS U3403 ( .A0(FPMULT_Sgf_normalized_result[4]), .A1(n6395), .B0(
mult_result[4]), .B1(n6406), .Y(n1868) );
OAI211X1TS U3404 ( .A0(n5399), .A1(n5424), .B0(n5398), .C0(n5397), .Y(n1841)
);
NOR3X1TS U3405 ( .A(n6584), .B(n5110), .C(n5108), .Y(n1837) );
AO22X1TS U3406 ( .A0(FPMULT_Sgf_normalized_result[3]), .A1(n6395), .B0(
mult_result[3]), .B1(n6401), .Y(n1869) );
AO22X1TS U3407 ( .A0(FPMULT_Sgf_normalized_result[9]), .A1(n6398), .B0(
mult_result[9]), .B1(n6406), .Y(n1863) );
AOI221X1TS U3408 ( .A0(FPSENCOS_cont_var_out[1]), .A1(n5110), .B0(n6677),
.B1(n5109), .C0(n6585), .Y(n1836) );
AO22X1TS U3409 ( .A0(n6400), .A1(FPMULT_Sgf_normalized_result[2]), .B0(
mult_result[2]), .B1(n6401), .Y(n1870) );
AO22X1TS U3410 ( .A0(FPMULT_Sgf_normalized_result[10]), .A1(n6398), .B0(
mult_result[10]), .B1(n6399), .Y(n1862) );
OAI21X1TS U3411 ( .A0(n6594), .A1(n5240), .B0(n5204), .Y(n1352) );
AO22X1TS U3412 ( .A0(FPMULT_Sgf_normalized_result[11]), .A1(n6398), .B0(
mult_result[11]), .B1(n6399), .Y(n1861) );
OAI21X1TS U3413 ( .A0(n6591), .A1(n5240), .B0(n5208), .Y(n1354) );
OAI21X1TS U3414 ( .A0(n6830), .A1(n5240), .B0(n5186), .Y(n1356) );
AO22X1TS U3415 ( .A0(n6400), .A1(FPMULT_Sgf_normalized_result[1]), .B0(
mult_result[1]), .B1(n6401), .Y(n1871) );
AO22X1TS U3416 ( .A0(FPMULT_Sgf_normalized_result[12]), .A1(n6398), .B0(
mult_result[12]), .B1(n6399), .Y(n1860) );
NOR2X1TS U3417 ( .A(n5421), .B(n5420), .Y(n5425) );
AO22X1TS U3418 ( .A0(FPMULT_Sgf_normalized_result[13]), .A1(n6398), .B0(
mult_result[13]), .B1(n6399), .Y(n1859) );
NAND2X6TS U3419 ( .A(n2273), .B(n2788), .Y(n3423) );
OAI21X1TS U3420 ( .A0(n6590), .A1(n5240), .B0(n5192), .Y(n1358) );
OAI21X1TS U3421 ( .A0(n6589), .A1(n5240), .B0(n5191), .Y(n1360) );
AO22X1TS U3422 ( .A0(n6400), .A1(FPMULT_Sgf_normalized_result[0]), .B0(
mult_result[0]), .B1(n6401), .Y(n1872) );
OAI21X1TS U3423 ( .A0(n6587), .A1(n5240), .B0(n5209), .Y(n1362) );
AO22X1TS U3424 ( .A0(FPMULT_Sgf_normalized_result[14]), .A1(n6398), .B0(
mult_result[14]), .B1(n6399), .Y(n1858) );
AO22X1TS U3425 ( .A0(FPMULT_Sgf_normalized_result[15]), .A1(n6398), .B0(
mult_result[15]), .B1(n6399), .Y(n1857) );
NOR2X1TS U3426 ( .A(n5935), .B(n5798), .Y(n5802) );
AO22X1TS U3427 ( .A0(FPMULT_Sgf_normalized_result[16]), .A1(n6400), .B0(
mult_result[16]), .B1(n6399), .Y(n1856) );
AO22X1TS U3428 ( .A0(FPMULT_Sgf_normalized_result[17]), .A1(n6400), .B0(
mult_result[17]), .B1(n6399), .Y(n1855) );
AO22X1TS U3429 ( .A0(FPMULT_Sgf_normalized_result[18]), .A1(n6400), .B0(
mult_result[18]), .B1(n6399), .Y(n1854) );
AO22X1TS U3430 ( .A0(n2293), .A1(FPADDSUB_Add_Subt_result[16]), .B0(
FPADDSUB_DmP[7]), .B1(n5472), .Y(n5268) );
OAI21X1TS U3431 ( .A0(n6557), .A1(n5230), .B0(n5206), .Y(n1404) );
NAND2X2TS U3432 ( .A(n2399), .B(n2398), .Y(n3556) );
OAI21X1TS U3433 ( .A0(n6556), .A1(n5230), .B0(n5198), .Y(n1406) );
INVX12TS U3434 ( .A(n2755), .Y(n2258) );
AO21X1TS U3435 ( .A0(n2322), .A1(FPMULT_Op_MX[5]), .B0(n2578), .Y(n2201) );
OAI21X1TS U3436 ( .A0(n6573), .A1(n5236), .B0(n5235), .Y(n1380) );
OAI21X1TS U3437 ( .A0(n6566), .A1(n5230), .B0(n5225), .Y(n1394) );
OAI21X1TS U3438 ( .A0(n6579), .A1(n5236), .B0(n5199), .Y(n1372) );
OR2X2TS U3439 ( .A(n5581), .B(n5533), .Y(n2197) );
OAI21X1TS U3440 ( .A0(n6555), .A1(n5230), .B0(n5197), .Y(n1408) );
NAND2X6TS U3441 ( .A(n2594), .B(n2793), .Y(n3229) );
AO22X1TS U3442 ( .A0(n5508), .A1(n5293), .B0(n5502), .B1(n5277), .Y(n2194)
);
OAI21X1TS U3443 ( .A0(n6559), .A1(n5230), .B0(n5229), .Y(n1402) );
AO22X1TS U3444 ( .A0(n2292), .A1(FPADDSUB_Add_Subt_result[8]), .B0(
FPADDSUB_DmP[15]), .B1(n5270), .Y(n5254) );
OAI21X1TS U3445 ( .A0(n6568), .A1(n5236), .B0(n5194), .Y(n1390) );
OAI21X1TS U3446 ( .A0(n6578), .A1(n5236), .B0(n5221), .Y(n1374) );
OAI21X1TS U3447 ( .A0(n6576), .A1(n5236), .B0(n5205), .Y(n1376) );
OAI21X1TS U3448 ( .A0(n6565), .A1(n5230), .B0(n5202), .Y(n1396) );
AO21X1TS U3449 ( .A0(FPSENCOS_d_ff3_LUT_out[13]), .A1(n6469), .B0(n6438),
.Y(n1815) );
OAI21X1TS U3450 ( .A0(n6567), .A1(n5230), .B0(n5226), .Y(n1392) );
OAI21X1TS U3451 ( .A0(n6569), .A1(n5236), .B0(n5224), .Y(n1388) );
OAI21X1TS U3452 ( .A0(n6561), .A1(n5230), .B0(n5203), .Y(n1398) );
ADDFHX2TS U3453 ( .A(n3576), .B(n3575), .CI(n3574), .CO(n4411), .S(n4350) );
OAI21X1TS U3454 ( .A0(n6580), .A1(n5240), .B0(n5193), .Y(n1370) );
AO21X1TS U3455 ( .A0(FPSENCOS_d_ff3_LUT_out[18]), .A1(n6445), .B0(n6438),
.Y(n1820) );
OAI21X1TS U3456 ( .A0(n6572), .A1(n5236), .B0(n5207), .Y(n1382) );
OAI21X1TS U3457 ( .A0(n6575), .A1(n5236), .B0(n5200), .Y(n1378) );
AO22X1TS U3458 ( .A0(Data_2[31]), .A1(n5878), .B0(FPADDSUB_intDY[31]), .B1(
n5877), .Y(n5879) );
OAI21X1TS U3459 ( .A0(n6554), .A1(n5230), .B0(n5223), .Y(n1410) );
OAI21X1TS U3460 ( .A0(n6560), .A1(n5230), .B0(n5196), .Y(n1400) );
OAI21X1TS U3461 ( .A0(n6583), .A1(n5240), .B0(n5231), .Y(n1366) );
AO21X1TS U3462 ( .A0(n2132), .A1(n2748), .B0(n2750), .Y(n2200) );
INVX2TS U3463 ( .A(n5974), .Y(n5976) );
CLKMX2X2TS U3464 ( .A(Data_1[22]), .B(n2704), .S0(n2132), .Y(n2046) );
OAI21X1TS U3465 ( .A0(n6615), .A1(n5103), .B0(n5107), .Y(n1348) );
OAI21X1TS U3466 ( .A0(n6831), .A1(n5103), .B0(n5106), .Y(n1350) );
NAND3BX1TS U3467 ( .AN(n5665), .B(n5663), .C(n5662), .Y(n5683) );
ADDFHX2TS U3468 ( .A(n3336), .B(n3335), .CI(n3334), .CO(n3396), .S(n3338) );
AO22X1TS U3469 ( .A0(n6617), .A1(n5049), .B0(n6445), .B1(
FPSENCOS_d_ff3_sh_y_out[25]), .Y(n1419) );
INVX2TS U3470 ( .A(n6087), .Y(n6089) );
INVX2TS U3471 ( .A(n6049), .Y(n6051) );
INVX2TS U3472 ( .A(n5996), .Y(n5998) );
INVX2TS U3473 ( .A(n6024), .Y(n6026) );
OAI21X1TS U3474 ( .A0(n5996), .A1(n5993), .B0(n5997), .Y(n2907) );
AO22X1TS U3475 ( .A0(n6617), .A1(n6439), .B0(n6562), .B1(
FPSENCOS_d_ff3_LUT_out[12]), .Y(n1814) );
ADDHX2TS U3476 ( .A(n3694), .B(n3693), .CO(n3699), .S(n3737) );
AO22X1TS U3477 ( .A0(n7012), .A1(n6392), .B0(n6391), .B1(FPMULT_zero_flag),
.Y(n1991) );
OAI21X1TS U3478 ( .A0(n6068), .A1(n6078), .B0(n6069), .Y(n2939) );
AO22X1TS U3479 ( .A0(n6563), .A1(n5043), .B0(n6472), .B1(
FPSENCOS_d_ff3_sh_x_out[25]), .Y(n1790) );
ADDFHX2TS U3480 ( .A(n2818), .B(n3083), .CI(n3082), .CO(n3032), .S(n3158) );
ADDFHX2TS U3481 ( .A(n3402), .B(n3401), .CI(n3400), .CO(n3481), .S(n3410) );
AO22X1TS U3482 ( .A0(n6623), .A1(FPSENCOS_sign_inv_out[19]), .B0(n6625),
.B1(cordic_result[19]), .Y(n1371) );
NAND4X1TS U3483 ( .A(n6436), .B(n6435), .C(n6434), .D(n6452), .Y(n6439) );
NAND3BX1TS U3484 ( .AN(n5938), .B(n5939), .C(FPADDSUB_Add_Subt_result[14]),
.Y(n5946) );
OAI21X1TS U3485 ( .A0(n6809), .A1(n6429), .B0(n5115), .Y(n1421) );
AO22X1TS U3486 ( .A0(n6623), .A1(FPSENCOS_sign_inv_out[16]), .B0(n6624),
.B1(cordic_result[16]), .Y(n1377) );
AO22X1TS U3487 ( .A0(n6623), .A1(FPSENCOS_sign_inv_out[14]), .B0(n6622),
.B1(cordic_result[14]), .Y(n1381) );
AO22X1TS U3488 ( .A0(n6628), .A1(n5034), .B0(n6625), .B1(cordic_result[31]),
.Y(n1346) );
NAND3BX4TS U3489 ( .AN(n6506), .B(n5050), .C(n6418), .Y(n5051) );
AO22X1TS U3490 ( .A0(n6617), .A1(n6600), .B0(n6616), .B1(
FPSENCOS_d_ff3_sh_y_out[24]), .Y(n1420) );
NOR2X1TS U3491 ( .A(FPSENCOS_sel_mux_1_reg), .B(n6613), .Y(n5431) );
OR2X2TS U3492 ( .A(n2963), .B(n2962), .Y(n6003) );
OAI21X1TS U3493 ( .A0(n6404), .A1(n6403), .B0(n6402), .Y(n6405) );
NAND3X1TS U3494 ( .A(n6423), .B(n6436), .C(n6435), .Y(n6432) );
AO22X1TS U3495 ( .A0(n6628), .A1(FPSENCOS_sign_inv_out[30]), .B0(n6626),
.B1(cordic_result[30]), .Y(n1349) );
NAND2X4TS U3496 ( .A(n5256), .B(n5255), .Y(n5252) );
AO22X1TS U3497 ( .A0(n6621), .A1(FPSENCOS_sign_inv_out[9]), .B0(n6625), .B1(
cordic_result[9]), .Y(n1391) );
AO22X1TS U3498 ( .A0(n6623), .A1(FPSENCOS_sign_inv_out[11]), .B0(n6625),
.B1(cordic_result[11]), .Y(n1387) );
AO22X1TS U3499 ( .A0(n6621), .A1(FPSENCOS_sign_inv_out[7]), .B0(n6622), .B1(
cordic_result[7]), .Y(n1395) );
OR2X2TS U3500 ( .A(n2948), .B(n2947), .Y(n2832) );
AO22X1TS U3501 ( .A0(n6627), .A1(FPSENCOS_sign_inv_out[20]), .B0(n6625),
.B1(cordic_result[20]), .Y(n1369) );
AO22X1TS U3502 ( .A0(n6623), .A1(FPSENCOS_sign_inv_out[10]), .B0(n6626),
.B1(cordic_result[10]), .Y(n1389) );
OR2X2TS U3503 ( .A(n2950), .B(n2949), .Y(n6033) );
AOI2BB1X1TS U3504 ( .A0N(n6563), .A1N(FPSENCOS_d_ff3_LUT_out[10]), .B0(n6453), .Y(n1812) );
AO22X1TS U3505 ( .A0(n6621), .A1(FPSENCOS_sign_inv_out[4]), .B0(n6622), .B1(
cordic_result[4]), .Y(n1401) );
AO22X1TS U3506 ( .A0(n6621), .A1(FPSENCOS_sign_inv_out[5]), .B0(n6622), .B1(
cordic_result[5]), .Y(n1399) );
AO22X1TS U3507 ( .A0(n6621), .A1(FPSENCOS_sign_inv_out[0]), .B0(n6624), .B1(
cordic_result[0]), .Y(n1409) );
AO22X1TS U3508 ( .A0(n6621), .A1(FPSENCOS_sign_inv_out[1]), .B0(n6622), .B1(
cordic_result[1]), .Y(n1407) );
AO22X1TS U3509 ( .A0(n6621), .A1(FPSENCOS_sign_inv_out[8]), .B0(n6625), .B1(
cordic_result[8]), .Y(n1393) );
AO22X1TS U3510 ( .A0(n6623), .A1(FPSENCOS_sign_inv_out[13]), .B0(n6622),
.B1(cordic_result[13]), .Y(n1383) );
AO22X1TS U3511 ( .A0(n6623), .A1(FPSENCOS_sign_inv_out[15]), .B0(n6624),
.B1(cordic_result[15]), .Y(n1379) );
AO22X1TS U3512 ( .A0(n6621), .A1(FPSENCOS_sign_inv_out[6]), .B0(n6622), .B1(
cordic_result[6]), .Y(n1397) );
AO22X1TS U3513 ( .A0(n6627), .A1(FPSENCOS_sign_inv_out[21]), .B0(n6626),
.B1(cordic_result[21]), .Y(n1367) );
AO22X1TS U3514 ( .A0(n6621), .A1(FPSENCOS_sign_inv_out[3]), .B0(n6622), .B1(
cordic_result[3]), .Y(n1403) );
AO22X1TS U3515 ( .A0(n6621), .A1(FPSENCOS_sign_inv_out[2]), .B0(n6622), .B1(
cordic_result[2]), .Y(n1405) );
OAI21X1TS U3516 ( .A0(n5072), .A1(n5071), .B0(n5070), .Y(n1706) );
AO22X1TS U3517 ( .A0(n6623), .A1(FPSENCOS_sign_inv_out[12]), .B0(n6624),
.B1(cordic_result[12]), .Y(n1385) );
AO22X1TS U3518 ( .A0(n6623), .A1(FPSENCOS_sign_inv_out[17]), .B0(n6624),
.B1(cordic_result[17]), .Y(n1375) );
AO22X1TS U3519 ( .A0(n6623), .A1(FPSENCOS_sign_inv_out[18]), .B0(n6624),
.B1(cordic_result[18]), .Y(n1373) );
OR2X2TS U3520 ( .A(n2979), .B(n2978), .Y(n4855) );
AO22X1TS U3521 ( .A0(n6627), .A1(FPSENCOS_sign_inv_out[26]), .B0(n6626),
.B1(cordic_result[26]), .Y(n1357) );
OAI21X1TS U3522 ( .A0(n6434), .A1(n6496), .B0(n5101), .Y(n1811) );
OR2X2TS U3523 ( .A(n5256), .B(n5255), .Y(n5257) );
OAI22X2TS U3524 ( .A0(n3915), .A1(n2234), .B0(n2166), .B1(n2600), .Y(n3942)
);
AO22X1TS U3525 ( .A0(n6627), .A1(FPSENCOS_sign_inv_out[27]), .B0(n6626),
.B1(cordic_result[27]), .Y(n1355) );
OR2X2TS U3526 ( .A(n5255), .B(n5882), .Y(n2199) );
AO22X1TS U3527 ( .A0(n6627), .A1(FPSENCOS_sign_inv_out[24]), .B0(n6626),
.B1(cordic_result[24]), .Y(n1361) );
AO22X1TS U3528 ( .A0(n6627), .A1(FPSENCOS_sign_inv_out[29]), .B0(n6625),
.B1(cordic_result[29]), .Y(n1351) );
AO22X1TS U3529 ( .A0(n6617), .A1(n5036), .B0(n6558), .B1(
FPSENCOS_d_ff3_sh_x_out[24]), .Y(n1791) );
AO22X1TS U3530 ( .A0(n6627), .A1(FPSENCOS_sign_inv_out[23]), .B0(n6626),
.B1(cordic_result[23]), .Y(n1363) );
AOI2BB2X1TS U3531 ( .B0(FPSENCOS_d_ff3_LUT_out[2]), .B1(n6464), .A0N(n6472),
.A1N(n5111), .Y(n5112) );
AO22X1TS U3532 ( .A0(n6627), .A1(FPSENCOS_sign_inv_out[22]), .B0(n6626),
.B1(cordic_result[22]), .Y(n1365) );
AO22X1TS U3533 ( .A0(n6627), .A1(FPSENCOS_sign_inv_out[25]), .B0(n6626),
.B1(cordic_result[25]), .Y(n1359) );
AO22X1TS U3534 ( .A0(n6627), .A1(FPSENCOS_sign_inv_out[28]), .B0(n6624),
.B1(cordic_result[28]), .Y(n1353) );
AO22X1TS U3535 ( .A0(n6497), .A1(Data_1[25]), .B0(n6498), .B1(
FPSENCOS_d_ff1_Z[25]), .Y(n1733) );
AO22X1TS U3536 ( .A0(n6503), .A1(Data_1[3]), .B0(n6502), .B1(
FPSENCOS_d_ff1_Z[3]), .Y(n1711) );
AO22X1TS U3537 ( .A0(n6617), .A1(FPSENCOS_d_ff2_Y[31]), .B0(n6616), .B1(
FPSENCOS_d_ff3_sh_y_out[31]), .Y(n1412) );
AO22X1TS U3538 ( .A0(n6501), .A1(Data_1[17]), .B0(n6500), .B1(
FPSENCOS_d_ff1_Z[17]), .Y(n1725) );
AO22X1TS U3539 ( .A0(n6563), .A1(FPSENCOS_d_ff2_Y[0]), .B0(n6558), .B1(
FPSENCOS_d_ff3_sh_y_out[0]), .Y(n1474) );
AO22X1TS U3540 ( .A0(n6505), .A1(Data_1[7]), .B0(n6502), .B1(
FPSENCOS_d_ff1_Z[7]), .Y(n1715) );
AO22X1TS U3541 ( .A0(n6501), .A1(Data_1[15]), .B0(n6500), .B1(
FPSENCOS_d_ff1_Z[15]), .Y(n1723) );
AO22X1TS U3542 ( .A0(n6505), .A1(Data_1[5]), .B0(n6502), .B1(
FPSENCOS_d_ff1_Z[5]), .Y(n1713) );
INVX6TS U3543 ( .A(n2415), .Y(n2252) );
AO22X1TS U3544 ( .A0(n6497), .A1(Data_1[27]), .B0(n6498), .B1(
FPSENCOS_d_ff1_Z[27]), .Y(n1735) );
OR2X2TS U3545 ( .A(FPMULT_FSM_selector_C), .B(n5809), .Y(n2202) );
AO22X1TS U3546 ( .A0(n6563), .A1(FPSENCOS_d_ff2_X[31]), .B0(n6616), .B1(
FPSENCOS_d_ff3_sh_x_out[31]), .Y(n1801) );
NAND3X1TS U3547 ( .A(n5068), .B(FPSENCOS_sel_mux_3_reg), .C(n6983), .Y(n5067) );
AO22X1TS U3548 ( .A0(n6503), .A1(Data_1[2]), .B0(n6502), .B1(
FPSENCOS_d_ff1_Z[2]), .Y(n1710) );
AOI31X1TS U3549 ( .A0(n6662), .A1(n5805), .A2(n5092), .B0(
FPMULT_FSM_selector_C), .Y(n5093) );
AO22X1TS U3550 ( .A0(n6503), .A1(Data_1[4]), .B0(n6502), .B1(
FPSENCOS_d_ff1_Z[4]), .Y(n1712) );
AO22X1TS U3551 ( .A0(n6501), .A1(Data_1[18]), .B0(n6500), .B1(
FPSENCOS_d_ff1_Z[18]), .Y(n1726) );
AO22X1TS U3552 ( .A0(n6497), .A1(Data_1[26]), .B0(n6498), .B1(
FPSENCOS_d_ff1_Z[26]), .Y(n1734) );
AO22X1TS U3553 ( .A0(n6501), .A1(Data_1[6]), .B0(n6502), .B1(
FPSENCOS_d_ff1_Z[6]), .Y(n1714) );
NOR2X4TS U3554 ( .A(operation[1]), .B(n6637), .Y(n5098) );
AO22X1TS U3555 ( .A0(n6497), .A1(Data_1[24]), .B0(n6498), .B1(
FPSENCOS_d_ff1_Z[24]), .Y(n1732) );
NAND2XLTS U3556 ( .A(FPSENCOS_sel_mux_2_reg[1]), .B(n6983), .Y(n5073) );
AOI31X1TS U3557 ( .A0(n6736), .A1(n6674), .A2(n5943), .B0(n5942), .Y(n5945)
);
AO22X1TS U3558 ( .A0(n6563), .A1(FPSENCOS_d_ff2_Y[6]), .B0(n6562), .B1(
FPSENCOS_d_ff3_sh_y_out[6]), .Y(n1462) );
AO22X1TS U3559 ( .A0(n6501), .A1(Data_1[22]), .B0(n6498), .B1(
FPSENCOS_d_ff1_Z[22]), .Y(n1730) );
OR2X2TS U3560 ( .A(n6763), .B(n5809), .Y(n5810) );
AO22X1TS U3561 ( .A0(n6501), .A1(Data_1[16]), .B0(n6500), .B1(
FPSENCOS_d_ff1_Z[16]), .Y(n1724) );
OAI21X1TS U3562 ( .A0(FPMULT_Sgf_normalized_result[0]), .A1(n6179), .B0(
n5058), .Y(n1989) );
AO22X1TS U3563 ( .A0(n6501), .A1(Data_1[19]), .B0(n6500), .B1(
FPSENCOS_d_ff1_Z[19]), .Y(n1727) );
AO22X1TS U3564 ( .A0(n6505), .A1(Data_1[10]), .B0(n6502), .B1(
FPSENCOS_d_ff1_Z[10]), .Y(n1718) );
NAND4X1TS U3565 ( .A(n5003), .B(n5002), .C(n5001), .D(n5000), .Y(n5707) );
AO22X1TS U3566 ( .A0(n6497), .A1(Data_1[29]), .B0(n6498), .B1(
FPSENCOS_d_ff1_Z[29]), .Y(n1737) );
INVX1TS U3567 ( .A(n5395), .Y(n5421) );
INVX6TS U3568 ( .A(n2232), .Y(n2234) );
AO22X1TS U3569 ( .A0(n6505), .A1(Data_1[14]), .B0(n6500), .B1(
FPSENCOS_d_ff1_Z[14]), .Y(n1722) );
AO22X1TS U3570 ( .A0(n6505), .A1(Data_1[11]), .B0(n6502), .B1(
FPSENCOS_d_ff1_Z[11]), .Y(n1719) );
AO22X1TS U3571 ( .A0(n6501), .A1(Data_1[23]), .B0(n6498), .B1(
FPSENCOS_d_ff1_Z[23]), .Y(n1731) );
AO22X1TS U3572 ( .A0(n6501), .A1(Data_1[20]), .B0(n6500), .B1(
FPSENCOS_d_ff1_Z[20]), .Y(n1728) );
AO22X1TS U3573 ( .A0(n6505), .A1(Data_1[12]), .B0(n6502), .B1(
FPSENCOS_d_ff1_Z[12]), .Y(n1720) );
AO22X1TS U3574 ( .A0(n6617), .A1(FPSENCOS_d_ff2_Y[21]), .B0(n6616), .B1(
FPSENCOS_d_ff3_sh_y_out[21]), .Y(n1432) );
AO22X1TS U3575 ( .A0(n6501), .A1(Data_1[21]), .B0(n6500), .B1(
FPSENCOS_d_ff1_Z[21]), .Y(n1729) );
AO22X1TS U3576 ( .A0(n6505), .A1(Data_1[13]), .B0(n6500), .B1(
FPSENCOS_d_ff1_Z[13]), .Y(n1721) );
AO22X1TS U3577 ( .A0(n6497), .A1(Data_1[30]), .B0(n6499), .B1(
FPSENCOS_d_ff1_Z[30]), .Y(n1738) );
AO22X1TS U3578 ( .A0(n6505), .A1(Data_1[31]), .B0(n6504), .B1(
FPSENCOS_d_ff1_Z[31]), .Y(n1707) );
AO22X1TS U3579 ( .A0(n6563), .A1(FPSENCOS_d_ff2_Y[1]), .B0(n6616), .B1(
FPSENCOS_d_ff3_sh_y_out[1]), .Y(n1472) );
AO22X1TS U3580 ( .A0(n6505), .A1(Data_1[8]), .B0(n6500), .B1(
FPSENCOS_d_ff1_Z[8]), .Y(n1716) );
AO22X1TS U3581 ( .A0(n6505), .A1(Data_1[9]), .B0(n6502), .B1(
FPSENCOS_d_ff1_Z[9]), .Y(n1717) );
OAI211X1TS U3582 ( .A0(n5092), .A1(n5087), .B0(n5086), .C0(n6201), .Y(n2058)
);
OAI21X1TS U3583 ( .A0(n6525), .A1(n6780), .B0(n5061), .Y(n1844) );
OR2X2TS U3584 ( .A(n5413), .B(n5091), .Y(n1699) );
AO22X1TS U3585 ( .A0(n6497), .A1(Data_1[28]), .B0(n6498), .B1(
FPSENCOS_d_ff1_Z[28]), .Y(n1736) );
OAI21XLTS U3586 ( .A0(n5181), .A1(n6778), .B0(n5137), .Y(op_result[15]) );
OAI21XLTS U3587 ( .A0(n5181), .A1(n6691), .B0(n5144), .Y(op_result[20]) );
OAI21XLTS U3588 ( .A0(n5181), .A1(n6697), .B0(n5145), .Y(op_result[12]) );
OAI21XLTS U3589 ( .A0(n5181), .A1(n6694), .B0(n5178), .Y(op_result[16]) );
OAI21XLTS U3590 ( .A0(n5181), .A1(n6695), .B0(n5139), .Y(op_result[14]) );
OAI21XLTS U3591 ( .A0(n5181), .A1(n6696), .B0(n5135), .Y(op_result[13]) );
OAI21XLTS U3592 ( .A0(n5181), .A1(n6776), .B0(n5143), .Y(op_result[21]) );
OAI21XLTS U3593 ( .A0(n5300), .A1(n6545), .B0(n5220), .Y(op_result[3]) );
OAI21XLTS U3594 ( .A0(n5217), .A1(n6551), .B0(n5215), .Y(op_result[1]) );
OAI21XLTS U3595 ( .A0(n5190), .A1(n6699), .B0(n5184), .Y(op_result[29]) );
OAI21XLTS U3596 ( .A0(n5190), .A1(n6700), .B0(n5182), .Y(op_result[28]) );
OAI21XLTS U3597 ( .A0(n5300), .A1(n6536), .B0(n5299), .Y(op_result[9]) );
OAI21XLTS U3598 ( .A0(n5217), .A1(n6619), .B0(n5216), .Y(op_result[0]) );
OAI21XLTS U3599 ( .A0(n5181), .A1(n6777), .B0(n5177), .Y(op_result[18]) );
OAI21XLTS U3600 ( .A0(n5190), .A1(n6705), .B0(n5185), .Y(op_result[30]) );
OAI21XLTS U3601 ( .A0(n5190), .A1(n6780), .B0(n5189), .Y(op_result[31]) );
OAI21XLTS U3602 ( .A0(n5190), .A1(n6703), .B0(n5136), .Y(op_result[25]) );
OAI21XLTS U3603 ( .A0(n5181), .A1(n6693), .B0(n5176), .Y(op_result[17]) );
OAI21XLTS U3604 ( .A0(n5190), .A1(n6704), .B0(n5134), .Y(op_result[24]) );
OAI21XLTS U3605 ( .A0(n5190), .A1(n6781), .B0(n5140), .Y(op_result[23]) );
OAI21XLTS U3606 ( .A0(n5190), .A1(n6775), .B0(n5138), .Y(op_result[22]) );
OAI21XLTS U3607 ( .A0(n5300), .A1(n6698), .B0(n5213), .Y(op_result[10]) );
OAI21XLTS U3608 ( .A0(n5300), .A1(n6549), .B0(n5214), .Y(op_result[2]) );
OAI21XLTS U3609 ( .A0(n5181), .A1(n6692), .B0(n5180), .Y(op_result[19]) );
OAI21XLTS U3610 ( .A0(n5300), .A1(n6779), .B0(n5219), .Y(op_result[11]) );
OAI21XLTS U3611 ( .A0(n5190), .A1(n6702), .B0(n5141), .Y(op_result[26]) );
OAI21XLTS U3612 ( .A0(n5190), .A1(n6701), .B0(n5142), .Y(op_result[27]) );
INVX6TS U3613 ( .A(n2989), .Y(n2913) );
AO22X1TS U3614 ( .A0(n6503), .A1(Data_1[0]), .B0(n6504), .B1(
FPSENCOS_d_ff1_Z[0]), .Y(n1708) );
OAI211X1TS U3615 ( .A0(n5064), .A1(n5063), .B0(n5062), .C0(n6416), .Y(
FPSENCOS_cordic_FSM_state_next_1_) );
NAND3X1TS U3616 ( .A(n2240), .B(n6433), .C(n6713), .Y(n6452) );
NAND2X4TS U3617 ( .A(n3068), .B(n3075), .Y(n2723) );
AO21X4TS U3618 ( .A0(n3190), .A1(n2628), .B0(n2627), .Y(n2626) );
NOR2X2TS U3619 ( .A(FPSENCOS_sel_mux_3_reg), .B(n5222), .Y(n5105) );
AO22X1TS U3620 ( .A0(n6503), .A1(Data_1[1]), .B0(n6504), .B1(
FPSENCOS_d_ff1_Z[1]), .Y(n1709) );
NOR2X1TS U3621 ( .A(n6201), .B(n1917), .Y(n6202) );
NAND2BX1TS U3622 ( .AN(n6201), .B(n1917), .Y(n5056) );
INVX12TS U3623 ( .A(n2742), .Y(n3744) );
OR2X2TS U3624 ( .A(n6108), .B(n6763), .Y(n5820) );
OR2X2TS U3625 ( .A(n6108), .B(FPMULT_FSM_selector_C), .Y(n6195) );
BUFX8TS U3626 ( .A(n2643), .Y(n2333) );
AOI21X2TS U3627 ( .A0(n3190), .A1(n2628), .B0(n3133), .Y(n2793) );
OAI21XLTS U3628 ( .A0(n5300), .A1(n6541), .B0(n5172), .Y(op_result[5]) );
OAI21XLTS U3629 ( .A0(n5300), .A1(n6540), .B0(n5171), .Y(op_result[6]) );
OAI21XLTS U3630 ( .A0(n5300), .A1(n6539), .B0(n5175), .Y(op_result[7]) );
OAI21XLTS U3631 ( .A0(n5300), .A1(n6538), .B0(n5170), .Y(op_result[8]) );
OAI21XLTS U3632 ( .A0(n5300), .A1(n6544), .B0(n5173), .Y(op_result[4]) );
OR2X4TS U3633 ( .A(n5004), .B(n2981), .Y(n2989) );
AO22X1TS U3634 ( .A0(FPADDSUB_LZA_output[4]), .A1(n5248), .B0(n5247), .B1(
FPADDSUB_DmP[27]), .Y(n2845) );
OAI21X1TS U3635 ( .A0(n5417), .A1(n5472), .B0(n5616), .Y(n4913) );
OR2X2TS U3636 ( .A(n5616), .B(FPADDSUB_FS_Module_state_reg[2]), .Y(n6407) );
OAI21X1TS U3637 ( .A0(FPMULT_FSM_selector_B[0]), .A1(n5868), .B0(n5861), .Y(
n5869) );
INVX12TS U3638 ( .A(n2267), .Y(n2268) );
NOR2X1TS U3639 ( .A(n6167), .B(FPMULT_Sgf_normalized_result[2]), .Y(n6168)
);
NAND2X2TS U3640 ( .A(n5104), .B(FPSENCOS_sel_mux_3_reg), .Y(n5103) );
NAND2X2TS U3641 ( .A(n2751), .B(n3122), .Y(n3115) );
INVX2TS U3642 ( .A(n2503), .Y(n3079) );
OA21X4TS U3643 ( .A0(n5808), .A1(n6662), .B0(n5807), .Y(n4922) );
NOR2X1TS U3644 ( .A(n6510), .B(FPADDSUB_Add_Subt_result[25]), .Y(n6511) );
NAND2BX1TS U3645 ( .AN(n2339), .B(FPMULT_Op_MY[13]), .Y(n4045) );
OAI211X1TS U3646 ( .A0(FPADDSUB_intDX[8]), .A1(n6788), .B0(n5646), .C0(n5649), .Y(n5660) );
BUFX12TS U3647 ( .A(n2120), .Y(n3743) );
CLKMX2X2TS U3648 ( .A(FPADDSUB_DMP[16]), .B(
FPADDSUB_Sgf_normalized_result[18]), .S0(n2970), .Y(n2959) );
NOR2X1TS U3649 ( .A(n6689), .B(n2981), .Y(n2977) );
NOR2X1TS U3650 ( .A(FPADDSUB_Add_Subt_result[7]), .B(n2350), .Y(n5613) );
CLKMX2X2TS U3651 ( .A(FPADDSUB_DMP[6]), .B(FPADDSUB_Sgf_normalized_result[8]), .S0(n2917), .Y(n2923) );
NOR2X1TS U3652 ( .A(n6675), .B(n2981), .Y(n2954) );
CLKMX2X2TS U3653 ( .A(FPADDSUB_DMP[5]), .B(FPADDSUB_Sgf_normalized_result[7]), .S0(n2917), .Y(n2921) );
CLKMX2X2TS U3654 ( .A(FPADDSUB_DMP[2]), .B(FPADDSUB_Sgf_normalized_result[4]), .S0(n2917), .Y(n2901) );
CLKMX2X2TS U3655 ( .A(FPADDSUB_DMP[3]), .B(FPADDSUB_Sgf_normalized_result[5]), .S0(n2917), .Y(n2903) );
CLKMX2X2TS U3656 ( .A(FPADDSUB_DMP[4]), .B(FPADDSUB_Sgf_normalized_result[6]), .S0(n2917), .Y(n2905) );
AND2X2TS U3657 ( .A(n5054), .B(n5053), .Y(n6125) );
OAI21X1TS U3658 ( .A0(r_mode[1]), .A1(FPADDSUB_sign_final_result), .B0(n5089), .Y(n5090) );
CLKMX2X2TS U3659 ( .A(FPADDSUB_DMP[1]), .B(FPADDSUB_Sgf_normalized_result[3]), .S0(n2917), .Y(n2899) );
CLKINVX2TS U3660 ( .A(n5102), .Y(n5788) );
INVX1TS U3661 ( .A(n5059), .Y(n4967) );
AND2X2TS U3662 ( .A(FPMULT_Op_MY[0]), .B(n6367), .Y(n2167) );
CLKMX2X2TS U3663 ( .A(FPADDSUB_DMP[11]), .B(
FPADDSUB_Sgf_normalized_result[13]), .S0(n2970), .Y(n2935) );
OAI221XLTS U3664 ( .A0(n6742), .A1(FPADDSUB_intDY[18]), .B0(n6760), .B1(
FPADDSUB_intDX[29]), .C0(n4985), .Y(n4990) );
CLKMX2X2TS U3665 ( .A(FPADDSUB_DMP[29]), .B(FPADDSUB_exp_oper_result[6]),
.S0(n2983), .Y(n2853) );
NOR2X1TS U3666 ( .A(n6676), .B(n2981), .Y(n2919) );
CLKMX2X2TS U3667 ( .A(FPADDSUB_DMP[22]), .B(
FPADDSUB_Sgf_normalized_result[24]), .S0(n2983), .Y(n2984) );
NOR2X1TS U3668 ( .A(n6690), .B(n2981), .Y(n2982) );
BUFX16TS U3669 ( .A(n6368), .Y(n2276) );
CLKMX2X2TS U3670 ( .A(FPADDSUB_DMP[7]), .B(FPADDSUB_Sgf_normalized_result[9]), .S0(n2917), .Y(n2925) );
NAND3X1TS U3671 ( .A(n6753), .B(n5621), .C(FPADDSUB_intDX[26]), .Y(n5623) );
NOR2X1TS U3672 ( .A(n6102), .B(n6733), .Y(n6104) );
NAND2BX1TS U3673 ( .AN(FPADDSUB_Sgf_normalized_result[25]), .B(n2986), .Y(
n4861) );
CLKMX2X2TS U3674 ( .A(FPADDSUB_DMP[10]), .B(
FPADDSUB_Sgf_normalized_result[12]), .S0(n2970), .Y(n2933) );
NOR2X1TS U3675 ( .A(n5679), .B(FPADDSUB_intDY[24]), .Y(n5620) );
CLKMX2X2TS U3676 ( .A(FPADDSUB_DMP[8]), .B(
FPADDSUB_Sgf_normalized_result[10]), .S0(n2917), .Y(n2927) );
OAI221XLTS U3677 ( .A0(n6739), .A1(FPADDSUB_intDX[25]), .B0(n6745), .B1(
FPADDSUB_intDX[24]), .C0(n4987), .Y(n4988) );
OAI211X2TS U3678 ( .A0(FPADDSUB_intDX[20]), .A1(n6723), .B0(n5676), .C0(
n5661), .Y(n5670) );
NOR2X1TS U3679 ( .A(n2981), .B(n6718), .Y(n2918) );
OAI211X2TS U3680 ( .A0(FPADDSUB_intDX[12]), .A1(n6749), .B0(n5656), .C0(
n5642), .Y(n5658) );
NOR2X1TS U3681 ( .A(n6102), .B(n6146), .Y(n6103) );
INVX3TS U3682 ( .A(n2238), .Y(n2240) );
NAND3X1TS U3683 ( .A(n6788), .B(n5646), .C(FPADDSUB_intDX[8]), .Y(n5647) );
CLKMX2X2TS U3684 ( .A(FPADDSUB_DMP[17]), .B(
FPADDSUB_Sgf_normalized_result[19]), .S0(n2970), .Y(n2962) );
INVX1TS U3685 ( .A(n1905), .Y(n6353) );
NOR2X1TS U3686 ( .A(n5644), .B(FPADDSUB_intDY[10]), .Y(n5645) );
NOR2X1TS U3687 ( .A(n6758), .B(n2986), .Y(n2961) );
NOR2X1TS U3688 ( .A(n6767), .B(n2986), .Y(n2974) );
CLKMX2X2TS U3689 ( .A(FPADDSUB_DMP[20]), .B(
FPADDSUB_Sgf_normalized_result[22]), .S0(n2986), .Y(n2975) );
NOR2X1TS U3690 ( .A(n6717), .B(n2981), .Y(n2920) );
CLKMX2X2TS U3691 ( .A(FPADDSUB_DMP[18]), .B(
FPADDSUB_Sgf_normalized_result[20]), .S0(n2970), .Y(n2966) );
CLKMX2X2TS U3692 ( .A(FPADDSUB_DMP[9]), .B(
FPADDSUB_Sgf_normalized_result[11]), .S0(n2917), .Y(n2931) );
NOR2X1TS U3693 ( .A(n6735), .B(n2986), .Y(n2945) );
OAI221XLTS U3694 ( .A0(n6756), .A1(FPADDSUB_intDY[1]), .B0(n6679), .B1(
FPADDSUB_intDX[0]), .C0(n4979), .Y(n4980) );
NOR2X1TS U3695 ( .A(n6768), .B(n2981), .Y(n2968) );
CLKMX2X2TS U3696 ( .A(FPADDSUB_DMP[19]), .B(
FPADDSUB_Sgf_normalized_result[21]), .S0(n2970), .Y(n2971) );
NOR2X1TS U3697 ( .A(n6686), .B(n2981), .Y(n2965) );
NAND3X1TS U3698 ( .A(n6325), .B(n6324), .C(n6323), .Y(n6855) );
OAI21X1TS U3699 ( .A0(FPADDSUB_intDX[15]), .A1(n6666), .B0(
FPADDSUB_intDX[14]), .Y(n5652) );
NOR2X1TS U3700 ( .A(n2163), .B(n2813), .Y(n3499) );
NAND2BX1TS U3701 ( .AN(FPADDSUB_intDX[19]), .B(FPADDSUB_intDY[19]), .Y(n5667) );
NOR2X1TS U3702 ( .A(n6672), .B(n6730), .Y(n5054) );
NAND2BX1TS U3703 ( .AN(FPADDSUB_intDX[27]), .B(FPADDSUB_intDY[27]), .Y(n5621) );
NAND2BX1TS U3704 ( .AN(FPADDSUB_intDY[27]), .B(FPADDSUB_intDX[27]), .Y(n5622) );
NAND2BX1TS U3705 ( .AN(FPADDSUB_intDX[13]), .B(FPADDSUB_intDY[13]), .Y(n5642) );
NAND2BX1TS U3706 ( .AN(FPADDSUB_intDX[9]), .B(FPADDSUB_intDY[9]), .Y(n5646)
);
CLKMX2X2TS U3707 ( .A(n6907), .B(n6906), .S0(n6905), .Y(n1905) );
NAND2BX1TS U3708 ( .AN(FPADDSUB_intDX[21]), .B(FPADDSUB_intDY[21]), .Y(n5661) );
OAI21X1TS U3709 ( .A0(FPADDSUB_intDX[21]), .A1(n6726), .B0(
FPADDSUB_intDX[20]), .Y(n5664) );
OAI21X1TS U3710 ( .A0(FPADDSUB_intDX[23]), .A1(n6762), .B0(
FPADDSUB_intDX[22]), .Y(n5672) );
NAND2BX1TS U3711 ( .AN(FPADDSUB_intDX[24]), .B(FPADDSUB_intDY[24]), .Y(n5677) );
CLKMX2X2TS U3712 ( .A(n6904), .B(n6854), .S0(n6903), .Y(n1906) );
INVX8TS U3713 ( .A(FPMULT_Op_MY[19]), .Y(n2749) );
OAI21X1TS U3714 ( .A0(FPADDSUB_intDX[13]), .A1(n6725), .B0(
FPADDSUB_intDX[12]), .Y(n5643) );
NOR2X1TS U3715 ( .A(n2163), .B(n2810), .Y(n3579) );
OR2X2TS U3716 ( .A(FPMULT_FSM_selector_B[1]), .B(n6738), .Y(n5861) );
NOR3X2TS U3717 ( .A(n6672), .B(n6662), .C(FPMULT_FS_Module_state_reg[2]),
.Y(n4852) );
NAND2XLTS U3718 ( .A(FPSENCOS_cordic_FSM_state_reg[0]), .B(n6720), .Y(n5244)
);
NAND2X2TS U3719 ( .A(FPSENCOS_cordic_FSM_state_reg[2]), .B(
FPSENCOS_cordic_FSM_state_reg[3]), .Y(n5243) );
AOI2BB2X1TS U3720 ( .B0(FPADDSUB_sign_final_result), .B1(n5088), .A0N(
FPADDSUB_Sgf_normalized_result[0]), .A1N(
FPADDSUB_Sgf_normalized_result[1]), .Y(n5089) );
CLKMX2X2TS U3721 ( .A(n6895), .B(n6894), .S0(n6893), .Y(n1917) );
NAND3X1TS U3722 ( .A(n4847), .B(n4846), .C(n4845), .Y(n4848) );
NAND2X1TS U3723 ( .A(operation[1]), .B(begin_operation), .Y(n5063) );
NAND2X1TS U3724 ( .A(operation[1]), .B(ack_operation), .Y(n5781) );
ADDFHX2TS U3725 ( .A(n3239), .B(n3238), .CI(n3237), .CO(n3296), .S(n3771) );
XNOR2X2TS U3726 ( .A(n4351), .B(n4350), .Y(n2767) );
XNOR2X2TS U3727 ( .A(n6365), .B(n6382), .Y(n3649) );
INVX8TS U3728 ( .A(n2460), .Y(n2505) );
NAND2X6TS U3729 ( .A(n2133), .B(n2739), .Y(n2516) );
NAND2X2TS U3730 ( .A(n4585), .B(n4601), .Y(n4586) );
OAI22X1TS U3731 ( .A0(n3660), .A1(n3725), .B0(n3656), .B1(n3831), .Y(n3720)
);
NOR2X6TS U3732 ( .A(n4701), .B(n4700), .Y(n4944) );
NOR2X4TS U3733 ( .A(n4704), .B(n4705), .Y(n2370) );
INVX4TS U3734 ( .A(n4326), .Y(n3373) );
NAND2X4TS U3735 ( .A(n2188), .B(n2369), .Y(n2548) );
NAND2X6TS U3736 ( .A(n2369), .B(n2130), .Y(n2474) );
NAND2X6TS U3737 ( .A(n2473), .B(n4715), .Y(n2144) );
NAND2X4TS U3738 ( .A(n2473), .B(n4715), .Y(n2486) );
BUFX16TS U3739 ( .A(n2573), .Y(n2473) );
ADDFHX4TS U3740 ( .A(n3707), .B(n3706), .CI(n3705), .CO(n3681), .S(n3814) );
XOR2X2TS U3741 ( .A(n4536), .B(n4535), .Y(n4564) );
XNOR2X2TS U3742 ( .A(n3923), .B(n3723), .Y(n3656) );
NAND2X4TS U3743 ( .A(n2145), .B(n2455), .Y(n2454) );
OAI22X2TS U3744 ( .A0(n2243), .A1(n3169), .B0(n2333), .B1(n3085), .Y(n3171)
);
XNOR2X2TS U3745 ( .A(n3919), .B(FPMULT_Op_MX[22]), .Y(n3085) );
XNOR2X2TS U3746 ( .A(n2480), .B(n3697), .Y(n3810) );
ADDFHX2TS U3747 ( .A(n3728), .B(n3727), .CI(n3726), .CO(n3697), .S(n3846) );
ADDFHX4TS U3748 ( .A(n3720), .B(n3719), .CI(n3718), .CO(n3700), .S(n3818) );
INVX4TS U3749 ( .A(n2146), .Y(n4603) );
NAND2X2TS U3750 ( .A(n4560), .B(n4559), .Y(n4588) );
XNOR2X2TS U3751 ( .A(n2277), .B(FPMULT_Op_MX[11]), .Y(n3404) );
NAND3X6TS U3752 ( .A(n2361), .B(n2395), .C(n2177), .Y(n2360) );
NOR2X2TS U3753 ( .A(n2326), .B(n3404), .Y(n3349) );
XNOR2X2TS U3754 ( .A(n4001), .B(n3136), .Y(n4024) );
NOR2X4TS U3755 ( .A(n3900), .B(FPMULT_Op_MX[4]), .Y(n3063) );
NAND2X2TS U3756 ( .A(n3065), .B(n3062), .Y(n2714) );
AOI21X2TS U3757 ( .A0(n2387), .A1(n3062), .B0(n3052), .Y(n3055) );
XNOR2X2TS U3758 ( .A(n2118), .B(n2131), .Y(n3128) );
NOR2X4TS U3759 ( .A(n2783), .B(n4697), .Y(n4951) );
CLKBUFX2TS U3760 ( .A(n4924), .Y(n4950) );
INVX6TS U3761 ( .A(n4951), .Y(n4925) );
OAI22X2TS U3762 ( .A0(n3424), .A1(n2325), .B0(n3474), .B1(n2236), .Y(n3448)
);
NOR2X4TS U3763 ( .A(n2148), .B(n2149), .Y(n2147) );
AND4X4TS U3764 ( .A(n2385), .B(n4726), .C(n2638), .D(n2618), .Y(n2148) );
AND2X4TS U3765 ( .A(n4692), .B(n4726), .Y(n2149) );
NOR2X2TS U3766 ( .A(n4812), .B(n4815), .Y(n4818) );
XNOR2X2TS U3767 ( .A(n2686), .B(n2276), .Y(n2182) );
ADDFHX2TS U3768 ( .A(n3393), .B(n3392), .CI(n3391), .CO(n3453), .S(n3414) );
NAND2X2TS U3769 ( .A(n2402), .B(n2401), .Y(n3276) );
NOR2X6TS U3770 ( .A(n4197), .B(n4196), .Y(n4649) );
NAND2X6TS U3771 ( .A(n4197), .B(n4196), .Y(n4648) );
NAND2X4TS U3772 ( .A(n2278), .B(n2244), .Y(n3004) );
NAND2X4TS U3773 ( .A(FPMULT_Op_MX[13]), .B(FPMULT_Op_MX[1]), .Y(n3117) );
ADDFHX2TS U3774 ( .A(n3652), .B(n3651), .CI(n3650), .CO(n3281), .S(n3687) );
OAI22X2TS U3775 ( .A0(n2128), .A1(n3903), .B0(n3951), .B1(n3952), .Y(n3955)
);
OAI22X2TS U3776 ( .A0(n2128), .A1(n2806), .B0(n3951), .B1(n3904), .Y(n3954)
);
BUFX12TS U3777 ( .A(n3187), .Y(n3951) );
OAI22X2TS U3778 ( .A0(n3423), .A1(n3971), .B0(n2273), .B1(n3870), .Y(n4018)
);
XOR2X4TS U3779 ( .A(n2492), .B(n2812), .Y(n3740) );
ADDFHX2TS U3780 ( .A(n2185), .B(n3676), .CI(n3675), .CO(n3682), .S(n3709) );
INVX2TS U3781 ( .A(n4260), .Y(n3995) );
INVX12TS U3782 ( .A(n2702), .Y(n2466) );
AO21X4TS U3783 ( .A0(n2247), .A1(n2260), .B0(n2801), .Y(n3318) );
INVX4TS U3784 ( .A(n4443), .Y(n2745) );
ADDFHX4TS U3785 ( .A(n4322), .B(n3288), .CI(n3287), .CO(n3290), .S(n3774) );
ADDFHX2TS U3786 ( .A(n3646), .B(n3645), .CI(n3644), .CO(n3655), .S(n3698) );
NAND2X4TS U3787 ( .A(n4706), .B(n2659), .Y(n2663) );
INVX4TS U3788 ( .A(n4706), .Y(n2661) );
ADDFHX4TS U3789 ( .A(n4160), .B(n4159), .CI(n4158), .CO(n4165), .S(n4167) );
INVX8TS U3790 ( .A(n2668), .Y(n3922) );
OAI22X2TS U3791 ( .A0(n3330), .A1(n2327), .B0(n2275), .B1(n3944), .Y(n3430)
);
ADDFX2TS U3792 ( .A(n3431), .B(n3430), .CI(n3429), .CO(n3483), .S(n3436) );
OAI21X4TS U3793 ( .A0(n3997), .A1(n2552), .B0(n3996), .Y(n2550) );
INVX8TS U3794 ( .A(n2668), .Y(n2243) );
INVX2TS U3795 ( .A(n4025), .Y(n2567) );
NOR2X4TS U3796 ( .A(FPADDSUB_Add_Subt_result[21]), .B(
FPADDSUB_Add_Subt_result[20]), .Y(n5797) );
NAND2BX2TS U3797 ( .AN(FPADDSUB_Add_Subt_result[12]), .B(n6517), .Y(n5948)
);
OAI211X1TS U3798 ( .A0(n6516), .A1(n5948), .B0(n5947), .C0(n5946), .Y(n5949)
);
NAND2X6TS U3799 ( .A(n2151), .B(n2152), .Y(n3264) );
OR2X4TS U3800 ( .A(n2241), .B(n3260), .Y(n2151) );
OR2X2TS U3801 ( .A(n3951), .B(n3164), .Y(n2152) );
ADDFHX4TS U3802 ( .A(n3869), .B(n3868), .CI(n3867), .CO(n3842), .S(n4132) );
BUFX12TS U3803 ( .A(n6360), .Y(n2285) );
ADDFHX2TS U3804 ( .A(n3323), .B(n3322), .CI(n3321), .CO(n3341), .S(n3309) );
NAND2BX1TS U3805 ( .AN(n2336), .B(n2263), .Y(n4032) );
INVX6TS U3806 ( .A(n3198), .Y(n2336) );
XNOR2X1TS U3807 ( .A(n3723), .B(n4088), .Y(n3722) );
OAI22X2TS U3808 ( .A0(n4023), .A1(n2251), .B0(n3848), .B1(n2334), .Y(n4135)
);
XNOR2X2TS U3809 ( .A(n3847), .B(n4048), .Y(n4023) );
AOI21X4TS U3810 ( .A0(n2462), .A1(n2136), .B0(n2540), .Y(n2538) );
BUFX4TS U3811 ( .A(n2468), .Y(n2462) );
INVX6TS U3812 ( .A(n4262), .Y(n4025) );
NAND2X4TS U3813 ( .A(n4104), .B(n4103), .Y(n4508) );
INVX4TS U3814 ( .A(n4421), .Y(n4053) );
BUFX12TS U3815 ( .A(n3187), .Y(n2329) );
CLKINVX3TS U3816 ( .A(n4323), .Y(n3372) );
OAI22X2TS U3817 ( .A0(n3789), .A1(n2335), .B0(n3832), .B1(n2165), .Y(n3873)
);
XNOR2X1TS U3818 ( .A(n3923), .B(n2223), .Y(n4039) );
XNOR2X2TS U3819 ( .A(n3923), .B(n2254), .Y(n3971) );
AND2X4TS U3820 ( .A(n4306), .B(n4305), .Y(n2177) );
OAI22X2TS U3821 ( .A0(n2219), .A1(n3573), .B0(n2448), .B1(n2704), .Y(n3550)
);
ADDFHX2TS U3822 ( .A(n3670), .B(n3669), .CI(n3668), .CO(n3269), .S(n3714) );
NAND2X2TS U3823 ( .A(n2729), .B(n2727), .Y(n3355) );
NAND2BX1TS U3824 ( .AN(n2728), .B(n2726), .Y(n2727) );
BUFX20TS U3825 ( .A(FPMULT_Op_MX[19]), .Y(n6374) );
XNOR2X2TS U3826 ( .A(n3783), .B(n2255), .Y(n3218) );
OAI22X2TS U3827 ( .A0(n2128), .A1(n3025), .B0(n3951), .B1(n2285), .Y(n3152)
);
NOR2X4TS U3828 ( .A(n4516), .B(n4517), .Y(n4549) );
INVX8TS U3829 ( .A(n2817), .Y(n2563) );
INVX6TS U3830 ( .A(n4283), .Y(n3683) );
XOR2X4TS U3831 ( .A(n2282), .B(FPMULT_Op_MY[8]), .Y(n2992) );
OAI22X2TS U3832 ( .A0(n3643), .A1(n3641), .B0(n2259), .B1(n3640), .Y(n3694)
);
OAI22X2TS U3833 ( .A0(n2247), .A1(n3916), .B0(n3925), .B1(n3908), .Y(n3940)
);
ADDFHX4TS U3834 ( .A(n4000), .B(n3999), .CI(n3998), .CO(n4007), .S(n3990) );
XNOR2X2TS U3835 ( .A(n2281), .B(n6380), .Y(n3908) );
NOR2X8TS U3836 ( .A(n4223), .B(n4224), .Y(n4713) );
OAI22X2TS U3837 ( .A0(n2241), .A1(n2285), .B0(n3951), .B1(n2806), .Y(n3332)
);
INVX4TS U3838 ( .A(n4324), .Y(n3297) );
ADDFHX4TS U3839 ( .A(n4113), .B(n4112), .CI(n4111), .CO(n4120), .S(n4122) );
NAND2BX2TS U3840 ( .AN(n2338), .B(n2492), .Y(n3914) );
XOR2X4TS U3841 ( .A(n4153), .B(n2153), .Y(n4159) );
NAND2X2TS U3842 ( .A(n4154), .B(n4153), .Y(n2155) );
OAI22X4TS U3843 ( .A0(n4022), .A1(n4038), .B0(n4021), .B1(n2264), .Y(n4155)
);
OAI22X2TS U3844 ( .A0(n4024), .A1(n2251), .B0(n4023), .B1(n4060), .Y(n4154)
);
INVX4TS U3845 ( .A(n4328), .Y(n3457) );
OAI22X2TS U3846 ( .A0(n2235), .A1(n3044), .B0(n2326), .B1(n3320), .Y(n3319)
);
OAI22X2TS U3847 ( .A0(n2128), .A1(n3164), .B0(n2329), .B1(n3089), .Y(n3267)
);
OAI22X2TS U3848 ( .A0(n2128), .A1(n3089), .B0(n2329), .B1(n3022), .Y(n3082)
);
ADDFHX2TS U3849 ( .A(n3267), .B(n3266), .CI(n3265), .CO(n3161), .S(n3662) );
XNOR2X2TS U3850 ( .A(n6360), .B(n3701), .Y(n3089) );
NAND3X8TS U3851 ( .A(n2473), .B(n2134), .C(n2545), .Y(n2544) );
AND2X4TS U3852 ( .A(n2658), .B(n2419), .Y(n2187) );
NAND2X8TS U3853 ( .A(n2588), .B(n3064), .Y(n3110) );
BUFX16TS U3854 ( .A(n2603), .Y(n2430) );
ADDFHX4TS U3855 ( .A(n3375), .B(n3374), .CI(n3373), .CO(n3421), .S(n3364) );
ADDFHX4TS U3856 ( .A(n4231), .B(n4230), .CI(n4229), .CO(n4246), .S(n4215) );
XNOR2X1TS U3857 ( .A(n3919), .B(n3701), .Y(n3259) );
AND4X8TS U3858 ( .A(n4785), .B(n4783), .C(n4782), .D(n4355), .Y(n2208) );
ADDFHX4TS U3859 ( .A(n3297), .B(n3296), .CI(n3295), .CO(n3882), .S(n3759) );
NAND2X4TS U3860 ( .A(n4746), .B(n4745), .Y(n4826) );
OAI21X1TS U3861 ( .A0(n3571), .A1(n3570), .B0(n2608), .Y(n2606) );
OAI2BB1X2TS U3862 ( .A0N(n3570), .A1N(n3571), .B0(n2606), .Y(n3597) );
NAND2X4TS U3863 ( .A(n2663), .B(n4211), .Y(n2662) );
ADDFHX2TS U3864 ( .A(n3557), .B(n3556), .CI(n3555), .CO(n3581), .S(n3546) );
AND3X8TS U3865 ( .A(n2130), .B(n2450), .C(n4296), .Y(n2188) );
NOR2BX2TS U3866 ( .AN(n2340), .B(n3925), .Y(n4416) );
NAND2BX1TS U3867 ( .AN(n2340), .B(n2277), .Y(n3733) );
OR2X2TS U3868 ( .A(n2337), .B(n2340), .Y(n3195) );
NOR2X8TS U3869 ( .A(n4713), .B(n4716), .Y(n4227) );
ADDFHX2TS U3870 ( .A(n3343), .B(n3342), .CI(n3341), .CO(n3418), .S(n3351) );
OAI2BB1X4TS U3871 ( .A0N(n4005), .A1N(n2691), .B0(n2690), .Y(n4141) );
OAI21X4TS U3872 ( .A0(n2691), .A1(n4005), .B0(n4004), .Y(n2690) );
INVX4TS U3873 ( .A(n4626), .Y(n4650) );
XNOR2X2TS U3874 ( .A(n2563), .B(n6382), .Y(n3827) );
OAI2BB1X2TS U3875 ( .A0N(n3873), .A1N(n3872), .B0(n2649), .Y(n3867) );
INVX12TS U3876 ( .A(n2755), .Y(n3725) );
XNOR2X4TS U3877 ( .A(n6365), .B(n2749), .Y(n2746) );
NAND2X2TS U3878 ( .A(n4415), .B(n4445), .Y(n4475) );
XNOR2X2TS U3879 ( .A(n2284), .B(n6382), .Y(n3201) );
NOR2X8TS U3880 ( .A(n4206), .B(n4205), .Y(n4678) );
NOR2X8TS U3881 ( .A(n2426), .B(n4677), .Y(n2425) );
ADDFHX2TS U3882 ( .A(n3449), .B(n3448), .CI(n3447), .CO(n3514), .S(n3485) );
NAND2X4TS U3883 ( .A(n3900), .B(FPMULT_Op_MX[4]), .Y(n3065) );
ADDFHX4TS U3884 ( .A(n3682), .B(n3681), .CI(n3680), .CO(n3663), .S(n3712) );
XNOR2X4TS U3885 ( .A(n2129), .B(n3919), .Y(n3186) );
OAI22X2TS U3886 ( .A0(n4039), .A1(n4085), .B0(n2264), .B1(n2715), .Y(n4042)
);
XNOR2X4TS U3887 ( .A(n3103), .B(n3098), .Y(n3102) );
XOR2X4TS U3888 ( .A(FPMULT_Op_MY[6]), .B(n6357), .Y(n3103) );
NAND2X6TS U3889 ( .A(n3023), .B(n2643), .Y(n2491) );
ADDFHX4TS U3890 ( .A(n3291), .B(n3290), .CI(n3289), .CO(n3369), .S(n3889) );
BUFX16TS U3891 ( .A(n3734), .Y(n2326) );
ADDFHX2TS U3892 ( .A(n3037), .B(n3036), .CI(n3035), .CO(n3326), .S(n3038) );
NOR2X8TS U3893 ( .A(n4304), .B(n4705), .Y(n2450) );
XOR2X4TS U3894 ( .A(n2683), .B(n4107), .Y(n4114) );
OAI21X2TS U3895 ( .A0(FPMULT_Op_MY[6]), .A1(FPMULT_Op_MY[18]), .B0(
FPMULT_Op_MY[5]), .Y(n3071) );
NAND2X6TS U3896 ( .A(n4503), .B(n4502), .Y(n4513) );
AND2X4TS U3897 ( .A(n2483), .B(n4698), .Y(n2157) );
OR2X8TS U3898 ( .A(n2483), .B(n4698), .Y(n4954) );
OAI22X2TS U3899 ( .A0(n3970), .A1(n2275), .B0(n3423), .B1(n3948), .Y(n4000)
);
XNOR2X2TS U3900 ( .A(n4070), .B(n2254), .Y(n3948) );
NAND2X4TS U3901 ( .A(n4214), .B(n4213), .Y(n4294) );
ADDFHX2TS U3902 ( .A(n3622), .B(n3621), .CI(n3620), .CO(n4216), .S(n4213) );
OAI22X2TS U3903 ( .A0(n3674), .A1(n6359), .B0(n2451), .B1(n2803), .Y(n3549)
);
XOR2X4TS U3904 ( .A(n4545), .B(n4544), .Y(n4563) );
OAI22X2TS U3905 ( .A0(n3423), .A1(n3944), .B0(n2274), .B1(n3943), .Y(n3968)
);
NAND2X4TS U3906 ( .A(n2539), .B(n2538), .Y(n2359) );
ADDFHX4TS U3907 ( .A(n3422), .B(n3421), .CI(n3420), .CO(n3445), .S(n3390) );
ADDFHX4TS U3908 ( .A(n3372), .B(n3371), .CI(n3370), .CO(n3422), .S(n3379) );
XOR2X2TS U3909 ( .A(n3573), .B(n3086), .Y(n2653) );
INVX8TS U3910 ( .A(n5857), .Y(n3086) );
OAI22X2TS U3911 ( .A0(n3744), .A1(n3084), .B0(n3743), .B1(n3028), .Y(n3088)
);
CMPR22X2TS U3912 ( .A(n4044), .B(n4043), .CO(n4255), .S(n4253) );
NAND2X8TS U3913 ( .A(n2384), .B(n4727), .Y(n2381) );
INVX8TS U3914 ( .A(n2180), .Y(n2267) );
OAI21X2TS U3915 ( .A0(n4816), .A1(n4815), .B0(n4814), .Y(n4817) );
XNOR2X4TS U3916 ( .A(n4004), .B(n4429), .Y(n2692) );
ADDFHX4TS U3917 ( .A(n4116), .B(n4115), .CI(n4114), .CO(n4117), .S(n4104) );
ADDFHX4TS U3918 ( .A(n3714), .B(n3713), .CI(n3712), .CO(n4278), .S(n4275) );
NAND2X6TS U3919 ( .A(n2693), .B(n4811), .Y(n2684) );
NAND2BX2TS U3920 ( .AN(n3094), .B(n2720), .Y(n2535) );
AOI21X2TS U3921 ( .A0(n4863), .A1(n4861), .B0(n4859), .Y(n2990) );
XOR2X4TS U3922 ( .A(n5708), .B(FPADDSUB_intDX[31]), .Y(n5004) );
XNOR2X4TS U3923 ( .A(FPADDSUB_intDY[31]), .B(FPADDSUB_intAS), .Y(n5708) );
AOI21X2TS U3924 ( .A0(n4409), .A1(n4374), .B0(n4376), .Y(n4373) );
INVX2TS U3925 ( .A(n4777), .Y(n4795) );
ADDFHX4TS U3926 ( .A(n3815), .B(n3814), .CI(n3813), .CO(n4276), .S(n4274) );
ADDFHX2TS U3927 ( .A(n3306), .B(n2150), .CI(n3305), .CO(n3380), .S(n3291) );
ADDFHX4TS U3928 ( .A(n3270), .B(n3269), .CI(n3268), .CO(n3285), .S(n3661) );
INVX8TS U3929 ( .A(n2639), .Y(n3187) );
NAND2X2TS U3930 ( .A(n4665), .B(n2159), .Y(n4666) );
XNOR2X2TS U3931 ( .A(n3977), .B(n2263), .Y(n3848) );
NOR2X8TS U3932 ( .A(n4819), .B(n4815), .Y(n2693) );
XOR2X4TS U3933 ( .A(FPMULT_Op_MY[20]), .B(n6359), .Y(n3024) );
OAI22X2TS U3934 ( .A0(n2718), .A1(n3165), .B0(n3090), .B1(n2451), .Y(n3266)
);
NAND2X8TS U3935 ( .A(n2632), .B(n4665), .Y(n4677) );
NAND2X6TS U3936 ( .A(n4744), .B(n4743), .Y(n4958) );
OR2X2TS U3937 ( .A(n4253), .B(n4252), .Y(n2802) );
OAI22X2TS U3938 ( .A0(n2243), .A1(n6909), .B0(n3914), .B1(n2333), .Y(n4252)
);
OAI22X1TS U3939 ( .A0(n2491), .A1(n2492), .B0(n6909), .B1(n2333), .Y(n3030)
);
XNOR2X2TS U3940 ( .A(FPMULT_Op_MY[16]), .B(n6909), .Y(n2639) );
NOR2X8TS U3941 ( .A(n4128), .B(n4127), .Y(n4570) );
NAND2X6TS U3942 ( .A(n4954), .B(n4925), .Y(n4943) );
INVX6TS U3943 ( .A(n2989), .Y(n2969) );
NOR2X6TS U3944 ( .A(n2506), .B(n4773), .Y(n4774) );
ADDFHX4TS U3945 ( .A(n3523), .B(n3522), .CI(n3521), .CO(n3551), .S(n3508) );
ADDFHX2TS U3946 ( .A(n6374), .B(n3792), .CI(n3520), .CO(n3553), .S(n3523) );
AO21X1TS U3947 ( .A0(n3744), .A1(n2328), .B0(n2819), .Y(n3522) );
OAI21X4TS U3948 ( .A0(n3615), .A1(n2672), .B0(n3614), .Y(n2671) );
NOR2X8TS U3949 ( .A(n2670), .B(n2511), .Y(n4218) );
NAND2X4TS U3950 ( .A(n4129), .B(n4130), .Y(n4573) );
ADDFHX2TS U3951 ( .A(n3088), .B(n3086), .CI(n3087), .CO(n3095), .S(n3162) );
XNOR2X4TS U3952 ( .A(n2817), .B(n2806), .Y(n3189) );
XOR2X2TS U3953 ( .A(n2789), .B(n3189), .Y(n2788) );
NOR2X2TS U3954 ( .A(n4258), .B(n4423), .Y(n3999) );
INVX2TS U3955 ( .A(n4813), .Y(n4816) );
NOR2X4TS U3956 ( .A(n3701), .B(FPMULT_Op_MX[8]), .Y(n3132) );
XNOR2X2TS U3957 ( .A(n3751), .B(n2224), .Y(n3784) );
OAI211X1TS U3958 ( .A0(n5911), .A1(n6801), .B0(n5910), .C0(n5909), .Y(n5912)
);
NOR2X4TS U3959 ( .A(n4502), .B(n4503), .Y(n4515) );
ADDFHX4TS U3960 ( .A(n3326), .B(n3325), .CI(n3324), .CO(n4503), .S(n4451) );
XOR2X4TS U3961 ( .A(n4844), .B(n4843), .Y(FPMULT_Sgf_operation_Result[37])
);
XOR2X4TS U3962 ( .A(n4641), .B(n2175), .Y(n2353) );
OAI21X4TS U3963 ( .A0(n4485), .A1(n6269), .B0(n4486), .Y(n4472) );
NOR2X4TS U3964 ( .A(n4443), .B(n4444), .Y(n4485) );
XOR2X4TS U3965 ( .A(n2596), .B(n2595), .Y(FPMULT_Sgf_operation_Result[35])
);
ADDFHX4TS U3966 ( .A(n3161), .B(n3162), .CI(n3163), .CO(n3235), .S(n3286) );
ADDFHX2TS U3967 ( .A(n3172), .B(n3171), .CI(n3170), .CO(n3163), .S(n3268) );
INVX2TS U3968 ( .A(n4550), .Y(n4537) );
OAI21X1TS U3969 ( .A0(n6190), .A1(n6186), .B0(n6187), .Y(n4933) );
OAI21X4TS U3970 ( .A0(n4900), .A1(n4896), .B0(n4897), .Y(n4863) );
AOI21X2TS U3971 ( .A0(n4287), .A1(n2176), .B0(n4217), .Y(n2524) );
XNOR2X4TS U3972 ( .A(n2669), .B(n4960), .Y(n4961) );
XNOR2X4TS U3973 ( .A(n2369), .B(n4693), .Y(n4701) );
NAND2X8TS U3974 ( .A(n2209), .B(n4319), .Y(n4409) );
NAND2X4TS U3975 ( .A(n4789), .B(n4785), .Y(n4786) );
OAI21X4TS U3976 ( .A0(n4467), .A1(n4470), .B0(n4468), .Y(n4455) );
AOI21X4TS U3977 ( .A0(n4480), .A1(n4092), .B0(n4091), .Y(n4470) );
NOR2X4TS U3978 ( .A(n4094), .B(n4093), .Y(n4467) );
ADDFHX2TS U3979 ( .A(n4078), .B(n4077), .CI(n4076), .CO(n4095), .S(n4094) );
INVX2TS U3980 ( .A(n4811), .Y(n4812) );
NOR2X8TS U3981 ( .A(n4394), .B(n4794), .Y(n4782) );
AOI21X4TS U3982 ( .A0(n4690), .A1(n2802), .B0(n4254), .Y(n4684) );
XNOR2X4TS U3983 ( .A(n2502), .B(n2501), .Y(n2709) );
OAI21X4TS U3984 ( .A0(n4650), .A1(n4649), .B0(n4648), .Y(n2502) );
OAI21X4TS U3985 ( .A0(n4952), .A1(n4943), .B0(n2782), .Y(n4948) );
NAND2X4TS U3986 ( .A(n2839), .B(n2838), .Y(n2876) );
NOR2X1TS U3987 ( .A(n5097), .B(n2837), .Y(n2838) );
ADDFHX2TS U3988 ( .A(n2854), .B(n2853), .CI(n2852), .CO(n2873), .S(n5928) );
CLKAND2X2TS U3989 ( .A(n5247), .B(FPADDSUB_DmP[29]), .Y(n2842) );
INVX2TS U3990 ( .A(n3107), .Y(n2584) );
INVX8TS U3991 ( .A(n2605), .Y(n4001) );
INVX2TS U3992 ( .A(n2586), .Y(n2751) );
NOR2X1TS U3993 ( .A(n3138), .B(n2365), .Y(n2642) );
OAI21X1TS U3994 ( .A0(n3543), .A1(n3544), .B0(n3542), .Y(n2576) );
NAND2X2TS U3995 ( .A(n2464), .B(n2463), .Y(n4240) );
INVX2TS U3996 ( .A(n3229), .Y(n2593) );
OAI2BB2XLTS U3997 ( .B0(FPADDSUB_intDY[12]), .B1(n5643), .A0N(
FPADDSUB_intDX[13]), .A1N(n6725), .Y(n5655) );
OAI2BB2XLTS U3998 ( .B0(n5651), .B1(n5658), .A0N(n5650), .A1N(n5649), .Y(
n5654) );
NOR2X1TS U3999 ( .A(n4341), .B(n4340), .Y(n4395) );
NOR2X1TS U4000 ( .A(n4395), .B(n4399), .Y(n4402) );
NOR2X4TS U4001 ( .A(n6186), .B(n4929), .Y(n4657) );
XOR2X1TS U4002 ( .A(n2969), .B(n2945), .Y(n2948) );
NAND2X1TS U4003 ( .A(n4290), .B(n4314), .Y(n4291) );
OR2X4TS U4004 ( .A(n2585), .B(n2637), .Y(n2700) );
NAND2X1TS U4005 ( .A(n4301), .B(n4300), .Y(n4302) );
INVX2TS U4006 ( .A(n4296), .Y(n2419) );
NAND2X1TS U4007 ( .A(n2948), .B(n2947), .Y(n6055) );
CLKAND2X2TS U4008 ( .A(n5247), .B(FPADDSUB_DmP[28]), .Y(n2843) );
MX2X1TS U4009 ( .A(FPMULT_Op_MX[23]), .B(FPMULT_exp_oper_result[0]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[0]) );
MX2X1TS U4010 ( .A(FPMULT_Op_MX[26]), .B(FPMULT_exp_oper_result[3]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[3]) );
INVX2TS U4011 ( .A(n3109), .Y(n2582) );
NOR2X2TS U4012 ( .A(n3188), .B(n2790), .Y(n2789) );
OAI22X1TS U4013 ( .A0(n3331), .A1(n3255), .B0(n3425), .B1(n2331), .Y(n3429)
);
XOR2X1TS U4014 ( .A(n3076), .B(n3075), .Y(n3077) );
NOR2X2TS U4015 ( .A(n2461), .B(n3074), .Y(n3076) );
NAND2X2TS U4016 ( .A(n2774), .B(n2405), .Y(n2404) );
INVX2TS U4017 ( .A(n2526), .Y(n2405) );
INVX4TS U4018 ( .A(n4252), .Y(n3928) );
XOR2X1TS U4019 ( .A(n2283), .B(n2813), .Y(n2529) );
NAND2X4TS U4020 ( .A(n2432), .B(n2517), .Y(n2997) );
OAI22X2TS U4021 ( .A0(n4022), .A1(n2264), .B0(n4085), .B1(n2652), .Y(n4027)
);
ADDHX1TS U4022 ( .A(n3955), .B(n3954), .CO(n3979), .S(n3945) );
ADDFHX2TS U4023 ( .A(n3536), .B(n3535), .CI(n3534), .CO(n3569), .S(n3564) );
AOI2BB2XLTS U4024 ( .B0(FPADDSUB_intDX[3]), .B1(n6789), .A0N(
FPADDSUB_intDY[2]), .A1N(n5635), .Y(n5636) );
OAI21XLTS U4025 ( .A0(FPADDSUB_intDX[3]), .A1(n6789), .B0(FPADDSUB_intDX[2]),
.Y(n5635) );
NAND2X4TS U4026 ( .A(n4225), .B(n4226), .Y(n4717) );
BUFX6TS U4027 ( .A(n3257), .Y(n4072) );
NOR2X2TS U4028 ( .A(FPMULT_Op_MX[22]), .B(n3623), .Y(n2737) );
NAND2X1TS U4029 ( .A(n2453), .B(n2452), .Y(n3576) );
CLKAND2X2TS U4030 ( .A(n4501), .B(n4514), .Y(n2175) );
INVX2TS U4031 ( .A(n4629), .Y(n4558) );
AOI21X1TS U4032 ( .A0(n6104), .A1(n6145), .B0(n6103), .Y(n6137) );
NAND2X1TS U4033 ( .A(FPMULT_Sgf_normalized_result[5]), .B(
FPMULT_Sgf_normalized_result[4]), .Y(n6146) );
XOR2X1TS U4034 ( .A(n2988), .B(n2958), .Y(n2960) );
XOR2X1TS U4035 ( .A(n2969), .B(n2954), .Y(n2956) );
NOR2X4TS U4036 ( .A(n4943), .B(n4944), .Y(n4703) );
NAND2X1TS U4037 ( .A(n4246), .B(n4245), .Y(n4247) );
NAND2X1TS U4038 ( .A(n4335), .B(n4334), .Y(n4359) );
NAND2X1TS U4039 ( .A(n4396), .B(n4402), .Y(n4405) );
NAND2X4TS U4040 ( .A(n2359), .B(n2579), .Y(n2358) );
XNOR2X2TS U4041 ( .A(n4310), .B(n4309), .Y(n4750) );
NAND2X1TS U4042 ( .A(n4308), .B(n4307), .Y(n4309) );
NAND2X2TS U4043 ( .A(n4426), .B(n4425), .Y(n6234) );
NAND2X2TS U4044 ( .A(n2353), .B(n4497), .Y(n6292) );
INVX2TS U4045 ( .A(n6215), .Y(n4420) );
NOR3XLTS U4046 ( .A(Data_1[2]), .B(Data_1[5]), .C(Data_1[4]), .Y(n6321) );
CLKAND2X2TS U4047 ( .A(n2983), .B(FPADDSUB_Sgf_normalized_result[0]), .Y(
n2889) );
INVX2TS U4048 ( .A(n6226), .Y(n6232) );
MX2X1TS U4049 ( .A(FPADDSUB_DMP[25]), .B(FPADDSUB_exp_oper_result[2]), .S0(
n2983), .Y(n2865) );
NAND2BXLTS U4050 ( .AN(FPADDSUB_Add_Subt_result[1]), .B(
FPADDSUB_Add_Subt_result[0]), .Y(n5792) );
INVX2TS U4051 ( .A(FPADDSUB_FS_Module_state_reg[0]), .Y(n5411) );
NAND3XLTS U4052 ( .A(dataB[28]), .B(dataB[23]), .C(dataB[25]), .Y(n6336) );
AOI31XLTS U4053 ( .A0(n6334), .A1(n6333), .A2(n6332), .B0(n6339), .Y(n6337)
);
NOR2X1TS U4054 ( .A(n2960), .B(n2959), .Y(n6007) );
NAND2X1TS U4055 ( .A(n2960), .B(n2959), .Y(n6008) );
NAND2X1TS U4056 ( .A(n2956), .B(n2955), .Y(n6017) );
NAND2X1TS U4057 ( .A(n2832), .B(n6033), .Y(n2953) );
MX2X1TS U4058 ( .A(FPMULT_Op_MX[24]), .B(FPMULT_exp_oper_result[1]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[1]) );
INVX2TS U4059 ( .A(n4752), .Y(n2611) );
NAND3X6TS U4060 ( .A(n2698), .B(n2635), .C(n2656), .Y(n2615) );
INVX2TS U4061 ( .A(n4751), .Y(n2566) );
BUFX3TS U4062 ( .A(n2825), .Y(n5713) );
CLKAND2X2TS U4063 ( .A(n5091), .B(FPADDSUB_Sgf_normalized_result[1]), .Y(
n2885) );
NAND2X1TS U4064 ( .A(n5096), .B(n4967), .Y(n5424) );
INVX2TS U4065 ( .A(n4928), .Y(n6190) );
OA21X2TS U4066 ( .A0(n2883), .A1(n2213), .B0(n2882), .Y(n2835) );
CLKXOR2X2TS U4067 ( .A(FPMULT_Op_MY[4]), .B(FPMULT_Op_MY[16]), .Y(n3188) );
INVX2TS U4068 ( .A(n2616), .Y(n3053) );
INVX2TS U4069 ( .A(n3063), .Y(n3062) );
INVX2TS U4070 ( .A(n3191), .Y(n2627) );
NAND2BXLTS U4071 ( .AN(n4088), .B(n2131), .Y(n3252) );
XNOR2X2TS U4072 ( .A(n3923), .B(n2252), .Y(n3789) );
NOR2X4TS U4073 ( .A(FPMULT_Op_MX[13]), .B(FPMULT_Op_MX[1]), .Y(n3116) );
INVX4TS U4074 ( .A(n3114), .Y(n3123) );
NOR2X2TS U4075 ( .A(n3608), .B(n2601), .Y(n3402) );
CLKXOR2X2TS U4076 ( .A(n2276), .B(n2820), .Y(n3315) );
XNOR2X1TS U4077 ( .A(n3518), .B(n2255), .Y(n3256) );
ADDFX2TS U4078 ( .A(n3245), .B(n3244), .CI(n3243), .CO(n3288), .S(n3767) );
INVX2TS U4079 ( .A(n4446), .Y(n3287) );
XNOR2X2TS U4080 ( .A(n3229), .B(n2224), .Y(n3753) );
INVX2TS U4081 ( .A(n4442), .Y(n3802) );
CLKAND2X2TS U4082 ( .A(n3079), .B(n3108), .Y(n3080) );
XOR2X2TS U4083 ( .A(n2654), .B(n3067), .Y(n3847) );
NAND2X1TS U4084 ( .A(n3066), .B(n3109), .Y(n3067) );
XNOR2X2TS U4085 ( .A(n4037), .B(n2254), .Y(n3970) );
OAI22X1TS U4086 ( .A0(n3303), .A1(n3899), .B0(n3181), .B1(n2257), .Y(n3306)
);
ADDFHX2TS U4087 ( .A(n3378), .B(n3377), .CI(n3376), .CO(n3420), .S(n3381) );
OAI22X1TS U4088 ( .A0(n3303), .A1(n2257), .B0(n3363), .B1(n2335), .Y(n3377)
);
INVX2TS U4089 ( .A(n4502), .Y(n3371) );
NAND2X4TS U4090 ( .A(n3194), .B(n3182), .Y(n2378) );
CLKXOR2X2TS U4091 ( .A(FPMULT_Op_MY[8]), .B(FPMULT_Op_MY[20]), .Y(n3074) );
NAND2X4TS U4092 ( .A(FPMULT_Op_MX[14]), .B(FPMULT_Op_MX[2]), .Y(n3122) );
NOR2X4TS U4093 ( .A(n6373), .B(FPMULT_Op_MX[5]), .Y(n2616) );
NOR2X4TS U4094 ( .A(n3792), .B(FPMULT_Op_MX[6]), .Y(n3107) );
NAND2X2TS U4095 ( .A(n3792), .B(FPMULT_Op_MX[6]), .Y(n3109) );
NAND2X1TS U4096 ( .A(n6374), .B(FPMULT_Op_MX[7]), .Y(n3108) );
NAND2X2TS U4097 ( .A(n4351), .B(n2679), .Y(n2678) );
AO21X1TS U4098 ( .A0(n3423), .A1(n2275), .B0(n3944), .Y(n3449) );
INVX2TS U4099 ( .A(n3933), .Y(n3474) );
INVX2TS U4100 ( .A(n3977), .Y(n3519) );
INVX2TS U4101 ( .A(n3518), .Y(n3537) );
XNOR2X1TS U4102 ( .A(n3977), .B(n2255), .Y(n3711) );
INVX2TS U4103 ( .A(n2272), .Y(n2274) );
OAI22X2TS U4104 ( .A0(n3689), .A1(n2335), .B0(n3688), .B1(n2257), .Y(n2776)
);
INVX2TS U4105 ( .A(n4270), .Y(n2648) );
INVX2TS U4106 ( .A(n4431), .Y(n2665) );
INVX2TS U4107 ( .A(n4269), .Y(n2666) );
XNOR2X1TS U4108 ( .A(n3933), .B(n2255), .Y(n3809) );
XNOR2X1TS U4109 ( .A(n4001), .B(n2255), .Y(n3871) );
XNOR2X2TS U4110 ( .A(FPMULT_Op_MY[11]), .B(FPMULT_Op_MX[2]), .Y(n3009) );
OAI22X1TS U4111 ( .A0(n3735), .A1(n2998), .B0(n3734), .B1(n3014), .Y(n3013)
);
ADDFHX2TS U4112 ( .A(n3043), .B(n3042), .CI(n3041), .CO(n3314), .S(n3039) );
ADDFHX2TS U4113 ( .A(n3319), .B(n3318), .CI(n3317), .CO(n3352), .S(n3313) );
ADDFHX2TS U4114 ( .A(n3465), .B(n3464), .CI(n3463), .CO(n3491), .S(n3460) );
INVX2TS U4115 ( .A(n4333), .Y(n3465) );
INVX2TS U4116 ( .A(n4542), .Y(n3464) );
ADDFHX2TS U4117 ( .A(n3224), .B(n3223), .CI(n3222), .CO(n3289), .S(n3761) );
ADDFHX2TS U4118 ( .A(n3141), .B(n3140), .CI(n3139), .CO(n3366), .S(n3298) );
NAND2BX1TS U4119 ( .AN(n3475), .B(n2774), .Y(n2408) );
XNOR2X2TS U4120 ( .A(n3977), .B(n2224), .Y(n4022) );
XOR2X2TS U4121 ( .A(n3518), .B(n2222), .Y(n4021) );
INVX2TS U4122 ( .A(n4425), .Y(n3996) );
NAND2X2TS U4123 ( .A(n3931), .B(n2495), .Y(n2499) );
NAND2X2TS U4124 ( .A(n4424), .B(n2500), .Y(n2495) );
NAND2X2TS U4125 ( .A(n3932), .B(n2498), .Y(n2497) );
INVX2TS U4126 ( .A(n2500), .Y(n2498) );
NAND2X2TS U4127 ( .A(n2774), .B(n2400), .Y(n2399) );
INVX2TS U4128 ( .A(n3501), .Y(n2400) );
INVX2TS U4129 ( .A(n4517), .Y(n3434) );
ADDFHX2TS U4130 ( .A(n3462), .B(n3461), .CI(n3460), .CO(n3493), .S(n3446) );
NAND2X1TS U4131 ( .A(n3573), .B(FPMULT_Op_MX[9]), .Y(n3177) );
NOR2X4TS U4132 ( .A(n3573), .B(FPMULT_Op_MX[9]), .Y(n3176) );
NOR2X4TS U4133 ( .A(n2616), .B(n3063), .Y(n3111) );
OR2X6TS U4134 ( .A(n2616), .B(n3065), .Y(n2588) );
INVX2TS U4135 ( .A(n3108), .Y(n2590) );
NOR2X2TS U4136 ( .A(n3176), .B(n3132), .Y(n3182) );
ADDHX1TS U4137 ( .A(n3167), .B(n3166), .CO(n3170), .S(n3262) );
OAI22X1TS U4138 ( .A0(n2466), .A1(n2339), .B0(n2448), .B1(n6379), .Y(n3166)
);
NAND2X1TS U4139 ( .A(n2192), .B(n2219), .Y(n3167) );
CLKAND2X2TS U4140 ( .A(n2731), .B(n2337), .Y(n2185) );
OAI22X1TS U4141 ( .A0(n3257), .A1(n2653), .B0(n2816), .B1(n2647), .Y(n3676)
);
OAI2BB2XLTS U4142 ( .B0(FPADDSUB_intDY[0]), .B1(n5632), .A0N(
FPADDSUB_intDX[1]), .A1N(n6790), .Y(n5634) );
NAND2BXLTS U4143 ( .AN(FPADDSUB_intDX[2]), .B(FPADDSUB_intDY[2]), .Y(n5633)
);
INVX2TS U4144 ( .A(n2776), .Y(n2604) );
INVX2TS U4145 ( .A(n4267), .Y(n2455) );
OAI22X2TS U4146 ( .A0(n3832), .A1(n3899), .B0(n3851), .B1(n2165), .Y(n4019)
);
INVX2TS U4147 ( .A(n4429), .Y(n2691) );
INVX2TS U4148 ( .A(n4157), .Y(n2771) );
NAND2X1TS U4149 ( .A(n2774), .B(n2403), .Y(n2402) );
INVX2TS U4150 ( .A(n3272), .Y(n2403) );
ADDFHX2TS U4151 ( .A(n3215), .B(n3214), .CI(n3213), .CO(n3221), .S(n3246) );
ADDFX2TS U4152 ( .A(n3212), .B(n3211), .CI(n3210), .CO(n3220), .S(n3247) );
ADDFHX2TS U4153 ( .A(n4075), .B(n4074), .CI(n4668), .CO(n4079), .S(n4082) );
NAND2X1TS U4154 ( .A(n2564), .B(n2563), .Y(n3405) );
OR2X2TS U4155 ( .A(n3350), .B(n3349), .Y(n3406) );
ADDFHX2TS U4156 ( .A(n3040), .B(n3039), .CI(n3038), .CO(n3325), .S(n3219) );
INVX2TS U4157 ( .A(n2263), .Y(n4033) );
INVX2TS U4158 ( .A(n3752), .Y(n4038) );
OAI22X1TS U4159 ( .A0(n2211), .A1(n2529), .B0(n3695), .B1(n2526), .Y(n3342)
);
ADDFHX2TS U4160 ( .A(n3311), .B(n3310), .CI(n3309), .CO(n3359), .S(n3312) );
ADDFHX2TS U4161 ( .A(n3353), .B(n3352), .CI(n3351), .CO(n3416), .S(n3357) );
XNOR2X1TS U4162 ( .A(n6360), .B(n6373), .Y(n3677) );
XOR2X1TS U4163 ( .A(n6099), .B(n2749), .Y(n3678) );
CLKXOR2X2TS U4164 ( .A(n3701), .B(n3086), .Y(n2651) );
XOR2X1TS U4165 ( .A(FPMULT_Op_MX[14]), .B(n2747), .Y(n3739) );
INVX2TS U4166 ( .A(n2643), .Y(n2365) );
INVX4TS U4167 ( .A(n2772), .Y(n2773) );
ADDFHX2TS U4168 ( .A(n3443), .B(n3442), .CI(n3441), .CO(n3530), .S(n3444) );
XNOR2X1TS U4169 ( .A(n3919), .B(n6099), .Y(n3902) );
XNOR2X1TS U4170 ( .A(n3919), .B(FPMULT_Op_MX[14]), .Y(n3910) );
XNOR2X1TS U4171 ( .A(n3229), .B(n2131), .Y(n3618) );
NAND2X1TS U4172 ( .A(n3191), .B(n2827), .Y(n3133) );
NOR2X1TS U4173 ( .A(FPMULT_Op_MX[22]), .B(FPMULT_Op_MX[10]), .Y(n3192) );
AND2X2TS U4174 ( .A(n3182), .B(n2628), .Y(n3193) );
INVX2TS U4175 ( .A(n3426), .Y(n2220) );
NAND2BX2TS U4176 ( .AN(n4643), .B(n3631), .Y(n2463) );
OAI22X1TS U4177 ( .A0(n3744), .A1(n3168), .B0(n2328), .B1(n3084), .Y(n3172)
);
OAI21X1TS U4178 ( .A0(n2818), .A1(n2221), .B0(n2373), .Y(n2371) );
OAI21X1TS U4179 ( .A0(n2374), .A1(n3900), .B0(n2645), .Y(n3157) );
NAND2X1TS U4180 ( .A(n2731), .B(n2824), .Y(n2645) );
INVX2TS U4181 ( .A(n4212), .Y(n2659) );
ADDFHX2TS U4182 ( .A(n3560), .B(n3559), .CI(n3558), .CO(n3570), .S(n3542) );
XOR2X2TS U4183 ( .A(n2722), .B(n3816), .Y(n4179) );
XOR2X1TS U4184 ( .A(n2277), .B(n2820), .Y(n3207) );
XNOR2X1TS U4185 ( .A(FPMULT_Op_MX[7]), .B(FPMULT_Op_MY[1]), .Y(n3825) );
INVX8TS U4186 ( .A(n2122), .Y(n2242) );
XNOR2X1TS U4187 ( .A(n2281), .B(FPMULT_Op_MX[6]), .Y(n3730) );
XNOR2X1TS U4188 ( .A(n2278), .B(FPMULT_Op_MX[8]), .Y(n2477) );
INVX2TS U4189 ( .A(n3560), .Y(n4580) );
INVX2TS U4190 ( .A(n2267), .Y(n2270) );
ADDHX1TS U4191 ( .A(n3854), .B(n3853), .CO(n3799), .S(n3983) );
OAI22X1TS U4192 ( .A0(n2245), .A1(n2819), .B0(n2328), .B1(n2171), .Y(n3853)
);
ADDFHX2TS U4193 ( .A(n3750), .B(n3749), .CI(n3748), .CO(n3815), .S(n3833) );
OAI22X1TS U4194 ( .A0(n4072), .A1(n2651), .B0(n2816), .B1(n2653), .Y(n3750)
);
OAI22X1TS U4195 ( .A0(n4072), .A1(n3855), .B0(n3793), .B1(n2816), .Y(n3859)
);
CLKXOR2X2TS U4196 ( .A(n6379), .B(n3086), .Y(n2780) );
CLKAND2X2TS U4197 ( .A(n2365), .B(n2339), .Y(n2183) );
OAI22X2TS U4198 ( .A0(n4047), .A1(n2816), .B0(n3257), .B1(n2780), .Y(n4251)
);
OAI2BB1X2TS U4199 ( .A0N(n4010), .A1N(n4011), .B0(n2487), .Y(n4168) );
ADDFHX2TS U4200 ( .A(n3980), .B(n3979), .CI(n3978), .CO(n4262), .S(n4260) );
AOI21X2TS U4201 ( .A0(n4696), .A1(n2821), .B0(n4259), .Y(n4730) );
NAND2X6TS U4202 ( .A(n4218), .B(n2450), .Y(n4228) );
INVX2TS U4203 ( .A(n3095), .Y(n2720) );
INVX2TS U4204 ( .A(n3149), .Y(n2728) );
OAI21X1TS U4205 ( .A0(n2726), .A1(n3149), .B0(n3148), .Y(n2729) );
ADDFHX2TS U4206 ( .A(n2799), .B(n3333), .CI(n3332), .CO(n3397), .S(n3339) );
AO21XLTS U4207 ( .A0(n2241), .A1(n3951), .B0(n2806), .Y(n3391) );
OAI22X1TS U4208 ( .A0(n2718), .A1(n2624), .B0(n3394), .B1(n2451), .Y(n3393)
);
ADDFHX2TS U4209 ( .A(n3398), .B(n3397), .CI(n3396), .CO(n3451), .S(n3415) );
ADDFHX2TS U4210 ( .A(n3473), .B(n3472), .CI(n3471), .CO(n3506), .S(n3452) );
NAND2X2TS U4211 ( .A(n4215), .B(n4216), .Y(n4288) );
OR2X4TS U4212 ( .A(n4216), .B(n4215), .Y(n2176) );
OR2X6TS U4213 ( .A(n4214), .B(n4213), .Y(n4295) );
INVX2TS U4214 ( .A(n4706), .Y(n2540) );
NOR2X1TS U4215 ( .A(n4274), .B(n4273), .Y(n4297) );
ADDHX1TS U4216 ( .A(n3861), .B(n3860), .CO(n3828), .S(n3986) );
OAI22X1TS U4217 ( .A0(n3735), .A1(n2815), .B0(n3734), .B1(n3733), .Y(n3860)
);
OAI22X1TS U4218 ( .A0(n3735), .A1(n3732), .B0(n3731), .B1(n3734), .Y(n3861)
);
NOR2X1TS U4219 ( .A(n2164), .B(n2355), .Y(n3964) );
INVX6TS U4220 ( .A(n2122), .Y(n2549) );
XOR2X1TS U4221 ( .A(n6380), .B(n2556), .Y(n3959) );
NAND2X4TS U4222 ( .A(n4101), .B(n4102), .Y(n4453) );
NAND2X1TS U4223 ( .A(n4447), .B(n4446), .Y(n4463) );
INVX2TS U4224 ( .A(n3222), .Y(n2160) );
INVX2TS U4225 ( .A(n4473), .Y(n4458) );
OAI21X1TS U4226 ( .A0(n4459), .A1(n4474), .B0(n4475), .Y(n4460) );
INVX2TS U4227 ( .A(n4472), .Y(n4459) );
NOR2X4TS U4228 ( .A(n4126), .B(n4125), .Y(n4532) );
OAI21X1TS U4229 ( .A0(n4538), .A1(n4549), .B0(n4553), .Y(n4539) );
NAND2X1TS U4230 ( .A(n4542), .B(n4541), .Y(n4551) );
INVX4TS U4231 ( .A(n6098), .Y(n2340) );
XNOR2X2TS U4232 ( .A(n2278), .B(n6380), .Y(n4046) );
NAND2X1TS U4233 ( .A(n4581), .B(n4580), .Y(n4589) );
NOR2X2TS U4234 ( .A(n4559), .B(n4560), .Y(n4577) );
OAI21X1TS U4235 ( .A0(n4638), .A1(n4577), .B0(n4588), .Y(n4578) );
XOR2X1TS U4236 ( .A(FPMULT_Op_MY[1]), .B(n2820), .Y(n3905) );
XOR2X2TS U4237 ( .A(n2278), .B(n2601), .Y(n2600) );
NOR2X1TS U4238 ( .A(n6042), .B(n6049), .Y(n2930) );
INVX2TS U4239 ( .A(n4716), .Y(n4718) );
NAND2X2TS U4240 ( .A(n4045), .B(n4072), .Y(n4668) );
CLKBUFX2TS U4241 ( .A(n2781), .Y(n2159) );
NOR2X1TS U4242 ( .A(n4256), .B(n4255), .Y(n4681) );
NAND2X1TS U4243 ( .A(n4256), .B(n4255), .Y(n4682) );
NAND2X1TS U4244 ( .A(n4258), .B(n4257), .Y(n4694) );
OAI21X2TS U4245 ( .A0(n4684), .A1(n4681), .B0(n4682), .Y(n4696) );
OR2X6TS U4246 ( .A(n4171), .B(n4170), .Y(n4601) );
OAI2BB1X2TS U4247 ( .A0N(n4557), .A1N(n4610), .B0(n4609), .Y(n4611) );
AOI21X1TS U4248 ( .A0(n4608), .A1(n4595), .B0(n4632), .Y(n4609) );
NAND2X1TS U4249 ( .A(n4263), .B(n4262), .Y(n4740) );
BUFX3TS U4250 ( .A(FPADDSUB_FSM_selector_A), .Y(n2970) );
NAND2X1TS U4251 ( .A(n6094), .B(n6108), .Y(n5809) );
OAI2BB1X1TS U4252 ( .A0N(n2737), .A1N(n4233), .B0(n2735), .Y(n4234) );
AOI21X1TS U4253 ( .A0(n4707), .A1(n4272), .B0(n4271), .Y(n4320) );
NOR2X2TS U4254 ( .A(n4277), .B(n4278), .Y(n4311) );
NAND2X1TS U4255 ( .A(n4278), .B(n4277), .Y(n4314) );
NOR2X2TS U4256 ( .A(n4299), .B(n4297), .Y(n4312) );
OAI21X2TS U4257 ( .A0(n4299), .A1(n4307), .B0(n4300), .Y(n4317) );
NAND2X1TS U4258 ( .A(n4276), .B(n4275), .Y(n4300) );
NAND2X4TS U4259 ( .A(n4295), .B(n4294), .Y(n4296) );
INVX2TS U4260 ( .A(n4304), .Y(n4306) );
INVX2TS U4261 ( .A(n2177), .Y(n2579) );
NAND2X1TS U4262 ( .A(n4274), .B(n4273), .Y(n4307) );
INVX2TS U4263 ( .A(n4320), .Y(n4310) );
AOI211X1TS U4264 ( .A0(FPADDSUB_intDY[28]), .A1(n6724), .B0(n5627), .C0(
n5625), .Y(n5678) );
OA21XLTS U4265 ( .A0(n4635), .A1(n4634), .B0(n4633), .Y(n4636) );
OR2X1TS U4266 ( .A(n4643), .B(n4642), .Y(n4645) );
NOR2X1TS U4267 ( .A(n6074), .B(n6087), .Y(n6062) );
OR2X1TS U4268 ( .A(n4668), .B(n4667), .Y(n4670) );
NAND2X1TS U4269 ( .A(n4725), .B(n2621), .Y(n4693) );
NAND2X1TS U4270 ( .A(n4735), .B(n4734), .Y(n4736) );
NOR3X1TS U4271 ( .A(n6357), .B(n2730), .C(n2205), .Y(n6364) );
INVX2TS U4272 ( .A(n5533), .Y(n5569) );
MX2X1TS U4273 ( .A(FPADDSUB_DMP[21]), .B(FPADDSUB_Sgf_normalized_result[23]),
.S0(FPADDSUB_FSM_selector_A), .Y(n2978) );
NAND2X1TS U4274 ( .A(n4329), .B(n4328), .Y(n4383) );
NAND2X1TS U4275 ( .A(n4351), .B(n4350), .Y(n4398) );
NAND2X1TS U4276 ( .A(n2733), .B(n2732), .Y(n4759) );
OAI2BB1X1TS U4277 ( .A0N(n2530), .A1N(n2704), .B0(n3607), .Y(n2733) );
NAND2X1TS U4278 ( .A(n2731), .B(n2829), .Y(n2732) );
XNOR2X2TS U4279 ( .A(n3623), .B(n2704), .Y(n4758) );
XNOR2X2TS U4280 ( .A(n2278), .B(n6381), .Y(n4062) );
INVX2TS U4281 ( .A(operation[2]), .Y(n6355) );
AOI31X1TS U4282 ( .A0(n6433), .A1(n6597), .A2(n6713), .B0(n5039), .Y(n5111)
);
NOR2X1TS U4283 ( .A(n6137), .B(n6105), .Y(n6135) );
MX2X1TS U4284 ( .A(FPADDSUB_DMP[24]), .B(FPADDSUB_exp_oper_result[1]), .S0(
n2983), .Y(n2870) );
CLKAND2X2TS U4285 ( .A(n5247), .B(FPADDSUB_DmP[30]), .Y(n2841) );
XNOR2X2TS U4286 ( .A(n4712), .B(n4711), .Y(n4748) );
NAND2X2TS U4287 ( .A(n4701), .B(n4700), .Y(n4945) );
AOI2BB1XLTS U4288 ( .A0N(n6509), .A1N(FPADDSUB_Add_Subt_result[23]), .B0(
FPADDSUB_Add_Subt_result[24]), .Y(n6510) );
INVX2TS U4289 ( .A(n5941), .Y(n5942) );
NAND3XLTS U4290 ( .A(n6774), .B(n6688), .C(FPADDSUB_Add_Subt_result[15]),
.Y(n5943) );
NAND2BXLTS U4291 ( .AN(n5616), .B(n5422), .Y(n6408) );
NOR2XLTS U4292 ( .A(n2554), .B(FPMULT_Op_MY[8]), .Y(n6372) );
NAND2X1TS U4293 ( .A(n2123), .B(n2555), .Y(n2554) );
NOR2XLTS U4294 ( .A(FPMULT_Op_MY[4]), .B(n2563), .Y(n2555) );
MX2X1TS U4295 ( .A(FPMULT_Op_MX[25]), .B(FPMULT_exp_oper_result[2]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[2]) );
CLKXOR2X2TS U4296 ( .A(n4390), .B(n4389), .Y(n4765) );
NAND2X1TS U4297 ( .A(n2531), .B(n4388), .Y(n4389) );
NAND2X1TS U4298 ( .A(n4392), .B(n4391), .Y(n4393) );
INVX2TS U4299 ( .A(n4363), .Y(n4775) );
AOI21X1TS U4300 ( .A0(n4409), .A1(n4357), .B0(n4356), .Y(n4362) );
CLKXOR2X2TS U4301 ( .A(n4343), .B(n4342), .Y(n4785) );
INVX2TS U4302 ( .A(n4789), .Y(n4790) );
OR2X1TS U4303 ( .A(n4759), .B(n4758), .Y(n4761) );
INVX2TS U4304 ( .A(n2797), .Y(n2472) );
INVX2TS U4305 ( .A(n2507), .Y(n2470) );
INVX2TS U4306 ( .A(n2797), .Y(n2507) );
INVX2TS U4307 ( .A(n4414), .Y(n4802) );
BUFX8TS U4308 ( .A(n2460), .Y(n2446) );
INVX2TS U4309 ( .A(FPSENCOS_d_ff2_X[9]), .Y(n6481) );
INVX2TS U4310 ( .A(FPSENCOS_d_ff_Yn[9]), .Y(n6567) );
INVX2TS U4311 ( .A(FPSENCOS_d_ff2_X[12]), .Y(n6478) );
INVX2TS U4312 ( .A(FPSENCOS_d_ff_Yn[12]), .Y(n6570) );
INVX2TS U4313 ( .A(FPSENCOS_d_ff_Yn[11]), .Y(n6569) );
INVX2TS U4314 ( .A(FPSENCOS_d_ff2_X[7]), .Y(n6483) );
INVX2TS U4315 ( .A(FPSENCOS_d_ff_Yn[7]), .Y(n6565) );
INVX2TS U4316 ( .A(FPSENCOS_d_ff2_X[14]), .Y(n6476) );
INVX2TS U4317 ( .A(FPSENCOS_d_ff_Yn[14]), .Y(n6572) );
INVX2TS U4318 ( .A(FPSENCOS_d_ff2_X[10]), .Y(n6480) );
INVX2TS U4319 ( .A(FPSENCOS_d_ff_Yn[10]), .Y(n6568) );
INVX2TS U4320 ( .A(FPSENCOS_d_ff2_X[16]), .Y(n6474) );
INVX2TS U4321 ( .A(FPSENCOS_d_ff_Yn[16]), .Y(n6575) );
INVX2TS U4322 ( .A(FPSENCOS_d_ff2_X[4]), .Y(n6487) );
INVX2TS U4323 ( .A(FPSENCOS_d_ff_Yn[4]), .Y(n6559) );
INVX2TS U4324 ( .A(FPSENCOS_d_ff2_X[17]), .Y(n6473) );
INVX2TS U4325 ( .A(FPSENCOS_d_ff_Yn[17]), .Y(n6576) );
INVX2TS U4326 ( .A(FPSENCOS_d_ff2_X[5]), .Y(n6486) );
INVX2TS U4327 ( .A(FPSENCOS_d_ff_Yn[5]), .Y(n6560) );
INVX2TS U4328 ( .A(FPSENCOS_d_ff_Yn[13]), .Y(n6571) );
INVX2TS U4329 ( .A(FPSENCOS_d_ff2_X[20]), .Y(n6467) );
INVX2TS U4330 ( .A(FPSENCOS_d_ff_Yn[20]), .Y(n6580) );
INVX2TS U4331 ( .A(FPSENCOS_d_ff2_X[1]), .Y(n6493) );
INVX2TS U4332 ( .A(FPSENCOS_d_ff2_X[8]), .Y(n6482) );
INVX2TS U4333 ( .A(FPSENCOS_d_ff_Yn[8]), .Y(n6566) );
INVX2TS U4334 ( .A(FPSENCOS_d_ff_Yn[15]), .Y(n6573) );
INVX2TS U4335 ( .A(FPSENCOS_d_ff2_X[18]), .Y(n6470) );
INVX2TS U4336 ( .A(FPSENCOS_d_ff2_X[21]), .Y(n6466) );
INVX2TS U4337 ( .A(FPSENCOS_d_ff_Yn[21]), .Y(n6582) );
INVX2TS U4338 ( .A(FPSENCOS_d_ff_Yn[2]), .Y(n6556) );
BUFX3TS U4339 ( .A(n2279), .Y(n6471) );
INVX2TS U4340 ( .A(FPSENCOS_d_ff2_X[19]), .Y(n6468) );
BUFX3TS U4341 ( .A(n5458), .Y(n5452) );
INVX2TS U4342 ( .A(FPSENCOS_d_ff2_X[3]), .Y(n6488) );
INVX2TS U4343 ( .A(FPSENCOS_d_ff_Yn[3]), .Y(n6557) );
INVX2TS U4344 ( .A(FPSENCOS_d_ff2_X[6]), .Y(n6484) );
INVX2TS U4345 ( .A(FPSENCOS_d_ff_Yn[6]), .Y(n6561) );
BUFX3TS U4346 ( .A(n5458), .Y(n5456) );
INVX2TS U4347 ( .A(FPSENCOS_d_ff_Yn[22]), .Y(n6583) );
INVX2TS U4348 ( .A(FPSENCOS_d_ff_Yn[0]), .Y(n6554) );
INVX2TS U4349 ( .A(FPSENCOS_d_ff_Yn[24]), .Y(n6587) );
INVX2TS U4350 ( .A(FPSENCOS_d_ff_Yn[25]), .Y(n6589) );
INVX2TS U4351 ( .A(FPSENCOS_d_ff_Yn[26]), .Y(n6590) );
INVX2TS U4352 ( .A(FPSENCOS_d_ff_Yn[28]), .Y(n6591) );
INVX2TS U4353 ( .A(FPSENCOS_d_ff_Yn[29]), .Y(n6594) );
BUFX3TS U4354 ( .A(n5458), .Y(n5871) );
BUFX3TS U4355 ( .A(n6471), .Y(n5468) );
INVX2TS U4356 ( .A(FPSENCOS_d_ff_Yn[31]), .Y(n6615) );
INVX2TS U4357 ( .A(FPSENCOS_d_ff2_X[0]), .Y(n6495) );
INVX2TS U4358 ( .A(FPSENCOS_d_ff2_X[30]), .Y(n6454) );
NOR2XLTS U4359 ( .A(FPSENCOS_cont_iter_out[3]), .B(n6713), .Y(n6437) );
BUFX3TS U4360 ( .A(FPMULT_Op_MY[14]), .Y(n6358) );
BUFX3TS U4361 ( .A(FPMULT_Op_MY[18]), .Y(n6357) );
MX2X1TS U4362 ( .A(Data_2[13]), .B(FPMULT_Op_MY[13]), .S0(n6097), .Y(n2005)
);
MX2X1TS U4363 ( .A(Data_2[2]), .B(FPMULT_Op_MY[2]), .S0(n6207), .Y(n1994) );
MX2X1TS U4364 ( .A(n6242), .B(FPMULT_P_Sgf[7]), .S0(n6306), .Y(n1925) );
CLKAND2X2TS U4365 ( .A(n6276), .B(n6281), .Y(n6277) );
OR2X1TS U4366 ( .A(n6275), .B(n6274), .Y(n6276) );
MX2X1TS U4367 ( .A(n6238), .B(FPMULT_P_Sgf[6]), .S0(n6306), .Y(n1924) );
MX2X1TS U4368 ( .A(n6254), .B(FPMULT_P_Sgf[9]), .S0(n6306), .Y(n1927) );
MX2X1TS U4369 ( .A(FPSENCOS_d_ff2_Z[31]), .B(FPSENCOS_d_ff3_sign_out), .S0(
n6464), .Y(n1477) );
NAND2X1TS U4370 ( .A(n6293), .B(n6292), .Y(n6294) );
NAND2X1TS U4371 ( .A(n4868), .B(n4867), .Y(n4869) );
MX2X1TS U4372 ( .A(n6219), .B(FPMULT_P_Sgf[3]), .S0(n6911), .Y(n1921) );
MX2X1TS U4373 ( .A(n6225), .B(FPMULT_P_Sgf[4]), .S0(n6911), .Y(n1922) );
NAND2X1TS U4374 ( .A(n6310), .B(n6309), .Y(n6311) );
MX2X1TS U4375 ( .A(n6214), .B(FPMULT_P_Sgf[2]), .S0(n6911), .Y(n1920) );
MX2X1TS U4376 ( .A(Data_2[24]), .B(FPMULT_Op_MY[24]), .S0(n2227), .Y(n2016)
);
MX2X1TS U4377 ( .A(n4904), .B(FPMULT_P_Sgf[25]), .S0(n6911), .Y(n1943) );
XNOR2X1TS U4378 ( .A(n4938), .B(n4903), .Y(n4904) );
NAND2X1TS U4379 ( .A(n4937), .B(n4935), .Y(n4903) );
MX2X1TS U4380 ( .A(n6180), .B(FPMULT_Add_result[1]), .S0(n6122), .Y(n1988)
);
MX2X1TS U4381 ( .A(n6169), .B(FPMULT_Add_result[3]), .S0(n6122), .Y(n1986)
);
INVX2TS U4382 ( .A(n6173), .Y(n6167) );
MX2X1TS U4383 ( .A(n6134), .B(FPMULT_Add_result[12]), .S0(n6199), .Y(n1977)
);
MX2X1TS U4384 ( .A(n6130), .B(FPMULT_Add_result[14]), .S0(n6122), .Y(n1975)
);
MX2X1TS U4385 ( .A(FPADDSUB_Add_Subt_result[0]), .B(n5887), .S0(n5969), .Y(
n1663) );
OAI31X1TS U4386 ( .A0(n2240), .A1(n5483), .A2(n6431), .B0(n5112), .Y(n1804)
);
MX2X1TS U4387 ( .A(n6229), .B(FPMULT_P_Sgf[5]), .S0(n6306), .Y(n1923) );
MX2X1TS U4388 ( .A(Data_2[23]), .B(FPMULT_Op_MY[23]), .S0(n6100), .Y(n2015)
);
MX2X1TS U4389 ( .A(FPMULT_exp_oper_result[2]), .B(
FPMULT_Exp_module_Data_S[2]), .S0(n6999), .Y(n1912) );
MX2X1TS U4390 ( .A(n6136), .B(FPMULT_Add_result[11]), .S0(n6199), .Y(n1978)
);
MX2X1TS U4391 ( .A(n6140), .B(FPMULT_Add_result[10]), .S0(n6122), .Y(n1979)
);
MX2X1TS U4392 ( .A(n6142), .B(FPMULT_Add_result[9]), .S0(n6199), .Y(n1980)
);
MX2X1TS U4393 ( .A(n6144), .B(FPMULT_Add_result[8]), .S0(n6199), .Y(n1981)
);
MX2X1TS U4394 ( .A(n6148), .B(FPMULT_Add_result[7]), .S0(n6179), .Y(n1982)
);
MX2X1TS U4395 ( .A(n6153), .B(FPMULT_Add_result[6]), .S0(n6179), .Y(n1983)
);
MX2X1TS U4396 ( .A(n6158), .B(FPMULT_Add_result[5]), .S0(n6179), .Y(n1984)
);
MX2X1TS U4397 ( .A(n6163), .B(FPMULT_Add_result[4]), .S0(n6179), .Y(n1985)
);
MX2X1TS U4398 ( .A(n6174), .B(FPMULT_Add_result[2]), .S0(n6179), .Y(n1987)
);
MX2X1TS U4399 ( .A(Data_1[29]), .B(FPMULT_Op_MX[29]), .S0(n2322), .Y(n2053)
);
MX2X1TS U4400 ( .A(n5950), .B(FPADDSUB_exp_oper_result[2]), .S0(n2213), .Y(
n1693) );
NAND3XLTS U4401 ( .A(n5071), .B(FPSENCOS_sel_mux_1_reg), .C(n6983), .Y(n5070) );
NAND3XLTS U4402 ( .A(FPSENCOS_cordic_FSM_state_reg[0]), .B(n5788), .C(n6667),
.Y(n5071) );
MX2X1TS U4403 ( .A(n5932), .B(FPADDSUB_exp_oper_result[1]), .S0(n2213), .Y(
n1692) );
MX2X1TS U4404 ( .A(n5933), .B(FPADDSUB_exp_oper_result[0]), .S0(n2213), .Y(
n1691) );
NAND3XLTS U4405 ( .A(FPSENCOS_cordic_FSM_state_reg[0]), .B(n6720), .C(n6670),
.Y(n5064) );
MX2X1TS U4406 ( .A(n6865), .B(n6864), .S0(n2116), .Y(n1949) );
MX2X1TS U4407 ( .A(n6880), .B(n6879), .S0(n2115), .Y(n1957) );
NAND2X1TS U4408 ( .A(n2162), .B(n4820), .Y(n4821) );
OR2X1TS U4409 ( .A(n4749), .B(n4748), .Y(n2162) );
NAND2X1TS U4410 ( .A(n4769), .B(n4814), .Y(n4770) );
CLKMX2X2TS U4411 ( .A(n4961), .B(FPMULT_P_Sgf[30]), .S0(n4922), .Y(n1948) );
NAND2X1TS U4412 ( .A(n4946), .B(n4945), .Y(n4947) );
CLKMX2X2TS U4413 ( .A(n4934), .B(FPMULT_P_Sgf[24]), .S0(n6911), .Y(n1942) );
XNOR2X1TS U4414 ( .A(n4933), .B(n4932), .Y(n4934) );
NAND2X1TS U4415 ( .A(n4931), .B(n4930), .Y(n4932) );
NAND2X1TS U4416 ( .A(n4877), .B(n4876), .Y(n4878) );
NAND2X1TS U4417 ( .A(n4884), .B(n4883), .Y(n4885) );
CLKMX2X2TS U4418 ( .A(n4927), .B(FPMULT_P_Sgf[27]), .S0(n4922), .Y(n1945) );
XOR2X1TS U4419 ( .A(n4952), .B(n4926), .Y(n4927) );
AOI211XLTS U4420 ( .A0(FPADDSUB_FS_Module_state_reg[1]), .A1(n5423), .B0(
n5413), .C0(n5412), .Y(n5414) );
OAI21XLTS U4421 ( .A0(n5418), .A1(n5416), .B0(n5270), .Y(n1688) );
OAI32X1TS U4422 ( .A0(n5785), .A1(FPSENCOS_cordic_FSM_state_reg[2]), .A2(
n5784), .B0(n6660), .B1(n5785), .Y(n5790) );
CLKBUFX3TS U4423 ( .A(n7006), .Y(n5028) );
MX2X1TS U4424 ( .A(FPADDSUB_Add_Subt_result[2]), .B(n5960), .S0(n5969), .Y(
n1665) );
OAI211XLTS U4425 ( .A0(FPADDSUB_sign_final_result), .A1(n1845), .B0(n6534),
.C0(n6787), .Y(n5061) );
NAND4XLTS U4426 ( .A(FPMULT_Exp_module_Data_S[3]), .B(
FPMULT_Exp_module_Data_S[2]), .C(FPMULT_Exp_module_Data_S[1]), .D(
FPMULT_Exp_module_Data_S[0]), .Y(n4888) );
MX2X1TS U4427 ( .A(n6863), .B(n6862), .S0(n2116), .Y(n1951) );
CLKMX2X2TS U4428 ( .A(FPADDSUB_Add_Subt_result[23]), .B(n4858), .S0(n5969),
.Y(n1686) );
NAND2X1TS U4429 ( .A(n4842), .B(n4841), .Y(n4843) );
MX2X1TS U4430 ( .A(n6872), .B(n6871), .S0(n2115), .Y(n1955) );
MX2X1TS U4431 ( .A(n6874), .B(n6873), .S0(n2116), .Y(n1956) );
MX2X1TS U4432 ( .A(n6876), .B(n6875), .S0(n2116), .Y(n1950) );
MX2X1TS U4433 ( .A(n6878), .B(n6877), .S0(n2116), .Y(n1952) );
NAND2X1TS U4434 ( .A(n4778), .B(n4777), .Y(n4779) );
MX2X1TS U4435 ( .A(n6882), .B(n6881), .S0(n2115), .Y(n1959) );
MX2X1TS U4436 ( .A(n6884), .B(n6883), .S0(n2115), .Y(n1961) );
MX2X1TS U4437 ( .A(n6886), .B(n6885), .S0(n2116), .Y(n1960) );
MX2X1TS U4438 ( .A(n6888), .B(n6887), .S0(n2116), .Y(n1962) );
MX2X1TS U4439 ( .A(n6890), .B(n6889), .S0(n2115), .Y(n1963) );
MX2X1TS U4440 ( .A(n6892), .B(n6891), .S0(n2116), .Y(n1958) );
NAND2X1TS U4441 ( .A(n2610), .B(n4836), .Y(n4805) );
MX2X1TS U4442 ( .A(n6900), .B(n6899), .S0(n2115), .Y(n1954) );
NAND2X1TS U4443 ( .A(n4833), .B(n2739), .Y(n2595) );
MX2X1TS U4444 ( .A(n6902), .B(n6901), .S0(n2115), .Y(n1953) );
MX2X1TS U4445 ( .A(n2348), .B(n5952), .S0(n5969), .Y(n1664) );
AOI31XLTS U4446 ( .A0(FPSENCOS_cont_iter_out[0]), .A1(
FPSENCOS_cont_iter_out[3]), .A2(n2800), .B0(n5041), .Y(n5040) );
OAI21XLTS U4447 ( .A0(n5483), .A1(n6711), .B0(FPSENCOS_cont_iter_out[0]),
.Y(n5044) );
MX2X1TS U4448 ( .A(n6255), .B(FPMULT_P_Sgf[0]), .S0(n6911), .Y(n1918) );
MX2X1TS U4449 ( .A(n6259), .B(FPMULT_P_Sgf[1]), .S0(n6306), .Y(n1919) );
CLKAND2X2TS U4450 ( .A(n6258), .B(n6257), .Y(n6259) );
NAND2X1TS U4451 ( .A(n6188), .B(n6187), .Y(n6189) );
MX2X1TS U4452 ( .A(Data_2[0]), .B(FPMULT_Op_MY[0]), .S0(n6097), .Y(n1992) );
NAND2X1TS U4453 ( .A(n2558), .B(n2557), .Y(n1997) );
NAND2X1TS U4454 ( .A(n2132), .B(FPMULT_Op_MY[5]), .Y(n2557) );
INVX2TS U4455 ( .A(n2559), .Y(n2558) );
NOR2BX1TS U4456 ( .AN(Data_2[5]), .B(n2132), .Y(n2559) );
MX2X1TS U4457 ( .A(Data_2[6]), .B(FPMULT_Op_MY[6]), .S0(n2132), .Y(n1998) );
MX2X1TS U4458 ( .A(Data_2[7]), .B(n6365), .S0(n2227), .Y(n1999) );
MX2X1TS U4459 ( .A(Data_2[8]), .B(FPMULT_Op_MY[8]), .S0(n2132), .Y(n2000) );
MX2X1TS U4460 ( .A(Data_2[9]), .B(n2284), .S0(n2227), .Y(n2001) );
MX2X1TS U4461 ( .A(Data_2[10]), .B(FPMULT_Op_MY[10]), .S0(n2132), .Y(n2002)
);
MX2X1TS U4462 ( .A(Data_2[11]), .B(n2276), .S0(n2132), .Y(n2003) );
MX2X1TS U4463 ( .A(Data_2[18]), .B(n6357), .S0(n6207), .Y(n2010) );
MX2X1TS U4464 ( .A(Data_2[20]), .B(FPMULT_Op_MY[20]), .S0(n2322), .Y(n2012)
);
MX2X1TS U4465 ( .A(Data_2[21]), .B(n6359), .S0(n6206), .Y(n2013) );
MX2X1TS U4466 ( .A(Data_2[22]), .B(n2730), .S0(n6206), .Y(n2014) );
MX2X1TS U4467 ( .A(Data_1[0]), .B(n2210), .S0(n6100), .Y(n2024) );
MX2X1TS U4468 ( .A(Data_1[1]), .B(n6381), .S0(n6100), .Y(n2025) );
MX2X1TS U4469 ( .A(Data_1[3]), .B(n6382), .S0(n6097), .Y(n2027) );
NOR2BX1TS U4470 ( .AN(Data_1[5]), .B(n2322), .Y(n2578) );
MX2X1TS U4471 ( .A(Data_1[12]), .B(n2338), .S0(n2227), .Y(n2036) );
MX2X1TS U4472 ( .A(Data_1[13]), .B(n6379), .S0(n2227), .Y(n2037) );
MX2X1TS U4473 ( .A(Data_1[14]), .B(n2221), .S0(n2227), .Y(n2038) );
MX2X1TS U4474 ( .A(Data_1[15]), .B(n6099), .S0(n2227), .Y(n2039) );
MX2X1TS U4475 ( .A(Data_1[16]), .B(FPMULT_Op_MX[16]), .S0(n6100), .Y(n2040)
);
MX2X1TS U4476 ( .A(Data_1[17]), .B(n6373), .S0(n2227), .Y(n2041) );
MX2X1TS U4477 ( .A(Data_1[18]), .B(FPMULT_Op_MX[18]), .S0(n6100), .Y(n2042)
);
MX2X1TS U4478 ( .A(Data_1[19]), .B(n6374), .S0(n2132), .Y(n2043) );
MX2X1TS U4479 ( .A(Data_1[20]), .B(FPMULT_Op_MX[20]), .S0(n6100), .Y(n2044)
);
MX2X1TS U4480 ( .A(Data_1[21]), .B(FPMULT_Op_MX[21]), .S0(n6100), .Y(n2045)
);
AOI21X1TS U4481 ( .A0(n4454), .A1(n4455), .B0(n2685), .Y(n2158) );
INVX6TS U4482 ( .A(n4924), .Y(n4699) );
CLKINVX6TS U4483 ( .A(n4835), .Y(n4837) );
INVX2TS U4484 ( .A(n2234), .Y(n2717) );
OAI22X1TS U4485 ( .A0(n2482), .A1(n2234), .B0(n2166), .B1(n2469), .Y(n3644)
);
OAI22X1TS U4486 ( .A0(n3825), .A1(n2234), .B0(n2166), .B1(n2477), .Y(n3822)
);
OAI22X1TS U4487 ( .A0(n2482), .A1(n2166), .B0(n2234), .B1(n2477), .Y(n3738)
);
ADDFHX4TS U4488 ( .A(n3880), .B(n3879), .CI(n3878), .CO(n3819), .S(n4176) );
INVX2TS U4489 ( .A(n4142), .Y(n2562) );
ADDFHX2TS U4490 ( .A(n3965), .B(n3964), .CI(n3963), .CO(n3985), .S(n3972) );
INVX6TS U4491 ( .A(n2324), .Y(n2397) );
NOR2X4TS U4492 ( .A(n2446), .B(n4801), .Y(n2571) );
NOR2X4TS U4493 ( .A(n2446), .B(n4794), .Y(n2644) );
NOR2X4TS U4494 ( .A(n2446), .B(n4786), .Y(n2447) );
NAND2X6TS U4495 ( .A(n2544), .B(n2521), .Y(n2543) );
XNOR2X1TS U4496 ( .A(n2563), .B(FPMULT_Op_MX[11]), .Y(n3316) );
OR2X6TS U4497 ( .A(n2170), .B(n4671), .Y(n4937) );
NAND2X6TS U4498 ( .A(n2170), .B(n4671), .Y(n4935) );
OAI22X2TS U4499 ( .A0(n3610), .A1(n3315), .B0(n2230), .B1(n3344), .Y(n3346)
);
AOI21X4TS U4500 ( .A0(n6272), .A1(n4473), .B0(n4472), .Y(n4478) );
NAND2X4TS U4501 ( .A(n2375), .B(n4747), .Y(n4814) );
NOR2X4TS U4502 ( .A(n4442), .B(n2434), .Y(n4483) );
NAND2X6TS U4503 ( .A(n2612), .B(n2610), .Y(n2459) );
OR2X6TS U4504 ( .A(n2706), .B(n2705), .Y(n4841) );
INVX8TS U4505 ( .A(n2246), .Y(n2247) );
INVX6TS U4506 ( .A(n2467), .Y(n2409) );
AND2X8TS U4507 ( .A(n4832), .B(n2739), .Y(n2172) );
NAND3X4TS U4508 ( .A(n2473), .B(n2450), .C(n2130), .Y(n2418) );
NOR2X6TS U4509 ( .A(n4212), .B(n4211), .Y(n4304) );
ADDFHX4TS U4510 ( .A(n3655), .B(n3654), .CI(n3653), .CO(n3667), .S(n3686) );
ADDFHX4TS U4511 ( .A(n3283), .B(n3282), .CI(n3281), .CO(n3248), .S(n3665) );
ADDFHX4TS U4512 ( .A(n3840), .B(n3839), .CI(n3838), .CO(n3816), .S(n4146) );
BUFX20TS U4513 ( .A(n2437), .Y(n2324) );
ADDFHX4TS U4514 ( .A(n3939), .B(n3938), .CI(n3937), .CO(n4258), .S(n4256) );
ADDFHX4TS U4515 ( .A(n4163), .B(n4162), .CI(n4161), .CO(n4192), .S(n4164) );
OAI21X2TS U4516 ( .A0(n3123), .A1(n2586), .B0(n3122), .Y(n2602) );
ADDFHX2TS U4517 ( .A(n4036), .B(n4035), .CI(n4034), .CO(n4041), .S(n4099) );
NAND2X4TS U4518 ( .A(n4564), .B(n4563), .Y(n6309) );
OR2X4TS U4519 ( .A(n4432), .B(n4431), .Y(n6247) );
INVX16TS U4520 ( .A(n2445), .Y(n4807) );
INVX12TS U4521 ( .A(n6909), .Y(n3919) );
OAI22X2TS U4522 ( .A0(n2251), .A1(n4033), .B0(n4060), .B1(n4032), .Y(n4100)
);
INVX8TS U4523 ( .A(n2229), .Y(n2230) );
INVX2TS U4524 ( .A(n2164), .Y(n2210) );
INVX2TS U4525 ( .A(n2262), .Y(n2513) );
INVX4TS U4526 ( .A(n2186), .Y(n2221) );
OAI22X2TS U4527 ( .A0(n3495), .A1(n2220), .B0(n3541), .B1(n2331), .Y(n3544)
);
CLKXOR2X2TS U4528 ( .A(FPMULT_Op_MY[0]), .B(n6367), .Y(n3231) );
INVX2TS U4529 ( .A(n6098), .Y(n2341) );
NAND2X8TS U4530 ( .A(n2680), .B(n3113), .Y(n2165) );
INVX2TS U4531 ( .A(n4289), .Y(n2763) );
NAND2X4TS U4532 ( .A(n4288), .B(n2176), .Y(n4289) );
INVX12TS U4533 ( .A(n3609), .Y(n2229) );
INVX6TS U4534 ( .A(n2229), .Y(n2231) );
INVX2TS U4535 ( .A(n2828), .Y(n2730) );
NAND2X1TS U4536 ( .A(n4324), .B(n4322), .Y(n4391) );
INVX2TS U4537 ( .A(n4391), .Y(n2532) );
INVX6TS U4538 ( .A(n2803), .Y(n2452) );
OAI2BB1X2TS U4539 ( .A0N(n2221), .A1N(n2818), .B0(n2371), .Y(n3149) );
OR2X1TS U4540 ( .A(n2556), .B(n2340), .Y(n2169) );
INVX2TS U4541 ( .A(n3255), .Y(n3426) );
XNOR2X4TS U4542 ( .A(n4666), .B(n2430), .Y(n2170) );
OR2X1TS U4543 ( .A(n2337), .B(n2747), .Y(n2171) );
INVX4TS U4544 ( .A(n5858), .Y(n2338) );
INVX2TS U4545 ( .A(n2252), .Y(n3850) );
XNOR2X4TS U4546 ( .A(n2792), .B(n2791), .Y(n2178) );
OR2X1TS U4547 ( .A(n2624), .B(n2688), .Y(n2179) );
NOR2X4TS U4548 ( .A(n4219), .B(n4220), .Y(n4692) );
XNOR2X4TS U4549 ( .A(n2129), .B(FPMULT_Op_MY[4]), .Y(n2180) );
INVX2TS U4550 ( .A(n3192), .Y(n2628) );
XNOR2X1TS U4551 ( .A(n2642), .B(n3186), .Y(n2181) );
AND2X2TS U4552 ( .A(n2628), .B(n3191), .Y(n2184) );
INVX2TS U4553 ( .A(n2222), .Y(n2224) );
INVX2TS U4554 ( .A(FPMULT_Op_MX[4]), .Y(n2601) );
INVX2TS U4555 ( .A(n4719), .Y(n2689) );
NAND2X2TS U4556 ( .A(n4718), .B(n4717), .Y(n4719) );
AND2X2TS U4557 ( .A(n2167), .B(n3230), .Y(n2189) );
INVX2TS U4558 ( .A(n2746), .Y(n3105) );
NAND2X1TS U4559 ( .A(n4248), .B(n4247), .Y(n2191) );
INVX2TS U4560 ( .A(n4334), .Y(n3563) );
NAND2X1TS U4561 ( .A(n2731), .B(n2173), .Y(n2192) );
NOR2X4TS U4562 ( .A(n5573), .B(n5511), .Y(n4909) );
INVX2TS U4563 ( .A(n3231), .Y(n4087) );
AND2X2TS U4564 ( .A(n3374), .B(n3293), .Y(n4387) );
INVX2TS U4565 ( .A(n4387), .Y(n2531) );
INVX2TS U4566 ( .A(n4753), .Y(n2705) );
CLKXOR2X2TS U4567 ( .A(n4303), .B(n4302), .Y(n4751) );
INVX2TS U4568 ( .A(n2829), .Y(n2704) );
INVX4TS U4569 ( .A(n3121), .Y(n2236) );
INVX2TS U4570 ( .A(n4764), .Y(n4809) );
NAND3X4TS U4571 ( .A(n6534), .B(n6356), .C(n6787), .Y(n6535) );
OR4X2TS U4572 ( .A(FPSENCOS_cordic_FSM_state_reg[3]), .B(n6670), .C(n6720),
.D(n6660), .Y(n2204) );
OR2X1TS U4573 ( .A(n2748), .B(FPMULT_Op_MY[16]), .Y(n2205) );
INVX2TS U4574 ( .A(rst), .Y(n7006) );
CLKBUFX3TS U4575 ( .A(n2217), .Y(n6943) );
CLKBUFX2TS U4576 ( .A(n6914), .Y(n6912) );
CLKBUFX3TS U4577 ( .A(n5028), .Y(n6930) );
INVX12TS U4578 ( .A(n2754), .Y(n3831) );
ADDFHX2TS U4579 ( .A(n3776), .B(n3775), .CI(n3774), .CO(n3887), .S(n3884) );
OAI22X2TS U4580 ( .A0(n3610), .A1(n3403), .B0(n2231), .B1(n3476), .Y(n3479)
);
ADDFHX4TS U4581 ( .A(n4139), .B(n4138), .CI(n4137), .CO(n4131), .S(n4162) );
OAI22X2TS U4582 ( .A0(n2997), .A1(n3207), .B0(n3734), .B1(n2998), .Y(n3205)
);
XNOR2X2TS U4583 ( .A(n2285), .B(n6099), .Y(n3795) );
OAI22X2TS U4584 ( .A0(n3450), .A1(n2165), .B0(n2335), .B1(n3850), .Y(n3517)
);
NOR2X4TS U4585 ( .A(n4744), .B(n4743), .Y(n4823) );
ADDFHX4TS U4586 ( .A(n4184), .B(n4183), .CI(n4182), .CO(n4189), .S(n4191) );
ADDFHX4TS U4587 ( .A(n4148), .B(n4147), .CI(n4146), .CO(n4187), .S(n4183) );
ADDFHX4TS U4588 ( .A(n4008), .B(n4007), .CI(n4006), .CO(n4140), .S(n4009) );
ADDFHX4TS U4589 ( .A(n4145), .B(n4144), .CI(n4143), .CO(n4180), .S(n4184) );
OAI22X2TS U4590 ( .A0(n3744), .A1(n3258), .B0(n3743), .B1(n3168), .Y(n3669)
);
INVX16TS U4591 ( .A(n2508), .Y(n2585) );
XNOR2X2TS U4592 ( .A(n3783), .B(n2256), .Y(n3467) );
INVX4TS U4593 ( .A(n4584), .Y(n4602) );
INVX12TS U4594 ( .A(n2449), .Y(n2530) );
NAND3X4TS U4595 ( .A(n2740), .B(n2741), .C(n2548), .Y(n2515) );
XOR2X2TS U4596 ( .A(FPMULT_Op_MY[6]), .B(FPMULT_Op_MY[7]), .Y(n2517) );
XOR2X4TS U4597 ( .A(n4478), .B(n4477), .Y(n4494) );
ADDFHX2TS U4598 ( .A(n3153), .B(n3152), .CI(n3151), .CO(n3340), .S(n3146) );
NAND2X2TS U4599 ( .A(n2493), .B(n2492), .Y(n3153) );
OAI22X2TS U4600 ( .A0(n3643), .A1(n3201), .B0(n3695), .B1(n3005), .Y(n3204)
);
OAI22X2TS U4601 ( .A0(n3610), .A1(n3199), .B0(n3009), .B1(n2231), .Y(n3007)
);
OAI22X2TS U4602 ( .A0(n3610), .A1(n3200), .B0(n2231), .B1(n3199), .Y(n3277)
);
ADDFHX2TS U4603 ( .A(n3866), .B(n3865), .CI(n3864), .CO(n4016), .S(n3984) );
NOR2X4TS U4604 ( .A(n6374), .B(FPMULT_Op_MX[7]), .Y(n2503) );
NAND3X6TS U4605 ( .A(n4626), .B(n4194), .C(n4195), .Y(n2476) );
NAND2X4TS U4606 ( .A(n3061), .B(n3060), .Y(n3068) );
INVX12TS U4607 ( .A(n3659), .Y(n2330) );
XNOR2X2TS U4608 ( .A(n3518), .B(n2256), .Y(n3328) );
XNOR2X2TS U4609 ( .A(FPMULT_Op_MX[8]), .B(n2563), .Y(n3011) );
XOR2X4TS U4610 ( .A(n2207), .B(n4385), .Y(n2206) );
AO21X1TS U4611 ( .A0(n4409), .A1(n4381), .B0(n4380), .Y(n2207) );
OR2X4TS U4612 ( .A(n4321), .B(n4320), .Y(n2209) );
AOI21X2TS U4613 ( .A0(n4318), .A1(n4317), .B0(n4316), .Y(n4319) );
AOI21X1TS U4614 ( .A0(n4409), .A1(n4408), .B0(n4407), .Y(n4757) );
XNOR2X2TS U4615 ( .A(n4409), .B(n4393), .Y(n4764) );
AOI21X1TS U4616 ( .A0(n4409), .A1(n4392), .B0(n2532), .Y(n4390) );
OAI21X2TS U4617 ( .A0(n4250), .A1(n4669), .B0(n4662), .Y(n4690) );
NAND2X4TS U4618 ( .A(n2599), .B(n4937), .Y(n4676) );
NOR2BX4TS U4619 ( .AN(n5795), .B(FPADDSUB_Add_Subt_result[13]), .Y(n6517) );
NOR3X2TS U4620 ( .A(FPADDSUB_Add_Subt_result[7]), .B(
FPADDSUB_Add_Subt_result[6]), .C(n6513), .Y(n5800) );
INVX12TS U4621 ( .A(n2775), .Y(n2211) );
INVX2TS U4622 ( .A(n2881), .Y(n2212) );
INVX2TS U4623 ( .A(n6987), .Y(n2214) );
INVX2TS U4624 ( .A(n2214), .Y(n2215) );
INVX2TS U4625 ( .A(n2214), .Y(n2216) );
INVX2TS U4626 ( .A(rst), .Y(n2217) );
INVX2TS U4627 ( .A(rst), .Y(n2218) );
INVX2TS U4628 ( .A(n2141), .Y(n6100) );
AO21X1TS U4629 ( .A0(n2766), .A1(n2230), .B0(n3608), .Y(n3624) );
OAI22X1TS U4630 ( .A0(n3554), .A1(n3610), .B0(n3577), .B1(n2231), .Y(n3578)
);
BUFX4TS U4631 ( .A(n3610), .Y(n2766) );
BUFX3TS U4632 ( .A(n2287), .Y(n6928) );
BUFX3TS U4633 ( .A(n2217), .Y(n5030) );
OAI22X1TS U4634 ( .A0(n2466), .A1(n3792), .B0(n2448), .B1(n6374), .Y(n3395)
);
OAI22X1TS U4635 ( .A0(n2466), .A1(n6374), .B0(n2448), .B1(n3701), .Y(n3470)
);
INVX2TS U4636 ( .A(rst), .Y(n2225) );
INVX2TS U4637 ( .A(rst), .Y(n2226) );
INVX2TS U4638 ( .A(n2141), .Y(n2227) );
INVX2TS U4639 ( .A(FPSENCOS_cont_iter_out[0]), .Y(n2228) );
INVX2TS U4640 ( .A(n3121), .Y(n2237) );
INVX2TS U4641 ( .A(FPSENCOS_cont_iter_out[1]), .Y(n2238) );
BUFX20TS U4642 ( .A(n2128), .Y(n2241) );
INVX8TS U4643 ( .A(n2246), .Y(n2248) );
OAI22X2TS U4644 ( .A0(n4002), .A1(n2334), .B0(n3936), .B1(n2251), .Y(n3998)
);
AO21X2TS U4645 ( .A0(n2251), .A1(n4060), .B0(n4033), .Y(n3362) );
XNOR2X1TS U4646 ( .A(n3836), .B(n2256), .Y(n3428) );
XNOR2X1TS U4647 ( .A(n3229), .B(n2256), .Y(n3548) );
XNOR2X1TS U4648 ( .A(n4001), .B(n3723), .Y(n3228) );
XNOR2X2TS U4649 ( .A(n4037), .B(n3723), .Y(n3660) );
BUFX3TS U4650 ( .A(n2165), .Y(n2257) );
OAI22X2TS U4651 ( .A0(n2165), .A1(n3852), .B0(n3851), .B1(n3899), .Y(n3975)
);
OAI22X4TS U4652 ( .A0(n2165), .A1(n3850), .B0(n2335), .B1(n3849), .Y(n3976)
);
OAI22X2TS U4653 ( .A0(n3227), .A1(n3831), .B0(n3656), .B1(n2258), .Y(n3249)
);
OAI22X2TS U4654 ( .A0(n3228), .A1(n3831), .B0(n3227), .B1(n3725), .Y(n3239)
);
AO21X1TS U4655 ( .A0(n2211), .A1(n3695), .B0(n2814), .Y(n3583) );
INVX2TS U4656 ( .A(n2259), .Y(n2407) );
OR2X1TS U4657 ( .A(n3695), .B(n3201), .Y(n2401) );
OR2X2TS U4658 ( .A(n2259), .B(n2814), .Y(n2398) );
INVX2TS U4659 ( .A(n2265), .Y(n2266) );
INVX2TS U4660 ( .A(n2267), .Y(n2269) );
INVX4TS U4661 ( .A(n6909), .Y(n2492) );
BUFX3TS U4662 ( .A(n3831), .Y(n2271) );
OAI22X1TS U4663 ( .A0(n3428), .A1(n3725), .B0(n2271), .B1(n3467), .Y(n3484)
);
INVX2TS U4664 ( .A(n2272), .Y(n2275) );
XNOR2X2TS U4665 ( .A(n2277), .B(FPMULT_Op_MX[6]), .Y(n2998) );
XNOR2X1TS U4666 ( .A(n6365), .B(FPMULT_Op_MX[10]), .Y(n3348) );
XNOR2X1TS U4667 ( .A(n2277), .B(n6381), .Y(n3731) );
XNOR2X1TS U4668 ( .A(n6365), .B(n6380), .Y(n3729) );
OAI21X1TS U4669 ( .A0(FPMULT_Op_MY[8]), .A1(FPMULT_Op_MY[20]), .B0(n2277),
.Y(n3061) );
NOR2X2TS U4670 ( .A(n6365), .B(n2748), .Y(n3069) );
INVX2TS U4671 ( .A(n2279), .Y(n2280) );
XNOR2X2TS U4672 ( .A(n2281), .B(FPMULT_Op_MX[8]), .Y(n3273) );
XNOR2X1TS U4673 ( .A(n2281), .B(FPMULT_Op_MX[4]), .Y(n3863) );
XOR2X1TS U4674 ( .A(n2129), .B(n2813), .Y(n3647) );
XNOR2X1TS U4675 ( .A(n2129), .B(n6381), .Y(n3916) );
XOR2X1TS U4676 ( .A(n2129), .B(n2820), .Y(n3826) );
NOR2X1TS U4677 ( .A(n2129), .B(n3919), .Y(n3184) );
OAI21X2TS U4678 ( .A0(FPMULT_Op_MY[4]), .A1(FPMULT_Op_MY[16]), .B0(n2129),
.Y(n3100) );
INVX4TS U4679 ( .A(n6366), .Y(n2283) );
XOR2X1TS U4680 ( .A(n2283), .B(n2820), .Y(n3016) );
XNOR2X2TS U4681 ( .A(n2284), .B(n6381), .Y(n3640) );
XNOR2X2TS U4682 ( .A(n2284), .B(FPMULT_Op_MX[8]), .Y(n2526) );
XNOR2X2TS U4683 ( .A(n2283), .B(n6380), .Y(n3272) );
OAI21X2TS U4684 ( .A0(FPMULT_Op_MY[10]), .A1(FPMULT_Op_MY[22]), .B0(n2282),
.Y(n3057) );
XNOR2X1TS U4685 ( .A(n6360), .B(FPMULT_Op_MX[19]), .Y(n3164) );
XNOR2X1TS U4686 ( .A(n6360), .B(n6379), .Y(n3952) );
XNOR2X1TS U4687 ( .A(n6360), .B(n3900), .Y(n3704) );
NOR2X2TS U4688 ( .A(FPMULT_Op_MY[5]), .B(n6360), .Y(n3098) );
XNOR2X2TS U4689 ( .A(n2452), .B(n6379), .Y(n3671) );
XNOR2X2TS U4690 ( .A(n6359), .B(n6099), .Y(n3165) );
XNOR2X2TS U4691 ( .A(n3701), .B(n2452), .Y(n2624) );
INVX2TS U4692 ( .A(rst), .Y(n2286) );
INVX2TS U4693 ( .A(rst), .Y(n2287) );
INVX2TS U4694 ( .A(rst), .Y(n2288) );
INVX2TS U4695 ( .A(n5500), .Y(n2291) );
INVX2TS U4696 ( .A(n2291), .Y(n2292) );
INVX2TS U4697 ( .A(n2291), .Y(n2293) );
INVX2TS U4698 ( .A(n5503), .Y(n2294) );
INVX2TS U4699 ( .A(n5503), .Y(n2295) );
INVX2TS U4700 ( .A(n5503), .Y(n2296) );
INVX2TS U4701 ( .A(n2199), .Y(n2297) );
INVX2TS U4702 ( .A(n2199), .Y(n2298) );
INVX2TS U4703 ( .A(n2199), .Y(n2299) );
INVX2TS U4704 ( .A(n5257), .Y(n2300) );
INVX2TS U4705 ( .A(n5257), .Y(n2301) );
INVX2TS U4706 ( .A(n5257), .Y(n2302) );
INVX2TS U4707 ( .A(n6535), .Y(n2303) );
INVX2TS U4708 ( .A(n2303), .Y(n2304) );
INVX2TS U4709 ( .A(n2202), .Y(n2306) );
INVX2TS U4710 ( .A(n2202), .Y(n2307) );
INVX2TS U4711 ( .A(n2202), .Y(n2308) );
INVX2TS U4712 ( .A(n5810), .Y(n2309) );
INVX2TS U4713 ( .A(n5810), .Y(n2310) );
INVX2TS U4714 ( .A(n5810), .Y(n2311) );
NOR4X1TS U4715 ( .A(FPMULT_P_Sgf[6]), .B(FPMULT_P_Sgf[7]), .C(
FPMULT_P_Sgf[8]), .D(FPMULT_P_Sgf[9]), .Y(n5076) );
NOR4X1TS U4716 ( .A(FPMULT_P_Sgf[13]), .B(FPMULT_P_Sgf[12]), .C(
FPMULT_P_Sgf[11]), .D(FPMULT_P_Sgf[10]), .Y(n5077) );
OAI32X1TS U4717 ( .A0(FPSENCOS_cordic_FSM_state_reg[2]), .A1(n5783), .A2(
n6660), .B0(n5782), .B1(n6670), .Y(n2063) );
CLKBUFX3TS U4718 ( .A(n5052), .Y(n5027) );
AOI222X4TS U4719 ( .A0(n6595), .A1(FPSENCOS_d_ff2_Z[1]), .B0(n5458), .B1(
FPSENCOS_d_ff1_Z[1]), .C0(FPSENCOS_d_ff_Zn[1]), .C1(n5455), .Y(n5429)
);
NOR4X2TS U4720 ( .A(FPMULT_FS_Module_state_reg[1]), .B(
FPMULT_FS_Module_state_reg[0]), .C(n6730), .D(n6659), .Y(n5241) );
OAI22X1TS U4721 ( .A0(n3344), .A1(n3610), .B0(n2231), .B1(n3403), .Y(n3400)
);
OAI211X4TS U4722 ( .A0(FPSENCOS_cordic_FSM_state_reg[1]), .A1(n5790), .B0(
n5789), .C0(n6415), .Y(n2062) );
AOI2BB2X1TS U4723 ( .B0(n5629), .B1(n5678), .A0N(n5628), .A1N(n5627), .Y(
n5684) );
AOI221X1TS U4724 ( .A0(n2352), .A1(n6685), .B0(FPADDSUB_intDX[29]), .B1(
n6760), .C0(n5626), .Y(n5628) );
INVX2TS U4725 ( .A(n2204), .Y(n2313) );
AOI31X4TS U4726 ( .A0(n2240), .A1(n5483), .A2(n6711), .B0(n6430), .Y(n6446)
);
INVX2TS U4727 ( .A(n5585), .Y(n2314) );
OAI21X1TS U4728 ( .A0(n3399), .A1(n3695), .B0(n2404), .Y(n3407) );
NOR2X2TS U4729 ( .A(n6351), .B(n6349), .Y(n5604) );
NOR2X2TS U4730 ( .A(FPSENCOS_cordic_FSM_state_reg[0]), .B(n6667), .Y(n5066)
);
INVX2TS U4731 ( .A(n2197), .Y(n2316) );
INVX2TS U4732 ( .A(n2197), .Y(n2317) );
BUFX3TS U4733 ( .A(n6942), .Y(n6913) );
BUFX3TS U4734 ( .A(n5030), .Y(n6914) );
NAND3X2TS U4735 ( .A(n5483), .B(n6713), .C(n2240), .Y(n6434) );
INVX2TS U4736 ( .A(n6550), .Y(n6530) );
NOR2X4TS U4737 ( .A(n5537), .B(n5572), .Y(n5589) );
CLKBUFX3TS U4738 ( .A(n6943), .Y(n6942) );
BUFX3TS U4739 ( .A(n2288), .Y(n6931) );
NOR4X1TS U4740 ( .A(FPMULT_Op_MY[27]), .B(FPMULT_Op_MY[26]), .C(
FPMULT_Op_MY[25]), .D(FPMULT_Op_MY[24]), .Y(n6362) );
NAND2X1TS U4741 ( .A(n5005), .B(n5472), .Y(n2839) );
NOR2X4TS U4742 ( .A(FPADDSUB_FS_Module_state_reg[0]), .B(
FPADDSUB_FS_Module_state_reg[3]), .Y(n5005) );
INVX2TS U4743 ( .A(n2203), .Y(n2318) );
AOI22X2TS U4744 ( .A0(n5508), .A1(n5289), .B0(n5582), .B1(n5264), .Y(n5515)
);
AOI22X2TS U4745 ( .A0(n5888), .A1(n5278), .B0(n5290), .B1(n5607), .Y(n5526)
);
AOI22X2TS U4746 ( .A0(n5888), .A1(n5290), .B0(n5289), .B1(n5264), .Y(n5520)
);
INVX2TS U4747 ( .A(n2195), .Y(n2319) );
AOI22X2TS U4748 ( .A0(n5508), .A1(n5474), .B0(n5507), .B1(n5264), .Y(n5596)
);
AOI22X2TS U4749 ( .A0(n5888), .A1(n5283), .B0(n5292), .B1(n5607), .Y(n5524)
);
AOI22X2TS U4750 ( .A0(n5888), .A1(n5292), .B0(n5291), .B1(n5607), .Y(n5519)
);
INVX2TS U4751 ( .A(n2194), .Y(n2320) );
AOI22X2TS U4752 ( .A0(n5508), .A1(n5294), .B0(n5293), .B1(n5264), .Y(n5514)
);
INVX2TS U4753 ( .A(n2193), .Y(n2321) );
AOI22X2TS U4754 ( .A0(n5888), .A1(n5493), .B0(n5282), .B1(n5607), .Y(n5525)
);
NOR2X2TS U4755 ( .A(FPMULT_Sgf_normalized_result[0]), .B(
FPMULT_Sgf_normalized_result[1]), .Y(n6173) );
NOR2X1TS U4756 ( .A(FPADDSUB_Add_Subt_result[9]), .B(
FPADDSUB_Add_Subt_result[8]), .Y(n5610) );
NOR2BX1TS U4757 ( .AN(Data_2[19]), .B(n2132), .Y(n2750) );
BUFX3TS U4758 ( .A(n3121), .Y(n2325) );
OAI22X1TS U4759 ( .A0(n3633), .A1(n2325), .B0(n2593), .B1(n2237), .Y(n4239)
);
INVX4TS U4760 ( .A(n3969), .Y(n2327) );
OAI22X1TS U4761 ( .A0(n3809), .A1(n2327), .B0(n3711), .B1(n2274), .Y(n3807)
);
XNOR2X2TS U4762 ( .A(n6381), .B(n2563), .Y(n3960) );
INVX2TS U4763 ( .A(FPMULT_Op_MY[5]), .Y(n2556) );
OAI22X1TS U4764 ( .A0(n2245), .A1(n3337), .B0(n2748), .B1(n3743), .Y(n3392)
);
OAI22X1TS U4765 ( .A0(n2245), .A1(n2748), .B0(n2328), .B1(n2819), .Y(n3469)
);
OAI22X1TS U4766 ( .A0(n3744), .A1(n3742), .B0(n3743), .B1(n3741), .Y(n3854)
);
OAI22X1TS U4767 ( .A0(n3744), .A1(n3741), .B0(n3743), .B1(n3739), .Y(n3801)
);
OAI22X1TS U4768 ( .A0(n3744), .A1(n3678), .B0(n3743), .B1(n3258), .Y(n3675)
);
INVX2TS U4769 ( .A(n3743), .Y(n3104) );
OAI22X1TS U4770 ( .A0(n2241), .A1(n3950), .B0(n2329), .B1(n3795), .Y(n3857)
);
OAI22X1TS U4771 ( .A0(n2128), .A1(n3704), .B0(n2329), .B1(n3677), .Y(n3747)
);
INVX2TS U4772 ( .A(n3659), .Y(n2331) );
AO21X1TS U4773 ( .A0(n2220), .A1(n2331), .B0(n2513), .Y(n4238) );
OAI2BB2X2TS U4774 ( .B0(n3466), .B1(n2330), .A0N(n3427), .A1N(n3426), .Y(
n3447) );
OAI22X2TS U4775 ( .A0(n3197), .A1(n2330), .B0(n3255), .B1(n2458), .Y(n3244)
);
OAI22X2TS U4776 ( .A0(n3255), .A1(n2513), .B0(n2330), .B1(n3252), .Y(n3658)
);
OAI22X1TS U4777 ( .A0(n3922), .A1(n3910), .B0(n2643), .B1(n3902), .Y(n3946)
);
OAI22X1TS U4778 ( .A0(n3922), .A1(n3259), .B0(n3169), .B1(n2333), .Y(n3668)
);
OAI22X1TS U4779 ( .A0(n3920), .A1(n3922), .B0(n3910), .B1(n2333), .Y(n3937)
);
OAI22X1TS U4780 ( .A0(n2243), .A1(n3902), .B0(n3856), .B1(n2333), .Y(n3956)
);
NAND2X2TS U4781 ( .A(n2243), .B(n2643), .Y(n2493) );
OAI22X2TS U4782 ( .A0(n3922), .A1(n3679), .B0(n3259), .B1(n2643), .Y(n3707)
);
OAI22X1TS U4783 ( .A0(n3226), .A1(n4051), .B0(n3217), .B1(n2334), .Y(n3224)
);
OAI22X1TS U4784 ( .A0(n2251), .A1(n4050), .B0(n4049), .B1(n2334), .Y(n4063)
);
AO21X1TS U4785 ( .A0(n2165), .A1(n3899), .B0(n3850), .Y(n3540) );
NOR2X2TS U4786 ( .A(n3899), .B(n2553), .Y(n2552) );
OAI22X1TS U4787 ( .A0(n4072), .A1(n2647), .B0(n2249), .B1(FPMULT_Op_MY[13]),
.Y(n3670) );
XNOR2X2TS U4788 ( .A(FPMULT_Op_MX[22]), .B(n5857), .Y(n2647) );
XNOR2X2TS U4789 ( .A(n5857), .B(n6374), .Y(n3793) );
NOR2X1TS U4790 ( .A(FPMULT_Op_MY[1]), .B(n5857), .Y(n3137) );
XNOR2X1TS U4791 ( .A(n5857), .B(n3900), .Y(n3909) );
INVX2TS U4792 ( .A(n4088), .Y(n2553) );
NOR2BX1TS U4793 ( .AN(n2336), .B(n4060), .Y(n4080) );
XNOR2X1TS U4794 ( .A(n2252), .B(n4088), .Y(n3852) );
NOR2BX1TS U4795 ( .AN(n2336), .B(n2236), .Y(n3251) );
INVX4TS U4796 ( .A(n5858), .Y(n2337) );
INVX4TS U4797 ( .A(n5858), .Y(n2339) );
OAI22X2TS U4798 ( .A0(n4072), .A1(n2339), .B0(n2249), .B1(n2780), .Y(n4667)
);
XOR2X1TS U4799 ( .A(n2338), .B(n2747), .Y(n3742) );
NOR2BX1TS U4800 ( .AN(n2338), .B(n2688), .Y(n3797) );
NOR2BX2TS U4801 ( .AN(n2339), .B(n3951), .Y(n3939) );
XNOR2X1TS U4802 ( .A(n2341), .B(FPMULT_Op_MY[5]), .Y(n3907) );
BUFX3TS U4803 ( .A(n6413), .Y(n2342) );
BUFX3TS U4804 ( .A(n6413), .Y(n2343) );
NOR3X2TS U4805 ( .A(n6412), .B(n6411), .C(n6506), .Y(n6413) );
INVX2TS U4806 ( .A(n6195), .Y(n2344) );
INVX2TS U4807 ( .A(n6195), .Y(n2345) );
INVX2TS U4808 ( .A(n6195), .Y(n2346) );
OAI221X1TS U4809 ( .A0(n6755), .A1(FPADDSUB_intDY[10]), .B0(n6757), .B1(
FPADDSUB_intDY[2]), .C0(n4970), .Y(n4973) );
OAI221X1TS U4810 ( .A0(n6684), .A1(FPADDSUB_intDY[7]), .B0(n6747), .B1(
FPADDSUB_intDY[14]), .C0(n4976), .Y(n4983) );
OAI221X1TS U4811 ( .A0(n6740), .A1(FPADDSUB_intDX[28]), .B0(n6663), .B1(
FPADDSUB_intDY[6]), .C0(n4984), .Y(n4991) );
INVX2TS U4812 ( .A(n2646), .Y(n3623) );
NAND2X1TS U4813 ( .A(n2466), .B(n2448), .Y(n2646) );
OAI22X1TS U4814 ( .A0(n2233), .A1(n3905), .B0(n3862), .B1(n2244), .Y(n3965)
);
OAI22X1TS U4815 ( .A0(n2233), .A1(n3862), .B0(n3825), .B1(n2244), .Y(n3866)
);
XNOR2X2TS U4816 ( .A(FPMULT_Op_MY[11]), .B(FPMULT_Op_MX[8]), .Y(n3476) );
NOR2X2TS U4817 ( .A(n4494), .B(n4493), .Y(n6278) );
ADDFHX2TS U4818 ( .A(n3143), .B(n3142), .CI(n4325), .CO(n3365), .S(n3300) );
NOR4X1TS U4819 ( .A(FPMULT_P_Sgf[2]), .B(FPMULT_P_Sgf[3]), .C(
FPMULT_P_Sgf[4]), .D(FPMULT_P_Sgf[5]), .Y(n5079) );
NOR4X1TS U4820 ( .A(FPMULT_Op_MY[10]), .B(n2281), .C(FPMULT_Op_MY[1]), .D(
FPMULT_Op_MY[2]), .Y(n6371) );
OAI22X1TS U4821 ( .A0(n3046), .A1(n2211), .B0(n2259), .B1(n2529), .Y(n3311)
);
NOR2X2TS U4822 ( .A(FPSENCOS_d_ff2_Y[23]), .B(n2228), .Y(n6599) );
NOR2X2TS U4823 ( .A(FPSENCOS_d_ff2_X[23]), .B(n2228), .Y(n5113) );
BUFX3TS U4824 ( .A(n6499), .Y(n6498) );
XNOR2X2TS U4825 ( .A(FPMULT_Op_MY[5]), .B(FPMULT_Op_MX[4]), .Y(n3696) );
OAI22X1TS U4826 ( .A0(n3794), .A1(n3922), .B0(n3740), .B1(n2333), .Y(n3800)
);
OAI22X2TS U4827 ( .A0(n3794), .A1(n2333), .B0(n2243), .B1(n3856), .Y(n3858)
);
AOI2BB2X2TS U4828 ( .B0(n5005), .B1(n2834), .A0N(n5393), .A1N(n5059), .Y(
n7002) );
AOI211X1TS U4829 ( .A0(FPADDSUB_intDY[16]), .A1(n6761), .B0(n5670), .C0(
n5671), .Y(n5662) );
OAI22X2TS U4830 ( .A0(n6854), .A1(n6861), .B0(n6860), .B1(n6859), .Y(n6403)
);
OAI22X1TS U4831 ( .A0(n3934), .A1(n4085), .B0(n2264), .B1(n2652), .Y(n3989)
);
OAI22X1TS U4832 ( .A0(n3934), .A1(n2264), .B0(n4085), .B1(n2715), .Y(n4111)
);
NOR2XLTS U4833 ( .A(n6713), .B(n6416), .Y(n6417) );
NAND4X2TS U4834 ( .A(FPSENCOS_cordic_FSM_state_reg[0]), .B(
FPSENCOS_cordic_FSM_state_reg[3]), .C(n6720), .D(n6670), .Y(n6416) );
XNOR2X2TS U4835 ( .A(n4691), .B(n4690), .Y(n4697) );
CLKBUFX3TS U4836 ( .A(n7007), .Y(n5023) );
BUFX3TS U4837 ( .A(n7007), .Y(n5022) );
NAND2X2TS U4838 ( .A(n4849), .B(n6672), .Y(n7007) );
NOR2XLTS U4839 ( .A(FPMULT_FSM_selector_B[1]), .B(FPMULT_Op_MY[23]), .Y(
n5868) );
NOR3XLTS U4840 ( .A(n2276), .B(n6367), .C(FPMULT_Op_MY[23]), .Y(n6369) );
NOR3XLTS U4841 ( .A(FPMULT_Op_MX[11]), .B(FPMULT_Op_MX[7]), .C(
FPMULT_Op_MX[24]), .Y(n6383) );
OAI21XLTS U4842 ( .A0(n5069), .A1(n5068), .B0(n5067), .Y(n1702) );
NOR2X4TS U4843 ( .A(FPADDSUB_FS_Module_state_reg[1]), .B(n6407), .Y(n6524)
);
AOI22X2TS U4844 ( .A0(n5508), .A1(n5507), .B0(n5506), .B1(n5607), .Y(n5605)
);
NAND2X2TS U4845 ( .A(n6592), .B(FPSENCOS_sel_mux_1_reg), .Y(n5433) );
AOI32X1TS U4846 ( .A0(FPADDSUB_Add_Subt_result[10]), .A1(n6517), .A2(n6764),
.B0(FPADDSUB_Add_Subt_result[12]), .B1(n6517), .Y(n5934) );
NAND2X1TS U4847 ( .A(FPMULT_Sgf_normalized_result[3]), .B(
FPMULT_Sgf_normalized_result[2]), .Y(n6101) );
OAI21XLTS U4848 ( .A0(FPADDSUB_intDX[1]), .A1(n6790), .B0(FPADDSUB_intDX[0]),
.Y(n5632) );
INVX2TS U4849 ( .A(n2347), .Y(n2348) );
INVX2TS U4850 ( .A(n2349), .Y(n2350) );
OAI221X1TS U4851 ( .A0(n6678), .A1(FPADDSUB_intDX[27]), .B0(n6746), .B1(
FPADDSUB_intDY[19]), .C0(n4986), .Y(n4989) );
OAI221X1TS U4852 ( .A0(n6741), .A1(FPADDSUB_intDY[22]), .B0(n6749), .B1(
FPADDSUB_intDX[12]), .C0(n4995), .Y(n4996) );
OAI221X1TS U4853 ( .A0(n6731), .A1(FPADDSUB_intDY[3]), .B0(n6753), .B1(
FPADDSUB_intDX[26]), .C0(n4978), .Y(n4981) );
OAI221X1TS U4854 ( .A0(n6744), .A1(FPADDSUB_intDY[17]), .B0(n6761), .B1(
FPADDSUB_intDY[16]), .C0(n4994), .Y(n4997) );
INVX2TS U4855 ( .A(n2351), .Y(n2352) );
NOR2X1TS U4856 ( .A(n6685), .B(FPADDSUB_intDX[30]), .Y(n5627) );
NOR2X1TS U4857 ( .A(n6739), .B(FPADDSUB_intDX[25]), .Y(n5679) );
OAI21X4TS U4858 ( .A0(n6288), .A1(n6291), .B0(n6292), .Y(n4498) );
NOR2X4TS U4859 ( .A(n4426), .B(n4425), .Y(n6233) );
NAND2X8TS U4860 ( .A(n4450), .B(n2354), .Y(n4641) );
NAND3BX4TS U4861 ( .AN(n4457), .B(n4449), .C(n4473), .Y(n2354) );
AOI21X4TS U4862 ( .A0(n6251), .A1(n4441), .B0(n4440), .Y(n4457) );
XNOR2X4TS U4863 ( .A(FPMULT_Op_MY[5]), .B(FPMULT_Op_MY[6]), .Y(n2432) );
NAND2X8TS U4864 ( .A(n2357), .B(n2356), .Y(n2445) );
NAND2X8TS U4865 ( .A(n4754), .B(n4803), .Y(n2356) );
NAND2X8TS U4866 ( .A(n2516), .B(n4833), .Y(n4803) );
OA21X4TS U4867 ( .A0(n4840), .A1(n4836), .B0(n4841), .Y(n2357) );
NAND2X8TS U4868 ( .A(n2467), .B(n4750), .Y(n4831) );
NAND3X8TS U4869 ( .A(n2362), .B(n2360), .C(n2358), .Y(n2467) );
OAI22X4TS U4870 ( .A0(n2541), .A1(n2542), .B0(n2136), .B1(n2540), .Y(n2361)
);
NAND2X8TS U4871 ( .A(n2363), .B(n2579), .Y(n2362) );
XNOR2X4TS U4872 ( .A(FPMULT_Op_MY[14]), .B(n2787), .Y(n2364) );
BUFX6TS U4873 ( .A(n2381), .Y(n2366) );
NAND2X8TS U4874 ( .A(n2381), .B(n4227), .Y(n2510) );
OAI2BB1X4TS U4875 ( .A0N(n3339), .A1N(n3340), .B0(n2367), .Y(n3413) );
XOR2X4TS U4876 ( .A(n2368), .B(n3340), .Y(n3354) );
XOR2X4TS U4877 ( .A(n3338), .B(n3339), .Y(n2368) );
NAND3X8TS U4878 ( .A(n2385), .B(n2638), .C(n2618), .Y(n2573) );
BUFX20TS U4879 ( .A(n2573), .Y(n2369) );
NAND2X8TS U4880 ( .A(n4733), .B(n4227), .Y(n4704) );
CLKINVX12TS U4881 ( .A(n2612), .Y(n4840) );
OAI22X4TS U4882 ( .A0(n2466), .A1(n6099), .B0(n2448), .B1(n3900), .Y(n2373)
);
NAND2X8TS U4883 ( .A(n2530), .B(n2828), .Y(n2374) );
NOR2X8TS U4884 ( .A(n2375), .B(n4747), .Y(n4815) );
NAND3X8TS U4885 ( .A(n2394), .B(n2393), .C(n2391), .Y(n2375) );
XOR2X4TS U4886 ( .A(n2376), .B(n2184), .Y(n3783) );
NAND2X8TS U4887 ( .A(n2380), .B(n2379), .Y(n2387) );
OA21X4TS U4888 ( .A0(n3122), .A1(n3124), .B0(n3125), .Y(n2379) );
NAND2X4TS U4889 ( .A(n2388), .B(n3114), .Y(n2380) );
OR2X8TS U4890 ( .A(n2622), .B(n4725), .Y(n2384) );
NAND2X8TS U4891 ( .A(n2425), .B(n2603), .Y(n2385) );
INVX12TS U4892 ( .A(n2386), .Y(n2426) );
NOR2X8TS U4893 ( .A(n2421), .B(n4678), .Y(n2386) );
NOR2X8TS U4894 ( .A(n4207), .B(n4208), .Y(n2421) );
OAI21X4TS U4895 ( .A0(n3116), .A1(n3119), .B0(n3117), .Y(n3114) );
NAND3X6TS U4896 ( .A(n2474), .B(n2527), .C(n2798), .Y(n2389) );
NOR2X8TS U4897 ( .A(n4749), .B(n4748), .Y(n4819) );
NAND3X8TS U4898 ( .A(n2390), .B(n2389), .C(n2121), .Y(n4749) );
OR2X8TS U4899 ( .A(n2474), .B(n2798), .Y(n2390) );
NAND3X6TS U4900 ( .A(n2144), .B(n2689), .C(n2484), .Y(n2393) );
XOR2X4TS U4901 ( .A(n4830), .B(n2397), .Y(FPMULT_Sgf_operation_Result[34])
);
NAND2X8TS U4902 ( .A(n2409), .B(n2609), .Y(n4832) );
NAND2X8TS U4903 ( .A(n2713), .B(n2410), .Y(n2414) );
NAND2X8TS U4904 ( .A(n2161), .B(n2694), .Y(n2713) );
BUFX20TS U4905 ( .A(n2437), .Y(n2411) );
NAND2X8TS U4906 ( .A(n2414), .B(n2412), .Y(n2437) );
AOI21X4TS U4907 ( .A0(n2693), .A1(n4813), .B0(n2413), .Y(n2412) );
OAI21X4TS U4908 ( .A0(n4819), .A1(n4814), .B0(n4820), .Y(n2413) );
OAI21X4TS U4909 ( .A0(n4825), .A1(n4958), .B0(n4826), .Y(n4813) );
XNOR2X4TS U4910 ( .A(n2746), .B(n3097), .Y(n2415) );
OAI2BB1X4TS U4911 ( .A0N(n2138), .A1N(n4334), .B0(n3562), .Y(n2417) );
AOI21X4TS U4912 ( .A0(n2603), .A1(n4665), .B0(n4658), .Y(n4661) );
NAND2X8TS U4913 ( .A(n2476), .B(n2475), .Y(n2603) );
XNOR2X4TS U4914 ( .A(n3194), .B(n3112), .Y(n3518) );
NAND3X8TS U4915 ( .A(n2589), .B(n2587), .C(n2420), .Y(n3194) );
OAI21X4TS U4916 ( .A0(n4204), .A1(n2781), .B0(n4659), .Y(n2695) );
NOR2X8TS U4917 ( .A(n2424), .B(n2423), .Y(n2638) );
NOR2X8TS U4918 ( .A(n4746), .B(n4745), .Y(n4825) );
XOR2X4TS U4919 ( .A(n4737), .B(n4736), .Y(n4746) );
AND2X8TS U4920 ( .A(n2120), .B(n2427), .Y(n2742) );
XOR2X4TS U4921 ( .A(n2428), .B(n4186), .Y(n4188) );
XOR2X4TS U4922 ( .A(n4185), .B(n4187), .Y(n2428) );
NOR2X8TS U4923 ( .A(n4199), .B(n4198), .Y(n4651) );
NAND2BX4TS U4924 ( .AN(n2429), .B(n4442), .Y(n6269) );
XNOR2X4TS U4925 ( .A(n2433), .B(n3686), .Y(n2429) );
XOR2X4TS U4926 ( .A(n2431), .B(n2125), .Y(n2483) );
OAI2BB1X4TS U4927 ( .A0N(n2603), .A1N(n2753), .B0(n2752), .Y(n2431) );
XOR2X4TS U4928 ( .A(n2436), .B(n3687), .Y(n2433) );
OAI21X4TS U4929 ( .A0(n2436), .A1(n3687), .B0(n3686), .Y(n2435) );
OAI2BB1X4TS U4930 ( .A0N(n3687), .A1N(n2436), .B0(n2435), .Y(n4443) );
NAND2BX4TS U4931 ( .AN(n4686), .B(n2444), .Y(n2439) );
NAND2X8TS U4932 ( .A(n2430), .B(n4687), .Y(n2444) );
NAND2X8TS U4933 ( .A(n2442), .B(n2441), .Y(n2783) );
NAND3BX4TS U4934 ( .AN(n4686), .B(n2443), .C(n2444), .Y(n2441) );
NAND2X8TS U4935 ( .A(n2783), .B(n4697), .Y(n4924) );
AOI2BB2X4TS U4936 ( .B0(n2324), .B1(n2447), .A0N(n4807), .A1N(n4786), .Y(
n4788) );
NAND2X8TS U4937 ( .A(n2172), .B(n4754), .Y(n2460) );
BUFX12TS U4938 ( .A(n2530), .Y(n2448) );
XOR2X4TS U4939 ( .A(FPMULT_Op_MY[21]), .B(FPMULT_Op_MY[22]), .Y(n2449) );
NAND2X8TS U4940 ( .A(n2688), .B(n3024), .Y(n3674) );
OAI22X1TS U4941 ( .A0(n2718), .A1(n3394), .B0(n3468), .B1(n2688), .Y(n3473)
);
OAI22X2TS U4942 ( .A0(n2718), .A1(n3027), .B0(n3155), .B1(n2451), .Y(n3150)
);
OAI2BB1X4TS U4943 ( .A0N(n4152), .A1N(n2139), .B0(n2454), .Y(n4148) );
NAND2X4TS U4944 ( .A(n3286), .B(n3284), .Y(n2456) );
OAI21X4TS U4945 ( .A0(n3286), .A1(n3284), .B0(n3285), .Y(n2457) );
OAI22X4TS U4946 ( .A0(n3255), .A1(n3253), .B0(n2330), .B1(n2458), .Y(n3250)
);
XNOR2X4TS U4947 ( .A(n2262), .B(n4037), .Y(n2458) );
NAND2X4TS U4948 ( .A(n4202), .B(n4203), .Y(n4659) );
XOR2X4TS U4949 ( .A(FPMULT_Op_MY[19]), .B(FPMULT_Op_MY[20]), .Y(n2461) );
OAI21X4TS U4950 ( .A0(n4716), .A1(n4734), .B0(n4717), .Y(n2468) );
OAI21X4TS U4951 ( .A0(n3631), .A1(n3632), .B0(n3630), .Y(n2464) );
OAI22X2TS U4952 ( .A0(n2219), .A1(n3701), .B0(n2448), .B1(n3573), .Y(n3520)
);
OAI22X1TS U4953 ( .A0(n2219), .A1(n6379), .B0(n2448), .B1(n2221), .Y(n3091)
);
OAI22X2TS U4954 ( .A0(n2219), .A1(n2221), .B0(n2448), .B1(n6099), .Y(n3083)
);
OAI22X1TS U4955 ( .A0(n3202), .A1(n2166), .B0(n2233), .B1(n2469), .Y(n3275)
);
XOR2X4TS U4956 ( .A(n2471), .B(n2830), .Y(FPMULT_Sgf_operation_Result[47])
);
AOI2BB2X4TS U4957 ( .B0(n2190), .B1(n2411), .A0N(n4807), .A1N(n2470), .Y(
n2471) );
NOR2X8TS U4958 ( .A(n2757), .B(n2758), .Y(n2475) );
OAI21X4TS U4959 ( .A0(n3698), .A1(n3699), .B0(n3697), .Y(n2479) );
XOR2X4TS U4960 ( .A(n3698), .B(n2481), .Y(n2480) );
NAND2X4TS U4961 ( .A(n4199), .B(n4198), .Y(n4652) );
OAI21X4TS U4962 ( .A0(n4011), .A1(n4010), .B0(n4009), .Y(n2487) );
XOR2X4TS U4963 ( .A(n2488), .B(n4011), .Y(n4029) );
XOR2X4TS U4964 ( .A(n4009), .B(n4010), .Y(n2488) );
AOI21X4TS U4965 ( .A0(n4547), .A1(n2490), .B0(n2489), .Y(n4584) );
OAI21X4TS U4966 ( .A0(n4572), .A1(n4569), .B0(n4573), .Y(n2489) );
NOR2X4TS U4967 ( .A(n4572), .B(n4570), .Y(n2490) );
NOR2X8TS U4968 ( .A(n4129), .B(n4130), .Y(n4572) );
OAI22X1TS U4969 ( .A0(n2243), .A1(n3740), .B0(n3679), .B1(n2333), .Y(n3745)
);
OAI22X1TS U4970 ( .A0(n3920), .A1(n2333), .B0(n2243), .B1(n3921), .Y(n4043)
);
XOR2X4TS U4971 ( .A(n4423), .B(n4258), .Y(n2494) );
XNOR2X4TS U4972 ( .A(n2496), .B(n3931), .Y(n4112) );
XOR2X4TS U4973 ( .A(n2500), .B(n3932), .Y(n2496) );
INVX4TS U4974 ( .A(n2510), .Y(n2542) );
NOR2X8TS U4975 ( .A(n4228), .B(n2585), .Y(n2522) );
NAND2X8TS U4976 ( .A(n4223), .B(n4224), .Y(n4734) );
NOR2X8TS U4977 ( .A(n4225), .B(n4226), .Y(n4716) );
XOR2X4TS U4978 ( .A(n2512), .B(n3850), .Y(n3181) );
XOR2X4TS U4979 ( .A(n2512), .B(n2514), .Y(n3788) );
NAND2X8TS U4980 ( .A(n2705), .B(n2706), .Y(n2612) );
OAI2BB1X4TS U4981 ( .A0N(n3456), .A1N(n3455), .B0(n2518), .Y(n4559) );
OAI21X4TS U4982 ( .A0(n3456), .A1(n3455), .B0(n3454), .Y(n2518) );
XOR2X4TS U4983 ( .A(n2519), .B(n3454), .Y(n4541) );
XOR2X4TS U4984 ( .A(n3456), .B(n3455), .Y(n2519) );
AOI21X4TS U4985 ( .A0(n3194), .A1(n3175), .B0(n3174), .Y(n3180) );
NAND2X4TS U4986 ( .A(n4293), .B(n4218), .Y(n2525) );
NOR2X8TS U4987 ( .A(n4221), .B(n4222), .Y(n2622) );
AOI21X4TS U4988 ( .A0(n4331), .A1(n4376), .B0(n4330), .Y(n4406) );
OAI2BB1X4TS U4989 ( .A0N(n2532), .A1N(n2531), .B0(n4388), .Y(n4376) );
INVX2TS U4990 ( .A(n4355), .Y(n4787) );
INVX2TS U4991 ( .A(n4785), .Y(n4792) );
NAND2BX2TS U4992 ( .AN(n2720), .B(n3094), .Y(n2533) );
NAND2BX4TS U4993 ( .AN(n2462), .B(n4706), .Y(n2541) );
XOR2X4TS U4994 ( .A(n2543), .B(n2191), .Y(n2706) );
XOR2X4TS U4995 ( .A(n2546), .B(n3148), .Y(n3145) );
XOR2X4TS U4996 ( .A(n3149), .B(n3150), .Y(n2546) );
OAI2BB1X4TS U4997 ( .A0N(n3308), .A1N(n2536), .B0(n2547), .Y(n4323) );
OAI21X4TS U4998 ( .A0(n2536), .A1(n3308), .B0(n3307), .Y(n2547) );
NAND2X1TS U4999 ( .A(n2242), .B(n2268), .Y(n2564) );
OAI22X2TS U5000 ( .A0(n2549), .A1(n3907), .B0(n2270), .B1(n3960), .Y(n3961)
);
OAI22X1TS U5001 ( .A0(n2549), .A1(n3959), .B0(n2268), .B1(n3827), .Y(n3864)
);
OAI22X1TS U5002 ( .A0(n2549), .A1(n3206), .B0(n2270), .B1(n3011), .Y(n3280)
);
OAI22X1TS U5003 ( .A0(n2549), .A1(n3960), .B0(n2268), .B1(n3959), .Y(n3974)
);
OAI22X2TS U5004 ( .A0(n2269), .A1(n3648), .B0(n3696), .B1(n2549), .Y(n3727)
);
OAI22X2TS U5005 ( .A0(n3017), .A1(n2270), .B0(n3011), .B1(n2242), .Y(n3018)
);
OAI22X1TS U5006 ( .A0(n3017), .A1(n2242), .B0(n3045), .B1(n2270), .Y(n3037)
);
OAI22X1TS U5007 ( .A0(n3274), .A1(n2269), .B0(n3648), .B1(n2242), .Y(n3690)
);
OAI22X1TS U5008 ( .A0(n3316), .A1(n2242), .B0(n2269), .B1(n2817), .Y(n3345)
);
OAI22X1TS U5009 ( .A0(n3316), .A1(n2270), .B0(n3045), .B1(n2242), .Y(n3317)
);
OAI2BB1X4TS U5010 ( .A0N(n2552), .A1N(n3997), .B0(n2550), .Y(n4008) );
XOR2X4TS U5011 ( .A(n2551), .B(n3997), .Y(n3992) );
XOR2X4TS U5012 ( .A(n3996), .B(n2552), .Y(n2551) );
XNOR2X1TS U5013 ( .A(FPMULT_Op_MY[5]), .B(FPMULT_Op_MX[10]), .Y(n3045) );
NAND2X4TS U5014 ( .A(n4882), .B(n4883), .Y(n4625) );
OR2X8TS U5015 ( .A(n4622), .B(n4621), .Y(n4883) );
XOR2X4TS U5016 ( .A(n2560), .B(n4604), .Y(n4622) );
AOI21X4TS U5017 ( .A0(n4602), .A1(n4601), .B0(n4600), .Y(n2560) );
NOR2X8TS U5018 ( .A(n4619), .B(n4620), .Y(n4875) );
XNOR2X4TS U5019 ( .A(n4586), .B(n4602), .Y(n4619) );
OAI22X4TS U5020 ( .A0(n4430), .A1(n2568), .B0(n4263), .B1(n2567), .Y(n4153)
);
NOR2BX4TS U5021 ( .AN(n4263), .B(n4025), .Y(n2568) );
XOR2X4TS U5022 ( .A(n4430), .B(n2569), .Y(n4026) );
XOR2X4TS U5023 ( .A(n4025), .B(n4263), .Y(n2569) );
XOR2X4TS U5024 ( .A(n2570), .B(n4802), .Y(FPMULT_Sgf_operation_Result[46])
);
AOI22X4TS U5025 ( .A0(n2571), .A1(n2411), .B0(n2445), .B1(n2208), .Y(n2570)
);
NAND3X8TS U5026 ( .A(n2369), .B(n2572), .C(n2134), .Y(n2701) );
NAND2X8TS U5027 ( .A(n2574), .B(n4289), .Y(n2698) );
INVX8TS U5028 ( .A(n2701), .Y(n2574) );
XNOR2X4TS U5029 ( .A(n3545), .B(n2575), .Y(n3560) );
XOR2X4TS U5030 ( .A(n3546), .B(n3547), .Y(n2575) );
XOR2X4TS U5031 ( .A(n2577), .B(n3542), .Y(n3566) );
XNOR2X4TS U5032 ( .A(n3080), .B(n2580), .Y(n2619) );
OAI21X4TS U5033 ( .A0(n3078), .A1(n2583), .B0(n2581), .Y(n2580) );
AOI21X4TS U5034 ( .A0(n3110), .A1(n2584), .B0(n2582), .Y(n2581) );
NAND2X2TS U5035 ( .A(n2387), .B(n2584), .Y(n2583) );
NAND2X6TS U5036 ( .A(n3110), .B(n2592), .Y(n2587) );
NOR2X8TS U5037 ( .A(n2591), .B(n2590), .Y(n2589) );
AOI21X4TS U5038 ( .A0(n2411), .A1(n4832), .B0(n2133), .Y(n2596) );
XNOR2X4TS U5039 ( .A(n2597), .B(n3286), .Y(n4283) );
XNOR2X4TS U5040 ( .A(n3285), .B(n3284), .Y(n2597) );
OAI22X2TS U5041 ( .A0(n2211), .A1(n3640), .B0(n2259), .B1(n3272), .Y(n3692)
);
ADDFHX4TS U5042 ( .A(n3264), .B(n3263), .CI(n3262), .CO(n3270), .S(n3680) );
INVX4TS U5043 ( .A(n4275), .Y(n3806) );
INVX2TS U5044 ( .A(n4410), .Y(n3613) );
XOR2X1TS U5045 ( .A(n2731), .B(n2829), .Y(n2734) );
INVX2TS U5046 ( .A(n4642), .Y(n3628) );
INVX6TS U5047 ( .A(n2759), .Y(n3001) );
NAND2X1TS U5048 ( .A(n4283), .B(n4282), .Y(n4313) );
ADDFHX4TS U5049 ( .A(n3767), .B(n3766), .CI(n3765), .CO(n3776), .S(n3779) );
NAND2X1TS U5050 ( .A(n2632), .B(n4659), .Y(n4660) );
NAND2X4TS U5051 ( .A(n4620), .B(n4619), .Y(n4876) );
NOR2X4TS U5052 ( .A(n4485), .B(n4483), .Y(n4473) );
XOR2X4TS U5053 ( .A(n4520), .B(n4519), .Y(n4528) );
OAI22X2TS U5054 ( .A0(n2248), .A1(n3647), .B0(n2260), .B1(n3273), .Y(n3691)
);
ADDFHX4TS U5055 ( .A(n3995), .B(n3994), .CI(n3993), .CO(n4010), .S(n3987) );
NAND2X1TS U5056 ( .A(n2119), .B(n4603), .Y(n4604) );
AOI21X4TS U5057 ( .A0(n2119), .A1(n4600), .B0(n2146), .Y(n4174) );
OAI2BB1X4TS U5058 ( .A0N(n4187), .A1N(n4185), .B0(n2598), .Y(n4178) );
OAI21X4TS U5059 ( .A0(n4185), .A1(n4187), .B0(n4186), .Y(n2598) );
NAND2X1TS U5060 ( .A(n2599), .B(n4939), .Y(n4940) );
INVX8TS U5061 ( .A(n4674), .Y(n2599) );
XNOR2X4TS U5062 ( .A(n2602), .B(n3127), .Y(n3923) );
XOR2X4TS U5063 ( .A(n4442), .B(n2604), .Y(n2756) );
XNOR2X4TS U5064 ( .A(n3055), .B(n3054), .Y(n2605) );
XNOR2X4TS U5065 ( .A(n2607), .B(n3571), .Y(n3592) );
XNOR2X4TS U5066 ( .A(n2614), .B(n3552), .Y(n3538) );
OAI2BB1X4TS U5067 ( .A0N(n3553), .A1N(n3551), .B0(n2617), .Y(n4351) );
XOR2X4TS U5068 ( .A(n2625), .B(FPMULT_Op_MX[11]), .Y(n3216) );
AOI21X4TS U5069 ( .A0(n3194), .A1(n3193), .B0(n2626), .Y(n2625) );
XNOR2X4TS U5070 ( .A(n2629), .B(n3562), .Y(n3535) );
XOR2X4TS U5071 ( .A(n2118), .B(n2140), .Y(n3227) );
XOR2X4TS U5072 ( .A(n3068), .B(n3075), .Y(n2633) );
XNOR2X4TS U5073 ( .A(n2284), .B(n6359), .Y(n3075) );
XNOR2X4TS U5074 ( .A(n2147), .B(n4729), .Y(n4744) );
AOI22X4TS U5075 ( .A0(n2634), .A1(n2411), .B0(n4764), .B1(n2445), .Y(n4767)
);
NOR2X8TS U5076 ( .A(n2506), .B(n4809), .Y(n2634) );
XOR2X4TS U5077 ( .A(n2640), .B(n2189), .Y(n2641) );
XNOR2X4TS U5078 ( .A(n3137), .B(n3138), .Y(n2640) );
AOI2BB2X4TS U5079 ( .B0(n2324), .B1(n2644), .A0N(n4807), .A1N(n4794), .Y(
n4796) );
NAND2BX1TS U5080 ( .AN(n3293), .B(n4325), .Y(n4388) );
XNOR2X4TS U5081 ( .A(n2725), .B(n3307), .Y(n3293) );
XNOR2X4TS U5082 ( .A(n2650), .B(n3872), .Y(n4138) );
AOI21X4TS U5083 ( .A0(n2387), .A1(n3111), .B0(n3110), .Y(n2654) );
NAND4X8TS U5084 ( .A(n2657), .B(n2701), .C(n2700), .D(n2763), .Y(n2656) );
NAND2X8TS U5085 ( .A(n4209), .B(n4210), .Y(n4706) );
NAND2X1TS U5086 ( .A(n4211), .B(n4212), .Y(n4305) );
XOR2X4TS U5087 ( .A(n2667), .B(n4003), .Y(n4142) );
XOR2X4TS U5088 ( .A(n4431), .B(n4269), .Y(n2667) );
XNOR2X4TS U5089 ( .A(n3614), .B(n2673), .Y(n3603) );
XOR2X4TS U5090 ( .A(n3615), .B(n2674), .Y(n2673) );
INVX2TS U5091 ( .A(n4350), .Y(n2679) );
XOR2X4TS U5092 ( .A(n3102), .B(n3101), .Y(n3113) );
XOR2X4TS U5093 ( .A(n3106), .B(n3105), .Y(n2680) );
XOR2X4TS U5094 ( .A(n2681), .B(n4152), .Y(n2772) );
XOR2X4TS U5095 ( .A(n4267), .B(n2139), .Y(n2681) );
XOR2X4TS U5096 ( .A(n4105), .B(n4106), .Y(n2683) );
OAI21X4TS U5097 ( .A0(n4507), .A1(n4510), .B0(n4508), .Y(n4524) );
AOI21X4TS U5098 ( .A0(n4454), .A1(n4455), .B0(n2685), .Y(n4510) );
XOR2X4TS U5099 ( .A(n2692), .B(n4005), .Y(n4028) );
XOR2X4TS U5100 ( .A(n2696), .B(n3700), .Y(n3804) );
XOR2X4TS U5101 ( .A(n4277), .B(n4443), .Y(n2696) );
XNOR2X4TS U5102 ( .A(n3059), .B(n2703), .Y(n2724) );
XNOR2X4TS U5103 ( .A(n2730), .B(FPMULT_Op_MY[10]), .Y(n2703) );
OAI2BB1X4TS U5104 ( .A0N(n3384), .A1N(n3383), .B0(n2707), .Y(n3388) );
OAI21X4TS U5105 ( .A0(n3383), .A1(n3384), .B0(n3382), .Y(n2707) );
XNOR2X4TS U5106 ( .A(n2708), .B(n3382), .Y(n3895) );
XNOR2X4TS U5107 ( .A(n3383), .B(n3384), .Y(n2708) );
AOI21X4TS U5108 ( .A0(n4524), .A1(n4521), .B0(n2710), .Y(n4535) );
NAND2X6TS U5109 ( .A(n2778), .B(n2779), .Y(n4454) );
OAI21X4TS U5110 ( .A0(n6239), .A1(n4435), .B0(n4434), .Y(n6251) );
AOI21X4TS U5111 ( .A0(n4428), .A1(n6226), .B0(n4427), .Y(n6239) );
NAND2X4TS U5112 ( .A(n2716), .B(n6221), .Y(n6226) );
OR2X4TS U5113 ( .A(n6223), .B(n6220), .Y(n2716) );
AOI21X4TS U5114 ( .A0(n6217), .A1(n6216), .B0(n4420), .Y(n6223) );
NAND2BX2TS U5115 ( .AN(n4075), .B(n6256), .Y(n6257) );
NOR2BX4TS U5116 ( .AN(n4061), .B(n2717), .Y(n4075) );
XNOR2X4TS U5117 ( .A(n2719), .B(n3093), .Y(n3234) );
XOR2X4TS U5118 ( .A(n3094), .B(n2720), .Y(n2719) );
OAI2BB1X4TS U5119 ( .A0N(n3818), .A1N(n3817), .B0(n2721), .Y(n3876) );
XOR2X4TS U5120 ( .A(n3818), .B(n3817), .Y(n2722) );
AND2X2TS U5121 ( .A(n2738), .B(n4088), .Y(n3787) );
XOR2X4TS U5122 ( .A(n2724), .B(n2723), .Y(n2738) );
XOR2X4TS U5123 ( .A(n2536), .B(n3308), .Y(n2725) );
OAI2BB1X4TS U5124 ( .A0N(n3700), .A1N(n2745), .B0(n2743), .Y(n3764) );
OAI21X4TS U5125 ( .A0(n3700), .A1(n2745), .B0(n2744), .Y(n2743) );
BUFX6TS U5126 ( .A(FPMULT_Op_MY[19]), .Y(n2748) );
XOR2X4TS U5127 ( .A(n3701), .B(n2747), .Y(n3026) );
AOI21X4TS U5128 ( .A0(n2695), .A1(n2135), .B0(n2137), .Y(n2752) );
XNOR2X4TS U5129 ( .A(n3073), .B(n3072), .Y(n2754) );
XNOR2X4TS U5130 ( .A(n2434), .B(n2756), .Y(n3841) );
XOR2X4TS U5131 ( .A(n2809), .B(FPMULT_Op_MY[9]), .Y(n2759) );
OR2X8TS U5132 ( .A(n3001), .B(n2760), .Y(n3610) );
XNOR2X4TS U5133 ( .A(FPMULT_Op_MY[10]), .B(FPMULT_Op_MY[11]), .Y(n2760) );
OAI21X4TS U5134 ( .A0(n3546), .A1(n3547), .B0(n3545), .Y(n2765) );
XOR2X4TS U5135 ( .A(n4156), .B(n2768), .Y(n4166) );
XOR2X4TS U5136 ( .A(n2773), .B(n4157), .Y(n2768) );
OAI2BB1X4TS U5137 ( .A0N(n2772), .A1N(n2771), .B0(n4156), .Y(n2770) );
OAI2BB1X4TS U5138 ( .A0N(n2776), .A1N(n2429), .B0(n2777), .Y(n3805) );
OAI21X4TS U5139 ( .A0(n2429), .A1(n2776), .B0(n3802), .Y(n2777) );
INVX3TS U5140 ( .A(n4102), .Y(n2779) );
INVX2TS U5141 ( .A(n2159), .Y(n4658) );
OAI21X4TS U5142 ( .A0(n2782), .A1(n4944), .B0(n4945), .Y(n4702) );
AOI21X4TS U5143 ( .A0(n4699), .A1(n4954), .B0(n2157), .Y(n2782) );
XNOR2X4TS U5144 ( .A(n4140), .B(n2784), .Y(n4169) );
XOR2X4TS U5145 ( .A(n4142), .B(n2785), .Y(n2784) );
XNOR2X4TS U5146 ( .A(n2786), .B(n6368), .Y(n3058) );
INVX2TS U5147 ( .A(n3187), .Y(n2790) );
XOR2X4TS U5148 ( .A(n3184), .B(n3188), .Y(n2792) );
ADDFHX4TS U5149 ( .A(n4031), .B(n4030), .CI(n4029), .CO(n4130), .S(n4128) );
XNOR2X2TS U5150 ( .A(n3923), .B(n2131), .Y(n3197) );
ADDFHX4TS U5151 ( .A(n4133), .B(n4132), .CI(n4131), .CO(n4185), .S(n4193) );
XNOR2X2TS U5152 ( .A(FPMULT_Op_MY[13]), .B(FPMULT_Op_MX[14]), .Y(n4047) );
OAI22X1TS U5153 ( .A0(n3744), .A1(n3028), .B0(n2328), .B1(n3026), .Y(n3031)
);
OAI22X1TS U5154 ( .A0(n3744), .A1(n3154), .B0(n2328), .B1(n3337), .Y(n3336)
);
ADDFHX2TS U5155 ( .A(n3092), .B(n2338), .CI(n3091), .CO(n3159), .S(n3265) );
ADDFHX4TS U5156 ( .A(n3846), .B(n3845), .CI(n3844), .CO(n4439), .S(n4437) );
ADDFHX4TS U5157 ( .A(n3843), .B(n3842), .CI(n3841), .CO(n3880), .S(n4186) );
ADDFHX4TS U5158 ( .A(n3459), .B(n3458), .CI(n3457), .CO(n3512), .S(n3462) );
NAND2X2TS U5159 ( .A(n4073), .B(n4085), .Y(n4083) );
ADDFHX2TS U5160 ( .A(n3031), .B(n3030), .CI(n3029), .CO(n3147), .S(n3094) );
ADDFHX4TS U5161 ( .A(n3221), .B(n3220), .CI(n3219), .CO(n4452), .S(n4447) );
ADDFHX4TS U5162 ( .A(n3913), .B(n3912), .CI(n3911), .CO(n4425), .S(n4424) );
OAI22X1TS U5163 ( .A0(n3711), .A1(n2327), .B0(n3256), .B1(n2274), .Y(n3756)
);
XNOR2X4TS U5164 ( .A(n3185), .B(n3186), .Y(n3136) );
CMPR22X2TS U5165 ( .A(n3976), .B(n3975), .CO(n4003), .S(n4004) );
CMPR22X2TS U5166 ( .A(n3791), .B(n3790), .CO(n3840), .S(n3872) );
ADDFHX4TS U5167 ( .A(n3387), .B(n3386), .CI(n3385), .CO(n3488), .S(n3440) );
XNOR2X2TS U5168 ( .A(n6365), .B(FPMULT_Op_MX[8]), .Y(n3044) );
INVX2TS U5169 ( .A(n4037), .Y(n3129) );
CMPR22X2TS U5170 ( .A(n3658), .B(n3657), .CO(n3757), .S(n3719) );
ADDFHX4TS U5171 ( .A(n3508), .B(n3507), .CI(n3506), .CO(n4341), .S(n4334) );
XNOR2X2TS U5172 ( .A(n2282), .B(FPMULT_Op_MX[11]), .Y(n3501) );
ADDFHX2TS U5173 ( .A(n3701), .B(n3573), .CI(n3572), .CO(n3607), .S(n3575) );
OAI22X2TS U5174 ( .A0(n3971), .A1(n2274), .B0(n3970), .B1(n3423), .Y(n4005)
);
ADDFHX2TS U5175 ( .A(n3008), .B(n3007), .CI(n3006), .CO(n3211), .S(n3278) );
ADDFHX2TS U5176 ( .A(n3049), .B(n3048), .CI(n3047), .CO(n3310), .S(n3035) );
CMPR22X2TS U5177 ( .A(n3209), .B(n3208), .CO(n3279), .S(n3650) );
OAI22X2TS U5178 ( .A0(n2247), .A1(n3273), .B0(n2260), .B1(n3003), .Y(n3208)
);
ADDFHX2TS U5179 ( .A(n3205), .B(n3204), .CI(n3203), .CO(n3215), .S(n3282) );
ADDFHX2TS U5180 ( .A(n3958), .B(n3957), .CI(n3956), .CO(n3982), .S(n3978) );
XNOR2X2TS U5181 ( .A(n2277), .B(FPMULT_Op_MX[7]), .Y(n3014) );
OAI22X2TS U5182 ( .A0(n2247), .A1(n3015), .B0(n2260), .B1(n2801), .Y(n3042)
);
XNOR2X2TS U5183 ( .A(n2281), .B(FPMULT_Op_MX[11]), .Y(n3015) );
ADDFHX4TS U5184 ( .A(n3511), .B(n3510), .CI(n3509), .CO(n4581), .S(n4560) );
ADDFHX4TS U5185 ( .A(n3381), .B(n3380), .CI(n3379), .CO(n3389), .S(n3367) );
ADDFHX4TS U5186 ( .A(n3410), .B(n3409), .CI(n3408), .CO(n3454), .S(n3417) );
ADDFHX4TS U5187 ( .A(n3983), .B(n3982), .CI(n3981), .CO(n4269), .S(n4263) );
XNOR2X4TS U5188 ( .A(n2492), .B(n3900), .Y(n3856) );
ADDFHX2TS U5189 ( .A(n3362), .B(n3361), .CI(n3360), .CO(n3433), .S(n3378) );
ADDFHX2TS U5190 ( .A(n3485), .B(n3484), .CI(n3483), .CO(n3489), .S(n3443) );
ADDFHX4TS U5191 ( .A(n3974), .B(n3973), .CI(n3972), .CO(n4429), .S(n4426) );
ADDFHX4TS U5192 ( .A(n3835), .B(n3834), .CI(n3833), .CO(n4273), .S(n4267) );
ADDFHX2TS U5193 ( .A(n3347), .B(n3346), .CI(n3345), .CO(n3409), .S(n3353) );
ADDFHX2TS U5194 ( .A(n3540), .B(n3539), .CI(n3538), .CO(n3585), .S(n3562) );
NOR2X6TS U5195 ( .A(n4439), .B(n4438), .Y(n6263) );
ADDFHX4TS U5196 ( .A(n3812), .B(n3811), .CI(n3810), .CO(n4442), .S(n4438) );
ADDFHX2TS U5197 ( .A(n3242), .B(n3241), .CI(n3240), .CO(n3299), .S(n3295) );
ADDFHX4TS U5198 ( .A(n3390), .B(n3389), .CI(n3388), .CO(n3487), .S(n3438) );
XNOR2X2TS U5199 ( .A(n2281), .B(FPMULT_Op_MX[9]), .Y(n3003) );
ADDFHX2TS U5200 ( .A(n3942), .B(n3941), .CI(n3940), .CO(n4423), .S(n4422) );
XNOR2X4TS U5201 ( .A(n4037), .B(n2252), .Y(n3832) );
ADDFHX2TS U5202 ( .A(n3770), .B(n3769), .CI(n3768), .CO(n3778), .S(n3875) );
ADDFHX2TS U5203 ( .A(n3758), .B(n3757), .CI(n3756), .CO(n3765), .S(n3768) );
ADDFHX4TS U5204 ( .A(n3453), .B(n3452), .CI(n3451), .CO(n4335), .S(n4332) );
ADDFHX2TS U5205 ( .A(n3277), .B(n3276), .CI(n3275), .CO(n3283), .S(n3653) );
ADDFHX4TS U5206 ( .A(n3482), .B(n3481), .CI(n3480), .CO(n3509), .S(n3456) );
OAI22X2TS U5207 ( .A0(n3754), .A1(n4051), .B0(n3226), .B1(n4060), .Y(n3772)
);
OAI22X2TS U5208 ( .A0(n3755), .A1(n4051), .B0(n3754), .B1(n2334), .Y(n3769)
);
OAI22X2TS U5209 ( .A0(n2128), .A1(n3677), .B0(n3951), .B1(n3260), .Y(n3706)
);
ADDFHX4TS U5210 ( .A(n3415), .B(n3414), .CI(n3413), .CO(n4333), .S(n4328) );
ADDFHX4TS U5211 ( .A(n3356), .B(n3355), .CI(n3354), .CO(n4329), .S(n4326) );
MXI2X1TS U5212 ( .A(Data_2[15]), .B(n2492), .S0(n6097), .Y(n2796) );
OR2X4TS U5213 ( .A(n4801), .B(n4802), .Y(n2797) );
OR2X2TS U5214 ( .A(n4613), .B(n4614), .Y(n2826) );
XOR2X1TS U5215 ( .A(n4763), .B(n4762), .Y(n2830) );
BUFX3TS U5216 ( .A(FPADDSUB_FSM_selector_A), .Y(n2986) );
XNOR2X2TS U5217 ( .A(n3751), .B(n2263), .Y(n3226) );
ADDFHX2TS U5218 ( .A(n4020), .B(n4019), .CI(n4018), .CO(n4152), .S(n4149) );
INVX2TS U5219 ( .A(n4288), .Y(n4217) );
OAI22X2TS U5220 ( .A0(n2766), .A1(n3476), .B0(n2231), .B1(n3502), .Y(n3498)
);
OAI22X2TS U5221 ( .A0(n3257), .A1(n3901), .B0(n3855), .B1(n2816), .Y(n3957)
);
ADDFHX2TS U5222 ( .A(n3617), .B(n3616), .CI(n2679), .CO(n3636), .S(n3614) );
NAND2X1TS U5223 ( .A(n4267), .B(n4270), .Y(n4709) );
NOR2X2TS U5224 ( .A(n4332), .B(n4333), .Y(n4366) );
NAND2X1TS U5225 ( .A(n4710), .B(n4709), .Y(n4711) );
NAND2X1TS U5226 ( .A(n4318), .B(n4312), .Y(n4321) );
NOR2X1TS U5227 ( .A(n6023), .B(n6024), .Y(n6038) );
NAND2X1TS U5228 ( .A(n4368), .B(n4367), .Y(n4369) );
INVX2TS U5229 ( .A(n6068), .Y(n6070) );
NAND2X2TS U5230 ( .A(n4437), .B(n4436), .Y(n6260) );
NAND2X1TS U5231 ( .A(n4950), .B(n4925), .Y(n4926) );
NAND2X1TS U5232 ( .A(n4832), .B(n4831), .Y(n4830) );
INVX2TS U5233 ( .A(FPSENCOS_d_ff2_X[11]), .Y(n6479) );
INVX2TS U5234 ( .A(FPSENCOS_d_ff2_X[13]), .Y(n6477) );
INVX2TS U5235 ( .A(FPSENCOS_d_ff2_X[15]), .Y(n6475) );
INVX2TS U5236 ( .A(FPSENCOS_d_ff2_X[2]), .Y(n6489) );
INVX2TS U5237 ( .A(FPSENCOS_d_ff2_X[22]), .Y(n6465) );
INVX2TS U5238 ( .A(FPSENCOS_d_ff_Yn[23]), .Y(n6586) );
OAI211XLTS U5239 ( .A0(n5417), .A1(n5416), .B0(n5415), .C0(n5414), .Y(n1839)
);
BUFX3TS U5240 ( .A(n6716), .Y(n5472) );
NAND2X2TS U5241 ( .A(FPADDSUB_FS_Module_state_reg[1]), .B(
FPADDSUB_FS_Module_state_reg[2]), .Y(n5416) );
NAND2X1TS U5242 ( .A(FPADDSUB_add_overflow_flag), .B(n5416), .Y(n2837) );
NOR2X2TS U5243 ( .A(FPADDSUB_FSM_selector_B[0]), .B(
FPADDSUB_FSM_selector_B[1]), .Y(n2840) );
XOR2X1TS U5244 ( .A(n2876), .B(n2841), .Y(n2875) );
BUFX3TS U5245 ( .A(FPADDSUB_FSM_selector_A), .Y(n2983) );
XOR2X1TS U5246 ( .A(n2876), .B(n2842), .Y(n2854) );
XOR2X1TS U5247 ( .A(n2876), .B(n2843), .Y(n2857) );
NOR2X2TS U5248 ( .A(n6715), .B(FPADDSUB_FSM_selector_B[1]), .Y(n2844) );
BUFX6TS U5249 ( .A(n2844), .Y(n5248) );
XOR2X1TS U5250 ( .A(n2876), .B(n2845), .Y(n2860) );
XOR2X1TS U5251 ( .A(n2876), .B(n2846), .Y(n2863) );
XOR2X1TS U5252 ( .A(n2876), .B(n2847), .Y(n2866) );
XOR2X1TS U5253 ( .A(n2876), .B(n2848), .Y(n2871) );
CLKMX2X2TS U5254 ( .A(FPADDSUB_DMP[23]), .B(FPADDSUB_exp_oper_result[0]),
.S0(n2983), .Y(n2868) );
NAND2X1TS U5255 ( .A(n5248), .B(FPADDSUB_LZA_output[0]), .Y(n2850) );
NAND2X1TS U5256 ( .A(n6715), .B(FPADDSUB_FSM_selector_B[1]), .Y(n2849) );
AO21X1TS U5257 ( .A0(FPADDSUB_DmP[23]), .A1(n6715), .B0(n5249), .Y(n2851) );
XOR2X4TS U5258 ( .A(n2876), .B(n2851), .Y(n2867) );
CMPR32X2TS U5259 ( .A(n2857), .B(n2856), .C(n2855), .CO(n2852), .S(n5929) );
CMPR32X2TS U5260 ( .A(n2863), .B(n2862), .C(n2861), .CO(n2858), .S(n5931) );
CMPR32X2TS U5261 ( .A(n2866), .B(n2865), .C(n2864), .CO(n2861), .S(n5950) );
CMPR32X2TS U5262 ( .A(n2868), .B(n2876), .C(n2867), .CO(n2869), .S(n5933) );
AND4X1TS U5263 ( .A(n5931), .B(n5950), .C(n5933), .D(n5932), .Y(n2872) );
AND4X1TS U5264 ( .A(n5928), .B(n5929), .C(n5930), .D(n2872), .Y(n2878) );
CMPR32X2TS U5265 ( .A(n2875), .B(n2874), .C(n2873), .CO(n2877), .S(n5927) );
XOR2X1TS U5266 ( .A(n2877), .B(n2876), .Y(n5715) );
AOI21X1TS U5267 ( .A0(n5927), .A1(n2878), .B0(n5715), .Y(n2883) );
OR2X2TS U5268 ( .A(FPADDSUB_FS_Module_state_reg[1]), .B(n6719), .Y(n5060) );
INVX2TS U5269 ( .A(n5060), .Y(n4912) );
NAND2X1TS U5270 ( .A(n5005), .B(n4912), .Y(n2880) );
NAND2X1TS U5271 ( .A(FPADDSUB_FS_Module_state_reg[1]), .B(n6719), .Y(n5393)
);
NAND2X1TS U5272 ( .A(FPADDSUB_FS_Module_state_reg[0]), .B(n5422), .Y(n2879)
);
NAND2X1TS U5273 ( .A(n2212), .B(overflow_flag_addsubt), .Y(n2882) );
INVX2TS U5274 ( .A(n5053), .Y(n2884) );
INVX4TS U5275 ( .A(n2141), .Y(n6206) );
XOR2X1TS U5290 ( .A(n2913), .B(FPADDSUB_Sgf_normalized_result[1]), .Y(n2886)
);
BUFX3TS U5291 ( .A(FPADDSUB_FSM_selector_A), .Y(n5091) );
NOR2X2TS U5292 ( .A(n2886), .B(n2885), .Y(n5953) );
OR2X1TS U5293 ( .A(n2981), .B(FPADDSUB_Sgf_normalized_result[2]), .Y(n2887)
);
XOR2X1TS U5294 ( .A(n2913), .B(n2887), .Y(n2892) );
BUFX3TS U5295 ( .A(FPADDSUB_FSM_selector_A), .Y(n2917) );
NOR2X1TS U5296 ( .A(n2892), .B(n2891), .Y(n5955) );
NOR2X1TS U5297 ( .A(n5953), .B(n5955), .Y(n2894) );
NOR2BX1TS U5298 ( .AN(FPADDSUB_Sgf_normalized_result[0]), .B(n2986), .Y(
n2888) );
XOR2X1TS U5299 ( .A(n2988), .B(n2888), .Y(n5885) );
INVX2TS U5300 ( .A(n5885), .Y(n2890) );
NOR2X1TS U5301 ( .A(n2988), .B(n2889), .Y(n5886) );
NOR2X1TS U5302 ( .A(n2890), .B(n5886), .Y(n5951) );
NAND2X1TS U5303 ( .A(n2892), .B(n2891), .Y(n5956) );
INVX2TS U5304 ( .A(n5956), .Y(n2893) );
AOI21X2TS U5305 ( .A0(n2894), .A1(n5951), .B0(n2893), .Y(n5961) );
NOR2BX1TS U5306 ( .AN(FPADDSUB_Sgf_normalized_result[3]), .B(n5091), .Y(
n2895) );
XOR2X1TS U5307 ( .A(n2913), .B(n2895), .Y(n2900) );
NOR2BX1TS U5308 ( .AN(FPADDSUB_Sgf_normalized_result[4]), .B(n2986), .Y(
n2896) );
XOR2X1TS U5309 ( .A(n2913), .B(n2896), .Y(n2902) );
NOR2X2TS U5310 ( .A(n2902), .B(n2901), .Y(n5974) );
NOR2BX1TS U5311 ( .AN(FPADDSUB_Sgf_normalized_result[5]), .B(n2986), .Y(
n2897) );
NOR2X2TS U5312 ( .A(n2904), .B(n2903), .Y(n5994) );
NOR2BX1TS U5313 ( .AN(FPADDSUB_Sgf_normalized_result[6]), .B(n5091), .Y(
n2898) );
XOR2X1TS U5314 ( .A(n2913), .B(n2898), .Y(n2906) );
NOR2X2TS U5315 ( .A(n2906), .B(n2905), .Y(n5996) );
NAND2X2TS U5316 ( .A(n2900), .B(n2899), .Y(n5971) );
NAND2X1TS U5317 ( .A(n2902), .B(n2901), .Y(n5975) );
OAI21X1TS U5318 ( .A0(n5974), .A1(n5971), .B0(n5975), .Y(n5987) );
NAND2X1TS U5319 ( .A(n2904), .B(n2903), .Y(n5993) );
NAND2X1TS U5320 ( .A(n2906), .B(n2905), .Y(n5997) );
AOI21X1TS U5321 ( .A0(n5987), .A1(n2908), .B0(n2907), .Y(n2909) );
NOR2BX1TS U5322 ( .AN(FPADDSUB_Sgf_normalized_result[7]), .B(n5091), .Y(
n2911) );
NOR2X2TS U5323 ( .A(n2922), .B(n2921), .Y(n6023) );
NOR2BX1TS U5324 ( .AN(FPADDSUB_Sgf_normalized_result[8]), .B(n5091), .Y(
n2912) );
XOR2X1TS U5325 ( .A(n2913), .B(n2912), .Y(n2924) );
NOR2X2TS U5326 ( .A(n2924), .B(n2923), .Y(n6024) );
NOR2BX1TS U5327 ( .AN(FPADDSUB_Sgf_normalized_result[9]), .B(n5091), .Y(
n2914) );
XOR2X1TS U5328 ( .A(n2969), .B(n2914), .Y(n2926) );
NOR2BX1TS U5329 ( .AN(FPADDSUB_Sgf_normalized_result[10]), .B(n5091), .Y(
n2915) );
XOR2X1TS U5330 ( .A(n2969), .B(n2915), .Y(n2928) );
NOR2X2TS U5331 ( .A(n2928), .B(n2927), .Y(n6049) );
NOR2BX1TS U5332 ( .AN(FPADDSUB_Sgf_normalized_result[11]), .B(n5091), .Y(
n2916) );
XOR2X1TS U5333 ( .A(n2969), .B(n2918), .Y(n2934) );
NOR2X2TS U5334 ( .A(n2934), .B(n2933), .Y(n6087) );
XOR2X1TS U5335 ( .A(n2969), .B(n2920), .Y(n2938) );
NOR2X2TS U5336 ( .A(n2938), .B(n2937), .Y(n6068) );
NAND2X2TS U5337 ( .A(n6062), .B(n2940), .Y(n2942) );
NOR2X2TS U5338 ( .A(n6060), .B(n2942), .Y(n2944) );
NAND2X2TS U5339 ( .A(n2922), .B(n2921), .Y(n6022) );
NAND2X1TS U5340 ( .A(n2924), .B(n2923), .Y(n6025) );
OAI21X1TS U5341 ( .A0(n6024), .A1(n6022), .B0(n6025), .Y(n6039) );
NAND2X1TS U5342 ( .A(n2926), .B(n2925), .Y(n6045) );
NAND2X1TS U5343 ( .A(n2928), .B(n2927), .Y(n6050) );
OAI21X1TS U5344 ( .A0(n6049), .A1(n6045), .B0(n6050), .Y(n2929) );
AOI21X2TS U5345 ( .A0(n6039), .A1(n2930), .B0(n2929), .Y(n6059) );
NAND2X2TS U5346 ( .A(n2932), .B(n2931), .Y(n6083) );
NAND2X1TS U5347 ( .A(n2934), .B(n2933), .Y(n6088) );
OAI21X1TS U5348 ( .A0(n6087), .A1(n6083), .B0(n6088), .Y(n6063) );
NAND2X1TS U5349 ( .A(n2936), .B(n2935), .Y(n6078) );
NAND2X1TS U5350 ( .A(n2938), .B(n2937), .Y(n6069) );
AOI21X1TS U5351 ( .A0(n6063), .A1(n2940), .B0(n2939), .Y(n2941) );
OAI21X2TS U5352 ( .A0(n6059), .A1(n2942), .B0(n2941), .Y(n2943) );
AOI21X4TS U5353 ( .A0(n6013), .A1(n2944), .B0(n2943), .Y(n6030) );
XOR2X1TS U5354 ( .A(n2969), .B(n2946), .Y(n2950) );
INVX2TS U5355 ( .A(n6055), .Y(n6031) );
NAND2X1TS U5356 ( .A(n2950), .B(n2949), .Y(n6032) );
INVX2TS U5357 ( .A(n6032), .Y(n2951) );
AOI21X1TS U5358 ( .A0(n6033), .A1(n6031), .B0(n2951), .Y(n2952) );
OAI21X4TS U5359 ( .A0(n6030), .A1(n2953), .B0(n2952), .Y(n6020) );
INVX2TS U5360 ( .A(n6017), .Y(n2957) );
XOR2X1TS U5361 ( .A(n2988), .B(n2961), .Y(n2963) );
NAND2X1TS U5362 ( .A(n2963), .B(n2962), .Y(n6002) );
INVX2TS U5363 ( .A(n6002), .Y(n2964) );
XOR2X1TS U5364 ( .A(n2988), .B(n2965), .Y(n2967) );
NOR2X1TS U5365 ( .A(n2967), .B(n2966), .Y(n5981) );
NAND2X1TS U5366 ( .A(n2967), .B(n2966), .Y(n5982) );
OAI21X4TS U5367 ( .A0(n5985), .A1(n5981), .B0(n5982), .Y(n5968) );
XOR2X1TS U5368 ( .A(n2969), .B(n2968), .Y(n2972) );
NAND2X1TS U5369 ( .A(n2972), .B(n2971), .Y(n5965) );
INVX2TS U5370 ( .A(n5965), .Y(n2973) );
AOI21X4TS U5371 ( .A0(n5968), .A1(n5966), .B0(n2973), .Y(n4894) );
XOR2X1TS U5372 ( .A(n2988), .B(n2974), .Y(n2976) );
NOR2X1TS U5373 ( .A(n2976), .B(n2975), .Y(n4890) );
NAND2X1TS U5374 ( .A(n2976), .B(n2975), .Y(n4891) );
OAI21X4TS U5375 ( .A0(n4894), .A1(n4890), .B0(n4891), .Y(n4857) );
XOR2X1TS U5376 ( .A(n2988), .B(n2977), .Y(n2979) );
NAND2X1TS U5377 ( .A(n2979), .B(n2978), .Y(n4854) );
INVX2TS U5378 ( .A(n4854), .Y(n2980) );
AOI21X4TS U5379 ( .A0(n4857), .A1(n4855), .B0(n2980), .Y(n4900) );
XOR2X1TS U5380 ( .A(n2988), .B(n2982), .Y(n2985) );
NOR2X1TS U5381 ( .A(n2985), .B(n2984), .Y(n4896) );
NAND2X1TS U5382 ( .A(n2985), .B(n2984), .Y(n4897) );
NOR2BX1TS U5383 ( .AN(FPADDSUB_Sgf_normalized_result[25]), .B(n5091), .Y(
n2987) );
XOR2X1TS U5384 ( .A(n2988), .B(n2987), .Y(n4859) );
XNOR2X4TS U5387 ( .A(FPMULT_Op_MY[8]), .B(FPMULT_Op_MY[7]), .Y(n2993) );
XNOR2X1TS U5388 ( .A(FPMULT_Op_MY[9]), .B(FPMULT_Op_MX[4]), .Y(n3005) );
XNOR2X4TS U5389 ( .A(FPMULT_Op_MY[2]), .B(FPMULT_Op_MY[1]), .Y(n2996) );
XNOR2X1TS U5390 ( .A(n2129), .B(FPMULT_Op_MX[10]), .Y(n2999) );
OAI22X1TS U5391 ( .A0(n2247), .A1(n3003), .B0(n2260), .B1(n2999), .Y(n3203)
);
OAI22X1TS U5392 ( .A0(n2995), .A1(n2999), .B0(n3925), .B1(n3015), .Y(n3012)
);
NAND2BX1TS U5393 ( .AN(n2340), .B(n2276), .Y(n3002) );
NOR2BX1TS U5394 ( .AN(n2210), .B(n2163), .Y(n3008) );
XNOR2X2TS U5395 ( .A(n6381), .B(n6368), .Y(n3199) );
XNOR2X1TS U5396 ( .A(FPMULT_Op_MY[1]), .B(FPMULT_Op_MX[11]), .Y(n3202) );
OAI22X1TS U5397 ( .A0(n2233), .A1(n3202), .B0(n2807), .B1(n2244), .Y(n3006)
);
OAI22X1TS U5398 ( .A0(n2211), .A1(n3005), .B0(n2259), .B1(n3016), .Y(n3212)
);
XNOR2X2TS U5399 ( .A(n6382), .B(n6368), .Y(n3020) );
OAI22X2TS U5400 ( .A0(n3610), .A1(n3009), .B0(n2230), .B1(n3020), .Y(n3019)
);
INVX2TS U5401 ( .A(n6381), .Y(n3010) );
ADDFX2TS U5402 ( .A(n3013), .B(n2807), .CI(n3012), .CO(n3040), .S(n3214) );
XNOR2X1TS U5403 ( .A(n2283), .B(FPMULT_Op_MX[6]), .Y(n3046) );
OAI22X1TS U5404 ( .A0(n2211), .A1(n3016), .B0(n3695), .B1(n3046), .Y(n3041)
);
ADDFHX2TS U5405 ( .A(n3019), .B(n3048), .CI(n3018), .CO(n3036), .S(n3210) );
NOR2X1TS U5406 ( .A(n2163), .B(n2804), .Y(n3049) );
XNOR2X2TS U5407 ( .A(n6368), .B(FPMULT_Op_MX[4]), .Y(n3051) );
XNOR2X1TS U5408 ( .A(n6360), .B(n3573), .Y(n3022) );
OAI22X1TS U5409 ( .A0(n2128), .A1(n3022), .B0(n2329), .B1(n3025), .Y(n3034)
);
XOR2X4TS U5410 ( .A(n6358), .B(n3919), .Y(n3023) );
XNOR2X1TS U5411 ( .A(FPMULT_Op_MY[21]), .B(n6373), .Y(n3081) );
XNOR2X1TS U5412 ( .A(FPMULT_Op_MY[21]), .B(n3792), .Y(n3027) );
OAI22X1TS U5413 ( .A0(n3674), .A1(n3081), .B0(n2688), .B1(n3027), .Y(n3029)
);
OAI22X1TS U5414 ( .A0(n2245), .A1(n3026), .B0(n3743), .B1(n3154), .Y(n3151)
);
ADDFHX4TS U5415 ( .A(n3034), .B(n3033), .CI(n3032), .CO(n3308), .S(n3093) );
INVX2TS U5416 ( .A(n6382), .Y(n3050) );
NOR2X1TS U5417 ( .A(n2163), .B(n3050), .Y(n3322) );
OAI22X2TS U5418 ( .A0(n3610), .A1(n3051), .B0(n2230), .B1(n3315), .Y(n3321)
);
INVX2TS U5419 ( .A(n4451), .Y(n3292) );
INVX2TS U5420 ( .A(n3065), .Y(n3052) );
OAI22X1TS U5421 ( .A0(n3144), .A1(n2331), .B0(n3128), .B1(n3255), .Y(n3143)
);
INVX2TS U5422 ( .A(n3107), .Y(n3066) );
XNOR2X4TS U5423 ( .A(n3074), .B(n3069), .Y(n3073) );
NAND2X4TS U5424 ( .A(n3071), .B(n3070), .Y(n3097) );
NAND2X4TS U5425 ( .A(n3105), .B(n3097), .Y(n3072) );
INVX2TS U5426 ( .A(n3111), .Y(n3078) );
OAI22X1TS U5427 ( .A0(n3096), .A1(n2258), .B0(n3302), .B1(n2271), .Y(n3142)
);
XNOR2X2TS U5428 ( .A(n6359), .B(n3900), .Y(n3090) );
NOR2X1TS U5429 ( .A(n3086), .B(n2249), .Y(n3092) );
OAI22X1TS U5430 ( .A0(n3228), .A1(n3725), .B0(n3096), .B1(n2271), .Y(n3242)
);
XNOR2X2TS U5431 ( .A(n3977), .B(n2253), .Y(n3233) );
NAND2X2TS U5432 ( .A(n3189), .B(n3183), .Y(n3101) );
NOR2X2TS U5433 ( .A(n3104), .B(n3103), .Y(n3106) );
INVX2TS U5434 ( .A(n3132), .Y(n3175) );
NAND2X2TS U5435 ( .A(n3175), .B(n3173), .Y(n3112) );
OAI22X2TS U5436 ( .A0(n3233), .A1(n2257), .B0(n3181), .B1(n3899), .Y(n3241)
);
INVX2TS U5437 ( .A(n3116), .Y(n3118) );
XOR2X4TS U5438 ( .A(n3120), .B(n3119), .Y(n4070) );
INVX2TS U5439 ( .A(n4070), .Y(n3196) );
OAI22X1TS U5440 ( .A0(n3129), .A1(n2236), .B0(n3196), .B1(n3121), .Y(n3131)
);
XNOR2X4TS U5441 ( .A(FPMULT_Op_MY[1]), .B(n5857), .Y(n3230) );
XNOR2X4TS U5442 ( .A(n3230), .B(n2167), .Y(n4069) );
INVX2TS U5443 ( .A(n3124), .Y(n3126) );
INVX2TS U5444 ( .A(n3923), .Y(n3301) );
OAI22X1TS U5445 ( .A0(n3301), .A1(n2237), .B0(n3129), .B1(n2325), .Y(n3141)
);
OAI21X4TS U5446 ( .A0(n3176), .A1(n3173), .B0(n3177), .Y(n3190) );
OAI21X4TS U5447 ( .A0(FPMULT_Op_MY[2]), .A1(n6358), .B0(FPMULT_Op_MY[1]),
.Y(n3135) );
NAND2X4TS U5448 ( .A(n3135), .B(n3134), .Y(n3185) );
XNOR2X2TS U5449 ( .A(n3229), .B(n2263), .Y(n3217) );
OAI22X1TS U5450 ( .A0(n3217), .A1(n4051), .B0(n4060), .B1(n4033), .Y(n3139)
);
XNOR2X2TS U5451 ( .A(n3933), .B(n2262), .Y(n3331) );
OAI22X1TS U5452 ( .A0(n3144), .A1(n3255), .B0(n3331), .B1(n2331), .Y(n3375)
);
NAND2X2TS U5453 ( .A(n3156), .B(n2179), .Y(n3335) );
ADDFHX4TS U5454 ( .A(n3160), .B(n3159), .CI(n3158), .CO(n3236), .S(n3284) );
XNOR2X2TS U5455 ( .A(n2285), .B(n3792), .Y(n3260) );
XNOR2X2TS U5456 ( .A(n2452), .B(FPMULT_Op_MX[14]), .Y(n3261) );
OAI22X2TS U5457 ( .A0(n3674), .A1(n3261), .B0(n2688), .B1(n3165), .Y(n3263)
);
INVX2TS U5458 ( .A(n3173), .Y(n3174) );
INVX2TS U5459 ( .A(n3176), .Y(n3178) );
NAND2X1TS U5460 ( .A(n3178), .B(n3177), .Y(n3179) );
XOR2X4TS U5461 ( .A(n3180), .B(n3179), .Y(n3327) );
XNOR2X1TS U5462 ( .A(n3216), .B(n2255), .Y(n3304) );
OAI22X1TS U5463 ( .A0(n3218), .A1(n2327), .B0(n3304), .B1(n2274), .Y(n3305)
);
NAND2X4TS U5464 ( .A(n3195), .B(n3119), .Y(n3198) );
OAI22X1TS U5465 ( .A0(n3196), .A1(n2236), .B0(n3198), .B1(n3121), .Y(n3245)
);
XNOR2X2TS U5466 ( .A(n4070), .B(n2131), .Y(n3253) );
XNOR2X1TS U5467 ( .A(n2276), .B(n2340), .Y(n3200) );
XNOR2X1TS U5468 ( .A(FPMULT_Op_MY[5]), .B(FPMULT_Op_MX[6]), .Y(n3274) );
XNOR2X1TS U5469 ( .A(FPMULT_Op_MY[7]), .B(FPMULT_Op_MX[4]), .Y(n3271) );
OAI22X1TS U5470 ( .A0(n3735), .A1(n3271), .B0(n3734), .B1(n3207), .Y(n3651)
);
OAI22X1TS U5471 ( .A0(n3225), .A1(n2274), .B0(n3256), .B1(n2327), .Y(n3773)
);
XNOR2X2TS U5472 ( .A(n3783), .B(n2263), .Y(n3754) );
XOR2X1TS U5473 ( .A(n2816), .B(n3230), .Y(n3232) );
AND2X4TS U5474 ( .A(n3232), .B(n4087), .Y(n3752) );
OAI22X2TS U5475 ( .A0(n3753), .A1(n4085), .B0(n2222), .B1(n4087), .Y(n3238)
);
XNOR2X2TS U5476 ( .A(n3933), .B(n2253), .Y(n3664) );
ADDFHX4TS U5477 ( .A(n3236), .B(n3235), .CI(n3234), .CO(n4325), .S(n4324) );
ADDFHX4TS U5478 ( .A(n3248), .B(n3247), .CI(n3246), .CO(n4446), .S(n4415) );
ADDFHX2TS U5479 ( .A(n3251), .B(n3250), .CI(n3249), .CO(n3243), .S(n3758) );
XNOR2X1TS U5480 ( .A(n2131), .B(n4088), .Y(n3254) );
OAI22X2TS U5481 ( .A0(n3649), .A1(n3735), .B0(n3734), .B1(n3271), .Y(n3646)
);
NOR2BX1TS U5482 ( .AN(n2340), .B(n2230), .Y(n3645) );
ADDFHX2TS U5483 ( .A(n3280), .B(n3279), .CI(n3278), .CO(n3213), .S(n3666) );
INVX4TS U5484 ( .A(n4445), .Y(n3684) );
ADDFHX4TS U5485 ( .A(n3294), .B(n3293), .CI(n3292), .CO(n3384), .S(n3883) );
ADDFHX4TS U5486 ( .A(n3300), .B(n3299), .CI(n3298), .CO(n3383), .S(n3881) );
INVX2TS U5487 ( .A(n2118), .Y(n3329) );
OAI22X1TS U5488 ( .A0(n3329), .A1(n2236), .B0(n3301), .B1(n3121), .Y(n3361)
);
XNOR2X4TS U5489 ( .A(n3783), .B(n2253), .Y(n3363) );
XNOR2X2TS U5490 ( .A(n3229), .B(n2255), .Y(n3330) );
OAI22X1TS U5491 ( .A0(n3304), .A1(n2327), .B0(n3330), .B1(n2274), .Y(n3376)
);
ADDFHX4TS U5492 ( .A(n3314), .B(n3313), .CI(n3312), .CO(n3358), .S(n3324) );
INVX2TS U5493 ( .A(n3402), .Y(n3347) );
XNOR2X1TS U5494 ( .A(n6368), .B(FPMULT_Op_MX[6]), .Y(n3344) );
OAI22X1TS U5495 ( .A0(n3735), .A1(n3320), .B0(n3734), .B1(n3348), .Y(n3343)
);
INVX2TS U5496 ( .A(n4503), .Y(n3370) );
OAI22X1TS U5497 ( .A0(n3428), .A1(n2271), .B0(n3328), .B1(n3725), .Y(n3437)
);
INVX2TS U5498 ( .A(n4001), .Y(n3424) );
OAI22X1TS U5499 ( .A0(n3424), .A1(n2237), .B0(n3329), .B1(n2325), .Y(n3431)
);
XNOR2X1TS U5500 ( .A(n6359), .B(n3573), .Y(n3394) );
XNOR2X2TS U5501 ( .A(FPMULT_Op_MX[7]), .B(n6368), .Y(n3403) );
XNOR2X1TS U5502 ( .A(n2282), .B(FPMULT_Op_MX[9]), .Y(n3399) );
NOR2X1TS U5503 ( .A(n3735), .B(n3348), .Y(n3350) );
ADDFHX4TS U5504 ( .A(n3359), .B(n3358), .CI(n3357), .CO(n4517), .S(n4502) );
OAI22X1TS U5505 ( .A0(n3363), .A1(n2257), .B0(n3419), .B1(n2335), .Y(n3432)
);
ADDFHX4TS U5506 ( .A(n3366), .B(n3365), .CI(n3364), .CO(n3385), .S(n3382) );
ADDFHX4TS U5507 ( .A(n3369), .B(n3368), .CI(n3367), .CO(n3439), .S(n3893) );
XNOR2X1TS U5508 ( .A(n2452), .B(FPMULT_Op_MX[22]), .Y(n3468) );
CMPR32X2TS U5509 ( .A(n3900), .B(n6373), .C(n3395), .CO(n3472), .S(n3398) );
INVX4TS U5510 ( .A(n4332), .Y(n3459) );
XNOR2X1TS U5511 ( .A(n2283), .B(FPMULT_Op_MX[10]), .Y(n3475) );
OAI22X1TS U5512 ( .A0(n2211), .A1(n3399), .B0(n2259), .B1(n3475), .Y(n3482)
);
INVX2TS U5513 ( .A(n3500), .Y(n3478) );
OAI22X1TS U5514 ( .A0(n3735), .A1(n3404), .B0(n3734), .B1(n2815), .Y(n3477)
);
ADDFHX2TS U5515 ( .A(n3407), .B(n3406), .CI(n3405), .CO(n3455), .S(n3408) );
ADDFHX4TS U5516 ( .A(n4328), .B(n3412), .CI(n3411), .CO(n3461), .S(n3435) );
ADDFHX4TS U5517 ( .A(n3418), .B(n3417), .CI(n3416), .CO(n4542), .S(n4516) );
XNOR2X2TS U5518 ( .A(n3229), .B(n2253), .Y(n3450) );
OAI22X1TS U5519 ( .A0(n3419), .A1(n2257), .B0(n3450), .B1(n3899), .Y(n3463)
);
INVX2TS U5520 ( .A(n3425), .Y(n3427) );
ADDFHX4TS U5521 ( .A(n3440), .B(n3439), .CI(n3438), .CO(n4222), .S(n4220) );
ADDFHX4TS U5522 ( .A(n3446), .B(n3445), .CI(n3444), .CO(n3529), .S(n3486) );
OAI22X1TS U5523 ( .A0(n3495), .A1(n2331), .B0(n3466), .B1(n2220), .Y(n3527)
);
OAI22X1TS U5524 ( .A0(n3467), .A1(n2258), .B0(n3524), .B1(n2271), .Y(n3526)
);
OAI22X1TS U5525 ( .A0(n3674), .A1(n3468), .B0(n2688), .B1(n2452), .Y(n3521)
);
ADDFHX2TS U5526 ( .A(n2812), .B(n3470), .CI(n3469), .CO(n3507), .S(n3471) );
OAI22X2TS U5527 ( .A0(n3474), .A1(n2325), .B0(n3519), .B1(n2237), .Y(n3497)
);
XNOR2X2TS U5528 ( .A(n2276), .B(FPMULT_Op_MX[9]), .Y(n3502) );
ADDFX2TS U5529 ( .A(n3479), .B(n3478), .CI(n3477), .CO(n3510), .S(n3480) );
ADDFHX4TS U5530 ( .A(n3488), .B(n3487), .CI(n3486), .CO(n4224), .S(n4221) );
ADDFHX2TS U5531 ( .A(n3491), .B(n3489), .CI(n3490), .CO(n3533), .S(n3492) );
ADDFHX4TS U5532 ( .A(n3494), .B(n3493), .CI(n3492), .CO(n3532), .S(n3528) );
ADDFHX4TS U5533 ( .A(n4334), .B(n3497), .CI(n3496), .CO(n3543), .S(n3525) );
INVX2TS U5534 ( .A(n3580), .Y(n3557) );
OAI22X1TS U5535 ( .A0(n3610), .A1(n3502), .B0(n2230), .B1(n3554), .Y(n3555)
);
INVX2TS U5536 ( .A(n4341), .Y(n3559) );
INVX2TS U5537 ( .A(n4581), .Y(n3558) );
ADDFX2TS U5538 ( .A(n3514), .B(n3513), .CI(n3512), .CO(n3565), .S(n3494) );
ADDFHX4TS U5539 ( .A(n3517), .B(n3516), .CI(n3515), .CO(n3536), .S(n3513) );
ADDFHX2TS U5540 ( .A(n3527), .B(n3526), .CI(n3525), .CO(n3534), .S(n3490) );
ADDFHX4TS U5541 ( .A(n3530), .B(n3529), .CI(n3528), .CO(n4226), .S(n4223) );
ADDFHX4TS U5542 ( .A(n3533), .B(n3532), .CI(n3531), .CO(n4210), .S(n4225) );
INVX2TS U5543 ( .A(n3836), .Y(n3587) );
OAI22X1TS U5544 ( .A0(n3587), .A1(n2237), .B0(n3537), .B1(n2325), .Y(n3586)
);
OAI22X1TS U5545 ( .A0(n3541), .A1(n2220), .B0(n3588), .B1(n2331), .Y(n3584)
);
INVX2TS U5546 ( .A(n4596), .Y(n3591) );
OAI22X1TS U5547 ( .A0(n3548), .A1(n3725), .B0(n2271), .B1(n2140), .Y(n3590)
);
ADDFHX2TS U5548 ( .A(n3566), .B(n3565), .CI(n3564), .CO(n3567), .S(n3531) );
ADDFHX4TS U5549 ( .A(n3569), .B(n3568), .CI(n3567), .CO(n4212), .S(n4209) );
INVX2TS U5550 ( .A(n4411), .Y(n3611) );
INVX2TS U5551 ( .A(n3626), .Y(n3606) );
OAI22X1TS U5552 ( .A0(n2766), .A1(n3577), .B0(n2231), .B1(n3608), .Y(n3605)
);
CMPR32X2TS U5553 ( .A(n3580), .B(n3579), .C(n3578), .CO(n3604), .S(n3582) );
INVX2TS U5554 ( .A(n4613), .Y(n3617) );
INVX2TS U5555 ( .A(n4614), .Y(n3616) );
CMPR32X2TS U5556 ( .A(n3586), .B(n3585), .C(n3584), .CO(n3602), .S(n3594) );
INVX2TS U5557 ( .A(n3783), .Y(n3619) );
OAI22X1TS U5558 ( .A0(n3587), .A1(n2325), .B0(n3619), .B1(n2237), .Y(n3600)
);
OAI22X1TS U5559 ( .A0(n3588), .A1(n2220), .B0(n3618), .B1(n2331), .Y(n3599)
);
ADDFHX2TS U5560 ( .A(n3591), .B(n3590), .CI(n3589), .CO(n3598), .S(n3571) );
CMPR32X2TS U5561 ( .A(n3606), .B(n3605), .C(n3604), .CO(n4643), .S(n4613) );
INVX2TS U5562 ( .A(n4643), .Y(n3632) );
INVX2TS U5563 ( .A(n4759), .Y(n3629) );
NOR2X1TS U5564 ( .A(n3608), .B(n2827), .Y(n3625) );
OAI22X1TS U5565 ( .A0(n3618), .A1(n2220), .B0(n2331), .B1(n2513), .Y(n3635)
);
INVX2TS U5566 ( .A(n3751), .Y(n3633) );
OAI22X1TS U5567 ( .A0(n3619), .A1(n2325), .B0(n3633), .B1(n2237), .Y(n3634)
);
CMPR32X2TS U5568 ( .A(n3626), .B(n3625), .C(n3624), .CO(n3627), .S(n4642) );
INVX2TS U5569 ( .A(n3627), .Y(n4233) );
INVX2TS U5570 ( .A(n4758), .Y(n4232) );
CMPR32X2TS U5571 ( .A(n4758), .B(n3629), .C(n3628), .CO(n4236), .S(n3631) );
CMPR32X2TS U5572 ( .A(n3636), .B(n3635), .C(n3634), .CO(n4230), .S(n3637) );
CMPR32X2TS U5573 ( .A(n3639), .B(n3638), .C(n3637), .CO(n4229), .S(n3620) );
XNOR2X1TS U5574 ( .A(n2284), .B(n2340), .Y(n3641) );
OAI22X1TS U5575 ( .A0(n2995), .A1(n3730), .B0(n3647), .B1(n3925), .Y(n3728)
);
OAI22X1TS U5576 ( .A0(n2235), .A1(n3729), .B0(n2326), .B1(n3649), .Y(n3726)
);
OAI22X4TS U5577 ( .A0(n3660), .A1(n3831), .B0(n2258), .B1(n3721), .Y(n3786)
);
XNOR2X2TS U5578 ( .A(n2118), .B(n2252), .Y(n3688) );
ADDFHX4TS U5579 ( .A(n3663), .B(n3662), .CI(n3661), .CO(n4282), .S(n4277) );
XNOR2X2TS U5580 ( .A(n4001), .B(n2253), .Y(n3689) );
OAI22X1TS U5581 ( .A0(n3689), .A1(n2165), .B0(n3664), .B1(n3899), .Y(n3717)
);
ADDFHX4TS U5582 ( .A(n3667), .B(n3666), .CI(n3665), .CO(n4445), .S(n4444) );
XNOR2X1TS U5583 ( .A(n2452), .B(n2337), .Y(n3672) );
NAND2BX1TS U5584 ( .AN(n2338), .B(n6359), .Y(n3673) );
OAI22X1TS U5585 ( .A0(n3744), .A1(n3739), .B0(n2328), .B1(n3678), .Y(n3746)
);
ADDFHX4TS U5586 ( .A(n3685), .B(n3684), .CI(n3683), .CO(n3775), .S(n3762) );
NOR2BX1TS U5587 ( .AN(n2210), .B(n3695), .Y(n3824) );
OAI22X2TS U5588 ( .A0(n3795), .A1(n2128), .B0(n2329), .B1(n3704), .Y(n3798)
);
INVX4TS U5589 ( .A(n4276), .Y(n3808) );
ADDFHX4TS U5590 ( .A(n3717), .B(n3716), .CI(n3715), .CO(n3763), .S(n3877) );
XNOR2X2TS U5591 ( .A(n3836), .B(n2263), .Y(n3755) );
OAI22X2TS U5592 ( .A0(n3755), .A1(n4060), .B0(n3788), .B1(n4051), .Y(n3817)
);
OAI22X2TS U5593 ( .A0(n3725), .A1(n3722), .B0(n3721), .B1(n3831), .Y(n3791)
);
NAND2BX1TS U5594 ( .AN(n2336), .B(n3723), .Y(n3724) );
OAI22X2TS U5595 ( .A0(n2258), .A1(n2140), .B0(n3831), .B1(n3724), .Y(n3790)
);
OAI22X1TS U5596 ( .A0(n3735), .A1(n3731), .B0(n3734), .B1(n3729), .Y(n3830)
);
OAI22X1TS U5597 ( .A0(n2995), .A1(n3826), .B0(n3925), .B1(n3730), .Y(n3829)
);
XNOR2X1TS U5598 ( .A(n6365), .B(n2340), .Y(n3732) );
ADDFHX2TS U5599 ( .A(n3738), .B(n3737), .CI(n3736), .CO(n3811), .S(n3844) );
XNOR2X1TS U5600 ( .A(n3919), .B(FPMULT_Op_MX[17]), .Y(n3794) );
ADDFHX2TS U5601 ( .A(n3747), .B(n3746), .CI(n3745), .CO(n3708), .S(n3834) );
OAI22X1TS U5602 ( .A0(n3784), .A1(n4038), .B0(n3753), .B1(n2264), .Y(n3770)
);
ADDFHX4TS U5603 ( .A(n3761), .B(n3760), .CI(n3759), .CO(n3888), .S(n3891) );
ADDFHX4TS U5604 ( .A(n3764), .B(n3763), .CI(n3762), .CO(n3886), .S(n3782) );
CMPR32X2TS U5605 ( .A(n3773), .B(n3772), .C(n3771), .CO(n3760), .S(n3777) );
ADDFHX4TS U5606 ( .A(n3779), .B(n3778), .CI(n3777), .CO(n3885), .S(n3821) );
ADDFHX4TS U5607 ( .A(n3782), .B(n3781), .CI(n3780), .CO(n3892), .S(n3820) );
OAI22X1TS U5608 ( .A0(n3837), .A1(n4038), .B0(n3784), .B1(n2264), .Y(n3843)
);
XNOR2X1TS U5609 ( .A(n2285), .B(n2221), .Y(n3950) );
ADDFHX2TS U5610 ( .A(n3798), .B(n3797), .CI(n3796), .CO(n3748), .S(n4013) );
ADDFHX2TS U5611 ( .A(n3801), .B(n3800), .CI(n3799), .CO(n3835), .S(n4012) );
ADDFHX4TS U5612 ( .A(n3805), .B(n3804), .CI(n3803), .CO(n3781), .S(n3879) );
ADDFHX2TS U5613 ( .A(n3808), .B(n3807), .CI(n3806), .CO(n3803), .S(n4181) );
OAI22X1TS U5614 ( .A0(n3871), .A1(n2327), .B0(n3809), .B1(n2275), .Y(n4145)
);
INVX2TS U5615 ( .A(n4274), .Y(n4143) );
ADDFHX4TS U5616 ( .A(n3821), .B(n3820), .CI(n3819), .CO(n4203), .S(n4201) );
ADDFHX2TS U5617 ( .A(n3824), .B(n3823), .CI(n3822), .CO(n3736), .S(n4017) );
XNOR2X1TS U5618 ( .A(FPMULT_Op_MY[1]), .B(FPMULT_Op_MX[6]), .Y(n3862) );
OAI22X2TS U5619 ( .A0(n2248), .A1(n3863), .B0(n3925), .B1(n3826), .Y(n3865)
);
ADDFHX2TS U5620 ( .A(n3830), .B(n3829), .CI(n3828), .CO(n3845), .S(n4015) );
NOR2BX1TS U5621 ( .AN(n2336), .B(n3831), .Y(n4020) );
OAI22X2TS U5622 ( .A0(n3874), .A1(n4085), .B0(n3837), .B1(n2264), .Y(n4147)
);
NAND2BX1TS U5623 ( .AN(n2336), .B(n2252), .Y(n3849) );
NOR2BX1TS U5624 ( .AN(n2339), .B(n2120), .Y(n3958) );
ADDFHX2TS U5625 ( .A(n3859), .B(n3858), .CI(n3857), .CO(n4014), .S(n3981) );
XNOR2X1TS U5626 ( .A(n2129), .B(n6382), .Y(n3906) );
OAI22X1TS U5627 ( .A0(n2248), .A1(n3906), .B0(n3925), .B1(n3863), .Y(n3963)
);
OAI22X1TS U5628 ( .A0(n3871), .A1(n2275), .B0(n3870), .B1(n2327), .Y(n4139)
);
OAI22X1TS U5629 ( .A0(n3874), .A1(n2264), .B0(n4021), .B1(n4038), .Y(n4137)
);
ADDFHX4TS U5630 ( .A(n3877), .B(n3876), .CI(n3875), .CO(n3780), .S(n4177) );
ADDFHX4TS U5631 ( .A(n3882), .B(n3883), .CI(n3881), .CO(n3368), .S(n3898) );
ADDFHX4TS U5632 ( .A(n3886), .B(n3885), .CI(n3884), .CO(n3897), .S(n3890) );
ADDFHX4TS U5633 ( .A(n3889), .B(n3888), .CI(n3887), .CO(n3894), .S(n3896) );
ADDFHX4TS U5634 ( .A(n3891), .B(n3892), .CI(n3890), .CO(n4205), .S(n4202) );
ADDFHX4TS U5635 ( .A(n3895), .B(n3894), .CI(n3893), .CO(n4219), .S(n4207) );
ADDFHX4TS U5636 ( .A(n3898), .B(n3897), .CI(n3896), .CO(n4208), .S(n4206) );
OAI22X1TS U5637 ( .A0(n4072), .A1(n3909), .B0(n3901), .B1(n2816), .Y(n3947)
);
XNOR2X1TS U5638 ( .A(n6360), .B(n2337), .Y(n3903) );
NAND2BX1TS U5639 ( .AN(n2339), .B(n2285), .Y(n3904) );
OAI22X2TS U5640 ( .A0(n2248), .A1(n3908), .B0(n2260), .B1(n3906), .Y(n3912)
);
XNOR2X2TS U5641 ( .A(n5857), .B(n6099), .Y(n3918) );
OAI22X2TS U5642 ( .A0(n3257), .A1(n3918), .B0(n3909), .B1(n2249), .Y(n3938)
);
XNOR2X1TS U5643 ( .A(n3919), .B(n6379), .Y(n3920) );
INVX2TS U5644 ( .A(n2183), .Y(n4059) );
INVX2TS U5645 ( .A(n4416), .Y(n4058) );
OR2X4TS U5646 ( .A(n4059), .B(n4058), .Y(n3927) );
XNOR2X1TS U5647 ( .A(n2281), .B(n2340), .Y(n3917) );
OAI22X1TS U5648 ( .A0(n2995), .A1(n3917), .B0(n3925), .B1(n3916), .Y(n3929)
);
XNOR2X1TS U5649 ( .A(n3919), .B(n2339), .Y(n3921) );
INVX2TS U5650 ( .A(n4255), .Y(n4052) );
NAND2BX1TS U5651 ( .AN(n2341), .B(n2281), .Y(n3924) );
OAI22X2TS U5652 ( .A0(n2248), .A1(n2801), .B0(n2260), .B1(n3924), .Y(n4418)
);
INVX2TS U5653 ( .A(n4418), .Y(n4036) );
CMPR22X2TS U5654 ( .A(n3928), .B(n3927), .CO(n4054), .S(n4035) );
CMPR22X2TS U5655 ( .A(n3930), .B(n3929), .CO(n4421), .S(n4419) );
INVX2TS U5656 ( .A(n4419), .Y(n4034) );
OAI22X1TS U5657 ( .A0(n3935), .A1(n4060), .B0(n4049), .B1(n2251), .Y(n4040)
);
XNOR2X1TS U5658 ( .A(n4001), .B(n2223), .Y(n3934) );
OAI22X1TS U5659 ( .A0(n3936), .A1(n2334), .B0(n3935), .B1(n2251), .Y(n4110)
);
NOR2BX1TS U5660 ( .AN(n2336), .B(n2273), .Y(n4057) );
INVX2TS U5661 ( .A(n4422), .Y(n4055) );
ADDFHX2TS U5662 ( .A(n3947), .B(n3946), .CI(n3945), .CO(n4261), .S(n4257) );
INVX2TS U5663 ( .A(n4257), .Y(n3967) );
XNOR2X1TS U5664 ( .A(n2254), .B(n4088), .Y(n3949) );
OAI22X1TS U5665 ( .A0(n3423), .A1(n3949), .B0(n3948), .B1(n2275), .Y(n3966)
);
OAI22X1TS U5666 ( .A0(n2241), .A1(n3952), .B0(n2329), .B1(n3950), .Y(n3980)
);
CMPR22X2TS U5667 ( .A(n3962), .B(n3961), .CO(n3973), .S(n3911) );
ADDFHX2TS U5668 ( .A(n3968), .B(n3967), .CI(n3966), .CO(n3993), .S(n4108) );
ADDFHX4TS U5669 ( .A(n3986), .B(n3985), .CI(n3984), .CO(n4431), .S(n4430) );
ADDFHX4TS U5670 ( .A(n3992), .B(n3991), .CI(n3990), .CO(n4011), .S(n4121) );
OAI22X1TS U5671 ( .A0(n4024), .A1(n2334), .B0(n4002), .B1(n4051), .Y(n4006)
);
ADDFHX4TS U5672 ( .A(n4014), .B(n4013), .CI(n4012), .CO(n4270), .S(n4268) );
INVX4TS U5673 ( .A(n4268), .Y(n4151) );
ADDFHX4TS U5674 ( .A(n4017), .B(n4016), .CI(n4015), .CO(n4436), .S(n4432) );
ADDFHX4TS U5675 ( .A(n4028), .B(n4027), .CI(n4026), .CO(n4158), .S(n4031) );
OAI22X1TS U5676 ( .A0(n4039), .A1(n2264), .B0(n4071), .B1(n4038), .Y(n4098)
);
ADDFHX4TS U5677 ( .A(n4042), .B(n4041), .CI(n4040), .CO(n4113), .S(n4115) );
INVX2TS U5678 ( .A(n4253), .Y(n4065) );
INVX2TS U5679 ( .A(n4668), .Y(n4068) );
INVX2TS U5680 ( .A(n4417), .Y(n4067) );
INVX2TS U5681 ( .A(n4251), .Y(n4066) );
XNOR2X1TS U5682 ( .A(n4048), .B(n2336), .Y(n4050) );
ADDFHX4TS U5683 ( .A(n4054), .B(n4053), .CI(n4052), .CO(n3931), .S(n4106) );
XNOR2X1TS U5684 ( .A(n4059), .B(n4058), .Y(n4081) );
NAND2BX1TS U5685 ( .AN(n2210), .B(n2278), .Y(n4061) );
OAI22X2TS U5686 ( .A0(n2233), .A1(n2210), .B0(n4062), .B1(n2244), .Y(n6256)
);
INVX2TS U5687 ( .A(n6256), .Y(n4074) );
ADDFHX4TS U5688 ( .A(n4065), .B(n4064), .CI(n4063), .CO(n4107), .S(n4096) );
CMPR32X2TS U5689 ( .A(n4068), .B(n4067), .C(n4066), .CO(n4064), .S(n4078) );
XNOR2X1TS U5690 ( .A(n4070), .B(n4069), .Y(n4086) );
OAI22X1TS U5691 ( .A0(n4071), .A1(n4087), .B0(n4086), .B1(n4085), .Y(n4077)
);
INVX2TS U5692 ( .A(n4667), .Y(n4084) );
NAND2BX1TS U5693 ( .AN(n4088), .B(n2223), .Y(n4073) );
OAI22X1TS U5694 ( .A0(n4086), .A1(n4087), .B0(n4085), .B1(n2336), .Y(n4089)
);
OR2X2TS U5695 ( .A(n4090), .B(n4089), .Y(n4480) );
NOR2BX1TS U5696 ( .AN(n2210), .B(n2166), .Y(n6255) );
INVX2TS U5697 ( .A(n6255), .Y(n4492) );
NOR2BX2TS U5698 ( .AN(n2338), .B(n2816), .Y(n4655) );
INVX2TS U5699 ( .A(n4655), .Y(n4491) );
NOR2BX1TS U5700 ( .AN(n4088), .B(n4087), .Y(n4490) );
INVX2TS U5701 ( .A(n4481), .Y(n4092) );
INVX2TS U5702 ( .A(n4479), .Y(n4091) );
ADDFHX4TS U5703 ( .A(n4097), .B(n4096), .CI(n4095), .CO(n4103), .S(n4102) );
ADDFHX4TS U5704 ( .A(n4124), .B(n4123), .CI(n4122), .CO(n4125), .S(n4118) );
OAI21X4TS U5705 ( .A0(n4535), .A1(n4532), .B0(n4533), .Y(n4547) );
ADDFHX2TS U5706 ( .A(n4135), .B(n4136), .CI(n4134), .CO(n4133), .S(n4163) );
ADDFHX4TS U5707 ( .A(n4151), .B(n4150), .CI(n4149), .CO(n4157), .S(n4160) );
ADDFHX4TS U5708 ( .A(n4165), .B(n4166), .CI(n4164), .CO(n4173), .S(n4171) );
ADDFHX4TS U5709 ( .A(n4169), .B(n4168), .CI(n4167), .CO(n4170), .S(n4129) );
NAND2X4TS U5710 ( .A(n4171), .B(n4170), .Y(n4585) );
OAI21X4TS U5711 ( .A0(n4175), .A1(n4584), .B0(n4174), .Y(n4626) );
ADDFHX4TS U5712 ( .A(n4178), .B(n4177), .CI(n4176), .CO(n4200), .S(n4199) );
ADDFHX2TS U5713 ( .A(n4181), .B(n4180), .CI(n4179), .CO(n3878), .S(n4190) );
INVX6TS U5714 ( .A(n4651), .Y(n4195) );
ADDFHX4TS U5715 ( .A(n4190), .B(n4189), .CI(n4188), .CO(n4198), .S(n4197) );
ADDFHX4TS U5716 ( .A(n4193), .B(n4192), .CI(n4191), .CO(n4196), .S(n4172) );
INVX6TS U5717 ( .A(n4649), .Y(n4194) );
XNOR2X1TS U5718 ( .A(n4235), .B(n4234), .Y(n4244) );
CMPR32X2TS U5719 ( .A(n4238), .B(n4237), .C(n4236), .CO(n4243), .S(n4241) );
CMPR32X2TS U5720 ( .A(n4241), .B(n4240), .C(n4239), .CO(n4242), .S(n4231) );
INVX2TS U5721 ( .A(n4312), .Y(n4249) );
NOR2X1TS U5722 ( .A(n4249), .B(n4311), .Y(n4281) );
NOR2X1TS U5723 ( .A(n4251), .B(n2183), .Y(n4250) );
NAND2X1TS U5724 ( .A(n4251), .B(n2183), .Y(n4662) );
INVX2TS U5725 ( .A(n4689), .Y(n4254) );
INVX2TS U5726 ( .A(n4694), .Y(n4259) );
NAND2X1TS U5727 ( .A(n4261), .B(n4260), .Y(n4731) );
INVX2TS U5728 ( .A(n4731), .Y(n4738) );
INVX2TS U5729 ( .A(n4740), .Y(n4264) );
AOI21X2TS U5730 ( .A0(n2823), .A1(n4738), .B0(n4264), .Y(n4265) );
OAI21X4TS U5731 ( .A0(n4730), .A1(n4266), .B0(n4265), .Y(n4707) );
NOR2X2TS U5732 ( .A(n4267), .B(n4270), .Y(n4708) );
NOR2X2TS U5733 ( .A(n4268), .B(n4269), .Y(n4720) );
INVX2TS U5734 ( .A(n4317), .Y(n4279) );
OAI21X1TS U5735 ( .A0(n4279), .A1(n4311), .B0(n4314), .Y(n4280) );
INVX2TS U5736 ( .A(n4315), .Y(n4284) );
INVX2TS U5737 ( .A(n4311), .Y(n4290) );
INVX2TS U5738 ( .A(n4297), .Y(n4308) );
INVX2TS U5739 ( .A(n4307), .Y(n4298) );
INVX2TS U5740 ( .A(n4299), .Y(n4301) );
OAI21X1TS U5741 ( .A0(n4315), .A1(n4314), .B0(n4313), .Y(n4316) );
NOR2X4TS U5742 ( .A(n4386), .B(n4387), .Y(n4374) );
NOR2X2TS U5743 ( .A(n4326), .B(n4327), .Y(n4378) );
NOR2X2TS U5744 ( .A(n4329), .B(n4328), .Y(n4382) );
NAND2X4TS U5745 ( .A(n4374), .B(n4331), .Y(n4397) );
NOR2X2TS U5746 ( .A(n4335), .B(n4334), .Y(n4358) );
NOR2X2TS U5747 ( .A(n4366), .B(n4358), .Y(n4396) );
INVX2TS U5748 ( .A(n4396), .Y(n4337) );
OAI21X1TS U5749 ( .A0(n4382), .A1(n4377), .B0(n4383), .Y(n4330) );
OAI21X2TS U5750 ( .A0(n4367), .A1(n4358), .B0(n4359), .Y(n4403) );
INVX2TS U5751 ( .A(n4403), .Y(n4336) );
OAI21X1TS U5752 ( .A0(n4406), .A1(n4337), .B0(n4336), .Y(n4338) );
AOI21X1TS U5753 ( .A0(n4409), .A1(n4339), .B0(n4338), .Y(n4343) );
INVX2TS U5754 ( .A(n4395), .Y(n4345) );
NAND2X1TS U5755 ( .A(n4341), .B(n4340), .Y(n4400) );
NAND2X1TS U5756 ( .A(n4345), .B(n4400), .Y(n4342) );
NAND2X1TS U5757 ( .A(n4396), .B(n4345), .Y(n4347) );
INVX2TS U5758 ( .A(n4400), .Y(n4344) );
AOI21X1TS U5759 ( .A0(n4403), .A1(n4345), .B0(n4344), .Y(n4346) );
AOI21X1TS U5760 ( .A0(n4409), .A1(n4349), .B0(n4348), .Y(n4354) );
NOR2X2TS U5761 ( .A(n4350), .B(n4351), .Y(n4399) );
INVX2TS U5762 ( .A(n4399), .Y(n4352) );
NAND2X1TS U5763 ( .A(n4352), .B(n4398), .Y(n4353) );
OAI21X1TS U5764 ( .A0(n4406), .A1(n4366), .B0(n4367), .Y(n4356) );
INVX2TS U5765 ( .A(n4358), .Y(n4360) );
NAND2X1TS U5766 ( .A(n4360), .B(n4359), .Y(n4361) );
XOR2X1TS U5767 ( .A(n4362), .B(n4361), .Y(n4363) );
INVX2TS U5768 ( .A(n4397), .Y(n4365) );
INVX2TS U5769 ( .A(n4406), .Y(n4364) );
INVX2TS U5770 ( .A(n4366), .Y(n4368) );
NOR2X4TS U5771 ( .A(n4775), .B(n4799), .Y(n4783) );
INVX2TS U5772 ( .A(n4378), .Y(n4371) );
INVX2TS U5773 ( .A(n4374), .Y(n4375) );
INVX2TS U5774 ( .A(n4376), .Y(n4379) );
INVX2TS U5775 ( .A(n4382), .Y(n4384) );
NAND2X1TS U5776 ( .A(n4384), .B(n4383), .Y(n4385) );
INVX2TS U5777 ( .A(n4386), .Y(n4392) );
NAND2X6TS U5778 ( .A(n4765), .B(n4764), .Y(n4794) );
AOI21X1TS U5779 ( .A0(n4403), .A1(n4402), .B0(n4401), .Y(n4404) );
OAI21X1TS U5780 ( .A0(n4406), .A1(n4405), .B0(n4404), .Y(n4407) );
NOR2X1TS U5781 ( .A(n4411), .B(n4410), .Y(n4756) );
INVX2TS U5782 ( .A(n4756), .Y(n4412) );
NAND2X1TS U5783 ( .A(n4411), .B(n4410), .Y(n4755) );
NAND2X1TS U5784 ( .A(n4412), .B(n4755), .Y(n4413) );
XOR2X1TS U5785 ( .A(n4757), .B(n4413), .Y(n4414) );
NOR2X4TS U5786 ( .A(n2160), .B(n4446), .Y(n4462) );
NOR2X2TS U5787 ( .A(n4462), .B(n4474), .Y(n4449) );
NOR2X2TS U5788 ( .A(n4424), .B(n4423), .Y(n6231) );
NAND2X1TS U5789 ( .A(n4417), .B(n4416), .Y(n6211) );
NAND2X1TS U5790 ( .A(n4419), .B(n4418), .Y(n6215) );
NAND2X1TS U5791 ( .A(n4422), .B(n4421), .Y(n6221) );
OAI21X2TS U5792 ( .A0(n6233), .A1(n6230), .B0(n6234), .Y(n4427) );
OR2X2TS U5793 ( .A(n4430), .B(n4429), .Y(n6244) );
NAND2X2TS U5794 ( .A(n4430), .B(n4429), .Y(n6240) );
INVX2TS U5795 ( .A(n6240), .Y(n6243) );
NAND2X2TS U5796 ( .A(n4432), .B(n4431), .Y(n6246) );
INVX2TS U5797 ( .A(n6246), .Y(n4433) );
AOI21X2TS U5798 ( .A0(n6247), .A1(n6243), .B0(n4433), .Y(n4434) );
NOR2X2TS U5799 ( .A(n4437), .B(n4436), .Y(n6261) );
NOR2X2TS U5800 ( .A(n6263), .B(n6261), .Y(n4441) );
NAND2X2TS U5801 ( .A(n4439), .B(n4438), .Y(n6264) );
OAI21X2TS U5802 ( .A0(n6263), .A1(n6260), .B0(n6264), .Y(n4440) );
OAI21X2TS U5803 ( .A0(n4462), .A1(n4475), .B0(n4463), .Y(n4448) );
AOI21X4TS U5804 ( .A0(n4472), .A1(n4449), .B0(n4448), .Y(n4450) );
NAND2X2TS U5805 ( .A(n4452), .B(n4451), .Y(n4514) );
NAND2X1TS U5806 ( .A(n4454), .B(n4453), .Y(n4456) );
XNOR2X2TS U5807 ( .A(n4456), .B(n4455), .Y(n4497) );
INVX6TS U5808 ( .A(n4457), .Y(n6272) );
NOR2X1TS U5809 ( .A(n4458), .B(n4474), .Y(n4461) );
AOI21X2TS U5810 ( .A0(n6272), .A1(n4461), .B0(n4460), .Y(n4466) );
INVX2TS U5811 ( .A(n4462), .Y(n4464) );
NAND2X1TS U5812 ( .A(n4464), .B(n4463), .Y(n4465) );
XOR2X4TS U5813 ( .A(n4466), .B(n4465), .Y(n4496) );
INVX2TS U5814 ( .A(n4467), .Y(n4469) );
NAND2X1TS U5815 ( .A(n4469), .B(n4468), .Y(n4471) );
CLKXOR2X2TS U5816 ( .A(n4471), .B(n4470), .Y(n4495) );
NOR2X4TS U5817 ( .A(n6291), .B(n6289), .Y(n4499) );
INVX2TS U5818 ( .A(n4474), .Y(n4476) );
NAND2X1TS U5819 ( .A(n4476), .B(n4475), .Y(n4477) );
NAND2X1TS U5820 ( .A(n4480), .B(n4479), .Y(n4482) );
XOR2X1TS U5821 ( .A(n4482), .B(n4481), .Y(n4493) );
INVX2TS U5822 ( .A(n4483), .Y(n6270) );
INVX2TS U5823 ( .A(n6269), .Y(n4484) );
AOI21X4TS U5824 ( .A0(n6272), .A1(n6270), .B0(n4484), .Y(n4489) );
INVX2TS U5825 ( .A(n4485), .Y(n4487) );
NAND2X1TS U5826 ( .A(n4487), .B(n4486), .Y(n4488) );
XOR2X2TS U5827 ( .A(n4489), .B(n4488), .Y(n6275) );
AFHCONX2TS U5828 ( .A(n4492), .B(n4491), .CI(n4490), .CON(n4481), .S(n6274)
);
NAND2X2TS U5829 ( .A(n6275), .B(n6274), .Y(n6281) );
NAND2X2TS U5830 ( .A(n4494), .B(n4493), .Y(n6279) );
OAI21X4TS U5831 ( .A0(n6278), .A1(n6281), .B0(n6279), .Y(n6284) );
NAND2X4TS U5832 ( .A(n4496), .B(n4495), .Y(n6288) );
AOI21X4TS U5833 ( .A0(n4499), .A1(n6284), .B0(n4498), .Y(n6297) );
INVX2TS U5834 ( .A(n4514), .Y(n4500) );
AOI21X4TS U5835 ( .A0(n4641), .A1(n4501), .B0(n4500), .Y(n4506) );
INVX2TS U5836 ( .A(n4515), .Y(n4504) );
NAND2X1TS U5837 ( .A(n4504), .B(n4513), .Y(n4505) );
XOR2X4TS U5838 ( .A(n4506), .B(n4505), .Y(n4526) );
INVX2TS U5839 ( .A(n4507), .Y(n4509) );
CLKXOR2X2TS U5840 ( .A(n4511), .B(n2158), .Y(n4525) );
OAI21X4TS U5841 ( .A0(n4515), .A1(n4514), .B0(n4513), .Y(n4556) );
AOI21X4TS U5842 ( .A0(n4641), .A1(n4550), .B0(n4556), .Y(n4520) );
INVX2TS U5843 ( .A(n4549), .Y(n4518) );
NAND2X1TS U5844 ( .A(n4522), .B(n4521), .Y(n4523) );
XNOR2X2TS U5845 ( .A(n4524), .B(n4523), .Y(n4527) );
NAND2X4TS U5846 ( .A(n2168), .B(n2794), .Y(n4531) );
NAND2X2TS U5847 ( .A(n4526), .B(n4525), .Y(n6298) );
INVX4TS U5848 ( .A(n6298), .Y(n6301) );
NAND2X2TS U5849 ( .A(n4528), .B(n4527), .Y(n6303) );
AOI21X4TS U5850 ( .A0(n2794), .A1(n6301), .B0(n4529), .Y(n4530) );
OAI21X4TS U5851 ( .A0(n6297), .A1(n4531), .B0(n4530), .Y(n4865) );
INVX2TS U5852 ( .A(n4532), .Y(n4534) );
NOR2X1TS U5853 ( .A(n4537), .B(n4549), .Y(n4540) );
INVX2TS U5854 ( .A(n4556), .Y(n4538) );
NOR2X2TS U5855 ( .A(n4541), .B(n4542), .Y(n4552) );
INVX2TS U5856 ( .A(n4552), .Y(n4543) );
NAND2X1TS U5857 ( .A(n4543), .B(n4551), .Y(n4544) );
INVX2TS U5858 ( .A(n4570), .Y(n4546) );
NAND2X1TS U5859 ( .A(n4546), .B(n4569), .Y(n4548) );
INVX2TS U5860 ( .A(n4547), .Y(n4571) );
XOR2X4TS U5861 ( .A(n4548), .B(n4571), .Y(n4566) );
AOI21X4TS U5862 ( .A0(n4556), .A1(n4555), .B0(n4554), .Y(n4638) );
AOI21X4TS U5863 ( .A0(n4641), .A1(n4558), .B0(n4557), .Y(n4562) );
INVX2TS U5864 ( .A(n4577), .Y(n4587) );
NAND2X1TS U5865 ( .A(n4587), .B(n4588), .Y(n4561) );
CLKXOR2X2TS U5866 ( .A(n4562), .B(n4561), .Y(n4565) );
NOR2X6TS U5867 ( .A(n4566), .B(n4565), .Y(n4866) );
NOR2X4TS U5868 ( .A(n6308), .B(n4866), .Y(n4568) );
NAND2X2TS U5869 ( .A(n4566), .B(n4565), .Y(n4867) );
OAI21X4TS U5870 ( .A0(n4866), .A1(n6309), .B0(n4867), .Y(n4567) );
AOI21X4TS U5871 ( .A0(n4865), .A1(n4568), .B0(n4567), .Y(n4872) );
OAI21X4TS U5872 ( .A0(n4571), .A1(n4570), .B0(n4569), .Y(n4576) );
INVX2TS U5873 ( .A(n4572), .Y(n4574) );
XNOR2X4TS U5874 ( .A(n4576), .B(n4575), .Y(n4618) );
NOR2X1TS U5875 ( .A(n4629), .B(n4577), .Y(n4579) );
AOI21X2TS U5876 ( .A0(n4641), .A1(n4579), .B0(n4578), .Y(n4583) );
NAND2X1TS U5877 ( .A(n4592), .B(n4589), .Y(n4582) );
NOR2X4TS U5878 ( .A(n4618), .B(n4617), .Y(n4873) );
NOR2X1TS U5879 ( .A(n4629), .B(n4628), .Y(n4594) );
INVX2TS U5880 ( .A(n4588), .Y(n4591) );
INVX2TS U5881 ( .A(n4589), .Y(n4590) );
AOI21X2TS U5882 ( .A0(n4641), .A1(n4594), .B0(n4593), .Y(n4599) );
NAND2X1TS U5883 ( .A(n4597), .B(n4596), .Y(n4607) );
NAND2X1TS U5884 ( .A(n4595), .B(n4607), .Y(n4598) );
INVX2TS U5885 ( .A(n4628), .Y(n4605) );
NAND2X2TS U5886 ( .A(n4605), .B(n4595), .Y(n4606) );
NOR2X1TS U5887 ( .A(n4629), .B(n4606), .Y(n4612) );
INVX2TS U5888 ( .A(n4606), .Y(n4610) );
INVX2TS U5889 ( .A(n4635), .Y(n4608) );
INVX2TS U5890 ( .A(n4607), .Y(n4632) );
AOI21X4TS U5891 ( .A0(n4641), .A1(n4612), .B0(n4611), .Y(n4616) );
NAND2X1TS U5892 ( .A(n4614), .B(n4613), .Y(n4630) );
NAND2X1TS U5893 ( .A(n2826), .B(n4630), .Y(n4615) );
OAI21X4TS U5894 ( .A0(n4875), .A1(n6314), .B0(n4876), .Y(n4881) );
NAND2X4TS U5895 ( .A(n4622), .B(n4621), .Y(n4884) );
AOI21X4TS U5896 ( .A0(n4881), .A1(n4883), .B0(n4623), .Y(n4624) );
OAI21X4TS U5897 ( .A0(n4872), .A1(n4625), .B0(n4624), .Y(n4928) );
NAND2X2TS U5898 ( .A(n4194), .B(n4648), .Y(n4627) );
XOR2X4TS U5899 ( .A(n4650), .B(n4627), .Y(n4654) );
NAND2X1TS U5900 ( .A(n4595), .B(n2826), .Y(n4634) );
OR2X2TS U5901 ( .A(n4628), .B(n4634), .Y(n4637) );
INVX2TS U5902 ( .A(n4630), .Y(n4631) );
AOI21X1TS U5903 ( .A0(n4632), .A1(n2826), .B0(n4631), .Y(n4633) );
AOI21X1TS U5904 ( .A0(n4641), .A1(n4640), .B0(n4639), .Y(n4647) );
NAND2X1TS U5905 ( .A(n4643), .B(n4642), .Y(n4644) );
NAND2X1TS U5906 ( .A(n4645), .B(n4644), .Y(n4646) );
XOR2X2TS U5907 ( .A(n4647), .B(n4646), .Y(n4653) );
NOR2X4TS U5908 ( .A(n4654), .B(n4653), .Y(n6186) );
NAND2X4TS U5909 ( .A(n4654), .B(n4653), .Y(n6187) );
OAI21X4TS U5910 ( .A0(n4929), .A1(n6187), .B0(n4930), .Y(n4656) );
AOI21X4TS U5911 ( .A0(n4928), .A1(n4657), .B0(n4656), .Y(n4902) );
XOR2X4TS U5912 ( .A(n4661), .B(n4660), .Y(n4673) );
INVX2TS U5913 ( .A(n4250), .Y(n4663) );
NAND2X1TS U5914 ( .A(n4663), .B(n4662), .Y(n4664) );
CLKXOR2X2TS U5915 ( .A(n4664), .B(n4669), .Y(n4672) );
OA21X4TS U5916 ( .A0(n4674), .A1(n4935), .B0(n4939), .Y(n4675) );
OAI21X4TS U5917 ( .A0(n4902), .A1(n4676), .B0(n4675), .Y(n4923) );
INVX2TS U5918 ( .A(n2396), .Y(n4680) );
INVX2TS U5919 ( .A(n4681), .Y(n4683) );
NAND2X1TS U5920 ( .A(n4683), .B(n4682), .Y(n4685) );
XOR2X1TS U5921 ( .A(n4685), .B(n4684), .Y(n4698) );
NAND2X1TS U5922 ( .A(n2802), .B(n4689), .Y(n4691) );
NAND2X1TS U5923 ( .A(n2821), .B(n4694), .Y(n4695) );
XNOR2X2TS U5924 ( .A(n4696), .B(n4695), .Y(n4700) );
INVX2TS U5925 ( .A(n4707), .Y(n4724) );
OAI21X1TS U5926 ( .A0(n4724), .A1(n4720), .B0(n4721), .Y(n4712) );
INVX2TS U5927 ( .A(n4708), .Y(n4710) );
INVX2TS U5928 ( .A(n4733), .Y(n4714) );
NOR2X4TS U5929 ( .A(n4714), .B(n4713), .Y(n4715) );
INVX2TS U5930 ( .A(n4720), .Y(n4722) );
NAND2X1TS U5931 ( .A(n4722), .B(n4721), .Y(n4723) );
CLKXOR2X2TS U5932 ( .A(n4724), .B(n4723), .Y(n4747) );
INVX2TS U5933 ( .A(n4730), .Y(n4739) );
NAND2X1TS U5934 ( .A(n2822), .B(n4731), .Y(n4732) );
XNOR2X2TS U5935 ( .A(n4739), .B(n4732), .Y(n4743) );
AOI21X4TS U5936 ( .A0(n2573), .A1(n4733), .B0(n2366), .Y(n4737) );
INVX2TS U5937 ( .A(n4713), .Y(n4735) );
AOI21X1TS U5938 ( .A0(n4739), .A1(n2822), .B0(n4738), .Y(n4742) );
NAND2X1TS U5939 ( .A(n2823), .B(n4740), .Y(n4741) );
CLKXOR2X2TS U5940 ( .A(n4742), .B(n4741), .Y(n4745) );
NAND2X4TS U5941 ( .A(n4749), .B(n4748), .Y(n4820) );
NAND2X1TS U5942 ( .A(n4759), .B(n4758), .Y(n4760) );
NAND2X1TS U5943 ( .A(n4761), .B(n4760), .Y(n4762) );
INVX2TS U5944 ( .A(n4765), .Y(n4766) );
XOR2X4TS U5945 ( .A(n4767), .B(n4766), .Y(FPMULT_Sgf_operation_Result[39])
);
CLKBUFX2TS U5946 ( .A(n4813), .Y(n4768) );
INVX2TS U5947 ( .A(n4815), .Y(n4769) );
NAND2X2TS U5948 ( .A(n4782), .B(n4772), .Y(n4773) );
AOI2BB2X4TS U5949 ( .B0(n2324), .B1(n4774), .A0N(n4807), .A1N(n4773), .Y(
n4776) );
XOR2X4TS U5950 ( .A(n4776), .B(n4775), .Y(FPMULT_Sgf_operation_Result[43])
);
INVX2TS U5951 ( .A(n4794), .Y(n4778) );
NOR2X2TS U5952 ( .A(n2460), .B(n4779), .Y(n4780) );
AOI2BB2X4TS U5953 ( .B0(n2324), .B1(n4780), .A0N(n4807), .A1N(n4779), .Y(
n4781) );
XOR2X4TS U5954 ( .A(n4781), .B(n2206), .Y(FPMULT_Sgf_operation_Result[41])
);
INVX2TS U5955 ( .A(n4783), .Y(n4784) );
XOR2X4TS U5956 ( .A(n4788), .B(n4787), .Y(FPMULT_Sgf_operation_Result[45])
);
NOR2X2TS U5957 ( .A(n2460), .B(n4790), .Y(n4791) );
AOI2BB2X4TS U5958 ( .B0(n2324), .B1(n4791), .A0N(n4807), .A1N(n4790), .Y(
n4793) );
XOR2X4TS U5959 ( .A(n4793), .B(n4792), .Y(FPMULT_Sgf_operation_Result[44])
);
XOR2X4TS U5960 ( .A(n4796), .B(n4795), .Y(FPMULT_Sgf_operation_Result[40])
);
NOR2X2TS U5961 ( .A(n2460), .B(n4797), .Y(n4798) );
AOI2BB2X4TS U5962 ( .B0(n2324), .B1(n4798), .A0N(n4807), .A1N(n4797), .Y(
n4800) );
XOR2X4TS U5963 ( .A(n4800), .B(n4799), .Y(FPMULT_Sgf_operation_Result[42])
);
AOI21X4TS U5964 ( .A0(n2324), .A1(n2172), .B0(n4835), .Y(n4806) );
XOR2X4TS U5965 ( .A(n4806), .B(n4805), .Y(FPMULT_Sgf_operation_Result[36])
);
AOI21X4TS U5966 ( .A0(n2411), .A1(n4808), .B0(n2445), .Y(n4810) );
XOR2X4TS U5967 ( .A(n4810), .B(n4809), .Y(FPMULT_Sgf_operation_Result[38])
);
INVX2TS U5968 ( .A(n4958), .Y(n4824) );
INVX2TS U5969 ( .A(n4825), .Y(n4827) );
INVX2TS U5970 ( .A(n2172), .Y(n4834) );
NOR2X2TS U5971 ( .A(n4834), .B(n4804), .Y(n4839) );
OAI21X4TS U5972 ( .A0(n4837), .A1(n4804), .B0(n4836), .Y(n4838) );
AOI21X2TS U5973 ( .A0(n4839), .A1(n2437), .B0(n4838), .Y(n4844) );
INVX2TS U5974 ( .A(n4840), .Y(n4842) );
NOR4X1TS U5975 ( .A(Data_2[7]), .B(Data_2[9]), .C(Data_2[11]), .D(Data_2[6]),
.Y(n6857) );
NOR4X1TS U5976 ( .A(Data_2[2]), .B(Data_2[10]), .C(Data_2[12]), .D(
Data_2[14]), .Y(n6858) );
NOR4X1TS U5977 ( .A(Data_2[15]), .B(Data_2[19]), .C(Data_2[13]), .D(
Data_2[21]), .Y(n4847) );
NOR4X1TS U5978 ( .A(Data_2[4]), .B(Data_2[18]), .C(Data_2[20]), .D(Data_2[1]), .Y(n4846) );
NOR4X1TS U5979 ( .A(Data_2[3]), .B(Data_2[5]), .C(Data_2[22]), .D(Data_2[0]),
.Y(n4845) );
NOR4X1TS U5980 ( .A(Data_2[17]), .B(Data_2[16]), .C(Data_2[8]), .D(n4848),
.Y(n6856) );
CLKBUFX2TS U5981 ( .A(n5022), .Y(n6998) );
INVX2TS U5982 ( .A(n6391), .Y(n7012) );
AOI21X1TS U5983 ( .A0(begin_operation), .A1(n5298), .B0(n6998), .Y(n4851) );
INVX2TS U5984 ( .A(ack_operation), .Y(n4963) );
NAND2X1TS U5985 ( .A(n4855), .B(n4854), .Y(n4856) );
XNOR2X1TS U5986 ( .A(n4857), .B(n4856), .Y(n4858) );
INVX2TS U5987 ( .A(n4859), .Y(n4860) );
NAND2X1TS U5988 ( .A(n4861), .B(n4860), .Y(n4862) );
NOR3X2TS U5989 ( .A(n6730), .B(FPMULT_FS_Module_state_reg[0]), .C(
FPMULT_FS_Module_state_reg[2]), .Y(n5805) );
NAND2X1TS U5990 ( .A(n5805), .B(FPMULT_FSM_add_overflow_flag), .Y(n5808) );
INVX2TS U5991 ( .A(n4865), .Y(n6312) );
INVX2TS U5992 ( .A(n4866), .Y(n4868) );
XNOR2X1TS U5993 ( .A(n4870), .B(n4869), .Y(n4871) );
BUFX3TS U5994 ( .A(n4922), .Y(n6911) );
INVX2TS U5995 ( .A(n4873), .Y(n6315) );
INVX2TS U5996 ( .A(n6314), .Y(n4874) );
AOI21X1TS U5997 ( .A0(n6317), .A1(n6315), .B0(n4874), .Y(n4879) );
INVX2TS U5998 ( .A(n4875), .Y(n4877) );
XOR2X1TS U5999 ( .A(n4879), .B(n4878), .Y(n4880) );
AOI21X1TS U6000 ( .A0(n6317), .A1(n4882), .B0(n4881), .Y(n4886) );
XOR2X1TS U6001 ( .A(n4886), .B(n4885), .Y(n4887) );
BUFX3TS U6002 ( .A(n4922), .Y(n6306) );
INVX2TS U6003 ( .A(n4890), .Y(n4892) );
NAND2X1TS U6004 ( .A(n4892), .B(n4891), .Y(n4893) );
XOR2X1TS U6005 ( .A(n4894), .B(n4893), .Y(n4895) );
INVX2TS U6006 ( .A(n4896), .Y(n4898) );
NAND2X1TS U6007 ( .A(n4898), .B(n4897), .Y(n4899) );
XOR2X1TS U6008 ( .A(n4900), .B(n4899), .Y(n4901) );
INVX2TS U6009 ( .A(n4902), .Y(n4938) );
INVX2TS U6010 ( .A(n5426), .Y(n5787) );
NAND3X1TS U6011 ( .A(FPSENCOS_cordic_FSM_state_reg[1]), .B(
FPSENCOS_cordic_FSM_state_reg[2]), .C(n5787), .Y(n5075) );
INVX2TS U6012 ( .A(n5075), .Y(n5074) );
NOR3X1TS U6013 ( .A(n5426), .B(FPSENCOS_cordic_FSM_state_reg[1]), .C(
FPSENCOS_cordic_FSM_state_reg[2]), .Y(n5021) );
XOR2X1TS U6014 ( .A(n6680), .B(FPSENCOS_d_ff1_shift_region_flag_out[1]), .Y(
n4905) );
XNOR2X1TS U6015 ( .A(n2198), .B(n4905), .Y(n5069) );
AOI22X2TS U6016 ( .A0(FPADDSUB_LZA_output[4]), .A1(n5248), .B0(n5247), .B1(
FPADDSUB_exp_oper_result[4]), .Y(n5007) );
AOI22X4TS U6017 ( .A0(FPADDSUB_LZA_output[3]), .A1(n5248), .B0(n5247), .B1(
FPADDSUB_exp_oper_result[3]), .Y(n5535) );
NOR2X1TS U6018 ( .A(n5007), .B(n5535), .Y(n4918) );
INVX2TS U6019 ( .A(n5007), .Y(n4910) );
NAND2X2TS U6020 ( .A(n5535), .B(n4910), .Y(n5572) );
INVX2TS U6021 ( .A(n5572), .Y(n5892) );
AOI22X1TS U6022 ( .A0(n5569), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[26]), .B0(n5892),
.B1(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[42]), .Y(n4906) );
OAI2BB1X1TS U6023 ( .A0N(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[50]), .A1N(n4918),
.B0(n4906), .Y(n5549) );
NAND2X1TS U6024 ( .A(n5417), .B(n5616), .Y(n4907) );
NOR2X4TS U6025 ( .A(n5535), .B(n4910), .Y(n5568) );
NAND2X2TS U6026 ( .A(n4909), .B(n5568), .Y(n5891) );
NOR2X4TS U6027 ( .A(n5573), .B(n2292), .Y(n5577) );
BUFX3TS U6028 ( .A(n5558), .Y(n5587) );
AOI22X1TS U6029 ( .A0(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[51]), .A1(n2312),
.B0(FPADDSUB_Sgf_normalized_result[25]), .B1(n5587), .Y(n4915) );
NAND2X1TS U6030 ( .A(n4913), .B(n4912), .Y(n5395) );
NAND2X1TS U6031 ( .A(n5395), .B(n7002), .Y(n4914) );
NAND2X2TS U6032 ( .A(n4914), .B(FPADDSUB_add_overflow_flag), .Y(n6349) );
NOR3X4TS U6033 ( .A(n5587), .B(n6349), .C(n5569), .Y(n5908) );
INVX2TS U6034 ( .A(n5908), .Y(n4919) );
AOI22X1TS U6035 ( .A0(n5569), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[27]), .B0(n5892),
.B1(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[43]), .Y(n4917) );
OAI2BB1X1TS U6036 ( .A0N(n4918), .A1N(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[51]), .B0(n4917),
.Y(n5546) );
AOI22X1TS U6037 ( .A0(n2312), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[50]), .B0(
FPADDSUB_Sgf_normalized_result[24]), .B1(n5587), .Y(n4920) );
INVX2TS U6038 ( .A(n4929), .Y(n4931) );
INVX2TS U6039 ( .A(n4944), .Y(n4946) );
OAI21X2TS U6040 ( .A0(n4952), .A1(n4951), .B0(n4950), .Y(n4956) );
NOR2X2TS U6041 ( .A(FPADDSUB_FS_Module_state_reg[2]), .B(
FPADDSUB_FS_Module_state_reg[1]), .Y(n5096) );
NAND2X2TS U6042 ( .A(n5005), .B(n5096), .Y(n1343) );
NOR2X2TS U6043 ( .A(n5616), .B(n5416), .Y(n5784) );
INVX2TS U6044 ( .A(n4962), .Y(n5217) );
OA22X1TS U6045 ( .A0(n5217), .A1(n4963), .B0(n6416), .B1(n5132), .Y(n4966)
);
INVX2TS U6046 ( .A(n1343), .Y(n4965) );
AOI22X1TS U6047 ( .A0(operation[1]), .A1(n2313), .B0(n4962), .B1(
begin_operation), .Y(n4964) );
AOI22X1TS U6048 ( .A0(n5784), .A1(n4966), .B0(n4965), .B1(n4964), .Y(n5394)
);
INVX2TS U6049 ( .A(n5394), .Y(n5423) );
AOI211X1TS U6050 ( .A0(FPADDSUB_FSM_selector_C), .A1(n6737), .B0(n5411),
.C0(n5060), .Y(n5412) );
OAI211XLTS U6051 ( .A0(FPADDSUB_FS_Module_state_reg[1]), .A1(n5616), .B0(
n2212), .C0(n5424), .Y(n4968) );
AOI211X1TS U6052 ( .A0(FPADDSUB_FS_Module_state_reg[2]), .A1(n5423), .B0(
n5412), .C0(n4968), .Y(n5006) );
AOI22X1TS U6053 ( .A0(FPADDSUB_intDY[23]), .A1(FPADDSUB_intDX[23]), .B0(
n6751), .B1(n6762), .Y(n4975) );
AOI22X1TS U6054 ( .A0(n6661), .A1(FPADDSUB_intDY[15]), .B0(n6722), .B1(
FPADDSUB_intDY[13]), .Y(n4969) );
OAI221XLTS U6055 ( .A0(n6661), .A1(FPADDSUB_intDY[15]), .B0(n6722), .B1(
FPADDSUB_intDY[13]), .C0(n4969), .Y(n4974) );
AOI22X1TS U6056 ( .A0(n6755), .A1(FPADDSUB_intDY[10]), .B0(n6757), .B1(
FPADDSUB_intDY[2]), .Y(n4970) );
AOI22X1TS U6057 ( .A0(n6682), .A1(FPADDSUB_intDY[9]), .B0(n6748), .B1(
FPADDSUB_intDY[11]), .Y(n4971) );
OAI221XLTS U6058 ( .A0(n6682), .A1(FPADDSUB_intDY[9]), .B0(n6748), .B1(
FPADDSUB_intDY[11]), .C0(n4971), .Y(n4972) );
NOR4X1TS U6059 ( .A(n4975), .B(n4974), .C(n4973), .D(n4972), .Y(n5003) );
AOI22X1TS U6060 ( .A0(n6684), .A1(FPADDSUB_intDY[7]), .B0(n6747), .B1(
FPADDSUB_intDY[14]), .Y(n4976) );
AOI22X1TS U6061 ( .A0(n6683), .A1(FPADDSUB_intDY[5]), .B0(n6664), .B1(
FPADDSUB_intDY[4]), .Y(n4977) );
OAI221XLTS U6062 ( .A0(n6683), .A1(FPADDSUB_intDY[5]), .B0(n6664), .B1(
FPADDSUB_intDY[4]), .C0(n4977), .Y(n4982) );
AOI22X1TS U6063 ( .A0(n6731), .A1(FPADDSUB_intDY[3]), .B0(n6753), .B1(
FPADDSUB_intDX[26]), .Y(n4978) );
AOI22X1TS U6064 ( .A0(n6756), .A1(FPADDSUB_intDY[1]), .B0(n6679), .B1(
FPADDSUB_intDX[0]), .Y(n4979) );
NOR4X1TS U6065 ( .A(n4983), .B(n4982), .C(n4981), .D(n4980), .Y(n5002) );
AOI22X1TS U6066 ( .A0(n6740), .A1(FPADDSUB_intDX[28]), .B0(n6663), .B1(
FPADDSUB_intDY[6]), .Y(n4984) );
AOI22X1TS U6067 ( .A0(n6742), .A1(FPADDSUB_intDY[18]), .B0(n6760), .B1(
FPADDSUB_intDX[29]), .Y(n4985) );
AOI22X1TS U6068 ( .A0(n6678), .A1(FPADDSUB_intDX[27]), .B0(n6746), .B1(
FPADDSUB_intDY[19]), .Y(n4986) );
AOI22X1TS U6069 ( .A0(n6739), .A1(FPADDSUB_intDX[25]), .B0(n6745), .B1(
FPADDSUB_intDX[24]), .Y(n4987) );
NOR4X1TS U6070 ( .A(n4991), .B(n4990), .C(n4989), .D(n4988), .Y(n5001) );
AOI22X1TS U6071 ( .A0(n6743), .A1(FPADDSUB_intDY[20]), .B0(n6685), .B1(n2352), .Y(n4992) );
OAI221XLTS U6072 ( .A0(n6743), .A1(FPADDSUB_intDY[20]), .B0(n6685), .B1(
FPADDSUB_intDX[30]), .C0(n4992), .Y(n4999) );
AOI22X1TS U6073 ( .A0(n6681), .A1(FPADDSUB_intDY[8]), .B0(n6721), .B1(
FPADDSUB_intDY[21]), .Y(n4993) );
OAI221XLTS U6074 ( .A0(n6681), .A1(FPADDSUB_intDY[8]), .B0(n6721), .B1(
FPADDSUB_intDY[21]), .C0(n4993), .Y(n4998) );
AOI22X1TS U6075 ( .A0(n6744), .A1(FPADDSUB_intDY[17]), .B0(n6761), .B1(
FPADDSUB_intDY[16]), .Y(n4994) );
AOI22X1TS U6076 ( .A0(n6741), .A1(FPADDSUB_intDY[22]), .B0(n6749), .B1(
FPADDSUB_intDX[12]), .Y(n4995) );
NOR4X1TS U6077 ( .A(n4996), .B(n4998), .C(n4997), .D(n4999), .Y(n5000) );
NOR2X1TS U6078 ( .A(n5004), .B(n5707), .Y(n5419) );
NAND2X1TS U6079 ( .A(n5419), .B(n2142), .Y(n5397) );
NAND2X1TS U6080 ( .A(n5006), .B(n5397), .Y(n1838) );
AOI22X1TS U6081 ( .A0(n5569), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[39]), .B0(n5568),
.B1(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[47]), .Y(n5008) );
INVX2TS U6082 ( .A(n5009), .Y(n5534) );
NAND2X1TS U6083 ( .A(n5008), .B(n5534), .Y(n5576) );
AOI21X1TS U6084 ( .A0(n5568), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[46]), .B0(n5009),
.Y(n5580) );
NAND2X1TS U6085 ( .A(n2312), .B(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[38]), .Y(n5011) );
NAND2X1TS U6086 ( .A(n5573), .B(FPADDSUB_Sgf_normalized_result[12]), .Y(
n5010) );
AOI22X1TS U6087 ( .A0(n5569), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[41]), .B0(n5568),
.B1(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[49]), .Y(n5014) );
NAND2X1TS U6088 ( .A(n5014), .B(n5534), .Y(n5559) );
NOR2X2TS U6089 ( .A(n5534), .B(n5537), .Y(n5914) );
OAI2BB1X1TS U6090 ( .A0N(n4909), .A1N(n5559), .B0(n5016), .Y(n1642) );
AOI22X1TS U6091 ( .A0(n5569), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[40]), .B0(n5568),
.B1(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[48]), .Y(n5017) );
NAND2X1TS U6092 ( .A(n5017), .B(n5534), .Y(n5562) );
OAI2BB1X1TS U6093 ( .A0N(n4909), .A1N(n5562), .B0(n5020), .Y(n1643) );
INVX2TS U6094 ( .A(n5021), .Y(n5052) );
CLKBUFX2TS U6095 ( .A(n5052), .Y(n5026) );
BUFX3TS U6096 ( .A(n5027), .Y(n6946) );
CLKBUFX2TS U6097 ( .A(n5052), .Y(n5025) );
BUFX3TS U6098 ( .A(n5027), .Y(n6976) );
CLKBUFX2TS U6099 ( .A(n5052), .Y(n5024) );
BUFX3TS U6100 ( .A(n5027), .Y(n6973) );
CLKBUFX2TS U6101 ( .A(n5052), .Y(n5029) );
BUFX3TS U6102 ( .A(n5027), .Y(n6960) );
BUFX3TS U6103 ( .A(n5029), .Y(n6958) );
BUFX3TS U6104 ( .A(n5029), .Y(n6948) );
BUFX3TS U6105 ( .A(n6981), .Y(n6947) );
BUFX3TS U6106 ( .A(n6914), .Y(n6927) );
BUFX3TS U6107 ( .A(n7006), .Y(n6926) );
BUFX3TS U6108 ( .A(n5023), .Y(n6991) );
BUFX3TS U6109 ( .A(n5022), .Y(n6992) );
BUFX3TS U6110 ( .A(n5022), .Y(n6993) );
BUFX3TS U6111 ( .A(n5022), .Y(n6994) );
BUFX3TS U6112 ( .A(n6998), .Y(n6995) );
BUFX3TS U6113 ( .A(n5023), .Y(n6996) );
BUFX3TS U6114 ( .A(n5022), .Y(n6997) );
BUFX3TS U6115 ( .A(n5023), .Y(n6990) );
BUFX3TS U6116 ( .A(n5029), .Y(n6970) );
BUFX3TS U6117 ( .A(n6981), .Y(n6969) );
BUFX3TS U6118 ( .A(n5026), .Y(n6968) );
BUFX3TS U6119 ( .A(n6982), .Y(n6972) );
BUFX3TS U6120 ( .A(n5027), .Y(n6967) );
BUFX3TS U6121 ( .A(n5029), .Y(n6965) );
BUFX3TS U6122 ( .A(n5022), .Y(n6984) );
BUFX3TS U6123 ( .A(n5023), .Y(n6985) );
BUFX3TS U6124 ( .A(n5022), .Y(n6986) );
BUFX3TS U6125 ( .A(n6981), .Y(n6966) );
BUFX3TS U6126 ( .A(n5023), .Y(n6989) );
BUFX3TS U6127 ( .A(n5028), .Y(n6937) );
BUFX3TS U6128 ( .A(n5024), .Y(n6971) );
BUFX3TS U6129 ( .A(n6982), .Y(n6944) );
BUFX3TS U6130 ( .A(n5023), .Y(n6988) );
BUFX3TS U6131 ( .A(n6914), .Y(n6932) );
BUFX3TS U6132 ( .A(n5030), .Y(n6916) );
BUFX3TS U6133 ( .A(n2288), .Y(n6925) );
BUFX3TS U6134 ( .A(n6924), .Y(n6929) );
BUFX3TS U6135 ( .A(n5023), .Y(n6987) );
BUFX3TS U6136 ( .A(n2226), .Y(n6917) );
BUFX3TS U6137 ( .A(n6924), .Y(n6919) );
BUFX3TS U6138 ( .A(n6914), .Y(n6920) );
BUFX3TS U6139 ( .A(n5029), .Y(n6977) );
BUFX3TS U6140 ( .A(n6982), .Y(n6950) );
BUFX3TS U6141 ( .A(n6981), .Y(n6953) );
BUFX3TS U6142 ( .A(n5025), .Y(n6954) );
BUFX3TS U6143 ( .A(n6981), .Y(n6956) );
BUFX3TS U6144 ( .A(n5052), .Y(n6983) );
BUFX3TS U6145 ( .A(n5027), .Y(n6951) );
BUFX3TS U6146 ( .A(n5024), .Y(n6959) );
BUFX3TS U6147 ( .A(n5028), .Y(n6938) );
BUFX3TS U6148 ( .A(n5026), .Y(n6955) );
BUFX3TS U6149 ( .A(n5028), .Y(n6939) );
BUFX3TS U6150 ( .A(n5025), .Y(n6957) );
BUFX3TS U6151 ( .A(n6942), .Y(n6924) );
BUFX3TS U6152 ( .A(n5026), .Y(n6975) );
BUFX3TS U6153 ( .A(n6982), .Y(n6978) );
BUFX3TS U6154 ( .A(n5024), .Y(n6952) );
BUFX3TS U6155 ( .A(n5024), .Y(n6979) );
BUFX3TS U6156 ( .A(n5025), .Y(n6974) );
BUFX3TS U6157 ( .A(n5025), .Y(n6945) );
BUFX3TS U6158 ( .A(n5026), .Y(n6949) );
BUFX3TS U6159 ( .A(n5029), .Y(n6980) );
BUFX3TS U6160 ( .A(n6928), .Y(n6915) );
BUFX3TS U6161 ( .A(n2226), .Y(n6918) );
BUFX3TS U6162 ( .A(n5028), .Y(n6923) );
BUFX3TS U6163 ( .A(n6982), .Y(n6964) );
BUFX3TS U6164 ( .A(n5024), .Y(n6963) );
BUFX3TS U6165 ( .A(n5025), .Y(n6962) );
BUFX3TS U6166 ( .A(n6942), .Y(n6921) );
BUFX3TS U6167 ( .A(n5028), .Y(n6935) );
BUFX3TS U6168 ( .A(n6942), .Y(n6940) );
BUFX3TS U6169 ( .A(n6942), .Y(n6941) );
CLKBUFX3TS U6170 ( .A(n5028), .Y(n6936) );
CLKBUFX3TS U6171 ( .A(n5028), .Y(n6934) );
CLKBUFX3TS U6172 ( .A(n6913), .Y(n6933) );
BUFX3TS U6173 ( .A(n5026), .Y(n6961) );
BUFX3TS U6174 ( .A(n6928), .Y(n6922) );
AOI211X1TS U6175 ( .A0(operation[1]), .A1(ack_operation), .B0(
FPSENCOS_cordic_FSM_state_reg[1]), .C0(n5243), .Y(n5786) );
AOI211X1TS U6176 ( .A0(n5066), .A1(n6720), .B0(n5786), .C0(n2313), .Y(n5032)
);
OAI211XLTS U6177 ( .A0(FPSENCOS_cordic_FSM_state_reg[1]), .A1(n6410), .B0(
FPSENCOS_cordic_FSM_state_reg[3]), .C0(n6670), .Y(n5031) );
NAND2X1TS U6178 ( .A(n5032), .B(n5031), .Y(n2064) );
INVX2TS U6179 ( .A(n6624), .Y(n6628) );
OAI33X1TS U6180 ( .A0(FPSENCOS_d_ff1_operation_out), .A1(
FPSENCOS_d_ff1_shift_region_flag_out[1]), .A2(n2198), .B0(n6680), .B1(
n6791), .B2(FPSENCOS_d_ff1_shift_region_flag_out[0]), .Y(n5033) );
XOR2X1TS U6181 ( .A(FPSENCOS_data_output2_31_), .B(n5033), .Y(n5034) );
INVX2TS U6182 ( .A(n6558), .Y(n6617) );
AOI22X1TS U6183 ( .A0(n2240), .A1(n6687), .B0(FPSENCOS_d_ff2_X[24]), .B1(
n6597), .Y(n5035) );
XNOR2X1TS U6184 ( .A(n5113), .B(n5035), .Y(n5036) );
NAND2X1TS U6185 ( .A(FPSENCOS_d_ff2_Y[24]), .B(n6597), .Y(n5037) );
AOI22X1TS U6186 ( .A0(n2240), .A1(n6750), .B0(n6599), .B1(n5037), .Y(n5048)
);
NOR2X1TS U6187 ( .A(FPSENCOS_d_ff2_Y[27]), .B(n6605), .Y(n6604) );
OR3X1TS U6188 ( .A(n6605), .B(FPSENCOS_d_ff2_Y[28]), .C(FPSENCOS_d_ff2_Y[27]), .Y(n6607) );
INVX2TS U6189 ( .A(n6616), .Y(n6585) );
BUFX3TS U6190 ( .A(n6558), .Y(n6496) );
NAND2X1TS U6191 ( .A(n6711), .B(n6442), .Y(n6448) );
INVX2TS U6192 ( .A(n6448), .Y(n6433) );
OAI21X1TS U6193 ( .A0(n6711), .A1(n6434), .B0(n5111), .Y(n5041) );
NOR4X2TS U6194 ( .A(n6442), .B(n2240), .C(FPSENCOS_cont_iter_out[0]), .D(
FPSENCOS_cont_iter_out[3]), .Y(n5072) );
NAND2X1TS U6195 ( .A(n6609), .B(n5072), .Y(n6441) );
OAI221XLTS U6196 ( .A0(n6585), .A1(n2795), .B0(n6496), .B1(n5040), .C0(n6441), .Y(n1808) );
OAI21X1TS U6197 ( .A0(n6597), .A1(n6713), .B0(n5483), .Y(n6426) );
OAI21X1TS U6198 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(n6426), .B0(n6609),
.Y(n6421) );
INVX2TS U6199 ( .A(n6558), .Y(n6563) );
OA22X1TS U6200 ( .A0(n5041), .A1(n6421), .B0(n6563), .B1(
FPSENCOS_d_ff3_LUT_out[4]), .Y(n1806) );
NAND2X1TS U6201 ( .A(FPSENCOS_d_ff2_X[24]), .B(n6597), .Y(n5042) );
AOI22X1TS U6202 ( .A0(n2239), .A1(n6687), .B0(n5113), .B1(n5042), .Y(n5046)
);
INVX2TS U6203 ( .A(n6616), .Y(n6584) );
XOR2X1TS U6204 ( .A(n2240), .B(n5044), .Y(n5045) );
OAI2BB2XLTS U6205 ( .B0(n6563), .B1(n6832), .A0N(n6449), .A1N(n5045), .Y(
n1826) );
NAND3BX1TS U6206 ( .AN(n6457), .B(n6665), .C(n6706), .Y(n6462) );
NOR2X1TS U6207 ( .A(FPSENCOS_d_ff2_X[29]), .B(n6462), .Y(n6461) );
XNOR2X1TS U6208 ( .A(n6454), .B(n6461), .Y(n5047) );
NOR2BX1TS U6209 ( .AN(n6435), .B(n5072), .Y(n6450) );
NOR3X2TS U6210 ( .A(FPSENCOS_cont_iter_out[3]), .B(n2228), .C(n6597), .Y(
n5094) );
NOR3BX1TS U6211 ( .AN(n6450), .B(n5094), .C(n6464), .Y(n6453) );
BUFX3TS U6212 ( .A(n6472), .Y(n6445) );
NAND4X1TS U6213 ( .A(n5784), .B(n5066), .C(n6720), .D(n6670), .Y(n6506) );
NOR2X2TS U6214 ( .A(FPSENCOS_cont_var_out[0]), .B(n6677), .Y(n6418) );
BUFX3TS U6215 ( .A(n5051), .Y(n6533) );
INVX2TS U6216 ( .A(result_add_subt[0]), .Y(n6619) );
OAI2BB2XLTS U6217 ( .B0(n6533), .B1(n6619), .A0N(n6526), .A1N(
FPSENCOS_d_ff_Zn[0]), .Y(n1510) );
BUFX3TS U6218 ( .A(n6526), .Y(n6547) );
INVX2TS U6219 ( .A(result_add_subt[1]), .Y(n6551) );
OAI2BB2XLTS U6220 ( .B0(n6547), .B1(n6551), .A0N(n5051), .A1N(
FPSENCOS_d_ff_Zn[1]), .Y(n1514) );
OAI2BB2XLTS U6221 ( .B0(n6526), .B1(n6705), .A0N(n5051), .A1N(
FPSENCOS_d_ff_Zn[30]), .Y(n1630) );
BUFX3TS U6222 ( .A(n5051), .Y(n6529) );
OAI2BB2XLTS U6223 ( .B0(n6529), .B1(n6780), .A0N(n5051), .A1N(
FPSENCOS_d_ff_Zn[31]), .Y(n1700) );
BUFX3TS U6224 ( .A(n5052), .Y(n6981) );
BUFX3TS U6225 ( .A(n5052), .Y(n6982) );
NOR2BX1TS U6226 ( .AN(n5804), .B(FPMULT_FS_Module_state_reg[1]), .Y(n5055)
);
NAND2X1TS U6227 ( .A(n5055), .B(FPMULT_FS_Module_state_reg[0]), .Y(n6201) );
OAI31X1TS U6228 ( .A0(n7012), .A1(n6125), .A2(n6671), .B0(n5056), .Y(n1915)
);
AOI211X1TS U6229 ( .A0(n5056), .A1(FPMULT_FSM_selector_B[0]), .B0(n7012),
.C0(n6125), .Y(n5057) );
INVX2TS U6230 ( .A(n5057), .Y(n1916) );
INVX2TS U6231 ( .A(n6125), .Y(n6179) );
NAND2X1TS U6232 ( .A(FPMULT_Add_result[0]), .B(n6179), .Y(n5058) );
INVX2TS U6233 ( .A(n6911), .Y(n6908) );
AOI31XLTS U6234 ( .A0(FPSENCOS_cordic_FSM_state_reg[1]), .A1(n6660), .A2(
n5243), .B0(n6609), .Y(n5062) );
INVX2TS U6235 ( .A(n6504), .Y(n6503) );
AOI32X1TS U6236 ( .A0(n6503), .A1(operation[1]), .A2(operation[0]), .B0(
n6504), .B1(FPSENCOS_d_ff1_operation_out), .Y(n5065) );
INVX2TS U6237 ( .A(n5065), .Y(n1705) );
NAND2X1TS U6238 ( .A(n5788), .B(n5066), .Y(n5068) );
OAI32X1TS U6239 ( .A0(n5075), .A1(n6410), .A2(n6677), .B0(n5074), .B1(n5073),
.Y(n1703) );
NOR4X1TS U6240 ( .A(FPMULT_P_Sgf[17]), .B(FPMULT_P_Sgf[16]), .C(
FPMULT_P_Sgf[14]), .D(FPMULT_P_Sgf[15]), .Y(n5085) );
NOR4X1TS U6241 ( .A(FPMULT_P_Sgf[20]), .B(FPMULT_P_Sgf[21]), .C(
FPMULT_P_Sgf[18]), .D(FPMULT_P_Sgf[19]), .Y(n5084) );
NOR3XLTS U6242 ( .A(FPMULT_P_Sgf[22]), .B(FPMULT_P_Sgf[1]), .C(
FPMULT_P_Sgf[0]), .Y(n5078) );
AND4X1TS U6243 ( .A(n5079), .B(n5078), .C(n5077), .D(n5076), .Y(n5083) );
CLKXOR2X2TS U6244 ( .A(FPMULT_Op_MX[31]), .B(FPMULT_Op_MY[31]), .Y(n6404) );
INVX2TS U6245 ( .A(n6404), .Y(n5081) );
INVX2TS U6246 ( .A(r_mode[0]), .Y(n5088) );
AOI32X1TS U6247 ( .A0(r_mode[1]), .A1(n5081), .A2(n5088), .B0(n6404), .B1(
n5080), .Y(n5082) );
AOI31X1TS U6248 ( .A0(n5085), .A1(n5084), .A2(n5083), .B0(n5082), .Y(n5092)
);
OAI221XLTS U6249 ( .A0(FPMULT_FS_Module_state_reg[1]), .A1(
FPMULT_FS_Module_state_reg[0]), .B0(n6662), .B1(n6672), .C0(n6659),
.Y(n5086) );
AOI21X1TS U6250 ( .A0(r_mode[1]), .A1(r_mode[0]), .B0(n5090), .Y(n5399) );
NOR2BX1TS U6251 ( .AN(n5399), .B(n5424), .Y(n5413) );
INVX2TS U6252 ( .A(n6403), .Y(n7005) );
INVX2TS U6253 ( .A(n5093), .Y(n2055) );
INVX2TS U6254 ( .A(n6616), .Y(n6449) );
INVX2TS U6255 ( .A(FPSENCOS_d_ff3_LUT_out[21]), .Y(n5162) );
NAND3X1TS U6256 ( .A(FPSENCOS_cont_iter_out[0]), .B(n6609), .C(n6711), .Y(
n6431) );
INVX2TS U6257 ( .A(n6434), .Y(n5095) );
AOI22X1TS U6258 ( .A0(n6433), .A1(n5484), .B0(n5094), .B1(n5483), .Y(n6423)
);
NAND2X1TS U6259 ( .A(n6442), .B(n5094), .Y(n6436) );
OAI21X2TS U6260 ( .A0(n5095), .A1(n6432), .B0(n6609), .Y(n6440) );
XOR2XLTS U6261 ( .A(FPSENCOS_cont_var_out[0]), .B(FPSENCOS_d_ff3_sign_out),
.Y(n5100) );
BUFX3TS U6262 ( .A(n5098), .Y(n5878) );
AOI22X1TS U6263 ( .A0(operation[0]), .A1(n5878), .B0(FPADDSUB_intAS), .B1(
n5877), .Y(n5099) );
NAND2X1TS U6264 ( .A(n6609), .B(n6428), .Y(n6430) );
AOI21X1TS U6265 ( .A0(FPSENCOS_d_ff3_LUT_out[9]), .A1(n6496), .B0(n6446),
.Y(n5101) );
BUFX3TS U6266 ( .A(n5222), .Y(n5237) );
AOI22X1TS U6267 ( .A0(FPSENCOS_d_ff_Xn[30]), .A1(n5105), .B0(
FPSENCOS_sign_inv_out[30]), .B1(n5237), .Y(n5106) );
AOI22X1TS U6268 ( .A0(FPSENCOS_d_ff_Xn[31]), .A1(n5105), .B0(
FPSENCOS_data_output2_31_), .B1(n5237), .Y(n5107) );
NOR2X2TS U6269 ( .A(n6410), .B(n6416), .Y(n5481) );
NAND2X1TS U6270 ( .A(FPSENCOS_cont_var_out[0]), .B(n5481), .Y(n5109) );
INVX2TS U6271 ( .A(n5109), .Y(n5110) );
AOI21X1TS U6272 ( .A0(n5481), .A1(n6677), .B0(FPSENCOS_cont_var_out[0]), .Y(
n5108) );
NAND2X1TS U6273 ( .A(n6449), .B(n6713), .Y(n6429) );
AOI22X1TS U6274 ( .A0(n6585), .A1(n5113), .B0(FPSENCOS_d_ff3_sh_x_out[23]),
.B1(n6464), .Y(n5114) );
AOI22X1TS U6275 ( .A0(n6584), .A1(n6599), .B0(FPSENCOS_d_ff3_sh_y_out[23]),
.B1(n6464), .Y(n5115) );
BUFX3TS U6276 ( .A(n5098), .Y(n5389) );
AOI22X1TS U6277 ( .A0(FPADDSUB_intDY[24]), .A1(n5407), .B0(n5389), .B1(
Data_2[24]), .Y(n5121) );
NOR4X1TS U6278 ( .A(FPSENCOS_sel_mux_2_reg[1]), .B(FPSENCOS_sel_mux_2_reg[0]), .C(n6637), .D(n5132), .Y(n5118) );
NOR4X1TS U6279 ( .A(n6772), .B(FPSENCOS_sel_mux_2_reg[1]), .C(n6637), .D(
n5132), .Y(n5119) );
AOI22X1TS U6280 ( .A0(n2266), .A1(FPSENCOS_d_ff3_sh_y_out[24]), .B0(n5402),
.B1(FPSENCOS_d_ff3_sh_x_out[24]), .Y(n5120) );
INVX2TS U6281 ( .A(FPSENCOS_d_ff3_LUT_out[25]), .Y(n6425) );
AOI22X1TS U6282 ( .A0(FPADDSUB_intDY[25]), .A1(n5407), .B0(n5389), .B1(
Data_2[25]), .Y(n5123) );
AOI22X1TS U6283 ( .A0(n2266), .A1(FPSENCOS_d_ff3_sh_y_out[25]), .B0(n6638),
.B1(FPSENCOS_d_ff3_sh_x_out[25]), .Y(n5122) );
INVX2TS U6284 ( .A(FPSENCOS_d_ff3_LUT_out[23]), .Y(n6427) );
AOI22X1TS U6285 ( .A0(FPADDSUB_intDY[23]), .A1(n5407), .B0(n5389), .B1(
Data_2[23]), .Y(n5125) );
AOI22X1TS U6286 ( .A0(n2266), .A1(FPSENCOS_d_ff3_sh_y_out[23]), .B0(n5402),
.B1(FPSENCOS_d_ff3_sh_x_out[23]), .Y(n5124) );
BUFX3TS U6287 ( .A(n2265), .Y(n5406) );
AOI22X1TS U6288 ( .A0(FPADDSUB_intDX[24]), .A1(n5401), .B0(n5389), .B1(
Data_1[24]), .Y(n5127) );
AOI22X1TS U6289 ( .A0(n5339), .A1(FPSENCOS_d_ff2_Z[24]), .B0(n5210), .B1(
FPSENCOS_d_ff2_Y[24]), .Y(n5126) );
AOI22X1TS U6290 ( .A0(FPADDSUB_intDX[26]), .A1(n5407), .B0(n5389), .B1(
Data_1[26]), .Y(n5129) );
AOI22X1TS U6291 ( .A0(n5339), .A1(FPSENCOS_d_ff2_Z[26]), .B0(n5402), .B1(
FPSENCOS_d_ff2_Y[26]), .Y(n5128) );
AOI22X1TS U6292 ( .A0(FPADDSUB_intDX[25]), .A1(n5407), .B0(n5389), .B1(
Data_1[25]), .Y(n5131) );
AOI22X1TS U6293 ( .A0(n5339), .A1(FPSENCOS_d_ff2_Z[25]), .B0(n5210), .B1(
FPSENCOS_d_ff2_Y[25]), .Y(n5130) );
AOI22X1TS U6294 ( .A0(n5188), .A1(mult_result[24]), .B0(n5183), .B1(
cordic_result[24]), .Y(n5134) );
AOI22X1TS U6295 ( .A0(n5179), .A1(mult_result[13]), .B0(n5218), .B1(
cordic_result[13]), .Y(n5135) );
AOI22X1TS U6296 ( .A0(n5188), .A1(mult_result[25]), .B0(n5183), .B1(
cordic_result[25]), .Y(n5136) );
AOI22X1TS U6297 ( .A0(n5179), .A1(mult_result[15]), .B0(n5218), .B1(
cordic_result[15]), .Y(n5137) );
AOI22X1TS U6298 ( .A0(n5188), .A1(mult_result[22]), .B0(n5183), .B1(
cordic_result[22]), .Y(n5138) );
AOI22X1TS U6299 ( .A0(n5179), .A1(mult_result[14]), .B0(n5218), .B1(
cordic_result[14]), .Y(n5139) );
AOI22X1TS U6300 ( .A0(n5188), .A1(mult_result[23]), .B0(n5183), .B1(
cordic_result[23]), .Y(n5140) );
AOI22X1TS U6301 ( .A0(n5188), .A1(mult_result[26]), .B0(n5183), .B1(
cordic_result[26]), .Y(n5141) );
AOI22X1TS U6302 ( .A0(n5188), .A1(mult_result[27]), .B0(n5183), .B1(
cordic_result[27]), .Y(n5142) );
AOI22X1TS U6303 ( .A0(n5179), .A1(mult_result[21]), .B0(n5183), .B1(
cordic_result[21]), .Y(n5143) );
AOI22X1TS U6304 ( .A0(n5179), .A1(mult_result[20]), .B0(n5183), .B1(
cordic_result[20]), .Y(n5144) );
AOI22X1TS U6305 ( .A0(n5179), .A1(mult_result[12]), .B0(n5218), .B1(
cordic_result[12]), .Y(n5145) );
BUFX3TS U6306 ( .A(n6631), .Y(n5400) );
AOI22X1TS U6307 ( .A0(FPADDSUB_intDX[22]), .A1(n5401), .B0(n5400), .B1(
Data_1[22]), .Y(n5147) );
AOI22X1TS U6308 ( .A0(n5403), .A1(FPSENCOS_d_ff2_Z[22]), .B0(n5402), .B1(
FPSENCOS_d_ff2_Y[22]), .Y(n5146) );
BUFX3TS U6309 ( .A(n2265), .Y(n5352) );
BUFX3TS U6310 ( .A(n6631), .Y(n5325) );
AOI22X1TS U6311 ( .A0(FPADDSUB_intDX[18]), .A1(n5326), .B0(n5325), .B1(
Data_1[18]), .Y(n5149) );
BUFX3TS U6312 ( .A(n5210), .Y(n5167) );
AOI22X1TS U6313 ( .A0(n5403), .A1(FPSENCOS_d_ff2_Z[18]), .B0(n5167), .B1(
FPSENCOS_d_ff2_Y[18]), .Y(n5148) );
BUFX3TS U6314 ( .A(n2265), .Y(n5374) );
AOI22X1TS U6315 ( .A0(FPADDSUB_intDY[18]), .A1(n5326), .B0(n5325), .B1(
Data_2[18]), .Y(n5151) );
AOI22X1TS U6316 ( .A0(FPSENCOS_d_ff3_LUT_out[18]), .A1(n5371), .B0(n5167),
.B1(FPSENCOS_d_ff3_sh_x_out[18]), .Y(n5150) );
BUFX3TS U6317 ( .A(n2265), .Y(n5380) );
AOI22X1TS U6318 ( .A0(FPADDSUB_intDY[9]), .A1(n5326), .B0(n5325), .B1(
Data_2[9]), .Y(n5153) );
AOI22X1TS U6319 ( .A0(n5390), .A1(FPSENCOS_d_ff3_LUT_out[9]), .B0(n5167),
.B1(FPSENCOS_d_ff3_sh_x_out[9]), .Y(n5152) );
AOI22X1TS U6320 ( .A0(FPADDSUB_intDY[15]), .A1(n5326), .B0(n5325), .B1(
Data_2[15]), .Y(n5155) );
AOI22X1TS U6321 ( .A0(FPSENCOS_d_ff3_LUT_out[15]), .A1(n5390), .B0(n5167),
.B1(FPSENCOS_d_ff3_sh_x_out[15]), .Y(n5154) );
AOI22X1TS U6322 ( .A0(FPADDSUB_intDX[15]), .A1(n5326), .B0(n5325), .B1(
Data_1[15]), .Y(n5157) );
AOI22X1TS U6323 ( .A0(n5339), .A1(FPSENCOS_d_ff2_Z[15]), .B0(n5167), .B1(
FPSENCOS_d_ff2_Y[15]), .Y(n5156) );
BUFX3TS U6324 ( .A(n6631), .Y(n5369) );
AOI22X1TS U6325 ( .A0(FPADDSUB_intDY[8]), .A1(n5370), .B0(n5369), .B1(
Data_2[8]), .Y(n5159) );
AOI22X1TS U6326 ( .A0(n5403), .A1(FPSENCOS_d_ff3_LUT_out[8]), .B0(n5167),
.B1(FPSENCOS_d_ff3_sh_x_out[8]), .Y(n5158) );
AOI22X1TS U6327 ( .A0(FPADDSUB_intDY[21]), .A1(n5326), .B0(n5325), .B1(
Data_2[21]), .Y(n5161) );
AOI22X1TS U6328 ( .A0(n2266), .A1(FPSENCOS_d_ff3_sh_y_out[21]), .B0(n5167),
.B1(FPSENCOS_d_ff3_sh_x_out[21]), .Y(n5160) );
AOI22X1TS U6329 ( .A0(FPADDSUB_intDX[1]), .A1(n5370), .B0(n5369), .B1(
Data_1[1]), .Y(n5164) );
AOI22X1TS U6330 ( .A0(n5403), .A1(FPSENCOS_d_ff2_Z[1]), .B0(n5167), .B1(
FPSENCOS_d_ff2_Y[1]), .Y(n5163) );
INVX2TS U6331 ( .A(FPSENCOS_d_ff3_LUT_out[1]), .Y(n6447) );
AOI22X1TS U6332 ( .A0(FPADDSUB_intDY[1]), .A1(n5370), .B0(n5369), .B1(
Data_2[1]), .Y(n5166) );
AOI22X1TS U6333 ( .A0(n2266), .A1(FPSENCOS_d_ff3_sh_y_out[1]), .B0(n5167),
.B1(FPSENCOS_d_ff3_sh_x_out[1]), .Y(n5165) );
AOI22X1TS U6334 ( .A0(FPADDSUB_intDX[8]), .A1(n5370), .B0(n5325), .B1(
Data_1[8]), .Y(n5169) );
AOI22X1TS U6335 ( .A0(n5403), .A1(FPSENCOS_d_ff2_Z[8]), .B0(n5167), .B1(
FPSENCOS_d_ff2_Y[8]), .Y(n5168) );
INVX2TS U6336 ( .A(result_add_subt[8]), .Y(n6538) );
AOI22X1TS U6337 ( .A0(n5174), .A1(mult_result[8]), .B0(n5297), .B1(
cordic_result[8]), .Y(n5170) );
INVX2TS U6338 ( .A(result_add_subt[6]), .Y(n6540) );
AOI22X1TS U6339 ( .A0(n5174), .A1(mult_result[6]), .B0(n5297), .B1(
cordic_result[6]), .Y(n5171) );
INVX2TS U6340 ( .A(result_add_subt[5]), .Y(n6541) );
AOI22X1TS U6341 ( .A0(n5174), .A1(mult_result[5]), .B0(n5297), .B1(
cordic_result[5]), .Y(n5172) );
INVX2TS U6342 ( .A(result_add_subt[4]), .Y(n6544) );
AOI22X1TS U6343 ( .A0(n5174), .A1(mult_result[4]), .B0(n5297), .B1(
cordic_result[4]), .Y(n5173) );
INVX2TS U6344 ( .A(result_add_subt[7]), .Y(n6539) );
AOI22X1TS U6345 ( .A0(n5174), .A1(mult_result[7]), .B0(n5297), .B1(
cordic_result[7]), .Y(n5175) );
AOI22X1TS U6346 ( .A0(n5179), .A1(mult_result[17]), .B0(n5218), .B1(
cordic_result[17]), .Y(n5176) );
AOI22X1TS U6347 ( .A0(n5179), .A1(mult_result[18]), .B0(n5218), .B1(
cordic_result[18]), .Y(n5177) );
AOI22X1TS U6348 ( .A0(n5179), .A1(mult_result[16]), .B0(n5218), .B1(
cordic_result[16]), .Y(n5178) );
AOI22X1TS U6349 ( .A0(n5179), .A1(mult_result[19]), .B0(n5218), .B1(
cordic_result[19]), .Y(n5180) );
AOI22X1TS U6350 ( .A0(n5188), .A1(mult_result[28]), .B0(n5183), .B1(
cordic_result[28]), .Y(n5182) );
AOI22X1TS U6351 ( .A0(n5188), .A1(mult_result[29]), .B0(n5183), .B1(
cordic_result[29]), .Y(n5184) );
INVX2TS U6352 ( .A(n5133), .Y(n5187) );
AOI22X1TS U6353 ( .A0(n5188), .A1(mult_result[30]), .B0(n5187), .B1(
cordic_result[30]), .Y(n5185) );
BUFX3TS U6354 ( .A(n5103), .Y(n5240) );
BUFX3TS U6355 ( .A(n5105), .Y(n5238) );
AOI22X1TS U6356 ( .A0(FPSENCOS_d_ff_Xn[27]), .A1(n5238), .B0(
FPSENCOS_sign_inv_out[27]), .B1(n5237), .Y(n5186) );
AOI22X1TS U6357 ( .A0(n5188), .A1(mult_result[31]), .B0(cordic_result[31]),
.B1(n5187), .Y(n5189) );
AOI22X1TS U6358 ( .A0(FPSENCOS_d_ff_Xn[25]), .A1(n5238), .B0(
FPSENCOS_sign_inv_out[25]), .B1(n5237), .Y(n5191) );
AOI22X1TS U6359 ( .A0(FPSENCOS_d_ff_Xn[26]), .A1(n5238), .B0(
FPSENCOS_sign_inv_out[26]), .B1(n5237), .Y(n5192) );
BUFX3TS U6360 ( .A(n5222), .Y(n5233) );
AOI22X1TS U6361 ( .A0(FPSENCOS_d_ff_Xn[20]), .A1(n5238), .B0(
FPSENCOS_sign_inv_out[20]), .B1(n5233), .Y(n5193) );
BUFX3TS U6362 ( .A(n5103), .Y(n5236) );
BUFX3TS U6363 ( .A(n5105), .Y(n5234) );
BUFX3TS U6364 ( .A(n5222), .Y(n5227) );
AOI22X1TS U6365 ( .A0(FPSENCOS_d_ff_Xn[10]), .A1(n5234), .B0(
FPSENCOS_sign_inv_out[10]), .B1(n5227), .Y(n5194) );
AOI22X1TS U6366 ( .A0(FPSENCOS_d_ff_Xn[13]), .A1(n5234), .B0(
FPSENCOS_sign_inv_out[13]), .B1(n5233), .Y(n5195) );
BUFX3TS U6367 ( .A(n5103), .Y(n5230) );
BUFX3TS U6368 ( .A(n5105), .Y(n5228) );
AOI22X1TS U6369 ( .A0(FPSENCOS_d_ff_Xn[5]), .A1(n5228), .B0(
FPSENCOS_sign_inv_out[5]), .B1(n5227), .Y(n5196) );
INVX2TS U6370 ( .A(FPSENCOS_d_ff_Yn[1]), .Y(n6555) );
AOI22X1TS U6371 ( .A0(FPSENCOS_d_ff_Xn[1]), .A1(n5228), .B0(
FPSENCOS_sign_inv_out[1]), .B1(n5222), .Y(n5197) );
AOI22X1TS U6372 ( .A0(FPSENCOS_d_ff_Xn[2]), .A1(n5228), .B0(
FPSENCOS_sign_inv_out[2]), .B1(n5227), .Y(n5198) );
INVX2TS U6373 ( .A(FPSENCOS_d_ff_Yn[19]), .Y(n6579) );
AOI22X1TS U6374 ( .A0(FPSENCOS_d_ff_Xn[19]), .A1(n5234), .B0(
FPSENCOS_sign_inv_out[19]), .B1(n5233), .Y(n5199) );
AOI22X1TS U6375 ( .A0(FPSENCOS_d_ff_Xn[16]), .A1(n5234), .B0(
FPSENCOS_sign_inv_out[16]), .B1(n5233), .Y(n5200) );
AOI22X1TS U6376 ( .A0(FPSENCOS_d_ff_Xn[12]), .A1(n5234), .B0(
FPSENCOS_sign_inv_out[12]), .B1(n5233), .Y(n5201) );
AOI22X1TS U6377 ( .A0(FPSENCOS_d_ff_Xn[7]), .A1(n5228), .B0(
FPSENCOS_sign_inv_out[7]), .B1(n5227), .Y(n5202) );
AOI22X1TS U6378 ( .A0(FPSENCOS_d_ff_Xn[6]), .A1(n5228), .B0(
FPSENCOS_sign_inv_out[6]), .B1(n5227), .Y(n5203) );
AOI22X1TS U6379 ( .A0(FPSENCOS_d_ff_Xn[29]), .A1(n5238), .B0(
FPSENCOS_sign_inv_out[29]), .B1(n5237), .Y(n5204) );
AOI22X1TS U6380 ( .A0(FPSENCOS_d_ff_Xn[17]), .A1(n5234), .B0(
FPSENCOS_sign_inv_out[17]), .B1(n5233), .Y(n5205) );
AOI22X1TS U6381 ( .A0(FPSENCOS_d_ff_Xn[3]), .A1(n5228), .B0(
FPSENCOS_sign_inv_out[3]), .B1(n5227), .Y(n5206) );
AOI22X1TS U6382 ( .A0(FPSENCOS_d_ff_Xn[14]), .A1(n5234), .B0(
FPSENCOS_sign_inv_out[14]), .B1(n5233), .Y(n5207) );
AOI22X1TS U6383 ( .A0(FPSENCOS_d_ff_Xn[28]), .A1(n5238), .B0(
FPSENCOS_sign_inv_out[28]), .B1(n5237), .Y(n5208) );
AOI22X1TS U6384 ( .A0(FPSENCOS_d_ff_Xn[24]), .A1(n5238), .B0(
FPSENCOS_sign_inv_out[24]), .B1(n5237), .Y(n5209) );
AOI22X1TS U6385 ( .A0(FPADDSUB_intDX[0]), .A1(n5401), .B0(n5400), .B1(
Data_1[0]), .Y(n5212) );
AOI22X1TS U6386 ( .A0(n5339), .A1(FPSENCOS_d_ff2_Z[0]), .B0(n5210), .B1(
FPSENCOS_d_ff2_Y[0]), .Y(n5211) );
AOI22X1TS U6387 ( .A0(n5298), .A1(mult_result[10]), .B0(n5218), .B1(
cordic_result[10]), .Y(n5213) );
INVX2TS U6388 ( .A(result_add_subt[2]), .Y(n6549) );
AOI22X1TS U6389 ( .A0(n5298), .A1(mult_result[2]), .B0(n5297), .B1(
cordic_result[2]), .Y(n5214) );
AOI22X1TS U6390 ( .A0(n5298), .A1(mult_result[1]), .B0(n5297), .B1(
cordic_result[1]), .Y(n5215) );
AOI22X1TS U6391 ( .A0(n5298), .A1(mult_result[0]), .B0(n5297), .B1(
cordic_result[0]), .Y(n5216) );
AOI22X1TS U6392 ( .A0(n5298), .A1(mult_result[11]), .B0(n5218), .B1(
cordic_result[11]), .Y(n5219) );
INVX2TS U6393 ( .A(result_add_subt[3]), .Y(n6545) );
AOI22X1TS U6394 ( .A0(n5298), .A1(mult_result[3]), .B0(n5297), .B1(
cordic_result[3]), .Y(n5220) );
INVX2TS U6395 ( .A(FPSENCOS_d_ff_Yn[18]), .Y(n6578) );
AOI22X1TS U6396 ( .A0(FPSENCOS_d_ff_Xn[18]), .A1(n5234), .B0(
FPSENCOS_sign_inv_out[18]), .B1(n5233), .Y(n5221) );
AOI22X1TS U6397 ( .A0(FPSENCOS_d_ff_Xn[0]), .A1(n5228), .B0(
FPSENCOS_sign_inv_out[0]), .B1(n5222), .Y(n5223) );
AOI22X1TS U6398 ( .A0(FPSENCOS_d_ff_Xn[11]), .A1(n5234), .B0(
FPSENCOS_sign_inv_out[11]), .B1(n5227), .Y(n5224) );
AOI22X1TS U6399 ( .A0(FPSENCOS_d_ff_Xn[8]), .A1(n5228), .B0(
FPSENCOS_sign_inv_out[8]), .B1(n5227), .Y(n5225) );
AOI22X1TS U6400 ( .A0(FPSENCOS_d_ff_Xn[9]), .A1(n5228), .B0(
FPSENCOS_sign_inv_out[9]), .B1(n5227), .Y(n5226) );
AOI22X1TS U6401 ( .A0(FPSENCOS_d_ff_Xn[4]), .A1(n5228), .B0(
FPSENCOS_sign_inv_out[4]), .B1(n5227), .Y(n5229) );
AOI22X1TS U6402 ( .A0(FPSENCOS_d_ff_Xn[22]), .A1(n5238), .B0(
FPSENCOS_sign_inv_out[22]), .B1(n5237), .Y(n5231) );
AOI22X1TS U6403 ( .A0(FPSENCOS_d_ff_Xn[21]), .A1(n5238), .B0(
FPSENCOS_sign_inv_out[21]), .B1(n5233), .Y(n5232) );
AOI22X1TS U6404 ( .A0(FPSENCOS_d_ff_Xn[15]), .A1(n5234), .B0(
FPSENCOS_sign_inv_out[15]), .B1(n5233), .Y(n5235) );
AOI22X1TS U6405 ( .A0(FPSENCOS_d_ff_Xn[23]), .A1(n5238), .B0(
FPSENCOS_sign_inv_out[23]), .B1(n5237), .Y(n5239) );
AOI22X1TS U6406 ( .A0(n5784), .A1(n4962), .B0(n5298), .B1(n5241), .Y(n5242)
);
INVX4TS U6407 ( .A(n5277), .Y(n5508) );
NAND2X2TS U6408 ( .A(n5511), .B(FPADDSUB_FSM_selector_C), .Y(n5503) );
BUFX3TS U6409 ( .A(n6716), .Y(n5509) );
AOI22X1TS U6410 ( .A0(n2293), .A1(FPADDSUB_Add_Subt_result[10]), .B0(
FPADDSUB_DmP[13]), .B1(n5509), .Y(n5245) );
OAI2BB1X1TS U6411 ( .A0N(FPADDSUB_Add_Subt_result[15]), .A1N(n2296), .B0(
n5245), .Y(n5287) );
AOI22X1TS U6412 ( .A0(n5500), .A1(n2350), .B0(FPADDSUB_DmP[17]), .B1(n5509),
.Y(n5246) );
OAI2BB1X1TS U6413 ( .A0N(FPADDSUB_Add_Subt_result[19]), .A1N(n2296), .B0(
n5246), .Y(n5499) );
AOI22X2TS U6414 ( .A0(n5508), .A1(n5287), .B0(n5499), .B1(n5264), .Y(n5595)
);
AOI22X2TS U6415 ( .A0(FPADDSUB_LZA_output[1]), .A1(n5248), .B0(n5247), .B1(
FPADDSUB_exp_oper_result[1]), .Y(n5256) );
INVX2TS U6416 ( .A(n5256), .Y(n5882) );
AOI21X2TS U6417 ( .A0(FPADDSUB_exp_oper_result[0]), .A1(n6715), .B0(n5249),
.Y(n5255) );
NAND2X2TS U6418 ( .A(n5882), .B(n5255), .Y(n5585) );
OAI2BB2XLTS U6419 ( .B0(n5511), .B1(n6764), .A0N(FPADDSUB_DmP[12]), .A1N(
n5472), .Y(n5250) );
AOI21X1TS U6420 ( .A0(n2295), .A1(FPADDSUB_Add_Subt_result[14]), .B0(n5250),
.Y(n5289) );
OAI2BB2XLTS U6421 ( .B0(n5511), .B1(n6766), .A0N(FPADDSUB_DmP[16]), .A1N(
n5472), .Y(n5251) );
AOI21X1TS U6422 ( .A0(n2295), .A1(FPADDSUB_Add_Subt_result[18]), .B0(n5251),
.Y(n5582) );
AOI21X1TS U6423 ( .A0(n2294), .A1(FPADDSUB_Add_Subt_result[13]), .B0(n5253),
.Y(n5291) );
AOI21X1TS U6424 ( .A0(n2294), .A1(FPADDSUB_Add_Subt_result[17]), .B0(n5254),
.Y(n5474) );
AOI22X1TS U6425 ( .A0(n2297), .A1(n5515), .B0(n2289), .B1(n2319), .Y(n5261)
);
AO22X1TS U6426 ( .A0(n5500), .A1(FPADDSUB_Add_Subt_result[9]), .B0(
FPADDSUB_DmP[14]), .B1(n5270), .Y(n5258) );
AOI21X1TS U6427 ( .A0(n2294), .A1(FPADDSUB_Add_Subt_result[16]), .B0(n5258),
.Y(n5293) );
OAI2BB2XLTS U6428 ( .B0(n5511), .B1(n6771), .A0N(FPADDSUB_DmP[18]), .A1N(
n5472), .Y(n5259) );
AOI21X1TS U6429 ( .A0(n2294), .A1(FPADDSUB_Add_Subt_result[20]), .B0(n5259),
.Y(n5502) );
NAND2X1TS U6430 ( .A(n2302), .B(n2320), .Y(n5260) );
INVX4TS U6431 ( .A(n5277), .Y(n5888) );
AOI22X1TS U6432 ( .A0(n2293), .A1(FPADDSUB_Add_Subt_result[18]), .B0(
FPADDSUB_DmP[5]), .B1(n5509), .Y(n5262) );
OAI21X1TS U6433 ( .A0(n6766), .A1(n5503), .B0(n5262), .Y(n5275) );
AOI22X1TS U6434 ( .A0(n5500), .A1(FPADDSUB_Add_Subt_result[14]), .B0(
FPADDSUB_DmP[9]), .B1(n5509), .Y(n5263) );
OAI21X1TS U6435 ( .A0(n6764), .A1(n5503), .B0(n5263), .Y(n5288) );
BUFX3TS U6436 ( .A(n5264), .Y(n6348) );
AOI22X2TS U6437 ( .A0(n5888), .A1(n5275), .B0(n5288), .B1(n6348), .Y(n5523)
);
AOI21X1TS U6438 ( .A0(n2296), .A1(n2350), .B0(n5265), .Y(n5278) );
AO22X1TS U6439 ( .A0(n2293), .A1(FPADDSUB_Add_Subt_result[15]), .B0(
FPADDSUB_DmP[8]), .B1(n5270), .Y(n5266) );
AOI21X1TS U6440 ( .A0(n2296), .A1(FPADDSUB_Add_Subt_result[10]), .B0(n5266),
.Y(n5290) );
BUFX3TS U6441 ( .A(n6348), .Y(n5607) );
AOI22X1TS U6442 ( .A0(n5500), .A1(FPADDSUB_Add_Subt_result[20]), .B0(
FPADDSUB_DmP[3]), .B1(n5509), .Y(n5267) );
OA21XLTS U6443 ( .A0(n5503), .A1(n6771), .B0(n5267), .Y(n5283) );
AOI21X1TS U6444 ( .A0(n2296), .A1(FPADDSUB_Add_Subt_result[9]), .B0(n5268),
.Y(n5292) );
AOI22X1TS U6445 ( .A0(n2297), .A1(n5526), .B0(n2289), .B1(n5524), .Y(n5273)
);
AOI21X1TS U6446 ( .A0(n2296), .A1(FPADDSUB_Add_Subt_result[8]), .B0(n5269),
.Y(n5282) );
AO22X1TS U6447 ( .A0(n2293), .A1(FPADDSUB_Add_Subt_result[13]), .B0(
FPADDSUB_DmP[10]), .B1(n5270), .Y(n5271) );
AOI21X1TS U6448 ( .A0(n2294), .A1(FPADDSUB_Add_Subt_result[12]), .B0(n5271),
.Y(n5294) );
NAND2X1TS U6449 ( .A(n2301), .B(n2321), .Y(n5272) );
AOI22X1TS U6450 ( .A0(n2293), .A1(FPADDSUB_Add_Subt_result[22]), .B0(
FPADDSUB_DmP[1]), .B1(n5509), .Y(n5274) );
OAI21X1TS U6451 ( .A0(n6754), .A1(n5503), .B0(n5274), .Y(n5276) );
AOI22X2TS U6452 ( .A0(n5888), .A1(n5276), .B0(n5275), .B1(n5607), .Y(n5529)
);
AOI22X1TS U6453 ( .A0(n5500), .A1(FPADDSUB_Add_Subt_result[23]), .B0(
FPADDSUB_DmP[0]), .B1(n5509), .Y(n5280) );
INVX2TS U6454 ( .A(n5277), .Y(n6351) );
NAND2X1TS U6455 ( .A(FPADDSUB_Add_Subt_result[2]), .B(n2295), .Y(n5279) );
AOI21X1TS U6456 ( .A0(FPADDSUB_Add_Subt_result[4]), .A1(n2295), .B0(n5281),
.Y(n5493) );
AOI22X1TS U6457 ( .A0(n2299), .A1(n5491), .B0(n2302), .B1(n5525), .Y(n5286)
);
AOI22X1TS U6458 ( .A0(n2296), .A1(n2348), .B0(n2293), .B1(
FPADDSUB_Add_Subt_result[24]), .Y(n5284) );
AOI22X1TS U6459 ( .A0(n5888), .A1(n5284), .B0(n5283), .B1(n5607), .Y(n5492)
);
NAND2X1TS U6460 ( .A(n2290), .B(n5492), .Y(n5285) );
AOI22X2TS U6461 ( .A0(n5508), .A1(n5288), .B0(n5287), .B1(n5264), .Y(n5518)
);
AOI22X1TS U6462 ( .A0(n2299), .A1(n5520), .B0(n2290), .B1(n5519), .Y(n5296)
);
NAND2X1TS U6463 ( .A(n2301), .B(n5514), .Y(n5295) );
INVX2TS U6464 ( .A(result_add_subt[9]), .Y(n6536) );
AOI22X1TS U6465 ( .A0(n5298), .A1(mult_result[9]), .B0(n5297), .B1(
cordic_result[9]), .Y(n5299) );
AOI22X1TS U6466 ( .A0(FPADDSUB_intDX[28]), .A1(n5407), .B0(n5389), .B1(
Data_1[28]), .Y(n5302) );
BUFX3TS U6467 ( .A(n5402), .Y(n5880) );
AOI22X1TS U6468 ( .A0(FPSENCOS_d_ff2_Y[28]), .A1(n5880), .B0(n5371), .B1(
FPSENCOS_d_ff2_Z[28]), .Y(n5301) );
AOI22X1TS U6469 ( .A0(FPADDSUB_intDY[3]), .A1(n5401), .B0(n5400), .B1(
Data_2[3]), .Y(n5304) );
AOI22X1TS U6470 ( .A0(n5403), .A1(FPSENCOS_d_ff3_LUT_out[3]), .B0(n5402),
.B1(FPSENCOS_d_ff3_sh_x_out[3]), .Y(n5303) );
BUFX3TS U6471 ( .A(n2265), .Y(n5386) );
BUFX3TS U6472 ( .A(n6631), .Y(n5381) );
AOI22X1TS U6473 ( .A0(FPADDSUB_intDY[16]), .A1(n5382), .B0(n5381), .B1(
Data_2[16]), .Y(n5306) );
BUFX3TS U6474 ( .A(n5402), .Y(n5377) );
AOI22X1TS U6475 ( .A0(n5117), .A1(FPSENCOS_d_ff3_LUT_out[16]), .B0(n5377),
.B1(FPSENCOS_d_ff3_sh_x_out[16]), .Y(n5305) );
AOI22X1TS U6476 ( .A0(FPADDSUB_intDX[12]), .A1(n5877), .B0(n5878), .B1(
Data_1[12]), .Y(n5308) );
AOI22X1TS U6477 ( .A0(n6632), .A1(FPSENCOS_d_ff2_Z[12]), .B0(n5880), .B1(
FPSENCOS_d_ff2_Y[12]), .Y(n5307) );
AOI22X1TS U6478 ( .A0(FPADDSUB_intDX[21]), .A1(n5326), .B0(n5325), .B1(
Data_1[21]), .Y(n5310) );
AOI22X1TS U6479 ( .A0(n5403), .A1(FPSENCOS_d_ff2_Z[21]), .B0(n5210), .B1(
FPSENCOS_d_ff2_Y[21]), .Y(n5309) );
AOI22X1TS U6480 ( .A0(FPADDSUB_intDX[6]), .A1(n5401), .B0(n5400), .B1(
Data_1[6]), .Y(n5312) );
AOI22X1TS U6481 ( .A0(n5371), .A1(FPSENCOS_d_ff2_Z[6]), .B0(n6638), .B1(
FPSENCOS_d_ff2_Y[6]), .Y(n5311) );
AOI22X1TS U6482 ( .A0(FPADDSUB_intDX[2]), .A1(n5326), .B0(n5325), .B1(
Data_1[2]), .Y(n5314) );
AOI22X1TS U6483 ( .A0(n5403), .A1(FPSENCOS_d_ff2_Z[2]), .B0(n5210), .B1(
FPSENCOS_d_ff2_Y[2]), .Y(n5313) );
AOI22X1TS U6484 ( .A0(FPADDSUB_intDX[19]), .A1(n5401), .B0(n5400), .B1(
Data_1[19]), .Y(n5316) );
AOI22X1TS U6485 ( .A0(n5403), .A1(FPSENCOS_d_ff2_Z[19]), .B0(n5210), .B1(
FPSENCOS_d_ff2_Y[19]), .Y(n5315) );
AOI22X1TS U6486 ( .A0(FPADDSUB_intDX[11]), .A1(n5877), .B0(n5878), .B1(
Data_1[11]), .Y(n5318) );
AOI22X1TS U6487 ( .A0(n6632), .A1(FPSENCOS_d_ff2_Z[11]), .B0(n5880), .B1(
FPSENCOS_d_ff2_Y[11]), .Y(n5317) );
AOI22X1TS U6488 ( .A0(FPADDSUB_intDX[9]), .A1(n5877), .B0(n5878), .B1(
Data_1[9]), .Y(n5320) );
AOI22X1TS U6489 ( .A0(n5390), .A1(FPSENCOS_d_ff2_Z[9]), .B0(n5880), .B1(
FPSENCOS_d_ff2_Y[9]), .Y(n5319) );
AOI22X1TS U6490 ( .A0(FPADDSUB_intDY[22]), .A1(n5401), .B0(n5400), .B1(
Data_2[22]), .Y(n5322) );
AOI22X1TS U6491 ( .A0(n5339), .A1(FPSENCOS_d_ff3_LUT_out[22]), .B0(n5402),
.B1(FPSENCOS_d_ff3_sh_x_out[22]), .Y(n5321) );
AOI22X1TS U6492 ( .A0(FPADDSUB_intDY[19]), .A1(n5326), .B0(n5400), .B1(
Data_2[19]), .Y(n5324) );
AOI22X1TS U6493 ( .A0(n5339), .A1(FPSENCOS_d_ff3_LUT_out[19]), .B0(n5402),
.B1(FPSENCOS_d_ff3_sh_x_out[19]), .Y(n5323) );
AOI22X1TS U6494 ( .A0(FPADDSUB_intDY[2]), .A1(n5326), .B0(n5325), .B1(
Data_2[2]), .Y(n5328) );
AOI22X1TS U6495 ( .A0(n5339), .A1(FPSENCOS_d_ff3_LUT_out[2]), .B0(n5210),
.B1(FPSENCOS_d_ff3_sh_x_out[2]), .Y(n5327) );
AOI22X1TS U6496 ( .A0(FPADDSUB_intDY[6]), .A1(n5401), .B0(n5400), .B1(
Data_2[6]), .Y(n5330) );
AOI22X1TS U6497 ( .A0(n6639), .A1(FPSENCOS_d_ff3_sh_y_out[6]), .B0(n6638),
.B1(FPSENCOS_d_ff3_sh_x_out[6]), .Y(n5329) );
INVX2TS U6498 ( .A(FPSENCOS_d_ff3_LUT_out[0]), .Y(n6451) );
AOI22X1TS U6499 ( .A0(n6639), .A1(FPSENCOS_d_ff3_sh_y_out[0]), .B0(n5880),
.B1(FPSENCOS_d_ff3_sh_x_out[0]), .Y(n5332) );
AOI22X1TS U6500 ( .A0(FPADDSUB_intDY[0]), .A1(n6637), .B0(n5878), .B1(
Data_2[0]), .Y(n5331) );
AOI22X1TS U6501 ( .A0(FPADDSUB_intDX[4]), .A1(n5382), .B0(n5381), .B1(
Data_1[4]), .Y(n5334) );
BUFX3TS U6502 ( .A(n5210), .Y(n5383) );
AOI22X1TS U6503 ( .A0(n5117), .A1(FPSENCOS_d_ff2_Z[4]), .B0(n5383), .B1(
FPSENCOS_d_ff2_Y[4]), .Y(n5333) );
AOI22X1TS U6504 ( .A0(FPADDSUB_intDX[14]), .A1(n5382), .B0(n5381), .B1(
Data_1[14]), .Y(n5336) );
AOI22X1TS U6505 ( .A0(n5371), .A1(FPSENCOS_d_ff2_Z[14]), .B0(n5377), .B1(
FPSENCOS_d_ff2_Y[14]), .Y(n5335) );
AOI22X1TS U6506 ( .A0(FPADDSUB_intDX[10]), .A1(n5382), .B0(n5381), .B1(
Data_1[10]), .Y(n5338) );
AOI22X1TS U6507 ( .A0(n6632), .A1(FPSENCOS_d_ff2_Z[10]), .B0(n5377), .B1(
FPSENCOS_d_ff2_Y[10]), .Y(n5337) );
AOI22X1TS U6508 ( .A0(FPADDSUB_intDX[20]), .A1(n5370), .B0(n5369), .B1(
Data_1[20]), .Y(n5341) );
AOI22X1TS U6509 ( .A0(n5403), .A1(FPSENCOS_d_ff2_Z[20]), .B0(n5383), .B1(
FPSENCOS_d_ff2_Y[20]), .Y(n5340) );
AOI22X1TS U6510 ( .A0(FPADDSUB_intDX[13]), .A1(n5370), .B0(n5369), .B1(
Data_1[13]), .Y(n5343) );
AOI22X1TS U6511 ( .A0(n5117), .A1(FPSENCOS_d_ff2_Z[13]), .B0(n5383), .B1(
FPSENCOS_d_ff2_Y[13]), .Y(n5342) );
AOI22X1TS U6512 ( .A0(FPADDSUB_intDX[17]), .A1(n5382), .B0(n5369), .B1(
Data_1[17]), .Y(n5345) );
AOI22X1TS U6513 ( .A0(n5390), .A1(FPSENCOS_d_ff2_Z[17]), .B0(n5383), .B1(
FPSENCOS_d_ff2_Y[17]), .Y(n5344) );
AOI22X1TS U6514 ( .A0(n2352), .A1(n5407), .B0(n5389), .B1(Data_1[30]), .Y(
n5347) );
AOI22X1TS U6515 ( .A0(FPSENCOS_d_ff2_Y[30]), .A1(n5880), .B0(n5390), .B1(
FPSENCOS_d_ff2_Z[30]), .Y(n5346) );
AOI22X1TS U6516 ( .A0(FPADDSUB_intDY[10]), .A1(n5382), .B0(n5381), .B1(
Data_2[10]), .Y(n5349) );
AOI22X1TS U6517 ( .A0(n6632), .A1(FPSENCOS_d_ff3_LUT_out[10]), .B0(n5377),
.B1(FPSENCOS_d_ff3_sh_x_out[10]), .Y(n5348) );
AOI22X1TS U6518 ( .A0(FPADDSUB_intDX[3]), .A1(n5401), .B0(n5400), .B1(
Data_1[3]), .Y(n5351) );
AOI22X1TS U6519 ( .A0(n5339), .A1(FPSENCOS_d_ff2_Z[3]), .B0(n6638), .B1(
FPSENCOS_d_ff2_Y[3]), .Y(n5350) );
AOI22X1TS U6520 ( .A0(FPADDSUB_intDY[17]), .A1(n5382), .B0(n5381), .B1(
Data_2[17]), .Y(n5354) );
AOI22X1TS U6521 ( .A0(FPSENCOS_d_ff3_LUT_out[17]), .A1(n5390), .B0(n5383),
.B1(FPSENCOS_d_ff3_sh_x_out[17]), .Y(n5353) );
AOI22X1TS U6522 ( .A0(FPADDSUB_intDY[20]), .A1(n5370), .B0(n5369), .B1(
Data_2[20]), .Y(n5356) );
AOI22X1TS U6523 ( .A0(FPSENCOS_d_ff3_LUT_out[20]), .A1(n6632), .B0(n5383),
.B1(FPSENCOS_d_ff3_sh_x_out[20]), .Y(n5355) );
AOI22X1TS U6524 ( .A0(FPADDSUB_intDY[14]), .A1(n5382), .B0(n5381), .B1(
Data_2[14]), .Y(n5358) );
AOI22X1TS U6525 ( .A0(FPSENCOS_d_ff3_LUT_out[14]), .A1(n5371), .B0(n5377),
.B1(FPSENCOS_d_ff3_sh_x_out[14]), .Y(n5357) );
AOI22X1TS U6526 ( .A0(FPADDSUB_intDY[5]), .A1(n5370), .B0(n5369), .B1(
Data_2[5]), .Y(n5360) );
AOI22X1TS U6527 ( .A0(FPSENCOS_d_ff3_LUT_out[5]), .A1(n5390), .B0(n5383),
.B1(FPSENCOS_d_ff3_sh_x_out[5]), .Y(n5359) );
AOI22X1TS U6528 ( .A0(FPADDSUB_intDX[5]), .A1(n5370), .B0(n5369), .B1(
Data_1[5]), .Y(n5362) );
AOI22X1TS U6529 ( .A0(n5390), .A1(FPSENCOS_d_ff2_Z[5]), .B0(n5383), .B1(
FPSENCOS_d_ff2_Y[5]), .Y(n5361) );
AOI22X1TS U6530 ( .A0(FPADDSUB_intDX[7]), .A1(n5877), .B0(n5381), .B1(
Data_1[7]), .Y(n5364) );
AOI22X1TS U6531 ( .A0(n6632), .A1(FPSENCOS_d_ff2_Z[7]), .B0(n5377), .B1(
FPSENCOS_d_ff2_Y[7]), .Y(n5363) );
AOI22X1TS U6532 ( .A0(FPADDSUB_intDX[16]), .A1(n5382), .B0(n5381), .B1(
Data_1[16]), .Y(n5366) );
AOI22X1TS U6533 ( .A0(n5390), .A1(FPSENCOS_d_ff2_Z[16]), .B0(n5377), .B1(
FPSENCOS_d_ff2_Y[16]), .Y(n5365) );
AOI22X1TS U6534 ( .A0(FPADDSUB_intDY[12]), .A1(n5877), .B0(n5878), .B1(
Data_2[12]), .Y(n5368) );
AOI22X1TS U6535 ( .A0(FPSENCOS_d_ff3_LUT_out[12]), .A1(n6632), .B0(n5377),
.B1(FPSENCOS_d_ff3_sh_x_out[12]), .Y(n5367) );
AOI22X1TS U6536 ( .A0(FPADDSUB_intDY[13]), .A1(n5370), .B0(n5369), .B1(
Data_2[13]), .Y(n5373) );
AOI22X1TS U6537 ( .A0(FPSENCOS_d_ff3_LUT_out[13]), .A1(n6632), .B0(n5383),
.B1(FPSENCOS_d_ff3_sh_x_out[13]), .Y(n5372) );
AOI22X1TS U6538 ( .A0(FPADDSUB_intDY[11]), .A1(n5877), .B0(n5878), .B1(
Data_2[11]), .Y(n5376) );
AOI22X1TS U6539 ( .A0(FPSENCOS_d_ff3_LUT_out[11]), .A1(n6632), .B0(n5377),
.B1(FPSENCOS_d_ff3_sh_x_out[11]), .Y(n5375) );
AOI22X1TS U6540 ( .A0(FPADDSUB_intDY[7]), .A1(n5877), .B0(n5878), .B1(
Data_2[7]), .Y(n5379) );
AOI22X1TS U6541 ( .A0(FPSENCOS_d_ff3_LUT_out[7]), .A1(n5390), .B0(n5377),
.B1(FPSENCOS_d_ff3_sh_x_out[7]), .Y(n5378) );
AOI22X1TS U6542 ( .A0(FPADDSUB_intDY[4]), .A1(n5382), .B0(n5381), .B1(
Data_2[4]), .Y(n5385) );
AOI22X1TS U6543 ( .A0(FPSENCOS_d_ff3_LUT_out[4]), .A1(n6632), .B0(n5383),
.B1(FPSENCOS_d_ff3_sh_x_out[4]), .Y(n5384) );
AOI22X1TS U6544 ( .A0(FPADDSUB_intDX[29]), .A1(n5407), .B0(n5389), .B1(
Data_1[29]), .Y(n5388) );
AOI22X1TS U6545 ( .A0(FPSENCOS_d_ff2_Y[29]), .A1(n5880), .B0(n5371), .B1(
FPSENCOS_d_ff2_Z[29]), .Y(n5387) );
AOI22X1TS U6546 ( .A0(FPADDSUB_intDX[27]), .A1(n5407), .B0(n5389), .B1(
Data_1[27]), .Y(n5392) );
AOI22X1TS U6547 ( .A0(FPSENCOS_d_ff2_Y[27]), .A1(n5880), .B0(n5371), .B1(
FPSENCOS_d_ff2_Z[27]), .Y(n5391) );
AOI21X1TS U6548 ( .A0(n5394), .A1(n5393), .B0(n6737), .Y(n5396) );
NOR4X1TS U6549 ( .A(n6534), .B(n5396), .C(n5979), .D(n5421), .Y(n5398) );
AOI22X1TS U6550 ( .A0(FPADDSUB_intDX[23]), .A1(n5401), .B0(n5400), .B1(
Data_1[23]), .Y(n5405) );
BUFX3TS U6551 ( .A(n5402), .Y(n6638) );
AOI22X1TS U6552 ( .A0(n5339), .A1(FPSENCOS_d_ff2_Z[23]), .B0(n6638), .B1(
FPSENCOS_d_ff2_Y[23]), .Y(n5404) );
INVX2TS U6553 ( .A(FPSENCOS_d_ff3_LUT_out[26]), .Y(n6422) );
AOI22X1TS U6554 ( .A0(FPADDSUB_intDY[26]), .A1(n5407), .B0(n6631), .B1(
Data_2[26]), .Y(n5409) );
AOI22X1TS U6555 ( .A0(n6639), .A1(FPSENCOS_d_ff3_sh_y_out[26]), .B0(n6638),
.B1(FPSENCOS_d_ff3_sh_x_out[26]), .Y(n5408) );
AOI21X1TS U6556 ( .A0(n5422), .A1(n5411), .B0(n2196), .Y(n5415) );
OAI22X1TS U6557 ( .A0(n5419), .A1(n5728), .B0(
FPADDSUB_FS_Module_state_reg[1]), .B1(n5418), .Y(n5420) );
NOR3X1TS U6558 ( .A(n6670), .B(n5426), .C(FPSENCOS_cordic_FSM_state_reg[1]),
.Y(n5427) );
INVX2TS U6559 ( .A(n5429), .Y(n1508) );
INVX2TS U6560 ( .A(n5433), .Y(n6494) );
INVX2TS U6561 ( .A(n5430), .Y(n1509) );
INVX2TS U6562 ( .A(n5432), .Y(n1501) );
BUFX3TS U6563 ( .A(n6588), .Y(n5453) );
INVX2TS U6564 ( .A(n5434), .Y(n1496) );
INVX2TS U6565 ( .A(n5435), .Y(n1491) );
INVX2TS U6566 ( .A(n5436), .Y(n1488) );
INVX2TS U6567 ( .A(n5437), .Y(n1494) );
INVX2TS U6568 ( .A(n5438), .Y(n1503) );
INVX2TS U6569 ( .A(n5439), .Y(n1504) );
INVX2TS U6570 ( .A(n5440), .Y(n1507) );
INVX2TS U6571 ( .A(n5441), .Y(n1492) );
INVX2TS U6572 ( .A(n5442), .Y(n1506) );
INVX2TS U6573 ( .A(n5443), .Y(n1489) );
INVX2TS U6574 ( .A(n5444), .Y(n1505) );
INVX2TS U6575 ( .A(n5445), .Y(n1490) );
INVX2TS U6576 ( .A(n5446), .Y(n1502) );
INVX2TS U6577 ( .A(n5447), .Y(n1499) );
INVX2TS U6578 ( .A(n5448), .Y(n1493) );
INVX2TS U6579 ( .A(n5449), .Y(n1498) );
INVX2TS U6580 ( .A(n5450), .Y(n1497) );
INVX2TS U6581 ( .A(n5454), .Y(n1495) );
INVX2TS U6582 ( .A(n5457), .Y(n1500) );
INVX2TS U6583 ( .A(n5459), .Y(n1485) );
INVX2TS U6584 ( .A(n5460), .Y(n1483) );
INVX2TS U6585 ( .A(n5461), .Y(n1486) );
INVX2TS U6586 ( .A(n5462), .Y(n1482) );
INVX2TS U6587 ( .A(n5463), .Y(n1487) );
INVX2TS U6588 ( .A(n5464), .Y(n1484) );
INVX2TS U6589 ( .A(n5465), .Y(n1481) );
INVX2TS U6590 ( .A(n5466), .Y(n1480) );
INVX2TS U6591 ( .A(n5469), .Y(n1479) );
AOI22X1TS U6592 ( .A0(n2314), .A1(n2321), .B0(n2289), .B1(n5526), .Y(n5471)
);
NAND2X1TS U6593 ( .A(n2302), .B(n5519), .Y(n5470) );
AOI22X1TS U6594 ( .A0(n2314), .A1(n2320), .B0(n2289), .B1(n5515), .Y(n5476)
);
AOI21X1TS U6595 ( .A0(n2295), .A1(FPADDSUB_Add_Subt_result[21]), .B0(n5473),
.Y(n5507) );
NAND2X1TS U6596 ( .A(n2302), .B(n5596), .Y(n5475) );
AOI22X1TS U6597 ( .A0(n2315), .A1(n5514), .B0(n2290), .B1(n5520), .Y(n5478)
);
NAND2X1TS U6598 ( .A(n2301), .B(n2319), .Y(n5477) );
AOI22X1TS U6599 ( .A0(n2314), .A1(n5525), .B0(n2289), .B1(n5491), .Y(n5480)
);
NAND2X1TS U6600 ( .A(n2301), .B(n5524), .Y(n5479) );
NAND2X2TS U6601 ( .A(n6418), .B(n5481), .Y(n6415) );
NAND2X1TS U6602 ( .A(n6504), .B(n6415), .Y(n6419) );
INVX2TS U6603 ( .A(n6419), .Y(n5482) );
AOI21X1TS U6604 ( .A0(n6504), .A1(n5484), .B0(n5482), .Y(n6414) );
OAI32X1TS U6605 ( .A0(n6442), .A1(n5484), .A2(n6415), .B0(n6414), .B1(n5483),
.Y(n1832) );
AOI22X1TS U6606 ( .A0(n2297), .A1(n5524), .B0(n2289), .B1(n5525), .Y(n5486)
);
NAND2X1TS U6607 ( .A(n2315), .B(n5526), .Y(n5485) );
AOI22X1TS U6608 ( .A0(n2299), .A1(n2319), .B0(n2289), .B1(n5514), .Y(n5488)
);
NAND2X1TS U6609 ( .A(n2315), .B(n5515), .Y(n5487) );
AOI22X1TS U6610 ( .A0(n2298), .A1(n5519), .B0(n2290), .B1(n2321), .Y(n5490)
);
NAND2X1TS U6611 ( .A(n2315), .B(n5520), .Y(n5489) );
AOI22X1TS U6612 ( .A0(n2298), .A1(n5492), .B0(n2315), .B1(n5491), .Y(n5497)
);
AOI22X1TS U6613 ( .A0(n2295), .A1(FPADDSUB_Add_Subt_result[0]), .B0(
FPADDSUB_Add_Subt_result[25]), .B1(n5500), .Y(n5494) );
AOI22X1TS U6614 ( .A0(n5508), .A1(n5494), .B0(n5493), .B1(n5607), .Y(n5495)
);
NAND2X1TS U6615 ( .A(n2290), .B(n5495), .Y(n5496) );
AOI22X1TS U6616 ( .A0(n2296), .A1(FPADDSUB_Add_Subt_result[23]), .B0(
FPADDSUB_DmP[21]), .B1(n5509), .Y(n5498) );
OAI21X2TS U6617 ( .A0(n6765), .A1(n5511), .B0(n5498), .Y(n6345) );
AOI22X2TS U6618 ( .A0(n5508), .A1(n5499), .B0(n6345), .B1(n5607), .Y(n5603)
);
AOI22X1TS U6619 ( .A0(n5500), .A1(FPADDSUB_Add_Subt_result[1]), .B0(
FPADDSUB_DmP[22]), .B1(n5509), .Y(n5501) );
OAI2BB1X2TS U6620 ( .A0N(FPADDSUB_Add_Subt_result[24]), .A1N(n2295), .B0(
n5501), .Y(n6344) );
AOI2BB2X2TS U6621 ( .B0(n6351), .B1(n5502), .A0N(n6344), .A1N(n6351), .Y(
n5600) );
NOR2X1TS U6622 ( .A(n5503), .B(FPADDSUB_Add_Subt_result[25]), .Y(n5505) );
NOR2X2TS U6623 ( .A(n5505), .B(n5504), .Y(n6347) );
INVX2TS U6624 ( .A(n6347), .Y(n5506) );
AOI22X1TS U6625 ( .A0(n2298), .A1(n5600), .B0(n2314), .B1(n5605), .Y(n5513)
);
AOI22X1TS U6626 ( .A0(n2294), .A1(FPADDSUB_Add_Subt_result[22]), .B0(
FPADDSUB_DmP[20]), .B1(n5509), .Y(n5510) );
OAI21X2TS U6627 ( .A0(n6754), .A1(n5511), .B0(n5510), .Y(n6346) );
AOI22X1TS U6628 ( .A0(n2299), .A1(n5514), .B0(n2314), .B1(n2319), .Y(n5517)
);
NAND2X1TS U6629 ( .A(n2300), .B(n5515), .Y(n5516) );
AOI22X1TS U6630 ( .A0(n2298), .A1(n2321), .B0(n2314), .B1(n5519), .Y(n5522)
);
NAND2X1TS U6631 ( .A(n2301), .B(n5520), .Y(n5521) );
AOI22X1TS U6632 ( .A0(n2299), .A1(n5525), .B0(n2314), .B1(n5524), .Y(n5528)
);
NAND2X1TS U6633 ( .A(n2302), .B(n5526), .Y(n5527) );
AOI22X1TS U6634 ( .A0(n2315), .A1(n6346), .B0(n2302), .B1(n6345), .Y(n5532)
);
AOI22X1TS U6635 ( .A0(n2298), .A1(n5605), .B0(n2290), .B1(n5600), .Y(n5531)
);
NAND2X1TS U6636 ( .A(n5604), .B(n5882), .Y(n5530) );
INVX2TS U6637 ( .A(n4909), .Y(n5581) );
INVX2TS U6638 ( .A(n2316), .Y(n5592) );
NOR2X2TS U6639 ( .A(n5537), .B(n5571), .Y(n5586) );
AOI21X1TS U6640 ( .A0(n5921), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[32]), .B0(n5536),
.Y(n5539) );
AOI22X1TS U6641 ( .A0(n5589), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[48]), .B0(n5922),
.B1(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[40]), .Y(n5538) );
AOI21X1TS U6642 ( .A0(n5921), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[33]), .B0(n5540),
.Y(n5542) );
AOI22X1TS U6643 ( .A0(n5589), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[49]), .B0(n5018),
.B1(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[41]), .Y(n5541) );
AOI21X1TS U6644 ( .A0(n5921), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[31]), .B0(n5543),
.Y(n5545) );
AOI22X1TS U6645 ( .A0(n5589), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[47]), .B0(n5018),
.B1(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[39]), .Y(n5544) );
NAND2X1TS U6646 ( .A(n5546), .B(n5577), .Y(n5548) );
AOI22X1TS U6647 ( .A0(n5922), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[35]), .B0(
FPADDSUB_Sgf_normalized_result[1]), .B1(n5573), .Y(n5547) );
NAND2X1TS U6648 ( .A(n5549), .B(n5577), .Y(n5551) );
AOI22X1TS U6649 ( .A0(n5018), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[34]), .B0(
FPADDSUB_Sgf_normalized_result[0]), .B1(n5573), .Y(n5550) );
AOI21X1TS U6650 ( .A0(n5921), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[30]), .B0(n5552),
.Y(n5554) );
AOI22X1TS U6651 ( .A0(n5589), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[46]), .B0(n5922),
.B1(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[38]), .Y(n5553) );
AOI21X1TS U6652 ( .A0(n5921), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[28]), .B0(n5555),
.Y(n5557) );
AOI22X1TS U6653 ( .A0(n5589), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[44]), .B0(n5018),
.B1(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[36]), .Y(n5556) );
NAND2X1TS U6654 ( .A(n2317), .B(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[36]), .Y(n5561) );
BUFX3TS U6655 ( .A(n5558), .Y(n5920) );
AOI22X1TS U6656 ( .A0(n5577), .A1(n5559), .B0(
FPADDSUB_Sgf_normalized_result[15]), .B1(n5920), .Y(n5560) );
NAND2X1TS U6657 ( .A(n2317), .B(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[37]), .Y(n5564) );
AOI22X1TS U6658 ( .A0(n5577), .A1(n5562), .B0(
FPADDSUB_Sgf_normalized_result[14]), .B1(n5920), .Y(n5563) );
NAND2X1TS U6659 ( .A(n2317), .B(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[42]), .Y(n5567) );
AOI22X1TS U6660 ( .A0(n5569), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[35]), .B0(n5568),
.B1(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[43]), .Y(n5565) );
OAI211X1TS U6661 ( .A0(n6794), .A1(n5572), .B0(n5571), .C0(n5565), .Y(n5919)
);
AOI22X1TS U6662 ( .A0(n5577), .A1(n5919), .B0(
FPADDSUB_Sgf_normalized_result[9]), .B1(n5573), .Y(n5566) );
NAND2X1TS U6663 ( .A(n2317), .B(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[43]), .Y(n5575) );
AOI22X1TS U6664 ( .A0(n5569), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[34]), .B0(n5568),
.B1(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[42]), .Y(n5570) );
OAI211X1TS U6665 ( .A0(n6707), .A1(n5572), .B0(n5571), .C0(n5570), .Y(n5915)
);
AOI22X1TS U6666 ( .A0(n5577), .A1(n5915), .B0(
FPADDSUB_Sgf_normalized_result[8]), .B1(n5573), .Y(n5574) );
NAND2X1TS U6667 ( .A(n2317), .B(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[38]), .Y(n5579) );
AOI22X1TS U6668 ( .A0(n5577), .A1(n5576), .B0(
FPADDSUB_Sgf_normalized_result[13]), .B1(n5587), .Y(n5578) );
AOI2BB2X2TS U6669 ( .B0(n6351), .B1(n5582), .A0N(n6346), .A1N(n6351), .Y(
n5599) );
AOI22X1TS U6670 ( .A0(n2297), .A1(n5599), .B0(n2289), .B1(n5596), .Y(n5584)
);
NAND2X1TS U6671 ( .A(n2301), .B(n5600), .Y(n5583) );
AOI21X1TS U6672 ( .A0(n5921), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[29]), .B0(n5588),
.Y(n5591) );
AOI22X1TS U6673 ( .A0(n5589), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[45]), .B0(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[37]), .B1(n5922),
.Y(n5590) );
AOI22X1TS U6674 ( .A0(n2299), .A1(n2320), .B0(n2314), .B1(n5596), .Y(n5594)
);
NAND2X1TS U6675 ( .A(n2302), .B(n5599), .Y(n5593) );
AOI22X1TS U6676 ( .A0(n2298), .A1(n5596), .B0(n2289), .B1(n2320), .Y(n5598)
);
NAND2X1TS U6677 ( .A(n2315), .B(n5599), .Y(n5597) );
AOI22X1TS U6678 ( .A0(n2315), .A1(n5600), .B0(n2290), .B1(n5599), .Y(n5602)
);
NAND2X1TS U6679 ( .A(n2302), .B(n5605), .Y(n5601) );
NOR2X1TS U6680 ( .A(n1685), .B(n1686), .Y(n6870) );
AOI222X1TS U6681 ( .A0(n6346), .A1(n2299), .B0(n6344), .B1(n2301), .C0(n6345), .C1(n2314), .Y(n5608) );
AOI22X1TS U6682 ( .A0(n2290), .A1(n5605), .B0(n5604), .B1(n5252), .Y(n5606)
);
NOR3X2TS U6683 ( .A(FPADDSUB_Add_Subt_result[17]), .B(
FPADDSUB_Add_Subt_result[16]), .C(FPADDSUB_Add_Subt_result[15]), .Y(
n5939) );
NAND2X1TS U6684 ( .A(n7003), .B(n7004), .Y(n5796) );
INVX2TS U6685 ( .A(n5797), .Y(n5609) );
NOR2X2TS U6686 ( .A(n5796), .B(n5609), .Y(n5941) );
AND2X4TS U6687 ( .A(n5941), .B(n6736), .Y(n6512) );
NOR3X2TS U6688 ( .A(FPADDSUB_Add_Subt_result[11]), .B(
FPADDSUB_Add_Subt_result[10]), .C(n5948), .Y(n5615) );
NAND2X2TS U6689 ( .A(n5610), .B(n5615), .Y(n6513) );
NAND2X2TS U6690 ( .A(n5800), .B(n6771), .Y(n5611) );
NOR2BX1TS U6691 ( .AN(FPADDSUB_Add_Subt_result[4]), .B(n5611), .Y(n5794) );
OAI22X1TS U6692 ( .A0(n5613), .A1(n6513), .B0(n5612), .B1(n5791), .Y(n5944)
);
AOI211X1TS U6693 ( .A0(n5615), .A1(n5614), .B0(n5794), .C0(n5944), .Y(n5619)
);
INVX2TS U6694 ( .A(n6524), .Y(n6522) );
AOI22X1TS U6695 ( .A0(FPADDSUB_intDX[25]), .A1(n6739), .B0(
FPADDSUB_intDX[24]), .B1(n5620), .Y(n5624) );
OAI21X1TS U6696 ( .A0(FPADDSUB_intDX[26]), .A1(n6753), .B0(n5621), .Y(n5680)
);
NOR3X1TS U6697 ( .A(n6724), .B(n5625), .C(FPADDSUB_intDY[28]), .Y(n5626) );
NOR2X1TS U6698 ( .A(n6728), .B(FPADDSUB_intDX[17]), .Y(n5665) );
NOR2X1TS U6699 ( .A(n6714), .B(FPADDSUB_intDX[11]), .Y(n5644) );
AOI21X1TS U6700 ( .A0(FPADDSUB_intDY[10]), .A1(n6755), .B0(n5644), .Y(n5649)
);
OAI2BB1X1TS U6701 ( .A0N(n6683), .A1N(FPADDSUB_intDY[5]), .B0(
FPADDSUB_intDX[4]), .Y(n5630) );
OAI22X1TS U6702 ( .A0(FPADDSUB_intDY[4]), .A1(n5630), .B0(n6683), .B1(
FPADDSUB_intDY[5]), .Y(n5641) );
OAI2BB1X1TS U6703 ( .A0N(n6684), .A1N(FPADDSUB_intDY[7]), .B0(
FPADDSUB_intDX[6]), .Y(n5631) );
OAI22X1TS U6704 ( .A0(FPADDSUB_intDY[6]), .A1(n5631), .B0(n6684), .B1(
FPADDSUB_intDY[7]), .Y(n5640) );
AOI222X1TS U6705 ( .A0(FPADDSUB_intDY[4]), .A1(n6664), .B0(n5637), .B1(n5636), .C0(FPADDSUB_intDY[5]), .C1(n6683), .Y(n5639) );
AOI22X1TS U6706 ( .A0(FPADDSUB_intDY[7]), .A1(n6684), .B0(FPADDSUB_intDY[6]),
.B1(n6663), .Y(n5638) );
OAI32X1TS U6707 ( .A0(n5641), .A1(n5640), .A2(n5639), .B0(n5638), .B1(n5640),
.Y(n5659) );
OA22X1TS U6708 ( .A0(n6712), .A1(FPADDSUB_intDX[14]), .B0(n6666), .B1(
FPADDSUB_intDX[15]), .Y(n5656) );
AOI22X1TS U6709 ( .A0(FPADDSUB_intDX[11]), .A1(n6714), .B0(
FPADDSUB_intDX[10]), .B1(n5645), .Y(n5651) );
AOI21X1TS U6710 ( .A0(n5648), .A1(n5647), .B0(n5658), .Y(n5650) );
OAI2BB2XLTS U6711 ( .B0(FPADDSUB_intDY[14]), .B1(n5652), .A0N(
FPADDSUB_intDX[15]), .A1N(n6666), .Y(n5653) );
AOI211X1TS U6712 ( .A0(n5656), .A1(n5655), .B0(n5654), .C0(n5653), .Y(n5657)
);
OAI31X1TS U6713 ( .A0(n5660), .A1(n5659), .A2(n5658), .B0(n5657), .Y(n5663)
);
OAI21X1TS U6714 ( .A0(FPADDSUB_intDX[18]), .A1(n6729), .B0(n5667), .Y(n5671)
);
OAI2BB2XLTS U6715 ( .B0(FPADDSUB_intDY[20]), .B1(n5664), .A0N(
FPADDSUB_intDX[21]), .A1N(n6726), .Y(n5675) );
AOI22X1TS U6716 ( .A0(FPADDSUB_intDX[17]), .A1(n6728), .B0(
FPADDSUB_intDX[16]), .B1(n5666), .Y(n5669) );
AOI32X1TS U6717 ( .A0(n6729), .A1(n5667), .A2(FPADDSUB_intDX[18]), .B0(
FPADDSUB_intDX[19]), .B1(n6669), .Y(n5668) );
OAI32X1TS U6718 ( .A0(n5671), .A1(n5670), .A2(n5669), .B0(n5668), .B1(n5670),
.Y(n5674) );
AOI211X1TS U6719 ( .A0(n5676), .A1(n5675), .B0(n5674), .C0(n5673), .Y(n5682)
);
NAND4BBX1TS U6720 ( .AN(n5680), .BN(n5679), .C(n5678), .D(n5677), .Y(n5681)
);
AOI32X4TS U6721 ( .A0(n5684), .A1(n5683), .A2(n5682), .B0(n5681), .B1(n5684),
.Y(n5685) );
AOI22X1TS U6722 ( .A0(n5694), .A1(FPADDSUB_intDY[13]), .B0(FPADDSUB_DMP[13]),
.B1(n5765), .Y(n5686) );
AOI22X1TS U6723 ( .A0(n5694), .A1(FPADDSUB_intDY[19]), .B0(FPADDSUB_DMP[19]),
.B1(n5765), .Y(n5687) );
AOI22X1TS U6724 ( .A0(n5694), .A1(FPADDSUB_intDY[18]), .B0(FPADDSUB_DMP[18]),
.B1(n5765), .Y(n5688) );
AOI22X1TS U6725 ( .A0(n5694), .A1(FPADDSUB_intDY[20]), .B0(FPADDSUB_DMP[20]),
.B1(n5765), .Y(n5689) );
AOI22X1TS U6726 ( .A0(n5694), .A1(FPADDSUB_intDX[28]), .B0(FPADDSUB_DmP[28]),
.B1(n5740), .Y(n5690) );
AOI22X1TS U6727 ( .A0(n5694), .A1(FPADDSUB_intDX[26]), .B0(FPADDSUB_DmP[26]),
.B1(n5740), .Y(n5691) );
AOI22X1TS U6728 ( .A0(n5694), .A1(FPADDSUB_intDX[25]), .B0(FPADDSUB_DmP[25]),
.B1(n5737), .Y(n5692) );
AOI22X1TS U6729 ( .A0(n5694), .A1(FPADDSUB_intDX[24]), .B0(FPADDSUB_DmP[24]),
.B1(n5771), .Y(n5693) );
AOI22X1TS U6730 ( .A0(n5743), .A1(FPADDSUB_intDY[14]), .B0(FPADDSUB_DMP[14]),
.B1(n5740), .Y(n5695) );
AOI22X1TS U6731 ( .A0(n5743), .A1(FPADDSUB_intDY[17]), .B0(FPADDSUB_DMP[17]),
.B1(n5765), .Y(n5696) );
AOI22X1TS U6732 ( .A0(n5694), .A1(FPADDSUB_intDY[21]), .B0(FPADDSUB_DMP[21]),
.B1(n5754), .Y(n5697) );
AOI22X1TS U6733 ( .A0(n5726), .A1(FPADDSUB_intDY[11]), .B0(FPADDSUB_DMP[11]),
.B1(n5754), .Y(n5698) );
AOI22X1TS U6734 ( .A0(n5743), .A1(FPADDSUB_intDY[15]), .B0(FPADDSUB_DMP[15]),
.B1(n5754), .Y(n5699) );
AOI22X1TS U6735 ( .A0(n5743), .A1(FPADDSUB_intDY[16]), .B0(FPADDSUB_DMP[16]),
.B1(n5740), .Y(n5700) );
AOI22X1TS U6736 ( .A0(n5743), .A1(n2352), .B0(FPADDSUB_DmP[30]), .B1(n5754),
.Y(n5701) );
AOI22X1TS U6737 ( .A0(n5743), .A1(FPADDSUB_intDX[27]), .B0(FPADDSUB_DmP[27]),
.B1(n5740), .Y(n5702) );
AOI22X1TS U6738 ( .A0(FPADDSUB_DmP[12]), .A1(n5771), .B0(FPADDSUB_intDX[12]),
.B1(n5743), .Y(n5703) );
AOI22X1TS U6739 ( .A0(FPADDSUB_DmP[0]), .A1(n5775), .B0(FPADDSUB_intDX[0]),
.B1(n5694), .Y(n5704) );
NAND2X1TS U6740 ( .A(n5705), .B(FPADDSUB_intDX[31]), .Y(n5710) );
AOI22X1TS U6741 ( .A0(n5726), .A1(FPADDSUB_intDY[22]), .B0(FPADDSUB_DMP[22]),
.B1(n5765), .Y(n5711) );
AOI22X1TS U6742 ( .A0(n5726), .A1(FPADDSUB_intDX[29]), .B0(FPADDSUB_DmP[29]),
.B1(n5740), .Y(n5712) );
OR4X2TS U6743 ( .A(n5950), .B(n5933), .C(n5932), .D(n7002), .Y(n5714) );
NOR4X1TS U6744 ( .A(n5929), .B(n5930), .C(n5931), .D(n5714), .Y(n5716) );
NOR4BX1TS U6745 ( .AN(n5716), .B(n5715), .C(n5927), .D(n5928), .Y(n7001) );
AOI22X1TS U6746 ( .A0(n5729), .A1(FPADDSUB_intDX[7]), .B0(FPADDSUB_DMP[7]),
.B1(n5728), .Y(n5717) );
AOI22X1TS U6747 ( .A0(n5729), .A1(FPADDSUB_intDX[4]), .B0(FPADDSUB_DMP[4]),
.B1(n5728), .Y(n5718) );
AOI22X1TS U6748 ( .A0(n5729), .A1(FPADDSUB_intDX[10]), .B0(FPADDSUB_DMP[10]),
.B1(n5728), .Y(n5719) );
AOI22X1TS U6749 ( .A0(n5729), .A1(FPADDSUB_intDX[2]), .B0(FPADDSUB_DMP[2]),
.B1(n5775), .Y(n5720) );
AOI22X1TS U6750 ( .A0(n5729), .A1(FPADDSUB_intDX[6]), .B0(FPADDSUB_DMP[6]),
.B1(n5728), .Y(n5721) );
AOI22X1TS U6751 ( .A0(n5729), .A1(FPADDSUB_intDX[5]), .B0(FPADDSUB_DMP[5]),
.B1(n5728), .Y(n5722) );
AOI22X1TS U6752 ( .A0(n5729), .A1(FPADDSUB_intDX[9]), .B0(FPADDSUB_DMP[9]),
.B1(n5728), .Y(n5723) );
AOI22X1TS U6753 ( .A0(n5729), .A1(FPADDSUB_intDX[1]), .B0(FPADDSUB_DMP[1]),
.B1(n5728), .Y(n5724) );
AOI22X1TS U6754 ( .A0(n5729), .A1(FPADDSUB_intDX[8]), .B0(FPADDSUB_DMP[8]),
.B1(n5728), .Y(n5725) );
AOI22X1TS U6755 ( .A0(n5755), .A1(FPADDSUB_intDX[0]), .B0(FPADDSUB_DMP[0]),
.B1(n5737), .Y(n5727) );
AOI22X1TS U6756 ( .A0(n5729), .A1(FPADDSUB_intDX[3]), .B0(FPADDSUB_DMP[3]),
.B1(n5728), .Y(n5730) );
AOI22X1TS U6757 ( .A0(n5755), .A1(FPADDSUB_intDX[25]), .B0(FPADDSUB_DMP[25]),
.B1(n5771), .Y(n5731) );
AOI22X1TS U6758 ( .A0(n5755), .A1(FPADDSUB_intDX[23]), .B0(FPADDSUB_DMP[23]),
.B1(n5775), .Y(n5732) );
AOI22X1TS U6759 ( .A0(n5770), .A1(FPADDSUB_intDX[12]), .B0(FPADDSUB_DMP[12]),
.B1(n5740), .Y(n5733) );
AOI22X1TS U6760 ( .A0(n5755), .A1(FPADDSUB_intDX[29]), .B0(FPADDSUB_DMP[29]),
.B1(n5740), .Y(n5734) );
AOI22X1TS U6761 ( .A0(n5755), .A1(FPADDSUB_intDY[23]), .B0(FPADDSUB_DmP[23]),
.B1(n5775), .Y(n5735) );
AOI22X1TS U6762 ( .A0(n5755), .A1(FPADDSUB_intDX[26]), .B0(FPADDSUB_DMP[26]),
.B1(n5737), .Y(n5736) );
AOI22X1TS U6763 ( .A0(n5755), .A1(FPADDSUB_intDX[24]), .B0(FPADDSUB_DMP[24]),
.B1(n5765), .Y(n5738) );
AOI22X1TS U6764 ( .A0(n5755), .A1(FPADDSUB_intDX[28]), .B0(FPADDSUB_DMP[28]),
.B1(n5740), .Y(n5739) );
AOI22X1TS U6765 ( .A0(n5755), .A1(FPADDSUB_intDX[27]), .B0(FPADDSUB_DMP[27]),
.B1(n5740), .Y(n5741) );
AOI22X1TS U6766 ( .A0(FPADDSUB_DmP[1]), .A1(n5765), .B0(FPADDSUB_intDY[1]),
.B1(n5770), .Y(n5744) );
INVX2TS U6767 ( .A(n5749), .Y(n5747) );
AOI22X1TS U6768 ( .A0(FPADDSUB_DmP[11]), .A1(n5737), .B0(FPADDSUB_intDY[11]),
.B1(n5747), .Y(n5745) );
AOI22X1TS U6769 ( .A0(FPADDSUB_DmP[9]), .A1(n5775), .B0(FPADDSUB_intDY[9]),
.B1(n5747), .Y(n5748) );
AOI22X1TS U6770 ( .A0(FPADDSUB_DmP[7]), .A1(n5771), .B0(FPADDSUB_intDY[7]),
.B1(n5774), .Y(n5750) );
AOI22X1TS U6771 ( .A0(FPADDSUB_DmP[3]), .A1(n5771), .B0(FPADDSUB_intDY[3]),
.B1(n5774), .Y(n5751) );
AOI22X1TS U6772 ( .A0(FPADDSUB_DmP[16]), .A1(n5775), .B0(FPADDSUB_intDY[16]),
.B1(n5774), .Y(n5752) );
AOI22X1TS U6773 ( .A0(FPADDSUB_DmP[8]), .A1(n5737), .B0(FPADDSUB_intDY[8]),
.B1(n5770), .Y(n5753) );
AOI22X1TS U6774 ( .A0(n5755), .A1(n2352), .B0(FPADDSUB_DMP[30]), .B1(n5754),
.Y(n5756) );
AOI22X1TS U6775 ( .A0(FPADDSUB_DmP[5]), .A1(n5737), .B0(FPADDSUB_intDY[5]),
.B1(n5770), .Y(n5757) );
AOI22X1TS U6776 ( .A0(FPADDSUB_DmP[2]), .A1(n5771), .B0(FPADDSUB_intDY[2]),
.B1(n5770), .Y(n5758) );
AOI22X1TS U6777 ( .A0(FPADDSUB_DmP[4]), .A1(n5771), .B0(FPADDSUB_intDY[4]),
.B1(n5774), .Y(n5759) );
AOI22X1TS U6778 ( .A0(FPADDSUB_DmP[13]), .A1(n5771), .B0(FPADDSUB_intDY[13]),
.B1(n5770), .Y(n5760) );
AOI22X1TS U6779 ( .A0(FPADDSUB_DmP[19]), .A1(n5771), .B0(FPADDSUB_intDY[19]),
.B1(n5774), .Y(n5761) );
AOI22X1TS U6780 ( .A0(FPADDSUB_DmP[6]), .A1(n5775), .B0(FPADDSUB_intDY[6]),
.B1(n5774), .Y(n5762) );
AOI22X1TS U6781 ( .A0(FPADDSUB_DmP[14]), .A1(n5737), .B0(FPADDSUB_intDY[14]),
.B1(n5774), .Y(n5763) );
AOI22X1TS U6782 ( .A0(FPADDSUB_DmP[21]), .A1(n5737), .B0(FPADDSUB_intDY[21]),
.B1(n5770), .Y(n5764) );
AOI22X1TS U6783 ( .A0(FPADDSUB_DmP[10]), .A1(n5737), .B0(FPADDSUB_intDY[10]),
.B1(n5774), .Y(n5766) );
AOI22X1TS U6784 ( .A0(FPADDSUB_DmP[17]), .A1(n5771), .B0(FPADDSUB_intDY[17]),
.B1(n5774), .Y(n5767) );
AOI22X1TS U6785 ( .A0(FPADDSUB_DmP[15]), .A1(n5775), .B0(FPADDSUB_intDY[15]),
.B1(n5770), .Y(n5768) );
AOI22X1TS U6786 ( .A0(FPADDSUB_DmP[18]), .A1(n5775), .B0(FPADDSUB_intDY[18]),
.B1(n5770), .Y(n5769) );
AOI22X1TS U6787 ( .A0(FPADDSUB_DmP[20]), .A1(n5737), .B0(FPADDSUB_intDY[20]),
.B1(n5770), .Y(n5772) );
AOI22X1TS U6788 ( .A0(FPADDSUB_DmP[22]), .A1(n5775), .B0(FPADDSUB_intDY[22]),
.B1(n5774), .Y(n5776) );
OAI31X1TS U6789 ( .A0(n6667), .A1(n6418), .A2(n6410), .B0(n6720), .Y(n5779)
);
INVX2TS U6790 ( .A(n5779), .Y(n5783) );
OAI32X1TS U6791 ( .A0(n5787), .A1(n5781), .A2(n5780), .B0(n6720), .B1(n5787),
.Y(n5782) );
AOI211X1TS U6792 ( .A0(operation[1]), .A1(begin_operation), .B0(
FPSENCOS_cordic_FSM_state_reg[2]), .C0(
FPSENCOS_cordic_FSM_state_reg[3]), .Y(n5785) );
AOI211XLTS U6793 ( .A0(n5788), .A1(n6660), .B0(n5787), .C0(n5786), .Y(n5789)
);
AOI211X1TS U6794 ( .A0(n6765), .A1(n5792), .B0(FPADDSUB_Add_Subt_result[3]),
.C0(n5791), .Y(n5793) );
AOI211X1TS U6795 ( .A0(n6512), .A1(FPADDSUB_Add_Subt_result[18]), .B0(n5794),
.C0(n5793), .Y(n6521) );
OA21XLTS U6796 ( .A0(FPADDSUB_Add_Subt_result[11]), .A1(
FPADDSUB_Add_Subt_result[13]), .B0(n5795), .Y(n5935) );
AOI21X1TS U6797 ( .A0(n5797), .A1(n6736), .B0(n5796), .Y(n5798) );
AOI22X1TS U6798 ( .A0(FPADDSUB_Add_Subt_result[5]), .A1(n5800), .B0(
FPADDSUB_Add_Subt_result[3]), .B1(n5799), .Y(n5801) );
NOR2X1TS U6799 ( .A(n5805), .B(n5804), .Y(n5806) );
NOR2X2TS U6800 ( .A(n5806), .B(n6662), .Y(n6094) );
INVX2TS U6801 ( .A(n5820), .Y(n6182) );
INVX2TS U6802 ( .A(n6094), .Y(n6110) );
BUFX3TS U6803 ( .A(n6110), .Y(n6181) );
AOI22X1TS U6804 ( .A0(n6182), .A1(FPMULT_Add_result[11]), .B0(
FPMULT_Sgf_normalized_result[10]), .B1(n6181), .Y(n5811) );
OAI2BB1X1TS U6805 ( .A0N(n2346), .A1N(n1952), .B0(n5811), .Y(n5812) );
AOI21X1TS U6806 ( .A0(n2309), .A1(FPMULT_Add_result[10]), .B0(n5812), .Y(
n5813) );
OAI2BB1X1TS U6807 ( .A0N(n2306), .A1N(n1951), .B0(n5813), .Y(n1892) );
INVX2TS U6808 ( .A(n5820), .Y(n6175) );
AOI22X1TS U6809 ( .A0(n6175), .A1(FPMULT_Add_result[9]), .B0(
FPMULT_Sgf_normalized_result[8]), .B1(n6181), .Y(n5814) );
OAI2BB1X1TS U6810 ( .A0N(n2344), .A1N(n1950), .B0(n5814), .Y(n5815) );
AOI21X1TS U6811 ( .A0(n2309), .A1(FPMULT_Add_result[8]), .B0(n5815), .Y(
n5816) );
OAI2BB1X1TS U6812 ( .A0N(n2306), .A1N(n1949), .B0(n5816), .Y(n1890) );
BUFX3TS U6813 ( .A(n6110), .Y(n6192) );
AOI22X1TS U6814 ( .A0(n6175), .A1(FPMULT_Add_result[15]), .B0(
FPMULT_Sgf_normalized_result[14]), .B1(n6192), .Y(n5817) );
OAI2BB1X1TS U6815 ( .A0N(n2345), .A1N(n1956), .B0(n5817), .Y(n5818) );
AOI21X1TS U6816 ( .A0(n2310), .A1(FPMULT_Add_result[14]), .B0(n5818), .Y(
n5819) );
OAI2BB1X1TS U6817 ( .A0N(n2306), .A1N(n1955), .B0(n5819), .Y(n1896) );
INVX2TS U6818 ( .A(n5820), .Y(n6193) );
AOI22X1TS U6819 ( .A0(n6193), .A1(FPMULT_Add_result[16]), .B0(
FPMULT_Sgf_normalized_result[15]), .B1(n6192), .Y(n5821) );
OAI2BB1X1TS U6820 ( .A0N(n2346), .A1N(n1957), .B0(n5821), .Y(n5822) );
AOI21X1TS U6821 ( .A0(n2311), .A1(FPMULT_Add_result[15]), .B0(n5822), .Y(
n5823) );
OAI2BB1X1TS U6822 ( .A0N(n2306), .A1N(n1956), .B0(n5823), .Y(n1897) );
AOI22X1TS U6823 ( .A0(n6193), .A1(FPMULT_Add_result[10]), .B0(
FPMULT_Sgf_normalized_result[9]), .B1(n6181), .Y(n5824) );
OAI2BB1X1TS U6824 ( .A0N(n2345), .A1N(n1951), .B0(n5824), .Y(n5825) );
AOI21X1TS U6825 ( .A0(n2309), .A1(FPMULT_Add_result[9]), .B0(n5825), .Y(
n5826) );
OAI2BB1X1TS U6826 ( .A0N(n2306), .A1N(n1950), .B0(n5826), .Y(n1891) );
AOI22X1TS U6827 ( .A0(n6175), .A1(FPMULT_Add_result[12]), .B0(
FPMULT_Sgf_normalized_result[11]), .B1(n6192), .Y(n5827) );
OAI2BB1X1TS U6828 ( .A0N(n2344), .A1N(n1953), .B0(n5827), .Y(n5828) );
AOI21X1TS U6829 ( .A0(n2310), .A1(FPMULT_Add_result[11]), .B0(n5828), .Y(
n5829) );
OAI2BB1X1TS U6830 ( .A0N(n2307), .A1N(n1952), .B0(n5829), .Y(n1893) );
AOI22X1TS U6831 ( .A0(n6182), .A1(FPMULT_Add_result[17]), .B0(
FPMULT_Sgf_normalized_result[16]), .B1(n6192), .Y(n5830) );
OAI2BB1X1TS U6832 ( .A0N(n2345), .A1N(n1958), .B0(n5830), .Y(n5831) );
AOI21X1TS U6833 ( .A0(n2311), .A1(FPMULT_Add_result[16]), .B0(n5831), .Y(
n5832) );
OAI2BB1X1TS U6834 ( .A0N(n2308), .A1N(n1957), .B0(n5832), .Y(n1898) );
AOI22X1TS U6835 ( .A0(n6193), .A1(FPMULT_Add_result[19]), .B0(
FPMULT_Sgf_normalized_result[18]), .B1(n6192), .Y(n5833) );
OAI2BB1X1TS U6836 ( .A0N(n2346), .A1N(n1960), .B0(n5833), .Y(n5834) );
AOI21X1TS U6837 ( .A0(n2310), .A1(FPMULT_Add_result[18]), .B0(n5834), .Y(
n5835) );
OAI2BB1X1TS U6838 ( .A0N(n2307), .A1N(n1959), .B0(n5835), .Y(n1900) );
AOI22X1TS U6839 ( .A0(n6175), .A1(FPMULT_Add_result[21]), .B0(
FPMULT_Sgf_normalized_result[20]), .B1(n6110), .Y(n5836) );
OAI2BB1X1TS U6840 ( .A0N(n2344), .A1N(n1962), .B0(n5836), .Y(n5837) );
AOI21X1TS U6841 ( .A0(n2311), .A1(FPMULT_Add_result[20]), .B0(n5837), .Y(
n5838) );
OAI2BB1X1TS U6842 ( .A0N(n2308), .A1N(n1961), .B0(n5838), .Y(n1902) );
AOI22X1TS U6843 ( .A0(n6182), .A1(FPMULT_Add_result[20]), .B0(
FPMULT_Sgf_normalized_result[19]), .B1(n6192), .Y(n5839) );
OAI2BB1X1TS U6844 ( .A0N(n2345), .A1N(n1961), .B0(n5839), .Y(n5840) );
AOI21X1TS U6845 ( .A0(n2310), .A1(FPMULT_Add_result[19]), .B0(n5840), .Y(
n5841) );
OAI2BB1X1TS U6846 ( .A0N(n2307), .A1N(n1960), .B0(n5841), .Y(n1901) );
AOI22X1TS U6847 ( .A0(n6193), .A1(FPMULT_Add_result[22]), .B0(
FPMULT_Sgf_normalized_result[21]), .B1(n6110), .Y(n5842) );
OAI2BB1X1TS U6848 ( .A0N(n1963), .A1N(n2344), .B0(n5842), .Y(n5843) );
AOI21X1TS U6849 ( .A0(n2311), .A1(FPMULT_Add_result[21]), .B0(n5843), .Y(
n5844) );
OAI2BB1X1TS U6850 ( .A0N(n2308), .A1N(n1962), .B0(n5844), .Y(n1903) );
AOI22X1TS U6851 ( .A0(n6182), .A1(FPMULT_Add_result[23]), .B0(
FPMULT_Sgf_normalized_result[22]), .B1(n6110), .Y(n5845) );
OAI2BB1X1TS U6852 ( .A0N(n1964), .A1N(n2345), .B0(n5845), .Y(n5846) );
AOI21X1TS U6853 ( .A0(n2310), .A1(FPMULT_Add_result[22]), .B0(n5846), .Y(
n5847) );
OAI2BB1X1TS U6854 ( .A0N(n2307), .A1N(n1963), .B0(n5847), .Y(n1904) );
AOI22X1TS U6855 ( .A0(n6175), .A1(FPMULT_Add_result[18]), .B0(
FPMULT_Sgf_normalized_result[17]), .B1(n6192), .Y(n5848) );
OAI2BB1X1TS U6856 ( .A0N(n2346), .A1N(n1959), .B0(n5848), .Y(n5849) );
AOI21X1TS U6857 ( .A0(n2311), .A1(FPMULT_Add_result[17]), .B0(n5849), .Y(
n5850) );
OAI2BB1X1TS U6858 ( .A0N(n2308), .A1N(n1958), .B0(n5850), .Y(n1899) );
AOI22X1TS U6859 ( .A0(n6182), .A1(FPMULT_Add_result[14]), .B0(
FPMULT_Sgf_normalized_result[13]), .B1(n6192), .Y(n5851) );
OAI2BB1X1TS U6860 ( .A0N(n2344), .A1N(n1955), .B0(n5851), .Y(n5852) );
AOI21X1TS U6861 ( .A0(n2310), .A1(FPMULT_Add_result[13]), .B0(n5852), .Y(
n5853) );
OAI2BB1X1TS U6862 ( .A0N(n2307), .A1N(n1954), .B0(n5853), .Y(n1895) );
AOI22X1TS U6863 ( .A0(n6193), .A1(FPMULT_Add_result[13]), .B0(
FPMULT_Sgf_normalized_result[12]), .B1(n6192), .Y(n5854) );
OAI2BB1X1TS U6864 ( .A0N(n2345), .A1N(n1954), .B0(n5854), .Y(n5855) );
AOI21X1TS U6865 ( .A0(n2311), .A1(FPMULT_Add_result[12]), .B0(n5855), .Y(
n5856) );
OAI2BB1X1TS U6866 ( .A0N(n2308), .A1N(n1953), .B0(n5856), .Y(n1894) );
INVX2TS U6867 ( .A(n2323), .Y(n5859) );
NOR3BX1TS U6868 ( .AN(FPMULT_Op_MY[30]), .B(FPMULT_FSM_selector_B[1]), .C(
FPMULT_FSM_selector_B[0]), .Y(n5860) );
XOR2X1TS U6869 ( .A(n2323), .B(n5860), .Y(DP_OP_134J305_123_859_n15) );
OAI2BB1X1TS U6870 ( .A0N(FPMULT_Op_MY[29]), .A1N(n6671), .B0(n5861), .Y(
n5862) );
XOR2X1TS U6871 ( .A(n2323), .B(n5862), .Y(DP_OP_134J305_123_859_n16) );
OAI2BB1X1TS U6872 ( .A0N(FPMULT_Op_MY[28]), .A1N(n6671), .B0(n5861), .Y(
n5863) );
XOR2X1TS U6873 ( .A(n2323), .B(n5863), .Y(DP_OP_134J305_123_859_n17) );
OAI2BB1X1TS U6874 ( .A0N(FPMULT_Op_MY[27]), .A1N(n6671), .B0(n5861), .Y(
n5864) );
XOR2X1TS U6875 ( .A(n2323), .B(n5864), .Y(DP_OP_134J305_123_859_n18) );
OAI2BB1X1TS U6876 ( .A0N(FPMULT_Op_MY[26]), .A1N(n6671), .B0(n5861), .Y(
n5865) );
XOR2X1TS U6877 ( .A(n2323), .B(n5865), .Y(DP_OP_134J305_123_859_n19) );
OAI2BB1X1TS U6878 ( .A0N(FPMULT_Op_MY[25]), .A1N(n6671), .B0(n5861), .Y(
n5866) );
XOR2X1TS U6879 ( .A(n2323), .B(n5866), .Y(DP_OP_134J305_123_859_n20) );
OAI2BB1X1TS U6880 ( .A0N(FPMULT_Op_MY[24]), .A1N(n6671), .B0(n5861), .Y(
n5867) );
XOR2X1TS U6881 ( .A(n5013), .B(n5867), .Y(DP_OP_134J305_123_859_n21) );
XOR2X1TS U6882 ( .A(n5013), .B(n5869), .Y(DP_OP_134J305_123_859_n22) );
AOI22X1TS U6883 ( .A0(FPSENCOS_d_ff_Zn[31]), .A1(n6492), .B0(n5871), .B1(
FPSENCOS_d_ff1_Z[31]), .Y(n5872) );
OAI2BB1X1TS U6884 ( .A0N(FPSENCOS_d_ff2_Z[31]), .A1N(n6471), .B0(n5872), .Y(
n1478) );
AOI22X1TS U6885 ( .A0(Data_1[31]), .A1(n5878), .B0(FPADDSUB_intDX[31]), .B1(
n5877), .Y(n5874) );
OAI2BB1X1TS U6886 ( .A0N(FPSENCOS_d_ff2_Z[31]), .A1N(n5371), .B0(n5874), .Y(
n5875) );
AOI21X1TS U6887 ( .A0(n5880), .A1(FPSENCOS_d_ff2_Y[31]), .B0(n5875), .Y(
n5876) );
OAI2BB1X1TS U6888 ( .A0N(n2266), .A1N(FPSENCOS_d_ff2_X[31]), .B0(n5876), .Y(
n1332) );
AOI21X1TS U6889 ( .A0(n5880), .A1(FPSENCOS_d_ff3_sh_x_out[31]), .B0(n5879),
.Y(n5881) );
OAI2BB1X1TS U6890 ( .A0N(n6639), .A1N(FPSENCOS_d_ff3_sh_y_out[31]), .B0(
n5881), .Y(n1333) );
AOI22X1TS U6891 ( .A0(n2298), .A1(n6347), .B0(n2290), .B1(n6344), .Y(n5884)
);
OAI22X1TS U6892 ( .A0(n5884), .A1(n6348), .B0(n5883), .B1(n6349), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[24]) );
XNOR2X1TS U6893 ( .A(n5886), .B(n5885), .Y(n5887) );
NAND2X1TS U6894 ( .A(n6347), .B(n5888), .Y(n5890) );
OAI22X1TS U6895 ( .A0(n5252), .A1(n5890), .B0(n5889), .B1(n6349), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[25]) );
INVX2TS U6896 ( .A(n5891), .Y(n5913) );
NAND2X2TS U6897 ( .A(n4909), .B(n5892), .Y(n5911) );
AOI21X1TS U6898 ( .A0(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[28]), .A1(n2317),
.B0(n5908), .Y(n5894) );
AOI22X1TS U6899 ( .A0(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[49]), .A1(n2312),
.B0(FPADDSUB_Sgf_normalized_result[23]), .B1(n5920), .Y(n5893) );
AOI21X1TS U6900 ( .A0(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[29]), .A1(n2317),
.B0(n5908), .Y(n5897) );
AOI22X1TS U6901 ( .A0(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[48]), .A1(n2312),
.B0(FPADDSUB_Sgf_normalized_result[22]), .B1(n5920), .Y(n5896) );
AOI21X1TS U6902 ( .A0(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[30]), .A1(n2317),
.B0(n5908), .Y(n5900) );
AOI22X1TS U6903 ( .A0(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[47]), .A1(n2312),
.B0(FPADDSUB_Sgf_normalized_result[21]), .B1(n5920), .Y(n5899) );
AOI21X1TS U6904 ( .A0(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[31]), .A1(n2316),
.B0(n5908), .Y(n5903) );
AOI22X1TS U6905 ( .A0(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[46]), .A1(n2312),
.B0(FPADDSUB_Sgf_normalized_result[20]), .B1(n5920), .Y(n5902) );
AOI21X1TS U6906 ( .A0(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[32]), .A1(n2316),
.B0(n5908), .Y(n5906) );
AOI22X1TS U6907 ( .A0(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[45]), .A1(n2312),
.B0(FPADDSUB_Sgf_normalized_result[19]), .B1(n5920), .Y(n5905) );
AOI21X1TS U6908 ( .A0(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[44]), .A1(n2312),
.B0(n5908), .Y(n5910) );
AOI22X1TS U6909 ( .A0(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[33]), .A1(n2316),
.B0(FPADDSUB_Sgf_normalized_result[18]), .B1(n5920), .Y(n5909) );
INVX2TS U6910 ( .A(n5914), .Y(n5926) );
NAND2X1TS U6911 ( .A(n4909), .B(n5915), .Y(n5918) );
AOI22X1TS U6912 ( .A0(n5921), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[43]), .B0(
FPADDSUB_Sgf_normalized_result[17]), .B1(n5920), .Y(n5917) );
NAND2X1TS U6913 ( .A(n5018), .B(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[51]), .Y(n5916) );
NAND2X1TS U6914 ( .A(n4909), .B(n5919), .Y(n5925) );
AOI22X1TS U6915 ( .A0(n5921), .A1(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[42]), .B0(
FPADDSUB_Sgf_normalized_result[16]), .B1(n5920), .Y(n5924) );
NAND2X1TS U6916 ( .A(n5922), .B(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[50]), .Y(n5923) );
MXI2X1TS U6917 ( .A(FPADDSUB_add_overflow_flag), .B(n6715), .S0(n6407), .Y(
n1698) );
NAND2X1TS U6918 ( .A(n5946), .B(n5934), .Y(n6514) );
NOR2X1TS U6919 ( .A(FPADDSUB_Add_Subt_result[11]), .B(
FPADDSUB_Add_Subt_result[10]), .Y(n6516) );
AOI211X1TS U6920 ( .A0(n7004), .A1(n6853), .B0(n5945), .C0(n5944), .Y(n5947)
);
INVX2TS U6921 ( .A(n5951), .Y(n5954) );
XOR2X1TS U6922 ( .A(n5953), .B(n5954), .Y(n5952) );
INVX2TS U6923 ( .A(n5955), .Y(n5957) );
NAND2X1TS U6924 ( .A(n5957), .B(n5956), .Y(n5958) );
XNOR2X1TS U6925 ( .A(n5959), .B(n5958), .Y(n5960) );
INVX2TS U6926 ( .A(n5961), .Y(n5989) );
INVX2TS U6927 ( .A(n5962), .Y(n5973) );
NAND2X1TS U6928 ( .A(n5973), .B(n5971), .Y(n5963) );
XNOR2X1TS U6929 ( .A(n5989), .B(n5963), .Y(n5964) );
NAND2X1TS U6930 ( .A(n5966), .B(n5965), .Y(n5967) );
XNOR2X1TS U6931 ( .A(n5968), .B(n5967), .Y(n5970) );
INVX2TS U6932 ( .A(n5971), .Y(n5972) );
AOI21X1TS U6933 ( .A0(n5989), .A1(n5973), .B0(n5972), .Y(n5978) );
NAND2X1TS U6934 ( .A(n5976), .B(n5975), .Y(n5977) );
XOR2X1TS U6935 ( .A(n5978), .B(n5977), .Y(n5980) );
BUFX3TS U6936 ( .A(n5979), .Y(n6036) );
INVX2TS U6937 ( .A(n5981), .Y(n5983) );
NAND2X1TS U6938 ( .A(n5983), .B(n5982), .Y(n5984) );
XOR2X1TS U6939 ( .A(n5985), .B(n5984), .Y(n5986) );
AOI21X1TS U6940 ( .A0(n5989), .A1(n5988), .B0(n5987), .Y(n5995) );
INVX2TS U6941 ( .A(n5994), .Y(n5990) );
NAND2X1TS U6942 ( .A(n5990), .B(n5993), .Y(n5991) );
XOR2X1TS U6943 ( .A(n5995), .B(n5991), .Y(n5992) );
NAND2X1TS U6944 ( .A(n5998), .B(n5997), .Y(n5999) );
XNOR2X1TS U6945 ( .A(n6000), .B(n5999), .Y(n6001) );
NAND2X1TS U6946 ( .A(n6003), .B(n6002), .Y(n6004) );
XNOR2X1TS U6947 ( .A(n6005), .B(n6004), .Y(n6006) );
INVX2TS U6948 ( .A(n6007), .Y(n6009) );
NAND2X1TS U6949 ( .A(n6009), .B(n6008), .Y(n6010) );
XOR2X1TS U6950 ( .A(n6011), .B(n6010), .Y(n6012) );
INVX2TS U6951 ( .A(n6013), .Y(n6061) );
INVX2TS U6952 ( .A(n6023), .Y(n6014) );
NAND2X1TS U6953 ( .A(n6014), .B(n6022), .Y(n6015) );
XOR2X1TS U6954 ( .A(n6061), .B(n6015), .Y(n6016) );
NAND2X1TS U6955 ( .A(n6018), .B(n6017), .Y(n6019) );
XNOR2X1TS U6956 ( .A(n6020), .B(n6019), .Y(n6021) );
NAND2X1TS U6957 ( .A(n6026), .B(n6025), .Y(n6027) );
XNOR2X1TS U6958 ( .A(n6028), .B(n6027), .Y(n6029) );
INVX2TS U6959 ( .A(n6030), .Y(n6057) );
AOI21X1TS U6960 ( .A0(n6057), .A1(n2832), .B0(n6031), .Y(n6035) );
NAND2X1TS U6961 ( .A(n6033), .B(n6032), .Y(n6034) );
XOR2X1TS U6962 ( .A(n6035), .B(n6034), .Y(n6037) );
INVX2TS U6963 ( .A(n6038), .Y(n6041) );
OAI21X1TS U6964 ( .A0(n6061), .A1(n6041), .B0(n6040), .Y(n6048) );
INVX2TS U6965 ( .A(n6042), .Y(n6047) );
NAND2X1TS U6966 ( .A(n6047), .B(n6045), .Y(n6043) );
XNOR2X1TS U6967 ( .A(n6048), .B(n6043), .Y(n6044) );
INVX2TS U6968 ( .A(n6045), .Y(n6046) );
AOI21X1TS U6969 ( .A0(n6048), .A1(n6047), .B0(n6046), .Y(n6053) );
NAND2X1TS U6970 ( .A(n6051), .B(n6050), .Y(n6052) );
XOR2X1TS U6971 ( .A(n6053), .B(n6052), .Y(n6054) );
NAND2X1TS U6972 ( .A(n2832), .B(n6055), .Y(n6056) );
XNOR2X1TS U6973 ( .A(n6057), .B(n6056), .Y(n6058) );
OAI21X1TS U6974 ( .A0(n6061), .A1(n6060), .B0(n6059), .Y(n6086) );
INVX2TS U6975 ( .A(n6086), .Y(n6076) );
INVX2TS U6976 ( .A(n6062), .Y(n6065) );
INVX2TS U6977 ( .A(n6063), .Y(n6064) );
OAI21X1TS U6978 ( .A0(n6076), .A1(n6065), .B0(n6064), .Y(n6081) );
INVX2TS U6979 ( .A(n6066), .Y(n6079) );
INVX2TS U6980 ( .A(n6078), .Y(n6067) );
AOI21X1TS U6981 ( .A0(n6081), .A1(n6079), .B0(n6067), .Y(n6072) );
NAND2X1TS U6982 ( .A(n6070), .B(n6069), .Y(n6071) );
XOR2X1TS U6983 ( .A(n6072), .B(n6071), .Y(n6073) );
INVX2TS U6984 ( .A(n6074), .Y(n6085) );
NAND2X1TS U6985 ( .A(n6085), .B(n6083), .Y(n6075) );
XOR2X1TS U6986 ( .A(n6076), .B(n6075), .Y(n6077) );
NAND2X1TS U6987 ( .A(n6079), .B(n6078), .Y(n6080) );
XNOR2X1TS U6988 ( .A(n6081), .B(n6080), .Y(n6082) );
INVX2TS U6989 ( .A(n6083), .Y(n6084) );
AOI21X1TS U6990 ( .A0(n6086), .A1(n6085), .B0(n6084), .Y(n6091) );
NAND2X1TS U6991 ( .A(n6089), .B(n6088), .Y(n6090) );
XOR2X1TS U6992 ( .A(n6091), .B(n6090), .Y(n6093) );
OAI2BB1X1TS U6993 ( .A0N(FPMULT_FS_Module_state_reg[2]), .A1N(n6205), .B0(
FPMULT_FS_Module_state_reg[3]), .Y(n6096) );
AOI21X1TS U6994 ( .A0(FPMULT_zero_flag), .A1(n2323), .B0(n6094), .Y(n6095)
);
NAND2X1TS U6995 ( .A(n6096), .B(n6095), .Y(n2060) );
NAND2X1TS U6996 ( .A(FPMULT_Sgf_normalized_result[6]), .B(
FPMULT_Sgf_normalized_result[7]), .Y(n6102) );
NOR2X1TS U6997 ( .A(n6673), .B(n6732), .Y(n6138) );
NAND2X1TS U6998 ( .A(n6138), .B(FPMULT_Sgf_normalized_result[10]), .Y(n6105)
);
MXI2X1TS U6999 ( .A(n1964), .B(FPMULT_Add_result[23]), .S0(
FPMULT_FSM_selector_C), .Y(n6107) );
AOI21X1TS U7000 ( .A0(n6108), .A1(n6107), .B0(n6110), .Y(n6109) );
AHHCINX2TS U7001 ( .A(FPMULT_Sgf_normalized_result[22]), .CIN(n6111), .S(
n6112), .CO(n6198) );
INVX2TS U7002 ( .A(n6125), .Y(n6122) );
AHHCONX2TS U7003 ( .A(FPMULT_Sgf_normalized_result[21]), .CI(n6113), .CON(
n6111), .S(n6114) );
AHHCINX2TS U7004 ( .A(FPMULT_Sgf_normalized_result[20]), .CIN(n6115), .S(
n6116), .CO(n6113) );
AHHCONX2TS U7005 ( .A(FPMULT_Sgf_normalized_result[19]), .CI(n6117), .CON(
n6115), .S(n6118) );
AHHCINX2TS U7006 ( .A(FPMULT_Sgf_normalized_result[18]), .CIN(n6119), .S(
n6120), .CO(n6117) );
AHHCONX2TS U7007 ( .A(FPMULT_Sgf_normalized_result[17]), .CI(n6121), .CON(
n6119), .S(n6123) );
AHHCINX2TS U7008 ( .A(FPMULT_Sgf_normalized_result[16]), .CIN(n6124), .S(
n6126), .CO(n6121) );
AHHCONX2TS U7009 ( .A(FPMULT_Sgf_normalized_result[15]), .CI(n6127), .CON(
n6124), .S(n6128) );
AHHCINX2TS U7010 ( .A(FPMULT_Sgf_normalized_result[14]), .CIN(n6129), .S(
n6130), .CO(n6127) );
AHHCONX2TS U7011 ( .A(FPMULT_Sgf_normalized_result[13]), .CI(n6131), .CON(
n6129), .S(n6132) );
AHHCINX2TS U7012 ( .A(FPMULT_Sgf_normalized_result[12]), .CIN(n6133), .S(
n6134), .CO(n6131) );
AHHCONX2TS U7013 ( .A(FPMULT_Sgf_normalized_result[11]), .CI(n6135), .CON(
n6133), .S(n6136) );
INVX2TS U7014 ( .A(n6137), .Y(n6143) );
NAND2X1TS U7015 ( .A(n6143), .B(n6138), .Y(n6139) );
XOR2X1TS U7016 ( .A(n6139), .B(n6805), .Y(n6140) );
NAND2X1TS U7017 ( .A(n6143), .B(FPMULT_Sgf_normalized_result[8]), .Y(n6141)
);
XOR2X1TS U7018 ( .A(n6141), .B(n6732), .Y(n6142) );
XNOR2X1TS U7019 ( .A(n6143), .B(n6673), .Y(n6144) );
INVX2TS U7020 ( .A(n6145), .Y(n6162) );
OAI21X1TS U7021 ( .A0(n6162), .A1(n6733), .B0(n6146), .Y(n6152) );
NAND2X1TS U7022 ( .A(n6152), .B(FPMULT_Sgf_normalized_result[6]), .Y(n6147)
);
XOR2X1TS U7023 ( .A(n6147), .B(n6806), .Y(n6148) );
AOI22X1TS U7024 ( .A0(n6182), .A1(FPMULT_Add_result[8]), .B0(
FPMULT_Sgf_normalized_result[7]), .B1(n6181), .Y(n6149) );
OAI2BB1X1TS U7025 ( .A0N(n2346), .A1N(n1949), .B0(n6149), .Y(n6150) );
AOI21X1TS U7026 ( .A0(n2309), .A1(FPMULT_Add_result[7]), .B0(n6150), .Y(
n6151) );
OAI2BB1X1TS U7027 ( .A0N(n2307), .A1N(FPMULT_P_Sgf[30]), .B0(n6151), .Y(
n1889) );
XNOR2X1TS U7028 ( .A(n6152), .B(n6793), .Y(n6153) );
AOI22X1TS U7029 ( .A0(n6193), .A1(FPMULT_Add_result[7]), .B0(
FPMULT_Sgf_normalized_result[6]), .B1(n6181), .Y(n6154) );
OAI2BB1X1TS U7030 ( .A0N(n2344), .A1N(FPMULT_P_Sgf[30]), .B0(n6154), .Y(
n6155) );
AOI21X1TS U7031 ( .A0(n2311), .A1(FPMULT_Add_result[6]), .B0(n6155), .Y(
n6156) );
OAI2BB1X1TS U7032 ( .A0N(n2308), .A1N(FPMULT_P_Sgf[29]), .B0(n6156), .Y(
n1888) );
NAND2X1TS U7033 ( .A(n6162), .B(n6792), .Y(n6157) );
XNOR2X1TS U7034 ( .A(n6157), .B(n6733), .Y(n6158) );
AOI22X1TS U7035 ( .A0(n6175), .A1(FPMULT_Add_result[6]), .B0(
FPMULT_Sgf_normalized_result[5]), .B1(n6181), .Y(n6159) );
OAI2BB1X1TS U7036 ( .A0N(n2344), .A1N(FPMULT_P_Sgf[29]), .B0(n6159), .Y(
n6160) );
AOI21X1TS U7037 ( .A0(n2309), .A1(FPMULT_Add_result[5]), .B0(n6160), .Y(
n6161) );
OAI2BB1X1TS U7038 ( .A0N(n2306), .A1N(FPMULT_P_Sgf[28]), .B0(n6161), .Y(
n1887) );
XOR2X1TS U7039 ( .A(n6162), .B(FPMULT_Sgf_normalized_result[4]), .Y(n6163)
);
AOI22X1TS U7040 ( .A0(n6182), .A1(FPMULT_Add_result[5]), .B0(
FPMULT_Sgf_normalized_result[4]), .B1(n6181), .Y(n6164) );
OAI2BB1X1TS U7041 ( .A0N(n2345), .A1N(FPMULT_P_Sgf[28]), .B0(n6164), .Y(
n6165) );
AOI21X1TS U7042 ( .A0(n2310), .A1(FPMULT_Add_result[4]), .B0(n6165), .Y(
n6166) );
OAI2BB1X1TS U7043 ( .A0N(n2307), .A1N(FPMULT_P_Sgf[27]), .B0(n6166), .Y(
n1886) );
XOR2X1TS U7044 ( .A(n6168), .B(n6727), .Y(n6169) );
AOI22X1TS U7045 ( .A0(n6193), .A1(FPMULT_Add_result[4]), .B0(
FPMULT_Sgf_normalized_result[3]), .B1(n6181), .Y(n6170) );
OAI2BB1X1TS U7046 ( .A0N(n2346), .A1N(FPMULT_P_Sgf[27]), .B0(n6170), .Y(
n6171) );
AOI21X1TS U7047 ( .A0(n2311), .A1(FPMULT_Add_result[3]), .B0(n6171), .Y(
n6172) );
OAI2BB1X1TS U7048 ( .A0N(n2308), .A1N(FPMULT_P_Sgf[26]), .B0(n6172), .Y(
n1885) );
XOR2X1TS U7049 ( .A(n6173), .B(FPMULT_Sgf_normalized_result[2]), .Y(n6174)
);
AOI22X1TS U7050 ( .A0(n6175), .A1(FPMULT_Add_result[3]), .B0(
FPMULT_Sgf_normalized_result[2]), .B1(n6181), .Y(n6176) );
OAI2BB1X1TS U7051 ( .A0N(n2346), .A1N(FPMULT_P_Sgf[26]), .B0(n6176), .Y(
n6177) );
AOI21X1TS U7052 ( .A0(n2309), .A1(FPMULT_Add_result[2]), .B0(n6177), .Y(
n6178) );
OAI2BB1X1TS U7053 ( .A0N(n2306), .A1N(FPMULT_P_Sgf[25]), .B0(n6178), .Y(
n1884) );
XNOR2X1TS U7054 ( .A(FPMULT_Sgf_normalized_result[0]), .B(
FPMULT_Sgf_normalized_result[1]), .Y(n6180) );
AOI22X1TS U7055 ( .A0(n6182), .A1(FPMULT_Add_result[2]), .B0(
FPMULT_Sgf_normalized_result[1]), .B1(n6181), .Y(n6183) );
OAI2BB1X1TS U7056 ( .A0N(n2344), .A1N(FPMULT_P_Sgf[25]), .B0(n6183), .Y(
n6184) );
AOI21X1TS U7057 ( .A0(n2310), .A1(FPMULT_Add_result[1]), .B0(n6184), .Y(
n6185) );
OAI2BB1X1TS U7058 ( .A0N(n2307), .A1N(FPMULT_P_Sgf[24]), .B0(n6185), .Y(
n1883) );
INVX2TS U7059 ( .A(n6186), .Y(n6188) );
XOR2X1TS U7060 ( .A(n6190), .B(n6189), .Y(n6191) );
AOI22X1TS U7061 ( .A0(n6193), .A1(FPMULT_Add_result[1]), .B0(
FPMULT_Sgf_normalized_result[0]), .B1(n6192), .Y(n6194) );
OAI2BB1X1TS U7062 ( .A0N(n2345), .A1N(FPMULT_P_Sgf[24]), .B0(n6194), .Y(
n6196) );
AOI21X1TS U7063 ( .A0(n2309), .A1(FPMULT_Add_result[0]), .B0(n6196), .Y(
n6197) );
OAI2BB1X1TS U7064 ( .A0N(FPMULT_P_Sgf[23]), .A1N(n2308), .B0(n6197), .Y(
n1882) );
ADDHXLTS U7065 ( .A(FPMULT_Sgf_normalized_result[23]), .B(n6198), .CO(n6200),
.S(n6106) );
NOR2XLTS U7066 ( .A(FPMULT_FS_Module_state_reg[2]), .B(
FPMULT_FS_Module_state_reg[0]), .Y(n6203) );
AOI211X1TS U7067 ( .A0(n2323), .A1(n6852), .B0(n6203), .C0(n6202), .Y(n6204)
);
NOR2BX1TS U7068 ( .AN(n6205), .B(n6204), .Y(n2059) );
NAND2X1TS U7069 ( .A(n6391), .B(n6803), .Y(n2056) );
INVX2TS U7070 ( .A(n1906), .Y(n6354) );
INVX4TS U7071 ( .A(n2141), .Y(n6207) );
INVX2TS U7072 ( .A(n2833), .Y(n6209) );
INVX2TS U7073 ( .A(n1845), .Y(n6356) );
OAI2BB2XLTS U7074 ( .B0(n6534), .B1(n6536), .A0N(n6208), .A1N(
FPADDSUB_Sgf_normalized_result[11]), .Y(n1547) );
OAI2BB2XLTS U7075 ( .B0(n6534), .B1(n6538), .A0N(n6208), .A1N(
FPADDSUB_Sgf_normalized_result[10]), .Y(n1543) );
OAI2BB2XLTS U7076 ( .B0(n6534), .B1(n6539), .A0N(n6208), .A1N(
FPADDSUB_Sgf_normalized_result[9]), .Y(n1539) );
OAI2BB2XLTS U7077 ( .B0(n6534), .B1(n6540), .A0N(n6208), .A1N(
FPADDSUB_Sgf_normalized_result[8]), .Y(n1535) );
OAI2BB2XLTS U7078 ( .B0(n6525), .B1(n6541), .A0N(n6208), .A1N(
FPADDSUB_Sgf_normalized_result[7]), .Y(n1531) );
OAI2BB2XLTS U7079 ( .B0(n6209), .B1(n6544), .A0N(n6208), .A1N(
FPADDSUB_Sgf_normalized_result[6]), .Y(n1527) );
OAI2BB2XLTS U7080 ( .B0(n6525), .B1(n6545), .A0N(n6208), .A1N(
FPADDSUB_Sgf_normalized_result[5]), .Y(n1523) );
OAI2BB2XLTS U7081 ( .B0(n6209), .B1(n6549), .A0N(n6208), .A1N(
FPADDSUB_Sgf_normalized_result[4]), .Y(n1519) );
OAI2BB2XLTS U7082 ( .B0(n6525), .B1(n6551), .A0N(n6208), .A1N(
FPADDSUB_Sgf_normalized_result[3]), .Y(n1515) );
OAI2BB2XLTS U7083 ( .B0(n6209), .B1(n6619), .A0N(n6208), .A1N(
FPADDSUB_Sgf_normalized_result[2]), .Y(n1511) );
INVX2TS U7084 ( .A(n6210), .Y(n6212) );
NAND2X1TS U7085 ( .A(n6212), .B(n6211), .Y(n6213) );
XOR2X1TS U7086 ( .A(n6213), .B(n6257), .Y(n6214) );
NAND2X1TS U7087 ( .A(n6216), .B(n6215), .Y(n6218) );
XNOR2X1TS U7088 ( .A(n6218), .B(n6217), .Y(n6219) );
INVX2TS U7089 ( .A(n6220), .Y(n6222) );
NAND2X1TS U7090 ( .A(n6222), .B(n6221), .Y(n6224) );
XOR2X1TS U7091 ( .A(n6224), .B(n6223), .Y(n6225) );
INVX2TS U7092 ( .A(n6231), .Y(n6227) );
NAND2X1TS U7093 ( .A(n6227), .B(n6230), .Y(n6228) );
XOR2X1TS U7094 ( .A(n6232), .B(n6228), .Y(n6229) );
INVX2TS U7095 ( .A(n6233), .Y(n6235) );
NAND2X1TS U7096 ( .A(n6235), .B(n6234), .Y(n6236) );
XNOR2X1TS U7097 ( .A(n6237), .B(n6236), .Y(n6238) );
INVX2TS U7098 ( .A(n6239), .Y(n6245) );
NAND2X1TS U7099 ( .A(n6244), .B(n6240), .Y(n6241) );
XNOR2X1TS U7100 ( .A(n6245), .B(n6241), .Y(n6242) );
AOI21X1TS U7101 ( .A0(n6245), .A1(n6244), .B0(n6243), .Y(n6249) );
NAND2X1TS U7102 ( .A(n6247), .B(n6246), .Y(n6248) );
XOR2X1TS U7103 ( .A(n6249), .B(n6248), .Y(n6250) );
INVX2TS U7104 ( .A(n6251), .Y(n6262) );
INVX2TS U7105 ( .A(n6261), .Y(n6252) );
NAND2X1TS U7106 ( .A(n6252), .B(n6260), .Y(n6253) );
XOR2X1TS U7107 ( .A(n6262), .B(n6253), .Y(n6254) );
INVX2TS U7108 ( .A(n6263), .Y(n6265) );
NAND2X1TS U7109 ( .A(n6265), .B(n6264), .Y(n6266) );
XNOR2X1TS U7110 ( .A(n6267), .B(n6266), .Y(n6268) );
NAND2X1TS U7111 ( .A(n6270), .B(n6269), .Y(n6271) );
XNOR2X1TS U7112 ( .A(n6272), .B(n6271), .Y(n6273) );
INVX2TS U7113 ( .A(n6278), .Y(n6280) );
NAND2X1TS U7114 ( .A(n6280), .B(n6279), .Y(n6282) );
XOR2X1TS U7115 ( .A(n6282), .B(n6281), .Y(n6283) );
INVX2TS U7116 ( .A(n6284), .Y(n6290) );
INVX2TS U7117 ( .A(n6289), .Y(n6285) );
NAND2X1TS U7118 ( .A(n6285), .B(n6288), .Y(n6286) );
XOR2X1TS U7119 ( .A(n6290), .B(n6286), .Y(n6287) );
INVX2TS U7120 ( .A(n6291), .Y(n6293) );
XNOR2X1TS U7121 ( .A(n6295), .B(n6294), .Y(n6296) );
INVX2TS U7122 ( .A(n6297), .Y(n6302) );
NAND2X1TS U7123 ( .A(n6298), .B(n2168), .Y(n6299) );
XNOR2X1TS U7124 ( .A(n6302), .B(n6299), .Y(n6300) );
AOI21X1TS U7125 ( .A0(n6302), .A1(n2168), .B0(n6301), .Y(n6305) );
NAND2X1TS U7126 ( .A(n2794), .B(n6303), .Y(n6304) );
XOR2X1TS U7127 ( .A(n6305), .B(n6304), .Y(n6307) );
INVX2TS U7128 ( .A(n6308), .Y(n6310) );
XOR2X1TS U7129 ( .A(n6312), .B(n6311), .Y(n6313) );
NAND2X1TS U7130 ( .A(n6315), .B(n6314), .Y(n6316) );
XNOR2X1TS U7131 ( .A(n6317), .B(n6316), .Y(n6318) );
NOR4X1TS U7132 ( .A(Data_1[12]), .B(Data_1[11]), .C(Data_1[10]), .D(
Data_1[9]), .Y(n6325) );
NOR4X1TS U7133 ( .A(Data_1[8]), .B(Data_1[7]), .C(Data_1[6]), .D(Data_1[0]),
.Y(n6324) );
NOR4X1TS U7134 ( .A(Data_1[3]), .B(Data_1[16]), .C(Data_1[1]), .D(Data_1[22]), .Y(n6322) );
NOR4X1TS U7135 ( .A(Data_1[21]), .B(Data_1[19]), .C(Data_1[14]), .D(
Data_1[20]), .Y(n6320) );
NOR4X1TS U7136 ( .A(Data_1[13]), .B(Data_1[15]), .C(Data_1[17]), .D(
Data_1[18]), .Y(n6319) );
AND4X1TS U7137 ( .A(n6322), .B(n6321), .C(n6320), .D(n6319), .Y(n6323) );
NOR4BX1TS U7138 ( .AN(n2318), .B(dataB[28]), .C(operation_reg_0_), .D(
dataB[23]), .Y(n6330) );
NOR4X1TS U7139 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[26]), .D(dataB[29]),
.Y(n6329) );
NAND4XLTS U7140 ( .A(dataA[30]), .B(dataA[27]), .C(dataA[28]), .D(dataA[26]),
.Y(n6327) );
NAND4XLTS U7141 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[25]), .D(dataA[24]),
.Y(n6326) );
OR3X1TS U7142 ( .A(n7008), .B(n6327), .C(n6326), .Y(n6331) );
NOR3X1TS U7143 ( .A(dataB[25]), .B(dataB[31]), .C(n6331), .Y(n6328) );
NOR4X1TS U7144 ( .A(dataA[30]), .B(dataA[27]), .C(dataA[28]), .D(dataA[26]),
.Y(n6334) );
NOR4X1TS U7145 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[25]), .D(dataA[24]),
.Y(n6333) );
NOR4BX1TS U7146 ( .AN(n2318), .B(dataA[31]), .C(operation_reg_0_), .D(n7008),
.Y(n6332) );
NOR2X1TS U7147 ( .A(n2318), .B(n6331), .Y(n6339) );
NAND4XLTS U7148 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[26]), .D(dataB[29]),
.Y(n6335) );
OAI31X1TS U7149 ( .A0(n6337), .A1(n6336), .A2(n6335), .B0(dataB[27]), .Y(
n6338) );
OAI2BB2XLTS U7150 ( .B0(n6341), .B1(n6340), .A0N(n6339), .A1N(
operation_reg_0_), .Y(NaN_reg) );
AOI222X1TS U7151 ( .A0(n6344), .A1(n2299), .B0(n6347), .B1(n2315), .C0(n6345), .C1(n2289), .Y(n6342) );
OAI22X1TS U7152 ( .A0(n6349), .A1(n6343), .B0(n6342), .B1(n6348), .Y(
FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[23]) );
AOI22X1TS U7153 ( .A0(n2298), .A1(n6345), .B0(n2315), .B1(n6344), .Y(n6352)
);
AOI22X1TS U7154 ( .A0(n6347), .A1(n2300), .B0(n2290), .B1(n6346), .Y(n6350)
);
AOI32X1TS U7155 ( .A0(n6352), .A1(n6351), .A2(n6350), .B0(n6349), .B1(n6348),
.Y(FPADDSUB_Barrel_Shifter_module_Mux_Array_Data_array[22]) );
AOI32X1TS U7156 ( .A0(n6354), .A1(operation[2]), .A2(n6353), .B0(n6787),
.B1(n6355), .Y(overflow_flag) );
AOI22X1TS U7157 ( .A0(operation[2]), .A1(n7005), .B0(n6356), .B1(n6355), .Y(
underflow_flag) );
NOR4X1TS U7158 ( .A(n2452), .B(FPMULT_Op_MY[20]), .C(n2492), .D(n6358), .Y(
n6363) );
NOR4X1TS U7159 ( .A(n2285), .B(FPMULT_Op_MY[30]), .C(FPMULT_Op_MY[29]), .D(
FPMULT_Op_MY[28]), .Y(n6361) );
NAND4XLTS U7160 ( .A(n6364), .B(n6363), .C(n6362), .D(n6361), .Y(n6390) );
NOR4X1TS U7161 ( .A(n2283), .B(n2277), .C(FPMULT_Op_MY[13]), .D(
FPMULT_Op_MY[0]), .Y(n6370) );
NAND4XLTS U7162 ( .A(n6372), .B(n6371), .C(n6370), .D(n6369), .Y(n6389) );
NOR4X1TS U7163 ( .A(FPMULT_Op_MX[21]), .B(n6374), .C(n6373), .D(n6099), .Y(
n6378) );
NOR4X1TS U7164 ( .A(FPMULT_Op_MX[20]), .B(FPMULT_Op_MX[18]), .C(
FPMULT_Op_MX[16]), .D(n2221), .Y(n6377) );
NOR4X1TS U7165 ( .A(FPMULT_Op_MX[27]), .B(FPMULT_Op_MX[26]), .C(
FPMULT_Op_MX[25]), .D(FPMULT_Op_MX[23]), .Y(n6376) );
NOR4X1TS U7166 ( .A(n2704), .B(FPMULT_Op_MX[30]), .C(FPMULT_Op_MX[29]), .D(
FPMULT_Op_MX[28]), .Y(n6375) );
NAND4XLTS U7167 ( .A(n6378), .B(n6377), .C(n6376), .D(n6375), .Y(n6388) );
NOR4X1TS U7168 ( .A(FPMULT_Op_MX[6]), .B(FPMULT_Op_MX[0]), .C(n6379), .D(
FPMULT_Op_MX[12]), .Y(n6386) );
NOR4X1TS U7169 ( .A(FPMULT_Op_MX[10]), .B(FPMULT_Op_MX[8]), .C(
FPMULT_Op_MX[4]), .D(n6380), .Y(n6385) );
NOR4X1TS U7170 ( .A(FPMULT_Op_MX[9]), .B(FPMULT_Op_MX[5]), .C(n6382), .D(
n6381), .Y(n6384) );
NAND4XLTS U7171 ( .A(n6386), .B(n6385), .C(n6384), .D(n6383), .Y(n6387) );
OAI22X1TS U7172 ( .A0(n6390), .A1(n6389), .B0(n6388), .B1(n6387), .Y(n6392)
);
OA22X1TS U7173 ( .A0(FPMULT_exp_oper_result[0]), .A1(n6396), .B0(n6397),
.B1(mult_result[23]), .Y(n1880) );
OA22X1TS U7174 ( .A0(FPMULT_exp_oper_result[1]), .A1(n6394), .B0(n6393),
.B1(mult_result[24]), .Y(n1879) );
OA22X1TS U7175 ( .A0(FPMULT_exp_oper_result[2]), .A1(n6394), .B0(n6393),
.B1(mult_result[25]), .Y(n1878) );
OA22X1TS U7176 ( .A0(FPMULT_exp_oper_result[3]), .A1(n6394), .B0(n6393),
.B1(mult_result[26]), .Y(n1877) );
OA22X1TS U7177 ( .A0(FPMULT_exp_oper_result[4]), .A1(n6394), .B0(n6393),
.B1(mult_result[27]), .Y(n1876) );
OA22X1TS U7178 ( .A0(FPMULT_exp_oper_result[5]), .A1(n6394), .B0(n6393),
.B1(mult_result[28]), .Y(n1875) );
OA22X1TS U7179 ( .A0(FPMULT_exp_oper_result[6]), .A1(n6394), .B0(n6393),
.B1(mult_result[29]), .Y(n1874) );
OA22X1TS U7180 ( .A0(FPMULT_exp_oper_result[7]), .A1(n6394), .B0(n6397),
.B1(mult_result[30]), .Y(n1873) );
INVX2TS U7181 ( .A(n6396), .Y(n6395) );
INVX2TS U7182 ( .A(n6397), .Y(n6406) );
INVX2TS U7183 ( .A(n6397), .Y(n6399) );
NOR3X1TS U7184 ( .A(n1906), .B(n1905), .C(n6401), .Y(n6402) );
OAI2BB1X1TS U7185 ( .A0N(mult_result[31]), .A1N(n6406), .B0(n6405), .Y(n1849) );
AOI22X1TS U7186 ( .A0(FPADDSUB_FSM_selector_B[1]), .A1(n6407), .B0(
FPADDSUB_add_overflow_flag), .B1(n6524), .Y(n6409) );
NAND2X1TS U7187 ( .A(n6409), .B(n6408), .Y(n1846) );
AOI21X1TS U7188 ( .A0(n6752), .A1(n6677), .B0(n6410), .Y(n6411) );
BUFX3TS U7189 ( .A(n6618), .Y(n6543) );
OAI2BB2XLTS U7190 ( .B0(n6543), .B1(n6780), .A0N(n6618), .A1N(
FPSENCOS_d_ff_Xn[31]), .Y(n1843) );
INVX2TS U7191 ( .A(n5870), .Y(n6596) );
CLKBUFX2TS U7192 ( .A(n2279), .Y(n6595) );
OAI222X1TS U7193 ( .A0(n6415), .A1(n6436), .B0(n6435), .B1(n6503), .C0(n6711), .C1(n6414), .Y(n1835) );
AOI22X1TS U7194 ( .A0(FPSENCOS_cont_iter_out[0]), .A1(n6419), .B0(n6415),
.B1(n6713), .Y(n1834) );
AOI32X1TS U7195 ( .A0(n6418), .A1(n6597), .A2(n6417), .B0(n2240), .B1(n6713),
.Y(n6420) );
OAI22X1TS U7196 ( .A0(n6503), .A1(n6420), .B0(n6597), .B1(n6419), .Y(n1833)
);
INVX2TS U7197 ( .A(n6499), .Y(n6497) );
OAI2BB2XLTS U7198 ( .B0(n6503), .B1(n2198), .A0N(n6497), .A1N(region_flag[0]), .Y(n1831) );
OAI2BB2XLTS U7199 ( .B0(n6503), .B1(n6791), .A0N(n6497), .A1N(region_flag[1]), .Y(n1830) );
INVX2TS U7200 ( .A(n6421), .Y(n6424) );
AOI22X1TS U7201 ( .A0(n6424), .A1(n6423), .B0(n6464), .B1(n6422), .Y(n1828)
);
AOI32X1TS U7202 ( .A0(n6426), .A1(n6584), .A2(n6436), .B0(n6425), .B1(n6464),
.Y(n1827) );
OAI222X1TS U7203 ( .A0(n6429), .A1(n6428), .B0(n6427), .B1(n6449), .C0(n2228), .C1(n6430), .Y(n1825) );
OAI2BB1X1TS U7204 ( .A0N(FPSENCOS_d_ff3_LUT_out[22]), .A1N(n6445), .B0(n6430), .Y(n1824) );
OAI2BB1X1TS U7205 ( .A0N(FPSENCOS_d_ff3_LUT_out[20]), .A1N(n6445), .B0(n6440), .Y(n1822) );
OAI2BB1X1TS U7206 ( .A0N(FPSENCOS_d_ff3_LUT_out[19]), .A1N(n6445), .B0(n6430), .Y(n1821) );
OAI2BB1X1TS U7207 ( .A0N(n6584), .A1N(n6432), .B0(n6431), .Y(n6438) );
OAI2BB1X1TS U7208 ( .A0N(FPSENCOS_d_ff3_LUT_out[17]), .A1N(n6445), .B0(n6440), .Y(n1819) );
OAI2BB1X1TS U7209 ( .A0N(FPSENCOS_d_ff3_LUT_out[15]), .A1N(n6445), .B0(n6440), .Y(n1817) );
AOI32X1TS U7210 ( .A0(n6437), .A1(n6585), .A2(n6597), .B0(n6439), .B1(n6449),
.Y(n6444) );
OAI2BB1X1TS U7211 ( .A0N(FPSENCOS_d_ff3_LUT_out[14]), .A1N(n6445), .B0(n6444), .Y(n1816) );
BUFX3TS U7212 ( .A(n6472), .Y(n6469) );
BUFX3TS U7213 ( .A(n6558), .Y(n6562) );
NAND2X1TS U7214 ( .A(n6441), .B(n6440), .Y(n6443) );
OAI2BB2XLTS U7215 ( .B0(n6496), .B1(n6442), .A0N(n6469), .A1N(
FPSENCOS_d_ff3_LUT_out[8]), .Y(n1810) );
OAI2BB1X1TS U7216 ( .A0N(FPSENCOS_d_ff3_LUT_out[5]), .A1N(n6445), .B0(n6444),
.Y(n1807) );
AOI32X1TS U7217 ( .A0(n6450), .A1(n6449), .A2(n6448), .B0(n6447), .B1(n6464),
.Y(n1803) );
AOI22X1TS U7218 ( .A0(n6453), .A1(n6452), .B0(n6464), .B1(n6451), .Y(n1802)
);
OAI2BB2XLTS U7219 ( .B0(n6454), .B1(n2280), .A0N(FPSENCOS_d_ff_Xn[30]),
.A1N(n6596), .Y(n1800) );
AOI32X1TS U7220 ( .A0(FPSENCOS_sel_mux_1_reg), .A1(n6592), .A2(n6829), .B0(
n6708), .B1(n6471), .Y(n1799) );
AOI22X1TS U7221 ( .A0(n6485), .A1(n6810), .B0(n6665), .B1(n2279), .Y(n1798)
);
AOI22X1TS U7222 ( .A0(n6485), .A1(n6811), .B0(n6706), .B1(n6471), .Y(n1797)
);
AOI22X1TS U7223 ( .A0(n6485), .A1(n6812), .B0(n6709), .B1(n6471), .Y(n1796)
);
AOI22X1TS U7224 ( .A0(n6485), .A1(n6813), .B0(n6710), .B1(n6471), .Y(n1795)
);
AOI22X1TS U7225 ( .A0(n6485), .A1(n6814), .B0(n6687), .B1(n6471), .Y(n1794)
);
OAI2BB2XLTS U7226 ( .B0(n6795), .B1(n6592), .A0N(FPSENCOS_d_ff_Xn[23]),
.A1N(n6596), .Y(n1793) );
CMPR32X2TS U7227 ( .A(FPSENCOS_d_ff2_X[26]), .B(n6711), .C(n6455), .CO(n6457), .S(n6456) );
BUFX3TS U7228 ( .A(n6472), .Y(n6602) );
NOR2X1TS U7229 ( .A(FPSENCOS_d_ff2_X[27]), .B(n6457), .Y(n6459) );
AOI21X1TS U7230 ( .A0(n6457), .A1(FPSENCOS_d_ff2_X[27]), .B0(n6459), .Y(
n6458) );
AOI21X1TS U7231 ( .A0(FPSENCOS_d_ff2_X[29]), .A1(n6462), .B0(n6461), .Y(
n6463) );
OAI2BB2XLTS U7232 ( .B0(n6465), .B1(n6592), .A0N(FPSENCOS_d_ff_Xn[22]),
.A1N(n6494), .Y(n1784) );
BUFX3TS U7233 ( .A(n6464), .Y(n6490) );
OAI2BB2XLTS U7234 ( .B0(n6490), .B1(n6465), .A0N(n6469), .A1N(
FPSENCOS_d_ff3_sh_x_out[22]), .Y(n1783) );
OAI2BB2XLTS U7235 ( .B0(n6466), .B1(n2280), .A0N(FPSENCOS_d_ff_Xn[21]),
.A1N(n6494), .Y(n1782) );
OAI2BB2XLTS U7236 ( .B0(n6496), .B1(n6466), .A0N(n6469), .A1N(
FPSENCOS_d_ff3_sh_x_out[21]), .Y(n1781) );
AOI22X1TS U7237 ( .A0(n6485), .A1(n6815), .B0(n6467), .B1(n6471), .Y(n1780)
);
OAI2BB2XLTS U7238 ( .B0(n6490), .B1(n6467), .A0N(n6469), .A1N(
FPSENCOS_d_ff3_sh_x_out[20]), .Y(n1779) );
AOI22X1TS U7239 ( .A0(n6492), .A1(n6816), .B0(n6468), .B1(n6471), .Y(n1778)
);
OAI2BB2XLTS U7240 ( .B0(n6490), .B1(n6468), .A0N(n6469), .A1N(
FPSENCOS_d_ff3_sh_x_out[19]), .Y(n1777) );
OAI2BB2XLTS U7241 ( .B0(n6470), .B1(n2280), .A0N(FPSENCOS_d_ff_Xn[18]),
.A1N(n6494), .Y(n1776) );
OAI2BB2XLTS U7242 ( .B0(n6496), .B1(n6470), .A0N(n6469), .A1N(
FPSENCOS_d_ff3_sh_x_out[18]), .Y(n1775) );
AOI22X1TS U7243 ( .A0(n6485), .A1(n6817), .B0(n6473), .B1(n6471), .Y(n1774)
);
OAI2BB2XLTS U7244 ( .B0(n6490), .B1(n6473), .A0N(n2831), .A1N(
FPSENCOS_d_ff3_sh_x_out[17]), .Y(n1773) );
AOI22X1TS U7245 ( .A0(n6492), .A1(n6818), .B0(n6474), .B1(n6588), .Y(n1772)
);
OAI2BB2XLTS U7246 ( .B0(n6496), .B1(n6474), .A0N(n2831), .A1N(
FPSENCOS_d_ff3_sh_x_out[16]), .Y(n1771) );
OAI2BB2XLTS U7247 ( .B0(n6475), .B1(n2280), .A0N(FPSENCOS_d_ff_Xn[15]),
.A1N(n6494), .Y(n1770) );
OAI2BB2XLTS U7248 ( .B0(n6496), .B1(n6475), .A0N(n6472), .A1N(
FPSENCOS_d_ff3_sh_x_out[15]), .Y(n1769) );
BUFX3TS U7249 ( .A(n5428), .Y(n6491) );
AOI22X1TS U7250 ( .A0(n6485), .A1(n6819), .B0(n6476), .B1(n6491), .Y(n1768)
);
OAI2BB2XLTS U7251 ( .B0(n6490), .B1(n6476), .A0N(n2831), .A1N(
FPSENCOS_d_ff3_sh_x_out[14]), .Y(n1767) );
AOI22X1TS U7252 ( .A0(n6492), .A1(n6820), .B0(n6477), .B1(n6491), .Y(n1766)
);
OAI2BB2XLTS U7253 ( .B0(n6490), .B1(n6477), .A0N(n2831), .A1N(
FPSENCOS_d_ff3_sh_x_out[13]), .Y(n1765) );
AOI22X1TS U7254 ( .A0(n6492), .A1(n6821), .B0(n6478), .B1(n6491), .Y(n1764)
);
OAI2BB2XLTS U7255 ( .B0(n6490), .B1(n6478), .A0N(n2831), .A1N(
FPSENCOS_d_ff3_sh_x_out[12]), .Y(n1763) );
OAI2BB2XLTS U7256 ( .B0(n6479), .B1(n2280), .A0N(FPSENCOS_d_ff_Xn[11]),
.A1N(n6494), .Y(n1762) );
OAI2BB2XLTS U7257 ( .B0(n6490), .B1(n6479), .A0N(n6472), .A1N(
FPSENCOS_d_ff3_sh_x_out[11]), .Y(n1761) );
AOI22X1TS U7258 ( .A0(n6492), .A1(n6822), .B0(n6480), .B1(n6491), .Y(n1760)
);
OAI2BB2XLTS U7259 ( .B0(n6562), .B1(n6480), .A0N(n2831), .A1N(
FPSENCOS_d_ff3_sh_x_out[10]), .Y(n1759) );
OAI2BB2XLTS U7260 ( .B0(n6481), .B1(n2280), .A0N(FPSENCOS_d_ff_Xn[9]), .A1N(
n6494), .Y(n1758) );
OAI2BB2XLTS U7261 ( .B0(n6490), .B1(n6481), .A0N(n2831), .A1N(
FPSENCOS_d_ff3_sh_x_out[9]), .Y(n1757) );
OAI2BB2XLTS U7262 ( .B0(n6482), .B1(n6592), .A0N(FPSENCOS_d_ff_Xn[8]), .A1N(
n6494), .Y(n1756) );
OAI2BB2XLTS U7263 ( .B0(n6562), .B1(n6482), .A0N(n6602), .A1N(
FPSENCOS_d_ff3_sh_x_out[8]), .Y(n1755) );
AOI22X1TS U7264 ( .A0(n6492), .A1(n6823), .B0(n6483), .B1(n6491), .Y(n1754)
);
OAI2BB2XLTS U7265 ( .B0(n6562), .B1(n6483), .A0N(n6602), .A1N(
FPSENCOS_d_ff3_sh_x_out[7]), .Y(n1753) );
AOI22X1TS U7266 ( .A0(n6485), .A1(n6824), .B0(n6484), .B1(n6491), .Y(n1752)
);
OAI2BB2XLTS U7267 ( .B0(n6562), .B1(n6484), .A0N(n2831), .A1N(
FPSENCOS_d_ff3_sh_x_out[6]), .Y(n1751) );
AOI22X1TS U7268 ( .A0(n6485), .A1(n6825), .B0(n6486), .B1(n6491), .Y(n1750)
);
OAI2BB2XLTS U7269 ( .B0(n6562), .B1(n6486), .A0N(n6602), .A1N(
FPSENCOS_d_ff3_sh_x_out[5]), .Y(n1749) );
OAI2BB2XLTS U7270 ( .B0(n6487), .B1(n2280), .A0N(FPSENCOS_d_ff_Xn[4]), .A1N(
n6494), .Y(n1748) );
OAI2BB2XLTS U7271 ( .B0(n6562), .B1(n6487), .A0N(n6602), .A1N(
FPSENCOS_d_ff3_sh_x_out[4]), .Y(n1747) );
AOI22X1TS U7272 ( .A0(n6492), .A1(n6826), .B0(n6488), .B1(n6491), .Y(n1746)
);
OAI2BB2XLTS U7273 ( .B0(n6562), .B1(n6488), .A0N(n6602), .A1N(
FPSENCOS_d_ff3_sh_x_out[3]), .Y(n1745) );
AOI22X1TS U7274 ( .A0(n6492), .A1(n6827), .B0(n6489), .B1(n6491), .Y(n1744)
);
OAI2BB2XLTS U7275 ( .B0(n6490), .B1(n6489), .A0N(n6602), .A1N(
FPSENCOS_d_ff3_sh_x_out[2]), .Y(n1743) );
AOI22X1TS U7276 ( .A0(n6492), .A1(n6828), .B0(n6493), .B1(n6491), .Y(n1742)
);
OAI2BB2XLTS U7277 ( .B0(n6496), .B1(n6493), .A0N(n6602), .A1N(
FPSENCOS_d_ff3_sh_x_out[1]), .Y(n1741) );
OAI2BB2XLTS U7278 ( .B0(n6495), .B1(n6592), .A0N(FPSENCOS_d_ff_Xn[0]), .A1N(
n6494), .Y(n1740) );
OAI2BB2XLTS U7279 ( .B0(n6496), .B1(n6495), .A0N(n6602), .A1N(
FPSENCOS_d_ff3_sh_x_out[0]), .Y(n1739) );
INVX2TS U7280 ( .A(n6499), .Y(n6501) );
BUFX3TS U7281 ( .A(n6499), .Y(n6500) );
INVX2TS U7282 ( .A(n6499), .Y(n6505) );
BUFX3TS U7283 ( .A(n6499), .Y(n6502) );
OR2X2TS U7284 ( .A(n6507), .B(n6506), .Y(n6528) );
BUFX3TS U7285 ( .A(n6508), .Y(n6531) );
OAI22X1TS U7286 ( .A0(n6531), .A1(n6780), .B0(n6527), .B1(n6615), .Y(n1701)
);
AOI21X1TS U7287 ( .A0(n6773), .A1(FPADDSUB_Add_Subt_result[20]), .B0(
FPADDSUB_Add_Subt_result[22]), .Y(n6509) );
INVX2TS U7288 ( .A(n2833), .Y(n6525) );
OA22X1TS U7289 ( .A0(n6525), .A1(result_add_subt[30]), .B0(
FPADDSUB_exp_oper_result[7]), .B1(n2305), .Y(n1631) );
OAI22X1TS U7290 ( .A0(n6531), .A1(n6705), .B0(n6527), .B1(n6831), .Y(n1629)
);
OAI2BB2XLTS U7291 ( .B0(n6543), .B1(n6705), .A0N(n6618), .A1N(
FPSENCOS_d_ff_Xn[30]), .Y(n1628) );
OA22X1TS U7292 ( .A0(n6525), .A1(result_add_subt[29]), .B0(
FPADDSUB_exp_oper_result[6]), .B1(n6535), .Y(n1627) );
BUFX3TS U7293 ( .A(n6526), .Y(n6546) );
OAI2BB2XLTS U7294 ( .B0(n6529), .B1(n6699), .A0N(n6546), .A1N(
FPSENCOS_d_ff_Zn[29]), .Y(n1626) );
OAI22X1TS U7295 ( .A0(n6531), .A1(n6699), .B0(n6527), .B1(n6594), .Y(n1625)
);
BUFX3TS U7296 ( .A(n6618), .Y(n6552) );
OAI22X1TS U7297 ( .A0(n6552), .A1(n6699), .B0(n2343), .B1(n6829), .Y(n1624)
);
OA22X1TS U7298 ( .A0(n6532), .A1(result_add_subt[28]), .B0(
FPADDSUB_exp_oper_result[5]), .B1(n2305), .Y(n1623) );
OAI2BB2XLTS U7299 ( .B0(n5051), .B1(n6700), .A0N(n6546), .A1N(
FPSENCOS_d_ff_Zn[28]), .Y(n1622) );
OAI22X1TS U7300 ( .A0(n6508), .A1(n6700), .B0(n6527), .B1(n6591), .Y(n1621)
);
OAI22X1TS U7301 ( .A0(n6552), .A1(n6700), .B0(n2342), .B1(n6810), .Y(n1620)
);
OA22X1TS U7302 ( .A0(n6532), .A1(result_add_subt[27]), .B0(
FPADDSUB_exp_oper_result[4]), .B1(n2304), .Y(n1619) );
OAI2BB2XLTS U7303 ( .B0(n5051), .B1(n6701), .A0N(n6546), .A1N(
FPSENCOS_d_ff_Zn[27]), .Y(n1618) );
OAI22X1TS U7304 ( .A0(n6528), .A1(n6701), .B0(n6527), .B1(n6830), .Y(n1617)
);
OAI22X1TS U7305 ( .A0(n6552), .A1(n6701), .B0(n2343), .B1(n6811), .Y(n1616)
);
OA22X1TS U7306 ( .A0(n6209), .A1(result_add_subt[26]), .B0(
FPADDSUB_exp_oper_result[3]), .B1(n2305), .Y(n1615) );
BUFX3TS U7307 ( .A(n6526), .Y(n6537) );
OAI2BB2XLTS U7308 ( .B0(n5051), .B1(n6702), .A0N(n6537), .A1N(
FPSENCOS_d_ff_Zn[26]), .Y(n1614) );
OAI22X1TS U7309 ( .A0(n6508), .A1(n6702), .B0(n6527), .B1(n6590), .Y(n1613)
);
OAI22X1TS U7310 ( .A0(n6552), .A1(n6702), .B0(n2342), .B1(n6812), .Y(n1612)
);
OA22X1TS U7311 ( .A0(n6532), .A1(result_add_subt[25]), .B0(
FPADDSUB_exp_oper_result[2]), .B1(n6535), .Y(n1611) );
OAI2BB2XLTS U7312 ( .B0(n6526), .B1(n6703), .A0N(n6537), .A1N(
FPSENCOS_d_ff_Zn[25]), .Y(n1610) );
OAI22X1TS U7313 ( .A0(n6508), .A1(n6703), .B0(n6527), .B1(n6589), .Y(n1609)
);
OAI22X1TS U7314 ( .A0(n6552), .A1(n6703), .B0(n2343), .B1(n6813), .Y(n1608)
);
OA22X1TS U7315 ( .A0(n6209), .A1(result_add_subt[24]), .B0(
FPADDSUB_exp_oper_result[1]), .B1(n6535), .Y(n1607) );
OAI2BB2XLTS U7316 ( .B0(n6526), .B1(n6704), .A0N(n6537), .A1N(
FPSENCOS_d_ff_Zn[24]), .Y(n1606) );
OAI22X1TS U7317 ( .A0(n6508), .A1(n6704), .B0(n6527), .B1(n6587), .Y(n1605)
);
OAI22X1TS U7318 ( .A0(n6552), .A1(n6704), .B0(n2342), .B1(n6814), .Y(n1604)
);
OA22X1TS U7319 ( .A0(n6209), .A1(result_add_subt[23]), .B0(
FPADDSUB_exp_oper_result[0]), .B1(n2305), .Y(n1603) );
OAI2BB2XLTS U7320 ( .B0(n6526), .B1(n6781), .A0N(n6529), .A1N(
FPSENCOS_d_ff_Zn[23]), .Y(n1602) );
OAI22X1TS U7321 ( .A0(n6508), .A1(n6781), .B0(n6527), .B1(n6586), .Y(n1601)
);
BUFX3TS U7322 ( .A(n6618), .Y(n6620) );
OAI2BB2XLTS U7323 ( .B0(n6620), .B1(n6781), .A0N(n6618), .A1N(
FPSENCOS_d_ff_Xn[23]), .Y(n1600) );
OAI22X1TS U7324 ( .A0(n2304), .A1(n6690), .B0(n6775), .B1(n6525), .Y(n1599)
);
OAI2BB2XLTS U7325 ( .B0(n6526), .B1(n6775), .A0N(n6537), .A1N(
FPSENCOS_d_ff_Zn[22]), .Y(n1598) );
OAI22X1TS U7326 ( .A0(n6508), .A1(n6775), .B0(n6527), .B1(n6583), .Y(n1597)
);
OAI2BB2XLTS U7327 ( .B0(n6620), .B1(n6775), .A0N(n6543), .A1N(
FPSENCOS_d_ff_Xn[22]), .Y(n1596) );
OAI22X1TS U7328 ( .A0(n2304), .A1(n6689), .B0(n6776), .B1(n6532), .Y(n1595)
);
OAI2BB2XLTS U7329 ( .B0(n6526), .B1(n6776), .A0N(n6529), .A1N(
FPSENCOS_d_ff_Zn[21]), .Y(n1594) );
OAI22X1TS U7330 ( .A0(n6550), .A1(n6776), .B0(n6548), .B1(n6582), .Y(n1593)
);
OAI2BB2XLTS U7331 ( .B0(n6620), .B1(n6776), .A0N(n6543), .A1N(
FPSENCOS_d_ff_Xn[21]), .Y(n1592) );
OAI22X1TS U7332 ( .A0(n2305), .A1(n6767), .B0(n6691), .B1(n6209), .Y(n1591)
);
OAI2BB2XLTS U7333 ( .B0(n6533), .B1(n6691), .A0N(n6529), .A1N(
FPSENCOS_d_ff_Zn[20]), .Y(n1590) );
OAI22X1TS U7334 ( .A0(n6550), .A1(n6691), .B0(n6548), .B1(n6580), .Y(n1589)
);
BUFX3TS U7335 ( .A(n6618), .Y(n6542) );
OAI22X1TS U7336 ( .A0(n6542), .A1(n6691), .B0(n2343), .B1(n6815), .Y(n1588)
);
OAI22X1TS U7337 ( .A0(n6535), .A1(n6768), .B0(n6692), .B1(n6532), .Y(n1587)
);
OAI2BB2XLTS U7338 ( .B0(n6533), .B1(n6692), .A0N(n6529), .A1N(
FPSENCOS_d_ff_Zn[19]), .Y(n1586) );
OAI22X1TS U7339 ( .A0(n6508), .A1(n6692), .B0(n6548), .B1(n6579), .Y(n1585)
);
OAI22X1TS U7340 ( .A0(n6542), .A1(n6692), .B0(n2342), .B1(n6816), .Y(n1584)
);
OAI22X1TS U7341 ( .A0(n2305), .A1(n6686), .B0(n6777), .B1(n6525), .Y(n1583)
);
OAI2BB2XLTS U7342 ( .B0(n6533), .B1(n6777), .A0N(n6529), .A1N(
FPSENCOS_d_ff_Zn[18]), .Y(n1582) );
OAI22X1TS U7343 ( .A0(n6531), .A1(n6777), .B0(n6548), .B1(n6578), .Y(n1581)
);
OAI2BB2XLTS U7344 ( .B0(n6620), .B1(n6777), .A0N(n6543), .A1N(
FPSENCOS_d_ff_Xn[18]), .Y(n1580) );
OAI22X1TS U7345 ( .A0(n6535), .A1(n6758), .B0(n6693), .B1(n6209), .Y(n1579)
);
OAI2BB2XLTS U7346 ( .B0(n6533), .B1(n6693), .A0N(n6529), .A1N(
FPSENCOS_d_ff_Zn[17]), .Y(n1578) );
OAI22X1TS U7347 ( .A0(n6531), .A1(n6693), .B0(n6548), .B1(n6576), .Y(n1577)
);
OAI22X1TS U7348 ( .A0(n6542), .A1(n6693), .B0(n2343), .B1(n6817), .Y(n1576)
);
OAI22X1TS U7349 ( .A0(n2305), .A1(n6759), .B0(n6694), .B1(n6532), .Y(n1575)
);
OAI2BB2XLTS U7350 ( .B0(n5051), .B1(n6694), .A0N(n6537), .A1N(
FPSENCOS_d_ff_Zn[16]), .Y(n1574) );
OAI22X1TS U7351 ( .A0(n6531), .A1(n6694), .B0(n6548), .B1(n6575), .Y(n1573)
);
OAI22X1TS U7352 ( .A0(n6542), .A1(n6694), .B0(n2342), .B1(n6818), .Y(n1572)
);
OAI22X1TS U7353 ( .A0(n6675), .A1(n6535), .B0(n6778), .B1(n6532), .Y(n1571)
);
OAI2BB2XLTS U7354 ( .B0(n6533), .B1(n6778), .A0N(n6529), .A1N(
FPSENCOS_d_ff_Zn[15]), .Y(n1570) );
OAI22X1TS U7355 ( .A0(n6531), .A1(n6778), .B0(n6548), .B1(n6573), .Y(n1569)
);
OAI2BB2XLTS U7356 ( .B0(n6620), .B1(n6778), .A0N(n6543), .A1N(
FPSENCOS_d_ff_Xn[15]), .Y(n1568) );
OAI22X1TS U7357 ( .A0(n6734), .A1(n2305), .B0(n6695), .B1(n6525), .Y(n1567)
);
OAI2BB2XLTS U7358 ( .B0(n6533), .B1(n6695), .A0N(n6529), .A1N(
FPSENCOS_d_ff_Zn[14]), .Y(n1566) );
OAI22X1TS U7359 ( .A0(n6531), .A1(n6695), .B0(n6548), .B1(n6572), .Y(n1565)
);
OAI22X1TS U7360 ( .A0(n6552), .A1(n6695), .B0(n2343), .B1(n6819), .Y(n1564)
);
OAI22X1TS U7361 ( .A0(n6735), .A1(n6535), .B0(n6696), .B1(n6209), .Y(n1563)
);
OAI2BB2XLTS U7362 ( .B0(n6533), .B1(n6696), .A0N(n6537), .A1N(
FPSENCOS_d_ff_Zn[13]), .Y(n1562) );
OAI22X1TS U7363 ( .A0(n6531), .A1(n6696), .B0(n6553), .B1(n6571), .Y(n1561)
);
OAI22X1TS U7364 ( .A0(n6542), .A1(n6696), .B0(n2342), .B1(n6820), .Y(n1560)
);
OAI22X1TS U7365 ( .A0(n6717), .A1(n2305), .B0(n6697), .B1(n6532), .Y(n1559)
);
OAI2BB2XLTS U7366 ( .B0(n6533), .B1(n6697), .A0N(n6537), .A1N(
FPSENCOS_d_ff_Zn[12]), .Y(n1558) );
OAI22X1TS U7367 ( .A0(n6531), .A1(n6697), .B0(n6530), .B1(n6570), .Y(n1557)
);
OAI22X1TS U7368 ( .A0(n6542), .A1(n6697), .B0(n2343), .B1(n6821), .Y(n1556)
);
OAI22X1TS U7369 ( .A0(n6676), .A1(n6535), .B0(n6779), .B1(n6532), .Y(n1555)
);
OAI2BB2XLTS U7370 ( .B0(n6533), .B1(n6779), .A0N(n6537), .A1N(
FPSENCOS_d_ff_Zn[11]), .Y(n1554) );
OAI22X1TS U7371 ( .A0(n6550), .A1(n6779), .B0(n6553), .B1(n6569), .Y(n1553)
);
OAI2BB2XLTS U7372 ( .B0(n6620), .B1(n6779), .A0N(n6543), .A1N(
FPSENCOS_d_ff_Xn[11]), .Y(n1552) );
OAI22X1TS U7373 ( .A0(n6718), .A1(n2305), .B0(n6698), .B1(n6532), .Y(n1551)
);
OAI2BB2XLTS U7374 ( .B0(n6547), .B1(n6698), .A0N(n6546), .A1N(
FPSENCOS_d_ff_Zn[10]), .Y(n1550) );
OAI22X1TS U7375 ( .A0(n6550), .A1(n6698), .B0(n6553), .B1(n6568), .Y(n1549)
);
OAI22X1TS U7376 ( .A0(n6542), .A1(n6698), .B0(n2342), .B1(n6822), .Y(n1548)
);
OAI2BB2XLTS U7377 ( .B0(n6547), .B1(n6536), .A0N(n6537), .A1N(
FPSENCOS_d_ff_Zn[9]), .Y(n1546) );
OAI22X1TS U7378 ( .A0(n6550), .A1(n6536), .B0(n6530), .B1(n6567), .Y(n1545)
);
OAI2BB2XLTS U7379 ( .B0(n6620), .B1(n6536), .A0N(n6543), .A1N(
FPSENCOS_d_ff_Xn[9]), .Y(n1544) );
OAI2BB2XLTS U7380 ( .B0(n6547), .B1(n6538), .A0N(n6537), .A1N(
FPSENCOS_d_ff_Zn[8]), .Y(n1542) );
OAI22X1TS U7381 ( .A0(n6508), .A1(n6538), .B0(n6553), .B1(n6566), .Y(n1541)
);
OAI2BB2XLTS U7382 ( .B0(n6620), .B1(n6538), .A0N(n6543), .A1N(
FPSENCOS_d_ff_Xn[8]), .Y(n1540) );
OAI2BB2XLTS U7383 ( .B0(n6547), .B1(n6539), .A0N(n6546), .A1N(
FPSENCOS_d_ff_Zn[7]), .Y(n1538) );
OAI22X1TS U7384 ( .A0(n6528), .A1(n6539), .B0(n6530), .B1(n6565), .Y(n1537)
);
OAI22X1TS U7385 ( .A0(n6542), .A1(n6539), .B0(n2343), .B1(n6823), .Y(n1536)
);
OAI2BB2XLTS U7386 ( .B0(n6547), .B1(n6540), .A0N(n6546), .A1N(
FPSENCOS_d_ff_Zn[6]), .Y(n1534) );
OAI22X1TS U7387 ( .A0(n6528), .A1(n6540), .B0(n6553), .B1(n6561), .Y(n1533)
);
OAI22X1TS U7388 ( .A0(n6542), .A1(n6540), .B0(n2342), .B1(n6824), .Y(n1532)
);
OAI2BB2XLTS U7389 ( .B0(n6547), .B1(n6541), .A0N(n6546), .A1N(
FPSENCOS_d_ff_Zn[5]), .Y(n1530) );
OAI22X1TS U7390 ( .A0(n6528), .A1(n6541), .B0(n6530), .B1(n6560), .Y(n1529)
);
OAI22X1TS U7391 ( .A0(n6542), .A1(n6541), .B0(n2343), .B1(n6825), .Y(n1528)
);
OAI2BB2XLTS U7392 ( .B0(n6547), .B1(n6544), .A0N(n6546), .A1N(
FPSENCOS_d_ff_Zn[4]), .Y(n1526) );
OAI22X1TS U7393 ( .A0(n6528), .A1(n6544), .B0(n6553), .B1(n6559), .Y(n1525)
);
OAI2BB2XLTS U7394 ( .B0(n6620), .B1(n6544), .A0N(n6543), .A1N(
FPSENCOS_d_ff_Xn[4]), .Y(n1524) );
OAI2BB2XLTS U7395 ( .B0(n6547), .B1(n6545), .A0N(n6546), .A1N(
FPSENCOS_d_ff_Zn[3]), .Y(n1522) );
OAI22X1TS U7396 ( .A0(n6528), .A1(n6545), .B0(n6530), .B1(n6557), .Y(n1521)
);
OAI22X1TS U7397 ( .A0(n6552), .A1(n6545), .B0(n2342), .B1(n6826), .Y(n1520)
);
OAI2BB2XLTS U7398 ( .B0(n6547), .B1(n6549), .A0N(n6546), .A1N(
FPSENCOS_d_ff_Zn[2]), .Y(n1518) );
OAI22X1TS U7399 ( .A0(n6528), .A1(n6549), .B0(n6553), .B1(n6556), .Y(n1517)
);
OAI22X1TS U7400 ( .A0(n6552), .A1(n6549), .B0(n2343), .B1(n6827), .Y(n1516)
);
OAI22X1TS U7401 ( .A0(n6550), .A1(n6551), .B0(n6530), .B1(n6555), .Y(n1513)
);
OAI22X1TS U7402 ( .A0(n6552), .A1(n6551), .B0(n2342), .B1(n6828), .Y(n1512)
);
OAI22X1TS U7403 ( .A0(n6550), .A1(n6619), .B0(n6553), .B1(n6554), .Y(n1476)
);
OAI2BB2XLTS U7404 ( .B0(n6554), .B1(n6593), .A0N(FPSENCOS_d_ff2_Y[0]), .A1N(
n6613), .Y(n1475) );
OAI2BB2XLTS U7405 ( .B0(n6555), .B1(n6564), .A0N(FPSENCOS_d_ff2_Y[1]), .A1N(
n6613), .Y(n1473) );
OAI2BB2XLTS U7406 ( .B0(n6556), .B1(n6564), .A0N(FPSENCOS_d_ff2_Y[2]), .A1N(
n6613), .Y(n1471) );
OAI2BB2XLTS U7407 ( .B0(n6563), .B1(n6836), .A0N(n6585), .A1N(
FPSENCOS_d_ff2_Y[2]), .Y(n1470) );
OAI2BB2XLTS U7408 ( .B0(n6557), .B1(n6564), .A0N(FPSENCOS_d_ff2_Y[3]), .A1N(
n6613), .Y(n1469) );
INVX2TS U7409 ( .A(n6558), .Y(n6577) );
OAI2BB2XLTS U7410 ( .B0(n6577), .B1(n6834), .A0N(n6581), .A1N(
FPSENCOS_d_ff2_Y[3]), .Y(n1468) );
OAI2BB2XLTS U7411 ( .B0(n6559), .B1(n6564), .A0N(FPSENCOS_d_ff2_Y[4]), .A1N(
n6613), .Y(n1467) );
OAI2BB2XLTS U7412 ( .B0(n6577), .B1(n6844), .A0N(n6612), .A1N(
FPSENCOS_d_ff2_Y[4]), .Y(n1466) );
OAI2BB2XLTS U7413 ( .B0(n6560), .B1(n6564), .A0N(FPSENCOS_d_ff2_Y[5]), .A1N(
n6613), .Y(n1465) );
OAI2BB2XLTS U7414 ( .B0(n6577), .B1(n6842), .A0N(n6584), .A1N(
FPSENCOS_d_ff2_Y[5]), .Y(n1464) );
OAI2BB2XLTS U7415 ( .B0(n6561), .B1(n6564), .A0N(FPSENCOS_d_ff2_Y[6]), .A1N(
n6613), .Y(n1463) );
BUFX3TS U7416 ( .A(n2279), .Y(n6574) );
OAI2BB2XLTS U7417 ( .B0(n6565), .B1(n6564), .A0N(FPSENCOS_d_ff2_Y[7]), .A1N(
n6574), .Y(n1461) );
OAI2BB2XLTS U7418 ( .B0(n6577), .B1(n6848), .A0N(n6612), .A1N(
FPSENCOS_d_ff2_Y[7]), .Y(n1460) );
OAI2BB2XLTS U7419 ( .B0(n6566), .B1(n6593), .A0N(FPSENCOS_d_ff2_Y[8]), .A1N(
n6574), .Y(n1459) );
OAI2BB2XLTS U7420 ( .B0(n6577), .B1(n6839), .A0N(n6612), .A1N(
FPSENCOS_d_ff2_Y[8]), .Y(n1458) );
OAI2BB2XLTS U7421 ( .B0(n6567), .B1(n5870), .A0N(FPSENCOS_d_ff2_Y[9]), .A1N(
n6574), .Y(n1457) );
OAI2BB2XLTS U7422 ( .B0(n6577), .B1(n6851), .A0N(n6612), .A1N(
FPSENCOS_d_ff2_Y[9]), .Y(n1456) );
OAI2BB2XLTS U7423 ( .B0(n6568), .B1(n5870), .A0N(FPSENCOS_d_ff2_Y[10]),
.A1N(n6574), .Y(n1455) );
OAI2BB2XLTS U7424 ( .B0(n6577), .B1(n6846), .A0N(n6581), .A1N(
FPSENCOS_d_ff2_Y[10]), .Y(n1454) );
OAI2BB2XLTS U7425 ( .B0(n6569), .B1(n5433), .A0N(FPSENCOS_d_ff2_Y[11]),
.A1N(n6574), .Y(n1453) );
OAI2BB2XLTS U7426 ( .B0(n6577), .B1(n6849), .A0N(n6581), .A1N(
FPSENCOS_d_ff2_Y[11]), .Y(n1452) );
OAI2BB2XLTS U7427 ( .B0(n6570), .B1(n5870), .A0N(FPSENCOS_d_ff2_Y[12]),
.A1N(n6574), .Y(n1451) );
OAI2BB2XLTS U7428 ( .B0(n6584), .B1(n6850), .A0N(n6581), .A1N(
FPSENCOS_d_ff2_Y[12]), .Y(n1450) );
OAI2BB2XLTS U7429 ( .B0(n6571), .B1(n5870), .A0N(FPSENCOS_d_ff2_Y[13]),
.A1N(n6574), .Y(n1449) );
OAI2BB2XLTS U7430 ( .B0(n6449), .B1(n6841), .A0N(n6581), .A1N(
FPSENCOS_d_ff2_Y[13]), .Y(n1448) );
BUFX3TS U7431 ( .A(n5870), .Y(n6614) );
OAI2BB2XLTS U7432 ( .B0(n6572), .B1(n6614), .A0N(FPSENCOS_d_ff2_Y[14]),
.A1N(n6574), .Y(n1447) );
OAI2BB2XLTS U7433 ( .B0(n6577), .B1(n6847), .A0N(n6449), .A1N(
FPSENCOS_d_ff2_Y[14]), .Y(n1446) );
OAI2BB2XLTS U7434 ( .B0(n6573), .B1(n6614), .A0N(FPSENCOS_d_ff2_Y[15]),
.A1N(n6574), .Y(n1445) );
OAI2BB2XLTS U7435 ( .B0(n6585), .B1(n6838), .A0N(n6581), .A1N(
FPSENCOS_d_ff2_Y[15]), .Y(n1444) );
OAI2BB2XLTS U7436 ( .B0(n6575), .B1(n6614), .A0N(FPSENCOS_d_ff2_Y[16]),
.A1N(n6574), .Y(n1443) );
OAI2BB2XLTS U7437 ( .B0(n6584), .B1(n6845), .A0N(n6581), .A1N(
FPSENCOS_d_ff2_Y[16]), .Y(n1442) );
OAI2BB2XLTS U7438 ( .B0(n6576), .B1(n6614), .A0N(FPSENCOS_d_ff2_Y[17]),
.A1N(n6595), .Y(n1441) );
OAI2BB2XLTS U7439 ( .B0(n6577), .B1(n6843), .A0N(n6585), .A1N(
FPSENCOS_d_ff2_Y[17]), .Y(n1440) );
OAI2BB2XLTS U7440 ( .B0(n6578), .B1(n6614), .A0N(FPSENCOS_d_ff2_Y[18]),
.A1N(n6588), .Y(n1439) );
OAI2BB2XLTS U7441 ( .B0(n6449), .B1(n6837), .A0N(n6581), .A1N(
FPSENCOS_d_ff2_Y[18]), .Y(n1438) );
OAI2BB2XLTS U7442 ( .B0(n6579), .B1(n6614), .A0N(FPSENCOS_d_ff2_Y[19]),
.A1N(n6588), .Y(n1437) );
OAI2BB2XLTS U7443 ( .B0(n6585), .B1(n6835), .A0N(n6581), .A1N(
FPSENCOS_d_ff2_Y[19]), .Y(n1436) );
OAI2BB2XLTS U7444 ( .B0(n6580), .B1(n6614), .A0N(FPSENCOS_d_ff2_Y[20]),
.A1N(n6588), .Y(n1435) );
OAI2BB2XLTS U7445 ( .B0(n6584), .B1(n6840), .A0N(n6581), .A1N(
FPSENCOS_d_ff2_Y[20]), .Y(n1434) );
OAI2BB2XLTS U7446 ( .B0(n6582), .B1(n6614), .A0N(FPSENCOS_d_ff2_Y[21]),
.A1N(n6588), .Y(n1433) );
OAI2BB2XLTS U7447 ( .B0(n6583), .B1(n6614), .A0N(FPSENCOS_d_ff2_Y[22]),
.A1N(n6588), .Y(n1431) );
OAI2BB2XLTS U7448 ( .B0(n6449), .B1(n6833), .A0N(n6584), .A1N(
FPSENCOS_d_ff2_Y[22]), .Y(n1430) );
OAI22X1TS U7449 ( .A0(n6592), .A1(n6809), .B0(n6586), .B1(n6593), .Y(n1429)
);
OAI22X1TS U7450 ( .A0(n2280), .A1(n6750), .B0(n6587), .B1(n6593), .Y(n1428)
);
OAI2BB2XLTS U7451 ( .B0(n6589), .B1(n6593), .A0N(FPSENCOS_d_ff2_Y[25]),
.A1N(n6588), .Y(n1427) );
OAI2BB2XLTS U7452 ( .B0(n6590), .B1(n6593), .A0N(FPSENCOS_d_ff2_Y[26]),
.A1N(n6595), .Y(n1426) );
OAI22X1TS U7453 ( .A0(n2280), .A1(n6796), .B0(n6591), .B1(n6593), .Y(n1424)
);
OAI2BB2XLTS U7454 ( .B0(n6594), .B1(n6593), .A0N(n6595), .A1N(
FPSENCOS_d_ff2_Y[29]), .Y(n1423) );
AOI22X1TS U7455 ( .A0(n2240), .A1(n6750), .B0(FPSENCOS_d_ff2_Y[24]), .B1(
n6597), .Y(n6598) );
XNOR2X1TS U7456 ( .A(n6599), .B(n6598), .Y(n6600) );
AOI21X1TS U7457 ( .A0(n6605), .A1(FPSENCOS_d_ff2_Y[27]), .B0(n6604), .Y(
n6606) );
NOR2X1TS U7458 ( .A(FPSENCOS_d_ff2_Y[29]), .B(n6607), .Y(n6610) );
AOI21X1TS U7459 ( .A0(FPSENCOS_d_ff2_Y[29]), .A1(n6607), .B0(n6610), .Y(
n6608) );
XOR2X1TS U7460 ( .A(FPSENCOS_d_ff2_Y[30]), .B(n6610), .Y(n6611) );
OAI2BB2XLTS U7461 ( .B0(n6615), .B1(n6614), .A0N(FPSENCOS_d_ff2_Y[31]),
.A1N(n6613), .Y(n1413) );
OAI2BB2XLTS U7462 ( .B0(n6620), .B1(n6619), .A0N(n6618), .A1N(
FPSENCOS_d_ff_Xn[0]), .Y(n1411) );
BUFX3TS U7463 ( .A(n6625), .Y(n6622) );
INVX2TS U7464 ( .A(n6622), .Y(n6621) );
INVX2TS U7465 ( .A(n6624), .Y(n6623) );
INVX2TS U7466 ( .A(n6624), .Y(n6627) );
AOI22X1TS U7467 ( .A0(FPSENCOS_d_ff3_sh_y_out[30]), .A1(n6639), .B0(n5098),
.B1(Data_2[30]), .Y(n6630) );
AOI22X1TS U7468 ( .A0(FPADDSUB_intDY[30]), .A1(n6637), .B0(
FPSENCOS_d_ff3_sh_x_out[30]), .B1(n6638), .Y(n6629) );
NAND2X1TS U7469 ( .A(n6630), .B(n6629), .Y(n1341) );
AOI22X1TS U7470 ( .A0(FPADDSUB_intDY[29]), .A1(n6637), .B0(n6631), .B1(
Data_2[29]), .Y(n6634) );
AOI22X1TS U7471 ( .A0(n2266), .A1(FPSENCOS_d_ff3_sh_y_out[29]), .B0(n6638),
.B1(FPSENCOS_d_ff3_sh_x_out[29]), .Y(n6633) );
NAND2X1TS U7472 ( .A(n5371), .B(FPSENCOS_d_ff3_LUT_out[27]), .Y(n6640) );
AOI22X1TS U7473 ( .A0(FPADDSUB_intDY[28]), .A1(n6637), .B0(n5098), .B1(
Data_2[28]), .Y(n6636) );
AOI22X1TS U7474 ( .A0(n2266), .A1(FPSENCOS_d_ff3_sh_y_out[28]), .B0(n6638),
.B1(FPSENCOS_d_ff3_sh_x_out[28]), .Y(n6635) );
AOI22X1TS U7475 ( .A0(FPADDSUB_intDY[27]), .A1(n6637), .B0(n5098), .B1(
Data_2[27]), .Y(n6642) );
AOI22X1TS U7476 ( .A0(n2266), .A1(FPSENCOS_d_ff3_sh_y_out[27]), .B0(n6638),
.B1(FPSENCOS_d_ff3_sh_x_out[27]), .Y(n6641) );
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_DFF_P_SYMBOL_V
`define SKY130_FD_SC_HVL__UDP_DFF_P_SYMBOL_V
/**
* udp_dff$P: Positive edge triggered D flip-flop (Q output UDP).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__udp_dff$P (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input CLK
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_DFF_P_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD3_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__CLKDLYINV5SD3_PP_BLACKBOX_V
/**
* clkdlyinv5sd3: Clock Delay Inverter 5-stage 0.50um length inner
* stage gate.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__clkdlyinv5sd3 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV5SD3_PP_BLACKBOX_V
|
///////////////////////////////////////////////////////////////////////////////
//
// Project: Aurora 64B/66B
// Company: Xilinx
//
//
//
// (c) Copyright 2008 - 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
///////////////////////////////////////////////////////////////////////////////
//
// CLOCK_MODULE
//
//
// Description: This module takes the reference clock as
// input, and produces a divided clock on a global clock net suitable
// for driving application logic connected to the Aurora User Interface.
//
`timescale 1 ps / 1 ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module aurora_64b66b_25p4G_CLOCK_MODULE #
(
parameter OUT2_DIVIDE = 2,
parameter OUT3_DIVIDE = 8
)
(
CLK,
CLK_LOCKED,
USER_CLK,
SYNC_CLK,
MMCM_NOT_LOCKED
);
`define DLY #1
//***********************************Port Declarations*******************************
input CLK;
input CLK_LOCKED;
output USER_CLK;
output SYNC_CLK;
output MMCM_NOT_LOCKED;
//*********************************Wire Declarations**********************************
//*********************************Main Body of Code**********************************
//------------------------------------------------------------------------------
// Tx is needed in ALL conditions like Duplex, Tx only, Rx/Tx simplex
// Ultrascale GT TX clocking module in outside of the GT
// ___________
// | |------> user_clk (Tx/Rx userclk2_out)
// |ultrascale |
// | Tx CLK |------> sync clk (Tx/Rx userclk_out)
// CLK --->| Userclk |
// (txoutclk_out) | MODULE |------> shim_clk - not connected
// | |
// CLK_LOCKED --->| |------> pll_not_locked
// (tx_pma_reset_done_out) | | (--> connect to userclk_tx_active_out in multi gt file)
// |___________|------------> clk_o
//
wire user_clk_i;
assign USER_CLK = user_clk_i;
assign SYNC_CLK = user_clk_i;
aurora_64b66b_25p4G_ultrascale_tx_userclk ultrascale_tx_userclk_1
(
// port declaration
.gtwiz_userclk_tx_srcclk_in (CLK ), // txoutclk_out (GT) input wire
.gtwiz_userclk_tx_reset_in (CLK_LOCKED ), // tx_pma_reset_done_out (GT) input wire
.gtwiz_userclk_tx_usrclk_out (user_clk_i ), // usrclk_out output wire
.gtwiz_userclk_tx_usrclk2_out ( ), // usrclk2_out output wire
.gtwiz_userclk_tx_active_out (MMCM_NOT_LOCKED )//gtwiz_userclk_tx_active_out(GT)output reg = 1'b0
);
endmodule
|
// nios_system.v
// Generated using ACDS version 12.1 177 at 2014.10.15.20:19:19
`timescale 1 ps / 1 ps
module nios_system (
output wire VGA_CLK_from_the_VGA_Controller, // VGA_Controller_external_interface.CLK
output wire VGA_HS_from_the_VGA_Controller, // .HS
output wire VGA_VS_from_the_VGA_Controller, // .VS
output wire VGA_BLANK_from_the_VGA_Controller, // .BLANK
output wire VGA_SYNC_from_the_VGA_Controller, // .SYNC
output wire [7:0] VGA_R_from_the_VGA_Controller, // .R
output wire [7:0] VGA_G_from_the_VGA_Controller, // .G
output wire [7:0] VGA_B_from_the_VGA_Controller, // .B
input wire [7:0] controller1_external_connection_export, // controller1_external_connection.export
inout wire altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_cmd, // altera_up_sd_card_avalon_interface_0_conduit_end.b_SD_cmd
inout wire altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat, // .b_SD_dat
inout wire altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat3, // .b_SD_dat3
output wire altera_up_sd_card_avalon_interface_0_conduit_end_o_SD_clock, // .o_SD_clock
output wire clock_signals_sdram_clk_clk, // clock_signals_sdram_clk.clk
input wire clk_0, // clk_0_clk_in.clk
input wire reset_n, // clk_0_clk_in_reset.reset_n
output wire [12:0] sdram_0_wire_addr, // sdram_0_wire.addr
output wire [1:0] sdram_0_wire_ba, // .ba
output wire sdram_0_wire_cas_n, // .cas_n
output wire sdram_0_wire_cke, // .cke
output wire sdram_0_wire_cs_n, // .cs_n
inout wire [31:0] sdram_0_wire_dq, // .dq
output wire [3:0] sdram_0_wire_dqm, // .dqm
output wire sdram_0_wire_ras_n, // .ras_n
output wire sdram_0_wire_we_n, // .we_n
inout wire [31:0] SRAM_DQ_to_and_from_the_Pixel_Buffer, // Pixel_Buffer_external_interface.DQ
inout wire [3:0] Pixel_Buffer_external_interface_DPA, // .DPA
output wire [18:0] SRAM_ADDR_from_the_Pixel_Buffer, // .ADDR
output wire Pixel_Buffer_external_interface_ADSC_N, // .ADSC_N
output wire Pixel_Buffer_external_interface_ADSP_N, // .ADSP_N
output wire Pixel_Buffer_external_interface_ADV_N, // .ADV_N
output wire [3:0] Pixel_Buffer_external_interface_BE_N, // .BE_N
output wire Pixel_Buffer_external_interface_CE1_N, // .CE1_N
output wire Pixel_Buffer_external_interface_CE2, // .CE2
output wire Pixel_Buffer_external_interface_CE3_N, // .CE3_N
output wire Pixel_Buffer_external_interface_GW_N, // .GW_N
output wire SRAM_OE_N_from_the_Pixel_Buffer, // .OE_N
output wire SRAM_WE_N_from_the_Pixel_Buffer, // .WE_N
output wire Pixel_Buffer_external_interface_CLK // .CLK
);
wire clock_signals_sys_clk_clk; // Clock_Signals:sys_clk -> [Altera_UP_SD_Card_Avalon_Interface_0:i_clock, Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator:clk, Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent:clk, Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, CPU:clk, CPU_data_master_translator:clk, CPU_data_master_translator_avalon_universal_master_0_agent:clk, CPU_instruction_master_translator:clk, CPU_instruction_master_translator_avalon_universal_master_0_agent:clk, CPU_jtag_debug_module_translator:clk, CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:clk, CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, Dual_Clock_FIFO:clk_stream_in, Pixel_Buffer:clk, Pixel_Buffer_DMA:clk, Pixel_Buffer_DMA_avalon_control_slave_translator:clk, Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:clk, Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:clk, Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:clk, Pixel_Buffer_avalon_ssram_slave_translator:clk, Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent:clk, Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, addr_router:clk, addr_router_001:clk, addr_router_002:clk, cmd_xbar_demux:clk, cmd_xbar_demux_001:clk, cmd_xbar_demux_002:clk, cmd_xbar_mux:clk, cmd_xbar_mux_001:clk, cmd_xbar_mux_002:clk, cmd_xbar_mux_003:clk, cmd_xbar_mux_004:clk, cmd_xbar_mux_006:clk, controller1:clk, controller1_s1_translator:clk, controller1_s1_translator_avalon_universal_slave_0_agent:clk, controller1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, id_router:clk, id_router_001:clk, id_router_002:clk, id_router_003:clk, id_router_004:clk, id_router_005:clk, id_router_006:clk, id_router_007:clk, irq_mapper:clk, jtag_uart:clk, jtag_uart_avalon_jtag_slave_translator:clk, jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:clk, jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, limiter:clk, limiter_001:clk, rsp_xbar_demux:clk, rsp_xbar_demux_001:clk, rsp_xbar_demux_002:clk, rsp_xbar_demux_003:clk, rsp_xbar_demux_004:clk, rsp_xbar_demux_005:clk, rsp_xbar_demux_006:clk, rsp_xbar_demux_007:clk, rsp_xbar_mux:clk, rsp_xbar_mux_001:clk, rst_controller:clk, rst_controller_003:clk, sdram_0:clk, sdram_0_s1_translator:clk, sdram_0_s1_translator_avalon_universal_slave_0_agent:clk, sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, sysid:clock, sysid_control_slave_translator:clk, sysid_control_slave_translator_avalon_universal_slave_0_agent:clk, sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk]
wire clock_signals_sys_clk_reset_reset; // Clock_Signals:sys_reset_n -> [cmd_xbar_mux_003:reset, id_router_003:reset, rsp_xbar_demux_003:reset, sdram_0:reset_n, sdram_0_s1_translator:reset, sdram_0_s1_translator_avalon_universal_slave_0_agent:reset, sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset]
wire clock_signals_vga_clk_clk; // Clock_Signals:VGA_CLK -> [Dual_Clock_FIFO:clk_stream_out, VGA_Controller:clk, rst_controller_001:clk]
wire dual_clock_fifo_avalon_dc_buffer_source_endofpacket; // Dual_Clock_FIFO:stream_out_endofpacket -> VGA_Controller:endofpacket
wire dual_clock_fifo_avalon_dc_buffer_source_valid; // Dual_Clock_FIFO:stream_out_valid -> VGA_Controller:valid
wire dual_clock_fifo_avalon_dc_buffer_source_startofpacket; // Dual_Clock_FIFO:stream_out_startofpacket -> VGA_Controller:startofpacket
wire [29:0] dual_clock_fifo_avalon_dc_buffer_source_data; // Dual_Clock_FIFO:stream_out_data -> VGA_Controller:data
wire dual_clock_fifo_avalon_dc_buffer_source_ready; // VGA_Controller:ready -> Dual_Clock_FIFO:stream_out_ready
wire pixel_buffer_dma_avalon_pixel_source_endofpacket; // Pixel_Buffer_DMA:stream_endofpacket -> Dual_Clock_FIFO:stream_in_endofpacket
wire pixel_buffer_dma_avalon_pixel_source_valid; // Pixel_Buffer_DMA:stream_valid -> Dual_Clock_FIFO:stream_in_valid
wire pixel_buffer_dma_avalon_pixel_source_startofpacket; // Pixel_Buffer_DMA:stream_startofpacket -> Dual_Clock_FIFO:stream_in_startofpacket
wire [29:0] pixel_buffer_dma_avalon_pixel_source_data; // Pixel_Buffer_DMA:stream_data -> Dual_Clock_FIFO:stream_in_data
wire pixel_buffer_dma_avalon_pixel_source_ready; // Dual_Clock_FIFO:stream_in_ready -> Pixel_Buffer_DMA:stream_ready
wire cpu_instruction_master_waitrequest; // CPU_instruction_master_translator:av_waitrequest -> CPU:i_waitrequest
wire [27:0] cpu_instruction_master_address; // CPU:i_address -> CPU_instruction_master_translator:av_address
wire cpu_instruction_master_read; // CPU:i_read -> CPU_instruction_master_translator:av_read
wire [31:0] cpu_instruction_master_readdata; // CPU_instruction_master_translator:av_readdata -> CPU:i_readdata
wire cpu_instruction_master_readdatavalid; // CPU_instruction_master_translator:av_readdatavalid -> CPU:i_readdatavalid
wire cpu_data_master_waitrequest; // CPU_data_master_translator:av_waitrequest -> CPU:d_waitrequest
wire [31:0] cpu_data_master_writedata; // CPU:d_writedata -> CPU_data_master_translator:av_writedata
wire [27:0] cpu_data_master_address; // CPU:d_address -> CPU_data_master_translator:av_address
wire cpu_data_master_write; // CPU:d_write -> CPU_data_master_translator:av_write
wire cpu_data_master_read; // CPU:d_read -> CPU_data_master_translator:av_read
wire [31:0] cpu_data_master_readdata; // CPU_data_master_translator:av_readdata -> CPU:d_readdata
wire cpu_data_master_debugaccess; // CPU:jtag_debug_module_debugaccess_to_roms -> CPU_data_master_translator:av_debugaccess
wire cpu_data_master_readdatavalid; // CPU_data_master_translator:av_readdatavalid -> CPU:d_readdatavalid
wire [3:0] cpu_data_master_byteenable; // CPU:d_byteenable -> CPU_data_master_translator:av_byteenable
wire pixel_buffer_dma_avalon_pixel_dma_master_waitrequest; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:av_waitrequest -> Pixel_Buffer_DMA:master_waitrequest
wire [31:0] pixel_buffer_dma_avalon_pixel_dma_master_address; // Pixel_Buffer_DMA:master_address -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:av_address
wire pixel_buffer_dma_avalon_pixel_dma_master_lock; // Pixel_Buffer_DMA:master_arbiterlock -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:av_lock
wire pixel_buffer_dma_avalon_pixel_dma_master_read; // Pixel_Buffer_DMA:master_read -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:av_read
wire [31:0] pixel_buffer_dma_avalon_pixel_dma_master_readdata; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:av_readdata -> Pixel_Buffer_DMA:master_readdata
wire pixel_buffer_dma_avalon_pixel_dma_master_readdatavalid; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:av_readdatavalid -> Pixel_Buffer_DMA:master_readdatavalid
wire [31:0] cpu_jtag_debug_module_translator_avalon_anti_slave_0_writedata; // CPU_jtag_debug_module_translator:av_writedata -> CPU:jtag_debug_module_writedata
wire [8:0] cpu_jtag_debug_module_translator_avalon_anti_slave_0_address; // CPU_jtag_debug_module_translator:av_address -> CPU:jtag_debug_module_address
wire cpu_jtag_debug_module_translator_avalon_anti_slave_0_chipselect; // CPU_jtag_debug_module_translator:av_chipselect -> CPU:jtag_debug_module_select
wire cpu_jtag_debug_module_translator_avalon_anti_slave_0_write; // CPU_jtag_debug_module_translator:av_write -> CPU:jtag_debug_module_write
wire [31:0] cpu_jtag_debug_module_translator_avalon_anti_slave_0_readdata; // CPU:jtag_debug_module_readdata -> CPU_jtag_debug_module_translator:av_readdata
wire cpu_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer; // CPU_jtag_debug_module_translator:av_begintransfer -> CPU:jtag_debug_module_begintransfer
wire cpu_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess; // CPU_jtag_debug_module_translator:av_debugaccess -> CPU:jtag_debug_module_debugaccess
wire [3:0] cpu_jtag_debug_module_translator_avalon_anti_slave_0_byteenable; // CPU_jtag_debug_module_translator:av_byteenable -> CPU:jtag_debug_module_byteenable
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_anti_slave_0_waitrequest; // Altera_UP_SD_Card_Avalon_Interface_0:o_avalon_waitrequest -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator:av_waitrequest
wire [31:0] altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_anti_slave_0_writedata; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator:av_writedata -> Altera_UP_SD_Card_Avalon_Interface_0:i_avalon_writedata
wire [7:0] altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_anti_slave_0_address; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator:av_address -> Altera_UP_SD_Card_Avalon_Interface_0:i_avalon_address
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_anti_slave_0_chipselect; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator:av_chipselect -> Altera_UP_SD_Card_Avalon_Interface_0:i_avalon_chip_select
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_anti_slave_0_write; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator:av_write -> Altera_UP_SD_Card_Avalon_Interface_0:i_avalon_write
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_anti_slave_0_read; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator:av_read -> Altera_UP_SD_Card_Avalon_Interface_0:i_avalon_read
wire [31:0] altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_anti_slave_0_readdata; // Altera_UP_SD_Card_Avalon_Interface_0:o_avalon_readdata -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator:av_readdata
wire [3:0] altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_anti_slave_0_byteenable; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator:av_byteenable -> Altera_UP_SD_Card_Avalon_Interface_0:i_avalon_byteenable
wire [0:0] sysid_control_slave_translator_avalon_anti_slave_0_address; // sysid_control_slave_translator:av_address -> sysid:address
wire [31:0] sysid_control_slave_translator_avalon_anti_slave_0_readdata; // sysid:readdata -> sysid_control_slave_translator:av_readdata
wire sdram_0_s1_translator_avalon_anti_slave_0_waitrequest; // sdram_0:za_waitrequest -> sdram_0_s1_translator:av_waitrequest
wire [31:0] sdram_0_s1_translator_avalon_anti_slave_0_writedata; // sdram_0_s1_translator:av_writedata -> sdram_0:az_data
wire [24:0] sdram_0_s1_translator_avalon_anti_slave_0_address; // sdram_0_s1_translator:av_address -> sdram_0:az_addr
wire sdram_0_s1_translator_avalon_anti_slave_0_chipselect; // sdram_0_s1_translator:av_chipselect -> sdram_0:az_cs
wire sdram_0_s1_translator_avalon_anti_slave_0_write; // sdram_0_s1_translator:av_write -> sdram_0:az_wr_n
wire sdram_0_s1_translator_avalon_anti_slave_0_read; // sdram_0_s1_translator:av_read -> sdram_0:az_rd_n
wire [31:0] sdram_0_s1_translator_avalon_anti_slave_0_readdata; // sdram_0:za_data -> sdram_0_s1_translator:av_readdata
wire sdram_0_s1_translator_avalon_anti_slave_0_readdatavalid; // sdram_0:za_valid -> sdram_0_s1_translator:av_readdatavalid
wire [3:0] sdram_0_s1_translator_avalon_anti_slave_0_byteenable; // sdram_0_s1_translator:av_byteenable -> sdram_0:az_be_n
wire [1:0] controller1_s1_translator_avalon_anti_slave_0_address; // controller1_s1_translator:av_address -> controller1:address
wire [31:0] controller1_s1_translator_avalon_anti_slave_0_readdata; // controller1:readdata -> controller1_s1_translator:av_readdata
wire [31:0] pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_writedata; // Pixel_Buffer_DMA_avalon_control_slave_translator:av_writedata -> Pixel_Buffer_DMA:slave_writedata
wire [1:0] pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_address; // Pixel_Buffer_DMA_avalon_control_slave_translator:av_address -> Pixel_Buffer_DMA:slave_address
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_write; // Pixel_Buffer_DMA_avalon_control_slave_translator:av_write -> Pixel_Buffer_DMA:slave_write
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_read; // Pixel_Buffer_DMA_avalon_control_slave_translator:av_read -> Pixel_Buffer_DMA:slave_read
wire [31:0] pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_readdata; // Pixel_Buffer_DMA:slave_readdata -> Pixel_Buffer_DMA_avalon_control_slave_translator:av_readdata
wire [3:0] pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_byteenable; // Pixel_Buffer_DMA_avalon_control_slave_translator:av_byteenable -> Pixel_Buffer_DMA:slave_byteenable
wire pixel_buffer_avalon_ssram_slave_translator_avalon_anti_slave_0_waitrequest; // Pixel_Buffer:waitrequest -> Pixel_Buffer_avalon_ssram_slave_translator:av_waitrequest
wire [31:0] pixel_buffer_avalon_ssram_slave_translator_avalon_anti_slave_0_writedata; // Pixel_Buffer_avalon_ssram_slave_translator:av_writedata -> Pixel_Buffer:writedata
wire [18:0] pixel_buffer_avalon_ssram_slave_translator_avalon_anti_slave_0_address; // Pixel_Buffer_avalon_ssram_slave_translator:av_address -> Pixel_Buffer:address
wire pixel_buffer_avalon_ssram_slave_translator_avalon_anti_slave_0_write; // Pixel_Buffer_avalon_ssram_slave_translator:av_write -> Pixel_Buffer:write
wire pixel_buffer_avalon_ssram_slave_translator_avalon_anti_slave_0_read; // Pixel_Buffer_avalon_ssram_slave_translator:av_read -> Pixel_Buffer:read
wire [31:0] pixel_buffer_avalon_ssram_slave_translator_avalon_anti_slave_0_readdata; // Pixel_Buffer:readdata -> Pixel_Buffer_avalon_ssram_slave_translator:av_readdata
wire pixel_buffer_avalon_ssram_slave_translator_avalon_anti_slave_0_readdatavalid; // Pixel_Buffer:readdatavalid -> Pixel_Buffer_avalon_ssram_slave_translator:av_readdatavalid
wire [3:0] pixel_buffer_avalon_ssram_slave_translator_avalon_anti_slave_0_byteenable; // Pixel_Buffer_avalon_ssram_slave_translator:av_byteenable -> Pixel_Buffer:byteenable
wire jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest; // jtag_uart:av_waitrequest -> jtag_uart_avalon_jtag_slave_translator:av_waitrequest
wire [31:0] jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata; // jtag_uart_avalon_jtag_slave_translator:av_writedata -> jtag_uart:av_writedata
wire [0:0] jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_address; // jtag_uart_avalon_jtag_slave_translator:av_address -> jtag_uart:av_address
wire jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect; // jtag_uart_avalon_jtag_slave_translator:av_chipselect -> jtag_uart:av_chipselect
wire jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_write; // jtag_uart_avalon_jtag_slave_translator:av_write -> jtag_uart:av_write_n
wire jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_read; // jtag_uart_avalon_jtag_slave_translator:av_read -> jtag_uart:av_read_n
wire [31:0] jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata; // jtag_uart:av_readdata -> jtag_uart_avalon_jtag_slave_translator:av_readdata
wire cpu_instruction_master_translator_avalon_universal_master_0_waitrequest; // CPU_instruction_master_translator_avalon_universal_master_0_agent:av_waitrequest -> CPU_instruction_master_translator:uav_waitrequest
wire [2:0] cpu_instruction_master_translator_avalon_universal_master_0_burstcount; // CPU_instruction_master_translator:uav_burstcount -> CPU_instruction_master_translator_avalon_universal_master_0_agent:av_burstcount
wire [31:0] cpu_instruction_master_translator_avalon_universal_master_0_writedata; // CPU_instruction_master_translator:uav_writedata -> CPU_instruction_master_translator_avalon_universal_master_0_agent:av_writedata
wire [31:0] cpu_instruction_master_translator_avalon_universal_master_0_address; // CPU_instruction_master_translator:uav_address -> CPU_instruction_master_translator_avalon_universal_master_0_agent:av_address
wire cpu_instruction_master_translator_avalon_universal_master_0_lock; // CPU_instruction_master_translator:uav_lock -> CPU_instruction_master_translator_avalon_universal_master_0_agent:av_lock
wire cpu_instruction_master_translator_avalon_universal_master_0_write; // CPU_instruction_master_translator:uav_write -> CPU_instruction_master_translator_avalon_universal_master_0_agent:av_write
wire cpu_instruction_master_translator_avalon_universal_master_0_read; // CPU_instruction_master_translator:uav_read -> CPU_instruction_master_translator_avalon_universal_master_0_agent:av_read
wire [31:0] cpu_instruction_master_translator_avalon_universal_master_0_readdata; // CPU_instruction_master_translator_avalon_universal_master_0_agent:av_readdata -> CPU_instruction_master_translator:uav_readdata
wire cpu_instruction_master_translator_avalon_universal_master_0_debugaccess; // CPU_instruction_master_translator:uav_debugaccess -> CPU_instruction_master_translator_avalon_universal_master_0_agent:av_debugaccess
wire [3:0] cpu_instruction_master_translator_avalon_universal_master_0_byteenable; // CPU_instruction_master_translator:uav_byteenable -> CPU_instruction_master_translator_avalon_universal_master_0_agent:av_byteenable
wire cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid; // CPU_instruction_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> CPU_instruction_master_translator:uav_readdatavalid
wire cpu_data_master_translator_avalon_universal_master_0_waitrequest; // CPU_data_master_translator_avalon_universal_master_0_agent:av_waitrequest -> CPU_data_master_translator:uav_waitrequest
wire [2:0] cpu_data_master_translator_avalon_universal_master_0_burstcount; // CPU_data_master_translator:uav_burstcount -> CPU_data_master_translator_avalon_universal_master_0_agent:av_burstcount
wire [31:0] cpu_data_master_translator_avalon_universal_master_0_writedata; // CPU_data_master_translator:uav_writedata -> CPU_data_master_translator_avalon_universal_master_0_agent:av_writedata
wire [31:0] cpu_data_master_translator_avalon_universal_master_0_address; // CPU_data_master_translator:uav_address -> CPU_data_master_translator_avalon_universal_master_0_agent:av_address
wire cpu_data_master_translator_avalon_universal_master_0_lock; // CPU_data_master_translator:uav_lock -> CPU_data_master_translator_avalon_universal_master_0_agent:av_lock
wire cpu_data_master_translator_avalon_universal_master_0_write; // CPU_data_master_translator:uav_write -> CPU_data_master_translator_avalon_universal_master_0_agent:av_write
wire cpu_data_master_translator_avalon_universal_master_0_read; // CPU_data_master_translator:uav_read -> CPU_data_master_translator_avalon_universal_master_0_agent:av_read
wire [31:0] cpu_data_master_translator_avalon_universal_master_0_readdata; // CPU_data_master_translator_avalon_universal_master_0_agent:av_readdata -> CPU_data_master_translator:uav_readdata
wire cpu_data_master_translator_avalon_universal_master_0_debugaccess; // CPU_data_master_translator:uav_debugaccess -> CPU_data_master_translator_avalon_universal_master_0_agent:av_debugaccess
wire [3:0] cpu_data_master_translator_avalon_universal_master_0_byteenable; // CPU_data_master_translator:uav_byteenable -> CPU_data_master_translator_avalon_universal_master_0_agent:av_byteenable
wire cpu_data_master_translator_avalon_universal_master_0_readdatavalid; // CPU_data_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> CPU_data_master_translator:uav_readdatavalid
wire pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_waitrequest; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_waitrequest -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_waitrequest
wire [2:0] pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_burstcount; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_burstcount -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_burstcount
wire [31:0] pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_writedata; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_writedata -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_writedata
wire [31:0] pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_address; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_address -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_address
wire pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_lock; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_lock -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_lock
wire pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_write; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_write -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_write
wire pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_read; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_read -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_read
wire [31:0] pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_readdata; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_readdata -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_readdata
wire pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_debugaccess; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_debugaccess -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_debugaccess
wire [3:0] pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_byteenable; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_byteenable -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_byteenable
wire pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_readdatavalid; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_readdatavalid
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest; // CPU_jtag_debug_module_translator:uav_waitrequest -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_burstcount -> CPU_jtag_debug_module_translator:uav_burstcount
wire [31:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_writedata -> CPU_jtag_debug_module_translator:uav_writedata
wire [31:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_address -> CPU_jtag_debug_module_translator:uav_address
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_write -> CPU_jtag_debug_module_translator:uav_write
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_lock -> CPU_jtag_debug_module_translator:uav_lock
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_read -> CPU_jtag_debug_module_translator:uav_read
wire [31:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata; // CPU_jtag_debug_module_translator:uav_readdata -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdata
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // CPU_jtag_debug_module_translator:uav_readdatavalid -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_debugaccess -> CPU_jtag_debug_module_translator:uav_debugaccess
wire [3:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_byteenable -> CPU_jtag_debug_module_translator:uav_byteenable
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_valid -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [105:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_data -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_ready
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [105:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_data
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_ready -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator:uav_waitrequest -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator:uav_burstcount
wire [31:0] altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator:uav_writedata
wire [31:0] altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_m0_address; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent:m0_address -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator:uav_address
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_m0_write; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent:m0_write -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator:uav_write
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_m0_lock; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent:m0_lock -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator:uav_lock
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_m0_read; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent:m0_read -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator:uav_read
wire [31:0] altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator:uav_readdata -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent:m0_readdata
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator:uav_readdatavalid -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator:uav_debugaccess
wire [3:0] altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator:uav_byteenable
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [105:0] altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [105:0] altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sysid_control_slave_translator:uav_waitrequest -> sysid_control_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // sysid_control_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> sysid_control_slave_translator:uav_burstcount
wire [31:0] sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // sysid_control_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> sysid_control_slave_translator:uav_writedata
wire [31:0] sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_address; // sysid_control_slave_translator_avalon_universal_slave_0_agent:m0_address -> sysid_control_slave_translator:uav_address
wire sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_write; // sysid_control_slave_translator_avalon_universal_slave_0_agent:m0_write -> sysid_control_slave_translator:uav_write
wire sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_lock; // sysid_control_slave_translator_avalon_universal_slave_0_agent:m0_lock -> sysid_control_slave_translator:uav_lock
wire sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_read; // sysid_control_slave_translator_avalon_universal_slave_0_agent:m0_read -> sysid_control_slave_translator:uav_read
wire [31:0] sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // sysid_control_slave_translator:uav_readdata -> sysid_control_slave_translator_avalon_universal_slave_0_agent:m0_readdata
wire sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sysid_control_slave_translator:uav_readdatavalid -> sysid_control_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sysid_control_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sysid_control_slave_translator:uav_debugaccess
wire [3:0] sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // sysid_control_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> sysid_control_slave_translator:uav_byteenable
wire sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sysid_control_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // sysid_control_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sysid_control_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [105:0] sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // sysid_control_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sysid_control_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
wire sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sysid_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sysid_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sysid_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [105:0] sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sysid_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
wire sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sysid_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire sysid_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sysid_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sysid_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] sysid_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sysid_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sysid_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire sysid_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sysid_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sysid_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sdram_0_s1_translator:uav_waitrequest -> sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> sdram_0_s1_translator:uav_burstcount
wire [31:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> sdram_0_s1_translator:uav_writedata
wire [31:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_address; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_address -> sdram_0_s1_translator:uav_address
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_write; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_write -> sdram_0_s1_translator:uav_write
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_lock; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> sdram_0_s1_translator:uav_lock
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_read; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_read -> sdram_0_s1_translator:uav_read
wire [31:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // sdram_0_s1_translator:uav_readdata -> sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_readdata
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sdram_0_s1_translator:uav_readdatavalid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sdram_0_s1_translator:uav_debugaccess
wire [3:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> sdram_0_s1_translator:uav_byteenable
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [105:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [105:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire controller1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // controller1_s1_translator:uav_waitrequest -> controller1_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] controller1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // controller1_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> controller1_s1_translator:uav_burstcount
wire [31:0] controller1_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // controller1_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> controller1_s1_translator:uav_writedata
wire [31:0] controller1_s1_translator_avalon_universal_slave_0_agent_m0_address; // controller1_s1_translator_avalon_universal_slave_0_agent:m0_address -> controller1_s1_translator:uav_address
wire controller1_s1_translator_avalon_universal_slave_0_agent_m0_write; // controller1_s1_translator_avalon_universal_slave_0_agent:m0_write -> controller1_s1_translator:uav_write
wire controller1_s1_translator_avalon_universal_slave_0_agent_m0_lock; // controller1_s1_translator_avalon_universal_slave_0_agent:m0_lock -> controller1_s1_translator:uav_lock
wire controller1_s1_translator_avalon_universal_slave_0_agent_m0_read; // controller1_s1_translator_avalon_universal_slave_0_agent:m0_read -> controller1_s1_translator:uav_read
wire [31:0] controller1_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // controller1_s1_translator:uav_readdata -> controller1_s1_translator_avalon_universal_slave_0_agent:m0_readdata
wire controller1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // controller1_s1_translator:uav_readdatavalid -> controller1_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire controller1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // controller1_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> controller1_s1_translator:uav_debugaccess
wire [3:0] controller1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // controller1_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> controller1_s1_translator:uav_byteenable
wire controller1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // controller1_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> controller1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire controller1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // controller1_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> controller1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire controller1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // controller1_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> controller1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [105:0] controller1_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // controller1_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> controller1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire controller1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // controller1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> controller1_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
wire controller1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // controller1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> controller1_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire controller1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // controller1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> controller1_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire controller1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // controller1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> controller1_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [105:0] controller1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // controller1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> controller1_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
wire controller1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // controller1_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> controller1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire controller1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // controller1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> controller1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] controller1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // controller1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> controller1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire controller1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // controller1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> controller1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // Pixel_Buffer_DMA_avalon_control_slave_translator:uav_waitrequest -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> Pixel_Buffer_DMA_avalon_control_slave_translator:uav_burstcount
wire [31:0] pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> Pixel_Buffer_DMA_avalon_control_slave_translator:uav_writedata
wire [31:0] pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_address; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_address -> Pixel_Buffer_DMA_avalon_control_slave_translator:uav_address
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_write; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_write -> Pixel_Buffer_DMA_avalon_control_slave_translator:uav_write
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_lock; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_lock -> Pixel_Buffer_DMA_avalon_control_slave_translator:uav_lock
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_read; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_read -> Pixel_Buffer_DMA_avalon_control_slave_translator:uav_read
wire [31:0] pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // Pixel_Buffer_DMA_avalon_control_slave_translator:uav_readdata -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_readdata
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // Pixel_Buffer_DMA_avalon_control_slave_translator:uav_readdatavalid -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> Pixel_Buffer_DMA_avalon_control_slave_translator:uav_debugaccess
wire [3:0] pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> Pixel_Buffer_DMA_avalon_control_slave_translator:uav_byteenable
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [105:0] pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [105:0] pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // Pixel_Buffer_avalon_ssram_slave_translator:uav_waitrequest -> Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> Pixel_Buffer_avalon_ssram_slave_translator:uav_burstcount
wire [31:0] pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> Pixel_Buffer_avalon_ssram_slave_translator:uav_writedata
wire [31:0] pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_m0_address; // Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent:m0_address -> Pixel_Buffer_avalon_ssram_slave_translator:uav_address
wire pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_m0_write; // Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent:m0_write -> Pixel_Buffer_avalon_ssram_slave_translator:uav_write
wire pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_m0_lock; // Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent:m0_lock -> Pixel_Buffer_avalon_ssram_slave_translator:uav_lock
wire pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_m0_read; // Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent:m0_read -> Pixel_Buffer_avalon_ssram_slave_translator:uav_read
wire [31:0] pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // Pixel_Buffer_avalon_ssram_slave_translator:uav_readdata -> Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent:m0_readdata
wire pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // Pixel_Buffer_avalon_ssram_slave_translator:uav_readdatavalid -> Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> Pixel_Buffer_avalon_ssram_slave_translator:uav_debugaccess
wire [3:0] pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> Pixel_Buffer_avalon_ssram_slave_translator:uav_byteenable
wire pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [105:0] pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
wire pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [105:0] pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
wire pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // jtag_uart_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> jtag_uart_avalon_jtag_slave_translator:uav_burstcount
wire [31:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> jtag_uart_avalon_jtag_slave_translator:uav_writedata
wire [31:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_address -> jtag_uart_avalon_jtag_slave_translator:uav_address
wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_write -> jtag_uart_avalon_jtag_slave_translator:uav_write
wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_lock -> jtag_uart_avalon_jtag_slave_translator:uav_lock
wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_read -> jtag_uart_avalon_jtag_slave_translator:uav_read
wire [31:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // jtag_uart_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdata
wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // jtag_uart_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> jtag_uart_avalon_jtag_slave_translator:uav_debugaccess
wire [3:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> jtag_uart_avalon_jtag_slave_translator:uav_byteenable
wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [105:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [105:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // CPU_instruction_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket
wire cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_valid; // CPU_instruction_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid
wire cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // CPU_instruction_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket
wire [104:0] cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_data; // CPU_instruction_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data
wire cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router:sink_ready -> CPU_instruction_master_translator_avalon_universal_master_0_agent:cp_ready
wire cpu_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // CPU_data_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_001:sink_endofpacket
wire cpu_data_master_translator_avalon_universal_master_0_agent_cp_valid; // CPU_data_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_001:sink_valid
wire cpu_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // CPU_data_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_001:sink_startofpacket
wire [104:0] cpu_data_master_translator_avalon_universal_master_0_agent_cp_data; // CPU_data_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_001:sink_data
wire cpu_data_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router_001:sink_ready -> CPU_data_master_translator_avalon_universal_master_0_agent:cp_ready
wire pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_002:sink_endofpacket
wire pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_valid; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_002:sink_valid
wire pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_002:sink_startofpacket
wire [104:0] pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_data; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_002:sink_data
wire pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router_002:sink_ready -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:cp_ready
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket
wire [104:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready; // id_router:sink_ready -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_ready
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rp_valid; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket
wire [104:0] altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rp_data; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_001:sink_ready -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent:rp_ready
wire sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sysid_control_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_002:sink_endofpacket
wire sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_valid; // sysid_control_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_002:sink_valid
wire sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sysid_control_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_002:sink_startofpacket
wire [104:0] sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_data; // sysid_control_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_002:sink_data
wire sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_002:sink_ready -> sysid_control_slave_translator_avalon_universal_slave_0_agent:rp_ready
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_003:sink_endofpacket
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_valid; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_003:sink_valid
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_003:sink_startofpacket
wire [104:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_data; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_003:sink_data
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_003:sink_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_ready
wire controller1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // controller1_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_004:sink_endofpacket
wire controller1_s1_translator_avalon_universal_slave_0_agent_rp_valid; // controller1_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_004:sink_valid
wire controller1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // controller1_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_004:sink_startofpacket
wire [104:0] controller1_s1_translator_avalon_universal_slave_0_agent_rp_data; // controller1_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_004:sink_data
wire controller1_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_004:sink_ready -> controller1_s1_translator_avalon_universal_slave_0_agent:rp_ready
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_005:sink_endofpacket
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_valid; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_005:sink_valid
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_005:sink_startofpacket
wire [104:0] pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_data; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_005:sink_data
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_005:sink_ready -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rp_ready
wire pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_006:sink_endofpacket
wire pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rp_valid; // Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_006:sink_valid
wire pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_006:sink_startofpacket
wire [104:0] pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rp_data; // Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_006:sink_data
wire pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_006:sink_ready -> Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent:rp_ready
wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_007:sink_endofpacket
wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_007:sink_valid
wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_007:sink_startofpacket
wire [104:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_007:sink_data
wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_007:sink_ready -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_ready
wire addr_router_src_endofpacket; // addr_router:src_endofpacket -> limiter:cmd_sink_endofpacket
wire addr_router_src_valid; // addr_router:src_valid -> limiter:cmd_sink_valid
wire addr_router_src_startofpacket; // addr_router:src_startofpacket -> limiter:cmd_sink_startofpacket
wire [104:0] addr_router_src_data; // addr_router:src_data -> limiter:cmd_sink_data
wire [7:0] addr_router_src_channel; // addr_router:src_channel -> limiter:cmd_sink_channel
wire addr_router_src_ready; // limiter:cmd_sink_ready -> addr_router:src_ready
wire limiter_rsp_src_endofpacket; // limiter:rsp_src_endofpacket -> CPU_instruction_master_translator_avalon_universal_master_0_agent:rp_endofpacket
wire limiter_rsp_src_valid; // limiter:rsp_src_valid -> CPU_instruction_master_translator_avalon_universal_master_0_agent:rp_valid
wire limiter_rsp_src_startofpacket; // limiter:rsp_src_startofpacket -> CPU_instruction_master_translator_avalon_universal_master_0_agent:rp_startofpacket
wire [104:0] limiter_rsp_src_data; // limiter:rsp_src_data -> CPU_instruction_master_translator_avalon_universal_master_0_agent:rp_data
wire [7:0] limiter_rsp_src_channel; // limiter:rsp_src_channel -> CPU_instruction_master_translator_avalon_universal_master_0_agent:rp_channel
wire limiter_rsp_src_ready; // CPU_instruction_master_translator_avalon_universal_master_0_agent:rp_ready -> limiter:rsp_src_ready
wire addr_router_001_src_endofpacket; // addr_router_001:src_endofpacket -> limiter_001:cmd_sink_endofpacket
wire addr_router_001_src_valid; // addr_router_001:src_valid -> limiter_001:cmd_sink_valid
wire addr_router_001_src_startofpacket; // addr_router_001:src_startofpacket -> limiter_001:cmd_sink_startofpacket
wire [104:0] addr_router_001_src_data; // addr_router_001:src_data -> limiter_001:cmd_sink_data
wire [7:0] addr_router_001_src_channel; // addr_router_001:src_channel -> limiter_001:cmd_sink_channel
wire addr_router_001_src_ready; // limiter_001:cmd_sink_ready -> addr_router_001:src_ready
wire limiter_001_rsp_src_endofpacket; // limiter_001:rsp_src_endofpacket -> CPU_data_master_translator_avalon_universal_master_0_agent:rp_endofpacket
wire limiter_001_rsp_src_valid; // limiter_001:rsp_src_valid -> CPU_data_master_translator_avalon_universal_master_0_agent:rp_valid
wire limiter_001_rsp_src_startofpacket; // limiter_001:rsp_src_startofpacket -> CPU_data_master_translator_avalon_universal_master_0_agent:rp_startofpacket
wire [104:0] limiter_001_rsp_src_data; // limiter_001:rsp_src_data -> CPU_data_master_translator_avalon_universal_master_0_agent:rp_data
wire [7:0] limiter_001_rsp_src_channel; // limiter_001:rsp_src_channel -> CPU_data_master_translator_avalon_universal_master_0_agent:rp_channel
wire limiter_001_rsp_src_ready; // CPU_data_master_translator_avalon_universal_master_0_agent:rp_ready -> limiter_001:rsp_src_ready
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [CPU:reset_n, CPU_data_master_translator:reset, CPU_data_master_translator_avalon_universal_master_0_agent:reset, CPU_instruction_master_translator:reset, CPU_instruction_master_translator_avalon_universal_master_0_agent:reset, CPU_jtag_debug_module_translator:reset, CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:reset, CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, Dual_Clock_FIFO:reset_stream_in, Pixel_Buffer:reset, Pixel_Buffer_DMA:reset, Pixel_Buffer_DMA_avalon_control_slave_translator:reset, Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:reset, Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:reset, Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:reset, Pixel_Buffer_avalon_ssram_slave_translator:reset, Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent:reset, Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, addr_router:reset, addr_router_001:reset, addr_router_002:reset, cmd_xbar_demux:reset, cmd_xbar_demux_001:reset, cmd_xbar_demux_002:reset, cmd_xbar_mux:reset, cmd_xbar_mux_006:reset, id_router:reset, id_router_005:reset, id_router_006:reset, irq_mapper:reset, limiter:reset, limiter_001:reset, rsp_xbar_demux:reset, rsp_xbar_demux_005:reset, rsp_xbar_demux_006:reset, rsp_xbar_mux:reset, rsp_xbar_mux_001:reset]
wire cpu_jtag_debug_module_reset_reset; // CPU:jtag_debug_module_resetrequest -> [rst_controller:reset_in1, rst_controller_001:reset_in1, rst_controller_002:reset_in1]
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [Dual_Clock_FIFO:reset_stream_out, VGA_Controller:reset]
wire rst_controller_002_reset_out_reset; // rst_controller_002:reset_out -> Clock_Signals:reset
wire rst_controller_003_reset_out_reset; // rst_controller_003:reset_out -> [Altera_UP_SD_Card_Avalon_Interface_0:i_reset_n, Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator:reset, Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent:reset, Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, cmd_xbar_mux_001:reset, cmd_xbar_mux_002:reset, cmd_xbar_mux_004:reset, controller1:reset_n, controller1_s1_translator:reset, controller1_s1_translator_avalon_universal_slave_0_agent:reset, controller1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, id_router_001:reset, id_router_002:reset, id_router_004:reset, id_router_007:reset, jtag_uart:rst_n, jtag_uart_avalon_jtag_slave_translator:reset, jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:reset, jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rsp_xbar_demux_001:reset, rsp_xbar_demux_002:reset, rsp_xbar_demux_004:reset, rsp_xbar_demux_007:reset, sysid:reset_n, sysid_control_slave_translator:reset, sysid_control_slave_translator_avalon_universal_slave_0_agent:reset, sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset]
wire cmd_xbar_demux_src0_endofpacket; // cmd_xbar_demux:src0_endofpacket -> cmd_xbar_mux:sink0_endofpacket
wire cmd_xbar_demux_src0_valid; // cmd_xbar_demux:src0_valid -> cmd_xbar_mux:sink0_valid
wire cmd_xbar_demux_src0_startofpacket; // cmd_xbar_demux:src0_startofpacket -> cmd_xbar_mux:sink0_startofpacket
wire [104:0] cmd_xbar_demux_src0_data; // cmd_xbar_demux:src0_data -> cmd_xbar_mux:sink0_data
wire [7:0] cmd_xbar_demux_src0_channel; // cmd_xbar_demux:src0_channel -> cmd_xbar_mux:sink0_channel
wire cmd_xbar_demux_src0_ready; // cmd_xbar_mux:sink0_ready -> cmd_xbar_demux:src0_ready
wire cmd_xbar_demux_src1_endofpacket; // cmd_xbar_demux:src1_endofpacket -> cmd_xbar_mux_001:sink0_endofpacket
wire cmd_xbar_demux_src1_valid; // cmd_xbar_demux:src1_valid -> cmd_xbar_mux_001:sink0_valid
wire cmd_xbar_demux_src1_startofpacket; // cmd_xbar_demux:src1_startofpacket -> cmd_xbar_mux_001:sink0_startofpacket
wire [104:0] cmd_xbar_demux_src1_data; // cmd_xbar_demux:src1_data -> cmd_xbar_mux_001:sink0_data
wire [7:0] cmd_xbar_demux_src1_channel; // cmd_xbar_demux:src1_channel -> cmd_xbar_mux_001:sink0_channel
wire cmd_xbar_demux_src1_ready; // cmd_xbar_mux_001:sink0_ready -> cmd_xbar_demux:src1_ready
wire cmd_xbar_demux_src2_endofpacket; // cmd_xbar_demux:src2_endofpacket -> cmd_xbar_mux_002:sink0_endofpacket
wire cmd_xbar_demux_src2_valid; // cmd_xbar_demux:src2_valid -> cmd_xbar_mux_002:sink0_valid
wire cmd_xbar_demux_src2_startofpacket; // cmd_xbar_demux:src2_startofpacket -> cmd_xbar_mux_002:sink0_startofpacket
wire [104:0] cmd_xbar_demux_src2_data; // cmd_xbar_demux:src2_data -> cmd_xbar_mux_002:sink0_data
wire [7:0] cmd_xbar_demux_src2_channel; // cmd_xbar_demux:src2_channel -> cmd_xbar_mux_002:sink0_channel
wire cmd_xbar_demux_src2_ready; // cmd_xbar_mux_002:sink0_ready -> cmd_xbar_demux:src2_ready
wire cmd_xbar_demux_src3_endofpacket; // cmd_xbar_demux:src3_endofpacket -> cmd_xbar_mux_003:sink0_endofpacket
wire cmd_xbar_demux_src3_valid; // cmd_xbar_demux:src3_valid -> cmd_xbar_mux_003:sink0_valid
wire cmd_xbar_demux_src3_startofpacket; // cmd_xbar_demux:src3_startofpacket -> cmd_xbar_mux_003:sink0_startofpacket
wire [104:0] cmd_xbar_demux_src3_data; // cmd_xbar_demux:src3_data -> cmd_xbar_mux_003:sink0_data
wire [7:0] cmd_xbar_demux_src3_channel; // cmd_xbar_demux:src3_channel -> cmd_xbar_mux_003:sink0_channel
wire cmd_xbar_demux_src3_ready; // cmd_xbar_mux_003:sink0_ready -> cmd_xbar_demux:src3_ready
wire cmd_xbar_demux_src4_endofpacket; // cmd_xbar_demux:src4_endofpacket -> cmd_xbar_mux_004:sink0_endofpacket
wire cmd_xbar_demux_src4_valid; // cmd_xbar_demux:src4_valid -> cmd_xbar_mux_004:sink0_valid
wire cmd_xbar_demux_src4_startofpacket; // cmd_xbar_demux:src4_startofpacket -> cmd_xbar_mux_004:sink0_startofpacket
wire [104:0] cmd_xbar_demux_src4_data; // cmd_xbar_demux:src4_data -> cmd_xbar_mux_004:sink0_data
wire [7:0] cmd_xbar_demux_src4_channel; // cmd_xbar_demux:src4_channel -> cmd_xbar_mux_004:sink0_channel
wire cmd_xbar_demux_src4_ready; // cmd_xbar_mux_004:sink0_ready -> cmd_xbar_demux:src4_ready
wire cmd_xbar_demux_001_src0_endofpacket; // cmd_xbar_demux_001:src0_endofpacket -> cmd_xbar_mux:sink1_endofpacket
wire cmd_xbar_demux_001_src0_valid; // cmd_xbar_demux_001:src0_valid -> cmd_xbar_mux:sink1_valid
wire cmd_xbar_demux_001_src0_startofpacket; // cmd_xbar_demux_001:src0_startofpacket -> cmd_xbar_mux:sink1_startofpacket
wire [104:0] cmd_xbar_demux_001_src0_data; // cmd_xbar_demux_001:src0_data -> cmd_xbar_mux:sink1_data
wire [7:0] cmd_xbar_demux_001_src0_channel; // cmd_xbar_demux_001:src0_channel -> cmd_xbar_mux:sink1_channel
wire cmd_xbar_demux_001_src0_ready; // cmd_xbar_mux:sink1_ready -> cmd_xbar_demux_001:src0_ready
wire cmd_xbar_demux_001_src1_endofpacket; // cmd_xbar_demux_001:src1_endofpacket -> cmd_xbar_mux_001:sink1_endofpacket
wire cmd_xbar_demux_001_src1_valid; // cmd_xbar_demux_001:src1_valid -> cmd_xbar_mux_001:sink1_valid
wire cmd_xbar_demux_001_src1_startofpacket; // cmd_xbar_demux_001:src1_startofpacket -> cmd_xbar_mux_001:sink1_startofpacket
wire [104:0] cmd_xbar_demux_001_src1_data; // cmd_xbar_demux_001:src1_data -> cmd_xbar_mux_001:sink1_data
wire [7:0] cmd_xbar_demux_001_src1_channel; // cmd_xbar_demux_001:src1_channel -> cmd_xbar_mux_001:sink1_channel
wire cmd_xbar_demux_001_src1_ready; // cmd_xbar_mux_001:sink1_ready -> cmd_xbar_demux_001:src1_ready
wire cmd_xbar_demux_001_src2_endofpacket; // cmd_xbar_demux_001:src2_endofpacket -> cmd_xbar_mux_002:sink1_endofpacket
wire cmd_xbar_demux_001_src2_valid; // cmd_xbar_demux_001:src2_valid -> cmd_xbar_mux_002:sink1_valid
wire cmd_xbar_demux_001_src2_startofpacket; // cmd_xbar_demux_001:src2_startofpacket -> cmd_xbar_mux_002:sink1_startofpacket
wire [104:0] cmd_xbar_demux_001_src2_data; // cmd_xbar_demux_001:src2_data -> cmd_xbar_mux_002:sink1_data
wire [7:0] cmd_xbar_demux_001_src2_channel; // cmd_xbar_demux_001:src2_channel -> cmd_xbar_mux_002:sink1_channel
wire cmd_xbar_demux_001_src2_ready; // cmd_xbar_mux_002:sink1_ready -> cmd_xbar_demux_001:src2_ready
wire cmd_xbar_demux_001_src3_endofpacket; // cmd_xbar_demux_001:src3_endofpacket -> cmd_xbar_mux_003:sink1_endofpacket
wire cmd_xbar_demux_001_src3_valid; // cmd_xbar_demux_001:src3_valid -> cmd_xbar_mux_003:sink1_valid
wire cmd_xbar_demux_001_src3_startofpacket; // cmd_xbar_demux_001:src3_startofpacket -> cmd_xbar_mux_003:sink1_startofpacket
wire [104:0] cmd_xbar_demux_001_src3_data; // cmd_xbar_demux_001:src3_data -> cmd_xbar_mux_003:sink1_data
wire [7:0] cmd_xbar_demux_001_src3_channel; // cmd_xbar_demux_001:src3_channel -> cmd_xbar_mux_003:sink1_channel
wire cmd_xbar_demux_001_src3_ready; // cmd_xbar_mux_003:sink1_ready -> cmd_xbar_demux_001:src3_ready
wire cmd_xbar_demux_001_src4_endofpacket; // cmd_xbar_demux_001:src4_endofpacket -> cmd_xbar_mux_004:sink1_endofpacket
wire cmd_xbar_demux_001_src4_valid; // cmd_xbar_demux_001:src4_valid -> cmd_xbar_mux_004:sink1_valid
wire cmd_xbar_demux_001_src4_startofpacket; // cmd_xbar_demux_001:src4_startofpacket -> cmd_xbar_mux_004:sink1_startofpacket
wire [104:0] cmd_xbar_demux_001_src4_data; // cmd_xbar_demux_001:src4_data -> cmd_xbar_mux_004:sink1_data
wire [7:0] cmd_xbar_demux_001_src4_channel; // cmd_xbar_demux_001:src4_channel -> cmd_xbar_mux_004:sink1_channel
wire cmd_xbar_demux_001_src4_ready; // cmd_xbar_mux_004:sink1_ready -> cmd_xbar_demux_001:src4_ready
wire cmd_xbar_demux_001_src5_endofpacket; // cmd_xbar_demux_001:src5_endofpacket -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_001_src5_valid; // cmd_xbar_demux_001:src5_valid -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_001_src5_startofpacket; // cmd_xbar_demux_001:src5_startofpacket -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [104:0] cmd_xbar_demux_001_src5_data; // cmd_xbar_demux_001:src5_data -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:cp_data
wire [7:0] cmd_xbar_demux_001_src5_channel; // cmd_xbar_demux_001:src5_channel -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_001_src6_endofpacket; // cmd_xbar_demux_001:src6_endofpacket -> cmd_xbar_mux_006:sink0_endofpacket
wire cmd_xbar_demux_001_src6_valid; // cmd_xbar_demux_001:src6_valid -> cmd_xbar_mux_006:sink0_valid
wire cmd_xbar_demux_001_src6_startofpacket; // cmd_xbar_demux_001:src6_startofpacket -> cmd_xbar_mux_006:sink0_startofpacket
wire [104:0] cmd_xbar_demux_001_src6_data; // cmd_xbar_demux_001:src6_data -> cmd_xbar_mux_006:sink0_data
wire [7:0] cmd_xbar_demux_001_src6_channel; // cmd_xbar_demux_001:src6_channel -> cmd_xbar_mux_006:sink0_channel
wire cmd_xbar_demux_001_src6_ready; // cmd_xbar_mux_006:sink0_ready -> cmd_xbar_demux_001:src6_ready
wire cmd_xbar_demux_001_src7_endofpacket; // cmd_xbar_demux_001:src7_endofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_001_src7_valid; // cmd_xbar_demux_001:src7_valid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_001_src7_startofpacket; // cmd_xbar_demux_001:src7_startofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [104:0] cmd_xbar_demux_001_src7_data; // cmd_xbar_demux_001:src7_data -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_data
wire [7:0] cmd_xbar_demux_001_src7_channel; // cmd_xbar_demux_001:src7_channel -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_002_src0_endofpacket; // cmd_xbar_demux_002:src0_endofpacket -> cmd_xbar_mux_006:sink1_endofpacket
wire cmd_xbar_demux_002_src0_valid; // cmd_xbar_demux_002:src0_valid -> cmd_xbar_mux_006:sink1_valid
wire cmd_xbar_demux_002_src0_startofpacket; // cmd_xbar_demux_002:src0_startofpacket -> cmd_xbar_mux_006:sink1_startofpacket
wire [104:0] cmd_xbar_demux_002_src0_data; // cmd_xbar_demux_002:src0_data -> cmd_xbar_mux_006:sink1_data
wire [7:0] cmd_xbar_demux_002_src0_channel; // cmd_xbar_demux_002:src0_channel -> cmd_xbar_mux_006:sink1_channel
wire cmd_xbar_demux_002_src0_ready; // cmd_xbar_mux_006:sink1_ready -> cmd_xbar_demux_002:src0_ready
wire rsp_xbar_demux_src0_endofpacket; // rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket
wire rsp_xbar_demux_src0_valid; // rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid
wire rsp_xbar_demux_src0_startofpacket; // rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket
wire [104:0] rsp_xbar_demux_src0_data; // rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data
wire [7:0] rsp_xbar_demux_src0_channel; // rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel
wire rsp_xbar_demux_src0_ready; // rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready
wire rsp_xbar_demux_src1_endofpacket; // rsp_xbar_demux:src1_endofpacket -> rsp_xbar_mux_001:sink0_endofpacket
wire rsp_xbar_demux_src1_valid; // rsp_xbar_demux:src1_valid -> rsp_xbar_mux_001:sink0_valid
wire rsp_xbar_demux_src1_startofpacket; // rsp_xbar_demux:src1_startofpacket -> rsp_xbar_mux_001:sink0_startofpacket
wire [104:0] rsp_xbar_demux_src1_data; // rsp_xbar_demux:src1_data -> rsp_xbar_mux_001:sink0_data
wire [7:0] rsp_xbar_demux_src1_channel; // rsp_xbar_demux:src1_channel -> rsp_xbar_mux_001:sink0_channel
wire rsp_xbar_demux_src1_ready; // rsp_xbar_mux_001:sink0_ready -> rsp_xbar_demux:src1_ready
wire rsp_xbar_demux_001_src0_endofpacket; // rsp_xbar_demux_001:src0_endofpacket -> rsp_xbar_mux:sink1_endofpacket
wire rsp_xbar_demux_001_src0_valid; // rsp_xbar_demux_001:src0_valid -> rsp_xbar_mux:sink1_valid
wire rsp_xbar_demux_001_src0_startofpacket; // rsp_xbar_demux_001:src0_startofpacket -> rsp_xbar_mux:sink1_startofpacket
wire [104:0] rsp_xbar_demux_001_src0_data; // rsp_xbar_demux_001:src0_data -> rsp_xbar_mux:sink1_data
wire [7:0] rsp_xbar_demux_001_src0_channel; // rsp_xbar_demux_001:src0_channel -> rsp_xbar_mux:sink1_channel
wire rsp_xbar_demux_001_src0_ready; // rsp_xbar_mux:sink1_ready -> rsp_xbar_demux_001:src0_ready
wire rsp_xbar_demux_001_src1_endofpacket; // rsp_xbar_demux_001:src1_endofpacket -> rsp_xbar_mux_001:sink1_endofpacket
wire rsp_xbar_demux_001_src1_valid; // rsp_xbar_demux_001:src1_valid -> rsp_xbar_mux_001:sink1_valid
wire rsp_xbar_demux_001_src1_startofpacket; // rsp_xbar_demux_001:src1_startofpacket -> rsp_xbar_mux_001:sink1_startofpacket
wire [104:0] rsp_xbar_demux_001_src1_data; // rsp_xbar_demux_001:src1_data -> rsp_xbar_mux_001:sink1_data
wire [7:0] rsp_xbar_demux_001_src1_channel; // rsp_xbar_demux_001:src1_channel -> rsp_xbar_mux_001:sink1_channel
wire rsp_xbar_demux_001_src1_ready; // rsp_xbar_mux_001:sink1_ready -> rsp_xbar_demux_001:src1_ready
wire rsp_xbar_demux_002_src0_endofpacket; // rsp_xbar_demux_002:src0_endofpacket -> rsp_xbar_mux:sink2_endofpacket
wire rsp_xbar_demux_002_src0_valid; // rsp_xbar_demux_002:src0_valid -> rsp_xbar_mux:sink2_valid
wire rsp_xbar_demux_002_src0_startofpacket; // rsp_xbar_demux_002:src0_startofpacket -> rsp_xbar_mux:sink2_startofpacket
wire [104:0] rsp_xbar_demux_002_src0_data; // rsp_xbar_demux_002:src0_data -> rsp_xbar_mux:sink2_data
wire [7:0] rsp_xbar_demux_002_src0_channel; // rsp_xbar_demux_002:src0_channel -> rsp_xbar_mux:sink2_channel
wire rsp_xbar_demux_002_src0_ready; // rsp_xbar_mux:sink2_ready -> rsp_xbar_demux_002:src0_ready
wire rsp_xbar_demux_002_src1_endofpacket; // rsp_xbar_demux_002:src1_endofpacket -> rsp_xbar_mux_001:sink2_endofpacket
wire rsp_xbar_demux_002_src1_valid; // rsp_xbar_demux_002:src1_valid -> rsp_xbar_mux_001:sink2_valid
wire rsp_xbar_demux_002_src1_startofpacket; // rsp_xbar_demux_002:src1_startofpacket -> rsp_xbar_mux_001:sink2_startofpacket
wire [104:0] rsp_xbar_demux_002_src1_data; // rsp_xbar_demux_002:src1_data -> rsp_xbar_mux_001:sink2_data
wire [7:0] rsp_xbar_demux_002_src1_channel; // rsp_xbar_demux_002:src1_channel -> rsp_xbar_mux_001:sink2_channel
wire rsp_xbar_demux_002_src1_ready; // rsp_xbar_mux_001:sink2_ready -> rsp_xbar_demux_002:src1_ready
wire rsp_xbar_demux_003_src0_endofpacket; // rsp_xbar_demux_003:src0_endofpacket -> rsp_xbar_mux:sink3_endofpacket
wire rsp_xbar_demux_003_src0_valid; // rsp_xbar_demux_003:src0_valid -> rsp_xbar_mux:sink3_valid
wire rsp_xbar_demux_003_src0_startofpacket; // rsp_xbar_demux_003:src0_startofpacket -> rsp_xbar_mux:sink3_startofpacket
wire [104:0] rsp_xbar_demux_003_src0_data; // rsp_xbar_demux_003:src0_data -> rsp_xbar_mux:sink3_data
wire [7:0] rsp_xbar_demux_003_src0_channel; // rsp_xbar_demux_003:src0_channel -> rsp_xbar_mux:sink3_channel
wire rsp_xbar_demux_003_src0_ready; // rsp_xbar_mux:sink3_ready -> rsp_xbar_demux_003:src0_ready
wire rsp_xbar_demux_003_src1_endofpacket; // rsp_xbar_demux_003:src1_endofpacket -> rsp_xbar_mux_001:sink3_endofpacket
wire rsp_xbar_demux_003_src1_valid; // rsp_xbar_demux_003:src1_valid -> rsp_xbar_mux_001:sink3_valid
wire rsp_xbar_demux_003_src1_startofpacket; // rsp_xbar_demux_003:src1_startofpacket -> rsp_xbar_mux_001:sink3_startofpacket
wire [104:0] rsp_xbar_demux_003_src1_data; // rsp_xbar_demux_003:src1_data -> rsp_xbar_mux_001:sink3_data
wire [7:0] rsp_xbar_demux_003_src1_channel; // rsp_xbar_demux_003:src1_channel -> rsp_xbar_mux_001:sink3_channel
wire rsp_xbar_demux_003_src1_ready; // rsp_xbar_mux_001:sink3_ready -> rsp_xbar_demux_003:src1_ready
wire rsp_xbar_demux_004_src0_endofpacket; // rsp_xbar_demux_004:src0_endofpacket -> rsp_xbar_mux:sink4_endofpacket
wire rsp_xbar_demux_004_src0_valid; // rsp_xbar_demux_004:src0_valid -> rsp_xbar_mux:sink4_valid
wire rsp_xbar_demux_004_src0_startofpacket; // rsp_xbar_demux_004:src0_startofpacket -> rsp_xbar_mux:sink4_startofpacket
wire [104:0] rsp_xbar_demux_004_src0_data; // rsp_xbar_demux_004:src0_data -> rsp_xbar_mux:sink4_data
wire [7:0] rsp_xbar_demux_004_src0_channel; // rsp_xbar_demux_004:src0_channel -> rsp_xbar_mux:sink4_channel
wire rsp_xbar_demux_004_src0_ready; // rsp_xbar_mux:sink4_ready -> rsp_xbar_demux_004:src0_ready
wire rsp_xbar_demux_004_src1_endofpacket; // rsp_xbar_demux_004:src1_endofpacket -> rsp_xbar_mux_001:sink4_endofpacket
wire rsp_xbar_demux_004_src1_valid; // rsp_xbar_demux_004:src1_valid -> rsp_xbar_mux_001:sink4_valid
wire rsp_xbar_demux_004_src1_startofpacket; // rsp_xbar_demux_004:src1_startofpacket -> rsp_xbar_mux_001:sink4_startofpacket
wire [104:0] rsp_xbar_demux_004_src1_data; // rsp_xbar_demux_004:src1_data -> rsp_xbar_mux_001:sink4_data
wire [7:0] rsp_xbar_demux_004_src1_channel; // rsp_xbar_demux_004:src1_channel -> rsp_xbar_mux_001:sink4_channel
wire rsp_xbar_demux_004_src1_ready; // rsp_xbar_mux_001:sink4_ready -> rsp_xbar_demux_004:src1_ready
wire rsp_xbar_demux_005_src0_endofpacket; // rsp_xbar_demux_005:src0_endofpacket -> rsp_xbar_mux_001:sink5_endofpacket
wire rsp_xbar_demux_005_src0_valid; // rsp_xbar_demux_005:src0_valid -> rsp_xbar_mux_001:sink5_valid
wire rsp_xbar_demux_005_src0_startofpacket; // rsp_xbar_demux_005:src0_startofpacket -> rsp_xbar_mux_001:sink5_startofpacket
wire [104:0] rsp_xbar_demux_005_src0_data; // rsp_xbar_demux_005:src0_data -> rsp_xbar_mux_001:sink5_data
wire [7:0] rsp_xbar_demux_005_src0_channel; // rsp_xbar_demux_005:src0_channel -> rsp_xbar_mux_001:sink5_channel
wire rsp_xbar_demux_005_src0_ready; // rsp_xbar_mux_001:sink5_ready -> rsp_xbar_demux_005:src0_ready
wire rsp_xbar_demux_006_src0_endofpacket; // rsp_xbar_demux_006:src0_endofpacket -> rsp_xbar_mux_001:sink6_endofpacket
wire rsp_xbar_demux_006_src0_valid; // rsp_xbar_demux_006:src0_valid -> rsp_xbar_mux_001:sink6_valid
wire rsp_xbar_demux_006_src0_startofpacket; // rsp_xbar_demux_006:src0_startofpacket -> rsp_xbar_mux_001:sink6_startofpacket
wire [104:0] rsp_xbar_demux_006_src0_data; // rsp_xbar_demux_006:src0_data -> rsp_xbar_mux_001:sink6_data
wire [7:0] rsp_xbar_demux_006_src0_channel; // rsp_xbar_demux_006:src0_channel -> rsp_xbar_mux_001:sink6_channel
wire rsp_xbar_demux_006_src0_ready; // rsp_xbar_mux_001:sink6_ready -> rsp_xbar_demux_006:src0_ready
wire rsp_xbar_demux_006_src1_endofpacket; // rsp_xbar_demux_006:src1_endofpacket -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:rp_endofpacket
wire rsp_xbar_demux_006_src1_valid; // rsp_xbar_demux_006:src1_valid -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:rp_valid
wire rsp_xbar_demux_006_src1_startofpacket; // rsp_xbar_demux_006:src1_startofpacket -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:rp_startofpacket
wire [104:0] rsp_xbar_demux_006_src1_data; // rsp_xbar_demux_006:src1_data -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:rp_data
wire [7:0] rsp_xbar_demux_006_src1_channel; // rsp_xbar_demux_006:src1_channel -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:rp_channel
wire rsp_xbar_demux_007_src0_endofpacket; // rsp_xbar_demux_007:src0_endofpacket -> rsp_xbar_mux_001:sink7_endofpacket
wire rsp_xbar_demux_007_src0_valid; // rsp_xbar_demux_007:src0_valid -> rsp_xbar_mux_001:sink7_valid
wire rsp_xbar_demux_007_src0_startofpacket; // rsp_xbar_demux_007:src0_startofpacket -> rsp_xbar_mux_001:sink7_startofpacket
wire [104:0] rsp_xbar_demux_007_src0_data; // rsp_xbar_demux_007:src0_data -> rsp_xbar_mux_001:sink7_data
wire [7:0] rsp_xbar_demux_007_src0_channel; // rsp_xbar_demux_007:src0_channel -> rsp_xbar_mux_001:sink7_channel
wire rsp_xbar_demux_007_src0_ready; // rsp_xbar_mux_001:sink7_ready -> rsp_xbar_demux_007:src0_ready
wire limiter_cmd_src_endofpacket; // limiter:cmd_src_endofpacket -> cmd_xbar_demux:sink_endofpacket
wire limiter_cmd_src_startofpacket; // limiter:cmd_src_startofpacket -> cmd_xbar_demux:sink_startofpacket
wire [104:0] limiter_cmd_src_data; // limiter:cmd_src_data -> cmd_xbar_demux:sink_data
wire [7:0] limiter_cmd_src_channel; // limiter:cmd_src_channel -> cmd_xbar_demux:sink_channel
wire limiter_cmd_src_ready; // cmd_xbar_demux:sink_ready -> limiter:cmd_src_ready
wire rsp_xbar_mux_src_endofpacket; // rsp_xbar_mux:src_endofpacket -> limiter:rsp_sink_endofpacket
wire rsp_xbar_mux_src_valid; // rsp_xbar_mux:src_valid -> limiter:rsp_sink_valid
wire rsp_xbar_mux_src_startofpacket; // rsp_xbar_mux:src_startofpacket -> limiter:rsp_sink_startofpacket
wire [104:0] rsp_xbar_mux_src_data; // rsp_xbar_mux:src_data -> limiter:rsp_sink_data
wire [7:0] rsp_xbar_mux_src_channel; // rsp_xbar_mux:src_channel -> limiter:rsp_sink_channel
wire rsp_xbar_mux_src_ready; // limiter:rsp_sink_ready -> rsp_xbar_mux:src_ready
wire limiter_001_cmd_src_endofpacket; // limiter_001:cmd_src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket
wire limiter_001_cmd_src_startofpacket; // limiter_001:cmd_src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket
wire [104:0] limiter_001_cmd_src_data; // limiter_001:cmd_src_data -> cmd_xbar_demux_001:sink_data
wire [7:0] limiter_001_cmd_src_channel; // limiter_001:cmd_src_channel -> cmd_xbar_demux_001:sink_channel
wire limiter_001_cmd_src_ready; // cmd_xbar_demux_001:sink_ready -> limiter_001:cmd_src_ready
wire rsp_xbar_mux_001_src_endofpacket; // rsp_xbar_mux_001:src_endofpacket -> limiter_001:rsp_sink_endofpacket
wire rsp_xbar_mux_001_src_valid; // rsp_xbar_mux_001:src_valid -> limiter_001:rsp_sink_valid
wire rsp_xbar_mux_001_src_startofpacket; // rsp_xbar_mux_001:src_startofpacket -> limiter_001:rsp_sink_startofpacket
wire [104:0] rsp_xbar_mux_001_src_data; // rsp_xbar_mux_001:src_data -> limiter_001:rsp_sink_data
wire [7:0] rsp_xbar_mux_001_src_channel; // rsp_xbar_mux_001:src_channel -> limiter_001:rsp_sink_channel
wire rsp_xbar_mux_001_src_ready; // limiter_001:rsp_sink_ready -> rsp_xbar_mux_001:src_ready
wire addr_router_002_src_endofpacket; // addr_router_002:src_endofpacket -> cmd_xbar_demux_002:sink_endofpacket
wire addr_router_002_src_valid; // addr_router_002:src_valid -> cmd_xbar_demux_002:sink_valid
wire addr_router_002_src_startofpacket; // addr_router_002:src_startofpacket -> cmd_xbar_demux_002:sink_startofpacket
wire [104:0] addr_router_002_src_data; // addr_router_002:src_data -> cmd_xbar_demux_002:sink_data
wire [7:0] addr_router_002_src_channel; // addr_router_002:src_channel -> cmd_xbar_demux_002:sink_channel
wire addr_router_002_src_ready; // cmd_xbar_demux_002:sink_ready -> addr_router_002:src_ready
wire rsp_xbar_demux_006_src1_ready; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_demux_006:src1_ready
wire cmd_xbar_mux_src_endofpacket; // cmd_xbar_mux:src_endofpacket -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_mux_src_valid; // cmd_xbar_mux:src_valid -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_mux_src_startofpacket; // cmd_xbar_mux:src_startofpacket -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [104:0] cmd_xbar_mux_src_data; // cmd_xbar_mux:src_data -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_data
wire [7:0] cmd_xbar_mux_src_channel; // cmd_xbar_mux:src_channel -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_mux_src_ready; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux:src_ready
wire id_router_src_endofpacket; // id_router:src_endofpacket -> rsp_xbar_demux:sink_endofpacket
wire id_router_src_valid; // id_router:src_valid -> rsp_xbar_demux:sink_valid
wire id_router_src_startofpacket; // id_router:src_startofpacket -> rsp_xbar_demux:sink_startofpacket
wire [104:0] id_router_src_data; // id_router:src_data -> rsp_xbar_demux:sink_data
wire [7:0] id_router_src_channel; // id_router:src_channel -> rsp_xbar_demux:sink_channel
wire id_router_src_ready; // rsp_xbar_demux:sink_ready -> id_router:src_ready
wire cmd_xbar_mux_001_src_endofpacket; // cmd_xbar_mux_001:src_endofpacket -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_mux_001_src_valid; // cmd_xbar_mux_001:src_valid -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_mux_001_src_startofpacket; // cmd_xbar_mux_001:src_startofpacket -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [104:0] cmd_xbar_mux_001_src_data; // cmd_xbar_mux_001:src_data -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent:cp_data
wire [7:0] cmd_xbar_mux_001_src_channel; // cmd_xbar_mux_001:src_channel -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_mux_001_src_ready; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_001:src_ready
wire id_router_001_src_endofpacket; // id_router_001:src_endofpacket -> rsp_xbar_demux_001:sink_endofpacket
wire id_router_001_src_valid; // id_router_001:src_valid -> rsp_xbar_demux_001:sink_valid
wire id_router_001_src_startofpacket; // id_router_001:src_startofpacket -> rsp_xbar_demux_001:sink_startofpacket
wire [104:0] id_router_001_src_data; // id_router_001:src_data -> rsp_xbar_demux_001:sink_data
wire [7:0] id_router_001_src_channel; // id_router_001:src_channel -> rsp_xbar_demux_001:sink_channel
wire id_router_001_src_ready; // rsp_xbar_demux_001:sink_ready -> id_router_001:src_ready
wire cmd_xbar_mux_002_src_endofpacket; // cmd_xbar_mux_002:src_endofpacket -> sysid_control_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_mux_002_src_valid; // cmd_xbar_mux_002:src_valid -> sysid_control_slave_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_mux_002_src_startofpacket; // cmd_xbar_mux_002:src_startofpacket -> sysid_control_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [104:0] cmd_xbar_mux_002_src_data; // cmd_xbar_mux_002:src_data -> sysid_control_slave_translator_avalon_universal_slave_0_agent:cp_data
wire [7:0] cmd_xbar_mux_002_src_channel; // cmd_xbar_mux_002:src_channel -> sysid_control_slave_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_mux_002_src_ready; // sysid_control_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_002:src_ready
wire id_router_002_src_endofpacket; // id_router_002:src_endofpacket -> rsp_xbar_demux_002:sink_endofpacket
wire id_router_002_src_valid; // id_router_002:src_valid -> rsp_xbar_demux_002:sink_valid
wire id_router_002_src_startofpacket; // id_router_002:src_startofpacket -> rsp_xbar_demux_002:sink_startofpacket
wire [104:0] id_router_002_src_data; // id_router_002:src_data -> rsp_xbar_demux_002:sink_data
wire [7:0] id_router_002_src_channel; // id_router_002:src_channel -> rsp_xbar_demux_002:sink_channel
wire id_router_002_src_ready; // rsp_xbar_demux_002:sink_ready -> id_router_002:src_ready
wire cmd_xbar_mux_003_src_endofpacket; // cmd_xbar_mux_003:src_endofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_mux_003_src_valid; // cmd_xbar_mux_003:src_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_mux_003_src_startofpacket; // cmd_xbar_mux_003:src_startofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [104:0] cmd_xbar_mux_003_src_data; // cmd_xbar_mux_003:src_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_data
wire [7:0] cmd_xbar_mux_003_src_channel; // cmd_xbar_mux_003:src_channel -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_mux_003_src_ready; // sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_003:src_ready
wire id_router_003_src_endofpacket; // id_router_003:src_endofpacket -> rsp_xbar_demux_003:sink_endofpacket
wire id_router_003_src_valid; // id_router_003:src_valid -> rsp_xbar_demux_003:sink_valid
wire id_router_003_src_startofpacket; // id_router_003:src_startofpacket -> rsp_xbar_demux_003:sink_startofpacket
wire [104:0] id_router_003_src_data; // id_router_003:src_data -> rsp_xbar_demux_003:sink_data
wire [7:0] id_router_003_src_channel; // id_router_003:src_channel -> rsp_xbar_demux_003:sink_channel
wire id_router_003_src_ready; // rsp_xbar_demux_003:sink_ready -> id_router_003:src_ready
wire cmd_xbar_mux_004_src_endofpacket; // cmd_xbar_mux_004:src_endofpacket -> controller1_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_mux_004_src_valid; // cmd_xbar_mux_004:src_valid -> controller1_s1_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_mux_004_src_startofpacket; // cmd_xbar_mux_004:src_startofpacket -> controller1_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [104:0] cmd_xbar_mux_004_src_data; // cmd_xbar_mux_004:src_data -> controller1_s1_translator_avalon_universal_slave_0_agent:cp_data
wire [7:0] cmd_xbar_mux_004_src_channel; // cmd_xbar_mux_004:src_channel -> controller1_s1_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_mux_004_src_ready; // controller1_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_004:src_ready
wire id_router_004_src_endofpacket; // id_router_004:src_endofpacket -> rsp_xbar_demux_004:sink_endofpacket
wire id_router_004_src_valid; // id_router_004:src_valid -> rsp_xbar_demux_004:sink_valid
wire id_router_004_src_startofpacket; // id_router_004:src_startofpacket -> rsp_xbar_demux_004:sink_startofpacket
wire [104:0] id_router_004_src_data; // id_router_004:src_data -> rsp_xbar_demux_004:sink_data
wire [7:0] id_router_004_src_channel; // id_router_004:src_channel -> rsp_xbar_demux_004:sink_channel
wire id_router_004_src_ready; // rsp_xbar_demux_004:sink_ready -> id_router_004:src_ready
wire cmd_xbar_demux_001_src5_ready; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src5_ready
wire id_router_005_src_endofpacket; // id_router_005:src_endofpacket -> rsp_xbar_demux_005:sink_endofpacket
wire id_router_005_src_valid; // id_router_005:src_valid -> rsp_xbar_demux_005:sink_valid
wire id_router_005_src_startofpacket; // id_router_005:src_startofpacket -> rsp_xbar_demux_005:sink_startofpacket
wire [104:0] id_router_005_src_data; // id_router_005:src_data -> rsp_xbar_demux_005:sink_data
wire [7:0] id_router_005_src_channel; // id_router_005:src_channel -> rsp_xbar_demux_005:sink_channel
wire id_router_005_src_ready; // rsp_xbar_demux_005:sink_ready -> id_router_005:src_ready
wire cmd_xbar_mux_006_src_endofpacket; // cmd_xbar_mux_006:src_endofpacket -> Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_mux_006_src_valid; // cmd_xbar_mux_006:src_valid -> Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_mux_006_src_startofpacket; // cmd_xbar_mux_006:src_startofpacket -> Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [104:0] cmd_xbar_mux_006_src_data; // cmd_xbar_mux_006:src_data -> Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent:cp_data
wire [7:0] cmd_xbar_mux_006_src_channel; // cmd_xbar_mux_006:src_channel -> Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_mux_006_src_ready; // Pixel_Buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_006:src_ready
wire id_router_006_src_endofpacket; // id_router_006:src_endofpacket -> rsp_xbar_demux_006:sink_endofpacket
wire id_router_006_src_valid; // id_router_006:src_valid -> rsp_xbar_demux_006:sink_valid
wire id_router_006_src_startofpacket; // id_router_006:src_startofpacket -> rsp_xbar_demux_006:sink_startofpacket
wire [104:0] id_router_006_src_data; // id_router_006:src_data -> rsp_xbar_demux_006:sink_data
wire [7:0] id_router_006_src_channel; // id_router_006:src_channel -> rsp_xbar_demux_006:sink_channel
wire id_router_006_src_ready; // rsp_xbar_demux_006:sink_ready -> id_router_006:src_ready
wire cmd_xbar_demux_001_src7_ready; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src7_ready
wire id_router_007_src_endofpacket; // id_router_007:src_endofpacket -> rsp_xbar_demux_007:sink_endofpacket
wire id_router_007_src_valid; // id_router_007:src_valid -> rsp_xbar_demux_007:sink_valid
wire id_router_007_src_startofpacket; // id_router_007:src_startofpacket -> rsp_xbar_demux_007:sink_startofpacket
wire [104:0] id_router_007_src_data; // id_router_007:src_data -> rsp_xbar_demux_007:sink_data
wire [7:0] id_router_007_src_channel; // id_router_007:src_channel -> rsp_xbar_demux_007:sink_channel
wire id_router_007_src_ready; // rsp_xbar_demux_007:sink_ready -> id_router_007:src_ready
wire [7:0] limiter_cmd_valid_data; // limiter:cmd_src_valid -> cmd_xbar_demux:sink_valid
wire [7:0] limiter_001_cmd_valid_data; // limiter_001:cmd_src_valid -> cmd_xbar_demux_001:sink_valid
wire irq_mapper_receiver0_irq; // jtag_uart:av_irq -> irq_mapper:receiver0_irq
wire [31:0] cpu_d_irq_irq; // irq_mapper:sender_irq -> CPU:d_irq
nios_system_Dual_Clock_FIFO dual_clock_fifo (
.clk_stream_in (clock_signals_sys_clk_clk), // clock_stream_in.clk
.reset_stream_in (rst_controller_reset_out_reset), // clock_stream_in_reset.reset
.clk_stream_out (clock_signals_vga_clk_clk), // clock_stream_out.clk
.reset_stream_out (rst_controller_001_reset_out_reset), // clock_stream_out_reset.reset
.stream_in_ready (pixel_buffer_dma_avalon_pixel_source_ready), // avalon_dc_buffer_sink.ready
.stream_in_startofpacket (pixel_buffer_dma_avalon_pixel_source_startofpacket), // .startofpacket
.stream_in_endofpacket (pixel_buffer_dma_avalon_pixel_source_endofpacket), // .endofpacket
.stream_in_valid (pixel_buffer_dma_avalon_pixel_source_valid), // .valid
.stream_in_data (pixel_buffer_dma_avalon_pixel_source_data), // .data
.stream_out_ready (dual_clock_fifo_avalon_dc_buffer_source_ready), // avalon_dc_buffer_source.ready
.stream_out_startofpacket (dual_clock_fifo_avalon_dc_buffer_source_startofpacket), // .startofpacket
.stream_out_endofpacket (dual_clock_fifo_avalon_dc_buffer_source_endofpacket), // .endofpacket
.stream_out_valid (dual_clock_fifo_avalon_dc_buffer_source_valid), // .valid
.stream_out_data (dual_clock_fifo_avalon_dc_buffer_source_data) // .data
);
nios_system_VGA_Controller vga_controller (
.clk (clock_signals_vga_clk_clk), // clock_reset.clk
.reset (rst_controller_001_reset_out_reset), // clock_reset_reset.reset
.data (dual_clock_fifo_avalon_dc_buffer_source_data), // avalon_vga_sink.data
.startofpacket (dual_clock_fifo_avalon_dc_buffer_source_startofpacket), // .startofpacket
.endofpacket (dual_clock_fifo_avalon_dc_buffer_source_endofpacket), // .endofpacket
.valid (dual_clock_fifo_avalon_dc_buffer_source_valid), // .valid
.ready (dual_clock_fifo_avalon_dc_buffer_source_ready), // .ready
.VGA_CLK (VGA_CLK_from_the_VGA_Controller), // external_interface.export
.VGA_HS (VGA_HS_from_the_VGA_Controller), // .export
.VGA_VS (VGA_VS_from_the_VGA_Controller), // .export
.VGA_BLANK (VGA_BLANK_from_the_VGA_Controller), // .export
.VGA_SYNC (VGA_SYNC_from_the_VGA_Controller), // .export
.VGA_R (VGA_R_from_the_VGA_Controller), // .export
.VGA_G (VGA_G_from_the_VGA_Controller), // .export
.VGA_B (VGA_B_from_the_VGA_Controller) // .export
);
nios_system_Pixel_Buffer pixel_buffer (
.clk (clock_signals_sys_clk_clk), // clock_reset.clk
.reset (rst_controller_reset_out_reset), // clock_reset_reset.reset
.SRAM_DQ (SRAM_DQ_to_and_from_the_Pixel_Buffer), // external_interface.export
.SRAM_DPA (Pixel_Buffer_external_interface_DPA), // .export
.SRAM_ADDR (SRAM_ADDR_from_the_Pixel_Buffer), // .export
.SRAM_ADSC_N (Pixel_Buffer_external_interface_ADSC_N), // .export
.SRAM_ADSP_N (Pixel_Buffer_external_interface_ADSP_N), // .export
.SRAM_ADV_N (Pixel_Buffer_external_interface_ADV_N), // .export
.SRAM_BE_N (Pixel_Buffer_external_interface_BE_N), // .export
.SRAM_CE1_N (Pixel_Buffer_external_interface_CE1_N), // .export
.SRAM_CE2 (Pixel_Buffer_external_interface_CE2), // .export
.SRAM_CE3_N (Pixel_Buffer_external_interface_CE3_N), // .export
.SRAM_GW_N (Pixel_Buffer_external_interface_GW_N), // .export
.SRAM_OE_N (SRAM_OE_N_from_the_Pixel_Buffer), // .export
.SRAM_WE_N (SRAM_WE_N_from_the_Pixel_Buffer), // .export
.SRAM_CLK (Pixel_Buffer_external_interface_CLK), // .export
.address (pixel_buffer_avalon_ssram_slave_translator_avalon_anti_slave_0_address), // avalon_ssram_slave.address
.byteenable (pixel_buffer_avalon_ssram_slave_translator_avalon_anti_slave_0_byteenable), // .byteenable
.read (pixel_buffer_avalon_ssram_slave_translator_avalon_anti_slave_0_read), // .read
.write (pixel_buffer_avalon_ssram_slave_translator_avalon_anti_slave_0_write), // .write
.writedata (pixel_buffer_avalon_ssram_slave_translator_avalon_anti_slave_0_writedata), // .writedata
.readdata (pixel_buffer_avalon_ssram_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.readdatavalid (pixel_buffer_avalon_ssram_slave_translator_avalon_anti_slave_0_readdatavalid), // .readdatavalid
.waitrequest (pixel_buffer_avalon_ssram_slave_translator_avalon_anti_slave_0_waitrequest) // .waitrequest
);
nios_system_Pixel_Buffer_DMA pixel_buffer_dma (
.clk (clock_signals_sys_clk_clk), // clock_reset.clk
.reset (rst_controller_reset_out_reset), // clock_reset_reset.reset
.master_readdatavalid (pixel_buffer_dma_avalon_pixel_dma_master_readdatavalid), // avalon_pixel_dma_master.readdatavalid
.master_waitrequest (pixel_buffer_dma_avalon_pixel_dma_master_waitrequest), // .waitrequest
.master_address (pixel_buffer_dma_avalon_pixel_dma_master_address), // .address
.master_arbiterlock (pixel_buffer_dma_avalon_pixel_dma_master_lock), // .lock
.master_read (pixel_buffer_dma_avalon_pixel_dma_master_read), // .read
.master_readdata (pixel_buffer_dma_avalon_pixel_dma_master_readdata), // .readdata
.slave_address (pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_address), // avalon_control_slave.address
.slave_byteenable (pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_byteenable), // .byteenable
.slave_read (pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_read), // .read
.slave_write (pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_write), // .write
.slave_writedata (pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_writedata), // .writedata
.slave_readdata (pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.stream_ready (pixel_buffer_dma_avalon_pixel_source_ready), // avalon_pixel_source.ready
.stream_startofpacket (pixel_buffer_dma_avalon_pixel_source_startofpacket), // .startofpacket
.stream_endofpacket (pixel_buffer_dma_avalon_pixel_source_endofpacket), // .endofpacket
.stream_valid (pixel_buffer_dma_avalon_pixel_source_valid), // .valid
.stream_data (pixel_buffer_dma_avalon_pixel_source_data) // .data
);
nios_system_CPU cpu (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset_n.reset_n
.d_address (cpu_data_master_address), // data_master.address
.d_byteenable (cpu_data_master_byteenable), // .byteenable
.d_read (cpu_data_master_read), // .read
.d_readdata (cpu_data_master_readdata), // .readdata
.d_waitrequest (cpu_data_master_waitrequest), // .waitrequest
.d_write (cpu_data_master_write), // .write
.d_writedata (cpu_data_master_writedata), // .writedata
.d_readdatavalid (cpu_data_master_readdatavalid), // .readdatavalid
.jtag_debug_module_debugaccess_to_roms (cpu_data_master_debugaccess), // .debugaccess
.i_address (cpu_instruction_master_address), // instruction_master.address
.i_read (cpu_instruction_master_read), // .read
.i_readdata (cpu_instruction_master_readdata), // .readdata
.i_waitrequest (cpu_instruction_master_waitrequest), // .waitrequest
.i_readdatavalid (cpu_instruction_master_readdatavalid), // .readdatavalid
.d_irq (cpu_d_irq_irq), // d_irq.irq
.jtag_debug_module_resetrequest (cpu_jtag_debug_module_reset_reset), // jtag_debug_module_reset.reset
.jtag_debug_module_address (cpu_jtag_debug_module_translator_avalon_anti_slave_0_address), // jtag_debug_module.address
.jtag_debug_module_begintransfer (cpu_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer), // .begintransfer
.jtag_debug_module_byteenable (cpu_jtag_debug_module_translator_avalon_anti_slave_0_byteenable), // .byteenable
.jtag_debug_module_debugaccess (cpu_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess), // .debugaccess
.jtag_debug_module_readdata (cpu_jtag_debug_module_translator_avalon_anti_slave_0_readdata), // .readdata
.jtag_debug_module_select (cpu_jtag_debug_module_translator_avalon_anti_slave_0_chipselect), // .chipselect
.jtag_debug_module_write (cpu_jtag_debug_module_translator_avalon_anti_slave_0_write), // .write
.jtag_debug_module_writedata (cpu_jtag_debug_module_translator_avalon_anti_slave_0_writedata), // .writedata
.no_ci_readra () // custom_instruction_master.readra
);
nios_system_Clock_Signals clock_signals (
.CLOCK_50 (clk_0), // clk_in_primary.clk
.reset (rst_controller_002_reset_out_reset), // clk_in_primary_reset.reset
.sys_clk (clock_signals_sys_clk_clk), // sys_clk.clk
.sys_reset_n (clock_signals_sys_clk_reset_reset), // sys_clk_reset.reset_n
.SDRAM_CLK (clock_signals_sdram_clk_clk), // sdram_clk.clk
.VGA_CLK (clock_signals_vga_clk_clk) // vga_clk.clk
);
Altera_UP_SD_Card_Avalon_Interface altera_up_sd_card_avalon_interface_0 (
.i_avalon_chip_select (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_anti_slave_0_chipselect), // avalon_sdcard_slave.chipselect
.i_avalon_address (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_anti_slave_0_address), // .address
.i_avalon_read (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_anti_slave_0_read), // .read
.i_avalon_write (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_anti_slave_0_write), // .write
.i_avalon_byteenable (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_anti_slave_0_byteenable), // .byteenable
.i_avalon_writedata (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_anti_slave_0_writedata), // .writedata
.o_avalon_readdata (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.o_avalon_waitrequest (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.i_clock (clock_signals_sys_clk_clk), // clock_sink.clk
.i_reset_n (~rst_controller_003_reset_out_reset), // clock_sink_reset.reset_n
.b_SD_cmd (altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_cmd), // conduit_end.export
.b_SD_dat (altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat), // .export
.b_SD_dat3 (altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat3), // .export
.o_SD_clock (altera_up_sd_card_avalon_interface_0_conduit_end_o_SD_clock) // .export
);
nios_system_jtag_uart jtag_uart (
.clk (clock_signals_sys_clk_clk), // clk.clk
.rst_n (~rst_controller_003_reset_out_reset), // reset.reset_n
.av_chipselect (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect), // avalon_jtag_slave.chipselect
.av_address (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_address), // .address
.av_read_n (~jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_read), // .read_n
.av_readdata (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.av_write_n (~jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_write), // .write_n
.av_writedata (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata), // .writedata
.av_waitrequest (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_irq (irq_mapper_receiver0_irq) // irq.irq
);
nios_system_sysid sysid (
.clock (clock_signals_sys_clk_clk), // clk.clk
.reset_n (~rst_controller_003_reset_out_reset), // reset.reset_n
.readdata (sysid_control_slave_translator_avalon_anti_slave_0_readdata), // control_slave.readdata
.address (sysid_control_slave_translator_avalon_anti_slave_0_address) // .address
);
nios_system_sdram_0 sdram_0 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset_n (clock_signals_sys_clk_reset_reset), // reset.reset_n
.az_addr (sdram_0_s1_translator_avalon_anti_slave_0_address), // s1.address
.az_be_n (~sdram_0_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable_n
.az_cs (sdram_0_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.az_data (sdram_0_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.az_rd_n (~sdram_0_s1_translator_avalon_anti_slave_0_read), // .read_n
.az_wr_n (~sdram_0_s1_translator_avalon_anti_slave_0_write), // .write_n
.za_data (sdram_0_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.za_valid (sdram_0_s1_translator_avalon_anti_slave_0_readdatavalid), // .readdatavalid
.za_waitrequest (sdram_0_s1_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.zs_addr (sdram_0_wire_addr), // wire.export
.zs_ba (sdram_0_wire_ba), // .export
.zs_cas_n (sdram_0_wire_cas_n), // .export
.zs_cke (sdram_0_wire_cke), // .export
.zs_cs_n (sdram_0_wire_cs_n), // .export
.zs_dq (sdram_0_wire_dq), // .export
.zs_dqm (sdram_0_wire_dqm), // .export
.zs_ras_n (sdram_0_wire_ras_n), // .export
.zs_we_n (sdram_0_wire_we_n) // .export
);
nios_system_controller1 controller1 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset_n (~rst_controller_003_reset_out_reset), // reset.reset_n
.address (controller1_s1_translator_avalon_anti_slave_0_address), // s1.address
.readdata (controller1_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.in_port (controller1_external_connection_export) // external_connection.export
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (28),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (1),
.AV_REGISTERINCOMINGSIGNALS (0)
) cpu_instruction_master_translator (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (cpu_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (cpu_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (cpu_instruction_master_translator_avalon_universal_master_0_read), // .read
.uav_write (cpu_instruction_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (cpu_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (cpu_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (cpu_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (cpu_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (cpu_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (cpu_instruction_master_address), // avalon_anti_master_0.address
.av_waitrequest (cpu_instruction_master_waitrequest), // .waitrequest
.av_read (cpu_instruction_master_read), // .read
.av_readdata (cpu_instruction_master_readdata), // .readdata
.av_readdatavalid (cpu_instruction_master_readdatavalid), // .readdatavalid
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1) // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (28),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) cpu_data_master_translator (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (cpu_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (cpu_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (cpu_data_master_translator_avalon_universal_master_0_read), // .read
.uav_write (cpu_data_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (cpu_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (cpu_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (cpu_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (cpu_data_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (cpu_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (cpu_data_master_address), // avalon_anti_master_0.address
.av_waitrequest (cpu_data_master_waitrequest), // .waitrequest
.av_byteenable (cpu_data_master_byteenable), // .byteenable
.av_read (cpu_data_master_read), // .read
.av_readdata (cpu_data_master_readdata), // .readdata
.av_readdatavalid (cpu_data_master_readdatavalid), // .readdatavalid
.av_write (cpu_data_master_write), // .write
.av_writedata (cpu_data_master_writedata), // .writedata
.av_debugaccess (cpu_data_master_debugaccess), // .debugaccess
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1) // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (32),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) pixel_buffer_dma_avalon_pixel_dma_master_translator (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_read), // .read
.uav_write (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (pixel_buffer_dma_avalon_pixel_dma_master_address), // avalon_anti_master_0.address
.av_waitrequest (pixel_buffer_dma_avalon_pixel_dma_master_waitrequest), // .waitrequest
.av_read (pixel_buffer_dma_avalon_pixel_dma_master_read), // .read
.av_readdata (pixel_buffer_dma_avalon_pixel_dma_master_readdata), // .readdata
.av_readdatavalid (pixel_buffer_dma_avalon_pixel_dma_master_readdatavalid), // .readdatavalid
.av_lock (pixel_buffer_dma_avalon_pixel_dma_master_lock), // .lock
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) cpu_jtag_debug_module_translator (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (cpu_jtag_debug_module_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (cpu_jtag_debug_module_translator_avalon_anti_slave_0_write), // .write
.av_readdata (cpu_jtag_debug_module_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (cpu_jtag_debug_module_translator_avalon_anti_slave_0_writedata), // .writedata
.av_begintransfer (cpu_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer), // .begintransfer
.av_byteenable (cpu_jtag_debug_module_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_chipselect (cpu_jtag_debug_module_translator_avalon_anti_slave_0_chipselect), // .chipselect
.av_debugaccess (cpu_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess), // .debugaccess
.av_read (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (8),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_003_reset_out_reset), // reset.reset
.uav_address (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_anti_slave_0_write), // .write
.av_read (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_anti_slave_0_read), // .read
.av_readdata (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_anti_slave_0_writedata), // .writedata
.av_byteenable (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_waitrequest (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_chipselect (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_anti_slave_0_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sysid_control_slave_translator (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_003_reset_out_reset), // reset.reset
.uav_address (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (sysid_control_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_readdata (sysid_control_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (25),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sdram_0_s1_translator (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (~clock_signals_sys_clk_reset_reset), // reset.reset
.uav_address (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (sdram_0_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (sdram_0_s1_translator_avalon_anti_slave_0_write), // .write
.av_read (sdram_0_s1_translator_avalon_anti_slave_0_read), // .read
.av_readdata (sdram_0_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (sdram_0_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.av_byteenable (sdram_0_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_readdatavalid (sdram_0_s1_translator_avalon_anti_slave_0_readdatavalid), // .readdatavalid
.av_waitrequest (sdram_0_s1_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_chipselect (sdram_0_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) controller1_s1_translator (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_003_reset_out_reset), // reset.reset
.uav_address (controller1_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (controller1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (controller1_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (controller1_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (controller1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (controller1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (controller1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (controller1_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (controller1_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (controller1_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (controller1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (controller1_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_readdata (controller1_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) pixel_buffer_dma_avalon_control_slave_translator (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_write), // .write
.av_read (pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_read), // .read
.av_readdata (pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_writedata), // .writedata
.av_byteenable (pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (19),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) pixel_buffer_avalon_ssram_slave_translator (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (pixel_buffer_avalon_ssram_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (pixel_buffer_avalon_ssram_slave_translator_avalon_anti_slave_0_write), // .write
.av_read (pixel_buffer_avalon_ssram_slave_translator_avalon_anti_slave_0_read), // .read
.av_readdata (pixel_buffer_avalon_ssram_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (pixel_buffer_avalon_ssram_slave_translator_avalon_anti_slave_0_writedata), // .writedata
.av_byteenable (pixel_buffer_avalon_ssram_slave_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_readdatavalid (pixel_buffer_avalon_ssram_slave_translator_avalon_anti_slave_0_readdatavalid), // .readdatavalid
.av_waitrequest (pixel_buffer_avalon_ssram_slave_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) jtag_uart_avalon_jtag_slave_translator (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_003_reset_out_reset), // reset.reset
.uav_address (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_write), // .write
.av_read (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_read), // .read
.av_readdata (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata), // .writedata
.av_waitrequest (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_chipselect (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (98),
.PKT_PROTECTION_L (96),
.PKT_BEGIN_BURST (87),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.PKT_BURST_TYPE_H (84),
.PKT_BURST_TYPE_L (83),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_TRANS_LOCK (72),
.PKT_TRANS_EXCLUSIVE (73),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (91),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (92),
.PKT_THREAD_ID_H (95),
.PKT_THREAD_ID_L (95),
.PKT_CACHE_H (102),
.PKT_CACHE_L (99),
.PKT_DATA_SIDEBAND_H (86),
.PKT_DATA_SIDEBAND_L (86),
.PKT_QOS_H (88),
.PKT_QOS_L (88),
.PKT_ADDR_SIDEBAND_H (85),
.PKT_ADDR_SIDEBAND_L (85),
.ST_DATA_W (105),
.ST_CHANNEL_W (8),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (3),
.CACHE_VALUE (4'b0000)
) cpu_instruction_master_translator_avalon_universal_master_0_agent (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.av_address (cpu_instruction_master_translator_avalon_universal_master_0_address), // av.address
.av_write (cpu_instruction_master_translator_avalon_universal_master_0_write), // .write
.av_read (cpu_instruction_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (cpu_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (cpu_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (cpu_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (cpu_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (cpu_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (cpu_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (cpu_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
.cp_data (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.cp_startofpacket (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.cp_ready (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready
.rp_valid (limiter_rsp_src_valid), // rp.valid
.rp_data (limiter_rsp_src_data), // .data
.rp_channel (limiter_rsp_src_channel), // .channel
.rp_startofpacket (limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (limiter_rsp_src_ready) // .ready
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (98),
.PKT_PROTECTION_L (96),
.PKT_BEGIN_BURST (87),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.PKT_BURST_TYPE_H (84),
.PKT_BURST_TYPE_L (83),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_TRANS_LOCK (72),
.PKT_TRANS_EXCLUSIVE (73),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (91),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (92),
.PKT_THREAD_ID_H (95),
.PKT_THREAD_ID_L (95),
.PKT_CACHE_H (102),
.PKT_CACHE_L (99),
.PKT_DATA_SIDEBAND_H (86),
.PKT_DATA_SIDEBAND_L (86),
.PKT_QOS_H (88),
.PKT_QOS_L (88),
.PKT_ADDR_SIDEBAND_H (85),
.PKT_ADDR_SIDEBAND_L (85),
.ST_DATA_W (105),
.ST_CHANNEL_W (8),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (4'b0000)
) cpu_data_master_translator_avalon_universal_master_0_agent (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.av_address (cpu_data_master_translator_avalon_universal_master_0_address), // av.address
.av_write (cpu_data_master_translator_avalon_universal_master_0_write), // .write
.av_read (cpu_data_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (cpu_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (cpu_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (cpu_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (cpu_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (cpu_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (cpu_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (cpu_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (cpu_data_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (cpu_data_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
.cp_data (cpu_data_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.cp_startofpacket (cpu_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (cpu_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.cp_ready (cpu_data_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready
.rp_valid (limiter_001_rsp_src_valid), // rp.valid
.rp_data (limiter_001_rsp_src_data), // .data
.rp_channel (limiter_001_rsp_src_channel), // .channel
.rp_startofpacket (limiter_001_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (limiter_001_rsp_src_endofpacket), // .endofpacket
.rp_ready (limiter_001_rsp_src_ready) // .ready
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (98),
.PKT_PROTECTION_L (96),
.PKT_BEGIN_BURST (87),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.PKT_BURST_TYPE_H (84),
.PKT_BURST_TYPE_L (83),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_TRANS_LOCK (72),
.PKT_TRANS_EXCLUSIVE (73),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (91),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (92),
.PKT_THREAD_ID_H (95),
.PKT_THREAD_ID_L (95),
.PKT_CACHE_H (102),
.PKT_CACHE_L (99),
.PKT_DATA_SIDEBAND_H (86),
.PKT_DATA_SIDEBAND_L (86),
.PKT_QOS_H (88),
.PKT_QOS_L (88),
.PKT_ADDR_SIDEBAND_H (85),
.PKT_ADDR_SIDEBAND_L (85),
.ST_DATA_W (105),
.ST_CHANNEL_W (8),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (2),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (4'b0000)
) pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.av_address (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_address), // av.address
.av_write (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_write), // .write
.av_read (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
.cp_data (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.cp_startofpacket (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.cp_ready (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready
.rp_valid (rsp_xbar_demux_006_src1_valid), // rp.valid
.rp_data (rsp_xbar_demux_006_src1_data), // .data
.rp_channel (rsp_xbar_demux_006_src1_channel), // .channel
.rp_startofpacket (rsp_xbar_demux_006_src1_startofpacket), // .startofpacket
.rp_endofpacket (rsp_xbar_demux_006_src1_endofpacket), // .endofpacket
.rp_ready (rsp_xbar_demux_006_src1_ready) // .ready
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (87),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_TRANS_LOCK (72),
.PKT_SRC_ID_H (91),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (92),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_PROTECTION_H (98),
.PKT_PROTECTION_L (96),
.PKT_RESPONSE_STATUS_H (104),
.PKT_RESPONSE_STATUS_L (103),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.ST_CHANNEL_W (8),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_mux_src_ready), // cp.ready
.cp_valid (cmd_xbar_mux_src_valid), // .valid
.cp_data (cmd_xbar_mux_src_data), // .data
.cp_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_mux_src_channel), // .channel
.rf_sink_ready (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (87),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_TRANS_LOCK (72),
.PKT_SRC_ID_H (91),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (92),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_PROTECTION_H (98),
.PKT_PROTECTION_L (96),
.PKT_RESPONSE_STATUS_H (104),
.PKT_RESPONSE_STATUS_L (103),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.ST_CHANNEL_W (8),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_003_reset_out_reset), // clk_reset.reset
.m0_address (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_mux_001_src_ready), // cp.ready
.cp_valid (cmd_xbar_mux_001_src_valid), // .valid
.cp_data (cmd_xbar_mux_001_src_data), // .data
.cp_startofpacket (cmd_xbar_mux_001_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_mux_001_src_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_mux_001_src_channel), // .channel
.rf_sink_ready (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_003_reset_out_reset), // clk_reset.reset
.in_data (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (87),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_TRANS_LOCK (72),
.PKT_SRC_ID_H (91),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (92),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_PROTECTION_H (98),
.PKT_PROTECTION_L (96),
.PKT_RESPONSE_STATUS_H (104),
.PKT_RESPONSE_STATUS_L (103),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.ST_CHANNEL_W (8),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) sysid_control_slave_translator_avalon_universal_slave_0_agent (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_003_reset_out_reset), // clk_reset.reset
.m0_address (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_mux_002_src_ready), // cp.ready
.cp_valid (cmd_xbar_mux_002_src_valid), // .valid
.cp_data (cmd_xbar_mux_002_src_data), // .data
.cp_startofpacket (cmd_xbar_mux_002_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_mux_002_src_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_mux_002_src_channel), // .channel
.rf_sink_ready (sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sysid_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sysid_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sysid_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sysid_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sysid_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sysid_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_003_reset_out_reset), // clk_reset.reset
.in_data (sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (87),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_TRANS_LOCK (72),
.PKT_SRC_ID_H (91),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (92),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_PROTECTION_H (98),
.PKT_PROTECTION_L (96),
.PKT_RESPONSE_STATUS_H (104),
.PKT_RESPONSE_STATUS_L (103),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.ST_CHANNEL_W (8),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) sdram_0_s1_translator_avalon_universal_slave_0_agent (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (~clock_signals_sys_clk_reset_reset), // clk_reset.reset
.m0_address (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_mux_003_src_ready), // cp.ready
.cp_valid (cmd_xbar_mux_003_src_valid), // .valid
.cp_data (cmd_xbar_mux_003_src_data), // .data
.cp_startofpacket (cmd_xbar_mux_003_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_mux_003_src_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_mux_003_src_channel), // .channel
.rf_sink_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (8),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (~clock_signals_sys_clk_reset_reset), // clk_reset.reset
.in_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (87),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_TRANS_LOCK (72),
.PKT_SRC_ID_H (91),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (92),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_PROTECTION_H (98),
.PKT_PROTECTION_L (96),
.PKT_RESPONSE_STATUS_H (104),
.PKT_RESPONSE_STATUS_L (103),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.ST_CHANNEL_W (8),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) controller1_s1_translator_avalon_universal_slave_0_agent (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_003_reset_out_reset), // clk_reset.reset
.m0_address (controller1_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (controller1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (controller1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (controller1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (controller1_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (controller1_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (controller1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (controller1_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (controller1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (controller1_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (controller1_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (controller1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (controller1_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (controller1_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (controller1_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (controller1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_mux_004_src_ready), // cp.ready
.cp_valid (cmd_xbar_mux_004_src_valid), // .valid
.cp_data (cmd_xbar_mux_004_src_data), // .data
.cp_startofpacket (cmd_xbar_mux_004_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_mux_004_src_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_mux_004_src_channel), // .channel
.rf_sink_ready (controller1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (controller1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (controller1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (controller1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (controller1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (controller1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (controller1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (controller1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (controller1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (controller1_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (controller1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (controller1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (controller1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (controller1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (controller1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (controller1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) controller1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_003_reset_out_reset), // clk_reset.reset
.in_data (controller1_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (controller1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (controller1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (controller1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (controller1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (controller1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (controller1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (controller1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (controller1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (controller1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (87),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_TRANS_LOCK (72),
.PKT_SRC_ID_H (91),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (92),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_PROTECTION_H (98),
.PKT_PROTECTION_L (96),
.PKT_RESPONSE_STATUS_H (104),
.PKT_RESPONSE_STATUS_L (103),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.ST_CHANNEL_W (8),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_001_src5_ready), // cp.ready
.cp_valid (cmd_xbar_demux_001_src5_valid), // .valid
.cp_data (cmd_xbar_demux_001_src5_data), // .data
.cp_startofpacket (cmd_xbar_demux_001_src5_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_001_src5_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_001_src5_channel), // .channel
.rf_sink_ready (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (87),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_TRANS_LOCK (72),
.PKT_SRC_ID_H (91),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (92),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_PROTECTION_H (98),
.PKT_PROTECTION_L (96),
.PKT_RESPONSE_STATUS_H (104),
.PKT_RESPONSE_STATUS_L (103),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.ST_CHANNEL_W (8),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_mux_006_src_ready), // cp.ready
.cp_valid (cmd_xbar_mux_006_src_valid), // .valid
.cp_data (cmd_xbar_mux_006_src_data), // .data
.cp_startofpacket (cmd_xbar_mux_006_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_mux_006_src_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_mux_006_src_channel), // .channel
.rf_sink_ready (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (5),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (87),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_TRANS_LOCK (72),
.PKT_SRC_ID_H (91),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (92),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_PROTECTION_H (98),
.PKT_PROTECTION_L (96),
.PKT_RESPONSE_STATUS_H (104),
.PKT_RESPONSE_STATUS_L (103),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.ST_CHANNEL_W (8),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_003_reset_out_reset), // clk_reset.reset
.m0_address (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_001_src7_ready), // cp.ready
.cp_valid (cmd_xbar_demux_001_src7_valid), // .valid
.cp_data (cmd_xbar_demux_001_src7_data), // .data
.cp_startofpacket (cmd_xbar_demux_001_src7_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_001_src7_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_001_src7_channel), // .channel
.rf_sink_ready (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_003_reset_out_reset), // clk_reset.reset
.in_data (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
nios_system_addr_router addr_router (
.sink_ready (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
.sink_valid (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid
.sink_data (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.sink_startofpacket (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (addr_router_src_ready), // src.ready
.src_valid (addr_router_src_valid), // .valid
.src_data (addr_router_src_data), // .data
.src_channel (addr_router_src_channel), // .channel
.src_startofpacket (addr_router_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_src_endofpacket) // .endofpacket
);
nios_system_addr_router_001 addr_router_001 (
.sink_ready (cpu_data_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
.sink_valid (cpu_data_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid
.sink_data (cpu_data_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.sink_startofpacket (cpu_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (addr_router_001_src_ready), // src.ready
.src_valid (addr_router_001_src_valid), // .valid
.src_data (addr_router_001_src_data), // .data
.src_channel (addr_router_001_src_channel), // .channel
.src_startofpacket (addr_router_001_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_001_src_endofpacket) // .endofpacket
);
nios_system_addr_router_002 addr_router_002 (
.sink_ready (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
.sink_valid (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid
.sink_data (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.sink_startofpacket (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (addr_router_002_src_ready), // src.ready
.src_valid (addr_router_002_src_valid), // .valid
.src_data (addr_router_002_src_data), // .data
.src_channel (addr_router_002_src_channel), // .channel
.src_startofpacket (addr_router_002_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_002_src_endofpacket) // .endofpacket
);
nios_system_id_router id_router (
.sink_ready (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_src_ready), // src.ready
.src_valid (id_router_src_valid), // .valid
.src_data (id_router_src_data), // .data
.src_channel (id_router_src_channel), // .channel
.src_startofpacket (id_router_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_src_endofpacket) // .endofpacket
);
nios_system_id_router id_router_001 (
.sink_ready (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_003_reset_out_reset), // clk_reset.reset
.src_ready (id_router_001_src_ready), // src.ready
.src_valid (id_router_001_src_valid), // .valid
.src_data (id_router_001_src_data), // .data
.src_channel (id_router_001_src_channel), // .channel
.src_startofpacket (id_router_001_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_001_src_endofpacket) // .endofpacket
);
nios_system_id_router id_router_002 (
.sink_ready (sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_003_reset_out_reset), // clk_reset.reset
.src_ready (id_router_002_src_ready), // src.ready
.src_valid (id_router_002_src_valid), // .valid
.src_data (id_router_002_src_data), // .data
.src_channel (id_router_002_src_channel), // .channel
.src_startofpacket (id_router_002_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_002_src_endofpacket) // .endofpacket
);
nios_system_id_router id_router_003 (
.sink_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (~clock_signals_sys_clk_reset_reset), // clk_reset.reset
.src_ready (id_router_003_src_ready), // src.ready
.src_valid (id_router_003_src_valid), // .valid
.src_data (id_router_003_src_data), // .data
.src_channel (id_router_003_src_channel), // .channel
.src_startofpacket (id_router_003_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_003_src_endofpacket) // .endofpacket
);
nios_system_id_router id_router_004 (
.sink_ready (controller1_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (controller1_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (controller1_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (controller1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (controller1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_003_reset_out_reset), // clk_reset.reset
.src_ready (id_router_004_src_ready), // src.ready
.src_valid (id_router_004_src_valid), // .valid
.src_data (id_router_004_src_data), // .data
.src_channel (id_router_004_src_channel), // .channel
.src_startofpacket (id_router_004_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_004_src_endofpacket) // .endofpacket
);
nios_system_id_router_005 id_router_005 (
.sink_ready (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_005_src_ready), // src.ready
.src_valid (id_router_005_src_valid), // .valid
.src_data (id_router_005_src_data), // .data
.src_channel (id_router_005_src_channel), // .channel
.src_startofpacket (id_router_005_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_005_src_endofpacket) // .endofpacket
);
nios_system_id_router_006 id_router_006 (
.sink_ready (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (pixel_buffer_avalon_ssram_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_006_src_ready), // src.ready
.src_valid (id_router_006_src_valid), // .valid
.src_data (id_router_006_src_data), // .data
.src_channel (id_router_006_src_channel), // .channel
.src_startofpacket (id_router_006_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_006_src_endofpacket) // .endofpacket
);
nios_system_id_router_005 id_router_007 (
.sink_ready (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_003_reset_out_reset), // clk_reset.reset
.src_ready (id_router_007_src_ready), // src.ready
.src_valid (id_router_007_src_valid), // .valid
.src_data (id_router_007_src_data), // .data
.src_channel (id_router_007_src_channel), // .channel
.src_startofpacket (id_router_007_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_007_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (92),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.MAX_OUTSTANDING_RESPONSES (7),
.PIPELINED (0),
.ST_DATA_W (105),
.ST_CHANNEL_W (8),
.VALID_WIDTH (8),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32)
) limiter (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.cmd_sink_ready (addr_router_src_ready), // cmd_sink.ready
.cmd_sink_valid (addr_router_src_valid), // .valid
.cmd_sink_data (addr_router_src_data), // .data
.cmd_sink_channel (addr_router_src_channel), // .channel
.cmd_sink_startofpacket (addr_router_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (addr_router_src_endofpacket), // .endofpacket
.cmd_src_ready (limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (limiter_cmd_src_data), // .data
.cmd_src_channel (limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_xbar_mux_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_xbar_mux_src_valid), // .valid
.rsp_sink_channel (rsp_xbar_mux_src_channel), // .channel
.rsp_sink_data (rsp_xbar_mux_src_data), // .data
.rsp_sink_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket
.rsp_src_ready (limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (limiter_rsp_src_valid), // .valid
.rsp_src_data (limiter_rsp_src_data), // .data
.rsp_src_channel (limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (limiter_cmd_valid_data) // cmd_valid.data
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (92),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.MAX_OUTSTANDING_RESPONSES (7),
.PIPELINED (0),
.ST_DATA_W (105),
.ST_CHANNEL_W (8),
.VALID_WIDTH (8),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32)
) limiter_001 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.cmd_sink_ready (addr_router_001_src_ready), // cmd_sink.ready
.cmd_sink_valid (addr_router_001_src_valid), // .valid
.cmd_sink_data (addr_router_001_src_data), // .data
.cmd_sink_channel (addr_router_001_src_channel), // .channel
.cmd_sink_startofpacket (addr_router_001_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (addr_router_001_src_endofpacket), // .endofpacket
.cmd_src_ready (limiter_001_cmd_src_ready), // cmd_src.ready
.cmd_src_data (limiter_001_cmd_src_data), // .data
.cmd_src_channel (limiter_001_cmd_src_channel), // .channel
.cmd_src_startofpacket (limiter_001_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (limiter_001_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_xbar_mux_001_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_xbar_mux_001_src_valid), // .valid
.rsp_sink_channel (rsp_xbar_mux_001_src_channel), // .channel
.rsp_sink_data (rsp_xbar_mux_001_src_data), // .data
.rsp_sink_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket
.rsp_src_ready (limiter_001_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (limiter_001_rsp_src_valid), // .valid
.rsp_src_data (limiter_001_rsp_src_data), // .data
.rsp_src_channel (limiter_001_rsp_src_channel), // .channel
.rsp_src_startofpacket (limiter_001_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (limiter_001_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (limiter_001_cmd_valid_data) // cmd_valid.data
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2)
) rst_controller (
.reset_in0 (~reset_n), // reset_in0.reset
.reset_in1 (cpu_jtag_debug_module_reset_reset), // reset_in1.reset
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2)
) rst_controller_001 (
.reset_in0 (~reset_n), // reset_in0.reset
.reset_in1 (cpu_jtag_debug_module_reset_reset), // reset_in1.reset
.clk (clock_signals_vga_clk_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2)
) rst_controller_002 (
.reset_in0 (~reset_n), // reset_in0.reset
.reset_in1 (cpu_jtag_debug_module_reset_reset), // reset_in1.reset
.clk (clk_0), // clk.clk
.reset_out (rst_controller_002_reset_out_reset), // reset_out.reset
.reset_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2)
) rst_controller_003 (
.reset_in0 (~reset_n), // reset_in0.reset
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset_out (rst_controller_003_reset_out_reset), // reset_out.reset
.reset_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_in15 (1'b0) // (terminated)
);
nios_system_cmd_xbar_demux cmd_xbar_demux (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (limiter_cmd_src_ready), // sink.ready
.sink_channel (limiter_cmd_src_channel), // .channel
.sink_data (limiter_cmd_src_data), // .data
.sink_startofpacket (limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_xbar_demux_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_src0_valid), // .valid
.src0_data (cmd_xbar_demux_src0_data), // .data
.src0_channel (cmd_xbar_demux_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_xbar_demux_src1_ready), // src1.ready
.src1_valid (cmd_xbar_demux_src1_valid), // .valid
.src1_data (cmd_xbar_demux_src1_data), // .data
.src1_channel (cmd_xbar_demux_src1_channel), // .channel
.src1_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_xbar_demux_src1_endofpacket), // .endofpacket
.src2_ready (cmd_xbar_demux_src2_ready), // src2.ready
.src2_valid (cmd_xbar_demux_src2_valid), // .valid
.src2_data (cmd_xbar_demux_src2_data), // .data
.src2_channel (cmd_xbar_demux_src2_channel), // .channel
.src2_startofpacket (cmd_xbar_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_xbar_demux_src2_endofpacket), // .endofpacket
.src3_ready (cmd_xbar_demux_src3_ready), // src3.ready
.src3_valid (cmd_xbar_demux_src3_valid), // .valid
.src3_data (cmd_xbar_demux_src3_data), // .data
.src3_channel (cmd_xbar_demux_src3_channel), // .channel
.src3_startofpacket (cmd_xbar_demux_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_xbar_demux_src3_endofpacket), // .endofpacket
.src4_ready (cmd_xbar_demux_src4_ready), // src4.ready
.src4_valid (cmd_xbar_demux_src4_valid), // .valid
.src4_data (cmd_xbar_demux_src4_data), // .data
.src4_channel (cmd_xbar_demux_src4_channel), // .channel
.src4_startofpacket (cmd_xbar_demux_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_xbar_demux_src4_endofpacket) // .endofpacket
);
nios_system_cmd_xbar_demux_001 cmd_xbar_demux_001 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (limiter_001_cmd_src_ready), // sink.ready
.sink_channel (limiter_001_cmd_src_channel), // .channel
.sink_data (limiter_001_cmd_src_data), // .data
.sink_startofpacket (limiter_001_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (limiter_001_cmd_src_endofpacket), // .endofpacket
.sink_valid (limiter_001_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_xbar_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_001_src0_valid), // .valid
.src0_data (cmd_xbar_demux_001_src0_data), // .data
.src0_channel (cmd_xbar_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_xbar_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_xbar_demux_001_src1_valid), // .valid
.src1_data (cmd_xbar_demux_001_src1_data), // .data
.src1_channel (cmd_xbar_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_xbar_demux_001_src1_endofpacket), // .endofpacket
.src2_ready (cmd_xbar_demux_001_src2_ready), // src2.ready
.src2_valid (cmd_xbar_demux_001_src2_valid), // .valid
.src2_data (cmd_xbar_demux_001_src2_data), // .data
.src2_channel (cmd_xbar_demux_001_src2_channel), // .channel
.src2_startofpacket (cmd_xbar_demux_001_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_xbar_demux_001_src2_endofpacket), // .endofpacket
.src3_ready (cmd_xbar_demux_001_src3_ready), // src3.ready
.src3_valid (cmd_xbar_demux_001_src3_valid), // .valid
.src3_data (cmd_xbar_demux_001_src3_data), // .data
.src3_channel (cmd_xbar_demux_001_src3_channel), // .channel
.src3_startofpacket (cmd_xbar_demux_001_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_xbar_demux_001_src3_endofpacket), // .endofpacket
.src4_ready (cmd_xbar_demux_001_src4_ready), // src4.ready
.src4_valid (cmd_xbar_demux_001_src4_valid), // .valid
.src4_data (cmd_xbar_demux_001_src4_data), // .data
.src4_channel (cmd_xbar_demux_001_src4_channel), // .channel
.src4_startofpacket (cmd_xbar_demux_001_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_xbar_demux_001_src4_endofpacket), // .endofpacket
.src5_ready (cmd_xbar_demux_001_src5_ready), // src5.ready
.src5_valid (cmd_xbar_demux_001_src5_valid), // .valid
.src5_data (cmd_xbar_demux_001_src5_data), // .data
.src5_channel (cmd_xbar_demux_001_src5_channel), // .channel
.src5_startofpacket (cmd_xbar_demux_001_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_xbar_demux_001_src5_endofpacket), // .endofpacket
.src6_ready (cmd_xbar_demux_001_src6_ready), // src6.ready
.src6_valid (cmd_xbar_demux_001_src6_valid), // .valid
.src6_data (cmd_xbar_demux_001_src6_data), // .data
.src6_channel (cmd_xbar_demux_001_src6_channel), // .channel
.src6_startofpacket (cmd_xbar_demux_001_src6_startofpacket), // .startofpacket
.src6_endofpacket (cmd_xbar_demux_001_src6_endofpacket), // .endofpacket
.src7_ready (cmd_xbar_demux_001_src7_ready), // src7.ready
.src7_valid (cmd_xbar_demux_001_src7_valid), // .valid
.src7_data (cmd_xbar_demux_001_src7_data), // .data
.src7_channel (cmd_xbar_demux_001_src7_channel), // .channel
.src7_startofpacket (cmd_xbar_demux_001_src7_startofpacket), // .startofpacket
.src7_endofpacket (cmd_xbar_demux_001_src7_endofpacket) // .endofpacket
);
nios_system_cmd_xbar_demux_002 cmd_xbar_demux_002 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (addr_router_002_src_ready), // sink.ready
.sink_channel (addr_router_002_src_channel), // .channel
.sink_data (addr_router_002_src_data), // .data
.sink_startofpacket (addr_router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (addr_router_002_src_endofpacket), // .endofpacket
.sink_valid (addr_router_002_src_valid), // .valid
.src0_ready (cmd_xbar_demux_002_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_002_src0_valid), // .valid
.src0_data (cmd_xbar_demux_002_src0_data), // .data
.src0_channel (cmd_xbar_demux_002_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_002_src0_endofpacket) // .endofpacket
);
nios_system_cmd_xbar_mux cmd_xbar_mux (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_src_ready), // src.ready
.src_valid (cmd_xbar_mux_src_valid), // .valid
.src_data (cmd_xbar_mux_src_data), // .data
.src_channel (cmd_xbar_mux_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_src0_valid), // .valid
.sink0_channel (cmd_xbar_demux_src0_channel), // .channel
.sink0_data (cmd_xbar_demux_src0_data), // .data
.sink0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket
.sink1_ready (cmd_xbar_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_xbar_demux_001_src0_valid), // .valid
.sink1_channel (cmd_xbar_demux_001_src0_channel), // .channel
.sink1_data (cmd_xbar_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_xbar_demux_001_src0_endofpacket) // .endofpacket
);
nios_system_cmd_xbar_mux cmd_xbar_mux_001 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_003_reset_out_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_001_src_ready), // src.ready
.src_valid (cmd_xbar_mux_001_src_valid), // .valid
.src_data (cmd_xbar_mux_001_src_data), // .data
.src_channel (cmd_xbar_mux_001_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_src1_valid), // .valid
.sink0_channel (cmd_xbar_demux_src1_channel), // .channel
.sink0_data (cmd_xbar_demux_src1_data), // .data
.sink0_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_src1_endofpacket), // .endofpacket
.sink1_ready (cmd_xbar_demux_001_src1_ready), // sink1.ready
.sink1_valid (cmd_xbar_demux_001_src1_valid), // .valid
.sink1_channel (cmd_xbar_demux_001_src1_channel), // .channel
.sink1_data (cmd_xbar_demux_001_src1_data), // .data
.sink1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_xbar_demux_001_src1_endofpacket) // .endofpacket
);
nios_system_cmd_xbar_mux cmd_xbar_mux_002 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_003_reset_out_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_002_src_ready), // src.ready
.src_valid (cmd_xbar_mux_002_src_valid), // .valid
.src_data (cmd_xbar_mux_002_src_data), // .data
.src_channel (cmd_xbar_mux_002_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_src2_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_src2_valid), // .valid
.sink0_channel (cmd_xbar_demux_src2_channel), // .channel
.sink0_data (cmd_xbar_demux_src2_data), // .data
.sink0_startofpacket (cmd_xbar_demux_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_src2_endofpacket), // .endofpacket
.sink1_ready (cmd_xbar_demux_001_src2_ready), // sink1.ready
.sink1_valid (cmd_xbar_demux_001_src2_valid), // .valid
.sink1_channel (cmd_xbar_demux_001_src2_channel), // .channel
.sink1_data (cmd_xbar_demux_001_src2_data), // .data
.sink1_startofpacket (cmd_xbar_demux_001_src2_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_xbar_demux_001_src2_endofpacket) // .endofpacket
);
nios_system_cmd_xbar_mux cmd_xbar_mux_003 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (~clock_signals_sys_clk_reset_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_003_src_ready), // src.ready
.src_valid (cmd_xbar_mux_003_src_valid), // .valid
.src_data (cmd_xbar_mux_003_src_data), // .data
.src_channel (cmd_xbar_mux_003_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_src3_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_src3_valid), // .valid
.sink0_channel (cmd_xbar_demux_src3_channel), // .channel
.sink0_data (cmd_xbar_demux_src3_data), // .data
.sink0_startofpacket (cmd_xbar_demux_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_src3_endofpacket), // .endofpacket
.sink1_ready (cmd_xbar_demux_001_src3_ready), // sink1.ready
.sink1_valid (cmd_xbar_demux_001_src3_valid), // .valid
.sink1_channel (cmd_xbar_demux_001_src3_channel), // .channel
.sink1_data (cmd_xbar_demux_001_src3_data), // .data
.sink1_startofpacket (cmd_xbar_demux_001_src3_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_xbar_demux_001_src3_endofpacket) // .endofpacket
);
nios_system_cmd_xbar_mux cmd_xbar_mux_004 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_003_reset_out_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_004_src_ready), // src.ready
.src_valid (cmd_xbar_mux_004_src_valid), // .valid
.src_data (cmd_xbar_mux_004_src_data), // .data
.src_channel (cmd_xbar_mux_004_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_004_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_src4_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_src4_valid), // .valid
.sink0_channel (cmd_xbar_demux_src4_channel), // .channel
.sink0_data (cmd_xbar_demux_src4_data), // .data
.sink0_startofpacket (cmd_xbar_demux_src4_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_src4_endofpacket), // .endofpacket
.sink1_ready (cmd_xbar_demux_001_src4_ready), // sink1.ready
.sink1_valid (cmd_xbar_demux_001_src4_valid), // .valid
.sink1_channel (cmd_xbar_demux_001_src4_channel), // .channel
.sink1_data (cmd_xbar_demux_001_src4_data), // .data
.sink1_startofpacket (cmd_xbar_demux_001_src4_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_xbar_demux_001_src4_endofpacket) // .endofpacket
);
nios_system_cmd_xbar_mux cmd_xbar_mux_006 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_006_src_ready), // src.ready
.src_valid (cmd_xbar_mux_006_src_valid), // .valid
.src_data (cmd_xbar_mux_006_src_data), // .data
.src_channel (cmd_xbar_mux_006_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_006_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_006_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_001_src6_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_001_src6_valid), // .valid
.sink0_channel (cmd_xbar_demux_001_src6_channel), // .channel
.sink0_data (cmd_xbar_demux_001_src6_data), // .data
.sink0_startofpacket (cmd_xbar_demux_001_src6_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_001_src6_endofpacket), // .endofpacket
.sink1_ready (cmd_xbar_demux_002_src0_ready), // sink1.ready
.sink1_valid (cmd_xbar_demux_002_src0_valid), // .valid
.sink1_channel (cmd_xbar_demux_002_src0_channel), // .channel
.sink1_data (cmd_xbar_demux_002_src0_data), // .data
.sink1_startofpacket (cmd_xbar_demux_002_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_xbar_demux_002_src0_endofpacket) // .endofpacket
);
nios_system_rsp_xbar_demux rsp_xbar_demux (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_src_ready), // sink.ready
.sink_channel (id_router_src_channel), // .channel
.sink_data (id_router_src_data), // .data
.sink_startofpacket (id_router_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_src_endofpacket), // .endofpacket
.sink_valid (id_router_src_valid), // .valid
.src0_ready (rsp_xbar_demux_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_src0_valid), // .valid
.src0_data (rsp_xbar_demux_src0_data), // .data
.src0_channel (rsp_xbar_demux_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket
.src1_ready (rsp_xbar_demux_src1_ready), // src1.ready
.src1_valid (rsp_xbar_demux_src1_valid), // .valid
.src1_data (rsp_xbar_demux_src1_data), // .data
.src1_channel (rsp_xbar_demux_src1_channel), // .channel
.src1_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_xbar_demux_src1_endofpacket) // .endofpacket
);
nios_system_rsp_xbar_demux rsp_xbar_demux_001 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_003_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_001_src_ready), // sink.ready
.sink_channel (id_router_001_src_channel), // .channel
.sink_data (id_router_001_src_data), // .data
.sink_startofpacket (id_router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_001_src_endofpacket), // .endofpacket
.sink_valid (id_router_001_src_valid), // .valid
.src0_ready (rsp_xbar_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_001_src0_valid), // .valid
.src0_data (rsp_xbar_demux_001_src0_data), // .data
.src0_channel (rsp_xbar_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (rsp_xbar_demux_001_src1_ready), // src1.ready
.src1_valid (rsp_xbar_demux_001_src1_valid), // .valid
.src1_data (rsp_xbar_demux_001_src1_data), // .data
.src1_channel (rsp_xbar_demux_001_src1_channel), // .channel
.src1_startofpacket (rsp_xbar_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_xbar_demux_001_src1_endofpacket) // .endofpacket
);
nios_system_rsp_xbar_demux rsp_xbar_demux_002 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_003_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_002_src_ready), // sink.ready
.sink_channel (id_router_002_src_channel), // .channel
.sink_data (id_router_002_src_data), // .data
.sink_startofpacket (id_router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_002_src_endofpacket), // .endofpacket
.sink_valid (id_router_002_src_valid), // .valid
.src0_ready (rsp_xbar_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_002_src0_valid), // .valid
.src0_data (rsp_xbar_demux_002_src0_data), // .data
.src0_channel (rsp_xbar_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_002_src0_endofpacket), // .endofpacket
.src1_ready (rsp_xbar_demux_002_src1_ready), // src1.ready
.src1_valid (rsp_xbar_demux_002_src1_valid), // .valid
.src1_data (rsp_xbar_demux_002_src1_data), // .data
.src1_channel (rsp_xbar_demux_002_src1_channel), // .channel
.src1_startofpacket (rsp_xbar_demux_002_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_xbar_demux_002_src1_endofpacket) // .endofpacket
);
nios_system_rsp_xbar_demux rsp_xbar_demux_003 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (~clock_signals_sys_clk_reset_reset), // clk_reset.reset
.sink_ready (id_router_003_src_ready), // sink.ready
.sink_channel (id_router_003_src_channel), // .channel
.sink_data (id_router_003_src_data), // .data
.sink_startofpacket (id_router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_003_src_endofpacket), // .endofpacket
.sink_valid (id_router_003_src_valid), // .valid
.src0_ready (rsp_xbar_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_003_src0_valid), // .valid
.src0_data (rsp_xbar_demux_003_src0_data), // .data
.src0_channel (rsp_xbar_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_003_src0_endofpacket), // .endofpacket
.src1_ready (rsp_xbar_demux_003_src1_ready), // src1.ready
.src1_valid (rsp_xbar_demux_003_src1_valid), // .valid
.src1_data (rsp_xbar_demux_003_src1_data), // .data
.src1_channel (rsp_xbar_demux_003_src1_channel), // .channel
.src1_startofpacket (rsp_xbar_demux_003_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_xbar_demux_003_src1_endofpacket) // .endofpacket
);
nios_system_rsp_xbar_demux rsp_xbar_demux_004 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_003_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_004_src_ready), // sink.ready
.sink_channel (id_router_004_src_channel), // .channel
.sink_data (id_router_004_src_data), // .data
.sink_startofpacket (id_router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_004_src_endofpacket), // .endofpacket
.sink_valid (id_router_004_src_valid), // .valid
.src0_ready (rsp_xbar_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_004_src0_valid), // .valid
.src0_data (rsp_xbar_demux_004_src0_data), // .data
.src0_channel (rsp_xbar_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_004_src0_endofpacket), // .endofpacket
.src1_ready (rsp_xbar_demux_004_src1_ready), // src1.ready
.src1_valid (rsp_xbar_demux_004_src1_valid), // .valid
.src1_data (rsp_xbar_demux_004_src1_data), // .data
.src1_channel (rsp_xbar_demux_004_src1_channel), // .channel
.src1_startofpacket (rsp_xbar_demux_004_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_xbar_demux_004_src1_endofpacket) // .endofpacket
);
nios_system_cmd_xbar_demux_002 rsp_xbar_demux_005 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_005_src_ready), // sink.ready
.sink_channel (id_router_005_src_channel), // .channel
.sink_data (id_router_005_src_data), // .data
.sink_startofpacket (id_router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_005_src_endofpacket), // .endofpacket
.sink_valid (id_router_005_src_valid), // .valid
.src0_ready (rsp_xbar_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_005_src0_valid), // .valid
.src0_data (rsp_xbar_demux_005_src0_data), // .data
.src0_channel (rsp_xbar_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_005_src0_endofpacket) // .endofpacket
);
nios_system_rsp_xbar_demux rsp_xbar_demux_006 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_006_src_ready), // sink.ready
.sink_channel (id_router_006_src_channel), // .channel
.sink_data (id_router_006_src_data), // .data
.sink_startofpacket (id_router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_006_src_endofpacket), // .endofpacket
.sink_valid (id_router_006_src_valid), // .valid
.src0_ready (rsp_xbar_demux_006_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_006_src0_valid), // .valid
.src0_data (rsp_xbar_demux_006_src0_data), // .data
.src0_channel (rsp_xbar_demux_006_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_006_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_006_src0_endofpacket), // .endofpacket
.src1_ready (rsp_xbar_demux_006_src1_ready), // src1.ready
.src1_valid (rsp_xbar_demux_006_src1_valid), // .valid
.src1_data (rsp_xbar_demux_006_src1_data), // .data
.src1_channel (rsp_xbar_demux_006_src1_channel), // .channel
.src1_startofpacket (rsp_xbar_demux_006_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_xbar_demux_006_src1_endofpacket) // .endofpacket
);
nios_system_cmd_xbar_demux_002 rsp_xbar_demux_007 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_003_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_007_src_ready), // sink.ready
.sink_channel (id_router_007_src_channel), // .channel
.sink_data (id_router_007_src_data), // .data
.sink_startofpacket (id_router_007_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_007_src_endofpacket), // .endofpacket
.sink_valid (id_router_007_src_valid), // .valid
.src0_ready (rsp_xbar_demux_007_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_007_src0_valid), // .valid
.src0_data (rsp_xbar_demux_007_src0_data), // .data
.src0_channel (rsp_xbar_demux_007_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_007_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_007_src0_endofpacket) // .endofpacket
);
nios_system_rsp_xbar_mux rsp_xbar_mux (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (rsp_xbar_mux_src_ready), // src.ready
.src_valid (rsp_xbar_mux_src_valid), // .valid
.src_data (rsp_xbar_mux_src_data), // .data
.src_channel (rsp_xbar_mux_src_channel), // .channel
.src_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_xbar_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_xbar_demux_src0_valid), // .valid
.sink0_channel (rsp_xbar_demux_src0_channel), // .channel
.sink0_data (rsp_xbar_demux_src0_data), // .data
.sink0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_xbar_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_xbar_demux_001_src0_valid), // .valid
.sink1_channel (rsp_xbar_demux_001_src0_channel), // .channel
.sink1_data (rsp_xbar_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_xbar_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (rsp_xbar_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_xbar_demux_002_src0_valid), // .valid
.sink2_channel (rsp_xbar_demux_002_src0_channel), // .channel
.sink2_data (rsp_xbar_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_xbar_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_xbar_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_xbar_demux_003_src0_valid), // .valid
.sink3_channel (rsp_xbar_demux_003_src0_channel), // .channel
.sink3_data (rsp_xbar_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_xbar_demux_003_src0_endofpacket), // .endofpacket
.sink4_ready (rsp_xbar_demux_004_src0_ready), // sink4.ready
.sink4_valid (rsp_xbar_demux_004_src0_valid), // .valid
.sink4_channel (rsp_xbar_demux_004_src0_channel), // .channel
.sink4_data (rsp_xbar_demux_004_src0_data), // .data
.sink4_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_xbar_demux_004_src0_endofpacket) // .endofpacket
);
nios_system_rsp_xbar_mux_001 rsp_xbar_mux_001 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (rsp_xbar_mux_001_src_ready), // src.ready
.src_valid (rsp_xbar_mux_001_src_valid), // .valid
.src_data (rsp_xbar_mux_001_src_data), // .data
.src_channel (rsp_xbar_mux_001_src_channel), // .channel
.src_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_xbar_demux_src1_ready), // sink0.ready
.sink0_valid (rsp_xbar_demux_src1_valid), // .valid
.sink0_channel (rsp_xbar_demux_src1_channel), // .channel
.sink0_data (rsp_xbar_demux_src1_data), // .data
.sink0_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_xbar_demux_src1_endofpacket), // .endofpacket
.sink1_ready (rsp_xbar_demux_001_src1_ready), // sink1.ready
.sink1_valid (rsp_xbar_demux_001_src1_valid), // .valid
.sink1_channel (rsp_xbar_demux_001_src1_channel), // .channel
.sink1_data (rsp_xbar_demux_001_src1_data), // .data
.sink1_startofpacket (rsp_xbar_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_xbar_demux_001_src1_endofpacket), // .endofpacket
.sink2_ready (rsp_xbar_demux_002_src1_ready), // sink2.ready
.sink2_valid (rsp_xbar_demux_002_src1_valid), // .valid
.sink2_channel (rsp_xbar_demux_002_src1_channel), // .channel
.sink2_data (rsp_xbar_demux_002_src1_data), // .data
.sink2_startofpacket (rsp_xbar_demux_002_src1_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_xbar_demux_002_src1_endofpacket), // .endofpacket
.sink3_ready (rsp_xbar_demux_003_src1_ready), // sink3.ready
.sink3_valid (rsp_xbar_demux_003_src1_valid), // .valid
.sink3_channel (rsp_xbar_demux_003_src1_channel), // .channel
.sink3_data (rsp_xbar_demux_003_src1_data), // .data
.sink3_startofpacket (rsp_xbar_demux_003_src1_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_xbar_demux_003_src1_endofpacket), // .endofpacket
.sink4_ready (rsp_xbar_demux_004_src1_ready), // sink4.ready
.sink4_valid (rsp_xbar_demux_004_src1_valid), // .valid
.sink4_channel (rsp_xbar_demux_004_src1_channel), // .channel
.sink4_data (rsp_xbar_demux_004_src1_data), // .data
.sink4_startofpacket (rsp_xbar_demux_004_src1_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_xbar_demux_004_src1_endofpacket), // .endofpacket
.sink5_ready (rsp_xbar_demux_005_src0_ready), // sink5.ready
.sink5_valid (rsp_xbar_demux_005_src0_valid), // .valid
.sink5_channel (rsp_xbar_demux_005_src0_channel), // .channel
.sink5_data (rsp_xbar_demux_005_src0_data), // .data
.sink5_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket
.sink5_endofpacket (rsp_xbar_demux_005_src0_endofpacket), // .endofpacket
.sink6_ready (rsp_xbar_demux_006_src0_ready), // sink6.ready
.sink6_valid (rsp_xbar_demux_006_src0_valid), // .valid
.sink6_channel (rsp_xbar_demux_006_src0_channel), // .channel
.sink6_data (rsp_xbar_demux_006_src0_data), // .data
.sink6_startofpacket (rsp_xbar_demux_006_src0_startofpacket), // .startofpacket
.sink6_endofpacket (rsp_xbar_demux_006_src0_endofpacket), // .endofpacket
.sink7_ready (rsp_xbar_demux_007_src0_ready), // sink7.ready
.sink7_valid (rsp_xbar_demux_007_src0_valid), // .valid
.sink7_channel (rsp_xbar_demux_007_src0_channel), // .channel
.sink7_data (rsp_xbar_demux_007_src0_data), // .data
.sink7_startofpacket (rsp_xbar_demux_007_src0_startofpacket), // .startofpacket
.sink7_endofpacket (rsp_xbar_demux_007_src0_endofpacket) // .endofpacket
);
nios_system_irq_mapper irq_mapper (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.sender_irq (cpu_d_irq_irq) // sender.irq
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFSTP_FUNCTIONAL_V
`define SKY130_FD_SC_HS__SDFSTP_FUNCTIONAL_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`include "../u_df_p_s_pg/sky130_fd_sc_hs__u_df_p_s_pg.v"
`celldefine
module sky130_fd_sc_hs__sdfstp (
VPWR ,
VGND ,
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, D, SCD, SCE );
sky130_fd_sc_hs__u_df_p_s_pg `UNIT_DELAY u_df_p_s_pg0 (buf_Q , mux_out, CLK, SET, VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFSTP_FUNCTIONAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////////////
// Company: Digilent Inc.
// Engineer: Andrew Skreen
//
// Create Date: 07/11/2012
// Module Name: seven_seg_decoder
// Project Name: PmodGYRO_Demo
// Target Devices: Nexys3
// Tool versions: ISE 14.1
// Description: Produces cathode signals for displaying digits on the SSD.
//
// Revision History:
// Revision 0.01 - File Created (Andrew Skreen)
// Revision 1.00 - Added Comments and Converted to Verilog (Josh Sackos)
//////////////////////////////////////////////////////////////////////////////////////////
// ==============================================================================
// Define Module
// ==============================================================================
module seven_seg_decoder(
num_in,
control,
seg_out,
display_sel
);
// ==============================================================================
// Port Declarations
// ==============================================================================
input [3:0] num_in;
input [1:0] control;
output [6:0] seg_out;
input display_sel;
// ==============================================================================
// Parameters, Registers, and Wires
// ==============================================================================
wire [6:0] seg_out_bcd;
wire [6:0] seg_out_hex;
wire [6:0] seg_out_buf;
// ==============================================================================
// Implementation
// ==============================================================================
// If displaying hex, then make digit 4 on the SSD be an "H"
assign seg_out = (control == 2'b11 & display_sel == 1'b0) ? 7'b0001001 : seg_out_buf;
// Select either the HEX data or Dec. data to display on the SSD.
assign seg_out_buf = (display_sel == 1'b1) ? seg_out_bcd : seg_out_hex;
// Decimal decoder
assign seg_out_bcd = (num_in == 4'b0000) ? 7'b1000000 : //0
(num_in == 4'b0001) ? 7'b1111001 : //1
(num_in == 4'b0010) ? 7'b0100100 : //2
(num_in == 4'b0011) ? 7'b0110000 : //3
(num_in == 4'b0100) ? 7'b0011001 : //4
(num_in == 4'b0101) ? 7'b0010010 : //5
(num_in == 4'b0110) ? 7'b0000010 : //6
(num_in == 4'b0111) ? 7'b1111000 : //7
(num_in == 4'b1000) ? 7'b0000000 : //8
(num_in == 4'b1001) ? 7'b0010000 : //9
(num_in == 4'b1010) ? 7'b1111111 : //nothing when positive
(num_in == 4'b1011) ? 7'b1000110 : //C for temperature reading
7'b0111111; //minus sign
// Hex decoder
assign seg_out_hex = (num_in == 4'b0000) ? 7'b1000000 : //0
(num_in == 4'b0001) ? 7'b1111001 : //1
(num_in == 4'b0010) ? 7'b0100100 : //2
(num_in == 4'b0011) ? 7'b0110000 : //3
(num_in == 4'b0100) ? 7'b0011001 : //4
(num_in == 4'b0101) ? 7'b0010010 : //5
(num_in == 4'b0110) ? 7'b0000010 : //6
(num_in == 4'b0111) ? 7'b1111000 : //7
(num_in == 4'b1000) ? 7'b0000000 : //8
(num_in == 4'b1001) ? 7'b0010000 : //9
(num_in == 4'b1010) ? 7'b0001000 : //A
(num_in == 4'b1011) ? 7'b0000011 : //B
(num_in == 4'b1100) ? 7'b1000110 : //C
(num_in == 4'b1101) ? 7'b0100001 : //D
(num_in == 4'b1110) ? 7'b0000110 : //E
7'b0001110; //F
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFSBP_2_V
`define SKY130_FD_SC_LP__DFSBP_2_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog wrapper for dfsbp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dfsbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfsbp_2 (
Q ,
Q_N ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfsbp_2 (
Q ,
Q_N ,
CLK ,
D ,
SET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFSBP_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFXTP_PP_BLACKBOX_V
`define SKY130_FD_SC_HVL__DFXTP_PP_BLACKBOX_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__dfxtp (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFXTP_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYGATE4S50_SYMBOL_V
`define SKY130_FD_SC_LP__DLYGATE4S50_SYMBOL_V
/**
* dlygate4s50: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlygate4s50 (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYGATE4S50_SYMBOL_V
|
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