text
stringlengths 938
1.05M
|
|---|
module test_bench(clk, rst);
input clk;
input rst;
wire [63:0] wire_39069600;
wire wire_39069600_stb;
wire wire_39069600_ack;
wire [63:0] wire_39795024;
wire wire_39795024_stb;
wire wire_39795024_ack;
wire [63:0] wire_39795168;
wire wire_39795168_stb;
wire wire_39795168_ack;
file_reader_a file_reader_a_39796104(
.clk(clk),
.rst(rst),
.output_z(wire_39069600),
.output_z_stb(wire_39069600_stb),
.output_z_ack(wire_39069600_ack));
file_reader_b file_reader_b_39759816(
.clk(clk),
.rst(rst),
.output_z(wire_39795024),
.output_z_stb(wire_39795024_stb),
.output_z_ack(wire_39795024_ack));
file_writer file_writer_39028208(
.clk(clk),
.rst(rst),
.input_a(wire_39795168),
.input_a_stb(wire_39795168_stb),
.input_a_ack(wire_39795168_ack));
double_divider divider_39759952(
.clk(clk),
.rst(rst),
.input_a(wire_39069600),
.input_a_stb(wire_39069600_stb),
.input_a_ack(wire_39069600_ack),
.input_b(wire_39795024),
.input_b_stb(wire_39795024_stb),
.input_b_ack(wire_39795024_ack),
.output_z(wire_39795168),
.output_z_stb(wire_39795168_stb),
.output_z_ack(wire_39795168_ack));
endmodule
|
module mojo_top(
// 50MHz clock input
input clk,
// Input from reset button (active low)
input rst_n,
// cclk input from AVR, high when AVR is ready
input cclk,
// Outputs to the 8 onboard LEDs
output[7:0]led,
// AVR SPI connections
output spi_miso,
input spi_ss,
input spi_mosi,
input spi_sck,
// AVR ADC channel select
output [3:0] spi_channel,
// Serial connections
input avr_tx, // AVR Tx => FPGA Rx
output avr_rx, // AVR Rx => FPGA Tx
input avr_rx_busy, // AVR Rx buffer full
output R0,
output G0,
output B0,
output R1,
output G1,
output B1,
output A,
output B,
output C,
output D,
output MATCLK,
output MATLAT,
output MATOE
);
wire rst = ~rst_n; // make reset active high
// these signals should be high-z when not used
assign spi_miso = 1'bz;
assign avr_rx = 1'bz;
assign spi_channel = 4'bzzzz;
assign led[6:0] = 7'b0;
wire [7:0] tx_data;
wire new_tx_data;
wire tx_busy;
wire [7:0] rx_data;
wire new_rx_data;
reg [23:0] counter10;
always @ (posedge clk or posedge rst)
begin
if (rst)
begin
counter10 <= 0;
end
else
begin
counter10 <= counter10 + 1;
end
end
assign led[7] = counter10[23];
avr_interface avr_interface (
.clk(clk),
.rst(rst),
.cclk(cclk),
.spi_miso(spi_miso),
.spi_mosi(spi_mosi),
.spi_sck(spi_sck),
.spi_ss(spi_ss),
.spi_channel(spi_channel),
.tx(avr_rx), // FPGA tx goes to AVR rx
.rx(avr_tx),
.channel(4'd15), // invalid channel disables the ADC
.new_sample(),
.sample(),
.sample_channel(),
.tx_data(tx_data),
.new_tx_data(new_tx_data),
.tx_busy(tx_busy),
.tx_block(avr_rx_busy),
.rx_data(rx_data),
.new_rx_data(new_rx_data)
);
message_printer helloWorldPrinter (
.clk(clk),
.rst(rst),
.tx_data(tx_data),
.new_tx_data(new_tx_data),
.tx_busy(tx_busy),
.rx_data(rx_data),
.new_rx_data(new_rx_data)
);
rgbmatrix rgbmatrix (
.clk(clk),
.rst(rst),
.R0(R0),
.G0(G0),
.B0(B0),
.R1(R1),
.G1(G1),
.B1(B1),
.A(A),
.B(B),
.C(C),
.D(D),
.MATCLK(MATCLK),
.MATLAT(MATLAT),
.MATOE(MATOE)
);
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DECAP_FUNCTIONAL_V
`define SKY130_FD_SC_MS__DECAP_FUNCTIONAL_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__decap ();
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DECAP_FUNCTIONAL_V |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcieCore_qpll_reset.v
// Version : 1.11
//------------------------------------------------------------------------------
// Filename : qpll_reset.v
// Description : QPLL Reset Module for 7 Series Transceiver
// Version : 11.4
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- QPLL Reset Module --------------------------------------------------
module pcieCore_qpll_reset #
(
//---------- Global ------------------------------------
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only
parameter PCIE_POWER_SAVING = "TRUE", // PCIe power saving
parameter PCIE_LANE = 1, // PCIe number of lanes
parameter BYPASS_COARSE_OVRD = 1 // Bypass coarse frequency override
)
(
//---------- Input -------------------------------------
input QRST_CLK,
input QRST_RST_N,
input QRST_MMCM_LOCK,
input [PCIE_LANE-1:0] QRST_CPLLLOCK,
input [(PCIE_LANE-1)>>2:0]QRST_DRP_DONE,
input [(PCIE_LANE-1)>>2:0]QRST_QPLLLOCK,
input [ 1:0] QRST_RATE,
input [PCIE_LANE-1:0] QRST_QPLLRESET_IN,
input [PCIE_LANE-1:0] QRST_QPLLPD_IN,
//---------- Output ------------------------------------
output QRST_OVRD,
output QRST_DRP_START,
output QRST_QPLLRESET_OUT,
output QRST_QPLLPD_OUT,
output QRST_IDLE,
output [ 3:0] QRST_FSM
);
//---------- Input Register ----------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] cplllock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [(PCIE_LANE-1)>>2:0]drp_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [(PCIE_LANE-1)>>2:0]qplllock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] qpllreset_in_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] qpllpd_in_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] cplllock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [(PCIE_LANE-1)>>2:0]drp_done_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [(PCIE_LANE-1)>>2:0]qplllock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] qpllreset_in_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] qpllpd_in_reg2;
//---------- Output Register --------------------------
reg ovrd = 1'd0;
reg qpllreset = 1'd1;
reg qpllpd = 1'd0;
reg [ 3:0] fsm = 2;
//---------- FSM ---------------------------------------
localparam FSM_IDLE = 1;
localparam FSM_WAIT_LOCK = 2;
localparam FSM_MMCM_LOCK = 3;
localparam FSM_DRP_START_NOM = 4;
localparam FSM_DRP_DONE_NOM = 5;
localparam FSM_QPLLLOCK = 6;
localparam FSM_DRP_START_OPT = 7;
localparam FSM_DRP_DONE_OPT = 8;
localparam FSM_QPLL_RESET = 9;
localparam FSM_QPLLLOCK2 = 10;
localparam FSM_QPLL_PDRESET = 11;
localparam FSM_QPLL_PD = 12;
//---------- Input FF ----------------------------------------------------------
always @ (posedge QRST_CLK)
begin
if (!QRST_RST_N)
begin
//---------- 1st Stage FF --------------------------
mmcm_lock_reg1 <= 1'd0;
cplllock_reg1 <= {PCIE_LANE{1'd1}};
drp_done_reg1 <= {(((PCIE_LANE-1)>>2)+1){1'd0}};
qplllock_reg1 <= {(((PCIE_LANE-1)>>2)+1){1'd0}};
rate_reg1 <= 2'd0;
qpllreset_in_reg1 <= {PCIE_LANE{1'd1}};
qpllpd_in_reg1 <= {PCIE_LANE{1'd0}};
//---------- 2nd Stage FF --------------------------
mmcm_lock_reg2 <= 1'd0;
cplllock_reg2 <= {PCIE_LANE{1'd1}};
drp_done_reg2 <= {(((PCIE_LANE-1)>>2)+1){1'd0}};
qplllock_reg2 <= {(((PCIE_LANE-1)>>2)+1){1'd0}};
rate_reg2 <= 2'd0;
qpllreset_in_reg2 <= {PCIE_LANE{1'd1}};
qpllpd_in_reg2 <= {PCIE_LANE{1'd0}};
end
else
begin
//---------- 1st Stage FF --------------------------
mmcm_lock_reg1 <= QRST_MMCM_LOCK;
cplllock_reg1 <= QRST_CPLLLOCK;
drp_done_reg1 <= QRST_DRP_DONE;
qplllock_reg1 <= QRST_QPLLLOCK;
rate_reg1 <= QRST_RATE;
qpllreset_in_reg1 <= QRST_QPLLRESET_IN;
qpllpd_in_reg1 <= QRST_QPLLPD_IN;
//---------- 2nd Stage FF --------------------------
mmcm_lock_reg2 <= mmcm_lock_reg1;
cplllock_reg2 <= cplllock_reg1;
drp_done_reg2 <= drp_done_reg1;
qplllock_reg2 <= qplllock_reg1;
rate_reg2 <= rate_reg1;
qpllreset_in_reg2 <= qpllreset_in_reg1;
qpllpd_in_reg2 <= qpllpd_in_reg1;
end
end
//---------- QPLL Reset FSM ----------------------------------------------------
always @ (posedge QRST_CLK)
begin
if (!QRST_RST_N)
begin
fsm <= FSM_WAIT_LOCK;
ovrd <= 1'd0;
qpllreset <= 1'd1;
qpllpd <= 1'd0;
end
else
begin
case (fsm)
//---------- Idle State ----------------------------
FSM_IDLE :
begin
if (!QRST_RST_N)
begin
fsm <= FSM_WAIT_LOCK;
ovrd <= 1'd0;
qpllreset <= 1'd1;
qpllpd <= 1'd0;
end
else
begin
fsm <= FSM_IDLE;
ovrd <= ovrd;
qpllreset <= &qpllreset_in_reg2;
qpllpd <= &qpllpd_in_reg2;
end
end
//---------- Wait for CPLL and QPLL to Lose Lock ---
FSM_WAIT_LOCK :
begin
fsm <= ((&(~cplllock_reg2)) && (&(~qplllock_reg2)) ? FSM_MMCM_LOCK : FSM_WAIT_LOCK);
ovrd <= ovrd;
qpllreset <= qpllreset;
qpllpd <= qpllpd;
end
//---------- Wait for MMCM and CPLL Lock -----------
FSM_MMCM_LOCK :
begin
fsm <= ((mmcm_lock_reg2 && (&cplllock_reg2)) ? FSM_DRP_START_NOM : FSM_MMCM_LOCK);
ovrd <= ovrd;
qpllreset <= qpllreset;
qpllpd <= qpllpd;
end
//---------- Start QPLL DRP for Normal QPLL Lock Mode
FSM_DRP_START_NOM:
begin
fsm <= (&(~drp_done_reg2) ? FSM_DRP_DONE_NOM : FSM_DRP_START_NOM);
ovrd <= ovrd;
qpllreset <= qpllreset;
qpllpd <= qpllpd;
end
//---------- Wait for QPLL DRP Done ----------------
FSM_DRP_DONE_NOM :
begin
fsm <= (&drp_done_reg2 ? FSM_QPLLLOCK : FSM_DRP_DONE_NOM);
ovrd <= ovrd;
qpllreset <= qpllreset;
qpllpd <= qpllpd;
end
//---------- Wait for QPLL Lock --------------------
FSM_QPLLLOCK :
begin
fsm <= (&qplllock_reg2 ? ((BYPASS_COARSE_OVRD == 1) ? FSM_QPLL_PDRESET : FSM_DRP_START_OPT) : FSM_QPLLLOCK);
ovrd <= ovrd;
qpllreset <= 1'd0;
qpllpd <= qpllpd;
end
//---------- Start QPLL DRP for Optimized QPLL Lock Mode
FSM_DRP_START_OPT:
begin
fsm <= (&(~drp_done_reg2) ? FSM_DRP_DONE_OPT : FSM_DRP_START_OPT);
ovrd <= 1'd1;
qpllreset <= qpllreset;
qpllpd <= qpllpd;
end
//---------- Wait for QPLL DRP Done ----------------
FSM_DRP_DONE_OPT :
begin
if (&drp_done_reg2)
begin
fsm <= ((PCIE_PLL_SEL == "QPLL") ? FSM_QPLL_RESET : FSM_QPLL_PDRESET);
ovrd <= ovrd;
qpllreset <= (PCIE_PLL_SEL == "QPLL");
qpllpd <= qpllpd;
end
else
begin
fsm <= FSM_DRP_DONE_OPT;
ovrd <= ovrd;
qpllreset <= qpllreset;
qpllpd <= qpllpd;
end
end
//---------- Reset QPLL ----------------------------
FSM_QPLL_RESET :
begin
fsm <= (&(~qplllock_reg2) ? FSM_QPLLLOCK2 : FSM_QPLL_RESET);
ovrd <= ovrd;
qpllreset <= 1'd1;
qpllpd <= 1'd0;
end
//---------- Wait for QPLL Lock --------------------
FSM_QPLLLOCK2 :
begin
fsm <= (&qplllock_reg2 ? FSM_IDLE : FSM_QPLLLOCK2);
ovrd <= ovrd;
qpllreset <= 1'd0;
qpllpd <= 1'd0;
end
//---------- Hold QPLL in Reset --------------------
FSM_QPLL_PDRESET :
begin
fsm <= FSM_QPLL_PD;
ovrd <= ovrd;
qpllreset <= (PCIE_PLL_SEL == "CPLL") ? (rate_reg2 != 2'd2) : 1'd0;
qpllpd <= qpllpd;
end
//---------- Power-down QPLL -----------------------
FSM_QPLL_PD :
begin
fsm <= FSM_IDLE;
ovrd <= ovrd;
qpllreset <= qpllreset;
qpllpd <= (PCIE_PLL_SEL == "CPLL") ? (rate_reg2 != 2'd2) : 1'd0;
end
//---------- Default State -------------------------
default :
begin
fsm <= FSM_WAIT_LOCK;
ovrd <= 1'd0;
qpllreset <= 1'd0;
qpllpd <= 1'd0;
end
endcase
end
end
//---------- QPLL Lock Output --------------------------------------------------
assign QRST_OVRD = ovrd;
assign QRST_DRP_START = (fsm == FSM_DRP_START_NOM) || (fsm == FSM_DRP_START_OPT);
assign QRST_QPLLRESET_OUT = qpllreset;
assign QRST_QPLLPD_OUT = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : qpllpd);
assign QRST_IDLE = (fsm == FSM_IDLE);
assign QRST_FSM = fsm;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A22O_PP_SYMBOL_V
`define SKY130_FD_SC_LS__A22O_PP_SYMBOL_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a22o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A22O_PP_SYMBOL_V
|
////////////////////////////////////////////////////////////////////////
//
// NetFPGA-10G http://www.netfpga.org
//
// Module:
// nf10_axis_converter
//
// Description:
// Convert AXI4-Streams to different data width
// Add LEN subchannel
//
// Revision history:
// 2011/2/6 hyzeng: Initial check-in
// 2011/4/13 hyzeng: Updated with new NetFPGA-10G AXI spec
//
////////////////////////////////////////////////////////////////////////
module nf10_axis_converter
#(
// Master AXI Stream Data Width
parameter C_M_AXIS_DATA_WIDTH=64,
parameter C_S_AXIS_DATA_WIDTH=256,
parameter C_USER_WIDTH=128,
parameter C_LEN_WIDTH=16,
parameter C_SPT_WIDTH=8,
parameter C_DPT_WIDTH=8,
parameter C_DEFAULT_VALUE_ENABLE=0,
parameter C_DEFAULT_SRC_PORT=0,
parameter C_DEFAULT_DST_PORT=0
)
(
// Part 1: System side signals
// Global Ports
input axi_aclk,
input axi_resetn,
// Master Stream Ports
output reg [C_M_AXIS_DATA_WIDTH - 1:0] m_axis_tdata,
output reg [((C_M_AXIS_DATA_WIDTH / 8)) - 1:0] m_axis_tstrb,
output [C_USER_WIDTH-1:0] m_axis_tuser,
output reg m_axis_tvalid,
input m_axis_tready,
output reg m_axis_tlast,
// Slave Stream Ports
input [C_S_AXIS_DATA_WIDTH - 1:0] s_axis_tdata,
input [((C_S_AXIS_DATA_WIDTH / 8)) - 1:0] s_axis_tstrb,
input [C_USER_WIDTH-1:0] s_axis_tuser,
input s_axis_tvalid,
output s_axis_tready,
input s_axis_tlast
);
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
localparam MAX_PKT_SIZE = 1600; // In bytes
localparam LENGTH_COUNTER_WIDTH = log2(C_S_AXIS_DATA_WIDTH / 8);
localparam IN_FIFO_DEPTH_BIT = log2(MAX_PKT_SIZE/(C_S_AXIS_DATA_WIDTH / 8));
localparam M_S_RATIO_COUNT = C_M_AXIS_DATA_WIDTH / C_S_AXIS_DATA_WIDTH;
localparam S_M_RATIO_COUNT = C_S_AXIS_DATA_WIDTH / C_M_AXIS_DATA_WIDTH;
wire in_fifo_nearly_full;
reg in_fifo_rd_en;
wire in_fifo_empty;
wire [C_S_AXIS_DATA_WIDTH - 1:0] s_axis_tdata_fifo;
wire [((C_S_AXIS_DATA_WIDTH / 8)) - 1:0] s_axis_tstrb_fifo;
wire s_axis_tlast_fifo;
reg info_fifo_wr_en;
reg info_fifo_rd_en;
wire info_fifo_empty;
wire info_fifo_nearly_full;
reg [C_LEN_WIDTH - 1:0] length_in;
reg [C_LEN_WIDTH - 1:0] length_prev, length_prev_next;
reg [LENGTH_COUNTER_WIDTH:0] local_sum;
reg [C_M_AXIS_DATA_WIDTH - 1:0] m_axis_tdata_prev, m_axis_tdata_prev_next;
reg [((C_M_AXIS_DATA_WIDTH / 8)) - 1:0] m_axis_tstrb_prev, m_axis_tstrb_prev_next;
reg [7:0] counter, counter_next;
reg first_time, first_time_next;
integer i, j, k;
wire [C_LEN_WIDTH - 1:0] tuser_len;
wire [C_SPT_WIDTH - 1:0] tuser_spt = C_DEFAULT_SRC_PORT;
wire [C_DPT_WIDTH - 1:0] tuser_dpt = C_DEFAULT_DST_PORT;
reg metadata_state, metadata_state_next;
localparam METADATA_STATE_WAIT_START = 0;
localparam METADATA_STATE_WAIT_END = 1;
fallthrough_small_fifo #
(.WIDTH(C_S_AXIS_DATA_WIDTH+C_S_AXIS_DATA_WIDTH / 8+1),
.MAX_DEPTH_BITS(IN_FIFO_DEPTH_BIT)
)
input_fifo
(.din ({s_axis_tlast, s_axis_tstrb, s_axis_tdata}), // Data in
.wr_en (s_axis_tvalid & ~in_fifo_nearly_full), // Write enable
.rd_en (in_fifo_rd_en), // Read the next word
.dout ({s_axis_tlast_fifo, s_axis_tstrb_fifo, s_axis_tdata_fifo}),
.full (),
.nearly_full (in_fifo_nearly_full),
.prog_full (),
.empty (in_fifo_empty),
.reset (~axi_resetn),
.clk (axi_aclk)
);
////////////////////////////////////////////////////////////////
// The following code generates metadata for each packet
// 1. Count incoming bytes and present to tuser_len
// 2. Fill tuser_dpt and tuser_spt with default value
////////////////////////////////////////////////////////////////
generate
if(C_DEFAULT_VALUE_ENABLE) begin: DEFAULT_VALUE_ENABLE
fallthrough_small_fifo #
(.WIDTH(C_LEN_WIDTH),
.MAX_DEPTH_BITS(5))
info_fifo
(.din (length_in), // Data in
.wr_en (info_fifo_wr_en), // Write enable
.rd_en (info_fifo_rd_en), // Read the next word
.dout (tuser_len),
.full (),
.nearly_full (info_fifo_nearly_full),
.prog_full (),
.empty (info_fifo_empty),
.reset (~axi_resetn),
.clk (axi_aclk)
);
assign s_axis_tready = ~in_fifo_nearly_full & ~info_fifo_nearly_full;
always @(*) begin
local_sum = 0;
for ( i=0; i< C_S_AXIS_DATA_WIDTH / 8; i=i+1 ) begin
if ( s_axis_tstrb[i] ) begin
local_sum = i+1;
end
end
end
always @(*) begin
info_fifo_wr_en = 1'b0;
length_prev_next = length_prev;
length_in = length_prev + local_sum;
if(s_axis_tvalid & s_axis_tready) begin
length_prev_next = length_prev + local_sum;
if(s_axis_tlast) begin
info_fifo_wr_en = 1'b1;
length_prev_next = 0;
end
end
end
assign m_axis_tuser = {96'b0, tuser_dpt, tuser_spt, tuser_len}; // According to NetFPGA-10G metadata format.
end
////////////////////////////////////////////////////////////////
// The following code passes the slave port TUSER along
////////////////////////////////////////////////////////////////
else begin: DEFAULT_VALUE_DISABLE
always @(*) begin
info_fifo_wr_en = 1'b0;
metadata_state_next = metadata_state;
case(metadata_state)
METADATA_STATE_WAIT_START: begin
if(s_axis_tvalid & s_axis_tready) begin
info_fifo_wr_en = 1'b1;
metadata_state_next = METADATA_STATE_WAIT_END;
end
end
METADATA_STATE_WAIT_END: begin
if(s_axis_tvalid & s_axis_tready & s_axis_tlast) begin
metadata_state_next = METADATA_STATE_WAIT_START;
end
end
endcase
end
always @(posedge axi_aclk) begin
if (~axi_resetn) begin
metadata_state <= METADATA_STATE_WAIT_START;
end
else begin
metadata_state <= metadata_state_next;
end
end
assign s_axis_tready = ~in_fifo_nearly_full & ~info_fifo_nearly_full;
fallthrough_small_fifo #
(.WIDTH(C_USER_WIDTH),
.MAX_DEPTH_BITS(5))
info_fifo
(.din (s_axis_tuser), // Data in
.wr_en (info_fifo_wr_en), // Write enable
.rd_en (info_fifo_rd_en), // Read the next word
.dout (m_axis_tuser),
.full (),
.nearly_full (info_fifo_nearly_full),
.prog_full (),
.empty (info_fifo_empty),
.reset (~axi_resetn),
.clk (axi_aclk)
);
end
endgenerate
////////////////////////////////////////////////////////////////
// Convert data width
// There are 2 cases
// 1. MASTER_WIDER
// 2. SLAVE_WIDER
////////////////////////////////////////////////////////////////
generate
if(C_M_AXIS_DATA_WIDTH >= C_S_AXIS_DATA_WIDTH) begin: MASTER_WIDER
always @(*) begin
in_fifo_rd_en = 1'b0;
info_fifo_rd_en = 1'b0;
m_axis_tdata = m_axis_tdata_prev;
m_axis_tstrb = m_axis_tstrb_prev;
m_axis_tlast = 1'b0;
m_axis_tdata_prev_next = m_axis_tdata_prev;
m_axis_tstrb_prev_next = m_axis_tstrb_prev;
counter_next = counter;
first_time_next = first_time;
m_axis_tvalid = 1'b0;
for(j=0;j<C_S_AXIS_DATA_WIDTH;j=j+1) m_axis_tdata[C_S_AXIS_DATA_WIDTH*counter+j] = s_axis_tdata_fifo[j];
for(k=0;k<C_S_AXIS_DATA_WIDTH/8;k=k+1) m_axis_tstrb[C_S_AXIS_DATA_WIDTH/8*counter+k] = s_axis_tstrb_fifo[k];
if(~in_fifo_empty) begin
if(counter == M_S_RATIO_COUNT - 1) begin
if(first_time) begin
if(~info_fifo_empty) begin
m_axis_tvalid = 1'b1;
if(m_axis_tready) begin
in_fifo_rd_en = 1'b1;
info_fifo_rd_en = 1'b1;
counter_next = 0;
first_time_next = 1'b0;
m_axis_tdata_prev_next = {C_M_AXIS_DATA_WIDTH{1'b0}};
m_axis_tstrb_prev_next = {C_M_AXIS_DATA_WIDTH/8{1'b0}};
end
end
end
else begin
m_axis_tvalid = 1'b1;
if(m_axis_tready) begin
counter_next = 0;
m_axis_tdata_prev_next = {C_M_AXIS_DATA_WIDTH{1'b0}};
m_axis_tstrb_prev_next = {C_M_AXIS_DATA_WIDTH/8{1'b0}};
in_fifo_rd_en = 1'b1;
if(s_axis_tlast_fifo) begin
first_time_next = 1'b1;
m_axis_tlast = 1'b1;
end
end
end
end
else begin
if(s_axis_tlast_fifo) begin
m_axis_tvalid = 1'b1;
m_axis_tlast = 1'b1;
if(m_axis_tready) begin
in_fifo_rd_en = 1'b1;
counter_next = 0;
m_axis_tdata_prev_next = {C_M_AXIS_DATA_WIDTH{1'b0}};
m_axis_tstrb_prev_next = {C_M_AXIS_DATA_WIDTH/8{1'b0}};
first_time_next = 1'b1;
end
end
else begin
if(m_axis_tready) begin
in_fifo_rd_en = 1'b1;
counter_next = counter + 1'b1;
m_axis_tdata_prev_next = m_axis_tdata;
m_axis_tstrb_prev_next = m_axis_tstrb;
end
end
end
end
end
always @(posedge axi_aclk) begin
if (~axi_resetn) begin
counter <= 0;
first_time <= 1'b1;
length_prev <= 1'b0;
m_axis_tdata_prev <= {C_M_AXIS_DATA_WIDTH{1'b0}};
m_axis_tstrb_prev <= {C_M_AXIS_DATA_WIDTH/8{1'b0}};
end
else begin
counter <= counter_next;
first_time <= first_time_next;
length_prev <= length_prev_next;
m_axis_tdata_prev <= m_axis_tdata_prev_next;
m_axis_tstrb_prev <= m_axis_tstrb_prev_next;
end
end
end
else begin: SLAVE_WIDER
always @(*) begin
in_fifo_rd_en = 1'b0;
info_fifo_rd_en = 1'b0;
m_axis_tdata = s_axis_tdata_fifo[C_M_AXIS_DATA_WIDTH * (counter) +: C_M_AXIS_DATA_WIDTH];
m_axis_tstrb = s_axis_tstrb_fifo[C_M_AXIS_DATA_WIDTH/8 * (counter) +: C_M_AXIS_DATA_WIDTH/8];
m_axis_tlast = 1'b0;
counter_next = counter;
first_time_next = first_time;
m_axis_tvalid = 1'b0;
if(~in_fifo_empty) begin
if(first_time) begin
if(~info_fifo_empty) begin
m_axis_tvalid = 1'b1;
if(m_axis_tready) begin
info_fifo_rd_en = 1'b1;
first_time_next = 1'b0;
counter_next = counter + 1'b1;
end
end
end
else begin
m_axis_tvalid = 1'b1;
if(s_axis_tlast_fifo) begin // Last SLAVE word
if(~|s_axis_tstrb_fifo[C_M_AXIS_DATA_WIDTH/8 * (counter+1) +: C_M_AXIS_DATA_WIDTH/8]) begin
m_axis_tlast = 1'b1;
end
end
if(m_axis_tready) begin
counter_next = counter + 1'b1;
if(counter == S_M_RATIO_COUNT - 1) begin
in_fifo_rd_en = 1'b1;
counter_next = 0;
end
if(s_axis_tlast_fifo) begin // Last SLAVE word
if(~|s_axis_tstrb_fifo[C_M_AXIS_DATA_WIDTH/8 * (counter+1) +: C_M_AXIS_DATA_WIDTH/8]) begin
// Next MASTER strobe is empty == This master word is the last
// Clean up the current word
counter_next = 0;
first_time_next = 1'b1;
in_fifo_rd_en = 1'b1;
end
end
end
end
end
end
always @(posedge axi_aclk) begin
if (~axi_resetn) begin
counter <= 0;
first_time <= 1'b1;
length_prev <= 1'b0;
end
else begin
counter <= counter_next;
first_time <= first_time_next;
length_prev <= length_prev_next;
end
end
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLRBN_FUNCTIONAL_V
`define SKY130_FD_SC_MS__DLRBN_FUNCTIONAL_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr/sky130_fd_sc_ms__udp_dlatch_pr.v"
`celldefine
module sky130_fd_sc_ms__dlrbn (
Q ,
Q_N ,
RESET_B,
D ,
GATE_N
);
// Module ports
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE_N ;
// Local signals
wire RESET ;
wire intgate;
wire buf_Q ;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intgate, GATE_N );
sky130_fd_sc_ms__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q , D, intgate, RESET);
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLRBN_FUNCTIONAL_V |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Wed Oct 18 11:58:34 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ srio_gen2_0_stub.v
// Design : srio_gen2_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "srio_gen2_v4_0_5,Vivado 2015.1.0" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(sys_clkp, sys_clkn, sys_rst, log_clk_out,
phy_clk_out, gt_clk_out, gt_pcs_clk_out, drpclk_out, refclk_out, clk_lock_out, cfg_rst_out,
log_rst_out, buf_rst_out, phy_rst_out, gt_pcs_rst_out, gt0_qpll_clk_out,
gt0_qpll_out_refclk_out, srio_rxn0, srio_rxp0, srio_txn0, srio_txp0, s_axis_iotx_tvalid,
s_axis_iotx_tready, s_axis_iotx_tlast, s_axis_iotx_tdata, s_axis_iotx_tkeep,
s_axis_iotx_tuser, m_axis_iorx_tvalid, m_axis_iorx_tready, m_axis_iorx_tlast,
m_axis_iorx_tdata, m_axis_iorx_tkeep, m_axis_iorx_tuser, s_axi_maintr_rst,
s_axi_maintr_awvalid, s_axi_maintr_awready, s_axi_maintr_awaddr, s_axi_maintr_wvalid,
s_axi_maintr_wready, s_axi_maintr_wdata, s_axi_maintr_bvalid, s_axi_maintr_bready,
s_axi_maintr_bresp, s_axi_maintr_arvalid, s_axi_maintr_arready, s_axi_maintr_araddr,
s_axi_maintr_rvalid, s_axi_maintr_rready, s_axi_maintr_rdata, s_axi_maintr_rresp,
sim_train_en, force_reinit, phy_mce, phy_link_reset, phy_rcvd_mce, phy_rcvd_link_reset,
phy_debug, gtrx_disperr_or, gtrx_notintable_or, port_error, port_timeout, srio_host,
port_decode_error, deviceid, idle2_selected, phy_lcl_master_enable_out,
buf_lcl_response_only_out, buf_lcl_tx_flow_control_out, buf_lcl_phy_buf_stat_out,
phy_lcl_phy_next_fm_out, phy_lcl_phy_last_ack_out, phy_lcl_phy_rewind_out,
phy_lcl_phy_rcvd_buf_stat_out, phy_lcl_maint_only_out, port_initialized,
link_initialized, idle_selected, mode_1x)
/* synthesis syn_black_box black_box_pad_pin="sys_clkp,sys_clkn,sys_rst,log_clk_out,phy_clk_out,gt_clk_out,gt_pcs_clk_out,drpclk_out,refclk_out,clk_lock_out,cfg_rst_out,log_rst_out,buf_rst_out,phy_rst_out,gt_pcs_rst_out,gt0_qpll_clk_out,gt0_qpll_out_refclk_out,srio_rxn0,srio_rxp0,srio_txn0,srio_txp0,s_axis_iotx_tvalid,s_axis_iotx_tready,s_axis_iotx_tlast,s_axis_iotx_tdata[63:0],s_axis_iotx_tkeep[7:0],s_axis_iotx_tuser[31:0],m_axis_iorx_tvalid,m_axis_iorx_tready,m_axis_iorx_tlast,m_axis_iorx_tdata[63:0],m_axis_iorx_tkeep[7:0],m_axis_iorx_tuser[31:0],s_axi_maintr_rst,s_axi_maintr_awvalid,s_axi_maintr_awready,s_axi_maintr_awaddr[31:0],s_axi_maintr_wvalid,s_axi_maintr_wready,s_axi_maintr_wdata[31:0],s_axi_maintr_bvalid,s_axi_maintr_bready,s_axi_maintr_bresp[1:0],s_axi_maintr_arvalid,s_axi_maintr_arready,s_axi_maintr_araddr[31:0],s_axi_maintr_rvalid,s_axi_maintr_rready,s_axi_maintr_rdata[31:0],s_axi_maintr_rresp[1:0],sim_train_en,force_reinit,phy_mce,phy_link_reset,phy_rcvd_mce,phy_rcvd_link_reset,phy_debug[223:0],gtrx_disperr_or,gtrx_notintable_or,port_error,port_timeout[23:0],srio_host,port_decode_error,deviceid[15:0],idle2_selected,phy_lcl_master_enable_out,buf_lcl_response_only_out,buf_lcl_tx_flow_control_out,buf_lcl_phy_buf_stat_out[5:0],phy_lcl_phy_next_fm_out[5:0],phy_lcl_phy_last_ack_out[5:0],phy_lcl_phy_rewind_out,phy_lcl_phy_rcvd_buf_stat_out[5:0],phy_lcl_maint_only_out,port_initialized,link_initialized,idle_selected,mode_1x" */;
input sys_clkp;
input sys_clkn;
input sys_rst;
output log_clk_out;
output phy_clk_out;
output gt_clk_out;
output gt_pcs_clk_out;
output drpclk_out;
output refclk_out;
output clk_lock_out;
output cfg_rst_out;
output log_rst_out;
output buf_rst_out;
output phy_rst_out;
output gt_pcs_rst_out;
output gt0_qpll_clk_out;
output gt0_qpll_out_refclk_out;
input srio_rxn0;
input srio_rxp0;
output srio_txn0;
output srio_txp0;
input s_axis_iotx_tvalid;
output s_axis_iotx_tready;
input s_axis_iotx_tlast;
input [63:0]s_axis_iotx_tdata;
input [7:0]s_axis_iotx_tkeep;
input [31:0]s_axis_iotx_tuser;
output m_axis_iorx_tvalid;
input m_axis_iorx_tready;
output m_axis_iorx_tlast;
output [63:0]m_axis_iorx_tdata;
output [7:0]m_axis_iorx_tkeep;
output [31:0]m_axis_iorx_tuser;
input s_axi_maintr_rst;
input s_axi_maintr_awvalid;
output s_axi_maintr_awready;
input [31:0]s_axi_maintr_awaddr;
input s_axi_maintr_wvalid;
output s_axi_maintr_wready;
input [31:0]s_axi_maintr_wdata;
output s_axi_maintr_bvalid;
input s_axi_maintr_bready;
output [1:0]s_axi_maintr_bresp;
input s_axi_maintr_arvalid;
output s_axi_maintr_arready;
input [31:0]s_axi_maintr_araddr;
output s_axi_maintr_rvalid;
input s_axi_maintr_rready;
output [31:0]s_axi_maintr_rdata;
output [1:0]s_axi_maintr_rresp;
input sim_train_en;
input force_reinit;
input phy_mce;
input phy_link_reset;
output phy_rcvd_mce;
output phy_rcvd_link_reset;
output [223:0]phy_debug;
output gtrx_disperr_or;
output gtrx_notintable_or;
output port_error;
output [23:0]port_timeout;
output srio_host;
output port_decode_error;
output [15:0]deviceid;
output idle2_selected;
output phy_lcl_master_enable_out;
output buf_lcl_response_only_out;
output buf_lcl_tx_flow_control_out;
output [5:0]buf_lcl_phy_buf_stat_out;
output [5:0]phy_lcl_phy_next_fm_out;
output [5:0]phy_lcl_phy_last_ack_out;
output phy_lcl_phy_rewind_out;
output [5:0]phy_lcl_phy_rcvd_buf_stat_out;
output phy_lcl_maint_only_out;
output port_initialized;
output link_initialized;
output idle_selected;
output mode_1x;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFXBP_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__SDFXBP_PP_BLACKBOX_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__sdfxbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFXBP_PP_BLACKBOX_V
|
//`#start header` -- edit after this line, do not edit this line
// ========================================
//
// Proper 8+2-bit DitherPWM, derived from PWM component v3.30
// Werner Johansson, [email protected]
//
// ========================================
`include "cypress.v"
//`#end` -- edit above this line, do not edit this line
// Generated on 01/29/2016 at 19:06
// Component: DitherPWM
module DitherPWM (
output pwm,
input clock,
input reset
);
//`#start body` -- edit after this line, do not edit this line
/**************************************************************************/
/* Parameters */
/**************************************************************************/
/* localparams */
localparam PWM_DITHER_OFFSET0 = 2'd0;
localparam PWM_DITHER_OFFSET25 = 2'd1;
localparam PWM_DITHER_OFFSET50 = 2'd2;
localparam PWM_DITHER_OFFSET75 = 2'd3;
/* Control Register Bits*/
localparam PWM_CTRL_ENABLE = 8'h7; /* Enable the PWM */
localparam PWM_CTRL_DITHER_1 = 8'h1; /* Dither bit 1 */
localparam PWM_CTRL_DITHER_0 = 8'h0; /* Dither bit 0 */
/* Datapath Implementation */
localparam RESET_PERIOD_SHIFT_OP = `CS_ALU_OP_PASS;
localparam RESET_PERIOD_SRC_B = `CS_SRCB_D0;
localparam RESET_PERIOD_A0_SRC = `CS_A0_SRC___F0;
parameter dpconfig0 = {
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM0: Idle */
RESET_PERIOD_SHIFT_OP, `CS_SRCA_A0, RESET_PERIOD_SRC_B,
`CS_SHFT_OP_PASS, RESET_PERIOD_A0_SRC, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM1: Reset Period */
`CS_ALU_OP__DEC, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM2: Dec A0 (A0 = A0 - 1) */
RESET_PERIOD_SHIFT_OP, `CS_SRCA_A0, RESET_PERIOD_SRC_B,
`CS_SHFT_OP_PASS, RESET_PERIOD_A0_SRC, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM3: Reset Period */
RESET_PERIOD_SHIFT_OP, `CS_SRCA_A0, RESET_PERIOD_SRC_B,
`CS_SHFT_OP_PASS, RESET_PERIOD_A0_SRC, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM4: Reset Period*/
RESET_PERIOD_SHIFT_OP, `CS_SRCA_A0, RESET_PERIOD_SRC_B,
`CS_SHFT_OP_PASS, RESET_PERIOD_A0_SRC, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM5: Reset Period */
RESET_PERIOD_SHIFT_OP, `CS_SRCA_A0, RESET_PERIOD_SRC_B,
`CS_SHFT_OP_PASS, RESET_PERIOD_A0_SRC, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM6: Reset Period */
RESET_PERIOD_SHIFT_OP, `CS_SRCA_A0, RESET_PERIOD_SRC_B,
`CS_SHFT_OP_PASS, RESET_PERIOD_A0_SRC, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM7: Reset Period */
8'hFF, 8'h00, /*CFG9: */
8'hFF, 8'hFF, /*CFG11-10: */
`SC_CMPB_A0_D1, `SC_CMPA_A0_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
`SC_SI_A_DEFSI, /*CFG13-12: */
`SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
1'h0, `SC_FIFO1__A0, `SC_FIFO0_BUS,
`SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*CFG15-14: */
10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_FX,
`SC_FIFO__EDGE,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*CFG17-16: */
};
/* Internal signals */
wire cmp1_eq; /* A0 is equal to compare value 1 */
wire cmp1_less; /* A0 is less than to compare value 1 */
/* Clock Enable block signal */
wire ClockOutFromEnBlock;
/* wires for output registering logic */
wire tc_i;
reg tc_i_reg;
wire pwm_i;
reg pwm_i_reg;
/* Control Register Output */
wire [7:0] control;
/* Control Signals */
wire ctrl_enable;
wire [1:0] dithOff;
/* Triggers */
wire final_enable;
/* Dither Impl */
wire dith_sel;
reg [1:0] dith_count;
/* PWM output(s) */
wire pwm_temp;
/* Run Mode */
reg runmode_enable;
/* Datapath Implementation */
wire [2:0] cs_addr;
/* Clock Enable Block Component instance */
cy_psoc3_udb_clock_enable_v1_0 #(.sync_mode(`TRUE))
clock_enable_block (
/* output */.clock_out(ClockOutFromEnBlock),
/* input */ .clock_in(clock),
/* input */ .enable(1'b1)
);
/**************************************************************************/
/* Control Register Implementation */
/**************************************************************************/
generate
cy_psoc3_control #(.cy_force_order(`TRUE), .cy_ctrl_mode_1(8'h00), .cy_ctrl_mode_0(8'hFF))
ctrlreg(
/* input */ .clock(ClockOutFromEnBlock),
/* output [07:00] */ .control(control)
);
assign ctrl_enable = control[PWM_CTRL_ENABLE];
assign dithOff = {control[PWM_CTRL_DITHER_1], control[PWM_CTRL_DITHER_0]};
endgenerate
/**************************************************************************/
/* Run Mode Block Implementations */
/**************************************************************************/
generate
always @(posedge ClockOutFromEnBlock or posedge reset)
begin
if(reset)
runmode_enable <= 1'b0;
else
runmode_enable <= ctrl_enable;
end
assign final_enable = runmode_enable;
endgenerate
/**************************************************************************/
/* Dither implementation */
/**************************************************************************/
always @(posedge ClockOutFromEnBlock or posedge reset)
begin
if(reset)
begin
dith_count <= 0;
end
else
begin
if(tc_i)
begin
dith_count <= dith_count + 1;
end
end
end
/* SUJA modified */
assign dith_sel = (dithOff[1:0] == PWM_DITHER_OFFSET0) ? 1'b0 :
(dithOff[1:0] == PWM_DITHER_OFFSET25) ? ((dith_count == 0) ? 1'b1 : 1'b0) :
(dithOff[1:0] == PWM_DITHER_OFFSET50) ? ((dith_count == 0 || dith_count == 2) ? 1'b1 : 1'b0) :
/*(DitherOffset == PWM_DITHER_OFFSET75) ? */((dith_count == 3) ? 1'b0 : 1'b1) ;
/**************************************************************************/
/* Datapath Implementation */
/**************************************************************************/
generate
assign cs_addr = {tc_i,final_enable,reset};
endgenerate
generate
cy_psoc3_dp8 #(.cy_dpconfig_a(dpconfig0)) pwmdp(
/* input */ .clk(ClockOutFromEnBlock),
/* input [02:00] */ .cs_addr(cs_addr),
/* input */ .route_si(1'b0),
/* input */ .route_ci(1'b0),
/* input */ .f0_load(1'b0),
/* input */ .f1_load(1'b0),
/* input */ .d0_load(1'b0),
/* input */ .d1_load(1'b0),
/* output */ .ce0(cmp1_eq), /* Compare1 ( A0 == D0 )*/
/* output */ .cl0(cmp1_less), /* Compare1 ( A0 < D0 ) */
/* output */ .z0(tc_i), /* tc ( A0 == 0 ) */
/* output */ .ff0(),
/* output */ .ce1(),
/* output */ .cl1(),
/* output */ .z1(),
/* output */ .ff1(),
/* output */ .ov_msb(),
/* output */ .co_msb(),
/* output */ .cmsb(),
/* output */ .so(),
/* output */ .f0_bus_stat(),
/* output */ .f0_blk_stat(),
/* TODO: Can't use this because we exceed the number of outputs allowed from one Datapath. */
/* output */ .f1_bus_stat(),
/* output */ .f1_blk_stat()
);
endgenerate
/**************************************************************************/
/* Pulse Width output(s) implementation */
/**************************************************************************/
/* Register the pwm output to avoid glitches on the output terminal*/
always @(posedge ClockOutFromEnBlock)
begin
pwm_i_reg <= pwm_i ;
/* Register the tc to avoid glitches on the output terminal */
tc_i_reg <= tc_i & final_enable;
end
assign pwm = pwm_i_reg;
assign pwm_i = pwm_temp & final_enable;
assign pwm_temp = (!dith_sel) ? cmp1_less : (cmp1_less | cmp1_eq);
//`#end` -- edit above this line, do not edit this line
endmodule
//`#start footer` -- edit after this line, do not edit this line
//`#end` -- edit above this line, do not edit this line
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFSTP_1_V
`define SKY130_FD_SC_HVL__DFSTP_1_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog wrapper for dfstp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__dfstp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__dfstp_1 (
Q ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__dfstp_1 (
Q ,
CLK ,
D ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFSTP_1_V
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.20131013
// \ \ Application: netgen
// / / Filename: adder8.v
// /___/ /\ Timestamp: Mon May 1 11:49:13 2017
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog /home/rohith/Image-Watermarking/ipcore_dir/tmp/_cg/adder8.ngc /home/rohith/Image-Watermarking/ipcore_dir/tmp/_cg/adder8.v
// Device : 3s500efg320-5
// Input file : /home/rohith/Image-Watermarking/ipcore_dir/tmp/_cg/adder8.ngc
// Output file : /home/rohith/Image-Watermarking/ipcore_dir/tmp/_cg/adder8.v
// # of Modules : 1
// Design Name : adder8
// Xilinx : /opt/14.7/ISE_DS/ISE/
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module adder8 (
add, s, a, b
)/* synthesis syn_black_box syn_noprune=1 */;
input add;
output [8 : 0] s;
input [7 : 0] a;
input [7 : 0] b;
// synthesis translate_off
wire \blk00000001/sig0000002c ;
wire \blk00000001/sig0000002b ;
wire \blk00000001/sig0000002a ;
wire \blk00000001/sig00000029 ;
wire \blk00000001/sig00000028 ;
wire \blk00000001/sig00000027 ;
wire \blk00000001/sig00000026 ;
wire \blk00000001/sig00000025 ;
wire \blk00000001/sig00000024 ;
wire \blk00000001/sig00000023 ;
wire \blk00000001/sig00000022 ;
wire \blk00000001/sig00000021 ;
wire \blk00000001/sig00000020 ;
wire \blk00000001/sig0000001f ;
wire \blk00000001/sig0000001e ;
wire \blk00000001/sig0000001d ;
wire \blk00000001/sig0000001c ;
wire \blk00000001/sig0000001b ;
INV \blk00000001/blk0000001c (
.I(add),
.O(\blk00000001/sig0000001b )
);
INV \blk00000001/blk0000001b (
.I(add),
.O(\blk00000001/sig0000002c )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000001/blk0000001a (
.I0(a[0]),
.I1(add),
.I2(b[0]),
.O(\blk00000001/sig00000024 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000001/blk00000019 (
.I0(a[1]),
.I1(add),
.I2(b[1]),
.O(\blk00000001/sig00000025 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000001/blk00000018 (
.I0(a[2]),
.I1(add),
.I2(b[2]),
.O(\blk00000001/sig00000026 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000001/blk00000017 (
.I0(a[3]),
.I1(add),
.I2(b[3]),
.O(\blk00000001/sig00000027 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000001/blk00000016 (
.I0(a[4]),
.I1(add),
.I2(b[4]),
.O(\blk00000001/sig00000028 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000001/blk00000015 (
.I0(a[5]),
.I1(add),
.I2(b[5]),
.O(\blk00000001/sig00000029 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000001/blk00000014 (
.I0(a[6]),
.I1(add),
.I2(b[6]),
.O(\blk00000001/sig0000002a )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000001/blk00000013 (
.I0(a[7]),
.I1(add),
.I2(b[7]),
.O(\blk00000001/sig0000002b )
);
MUXCY \blk00000001/blk00000012 (
.CI(\blk00000001/sig0000001b ),
.DI(a[0]),
.S(\blk00000001/sig00000024 ),
.O(\blk00000001/sig0000001c )
);
XORCY \blk00000001/blk00000011 (
.CI(\blk00000001/sig0000001b ),
.LI(\blk00000001/sig00000024 ),
.O(s[0])
);
XORCY \blk00000001/blk00000010 (
.CI(\blk00000001/sig00000023 ),
.LI(\blk00000001/sig0000002c ),
.O(s[8])
);
MUXCY \blk00000001/blk0000000f (
.CI(\blk00000001/sig0000001c ),
.DI(a[1]),
.S(\blk00000001/sig00000025 ),
.O(\blk00000001/sig0000001d )
);
XORCY \blk00000001/blk0000000e (
.CI(\blk00000001/sig0000001c ),
.LI(\blk00000001/sig00000025 ),
.O(s[1])
);
MUXCY \blk00000001/blk0000000d (
.CI(\blk00000001/sig0000001d ),
.DI(a[2]),
.S(\blk00000001/sig00000026 ),
.O(\blk00000001/sig0000001e )
);
XORCY \blk00000001/blk0000000c (
.CI(\blk00000001/sig0000001d ),
.LI(\blk00000001/sig00000026 ),
.O(s[2])
);
MUXCY \blk00000001/blk0000000b (
.CI(\blk00000001/sig0000001e ),
.DI(a[3]),
.S(\blk00000001/sig00000027 ),
.O(\blk00000001/sig0000001f )
);
XORCY \blk00000001/blk0000000a (
.CI(\blk00000001/sig0000001e ),
.LI(\blk00000001/sig00000027 ),
.O(s[3])
);
MUXCY \blk00000001/blk00000009 (
.CI(\blk00000001/sig0000001f ),
.DI(a[4]),
.S(\blk00000001/sig00000028 ),
.O(\blk00000001/sig00000020 )
);
XORCY \blk00000001/blk00000008 (
.CI(\blk00000001/sig0000001f ),
.LI(\blk00000001/sig00000028 ),
.O(s[4])
);
MUXCY \blk00000001/blk00000007 (
.CI(\blk00000001/sig00000020 ),
.DI(a[5]),
.S(\blk00000001/sig00000029 ),
.O(\blk00000001/sig00000021 )
);
XORCY \blk00000001/blk00000006 (
.CI(\blk00000001/sig00000020 ),
.LI(\blk00000001/sig00000029 ),
.O(s[5])
);
MUXCY \blk00000001/blk00000005 (
.CI(\blk00000001/sig00000021 ),
.DI(a[6]),
.S(\blk00000001/sig0000002a ),
.O(\blk00000001/sig00000022 )
);
XORCY \blk00000001/blk00000004 (
.CI(\blk00000001/sig00000021 ),
.LI(\blk00000001/sig0000002a ),
.O(s[6])
);
MUXCY \blk00000001/blk00000003 (
.CI(\blk00000001/sig00000022 ),
.DI(a[7]),
.S(\blk00000001/sig0000002b ),
.O(\blk00000001/sig00000023 )
);
XORCY \blk00000001/blk00000002 (
.CI(\blk00000001/sig00000022 ),
.LI(\blk00000001/sig0000002b ),
.O(s[7])
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* 10M/100M Ethernet MAC with MII interface and TX and RX FIFOs
*/
module eth_mac_mii_fifo #
(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// Clock input style ("BUFG", "BUFR", "BUFIO", "BUFIO2")
// Use BUFR for Virtex-5, Virtex-6, 7-series
// Use BUFG for Ultrascale
// Use BUFIO2 for Spartan-6
parameter CLOCK_INPUT_STYLE = "BUFIO2",
parameter AXIS_DATA_WIDTH = 8,
parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8),
parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8),
parameter ENABLE_PADDING = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter TX_FIFO_DEPTH = 4096,
parameter TX_FIFO_PIPELINE_OUTPUT = 2,
parameter TX_FRAME_FIFO = 1,
parameter TX_DROP_OVERSIZE_FRAME = TX_FRAME_FIFO,
parameter TX_DROP_BAD_FRAME = TX_DROP_OVERSIZE_FRAME,
parameter TX_DROP_WHEN_FULL = 0,
parameter RX_FIFO_DEPTH = 4096,
parameter RX_FIFO_PIPELINE_OUTPUT = 2,
parameter RX_FRAME_FIFO = 1,
parameter RX_DROP_OVERSIZE_FRAME = RX_FRAME_FIFO,
parameter RX_DROP_BAD_FRAME = RX_DROP_OVERSIZE_FRAME,
parameter RX_DROP_WHEN_FULL = RX_DROP_OVERSIZE_FRAME
)
(
input wire rst,
input wire logic_clk,
input wire logic_rst,
/*
* AXI input
*/
input wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata,
input wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep,
input wire tx_axis_tvalid,
output wire tx_axis_tready,
input wire tx_axis_tlast,
input wire tx_axis_tuser,
/*
* AXI output
*/
output wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata,
output wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep,
output wire rx_axis_tvalid,
input wire rx_axis_tready,
output wire rx_axis_tlast,
output wire rx_axis_tuser,
/*
* MII interface
*/
input wire mii_rx_clk,
input wire [3:0] mii_rxd,
input wire mii_rx_dv,
input wire mii_rx_er,
input wire mii_tx_clk,
output wire [3:0] mii_txd,
output wire mii_tx_en,
output wire mii_tx_er,
/*
* Status
*/
output wire tx_error_underflow,
output wire tx_fifo_overflow,
output wire tx_fifo_bad_frame,
output wire tx_fifo_good_frame,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
output wire rx_fifo_overflow,
output wire rx_fifo_bad_frame,
output wire rx_fifo_good_frame,
/*
* Configuration
*/
input wire [7:0] ifg_delay
);
wire tx_clk;
wire rx_clk;
wire tx_rst;
wire rx_rst;
wire [7:0] tx_fifo_axis_tdata;
wire tx_fifo_axis_tvalid;
wire tx_fifo_axis_tready;
wire tx_fifo_axis_tlast;
wire tx_fifo_axis_tuser;
wire [7:0] rx_fifo_axis_tdata;
wire rx_fifo_axis_tvalid;
wire rx_fifo_axis_tlast;
wire rx_fifo_axis_tuser;
// synchronize MAC status signals into logic clock domain
wire tx_error_underflow_int;
reg [0:0] tx_sync_reg_1 = 1'b0;
reg [0:0] tx_sync_reg_2 = 1'b0;
reg [0:0] tx_sync_reg_3 = 1'b0;
reg [0:0] tx_sync_reg_4 = 1'b0;
assign tx_error_underflow = tx_sync_reg_3[0] ^ tx_sync_reg_4[0];
always @(posedge tx_clk or posedge tx_rst) begin
if (tx_rst) begin
tx_sync_reg_1 <= 1'b0;
end else begin
tx_sync_reg_1 <= tx_sync_reg_1 ^ {tx_error_underflow_int};
end
end
always @(posedge logic_clk or posedge logic_rst) begin
if (logic_rst) begin
tx_sync_reg_2 <= 1'b0;
tx_sync_reg_3 <= 1'b0;
tx_sync_reg_4 <= 1'b0;
end else begin
tx_sync_reg_2 <= tx_sync_reg_1;
tx_sync_reg_3 <= tx_sync_reg_2;
tx_sync_reg_4 <= tx_sync_reg_3;
end
end
wire rx_error_bad_frame_int;
wire rx_error_bad_fcs_int;
reg [1:0] rx_sync_reg_1 = 2'd0;
reg [1:0] rx_sync_reg_2 = 2'd0;
reg [1:0] rx_sync_reg_3 = 2'd0;
reg [1:0] rx_sync_reg_4 = 2'd0;
assign rx_error_bad_frame = rx_sync_reg_3[0] ^ rx_sync_reg_4[0];
assign rx_error_bad_fcs = rx_sync_reg_3[1] ^ rx_sync_reg_4[1];
always @(posedge rx_clk or posedge rx_rst) begin
if (rx_rst) begin
rx_sync_reg_1 <= 2'd0;
end else begin
rx_sync_reg_1 <= rx_sync_reg_1 ^ {rx_error_bad_fcs_int, rx_error_bad_frame_int};
end
end
always @(posedge logic_clk or posedge logic_rst) begin
if (logic_rst) begin
rx_sync_reg_2 <= 2'd0;
rx_sync_reg_3 <= 2'd0;
rx_sync_reg_4 <= 2'd0;
end else begin
rx_sync_reg_2 <= rx_sync_reg_1;
rx_sync_reg_3 <= rx_sync_reg_2;
rx_sync_reg_4 <= rx_sync_reg_3;
end
end
eth_mac_mii #(
.TARGET(TARGET),
.CLOCK_INPUT_STYLE(CLOCK_INPUT_STYLE),
.ENABLE_PADDING(ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH)
)
eth_mac_1g_mii_inst (
.rst(rst),
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_axis_tdata(tx_fifo_axis_tdata),
.tx_axis_tvalid(tx_fifo_axis_tvalid),
.tx_axis_tready(tx_fifo_axis_tready),
.tx_axis_tlast(tx_fifo_axis_tlast),
.tx_axis_tuser(tx_fifo_axis_tuser),
.rx_axis_tdata(rx_fifo_axis_tdata),
.rx_axis_tvalid(rx_fifo_axis_tvalid),
.rx_axis_tlast(rx_fifo_axis_tlast),
.rx_axis_tuser(rx_fifo_axis_tuser),
.mii_rx_clk(mii_rx_clk),
.mii_rxd(mii_rxd),
.mii_rx_dv(mii_rx_dv),
.mii_rx_er(mii_rx_er),
.mii_tx_clk(mii_tx_clk),
.mii_txd(mii_txd),
.mii_tx_en(mii_tx_en),
.mii_tx_er(mii_tx_er),
.tx_error_underflow(tx_error_underflow_int),
.rx_error_bad_frame(rx_error_bad_frame_int),
.rx_error_bad_fcs(rx_error_bad_fcs_int),
.ifg_delay(ifg_delay)
);
axis_async_fifo_adapter #(
.DEPTH(TX_FIFO_DEPTH),
.S_DATA_WIDTH(AXIS_DATA_WIDTH),
.S_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.S_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.M_DATA_WIDTH(8),
.M_KEEP_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.PIPELINE_OUTPUT(TX_FIFO_PIPELINE_OUTPUT),
.FRAME_FIFO(TX_FRAME_FIFO),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_OVERSIZE_FRAME(TX_DROP_OVERSIZE_FRAME),
.DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
.DROP_WHEN_FULL(TX_DROP_WHEN_FULL)
)
tx_fifo (
// AXI input
.s_clk(logic_clk),
.s_rst(logic_rst),
.s_axis_tdata(tx_axis_tdata),
.s_axis_tkeep(tx_axis_tkeep),
.s_axis_tvalid(tx_axis_tvalid),
.s_axis_tready(tx_axis_tready),
.s_axis_tlast(tx_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(tx_axis_tuser),
// AXI output
.m_clk(tx_clk),
.m_rst(tx_rst),
.m_axis_tdata(tx_fifo_axis_tdata),
.m_axis_tkeep(),
.m_axis_tvalid(tx_fifo_axis_tvalid),
.m_axis_tready(tx_fifo_axis_tready),
.m_axis_tlast(tx_fifo_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_axis_tuser),
// Status
.s_status_overflow(tx_fifo_overflow),
.s_status_bad_frame(tx_fifo_bad_frame),
.s_status_good_frame(tx_fifo_good_frame),
.m_status_overflow(),
.m_status_bad_frame(),
.m_status_good_frame()
);
axis_async_fifo_adapter #(
.DEPTH(RX_FIFO_DEPTH),
.S_DATA_WIDTH(8),
.S_KEEP_ENABLE(0),
.M_DATA_WIDTH(AXIS_DATA_WIDTH),
.M_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.M_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.PIPELINE_OUTPUT(RX_FIFO_PIPELINE_OUTPUT),
.FRAME_FIFO(RX_FRAME_FIFO),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_OVERSIZE_FRAME(RX_DROP_OVERSIZE_FRAME),
.DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
.DROP_WHEN_FULL(RX_DROP_WHEN_FULL)
)
rx_fifo (
// AXI input
.s_clk(rx_clk),
.s_rst(rx_rst),
.s_axis_tdata(rx_fifo_axis_tdata),
.s_axis_tkeep(0),
.s_axis_tvalid(rx_fifo_axis_tvalid),
.s_axis_tready(),
.s_axis_tlast(rx_fifo_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_axis_tuser),
// AXI output
.m_clk(logic_clk),
.m_rst(logic_rst),
.m_axis_tdata(rx_axis_tdata),
.m_axis_tkeep(rx_axis_tkeep),
.m_axis_tvalid(rx_axis_tvalid),
.m_axis_tready(rx_axis_tready),
.m_axis_tlast(rx_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(rx_axis_tuser),
// Status
.s_status_overflow(),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_overflow(rx_fifo_overflow),
.m_status_bad_frame(rx_fifo_bad_frame),
.m_status_good_frame(rx_fifo_good_frame)
);
endmodule
`resetall
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFXBP_SYMBOL_V
`define SKY130_FD_SC_HDLL__SDFXBP_SYMBOL_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__sdfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFXBP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLXBN_BLACKBOX_V
`define SKY130_FD_SC_MS__DLXBN_BLACKBOX_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlxbn (
Q ,
Q_N ,
D ,
GATE_N
);
output Q ;
output Q_N ;
input D ;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLXBN_BLACKBOX_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:34:06 10/26/2015
// Design Name: UART_rx
// Module Name: C:/Users/Juanjo/Documents/Juanjo/Facu/Arquitectura/Workspace Xilinx/UART/RXTest.v
// Project Name: UART
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: UART_rx
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module RXTest;
// Inputs
reg rx;
reg reset;
reg clock;
// Outputs
wire rx_done;
wire [7:0] d_out;
// Outputs
wire baud_rate_clock;
reg [5:0]counter;
reg [4:0]counter_baud;
// Instantiate the Unit Under Test (UUT)
UART_rx uut (
.rx(rx),
.s_tick(baud_rate_clock),
.reset(reset),
.clock(clock),
.rx_done(rx_done),
.d_out(d_out)
);
// Instantiate the Unit Under Test (UUT)
UART_baud_rate_generator baud_rate (
.clock(clock),
.baud_rate_clock(baud_rate_clock)
);
initial begin
// Initialize Inputs
rx = 1;
reset = 1;
clock = 0;
counter = 0;
counter_baud=0;
// Wait 100 ns for global reset to finish
#100;
reset = 0;
// Add stimulus here
end
always begin
clock = ~clock;
#10;
end
always @(baud_rate_clock) begin
counter_baud=counter_baud+1;
if(counter_baud==0) begin
counter=counter+1;
case (counter)
7: rx=0; //start bit
8: rx=1;
9: rx=1;
10: rx=1;
11: rx=0;
12: rx=1;
13: rx=0;
14: rx=1;
15: rx=0;
16: rx=1;// stop bit
17: rx=1;// otro porque soy re heavy
18: counter=0;
default: rx=1;
endcase;
end
end
endmodule
|
// ********************************************************************/
// Actel Corporation Proprietary and Confidential
// Copyright 2009 Actel Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
// Description: AMBA BFMs
// AHB Lite BFM
//
// Revision Information:
// Date Description
// 01Sep07 Initial Release
// 14Sep07 Updated for 1.2 functionality
// 25Sep07 Updated for 1.3 functionality
// 09Nov07 Updated for 1.4 functionality
// 18Dec08 Updated for 1.5 functionality
// 18Feb08 Updated for 1.6 functionality
// 08May08 2.0 for Soft IP Usage
// 08May08 2.0 for Soft IP Usage
// 04Feb09 2.1 Created fileset for G4 with CON bus back
//
//
// SVN Revision Information:
// SVN $Revision: 21608 $
// SVN $Date: 2013-12-02 16:03:36 -0800 (Mon, 02 Dec 2013) $
//
//
// Resolved SARs
// SAR Date Who Description
//
//
// Notes:
//
// Release 2.0
// Soft IP Release of Internal Hard IP Models
// Release 2.1
// Added else and case support
//
// Requested Enhancements
// Ability to do back-to-back single cycle checking of the IO_IN inputs
//
//
//
// *********************************************************************/
`timescale 1 ns / 100 ps
module BFM_MAIN (SYSCLK, SYSRSTN, PCLK, HCLK, HRESETN,
HADDR, HBURST, HMASTLOCK, HPROT, HSIZE, HTRANS, HWRITE, HWDATA, HRDATA, HREADY, HRESP, HSEL,
INTERRUPT, GP_OUT, GP_IN, EXT_WR, EXT_RD, EXT_ADDR, EXT_DATA, EXT_WAIT,
CON_ADDR, CON_DATA, CON_RD, CON_WR, CON_BUSY,
INSTR_OUT, INSTR_IN, FINISHED, FAILED);
parameter OPMODE = 0;
parameter VECTFILE = "test.vec";
parameter MAX_INSTRUCTIONS = 16384;
parameter MAX_STACK = 1024;
parameter MAX_MEMTEST = 65536;
parameter TPD = 1;
parameter DEBUGLEVEL = -1;
parameter CON_SPULSE = 0;
parameter ARGVALUE0 = 0;
parameter ARGVALUE1 = 0;
parameter ARGVALUE2 = 0;
parameter ARGVALUE3 = 0;
parameter ARGVALUE4 = 0;
parameter ARGVALUE5 = 0;
parameter ARGVALUE6 = 0;
parameter ARGVALUE7 = 0;
parameter ARGVALUE8 = 0;
parameter ARGVALUE9 = 0;
parameter ARGVALUE10 = 0;
parameter ARGVALUE11 = 0;
parameter ARGVALUE12 = 0;
parameter ARGVALUE13 = 0;
parameter ARGVALUE14 = 0;
parameter ARGVALUE15 = 0;
parameter ARGVALUE16 = 0;
parameter ARGVALUE17 = 0;
parameter ARGVALUE18 = 0;
parameter ARGVALUE19 = 0;
parameter ARGVALUE20 = 0;
parameter ARGVALUE21 = 0;
parameter ARGVALUE22 = 0;
parameter ARGVALUE23 = 0;
parameter ARGVALUE24 = 0;
parameter ARGVALUE25 = 0;
parameter ARGVALUE26 = 0;
parameter ARGVALUE27 = 0;
parameter ARGVALUE28 = 0;
parameter ARGVALUE29 = 0;
parameter ARGVALUE30 = 0;
parameter ARGVALUE31 = 0;
parameter ARGVALUE32 = 0;
parameter ARGVALUE33 = 0;
parameter ARGVALUE34 = 0;
parameter ARGVALUE35 = 0;
parameter ARGVALUE36 = 0;
parameter ARGVALUE37 = 0;
parameter ARGVALUE38 = 0;
parameter ARGVALUE39 = 0;
parameter ARGVALUE40 = 0;
parameter ARGVALUE41 = 0;
parameter ARGVALUE42 = 0;
parameter ARGVALUE43 = 0;
parameter ARGVALUE44 = 0;
parameter ARGVALUE45 = 0;
parameter ARGVALUE46 = 0;
parameter ARGVALUE47 = 0;
parameter ARGVALUE48 = 0;
parameter ARGVALUE49 = 0;
parameter ARGVALUE50 = 0;
parameter ARGVALUE51 = 0;
parameter ARGVALUE52 = 0;
parameter ARGVALUE53 = 0;
parameter ARGVALUE54 = 0;
parameter ARGVALUE55 = 0;
parameter ARGVALUE56 = 0;
parameter ARGVALUE57 = 0;
parameter ARGVALUE58 = 0;
parameter ARGVALUE59 = 0;
parameter ARGVALUE60 = 0;
parameter ARGVALUE61 = 0;
parameter ARGVALUE62 = 0;
parameter ARGVALUE63 = 0;
parameter ARGVALUE64 = 0;
parameter ARGVALUE65 = 0;
parameter ARGVALUE66 = 0;
parameter ARGVALUE67 = 0;
parameter ARGVALUE68 = 0;
parameter ARGVALUE69 = 0;
parameter ARGVALUE70 = 0;
parameter ARGVALUE71 = 0;
parameter ARGVALUE72 = 0;
parameter ARGVALUE73 = 0;
parameter ARGVALUE74 = 0;
parameter ARGVALUE75 = 0;
parameter ARGVALUE76 = 0;
parameter ARGVALUE77 = 0;
parameter ARGVALUE78 = 0;
parameter ARGVALUE79 = 0;
parameter ARGVALUE80 = 0;
parameter ARGVALUE81 = 0;
parameter ARGVALUE82 = 0;
parameter ARGVALUE83 = 0;
parameter ARGVALUE84 = 0;
parameter ARGVALUE85 = 0;
parameter ARGVALUE86 = 0;
parameter ARGVALUE87 = 0;
parameter ARGVALUE88 = 0;
parameter ARGVALUE89 = 0;
parameter ARGVALUE90 = 0;
parameter ARGVALUE91 = 0;
parameter ARGVALUE92 = 0;
parameter ARGVALUE93 = 0;
parameter ARGVALUE94 = 0;
parameter ARGVALUE95 = 0;
parameter ARGVALUE96 = 0;
parameter ARGVALUE97 = 0;
parameter ARGVALUE98 = 0;
parameter ARGVALUE99 = 0;
localparam [1:(3)*8] BFM_VERSION = "2.1";
localparam [1:(7)*8] BFM_DATE = "04FEB09";
input SYSCLK;
input SYSRSTN;
output PCLK;
wire PCLK;
output HCLK;
wire HCLK;
output HRESETN;
wire #TPD HRESETN;
output[31:0] HADDR;
wire[31:0] #TPD HADDR;
output[2:0] HBURST;
wire[2:0] #TPD HBURST;
output HMASTLOCK;
wire #TPD HMASTLOCK;
output[3:0] HPROT;
wire[3:0] #TPD HPROT;
output[2:0] HSIZE;
wire[2:0] #TPD HSIZE;
output[1:0] HTRANS;
wire[1:0] #TPD HTRANS;
output HWRITE;
wire #TPD HWRITE;
output[31:0] HWDATA;
wire[31:0] #TPD HWDATA;
input[31:0] HRDATA;
input HREADY;
input HRESP;
output[15:0] HSEL;
wire[15:0] #TPD HSEL;
input[255:0] INTERRUPT;
output[31:0] GP_OUT;
wire[31:0] #TPD GP_OUT;
input[31:0] GP_IN;
output EXT_WR;
wire #TPD EXT_WR;
output EXT_RD;
wire #TPD EXT_RD;
output[31:0] EXT_ADDR;
wire[31:0] #TPD EXT_ADDR;
inout[31:0] EXT_DATA;
wire[31:0] #TPD EXT_DATA;
input EXT_WAIT;
input[15:0] CON_ADDR;
inout[31:0] CON_DATA;
wire[31:0] #TPD CON_DATA;
wire[31:0] CON_DATA_xhdl1;
input CON_RD;
input CON_WR;
output CON_BUSY;
reg CON_BUSY;
output[31:0] INSTR_OUT;
reg[31:0] INSTR_OUT;
input[31:0] INSTR_IN;
output FINISHED;
wire #TPD FINISHED;
output FAILED;
wire #TPD FAILED;
localparam NUL = 0;
wire SCLK;
integer command [0:255];
integer vectors [0:MAX_INSTRUCTIONS - 1];
reg HRESETN_P0;
reg[2:0] HBURST_P0;
reg HMASTLOCK_P0;
reg[3:0] HPROT_P0;
reg[1:0] HTRANS_P0;
reg HWRITE_P0;
wire[31:0] HWDATA_P0;
reg[31:0] HADDR_P0;
reg[31:0] HADDR_P1;
reg[2:0] HSIZE_P0;
reg[2:0] HSIZE_P1;
reg[15:0] HSEL_P0;
reg WRITE_P1;
reg WRITE_P0;
reg READ_P0;
reg READ_P1;
reg POLL_P0;
reg POLL_P1;
reg RDCHK_P0;
reg RDCHK_P1;
reg[31:0] RDATA_P0;
reg[31:0] MDATA_P0;
reg[31:0] WDATA_P0;
reg[31:0] RDATA_P1;
reg[31:0] MDATA_P1;
reg[31:0] WDATA_P1;
reg[31:0] EIO_RDATA_P0;
reg[31:0] EIO_MDATA_P0;
integer EIO_LINENO_P0;
reg EIO_RDCHK_P0;
reg EIO_RDCHK_P1;
reg[31:0] EIO_RDATA_P1;
reg[31:0] EIO_MDATA_P1;
integer EIO_LINENO_P1;
reg EXTWR_P0;
reg EXTRD_P0;
reg EXTRD_P1;
reg GPIORD_P0;
reg GPIOWR_P0;
wire[31:0] EXT_DIN;
reg[31:0] EXT_DOUT;
reg[31:0] EXTADDR_P0;
reg[31:0] EXTADDR_P1;
wire[31:0] CON_DIN;
reg[31:0] CON_DOUT;
reg CON_RDP1;
reg CON_WRP1;
integer LINENO_P0;
integer LINENO_P1;
reg HCLK_STOP = 1'b0;
reg[31:0] GPOUT_P0;
reg[1:(80)*8] FILENAME;
reg FINISHED_P0;
reg FAILED_P0;
reg DRIVEX_CLK;
reg DRIVEX_RST;
reg DRIVEX_ADD;
reg DRIVEX_DAT;
parameter[31:0] ZEROLV = {32{1'b0}};
parameter[255:0] ZERO256 = {256{1'b0}};
parameter TPDns = TPD * 1;
assign SCLK = SYSCLK ;
integer stack[0:MAX_STACK - 1];
integer return_value;
integer stkptr;
integer cmd_lineno;
integer DEBUG;
integer logopen;
`include "bfm_package.v"
function integer len_string;
input len;
integer len;
integer nparas;
integer nchars;
integer n;
begin
nchars = len / 65536;
nparas = len % 65536;
n = 2 + nparas + 1 + ((nchars - 1) / 4);
len_string = n;
end
endfunction
function [1:(256)*8] extract_string;
input cptr;
integer cptr;
reg[1:(256)*8] pstr;
reg[1:(256)*8] str;
integer i;
integer p;
integer j;
reg[31:0] tmp_un;
integer nparas;
integer nchars;
integer len;
integer b;
begin
nchars = vectors[cptr + 1] / 65536;
nparas = vectors[cptr + 1] % 65536;
len = 2 + nparas + 1 + ((nchars - 1) / 4);
for(p = 1; p <= 256*8; p = p + 1) pstr[p]=0;
i = cptr + 2 + nparas;
j = 3;
begin : xhdl_3
integer p;
for(p = 1; p <= nchars; p = p + 1)
begin
tmp_un = vectors[i];
for (b=1;b<=8;b=b+1)
pstr[(p-1)*8+b] = tmp_un[j * 8 + 8-b];
if (j == 0)
begin
i = i + 1;
j = 4;
end
j = j - 1;
end
end
case (nparas)
0 :
begin
$sformat(str, pstr);
end
1 :
begin
$sformat(str, pstr, command[2]);
end
2 :
begin
$sformat(str, pstr, command[2], command[3]);
end
3 :
begin
$sformat(str, pstr, command[2], command[3], command[4]);
end
4 :
begin
$sformat(str, pstr, command[2], command[3], command[4], command[5]);
end
5 :
begin
$sformat(str, pstr, command[2], command[3], command[4], command[5], command[6]);
end
6 :
begin
$sformat(str, pstr, command[2], command[3], command[4], command[5], command[6], command[7]);
end
7 :
begin
$sformat(str, pstr, command[2], command[3], command[4], command[5], command[6], command[7], command[8]);
end
default :
begin
$display("String Error (FAILURE)");
end
endcase
extract_string = str;
end
endfunction
integer lastrandom;
integer setrandom;
integer ERRORS;
integer reset_pulse;
parameter[2:0] idle = 0;
parameter[2:0] init = 1;
parameter[2:0] active = 2;
parameter[2:0] done = 3;
parameter[2:0] fill = 4;
parameter[2:0] scan = 5;
integer mt_addr;
integer mt_size;
integer mt_align;
integer mt_cycles;
integer mt_seed;
reg[2:0] mt_state;
integer mt_image[0:MAX_MEMTEST-1];
integer mt_ad;
integer mt_op;
integer mt_base;
integer mt_base2;
reg mt_readok;
integer mt_reads;
integer mt_writes;
integer mt_nops;
integer var_ltimer;
integer var_licycles;
integer instructions_timer;
reg mt_dual;
reg mt_fill;
reg mt_scan;
reg mt_restart;
integer mt_fillad;
function automatic integer get_para_value;
input isvar;
input x;
integer x;
integer y;
integer x30x16;
integer x14x13;
integer x12x0;
integer x12x8;
integer x7x0;
reg[31:0] xlv;
integer offset;
begin
if (isvar)
begin
xlv = x;
x30x16 = xlv[30:16];
x14x13 = xlv[14:13];
x12x0 = xlv[12:0];
x12x8 = xlv[12:8];
x7x0 = xlv[7:0];
offset = 0;
if ((xlv[15]) == 1'b1)
begin
// ARRAY offset in upper 16 bits
offset = get_para_value(1, x30x16);
end
case (x14x13)
3 :
begin
case (x12x8)
D_NORMAL :
begin
case (x7x0)
// E_CONST
D_RETVALUE :
begin
y = return_value;
end
D_TIME :
begin
y = ( $time / 1);
end
D_DEBUG :
begin
y = DEBUG;
end
D_LINENO :
begin
y = cmd_lineno;
end
D_ERRORS :
begin
y = ERRORS;
end
D_TIMER :
begin
y = instructions_timer - 1;
end
D_LTIMER :
begin
y = var_ltimer;
end
D_LICYCLES :
begin
y = var_licycles;
end
default :
begin
$display("Illegal Parameter P0 (FAILURE)");
end
endcase
end
D_ARGVALUE :
begin
case (x7x0)
0 : y = ARGVALUE0;
1 : y = ARGVALUE1;
2 : y = ARGVALUE2;
3 : y = ARGVALUE3;
4 : y = ARGVALUE4;
5 : y = ARGVALUE5;
6 : y = ARGVALUE6;
7 : y = ARGVALUE7;
8 : y = ARGVALUE8;
9 : y = ARGVALUE9;
10 : y = ARGVALUE10;
11 : y = ARGVALUE11;
12 : y = ARGVALUE12;
13 : y = ARGVALUE13;
14 : y = ARGVALUE14;
15 : y = ARGVALUE15;
16 : y = ARGVALUE16;
17 : y = ARGVALUE17;
18 : y = ARGVALUE18;
19 : y = ARGVALUE19;
20 : y = ARGVALUE20;
21 : y = ARGVALUE21;
22 : y = ARGVALUE22;
23 : y = ARGVALUE23;
24 : y = ARGVALUE24;
25 : y = ARGVALUE25;
26 : y = ARGVALUE26;
27 : y = ARGVALUE27;
28 : y = ARGVALUE28;
29 : y = ARGVALUE29;
30 : y = ARGVALUE30;
31 : y = ARGVALUE31;
32 : y = ARGVALUE32;
33 : y = ARGVALUE33;
34 : y = ARGVALUE34;
35 : y = ARGVALUE35;
36 : y = ARGVALUE36;
37 : y = ARGVALUE37;
38 : y = ARGVALUE38;
39 : y = ARGVALUE39;
40 : y = ARGVALUE40;
41 : y = ARGVALUE41;
42 : y = ARGVALUE42;
43 : y = ARGVALUE43;
44 : y = ARGVALUE44;
45 : y = ARGVALUE45;
46 : y = ARGVALUE46;
47 : y = ARGVALUE47;
48 : y = ARGVALUE48;
49 : y = ARGVALUE49;
50 : y = ARGVALUE50;
51 : y = ARGVALUE51;
52 : y = ARGVALUE52;
53 : y = ARGVALUE53;
54 : y = ARGVALUE54;
55 : y = ARGVALUE55;
56 : y = ARGVALUE56;
57 : y = ARGVALUE57;
58 : y = ARGVALUE58;
59 : y = ARGVALUE59;
60 : y = ARGVALUE60;
61 : y = ARGVALUE61;
62 : y = ARGVALUE62;
63 : y = ARGVALUE63;
64 : y = ARGVALUE64;
65 : y = ARGVALUE65;
66 : y = ARGVALUE66;
67 : y = ARGVALUE67;
68 : y = ARGVALUE68;
69 : y = ARGVALUE69;
70 : y = ARGVALUE70;
71 : y = ARGVALUE71;
72 : y = ARGVALUE72;
73 : y = ARGVALUE73;
74 : y = ARGVALUE74;
75 : y = ARGVALUE75;
76 : y = ARGVALUE76;
77 : y = ARGVALUE77;
78 : y = ARGVALUE78;
79 : y = ARGVALUE79;
80 : y = ARGVALUE80;
81 : y = ARGVALUE81;
82 : y = ARGVALUE82;
83 : y = ARGVALUE83;
84 : y = ARGVALUE84;
85 : y = ARGVALUE85;
86 : y = ARGVALUE86;
87 : y = ARGVALUE87;
88 : y = ARGVALUE88;
89 : y = ARGVALUE89;
90 : y = ARGVALUE90;
91 : y = ARGVALUE91;
92 : y = ARGVALUE92;
93 : y = ARGVALUE93;
94 : y = ARGVALUE94;
95 : y = ARGVALUE95;
96 : y = ARGVALUE96;
97 : y = ARGVALUE97;
98 : y = ARGVALUE98;
99 : y = ARGVALUE99;
default :
begin
$display("Illegal Parameter P1 (FAILURE)");
end
endcase
end
D_RAND :
begin
lastrandom = random(lastrandom);
y = mask_randomN(lastrandom, x7x0);
end
D_RANDSET :
begin
setrandom = lastrandom;
lastrandom = random(lastrandom);
y = mask_randomN(lastrandom, x7x0);
end
D_RANDRESET :
begin
lastrandom = setrandom;
lastrandom = random(lastrandom);
y = mask_randomN(lastrandom, x7x0);
end
default :
begin
$display("Illegal Parameter P2 (FAILURE)");
end
endcase
end
2 :
begin
y = stack[stkptr - x12x0 + offset]; // E_STACK
end
1 :
begin
y = stack[x12x0 + offset]; // E_ADDR
end
0 :
begin
y = x12x0; // E_DATA
end
default :
begin
$display("Illegal Parameter P3 (FAILURE)");
end
endcase
end
else
begin
// immediate data
y = x;
end
get_para_value = y;
end
endfunction
function integer get_storeaddr;
input x;
integer x;
input stkptr;
integer stkptr;
integer sa;
integer x30x16;
integer x14x13;
integer x12x0;
integer x12x8;
integer x7x0;
reg[31:0] xlv;
integer offset;
begin
xlv = x;
x30x16 = xlv[30:16];
x14x13 = xlv[14:13];
x12x0 = xlv[12:0];
x12x8 = xlv[12:8];
x7x0 = xlv[7:0];
offset = 0;
if ((xlv[15]) == 1'b1)
begin
// ARRAY offset in upper 16 bits
offset = get_para_value(1, x30x16);
end
case (x14x13)
3 :
begin
$display("$Variables not allowed (FAILURE)");
end
2 :
begin
sa = stkptr - x12x0 + offset; // E_STACK
end
1 :
begin
sa = x12x0 + offset; // E_ADDR
end
0 :
begin
$display("Immediate data not allowed (FAILURE)");
end
default :
begin
$display("Illegal Parameter P3 (FAILURE)");
end
endcase
get_storeaddr = sa;
end
endfunction
//---------------------------------------------------------------------------------------
// NOTE THIS IS IN ONE HUGE PROCESS FOR SIMULATION PERFORMANCE REASONS
always @(posedge SCLK or negedge SYSRSTN)
begin : BFM
parameter[0:0] OK1 = 0;
parameter[0:0] OK2 = 1;
integer flog;
reg initdone;
integer Loopcmd[0:4];
reg [31:0] commandLV [0:255];
integer Nvectors;
integer cptr;
integer lptr;
integer fptr;
integer loopcounter;
reg[31:0] command0;
reg[1:0] cmd_size;
integer cmd_cmd;
integer cmd_cmdx4;
integer cmd_scmd;
integer command_length;
integer command_timeout;
reg[2:0] command_size;
reg[31:0] command_address;
reg[31:0] command_data;
reg[31:0] command_mask;
reg do_case;
reg do_read;
reg do_bwrite;
reg do_bread;
reg do_write;
reg do_poll;
reg do_flush;
reg do_idle;
reg do_io;
reg cmd_active;
reg last_match;
integer wait_counter;
integer bitn;
integer timer;
integer n;
integer i;
integer j;
integer x;
integer y;
integer v;
reg[1:(256)*8] str;
reg[1:(256)*8] logstr;
reg[1:(256)*8] logfile;
integer burst_address;
integer burst_length;
integer burst_count;
integer burst_addrinc;
integer burst_data[0:8191];
reg[1:(8)*8] istr;
reg bfm_done;
reg filedone;
reg ch;
integer tableid;
integer characters;
integer int_vector;
integer call_address;
integer return_address;
integer jump_address;
integer nparas;
integer data_start;
integer data_inc;
integer hresp_mode;
integer bfm_mode;
integer instruct_cycles;
integer instuct_count;
integer setvar;
integer newvalue;
reg[31:0] EXP;
reg[31:0] GOT;
reg DATA_MATCH_AHB;
reg DATA_MATCH_EXT;
reg DATA_MATCH_IO;
reg hresp_occured;
reg[0:0] HRESP_STATE;
reg[1:(10)*8] tmpstr;
reg ahb_lock;
reg[3:0] ahb_prot;
reg[2:0] ahb_burst;
integer storeaddr;
reg piped_activity;
reg [1:(256)*8] filenames[0:100];
integer NFILES;
integer filemult;
reg[1:0] su_xsize;
reg[5:0] su_xainc;
reg[16:0] su_xrate;
reg su_flush;
integer su_noburst;
reg su_align;
reg bfm_run;
reg bfm_single;
reg int_active;
reg su_endsim;
integer count_xrate;
reg insert_busy;
reg log_ahb;
reg log_ext;
reg log_gpio;
reg log_bfm;
integer bfmc_version;
integer cmpvalue;
integer vectors_version;
integer wait_time;
reg ahbc_hwrite;
reg[1:0] ahbc_htrans;
reg[3:0] ahbc_prot;
reg[2:0] ahbc_burst;
reg ahbc_lock;
reg ahb_activity;
reg [256*8:0] vchar;
integer c;
integer b;
integer ni;
reg zerocycle;
integer mt_dual;
integer passed[0:15];
integer npass;
integer returnstk[0:255];
reg[8:0] wptr_cstk;
reg[8:0] rptr_cstk;
integer casedone[0:255];
integer casedepth;
if (SYSRSTN == 1'b0)
begin
// These are auto initialized in VHDL
instruct_cycles = 0;
instuct_count = 0;
ERRORS = 0;
NFILES = 0;
filemult = 65536;
HRESP_STATE = OK1;
reset_pulse = 0;
var_ltimer = 0;
var_licycles = 0;
//
HCLK_STOP <= 1'b0 ;
DEBUG <= DEBUGLEVEL ;
HADDR_P0 <= {32{1'b0}} ;
HBURST_P0 <= {3{1'b0}} ;
HMASTLOCK_P0 <= 1'b0 ;
HPROT_P0 <= {4{1'b0}} ;
HSIZE_P0 <= {3{1'b0}} ;
HTRANS_P0 <= {2{1'b0}} ;
HWRITE_P0 <= 1'b0 ;
GPOUT_P0 <= {32{1'b0}} ;
INSTR_OUT <= {32{1'b0}} ;
WRITE_P0 <= 1'b0 ;
READ_P0 <= 1'b0 ;
RDATA_P0 <= {32{1'b0}} ;
MDATA_P0 <= {32{1'b0}} ;
WDATA_P0 <= {32{1'b0}} ;
GPIORD_P0 <= 1'b0 ;
EXTWR_P0 <= 1'b0 ;
EXTRD_P0 <= 1'b0 ;
EXTADDR_P0 <= {32{1'b0}} ;
EXT_DOUT <= {32{1'b0}} ;
FINISHED_P0 <= 1'b0 ;
FILENAME[1:8] <= {"UNKNOWN", 8'b0 } ;
READ_P1 <= 1'b0 ;
RDATA_P1 <= {32{1'b0}} ;
MDATA_P1 <= {32{1'b0}} ;
LINENO_P1 <= 0 ;
HADDR_P1 <= {32{1'b0}} ;
FAILED_P0 <= 1'b0 ;
HRESETN_P0 <= 1'b0 ;
CON_BUSY <= 1'b0 ;
LINENO_P1 <= 0 ;
POLL_P0 <= 1'b0 ;
POLL_P1 <= 1'b0 ;
DRIVEX_CLK <= 0 ;
DRIVEX_RST <= 0 ;
DRIVEX_ADD <= 0 ;
DRIVEX_DAT <= 0 ;
initdone = 0;
cptr = 0;
cmd_active = 0;
bfm_mode = 0;
do_case = 0;
do_flush = 0;
do_write = 0;
do_read = 0;
do_bwrite = 0;
do_bread = 0;
do_poll = 0;
do_idle = 0;
stkptr = 0;
hresp_mode = 0;
command_timeout = 512;
piped_activity = 0;
ERRORS = 0;
hresp_occured = 0;
ahb_lock = 1'b0;
ahb_prot = 4'b0011;
ahb_burst = 3'b001;
bfm_done = 0;
su_xsize = 2;
su_xainc = 4;
su_xrate = 0;
su_flush = 0;
su_align = 0;
su_endsim = 0;
return_value = 0;
bfm_run = 0;
count_xrate = 0;
log_ahb = 0;
log_ext = 0;
log_gpio = 0;
log_bfm = 0;
logopen = NUL;
insert_busy = 0;
wait_time = 0;
lastrandom =1;
setrandom =1;
logopen =1;
npass = 0;
wptr_cstk = 0;
rptr_cstk = 0;
casedepth = 0;
su_noburst = 0;
end
else
begin
CON_RDP1 <= CON_RD ;
CON_WRP1 <= CON_WR ;
EXTWR_P0 <= 1'b0 ;
EXTRD_P0 <= 1'b0 ;
GPIORD_P0 <= 1'b0 ;
GPIOWR_P0 <= 1'b0 ;
do_io = 0;
if (~initdone)
begin
$display(" ");
$display("###########################################################################");
$display("AMBA BFM Model");
$display("Version %s %s",BFM_VERSION,BFM_DATE);
$display(" ");
$display("Opening BFM Script file %0s", VECTFILE);
if (~initdone & OPMODE != 2)
begin
$readmemh(VECTFILE,vectors);
v = 3000;
initdone = 1;
Nvectors = vectors[4];
bfmc_version = vectors[0] % 65536;
vectors_version = vectors[0] / 65536;
$display("Read %0d Vectors - Compiler Version %0d.%0d", Nvectors, vectors_version, bfmc_version);
if (vectors_version != C_VECTORS_VERSION)
begin
$display("Incorrect vectors file format for this BFM %0s (FAILURE) == ", VECTFILE);
$stop;
end
cptr = vectors[1];
fptr = vectors[2];
stkptr = vectors[3]; // Start Stack after required global storage area
stack[stkptr] = 0; // put a return address of zero on the stack
stkptr = stkptr +1;
if (cptr == 0)
begin
$display("BFM Compiler reported errors (FAILURE)");
$stop;
end
// extract files names
$display("BFM:Filenames referenced in Vectors");
command0 = vectors[fptr];
cmd_cmd = vectors[fptr] % 256;
while (cmd_cmd == C_FILEN)
begin
command_length = len_string(vectors[fptr+1]);
str = extract_string(fptr);
$display(" %0s", str);
begin : xhdl_6
integer i,b;
for(i = 0; i<256; i=i+1)
for (b=1;b<=8;b=b+1) filenames[NFILES][i*8+b] = str[i*8+b];
end
NFILES = NFILES + 1;
fptr = fptr + command_length;
command0 = to_slv32(vectors[fptr]);
cmd_cmd = vectors[fptr] % 256;
end
filemult = 65536;
if (NFILES > 1) filemult = 32768;
if (NFILES > 2) filemult = 16384;
if (NFILES > 4) filemult = 8912;
if (NFILES > 8) filemult = 4096;
if (NFILES > 16) filemult = 2048;
if (NFILES > 32) filemult = 1024;
bfm_run = (OPMODE == 0);
end
end
if (OPMODE == 2 & ~initdone)
begin
filemult = 65536;
initdone = 1;
bfm_run = 0;
stkptr = vectors[3]+1;
stack[stkptr] =0;
stkptr = stkptr+1;
end
//--------------------------------------------------------------------------
// see whether reset needs deasserting
if (reset_pulse <= 1)
begin
HRESETN_P0 <= 1'b1 ;
end
else
begin
reset_pulse = reset_pulse - 1;
end
//----------------------------------------------------------------------------------------------------------
case (HRESP_STATE)
OK1 :
begin
if (HRESP == 1'b1 & HREADY == 1'b1)
begin
$display("BFM: HRESP Signaling Protocol Error T2 (ERROR)");
ERRORS = ERRORS + 1;
end
if (HRESP == 1'b1 & HREADY == 1'b0)
begin
HRESP_STATE = OK2;
end
end
OK2 :
begin
if (HRESP == 1'b0 | HREADY == 1'b0)
begin
$display("BFM: HRESP Signaling Protocol Error T3 (ERROR)");
ERRORS = ERRORS + 1;
end
if (HRESP == 1'b1 & HREADY == 1'b1)
begin
HRESP_STATE = OK1;
end
case (hresp_mode)
0 :
begin
// should not have occured
$display("BFM: Unexpected HRESP Signaling Occured (ERROR)");
ERRORS = ERRORS + 1;
end
1 :
begin
// Ignore
hresp_occured = 1;
end
default :
begin
$display("BFM: HRESP mode is not correctly set (ERROR)");
ERRORS = ERRORS + 1;
end
endcase
end
endcase
//----------------------------------------------------------------------------------------------------------
if (OPMODE > 0)
begin
if ((CON_WR == 1'b1) && ( CON_WRP1 == 1'b0 || CON_SPULSE ==1))
begin
n = to_int(CON_ADDR);
case (n)
0 :
begin
bfm_run = ((CON_DIN[0]) == 1'b1);
bfm_single = ((CON_DIN[1]) == 1'b1);
bfm_done = 0;
if ( bfm_run & ~bfm_single)
begin
stack[stkptr] = 0; // null return address
stkptr = stkptr+1;
end
//----------------------------------------------------------------------------------------
// Handle the external command interface
if (DEBUG >= 2 & bfm_run & ~bfm_single)
begin
$display("BFM: Starting script at %08x (%0d parameters)", cptr,npass);
end
if (DEBUG >= 2 & bfm_run & bfm_single)
begin
$display("BFM: Starting instruction at %08x", cptr);
end
if (bfm_run)
begin
if (npass > 0)
begin
// put the stored parameters on the stack
begin : xhdl_7
integer i;
for(i = 0; i <= npass - 1; i = i + 1)
begin
stack[stkptr] = passed[i];
stkptr = stkptr + 1;
end
end
npass = 0;
end
wptr_cstk = 0;
rptr_cstk = 0;
end
end
1 :
begin
cptr = CON_DIN;
end
2 :
begin
passed[npass] = CON_DIN;
npass = npass + 1;
end
default :
begin
vectors[n] = to_int_signed(CON_DIN);
end
endcase
end
if ((CON_RD == 1'b1) && ( CON_RDP1 == 1'b0 || CON_SPULSE ==1))
begin
n = to_int(CON_ADDR);
case (n)
0 :
begin
CON_DOUT <= {32{1'b0}} ;
CON_DOUT[2] <= bfm_run ;
CON_DOUT[3] <= (ERRORS > 0) ;
end
1 :
begin
CON_DOUT <= cptr;
end
2 :
begin
CON_DOUT <= return_value;
npass = 0;
end
3 :
begin
if (wptr_cstk > rptr_cstk)
begin
CON_DOUT <= returnstk[rptr_cstk] ;
rptr_cstk = rptr_cstk + 1;
end
else
begin
$display("BFM: Overread Control return stack");
CON_DOUT <= {32{1'b0}} ;
end
end
default :
begin
CON_DOUT <= {32{1'b0}} ;
end
endcase
end
end
//----------------------------------------------------------------------------------------
// Decode the Commands and schedule activities
// Command Processing no requirement on HREADY
instruct_cycles = instruct_cycles + 1;
instructions_timer = instructions_timer + 1;
zerocycle = 1;
while (zerocycle)
begin
zerocycle = 0;
if (~cmd_active & bfm_run)
begin
for (i=0;i<=7;i=i+1) command[i]=0;
command0 = vectors[cptr];
cmd_size = command0[1:0];
cmd_cmd = command0[7:0];
cmd_scmd = command0[15:8];
cmd_lineno = command0[31:16];
timer = command_timeout;
instuct_count = instuct_count + 1;
command_length = 1;
storeaddr = -1;
count_xrate = 0;
if (DEBUG>=5) $display( "BFM: Instruction %0d Line Number %0d Command %0d", cptr, cmd_lineno, cmd_cmd);
if (log_bfm)
begin
$fdisplay(flog,"%05d BF %4d %4d %3d", $time, cptr, cmd_lineno, cmd_cmd);
end
if (cmd_cmd >= 100)
begin
cmd_cmdx4 = cmd_cmd;
end
else
begin
cmd_cmdx4 = 4 * (cmd_cmd / 4);
end
if (cmd_cmd != C_CHKT)
begin
instruct_cycles = 0;
end
// Move command from vectors to stack switching parameters if necessary
case (cmd_cmdx4)
C_PRINT, C_HEAD, C_FILEN, C_LOGF : n = 8;
C_WRTM, C_RDMC : n = 4 + vectors[cptr + 1];
C_CALLP : n = 3 + vectors[cptr + 2];
C_CALL : n = 3;
C_TABLE : n = 2 + vectors[cptr + 1];
C_CALC : n = 3 + vectors[cptr + 2];
C_ECHO : n = 2 + vectors[cptr + 1];
C_EXTWM : n = 3 + vectors[cptr + 1];
default : n = 8;
endcase
if (n > 0)
begin
begin : xhdl_7aa
integer i;
for(i = 0; i <= n - 1; i = i + 1)
begin
if (i >= 1 & i <= 8)
begin
command[i] = get_para_value(((command0[7 + i]) == 1'b1), vectors[cptr + i]);
end
else
begin
command[i] = vectors[cptr + i];
end
commandLV[i] = to_slv32(command[i]);
end
end
end
case (cmd_cmdx4)
C_FAIL :
begin
$display("BFM Compiler reported an error (FAILURE)");
ERRORS = ERRORS + 1;
$stop;
end
C_CONPU :
begin
command_length = 2;
zerocycle = 1;
returnstk[wptr_cstk] = command[1];
wptr_cstk = wptr_cstk + 1;
if (DEBUG>=2) $display( "BFM:%0d:conifpush %0d", cmd_lineno,command[1]);
end
C_RESET :
begin
command_length = 2;
HRESETN_P0 <= 1'b0 ;
reset_pulse = command[1];
if (DEBUG>=2) $display( "BFM:%0d:RESET %0d", cmd_lineno,reset_pulse);
end
C_CLKS :
begin
command_length = 2;
HCLK_STOP <= commandLV[1][0] ;
if (DEBUG>=2) $display( "BFM:%0d:STOPCLK %0d ", cmd_lineno, commandLV[1][0]);
end
C_MODE :
begin
command_length = 2;
bfm_mode = command[1];
if (DEBUG>=2) $display( "BFM:%0d:mode %0d (No effect in this version)", cmd_lineno, bfm_mode);
end
C_SETUP :
begin
zerocycle = 1;
command_length = 4;
n = command[1];
x = command[2];
y = command[3];
if (DEBUG>=2) $display( "BFM:%0d:setup %0d %0d %0d ", cmd_lineno, n, x, y);
// Main Command Processing
case (n)
1 :
begin
command_length = 4;
su_xsize = x;
su_xainc = y;
if (DEBUG>=2) $display( "BFM:%0d:Setup- Memory Cycle Transfer Size %0s %0d", cmd_lineno, to_char(su_xsize), su_xainc);
end
2 :
begin
command_length = 3;
su_flush = to_boolean(x);
if (DEBUG>=2) $display( "BFM:%0d:Setup- Automatic Flush %0d", cmd_lineno, su_flush);
end
3 :
begin
command_length = 3;
su_xrate = x;
if (DEBUG>=2) $display( "BFM:%0d:Setup- XRATE %0d", cmd_lineno, su_xrate);
end
4 :
begin
command_length = 3;
su_noburst = x;
if (DEBUG>=2) $display( "BFM:%0d:Setup- Burst Mode %0d", cmd_lineno, su_noburst);
end
5 :
begin
command_length = 3;
su_align = x;
if (DEBUG >= 2) $display( "BFM:%0d:Setup- Alignment %0d", cmd_lineno, su_align);
if (su_align == 1 | su_align == 2)
begin
$display("BFM: Untested 8 or 16 Bit alignment selected (WARNING)");
end
end
6: begin
command_length = 3;
// ignore VHDL endsim command
end
7: begin
command_length = 3;
su_endsim = x;
if (DEBUG >= 2) $display( "BFM:%0d:Setup- End Sim Action %0d", cmd_lineno, su_endsim);
if ( su_endsim > 2)
begin
$display("BFM: Unexpected End Simulation value (WARNING)");
end
end
default :
begin
$display("BFM Unknown Setup Command (FAILURE)");
end
endcase
end
C_DRVX :
begin
zerocycle = 1;
command_length = 2;
DRIVEX_ADD <= ((commandLV[1][0]) == 1'b1) ;
DRIVEX_DAT <= ((commandLV[1][1]) == 1'b1) ;
DRIVEX_RST <= ((commandLV[1][2]) == 1'b1) ;
DRIVEX_CLK <= ((commandLV[1][3]) == 1'b1) ;
if (DEBUG >= 2) $display( "BFM:%0d:drivex %0d ", cmd_lineno,command[1]);
end
C_ERROR :
begin
zerocycle = 1;
command_length = 3;
if (DEBUG>=2) $display( "BFM:%0d:error %0d %0d (No effect in this version)", cmd_lineno, command[1], command[2]);
end
C_PROT :
begin
zerocycle = 1;
command_length = 2;
ahb_prot = commandLV[1][3:0];
if (DEBUG>=2) $display( "BFM:%0d:prot %0d ", cmd_lineno, ahb_prot);
end
C_LOCK :
begin
zerocycle = 1;
command_length = 2;
ahb_lock = commandLV[1][0];
if (DEBUG>=2) $display( "BFM:%0d:lock %0d ", cmd_lineno, ahb_lock);
end
C_BURST :
begin
zerocycle = 1;
command_length = 2;
ahb_burst = commandLV[1][2:0];
if (DEBUG>=2) $display( "BFM:%0d:burst %0d ", cmd_lineno, ahb_burst);
end
C_WAIT :
begin
command_length = 2;
wait_counter = command[1];
if (DEBUG>=2) $display( "BFM:%0d:wait %0d starting at %0d ns", cmd_lineno, wait_counter,$time);
do_case = 1;
end
C_WAITUS :
begin
command_length = 2;
wait_time = command[1] * 1000 + ($time / 1);
if (DEBUG>=2) $display( "BFM:%0d:waitus %0d starting at %0d ns", cmd_lineno, command[1],$time);
do_case = 1;
end
C_WAITNS :
begin
command_length = 2;
wait_time = command[1] * 1 + ($time / 1);
if (DEBUG>=2) $display( "BFM:%0d:waitns %0d starting at %0d ns", cmd_lineno, command[1],$time);
do_case = 1;
end
C_CHKT :
begin
command_length = 3;
if (DEBUG>=2) $display( "BFM:%0d:checktime %0d %0d at %0d ns", cmd_lineno, command[1], command[2],$time);
do_case = 1;
end
C_STTIM :
begin
zerocycle = 1;
command_length = 1;
instructions_timer = 1;
if (DEBUG>=2) $display("BFM:%0d:starttimer at %0d ns", cmd_lineno,$time);
end
C_CKTIM :
begin
command_length = 3;
if (DEBUG>=2) $display("BFM:%0d:checktimer %0d %0d at %0d ns ", cmd_lineno, command[1], command[2],$time);
do_case = 1;
end
C_NOP :
begin
command_length = 1;
if (DEBUG>=2) $display( "BFM:%0d:nop", cmd_lineno);
end
C_WRITE :
begin
command_length = 4;
command_size = xfer_size(cmd_size, su_xsize);
command_address = to_slv32(command[1] + command[2]);
command_data = commandLV[3];
if (DEBUG>=2) $display( "BFM:%0d:write %c %08x %08x at %0d ns", cmd_lineno, to_char(cmd_size), command_address, command_data,$time);
do_write = 1;
end
C_AHBC :
begin
command_length = 5;
command_size = xfer_size(cmd_size, su_xsize);
command_address = to_slv32(command[1] + command[2]);
command_data = commandLV[3];
ahbc_hwrite = commandLV[4][0];
ahbc_htrans = commandLV[4][5:4];
ahbc_burst = commandLV[4][10:8];
ahbc_lock = commandLV[4][12];
ahbc_prot = commandLV[4][19:16];
if (DEBUG>=2) $display( "BFM:%0d:idle %c %08x %08x %08x at %0d ns",cmd_lineno, to_char(cmd_size),
command_address,command_data, commandLV[4],$time);
do_idle = 1;
end
C_READ :
begin
command_length = 3;
command_size = xfer_size(cmd_size, su_xsize);
command_address = to_slv32(command[1] + command[2]);
command_data = {32{1'b0}};
command_mask = {32{1'b0}};
if (DEBUG>=2) $display("BFM:%0d:read %c %08x at %0d ns", cmd_lineno, to_char(cmd_size), command_address,$time);
do_read = 1;
end
C_READS :
begin
command_length = 4;
command_size = xfer_size(cmd_size, su_xsize);
command_address = to_slv32(command[1] + command[2]);
command_data = {32{1'b0}};
command_mask = {32{1'b0}};
storeaddr = get_storeaddr(vectors[cptr + 3],stkptr); // take pointer from vectors
if (DEBUG>=2) $display( "BFM:%0d:readstore %c %08x @%0d at %0d ns ",
cmd_lineno, to_char(cmd_size), command_address, storeaddr,$time);
do_read = 1;
do_flush = 1;
end
C_RDCHK :
begin
command_length = 4;
command_size = xfer_size(cmd_size, su_xsize);
command_address = to_slv32(command[1] + command[2]);
command_data = commandLV[3];
command_mask = {32{1'b1}};
if (DEBUG>=2) $display( "BFM:%0d:readcheck %c %08x %08x at %0d ns", cmd_lineno, to_char(cmd_size), command_address, command_data,$time);
do_read = 1;
end
C_RDMSK :
begin
command_length = 5;
command_size = xfer_size(cmd_size, su_xsize);
command_address = to_slv32(command[1] + command[2]);
command_data = commandLV[3];
command_mask = commandLV[4];
if (DEBUG>=2) $display( "BFM:%0d:readmask %c %08x %08x %08x at %0d ns", cmd_lineno, to_char(cmd_size), command_address, command_data, command_mask,$time);
do_read = 1;
end
C_POLL :
begin
command_length = 4;
command_size = xfer_size(cmd_size, su_xsize);
command_address = to_slv32(command[1] + command[2]);
command_data = commandLV[3];
command_mask = {32{1'b1}};
if (DEBUG>=2) $display( "BFM:%0d:poll %c %08x %08x at %0d ns", cmd_lineno, to_char(cmd_size), command_address, command_data,$time);
cmd_active = 1;
do_poll = 1;
do_poll = 1;
end
C_POLLM :
begin
command_length = 5;
command_size = xfer_size(cmd_size, su_xsize);
command_address = to_slv32(command[1] + command[2]);
command_data = commandLV[3];
command_mask = commandLV[4];
if (DEBUG>=2) $display( "BFM:%0d:pollmask %c %08x %08x %08x at %0d ns", cmd_lineno, to_char(cmd_size), command_address, command_data, command_mask,$time);
do_poll = 1;
end
C_POLLB :
begin
command_length = 5;
command_size = xfer_size(cmd_size, su_xsize);
command_address = to_slv32(command[1] + command[2]);
command_data = {32{1'b0}};
command_mask = {32{1'b0}};
bitn = command[3];
command_mask[bitn] = 1'b1;
command_data[bitn] = commandLV[4][0];
if (DEBUG>=2) $display( "BFM:%0d:pollbit %c %08x %0d %0d at %0d ns", cmd_lineno, to_char(cmd_size), command_address, bitn, command_data[bitn],$time);
do_poll = 1;
end
C_WRTM :
begin
burst_length = command[1];
command_length = 4 + burst_length;
command_size = xfer_size(cmd_size, su_xsize);
command_address = to_slv32(command[2] + command[3]);
burst_count = 0;
burst_addrinc = address_increment(cmd_size, su_xainc);
begin : xhdl_8
integer i;
for(i = 0; i <= burst_length - 1; i = i + 1)
begin
burst_data[i] = command[i + 4];
end
end
if (DEBUG>=2) $display( "BFM:%0d:writemultiple %c %08x %08x ... at %0d ns", cmd_lineno, to_char(cmd_size), command_address, burst_data[0],$time);
do_bwrite = 1;
end
C_FILL :
begin
burst_length = command[3];
command_length = 6;
command_size = xfer_size(cmd_size, su_xsize);
command_address = to_slv32(command[1] + command[2]);
burst_count = 0;
burst_addrinc = address_increment(cmd_size, su_xainc);
data_start = command[4];
data_inc = command[5];
begin : xhdl_9
integer i;
for(i = 0; i <= burst_length - 1; i = i + 1)
begin
burst_data[i] = data_start;
data_start = data_start + data_inc;
end
end
if (DEBUG>=2) $display( "BFM:%0d:fill %c %08x %0d %0d %0d at %0d ns", cmd_lineno, to_char(cmd_size), command_address, burst_length, command[4], command[4],$time);
do_bwrite = 1;
end
C_WRTT :
begin
burst_length = command[4];
command_length = 5;
command_size = xfer_size(cmd_size, su_xsize);
command_address = to_slv32(command[1] + command[2]);
burst_count = 0;
burst_addrinc = address_increment(cmd_size, su_xainc);
tableid = command[3];
begin : xhdl_10
integer i;
for(i = 0; i <= burst_length - 1; i = i + 1)
begin
burst_data[i] = vectors[2 + tableid + i];
end
end
if (DEBUG>=2) $display( "BFM:%0d:writetable %c %08x %0d %0d at %0d ns ", cmd_lineno, to_char(cmd_size), command_address, tableid, burst_length,$time);
do_bwrite = 1;
end
C_WRTA :
begin
burst_length = command[4];
command_length = 5;
command_size = xfer_size(cmd_size, su_xsize);
command_address = to_slv32(command[1] + command[2]);
burst_count = 0;
burst_addrinc = address_increment(cmd_size, su_xainc);
setvar = get_storeaddr(vectors[cptr + 3],stkptr);
begin : xhdl_10a
integer i;
for(i = 0; i <= burst_length - 1; i = i + 1)
begin
burst_data[i] = stack[setvar + i];
end
end
if (DEBUG>=2) $display( "BFM:%0d:writearray %c %08x %0d %0d at %0d ns ",
cmd_lineno, to_char(cmd_size), command_address,setvar, burst_length,$time);
do_bwrite = 1;
end
C_RDM :
begin
burst_length = command[3]; // note this is a fixed length instruction
command_length = 4;
command_size = xfer_size(cmd_size, su_xsize);
command_address = to_slv32(command[1] + command[2]);
command_mask = {32{1'b0}};
burst_count = 0;
burst_addrinc = address_increment(cmd_size, su_xainc);
command_mask = {32{1'b0}};
if (DEBUG>=2) $display( "BFM:%0d:readmult %c %08x %0d at %0d ns", cmd_lineno, to_char(cmd_size), command_address, burst_length,$time);
do_bread = 1;
end
C_RDMC :
begin
burst_length = command[1];
command_length = 4 + burst_length;
command_size = xfer_size(cmd_size, su_xsize);
command_address = to_slv32(command[2] + command[3]);
command_mask = {32{1'b1}};
burst_count = 0;
burst_addrinc = address_increment(cmd_size, su_xainc);
command_mask = {32{1'b1}};
begin : xhdl_11
integer i;
for(i = 0; i <= burst_length - 1; i = i + 1)
begin
burst_data[i] = command[i + 4];
end
end
if (DEBUG>=2) $display( "BFM:%0d:readmultchk %c %08x %08x ... at %0d ns", cmd_lineno, to_char(cmd_size), command_address, burst_data[0],$time);
do_bread = 1;
end
C_READF :
begin
burst_length = command[3];
command_length = 6;
command_size = xfer_size(cmd_size, su_xsize);
command_address = to_slv32(command[1] + command[2]);
command_mask = {32{1'b1}};
burst_count = 0;
burst_addrinc = address_increment(cmd_size, su_xainc);
data_start = command[4];
data_inc = command[5];
begin : xhdl_12
integer i;
for(i = 0; i <= burst_length - 1; i = i + 1)
begin
burst_data[i] = data_start;
data_start = data_start + data_inc;
end
end
if (DEBUG>=2) $display( "BFM:%0d:fillcheck %c %08x %0d %0d %0d at %0d ns", cmd_lineno, to_char(cmd_size), command_address, burst_length, command[4], command[5],$time);
do_bread = 1;
end
C_READT :
begin
burst_length = command[4];
command_length = 5;
command_size = xfer_size(cmd_size, su_xsize);
command_address = to_slv32(command[1] + command[2]);
command_mask = {32{1'b1}};
burst_count = 0;
burst_addrinc = address_increment(cmd_size, su_xainc);
tableid = command[3];
begin : xhdl_13
integer i;
for(i = 0; i <= burst_length - 1; i = i + 1)
begin
burst_data[i] = vectors[tableid + 2 + i];
end
end
if (DEBUG>=2) $display( "BFM:%0d:readtable %c %08x %0d %0d at %0d ns", cmd_lineno, to_char(cmd_size), command_address, tableid, burst_length,$time);
do_bread = 1;
end
C_READA :
begin
burst_length = command[4];
command_length = 5;
command_size = xfer_size(cmd_size, su_xsize);
command_address = to_slv32(command[1] + command[2]);
command_mask = {32{1'b1}};
burst_count = 0;
burst_addrinc = address_increment(cmd_size, su_xainc);
setvar = get_storeaddr(vectors[cptr + 3],stkptr);
begin : xhdl_13s
integer i;
for(i = 0; i <= burst_length - 1; i = i + 1)
begin
burst_data[i] = stack[setvar + i];
end
end
if (DEBUG>=2) $display( "BFM:%0d:readtable %c %08x %0d %0d at %0d ns",
cmd_lineno, to_char(cmd_size), command_address, setvar, burst_length,$time);
do_bread = 1;
end
C_MEMT :
begin
command_length = 7;
do_case = 1;
mt_state = init;
end
C_MEMT2 :
begin
command_length = 7;
do_case = 1;
mt_state = init;
end
C_FIQ :
begin
command_length = 1;
int_vector = 0;
if (DEBUG>=2) $display( "BFM:%0d:waitfiq at %0d ns ", cmd_lineno,$time);
do_case = 1;
end
C_IRQ :
begin
command_length = 1;
int_vector = 1;
if (DEBUG>=2) $display( "BFM:%0d:waitirq at %0d ns ", cmd_lineno,$time);
do_case = 1;
end
C_INTREQ :
begin
command_length = 2;
int_vector = command[1];
if (DEBUG>=2) $display( "BFM:%0d:waitint %0d at %0d ns", cmd_lineno, int_vector,$time);
do_case = 1;
end
C_IOWR :
begin
command_length = 2;
command_data = commandLV[1];
GPOUT_P0 <= command_data ;
GPIOWR_P0 <= 1'b1 ;
if (DEBUG>=2) $display( "BFM:%0d:iowrite %08x at %0d ns ", cmd_lineno, command_data,$time);
end
C_IORD :
begin
command_length = 2;
command_data = {32{1'b0}};
command_mask = {32{1'b0}};
storeaddr = get_storeaddr(vectors[cptr + 1],stkptr); // take pointer from vectors
if (DEBUG>=2) $display( "BFM:%0d:ioread @%0d at %0d ns", cmd_lineno, storeaddr,$time);
GPIORD_P0 <= 1'b1 ;
do_case = 1;
do_flush = 1;
do_io = 1;
end
C_IOCHK :
begin
command_length = 2;
command_data = commandLV[1];
command_mask = {32{1'b1}};
GPIORD_P0 <= 1'b1 ;
if (DEBUG>=2) $display( "BFM:%0d:iocheck %08x at %0d ns ", cmd_lineno, command_data,$time);
do_case = 1;
end
C_IOMSK :
begin
command_length = 3;
command_data = commandLV[1];
command_mask = commandLV[2];
if (DEBUG>=2) $display( "BFM:%0d:iomask %08x %08x at %0d ns", cmd_lineno, command_data, command_mask,$time);
GPIORD_P0 <= 1'b1 ;
do_case = 1;
end
C_IOTST :
begin
command_length = 2;
command_data = {32{1'b0}};
command_mask = {32{1'b0}};
bitn = command[1];
command_data[bitn] = command0[0];
command_mask[bitn] = 1'b1;
GPIORD_P0 <= 1'b1 ;
if (DEBUG>=2) $display( "BFM:%0d:iotest %0d %0d at %0d ns", cmd_lineno, bitn, command0[0],$time);
do_case = 1;
end
C_IOSET :
begin
command_length = 2;
bitn = command[1];
GPOUT_P0[bitn] <= 1'b1 ;
GPIOWR_P0 <= 1'b1 ;
if (DEBUG>=2) $display( "BFM:%0d:ioset %0d at %0d ns", cmd_lineno, bitn,$time);
end
C_IOCLR :
begin
command_length = 2;
bitn = command[1];
GPOUT_P0[bitn] <= 1'b0 ;
GPIOWR_P0 <= 1'b1 ;
if (DEBUG>=2) $display( "BFM:%0d:ioclr %0d at %0d ns", cmd_lineno, bitn,$time);
end
C_IOWAIT :
begin
command_length = 2;
command_data = {32{1'b0}};
command_mask = {32{1'b0}};
bitn = command[1];
command_data[bitn] = command0[0];
command_mask[bitn] = 1'b1;
if (DEBUG>=2) $display( "BFM:%0d:iowait %0d %0d at %0d ns ", cmd_lineno, bitn, command0[0],$time);
GPIORD_P0 <= 1'b1 ;
do_case = 1;
end
C_EXTW :
begin
command_length = 3;
command_address = commandLV[1];
command_data = commandLV[2];
if ( DEBUG >=2) $display("BFM:%0d:extwrite %08x %08x at %0d ns", cmd_lineno, command_address, command_data,$time);
do_case = 1;
end
C_EXTR :
begin
command_length = 3;
command_address = commandLV[1];
command_data = {32{1'b0}};
command_mask = {32{1'b0}};
storeaddr =get_storeaddr(vectors[cptr + 2],stkptr); // take pointer from vectors
EXTRD_P0 <= 1'b1 ;
if ( DEBUG >=2) $display("BFM:%0d:extread @%0d %08x at %0d ns ", cmd_lineno, storeaddr, command_address,$time);
do_case = 1;
do_flush = 1;
do_io = 1;
end
C_EXTWM :
begin
burst_length = command[1];
burst_address = command[2];
command_length = burst_length + 3;
begin : xhdl_14
integer i;
for(i = 0; i < burst_length ; i = i + 1)
begin
burst_data[i] = command[i + 3];
end
end
if (DEBUG >= 2) $display("BFM:%0d:extwrite %08x %0d Words at %0t ns", cmd_lineno,command_address, burst_length, $time);
burst_count = 0;
do_case = 1;
end
C_EXTRC :
begin
command_length = 3;
command_address = commandLV[1];
command_data = commandLV[2];
command_mask = {32{1'b1}};
cmd_active = 1;
EXTRD_P0 <= 1'b1 ;
if ( DEBUG >=2) $display("BFM:%0d:extcheck %08x %08x at %0d ns", cmd_lineno, command_address, command_data,$time);
do_case = 1;
end
C_EXTMSK :
begin
command_length = 4;
command_address = commandLV[1];
command_data = commandLV[2];
command_mask = commandLV[3];
EXTRD_P0 <= 1'b1 ;
if ( DEBUG >=2) $display("BFM:%0d:extmask %08x %08x %08x at %0d ns", cmd_lineno, command_address, command_data, command_mask,$time);
do_case = 1;
end
C_EXTWT :
begin
command_length = 1;
wait_counter = 1;
cmd_active = 1;
if ( DEBUG >=2) $display("BFM:%0d:extwait ", cmd_lineno);
do_case = 1;
end
C_LABEL :
begin
$display("LABEL instructions not allowed in vector files (FAILURE)");
end
C_TABLE :
begin
zerocycle = 1;
command_length = 2 + command[1];
if (DEBUG>=2) $display( "BFM:%0d:table %08x ... (length=%0d)", cmd_lineno, command[2], command_length - 2);
end
C_JMP :
begin
zerocycle = 1;
command_length = 2;
jump_address = command[1];
command_length = jump_address - cptr; // point at new address
if (DEBUG>=2) $display( "BFM:%0d:jump", cmd_lineno);
end
C_JMPZ :
begin
zerocycle = 1;
command_length = 3;
jump_address = command[1];
if (command[2] == 0)
begin
command_length = jump_address - cptr; // point at new address
end
if (DEBUG>=2) $display( "BFM:%0d:jumpz %08x", cmd_lineno, command[2]);
end
C_IF :
begin
zerocycle = 1;
command_length = 5;
jump_address = command[1];
newvalue = calculate(command[3], command[2], command[4], DEBUG);
if (newvalue == 0)
begin
command_length = jump_address + 2 - cptr; // point at new address
end
if (DEBUG>=2) $display("BFM:%0d:if %08x func %08x", cmd_lineno, command[2], command[4]);
end
C_IFNOT :
begin
zerocycle = 1;
command_length = 5;
jump_address = command[1];
newvalue = calculate(command[3], command[2], command[4], DEBUG);
if (newvalue != 0)
begin
command_length = jump_address + 2 - cptr; // point at new address
end
if (DEBUG>=2) $display("BFM:%0d:ifnot %08x func %08x", cmd_lineno, command[2], command[4]);
end
C_ELSE :
begin
zerocycle = 1;
command_length = 2;
jump_address = command[1];
command_length = jump_address + 2 - cptr; // point at new address
if (DEBUG>=2) $display("BFM:%0d:else ",cmd_lineno);
end
C_ENDIF :
begin
zerocycle = 1; // do nothing endif is pad instruction stream so +2 works
command_length = 2;
if (DEBUG>=2) $display("BFM:%0d:endif ",cmd_lineno);
end
C_WHILE :
begin
zerocycle = 1;
command_length = 5;
jump_address = command[1] + 2; // after endwhile
newvalue = calculate(command[3], command[2], command[4], DEBUG);
if (newvalue == 0)
begin
command_length = jump_address - cptr; // point at new address
end
if (DEBUG>=2) $display("BFM:%0d:while %08x func %08x", cmd_lineno, command[2], command[4]);
end
C_ENDWHILE :
begin
zerocycle = 1;
command_length = 2;
jump_address = command[1];
command_length = jump_address - cptr; // point at new address
if (DEBUG>=2) $display( "BFM:%0d:endwhile", cmd_lineno);
end
C_WHEN :
begin
zerocycle = 1;
command_length = 4;
jump_address = command[3];
if (command[1] != command[2])
begin
command_length = jump_address - cptr; // point at new address ie next when/endcase
end
else
begin
casedone[casedepth] = 1; // doing this branch
end
if (DEBUG>=2) $display( "BFM:%0d:when %08x=%08x %08x", cmd_lineno, command[1], command[2], command[3]);
end
C_DEFAULT :
begin
zerocycle = 1;
command_length = 4;
jump_address = command[3];
if (casedone[casedepth])
begin
// if already done then branch
command_length = jump_address - cptr; // point at new address ie next when/endcase
end
else
begin
casedone[casedepth] = 0; // doing this branch
end
if (DEBUG>=2) $display("BFM:%0d:default %08x=%08x %08x", cmd_lineno, command[1], command[2],command[3]);
end
C_CASE :
begin
zerocycle = 1;
command_length = 1;
casedepth = casedepth + 1;
casedone[casedepth] = 0;
if (DEBUG>=2) $display( "BFM:%0d:case", cmd_lineno);
end
C_ENDCASE :
begin
zerocycle = 1;
command_length = 1;
casedepth = casedepth - 1;
if (DEBUG>=2) $display("BFM:%0d:endcase", cmd_lineno);
end
C_JMPNZ :
begin
zerocycle = 1;
command_length = 3;
jump_address = command[1];
if (command[2] != 0)
begin
command_length = jump_address - cptr; // point at new address
end
if (DEBUG>=2) $display( "BFM:%0d:jumpnz %08x", cmd_lineno, command[2]);
end
C_CMP :
begin
zerocycle = 1;
command_length = 4;
command_data = commandLV[2];
command_mask = commandLV[3];
cmpvalue = (commandLV[1] ^ command_data) & command_mask;
if ( DEBUG >=2) $display("BFM:%0d:compare %08x==%08x Mask=%08x (RES=%08x) at %0d ns", cmd_lineno, command[1], command_data, command_mask, cmpvalue,$time);
if (cmpvalue != 0)
begin
ERRORS = ERRORS + 1;
$display("ERROR: compare failed %08x==%08x Mask=%08x (RES=%08x) ", command[1], command_data, command_mask, cmpvalue);
$display(" Stimulus file %0s Line No %0d", filenames[get_file(cmd_lineno, filemult)], get_line(cmd_lineno, filemult));
$display("BFM Data Compare Error (ERROR)");
$stop;
end
end
C_CMPR :
begin
zerocycle = 1;
command_length = 4;
command_data = commandLV[2];
command_mask = commandLV[3];
if (command[1] >= command[2] & command[1] <= command[3])
begin
cmpvalue = 1;
end
else
begin
cmpvalue = 0;
end
if ( DEBUG >=2) $display("BFM:%0d:cmprange %0d in %0d to %0d at %0d ns", cmd_lineno, command[1], command[2], command[3],$time);
if (cmpvalue == 0)
begin
ERRORS = ERRORS + 1;
$display("ERROR: cmprange failed %0d in %0d to %0d", command[1], command[2], command[3]);
$display(" Stimulus file %0s Line No %0d", filenames[get_file(cmd_lineno, filemult)], get_line(cmd_lineno, filemult));
$display("BFM Data Compare Error (ERROR)");
$stop;
end
end
C_INT :
begin
zerocycle = 1;
command_length = 2;
nparas = command[1];
stkptr = stkptr + nparas;
stack[stkptr] = 0;
if (DEBUG>=2) $display( "BFM:%0d:int %0d", cmd_lineno, command[1]);
end
C_CALL, C_CALLP :
begin
zerocycle = 1;
if (cmd_cmd == C_CALL)
begin
command_length = 2;
nparas = 0;
end
else
begin
nparas = command[2];
command_length = 3 + nparas;
end
call_address = command[1];
return_address = cptr + command_length;
command_length = call_address - cptr; // point at new address
stack[stkptr] = return_address;
stkptr = stkptr + 1;
if (nparas > 0)
begin
begin : xhdl_16
integer i;
for(i = 0; i <= nparas - 1; i = i + 1)
begin
stack[stkptr] = command[3 + i];
stkptr = stkptr + 1;
end
end
end
if (DEBUG >= 2 & cmd_cmd == C_CALL) $display("BFM:%0d:call %0d", cmd_lineno, call_address);
if (DEBUG >= 2 & cmd_cmd == C_CALLP) $display("BFM:%0d:call %0d %08x ...", cmd_lineno, call_address, command[3]);
end
C_RET :
begin
zerocycle = 1;
command_length = 2;
stkptr = stkptr - command[1]; // no of values pushed
return_address = 0;
if (stkptr > 0)
begin
stkptr = stkptr - 1;
return_address = stack[stkptr];
end
if (return_address == 0)
begin
bfm_done = 1;
do_flush = 1;
zerocycle = 0;
end
else
begin
command_length = return_address - cptr; // point at new address
end
if (DEBUG>=2) $display( "BFM:%0d:return", cmd_lineno);
end
C_RETV :
begin
zerocycle = 1;
command_length = 3;
stkptr = stkptr - command[1]; // no of values pushed
return_address = 0;
if (stkptr > 0)
begin
stkptr = stkptr - 1;
return_address = stack[stkptr];
end
return_value = command[2];
if (return_address == 0)
begin
bfm_done = 1;
do_flush = 1;
zerocycle = 0;
end
else
begin
command_length = return_address - cptr; // point at new address
end
if (DEBUG>=2) $display( "BFM:%0d:return %08x", cmd_lineno, return_value);
end
C_LOOP :
begin
zerocycle = 1;
command_length = 5;
setvar = get_storeaddr(vectors[cptr + 1],stkptr);
newvalue = command[2];
stack[setvar] = newvalue;
if (DEBUG >= 2) $display("BFM:%0d:loop %0d %0d %0d %0d ", cmd_lineno, setvar, command[2], command[3], command[4]);
end
C_LOOPE :
begin
zerocycle = 1;
command_length = 2;
lptr = command[1]; // points at the loop commands
// Get parameters from the loop command
begin : xhdl_19a
integer i;
for(i = 2; i <= 4; i = i + 1)
begin
Loopcmd[i] = get_para_value((to_slv32(vectors[lptr][7 + i]) == 1'b1), vectors[lptr + i]);
end
end
setvar = get_storeaddr(vectors[lptr + 1],stkptr);
n = Loopcmd[4];
j = Loopcmd[3];
//$display("OLD LOOP %0d INC %0d LIMIT %0d",stack(setvar)),n),j);
loopcounter = stack[setvar];
loopcounter = loopcounter + n;
stack[setvar] = loopcounter;
jump_address = lptr + 5;
if ((n >= 0 & loopcounter <= j) | (n < 0 & loopcounter >= j))
begin
command_length = jump_address - cptr; // point at new address
if ( DEBUG >=2) $display("BFM:%0d:endloop (Next Loop=%0d)", cmd_lineno, loopcounter);
end
else
begin
if ( DEBUG >=2) $display("BFM:%0d:endloop (Finished)", cmd_lineno);
end
end
C_TOUT :
begin
zerocycle = 1;
command_length = 2;
command_timeout = command[1];
if ( DEBUG >=2) $display("BFM:%0d:timeout %0d", cmd_lineno, command_timeout);
end
C_RAND :
begin
zerocycle = 1;
command_length = 2;
lastrandom = command[1];
if ( DEBUG >=2) $display("BFM:%0d:rand %0d",cmd_lineno,lastrandom);
end
C_PRINT :
begin
zerocycle = 1;
command_length = len_string(vectors[cptr+1]);
str = extract_string(cptr);
$display("BFM:%0s", str);
end
C_HEAD :
begin
zerocycle = 1;
command_length = len_string(vectors[cptr+1]);
str = extract_string(cptr);
$display("################################################################");
$display("BFM:%0s", str);
end
C_FILEN :
begin
zerocycle = 1;
characters = to_int(command0[15:8]);
command_length = (characters - 1) / 4 + 2;
end
C_DEBUG :
begin
zerocycle = 1;
command_length = 2;
if (DEBUGLEVEL >= 0 & DEBUGLEVEL <= 5)
begin
$display("BFM:%0d: DEBUG - ignored due to DEBUGLEVEL generic setting", cmd_lineno);
end
else
begin
DEBUG <= command[1] ;
$display("BFM:%0d: DEBUG %0d", cmd_lineno, command[1]);
end
end
C_HRESP :
begin
zerocycle = 0;
command_length = 2;
hresp_mode = command[1];
tmpstr[1] = NUL;
if (hresp_mode == 2)
begin
if (hresp_occured)
begin
tmpstr[1:9] = {"OCCURRED", NUL};
end
else
begin
$display("BFM: HRESP Did Not Occur When Expected (ERROR)");
ERRORS = ERRORS + 1;
$stop;
end
hresp_mode = 0;
end
hresp_occured = 0;
if (DEBUG >= 2) $display("BFM:%0d:hresp %0d %0s", cmd_lineno, hresp_mode, tmpstr);
end
C_STOP :
begin
zerocycle = 1;
command_length = 2;
if ( DEBUG >=2) $display("BFM:%0d:stop %0d", cmd_lineno, command[1]);
$display(" Stimulus file %0s Line No %0d", filenames[get_file(cmd_lineno, filemult)], get_line(cmd_lineno, filemult));
case (command[1])
0 :
begin
$display("BFM Script Stop Command (NOTE)");
end
1 :
begin
$display("BFM Script Stop Command (WARNING)");
//$stop;
end
3 :
begin
$display("BFM Script Stop Command (FAILURE)");
$stop;
end
default :
begin
$display("BFM Script Stop Command (ERROR)");
$stop;
end
endcase
end
C_QUIT :
begin
bfm_done = 1;
end
C_ECHO :
begin
zerocycle = 1;
if (DEBUG>=1) $display("BFM:%0d:echo at %0d ns", cmd_lineno,$time);
command_length = 2 + command[1];
$display("BFM Parameter values are");
begin : xhdl_21
integer i;
for(i = 0; i <= command_length - 3; i = i + 1)
begin
$display(" Para %0d=0x%08x (%0d)", i + 1, commandLV[2 + i], commandLV[2 + i]);
end
end
end
C_FLUSH :
begin
command_length = 2;
wait_counter = command[1];
if ( DEBUG >=2) $display("BFM:%0d:flush %0d at %0d ns", cmd_lineno, wait_counter,$time);
do_flush = 1;
do_case = 1;
end
C_SFAIL :
begin
zerocycle = 1;
ERRORS = ERRORS + 1;
if ( DEBUG >=2) $display("BFM:%0d:setfail", cmd_lineno);
$display("BFM: User Script detected ERROR (ERROR)");
$stop;
end
C_SET :
begin
zerocycle = 1;
command_length = 3;
setvar = get_storeaddr(vectors[cptr + 1],stkptr);
newvalue = command[2];
stack[setvar] = newvalue;
if (DEBUG >= 2) $display("BFM:%0d:set %0d= 0x%08x (%0d)", cmd_lineno, setvar, newvalue, newvalue);
end
C_CALC :
begin
zerocycle = 1;
command_length = command[2] + 3;
setvar = get_storeaddr(vectors[cptr + 1],stkptr);
newvalue = calculate(command[4], command[3], command[5], DEBUG);
i = 6;
while (i < command_length)
begin
newvalue = calculate(command[i], newvalue, command[i + 1], DEBUG);
i = i + 2;
end
stack[setvar] = newvalue;
if (DEBUG >= 2) $display("BFM:%0d:set %0d= 0x%08x (%0d)", cmd_lineno, setvar, newvalue, newvalue);
end
C_LOGF :
begin
zerocycle = 1;
if (logopen)
begin
$fflush(flog);
$fclose(flog);
end
command_length = len_string(vectors[cptr+1]);
logfile = extract_string(cptr);
$display("BFM:%0d:LOGFILE %0s", cmd_lineno, logfile);
flog = $fopen(logfile,"w");
logopen = 1;
end
C_LOGS :
begin
zerocycle = 1;
command_length = 2;
$display("BFM:%0d:LOGSTART %0d", cmd_lineno, command[1]);
if (logopen==0)
begin
$display("Logfile not defined, ignoring command (ERROR)");
end
else
begin
log_ahb = ((commandLV[1][0]) == 1'b1);
log_ext = ((commandLV[1][1]) == 1'b1);
log_gpio = ((commandLV[1][2]) == 1'b1);
log_bfm = ((commandLV[1][3]) == 1'b1);
end
end
C_LOGE :
begin
zerocycle = 1;
command_length = 1;
$display("BFM:%0d:LOGSTOP", cmd_lineno);
log_ahb = 0;
log_ext = 0;
log_gpio = 0;
log_bfm = 0;
end
C_VERS :
begin
zerocycle = 1;
command_length = 1;
$display("BFM:%0d:VERSION", cmd_lineno);
$display(" BFM Verilog Version %0s", BFM_VERSION);
$display(" BFM Date %0s", BFM_DATE);
// The two lines below will be autoupdated when file is commited to SubVersion
$display(" SVN Revision $Revision: 21608 $");
$display(" SVN Date $Date: 2013-12-02 16:03:36 -0800 (Mon, 02 Dec 2013) $");
$display(" Compiler Version %0d", bfmc_version);
$display(" Vectors Version %0d", vectors_version);
$display(" No of Vectors %0d", Nvectors);
if (logopen != NUL)
begin
$fdisplay(flog,"%05d VR %0s %0s %0d %0d %0d", $time,BFM_VERSION, BFM_DATE, bfmc_version, vectors_version, Nvectors);
end
end
default :
begin
$display("BFM: Instruction %0d Line Number %0d Command %0d", cptr, cmd_lineno, cmd_cmd);
$display(" Stimulus file %0s Line No %0d", filenames[get_file(cmd_lineno, filemult)], get_line(cmd_lineno, filemult));
$display("Instruction not yet implemented (ERROR)");
$stop;
end
endcase
end
// zero cycle was set indicating instruction does not require a clock!
if (zerocycle)
begin
cmd_active = 0;
cptr = cptr + command_length;
command_length = 0;
end
end
//----------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------------
// Data Checker, needs to happen before multi cycle command processing
DATA_MATCH_AHB = 0;
DATA_MATCH_EXT = 0;
DATA_MATCH_IO = 0;
if (READ_P1 == 1'b1)
begin
EXP = RDATA_P1 & MDATA_P1;
GOT = HRDATA & MDATA_P1;
DATA_MATCH_AHB = (EXP === GOT);
end
if (EXTRD_P1 == 1'b1)
begin
EXP = EIO_RDATA_P1 & EIO_MDATA_P1;
GOT = EXT_DIN & EIO_MDATA_P1;
DATA_MATCH_EXT = (EXP === GOT);
end
if (GPIORD_P0 == 1'b1)
begin
EXP = EIO_RDATA_P0 & EIO_MDATA_P0;
GOT = GP_IN & EIO_MDATA_P0;
DATA_MATCH_IO = (EXP === GOT);
end
//----------------------------------------------------------------------------------------------------------
piped_activity = do_read | do_write | do_bwrite | do_bread | do_poll | do_idle | do_io
| to_boolean(READ_P1 | READ_P0 | WRITE_P0 | WRITE_P1 | EXTRD_P0 | EXTRD_P1 | GPIORD_P0 );
if (do_case)
begin
case (cmd_cmdx4)
C_FLUSH :
begin
if (~piped_activity)
begin
//----------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------------
// Command Processing for multi cycle commands etc
if (wait_counter <= 1)
begin
do_case = 0;
end
else
begin
wait_counter = wait_counter - 1;
end
end
end
C_WAIT :
begin
if (wait_counter <= 1)
begin
do_case = 0;
end
else
begin
wait_counter = wait_counter - 1;
end
end
C_WAITNS, C_WAITUS :
begin
if ($time >= wait_time)
begin
do_case = 0;
end
end
C_IRQ, C_FIQ, C_INTREQ :
begin
if (int_vector == 256)
begin
int_active = (INTERRUPT != ZERO256);
end
else
begin
int_active = ((INTERRUPT[int_vector]) === 1'b1);
end
if (int_active)
begin
if (DEBUG>=2) $display( "BFM:Interrupt Wait Time %0d cycles", instruct_cycles);
do_case = 0;
end
end
C_EXTW :
begin
EXTADDR_P0 <= command_address ;
EXT_DOUT <= command_data ;
EXTWR_P0 <= 1'b1 ;
do_case = 0;
end
C_EXTWM :
begin
EXTADDR_P0 <= burst_address + burst_count ;
EXT_DOUT <= burst_data[burst_count] ;
EXTWR_P0 <= 1'b1 ;
burst_count = burst_count + 1;
if (burst_count >= burst_length)
begin
do_case = 0;
end
end
C_EXTR, C_EXTRC, C_EXTMSK :
begin
EXTADDR_P0 <= command_address ;
EIO_RDATA_P0 <= command_data ;
EIO_MDATA_P0 <= command_mask ;
EIO_LINENO_P0 <= cmd_lineno ;
EIO_RDCHK_P0 <= 1'b1 ;
if (EXTRD_P1 == 1'b1)
begin
// must wait until data on bus, cannot allow immediate write
do_case = 0;
end
end
C_EXTWT :
begin
if (EXT_WAIT == 1'b0 & wait_counter == 0)
begin
if (DEBUG>=2) $display( "BFM:Exteral Wait Time %0d cycles", instruct_cycles);
do_case = 0;
end
if (wait_counter >= 1)
begin
wait_counter = wait_counter - 1;
end
end
C_IOCHK, C_IOMSK, C_IOTST, C_IORD :
begin
EIO_RDCHK_P0 <= 1'b1 ;
EIO_RDATA_P0 <= command_data ;
EIO_MDATA_P0 <= command_mask ;
EIO_LINENO_P0 <= cmd_lineno ;
do_case = 0;
end
C_IOWAIT :
begin
EIO_RDATA_P0 <= command_data ;
EIO_MDATA_P0 <= command_mask ;
EIO_LINENO_P0 <= cmd_lineno ;
GPIORD_P0 <= 1'b1 ;
EIO_RDCHK_P0 <= 1'b0 ;
if (GPIORD_P0 == 1'b1 & DATA_MATCH_IO)
begin
GPIORD_P0 <= 1'b0 ;
do_case = 0;
if (DEBUG>=2) $display( "BFM:GP IO Wait Time %0d cycles", instruct_cycles);
end
end
C_MEMT , C_MEMT2 :
begin
case (mt_state)
//memtest resource addr size align cycles
idle : do_case = 0;
init : begin
mt_base = command[1] + command[2];
mt_size = command[3];
mt_align = command[4] % 65536;
mt_fill = ((commandLV[4][16]) == 1'b1);
mt_scan = ((commandLV[4][17]) == 1'b1);
mt_restart = ((commandLV[4][18]) == 1'b1);
mt_cycles = command[5];
mt_seed = command[6];
if (~mt_restart)
for (i=0;i<MAX_MEMTEST;i=i+1) mt_image[i] = 0;
mt_reads = 0;
mt_writes = 0;
mt_nops = 0;
mt_dual = 0;
mt_fillad = 0;
if (cmd_cmdx4 == C_MEMT2)
begin
// if two banks double size
mt_base = command[1];
mt_base2 = command[2] - mt_size;
mt_size = 2 * mt_size;
mt_dual = 1;
end
if (cmd_cmdx4 == C_MEMT)
begin
$display("BFM:%0d: memtest Started at %0d ns", cmd_lineno, $time);
$display("BFM: Address %08x Size %0d Cycles %5d", mt_base, mt_size, mt_cycles);
end
else
begin
$display("BFM:%0d: dual memtest Started at %0d ns", cmd_lineno, $time);
$display("BFM: Address %08x %08x Size %0d Cycles %5d", mt_base,mt_base2 + mt_size/2, mt_size/2, mt_cycles);
end
case (mt_align)
0 : begin end
1 : $display("BFM: Transfers are APB Byte aligned");
2 : $display("BFM: Transfers are APB Half Word aligned");
3 : $display("BFM: Transfers are APB Word aligned");
4 : $display("BFM: Byte Writes Suppressed");
default : $display("Illegal Align on memtest (FAILURE)");
endcase
if (mt_restart)
begin
$display("BFM: memtest restarted");
end
if (mt_fill)
begin
$display("BFM: Memtest Filling Memory");
mt_state = fill;
end
else if (mt_cycles > 0)
begin
$display("BFM: Memtest Random Read Writes");
mt_state = active;
end
else if (mt_scan)
begin
$display("BFM: Memtest Verifying Memory Content");
mt_state = scan;
end
else
begin
mt_state = done;
end
end
active, fill, scan :
begin
if (~(do_write | do_read))
begin
case (mt_state)
active :
begin
mt_seed = random(mt_seed);
mt_ad = mask_randomS(mt_seed, mt_size);
mt_seed = random(mt_seed);
mt_op = mask_randomS(mt_seed, 8);
end
fill :
begin
mt_ad = mt_fillad;
mt_op = 6;
end
scan :
begin
mt_ad = mt_fillad;
mt_op = 2;
end
default :
begin
end
endcase
case (mt_align)
0 :
begin
end
1 :
begin
// byte wide APB
mt_ad = 4 * (mt_ad / 4);
case (mt_op)
// full AHB operation
0, 4 :
begin
mt_op = mt_op; // all to op 0 and 4
end
1, 5 :
begin
mt_op = mt_op - 1;
end
2, 6 :
begin
mt_op = mt_op - 2;
end
default :
begin
end
endcase
end
2 :
begin
// half wide APB
mt_ad = 4 * (mt_ad / 4);
case (mt_op)
0, 4 :
begin
mt_op = mt_op + 1; // all to op 1 and 5
end
1, 5 :
begin
mt_op = mt_op;
end
2, 6 :
begin
mt_op = mt_op - 1;
end
default :
begin
end
endcase
end
3 :
begin
// word wide APB
mt_ad = 4 * (mt_ad / 4);
case (mt_op)
0, 4 :
begin
mt_op = mt_op + 2; // all to op 2 and 6
end
1, 5 :
begin
mt_op = mt_op + 1;
end
2, 6 :
begin
mt_op = mt_op;
end
default :
begin
end
endcase
end
4 :
begin
// Dont allow Byte writes
case (mt_op)
4 :
begin
mt_ad = 2 * (mt_ad / 2);
mt_op = 5; // stop a byte write, make a half write
end
default :
begin
end
endcase
end
default :
begin
end
endcase
if (mt_op >= 0 & mt_op <= 2)
begin
// do read
case (mt_op)
// see if valid data
0 :
begin
command_size = 3'b000;
mt_ad = mt_ad;
mt_readok = (mt_image[mt_ad + 0] >= 256);
end
1 :
begin
command_size = 3'b001;
mt_ad = 2 * (mt_ad / 2);
mt_readok = ((mt_image[mt_ad + 0] >= 256) & (mt_image[mt_ad + 1] >= 256));
end
2 :
begin
command_size = 3'b010;
mt_ad = 4 * (mt_ad / 4);
mt_readok = ((mt_image[mt_ad + 0] >= 256) & (mt_image[mt_ad + 1] >= 256) & (mt_image[mt_ad + 2] >= 256) & (mt_image[mt_ad + 3] >= 256));
end
default :
begin
end
endcase
// wait until previous cycle clears
if (mt_readok)
begin
// do a read
do_read = 1;
mt_reads = mt_reads + 1;
if (mt_dual == 1 & mt_ad >= mt_size / 2)
begin
command_address = mt_base2 + mt_ad;
end
else
begin
command_address = mt_base + mt_ad;
end
case (mt_op)
0 : begin
command_data = {ZEROLV[31:8], mt_image[mt_ad + 0][7:0]};
end
1 : begin
command_data = {ZEROLV[31:16], mt_image[mt_ad + 1][7:0], mt_image[mt_ad + 0][7:0]};
end
2 : begin
command_data = {mt_image[mt_ad + 3][7:0], mt_image[mt_ad + 2][7:0],
mt_image[mt_ad + 1][7:0], mt_image[mt_ad + 0][7:0]};
end
default : begin
command_data = ZEROLV[31:0];
end
endcase
command_mask = {32{1'b1}};
end
else
begin
//$display("Memtest read converted to write");
mt_op = mt_op + 4; // force a write if not written
// if a byte read converted to byte write and byte writes not allowed make a half word write!
if (mt_op == 4 & mt_align == 4)
begin
mt_op = 5;
end
end
end
if (mt_op >= 4 & mt_op <= 6)
begin
// do write
do_write = 1;
mt_writes = mt_writes + 1;
mt_seed = random(mt_seed);
command_data = mt_seed;
case (mt_op)
// update image
4 :
begin
command_size = 3'b000;
mt_ad = mt_ad;
mt_image[mt_ad + 0] = 256 + command_data[7:0];
end
5 :
begin
command_size = 3'b001;
mt_ad = 2 * (mt_ad / 2);
mt_image[mt_ad + 0] = 256 + command_data[7:0];
mt_image[mt_ad + 1] = 256 + command_data[15:8];
end
6 :
begin
command_size = 3'b010;
mt_ad = 4 * (mt_ad / 4);
mt_image[mt_ad + 0] = 256 + command_data[7:0];
mt_image[mt_ad + 1] = 256 + command_data[15:8];
mt_image[mt_ad + 2] = 256 + command_data[23:16];
mt_image[mt_ad + 3] = 256 + command_data[31:24];
end
default :
begin
end
endcase
if (mt_dual == 1 & mt_ad >= mt_size / 2)
begin
command_address = mt_base2 + mt_ad;
end
else
begin
command_address = mt_base + mt_ad;
end
end
if (mt_op == 3 | mt_op == 7)
begin
// insert one wait cycle
mt_nops = mt_nops + 1;
end
mt_fillad = mt_fillad + 4;
case (mt_state)
active :
begin
if (mt_cycles > 0)
begin
mt_cycles = mt_cycles - 1;
end
else if (mt_scan)
begin
mt_fillad = 0;
mt_state = scan;
$display("BFM: Memtest Verifying Memory Content");
end
else
begin
mt_state = done;
end
end
fill :
begin
if (mt_fillad >= mt_size)
begin
if (mt_cycles == 0)
begin
if (mt_scan)
begin
mt_fillad = 0;
mt_state = scan;
$display("BFM: Memtest Verifying Memory Content");
end
else
begin
mt_state = done;
end
end
else
begin
mt_state = active;
$display("BFM: Memtest Random Read Writes");
end
end
end
scan :
begin
if (mt_fillad >= mt_size)
begin
mt_state = done;
end
end
default :
begin
end
endcase
timer = command_timeout; // also reset the timer as we completed a cycle
end
end
done :
begin
if (~piped_activity)
begin
mt_state = idle;
$display("BFM: bfmtest complete Writes %0d Reads %0d Nops %0d", mt_writes, mt_reads, mt_nops);
end
end
endcase
end
default :
begin
end
endcase
end
//----------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------------
// AMBA Bus Cycles
//- this inserts AHB BUSY cycles
if (count_xrate == 0)
begin
insert_busy = 0;
count_xrate = su_xrate;
end
else
begin
count_xrate = count_xrate - 1;
insert_busy = 1;
end
if (HREADY == 1'b1)
begin
HTRANS_P0 <= 2'b00 ; // IDLE
HWRITE_P0 <= 1'b0 ;
// AMBA Cycles
WRITE_P0 <= 1'b0 ;
READ_P0 <= 1'b0 ;
POLL_P0 <= 1'b0 ;
//---------
if (WRITE_P0 == 1'b1 | READ_P0 == 1'b1)
begin
RDCHK_P0 <= 1'b0 ;
end
if (do_write & HREADY == 1'b1)
begin
HADDR_P0 <= command_address ;
HWRITE_P0 <= 1'b1 ;
HBURST_P0 <= ahb_burst ;
HTRANS_P0 <= 2'b10 ;
HMASTLOCK_P0 <= ahb_lock ;
HPROT_P0 <= ahb_prot ;
HSIZE_P0 <= command_size ;
WDATA_P0 <= align_data(command_size, command_address[1:0], command_data, su_align) ;
WRITE_P0 <= 1'b1 ;
LINENO_P0 <= cmd_lineno ;
do_write = 0;
end
if (do_read & HREADY == 1'b1)
begin
HADDR_P0 <= command_address ;
HWRITE_P0 <= 1'b0 ;
HBURST_P0 <= ahb_burst ;
HTRANS_P0 <= 2'b10 ;
HMASTLOCK_P0 <= ahb_lock ;
HPROT_P0 <= ahb_prot ;
HSIZE_P0 <= command_size ;
RDATA_P0 <= align_data(command_size, command_address[1:0], command_data, su_align) ;
MDATA_P0 <= align_mask(command_size, command_address[1:0], command_mask, su_align) ;
LINENO_P0 <= cmd_lineno ;
READ_P0 <= 1'b1 ;
RDCHK_P0 <= 1'b1 ;
do_read = 0;
end
if (do_idle & HREADY == 1'b1)
begin
HADDR_P0 <= command_address ;
HWRITE_P0 <= ahbc_hwrite ;
HBURST_P0 <= ahbc_burst ;
HTRANS_P0 <= ahbc_htrans ;
HMASTLOCK_P0 <= ahbc_lock ;
HPROT_P0 <= ahbc_prot ;
HSIZE_P0 <= command_size ;
WDATA_P0 <= align_data(command_size, command_address[1:0], command_data, su_align) ;
WRITE_P0 <= 1'b1 ; // use write pipe line to control timing
LINENO_P0 <= cmd_lineno ;
do_idle = 0;
end
if (do_poll & HREADY == 1'b1)
begin
//$display("POLL %08x %08x",RDATA_P0),MDATA_P0));
HADDR_P0 <= command_address ;
HWRITE_P0 <= 1'b0 ;
HBURST_P0 <= ahb_burst ;
HMASTLOCK_P0 <= ahb_lock ;
HPROT_P0 <= ahb_prot ;
HSIZE_P0 <= command_size ;
RDATA_P0 <= align_data(command_size, command_address[1:0], command_data, su_align) ;
MDATA_P0 <= align_mask(command_size, command_address[1:0], command_mask, su_align) ;
LINENO_P0 <= cmd_lineno ;
if (READ_P0 == 1'b1 | READ_P1 == 1'b1)
begin
HTRANS_P0 <= 2'b00 ; // No cycle, waiting to check data
end
else
begin
HTRANS_P0 <= 2'b10 ;
READ_P0 <= 1'b1 ;
POLL_P0 <= 1'b1 ;
end
if (POLL_P1 == 1'b1 & DATA_MATCH_AHB)
begin
do_poll = 0;
end
end
if (do_bwrite & HREADY == 1'b1)
begin
HADDR_P0 <= command_address ;
HWRITE_P0 <= 1'b1 ;
HBURST_P0 <= ahb_burst ;
HMASTLOCK_P0 <= ahb_lock ;
HPROT_P0 <= ahb_prot ;
HSIZE_P0 <= command_size ;
LINENO_P0 <= cmd_lineno ;
if (insert_busy)
begin
HTRANS_P0 <= 2'b01 ;
end
else
begin
WDATA_P0 <= align_data(command_size, command_address[1:0], to_slv32(burst_data[burst_count]), su_align) ;
WRITE_P0 <= 1'b1 ;
if (burst_count == 0 | cmd_size == 3 | bound1k(su_noburst, command_address) )
begin
HTRANS_P0 <= 2'b10 ;
end
else
begin
HTRANS_P0 <= 2'b11 ;
end
command_address = command_address + burst_addrinc;
burst_count = burst_count + 1;
if (burst_count == burst_length)
begin
do_bwrite = 0;
end
end
end
if (do_bread & HREADY == 1'b1)
begin
HADDR_P0 <= command_address ;
HWRITE_P0 <= 1'b0 ;
HBURST_P0 <= ahb_burst ;
HMASTLOCK_P0 <= ahb_lock ;
HPROT_P0 <= ahb_prot ;
HSIZE_P0 <= command_size ;
LINENO_P0 <= cmd_lineno ;
if (insert_busy)
begin
HTRANS_P0 <= 2'b01 ;
end
else
begin
RDATA_P0 <= align_data(command_size, command_address[1:0], to_slv32(burst_data[burst_count]), su_align) ;
MDATA_P0 <= align_mask(command_size, command_address[1:0], command_mask, su_align) ;
READ_P0 <= 1'b1 ;
RDCHK_P0 <= 1'b1 ;
if (burst_count == 0 | cmd_size == 3 | bound1k(su_noburst, command_address) )
begin
HTRANS_P0 <= 2'b10 ;
end
else
begin
HTRANS_P0 <= 2'b11 ;
end
command_address = command_address + burst_addrinc;
burst_count = burst_count + 1;
if (burst_count == burst_length)
begin
do_bread = 0;
end
end
end
end
//----------------------------------------------------------------------------------------------------------
if (HREADY == 1'b1)
begin
WRITE_P1 <= WRITE_P0 ;
READ_P1 <= READ_P0 ;
POLL_P1 <= POLL_P0 ;
RDCHK_P1 <= RDCHK_P0 ;
RDATA_P1 <= RDATA_P0 ;
MDATA_P1 <= MDATA_P0 ;
LINENO_P1 <= LINENO_P0 ;
HADDR_P1 <= HADDR_P0 ;
HSIZE_P1 <= HSIZE_P0 ;
end
EXTRD_P1 <= EXTRD_P0 ;
EXTADDR_P1 <= EXTADDR_P0 ;
//seperate data pipe to AHB!
EIO_RDCHK_P1 <= EIO_RDCHK_P0 ;
EIO_RDATA_P1 <= EIO_RDATA_P0 ;
EIO_MDATA_P1 <= EIO_MDATA_P0 ;
EIO_LINENO_P1 <= EIO_LINENO_P0 ;
if (HREADY == 1'b1)
begin
//----------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------------
// Write Data Pipeline and logger
if (WRITE_P0 == 1'b1)
begin
WDATA_P1 <= WDATA_P0 ;
end
else
begin
WDATA_P1 <= {32{1'b0}} ;
end
if (WRITE_P1 == 1'b1 & DEBUG >= 3)
begin
$display("BFM: Data Write %08x %08x", HADDR_P1, WDATA_P1);
end
if (log_ahb & WRITE_P1 == 1'b1)
begin
$fdisplay(flog,"%05d AW %c %08x %08x", $time,to_char(HSIZE_P1), HADDR_P1, WDATA_P1);
end
end
if (GPIOWR_P0 == 1'b1 & log_gpio)
begin
$fdisplay(flog,"%05d GW %08x ", $time,GPOUT_P0);
end
if (EXTWR_P0 == 1'b1 & log_ext)
begin
$fdisplay(flog,"%05d EW %08x %08x", $time,EXTADDR_P0, EXT_DOUT);
end
if (HREADY == 1'b1)
begin
if (READ_P1 == 1'b1)
begin
if (DEBUG >= 3)
begin
//----------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------------
// Read Data Pipeline, Checker and logger
// AHB Read Checks
if (MDATA_P1 == ZEROLV)
begin
$display("BFM: Data Read %08x %08x", HADDR_P1, HRDATA);
end
else
begin
$display("BFM: Data Read %08x %08x MASK:%08x", HADDR_P1, HRDATA, MDATA_P1);
end
end
if (log_ahb)
begin
$fdisplay(flog,"%05d AR %c %08x %08x", $time,to_char(HSIZE_P1), HADDR_P1, HRDATA);
end
if (storeaddr >= 0)
begin
stack[storeaddr] = to_int(align_read(HSIZE_P1, HADDR_P1[1:0], HRDATA,su_align));
end
if (RDCHK_P1 == 1'b1 & ~DATA_MATCH_AHB)
begin
ERRORS = ERRORS + 1;
$display("ERROR: AHB Data Read Comparison failed Addr:%08x Got:%08x EXP:%08x (MASK:%08x)", HADDR_P1, HRDATA, RDATA_P1, MDATA_P1);
$display(" Stimulus file %0s Line No %0d", filenames[get_file(LINENO_P1, filemult)], get_line(LINENO_P1, filemult));
$display("BFM Data Compare Error (ERROR)");
$stop;
if (log_ahb)
begin
$fdisplay(flog, "%05d ERROR Addr:%08x Got:%08x EXP:%08x (MASK:%08x)", $time,HADDR_P1, HRDATA, RDATA_P1, MDATA_P1);
end
end
end
end
if (GPIORD_P0 == 1'b1)
begin
if (DEBUG >= 3)
begin
// IO Port Checker
if (EIO_MDATA_P0 == ZEROLV)
begin
$display("BFM: GP IO Data Read %08x", GP_IN);
end
else
begin
$display("BFM: GP IO Data Read %08x MASK:%08x", GP_IN, EIO_MDATA_P0);
end
end
if (log_gpio)
begin
$fdisplay(flog,"%05d GR %08x ",$time, EIO_RDATA_P0);
end
if (storeaddr >= 0)
begin
stack[storeaddr] = GP_IN;
end
if (EIO_RDCHK_P0 == 1'b1 & ~DATA_MATCH_IO)
begin
ERRORS = ERRORS + 1;
$display("GPIO input not as expected Got:%08x EXP:%08x (MASK:%08x)", GP_IN, EIO_RDATA_P0, EIO_MDATA_P0);
$display(" Stimulus file %0s Line No %0d", filenames[get_file(EIO_LINENO_P0, filemult)], get_line(EIO_LINENO_P0, filemult));
$display("BFM GPIO Compare Error (ERROR)");
$stop;
if (log_gpio)
begin
$fdisplay(flog,"ERROR Got:%08x EXP:%08x (MASK:%08x)", GP_IN, EIO_RDATA_P0, EIO_MDATA_P0);
end
end
end
if (EXTRD_P1 == 1'b1)
begin
if (DEBUG >= 3)
begin
// Extention Read Checks
if (EIO_MDATA_P1 == ZEROLV)
begin
$display("BFM: Extention Data Read %08x %08x", EXTADDR_P1, EXT_DIN);
end
else
begin
$display("BFM: Extention Data Read %08x %08x MASK:%08x", EXTADDR_P1, EXT_DIN, EIO_MDATA_P1);
end
end
if (log_ext)
begin
$fdisplay(flog,"%05d ER %08x %08x", $time,EXTADDR_P1, EIO_RDATA_P1);
end
if (storeaddr >= 0)
begin
stack[storeaddr] = to_int(EXT_DIN);
end
if (EIO_RDCHK_P1 == 1'b1 & ~DATA_MATCH_EXT)
begin
ERRORS = ERRORS + 1;
$display("ERROR: Extention Data Read Comparison FAILED Got:%08x EXP:%08x (MASK:%08x)", EXT_DIN, EIO_RDATA_P1, EIO_MDATA_P1);
$display(" Stimulus file %0s Line No %0d", filenames[get_file(EIO_LINENO_P1, filemult)], get_line(EIO_LINENO_P1, filemult));
$display("BFM Extention Data Compare Error (ERROR)");
$stop;
if (log_ext)
begin
$fdisplay(flog,"ERROR Got:%08x EXP:%08x (MASK:%08x)", EXT_DIN, EIO_RDATA_P1, EIO_MDATA_P1);
end
end
end
//----------------------------------------------------------------------------------------------------------
// routines that require operation after AHB cycle completes
ahb_activity = do_read | do_write | do_bwrite | do_bread | do_poll | do_idle | to_boolean(READ_P0 | WRITE_P0 | EXTRD_P0 | GPIORD_P0) | (to_boolean((READ_P1 | WRITE_P1) & ~HREADY));
if (do_case)
begin
case (cmd_cmdx4)
C_CHKT :
begin
if (~ahb_activity)
begin
if (DEBUG >= 2) $display( "BFM:%0d:checktime was %0d cycles ", cmd_lineno, instruct_cycles);
if (instruct_cycles < command[1] | instruct_cycles > command[2])
begin
$display("BFM: ERROR checktime %0d %0d Actual %0d", command[1], command[2], instruct_cycles);
$display(" Stimulus file %0s Line No %0d", filenames[get_file(LINENO_P1, filemult)], get_line(LINENO_P1, filemult));
$display("BFM checktime failure (ERROR)");
ERRORS = ERRORS + 1;
$stop;
end
do_case = 0;
var_licycles = instruct_cycles;
end
end
C_CKTIM :
begin
if (~ahb_activity)
begin
instructions_timer = instructions_timer - 1; // need to allow for check instruction
if (DEBUG >= 2) $display( "BFM:%0d:checktimer was %0d cycles ", cmd_lineno, instructions_timer);
if (instructions_timer < command[1] | instructions_timer > command[2])
begin
$display("BFM: ERROR checktimer %0d %0d Actual %0d", command[1], command[2], instructions_timer);
$display(" Stimulus file %0s Line No %0d", filenames[get_file(LINENO_P1, filemult)], get_line(LINENO_P1, filemult));
$display("BFM checktimer failure (ERROR)");
ERRORS = ERRORS + 1;
$stop;
end
do_case = 0;
var_ltimer = instructions_timer;
end
end
default :
begin
end
endcase
end
//----------------------------------------------------------------------------------------------------------
if (bfm_run)
begin
//----------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------------
// Watchdog timer
if (timer > 0)
begin
timer = timer - 1;
end
else
begin
timer = command_timeout;
$display("BFM Command Timeout Occured");
$display(" Stimulus file %0s Line No %0d", filenames[get_file(LINENO_P1, filemult)], get_line(LINENO_P1, filemult));
if (~bfm_done) $display("BFM Command timeout occured (ERROR)");
if ( bfm_done) $display("BFM Completed and timeout occured (ERROR)");
$stop;
end
end
else
begin
timer = command_timeout;
end
if (ERRORS > 0)
begin
FAILED_P0 <= 1'b1 ;
end
if (do_case | do_read | do_write | do_bwrite | do_bread | do_poll | do_idle | ((do_flush | su_flush) & piped_activity))
begin
cmd_active = 1;
end
else
begin
do_flush = 0;
// See if command done, if so allow next command to be started
if (~bfm_done)
begin
cmd_active = 0;
end
cptr = cptr + command_length;
command_length = 0;
if (OPMODE > 0)
begin
if (bfm_single | bfm_done)
begin
bfm_run = 0;
cmd_active = 0;
end
end
end
if (FINISHED_P0 == 1'b0 & OPMODE == 0 & bfm_done & ~piped_activity)
begin
$display("###########################################################");
$display(" ");
//----------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------------
if (ERRORS == 0)
begin
$display("BFM Simulation Complete - %0d Instructions - NO ERRORS", instuct_count);
end
else
begin
$display("BFM Simulation Complete - %0d Instructions - %0d ERRORS OCCURED", instuct_count, ERRORS);
end
$display(" ");
$display("###########################################################");
$display(" ");
FINISHED_P0 <= 1'b1 ;
cmd_active = 1;
bfm_run = 0;
if (logopen)
begin
// close log file
$fflush(flog);
$fclose(flog);
end
if ( su_endsim==1 ) $stop;
if ( su_endsim==2 ) $finish;
end
CON_BUSY <= (bfm_run | piped_activity) ;
INSTR_OUT <= to_slv32(cptr) ;
end
end
assign #TPD GP_OUT = GPOUT_P0 ;
assign #TPD EXT_WR = EXTWR_P0 ;
assign #TPD EXT_RD = EXTRD_P0 ;
assign #TPD EXT_ADDR = EXTADDR_P0 ;
assign #TPD EXT_DATA = (EXTWR_P0 == 1'b1) ? EXT_DOUT : {32{1'bz}} ;
assign EXT_DIN = EXT_DATA ;
always @(HADDR_P0)
begin
begin : xhdl_29
integer i;
for(i = 0; i <= 15; i = i + 1)
begin
HSEL_P0[i] <= (HADDR_P0[31:28] == i) ;
end
end
end
assign HCLK = (DRIVEX_CLK) ? 1'bx : (SYSCLK | HCLK_STOP) ;
assign PCLK = (DRIVEX_CLK) ? 1'bx : (SYSCLK | HCLK_STOP) ;
assign #TPD HRESETN = (DRIVEX_RST) ? 1'bx : HRESETN_P0 ;
assign #TPD HADDR = (DRIVEX_ADD) ? {32{1'bx}} : HADDR_P0 ;
assign #TPD HWDATA = (DRIVEX_DAT) ? {32{1'bx}} : WDATA_P1 ;
assign #TPD HBURST = (DRIVEX_ADD) ? {3{1'bx}} : HBURST_P0 ;
assign #TPD HMASTLOCK = (DRIVEX_ADD) ? 1'bx : HMASTLOCK_P0 ;
assign #TPD HPROT = (DRIVEX_ADD) ? {4{1'bx}} : HPROT_P0 ;
assign #TPD HSIZE = (DRIVEX_ADD) ? {3{1'bx}} : HSIZE_P0 ;
assign #TPD HTRANS = (DRIVEX_ADD) ? {2{1'bx}} : HTRANS_P0 ;
assign #TPD HWRITE = (DRIVEX_ADD) ? 1'bx : HWRITE_P0 ;
assign #TPD HSEL = (DRIVEX_ADD) ? {16{1'bx}} : HSEL_P0 ;
assign #TPD CON_DATA = (CON_RDP1 == 1'b1) ? CON_DOUT : {32{1'bz}} ;
assign CON_DIN = CON_DATA ;
assign #TPD FINISHED = FINISHED_P0 ;
assign #TPD FAILED = FAILED_P0 ;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SEDFXBP_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__SEDFXBP_BEHAVIORAL_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_hdll__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hdll__sedfxbp (
Q ,
Q_N,
CLK,
D ,
DE ,
SCD,
SCE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire DE_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire mux_out ;
wire de_d ;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD_delayed, SCE_delayed );
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D_delayed, DE_delayed );
sky130_fd_sc_hdll__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( awake && ( SCE_delayed === 1'b0 ) && ( DE_delayed === 1'b1 ) );
assign cond2 = ( awake && ( SCE_delayed === 1'b1 ) );
assign cond3 = ( awake && ( DE_delayed === 1'b1 ) && ( D_delayed !== SCD_delayed ) );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SEDFXBP_BEHAVIORAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/13/2015 09:33:31 AM
// Design Name:
// Module Name: Components
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// module MicroToAngle(
// input wire [RC_SIGNAL_WIDTH-1:0] pos,
// output reg [RC_SIGNAL_WIDTH-1:0] out_pos
// );
// integer i;
// integer at5;
// always @(*) begin
// for(i = 0; i < 1000; i)
// end
module PositionMux(
input wire [1:0] ctrl,
input wire [RC_SIGNAL_WIDTH-1:0] sweep_pos,
input wire [PIN_POS_WIDTH-1:0] pin_pos,
input wire [RC_SIGNAL_WIDTH-1:0] ser_pos,
output reg [RC_SIGNAL_WIDTH-1:0] out_pos
);
parameter RC_SIGNAL_WIDTH = 11;
parameter PIN_POS_WIDTH = 10;
parameter BCD_WIDTH = 4;
parameter POSITION_FILE_WIDTH = 32;
parameter POSITION_WIDTH = 11;
parameter PWMS = 4;
wire valid;
wire [RC_SIGNAL_WIDTH-1:0] segment_pos;
Segment U0 (
.in(pin_pos),
.out(segment_pos),
.valid(valid)
);
always @(*) begin
case(ctrl)
0: out_pos = sweep_pos;
1: out_pos = (pin_pos << 1) | 1'b1;
2: out_pos = segment_pos;
3: out_pos = ser_pos;
default: out_pos = sweep_pos;
endcase
end
endmodule
module SweepPosition(
input wire clk200Hz,
input wire rst,
input wire [2:0] speed,
output reg [RC_SIGNAL_WIDTH-1:0] pos
);
parameter RC_SIGNAL_WIDTH = 11;
parameter PIN_POS_WIDTH = 10;
parameter BCD_WIDTH = 4;
parameter POSITION_FILE_WIDTH = 32;
parameter POSITION_WIDTH = 11;
parameter PWMS = 4;
reg dir;
/* Will sweep from 0 degrees to 180 degrees and back with 1000 degrees of precision.
* Will take 5 seconds to do one sweep.
*
*/
always @(posedge clk200Hz or posedge rst) begin
if (rst) begin
pos = 10'd0;
dir = 0;
end
else if(dir == 0) begin
pos = pos + (speed << 1);
// max of 1000 positions
if(pos >= 2000) begin
dir = 1;
end
end
else if(dir == 1) begin
pos = pos - (speed << 1);
// Check Position to determine
if (pos <= 0) begin
dir = 0;
end
end
end
endmodule
module AngleToPWM(
input wire [RC_SIGNAL_WIDTH-1:0] pos,
input wire clk1MHz,
input wire rst,
output reg pwm
);
parameter RC_SIGNAL_WIDTH = 11;
parameter PIN_POS_WIDTH = 10;
parameter BCD_WIDTH = 4;
parameter POSITION_FILE_WIDTH = 32;
parameter POSITION_WIDTH = 11;
parameter PWMS = 4;
parameter time_width = 20000; // 20 ms = 20000 us
parameter pos_time_min = 500; // 1 ms = 1000 us
parameter pos_time_max = 2500; // 2 ms = 2000 us
integer current_time;
reg [10:0] stored_pos;
reg [1:0] state;
always @(posedge clk1MHz or posedge rst) begin
if (rst) begin
pwm = 1'b1;
state = 3'b0;
current_time = 0;
stored_pos = 0;
end
else if(pos > 2500 || pos < 0) begin
pwm = 1'b1;
end
else begin
case(state)
// Set inital pulse
// Set pulse high for 1ms
0: begin
pwm = 1;
//if (current_time >= pos_time_min) begin
stored_pos = pos;
state = 3'h1;
//end
end
// Set Positive Angle portion of pulse
1: begin
pwm = 1;
if (current_time >= stored_pos) begin
state = 3'h2;
end
end
// Set Negative Angle portion of pulse
// Wait until 20ms is up!
2: begin
pwm = 0;
if (current_time >= time_width) begin
state = 3'h0;
current_time = 0;
end
end
endcase
current_time = current_time + 1;
end
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: riffa_wrapper_de2i.v
// Version: 1.00a
// Verilog Standard: Verilog-2001
// Description: Wrapper file for all riffa logic for Altera DE2I boards
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "trellis.vh"
`include "riffa.vh"
`include "altera.vh"
`include "ultrascale.vh"
`include "functions.vh"
`timescale 1ps / 1ps
module riffa_wrapper_de2i
#(// Number of RIFFA Channels
parameter C_NUM_CHNL = 1,
// Bit-Width from Quartus IP Generator
parameter C_PCI_DATA_WIDTH = 64,
parameter C_MAX_PAYLOAD_BYTES = 256,
parameter C_LOG_NUM_TAGS = 5,
parameter C_FPGA_ID = "DE2i")
(// Interface: Altera RX
input [C_PCI_DATA_WIDTH-1:0] RX_ST_DATA,
input [0:0] RX_ST_EOP,
input [0:0] RX_ST_SOP,
input [0:0] RX_ST_VALID,
output RX_ST_READY,
input [0:0] RX_ST_EMPTY,
// Interface: Altera TX
output [C_PCI_DATA_WIDTH-1:0] TX_ST_DATA,
output [0:0] TX_ST_VALID,
input TX_ST_READY,
output [0:0] TX_ST_EOP,
output [0:0] TX_ST_SOP,
output [0:0] TX_ST_EMPTY,
// Interface: Altera Config
input [`SIG_CFG_CTL_W-1:0] TL_CFG_CTL,
input [`SIG_CFG_ADD_W-1:0] TL_CFG_ADD,
input [`SIG_CFG_STS_W-1:0] TL_CFG_STS,
// Interface: Altera Flow Control
input [`SIG_KO_CPLH_W-1:0] KO_CPL_SPC_HEADER,
input [`SIG_KO_CPLD_W-1:0] KO_CPL_SPC_DATA,
// Interface: Altera Interrupt
input APP_MSI_ACK,
output APP_MSI_REQ,
// Interface: Altera CLK/RESET
input PLD_CLK,
input RESET_STATUS,
// RIFFA Interface Signals
output RST_OUT,
input [C_NUM_CHNL-1:0] CHNL_RX_CLK, // Channel read clock
output [C_NUM_CHNL-1:0] CHNL_RX, // Channel read receive signal
input [C_NUM_CHNL-1:0] CHNL_RX_ACK, // Channel read received signal
output [C_NUM_CHNL-1:0] CHNL_RX_LAST, // Channel last read
output [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_RX_LEN, // Channel read length
output [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_RX_OFF, // Channel read offset
output [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_RX_DATA, // Channel read data
output [C_NUM_CHNL-1:0] CHNL_RX_DATA_VALID, // Channel read data valid
input [C_NUM_CHNL-1:0] CHNL_RX_DATA_REN, // Channel read data has been recieved
input [C_NUM_CHNL-1:0] CHNL_TX_CLK, // Channel write clock
input [C_NUM_CHNL-1:0] CHNL_TX, // Channel write receive signal
output [C_NUM_CHNL-1:0] CHNL_TX_ACK, // Channel write acknowledgement signal
input [C_NUM_CHNL-1:0] CHNL_TX_LAST, // Channel last write
input [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_TX_OFF, // Channel write offset
input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_TX_DATA, // Channel write data
input [C_NUM_CHNL-1:0] CHNL_TX_DATA_VALID, // Channel write data valid
output [C_NUM_CHNL-1:0] CHNL_TX_DATA_REN); // Channel write data has been recieved
localparam C_FPGA_NAME = "REGT"; // This is not yet exposed in the driver
localparam C_MAX_READ_REQ_BYTES = C_MAX_PAYLOAD_BYTES * 2;
localparam C_VENDOR = "ALTERA";
localparam C_ALTERA_TX_READY_LATENCY = 2;
localparam C_KEEP_WIDTH = C_PCI_DATA_WIDTH / 32;
localparam C_PIPELINE_OUTPUT = 1;
localparam C_PIPELINE_INPUT = 1;
localparam C_DEPTH_PACKETS = 4;
wire clk;
wire rst_in;
wire done_txc_rst;
wire done_txr_rst;
wire done_rxr_rst;
wire done_rxc_rst;
// Interface: RXC Engine
wire [C_PCI_DATA_WIDTH-1:0] rxc_data;
wire rxc_data_valid;
wire rxc_data_start_flag;
wire [(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_word_enable;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_start_offset;
wire [`SIG_FBE_W-1:0] rxc_meta_fdwbe;
wire rxc_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_end_offset;
wire [`SIG_LBE_W-1:0] rxc_meta_ldwbe;
wire [`SIG_TAG_W-1:0] rxc_meta_tag;
wire [`SIG_LOWADDR_W-1:0] rxc_meta_addr;
wire [`SIG_TYPE_W-1:0] rxc_meta_type;
wire [`SIG_LEN_W-1:0] rxc_meta_length;
wire [`SIG_BYTECNT_W-1:0] rxc_meta_bytes_remaining;
wire [`SIG_CPLID_W-1:0] rxc_meta_completer_id;
wire rxc_meta_ep;
// Interface: RXR Engine
wire [C_PCI_DATA_WIDTH-1:0] rxr_data;
wire rxr_data_valid;
wire [(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_word_enable;
wire rxr_data_start_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_start_offset;
wire [`SIG_FBE_W-1:0] rxr_meta_fdwbe;
wire rxr_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_end_offset;
wire [`SIG_LBE_W-1:0] rxr_meta_ldwbe;
wire [`SIG_TC_W-1:0] rxr_meta_tc;
wire [`SIG_ATTR_W-1:0] rxr_meta_attr;
wire [`SIG_TAG_W-1:0] rxr_meta_tag;
wire [`SIG_TYPE_W-1:0] rxr_meta_type;
wire [`SIG_ADDR_W-1:0] rxr_meta_addr;
wire [`SIG_BARDECODE_W-1:0] rxr_meta_bar_decoded;
wire [`SIG_REQID_W-1:0] rxr_meta_requester_id;
wire [`SIG_LEN_W-1:0] rxr_meta_length;
wire rxr_meta_ep;
// interface: TXC Engine
wire txc_data_valid;
wire [C_PCI_DATA_WIDTH-1:0] txc_data;
wire txc_data_start_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_start_offset;
wire txc_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_end_offset;
wire txc_data_ready;
wire txc_meta_valid;
wire [`SIG_FBE_W-1:0] txc_meta_fdwbe;
wire [`SIG_LBE_W-1:0] txc_meta_ldwbe;
wire [`SIG_LOWADDR_W-1:0] txc_meta_addr;
wire [`SIG_TYPE_W-1:0] txc_meta_type;
wire [`SIG_LEN_W-1:0] txc_meta_length;
wire [`SIG_BYTECNT_W-1:0] txc_meta_byte_count;
wire [`SIG_TAG_W-1:0] txc_meta_tag;
wire [`SIG_REQID_W-1:0] txc_meta_requester_id;
wire [`SIG_TC_W-1:0] txc_meta_tc;
wire [`SIG_ATTR_W-1:0] txc_meta_attr;
wire txc_meta_ep;
wire txc_meta_ready;
wire txc_sent;
// Interface: TXR Engine
wire txr_data_valid;
wire [C_PCI_DATA_WIDTH-1:0] txr_data;
wire txr_data_start_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_start_offset;
wire txr_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_end_offset;
wire txr_data_ready;
wire txr_meta_valid;
wire [`SIG_FBE_W-1:0] txr_meta_fdwbe;
wire [`SIG_LBE_W-1:0] txr_meta_ldwbe;
wire [`SIG_ADDR_W-1:0] txr_meta_addr;
wire [`SIG_LEN_W-1:0] txr_meta_length;
wire [`SIG_TAG_W-1:0] txr_meta_tag;
wire [`SIG_TC_W-1:0] txr_meta_tc;
wire [`SIG_ATTR_W-1:0] txr_meta_attr;
wire [`SIG_TYPE_W-1:0] txr_meta_type;
wire txr_meta_ep;
wire txr_meta_ready;
wire txr_sent;
// Classic Interface Wires
wire rx_tlp_ready;
wire [C_PCI_DATA_WIDTH-1:0] rx_tlp;
wire rx_tlp_end_flag;
wire [`SIG_OFFSET_W-1:0] rx_tlp_end_offset;
wire rx_tlp_start_flag;
wire [`SIG_OFFSET_W-1:0] rx_tlp_start_offset;
wire rx_tlp_valid;
wire [`SIG_BARDECODE_W-1:0] rx_tlp_bar_decode;
wire tx_tlp_ready;
wire [C_PCI_DATA_WIDTH-1:0] tx_tlp;
wire tx_tlp_end_flag;
wire [`SIG_OFFSET_W-1:0] tx_tlp_end_offset;
wire tx_tlp_start_flag;
wire [`SIG_OFFSET_W-1:0] tx_tlp_start_offset;
wire tx_tlp_valid;
// Unconnected Wires (Used in ultrascale interface)
// Interface: RQ (TXC)
wire s_axis_rq_tlast_nc;
wire [C_PCI_DATA_WIDTH-1:0] s_axis_rq_tdata_nc;
wire [`SIG_RQ_TUSER_W-1:0] s_axis_rq_tuser_nc;
wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_rq_tkeep_nc;
wire s_axis_rq_tready_nc = 0;
wire s_axis_rq_tvalid_nc;
// Interface: RC (RXC)
wire [C_PCI_DATA_WIDTH-1:0] m_axis_rc_tdata_nc = 0;
wire [`SIG_RC_TUSER_W-1:0] m_axis_rc_tuser_nc = 0;
wire m_axis_rc_tlast_nc = 0;
wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_rc_tkeep_nc = 0;
wire m_axis_rc_tvalid_nc = 0;
wire m_axis_rc_tready_nc;
// Interface: CQ (RXR)
wire [C_PCI_DATA_WIDTH-1:0] m_axis_cq_tdata_nc = 0;
wire [`SIG_CQ_TUSER_W-1:0] m_axis_cq_tuser_nc = 0;
wire m_axis_cq_tlast_nc = 0;
wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_cq_tkeep_nc = 0;
wire m_axis_cq_tvalid_nc = 0;
wire m_axis_cq_tready_nc = 0;
// Interface: CC (TXC)
wire [C_PCI_DATA_WIDTH-1:0] s_axis_cc_tdata_nc;
wire [`SIG_CC_TUSER_W-1:0] s_axis_cc_tuser_nc;
wire s_axis_cc_tlast_nc;
wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_cc_tkeep_nc;
wire s_axis_cc_tvalid_nc;
wire s_axis_cc_tready_nc = 0;
// Interface: Configuration
wire config_bus_master_enable;
wire [`SIG_CPLID_W-1:0] config_completer_id;
wire config_cpl_boundary_sel;
wire config_interrupt_msienable;
wire [`SIG_LINKRATE_W-1:0] config_link_rate;
wire [`SIG_LINKWIDTH_W-1:0] config_link_width;
wire [`SIG_MAXPAYLOAD_W-1:0] config_max_payload_size;
wire [`SIG_MAXREAD_W-1:0] config_max_read_request_size;
wire [`SIG_FC_CPLD_W-1:0] config_max_cpl_data;
wire [`SIG_FC_CPLH_W-1:0] config_max_cpl_hdr;
wire intr_msi_request;
wire intr_msi_rdy;
genvar chnl;
assign clk = PLD_CLK;
assign rst_in = RESET_STATUS;
translation_altera
#(/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH))
trans
(
// Outputs
.RX_TLP (rx_tlp[C_PCI_DATA_WIDTH-1:0]),
.RX_TLP_VALID (rx_tlp_valid),
.RX_TLP_START_FLAG (rx_tlp_start_flag),
.RX_TLP_START_OFFSET (rx_tlp_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RX_TLP_END_FLAG (rx_tlp_end_flag),
.RX_TLP_END_OFFSET (rx_tlp_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RX_TLP_BAR_DECODE (rx_tlp_bar_decode[`SIG_BARDECODE_W-1:0]),
.TX_TLP_READY (tx_tlp_ready),
.CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]),
.CONFIG_BUS_MASTER_ENABLE (config_bus_master_enable),
.CONFIG_LINK_WIDTH (config_link_width[`SIG_LINKWIDTH_W-1:0]),
.CONFIG_LINK_RATE (config_link_rate[`SIG_LINKRATE_W-1:0]),
.CONFIG_MAX_READ_REQUEST_SIZE (config_max_read_request_size[`SIG_MAXREAD_W-1:0]),
.CONFIG_MAX_PAYLOAD_SIZE (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]),
.CONFIG_INTERRUPT_MSIENABLE (config_interrupt_msienable),
.CONFIG_CPL_BOUNDARY_SEL (config_cpl_boundary_sel),
.CONFIG_MAX_CPL_DATA (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]),
.CONFIG_MAX_CPL_HDR (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]),
.INTR_MSI_RDY (intr_msi_rdy),
// Inputs
.CLK (clk),
.RST_IN (rst_in),
.RX_TLP_READY (rx_tlp_ready),
.TX_TLP (tx_tlp[C_PCI_DATA_WIDTH-1:0]),
.TX_TLP_VALID (tx_tlp_valid),
.TX_TLP_START_FLAG (tx_tlp_start_flag),
.TX_TLP_START_OFFSET (tx_tlp_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TX_TLP_END_FLAG (tx_tlp_end_flag),
.TX_TLP_END_OFFSET (tx_tlp_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.INTR_MSI_REQUEST (intr_msi_request),
/*AUTOINST*/
// Outputs
.RX_ST_READY (RX_ST_READY),
.TX_ST_DATA (TX_ST_DATA[C_PCI_DATA_WIDTH-1:0]),
.TX_ST_VALID (TX_ST_VALID[0:0]),
.TX_ST_EOP (TX_ST_EOP[0:0]),
.TX_ST_SOP (TX_ST_SOP[0:0]),
.TX_ST_EMPTY (TX_ST_EMPTY[0:0]),
.APP_MSI_REQ (APP_MSI_REQ),
// Inputs
.RX_ST_DATA (RX_ST_DATA[C_PCI_DATA_WIDTH-1:0]),
.RX_ST_EOP (RX_ST_EOP[0:0]),
.RX_ST_SOP (RX_ST_SOP[0:0]),
.RX_ST_VALID (RX_ST_VALID[0:0]),
.RX_ST_EMPTY (RX_ST_EMPTY[0:0]),
.TX_ST_READY (TX_ST_READY),
.TL_CFG_CTL (TL_CFG_CTL[`SIG_CFG_CTL_W-1:0]),
.TL_CFG_ADD (TL_CFG_ADD[`SIG_CFG_ADD_W-1:0]),
.TL_CFG_STS (TL_CFG_STS[`SIG_CFG_STS_W-1:0]),
.KO_CPL_SPC_HEADER (KO_CPL_SPC_HEADER[`SIG_FC_CPLH_W-1:0]),
.KO_CPL_SPC_DATA (KO_CPL_SPC_DATA[`SIG_FC_CPLD_W-1:0]),
.APP_MSI_ACK (APP_MSI_ACK));
engine_layer
#(// Parameters
.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_BYTES/4),
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_LOG_NUM_TAGS (C_LOG_NUM_TAGS),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_VENDOR (C_VENDOR))
engine_layer_inst
(// Outputs
.RXC_DATA (rxc_data[C_PCI_DATA_WIDTH-1:0]),
.RXC_DATA_WORD_ENABLE (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_VALID (rxc_data_valid),
.RXC_DATA_START_FLAG (rxc_data_start_flag),
.RXC_DATA_START_OFFSET (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_FDWBE (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXC_DATA_END_FLAG (rxc_data_end_flag),
.RXC_DATA_END_OFFSET (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_LDWBE (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXC_META_TAG (rxc_meta_tag[`SIG_TAG_W-1:0]),
.RXC_META_ADDR (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
.RXC_META_TYPE (rxc_meta_type[`SIG_TYPE_W-1:0]),
.RXC_META_LENGTH (rxc_meta_length[`SIG_LEN_W-1:0]),
.RXC_META_BYTES_REMAINING (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
.RXC_META_COMPLETER_ID (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
.RXC_META_EP (rxc_meta_ep),
.RXR_DATA (rxr_data[C_PCI_DATA_WIDTH-1:0]),
.RXR_DATA_WORD_ENABLE (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_VALID (rxr_data_valid),
.RXR_DATA_START_FLAG (rxr_data_start_flag),
.RXR_DATA_START_OFFSET (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_END_FLAG (rxr_data_end_flag),
.RXR_DATA_END_OFFSET (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_META_FDWBE (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXR_META_LDWBE (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXR_META_TC (rxr_meta_tc[`SIG_TC_W-1:0]),
.RXR_META_ATTR (rxr_meta_attr[`SIG_ATTR_W-1:0]),
.RXR_META_TAG (rxr_meta_tag[`SIG_TAG_W-1:0]),
.RXR_META_TYPE (rxr_meta_type[`SIG_TYPE_W-1:0]),
.RXR_META_ADDR (rxr_meta_addr[`SIG_ADDR_W-1:0]),
.RXR_META_BAR_DECODED (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
.RXR_META_REQUESTER_ID (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
.RXR_META_LENGTH (rxr_meta_length[`SIG_LEN_W-1:0]),
.RXR_META_EP (rxr_meta_ep),
.TXC_DATA_READY (txc_data_ready),
.TXC_META_READY (txc_meta_ready),
.TXC_SENT (txc_sent),
.TXR_DATA_READY (txr_data_ready),
.TXR_META_READY (txr_meta_ready),
.TXR_SENT (txr_sent),
.RST_LOGIC (RST_OUT),
// Unconnected Outputs
.TX_TLP (tx_tlp),
.TX_TLP_VALID (tx_tlp_valid),
.TX_TLP_START_FLAG (tx_tlp_start_flag),
.TX_TLP_START_OFFSET (tx_tlp_start_offset),
.TX_TLP_END_FLAG (tx_tlp_end_flag),
.TX_TLP_END_OFFSET (tx_tlp_end_offset),
.RX_TLP_READY (rx_tlp_ready),
// Inputs
.CLK_BUS (clk),
.RST_BUS (rst_in),
.CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]),
.TXC_DATA_VALID (txc_data_valid),
.TXC_DATA (txc_data[C_PCI_DATA_WIDTH-1:0]),
.TXC_DATA_START_FLAG (txc_data_start_flag),
.TXC_DATA_START_OFFSET (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_DATA_END_FLAG (txc_data_end_flag),
.TXC_DATA_END_OFFSET (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_META_VALID (txc_meta_valid),
.TXC_META_FDWBE (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
.TXC_META_TYPE (txc_meta_type[`SIG_TYPE_W-1:0]),
.TXC_META_LENGTH (txc_meta_length[`SIG_LEN_W-1:0]),
.TXC_META_BYTE_COUNT (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (txc_meta_tag[`SIG_TAG_W-1:0]),
.TXC_META_REQUESTER_ID (txc_meta_requester_id[`SIG_REQID_W-1:0]),
.TXC_META_TC (txc_meta_tc[`SIG_TC_W-1:0]),
.TXC_META_ATTR (txc_meta_attr[`SIG_ATTR_W-1:0]),
.TXC_META_EP (txc_meta_ep),
.TXR_DATA_VALID (txr_data_valid),
.TXR_DATA (txr_data[C_PCI_DATA_WIDTH-1:0]),
.TXR_DATA_START_FLAG (txr_data_start_flag),
.TXR_DATA_START_OFFSET (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (txr_data_end_flag),
.TXR_DATA_END_OFFSET (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (txr_meta_valid),
.TXR_META_FDWBE (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (txr_meta_addr[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (txr_meta_length[`SIG_LEN_W-1:0]),
.TXR_META_TAG (txr_meta_tag[`SIG_TAG_W-1:0]),
.TXR_META_TC (txr_meta_tc[`SIG_TC_W-1:0]),
.TXR_META_ATTR (txr_meta_attr[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (txr_meta_type[`SIG_TYPE_W-1:0]),
.TXR_META_EP (txr_meta_ep),
// Unconnected Inputs
.RX_TLP (rx_tlp),
.RX_TLP_VALID (rx_tlp_valid),
.RX_TLP_START_FLAG (rx_tlp_start_flag),
.RX_TLP_START_OFFSET (rx_tlp_start_offset),
.RX_TLP_END_FLAG (rx_tlp_end_flag),
.RX_TLP_END_OFFSET (rx_tlp_end_offset),
.RX_TLP_BAR_DECODE (rx_tlp_bar_decode),
.TX_TLP_READY (tx_tlp_ready),
.DONE_TXC_RST (done_txc_rst),
.DONE_TXR_RST (done_txr_rst),
.DONE_RXR_RST (done_rxc_rst),
.DONE_RXC_RST (done_rxr_rst),
// Outputs
.M_AXIS_CQ_TREADY (m_axis_cq_tready_nc),
.M_AXIS_RC_TREADY (m_axis_rc_tready_nc),
.S_AXIS_CC_TVALID (s_axis_cc_tvalid_nc),
.S_AXIS_CC_TLAST (s_axis_cc_tlast_nc),
.S_AXIS_CC_TDATA (s_axis_cc_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_CC_TKEEP (s_axis_cc_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_CC_TUSER (s_axis_cc_tuser_nc[`SIG_CC_TUSER_W-1:0]),
.S_AXIS_RQ_TVALID (s_axis_rq_tvalid_nc),
.S_AXIS_RQ_TLAST (s_axis_rq_tlast_nc),
.S_AXIS_RQ_TDATA (s_axis_rq_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_RQ_TKEEP (s_axis_rq_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_RQ_TUSER (s_axis_rq_tuser_nc[`SIG_RQ_TUSER_W-1:0]),
// Inputs
.M_AXIS_CQ_TVALID (m_axis_cq_tvalid_nc),
.M_AXIS_CQ_TLAST (m_axis_cq_tlast_nc),
.M_AXIS_CQ_TDATA (m_axis_cq_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_CQ_TKEEP (m_axis_cq_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_CQ_TUSER (m_axis_cq_tuser_nc[`SIG_CQ_TUSER_W-1:0]),
.M_AXIS_RC_TVALID (m_axis_rc_tvalid_nc),
.M_AXIS_RC_TLAST (m_axis_rc_tlast_nc),
.M_AXIS_RC_TDATA (m_axis_rc_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_RC_TKEEP (m_axis_rc_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_RC_TUSER (m_axis_rc_tuser_nc[`SIG_RC_TUSER_W-1:0]),
.S_AXIS_CC_TREADY (s_axis_cc_tready_nc),
.S_AXIS_RQ_TREADY (s_axis_rq_tready_nc)
/*AUTOINST*/);
riffa
#(.C_TAG_WIDTH (C_LOG_NUM_TAGS),/* TODO: Standardize declaration*/
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_NUM_CHNL (C_NUM_CHNL),
.C_MAX_READ_REQ_BYTES (C_MAX_READ_REQ_BYTES),
.C_VENDOR (C_VENDOR),
.C_FPGA_NAME (C_FPGA_NAME),
.C_FPGA_ID (C_FPGA_ID),
.C_DEPTH_PACKETS (C_DEPTH_PACKETS))
riffa_inst
(// Outputs
.TXC_DATA (txc_data[C_PCI_DATA_WIDTH-1:0]),
.TXC_DATA_VALID (txc_data_valid),
.TXC_DATA_START_FLAG (txc_data_start_flag),
.TXC_DATA_START_OFFSET (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_DATA_END_FLAG (txc_data_end_flag),
.TXC_DATA_END_OFFSET (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_META_VALID (txc_meta_valid),
.TXC_META_FDWBE (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
.TXC_META_TYPE (txc_meta_type[`SIG_TYPE_W-1:0]),
.TXC_META_LENGTH (txc_meta_length[`SIG_LEN_W-1:0]),
.TXC_META_BYTE_COUNT (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (txc_meta_tag[`SIG_TAG_W-1:0]),
.TXC_META_REQUESTER_ID (txc_meta_requester_id[`SIG_REQID_W-1:0]),
.TXC_META_TC (txc_meta_tc[`SIG_TC_W-1:0]),
.TXC_META_ATTR (txc_meta_attr[`SIG_ATTR_W-1:0]),
.TXC_META_EP (txc_meta_ep),
.TXR_DATA_VALID (txr_data_valid),
.TXR_DATA (txr_data[C_PCI_DATA_WIDTH-1:0]),
.TXR_DATA_START_FLAG (txr_data_start_flag),
.TXR_DATA_START_OFFSET (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (txr_data_end_flag),
.TXR_DATA_END_OFFSET (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (txr_meta_valid),
.TXR_META_FDWBE (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (txr_meta_addr[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (txr_meta_length[`SIG_LEN_W-1:0]),
.TXR_META_TAG (txr_meta_tag[`SIG_TAG_W-1:0]),
.TXR_META_TC (txr_meta_tc[`SIG_TC_W-1:0]),
.TXR_META_ATTR (txr_meta_attr[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (txr_meta_type[`SIG_TYPE_W-1:0]),
.TXR_META_EP (txr_meta_ep),
.INTR_MSI_REQUEST (intr_msi_request),
// Inputs
.CLK (clk),
.RXR_DATA (rxr_data[C_PCI_DATA_WIDTH-1:0]),
.RXR_DATA_VALID (rxr_data_valid),
.RXR_DATA_START_FLAG (rxr_data_start_flag),
.RXR_DATA_START_OFFSET (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_WORD_ENABLE (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_END_FLAG (rxr_data_end_flag),
.RXR_DATA_END_OFFSET (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_META_FDWBE (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXR_META_LDWBE (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXR_META_TC (rxr_meta_tc[`SIG_TC_W-1:0]),
.RXR_META_ATTR (rxr_meta_attr[`SIG_ATTR_W-1:0]),
.RXR_META_TAG (rxr_meta_tag[`SIG_TAG_W-1:0]),
.RXR_META_TYPE (rxr_meta_type[`SIG_TYPE_W-1:0]),
.RXR_META_ADDR (rxr_meta_addr[`SIG_ADDR_W-1:0]),
.RXR_META_BAR_DECODED (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
.RXR_META_REQUESTER_ID (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
.RXR_META_LENGTH (rxr_meta_length[`SIG_LEN_W-1:0]),
.RXR_META_EP (rxr_meta_ep),
.RXC_DATA_VALID (rxc_data_valid),
.RXC_DATA (rxc_data[C_PCI_DATA_WIDTH-1:0]),
.RXC_DATA_START_FLAG (rxc_data_start_flag),
.RXC_DATA_START_OFFSET (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_WORD_ENABLE (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_END_FLAG (rxc_data_end_flag),
.RXC_DATA_END_OFFSET (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_FDWBE (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXC_META_LDWBE (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXC_META_TAG (rxc_meta_tag[`SIG_TAG_W-1:0]),
.RXC_META_ADDR (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
.RXC_META_TYPE (rxc_meta_type[`SIG_TYPE_W-1:0]),
.RXC_META_LENGTH (rxc_meta_length[`SIG_LEN_W-1:0]),
.RXC_META_BYTES_REMAINING (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
.RXC_META_COMPLETER_ID (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
.RXC_META_EP (rxc_meta_ep),
.TXC_DATA_READY (txc_data_ready),
.TXC_META_READY (txc_meta_ready),
.TXC_SENT (txc_sent),
.TXR_DATA_READY (txr_data_ready),
.TXR_META_READY (txr_meta_ready),
.TXR_SENT (txr_sent),
.CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]),
.CONFIG_BUS_MASTER_ENABLE (config_bus_master_enable),
.CONFIG_LINK_WIDTH (config_link_width[`SIG_LINKWIDTH_W-1:0]),
.CONFIG_LINK_RATE (config_link_rate[`SIG_LINKRATE_W-1:0]),
.CONFIG_MAX_READ_REQUEST_SIZE (config_max_read_request_size[`SIG_MAXREAD_W-1:0]),
.CONFIG_MAX_PAYLOAD_SIZE (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]),
.CONFIG_INTERRUPT_MSIENABLE (config_interrupt_msienable),
.CONFIG_CPL_BOUNDARY_SEL (config_cpl_boundary_sel),
.CONFIG_MAX_CPL_DATA (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]),
.CONFIG_MAX_CPL_HDR (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]),
.INTR_MSI_RDY (intr_msi_rdy),
.DONE_TXC_RST (done_txc_rst),
.DONE_TXR_RST (done_txr_rst),
.RST_BUS (rst_in),
/*AUTOINST*/
// Outputs
.RST_OUT (RST_OUT),
.CHNL_RX (CHNL_RX[C_NUM_CHNL-1:0]),
.CHNL_RX_LAST (CHNL_RX_LAST[C_NUM_CHNL-1:0]),
.CHNL_RX_LEN (CHNL_RX_LEN[(C_NUM_CHNL*32)-1:0]),
.CHNL_RX_OFF (CHNL_RX_OFF[(C_NUM_CHNL*31)-1:0]),
.CHNL_RX_DATA (CHNL_RX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_RX_DATA_VALID (CHNL_RX_DATA_VALID[C_NUM_CHNL-1:0]),
.CHNL_TX_ACK (CHNL_TX_ACK[C_NUM_CHNL-1:0]),
.CHNL_TX_DATA_REN (CHNL_TX_DATA_REN[C_NUM_CHNL-1:0]),
// Inputs
.CHNL_RX_CLK (CHNL_RX_CLK[C_NUM_CHNL-1:0]),
.CHNL_RX_ACK (CHNL_RX_ACK[C_NUM_CHNL-1:0]),
.CHNL_RX_DATA_REN (CHNL_RX_DATA_REN[C_NUM_CHNL-1:0]),
.CHNL_TX_CLK (CHNL_TX_CLK[C_NUM_CHNL-1:0]),
.CHNL_TX (CHNL_TX[C_NUM_CHNL-1:0]),
.CHNL_TX_LAST (CHNL_TX_LAST[C_NUM_CHNL-1:0]),
.CHNL_TX_LEN (CHNL_TX_LEN[(C_NUM_CHNL*32)-1:0]),
.CHNL_TX_OFF (CHNL_TX_OFF[(C_NUM_CHNL*31)-1:0]),
.CHNL_TX_DATA (CHNL_TX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_TX_DATA_VALID (CHNL_TX_DATA_VALID[C_NUM_CHNL-1:0]));
endmodule
// Local Variables:
// verilog-library-directories:("../../riffa_hdl/")
// End:
|
module MEM_WR(
input clk,
input stall,
input flush,
input [31:0] MemData_Mem,
input [3:0] Rd_write_byte_en_Mem,
input [31:0] WBData_Mem,
input MemRead_Mem,
input RegWrite_Mem,
input [4:0] Rd_Mem,
output reg [31:0] MemData_Wr,
output reg [3:0] Rd_write_byte_en_Wr,
output reg [31:0] WBData_Wr,
output reg MemRead_Wr,
output reg RegWrite_Wr,
output reg [4:0] Rd_Wr
);
initial
begin
MemData_Wr=32'b0;
Rd_write_byte_en_Wr=4'b0;
WBData_Wr=32'b0;
MemRead_Wr=0;
RegWrite_Wr=0;
Rd_Wr=5'b0;
end
always@(negedge clk)begin
if(flush)begin//冲刷，防止出错
MemData_Wr<= 32'h00000000;
Rd_write_byte_en_Wr<= 4'b0000;
WBData_Wr<= 32'b0;
MemRead_Wr<= 0;
RegWrite_Wr<= 0;
Rd_Wr<= 4'b0000;
//其他信号没有关系，不关心
end
else if(!stall)begin//如果不是保持就继续向下传递流水
MemData_Wr<=MemData_Mem;
Rd_write_byte_en_Wr<=Rd_write_byte_en_Mem;
WBData_Wr<=WBData_Mem;
MemRead_Wr<=MemRead_Mem;
RegWrite_Wr<=RegWrite_Mem;
Rd_Wr<= Rd_Mem;
end
end
/*always @(negedge clk)begin
// 否则就是保持，也即什么赋值也不需要做继续保持
end*/
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFSTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__SDFSTP_BEHAVIORAL_PP_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_hdll__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hdll__sdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hdll__udp_dff$PS_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( SET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( SET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFSTP_BEHAVIORAL_PP_V |
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
// Date : Sun Aug 28 08:25:18 2016
// Host : fpgaserv running 64-bit Ubuntu 14.04.4 LTS
// Command : write_verilog -force -mode synth_stub
// /home/kobayashi/PCIe_test/branches/IEICE/data_compression/16-way_2-tree/src/ip_pcie/PCIeGen2x8If128_stub.v
// Design : PCIeGen2x8If128
// Purpose : Stub declaration of top-level module interface
// Device : xc7vx485tffg1761-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "PCIeGen2x8If128_pcie2_top,Vivado 2015.4" *)
module PCIeGen2x8If128(pci_exp_txp, pci_exp_txn, pci_exp_rxp, pci_exp_rxn, user_clk_out, user_reset_out, user_lnk_up, user_app_rdy, tx_buf_av, tx_cfg_req, tx_err_drop, s_axis_tx_tready, s_axis_tx_tdata, s_axis_tx_tkeep, s_axis_tx_tlast, s_axis_tx_tvalid, s_axis_tx_tuser, tx_cfg_gnt, m_axis_rx_tdata, m_axis_rx_tkeep, m_axis_rx_tlast, m_axis_rx_tvalid, m_axis_rx_tready, m_axis_rx_tuser, rx_np_ok, rx_np_req, fc_cpld, fc_cplh, fc_npd, fc_nph, fc_pd, fc_ph, fc_sel, cfg_status, cfg_command, cfg_dstatus, cfg_dcommand, cfg_lstatus, cfg_lcommand, cfg_dcommand2, cfg_pcie_link_state, cfg_pmcsr_pme_en, cfg_pmcsr_powerstate, cfg_pmcsr_pme_status, cfg_received_func_lvl_rst, cfg_trn_pending, cfg_pm_halt_aspm_l0s, cfg_pm_halt_aspm_l1, cfg_pm_force_state_en, cfg_pm_force_state, cfg_dsn, cfg_interrupt, cfg_interrupt_rdy, cfg_interrupt_assert, cfg_interrupt_di, cfg_interrupt_do, cfg_interrupt_mmenable, cfg_interrupt_msienable, cfg_interrupt_msixenable, cfg_interrupt_msixfm, cfg_interrupt_stat, cfg_pciecap_interrupt_msgnum, cfg_to_turnoff, cfg_turnoff_ok, cfg_bus_number, cfg_device_number, cfg_function_number, cfg_pm_wake, cfg_pm_send_pme_to, cfg_ds_bus_number, cfg_ds_device_number, cfg_ds_function_number, cfg_bridge_serr_en, cfg_slot_control_electromech_il_ctl_pulse, cfg_root_control_syserr_corr_err_en, cfg_root_control_syserr_non_fatal_err_en, cfg_root_control_syserr_fatal_err_en, cfg_root_control_pme_int_en, cfg_aer_rooterr_corr_err_reporting_en, cfg_aer_rooterr_non_fatal_err_reporting_en, cfg_aer_rooterr_fatal_err_reporting_en, cfg_aer_rooterr_corr_err_received, cfg_aer_rooterr_non_fatal_err_received, cfg_aer_rooterr_fatal_err_received, cfg_vc_tcvc_map, sys_clk, sys_rst_n)
/* synthesis syn_black_box black_box_pad_pin="pci_exp_txp[7:0],pci_exp_txn[7:0],pci_exp_rxp[7:0],pci_exp_rxn[7:0],user_clk_out,user_reset_out,user_lnk_up,user_app_rdy,tx_buf_av[5:0],tx_cfg_req,tx_err_drop,s_axis_tx_tready,s_axis_tx_tdata[127:0],s_axis_tx_tkeep[15:0],s_axis_tx_tlast,s_axis_tx_tvalid,s_axis_tx_tuser[3:0],tx_cfg_gnt,m_axis_rx_tdata[127:0],m_axis_rx_tkeep[15:0],m_axis_rx_tlast,m_axis_rx_tvalid,m_axis_rx_tready,m_axis_rx_tuser[21:0],rx_np_ok,rx_np_req,fc_cpld[11:0],fc_cplh[7:0],fc_npd[11:0],fc_nph[7:0],fc_pd[11:0],fc_ph[7:0],fc_sel[2:0],cfg_status[15:0],cfg_command[15:0],cfg_dstatus[15:0],cfg_dcommand[15:0],cfg_lstatus[15:0],cfg_lcommand[15:0],cfg_dcommand2[15:0],cfg_pcie_link_state[2:0],cfg_pmcsr_pme_en,cfg_pmcsr_powerstate[1:0],cfg_pmcsr_pme_status,cfg_received_func_lvl_rst,cfg_trn_pending,cfg_pm_halt_aspm_l0s,cfg_pm_halt_aspm_l1,cfg_pm_force_state_en,cfg_pm_force_state[1:0],cfg_dsn[63:0],cfg_interrupt,cfg_interrupt_rdy,cfg_interrupt_assert,cfg_interrupt_di[7:0],cfg_interrupt_do[7:0],cfg_interrupt_mmenable[2:0],cfg_interrupt_msienable,cfg_interrupt_msixenable,cfg_interrupt_msixfm,cfg_interrupt_stat,cfg_pciecap_interrupt_msgnum[4:0],cfg_to_turnoff,cfg_turnoff_ok,cfg_bus_number[7:0],cfg_device_number[4:0],cfg_function_number[2:0],cfg_pm_wake,cfg_pm_send_pme_to,cfg_ds_bus_number[7:0],cfg_ds_device_number[4:0],cfg_ds_function_number[2:0],cfg_bridge_serr_en,cfg_slot_control_electromech_il_ctl_pulse,cfg_root_control_syserr_corr_err_en,cfg_root_control_syserr_non_fatal_err_en,cfg_root_control_syserr_fatal_err_en,cfg_root_control_pme_int_en,cfg_aer_rooterr_corr_err_reporting_en,cfg_aer_rooterr_non_fatal_err_reporting_en,cfg_aer_rooterr_fatal_err_reporting_en,cfg_aer_rooterr_corr_err_received,cfg_aer_rooterr_non_fatal_err_received,cfg_aer_rooterr_fatal_err_received,cfg_vc_tcvc_map[6:0],sys_clk,sys_rst_n" */;
output [7:0]pci_exp_txp;
output [7:0]pci_exp_txn;
input [7:0]pci_exp_rxp;
input [7:0]pci_exp_rxn;
output user_clk_out;
output user_reset_out;
output user_lnk_up;
output user_app_rdy;
output [5:0]tx_buf_av;
output tx_cfg_req;
output tx_err_drop;
output s_axis_tx_tready;
input [127:0]s_axis_tx_tdata;
input [15:0]s_axis_tx_tkeep;
input s_axis_tx_tlast;
input s_axis_tx_tvalid;
input [3:0]s_axis_tx_tuser;
input tx_cfg_gnt;
output [127:0]m_axis_rx_tdata;
output [15:0]m_axis_rx_tkeep;
output m_axis_rx_tlast;
output m_axis_rx_tvalid;
input m_axis_rx_tready;
output [21:0]m_axis_rx_tuser;
input rx_np_ok;
input rx_np_req;
output [11:0]fc_cpld;
output [7:0]fc_cplh;
output [11:0]fc_npd;
output [7:0]fc_nph;
output [11:0]fc_pd;
output [7:0]fc_ph;
input [2:0]fc_sel;
output [15:0]cfg_status;
output [15:0]cfg_command;
output [15:0]cfg_dstatus;
output [15:0]cfg_dcommand;
output [15:0]cfg_lstatus;
output [15:0]cfg_lcommand;
output [15:0]cfg_dcommand2;
output [2:0]cfg_pcie_link_state;
output cfg_pmcsr_pme_en;
output [1:0]cfg_pmcsr_powerstate;
output cfg_pmcsr_pme_status;
output cfg_received_func_lvl_rst;
input cfg_trn_pending;
input cfg_pm_halt_aspm_l0s;
input cfg_pm_halt_aspm_l1;
input cfg_pm_force_state_en;
input [1:0]cfg_pm_force_state;
input [63:0]cfg_dsn;
input cfg_interrupt;
output cfg_interrupt_rdy;
input cfg_interrupt_assert;
input [7:0]cfg_interrupt_di;
output [7:0]cfg_interrupt_do;
output [2:0]cfg_interrupt_mmenable;
output cfg_interrupt_msienable;
output cfg_interrupt_msixenable;
output cfg_interrupt_msixfm;
input cfg_interrupt_stat;
input [4:0]cfg_pciecap_interrupt_msgnum;
output cfg_to_turnoff;
input cfg_turnoff_ok;
output [7:0]cfg_bus_number;
output [4:0]cfg_device_number;
output [2:0]cfg_function_number;
input cfg_pm_wake;
input cfg_pm_send_pme_to;
input [7:0]cfg_ds_bus_number;
input [4:0]cfg_ds_device_number;
input [2:0]cfg_ds_function_number;
output cfg_bridge_serr_en;
output cfg_slot_control_electromech_il_ctl_pulse;
output cfg_root_control_syserr_corr_err_en;
output cfg_root_control_syserr_non_fatal_err_en;
output cfg_root_control_syserr_fatal_err_en;
output cfg_root_control_pme_int_en;
output cfg_aer_rooterr_corr_err_reporting_en;
output cfg_aer_rooterr_non_fatal_err_reporting_en;
output cfg_aer_rooterr_fatal_err_reporting_en;
output cfg_aer_rooterr_corr_err_received;
output cfg_aer_rooterr_non_fatal_err_received;
output cfg_aer_rooterr_fatal_err_received;
output [6:0]cfg_vc_tcvc_map;
input sys_clk;
input sys_rst_n;
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Fri Sep 22 22:04:40 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_stub.v
// Design : zqynq_lab_1_design_axi_bram_ctrl_0_bram_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_3_6,Vivado 2017.2.1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clka, rsta, ena, wea, addra, dina, douta, clkb, rstb, enb,
web, addrb, dinb, doutb)
/* synthesis syn_black_box black_box_pad_pin="clka,rsta,ena,wea[3:0],addra[31:0],dina[31:0],douta[31:0],clkb,rstb,enb,web[3:0],addrb[31:0],dinb[31:0],doutb[31:0]" */;
input clka;
input rsta;
input ena;
input [3:0]wea;
input [31:0]addra;
input [31:0]dina;
output [31:0]douta;
input clkb;
input rstb;
input enb;
input [3:0]web;
input [31:0]addrb;
input [31:0]dinb;
output [31:0]doutb;
endmodule
|
`timescale 1ns / 1ps
module text_editor_top(
MemOE, MemWR, RamCS, FlashCS, QuadSpiFlashCS, // Disable the three memory chips
ClkPort, // the 100 MHz incoming clock signal
BtnC, // the middle button used as Reset
Ld7, Ld6, Ld5, Ld4, Ld3, Ld2, Ld1, Ld0,
An3, An2, An1, An0, // 4 anodes
Ca, Cb, Cc, Cd, Ce, Cf, Cg, // 7 cathodes
Dp, // Dot Point Cathode on SSDs
PS2KeyboardData, // PS2 Keyboard data bus
PS2KeyboardClk, // PS2 Keyboard data clock
vga_h_sync, // VGA Output Horizontal Sync signal
vga_v_sync, // VGA Output Vertical Sync signal
vga_r, // Red value for current scanning pixel
vga_g, // Green value for current scanning pixel
vga_b // Blue value for current scanning pixel
);
/************************************************************************
* INPUTS *
************************************************************************/
input ClkPort;
input BtnC;
/************************************************************************
* BIDIRECTIONALS *
************************************************************************/
inout PS2KeyboardData, PS2KeyboardClk;
/************************************************************************
* OUTPUTS *
************************************************************************/
output MemOE, MemWR, RamCS, FlashCS, QuadSpiFlashCS;
output Ld7, Ld6, Ld5, Ld4, Ld3, Ld2, Ld1, Ld0;
output Cg, Cf, Ce, Cd, Cc, Cb, Ca, Dp;
output An0, An1, An2, An3;
output vga_h_sync, vga_v_sync, vga_r, vga_g, vga_b;
/************************************************************************
* LOCAL SIGNALS *
************************************************************************/
wire Reset, ClkPort;
wire board_clk, sys_clk, PS2_clk, VGA_clk, cursor_clk;
wire [1:0] ssdscan_clk;
reg [26:0] DIV_CLK;
reg [3:0] SSD;
wire [3:0] SSD3, SSD2, SSD1, SSD0;
reg [7:0] SSD_CATHODES;
wire [7:0] KeyData;
wire KeyReleased;
reg [7:0] CurrentKey;
reg [8:0] document_pointer;
reg [8:0] write_location;
reg write_to_RAM;
wire [7:0] RAM_data;
wire [9:0] read_address;
reg vga_r, vga_g, vga_b;
assign { Ld7, Ld6, Ld5, Ld4, Ld3, Ld2, Ld1, Ld0 } = document_pointer[7:0];
assign Reset = BtnC;
// Disable the three memories so that they do not interfere with the rest of the design.
assign {MemOE, MemWR, RamCS, FlashCS, QuadSpiFlashCS} = 5'b11111;
/************************************************************************
* CLOCK DIVISION *
************************************************************************/
BUFGP BUFGP1 (board_clk, ClkPort);
// Our clock is too fast (100MHz) for SSD scanning
// create a series of slower "divided" clocks
// each successive bit is 1/2 frequency
always @(posedge board_clk, posedge Reset) begin
if (Reset)
DIV_CLK <= 0;
else
DIV_CLK <= DIV_CLK + 1'b1;
end
assign sys_clk = board_clk; // 100 MHz
assign PS2_clk = DIV_CLK[0]; // 50 MHz
assign VGA_clk = DIV_CLK[1]; // 25 MHz
assign cursor_clk = DIV_CLK[26]; // .75 Hz
/************************************************************************
* VGA Control *
************************************************************************/
parameter RAM_size = 10'd512; // Size of the RAM
parameter write_area = RAM_size - 10'd2; // Allowable write area in the RAM (last location used as a null location)
parameter char_dim = 10'd16; // Dimension of a character (16x16 bits)
parameter char_scale_i = 10'd2; // Initial character scale
parameter row_length_i = 10'd18; // Initial length of a row (number of columns)
parameter col_length_i = 10'd29; // Initial length of a column (number of rows)
reg [9:0] char_scale;
reg [9:0] row_length;
reg [9:0] col_length;
reg [9:0] scroll;
reg text_red;
reg text_green;
reg text_blue;
wire inDisplayArea;
wire [9:0] CounterX;
wire [9:0] CounterY;
wire [9:0] CounterXDiv;
wire [9:0] CounterYDiv;
assign CounterXDiv = CounterX / char_scale;
assign CounterYDiv = CounterY / char_scale;
wire shouldDraw;
assign shouldDraw = CounterXDiv < char_dim * row_length && CounterYDiv < char_dim * col_length;
wire [0:255] relativePixel;
assign relativePixel = CounterXDiv % char_dim + CounterYDiv % char_dim * char_dim;
wire drawCursor;
assign drawCursor = read_address == document_pointer && Cursor[relativePixel] && cursor_clk;
assign read_address = (CounterXDiv / char_dim + CounterYDiv / char_dim * row_length + scroll * row_length) < RAM_size - 1'b1 ?
(CounterXDiv / char_dim + CounterYDiv / char_dim * row_length + scroll * row_length) :
RAM_size - 1'b1;
hvsync_generator vgaSyncGen(
// Inputs
.clk(VGA_clk),
.reset(Reset),
// Outputs
.vga_h_sync(vga_h_sync),
.vga_v_sync(vga_v_sync),
.inDisplayArea(inDisplayArea),
.CounterX(CounterX),
.CounterY(CounterY)
);
always @(posedge VGA_clk) begin
vga_r <= Red & inDisplayArea;
vga_g <= Green & inDisplayArea;
vga_b <= Blue & inDisplayArea;
end
wire Red = shouldDraw && ((~drawCursor && text_red && toDraw[relativePixel]) || (drawCursor && !text_red) || (drawCursor && text_red && text_green && text_blue));
wire Blue = shouldDraw && ((~drawCursor && text_blue && toDraw[relativePixel]) || (drawCursor && !text_blue));
wire Green = shouldDraw && ((~drawCursor && text_green && toDraw[relativePixel]) || (drawCursor && !text_green));
wire [0:255] toDraw;
assign toDraw = RAM_data == 8'h70 ? Block :
RAM_data == 8'h49 ? Period :
RAM_data == 8'h41 ? Comma :
RAM_data == 8'h52 ? Apost :
RAM_data == 8'h1C ? A :
RAM_data == 8'h32 ? B :
RAM_data == 8'h21 ? C :
RAM_data == 8'h23 ? D :
RAM_data == 8'h24 ? E :
RAM_data == 8'h2B ? F :
RAM_data == 8'h34 ? G :
RAM_data == 8'h33 ? H :
RAM_data == 8'h43 ? I :
RAM_data == 8'h3B ? J :
RAM_data == 8'h42 ? K :
RAM_data == 8'h4B ? L :
RAM_data == 8'h3A ? M :
RAM_data == 8'h31 ? N :
RAM_data == 8'h44 ? O :
RAM_data == 8'h4D ? P :
RAM_data == 8'h15 ? Q :
RAM_data == 8'h2D ? R :
RAM_data == 8'h1B ? S :
RAM_data == 8'h2C ? T :
RAM_data == 8'h3C ? U :
RAM_data == 8'h2A ? V :
RAM_data == 8'h1D ? W :
RAM_data == 8'h22 ? X :
RAM_data == 8'h35 ? Y :
RAM_data == 8'h1A ? Z :
RAM_data == 8'h16 ? num1 :
RAM_data == 8'h1E ? num2 :
RAM_data == 8'h26 ? num3 :
RAM_data == 8'h25 ? num4 :
RAM_data == 8'h2E ? num5 :
RAM_data == 8'h36 ? num6 :
RAM_data == 8'h3D ? num7 :
RAM_data == 8'h3E ? num8 :
RAM_data == 8'h46 ? num9 :
RAM_data == 8'h45 ? num0 :
256'd0;
parameter [0:255] Cursor = 256'hC000C000C000C000C000C000C000C000C000C000C000C000C000C000C000C000;
parameter [0:255] Block = 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;
parameter [0:255] Period = 256'h0000000000000000000000000000000000000000000000000000E000E000E000;
parameter [0:255] Comma = 256'h000000000000000000000000000000000000000000000000000070007000E000;
parameter [0:255] Apost = 256'h070007000E000000000000000000000000000000000000000000000000000000;
parameter [0:255] A = 256'h00001FE03870387070387038E01CE01CE01CFFFCFFFCE01CE01CE01CE01CE01C;
parameter [0:255] B = 256'h0000FFC0FFF0F078F03CF03CF038FFE0FFE0F038F03CF03CF03CF07CFFF8FFE0;
parameter [0:255] C = 256'h00001FF07FFCF81EF01EE000E000E000E000E000E000E000E01EF01E7FFC1FF0;
parameter [0:255] D = 256'h0000FFE0FFF8F03CF01CF00EF00EF00EF00EF00EF00EF00EF01CF03CFFF8FFE0;
parameter [0:255] E = 256'h0000FFFEFFFEE000E000E000E000FFFEFFFEE000E000E000E000E000FFFEFFFE;
parameter [0:255] F = 256'h0000FFFEFFFEF000F000F000F000FFFEFFFEF000F000F000F000F000F000F000;
parameter [0:255] G = 256'h00003FF07FF8F01EE00EC000C000C000C000C07EC07EC00EC00EF01E7FF83FF0;
parameter [0:255] H = 256'h0000E00EE00EE00EE00EE00EE00EFFFEFFFEE00EE00EE00EE00EE00EE00EE00E;
parameter [0:255] I = 256'h0000FFFCFFFC07800780078007800780078007800780078007800780FFFCFFFC;
parameter [0:255] J = 256'h00003FFC3FFC001C001C001C001C001C001C001CE01CE01CE01CF03C7FF83FF0;
parameter [0:255] K = 256'h0000E00EE00EE01CE038E070E0E0FFC0FFC0E0E0E070E038E01CE00EE00EE00E;
parameter [0:255] L = 256'h0000E000E000E000E000E000E000E000E000E000E000E000E000E000FFFCFFFC;
parameter [0:255] M = 256'h0000F87CFCFCFCFCECDCEFDCE79CE31CE01CE01CE01CE01CE01CE01CE01CE01C;
parameter [0:255] N = 256'h0000F81CF81CEC1CEC1CE61CE61CE31CE31CE31CE19CE19CE0DCE0DCE07CE07C;
parameter [0:255] O = 256'h00003FF07878E01CE01CE01CE01CE01CE01CE01CE01CE01CE01CF03C78783FF0;
parameter [0:255] P = 256'h0000FFC0FFF8F07CF03CF03CF03CF07CFFF8FFC0F000F000F000F000F000F000;
parameter [0:255] Q = 256'h00003FF07878E01CE01CE01CE01CE01CE01CE01CE01CE01CE01CF03C787C0FDE;
parameter [0:255] R = 256'h0000FFF0FFFCF01EF01EF01EF01EFFF0FFC0F0F0F078F03CF03CF01EF01EF01E;
parameter [0:255] S = 256'h00000FF03FFCE01EE00EE00EF0007FF01FFC001EE00EE00EF00E781E3FFC07F8;
parameter [0:255] T = 256'h0000FFFEFFFE0380038003800380038003800380038003800380038003800380;
parameter [0:255] U = 256'h0000E00EE00EE00EE00EE00EE00EE00EE00EE00EE00EE00EE00EE00E783C1FF0;
parameter [0:255] V = 256'h0000E00EF01EF01E783C783C3C783C783C781EF01EF00FE00FE007C003800100;
parameter [0:255] W = 256'h0000E01CE01CE01CE01CE01CE01CE01CE01CE31CE79CEFDCECDCFCFCFCFCF87C;
parameter [0:255] X = 256'h0000F01EF01E78783CF03CF01FE00FC007800FC01FE03CF03CF07878F03CF03C;
parameter [0:255] Y = 256'h0000E00EE00E701C781C3C780FE007C003800380038003800380038003800380;
parameter [0:255] Z = 256'h0000FFFEFFFE001E003C007800F001E003C00F001E003C007800F000FFFEFFFE;
parameter [0:255] num1 = 256'h0000003C00FC01DC039C071C001C001C001C001C001C001C001C001C001C001C;
parameter [0:255] num2 = 256'h00000FF01FF8381C001C001C001C0038007000E001C0038007001C003FFC3FFC;
parameter [0:255] num3 = 256'h00003FFC3FFC000C00180060018003C000E0003000380038003800383FF03FC0;
parameter [0:255] num4 = 256'h0000007C00DC019C031C061C0C1C181C301C3FFC001C001C001C001C001C001C;
parameter [0:255] num5 = 256'h00003FFC3FFC3000300030003FC001E00070003000380038007000E03FC03F00;
parameter [0:255] num6 = 256'h000000E003800E0018003800380038003FE03FF03C18381838181C181FF00FE0;
parameter [0:255] num7 = 256'h00003FFC3FFC001C001C001C3FFC3FFC001C001C001C001C001C001C001C001C;
parameter [0:255] num8 = 256'h00001FF83FFC381C381C381C3FFC3FFC381C381C381C381C381C381C3FFC1FF8;
parameter [0:255] num9 = 256'h00001FFC3FFC381C300C300C381C1FFC0FFC000C000C000C000C000C007C007C;
parameter [0:255] num0 = 256'h00001FF83FFC381C381C381C381C381C381C381C381C381C381C381C3FFC1FF8;
/************************************************************************
* PS2 KEYBOARD *
************************************************************************/
text_editor_keyboard_controller KeyBoard(
// Inputs
.sys_Clk(sys_clk),
.PS2_Clk(PS2_clk),
.Reset(Reset),
// Bidirectionals
.PS2KeyboardData(PS2KeyboardData),
.PS2KeyboardClk(PS2KeyboardClk),
// Outputs
.KeyData(KeyData),
.KeyReleased(KeyReleased)
);
/************************************************************************
* TEXT RAM *
************************************************************************/
text_editor_RAM RAM(
// Inputs
.clk(sys_clk),
.Reset(Reset),
.write(write_to_RAM),
.write_address(write_location),
.write_data(CurrentKey),
.read_address(read_address[8:0]),
// Outputs
.read_data(RAM_data)
);
/************************************************************************
* STATE MACHINE *
************************************************************************/
reg [1:0] state;
localparam
INI = 2'b00,
GETKEY = 2'b01,
EDIT = 2'b10,
WRITE = 2'b11,
UNK = 2'bXX;
always @ (posedge sys_clk, posedge Reset) begin: STATE_MACHINE
if (Reset) begin
CurrentKey <= 8'hXX;
document_pointer <= 9'bXXXXXXXXX;
write_location <= 9'bXXXXXXXXX;
write_to_RAM <= 1'bX;
char_scale <= 10'bXXXXXXXXXX;
row_length <= 10'bXXXXXXXXXX;
col_length <= 10'bXXXXXXXXXX;
scroll <= 10'bXXXXXXXXXX;
text_red <= 1'bX;
text_green <= 1'bX;
text_blue <= 1'bX;
state <= INI;
end else begin
case (state)
INI: begin
state <= GETKEY;
CurrentKey <= 8'h29; // SPACE
write_to_RAM <= 1'b0;
document_pointer <= 10'd0;
write_location <= 10'd0;
char_scale <= char_scale_i;
row_length <= row_length_i;
col_length <= col_length_i;
scroll <= 10'd0;
text_red <= 1'b0;
text_green <= 1'b1;
text_blue <= 1'b0;
end
GETKEY: begin
if (KeyReleased) begin
state <= EDIT;
end
CurrentKey <= KeyData;
case(char_scale)
2'd1: begin row_length <= 10'd36; col_length <= 10'd15; end
2'd2: begin row_length <= 10'd18; col_length <= 10'd29; end
2'd3: begin row_length <= 10'd12; col_length <= 10'd43; end
default: begin row_length <= 10'd18; col_length <= 10'd29; end
endcase
end
EDIT: begin
state <= WRITE;
write_to_RAM <= 1'b1;
write_location <= document_pointer;
case (CurrentKey)
8'h66: begin // BACKSPACE
if (document_pointer > 10'd0) begin
document_pointer <= document_pointer - 1'b1;
write_location <= document_pointer - 1'b1;
end
CurrentKey <= 8'h29; // SPACE
end
8'h6B: begin // LEFT ARROW
write_to_RAM <= 1'b0;
if (document_pointer > 10'd0) begin
document_pointer <= document_pointer - 1'b1;
end
end
8'h74: begin // RIGHT ARROW
write_to_RAM <= 1'b0;
if (document_pointer < write_area) begin
document_pointer <= document_pointer + 1'b1;
end
end
8'h75: begin // UP ARROW
write_to_RAM <= 1'b0;
if (document_pointer >= row_length) begin
document_pointer <= document_pointer - row_length;
end
end
8'h72: begin // DOWN ARROW
write_to_RAM <= 1'b0;
if (document_pointer <= write_area - row_length) begin
document_pointer <= document_pointer + row_length;
end
end
8'h79: begin // + KEYPAD
write_to_RAM <= 1'b0;
if (char_scale < 10'd3) begin
char_scale <= char_scale + 1'b1;
end
end
8'h7B: begin // - KEYPAD
write_to_RAM <= 1'b0;
if (char_scale > 10'd1) begin
char_scale <= char_scale - 1'b1;
end
end
8'h7D: begin // PG UP
write_to_RAM <= 1'b0;
if (scroll < col_length - 2'd2) begin
scroll <= scroll + 1'b1;
end
end
8'h7A: begin // PG DOWN
write_to_RAM <= 1'b0;
if (scroll > 10'd0) begin
scroll <= scroll - 1'b1;
end
end
8'h05: begin // F1 (Red color)
write_to_RAM <= 1'b0;
text_red <= ~text_red;
if (text_red && !text_blue) begin
text_green <= 1'b1;
end
end
8'h06: begin // F2 (Green color)
write_to_RAM <= 1'b0;
text_green <= ~text_green;
if (text_green && !text_blue && !text_red) begin
text_green <= 1'b1;
end
end
8'h04: begin // F3 (Blue color)
write_to_RAM <= 1'b0;
text_blue <= ~text_blue;
if (text_blue && !text_red) begin
text_green <= 1'b1;
end
end
8'h71: begin // DELETE KEY
CurrentKey <= 8'h29; // SPACE
end
default: begin
if (document_pointer < write_area) begin
document_pointer <= document_pointer + 1'b1;
end
end
endcase
end
WRITE: begin
state <= GETKEY;
write_to_RAM <= 1'b0;
end
default: begin
state <= UNK;
end
endcase
end
end
/************************************************************************
* SSD OUTPUT *
************************************************************************/
assign SSD3 = 0;
assign SSD2 = 0;
assign SSD1 = KeyData[7:4];
assign SSD0 = KeyData[3:0];
assign ssdscan_clk = DIV_CLK[19:18];
assign An3 = 1; //!(~(ssdscan_clk[1]) && ~(ssdscan_clk[0])); // when ssdscan_clk = 00 **Used for debugging, disabled in final project**
assign An2 = 1; //!(~(ssdscan_clk[1]) && (ssdscan_clk[0])); // when ssdscan_clk = 01 **Used for debugging, disabled in final project**
assign An1 = !((ssdscan_clk[1]) && ~(ssdscan_clk[0])); // when ssdscan_clk = 10
assign An0 = !((ssdscan_clk[1]) && (ssdscan_clk[0])); // when ssdscan_clk = 11
always @ (ssdscan_clk, SSD0, SSD1, SSD2, SSD3) begin: SSD_SCAN_OUT
case (ssdscan_clk)
2'b00: SSD = SSD3;
2'b01: SSD = SSD2;
2'b10: SSD = SSD1;
2'b11: SSD = SSD0;
endcase
end
// and finally convert SSD_num to ssd
// We convert the output of our 4-bit 4x1 mux
assign {Ca, Cb, Cc, Cd, Ce, Cf, Cg, Dp} = {SSD_CATHODES};
// Following is Hex-to-SSD conversion
always @ (SSD)
begin : HEX_TO_SSD
case (SSD)
4'b0000: SSD_CATHODES = 8'b00000011; // 0
4'b0001: SSD_CATHODES = 8'b10011111; // 1
4'b0010: SSD_CATHODES = 8'b00100101; // 2
4'b0011: SSD_CATHODES = 8'b00001101; // 3
4'b0100: SSD_CATHODES = 8'b10011001; // 4
4'b0101: SSD_CATHODES = 8'b01001001; // 5
4'b0110: SSD_CATHODES = 8'b01000001; // 6
4'b0111: SSD_CATHODES = 8'b00011111; // 7
4'b1000: SSD_CATHODES = 8'b00000001; // 8
4'b1001: SSD_CATHODES = 8'b00001001; // 9
4'b1010: SSD_CATHODES = 8'b00010001; // A
4'b1011: SSD_CATHODES = 8'b11000001; // B
4'b1100: SSD_CATHODES = 8'b01100011; // C
4'b1101: SSD_CATHODES = 8'b10000101; // D
4'b1110: SSD_CATHODES = 8'b01100001; // E
4'b1111: SSD_CATHODES = 8'b01110001; // F
default: SSD_CATHODES = 8'bXXXXXXXX; // default is not needed as we covered all cases
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR4B_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__OR4B_PP_BLACKBOX_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__or4b (
X ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR4B_PP_BLACKBOX_V
|
// -----------------------------------------------------------------------
//
// Copyright 2004 Tommy Thorn - All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, Inc., 53 Temple Place Ste 330,
// Bostom MA 02111-1307, USA; either version 2 of the License, or
// (at your option) any later version; incorporated herein by reference.
//
// -----------------------------------------------------------------------
/*
* Simulate a specific subset of the Altera Shift register
* (lpm_clshift).
*
* Not very ambitious, just the bare minimum.
*/
module arithshiftbidir(distance,
data,
direction,
result);
parameter lpm_type = "LPM_CLSHIFT";
parameter lpm_shifttype = "ARITHMETIC";
parameter lpm_width = 32;
parameter lpm_widthdist = 5;
input wire [lpm_widthdist-1:0] distance;
input wire [lpm_width-1 :0] data;
input wire direction;
output wire [lpm_width-1 :0] result;
assign result = direction ? data >>> distance : data << distance;
endmodule
module test_arithshiftbidir();
reg [31:0] data;
reg [ 4:0] dist;
reg dir;
wire [31:0] resulta, resultl;
arithshiftbidir a(dist, data, dir, resulta);
defparam a.lpm_shifttype = "ARITHMETIC";
initial begin
#0 data = 48; dir = 0; dist = 0;
$monitor("dir %d dist %2d A %8x", dir, dist, resulta);
repeat (2) begin
repeat (32)
#1 dist = dist + 1;
dir = ~dir;
end
end
endmodule |
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
`define ENABLE_VCD
module tb_fmlbrg();
reg clk;
initial clk = 1'b0;
always #5 clk = ~clk;
reg rst;
reg [31:0] wb_adr_i;
reg [31:0] wb_dat_i;
wire [31:0] wb_dat_o;
reg [3:0] wb_sel_i;
reg wb_cyc_i;
reg wb_stb_i;
reg wb_we_i;
wire wb_ack_o;
wire [25:0] fml_adr;
wire fml_stb;
wire fml_we;
reg fml_ack;
wire [7:0] fml_sel;
wire [63:0] fml_dw;
reg [63:0] fml_dr;
reg dcb_stb;
reg [25:0] dcb_adr;
wire [63:0] dcb_dat;
wire dcb_hit;
/* Process FML requests */
reg [1:0] fml_wcount;
reg [1:0] fml_rcount;
initial begin
fml_ack = 1'b0;
fml_wcount = 0;
fml_rcount = 0;
end
always @(posedge clk) begin
if(fml_stb & (fml_wcount == 0) & (fml_rcount == 0)) begin
fml_ack <= 1'b1;
if(fml_we) begin
$display("%t FML W addr %x data %x", $time, fml_adr, fml_dw);
fml_wcount <= 3;
end else begin
fml_dr = 64'hcafebabedeadbeef;
$display("%t FML R addr %x data %x", $time, fml_adr, fml_dr);
fml_rcount <= 3;
end
end else
fml_ack <= 1'b0;
if(fml_wcount != 0) begin
#1 $display("%t FML W continuing %x / %d", $time, fml_dw, fml_wcount);
fml_wcount <= fml_wcount - 1;
end
if(fml_rcount != 0) begin
fml_dr = #1 {24'hdeadbe, 6'd0, fml_rcount, 24'hcafeba, 6'd0, fml_rcount};
$display("%t FML R continuing %x / %d", $time, fml_dr, fml_rcount);
fml_rcount <= fml_rcount - 1;
end
end
fmlbrg dut(
.sys_clk(clk),
.sys_rst(rst),
.wb_adr_i(wb_adr_i),
.wb_cti_i(3'd0),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_sel_i(wb_sel_i),
.wb_cyc_i(wb_cyc_i),
.wb_stb_i(wb_stb_i),
.wb_we_i(wb_we_i),
.wb_ack_o(wb_ack_o),
.fml_adr(fml_adr),
.fml_stb(fml_stb),
.fml_we(fml_we),
.fml_ack(fml_ack),
.fml_sel(fml_sel),
.fml_do(fml_dw),
.fml_di(fml_dr),
.dcb_stb(dcb_stb),
.dcb_adr(dcb_adr),
.dcb_dat(dcb_dat),
.dcb_hit(dcb_hit)
);
task waitclock;
begin
@(posedge clk);
#1;
end
endtask
task wbwrite;
input [31:0] address;
input [31:0] data;
integer i;
begin
wb_adr_i = address;
wb_dat_i = data;
wb_sel_i = 4'hf;
wb_cyc_i = 1'b1;
wb_stb_i = 1'b1;
wb_we_i = 1'b1;
i = 0;
while(~wb_ack_o) begin
i = i+1;
waitclock;
end
waitclock;
$display("WB Write: %x=%x acked in %d clocks", address, data, i);
wb_adr_i = 32'hx;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
end
endtask
task wbread;
input [31:0] address;
integer i;
begin
wb_adr_i = address;
wb_cyc_i = 1'b1;
wb_stb_i = 1'b1;
wb_we_i = 1'b0;
i = 0;
while(~wb_ack_o) begin
i = i+1;
waitclock;
end
$display("WB Read : %x=%x acked in %d clocks", address, wb_dat_o, i);
waitclock;
wb_adr_i = 32'hx;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
end
endtask
always begin
`ifdef ENABLE_VCD
$dumpfile("fmlbrg.vcd");
$dumpvars(0, dut);
`endif
rst = 1'b1;
wb_adr_i = 32'd0;
wb_dat_i = 32'd0;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
dcb_stb = 1'b0;
dcb_adr = 26'd0;
waitclock;
rst = 1'b0;
waitclock;
$display("Testing: read miss");
wbread(26'h0);
$display("Testing: write hit");
wbwrite(26'h0, 32'h12345678);
wbread(26'h0);
$display("Testing: read miss on a dirty line");
wbread(26'h10000);
$display("Testing: read hit");
wbread(26'h10004);
$display("Testing: write miss");
wbwrite(26'h0, 32'habadface);
wbread(26'h0);
wbread(26'h4);
$display("Testing: DCB miss");
dcb_adr = 26'hfebabe;
dcb_stb = 1'b1;
waitclock;
$display("Result: hit=%b dat=%x", dcb_hit, dcb_dat);
$display("Testing: DCB hit");
dcb_adr = 26'h0;
dcb_stb = 1'b1;
waitclock;
$display("Result: hit=%b dat=%x", dcb_hit, dcb_dat);
$finish;
end
endmodule
|
module peripheral_SD(clk , reset , d_in , cs , addr , rd , wr, d_out, sclk, mosi, miso, ss );
input clk;
input rst;
input [15:0]d_in;
input cs;
input [3:0]addr; // 4 LSB from j1_io_addr
input rd;
input wr;
output reg [15:0]d_out;
input reset;
output sclk;
input miso;
output mosi;
output ss;
//------------------------------------ regs and wires-------------------------------
reg [5:0] s; //selector mux_4 and write registers
reg [15:0] datain=0;//---mult_32 input registers
reg enable=0;
wire [15:0] dataout; //mult_32 output Regs
wire done;
//------------------------------------ regs and wires-------------------------------
spi driver ( .clk(clk), .reset(reset), .datain(datain), .en(enable), .dataout(dataout), .done(done), .sclk(sclk), .mosi(mosi), .miso(miso), .ss(ss) );
always @(*) begin//------address_decoder------------------------------
case (addr)
4'h0:begin s = (cs && wr) ? 4'b0001 : 6'b0000 ;end //datain
4'h2:begin s = (cs && wr) ? 4'b0010 : 6'b0000 ;end //en
4'h4:begin s = (cs && rd) ? 4'b0100 : 6'b0000 ;end //done
4'h6:begin s = (cs && rd) ? 4'b1000 : 6'b0000 ;end //dataout
default:begin s = 6'b000000 ; end
endcase
end//------------------address_decoder--------------------------------
always @(negedge clk) begin//-------------------- escritura de registros
datain = (s[0]) ? d_in : datain; //Write Registers
enable = (s[1]) ? d_in[0] : enable; //Write Registers
end//------------------------------------------- escritura de registros
always @(negedge clk) begin//-----------------------mux_2 : multiplexa salidas del periferico
case (s)
4'b0100: d_out[0] = done ;
3'b1000: d_out = dataout[15:0] ;
default: d_out = 0 ;
endcase
end//-----------------------------------------------mux_2
endmodule
|
// nios_solo_mm_interconnect_0_avalon_st_adapter.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module nios_solo_mm_interconnect_0_avalon_st_adapter #(
parameter inBitsPerSymbol = 10,
parameter inUsePackets = 0,
parameter inDataWidth = 10,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 10,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [9:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [9:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 10)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 10)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 10)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
nios_solo_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
//---------------------------------------------------------------------------
//-- Copyright 2015 - 2017 Systems Group, ETH Zurich
//--
//-- This hardware module is free software: you can redistribute it and/or
//-- modify it under the terms of the GNU General Public License as published
//-- by the Free Software Foundation, either version 3 of the License, or
//-- (at your option) any later version.
//--
//-- This program is distributed in the hope that it will be useful,
//-- but WITHOUT ANY WARRANTY; without even the implied warranty of
//-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
//-- GNU General Public License for more details.
//--
//-- You should have received a copy of the GNU General Public License
//-- along with this program. If not, see <http://www.gnu.org/licenses/>.
//---------------------------------------------------------------------------
module rem_decoder #(parameter CHAR_COUNT=16, DELIMITER=0)
(
clk,
rst, //active high
config_valid,
config_chars, // an eight bit character for each checker
config_ranges, // two eight bit characters for each range checker (>=LOW, <LARGE)
config_conds, // one bit to indicate whether the checker should only match if the previous one in line matched
input_valid,
input_last,
input_char,
index_rewind,
output_valid,
output_data, // bitmask for each char and range matcher
output_index, // the sequence number of the character in the string
output_last // high for the last character (delimiter)
);
input clk;
input rst;
input config_valid;
input [CHAR_COUNT*8-1:0] config_chars;
input [(CHAR_COUNT/2)-1:0] config_ranges;
input [CHAR_COUNT-1:0] config_conds;
input input_valid;
input input_last;
input [7:0] input_char;
input index_rewind;
output reg output_valid;
output reg [CHAR_COUNT-1:0] output_data;
output reg [15:0] output_index;
output reg output_last;
reg [15:0] index;
reg in_reg_valid;
reg [7:0] in_reg_char;
reg in_reg_last;
wire [CHAR_COUNT:0] match_bits;
wire [CHAR_COUNT-1:0] intermediary;
assign match_bits[0] = 0;
genvar X;
generate
for (X=0; X < CHAR_COUNT; X=X+2)
begin: gen_charmatch
rem_halfrange #(.HIGH_HALF(0)) match_low (
.clk(clk),
.rst(rst),
.config_valid(config_valid),
.config_char(config_chars[X*8+7:X*8]),
.config_chained(config_conds[X]),
.config_range_en(1'b0),
.input_valid(input_valid),
.input_char(input_char),
.prev_matched(match_bits[X]),
.this_matched(match_bits[X+1]),
.low_smaller(),
.this_smaller(intermediary[X])
);
rem_halfrange #(.HIGH_HALF(1)) match_high (
.clk(clk),
.rst(rst),
.config_valid(config_valid),
.config_char(config_chars[(X+1)*8+7:(X+1)*8]),
.config_chained(config_conds[(X+1)]),
.config_range_en(config_ranges[(X+1)/2]),
.input_valid(input_valid),
.input_char(input_char),
.prev_matched(match_bits[(X+1)]),
.this_matched(match_bits[(X+1)+1]),
.low_smaller(intermediary[X]),
.this_smaller()
);
end
endgenerate
always @(posedge clk)
begin
if (rst) begin
output_valid <= 0;
in_reg_valid <= 0;
in_reg_last <= 0;
index <= 0;
end
else begin
in_reg_valid <= input_valid;
in_reg_char <= input_char;
in_reg_last <= input_last;
if (in_reg_valid) begin
index <= index+1;
//if (in_reg_char==DELIMITER) index <= 0;
if (in_reg_last==1) index <= 0;
end
output_valid <= in_reg_valid;
output_data <= match_bits[CHAR_COUNT:1];
output_last <= in_reg_last;//(in_reg_char==DELIMITER) ? 1 : 0;
output_index <= index;
if (index_rewind==1) begin
index <= 0;
end
end
end
endmodule
|
module alu( input [6:0] ctrl,
input [31:0] A,
input [31:0] B,
input [4:0] SH,
output [31:0] Y,
output Z );
// ctrl [6]: SHIFT SRC (1 - reg, 0 - shamt)
// ctrl[5:4]: SHIFT OP
// ctrl [3]: NEGATE B
// ctrl[2:0]: ALU OP
wire Cin = ctrl[3]; //carry in. Equals 1 when B = NEGATE(B)
wire [31:0] BB; //inverted or not B
wire [31:0] Sum = A + BB + Cin;
wire [31:0] Zero_extend;
mux2 bb_mux( .S(ctrl[3]),
.D0( B),
.D1(~B),
.Y (BB) );
wire [4:0] shamt;
mux2 #(5) shift_in_mux( .S (ctrl[6]),
.D0(SH),
.D1(A[4:0]),
.Y (shamt));
wire[31:0] sh_out;
shifter shifter_unit( .S(ctrl[5:4]),
.N( shamt ),
.A( B ),
.Y( sh_out ) );
assign Zero_extend = {31'b0, Sum[31]};
mux8 out_mux( .S ( ctrl[2:0] ),
.D0( A & BB ),
.D1( A | BB ),
.D2( A ^ BB ),
.D3(~(A | BB) ),
.D4( Sum ),
.D5( 0 ), //mul?
.D6( sh_out ),
.D7( Zero_extend ),
.Y ( Y ) );
assign Z = {Y == 32'b0};
endmodule
//-------------------------------------------------------------------------//
module shifter( input [1:0] S,
input [4:0] N,
input signed [31:0] A,
output [31:0] Y );
//sel[1]: 0 -- logical, 1 -- arithmetic
//sel[0]: 0 -- left, 1 --right
assign Y = S[1] ? (S[0] ? A >>> N : A <<< N) :
(S[0] ? A >> N : A << N);
endmodule
//-------------------------------------------------------------------------//
/*
//-------------------------NORMAL-ADDER------------------------------//
module qqq_sum( input[31:0] A, B,
output[31:0] R,
input Cin );
//assign {Cout, R} = A + B + Cin;
assign R = A + B + Cin;
endmodule
//-------------------------RIPPLE-CARRY-ADDER------------------------------//
module rca_sum( input[31:0] A, B,
output[31:0] R,
input Cin,
output Cout );
wire c0, c1, c2, c3, c4, c5, c6, c7,
c8, c9, c10, c11, c12, c13, c14, c15,
c16, c17, c18, c19, c20, c21, c22, c23,
c24, c25, c26, c27, c28, c29, c30;
full_adder fa0(A[ 0], B[ 0], R[ 0], Cin, c0);
full_adder fa1(A[ 1], B[ 1], R[ 1], c0, c1);
full_adder fa2(A[ 2], B[ 2], R[ 2], c1, c2);
full_adder fa3(A[ 3], B[ 3], R[ 3], c2, c3);
full_adder fa4(A[ 4], B[ 4], R[ 4], c3, c4);
full_adder fa5(A[ 5], B[ 5], R[ 5], c4, c5);
full_adder fa6(A[ 6], B[ 6], R[ 6], c5, c6);
full_adder fa7(A[ 7], B[ 7], R[ 7], c6, c7);
full_adder fa8(A[ 8], B[ 8], R[ 8], c7, c8);
full_adder fa9(A[ 9], B[ 9], R[ 9], c8, c9);
full_adder fa10(A[10], B[10], R[10], c9, c10);
full_adder fa11(A[11], B[11], R[11], c10, c11);
full_adder fa12(A[12], B[12], R[12], c11, c12);
full_adder fa13(A[13], B[13], R[13], c12, c13);
full_adder fa14(A[14], B[14], R[14], c13, c14);
full_adder fa15(A[15], B[15], R[15], c14, c15);
full_adder fa16(A[16], B[16], R[16], c15, c16);
full_adder fa17(A[17], B[17], R[17], c16, c17);
full_adder fa18(A[18], B[18], R[18], c17, c18);
full_adder fa19(A[19], B[19], R[19], c18, c19);
full_adder fa20(A[20], B[20], R[20], c19, c20);
full_adder fa21(A[21], B[21], R[21], c20, c21);
full_adder fa22(A[22], B[22], R[22], c21, c22);
full_adder fa23(A[23], B[23], R[23], c22, c23);
full_adder fa24(A[24], B[24], R[24], c23, c24);
full_adder fa25(A[25], B[25], R[25], c24, c25);
full_adder fa26(A[26], B[26], R[26], c25, c26);
full_adder fa27(A[27], B[27], R[27], c26, c27);
full_adder fa28(A[28], B[28], R[28], c27, c28);
full_adder fa29(A[29], B[29], R[29], c28, c29);
full_adder fa30(A[30], B[30], R[30], c29, c30);
full_adder fa31(A[31], B[31], R[31], c30, Cout);
endmodule
//-------------------------------------------------------------------------//
//--------------------------------------FULL ADDER-------------------------//
module full_adder( input A, B,
output S,
input Cin,
output Cout );
assign S = A ^ B ^ Cin;
assign Cout = (A & B) | (A & Cin) | (B & Cin);
endmodule */ |
/*
Distributed under the MIT license.
Copyright (c) 2017 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author:
* Description:
*
* When the user enters a new character on i_char and strobes 'i_char_stb'
* then the it will be inserted into the buffer
*
*
* Changes: Who? What?
* XX/XX/XXXX XXX XXXX
*/
`timescale 1ps / 1ps
`include "char_defines.v"
module character_buffer #(
parameter CONSOLE_DEPTH = 12,
parameter FONT_WIDTH = 5,
parameter FONT_HEIGHT = 8,
parameter CHAR_IMAGE_WIDTH = 80,
parameter CHAR_IMAGE_HEIGHT = 34,
parameter CHAR_IMAGE_SIZE = CHAR_IMAGE_WIDTH * CHAR_IMAGE_HEIGHT
)(
input clk,
input rst,
input i_alt_func_en,
input i_clear_screen_stb,
input [2:0] i_tab_count,
input i_char_stb,
input [7:0] i_char,
output o_wr_char_rdy,
input i_read_frame_stb,
input i_char_req_en,
output reg o_char_rdy,
output [7:0] o_char,
//When new frame is strobed the address is put back to the beginning of the frame
input i_scroll_en,
input i_scroll_up_stb,
input i_scroll_down_stb
);
//local parameters
localparam IDLE = 0;
localparam PROCESS_NORMAL_CHAR = 1;
localparam PROCESS_BACKSPACE_PREP = 2;
localparam PROCESS_BACKSPACE = 3;
localparam NOM_BLANKS_PREP1 = 4;
localparam NOM_BLANKS_PREP2 = 5;
localparam NOM_BLANKS = 6;
localparam PROCESS_CARRIAGE_RETURN = 7;
localparam PROCESS_TAB = 8;
localparam CLEAR_BUFFER = 9;
localparam CLEAR_LINE = 10;
localparam START_READ_FRAME = 1;
localparam START_READ_FRAME_DELAY = 2;
localparam GET_CHAR = 3;
localparam GET_CHAR_DELAY = 4;
localparam CONSOLE_SIZE = (1 << CONSOLE_DEPTH);
localparam MAX_LINES = CONSOLE_SIZE / CHAR_IMAGE_WIDTH;
//registes/wires
reg [3:0] in_state;
reg [3:0] out_state;
reg r_char_stb;
reg r_bs_line_flag;
//reg [CONSOLE_DEPTH - 1:0] r_write_addr_pos;
reg [CONSOLE_DEPTH :0] r_write_addr_pos;
wire [CONSOLE_DEPTH - 1:0] w_write_addr_pos;
reg [CONSOLE_DEPTH - 1:0] r_write_addr_pos_prev;
reg [CONSOLE_DEPTH - 1:0] r_write_addr_end;
wire [CONSOLE_DEPTH - 1:0] w_write_addr_start;
reg [CONSOLE_DEPTH - 1:0] r_char_line_count;
reg [7:0] r_char;
reg [2:0] r_tab_count;
wire [7:0] w_char;
wire w_buf_full;
wire [CONSOLE_DEPTH - 1: 0] w_read_addr;
reg [CONSOLE_DEPTH - 1: 0] r_read_addr;
reg [CONSOLE_DEPTH - 1: 0] r_read_char_count;
reg [CONSOLE_DEPTH - 1: 0] r_start_frame_addr;
reg [CONSOLE_DEPTH : 0] r_prev_line_addr;
wire [CONSOLE_DEPTH - 1: 0] w_prev_line_addr;
reg [CONSOLE_DEPTH : 0] r_curr_line_addr;
wire [CONSOLE_DEPTH - 1: 0] w_curr_line_addr;
reg [CONSOLE_DEPTH : 0] r_next_line_addr;
wire [CONSOLE_DEPTH - 1: 0] w_next_line_addr;
reg r_dbg_prev_wrap_stb;
reg r_dbg_next_wrap_stb;
reg r_dbg_next_stb;
reg r_dbg_prev_stb;
wire w_in_busy;
wire w_out_busy;
wire w_clear_screen;
wire w_backspace;
reg [3:0] r_font_height_pos;
reg [7:0] r_read_width_pos;
reg r_clear_req;
wire w_scroll_enable;
wire [CONSOLE_DEPTH - 1: 0] w_prev_line_addr_start = (CONSOLE_SIZE - CHAR_IMAGE_WIDTH);
//*************** DEBUG ******************************************************
wire [CONSOLE_DEPTH - 1: 0] w_dbg_char_image_width = CHAR_IMAGE_WIDTH;
wire [CONSOLE_DEPTH - 1: 0] w_dbg_char_image_height = CHAR_IMAGE_HEIGHT;
wire [CONSOLE_DEPTH - 1: 0] w_dbg_char_image_size = CHAR_IMAGE_SIZE;
wire [CONSOLE_DEPTH : 0] w_dbg_console_depth = CONSOLE_SIZE;
wire [CONSOLE_DEPTH - 1: 0] w_dbg_max_lines = MAX_LINES;
//****************************************************************************
assign w_prev_line_addr = r_prev_line_addr;
assign w_curr_line_addr = r_curr_line_addr;
assign w_next_line_addr = r_next_line_addr;
assign w_scroll_enable = (r_char_line_count >= CHAR_IMAGE_HEIGHT);
//assign w_read_addr = r_read_addr;
//submodules
bram #(
.DATA_WIDTH (8 ),
.ADDR_WIDTH (CONSOLE_DEPTH ) //4096 Console Depth
) char_buffer (
.clk (clk ),
.rst (rst ),
.en (1'b1 ),
.we (r_char_stb ),
.write_address (w_write_addr_pos ),
.data_in (r_char ),
.read_address (w_read_addr ),
.data_out (o_char )
);
//asynchronous logic
assign w_in_busy = (in_state != IDLE);
assign o_wr_char_rdy = !w_in_busy;
assign w_out_busy = (out_state != IDLE);
assign w_buf_full = (w_write_addr_pos == r_write_addr_end);
assign w_write_addr_start = r_write_addr_end + 1;
//assign w_read_addr = r_read_addr;
assign w_read_addr = w_backspace ? w_write_addr_pos : r_read_addr;
assign w_write_addr_pos = r_write_addr_pos;
assign w_clear_screen = ((in_state == CLEAR_BUFFER) ||
(in_state == CLEAR_LINE));
assign w_backspace = ((in_state == PROCESS_BACKSPACE) ||
(in_state == NOM_BLANKS) ||
(in_state == NOM_BLANKS_PREP1) ||
(in_state == NOM_BLANKS_PREP2));
//synchronous logic
//Incomming state machine
always @ (posedge clk) begin
r_char_stb <= 0;
r_dbg_prev_wrap_stb <= 0;
r_dbg_next_wrap_stb <= 0;
r_dbg_next_stb <= 0;
r_dbg_prev_stb <= 0;
if (rst) begin
r_char <= 0;
r_write_addr_pos <= 0;
r_write_addr_pos_prev <= 0;
r_write_addr_end <= (CONSOLE_SIZE - 1);
r_tab_count <= 0;
//r_prev_line_addr <= (1 << CONSOLE_DEPTH) - CHAR_IMAGE_WIDTH;
r_prev_line_addr <= w_prev_line_addr_start;
r_curr_line_addr <= 0;
r_next_line_addr <= CHAR_IMAGE_WIDTH;
in_state <= CLEAR_BUFFER;
r_clear_req <= 0;
r_char_line_count <= 0;
r_bs_line_flag <= 0;
end
else begin
case (in_state)
IDLE: begin
r_bs_line_flag <= 0;
if (r_clear_req && (out_state == IDLE)) begin
r_clear_req <= 0;
r_char_stb <= 1;
r_char <= 0;
r_write_addr_pos <= 0;
r_write_addr_end <= ((CONSOLE_SIZE) - 1);
in_state <= CLEAR_BUFFER;
r_char_line_count <= 0;
end
else if (i_char_stb) begin
if (i_alt_func_en) begin
//Allows user to put in special characters like hearts and clovers
r_tab_count <= 0;
r_char_stb <= 1;
r_char <= i_char;
in_state <= PROCESS_NORMAL_CHAR;
end
else begin
case (i_char)
`NUL: begin //NULL Character
end
`SOH: begin //Start of Header
end
`STX: begin //Start of Text
end
`ETX: begin //End of Text
end
`EOT: begin //End of Transmission
end
`ENQ: begin //Enquiry
end
`ACK: begin //Ack
end
`BEL: begin //Bing!
end
`BS : begin //Backspace
r_char <= 0;
//r_char_stb <= 1;
in_state <= PROCESS_BACKSPACE_PREP;
end
`HT : begin //Horizontal Tab
r_char <= 0;
r_char_stb <= 1;
in_state <= PROCESS_TAB;
end
`LF : begin //Line Feed
//Simplify this, only carriage return (goes to new line too)
r_char <= 0;
r_char_stb <= 1;
in_state <= PROCESS_CARRIAGE_RETURN;
end
`VT : begin //Vertical Tab
end
`FF : begin //Form Feed
end
`CR : begin //Carriage Return
r_char <= 0;
r_char_stb <= 1;
in_state <= PROCESS_CARRIAGE_RETURN;
end
`SO : begin //Shift Out
end
`SI : begin //Shift In
end
`DLE: begin //Data Link Escape
end
`DC1: begin //Device Control 1
end
`DC2: begin //Device Control 2
end
`DC3: begin //Device Control 3
end
`DC4: begin //Device Control 4
end
`NAK: begin //Nack
end
`SYN: begin //Sync
end
`ETB: begin //End of Transmission Block
end
`CAN: begin //Cancel
end
`EM : begin //End of Medium
end
`SUB: begin //Substitue
end
`ESC: begin //Escape
end
`FS : begin //File Seperator
end
`GS : begin //Group Seperator
end
`RS : begin //Record Seperator
end
`US : begin //Unit Seperator
end
`DEL: begin //Delete
end
default: begin
//Normal Character to put into the buffer
r_char <= i_char;
r_char_stb <= 1;
in_state <= PROCESS_NORMAL_CHAR;
end
endcase
end
end
end
PROCESS_NORMAL_CHAR: begin
if (w_buf_full) begin
r_write_addr_end <= r_write_addr_end + 1;
end
r_write_addr_pos <= r_write_addr_pos + 1;
in_state <= IDLE;
end
PROCESS_BACKSPACE_PREP: begin
if (!w_out_busy) begin
//in_state <= PROCESS_BACKSPACE;
in_state <= NOM_BLANKS_PREP1;
end
end
PROCESS_BACKSPACE: begin
//if (w_write_addr_pos != w_write_addr_start) begin
if (r_bs_line_flag && (w_write_addr_pos == w_curr_line_addr)) begin
in_state <= IDLE;
end
else if (r_write_addr_pos != w_write_addr_start) begin
r_write_addr_pos <= r_write_addr_pos - 1;
in_state <= NOM_BLANKS_PREP1;
end
else begin
in_state <= IDLE;
end
end
NOM_BLANKS_PREP1: begin
in_state <= NOM_BLANKS_PREP2;
end
NOM_BLANKS_PREP2: begin
in_state <= NOM_BLANKS;
end
NOM_BLANKS: begin
if (o_char == 0) begin
in_state <= PROCESS_BACKSPACE;
end
else begin
r_char <= 0;
r_char_stb <= 1;
in_state <= IDLE;
end
end
PROCESS_CARRIAGE_RETURN: begin
if (r_write_addr_pos < r_next_line_addr) begin
if (r_char_stb) begin
r_write_addr_pos <= r_write_addr_pos + 1;
end
r_char <= 0;
r_char_stb <= 1;
end
else begin
//in_state <= IDLE;
in_state <= CLEAR_LINE;
end
end
PROCESS_TAB: begin
if (r_tab_count < i_tab_count) begin
r_tab_count <= r_tab_count + 1;
r_char <= 0;
r_char_stb <= 1;
if (w_buf_full) begin
r_write_addr_end <= r_write_addr_end + 1;
end
r_write_addr_pos <= r_write_addr_pos + 1;
end
else begin
in_state <= IDLE;
end
end
CLEAR_BUFFER: begin
r_prev_line_addr <= w_prev_line_addr_start;
r_curr_line_addr <= 0;
r_next_line_addr <= CHAR_IMAGE_WIDTH;
if (!w_buf_full) begin
r_char_stb <= 1;
if (r_char_stb) begin
r_char <= 0;
r_write_addr_pos <= r_write_addr_pos + 1;
//r_write_addr_end <= ((1 << CONSOLE_DEPTH) - 1);
end
end
else begin
r_char <= 0;
r_write_addr_pos <= 0;
r_write_addr_end <= ((CONSOLE_SIZE) - 1);
r_tab_count <= 0;
//r_prev_line_addr <= {1'b0, (1 << CONSOLE_DEPTH) - CHAR_IMAGE_WIDTH};
in_state <= IDLE;
end
end
default: begin
in_state <= IDLE;
end
CLEAR_LINE: begin
if (r_write_addr_pos < r_next_line_addr) begin
if (r_char_stb) begin
r_write_addr_pos <= r_write_addr_pos + 1;
end
if (w_buf_full) begin
r_write_addr_end <= r_write_addr_end + 1;
end
r_char <= 0;
r_char_stb <= 1;
end
else begin
r_write_addr_pos <= r_curr_line_addr;
in_state <= IDLE;
end
end
endcase
if (!w_clear_screen) begin
//Move to next line
if (r_write_addr_pos >= r_next_line_addr) begin
r_dbg_next_stb <= 1;
if (r_char_line_count < MAX_LINES) begin
r_char_line_count <= r_char_line_count + 1;
end
$display("Move to next line");
if ((r_write_addr_pos > CHAR_IMAGE_WIDTH) &&
(r_prev_line_addr > CONSOLE_SIZE)) begin
r_dbg_prev_wrap_stb <= 1;
r_prev_line_addr <= r_prev_line_addr + (CHAR_IMAGE_WIDTH - CONSOLE_SIZE);
end
else begin
r_prev_line_addr <= r_prev_line_addr + CHAR_IMAGE_WIDTH;
end
if ((r_curr_line_addr > CONSOLE_SIZE) &&
(r_next_line_addr > CONSOLE_SIZE)) begin
r_curr_line_addr <= r_curr_line_addr + (CHAR_IMAGE_WIDTH - CONSOLE_SIZE);
r_next_line_addr <= r_next_line_addr + (CHAR_IMAGE_WIDTH - CONSOLE_SIZE);
r_write_addr_pos[CONSOLE_DEPTH] <= 0;
r_dbg_next_wrap_stb <= 1;
end
else begin
r_next_line_addr <= r_next_line_addr + CHAR_IMAGE_WIDTH;
r_curr_line_addr <= r_curr_line_addr + CHAR_IMAGE_WIDTH;
end
end
//Move to previous line
else if (w_backspace && (r_write_addr_pos < r_curr_line_addr)) begin
//else if (w_backspace && (w_write_addr_pos < w_curr_line_addr)) begin
r_bs_line_flag <= 1;
if (r_char_line_count > 0) begin
r_char_line_count <= r_char_line_count - 1;
end
if (r_prev_line_addr < CHAR_IMAGE_WIDTH) begin
r_prev_line_addr <= r_prev_line_addr + (CONSOLE_SIZE - CHAR_IMAGE_WIDTH);
end
else begin
r_prev_line_addr <= r_prev_line_addr - CHAR_IMAGE_WIDTH;
end
if (r_curr_line_addr < (2 * CHAR_IMAGE_WIDTH)) begin
//r_curr_line_addr <= {1'b1, w_prev_line_addr};
//r_curr_line_addr <= r_prev_line_addr;
r_curr_line_addr <= r_curr_line_addr + (CONSOLE_SIZE - CHAR_IMAGE_WIDTH);
r_write_addr_pos <= r_write_addr_pos + CONSOLE_SIZE;
end
else begin
r_curr_line_addr <= r_prev_line_addr;
end
if (r_next_line_addr < (3 * CHAR_IMAGE_WIDTH)) begin
//r_next_line_addr <= {1'b1, w_curr_line_addr};
r_next_line_addr <= r_next_line_addr + (CONSOLE_SIZE - CHAR_IMAGE_WIDTH);
end
else begin
r_next_line_addr <= r_curr_line_addr;
end
end
end
if (i_clear_screen_stb) begin
r_clear_req <= 1;
end
end
end
//Outgoing state machine
always @ (posedge clk) begin
o_char_rdy <= 0;
if (rst) begin
r_read_addr <= 0;
r_read_char_count <= 0;
r_read_width_pos <= 0;
r_start_frame_addr <= 0;
out_state <= IDLE;
r_font_height_pos <= 0;
o_char_rdy <= 0;
//w_scroll_enable <= 0;
end
else begin
case (out_state)
IDLE: begin
o_char_rdy <= 0;
r_font_height_pos <= 0;
if (i_read_frame_stb) begin
out_state <= START_READ_FRAME;
end
end
START_READ_FRAME: begin
o_char_rdy <= 0;
r_font_height_pos <= 0;
if (!w_in_busy) begin
r_read_char_count <= 0;
//Don't start outputting the data until the in state is idle, otherwise we may get corrupted data
r_read_addr <= r_start_frame_addr;
out_state <= START_READ_FRAME_DELAY;
end
end
START_READ_FRAME_DELAY: begin
out_state <= GET_CHAR;
end
GET_CHAR: begin
if (i_char_req_en) begin
o_char_rdy <= 1;
if (r_read_width_pos < (CHAR_IMAGE_WIDTH - 1)) begin
//Go to the next character positoin
r_read_width_pos <= r_read_width_pos + 1;
r_read_addr <= r_read_addr + 1;
end
else begin
r_read_width_pos <= 0;
//if (r_font_height_pos < (FONT_HEIGHT - 1)) begin
if (r_font_height_pos < (FONT_HEIGHT - 1)) begin
//Go back to the beginning of the current line
r_font_height_pos <= r_font_height_pos + 1;
r_read_addr <= r_read_addr - (CHAR_IMAGE_WIDTH - 1);
end
else begin
//Go to the next character line
r_read_addr <= r_read_addr + 1;
r_font_height_pos <= 0;
r_read_char_count <= r_read_char_count + CHAR_IMAGE_WIDTH;
end
end
out_state <= GET_CHAR_DELAY;
end
end
GET_CHAR_DELAY: begin
if (r_read_char_count < CHAR_IMAGE_SIZE) begin
out_state <= GET_CHAR;
end
else begin
out_state <= IDLE;
end
end
default: begin
end
endcase
if (in_state == CLEAR_BUFFER) begin
r_start_frame_addr <= r_curr_line_addr;
end
if (w_scroll_enable) begin
r_start_frame_addr <= (w_next_line_addr - CHAR_IMAGE_SIZE);
end
if (i_read_frame_stb) begin
out_state <= START_READ_FRAME;
end
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
//
// This file is part of the N64 RGB/YPbPr DAC project.
//
// Copyright (C) 2015-2021 by Peter Bartmann <[email protected]>
//
// N64 RGB/YPbPr DAC is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//////////////////////////////////////////////////////////////////////////////////
//
// Company: Circuit-Board.de
// Engineer: borti4938
//
// Module Name: n64a_vdemux
// Project Name: N64 Advanced RGB/YPbPr DAC Mod
// Target Devices: Cyclone IV and Cyclone 10 LP devices
// Tool versions: Altera Quartus Prime
// Description: demux the video data from the input data stream
//
// Dependencies: vh/n64a_params.vh
//
//////////////////////////////////////////////////////////////////////////////////
module n64a_vdemux(
VCLK,
nVDSYNC,
nRST,
VD_i,
demuxparams_i,
vdata_valid_0,
vdata_r_sy_0,
vdata_valid_1,
vdata_r_1
);
`include "vh/n64adv_vparams.vh"
input VCLK;
input nVDSYNC;
input nRST;
input [color_width_i-1:0] VD_i;
input [ 2:0] demuxparams_i;
output reg vdata_valid_0 = 1'b0;
output [`VDATA_I_SY_SLICE] vdata_r_sy_0;
output reg vdata_valid_1 = 1'b0;
output reg [`VDATA_I_FU_SLICE] vdata_r_1 = {vdata_width_i{1'b0}}; // (unpacked array types in ports requires system verilog)
// unpack demux info
wire palmode = demuxparams_i[ 2];
wire ndo_deblur = demuxparams_i[ 1];
wire n16bit_mode = demuxparams_i[ 0];
wire posedge_nCSYNC = !vdata_r_0[3*color_width_i] & VD_i[0];
// start of rtl
reg [1:0] data_cnt = 2'b00;
reg nblank_rgb = 1'b1;
reg [`VDATA_I_FU_SLICE] vdata_r_0 = {vdata_width_i{1'b0}}; // buffer for sync, red, green and blue
always @(posedge VCLK or negedge nRST) // data register management
if (!nRST)
data_cnt <= 2'b00;
else begin
if (!nVDSYNC)
data_cnt <= 2'b01; // reset data counter
else
data_cnt <= data_cnt + 1'b1; // increment data counter
end
always @(posedge VCLK or negedge nRST)
if (!nRST) begin
nblank_rgb <= 1'b1;
end else if (!nVDSYNC) begin
if (ndo_deblur) begin
nblank_rgb <= 1'b1;
end else begin
if(posedge_nCSYNC) // posedge nCSYNC -> reset blanking
nblank_rgb <= palmode;
else
nblank_rgb <= ~nblank_rgb;
end
end
always @(posedge VCLK or negedge nRST) // data register management
if (!nRST) begin
vdata_valid_0 <= 1'b0;
vdata_r_0 <= {vdata_width_i{1'b0}};
vdata_valid_1 <= 1'b0;
vdata_r_1 <= {vdata_width_i{1'b0}};
end else begin
vdata_valid_0 <= 1'b0;
vdata_valid_1 <= 1'b0;
if (!nVDSYNC) begin
vdata_valid_1 <= 1'b1; // set also valid flag for
// shift data to output registers
vdata_r_1[`VDATA_I_SY_SLICE] <= vdata_r_0[`VDATA_I_SY_SLICE];
if (nblank_rgb) // deblur active: pass RGB only if not blanked
vdata_r_1[`VDATA_I_CO_SLICE] <= vdata_r_0[`VDATA_I_CO_SLICE];
// get new sync data
vdata_valid_0 <= 1'b1;
vdata_r_0[`VDATA_I_SY_SLICE] <= VD_i[3:0];
end else begin
// demux of RGB
case(data_cnt)
2'b01: vdata_r_0[`VDATA_I_RE_SLICE] <= n16bit_mode ? VD_i : {VD_i[6:2], 2'b00};
2'b10: vdata_r_0[`VDATA_I_GR_SLICE] <= n16bit_mode ? VD_i : {VD_i[6:1], 1'b0};
2'b11: vdata_r_0[`VDATA_I_BL_SLICE] <= n16bit_mode ? VD_i : {VD_i[6:2], 2'b00};
endcase
end
end
assign vdata_r_sy_0 = vdata_r_0[`VDATA_I_SY_SLICE];
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O31AI_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__O31AI_FUNCTIONAL_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__o31ai (
Y ,
A1,
A2,
A3,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
nand nand0 (nand0_out_Y, B1, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O31AI_FUNCTIONAL_V |
module ultrasonic_control (
input clk ,
input enable ,
input signal ,
output reg start ,
output [15:0] value
) ;
reg [2:0] state ;
reg enableClk ;
reg rst_clk_n ;
reg rst_ult_n ;
wire [31:0] clkNumber ;
wire done ;
// Definición de estados
localparam S0 = 3'b000 ;
localparam S1 = 3'b001 ;
localparam S2 = 3'b010 ;
localparam S3 = 3'b011 ;
always @ ( negedge clk )
if ( enable )
case ( state )
S0:
state <= S1 ;
S1:
if ( 1_200 == clkNumber )
state <= S2 ;
else
state <= S1 ;
S2:
if ( 25_000_000 == clkNumber )
state <= S0 ;
else
state <= S2 ;
default:
state <= S0 ;
endcase
else
state <= S0 ;
// Logica de estados
always @ ( posedge clk)
case ( state )
S0: begin
start <= 0 ;
rst_clk_n <= 0 ;
rst_ult_n <= 0 ;
enableClk <= 0 ;
end S1: begin
start <= 1 ;
rst_clk_n <= 1 ;
rst_ult_n <= 1 ;
enableClk <= 1 ;
end S2: begin
start <= 0 ;
rst_clk_n <= 1 ;
rst_ult_n <= 1 ;
enableClk <= 1 ;
end default: begin
start <= 0 ;
rst_clk_n <= 0 ;
rst_ult_n <= 0 ;
enableClk <= 0 ;
end
endcase
// Modulos instanciados
clk_counter medidorDeTiempo (
.clk (clk) ,
.enable (enableClk) ,
.rst_n (rst_clk_n) ,
.clkNumber(clkNumber)
) ;
ultrasonic modulo (
.clk (clk) ,
.signal (signal) ,
.rst_n (rst_ult_n) ,
.value (value) ,
.done (done)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:48:52 12/01/2014
// Design Name:
// Module Name: ALUborrar
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ALUNeuralNetwork#(parameter Width = 32,ConLimitador=0, Magnitud = 9, Precision = 22, Signo = 1, A00= 0,
A01= 1, A02 = 2, A03 = 3, A04 = 4, A05 = 5, A06 = 6, A07 = 7, A08 = 8, A09 = 9,
A10= 10, A11= 11, A12 = 12, A13 = 13, A14 = 14, A15 = 15, A16 = 16, A17 = 17, A18 = 18, A19 = 19,
A20= 20, A21= 21,A22 = 22, A23 = 23, A24 = 24, A25 = 25, A26 = 26, A27 = 27, A28 = 28, A29 = 29,
A30 = 30, M01= 1, M02 = 2, M03 = 3, M04 = 4, M05 = 5, M06 = 6, M07 = 7, M08 = 8, M09 = 9, M10= 10,
M11= 11, M12 = 12, M13 = 13, M14 = 14, M15 = 15, M16 = 16, M17 = 17, M18 = 18, M19 = 19, M20= 20,
M21= 21,M22 = 22, M23 = 23, M24 = 24, M25 = 25, M26 = 26, M27 = 27, M28 = 28, M29 = 29, M30 = 30,
B01= 1, B02 = 2, B03 = 3, B04 = 4, B05 = 5, B06 = 6, B07 = 7, B08 = 8, B09 = 9,
B10= 10, B11= 11, B12 = 12, B13 = 13, B14 = 14, B15 = 15, B16 = 16, B17 = 17, B18 = 18, B19 = 19,
B20= 20, B21= 21,B22 = 22, B23 = 23, B24 = 24, B25 = 25, B26 = 26, B27 = 27, B28 = 28, B29 = 29,
B30 = 30)
(CLK,reset,EnableLoadCoeff, EnableMulX,EnableRegOutMultCoeffX,EnableFuctAct,EnableRegActFunc,EnableMulY,
EnableRegDesplazamiento,EnableSum,InDato,Acumulador,SELCoeffX,SELCoeffY,SELOffset,Coeff00,Coeff01,Coeff02,Coeff03,Coeff04,Coeff05,
Coeff06,Coeff07,Coeff08,Coeff09,Coeff10,Coeff11,Coeff12,Coeff13,Coeff14,Coeff15,Coeff16,Coeff17,Coeff18,
Coeff19,Offset,Error,OutDato,Y0,Y1,Y2,Y3,Y4,Y5,Y6,Y7,Y8,Y9);
input CLK, reset, EnableLoadCoeff,EnableRegOutMultCoeffX,EnableMulX,EnableFuctAct,EnableMulY,
EnableRegActFunc,EnableRegDesplazamiento,EnableSum;
input [3:0] SELCoeffX,SELCoeffY;
input SELOffset; // Si SELOffset es 1, es una suma con el offset, sino es una suma con el resultado
// de multcoeffY
input signed [Width-1:0] InDato,Acumulador,Coeff00,Coeff01,Coeff02,Coeff03,Coeff04,Coeff05,
Coeff06,Coeff07,Coeff08,Coeff09,Coeff10,Coeff11,Coeff12,Coeff13,Coeff14,Coeff15,Coeff16,Coeff17,
Coeff18,Coeff19,Offset;
output Error;
output signed [Width-1:0] OutDato,Y0,Y1,Y2,Y3,Y4,Y5,Y6,Y7,Y8,Y9;
wire signed [Width-1:0] OutMultCoeffX,OutRegisterMultCoeffX,OutActFunct,OutRegActFunct,OutCoeffY,
OutCoeffX,OutMultCoeffY,OffsetOut, OutMuXOffsetOrMultCoeffY;
wire Error1,Error2,Error3,Error4;
RegistroWithMuxInput #(.Width(Width)) RegistroWithMuxInputCopia (
.CLK(CLK), //************************************
.EnableRegisterIn(EnableLoadCoeff), //************************************
.reset(reset), //************************************
.SELCoeffX(SELCoeffX), //************************************
.SELCoeffY(SELCoeffY),//************************************
.Coeff00(Coeff00), //************************************
.Coeff01(Coeff01), //************************************
.Coeff02(Coeff02), //************************************
.Coeff03(Coeff03), //************************************
.Coeff04(Coeff04), //************************************
.Coeff05(Coeff05), //************************************
.Coeff06(Coeff06), //************************************
.Coeff07(Coeff07), //************************************
.Coeff08(Coeff08), //************************************
.Coeff09(Coeff09), //************************************
.Coeff10(Coeff10), //************************************
.Coeff11(Coeff11), //************************************
.Coeff12(Coeff12), //************************************
.Coeff13(Coeff13), //************************************
.Coeff14(Coeff14), //************************************
.Coeff15(Coeff15), //************************************
.Coeff16(Coeff16), //************************************
.Coeff17(Coeff17), //************************************
.Coeff18(Coeff18), //************************************
.Coeff19(Coeff19), //************************************
.OffsetIn(Offset), //************************************
.OutCoeffX(OutCoeffX), //************************************
.OutCoeffY(OutCoeffY), //************************************
.OffsetOut(OffsetOut) //************************************
);
multiplicadorPuntoFijo #(.Width(Width), .Magnitud(Magnitud), .Precision(Precision),.Signo(Signo))
multiplicadorPuntoFijoCoeficienteX (
.EnableMul(EnableMulX), //************************************
.In(InDato), //************************************
.Coeff(OutCoeffX), //************************************
.OutMul(OutMultCoeffX), //************************************
.Error(Error1) //************************************
);
Registro #(.Width(Width)) RegistroOutMultCoeffX (
.CLK(CLK), //************************************
.reset(reset), //************************************
.Enable(EnableRegOutMultCoeffX), //************************************
.Entrada(OutMultCoeffX), //************************************
.Salida(OutRegisterMultCoeffX) //************************************
);
FuncionActivacion #(.Width(Width),.ConLimitador(ConLimitador),.Magnitud(Magnitud), .Precision(Precision), .Signo(Signo), .A00(A00),
.A01(A01),.A02(A02),.A03(A03),.A04(A04),.A05(A05),.A06(A06),.A07(A07),.A08(A08),.A09(A09),
.A10(A10),.A11(A11),.A12(A12),.A13(A13),.A14(A14),.A15(A15),.A16(A16),.A17(A17),.A18(A18),.A19(A19),
.A20(A20),.A21(A21),.A22(A22),.A23(A23),.A24(A24),.A25(A25),.A26(A26),.A27(A27),.A28(A28),.A29(A29),
.A30(A30),
.M01(M01),.M02(M02),.M03(M03),.M04(M04),.M05(M05),.M06(M06),.M07(M07),.M08(M08),.M09(M09),
.M10(M10),.M11(M11),.M12(M12),.M13(M13),.M14(M14),.M15(M15),.M16(M16),.M17(M17),.M18(M18),.M19(M19),
.M20(M20),.M21(M21),.M22(M22),.M23(M23),.M24(M24),.M25(M25),.M26(M26),.M27(M27),.M28(M28),.M29(M29),
.M30(M30),
.B01(B01),.B02(B02),.B03(B03),.B04(B04),.B05(B05),.B06(B06),.B07(B07),.B08(B08),.B09(B09),
.B10(B10),.B11(B11),.B12(B12),.B13(B13),.B14(B14),.B15(B15),.B16(B16),.B17(B17),.B18(B18),.B19(B19),
.B20(B20),.B21(B21),.B22(B22),.B23(B23),.B24(B24),.B25(B25),.B26(B26),.B27(B27),.B28(B28),.B29(B29),
.B30(B30))
FuncionActivacionSigmoidal (
.Entrada(OutRegisterMultCoeffX), //************************************
.Enable(EnableFuctAct), //************************************
.Error(Error2), //************************************
.Salida(OutActFunct) //************************************
);
//assign OutActFunct=OutRegisterMultCoeffX; // Borrar
Registro #(.Width(Width)) RegistroOutActFunct (
.CLK(CLK), //************************************
.reset(reset), //************************************
.Enable(EnableRegActFunc), //************************************
.Entrada(OutActFunct), //OutActFunct //************************************
.Salida(OutRegActFunct) //************************************
);
multiplicadorPuntoFijo #(.Width(Width), .Magnitud(Magnitud), .Precision(Precision),.Signo(Signo))
multiplicadorPuntoFijoCoeffY (
.EnableMul(EnableMulY), //************************************
.In(OutRegActFunct), //************************************
.Coeff(OutCoeffY), //************************************
.OutMul(OutMultCoeffY), //************************************
.Error(Error3) //************************************
);
Registrodesplazamiento #(.Width(Width)) RegistrodesplazamientoCopia (
.CLK(CLK), //************************************
.reset(reset), //************************************
.Enable(EnableRegDesplazamiento), //************************************
.Indato(OutMultCoeffY), //************************************
.Y0(Y0), //************************************
.Y1(Y1), //************************************
.Y2(Y2), //************************************
.Y3(Y3), //************************************
.Y4(Y4), //************************************
.Y5(Y5), //************************************
.Y6(Y6), //************************************
.Y7(Y7), //************************************
.Y8(Y8), //************************************
.Y9(Y9) //************************************
);
assign OutMuXOffsetOrMultCoeffY = SELOffset ? OffsetOut : OutMultCoeffY; //Mux selector de offset
sumadorPuntoFijo #(.Width(Width), .Magnitud(Magnitud), .Precision(Precision),.Signo(Signo))
sumadorPuntoFijocopia (
.EnableSum(EnableSum), //************************************
.In(OutMuXOffsetOrMultCoeffY), //************************************
.Acumulador(Acumulador), //************************************
.OutSum(OutDato), //************************************
.Error(Error4) //************************************
);
assign Error = Error1 | Error2 | Error3 | Error4;
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module nios_mem_if_ddr2_emif_0_p0_iss_probe (
probe_input
);
parameter WIDTH = 1;
parameter ID_NAME = "PROB";
input [WIDTH-1:0] probe_input;
altsource_probe iss_probe_inst (
.probe (probe_input),
.source ()
// synopsys translate_off
,
.clr (),
.ena (),
.ir_in (),
.ir_out (),
.jtag_state_cdr (),
.jtag_state_cir (),
.jtag_state_e1dr (),
.jtag_state_sdr (),
.jtag_state_tlr (),
.jtag_state_udr (),
.jtag_state_uir (),
.raw_tck (),
.source_clk (),
.source_ena (),
.tdi (),
.tdo (),
.usr1 ()
// synopsys translate_on
);
defparam
iss_probe_inst.enable_metastability = "NO",
iss_probe_inst.instance_id = ID_NAME,
iss_probe_inst.probe_width = WIDTH,
iss_probe_inst.sld_auto_instance_index = "YES",
iss_probe_inst.sld_instance_index = 0,
iss_probe_inst.source_initial_value = "0",
iss_probe_inst.source_width = 0;
endmodule
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
// Guarded parameter for num_cks < 1 (which is bad usage - see warning in top-level file)
parameter NUM_CKS_1 = (num_cks > 0) ? (num_cks - 1) : 0;
//------------------------------------------------------------------------------
// SHARED CODE
//------------------------------------------------------------------------------
`ifdef OVL_SHARED_CODE
reg [NUM_CKS_1:0] monitor;
wire [NUM_CKS_1:0] monitor_1 = (monitor << 1);
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
monitor <= {num_cks{1'b0}};
end
else begin
monitor <= (monitor_1 | start_event);
end
end
`endif
//------------------------------------------------------------------------------
// ASSERTION
//------------------------------------------------------------------------------
`ifdef OVL_ASSERT_ON
// 2-STATE
// =======
wire fire_2state_1, fire_2state_2, fire_2state_3;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_2state_1) begin
ovl_error_t(`OVL_FIRE_2STATE,"Illegal overlapping condition of start event is detected");
end
if (fire_2state_2) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expresson is asserted without a corresponding start_event");
end
if (fire_2state_3) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression is not asserted after elapse of num_cks cycles from start event");
end
end
end
assign fire_2state_1 = ((check_overlapping == 0) && (monitor_1 != {num_cks{1'b0}}) && start_event); // new start_event can occur in cycle test_expr is checked
assign fire_2state_2 = ((check_missing_start != 0) && ~monitor[NUM_CKS_1] && test_expr);
assign fire_2state_3 = (monitor[NUM_CKS_1] && ~test_expr);
// X-CHECK
// =======
`ifdef OVL_XCHECK_OFF
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
`else
reg fire_xcheck_1, fire_xcheck_2;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_xcheck_1) begin
ovl_error_t(`OVL_FIRE_XCHECK,"start_event contains X or Z");
end
if (fire_xcheck_2) begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
end
end
wire valid_start_event = ((start_event ^ start_event) == 1'b0);
wire valid_test_expr = ((test_expr ^ test_expr) == 1'b0);
always @ (valid_start_event) begin
if (valid_start_event) begin
fire_xcheck_1 = 1'b0;
end
else begin
fire_xcheck_1 = 1'b1;
end
end
always @ (valid_test_expr or monitor) begin
if (valid_test_expr || ~((check_missing_start==1) || monitor[NUM_CKS_1])) begin
fire_xcheck_2 = 1'b0;
end
else begin
fire_xcheck_2 = 1'b1; // test_expr X when check_missing_start or monitor[num_cks-1]
end
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`endif // OVL_ASSERT_ON
//------------------------------------------------------------------------------
// COVERAGE
//------------------------------------------------------------------------------
`ifdef OVL_COVER_ON
wire fire_cover_1, fire_cover_2;
always @ (posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_cover_1) begin
ovl_cover_t("start_event covered"); // basic
end
if (fire_cover_2) begin
ovl_cover_t("overlapping_start_events covered"); // corner
end
end
end
assign fire_cover_1 = ((OVL_COVER_BASIC_ON > 0) && (start_event == 1'b1));
assign fire_cover_2 = ((OVL_COVER_CORNER_ON > 0) && ((check_overlapping==1) && (monitor_1 != {num_cks{1'b0}}) && start_event));
`endif // OVL_COVER_ON
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2012 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
Require Import Le Gt Minus Bool.
Require Setoid.
Set Implicit Arguments.
(******************************************************************)
(** * Basics: definition of polymorphic lists and some operations *)
(******************************************************************)
(** The definition of [list] is now in [Init/Datatypes],
as well as the definitions of [length] and [app] *)
Open Scope list_scope.
Section Lists.
Variable A : Type.
(** Head and tail *)
Definition hd (default:A) (l:list A) :=
match l with
| nil => default
| x :: _ => x
end.
Definition hd_error (l:list A) :=
match l with
| nil => error
| x :: _ => value x
end.
Definition tl (l:list A) :=
match l with
| nil => nil
| a :: m => m
end.
(** The [In] predicate *)
Fixpoint In (a:A) (l:list A) : Prop :=
match l with
| nil => False
| b :: m => b = a \/ In a m
end.
End Lists.
(** Standard notations for lists.
In a special module to avoid conflict. *)
Module ListNotations.
Notation " [ ] " := nil : list_scope.
Notation " [ x ] " := (cons x nil) : list_scope.
Notation " [ x ; .. ; y ] " := (cons x .. (cons y nil) ..) : list_scope.
End ListNotations.
Import ListNotations.
(** ** Facts about lists *)
Section Facts.
Variable A : Type.
(** *** Genereric facts *)
(** Discrimination *)
Theorem nil_cons : forall (x:A) (l:list A), [] <> x :: l.
Proof.
intros; discriminate.
Qed.
(** Destruction *)
Theorem destruct_list : forall l : list A, {x:A & {tl:list A | l = x::tl}}+{l = []}.
Proof.
induction l as [|a tail].
right; reflexivity.
left; exists a, tail; reflexivity.
Qed.
(** *** Head and tail *)
Theorem hd_error_nil : hd_error (@nil A) = None.
Proof.
simpl; reflexivity.
Qed.
Theorem hd_error_cons : forall (l : list A) (x : A), hd_error (x::l) = Some x.
Proof.
intros; simpl; reflexivity.
Qed.
(************************)
(** *** Facts about [In] *)
(************************)
(** Characterization of [In] *)
Theorem in_eq : forall (a:A) (l:list A), In a (a :: l).
Proof.
simpl; auto.
Qed.
Theorem in_cons : forall (a b:A) (l:list A), In b l -> In b (a :: l).
Proof.
simpl; auto.
Qed.
Theorem in_nil : forall a:A, ~ In a [].
Proof.
unfold not; intros a H; inversion_clear H.
Qed.
Theorem in_split : forall x (l:list A), In x l -> exists l1 l2, l = l1++x::l2.
Proof.
induction l; simpl; destruct 1.
subst a; auto.
exists [], l; auto.
destruct (IHl H) as (l1,(l2,H0)).
exists (a::l1), l2; simpl; f_equal; auto.
Qed.
(** Inversion *)
Lemma in_inv : forall (a b:A) (l:list A), In b (a :: l) -> a = b \/ In b l.
Proof.
intros a b l H; inversion_clear H; auto.
Qed.
(** Decidability of [In] *)
Theorem in_dec :
(forall x y:A, {x = y} + {x <> y}) ->
forall (a:A) (l:list A), {In a l} + {~ In a l}.
Proof.
intro H; induction l as [| a0 l IHl].
right; apply in_nil.
destruct (H a0 a); simpl; auto.
destruct IHl; simpl; auto.
right; unfold not; intros [Hc1| Hc2]; auto.
Defined.
(**************************)
(** *** Facts about [app] *)
(**************************)
(** Discrimination *)
Theorem app_cons_not_nil : forall (x y:list A) (a:A), [] <> x ++ a :: y.
Proof.
unfold not.
destruct x as [| a l]; simpl; intros.
discriminate H.
discriminate H.
Qed.
(** Concat with [nil] *)
Theorem app_nil_l : forall l:list A, [] ++ l = l.
Proof.
reflexivity.
Qed.
Theorem app_nil_r : forall l:list A, l ++ [] = l.
Proof.
induction l; simpl; f_equal; auto.
Qed.
(* begin hide *)
(* Deprecated *)
Theorem app_nil_end : forall (l:list A), l = l ++ [].
Proof. symmetry; apply app_nil_r. Qed.
(* end hide *)
(** [app] is associative *)
Theorem app_assoc : forall l m n:list A, l ++ m ++ n = (l ++ m) ++ n.
Proof.
intros l m n; induction l; simpl; f_equal; auto.
Qed.
(* begin hide *)
(* Deprecated *)
Theorem app_assoc_reverse : forall l m n:list A, (l ++ m) ++ n = l ++ m ++ n.
Proof.
auto using app_assoc.
Qed.
Hint Resolve app_assoc_reverse.
(* end hide *)
(** [app] commutes with [cons] *)
Theorem app_comm_cons : forall (x y:list A) (a:A), a :: (x ++ y) = (a :: x) ++ y.
Proof.
auto.
Qed.
(** Facts deduced from the result of a concatenation *)
Theorem app_eq_nil : forall l l':list A, l ++ l' = [] -> l = [] /\ l' = [].
Proof.
destruct l as [| x l]; destruct l' as [| y l']; simpl; auto.
intro; discriminate.
intros H; discriminate H.
Qed.
Theorem app_eq_unit :
forall (x y:list A) (a:A),
x ++ y = [a] -> x = [] /\ y = [a] \/ x = [a] /\ y = [].
Proof.
destruct x as [| a l]; [ destruct y as [| a l] | destruct y as [| a0 l0] ];
simpl.
intros a H; discriminate H.
left; split; auto.
right; split; auto.
generalize H.
generalize (app_nil_r l); intros E.
rewrite -> E; auto.
intros.
injection H.
intro.
cut ([] = l ++ a0 :: l0); auto.
intro.
generalize (app_cons_not_nil _ _ _ H1); intro.
elim H2.
Qed.
Lemma app_inj_tail :
forall (x y:list A) (a b:A), x ++ [a] = y ++ [b] -> x = y /\ a = b.
Proof.
induction x as [| x l IHl];
[ destruct y as [| a l] | destruct y as [| a l0] ];
simpl; auto.
intros a b H.
injection H.
auto.
intros a0 b H.
injection H; intros.
generalize (app_cons_not_nil _ _ _ H0); destruct 1.
intros a b H.
injection H; intros.
cut ([] = l ++ [a]); auto.
intro.
generalize (app_cons_not_nil _ _ _ H2); destruct 1.
intros a0 b H.
injection H; intros.
destruct (IHl l0 a0 b H0).
split; auto.
rewrite <- H1; rewrite <- H2; reflexivity.
Qed.
(** Compatibility with other operations *)
Lemma app_length : forall l l' : list A, length (l++l') = length l + length l'.
Proof.
induction l; simpl; auto.
Qed.
Lemma in_app_or : forall (l m:list A) (a:A), In a (l ++ m) -> In a l \/ In a m.
Proof.
intros l m a.
elim l; simpl; auto.
intros a0 y H H0.
now_show ((a0 = a \/ In a y) \/ In a m).
elim H0; auto.
intro H1.
now_show ((a0 = a \/ In a y) \/ In a m).
elim (H H1); auto.
Qed.
Lemma in_or_app : forall (l m:list A) (a:A), In a l \/ In a m -> In a (l ++ m).
Proof.
intros l m a.
elim l; simpl; intro H.
now_show (In a m).
elim H; auto; intro H0.
now_show (In a m).
elim H0. (* subProof completed *)
intros y H0 H1.
now_show (H = a \/ In a (y ++ m)).
elim H1; auto 4.
intro H2.
now_show (H = a \/ In a (y ++ m)).
elim H2; auto.
Qed.
Lemma in_app_iff : forall l l' (a:A), In a (l++l') <-> In a l \/ In a l'.
Proof.
split; auto using in_app_or, in_or_app.
Qed.
Lemma app_inv_head:
forall l l1 l2 : list A, l ++ l1 = l ++ l2 -> l1 = l2.
Proof.
induction l; simpl; auto; injection 1; auto.
Qed.
Lemma app_inv_tail:
forall l l1 l2 : list A, l1 ++ l = l2 ++ l -> l1 = l2.
Proof.
intros l l1 l2; revert l1 l2 l.
induction l1 as [ | x1 l1]; destruct l2 as [ | x2 l2];
simpl; auto; intros l H.
absurd (length (x2 :: l2 ++ l) <= length l).
simpl; rewrite app_length; auto with arith.
rewrite <- H; auto with arith.
absurd (length (x1 :: l1 ++ l) <= length l).
simpl; rewrite app_length; auto with arith.
rewrite H; auto with arith.
injection H; clear H; intros; f_equal; eauto.
Qed.
End Facts.
Hint Resolve app_assoc app_assoc_reverse: datatypes v62.
Hint Resolve app_comm_cons app_cons_not_nil: datatypes v62.
Hint Immediate app_eq_nil: datatypes v62.
Hint Resolve app_eq_unit app_inj_tail: datatypes v62.
Hint Resolve in_eq in_cons in_inv in_nil in_app_or in_or_app: datatypes v62.
(*******************************************)
(** * Operations on the elements of a list *)
(*******************************************)
Section Elts.
Variable A : Type.
(*****************************)
(** ** Nth element of a list *)
(*****************************)
Fixpoint nth (n:nat) (l:list A) (default:A) {struct l} : A :=
match n, l with
| O, x :: l' => x
| O, other => default
| S m, [] => default
| S m, x :: t => nth m t default
end.
Fixpoint nth_ok (n:nat) (l:list A) (default:A) {struct l} : bool :=
match n, l with
| O, x :: l' => true
| O, other => false
| S m, [] => false
| S m, x :: t => nth_ok m t default
end.
Lemma nth_in_or_default :
forall (n:nat) (l:list A) (d:A), {In (nth n l d) l} + {nth n l d = d}.
Proof.
intros n l d; revert n; induction l.
- right; destruct n; trivial.
- intros [|n]; simpl.
* left; auto.
* destruct (IHl n); auto.
Qed.
Lemma nth_S_cons :
forall (n:nat) (l:list A) (d a:A),
In (nth n l d) l -> In (nth (S n) (a :: l) d) (a :: l).
Proof.
simpl; auto.
Qed.
Fixpoint nth_error (l:list A) (n:nat) {struct n} : Exc A :=
match n, l with
| O, x :: _ => value x
| S n, _ :: l => nth_error l n
| _, _ => error
end.
Definition nth_default (default:A) (l:list A) (n:nat) : A :=
match nth_error l n with
| Some x => x
| None => default
end.
Lemma nth_default_eq :
forall n l (d:A), nth_default d l n = nth n l d.
Proof.
unfold nth_default; induction n; intros [ | ] ?; simpl; auto.
Qed.
(** Results about [nth] *)
Lemma nth_In :
forall (n:nat) (l:list A) (d:A), n < length l -> In (nth n l d) l.
Proof.
unfold lt; induction n as [| n hn]; simpl.
- destruct l; simpl; [ inversion 2 | auto ].
- destruct l as [| a l hl]; simpl.
* inversion 2.
* intros d ie; right; apply hn; auto with arith.
Qed.
Lemma In_nth l x d : In x l ->
exists n, n < length l /\ nth n l d = x.
Proof.
induction l as [|a l IH].
- easy.
- intros [H|H].
* subst; exists 0; simpl; auto with arith.
* destruct (IH H) as (n & Hn & Hn').
exists (S n); simpl; auto with arith.
Qed.
Lemma nth_overflow : forall l n d, length l <= n -> nth n l d = d.
Proof.
induction l; destruct n; simpl; intros; auto.
- inversion H.
- apply IHl; auto with arith.
Qed.
Lemma nth_indep :
forall l n d d', n < length l -> nth n l d = nth n l d'.
Proof.
induction l.
- inversion 1.
- intros [|n] d d'; simpl; auto with arith.
Qed.
Lemma app_nth1 :
forall l l' d n, n < length l -> nth n (l++l') d = nth n l d.
Proof.
induction l.
- inversion 1.
- intros l' d [|n]; simpl; auto with arith.
Qed.
Lemma app_nth2 :
forall l l' d n, n >= length l -> nth n (l++l') d = nth (n-length l) l' d.
Proof.
induction l; intros l' d [|n]; auto.
- inversion 1.
- intros; simpl; rewrite IHl; auto with arith.
Qed.
Lemma nth_split n l d : n < length l ->
exists l1, exists l2, l = l1 ++ nth n l d :: l2 /\ length l1 = n.
Proof.
revert l.
induction n as [|n IH]; intros [|a l] H; try easy.
- exists nil; exists l; now simpl.
- destruct (IH l) as (l1 & l2 & Hl & Hl1); auto with arith.
exists (a::l1); exists l2; simpl; split; now f_equal.
Qed.
(** Results about [nth_error] *)
Lemma nth_error_In l n x : nth_error l n = Some x -> In x l.
Proof.
revert n. induction l as [|a l IH]; intros [|n]; simpl; try easy.
- injection 1; auto.
- eauto.
Qed.
Lemma In_nth_error l x : In x l -> exists n, nth_error l n = Some x.
Proof.
induction l as [|a l IH].
- easy.
- intros [H|H].
* subst; exists 0; simpl; auto with arith.
* destruct (IH H) as (n,Hn).
exists (S n); simpl; auto with arith.
Qed.
Lemma nth_error_None l n : nth_error l n = None <-> length l <= n.
Proof.
revert n. induction l; destruct n; simpl.
- split; auto.
- split; auto with arith.
- split; now auto with arith.
- rewrite IHl; split; auto with arith.
Qed.
Lemma nth_error_Some l n : nth_error l n <> None <-> n < length l.
Proof.
revert n. induction l; destruct n; simpl.
- split; [now destruct 1 | inversion 1].
- split; [now destruct 1 | inversion 1].
- split; now auto with arith.
- rewrite IHl; split; auto with arith.
Qed.
Lemma nth_error_split l n a : nth_error l n = Some a ->
exists l1, exists l2, l = l1 ++ a :: l2 /\ length l1 = n.
Proof.
revert l.
induction n as [|n IH]; intros [|x l] H; simpl in *; try easy.
- exists nil; exists l. injection H; clear H; intros; now subst.
- destruct (IH _ H) as (l1 & l2 & H1 & H2).
exists (x::l1); exists l2; simpl; split; now f_equal.
Qed.
Lemma nth_error_app1 l l' n : n < length l ->
nth_error (l++l') n = nth_error l n.
Proof.
revert l.
induction n; intros [|a l] H; auto; try solve [inversion H].
simpl in *. apply IHn. auto with arith.
Qed.
Lemma nth_error_app2 l l' n : length l <= n ->
nth_error (l++l') n = nth_error l' (n-length l).
Proof.
revert l.
induction n; intros [|a l] H; auto; try solve [inversion H].
simpl in *. apply IHn. auto with arith.
Qed.
(*****************)
(** ** Remove *)
(*****************)
Hypothesis eq_dec : forall x y : A, {x = y}+{x <> y}.
Fixpoint remove (x : A) (l : list A) : list A :=
match l with
| [] => []
| y::tl => if (eq_dec x y) then remove x tl else y::(remove x tl)
end.
Theorem remove_In : forall (l : list A) (x : A), ~ In x (remove x l).
Proof.
induction l as [|x l]; auto.
intro y; simpl; destruct (eq_dec y x) as [yeqx | yneqx].
apply IHl.
unfold not; intro HF; simpl in HF; destruct HF; auto.
apply (IHl y); assumption.
Qed.
(******************************)
(** ** Last element of a list *)
(******************************)
(** [last l d] returns the last element of the list [l],
or the default value [d] if [l] is empty. *)
Fixpoint last (l:list A) (d:A) : A :=
match l with
| [] => d
| [a] => a
| a :: l => last l d
end.
(** [removelast l] remove the last element of [l] *)
Fixpoint removelast (l:list A) : list A :=
match l with
| [] => []
| [a] => []
| a :: l => a :: removelast l
end.
Lemma app_removelast_last :
forall l d, l <> [] -> l = removelast l ++ [last l d].
Proof.
induction l.
destruct 1; auto.
intros d _.
destruct l; auto.
pattern (a0::l) at 1; rewrite IHl with d; auto; discriminate.
Qed.
Lemma exists_last :
forall l, l <> [] -> { l' : (list A) & { a : A | l = l' ++ [a]}}.
Proof.
induction l.
destruct 1; auto.
intros _.
destruct l.
exists [], a; auto.
destruct IHl as [l' (a',H)]; try discriminate.
rewrite H.
exists (a::l'), a'; auto.
Qed.
Lemma removelast_app :
forall l l', l' <> [] -> removelast (l++l') = l ++ removelast l'.
Proof.
induction l.
simpl; auto.
simpl; intros.
assert (l++l' <> []).
destruct l.
simpl; auto.
simpl; discriminate.
specialize (IHl l' H).
destruct (l++l'); [elim H0; auto|f_equal; auto].
Qed.
(****************************************)
(** ** Counting occurences of a element *)
(****************************************)
Fixpoint count_occ (l : list A) (x : A) : nat :=
match l with
| [] => 0
| y :: tl =>
let n := count_occ tl x in
if eq_dec y x then S n else n
end.
(** Compatibility of count_occ with operations on list *)
Theorem count_occ_In (l : list A) (x : A) : In x l <-> count_occ l x > 0.
Proof.
induction l as [|y l]; simpl.
- split; [destruct 1 | apply gt_irrefl].
- destruct eq_dec as [->|Hneq]; rewrite IHl; intuition.
Qed.
Theorem count_occ_inv_nil (l : list A) :
(forall x:A, count_occ l x = 0) <-> l = [].
Proof.
split.
- induction l as [|x l]; trivial.
intros H. specialize (H x). simpl in H.
destruct eq_dec as [_|NEQ]; [discriminate|now elim NEQ].
- now intros ->.
Qed.
Lemma count_occ_nil : forall (x : A), count_occ [] x = 0.
Proof.
intro x; simpl; reflexivity.
Qed.
Lemma count_occ_cons_eq : forall (l : list A) (x y : A), x = y -> count_occ (x::l) y = S (count_occ l y).
Proof.
intros l x y H; simpl.
destruct (eq_dec x y); [reflexivity | contradiction].
Qed.
Lemma count_occ_cons_neq : forall (l : list A) (x y : A), x <> y -> count_occ (x::l) y = count_occ l y.
Proof.
intros l x y H; simpl.
destruct (eq_dec x y); [contradiction | reflexivity].
Qed.
End Elts.
(*******************************)
(** * Manipulating whole lists *)
(*******************************)
Section ListOps.
Variable A : Type.
(*************************)
(** ** Reverse *)
(*************************)
Fixpoint rev (l:list A) : list A :=
match l with
| [] => []
| x :: l' => rev l' ++ [x]
end.
Lemma rev_app_distr : forall x y:list A, rev (x ++ y) = rev y ++ rev x.
Proof.
induction x as [| a l IHl].
destruct y as [| a l].
simpl.
auto.
simpl.
rewrite app_nil_r; auto.
intro y.
simpl.
rewrite (IHl y).
rewrite app_assoc; trivial.
Qed.
Remark rev_unit : forall (l:list A) (a:A), rev (l ++ [a]) = a :: rev l.
Proof.
intros.
apply (rev_app_distr l [a]); simpl; auto.
Qed.
Lemma rev_involutive : forall l:list A, rev (rev l) = l.
Proof.
induction l as [| a l IHl].
simpl; auto.
simpl.
rewrite (rev_unit (rev l) a).
rewrite IHl; auto.
Qed.
(** Compatibility with other operations *)
Lemma in_rev : forall l x, In x l <-> In x (rev l).
Proof.
induction l.
simpl; intuition.
intros.
simpl.
intuition.
subst.
apply in_or_app; right; simpl; auto.
apply in_or_app; left; firstorder.
destruct (in_app_or _ _ _ H); firstorder.
Qed.
Lemma rev_length : forall l, length (rev l) = length l.
Proof.
induction l;simpl; auto.
rewrite app_length.
rewrite IHl.
simpl.
elim (length l); simpl; auto.
Qed.
Lemma rev_nth : forall l d n, n < length l ->
nth n (rev l) d = nth (length l - S n) l d.
Proof.
induction l.
intros; inversion H.
intros.
simpl in H.
simpl (rev (a :: l)).
simpl (length (a :: l) - S n).
inversion H.
rewrite <- minus_n_n; simpl.
rewrite <- rev_length.
rewrite app_nth2; auto.
rewrite <- minus_n_n; auto.
rewrite app_nth1; auto.
rewrite (minus_plus_simpl_l_reverse (length l) n 1).
replace (1 + length l) with (S (length l)); auto with arith.
rewrite <- minus_Sn_m; auto with arith.
apply IHl ; auto with arith.
rewrite rev_length; auto.
Qed.
(** An alternative tail-recursive definition for reverse *)
Fixpoint rev_append (l l': list A) : list A :=
match l with
| [] => l'
| a::l => rev_append l (a::l')
end.
Definition rev' l : list A := rev_append l [].
Lemma rev_append_rev : forall l l', rev_append l l' = rev l ++ l'.
Proof.
induction l; simpl; auto; intros.
rewrite <- app_assoc; firstorder.
Qed.
Lemma rev_alt : forall l, rev l = rev_append l [].
Proof.
intros; rewrite rev_append_rev.
rewrite app_nil_r; trivial.
Qed.
(*********************************************)
(** Reverse Induction Principle on Lists *)
(*********************************************)
Section Reverse_Induction.
Lemma rev_list_ind :
forall P:list A-> Prop,
P [] ->
(forall (a:A) (l:list A), P (rev l) -> P (rev (a :: l))) ->
forall l:list A, P (rev l).
Proof.
induction l; auto.
Qed.
Theorem rev_ind :
forall P:list A -> Prop,
P [] ->
(forall (x:A) (l:list A), P l -> P (l ++ [x])) -> forall l:list A, P l.
Proof.
intros.
generalize (rev_involutive l).
intros E; rewrite <- E.
apply (rev_list_ind P).
auto.
simpl.
intros.
apply (H0 a (rev l0)).
auto.
Qed.
End Reverse_Induction.
(***********************************)
(** ** Decidable equality on lists *)
(***********************************)
Hypothesis eq_dec : forall (x y : A), {x = y}+{x <> y}.
Lemma list_eq_dec : forall l l':list A, {l = l'} + {l <> l'}.
Proof. decide equality. Defined.
End ListOps.
(***************************************************)
(** * Applying functions to the elements of a list *)
(***************************************************)
(************)
(** ** Map *)
(************)
Section Map.
Variables A B : Type.
Variable f : A -> B.
Fixpoint map (l:list A) : list B :=
match l with
| nil => nil
| cons a t => cons (f a) (map t)
end.
Lemma in_map :
forall (l:list A) (x:A), In x l -> In (f x) (map l).
Proof.
induction l; firstorder (subst; auto).
Qed.
Lemma in_map_iff : forall l y, In y (map l) <-> exists x, f x = y /\ In x l.
Proof.
induction l; firstorder (subst; auto).
Qed.
Lemma map_length : forall l, length (map l) = length l.
Proof.
induction l; simpl; auto.
Qed.
Lemma map_nth : forall l d n,
nth n (map l) (f d) = f (nth n l d).
Proof.
induction l; simpl map; destruct n; firstorder.
Qed.
Lemma map_nth_error : forall n l d,
nth_error l n = Some d -> nth_error (map l) n = Some (f d).
Proof.
induction n; intros [ | ] ? Heq; simpl in *; inversion Heq; auto.
Qed.
Lemma map_app : forall l l',
map (l++l') = (map l)++(map l').
Proof.
induction l; simpl; auto.
intros; rewrite IHl; auto.
Qed.
Lemma map_rev : forall l, map (rev l) = rev (map l).
Proof.
induction l; simpl; auto.
rewrite map_app.
rewrite IHl; auto.
Qed.
Lemma map_eq_nil : forall l, map l = [] -> l = [].
Proof.
destruct l; simpl; reflexivity || discriminate.
Qed.
(** [flat_map] *)
Definition flat_map (f:A -> list B) :=
fix flat_map (l:list A) : list B :=
match l with
| nil => nil
| cons x t => (f x)++(flat_map t)
end.
Lemma in_flat_map : forall (f:A->list B)(l:list A)(y:B),
In y (flat_map f l) <-> exists x, In x l /\ In y (f x).
Proof.
induction l; simpl; split; intros.
contradiction.
destruct H as (x,(H,_)); contradiction.
destruct (in_app_or _ _ _ H).
exists a; auto.
destruct (IHl y) as (H1,_); destruct (H1 H0) as (x,(H2,H3)).
exists x; auto.
apply in_or_app.
destruct H as (x,(H0,H1)); destruct H0.
subst; auto.
right; destruct (IHl y) as (_,H2); apply H2.
exists x; auto.
Qed.
End Map.
Lemma map_id : forall (A :Type) (l : list A),
map (fun x => x) l = l.
Proof.
induction l; simpl; auto; rewrite IHl; auto.
Qed.
Lemma map_map : forall (A B C:Type)(f:A->B)(g:B->C) l,
map g (map f l) = map (fun x => g (f x)) l.
Proof.
induction l; simpl; auto.
rewrite IHl; auto.
Qed.
Lemma map_ext :
forall (A B : Type)(f g:A->B), (forall a, f a = g a) -> forall l, map f l = map g l.
Proof.
induction l; simpl; auto.
rewrite H; rewrite IHl; auto.
Qed.
(************************************)
(** Left-to-right iterator on lists *)
(************************************)
Section Fold_Left_Recursor.
Variables A B : Type.
Variable f : A -> B -> A.
Fixpoint fold_left (l:list B) (a0:A) : A :=
match l with
| nil => a0
| cons b t => fold_left t (f a0 b)
end.
Lemma fold_left_app : forall (l l':list B)(i:A),
fold_left (l++l') i = fold_left l' (fold_left l i).
Proof.
induction l.
simpl; auto.
intros.
simpl.
auto.
Qed.
End Fold_Left_Recursor.
Lemma fold_left_length :
forall (A:Type)(l:list A), fold_left (fun x _ => S x) l 0 = length l.
Proof.
intro A.
cut (forall (l:list A) n, fold_left (fun x _ => S x) l n = n + length l).
intros.
exact (H l 0).
induction l; simpl; auto.
intros; rewrite IHl.
simpl; auto with arith.
Qed.
(************************************)
(** Right-to-left iterator on lists *)
(************************************)
Section Fold_Right_Recursor.
Variables A B : Type.
Variable f : B -> A -> A.
Variable a0 : A.
Fixpoint fold_right (l:list B) : A :=
match l with
| nil => a0
| cons b t => f b (fold_right t)
end.
End Fold_Right_Recursor.
Lemma fold_right_app : forall (A B:Type)(f:A->B->B) l l' i,
fold_right f i (l++l') = fold_right f (fold_right f i l') l.
Proof.
induction l.
simpl; auto.
simpl; intros.
f_equal; auto.
Qed.
Lemma fold_left_rev_right : forall (A B:Type)(f:A->B->B) l i,
fold_right f i (rev l) = fold_left (fun x y => f y x) l i.
Proof.
induction l.
simpl; auto.
intros.
simpl.
rewrite fold_right_app; simpl; auto.
Qed.
Theorem fold_symmetric :
forall (A:Type) (f:A -> A -> A),
(forall x y z:A, f x (f y z) = f (f x y) z) ->
(forall x y:A, f x y = f y x) ->
forall (a0:A) (l:list A), fold_left f l a0 = fold_right f a0 l.
Proof.
destruct l as [| a l].
reflexivity.
simpl.
rewrite <- H0.
generalize a0 a.
induction l as [| a3 l IHl]; simpl.
trivial.
intros.
rewrite H.
rewrite (H0 a2).
rewrite <- (H a1).
rewrite (H0 a1).
rewrite IHl.
reflexivity.
Qed.
(** [(list_power x y)] is [y^x], or the set of sequences of elts of [y]
indexed by elts of [x], sorted in lexicographic order. *)
Fixpoint list_power (A B:Type)(l:list A) (l':list B) :
list (list (A * B)) :=
match l with
| nil => cons nil nil
| cons x t =>
flat_map (fun f:list (A * B) => map (fun y:B => cons (x, y) f) l')
(list_power t l')
end.
(*************************************)
(** ** Boolean operations over lists *)
(*************************************)
Section Bool.
Variable A : Type.
Variable f : A -> bool.
(** find whether a boolean function can be satisfied by an
elements of the list. *)
Fixpoint existsb (l:list A) : bool :=
match l with
| nil => false
| a::l => f a || existsb l
end.
Lemma existsb_exists :
forall l, existsb l = true <-> exists x, In x l /\ f x = true.
Proof.
induction l; simpl; intuition.
inversion H.
firstorder.
destruct (orb_prop _ _ H1); firstorder.
firstorder.
subst.
rewrite H2; auto.
Qed.
Lemma existsb_nth : forall l n d, n < length l ->
existsb l = false -> f (nth n l d) = false.
Proof.
induction l.
inversion 1.
simpl; intros.
destruct (orb_false_elim _ _ H0); clear H0; auto.
destruct n ; auto.
rewrite IHl; auto with arith.
Qed.
Lemma existsb_app : forall l1 l2,
existsb (l1++l2) = existsb l1 || existsb l2.
Proof.
induction l1; intros l2; simpl.
solve[auto].
case (f a); simpl; solve[auto].
Qed.
(** find whether a boolean function is satisfied by
all the elements of a list. *)
Fixpoint forallb (l:list A) : bool :=
match l with
| nil => true
| a::l => f a && forallb l
end.
Lemma forallb_forall :
forall l, forallb l = true <-> (forall x, In x l -> f x = true).
Proof.
induction l; simpl; intuition.
destruct (andb_prop _ _ H1).
congruence.
destruct (andb_prop _ _ H1); auto.
assert (forallb l = true).
apply H0; intuition.
rewrite H1; auto.
Qed.
Lemma forallb_app :
forall l1 l2, forallb (l1++l2) = forallb l1 && forallb l2.
Proof.
induction l1; simpl.
solve[auto].
case (f a); simpl; solve[auto].
Qed.
(** [filter] *)
Fixpoint filter (l:list A) : list A :=
match l with
| nil => nil
| x :: l => if f x then x::(filter l) else filter l
end.
Lemma filter_In : forall x l, In x (filter l) <-> In x l /\ f x = true.
Proof.
induction l; simpl.
intuition.
intros.
case_eq (f a); intros; simpl; intuition congruence.
Qed.
(** [find] *)
Fixpoint find (l:list A) : option A :=
match l with
| nil => None
| x :: tl => if f x then Some x else find tl
end.
(** [partition] *)
Fixpoint partition (l:list A) : list A * list A :=
match l with
| nil => (nil, nil)
| x :: tl => let (g,d) := partition tl in
if f x then (x::g,d) else (g,x::d)
end.
End Bool.
(******************************************************)
(** ** Operations on lists of pairs or lists of lists *)
(******************************************************)
Section ListPairs.
Variables A B : Type.
(** [split] derives two lists from a list of pairs *)
Fixpoint split (l:list (A*B)) : list A * list B :=
match l with
| nil => (nil, nil)
| (x,y) :: tl => let (g,d) := split tl in (x::g, y::d)
end.
Lemma in_split_l : forall (l:list (A*B))(p:A*B),
In p l -> In (fst p) (fst (split l)).
Proof.
induction l; simpl; intros; auto.
destruct p; destruct a; destruct (split l); simpl in *.
destruct H.
injection H; auto.
right; apply (IHl (a0,b) H).
Qed.
Lemma in_split_r : forall (l:list (A*B))(p:A*B),
In p l -> In (snd p) (snd (split l)).
Proof.
induction l; simpl; intros; auto.
destruct p; destruct a; destruct (split l); simpl in *.
destruct H.
injection H; auto.
right; apply (IHl (a0,b) H).
Qed.
Lemma split_nth : forall (l:list (A*B))(n:nat)(d:A*B),
nth n l d = (nth n (fst (split l)) (fst d), nth n (snd (split l)) (snd d)).
Proof.
induction l.
destruct n; destruct d; simpl; auto.
destruct n; destruct d; simpl; auto.
destruct a; destruct (split l); simpl; auto.
destruct a; destruct (split l); simpl in *; auto.
apply IHl.
Qed.
Lemma split_length_l : forall (l:list (A*B)),
length (fst (split l)) = length l.
Proof.
induction l; simpl; auto.
destruct a; destruct (split l); simpl; auto.
Qed.
Lemma split_length_r : forall (l:list (A*B)),
length (snd (split l)) = length l.
Proof.
induction l; simpl; auto.
destruct a; destruct (split l); simpl; auto.
Qed.
(** [combine] is the opposite of [split].
Lists given to [combine] are meant to be of same length.
If not, [combine] stops on the shorter list *)
Fixpoint combine (l : list A) (l' : list B) : list (A*B) :=
match l,l' with
| x::tl, y::tl' => (x,y)::(combine tl tl')
| _, _ => nil
end.
Lemma split_combine : forall (l: list (A*B)),
let (l1,l2) := split l in combine l1 l2 = l.
Proof.
induction l.
simpl; auto.
destruct a; simpl.
destruct (split l); simpl in *.
f_equal; auto.
Qed.
Lemma combine_split : forall (l:list A)(l':list B), length l = length l' ->
split (combine l l') = (l,l').
Proof.
induction l; destruct l'; simpl; intros; auto; try discriminate.
injection H; clear H; intros.
rewrite IHl; auto.
Qed.
Lemma in_combine_l : forall (l:list A)(l':list B)(x:A)(y:B),
In (x,y) (combine l l') -> In x l.
Proof.
induction l.
simpl; auto.
destruct l'; simpl; auto; intros.
contradiction.
destruct H.
injection H; auto.
right; apply IHl with l' y; auto.
Qed.
Lemma in_combine_r : forall (l:list A)(l':list B)(x:A)(y:B),
In (x,y) (combine l l') -> In y l'.
Proof.
induction l.
simpl; intros; contradiction.
destruct l'; simpl; auto; intros.
destruct H.
injection H; auto.
right; apply IHl with x; auto.
Qed.
Lemma combine_length : forall (l:list A)(l':list B),
length (combine l l') = min (length l) (length l').
Proof.
induction l.
simpl; auto.
destruct l'; simpl; auto.
Qed.
Lemma combine_nth : forall (l:list A)(l':list B)(n:nat)(x:A)(y:B),
length l = length l' ->
nth n (combine l l') (x,y) = (nth n l x, nth n l' y).
Proof.
induction l; destruct l'; intros; try discriminate.
destruct n; simpl; auto.
destruct n; simpl in *; auto.
Qed.
(** [list_prod] has the same signature as [combine], but unlike
[combine], it adds every possible pairs, not only those at the
same position. *)
Fixpoint list_prod (l:list A) (l':list B) :
list (A * B) :=
match l with
| nil => nil
| cons x t => (map (fun y:B => (x, y)) l')++(list_prod t l')
end.
Lemma in_prod_aux :
forall (x:A) (y:B) (l:list B),
In y l -> In (x, y) (map (fun y0:B => (x, y0)) l).
Proof.
induction l;
[ simpl; auto
| simpl; destruct 1 as [H1| ];
[ left; rewrite H1; trivial | right; auto ] ].
Qed.
Lemma in_prod :
forall (l:list A) (l':list B) (x:A) (y:B),
In x l -> In y l' -> In (x, y) (list_prod l l').
Proof.
induction l;
[ simpl; tauto
| simpl; intros; apply in_or_app; destruct H;
[ left; rewrite H; apply in_prod_aux; assumption | right; auto ] ].
Qed.
Lemma in_prod_iff :
forall (l:list A)(l':list B)(x:A)(y:B),
In (x,y) (list_prod l l') <-> In x l /\ In y l'.
Proof.
split; [ | intros; apply in_prod; intuition ].
induction l; simpl; intros.
intuition.
destruct (in_app_or _ _ _ H); clear H.
destruct (in_map_iff (fun y : B => (a, y)) l' (x,y)) as (H1,_).
destruct (H1 H0) as (z,(H2,H3)); clear H0 H1.
injection H2; clear H2; intros; subst; intuition.
intuition.
Qed.
Lemma prod_length : forall (l:list A)(l':list B),
length (list_prod l l') = (length l) * (length l').
Proof.
induction l; simpl; auto.
intros.
rewrite app_length.
rewrite map_length.
auto.
Qed.
End ListPairs.
(*****************************************)
(** * Miscellaneous operations on lists *)
(*****************************************)
(******************************)
(** ** Length order of lists *)
(******************************)
Section length_order.
Variable A : Type.
Definition lel (l m:list A) := length l <= length m.
Variables a b : A.
Variables l m n : list A.
Lemma lel_refl : lel l l.
Proof.
unfold lel; auto with arith.
Qed.
Lemma lel_trans : lel l m -> lel m n -> lel l n.
Proof.
unfold lel; intros.
now_show (length l <= length n).
apply le_trans with (length m); auto with arith.
Qed.
Lemma lel_cons_cons : lel l m -> lel (a :: l) (b :: m).
Proof.
unfold lel; simpl; auto with arith.
Qed.
Lemma lel_cons : lel l m -> lel l (b :: m).
Proof.
unfold lel; simpl; auto with arith.
Qed.
Lemma lel_tail : lel (a :: l) (b :: m) -> lel l m.
Proof.
unfold lel; simpl; auto with arith.
Qed.
Lemma lel_nil : forall l':list A, lel l' nil -> nil = l'.
Proof.
intro l'; elim l'; auto with arith.
intros a' y H H0.
now_show (nil = a' :: y).
absurd (S (length y) <= 0); auto with arith.
Qed.
End length_order.
Hint Resolve lel_refl lel_cons_cons lel_cons lel_nil lel_nil nil_cons:
datatypes v62.
(******************************)
(** ** Set inclusion on list *)
(******************************)
Section SetIncl.
Variable A : Type.
Definition incl (l m:list A) := forall a:A, In a l -> In a m.
Hint Unfold incl.
Lemma incl_refl : forall l:list A, incl l l.
Proof.
auto.
Qed.
Hint Resolve incl_refl.
Lemma incl_tl : forall (a:A) (l m:list A), incl l m -> incl l (a :: m).
Proof.
auto with datatypes.
Qed.
Hint Immediate incl_tl.
Lemma incl_tran : forall l m n:list A, incl l m -> incl m n -> incl l n.
Proof.
auto.
Qed.
Lemma incl_appl : forall l m n:list A, incl l n -> incl l (n ++ m).
Proof.
auto with datatypes.
Qed.
Hint Immediate incl_appl.
Lemma incl_appr : forall l m n:list A, incl l n -> incl l (m ++ n).
Proof.
auto with datatypes.
Qed.
Hint Immediate incl_appr.
Lemma incl_cons :
forall (a:A) (l m:list A), In a m -> incl l m -> incl (a :: l) m.
Proof.
unfold incl; simpl; intros a l m H H0 a0 H1.
now_show (In a0 m).
elim H1.
now_show (a = a0 -> In a0 m).
elim H1; auto; intro H2.
now_show (a = a0 -> In a0 m).
elim H2; auto. (* solves subgoal *)
now_show (In a0 l -> In a0 m).
auto.
Qed.
Hint Resolve incl_cons.
Lemma incl_app : forall l m n:list A, incl l n -> incl m n -> incl (l ++ m) n.
Proof.
unfold incl; simpl; intros l m n H H0 a H1.
now_show (In a n).
elim (in_app_or _ _ _ H1); auto.
Qed.
Hint Resolve incl_app.
End SetIncl.
Hint Resolve incl_refl incl_tl incl_tran incl_appl incl_appr incl_cons
incl_app: datatypes v62.
(**************************************)
(** * Cutting a list at some position *)
(**************************************)
Section Cutting.
Variable A : Type.
Fixpoint firstn (n:nat)(l:list A) : list A :=
match n with
| 0 => nil
| S n => match l with
| nil => nil
| a::l => a::(firstn n l)
end
end.
Fixpoint skipn (n:nat)(l:list A) : list A :=
match n with
| 0 => l
| S n => match l with
| nil => nil
| a::l => skipn n l
end
end.
Lemma firstn_skipn : forall n l, firstn n l ++ skipn n l = l.
Proof.
induction n.
simpl; auto.
destruct l; simpl; auto.
f_equal; auto.
Qed.
Lemma firstn_length : forall n l, length (firstn n l) = min n (length l).
Proof.
induction n; destruct l; simpl; auto.
Qed.
Lemma removelast_firstn : forall n l, n < length l ->
removelast (firstn (S n) l) = firstn n l.
Proof.
induction n; destruct l.
simpl; auto.
simpl; auto.
simpl; auto.
intros.
simpl in H.
change (firstn (S (S n)) (a::l)) with ((a::nil)++firstn (S n) l).
change (firstn (S n) (a::l)) with (a::firstn n l).
rewrite removelast_app.
rewrite IHn; auto with arith.
clear IHn; destruct l; simpl in *; try discriminate.
inversion_clear H.
inversion_clear H0.
Qed.
Lemma firstn_removelast : forall n l, n < length l ->
firstn n (removelast l) = firstn n l.
Proof.
induction n; destruct l.
simpl; auto.
simpl; auto.
simpl; auto.
intros.
simpl in H.
change (removelast (a :: l)) with (removelast ((a::nil)++l)).
rewrite removelast_app.
simpl; f_equal; auto with arith.
intro H0; rewrite H0 in H; inversion_clear H; inversion_clear H1.
Qed.
End Cutting.
(********************************)
(** ** Lists without redundancy *)
(********************************)
Section ReDun.
Variable A : Type.
Inductive NoDup : list A -> Prop :=
| NoDup_nil : NoDup nil
| NoDup_cons : forall x l, ~ In x l -> NoDup l -> NoDup (x::l).
Lemma NoDup_remove_1 : forall l l' a, NoDup (l++a::l') -> NoDup (l++l').
Proof.
induction l; simpl.
inversion_clear 1; auto.
inversion_clear 1.
constructor.
contradict H0.
apply in_or_app; destruct (in_app_or _ _ _ H0); simpl; tauto.
apply IHl with a0; auto.
Qed.
Lemma NoDup_remove_2 : forall l l' a, NoDup (l++a::l') -> ~In a (l++l').
Proof.
induction l; simpl.
inversion_clear 1; auto.
inversion_clear 1.
contradict H0.
destruct H0.
subst a0.
apply in_or_app; right; red; auto.
destruct (IHl _ _ H1); auto.
Qed.
(** Alternative characterisations of being without duplicates,
thanks to [nth_error] and [nth] *)
Lemma NoDup_nth_error l :
NoDup l <->
(forall i j, i<length l -> nth_error l i = nth_error l j -> i = j).
Proof.
split.
{ intros H; induction H as [|a l Hal Hl IH]; intros i j Hi E.
- inversion Hi.
- destruct i, j; simpl in *; auto.
* elim Hal. eapply nth_error_In; eauto.
* elim Hal. eapply nth_error_In; eauto.
* f_equal. apply IH; auto with arith. }
{ induction l as [|a l]; intros H; constructor.
* intro Ha. apply In_nth_error in Ha. destruct Ha as (n,Hn).
assert (n < length l) by (now rewrite <- nth_error_Some, Hn).
specialize (H 0 (S n)). simpl in H. discriminate H; auto with arith.
* apply IHl.
intros i j Hi E. apply eq_add_S, H; simpl; auto with arith. }
Qed.
Lemma NoDup_nth l d :
NoDup l <->
(forall i j, i<length l -> j<length l ->
nth i l d = nth j l d -> i = j).
Proof.
split.
{ intros H; induction H as [|a l Hal Hl IH]; intros i j Hi Hj E.
- inversion Hi.
- destruct i, j; simpl in *; auto.
* elim Hal. subst a. apply nth_In; auto with arith.
* elim Hal. subst a. apply nth_In; auto with arith.
* f_equal. apply IH; auto with arith. }
{ induction l as [|a l]; intros H; constructor.
* intro Ha. eapply In_nth in Ha. destruct Ha as (n & Hn & Hn').
specialize (H 0 (S n)). simpl in H. discriminate H; eauto with arith.
* apply IHl.
intros i j Hi Hj E. apply eq_add_S, H; simpl; auto with arith. }
Qed.
End ReDun.
(***********************************)
(** ** Sequence of natural numbers *)
(***********************************)
Section NatSeq.
(** [seq] computes the sequence of [len] contiguous integers
that starts at [start]. For instance, [seq 2 3] is [2::3::4::nil]. *)
Fixpoint seq (start len:nat) : list nat :=
match len with
| 0 => nil
| S len => start :: seq (S start) len
end.
Lemma seq_length : forall len start, length (seq start len) = len.
Proof.
induction len; simpl; auto.
Qed.
Lemma seq_nth : forall len start n d,
n < len -> nth n (seq start len) d = start+n.
Proof.
induction len; intros.
inversion H.
simpl seq.
destruct n; simpl.
auto with arith.
rewrite IHlen;simpl; auto with arith.
Qed.
Lemma seq_shift : forall len start,
map S (seq start len) = seq (S start) len.
Proof.
induction len; simpl; auto.
intros.
rewrite IHlen.
auto with arith.
Qed.
Lemma in_seq len start n :
In n (seq start len) <-> start <= n < start+len.
Proof.
revert start. induction len; simpl; intros.
- rewrite <- plus_n_O. split;[easy|].
intros (H,H'). apply (Lt.lt_irrefl _ (Lt.le_lt_trans _ _ _ H H')).
- rewrite IHlen, <- plus_n_Sm; simpl; split.
* intros [H|H]; subst; intuition auto with arith.
* intros (H,H'). destruct (Lt.le_lt_or_eq _ _ H); intuition.
Qed.
Lemma seq_NoDup len start : NoDup (seq start len).
Proof.
revert start; induction len; simpl; constructor; trivial.
rewrite in_seq. intros (H,_). apply (Lt.lt_irrefl _ H).
Qed.
End NatSeq.
(** * Existential and universal predicates over lists *)
Inductive Exists {A} (P:A->Prop) : list A -> Prop :=
| Exists_cons_hd : forall x l, P x -> Exists P (x::l)
| Exists_cons_tl : forall x l, Exists P l -> Exists P (x::l).
Hint Constructors Exists.
Lemma Exists_exists : forall A P (l:list A),
Exists P l <-> (exists x, In x l /\ P x).
Proof.
split.
induction 1; firstorder.
induction l; firstorder; subst; auto.
Qed.
Lemma Exists_nil : forall A (P:A->Prop), Exists P nil <-> False.
Proof. split; inversion 1. Qed.
Lemma Exists_cons : forall A (P:A->Prop) x l,
Exists P (x::l) <-> P x \/ Exists P l.
Proof. split; inversion 1; auto. Qed.
Inductive Forall {A} (P:A->Prop) : list A -> Prop :=
| Forall_nil : Forall P nil
| Forall_cons : forall x l, P x -> Forall P l -> Forall P (x::l).
Hint Constructors Forall.
Lemma Forall_forall : forall A P (l:list A),
Forall P l <-> (forall x, In x l -> P x).
Proof.
split.
induction 1; firstorder; subst; auto.
induction l; firstorder.
Qed.
Lemma Forall_inv : forall A P (a:A) l, Forall P (a :: l) -> P a.
Proof.
intros; inversion H; trivial.
Defined.
Lemma Forall_rect : forall A (P:A->Prop) (Q : list A -> Type),
Q [] -> (forall b l, P b -> Q (b :: l)) -> forall l, Forall P l -> Q l.
Proof.
intros A P Q H H'; induction l; intro; [|eapply H', Forall_inv]; eassumption.
Defined.
Lemma Forall_impl : forall A (P Q : A -> Prop), (forall a, P a -> Q a) ->
forall l, Forall P l -> Forall Q l.
Proof.
intros A P Q Himp l H.
induction H; firstorder.
Qed.
(** [Forall2]: stating that elements of two lists are pairwise related. *)
Inductive Forall2 A B (R:A->B->Prop) : list A -> list B -> Prop :=
| Forall2_nil : Forall2 R [] []
| Forall2_cons : forall x y l l',
R x y -> Forall2 R l l' -> Forall2 R (x::l) (y::l').
Hint Constructors Forall2.
Theorem Forall2_refl : forall A B (R:A->B->Prop), Forall2 R [] [].
Proof. exact Forall2_nil. Qed.
Theorem Forall2_app_inv_l : forall A B (R:A->B->Prop) l1 l2 l',
Forall2 R (l1 ++ l2) l' ->
exists l1' l2', Forall2 R l1 l1' /\ Forall2 R l2 l2' /\ l' = l1' ++ l2'.
Proof.
induction l1; intros.
exists [], l'; auto.
simpl in H; inversion H; subst; clear H.
apply IHl1 in H4 as (l1' & l2' & Hl1 & Hl2 & ->).
exists (y::l1'), l2'; simpl; auto.
Qed.
Theorem Forall2_app_inv_r : forall A B (R:A->B->Prop) l1' l2' l,
Forall2 R l (l1' ++ l2') ->
exists l1 l2, Forall2 R l1 l1' /\ Forall2 R l2 l2' /\ l = l1 ++ l2.
Proof.
induction l1'; intros.
exists [], l; auto.
simpl in H; inversion H; subst; clear H.
apply IHl1' in H4 as (l1 & l2 & Hl1 & Hl2 & ->).
exists (x::l1), l2; simpl; auto.
Qed.
Theorem Forall2_app : forall A B (R:A->B->Prop) l1 l2 l1' l2',
Forall2 R l1 l1' -> Forall2 R l2 l2' -> Forall2 R (l1 ++ l2) (l1' ++ l2').
Proof.
intros. induction l1 in l1', H, H0 |- *; inversion H; subst; simpl; auto.
Qed.
(** [ForallPairs] : specifies that a certain relation should
always hold when inspecting all possible pairs of elements of a list. *)
Definition ForallPairs A (R : A -> A -> Prop) l :=
forall a b, In a l -> In b l -> R a b.
(** [ForallOrdPairs] : we still check a relation over all pairs
of elements of a list, but now the order of elements matters. *)
Inductive ForallOrdPairs A (R : A -> A -> Prop) : list A -> Prop :=
| FOP_nil : ForallOrdPairs R nil
| FOP_cons : forall a l,
Forall (R a) l -> ForallOrdPairs R l -> ForallOrdPairs R (a::l).
Hint Constructors ForallOrdPairs.
Lemma ForallOrdPairs_In : forall A (R:A->A->Prop) l,
ForallOrdPairs R l ->
forall x y, In x l -> In y l -> x=y \/ R x y \/ R y x.
Proof.
induction 1.
inversion 1.
simpl; destruct 1; destruct 1; repeat subst; auto.
right; left. apply -> Forall_forall; eauto.
right; right. apply -> Forall_forall; eauto.
Qed.
(** [ForallPairs] implies [ForallOrdPairs]. The reverse implication is true
only when [R] is symmetric and reflexive. *)
Lemma ForallPairs_ForallOrdPairs : forall A (R:A->A->Prop) l,
ForallPairs R l -> ForallOrdPairs R l.
Proof.
induction l; auto. intros H.
constructor.
apply <- Forall_forall. intros; apply H; simpl; auto.
apply IHl. red; intros; apply H; simpl; auto.
Qed.
Lemma ForallOrdPairs_ForallPairs : forall A (R:A->A->Prop),
(forall x, R x x) ->
(forall x y, R x y -> R y x) ->
forall l, ForallOrdPairs R l -> ForallPairs R l.
Proof.
intros A R Refl Sym l Hl x y Hx Hy.
destruct (ForallOrdPairs_In Hl _ _ Hx Hy); subst; intuition.
Qed.
(** * Inversion of predicates over lists based on head symbol *)
Ltac is_list_constr c :=
match c with
| nil => idtac
| (_::_) => idtac
| _ => fail
end.
Ltac invlist f :=
match goal with
| H:f ?l |- _ => is_list_constr l; inversion_clear H; invlist f
| H:f _ ?l |- _ => is_list_constr l; inversion_clear H; invlist f
| H:f _ _ ?l |- _ => is_list_constr l; inversion_clear H; invlist f
| H:f _ _ _ ?l |- _ => is_list_constr l; inversion_clear H; invlist f
| H:f _ _ _ _ ?l |- _ => is_list_constr l; inversion_clear H; invlist f
| _ => idtac
end.
(** * Exporting hints and tactics *)
Hint Rewrite
rev_involutive (* rev (rev l) = l *)
rev_unit (* rev (l ++ a :: nil) = a :: rev l *)
map_nth (* nth n (map f l) (f d) = f (nth n l d) *)
map_length (* length (map f l) = length l *)
seq_length (* length (seq start len) = len *)
app_length (* length (l ++ l') = length l + length l' *)
rev_length (* length (rev l) = length l *)
app_nil_r (* l ++ nil = l *)
: list.
Ltac simpl_list := autorewrite with list.
Ltac ssimpl_list := autorewrite with list using simpl.
(* begin hide *)
(* Compatibility notations after the migration of [list] to [Datatypes] *)
Notation list := list (only parsing).
Notation list_rect := list_rect (only parsing).
Notation list_rec := list_rec (only parsing).
Notation list_ind := list_ind (only parsing).
Notation nil := nil (only parsing).
Notation cons := cons (only parsing).
Notation length := length (only parsing).
Notation app := app (only parsing).
(* Compatibility Names *)
Notation tail := tl (only parsing).
Notation head := hd_error (only parsing).
Notation head_nil := hd_error_nil (only parsing).
Notation head_cons := hd_error_cons (only parsing).
Notation ass_app := app_assoc (only parsing).
Notation app_ass := app_assoc_reverse (only parsing).
Notation In_split := in_split (only parsing).
Notation In_rev := in_rev (only parsing).
Notation In_dec := in_dec (only parsing).
Notation distr_rev := rev_app_distr (only parsing).
Notation rev_acc := rev_append (only parsing).
Notation rev_acc_rev := rev_append_rev (only parsing).
Notation AllS := Forall (only parsing). (* was formerly in TheoryList *)
Hint Resolve app_nil_end : datatypes v62.
(* end hide *)
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of rs_urac_fe1
//
// Generated
// by: lutscher
// on: Mon Aug 24 13:45:20 2009
// cmd: /tools/mix/2.0/bin/mix_1.pl test_urac.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author$
// $Id$
// $Date$
// $Log$
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.110 2009/06/25 15:41:53 lutscher Exp
//
// Generator: mix_1.pl Revision: 1.3 , [email protected] and [email protected]
// (C) 2003-2009 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of rs_urac_fe1
//
// No user `defines in this module
`define tie0_1_c 1'b0
module rs_urac_fe1
//
// Generated Module rs_urac_fe1_i
//
(
input wire clk_i,
input wire res_n_i,
input wire [7:0] urac_addr_i,
input wire [7:0] urac_data_i,
input wire urac_wren_i,
input wire urac_rden_i,
output reg [7:0] urac_dout_o,
output reg [3:0] dgatel_par_o,
output reg [3:0] dgates_par_o,
input wire cvbsdetect_par_i,
output wire y_test_par_o,
input wire y_test_set_p_i,
input wire ycdetect_par_i,
output reg [4:0] mvstart_par_o,
output reg [2:0] mvstop_par_o,
output reg [4:0] prova_par_o,
input wire [1:0] r_native_par_i,
output wire [1:0] rw_native_par_o,
input wire cvbsdetect2_par_i,
output wire ycdetect2_par_o,
input wire clk_f20_i,
input wire res_f20_n_i,
input wire hsync_p_i
);
// Module parameters:
parameter P_MIX_SIG = "M1";
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire REG_0_wr_ts;
wire REG_0_wr_ts_p;
wire REG_2_wr_ts;
wire REG_2_wr_ts_p;
wire REG_3_wr_ts;
wire REG_3_wr_ts_p;
wire clk; // __W_PORT_SIGNAL_MAP_REQ
wire clk_f20; // __W_PORT_SIGNAL_MAP_REQ
wire hsync_p; // __W_PORT_SIGNAL_MAP_REQ
wire int_hsync_p_clk_f20_p;
wire int_hsync_p_clk_p;
wire res_f20_n; // __W_PORT_SIGNAL_MAP_REQ
wire res_n; // __W_PORT_SIGNAL_MAP_REQ
wire tie0_1;
wire y_test_set_p; // __W_PORT_SIGNAL_MAP_REQ
wire y_test_set_p_sync;
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
assign clk = clk_i; // __I_I_BIT_PORT
assign clk_f20 = clk_f20_i; // __I_I_BIT_PORT
assign hsync_p = hsync_p_i; // __I_I_BIT_PORT
assign res_f20_n = res_f20_n_i; // __I_I_BIT_PORT
assign res_n = res_n_i; // __I_I_BIT_PORT
assign tie0_1 = `tie0_1_c;
assign y_test_set_p = y_test_set_p_i; // __I_I_BIT_PORT
/*
checking code
*/
`ifdef ASSERT_ON
// msd parse off
parameter P_WAIT_IS_DRIVEN = 256;
property is_driven(clk, rst_n, sig);
@(posedge clk) $rose(rst_n) |=> ##P_WAIT_IS_DRIVEN !$isunknown(sig);
endproperty
assert_urac_wren_driven: assert property(is_driven(clk_i, res_n_i, urac_wren_i)) else $error("ERROR: input port urac_wren is undriven after reset");
assert_urac_rden_driven: assert property(is_driven(clk_i, res_n_i, urac_rden_i)) else $error("ERROR: input port urac_rden is undriven after reset");
// msd parse on
`endif
/* ------------------------------------------------------------
Generator information:
used package Micronas::Reg is version 1.90
package RegViewURAC is version 1.3
use with RTL libraries (this release or higher):
ip_sync/0001/ip_sync_006_23jan2008
------------------------------------------------------------ */
/*
local definitions
*/
localparam REG_0_OFFS = 0; // FE_YCDET_CTRL
localparam REG_1_OFFS = 1; // FE_YCDET_STAT
localparam REG_2_OFFS = 2; // FE_YCDET_CTRL2
localparam REG_3_OFFS = 3; // FE_MVDET
localparam REG_4_OFFS = 4; // FE_NATIVE
localparam REG_5_OFFS = 5; // FE_NT
/*
local wire or register declarations
*/
reg [7:0] REG_0;
reg REG_0_wr_ts_s;
wire [3:0] dgatel_shdw;
wire [3:0] dgates_shdw;
reg [7:0] REG_1;
reg [0:0] cvbsdetect_shdw;
reg [7:0] REG_2;
reg REG_2_wr_ts_s;
wire [4:0] mvstart_shdw;
reg [7:0] REG_3;
reg REG_3_wr_ts_s;
wire [2:0] mvstop_shdw;
wire [4:0] prova_shdw;
reg [7:0] REG_4;
reg [1:0] r_native_shdw;
reg [7:0] REG_5;
wire [2:0] iaddr;
wire [7:0] wdata;
reg [7:0] mux_rd_data;
/*
local wire and output assignments
*/
assign dgatel_shdw[3:0] = REG_0[3:0];
assign dgates_shdw[3:0] = REG_0[7:4];
assign REG_0_wr_ts = REG_0_wr_ts_s;
assign y_test_par_o = REG_1[2];
assign mvstart_shdw[4:0] = REG_2[4:0];
assign REG_2_wr_ts = REG_2_wr_ts_s;
assign prova_shdw[4:0] = REG_3[4:0];
assign mvstop_shdw[2:0] = REG_3[7:5];
assign REG_3_wr_ts = REG_3_wr_ts_s;
assign rw_native_par_o[1:0] = REG_4[1:0];
assign ycdetect2_par_o = REG_5[1];
/*
inputs
*/
assign iaddr = urac_addr_i[2:0];
assign wdata = urac_data_i;
/*
read data output assignment
*/
always @(posedge clk_i or negedge res_n_i) begin
if (~res_n_i)
urac_dout_o <= 0;
else
if (urac_rden_i)
urac_dout_o <= mux_rd_data;
end
/*
write process
*/
always @(posedge clk_i or negedge res_n_i) begin
if (~res_n_i) begin
REG_0[3:0] <= 'h4;
REG_0[7:4] <= 'hf;
REG_2[4:0] <= 'h7;
REG_3[4:0] <= 'h4;
REG_3[7:5] <= 'h0;
REG_4[1:0] <= 'h0;
REG_5[1] <= 'h0;
end
else begin
if (urac_wren_i)
case (iaddr)
REG_0_OFFS: begin
REG_0[3:0] <= wdata[3:0];
REG_0[7:4] <= wdata[7:4];
end
REG_2_OFFS: begin
REG_2[4:0] <= wdata[4:0];
end
REG_3_OFFS: begin
REG_3[4:0] <= wdata[4:0];
REG_3[7:5] <= wdata[7:5];
end
REG_4_OFFS: begin
REG_4[1:0] <= wdata[1:0];
end
REG_5_OFFS: begin
REG_5[1] <= wdata[1];
end
default: ;
endcase
end
end
/*
write process for status registers
*/
always @(posedge clk_i or negedge res_n_i) begin
if (~res_n_i) begin
REG_1[2] <= 'h0;
end
else begin
if (y_test_set_p_sync)
REG_1[2] <= 1;
else if (urac_wren_i && iaddr == REG_1_OFFS) begin
REG_1[2] <= REG_1[2] & ~wdata[2];
end
end
end
/*
shadowing (into clock domain clk)
*/
always @(posedge clk_i or negedge res_n_i) begin
if (~res_n_i) begin
r_native_shdw <= 'h0;
end
else begin
if (int_hsync_p_clk_p) begin
r_native_shdw <= r_native_par_i;
end
end
end
/*
shadowing (into clock domain clk_f20)
*/
always @(posedge clk_f20_i or negedge res_f20_n_i) begin
if (~res_f20_n_i) begin
dgatel_par_o <= 'h4;
dgates_par_o <= 'hf;
mvstart_par_o <= 'h7;
mvstop_par_o <= 'h0;
prova_par_o <= 'h4;
cvbsdetect_shdw <= 'h0;
end
else begin
if (REG_0_wr_ts_p) begin
dgatel_par_o <= dgatel_shdw;
dgates_par_o <= dgates_shdw;
end
if (REG_2_wr_ts_p) begin
mvstart_par_o <= mvstart_shdw;
end
if (REG_3_wr_ts_p) begin
mvstop_par_o <= mvstop_shdw;
prova_par_o <= prova_shdw;
end
if (int_hsync_p_clk_f20_p) begin
cvbsdetect_shdw <= cvbsdetect_par_i;
end
end
end
/*
toggle-signals for automatic takeover (read and write)
*/
always @(posedge clk_i or negedge res_n_i) begin
if (~res_n_i) begin
REG_0_wr_ts_s <= 0;
REG_2_wr_ts_s <= 0;
REG_3_wr_ts_s <= 0;
end
else begin
if (iaddr == REG_0_OFFS && urac_wren_i)
REG_0_wr_ts_s <= ~REG_0_wr_ts_s;
if (iaddr == REG_2_OFFS && urac_wren_i)
REG_2_wr_ts_s <= ~REG_2_wr_ts_s;
if (iaddr == REG_3_OFFS && urac_wren_i)
REG_3_wr_ts_s <= ~REG_3_wr_ts_s;
end
end
/*
read logic and mux process
*/
always @(*) begin
mux_rd_data <= 0;
case (iaddr)
REG_0_OFFS : begin
mux_rd_data[3:0] <= dgatel_shdw;
mux_rd_data[7:4] <= dgates_shdw;
end
REG_1_OFFS : begin
mux_rd_data[0] <= cvbsdetect_shdw;
mux_rd_data[2] <= REG_1[2];
mux_rd_data[1] <= ycdetect_par_i;
end
REG_2_OFFS : begin
mux_rd_data[4:0] <= mvstart_shdw;
end
REG_3_OFFS : begin
mux_rd_data[7:5] <= mvstop_shdw;
mux_rd_data[4:0] <= prova_shdw;
end
REG_4_OFFS : begin
mux_rd_data[3:2] <= r_native_shdw;
mux_rd_data[1:0] <= REG_4[1:0];
end
REG_5_OFFS : begin
mux_rd_data[0] <= cvbsdetect2_par_i;
end
default: ;
endcase
end
/*
checking code
*/
`ifdef ASSERT_ON
// msd parse off
property p_pos_pulse_check (clock, reset, sig); // check for positive pulse
@(posedge clock) disable iff (~reset)
sig |=> ~sig;
endproperty
assert_y_test_set_p_i_is_a_pulse: assert property(p_pos_pulse_check(clk_f20_i, res_f20_n_i, y_test_set_p_i));
// msd parse on
`endif
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for u0_sync_generic_i
sync_generic #(
.act(1),
.kind(0),
.rstact(0),
.rstval(0),
.sync(1)
) u0_sync_generic_i ( // Synchronizer for set-signal y_test_set_p
.clk_r(clk),
.clk_s(clk_f20),
.rcv_o(y_test_set_p_sync),
.rst_r(res_n),
.rst_s(res_f20_n),
.snd_i(y_test_set_p)
);
// End of Generated Instance Port Map for u0_sync_generic_i
// Generated Instance Port Map for u1_sync_generic_i
sync_generic #(
.act(1),
.kind(2),
.rstact(0),
.rstval(0),
.sync(1)
) u1_sync_generic_i ( // Synchronizer for internal takeover-signal REG_3_wr_ts
.clk_r(clk_f20),
.clk_s(tie0_1),
.rcv_o(REG_3_wr_ts_p),
.rst_r(res_f20_n),
.rst_s(tie0_1),
.snd_i(REG_3_wr_ts)
);
// End of Generated Instance Port Map for u1_sync_generic_i
// Generated Instance Port Map for u2_sync_generic_i
sync_generic #(
.act(1),
.kind(2),
.rstact(0),
.rstval(0),
.sync(1)
) u2_sync_generic_i ( // Synchronizer for internal takeover-signal REG_0_wr_ts
.clk_r(clk_f20),
.clk_s(tie0_1),
.rcv_o(REG_0_wr_ts_p),
.rst_r(res_f20_n),
.rst_s(tie0_1),
.snd_i(REG_0_wr_ts)
);
// End of Generated Instance Port Map for u2_sync_generic_i
// Generated Instance Port Map for u3_sync_generic_i
sync_generic #(
.act(1),
.kind(2),
.rstact(0),
.rstval(0),
.sync(1)
) u3_sync_generic_i ( // Synchronizer for internal takeover-signal REG_2_wr_ts
.clk_r(clk_f20),
.clk_s(tie0_1),
.rcv_o(REG_2_wr_ts_p),
.rst_r(res_f20_n),
.rst_s(tie0_1),
.snd_i(REG_2_wr_ts)
);
// End of Generated Instance Port Map for u3_sync_generic_i
// Generated Instance Port Map for u4_sync_generic_i
sync_generic #(
.act(1),
.kind(3),
.rstact(0),
.rstval(0),
.sync(0)
) u4_sync_generic_i ( // Synchronizer for external takeover-signal hsync_p
.clk_r(clk),
.clk_s(tie0_1),
.rcv_o(int_hsync_p_clk_p),
.rst_r(res_n),
.rst_s(tie0_1),
.snd_i(hsync_p)
);
// End of Generated Instance Port Map for u4_sync_generic_i
// Generated Instance Port Map for u5_sync_generic_i
sync_generic #(
.act(1),
.kind(3),
.rstact(0),
.rstval(0),
.sync(1)
) u5_sync_generic_i ( // Synchronizer for external takeover-signal hsync_p
.clk_r(clk_f20),
.clk_s(tie0_1),
.rcv_o(int_hsync_p_clk_f20_p),
.rst_r(res_f20_n),
.rst_s(tie0_1),
.snd_i(hsync_p)
);
// End of Generated Instance Port Map for u5_sync_generic_i
endmodule
//
// End of Generated Module rtl of rs_urac_fe1
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAPMET1_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__TAPMET1_FUNCTIONAL_PP_V
/**
* tapmet1: Tap cell with isolated power and ground connections.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hs__tapmet1 (
VGND,
VPWR
);
// Module ports
input VGND;
input VPWR;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAPMET1_FUNCTIONAL_PP_V |
(** * Norm: Normalization of STLC *)
(* Chapter written and maintained by Andrew Tolmach *)
(** This optional chapter is based on chapter 12 of _Types and
Programming Languages_ (Pierce). It may be useful to look at the
two together, as that chapter includes explanations and informal
proofs that are not repeated here.
In this chapter, we consider another fundamental theoretical
property of the simply typed lambda-calculus: the fact that the
evaluation of a well-typed program is guaranteed to halt in a
finite number of steps---i.e., every well-typed term is
_normalizable_.
Unlike the type-safety properties we have considered so far, the
normalization property does not extend to full-blown programming
languages, because these languages nearly always extend the simply
typed lambda-calculus with constructs, such as general
recursion (see the [MoreStlc] chapter) or recursive types, that
can be used to write nonterminating programs. However, the issue
of normalization reappears at the level of _types_ when we
consider the metatheory of polymorphic versions of the lambda
calculus such as System F-omega: in this system, the language of
types effectively contains a copy of the simply typed
lambda-calculus, and the termination of the typechecking algorithm
will hinge on the fact that a "normalization" operation on type
expressions is guaranteed to terminate.
Another reason for studying normalization proofs is that they are
some of the most beautiful---and mind-blowing---mathematics to be
found in the type theory literature, often (as here) involving the
fundamental proof technique of _logical relations_.
The calculus we shall consider here is the simply typed
lambda-calculus over a single base type [bool] and with
pairs. We'll give most details of the development for the basic
lambda-calculus terms treating [bool] as an uninterpreted base
type, and leave the extension to the boolean operators and pairs
to the reader. Even for the base calculus, normalization is not
entirely trivial to prove, since each reduction of a term can
duplicate redexes in subterms. *)
(** **** Exercise: 2 stars *)
(** Where do we fail if we attempt to prove normalization by a
straightforward induction on the size of a well-typed term? *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 5 stars, recommended *)
(** The best ways to understand an intricate proof like this is
are (1) to help fill it in and (2) to extend it. We've left out some
parts of the following development, including some proofs of lemmas
and the all the cases involving products and conditionals. Fill them
in. *)
(** [] *)
(* ###################################################################### *)
(** * Language *)
(** We begin by repeating the relevant language definition, which is
similar to those in the [MoreStlc] chapter, plus supporting
results including type preservation and step determinism. (We
won't need progress.) You may just wish to skip down to the
Normalization section... *)
(* ###################################################################### *)
(** *** Syntax and Operational Semantics *)
Require Import Coq.Lists.List.
Import ListNotations.
Require Import SfLib.
Require Import Maps.
Require Import Smallstep.
Hint Constructors multi.
Inductive ty : Type :=
| TBool : ty
| TArrow : ty -> ty -> ty
| TProd : ty -> ty -> ty
.
Inductive tm : Type :=
(* pure STLC *)
| tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
(* pairs *)
| tpair : tm -> tm -> tm
| tfst : tm -> tm
| tsnd : tm -> tm
(* booleans *)
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm.
(* i.e., [if t0 then t1 else t2] *)
(* ###################################################################### *)
(** *** Substitution *)
Fixpoint subst (x:id) (s:tm) (t:tm) : tm :=
match t with
| tvar y => if beq_id x y then s else t
| tabs y T t1 =>
tabs y T (if beq_id x y then t1 else (subst x s t1))
| tapp t1 t2 => tapp (subst x s t1) (subst x s t2)
| tpair t1 t2 => tpair (subst x s t1) (subst x s t2)
| tfst t1 => tfst (subst x s t1)
| tsnd t1 => tsnd (subst x s t1)
| ttrue => ttrue
| tfalse => tfalse
| tif t0 t1 t2 =>
tif (subst x s t0) (subst x s t1) (subst x s t2)
end.
Notation "'[' x ':=' s ']' t" := (subst x s t) (at level 20).
(* ###################################################################### *)
(** *** Reduction *)
Inductive value : tm -> Prop :=
| v_abs : forall x T11 t12,
value (tabs x T11 t12)
| v_pair : forall v1 v2,
value v1 ->
value v2 ->
value (tpair v1 v2)
| v_true : value ttrue
| v_false : value tfalse
.
Hint Constructors value.
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_AppAbs : forall x T11 t12 v2,
value v2 ->
(tapp (tabs x T11 t12) v2) ==> [x:=v2]t12
| ST_App1 : forall t1 t1' t2,
t1 ==> t1' ->
(tapp t1 t2) ==> (tapp t1' t2)
| ST_App2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tapp v1 t2) ==> (tapp v1 t2')
(* pairs *)
| ST_Pair1 : forall t1 t1' t2,
t1 ==> t1' ->
(tpair t1 t2) ==> (tpair t1' t2)
| ST_Pair2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tpair v1 t2) ==> (tpair v1 t2')
| ST_Fst : forall t1 t1',
t1 ==> t1' ->
(tfst t1) ==> (tfst t1')
| ST_FstPair : forall v1 v2,
value v1 ->
value v2 ->
(tfst (tpair v1 v2)) ==> v1
| ST_Snd : forall t1 t1',
t1 ==> t1' ->
(tsnd t1) ==> (tsnd t1')
| ST_SndPair : forall v1 v2,
value v1 ->
value v2 ->
(tsnd (tpair v1 v2)) ==> v2
(* booleans *)
| ST_IfTrue : forall t1 t2,
(tif ttrue t1 t2) ==> t1
| ST_IfFalse : forall t1 t2,
(tif tfalse t1 t2) ==> t2
| ST_If : forall t0 t0' t1 t2,
t0 ==> t0' ->
(tif t0 t1 t2) ==> (tif t0' t1 t2)
where "t1 '==>' t2" := (step t1 t2).
Notation multistep := (multi step).
Notation "t1 '==>*' t2" := (multistep t1 t2) (at level 40).
Hint Constructors step.
Notation step_normal_form := (normal_form step).
Lemma value__normal : forall t, value t -> step_normal_form t.
Proof with eauto.
intros t H; induction H; intros [t' ST]; inversion ST...
Qed.
(* ###################################################################### *)
(** *** Typing *)
Definition context := partial_map ty.
Inductive has_type : context -> tm -> ty -> Prop :=
(* Typing rules for proper terms *)
| T_Var : forall Gamma x T,
Gamma x = Some T ->
has_type Gamma (tvar x) T
| T_Abs : forall Gamma x T11 T12 t12,
has_type (update Gamma x T11) t12 T12 ->
has_type Gamma (tabs x T11 t12) (TArrow T11 T12)
| T_App : forall T1 T2 Gamma t1 t2,
has_type Gamma t1 (TArrow T1 T2) ->
has_type Gamma t2 T1 ->
has_type Gamma (tapp t1 t2) T2
(* pairs *)
| T_Pair : forall Gamma t1 t2 T1 T2,
has_type Gamma t1 T1 ->
has_type Gamma t2 T2 ->
has_type Gamma (tpair t1 t2) (TProd T1 T2)
| T_Fst : forall Gamma t T1 T2,
has_type Gamma t (TProd T1 T2) ->
has_type Gamma (tfst t) T1
| T_Snd : forall Gamma t T1 T2,
has_type Gamma t (TProd T1 T2) ->
has_type Gamma (tsnd t) T2
(* booleans *)
| T_True : forall Gamma,
has_type Gamma ttrue TBool
| T_False : forall Gamma,
has_type Gamma tfalse TBool
| T_If : forall Gamma t0 t1 t2 T,
has_type Gamma t0 TBool ->
has_type Gamma t1 T ->
has_type Gamma t2 T ->
has_type Gamma (tif t0 t1 t2) T
.
Hint Constructors has_type.
Hint Extern 2 (has_type _ (tapp _ _) _) => eapply T_App; auto.
Hint Extern 2 (_ = _) => compute; reflexivity.
(* ###################################################################### *)
(** *** Context Invariance *)
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tvar x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tapp t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tapp t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tabs y T11 t12)
(* pairs *)
| afi_pair1 : forall x t1 t2,
appears_free_in x t1 ->
appears_free_in x (tpair t1 t2)
| afi_pair2 : forall x t1 t2,
appears_free_in x t2 ->
appears_free_in x (tpair t1 t2)
| afi_fst : forall x t,
appears_free_in x t ->
appears_free_in x (tfst t)
| afi_snd : forall x t,
appears_free_in x t ->
appears_free_in x (tsnd t)
(* booleans *)
| afi_if0 : forall x t0 t1 t2,
appears_free_in x t0 ->
appears_free_in x (tif t0 t1 t2)
| afi_if1 : forall x t0 t1 t2,
appears_free_in x t1 ->
appears_free_in x (tif t0 t1 t2)
| afi_if2 : forall x t0 t1 t2,
appears_free_in x t2 ->
appears_free_in x (tif t0 t1 t2)
.
Hint Constructors appears_free_in.
Definition closed (t:tm) :=
forall x, ~ appears_free_in x t.
Lemma context_invariance : forall Gamma Gamma' t S,
has_type Gamma t S ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
has_type Gamma' t S.
Proof with eauto.
intros. generalize dependent Gamma'.
induction H;
intros Gamma' Heqv...
- (* T_Var *)
apply T_Var... rewrite <- Heqv...
- (* T_Abs *)
apply T_Abs... apply IHhas_type. intros y Hafi.
unfold update, t_update. destruct (beq_idP x y)...
- (* T_Pair *)
apply T_Pair...
- (* T_If *)
eapply T_If...
Qed.
Lemma free_in_context : forall x t T Gamma,
appears_free_in x t ->
has_type Gamma t T ->
exists T', Gamma x = Some T'.
Proof with eauto.
intros x t T Gamma Hafi Htyp.
induction Htyp; inversion Hafi; subst...
- (* T_Abs *)
destruct IHHtyp as [T' Hctx]... exists T'.
unfold update, t_update in Hctx.
rewrite false_beq_id in Hctx...
Qed.
Corollary typable_empty__closed : forall t T,
has_type empty t T ->
closed t.
Proof.
intros. unfold closed. intros x H1.
destruct (free_in_context _ _ _ _ H1 H) as [T' C].
inversion C. Qed.
(* ###################################################################### *)
(** *** Preservation *)
Lemma substitution_preserves_typing : forall Gamma x U v t S,
has_type (update Gamma x U) t S ->
has_type empty v U ->
has_type Gamma ([x:=v]t) S.
Proof with eauto.
(* Theorem: If Gamma,x:U |- t : S and empty |- v : U, then
Gamma |- ([x:=v]t) S. *)
intros Gamma x U v t S Htypt Htypv.
generalize dependent Gamma. generalize dependent S.
(* Proof: By induction on the term t. Most cases follow directly
from the IH, with the exception of tvar and tabs.
The former aren't automatic because we must reason about how the
variables interact. *)
induction t;
intros S Gamma Htypt; simpl; inversion Htypt; subst...
- (* tvar *)
simpl. rename i into y.
(* If t = y, we know that
[empty |- v : U] and
[Gamma,x:U |- y : S]
and, by inversion, [update Gamma x U y = Some S]. We want to
show that [Gamma |- [x:=v]y : S].
There are two cases to consider: either [x=y] or [x<>y]. *)
unfold update, t_update in H1.
destruct (beq_idP x y).
+ (* x=y *)
(* If [x = y], then we know that [U = S], and that [[x:=v]y = v].
So what we really must show is that if [empty |- v : U] then
[Gamma |- v : U]. We have already proven a more general version
of this theorem, called context invariance. *)
subst.
inversion H1; subst. clear H1.
eapply context_invariance...
intros x Hcontra.
destruct (free_in_context _ _ S empty Hcontra) as [T' HT']...
inversion HT'.
+ (* x<>y *)
(* If [x <> y], then [Gamma y = Some S] and the substitution has no
effect. We can show that [Gamma |- y : S] by [T_Var]. *)
apply T_Var...
- (* tabs *)
rename i into y. rename t into T11.
(* If [t = tabs y T11 t0], then we know that
[Gamma,x:U |- tabs y T11 t0 : T11->T12]
[Gamma,x:U,y:T11 |- t0 : T12]
[empty |- v : U]
As our IH, we know that forall S Gamma,
[Gamma,x:U |- t0 : S -> Gamma |- [x:=v]t0 S].
We can calculate that
[x:=v]t = tabs y T11 (if beq_id x y then t0 else [x:=v]t0)
And we must show that [Gamma |- [x:=v]t : T11->T12]. We know
we will do so using [T_Abs], so it remains to be shown that:
[Gamma,y:T11 |- if beq_id x y then t0 else [x:=v]t0 : T12]
We consider two cases: [x = y] and [x <> y].
*)
apply T_Abs...
destruct (beq_idP x y).
+ (* x=y *)
(* If [x = y], then the substitution has no effect. Context
invariance shows that [Gamma,y:U,y:T11] and [Gamma,y:T11] are
equivalent. Since the former context shows that [t0 : T12], so
does the latter. *)
eapply context_invariance...
subst.
intros x Hafi. unfold update, t_update.
destruct (beq_id y x)...
+ (* x<>y *)
(* If [x <> y], then the IH and context invariance allow us to show that
[Gamma,x:U,y:T11 |- t0 : T12] =>
[Gamma,y:T11,x:U |- t0 : T12] =>
[Gamma,y:T11 |- [x:=v]t0 : T12] *)
apply IHt. eapply context_invariance...
intros z Hafi. unfold update, t_update.
destruct (beq_idP y z)...
subst. rewrite false_beq_id...
Qed.
Theorem preservation : forall t t' T,
has_type empty t T ->
t ==> t' ->
has_type empty t' T.
Proof with eauto.
intros t t' T HT.
(* Theorem: If [empty |- t : T] and [t ==> t'], then [empty |- t' : T]. *)
remember (@empty ty) as Gamma. generalize dependent HeqGamma.
generalize dependent t'.
(* Proof: By induction on the given typing derivation. Many cases are
contradictory ([T_Var], [T_Abs]). We show just the interesting ones. *)
induction HT;
intros t' HeqGamma HE; subst; inversion HE; subst...
- (* T_App *)
(* If the last rule used was [T_App], then [t = t1 t2], and three rules
could have been used to show [t ==> t']: [ST_App1], [ST_App2], and
[ST_AppAbs]. In the first two cases, the result follows directly from
the IH. *)
inversion HE; subst...
+ (* ST_AppAbs *)
(* For the third case, suppose
[t1 = tabs x T11 t12]
and
[t2 = v2].
We must show that [empty |- [x:=v2]t12 : T2].
We know by assumption that
[empty |- tabs x T11 t12 : T1->T2]
and by inversion
[x:T1 |- t12 : T2]
We have already proven that substitution_preserves_typing and
[empty |- v2 : T1]
by assumption, so we are done. *)
apply substitution_preserves_typing with T1...
inversion HT1...
- (* T_Fst *)
inversion HT...
- (* T_Snd *)
inversion HT...
Qed.
(* ###################################################################### *)
(** *** Determinism *)
Lemma step_deterministic :
deterministic step.
Proof with eauto.
unfold deterministic.
intros t t' t'' E1 E2.
generalize dependent t''.
induction E1; intros t'' E2; inversion E2; subst; clear E2...
(* ST_AppAbs *)
- inversion H3.
- exfalso; apply value__normal in H...
(* ST_App1 *)
- inversion E1.
- f_equal...
- exfalso; apply value__normal in H1...
(* ST_App2 *)
- exfalso; apply value__normal in H3...
- exfalso; apply value__normal in H...
- f_equal...
(* ST_Pair1 *)
- f_equal...
- exfalso; apply value__normal in H1...
(* ST_Pair2 *)
- exfalso; apply value__normal in H...
- f_equal...
(* ST_Fst *)
- f_equal...
- exfalso.
inversion E1; subst.
+ apply value__normal in H0...
+ apply value__normal in H1...
(* ST_FstPair *)
- exfalso.
inversion H2; subst.
+ apply value__normal in H...
+ apply value__normal in H0...
(* ST_Snd *)
- f_equal...
- exfalso.
inversion E1; subst.
+ apply value__normal in H0...
+ apply value__normal in H1...
(* ST_SndPair *)
- exfalso.
inversion H2; subst.
+ apply value__normal in H...
+ apply value__normal in H0...
- (* ST_IfTrue *)
inversion H3.
- (* ST_IfFalse *)
inversion H3.
(* ST_If *)
- inversion E1.
- inversion E1.
- f_equal...
Qed.
(* ###################################################################### *)
(** * Normalization *)
(** Now for the actual normalization proof.
Our goal is to prove that every well-typed term reduces to a
normal form. In fact, it turns out to be convenient to prove
something slightly stronger, namely that every well-typed term
reduces to a _value_. This follows from the weaker property
anyway via Progress (why?) but otherwise we don't need Progress,
and we didn't bother re-proving it above.
Here's the key definition: *)
Definition halts (t:tm) : Prop := exists t', t ==>* t' /\ value t'.
(** A trivial fact: *)
Lemma value_halts : forall v, value v -> halts v.
Proof.
intros v H. unfold halts.
exists v. split.
apply multi_refl.
assumption.
Qed.
(** The key issue in the normalization proof (as in many proofs by
induction) is finding a strong enough induction hypothesis. To
this end, we begin by defining, for each type [T], a set [R_T] of
closed terms of type [T]. We will specify these sets using a
relation [R] and write [R T t] when [t] is in [R_T]. (The sets
[R_T] are sometimes called _saturated sets_ or _reducibility
candidates_.)
Here is the definition of [R] for the base language:
- [R bool t] iff [t] is a closed term of type [bool] and [t] halts
in a value
- [R (T1 -> T2) t] iff [t] is a closed term of type [T1 -> T2] and
[t] halts in a value _and_ for any term [s] such that [R T1 s],
we have [R T2 (t s)]. *)
(** This definition gives us the strengthened induction hypothesis that we
need. Our primary goal is to show that all _programs_ ---i.e., all
closed terms of base type---halt. But closed terms of base type can
contain subterms of functional type, so we need to know something
about these as well. Moreover, it is not enough to know that these
subterms halt, because the application of a normalized function to a
normalized argument involves a substitution, which may enable more
reduction steps. So we need a stronger condition for terms of
functional type: not only should they halt themselves, but, when
applied to halting arguments, they should yield halting results.
The form of [R] is characteristic of the _logical relations_ proof
technique. (Since we are just dealing with unary relations here, we
could perhaps more properly say _logical properties_.) If we want to
prove some property [P] of all closed terms of type [A], we proceed by
proving, by induction on types, that all terms of type [A] _possess_
property [P], all terms of type [A->A] _preserve_ property [P], all
terms of type [(A->A)->(A->A)] _preserve the property of preserving_
property [P], and so on. We do this by defining a family of
properties, indexed by types. For the base type [A], the property is
just [P]. For functional types, it says that the function should map
values satisfying the property at the input type to values satisfying
the property at the output type.
When we come to formalize the definition of [R] in Coq, we hit a
problem. The most obvious formulation would be as a parameterized
Inductive proposition like this:
Inductive R : ty -> tm -> Prop :=
| R_bool : forall b t, has_type empty t TBool ->
halts t ->
R TBool t
| R_arrow : forall T1 T2 t, has_type empty t (TArrow T1 T2) ->
halts t ->
(forall s, R T1 s -> R T2 (tapp t s)) ->
R (TArrow T1 T2) t.
Unfortunately, Coq rejects this definition because it violates the
_strict positivity requirement_ for inductive definitions, which says
that the type being defined must not occur to the left of an arrow in
the type of a constructor argument. Here, it is the third argument to
[R_arrow], namely [(forall s, R T1 s -> R TS (tapp t s))], and
specifically the [R T1 s] part, that violates this rule. (The
outermost arrows separating the constructor arguments don't count when
applying this rule; otherwise we could never have genuinely inductive
properties at all!) The reason for the rule is that types defined
with non-positive recursion can be used to build non-terminating
functions, which as we know would be a disaster for Coq's logical
soundness. Even though the relation we want in this case might be
perfectly innocent, Coq still rejects it because it fails the
positivity test.
Fortunately, it turns out that we _can_ define [R] using a
[Fixpoint]: *)
Fixpoint R (T:ty) (t:tm) {struct T} : Prop :=
has_type empty t T /\ halts t /\
(match T with
| TBool => True
| TArrow T1 T2 => (forall s, R T1 s -> R T2 (tapp t s))
(* ... edit the next line when dealing with products *)
| TProd T1 T2 => False
end).
(** As immediate consequences of this definition, we have that every
element of every set [R_T] halts in a value and is closed with type
[t] :*)
Lemma R_halts : forall {T} {t}, R T t -> halts t.
Proof.
intros. destruct T; unfold R in H; inversion H; inversion H1; assumption.
Qed.
Lemma R_typable_empty : forall {T} {t}, R T t -> has_type empty t T.
Proof.
intros. destruct T; unfold R in H; inversion H; inversion H1; assumption.
Qed.
(** Now we proceed to show the main result, which is that every
well-typed term of type [T] is an element of [R_T]. Together with
[R_halts], that will show that every well-typed term halts in a
value. *)
(* ###################################################################### *)
(** ** Membership in [R_T] Is Invariant Under Reduction *)
(** We start with a preliminary lemma that shows a kind of strong
preservation property, namely that membership in [R_T] is _invariant_
under reduction. We will need this property in both directions,
i.e., both to show that a term in [R_T] stays in [R_T] when it takes a
forward step, and to show that any term that ends up in [R_T] after a
step must have been in [R_T] to begin with.
First of all, an easy preliminary lemma. Note that in the forward
direction the proof depends on the fact that our language is
determinstic. This lemma might still be true for nondeterministic
languages, but the proof would be harder! *)
Lemma step_preserves_halting : forall t t', (t ==> t') -> (halts t <-> halts t').
Proof.
intros t t' ST. unfold halts.
split.
- (* -> *)
intros [t'' [STM V]].
inversion STM; subst.
exfalso. apply value__normal in V. unfold normal_form in V. apply V. exists t'. auto.
rewrite (step_deterministic _ _ _ ST H). exists t''. split; assumption.
- (* <- *)
intros [t'0 [STM V]].
exists t'0. split; eauto.
Qed.
(** Now the main lemma, which comes in two parts, one for each
direction. Each proceeds by induction on the structure of the type
[T]. In fact, this is where we make fundamental use of the
structure of types.
One requirement for staying in [R_T] is to stay in type [T]. In the
forward direction, we get this from ordinary type Preservation. *)
Lemma step_preserves_R : forall T t t', (t ==> t') -> R T t -> R T t'.
Proof.
induction T; intros t t' E Rt; unfold R; fold R; unfold R in Rt; fold R in Rt;
destruct Rt as [typable_empty_t [halts_t RRt]].
(* TBool *)
split. eapply preservation; eauto.
split. apply (step_preserves_halting _ _ E); eauto.
auto.
(* TArrow *)
split. eapply preservation; eauto.
split. apply (step_preserves_halting _ _ E); eauto.
intros.
eapply IHT2.
apply ST_App1. apply E.
apply RRt; auto.
(* FILL IN HERE *) Admitted.
(** The generalization to multiple steps is trivial: *)
Lemma multistep_preserves_R : forall T t t',
(t ==>* t') -> R T t -> R T t'.
Proof.
intros T t t' STM; induction STM; intros.
assumption.
apply IHSTM. eapply step_preserves_R. apply H. assumption.
Qed.
(** In the reverse direction, we must add the fact that [t] has type
[T] before stepping as an additional hypothesis. *)
Lemma step_preserves_R' : forall T t t',
has_type empty t T -> (t ==> t') -> R T t' -> R T t.
Proof.
(* FILL IN HERE *) Admitted.
Lemma multistep_preserves_R' : forall T t t',
has_type empty t T -> (t ==>* t') -> R T t' -> R T t.
Proof.
intros T t t' HT STM.
induction STM; intros.
assumption.
eapply step_preserves_R'. assumption. apply H. apply IHSTM.
eapply preservation; eauto. auto.
Qed.
(* ###################################################################### *)
(** ** Closed Instances of Terms of Type [t] Belong to [R_T] *)
(** Now we proceed to show that every term of type [T] belongs to
[R_T]. Here, the induction will be on typing derivations (it would be
surprising to see a proof about well-typed terms that did not
somewhere involve induction on typing derivations!). The only
technical difficulty here is in dealing with the abstraction case.
Since we are arguing by induction, the demonstration that a term
[tabs x T1 t2] belongs to [R_(T1->T2)] should involve applying the
induction hypothesis to show that [t2] belongs to [R_(T2)]. But
[R_(T2)] is defined to be a set of _closed_ terms, while [t2] may
contain [x] free, so this does not make sense.
This problem is resolved by using a standard trick to suitably
generalize the induction hypothesis: instead of proving a statement
involving a closed term, we generalize it to cover all closed
_instances_ of an open term [t]. Informally, the statement of the
lemma will look like this:
If [x1:T1,..xn:Tn |- t : T] and [v1,...,vn] are values such that
[R T1 v1], [R T2 v2], ..., [R Tn vn], then
[R T ([x1:=v1][x2:=v2]...[xn:=vn]t)].
The proof will proceed by induction on the typing derivation
[x1:T1,..xn:Tn |- t : T]; the most interesting case will be the one
for abstraction. *)
(* ###################################################################### *)
(** *** Multisubstitutions, Multi-Extensions, and Instantiations *)
(** However, before we can proceed to formalize the statement and
proof of the lemma, we'll need to build some (rather tedious)
machinery to deal with the fact that we are performing _multiple_
substitutions on term [t] and _multiple_ extensions of the typing
context. In particular, we must be precise about the order in which
the substitutions occur and how they act on each other. Often these
details are simply elided in informal paper proofs, but of course Coq
won't let us do that. Since here we are substituting closed terms, we
don't need to worry about how one substitution might affect the term
put in place by another. But we still do need to worry about the
_order_ of substitutions, because it is quite possible for the same
identifier to appear multiple times among the [x1,...xn] with
different associated [vi] and [Ti].
To make everything precise, we will assume that environments are
extended from left to right, and multiple substitutions are performed
from right to left. To see that this is consistent, suppose we have
an environment written as [...,y:bool,...,y:nat,...] and a
corresponding term substitution written as [...[y:=(tbool
true)]...[y:=(tnat 3)]...t]. Since environments are extended from
left to right, the binding [y:nat] hides the binding [y:bool]; since
substitutions are performed right to left, we do the substitution
[y:=(tnat 3)] first, so that the substitution [y:=(tbool true)] has
no effect. Substitution thus correctly preserves the type of the term.
With these points in mind, the following definitions should make sense.
A _multisubstitution_ is the result of applying a list of
substitutions, which we call an _environment_. *)
Definition env := list (id * tm).
Fixpoint msubst (ss:env) (t:tm) {struct ss} : tm :=
match ss with
| nil => t
| ((x,s)::ss') => msubst ss' ([x:=s]t)
end.
(** We need similar machinery to talk about repeated extension of a
typing context using a list of (identifier, type) pairs, which we
call a _type assignment_. *)
Definition tass := list (id * ty).
Fixpoint mupdate (Gamma : context) (xts : tass) :=
match xts with
| nil => Gamma
| ((x,v)::xts') => update (mupdate Gamma xts') x v
end.
(** We will need some simple operations that work uniformly on
environments and type assigments *)
Fixpoint lookup {X:Set} (k : id) (l : list (id * X)) {struct l}
: option X :=
match l with
| nil => None
| (j,x) :: l' =>
if beq_id j k then Some x else lookup k l'
end.
Fixpoint drop {X:Set} (n:id) (nxs:list (id * X)) {struct nxs}
: list (id * X) :=
match nxs with
| nil => nil
| ((n',x)::nxs') =>
if beq_id n' n then drop n nxs'
else (n',x)::(drop n nxs')
end.
(** An _instantiation_ combines a type assignment and a value
environment with the same domains, where corresponding elements are
in R. *)
Inductive instantiation : tass -> env -> Prop :=
| V_nil :
instantiation nil nil
| V_cons : forall x T v c e,
value v -> R T v ->
instantiation c e ->
instantiation ((x,T)::c) ((x,v)::e).
(** We now proceed to prove various properties of these definitions. *)
(* ###################################################################### *)
(** *** More Substitution Facts *)
(** First we need some additional lemmas on (ordinary) substitution. *)
Lemma vacuous_substitution : forall t x,
~ appears_free_in x t ->
forall t', [x:=t']t = t.
Proof with eauto.
(* FILL IN HERE *) Admitted.
Lemma subst_closed: forall t,
closed t ->
forall x t', [x:=t']t = t.
Proof.
intros. apply vacuous_substitution. apply H. Qed.
Lemma subst_not_afi : forall t x v,
closed v -> ~ appears_free_in x ([x:=v]t).
Proof with eauto. (* rather slow this way *)
unfold closed, not.
induction t; intros x v P A; simpl in A.
- (* tvar *)
destruct (beq_idP x i)...
inversion A; subst. auto.
- (* tapp *)
inversion A; subst...
- (* tabs *)
destruct (beq_idP x i)...
+ inversion A; subst...
+ inversion A; subst...
- (* tpair *)
inversion A; subst...
- (* tfst *)
inversion A; subst...
- (* tsnd *)
inversion A; subst...
- (* ttrue *)
inversion A.
- (* tfalse *)
inversion A.
- (* tif *)
inversion A; subst...
Qed.
Lemma duplicate_subst : forall t' x t v,
closed v -> [x:=t]([x:=v]t') = [x:=v]t'.
Proof.
intros. eapply vacuous_substitution. apply subst_not_afi. auto.
Qed.
Lemma swap_subst : forall t x x1 v v1,
x <> x1 ->
closed v -> closed v1 ->
[x1:=v1]([x:=v]t) = [x:=v]([x1:=v1]t).
Proof with eauto.
induction t; intros; simpl.
- (* tvar *)
destruct (beq_idP x i); destruct (beq_idP x1 i).
+ subst. exfalso...
+ subst. simpl. rewrite <- beq_id_refl. apply subst_closed...
+ subst. simpl. rewrite <- beq_id_refl. rewrite subst_closed...
+ simpl. rewrite false_beq_id... rewrite false_beq_id...
(* FILL IN HERE *) Admitted.
(* ###################################################################### *)
(** *** Properties of Multi-Substitutions *)
Lemma msubst_closed: forall t, closed t -> forall ss, msubst ss t = t.
Proof.
induction ss.
reflexivity.
destruct a. simpl. rewrite subst_closed; assumption.
Qed.
(** Closed environments are those that contain only closed terms. *)
Fixpoint closed_env (env:env) {struct env} :=
match env with
| nil => True
| (x,t)::env' => closed t /\ closed_env env'
end.
(** Next come a series of lemmas charcterizing how [msubst] of closed terms
distributes over [subst] and over each term form *)
Lemma subst_msubst: forall env x v t, closed v -> closed_env env ->
msubst env ([x:=v]t) = [x:=v](msubst (drop x env) t).
Proof.
induction env0; intros; auto.
destruct a. simpl.
inversion H0. fold closed_env in H2.
destruct (beq_idP i x).
- subst. rewrite duplicate_subst; auto.
- simpl. rewrite swap_subst; eauto.
Qed.
Lemma msubst_var: forall ss x, closed_env ss ->
msubst ss (tvar x) =
match lookup x ss with
| Some t => t
| None => tvar x
end.
Proof.
induction ss; intros.
reflexivity.
destruct a.
simpl. destruct (beq_id i x).
apply msubst_closed. inversion H; auto.
apply IHss. inversion H; auto.
Qed.
Lemma msubst_abs: forall ss x T t,
msubst ss (tabs x T t) = tabs x T (msubst (drop x ss) t).
Proof.
induction ss; intros.
reflexivity.
destruct a.
simpl. destruct (beq_id i x); simpl; auto.
Qed.
Lemma msubst_app : forall ss t1 t2, msubst ss (tapp t1 t2) = tapp (msubst ss t1) (msubst ss t2).
Proof.
induction ss; intros.
reflexivity.
destruct a.
simpl. rewrite <- IHss. auto.
Qed.
(** You'll need similar functions for the other term constructors. *)
(* FILL IN HERE *)
(* ###################################################################### *)
(** *** Properties of Multi-Extensions *)
(** We need to connect the behavior of type assignments with that of
their corresponding contexts. *)
Lemma mupdate_lookup : forall (c : tass) (x:id),
lookup x c = (mupdate empty c) x.
Proof.
induction c; intros.
auto.
destruct a. unfold lookup, mupdate, update, t_update. destruct (beq_id i x); auto.
Qed.
Lemma mupdate_drop : forall (c: tass) Gamma x x',
mupdate Gamma (drop x c) x'
= if beq_id x x' then Gamma x' else mupdate Gamma c x'.
Proof.
induction c; intros.
- destruct (beq_idP x x'); auto.
- destruct a. simpl.
destruct (beq_idP i x).
+ subst. rewrite IHc.
unfold update, t_update. destruct (beq_idP x x'); auto.
+ simpl. unfold update, t_update. destruct (beq_idP i x'); auto.
subst. rewrite false_beq_id; congruence.
Qed.
(* ###################################################################### *)
(** *** Properties of Instantiations *)
(** These are strightforward. *)
Lemma instantiation_domains_match: forall {c} {e},
instantiation c e ->
forall {x} {T},
lookup x c = Some T -> exists t, lookup x e = Some t.
Proof.
intros c e V. induction V; intros x0 T0 C.
solve by inversion .
simpl in *.
destruct (beq_id x x0); eauto.
Qed.
Lemma instantiation_env_closed : forall c e,
instantiation c e -> closed_env e.
Proof.
intros c e V; induction V; intros.
econstructor.
unfold closed_env. fold closed_env.
split. eapply typable_empty__closed. eapply R_typable_empty. eauto.
auto.
Qed.
Lemma instantiation_R : forall c e,
instantiation c e ->
forall x t T,
lookup x c = Some T ->
lookup x e = Some t -> R T t.
Proof.
intros c e V. induction V; intros x' t' T' G E.
solve by inversion.
unfold lookup in *. destruct (beq_id x x').
inversion G; inversion E; subst. auto.
eauto.
Qed.
Lemma instantiation_drop : forall c env,
instantiation c env ->
forall x, instantiation (drop x c) (drop x env).
Proof.
intros c e V. induction V.
intros. simpl. constructor.
intros. unfold drop. destruct (beq_id x x0); auto. constructor; eauto.
Qed.
(* ###################################################################### *)
(** *** Congruence Lemmas on Multistep *)
(** We'll need just a few of these; add them as the demand arises. *)
Lemma multistep_App2 : forall v t t',
value v -> (t ==>* t') -> (tapp v t) ==>* (tapp v t').
Proof.
intros v t t' V STM. induction STM.
apply multi_refl.
eapply multi_step.
apply ST_App2; eauto. auto.
Qed.
(* FILL IN HERE *)
(* ###################################################################### *)
(** *** The R Lemma. *)
(** We can finally put everything together.
The key lemma about preservation of typing under substitution can
be lifted to multi-substitutions: *)
Lemma msubst_preserves_typing : forall c e,
instantiation c e ->
forall Gamma t S, has_type (mupdate Gamma c) t S ->
has_type Gamma (msubst e t) S.
Proof.
induction 1; intros.
simpl in H. simpl. auto.
simpl in H2. simpl.
apply IHinstantiation.
eapply substitution_preserves_typing; eauto.
apply (R_typable_empty H0).
Qed.
(** And at long last, the main lemma. *)
Lemma msubst_R : forall c env t T,
has_type (mupdate empty c) t T ->
instantiation c env ->
R T (msubst env t).
Proof.
intros c env0 t T HT V.
generalize dependent env0.
(* We need to generalize the hypothesis a bit before setting up the induction. *)
remember (mupdate empty c) as Gamma.
assert (forall x, Gamma x = lookup x c).
intros. rewrite HeqGamma. rewrite mupdate_lookup. auto.
clear HeqGamma.
generalize dependent c.
induction HT; intros.
- (* T_Var *)
rewrite H0 in H. destruct (instantiation_domains_match V H) as [t P].
eapply instantiation_R; eauto.
rewrite msubst_var. rewrite P. auto. eapply instantiation_env_closed; eauto.
- (* T_Abs *)
rewrite msubst_abs.
(* We'll need variants of the following fact several times, so its simplest to
establish it just once. *)
assert (WT: has_type empty (tabs x T11 (msubst (drop x env0) t12)) (TArrow T11 T12)).
{ eapply T_Abs. eapply msubst_preserves_typing.
{ eapply instantiation_drop; eauto. }
eapply context_invariance.
{ apply HT. }
intros.
unfold update, t_update. rewrite mupdate_drop. destruct (beq_idP x x0).
+ auto.
+ rewrite H.
clear - c n. induction c.
simpl. rewrite false_beq_id; auto.
simpl. destruct a. unfold update, t_update.
destruct (beq_id i x0); auto. }
unfold R. fold R. split.
auto.
split. apply value_halts. apply v_abs.
intros.
destruct (R_halts H0) as [v [P Q]].
pose proof (multistep_preserves_R _ _ _ P H0).
apply multistep_preserves_R' with (msubst ((x,v)::env0) t12).
eapply T_App. eauto.
apply R_typable_empty; auto.
eapply multi_trans. eapply multistep_App2; eauto.
eapply multi_R.
simpl. rewrite subst_msubst.
eapply ST_AppAbs; eauto.
eapply typable_empty__closed.
apply (R_typable_empty H1).
eapply instantiation_env_closed; eauto.
eapply (IHHT ((x,T11)::c)).
intros. unfold update, t_update, lookup. destruct (beq_id x x0); auto.
constructor; auto.
- (* T_App *)
rewrite msubst_app.
destruct (IHHT1 c H env0 V) as [_ [_ P1]].
pose proof (IHHT2 c H env0 V) as P2. fold R in P1. auto.
(* FILL IN HERE *) Admitted.
(* ###################################################################### *)
(** *** Normalization Theorem *)
Theorem normalization : forall t T, has_type empty t T -> halts t.
Proof.
intros.
replace t with (msubst nil t) by reflexivity.
apply (@R_halts T).
apply (msubst_R nil); eauto.
eapply V_nil.
Qed.
(** $Date: 2016-05-26 16:17:19 -0400 (Thu, 26 May 2016) $ *)
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_3_axi_basic_tx.v
// Version : 1.3
// //
// Description: //
// AXI to TRN TX module. Instantiates pipeline and throttle control TX //
// submodules. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_tx //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie_7x_v1_3_axi_basic_tx #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI TX
//-----------
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
input s_axis_tx_tvalid, // TX data is valid
output s_axis_tx_tready, // TX ready for data
input [KEEP_WIDTH-1:0] s_axis_tx_tkeep, // TX strobe byte enables
input s_axis_tx_tlast, // TX data is last
input [3:0] s_axis_tx_tuser, // TX user signals
// User Misc.
//-----------
input user_turnoff_ok, // Turnoff OK from user
input user_tcfg_gnt, // Send cfg OK from user
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN TX
//-----------
output [C_DATA_WIDTH-1:0] trn_td, // TX data from block
output trn_tsof, // TX start of packet
output trn_teof, // TX end of packet
output trn_tsrc_rdy, // TX source ready
input trn_tdst_rdy, // TX destination ready
output trn_tsrc_dsc, // TX source discontinue
output [REM_WIDTH-1:0] trn_trem, // TX remainder
output trn_terrfwd, // TX error forward
output trn_tstr, // TX streaming enable
input [5:0] trn_tbuf_av, // TX buffers available
output trn_tecrc_gen, // TX ECRC generate
// TRN Misc.
//-----------
input trn_tcfg_req, // TX config request
output trn_tcfg_gnt, // RX config grant
input trn_lnk_up, // PCIe link up
// 7 Series/Virtex6 PM
//-----------
input [2:0] cfg_pcie_link_state, // Encoded PCIe link state
// Virtex6 PM
//-----------
input cfg_pm_send_pme_to, // PM send PME turnoff msg
input [1:0] cfg_pmcsr_powerstate, // PMCSR power state
input [31:0] trn_rdllp_data, // RX DLLP data
input trn_rdllp_src_rdy, // RX DLLP source ready
// Virtex6/Spartan6 PM
//-----------
input cfg_to_turnoff, // Turnoff request
output cfg_turnoff_ok, // Turnoff grant
// System
//-----------
input user_clk, // user clock from block
input user_rst // user reset from block
);
wire tready_thrtl;
//---------------------------------------------//
// TX Data Pipeline //
//---------------------------------------------//
pcie_7x_v1_3_axi_basic_tx_pipeline #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_PM_PRIORITY( C_PM_PRIORITY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) tx_pipeline_inst (
// Incoming AXI RX
//-----------
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tready( s_axis_tx_tready ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.s_axis_tx_tkeep( s_axis_tx_tkeep ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
// Outgoing TRN TX
//-----------
.trn_td( trn_td ),
.trn_tsof( trn_tsof ),
.trn_teof( trn_teof ),
.trn_tsrc_rdy( trn_tsrc_rdy ),
.trn_tdst_rdy( trn_tdst_rdy ),
.trn_tsrc_dsc( trn_tsrc_dsc ),
.trn_trem( trn_trem ),
.trn_terrfwd( trn_terrfwd ),
.trn_tstr( trn_tstr ),
.trn_tecrc_gen( trn_tecrc_gen ),
.trn_lnk_up( trn_lnk_up ),
// System
//-----------
.tready_thrtl( tready_thrtl ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
//---------------------------------------------//
// TX Throttle Controller //
//---------------------------------------------//
generate
if(C_PM_PRIORITY == "FALSE") begin : thrtl_ctl_enabled
pcie_7x_v1_3_axi_basic_tx_thrtl_ctl #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.C_ROOT_PORT( C_ROOT_PORT ),
.TCQ( TCQ )
) tx_thrl_ctl_inst (
// Outgoing AXI TX
//-----------
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
// User Misc.
//-----------
.user_turnoff_ok( user_turnoff_ok ),
.user_tcfg_gnt( user_tcfg_gnt ),
// Incoming TRN RX
//-----------
.trn_tbuf_av( trn_tbuf_av ),
.trn_tdst_rdy( trn_tdst_rdy ),
// TRN Misc.
//-----------
.trn_tcfg_req( trn_tcfg_req ),
.trn_tcfg_gnt( trn_tcfg_gnt ),
.trn_lnk_up( trn_lnk_up ),
// 7 Seriesq/Virtex6 PM
//-----------
.cfg_pcie_link_state( cfg_pcie_link_state ),
// Virtex6 PM
//-----------
.cfg_pm_send_pme_to( cfg_pm_send_pme_to ),
.cfg_pmcsr_powerstate( cfg_pmcsr_powerstate ),
.trn_rdllp_data( trn_rdllp_data ),
.trn_rdllp_src_rdy( trn_rdllp_src_rdy ),
// Spartan6 PM
//-----------
.cfg_to_turnoff( cfg_to_turnoff ),
.cfg_turnoff_ok( cfg_turnoff_ok ),
// System
//-----------
.tready_thrtl( tready_thrtl ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
end
else begin : thrtl_ctl_disabled
assign tready_thrtl = 1'b0;
assign cfg_turnoff_ok = user_turnoff_ok;
assign trn_tcfg_gnt = user_tcfg_gnt;
end
endgenerate
endmodule
|
module division_factor(div, mul, shift);
input [7:0] div;
output [15:0] mul;
output [8:0] shift;
reg [15:0] mul;
reg [8:0] shift;
always @(div)
begin
case(div)
8'd1: begin mul = 16'd1; shift = 8'd0; end
8'd2: begin mul = 16'd1; shift = 8'd1; end
8'd3: begin mul = 16'd21845; shift = 8'd16; end
8'd4: begin mul = 16'd1; shift = 8'd2; end
8'd5: begin mul = 16'd13107; shift = 8'd16; end
8'd6: begin mul = 16'd10923; shift = 8'd16; end
8'd7: begin mul = 16'd9362; shift = 8'd16; end
8'd8: begin mul = 16'd1; shift = 8'd3; end
8'd9: begin mul = 16'd7282; shift = 8'd16; end
8'd10:begin mul = 16'd6554; shift = 8'd16; end
8'd11:begin mul = 16'd5958; shift = 8'd16; end
8'd12:begin mul = 16'd5461; shift = 8'd16; end
8'd13:begin mul = 16'd5041; shift = 8'd16; end
8'd14:begin mul = 16'd4681; shift = 8'd16; end
8'd15:begin mul = 16'd4369; shift = 8'd16; end
8'd16:begin mul = 16'd1; shift = 8'd4; end
8'd17:begin mul = 16'd3855; shift = 8'd16; end
8'd18:begin mul = 16'd3641; shift = 8'd16; end
8'd19:begin mul = 16'd3449; shift = 8'd16; end
8'd20:begin mul = 16'd3277; shift = 8'd16; end
8'd21:begin mul = 16'd3121; shift = 8'd16; end
8'd22:begin mul = 16'd2979; shift = 8'd16; end
8'd23:begin mul = 16'd2849; shift = 8'd16; end
8'd24:begin mul = 16'd2731; shift = 8'd16; end
8'd25:begin mul = 16'd2621; shift = 8'd16; end
8'd26:begin mul = 16'd2521; shift = 8'd16; end
8'd27:begin mul = 16'd2427; shift = 8'd16; end
8'd28:begin mul = 16'd2341; shift = 8'd16; end
8'd29:begin mul = 16'd2260; shift = 8'd16; end
8'd30:begin mul = 16'd2185; shift = 8'd16; end
default: begin mul = 16'd1; shift = 8'd0; end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SEDFXBP_TB_V
`define SKY130_FD_SC_LS__SEDFXBP_TB_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__sedfxbp.v"
module top();
// Inputs are registered
reg D;
reg DE;
reg SCD;
reg SCE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
DE = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 DE = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 D = 1'b1;
#200 DE = 1'b1;
#220 SCD = 1'b1;
#240 SCE = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 D = 1'b0;
#360 DE = 1'b0;
#380 SCD = 1'b0;
#400 SCE = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 SCE = 1'b1;
#600 SCD = 1'b1;
#620 DE = 1'b1;
#640 D = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 SCE = 1'bx;
#760 SCD = 1'bx;
#780 DE = 1'bx;
#800 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_ls__sedfxbp dut (.D(D), .DE(DE), .SCD(SCD), .SCE(SCE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__SEDFXBP_TB_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
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// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
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// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
module cf_spi (
spi_cs0n,
spi_cs1n,
spi_clk,
spi_sd_o,
spi_sd_i,
up_rstn,
up_clk,
up_spi_start,
up_spi_devsel,
up_spi_wdata_1,
up_spi_wdata_0,
up_spi_rdata,
up_spi_status,
debug_trigger,
debug_data);
output spi_cs0n;
output spi_cs1n;
output spi_clk;
output spi_sd_o;
input spi_sd_i;
input up_rstn;
input up_clk;
input up_spi_start;
input up_spi_devsel;
input [31:0] up_spi_wdata_1;
input [15:0] up_spi_wdata_0;
output [ 7:0] up_spi_rdata;
output up_spi_status;
output [ 7:0] debug_trigger;
output [63:0] debug_data;
reg spi_cs0n = 'd0;
reg spi_cs1n = 'd0;
reg spi_clk = 'd0;
reg spi_sd_o = 'd0;
reg spi_count_5_d = 'd0;
reg [ 2:0] spi_clk_count = 'd0;
reg [ 5:0] spi_count = 'd0;
reg spi_rwn = 'd0;
reg [31:0] spi_data_out = 'd0;
reg [ 7:0] spi_data_in = 'd0;
reg up_spi_start_d = 'd0;
reg up_spi_status = 'd0;
reg [ 7:0] up_spi_rdata = 'd0;
wire spi_cs_en_s;
wire [31:0] up_spi_wdata_s;
assign debug_trigger[7] = spi_cs0n;
assign debug_trigger[6] = spi_cs1n;
assign debug_trigger[5] = spi_clk_count[2];
assign debug_trigger[4] = spi_count[5];
assign debug_trigger[3] = up_spi_devsel;
assign debug_trigger[2] = up_spi_start;
assign debug_trigger[1] = up_spi_start_d;
assign debug_trigger[0] = up_spi_status;
assign debug_data[63:56] = 'd0;
assign debug_data[55:55] = spi_cs_en_s;
assign debug_data[54:54] = spi_cs0n;
assign debug_data[53:53] = spi_cs1n;
assign debug_data[52:52] = spi_clk;
assign debug_data[51:51] = spi_sd_o;
assign debug_data[50:50] = spi_count_5_d;
assign debug_data[49:47] = spi_clk_count;
assign debug_data[46:41] = spi_count;
assign debug_data[40:40] = spi_rwn;
assign debug_data[39: 8] = spi_data_out;
assign debug_data[ 7: 0] = spi_data_in;
assign spi_cs_en_s = spi_count_5_d | spi_count[5];
assign up_spi_wdata_s = (up_spi_devsel == 1) ? up_spi_wdata_1 : {up_spi_wdata_0, 16'd0};
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
spi_cs0n <= 'd1;
spi_cs1n <= 'd1;
spi_clk <= 'd0;
spi_sd_o <= 'd0;
spi_count_5_d <= 'd0;
spi_clk_count <= 'd0;
spi_count <= 'd0;
spi_rwn <= 'd0;
spi_data_out <= 'd0;
spi_data_in <= 'd0;
up_spi_start_d <= 'd0;
up_spi_status <= 'd0;
up_spi_rdata <= 'd0;
end else begin
spi_cs0n <= up_spi_devsel | (~spi_cs_en_s);
spi_cs1n <= (~up_spi_devsel) | (~spi_cs_en_s);
spi_clk <= spi_clk_count[2] & spi_count[5];
if ((spi_count_5_d == 1'b0) || (spi_count[5] == 1'b1)) begin
spi_sd_o <= spi_data_out[31];
end
if (spi_clk_count == 3'b100) begin
spi_count_5_d <= spi_count[5];
end
spi_clk_count <= spi_clk_count + 1'b1;
if (spi_count[5] == 1'b1) begin
if (spi_clk_count == 3'b111) begin
spi_count <= spi_count + 1'b1;
end
spi_rwn <= spi_rwn;
if (spi_clk_count == 3'b111) begin
spi_data_out <= {spi_data_out[30:0], 1'b0};
end
if ((spi_clk_count == 3'b100) && (spi_rwn == 1'b1) && (spi_count[3] == 1'b1)) begin
spi_data_in <= {spi_data_in[6:0], spi_sd_i};
end
end else if ((spi_clk_count == 3'b111) && (up_spi_start == 1'b1) &&
(up_spi_start_d == 1'b0)) begin
spi_count <= (up_spi_devsel == 1'b1) ? 6'h20 : 6'h30;
spi_rwn <= (~up_spi_devsel) & up_spi_wdata_s[31];
spi_data_out <= up_spi_wdata_s;
spi_data_in <= 8'd0;
end
if (spi_clk_count == 3'b111) begin
up_spi_start_d <= up_spi_start;
end
up_spi_status <= ~(spi_count[5] | (up_spi_start & ~up_spi_start_d));
up_spi_rdata <= spi_data_in;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O2BB2AI_4_V
`define SKY130_FD_SC_HS__O2BB2AI_4_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog wrapper for o2bb2ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o2bb2ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o2bb2ai_4 (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o2bb2ai base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o2bb2ai_4 (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o2bb2ai base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O2BB2AI_4_V
|
// Single-Port BRAM with Byte-wide Write Enable
// Read-First mode
// Single-process description
// Compact description of the write with a generate-for
// statement
// Column width and number of columns easily configurable
//
// bytewrite_ram_1b.v
//
module bytewrite_ram_1b (clk, we, addr, din, dout);
parameter SIZE = 1024;
parameter ADDR_WIDTH = 12;
parameter COL_WIDTH = 8;
parameter NB_COL = 4;
parameter filename = "code.hex";
input clk;
input [NB_COL-1:0] we;
input [ADDR_WIDTH-1:0] addr;
input [NB_COL*COL_WIDTH-1:0] din;
output reg [NB_COL*COL_WIDTH-1:0] dout;
reg [NB_COL*COL_WIDTH-1:0] RAM [SIZE-1:0];
integer _i;
initial begin
`ifndef IVERILOG
$readmemh(filename,RAM);
`endif
#10;
// Just for debugging readmemh in case it does not work as expected
for(_i=0;_i<6;_i=_i+1) begin
$display("idx : %d data : %x",_i,RAM[_i]);
end
$display("======================");
end
always @(posedge clk)
begin
dout <= RAM[addr];
end
generate genvar i;
for (i = 0; i < NB_COL; i = i+1)
begin
always @(posedge clk)
begin
if (we[i])
RAM[addr][(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= din[(i+1)*COL_WIDTH-1:i*COL_WIDTH];
end
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__MUX2_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__MUX2_BEHAVIORAL_V
/**
* mux2: 2-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_hvl__mux2 (
X ,
A0,
A1,
S
);
// Module ports
output X ;
input A0;
input A1;
input S ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire mux_2to10_out_X;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_2to10_out_X, A0, A1, S );
buf buf0 (X , mux_2to10_out_X);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__MUX2_BEHAVIORAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:12:42 05/20/2015
// Design Name:
// Module Name: ALU
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ALU(
input[31:0] A,
input[31:0] B,
input[1:0] ALUop,
input[5:0] Func,
output[31:0] result,
output ZF
);
//adition or subtraction
wire AddOrSub,SF,OF;
wire[63:0] AddOrSubResult;
assign AddOrSub =
(ALUop[1]==0) & ALUop[0] |
(ALUop[1]==1) & Func[1];
AdderAndSubber64 adder64 (
.A({ {32{A[31]}}, A}),
.B({ {32{B[31]}}, B}),
.mode(AddOrSub),
.result(AddOrSubResult),
.OF(OF),
.SF(SF),
.ZF(ZF),
.CF(CF)/*,
.PF(PF)*/
);
//rotation
wire[31:0] RotatorOut;
Rotator rotator (
.RotatorIn(B),
.RotatorBitNum(A[4:0]),
.RotatorOp(Func[1:0]),
.RotatorOut(RotatorOut)
);
//mul
wire[31:0] mulResult;
assign mulResult = A*B;
assign result =
{32{ALUop[1]==0}} & AddOrSubResult |
{32{ALUop[1]==1}} & (
{32{Func[5:3]==3'b000}} & RotatorOut | // sll srl sra sllv srlv srav
{32{Func[5:2]==4'b1000}} & AddOrSubResult | //sub or and
{32{Func[5:0]==6'b100100}} & (A & B) |//and
{32{Func[5:0]==6'b100101}} & (A | B) |//or
{32{Func[5:0]==6'b100110}} & (A ^ B) |//xor
{32{Func[5:0]==6'b100111}} & ~(A | B) |//nor
{32{Func[5:0]==6'b101010}} & {31'h0,SF^OF} |//slt
{32{Func[5:0]==6'b101011}} & {31'h0,~CF} |//sltu
{32{Func[5:0]==6'b111111}} & mulResult
);
endmodule
|
(* src = "../../verilog/adt7410.v:1" *)
module ADT7410 (
(* intersynth_port = "Reset_n_i", src = "../../verilog/adt7410.v:3" *)
input Reset_n_i,
(* intersynth_port = "Clk_i", src = "../../verilog/adt7410.v:5" *)
input Clk_i,
(* intersynth_conntype = "Bit", intersynth_port = "ReconfModuleIn_s", src = "../../verilog/adt7410.v:7" *)
input Enable_i,
(* intersynth_conntype = "Bit", intersynth_port = "ReconfModuleIRQs_s", src = "../../verilog/adt7410.v:9" *)
output CpuIntr_o,
(* intersynth_conntype = "Bit", intersynth_port = "I2C_ReceiveSend_n", src = "../../verilog/adt7410.v:11" *)
output I2C_ReceiveSend_n_o,
(* intersynth_conntype = "Byte", intersynth_port = "I2C_ReadCount", src = "../../verilog/adt7410.v:13" *)
output[7:0] I2C_ReadCount_o,
(* intersynth_conntype = "Bit", intersynth_port = "I2C_StartProcess", src = "../../verilog/adt7410.v:15" *)
output I2C_StartProcess_o,
(* intersynth_conntype = "Bit", intersynth_port = "I2C_Busy", src = "../../verilog/adt7410.v:17" *)
input I2C_Busy_i,
(* intersynth_conntype = "Bit", intersynth_port = "I2C_FIFOReadNext", src = "../../verilog/adt7410.v:19" *)
output I2C_FIFOReadNext_o,
(* intersynth_conntype = "Bit", intersynth_port = "I2C_FIFOWrite", src = "../../verilog/adt7410.v:21" *)
output I2C_FIFOWrite_o,
(* intersynth_conntype = "Byte", intersynth_port = "I2C_DataIn", src = "../../verilog/adt7410.v:23" *)
output[7:0] I2C_Data_o,
(* intersynth_conntype = "Byte", intersynth_port = "I2C_DataOut", src = "../../verilog/adt7410.v:25" *)
input[7:0] I2C_Data_i,
(* intersynth_conntype = "Bit", intersynth_port = "I2C_Error", src = "../../verilog/adt7410.v:27" *)
input I2C_Error_i,
(* intersynth_conntype = "Word", intersynth_param = "PeriodCounterPreset_i", src = "../../verilog/adt7410.v:29" *)
input[15:0] PeriodCounterPreset_i,
(* intersynth_conntype = "Word", intersynth_param = "SensorValue_o", src = "../../verilog/adt7410.v:31" *)
output[15:0] SensorValue_o,
(* intersynth_conntype = "Word", intersynth_param = "Threshold_i", src = "../../verilog/adt7410.v:33" *)
input[15:0] Threshold_i,
(* intersynth_conntype = "Word", intersynth_param = "WaitCounterPreset_i", src = "../../verilog/adt7410.v:35" *)
input[15:0] WaitCounterPreset_i
);
(* src = "../../verilog/i2cfsm.v:240" *)
wire [7:0] \$techmap\I2CFSM_1.$0\Byte0_o[7:0] ;
(* src = "../../verilog/i2cfsm.v:240" *)
wire [7:0] \$techmap\I2CFSM_1.$0\Byte1_o[7:0] ;
(* src = "../../verilog/i2cfsm.v:270" *)
wire [15:0] \$techmap\I2CFSM_1.$0\I2C_FSM_Timer[15:0] ;
(* src = "../../verilog/i2cfsm.v:97" *)
wire \$techmap\I2CFSM_1.$2\I2C_FIFOReadNext_o[0:0] ;
(* src = "../../verilog/i2cfsm.v:97" *)
wire \$techmap\I2CFSM_1.$2\I2C_FSM_TimerEnable[0:0] ;
(* src = "../../verilog/i2cfsm.v:97" *)
wire \$techmap\I2CFSM_1.$2\I2C_FSM_TimerPreset[0:0] ;
(* src = "../../verilog/i2cfsm.v:97" *)
wire \$techmap\I2CFSM_1.$4\I2C_FSM_TimerEnable[0:0] ;
wire \$techmap\I2CFSM_1.$auto$opt_reduce.cc:126:opt_mux$2832 ;
wire \$techmap\I2CFSM_1.$auto$opt_reduce.cc:126:opt_mux$2834 ;
wire \$techmap\I2CFSM_1.$procmux$1152_CMP ;
wire \$techmap\I2CFSM_1.$procmux$1153_CMP ;
wire \$techmap\I2CFSM_1.$procmux$1156_CMP ;
wire \$techmap\I2CFSM_1.$procmux$1157_CMP ;
wire \$techmap\I2CFSM_1.$procmux$1158_CMP ;
wire \$techmap\I2CFSM_1.$procmux$1161_CMP ;
wire \$techmap\I2CFSM_1.$procmux$1166_CMP ;
wire \$techmap\I2CFSM_1.$procmux$1167_CMP ;
wire \$techmap\I2CFSM_1.$procmux$1168_CMP ;
wire \$techmap\I2CFSM_1.$procmux$1169_CMP ;
wire \$techmap\I2CFSM_1.$procmux$1172_CMP ;
wire [15:0] \$techmap\I2CFSM_1.$procmux$803_Y ;
(* src = "../../verilog/i2cfsm.v:284" *)
wire [15:0] \$techmap\I2CFSM_1.$sub$../../verilog/i2cfsm.v:284$14_Y ;
(* src = "../../verilog/sensorfsm.v:145" *)
wire [15:0] \$techmap\SensorFSM_1.$0\SensorFSM_Timer[15:0] ;
(* src = "../../verilog/sensorfsm.v:168" *)
wire [15:0] \$techmap\SensorFSM_1.$0\Word0[15:0] ;
(* src = "../../verilog/sensorfsm.v:59" *)
wire \$techmap\SensorFSM_1.$2\MeasureFSM_Start_o[0:0] ;
(* src = "../../verilog/sensorfsm.v:59" *)
wire \$techmap\SensorFSM_1.$2\SensorFSM_StoreNewValue[0:0] ;
(* src = "../../verilog/sensorfsm.v:59" *)
wire \$techmap\SensorFSM_1.$2\SensorFSM_TimerPreset[0:0] ;
(* src = "../../verilog/sensorfsm.v:59" *)
wire \$techmap\SensorFSM_1.$3\SensorFSM_StoreNewValue[0:0] ;
(* src = "../../verilog/sensorfsm.v:59" *)
wire \$techmap\SensorFSM_1.$3\SensorFSM_TimerPreset[0:0] ;
(* src = "../../verilog/sensorfsm.v:59" *)
wire \$techmap\SensorFSM_1.$4\SensorFSM_TimerPreset[0:0] ;
(* src = "../../verilog/sensorfsm.v:59" *)
wire \$techmap\SensorFSM_1.$5\SensorFSM_TimerPreset[0:0] ;
wire \$techmap\SensorFSM_1.$procmux$195_CMP ;
wire \$techmap\SensorFSM_1.$procmux$202_CMP ;
wire \$techmap\SensorFSM_1.$procmux$207_CMP ;
wire \$techmap\SensorFSM_1.$procmux$210_CMP ;
wire [15:0] \$techmap\SensorFSM_1.$procmux$62_Y ;
(* src = "../../verilog/sensorfsm.v:159" *)
wire [15:0] \$techmap\SensorFSM_1.$sub$../../verilog/sensorfsm.v:159$51_Y ;
(* src = "../../verilog/i2cfsm.v:10" *)
wire [7:0] \I2CFSM_1.Byte0_o ;
(* src = "../../verilog/i2cfsm.v:11" *)
wire [7:0] \I2CFSM_1.Byte1_o ;
(* src = "../../verilog/i2cfsm.v:5" *)
wire \I2CFSM_1.Clk_i ;
(* src = "../../verilog/i2cfsm.v:8" *)
wire \I2CFSM_1.Done_o ;
(* src = "../../verilog/i2cfsm.v:9" *)
wire \I2CFSM_1.Error_o ;
(* src = "../../verilog/i2cfsm.v:17" *)
wire \I2CFSM_1.I2C_Busy_i ;
(* src = "../../verilog/i2cfsm.v:22" *)
wire [7:0] \I2CFSM_1.I2C_Data_i ;
(* src = "../../verilog/i2cfsm.v:21" *)
wire [7:0] \I2CFSM_1.I2C_Data_o ;
(* src = "../../verilog/i2cfsm.v:24" *)
wire \I2CFSM_1.I2C_Error_i ;
(* src = "../../verilog/i2cfsm.v:19" *)
wire \I2CFSM_1.I2C_FIFOReadNext_o ;
(* src = "../../verilog/i2cfsm.v:20" *)
wire \I2CFSM_1.I2C_FIFOWrite_o ;
(* src = "../../verilog/i2cfsm.v:268" *)
wire [15:0] \I2CFSM_1.I2C_FSM_Timer ;
(* src = "../../verilog/i2cfsm.v:77" *)
wire \I2CFSM_1.I2C_FSM_TimerEnable ;
(* src = "../../verilog/i2cfsm.v:75" *)
wire \I2CFSM_1.I2C_FSM_TimerOvfl ;
(* src = "../../verilog/i2cfsm.v:76" *)
wire \I2CFSM_1.I2C_FSM_TimerPreset ;
(* src = "../../verilog/i2cfsm.v:79" *)
wire \I2CFSM_1.I2C_FSM_Wr0 ;
(* src = "../../verilog/i2cfsm.v:78" *)
wire \I2CFSM_1.I2C_FSM_Wr1 ;
(* src = "../../verilog/i2cfsm.v:15" *)
wire [7:0] \I2CFSM_1.I2C_ReadCount_o ;
(* src = "../../verilog/i2cfsm.v:14" *)
wire \I2CFSM_1.I2C_ReceiveSend_n_o ;
(* src = "../../verilog/i2cfsm.v:16" *)
wire \I2CFSM_1.I2C_StartProcess_o ;
(* src = "../../verilog/i2cfsm.v:26" *)
wire [15:0] \I2CFSM_1.ParamCounterPreset_i ;
(* src = "../../verilog/i2cfsm.v:4" *)
wire \I2CFSM_1.Reset_n_i ;
(* src = "../../verilog/i2cfsm.v:7" *)
wire \I2CFSM_1.Start_i ;
(* src = "../../verilog/adt7410.v:41" *)
wire [7:0] I2CFSM_Byte0_s;
(* src = "../../verilog/adt7410.v:42" *)
wire [7:0] I2CFSM_Byte1_s;
(* src = "../../verilog/adt7410.v:39" *)
wire I2CFSM_Done_s;
(* src = "../../verilog/adt7410.v:40" *)
wire I2CFSM_Error_s;
(* src = "../../verilog/adt7410.v:38" *)
wire I2CFSM_Start_s;
(* src = "../../verilog/sensorfsm.v:41" *)
wire [15:0] \SensorFSM_1.AbsDiffResult ;
(* src = "../../verilog/sensorfsm.v:7" *)
wire \SensorFSM_1.Clk_i ;
(* src = "../../verilog/sensorfsm.v:10" *)
wire \SensorFSM_1.CpuIntr_o ;
(* src = "../../verilog/sensorfsm.v:183" *)
wire [16:0] \SensorFSM_1.DiffAB ;
(* src = "../../verilog/sensorfsm.v:184" *)
wire [15:0] \SensorFSM_1.DiffBA ;
(* src = "../../verilog/sensorfsm.v:9" *)
wire \SensorFSM_1.Enable_i ;
(* src = "../../verilog/sensorfsm.v:16" *)
wire [7:0] \SensorFSM_1.MeasureFSM_Byte0_i ;
(* src = "../../verilog/sensorfsm.v:17" *)
wire [7:0] \SensorFSM_1.MeasureFSM_Byte1_i ;
(* src = "../../verilog/sensorfsm.v:14" *)
wire \SensorFSM_1.MeasureFSM_Done_i ;
(* src = "../../verilog/sensorfsm.v:15" *)
wire \SensorFSM_1.MeasureFSM_Error_i ;
(* src = "../../verilog/sensorfsm.v:13" *)
wire \SensorFSM_1.MeasureFSM_Start_o ;
(* src = "../../verilog/sensorfsm.v:20" *)
wire [15:0] \SensorFSM_1.ParamCounterPreset_i ;
(* src = "../../verilog/sensorfsm.v:19" *)
wire [15:0] \SensorFSM_1.ParamThreshold_i ;
(* src = "../../verilog/sensorfsm.v:6" *)
wire \SensorFSM_1.Reset_n_i ;
(* src = "../../verilog/sensorfsm.v:34" *)
wire \SensorFSM_1.SensorFSM_DiffTooLarge ;
(* src = "../../verilog/sensorfsm.v:35" *)
wire \SensorFSM_1.SensorFSM_StoreNewValue ;
(* src = "../../verilog/sensorfsm.v:143" *)
wire [15:0] \SensorFSM_1.SensorFSM_Timer ;
(* src = "../../verilog/sensorfsm.v:33" *)
wire \SensorFSM_1.SensorFSM_TimerEnable ;
(* src = "../../verilog/sensorfsm.v:31" *)
wire \SensorFSM_1.SensorFSM_TimerOvfl ;
(* src = "../../verilog/sensorfsm.v:32" *)
wire \SensorFSM_1.SensorFSM_TimerPreset ;
(* src = "../../verilog/sensorfsm.v:39" *)
wire [15:0] \SensorFSM_1.SensorValue ;
(* src = "../../verilog/sensorfsm.v:11" *)
wire [15:0] \SensorFSM_1.SensorValue_o ;
(* src = "../../verilog/sensorfsm.v:40" *)
wire [15:0] \SensorFSM_1.Word0 ;
wire I2CFSM_1_Out13_s;
wire I2CFSM_1_Out14_s;
wire I2CFSM_1_CfgMode_s;
wire I2CFSM_1_CfgClk_s;
wire I2CFSM_1_CfgShift_s;
wire I2CFSM_1_CfgDataIn_s;
wire I2CFSM_1_CfgDataOut_s;
wire SensorFSM_1_Out4_s;
wire SensorFSM_1_Out5_s;
wire SensorFSM_1_Out6_s;
wire SensorFSM_1_Out7_s;
wire SensorFSM_1_Out8_s;
wire SensorFSM_1_Out9_s;
wire SensorFSM_1_CfgMode_s;
wire SensorFSM_1_CfgClk_s;
wire SensorFSM_1_CfgShift_s;
wire SensorFSM_1_CfgDataIn_s;
wire SensorFSM_1_CfgDataOut_s;
\$reduce_or #(
.A_SIGNED(0),
.A_WIDTH(2),
.Y_WIDTH(1)
) \$techmap\I2CFSM_1.$auto$opt_reduce.cc:130:opt_mux$2827 (
.A({ \$techmap\I2CFSM_1.$procmux$1153_CMP , \$techmap\I2CFSM_1.$procmux$1152_CMP }),
.Y(\I2CFSM_1.I2C_ReceiveSend_n_o )
);
\$reduce_or #(
.A_SIGNED(0),
.A_WIDTH(3),
.Y_WIDTH(1)
) \$techmap\I2CFSM_1.$auto$opt_reduce.cc:130:opt_mux$2831 (
.A({ \$techmap\I2CFSM_1.$procmux$1167_CMP , \$techmap\I2CFSM_1.$procmux$1157_CMP , \$techmap\I2CFSM_1.$procmux$1153_CMP }),
.Y(\I2CFSM_1.I2C_StartProcess_o )
);
\$reduce_or #(
.A_SIGNED(0),
.A_WIDTH(2),
.Y_WIDTH(1)
) \$techmap\I2CFSM_1.$auto$opt_reduce.cc:130:opt_mux$2833 (
.A({ \$techmap\I2CFSM_1.$procmux$1172_CMP , \$techmap\I2CFSM_1.$procmux$1161_CMP }),
.Y(\$techmap\I2CFSM_1.$auto$opt_reduce.cc:126:opt_mux$2832 )
);
\$reduce_or #(
.A_SIGNED(0),
.A_WIDTH(3),
.Y_WIDTH(1)
) \$techmap\I2CFSM_1.$auto$opt_reduce.cc:130:opt_mux$2835 (
.A({ \$techmap\I2CFSM_1.$procmux$1169_CMP , \$techmap\I2CFSM_1.$procmux$1168_CMP , \$techmap\I2CFSM_1.$procmux$1158_CMP }),
.Y(\$techmap\I2CFSM_1.$auto$opt_reduce.cc:126:opt_mux$2834 )
);
(* src = "../../verilog/i2cfsm.v:289" *)
\$eq #(
.A_SIGNED(0),
.A_WIDTH(16),
.B_SIGNED(0),
.B_WIDTH(16),
.Y_WIDTH(1)
) \$techmap\I2CFSM_1.$eq$../../verilog/i2cfsm.v:289$15 (
.A(\I2CFSM_1.I2C_FSM_Timer ),
.B(16'b0000000000000000),
.Y(\I2CFSM_1.I2C_FSM_TimerOvfl )
);
I2CFSM I2CFSM_1 (
.Reset_n_i(\I2CFSM_1.Reset_n_i ),
.Clk_i(\I2CFSM_1.Clk_i ),
.In0_i(\I2CFSM_1.I2C_Busy_i ),
.In1_i(\I2CFSM_1.I2C_Error_i ),
.In2_i(\I2CFSM_1.I2C_FSM_TimerOvfl ),
.In3_i(\I2CFSM_1.Start_i ),
.In4_i(1'b0),
.In5_i(1'b0),
.In6_i(1'b0),
.In7_i(1'b0),
.Out0_o(\$techmap\I2CFSM_1.$procmux$1152_CMP ),
.Out1_o(\$techmap\I2CFSM_1.$procmux$1153_CMP ),
.Out2_o(\$techmap\I2CFSM_1.$procmux$1156_CMP ),
.Out3_o(\$techmap\I2CFSM_1.$procmux$1157_CMP ),
.Out4_o(\$techmap\I2CFSM_1.$procmux$1158_CMP ),
.Out5_o(\$techmap\I2CFSM_1.$procmux$1161_CMP ),
.Out6_o(\$techmap\I2CFSM_1.$procmux$1166_CMP ),
.Out7_o(\$techmap\I2CFSM_1.$procmux$1167_CMP ),
.Out8_o(\$techmap\I2CFSM_1.$procmux$1168_CMP ),
.Out9_o(\$techmap\I2CFSM_1.$procmux$1169_CMP ),
.Out10_o(\$techmap\I2CFSM_1.$procmux$1172_CMP ),
.Out11_o(\I2CFSM_1.Done_o ),
.Out12_o(\I2CFSM_1.I2C_FSM_Wr0 ),
.Out13_o(I2CFSM_1_Out13_s),
.Out14_o(I2CFSM_1_Out14_s),
.CfgMode_i(I2CFSM_1_CfgMode_s),
.CfgClk_i(I2CFSM_1_CfgClk_s),
.CfgShift_i(I2CFSM_1_CfgShift_s),
.CfgDataIn_i(I2CFSM_1_CfgDataIn_s),
.CfgDataOut_o(I2CFSM_1_CfgDataOut_s)
);
(* src = "../../verilog/i2cfsm.v:240" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(8'b00000000),
.CLK_POLARITY(1'b1),
.WIDTH(8)
) \$techmap\I2CFSM_1.$procdff$2819 (
.ARST(\I2CFSM_1.Reset_n_i ),
.CLK(\I2CFSM_1.Clk_i ),
.D(\$techmap\I2CFSM_1.$0\Byte0_o[7:0] ),
.Q(\I2CFSM_1.Byte0_o )
);
(* src = "../../verilog/i2cfsm.v:240" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(8'b00000000),
.CLK_POLARITY(1'b1),
.WIDTH(8)
) \$techmap\I2CFSM_1.$procdff$2820 (
.ARST(\I2CFSM_1.Reset_n_i ),
.CLK(\I2CFSM_1.Clk_i ),
.D(\$techmap\I2CFSM_1.$0\Byte1_o[7:0] ),
.Q(\I2CFSM_1.Byte1_o )
);
(* src = "../../verilog/i2cfsm.v:270" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(16'b0000000000000000),
.CLK_POLARITY(1'b1),
.WIDTH(16)
) \$techmap\I2CFSM_1.$procdff$2821 (
.ARST(\I2CFSM_1.Reset_n_i ),
.CLK(\I2CFSM_1.Clk_i ),
.D(\$techmap\I2CFSM_1.$0\I2C_FSM_Timer[15:0] ),
.Q(\I2CFSM_1.I2C_FSM_Timer )
);
\$and #(
.A_SIGNED(0),
.A_WIDTH(1),
.B_SIGNED(0),
.B_WIDTH(1),
.Y_WIDTH(1)
) \$techmap\I2CFSM_1.$procmux$1192 (
.A(\$techmap\I2CFSM_1.$procmux$1166_CMP ),
.B(\I2CFSM_1.I2C_Error_i ),
.Y(\I2CFSM_1.Error_o )
);
\$pmux #(
.S_WIDTH(2),
.WIDTH(1)
) \$techmap\I2CFSM_1.$procmux$1202 (
.A(1'b0),
.B({ \$techmap\I2CFSM_1.$2\I2C_FIFOReadNext_o[0:0] , 1'b1 }),
.S({ \$techmap\I2CFSM_1.$procmux$1152_CMP , \I2CFSM_1.I2C_FSM_Wr0 }),
.Y(\I2CFSM_1.I2C_FIFOReadNext_o )
);
\$pmux #(
.S_WIDTH(2),
.WIDTH(1)
) \$techmap\I2CFSM_1.$procmux$1241 (
.A(1'b0),
.B({ \$techmap\I2CFSM_1.$2\I2C_FSM_TimerEnable[0:0] , \$techmap\I2CFSM_1.$4\I2C_FSM_TimerEnable[0:0] }),
.S({ \$techmap\I2CFSM_1.$procmux$1166_CMP , \$techmap\I2CFSM_1.$procmux$1161_CMP }),
.Y(\I2CFSM_1.I2C_FSM_TimerEnable )
);
\$pmux #(
.S_WIDTH(2),
.WIDTH(1)
) \$techmap\I2CFSM_1.$procmux$1268 (
.A(1'b1),
.B({ \$techmap\I2CFSM_1.$2\I2C_FSM_TimerPreset[0:0] , \I2CFSM_1.I2C_FSM_TimerOvfl }),
.S({ \$techmap\I2CFSM_1.$procmux$1166_CMP , \$techmap\I2CFSM_1.$procmux$1161_CMP }),
.Y(\I2CFSM_1.I2C_FSM_TimerPreset )
);
\$and #(
.A_SIGNED(0),
.A_WIDTH(1),
.B_SIGNED(0),
.B_WIDTH(1),
.Y_WIDTH(1)
) \$techmap\I2CFSM_1.$procmux$1313 (
.A(\$techmap\I2CFSM_1.$procmux$1152_CMP ),
.B(\$techmap\I2CFSM_1.$2\I2C_FIFOReadNext_o[0:0] ),
.Y(\I2CFSM_1.I2C_FSM_Wr1 )
);
\$mux #(
.WIDTH(8)
) \$techmap\I2CFSM_1.$procmux$1340 (
.A(8'b00000000),
.B(8'b00000010),
.S(\I2CFSM_1.I2C_ReceiveSend_n_o ),
.Y(\I2CFSM_1.I2C_ReadCount_o )
);
\$pmux #(
.S_WIDTH(4),
.WIDTH(8)
) \$techmap\I2CFSM_1.$procmux$1425 (
.A(8'b00000000),
.B(52465809),
.S({ \$techmap\I2CFSM_1.$procmux$1169_CMP , \$techmap\I2CFSM_1.$procmux$1168_CMP , \$techmap\I2CFSM_1.$auto$opt_reduce.cc:126:opt_mux$2832 , \$techmap\I2CFSM_1.$procmux$1156_CMP }),
.Y(\I2CFSM_1.I2C_Data_o )
);
\$pmux #(
.S_WIDTH(4),
.WIDTH(1)
) \$techmap\I2CFSM_1.$procmux$1452 (
.A(1'b0),
.B({ \I2CFSM_1.Start_i , \I2CFSM_1.I2C_FSM_TimerOvfl , 1'b1, \$techmap\I2CFSM_1.$2\I2C_FIFOReadNext_o[0:0] }),
.S({ \$techmap\I2CFSM_1.$procmux$1172_CMP , \$techmap\I2CFSM_1.$procmux$1161_CMP , \$techmap\I2CFSM_1.$auto$opt_reduce.cc:126:opt_mux$2834 , \$techmap\I2CFSM_1.$procmux$1156_CMP }),
.Y(\I2CFSM_1.I2C_FIFOWrite_o )
);
\$mux #(
.WIDTH(1)
) \$techmap\I2CFSM_1.$procmux$1598 (
.A(\$techmap\I2CFSM_1.$2\I2C_FIFOReadNext_o[0:0] ),
.B(1'b0),
.S(\I2CFSM_1.I2C_Error_i ),
.Y(\$techmap\I2CFSM_1.$2\I2C_FSM_TimerEnable[0:0] )
);
\$or #(
.A_SIGNED(0),
.A_WIDTH(1),
.B_SIGNED(0),
.B_WIDTH(1),
.Y_WIDTH(1)
) \$techmap\I2CFSM_1.$procmux$1626 (
.A(\I2CFSM_1.I2C_Busy_i ),
.B(\I2CFSM_1.I2C_Error_i ),
.Y(\$techmap\I2CFSM_1.$2\I2C_FSM_TimerPreset[0:0] )
);
\$not #(
.A_SIGNED(0),
.A_WIDTH(1),
.Y_WIDTH(1)
) \$techmap\I2CFSM_1.$procmux$1766 (
.A(\I2CFSM_1.I2C_Busy_i ),
.Y(\$techmap\I2CFSM_1.$2\I2C_FIFOReadNext_o[0:0] )
);
\$not #(
.A_SIGNED(0),
.A_WIDTH(1),
.Y_WIDTH(1)
) \$techmap\I2CFSM_1.$procmux$1876 (
.A(\I2CFSM_1.I2C_FSM_TimerOvfl ),
.Y(\$techmap\I2CFSM_1.$4\I2C_FSM_TimerEnable[0:0] )
);
\$mux #(
.WIDTH(8)
) \$techmap\I2CFSM_1.$procmux$793 (
.A(\I2CFSM_1.Byte0_o ),
.B(\I2CFSM_1.I2C_Data_i ),
.S(\I2CFSM_1.I2C_FSM_Wr0 ),
.Y(\$techmap\I2CFSM_1.$0\Byte0_o[7:0] )
);
\$mux #(
.WIDTH(8)
) \$techmap\I2CFSM_1.$procmux$800 (
.A(\I2CFSM_1.Byte1_o ),
.B(\I2CFSM_1.I2C_Data_i ),
.S(\I2CFSM_1.I2C_FSM_Wr1 ),
.Y(\$techmap\I2CFSM_1.$0\Byte1_o[7:0] )
);
\$mux #(
.WIDTH(16)
) \$techmap\I2CFSM_1.$procmux$803 (
.A(\I2CFSM_1.I2C_FSM_Timer ),
.B(\$techmap\I2CFSM_1.$sub$../../verilog/i2cfsm.v:284$14_Y ),
.S(\I2CFSM_1.I2C_FSM_TimerEnable ),
.Y(\$techmap\I2CFSM_1.$procmux$803_Y )
);
\$mux #(
.WIDTH(16)
) \$techmap\I2CFSM_1.$procmux$806 (
.A(\$techmap\I2CFSM_1.$procmux$803_Y ),
.B(\I2CFSM_1.ParamCounterPreset_i ),
.S(\I2CFSM_1.I2C_FSM_TimerPreset ),
.Y(\$techmap\I2CFSM_1.$0\I2C_FSM_Timer[15:0] )
);
(* src = "../../verilog/i2cfsm.v:284" *)
\$sub #(
.A_SIGNED(0),
.A_WIDTH(16),
.B_SIGNED(0),
.B_WIDTH(1),
.Y_WIDTH(16)
) \$techmap\I2CFSM_1.$sub$../../verilog/i2cfsm.v:284$14 (
.A(\I2CFSM_1.I2C_FSM_Timer ),
.B(1'b1),
.Y(\$techmap\I2CFSM_1.$sub$../../verilog/i2cfsm.v:284$14_Y )
);
(* src = "../../verilog/sensorfsm.v:164" *)
\$eq #(
.A_SIGNED(0),
.A_WIDTH(16),
.B_SIGNED(0),
.B_WIDTH(16),
.Y_WIDTH(1)
) \$techmap\SensorFSM_1.$eq$../../verilog/sensorfsm.v:164$52 (
.A(\SensorFSM_1.SensorFSM_Timer ),
.B(16'b0000000000000000),
.Y(\SensorFSM_1.SensorFSM_TimerOvfl )
);
SensorFSM SensorFSM_1 (
.Reset_n_i(\SensorFSM_1.Reset_n_i ),
.Clk_i(\SensorFSM_1.Clk_i ),
.In0_i(\SensorFSM_1.Enable_i ),
.In1_i(\SensorFSM_1.MeasureFSM_Done_i ),
.In2_i(\SensorFSM_1.MeasureFSM_Error_i ),
.In3_i(\SensorFSM_1.SensorFSM_DiffTooLarge ),
.In4_i(\SensorFSM_1.SensorFSM_TimerOvfl ),
.In5_i(1'b0),
.In6_i(1'b0),
.In7_i(1'b0),
.In8_i(1'b0),
.In9_i(1'b0),
.Out0_o(\$techmap\SensorFSM_1.$procmux$195_CMP ),
.Out1_o(\$techmap\SensorFSM_1.$procmux$202_CMP ),
.Out2_o(\$techmap\SensorFSM_1.$procmux$207_CMP ),
.Out3_o(\$techmap\SensorFSM_1.$procmux$210_CMP ),
.Out4_o(SensorFSM_1_Out4_s),
.Out5_o(SensorFSM_1_Out5_s),
.Out6_o(SensorFSM_1_Out6_s),
.Out7_o(SensorFSM_1_Out7_s),
.Out8_o(SensorFSM_1_Out8_s),
.Out9_o(SensorFSM_1_Out9_s),
.CfgMode_i(SensorFSM_1_CfgMode_s),
.CfgClk_i(SensorFSM_1_CfgClk_s),
.CfgShift_i(SensorFSM_1_CfgShift_s),
.CfgDataIn_i(SensorFSM_1_CfgDataIn_s),
.CfgDataOut_o(SensorFSM_1_CfgDataOut_s)
);
(* src = "../../verilog/sensorfsm.v:189" *)
\$gt #(
.A_SIGNED(0),
.A_WIDTH(16),
.B_SIGNED(0),
.B_WIDTH(16),
.Y_WIDTH(1)
) \$techmap\SensorFSM_1.$gt$../../verilog/sensorfsm.v:189$59 (
.A(\SensorFSM_1.AbsDiffResult ),
.B(\SensorFSM_1.ParamThreshold_i ),
.Y(\SensorFSM_1.SensorFSM_DiffTooLarge )
);
(* src = "../../verilog/sensorfsm.v:145" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(16'b0000000000000000),
.CLK_POLARITY(1'b1),
.WIDTH(16)
) \$techmap\SensorFSM_1.$procdff$2816 (
.ARST(\SensorFSM_1.Reset_n_i ),
.CLK(\SensorFSM_1.Clk_i ),
.D(\$techmap\SensorFSM_1.$0\SensorFSM_Timer[15:0] ),
.Q(\SensorFSM_1.SensorFSM_Timer )
);
(* src = "../../verilog/sensorfsm.v:168" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(16'b0000000000000000),
.CLK_POLARITY(1'b1),
.WIDTH(16)
) \$techmap\SensorFSM_1.$procdff$2817 (
.ARST(\SensorFSM_1.Reset_n_i ),
.CLK(\SensorFSM_1.Clk_i ),
.D(\$techmap\SensorFSM_1.$0\Word0[15:0] ),
.Q(\SensorFSM_1.Word0 )
);
\$pmux #(
.S_WIDTH(2),
.WIDTH(1)
) \$techmap\SensorFSM_1.$procmux$194 (
.A(1'b0),
.B({ \SensorFSM_1.MeasureFSM_Error_i , 1'b1 }),
.S({ \$techmap\SensorFSM_1.$procmux$202_CMP , \$techmap\SensorFSM_1.$procmux$195_CMP }),
.Y(\SensorFSM_1.CpuIntr_o )
);
\$and #(
.A_SIGNED(0),
.A_WIDTH(1),
.B_SIGNED(0),
.B_WIDTH(1),
.Y_WIDTH(1)
) \$techmap\SensorFSM_1.$procmux$227 (
.A(\$techmap\SensorFSM_1.$procmux$207_CMP ),
.B(\$techmap\SensorFSM_1.$2\MeasureFSM_Start_o[0:0] ),
.Y(\SensorFSM_1.MeasureFSM_Start_o )
);
\$and #(
.A_SIGNED(0),
.A_WIDTH(1),
.B_SIGNED(0),
.B_WIDTH(1),
.Y_WIDTH(1)
) \$techmap\SensorFSM_1.$procmux$243 (
.A(\$techmap\SensorFSM_1.$procmux$202_CMP ),
.B(\$techmap\SensorFSM_1.$2\SensorFSM_StoreNewValue[0:0] ),
.Y(\SensorFSM_1.SensorFSM_StoreNewValue )
);
\$pmux #(
.S_WIDTH(3),
.WIDTH(1)
) \$techmap\SensorFSM_1.$procmux$285 (
.A(1'b0),
.B({ \SensorFSM_1.Enable_i , 1'b1, \$techmap\SensorFSM_1.$2\SensorFSM_StoreNewValue[0:0] }),
.S({ \$techmap\SensorFSM_1.$procmux$210_CMP , \$techmap\SensorFSM_1.$procmux$207_CMP , \$techmap\SensorFSM_1.$procmux$202_CMP }),
.Y(\SensorFSM_1.SensorFSM_TimerEnable )
);
\$pmux #(
.S_WIDTH(3),
.WIDTH(1)
) \$techmap\SensorFSM_1.$procmux$306 (
.A(1'b1),
.B({ \$techmap\SensorFSM_1.$2\SensorFSM_TimerPreset[0:0] , 1'b0, \$techmap\SensorFSM_1.$3\SensorFSM_TimerPreset[0:0] }),
.S({ \$techmap\SensorFSM_1.$procmux$210_CMP , \$techmap\SensorFSM_1.$procmux$207_CMP , \$techmap\SensorFSM_1.$procmux$202_CMP }),
.Y(\SensorFSM_1.SensorFSM_TimerPreset )
);
\$not #(
.A_SIGNED(0),
.A_WIDTH(1),
.Y_WIDTH(1)
) \$techmap\SensorFSM_1.$procmux$356 (
.A(\SensorFSM_1.Enable_i ),
.Y(\$techmap\SensorFSM_1.$2\SensorFSM_TimerPreset[0:0] )
);
\$and #(
.A_SIGNED(0),
.A_WIDTH(1),
.B_SIGNED(0),
.B_WIDTH(1),
.Y_WIDTH(1)
) \$techmap\SensorFSM_1.$procmux$397 (
.A(\SensorFSM_1.Enable_i ),
.B(\SensorFSM_1.SensorFSM_TimerOvfl ),
.Y(\$techmap\SensorFSM_1.$2\MeasureFSM_Start_o[0:0] )
);
\$mux #(
.WIDTH(1)
) \$techmap\SensorFSM_1.$procmux$482 (
.A(\$techmap\SensorFSM_1.$3\SensorFSM_StoreNewValue[0:0] ),
.B(1'b0),
.S(\SensorFSM_1.MeasureFSM_Error_i ),
.Y(\$techmap\SensorFSM_1.$2\SensorFSM_StoreNewValue[0:0] )
);
\$or #(
.A_SIGNED(0),
.A_WIDTH(1),
.B_SIGNED(0),
.B_WIDTH(1),
.Y_WIDTH(1)
) \$techmap\SensorFSM_1.$procmux$526 (
.A(\$techmap\SensorFSM_1.$4\SensorFSM_TimerPreset[0:0] ),
.B(\SensorFSM_1.MeasureFSM_Error_i ),
.Y(\$techmap\SensorFSM_1.$3\SensorFSM_TimerPreset[0:0] )
);
\$and #(
.A_SIGNED(0),
.A_WIDTH(1),
.B_SIGNED(0),
.B_WIDTH(1),
.Y_WIDTH(1)
) \$techmap\SensorFSM_1.$procmux$613 (
.A(\SensorFSM_1.MeasureFSM_Done_i ),
.B(\SensorFSM_1.SensorFSM_DiffTooLarge ),
.Y(\$techmap\SensorFSM_1.$3\SensorFSM_StoreNewValue[0:0] )
);
\$mux #(
.WIDTH(16)
) \$techmap\SensorFSM_1.$procmux$62 (
.A(\SensorFSM_1.SensorFSM_Timer ),
.B(\$techmap\SensorFSM_1.$sub$../../verilog/sensorfsm.v:159$51_Y ),
.S(\SensorFSM_1.SensorFSM_TimerEnable ),
.Y(\$techmap\SensorFSM_1.$procmux$62_Y )
);
\$mux #(
.WIDTH(16)
) \$techmap\SensorFSM_1.$procmux$65 (
.A(\$techmap\SensorFSM_1.$procmux$62_Y ),
.B(\SensorFSM_1.ParamCounterPreset_i ),
.S(\SensorFSM_1.SensorFSM_TimerPreset ),
.Y(\$techmap\SensorFSM_1.$0\SensorFSM_Timer[15:0] )
);
\$mux #(
.WIDTH(1)
) \$techmap\SensorFSM_1.$procmux$659 (
.A(1'b1),
.B(\$techmap\SensorFSM_1.$5\SensorFSM_TimerPreset[0:0] ),
.S(\SensorFSM_1.MeasureFSM_Done_i ),
.Y(\$techmap\SensorFSM_1.$4\SensorFSM_TimerPreset[0:0] )
);
\$mux #(
.WIDTH(16)
) \$techmap\SensorFSM_1.$procmux$68 (
.A(\SensorFSM_1.Word0 ),
.B({ \SensorFSM_1.MeasureFSM_Byte1_i , \SensorFSM_1.MeasureFSM_Byte0_i }),
.S(\SensorFSM_1.SensorFSM_StoreNewValue ),
.Y(\$techmap\SensorFSM_1.$0\Word0[15:0] )
);
\$not #(
.A_SIGNED(0),
.A_WIDTH(1),
.Y_WIDTH(1)
) \$techmap\SensorFSM_1.$procmux$705 (
.A(\SensorFSM_1.SensorFSM_DiffTooLarge ),
.Y(\$techmap\SensorFSM_1.$5\SensorFSM_TimerPreset[0:0] )
);
(* src = "../../verilog/sensorfsm.v:159" *)
\$sub #(
.A_SIGNED(0),
.A_WIDTH(16),
.B_SIGNED(0),
.B_WIDTH(1),
.Y_WIDTH(16)
) \$techmap\SensorFSM_1.$sub$../../verilog/sensorfsm.v:159$51 (
.A(\SensorFSM_1.SensorFSM_Timer ),
.B(1'b1),
.Y(\$techmap\SensorFSM_1.$sub$../../verilog/sensorfsm.v:159$51_Y )
);
(* src = "../../verilog/sensorfsm.v:185" *)
\$sub #(
.A_SIGNED(0),
.A_WIDTH(17),
.B_SIGNED(0),
.B_WIDTH(17),
.Y_WIDTH(17)
) \$techmap\SensorFSM_1.$sub$../../verilog/sensorfsm.v:185$56 (
.A({ 1'b0, \SensorFSM_1.MeasureFSM_Byte1_i , \SensorFSM_1.MeasureFSM_Byte0_i }),
.B({ 1'b0, \SensorFSM_1.Word0 }),
.Y(\SensorFSM_1.DiffAB )
);
(* src = "../../verilog/sensorfsm.v:186" *)
\$sub #(
.A_SIGNED(0),
.A_WIDTH(16),
.B_SIGNED(0),
.B_WIDTH(16),
.Y_WIDTH(16)
) \$techmap\SensorFSM_1.$sub$../../verilog/sensorfsm.v:186$57 (
.A(\SensorFSM_1.Word0 ),
.B({ \SensorFSM_1.MeasureFSM_Byte1_i , \SensorFSM_1.MeasureFSM_Byte0_i }),
.Y(\SensorFSM_1.DiffBA )
);
(* src = "../../verilog/sensorfsm.v:187" *)
\$mux #(
.WIDTH(16)
) \$techmap\SensorFSM_1.$ternary$../../verilog/sensorfsm.v:187$58 (
.A(\SensorFSM_1.DiffAB [15:0]),
.B(\SensorFSM_1.DiffBA ),
.S(\SensorFSM_1.DiffAB [16]),
.Y(\SensorFSM_1.AbsDiffResult )
);
assign I2CFSM_Byte0_s = \I2CFSM_1.Byte0_o ;
assign I2CFSM_Byte1_s = \I2CFSM_1.Byte1_o ;
assign \I2CFSM_1.Clk_i = Clk_i;
assign I2CFSM_Done_s = \I2CFSM_1.Done_o ;
assign I2CFSM_Error_s = \I2CFSM_1.Error_o ;
assign \I2CFSM_1.I2C_Busy_i = I2C_Busy_i;
assign \I2CFSM_1.I2C_Data_i = I2C_Data_i;
assign I2C_Data_o = \I2CFSM_1.I2C_Data_o ;
assign \I2CFSM_1.I2C_Error_i = I2C_Error_i;
assign I2C_FIFOReadNext_o = \I2CFSM_1.I2C_FIFOReadNext_o ;
assign I2C_FIFOWrite_o = \I2CFSM_1.I2C_FIFOWrite_o ;
assign I2C_ReadCount_o = \I2CFSM_1.I2C_ReadCount_o ;
assign I2C_ReceiveSend_n_o = \I2CFSM_1.I2C_ReceiveSend_n_o ;
assign I2C_StartProcess_o = \I2CFSM_1.I2C_StartProcess_o ;
assign \I2CFSM_1.ParamCounterPreset_i = WaitCounterPreset_i;
assign \I2CFSM_1.Reset_n_i = Reset_n_i;
assign \I2CFSM_1.Start_i = I2CFSM_Start_s;
assign \SensorFSM_1.Clk_i = Clk_i;
assign CpuIntr_o = \SensorFSM_1.CpuIntr_o ;
assign \SensorFSM_1.Enable_i = Enable_i;
assign \SensorFSM_1.MeasureFSM_Byte0_i = I2CFSM_Byte0_s;
assign \SensorFSM_1.MeasureFSM_Byte1_i = I2CFSM_Byte1_s;
assign \SensorFSM_1.MeasureFSM_Done_i = I2CFSM_Done_s;
assign \SensorFSM_1.MeasureFSM_Error_i = I2CFSM_Error_s;
assign I2CFSM_Start_s = \SensorFSM_1.MeasureFSM_Start_o ;
assign \SensorFSM_1.ParamCounterPreset_i = PeriodCounterPreset_i;
assign \SensorFSM_1.ParamThreshold_i = Threshold_i;
assign \SensorFSM_1.Reset_n_i = Reset_n_i;
assign SensorValue_o = \SensorFSM_1.SensorValue_o ;
assign \SensorFSM_1.SensorValue = { \SensorFSM_1.MeasureFSM_Byte1_i , \SensorFSM_1.MeasureFSM_Byte0_i };
assign \SensorFSM_1.SensorValue_o = \SensorFSM_1.Word0 ;
assign I2CFSM_1_CfgMode_s = 1'b0;
assign I2CFSM_1_CfgClk_s = 1'b0;
assign I2CFSM_1_CfgShift_s = 1'b0;
assign I2CFSM_1_CfgDataIn_s = 1'b0;
assign SensorFSM_1_CfgMode_s = 1'b0;
assign SensorFSM_1_CfgClk_s = 1'b0;
assign SensorFSM_1_CfgShift_s = 1'b0;
assign SensorFSM_1_CfgDataIn_s = 1'b0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21AI_1_V
`define SKY130_FD_SC_HD__O21AI_1_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog wrapper for o21ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o21ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o21ai_1 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o21ai_1 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21AI_1_V
|
//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module sdram_0_input_efifo_module (
// inputs:
clk,
rd,
reset_n,
wr,
wr_data,
// outputs:
almost_empty,
almost_full,
empty,
full,
rd_data
)
;
output almost_empty;
output almost_full;
output empty;
output full;
output [ 40: 0] rd_data;
input clk;
input rd;
input reset_n;
input wr;
input [ 40: 0] wr_data;
wire almost_empty;
wire almost_full;
wire empty;
reg [ 1: 0] entries;
reg [ 40: 0] entry_0;
reg [ 40: 0] entry_1;
wire full;
reg rd_address;
reg [ 40: 0] rd_data;
wire [ 1: 0] rdwr;
reg wr_address;
assign rdwr = {rd, wr};
assign full = entries == 2;
assign almost_full = entries >= 1;
assign empty = entries == 0;
assign almost_empty = entries <= 1;
always @(entry_0 or entry_1 or rd_address)
begin
case (rd_address) // synthesis parallel_case full_case
1'd0: begin
rd_data = entry_0;
end // 1'd0
1'd1: begin
rd_data = entry_1;
end // 1'd1
default: begin
end // default
endcase // rd_address
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
wr_address <= 0;
rd_address <= 0;
entries <= 0;
end
else
case (rdwr) // synthesis parallel_case full_case
2'd1: begin
// Write data
if (!full)
begin
entries <= entries + 1;
wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
end
end // 2'd1
2'd2: begin
// Read data
if (!empty)
begin
entries <= entries - 1;
rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
end
end // 2'd2
2'd3: begin
wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
end // 2'd3
default: begin
end // default
endcase // rdwr
end
always @(posedge clk)
begin
//Write data
if (wr & !full)
case (wr_address) // synthesis parallel_case full_case
1'd0: begin
entry_0 <= wr_data;
end // 1'd0
1'd1: begin
entry_1 <= wr_data;
end // 1'd1
default: begin
end // default
endcase // wr_address
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module sdram_0 (
// inputs:
az_addr,
az_be_n,
az_cs,
az_data,
az_rd_n,
az_wr_n,
clk,
reset_n,
// outputs:
za_data,
za_valid,
za_waitrequest,
zs_addr,
zs_ba,
zs_cas_n,
zs_cke,
zs_cs_n,
zs_dq,
zs_dqm,
zs_ras_n,
zs_we_n
)
;
output [ 15: 0] za_data;
output za_valid;
output za_waitrequest;
output [ 11: 0] zs_addr;
output [ 1: 0] zs_ba;
output zs_cas_n;
output zs_cke;
output zs_cs_n;
inout [ 15: 0] zs_dq;
output [ 1: 0] zs_dqm;
output zs_ras_n;
output zs_we_n;
input [ 21: 0] az_addr;
input [ 1: 0] az_be_n;
input az_cs;
input [ 15: 0] az_data;
input az_rd_n;
input az_wr_n;
input clk;
input reset_n;
wire [ 23: 0] CODE;
reg ack_refresh_request;
reg [ 21: 0] active_addr;
wire [ 1: 0] active_bank;
reg active_cs_n;
reg [ 15: 0] active_data;
reg [ 1: 0] active_dqm;
reg active_rnw;
wire almost_empty;
wire almost_full;
wire bank_match;
wire [ 7: 0] cas_addr;
wire clk_en;
wire [ 3: 0] cmd_all;
wire [ 2: 0] cmd_code;
wire cs_n;
wire csn_decode;
wire csn_match;
wire [ 21: 0] f_addr;
wire [ 1: 0] f_bank;
wire f_cs_n;
wire [ 15: 0] f_data;
wire [ 1: 0] f_dqm;
wire f_empty;
reg f_pop;
wire f_rnw;
wire f_select;
wire [ 40: 0] fifo_read_data;
reg [ 11: 0] i_addr;
reg [ 3: 0] i_cmd;
reg [ 2: 0] i_count;
reg [ 2: 0] i_next;
reg [ 2: 0] i_refs;
reg [ 2: 0] i_state;
reg init_done;
reg [ 11: 0] m_addr /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 1: 0] m_bank /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 3: 0] m_cmd /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 2: 0] m_count;
reg [ 15: 0] m_data /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON ; FAST_OUTPUT_ENABLE_REGISTER=ON" */;
reg [ 1: 0] m_dqm /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 8: 0] m_next;
reg [ 8: 0] m_state;
reg oe /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_ENABLE_REGISTER=ON" */;
wire pending;
wire rd_strobe;
reg [ 2: 0] rd_valid;
reg [ 12: 0] refresh_counter;
reg refresh_request;
wire rnw_match;
wire row_match;
wire [ 23: 0] txt_code;
reg za_cannotrefresh;
reg [ 15: 0] za_data /* synthesis ALTERA_ATTRIBUTE = "FAST_INPUT_REGISTER=ON" */;
reg za_valid;
wire za_waitrequest;
wire [ 11: 0] zs_addr;
wire [ 1: 0] zs_ba;
wire zs_cas_n;
wire zs_cke;
wire zs_cs_n;
wire [ 15: 0] zs_dq;
wire [ 1: 0] zs_dqm;
wire zs_ras_n;
wire zs_we_n;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign {zs_cs_n, zs_ras_n, zs_cas_n, zs_we_n} = m_cmd;
assign zs_addr = m_addr;
assign zs_cke = clk_en;
assign zs_dq = oe?m_data:{16{1'bz}};
assign zs_dqm = m_dqm;
assign zs_ba = m_bank;
assign f_select = f_pop & pending;
assign f_cs_n = 1'b0;
assign cs_n = f_select ? f_cs_n : active_cs_n;
assign csn_decode = cs_n;
assign {f_rnw, f_addr, f_dqm, f_data} = fifo_read_data;
sdram_0_input_efifo_module the_sdram_0_input_efifo_module
(
.almost_empty (almost_empty),
.almost_full (almost_full),
.clk (clk),
.empty (f_empty),
.full (za_waitrequest),
.rd (f_select),
.rd_data (fifo_read_data),
.reset_n (reset_n),
.wr ((~az_wr_n | ~az_rd_n) & !za_waitrequest),
.wr_data ({az_wr_n, az_addr, az_wr_n ? 2'b0 : az_be_n, az_data})
);
assign f_bank = {f_addr[21],f_addr[8]};
// Refresh/init counter.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
refresh_counter <= 5000;
else if (refresh_counter == 0)
refresh_counter <= 781;
else
refresh_counter <= refresh_counter - 1'b1;
end
// Refresh request signal.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
refresh_request <= 0;
else if (1)
refresh_request <= ((refresh_counter == 0) | refresh_request) & ~ack_refresh_request & init_done;
end
// Generate an Interrupt if two ref_reqs occur before one ack_refresh_request
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_cannotrefresh <= 0;
else if (1)
za_cannotrefresh <= (refresh_counter == 0) & refresh_request;
end
// Initialization-done flag.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
init_done <= 0;
else if (1)
init_done <= init_done | (i_state == 3'b101);
end
// **** Init FSM ****
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
i_state <= 3'b000;
i_next <= 3'b000;
i_cmd <= 4'b1111;
i_addr <= {12{1'b1}};
i_count <= {3{1'b0}};
end
else
begin
i_addr <= {12{1'b1}};
case (i_state) // synthesis parallel_case full_case
3'b000: begin
i_cmd <= 4'b1111;
i_refs <= 3'b0;
//Wait for refresh count-down after reset
if (refresh_counter == 0)
i_state <= 3'b001;
end // 3'b000
3'b001: begin
i_state <= 3'b011;
i_cmd <= {{1{1'b0}},3'h2};
i_count <= 0;
i_next <= 3'b010;
end // 3'b001
3'b010: begin
i_cmd <= {{1{1'b0}},3'h1};
i_refs <= i_refs + 1'b1;
i_state <= 3'b011;
i_count <= 3;
// Count up init_refresh_commands
if (i_refs == 3'h1)
i_next <= 3'b111;
else
i_next <= 3'b010;
end // 3'b010
3'b011: begin
i_cmd <= {{1{1'b0}},3'h7};
//WAIT til safe to Proceed...
if (i_count > 1)
i_count <= i_count - 1'b1;
else
i_state <= i_next;
end // 3'b011
3'b101: begin
i_state <= 3'b101;
end // 3'b101
3'b111: begin
i_state <= 3'b011;
i_cmd <= {{1{1'b0}},3'h0};
i_addr <= {{2{1'b0}},1'b0,2'b00,3'h3,4'h0};
i_count <= 4;
i_next <= 3'b101;
end // 3'b111
default: begin
i_state <= 3'b000;
end // default
endcase // i_state
end
end
assign active_bank = {active_addr[21],active_addr[8]};
assign csn_match = active_cs_n == f_cs_n;
assign rnw_match = active_rnw == f_rnw;
assign bank_match = active_bank == f_bank;
assign row_match = {active_addr[20 : 9]} == {f_addr[20 : 9]};
assign pending = csn_match && rnw_match && bank_match && row_match && !f_empty;
assign cas_addr = f_select ? { {4{1'b0}},f_addr[7 : 0] } : { {4{1'b0}},active_addr[7 : 0] };
// **** Main FSM ****
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
m_state <= 9'b000000001;
m_next <= 9'b000000001;
m_cmd <= 4'b1111;
m_bank <= 2'b00;
m_addr <= 12'b000000000000;
m_data <= 16'b0000000000000000;
m_dqm <= 2'b00;
m_count <= 3'b000;
ack_refresh_request <= 1'b0;
f_pop <= 1'b0;
oe <= 1'b0;
end
else
begin
f_pop <= 1'b0;
oe <= 1'b0;
case (m_state) // synthesis parallel_case full_case
9'b000000001: begin
//Wait for init-fsm to be done...
if (init_done)
begin
//Hold bus if another cycle ended to arf.
if (refresh_request)
m_cmd <= {{1{1'b0}},3'h7};
else
m_cmd <= 4'b1111;
ack_refresh_request <= 1'b0;
//Wait for a read/write request.
if (refresh_request)
begin
m_state <= 9'b001000000;
m_next <= 9'b010000000;
m_count <= 0;
active_cs_n <= 1'b1;
end
else if (!f_empty)
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
m_state <= 9'b000000010;
end
end
else
begin
m_addr <= i_addr;
m_state <= 9'b000000001;
m_next <= 9'b000000001;
m_cmd <= i_cmd;
end
end // 9'b000000001
9'b000000010: begin
m_state <= 9'b000000100;
m_cmd <= {csn_decode,3'h3};
m_bank <= active_bank;
m_addr <= active_addr[20 : 9];
m_data <= active_data;
m_dqm <= active_dqm;
m_count <= 1;
m_next <= active_rnw ? 9'b000001000 : 9'b000010000;
end // 9'b000000010
9'b000000100: begin
// precharge all if arf, else precharge csn_decode
if (m_next == 9'b010000000)
m_cmd <= {{1{1'b0}},3'h7};
else
m_cmd <= {csn_decode,3'h7};
//Count down til safe to Proceed...
if (m_count > 1)
m_count <= m_count - 1'b1;
else
m_state <= m_next;
end // 9'b000000100
9'b000001000: begin
m_cmd <= {csn_decode,3'h5};
m_bank <= f_select ? f_bank : active_bank;
m_dqm <= f_select ? f_dqm : active_dqm;
m_addr <= cas_addr;
//Do we have a transaction pending?
if (pending)
begin
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 2;
end
else
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
end
else
begin
//correctly end RD spin cycle if fifo mt
if (~pending & f_pop)
m_cmd <= {csn_decode,3'h7};
m_state <= 9'b100000000;
end
end // 9'b000001000
9'b000010000: begin
m_cmd <= {csn_decode,3'h4};
oe <= 1'b1;
m_data <= f_select ? f_data : active_data;
m_dqm <= f_select ? f_dqm : active_dqm;
m_bank <= f_select ? f_bank : active_bank;
m_addr <= cas_addr;
//Do we have a transaction pending?
if (pending)
begin
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 1;
end
else
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
end
else
begin
//correctly end WR spin cycle if fifo empty
if (~pending & f_pop)
begin
m_cmd <= {csn_decode,3'h7};
oe <= 1'b0;
end
m_state <= 9'b100000000;
end
end // 9'b000010000
9'b000100000: begin
m_cmd <= {csn_decode,3'h7};
//Count down til safe to Proceed...
if (m_count > 1)
m_count <= m_count - 1'b1;
else
begin
m_state <= 9'b001000000;
m_count <= 0;
end
end // 9'b000100000
9'b001000000: begin
m_state <= 9'b000000100;
m_addr <= {12{1'b1}};
// precharge all if arf, else precharge csn_decode
if (refresh_request)
m_cmd <= {{1{1'b0}},3'h2};
else
m_cmd <= {csn_decode,3'h2};
end // 9'b001000000
9'b010000000: begin
ack_refresh_request <= 1'b1;
m_state <= 9'b000000100;
m_cmd <= {{1{1'b0}},3'h1};
m_count <= 3;
m_next <= 9'b000000001;
end // 9'b010000000
9'b100000000: begin
m_cmd <= {csn_decode,3'h7};
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 1;
end
else //wait for fifo to have contents
if (!f_empty)
//Are we 'pending' yet?
if (csn_match && rnw_match && bank_match && row_match)
begin
m_state <= f_rnw ? 9'b000001000 : 9'b000010000;
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
else
begin
m_state <= 9'b000100000;
m_next <= 9'b000000001;
m_count <= 1;
end
end // 9'b100000000
// synthesis translate_off
default: begin
m_state <= m_state;
m_cmd <= 4'b1111;
f_pop <= 1'b0;
oe <= 1'b0;
end // default
// synthesis translate_on
endcase // m_state
end
end
assign rd_strobe = m_cmd[2 : 0] == 3'h5;
//Track RD Req's based on cas_latency w/shift reg
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
rd_valid <= {3{1'b0}};
else
rd_valid <= (rd_valid << 1) | { {2{1'b0}}, rd_strobe };
end
// Register dq data.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_data <= 0;
else
za_data <= zs_dq;
end
// Delay za_valid to match registered data.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_valid <= 0;
else if (1)
za_valid <= rd_valid[2];
end
assign cmd_code = m_cmd[2 : 0];
assign cmd_all = m_cmd;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign txt_code = (cmd_code == 3'h0)? 24'h4c4d52 :
(cmd_code == 3'h1)? 24'h415246 :
(cmd_code == 3'h2)? 24'h505245 :
(cmd_code == 3'h3)? 24'h414354 :
(cmd_code == 3'h4)? 24'h205752 :
(cmd_code == 3'h5)? 24'h205244 :
(cmd_code == 3'h6)? 24'h425354 :
(cmd_code == 3'h7)? 24'h4e4f50 :
24'h424144;
assign CODE = &(cmd_all|4'h7) ? 24'h494e48 : txt_code;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun Apr 09 08:38:15 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_zed_vga_0_0 -prefix
// system_zed_vga_0_0_ system_zed_vga_0_0_stub.v
// Design : system_zed_vga_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "zed_vga,Vivado 2016.4" *)
module system_zed_vga_0_0(rgb565, vga_r, vga_g, vga_b)
/* synthesis syn_black_box black_box_pad_pin="rgb565[15:0],vga_r[3:0],vga_g[3:0],vga_b[3:0]" */;
input [15:0]rgb565;
output [3:0]vga_r;
output [3:0]vga_g;
output [3:0]vga_b;
endmodule
|
//==================================================================================================
// Filename : FPU_ADD_Substract_PIPELINED.v
// Created On : 2016-09-27 20:11:48
// Last Modified : 2016-11-19 21:00:16
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description :
//
//
//==================================================================================================
`timescale 1ns/1ps
//==================================================================================================
// Filename : FPU_ADD_Substract_PIPELINED.v
// Created On : 2016-09-21 14:31:41
// Last Modified : 2016-09-27 08:58:31
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description : This is the TOP for the pipelined FP Addition and substraction.
//
//
//==================================================================================================
// `include "Tenth_Phase_v2.v"
// `include "Priority_Codec_32.v"
// `include "Priority_Codec_64.v"
// `include "sgn_result.v"
// `include "Shift_left_logical.v"
// `include "xor_tri.v"
// `include "RegisterAdd.v"
// `include "Multiplexer_AC.v"
// `include "FSM_input_enable.v"
// `include "MultiplexTxT.v"
// `include "shift_mux.v"
// `include "FORMATTER.v"
// `include "Rotate_Mux_Array.v"
module FPU_PIPELINED_FPADDSUB
/*#(parameter W = 32, parameter EW = 8, parameter SW = 23,
parameter SWR=26, parameter EWR = 5) //Single Precision */
#(parameter W = 64, parameter EW = 11, parameter SW = 52,
parameter SWR = 55, parameter EWR = 6) //-- Double Precision */
(
//FSM Signals
input wire clk,
input wire rst,
input wire beg_OP,
//input wire ack_OP,
//Oper_Start_in signals
input wire [W-1:0] Data_X,
input wire [W-1:0] Data_Y,
input wire add_subt,
//Round signals signals
//input wire [1:0] r_mode,
//OUTPUT SIGNALS
output wire busy,
output wire overflow_flag,
output wire underflow_flag,
output wire zero_flag,
output wire ready,
output wire [W-1:0] final_result_ieee
);
///////////////////WE LOAD THE INPUT VALUES AND OTHER SIGNALS ////
// ONTO THE FIRST STAGE//////
wire enable_Pipeline_input;
wire FSM_enable_input_internal;
wire [6:0] Shift_reg_FLAGS_7;
wire real_input_enable;
wire enable_shift_reg;
FSM_INPUT_ENABLE inst_FSM_INPUT_ENABLE (
.clk (clk),
.rst (rst),
.init_OPERATION (beg_OP),
.enable_input_internal (FSM_enable_input_internal),
.enable_Pipeline_input (enable_Pipeline_input),
.enable_shift_reg (enable_shift_reg)
);
ShiftRegister #(.W(7)) inst_ShiftRegister (
.clk(clk),
.rst(rst),
.load (enable_shift_reg),
.in_bit (FSM_enable_input_internal),
.Q(Shift_reg_FLAGS_7));
//////////////////////////////----------------INIT------------------///////////////////////////////
wire ZERO_FLAG_INIT;
wire [W-1:0] intDX_EWSW, intDY_EWSW; //BUFFER OPERAND 1, OPERAND 2
wire intAS; //ADD SUB INPUT OPERATION
wire INPUT_ACTIVE;
wire gtXY, eqXY;
/// FLAGS PIPE STAGE: INIT
wire OP_FLAG_INIT, SIGN_FLAG_INIT;
/// DATA PIPE STAGE : INIT
wire [W-2:0] DMP_INIT_EWSW, DmP_INIT_EWSW;
//////////////////////////////----------------EXP------------------///////////////////////////////
// FLAGS
wire SIGN_FLAG_EXP, OP_FLAG_EXP, ZERO_FLAG_EXP, EXP_ACTIVE;
//Whole operand declaration
wire [W-2:0] DMP_EXP_EWSW, DmP_EXP_EWSW;
/// EXPONENT DECLARATION
wire [EW-1:0] DMP_exp_EXP_EW, DmP_exp_EXP_EW;
/// MANTISSA OR SIGNIFICAND DECLARATION
wire [SW-1:0] DMP_mant_EXP_SW, DmP_mant_EXP_SW;
//SHIFT AMOUNT DECLARATION
wire [EW-1:0] Shift_amount_EXP_EW; //Exponent operation result
//////////////////////////////----------------SHT1------------------///////////////////////////////
//FLAGS
wire [EWR-1:0]b_shifter_one_EWR;
wire SIGN_FLAG_SHT1, OP_FLAG_SHT1, ZERO_FLAG_SHT1, SHT1_ACTIVE;
//OPERAND SIGNALS
wire [W-2:0] DMP_SHT1_EWSW;
wire [SW-1:0] DmP_mant_SHT1_SW;
wire [EWR-1:0] Shift_amount_SHT1_EWR;
/////////////////------SIGNALS FOR THE FIRST PART OF THE SHIFTER-------//////////-///////////////////
wire [EWR-1:0] shft_value_mux_o_EWR;
wire left_right_SHT1;
wire bit_shift_SHT1;
wire [SWR-1:0] sftr_idat_SHT1_SWR; //SHIFTER INPUT DATA
wire [SWR-1:0] sftr_odat_SHT1_SWR; //SHIFTER OUTPUT DATA
///////////BARREL SHIFTER INPUT VALUE MUX SIGNALS
// TEMPORARY WIRES
wire [EWR-1:0] mux_sel_norm_EWR; //OUTPUT SIGNAL FOR MUX SHIFT VALUE
wire [SWR-1:0] Data_array_SWR[EWR+1:0]; //TEMPORARY FOR THE DIFFERENT STAGES OF THE SHIFTER
//////////////////////////////----------------SHT2------------------///////////////////////////////
//FLAGS
wire SIGN_FLAG_SHT2, OP_FLAG_SHT2, ZERO_FLAG_SHT2, SHT2_ACTIVE;
/////////////////------SIGNALS FOR THE SECOND PART OF THE SHIFTER-------//////////-///////////////////
wire [W-2:0]DMP_SHT2_EWSW;
wire [EWR-1:0] shift_value_SHT2_EWR;
wire left_right_SHT2;
wire bit_shift_SHT2;
wire [SWR-1:0] sftr_idat_SHT2_SWR; //SHIFTER INPUT DATA
wire [SWR-1:0] sftr_odat_SHT2_SWR; //SHIFTER OUTPUT DATA
wire ADD_OVRFLW_NRM2, NRM2_ACTIVE;
wire [EW-1:0]Exp_oper_1_EW;
/////////////////------SIGNALS FOR THE LAST EXPONENT OPERATION-------/////////-///////////////////
reg [EW:0] exp_rslt_NRM2_EW1;
wire [EW-1:0] ADDSUB_exp_operand_EW;
wire [EW-1:0]DMP_exp_NRM2_EW;
wire SIGN_FLAG_SHT1SHT2, ZERO_FLAG_SHT1SHT2;
//////////////////////////////----------------SGF------------------///////////////////////////////
//FLAGS
wire SIGN_FLAG_SFG, OP_FLAG_SFG, ZERO_FLAG_SFG, SFG_ACTIVE;
wire ADD_OVRFLW_SGF;
wire [SWR-1:0] DmP_mant_SFG_SWR;
wire [SWR-1:0] DMP_mant_SFG_SWR;
wire [EW-1:0] DMP_exp_SFG;
reg Carry_out_SGF;
reg [SWR-1:0] Raw_mant_SGF;
wire [W-2:0] DMP_SFG;
//////////////////////////////----------------NRM------------------///////////////////////////////
//Flags
wire ADD_OVRFLW_NRM, SIGN_FLAG_NRM, ZERO_FLAG_NRM, NRM_ACTIVE;
wire [EW-1:0]DMP_exp_NRM_EW;
wire [SWR-1:0] Add_Subt_LZD_SWR;
wire [SWR-1:0] Raw_mant_NRM_SWR;
wire [EW-1:0] LZD_output_NRM2_EW;
wire [EWR-1:0] LZD_raw_out_NRM2_EWR;
wire [EWR-1:0] LZD_raw_out_EWR;
wire [EW-EWR-1:0] LZD_ZFiller;
//////////////////////////////----------------FRMT------------------///////////////////////////////
wire OVRFLW_FLAG_FRMT, UNDRFLW_FLAG_FRMT;
wire [W-1:0] formatted_number_W;
/////////////////////////////////////FIRST STAGE "INIT" ///////////////////////////////
///////////////////////////////////// PIPELINE REGISTER = INIT//////////////////////////////////////
//////////////////////////////----------------------------------///////////////////////////////
RegisterAdd #(.W(W)) INPUT_STAGE_OPERANDX (
.clk(clk),
.rst(rst),
.load(enable_Pipeline_input),
.D(Data_X),
.Q(intDX_EWSW));
RegisterAdd #(.W(W)) INPUT_STAGE_OPERANDY (
.clk(clk),
.rst(rst),
.load(enable_Pipeline_input),
.D(Data_Y),
.Q(intDY_EWSW));
RegisterAdd #(.W(1)) INPUT_STAGE_FLAGS (
.clk(clk),
.rst(rst),
.load(enable_Pipeline_input),
.D(add_subt),
.Q(intAS));
// RegisterAdd #(.W(2*W+1+1)) INPUT_STAGE (
// .clk(clk),
// .rst(rst),
// .load(enable_Pipeline_input),
// .D({add_subt , Data_X, Data_Y, enable_Pipeline_input}),
// .Q({intAS , intDX_EWSW , intDY_EWSW , INPUT_ACTIVE})
// );
//////////////////////////////----------------------------------///////////////////////////////
//////////////////////////////----------------------------------///////////////////////////////
//Compares between magnitude for DATA_X and DATA_Y and select whos bigger and if there's a equality
Comparator #(.W(W-1)) Magnitude_Comparator (
.Data_X_i(intDX_EWSW[W-2:0]),
.Data_Y_i(intDY_EWSW[W-2:0]),
.gtXY_o(gtXY),
.eqXY_o(eqXY)
);
//Classifies in the registers the bigger value (M) and the smaller value (m)
MultiplexTxT #(.W(W-1)) MuxXY (
.select(gtXY),
.D0_i(intDX_EWSW[W-2:0]),
.D1_i(intDY_EWSW[W-2:0]),
.S0_o(DMP_INIT_EWSW),
.S1_o(DmP_INIT_EWSW)
);
//Operation between the DATA_X & Y's sign bit and the operation bit to find the real operation for ADDER/SUBTRACT
xor_tri #(.W(W)) Op_verification (
.A_i(intDX_EWSW[W-1]), //Signo de ese operando
.B_i(intDY_EWSW[W-1]), //Signo de ese operando
.C_i(intAS), //Operacion ingresada por modulo externo
.Z_o(OP_FLAG_INIT)
);
//Calculate the sign bit for the final result
sgn_result result_sign_bit (
.Add_Subt_i(intAS),
.sgn_X_i(intDX_EWSW[W-1]),
.sgn_Y_i(intDY_EWSW[W-1]),
.gtXY_i(gtXY),
.eqXY_i(eqXY),
.sgn_result_o(SIGN_FLAG_INIT)
);
//zero flag if theres a subtraction and the variables are equal
assign ZERO_FLAG_INIT = OP_FLAG_INIT & eqXY;
//////////////////////////////----------------------------------///////////////////////////////
////////////////////////////////////////SECOND STAGE "EXP" ///////////////////////////////
///////////////////////////////////// PIPELINE REGISTER = EXP//////////////////////////////////////
//////////////////////////////----------------------------------///////////////////////////////
RegisterAdd #(.W(W-1)) EXP_STAGE_DMP (
.clk(clk),
.rst(rst),
.load(INPUT_ACTIVE),
.D(DMP_INIT_EWSW),
.Q(DMP_EXP_EWSW));
//El sintetizador puede eliminar algunos registros de acá debido a
//la no utilización de estos. Para este caso, se reducirá el tamaño
//de el registro de menor tamaño
//Estos warnings pueden ser ignorados.
RegisterAdd #(.W(W-1)) EXP_STAGE_DmP (
.clk(clk),
.rst(rst),
.load(INPUT_ACTIVE),
.D(DmP_INIT_EWSW),
.Q(DmP_EXP_EWSW));
RegisterAdd #(.W(3)) EXP_STAGE_FLAGS (
.clk(clk),
.rst(rst),
.load(INPUT_ACTIVE),
.D({SIGN_FLAG_INIT, OP_FLAG_INIT, ZERO_FLAG_INIT}),
.Q({SIGN_FLAG_EXP , OP_FLAG_EXP , ZERO_FLAG_EXP}));
// RegisterAdd #(.W( W - 1 + W - 1 + 3 )) EXP_STAGE (
// .clk(clk),
// .rst(rst),
// .load(INPUT_ACTIVE),
// .D({DMP_EXP_EWSW, DmP_INIT_EWSW, SIGN_FLAG_INIT, OP_FLAG_INIT, ZERO_FLAG_INIT, INPUT_ACTIVE}),
// .Q({DMP_EXP_EWSW , DmP_EXP_EWSW , SIGN_FLAG_EXP , OP_FLAG_EXP , ZERO_FLAG_EXP , EXP_ACTIVE })
// );
//////////////////////////////----------------------------------///////////////////////////////
//////////////////////////////----------------------------------///////////////////////////////
//Aca pueden salir problemas por el largo del exponente.
//THE FOLLOWING IS JUST FOR SIMULATION PURPOSES
assign DMP_exp_EXP_EW = DMP_EXP_EWSW[W-2:W-EW-1]; //We assign the exponent bits for the comming operation
assign DmP_exp_EXP_EW = DmP_EXP_EWSW[W-2:W-EW-1]; //We assign the exponent bits for the comming operation
assign DMP_mant_EXP_SW = DMP_EXP_EWSW[SW-1:0];
////////////WE SUBTRACT THE DIFFERENCE BETWEEN EXPONENTS (hence, the EXP name) /////////////
assign Shift_amount_EXP_EW = DMP_EXP_EWSW[W-2:SW] - DmP_EXP_EWSW[W-2:SW];
//assign DMP_mant_EXP_SW = DMP_EXP_EWSW[SW-1:0];
assign DmP_mant_EXP_SW = DmP_EXP_EWSW[SW-1:0];
//////////////////////////////----------------------------------///////////////////////////////
/////////////////////////////////////////THIRD STAGE "SFT1" ////////////////////////////
/////////////////////////////////// PIPELINE REGISTER = SFT1 /////////////////////////////
//////////////////////////////----------------------------------///////////////////////////////
// RegisterAdd #(.W(W-1+SW+EWR+4)) SHT1_STAGE (
// .clk(clk),
// .rst(rst),
// .load(EXP_ACTIVE),
// .D({DMP_EXP_EWSW , DmP_mant_EXP_SW , Shift_amount_EXP_EW , SIGN_FLAG_EXP , OP_FLAG_EXP , ZERO_FLAG_EXP , EXP_ACTIVE}),
// .Q({DMP_SHT1_EWSW, DmP_mant_SHT1_SW, Shift_amount_SHT1_EWR, SIGN_FLAG_SHT1, OP_FLAG_SHT1, ZERO_FLAG_SHT1, SHT1_ACTIVE})
// );
RegisterAdd #(.W(W-1)) SHT1_STAGE_DMP (
.clk(clk),
.rst(rst),
.load(EXP_ACTIVE),
.D(DMP_EXP_EWSW),
.Q(DMP_SHT1_EWSW));
RegisterAdd #(.W(SW)) SHT1_STAGE_DmP_mant (
.clk(clk),
.rst(rst),
.load(EXP_ACTIVE),
.D(DmP_mant_EXP_SW),
.Q(DmP_mant_SHT1_SW));
RegisterAdd #(.W(EWR)) SHT1_STAGE_sft_amount (
.clk(clk),
.rst(rst),
.load(EXP_ACTIVE),
.D(Shift_amount_EXP_EW[EWR-1:0]),
.Q(Shift_amount_SHT1_EWR));
RegisterAdd #(.W(3)) SHT1_STAGE_FLAGS (
.clk(clk),
.rst(rst),
.load(EXP_ACTIVE),
.D({SIGN_FLAG_EXP , OP_FLAG_EXP , ZERO_FLAG_EXP}),
.Q({SIGN_FLAG_SHT1, OP_FLAG_SHT1, ZERO_FLAG_SHT1}));
////////////////////////----------------------TEMPS---------------///////////////////////////////
//////////////////////////////----------------------------------///////////////////////////////
assign b_shifter_one_EWR = {{(EWR-1){1'b0}},1'b1};
assign LZD_ZFiller ={(EW-EWR){1'b0}};
assign Exp_oper_1_EW = {{(EW-1){1'b0}},1'b1};
//assign mux_out = (sel) ? din_1 : din_0;
//Input variables for the shifter, depending upon the stage.
assign mux_sel_norm_EWR = (ADD_OVRFLW_NRM) ? b_shifter_one_EWR : LZD_raw_out_EWR;
assign shft_value_mux_o_EWR = (NRM_ACTIVE) ? mux_sel_norm_EWR : Shift_amount_SHT1_EWR;
//assign left_right_SHT1 = (NRM_ACTIVE) ? (~ADD_OVRFLW_NRM) : 1'b0;
assign left_right_SHT1 = (NRM_ACTIVE)&(~ADD_OVRFLW_NRM);
assign bit_shift_SHT1 = (NRM_ACTIVE)&(ADD_OVRFLW_NRM);
Multiplexer_AC #(.W(SWR)) b_shftr_idat_mux_SHT1 (
.ctrl(NRM_ACTIVE ),
.D0 ({1'b1,DmP_mant_SHT1_SW,2'b00}),
.D1 (Raw_mant_NRM_SWR ),
.S (sftr_idat_SHT1_SWR )
);
////////////////////////////////////////////////////
genvar k; //Level//
////////////////////////////////////////////////////
Rotate_Mux_Array #(.SWR(SWR)) first_rotate(
.Data_i (sftr_idat_SHT1_SWR),
.select_i(left_right_SHT1),
.Data_o (Data_array_SWR [0][SWR-1:0])
);
generate for (k=0; k < 2; k=k+1) begin : shift_mux_array1
shift_mux_array #(.SWR(SWR), .LEVEL(k)) shift_mux_array(
.Data_i (Data_array_SWR[k]),
.select_i (shft_value_mux_o_EWR[k]),
.bit_shift_i(bit_shift_SHT1),
.Data_o (Data_array_SWR[k+1])
);
end
endgenerate
assign sftr_odat_SHT1_SWR = Data_array_SWR[2];
assign Data_array_SWR[3] = sftr_idat_SHT2_SWR;
//////////////////////////////----------------------------------///////////////////////////////
/////////////////////////////////////////FOURTH STAGE "SFT2" ////////////////////////////
/////////////////////////////////// PIPELINE REGISTER = SFT2 /////////////////////////////
//////////////////////////////----------------------------------///////////////////////////////
RegisterAdd #(.W(W-1)) SHT2_STAGE_DMP (
.clk(clk),
.rst(rst),
.load(SHT1_ACTIVE),
.D(DMP_SHT1_EWSW),
.Q(DMP_SHT2_EWSW));
RegisterAdd #(.W(SWR)) SHT2_SHIFT_DATA (
.clk(clk),
.rst(rst),
.load((SHT1_ACTIVE|NRM_ACTIVE)),
.D(sftr_odat_SHT1_SWR),
.Q(sftr_idat_SHT2_SWR));
//LOS BITS 4, 3 y 2 DE ESTE REGISTRO PUEDEN SER ELIMINADOS
//GRACIAS A QUE SE UTILIZARON EN LA ETAPA ANTERIOR DE CORRIMIENTO.
RegisterAdd #(.W(EWR)) SHT2_STAGE_SHFTVARS1 (
.clk(clk),
.rst(rst),
.load(SHT1_ACTIVE|NRM_ACTIVE),
.D({shft_value_mux_o_EWR}),
.Q({shift_value_SHT2_EWR}));
RegisterAdd #(.W(2)) SHT2_STAGE_SHFTVARS2 (
.clk(clk),
.rst(rst),
.load(SHT1_ACTIVE|NRM_ACTIVE),
.D({left_right_SHT1,bit_shift_SHT1}),
.Q({left_right_SHT2, bit_shift_SHT2}));
RegisterAdd #(.W(3)) SHT2_STAGE_FLAGS (
.clk(clk),
.rst(rst),
.load(SHT1_ACTIVE),
.D({SIGN_FLAG_SHT1, OP_FLAG_SHT1, ZERO_FLAG_SHT1}),
.Q({SIGN_FLAG_SHT2, OP_FLAG_SHT2, ZERO_FLAG_SHT2}));
/////////////////DE ACA SALE DIRECTO A LA ETAPA DE FORMATO//////////////
RegisterAdd #(.W(EWR+EW)) SFT2FRMT_STAGE_VARS(
.clk(clk),
.rst(rst),
.load(NRM_ACTIVE),
.D({LZD_raw_out_EWR , DMP_exp_NRM_EW }),
.Q({LZD_raw_out_NRM2_EWR, DMP_exp_NRM2_EW})
);
RegisterAdd #(.W(3)) SFT2FRMT_STAGE_FLAGS (
.clk(clk),
.rst(rst),
.load(NRM_ACTIVE),
.D({ADD_OVRFLW_NRM , SIGN_FLAG_NRM , ZERO_FLAG_NRM }),
.Q({ADD_OVRFLW_NRM2, SIGN_FLAG_SHT1SHT2, ZERO_FLAG_SHT1SHT2}));
//////////////////////////////----------------------------------///////////////////////////////
//////////////////////////////----------------------------------///////////////////////////////
generate for (k=2; k < EWR; k=k+1) begin : shift_mux_array2
shift_mux_array #(.SWR(SWR), .LEVEL(k)) shift_mux_array(
.Data_i(Data_array_SWR[k+1]),
.select_i(shift_value_SHT2_EWR[k]),
.bit_shift_i(bit_shift_SHT2),
.Data_o(Data_array_SWR[k+2])
);
end
endgenerate
Rotate_Mux_Array #(.SWR(SWR)) last_rotate(
.Data_i(Data_array_SWR[EWR+1]),
.select_i(left_right_SHT2),
.Data_o(sftr_odat_SHT2_SWR)
);
assign LZD_output_NRM2_EW = {LZD_ZFiller, LZD_raw_out_NRM2_EWR};
////////////////////////INPUT MUX FOR ADD/SUB/////////////////////////
assign ADDSUB_exp_operand_EW = (ADD_OVRFLW_NRM2) ? Exp_oper_1_EW : LZD_output_NRM2_EW;
////////////////////////INPUT MUX FOR ADD/SUB/////////////////////////
//////////////////////////ADDER/SUBSTRACTOR///////////////////////
// always @* begin : ADD_SUB_NRM
// case (ADD_OVRFLW_NRM2)
// 1'b0 : begin
// {Carry_out_SFT2, exp_rslt_NRM2_EW1} = DMP_exp_NRM2_EW + ADDSUB_exp_operand_EW;
// end
// 1'b1 : begin
// {Carry_out_SFT2, exp_rslt_NRM2_EW1} = DMP_exp_NRM2_EW - ADDSUB_exp_operand_EW;
// end
// default: begin
// {Carry_out_SFT2, exp_rslt_NRM2_EW1} = DMP_exp_NRM2_EW + ADDSUB_exp_operand_EW;
// end
// endcase
always @* begin
if (ADD_OVRFLW_NRM2) begin
exp_rslt_NRM2_EW1 = DMP_exp_NRM2_EW + ADDSUB_exp_operand_EW;
end
else begin
exp_rslt_NRM2_EW1 = DMP_exp_NRM2_EW - ADDSUB_exp_operand_EW;
end
end
//////////////////////////ADDER/SUBSTRACTOR///////////////////////
FORMATTER #(.EW(EW+1)) array_comparators(
.exp(exp_rslt_NRM2_EW1),
.overflow (OVRFLW_FLAG_FRMT),
.underflow(UNDRFLW_FLAG_FRMT));
//////////////////////////////----------------------------------///////////////////////////////
/////////////////////////////////////////FIFTH STAGE "SGF" ////////////////////////////
/////////////////////////////////// PIPELINE REGISTER = SGF /////////////////////////////
//////////////////////////////----------------------------------///////////////////////////////
RegisterAdd #(.W(W-1)) SGF_STAGE_DMP (
.clk(clk),
.rst(rst),
.load((SHT2_ACTIVE&~NRM2_ACTIVE)),
.D(DMP_SHT2_EWSW),
.Q(DMP_SFG));
RegisterAdd #(.W(SWR)) SGF_STAGE_DmP_mant (
.clk(clk),
.rst(rst),
.load(SHT2_ACTIVE&~NRM2_ACTIVE),
.D(sftr_odat_SHT2_SWR),
.Q(DmP_mant_SFG_SWR));
RegisterAdd #(.W(3)) SGF_STAGE_FLAGS (
.clk(clk),
.rst(rst),
.load(SHT2_ACTIVE&~NRM2_ACTIVE),
.D({SIGN_FLAG_SHT2,OP_FLAG_SHT2, ZERO_FLAG_SHT2}),
.Q({SIGN_FLAG_SFG , OP_FLAG_SFG, ZERO_FLAG_SFG }));
// RegisterAdd #(.W(W+SWR+4)) SGF_STAGE(
// .clk(clk),
// .rst(rst),
// .load(SHT2_ACTIVE&~NRM2_ACTIVE),//Esto significa que si esta en NRM2, no active SGF
// .D({DMP_SHT2_EWSW, sftr_odat_SHT2_SWR, SIGN_FLAG_SHT2,OP_FLAG_SHT2, ZERO_FLAG_SHT2, SHT2_ACTIVE}),
// .Q({DMP_SFG , DmP_mant_SFG_SWR , SIGN_FLAG_SFG , OP_FLAG_SFG, ZERO_FLAG_SFG , SFG_ACTIVE})
// );
// RegisterAdd #(.W( )) NORM_2_SGF_STAGE(
// .clk(clk),+
// .rst(rst),
// .load(NRM2SFT2_ACTIVE),
// .D({, Overflow_flag_SHT2, Underflow_flag_SHT2, NRM2SFT2_ACTIVE}),
// .Q({, OVRFLW_FLAG_FRMT, UNDRFLW_FLAG_FRMT, SFT2FRMT_ACTIVE })
// );
//////////////////////////////----------------------------------///////////////////////////////
//////////////////////////////----------------------------------///////////////////////////////
assign DMP_mant_SFG_SWR = {1'b1,DMP_SFG[SW-1:0],2'b00};
assign DMP_exp_SFG = DMP_SFG[W-2:SW];
wire Approx_carrout;
`ifdef ACAIN16Q4
wire [SWR-1:0] DmP_mant_SFG_SWR_signed;
wire [16-1:0] Lower_Raw_mant_SGF;
assign DmP_mant_SFG_SWR_signed = (OP_FLAG_SFG) ? ~DmP_mant_SFG_SWR : DmP_mant_SFG_SWR;
ACA_I_N16_Q4 ApproxAdd (.in1(DMP_mant_SFG_SWR[15:0]), .in2(DmP_mant_SFG_SWR_signed[15:0]), .res({Approx_carrout,Lower_Raw_mant_SGF}));
always @* begin : ADD_SUB_SGF
{Carry_out_SGF, Raw_mant_SGF} = {(DMP_mant_SFG_SWR[SWR-1:16] + DmP_mant_SFG_SWR_signed[SWR-1:16] + Approx_carrout),Lower_Raw_mant_SGF};
end
`elsif ETAIIN16Q4
wire [SWR-1:0] DmP_mant_SFG_SWR_signed;
wire [16-1:0] Lower_Raw_mant_SGF;
assign DmP_mant_SFG_SWR_signed = (OP_FLAG_SFG) ? ~DmP_mant_SFG_SWR : DmP_mant_SFG_SWR;
ETAII_N16_Q4 ApproxAdd (.in1(DMP_mant_SFG_SWR[15:0]), .in2(DmP_mant_SFG_SWR_signed[15:0]), .res({Approx_carrout,Lower_Raw_mant_SGF}));
always @* begin : ADD_SUB_SGF
{Carry_out_SGF, Raw_mant_SGF} = {(DMP_mant_SFG_SWR[SWR-1:16] + DmP_mant_SFG_SWR_signed[SWR-1:16] + Approx_carrout),Lower_Raw_mant_SGF};
end
`elsif ETAIIN16Q8
wire [SWR-1:0] DmP_mant_SFG_SWR_signed;
wire [16-1:0] Lower_Raw_mant_SGF;
assign DmP_mant_SFG_SWR_signed = (OP_FLAG_SFG) ? ~DmP_mant_SFG_SWR : DmP_mant_SFG_SWR;
ETAII_N16_Q8 ApproxAdd (.in1(DMP_mant_SFG_SWR[15:0]), .in2(DmP_mant_SFG_SWR_signed[15:0]), .res({Approx_carrout,Lower_Raw_mant_SGF}));
always @* begin : ADD_SUB_SGF
{Carry_out_SGF, Raw_mant_SGF} = {(DMP_mant_SFG_SWR[SWR-1:16] + DmP_mant_SFG_SWR_signed[SWR-1:16] + Approx_carrout),Lower_Raw_mant_SGF};
end
`elsif ACAIIN16Q4
wire [SWR-1:0] DmP_mant_SFG_SWR_signed;
wire [16-1:0] Lower_Raw_mant_SGF;
assign DmP_mant_SFG_SWR_signed = (OP_FLAG_SFG) ? ~DmP_mant_SFG_SWR : DmP_mant_SFG_SWR;
ACA_II_N16_Q4 ApproxAdd (.in1(DMP_mant_SFG_SWR[15:0]), .in2(DmP_mant_SFG_SWR_signed[15:0]), .res({Approx_carrout,Lower_Raw_mant_SGF}));
always @* begin : ADD_SUB_SGF
{Carry_out_SGF, Raw_mant_SGF} = {(DMP_mant_SFG_SWR[SWR-1:16] + DmP_mant_SFG_SWR_signed[SWR-1:16] + Approx_carrout),Lower_Raw_mant_SGF};
end
`elsif ACAIIN16Q8
wire [SWR-1:0] DmP_mant_SFG_SWR_signed;
wire [16-1:0] Lower_Raw_mant_SGF;
assign DmP_mant_SFG_SWR_signed = (OP_FLAG_SFG) ? ~DmP_mant_SFG_SWR : DmP_mant_SFG_SWR;
ACA_II_N16_Q8 ApproxAdd (.in1(DMP_mant_SFG_SWR[15:0]), .in2(DmP_mant_SFG_SWR_signed[15:0]), .res({Approx_carrout,Lower_Raw_mant_SGF}));
always @* begin : ADD_SUB_SGF
{Carry_out_SGF, Raw_mant_SGF} = {(DMP_mant_SFG_SWR[SWR-1:16] + DmP_mant_SFG_SWR_signed[SWR-1:16] + Approx_carrout),Lower_Raw_mant_SGF};
end
`elsif GDAN16M4P4
wire [SWR-1:0] DmP_mant_SFG_SWR_signed;
wire [16-1:0] Lower_Raw_mant_SGF;
assign DmP_mant_SFG_SWR_signed = (OP_FLAG_SFG) ? ~DmP_mant_SFG_SWR : DmP_mant_SFG_SWR;
GDA_St_N16_M4_P4 ApproxAdd (.in1(DMP_mant_SFG_SWR[15:0]), .in2(DmP_mant_SFG_SWR_signed[15:0]), .res({Approx_carrout,Lower_Raw_mant_SGF}));
always @* begin : ADD_SUB_SGF
{Carry_out_SGF, Raw_mant_SGF} = {(DMP_mant_SFG_SWR[SWR-1:16] + DmP_mant_SFG_SWR_signed[SWR-1:16] + Approx_carrout),Lower_Raw_mant_SGF};
end
`elsif GDAN16M4P8
wire [SWR-1:0] DmP_mant_SFG_SWR_signed;
wire [16-1:0] Lower_Raw_mant_SGF;
assign DmP_mant_SFG_SWR_signed = (OP_FLAG_SFG) ? ~DmP_mant_SFG_SWR : DmP_mant_SFG_SWR;
GDA_St_N16_M4_P8 ApproxAdd (.in1(DMP_mant_SFG_SWR[15:0]), .in2(DmP_mant_SFG_SWR_signed[15:0]), .res({Approx_carrout,Lower_Raw_mant_SGF}));
always @* begin : ADD_SUB_SGF
{Carry_out_SGF, Raw_mant_SGF} = {(DMP_mant_SFG_SWR[SWR-1:16] + DmP_mant_SFG_SWR_signed[SWR-1:16] + Approx_carrout),Lower_Raw_mant_SGF};
end
`elsif GeArN16R2P4
wire [SWR-1:0] DmP_mant_SFG_SWR_signed;
wire [16-1:0] Lower_Raw_mant_SGF;
assign DmP_mant_SFG_SWR_signed = (OP_FLAG_SFG) ? ~DmP_mant_SFG_SWR : DmP_mant_SFG_SWR;
GeAr_N16_R2_P4 ApproxAdd (.in1(DMP_mant_SFG_SWR[15:0]), .in2(DmP_mant_SFG_SWR_signed[15:0]), .res({Approx_carrout,Lower_Raw_mant_SGF}));
always @* begin : ADD_SUB_SGF
{Carry_out_SGF, Raw_mant_SGF} = {(DMP_mant_SFG_SWR[SWR-1:16] + DmP_mant_SFG_SWR_signed[SWR-1:16] + Approx_carrout),Lower_Raw_mant_SGF};
end
`elsif GeArN16R4P4
wire [SWR-1:0] DmP_mant_SFG_SWR_signed;
wire [16-1:0] Lower_Raw_mant_SGF;
assign DmP_mant_SFG_SWR_signed = (OP_FLAG_SFG) ? ~DmP_mant_SFG_SWR : DmP_mant_SFG_SWR;
GeAr_N16_R4_P4 ApproxAdd (.in1(DMP_mant_SFG_SWR[15:0]), .in2(DmP_mant_SFG_SWR_signed[15:0]), .res({Approx_carrout,Lower_Raw_mant_SGF}));
always @* begin : ADD_SUB_SGF
{Carry_out_SGF, Raw_mant_SGF} = {(DMP_mant_SFG_SWR[SWR-1:16] + DmP_mant_SFG_SWR_signed[SWR-1:16] + Approx_carrout),Lower_Raw_mant_SGF};
end
`elsif GeArN16R4P8
wire [SWR-1:0] DmP_mant_SFG_SWR_signed;
wire [16-1:0] Lower_Raw_mant_SGF;
assign DmP_mant_SFG_SWR_signed = (OP_FLAG_SFG) ? ~DmP_mant_SFG_SWR : DmP_mant_SFG_SWR;
GeAr_N16_R4_P8 ApproxAdd (.in1(DMP_mant_SFG_SWR[15:0]), .in2(DmP_mant_SFG_SWR_signed[15:0]), .res({Approx_carrout,Lower_Raw_mant_SGF}));
always @* begin : ADD_SUB_SGF
{Carry_out_SGF, Raw_mant_SGF} = {(DMP_mant_SFG_SWR[SWR-1:16] + DmP_mant_SFG_SWR_signed[SWR-1:16] + Approx_carrout),Lower_Raw_mant_SGF};
end
`elsif LOA
wire [SWR-1:0] DmP_mant_SFG_SWR_signed;
wire [16-1:0] Lower_Raw_mant_SGF;
assign DmP_mant_SFG_SWR_signed = (OP_FLAG_SFG) ? ~DmP_mant_SFG_SWR : DmP_mant_SFG_SWR;
LOA #(.LPL(11), .W(16)) ApproxAdd (.in1(DMP_mant_SFG_SWR[15:0]), .in2(DmP_mant_SFG_SWR_signed[15:0]), .res({Approx_carrout,Lower_Raw_mant_SGF}));
always @* begin : ADD_SUB_SGF
{Carry_out_SGF, Raw_mant_SGF} = {(DMP_mant_SFG_SWR[SWR-1:16] + DmP_mant_SFG_SWR_signed[SWR-1:16] + Approx_carrout),Lower_Raw_mant_SGF};
end
`elsif GeArN16R6P4
wire [SWR-1:0] DmP_mant_SFG_SWR_signed;
wire [16-1:0] Lower_Raw_mant_SGF;
assign DmP_mant_SFG_SWR_signed = (OP_FLAG_SFG) ? ~DmP_mant_SFG_SWR : DmP_mant_SFG_SWR;
GeAr_N16_R6_P4 ApproxAdd (.in1(DMP_mant_SFG_SWR[15:0]), .in2(DmP_mant_SFG_SWR_signed[15:0]), .res({Approx_carrout,Lower_Raw_mant_SGF}));
always @* begin : ADD_SUB_SGF
{Carry_out_SGF, Raw_mant_SGF} = {(DMP_mant_SFG_SWR[SWR-1:16] + DmP_mant_SFG_SWR_signed[SWR-1:16] + Approx_carrout),Lower_Raw_mant_SGF};
end
`else
always @* begin : ADD_SUB_SGF
if (OP_FLAG_SFG) begin
{Carry_out_SGF, Raw_mant_SGF} = DMP_mant_SFG_SWR - DmP_mant_SFG_SWR;
end else begin
{Carry_out_SGF, Raw_mant_SGF} = DMP_mant_SFG_SWR + DmP_mant_SFG_SWR;
end
end
`endif
assign ADD_OVRFLW_SGF = Carry_out_SGF&(~OP_FLAG_SFG);
//////////////////////////////----------------------------------///////////////////////////////
/////////////////////////////////////////SIXTH STAGE "NRM" ////////////////////////////
/////////////////////////////////// PIPELINE REGISTER = NRM /////////////////////////////
//////////////////////////////----------------------------------///////////////////////////////
// RegisterAdd #(.W( )) NRM_STAGE(
// .clk(clk),
// .rst(rst),
// .load(SFG_ACTIVE),
// .D({Raw_mant_SGF, DMP_exp_SFG, ADD_OVRFLW_SGF, SIGN_FLAG_SFG, ZERO_FLAG_SFG, SFG_ACTIVE}),
// .Q({Raw_mant_NRM_SWR, DMP_exp_NRM_EW, ADD_OVRFLW_NRM, SIGN_FLAG_NRM, ZERO_FLAG_NRM, NRM_ACTIVE})
// );
RegisterAdd #(.W(SWR)) NRM_STAGE_Raw_mant (
.clk(clk),
.rst(rst),
.load(SFG_ACTIVE),
.D(Raw_mant_SGF),
.Q(Raw_mant_NRM_SWR));
RegisterAdd #(.W(EW)) NRM_STAGE_DMP_exp (
.clk(clk),
.rst(rst),
.load(SFG_ACTIVE),
.D(DMP_exp_SFG),
.Q(DMP_exp_NRM_EW));
RegisterAdd #(.W(3)) NRM_STAGE_FLAGS (
.clk(clk),
.rst(rst),
.load(SFG_ACTIVE),
.D({ADD_OVRFLW_SGF, SIGN_FLAG_SFG, ZERO_FLAG_SFG}),
.Q({ADD_OVRFLW_NRM, SIGN_FLAG_NRM, ZERO_FLAG_NRM}));
//////////////////////////////----------------------------------///////////////////////////////
//////////////////////////////----------------------------------///////////////////////////////
//assign mux_out = (sel) ? din_1 : din_0;
assign Add_Subt_LZD_SWR = ~Raw_mant_NRM_SWR;
/////////////////////////LZD BEGIN////////////////////////////
generate
case (SWR)
26:begin : LZD_SINGLE
Priority_Codec_32 Codec_32(
.Data_Dec_i(Add_Subt_LZD_SWR),
.Data_Bin_o(LZD_raw_out_EWR)
);
end
55:begin : LZD_DOUBLE
Priority_Codec_64 Codec_64(
.Data_Dec_i(Add_Subt_LZD_SWR),
.Data_Bin_o(LZD_raw_out_EWR)
);
end
endcase
endgenerate
//////////////////////////////----------------------------------///////////////////////////////
/////////////////////////////////////////SEVENTH STAGE "FRMT" ////////////////////////////
/////////////////////////////////// PIPELINE REGISTER = FRMT /////////////////////////////
//////////////////////////////----------------------------------///////////////////////////////
// NO REGISTER FOR THIS STAGE, BECAUSE WE RECYCLE THE BARREL SHIFTER
//////////////////////////////----------------------------------///////////////////////////////
//////////////////////////////----------------------------------///////////////////////////////
FRMT_STAGE #(.W(W),.EW(EW),.SW(SW)) inst_FRMT_STAGE (
.overflow_flag (OVRFLW_FLAG_FRMT ),
.underflow_flag (UNDRFLW_FLAG_FRMT),
.sign_i (SIGN_FLAG_SHT1SHT2),
.exp_ieee_i (exp_rslt_NRM2_EW1[EW-1:0]),
.sgf_ieee_i (sftr_odat_SHT2_SWR[SWR-2:2]),
.formatted_number (formatted_number_W)
);
//////////////////////////////-------------------------------------///////////////////////////////
/////////////////////////////////////////EIGHT STAGE "DATAO" ////////////////////////////
/////////////////////////////////// PIPELINE REGISTER = DATAO /////////////////////////////
//////////////////////////////-------------------------------------///////////////////////////////
assign {INPUT_ACTIVE,
EXP_ACTIVE,
SHT1_ACTIVE,
SHT2_ACTIVE,
SFG_ACTIVE,
NRM_ACTIVE,
NRM2_ACTIVE} = Shift_reg_FLAGS_7;
assign busy = SHT1_ACTIVE;
RegisterAdd #(.W(W)) FRMT_STAGE_DATAOUT (
.clk(clk),
.rst(rst),
.load(NRM2_ACTIVE),
.D(formatted_number_W),
.Q(final_result_ieee)
);
RegisterAdd #(.W(3)) FRMT_STAGE_FLAGS (
.clk(clk),
.rst(rst),
.load(NRM2_ACTIVE),
.D({OVRFLW_FLAG_FRMT,UNDRFLW_FLAG_FRMT, ZERO_FLAG_SHT1SHT2}),
.Q({overflow_flag , underflow_flag , zero_flag })
);
FFD_NoCE #(.W(1)) Ready_reg (
.clk(clk),
.rst(rst),
.D(NRM2_ACTIVE),
.Q(ready));
//////////////////////////////----------------------------------///////////////////////////////
//////////////////////////////----------------------------------///////////////////////////////
endmodule
|
// $Id: router_wrap.v 5188 2012-08-30 00:31:31Z dub $
/*
Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// wrapper around router component (configures router parameters based on
// selected network topology, etc.)
//==============================================================================
module router_wrap
(clk, reset, router_address, channel_in_ip, flow_ctrl_out_ip, channel_out_op,
flow_ctrl_in_op, error, count_down, DoS_detected, permanent_blocked);
`include "c_functions.v"
`include "c_constants.v"
`include "rtr_constants.v"
`include "vcr_constants.v"
`include "parameters.v"
// total number of packet classes
localparam num_packet_classes = num_message_classes * num_resource_classes;
// number of VCs
localparam num_vcs = num_packet_classes * num_vcs_per_class;
// width required to select individual VC
localparam vc_idx_width = clogb(num_vcs);
// total number of routers
localparam num_routers
= (num_nodes + num_nodes_per_router - 1) / num_nodes_per_router;
// number of routers in each dimension
localparam num_routers_per_dim = croot(num_routers, num_dimensions);
// width required to select individual router in a dimension
localparam dim_addr_width = clogb(num_routers_per_dim);
// width required to select individual router in entire network
localparam router_addr_width = num_dimensions * dim_addr_width;
// connectivity within each dimension
localparam connectivity
= (topology == `TOPOLOGY_MESH) ?
`CONNECTIVITY_LINE :
(topology == `TOPOLOGY_TORUS) ?
`CONNECTIVITY_RING :
(topology == `TOPOLOGY_FBFLY) ?
`CONNECTIVITY_FULL :
-1;
// number of adjacent routers in each dimension
localparam num_neighbors_per_dim
= ((connectivity == `CONNECTIVITY_LINE) ||
(connectivity == `CONNECTIVITY_RING)) ?
2 :
(connectivity == `CONNECTIVITY_FULL) ?
(num_routers_per_dim - 1) :
-1;
// number of input and output ports on router
localparam num_ports
= num_dimensions * num_neighbors_per_dim + num_nodes_per_router;
// width of flow control signals
localparam flow_ctrl_width
= (flow_ctrl_type == `FLOW_CTRL_TYPE_CREDIT) ? (1 + vc_idx_width) :
-1;
// width of link management signals
localparam link_ctrl_width = enable_link_pm ? 1 : 0;
// width of flit control signals
localparam flit_ctrl_width
= (packet_format == `PACKET_FORMAT_HEAD_TAIL) ?
(1 + vc_idx_width + 1 + 1) :
(packet_format == `PACKET_FORMAT_TAIL_ONLY) ?
(1 + vc_idx_width + 1) :
(packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ?
(1 + vc_idx_width + 1) :
-1;
// width of channel
localparam channel_width
= link_ctrl_width + flit_ctrl_width + flit_data_width;
//DoS Attack Detection
wire [0:channel_width-1] local_port;
wire valid_packet;
assign local_port = channel_in_ip[(num_ports-1)*channel_width:num_ports*channel_width-1];
assign valid_packet = local_port[0];
reg [9:0] packet_count;
reg [9:0] epoch;
output reg [10:0] count_down;
output reg DoS_detected;
output reg permanent_blocked;
always @(posedge clk, posedge reset) begin
if (reset)
epoch <= 0;
else begin
if (epoch == 1000)
epoch <= 0;
else begin
epoch <= epoch + 1;
//$display("%d",epoch);
end
end
end
always @(posedge clk, posedge reset) begin
if (reset)
packet_count <= 0;
else begin
if (epoch == 1000)
packet_count <= 0;
else if (valid_packet)
packet_count <= packet_count + 1;
end
end
always @(posedge clk, posedge reset) begin
if (reset)
DoS_detected <= 0;
else begin
if (epoch == 1000 && packet_count >= 700) begin
$display("At time:%t, Router Address: %b, DoS attack detected!!!", $time, router_address);
DoS_detected <= 1;
end
else if (count_down == 0 && epoch == 1000 && packet_count < 700 && DoS_detected) begin
$display("At time: %t, Router Address: %b, DoS cleared", $time, router_address);
DoS_detected <= 0;
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
count_down <= 2002;
permanent_blocked <= 0;
end
else begin
if (DoS_detected && count_down != 0)
count_down <= count_down - 1;
else if (count_down == 0 && epoch == 1000 && packet_count >= 700 && DoS_detected) begin
permanent_blocked <= 1;
$display("Router Address: %b, Permanent Blocked!!!", router_address);
end
else if (count_down == 0 && epoch == 1000 && packet_count < 700 && DoS_detected)
count_down <= 2002;
end
end
//PRIV MODE
reg [3:0] counter;
wire increment, decrement;
assign increment = channel_in_ip[0];
assign decrement = channel_in_ip[1];
always @(posedge clk) begin
if (reset)
counter <= 0;
else begin
if (increment && !decrement)
counter <= counter + 1;
else if (!increment && decrement && counter > 0)
counter <= counter - 1;
end
end
input clk;
input reset;
// current router's address
input [0:router_addr_width-1] router_address;
// incoming channels
input [0:num_ports*channel_width-1] channel_in_ip;
// outgoing flow control signals
output [0:num_ports*flow_ctrl_width-1] flow_ctrl_out_ip;
wire [0:num_ports*flow_ctrl_width-1] flow_ctrl_out_ip;
// outgoing channels
output [0:num_ports*channel_width-1] channel_out_op;
wire [0:num_ports*channel_width-1] channel_out_op;
// incoming flow control signals
input [0:num_ports*flow_ctrl_width-1] flow_ctrl_in_op;
// internal error condition detected
output error;
wire error;
generate
case(router_type)
`ROUTER_TYPE_WORMHOLE:
begin
whr_top
#(.buffer_size(buffer_size),
.num_routers_per_dim(num_routers_per_dim),
.num_dimensions(num_dimensions),
.num_nodes_per_router(num_nodes_per_router),
.connectivity(connectivity),
.packet_format(packet_format),
.flow_ctrl_type(flow_ctrl_type),
.flow_ctrl_bypass(flow_ctrl_bypass),
.max_payload_length(max_payload_length),
.min_payload_length(min_payload_length),
.enable_link_pm(enable_link_pm),
.flit_data_width(flit_data_width),
.error_capture_mode(error_capture_mode),
.restrict_turns(restrict_turns),
.routing_type(routing_type),
.dim_order(dim_order),
.input_stage_can_hold(input_stage_can_hold),
.fb_regfile_type(fb_regfile_type),
.fb_fast_peek(fb_fast_peek),
.explicit_pipeline_register(explicit_pipeline_register),
.gate_buffer_write(gate_buffer_write),
.precomp_ip_sel(precomp_ip_sel),
.arbiter_type(sw_alloc_arbiter_type),
.crossbar_type(crossbar_type),
.reset_type(reset_type))
whr
(.clk(clk),
.reset(reset),
.router_address(router_address),
.channel_in_ip(channel_in_ip),
.flow_ctrl_out_ip(flow_ctrl_out_ip),
.channel_out_op(channel_out_op),
.flow_ctrl_in_op(flow_ctrl_in_op),
.error(error));
end
`ROUTER_TYPE_VC:
begin
vcr_top
#(.buffer_size(buffer_size),
.num_message_classes(num_message_classes),
.num_resource_classes(num_resource_classes),
.num_vcs_per_class(num_vcs_per_class),
.num_routers_per_dim(num_routers_per_dim),
.num_dimensions(num_dimensions),
.num_nodes_per_router(num_nodes_per_router),
.connectivity(connectivity),
.packet_format(packet_format),
.flow_ctrl_type(flow_ctrl_type),
.flow_ctrl_bypass(flow_ctrl_bypass),
.max_payload_length(max_payload_length),
.min_payload_length(min_payload_length),
.enable_link_pm(enable_link_pm),
.flit_data_width(flit_data_width),
.error_capture_mode(error_capture_mode),
.restrict_turns(restrict_turns),
.routing_type(routing_type),
.dim_order(dim_order),
.fb_regfile_type(fb_regfile_type),
.fb_mgmt_type(fb_mgmt_type),
.fb_fast_peek(fb_fast_peek),
.disable_static_reservations(disable_static_reservations),
.explicit_pipeline_register(explicit_pipeline_register),
.gate_buffer_write(gate_buffer_write),
.elig_mask(elig_mask),
.vc_alloc_type(vc_alloc_type),
.vc_alloc_arbiter_type(vc_alloc_arbiter_type),
.sw_alloc_type(sw_alloc_type),
.sw_alloc_arbiter_type(sw_alloc_arbiter_type),
.sw_alloc_spec_type(sw_alloc_spec_type),
.crossbar_type(crossbar_type),
.reset_type(reset_type))
vcr
(.clk(clk),
.reset(reset),
.router_address(router_address),
.channel_in_ip(channel_in_ip),
.flow_ctrl_out_ip(flow_ctrl_out_ip),
.channel_out_op(channel_out_op),
.flow_ctrl_in_op(flow_ctrl_in_op),
.error(error));
end
`ROUTER_TYPE_COMBINED:
begin
rtr_top
#(.buffer_size(buffer_size),
.num_message_classes(num_message_classes),
.num_resource_classes(num_resource_classes),
.num_vcs_per_class(num_vcs_per_class),
.num_routers_per_dim(num_routers_per_dim),
.num_dimensions(num_dimensions),
.num_nodes_per_router(num_nodes_per_router),
.connectivity(connectivity),
.packet_format(packet_format),
.flow_ctrl_type(flow_ctrl_type),
.flow_ctrl_bypass(flow_ctrl_bypass),
.max_payload_length(max_payload_length),
.min_payload_length(min_payload_length),
.enable_link_pm(enable_link_pm),
.flit_data_width(flit_data_width),
.error_capture_mode(error_capture_mode),
.restrict_turns(restrict_turns),
.predecode_lar_info(predecode_lar_info),
.routing_type(routing_type),
.dim_order(dim_order),
.fb_regfile_type(fb_regfile_type),
.fb_mgmt_type(fb_mgmt_type),
.fb_fast_peek(fb_fast_peek),
.disable_static_reservations(disable_static_reservations),
.explicit_pipeline_register(explicit_pipeline_register),
.gate_buffer_write(gate_buffer_write),
.dual_path_alloc(dual_path_alloc),
.dual_path_allow_conflicts(dual_path_allow_conflicts),
.dual_path_mask_on_ready(dual_path_mask_on_ready),
.precomp_ivc_sel(precomp_ivc_sel),
.precomp_ip_sel(precomp_ip_sel),
.elig_mask(elig_mask),
.sw_alloc_arbiter_type(sw_alloc_arbiter_type),
.vc_alloc_arbiter_type(vc_alloc_arbiter_type),
.vc_alloc_prefer_empty(vc_alloc_prefer_empty),
.crossbar_type(crossbar_type),
.reset_type(reset_type))
rtr
(.clk(clk),
.reset(reset),
.router_address(router_address),
.channel_in_ip(channel_in_ip),
.flow_ctrl_out_ip(flow_ctrl_out_ip),
.channel_out_op(channel_out_op),
.flow_ctrl_in_op(flow_ctrl_in_op),
.error(error));
end
endcase
endgenerate
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// dbg_register.v ////
//// ////
//// ////
//// This file is part of the SoC/OpenRISC Development Interface ////
//// http://www.opencores.org/cores/DebugInterface/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// [email protected] ////
//// ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000,2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: dbg_register.v,v $
// Revision 1.1 2006-12-21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.1.1.1 2002/03/21 16:55:44 lampret
// First import of the "new" XESS XSV environment.
//
//
// Revision 1.3 2001/11/26 10:47:09 mohor
// Crc generation is different for read or write commands. Small synthesys fixes.
//
// Revision 1.2 2001/10/19 11:40:02 mohor
// dbg_timescale.v changed to timescale.v This is done for the simulation of
// few different cores in a single project.
//
// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
// Initial official release.
//
//
//
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
module dbg_register(DataIn, DataOut, Write, Clk, Reset, Default);
parameter WIDTH = 8; // default parameter of the register width
input [WIDTH-1:0] DataIn;
input Write;
input Clk;
input Reset;
input [WIDTH-1:0] Default;
output [WIDTH-1:0] DataOut;
reg [WIDTH-1:0] DataOut;
//always @ (posedge Clk or posedge Reset)
always @ (posedge Clk)
begin
if(Reset)
DataOut[WIDTH-1:0]<=#1 Default;
else
begin
if(Write) // write
DataOut[WIDTH-1:0]<=#1 DataIn[WIDTH-1:0];
end
end
endmodule // Register
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A2BB2OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__A2BB2OI_BEHAVIORAL_PP_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__a2bb2oi (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out ;
wire nor1_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
nor nor1 (nor1_out_Y , nor0_out, and0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor1_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A2BB2OI_BEHAVIORAL_PP_V |
/**
* A module for getting button state from an SNES controller.
* If no controller is plugged in, serial_in should be low so
* the buttons will all be in the "off" position. The button_state
* output array is active (pressed) high. The button_state array
* has buttons in the following order (from 0 to 11): B, Y, SELECT,
* START, UP, DOWN, LEFT, RIGHT, A, X, L, R. See details at
* http://www.gamefaqs.com/snes/916396-super-nintendo/faqs/5395
*
* @author Robert Fotino, 2016
*/
module snes_controller
(
input clk,
input serial_in,
output reg data_clk,
output reg data_latch,
output reg [SNES_BUTTON_COUNT-1:0] button_state
);
initial begin
data_clk = 0;
data_latch = 0;
button_state = 0;
end
localparam SNES_BUTTON_COUNT = 12;
localparam COUNTER_60HZ_MAX = 100000000 / 60;
localparam COUNTER_12US_MAX = 1200;
localparam STATE_WAIT = 0;
localparam STATE_LATCH = 1;
localparam STATE_DATA = 2;
reg [1:0] state = STATE_WAIT;
reg [$clog2(COUNTER_60HZ_MAX)-1:0] counter_60hz = 0;
reg [$clog2(COUNTER_12US_MAX)-1:0] counter_12us = 0;
reg [3:0] data_counter = 0;
reg [SNES_BUTTON_COUNT-1:0] buf_button_state = 0;
always @ (posedge clk) begin
// Default outputs for data_clk and data_latch
data_clk <= counter_12us < 600;
data_latch <= 0;
// A 60 Hz counter for the data latch
if (COUNTER_60HZ_MAX - 1 == counter_60hz) begin
counter_60hz <= 0;
end else begin
counter_60hz <= counter_60hz + 1;
end
// A 12 microsecond counter for communication
if (COUNTER_12US_MAX - 1 == counter_12us) begin
counter_12us <= 0;
end else begin
counter_12us <= counter_12us + 1;
end
// State machine logic
case (state)
// Wait for the next change of the 60 Hz sample clock
STATE_WAIT: begin
data_clk <= 1;
if (0 == counter_60hz) begin
counter_12us <= 0;
state <= STATE_LATCH;
end
end
// Sends a 12 microsecond pulse on the data latch, indicating we are
// ready to receive the button state from the controller
STATE_LATCH: begin
data_clk <= 1;
data_latch <= 1;
if (COUNTER_12US_MAX - 1 == counter_12us) begin
state <= STATE_DATA;
end
end
// In the middle of the 12 microsecond serial data pulse, sample the
// data and shift it onto the parallel output
STATE_DATA: begin
if ((COUNTER_12US_MAX / 2) - 1 == counter_12us) begin
if (data_counter < 12) begin
buf_button_state <= { ~serial_in, buf_button_state[11:1] };
end else if (~serial_in) begin
// The serial input is always high for the last 4 pulses
// that aren't mapped to any of the 12 buttons. If the serial
// input is low, the controller isn't connected so we default low
buf_button_state <= 0;
end
if (15 == data_counter) begin
data_counter <= 0;
button_state <= buf_button_state;
state <= STATE_WAIT;
end else begin
data_counter <= data_counter + 1;
end
end
end
endcase
end
endmodule
|
module wasca (
abus_avalon_sdram_bridge_0_abus_address,
abus_avalon_sdram_bridge_0_abus_read,
abus_avalon_sdram_bridge_0_abus_waitrequest,
abus_avalon_sdram_bridge_0_abus_addressdata,
abus_avalon_sdram_bridge_0_abus_chipselect,
abus_avalon_sdram_bridge_0_abus_direction,
abus_avalon_sdram_bridge_0_abus_disable_out,
abus_avalon_sdram_bridge_0_abus_interrupt,
abus_avalon_sdram_bridge_0_abus_muxing,
abus_avalon_sdram_bridge_0_abus_writebyteenable_n,
abus_avalon_sdram_bridge_0_abus_reset,
abus_avalon_sdram_bridge_0_sdram_addr,
abus_avalon_sdram_bridge_0_sdram_ba,
abus_avalon_sdram_bridge_0_sdram_cas_n,
abus_avalon_sdram_bridge_0_sdram_cke,
abus_avalon_sdram_bridge_0_sdram_cs_n,
abus_avalon_sdram_bridge_0_sdram_dq,
abus_avalon_sdram_bridge_0_sdram_dqm,
abus_avalon_sdram_bridge_0_sdram_ras_n,
abus_avalon_sdram_bridge_0_sdram_we_n,
abus_avalon_sdram_bridge_0_sdram_clk,
altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_cmd,
altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat,
altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat3,
altera_up_sd_card_avalon_interface_0_conduit_end_o_SD_clock,
altpll_1_areset_conduit_export,
altpll_1_locked_conduit_export,
altpll_1_phasedone_conduit_export,
audio_out_BCLK,
audio_out_DACDAT,
audio_out_DACLRCK,
buffered_spi_mosi,
buffered_spi_clk,
buffered_spi_miso,
buffered_spi_cs,
clk_clk,
clock_116_mhz_clk,
reset_reset_n,
reset_controller_0_reset_in1_reset,
uart_0_external_connection_rxd,
uart_0_external_connection_txd);
input [9:0] abus_avalon_sdram_bridge_0_abus_address;
input abus_avalon_sdram_bridge_0_abus_read;
output abus_avalon_sdram_bridge_0_abus_waitrequest;
inout [15:0] abus_avalon_sdram_bridge_0_abus_addressdata;
input [2:0] abus_avalon_sdram_bridge_0_abus_chipselect;
output abus_avalon_sdram_bridge_0_abus_direction;
output abus_avalon_sdram_bridge_0_abus_disable_out;
output abus_avalon_sdram_bridge_0_abus_interrupt;
output [1:0] abus_avalon_sdram_bridge_0_abus_muxing;
input [1:0] abus_avalon_sdram_bridge_0_abus_writebyteenable_n;
input abus_avalon_sdram_bridge_0_abus_reset;
output [12:0] abus_avalon_sdram_bridge_0_sdram_addr;
output [1:0] abus_avalon_sdram_bridge_0_sdram_ba;
output abus_avalon_sdram_bridge_0_sdram_cas_n;
output abus_avalon_sdram_bridge_0_sdram_cke;
output abus_avalon_sdram_bridge_0_sdram_cs_n;
inout [15:0] abus_avalon_sdram_bridge_0_sdram_dq;
output [1:0] abus_avalon_sdram_bridge_0_sdram_dqm;
output abus_avalon_sdram_bridge_0_sdram_ras_n;
output abus_avalon_sdram_bridge_0_sdram_we_n;
output abus_avalon_sdram_bridge_0_sdram_clk;
inout altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_cmd;
inout altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat;
inout altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat3;
output altera_up_sd_card_avalon_interface_0_conduit_end_o_SD_clock;
input altpll_1_areset_conduit_export;
output altpll_1_locked_conduit_export;
output altpll_1_phasedone_conduit_export;
input audio_out_BCLK;
output audio_out_DACDAT;
input audio_out_DACLRCK;
output buffered_spi_mosi;
output buffered_spi_clk;
input buffered_spi_miso;
output buffered_spi_cs;
input clk_clk;
output clock_116_mhz_clk;
input reset_reset_n;
input reset_controller_0_reset_in1_reset;
input uart_0_external_connection_rxd;
output uart_0_external_connection_txd;
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ab
//
// Generated
// by: wig
// on: Wed Jul 16 10:16:52 2003
// cmd: H:\work\mix\mix_0.pl -nodelta ..\conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ab.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_ab.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
// Revision 1.1 2004/04/06 11:12:09 wig
// Adding result/conf
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.19 2003/07/09 07:52:44 wig Exp
//
// Generator: mix_0.pl Revision: 1.13 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
'timescale 1ns / 1ns;
//
//
// Start of Generated Module rtl of ent_ab
//
module ent_ab
//
// Generated module inst_ab
//
(
port_ab_1,
port_ab_2,
sig_13,
);
// Generated Module Inputs:
input port_ab_1;
input [4:0] sig_13;
// Generated Module Outputs:
output port_ab_2;
// Generated Wires:
wire port_ab_1;
wire port_ab_2;
wire [4:0] sig_13;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//TODO: %VERI_CONSTANTS%
// %VERI_CONCURS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_ab
//
//
//!End of Module/s
// --------------------------------------------------------------
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ab
//
// Generated
// by: wig
// on: Tue Jul 22 11:18:49 2003
// cmd: H:\work\mix\mix_0.pl -nodelta ..\conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ab.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_ab.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
// Revision 1.1 2004/04/06 11:12:09 wig
// Adding result/conf
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.21 2003/07/17 12:10:43 wig Exp
//
// Generator: mix_0.pl Revision: 1.13 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps;
//
//
// Start of Generated Module rtl of ent_ab
//
// No `defines in this module
module ent_ab
//
// Generated module inst_ab
//
(
port_ab_1,
port_ab_2,
sig_13,
);
// Generated Module Inputs:
input port_ab_1;
input [4:0] sig_13;
// Generated Module Outputs:
output port_ab_2;
// Generated Wires:
wire port_ab_1;
wire port_ab_2;
wire [4:0] sig_13;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//TODO: %VERI_CONSTANTS%
// %VERI_CONCURS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_ab
//
//
//!End of Module/s
// --------------------------------------------------------------
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ab
//
// Generated
// by: wig
// on: Tue Aug 12 16:53:17 2003
// cmd: H:\work\mix\mix_0.pl -nodelta ..\conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ab.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_ab.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
// Revision 1.1 2004/04/06 11:12:09 wig
// Adding result/conf
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.24 2003/08/11 07:16:25 wig Exp
//
// Generator: mix_0.pl Revision: 1.14 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_ab
//
// No `defines in this module
module ent_ab
//
// Generated module inst_ab
//
(
port_ab_1,
port_ab_2,
sig_13,
);
// Generated Module Inputs:
input port_ab_1;
input [4:0] sig_13;
// Generated Module Outputs:
output port_ab_2;
// Generated Wires:
wire port_ab_1;
wire port_ab_2;
wire [4:0] sig_13;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_ab
//
//
//!End of Module/s
// --------------------------------------------------------------
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ab
//
// Generated
// by: wig
// on: Mon Sep 8 17:52:50 2003
// cmd: H:\work\mix\mix_0.pl -nodelta ..\conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ab.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_ab.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
// Revision 1.1 2004/04/06 11:12:09 wig
// Adding result/conf
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.27 2003/09/08 15:14:24 wig Exp
//
// Generator: mix_0.pl Revision: 1.14 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_ab
//
// No `defines in this module
module ent_ab
//
// Generated module inst_ab
//
(
port_ab_1,
port_ab_2,
sig_13,
);
// Generated Module Inputs:
input port_ab_1;
input [4:0] sig_13;
// Generated Module Outputs:
output port_ab_2;
// Generated Wires:
wire port_ab_1;
wire port_ab_2;
wire [4:0] sig_13;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_ab
//
//
//!End of Module/s
// --------------------------------------------------------------
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ab
//
// Generated
// by: wig
// on: Wed Oct 8 09:51:06 2003
// cmd: H:\work\mix\mix_0.pl -nodelta ..\conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ab.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_ab.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
// Revision 1.1 2004/04/06 11:12:09 wig
// Adding result/conf
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.27 2003/09/08 15:14:24 wig Exp
//
// Generator: mix_0.pl Revision: 1.14 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_ab
//
// No `defines in this module
module ent_ab
//
// Generated module inst_ab
//
(
port_ab_1,
port_ab_2,
sig_13
);
// Generated Module Inputs:
input port_ab_1;
input [4:0] sig_13;
// Generated Module Outputs:
output port_ab_2;
// Generated Wires:
wire port_ab_1;
wire port_ab_2;
wire [4:0] sig_13;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_ab
//
//
//!End of Module/s
// --------------------------------------------------------------
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ab
//
// Generated
// by: wig
// on: Wed Oct 8 10:24:03 2003
// cmd: H:\work\mix\mix_0.pl -nodelta ..\conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ab.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_ab.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
// Revision 1.1 2004/04/06 11:12:09 wig
// Adding result/conf
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.27 2003/09/08 15:14:24 wig Exp
//
// Generator: mix_0.pl Revision: 1.14 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_ab
//
// No `defines in this module
module ent_ab
//
// Generated module inst_ab
//
(
port_ab_1,
port_ab_2,
sig_13
);
// Generated Module Inputs:
input port_ab_1;
input [4:0] sig_13;
// Generated Module Outputs:
output port_ab_2;
// Generated Wires:
wire port_ab_1;
wire port_ab_2;
wire [4:0] sig_13;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_ab
//
//
//!End of Module/s
// --------------------------------------------------------------
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ab
//
// Generated
// by: wig
// on: Mon Oct 13 09:32:34 2003
// cmd: H:\work\mix\mix_0.pl -nodelta ..\conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ab.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_ab.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
// Revision 1.1 2004/04/06 11:12:09 wig
// Adding result/conf
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.27 2003/09/08 15:14:24 wig Exp
//
// Generator: mix_0.pl Revision: 1.14 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_ab
//
// No `defines in this module
module ent_ab
//
// Generated module inst_ab
//
(
port_ab_1,
port_ab_2,
sig_13
);
// Generated Module Inputs:
input port_ab_1;
input [4:0] sig_13;
// Generated Module Outputs:
output port_ab_2;
// Generated Wires:
wire port_ab_1;
wire port_ab_2;
wire [4:0] sig_13;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_ab
//
//
//!End of Module/s
// --------------------------------------------------------------
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ab
//
// Generated
// by: wig
// on: Thu Nov 6 15:57:35 2003
// cmd: H:\work\mix\mix_0.pl -nodelta ..\conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ab.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_ab.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
// Revision 1.1 2004/04/06 11:12:09 wig
// Adding result/conf
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.31 2003/10/23 12:13:17 wig Exp
//
// Generator: mix_0.pl Revision: 1.17 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_ab
//
// No `defines in this module
module ent_ab
//
// Generated module inst_ab
//
(
port_ab_1,
port_ab_2,
sig_13
);
// Generated Module Inputs:
input port_ab_1;
input [4:0] sig_13;
// Generated Module Outputs:
output port_ab_2;
// Generated Wires:
wire port_ab_1;
wire port_ab_2;
wire [4:0] sig_13;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_ab
//
//
//!End of Module/s
// --------------------------------------------------------------
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ab
//
// Generated
// by: wig
// on: Fri Jul 15 12:55:13 2005
// cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ab.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_ab.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
//
// Generator: mix_0.pl Revision: 1.36 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_ab
//
// No `defines in this module
module ent_ab
//
// Generated module inst_ab
//
(
port_ab_1,
port_ab_2,
sig_13
);
// Generated Module Inputs:
input port_ab_1;
input [4:0] sig_13;
// Generated Module Outputs:
output port_ab_2;
// Generated Wires:
wire port_ab_1;
wire port_ab_2;
wire [4:0] sig_13;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_ab
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKBUF_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__CLKBUF_PP_BLACKBOX_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__clkbuf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKBUF_PP_BLACKBOX_V
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Expert(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Wed Oct 19 14:29:52 2016
/////////////////////////////////////////////////////////////
module Priority_Codec_32 ( Data_Dec_i, Data_Bin_o );
input [25:0] Data_Dec_i;
output [4:0] Data_Bin_o;
wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16,
n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44,
n45, n46, n47, n48, n49, n50;
NOR3BX1TS U3 ( .AN(n25), .B(Data_Dec_i[18]), .C(n6), .Y(n31) );
NOR3BX1TS U4 ( .AN(n39), .B(Data_Dec_i[10]), .C(Data_Dec_i[11]), .Y(
Data_Bin_o[4]) );
INVX2TS U5 ( .A(n31), .Y(n5) );
AOI31X1TS U6 ( .A0(n7), .A1(n1), .A2(n40), .B0(n41), .Y(n34) );
INVX2TS U7 ( .A(Data_Bin_o[4]), .Y(n4) );
INVX2TS U8 ( .A(n42), .Y(n6) );
INVX2TS U9 ( .A(n16), .Y(n3) );
NOR2X1TS U10 ( .A(n22), .B(n23), .Y(n21) );
NOR4BX1TS U11 ( .AN(n13), .B(n5), .C(Data_Dec_i[13]), .D(Data_Dec_i[14]),
.Y(n50) );
NOR3X1TS U12 ( .A(Data_Dec_i[24]), .B(Data_Dec_i[25]), .C(n40), .Y(n42) );
NOR4BX1TS U13 ( .AN(n24), .B(n4), .C(Data_Dec_i[5]), .D(Data_Dec_i[6]), .Y(
n49) );
NOR2BX1TS U14 ( .AN(n50), .B(Data_Dec_i[12]), .Y(n39) );
NAND2BX1TS U15 ( .AN(Data_Dec_i[3]), .B(n38), .Y(n16) );
NAND4X1TS U16 ( .A(n32), .B(n33), .C(n34), .D(n35), .Y(Data_Bin_o[1]) );
NAND4BX1TS U17 ( .AN(Data_Dec_i[21]), .B(Data_Dec_i[19]), .C(n42), .D(n9),
.Y(n32) );
NAND4BX1TS U18 ( .AN(Data_Dec_i[17]), .B(Data_Dec_i[15]), .C(n31), .D(n10),
.Y(n33) );
NOR2BX1TS U19 ( .AN(n49), .B(Data_Dec_i[4]), .Y(n38) );
NAND2BX1TS U20 ( .AN(Data_Dec_i[23]), .B(n8), .Y(n40) );
NAND2X1TS U21 ( .A(Data_Dec_i[2]), .B(n3), .Y(n20) );
NAND4X1TS U22 ( .A(n26), .B(n28), .C(n48), .D(n17), .Y(n41) );
AOI31X1TS U23 ( .A0(Data_Bin_o[4]), .A1(n24), .A2(Data_Dec_i[6]), .B0(n2),
.Y(n48) );
INVX2TS U24 ( .A(n20), .Y(n2) );
INVX2TS U25 ( .A(Data_Dec_i[22]), .Y(n8) );
NOR4BX1TS U26 ( .AN(n29), .B(n36), .C(n23), .D(n37), .Y(n35) );
NOR4BX1TS U27 ( .AN(Data_Dec_i[7]), .B(Data_Dec_i[9]), .C(Data_Dec_i[8]),
.D(n4), .Y(n37) );
NOR3X1TS U28 ( .A(n16), .B(Data_Dec_i[1]), .C(Data_Dec_i[0]), .Y(n36) );
NOR3X1TS U29 ( .A(Data_Dec_i[16]), .B(Data_Dec_i[17]), .C(Data_Dec_i[15]),
.Y(n13) );
NOR3X1TS U30 ( .A(Data_Dec_i[20]), .B(Data_Dec_i[21]), .C(Data_Dec_i[19]),
.Y(n25) );
NAND3BX1TS U31 ( .AN(n43), .B(n44), .C(n45), .Y(Data_Bin_o[0]) );
OAI31X1TS U32 ( .A0(n4), .A1(Data_Dec_i[9]), .A2(n11), .B0(n30), .Y(n43) );
AOI31X1TS U33 ( .A0(n3), .A1(n12), .A2(Data_Dec_i[0]), .B0(n22), .Y(n44) );
NAND4BX1TS U34 ( .AN(n18), .B(n19), .C(n20), .D(n21), .Y(Data_Bin_o[2]) );
NAND4BX1TS U35 ( .AN(Data_Dec_i[6]), .B(Data_Dec_i[5]), .C(Data_Bin_o[4]),
.D(n24), .Y(n19) );
OAI211X1TS U36 ( .A0(n6), .A1(n25), .B0(n14), .C0(n26), .Y(n18) );
OAI211X1TS U37 ( .A0(n13), .A1(n5), .B0(n14), .C0(n15), .Y(Data_Bin_o[3]) );
OA21XLTS U38 ( .A0(n16), .A1(Data_Dec_i[2]), .B0(n17), .Y(n15) );
AND2X2TS U39 ( .A(Data_Dec_i[3]), .B(n38), .Y(n23) );
AND2X2TS U40 ( .A(Data_Dec_i[4]), .B(n49), .Y(n22) );
AOI211X1TS U41 ( .A0(n46), .A1(n1), .B0(n47), .C0(n41), .Y(n45) );
OAI21X1TS U42 ( .A0(Data_Dec_i[23]), .A1(n8), .B0(n7), .Y(n46) );
OAI33XLTS U43 ( .A0(n9), .A1(Data_Dec_i[21]), .A2(n6), .B0(n10), .B1(
Data_Dec_i[17]), .B2(n5), .Y(n47) );
NAND3BX1TS U44 ( .AN(Data_Dec_i[11]), .B(n39), .C(Data_Dec_i[10]), .Y(n28)
);
NAND2X1TS U45 ( .A(Data_Dec_i[12]), .B(n50), .Y(n30) );
NAND2X1TS U46 ( .A(Data_Dec_i[11]), .B(n39), .Y(n29) );
AND4X1TS U47 ( .A(n27), .B(n28), .C(n29), .D(n30), .Y(n14) );
NAND4BX1TS U48 ( .AN(Data_Dec_i[14]), .B(Data_Dec_i[13]), .C(n31), .D(n13),
.Y(n27) );
NAND3X1TS U49 ( .A(n31), .B(n13), .C(Data_Dec_i[14]), .Y(n17) );
NOR3X1TS U50 ( .A(Data_Dec_i[8]), .B(Data_Dec_i[9]), .C(Data_Dec_i[7]), .Y(
n24) );
NAND3X1TS U51 ( .A(n42), .B(n25), .C(Data_Dec_i[18]), .Y(n26) );
INVX2TS U52 ( .A(Data_Dec_i[20]), .Y(n9) );
INVX2TS U53 ( .A(Data_Dec_i[16]), .Y(n10) );
INVX2TS U54 ( .A(Data_Dec_i[24]), .Y(n7) );
INVX2TS U55 ( .A(Data_Dec_i[25]), .Y(n1) );
INVX2TS U56 ( .A(Data_Dec_i[8]), .Y(n11) );
INVX2TS U57 ( .A(Data_Dec_i[1]), .Y(n12) );
endmodule
module RegisterAdd_W5 ( clk, rst, load, D, Q );
input [4:0] D;
output [4:0] Q;
input clk, rst, load;
wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11;
OAI2BB2XLTS U2 ( .B0(n1), .B1(load), .A0N(load), .A1N(D[0]), .Y(n6) );
OAI2BB2XLTS U3 ( .B0(n2), .B1(load), .A0N(D[1]), .A1N(load), .Y(n7) );
OAI2BB2XLTS U4 ( .B0(n3), .B1(load), .A0N(D[2]), .A1N(load), .Y(n8) );
OAI2BB2XLTS U5 ( .B0(n4), .B1(load), .A0N(D[3]), .A1N(load), .Y(n9) );
CLKINVX1TS U6 ( .A(rst), .Y(n10) );
OAI2BB2XLTS U7 ( .B0(n5), .B1(load), .A0N(D[4]), .A1N(load), .Y(n11) );
DFFRX2TS \Q_reg[4] ( .D(n11), .CK(clk), .RN(n10), .Q(Q[4]), .QN(n5) );
DFFRX2TS \Q_reg[3] ( .D(n9), .CK(clk), .RN(n10), .Q(Q[3]), .QN(n4) );
DFFRX2TS \Q_reg[2] ( .D(n8), .CK(clk), .RN(n10), .Q(Q[2]), .QN(n3) );
DFFRX2TS \Q_reg[1] ( .D(n7), .CK(clk), .RN(n10), .Q(Q[1]), .QN(n2) );
DFFRX2TS \Q_reg[0] ( .D(n6), .CK(clk), .RN(n10), .Q(Q[0]), .QN(n1) );
endmodule
module LZD ( clk, rst, load_i, Add_subt_result_i, Shift_Value_o );
input [25:0] Add_subt_result_i;
output [4:0] Shift_Value_o;
input clk, rst, load_i;
wire [4:0] Codec_to_Reg;
Priority_Codec_32 \LZD_SINGLEBLK.Codec_32 ( .Data_Dec_i(Add_subt_result_i),
.Data_Bin_o(Codec_to_Reg) );
RegisterAdd_W5 Output_Reg ( .clk(clk), .rst(rst), .load(load_i), .D(
Codec_to_Reg), .Q(Shift_Value_o) );
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD1_SYMBOL_V
`define SKY130_FD_SC_LS__CLKDLYINV3SD1_SYMBOL_V
/**
* clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
* stage gate.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__clkdlyinv3sd1 (
//# {{data|Data Signals}}
input A,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV3SD1_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYMETAL6S2S_FUNCTIONAL_V
`define SKY130_FD_SC_LP__DLYMETAL6S2S_FUNCTIONAL_V
/**
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__dlymetal6s2s (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYMETAL6S2S_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A2111O_4_V
`define SKY130_FD_SC_LS__A2111O_4_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog wrapper for a2111o with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a2111o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a2111o_4 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a2111o_4 (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A2111O_4_V
|
(** * Hoare2: Hoare Logic, Part II *)
Require Import Coq.Bool.Bool.
Require Import Coq.Arith.Arith.
Require Import Coq.Arith.EqNat.
Require Import Coq.omega.Omega.
Require Import SfLib.
Require Import Maps.
Require Import Imp.
Require Import Hoare.
(* ################################################################# *)
(** * Decorated Programs *)
(** The beauty of Hoare Logic is that it is _compositional_: the
structure of proofs exactly follows the structure of programs.
This suggests that we can record the essential ideas of a proof
informally (leaving out some low-level calculational details) by
decorating a program with appropriate assertions on each of its
commands. Such a _decorated program_ carries with it
an (informal) proof of its own correctness.
For example, here is a complete decorated program: *)
(**
{{ True }} ->>
{{ m = m }}
X ::= m;;
{{ X = m }} ->>
{{ X = m /\ p = p }}
Z ::= p;
{{ X = m /\ Z = p }} ->>
{{ Z - X = p - m }}
WHILE X <> 0 DO
{{ Z - X = p - m /\ X <> 0 }} ->>
{{ (Z - 1) - (X - 1) = p - m }}
Z ::= Z - 1;;
{{ Z - (X - 1) = p - m }}
X ::= X - 1
{{ Z - X = p - m }}
END;
{{ Z - X = p - m /\ ~ (X <> 0) }} ->>
{{ Z = p - m }}
*)
(** Concretely, a decorated program consists of the program text
interleaved with assertions (either a single assertion or possibly
two assertions separated by an implication). To check that a
decorated program represents a valid proof, we check that each
individual command is _locally consistent_ with its nearby
assertions in the following sense: *)
(** - [SKIP] is locally consistent if its precondition and
postcondition are the same:
{{ P }}
SKIP
{{ P }}
*)
(** - The sequential composition of [c1] and [c2] is locally
consistent (with respect to assertions [P] and [R]) if [c1] is
locally consistent (with respect to [P] and [Q]) and [c2] is
locally consistent (with respect to [Q] and [R]):
{{ P }}
c1;;
{{ Q }}
c2
{{ R }}
*)
(** - An assignment is locally consistent if its precondition is
the appropriate substitution of its postcondition:
{{ P [X |-> a] }}
X ::= a
{{ P }}
*)
(** - A conditional is locally consistent (with respect to assertions
[P] and [Q]) if the assertions at the top of its "then" and
"else" branches are exactly [P /\ b] and [P /\ ~b] and if its "then"
branch is locally consistent (with respect to [P /\ b] and [Q])
and its "else" branch is locally consistent (with respect to
[P /\ ~b] and [Q]):
{{ P }}
IFB b THEN
{{ P /\ b }}
c1
{{ Q }}
ELSE
{{ P /\ ~b }}
c2
{{ Q }}
FI
{{ Q }}
*)
(** - A while loop with precondition [P] is locally consistent if its
postcondition is [P /\ ~b], if the pre- and postconditions of
its body are exactly [P /\ b] and [P], and if its body is locally
consistent:
{{ P }}
WHILE b DO
{{ P /\ b }}
c1
{{ P }}
END
{{ P /\ ~b }}
*)
(** - A pair of assertions separated by [->>] is locally consistent if
the first implies the second (in all states):
{{ P }} ->>
{{ P' }}
This corresponds to the application of [hoare_consequence] and
is the only place in a decorated program where checking if
decorations are correct is not fully mechanical and syntactic,
but rather may involve logical and/or arithmetic reasoning. *)
(** The above essentially describes a procedure for _verifying_
the correctness of a given proof involves checking that every
single command is locally consistent with the accompanying
assertions. If we are instead interested in _finding_ a proof for
a given specification, we need to discover the right assertions.
This can be done in an almost mechanical way, with the exception
of finding loop invariants, which is the subject of the next
section. In the remainder of this section we explain in detail how
to construct decorations for several simple programs that don't
involve non-trivial loop invariants. *)
(* ================================================================= *)
(** ** Example: Swapping Using Addition and Subtraction *)
(** Here is a program that swaps the values of two variables using
addition and subtraction (instead of by assigning to a temporary
variable).
X ::= X + Y;;
Y ::= X - Y;;
X ::= X - Y
We can prove using decorations that this program is correct --
i.e., it always swaps the values of variables [X] and [Y]. *)
(**
(1) {{ X = m /\ Y = n }} ->>
(2) {{ (X + Y) - ((X + Y) - Y) = n /\ (X + Y) - Y = m }}
X ::= X + Y;;
(3) {{ X - (X - Y) = n /\ X - Y = m }}
Y ::= X - Y;;
(4) {{ X - Y = n /\ Y = m }}
X ::= X - Y
(5) {{ X = n /\ Y = m }}
*)
(** These decorations can be constructed as follows:
- We begin with the undecorated program (the unnumbered lines).
- We then add the specification -- i.e., the outer
precondition (1) and postcondition (5). In the precondition we
use auxiliary variables (parameters) [m] and [n] to remember
the initial values of variables [X] and respectively [Y], so
that we can refer to them in the postcondition (5).
- We work backwards mechanically, starting from (5) and
proceeding until we get to (2). At each step, we obtain the
precondition of the assignment from its postcondition by
substituting the assigned variable with the right-hand-side of
the assignment. For instance, we obtain (4) by substituting
[X] with [X - Y] in (5), and (3) by substituting [Y] with [X -
Y] in (4).
- Finally, we verify that (1) logically implies (2) -- i.e.,
that the step from (1) to (2) is a valid use of the law of
consequence. For this we substitute [X] by [m] and [Y] by [n]
and calculate as follows:
(m + n) - ((m + n) - n) = n /\ (m + n) - n = m
(m + n) - m = n /\ m = m
n = n /\ m = m
Note that, since we are working with natural numbers, not
fixed-width machine integers, we don't need to worry about the
possibility of arithmetic overflow anywhere in this argument.
This makes life quite a bit simpler! *)
(* ================================================================= *)
(** ** Example: Simple Conditionals *)
(** Here is a simple decorated program using conditionals:
(1) {{True}}
IFB X <= Y THEN
(2) {{True /\ X <= Y}} ->>
(3) {{(Y - X) + X = Y \/ (Y - X) + Y = X}}
Z ::= Y - X
(4) {{Z + X = Y \/ Z + Y = X}}
ELSE
(5) {{True /\ ~(X <= Y) }} ->>
(6) {{(X - Y) + X = Y \/ (X - Y) + Y = X}}
Z ::= X - Y
(7) {{Z + X = Y \/ Z + Y = X}}
FI
(8) {{Z + X = Y \/ Z + Y = X}}
These decorations were constructed as follows:
- We start with the outer precondition (1) and postcondition (8).
- We follow the format dictated by the [hoare_if] rule and copy the
postcondition (8) to (4) and (7). We conjoin the precondition (1)
with the guard of the conditional to obtain (2). We conjoin (1)
with the negated guard of the conditional to obtain (5).
- In order to use the assignment rule and obtain (3), we substitute
[Z] by [Y - X] in (4). To obtain (6) we substitute [Z] by [X - Y]
in (7).
- Finally, we verify that (2) implies (3) and (5) implies (6). Both
of these implications crucially depend on the ordering of [X] and
[Y] obtained from the guard. For instance, knowing that [X <= Y]
ensures that subtracting [X] from [Y] and then adding back [X]
produces [Y], as required by the first disjunct of (3). Similarly,
knowing that [~ (X <= Y)] ensures that subtracting [Y] from [X] and
then adding back [Y] produces [X], as needed by the second
disjunct of (6). Note that [n - m + m = n] does _not_ hold for
arbitrary natural numbers [n] and [m] (for example, [3 - 5 + 5 =
5]). *)
(** **** Exercise: 2 stars (if_minus_plus_reloaded) *)
(** Fill in valid decorations for the following program:
{{ True }}
IFB X <= Y THEN
{{ }} ->>
{{ }}
Z ::= Y - X
{{ }}
ELSE
{{ }} ->>
{{ }}
Y ::= X + Z
{{ }}
FI
{{ Y = X + Z }}
*)
(** [] *)
(* ================================================================= *)
(** ** Example: Reduce to Zero *)
(** Here is a [WHILE] loop that is so simple it needs no
invariant (i.e., the invariant [True] will do the job).
(1) {{ True }}
WHILE X <> 0 DO
(2) {{ True /\ X <> 0 }} ->>
(3) {{ True }}
X ::= X - 1
(4) {{ True }}
END
(5) {{ True /\ X = 0 }} ->>
(6) {{ X = 0 }}
The decorations can be constructed as follows:
- Start with the outer precondition (1) and postcondition (6).
- Following the format dictated by the [hoare_while] rule, we copy
(1) to (4). We conjoin (1) with the guard to obtain (2) and with
the negation of the guard to obtain (5). Note that, because the
outer postcondition (6) does not syntactically match (5), we need a
trivial use of the consequence rule from (5) to (6).
- Assertion (3) is the same as (4), because [X] does not appear in
[4], so the substitution in the assignment rule is trivial.
- Finally, the implication between (2) and (3) is also trivial. *)
(** From this informal proof, it is easy to read off a formal proof
using the Coq versions of the Hoare rules. Note that we do _not_
unfold the definition of [hoare_triple] anywhere in this proof --
the idea is to use the Hoare rules as a "self-contained" logic for
reasoning about programs. *)
Definition reduce_to_zero' : com :=
WHILE BNot (BEq (AId X) (ANum 0)) DO
X ::= AMinus (AId X) (ANum 1)
END.
Theorem reduce_to_zero_correct' :
{{fun st => True}}
reduce_to_zero'
{{fun st => st X = 0}}.
Proof.
unfold reduce_to_zero'.
(* First we need to transform the postcondition so
that hoare_while will apply. *)
eapply hoare_consequence_post.
apply hoare_while.
- (* Loop body preserves invariant *)
(* Need to massage precondition before [hoare_asgn] applies *)
eapply hoare_consequence_pre. apply hoare_asgn.
(* Proving trivial implication (2) ->> (3) *)
intros st [HT Hbp]. unfold assn_sub. apply I.
- (* Invariant and negated guard imply postcondition *)
intros st [Inv GuardFalse].
unfold bassn in GuardFalse. simpl in GuardFalse.
(* SearchAbout helps to find the right lemmas *)
SearchAbout [not true].
rewrite not_true_iff_false in GuardFalse.
SearchAbout [negb false].
rewrite negb_false_iff in GuardFalse.
SearchAbout [beq_nat true].
apply beq_nat_true in GuardFalse.
apply GuardFalse. Qed.
(* ================================================================= *)
(** ** Example: Division *)
(** The following Imp program calculates the integer quotient and
remainder of two numbers [m] and [n] that are arbitrary constants
in the program.
X ::= m;;
Y ::= 0;;
WHILE n <= X DO
X ::= X - n;;
Y ::= Y + 1
END;
In we replace [m] and [n] by concrete numbers and execute the program,
it will terminate with the variable [X] set to the remainder when [m]
is divided by [n] and [Y] set to the quotient. *)
(** In order to give a specification to this program we need to
remember that dividing [m] by [n] produces a reminder [X] and a
quotient [Y] such that [n * Y + X = m /\ X < n].
It turns out that we get lucky with this program and don't have to
think very hard about the loop invariant: the invariant is just the
first conjunct [n * Y + X = m], and we can use this to decorate
the program.
(1) {{ True }} ->>
(2) {{ n * 0 + m = m }}
X ::= m;;
(3) {{ n * 0 + X = m }}
Y ::= 0;;
(4) {{ n * Y + X = m }}
WHILE n <= X DO
(5) {{ n * Y + X = m /\ n <= X }} ->>
(6) {{ n * (Y + 1) + (X - n) = m }}
X ::= X - n;;
(7) {{ n * (Y + 1) + X = m }}
Y ::= Y + 1
(8) {{ n * Y + X = m }}
END
(9) {{ n * Y + X = m /\ X < n }}
Assertions (4), (5), (8), and (9) are derived mechanically from
the invariant and the loop's guard. Assertions (8), (7), and (6)
are derived using the assignment rule going backwards from (8) to
(6). Assertions (4), (3), and (2) are again backwards applications
of the assignment rule.
Now that we've decorated the program it only remains to check that
the two uses of the consequence rule are correct -- i.e., that (1)
implies (2) and that (5) implies (6). This is indeed the case, so
we have a valid decorated program. *)
(* ################################################################# *)
(** * Finding Loop Invariants *)
(** Once the outermost precondition and postcondition are
chosen, the only creative part in verifying programs using Hoare
Logic is finding the right loop invariants. The reason this is
difficult is the same as the reason that inductive mathematical
proofs are: strengthening the loop invariant (or the induction
hypothesis) means that you have a stronger assumption to work with
when trying to establish the postcondition of the loop body (or
complete the induction step of the proof), but it also means that
the loop body postcondition itself (or the statement being proved
inductively) is stronger and thus harder to prove!
This section shows how to approach the challenge of finding loop
invariants through a series of examples and exercises. *)
(* ================================================================= *)
(** ** Example: Slow Subtraction *)
(** The following program subtracts the value of [X] from the value of
[Y] by repeatedly decrementing both [X] and [Y]. We want to verify its
correctness with respect to the following specification:
{{ X = m /\ Y = n }}
WHILE X <> 0 DO
Y ::= Y - 1;;
X ::= X - 1
END
{{ Y = n - m }}
To verify this program, we need to find an invariant [I] for the
loop. As a first step we can leave [I] as an unknown and build a
_skeleton_ for the proof by applying (backward) the rules for local
consistency. This process leads to the following skeleton:
(1) {{ X = m /\ Y = n }} ->> (a)
(2) {{ I }}
WHILE X <> 0 DO
(3) {{ I /\ X <> 0 }} ->> (c)
(4) {{ I [X |-> X-1] [Y |-> Y-1] }}
Y ::= Y - 1;;
(5) {{ I [X |-> X-1] }}
X ::= X - 1
(6) {{ I }}
END
(7) {{ I /\ ~ (X <> 0) }} ->> (b)
(8) {{ Y = n - m }}
By examining this skeleton, we can see that any valid [I] will
have to respect three conditions:
- (a) it must be weak enough to be implied by the loop's
precondition, i.e., (1) must imply (2);
- (b) it must be strong enough to imply the loop's postcondition,
i.e., (7) must imply (8);
- (c) it must be preserved by one iteration of the loop, i.e., (3)
must imply (4). *)
(** These conditions are actually independent of the particular
program and specification we are considering. Indeed, every loop
invariant has to satisfy them. One way to find an invariant that
simultaneously satisfies these three conditions is by using an
iterative process: start with a "candidate" invariant (e.g., a
guess or a heuristic choice) and check the three conditions above;
if any of the checks fails, try to use the information that we get
from the failure to produce another -- hopefully better -- candidate
invariant, and repeat the process.
For instance, in the reduce-to-zero example above, we saw that,
for a very simple loop, choosing [True] as an invariant did the
job. So let's try instantiating [I] with [True] in the skeleton
above see what we get...
(1) {{ X = m /\ Y = n }} ->> (a - OK)
(2) {{ True }}
WHILE X <> 0 DO
(3) {{ True /\ X <> 0 }} ->> (c - OK)
(4) {{ True }}
Y ::= Y - 1;;
(5) {{ True }}
X ::= X - 1
(6) {{ True }}
END
(7) {{ True /\ X = 0 }} ->> (b - WRONG!)
(8) {{ Y = n - m }}
While conditions (a) and (c) are trivially satisfied,
condition (b) is wrong, i.e., it is not the case that (7) [True /\
X = 0] implies (8) [Y = n - m]. In fact, the two assertions are
completely unrelated, so it is very easy to find a counterexample
to the implication (say, [Y = X = m = 0] and [n = 1]).
If we want (b) to hold, we need to strengthen the invariant so
that it implies the postcondition (8). One simple way to do
this is to let the invariant _be_ the postcondition. So let's
return to our skeleton, instantiate [I] with [Y = n - m], and
check conditions (a) to (c) again.
(1) {{ X = m /\ Y = n }} ->> (a - WRONG!)
(2) {{ Y = n - m }}
WHILE X <> 0 DO
(3) {{ Y = n - m /\ X <> 0 }} ->> (c - WRONG!)
(4) {{ Y - 1 = n - m }}
Y ::= Y - 1;;
(5) {{ Y = n - m }}
X ::= X - 1
(6) {{ Y = n - m }}
END
(7) {{ Y = n - m /\ X = 0 }} ->> (b - OK)
(8) {{ Y = n - m }}
This time, condition (b) holds trivially, but (a) and (c) are
broken. Condition (a) requires that (1) [X = m /\ Y = n]
implies (2) [Y = n - m]. If we substitute [Y] by [n] we have to
show that [n = n - m] for arbitrary [m] and [n], which is not
the case (for instance, when [m = n = 1]). Condition (c) requires
that [n - m - 1 = n - m], which fails, for instance, for [n = 1]
and [m = 0]. So, although [Y = n - m] holds at the end of the loop,
it does not hold from the start, and it doesn't hold on each
iteration; it is not a correct invariant.
This failure is not very surprising: the variable [Y] changes
during the loop, while [m] and [n] are constant, so the assertion
we chose didn't have much chance of being an invariant!
To do better, we need to generalize (8) to some statement that is
equivalent to (8) when [X] is [0], since this will be the case
when the loop terminates, and that "fills the gap" in some
appropriate way when [X] is nonzero. Looking at how the loop
works, we can observe that [X] and [Y] are decremented together
until [X] reaches [0]. So, if [X = 2] and [Y = 5] initially,
after one iteration of the loop we obtain [X = 1] and [Y = 4];
after two iterations [X = 0] and [Y = 3]; and then the loop stops.
Notice that the difference between [Y] and [X] stays constant
between iterations: initially, [Y = n] and [X = m], and the
difference is always [n - m]. So let's try instantiating [I] in
the skeleton above with [Y - X = n - m].
(1) {{ X = m /\ Y = n }} ->> (a - OK)
(2) {{ Y - X = n - m }}
WHILE X <> 0 DO
(3) {{ Y - X = n - m /\ X <> 0 }} ->> (c - OK)
(4) {{ (Y - 1) - (X - 1) = n - m }}
Y ::= Y - 1;;
(5) {{ Y - (X - 1) = n - m }}
X ::= X - 1
(6) {{ Y - X = n - m }}
END
(7) {{ Y - X = n - m /\ X = 0 }} ->> (b - OK)
(8) {{ Y = n - m }}
Success! Conditions (a), (b) and (c) all hold now. (To
verify (c), we need to check that, under the assumption that [X <>
0], we have [Y - X = (Y - 1) - (X - 1)]; this holds for all
natural numbers [X] and [Y].) *)
(* ================================================================= *)
(** ** Exercise: Slow Assignment *)
(** **** Exercise: 2 stars (slow_assignment) *)
(** A roundabout way of assigning a number currently stored in [X] to
the variable [Y] is to start [Y] at [0], then decrement [X] until
it hits [0], incrementing [Y] at each step. Here is a program that
implements this idea:
{{ X = m }}
Y ::= 0;;
WHILE X <> 0 DO
X ::= X - 1;;
Y ::= Y + 1
END
{{ Y = m }}
Write an informal decorated program showing that this procedure
is correct. *)
(* FILL IN HERE *)
(** [] *)
(* ================================================================= *)
(** ** Exercise: Slow Addition *)
(** **** Exercise: 3 stars, optional (add_slowly_decoration) *)
(** The following program adds the variable X into the variable Z
by repeatedly decrementing X and incrementing Z.
WHILE X <> 0 DO
Z ::= Z + 1;;
X ::= X - 1
END
Following the pattern of the [subtract_slowly] example above, pick
a precondition and postcondition that give an appropriate
specification of [add_slowly]; then (informally) decorate the
program accordingly. *)
(* FILL IN HERE *)
(** [] *)
(* ================================================================= *)
(** ** Example: Parity *)
(** Here is a cute little program for computing the parity of the
value initially stored in [X] (due to Daniel Cristofani).
{{ X = m }}
WHILE 2 <= X DO
X ::= X - 2
END
{{ X = parity m }}
The mathematical [parity] function used in the specification is
defined in Coq as follows: *)
Fixpoint parity x :=
match x with
| 0 => 0
| 1 => 1
| S (S x') => parity x'
end.
(** The postcondition does not hold at the beginning of the loop,
since [m = parity m] does not hold for an arbitrary [m], so we
cannot use that as an invariant. To find an invariant that works,
let's think a bit about what this loop does. On each iteration it
decrements [X] by [2], which preserves the parity of [X]. So the
parity of [X] does not change, i.e., it is invariant. The initial
value of [X] is [m], so the parity of [X] is always equal to the
parity of [m]. Using [parity X = parity m] as an invariant we
obtain the following decorated program:
{{ X = m }} ->> (a - OK)
{{ parity X = parity m }}
WHILE 2 <= X DO
{{ parity X = parity m /\ 2 <= X }} ->> (c - OK)
{{ parity (X-2) = parity m }}
X ::= X - 2
{{ parity X = parity m }}
END
{{ parity X = parity m /\ X < 2 }} ->> (b - OK)
{{ X = parity m }}
With this invariant, conditions (a), (b), and (c) are all
satisfied. For verifying (b), we observe that, when [X < 2], we
have [parity X = X] (we can easily see this in the definition of
[parity]). For verifying (c), we observe that, when [2 <= X], we
have [parity X = parity (X-2)]. *)
(** **** Exercise: 3 stars, optional (parity_formal) *)
(** Translate this proof to Coq. Refer to the reduce-to-zero example
for ideas. You may find the following two lemmas useful: *)
Lemma parity_ge_2 : forall x,
2 <= x ->
parity (x - 2) = parity x.
Proof.
induction x; intro. reflexivity.
destruct x. inversion H. inversion H1.
simpl. rewrite <- minus_n_O. reflexivity.
Qed.
Lemma parity_lt_2 : forall x,
~ 2 <= x ->
parity (x) = x.
Proof.
intros. induction x. reflexivity. destruct x. reflexivity.
exfalso. apply H. omega.
Qed.
Theorem parity_correct : forall m,
{{ fun st => st X = m }}
WHILE BLe (ANum 2) (AId X) DO
X ::= AMinus (AId X) (ANum 2)
END
{{ fun st => st X = parity m }}.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ================================================================= *)
(** ** Example: Finding Square Roots *)
(** The following program computes the square root of [X]
by naive iteration:
{{ X=m }}
Z ::= 0;;
WHILE (Z+1)*(Z+1) <= X DO
Z ::= Z+1
END
{{ Z*Z<=m /\ m<(Z+1)*(Z+1) }}
*)
(** As above, we can try to use the postcondition as a candidate
invariant, obtaining the following decorated program:
(1) {{ X=m }} ->> (a - second conjunct of (2) WRONG!)
(2) {{ 0*0 <= m /\ m<1*1 }}
Z ::= 0;;
(3) {{ Z*Z <= m /\ m<(Z+1)*(Z+1) }}
WHILE (Z+1)*(Z+1) <= X DO
(4) {{ Z*Z<=m /\ (Z+1)*(Z+1)<=X }} ->> (c - WRONG!)
(5) {{ (Z+1)*(Z+1)<=m /\ m<(Z+2)*(Z+2) }}
Z ::= Z+1
(6) {{ Z*Z<=m /\ m<(Z+1)*(Z+1) }}
END
(7) {{ Z*Z<=m /\ m<(Z+1)*(Z+1) /\ X<(Z+1)*(Z+1) }} ->> (b - OK)
(8) {{ Z*Z<=m /\ m<(Z+1)*(Z+1) }}
This didn't work very well: conditions (a) and (c) both failed.
Looking at condition (c), we see that the second conjunct of (4)
is almost the same as the first conjunct of (5), except that (4)
mentions [X] while (5) mentions [m]. But note that [X] is never
assigned in this program, so we should always have [X=m], but we
didn't propagate this information from (1) into the loop invariant.
Also, looking at the second conjunct of (8), it seems quite
hopeless as an invariant; fortunately and we don't even need it,
since we can obtain it from the negation of the guard -- the third
conjunct in (7) -- again under the assumption that [X=m].
So we now try [X=m /\ Z*Z <= m] as the loop invariant:
{{ X=m }} ->> (a - OK)
{{ X=m /\ 0*0 <= m }}
Z ::= 0;
{{ X=m /\ Z*Z <= m }}
WHILE (Z+1)*(Z+1) <= X DO
{{ X=m /\ Z*Z<=m /\ (Z+1)*(Z+1)<=X }} ->> (c - OK)
{{ X=m /\ (Z+1)*(Z+1)<=m }}
Z ::= Z+1
{{ X=m /\ Z*Z<=m }}
END
{{ X=m /\ Z*Z<=m /\ X<(Z+1)*(Z+1) }} ->> (b - OK)
{{ Z*Z<=m /\ m<(Z+1)*(Z+1) }}
This works, since conditions (a), (b), and (c) are now all
trivially satisfied.
Very often, even if a variable is used in a loop in a read-only
fashion (i.e., it is referred to by the program or by the
specification and it is not changed by the loop), it is necessary
to add the fact that it doesn't change to the loop invariant. *)
(* ================================================================= *)
(** ** Example: Squaring *)
(** Here is a program that squares [X] by repeated addition:
{{ X = m }}
Y ::= 0;;
Z ::= 0;;
WHILE Y <> X DO
Z ::= Z + X;;
Y ::= Y + 1
END
{{ Z = m*m }}
*)
(** The first thing to note is that the loop reads [X] but doesn't
change its value. As we saw in the previous example, it is a good idea
in such cases to add [X = m] to the invariant. The other thing
that we know is often useful in the invariant is the postcondition,
so let's add that too, leading to the invariant candidate
[Z = m * m /\ X = m].
{{ X = m }} ->> (a - WRONG)
{{ 0 = m*m /\ X = m }}
Y ::= 0;;
{{ 0 = m*m /\ X = m }}
Z ::= 0;;
{{ Z = m*m /\ X = m }}
WHILE Y <> X DO
{{ Z = Y*m /\ X = m /\ Y <> X }} ->> (c - WRONG)
{{ Z+X = m*m /\ X = m }}
Z ::= Z + X;;
{{ Z = m*m /\ X = m }}
Y ::= Y + 1
{{ Z = m*m /\ X = m }}
END
{{ Z = m*m /\ X = m /\ Y = X }} ->> (b - OK)
{{ Z = m*m }}
Conditions (a) and (c) fail because of the [Z = m*m] part. While
[Z] starts at [0] and works itself up to [m*m], we can't expect
[Z] to be [m*m] from the start. If we look at how [Z] progesses
in the loop, after the 1st iteration [Z = m], after the 2nd
iteration [Z = 2*m], and at the end [Z = m*m]. Since the variable
[Y] tracks how many times we go through the loop, this leads us to
derive a new invariant candidate: [Z = Y*m /\ X = m].
{{ X = m }} ->> (a - OK)
{{ 0 = 0*m /\ X = m }}
Y ::= 0;;
{{ 0 = Y*m /\ X = m }}
Z ::= 0;;
{{ Z = Y*m /\ X = m }}
WHILE Y <> X DO
{{ Z = Y*m /\ X = m /\ Y <> X }} ->> (c - OK)
{{ Z+X = (Y+1)*m /\ X = m }}
Z ::= Z + X;
{{ Z = (Y+1)*m /\ X = m }}
Y ::= Y + 1
{{ Z = Y*m /\ X = m }}
END
{{ Z = Y*m /\ X = m /\ Y = X }} ->> (b - OK)
{{ Z = m*m }}
This new invariant makes the proof go through: all three
conditions are easy to check.
It is worth comparing the postcondition [Z = m*m] and the [Z =
Y*m] conjunct of the invariant. It is often the case that one has
to replace auxiliary variabes (parameters) with variables -- or
with expressions involving both variables and parameters, like
[m - Y] -- when going from postconditions to invariants. *)
(* ================================================================= *)
(** ** Exercise: Factorial *)
(** **** Exercise: 3 stars (factorial) *)
(** Recall that [n!] denotes the factorial of [n] (i.e., [n! =
1*2*...*n]). Here is an Imp program that calculates the factorial
of the number initially stored in the variable [X] and puts it in
the variable [Y]:
{{ X = m }}
Y ::= 1 ;;
WHILE X <> 0
DO
Y ::= Y * X ;;
X ::= X - 1
END
{{ Y = m! }}
Fill in the blanks in following decorated program:
{{ X = m }} ->>
{{ }}
Y ::= 1;;
{{ }}
WHILE X <> 0
DO {{ }} ->>
{{ }}
Y ::= Y * X;;
{{ }}
X ::= X - 1
{{ }}
END
{{ }} ->>
{{ Y = m! }}
*)
(** [] *)
(* ================================================================= *)
(** ** Exercise: Min *)
(** **** Exercise: 3 stars (Min_Hoare) *)
(** Fill in valid decorations for the following program.
For the [=>] steps in your annotations, you may rely (silently)
on the following facts about min
Lemma lemma1 : forall x y,
(x=0 \/ y=0) -> min x y = 0.
Lemma lemma2 : forall x y,
min (x-1) (y-1) = (min x y) - 1.
plus standard high-school algebra, as always.
{{ True }} ->>
{{ }}
X ::= a;;
{{ }}
Y ::= b;;
{{ }}
Z ::= 0;;
{{ }}
WHILE (X <> 0 /\ Y <> 0) DO
{{ }} ->>
{{ }}
X := X - 1;;
{{ }}
Y := Y - 1;;
{{ }}
Z := Z + 1
{{ }}
END
{{ }} ->>
{{ Z = min a b }}
*)
(** [] *)
(** **** Exercise: 3 stars (two_loops) *)
(** Here is a very inefficient way of adding 3 numbers:
X ::= 0;;
Y ::= 0;;
Z ::= c;;
WHILE X <> a DO
X ::= X + 1;;
Z ::= Z + 1
END;;
WHILE Y <> b DO
Y ::= Y + 1;;
Z ::= Z + 1
END
Show that it does what it should by filling in the blanks in the
following decorated program.
{{ True }} ->>
{{ }}
X ::= 0;;
{{ }}
Y ::= 0;;
{{ }}
Z ::= c;;
{{ }}
WHILE X <> a DO
{{ }} ->>
{{ }}
X ::= X + 1;;
{{ }}
Z ::= Z + 1
{{ }}
END;;
{{ }} ->>
{{ }}
WHILE Y <> b DO
{{ }} ->>
{{ }}
Y ::= Y + 1;;
{{ }}
Z ::= Z + 1
{{ }}
END
{{ }} ->>
{{ Z = a + b + c }}
*)
(** [] *)
(* ================================================================= *)
(** ** Exercise: Power Series *)
(** **** Exercise: 4 stars, optional (dpow2_down) *)
(** Here is a program that computes the series:
[1 + 2 + 2^2 + ... + 2^m = 2^(m+1) - 1]
X ::= 0;;
Y ::= 1;;
Z ::= 1;;
WHILE X <> m DO
Z ::= 2 * Z;;
Y ::= Y + Z;;
X ::= X + 1
END
Write a decorated program for this. *)
(* FILL IN HERE *)
(* ################################################################# *)
(** * Weakest Preconditions (Optional) *)
(** Some Hoare triples are more interesting than others.
For example,
{{ False }} X ::= Y + 1 {{ X <= 5 }}
is _not_ very interesting: although it is perfectly valid, it
tells us nothing useful. Since the precondition isn't satisfied
by any state, it doesn't describe any situations where we can use
the command [X ::= Y + 1] to achieve the postcondition [X <= 5].
By contrast,
{{ Y <= 4 /\ Z = 0 }} X ::= Y + 1 {{ X <= 5 }}
is useful: it tells us that, if we can somehow create a situation
in which we know that [Y <= 4 /\ Z = 0], then running this command
will produce a state satisfying the postcondition. However, this
triple is still not as useful as it could be, because the [Z = 0]
clause in the precondition actually has nothing to do with the
postcondition [X <= 5]. The _most_ useful triple (for this
command and postcondition) is this one:
{{ Y <= 4 }} X ::= Y + 1 {{ X <= 5 }}
In other words, [Y <= 4] is the _weakest_ valid precondition of
the command [X ::= Y + 1] for the postcondition [X <= 5]. *)
(** In general, we say that "[P] is the weakest precondition of
command [c] for postcondition [Q]" if [{{P}} c {{Q}}] and if,
whenever [P'] is an assertion such that [{{P'}} c {{Q}}], it is
the case that [P' st] implies [P st] for all states [st]. *)
Definition is_wp P c Q :=
{{P}} c {{Q}} /\
forall P', {{P'}} c {{Q}} -> (P' ->> P).
(** That is, [P] is the weakest precondition of [c] for [Q]
if (a) [P] _is_ a precondition for [Q] and [c], and (b) [P] is the
_weakest_ (easiest to satisfy) assertion that guarantees that
[Q] will hold after executing [c]. *)
(** **** Exercise: 1 star, optional (wp) *)
(** What are the weakest preconditions of the following commands
for the following postconditions?
1) {{ ? }} SKIP {{ X = 5 }}
2) {{ ? }} X ::= Y + Z {{ X = 5 }}
3) {{ ? }} X ::= Y {{ X = Y }}
4) {{ ? }}
IFB X == 0 THEN Y ::= Z + 1 ELSE Y ::= W + 2 FI
{{ Y = 5 }}
5) {{ ? }}
X ::= 5
{{ X = 0 }}
6) {{ ? }}
WHILE True DO X ::= 0 END
{{ X = 0 }}
*)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars, advanced, optional (is_wp_formal) *)
(** Prove formally, using the definition of [hoare_triple], that [Y <= 4]
is indeed the weakest precondition of [X ::= Y + 1] with respect to
postcondition [X <= 5]. *)
Theorem is_wp_example :
is_wp (fun st => st Y <= 4)
(X ::= APlus (AId Y) (ANum 1)) (fun st => st X <= 5).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, advanced, optional (hoare_asgn_weakest) *)
(** Show that the precondition in the rule [hoare_asgn] is in fact the
weakest precondition. *)
Theorem hoare_asgn_weakest : forall Q X a,
is_wp (Q [X |-> a]) (X ::= a) Q.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, advanced, optional (hoare_havoc_weakest) *)
(** Show that your [havoc_pre] rule from the [himp_hoare] exercise
in the [Hoare] chapter returns the weakest precondition. *)
Module Himp2.
Import Himp.
Lemma hoare_havoc_weakest : forall (P Q : Assertion) (X : id),
{{ P }} HAVOC X {{ Q }} ->
P ->> havoc_pre X Q.
Proof.
(* FILL IN HERE *) Admitted.
End Himp2.
(** [] *)
(* ################################################################# *)
(** * Formal Decorated Programs (Optional) *)
(** Our informal conventions for decorated programs amount to a
way of displaying Hoare triples, in which commands are annotated
with enough embedded assertions that checking the validity of a
triple is reduced to simple logical and algebraic calculations
showing that some assertions imply others. In this section, we
show that this informal presentation style can actually be made
completely formal and indeed that checking the validity of
decorated programs can mostly be automated. *)
(* ================================================================= *)
(** ** Syntax *)
(** The first thing we need to do is to formalize a variant of the
syntax of commands with embedded assertions. We call the new
commands _decorated commands_, or [dcom]s. *)
Inductive dcom : Type :=
| DCSkip : Assertion -> dcom
| DCSeq : dcom -> dcom -> dcom
| DCAsgn : id -> aexp -> Assertion -> dcom
| DCIf : bexp -> Assertion -> dcom -> Assertion -> dcom
-> Assertion-> dcom
| DCWhile : bexp -> Assertion -> dcom -> Assertion -> dcom
| DCPre : Assertion -> dcom -> dcom
| DCPost : dcom -> Assertion -> dcom.
Notation "'SKIP' {{ P }}"
:= (DCSkip P)
(at level 10) : dcom_scope.
Notation "l '::=' a {{ P }}"
:= (DCAsgn l a P)
(at level 60, a at next level) : dcom_scope.
Notation "'WHILE' b 'DO' {{ Pbody }} d 'END' {{ Ppost }}"
:= (DCWhile b Pbody d Ppost)
(at level 80, right associativity) : dcom_scope.
Notation "'IFB' b 'THEN' {{ P }} d 'ELSE' {{ P' }} d' 'FI' {{ Q }}"
:= (DCIf b P d P' d' Q)
(at level 80, right associativity) : dcom_scope.
Notation "'->>' {{ P }} d"
:= (DCPre P d)
(at level 90, right associativity) : dcom_scope.
Notation "{{ P }} d"
:= (DCPre P d)
(at level 90) : dcom_scope.
Notation "d '->>' {{ P }}"
:= (DCPost d P)
(at level 80, right associativity) : dcom_scope.
Notation " d ;; d' "
:= (DCSeq d d')
(at level 80, right associativity) : dcom_scope.
Delimit Scope dcom_scope with dcom.
(** To avoid clashing with the existing [Notation] definitions
for ordinary [com]mands, we introduce these notations in a special
scope called [dcom_scope], and we wrap examples with the
declaration [% dcom] to signal that we want the notations to be
interpreted in this scope.
Careful readers will note that we've defined two notations for the
[DCPre] constructor, one with and one without a [->>]. The
"without" version is intended to be used to supply the initial
precondition at the very top of the program. *)
Example dec_while : dcom := (
{{ fun st => True }}
WHILE (BNot (BEq (AId X) (ANum 0)))
DO
{{ fun st => True /\ st X <> 0}}
X ::= (AMinus (AId X) (ANum 1))
{{ fun _ => True }}
END
{{ fun st => True /\ st X = 0}} ->>
{{ fun st => st X = 0 }}
) % dcom.
(** It is easy to go from a [dcom] to a [com] by erasing all
annotations. *)
Fixpoint extract (d:dcom) : com :=
match d with
| DCSkip _ => SKIP
| DCSeq d1 d2 => (extract d1 ;; extract d2)
| DCAsgn X a _ => X ::= a
| DCIf b _ d1 _ d2 _ => IFB b THEN extract d1 ELSE extract d2 FI
| DCWhile b _ d _ => WHILE b DO extract d END
| DCPre _ d => extract d
| DCPost d _ => extract d
end.
(** The choice of exactly where to put assertions in the definition of
[dcom] is a bit subtle. The simplest thing to do would be to
annotate every [dcom] with a precondition and postcondition. But
this would result in very verbose programs with a lot of repeated
annotations: for example, a program like [SKIP;SKIP] would have to
be annotated as
{{P}} ({{P}} SKIP {{P}}) ;; ({{P}} SKIP {{P}}) {{P}},
with pre- and post-conditions on each [SKIP], plus identical pre-
and post-conditions on the semicolon!
Instead, the rule we've followed is this:
- The _post_-condition expected by each [dcom] [d] is embedded
in [d].
- The _pre_-condition is supplied by the context. *)
(** In other words, the invariant of the representation is that a
[dcom] [d] together with a precondition [P] determines a Hoare
triple [{{P}} (extract d) {{post d}}], where [post] is defined as
follows: *)
Fixpoint post (d:dcom) : Assertion :=
match d with
| DCSkip P => P
| DCSeq d1 d2 => post d2
| DCAsgn X a Q => Q
| DCIf _ _ d1 _ d2 Q => Q
| DCWhile b Pbody c Ppost => Ppost
| DCPre _ d => post d
| DCPost c Q => Q
end.
(** Similarly, we can extract the "initial precondition" from a
decorated program. *)
Fixpoint pre (d:dcom) : Assertion :=
match d with
| DCSkip P => fun st => True
| DCSeq c1 c2 => pre c1
| DCAsgn X a Q => fun st => True
| DCIf _ _ t _ e _ => fun st => True
| DCWhile b Pbody c Ppost => fun st => True
| DCPre P c => P
| DCPost c Q => pre c
end.
(** This function is not doing anything sophisticated like calculating
a weakest precondition; it just recursively searches for an
explicit annotation at the very beginning of the program,
returning default answers for programs that lack an explicit
precondition (like a bare assignment or [SKIP]). *)
(** Using [pre] and [post], and assuming that we adopt the convention
of always supplying an explicit precondition annotation at the
very beginning of our decorated programs, we can express what it
means for a decorated program to be correct as follows: *)
Definition dec_correct (d:dcom) :=
{{pre d}} (extract d) {{post d}}.
(** To check whether this Hoare triple is _valid_, we need a way to
extract the "proof obligations" from a decorated program. These
obligations are often called _verification conditions_, because
they are the facts that must be verified to see that the
decorations are logically consistent and thus add up to a complete
proof of correctness. *)
(* ================================================================= *)
(** ** Extracting Verification Conditions *)
(** The function [verification_conditions] takes a [dcom] [d] together
with a precondition [P] and returns a _proposition_ that, if it
can be proved, implies that the triple [{{P}} (extract d) {{post d}}]
is valid. *)
(** It does this by walking over [d] and generating a big
conjunction including all the "local checks" that we listed when
we described the informal rules for decorated programs. (Strictly
speaking, we need to massage the informal rules a little bit to
add some uses of the rule of consequence, but the correspondence
should be clear.) *)
Fixpoint verification_conditions (P : Assertion) (d:dcom)
: Prop :=
match d with
| DCSkip Q =>
(P ->> Q)
| DCSeq d1 d2 =>
verification_conditions P d1
/\ verification_conditions (post d1) d2
| DCAsgn X a Q =>
(P ->> Q [X |-> a])
| DCIf b P1 d1 P2 d2 Q =>
((fun st => P st /\ bassn b st) ->> P1)
/\ ((fun st => P st /\ ~ (bassn b st)) ->> P2)
/\ (Q <<->> post d1) /\ (Q <<->> post d2)
/\ verification_conditions P1 d1
/\ verification_conditions P2 d2
| DCWhile b Pbody d Ppost =>
(* post d is the loop invariant and the initial precondition *)
(P ->> post d)
/\ (Pbody <<->> (fun st => post d st /\ bassn b st))
/\ (Ppost <<->> (fun st => post d st /\ ~(bassn b st)))
/\ verification_conditions Pbody d
| DCPre P' d =>
(P ->> P') /\ verification_conditions P' d
| DCPost d Q =>
verification_conditions P d /\ (post d ->> Q)
end.
(** And now the key theorem, stating that [verification_conditions]
does its job correctly. Not surprisingly, we need to use each of
the Hoare Logic rules at some point in the proof. *)
Theorem verification_correct : forall d P,
verification_conditions P d -> {{P}} (extract d) {{post d}}.
Proof.
induction d; intros P H; simpl in *.
- (* Skip *)
eapply hoare_consequence_pre.
apply hoare_skip.
assumption.
- (* Seq *)
inversion H as [H1 H2]. clear H.
eapply hoare_seq.
apply IHd2. apply H2.
apply IHd1. apply H1.
- (* Asgn *)
eapply hoare_consequence_pre.
apply hoare_asgn.
assumption.
- (* If *)
inversion H as [HPre1 [HPre2 [[Hd11 Hd12]
[[Hd21 Hd22] [HThen HElse]]]]].
clear H.
apply IHd1 in HThen. clear IHd1.
apply IHd2 in HElse. clear IHd2.
apply hoare_if.
eapply hoare_consequence_pre; eauto.
eapply hoare_consequence_post; eauto.
eapply hoare_consequence_pre; eauto.
eapply hoare_consequence_post; eauto.
- (* While *)
inversion H as [Hpre [[Hbody1 Hbody2] [[Hpost1 Hpost2] Hd]]];
subst; clear H.
eapply hoare_consequence_pre; eauto.
eapply hoare_consequence_post; eauto.
apply hoare_while.
eapply hoare_consequence_pre; eauto.
- (* Pre *)
inversion H as [HP Hd]; clear H.
eapply hoare_consequence_pre. apply IHd. apply Hd. assumption.
- (* Post *)
inversion H as [Hd HQ]; clear H.
eapply hoare_consequence_post. apply IHd. apply Hd. assumption.
Qed.
(** (If you expand the proof, you'll see that it uses an
unfamiliar idiom: [simpl in *]. We have used [...in...] variants
of several tactics before, to apply them to values in the context
rather than the goal. The syntax [tactic in *] extends this idea,
applying [tactic] in the goal and every hypothesis in the
context.) *)
(* ================================================================= *)
(** ** Automation *)
(** The propositions generated by [verification_conditions] are fairly
big, and they contain many conjuncts that are essentially trivial. *)
Eval simpl in (verification_conditions (fun st => True) dec_while).
(**
==>
(((fun _ : state => True) ->> (fun _ : state => True)) /\
((fun _ : state => True) ->> (fun _ : state => True)) /\
(fun st : state => True /\ bassn (BNot (BEq (AId X) (ANum 0))) st) =
(fun st : state => True /\ bassn (BNot (BEq (AId X) (ANum 0))) st) /\
(fun st : state => True /\ ~ bassn (BNot (BEq (AId X) (ANum 0))) st) =
(fun st : state => True /\ ~ bassn (BNot (BEq (AId X) (ANum 0))) st) /\
(fun st : state => True /\ bassn (BNot (BEq (AId X) (ANum 0))) st) ->>
(fun _ : state => True) [X |-> AMinus (AId X) (ANum 1)]) /\
(fun st : state => True /\ ~ bassn (BNot (BEq (AId X) (ANum 0))) st) ->>
(fun st : state => st X = 0)
*)
(** In principle, we could work with such propositions using just the
tactics we have so far, but we can make things much smoother with
a bit of automation. We first define a custom [verify] tactic
that uses [split] repeatedly to turn all the conjunctions into
separate subgoals and then uses [omega] and [eauto] (a handy
general-purpose automation tactic that we'll discuss in detail
later) to deal with as many of them as possible. *)
Tactic Notation "verify" :=
apply verification_correct;
repeat split;
simpl; unfold assert_implies;
unfold bassn in *; unfold beval in *; unfold aeval in *;
unfold assn_sub; intros;
repeat rewrite t_update_eq;
repeat (rewrite t_update_neq; [| (intro X; inversion X)]);
simpl in *;
repeat match goal with [H : _ /\ _ |- _] => destruct H end;
repeat rewrite not_true_iff_false in *;
repeat rewrite not_false_iff_true in *;
repeat rewrite negb_true_iff in *;
repeat rewrite negb_false_iff in *;
repeat rewrite beq_nat_true_iff in *;
repeat rewrite beq_nat_false_iff in *;
repeat rewrite leb_iff in *;
repeat rewrite leb_iff_conv in *;
try subst;
repeat
match goal with
[st : state |- _] =>
match goal with
[H : st _ = _ |- _] => rewrite -> H in *; clear H
| [H : _ = st _ |- _] => rewrite <- H in *; clear H
end
end;
try eauto; try omega.
(** What's left after [verify] does its thing is "just the interesting
parts" of checking that the decorations are correct. For very
simple examples [verify] immediately solves the goal (provided
that the annotations are correct). *)
Theorem dec_while_correct :
dec_correct dec_while.
Proof. verify. Qed.
(** Another example (formalizing a decorated program we've seen
before): *)
Example subtract_slowly_dec (m:nat) (p:nat) : dcom := (
{{ fun st => st X = m /\ st Z = p }} ->>
{{ fun st => st Z - st X = p - m }}
WHILE BNot (BEq (AId X) (ANum 0))
DO {{ fun st => st Z - st X = p - m /\ st X <> 0 }} ->>
{{ fun st => (st Z - 1) - (st X - 1) = p - m }}
Z ::= AMinus (AId Z) (ANum 1)
{{ fun st => st Z - (st X - 1) = p - m }} ;;
X ::= AMinus (AId X) (ANum 1)
{{ fun st => st Z - st X = p - m }}
END
{{ fun st => st Z - st X = p - m /\ st X = 0 }} ->>
{{ fun st => st Z = p - m }}
) % dcom.
Theorem subtract_slowly_dec_correct : forall m p,
dec_correct (subtract_slowly_dec m p).
Proof. intros m p. verify. (* this grinds for a bit! *) Qed.
(** **** Exercise: 3 stars, advanced (slow_assignment_dec) *)
(** In the [slow_assignment] exercise above, we saw a roundabout way
of assigning a number currently stored in [X] to the variable [Y]:
start [Y] at [0], then decrement [X] until it hits [0],
incrementing [Y] at each step. Write a formal version of this
decorated program and prove it correct. *)
Example slow_assignment_dec (m:nat) : dcom :=
(* FILL IN HERE *) admit.
Theorem slow_assignment_dec_correct : forall m,
dec_correct (slow_assignment_dec m).
Proof. (* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars, advanced (factorial_dec) *)
(** Remember the factorial function we worked with before: *)
Fixpoint real_fact (n:nat) : nat :=
match n with
| O => 1
| S n' => n * (real_fact n')
end.
(** Following the pattern of [subtract_slowly_dec], write a decorated
program [factorial_dec] that implements the factorial function and
prove it correct as [factorial_dec_correct]. *)
(* FILL IN HERE *)
(** [] *)
(* ================================================================= *)
(** ** Examples *)
(** In this section, we use the automation developed above to verify
formal decorated programs corresponding to most of the informal
ones we have seen. *)
(* ----------------------------------------------------------------- *)
(** *** Swapping Using Addition and Subtraction *)
Definition swap : com :=
X ::= APlus (AId X) (AId Y);;
Y ::= AMinus (AId X) (AId Y);;
X ::= AMinus (AId X) (AId Y).
Definition swap_dec m n : dcom :=
({{ fun st => st X = m /\ st Y = n}} ->>
{{ fun st => (st X + st Y) - ((st X + st Y) - st Y) = n
/\ (st X + st Y) - st Y = m }}
X ::= APlus (AId X) (AId Y)
{{ fun st => st X - (st X - st Y) = n /\ st X - st Y = m }};;
Y ::= AMinus (AId X) (AId Y)
{{ fun st => st X - st Y = n /\ st Y = m }};;
X ::= AMinus (AId X) (AId Y)
{{ fun st => st X = n /\ st Y = m}})%dcom.
Theorem swap_correct : forall m n,
dec_correct (swap_dec m n).
Proof. intros; verify. Qed.
(* ----------------------------------------------------------------- *)
(** *** Simple Conditionals *)
Definition if_minus_plus_com :=
IFB (BLe (AId X) (AId Y))
THEN (Z ::= AMinus (AId Y) (AId X))
ELSE (Y ::= APlus (AId X) (AId Z))
FI.
Definition if_minus_plus_dec :=
({{fun st => True}}
IFB (BLe (AId X) (AId Y)) THEN
{{ fun st => True /\ st X <= st Y }} ->>
{{ fun st => st Y = st X + (st Y - st X) }}
Z ::= AMinus (AId Y) (AId X)
{{ fun st => st Y = st X + st Z }}
ELSE
{{ fun st => True /\ ~(st X <= st Y) }} ->>
{{ fun st => st X + st Z = st X + st Z }}
Y ::= APlus (AId X) (AId Z)
{{ fun st => st Y = st X + st Z }}
FI
{{fun st => st Y = st X + st Z}})%dcom.
Theorem if_minus_plus_correct :
dec_correct if_minus_plus_dec.
Proof. intros; verify. Qed.
Definition if_minus_dec :=
( {{fun st => True}}
IFB (BLe (AId X) (AId Y)) THEN
{{fun st => True /\ st X <= st Y }} ->>
{{fun st => (st Y - st X) + st X = st Y
\/ (st Y - st X) + st Y = st X}}
Z ::= AMinus (AId Y) (AId X)
{{fun st => st Z + st X = st Y \/ st Z + st Y = st X}}
ELSE
{{fun st => True /\ ~(st X <= st Y) }} ->>
{{fun st => (st X - st Y) + st X = st Y
\/ (st X - st Y) + st Y = st X}}
Z ::= AMinus (AId X) (AId Y)
{{fun st => st Z + st X = st Y \/ st Z + st Y = st X}}
FI
{{fun st => st Z + st X = st Y \/ st Z + st Y = st X}})%dcom.
Theorem if_minus_correct :
dec_correct if_minus_dec.
Proof. verify. Qed.
(* ----------------------------------------------------------------- *)
(** *** Division *)
Definition div_mod_dec (a b : nat) : dcom := (
{{ fun st => True }} ->>
{{ fun st => b * 0 + a = a }}
X ::= ANum a
{{ fun st => b * 0 + st X = a }};;
Y ::= ANum 0
{{ fun st => b * st Y + st X = a }};;
WHILE (BLe (ANum b) (AId X)) DO
{{ fun st => b * st Y + st X = a /\ b <= st X }} ->>
{{ fun st => b * (st Y + 1) + (st X - b) = a }}
X ::= AMinus (AId X) (ANum b)
{{ fun st => b * (st Y + 1) + st X = a }};;
Y ::= APlus (AId Y) (ANum 1)
{{ fun st => b * st Y + st X = a }}
END
{{ fun st => b * st Y + st X = a /\ ~(b <= st X) }} ->>
{{ fun st => b * st Y + st X = a /\ (st X < b) }}
)%dcom.
Theorem div_mod_dec_correct : forall a b,
dec_correct (div_mod_dec a b).
Proof. intros a b. verify.
rewrite mult_plus_distr_l. omega.
Qed.
(* ----------------------------------------------------------------- *)
(** *** Parity *)
Definition find_parity : com :=
WHILE (BLe (ANum 2) (AId X)) DO
X ::= AMinus (AId X) (ANum 2)
END.
(** There are actually several ways to phrase the loop invariant for
this program. Here is one natural one, which leads to a rather
long proof: *)
Inductive ev : nat -> Prop :=
| ev_0 : ev O
| ev_SS : forall n:nat, ev n -> ev (S (S n)).
Definition find_parity_dec m : dcom :=
({{ fun st => st X = m}} ->>
{{ fun st => st X <= m /\ ev (m - st X) }}
WHILE (BLe (ANum 2) (AId X)) DO
{{ fun st => (st X <= m /\ ev (m - st X)) /\ 2 <= st X }} ->>
{{ fun st => st X - 2 <= m /\ (ev (m - (st X - 2))) }}
X ::= AMinus (AId X) (ANum 2)
{{ fun st => st X <= m /\ ev (m - st X) }}
END
{{ fun st => (st X <= m /\ ev (m - st X)) /\ st X < 2 }} ->>
{{ fun st => st X=0 <-> ev m }})%dcom.
Lemma l1 : forall m n p,
p <= n ->
n <= m ->
m - (n - p) = m - n + p.
Proof. intros. omega. Qed.
Lemma l2 : forall m,
ev m ->
ev (m + 2).
Proof. intros. rewrite plus_comm. simpl. constructor. assumption. Qed.
Lemma l3' : forall m,
ev m ->
~ev (S m).
Proof. induction m; intros H1 H2. inversion H2. apply IHm.
inversion H2; subst; assumption. assumption. Qed.
Lemma l3 : forall m,
1 <= m ->
ev m ->
ev (m - 1) ->
False.
Proof. intros. apply l2 in H1.
assert (G : m - 1 + 2 = S m). clear H0 H1. omega.
rewrite G in H1. apply l3' in H0. apply H0. assumption. Qed.
Theorem find_parity_correct : forall m,
dec_correct (find_parity_dec m).
Proof.
intro m. verify;
(* simplification too aggressive ... reverting a bit *)
fold (leb 2 (st X)) in *;
try rewrite leb_iff in *;
try rewrite leb_iff_conv in *; eauto; try omega.
- (* invariant holds initially *)
rewrite minus_diag. constructor.
- (* invariant preserved *)
rewrite l1; try assumption.
apply l2; assumption.
- (* invariant strong enough to imply conclusion
(-> direction) *)
rewrite <- minus_n_O in H2. assumption.
- (* invariant strong enough to imply conclusion
(<- direction) *)
destruct (st X) as [| [| n]]. (* by H1 X can only be 0 or 1 *)
+ (* st X = 0 *)
reflexivity.
+ (* st X = 1 *)
apply l3 in H; try assumption. inversion H.
+ (* st X = 2 *)
clear H0 H2. (* omega confused otherwise *)
omega.
Qed.
(** Here is a more intuitive way of writing the invariant: *)
Definition find_parity_dec' m : dcom :=
({{ fun st => st X = m}} ->>
{{ fun st => ev (st X) <-> ev m }}
WHILE (BLe (ANum 2) (AId X)) DO
{{ fun st => (ev (st X) <-> ev m) /\ 2 <= st X }} ->>
{{ fun st => (ev (st X - 2) <-> ev m) }}
X ::= AMinus (AId X) (ANum 2)
{{ fun st => (ev (st X) <-> ev m) }}
END
{{ fun st => (ev (st X) <-> ev m) /\ ~(2 <= st X) }} ->>
{{ fun st => st X=0 <-> ev m }})%dcom.
Lemma l4 : forall m,
2 <= m ->
(ev (m - 2) <-> ev m).
Proof.
induction m; intros. split; intro; constructor.
destruct m. inversion H. inversion H1. simpl in *.
rewrite <- minus_n_O in *. split; intro.
constructor. assumption.
inversion H0. assumption.
Qed.
Theorem find_parity_correct' : forall m,
dec_correct (find_parity_dec' m).
Proof.
intros m. verify;
(* simplification too aggressive ... reverting a bit *)
fold (leb 2 (st X)) in *;
try rewrite leb_iff in *;
try rewrite leb_iff_conv in *; intuition; eauto; try omega.
- (* invariant preserved (part 1) *)
rewrite l4 in H0; eauto.
- (* invariant preserved (part 2) *)
rewrite l4; eauto.
- (* invariant strong enough to imply conclusion
(-> direction) *)
apply H0. constructor.
- (* invariant strong enough to imply conclusion
(<- direction) *)
destruct (st X) as [| [| n]]. (* by H1 X can only be 0 or 1 *)
+ (* st X = 0 *)
reflexivity.
+ (* st X = 1 *)
inversion H.
+ (* st X = 2 *)
clear H0 H H3. (* omega confused otherwise *)
omega.
Qed.
(** Here is the simplest invariant we've found for this program: *)
Definition parity_dec m : dcom :=
({{ fun st => st X = m}} ->>
{{ fun st => parity (st X) = parity m }}
WHILE (BLe (ANum 2) (AId X)) DO
{{ fun st => parity (st X) = parity m /\ 2 <= st X }} ->>
{{ fun st => parity (st X - 2) = parity m }}
X ::= AMinus (AId X) (ANum 2)
{{ fun st => parity (st X) = parity m }}
END
{{ fun st => parity (st X) = parity m /\ ~(2 <= st X) }} ->>
{{ fun st => st X = parity m }})%dcom.
Theorem parity_dec_correct : forall m,
dec_correct (parity_dec m).
Proof.
intros. verify;
(* simplification too aggressive ... reverting a bit *)
fold (leb 2 (st X)) in *;
try rewrite leb_iff in *;
try rewrite leb_iff_conv in *; eauto; try omega.
- (* invariant preserved *)
rewrite <- H. apply parity_ge_2. assumption.
- (* invariant strong enough *)
rewrite <- H. symmetry. apply parity_lt_2. assumption.
Qed.
(* ----------------------------------------------------------------- *)
(** *** Square Roots *)
Definition sqrt_dec m : dcom := (
{{ fun st => st X = m }} ->>
{{ fun st => st X = m /\ 0*0 <= m }}
Z ::= ANum 0
{{ fun st => st X = m /\ st Z*st Z <= m }};;
WHILE BLe (AMult (APlus (AId Z) (ANum 1))
(APlus (AId Z) (ANum 1)))
(AId X) DO
{{ fun st => (st X = m /\ st Z*st Z<=m)
/\ (st Z + 1)*(st Z + 1) <= st X }} ->>
{{ fun st => st X = m /\ (st Z+1)*(st Z+1)<=m }}
Z ::= APlus (AId Z) (ANum 1)
{{ fun st => st X = m /\ st Z*st Z<=m }}
END
{{ fun st => (st X = m /\ st Z*st Z<=m)
/\ ~((st Z + 1)*(st Z + 1) <= st X) }} ->>
{{ fun st => st Z*st Z<=m /\ m<(st Z+1)*(st Z+1) }})%dcom.
Theorem sqrt_correct : forall m,
dec_correct (sqrt_dec m).
Proof. intro m. verify. Qed.
(* ----------------------------------------------------------------- *)
(** *** Squaring *)
(** Again, there are several ways of annotating the squaring program.
The simplest variant we've found, [square_simpler_dec], is given
last. *)
Definition square_dec (m : nat) : dcom := (
{{ fun st => st X = m }}
Y ::= AId X
{{ fun st => st X = m /\ st Y = m }};;
Z ::= ANum 0
{{ fun st => st X = m /\ st Y = m /\ st Z = 0}};;
{{ fun st => st Z + st X * st Y = m * m }}
WHILE BNot (BEq (AId Y) (ANum 0)) DO
{{ fun st => st Z + st X * st Y = m * m /\ st Y <> 0 }} ->>
{{ fun st => (st Z + st X) + st X * (st Y - 1) = m * m }}
Z ::= APlus (AId Z) (AId X)
{{ fun st => st Z + st X * (st Y - 1) = m * m }};;
Y ::= AMinus (AId Y) (ANum 1)
{{ fun st => st Z + st X * st Y = m * m }}
END
{{ fun st => st Z + st X * st Y = m * m /\ st Y = 0 }} ->>
{{ fun st => st Z = m * m }}
)%dcom.
Theorem square_dec_correct : forall m,
dec_correct (square_dec m).
Proof.
intro n. verify.
- (* invariant preserved *)
destruct (st Y) as [| y']. apply False_ind. apply H0.
reflexivity.
simpl. rewrite <- minus_n_O.
assert (G : forall n m, n * S m = n + n * m). {
clear. intros. induction n. reflexivity. simpl.
rewrite IHn. omega. }
rewrite <- H. rewrite G. rewrite plus_assoc. reflexivity.
Qed.
Definition square_dec' (n : nat) : dcom := (
{{ fun st => True }}
X ::= ANum n
{{ fun st => st X = n }};;
Y ::= AId X
{{ fun st => st X = n /\ st Y = n }};;
Z ::= ANum 0
{{ fun st => st X = n /\ st Y = n /\ st Z = 0 }};;
{{ fun st => st Z = st X * (st X - st Y)
/\ st X = n /\ st Y <= st X }}
WHILE BNot (BEq (AId Y) (ANum 0)) DO
{{ fun st => (st Z = st X * (st X - st Y)
/\ st X = n /\ st Y <= st X)
/\ st Y <> 0 }}
Z ::= APlus (AId Z) (AId X)
{{ fun st => st Z = st X * (st X - (st Y - 1))
/\ st X = n /\ st Y <= st X }};;
Y ::= AMinus (AId Y) (ANum 1)
{{ fun st => st Z = st X * (st X - st Y)
/\ st X = n /\ st Y <= st X }}
END
{{ fun st => (st Z = st X * (st X - st Y)
/\ st X = n /\ st Y <= st X)
/\ st Y = 0 }} ->>
{{ fun st => st Z = n * n }}
)%dcom.
Theorem square_dec'_correct : forall n,
dec_correct (square_dec' n).
Proof.
intro n. verify.
- (* invariant holds initially *)
rewrite minus_diag. omega.
- (* invariant preserved *) subst.
rewrite mult_minus_distr_l.
repeat rewrite mult_minus_distr_l. rewrite mult_1_r.
assert (G : forall n m p, m <= n -> p <= m -> n - (m - p) = n - m + p).
intros. omega.
rewrite G. reflexivity. apply mult_le_compat_l. assumption.
destruct (st Y). apply False_ind. apply H0. reflexivity.
clear. rewrite mult_succ_r. rewrite plus_comm.
apply le_plus_l.
- (* invarint + negation of guard imply desired postcondition *)
rewrite <- minus_n_O. reflexivity.
Qed.
Definition square_simpler_dec (m : nat) : dcom := (
{{ fun st => st X = m }} ->>
{{ fun st => 0 = 0*m /\ st X = m }}
Y ::= ANum 0
{{ fun st => 0 = (st Y)*m /\ st X = m }};;
Z ::= ANum 0
{{ fun st => st Z = (st Y)*m /\ st X = m }};;
{{ fun st => st Z = (st Y)*m /\ st X = m }}
WHILE BNot (BEq (AId Y) (AId X)) DO
{{ fun st => (st Z = (st Y)*m /\ st X = m)
/\ st Y <> st X }} ->>
{{ fun st => st Z + st X = ((st Y) + 1)*m /\ st X = m }}
Z ::= APlus (AId Z) (AId X)
{{ fun st => st Z = ((st Y) + 1)*m /\ st X = m }};;
Y ::= APlus (AId Y) (ANum 1)
{{ fun st => st Z = (st Y)*m /\ st X = m }}
END
{{ fun st => (st Z = (st Y)*m /\ st X = m) /\ st Y = st X }} ->>
{{ fun st => st Z = m*m }}
)%dcom.
Theorem square_simpler_dec_correct : forall m,
dec_correct (square_simpler_dec m).
Proof.
intro m. verify.
rewrite mult_plus_distr_r. simpl. rewrite <- plus_n_O.
reflexivity.
Qed.
(* ----------------------------------------------------------------- *)
(** *** Two loops *)
Definition two_loops_dec (a b c : nat) :=
( {{ fun st => True }} ->>
{{ fun st => c = 0 + c /\ 0 = 0 }}
X ::= ANum 0
{{ fun st => c = st X + c /\ 0 = 0 }};;
Y ::= ANum 0
{{ fun st => c = st X + c /\ st Y = 0 }};;
Z ::= ANum c
{{ fun st => st Z = st X + c /\ st Y = 0 }};;
WHILE BNot (BEq (AId X) (ANum a)) DO
{{ fun st => (st Z = st X + c /\ st Y = 0) /\ st X <> a }} ->>
{{ fun st => st Z + 1 = st X + 1 + c /\ st Y = 0 }}
X ::= APlus (AId X) (ANum 1)
{{ fun st => st Z + 1 = st X + c /\ st Y = 0 }};;
Z ::= APlus (AId Z) (ANum 1)
{{ fun st => st Z = st X + c /\ st Y = 0 }}
END
{{ fun st => (st Z = st X + c /\ st Y = 0) /\ st X = a }} ->>
{{ fun st => st Z = a + st Y + c }};;
WHILE BNot (BEq (AId Y) (ANum b)) DO
{{ fun st => st Z = a + st Y + c /\ st Y <> b }} ->>
{{ fun st => st Z + 1 = a + st Y + 1 + c }}
Y ::= APlus (AId Y) (ANum 1)
{{ fun st => st Z + 1 = a + st Y + c }};;
Z ::= APlus (AId Z) (ANum 1)
{{ fun st => st Z = a + st Y + c }}
END
{{ fun st => (st Z = a + st Y + c) /\ st Y = b }} ->>
{{ fun st => st Z = a + b + c }}
)%dcom.
Theorem two_loops_correct : forall a b c,
dec_correct (two_loops_dec a b c).
Proof. intros a b c. verify. Qed.
(* ----------------------------------------------------------------- *)
(** *** Power series *)
Fixpoint pow2 n :=
match n with
| 0 => 1
| S n' => 2 * (pow2 n')
end.
Definition dpow2_down n :=
( {{ fun st => True }} ->>
{{ fun st => 1 = (pow2 (0 + 1))-1 /\ 1 = pow2 0 }}
X ::= ANum 0
{{ fun st => 1 = (pow2 (0 + 1))-1 /\ 1 = pow2 (st X) }};;
Y ::= ANum 1
{{ fun st => st Y = (pow2 (st X + 1))-1 /\ 1 = pow2 (st X) }};;
Z ::= ANum 1
{{ fun st => st Y = (pow2 (st X + 1))-1 /\ st Z = pow2 (st X) }};;
WHILE BNot (BEq (AId X) (ANum n)) DO
{{ fun st => (st Y = (pow2 (st X + 1))-1 /\ st Z = pow2 (st X))
/\ st X <> n }} ->>
{{ fun st => st Y + 2 * st Z = (pow2 (st X + 2))-1
/\ 2 * st Z = pow2 (st X + 1) }}
Z ::= AMult (ANum 2) (AId Z)
{{ fun st => st Y + st Z = (pow2 (st X + 2))-1
/\ st Z = pow2 (st X + 1) }};;
Y ::= APlus (AId Y) (AId Z)
{{ fun st => st Y = (pow2 (st X + 2))-1
/\ st Z = pow2 (st X + 1) }};;
X ::= APlus (AId X) (ANum 1)
{{ fun st => st Y = (pow2 (st X + 1))-1
/\ st Z = pow2 (st X) }}
END
{{ fun st => (st Y = (pow2 (st X + 1))-1 /\ st Z = pow2 (st X))
/\ st X = n }} ->>
{{ fun st => st Y = pow2 (n+1) - 1 }}
)%dcom.
Lemma pow2_plus_1 : forall n,
pow2 (n+1) = pow2 n + pow2 n.
Proof. induction n; simpl. reflexivity. omega. Qed.
Lemma pow2_le_1 : forall n, pow2 n >= 1.
Proof. induction n. simpl. constructor. simpl. omega. Qed.
Theorem dpow2_down_correct : forall n,
dec_correct (dpow2_down n).
Proof.
intro m. verify.
- (* 1 *)
rewrite pow2_plus_1. rewrite <- H0. reflexivity.
- (* 2 *)
rewrite <- plus_n_O.
rewrite <- pow2_plus_1. remember (st X) as n.
replace (pow2 (n + 1) - 1 + pow2 (n + 1))
with (pow2 (n + 1) + pow2 (n + 1) - 1) by omega.
rewrite <- pow2_plus_1.
replace (n + 1 + 1) with (n + 2) by omega.
reflexivity.
- (* 3 *)
rewrite <- plus_n_O. rewrite <- pow2_plus_1.
reflexivity.
- (* 4 *)
replace (st X + 1 + 1) with (st X + 2) by omega.
reflexivity.
Qed.
(** $Date: 2016-05-26 16:17:19 -0400 (Thu, 26 May 2016) $ *)
|
`timescale 1ns / 1ps
/*
-- Module Name: DES Sbox 5
-- Description: Sbox 5 del algoritmo DES
-- Dependencies: -- none
-- Parameters: -- none
-- Original Author: Héctor Cabrera
-- Current Author:
-- Notas:
-- History:
-- Creacion 05 de Junio 2015
*/
module des_sbox5
(
// -- inputs --------------------------------------------------------- >>>>>
input wire [0:5] right_xor_key_segment_din,
// -- outputs -------------------------------------------------------- >>>>>
output reg [0:3] sbox_dout
);
always @(*)
case ({right_xor_key_segment_din[0], right_xor_key_segment_din[5]})
2'b00:
case (right_xor_key_segment_din[1:4])
4'd0: sbox_dout = 4'd2;
4'd1: sbox_dout = 4'd12;
4'd2: sbox_dout = 4'd4;
4'd3: sbox_dout = 4'd1;
4'd4: sbox_dout = 4'd7;
4'd5: sbox_dout = 4'd10;
4'd6: sbox_dout = 4'd11;
4'd7: sbox_dout = 4'd6;
4'd8: sbox_dout = 4'd8;
4'd9: sbox_dout = 4'd5;
4'd10: sbox_dout = 4'd3;
4'd11: sbox_dout = 4'd15;
4'd12: sbox_dout = 4'd13;
4'd13: sbox_dout = 4'd0;
4'd14: sbox_dout = 4'd14;
4'd15: sbox_dout = 4'd9;
endcase
2'b01:
case (right_xor_key_segment_din[1:4])
4'd0: sbox_dout = 4'd14;
4'd1: sbox_dout = 4'd11;
4'd2: sbox_dout = 4'd2;
4'd3: sbox_dout = 4'd12;
4'd4: sbox_dout = 4'd4;
4'd5: sbox_dout = 4'd7;
4'd6: sbox_dout = 4'd13;
4'd7: sbox_dout = 4'd1;
4'd8: sbox_dout = 4'd5;
4'd9: sbox_dout = 4'd0;
4'd10: sbox_dout = 4'd15;
4'd11: sbox_dout = 4'd10;
4'd12: sbox_dout = 4'd3;
4'd13: sbox_dout = 4'd9;
4'd14: sbox_dout = 4'd8;
4'd15: sbox_dout = 4'd6;
endcase
2'b10:
case (right_xor_key_segment_din[1:4])
4'd0: sbox_dout = 4'd4;
4'd1: sbox_dout = 4'd2;
4'd2: sbox_dout = 4'd1;
4'd3: sbox_dout = 4'd11;
4'd4: sbox_dout = 4'd10;
4'd5: sbox_dout = 4'd13;
4'd6: sbox_dout = 4'd7;
4'd7: sbox_dout = 4'd8;
4'd8: sbox_dout = 4'd15;
4'd9: sbox_dout = 4'd9;
4'd10: sbox_dout = 4'd12;
4'd11: sbox_dout = 4'd5;
4'd12: sbox_dout = 4'd6;
4'd13: sbox_dout = 4'd3;
4'd14: sbox_dout = 4'd0;
4'd15: sbox_dout = 4'd14;
endcase
2'b11:
case (right_xor_key_segment_din[1:4])
4'd0: sbox_dout = 4'd11;
4'd1: sbox_dout = 4'd8;
4'd2: sbox_dout = 4'd12;
4'd3: sbox_dout = 4'd7;
4'd4: sbox_dout = 4'd1;
4'd5: sbox_dout = 4'd14;
4'd6: sbox_dout = 4'd2;
4'd7: sbox_dout = 4'd13;
4'd8: sbox_dout = 4'd6;
4'd9: sbox_dout = 4'd15;
4'd10: sbox_dout = 4'd0;
4'd11: sbox_dout = 4'd9;
4'd12: sbox_dout = 4'd10;
4'd13: sbox_dout = 4'd4;
4'd14: sbox_dout = 4'd5;
4'd15: sbox_dout = 4'd3;
endcase
endcase // right_xor_key_segment_din[0], right_xor_key_segment_din[5]
endmodule
/* -- Plantilla de Instancia ------------------------------------- >>>>>
des_sbox5 sbox5
(
// -- inputs ------------------------------------------------- >>>>>
.right_xor_key_segment_din (right_xor_key_segment),
// -- outputs ------------------------------------------------ >>>>>
sbox_dout (sbox_dout)
);
*/ |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2BB2A_SYMBOL_V
`define SKY130_FD_SC_MS__O2BB2A_SYMBOL_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o2bb2a (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2BB2A_SYMBOL_V
|
////////////////////////////////////////////////////////////////
// File: new_pipeline_2.v
// Author: B. Brown, T. Dotsikas
// About: Top-level module for experiment.
////////////////////////////////////////////////////////////////
//=======================================================
// Ports generated by Terasic System Builder
//=======================================================
module new_pipeline_2(
//////////// CLOCK //////////
input CLOCK_50,
input CLOCK2_50,
input CLOCK3_50,
//////////// LED //////////
output [8:0] LEDG,
output [17:0] LEDR,
//////////// KEY //////////
input [3:0] KEY,
//////////// SW //////////
input [17:0] SW,
//////////// VGA //////////
output [7:0] VGA_B,
output VGA_BLANK_N,
output VGA_CLK,
output [7:0] VGA_G,
output VGA_HS,
output [7:0] VGA_R,
output VGA_SYNC_N,
output VGA_VS,
//////////// I2C for Tv-Decoder //////////
output I2C_SCLK,
inout I2C_SDAT,
//////////// TV Decoder //////////
input TD_CLK27,
input [7:0] TD_DATA,
input TD_HS,
output TD_RESET_N,
input TD_VS,
//////////// SDRAM //////////
output [12:0] DRAM_ADDR,
output [1:0] DRAM_BA,
output DRAM_CAS_N,
output DRAM_CKE,
output DRAM_CLK,
output DRAM_CS_N,
inout [31:0] DRAM_DQ,
output [3:0] DRAM_DQM,
output DRAM_RAS_N,
output DRAM_WE_N,
//////////// SRAM //////////
output [19:0] SRAM_ADDR,
output SRAM_CE_N,
inout [15:0] SRAM_DQ,
output SRAM_LB_N,
output SRAM_OE_N,
output SRAM_UB_N,
output SRAM_WE_N
);
// VGA Display Width
localparam DISP_WIDTH = 11;
// Color Width
localparam COLOR_WIDTH = 10;
// SDRAM and SRAM Data Width
localparam RAM_WIDTH = 16;
// Pad bits needed for memory
localparam PAD_BITS = RAM_WIDTH - COLOR_WIDTH;
// VGA Operating Frequency of 60Hz = 450000 cycles at 27MHz
localparam CYCLE_PER_FRAME = 450000;
// Input Resolution Parameters (units: pixels)
localparam NTSC_RES_H = 720;
// Output Resolution Parameters (units: pixels)
localparam VGA_RES_POLAR = 1'b0; // HS and VS are active-low for these settings
localparam VGA_RES_H_FRONT = 16; // Horizontal Front Porch
localparam VGA_RES_H_SYNC = 98; // Horizontal Sync Length
localparam VGA_RES_H_BACK = 46; // Horizontal Back Porch
localparam VGA_RES_H_ACT = 640; // Horizontal Actual (Visible)
localparam VGA_RES_V_FRONT = 11; // Vertical Front Porch
localparam VGA_RES_V_SYNC = 2; // Vertical Sync Length
localparam VGA_RES_V_BACK = 31; // Vertical Back Porch
localparam VGA_RES_V_ACT = 480; // Vertical Actual (Visible)
localparam VGA_RES_V_ACT_2 = 240; // Just divide the above number by 2
// SDRAM Parameters (units: pixels)
localparam LINES_ODD_START = VGA_RES_V_FRONT + VGA_RES_V_SYNC;
localparam LINES_ODD_END = LINES_ODD_START + VGA_RES_V_ACT_2;
localparam LINES_EVEN_START = LINES_ODD_END + LINES_ODD_START + 1;
localparam LINES_EVEN_END = LINES_EVEN_START + VGA_RES_V_ACT_2;
// Global Reset
wire aresetn;
// TV Decode Pipeline Output
wire [(COLOR_WIDTH-1):0] Red; // RGB data after YCbCr conversion
wire [(COLOR_WIDTH-1):0] Green; // RGB data after YCbCr conversion
wire [(COLOR_WIDTH-1):0] Blue; // RGB data after YCbCr conversion
wire RGB_valid; // Valid RGB data after YCbCr conversion, unused
// RGB to Grayscale Converter
wire [(COLOR_WIDTH-1):0] grayscale;
wire grayscale_valid;
// Curr Frame SDRAM
wire [(RAM_WIDTH-1):0] sdram_output; // SDRAM read data muxed for odd or even field
wire [(RAM_WIDTH-1):0] grayscale_odd; // SDRAM data odd field
wire [(RAM_WIDTH-1):0] grayscale_even; // SDRAM data even field
wire vga_odd_ready; // VGA data request odd field
wire vga_even_ready; // VGA data request even field
// Base Frame SRAM
wire [(RAM_WIDTH-1):0] sram_output;
// Delta Frame Generator
wire [(COLOR_WIDTH-1):0] delta_frame;
// VGA Controller Output
wire [(DISP_WIDTH-1):0] vga_x; // VGA horizontal position
wire [(DISP_WIDTH-1):0] vga_y; // VGA vertical position
wire vga_ready; // VGA data request
// Reset to Key
assign aresetn = KEY[0];
// Video Input Decode Pipeline
video_input video_input_inst
(
.aresetn (aresetn),
// TV Decoder
.TD_CLK27 (TD_CLK27),
.TD_DATA (TD_DATA),
.TD_HS (TD_HS),
.TD_RESET_N (TD_RESET_N),
.TD_VS (TD_VS),
// RGB
.R_out (Red),
.B_out (Blue),
.G_out (Green),
.RGB_valid (RGB_valid)
);
// RGB 30-bit convertered to 10-bit grayscale
rgb_to_grayscale #(
.rgb_width (COLOR_WIDTH)
) conv_rgb_to_gray (
.clk (TD_CLK27),
.aresetn (aresetn),
// Input Data Bus
.RED (Red),
.GREEN (Green),
.BLUE (Blue),
.valid_in (RGB_valid),
// Output Data Bus
.GRAYSCALE (grayscale),
.valid_out (grayscale_valid)
);
// SDRAM Frame Buffer
Sdram_Control_4Port sdram_control_inst
(
.REF_CLK (TD_CLK27),
.RESET_N (aresetn),
// FIFO Write Side 1
.WR1_DATA ({{PAD_BITS{1'b0}}, grayscale}),
.WR1 (grayscale_valid), // Write Enable
.WR1_ADDR (0), // Base address
.WR1_MAX_ADDR (VGA_RES_H_ACT*LINES_EVEN_END), // Store every pixel of every line. Blanking lines, odd lines, blanking lines, and even lines.
.WR1_LENGTH (9'h80), // The valid signal drops low every 8 samples, 16*8 = 128 bits per burst?
.WR1_LOAD (~aresetn), // Clears FIFO
.WR1_CLK (TD_CLK27),
// FIFO Read Side 1 (Odd Field, Bypass Blanking)
.RD1_DATA (grayscale_odd),
.RD1 (vga_odd_ready), // Read Enable
.RD1_ADDR (VGA_RES_H_ACT*LINES_ODD_START), // Bypass the blanking lines
.RD1_MAX_ADDR (VGA_RES_H_ACT*LINES_ODD_END ), // Read out of the valid odd lines
.RD1_LENGTH (9'h80), // Just being consistent with write length?
.RD1_LOAD (~aresetn), // Clears FIFO
.RD1_CLK (TD_CLK27),
// FIFO Read Side 2 (Even Field, Bypass Blanking)
.RD2_DATA (grayscale_even),
.RD2 (vga_even_ready), // Read Enable
.RD2_ADDR (VGA_RES_H_ACT*LINES_EVEN_START), // Bypass the blanking lines
.RD2_MAX_ADDR (VGA_RES_H_ACT*LINES_EVEN_END ), // Read out of the valid even lines
.RD2_LENGTH (9'h80), // Just being consistent with write length?
.RD2_LOAD (~aresetn), // Clears FIFO
.RD2_CLK (TD_CLK27),
// SDRAM
.SA (DRAM_ADDR),
.BA (DRAM_BA),
.CS_N (DRAM_CS_N),
.CKE (DRAM_CKE),
.RAS_N (DRAM_RAS_N),
.CAS_N (DRAM_CAS_N),
.WE_N (DRAM_WE_N),
.DQ (DRAM_DQ),
.DQM ({DRAM_DQM[1], DRAM_DQM[0]}),
.SDR_CLK (DRAM_CLK)
);
// Field Select Logic (Odd/Even)
assign vga_odd_ready = vga_y[0] ? 1'b0 : vga_ready;
assign vga_even_ready = vga_y[0] ? vga_ready : 1'b0;
assign sdram_output = ~vga_y[0] ? grayscale_odd : grayscale_even;
// SRAM Controller
sram_wrapper sram_wrapper_inst
(
// Clock and Reset
.clk (TD_CLK27),
.aresetn (aresetn),
// Wrapper Signals
.wen (~KEY[1]),
.addr ({vga_x[9:0], vga_y[9:0]}),
.din (sdram_output),
.dout (sram_output),
// SRAM Signals
.SRAM_ADDR (SRAM_ADDR),
.SRAM_CE_N (SRAM_CE_N),
.SRAM_DQ (SRAM_DQ),
.SRAM_LB_N (SRAM_LB_N),
.SRAM_OE_N (SRAM_OE_N),
.SRAM_UB_N (SRAM_UB_N),
.SRAM_WE_N (SRAM_WE_N)
);
delta_frame #(
.INPUT_WIDTH (COLOR_WIDTH)
) delta_frame_inst (
// Control
.clk (TD_CLK27),
.aresetn (aresetn),
.enable (SW[17]),
// For Moving Average Filter
.is_not_blank (vga_ready),
// For Saturation Filter
.threshold (SW[(COLOR_WIDTH-1):0]),
// Input Data
.base_frame (sram_output [(COLOR_WIDTH-1):0]),
.curr_frame (sdram_output[(COLOR_WIDTH-1):0]),
// Output Data
.delta_frame (delta_frame)
);
// VGA Controller
vga_sync #(
.H_TOTAL_WIDTH (DISP_WIDTH),
.V_TOTAL_WIDTH (DISP_WIDTH),
.POLARITY (VGA_RES_POLAR),
.H_FRONT (VGA_RES_H_FRONT),
.H_SYNC (VGA_RES_H_SYNC),
.H_BACK (VGA_RES_H_BACK),
.H_ACT (VGA_RES_H_ACT),
.V_FRONT (VGA_RES_V_FRONT),
.V_SYNC (VGA_RES_V_SYNC),
.V_BACK (VGA_RES_V_BACK),
.V_ACT (VGA_RES_V_ACT)
) vga_sync_inst (
.clock (TD_CLK27),
.aresetn (aresetn),
// Input Data
.R_in (delta_frame),
.G_in (delta_frame),
.B_in (delta_frame),
// Output Control Logic
.current_x (vga_x),
.current_y (vga_y),
.ready (vga_ready),
// Output VGA Signals
.vga_clk (VGA_CLK),
.R_out (VGA_R),
.G_out (VGA_G),
.B_out (VGA_B),
.h_sync (VGA_HS),
.v_sync (VGA_VS),
.blank_n (VGA_BLANK_N),
.sync_n (VGA_SYNC_N)
);
endmodule
|
`include "minsoc_defines.v"
module OR1K_startup
(
input [6:2] wb_adr_i,
input wb_stb_i,
input wb_cyc_i,
output reg [31:0] wb_dat_o,
output reg wb_ack_o,
input wb_clk,
input wb_rst
);
always @ (posedge wb_clk or posedge wb_rst)
if (wb_rst)
wb_dat_o <= 32'h15000000;
else
case (wb_adr_i)
0 : wb_dat_o <= 32'h18000000;
1 : wb_dat_o <= 32'hA8200000;
2 : wb_dat_o <= { 16'h1880 , `APP_ADDR_SPI , 8'h00 };
3 : wb_dat_o <= 32'hA8A00520;
4 : wb_dat_o <= 32'hA8600001;
5 : wb_dat_o <= 32'h04000014;
6 : wb_dat_o <= 32'hD4041818;
7 : wb_dat_o <= 32'h04000012;
8 : wb_dat_o <= 32'hD4040000;
9 : wb_dat_o <= 32'hE0431804;
10 : wb_dat_o <= 32'h0400000F;
11 : wb_dat_o <= 32'h9C210008;
12 : wb_dat_o <= 32'h0400000D;
13 : wb_dat_o <= 32'hE1031804;
14 : wb_dat_o <= 32'hE4080000;
15 : wb_dat_o <= 32'h0FFFFFFB;
16 : wb_dat_o <= 32'hD4081800;
17 : wb_dat_o <= 32'h04000008;
18 : wb_dat_o <= 32'h9C210004;
19 : wb_dat_o <= 32'hD4011800;
20 : wb_dat_o <= 32'hE4011000;
21 : wb_dat_o <= 32'h0FFFFFFC;
22 : wb_dat_o <= 32'hA8C00100;
23 : wb_dat_o <= 32'h44003000;
24 : wb_dat_o <= 32'hD4040018;
25 : wb_dat_o <= 32'hD4042810;
26 : wb_dat_o <= 32'h84640010;
27 : wb_dat_o <= 32'hBC030520;
28 : wb_dat_o <= 32'h13FFFFFE;
29 : wb_dat_o <= 32'h15000000;
30 : wb_dat_o <= 32'h44004800;
31 : wb_dat_o <= 32'h84640000;
endcase
always @ (posedge wb_clk or posedge wb_rst)
if (wb_rst)
wb_ack_o <= 1'b0;
else
wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o;
endmodule // OR1K_startup
|
`timescale 1ns / 1ps
module spi_amba_connector(
input clk,
input rst,
input hwrite,
input [31:0] hwdata,
input [31:0] haddr,
input hsel,
output [31:0] hrdata,
input [ 7:0] spi_data_out,
input spi_busy,
output reg [ 7:0] spi_data_in,
output reg spi_ready_send
);
reg [7:0] spi_data_out_reg;
reg [7:0] spi_data_in_reg;
assign hrdata = {{25'b0, phase || spi_busy || spi_ready_send, spi_busy ? spi_data_out_reg : spi_data_out}};
localparam IDLE = 0, DATA = 1;
reg phase;
always @(posedge clk) begin
if (rst) begin
spi_data_in <= 0;
spi_ready_send <= 0;
phase <= 0;
end else if (spi_ready_send && spi_busy) begin
spi_ready_send <= 0;
end else if (!spi_ready_send && !spi_busy) begin
if (!phase) begin
if (hsel && haddr[15:0] == 'h0000 && hwrite) phase <= 1;
end else begin
spi_data_out_reg <= spi_data_in;
spi_data_in <= spi_data_in_reg;
spi_ready_send <= 1;
phase <= 0;
end
end
end
always @(negedge clk) begin
if (phase) spi_data_in_reg <= hwdata[7:0];
end
endmodule
|
//
// GPIO controller for picorv32
//
// Little endian.
// Increasing numeric significance with increasing memory addresses known as "little-endian".
//
`include "inc/timescale.vh"
module gpio (
// Bus interface
input wire clk,
input wire resetn,
input wire enable,
input wire mem_valid,
output wire mem_ready,
input wire mem_instr,
input wire [3:0] mem_wstrb,
input wire [31:0] mem_wdata,
input wire [31:0] mem_addr,
output wire [31:0] mem_rdata,
// gpio interface
output reg [31:0] gpio
);
reg [7:0] q;
reg rdy;
always @(posedge clk) begin
if (!resetn) begin
rdy <= 0;
q <= 0;
gpio <= 0;
end else if (mem_valid & enable) begin
if (mem_wstrb[0])
gpio[7:0] <= mem_wdata[7:0];
if (mem_wstrb[1])
gpio[15:8] <= mem_wdata[15:8];
if (mem_wstrb[2])
gpio[23:16] <= mem_wdata[23:16];
if (mem_wstrb[3])
gpio[31:24] <= mem_wdata[31:24];
rdy <= 1;
end else begin
rdy <= 0;
end
q <= gpio;
end
// Wire-OR'ed bus outputs.
assign mem_rdata = enable ? q : 1'b0;
assign mem_ready = enable ? rdy : 1'b0;
endmodule
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* UDP multiplexer
*/
module udp_mux #
(
parameter S_COUNT = 4,
parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1
)
(
input wire clk,
input wire rst,
/*
* UDP frame inputs
*/
input wire [S_COUNT-1:0] s_udp_hdr_valid,
output wire [S_COUNT-1:0] s_udp_hdr_ready,
input wire [S_COUNT*48-1:0] s_eth_dest_mac,
input wire [S_COUNT*48-1:0] s_eth_src_mac,
input wire [S_COUNT*16-1:0] s_eth_type,
input wire [S_COUNT*4-1:0] s_ip_version,
input wire [S_COUNT*4-1:0] s_ip_ihl,
input wire [S_COUNT*6-1:0] s_ip_dscp,
input wire [S_COUNT*2-1:0] s_ip_ecn,
input wire [S_COUNT*16-1:0] s_ip_length,
input wire [S_COUNT*16-1:0] s_ip_identification,
input wire [S_COUNT*3-1:0] s_ip_flags,
input wire [S_COUNT*13-1:0] s_ip_fragment_offset,
input wire [S_COUNT*8-1:0] s_ip_ttl,
input wire [S_COUNT*8-1:0] s_ip_protocol,
input wire [S_COUNT*16-1:0] s_ip_header_checksum,
input wire [S_COUNT*32-1:0] s_ip_source_ip,
input wire [S_COUNT*32-1:0] s_ip_dest_ip,
input wire [S_COUNT*16-1:0] s_udp_source_port,
input wire [S_COUNT*16-1:0] s_udp_dest_port,
input wire [S_COUNT*16-1:0] s_udp_length,
input wire [S_COUNT*16-1:0] s_udp_checksum,
input wire [S_COUNT*DATA_WIDTH-1:0] s_udp_payload_axis_tdata,
input wire [S_COUNT*KEEP_WIDTH-1:0] s_udp_payload_axis_tkeep,
input wire [S_COUNT-1:0] s_udp_payload_axis_tvalid,
output wire [S_COUNT-1:0] s_udp_payload_axis_tready,
input wire [S_COUNT-1:0] s_udp_payload_axis_tlast,
input wire [S_COUNT*ID_WIDTH-1:0] s_udp_payload_axis_tid,
input wire [S_COUNT*DEST_WIDTH-1:0] s_udp_payload_axis_tdest,
input wire [S_COUNT*USER_WIDTH-1:0] s_udp_payload_axis_tuser,
/*
* UDP frame output
*/
output wire m_udp_hdr_valid,
input wire m_udp_hdr_ready,
output wire [47:0] m_eth_dest_mac,
output wire [47:0] m_eth_src_mac,
output wire [15:0] m_eth_type,
output wire [3:0] m_ip_version,
output wire [3:0] m_ip_ihl,
output wire [5:0] m_ip_dscp,
output wire [1:0] m_ip_ecn,
output wire [15:0] m_ip_length,
output wire [15:0] m_ip_identification,
output wire [2:0] m_ip_flags,
output wire [12:0] m_ip_fragment_offset,
output wire [7:0] m_ip_ttl,
output wire [7:0] m_ip_protocol,
output wire [15:0] m_ip_header_checksum,
output wire [31:0] m_ip_source_ip,
output wire [31:0] m_ip_dest_ip,
output wire [15:0] m_udp_source_port,
output wire [15:0] m_udp_dest_port,
output wire [15:0] m_udp_length,
output wire [15:0] m_udp_checksum,
output wire [DATA_WIDTH-1:0] m_udp_payload_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_udp_payload_axis_tkeep,
output wire m_udp_payload_axis_tvalid,
input wire m_udp_payload_axis_tready,
output wire m_udp_payload_axis_tlast,
output wire [ID_WIDTH-1:0] m_udp_payload_axis_tid,
output wire [DEST_WIDTH-1:0] m_udp_payload_axis_tdest,
output wire [USER_WIDTH-1:0] m_udp_payload_axis_tuser,
/*
* Control
*/
input wire enable,
input wire [$clog2(S_COUNT)-1:0] select
);
parameter CL_S_COUNT = $clog2(S_COUNT);
reg [CL_S_COUNT-1:0] select_reg = 2'd0, select_next;
reg frame_reg = 1'b0, frame_next;
reg [S_COUNT-1:0] s_udp_hdr_ready_reg = 0, s_udp_hdr_ready_next;
reg [S_COUNT-1:0] s_udp_payload_axis_tready_reg = 0, s_udp_payload_axis_tready_next;
reg m_udp_hdr_valid_reg = 1'b0, m_udp_hdr_valid_next;
reg [47:0] m_eth_dest_mac_reg = 48'd0, m_eth_dest_mac_next;
reg [47:0] m_eth_src_mac_reg = 48'd0, m_eth_src_mac_next;
reg [15:0] m_eth_type_reg = 16'd0, m_eth_type_next;
reg [3:0] m_ip_version_reg = 4'd0, m_ip_version_next;
reg [3:0] m_ip_ihl_reg = 4'd0, m_ip_ihl_next;
reg [5:0] m_ip_dscp_reg = 6'd0, m_ip_dscp_next;
reg [1:0] m_ip_ecn_reg = 2'd0, m_ip_ecn_next;
reg [15:0] m_ip_length_reg = 16'd0, m_ip_length_next;
reg [15:0] m_ip_identification_reg = 16'd0, m_ip_identification_next;
reg [2:0] m_ip_flags_reg = 3'd0, m_ip_flags_next;
reg [12:0] m_ip_fragment_offset_reg = 13'd0, m_ip_fragment_offset_next;
reg [7:0] m_ip_ttl_reg = 8'd0, m_ip_ttl_next;
reg [7:0] m_ip_protocol_reg = 8'd0, m_ip_protocol_next;
reg [15:0] m_ip_header_checksum_reg = 16'd0, m_ip_header_checksum_next;
reg [31:0] m_ip_source_ip_reg = 32'd0, m_ip_source_ip_next;
reg [31:0] m_ip_dest_ip_reg = 32'd0, m_ip_dest_ip_next;
reg [15:0] m_udp_source_port_reg = 16'd0, m_udp_source_port_next;
reg [15:0] m_udp_dest_port_reg = 16'd0, m_udp_dest_port_next;
reg [15:0] m_udp_length_reg = 16'd0, m_udp_length_next;
reg [15:0] m_udp_checksum_reg = 16'd0, m_udp_checksum_next;
// internal datapath
reg [DATA_WIDTH-1:0] m_udp_payload_axis_tdata_int;
reg [KEEP_WIDTH-1:0] m_udp_payload_axis_tkeep_int;
reg m_udp_payload_axis_tvalid_int;
reg m_udp_payload_axis_tready_int_reg = 1'b0;
reg m_udp_payload_axis_tlast_int;
reg [ID_WIDTH-1:0] m_udp_payload_axis_tid_int;
reg [DEST_WIDTH-1:0] m_udp_payload_axis_tdest_int;
reg [USER_WIDTH-1:0] m_udp_payload_axis_tuser_int;
wire m_udp_payload_axis_tready_int_early;
assign s_udp_hdr_ready = s_udp_hdr_ready_reg;
assign s_udp_payload_axis_tready = s_udp_payload_axis_tready_reg;
assign m_udp_hdr_valid = m_udp_hdr_valid_reg;
assign m_eth_dest_mac = m_eth_dest_mac_reg;
assign m_eth_src_mac = m_eth_src_mac_reg;
assign m_eth_type = m_eth_type_reg;
assign m_ip_version = m_ip_version_reg;
assign m_ip_ihl = m_ip_ihl_reg;
assign m_ip_dscp = m_ip_dscp_reg;
assign m_ip_ecn = m_ip_ecn_reg;
assign m_ip_length = m_ip_length_reg;
assign m_ip_identification = m_ip_identification_reg;
assign m_ip_flags = m_ip_flags_reg;
assign m_ip_fragment_offset = m_ip_fragment_offset_reg;
assign m_ip_ttl = m_ip_ttl_reg;
assign m_ip_protocol = m_ip_protocol_reg;
assign m_ip_header_checksum = m_ip_header_checksum_reg;
assign m_ip_source_ip = m_ip_source_ip_reg;
assign m_ip_dest_ip = m_ip_dest_ip_reg;
assign m_udp_source_port = m_udp_source_port_reg;
assign m_udp_dest_port = m_udp_dest_port_reg;
assign m_udp_length = m_udp_length_reg;
assign m_udp_checksum = m_udp_checksum_reg;
// mux for incoming packet
wire [DATA_WIDTH-1:0] current_s_tdata = s_udp_payload_axis_tdata[select_reg*DATA_WIDTH +: DATA_WIDTH];
wire [KEEP_WIDTH-1:0] current_s_tkeep = s_udp_payload_axis_tkeep[select_reg*KEEP_WIDTH +: KEEP_WIDTH];
wire current_s_tvalid = s_udp_payload_axis_tvalid[select_reg];
wire current_s_tready = s_udp_payload_axis_tready[select_reg];
wire current_s_tlast = s_udp_payload_axis_tlast[select_reg];
wire [ID_WIDTH-1:0] current_s_tid = s_udp_payload_axis_tid[select_reg*ID_WIDTH +: ID_WIDTH];
wire [DEST_WIDTH-1:0] current_s_tdest = s_udp_payload_axis_tdest[select_reg*DEST_WIDTH +: DEST_WIDTH];
wire [USER_WIDTH-1:0] current_s_tuser = s_udp_payload_axis_tuser[select_reg*USER_WIDTH +: USER_WIDTH];
always @* begin
select_next = select_reg;
frame_next = frame_reg;
s_udp_hdr_ready_next = 0;
s_udp_payload_axis_tready_next = 0;
m_udp_hdr_valid_next = m_udp_hdr_valid_reg && !m_udp_hdr_ready;
m_eth_dest_mac_next = m_eth_dest_mac_reg;
m_eth_src_mac_next = m_eth_src_mac_reg;
m_eth_type_next = m_eth_type_reg;
m_ip_version_next = m_ip_version_reg;
m_ip_ihl_next = m_ip_ihl_reg;
m_ip_dscp_next = m_ip_dscp_reg;
m_ip_ecn_next = m_ip_ecn_reg;
m_ip_length_next = m_ip_length_reg;
m_ip_identification_next = m_ip_identification_reg;
m_ip_flags_next = m_ip_flags_reg;
m_ip_fragment_offset_next = m_ip_fragment_offset_reg;
m_ip_ttl_next = m_ip_ttl_reg;
m_ip_protocol_next = m_ip_protocol_reg;
m_ip_header_checksum_next = m_ip_header_checksum_reg;
m_ip_source_ip_next = m_ip_source_ip_reg;
m_ip_dest_ip_next = m_ip_dest_ip_reg;
m_udp_source_port_next = m_udp_source_port_reg;
m_udp_dest_port_next = m_udp_dest_port_reg;
m_udp_length_next = m_udp_length_reg;
m_udp_checksum_next = m_udp_checksum_reg;
if (current_s_tvalid & current_s_tready) begin
// end of frame detection
if (current_s_tlast) begin
frame_next = 1'b0;
end
end
if (!frame_reg && enable && !m_udp_hdr_valid && (s_udp_hdr_valid & (1 << select))) begin
// start of frame, grab select value
frame_next = 1'b1;
select_next = select;
s_udp_hdr_ready_next = (1 << select);
m_udp_hdr_valid_next = 1'b1;
m_eth_dest_mac_next = s_eth_dest_mac[select*48 +: 48];
m_eth_src_mac_next = s_eth_src_mac[select*48 +: 48];
m_eth_type_next = s_eth_type[select*16 +: 16];
m_ip_version_next = s_ip_version[select*4 +: 4];
m_ip_ihl_next = s_ip_ihl[select*4 +: 4];
m_ip_dscp_next = s_ip_dscp[select*6 +: 6];
m_ip_ecn_next = s_ip_ecn[select*2 +: 2];
m_ip_length_next = s_ip_length[select*16 +: 16];
m_ip_identification_next = s_ip_identification[select*16 +: 16];
m_ip_flags_next = s_ip_flags[select*3 +: 3];
m_ip_fragment_offset_next = s_ip_fragment_offset[select*13 +: 13];
m_ip_ttl_next = s_ip_ttl[select*8 +: 8];
m_ip_protocol_next = s_ip_protocol[select*8 +: 8];
m_ip_header_checksum_next = s_ip_header_checksum[select*16 +: 16];
m_ip_source_ip_next = s_ip_source_ip[select*32 +: 32];
m_ip_dest_ip_next = s_ip_dest_ip[select*32 +: 32];
m_udp_source_port_next = s_udp_source_port[select*16 +: 16];
m_udp_dest_port_next = s_udp_dest_port[select*16 +: 16];
m_udp_length_next = s_udp_length[select*16 +: 16];
m_udp_checksum_next = s_udp_checksum[select*16 +: 16];
end
// generate ready signal on selected port
s_udp_payload_axis_tready_next = (m_udp_payload_axis_tready_int_early && frame_next) << select_next;
// pass through selected packet data
m_udp_payload_axis_tdata_int = current_s_tdata;
m_udp_payload_axis_tkeep_int = current_s_tkeep;
m_udp_payload_axis_tvalid_int = current_s_tvalid && current_s_tready && frame_reg;
m_udp_payload_axis_tlast_int = current_s_tlast;
m_udp_payload_axis_tid_int = current_s_tid;
m_udp_payload_axis_tdest_int = current_s_tdest;
m_udp_payload_axis_tuser_int = current_s_tuser;
end
always @(posedge clk) begin
if (rst) begin
select_reg <= 0;
frame_reg <= 1'b0;
s_udp_hdr_ready_reg <= 0;
s_udp_payload_axis_tready_reg <= 0;
m_udp_hdr_valid_reg <= 1'b0;
end else begin
select_reg <= select_next;
frame_reg <= frame_next;
s_udp_hdr_ready_reg <= s_udp_hdr_ready_next;
s_udp_payload_axis_tready_reg <= s_udp_payload_axis_tready_next;
m_udp_hdr_valid_reg <= m_udp_hdr_valid_next;
end
m_eth_dest_mac_reg <= m_eth_dest_mac_next;
m_eth_src_mac_reg <= m_eth_src_mac_next;
m_eth_type_reg <= m_eth_type_next;
m_ip_version_reg <= m_ip_version_next;
m_ip_ihl_reg <= m_ip_ihl_next;
m_ip_dscp_reg <= m_ip_dscp_next;
m_ip_ecn_reg <= m_ip_ecn_next;
m_ip_length_reg <= m_ip_length_next;
m_ip_identification_reg <= m_ip_identification_next;
m_ip_flags_reg <= m_ip_flags_next;
m_ip_fragment_offset_reg <= m_ip_fragment_offset_next;
m_ip_ttl_reg <= m_ip_ttl_next;
m_ip_protocol_reg <= m_ip_protocol_next;
m_ip_header_checksum_reg <= m_ip_header_checksum_next;
m_ip_source_ip_reg <= m_ip_source_ip_next;
m_ip_dest_ip_reg <= m_ip_dest_ip_next;
m_udp_source_port_reg <= m_udp_source_port_next;
m_udp_dest_port_reg <= m_udp_dest_port_next;
m_udp_length_reg <= m_udp_length_next;
m_udp_checksum_reg <= m_udp_checksum_next;
end
// output datapath logic
reg [DATA_WIDTH-1:0] m_udp_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] m_udp_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg m_udp_payload_axis_tvalid_reg = 1'b0, m_udp_payload_axis_tvalid_next;
reg m_udp_payload_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] m_udp_payload_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] m_udp_payload_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] m_udp_payload_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] temp_m_udp_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_m_udp_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_m_udp_payload_axis_tvalid_reg = 1'b0, temp_m_udp_payload_axis_tvalid_next;
reg temp_m_udp_payload_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] temp_m_udp_payload_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] temp_m_udp_payload_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_m_udp_payload_axis_tuser_reg = {USER_WIDTH{1'b0}};
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_axis_temp_to_output;
assign m_udp_payload_axis_tdata = m_udp_payload_axis_tdata_reg;
assign m_udp_payload_axis_tkeep = KEEP_ENABLE ? m_udp_payload_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign m_udp_payload_axis_tvalid = m_udp_payload_axis_tvalid_reg;
assign m_udp_payload_axis_tlast = m_udp_payload_axis_tlast_reg;
assign m_udp_payload_axis_tid = ID_ENABLE ? m_udp_payload_axis_tid_reg : {ID_WIDTH{1'b0}};
assign m_udp_payload_axis_tdest = DEST_ENABLE ? m_udp_payload_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign m_udp_payload_axis_tuser = USER_ENABLE ? m_udp_payload_axis_tuser_reg : {USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_udp_payload_axis_tready_int_early = m_udp_payload_axis_tready || (!temp_m_udp_payload_axis_tvalid_reg && (!m_udp_payload_axis_tvalid_reg || !m_udp_payload_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_udp_payload_axis_tvalid_next = m_udp_payload_axis_tvalid_reg;
temp_m_udp_payload_axis_tvalid_next = temp_m_udp_payload_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (m_udp_payload_axis_tready_int_reg) begin
// input is ready
if (m_udp_payload_axis_tready || !m_udp_payload_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_udp_payload_axis_tvalid_next = m_udp_payload_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_udp_payload_axis_tvalid_next = m_udp_payload_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (m_udp_payload_axis_tready) begin
// input is not ready, but output is ready
m_udp_payload_axis_tvalid_next = temp_m_udp_payload_axis_tvalid_reg;
temp_m_udp_payload_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_udp_payload_axis_tvalid_reg <= 1'b0;
m_udp_payload_axis_tready_int_reg <= 1'b0;
temp_m_udp_payload_axis_tvalid_reg <= 1'b0;
end else begin
m_udp_payload_axis_tvalid_reg <= m_udp_payload_axis_tvalid_next;
m_udp_payload_axis_tready_int_reg <= m_udp_payload_axis_tready_int_early;
temp_m_udp_payload_axis_tvalid_reg <= temp_m_udp_payload_axis_tvalid_next;
end
// datapath
if (store_axis_int_to_output) begin
m_udp_payload_axis_tdata_reg <= m_udp_payload_axis_tdata_int;
m_udp_payload_axis_tkeep_reg <= m_udp_payload_axis_tkeep_int;
m_udp_payload_axis_tlast_reg <= m_udp_payload_axis_tlast_int;
m_udp_payload_axis_tid_reg <= m_udp_payload_axis_tid_int;
m_udp_payload_axis_tdest_reg <= m_udp_payload_axis_tdest_int;
m_udp_payload_axis_tuser_reg <= m_udp_payload_axis_tuser_int;
end else if (store_axis_temp_to_output) begin
m_udp_payload_axis_tdata_reg <= temp_m_udp_payload_axis_tdata_reg;
m_udp_payload_axis_tkeep_reg <= temp_m_udp_payload_axis_tkeep_reg;
m_udp_payload_axis_tlast_reg <= temp_m_udp_payload_axis_tlast_reg;
m_udp_payload_axis_tid_reg <= temp_m_udp_payload_axis_tid_reg;
m_udp_payload_axis_tdest_reg <= temp_m_udp_payload_axis_tdest_reg;
m_udp_payload_axis_tuser_reg <= temp_m_udp_payload_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_m_udp_payload_axis_tdata_reg <= m_udp_payload_axis_tdata_int;
temp_m_udp_payload_axis_tkeep_reg <= m_udp_payload_axis_tkeep_int;
temp_m_udp_payload_axis_tlast_reg <= m_udp_payload_axis_tlast_int;
temp_m_udp_payload_axis_tid_reg <= m_udp_payload_axis_tid_int;
temp_m_udp_payload_axis_tdest_reg <= m_udp_payload_axis_tdest_int;
temp_m_udp_payload_axis_tuser_reg <= m_udp_payload_axis_tuser_int;
end
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// dc filter- y(n) = c*x(n) + (1-c)*y(n-1)
`timescale 1ps/1ps
module ad_dcfilter #(
// data path disable
parameter DISABLE = 0) (
// data interface
input clk,
input valid,
input [15:0] data,
output valid_out,
output [15:0] data_out,
// control interface
input dcfilt_enb,
input [15:0] dcfilt_coeff,
input [15:0] dcfilt_offset);
// internal registers
reg [15:0] dcfilt_coeff_d = 'd0;
reg [47:0] dc_offset = 'd0;
reg [47:0] dc_offset_d = 'd0;
reg valid_d = 'd0;
reg [15:0] data_d = 'd0;
reg valid_2d = 'd0;
reg [15:0] data_2d = 'd0;
reg [15:0] data_dcfilt = 'd0;
reg valid_int = 'd0;
reg [15:0] data_int = 'd0;
// internal signals
wire [47:0] dc_offset_s;
// data-path disable
generate
if (DISABLE == 1) begin
assign valid_out = valid;
assign data_out = data;
end else begin
assign valid_out = valid_int;
assign data_out = data_int;
end
endgenerate
// dcfilt_coeff is flopped so to remove warnings from vivado
always @(posedge clk) begin
dcfilt_coeff_d <= dcfilt_coeff;
end
// removing dc offset
always @(posedge clk) begin
dc_offset <= dc_offset_s;
dc_offset_d <= dc_offset;
valid_d <= valid;
if (valid == 1'b1) begin
data_d <= data + dcfilt_offset;
end
valid_2d <= valid_d;
data_2d <= data_d;
data_dcfilt <= data_d - dc_offset[32:17];
if (dcfilt_enb == 1'b1) begin
valid_int <= valid_2d;
data_int <= data_dcfilt;
end else begin
valid_int <= valid_2d;
data_int <= data_2d;
end
end
// dsp slice instance ((D-A)*B)+C
DSP48E1 #(
.ACASCREG (1),
.ADREG (1),
.ALUMODEREG (0),
.AREG (1),
.AUTORESET_PATDET ("NO_RESET"),
.A_INPUT ("DIRECT"),
.BCASCREG (1),
.BREG (1),
.B_INPUT ("DIRECT"),
.CARRYINREG (0),
.CARRYINSELREG (0),
.CREG (1),
.DREG (0),
.INMODEREG (0),
.MASK (48'h3fffffffffff),
.MREG (1),
.OPMODEREG (0),
.PATTERN (48'h000000000000),
.PREG (1),
.SEL_MASK ("MASK"),
.SEL_PATTERN ("PATTERN"),
.USE_DPORT ("TRUE"),
.USE_MULT ("MULTIPLY"),
.USE_PATTERN_DETECT ("NO_PATDET"),
.USE_SIMD ("ONE48"))
i_dsp48e1 (
.CLK (clk),
.A ({{14{dc_offset_s[32]}}, dc_offset_s[32:17]}),
.B ({{2{dcfilt_coeff_d[15]}}, dcfilt_coeff_d}),
.C (dc_offset_d),
.D ({{9{data_d[15]}}, data_d}),
.MULTSIGNIN (1'd0),
.CARRYIN (1'd0),
.CARRYCASCIN (1'd0),
.ACIN (30'd0),
.BCIN (18'd0),
.PCIN (48'd0),
.P (dc_offset_s),
.MULTSIGNOUT (),
.CARRYOUT (),
.CARRYCASCOUT (),
.ACOUT (),
.BCOUT (),
.PCOUT (),
.ALUMODE (4'd0),
.CARRYINSEL (3'd0),
.INMODE (5'b01100),
.OPMODE (7'b0110101),
.PATTERNBDETECT (),
.PATTERNDETECT (),
.OVERFLOW (),
.UNDERFLOW (),
.CEA1 (1'd0),
.CEA2 (1'd1),
.CEAD (1'd1),
.CEALUMODE (1'd0),
.CEB1 (1'd0),
.CEB2 (1'd1),
.CEC (1'd1),
.CECARRYIN (1'd0),
.CECTRL (1'd0),
.CED (1'd1),
.CEINMODE (1'd0),
.CEM (1'd1),
.CEP (1'd0),
.RSTA (1'd0),
.RSTALLCARRYIN (1'd0),
.RSTALUMODE (1'd0),
.RSTB (1'd0),
.RSTC (1'd0),
.RSTCTRL (1'd0),
.RSTD (1'd0),
.RSTINMODE (1'd0),
.RSTM (1'd0),
.RSTP (1'd0));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR4_TB_V
`define SKY130_FD_SC_HS__NOR4_TB_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nor4.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg D;
reg VPWR;
reg VGND;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 C = 1'b1;
#200 D = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 C = 1'b0;
#320 D = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 D = 1'b1;
#440 C = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 D = 1'bx;
#560 C = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hs__nor4 dut (.A(A), .B(B), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR4_TB_V
|
/*
* Copyright (c) 2015, Ziliang Guo
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Wisconsin Robotics nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL WISCONSIN ROBOTICS BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
`define init_camera_amd_cnt 6
`define init_camera_acn_cnt 6
`define init_camera_act_i_cnt 6
`define init_camera_act_s_cnt 6
module camera_serial_command_generator
(
init_camera,
take_photo,
stop_photo,
tx_data,
tx_en,
tx_busy,
rx_data,
rx_done,
sys_clk_50,
rst,
busy,
cmd_gen_state_debug,
counter_debug,
rx_data_debug
);
`define idle_state 4'b0000
`define init_camera_amd_state 4'b0001
`define init_camera_amd_ack_state 4'b0010
`define init_camera_acn_state 4'b0011
`define init_camera_acn_ack_state 4'b0100
`define init_camera_act_i_state 4'b0101
`define init_camera_act_i_ack_state 4'b0110
`define init_camera_act_s_state 4'b0111
`define init_camera_act_s_ack_state 4'b1000
input init_camera;
input take_photo;
input stop_photo;
input sys_clk_50;
input rst;
input tx_busy;
output [7:0] tx_data;
output tx_en;
input [7:0] rx_data;
input rx_done;
output busy;
output [4:0] cmd_gen_state_debug;
output [3:0] counter_debug;
output [7:0] rx_data_debug;
reg [3:0] cmd_gen_state;
reg [3:0] cmd_gen_state_next;
reg [3:0] counter;
reg [3:0] counter_next;
wire [7:0] init_camera_amd [0:`init_camera_amd_cnt-1];
assign init_camera_amd[0] = "A";
assign init_camera_amd[1] = "M";
assign init_camera_amd[2] = "D";
assign init_camera_amd[3] = " ";
assign init_camera_amd[4] = "N";
assign init_camera_amd[5] = "\r";
wire [7:0] init_camera_acn [0:`init_camera_acn_cnt-1];
assign init_camera_acn[0] = "A";
assign init_camera_acn[1] = "C";
assign init_camera_acn[2] = "N";
assign init_camera_acn[3] = " ";
assign init_camera_acn[4] = "1";
assign init_camera_acn[5] = "\r";
wire [7:0] init_camera_act_i [0:`init_camera_act_i_cnt-1];
assign init_camera_act_i[0] = "A";
assign init_camera_act_i[1] = "C";
assign init_camera_act_i[2] = "T";
assign init_camera_act_i[3] = " ";
assign init_camera_act_i[4] = "I";
assign init_camera_act_i[5] = "\r";
wire [7:0] init_camera_act_s [0:`init_camera_act_s_cnt-1];
assign init_camera_act_s[0] = "A";
assign init_camera_act_s[1] = "C";
assign init_camera_act_s[2] = "T";
assign init_camera_act_s[3] = " ";
assign init_camera_act_s[4] = "S";
assign init_camera_act_s[5] = "\r";
reg busy_reg;
reg [7:0] tx_data_reg;
//(* KEEP = "TRUE" *) reg tx_en_reg;
reg tx_en_reg;
(* KEEP = "TRUE" *) reg [7:0] rx_data_reg;
assign rx_data_debug = rx_data_reg;
reg init_camera_reg;
reg take_photo_reg;
reg stop_photo_reg;
reg camera_initiated_reg;
reg camera_initiated_reg_next;
reg tx_busy_reg;
assign cmd_gen_state_debug = {camera_initiated_reg, cmd_gen_state};
assign counter_debug = counter;
always@(posedge sys_clk_50) begin
if(rst) begin
init_camera_reg <= 1'b0;
take_photo_reg <= 1'b0;
stop_photo_reg <= 1'b0;
cmd_gen_state <= `idle_state;
counter <= 4'd0;
camera_initiated_reg <= 1'b0;
tx_busy_reg <= 1'b0;
rx_data_reg <= 8'd0;
end
else begin
init_camera_reg <= init_camera;
take_photo_reg <= take_photo;
stop_photo_reg <= stop_photo;
cmd_gen_state <= cmd_gen_state_next;
counter <= counter_next;
camera_initiated_reg <= camera_initiated_reg_next;
tx_busy_reg <= tx_busy;
if(rx_done) begin
rx_data_reg <= rx_data;
end
end
end
always@(*) begin
cmd_gen_state_next <= cmd_gen_state;
busy_reg <= 1'b0;
counter_next <= counter;
tx_data_reg <= 8'd0;
tx_en_reg <= 1'b0;
camera_initiated_reg_next <= camera_initiated_reg;
/*
if(tx_busy_reg & ~tx_busy) begin
camera_initiated_reg_next <= 1'b1;
end
*/
if(cmd_gen_state != `idle_state) begin
busy_reg <= 1'b1;
end
case(cmd_gen_state)
`idle_state: begin
counter_next <= 4'd0;
if(~init_camera_reg & init_camera) begin
cmd_gen_state_next <= `init_camera_amd_state;
end
else if(~take_photo_reg & take_photo) begin
cmd_gen_state_next <= `init_camera_act_i_state;
end
else if(~stop_photo_reg & stop_photo) begin
cmd_gen_state_next <= `init_camera_act_s_state;
end
end
`init_camera_amd_state: begin
tx_data_reg <= init_camera_amd[counter];
tx_en_reg <= 1'b1;
if(~tx_busy_reg & tx_busy) begin
counter_next <= counter + 4'd1;
if(counter == 4'd5) begin
cmd_gen_state_next <= `init_camera_amd_ack_state;
counter_next <= 4'd0;
end
end
end
`init_camera_amd_ack_state: begin
if(rx_done == 1'b1) begin
counter_next <= counter + 4'd1;
if(counter == 4'd5) begin
cmd_gen_state_next <= `init_camera_acn_state;
counter_next <= 4'd0;
end
end
end
`init_camera_acn_state: begin
tx_data_reg <= init_camera_acn[counter];
tx_en_reg <= 1'b1;
if(~tx_busy_reg & tx_busy) begin
counter_next <= counter + 4'd1;
if(counter == 4'd5) begin
cmd_gen_state_next <= `init_camera_acn_ack_state;
counter_next <= 4'd0;
end
end
end
`init_camera_acn_ack_state: begin
if(rx_done == 1'b1) begin
counter_next <= counter + 4'd1;
if(counter == 4'd5) begin
camera_initiated_reg_next <= 1'b1;
cmd_gen_state_next <= `idle_state;
counter_next <= 4'd0;
end
end
end
`init_camera_act_i_state: begin
tx_data_reg <= init_camera_act_i[counter];
tx_en_reg <= 1'b1;
if(~tx_busy_reg & tx_busy) begin
if(counter == (`init_camera_act_i_cnt - 1)) begin
cmd_gen_state_next <= `init_camera_act_i_ack_state;
counter_next <= 4'd0;
end
else begin
counter_next <= counter + 4'd1;
end
end
end
`init_camera_act_i_ack_state: begin
if(counter == `init_camera_act_i_cnt) begin
cmd_gen_state_next <= `idle_state;
counter_next <= 4'd0;
end
else if(rx_done) begin
counter_next <= counter + 4'd1;
end
end
`init_camera_act_s_state: begin
tx_data_reg <= init_camera_act_s[counter];
tx_en_reg <= 1'b1;
if(~tx_busy_reg & tx_busy) begin
if(counter == (`init_camera_act_s_cnt - 1)) begin
cmd_gen_state_next <= `init_camera_act_s_ack_state;
counter_next <= 4'd0;
end
else begin
counter_next <= counter + 4'd1;
end
end
end
`init_camera_act_s_ack_state: begin
if(counter == `init_camera_act_s_cnt) begin
cmd_gen_state_next <= `idle_state;
counter_next <= 4'd0;
end
else if(rx_done) begin
counter_next <= counter + 4'd1;
end
end
endcase
end
assign busy = busy_reg;
assign tx_data = tx_data_reg;
assign tx_en = tx_en_reg;
endmodule |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 07:22:37 05/11/2017
// Design Name: axi_spi_if
// Module Name: E:/University/AXI_SPI_IF/ise/axi_spi_test_transfer.v
// Project Name: axi_spi_if
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: axi_spi_if
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module axi_spi_transfer_test;
// Inputs
reg clk_i;
reg reset_n_i;
reg awvalid_i;
reg [27:0] awaddr_i;
reg awprot_i;
reg wvalid_i;
reg [31:0] wdata_i;
reg [3:0] wstrb_i;
reg bready_i;
reg arvalid_i;
reg [27:0] araddr_i;
reg [2:0] arprot_i;
reg rready_i;
reg spi_miso_i;
reg [2:0] read_status_reg;
// Outputs
wire awready_o;
wire wready_o;
wire bvalid_o;
wire [1:0] bresp_o;
wire arready_o;
wire rvalid_o;
wire [31:0] rdata_o;
wire [1:0] rresp_o;
wire [3:0] spi_ssel_o;
wire spi_sck_o;
wire spi_mosi_o;
integer i;
// Instantiate the Unit Under Test (UUT)
axi_spi_if uut (
.clk_i(clk_i),
.reset_n_i(reset_n_i),
.awvalid_i(awvalid_i),
.awready_o(awready_o),
.awaddr_i(awaddr_i),
.awprot_i(awprot_i),
.wvalid_i(wvalid_i),
.wready_o(wready_o),
.wdata_i(wdata_i),
.wstrb_i(wstrb_i),
.bvalid_o(bvalid_o),
.bready_i(bready_i),
.bresp_o(bresp_o),
.arvalid_i(arvalid_i),
.arready_o(arready_o),
.araddr_i(araddr_i),
.arprot_i(arprot_i),
.rvalid_o(rvalid_o),
.rready_i(rready_i),
.rdata_o(rdata_o),
.rresp_o(rresp_o),
.spi_ssel_o(spi_ssel_o),
.spi_sck_o(spi_sck_o),
.spi_mosi_o(spi_mosi_o),
.spi_miso_i(spi_mosi_o)
);
initial begin
// Initialize Inputs
clk_i = 0;
reset_n_i = 0;
awvalid_i = 0;
awaddr_i = 0;
awprot_i = 0;
wvalid_i = 0;
wdata_i = 0;
wstrb_i = 0;
bready_i = 0;
arvalid_i = 0;
araddr_i = 0;
arprot_i = 0;
rready_i = 0;
spi_miso_i = 0;
read_status_reg = 7;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
reset_n_i = 1;
spi_miso_i = 1;
bready_i = 1;
rready_i = 1;
/*
reg_control_i = 32'h0000_0602;
reg_trans_ctrl_i = 32'h0000_0002;
*/
// ===========================================
// WRITE CONTROL REGISTER
// ===========================================
wdata_i = 32'h0000_0102;
awaddr_i = 0;
awvalid_i = 1;
wvalid_i = 1;
wait(awready_o && wready_o);
@(posedge clk_i) #1;
awvalid_i = 0;
wvalid_i = 0;
#100;
// ===========================================
// WRITE TX FIFO
// ===========================================
for (i=0; i < 8; i = i + 1) begin
wdata_i = 32'd1 + i;
awaddr_i = 3;
awvalid_i = 1;
wvalid_i = 1;
wait(awready_o && wready_o);
@(posedge clk_i) #1;
awvalid_i = 0;
wvalid_i = 0;
#100;
end
// ===========================================
// WRITE TRANSFER CONTROL REGISTER
// ===========================================
wdata_i = 32'h0000_2002;
awaddr_i = 1;
awvalid_i = 1;
wvalid_i = 1;
wait(awready_o && wready_o);
@(posedge clk_i) #1;
awvalid_i = 0;
wvalid_i = 0;
spi_miso_i = 1;
// ===========================================
// READ STATUS REGISTER
// ===========================================
araddr_i = 2;
arvalid_i = 1;
wait(arready_o);
@(posedge clk_i) #1;
arvalid_i = 0;
#100;
while (rdata_o) begin
araddr_i = 2;
arvalid_i = 1;
wait(arready_o);
@(posedge clk_i) #1;
arvalid_i = 0;
#100;
end
#500;
// ===========================================
// READ RX FIFO
// ===========================================
for (i=0; i < 8; i = i + 1) begin
araddr_i = 3;
arvalid_i = 1;
wait(arready_o);
@(posedge clk_i) #1;
arvalid_i = 0;
#100;
end
end
always #77 spi_miso_i = ~spi_miso_i;
always #5 clk_i = ~clk_i;
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O211A_M_V
`define SKY130_FD_SC_LP__O211A_M_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog wrapper for o211a with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o211a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o211a_m (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o211a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o211a_m (
X ,
A1,
A2,
B1,
C1
);
output X ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o211a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O211A_M_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2014/03/17 18:08:10
// Design Name:
// Module Name: filter
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
//symmetric filter
module filter
(
input clk,
input resetn,
input [71:0] din,
input [53:0] kernel,
input din_valid,
output [15:0] dout,
output dout_valid
);
parameter latency = 9;// layer 1: 3, layer 2: 3, layer 3~5: 3, 3+3+3 = 9
wire [8:0] din_array [8:0];
wire [5:0] kernel_array [8:0];
wire plus_or_minus [2:0]; // 0 for plus, 1 for minus.
genvar i;
generate
for(i = 0; i < 9; i = i + 1) begin
assign din_array[i] = {1'b0, din[i*8 +: 8]}; // for signed num 0~255
assign kernel_array[i] = kernel[i*6 +: 6]; // -32~31
end
for(i = 0; i < 3; i = i + 1) begin
assign plus_or_minus[i] = (kernel_array[i*3] == kernel_array[i*3+2]) ? 1'b0 : 1'b1;
end
endgenerate
reg [latency-1:0] layer_valid;
wire [14:0] layer_1_2 [2:0];//(a+b)*c
reg [8:0] layer_1_2_buf [3*3-1:0];// din_array 1 4 7 buffer (din1 -> 0->1->2) (din3 -> 3->4->5) (din5 -> 6->7->8) latency of layer 1 is 3
wire [15:0] layer_2_3 [2:0];// a*b+c result, latency of layer 3 is 3
reg [15:0] layer_3_4 [1:0];
reg [15:0] layer_4_5;
reg [15:0] layer_5_end;
assign dout = layer_5_end;
assign dout_valid = layer_valid[latency-1];
generate
for(i = 0; i < 3; i = i + 1)
begin:layer1 // (0 +/- 2)*kernel (3 +/- 5)*kernel (6 +/- 8)*kernel
xbip_dsp48_macro_preadder_l3 pre_adder (// (A+D)*B latency 3
.CLK(clk), // input CLK
.A(din_array[i*3]), // input [8 : 0] A
.B(kernel_array[i*3]), // input [5 : 0] B
.D(plus_or_minus[i] == 1'b0 ? din_array[i*3+2] : -din_array[i*3+2]), // input [8 : 0] D
.P(layer_1_2[i]) // output [14 : 0] P
);
end
for(i = 0; i < 3; i = i + 1)
begin:layer2// (1, 4, 7)*kernel + pre-result
xbip_dsp48_macro_macc_l3 macc_ABC (//A*B+C, latency 3
.CLK(clk), // input CLK
.A(layer_1_2_buf[i*3+2]), // input [8 : 0] A
.B(kernel_array[i*3+1]), // input [5 : 0] B
.C(layer_1_2[i]), // input [14 : 0] C
.P(layer_2_3[i]) // output [15 : 0] P
);
end
endgenerate
integer j;
always@(posedge clk) begin
if( resetn == 1'b0 ) begin
layer_valid <= 0;
for(j = 0; j < 9; j = j + 1)begin
layer_1_2_buf[j] <= 9'b0;
end
for(j = 0; j < 2; j = j + 1)begin
layer_3_4[j] <= 16'b0;
end
layer_4_5 <= 16'b0;
layer_5_end <= 16'b0;
end
else begin
//layer 1 buffer for 1 4 7
for(j = 0; j < 3; j = j + 1) begin
layer_1_2_buf[j*3] <= din_array[j*3+1];
layer_1_2_buf[j*3+1] <= layer_1_2_buf[j*3];
layer_1_2_buf[j*3+2] <= layer_1_2_buf[j*3+1];
end
//adder tree
//layer 3
layer_3_4[0] <= layer_2_3[0] + layer_2_3[1];
layer_3_4[1] <= layer_2_3[2];
//layer 4
layer_4_5 <= layer_3_4[0] + layer_3_4[1];
//layer 5
layer_5_end <= layer_4_5;
//layer_valid <= {layer_valid, din_valid};
layer_valid <= {layer_valid, din_valid};
/*layer_valid[0] <= din_valid;
for(j = 1; j < latency; j = j + 1)begin
layer_valid[j] <= layer_valid[j-1];
end*/
end
end
endmodule
|
/*
Filename : UART.v
Compiler : Quartus II
Description : UART TX Send Data and RX Receive Data
Modules : UART_TX...input clk; //系统时钟
input rst;
input [7:0]DATA; //发送数据
input EN; //使能信号
output reg TX; //发送数据
output reg STATUS; //TX状态，高时空闲
output reg END; //TX发送完毕，有一个高电平脉冲
//发送TX时启动波特率发生器
UART_RX...input clk; //系统时钟
input RX; //接受数据
input rst;
output reg [7:0]DATA; //8位数据存储
output reg STATUS; //RX接受完毕，有一个高电平脉冲
BaudGen... input clk; //系统时钟,27MHz
input start; //开始信号
input rst;
output reg clk_9600;//9600Hz脉冲
Attention : clk should be 27MHz
Author : Yeoman Zhuang
Release : *
*/
module UART_TX(
input clk, rst, EN,
input [7:0]DATA,
output reg TX,STATUS,END
);
wire clk_9600; //发送时钟
BaudGen TXbg(.clk(clk),
.clk_9600(clk_9600),
.start(~STATUS),
.rst(rst));
reg [3:0]TX_num;
reg [7:0]TX_DATA;
initial
begin
TX<=1'b1;
STATUS<=1;
END<=0;
TX_num<=4'h0;
end
always @(posedge clk or posedge rst) begin
if (rst) begin
// reset
STATUS<=1;
TX_DATA<=8'h00;
end else if (EN) begin //检测到EN信号
TX_DATA<=DATA;
STATUS<=0;
end else if (TX_num==4'hA) begin
STATUS<=1;
end
end
always @(posedge clk or posedge rst) begin//发送数据
if (rst) begin
// reset
TX<=1'b1;
TX_num<=0;
END<=1'b0;
end
else if (clk_9600&&(~STATUS)) begin
TX_num<=TX_num+4'h1;
case(TX_num)
4'h0: TX<=1'b0; //起始位
4'h1: TX<=TX_DATA[0];
4'h2: TX<=TX_DATA[1];
4'h3: TX<=TX_DATA[2];
4'h4: TX<=TX_DATA[3];
4'h5: TX<=TX_DATA[4];
4'h6: TX<=TX_DATA[5];
4'h7: TX<=TX_DATA[6];
4'h8: begin
TX<=TX_DATA[7];
END<=1'b1;
end
4'h9: TX<=1'b1;
default: ;
endcase
end
else if (TX_num==4'hA) begin
TX_num<=4'h0;
TX<=1'b1;
end
else END<=0;
end
endmodule
module UART_RX(
input clk, rst, RX,
output reg [7:0]DATA,
output reg STATUS
);
wire clk_9600; //中间采样点
reg start; //接受RX时启动波特率发生器
reg [7:0]temp_DATA;
reg [3:0]RX_num; //接受字节数
BaudGen RXbg(.clk(clk),
.clk_9600(clk_9600),
.start(start),
.rst(rst));
always @(posedge clk or posedge rst) begin
if (rst) begin
// reset
start<=1'b0;
end
else if (~RX) begin
start<=1'b1; //开启波特率发生器//开始接受
end
else if (RX_num==4'hA)begin
start<=1'b0; //关闭波特率发生器
end
end
always @(posedge clk or posedge rst) begin
if (rst) begin
// reset
STATUS<=0;
DATA<=8'h00;
temp_DATA<=8'h00;
RX_num<=4'h0;
end
else if (clk_9600&&start) begin
RX_num<=RX_num+4'h1;
case(RX_num)
4'h1: temp_DATA[0] <= RX;
4'h2: temp_DATA[1] <= RX;
4'h3: temp_DATA[2] <= RX;
4'h4: temp_DATA[3] <= RX;
4'h5: temp_DATA[4] <= RX;
4'h6: temp_DATA[5] <= RX;
4'h7: temp_DATA[6] <= RX;
4'h8: temp_DATA[7] <= RX;
default: ;
endcase
end
else if(RX_num==4'hA)begin
RX_num<=0;
STATUS<=1;
DATA<=temp_DATA;
end
else STATUS<=0;
end
endmodule
module BaudGen(
input clk, start, rst,
output reg clk_9600
);
// clk should be 27MHz
// start, rst, 高电平有效
// 产生9600Hz脉冲
input rst;
input start;
input clk;
output reg clk_9600;
reg [15:0]state;
initial
begin
clk_9600 <= 0;
state <= 0;
end
always@(posedge clk or posedge rst) begin
// Counter, period is 1/9600s
if(rst) begin
state<=0;
end
else if(state==2812 || !start) begin//2812
state<=0;
end
else begin
state<=state+16'd1;
end
end
always @(posedge clk or posedge rst) begin
// generate 50%-duty 9600Hz clock, half the counter
if (rst) begin
clk_9600<=0;
end
else if (state==1406) begin//1406
clk_9600<=1;
end
else begin
clk_9600<=0;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S15_FUNCTIONAL_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S15_FUNCTIONAL_V
/**
* clkdlybuf4s15: Clock Delay Buffer 4-stage 0.15um length inner stage
* gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__clkdlybuf4s15 (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S15_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SEDFXBP_1_V
`define SKY130_FD_SC_HS__SEDFXBP_1_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Verilog wrapper for sedfxbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__sedfxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sedfxbp_1 (
Q ,
Q_N ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
sky130_fd_sc_hs__sedfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sedfxbp_1 (
Q ,
Q_N,
CLK,
D ,
DE ,
SCD,
SCE
);
output Q ;
output Q_N;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__sedfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__SEDFXBP_1_V
|
//-----------------------------------------------------------------------------
// (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Filename: axi_traffic_gen_v2_0_7_systeminit_dmg.v
// Version : v1.0
// Description: Rd/wr command generator
// various features/status of the core.
// Verilog-Standard:verilog-2001
//---------------------------------------------------------------------------
`timescale 1ps/1ps
`include "axi_traffic_gen_v2_0_7_defines.v"
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_traffic_gen_v2_0_7_systeminit_dmg
# (
parameter C_FAMILY = "virtex7" ,
parameter C_ATG_MIF_ADDR_BITS = 4 ,// 4(16),5(32),6(64),7(128),8(256)
parameter C_ATG_MIF_DATA_DEPTH = 16 ,// 4(16),5(32),6(64),7(128),8(256)
parameter C_ATG_MIF = "atg_init.mif"
) (
input [C_ATG_MIF_ADDR_BITS-1 : 0] a ,
input clk ,
input qspo_srst ,
output [31 : 0] qspo
);
//wire [31:0] rom_matrix[255:0] ;
//reg [31:0] qspo_i;
//assign rom_matrix[0] = {32'h81111111};
//assign rom_matrix[1] = {32'h82222222};
//assign rom_matrix[2] = {32'h73333333};
//assign rom_matrix[3] = {32'h84444444};
//assign rom_matrix[4] = {32'h85555555};
//assign rom_matrix[5] = {32'h86666666};
//assign rom_matrix[6] = {32'h87777777};
//assign rom_matrix[7] = {32'h88888888};
//assign rom_matrix[8] = {32'h89999999};
//assign rom_matrix[9] = {32'h80000000};
//assign rom_matrix[10] = {32'h8aaaaaaa};
//assign rom_matrix[11] = {32'h8bbbbbbb};
//assign rom_matrix[12] = {32'h8ccccccc};
//assign rom_matrix[13] = {32'h8ddddddd};
//assign rom_matrix[14] = {32'h0fffffff};
//assign rom_matrix[15] = {32'h8fffffff};
//assign rom_matrix[16] = {32'h23232323};
//assign rom_matrix[17] = {32'h11111111};
//assign rom_matrix[18] = {32'h22222222};
//assign rom_matrix[19] = {32'h33333333};
//assign rom_matrix[20] = {32'h44444444};
//assign rom_matrix[21] = {32'h55555555};
//assign rom_matrix[22] = {32'hffffffff};
//assign rom_matrix[23] = {32'h66666666};
//assign rom_matrix[24] = {32'h77777777};
//assign rom_matrix[25] = {32'h88888888};
//assign rom_matrix[26] = {32'h99999999};
//assign rom_matrix[27] = {32'haaaaaaaa};
//assign rom_matrix[28] = {32'hbbbbbbbb};
//assign rom_matrix[29] = {32'hcccccccc};
//assign rom_matrix[30] = {32'hdddddddd};
//assign rom_matrix[31] = {32'heeeeeeee};
//always @(posedge clk) begin
// if(qspo_srst == 1'b1) begin
// qspo_i <= 32'h0;
// end else begin
// qspo_i <= rom_matrix[a];
// end
//end
// assign qspo = qspo_i;
dist_mem_gen_v8_0_9 #(
.C_ADDR_WIDTH (C_ATG_MIF_ADDR_BITS ),
.C_DEFAULT_DATA ("0" ),
.C_DEPTH (C_ATG_MIF_DATA_DEPTH),
.C_FAMILY (C_FAMILY ),
.C_HAS_CLK (1 ),
.C_HAS_D (0 ),
.C_HAS_DPO (0 ),
.C_HAS_DPRA (0 ),
.C_HAS_I_CE (0 ),
.C_HAS_QDPO (0 ),
.C_HAS_QDPO_CE (0 ),
.C_HAS_QDPO_CLK (0 ),
.C_HAS_QDPO_RST (0 ),
.C_HAS_QDPO_SRST (0 ),
.C_HAS_QSPO (1 ),
.C_HAS_QSPO_CE (0 ),
.C_HAS_QSPO_RST (0 ),
.C_HAS_QSPO_SRST (1 ),
.C_HAS_SPO (0 ),
.C_HAS_WE (0 ),
.C_MEM_INIT_FILE (C_ATG_MIF ),
.C_MEM_TYPE (0 ),
.C_PARSER_TYPE (1 ),
.C_PIPELINE_STAGES(0 ),
.C_QCE_JOINED (0 ),
.C_QUALIFY_WE (0 ),
.C_READ_MIF (1 ),
.C_REG_A_D_INPUTS (0 ),
.C_REG_DPRA_INPUT (0 ),
.C_SYNC_ENABLE (1 ),
.C_WIDTH (32 )
)
inst (
.a (a ),
.clk (clk ),
.qspo_srst(qspo_srst ),
.qspo (qspo ),
//Default out/inputs
.d (32'h0 ),
.dpra ({C_ATG_MIF_ADDR_BITS{1'b0}}),
.we (1'b0 ),
.i_ce (1'b0 ),
.qspo_ce (1'b0 ),
.qdpo_ce (1'b0 ),
.qdpo_clk (1'b0 ),
.qspo_rst (1'b0 ),
.qdpo_rst (1'b0 ),
.qdpo_srst(1'b0 ),
.spo ( ),
.dpo ( ),
.qdpo ( )
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_DFF_PS_PP_PG_N_SYMBOL_V
`define SKY130_FD_SC_HDLL__UDP_DFF_PS_PP_PG_N_SYMBOL_V
/**
* udp_dff$PS_pp$PG$N: Positive edge triggered D flip-flop with active
* high
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__udp_dff$PS_pp$PG$N (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_DFF_PS_PP_PG_N_SYMBOL_V
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2014, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//
//-------------------------------------------------------------------
//
// Filename : fme_interpolator_8pel.v
// Author : Yufeng Bai
// Email : [email protected]
//
// $Id$
//
//-------------------------------------------------------------------
`include "enc_defines.v"
module fme_interpolator_8pel (
ref_pel0_i ,
ref_pel1_i ,
ref_pel2_i ,
ref_pel3_i ,
ref_pel4_i ,
ref_pel5_i ,
ref_pel6_i ,
ref_pel7_i ,
ref_pel8_i ,
ref_pel9_i ,
ref_pel10_i ,
ref_pel11_i ,
ref_pel12_i ,
ref_pel13_i ,
ref_pel14_i ,
ref_pel15_i ,
half_buf_0 ,
half_buf_1 ,
half_buf_2 ,
half_buf_3 ,
half_buf_4 ,
half_buf_5 ,
half_buf_6 ,
half_buf_7 ,
half_buf_8 ,
q1_buf_0 ,
q1_buf_1 ,
q1_buf_2 ,
q1_buf_3 ,
q1_buf_4 ,
q1_buf_5 ,
q1_buf_6 ,
q1_buf_7 ,
q1_buf_8 ,
q3_buf_0 ,
q3_buf_1 ,
q3_buf_2 ,
q3_buf_3 ,
q3_buf_4 ,
q3_buf_5 ,
q3_buf_6 ,
q3_buf_7 ,
q3_buf_8 ,
hhalf_pel0_o ,
hhalf_pel1_o ,
hhalf_pel2_o ,
hhalf_pel3_o ,
hhalf_pel4_o ,
hhalf_pel5_o ,
hhalf_pel6_o ,
hhalf_pel7_o ,
hhalf_pel8_o
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input [`PIXEL_WIDTH-1:0] ref_pel0_i ; // ref_pel0
input [`PIXEL_WIDTH-1:0] ref_pel1_i ; // ref_pel1
input [`PIXEL_WIDTH-1:0] ref_pel2_i ; // ref_pel2
input [`PIXEL_WIDTH-1:0] ref_pel3_i ; // ref_pel3
input [`PIXEL_WIDTH-1:0] ref_pel4_i ; // ref_pel4
input [`PIXEL_WIDTH-1:0] ref_pel5_i ; // ref_pel5
input [`PIXEL_WIDTH-1:0] ref_pel6_i ; // ref_pel6
input [`PIXEL_WIDTH-1:0] ref_pel7_i ; // ref_pel7
input [`PIXEL_WIDTH-1:0] ref_pel8_i ; // ref_pel8
input [`PIXEL_WIDTH-1:0] ref_pel9_i ; // ref_pel9
input [`PIXEL_WIDTH-1:0] ref_pel10_i ; // ref_pel10
input [`PIXEL_WIDTH-1:0] ref_pel11_i ; // ref_pel11
input [`PIXEL_WIDTH-1:0] ref_pel12_i ; // ref_pel12
input [`PIXEL_WIDTH-1:0] ref_pel13_i ; // ref_pel13
input [`PIXEL_WIDTH-1:0] ref_pel14_i ; // ref_pel14
input [`PIXEL_WIDTH-1:0] ref_pel15_i ; // ref_pel15
output [2*`PIXEL_WIDTH-1:0] half_buf_0 ; // 9 pixels 16 bits/pixel
output [2*`PIXEL_WIDTH-1:0] half_buf_1 ; // 9 pixels 16 bits/pixel
output [2*`PIXEL_WIDTH-1:0] half_buf_2 ; // 9 pixels 16 bits/pixel
output [2*`PIXEL_WIDTH-1:0] half_buf_3 ; // 9 pixels 16 bits/pixel
output [2*`PIXEL_WIDTH-1:0] half_buf_4 ; // 9 pixels 16 bits/pixel
output [2*`PIXEL_WIDTH-1:0] half_buf_5 ; // 9 pixels 16 bits/pixel
output [2*`PIXEL_WIDTH-1:0] half_buf_6 ; // 9 pixels 16 bits/pixel
output [2*`PIXEL_WIDTH-1:0] half_buf_7 ; // 9 pixels 16 bits/pixel
output [2*`PIXEL_WIDTH-1:0] half_buf_8 ; // 9 pixels 16 bits/pixel
output [2*`PIXEL_WIDTH-1:0] q1_buf_0 ; // 9 pixels 16 bits/pixel
output [2*`PIXEL_WIDTH-1:0] q3_buf_0 ; // 9 pixels 16 bits/pixel
output [2*`PIXEL_WIDTH-1:0] q1_buf_1 ; // 9 pixels 16 bits/pixel
output [2*`PIXEL_WIDTH-1:0] q3_buf_1 ; // 9 pixels 16 bits/pixel
output [2*`PIXEL_WIDTH-1:0] q1_buf_2 ; // 9 pixels 16 bits/pixel
output [2*`PIXEL_WIDTH-1:0] q3_buf_2 ; // 9 pixels 16 bits/pixel
output [2*`PIXEL_WIDTH-1:0] q1_buf_3 ; // 9 pixels 16 bits/pixel
output [2*`PIXEL_WIDTH-1:0] q3_buf_3 ; // 9 pixels 16 bits/pixel
output [2*`PIXEL_WIDTH-1:0] q1_buf_4 ; // 9 pixels 16 bits/pixel
output [2*`PIXEL_WIDTH-1:0] q3_buf_4 ; // 9 pixels 16 bits/pixel
output [2*`PIXEL_WIDTH-1:0] q1_buf_5 ; // 9 pixels 16 bits/pixel
output [2*`PIXEL_WIDTH-1:0] q3_buf_5 ; // 9 pixels 16 bits/pixel
output [2*`PIXEL_WIDTH-1:0] q1_buf_6 ; // 9 pixels 16 bits/pixel
output [2*`PIXEL_WIDTH-1:0] q3_buf_6 ; // 9 pixels 16 bits/pixel
output [2*`PIXEL_WIDTH-1:0] q1_buf_7 ; // 9 pixels 16 bits/pixel
output [2*`PIXEL_WIDTH-1:0] q3_buf_7 ; // 9 pixels 16 bits/pixel
output [2*`PIXEL_WIDTH-1:0] q1_buf_8 ; // 9 pixels 16 bits/pixel
output [2*`PIXEL_WIDTH-1:0] q3_buf_8 ; // 9 pixels 16 bits/pixel
output [`PIXEL_WIDTH-1:0] hhalf_pel0_o ; // cliped half pixel 0
output [`PIXEL_WIDTH-1:0] hhalf_pel1_o ; // cliped half pixel 1
output [`PIXEL_WIDTH-1:0] hhalf_pel2_o ; // cliped half pixel 2
output [`PIXEL_WIDTH-1:0] hhalf_pel3_o ; // cliped half pixel 3
output [`PIXEL_WIDTH-1:0] hhalf_pel4_o ; // cliped half pixel 4
output [`PIXEL_WIDTH-1:0] hhalf_pel5_o ; // cliped half pixel 5
output [`PIXEL_WIDTH-1:0] hhalf_pel6_o ; // cliped half pixel 6
output [`PIXEL_WIDTH-1:0] hhalf_pel7_o ; // cliped half pixel 7
output [`PIXEL_WIDTH-1:0] hhalf_pel8_o ; // cliped half pixel 8
// ********************************************
//
// Sub Module DECLARATION
//
// ********************************************
// half interpolator
fme_interpolator #(
.TYPE(0),
.HOR(1),
.LAST(0),
.IN_EXPAND(0), // interpolator input : 8 bits
.OUT_EXPAND(1)
) horizontal_half_0 (
.tap_0_i( ref_pel0_i ) ,
.tap_1_i( ref_pel1_i ) ,
.tap_2_i( ref_pel2_i ) ,
.tap_3_i( ref_pel3_i ) ,
.tap_4_i( ref_pel4_i ) ,
.tap_5_i( ref_pel5_i ) ,
.tap_6_i( ref_pel6_i ) ,
.tap_7_i( ref_pel7_i ) ,
.val_o ( half_buf_0 )
);
fme_interpolator #(
.TYPE(0),
.HOR(1),
.LAST(0),
.IN_EXPAND(0), // interpolator input : 8 bits
.OUT_EXPAND(1)
) horizontal_half_1 (
.tap_0_i( ref_pel1_i ) ,
.tap_1_i( ref_pel2_i ) ,
.tap_2_i( ref_pel3_i ) ,
.tap_3_i( ref_pel4_i ) ,
.tap_4_i( ref_pel5_i ) ,
.tap_5_i( ref_pel6_i ) ,
.tap_6_i( ref_pel7_i ) ,
.tap_7_i( ref_pel8_i ) ,
.val_o ( half_buf_1 )
);
fme_interpolator #(
.TYPE(0),
.HOR(1),
.LAST(0),
.IN_EXPAND(0), // interpolator input : 8 bits
.OUT_EXPAND(1)
) horizontal_half_2 (
.tap_0_i( ref_pel2_i ) ,
.tap_1_i( ref_pel3_i ) ,
.tap_2_i( ref_pel4_i ) ,
.tap_3_i( ref_pel5_i ) ,
.tap_4_i( ref_pel6_i ) ,
.tap_5_i( ref_pel7_i ) ,
.tap_6_i( ref_pel8_i ) ,
.tap_7_i( ref_pel9_i ) ,
.val_o ( half_buf_2 )
);
fme_interpolator #(
.TYPE(0),
.HOR(1),
.LAST(0),
.IN_EXPAND(0), // interpolator input : 8 bits
.OUT_EXPAND(1)
) horizontal_half_3 (
.tap_0_i( ref_pel3_i ) ,
.tap_1_i( ref_pel4_i ) ,
.tap_2_i( ref_pel5_i ) ,
.tap_3_i( ref_pel6_i ) ,
.tap_4_i( ref_pel7_i ) ,
.tap_5_i( ref_pel8_i ) ,
.tap_6_i( ref_pel9_i ) ,
.tap_7_i( ref_pel10_i ) ,
.val_o ( half_buf_3 )
);
fme_interpolator #(
.TYPE(0),
.HOR(1),
.LAST(0),
.IN_EXPAND(0), // interpolator input : 8 bits
.OUT_EXPAND(1)
) horizontal_half_4 (
.tap_0_i( ref_pel4_i ) ,
.tap_1_i( ref_pel5_i ) ,
.tap_2_i( ref_pel6_i ) ,
.tap_3_i( ref_pel7_i ) ,
.tap_4_i( ref_pel8_i ) ,
.tap_5_i( ref_pel9_i ) ,
.tap_6_i( ref_pel10_i ) ,
.tap_7_i( ref_pel11_i ) ,
.val_o ( half_buf_4 )
);
fme_interpolator #(
.TYPE(0),
.HOR(1),
.LAST(0),
.IN_EXPAND(0), // interpolator input : 8 bits
.OUT_EXPAND(1)
) horizontal_half_5 (
.tap_0_i( ref_pel5_i ) ,
.tap_1_i( ref_pel6_i ) ,
.tap_2_i( ref_pel7_i ) ,
.tap_3_i( ref_pel8_i ) ,
.tap_4_i( ref_pel9_i ) ,
.tap_5_i( ref_pel10_i ) ,
.tap_6_i( ref_pel11_i ) ,
.tap_7_i( ref_pel12_i ) ,
.val_o ( half_buf_5 )
);
fme_interpolator #(
.TYPE(0),
.HOR(1),
.LAST(0),
.IN_EXPAND(0), // interpolator input : 8 bits
.OUT_EXPAND(1)
) horizontal_half_6 (
.tap_0_i( ref_pel6_i ) ,
.tap_1_i( ref_pel7_i ) ,
.tap_2_i( ref_pel8_i ) ,
.tap_3_i( ref_pel9_i ) ,
.tap_4_i( ref_pel10_i ) ,
.tap_5_i( ref_pel11_i ) ,
.tap_6_i( ref_pel12_i ) ,
.tap_7_i( ref_pel13_i ) ,
.val_o ( half_buf_6 )
);
fme_interpolator #(
.TYPE(0),
.HOR(1),
.LAST(0),
.IN_EXPAND(0), // interpolator input : 8 bits
.OUT_EXPAND(1)
) horizontal_half_7 (
.tap_0_i( ref_pel7_i ) ,
.tap_1_i( ref_pel8_i ) ,
.tap_2_i( ref_pel9_i ) ,
.tap_3_i( ref_pel10_i ) ,
.tap_4_i( ref_pel11_i ) ,
.tap_5_i( ref_pel12_i ) ,
.tap_6_i( ref_pel13_i ) ,
.tap_7_i( ref_pel14_i ) ,
.val_o ( half_buf_7 )
);
fme_interpolator #(
.TYPE(0),
.HOR(1),
.LAST(0),
.IN_EXPAND(0), // interpolator input : 8 bits
.OUT_EXPAND(1)
) horizontal_half_8 (
.tap_0_i( ref_pel8_i ) ,
.tap_1_i( ref_pel9_i ) ,
.tap_2_i( ref_pel10_i ) ,
.tap_3_i( ref_pel11_i ) ,
.tap_4_i( ref_pel12_i ) ,
.tap_5_i( ref_pel13_i ) ,
.tap_6_i( ref_pel14_i ) ,
.tap_7_i( ref_pel15_i ) ,
.val_o ( half_buf_8 )
);
// 1/4 interpolator
fme_interpolator #(
.TYPE(1),
.HOR(1),
.LAST(0),
.IN_EXPAND(0), // interpolator input : 8 bits
.OUT_EXPAND(1)
) horizontal_q1_0 (
.tap_0_i( ref_pel0_i ) ,
.tap_1_i( ref_pel1_i ) ,
.tap_2_i( ref_pel2_i ) ,
.tap_3_i( ref_pel3_i ) ,
.tap_4_i( ref_pel4_i ) ,
.tap_5_i( ref_pel5_i ) ,
.tap_6_i( ref_pel6_i ) ,
.tap_7_i( ref_pel7_i ) ,
.val_o ( q1_buf_0 )
);
fme_interpolator #(
.TYPE(1),
.HOR(1),
.LAST(0),
.IN_EXPAND(0), // interpolator input : 8 bits
.OUT_EXPAND(1)
) horizontal_q1_1 (
.tap_0_i( ref_pel1_i ) ,
.tap_1_i( ref_pel2_i ) ,
.tap_2_i( ref_pel3_i ) ,
.tap_3_i( ref_pel4_i ) ,
.tap_4_i( ref_pel5_i ) ,
.tap_5_i( ref_pel6_i ) ,
.tap_6_i( ref_pel7_i ) ,
.tap_7_i( ref_pel8_i ) ,
.val_o ( q1_buf_1 )
);
fme_interpolator #(
.TYPE(1),
.HOR(1),
.LAST(0),
.IN_EXPAND(0), // interpolator input : 8 bits
.OUT_EXPAND(1)
) horizontal_q1_2 (
.tap_0_i( ref_pel2_i ) ,
.tap_1_i( ref_pel3_i ) ,
.tap_2_i( ref_pel4_i ) ,
.tap_3_i( ref_pel5_i ) ,
.tap_4_i( ref_pel6_i ) ,
.tap_5_i( ref_pel7_i ) ,
.tap_6_i( ref_pel8_i ) ,
.tap_7_i( ref_pel9_i ) ,
.val_o ( q1_buf_2 )
);
fme_interpolator #(
.TYPE(1),
.HOR(1),
.LAST(0),
.IN_EXPAND(0), // interpolator input : 8 bits
.OUT_EXPAND(1)
) horizontal_q1_3 (
.tap_0_i( ref_pel3_i ) ,
.tap_1_i( ref_pel4_i ) ,
.tap_2_i( ref_pel5_i ) ,
.tap_3_i( ref_pel6_i ) ,
.tap_4_i( ref_pel7_i ) ,
.tap_5_i( ref_pel8_i ) ,
.tap_6_i( ref_pel9_i ) ,
.tap_7_i( ref_pel10_i ) ,
.val_o ( q1_buf_3 )
);
fme_interpolator #(
.TYPE(1),
.HOR(1),
.LAST(0),
.IN_EXPAND(0), // interpolator input : 8 bits
.OUT_EXPAND(1)
) horizontal_q1_4 (
.tap_0_i( ref_pel4_i ) ,
.tap_1_i( ref_pel5_i ) ,
.tap_2_i( ref_pel6_i ) ,
.tap_3_i( ref_pel7_i ) ,
.tap_4_i( ref_pel8_i ) ,
.tap_5_i( ref_pel9_i ) ,
.tap_6_i( ref_pel10_i ) ,
.tap_7_i( ref_pel11_i ) ,
.val_o ( q1_buf_4 )
);
fme_interpolator #(
.TYPE(1),
.HOR(1),
.LAST(0),
.IN_EXPAND(0), // interpolator input : 8 bits
.OUT_EXPAND(1)
) horizontal_q1_5 (
.tap_0_i( ref_pel5_i ) ,
.tap_1_i( ref_pel6_i ) ,
.tap_2_i( ref_pel7_i ) ,
.tap_3_i( ref_pel8_i ) ,
.tap_4_i( ref_pel9_i ) ,
.tap_5_i( ref_pel10_i ) ,
.tap_6_i( ref_pel11_i ) ,
.tap_7_i( ref_pel12_i ) ,
.val_o ( q1_buf_5 )
);
fme_interpolator #(
.TYPE(1),
.HOR(1),
.LAST(0),
.IN_EXPAND(0), // interpolator input : 8 bits
.OUT_EXPAND(1)
) horizontal_q1_6 (
.tap_0_i( ref_pel6_i ) ,
.tap_1_i( ref_pel7_i ) ,
.tap_2_i( ref_pel8_i ) ,
.tap_3_i( ref_pel9_i ) ,
.tap_4_i( ref_pel10_i ) ,
.tap_5_i( ref_pel11_i ) ,
.tap_6_i( ref_pel12_i ) ,
.tap_7_i( ref_pel13_i ) ,
.val_o ( q1_buf_6 )
);
fme_interpolator #(
.TYPE(1),
.HOR(1),
.LAST(0),
.IN_EXPAND(0), // interpolator input : 8 bits
.OUT_EXPAND(1)
) horizontal_q1_7 (
.tap_0_i( ref_pel7_i ) ,
.tap_1_i( ref_pel8_i ) ,
.tap_2_i( ref_pel9_i ) ,
.tap_3_i( ref_pel10_i ) ,
.tap_4_i( ref_pel11_i ) ,
.tap_5_i( ref_pel12_i ) ,
.tap_6_i( ref_pel13_i ) ,
.tap_7_i( ref_pel14_i ) ,
.val_o ( q1_buf_7 )
);
fme_interpolator #(
.TYPE(1),
.HOR(1),
.LAST(0),
.IN_EXPAND(0), // interpolator input : 8 bits
.OUT_EXPAND(1)
) horizontal_q1_8 (
.tap_0_i( ref_pel8_i ) ,
.tap_1_i( ref_pel9_i ) ,
.tap_2_i( ref_pel10_i ) ,
.tap_3_i( ref_pel11_i ) ,
.tap_4_i( ref_pel12_i ) ,
.tap_5_i( ref_pel13_i ) ,
.tap_6_i( ref_pel14_i ) ,
.tap_7_i( ref_pel15_i ) ,
.val_o ( q1_buf_8 )
);
// 3/4 interpolator
fme_interpolator #(
.TYPE(2),
.HOR(1),
.LAST(0),
.IN_EXPAND(0), // interpolator input : 8 bits
.OUT_EXPAND(1)
) horizontal_q3_0 (
.tap_0_i( ref_pel0_i ) ,
.tap_1_i( ref_pel1_i ) ,
.tap_2_i( ref_pel2_i ) ,
.tap_3_i( ref_pel3_i ) ,
.tap_4_i( ref_pel4_i ) ,
.tap_5_i( ref_pel5_i ) ,
.tap_6_i( ref_pel6_i ) ,
.tap_7_i( ref_pel7_i ) ,
.val_o ( q3_buf_0 )
);
fme_interpolator #(
.TYPE(2),
.HOR(1),
.LAST(0),
.IN_EXPAND(0), // interpolator input : 8 bits
.OUT_EXPAND(1)
) horizontal_q3_1 (
.tap_0_i( ref_pel1_i ) ,
.tap_1_i( ref_pel2_i ) ,
.tap_2_i( ref_pel3_i ) ,
.tap_3_i( ref_pel4_i ) ,
.tap_4_i( ref_pel5_i ) ,
.tap_5_i( ref_pel6_i ) ,
.tap_6_i( ref_pel7_i ) ,
.tap_7_i( ref_pel8_i ) ,
.val_o ( q3_buf_1 )
);
fme_interpolator #(
.TYPE(2),
.HOR(1),
.LAST(0),
.IN_EXPAND(0), // interpolator input : 8 bits
.OUT_EXPAND(1)
) horizontal_q3_2 (
.tap_0_i( ref_pel2_i ) ,
.tap_1_i( ref_pel3_i ) ,
.tap_2_i( ref_pel4_i ) ,
.tap_3_i( ref_pel5_i ) ,
.tap_4_i( ref_pel6_i ) ,
.tap_5_i( ref_pel7_i ) ,
.tap_6_i( ref_pel8_i ) ,
.tap_7_i( ref_pel9_i ) ,
.val_o ( q3_buf_2 )
);
fme_interpolator #(
.TYPE(2),
.HOR(1),
.LAST(0),
.IN_EXPAND(0), // interpolator input : 8 bits
.OUT_EXPAND(1)
) horizontal_q3_3 (
.tap_0_i( ref_pel3_i ) ,
.tap_1_i( ref_pel4_i ) ,
.tap_2_i( ref_pel5_i ) ,
.tap_3_i( ref_pel6_i ) ,
.tap_4_i( ref_pel7_i ) ,
.tap_5_i( ref_pel8_i ) ,
.tap_6_i( ref_pel9_i ) ,
.tap_7_i( ref_pel10_i ) ,
.val_o ( q3_buf_3 )
);
fme_interpolator #(
.TYPE(2),
.HOR(1),
.LAST(0),
.IN_EXPAND(0), // interpolator input : 8 bits
.OUT_EXPAND(1)
) horizontal_q3_4 (
.tap_0_i( ref_pel4_i ) ,
.tap_1_i( ref_pel5_i ) ,
.tap_2_i( ref_pel6_i ) ,
.tap_3_i( ref_pel7_i ) ,
.tap_4_i( ref_pel8_i ) ,
.tap_5_i( ref_pel9_i ) ,
.tap_6_i( ref_pel10_i ) ,
.tap_7_i( ref_pel11_i ) ,
.val_o ( q3_buf_4 )
);
fme_interpolator #(
.TYPE(2),
.HOR(1),
.LAST(0),
.IN_EXPAND(0), // interpolator input : 8 bits
.OUT_EXPAND(1)
) horizontal_q3_5 (
.tap_0_i( ref_pel5_i ) ,
.tap_1_i( ref_pel6_i ) ,
.tap_2_i( ref_pel7_i ) ,
.tap_3_i( ref_pel8_i ) ,
.tap_4_i( ref_pel9_i ) ,
.tap_5_i( ref_pel10_i ) ,
.tap_6_i( ref_pel11_i ) ,
.tap_7_i( ref_pel12_i ) ,
.val_o ( q3_buf_5 )
);
fme_interpolator #(
.TYPE(2),
.HOR(1),
.LAST(0),
.IN_EXPAND(0), // interpolator input : 8 bits
.OUT_EXPAND(1)
) horizontal_q3_6 (
.tap_0_i( ref_pel6_i ) ,
.tap_1_i( ref_pel7_i ) ,
.tap_2_i( ref_pel8_i ) ,
.tap_3_i( ref_pel9_i ) ,
.tap_4_i( ref_pel10_i ) ,
.tap_5_i( ref_pel11_i ) ,
.tap_6_i( ref_pel12_i ) ,
.tap_7_i( ref_pel13_i ) ,
.val_o ( q3_buf_6 )
);
fme_interpolator #(
.TYPE(2),
.HOR(1),
.LAST(0),
.IN_EXPAND(0), // interpolator input : 8 bits
.OUT_EXPAND(1)
) horizontal_q3_7 (
.tap_0_i( ref_pel7_i ) ,
.tap_1_i( ref_pel8_i ) ,
.tap_2_i( ref_pel9_i ) ,
.tap_3_i( ref_pel10_i ) ,
.tap_4_i( ref_pel11_i ) ,
.tap_5_i( ref_pel12_i ) ,
.tap_6_i( ref_pel13_i ) ,
.tap_7_i( ref_pel14_i ) ,
.val_o ( q3_buf_7 )
);
fme_interpolator #(
.TYPE(2),
.HOR(1),
.LAST(0),
.IN_EXPAND(0), // interpolator input : 8 bits
.OUT_EXPAND(1)
) horizontal_q3_8 (
.tap_0_i( ref_pel8_i ) ,
.tap_1_i( ref_pel9_i ) ,
.tap_2_i( ref_pel10_i ) ,
.tap_3_i( ref_pel11_i ) ,
.tap_4_i( ref_pel12_i ) ,
.tap_5_i( ref_pel13_i ) ,
.tap_6_i( ref_pel14_i ) ,
.tap_7_i( ref_pel15_i ) ,
.val_o ( q3_buf_8 )
);
//clip
clip2 clip_half_0 (
.val_in(half_buf_0),
.val_out(hhalf_pel0_o)
);
clip2 clip_half_1 (
.val_in(half_buf_1),
.val_out(hhalf_pel1_o)
);
clip2 clip_half_2 (
.val_in(half_buf_2),
.val_out(hhalf_pel2_o)
);
clip2 clip_half_3 (
.val_in(half_buf_3),
.val_out(hhalf_pel3_o)
);
clip2 clip_half_4 (
.val_in(half_buf_4),
.val_out(hhalf_pel4_o)
);
clip2 clip_half_5 (
.val_in(half_buf_5),
.val_out(hhalf_pel5_o)
);
clip2 clip_half_6 (
.val_in(half_buf_6),
.val_out(hhalf_pel6_o)
);
clip2 clip_half_7 (
.val_in(half_buf_7),
.val_out(hhalf_pel7_o)
);
clip2 clip_half_8 (
.val_in(half_buf_8),
.val_out(hhalf_pel8_o)
);
// ********************************************
//
// Combinational Logic
//
// ********************************************
// ********************************************
//
// Sequential Logic
//
// ********************************************
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:21:34 03/13/2015
// Design Name:
// Module Name: serializer_gen_test
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module serializer_gen_test (
output [7:0] data,
output send,
output clk
);
reg [7:0] data_buf;
reg send_buf;
reg clk_buf;
assign clk = clk_buf;
assign send = send_buf;
assign data = data_buf;
integer data_src;
integer i;
integer j;
initial
begin
data_buf = 0;
clk_buf = 0;
send_buf = 0;
data_src = $fopen("test_serializer/data/in_parallel_vector.txt", "rb");
#100;
for(i = 0; i < 16; i = i + 1)
begin
clk_buf = 0;
#2;
clk_buf = 1;
#1;
data_buf = $fgetc(data_src);
#1;
clk_buf = 0;
#1;
send_buf = 1;
#1;
clk_buf = 1;
#1;
send_buf = 0;
#1;
for(j = 0; j < 10; j = j + 1)
begin
clk_buf = 0;
#2;
clk_buf = 1;
#2;
end
end
clk_buf = 0;
#2;
clk_buf = 1;
#2;
$fclose(data_src);
end
endmodule
|
/*!
* <b>Module:</b>condition_mux
* @file condition_mux.v
* @date 2016-12-08
* @author auto-generated file, see ahci_fsm_sequence.py
* @brief Select condition
*/
`timescale 1ns/1ps
module condition_mux (
input clk,
input ce, // enable recording all conditions
input [ 7:0] sel,
output condition,
input ST_NB_ND,
input PXCI0_NOT_CMDTOISSUE,
input PCTI_CTBAR_XCZ,
input PCTI_XCZ,
input NST_D2HR,
input NPD_NCA,
input CHW_DMAA,
input SCTL_DET_CHANGED_TO_4,
input SCTL_DET_CHANGED_TO_1,
input PXSSTS_DET_NE_3,
input PXSSTS_DET_EQ_1,
input NPCMD_FRE,
input FIS_OK,
input FIS_ERR,
input FIS_FERR,
input FIS_EXTRA,
input FIS_FIRST_INVALID,
input FR_D2HR,
input FIS_DATA,
input FIS_ANY,
input NB_ND_D2HR_PIO,
input D2HR,
input SDB,
input DMA_ACT,
input DMA_SETUP,
input BIST_ACT_FE,
input BIST_ACT,
input PIO_SETUP,
input NB_ND,
input TFD_STS_ERR,
input FIS_I,
input PIO_I,
input NPD,
input PIOX,
input XFER0,
input PIOX_XFER0,
input CTBAA_CTBAP,
input CTBAP,
input CTBA_B,
input CTBA_C,
input TX_ERR,
input SYNCESC_ERR,
input DMA_PRD_IRQ_PEND,
input X_RDY_COLLISION);
wire [44:0] masked;
reg [43:0] registered;
reg [ 5:0] cond_r;
assign condition = |cond_r;
assign masked[ 0] = registered[ 0] && sel[ 2] && sel[ 1] && sel[ 0];
assign masked[ 1] = registered[ 1] && sel[ 3] && sel[ 1] && sel[ 0];
assign masked[ 2] = registered[ 2] && sel[ 4] && sel[ 1] && sel[ 0];
assign masked[ 3] = registered[ 3] && sel[ 5] && sel[ 1] && sel[ 0];
assign masked[ 4] = registered[ 4] && sel[ 6] && sel[ 1] && sel[ 0];
assign masked[ 5] = registered[ 5] && sel[ 7] && sel[ 1] && sel[ 0];
assign masked[ 6] = registered[ 6] && sel[ 3] && sel[ 2] && sel[ 0];
assign masked[ 7] = registered[ 7] && sel[ 4] && sel[ 2] && sel[ 0];
assign masked[ 8] = registered[ 8] && sel[ 5] && sel[ 2] && sel[ 0];
assign masked[ 9] = registered[ 9] && sel[ 6] && sel[ 2] && sel[ 0];
assign masked[10] = registered[10] && sel[ 7] && sel[ 2] && sel[ 0];
assign masked[11] = registered[11] && sel[ 4] && sel[ 3] && sel[ 0];
assign masked[12] = registered[12] && sel[ 5] && sel[ 3] && sel[ 0];
assign masked[13] = registered[13] && sel[ 6] && sel[ 3] && sel[ 0];
assign masked[14] = registered[14] && sel[ 7] && sel[ 3] && sel[ 0];
assign masked[15] = registered[15] && sel[ 5] && sel[ 4] && sel[ 0];
assign masked[16] = registered[16] && sel[ 6] && sel[ 4] && sel[ 0];
assign masked[17] = registered[17] && sel[ 7] && sel[ 4] && sel[ 0];
assign masked[18] = registered[18] && sel[ 6] && sel[ 5] && sel[ 0];
assign masked[19] = registered[19] && sel[ 7] && sel[ 5] && sel[ 0];
assign masked[20] = registered[20] && sel[ 7] && sel[ 6] && sel[ 0];
assign masked[21] = registered[21] && sel[ 3] && sel[ 2] && sel[ 1];
assign masked[22] = registered[22] && sel[ 4] && sel[ 2] && sel[ 1];
assign masked[23] = registered[23] && sel[ 5] && sel[ 2] && sel[ 1];
assign masked[24] = registered[24] && sel[ 6] && sel[ 2] && sel[ 1];
assign masked[25] = registered[25] && sel[ 7] && sel[ 2] && sel[ 1];
assign masked[26] = registered[26] && sel[ 4] && sel[ 3] && sel[ 1];
assign masked[27] = registered[27] && sel[ 5] && sel[ 3] && sel[ 1];
assign masked[28] = registered[28] && sel[ 6] && sel[ 3] && sel[ 1];
assign masked[29] = registered[29] && sel[ 7] && sel[ 3] && sel[ 1];
assign masked[30] = registered[30] && sel[ 5] && sel[ 4] && sel[ 1];
assign masked[31] = registered[31] && sel[ 6] && sel[ 4] && sel[ 1];
assign masked[32] = registered[32] && sel[ 7] && sel[ 4] && sel[ 1];
assign masked[33] = registered[33] && sel[ 6] && sel[ 5] && sel[ 1];
assign masked[34] = registered[34] && sel[ 7] && sel[ 5] && sel[ 1];
assign masked[35] = registered[35] && sel[ 7] && sel[ 6] && sel[ 1];
assign masked[36] = registered[36] && sel[ 4] && sel[ 3] && sel[ 2];
assign masked[37] = registered[37] && sel[ 5] && sel[ 3] && sel[ 2];
assign masked[38] = registered[38] && sel[ 6] && sel[ 3] && sel[ 2];
assign masked[39] = registered[39] && sel[ 7] && sel[ 3] && sel[ 2];
assign masked[40] = registered[40] && sel[ 5] && sel[ 4] && sel[ 2];
assign masked[41] = registered[41] && sel[ 6] && sel[ 4] && sel[ 2];
assign masked[42] = registered[42] && sel[ 7] && sel[ 4] && sel[ 2];
assign masked[43] = registered[43] && sel[ 6] && sel[ 5] && sel[ 2];
assign masked[44] = !(|sel); // always TRUE condition (sel ==0)
always @(posedge clk) begin
if (ce) begin
registered[ 0] <= ST_NB_ND;
registered[ 1] <= PXCI0_NOT_CMDTOISSUE;
registered[ 2] <= PCTI_CTBAR_XCZ;
registered[ 3] <= PCTI_XCZ;
registered[ 4] <= NST_D2HR;
registered[ 5] <= NPD_NCA;
registered[ 6] <= CHW_DMAA;
registered[ 7] <= SCTL_DET_CHANGED_TO_4;
registered[ 8] <= SCTL_DET_CHANGED_TO_1;
registered[ 9] <= PXSSTS_DET_NE_3;
registered[10] <= PXSSTS_DET_EQ_1;
registered[11] <= NPCMD_FRE;
registered[12] <= FIS_OK;
registered[13] <= FIS_ERR;
registered[14] <= FIS_FERR;
registered[15] <= FIS_EXTRA;
registered[16] <= FIS_FIRST_INVALID;
registered[17] <= FR_D2HR;
registered[18] <= FIS_DATA;
registered[19] <= FIS_ANY;
registered[20] <= NB_ND_D2HR_PIO;
registered[21] <= D2HR;
registered[22] <= SDB;
registered[23] <= DMA_ACT;
registered[24] <= DMA_SETUP;
registered[25] <= BIST_ACT_FE;
registered[26] <= BIST_ACT;
registered[27] <= PIO_SETUP;
registered[28] <= NB_ND;
registered[29] <= TFD_STS_ERR;
registered[30] <= FIS_I;
registered[31] <= PIO_I;
registered[32] <= NPD;
registered[33] <= PIOX;
registered[34] <= XFER0;
registered[35] <= PIOX_XFER0;
registered[36] <= CTBAA_CTBAP;
registered[37] <= CTBAP;
registered[38] <= CTBA_B;
registered[39] <= CTBA_C;
registered[40] <= TX_ERR;
registered[41] <= SYNCESC_ERR;
registered[42] <= DMA_PRD_IRQ_PEND;
registered[43] <= X_RDY_COLLISION;
end
cond_r[ 0] <= |masked[ 7: 0];
cond_r[ 1] <= |masked[15: 8];
cond_r[ 2] <= |masked[23:16];
cond_r[ 3] <= |masked[31:24];
cond_r[ 4] <= |masked[39:32];
cond_r[ 5] <= |masked[44:40];
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:27:45 02/22/2015
// Design Name:
// Module Name: NormaliseAdder
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module NormaliseAdderProcess(
input [31:0] z_postAddState,
input [3:0] Opcode_AddState,
input idle_AddState,
input [31:0] sout_AddState,
input [27:0] sum_AddState,
input [7:0] InsTagAdder,
input clock,
output reg idle_NormaliseSum,
output reg [31:0] sout_NormaliseSum,
output reg [27:0] sum_NormaliseSum,
output reg [3:0] Opcode_NormaliseSum,
output reg [31:0] z_postNormaliseSum,
output reg [7:0] InsTagNormaliseAdder
);
parameter no_idle = 1'b0,
put_idle = 1'b1;
wire [7:0] s_exponent;
assign s_exponent = sout_AddState[30:23];
parameter sin_cos = 4'd0,
sinh_cosh = 4'd1,
arctan = 4'd2,
arctanh = 4'd3,
exp = 4'd4,
sqr_root = 4'd5, // Pre processed input is given 4'd11
// This requires pre processing. x = (a+1)/2 and y = (a-1)/2
division = 4'd6,
tan = 4'd7, // This is iterative. sin_cos followed by division.
tanh = 4'd8, // This is iterative. sinh_cosh followed by division.
nat_log = 4'd9, // This requires pre processing. x = (a+1) and y = (a-1)
hypotenuse = 4'd10,
PreProcess = 4'd11;
always @ (posedge clock)
begin
InsTagNormaliseAdder <= InsTagAdder;
z_postNormaliseSum <= z_postAddState;
Opcode_NormaliseSum <= Opcode_AddState;
//if(Opcode_AddState == PreProcess) begin
idle_NormaliseSum <= idle_AddState;
if (idle_AddState != put_idle) begin
sout_NormaliseSum[31] <= sout_AddState[31];
sout_NormaliseSum[22:0] <= sout_AddState[22:0];
if (sum_AddState[27] == 1'b1) begin
sout_NormaliseSum[30:23] <= s_exponent + 1;
sum_NormaliseSum <= sum_AddState >> 1;
end
else if(sum_AddState[26:3] == 24'h000000) begin
sout_NormaliseSum[30:23] <= 10'h382;
end
else if (sum_AddState[26:4] == 23'h000000) begin
sout_NormaliseSum[30:23] <= s_exponent - 23;
sum_NormaliseSum <= sum_AddState << 23;
end
else if (sum_AddState[26:5] == 22'h000000) begin
sout_NormaliseSum[30:23] <= s_exponent - 22;
sum_NormaliseSum <= sum_AddState << 22;
end
else if (sum_AddState[26:6] == 21'h000000) begin
sout_NormaliseSum[30:23] <= s_exponent - 21;
sum_NormaliseSum <= sum_AddState << 21;
end
else if (sum_AddState[26:7] == 20'h00000) begin
sout_NormaliseSum[30:23] <= s_exponent - 20;
sum_NormaliseSum <= sum_AddState << 20;
end
else if (sum_AddState[26:8] == 19'h00000) begin
sout_NormaliseSum[30:23] <= s_exponent - 19;
sum_NormaliseSum <= sum_AddState << 19;
end
else if (sum_AddState[26:9] == 18'h00000) begin
sout_NormaliseSum[30:23] <= s_exponent - 18;
sum_NormaliseSum <= sum_AddState << 18;
end
else if (sum_AddState[26:10] == 17'h00000) begin
sout_NormaliseSum[30:23] <= s_exponent - 17;
sum_NormaliseSum <= sum_AddState << 17;
end
else if (sum_AddState[26:11] == 16'h0000) begin
sout_NormaliseSum[30:23] <= s_exponent - 16;
sum_NormaliseSum <= sum_AddState << 16;
end
else if (sum_AddState[26:12] == 15'h0000) begin
sout_NormaliseSum[30:23] <= s_exponent - 15;
sum_NormaliseSum <= sum_AddState << 15;
end
else if (sum_AddState[26:13] == 14'h0000) begin
sout_NormaliseSum[30:23] <= s_exponent - 14;
sum_NormaliseSum <= sum_AddState << 14;
end
else if (sum_AddState[26:14] == 13'h0000) begin
sout_NormaliseSum[30:23] <= s_exponent - 13;
sum_NormaliseSum <= sum_AddState << 13;
end
else if (sum_AddState[26:15] == 12'h000) begin
sout_NormaliseSum[30:23] <= s_exponent - 12;
sum_NormaliseSum <= sum_AddState << 12;
end
else if (sum_AddState[26:16] == 11'h000) begin
sout_NormaliseSum[30:23] <= s_exponent - 11;
sum_NormaliseSum <= sum_AddState << 11;
end
else if (sum_AddState[26:17] == 10'h000) begin
sout_NormaliseSum[30:23] <= s_exponent - 10;
sum_NormaliseSum <= sum_AddState << 10;
end
else if (sum_AddState[26:18] == 9'h0000) begin
sout_NormaliseSum[30:23] <= s_exponent - 9;
sum_NormaliseSum <= sum_AddState << 9;
end
else if (sum_AddState[26:19] == 8'h00) begin
sout_NormaliseSum[30:23] <= s_exponent - 8;
sum_NormaliseSum <= sum_AddState << 8;
end
else if (sum_AddState[26:20] == 7'h00) begin
sout_NormaliseSum[30:23] <= s_exponent - 7;
sum_NormaliseSum <= sum_AddState << 7;
end
else if (sum_AddState[26:21] == 6'h00) begin
sout_NormaliseSum[30:23] <= s_exponent - 6;
sum_NormaliseSum <= sum_AddState << 6;
end
else if (sum_AddState[26:22] == 5'h00) begin
sout_NormaliseSum[30:23] <= s_exponent - 5;
sum_NormaliseSum <= sum_AddState << 5;
end
else if (sum_AddState[26:23] == 4'h0) begin
sout_NormaliseSum[30:23] <= s_exponent - 4;
sum_NormaliseSum <= sum_AddState << 4;
end
else if (sum_AddState[26:24] == 3'h0) begin
sout_NormaliseSum[30:23] <= s_exponent - 3;
sum_NormaliseSum <= sum_AddState << 3;
end
else if (sum_AddState[26:25] == 2'h0) begin
sout_NormaliseSum[30:23] <= s_exponent - 2;
sum_NormaliseSum <= sum_AddState << 2;
end
else if (sum_AddState[26] == 1'h0) begin
sout_NormaliseSum[30:23] <= s_exponent - 1;
sum_NormaliseSum <= sum_AddState << 1;
end
else begin
sout_NormaliseSum[30:23] <= s_exponent;
sum_NormaliseSum <= sum_AddState;
end
end
else begin
sout_NormaliseSum <= sout_AddState;
sum_NormaliseSum <= 0;
end
//end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND3_BEHAVIORAL_V
`define SKY130_FD_SC_MS__AND3_BEHAVIORAL_V
/**
* and3: 3-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__and3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, C, A, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND3_BEHAVIORAL_V |
// MBT 4/1/2014
//
// 2 read-port, 1 write-port ram
//
// reads are asynchronous
//
`define bsg_mem_2r1w_macro(words,bits) \
if (els_p == words && width_p == bits) \
begin: macro \
wire [els_p-1:0] wa_one_hot = (w_v_i << w_addr_i); \
wire [els_p-1:0] ra_one_hot0 = (r0_v_i << r0_addr_i); \
wire [els_p-1:0] ra_one_hot1 = (r1_v_i << r1_addr_i); \
\
bsg_rp_tsmc_40_rf_w``words``_b``bits``_2r1w w``words``_b``bits \
( .clock_i(w_clk_i) \
,.data_i(w_data_i) \
,.write_sel_one_hot_i(wa_one_hot) \
,.read_sel_one_hot_i ({ra_one_hot1,ra_one_hot0}) \
,.data_o({r1_data_o,r0_data_o}) \
); \
end
module bsg_mem_2r1w #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=$clog2(els_p)
)
(input w_clk_i
, input w_reset_i
, input w_v_i
, input [addr_width_lp-1:0] w_addr_i
, input [width_p-1:0] w_data_i
, input r0_v_i
, input [addr_width_lp-1:0] r0_addr_i
, output logic [width_p-1:0] r0_data_o
, input r1_v_i
, input [addr_width_lp-1:0] r1_addr_i
, output logic [width_p-1:0] r1_data_o
);
`bsg_mem_2r1w_macro(32,32)
else
begin: notmacro
bsg_mem_2r1w_synth
#(.width_p(width_p)
,.els_p(els_p)
,.read_write_same_addr_p(read_write_same_addr_p)
) synth
(.*);
end
// synopsys translate_off
always_ff @(posedge w_clk_i)
if (w_v_i)
begin
assert (w_addr_i < els_p)
else $error("Invalid address %x to %m of size %x\n", w_addr_i, els_p);
assert (~(r0_addr_i == w_addr_i && w_v_i && r0_v_i && !read_write_same_addr_p))
else $error("%m: Attempt to read and write same address");
assert (~(r1_addr_i == w_addr_i && w_v_i && r1_v_i && !read_write_same_addr_p))
else $error("%m: Attempt to read and write same address");
end
initial
begin
$display("## %L: instantiating width_p=%d, els_p=%d, read_write_same_addr_p=%d (%m)",width_p,els_p,read_write_same_addr_p);
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_2r1w)
|
//============================================================
//
// Hsiang-Yi Chung
// March 2016
//
// This is the top level of the radar dsp module
//
//============================================================
module Radar_top(
input clk,
input reset_n,
input [11:0] adc_in,
output [11:0] mag_out1,
output [11:0] mag_out2,
output next_data,
output data,
output clk_div_16,
//for debugging
output fft_next_out,
output [11:0] avg_out1,
output [11:0] avg_out2,
output [11:0] win_out1,
output [11:0] win_out2,
input fft_next,
input fft_reset
);
wire clk_div_32, win_next, reset_fft;
clk_div clk_div_inst (.clk(clk), .clk_div_16(clk_div_16), .clk_div_32(clk_div_32));
windowing window_inst(.in1(avg_out1), .in2(avg_out2), .clk(clk_div_16),
.out1(win_out1), .out2(win_out2), .next(win_next), .fft_reset(reset_fft));
FFT_Mag fft_inst(.clk(clk_div_32), .reset(reset_fft), .next(win_next),
.X0(win_out1), .X1(0), .X2(win_out2), .X3(0),
.mag1(mag_out1), .mag2(mag_out2), .next_out(fft_next_out));
Average_Filter avg_filter_inst(.in(adc_in), .clk(clk), .reset_n(reset_n),
.out1(avg_out1), .out2(avg_out2));
SerialInterface serialInterface_inst(.clk(clk_div_16), .next_out(fft_next_out), .reset_n(reset_n),
.fft_out1(mag_out1), .fft_out2(mag_out2), .next_data(next_data), .data(data));
endmodule
|
//////////////////////////////////////////////////////////////////
// //
// Wishbone wrapper for vscale/riscv core //
// //
// //
// Description //
// This file wraps the vscale/riscv core to work with the //
// existing opencores/openrisc cores and ecosystem. //
// //
// Author(s): //
// - Hesham Almatary, [email protected] //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2015 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
`include "vscale_ctrl_constants.vh"
`include "vscale_alu_ops.vh"
`include "rv32_opcodes.vh"
`include "vscale_csr_addr_map.vh"
`include "vscale_md_constants.vh"
`include "vscale_platform_constants.vh"
module wb_vscale (
input clk,
input rst,
input [`N_EXT_INTS-1:0] ext_interrupts,
// Wishbone interface
output [31:0] iwbm_adr_o,
output iwbm_stb_o,
output iwbm_cyc_o,
output [3:0] iwbm_sel_o,
output iwbm_we_o,
output [2:0] iwbm_cti_o,
output [1:0] iwbm_bte_o,
output [31:0] iwbm_dat_o,
input iwbm_err_i,
input iwbm_ack_i,
input [31:0] iwbm_dat_i,
input iwbm_rty_i,
output [31:0] dwbm_adr_o,
output dwbm_stb_o,
output dwbm_cyc_o,
output [3:0] dwbm_sel_o,
output dwbm_we_o,
output [2:0] dwbm_cti_o,
output [1:0] dwbm_bte_o,
output [31:0] dwbm_dat_o,
input dwbm_err_i,
input dwbm_ack_i,
input [31:0] dwbm_dat_i,
input dwbm_rty_i
);
wire dmem_request;
wire dmem_we;
wire [31:0] dmem_addr;
wire [31:0] data_wire;
wire [2:0] dmem_size;
wire [31:0] pc;
wire replay_IF_out;
reg iwbm_riscv_cyc = 0;
reg iwbm_riscv_stb = 0;
reg [31:0] instruction = 0;
reg [31:0] iwbm_riscv_adr = 0;
reg dwbm_riscv_cyc = 0;
reg dwbm_riscv_stb = 0;
reg [2:0] dwbm_riscv_cti = 7;
reg [1:0] dwbm_riscv_bte = 2;
reg [3:0] dwbm_riscv_sel = 4'hF;
reg [31:0] dwbm_riscv_dat = 0;
reg dwbm_riscv_we = 0;
reg [31:0] mem_read_value = 0;
reg [31:0] dwbm_riscv_adr = 0;
reg [2:0] state = 0;
reg [2:0] dstate = 0;
reg [31:0] ddata = 0;
reg dmem_wait = 0;
reg imem_wait = 1;
reg previous_dmem_access = 0;
reg [1:0] kill_wishbone_ireq = 0;
reg cpu_start = 0;
assign iwbm_stb_o = iwbm_riscv_stb;
assign iwbm_cyc_o = iwbm_riscv_cyc;
assign iwbm_cti_o = 0;
assign iwbm_bte_o = 0;
assign iwbm_sel_o = 4'hf;
assign iwbm_we_o = 0;
assign iwbm_adr_o = iwbm_riscv_adr;
assign dwbm_stb_o = dwbm_riscv_stb;
assign dwbm_cyc_o = dwbm_riscv_cyc;
assign dwbm_cti_o = dwbm_riscv_cti;
assign dwbm_bte_o = dwbm_riscv_bte;
assign dwbm_sel_o = dwbm_riscv_sel;
assign dwbm_we_o = dwbm_riscv_we;
assign dwbm_adr_o = dwbm_riscv_adr;
always @(posedge clk)
begin
if(rst)
begin
state <= 3;
instruction <= 0;
iwbm_riscv_adr <= 0;
kill_wishbone_ireq <= 0;
imem_wait <= 1;
end
/* initalize */
if(state == 3)
begin
// iwbm_riscv_adr <= 32'hf0000000;
iwbm_riscv_adr <= 32'h00000000;
iwbm_riscv_cyc <= 1;
iwbm_riscv_stb <= 1;
state <= 2;
end
case (state)
1: begin
iwbm_riscv_adr <= (kill_wishbone_ireq)? pc - 4 : pc;
iwbm_riscv_cyc <= 1;
iwbm_riscv_stb <= 1;
state <= 2;
imem_wait <= 1;
// kill_wishbone_ireq <= (kill_wishbone_ireq[0])? 2 : 0;
end
2: begin
/* Kill wb imem request if jal(r)/branch taken. Avoid reset case */
// if(replay_IF_out && !rst && iwbm_riscv_adr != 32'hf0000000)
if(!rst && iwbm_riscv_adr != 32'h00000000)
begin
iwbm_riscv_adr <= pc;
instruction <= iwbm_dat_i;
iwbm_riscv_cyc <= 0;
iwbm_riscv_stb <= 0;
kill_wishbone_ireq <= 1;
state <= 1;
imem_wait <= 1;
end
// if((iwbm_ack_i) && !replay_IF_out) /*|| kill_wishbone_ireq == 2*/
if(iwbm_ack_i) /*|| kill_wishbone_ireq == 2*/
begin
instruction <= iwbm_dat_i;
kill_wishbone_ireq <= 0;
iwbm_riscv_cyc <= 0;
iwbm_riscv_stb <= 0;
state <=1;
imem_wait <= 0;
end
end
endcase
end // always
always @(posedge clk)
begin
if(rst)
begin
dstate <= 1;
dwbm_riscv_we <= 0;
dwbm_riscv_cyc <= 0;
dwbm_riscv_stb <= 0;
dwbm_riscv_cti <= 7;
dwbm_riscv_bte <= 2;
dwbm_riscv_sel <= 4'hF;
mem_read_value <= 0;
dwbm_riscv_adr <= 0;
dmem_wait <= 0;
end
/* Mem Write Operation */
if((dmem_request && dmem_we) || (dstate == 2 && dwbm_riscv_we))
begin
case(dstate)
1: begin
dwbm_riscv_adr <= dmem_addr;
dwbm_riscv_we <= dmem_we;
//dwbm_riscv_sel <= (dmem_size == 0)? 4'h8 : (dmem_size == 1)? 4'hC : (dmem_size == 2)? 4'hF : 4'hF;
dwbm_riscv_sel <= (dmem_size == 0)? (1 << dmem_addr[1:0]) : (dmem_size == 1)? 4'h3 : (dmem_size == 2)? 4'hF : 4'hF;
//dwbm_riscv_sel <= (dmem_size == 0)? 4'h1 : (dmem_size == 1)? 4'h3 : (dmem_size == 2)? 4'hF : 4'hF;
dwbm_riscv_cyc <= 1;
dwbm_riscv_stb <= 1;
dmem_wait <= 1;
dstate <=2;
end
2: begin
if(dwbm_ack_i)
begin
dwbm_riscv_cyc <= 0;
dwbm_riscv_stb <= 0;
dwbm_riscv_we <= 0;
dmem_wait <= 0;
dstate <= 1;
end
end
endcase
end
/* Mem Read Operation */
if((dmem_request && !dmem_we) || (dstate == 2 && !dwbm_riscv_we) || dstate == 3)
begin
case(dstate)
1: begin
dwbm_riscv_adr <= dmem_addr;
dwbm_riscv_stb <= 1;
dwbm_riscv_cyc <= 1;
dmem_wait <= 1;
//dwbm_riscv_sel <= (dmem_size == 0)? 4'h8 : (dmem_size == 1)? 4'hC : (dmem_size == 2)? 4'hF : 4'hF;
dwbm_riscv_sel <= (dmem_size == 0 || dmem_size == 4)? 1 :
(dmem_size == 1 || dmem_size == 5)? 4'h3 : (dmem_size == 2)? 4'hF : 4'hF;
//dwbm_riscv_sel <= (dmem_size == 0)? 4'h1 : (dmem_size == 1)? 4'h3 : (dmem_size == 2)? 4'hF : 4'hF;
dstate <= 2;
end
2: begin
if(dwbm_ack_i)
begin
dwbm_riscv_cyc <= 0;
dwbm_riscv_stb <= 0;
dstate <= 3;
dwbm_riscv_dat <= dwbm_dat_i;
previous_dmem_access <= 1;
end
end
3: begin
dmem_wait <= 0;
dstate <= 1;
end
endcase
end
end
vscale_pipeline vscale_core (
.clk(clk),
.reset(rst),
.ext_interrupts(ext_interrupts),
.imem_wait(imem_wait),
.imem_addr(pc),
.imem_rdata(instruction),
.imem_badmem_e(iwbm_err_i),
//.replay_IF_out(replay_IF_out),
.dmem_wait(dmem_wait),
.dmem_en(dmem_request),
.dmem_wen(dmem_we),
.dmem_size(dmem_size),
.dmem_addr(dmem_addr),
.dmem_wdata_delayed(dwbm_dat_o),
.dmem_rdata(dwbm_riscv_dat),
.dmem_badmem_e(1'b0) /* TODO */
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_FUNCTIONAL_V
`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_FUNCTIONAL_V
/**
* lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__lpflow_clkinvkapwr (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S18_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__CLKDLYBUF4S18_PP_BLACKBOX_V
/**
* clkdlybuf4s18: Clock Delay Buffer 4-stage 0.18um length inner stage
* gates.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__clkdlybuf4s18 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S18_PP_BLACKBOX_V
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_di_buffer_wrap(
clock,
data,
rdaddress,
wraddress,
wren,
q,
clear);
parameter DATA_WIDTH = 18;
parameter READ_DATA_SIZE = 9;
parameter WRITE_TO_READ_RATIO_2_EXPONENT = 2;
parameter WRITE_TO_READ_RATIO = 1;
parameter ADDR_WIDTH = 2;
parameter NUM_WORDS = 16;
input clock;
input [DATA_WIDTH-1:0] data;
input [ADDR_WIDTH - 1 : 0] rdaddress;
input [ADDR_WIDTH-1:0] wraddress;
input wren;
output [READ_DATA_SIZE - 1 : 0] q;
input clear;
wire [DATA_WIDTH-1:0] q_wire;
wire wren_gated;
wire [ADDR_WIDTH + ADDR_WIDTH - WRITE_TO_READ_RATIO_2_EXPONENT - 1 : 0] rdaddress_tmp = {{ADDR_WIDTH{1'b0}}, rdaddress[ADDR_WIDTH-1 : WRITE_TO_READ_RATIO_2_EXPONENT]};
assign wren_gated = (wraddress >= NUM_WORDS) ? 1'b0 : wren;
rw_manager_di_buffer rw_manager_di_buffer_i(
.clock(clock),
.data(data),
.rdaddress(rdaddress_tmp[ADDR_WIDTH-1 : 0]),
.wraddress(wraddress),
.wren(wren_gated),
.q(q_wire),
.clear(clear));
defparam rw_manager_di_buffer_i.DATA_WIDTH = DATA_WIDTH;
defparam rw_manager_di_buffer_i.ADDR_WIDTH = ADDR_WIDTH;
defparam rw_manager_di_buffer_i.NUM_WORDS = NUM_WORDS;
generate
if(WRITE_TO_READ_RATIO_2_EXPONENT > 0) begin
wire [WRITE_TO_READ_RATIO * READ_DATA_SIZE + DATA_WIDTH - 1 : 0] datain_tmp = {{(WRITE_TO_READ_RATIO * READ_DATA_SIZE){1'b0}}, q_wire};
rw_manager_datamux rw_manager_datamux_i(
.datain(datain_tmp[WRITE_TO_READ_RATIO*READ_DATA_SIZE-1:0]),
.sel(rdaddress[WRITE_TO_READ_RATIO_2_EXPONENT - 1 : 0]),
.dataout(q)
);
defparam rw_manager_datamux_i.DATA_WIDTH = READ_DATA_SIZE;
defparam rw_manager_datamux_i.SELECT_WIDTH = WRITE_TO_READ_RATIO_2_EXPONENT;
defparam rw_manager_datamux_i.NUMBER_OF_CHANNELS = WRITE_TO_READ_RATIO;
end
else begin
assign q = q_wire;
end
endgenerate
endmodule
|
module pipeline_ctrl(
clk, RST, // clk e reset
A_addr, // endereco dos registradores decodificados no pipe 2
B_addr,
ctrl, // indica operacao a ser executada (ainda nao foi pro pipeline 3)
ctrl_p34, // ctrl pipe 3-4
ctrl_p45, // ctrl pipe 4-5
reg_en_p52, // enable reg pipe 5-2
reg_addr_p34, // controle de hazards - ADDR
reg_addr_p45,
reg_addr_p52,
reg_dataA_p2, // controle de hazards - selecao de dados - dados em p2
reg_dataB_p2,
reg_data_p34, // data entre p3-4
imm_data_p34, // data entre p3-4 (immediato)
reg_data_p45, // data entre p4-5
reg_data_p52, // data entre p5-2
muxA_data, // saida dos multiplexadores - entrada de p3
muxB_data
);
// faz o include dos parameters das instrucoes
`include "params_proc.v"
// input output
input clk, RST;
input [REG_ADDR_WIDTH-1:0] A_addr, B_addr;
input [CTRL_WIDTH-1:0] ctrl, ctrl_p34, ctrl_p45;
input reg_en_p52;
input [REG_ADDR_WIDTH-1:0] reg_addr_p34, reg_addr_p45, reg_addr_p52;
input signed [DATA_WIDTH-1:0] reg_dataA_p2, reg_dataB_p2, reg_data_p34, imm_data_p34, reg_data_p45, reg_data_p52;
output reg signed [DATA_WIDTH-1:0] muxA_data, muxB_data;
// TODO controle dos hazards do processador
// usando como informacao :
// input [CTRL_WIDTH-1:0] ctrl;
// input [REG_ADDR_WIDTH-1:0] A_addr (reg_addrA_p23), B_addr (reg_addrB_p23), reg_addr_p34, reg_addr_p45, reg_addr_p52;
// input signed [DATA_WIDTH-1:0] reg_dataA_p2, reg_dataB_p2, reg_data_p34, reg_data_p45, reg_data_p52;
// gerando como saida:
// output reg signed [DATA_WIDTH-1:0] muxA_data, muxB_data;
always @(*) begin
// por default coloque o mux (input do p3)
// com os dados do p2
muxA_data = reg_dataA_p2;
muxB_data = reg_dataB_p2;
if (ctrl_p34 == LW_IMM) begin
muxA_data = imm_data_p34;
end else if (A_addr == reg_addr_p34 && ctrl_p34 != NOP) begin
// atualize os dados que chegam em p3 para os dados que estao entre p3-4
muxA_data = reg_data_p34;
end else if (A_addr == reg_addr_p45 && ctrl_p45 != NOP) begin
// atualize os dados que chegam em p3 para os dados que estao entre p4-5
muxA_data = reg_data_p45;
end else if (A_addr == reg_addr_p52 && reg_en_p52 == 1) begin
// atualize os dados que chegam em p3 para os dados que estao entre p5-2
muxA_data = reg_data_p52;
end
if (B_addr == reg_addr_p34 && ctrl_p34 != NOP) begin
// atualize os dados que chegam em p3 para os dados que estao entre p3-4
muxB_data = reg_data_p34;
end else if (B_addr == reg_addr_p45 && ctrl_p45 != NOP) begin
// atualize os dados que chegam em p3 para os dados que estao entre p4-5
muxB_data = reg_data_p45;
end else if (B_addr == reg_addr_p52 && reg_en_p52 == 1) begin
// atualize os dados que chegam em p3 para os dados que estao entre p5-2
muxB_data = reg_data_p52;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISO0P_PP_SYMBOL_V
`define SKY130_FD_SC_LP__ISO0P_PP_SYMBOL_V
/**
* iso0p: ????.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__iso0p (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP,
input KAPWR,
input VPB ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISO0P_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O311AI_1_V
`define SKY130_FD_SC_MS__O311AI_1_V
/**
* o311ai: 3-input OR into 3-input NAND.
*
* Y = !((A1 | A2 | A3) & B1 & C1)
*
* Verilog wrapper for o311ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o311ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o311ai_1 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o311ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o311ai_1 (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o311ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O311AI_1_V
|
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