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// Copyright (c) 2014 Takashi Toyoshima <[email protected]>.
// All rights reserved. Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
`timescale 100ps/100ps
module ShifterTest;
wire [7:0] w_data;
wire w_n;
wire w_z;
wire w_c;
reg [7:0] r_data;
reg r_rotate;
reg r_right;
reg r_c;
reg clk;
MC6502Shifter dut(
.i_data (r_data ),
.i_rotate(r_rotate),
.i_right (r_right ),
.i_c (r_c ),
.o_data (w_data ),
.o_n (w_n ),
.o_z (w_z ),
.o_c (w_c ));
always #1 clk = !clk;
always @ (posedge clk) begin
$display({ "result %04b_%04b, c=%b, rotate=%b, right=%b => ",
"%04b_%04b, n=%b, z=%b, c=%b" },
r_data[7:4], r_data[3:0], r_c, r_rotate, r_right,
w_data[7:4], w_data[3:0], w_n, w_z, w_c);
end
initial begin
$dumpfile("Shifter.vcd");
$dumpvars(0, dut);
clk <= 1'b0;
r_data <= 8'h00;
r_rotate <= 1'b0;
r_right <= 1'b0;
r_c <= 1'b0;
#2
r_data <= 8'h80;
#2
r_data <= 8'h41;
#2
r_c <= 1'b1;
#2
r_rotate <= 1'b1;
#2
r_data <= 8'h80;
#2
r_right <= 1'b1;
#2
r_c <= 1'b0;
#2
r_rotate <= 1'b0;
#2
r_c <= 1'b1;
#2
r_data <= 8'h01;
#2
$finish;
end
endmodule // ShifterTest
|
//////////////////////////////////////////////////////////////////////
//// ////
//// hostSlaveMux.v ////
//// ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
//// Controls the select line for the mux that enables the sharing
//// of a single SerialInterfaceEgine between the hostController
//// and slaveController
//// Also a dumping area for any features common to host and slave
//// operation. That is reset control and version number report.
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
module hostSlaveMux (
SIEPortCtrlInToSIE,
SIEPortCtrlInFromHost,
SIEPortCtrlInFromSlave,
SIEPortDataInToSIE,
SIEPortDataInFromHost,
SIEPortDataInFromSlave,
SIEPortWEnToSIE,
SIEPortWEnFromHost,
SIEPortWEnFromSlave,
fullSpeedPolarityToSIE,
fullSpeedPolarityFromHost,
fullSpeedPolarityFromSlave,
fullSpeedBitRateToSIE,
fullSpeedBitRateFromHost,
fullSpeedBitRateFromSlave,
noActivityTimeOutEnableToSIE,
noActivityTimeOutEnableFromHost,
noActivityTimeOutEnableFromSlave,
dataIn,
dataOut,
address,
writeEn,
strobe_i,
busClk,
usbClk,
hostSlaveMuxSel,
rstFromWire,
rstSyncToBusClkOut,
rstSyncToUsbClkOut
);
output [7:0] SIEPortCtrlInToSIE;
input [7:0] SIEPortCtrlInFromHost;
input [7:0] SIEPortCtrlInFromSlave;
output [7:0] SIEPortDataInToSIE;
input [7:0] SIEPortDataInFromHost;
input [7:0] SIEPortDataInFromSlave;
output SIEPortWEnToSIE;
input SIEPortWEnFromHost;
input SIEPortWEnFromSlave;
output fullSpeedPolarityToSIE;
input fullSpeedPolarityFromHost;
input fullSpeedPolarityFromSlave;
output fullSpeedBitRateToSIE;
input fullSpeedBitRateFromHost;
input fullSpeedBitRateFromSlave;
output noActivityTimeOutEnableToSIE;
input noActivityTimeOutEnableFromHost;
input noActivityTimeOutEnableFromSlave;
//hostSlaveMuxBI
input [7:0] dataIn;
input address;
input writeEn;
input strobe_i;
input busClk;
input usbClk;
input rstFromWire;
output rstSyncToBusClkOut;
output rstSyncToUsbClkOut;
output [7:0] dataOut;
input hostSlaveMuxSel;
reg [7:0] SIEPortCtrlInToSIE;
wire [7:0] SIEPortCtrlInFromHost;
wire [7:0] SIEPortCtrlInFromSlave;
reg [7:0] SIEPortDataInToSIE;
wire [7:0] SIEPortDataInFromHost;
wire [7:0] SIEPortDataInFromSlave;
reg SIEPortWEnToSIE;
wire SIEPortWEnFromHost;
wire SIEPortWEnFromSlave;
reg fullSpeedPolarityToSIE;
wire fullSpeedPolarityFromHost;
wire fullSpeedPolarityFromSlave;
reg fullSpeedBitRateToSIE;
wire fullSpeedBitRateFromHost;
wire fullSpeedBitRateFromSlave;
reg noActivityTimeOutEnableToSIE;
wire noActivityTimeOutEnableFromHost;
wire noActivityTimeOutEnableFromSlave;
//hostSlaveMuxBI
wire [7:0] dataIn;
wire address;
wire writeEn;
wire strobe_i;
wire busClk;
wire usbClk;
wire rstSyncToBusClkOut;
wire rstSyncToUsbClkOut;
wire rstFromWire;
wire [7:0] dataOut;
wire hostSlaveMuxSel;
//internal wires and regs
wire hostMode;
always @(hostMode or
SIEPortCtrlInFromHost or
SIEPortCtrlInFromSlave or
SIEPortDataInFromHost or
SIEPortDataInFromSlave or
SIEPortWEnFromHost or
SIEPortWEnFromSlave or
fullSpeedPolarityFromHost or
fullSpeedPolarityFromSlave or
fullSpeedBitRateFromHost or
fullSpeedBitRateFromSlave or
noActivityTimeOutEnableFromHost or
noActivityTimeOutEnableFromSlave)
begin
if (hostMode == 1'b1)
begin
SIEPortCtrlInToSIE <= SIEPortCtrlInFromHost;
SIEPortDataInToSIE <= SIEPortDataInFromHost;
SIEPortWEnToSIE <= SIEPortWEnFromHost;
fullSpeedPolarityToSIE <= fullSpeedPolarityFromHost;
fullSpeedBitRateToSIE <= fullSpeedBitRateFromHost;
noActivityTimeOutEnableToSIE <= noActivityTimeOutEnableFromHost;
end
else
begin
SIEPortCtrlInToSIE <= SIEPortCtrlInFromSlave;
SIEPortDataInToSIE <= SIEPortDataInFromSlave;
SIEPortWEnToSIE <= SIEPortWEnFromSlave;
fullSpeedPolarityToSIE <= fullSpeedPolarityFromSlave;
fullSpeedBitRateToSIE <= fullSpeedBitRateFromSlave;
noActivityTimeOutEnableToSIE <= noActivityTimeOutEnableFromSlave;
end
end
hostSlaveMuxBI u_hostSlaveMuxBI (
.dataIn(dataIn),
.dataOut(dataOut),
.address(address),
.writeEn(writeEn),
.strobe_i(strobe_i),
.busClk(busClk),
.usbClk(usbClk),
.hostMode(hostMode),
.hostSlaveMuxSel(hostSlaveMuxSel),
.rstFromWire(rstFromWire),
.rstSyncToBusClkOut(rstSyncToBusClkOut),
.rstSyncToUsbClkOut(rstSyncToUsbClkOut) );
endmodule
|
//altera_mult_add ADDNSUB_MULTIPLIER_PIPELINE_ACLR1="ACLR0" ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1="CLOCK0" ADDNSUB_MULTIPLIER_REGISTER1="UNREGISTERED" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEDICATED_MULTIPLIER_CIRCUITRY="YES" DEVICE_FAMILY="Cyclone V" DSP_BLOCK_BALANCING="Auto" INPUT_REGISTER_A0="UNREGISTERED" INPUT_REGISTER_B0="UNREGISTERED" INPUT_SOURCE_A0="DATAA" INPUT_SOURCE_B0="DATAB" MULTIPLIER1_DIRECTION="ADD" MULTIPLIER_ACLR0="ACLR0" MULTIPLIER_REGISTER0="CLOCK0" NUMBER_OF_MULTIPLIERS=1 OUTPUT_REGISTER="UNREGISTERED" port_addnsub1="PORT_UNUSED" port_addnsub3="PORT_UNUSED" port_signa="PORT_UNUSED" port_signb="PORT_UNUSED" REPRESENTATION_A="UNSIGNED" REPRESENTATION_B="UNSIGNED" SELECTED_DEVICE_FAMILY="CYCLONEV" SIGNED_PIPELINE_ACLR_A="ACLR0" SIGNED_PIPELINE_ACLR_B="ACLR0" SIGNED_PIPELINE_REGISTER_A="CLOCK0" SIGNED_PIPELINE_REGISTER_B="CLOCK0" SIGNED_REGISTER_A="UNREGISTERED" SIGNED_REGISTER_B="UNREGISTERED" WIDTH_A=16 WIDTH_B=16 WIDTH_RESULT=16 aclr0 clock0 dataa datab result
//VERSION_BEGIN 13.1 cbx_altera_mult_add 2013:10:23:18:05:48:SJ cbx_altera_mult_add_rtl 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//synthesis_resources = altera_mult_add_rtl 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module altera_mult_add_0kt2
(
aclr0,
clock0,
dataa,
datab,
result) /* synthesis synthesis_clearbox=1 */;
input aclr0;
input clock0;
input [15:0] dataa;
input [15:0] datab;
output [15:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr0;
tri1 clock0;
tri0 [15:0] dataa;
tri0 [15:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] wire_altera_mult_add_rtl1_result;
altera_mult_add_rtl altera_mult_add_rtl1
(
.aclr0(aclr0),
.chainout_sat_overflow(),
.clock0(clock0),
.dataa(dataa),
.datab(datab),
.mult0_is_saturated(),
.mult1_is_saturated(),
.mult2_is_saturated(),
.mult3_is_saturated(),
.overflow(),
.result(wire_altera_mult_add_rtl1_result),
.scanouta(),
.scanoutb(),
.accum_sload(1'b0),
.aclr1(1'b0),
.aclr2(1'b0),
.aclr3(1'b0),
.addnsub1(1'b1),
.addnsub1_round(1'b0),
.addnsub3(1'b1),
.addnsub3_round(1'b0),
.chainin({1{1'b0}}),
.chainout_round(1'b0),
.chainout_saturate(1'b0),
.clock1(1'b1),
.clock2(1'b1),
.clock3(1'b1),
.coefsel0({3{1'b0}}),
.coefsel1({3{1'b0}}),
.coefsel2({3{1'b0}}),
.coefsel3({3{1'b0}}),
.datac({22{1'b0}}),
.ena0(1'b1),
.ena1(1'b1),
.ena2(1'b1),
.ena3(1'b1),
.mult01_round(1'b0),
.mult01_saturation(1'b0),
.mult23_round(1'b0),
.mult23_saturation(1'b0),
.output_round(1'b0),
.output_saturate(1'b0),
.rotate(1'b0),
.scanina({16{1'b0}}),
.scaninb({16{1'b0}}),
.shift_right(1'b0),
.signa(1'b0),
.signb(1'b0),
.sload_accum(1'b0),
.sourcea({1{1'b0}}),
.sourceb({1{1'b0}}),
.zero_chainout(1'b0),
.zero_loopback(1'b0)
);
defparam
altera_mult_add_rtl1.accum_direction = "ADD",
altera_mult_add_rtl1.accum_sload_aclr = "NONE",
altera_mult_add_rtl1.accum_sload_latency_aclr = "NONE",
altera_mult_add_rtl1.accum_sload_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.accum_sload_register = "UNREGISTERED",
altera_mult_add_rtl1.accumulator = "NO",
altera_mult_add_rtl1.adder1_rounding = "NO",
altera_mult_add_rtl1.adder3_rounding = "NO",
altera_mult_add_rtl1.addnsub1_round_aclr = "NONE",
altera_mult_add_rtl1.addnsub1_round_pipeline_aclr = "NONE",
altera_mult_add_rtl1.addnsub1_round_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.addnsub1_round_register = "UNREGISTERED",
altera_mult_add_rtl1.addnsub3_round_aclr = "NONE",
altera_mult_add_rtl1.addnsub3_round_pipeline_aclr = "NONE",
altera_mult_add_rtl1.addnsub3_round_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.addnsub3_round_register = "UNREGISTERED",
altera_mult_add_rtl1.addnsub_multiplier_aclr1 = "NONE",
altera_mult_add_rtl1.addnsub_multiplier_aclr3 = "NONE",
altera_mult_add_rtl1.addnsub_multiplier_latency_aclr1 = "NONE",
altera_mult_add_rtl1.addnsub_multiplier_latency_aclr3 = "NONE",
altera_mult_add_rtl1.addnsub_multiplier_latency_clock1 = "UNREGISTERED",
altera_mult_add_rtl1.addnsub_multiplier_latency_clock3 = "UNREGISTERED",
altera_mult_add_rtl1.addnsub_multiplier_register1 = "UNREGISTERED",
altera_mult_add_rtl1.addnsub_multiplier_register3 = "UNREGISTERED",
altera_mult_add_rtl1.chainout_aclr = "NONE",
altera_mult_add_rtl1.chainout_adder = "NO",
altera_mult_add_rtl1.chainout_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_round_aclr = "NONE",
altera_mult_add_rtl1.chainout_round_output_aclr = "NONE",
altera_mult_add_rtl1.chainout_round_output_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_round_pipeline_aclr = "NONE",
altera_mult_add_rtl1.chainout_round_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_round_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_rounding = "NO",
altera_mult_add_rtl1.chainout_saturate_aclr = "NONE",
altera_mult_add_rtl1.chainout_saturate_output_aclr = "NONE",
altera_mult_add_rtl1.chainout_saturate_output_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_saturate_pipeline_aclr = "NONE",
altera_mult_add_rtl1.chainout_saturate_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_saturate_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_saturation = "NO",
altera_mult_add_rtl1.coef0_0 = 0,
altera_mult_add_rtl1.coef0_1 = 0,
altera_mult_add_rtl1.coef0_2 = 0,
altera_mult_add_rtl1.coef0_3 = 0,
altera_mult_add_rtl1.coef0_4 = 0,
altera_mult_add_rtl1.coef0_5 = 0,
altera_mult_add_rtl1.coef0_6 = 0,
altera_mult_add_rtl1.coef0_7 = 0,
altera_mult_add_rtl1.coef1_0 = 0,
altera_mult_add_rtl1.coef1_1 = 0,
altera_mult_add_rtl1.coef1_2 = 0,
altera_mult_add_rtl1.coef1_3 = 0,
altera_mult_add_rtl1.coef1_4 = 0,
altera_mult_add_rtl1.coef1_5 = 0,
altera_mult_add_rtl1.coef1_6 = 0,
altera_mult_add_rtl1.coef1_7 = 0,
altera_mult_add_rtl1.coef2_0 = 0,
altera_mult_add_rtl1.coef2_1 = 0,
altera_mult_add_rtl1.coef2_2 = 0,
altera_mult_add_rtl1.coef2_3 = 0,
altera_mult_add_rtl1.coef2_4 = 0,
altera_mult_add_rtl1.coef2_5 = 0,
altera_mult_add_rtl1.coef2_6 = 0,
altera_mult_add_rtl1.coef2_7 = 0,
altera_mult_add_rtl1.coef3_0 = 0,
altera_mult_add_rtl1.coef3_1 = 0,
altera_mult_add_rtl1.coef3_2 = 0,
altera_mult_add_rtl1.coef3_3 = 0,
altera_mult_add_rtl1.coef3_4 = 0,
altera_mult_add_rtl1.coef3_5 = 0,
altera_mult_add_rtl1.coef3_6 = 0,
altera_mult_add_rtl1.coef3_7 = 0,
altera_mult_add_rtl1.coefsel0_aclr = "NONE",
altera_mult_add_rtl1.coefsel0_latency_aclr = "NONE",
altera_mult_add_rtl1.coefsel0_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.coefsel0_register = "UNREGISTERED",
altera_mult_add_rtl1.coefsel1_aclr = "NONE",
altera_mult_add_rtl1.coefsel1_latency_aclr = "NONE",
altera_mult_add_rtl1.coefsel1_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.coefsel1_register = "UNREGISTERED",
altera_mult_add_rtl1.coefsel2_aclr = "NONE",
altera_mult_add_rtl1.coefsel2_latency_aclr = "NONE",
altera_mult_add_rtl1.coefsel2_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.coefsel2_register = "UNREGISTERED",
altera_mult_add_rtl1.coefsel3_aclr = "NONE",
altera_mult_add_rtl1.coefsel3_latency_aclr = "NONE",
altera_mult_add_rtl1.coefsel3_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.coefsel3_register = "UNREGISTERED",
altera_mult_add_rtl1.dedicated_multiplier_circuitry = "YES",
altera_mult_add_rtl1.double_accum = "NO",
altera_mult_add_rtl1.dsp_block_balancing = "Auto",
altera_mult_add_rtl1.extra_latency = 0,
altera_mult_add_rtl1.input_a0_latency_aclr = "NONE",
altera_mult_add_rtl1.input_a0_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_a1_latency_aclr = "NONE",
altera_mult_add_rtl1.input_a1_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_a2_latency_aclr = "NONE",
altera_mult_add_rtl1.input_a2_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_a3_latency_aclr = "NONE",
altera_mult_add_rtl1.input_a3_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_aclr_a0 = "NONE",
altera_mult_add_rtl1.input_aclr_a1 = "NONE",
altera_mult_add_rtl1.input_aclr_a2 = "NONE",
altera_mult_add_rtl1.input_aclr_a3 = "NONE",
altera_mult_add_rtl1.input_aclr_b0 = "NONE",
altera_mult_add_rtl1.input_aclr_b1 = "NONE",
altera_mult_add_rtl1.input_aclr_b2 = "NONE",
altera_mult_add_rtl1.input_aclr_b3 = "NONE",
altera_mult_add_rtl1.input_aclr_c0 = "NONE",
altera_mult_add_rtl1.input_aclr_c1 = "NONE",
altera_mult_add_rtl1.input_aclr_c2 = "NONE",
altera_mult_add_rtl1.input_aclr_c3 = "NONE",
altera_mult_add_rtl1.input_b0_latency_aclr = "NONE",
altera_mult_add_rtl1.input_b0_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_b1_latency_aclr = "NONE",
altera_mult_add_rtl1.input_b1_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_b2_latency_aclr = "NONE",
altera_mult_add_rtl1.input_b2_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_b3_latency_aclr = "NONE",
altera_mult_add_rtl1.input_b3_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_c0_latency_aclr = "NONE",
altera_mult_add_rtl1.input_c0_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_c1_latency_aclr = "NONE",
altera_mult_add_rtl1.input_c1_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_c2_latency_aclr = "NONE",
altera_mult_add_rtl1.input_c2_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_c3_latency_aclr = "NONE",
altera_mult_add_rtl1.input_c3_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_register_a0 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_a1 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_a2 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_a3 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_b0 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_b1 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_b2 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_b3 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_c0 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_c1 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_c2 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_c3 = "UNREGISTERED",
altera_mult_add_rtl1.input_source_a0 = "DATAA",
altera_mult_add_rtl1.input_source_a1 = "DATAA",
altera_mult_add_rtl1.input_source_a2 = "DATAA",
altera_mult_add_rtl1.input_source_a3 = "DATAA",
altera_mult_add_rtl1.input_source_b0 = "DATAB",
altera_mult_add_rtl1.input_source_b1 = "DATAB",
altera_mult_add_rtl1.input_source_b2 = "DATAB",
altera_mult_add_rtl1.input_source_b3 = "DATAB",
altera_mult_add_rtl1.latency = 0,
altera_mult_add_rtl1.loadconst_control_aclr = "NONE",
altera_mult_add_rtl1.loadconst_control_register = "UNREGISTERED",
altera_mult_add_rtl1.loadconst_value = 64,
altera_mult_add_rtl1.mult01_round_aclr = "NONE",
altera_mult_add_rtl1.mult01_round_register = "UNREGISTERED",
altera_mult_add_rtl1.mult01_saturation_aclr = "ACLR0",
altera_mult_add_rtl1.mult01_saturation_register = "UNREGISTERED",
altera_mult_add_rtl1.mult23_round_aclr = "NONE",
altera_mult_add_rtl1.mult23_round_register = "UNREGISTERED",
altera_mult_add_rtl1.mult23_saturation_aclr = "NONE",
altera_mult_add_rtl1.mult23_saturation_register = "UNREGISTERED",
altera_mult_add_rtl1.multiplier01_rounding = "NO",
altera_mult_add_rtl1.multiplier01_saturation = "NO",
altera_mult_add_rtl1.multiplier1_direction = "ADD",
altera_mult_add_rtl1.multiplier23_rounding = "NO",
altera_mult_add_rtl1.multiplier23_saturation = "NO",
altera_mult_add_rtl1.multiplier3_direction = "ADD",
altera_mult_add_rtl1.multiplier_aclr0 = "ACLR0",
altera_mult_add_rtl1.multiplier_aclr1 = "NONE",
altera_mult_add_rtl1.multiplier_aclr2 = "NONE",
altera_mult_add_rtl1.multiplier_aclr3 = "NONE",
altera_mult_add_rtl1.multiplier_register0 = "CLOCK0",
altera_mult_add_rtl1.multiplier_register1 = "UNREGISTERED",
altera_mult_add_rtl1.multiplier_register2 = "UNREGISTERED",
altera_mult_add_rtl1.multiplier_register3 = "UNREGISTERED",
altera_mult_add_rtl1.number_of_multipliers = 1,
altera_mult_add_rtl1.output_aclr = "NONE",
altera_mult_add_rtl1.output_register = "UNREGISTERED",
altera_mult_add_rtl1.output_round_aclr = "NONE",
altera_mult_add_rtl1.output_round_pipeline_aclr = "NONE",
altera_mult_add_rtl1.output_round_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.output_round_register = "UNREGISTERED",
altera_mult_add_rtl1.output_round_type = "NEAREST_INTEGER",
altera_mult_add_rtl1.output_rounding = "NO",
altera_mult_add_rtl1.output_saturate_aclr = "NONE",
altera_mult_add_rtl1.output_saturate_pipeline_aclr = "NONE",
altera_mult_add_rtl1.output_saturate_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.output_saturate_register = "UNREGISTERED",
altera_mult_add_rtl1.output_saturate_type = "ASYMMETRIC",
altera_mult_add_rtl1.output_saturation = "NO",
altera_mult_add_rtl1.port_addnsub1 = "PORT_UNUSED",
altera_mult_add_rtl1.port_addnsub3 = "PORT_UNUSED",
altera_mult_add_rtl1.port_chainout_sat_is_overflow = "PORT_UNUSED",
altera_mult_add_rtl1.port_output_is_overflow = "PORT_UNUSED",
altera_mult_add_rtl1.port_signa = "PORT_UNUSED",
altera_mult_add_rtl1.port_signb = "PORT_UNUSED",
altera_mult_add_rtl1.preadder_direction_0 = "ADD",
altera_mult_add_rtl1.preadder_direction_1 = "ADD",
altera_mult_add_rtl1.preadder_direction_2 = "ADD",
altera_mult_add_rtl1.preadder_direction_3 = "ADD",
altera_mult_add_rtl1.preadder_mode = "SIMPLE",
altera_mult_add_rtl1.representation_a = "UNSIGNED",
altera_mult_add_rtl1.representation_b = "UNSIGNED",
altera_mult_add_rtl1.rotate_aclr = "NONE",
altera_mult_add_rtl1.rotate_output_aclr = "NONE",
altera_mult_add_rtl1.rotate_output_register = "UNREGISTERED",
altera_mult_add_rtl1.rotate_pipeline_aclr = "NONE",
altera_mult_add_rtl1.rotate_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.rotate_register = "UNREGISTERED",
altera_mult_add_rtl1.scanouta_aclr = "NONE",
altera_mult_add_rtl1.scanouta_register = "UNREGISTERED",
altera_mult_add_rtl1.selected_device_family = "Cyclone V",
altera_mult_add_rtl1.shift_mode = "NO",
altera_mult_add_rtl1.shift_right_aclr = "NONE",
altera_mult_add_rtl1.shift_right_output_aclr = "NONE",
altera_mult_add_rtl1.shift_right_output_register = "UNREGISTERED",
altera_mult_add_rtl1.shift_right_pipeline_aclr = "NONE",
altera_mult_add_rtl1.shift_right_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.shift_right_register = "UNREGISTERED",
altera_mult_add_rtl1.signed_aclr_a = "NONE",
altera_mult_add_rtl1.signed_aclr_b = "NONE",
altera_mult_add_rtl1.signed_latency_aclr_a = "NONE",
altera_mult_add_rtl1.signed_latency_aclr_b = "NONE",
altera_mult_add_rtl1.signed_latency_clock_a = "UNREGISTERED",
altera_mult_add_rtl1.signed_latency_clock_b = "UNREGISTERED",
altera_mult_add_rtl1.signed_register_a = "UNREGISTERED",
altera_mult_add_rtl1.signed_register_b = "UNREGISTERED",
altera_mult_add_rtl1.systolic_aclr1 = "NONE",
altera_mult_add_rtl1.systolic_aclr3 = "NONE",
altera_mult_add_rtl1.systolic_delay1 = "UNREGISTERED",
altera_mult_add_rtl1.systolic_delay3 = "UNREGISTERED",
altera_mult_add_rtl1.use_sload_accum_port = "NO",
altera_mult_add_rtl1.width_a = 16,
altera_mult_add_rtl1.width_b = 16,
altera_mult_add_rtl1.width_c = 22,
altera_mult_add_rtl1.width_chainin = 1,
altera_mult_add_rtl1.width_coef = 18,
altera_mult_add_rtl1.width_msb = 17,
altera_mult_add_rtl1.width_result = 16,
altera_mult_add_rtl1.width_saturate_sign = 1,
altera_mult_add_rtl1.zero_chainout_output_aclr = "NONE",
altera_mult_add_rtl1.zero_chainout_output_register = "UNREGISTERED",
altera_mult_add_rtl1.zero_loopback_aclr = "NONE",
altera_mult_add_rtl1.zero_loopback_output_aclr = "NONE",
altera_mult_add_rtl1.zero_loopback_output_register = "UNREGISTERED",
altera_mult_add_rtl1.zero_loopback_pipeline_aclr = "NONE",
altera_mult_add_rtl1.zero_loopback_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.zero_loopback_register = "UNREGISTERED",
altera_mult_add_rtl1.lpm_type = "altera_mult_add_rtl";
assign
result = wire_altera_mult_add_rtl1_result;
endmodule //altera_mult_add_0kt2
//VALID FILE
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21BA_FUNCTIONAL_V
`define SKY130_FD_SC_LP__O21BA_FUNCTIONAL_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__o21ba (
X ,
A1 ,
A2 ,
B1_N
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1_N;
// Local signals
wire nor0_out ;
wire nor1_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A1, A2 );
nor nor1 (nor1_out_X, B1_N, nor0_out );
buf buf0 (X , nor1_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21BA_FUNCTIONAL_V |
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Set_Acceleration.v
// Created: 2014-09-08 14:12:04
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Set_Acceleration
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Generate_Position_And_Voltage_Ramp/Rotor_Acceleration_To_Velocity/Set_Acceleration
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Set_Acceleration
(
CLK_IN,
reset,
enb_1_2000_0,
v_target,
v_current,
a
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input signed [17:0] v_target; // sfix18_En8
input signed [31:0] v_current; // sfix32_En22
output signed [17:0] a; // sfix18_En10
wire signed [31:0] Relational_Operator_1_cast; // sfix32_En22
wire Relational_Operator_relop1;
wire current_less_than_target;
wire current_less_than_target_1;
wire current_greater_than_target;
wire target_has_changed;
wire Latch_out1;
reg Delay1_out1;
wire Latch_out1_1;
wire negative_direction;
wire switch_compare_1;
wire signed [17:0] Acceleration1_out1; // sfix18_En10
wire signed [18:0] Neg_cast; // sfix19_En10
wire signed [18:0] Neg_cast_1; // sfix19_En10
wire signed [35:0] Neg_cast_2; // sfix36_En27
wire signed [17:0] Neg_out1; // sfix18_En10
wire current_greater_than_target_1;
wire stop_positive_acceleration;
wire current_less_than_target_2;
wire stop_negative_acceleration;
wire stop_positive_acceleration_1;
wire stop_accelerating;
wire signed [17:0] positive_accleration; // sfix18_En10
wire signed [17:0] accleration; // sfix18_En10
wire signed [17:0] Constant_out1; // sfix18_En10
wire signed [17:0] Switch_Stop_out1; // sfix18_En10
// Set Acceleration
// <S29>/Relational Operator
assign Relational_Operator_1_cast = {v_target, 14'b00000000000000};
assign Relational_Operator_relop1 = (Relational_Operator_1_cast > v_current ? 1'b1 :
1'b0);
assign current_less_than_target = Relational_Operator_relop1;
// <S29>/NOT2
assign current_less_than_target_1 = ~ current_less_than_target;
assign current_greater_than_target = current_less_than_target_1;
// <S29>/Detect_Change
controllerHdl_Detect_Change u_Detect_Change (.CLK_IN(CLK_IN),
.reset(reset),
.enb_1_2000_0(enb_1_2000_0),
.x(v_target), // sfix18_En8
.y(target_has_changed)
);
// <S29>/Delay1
always @(posedge CLK_IN)
begin : Delay1_process
if (reset == 1'b1) begin
Delay1_out1 <= 1'b0;
end
else if (enb_1_2000_0) begin
Delay1_out1 <= Latch_out1;
end
end
// <S29>/Latch
//
// <S29>/Signal Specification
assign Latch_out1 = (target_has_changed == 1'b0 ? Delay1_out1 :
current_less_than_target);
// <S29>/NOT3
assign Latch_out1_1 = ~ Latch_out1;
assign negative_direction = Latch_out1_1;
assign switch_compare_1 = (Latch_out1 > 1'b0 ? 1'b1 :
1'b0);
// <S29>/Acceleration1
assign Acceleration1_out1 = 18'sb001010000000000000;
// <S29>/Neg
assign Neg_cast = Acceleration1_out1;
assign Neg_cast_1 = - (Neg_cast);
assign Neg_cast_2 = {Neg_cast_1, 17'b00000000000000000};
assign Neg_out1 = Neg_cast_2[34:17];
// <S29>/AND_Pos
assign current_greater_than_target_1 = current_greater_than_target & Latch_out1;
assign stop_positive_acceleration = current_greater_than_target_1;
// <S29>/AND_Neg
assign current_less_than_target_2 = current_less_than_target & negative_direction;
assign stop_negative_acceleration = current_less_than_target_2;
// <S29>/OR_SAT1
assign stop_positive_acceleration_1 = stop_positive_acceleration | stop_negative_acceleration;
assign stop_accelerating = stop_positive_acceleration_1;
// <S29>/Acceleration
assign positive_accleration = 18'sb001010000000000000;
// <S29>/Switch_Dir
assign accleration = (switch_compare_1 == 1'b0 ? Neg_out1 :
positive_accleration);
// <S29>/Constant
assign Constant_out1 = 18'sb000000000000000000;
// <S29>/Switch_Stop
assign Switch_Stop_out1 = (stop_accelerating == 1'b0 ? accleration :
Constant_out1);
assign a = Switch_Stop_out1;
endmodule // controllerHdl_Set_Acceleration
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A211OI_4_V
`define SKY130_FD_SC_HD__A211OI_4_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog wrapper for a211oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a211oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a211oi_4 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a211oi_4 (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A211OI_4_V
|
//----------------------------------------------------------------------------
// Copyright (C) 2015 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: ogfx_if_lt24.v
//
// *Module Description:
// Interface to the LT24 LCD display.
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`ifdef OGFX_NO_INCLUDE
`else
`include "openGFX430_defines.v"
`endif
module ogfx_if_lt24 (
// OUTPUTs
event_fsm_done_o, // Event - FSM is done
event_fsm_start_o, // Event - FSM is starting
lt24_cs_n_o, // LT24 Chip select (Active low)
lt24_d_o, // LT24 Data output
lt24_d_en_o, // LT24 Data output enable
lt24_rd_n_o, // LT24 Read strobe (Active low)
lt24_rs_o, // LT24 Command/Param selection (Cmd=0/Param=1)
lt24_wr_n_o, // LT24 Write strobe (Active low)
refresh_active_o, // Display refresh on going
refresh_data_request_o, // Display refresh new data request
status_o, // Status - FSM
// INPUTs
mclk, // Main system clock
puc_rst, // Main system reset
cfg_lt24_clk_div_i, // Clock Divider configuration for LT24 interface
cfg_lt24_display_size_i, // Display size (number of pixels)
cfg_lt24_refresh_i, // Refresh rate configuration for LT24 interface
cfg_lt24_refresh_sync_en_i, // Refresh sync enable configuration for LT24 interface
cfg_lt24_refresh_sync_val_i, // Refresh sync value configuration for LT24 interface
cmd_dfill_i, // Display refresh data
cmd_dfill_trig_i, // Trigger a full display refresh
cmd_generic_cmd_val_i, // Generic command value
cmd_generic_has_param_i, // Generic command to be sent has parameter(s)
cmd_generic_param_val_i, // Generic command parameter value
cmd_generic_trig_i, // Trigger generic command transmit (or new parameter available)
cmd_refresh_i, // Display refresh command
lt24_d_i, // LT24 Data input
refresh_data_i, // Display refresh data
refresh_data_ready_i // Display refresh new data is ready
);
// OUTPUTs
//=========
output event_fsm_done_o; // LT24 FSM done event
output event_fsm_start_o; // LT24 FSM start event
output lt24_cs_n_o; // LT24 Chip select (Active low)
output [15:0] lt24_d_o; // LT24 Data output
output lt24_d_en_o; // LT24 Data output enable
output lt24_rd_n_o; // LT24 Read strobe (Active low)
output lt24_rs_o; // LT24 Command/Param selection (Cmd=0/Param=1)
output lt24_wr_n_o; // LT24 Write strobe (Active low)
output refresh_active_o; // Display refresh on going
output refresh_data_request_o; // Display refresh new data request
output [4:0] status_o; // LT24 FSM Status
// INPUTs
//=========
input mclk; // Main system clock
input puc_rst; // Main system reset
input [2:0] cfg_lt24_clk_div_i; // Clock Divider configuration for LT24 interface
input [`SPIX_MSB:0] cfg_lt24_display_size_i; // Display size (number of pixels)
input [11:0] cfg_lt24_refresh_i; // Refresh rate configuration for LT24 interface
input cfg_lt24_refresh_sync_en_i; // Refresh sync enable configuration for LT24 interface
input [9:0] cfg_lt24_refresh_sync_val_i; // Refresh sync value configuration for LT24 interface
input [15:0] cmd_dfill_i; // Display refresh data
input cmd_dfill_trig_i; // Trigger a full display refresh
input [7:0] cmd_generic_cmd_val_i; // Generic command value
input cmd_generic_has_param_i; // Generic command to be sent has parameter(s)
input [15:0] cmd_generic_param_val_i; // Generic command parameter value
input cmd_generic_trig_i; // Trigger generic command transmit (or new parameter available)
input cmd_refresh_i; // Display refresh command
input [15:0] lt24_d_i; // LT24 Data input
input [15:0] refresh_data_i; // Display refresh data
input refresh_data_ready_i; // Display refresh new data is ready
//=============================================================================
// 1) WIRE, REGISTERS AND PARAMETER DECLARATION
//=============================================================================
// State machine registers
reg [4:0] lt24_state;
reg [4:0] lt24_state_nxt;
// Others
reg refresh_trigger;
wire status_gts_match;
// State definition
parameter STATE_IDLE = 0, // IDLE state
STATE_CMD_LO = 1, // Generic command to LT24
STATE_CMD_HI = 2,
STATE_CMD_PARAM_LO = 3,
STATE_CMD_PARAM_HI = 4,
STATE_CMD_PARAM_WAIT = 5,
STATE_RAMWR_INIT_CMD_LO = 6, // Initialize display buffer with data
STATE_RAMWR_INIT_CMD_HI = 7,
STATE_RAMWR_INIT_DATA_LO = 8,
STATE_RAMWR_INIT_DATA_HI = 9,
STATE_SCANLINE_CMD_LO = 10, // Wait for right scanline
STATE_SCANLINE_CMD_HI = 11,
STATE_SCANLINE_DUMMY_LO = 12,
STATE_SCANLINE_DUMMY_HI = 13,
STATE_SCANLINE_GTS1_LO = 14,
STATE_SCANLINE_GTS1_HI = 15,
STATE_SCANLINE_GTS2_LO = 16,
STATE_SCANLINE_GTS2_HI = 17,
STATE_RAMWR_REFR_CMD_LO = 18, // Refresh display buffer
STATE_RAMWR_REFR_CMD_HI = 19,
STATE_RAMWR_REFR_WAIT = 20,
STATE_RAMWR_REFR_DATA_LO = 21,
STATE_RAMWR_REFR_DATA_HI = 22;
//============================================================================
// 5) STATE MACHINE SENDING IMAGE DATA TO A SPECIFIED DISPLAY
//============================================================================
//--------------------------------
// LT24 Controller Clock Timer
//--------------------------------
reg [3:0] lt24_timer;
wire lt24_timer_done = lt24_d_en_o ? (lt24_timer == {1'b0, cfg_lt24_clk_div_i}) :
(lt24_timer == {cfg_lt24_clk_div_i, 1'b0}) ; // Use slower timing for read accesses
wire lt24_timer_run = (lt24_state != STATE_IDLE) &
(lt24_state != STATE_CMD_PARAM_WAIT) &
(lt24_state != STATE_RAMWR_REFR_WAIT) &
~lt24_timer_done;
wire lt24_timer_init = (lt24_timer_done & // Init if counter reaches limit:
!((lt24_state == STATE_CMD_PARAM_HI) & cmd_generic_has_param_i) & // -> if not moving to STATE_CMD_PARAM_WAIT
!((lt24_state == STATE_CMD_PARAM_WAIT))) | // -> if not in STATE_CMD_PARAM_WAIT
((lt24_state == STATE_CMD_PARAM_WAIT) & (cmd_generic_trig_i | ~cmd_generic_has_param_i)); // Init when leaving the STATE_CMD_PARAM_WAIT state
always @(posedge mclk or posedge puc_rst)
if (puc_rst) lt24_timer <= 4'h0;
else if (lt24_timer_init) lt24_timer <= 4'h0;
else if (lt24_timer_run) lt24_timer <= lt24_timer+4'h1;
//--------------------------------
// Pixel counter
//--------------------------------
reg [`SPIX_MSB:0] lt24_pixel_cnt;
wire lt24_pixel_cnt_run = (lt24_state==STATE_RAMWR_INIT_DATA_HI) |
(lt24_state==STATE_RAMWR_REFR_DATA_HI);
wire lt24_pixel_cnt_done = (lt24_pixel_cnt==1) | (lt24_pixel_cnt==0);
wire lt24_pixel_cnt_init = (lt24_state==STATE_RAMWR_INIT_CMD_HI) |
(lt24_state==STATE_RAMWR_REFR_CMD_HI) |
(lt24_pixel_cnt_done & lt24_pixel_cnt_run);
always @(posedge mclk or posedge puc_rst)
if (puc_rst) lt24_pixel_cnt <= {`SPIX_MSB+1{1'h0}};
else if (lt24_timer_init)
begin
if (lt24_pixel_cnt_init) lt24_pixel_cnt <= cfg_lt24_display_size_i;
else if (lt24_pixel_cnt_run) lt24_pixel_cnt <= lt24_pixel_cnt-{{`SPIX_MSB{1'h0}},1'b1};
end
//--------------------------------
// States Transitions
//--------------------------------
always @(lt24_state or cmd_dfill_trig_i or cmd_generic_trig_i or refresh_trigger or cfg_lt24_refresh_sync_en_i or status_gts_match or refresh_data_request_o or cmd_generic_has_param_i or lt24_timer_done or lt24_pixel_cnt_done)
case(lt24_state)
STATE_IDLE : lt24_state_nxt = cmd_dfill_trig_i ? STATE_RAMWR_INIT_CMD_LO :
refresh_trigger ?
(cfg_lt24_refresh_sync_en_i ? STATE_SCANLINE_CMD_LO : STATE_RAMWR_REFR_CMD_LO) :
cmd_generic_trig_i ? STATE_CMD_LO : STATE_IDLE ;
// GENERIC COMMANDS
STATE_CMD_LO : lt24_state_nxt = ~lt24_timer_done ? STATE_CMD_LO : STATE_CMD_HI ;
STATE_CMD_HI : lt24_state_nxt = ~lt24_timer_done ? STATE_CMD_HI :
cmd_generic_has_param_i ? STATE_CMD_PARAM_LO : STATE_IDLE ;
STATE_CMD_PARAM_LO : lt24_state_nxt = ~lt24_timer_done ? STATE_CMD_PARAM_LO : STATE_CMD_PARAM_HI ;
STATE_CMD_PARAM_HI : lt24_state_nxt = ~lt24_timer_done ? STATE_CMD_PARAM_HI :
cmd_generic_has_param_i ? STATE_CMD_PARAM_WAIT : STATE_IDLE ;
STATE_CMD_PARAM_WAIT : lt24_state_nxt = cmd_generic_trig_i ? STATE_CMD_PARAM_LO :
cmd_generic_has_param_i ? STATE_CMD_PARAM_WAIT : STATE_IDLE ;
// MEMORY INITIALIZATION
STATE_RAMWR_INIT_CMD_LO : lt24_state_nxt = ~lt24_timer_done ? STATE_RAMWR_INIT_CMD_LO : STATE_RAMWR_INIT_CMD_HI ;
STATE_RAMWR_INIT_CMD_HI : lt24_state_nxt = ~lt24_timer_done ? STATE_RAMWR_INIT_CMD_HI : STATE_RAMWR_INIT_DATA_LO ;
STATE_RAMWR_INIT_DATA_LO : lt24_state_nxt = ~lt24_timer_done ? STATE_RAMWR_INIT_DATA_LO : STATE_RAMWR_INIT_DATA_HI ;
STATE_RAMWR_INIT_DATA_HI : lt24_state_nxt = lt24_timer_done &
lt24_pixel_cnt_done ? STATE_IDLE :
~lt24_timer_done ? STATE_RAMWR_INIT_DATA_HI : STATE_RAMWR_INIT_DATA_LO ;
// WAIT FOR RIGHT SCANLINE BEFORE REFRESH
STATE_SCANLINE_CMD_LO : lt24_state_nxt = ~lt24_timer_done ? STATE_SCANLINE_CMD_LO : STATE_SCANLINE_CMD_HI ;
STATE_SCANLINE_CMD_HI : lt24_state_nxt = ~lt24_timer_done ? STATE_SCANLINE_CMD_HI : STATE_SCANLINE_DUMMY_LO ;
STATE_SCANLINE_DUMMY_LO : lt24_state_nxt = ~lt24_timer_done ? STATE_SCANLINE_DUMMY_LO : STATE_SCANLINE_DUMMY_HI ;
STATE_SCANLINE_DUMMY_HI : lt24_state_nxt = ~lt24_timer_done ? STATE_SCANLINE_DUMMY_HI : STATE_SCANLINE_GTS1_LO ;
STATE_SCANLINE_GTS1_LO : lt24_state_nxt = ~lt24_timer_done ? STATE_SCANLINE_GTS1_LO : STATE_SCANLINE_GTS1_HI ;
STATE_SCANLINE_GTS1_HI : lt24_state_nxt = ~lt24_timer_done ? STATE_SCANLINE_GTS1_HI : STATE_SCANLINE_GTS2_LO ;
STATE_SCANLINE_GTS2_LO : lt24_state_nxt = ~lt24_timer_done ? STATE_SCANLINE_GTS2_LO : STATE_SCANLINE_GTS2_HI ;
STATE_SCANLINE_GTS2_HI : lt24_state_nxt = ~lt24_timer_done ? STATE_SCANLINE_GTS2_HI :
(status_gts_match |
~cfg_lt24_refresh_sync_en_i) ? STATE_RAMWR_REFR_CMD_LO : STATE_SCANLINE_CMD_LO ;
// FRAME REFRESH
STATE_RAMWR_REFR_CMD_LO : lt24_state_nxt = ~lt24_timer_done ? STATE_RAMWR_REFR_CMD_LO : STATE_RAMWR_REFR_CMD_HI ;
STATE_RAMWR_REFR_CMD_HI : lt24_state_nxt = ~lt24_timer_done ? STATE_RAMWR_REFR_CMD_HI :
~refresh_data_request_o ? STATE_RAMWR_REFR_DATA_LO : STATE_RAMWR_REFR_WAIT ;
STATE_RAMWR_REFR_WAIT : lt24_state_nxt = ~refresh_data_request_o ? STATE_RAMWR_REFR_DATA_LO : STATE_RAMWR_REFR_WAIT ;
STATE_RAMWR_REFR_DATA_LO : lt24_state_nxt = ~lt24_timer_done ? STATE_RAMWR_REFR_DATA_LO : STATE_RAMWR_REFR_DATA_HI ;
STATE_RAMWR_REFR_DATA_HI : lt24_state_nxt = lt24_timer_done &
lt24_pixel_cnt_done ? STATE_IDLE :
~lt24_timer_done ? STATE_RAMWR_REFR_DATA_HI :
~refresh_data_request_o ? STATE_RAMWR_REFR_DATA_LO : STATE_RAMWR_REFR_WAIT ;
// pragma coverage off
default : lt24_state_nxt = STATE_IDLE;
// pragma coverage on
endcase
// State machine
always @(posedge mclk or posedge puc_rst)
if (puc_rst) lt24_state <= STATE_IDLE;
else lt24_state <= lt24_state_nxt;
// Output status
assign status_o[0] = (lt24_state != STATE_IDLE); // LT24 FSM BUSY
assign status_o[1] = (lt24_state == STATE_CMD_PARAM_WAIT); // LT24 Waits for command parameter
assign status_o[2] = (lt24_state == STATE_RAMWR_REFR_CMD_LO) | (lt24_state == STATE_RAMWR_REFR_CMD_HI) | // LT24 REFRESH BUSY
(lt24_state == STATE_RAMWR_REFR_DATA_LO) | (lt24_state == STATE_RAMWR_REFR_DATA_HI) |
(lt24_state == STATE_RAMWR_REFR_WAIT);
assign status_o[3] = (lt24_state == STATE_SCANLINE_CMD_LO) | (lt24_state == STATE_SCANLINE_CMD_HI) | // LT24 WAIT FOR SCANLINE
(lt24_state == STATE_SCANLINE_DUMMY_LO) | (lt24_state == STATE_SCANLINE_DUMMY_HI) |
(lt24_state == STATE_SCANLINE_GTS1_LO) | (lt24_state == STATE_SCANLINE_GTS1_HI) |
(lt24_state == STATE_SCANLINE_GTS2_LO) | (lt24_state == STATE_SCANLINE_GTS2_HI);
assign status_o[4] = (lt24_state == STATE_RAMWR_INIT_CMD_LO) | (lt24_state == STATE_RAMWR_INIT_CMD_HI) | // LT24 INIT BUSY
(lt24_state == STATE_RAMWR_INIT_DATA_LO) | (lt24_state == STATE_RAMWR_INIT_DATA_HI);
assign refresh_active_o = status_o[2];
// Refresh data request
wire refresh_data_request_set = ((lt24_state == STATE_RAMWR_REFR_CMD_LO) & (lt24_state_nxt == STATE_RAMWR_REFR_CMD_HI)) |
((lt24_state == STATE_RAMWR_REFR_DATA_LO) & (lt24_state_nxt == STATE_RAMWR_REFR_DATA_HI)) |
(lt24_state == STATE_RAMWR_REFR_WAIT);
wire refresh_data_request_clr = refresh_data_ready_i;
reg refresh_data_request_reg;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) refresh_data_request_reg <= 1'b0;
else refresh_data_request_reg <= refresh_data_request_clr ? 1'b0 :
refresh_data_request_set ? 1'b1 : refresh_data_request_reg;
assign refresh_data_request_o = refresh_data_request_reg & ~refresh_data_ready_i;
assign event_fsm_start_o = (lt24_state_nxt != STATE_IDLE) & (lt24_state == STATE_IDLE);
assign event_fsm_done_o = (lt24_state != STATE_IDLE) & (lt24_state_nxt == STATE_IDLE);
//============================================================================
// 6) LT24 CONTROLLER OUTPUT ASSIGNMENT
//============================================================================
// LT24 Chip select (active low)
reg lt24_cs_n_o;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) lt24_cs_n_o <= 1'b1;
else lt24_cs_n_o <= (lt24_state_nxt==STATE_IDLE);
// Command (0) or Data (1)
reg lt24_rs_o;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) lt24_rs_o <= 1'b1;
else lt24_rs_o <= ~((lt24_state_nxt==STATE_CMD_LO) | (lt24_state_nxt==STATE_CMD_HI) |
(lt24_state_nxt==STATE_SCANLINE_CMD_LO) | (lt24_state_nxt==STATE_SCANLINE_CMD_HI) |
(lt24_state_nxt==STATE_RAMWR_INIT_CMD_LO) | (lt24_state_nxt==STATE_RAMWR_INIT_CMD_HI) |
(lt24_state_nxt==STATE_RAMWR_REFR_CMD_LO) | (lt24_state_nxt==STATE_RAMWR_REFR_CMD_HI));
// LT24 Write strobe (Active low)
reg lt24_wr_n_o;
wire lt24_wr_n_clr = (lt24_state_nxt==STATE_CMD_LO) | (lt24_state_nxt==STATE_CMD_PARAM_LO) | (lt24_state_nxt==STATE_SCANLINE_CMD_LO) |
(lt24_state_nxt==STATE_RAMWR_INIT_CMD_LO) | (lt24_state_nxt==STATE_RAMWR_INIT_DATA_LO) |
(lt24_state_nxt==STATE_RAMWR_REFR_CMD_LO) | (lt24_state_nxt==STATE_RAMWR_REFR_DATA_LO);
always @(posedge mclk or posedge puc_rst)
if (puc_rst) lt24_wr_n_o <= 1'b1;
else if (lt24_wr_n_clr) lt24_wr_n_o <= 1'b0;
else lt24_wr_n_o <= 1'b1;
// LT24 Read strobe (active low)
reg lt24_rd_n_o;
wire lt24_rd_n_clr = (lt24_state_nxt==STATE_SCANLINE_DUMMY_LO) |
(lt24_state_nxt==STATE_SCANLINE_GTS1_LO) | (lt24_state_nxt==STATE_SCANLINE_GTS2_LO);
always @(posedge mclk or posedge puc_rst)
if (puc_rst) lt24_rd_n_o <= 1'b1;
else if (lt24_rd_n_clr) lt24_rd_n_o <= 1'b0;
else lt24_rd_n_o <= 1'b1;
// LT24 Data
reg [15:0] lt24_d_nxt;
always @(lt24_state_nxt or cmd_generic_cmd_val_i or cmd_generic_param_val_i or lt24_d_o or cmd_dfill_i or refresh_data_i)
case(lt24_state_nxt)
STATE_IDLE : lt24_d_nxt = 16'h0000;
STATE_CMD_LO,
STATE_CMD_HI : lt24_d_nxt = {8'h00, cmd_generic_cmd_val_i};
STATE_CMD_PARAM_LO,
STATE_CMD_PARAM_HI : lt24_d_nxt = cmd_generic_param_val_i;
STATE_CMD_PARAM_WAIT : lt24_d_nxt = lt24_d_o;
STATE_RAMWR_INIT_CMD_LO,
STATE_RAMWR_INIT_CMD_HI : lt24_d_nxt = 16'h002C;
STATE_RAMWR_INIT_DATA_LO,
STATE_RAMWR_INIT_DATA_HI : lt24_d_nxt = cmd_dfill_i;
STATE_SCANLINE_CMD_LO,
STATE_SCANLINE_CMD_HI : lt24_d_nxt = 16'h0045;
STATE_RAMWR_REFR_CMD_LO,
STATE_RAMWR_REFR_CMD_HI : lt24_d_nxt = 16'h002C;
STATE_RAMWR_REFR_DATA_LO : lt24_d_nxt = refresh_data_i;
STATE_RAMWR_REFR_DATA_HI : lt24_d_nxt = lt24_d_o;
STATE_RAMWR_REFR_WAIT : lt24_d_nxt = lt24_d_o;
// pragma coverage off
default : lt24_d_nxt = 16'h0000;
// pragma coverage on
endcase
reg [15:0] lt24_d_o;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) lt24_d_o <= 16'h0000;
else lt24_d_o <= lt24_d_nxt;
// Output enable
reg lt24_d_en_o;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) lt24_d_en_o <= 1'h0; // Don't drive output during reset
else lt24_d_en_o <= ~((lt24_state_nxt == STATE_SCANLINE_DUMMY_LO) |
(lt24_state_nxt == STATE_SCANLINE_DUMMY_HI) |
(lt24_state_nxt == STATE_SCANLINE_GTS1_LO ) |
(lt24_state_nxt == STATE_SCANLINE_GTS1_HI ) |
(lt24_state_nxt == STATE_SCANLINE_GTS2_LO ) |
(lt24_state_nxt == STATE_SCANLINE_GTS2_HI ));
//============================================================================
// 7) LT24 GTS VALUE (i.e. CURRENT SCAN LINE)
//============================================================================
reg [1:0] status_gts_msb;
wire status_gts_msb_wr = ((lt24_state == STATE_SCANLINE_GTS1_LO) & (lt24_state_nxt == STATE_SCANLINE_GTS1_HI));
always @(posedge mclk or posedge puc_rst)
if (puc_rst) status_gts_msb <= 2'h0;
else if (status_gts_msb_wr) status_gts_msb <= lt24_d_i[1:0];
reg [7:0] status_gts_lsb;
wire status_gts_lsb_wr = ((lt24_state == STATE_SCANLINE_GTS2_LO) & (lt24_state_nxt == STATE_SCANLINE_GTS2_HI));
always @(posedge mclk or posedge puc_rst)
if (puc_rst) status_gts_lsb <= 8'h00;
else if (status_gts_lsb_wr) status_gts_lsb <= lt24_d_i[7:0];
wire [7:0] unused_lt24_d_15_8 = lt24_d_i[15:8];
wire [9:0] status_gts = {status_gts_msb, status_gts_lsb};
assign status_gts_match = (status_gts == cfg_lt24_refresh_sync_val_i);
//============================================================================
// 8) REFRESH TIMER & TRIGGER
//============================================================================
// Refresh Timer
reg [23:0] refresh_timer;
wire refresh_timer_disable = (cfg_lt24_refresh_i==12'h000) | ~cmd_refresh_i;
wire refresh_timer_done = (refresh_timer[23:12]==cfg_lt24_refresh_i);
always @(posedge mclk or posedge puc_rst)
if (puc_rst) refresh_timer <= 24'h000000;
else if (refresh_timer_disable) refresh_timer <= 24'h000000;
else if (refresh_timer_done) refresh_timer <= 24'h000000;
else refresh_timer <= refresh_timer + 24'h1;
// Refresh Trigger
wire refresh_trigger_set = (lt24_state==STATE_IDLE) & cmd_refresh_i & (refresh_timer==24'h000000);
wire refresh_trigger_clr = (lt24_state==STATE_RAMWR_REFR_CMD_LO);
always @(posedge mclk or posedge puc_rst)
if (puc_rst) refresh_trigger <= 1'b0;
else if (refresh_trigger_set) refresh_trigger <= 1'b1;
else if (refresh_trigger_clr) refresh_trigger <= 1'b0;
endmodule // ogfx_if_lt24
`ifdef OGFX_NO_INCLUDE
`else
`include "openGFX430_undefines.v"
`endif
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Dual-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common dual-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// dual-port synchronous RAM. ////
//// It also contains a fully synthesizeable model for FPGAs. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// - Artisan Dual-Port Sync RAM ////
//// - Avant! Two-Port Sync RAM (*) ////
//// - Virage 2-port Sync RAM ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Generic FPGA (VENDOR_FPGA) ////
//// Tested RAMs: Altera, Xilinx ////
//// Synthesis tools: LeonardoSpectrum, Synplicity ////
//// - Xilinx (VENDOR_XILINX) ////
//// - Altera (VENDOR_ALTERA) ////
//// ////
//// To Do: ////
//// - fix Avant! ////
//// - add additional RAMs (VS etc) ////
//// ////
//// Author(s): ////
//// - Richard Herveille, [email protected] ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2001/11/09 00:34:18 samg
// minor changes: unified with all common rams
//
// Revision 1.2 2001/11/08 19:11:31 samg
// added valid checks to behvioral model
//
// Revision 1.1.1.1 2001/09/14 09:57:10 rherveille
// Major cleanup.
// Files are now compliant to Altera & Xilinx memories.
// Memories are now compatible, i.e. drop-in replacements.
// Added synthesizeable generic FPGA description.
// Created "generic_memories" cvs entry.
//
// Revision 1.1.1.2 2001/08/21 13:09:27 damjan
// *** empty log message ***
//
// Revision 1.1 2001/08/20 18:23:20 damjan
// Initial revision
//
// Revision 1.1 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.2 2001/07/30 05:38:02 lampret
// Adding empty directories required by HDL coding guidelines
//
//
//`include "timescale.v"
`define VENDOR_FPGA
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
module generic_dpram(
// Generic synchronous dual-port RAM interface
rclk, rrst, rce, oe, raddr, do,
wclk, wrst, wce, we, waddr, di
);
//
// Default address and data buses width
//
parameter aw = 5; // number of bits in address-bus
parameter dw = 16; // number of bits in data-bus
//
// Generic synchronous double-port RAM interface
//
// read port
input rclk; // read clock, rising edge trigger
input rrst; // read port reset, active high
input rce; // read port chip enable, active high
input oe; // output enable, active high
input [aw-1:0] raddr; // read address
output [dw-1:0] do; // data output
// write port
input wclk; // write clock, rising edge trigger
input wrst; // write port reset, active high
input wce; // write port chip enable, active high
input we; // write enable, active high
input [aw-1:0] waddr; // write address
input [dw-1:0] di; // data input
//
// Module body
//
`ifdef VENDOR_FPGA
//
// Instantiation synthesizeable FPGA memory
//
// This code has been tested using LeonardoSpectrum and Synplicity.
// The code correctly instantiates Altera EABs and Xilinx BlockRAMs.
//
reg [dw-1:0] mem [(1<<aw) -1:0]; // instantiate memory
reg [aw-1:0] ra; // register read address
// read operation
always @(posedge rclk)
if (rce)
ra <= #1 raddr;
assign do = mem[ra];
// write operation
always@(posedge wclk)
if (we && wce)
mem[waddr] <= #1 di;
`else
`ifdef VENDOR_XILINX
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2 BlockRAMs
//
xilinx_ram_dp xilinx_ram(
// read port
.CLKA(rclk),
.RSTA(rrst),
.ENA(rce),
.ADDRA(raddr),
.DIA( {dw{1'b0}} ),
.WEA(1'b0),
.DOA(do),
// write port
.CLKB(wclk),
.RSTB(wrst),
.ENB(wce),
.ADDRB(waddr),
.DIB(di),
.WEB(we),
.DOB()
);
defparam
xilinx_ram.dwidth = dw,
xilinx_ram.awidth = aw;
`else
`ifdef VENDOR_ALTERA
//
// Instantiation of FPGA memory:
//
// Altera FLEX/APEX EABs
//
altera_ram_dp altera_ram(
// read port
.rdclock(rclk),
.rdclocken(rce),
.rdaddress(raddr),
.q(do),
// write port
.wrclock(wclk),
.wrclocken(wce),
.wren(we),
.wraddress(waddr),
.data(di)
);
defparam
altera_ram.dwidth = dw,
altera_ram.awidth = aw;
`else
`ifdef VENDOR_ARTISAN
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Double-Port RAM (ra2sh)
//
art_hsdp #(dw, 1<<aw, aw) artisan_sdp(
// read port
.qa(do),
.clka(rclk),
.cena(~rce),
.wena(1'b1),
.aa(raddr),
.da( {dw{1'b0}} ),
.oena(~oe),
// write port
.qb(),
.clkb(wclk),
.cenb(~wce),
.wenb(~we),
.ab(waddr),
.db(di),
.oenb(1'b1)
);
`else
`ifdef VENDOR_AVANT
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
.web(~we),
.reb(),
.oeb(~oe),
.rcsb(),
.wcsb(),
.ra(raddr),
.wa(waddr),
.di(di),
.do(do)
);
`else
`ifdef VENDOR_VIRAGE
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 2-port R/W RAM
//
virage_stp virage_stp(
// read port
.CLKA(rclk),
.MEA(rce_a),
.ADRA(raddr),
.DA( {dw{1'b0}} ),
.WEA(1'b0),
.OEA(oe),
.QA(do),
// write port
.CLKB(wclk),
.MEB(wce),
.ADRB(waddr),
.DB(di),
.WEB(we),
.OEB(1'b1),
.QB()
);
`else
//
// Generic dual-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [dw-1:0] do_reg; // RAM data output register
//
// Data output drivers
//
assign do = (oe & rce) ? do_reg : {dw{1'bz}};
// read operation
always @(posedge rclk)
if (rce)
do_reg <= #1 (we && (waddr==raddr)) ? {dw{1'b x}} : mem[raddr];
// write operation
always @(posedge wclk)
if (wce && we)
mem[waddr] <= #1 di;
// Task prints range of memory
// *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations.
task print_ram;
input [aw-1:0] start;
input [aw-1:0] finish;
integer rnum;
begin
for (rnum=start;rnum<=finish;rnum=rnum+1)
$display("Addr %h = %h",rnum,mem[rnum]);
end
endtask
`endif // !VENDOR_VIRAGE
`endif // !VENDOR_AVANT
`endif // !VENDOR_ARTISAN
`endif // !VENDOR_ALTERA
`endif // !VENDOR_XILINX
`endif // !VENDOR_FPGA
endmodule
//
// Black-box modules
//
`ifdef VENDOR_ALTERA
module altera_ram_dp(
data,
wraddress,
rdaddress,
wren,
wrclock,
wrclocken,
rdclock,
rdclocken,
q) /* synthesis black_box */;
parameter awidth = 7;
parameter dwidth = 8;
input [dwidth -1:0] data;
input [awidth -1:0] wraddress;
input [awidth -1:0] rdaddress;
input wren;
input wrclock;
input wrclocken;
input rdclock;
input rdclocken;
output [dwidth -1:0] q;
// synopsis translate_off
// exemplar translate_off
syn_dpram_rowr #(
"UNUSED",
dwidth,
awidth,
1 << awidth
)
altera_dpram_model (
// read port
.RdClock(rdclock),
.RdClken(rdclocken),
.RdAddress(rdaddress),
.RdEn(1'b1),
.Q(q),
// write port
.WrClock(wrclock),
.WrClken(wrclocken),
.WrAddress(wraddress),
.WrEn(wren),
.Data(data)
);
// exemplar translate_on
// synopsis translate_on
endmodule
`endif // VENDOR_ALTERA
`ifdef VENDOR_XILINX
module xilinx_ram_dp (
ADDRA,
CLKA,
ADDRB,
CLKB,
DIA,
WEA,
DIB,
WEB,
ENA,
ENB,
RSTA,
RSTB,
DOA,
DOB) /* synthesis black_box */ ;
parameter awidth = 7;
parameter dwidth = 8;
// port_a
input CLKA;
input RSTA;
input ENA;
input [awidth-1:0] ADDRA;
input [dwidth-1:0] DIA;
input WEA;
output [dwidth-1:0] DOA;
// port_b
input CLKB;
input RSTB;
input ENB;
input [awidth-1:0] ADDRB;
input [dwidth-1:0] DIB;
input WEB;
output [dwidth-1:0] DOB;
// insert simulation model
// synopsys translate_off
// exemplar translate_off
C_MEM_DP_BLOCK_V1_0 #(
awidth,
awidth,
1,
1,
"0",
1 << awidth,
1 << awidth,
1,
1,
1,
1,
1,
1,
1,
1,
1,
1,
1,
1,
1,
"",
16,
0,
0,
1,
1,
1,
1,
dwidth,
dwidth)
xilinx_dpram_model (
.ADDRA(ADDRA),
.CLKA(CLKA),
.ADDRB(ADDRB),
.CLKB(CLKB),
.DIA(DIA),
.WEA(WEA),
.DIB(DIB),
.WEB(WEB),
.ENA(ENA),
.ENB(ENB),
.RSTA(RSTA),
.RSTB(RSTB),
.DOA(DOA),
.DOB(DOB));
// exemplar translate_on
// synopsys translate_on
endmodule
`endif // VENDOR_XILINX
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Tue Nov 8 02:10:26 2016
/////////////////////////////////////////////////////////////
module CORDIC_Arch2v1_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_fsm_cordic,
ack_cordic, operation, data_in, shift_region_flag, ready_cordic,
data_output, beg_add_subt, ack_add_subt, add_subt_dataA,
add_subt_dataB, result_add_subt, op_add_subt, ready_add_subt );
input [31:0] data_in;
input [1:0] shift_region_flag;
output [31:0] data_output;
output [31:0] add_subt_dataA;
output [31:0] add_subt_dataB;
input [31:0] result_add_subt;
input clk, rst, beg_fsm_cordic, ack_cordic, operation, ready_add_subt;
output ready_cordic, beg_add_subt, ack_add_subt, op_add_subt;
wire d_ff1_operation_out, cont_iter_out_2_, d_ff3_sign_out,
data_output2_31_, cordic_FSM_state_next_1_, cordic_FSM_state_reg_0_,
n331, n336, n337, n338, n339, n341, n342, n343, n344, n346, n347,
n348, n349, n350, n351, n352, n353, n354, n355, n356, n357, n358,
n359, n360, n361, n362, n363, n364, n365, n366, n367, n368, n369,
n370, n371, n372, n373, n374, n375, n376, n377, n378, n379, n380,
n381, n382, n383, n384, n385, n386, n387, n388, n389, n390, n391,
n392, n393, n394, n395, n396, n397, n398, n399, n400, n401, n402,
n403, n406, n407, n408, n410, n411, n412, n413, n414, n415, n416,
n417, n418, n419, n420, n421, n422, n423, n424, n425, n426, n427,
n428, n429, n430, n431, n432, n433, n434, n435, n436, n437, n438,
n439, n440, n441, n442, n443, n444, n445, n446, n447, n448, n449,
n450, n451, n452, n453, n454, n455, n456, n457, n458, n459, n460,
n461, n462, n463, n464, n465, n466, n467, n468, n469, n470, n471,
n472, n473, n474, n475, n476, n477, n478, n479, n480, n481, n482,
n483, n484, n485, n486, n487, n488, n489, n490, n491, n492, n493,
n494, n495, n496, n497, n502, n503, n504, n505, n506, n507, n508,
n509, n511, n512, n513, n514, n515, n516, n517, n518, n520, n521,
n522, n524, n525, n526, n527, n528, n529, n530, n531, n532, n533,
n534, n535, n536, n537, n538, n539, n540, n541, n542, n543, n544,
n545, n546, n547, n548, n549, n550, n551, n552, n553, n554, n555,
n556, n557, n558, n559, n560, n561, n562, n563, n564, n565, n566,
n567, n568, n569, n570, n571, n572, n573, n574, n575, n576, n577,
n578, n579, n580, n581, n582, n583, n584, n585, n586, n587, n588,
n597, n607, n608, n610, n621, n622, n623, n624, n626, n627, n628,
n630, n631, n632, n634, n636, n638, n640, n641, n642, n644, n646,
n649, n650, n651, n652, n663, n664, n665, n666, n667, n668, n669,
n670, n671, n672, n673, n674, n675, n676, n677, n678, n679, n680,
n681, n682, n683, n684, n689, n690, n691, n692, n693, n694, n695,
n696, n697, n698, n699, n700, n701, n702, n703, n704, n705, n706,
n707, n708, n709, n710, n711, n712, n713, n714, n715, n716, n717,
n718, n719, n720, n721, n723, n724, n725, n726, n727, n728, n729,
n730, n731, n732, net5420, net5449, net5513, net5617, net5649,
net5801, net5805, net6074, net6633, net6644, net6643, net6713,
net6761, net7391, net7462, net7519, net7520, net7526, net7541,
net7544, net7560, net12499, net13653, net13654, net13657, net13662,
net13665, net13666, net13667, net13670, net13671, net13672, net13673,
net13674, net13805, net13816, net13817, net13889, net13890, net13896,
net13899, net13910, net13913, net13933, net13943, net13948, net13950,
net13951, net13960, net13967, net13969, net14072, net14080, net14146,
net14149, net14160, net14189, net14213, net14325, net14330, net14332,
net14367, net14374, net14376, net14383, net14393, net14399, net14400,
net14404, net14444, net14445, net14447, net14457, net14688, net14689,
net14753, net14838, net14841, net14847, net14848, net14851, net14857,
net14972, net14971, net15017, net15081, net15104, net15103, net15102,
net15101, net15128, net15156, net15155, net15160, net15166, net15216,
net15219, net15395, net15394, net15397, net15425, net15424, net15434,
net15447, net15446, net15444, net15442, net15483, net15482, net15759,
net15794, net15798, net15797, net15304, net14448, net13968, net15671,
net14755, net14331, net14152, net15305, net15445, net15433, net15441,
net14440, net14333, net13912, net13909, net13887, n806, n807, n808,
n809, n810, n811, n812, n816, n817, n818, n819, n820, n821, n822,
n823, n824, n825, n826, n827, n828, n829, n830, n831, n832, n833,
n834, n835, n836, n837, n838, n839, n840, n841, n842, n843, n844,
n845, n846, n847, n848, n849, n850, n851, n852, n853, n854, n855,
n856, n857, n858, n859, n860, n861, n862, n863, n864, n865, n866,
n867, n868, n869, n870, n871, n872, n873, n874, n875, n876, n877,
n878, n880, n881, n882, n883, n884, n885, n886, n887, n888, n889,
n890, n891, n892, n893, n894, n895, n896, n897, n898, n899, n900,
n901, n902, n903, n904, n905, n906, n907, n908, n909, n910, n911,
n912, n913, n914, n915, n916, n917, n918, n919, n921, n922, n923,
n924, n925, n926, n927, n928, n929, n931, n932, n933, n934, n935,
n936, n937, n938, n939, n940, n941, n942, n943, n944, n945, n946,
n947, n948, n949, n950, n951, n952, n953, n954, n955, n956, n957,
n958, n959, n960, n961, n962, n963, n964, n965, n966, n967, n968,
n969, n970, n971, n972, n973, n974, n975, n976, n977, n978, n979,
n980, n981, n982, n983, n984, n985, n986, n987, n988, n989, n990,
n991, n992, n993, n994, n995, n996, n997, n998, n999, n1000, n1001,
n1002, n1003, n1004, n1005, n1006, n1007, n1008, n1009, n1010, n1011,
n1012, n1013, n1014, n1015, n1016, n1017, n1018, n1019, n1020, n1021,
n1022, n1023, n1024, n1025, n1026, n1027, n1028, n1029, n1030, n1031,
n1032, n1033, n1034, n1035, n1036, n1037, n1038, n1039, n1040, n1041,
n1042, n1043, n1044, n1045, n1046, n1047, n1048, n1049, n1050, n1051,
n1052, n1053, n1054, n1055, n1056, n1057, n1058, n1059, n1060, n1061,
n1062, n1063, n1064, n1065, n1066, n1067, n1068, n1069, n1070, n1071,
n1072, n1073, n1074, n1075, n1076, n1077, n1078, n1079, n1080, n1081,
n1082, n1083, n1084, n1085, n1086, n1087, n1088, n1089, n1090, n1091,
n1092, n1093, n1094, n1095, n1096, n1097, n1098, n1099, n1100, n1101,
n1102, n1103, n1104, n1105, n1106, n1107, n1108, n1109, n1110, n1111,
n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119, n1120, n1121,
n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129, n1130, n1131,
n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139, n1140, n1141,
n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149, n1150, n1151,
n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159, n1160, n1161,
n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170, n1171,
n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179, n1180, n1181,
n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1190, n1191,
n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200, n1201,
n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210, n1211,
n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220, n1221,
n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230, n1231,
n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240, n1241,
n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251,
n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260, n1261,
n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270, n1271,
n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280, n1281,
n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290, n1291,
n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300, n1301,
n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310, n1311,
n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320, n1321,
n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330, n1331,
n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341,
n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350, n1351,
n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360, n1361,
n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371,
n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381,
n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391,
n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401,
n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411,
n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421,
n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431,
n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441,
n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451,
n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461,
n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471,
n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480, n1481,
n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491,
n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501,
n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511,
n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520, n1521,
n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530, n1531,
n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541,
n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551,
n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560, n1561,
n1562, n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570, n1571,
n1572, n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580, n1581,
n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590, n1591,
n1592, n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600, n1601,
n1602, n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610, n1611,
n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620, n1621,
n1622, n1623, n1624, n1625, n1626, n1627, n1628, n1629, n1630, n1631,
n1632, n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640, n1641,
n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650, n1651,
n1652, n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660, n1661,
n1662, n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670, n1671,
n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680, n1681,
n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690, n1691,
n1692, n1693, n1694, n1695, n1696, n1697, n1698, n1699, n1700, n1701,
n1702, n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710, n1711,
n1712, n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720, n1721,
n1722, n1723, n1724, n1725, n1727, n1728, n1729, n1730, n1731, n1732,
n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740, n1741, n1742,
n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750, n1751, n1752,
n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760, n1761, n1762,
n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770, n1771, n1772,
n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780, n1781, n1782,
n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790, n1791, n1792,
n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800, n1801, n1802,
n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810, n1811, n1812,
n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1820, n1821, n1822,
n1823, n1824, n1825, n1826, n1827, n1828, n1829, n1830, n1831, n1832,
n1833, n1834, n1835, n1836, n1837, n1838, n1839, n1840, n1841, n1842,
n1843, n1844, n1845, n1846, n1847, n1848, n1849, n1850, n1851, n1852,
n1853, n1854, n1855, n1856, n1857, n1858, n1859, n1860, n1861, n1862,
n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870, n1871, n1872,
n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880, n1881, n1882,
n1883, n1884, n1885, n1886, n1887, n1888, n1889, n1890, n1891, n1892,
n1893, n1894, n1895, n1896, n1897, n1898, n1899, n1900, n1901, n1902,
n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910, n1911, n1912,
n1913, n1914, n1915, n1916, n1917, n1918, n1919, n1920, n1921, n1922,
n1923, n1924, n1925, n1926, n1927, n1928, n1929, n1930, n1931, n1932,
n1933, n1934, n1935, n1936, n1937, n1938, n1939, n1940, n1941, n1942,
n1943, n1944, n1945, n1946, n1947, n1948, n1949, n1950, n1951, n1952,
n1953, n1954, n1955, n1956, n1957, n1958, n1959, n1960, n1961, n1962,
n1963, n1964, n1965, n1966, n1967, n1968, n1969, n1970, n1971, n1972,
n1973, n1974, n1975, n1976, n1977, n1978, n1979, n1980, n1981, n1982,
n1983, n1984, n1985, n1986, n1987, n1988, n1989, n1990, n1991, n1992,
n1993, n1994, n1995, n1996, n1997, n1998, n1999, n2000, n2001, n2002,
n2003, n2004, n2005, n2006, n2007, n2008, n2009, n2010, n2011, n2012,
n2013, n2014, n2015, n2016, n2017, n2018, n2019, n2020, n2021, n2022,
n2023, n2024, n2025, n2026, n2027, n2028, n2029, n2030, n2031, n2032,
n2033, n2034, n2035, n2036, n2037, n2038, n2039, n2040, n2041, n2042,
n2043, n2044, n2045, n2046, n2047, n2048, n2049, n2050, n2051, n2052,
n2053, n2054, n2055, n2056, n2057, n2058, n2059, n2060, n2061, n2062,
n2063, n2064, n2065, n2066, n2067, n2068, n2069, n2070, n2071, n2072,
n2073, n2074, n2075, n2076, n2077, n2078, n2079, n2080, n2081, n2082,
n2083, n2084, n2085, n2086, n2087, n2088, n2089, n2090, n2091, n2092,
n2093, n2094, n2095, n2096, n2097, n2098, n2099, n2100, n2101, n2102,
n2103, n2104, n2105, n2106, n2107, n2108, n2109, n2110, n2111, n2112,
n2113, n2114, n2115, n2116, n2117, n2118, n2119, n2120, n2121, n2122,
n2123, n2124, n2125, n2126, n2127, n2128, n2129, n2130, n2131, n2132,
n2133, n2134, n2135, n2136, n2137, n2138, n2139, n2140, n2141, n2142,
n2143, n2144, n2145, n2146, n2147, n2148, n2149, n2150, n2151, n2152,
n2153, n2154, n2155, n2156, n2157, n2158, n2159, n2160, n2161, n2162,
n2163, n2164, n2165, n2166, n2167, n2168, n2169, n2170, n2171;
wire [1:0] cont_var_out;
wire [31:0] d_ff1_Z;
wire [31:0] d_ff_Yn;
wire [21:0] d_ff_Zn;
wire [31:0] d_ff2_X;
wire [31:0] d_ff2_Y;
wire [31:0] d_ff2_Z;
wire [31:26] d_ff3_sh_x_out;
wire [31:0] d_ff3_sh_y_out;
wire [27:0] d_ff3_LUT_out;
wire [1:0] sel_mux_2_reg;
wire [30:0] sign_inv_out;
DFFRXLTS d_ff4_Zn_Q_reg_0_ ( .D(n684), .CK(clk), .RN(n2042), .Q(d_ff_Zn[0]),
.QN(n1808) );
DFFRXLTS d_ff4_Zn_Q_reg_1_ ( .D(n683), .CK(clk), .RN(n2171), .Q(d_ff_Zn[1]),
.QN(n1809) );
DFFRXLTS d_ff4_Zn_Q_reg_2_ ( .D(n682), .CK(clk), .RN(n2034), .Q(d_ff_Zn[2]),
.QN(n1810) );
DFFRXLTS d_ff4_Zn_Q_reg_3_ ( .D(n681), .CK(clk), .RN(n2033), .Q(d_ff_Zn[3]),
.QN(n1811) );
DFFRXLTS d_ff4_Zn_Q_reg_4_ ( .D(n680), .CK(clk), .RN(n2171), .Q(d_ff_Zn[4]),
.QN(n1740) );
DFFRXLTS d_ff4_Zn_Q_reg_5_ ( .D(n679), .CK(clk), .RN(n2171), .Q(d_ff_Zn[5]),
.QN(n1812) );
DFFRXLTS d_ff4_Zn_Q_reg_6_ ( .D(n678), .CK(clk), .RN(n2043), .Q(d_ff_Zn[6]),
.QN(n1813) );
DFFRXLTS d_ff4_Zn_Q_reg_7_ ( .D(n677), .CK(clk), .RN(n991), .Q(d_ff_Zn[7]),
.QN(n1814) );
DFFRXLTS d_ff4_Zn_Q_reg_8_ ( .D(n676), .CK(clk), .RN(n987), .Q(d_ff_Zn[8]),
.QN(n1741) );
DFFRXLTS d_ff4_Zn_Q_reg_9_ ( .D(n675), .CK(clk), .RN(n2043), .Q(d_ff_Zn[9]),
.QN(n1815) );
DFFRXLTS d_ff4_Zn_Q_reg_10_ ( .D(n674), .CK(clk), .RN(n2043), .Q(d_ff_Zn[10]), .QN(n1816) );
DFFRXLTS d_ff4_Zn_Q_reg_11_ ( .D(n673), .CK(clk), .RN(n2044), .Q(d_ff_Zn[11]), .QN(n1831) );
DFFRXLTS d_ff4_Zn_Q_reg_12_ ( .D(n672), .CK(clk), .RN(n2049), .Q(d_ff_Zn[12]), .QN(net7544) );
DFFRXLTS d_ff4_Zn_Q_reg_13_ ( .D(n671), .CK(clk), .RN(n2044), .Q(d_ff_Zn[13]), .QN(n1742) );
DFFRXLTS d_ff4_Zn_Q_reg_14_ ( .D(n670), .CK(clk), .RN(n2051), .Q(d_ff_Zn[14]), .QN(n1817) );
DFFRXLTS d_ff4_Zn_Q_reg_15_ ( .D(n669), .CK(clk), .RN(n2051), .Q(d_ff_Zn[15]), .QN(n1818) );
DFFRXLTS d_ff4_Zn_Q_reg_16_ ( .D(n668), .CK(clk), .RN(n2044), .Q(d_ff_Zn[16]), .QN(net7541) );
DFFRXLTS d_ff4_Zn_Q_reg_17_ ( .D(n667), .CK(clk), .RN(n2042), .Q(d_ff_Zn[17]), .QN(n1819) );
DFFRXLTS d_ff4_Zn_Q_reg_18_ ( .D(n666), .CK(clk), .RN(n2050), .Q(d_ff_Zn[18]), .QN(n1820) );
DFFRXLTS d_ff4_Zn_Q_reg_19_ ( .D(n665), .CK(clk), .RN(n2052), .Q(d_ff_Zn[19]), .QN(n1821) );
DFFRXLTS d_ff4_Zn_Q_reg_20_ ( .D(n664), .CK(clk), .RN(n2049), .Q(d_ff_Zn[20]), .QN(n1822) );
DFFRX1TS d_ff4_Yn_Q_reg_0_ ( .D(n652), .CK(clk), .RN(n1908), .Q(d_ff_Yn[0]),
.QN(n1845) );
DFFRX1TS d_ff4_Yn_Q_reg_11_ ( .D(n641), .CK(clk), .RN(n2041), .Q(d_ff_Yn[11]), .QN(n1806) );
DFFRX1TS d_ff4_Yn_Q_reg_12_ ( .D(n640), .CK(clk), .RN(n2040), .Q(d_ff_Yn[12]), .QN(net7520) );
DFFRX1TS d_ff4_Yn_Q_reg_14_ ( .D(n638), .CK(clk), .RN(n995), .Q(d_ff_Yn[14]),
.QN(n1842) );
DFFRX1TS d_ff4_Yn_Q_reg_16_ ( .D(n636), .CK(clk), .RN(n995), .Q(d_ff_Yn[16]),
.QN(net7519) );
DFFRX1TS d_ff4_Yn_Q_reg_18_ ( .D(n634), .CK(clk), .RN(n995), .Q(d_ff_Yn[18]),
.QN(n1843) );
DFFRX1TS d_ff4_Yn_Q_reg_20_ ( .D(n632), .CK(clk), .RN(n995), .Q(d_ff_Yn[20]),
.QN(n1834) );
DFFRX1TS d_ff4_Yn_Q_reg_21_ ( .D(n631), .CK(clk), .RN(n995), .Q(d_ff_Yn[21]),
.QN(n1836) );
DFFRX1TS d_ff4_Yn_Q_reg_22_ ( .D(n630), .CK(clk), .RN(n995), .Q(d_ff_Yn[22]),
.QN(n1839) );
DFFRX1TS d_ff4_Yn_Q_reg_24_ ( .D(n628), .CK(clk), .RN(n978), .Q(d_ff_Yn[24]),
.QN(net7526) );
DFFRX1TS d_ff4_Yn_Q_reg_25_ ( .D(n627), .CK(clk), .RN(n978), .Q(d_ff_Yn[25]),
.QN(n1837) );
DFFRX1TS d_ff4_Yn_Q_reg_26_ ( .D(n626), .CK(clk), .RN(n978), .Q(d_ff_Yn[26]),
.QN(n1840) );
DFFRX1TS d_ff4_Yn_Q_reg_29_ ( .D(n623), .CK(clk), .RN(n978), .Q(d_ff_Yn[29]),
.QN(n1838) );
DFFRX1TS d_ff4_Yn_Q_reg_31_ ( .D(n621), .CK(clk), .RN(n978), .Q(d_ff_Yn[31]),
.QN(net7560) );
DFFRX1TS d_ff5_Q_reg_0_ ( .D(n588), .CK(clk), .RN(n2050), .Q(sign_inv_out[0]), .QN(n1764) );
DFFRX1TS d_ff5_Q_reg_1_ ( .D(n586), .CK(clk), .RN(n2042), .Q(sign_inv_out[1]), .QN(n1765) );
DFFRX1TS d_ff5_Q_reg_2_ ( .D(n584), .CK(clk), .RN(n2044), .Q(sign_inv_out[2]), .QN(n1766) );
DFFRX1TS d_ff5_Q_reg_3_ ( .D(n582), .CK(clk), .RN(n997), .Q(sign_inv_out[3]),
.QN(n1767) );
DFFRX1TS d_ff5_Q_reg_4_ ( .D(n580), .CK(clk), .RN(n997), .Q(sign_inv_out[4]),
.QN(n1768) );
DFFRX1TS d_ff5_Q_reg_5_ ( .D(n578), .CK(clk), .RN(n997), .Q(sign_inv_out[5]),
.QN(n1769) );
DFFRX1TS d_ff5_Q_reg_6_ ( .D(n576), .CK(clk), .RN(n989), .Q(sign_inv_out[6]),
.QN(n1732) );
DFFRX1TS d_ff5_Q_reg_7_ ( .D(n574), .CK(clk), .RN(n989), .Q(sign_inv_out[7]),
.QN(n1733) );
DFFRX1TS d_ff5_Q_reg_8_ ( .D(n572), .CK(clk), .RN(n989), .Q(sign_inv_out[8]),
.QN(n1734) );
DFFRX1TS d_ff5_Q_reg_11_ ( .D(n566), .CK(clk), .RN(n2032), .Q(
sign_inv_out[11]), .QN(n1771) );
DFFRX1TS d_ff5_Q_reg_12_ ( .D(n564), .CK(clk), .RN(n2032), .Q(
sign_inv_out[12]), .QN(n1772) );
DFFRX1TS d_ff5_Q_reg_13_ ( .D(n562), .CK(clk), .RN(n2042), .Q(
sign_inv_out[13]), .QN(n1773) );
DFFRX1TS d_ff5_Q_reg_14_ ( .D(n560), .CK(clk), .RN(n2042), .Q(
sign_inv_out[14]), .QN(n1774) );
DFFRX1TS d_ff5_Q_reg_15_ ( .D(n558), .CK(clk), .RN(n2051), .Q(
sign_inv_out[15]), .QN(n1775) );
DFFRX1TS d_ff5_Q_reg_16_ ( .D(n556), .CK(clk), .RN(n810), .Q(
sign_inv_out[16]), .QN(n1776) );
DFFRX1TS d_ff5_Q_reg_17_ ( .D(n554), .CK(clk), .RN(n2047), .Q(
sign_inv_out[17]), .QN(n1777) );
DFFRX1TS d_ff5_Q_reg_19_ ( .D(n550), .CK(clk), .RN(n810), .Q(
sign_inv_out[19]), .QN(n1778) );
DFFRX1TS d_ff5_Q_reg_20_ ( .D(n548), .CK(clk), .RN(n985), .Q(
sign_inv_out[20]), .QN(n1779) );
DFFRX1TS d_ff5_Q_reg_21_ ( .D(n546), .CK(clk), .RN(n985), .Q(
sign_inv_out[21]), .QN(n1780) );
DFFRX1TS d_ff5_Q_reg_22_ ( .D(n544), .CK(clk), .RN(n985), .Q(
sign_inv_out[22]), .QN(n1781) );
DFFRX1TS d_ff5_Q_reg_24_ ( .D(n540), .CK(clk), .RN(n811), .Q(
sign_inv_out[24]), .QN(n1783) );
DFFRX1TS d_ff5_Q_reg_25_ ( .D(n538), .CK(clk), .RN(n811), .Q(
sign_inv_out[25]), .QN(n1784) );
DFFRX1TS d_ff5_Q_reg_26_ ( .D(n536), .CK(clk), .RN(n982), .Q(
sign_inv_out[26]), .QN(n1785) );
DFFRX1TS d_ff5_Q_reg_28_ ( .D(n532), .CK(clk), .RN(n982), .Q(
sign_inv_out[28]), .QN(n1787) );
DFFRX1TS d_ff5_Q_reg_29_ ( .D(n530), .CK(clk), .RN(n982), .Q(
sign_inv_out[29]), .QN(n1788) );
DFFRX1TS d_ff5_Q_reg_30_ ( .D(n528), .CK(clk), .RN(n985), .Q(
sign_inv_out[30]), .QN(n1738) );
DFFRX1TS reg_LUT_Q_reg_0_ ( .D(n524), .CK(clk), .RN(n971), .Q(
d_ff3_LUT_out[0]) );
DFFRX1TS reg_LUT_Q_reg_2_ ( .D(n522), .CK(clk), .RN(n969), .Q(
d_ff3_LUT_out[2]) );
DFFRX1TS reg_LUT_Q_reg_3_ ( .D(n521), .CK(clk), .RN(n983), .Q(
d_ff3_LUT_out[3]) );
DFFRX1TS reg_LUT_Q_reg_4_ ( .D(n520), .CK(clk), .RN(n970), .Q(
d_ff3_LUT_out[4]) );
DFFRX1TS reg_LUT_Q_reg_6_ ( .D(n518), .CK(clk), .RN(n979), .Q(
d_ff3_LUT_out[6]) );
DFFRX1TS reg_LUT_Q_reg_7_ ( .D(n517), .CK(clk), .RN(n983), .Q(
d_ff3_LUT_out[7]) );
DFFRX1TS reg_LUT_Q_reg_9_ ( .D(n515), .CK(clk), .RN(n967), .Q(
d_ff3_LUT_out[9]) );
DFFRX1TS reg_LUT_Q_reg_10_ ( .D(n514), .CK(clk), .RN(n967), .Q(
d_ff3_LUT_out[10]) );
DFFRX1TS reg_LUT_Q_reg_11_ ( .D(n513), .CK(clk), .RN(n2033), .Q(
d_ff3_LUT_out[11]) );
DFFRX1TS reg_LUT_Q_reg_13_ ( .D(n511), .CK(clk), .RN(n984), .Q(
d_ff3_LUT_out[13]) );
DFFRX1TS reg_LUT_Q_reg_15_ ( .D(n509), .CK(clk), .RN(n2042), .Q(
d_ff3_LUT_out[15]) );
DFFRX1TS reg_LUT_Q_reg_16_ ( .D(n508), .CK(clk), .RN(n2040), .Q(
d_ff3_LUT_out[16]) );
DFFRX1TS reg_LUT_Q_reg_17_ ( .D(n507), .CK(clk), .RN(n2049), .Q(
d_ff3_LUT_out[17]) );
DFFRX1TS reg_LUT_Q_reg_19_ ( .D(n505), .CK(clk), .RN(n2052), .Q(
d_ff3_LUT_out[19]) );
DFFRX1TS reg_LUT_Q_reg_20_ ( .D(n504), .CK(clk), .RN(n2038), .Q(
d_ff3_LUT_out[20]) );
DFFRX1TS reg_LUT_Q_reg_22_ ( .D(n502), .CK(clk), .RN(n2056), .Q(
d_ff3_LUT_out[22]) );
DFFRX1TS reg_shift_y_Q_reg_24_ ( .D(n408), .CK(clk), .RN(n979), .Q(
d_ff3_sh_y_out[24]), .QN(n1864) );
DFFRX1TS reg_shift_x_Q_reg_26_ ( .D(n342), .CK(clk), .RN(n1910), .Q(
d_ff3_sh_x_out[26]) );
DFFRX1TS reg_shift_x_Q_reg_27_ ( .D(n341), .CK(clk), .RN(n1910), .Q(
d_ff3_sh_x_out[27]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_0_ ( .D(n496), .CK(clk), .RN(n2052), .Q(
d_ff2_Z[0]), .QN(n949) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_1_ ( .D(n495), .CK(clk), .RN(n2040), .Q(
d_ff2_Z[1]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_3_ ( .D(n493), .CK(clk), .RN(n2041), .Q(
d_ff2_Z[3]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_4_ ( .D(n492), .CK(clk), .RN(n2038), .Q(
d_ff2_Z[4]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_5_ ( .D(n491), .CK(clk), .RN(n2042), .Q(
d_ff2_Z[5]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_7_ ( .D(n489), .CK(clk), .RN(n2038), .Q(
d_ff2_Z[7]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_8_ ( .D(n488), .CK(clk), .RN(n2044), .Q(
d_ff2_Z[8]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_9_ ( .D(n487), .CK(clk), .RN(n2050), .Q(
d_ff2_Z[9]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_10_ ( .D(n486), .CK(clk), .RN(n2049), .Q(
d_ff2_Z[10]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_11_ ( .D(n485), .CK(clk), .RN(n2042), .Q(
d_ff2_Z[11]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_12_ ( .D(n484), .CK(clk), .RN(n2051), .Q(
d_ff2_Z[12]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_13_ ( .D(n483), .CK(clk), .RN(n2042), .Q(
d_ff2_Z[13]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_14_ ( .D(n482), .CK(clk), .RN(n2044), .Q(
d_ff2_Z[14]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_15_ ( .D(n481), .CK(clk), .RN(n2050), .Q(
d_ff2_Z[15]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_16_ ( .D(n480), .CK(clk), .RN(n2052), .Q(
d_ff2_Z[16]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_17_ ( .D(n479), .CK(clk), .RN(n2049), .Q(
d_ff2_Z[17]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_18_ ( .D(n478), .CK(clk), .RN(n2042), .Q(
d_ff2_Z[18]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_19_ ( .D(n477), .CK(clk), .RN(n2051), .Q(
d_ff2_Z[19]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_20_ ( .D(n476), .CK(clk), .RN(n2038), .Q(
d_ff2_Z[20]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_22_ ( .D(n474), .CK(clk), .RN(n2041), .Q(
d_ff2_Z[22]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_23_ ( .D(n473), .CK(clk), .RN(n2038), .Q(
d_ff2_Z[23]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_24_ ( .D(n472), .CK(clk), .RN(n2040), .Q(
d_ff2_Z[24]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_25_ ( .D(n471), .CK(clk), .RN(n2041), .Q(
d_ff2_Z[25]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_26_ ( .D(n470), .CK(clk), .RN(n2038), .Q(
d_ff2_Z[26]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_27_ ( .D(n469), .CK(clk), .RN(n2040), .Q(
d_ff2_Z[27]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_28_ ( .D(n468), .CK(clk), .RN(n2041), .Q(
d_ff2_Z[28]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_30_ ( .D(n466), .CK(clk), .RN(n2039), .Q(
d_ff2_Z[30]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_31_ ( .D(n465), .CK(clk), .RN(n2034), .Q(
d_ff2_Z[31]), .QN(n1739) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_0_ ( .D(n463), .CK(clk), .RN(n990), .Q(
d_ff2_Y[0]), .QN(n1744) );
DFFRX1TS reg_shift_y_Q_reg_0_ ( .D(n462), .CK(clk), .RN(n2033), .Q(
d_ff3_sh_y_out[0]), .QN(n1846) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_1_ ( .D(n461), .CK(clk), .RN(n986), .Q(
d_ff2_Y[1]), .QN(n1745) );
DFFRX1TS reg_shift_y_Q_reg_1_ ( .D(n460), .CK(clk), .RN(n989), .Q(
d_ff3_sh_y_out[1]), .QN(n1847) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_3_ ( .D(n457), .CK(clk), .RN(n973), .Q(
d_ff2_Y[3]), .QN(n1728) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_4_ ( .D(n455), .CK(clk), .RN(n2053), .Q(
d_ff2_Y[4]), .QN(n1748) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_5_ ( .D(n453), .CK(clk), .RN(n2053), .Q(
d_ff2_Y[5]), .QN(n1747) );
DFFRX1TS reg_shift_y_Q_reg_5_ ( .D(n452), .CK(clk), .RN(n2053), .Q(
d_ff3_sh_y_out[5]), .QN(n1850) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_6_ ( .D(n451), .CK(clk), .RN(n2053), .Q(
d_ff2_Y[6]), .QN(n1749) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_7_ ( .D(n449), .CK(clk), .RN(n2053), .Q(
d_ff2_Y[7]), .QN(n1750) );
DFFRX1TS reg_shift_y_Q_reg_7_ ( .D(n448), .CK(clk), .RN(n2053), .Q(
d_ff3_sh_y_out[7]), .QN(n1852) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_8_ ( .D(n447), .CK(clk), .RN(n2053), .Q(
d_ff2_Y[8]), .QN(n1751) );
DFFRX1TS reg_shift_y_Q_reg_8_ ( .D(n446), .CK(clk), .RN(n2054), .Q(
d_ff3_sh_y_out[8]), .QN(n1853) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_9_ ( .D(n445), .CK(clk), .RN(n2054), .Q(
d_ff2_Y[9]), .QN(n1752) );
DFFRX1TS reg_shift_y_Q_reg_9_ ( .D(n444), .CK(clk), .RN(n2054), .Q(
d_ff3_sh_y_out[9]), .QN(n1854) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_10_ ( .D(n443), .CK(clk), .RN(n2054), .Q(
d_ff2_Y[10]), .QN(n1753) );
DFFRX1TS reg_shift_y_Q_reg_10_ ( .D(n442), .CK(clk), .RN(n2054), .Q(
d_ff3_sh_y_out[10]), .QN(n1855) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_11_ ( .D(n441), .CK(clk), .RN(n2054), .Q(
d_ff2_Y[11]), .QN(n1754) );
DFFRX1TS reg_shift_y_Q_reg_11_ ( .D(n440), .CK(clk), .RN(n2054), .Q(
d_ff3_sh_y_out[11]), .QN(n1856) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_12_ ( .D(n439), .CK(clk), .RN(n2054), .Q(
d_ff2_Y[12]), .QN(n1755) );
DFFRX1TS reg_shift_y_Q_reg_12_ ( .D(n438), .CK(clk), .RN(n2054), .Q(
d_ff3_sh_y_out[12]), .QN(n1857) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_13_ ( .D(n437), .CK(clk), .RN(n2054), .Q(
d_ff2_Y[13]), .QN(n1756) );
DFFRX1TS reg_shift_y_Q_reg_13_ ( .D(n436), .CK(clk), .RN(n2045), .Q(
d_ff3_sh_y_out[13]), .QN(n1858) );
DFFRX1TS reg_shift_y_Q_reg_14_ ( .D(n434), .CK(clk), .RN(n2045), .Q(
d_ff3_sh_y_out[14]), .QN(n1789) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_15_ ( .D(n433), .CK(clk), .RN(n810), .Q(
d_ff2_Y[15]), .QN(n1730) );
DFFRX1TS reg_shift_y_Q_reg_15_ ( .D(n432), .CK(clk), .RN(n2046), .Q(
d_ff3_sh_y_out[15]), .QN(n1790) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_16_ ( .D(n431), .CK(clk), .RN(n2047), .Q(
d_ff2_Y[16]), .QN(n1731) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_17_ ( .D(n429), .CK(clk), .RN(n2047), .Q(
d_ff2_Y[17]), .QN(n1757) );
DFFRX1TS reg_shift_y_Q_reg_17_ ( .D(n428), .CK(clk), .RN(n2046), .Q(
d_ff3_sh_y_out[17]), .QN(n1859) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_19_ ( .D(n425), .CK(clk), .RN(n2037), .Q(
d_ff2_Y[19]), .QN(n1758) );
DFFRX1TS reg_shift_y_Q_reg_19_ ( .D(n424), .CK(clk), .RN(n2057), .Q(
d_ff3_sh_y_out[19]), .QN(n1860) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_20_ ( .D(n423), .CK(clk), .RN(n2056), .Q(
d_ff2_Y[20]), .QN(n1759) );
DFFRX1TS reg_shift_y_Q_reg_20_ ( .D(n422), .CK(clk), .RN(n2055), .Q(
d_ff3_sh_y_out[20]), .QN(n1861) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_21_ ( .D(n421), .CK(clk), .RN(n2037), .Q(
d_ff2_Y[21]), .QN(n1760) );
DFFRX1TS reg_shift_y_Q_reg_21_ ( .D(n420), .CK(clk), .RN(n2056), .Q(
d_ff3_sh_y_out[21]), .QN(n1862) );
DFFRX1TS reg_shift_y_Q_reg_22_ ( .D(n418), .CK(clk), .RN(n2055), .Q(
d_ff3_sh_y_out[22]), .QN(n1863) );
DFFRX2TS reg_val_muxY_2stage_Q_reg_30_ ( .D(n410), .CK(clk), .RN(n2056), .Q(
d_ff2_Y[30]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_31_ ( .D(n401), .CK(clk), .RN(n2056), .Q(
d_ff2_Y[31]), .QN(n1762) );
DFFRX1TS reg_shift_y_Q_reg_31_ ( .D(n400), .CK(clk), .RN(n810), .Q(
d_ff3_sh_y_out[31]), .QN(n1865) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_0_ ( .D(n399), .CK(clk), .RN(n810), .Q(
d_ff2_X[0]), .QN(n1824) );
DFFRXLTS reg_shift_x_Q_reg_0_ ( .D(n398), .CK(clk), .RN(n2058), .QN(n2060)
);
DFFRX1TS reg_val_muxX_2stage_Q_reg_1_ ( .D(n397), .CK(clk), .RN(n2058), .Q(
d_ff2_X[1]), .QN(n1791) );
DFFRXLTS reg_shift_x_Q_reg_1_ ( .D(n396), .CK(clk), .RN(n2058), .QN(n2061)
);
DFFRX1TS reg_val_muxX_2stage_Q_reg_2_ ( .D(n395), .CK(clk), .RN(n2058), .Q(
d_ff2_X[2]), .QN(n1792) );
DFFRXLTS reg_shift_x_Q_reg_2_ ( .D(n394), .CK(clk), .RN(n2058), .QN(n2063)
);
DFFRX1TS reg_val_muxX_2stage_Q_reg_3_ ( .D(n393), .CK(clk), .RN(n2058), .Q(
d_ff2_X[3]), .QN(n1794) );
DFFRXLTS reg_shift_x_Q_reg_3_ ( .D(n392), .CK(clk), .RN(n2058), .Q(n1010),
.QN(n2065) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_4_ ( .D(n391), .CK(clk), .RN(n2058), .Q(
d_ff2_X[4]), .QN(n1825) );
DFFRXLTS reg_shift_x_Q_reg_4_ ( .D(n390), .CK(clk), .RN(n2058), .QN(n2068)
);
DFFRXLTS reg_shift_x_Q_reg_5_ ( .D(n388), .CK(clk), .RN(n2033), .QN(n2071)
);
DFFRX1TS reg_val_muxX_2stage_Q_reg_6_ ( .D(n387), .CK(clk), .RN(n985), .Q(
d_ff2_X[6]), .QN(n1796) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_7_ ( .D(n385), .CK(clk), .RN(n996), .Q(
d_ff2_X[7]), .QN(n1797) );
DFFRXLTS reg_shift_x_Q_reg_7_ ( .D(n384), .CK(clk), .RN(n990), .QN(n2075) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_9_ ( .D(n381), .CK(clk), .RN(n978), .Q(
d_ff2_X[9]), .QN(n1827) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_11_ ( .D(n377), .CK(clk), .RN(n2039), .Q(
d_ff2_X[11]), .QN(n1828) );
DFFRXLTS reg_shift_x_Q_reg_12_ ( .D(n374), .CK(clk), .RN(n990), .QN(n2085)
);
DFFRX1TS reg_val_muxX_2stage_Q_reg_13_ ( .D(n373), .CK(clk), .RN(n989), .Q(
d_ff2_X[13]), .QN(n1800) );
DFFRXLTS reg_shift_x_Q_reg_13_ ( .D(n372), .CK(clk), .RN(n2034), .QN(n2086)
);
DFFRX1TS reg_val_muxX_2stage_Q_reg_14_ ( .D(n371), .CK(clk), .RN(n985), .Q(
d_ff2_X[14]), .QN(n1736) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_15_ ( .D(n369), .CK(clk), .RN(n991), .Q(
d_ff2_X[15]), .QN(n1763) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_16_ ( .D(n367), .CK(clk), .RN(n968), .Q(
d_ff2_X[16]), .QN(n1737) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_17_ ( .D(n365), .CK(clk), .RN(n2039), .Q(
d_ff2_X[17]), .QN(n1801) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_18_ ( .D(n363), .CK(clk), .RN(n970), .Q(
d_ff2_X[18]), .QN(n1829) );
DFFRXLTS reg_shift_x_Q_reg_18_ ( .D(n362), .CK(clk), .RN(n2034), .QN(n2094)
);
DFFRX1TS reg_val_muxX_2stage_Q_reg_19_ ( .D(n361), .CK(clk), .RN(n967), .Q(
d_ff2_X[19]), .QN(n1802) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_21_ ( .D(n357), .CK(clk), .RN(n2171), .Q(
d_ff2_X[21]), .QN(n1830) );
DFFRXLTS reg_shift_x_Q_reg_21_ ( .D(n356), .CK(clk), .RN(n2044), .QN(n2099)
);
DFFRX1TS reg_LUT_Q_reg_8_ ( .D(n516), .CK(clk), .RN(n1909), .Q(
d_ff3_LUT_out[8]) );
DFFRX1TS d_ff4_Yn_Q_reg_1_ ( .D(n651), .CK(clk), .RN(n2043), .Q(d_ff_Yn[1]),
.QN(n1833) );
DFFSX1TS R_21 ( .D(n2081), .CK(clk), .SN(n968), .Q(n2020) );
DFFSX1TS R_22 ( .D(net6074), .CK(clk), .SN(n970), .Q(n2019) );
DFFSX2TS R_24 ( .D(n2118), .CK(clk), .SN(n2052), .Q(n2017) );
DFFSX2TS R_25 ( .D(n2117), .CK(clk), .SN(n983), .Q(n2016) );
DFFSX1TS R_50 ( .D(net5801), .CK(clk), .SN(n984), .Q(n2007) );
DFFSX1TS R_51 ( .D(n2112), .CK(clk), .SN(n1907), .Q(n2006) );
DFFSX1TS R_52 ( .D(n2111), .CK(clk), .SN(n1908), .Q(n2005) );
DFFRXLTS R_136 ( .D(d_ff2_Y[23]), .CK(clk), .RN(n990), .Q(n1965) );
DFFSX1TS R_137 ( .D(n2102), .CK(clk), .SN(n1908), .Q(n1964) );
DFFSX1TS R_141 ( .D(n2116), .CK(clk), .SN(n1907), .Q(n1961) );
DFFSX1TS R_142 ( .D(n2115), .CK(clk), .SN(n1907), .Q(n1960) );
DFFSX1TS R_143 ( .D(n2114), .CK(clk), .SN(n1907), .Q(n1959) );
DFFSX1TS R_152 ( .D(n2103), .CK(clk), .SN(n1912), .Q(n1952) );
DFFSX1TS R_153 ( .D(n2122), .CK(clk), .SN(n1909), .Q(n1951) );
DFFSX1TS R_154 ( .D(n2121), .CK(clk), .SN(n1909), .Q(n1950) );
DFFSX1TS R_155 ( .D(n2120), .CK(clk), .SN(n1909), .Q(n1949) );
DFFSX1TS R_156 ( .D(n2126), .CK(clk), .SN(n1912), .Q(n1948) );
DFFSX1TS R_157 ( .D(n2125), .CK(clk), .SN(n1912), .Q(n1947) );
DFFSX1TS R_158 ( .D(n2124), .CK(clk), .SN(n1912), .Q(n1946) );
DFFSX1TS R_162 ( .D(n1870), .CK(clk), .SN(n1909), .Q(n1943) );
DFFSX1TS R_163 ( .D(n1872), .CK(clk), .SN(n2052), .Q(n1942) );
DFFSX1TS R_164 ( .D(n2087), .CK(clk), .SN(n2049), .Q(n1941) );
DFFSX2TS R_176 ( .D(n2104), .CK(clk), .SN(n1909), .Q(n1931) );
DFFSX1TS R_214 ( .D(n1872), .CK(clk), .SN(n971), .Q(n1914) );
DFFSX1TS R_215 ( .D(n2070), .CK(clk), .SN(n972), .Q(n1913) );
DFFRXLTS d_ff5_data_out_Q_reg_29_ ( .D(n529), .CK(clk), .RN(n983), .Q(
data_output[29]), .QN(n1906) );
DFFRXLTS d_ff5_data_out_Q_reg_28_ ( .D(n531), .CK(clk), .RN(n982), .Q(
data_output[28]), .QN(n1905) );
DFFRXLTS d_ff5_data_out_Q_reg_27_ ( .D(n533), .CK(clk), .RN(n983), .Q(
data_output[27]), .QN(n1904) );
DFFRXLTS d_ff5_data_out_Q_reg_26_ ( .D(n535), .CK(clk), .RN(n984), .Q(
data_output[26]), .QN(n1903) );
DFFRXLTS d_ff5_data_out_Q_reg_25_ ( .D(n537), .CK(clk), .RN(n2046), .Q(
data_output[25]), .QN(n1902) );
DFFRXLTS d_ff5_data_out_Q_reg_24_ ( .D(n539), .CK(clk), .RN(n2045), .Q(
data_output[24]), .QN(n1901) );
DFFRXLTS d_ff5_data_out_Q_reg_23_ ( .D(n541), .CK(clk), .RN(n811), .Q(
data_output[23]), .QN(n1900) );
DFFRXLTS d_ff5_data_out_Q_reg_22_ ( .D(n543), .CK(clk), .RN(n985), .Q(
data_output[22]), .QN(n1899) );
DFFRXLTS d_ff5_data_out_Q_reg_21_ ( .D(n545), .CK(clk), .RN(n985), .Q(
data_output[21]), .QN(n1898) );
DFFRXLTS d_ff5_data_out_Q_reg_20_ ( .D(n547), .CK(clk), .RN(n986), .Q(
data_output[20]), .QN(n1897) );
DFFRXLTS d_ff5_data_out_Q_reg_19_ ( .D(n549), .CK(clk), .RN(n987), .Q(
data_output[19]), .QN(n1896) );
DFFRXLTS d_ff5_data_out_Q_reg_18_ ( .D(n551), .CK(clk), .RN(n2046), .Q(
data_output[18]), .QN(n1895) );
DFFRXLTS d_ff5_data_out_Q_reg_17_ ( .D(n553), .CK(clk), .RN(n2045), .Q(
data_output[17]), .QN(n1894) );
DFFRXLTS d_ff5_data_out_Q_reg_16_ ( .D(n555), .CK(clk), .RN(n2046), .Q(
data_output[16]), .QN(n1893) );
DFFRXLTS d_ff5_data_out_Q_reg_15_ ( .D(n557), .CK(clk), .RN(n2050), .Q(
data_output[15]), .QN(n1892) );
DFFRXLTS d_ff5_data_out_Q_reg_14_ ( .D(n559), .CK(clk), .RN(n2052), .Q(
data_output[14]), .QN(n1891) );
DFFRXLTS d_ff5_data_out_Q_reg_13_ ( .D(n561), .CK(clk), .RN(n2049), .Q(
data_output[13]), .QN(n1890) );
DFFRXLTS d_ff5_data_out_Q_reg_8_ ( .D(n571), .CK(clk), .RN(n989), .Q(
data_output[8]), .QN(n1885) );
DFFRXLTS d_ff5_data_out_Q_reg_7_ ( .D(n573), .CK(clk), .RN(n990), .Q(
data_output[7]), .QN(n1884) );
DFFRXLTS d_ff5_data_out_Q_reg_6_ ( .D(n575), .CK(clk), .RN(n991), .Q(
data_output[6]), .QN(n1883) );
DFFRXLTS d_ff5_data_out_Q_reg_5_ ( .D(n577), .CK(clk), .RN(n997), .Q(
data_output[5]), .QN(n1882) );
DFFRXLTS d_ff5_data_out_Q_reg_4_ ( .D(n579), .CK(clk), .RN(n997), .Q(
data_output[4]), .QN(n1881) );
DFFRXLTS d_ff5_data_out_Q_reg_3_ ( .D(n581), .CK(clk), .RN(n997), .Q(
data_output[3]), .QN(n1880) );
DFFRXLTS d_ff5_data_out_Q_reg_2_ ( .D(n583), .CK(clk), .RN(n1909), .Q(
data_output[2]), .QN(n1879) );
DFFRXLTS d_ff5_data_out_Q_reg_1_ ( .D(n585), .CK(clk), .RN(n2051), .Q(
data_output[1]), .QN(n1878) );
DFFRXLTS d_ff5_data_out_Q_reg_0_ ( .D(n587), .CK(clk), .RN(n2044), .Q(
data_output[0]), .QN(n1877) );
DFFRXLTS d_ff5_data_out_Q_reg_31_ ( .D(n525), .CK(clk), .RN(n972), .Q(
data_output[31]), .QN(n1875) );
DFFRXLTS d_ff5_data_out_Q_reg_30_ ( .D(n527), .CK(clk), .RN(n984), .Q(
data_output[30]), .QN(n1874) );
DFFRXLTS d_ff5_data_out_Q_reg_9_ ( .D(n569), .CK(clk), .RN(n2032), .Q(
data_output[9]), .QN(n1886) );
DFFRXLTS d_ff5_data_out_Q_reg_10_ ( .D(n567), .CK(clk), .RN(n2032), .Q(
data_output[10]), .QN(n1887) );
DFFRXLTS d_ff5_data_out_Q_reg_11_ ( .D(n565), .CK(clk), .RN(n2032), .Q(
data_output[11]), .QN(n1888) );
DFFRXLTS d_ff5_data_out_Q_reg_12_ ( .D(n563), .CK(clk), .RN(n2032), .Q(
data_output[12]), .QN(n1889) );
DFFRXLTS reg_sign_Q_reg_0_ ( .D(n464), .CK(clk), .RN(n987), .Q(
d_ff3_sign_out), .QN(net7391) );
DFFSX2TS R_57 ( .D(net5805), .CK(clk), .SN(n1907), .Q(n2002) );
DFFSX2TS R_58 ( .D(n2106), .CK(clk), .SN(n1907), .Q(n2001) );
DFFSX2TS R_94 ( .D(net14971), .CK(clk), .SN(n1911), .Q(n1988) );
DFFSX2TS R_99 ( .D(net13662), .CK(clk), .SN(n1911), .Q(n1985) );
DFFSX2TS R_139 ( .D(net14851), .CK(clk), .SN(n982), .Q(n1962) );
DFFSX2TS R_166 ( .D(net14972), .CK(clk), .SN(n1912), .Q(n1939) );
DFFSX2TS R_56 ( .D(n2107), .CK(clk), .SN(n1907), .Q(n2003) );
DFFRXLTS R_90 ( .D(n338), .CK(clk), .RN(n1910), .Q(n1990) );
DFFRXLTS R_93 ( .D(n403), .CK(clk), .RN(n1910), .Q(n1989) );
DFFRXLTS R_98 ( .D(n402), .CK(clk), .RN(n1910), .Q(n1986) );
DFFRXLTS R_138 ( .D(n512), .CK(clk), .RN(n2045), .Q(n1963) );
DFFRXLTS R_168 ( .D(n407), .CK(clk), .RN(n986), .Q(n1937) );
DFFSX2TS R_100 ( .D(n2131), .CK(clk), .SN(n1911), .Q(n1984) );
DFFSX2TS R_167 ( .D(n2110), .CK(clk), .SN(n1911), .Q(n1938) );
DFFSX2TS R_170 ( .D(n2109), .CK(clk), .SN(n982), .Q(n1935) );
DFFSX2TS R_39 ( .D(n2123), .CK(clk), .SN(n983), .Q(n2012) );
DFFSX2TS R_42 ( .D(n899), .CK(clk), .SN(n984), .Q(n2011) );
DFFSX2TS R_54 ( .D(n2113), .CK(clk), .SN(n2055), .Q(n2004) );
DFFSX2TS R_60 ( .D(n917), .CK(clk), .SN(n2057), .Q(n2000) );
DFFSX2TS R_72 ( .D(n918), .CK(clk), .SN(n2056), .Q(n1995) );
DFFSX2TS R_115 ( .D(n2062), .CK(clk), .SN(n2051), .Q(n1977) );
DFFSX2TS R_127 ( .D(n960), .CK(clk), .SN(n984), .Q(n1969) );
DFFSX2TS R_178 ( .D(n2163), .CK(clk), .SN(n972), .Q(n1930) );
DFFSX2TS R_181 ( .D(n2161), .CK(clk), .SN(n974), .Q(n1929) );
DFFSX2TS R_184 ( .D(n886), .CK(clk), .SN(n2033), .Q(n1927) );
DFFSX2TS R_190 ( .D(n2059), .CK(clk), .SN(n974), .Q(n1923) );
DFFSX2TS R_193 ( .D(n884), .CK(clk), .SN(n970), .Q(n1922) );
DFFSX2TS R_196 ( .D(n885), .CK(clk), .SN(n971), .Q(n1921) );
DFFSX2TS R_199 ( .D(n882), .CK(clk), .SN(n972), .QN(n883) );
DFFSX2TS R_202 ( .D(n887), .CK(clk), .SN(n2039), .Q(n1920) );
DFFSX2TS R_205 ( .D(n2166), .CK(clk), .SN(n973), .Q(n1919) );
DFFSX2TS R_208 ( .D(n2164), .CK(clk), .SN(n2034), .Q(n1917) );
DFFSX2TS R_29 ( .D(n2138), .CK(clk), .SN(n973), .Q(n2015) );
DFFSX2TS R_35 ( .D(n2147), .CK(clk), .SN(n996), .QN(n873) );
DFFSX2TS R_62 ( .D(n2149), .CK(clk), .SN(n996), .Q(n1999) );
DFFSX2TS R_80 ( .D(n2153), .CK(clk), .SN(n986), .Q(n1993) );
DFFSX2TS R_103 ( .D(n2148), .CK(clk), .SN(n2040), .Q(n1981) );
DFFSX2TS R_114 ( .D(n2139), .CK(clk), .SN(n970), .Q(n1978) );
DFFSX2TS R_123 ( .D(net5617), .CK(clk), .SN(n987), .Q(n1972) );
DFFSX2TS R_126 ( .D(n2165), .CK(clk), .SN(n983), .Q(n1970) );
DFFSX2TS R_129 ( .D(n2142), .CK(clk), .SN(n991), .Q(n1968) );
DFFSX2TS R_186 ( .D(net5513), .CK(clk), .SN(n2048), .Q(n1926) );
DFFSX2TS R_189 ( .D(net5649), .CK(clk), .SN(n2050), .Q(n1924) );
DFFSX2TS R_207 ( .D(n2165), .CK(clk), .SN(n973), .Q(n1918) );
DFFRXLTS R_102 ( .D(net14325), .CK(clk), .RN(n1910), .Q(n1982) );
DFFSX2TS R_101 ( .D(n2127), .CK(clk), .SN(n1911), .Q(n1983) );
DFFRXLTS R_149 ( .D(n2133), .CK(clk), .RN(n1911), .Q(n1954) );
DFFSX2TS R_148 ( .D(n2134), .CK(clk), .SN(n1912), .Q(n1955) );
DFFSX2TS R_147 ( .D(n2135), .CK(clk), .SN(n1912), .Q(n1956) );
DFFSX2TS R_182 ( .D(net13889), .CK(clk), .SN(n973), .Q(n1928) );
DFFSX2TS R_117 ( .D(n2130), .CK(clk), .SN(n1912), .Q(n1976) );
DFFRXLTS R_23 ( .D(n2119), .CK(clk), .RN(n2050), .Q(n2018) );
DFFSX2TS R_1 ( .D(n2079), .CK(clk), .SN(n991), .Q(n2029) );
DFFSX2TS R_4 ( .D(n816), .CK(clk), .SN(n987), .Q(n2027) );
DFFSX2TS R_7 ( .D(n842), .CK(clk), .SN(n979), .QN(n844) );
DFFSX2TS R_10 ( .D(n875), .CK(clk), .SN(n996), .QN(n876) );
DFFSX2TS R_13 ( .D(n2066), .CK(clk), .SN(n968), .Q(n2026) );
DFFSX2TS R_16 ( .D(n958), .CK(clk), .SN(n2047), .Q(n2024) );
DFFSX2TS R_19 ( .D(n2083), .CK(clk), .SN(n2043), .Q(n2022) );
DFFSX2TS R_27 ( .D(n2100), .CK(clk), .SN(n986), .QN(n902) );
DFFSX2TS R_33 ( .D(n871), .CK(clk), .SN(n979), .Q(n2013) );
DFFSX2TS R_36 ( .D(n872), .CK(clk), .SN(n996), .QN(n874) );
DFFSX2TS R_45 ( .D(n2095), .CK(clk), .SN(n996), .Q(n2010) );
DFFSX2TS R_48 ( .D(n2078), .CK(clk), .SN(n969), .Q(n2008) );
DFFSX2TS R_63 ( .D(n2089), .CK(clk), .SN(n996), .Q(n1998) );
DFFSX2TS R_66 ( .D(n2076), .CK(clk), .SN(n990), .QN(n892) );
DFFSX2TS R_69 ( .D(n2069), .CK(clk), .SN(n2049), .Q(n1997) );
DFFSX2TS R_75 ( .D(n2067), .CK(clk), .SN(n2033), .Q(n1994) );
DFFSX2TS R_78 ( .D(n839), .CK(clk), .SN(n2045), .QN(n841) );
DFFSX2TS R_81 ( .D(n903), .CK(clk), .SN(n987), .Q(n1992) );
DFFSX2TS R_104 ( .D(n959), .CK(clk), .SN(n2038), .Q(n1980) );
DFFSX2TS R_109 ( .D(n893), .CK(clk), .SN(n971), .QN(n895) );
DFFSX2TS R_112 ( .D(n898), .CK(clk), .SN(n2046), .Q(n1979) );
DFFSX2TS R_121 ( .D(n2096), .CK(clk), .SN(n2047), .Q(n1973) );
DFFSX2TS R_124 ( .D(n2064), .CK(clk), .SN(n2034), .Q(n1971) );
DFFSX2TS R_130 ( .D(n2072), .CK(clk), .SN(n2046), .Q(n1967) );
DFFSX2TS R_133 ( .D(n2074), .CK(clk), .SN(n991), .Q(n1966) );
DFFSX2TS R_145 ( .D(n2136), .CK(clk), .SN(n968), .Q(n1957) );
DFFSX2TS R_160 ( .D(n2132), .CK(clk), .SN(n1909), .Q(n1945) );
DFFSX2TS R_172 ( .D(n2093), .CK(clk), .SN(n2045), .Q(n1933) );
DFFSX2TS R_187 ( .D(n832), .CK(clk), .SN(n2041), .Q(n1925) );
DFFSX2TS R_211 ( .D(n2090), .CK(clk), .SN(n2040), .Q(n1915) );
DFFSX2TS R_3 ( .D(n2154), .CK(clk), .SN(n986), .Q(n2028) );
DFFSX2TS R_18 ( .D(n2146), .CK(clk), .SN(n2043), .Q(n2023) );
DFFSX2TS R_65 ( .D(n2144), .CK(clk), .SN(n991), .QN(n891) );
DFFSX2TS R_108 ( .D(n2137), .CK(clk), .SN(n2044), .QN(n894) );
DFFSX2TS R_144 ( .D(net5649), .CK(clk), .SN(n969), .Q(n1958) );
DFFSX2TS R_171 ( .D(n2151), .CK(clk), .SN(n2046), .Q(n1934) );
DFFSX2TS R_210 ( .D(n2149), .CK(clk), .SN(n2048), .Q(n1916) );
DFFSX2TS R_14 ( .D(n821), .CK(clk), .SN(n2034), .Q(n2025) );
DFFSX2TS R_20 ( .D(n940), .CK(clk), .SN(n2043), .Q(n2021) );
DFFSX2TS R_46 ( .D(net15447), .CK(clk), .SN(n995), .Q(n2009) );
DFFSX2TS R_161 ( .D(n940), .CK(clk), .SN(n973), .Q(n1944) );
DFFRXLTS R_175 ( .D(n2030), .CK(clk), .RN(n2051), .Q(n1932) );
DFFRX4TS reg_val_muxY_2stage_Q_reg_25_ ( .D(n415), .CK(clk), .RN(n2037), .Q(
d_ff2_Y[25]), .QN(n1866) );
DFFRX4TS reg_val_muxY_2stage_Q_reg_27_ ( .D(n413), .CK(clk), .RN(n2057), .Q(
d_ff2_Y[27]), .QN(n1869) );
DFFRX4TS reg_val_muxY_2stage_Q_reg_24_ ( .D(n416), .CK(clk), .RN(n2057), .Q(
d_ff2_Y[24]), .QN(n2157) );
DFFRX4TS cont_var_count_reg_1_ ( .D(n729), .CK(clk), .RN(n967), .Q(
cont_var_out[1]), .QN(n2031) );
DFFRX4TS reg_val_muxY_2stage_Q_reg_26_ ( .D(n414), .CK(clk), .RN(n2055), .Q(
d_ff2_Y[26]), .QN(n2160) );
DFFRX2TS reg_val_muxX_2stage_Q_reg_29_ ( .D(n347), .CK(clk), .RN(n971), .Q(
d_ff2_X[29]), .QN(n1793) );
DFFRX4TS cont_iter_count_reg_2_ ( .D(n726), .CK(clk), .RN(n2035), .Q(
cont_iter_out_2_), .QN(net6713) );
DFFRX4TS cont_var_count_reg_0_ ( .D(n724), .CK(clk), .RN(n2035), .Q(
cont_var_out[0]), .QN(net6633) );
DFFRX4TS reg_val_muxX_2stage_Q_reg_24_ ( .D(n352), .CK(clk), .RN(n967), .Q(
d_ff2_X[24]), .QN(n1876) );
DFFRX4TS reg_val_muxY_2stage_Q_reg_28_ ( .D(n412), .CK(clk), .RN(n2056), .Q(
d_ff2_Y[28]), .QN(n1873) );
DFFRX4TS reg_val_muxX_2stage_Q_reg_26_ ( .D(n350), .CK(clk), .RN(n982), .Q(
d_ff2_X[26]), .QN(n1868) );
DFFRX4TS reg_val_muxX_2stage_Q_reg_25_ ( .D(n351), .CK(clk), .RN(n1909), .Q(
d_ff2_X[25]), .QN(n1807) );
DFFRHQX1TS reg_shift_x_Q_reg_16_ ( .D(n366), .CK(clk), .RN(n2171), .Q(n1727)
);
DFFRHQX1TS reg_shift_y_Q_reg_16_ ( .D(n430), .CK(clk), .RN(n974), .Q(
d_ff3_sh_y_out[16]) );
DFFRHQX2TS reg_val_muxY_2stage_Q_reg_29_ ( .D(n411), .CK(clk), .RN(n2171),
.Q(d_ff2_Y[29]) );
DFFRHQX8TS cordic_FSM_state_reg_reg_0_ ( .D(n730), .CK(clk), .RN(n331), .Q(
cordic_FSM_state_reg_0_) );
DFFRXLTS d_ff5_Q_reg_23_ ( .D(n542), .CK(clk), .RN(n2047), .Q(
sign_inv_out[23]), .QN(n1782) );
DFFRXLTS reg_shift_y_Q_reg_6_ ( .D(n450), .CK(clk), .RN(n2053), .Q(
d_ff3_sh_y_out[6]), .QN(n1851) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_5_ ( .D(n389), .CK(clk), .RN(n2058), .Q(
d_ff2_X[5]), .QN(n1795) );
DFFRX4TS reg_operation_Q_reg_0_ ( .D(n723), .CK(clk), .RN(n2035), .Q(
d_ff1_operation_out), .QN(net6761) );
DFFRX4TS reg_ch_mux_2_Q_reg_0_ ( .D(n2169), .CK(clk), .RN(n1908), .Q(
sel_mux_2_reg[0]), .QN(net7462) );
DFFRX4TS reg_ch_mux_2_Q_reg_1_ ( .D(n2168), .CK(clk), .RN(n1907), .Q(
sel_mux_2_reg[1]), .QN(n1871) );
DFFRX4TS reg_val_muxY_2stage_Q_reg_23_ ( .D(n417), .CK(clk), .RN(n2055), .Q(
d_ff2_Y[23]), .QN(n1823) );
DFFRX4TS reg_val_muxX_2stage_Q_reg_27_ ( .D(n349), .CK(clk), .RN(n967), .Q(
d_ff2_X[27]), .QN(n1867) );
DFFRX2TS d_ff4_Zn_Q_reg_21_ ( .D(n663), .CK(clk), .RN(n971), .Q(d_ff_Zn[21]),
.QN(n1743) );
DFFRX2TS reg_Z0_Q_reg_0_ ( .D(n720), .CK(clk), .RN(n2035), .Q(d_ff1_Z[0]) );
DFFRX2TS reg_Z0_Q_reg_3_ ( .D(n717), .CK(clk), .RN(n2057), .Q(d_ff1_Z[3]) );
DFFRX2TS reg_Z0_Q_reg_4_ ( .D(n716), .CK(clk), .RN(n2055), .Q(d_ff1_Z[4]) );
DFFRX2TS reg_Z0_Q_reg_2_ ( .D(n718), .CK(clk), .RN(n2035), .Q(d_ff1_Z[2]) );
DFFRX2TS d_ff4_Yn_Q_reg_2_ ( .D(n650), .CK(clk), .RN(n1908), .Q(d_ff_Yn[2]),
.QN(n1844) );
DFFRX1TS reg_Z0_Q_reg_19_ ( .D(n701), .CK(clk), .RN(n1000), .Q(d_ff1_Z[19])
);
DFFRHQX2TS reg_val_muxX_2stage_Q_reg_30_ ( .D(n346), .CK(clk), .RN(n974),
.Q(d_ff2_X[30]) );
DFFRX4TS reg_val_muxY_2stage_Q_reg_14_ ( .D(n435), .CK(clk), .RN(n2037), .Q(
d_ff2_Y[14]), .QN(n1729) );
DFFRX4TS reg_Z0_Q_reg_30_ ( .D(n690), .CK(clk), .RN(n2041), .Q(d_ff1_Z[30])
);
DFFRX4TS reg_Z0_Q_reg_26_ ( .D(n694), .CK(clk), .RN(n2048), .Q(d_ff1_Z[26])
);
DFFRX4TS reg_Z0_Q_reg_25_ ( .D(n695), .CK(clk), .RN(n2041), .Q(d_ff1_Z[25])
);
DFFRX4TS reg_Z0_Q_reg_24_ ( .D(n696), .CK(clk), .RN(n2040), .Q(d_ff1_Z[24])
);
DFFRX4TS reg_Z0_Q_reg_23_ ( .D(n697), .CK(clk), .RN(n2041), .Q(d_ff1_Z[23])
);
DFFRX4TS reg_Z0_Q_reg_22_ ( .D(n698), .CK(clk), .RN(n1000), .Q(d_ff1_Z[22])
);
DFFRX4TS reg_Z0_Q_reg_21_ ( .D(n699), .CK(clk), .RN(n1000), .Q(d_ff1_Z[21])
);
DFFRHQX2TS reg_LUT_Q_reg_21_ ( .D(n503), .CK(clk), .RN(n973), .Q(
d_ff3_LUT_out[21]) );
DFFSHQX8TS reg_region_flag_Q_reg_0_ ( .D(n1093), .CK(clk), .SN(n973), .Q(
net12499) );
DFFSX2TS R_169 ( .D(net14688), .CK(clk), .SN(n1909), .Q(n1936) );
DFFRHQX8TS cordic_FSM_state_reg_reg_3_ ( .D(n732), .CK(clk), .RN(n331), .Q(
net15081) );
DFFRHQX2TS d_ff4_Yn_Q_reg_28_ ( .D(n624), .CK(clk), .RN(n978), .Q(net15103)
);
DFFRHQX2TS d_ff4_Yn_Q_reg_3_ ( .D(n649), .CK(clk), .RN(n1908), .Q(net15101)
);
DFFRHQX8TS cordic_FSM_state_reg_reg_2_ ( .D(n731), .CK(clk), .RN(n331), .Q(
n965) );
DFFRHQX2TS reg_ch_mux_1_Q_reg_0_ ( .D(n2170), .CK(clk), .RN(n1907), .Q(n963)
);
DFFRX4TS d_ff5_Q_reg_31_ ( .D(n526), .CK(clk), .RN(n967), .Q(
data_output2_31_), .QN(n962) );
DFFRX1TS d_ff4_Yn_Q_reg_8_ ( .D(n644), .CK(clk), .RN(n2048), .Q(d_ff_Yn[8]),
.QN(n1835) );
DFFRX1TS d_ff4_Yn_Q_reg_6_ ( .D(n646), .CK(clk), .RN(n1908), .Q(d_ff_Yn[6]),
.QN(n1832) );
DFFRX4TS reg_Z0_Q_reg_1_ ( .D(n719), .CK(clk), .RN(n2035), .Q(d_ff1_Z[1]) );
DFFRHQX8TS cont_iter_count_reg_0_ ( .D(n728), .CK(clk), .RN(n2035), .Q(
net15394) );
DFFRHQX8TS cont_iter_count_reg_3_ ( .D(n725), .CK(clk), .RN(n2035), .Q(
net15397) );
DFFRHQX2TS reg_ch_mux_3_Q_reg_0_ ( .D(n910), .CK(clk), .RN(n1907), .Q(n945)
);
DFFRXLTS R_87 ( .D(n339), .CK(clk), .RN(n1910), .Q(n1991) );
DFFSX1TS R_118 ( .D(n2129), .CK(clk), .SN(n1912), .Q(n1975) );
DFFSRHQX4TS reg_LUT_Q_reg_18_ ( .D(n506), .CK(clk), .SN(1'b1), .RN(n973),
.Q(d_ff3_LUT_out[18]) );
DFFRXLTS reg_shift_y_Q_reg_4_ ( .D(n454), .CK(clk), .RN(n2053), .Q(
d_ff3_sh_y_out[4]), .QN(n1849) );
DFFRXLTS reg_shift_y_Q_reg_3_ ( .D(n456), .CK(clk), .RN(n2053), .Q(
d_ff3_sh_y_out[3]), .QN(n1848) );
DFFRX4TS reg_val_muxX_2stage_Q_reg_31_ ( .D(n337), .CK(clk), .RN(n970), .Q(
d_ff2_X[31]) );
DFFSX2TS R_221 ( .D(n877), .CK(clk), .SN(n978), .QN(n878) );
DFFSX2TS R_224 ( .D(n1805), .CK(clk), .SN(n811), .Q(n915) );
DFFSX2TS R_226 ( .D(n1175), .CK(clk), .SN(n2048), .Q(n914) );
DFFSX2TS R_227 ( .D(n1174), .CK(clk), .SN(n2048), .Q(n913) );
DFFSX2TS R_228 ( .D(n1173), .CK(clk), .SN(n2048), .Q(n912) );
DFFSX4TS R_236 ( .D(n940), .CK(clk), .SN(n974), .Q(n896) );
DFFSX2TS R_237 ( .D(net6644), .CK(clk), .SN(n969), .Q(n889) );
DFFSX2TS R_238 ( .D(n938), .CK(clk), .SN(n990), .Q(n881) );
DFFSX2TS R_241 ( .D(n2156), .CK(clk), .SN(n811), .Q(n868), .QN(n867) );
DFFSX2TS R_242 ( .D(n2105), .CK(clk), .SN(n2050), .Q(n866) );
DFFSX4TS R_243 ( .D(n2162), .CK(clk), .SN(n974), .Q(n865), .QN(n843) );
DFFSX2TS R_245 ( .D(n2150), .CK(clk), .SN(n2047), .Q(n863), .QN(n862) );
DFFSX2TS R_246 ( .D(n2145), .CK(clk), .SN(n990), .Q(n861) );
DFFSX2TS R_247 ( .D(n2141), .CK(clk), .SN(n984), .Q(n860) );
DFFSX2TS R_248 ( .D(n2140), .CK(clk), .SN(n2046), .Q(n859) );
DFFSX2TS R_249 ( .D(n2152), .CK(clk), .SN(n2045), .Q(n858) );
DFFSX2TS R_250 ( .D(n2143), .CK(clk), .SN(n990), .Q(n857), .QN(n840) );
DFFSX2TS R_251 ( .D(n2155), .CK(clk), .SN(n987), .Q(n856), .QN(n855) );
DFFSX2TS R_252 ( .D(n2159), .CK(clk), .SN(n2034), .Q(n854) );
DFFSX2TS R_253 ( .D(n2158), .CK(clk), .SN(n971), .Q(n853) );
DFFSX2TS R_254 ( .D(n1870), .CK(clk), .SN(n968), .Q(n852) );
DFFSX2TS R_255 ( .D(net6643), .CK(clk), .SN(n2171), .Q(n851) );
DFFSX2TS R_256 ( .D(net6643), .CK(clk), .SN(n2045), .Q(n850) );
DFFSX2TS R_258 ( .D(net13657), .CK(clk), .SN(n1911), .Q(n848) );
DFFSX2TS R_259 ( .D(net5449), .CK(clk), .SN(n972), .Q(n847) );
DFFSX2TS R_260 ( .D(net5420), .CK(clk), .SN(n2039), .Q(n846) );
DFFSX2TS R_261 ( .D(n821), .CK(clk), .SN(n979), .Q(n845) );
DFFSX2TS R_262 ( .D(n821), .CK(clk), .SN(n971), .Q(n838) );
DFFRHQX8TS cordic_FSM_state_reg_reg_1_ ( .D(cordic_FSM_state_next_1_), .CK(
clk), .RN(n331), .Q(net15128) );
DFFRX4TS reg_shift_x_Q_reg_20_ ( .D(n358), .CK(clk), .RN(n972), .Q(n835),
.QN(n2098) );
DFFSX2TS R_257 ( .D(n966), .CK(clk), .SN(n2040), .Q(n849), .QN(n833) );
DFFSX4TS R_235 ( .D(n938), .CK(clk), .SN(n2039), .Q(n906) );
DFFRX4TS reg_val_muxX_2stage_Q_reg_23_ ( .D(n353), .CK(clk), .RN(n967), .Q(
d_ff2_X[23]), .QN(n1804) );
DFFSX4TS R_240 ( .D(n2167), .CK(clk), .SN(n978), .Q(n870), .QN(n869) );
DFFRXLTS d_ff5_Q_reg_9_ ( .D(n570), .CK(clk), .RN(n989), .Q(sign_inv_out[9]),
.QN(n1735) );
DFFRXLTS d_ff5_Q_reg_27_ ( .D(n534), .CK(clk), .RN(n982), .Q(
sign_inv_out[27]), .QN(n1786) );
DFFRXLTS R_97 ( .D(net14457), .CK(clk), .RN(n1911), .Q(n1987) );
DFFRX1TS d_ff4_Yn_Q_reg_10_ ( .D(n642), .CK(clk), .RN(n1908), .Q(d_ff_Yn[10]), .QN(n1841) );
DFFRX4TS reg_val_muxZ_2stage_Q_reg_21_ ( .D(n475), .CK(clk), .RN(n2048), .Q(
d_ff2_Z[21]), .QN(n948) );
DFFRX4TS reg_val_muxZ_2stage_Q_reg_2_ ( .D(n494), .CK(clk), .RN(n2048), .Q(
d_ff2_Z[2]) );
DFFRX4TS reg_val_muxZ_2stage_Q_reg_6_ ( .D(n490), .CK(clk), .RN(n2048), .Q(
d_ff2_Z[6]) );
DFFSX4TS R_244 ( .D(n966), .CK(clk), .SN(n811), .Q(n864) );
DFFRHQX8TS cont_iter_count_reg_1_ ( .D(n727), .CK(clk), .RN(n1908), .Q(n934)
);
DFFRHQX8TS reg_region_flag_Q_reg_1_ ( .D(n721), .CK(clk), .RN(n2035), .Q(
net15155) );
DFFRX2TS R_119 ( .D(n2128), .CK(clk), .RN(n1911), .Q(n1974) );
DFFRHQX2TS reg_val_muxX_2stage_Q_reg_28_ ( .D(n348), .CK(clk), .RN(n974),
.Q(d_ff2_X[28]) );
DFFSX4TS R_239 ( .D(n821), .CK(clk), .SN(n978), .Q(n880) );
DFFRX2TS R_165 ( .D(n343), .CK(clk), .RN(n1910), .Q(n1940) );
DFFRXLTS R_151 ( .D(d_ff2_X[23]), .CK(clk), .RN(n1910), .Q(n1953) );
DFFRX1TS reg_Z0_Q_reg_7_ ( .D(n713), .CK(clk), .RN(n2055), .Q(d_ff1_Z[7]) );
DFFRX1TS reg_Z0_Q_reg_5_ ( .D(n715), .CK(clk), .RN(n2056), .Q(d_ff1_Z[5]) );
DFFRX1TS reg_Z0_Q_reg_12_ ( .D(n708), .CK(clk), .RN(n2057), .Q(d_ff1_Z[12])
);
DFFRX1TS reg_Z0_Q_reg_8_ ( .D(n712), .CK(clk), .RN(n2057), .Q(d_ff1_Z[8]) );
DFFRX1TS reg_Z0_Q_reg_13_ ( .D(n707), .CK(clk), .RN(n1000), .Q(d_ff1_Z[13])
);
DFFRX1TS reg_Z0_Q_reg_20_ ( .D(n700), .CK(clk), .RN(n1000), .Q(d_ff1_Z[20])
);
DFFRX1TS reg_Z0_Q_reg_15_ ( .D(n705), .CK(clk), .RN(n1000), .Q(d_ff1_Z[15])
);
DFFRX1TS reg_Z0_Q_reg_14_ ( .D(n706), .CK(clk), .RN(n1000), .Q(d_ff1_Z[14])
);
DFFRX1TS reg_Z0_Q_reg_9_ ( .D(n711), .CK(clk), .RN(n2037), .Q(d_ff1_Z[9]) );
DFFRX1TS reg_Z0_Q_reg_11_ ( .D(n709), .CK(clk), .RN(n2055), .Q(d_ff1_Z[11])
);
DFFRX1TS reg_Z0_Q_reg_10_ ( .D(n710), .CK(clk), .RN(n2056), .Q(d_ff1_Z[10])
);
DFFRX2TS reg_Z0_Q_reg_27_ ( .D(n693), .CK(clk), .RN(n2040), .Q(d_ff1_Z[27])
);
DFFRX1TS reg_Z0_Q_reg_18_ ( .D(n702), .CK(clk), .RN(n1000), .Q(d_ff1_Z[18])
);
DFFRX1TS reg_Z0_Q_reg_17_ ( .D(n703), .CK(clk), .RN(n1000), .Q(d_ff1_Z[17])
);
DFFRX1TS reg_Z0_Q_reg_16_ ( .D(n704), .CK(clk), .RN(n1000), .Q(d_ff1_Z[16])
);
DFFSX2TS R_30 ( .D(n904), .CK(clk), .SN(n2052), .Q(n2014) );
DFFSX1TS R_70 ( .D(n821), .CK(clk), .SN(n2050), .Q(n1996) );
DFFRHQX2TS reg_LUT_Q_reg_27_ ( .D(n497), .CK(clk), .RN(n973), .Q(
d_ff3_LUT_out[27]) );
DFFRX1TS reg_shift_x_Q_reg_31_ ( .D(n336), .CK(clk), .RN(n972), .Q(
d_ff3_sh_x_out[31]) );
DFFRX1TS reg_shift_y_Q_reg_2_ ( .D(n458), .CK(clk), .RN(n2039), .Q(
d_ff3_sh_y_out[2]) );
DFFRX1TS reg_shift_y_Q_reg_18_ ( .D(n426), .CK(clk), .RN(n2057), .Q(
d_ff3_sh_y_out[18]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_22_ ( .D(n419), .CK(clk), .RN(n2057), .Q(
d_ff2_Y[22]), .QN(n1761) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_20_ ( .D(n359), .CK(clk), .RN(n969), .Q(
d_ff2_X[20]), .QN(n1803) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_22_ ( .D(n355), .CK(clk), .RN(n968), .Q(
d_ff2_X[22]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_2_ ( .D(n459), .CK(clk), .RN(n985), .Q(
d_ff2_Y[2]), .QN(n1746) );
DFFRXLTS reg_shift_y_Q_reg_26_ ( .D(n406), .CK(clk), .RN(n989), .Q(
d_ff3_sh_y_out[26]), .QN(n926) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_8_ ( .D(n383), .CK(clk), .RN(n2039), .Q(
d_ff2_X[8]), .QN(n1826) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_10_ ( .D(n379), .CK(clk), .RN(n991), .Q(
d_ff2_X[10]), .QN(n1798) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_12_ ( .D(n375), .CK(clk), .RN(n979), .Q(
d_ff2_X[12]), .QN(n1799) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_18_ ( .D(n427), .CK(clk), .RN(n810), .Q(
d_ff2_Y[18]) );
DFFRHQX2TS d_ff5_Q_reg_18_ ( .D(n552), .CK(clk), .RN(n2171), .Q(
sign_inv_out[18]) );
DFFRXLTS reg_Z0_Q_reg_28_ ( .D(n692), .CK(clk), .RN(n2038), .Q(d_ff1_Z[28]),
.QN(n950) );
DFFRX1TS reg_Z0_Q_reg_6_ ( .D(n714), .CK(clk), .RN(n2037), .Q(d_ff1_Z[6]) );
DFFRX1TS reg_Z0_Q_reg_31_ ( .D(n689), .CK(clk), .RN(n2050), .Q(d_ff1_Z[31])
);
DFFRX1TS d_ff5_Q_reg_10_ ( .D(n568), .CK(clk), .RN(n2043), .Q(
sign_inv_out[10]), .QN(n1770) );
DFFRHQX4TS d_ff4_Xn_Q_reg_13_ ( .D(n607), .CK(clk), .RN(n2044), .Q(n941) );
DFFRHQX4TS d_ff4_Xn_Q_reg_12_ ( .D(n608), .CK(clk), .RN(n2032), .Q(net15424)
);
DFFRHQX4TS d_ff4_Xn_Q_reg_10_ ( .D(n610), .CK(clk), .RN(n2032), .Q(n943) );
DFFRXLTS reg_shift_x_Q_reg_22_ ( .D(n354), .CK(clk), .RN(n984), .Q(n928),
.QN(n2101) );
DFFRXLTS reg_shift_x_Q_reg_8_ ( .D(n382), .CK(clk), .RN(n986), .Q(n921),
.QN(n2077) );
DFFRXLTS reg_shift_x_Q_reg_10_ ( .D(n378), .CK(clk), .RN(n2033), .Q(n931),
.QN(n2082) );
DFFRX1TS reg_shift_x_Q_reg_9_ ( .D(n380), .CK(clk), .RN(n979), .QN(n2080) );
DFFRX1TS reg_shift_x_Q_reg_15_ ( .D(n368), .CK(clk), .RN(n968), .QN(n2091)
);
DFFRX1TS reg_shift_x_Q_reg_14_ ( .D(n370), .CK(clk), .RN(n986), .QN(n2088)
);
DFFRX1TS reg_shift_x_Q_reg_19_ ( .D(n360), .CK(clk), .RN(n972), .QN(n2097)
);
DFFRX1TS reg_shift_x_Q_reg_11_ ( .D(n376), .CK(clk), .RN(n987), .QN(n2084)
);
DFFRX1TS reg_shift_x_Q_reg_17_ ( .D(n364), .CK(clk), .RN(n969), .QN(n2092)
);
DFFRX1TS reg_shift_x_Q_reg_6_ ( .D(n386), .CK(clk), .RN(n989), .QN(n2073) );
DFFRX1TS reg_shift_x_Q_reg_24_ ( .D(n344), .CK(clk), .RN(n1910), .QN(n2108)
);
DFFRX2TS reg_Z0_Q_reg_29_ ( .D(n691), .CK(clk), .RN(n2052), .Q(d_ff1_Z[29])
);
CLKMX2X3TS U795 ( .A(data_in[20]), .B(d_ff1_Z[20]), .S0(n1083), .Y(n700) );
CLKMX2X3TS U796 ( .A(data_in[17]), .B(d_ff1_Z[17]), .S0(n1083), .Y(n703) );
CLKMX2X3TS U797 ( .A(data_in[15]), .B(d_ff1_Z[15]), .S0(n1083), .Y(n705) );
CLKMX2X2TS U798 ( .A(n931), .B(d_ff2_X[10]), .S0(net14325), .Y(n378) );
CLKMX2X3TS U799 ( .A(data_in[18]), .B(d_ff1_Z[18]), .S0(n1083), .Y(n702) );
CLKMX2X3TS U800 ( .A(data_in[16]), .B(d_ff1_Z[16]), .S0(n1083), .Y(n704) );
INVX2TS U801 ( .A(n981), .Y(n2038) );
MXI2X1TS U802 ( .A(n1775), .B(n1892), .S0(n1700), .Y(n557) );
AO21X2TS U803 ( .A0(d_ff3_LUT_out[22]), .A1(net14753), .B0(n1530), .Y(n502)
);
CLKMX2X2TS U804 ( .A(d_ff3_sh_x_out[31]), .B(d_ff2_X[31]), .S0(net14072),
.Y(n336) );
CLKMX2X3TS U805 ( .A(data_in[14]), .B(d_ff1_Z[14]), .S0(n1083), .Y(n706) );
AO21X1TS U806 ( .A0(d_ff3_LUT_out[8]), .A1(net14753), .B0(n1721), .Y(n516)
);
CLKINVX2TS U807 ( .A(n809), .Y(n811) );
CLKMX2X3TS U808 ( .A(d_ff3_sh_y_out[18]), .B(d_ff2_Y[18]), .S0(net14325),
.Y(n426) );
CLKMX2X3TS U809 ( .A(data_in[31]), .B(d_ff1_Z[31]), .S0(n953), .Y(n689) );
INVX2TS U810 ( .A(n809), .Y(n810) );
CLKINVX3TS U811 ( .A(n1422), .Y(n2048) );
NAND3X2TS U812 ( .A(n1124), .B(n1123), .C(n1125), .Y(n526) );
NAND3X4TS U813 ( .A(n1351), .B(n1352), .C(n1350), .Y(n474) );
NAND3X4TS U814 ( .A(n1354), .B(n1355), .C(n1353), .Y(n473) );
NAND3X2TS U815 ( .A(n1292), .B(n1291), .C(n1290), .Y(n520) );
NAND2X1TS U816 ( .A(n1271), .B(sign_inv_out[16]), .Y(n1253) );
NAND2X2TS U817 ( .A(n1007), .B(n1538), .Y(n1170) );
NAND2X2TS U818 ( .A(n1046), .B(n1554), .Y(n1311) );
AND2X4TS U819 ( .A(n980), .B(d_ff_Zn[7]), .Y(n1080) );
NAND2X1TS U820 ( .A(n1087), .B(n943), .Y(n1207) );
NAND2X2TS U821 ( .A(n1086), .B(n1455), .Y(n1217) );
OR2X2TS U822 ( .A(n1025), .B(n1752), .Y(n1028) );
NAND3X1TS U823 ( .A(n1708), .B(d_ff1_Z[31]), .C(n1365), .Y(n1171) );
NAND2X2TS U824 ( .A(n1006), .B(d_ff_Yn[2]), .Y(n1237) );
NAND2X2TS U825 ( .A(n1036), .B(d_ff_Yn[26]), .Y(n1274) );
NAND2X1TS U826 ( .A(net14688), .B(d_ff3_LUT_out[4]), .Y(n1291) );
NAND2X1TS U827 ( .A(n993), .B(n1544), .Y(n1154) );
NAND2X1TS U828 ( .A(n1271), .B(sign_inv_out[18]), .Y(n1153) );
INVX2TS U829 ( .A(result_add_subt[31]), .Y(net5649) );
NAND2X1TS U830 ( .A(n1079), .B(d_ff_Zn[19]), .Y(n1169) );
INVX2TS U831 ( .A(n941), .Y(n942) );
INVX2TS U832 ( .A(result_add_subt[5]), .Y(n2141) );
INVX2TS U833 ( .A(result_add_subt[19]), .Y(n2152) );
INVX2TS U834 ( .A(result_add_subt[9]), .Y(n2145) );
INVX2TS U835 ( .A(result_add_subt[4]), .Y(n2140) );
INVX2TS U836 ( .A(result_add_subt[24]), .Y(net5449) );
INVX2TS U837 ( .A(result_add_subt[7]), .Y(n2143) );
INVX2TS U838 ( .A(result_add_subt[22]), .Y(n2155) );
INVX2TS U839 ( .A(result_add_subt[25]), .Y(n2158) );
INVX2TS U840 ( .A(result_add_subt[17]), .Y(n2150) );
CLKMX2X4TS U841 ( .A(n853), .B(n2000), .S0(n812), .Y(n917) );
OAI21X2TS U842 ( .A0(n817), .A1(net13654), .B0(n1721), .Y(n1292) );
INVX2TS U843 ( .A(result_add_subt[28]), .Y(net5420) );
NAND2XLTS U844 ( .A(n1087), .B(n1458), .Y(n1250) );
NAND2X1TS U845 ( .A(net14400), .B(net14399), .Y(net14367) );
NAND2X1TS U846 ( .A(n1075), .B(n1003), .Y(n1363) );
NAND2X1TS U847 ( .A(n1057), .B(n1004), .Y(n1162) );
NAND2X1TS U848 ( .A(n1056), .B(n1003), .Y(n1159) );
NAND2X1TS U849 ( .A(n1069), .B(n1004), .Y(n1453) );
NAND2X1TS U850 ( .A(n1074), .B(n1003), .Y(n1360) );
NAND2X2TS U851 ( .A(n980), .B(d_ff_Zn[6]), .Y(n1115) );
INVX2TS U852 ( .A(result_add_subt[15]), .Y(n2149) );
INVX2TS U853 ( .A(result_add_subt[29]), .Y(n2165) );
NOR2X2TS U854 ( .A(n1718), .B(n817), .Y(n1720) );
NAND2X1TS U855 ( .A(net15017), .B(d_ff3_sh_x_out[26]), .Y(n1396) );
NOR2X4TS U856 ( .A(n1725), .B(net13805), .Y(n1529) );
OR2X2TS U857 ( .A(n1025), .B(n1753), .Y(n1027) );
INVX2TS U858 ( .A(result_add_subt[3]), .Y(net5617) );
INVX2TS U859 ( .A(result_add_subt[13]), .Y(n2147) );
NOR2X2TS U860 ( .A(net14972), .B(n927), .Y(n1415) );
NAND2X2TS U861 ( .A(n1086), .B(n1463), .Y(n1273) );
NAND2X2TS U862 ( .A(n1296), .B(n1295), .Y(n1393) );
INVX2TS U863 ( .A(result_add_subt[12]), .Y(net13887) );
INVX2TS U864 ( .A(result_add_subt[10]), .Y(n1519) );
NAND2X2TS U865 ( .A(n1122), .B(data_output2_31_), .Y(n1123) );
NAND2X2TS U866 ( .A(n1046), .B(n1533), .Y(n1368) );
NAND2X2TS U867 ( .A(n1036), .B(d_ff_Yn[20]), .Y(n1140) );
NAND2X2TS U868 ( .A(n1036), .B(d_ff_Yn[11]), .Y(n1270) );
INVX2TS U869 ( .A(result_add_subt[2]), .Y(n2139) );
NAND2X2TS U870 ( .A(n1034), .B(n1552), .Y(n1228) );
NAND2X2TS U871 ( .A(n1034), .B(n1545), .Y(n1247) );
NAND2X2TS U872 ( .A(n1089), .B(sign_inv_out[24]), .Y(n1197) );
NAND2X2TS U873 ( .A(n994), .B(n1460), .Y(n1223) );
INVX2TS U874 ( .A(result_add_subt[11]), .Y(n2146) );
INVX2TS U875 ( .A(result_add_subt[8]), .Y(n2144) );
INVX2TS U876 ( .A(result_add_subt[20]), .Y(n2153) );
INVX2TS U877 ( .A(result_add_subt[18]), .Y(n2151) );
INVX2TS U878 ( .A(result_add_subt[0]), .Y(n2137) );
NAND2X2TS U879 ( .A(n1036), .B(n622), .Y(n1108) );
NAND2X2TS U880 ( .A(n1036), .B(n1559), .Y(n1264) );
CLKINVX3TS U881 ( .A(n1723), .Y(n1527) );
NAND3X2TS U882 ( .A(n1708), .B(d_ff1_Z[0]), .C(n1041), .Y(n1327) );
NAND2X2TS U883 ( .A(n1006), .B(d_ff_Yn[10]), .Y(n1209) );
NAND2X2TS U884 ( .A(n1036), .B(n1551), .Y(n1252) );
NAND2X2TS U885 ( .A(n1034), .B(d_ff_Yn[12]), .Y(n1267) );
NAND2X2TS U886 ( .A(n1034), .B(d_ff_Yn[21]), .Y(n1242) );
NAND3X4TS U887 ( .A(n1401), .B(d_ff2_Y[29]), .C(n1528), .Y(n1392) );
NAND2X2TS U888 ( .A(n1034), .B(n1554), .Y(n1219) );
NAND2X2TS U889 ( .A(n1089), .B(sign_inv_out[25]), .Y(n1229) );
NAND2X2TS U890 ( .A(n1089), .B(sign_inv_out[15]), .Y(n1257) );
NAND2X2TS U891 ( .A(n1089), .B(sign_inv_out[29]), .Y(n1135) );
NAND2X2TS U892 ( .A(n1034), .B(d_ff_Yn[18]), .Y(n1155) );
INVX2TS U893 ( .A(n2036), .Y(n809) );
NAND2X1TS U894 ( .A(n1036), .B(d_ff_Yn[6]), .Y(n1220) );
BUFX4TS U895 ( .A(n1094), .Y(n1593) );
AOI22X1TS U896 ( .A0(d_ff3_LUT_out[0]), .A1(n1582), .B0(n830), .B1(
d_ff3_sh_y_out[0]), .Y(n1425) );
AOI22X1TS U897 ( .A0(d_ff3_LUT_out[19]), .A1(n1591), .B0(n830), .B1(
d_ff3_sh_y_out[19]), .Y(n1567) );
AO22X2TS U898 ( .A0(d_ff3_LUT_out[20]), .A1(n1680), .B0(n1589), .B1(
d_ff3_sh_y_out[20]), .Y(n836) );
AOI22X1TS U899 ( .A0(n512), .A1(n808), .B0(n1690), .B1(d_ff3_sh_y_out[12]),
.Y(n1563) );
NOR2BX1TS U900 ( .AN(d_ff1_Z[23]), .B(n1077), .Y(n1071) );
NOR2BX1TS U901 ( .AN(d_ff1_Z[22]), .B(n1077), .Y(n1070) );
BUFX12TS U902 ( .A(n1210), .Y(n1089) );
INVX6TS U903 ( .A(net13805), .Y(n925) );
CLKBUFX3TS U904 ( .A(net13968), .Y(n919) );
INVX4TS U905 ( .A(n1725), .Y(n1401) );
BUFX16TS U906 ( .A(n1121), .Y(n1034) );
NOR2X1TS U907 ( .A(n1492), .B(n1130), .Y(n1132) );
INVX12TS U908 ( .A(n1708), .Y(n976) );
INVX2TS U909 ( .A(n1721), .Y(n1301) );
NOR2X4TS U910 ( .A(n2030), .B(net15395), .Y(n1718) );
INVX3TS U911 ( .A(n875), .Y(n1551) );
CLKMX2X4TS U912 ( .A(n855), .B(n902), .S0(n905), .Y(n1550) );
CLKINVX6TS U913 ( .A(n893), .Y(n1558) );
BUFX12TS U914 ( .A(n1087), .Y(n993) );
INVX2TS U915 ( .A(n977), .Y(n2036) );
NAND2X1TS U916 ( .A(net14149), .B(n909), .Y(n1336) );
BUFX12TS U917 ( .A(net14753), .Y(net14689) );
NAND2X2TS U918 ( .A(n1505), .B(n1403), .Y(n1399) );
NAND2X2TS U919 ( .A(n1040), .B(net5805), .Y(n1039) );
NOR2BX1TS U920 ( .AN(d_ff1_Z[26]), .B(n1077), .Y(n1076) );
MXI2X2TS U921 ( .A(n1970), .B(n1969), .S0(n812), .Y(n897) );
INVX12TS U922 ( .A(net13666), .Y(net14325) );
INVX6TS U923 ( .A(n1094), .Y(n1679) );
NAND2X1TS U924 ( .A(n2020), .B(n2019), .Y(net13674) );
NAND3X1TS U925 ( .A(n852), .B(n1914), .C(n1913), .Y(n1596) );
NAND3X1TS U926 ( .A(n1943), .B(n1942), .C(n1941), .Y(n1597) );
NAND3X1TS U927 ( .A(n1961), .B(n1960), .C(n1959), .Y(n1595) );
BUFX16TS U928 ( .A(n831), .Y(n807) );
CLKBUFX2TS U929 ( .A(n1091), .Y(n908) );
NOR2X1TS U930 ( .A(net14444), .B(net13816), .Y(net14857) );
NAND2X2TS U931 ( .A(net13960), .B(net15397), .Y(n1283) );
INVX4TS U932 ( .A(n1365), .Y(n1077) );
INVX12TS U933 ( .A(n1081), .Y(n1087) );
BUFX16TS U934 ( .A(n1052), .Y(n1025) );
BUFX16TS U935 ( .A(n906), .Y(n905) );
INVX12TS U936 ( .A(net13951), .Y(net13805) );
INVX12TS U937 ( .A(net13666), .Y(net14072) );
NAND2X2TS U938 ( .A(n947), .B(net13670), .Y(n964) );
INVX8TS U939 ( .A(net14457), .Y(net15017) );
NOR3X4TS U940 ( .A(n946), .B(n837), .C(n929), .Y(ack_add_subt) );
NAND2X2TS U941 ( .A(n1411), .B(n923), .Y(n1413) );
NAND2X2TS U942 ( .A(n916), .B(net13673), .Y(n1420) );
NAND2X2TS U943 ( .A(net13667), .B(d_ff3_LUT_out[0]), .Y(n1040) );
NAND2X4TS U944 ( .A(net15166), .B(n1048), .Y(n1515) );
BUFX16TS U945 ( .A(n1094), .Y(n1584) );
NAND2X1TS U946 ( .A(net6633), .B(n2031), .Y(n1179) );
INVX2TS U947 ( .A(net14848), .Y(net15166) );
INVX2TS U948 ( .A(net15155), .Y(net15156) );
INVX12TS U949 ( .A(net13673), .Y(n927) );
NAND2X4TS U950 ( .A(n1298), .B(n1297), .Y(n1299) );
AND2X4TS U951 ( .A(n934), .B(net13654), .Y(n916) );
BUFX3TS U952 ( .A(net15305), .Y(n822) );
INVX8TS U953 ( .A(net15160), .Y(net13948) );
INVX4TS U954 ( .A(n817), .Y(n932) );
OR2X4TS U955 ( .A(d_ff2_X[27]), .B(d_ff2_X[28]), .Y(n1275) );
BUFX12TS U956 ( .A(net14457), .Y(net13951) );
NAND2X6TS U957 ( .A(n1715), .B(n1180), .Y(n1298) );
NAND2X4TS U958 ( .A(n1823), .B(net13670), .Y(n1709) );
INVX4TS U959 ( .A(n945), .Y(n909) );
NOR2X6TS U960 ( .A(n837), .B(n1330), .Y(n828) );
NAND2X6TS U961 ( .A(n817), .B(n825), .Y(net13653) );
INVX4TS U962 ( .A(n1297), .Y(n1182) );
BUFX8TS U963 ( .A(net15394), .Y(net13670) );
NAND2X4TS U964 ( .A(net15305), .B(net15397), .Y(net15671) );
INVX12TS U965 ( .A(net13943), .Y(n817) );
INVX12TS U966 ( .A(net13943), .Y(net15305) );
INVX12TS U967 ( .A(n934), .Y(net13943) );
NAND3X6TS U968 ( .A(n1214), .B(n1215), .C(n1216), .Y(n572) );
NAND2X4TS U969 ( .A(n994), .B(n1557), .Y(n1215) );
NAND2BX4TS U970 ( .AN(n1043), .B(n1243), .Y(n586) );
BUFX20TS U971 ( .A(n1584), .Y(n1578) );
BUFX20TS U972 ( .A(n1087), .Y(n1086) );
BUFX20TS U973 ( .A(n1052), .Y(n1708) );
MXI2X2TS U974 ( .A(n1776), .B(n1893), .S0(n1700), .Y(n555) );
MXI2X2TS U975 ( .A(n1777), .B(n1894), .S0(n1700), .Y(n553) );
BUFX20TS U976 ( .A(n1700), .Y(n1702) );
BUFX20TS U977 ( .A(n1700), .Y(n1009) );
BUFX20TS U978 ( .A(n1700), .Y(n1008) );
NAND2X2TS U979 ( .A(n1436), .B(n1435), .Y(add_subt_dataB[31]) );
OAI2BB1X4TS U980 ( .A0N(d_ff2_Y[12]), .A1N(n1032), .B0(n1476), .Y(n439) );
OAI2BB1X4TS U981 ( .A0N(d_ff2_Y[11]), .A1N(n1032), .B0(n1445), .Y(n441) );
OAI2BB1X4TS U982 ( .A0N(d_ff2_Y[13]), .A1N(n1032), .B0(n1307), .Y(n437) );
OAI2BB1X4TS U983 ( .A0N(d_ff2_Y[31]), .A1N(n1032), .B0(n1449), .Y(n401) );
OAI2BB1X4TS U984 ( .A0N(d_ff2_X[21]), .A1N(n1032), .B0(n1444), .Y(n357) );
OAI2BB1X4TS U985 ( .A0N(d_ff2_Y[21]), .A1N(n1032), .B0(n1446), .Y(n421) );
OAI2BB1X4TS U986 ( .A0N(d_ff2_Y[20]), .A1N(n1032), .B0(n1448), .Y(n423) );
OAI2BB1X4TS U987 ( .A0N(d_ff2_X[9]), .A1N(n1032), .B0(n1470), .Y(n381) );
OAI2BB1X4TS U988 ( .A0N(d_ff2_X[23]), .A1N(n1032), .B0(n1707), .Y(n353) );
NAND2X2TS U989 ( .A(n1032), .B(d_ff2_Y[14]), .Y(n1026) );
NAND2X2TS U990 ( .A(n1122), .B(sign_inv_out[23]), .Y(n1234) );
NAND2X4TS U991 ( .A(n1413), .B(d_ff2_Y[25]), .Y(n1412) );
XOR2X4TS U992 ( .A(n961), .B(n962), .Y(n1332) );
MX2X4TS U993 ( .A(n1329), .B(net14160), .S0(n937), .Y(n961) );
NAND2X4TS U994 ( .A(n1007), .B(n1537), .Y(n1353) );
NAND3X6TS U995 ( .A(n1357), .B(n1358), .C(n1356), .Y(n469) );
NAND2X4TS U996 ( .A(n1007), .B(n1535), .Y(n1356) );
NAND2X4TS U997 ( .A(n1007), .B(n1536), .Y(n1350) );
INVX16TS U998 ( .A(n1003), .Y(n975) );
NAND2X4TS U999 ( .A(n1089), .B(sign_inv_out[20]), .Y(n1138) );
NAND2X4TS U1000 ( .A(n1089), .B(sign_inv_out[22]), .Y(n1200) );
NAND2X4TS U1001 ( .A(n1089), .B(sign_inv_out[11]), .Y(n1268) );
NAND2X4TS U1002 ( .A(n1089), .B(sign_inv_out[8]), .Y(n1216) );
NAND2X4TS U1003 ( .A(n1089), .B(sign_inv_out[14]), .Y(n1259) );
NAND2X4TS U1004 ( .A(n1089), .B(sign_inv_out[26]), .Y(n1272) );
NAND3X4TS U1005 ( .A(n1111), .B(n1110), .C(n1112), .Y(n491) );
NAND3X4TS U1006 ( .A(n1117), .B(n1116), .C(n1118), .Y(n488) );
NAND3X4TS U1007 ( .A(n1373), .B(n1372), .C(n1374), .Y(n487) );
NOR2X4TS U1008 ( .A(net14080), .B(n1704), .Y(n727) );
NAND2X4TS U1009 ( .A(n1047), .B(n1557), .Y(n1315) );
NOR2X4TS U1010 ( .A(net14146), .B(n1337), .Y(n910) );
NAND2X4TS U1011 ( .A(n1336), .B(n2032), .Y(n1337) );
NAND3X4TS U1012 ( .A(n1321), .B(n1320), .C(n1322), .Y(n492) );
MX2X4TS U1013 ( .A(data_in[29]), .B(d_ff1_Z[29]), .S0(n953), .Y(n691) );
NAND4X2TS U1014 ( .A(n933), .B(n1722), .C(n1393), .D(n1793), .Y(n2129) );
OAI21X2TS U1015 ( .A0(n1526), .A1(d_ff2_X[29]), .B0(n1722), .Y(n1482) );
AOI2BB1X2TS U1016 ( .A0N(n1722), .A1N(d_ff2_X[30]), .B0(n1531), .Y(n2134) );
AND2X4TS U1017 ( .A(n1722), .B(n1277), .Y(n1281) );
NAND3X4TS U1018 ( .A(n1722), .B(d_ff2_X[30]), .C(n1793), .Y(n1418) );
OAI21X2TS U1019 ( .A0(n1025), .A1(n1866), .B0(n1104), .Y(n415) );
INVX6TS U1020 ( .A(net15128), .Y(net13817) );
MXI2X4TS U1021 ( .A(n1755), .B(n1857), .S0(net14972), .Y(n438) );
BUFX20TS U1022 ( .A(net14753), .Y(net14972) );
MXI2X2TS U1023 ( .A(n1796), .B(n2073), .S0(net14688), .Y(n386) );
MXI2X4TS U1024 ( .A(n1827), .B(n2080), .S0(net14971), .Y(n380) );
MXI2X2TS U1025 ( .A(n1828), .B(n2084), .S0(net14689), .Y(n376) );
BUFX20TS U1026 ( .A(net14753), .Y(net14971) );
MXI2X2TS U1027 ( .A(n1736), .B(n2088), .S0(net15017), .Y(n370) );
MXI2X4TS U1028 ( .A(n1763), .B(n2091), .S0(net15017), .Y(n368) );
MXI2X2TS U1029 ( .A(n1801), .B(n2092), .S0(net14688), .Y(n364) );
BUFX20TS U1030 ( .A(net14753), .Y(net14688) );
MXI2X2TS U1031 ( .A(n1802), .B(n2097), .S0(net14972), .Y(n360) );
MXI2X4TS U1032 ( .A(n846), .B(n1930), .S0(n851), .Y(n1534) );
MX2X6TS U1033 ( .A(n891), .B(n892), .S0(n890), .Y(n1557) );
BUFX20TS U1034 ( .A(n1004), .Y(n1044) );
INVX16TS U1035 ( .A(n1002), .Y(n1004) );
CLKINVX6TS U1036 ( .A(n1299), .Y(n957) );
BUFX16TS U1037 ( .A(n889), .Y(n888) );
NAND2X8TS U1038 ( .A(net14072), .B(n1485), .Y(n1523) );
BUFX20TS U1039 ( .A(n896), .Y(n890) );
NAND2X4TS U1040 ( .A(n1034), .B(n1543), .Y(n1236) );
NAND2X4TS U1041 ( .A(n1034), .B(d_ff_Yn[8]), .Y(n1214) );
NAND2X4TS U1042 ( .A(n1034), .B(d_ff_Yn[14]), .Y(n1261) );
NOR2X6TS U1043 ( .A(n1868), .B(net15397), .Y(n1276) );
NAND2X2TS U1044 ( .A(n1036), .B(n1547), .Y(n1213) );
INVX16TS U1045 ( .A(n1035), .Y(n1121) );
MX2X4TS U1046 ( .A(data_in[2]), .B(d_ff1_Z[2]), .S0(n1083), .Y(n718) );
MX2X4TS U1047 ( .A(data_in[0]), .B(d_ff1_Z[0]), .S0(n1083), .Y(n720) );
MX2X4TS U1048 ( .A(data_in[3]), .B(d_ff1_Z[3]), .S0(n1083), .Y(n717) );
BUFX8TS U1049 ( .A(n1083), .Y(n953) );
NAND2X2TS U1050 ( .A(n1006), .B(n1556), .Y(n1258) );
NAND2X4TS U1051 ( .A(n980), .B(d_ff_Zn[5]), .Y(n1112) );
NAND2X4TS U1052 ( .A(n980), .B(d_ff_Zn[8]), .Y(n1118) );
NAND2X4TS U1053 ( .A(n980), .B(d_ff_Zn[9]), .Y(n1374) );
NAND2X4TS U1054 ( .A(n980), .B(d_ff_Zn[4]), .Y(n1322) );
NAND2X4TS U1055 ( .A(n980), .B(d_ff_Zn[2]), .Y(n1319) );
BUFX20TS U1056 ( .A(n1079), .Y(n1047) );
BUFX20TS U1057 ( .A(n1079), .Y(n1078) );
NAND3X2TS U1058 ( .A(n1529), .B(d_ff2_Y[28]), .C(n1528), .Y(n2122) );
NAND3X2TS U1059 ( .A(n1529), .B(d_ff2_Y[27]), .C(n1528), .Y(n2118) );
NAND2X4TS U1060 ( .A(n1498), .B(n1551), .Y(n1474) );
BUFX20TS U1061 ( .A(n1079), .Y(n1007) );
BUFX20TS U1062 ( .A(n1079), .Y(n980) );
NAND3X8TS U1063 ( .A(net13960), .B(net15395), .C(net13654), .Y(net15160) );
NAND2X4TS U1064 ( .A(net14838), .B(n1015), .Y(n1421) );
NOR2X8TS U1065 ( .A(net14848), .B(n964), .Y(net14838) );
BUFX20TS U1066 ( .A(n1053), .Y(n1050) );
NAND2XLTS U1067 ( .A(n1018), .B(d_ff_Zn[13]), .Y(n1340) );
BUFX20TS U1068 ( .A(n1005), .Y(n1021) );
BUFX20TS U1069 ( .A(n1079), .Y(n1046) );
BUFX20TS U1070 ( .A(n1422), .Y(n1508) );
INVX16TS U1071 ( .A(n2171), .Y(n1422) );
NAND2X8TS U1072 ( .A(n1183), .B(n1295), .Y(n1723) );
INVX16TS U1073 ( .A(n1002), .Y(n1003) );
INVX16TS U1074 ( .A(n1052), .Y(n1002) );
NAND2X8TS U1075 ( .A(net13948), .B(n932), .Y(net13933) );
NAND2X4TS U1076 ( .A(n976), .B(d_ff2_Z[2]), .Y(n1317) );
NAND3X6TS U1077 ( .A(n1368), .B(n1367), .C(n1366), .Y(n470) );
NOR2X2TS U1078 ( .A(net6761), .B(net15156), .Y(n1329) );
MXI2X4TS U1079 ( .A(n1720), .B(n1719), .S0(net13662), .Y(n2107) );
AND2X8TS U1080 ( .A(net14332), .B(net14333), .Y(net14330) );
MXI2X4TS U1081 ( .A(n1968), .B(n1967), .S0(n896), .Y(n1461) );
MXI2X4TS U1082 ( .A(n1978), .B(n1977), .S0(n896), .Y(n1442) );
MXI2X4TS U1083 ( .A(n1972), .B(n1971), .S0(n896), .Y(n1456) );
MXI2X4TS U1084 ( .A(n1958), .B(n1957), .S0(n896), .Y(n1561) );
NAND3X6TS U1085 ( .A(n1199), .B(n1198), .C(n1197), .Y(n540) );
NAND2X4TS U1086 ( .A(n1515), .B(n908), .Y(n1516) );
AOI21X4TS U1087 ( .A0(net14848), .A1(n1330), .B0(n1492), .Y(n1045) );
BUFX20TS U1088 ( .A(n1210), .Y(n1122) );
NOR2BX4TS U1089 ( .AN(n965), .B(net15081), .Y(n1096) );
AND2X6TS U1090 ( .A(net13816), .B(n1330), .Y(n1334) );
BUFX20TS U1091 ( .A(n1121), .Y(n1036) );
INVX4TS U1092 ( .A(n1455), .Y(n2074) );
INVX6TS U1093 ( .A(n1465), .Y(n2096) );
NAND2X6TS U1094 ( .A(net14374), .B(n1096), .Y(net14383) );
NOR2X8TS U1095 ( .A(n1182), .B(n1181), .Y(n1293) );
NOR2X4TS U1096 ( .A(net14445), .B(n1101), .Y(n724) );
MXI2X4TS U1097 ( .A(n2138), .B(n1809), .S0(n922), .Y(n683) );
MXI2X4TS U1098 ( .A(net5617), .B(n1811), .S0(n922), .Y(n681) );
MXI2X4TS U1099 ( .A(n2149), .B(n1818), .S0(n922), .Y(n669) );
MXI2X4TS U1100 ( .A(net5513), .B(net7541), .S0(n922), .Y(n668) );
BUFX6TS U1101 ( .A(d_ff2_X[27]), .Y(n806) );
MXI2X4TS U1102 ( .A(n1132), .B(n1131), .S0(net13896), .Y(n1133) );
NAND3BX4TS U1103 ( .AN(n1133), .B(net14851), .C(net14393), .Y(
cordic_FSM_state_next_1_) );
BUFX8TS U1104 ( .A(n1689), .Y(n808) );
NAND2X4TS U1105 ( .A(net14330), .B(net14847), .Y(n966) );
MXI2X2TS U1106 ( .A(net13887), .B(net15425), .S0(n938), .Y(n608) );
MXI2X2TS U1107 ( .A(n1519), .B(n944), .S0(n938), .Y(n610) );
MXI2X2TS U1108 ( .A(n2147), .B(n942), .S0(n938), .Y(n607) );
BUFX20TS U1109 ( .A(n831), .Y(n1680) );
BUFX20TS U1110 ( .A(n954), .Y(n830) );
BUFX6TS U1111 ( .A(n954), .Y(n1690) );
BUFX6TS U1112 ( .A(n954), .Y(n1589) );
BUFX20TS U1113 ( .A(n1689), .Y(n831) );
BUFX20TS U1114 ( .A(n906), .Y(n812) );
MXI2X4TS U1115 ( .A(n863), .B(n1979), .S0(n812), .Y(n1458) );
AND2X2TS U1116 ( .A(net15219), .B(n1049), .Y(n1048) );
NOR2BX1TS U1117 ( .AN(d_ff1_Z[21]), .B(n1077), .Y(n1073) );
NOR2X1TS U1118 ( .A(net14149), .B(net14152), .Y(net14146) );
NAND2X2TS U1119 ( .A(n1086), .B(n597), .Y(n1235) );
NAND2X1TS U1120 ( .A(n1271), .B(sign_inv_out[21]), .Y(n1240) );
NAND2X2TS U1121 ( .A(n1086), .B(n1553), .Y(n1226) );
AOI22X1TS U1122 ( .A0(n808), .A1(d_ff3_LUT_out[18]), .B0(n1690), .B1(
d_ff3_sh_y_out[18]), .Y(n1571) );
NAND2X1TS U1123 ( .A(n1688), .B(d_ff3_sh_x_out[31]), .Y(n1436) );
NAND2X1TS U1124 ( .A(n1695), .B(d_ff2_Z[11]), .Y(n1665) );
AND2X2TS U1125 ( .A(n1658), .B(d_ff2_Y[14]), .Y(n1024) );
NAND2X1TS U1126 ( .A(n1694), .B(d_ff2_Y[22]), .Y(n1648) );
INVX2TS U1127 ( .A(result_add_subt[26]), .Y(n2159) );
OAI21X2TS U1128 ( .A0(n1415), .A1(n1303), .B0(n1302), .Y(n2110) );
CLKMX2X4TS U1129 ( .A(n2028), .B(n2027), .S0(n812), .Y(n816) );
NAND2X8TS U1130 ( .A(net14847), .B(net14330), .Y(n938) );
BUFX12TS U1131 ( .A(net15444), .Y(n821) );
NOR2X2TS U1132 ( .A(n1417), .B(n1508), .Y(n2168) );
NAND3X1TS U1133 ( .A(n1155), .B(n1154), .C(n1153), .Y(n552) );
MXI2X2TS U1134 ( .A(n1748), .B(n1849), .S0(net14851), .Y(n454) );
MXI2X2TS U1135 ( .A(n1762), .B(n1865), .S0(net14851), .Y(n400) );
BUFX12TS U1136 ( .A(n1018), .Y(n1706) );
NOR2X4TS U1137 ( .A(net13667), .B(n1283), .Y(n1141) );
BUFX12TS U1138 ( .A(n831), .Y(n1662) );
MX2X2TS U1139 ( .A(n863), .B(n1979), .S0(n812), .Y(n898) );
CLKMX2X4TS U1140 ( .A(n1993), .B(n1992), .S0(n905), .Y(n903) );
BUFX6TS U1141 ( .A(n954), .Y(n1696) );
XNOR2X2TS U1142 ( .A(d_ff2_X[26]), .B(n823), .Y(n1395) );
MX2X2TS U1143 ( .A(n1970), .B(n1969), .S0(n812), .Y(n960) );
CLKMX2X4TS U1144 ( .A(n865), .B(n2011), .S0(n905), .Y(n899) );
INVX8TS U1145 ( .A(result_add_subt[6]), .Y(n2142) );
INVX8TS U1146 ( .A(result_add_subt[14]), .Y(n2148) );
INVX8TS U1147 ( .A(result_add_subt[21]), .Y(n2154) );
NAND2X2TS U1148 ( .A(n1046), .B(net15101), .Y(n1156) );
NAND2X2TS U1149 ( .A(n1046), .B(d_ff_Yn[6]), .Y(n1472) );
MXI2X2TS U1150 ( .A(n1744), .B(n1846), .S0(net13662), .Y(n462) );
MXI2X2TS U1151 ( .A(n1758), .B(n1860), .S0(net13662), .Y(n424) );
MXI2X2TS U1152 ( .A(n1752), .B(n1854), .S0(net13662), .Y(n444) );
NOR2X4TS U1153 ( .A(n1524), .B(n1141), .Y(n2081) );
MXI2X2TS U1154 ( .A(n1759), .B(n1861), .S0(net13662), .Y(n422) );
MXI2X2TS U1155 ( .A(n1332), .B(n1875), .S0(n1702), .Y(n525) );
NOR2BX2TS U1156 ( .AN(d_ff1_Z[15]), .B(n818), .Y(n1068) );
NOR2BX2TS U1157 ( .AN(d_ff1_Z[14]), .B(n818), .Y(n1066) );
NOR2BX2TS U1158 ( .AN(d_ff1_Z[13]), .B(n818), .Y(n1065) );
NAND2X4TS U1159 ( .A(n916), .B(n927), .Y(net13950) );
INVX6TS U1160 ( .A(n1277), .Y(n1526) );
BUFX12TS U1161 ( .A(n831), .Y(n1695) );
BUFX12TS U1162 ( .A(n830), .Y(n955) );
BUFX8TS U1163 ( .A(n1689), .Y(n1591) );
BUFX8TS U1164 ( .A(n1689), .Y(n1582) );
AND3X4TS U1165 ( .A(n1100), .B(n1099), .C(n1098), .Y(n1870) );
OAI21X1TS U1166 ( .A0(n1005), .A1(n1873), .B0(n1105), .Y(n412) );
OAI2BB1X2TS U1167 ( .A0N(d_ff3_LUT_out[17]), .A1N(net13662), .B0(n1523), .Y(
n507) );
MXI2X2TS U1168 ( .A(n1745), .B(n1847), .S0(net13657), .Y(n460) );
MXI2X2TS U1169 ( .A(n1794), .B(n1011), .S0(net13657), .Y(n392) );
NAND2X1TS U1170 ( .A(net14971), .B(n1595), .Y(n2114) );
NAND2X1TS U1171 ( .A(net14971), .B(n1597), .Y(n2087) );
INVX2TS U1172 ( .A(n1403), .Y(n1406) );
BUFX8TS U1173 ( .A(n1050), .Y(n1051) );
BUFX8TS U1174 ( .A(n1724), .Y(n956) );
BUFX12TS U1175 ( .A(n830), .Y(n1663) );
BUFX12TS U1176 ( .A(n830), .Y(n1681) );
INVX4TS U1177 ( .A(net15395), .Y(n825) );
INVX6TS U1178 ( .A(net12499), .Y(n937) );
NAND3X2TS U1179 ( .A(n1129), .B(net14367), .C(n1128), .Y(n732) );
OAI2BB1X2TS U1180 ( .A0N(d_ff2_X[15]), .A1N(n976), .B0(n1305), .Y(n369) );
OAI21X1TS U1181 ( .A0(n1005), .A1(n2160), .B0(n1103), .Y(n414) );
BUFX12TS U1182 ( .A(net13667), .Y(net14851) );
NAND2X2TS U1183 ( .A(n1299), .B(d_ff2_X[25]), .Y(n1300) );
BUFX12TS U1184 ( .A(n1210), .Y(n1271) );
INVX6TS U1185 ( .A(n1052), .Y(n1032) );
NOR2BX2TS U1186 ( .AN(d_ff1_Z[11]), .B(n819), .Y(n1064) );
NOR2BX2TS U1187 ( .AN(d_ff1_Z[10]), .B(n819), .Y(n1063) );
NAND2X1TS U1188 ( .A(n808), .B(n1714), .Y(n1692) );
NAND2X4TS U1189 ( .A(n1804), .B(net13670), .Y(n1715) );
NAND2X2TS U1190 ( .A(n1038), .B(n2081), .Y(n524) );
NAND2X2TS U1191 ( .A(n993), .B(n1548), .Y(n1211) );
NAND2X2TS U1192 ( .A(n993), .B(net15424), .Y(n1265) );
NAND2X2TS U1193 ( .A(n994), .B(n941), .Y(n1262) );
MXI2X2TS U1194 ( .A(n1503), .B(n2108), .S0(net13657), .Y(n344) );
MXI2X2TS U1195 ( .A(n1507), .B(n1506), .S0(net13657), .Y(n2119) );
BUFX8TS U1196 ( .A(n1018), .Y(n1478) );
NOR2X2TS U1197 ( .A(n1283), .B(net14213), .Y(n1284) );
OAI21X2TS U1198 ( .A0(net13933), .A1(n1494), .B0(n1493), .Y(n826) );
BUFX12TS U1199 ( .A(n1082), .Y(n1083) );
NOR2BX2TS U1200 ( .AN(d_ff1_Z[18]), .B(n819), .Y(n1056) );
NOR2BX2TS U1201 ( .AN(d_ff1_Z[17]), .B(n819), .Y(n1057) );
NOR2BX2TS U1202 ( .AN(d_ff1_Z[19]), .B(n819), .Y(n1059) );
NOR2BX2TS U1203 ( .AN(d_ff1_Z[16]), .B(n819), .Y(n1058) );
INVX6TS U1204 ( .A(n1041), .Y(n818) );
CLKINVX6TS U1205 ( .A(n1528), .Y(n1505) );
MXI2X2TS U1206 ( .A(n853), .B(n2000), .S0(n905), .Y(n900) );
AND2X8TS U1207 ( .A(net13817), .B(cordic_FSM_state_reg_0_), .Y(net14374) );
NOR2X6TS U1208 ( .A(net13654), .B(d_ff2_X[26]), .Y(n1277) );
INVX6TS U1209 ( .A(net15394), .Y(net15395) );
NAND2X2TS U1210 ( .A(n1378), .B(n1560), .Y(n1310) );
OAI2BB1X2TS U1211 ( .A0N(d_ff3_LUT_out[16]), .A1N(net14972), .B0(n1486), .Y(
n508) );
NAND2X2TS U1212 ( .A(n1478), .B(d_ff_Zn[20]), .Y(n1346) );
NAND2X2TS U1213 ( .A(n1478), .B(d_ff_Yn[1]), .Y(n1469) );
NAND2X2TS U1214 ( .A(n1378), .B(d_ff_Zn[0]), .Y(n1328) );
BUFX12TS U1215 ( .A(n1018), .Y(n1498) );
NAND2X2TS U1216 ( .A(n1006), .B(d_ff_Yn[25]), .Y(n1033) );
NAND2X2TS U1217 ( .A(n994), .B(n900), .Y(n1230) );
NAND3X2TS U1218 ( .A(n1005), .B(n1365), .C(d_ff1_Z[6]), .Y(n1114) );
NAND2X2TS U1219 ( .A(n994), .B(n1457), .Y(n1260) );
NAND2X2TS U1220 ( .A(n994), .B(n897), .Y(n1136) );
NAND3X2TS U1221 ( .A(n1025), .B(n1365), .C(d_ff1_Z[28]), .Y(n1177) );
INVX12TS U1222 ( .A(n1002), .Y(n1005) );
INVX12TS U1223 ( .A(n1508), .Y(n2032) );
INVX16TS U1224 ( .A(n827), .Y(n1018) );
NOR2BX2TS U1225 ( .AN(d_ff1_Z[7]), .B(n818), .Y(n1055) );
NOR2BX2TS U1226 ( .AN(d_ff1_Z[5]), .B(n818), .Y(n1060) );
NOR2BX2TS U1227 ( .AN(d_ff1_Z[9]), .B(n819), .Y(n1062) );
NOR2BX2TS U1228 ( .AN(d_ff1_Z[20]), .B(n818), .Y(n1067) );
NOR2BX2TS U1229 ( .AN(d_ff1_Z[8]), .B(n818), .Y(n1054) );
NOR2BX2TS U1230 ( .AN(d_ff1_Z[12]), .B(n818), .Y(n1061) );
NOR2BX2TS U1231 ( .AN(d_ff1_Z[30]), .B(n818), .Y(n1069) );
INVX1TS U1232 ( .A(n1514), .Y(n1127) );
INVX4TS U1233 ( .A(d_ff2_Y[29]), .Y(n1500) );
OAI2BB1X2TS U1234 ( .A0N(d_ff3_LUT_out[20]), .A1N(net15017), .B0(n1523), .Y(
n504) );
OAI2BB1X2TS U1235 ( .A0N(d_ff3_LUT_out[15]), .A1N(net14972), .B0(n1523), .Y(
n509) );
OAI2BB1X2TS U1236 ( .A0N(d_ff3_LUT_out[3]), .A1N(net14753), .B0(n1486), .Y(
n521) );
NAND2X2TS U1237 ( .A(n1055), .B(n1003), .Y(n1120) );
NAND2X2TS U1238 ( .A(n1478), .B(n1553), .Y(n1309) );
BUFX12TS U1239 ( .A(n1018), .Y(n1378) );
NAND2X2TS U1240 ( .A(n993), .B(n1562), .Y(n1107) );
NAND2X1TS U1241 ( .A(n1079), .B(n1541), .Y(n1175) );
CLKMX2X2TS U1242 ( .A(data_in[4]), .B(d_ff1_Z[4]), .S0(n1001), .Y(n716) );
NAND2X1TS U1243 ( .A(n1050), .B(n467), .Y(n1173) );
NOR2BX2TS U1244 ( .AN(d_ff1_Z[27]), .B(n1077), .Y(n1072) );
MXI2X2TS U1245 ( .A(n2028), .B(n2027), .S0(n812), .Y(n1549) );
BUFX6TS U1246 ( .A(n1109), .Y(n1041) );
MXI2X2TS U1247 ( .A(n2028), .B(n2027), .S0(n812), .Y(n901) );
INVX6TS U1248 ( .A(result_add_subt[16]), .Y(net5513) );
INVX6TS U1249 ( .A(result_add_subt[1]), .Y(n2138) );
NAND2X2TS U1250 ( .A(n1706), .B(d_ff_Yn[21]), .Y(n1446) );
NAND2X2TS U1251 ( .A(n1378), .B(d_ff_Yn[31]), .Y(n1449) );
NAND2X2TS U1252 ( .A(n1047), .B(n1548), .Y(n1470) );
NAND2X2TS U1253 ( .A(n1706), .B(d_ff_Yn[20]), .Y(n1448) );
NAND2X2TS U1254 ( .A(n1047), .B(d_ff_Yn[10]), .Y(n1471) );
NAND2X2TS U1255 ( .A(n1706), .B(d_ff_Yn[11]), .Y(n1445) );
NOR2X2TS U1256 ( .A(n1508), .B(n826), .Y(n2170) );
OAI2BB1X2TS U1257 ( .A0N(d_ff3_LUT_out[13]), .A1N(net13667), .B0(n1487), .Y(
n511) );
NAND2X2TS U1258 ( .A(n1034), .B(n1560), .Y(n1225) );
NAND2X2TS U1259 ( .A(n1062), .B(n1005), .Y(n1373) );
NAND2X2TS U1260 ( .A(n1054), .B(n1005), .Y(n1117) );
NAND2X2TS U1261 ( .A(n1058), .B(n1005), .Y(n1165) );
NAND2X2TS U1262 ( .A(n1067), .B(n1005), .Y(n1345) );
NAND2X2TS U1263 ( .A(n1072), .B(n1005), .Y(n1357) );
MXI2X2TS U1264 ( .A(n1729), .B(n1789), .S0(net15017), .Y(n434) );
MXI2X2TS U1265 ( .A(n1730), .B(n1790), .S0(net15017), .Y(n432) );
NAND2X2TS U1266 ( .A(n1492), .B(n1335), .Y(net14149) );
OAI21X1TS U1267 ( .A0(n2108), .A1(n1593), .B0(n1572), .Y(add_subt_dataB[24])
);
OAI21X1TS U1268 ( .A0(n2101), .A1(n1593), .B0(n1566), .Y(add_subt_dataB[22])
);
NOR2BX2TS U1269 ( .AN(d_ff1_Z[24]), .B(n1077), .Y(n1075) );
NOR2BX2TS U1270 ( .AN(d_ff1_Z[25]), .B(n1077), .Y(n1074) );
INVX6TS U1271 ( .A(n1041), .Y(n819) );
OR2X6TS U1272 ( .A(net13960), .B(d_ff2_X[25]), .Y(n1295) );
NAND2X2TS U1273 ( .A(n1378), .B(n1545), .Y(n1306) );
NAND2X2TS U1274 ( .A(n1378), .B(n1562), .Y(n1450) );
NAND2X2TS U1275 ( .A(net14851), .B(n1596), .Y(n2070) );
NAND2X2TS U1276 ( .A(n1061), .B(n1004), .Y(n1370) );
NAND2X2TS U1277 ( .A(n1060), .B(n1004), .Y(n1111) );
NAND2X2TS U1278 ( .A(n1070), .B(n1004), .Y(n1351) );
NAND2X2TS U1279 ( .A(n1071), .B(n1004), .Y(n1354) );
BUFX20TS U1280 ( .A(n1018), .Y(n1079) );
INVX12TS U1281 ( .A(n1704), .Y(n998) );
NAND2X2TS U1282 ( .A(net14688), .B(n1594), .Y(n2111) );
MXI2X2TS U1283 ( .A(n1782), .B(n1900), .S0(n1008), .Y(n541) );
MXI2X2TS U1284 ( .A(n1780), .B(n1898), .S0(n1009), .Y(n545) );
MXI2X2TS U1285 ( .A(n1766), .B(n1879), .S0(n1008), .Y(n583) );
NOR2X4TS U1286 ( .A(net13670), .B(n822), .Y(net14213) );
MXI2X2TS U1287 ( .A(n1781), .B(n1899), .S0(n1009), .Y(n543) );
MXI2X2TS U1288 ( .A(n1735), .B(n1886), .S0(n1008), .Y(n569) );
MXI2X2TS U1289 ( .A(n1779), .B(n1897), .S0(n1008), .Y(n547) );
MXI2X2TS U1290 ( .A(n1734), .B(n1885), .S0(n1009), .Y(n571) );
MXI2X2TS U1291 ( .A(n1733), .B(n1884), .S0(n1009), .Y(n573) );
MXI2X2TS U1292 ( .A(n1732), .B(n1883), .S0(n1008), .Y(n575) );
MXI2X2TS U1293 ( .A(n1764), .B(n1877), .S0(n1008), .Y(n587) );
MXI2X2TS U1294 ( .A(n1765), .B(n1878), .S0(n1009), .Y(n585) );
MXI2X2TS U1295 ( .A(n1788), .B(n1906), .S0(n1009), .Y(n529) );
MXI2X2TS U1296 ( .A(n1785), .B(n1903), .S0(n1008), .Y(n535) );
MXI2X2TS U1297 ( .A(n1787), .B(n1905), .S0(n1008), .Y(n531) );
NAND2X4TS U1298 ( .A(n1724), .B(n1398), .Y(n1403) );
INVX12TS U1299 ( .A(n1584), .Y(n1688) );
NAND2X2TS U1300 ( .A(n1437), .B(n1987), .Y(n1438) );
INVX2TS U1301 ( .A(n832), .Y(n1459) );
MX2X2TS U1302 ( .A(n2015), .B(n2014), .S0(n812), .Y(n904) );
OAI2BB1X2TS U1303 ( .A0N(n866), .A1N(n1965), .B0(n1964), .Y(n1710) );
OAI2BB1X2TS U1304 ( .A0N(n866), .A1N(n1953), .B0(n1952), .Y(n1716) );
NAND3X2TS U1305 ( .A(n2007), .B(n2006), .C(n2005), .Y(n1594) );
NAND3X2TS U1306 ( .A(n914), .B(n913), .C(n912), .Y(n467) );
OAI2BB1X2TS U1307 ( .A0N(n866), .A1N(n1932), .B0(n1931), .Y(n1714) );
MXI2X4TS U1308 ( .A(n870), .B(n1945), .S0(n1944), .Y(n1562) );
NAND2X2TS U1309 ( .A(n1498), .B(d_ff_Yn[16]), .Y(n1475) );
NAND2X2TS U1310 ( .A(n1498), .B(d_ff_Yn[12]), .Y(n1476) );
NAND2X2TS U1311 ( .A(n1478), .B(n1556), .Y(n1308) );
NAND2X2TS U1312 ( .A(n1478), .B(d_ff_Zn[12]), .Y(n1371) );
MXI2X2TS U1313 ( .A(n1784), .B(n1902), .S0(n1702), .Y(n537) );
MXI2X2TS U1314 ( .A(n1783), .B(n1901), .S0(n1702), .Y(n539) );
MXI2X2TS U1315 ( .A(n1769), .B(n1882), .S0(n1702), .Y(n577) );
MXI2X2TS U1316 ( .A(n1768), .B(n1881), .S0(n1702), .Y(n579) );
MXI2X2TS U1317 ( .A(n1767), .B(n1880), .S0(n1702), .Y(n581) );
MXI2X2TS U1318 ( .A(n1786), .B(n1904), .S0(n1702), .Y(n533) );
INVX2TS U1319 ( .A(n1578), .Y(n834) );
INVX2TS U1320 ( .A(n882), .Y(n1537) );
CLKMX2X3TS U1321 ( .A(n854), .B(n1927), .S0(n888), .Y(n886) );
CLKMX2X3TS U1322 ( .A(n853), .B(n1922), .S0(n888), .Y(n884) );
CLKMX2X3TS U1323 ( .A(n847), .B(n1921), .S0(n888), .Y(n885) );
CLKMX2X3TS U1324 ( .A(n856), .B(n1920), .S0(n888), .Y(n887) );
CLKMX2X2TS U1325 ( .A(n868), .B(n2013), .S0(n880), .Y(n871) );
OAI21X2TS U1326 ( .A0(n1750), .A1(n1021), .B0(n1311), .Y(n449) );
OAI21X2TS U1327 ( .A0(n1749), .A1(n1021), .B0(n1472), .Y(n451) );
OAI21X2TS U1328 ( .A0(n1020), .A1(n1021), .B0(n1156), .Y(n457) );
NAND2X2TS U1329 ( .A(n1378), .B(d_ff_Yn[18]), .Y(n1477) );
MX2X2TS U1330 ( .A(data_in[21]), .B(d_ff1_Z[21]), .S0(n1705), .Y(n699) );
MX2X2TS U1331 ( .A(data_in[22]), .B(d_ff1_Z[22]), .S0(n1705), .Y(n698) );
MX2X2TS U1332 ( .A(data_in[23]), .B(d_ff1_Z[23]), .S0(n1705), .Y(n697) );
MX2X2TS U1333 ( .A(data_in[24]), .B(d_ff1_Z[24]), .S0(n1705), .Y(n696) );
MX2X2TS U1334 ( .A(data_in[25]), .B(d_ff1_Z[25]), .S0(n1705), .Y(n695) );
MX2X2TS U1335 ( .A(data_in[26]), .B(d_ff1_Z[26]), .S0(n1705), .Y(n694) );
MX2X2TS U1336 ( .A(data_in[30]), .B(d_ff1_Z[30]), .S0(n1705), .Y(n690) );
MX2X2TS U1337 ( .A(data_in[1]), .B(d_ff1_Z[1]), .S0(n1705), .Y(n719) );
MXI2X2TS U1338 ( .A(n950), .B(n1084), .S0(n1704), .Y(n692) );
INVX4TS U1339 ( .A(n877), .Y(n622) );
NAND2X6TS U1340 ( .A(n823), .B(n2160), .Y(n1528) );
INVX4TS U1341 ( .A(n943), .Y(n944) );
INVX2TS U1342 ( .A(data_in[28]), .Y(n1084) );
NAND3X2TS U1343 ( .A(n1364), .B(n1363), .C(n1362), .Y(n472) );
NAND2X2TS U1344 ( .A(n1023), .B(n1467), .Y(n463) );
NAND3X2TS U1345 ( .A(n1178), .B(n1177), .C(n1176), .Y(n468) );
NAND2X2TS U1346 ( .A(n1471), .B(n1027), .Y(n443) );
NAND2X2TS U1347 ( .A(n1314), .B(n1028), .Y(n445) );
NAND3X2TS U1348 ( .A(n1370), .B(n1371), .C(n1369), .Y(n484) );
NAND2X4TS U1349 ( .A(n1063), .B(n1044), .Y(n1376) );
NAND2X4TS U1350 ( .A(n1303), .B(n1301), .Y(n1302) );
NAND2X4TS U1351 ( .A(n1076), .B(n1013), .Y(n1367) );
INVX2TS U1352 ( .A(net13653), .Y(n824) );
INVX2TS U1353 ( .A(ack_add_subt), .Y(net14393) );
INVX4TS U1354 ( .A(n872), .Y(n1559) );
INVX4TS U1355 ( .A(n842), .Y(n1423) );
BUFX16TS U1356 ( .A(n1109), .Y(n1365) );
INVX4TS U1357 ( .A(n839), .Y(n1554) );
INVX12TS U1358 ( .A(net15397), .Y(net13654) );
INVX12TS U1359 ( .A(cordic_FSM_state_reg_0_), .Y(net14404) );
BUFX8TS U1360 ( .A(net15397), .Y(n823) );
INVX4TS U1361 ( .A(n1143), .Y(n1100) );
OAI2BB1X2TS U1362 ( .A0N(d_ff2_Y[22]), .A1N(n992), .B0(n1447), .Y(n419) );
NAND2X2TS U1363 ( .A(n1312), .B(n1030), .Y(n377) );
NAND3X2TS U1364 ( .A(n1340), .B(n1339), .C(n1338), .Y(n483) );
OAI2BB1X2TS U1365 ( .A0N(d_ff2_X[31]), .A1N(n1051), .B0(n1102), .Y(n337) );
OAI2BB1X2TS U1366 ( .A0N(d_ff2_Y[23]), .A1N(n1014), .B0(n1316), .Y(n417) );
NAND3X2TS U1367 ( .A(n1361), .B(n1360), .C(n1359), .Y(n471) );
OAI2BB1X2TS U1368 ( .A0N(d_ff2_Y[30]), .A1N(n1051), .B0(n1451), .Y(n410) );
NAND2X2TS U1369 ( .A(n1304), .B(n1031), .Y(n363) );
NAND2X2TS U1370 ( .A(n1479), .B(n1026), .Y(n435) );
NAND3X2TS U1371 ( .A(n1171), .B(n1170), .C(n1172), .Y(n465) );
NAND2X2TS U1372 ( .A(n1029), .B(n1315), .Y(n383) );
NOR2X4TS U1373 ( .A(n1143), .B(n1039), .Y(n1038) );
NAND3X2TS U1374 ( .A(n1229), .B(n1230), .C(n1033), .Y(n538) );
AOI2BB2X2TS U1375 ( .B0(n2123), .B1(n1706), .A0N(n1708), .A1N(d_ff2_X[28]),
.Y(n348) );
NAND3X2TS U1376 ( .A(n1044), .B(n1365), .C(d_ff1_Z[29]), .Y(n1174) );
NAND2X6TS U1377 ( .A(n1509), .B(n824), .Y(n952) );
NAND2X4TS U1378 ( .A(n993), .B(n1462), .Y(n1198) );
NAND2X2TS U1379 ( .A(n1294), .B(n1295), .Y(n933) );
CLKMX2X2TS U1380 ( .A(data_in[19]), .B(d_ff1_Z[19]), .S0(n1001), .Y(n701) );
OR2X4TS U1381 ( .A(n1003), .B(n948), .Y(n1017) );
BUFX16TS U1382 ( .A(n1087), .Y(n994) );
INVX8TS U1383 ( .A(net15216), .Y(net15797) );
BUFX16TS U1384 ( .A(n1087), .Y(n1085) );
OR2X2TS U1385 ( .A(n1744), .B(n1052), .Y(n1023) );
INVX2TS U1386 ( .A(n1420), .Y(n1015) );
NAND2X6TS U1387 ( .A(n1090), .B(n1492), .Y(n1035) );
NAND2X2TS U1388 ( .A(net13896), .B(n929), .Y(n1587) );
INVX8TS U1389 ( .A(n1365), .Y(n829) );
AND2X4TS U1390 ( .A(n1500), .B(d_ff2_Y[30]), .Y(n1398) );
NOR2X6TS U1391 ( .A(n1330), .B(n837), .Y(n907) );
INVX16TS U1392 ( .A(n1088), .Y(n1513) );
INVX6TS U1393 ( .A(n918), .Y(n1462) );
INVX2TS U1394 ( .A(n597), .Y(n1805) );
OAI2BB1X2TS U1395 ( .A0N(n1963), .A1N(n1962), .B0(n852), .Y(n512) );
MXI2X4TS U1396 ( .A(n860), .B(n1997), .S0(n1996), .Y(n1560) );
INVX2TS U1397 ( .A(d_ff2_Y[3]), .Y(n1020) );
INVX2TS U1398 ( .A(d_ff2_Y[1]), .Y(n1022) );
INVX4TS U1399 ( .A(net15424), .Y(net15425) );
NAND2X4TS U1400 ( .A(net15304), .B(net15397), .Y(net13968) );
BUFX6TS U1401 ( .A(n1509), .Y(n820) );
INVX12TS U1402 ( .A(net14841), .Y(net15219) );
NAND2X8TS U1403 ( .A(net15798), .B(net15797), .Y(n922) );
INVX16TS U1404 ( .A(net13890), .Y(net14189) );
NAND2X8TS U1405 ( .A(net15798), .B(net15797), .Y(net13890) );
INVX16TS U1406 ( .A(net14383), .Y(net14457) );
OR2X8TS U1407 ( .A(net15081), .B(cordic_FSM_state_reg_0_), .Y(n1088) );
NOR2X8TS U1408 ( .A(net14448), .B(n935), .Y(net14755) );
NAND2X8TS U1409 ( .A(net15304), .B(net15394), .Y(net14448) );
INVX16TS U1410 ( .A(net15445), .Y(net15446) );
CLKINVX12TS U1411 ( .A(net15219), .Y(net15483) );
MXI2X2TS U1412 ( .A(n2139), .B(n1810), .S0(net13890), .Y(n682) );
OAI21X4TS U1413 ( .A0(net14072), .A1(d_ff3_sh_x_out[27]), .B0(n1185), .Y(
n1187) );
NAND2X8TS U1414 ( .A(ack_add_subt), .B(net15434), .Y(n1383) );
NOR2X2TS U1415 ( .A(cont_var_out[1]), .B(net15216), .Y(net14447) );
INVX16TS U1416 ( .A(net15441), .Y(net15442) );
INVX6TS U1417 ( .A(n963), .Y(n1109) );
NAND3X8TS U1418 ( .A(n829), .B(n1513), .C(n828), .Y(n827) );
NOR2X8TS U1419 ( .A(sel_mux_2_reg[0]), .B(sel_mux_2_reg[1]), .Y(n954) );
NOR2X8TS U1420 ( .A(n1871), .B(sel_mux_2_reg[0]), .Y(n1689) );
BUFX4TS U1421 ( .A(net14331), .Y(net14847) );
MX2X4TS U1422 ( .A(n1925), .B(n1926), .S0(n833), .Y(n832) );
AO21X4TS U1423 ( .A0(n835), .A1(n834), .B0(n836), .Y(add_subt_dataB[20]) );
BUFX20TS U1424 ( .A(net15128), .Y(n837) );
MXI2X2TS U1425 ( .A(n1146), .B(n1514), .S0(n929), .Y(n1149) );
MXI2X4TS U1426 ( .A(n840), .B(n841), .S0(n845), .Y(n839) );
MXI2X4TS U1427 ( .A(n843), .B(n844), .S0(n845), .Y(n842) );
MXI2X4TS U1428 ( .A(n846), .B(n2012), .S0(n881), .Y(n1203) );
MXI2X2TS U1429 ( .A(n847), .B(n1921), .S0(n888), .Y(n1539) );
OAI2BB1X2TS U1430 ( .A0N(n1990), .A1N(n848), .B0(n1434), .Y(n338) );
OAI2BB1X2TS U1431 ( .A0N(n1991), .A1N(n848), .B0(n1438), .Y(n339) );
MXI2X2TS U1432 ( .A(n1918), .B(n1917), .S0(n850), .Y(n1541) );
MXI2X4TS U1433 ( .A(n1924), .B(n1923), .S0(n851), .Y(n1538) );
MXI2X2TS U1434 ( .A(n854), .B(n1927), .S0(n888), .Y(n1533) );
MXI2X2TS U1435 ( .A(n856), .B(n1920), .S0(n888), .Y(n1536) );
MXI2X4TS U1436 ( .A(n859), .B(n1994), .S0(n890), .Y(n1553) );
MXI2X4TS U1437 ( .A(n854), .B(n2004), .S0(n864), .Y(n1463) );
MXI2X2TS U1438 ( .A(n865), .B(n2011), .S0(n905), .Y(n1464) );
MXI2X2TS U1439 ( .A(n870), .B(n1919), .S0(n850), .Y(n1540) );
MXI2X4TS U1440 ( .A(n873), .B(n874), .S0(n880), .Y(n872) );
MXI2X4TS U1441 ( .A(n862), .B(n876), .S0(n880), .Y(n875) );
MXI2X4TS U1442 ( .A(n869), .B(n878), .S0(n880), .Y(n877) );
MXI2X4TS U1443 ( .A(n857), .B(n1966), .S0(n881), .Y(n1455) );
MXI2X4TS U1444 ( .A(n858), .B(n1973), .S0(n881), .Y(n1465) );
MXI2X4TS U1445 ( .A(n867), .B(n883), .S0(n888), .Y(n882) );
MXI2X4TS U1446 ( .A(n894), .B(n895), .S0(n890), .Y(n893) );
MXI2X4TS U1447 ( .A(n1934), .B(n1933), .S0(n890), .Y(n1544) );
MXI2X4TS U1448 ( .A(n1916), .B(n1915), .S0(n905), .Y(n1546) );
MXI2X4TS U1449 ( .A(n861), .B(n2029), .S0(n905), .Y(n1548) );
NOR2X8TS U1450 ( .A(net13816), .B(n837), .Y(net14399) );
AND3X2TS U1451 ( .A(n929), .B(n1513), .C(n837), .Y(net13913) );
NAND2X8TS U1452 ( .A(n1330), .B(n837), .Y(n1091) );
OR2X2TS U1453 ( .A(net13816), .B(n837), .Y(n1588) );
NOR4X1TS U1454 ( .A(n1514), .B(n1511), .C(n1512), .D(n1513), .Y(n1518) );
NAND2X8TS U1455 ( .A(n1513), .B(n907), .Y(n1053) );
INVX8TS U1456 ( .A(n1330), .Y(n929) );
INVX2TS U1457 ( .A(n1511), .Y(n911) );
NOR2X2TS U1458 ( .A(n837), .B(n924), .Y(n1511) );
NOR2X2TS U1459 ( .A(net13817), .B(n924), .Y(n1130) );
INVX16TS U1460 ( .A(net14457), .Y(net13667) );
NOR2X4TS U1461 ( .A(net14848), .B(n2031), .Y(n1416) );
BUFX8TS U1462 ( .A(net15216), .Y(net14848) );
NOR2X6TS U1463 ( .A(net15671), .B(net14448), .Y(net15216) );
AND2X8TS U1464 ( .A(n947), .B(net13899), .Y(n1509) );
NAND2X6TS U1465 ( .A(net15305), .B(net15397), .Y(n935) );
INVX6TS U1466 ( .A(n923), .Y(n1410) );
AND2X8TS U1467 ( .A(n934), .B(net13654), .Y(n1144) );
NOR2X8TS U1468 ( .A(n1807), .B(net13673), .Y(n1181) );
MX2X6TS U1469 ( .A(n847), .B(n1995), .S0(n881), .Y(n918) );
INVX8TS U1470 ( .A(net14755), .Y(net13899) );
NAND2X6TS U1471 ( .A(net13899), .B(n1179), .Y(net14332) );
AND3X6TS U1472 ( .A(net14841), .B(net14374), .C(n1049), .Y(n947) );
BUFX8TS U1473 ( .A(net15081), .Y(n924) );
INVX16TS U1474 ( .A(net14457), .Y(net13666) );
MX2X4TS U1475 ( .A(n921), .B(d_ff2_X[8]), .S0(n925), .Y(n382) );
BUFX12TS U1476 ( .A(net13666), .Y(net13662) );
CLKINVX12TS U1477 ( .A(net15482), .Y(net15798) );
NOR2X8TS U1478 ( .A(net15017), .B(n823), .Y(net13672) );
NAND2BX4TS U1479 ( .AN(n934), .B(d_ff2_Y[24]), .Y(n923) );
INVX16TS U1480 ( .A(net15441), .Y(net15444) );
OR2X6TS U1481 ( .A(n925), .B(n926), .Y(n1192) );
XNOR2X2TS U1482 ( .A(n1502), .B(n1715), .Y(n1503) );
MX2X4TS U1483 ( .A(d_ff3_sh_y_out[2]), .B(d_ff2_Y[2]), .S0(net14325), .Y(
n458) );
BUFX16TS U1484 ( .A(net13666), .Y(net13665) );
NOR2X4TS U1485 ( .A(n951), .B(n1704), .Y(n726) );
INVX16TS U1486 ( .A(net15445), .Y(net15759) );
MX2X4TS U1487 ( .A(n928), .B(d_ff2_X[22]), .S0(net14325), .Y(n354) );
INVX8TS U1488 ( .A(net6713), .Y(net15304) );
BUFX20TS U1489 ( .A(cont_iter_out_2_), .Y(net13673) );
NAND2X8TS U1490 ( .A(net14755), .B(net14152), .Y(net14331) );
INVX16TS U1491 ( .A(n965), .Y(n1330) );
NOR2X4TS U1492 ( .A(net13816), .B(n929), .Y(n1049) );
NAND2X4TS U1493 ( .A(net13943), .B(d_ff2_X[24]), .Y(n1297) );
OR2X4TS U1494 ( .A(net13943), .B(d_ff2_X[24]), .Y(n1180) );
NAND3X4TS U1495 ( .A(n933), .B(n1394), .C(n1393), .Y(n2133) );
XNOR2X1TS U1496 ( .A(n934), .B(d_ff2_X[24]), .Y(n1502) );
NAND2X1TS U1497 ( .A(n908), .B(net14857), .Y(n1147) );
OAI21X2TS U1498 ( .A0(d_ff2_Y[30]), .A1(n1500), .B0(net14072), .Y(n1402) );
INVX2TS U1499 ( .A(n959), .Y(n1457) );
NAND3BX1TS U1500 ( .AN(n1024), .B(n1623), .C(n1624), .Y(add_subt_dataA[14])
);
NAND2X2TS U1501 ( .A(n1378), .B(net15103), .Y(n1105) );
NAND2X2TS U1502 ( .A(n1478), .B(d_ff_Yn[25]), .Y(n1104) );
INVX12TS U1503 ( .A(n946), .Y(n1092) );
NOR2X2TS U1504 ( .A(net14404), .B(n924), .Y(n1491) );
INVX2TS U1505 ( .A(n1298), .Y(n1296) );
INVX2TS U1506 ( .A(n1293), .Y(n1294) );
INVX2TS U1507 ( .A(n958), .Y(n1460) );
INVX2TS U1508 ( .A(n974), .Y(n1012) );
AOI21X2TS U1509 ( .A0(n1421), .A1(net13654), .B0(n1704), .Y(n725) );
AOI22X2TS U1510 ( .A0(n1078), .A1(net15425), .B0(n1799), .B1(n1379), .Y(n375) );
NAND2X2TS U1511 ( .A(n1706), .B(d_ff_Yn[22]), .Y(n1447) );
INVX3TS U1512 ( .A(n999), .Y(n1000) );
NOR2X2TS U1513 ( .A(n911), .B(beg_fsm_cordic), .Y(n1146) );
OAI2BB1X1TS U1514 ( .A0N(d_ff3_LUT_out[18]), .A1N(net13667), .B0(n1487), .Y(
n506) );
AOI22X2TS U1515 ( .A0(n918), .A1(n1478), .B0(n976), .B1(n1876), .Y(n352) );
NAND2X2TS U1516 ( .A(n1706), .B(n597), .Y(n1707) );
NAND2X2TS U1517 ( .A(n1706), .B(d_ff_Yn[24]), .Y(n1440) );
INVX2TS U1518 ( .A(n1546), .Y(n2090) );
INVX2TS U1519 ( .A(n1544), .Y(n2093) );
INVX2TS U1520 ( .A(n1553), .Y(n2067) );
INVX2TS U1521 ( .A(n1560), .Y(n2069) );
INVX2TS U1522 ( .A(n1557), .Y(n2076) );
INVX2TS U1523 ( .A(n1555), .Y(n2083) );
NAND2X2TS U1524 ( .A(n1419), .B(n1527), .Y(n2135) );
INVX2TS U1525 ( .A(n1418), .Y(n1394) );
NAND2X2TS U1526 ( .A(n1514), .B(n1334), .Y(n974) );
MXI2X2TS U1527 ( .A(n1415), .B(n1721), .S0(n1414), .Y(n2109) );
MXI2X1TS U1528 ( .A(n1718), .B(n1714), .S0(net13662), .Y(n2104) );
NAND3X4TS U1529 ( .A(net13951), .B(net15394), .C(net13671), .Y(n1872) );
OAI21X2TS U1530 ( .A0(n1279), .A1(n1278), .B0(net14325), .Y(n1280) );
OAI22X2TS U1531 ( .A0(n1289), .A1(n1288), .B0(net13951), .B1(n1605), .Y(
n2121) );
AOI22X1TS U1532 ( .A0(net13672), .A1(net13673), .B0(net13674), .B1(net14851),
.Y(net6074) );
CLKBUFX3TS U1533 ( .A(n2051), .Y(n1909) );
OR2X2TS U1534 ( .A(n1025), .B(n1829), .Y(n1031) );
NAND2X2TS U1535 ( .A(n1078), .B(n1544), .Y(n1304) );
OR2X2TS U1536 ( .A(n1025), .B(n1828), .Y(n1030) );
NAND2X2TS U1537 ( .A(n1046), .B(n1555), .Y(n1312) );
OR2X2TS U1538 ( .A(n1025), .B(n1826), .Y(n1029) );
NAND2X2TS U1539 ( .A(n1478), .B(n622), .Y(n1451) );
MXI2X1TS U1540 ( .A(n1761), .B(n1863), .S0(net14689), .Y(n418) );
INVX2TS U1541 ( .A(n988), .Y(n2045) );
NAND2X2TS U1542 ( .A(n1047), .B(n1547), .Y(n1314) );
NAND2X2TS U1543 ( .A(n1078), .B(d_ff_Yn[8]), .Y(n1473) );
NAND2X2TS U1544 ( .A(n1047), .B(n1552), .Y(n1313) );
NAND2X2TS U1545 ( .A(n1378), .B(d_ff_Yn[2]), .Y(n1157) );
INVX2TS U1546 ( .A(n988), .Y(n990) );
NAND2X2TS U1547 ( .A(n1047), .B(d_ff_Yn[0]), .Y(n1467) );
NAND2X1TS U1548 ( .A(n1050), .B(d_ff2_Z[28]), .Y(n1176) );
NAND3X2TS U1549 ( .A(n1016), .B(n1019), .C(n1017), .Y(n475) );
NAND2X1TS U1550 ( .A(n1379), .B(d_ff2_Z[15]), .Y(n1347) );
NAND2X4TS U1551 ( .A(n1068), .B(n1044), .Y(n1348) );
NAND2X1TS U1552 ( .A(n1379), .B(d_ff2_Z[14]), .Y(n1341) );
NAND2X4TS U1553 ( .A(n1066), .B(n1044), .Y(n1342) );
NAND2X4TS U1554 ( .A(n1065), .B(n1044), .Y(n1339) );
NAND2X2TS U1555 ( .A(n1014), .B(d_ff2_Z[12]), .Y(n1369) );
NAND2X1TS U1556 ( .A(n1379), .B(d_ff2_Z[11]), .Y(n1380) );
NAND2X4TS U1557 ( .A(n1064), .B(n1044), .Y(n1381) );
NAND2X1TS U1558 ( .A(d_ff2_Z[1]), .B(n1050), .Y(n1194) );
OR2X2TS U1559 ( .A(n1025), .B(n949), .Y(n1326) );
NAND3X2TS U1560 ( .A(n2081), .B(net5805), .C(n1333), .Y(n514) );
AOI2BB2X2TS U1561 ( .B0(n1481), .B1(net14376), .A0N(net13951), .A1N(
d_ff3_LUT_out[9]), .Y(n515) );
INVX2TS U1562 ( .A(n977), .Y(n979) );
NAND3X2TS U1563 ( .A(n1490), .B(n2106), .C(n1489), .Y(n522) );
NAND3X2TS U1564 ( .A(n932), .B(net13673), .C(net13672), .Y(n1490) );
NAND2X1TS U1565 ( .A(n1122), .B(sign_inv_out[28]), .Y(n1204) );
NAND2X2TS U1566 ( .A(n1006), .B(net15103), .Y(n1206) );
NAND2X1TS U1567 ( .A(n1122), .B(sign_inv_out[27]), .Y(n1150) );
INVX2TS U1568 ( .A(n981), .Y(n982) );
NAND2X1TS U1569 ( .A(n1271), .B(sign_inv_out[19]), .Y(n1246) );
NAND2X1TS U1570 ( .A(n1271), .B(sign_inv_out[17]), .Y(n1251) );
NAND2X2TS U1571 ( .A(n1271), .B(sign_inv_out[13]), .Y(n1263) );
NAND2X2TS U1572 ( .A(n1271), .B(sign_inv_out[12]), .Y(n1266) );
CLKINVX3TS U1573 ( .A(n988), .Y(n989) );
NAND2X2TS U1574 ( .A(n1086), .B(n1461), .Y(n1221) );
NAND2X1TS U1575 ( .A(n1271), .B(sign_inv_out[6]), .Y(n1222) );
INVX2TS U1576 ( .A(n977), .Y(n997) );
NAND2X2TS U1577 ( .A(n1086), .B(n1456), .Y(n1232) );
NAND2X2TS U1578 ( .A(n1036), .B(net15101), .Y(n1231) );
NAND2X2TS U1579 ( .A(n993), .B(n1442), .Y(n1238) );
CLKINVX3TS U1580 ( .A(n977), .Y(n978) );
INVX2TS U1581 ( .A(n999), .Y(n995) );
CLKINVX3TS U1582 ( .A(n1508), .Y(n2044) );
CLKINVX3TS U1583 ( .A(n999), .Y(n2042) );
MXI2X4TS U1584 ( .A(net13887), .B(net7520), .S0(net15794), .Y(n640) );
MXI2X2TS U1585 ( .A(net5420), .B(net15104), .S0(net15794), .Y(n624) );
MXI2X4TS U1586 ( .A(net5649), .B(net7560), .S0(net15444), .Y(n621) );
INVX16TS U1587 ( .A(net13909), .Y(net15441) );
INVX16TS U1588 ( .A(net15441), .Y(net15794) );
NAND2X8TS U1589 ( .A(net13912), .B(net14333), .Y(net13909) );
MXI2X4TS U1590 ( .A(net13887), .B(net7544), .S0(net6643), .Y(n672) );
NAND2X8TS U1591 ( .A(net14331), .B(net14440), .Y(net13912) );
NAND2X8TS U1592 ( .A(net13912), .B(net14333), .Y(net15433) );
MXI2X2TS U1593 ( .A(sel_mux_2_reg[0]), .B(net13912), .S0(net13913), .Y(
net13910) );
OAI21X4TS U1594 ( .A0(net13653), .A1(net13968), .B0(cont_var_out[0]), .Y(
net14440) );
AND3X8TS U1595 ( .A(net14444), .B(net14399), .C(net14404), .Y(net14333) );
NAND2X8TS U1596 ( .A(net15483), .B(net14333), .Y(net15482) );
NAND2BX1TS U1597 ( .AN(net13948), .B(n919), .Y(net13967) );
NAND2X1TS U1598 ( .A(net13950), .B(n919), .Y(net14376) );
AND2X8TS U1599 ( .A(net13899), .B(cont_var_out[0]), .Y(net15434) );
AOI21X2TS U1600 ( .A0(net14447), .A1(ack_add_subt), .B0(cont_var_out[0]),
.Y(net14445) );
XNOR2X1TS U1601 ( .A(cont_var_out[0]), .B(d_ff3_sign_out), .Y(op_add_subt)
);
BUFX3TS U1602 ( .A(cordic_FSM_state_reg_0_), .Y(net13896) );
MXI2X4TS U1603 ( .A(net5513), .B(net7519), .S0(net15759), .Y(n636) );
MXI2X2TS U1604 ( .A(net5617), .B(net15102), .S0(net15446), .Y(n649) );
MXI2X4TS U1605 ( .A(net5449), .B(net7526), .S0(net15447), .Y(n628) );
INVX16TS U1606 ( .A(net15433), .Y(net15445) );
INVX16TS U1607 ( .A(net15445), .Y(net15447) );
NOR2X4TS U1608 ( .A(n822), .B(n823), .Y(net13671) );
XOR2X4TS U1609 ( .A(net14838), .B(n932), .Y(net14080) );
XOR2X4TS U1610 ( .A(n936), .B(d_ff1_operation_out), .Y(net14152) );
XOR2X4TS U1611 ( .A(net15155), .B(n937), .Y(n936) );
NOR2X2TS U1612 ( .A(d_ff1_operation_out), .B(net15155), .Y(net14160) );
NAND2X2TS U1613 ( .A(net13969), .B(cont_iter_out_2_), .Y(net5801) );
INVX8TS U1614 ( .A(cont_iter_out_2_), .Y(net13960) );
OR2X8TS U1615 ( .A(net13816), .B(net14404), .Y(n946) );
NOR2X2TS U1616 ( .A(net13910), .B(n1508), .Y(n2169) );
NAND2X8TS U1617 ( .A(n1183), .B(n1295), .Y(n939) );
NAND2X4TS U1618 ( .A(net14847), .B(net14330), .Y(n940) );
AND2X8TS U1619 ( .A(net14404), .B(net13817), .Y(n1514) );
BUFX4TS U1620 ( .A(n1025), .Y(n1013) );
INVX4TS U1621 ( .A(n1704), .Y(n1001) );
BUFX12TS U1622 ( .A(net13666), .Y(net13657) );
BUFX12TS U1623 ( .A(n1050), .Y(n992) );
BUFX8TS U1624 ( .A(n1050), .Y(n1014) );
CLKINVX3TS U1625 ( .A(n1012), .Y(n2056) );
INVX2TS U1626 ( .A(n2033), .Y(n988) );
INVX2TS U1627 ( .A(n1012), .Y(n986) );
INVX2TS U1628 ( .A(n981), .Y(n984) );
INVX2TS U1629 ( .A(n981), .Y(n983) );
INVX2TS U1630 ( .A(n988), .Y(n2047) );
INVX2TS U1631 ( .A(n977), .Y(n2046) );
INVX2TS U1632 ( .A(n1012), .Y(n2033) );
INVX2TS U1633 ( .A(n999), .Y(n2039) );
INVX2TS U1634 ( .A(n977), .Y(n996) );
INVX2TS U1635 ( .A(n2037), .Y(n999) );
INVX2TS U1636 ( .A(n2034), .Y(n977) );
INVX2TS U1637 ( .A(n988), .Y(n987) );
INVX2TS U1638 ( .A(n988), .Y(n991) );
INVX2TS U1639 ( .A(n988), .Y(n968) );
INVX2TS U1640 ( .A(n981), .Y(n967) );
NAND2X4TS U1641 ( .A(n1514), .B(n1334), .Y(n973) );
INVX2TS U1642 ( .A(n985), .Y(n981) );
INVX2TS U1643 ( .A(n981), .Y(n2034) );
AND2X8TS U1644 ( .A(net6633), .B(cont_var_out[1]), .Y(net14841) );
XNOR2X4TS U1645 ( .A(n952), .B(n927), .Y(n951) );
NAND3X6TS U1646 ( .A(n1188), .B(n1187), .C(n1186), .Y(n341) );
NAND3X4TS U1647 ( .A(n939), .B(net14325), .C(n1279), .Y(n1186) );
OAI21X2TS U1648 ( .A0(d_ff2_X[29]), .A1(n1722), .B0(n1482), .Y(n2128) );
MX2X4TS U1649 ( .A(n860), .B(n2024), .S0(n864), .Y(n958) );
AOI2BB2X4TS U1650 ( .B0(n1276), .B1(n806), .A0N(n1526), .A1N(n806), .Y(n1184) );
MX2X4TS U1651 ( .A(n1981), .B(n1980), .S0(n849), .Y(n959) );
NAND2X8TS U1652 ( .A(n1298), .B(n1293), .Y(n1183) );
BUFX12TS U1653 ( .A(net14383), .Y(net14753) );
INVX16TS U1654 ( .A(n1091), .Y(n1492) );
INVX2TS U1655 ( .A(net15101), .Y(net15102) );
INVX2TS U1656 ( .A(net15103), .Y(net15104) );
AND2X8TS U1657 ( .A(d_ff2_Y[25]), .B(net13960), .Y(n1190) );
INVX16TS U1658 ( .A(net15081), .Y(net13816) );
AOI22X2TS U1659 ( .A0(n1078), .A1(n944), .B0(n1798), .B1(n1051), .Y(n379) );
INVX12TS U1660 ( .A(n1704), .Y(n1705) );
NAND2X2TS U1661 ( .A(n1007), .B(d_ff_Yn[14]), .Y(n1479) );
AND2X4TS U1662 ( .A(n1144), .B(net13670), .Y(n1142) );
AND2X8TS U1663 ( .A(net13673), .B(net15397), .Y(n2030) );
CLKINVX3TS U1664 ( .A(n1508), .Y(n2043) );
INVX2TS U1665 ( .A(n999), .Y(n969) );
INVX2TS U1666 ( .A(n977), .Y(n970) );
INVX2TS U1667 ( .A(n999), .Y(n971) );
INVX2TS U1668 ( .A(n977), .Y(n972) );
AOI22X2TS U1669 ( .A0(n980), .A1(n2074), .B0(n1797), .B1(n975), .Y(n385) );
AOI22X2TS U1670 ( .A0(n980), .A1(n2072), .B0(n1796), .B1(n975), .Y(n387) );
NAND2X2TS U1671 ( .A(n975), .B(d_ff2_Z[6]), .Y(n1113) );
NAND2X2TS U1672 ( .A(n976), .B(d_ff2_Z[30]), .Y(n1452) );
NAND2X2TS U1673 ( .A(n976), .B(d_ff2_Z[5]), .Y(n1110) );
NAND2X2TS U1674 ( .A(n976), .B(d_ff2_Z[8]), .Y(n1116) );
NAND2X2TS U1675 ( .A(n976), .B(d_ff2_Z[9]), .Y(n1372) );
NAND2X2TS U1676 ( .A(n975), .B(d_ff2_Z[20]), .Y(n1344) );
NAND2X2TS U1677 ( .A(n975), .B(d_ff2_Z[13]), .Y(n1338) );
NAND2X2TS U1678 ( .A(n976), .B(d_ff2_Z[3]), .Y(n1323) );
NAND2X2TS U1679 ( .A(n976), .B(d_ff2_Z[4]), .Y(n1320) );
NAND2X2TS U1680 ( .A(n992), .B(d_ff2_Z[10]), .Y(n1375) );
INVX3TS U1681 ( .A(n1012), .Y(n985) );
AOI22X2TS U1682 ( .A0(n917), .A1(n1378), .B0(n1014), .B1(n1807), .Y(n351) );
AOI22X2TS U1683 ( .A0(n2113), .A1(n1047), .B0(n1051), .B1(n1868), .Y(n350)
);
AOI22X2TS U1684 ( .A0(n1078), .A1(n899), .B0(n1867), .B1(n1051), .Y(n349) );
AOI22X2TS U1685 ( .A0(n960), .A1(n1046), .B0(n1793), .B1(n1051), .Y(n347) );
MXI2X2TS U1686 ( .A(n1134), .B(net6761), .S0(n1705), .Y(n723) );
MXI2X2TS U1687 ( .A(n1703), .B(net15156), .S0(n1705), .Y(n721) );
INVX16TS U1688 ( .A(n1082), .Y(n1704) );
AOI22X2TS U1689 ( .A0(n1046), .A1(n903), .B0(n1014), .B1(n1803), .Y(n359) );
CLKMX2X2TS U1690 ( .A(data_in[6]), .B(d_ff1_Z[6]), .S0(n998), .Y(n714) );
CLKMX2X2TS U1691 ( .A(data_in[27]), .B(d_ff1_Z[27]), .S0(n998), .Y(n693) );
CLKMX2X2TS U1692 ( .A(data_in[13]), .B(d_ff1_Z[13]), .S0(n998), .Y(n707) );
CLKMX2X2TS U1693 ( .A(data_in[12]), .B(d_ff1_Z[12]), .S0(n998), .Y(n708) );
CLKMX2X2TS U1694 ( .A(data_in[11]), .B(d_ff1_Z[11]), .S0(n998), .Y(n709) );
CLKMX2X2TS U1695 ( .A(data_in[10]), .B(d_ff1_Z[10]), .S0(n998), .Y(n710) );
CLKMX2X2TS U1696 ( .A(data_in[9]), .B(d_ff1_Z[9]), .S0(n998), .Y(n711) );
CLKMX2X2TS U1697 ( .A(data_in[8]), .B(d_ff1_Z[8]), .S0(n998), .Y(n712) );
CLKMX2X2TS U1698 ( .A(data_in[7]), .B(d_ff1_Z[7]), .S0(n998), .Y(n713) );
CLKMX2X2TS U1699 ( .A(data_in[5]), .B(d_ff1_Z[5]), .S0(n998), .Y(n715) );
BUFX20TS U1700 ( .A(n1121), .Y(n1006) );
AOI22X2TS U1701 ( .A0(n1007), .A1(n2096), .B0(n1802), .B1(n1050), .Y(n361)
);
NAND2X2TS U1702 ( .A(n1047), .B(d_ff_Zn[21]), .Y(n1016) );
NAND2X2TS U1703 ( .A(n1047), .B(n1539), .Y(n1364) );
NAND2X2TS U1704 ( .A(n1078), .B(n1542), .Y(n1361) );
NAND2X2TS U1705 ( .A(n1078), .B(n1534), .Y(n1178) );
AOI22X2TS U1706 ( .A0(n1007), .A1(n898), .B0(n1801), .B1(n1379), .Y(n365) );
AOI22X2TS U1707 ( .A0(n1007), .A1(n2064), .B0(n1794), .B1(n1379), .Y(n393)
);
NAND2X2TS U1708 ( .A(n1271), .B(sign_inv_out[10]), .Y(n1208) );
MXI2X1TS U1709 ( .A(n1799), .B(n2085), .S0(net14971), .Y(n374) );
NAND2X2TS U1710 ( .A(n1498), .B(n1558), .Y(n1468) );
INVX2TS U1711 ( .A(n1010), .Y(n1011) );
NAND3X2TS U1712 ( .A(n1025), .B(d_ff1_Z[1]), .C(n1041), .Y(n1195) );
NAND2X2TS U1713 ( .A(n1086), .B(n1555), .Y(n1269) );
MXI2X4TS U1714 ( .A(n2023), .B(n2022), .S0(n2021), .Y(n1555) );
NAND2X2TS U1715 ( .A(n1085), .B(n1546), .Y(n1256) );
NAND2X2TS U1716 ( .A(n1046), .B(n1546), .Y(n1305) );
NAND2X2TS U1717 ( .A(n1046), .B(n1559), .Y(n1307) );
OAI21X2TS U1718 ( .A0(d_ff2_X[30]), .A1(n1793), .B0(net14325), .Y(n1531) );
NAND2X2TS U1719 ( .A(n1690), .B(d_ff2_X[30]), .Y(n1685) );
AND2X8TS U1720 ( .A(n1330), .B(ready_add_subt), .Y(net14444) );
MXI2X4TS U1721 ( .A(n868), .B(n915), .S0(n864), .Y(n597) );
NOR2X8TS U1722 ( .A(n1420), .B(net13805), .Y(n1143) );
NAND3X8TS U1723 ( .A(n1520), .B(n806), .C(n1526), .Y(n1188) );
OAI21X2TS U1724 ( .A0(n1021), .A1(n1751), .B0(n1473), .Y(n447) );
NAND2X2TS U1725 ( .A(net13805), .B(d_ff3_LUT_out[2]), .Y(n1489) );
NAND3X1TS U1726 ( .A(n1708), .B(d_ff1_Z[2]), .C(n1041), .Y(n1318) );
NAND3X1TS U1727 ( .A(n1052), .B(d_ff1_Z[4]), .C(n1041), .Y(n1321) );
NAND3X1TS U1728 ( .A(n1708), .B(d_ff1_Z[3]), .C(n1041), .Y(n1324) );
OAI21X2TS U1729 ( .A0(n1021), .A1(n1748), .B0(n1313), .Y(n455) );
OAI21X2TS U1730 ( .A0(n1021), .A1(n1746), .B0(n1157), .Y(n459) );
OAI21X2TS U1731 ( .A0(n1021), .A1(n1022), .B0(n1469), .Y(n461) );
OAI21X2TS U1732 ( .A0(n1021), .A1(n1825), .B0(n1309), .Y(n391) );
OAI21X2TS U1733 ( .A0(n1021), .A1(n1824), .B0(n1468), .Y(n399) );
OAI21X2TS U1734 ( .A0(n1021), .A1(n1747), .B0(n1310), .Y(n453) );
NAND2X2TS U1735 ( .A(net13805), .B(d_ff3_LUT_out[10]), .Y(n1333) );
AOI21X4TS U1736 ( .A0(net13671), .A1(n927), .B0(n2030), .Y(n1485) );
NAND2X2TS U1737 ( .A(n992), .B(d_ff2_Z[7]), .Y(n1119) );
AOI2BB1X4TS U1738 ( .A0N(n956), .A1N(d_ff2_Y[30]), .B0(n1402), .Y(n1408) );
NAND3X4TS U1739 ( .A(n1409), .B(n1408), .C(n1407), .Y(n2131) );
NAND2X2TS U1740 ( .A(n1059), .B(n1708), .Y(n1168) );
NAND2X2TS U1741 ( .A(n1014), .B(d_ff2_Z[19]), .Y(n1167) );
NAND2X2TS U1742 ( .A(n1014), .B(d_ff2_Z[18]), .Y(n1158) );
NAND2X2TS U1743 ( .A(n1014), .B(d_ff2_Z[17]), .Y(n1161) );
NAND2X2TS U1744 ( .A(n1014), .B(d_ff2_Z[16]), .Y(n1164) );
XOR2X4TS U1745 ( .A(n1383), .B(cont_var_out[1]), .Y(n1384) );
NAND3BX4TS U1746 ( .AN(n1080), .B(n1120), .C(n1119), .Y(n489) );
NAND2BX4TS U1747 ( .AN(n992), .B(n1073), .Y(n1019) );
NOR2X8TS U1748 ( .A(net13667), .B(n2030), .Y(n1530) );
NAND2X2TS U1749 ( .A(n1271), .B(sign_inv_out[2]), .Y(n1239) );
OAI2BB1X4TS U1750 ( .A0N(d_ff_Yn[1]), .A1N(n1006), .B0(n1244), .Y(n1043) );
OAI2BB1X4TS U1751 ( .A0N(d_ff_Yn[0]), .A1N(n1036), .B0(n1249), .Y(n1042) );
MXI2X4TS U1752 ( .A(n858), .B(n2010), .S0(n2009), .Y(n1545) );
MXI2X4TS U1753 ( .A(n1999), .B(n1998), .S0(n838), .Y(n1556) );
MXI2X4TS U1754 ( .A(n868), .B(n2013), .S0(n880), .Y(n1543) );
NAND2X2TS U1755 ( .A(n1006), .B(n1423), .Y(n1152) );
XNOR2X4TS U1756 ( .A(n1725), .B(n1037), .Y(n1193) );
CLKXOR2X2TS U1757 ( .A(n823), .B(d_ff2_Y[26]), .Y(n1037) );
INVX16TS U1758 ( .A(n1053), .Y(n1052) );
INVX16TS U1759 ( .A(net14189), .Y(net13889) );
MXI2X4TS U1760 ( .A(n865), .B(n1929), .S0(n1928), .Y(n1535) );
NAND2BX4TS U1761 ( .AN(n1042), .B(n1248), .Y(n588) );
MXI2X4TS U1762 ( .A(n859), .B(n2026), .S0(n2025), .Y(n1552) );
MXI2X4TS U1763 ( .A(n861), .B(n2008), .S0(n838), .Y(n1547) );
AOI22X2TS U1764 ( .A0(n1007), .A1(n2062), .B0(n1792), .B1(n992), .Y(n395) );
NAND2X2TS U1765 ( .A(n992), .B(d_ff2_Z[31]), .Y(n1172) );
OAI2BB1X4TS U1766 ( .A0N(n1045), .A1N(n1127), .B0(n924), .Y(n1129) );
NAND3X4TS U1767 ( .A(net13951), .B(net14213), .C(net13654), .Y(n1290) );
NAND3X8TS U1768 ( .A(n1092), .B(n1492), .C(n909), .Y(n1081) );
NAND2X8TS U1769 ( .A(n1513), .B(n1492), .Y(n1082) );
NAND2X2TS U1770 ( .A(n1087), .B(n1465), .Y(n1245) );
NAND2X2TS U1771 ( .A(n1085), .B(n1459), .Y(n1254) );
NAND2X2TS U1772 ( .A(n1085), .B(n1549), .Y(n1241) );
NAND2X2TS U1773 ( .A(n1085), .B(n1550), .Y(n1201) );
NAND2X2TS U1774 ( .A(n1085), .B(n1466), .Y(n1139) );
NAND2X2TS U1775 ( .A(n1085), .B(n1464), .Y(n1151) );
NAND2X2TS U1776 ( .A(n1085), .B(n1203), .Y(n1205) );
NOR2X8TS U1777 ( .A(n946), .B(n909), .Y(n1090) );
NAND2X2TS U1778 ( .A(n1494), .B(n1365), .Y(n1493) );
NAND3X2TS U1779 ( .A(n1406), .B(n1405), .C(n1404), .Y(n1407) );
NAND2X2TS U1780 ( .A(n1047), .B(n1561), .Y(n1102) );
NAND3X4TS U1781 ( .A(n1401), .B(n1400), .C(n1399), .Y(n1409) );
AND2X4TS U1782 ( .A(n1505), .B(n956), .Y(n1289) );
NAND4X2TS U1783 ( .A(n1405), .B(n956), .C(n1404), .D(n1500), .Y(n1391) );
OAI21X2TS U1784 ( .A0(d_ff2_Y[29]), .A1(n956), .B0(n1389), .Y(n1390) );
OAI21X2TS U1785 ( .A0(d_ff2_Y[29]), .A1(n1528), .B0(n1724), .Y(n1389) );
MXI2X4TS U1786 ( .A(n1484), .B(n1864), .S0(net13665), .Y(n408) );
XOR2X2TS U1787 ( .A(n1483), .B(n1709), .Y(n1484) );
OAI2BB1X2TS U1788 ( .A0N(d_ff2_X[30]), .A1N(n1051), .B0(n1450), .Y(n346) );
AOI22X2TS U1789 ( .A0(n1505), .A1(n1869), .B0(n1504), .B1(d_ff2_Y[27]), .Y(
n1507) );
NAND2X2TS U1790 ( .A(n1706), .B(n901), .Y(n1444) );
NAND2X2TS U1791 ( .A(n1706), .B(n1550), .Y(n1443) );
AOI22X2TS U1792 ( .A0(n1007), .A1(n904), .B0(n1791), .B1(n992), .Y(n397) );
NAND2X2TS U1793 ( .A(n1478), .B(n1423), .Y(n1095) );
NAND2X2TS U1794 ( .A(n1478), .B(d_ff_Yn[29]), .Y(n1499) );
NAND2X2TS U1795 ( .A(n1378), .B(d_ff_Yn[26]), .Y(n1103) );
NAND2X8TS U1796 ( .A(n1709), .B(n1189), .Y(n1411) );
NOR2X4TS U1797 ( .A(net13816), .B(n1330), .Y(n1331) );
NAND2X6TS U1798 ( .A(n1411), .B(n1386), .Y(n1191) );
NAND2X6TS U1799 ( .A(n1866), .B(net13673), .Y(n1387) );
NOR2X4TS U1800 ( .A(n1510), .B(n1704), .Y(n728) );
OAI2BB1X2TS U1801 ( .A0N(d_ff2_Y[16]), .A1N(n976), .B0(n1475), .Y(n431) );
OAI2BB1X2TS U1802 ( .A0N(d_ff2_Y[18]), .A1N(n1051), .B0(n1477), .Y(n427) );
NAND2X2TS U1803 ( .A(n1721), .B(net13653), .Y(n2112) );
NAND2X2TS U1804 ( .A(n1721), .B(net13654), .Y(n2116) );
OAI2BB1X2TS U1805 ( .A0N(d_ff2_X[22]), .A1N(n1014), .B0(n1443), .Y(n355) );
OAI2BB1X2TS U1806 ( .A0N(d_ff2_Y[17]), .A1N(n1014), .B0(n1474), .Y(n429) );
NAND3X2TS U1807 ( .A(n1453), .B(n1452), .C(n1454), .Y(n466) );
NAND2X8TS U1808 ( .A(n1514), .B(n1331), .Y(n1700) );
NAND2X2TS U1809 ( .A(n1085), .B(n1561), .Y(n1124) );
NAND2X2TS U1810 ( .A(n993), .B(n1441), .Y(n1243) );
NAND2X2TS U1811 ( .A(n994), .B(n1558), .Y(n1248) );
NAND2X2TS U1812 ( .A(n1006), .B(d_ff_Yn[31]), .Y(n1125) );
MXI2X2TS U1813 ( .A(n1711), .B(n1710), .S0(net13657), .Y(n2102) );
MXI2X4TS U1814 ( .A(n2142), .B(n1832), .S0(net15444), .Y(n646) );
MXI2X4TS U1815 ( .A(n2148), .B(n1842), .S0(net15759), .Y(n638) );
MXI2X4TS U1816 ( .A(n2155), .B(n1839), .S0(net15759), .Y(n630) );
MXI2X4TS U1817 ( .A(n2139), .B(n1844), .S0(net15442), .Y(n650) );
MXI2X4TS U1818 ( .A(n1519), .B(n1841), .S0(net15446), .Y(n642) );
MXI2X4TS U1819 ( .A(n2151), .B(n1843), .S0(net15794), .Y(n634) );
MXI2X4TS U1820 ( .A(n2159), .B(n1840), .S0(net15442), .Y(n626) );
OAI21X2TS U1821 ( .A0(n1501), .A1(n1873), .B0(net14325), .Y(n1288) );
OAI21X4TS U1822 ( .A0(d_ff2_Y[25]), .A1(n1413), .B0(n1412), .Y(n1414) );
NAND3BX2TS U1823 ( .AN(n1524), .B(n1523), .C(n1522), .Y(n513) );
NAND3BX2TS U1824 ( .AN(n1524), .B(n1523), .C(n1521), .Y(n517) );
MXI2X4TS U1825 ( .A(n2145), .B(n1815), .S0(net6643), .Y(n675) );
MXI2X4TS U1826 ( .A(n2141), .B(n1812), .S0(net6643), .Y(n679) );
MXI2X4TS U1827 ( .A(n2142), .B(n1813), .S0(net6643), .Y(n678) );
MXI2X4TS U1828 ( .A(n2150), .B(n1819), .S0(net6643), .Y(n667) );
MXI2X4TS U1829 ( .A(n2144), .B(n1835), .S0(net15447), .Y(n644) );
MXI2X4TS U1830 ( .A(n2153), .B(n1834), .S0(net15447), .Y(n632) );
MXI2X4TS U1831 ( .A(n2137), .B(n1845), .S0(net15794), .Y(n652) );
MXI2X4TS U1832 ( .A(n2165), .B(n1838), .S0(net15759), .Y(n623) );
MXI2X4TS U1833 ( .A(n2158), .B(n1837), .S0(net15446), .Y(n627) );
MXI2X4TS U1834 ( .A(n2154), .B(n1836), .S0(net15446), .Y(n631) );
MXI2X4TS U1835 ( .A(n2146), .B(n1806), .S0(net15444), .Y(n641) );
MXI2X4TS U1836 ( .A(n2138), .B(n1833), .S0(net15442), .Y(n651) );
MXI2X4TS U1837 ( .A(n1519), .B(n1816), .S0(net13889), .Y(n674) );
MXI2X4TS U1838 ( .A(n2147), .B(n1742), .S0(net13889), .Y(n671) );
MXI2X4TS U1839 ( .A(n2137), .B(n1808), .S0(net6643), .Y(n684) );
MXI2X4TS U1840 ( .A(n2148), .B(n1817), .S0(net13889), .Y(n670) );
MXI2X4TS U1841 ( .A(n2154), .B(n1743), .S0(net13889), .Y(n663) );
MXI2X4TS U1842 ( .A(n2144), .B(n1741), .S0(net6644), .Y(n676) );
MXI2X4TS U1843 ( .A(n2140), .B(n1740), .S0(net6644), .Y(n680) );
MXI2X4TS U1844 ( .A(n2152), .B(n1821), .S0(net13889), .Y(n665) );
MXI2X4TS U1845 ( .A(n2146), .B(n1831), .S0(net6644), .Y(n673) );
MXI2X4TS U1846 ( .A(n2151), .B(n1820), .S0(net6644), .Y(n666) );
MXI2X4TS U1847 ( .A(n2143), .B(n1814), .S0(net6644), .Y(n677) );
MXI2X4TS U1848 ( .A(n2153), .B(n1822), .S0(net6644), .Y(n664) );
OAI21X2TS U1849 ( .A0(n1518), .A1(n1330), .B0(n1517), .Y(n731) );
NAND2X4TS U1850 ( .A(n1530), .B(net15160), .Y(n1487) );
AO21X4TS U1851 ( .A0(d_ff3_LUT_out[19]), .A1(net13805), .B0(n1530), .Y(n505)
);
NAND2X4TS U1852 ( .A(n1530), .B(net13950), .Y(n1486) );
OAI21X2TS U1853 ( .A0(n1005), .A1(n2157), .B0(n1440), .Y(n416) );
NAND2X2TS U1854 ( .A(n1284), .B(net14072), .Y(n1286) );
NOR2X4TS U1855 ( .A(n1276), .B(n806), .Y(n1279) );
MXI2X1TS U1856 ( .A(shift_region_flag[0]), .B(n937), .S0(n1001), .Y(n1093)
);
OR2X8TS U1857 ( .A(net7462), .B(sel_mux_2_reg[1]), .Y(n1094) );
INVX2TS U1858 ( .A(n1727), .Y(n1712) );
NAND2X1TS U1859 ( .A(n1680), .B(d_ff2_Z[8]), .Y(n1650) );
NAND2X1TS U1860 ( .A(n1680), .B(d_ff2_Z[9]), .Y(n1644) );
NAND2X1TS U1861 ( .A(n807), .B(d_ff2_Z[15]), .Y(n1656) );
INVX2TS U1862 ( .A(result_add_subt[27]), .Y(n2162) );
OAI2BB1X2TS U1864 ( .A0N(d_ff2_Y[27]), .A1N(n992), .B0(n1095), .Y(n413) );
INVX2TS U1865 ( .A(n1141), .Y(n1099) );
NAND2X1TS U1866 ( .A(n1144), .B(net15395), .Y(n1097) );
OR2X2TS U1867 ( .A(net15017), .B(n1097), .Y(n1098) );
NAND2X4TS U1868 ( .A(n1383), .B(net14689), .Y(n1101) );
NAND2X8TS U1869 ( .A(n1092), .B(n1492), .Y(n1210) );
NAND2X1TS U1870 ( .A(n1122), .B(sign_inv_out[30]), .Y(n1106) );
NAND3X2TS U1871 ( .A(n1107), .B(n1106), .C(n1108), .Y(n528) );
NAND3X2TS U1872 ( .A(n1115), .B(n1113), .C(n1114), .Y(n490) );
INVX2TS U1873 ( .A(n1130), .Y(n1126) );
NOR2X2TS U1874 ( .A(n1126), .B(n1587), .Y(beg_add_subt) );
NOR2X1TS U1875 ( .A(n1330), .B(ack_cordic), .Y(net14400) );
INVX2TS U1876 ( .A(beg_add_subt), .Y(n1128) );
NAND2X1TS U1877 ( .A(n1511), .B(beg_fsm_cordic), .Y(n1131) );
INVX2TS U1878 ( .A(operation), .Y(n1134) );
NAND2X1TS U1879 ( .A(n1006), .B(d_ff_Yn[29]), .Y(n1137) );
NAND3X2TS U1880 ( .A(n1137), .B(n1136), .C(n1135), .Y(n530) );
MXI2X2TS U1881 ( .A(n1993), .B(n1992), .S0(n905), .Y(n1466) );
NAND3X2TS U1882 ( .A(n1140), .B(n1139), .C(n1138), .Y(n548) );
NOR2X8TS U1883 ( .A(net13933), .B(net13667), .Y(n1524) );
NAND2X4TS U1884 ( .A(n1142), .B(net14457), .Y(net5805) );
NOR2X4TS U1885 ( .A(net13950), .B(net13670), .Y(n1145) );
NOR2X4TS U1886 ( .A(n1145), .B(net13805), .Y(n1481) );
NAND2X1TS U1887 ( .A(n1147), .B(net14404), .Y(n1148) );
NAND4BX2TS U1888 ( .AN(n820), .B(n1149), .C(net14367), .D(n1148), .Y(n730)
);
NAND3X2TS U1889 ( .A(n1150), .B(n1151), .C(n1152), .Y(n534) );
INVX16TS U1890 ( .A(net14189), .Y(net6643) );
NAND2X1TS U1891 ( .A(n1498), .B(d_ff_Zn[18]), .Y(n1160) );
INVX8TS U1892 ( .A(n1052), .Y(n1379) );
NAND3X2TS U1893 ( .A(n1160), .B(n1159), .C(n1158), .Y(n478) );
NAND2X1TS U1894 ( .A(n1498), .B(d_ff_Zn[17]), .Y(n1163) );
NAND3X2TS U1895 ( .A(n1163), .B(n1162), .C(n1161), .Y(n479) );
NAND2X1TS U1896 ( .A(n1498), .B(d_ff_Zn[16]), .Y(n1166) );
NAND3X2TS U1897 ( .A(n1166), .B(n1165), .C(n1164), .Y(n480) );
NAND3X2TS U1898 ( .A(n1169), .B(n1167), .C(n1168), .Y(n477) );
INVX2TS U1899 ( .A(n1203), .Y(n2123) );
INVX2TS U1900 ( .A(d_ff2_X[28]), .Y(n1278) );
NOR2X8TS U1901 ( .A(n1723), .B(net13805), .Y(n1520) );
NAND2X2TS U1902 ( .A(n1184), .B(net13951), .Y(n1185) );
NAND2X4TS U1903 ( .A(n2157), .B(n934), .Y(n1189) );
NOR2X8TS U1904 ( .A(n1410), .B(n1190), .Y(n1386) );
NAND2X8TS U1905 ( .A(n1191), .B(n1387), .Y(n1725) );
OAI21X4TS U1906 ( .A0(n1193), .A1(net14851), .B0(n1192), .Y(n406) );
NAND2X1TS U1907 ( .A(n1079), .B(d_ff_Zn[1]), .Y(n1196) );
NAND3X2TS U1908 ( .A(n1195), .B(n1196), .C(n1194), .Y(n495) );
NAND2X1TS U1909 ( .A(n1121), .B(d_ff_Yn[24]), .Y(n1199) );
NAND2X1TS U1910 ( .A(n1121), .B(d_ff_Yn[22]), .Y(n1202) );
NAND3X2TS U1911 ( .A(n1202), .B(n1201), .C(n1200), .Y(n544) );
NAND3X2TS U1912 ( .A(n1204), .B(n1205), .C(n1206), .Y(n532) );
NAND3X2TS U1913 ( .A(n1209), .B(n1208), .C(n1207), .Y(n568) );
NAND2X1TS U1914 ( .A(n1122), .B(sign_inv_out[9]), .Y(n1212) );
NAND3X2TS U1915 ( .A(n1213), .B(n1212), .C(n1211), .Y(n570) );
NAND2X1TS U1916 ( .A(n1122), .B(sign_inv_out[7]), .Y(n1218) );
NAND3X2TS U1917 ( .A(n1219), .B(n1218), .C(n1217), .Y(n574) );
NAND3X2TS U1918 ( .A(n1220), .B(n1221), .C(n1222), .Y(n576) );
NAND2X1TS U1919 ( .A(n1122), .B(sign_inv_out[5]), .Y(n1224) );
NAND3X2TS U1920 ( .A(n1225), .B(n1224), .C(n1223), .Y(n578) );
NAND2X1TS U1921 ( .A(n1122), .B(sign_inv_out[4]), .Y(n1227) );
NAND3X2TS U1922 ( .A(n1228), .B(n1227), .C(n1226), .Y(n580) );
NAND2X1TS U1923 ( .A(n1122), .B(sign_inv_out[3]), .Y(n1233) );
NAND3X2TS U1924 ( .A(n1233), .B(n1232), .C(n1231), .Y(n582) );
NAND3X2TS U1925 ( .A(n1236), .B(n1235), .C(n1234), .Y(n542) );
NAND3X2TS U1926 ( .A(n1237), .B(n1238), .C(n1239), .Y(n584) );
NAND3X2TS U1927 ( .A(n1241), .B(n1242), .C(n1240), .Y(n546) );
NAND2X1TS U1928 ( .A(n1210), .B(sign_inv_out[1]), .Y(n1244) );
MXI2X2TS U1929 ( .A(n2015), .B(n2014), .S0(n812), .Y(n1441) );
NAND3X2TS U1930 ( .A(n1247), .B(n1246), .C(n1245), .Y(n550) );
NAND2X1TS U1931 ( .A(n1210), .B(sign_inv_out[0]), .Y(n1249) );
NAND3X2TS U1932 ( .A(n1252), .B(n1251), .C(n1250), .Y(n554) );
NAND2X1TS U1933 ( .A(n1006), .B(d_ff_Yn[16]), .Y(n1255) );
NAND3X2TS U1934 ( .A(n1255), .B(n1254), .C(n1253), .Y(n556) );
NAND3X2TS U1935 ( .A(n1258), .B(n1257), .C(n1256), .Y(n558) );
NAND3X2TS U1936 ( .A(n1261), .B(n1260), .C(n1259), .Y(n560) );
NAND3X2TS U1937 ( .A(n1264), .B(n1263), .C(n1262), .Y(n562) );
NAND3X2TS U1938 ( .A(n1267), .B(n1266), .C(n1265), .Y(n564) );
NAND3X2TS U1939 ( .A(n1270), .B(n1269), .C(n1268), .Y(n566) );
NAND3X2TS U1940 ( .A(n1274), .B(n1273), .C(n1272), .Y(n536) );
NOR2X8TS U1941 ( .A(n1276), .B(n1275), .Y(n1722) );
NAND3X1TS U1942 ( .A(n1948), .B(n1947), .C(n1946), .Y(n1604) );
OAI22X2TS U1943 ( .A0(n1281), .A1(n1280), .B0(net14072), .B1(n1604), .Y(
n2125) );
NOR2X2TS U1944 ( .A(net13653), .B(net13673), .Y(n1282) );
NAND2X4TS U1945 ( .A(net14072), .B(n1282), .Y(n2106) );
NAND2X1TS U1946 ( .A(net13667), .B(d_ff3_LUT_out[6]), .Y(n1285) );
NAND4X2TS U1947 ( .A(n1286), .B(n2106), .C(n1285), .D(n1290), .Y(n518) );
NOR2X6TS U1948 ( .A(n823), .B(n2160), .Y(n1504) );
OR2X4TS U1949 ( .A(d_ff2_Y[27]), .B(d_ff2_Y[28]), .Y(n1287) );
NOR2X8TS U1950 ( .A(n1504), .B(n1287), .Y(n1724) );
NOR2X2TS U1951 ( .A(n1504), .B(d_ff2_Y[27]), .Y(n1501) );
NAND3X1TS U1952 ( .A(n1951), .B(n1950), .C(n1949), .Y(n1605) );
NOR2X8TS U1953 ( .A(net13667), .B(net13673), .Y(n1721) );
OAI2BB1X4TS U1954 ( .A0N(n1807), .A1N(n957), .B0(n1300), .Y(n1303) );
INVX16TS U1955 ( .A(net14189), .Y(net6644) );
OAI2BB1X2TS U1956 ( .A0N(d_ff2_Y[19]), .A1N(n1051), .B0(n1306), .Y(n425) );
OAI2BB1X2TS U1957 ( .A0N(d_ff2_Y[15]), .A1N(n1051), .B0(n1308), .Y(n433) );
NAND2X2TS U1958 ( .A(n1706), .B(n1543), .Y(n1316) );
NAND3X2TS U1959 ( .A(n1318), .B(n1317), .C(n1319), .Y(n494) );
NAND2X1TS U1960 ( .A(n1079), .B(d_ff_Zn[3]), .Y(n1325) );
NAND3X2TS U1961 ( .A(n1324), .B(n1323), .C(n1325), .Y(n493) );
NAND3X2TS U1962 ( .A(n1327), .B(n1328), .C(n1326), .Y(n496) );
NAND2X8TS U1963 ( .A(n1514), .B(n1334), .Y(n2171) );
NOR2X2TS U1964 ( .A(net13816), .B(net13896), .Y(n1335) );
NAND2X1TS U1965 ( .A(n1498), .B(d_ff_Zn[14]), .Y(n1343) );
NAND3X2TS U1966 ( .A(n1343), .B(n1342), .C(n1341), .Y(n482) );
NAND3X2TS U1967 ( .A(n1345), .B(n1344), .C(n1346), .Y(n476) );
NAND2X1TS U1968 ( .A(n1498), .B(d_ff_Zn[15]), .Y(n1349) );
NAND3X2TS U1969 ( .A(n1349), .B(n1348), .C(n1347), .Y(n481) );
NAND2X1TS U1970 ( .A(n1050), .B(d_ff2_Z[22]), .Y(n1352) );
NAND2X1TS U1971 ( .A(n1050), .B(d_ff2_Z[23]), .Y(n1355) );
NAND2X1TS U1972 ( .A(n1050), .B(d_ff2_Z[27]), .Y(n1358) );
MXI2X2TS U1973 ( .A(n853), .B(n1922), .S0(n888), .Y(n1542) );
NAND2X2TS U1974 ( .A(n975), .B(d_ff2_Z[25]), .Y(n1359) );
NAND2X2TS U1975 ( .A(n992), .B(d_ff2_Z[24]), .Y(n1362) );
NAND2X2TS U1976 ( .A(n992), .B(d_ff2_Z[26]), .Y(n1366) );
NAND2X1TS U1977 ( .A(n1079), .B(d_ff_Zn[10]), .Y(n1377) );
NAND3X2TS U1978 ( .A(n1377), .B(n1375), .C(n1376), .Y(n486) );
NAND2X1TS U1979 ( .A(n1498), .B(d_ff_Zn[11]), .Y(n1382) );
NAND3X2TS U1980 ( .A(n1382), .B(n1381), .C(n1380), .Y(n485) );
NOR2X4TS U1981 ( .A(n1384), .B(net14072), .Y(n729) );
INVX2TS U1982 ( .A(n1411), .Y(n1385) );
NAND2X2TS U1983 ( .A(n1385), .B(n1387), .Y(n1405) );
INVX2TS U1984 ( .A(n1386), .Y(n1388) );
NAND2X4TS U1985 ( .A(n1388), .B(n1387), .Y(n1404) );
NAND3X2TS U1986 ( .A(n1392), .B(n1391), .C(n1390), .Y(n2127) );
XOR2X4TS U1987 ( .A(n939), .B(n1395), .Y(n1397) );
OAI21X4TS U1988 ( .A0(n1397), .A1(net14851), .B0(n1396), .Y(n342) );
NAND2X1TS U1989 ( .A(n1528), .B(d_ff2_Y[30]), .Y(n1400) );
MXI2X4TS U1990 ( .A(sel_mux_2_reg[1]), .B(n1416), .S0(net13913), .Y(n1417)
);
MXI2X4TS U1991 ( .A(n1418), .B(d_ff2_X[30]), .S0(n1526), .Y(n1419) );
CLKINVX3TS U1992 ( .A(n1508), .Y(n2051) );
CLKINVX3TS U1993 ( .A(n1012), .Y(n2053) );
CLKINVX3TS U1994 ( .A(n1422), .Y(n2050) );
CLKINVX3TS U1995 ( .A(n981), .Y(n2054) );
INVX2TS U1996 ( .A(n999), .Y(n2055) );
CLKINVX3TS U1997 ( .A(n999), .Y(n2058) );
CLKINVX3TS U1998 ( .A(n988), .Y(n2057) );
INVX2TS U1999 ( .A(n981), .Y(n2037) );
CLKINVX3TS U2000 ( .A(n1422), .Y(n2052) );
CLKINVX3TS U2001 ( .A(n1422), .Y(n2049) );
CLKINVX3TS U2002 ( .A(n1012), .Y(n2035) );
CLKBUFX3TS U2003 ( .A(n2043), .Y(n1907) );
CLKINVX3TS U2004 ( .A(n1508), .Y(n2040) );
CLKBUFX3TS U2005 ( .A(n2043), .Y(n1908) );
CLKINVX3TS U2006 ( .A(n1508), .Y(n2041) );
AOI22X1TS U2007 ( .A0(n1591), .A1(net13674), .B0(n830), .B1(
d_ff3_sh_y_out[1]), .Y(n1424) );
OAI21X1TS U2008 ( .A0(n2061), .A1(n1584), .B0(n1424), .Y(add_subt_dataB[1])
);
OAI21X1TS U2009 ( .A0(n2060), .A1(n1584), .B0(n1425), .Y(add_subt_dataB[0])
);
NAND2X2TS U2010 ( .A(n1688), .B(d_ff3_sh_x_out[26]), .Y(n1428) );
NAND2X1TS U2011 ( .A(n1695), .B(n1595), .Y(n1427) );
NAND2X1TS U2012 ( .A(n1696), .B(d_ff3_sh_y_out[26]), .Y(n1426) );
NAND3X1TS U2013 ( .A(n1428), .B(n1427), .C(n1426), .Y(add_subt_dataB[26]) );
OAI2BB1X2TS U2014 ( .A0N(n1940), .A1N(n1939), .B0(n1938), .Y(n343) );
OAI2BB1X2TS U2015 ( .A0N(n1937), .A1N(n1936), .B0(n1935), .Y(n407) );
NAND2X2TS U2016 ( .A(n1688), .B(n343), .Y(n1431) );
NAND2X1TS U2017 ( .A(n1662), .B(n1594), .Y(n1430) );
NAND2X1TS U2018 ( .A(n1690), .B(n407), .Y(n1429) );
NAND3X1TS U2019 ( .A(n1431), .B(n1430), .C(n1429), .Y(add_subt_dataB[25]) );
AOI22X1TS U2020 ( .A0(d_ff3_LUT_out[3]), .A1(n808), .B0(n955), .B1(
d_ff3_sh_y_out[3]), .Y(n1432) );
OAI21X1TS U2021 ( .A0(n2065), .A1(n1584), .B0(n1432), .Y(add_subt_dataB[3])
);
AOI22X1TS U2022 ( .A0(d_ff3_LUT_out[2]), .A1(n808), .B0(n955), .B1(
d_ff3_sh_y_out[2]), .Y(n1433) );
OAI21X1TS U2023 ( .A0(n2063), .A1(n1584), .B0(n1433), .Y(add_subt_dataB[2])
);
NAND3X1TS U2024 ( .A(n1956), .B(n1955), .C(n1954), .Y(n1434) );
NAND2X1TS U2025 ( .A(n1681), .B(d_ff3_sh_y_out[31]), .Y(n1435) );
NAND3X1TS U2026 ( .A(n1976), .B(n1975), .C(n1974), .Y(n1437) );
AOI22X1TS U2027 ( .A0(d_ff2_Z[26]), .A1(n808), .B0(n955), .B1(d_ff2_X[26]),
.Y(n1439) );
OAI21X1TS U2028 ( .A0(n2160), .A1(n1593), .B0(n1439), .Y(add_subt_dataA[26])
);
NOR2X2TS U2029 ( .A(net14971), .B(net15394), .Y(n2105) );
INVX2TS U2030 ( .A(n1442), .Y(n2062) );
NAND2X2TS U2031 ( .A(n980), .B(n1540), .Y(n1454) );
INVX2TS U2032 ( .A(n1456), .Y(n2064) );
INVX2TS U2033 ( .A(n1461), .Y(n2072) );
INVX2TS U2034 ( .A(n1463), .Y(n2113) );
AOI22X1TS U2035 ( .A0(d_ff2_Z[24]), .A1(n808), .B0(n955), .B1(d_ff2_X[24]),
.Y(n1480) );
OAI21X1TS U2036 ( .A0(n2157), .A1(n1593), .B0(n1480), .Y(add_subt_dataA[24])
);
INVX2TS U2037 ( .A(net5805), .Y(net13969) );
AOI2BB2X1TS U2038 ( .B0(n1481), .B1(net13967), .A0N(net14457), .A1N(
d_ff3_LUT_out[21]), .Y(n503) );
MXI2X1TS U2039 ( .A(n1739), .B(net7391), .S0(net13665), .Y(n464) );
MXI2X1TS U2040 ( .A(n1825), .B(n2068), .S0(net13665), .Y(n390) );
MXI2X1TS U2041 ( .A(n1824), .B(n2060), .S0(net13665), .Y(n398) );
MXI2X1TS U2042 ( .A(n1792), .B(n2063), .S0(net13665), .Y(n394) );
MXI2X1TS U2043 ( .A(n1791), .B(n2061), .S0(net13665), .Y(n396) );
MXI2X1TS U2044 ( .A(n1728), .B(n1848), .S0(net13665), .Y(n456) );
XOR2X1TS U2045 ( .A(n934), .B(d_ff2_Y[24]), .Y(n1483) );
MXI2X1TS U2046 ( .A(n1829), .B(n2094), .S0(net14688), .Y(n362) );
MXI2X1TS U2047 ( .A(n1803), .B(n2098), .S0(net14971), .Y(n358) );
MXI2X1TS U2048 ( .A(n1830), .B(n2099), .S0(net14972), .Y(n356) );
MXI2X1TS U2049 ( .A(n1800), .B(n2086), .S0(net13665), .Y(n372) );
MXI2X1TS U2050 ( .A(n1797), .B(n2075), .S0(net14689), .Y(n384) );
MXI2X1TS U2051 ( .A(n1795), .B(n2071), .S0(net14689), .Y(n388) );
MXI2X1TS U2052 ( .A(n1749), .B(n1851), .S0(net14688), .Y(n450) );
MXI2X1TS U2053 ( .A(n1753), .B(n1855), .S0(net14971), .Y(n442) );
MXI2X1TS U2054 ( .A(n1747), .B(n1850), .S0(net14688), .Y(n452) );
MXI2X1TS U2055 ( .A(n1751), .B(n1853), .S0(net14689), .Y(n446) );
MXI2X1TS U2056 ( .A(n1754), .B(n1856), .S0(net14971), .Y(n440) );
MXI2X1TS U2057 ( .A(n1756), .B(n1858), .S0(net14689), .Y(n436) );
MXI2X1TS U2058 ( .A(n1750), .B(n1852), .S0(net14972), .Y(n448) );
MXI2X1TS U2059 ( .A(n1757), .B(n1859), .S0(net14688), .Y(n428) );
MXI2X1TS U2060 ( .A(n1760), .B(n1862), .S0(net14971), .Y(n420) );
AOI22X1TS U2061 ( .A0(n1582), .A1(n467), .B0(n830), .B1(d_ff2_X[29]), .Y(
n1488) );
OAI21X1TS U2062 ( .A0(n1500), .A1(n1593), .B0(n1488), .Y(add_subt_dataA[29])
);
NAND2X2TS U2063 ( .A(n1492), .B(n1491), .Y(n1494) );
INVX4TS U2064 ( .A(n1094), .Y(n1694) );
NAND2X1TS U2065 ( .A(n1694), .B(d_ff2_Y[27]), .Y(n1497) );
NAND2X1TS U2066 ( .A(n1662), .B(d_ff2_Z[27]), .Y(n1496) );
NAND2X1TS U2067 ( .A(n1696), .B(n806), .Y(n1495) );
NAND3X1TS U2068 ( .A(n1497), .B(n1496), .C(n1495), .Y(add_subt_dataA[27]) );
OAI21X1TS U2069 ( .A0(n1013), .A1(n1500), .B0(n1499), .Y(n411) );
INVX2TS U2070 ( .A(result_add_subt[23]), .Y(n2156) );
NAND3X1TS U2071 ( .A(n1725), .B(net14072), .C(n1501), .Y(n2117) );
NAND3BX2TS U2072 ( .AN(n2018), .B(n2017), .C(n2016), .Y(n1608) );
INVX2TS U2073 ( .A(n1608), .Y(n1506) );
XNOR2X4TS U2074 ( .A(n820), .B(net13670), .Y(n1510) );
NOR2X1TS U2075 ( .A(n837), .B(ack_cordic), .Y(n1512) );
NAND2X4TS U2076 ( .A(n1516), .B(net13896), .Y(n1517) );
INVX2TS U2077 ( .A(result_add_subt[30]), .Y(n2167) );
OAI2BB1X2TS U2078 ( .A0N(n1986), .A1N(n1985), .B0(n1984), .Y(n402) );
NAND3X1TS U2079 ( .A(d_ff2_X[28]), .B(n1520), .C(n1526), .Y(n2126) );
NAND2X1TS U2080 ( .A(net15017), .B(d_ff3_LUT_out[7]), .Y(n1521) );
NAND2X1TS U2081 ( .A(net15017), .B(d_ff3_LUT_out[11]), .Y(n1522) );
NAND2X1TS U2082 ( .A(n1983), .B(n1982), .Y(n1525) );
OAI2BB1X2TS U2083 ( .A0N(n1989), .A1N(n1988), .B0(n1525), .Y(n403) );
NAND3X1TS U2084 ( .A(n1527), .B(d_ff2_X[29]), .C(n1526), .Y(n2130) );
INVX2TS U2085 ( .A(d_ff3_LUT_out[27]), .Y(n1532) );
NAND2X1TS U2086 ( .A(net13805), .B(n1532), .Y(n497) );
CLKBUFX3TS U2087 ( .A(n2052), .Y(n1912) );
INVX2TS U2088 ( .A(rst), .Y(n331) );
CLKBUFX3TS U2089 ( .A(n2049), .Y(n1911) );
BUFX3TS U2090 ( .A(n2049), .Y(n1910) );
INVX2TS U2091 ( .A(n1534), .Y(n2163) );
INVX2TS U2092 ( .A(n1535), .Y(n2161) );
INVX2TS U2093 ( .A(n1538), .Y(n2059) );
INVX2TS U2094 ( .A(n1540), .Y(n2166) );
INVX2TS U2095 ( .A(n1541), .Y(n2164) );
INVX2TS U2096 ( .A(n1545), .Y(n2095) );
INVX2TS U2097 ( .A(n1547), .Y(n2078) );
INVX2TS U2098 ( .A(n1548), .Y(n2079) );
INVX2TS U2099 ( .A(n1550), .Y(n2100) );
INVX2TS U2100 ( .A(n1552), .Y(n2066) );
INVX2TS U2101 ( .A(n1556), .Y(n2089) );
INVX2TS U2102 ( .A(n1561), .Y(n2136) );
INVX2TS U2103 ( .A(n1562), .Y(n2132) );
OAI21X1TS U2104 ( .A0(n2085), .A1(n1578), .B0(n1563), .Y(add_subt_dataB[12])
);
AOI22X1TS U2105 ( .A0(n1597), .A1(n1591), .B0(n1696), .B1(d_ff3_sh_y_out[14]), .Y(n1564) );
OAI21X1TS U2106 ( .A0(n2088), .A1(n1578), .B0(n1564), .Y(add_subt_dataB[14])
);
AOI22X1TS U2107 ( .A0(n1596), .A1(n1591), .B0(n955), .B1(d_ff3_sh_y_out[5]),
.Y(n1565) );
OAI21X1TS U2108 ( .A0(n2071), .A1(n1094), .B0(n1565), .Y(add_subt_dataB[5])
);
AOI22X1TS U2109 ( .A0(d_ff3_LUT_out[22]), .A1(n1591), .B0(n1589), .B1(
d_ff3_sh_y_out[22]), .Y(n1566) );
OAI21X1TS U2110 ( .A0(n2097), .A1(n1593), .B0(n1567), .Y(add_subt_dataB[19])
);
AOI22X1TS U2111 ( .A0(d_ff3_LUT_out[21]), .A1(n808), .B0(n830), .B1(
d_ff3_sh_y_out[21]), .Y(n1568) );
OAI21X1TS U2112 ( .A0(n2099), .A1(n1578), .B0(n1568), .Y(add_subt_dataB[21])
);
AOI22X1TS U2113 ( .A0(d_ff3_LUT_out[13]), .A1(n1582), .B0(n1696), .B1(
d_ff3_sh_y_out[13]), .Y(n1569) );
OAI21X1TS U2114 ( .A0(n2086), .A1(n1578), .B0(n1569), .Y(add_subt_dataB[13])
);
AOI22X1TS U2115 ( .A0(d_ff3_LUT_out[16]), .A1(n1591), .B0(n1589), .B1(
d_ff3_sh_y_out[16]), .Y(n1570) );
OAI21X1TS U2116 ( .A0(n1712), .A1(n1578), .B0(n1570), .Y(add_subt_dataB[16])
);
OAI21X1TS U2117 ( .A0(n2094), .A1(n1094), .B0(n1571), .Y(add_subt_dataB[18])
);
NAND3X1TS U2118 ( .A(n2003), .B(n2002), .C(n2001), .Y(n1719) );
AOI22X1TS U2119 ( .A0(n1719), .A1(n1582), .B0(n830), .B1(d_ff3_sh_y_out[24]),
.Y(n1572) );
AOI22X1TS U2120 ( .A0(d_ff3_LUT_out[7]), .A1(n1582), .B0(n955), .B1(
d_ff3_sh_y_out[7]), .Y(n1573) );
OAI21X1TS U2121 ( .A0(n2075), .A1(n1584), .B0(n1573), .Y(add_subt_dataB[7])
);
AOI22X1TS U2122 ( .A0(d_ff3_LUT_out[11]), .A1(n1582), .B0(n1696), .B1(
d_ff3_sh_y_out[11]), .Y(n1574) );
OAI21X1TS U2123 ( .A0(n2084), .A1(n1578), .B0(n1574), .Y(add_subt_dataB[11])
);
AOI22X1TS U2124 ( .A0(d_ff3_LUT_out[10]), .A1(n1591), .B0(n1696), .B1(
d_ff3_sh_y_out[10]), .Y(n1575) );
OAI21X1TS U2125 ( .A0(n2082), .A1(n1578), .B0(n1575), .Y(add_subt_dataB[10])
);
AOI22X1TS U2126 ( .A0(d_ff3_LUT_out[15]), .A1(n1582), .B0(n1589), .B1(
d_ff3_sh_y_out[15]), .Y(n1576) );
OAI21X1TS U2127 ( .A0(n2091), .A1(n1578), .B0(n1576), .Y(add_subt_dataB[15])
);
AOI22X1TS U2128 ( .A0(d_ff3_LUT_out[17]), .A1(n808), .B0(n1690), .B1(
d_ff3_sh_y_out[17]), .Y(n1577) );
OAI21X1TS U2129 ( .A0(n2092), .A1(n1578), .B0(n1577), .Y(add_subt_dataB[17])
);
AOI22X1TS U2130 ( .A0(d_ff3_LUT_out[8]), .A1(n1591), .B0(n955), .B1(
d_ff3_sh_y_out[8]), .Y(n1579) );
OAI21X1TS U2131 ( .A0(n2077), .A1(n1584), .B0(n1579), .Y(add_subt_dataB[8])
);
AOI22X1TS U2132 ( .A0(d_ff3_LUT_out[4]), .A1(n1582), .B0(n955), .B1(
d_ff3_sh_y_out[4]), .Y(n1580) );
OAI21X1TS U2133 ( .A0(n2068), .A1(n1094), .B0(n1580), .Y(add_subt_dataB[4])
);
AOI22X1TS U2134 ( .A0(d_ff3_LUT_out[6]), .A1(n1591), .B0(n955), .B1(
d_ff3_sh_y_out[6]), .Y(n1581) );
OAI21X1TS U2135 ( .A0(n2073), .A1(n1584), .B0(n1581), .Y(add_subt_dataB[6])
);
AOI22X1TS U2136 ( .A0(d_ff3_LUT_out[9]), .A1(n1582), .B0(n1589), .B1(
d_ff3_sh_y_out[9]), .Y(n1583) );
OAI21X1TS U2137 ( .A0(n2080), .A1(n1584), .B0(n1583), .Y(add_subt_dataB[9])
);
NAND2X2TS U2138 ( .A(n1688), .B(n338), .Y(n1586) );
NAND2X1TS U2139 ( .A(n1681), .B(n402), .Y(n1585) );
NAND2X2TS U2140 ( .A(n1586), .B(n1585), .Y(add_subt_dataB[30]) );
NOR2X1TS U2141 ( .A(n1588), .B(n1587), .Y(ready_cordic) );
AOI22X1TS U2142 ( .A0(n808), .A1(d_ff2_Z[28]), .B0(n830), .B1(d_ff2_X[28]),
.Y(n1590) );
OAI21X1TS U2143 ( .A0(n1873), .A1(n1593), .B0(n1590), .Y(add_subt_dataA[28])
);
AOI22X1TS U2144 ( .A0(d_ff2_Z[25]), .A1(n1591), .B0(n955), .B1(d_ff2_X[25]),
.Y(n1592) );
OAI21X1TS U2145 ( .A0(n1866), .A1(n1593), .B0(n1592), .Y(add_subt_dataA[25])
);
NAND2X2TS U2146 ( .A(n1688), .B(d_ff2_Y[1]), .Y(n1600) );
NAND2X1TS U2147 ( .A(n807), .B(d_ff2_Z[1]), .Y(n1599) );
NAND2X1TS U2148 ( .A(n1681), .B(d_ff2_X[1]), .Y(n1598) );
NAND3X1TS U2149 ( .A(n1600), .B(n1599), .C(n1598), .Y(add_subt_dataA[1]) );
NAND2X2TS U2150 ( .A(n1688), .B(d_ff2_Y[0]), .Y(n1603) );
NAND2X1TS U2151 ( .A(n807), .B(d_ff2_Z[0]), .Y(n1602) );
NAND2X1TS U2152 ( .A(n1681), .B(d_ff2_X[0]), .Y(n1601) );
NAND3X1TS U2153 ( .A(n1603), .B(n1602), .C(n1601), .Y(add_subt_dataA[0]) );
NAND2X2TS U2154 ( .A(n1680), .B(d_ff3_LUT_out[27]), .Y(n1613) );
NAND2X2TS U2155 ( .A(n1688), .B(n1604), .Y(n1607) );
NAND2X1TS U2156 ( .A(n1589), .B(n1605), .Y(n1606) );
NAND3X1TS U2157 ( .A(n1613), .B(n1607), .C(n1606), .Y(add_subt_dataB[28]) );
NAND2X2TS U2158 ( .A(n1688), .B(d_ff3_sh_x_out[27]), .Y(n1610) );
NAND2X1TS U2159 ( .A(n1690), .B(n1608), .Y(n1609) );
NAND3X1TS U2160 ( .A(n1613), .B(n1610), .C(n1609), .Y(add_subt_dataB[27]) );
NAND2X1TS U2161 ( .A(n1681), .B(n403), .Y(n1612) );
NAND2X2TS U2162 ( .A(n1688), .B(n339), .Y(n1611) );
NAND3X1TS U2163 ( .A(n1613), .B(n1612), .C(n1611), .Y(add_subt_dataB[29]) );
NAND2X1TS U2164 ( .A(n1679), .B(d_ff2_Y[7]), .Y(n1616) );
NAND2X1TS U2165 ( .A(n1680), .B(d_ff2_Z[7]), .Y(n1615) );
NAND2X1TS U2166 ( .A(n1663), .B(d_ff2_X[7]), .Y(n1614) );
NAND3X1TS U2167 ( .A(n1616), .B(n1615), .C(n1614), .Y(add_subt_dataA[7]) );
INVX8TS U2168 ( .A(n1094), .Y(n1658) );
NAND2X1TS U2169 ( .A(n1658), .B(d_ff2_Y[17]), .Y(n1619) );
NAND2X1TS U2170 ( .A(n1695), .B(d_ff2_Z[17]), .Y(n1618) );
NAND2X1TS U2171 ( .A(n1690), .B(d_ff2_X[17]), .Y(n1617) );
NAND3X1TS U2172 ( .A(n1619), .B(n1618), .C(n1617), .Y(add_subt_dataA[17]) );
NAND2X1TS U2173 ( .A(n1658), .B(d_ff2_Y[16]), .Y(n1622) );
NAND2X1TS U2174 ( .A(n1662), .B(d_ff2_Z[16]), .Y(n1621) );
NAND2X1TS U2175 ( .A(n1696), .B(d_ff2_X[16]), .Y(n1620) );
NAND3X1TS U2176 ( .A(n1622), .B(n1621), .C(n1620), .Y(add_subt_dataA[16]) );
NAND2X1TS U2177 ( .A(n1680), .B(d_ff2_Z[14]), .Y(n1624) );
NAND2X1TS U2178 ( .A(n1663), .B(d_ff2_X[14]), .Y(n1623) );
NAND2X1TS U2179 ( .A(n1679), .B(d_ff2_Y[6]), .Y(n1627) );
NAND2X1TS U2180 ( .A(n807), .B(d_ff2_Z[6]), .Y(n1626) );
NAND2X1TS U2181 ( .A(n1663), .B(d_ff2_X[6]), .Y(n1625) );
NAND3X1TS U2182 ( .A(n1627), .B(n1626), .C(n1625), .Y(add_subt_dataA[6]) );
NAND2X1TS U2183 ( .A(n1658), .B(d_ff2_Y[12]), .Y(n1630) );
NAND2X1TS U2184 ( .A(n1680), .B(d_ff2_Z[12]), .Y(n1629) );
NAND2X1TS U2185 ( .A(n1663), .B(d_ff2_X[12]), .Y(n1628) );
NAND3X1TS U2186 ( .A(n1630), .B(n1629), .C(n1628), .Y(add_subt_dataA[12]) );
NAND2X1TS U2187 ( .A(n1658), .B(d_ff2_Y[19]), .Y(n1633) );
NAND2X1TS U2188 ( .A(n1695), .B(d_ff2_Z[19]), .Y(n1632) );
NAND2X1TS U2189 ( .A(n1589), .B(d_ff2_X[19]), .Y(n1631) );
NAND3X1TS U2190 ( .A(n1633), .B(n1632), .C(n1631), .Y(add_subt_dataA[19]) );
NAND2X1TS U2191 ( .A(n1679), .B(d_ff2_Y[10]), .Y(n1636) );
NAND2X1TS U2192 ( .A(n1695), .B(d_ff2_Z[10]), .Y(n1635) );
NAND2X1TS U2193 ( .A(n1663), .B(d_ff2_X[10]), .Y(n1634) );
NAND3X1TS U2194 ( .A(n1636), .B(n1635), .C(n1634), .Y(add_subt_dataA[10]) );
NAND2X1TS U2195 ( .A(n1658), .B(d_ff2_Y[13]), .Y(n1639) );
NAND2X1TS U2196 ( .A(n1662), .B(d_ff2_Z[13]), .Y(n1638) );
NAND2X1TS U2197 ( .A(n1663), .B(d_ff2_X[13]), .Y(n1637) );
NAND3X1TS U2198 ( .A(n1639), .B(n1638), .C(n1637), .Y(add_subt_dataA[13]) );
NAND2X1TS U2199 ( .A(n1658), .B(d_ff2_Y[20]), .Y(n1642) );
NAND2X1TS U2200 ( .A(n807), .B(d_ff2_Z[20]), .Y(n1641) );
NAND2X1TS U2201 ( .A(n1690), .B(d_ff2_X[20]), .Y(n1640) );
NAND3X1TS U2202 ( .A(n1642), .B(n1641), .C(n1640), .Y(add_subt_dataA[20]) );
NAND2X1TS U2203 ( .A(n1679), .B(d_ff2_Y[9]), .Y(n1645) );
NAND2X1TS U2204 ( .A(n1663), .B(d_ff2_X[9]), .Y(n1643) );
NAND3X1TS U2205 ( .A(n1645), .B(n1644), .C(n1643), .Y(add_subt_dataA[9]) );
NAND2X1TS U2206 ( .A(n807), .B(d_ff2_Z[22]), .Y(n1647) );
NAND2X1TS U2207 ( .A(n1696), .B(d_ff2_X[22]), .Y(n1646) );
NAND3X1TS U2208 ( .A(n1648), .B(n1647), .C(n1646), .Y(add_subt_dataA[22]) );
NAND2X1TS U2209 ( .A(n1679), .B(d_ff2_Y[8]), .Y(n1651) );
NAND2X1TS U2210 ( .A(n1663), .B(d_ff2_X[8]), .Y(n1649) );
NAND3X1TS U2211 ( .A(n1651), .B(n1650), .C(n1649), .Y(add_subt_dataA[8]) );
NAND2X1TS U2212 ( .A(n1658), .B(d_ff2_Y[21]), .Y(n1654) );
NAND2X1TS U2213 ( .A(n1662), .B(d_ff2_Z[21]), .Y(n1653) );
NAND2X1TS U2214 ( .A(n1690), .B(d_ff2_X[21]), .Y(n1652) );
NAND3X1TS U2215 ( .A(n1654), .B(n1653), .C(n1652), .Y(add_subt_dataA[21]) );
NAND2X1TS U2216 ( .A(n1658), .B(d_ff2_Y[15]), .Y(n1657) );
NAND2X1TS U2217 ( .A(n1663), .B(d_ff2_X[15]), .Y(n1655) );
NAND3X1TS U2218 ( .A(n1657), .B(n1656), .C(n1655), .Y(add_subt_dataA[15]) );
NAND2X1TS U2219 ( .A(n1658), .B(d_ff2_Y[18]), .Y(n1661) );
NAND2X1TS U2220 ( .A(n807), .B(d_ff2_Z[18]), .Y(n1660) );
NAND2X1TS U2221 ( .A(n1690), .B(d_ff2_X[18]), .Y(n1659) );
NAND3X1TS U2222 ( .A(n1661), .B(n1660), .C(n1659), .Y(add_subt_dataA[18]) );
NAND2X1TS U2223 ( .A(n1679), .B(d_ff2_Y[11]), .Y(n1666) );
NAND2X1TS U2224 ( .A(n1663), .B(d_ff2_X[11]), .Y(n1664) );
NAND3X1TS U2225 ( .A(n1666), .B(n1665), .C(n1664), .Y(add_subt_dataA[11]) );
NAND2X1TS U2226 ( .A(n1679), .B(d_ff2_Y[5]), .Y(n1669) );
NAND2X1TS U2227 ( .A(n807), .B(d_ff2_Z[5]), .Y(n1668) );
NAND2X1TS U2228 ( .A(n1681), .B(d_ff2_X[5]), .Y(n1667) );
NAND3X1TS U2229 ( .A(n1669), .B(n1668), .C(n1667), .Y(add_subt_dataA[5]) );
NAND2X1TS U2230 ( .A(n1679), .B(d_ff2_Y[3]), .Y(n1672) );
NAND2X1TS U2231 ( .A(n1662), .B(d_ff2_Z[3]), .Y(n1671) );
NAND2X1TS U2232 ( .A(n1681), .B(d_ff2_X[3]), .Y(n1670) );
NAND3X1TS U2233 ( .A(n1672), .B(n1671), .C(n1670), .Y(add_subt_dataA[3]) );
NAND2X1TS U2234 ( .A(n1679), .B(d_ff2_Y[2]), .Y(n1675) );
NAND2X1TS U2235 ( .A(n807), .B(d_ff2_Z[2]), .Y(n1674) );
NAND2X1TS U2236 ( .A(n1681), .B(d_ff2_X[2]), .Y(n1673) );
NAND3X1TS U2237 ( .A(n1675), .B(n1674), .C(n1673), .Y(add_subt_dataA[2]) );
NAND2X1TS U2238 ( .A(n1694), .B(d_ff2_Y[31]), .Y(n1678) );
NAND2X1TS U2239 ( .A(n807), .B(d_ff2_Z[31]), .Y(n1677) );
NAND2X1TS U2240 ( .A(n1681), .B(d_ff2_X[31]), .Y(n1676) );
NAND3X1TS U2241 ( .A(n1678), .B(n1677), .C(n1676), .Y(add_subt_dataA[31]) );
NAND2X1TS U2242 ( .A(n1679), .B(d_ff2_Y[4]), .Y(n1684) );
NAND2X1TS U2243 ( .A(n1695), .B(d_ff2_Z[4]), .Y(n1683) );
NAND2X1TS U2244 ( .A(n1681), .B(d_ff2_X[4]), .Y(n1682) );
NAND3X1TS U2245 ( .A(n1684), .B(n1683), .C(n1682), .Y(add_subt_dataA[4]) );
NAND2X1TS U2246 ( .A(n1694), .B(d_ff2_Y[30]), .Y(n1687) );
NAND2X1TS U2247 ( .A(n1662), .B(d_ff2_Z[30]), .Y(n1686) );
NAND3X1TS U2248 ( .A(n1687), .B(n1686), .C(n1685), .Y(add_subt_dataA[30]) );
NAND2X2TS U2249 ( .A(n1688), .B(n1716), .Y(n1693) );
NAND2X1TS U2250 ( .A(n1696), .B(n1710), .Y(n1691) );
NAND3X1TS U2251 ( .A(n1693), .B(n1692), .C(n1691), .Y(add_subt_dataB[23]) );
NAND2X1TS U2252 ( .A(n1694), .B(d_ff2_Y[23]), .Y(n1699) );
NAND2X1TS U2253 ( .A(n1695), .B(d_ff2_Z[23]), .Y(n1698) );
NAND2X1TS U2254 ( .A(n1696), .B(d_ff2_X[23]), .Y(n1697) );
NAND3X1TS U2255 ( .A(n1699), .B(n1698), .C(n1697), .Y(add_subt_dataA[23]) );
MXI2X1TS U2256 ( .A(n1738), .B(n1874), .S0(n1009), .Y(n527) );
MXI2X1TS U2257 ( .A(n1778), .B(n1896), .S0(n1009), .Y(n549) );
MXI2X1TS U2258 ( .A(n1772), .B(n1889), .S0(n1008), .Y(n563) );
MXI2X1TS U2259 ( .A(n1771), .B(n1888), .S0(n1702), .Y(n565) );
MXI2X1TS U2260 ( .A(n1770), .B(n1887), .S0(n1009), .Y(n567) );
MXI2X1TS U2261 ( .A(n1774), .B(n1891), .S0(n1008), .Y(n559) );
MXI2X1TS U2262 ( .A(n1773), .B(n1890), .S0(n1702), .Y(n561) );
INVX2TS U2263 ( .A(sign_inv_out[18]), .Y(n1701) );
MXI2X1TS U2264 ( .A(n1701), .B(n1895), .S0(n1009), .Y(n551) );
INVX2TS U2265 ( .A(shift_region_flag[1]), .Y(n1703) );
AOI22X1TS U2266 ( .A0(n1078), .A1(n959), .B0(n1736), .B1(n1379), .Y(n371) );
AOI22X1TS U2267 ( .A0(n1078), .A1(n832), .B0(n1737), .B1(n1379), .Y(n367) );
AOI22X1TS U2268 ( .A0(n1046), .A1(n958), .B0(n1795), .B1(n1379), .Y(n389) );
AOI22X1TS U2269 ( .A0(n1078), .A1(n942), .B0(n1800), .B1(n1379), .Y(n373) );
INVX2TS U2270 ( .A(n1709), .Y(n1711) );
NAND2X1TS U2271 ( .A(net13672), .B(net13653), .Y(n2115) );
MXI2X1TS U2272 ( .A(n1737), .B(n1712), .S0(net14972), .Y(n366) );
INVX2TS U2273 ( .A(d_ff3_sh_y_out[16]), .Y(n1713) );
MXI2X1TS U2274 ( .A(n1731), .B(n1713), .S0(net14688), .Y(n430) );
INVX2TS U2275 ( .A(n1715), .Y(n1717) );
MXI2X1TS U2276 ( .A(n1717), .B(n1716), .S0(net13657), .Y(n2103) );
NAND3X1TS U2277 ( .A(n939), .B(net14325), .C(n1722), .Y(n2124) );
NAND3X1TS U2278 ( .A(n1725), .B(net13951), .C(n956), .Y(n2120) );
initial $sdf_annotate("CORDIC_Arch2v1_ASIC_fpu_syn_constraints_clk1.tcl_syn.sdf");
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR4BB_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__OR4BB_BEHAVIORAL_PP_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__or4bb (
X ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , D_N, C_N );
or or0 (or0_out_X , B, A, nand0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR4BB_BEHAVIORAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR2_FUNCTIONAL_V
`define SKY130_FD_SC_MS__OR2_FUNCTIONAL_V
/**
* or2: 2-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__or2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR2_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FAH_1_V
`define SKY130_FD_SC_MS__FAH_1_V
/**
* fah: Full adder.
*
* Verilog wrapper for fah with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__fah.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__fah_1 (
COUT,
SUM ,
A ,
B ,
CI ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__fah base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__fah_1 (
COUT,
SUM ,
A ,
B ,
CI
);
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__fah base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__FAH_1_V
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pci_pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pci_pll (
areset,
inclk0,
c0,
locked);
input areset;
input inclk0;
output c0;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire [6:0] sub_wire1;
wire [0:0] sub_wire5 = 1'h0;
wire locked = sub_wire0;
wire [0:0] sub_wire2 = sub_wire1[0:0];
wire c0 = sub_wire2;
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire4),
.locked (sub_wire0),
.clk (sub_wire1),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 15151,
altpll_component.intended_device_family = "Arria II GX",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pci_pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "Left_Right",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_fbout = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clk6 = "PORT_UNUSED",
altpll_component.port_clk7 = "PORT_UNUSED",
altpll_component.port_clk8 = "PORT_UNUSED",
altpll_component.port_clk9 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.using_fbmimicbidir_port = "OFF",
altpll_component.width_clock = 7;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "3"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "66.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "66.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pci_pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15151"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "Left_Right"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk6 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk7 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk8 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk9 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "7"
// Retrieval info: USED_PORT: @clk 0 0 7 0 OUTPUT_CLK_EXT VCC "@clk[6..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pci_pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pci_pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pci_pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pci_pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pci_pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pci_pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pci_pll_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: riffa_wrapper_kc705.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: RIFFA wrapper for the KC705 (REV C) Development board.
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "trellis.vh"
`include "riffa.vh"
`include "xilinx.vh"
`include "ultrascale.vh"
`include "functions.vh"
`timescale 1ps / 1ps
module riffa_wrapper_kc705
#(// Number of RIFFA Channels
parameter C_NUM_CHNL = 1,
// Bit-Width from Vivado IP Generator
parameter C_PCI_DATA_WIDTH = 128,
// 4-Byte Name for this FPGA
parameter C_MAX_PAYLOAD_BYTES = 256,
parameter C_LOG_NUM_TAGS = 5,
parameter C_FPGA_ID = "K705")
(// Interface: Xilinx RX
input [C_PCI_DATA_WIDTH-1:0] M_AXIS_RX_TDATA,
input [(C_PCI_DATA_WIDTH/8)-1:0] M_AXIS_RX_TKEEP,
input M_AXIS_RX_TLAST,
input M_AXIS_RX_TVALID,
output M_AXIS_RX_TREADY,
input [`SIG_XIL_RX_TUSER_W-1:0] M_AXIS_RX_TUSER,
output RX_NP_OK,
output RX_NP_REQ,
// Interface: Xilinx TX
output [C_PCI_DATA_WIDTH-1:0] S_AXIS_TX_TDATA,
output [(C_PCI_DATA_WIDTH/8)-1:0] S_AXIS_TX_TKEEP,
output S_AXIS_TX_TLAST,
output S_AXIS_TX_TVALID,
input S_AXIS_TX_TREADY,
output [`SIG_XIL_TX_TUSER_W-1:0] S_AXIS_TX_TUSER,
output TX_CFG_GNT,
// Interface: Xilinx Configuration
input [`SIG_BUSID_W-1:0] CFG_BUS_NUMBER,
input [`SIG_DEVID_W-1:0] CFG_DEVICE_NUMBER,
input [`SIG_FNID_W-1:0] CFG_FUNCTION_NUMBER,
input [`SIG_CFGREG_W-1:0] CFG_COMMAND,
input [`SIG_CFGREG_W-1:0] CFG_DCOMMAND,
input [`SIG_CFGREG_W-1:0] CFG_LSTATUS,
input [`SIG_CFGREG_W-1:0] CFG_LCOMMAND,
// Interface: Xilinx Flow Control
input [`SIG_FC_CPLD_W-1:0] FC_CPLD,
input [`SIG_FC_CPLH_W-1:0] FC_CPLH,
output [`SIG_FC_SEL_W-1:0] FC_SEL,
// Interface: Xilinx Interrupt
input CFG_INTERRUPT_MSIEN,
input CFG_INTERRUPT_RDY,
output CFG_INTERRUPT,
input USER_CLK,
input USER_RESET,
// RIFFA Interface Signals
output RST_OUT,
input [C_NUM_CHNL-1:0] CHNL_RX_CLK, // Channel read clock
output [C_NUM_CHNL-1:0] CHNL_RX, // Channel read receive signal
input [C_NUM_CHNL-1:0] CHNL_RX_ACK, // Channel read received signal
output [C_NUM_CHNL-1:0] CHNL_RX_LAST, // Channel last read
output [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_RX_LEN, // Channel read length
output [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_RX_OFF, // Channel read offset
output [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_RX_DATA, // Channel read data
output [C_NUM_CHNL-1:0] CHNL_RX_DATA_VALID, // Channel read data valid
input [C_NUM_CHNL-1:0] CHNL_RX_DATA_REN, // Channel read data has been recieved
input [C_NUM_CHNL-1:0] CHNL_TX_CLK, // Channel write clock
input [C_NUM_CHNL-1:0] CHNL_TX, // Channel write receive signal
output [C_NUM_CHNL-1:0] CHNL_TX_ACK, // Channel write acknowledgement signal
input [C_NUM_CHNL-1:0] CHNL_TX_LAST, // Channel last write
input [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_TX_OFF, // Channel write offset
input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_TX_DATA, // Channel write data
input [C_NUM_CHNL-1:0] CHNL_TX_DATA_VALID, // Channel write data valid
output [C_NUM_CHNL-1:0] CHNL_TX_DATA_REN); // Channel write data has been recieved
localparam C_FPGA_NAME = "REGT"; // This is not yet exposed in the driver
localparam C_MAX_READ_REQ_BYTES = C_MAX_PAYLOAD_BYTES * 2;
// ALTERA, XILINX or ULTRASCALE
localparam C_VENDOR = "XILINX";
localparam C_KEEP_WIDTH = C_PCI_DATA_WIDTH / 32;
localparam C_PIPELINE_OUTPUT = 1;
localparam C_PIPELINE_INPUT = 1;
localparam C_DEPTH_PACKETS = 4;
wire clk;
wire rst_in;
wire done_txc_rst;
wire done_txr_rst;
wire done_rxr_rst;
wire done_rxc_rst;
// Interface: RXC Engine
wire [C_PCI_DATA_WIDTH-1:0] rxc_data;
wire rxc_data_valid;
wire rxc_data_start_flag;
wire [(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_word_enable;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_start_offset;
wire [`SIG_FBE_W-1:0] rxc_meta_fdwbe;
wire rxc_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_end_offset;
wire [`SIG_LBE_W-1:0] rxc_meta_ldwbe;
wire [`SIG_TAG_W-1:0] rxc_meta_tag;
wire [`SIG_LOWADDR_W-1:0] rxc_meta_addr;
wire [`SIG_TYPE_W-1:0] rxc_meta_type;
wire [`SIG_LEN_W-1:0] rxc_meta_length;
wire [`SIG_BYTECNT_W-1:0] rxc_meta_bytes_remaining;
wire [`SIG_CPLID_W-1:0] rxc_meta_completer_id;
wire rxc_meta_ep;
// Interface: RXR Engine
wire [C_PCI_DATA_WIDTH-1:0] rxr_data;
wire rxr_data_valid;
wire [(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_word_enable;
wire rxr_data_start_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_start_offset;
wire [`SIG_FBE_W-1:0] rxr_meta_fdwbe;
wire rxr_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_end_offset;
wire [`SIG_LBE_W-1:0] rxr_meta_ldwbe;
wire [`SIG_TC_W-1:0] rxr_meta_tc;
wire [`SIG_ATTR_W-1:0] rxr_meta_attr;
wire [`SIG_TAG_W-1:0] rxr_meta_tag;
wire [`SIG_TYPE_W-1:0] rxr_meta_type;
wire [`SIG_ADDR_W-1:0] rxr_meta_addr;
wire [`SIG_BARDECODE_W-1:0] rxr_meta_bar_decoded;
wire [`SIG_REQID_W-1:0] rxr_meta_requester_id;
wire [`SIG_LEN_W-1:0] rxr_meta_length;
wire rxr_meta_ep;
// interface: TXC Engine
wire txc_data_valid;
wire [C_PCI_DATA_WIDTH-1:0] txc_data;
wire txc_data_start_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_start_offset;
wire txc_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_end_offset;
wire txc_data_ready;
wire txc_meta_valid;
wire [`SIG_FBE_W-1:0] txc_meta_fdwbe;
wire [`SIG_LBE_W-1:0] txc_meta_ldwbe;
wire [`SIG_LOWADDR_W-1:0] txc_meta_addr;
wire [`SIG_TYPE_W-1:0] txc_meta_type;
wire [`SIG_LEN_W-1:0] txc_meta_length;
wire [`SIG_BYTECNT_W-1:0] txc_meta_byte_count;
wire [`SIG_TAG_W-1:0] txc_meta_tag;
wire [`SIG_REQID_W-1:0] txc_meta_requester_id;
wire [`SIG_TC_W-1:0] txc_meta_tc;
wire [`SIG_ATTR_W-1:0] txc_meta_attr;
wire txc_meta_ep;
wire txc_meta_ready;
wire txc_sent;
// Interface: TXR Engine
wire txr_data_valid;
wire [C_PCI_DATA_WIDTH-1:0] txr_data;
wire txr_data_start_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_start_offset;
wire txr_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_end_offset;
wire txr_data_ready;
wire txr_meta_valid;
wire [`SIG_FBE_W-1:0] txr_meta_fdwbe;
wire [`SIG_LBE_W-1:0] txr_meta_ldwbe;
wire [`SIG_ADDR_W-1:0] txr_meta_addr;
wire [`SIG_LEN_W-1:0] txr_meta_length;
wire [`SIG_TAG_W-1:0] txr_meta_tag;
wire [`SIG_TC_W-1:0] txr_meta_tc;
wire [`SIG_ATTR_W-1:0] txr_meta_attr;
wire [`SIG_TYPE_W-1:0] txr_meta_type;
wire txr_meta_ep;
wire txr_meta_ready;
wire txr_sent;
// Classic Interface Wires
wire rx_tlp_ready;
wire [C_PCI_DATA_WIDTH-1:0] rx_tlp;
wire rx_tlp_end_flag;
wire [`SIG_OFFSET_W-1:0] rx_tlp_end_offset;
wire rx_tlp_start_flag;
wire [`SIG_OFFSET_W-1:0] rx_tlp_start_offset;
wire rx_tlp_valid;
wire [`SIG_BARDECODE_W-1:0] rx_tlp_bar_decode;
wire tx_tlp_ready;
wire [C_PCI_DATA_WIDTH-1:0] tx_tlp;
wire tx_tlp_end_flag;
wire [`SIG_OFFSET_W-1:0] tx_tlp_end_offset;
wire tx_tlp_start_flag;
wire [`SIG_OFFSET_W-1:0] tx_tlp_start_offset;
wire tx_tlp_valid;
// Unconnected Wires (Used in ultrascale interface)
// Interface: RQ (TXC)
wire s_axis_rq_tlast_nc;
wire [C_PCI_DATA_WIDTH-1:0] s_axis_rq_tdata_nc;
wire [`SIG_RQ_TUSER_W-1:0] s_axis_rq_tuser_nc;
wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_rq_tkeep_nc;
wire s_axis_rq_tready_nc = 0;
wire s_axis_rq_tvalid_nc;
// Interface: RC (RXC)
wire [C_PCI_DATA_WIDTH-1:0] m_axis_rc_tdata_nc = 0;
wire [`SIG_RC_TUSER_W-1:0] m_axis_rc_tuser_nc = 0;
wire m_axis_rc_tlast_nc = 0;
wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_rc_tkeep_nc = 0;
wire m_axis_rc_tvalid_nc = 0;
wire m_axis_rc_tready_nc;
// Interface: CQ (RXR)
wire [C_PCI_DATA_WIDTH-1:0] m_axis_cq_tdata_nc = 0;
wire [`SIG_CQ_TUSER_W-1:0] m_axis_cq_tuser_nc = 0;
wire m_axis_cq_tlast_nc = 0;
wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_cq_tkeep_nc = 0;
wire m_axis_cq_tvalid_nc = 0;
wire m_axis_cq_tready_nc = 0;
// Interface: CC (TXC)
wire [C_PCI_DATA_WIDTH-1:0] s_axis_cc_tdata_nc;
wire [`SIG_CC_TUSER_W-1:0] s_axis_cc_tuser_nc;
wire s_axis_cc_tlast_nc;
wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_cc_tkeep_nc;
wire s_axis_cc_tvalid_nc;
wire s_axis_cc_tready_nc = 0;
// Interface: Configuration
wire config_bus_master_enable;
wire [`SIG_CPLID_W-1:0] config_completer_id;
wire config_cpl_boundary_sel;
wire config_interrupt_msienable;
wire [`SIG_LINKRATE_W-1:0] config_link_rate;
wire [`SIG_LINKWIDTH_W-1:0] config_link_width;
wire [`SIG_MAXPAYLOAD_W-1:0] config_max_payload_size;
wire [`SIG_MAXREAD_W-1:0] config_max_read_request_size;
wire [`SIG_FC_CPLD_W-1:0] config_max_cpl_data;
wire [`SIG_FC_CPLH_W-1:0] config_max_cpl_hdr;
wire intr_msi_request;
wire intr_msi_rdy;
genvar chnl;
reg rRxTlpValid;
reg rRxTlpEndFlag;
assign clk = USER_CLK;
assign rst_in = USER_RESET;
translation_xilinx
#(/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH))
trans
(// Outputs
.RX_TLP (rx_tlp[C_PCI_DATA_WIDTH-1:0]),
.RX_TLP_VALID (rx_tlp_valid),
.RX_TLP_START_FLAG (rx_tlp_start_flag),
.RX_TLP_START_OFFSET (rx_tlp_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RX_TLP_END_FLAG (rx_tlp_end_flag),
.RX_TLP_END_OFFSET (rx_tlp_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RX_TLP_BAR_DECODE (rx_tlp_bar_decode[`SIG_BARDECODE_W-1:0]),
.TX_TLP_READY (tx_tlp_ready),
.CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]),
.CONFIG_BUS_MASTER_ENABLE (config_bus_master_enable),
.CONFIG_LINK_WIDTH (config_link_width[`SIG_LINKWIDTH_W-1:0]),
.CONFIG_LINK_RATE (config_link_rate[`SIG_LINKRATE_W-1:0]),
.CONFIG_MAX_READ_REQUEST_SIZE (config_max_read_request_size[`SIG_MAXREAD_W-1:0]),
.CONFIG_MAX_PAYLOAD_SIZE (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]),
.CONFIG_INTERRUPT_MSIENABLE (config_interrupt_msienable),
.CONFIG_CPL_BOUNDARY_SEL (config_cpl_boundary_sel),
.CONFIG_MAX_CPL_DATA (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]),
.CONFIG_MAX_CPL_HDR (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]),
.INTR_MSI_RDY (intr_msi_rdy),
// Inputs
.CLK (clk),
.RST_IN (rst_in),
.RX_TLP_READY (rx_tlp_ready),
.TX_TLP (tx_tlp[C_PCI_DATA_WIDTH-1:0]),
.TX_TLP_VALID (tx_tlp_valid),
.TX_TLP_START_FLAG (tx_tlp_start_flag),
.TX_TLP_START_OFFSET (tx_tlp_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TX_TLP_END_FLAG (tx_tlp_end_flag),
.TX_TLP_END_OFFSET (tx_tlp_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.INTR_MSI_REQUEST (intr_msi_request),
/*AUTOINST*/
// Outputs
.M_AXIS_RX_TREADY (M_AXIS_RX_TREADY),
.RX_NP_OK (RX_NP_OK),
.RX_NP_REQ (RX_NP_REQ),
.S_AXIS_TX_TDATA (S_AXIS_TX_TDATA[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_TX_TKEEP (S_AXIS_TX_TKEEP[(C_PCI_DATA_WIDTH/8)-1:0]),
.S_AXIS_TX_TLAST (S_AXIS_TX_TLAST),
.S_AXIS_TX_TVALID (S_AXIS_TX_TVALID),
.S_AXIS_TX_TUSER (S_AXIS_TX_TUSER[`SIG_XIL_TX_TUSER_W-1:0]),
.TX_CFG_GNT (TX_CFG_GNT),
.FC_SEL (FC_SEL[`SIG_FC_SEL_W-1:0]),
.CFG_INTERRUPT (CFG_INTERRUPT),
// Inputs
.M_AXIS_RX_TDATA (M_AXIS_RX_TDATA[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_RX_TKEEP (M_AXIS_RX_TKEEP[(C_PCI_DATA_WIDTH/8)-1:0]),
.M_AXIS_RX_TLAST (M_AXIS_RX_TLAST),
.M_AXIS_RX_TVALID (M_AXIS_RX_TVALID),
.M_AXIS_RX_TUSER (M_AXIS_RX_TUSER[`SIG_XIL_RX_TUSER_W-1:0]),
.S_AXIS_TX_TREADY (S_AXIS_TX_TREADY),
.CFG_BUS_NUMBER (CFG_BUS_NUMBER[`SIG_BUSID_W-1:0]),
.CFG_DEVICE_NUMBER (CFG_DEVICE_NUMBER[`SIG_DEVID_W-1:0]),
.CFG_FUNCTION_NUMBER (CFG_FUNCTION_NUMBER[`SIG_FNID_W-1:0]),
.CFG_COMMAND (CFG_COMMAND[`SIG_CFGREG_W-1:0]),
.CFG_DCOMMAND (CFG_DCOMMAND[`SIG_CFGREG_W-1:0]),
.CFG_LSTATUS (CFG_LSTATUS[`SIG_CFGREG_W-1:0]),
.CFG_LCOMMAND (CFG_LCOMMAND[`SIG_CFGREG_W-1:0]),
.FC_CPLD (FC_CPLD[`SIG_FC_CPLD_W-1:0]),
.FC_CPLH (FC_CPLH[`SIG_FC_CPLH_W-1:0]),
.CFG_INTERRUPT_MSIEN (CFG_INTERRUPT_MSIEN),
.CFG_INTERRUPT_RDY (CFG_INTERRUPT_RDY));
engine_layer
#(// Parameters
.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_BYTES/4),
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_LOG_NUM_TAGS (C_LOG_NUM_TAGS),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_VENDOR (C_VENDOR))
engine_layer_inst
(// Outputs
.RXC_DATA (rxc_data[C_PCI_DATA_WIDTH-1:0]),
.RXC_DATA_WORD_ENABLE (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_VALID (rxc_data_valid),
.RXC_DATA_START_FLAG (rxc_data_start_flag),
.RXC_DATA_START_OFFSET (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_FDWBE (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXC_DATA_END_FLAG (rxc_data_end_flag),
.RXC_DATA_END_OFFSET (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_LDWBE (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXC_META_TAG (rxc_meta_tag[`SIG_TAG_W-1:0]),
.RXC_META_ADDR (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
.RXC_META_TYPE (rxc_meta_type[`SIG_TYPE_W-1:0]),
.RXC_META_LENGTH (rxc_meta_length[`SIG_LEN_W-1:0]),
.RXC_META_BYTES_REMAINING (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
.RXC_META_COMPLETER_ID (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
.RXC_META_EP (rxc_meta_ep),
.RXR_DATA (rxr_data[C_PCI_DATA_WIDTH-1:0]),
.RXR_DATA_WORD_ENABLE (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_VALID (rxr_data_valid),
.RXR_DATA_START_FLAG (rxr_data_start_flag),
.RXR_DATA_START_OFFSET (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_END_FLAG (rxr_data_end_flag),
.RXR_DATA_END_OFFSET (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_META_FDWBE (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXR_META_LDWBE (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXR_META_TC (rxr_meta_tc[`SIG_TC_W-1:0]),
.RXR_META_ATTR (rxr_meta_attr[`SIG_ATTR_W-1:0]),
.RXR_META_TAG (rxr_meta_tag[`SIG_TAG_W-1:0]),
.RXR_META_TYPE (rxr_meta_type[`SIG_TYPE_W-1:0]),
.RXR_META_ADDR (rxr_meta_addr[`SIG_ADDR_W-1:0]),
.RXR_META_BAR_DECODED (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
.RXR_META_REQUESTER_ID (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
.RXR_META_LENGTH (rxr_meta_length[`SIG_LEN_W-1:0]),
.RXR_META_EP (rxr_meta_ep),
.TXC_DATA_READY (txc_data_ready),
.TXC_META_READY (txc_meta_ready),
.TXC_SENT (txc_sent),
.TXR_DATA_READY (txr_data_ready),
.TXR_META_READY (txr_meta_ready),
.TXR_SENT (txr_sent),
.RST_LOGIC (RST_OUT),
// Unconnected Outputs
.TX_TLP (tx_tlp),
.TX_TLP_VALID (tx_tlp_valid),
.TX_TLP_START_FLAG (tx_tlp_start_flag),
.TX_TLP_START_OFFSET (tx_tlp_start_offset),
.TX_TLP_END_FLAG (tx_tlp_end_flag),
.TX_TLP_END_OFFSET (tx_tlp_end_offset),
.RX_TLP_READY (rx_tlp_ready),
// Inputs
.CLK_BUS (clk),
.RST_BUS (rst_in),
.CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]),
.TXC_DATA_VALID (txc_data_valid),
.TXC_DATA (txc_data[C_PCI_DATA_WIDTH-1:0]),
.TXC_DATA_START_FLAG (txc_data_start_flag),
.TXC_DATA_START_OFFSET (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_DATA_END_FLAG (txc_data_end_flag),
.TXC_DATA_END_OFFSET (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_META_VALID (txc_meta_valid),
.TXC_META_FDWBE (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
.TXC_META_TYPE (txc_meta_type[`SIG_TYPE_W-1:0]),
.TXC_META_LENGTH (txc_meta_length[`SIG_LEN_W-1:0]),
.TXC_META_BYTE_COUNT (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (txc_meta_tag[`SIG_TAG_W-1:0]),
.TXC_META_REQUESTER_ID (txc_meta_requester_id[`SIG_REQID_W-1:0]),
.TXC_META_TC (txc_meta_tc[`SIG_TC_W-1:0]),
.TXC_META_ATTR (txc_meta_attr[`SIG_ATTR_W-1:0]),
.TXC_META_EP (txc_meta_ep),
.TXR_DATA_VALID (txr_data_valid),
.TXR_DATA (txr_data[C_PCI_DATA_WIDTH-1:0]),
.TXR_DATA_START_FLAG (txr_data_start_flag),
.TXR_DATA_START_OFFSET (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (txr_data_end_flag),
.TXR_DATA_END_OFFSET (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (txr_meta_valid),
.TXR_META_FDWBE (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (txr_meta_addr[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (txr_meta_length[`SIG_LEN_W-1:0]),
.TXR_META_TAG (txr_meta_tag[`SIG_TAG_W-1:0]),
.TXR_META_TC (txr_meta_tc[`SIG_TC_W-1:0]),
.TXR_META_ATTR (txr_meta_attr[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (txr_meta_type[`SIG_TYPE_W-1:0]),
.TXR_META_EP (txr_meta_ep),
// Unconnected Inputs
.RX_TLP (rx_tlp),
.RX_TLP_VALID (rx_tlp_valid),
.RX_TLP_START_FLAG (rx_tlp_start_flag),
.RX_TLP_START_OFFSET (rx_tlp_start_offset),
.RX_TLP_END_FLAG (rx_tlp_end_flag),
.RX_TLP_END_OFFSET (rx_tlp_end_offset),
.RX_TLP_BAR_DECODE (rx_tlp_bar_decode),
.TX_TLP_READY (tx_tlp_ready),
.DONE_TXC_RST (done_txc_rst),
.DONE_TXR_RST (done_txr_rst),
.DONE_RXR_RST (done_rxc_rst),
.DONE_RXC_RST (done_rxr_rst),
// Outputs
.M_AXIS_CQ_TREADY (m_axis_cq_tready_nc),
.M_AXIS_RC_TREADY (m_axis_rc_tready_nc),
.S_AXIS_CC_TVALID (s_axis_cc_tvalid_nc),
.S_AXIS_CC_TLAST (s_axis_cc_tlast_nc),
.S_AXIS_CC_TDATA (s_axis_cc_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_CC_TKEEP (s_axis_cc_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_CC_TUSER (s_axis_cc_tuser_nc[`SIG_CC_TUSER_W-1:0]),
.S_AXIS_RQ_TVALID (s_axis_rq_tvalid_nc),
.S_AXIS_RQ_TLAST (s_axis_rq_tlast_nc),
.S_AXIS_RQ_TDATA (s_axis_rq_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_RQ_TKEEP (s_axis_rq_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_RQ_TUSER (s_axis_rq_tuser_nc[`SIG_RQ_TUSER_W-1:0]),
// Inputs
.M_AXIS_CQ_TVALID (m_axis_cq_tvalid_nc),
.M_AXIS_CQ_TLAST (m_axis_cq_tlast_nc),
.M_AXIS_CQ_TDATA (m_axis_cq_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_CQ_TKEEP (m_axis_cq_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_CQ_TUSER (m_axis_cq_tuser_nc[`SIG_CQ_TUSER_W-1:0]),
.M_AXIS_RC_TVALID (m_axis_rc_tvalid_nc),
.M_AXIS_RC_TLAST (m_axis_rc_tlast_nc),
.M_AXIS_RC_TDATA (m_axis_rc_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_RC_TKEEP (m_axis_rc_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_RC_TUSER (m_axis_rc_tuser_nc[`SIG_RC_TUSER_W-1:0]),
.S_AXIS_CC_TREADY (s_axis_cc_tready_nc),
.S_AXIS_RQ_TREADY (s_axis_rq_tready_nc)
/*AUTOINST*/);
riffa
#(.C_TAG_WIDTH (C_LOG_NUM_TAGS),/* TODO: Standardize declaration*/
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_NUM_CHNL (C_NUM_CHNL),
.C_MAX_READ_REQ_BYTES (C_MAX_READ_REQ_BYTES),
.C_VENDOR (C_VENDOR),
.C_FPGA_NAME (C_FPGA_NAME),
.C_FPGA_ID (C_FPGA_ID),
.C_DEPTH_PACKETS (C_DEPTH_PACKETS))
riffa_inst
(// Outputs
.TXC_DATA (txc_data[C_PCI_DATA_WIDTH-1:0]),
.TXC_DATA_VALID (txc_data_valid),
.TXC_DATA_START_FLAG (txc_data_start_flag),
.TXC_DATA_START_OFFSET (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_DATA_END_FLAG (txc_data_end_flag),
.TXC_DATA_END_OFFSET (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_META_VALID (txc_meta_valid),
.TXC_META_FDWBE (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
.TXC_META_TYPE (txc_meta_type[`SIG_TYPE_W-1:0]),
.TXC_META_LENGTH (txc_meta_length[`SIG_LEN_W-1:0]),
.TXC_META_BYTE_COUNT (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (txc_meta_tag[`SIG_TAG_W-1:0]),
.TXC_META_REQUESTER_ID (txc_meta_requester_id[`SIG_REQID_W-1:0]),
.TXC_META_TC (txc_meta_tc[`SIG_TC_W-1:0]),
.TXC_META_ATTR (txc_meta_attr[`SIG_ATTR_W-1:0]),
.TXC_META_EP (txc_meta_ep),
.TXR_DATA_VALID (txr_data_valid),
.TXR_DATA (txr_data[C_PCI_DATA_WIDTH-1:0]),
.TXR_DATA_START_FLAG (txr_data_start_flag),
.TXR_DATA_START_OFFSET (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (txr_data_end_flag),
.TXR_DATA_END_OFFSET (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (txr_meta_valid),
.TXR_META_FDWBE (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (txr_meta_addr[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (txr_meta_length[`SIG_LEN_W-1:0]),
.TXR_META_TAG (txr_meta_tag[`SIG_TAG_W-1:0]),
.TXR_META_TC (txr_meta_tc[`SIG_TC_W-1:0]),
.TXR_META_ATTR (txr_meta_attr[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (txr_meta_type[`SIG_TYPE_W-1:0]),
.TXR_META_EP (txr_meta_ep),
.INTR_MSI_REQUEST (intr_msi_request),
// Inputs
.CLK (clk),
.RXR_DATA (rxr_data[C_PCI_DATA_WIDTH-1:0]),
.RXR_DATA_VALID (rxr_data_valid),
.RXR_DATA_START_FLAG (rxr_data_start_flag),
.RXR_DATA_START_OFFSET (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_WORD_ENABLE (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_END_FLAG (rxr_data_end_flag),
.RXR_DATA_END_OFFSET (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_META_FDWBE (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXR_META_LDWBE (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXR_META_TC (rxr_meta_tc[`SIG_TC_W-1:0]),
.RXR_META_ATTR (rxr_meta_attr[`SIG_ATTR_W-1:0]),
.RXR_META_TAG (rxr_meta_tag[`SIG_TAG_W-1:0]),
.RXR_META_TYPE (rxr_meta_type[`SIG_TYPE_W-1:0]),
.RXR_META_ADDR (rxr_meta_addr[`SIG_ADDR_W-1:0]),
.RXR_META_BAR_DECODED (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
.RXR_META_REQUESTER_ID (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
.RXR_META_LENGTH (rxr_meta_length[`SIG_LEN_W-1:0]),
.RXR_META_EP (rxr_meta_ep),
.RXC_DATA_VALID (rxc_data_valid),
.RXC_DATA (rxc_data[C_PCI_DATA_WIDTH-1:0]),
.RXC_DATA_START_FLAG (rxc_data_start_flag),
.RXC_DATA_START_OFFSET (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_WORD_ENABLE (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_END_FLAG (rxc_data_end_flag),
.RXC_DATA_END_OFFSET (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_FDWBE (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXC_META_LDWBE (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXC_META_TAG (rxc_meta_tag[`SIG_TAG_W-1:0]),
.RXC_META_ADDR (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
.RXC_META_TYPE (rxc_meta_type[`SIG_TYPE_W-1:0]),
.RXC_META_LENGTH (rxc_meta_length[`SIG_LEN_W-1:0]),
.RXC_META_BYTES_REMAINING (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
.RXC_META_COMPLETER_ID (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
.RXC_META_EP (rxc_meta_ep),
.TXC_DATA_READY (txc_data_ready),
.TXC_META_READY (txc_meta_ready),
.TXC_SENT (txc_sent),
.TXR_DATA_READY (txr_data_ready),
.TXR_META_READY (txr_meta_ready),
.TXR_SENT (txr_sent),
.CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]),
.CONFIG_BUS_MASTER_ENABLE (config_bus_master_enable),
.CONFIG_LINK_WIDTH (config_link_width[`SIG_LINKWIDTH_W-1:0]),
.CONFIG_LINK_RATE (config_link_rate[`SIG_LINKRATE_W-1:0]),
.CONFIG_MAX_READ_REQUEST_SIZE (config_max_read_request_size[`SIG_MAXREAD_W-1:0]),
.CONFIG_MAX_PAYLOAD_SIZE (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]),
.CONFIG_INTERRUPT_MSIENABLE (config_interrupt_msienable),
.CONFIG_CPL_BOUNDARY_SEL (config_cpl_boundary_sel),
.CONFIG_MAX_CPL_DATA (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]),
.CONFIG_MAX_CPL_HDR (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]),
.INTR_MSI_RDY (intr_msi_rdy),
.DONE_TXC_RST (done_txc_rst),
.DONE_TXR_RST (done_txr_rst),
.RST_BUS (rst_in),
/*AUTOINST*/
// Outputs
.RST_OUT (RST_OUT),
.CHNL_RX (CHNL_RX[C_NUM_CHNL-1:0]),
.CHNL_RX_LAST (CHNL_RX_LAST[C_NUM_CHNL-1:0]),
.CHNL_RX_LEN (CHNL_RX_LEN[(C_NUM_CHNL*32)-1:0]),
.CHNL_RX_OFF (CHNL_RX_OFF[(C_NUM_CHNL*31)-1:0]),
.CHNL_RX_DATA (CHNL_RX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_RX_DATA_VALID (CHNL_RX_DATA_VALID[C_NUM_CHNL-1:0]),
.CHNL_TX_ACK (CHNL_TX_ACK[C_NUM_CHNL-1:0]),
.CHNL_TX_DATA_REN (CHNL_TX_DATA_REN[C_NUM_CHNL-1:0]),
// Inputs
.CHNL_RX_CLK (CHNL_RX_CLK[C_NUM_CHNL-1:0]),
.CHNL_RX_ACK (CHNL_RX_ACK[C_NUM_CHNL-1:0]),
.CHNL_RX_DATA_REN (CHNL_RX_DATA_REN[C_NUM_CHNL-1:0]),
.CHNL_TX_CLK (CHNL_TX_CLK[C_NUM_CHNL-1:0]),
.CHNL_TX (CHNL_TX[C_NUM_CHNL-1:0]),
.CHNL_TX_LAST (CHNL_TX_LAST[C_NUM_CHNL-1:0]),
.CHNL_TX_LEN (CHNL_TX_LEN[(C_NUM_CHNL*32)-1:0]),
.CHNL_TX_OFF (CHNL_TX_OFF[(C_NUM_CHNL*31)-1:0]),
.CHNL_TX_DATA (CHNL_TX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_TX_DATA_VALID (CHNL_TX_DATA_VALID[C_NUM_CHNL-1:0]));
endmodule
// Local Variables:
// verilog-library-directories:("../../riffa_hdl/")
// End:
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Power Management ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// PM according to OR1K architectural specification. ////
//// ////
//// To Do: ////
//// - add support for dynamic clock gating ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_pm.v,v $
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7 2001/10/14 13:12:10 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:21 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "rtl/verilog/or1200/timescale.v"
// synopsys translate_on
`include "rtl/verilog/or1200/or1200_defines.v"
module or1200_pm(
// RISC Internal Interface
clk, rst, pic_wakeup, spr_write, spr_addr, spr_dat_i, spr_dat_o,
// Power Management Interface
pm_clksd, pm_cpustall, pm_dc_gate, pm_ic_gate, pm_dmmu_gate,
pm_immu_gate, pm_tt_gate, pm_cpu_gate, pm_wakeup, pm_lvolt
);
//
// RISC Internal Interface
//
input clk; // Clock
input rst; // Reset
input pic_wakeup; // Wakeup from the PIC
input spr_write; // SPR Read/Write
input [31:0] spr_addr; // SPR Address
input [31:0] spr_dat_i; // SPR Write Data
output [31:0] spr_dat_o; // SPR Read Data
//
// Power Management Interface
//
input pm_cpustall; // Stall the CPU
output [3:0] pm_clksd; // Clock Slowdown factor
output pm_dc_gate; // Gate DCache clock
output pm_ic_gate; // Gate ICache clock
output pm_dmmu_gate; // Gate DMMU clock
output pm_immu_gate; // Gate IMMU clock
output pm_tt_gate; // Gate Tick Timer clock
output pm_cpu_gate; // Gate main RISC/CPU clock
output pm_wakeup; // Activate (de-gate) all clocks
output pm_lvolt; // Lower operating voltage
`ifdef OR1200_PM_IMPLEMENTED
//
// Power Management Register bits
//
reg [3:0] sdf; // Slow-down factor
reg dme; // Doze Mode Enable
reg sme; // Sleep Mode Enable
reg dcge; // Dynamic Clock Gating Enable
//
// Internal wires
//
wire pmr_sel; // PMR select
//
// PMR address decoder (partial decoder)
//
`ifdef OR1200_PM_PARTIAL_DECODING
assign pmr_sel = (spr_addr[`OR1200_SPR_GROUP_BITS] == `OR1200_SPRGRP_PM) ? 1'b1 : 1'b0;
`else
assign pmr_sel = ((spr_addr[`OR1200_SPR_GROUP_BITS] == `OR1200_SPRGRP_PM) &&
(spr_addr[`OR1200_SPR_OFS_BITS] == `OR1200_PM_OFS_PMR)) ? 1'b1 : 1'b0;
`endif
//
// Write to PMR and also PMR[DME]/PMR[SME] reset when
// pic_wakeup is asserted
//
always @(posedge clk or posedge rst)
if (rst)
{dcge, sme, dme, sdf} <= 7'b0;
else if (pmr_sel && spr_write) begin
sdf <= #1 spr_dat_i[`OR1200_PM_PMR_SDF];
dme <= #1 spr_dat_i[`OR1200_PM_PMR_DME];
sme <= #1 spr_dat_i[`OR1200_PM_PMR_SME];
dcge <= #1 spr_dat_i[`OR1200_PM_PMR_DCGE];
end
else if (pic_wakeup) begin
dme <= #1 1'b0;
sme <= #1 1'b0;
end
//
// Read PMR
//
`ifdef OR1200_PM_READREGS
assign spr_dat_o[`OR1200_PM_PMR_SDF] = sdf;
assign spr_dat_o[`OR1200_PM_PMR_DME] = dme;
assign spr_dat_o[`OR1200_PM_PMR_SME] = sme;
assign spr_dat_o[`OR1200_PM_PMR_DCGE] = dcge;
`ifdef OR1200_PM_UNUSED_ZERO
assign spr_dat_o[`OR1200_PM_PMR_UNUSED] = 25'b0;
`endif
`endif
//
// Generate pm_clksd
//
assign pm_clksd = sdf;
//
// Statically generate all clock gate outputs
// TODO: add dynamic clock gating feature
//
assign pm_cpu_gate = (dme | sme) & ~pic_wakeup;
assign pm_dc_gate = pm_cpu_gate;
assign pm_ic_gate = pm_cpu_gate;
assign pm_dmmu_gate = pm_cpu_gate;
assign pm_immu_gate = pm_cpu_gate;
assign pm_tt_gate = sme & ~pic_wakeup;
//
// Assert pm_wakeup when pic_wakeup is asserted
//
assign pm_wakeup = pic_wakeup;
//
// Assert pm_lvolt when pm_cpu_gate or pm_cpustall are asserted
//
assign pm_lvolt = pm_cpu_gate | pm_cpustall;
`else
//
// When PM is not implemented, drive all outputs as would when PM is disabled
//
assign pm_clksd = 4'b0;
assign pm_cpu_gate = 1'b0;
assign pm_dc_gate = 1'b0;
assign pm_ic_gate = 1'b0;
assign pm_dmmu_gate = 1'b0;
assign pm_immu_gate = 1'b0;
assign pm_tt_gate = 1'b0;
assign pm_wakeup = 1'b1;
assign pm_lvolt = 1'b0;
//
// Read PMR
//
`ifdef OR1200_PM_READREGS
assign spr_dat_o[`OR1200_PM_PMR_SDF] = 4'b0;
assign spr_dat_o[`OR1200_PM_PMR_DME] = 1'b0;
assign spr_dat_o[`OR1200_PM_PMR_SME] = 1'b0;
assign spr_dat_o[`OR1200_PM_PMR_DCGE] = 1'b0;
`ifdef OR1200_PM_UNUSED_ZERO
assign spr_dat_o[`OR1200_PM_PMR_UNUSED] = 25'b0;
`endif
`endif
`endif
endmodule
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: upd77c25_datram.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
// ************************************************************
//Copyright (C) 2020 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module upd77c25_datram (
address_a,
address_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [9:0] address_a;
input [10:0] address_b;
input clock;
input [15:0] data_a;
input [7:0] data_b;
input wren_a;
input wren_b;
output [15:0] q_a;
output [7:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [7:0] sub_wire1;
wire [15:0] q_a = sub_wire0[15:0];
wire [7:0] q_b = sub_wire1[7:0];
altsyncram altsyncram_component (
.address_a (address_a),
.address_b (address_b),
.clock0 (clock),
.data_a (data_a),
.data_b (data_b),
.wren_a (wren_a),
.wren_b (wren_b),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.numwords_b = 2048,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 10,
altsyncram_component.widthad_b = 11,
altsyncram_component.width_a = 16,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "2048"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL "address_a[9..0]"
// Retrieval info: USED_PORT: address_b 0 0 11 0 INPUT NODEFVAL "address_b[10..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data_a 0 0 16 0 INPUT NODEFVAL "data_a[15..0]"
// Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL "data_b[7..0]"
// Retrieval info: USED_PORT: q_a 0 0 16 0 OUTPUT NODEFVAL "q_a[15..0]"
// Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL "q_b[7..0]"
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0
// Retrieval info: CONNECT: @address_b 0 0 11 0 address_b 0 0 11 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 data_a 0 0 16 0
// Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL upd77c25_datram.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL upd77c25_datram.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL upd77c25_datram.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL upd77c25_datram.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL upd77c25_datram_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL upd77c25_datram_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
`timescale 1ns / 1ps
`default_nettype none //To avoid bugs involving implicit nets
////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Acknowledgements: Prof. Kyle Gilsdorf (Arizona State)
// - http://www.public.asu.edu/~kyle135/
// - [email protected]
//
//
// Author: Rushang Vinod Vandana Karia
// - Masters in Computer Science @ Arizona State
// - [email protected]
// - 4806283130
// - github.com/RushangKaria
//
//
// Module: Input_Sync.v
//
//
// Description : Synchronizer for the MSEL with the TFT Clock
//
// Copyright : Copyright (C) 2014 Rushang Vinod Vandana Karia
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
//
//////////////////////////////////////////////////////////////////////////////////////////////////////////////
module InputSyncV #(parameter WIDTH=4)
(
input wire CLK_I,
input wire [3:0] D_I,
output wire [3:0] D_O
);
///////////////////////////////////////////////////////////////////////////////////////
// SYNTHESIS SPECIFIC INSTRUCTIONS
///////////////////////////////////////////////////////////////////////////////////////
//synthesis attribute TIG of D_I is "TRUE"
//synthesis attribute IOB of D_I is "FALSE"
//synthesis attribute ASYNC_REG of sreg is "TRUE"
//synthesis attribute SHIFT_EXTRACT of sreg is "NO"
//synthesis attribute HBLKMN of sreg is "sync_reg"
//////////////////////////////////
// SYNC PROCESS
//////////////////////////////////
genvar i;
generate
for(i=3;i>=0;i=i-1)
begin
InputSync input_sync_inst
(
.CLK_I (CLK_I),
.D_I (D_I[i]),
.D_O (D_O[i])
);
end
endgenerate
endmodule
module InputSync
(
input wire D_I,
input wire CLK_I,
output reg D_O
);
///////////////////////////////////////////////////////////////////////////////////////
// SIGNALS LOCAL TO MODULE
///////////////////////////////////////////////////////////////////////////////////////
reg [1:0] sreg;
///////////////////////////////////////////////////////////////////////////////////////
// SYNTHESIS SPECIFIC INSTRUCTIONS
///////////////////////////////////////////////////////////////////////////////////////
//synthesis attribute TIG of D_I is "TRUE"
//synthesis attribute IOB of D_I is "FALSE"
//synthesis attribute ASYNC_REG of sreg is "TRUE"
//synthesis attribute SHIFT_EXTRACT of sreg is "NO"
//synthesis attribute HBLKMN of sreg is "sync_reg"
//////////////////////////////////
// SYNC PROCESS
//////////////////////////////////
always@(posedge CLK_I)
begin
D_O <= sreg[1];
sreg <= {sreg[0],D_I};
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFXBP_BEHAVIORAL_V
`define SKY130_FD_SC_LP__DFXBP_BEHAVIORAL_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_lp__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dfxbp (
Q ,
Q_N,
CLK,
D
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire CLK_delayed;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_lp__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFXBP_BEHAVIORAL_V |
// Copyright (C) 2013 Simon Que
//
// This file is part of DuinoCube.
//
// DuinoCube is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// DuinoCube is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with DuinoCube. If not, see <http://www.gnu.org/licenses/>.
// DuinoCube tile layer register field decoder.
`include "memory_map.vh"
`include "tile_registers.vh"
module TileRegDecoder(current_layer,
reg_values,
layer_enabled,
enable_8bit,
enable_nop,
enable_scroll,
enable_transp,
enable_alpha,
enable_color,
enable_wrap_x,
enable_wrap_y,
enable_flip,
shift_data_offset,
tile_hsize_enum,
tile_vsize_enum,
ctrl0,
ctrl1,
data_offset,
nop_value,
color_key,
offset_x,
offset_y);
input [1:0] current_layer;
input [`NUM_TOTAL_TILE_REG_BITS-1:0] reg_values;
wire [`NUM_REG_BITS_PER_TILE_LAYER-1:0]
reg_values_array[`NUM_TILE_LAYERS-1:0];
genvar i;
generate
for (i = 0; i < `NUM_TILE_LAYERS; i = i + 1) begin: TILE_REG_VALUES
assign reg_values_array[i] =
reg_values[(i + 1) * `NUM_REG_BITS_PER_TILE_LAYER - 1:
i * `NUM_REG_BITS_PER_TILE_LAYER];
end
endgenerate
wire [`REG_DATA_WIDTH-1:0] regs [`NUM_TILE_REGISTERS-1:0];
generate
for (i = 0; i < `NUM_TILE_REGISTERS; i = i + 1) begin: TILE_REGS
assign regs[i] =
reg_values_array[current_layer][(i+1)*`REG_DATA_WIDTH-1:
i*`REG_DATA_WIDTH];
end
endgenerate
output layer_enabled ;
output enable_8bit ;
output enable_nop ;
output enable_scroll ;
output enable_transp ;
output enable_alpha ;
output enable_color ;
output enable_wrap_x ;
output enable_wrap_y ;
output enable_flip ;
output shift_data_offset;
output [`TILE_HSIZE_WIDTH-1:0] tile_hsize_enum;
output [`TILE_VSIZE_WIDTH-1:0] tile_vsize_enum;
output [`REG_DATA_WIDTH-1:0] ctrl0 ;
output [`REG_DATA_WIDTH-1:0] ctrl1 ;
output [`VRAM_ADDR_WIDTH:0] data_offset ;
output [`REG_DATA_WIDTH-1:0] nop_value ;
output [`REG_DATA_WIDTH-1:0] color_key ;
output [`REG_DATA_WIDTH-1:0] offset_x ;
output [`REG_DATA_WIDTH-1:0] offset_y ;
assign layer_enabled = regs[`TILE_CTRL0][`TILE_LAYER_ENABLED];
assign enable_8bit = regs[`TILE_CTRL0][`TILE_ENABLE_8_BIT];
assign enable_nop = regs[`TILE_CTRL0][`TILE_ENABLE_NOP];
assign enable_scroll = regs[`TILE_CTRL0][`TILE_ENABLE_SCROLL];
assign enable_transp = regs[`TILE_CTRL0][`TILE_ENABLE_TRANSP];
assign enable_alpha = regs[`TILE_CTRL0][`TILE_ENABLE_ALPHA];
assign enable_color = regs[`TILE_CTRL0][`TILE_ENABLE_COLOR];
assign enable_wrap_x = regs[`TILE_CTRL0][`TILE_ENABLE_WRAP_X];
assign enable_wrap_y = regs[`TILE_CTRL0][`TILE_ENABLE_WRAP_Y];
assign enable_flip = regs[`TILE_CTRL0][`TILE_ENABLE_FLIP];
assign shift_data_offset = regs[`TILE_CTRL0][`TILE_SHIFT_DATA_OFFSET];
assign tile_hsize_enum = regs[`TILE_CTRL1][`TILE_HSIZE_1:`TILE_HSIZE_0];
assign tile_vsize_enum = regs[`TILE_CTRL1][`TILE_VSIZE_1:`TILE_VSIZE_0];
assign ctrl0 = regs[`TILE_CTRL0];
assign ctrl1 = regs[`TILE_CTRL1];
assign data_offset =
shift_data_offset ? (regs[`TILE_DATA_OFFSET] << `TILE_DATA_OFFSET_SHIFT)
: regs[`TILE_DATA_OFFSET];
assign nop_value = regs[`TILE_NOP_VALUE];
assign color_key = regs[`TILE_COLOR_KEY];
assign offset_x = regs[`TILE_OFFSET_X];
assign offset_y = regs[`TILE_OFFSET_Y];
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// (c) Copyright 2008 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//
///////////////////////////////////////////////////////////////////////////////
//
// SYM_DEC
//
//
// Description: The SYM_DEC module is a symbol decoder for the 2-byte
// Aurora Lane. Its inputs are the raw data from the GTP.
// It word-aligns the regular data and decodes all of the
// Aurora control symbols. Its outputs are the word-aligned
// data and signals indicating the arrival of specific
// control characters.
//
`timescale 1 ns / 1 ps
module aur1_SYM_DEC
(
// RX_LL Interface
RX_PAD,
RX_PE_DATA,
RX_PE_DATA_V,
RX_SCP,
RX_ECP,
// Lane Init SM Interface
DO_WORD_ALIGN,
RX_SP,
RX_SPA,
RX_NEG,
// Global Logic Interface
GOT_A,
GOT_V,
// GTP Interface
RX_DATA,
RX_CHAR_IS_K,
RX_CHAR_IS_COMMA,
// System Interface
USER_CLK,
RESET
);
`define DLY #1
//***********************************Parameter Declarations**************************
parameter K_CHAR_0 = 4'hb;
parameter K_CHAR_1 = 4'hc;
parameter SP_DATA_0 = 4'h4;
parameter SP_DATA_1 = 4'ha;
parameter SPA_DATA_0 = 4'h2;
parameter SPA_DATA_1 = 4'hc;
parameter SP_NEG_DATA_0 = 4'hb;
parameter SP_NEG_DATA_1 = 4'h5;
parameter SPA_NEG_DATA_0 = 4'hd;
parameter SPA_NEG_DATA_1 = 4'h3;
parameter PAD_0 = 4'h9;
parameter PAD_1 = 4'hc;
parameter SCP_0 = 4'h5;
parameter SCP_1 = 4'hc;
parameter SCP_2 = 4'hf;
parameter SCP_3 = 4'hb;
parameter ECP_0 = 4'hf;
parameter ECP_1 = 4'hd;
parameter ECP_2 = 4'hf;
parameter ECP_3 = 4'he;
parameter A_CHAR_0 = 4'h7;
parameter A_CHAR_1 = 4'hc;
parameter VER_DATA_0 = 4'he;
parameter VER_DATA_1 = 4'h8;
//***********************************Port Declarations*******************************
// RX_LL Interface
output RX_PAD; // LSByte is PAD.
output [0:15] RX_PE_DATA; // Word aligned data from channel partner.
output RX_PE_DATA_V; // Data is valid data and not a control character.
output RX_SCP; // SCP symbol received.
output RX_ECP; // ECP symbol received.
// Lane Init SM Interface
input DO_WORD_ALIGN; // Word alignment is allowed.
output RX_SP; // SP sequence received with positive or negative data.
output RX_SPA; // SPA sequence received.
output RX_NEG; // Intverted data for SP or SPA received.
// Global Logic Interface
output [0:1] GOT_A; // A character received on indicated byte(s).
output GOT_V; // V sequence received.
// GTP Interface
input [15:0] RX_DATA; // Raw RX data from GTP.
input [1:0] RX_CHAR_IS_K; // Bits indicating which bytes are control characters.
input [1:0] RX_CHAR_IS_COMMA; // Rx'ed a comma.
// System Interface
input USER_CLK; // System clock for all non-GTP Aurora Logic.
input RESET;
//**************************External Register Declarations****************************
reg [0:15] RX_PE_DATA;
reg RX_PAD;
reg RX_PE_DATA_V;
reg RX_SCP;
reg RX_ECP;
reg RX_SP;
reg RX_SPA;
reg RX_NEG;
reg [0:1] GOT_A;
reg GOT_V;
//**************************Internal Register Declarations****************************
reg left_aligned_r;
reg [0:7] previous_cycle_data_r;
reg previous_cycle_control_r;
reg prev_beat_sp_r;
reg prev_beat_spa_r;
reg [0:15] word_aligned_data_r;
reg [0:1] word_aligned_control_bits_r;
reg [0:15] rx_pe_data_r;
reg [0:1] rx_pe_control_r;
reg [0:1] rx_pad_d_r;
reg [0:3] rx_scp_d_r;
reg [0:3] rx_ecp_d_r;
reg [0:3] prev_beat_sp_d_r;
reg [0:3] prev_beat_spa_d_r;
reg [0:3] rx_sp_d_r;
reg [0:3] rx_spa_d_r;
reg [0:1] rx_sp_neg_d_r;
reg [0:1] rx_spa_neg_d_r;
reg [0:3] prev_beat_v_d_r;
reg prev_beat_v_r;
reg [0:3] rx_v_d_r;
reg [0:3] got_a_d_r;
reg first_v_received_r;
//*********************************Wire Declarations**********************************
wire got_v_c;
//*********************************Main Body of Code**********************************
//__________________________Word Alignment__________________________________
// Determine whether the lane is aligned to the left byte (MS byte) or the
// right byte (LS byte). This information is used for word alignment. To
// prevent the word align from changing during normal operation, we do word
// alignment only when it is allowed by the lane_init_sm.
always @(posedge USER_CLK)
if(DO_WORD_ALIGN & !first_v_received_r)
case({RX_CHAR_IS_COMMA,RX_CHAR_IS_K})
4'b1010 : left_aligned_r <= `DLY 1'b1;
4'b0101 : left_aligned_r <= `DLY 1'b0;
default : left_aligned_r <= `DLY left_aligned_r;
endcase
// Store the LS byte from the previous cycle. If the lane is aligned on
// the LS byte, we use it as the MS byte on the current cycle.
always @(posedge USER_CLK)
previous_cycle_data_r <= `DLY RX_DATA[7:0];
// Store the control bit from the previous cycle LS byte. It becomes the
// control bit for the MS byte on this cycle if the lane is aligned to the
// LS byte.
always @(posedge USER_CLK)
previous_cycle_control_r <= `DLY RX_CHAR_IS_K[0];
// Select the word-aligned MS byte. Use the current MS byte if the data is
// left-aligned, otherwise use the LS byte from the previous cycle.
always @(posedge USER_CLK)
word_aligned_data_r[0:7] <= `DLY left_aligned_r? RX_DATA[15:8]
: previous_cycle_data_r;
// Select the word-aligned LS byte. Use the current LSByte if the data is
// right-aligned, otherwise use the current MS byte.
always @(posedge USER_CLK)
word_aligned_data_r[8:15] <= `DLY left_aligned_r? RX_DATA[7:0] : RX_DATA[15:8];
// Select the word-aligned MS byte control bit. Use the current MSByte's
// control bit if the data is left-aligned, otherwise use the LS byte's
// control bit from the previous cycle.
always @(posedge USER_CLK)
word_aligned_control_bits_r[0] <= `DLY left_aligned_r? RX_CHAR_IS_K[1]
: previous_cycle_control_r;
// Select the word-aligned LS byte control bit. Use the current LSByte's control
// bit if the data is left-aligned, otherwise use the current MS byte's control bit.
always @(posedge USER_CLK)
word_aligned_control_bits_r[1] <= `DLY left_aligned_r? RX_CHAR_IS_K[0]
: RX_CHAR_IS_K[1];
// Pipeline the word-aligned data for 1 cycle to match the Decodes.
always @(posedge USER_CLK)
rx_pe_data_r <= `DLY word_aligned_data_r;
// Register the pipelined word-aligned data for the RX_LL interface.
always @(posedge USER_CLK)
RX_PE_DATA <= `DLY rx_pe_data_r;
//_____________________________Decode Control Symbols___________________________
// All decodes are pipelined to keep the number of logic levels to a minimum.
// Delay the control bits: they are most often used in the second stage of
// the decoding process.
always @(posedge USER_CLK)
rx_pe_control_r <= `DLY word_aligned_control_bits_r;
// Decode PAD
always @(posedge USER_CLK)
begin
rx_pad_d_r[0] <= `DLY (word_aligned_data_r[8:11] == PAD_0);
rx_pad_d_r[1] <= `DLY (word_aligned_data_r[12:15] == PAD_1);
end
always @(posedge USER_CLK)
RX_PAD <= `DLY (rx_pad_d_r== 2'b11) & (rx_pe_control_r == 2'b01);
// Decode RX_PE_DATA_V
always @(posedge USER_CLK)
RX_PE_DATA_V <= `DLY !rx_pe_control_r[0];
// Decode RX_SCP
always @(posedge USER_CLK)
begin
rx_scp_d_r[0] <= `DLY (word_aligned_data_r[0:3] == SCP_0);
rx_scp_d_r[1] <= `DLY (word_aligned_data_r[4:7] == SCP_1);
rx_scp_d_r[2] <= `DLY (word_aligned_data_r[8:11] == SCP_2);
rx_scp_d_r[3] <= `DLY (word_aligned_data_r[12:15] == SCP_3);
end
always @(posedge USER_CLK)
RX_SCP <= `DLY &{rx_pe_control_r, rx_scp_d_r};
// Decode RX_ECP
always @(posedge USER_CLK)
begin
rx_ecp_d_r[0] <= `DLY (word_aligned_data_r[0:3] == ECP_0);
rx_ecp_d_r[1] <= `DLY (word_aligned_data_r[4:7] == ECP_1);
rx_ecp_d_r[2] <= `DLY (word_aligned_data_r[8:11] == ECP_2);
rx_ecp_d_r[3] <= `DLY (word_aligned_data_r[12:15] == ECP_3);
end
always @(posedge USER_CLK)
RX_ECP <= `DLY &{rx_pe_control_r, rx_ecp_d_r};
// For an SP sequence to be valid, there must be 2 bytes of SP Data preceded
// by a Comma and an SP Data byte in the MS byte and LS byte positions
// respectively. This flop stores the decode of the Comma and SP Data byte
// combination from the previous cycle. Data can be positive or negative.
always @(posedge USER_CLK)
begin
prev_beat_sp_d_r[0] <= `DLY (word_aligned_data_r[0:3] == K_CHAR_0);
prev_beat_sp_d_r[1] <= `DLY (word_aligned_data_r[4:7] == K_CHAR_1);
prev_beat_sp_d_r[2] <= `DLY (word_aligned_data_r[8:11] == SP_DATA_0)|
(word_aligned_data_r[8:11] == SP_NEG_DATA_0);
prev_beat_sp_d_r[3] <= `DLY (word_aligned_data_r[12:15] == SP_DATA_1)|
(word_aligned_data_r[12:15] == SP_NEG_DATA_1);
end
always @(posedge USER_CLK)
prev_beat_sp_r <= `DLY (rx_pe_control_r == 2'b10) &
(prev_beat_sp_d_r == 4'b1111);
// This flow stores the decode of a Comma and SPA Data byte combination from the
// previous cycle. It is used along with decodes for SPA data in the current
// cycle to determine whether an SPA sequence was received.
always @(posedge USER_CLK)
begin
prev_beat_spa_d_r[0] <= `DLY (word_aligned_data_r[0:3] == K_CHAR_0);
prev_beat_spa_d_r[1] <= `DLY (word_aligned_data_r[4:7] == K_CHAR_1);
prev_beat_spa_d_r[2] <= `DLY (word_aligned_data_r[8:11] == SPA_DATA_0);
prev_beat_spa_d_r[3] <= `DLY (word_aligned_data_r[12:15] == SPA_DATA_1);
end
always @(posedge USER_CLK)
prev_beat_spa_r <= `DLY (rx_pe_control_r == 2'b10) &
(prev_beat_spa_d_r == 4'b1111);
// Indicate the SP sequence was received.
always @(posedge USER_CLK)
begin
rx_sp_d_r[0] <= `DLY (word_aligned_data_r[0:3] == SP_DATA_0)|
(word_aligned_data_r[0:3] == SP_NEG_DATA_0);
rx_sp_d_r[1] <= `DLY (word_aligned_data_r[4:7] == SP_DATA_1)|
(word_aligned_data_r[4:7] == SP_NEG_DATA_1);
rx_sp_d_r[2] <= `DLY (word_aligned_data_r[8:11] == SP_DATA_0)|
(word_aligned_data_r[8:11] == SP_NEG_DATA_0);
rx_sp_d_r[3] <= `DLY (word_aligned_data_r[12:15] == SP_DATA_1)|
(word_aligned_data_r[12:15] == SP_NEG_DATA_1);
end
always @(posedge USER_CLK)
RX_SP <= `DLY prev_beat_sp_r &
(rx_pe_control_r == 2'b00) &
(rx_sp_d_r == 4'b1111);
// Indicate the SPA sequence was received.
always @(posedge USER_CLK)
begin
rx_spa_d_r[0] <= `DLY (word_aligned_data_r[0:3] == SPA_DATA_0);
rx_spa_d_r[1] <= `DLY (word_aligned_data_r[4:7] == SPA_DATA_1);
rx_spa_d_r[2] <= `DLY (word_aligned_data_r[8:11] == SPA_DATA_0);
rx_spa_d_r[3] <= `DLY (word_aligned_data_r[12:15] == SPA_DATA_1);
end
always @(posedge USER_CLK)
RX_SPA <= `DLY prev_beat_spa_r &
(rx_pe_control_r == 2'b00) &
(rx_spa_d_r == 4'b1111);
// Indicate reversed data received. We look only at the word-aligned LS byte
// which, during an /SP/ or /SPA/ sequence, will always contain a data byte.
always @(posedge USER_CLK)
begin
rx_sp_neg_d_r[0] <= `DLY (word_aligned_data_r[8:11] == SP_NEG_DATA_0);
rx_sp_neg_d_r[1] <= `DLY (word_aligned_data_r[12:15] == SP_NEG_DATA_1);
rx_spa_neg_d_r[0] <= `DLY (word_aligned_data_r[8:11] == SPA_NEG_DATA_0);
rx_spa_neg_d_r[1] <= `DLY (word_aligned_data_r[12:15] == SPA_NEG_DATA_1);
end
always @(posedge USER_CLK)
RX_NEG <= `DLY !rx_pe_control_r[1] &
((rx_sp_neg_d_r == 2'b11)|
(rx_spa_neg_d_r == 2'b11));
// GOT_A is decoded from the non_word-aligned input.
always @(posedge USER_CLK)
begin
got_a_d_r[0] <= `DLY (word_aligned_data_r[0:3] == A_CHAR_0);
got_a_d_r[1] <= `DLY (word_aligned_data_r[4:7] == A_CHAR_1);
got_a_d_r[2] <= `DLY (word_aligned_data_r[8:11] == A_CHAR_0);
got_a_d_r[3] <= `DLY (word_aligned_data_r[12:15] == A_CHAR_1);
end
always @(posedge USER_CLK)
begin
GOT_A[0] <= `DLY rx_pe_control_r[0] & (got_a_d_r[0:1] == 2'b11);
GOT_A[1] <= `DLY rx_pe_control_r[1] & (got_a_d_r[2:3] == 2'b11);
end
//_______________________Verification symbol decode__________________________
// This flow stores the decode of a Comma and SPA Data byte combination from the
// previous cycle. It is used along with decodes for SPA data in the current
// cycle to determine whether an SPA sequence was received.
always @(posedge USER_CLK)
begin
prev_beat_v_d_r[0] <= `DLY (word_aligned_data_r[0:3] == K_CHAR_0);
prev_beat_v_d_r[1] <= `DLY (word_aligned_data_r[4:7] == K_CHAR_1);
prev_beat_v_d_r[2] <= `DLY (word_aligned_data_r[8:11] == VER_DATA_0);
prev_beat_v_d_r[3] <= `DLY (word_aligned_data_r[12:15] == VER_DATA_1);
end
always @(posedge USER_CLK)
prev_beat_v_r <= `DLY (rx_pe_control_r == 2'b10) &
(prev_beat_v_d_r == 4'b1111);
// Indicate the SP sequence was received.
always @(posedge USER_CLK)
begin
rx_v_d_r[0] <= `DLY (word_aligned_data_r[0:3] == VER_DATA_0);
rx_v_d_r[1] <= `DLY (word_aligned_data_r[4:7] == VER_DATA_1);
rx_v_d_r[2] <= `DLY (word_aligned_data_r[8:11] == VER_DATA_0);
rx_v_d_r[3] <= `DLY (word_aligned_data_r[12:15] == VER_DATA_1);
end
assign got_v_c = prev_beat_v_r & (rx_pe_control_r == 2'b00) &
(rx_v_d_r == 4'b1111);
always @(posedge USER_CLK)
GOT_V <= `DLY got_v_c;
// Remember that the first V sequence has been detected.
initial
first_v_received_r = 1'b0;
always @(posedge USER_CLK)
if(RESET) first_v_received_r <= `DLY 1'b0;
else if(got_v_c) first_v_received_r <= `DLY 1'b1;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFXBP_LP_V
`define SKY130_FD_SC_LP__DFXBP_LP_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog wrapper for dfxbp with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dfxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfxbp_lp (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfxbp_lp (
Q ,
Q_N,
CLK,
D
);
output Q ;
output Q_N;
input CLK;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFXBP_LP_V
|
/*
* Copyright (c) 2015-2017 The Ultiparc Project. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* System fabric (version 2)
*/
`include "common.vh"
`include "ocp_const.vh"
/* Master ports switch */
module fabric2_mswitch #(
parameter PORTNO_WIDTH = 11
)
(
/* Destination port select */
i_portno,
/* OCP interface: instructions/data (master) */
i_ID_MAddr, i_ID_MCmd, i_ID_MData, i_ID_MByteEn, o_ID_SCmdAccept, o_ID_SData, o_ID_SResp,
/* OCP interface: Port 0 (slave) */
o_P0_MAddr, o_P0_MCmd, o_P0_MData, o_P0_MByteEn, i_P0_SCmdAccept, i_P0_SData, i_P0_SResp,
/* OCP interface: Port 1 (slave) */
o_P1_MAddr, o_P1_MCmd, o_P1_MData, o_P1_MByteEn, i_P1_SCmdAccept, i_P1_SData, i_P1_SResp,
/* OCP interface: Port 2 (slave) */
o_P2_MAddr, o_P2_MCmd, o_P2_MData, o_P2_MByteEn, i_P2_SCmdAccept, i_P2_SData, i_P2_SResp,
/* OCP interface: Port 3 (slave) */
o_P3_MAddr, o_P3_MCmd, o_P3_MData, o_P3_MByteEn, i_P3_SCmdAccept, i_P3_SData, i_P3_SResp,
/* OCP interface: Port 4 (slave) */
o_P4_MAddr, o_P4_MCmd, o_P4_MData, o_P4_MByteEn, i_P4_SCmdAccept, i_P4_SData, i_P4_SResp
);
/* Destination port select */
input wire [PORTNO_WIDTH-1:0] i_portno;
/* OCP interface: instructions/data (master) */
input wire [`ADDR_WIDTH-1:0] i_ID_MAddr;
input wire [2:0] i_ID_MCmd;
input wire [`DATA_WIDTH-1:0] i_ID_MData;
input wire [`BEN_WIDTH-1:0] i_ID_MByteEn;
output reg o_ID_SCmdAccept;
output reg [`DATA_WIDTH-1:0] o_ID_SData;
output reg [1:0] o_ID_SResp;
/* OCP interface: Port 0 (slave) */
output reg [`ADDR_WIDTH-1:0] o_P0_MAddr;
output reg [2:0] o_P0_MCmd;
output reg [`DATA_WIDTH-1:0] o_P0_MData;
output reg [`BEN_WIDTH-1:0] o_P0_MByteEn;
input wire i_P0_SCmdAccept;
input wire [`DATA_WIDTH-1:0] i_P0_SData;
input wire [1:0] i_P0_SResp;
/* OCP interface: Port 1 (slave) */
output reg [`ADDR_WIDTH-1:0] o_P1_MAddr;
output reg [2:0] o_P1_MCmd;
output reg [`DATA_WIDTH-1:0] o_P1_MData;
output reg [`BEN_WIDTH-1:0] o_P1_MByteEn;
input wire i_P1_SCmdAccept;
input wire [`DATA_WIDTH-1:0] i_P1_SData;
input wire [1:0] i_P1_SResp;
/* OCP interface: Port 2 (slave) */
output reg [`ADDR_WIDTH-1:0] o_P2_MAddr;
output reg [2:0] o_P2_MCmd;
output reg [`DATA_WIDTH-1:0] o_P2_MData;
output reg [`BEN_WIDTH-1:0] o_P2_MByteEn;
input wire i_P2_SCmdAccept;
input wire [`DATA_WIDTH-1:0] i_P2_SData;
input wire [1:0] i_P2_SResp;
/* OCP interface: Port 3 (slave) */
output reg [`ADDR_WIDTH-1:0] o_P3_MAddr;
output reg [2:0] o_P3_MCmd;
output reg [`DATA_WIDTH-1:0] o_P3_MData;
output reg [`BEN_WIDTH-1:0] o_P3_MByteEn;
input wire i_P3_SCmdAccept;
input wire [`DATA_WIDTH-1:0] i_P3_SData;
input wire [1:0] i_P3_SResp;
/* OCP interface: Port 4 (slave) */
output reg [`ADDR_WIDTH-1:0] o_P4_MAddr;
output reg [2:0] o_P4_MCmd;
output reg [`DATA_WIDTH-1:0] o_P4_MData;
output reg [`BEN_WIDTH-1:0] o_P4_MByteEn;
input wire i_P4_SCmdAccept;
input wire [`DATA_WIDTH-1:0] i_P4_SData;
input wire [1:0] i_P4_SResp;
always @(*)
begin
o_ID_SCmdAccept = 1'b0;
o_ID_SData = { (`DATA_WIDTH){1'b0} };
o_ID_SResp = 2'b00;
o_P0_MAddr = { (`ADDR_WIDTH){1'b0} };
o_P0_MCmd = 3'b000;
o_P0_MData = { (`DATA_WIDTH){1'b0} };
o_P0_MByteEn = { (`BEN_WIDTH){1'b0} };
o_P1_MAddr = { (`ADDR_WIDTH){1'b0} };
o_P1_MCmd = 3'b000;
o_P1_MData = { (`DATA_WIDTH){1'b0} };
o_P1_MByteEn = { (`BEN_WIDTH){1'b0} };
o_P2_MAddr = { (`ADDR_WIDTH){1'b0} };
o_P2_MCmd = 3'b000;
o_P2_MData = { (`DATA_WIDTH){1'b0} };
o_P2_MByteEn = { (`BEN_WIDTH){1'b0} };
o_P3_MAddr = { (`ADDR_WIDTH){1'b0} };
o_P3_MCmd = 3'b000;
o_P3_MData = { (`DATA_WIDTH){1'b0} };
o_P3_MByteEn = { (`BEN_WIDTH){1'b0} };
o_P4_MAddr = { (`ADDR_WIDTH){1'b0} };
o_P4_MCmd = 3'b000;
o_P4_MData = { (`DATA_WIDTH){1'b0} };
o_P4_MByteEn = { (`BEN_WIDTH){1'b0} };
case(i_portno)
'd1: begin
o_P1_MAddr = i_ID_MAddr;
o_P1_MCmd = i_ID_MCmd;
o_P1_MData = i_ID_MData;
o_P1_MByteEn = i_ID_MByteEn;
o_ID_SCmdAccept = i_P1_SCmdAccept;
o_ID_SData = i_P1_SData;
o_ID_SResp = i_P1_SResp;
end
'd2: begin
o_P2_MAddr = i_ID_MAddr;
o_P2_MCmd = i_ID_MCmd;
o_P2_MData = i_ID_MData;
o_P2_MByteEn = i_ID_MByteEn;
o_ID_SCmdAccept = i_P2_SCmdAccept;
o_ID_SData = i_P2_SData;
o_ID_SResp = i_P2_SResp;
end
'd3: begin
o_P3_MAddr = i_ID_MAddr;
o_P3_MCmd = i_ID_MCmd;
o_P3_MData = i_ID_MData;
o_P3_MByteEn = i_ID_MByteEn;
o_ID_SCmdAccept = i_P3_SCmdAccept;
o_ID_SData = i_P3_SData;
o_ID_SResp = i_P3_SResp;
end
'd4: begin
o_P4_MAddr = i_ID_MAddr;
o_P4_MCmd = i_ID_MCmd;
o_P4_MData = i_ID_MData;
o_P4_MByteEn = i_ID_MByteEn;
o_ID_SCmdAccept = i_P4_SCmdAccept;
o_ID_SData = i_P4_SData;
o_ID_SResp = i_P4_SResp;
end
default: begin
o_P0_MAddr = i_ID_MAddr;
o_P0_MCmd = i_ID_MCmd;
o_P0_MData = i_ID_MData;
o_P0_MByteEn = i_ID_MByteEn;
o_ID_SCmdAccept = i_P0_SCmdAccept;
o_ID_SData = i_P0_SData;
o_ID_SResp = i_P0_SResp;
end
endcase
end
endmodule /* fabric2_mswitch */
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_exu_alu_16eql.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: sparc_exu_alu_16eql
// Description: Takes a 17 bit input and generates an active low output
// signifying that all 17 bits have the same value.
*/
module sparc_exu_alu_16eql (/*AUTOARG*/
// Outputs
equal,
// Inputs
in
) ;
input [16:0] in;
output equal;
wire [15:0] inxor;
wire [7:0] nor1;
wire [1:0] nand2;
assign inxor[0] = in[15] ^ in[14];
assign inxor[1] = in[14] ^ in[13];
assign inxor[2] = in[13] ^ in[12];
assign inxor[3] = in[12] ^ in[11];
assign inxor[4] = in[11] ^ in[10];
assign inxor[5] = in[10] ^ in[9];
assign inxor[6] = in[9] ^ in[8];
assign inxor[7] = in[8] ^ in[7];
assign inxor[8] = in[7] ^ in[6];
assign inxor[9] = in[6] ^ in[5];
assign inxor[10] = in[5] ^ in[4];
assign inxor[11] = in[4] ^ in[3];
assign inxor[12] = in[3] ^ in[2];
assign inxor[13] = in[2] ^ in[1];
assign inxor[14] = in[1] ^ in[0];
assign inxor[15] = in[16] ^ in[15];
assign nor1[0] = ~(inxor[15] | inxor[14]);
assign nor1[1] = ~(inxor[1] | inxor[0]);
assign nor1[2] = ~(inxor[3] | inxor[2]);
assign nor1[3] = ~(inxor[5] | inxor[4]);
assign nor1[4] = ~(inxor[7] | inxor[6]);
assign nor1[5] = ~(inxor[9] | inxor[8]);
assign nor1[6] = ~(inxor[11] | inxor[10]);
assign nor1[7] = ~(inxor[13] | inxor[12]);
assign nand2[0] = ~(nor1[1] & nor1[2] & nor1[3] & nor1[4]);
assign nand2[1] = ~(nor1[5] & nor1[6] & nor1[7] & nor1[0]);
assign equal = ~(nand2[1] | nand2[0]);
endmodule // sparc_exu_div_32eql
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
sys_rst,
sys_clk_p,
sys_clk_n,
uart_sin,
uart_sout,
ddr4_act_n,
ddr4_addr,
ddr4_ba,
ddr4_bg,
ddr4_ck_p,
ddr4_ck_n,
ddr4_cke,
ddr4_cs_n,
ddr4_dm_n,
ddr4_dq,
ddr4_dqs_p,
ddr4_dqs_n,
ddr4_odt,
ddr4_reset_n,
mdio_mdc,
mdio_mdio,
phy_clk_p,
phy_clk_n,
phy_rst_n,
phy_rx_p,
phy_rx_n,
phy_tx_p,
phy_tx_n,
fan_pwm,
gpio_bd,
iic_scl,
iic_sda,
hdmi_out_clk,
hdmi_hsync,
hdmi_vsync,
hdmi_data_e,
hdmi_data,
spdif);
input sys_rst;
input sys_clk_p;
input sys_clk_n;
input uart_sin;
output uart_sout;
output ddr4_act_n;
output [16:0] ddr4_addr;
output [ 1:0] ddr4_ba;
output [ 0:0] ddr4_bg;
output ddr4_ck_p;
output ddr4_ck_n;
output [ 0:0] ddr4_cke;
output [ 0:0] ddr4_cs_n;
inout [ 7:0] ddr4_dm_n;
inout [63:0] ddr4_dq;
inout [ 7:0] ddr4_dqs_p;
inout [ 7:0] ddr4_dqs_n;
output [ 0:0] ddr4_odt;
output ddr4_reset_n;
output mdio_mdc;
inout mdio_mdio;
input phy_clk_p;
input phy_clk_n;
output phy_rst_n;
input phy_rx_p;
input phy_rx_n;
output phy_tx_p;
output phy_tx_n;
output fan_pwm;
inout [16:0] gpio_bd;
inout iic_scl;
inout iic_sda;
output hdmi_out_clk;
output hdmi_hsync;
output hdmi_vsync;
output hdmi_data_e;
output [15:0] hdmi_data;
output spdif;
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
// default logic
assign fan_pwm = 1'b1;
// instantiations
ad_iobuf #(.DATA_WIDTH(17)) i_iobuf_bd (
.dio_t (gpio_t[16:0]),
.dio_i (gpio_o[16:0]),
.dio_o (gpio_i[16:0]),
.dio_p (gpio_bd));
system_wrapper i_system_wrapper (
.c0_ddr4_act_n (ddr4_act_n),
.c0_ddr4_adr (ddr4_addr),
.c0_ddr4_ba (ddr4_ba),
.c0_ddr4_bg (ddr4_bg),
.c0_ddr4_ck_c (ddr4_ck_n),
.c0_ddr4_ck_t (ddr4_ck_p),
.c0_ddr4_cke (ddr4_cke),
.c0_ddr4_cs_n (ddr4_cs_n),
.c0_ddr4_dm_n (ddr4_dm_n),
.c0_ddr4_dq (ddr4_dq),
.c0_ddr4_dqs_c (ddr4_dqs_n),
.c0_ddr4_dqs_t (ddr4_dqs_p),
.c0_ddr4_odt (ddr4_odt),
.c0_ddr4_reset_n (ddr4_reset_n),
.gpio0_i (gpio_i[31:0]),
.gpio0_o (gpio_o[31:0]),
.gpio0_t (gpio_t[31:0]),
.gpio1_i (gpio_i[63:32]),
.gpio1_o (gpio_o[63:32]),
.gpio1_t (gpio_t[63:32]),
.hdmi_16_data (hdmi_data),
.hdmi_16_data_e (hdmi_data_e),
.hdmi_16_hsync (hdmi_hsync),
.hdmi_16_vsync (hdmi_vsync),
.hdmi_24_data (),
.hdmi_24_data_e (),
.hdmi_24_hsync (),
.hdmi_24_vsync (),
.hdmi_36_data (),
.hdmi_36_data_e (),
.hdmi_36_hsync (),
.hdmi_36_vsync (),
.hdmi_out_clk (hdmi_out_clk),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.mb_intr_05 (1'b0),
.mb_intr_06 (1'b0),
.mb_intr_12 (1'b0),
.mb_intr_13 (1'b0),
.mb_intr_14 (1'b0),
.mb_intr_15 (1'b0),
.mdio_mdc (mdio_mdc),
.mdio_mdio_io (mdio_mdio),
.phy_clk_clk_n (phy_clk_n),
.phy_clk_clk_p (phy_clk_p),
.phy_rst_n (phy_rst_n),
.phy_sd (1'b1),
.sgmii_rxn (phy_rx_n),
.sgmii_rxp (phy_rx_p),
.sgmii_txn (phy_tx_n),
.sgmii_txp (phy_tx_p),
.spdif (spdif),
.sys_clk_clk_n (sys_clk_n),
.sys_clk_clk_p (sys_clk_p),
.sys_rst (sys_rst),
.uart_sin (uart_sin),
.uart_sout (uart_sout));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A21O_BEHAVIORAL_V
`define SKY130_FD_SC_LS__A21O_BEHAVIORAL_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a21o (
X ,
A1,
A2,
B1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X, and0_out, B1 );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A21O_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR4B_SYMBOL_V
`define SKY130_FD_SC_LS__OR4B_SYMBOL_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__or4b (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D_N,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR4B_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKBUF_4_V
`define SKY130_FD_SC_HD__CLKBUF_4_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog wrapper for clkbuf with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__clkbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__clkbuf_4 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__clkbuf_4 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__clkbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKBUF_4_V
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ram_128x8_dp_be.v
// Megafunction Name(s):
// altsyncram
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.1 Build 176 10/26/2005 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ram_128x8_dp_be (
address_a,
address_b,
byteena_a,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [2:0] address_a;
input [2:0] address_b;
input [15:0] byteena_a;
input clock_a;
input clock_b;
input [127:0] data_a;
input [127:0] data_b;
input wren_a;
input wren_b;
output [127:0] q_a;
output [127:0] q_b;
wire [127:0] sub_wire0;
wire [127:0] sub_wire1;
wire [127:0] q_a = sub_wire0[127:0];
wire [127:0] q_b = sub_wire1[127:0];
altsyncram altsyncram_component (
.wren_a (wren_a),
.clock0 (clock_a),
.wren_b (wren_b),
.clock1 (clock_b),
.byteena_a (byteena_a),
.address_a (address_a),
.address_b (address_b),
.data_a (data_a),
.data_b (data_b),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.clocken1 (1'b1),
.clocken0 (1'b1),
.rden_b (1'b1),
.byteena_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0));
defparam
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK1",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 8,
altsyncram_component.numwords_b = 8,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M4K",
altsyncram_component.widthad_a = 3,
altsyncram_component.widthad_b = 3,
altsyncram_component.width_a = 128,
altsyncram_component.width_b = 128,
altsyncram_component.width_byteena_a = 16,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "5"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "1024"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "128"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "128"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "128"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "128"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "8"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M4K"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "3"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "3"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "128"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "128"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: USED_PORT: address_a 0 0 3 0 INPUT NODEFVAL address_a[2..0]
// Retrieval info: USED_PORT: address_b 0 0 3 0 INPUT NODEFVAL address_b[2..0]
// Retrieval info: USED_PORT: byteena_a 0 0 16 0 INPUT VCC byteena_a[15..0]
// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT NODEFVAL clock_a
// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL clock_b
// Retrieval info: USED_PORT: data_a 0 0 128 0 INPUT NODEFVAL data_a[127..0]
// Retrieval info: USED_PORT: data_b 0 0 128 0 INPUT NODEFVAL data_b[127..0]
// Retrieval info: USED_PORT: q_a 0 0 128 0 OUTPUT NODEFVAL q_a[127..0]
// Retrieval info: USED_PORT: q_b 0 0 128 0 OUTPUT NODEFVAL q_b[127..0]
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b
// Retrieval info: CONNECT: @data_a 0 0 128 0 data_a 0 0 128 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 128 0 @q_a 0 0 128 0
// Retrieval info: CONNECT: q_b 0 0 128 0 @q_b 0 0 128 0
// Retrieval info: CONNECT: @address_a 0 0 3 0 address_a 0 0 3 0
// Retrieval info: CONNECT: @data_b 0 0 128 0 data_b 0 0 128 0
// Retrieval info: CONNECT: @address_b 0 0 3 0 address_b 0 0 3 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: @byteena_a 0 0 16 0 byteena_a 0 0 16 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_128x8_dp_be.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_128x8_dp_be.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_128x8_dp_be.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_128x8_dp_be.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_128x8_dp_be_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_128x8_dp_be_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_128x8_dp_be_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_128x8_dp_be_wave*.jpg FALSE
|
`timescale 1ns / 1ps
/*
* Simple Brainfuck CPU in Verilog.
* Copyright (C) 2011 Sergey Gridasov <[email protected]>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module Nexys2Top(
input CLK_IN,
input RESET_IN,
input UART_RX,
output UART_TX
);
wire CLK_MAIN, RESET;
wire [7:0] CIN, COUT;
wire CRDA, CACK, CWR, CRDY;
ClockManager #(
.DELAY(16)
) clock (
.CLK_IN(CLK_IN),
.RESET_IN(RESET_IN),
.CLK_MAIN(CLK_MAIN),
.RESET(RESET)
);
BrainfuckWrapper #(
.IA_WIDTH(12)
) wrap (
.CLK(CLK_MAIN),
.RESET(RESET),
.CIN(CIN),
.COUT(COUT),
.CRDA(CRDA),
.CACK(CACK),
.CWR(CWR),
.CRDY(CRDY)
);
UART uart (
.CLK(CLK_MAIN),
.RESET(RESET),
.TX(UART_TX),
.RX(UART_RX),
.IN(COUT),
.OUT(CIN),
.RDA(CRDA),
.ACK(CACK),
.RDY(CRDY),
.WR(CWR)
);
endmodule
|
`default_nettype none
/*
References:
https://eewiki.net/pages/viewpage.action?pageId=10125324
http://faculty.lasierra.edu/~ehwang/digitaldesign/public/projects/DE2/I2C/I2C.pdf
*/
module i2c_master(
input wire clk,
input wire reset,
input wire start,
input wire [7:0] nbytes_in,
input wire [6:0] addr_in,
input wire rw_in,
input wire [7:0] write_data,
output reg [7:0] read_data,
output reg tx_data_req,
output reg rx_data_ready,
inout wire sda_w,
output wire scl
);
//state parameters
localparam STATE_IDLE = 0;
localparam STATE_START = 1;
localparam STATE_ADDR = 2;
localparam STATE_RW = 3;
localparam STATE_ACK = 4;
localparam STATE_READ_ACK = 5;
localparam STATE_TX_DATA = 6;
localparam STATE_RX_DATA = 7;
localparam STATE_STOP = 8;
localparam READ = 1;
localparam WRITE = 0;
localparam ACK = 0;
reg [5:0] state;
reg [7:0] bit_count; //bit counter
//local buffers
reg [6:0] addr;
reg [7:0] data;
reg [7:0] nbytes;
reg rw;
reg scl_en = 0;
reg sda;
//i2c needs to float the sda line when it is high.
//so here I define sda_w which is the wire actually connected to the
// line to be z when sda (logical signal) is 1
assign sda_w = ((sda)==0) ? 1'b0 : 1'bz;
//clock
//scl is enabled whenever we are sending or receiving data.
// otherwise it is held at 1
//Note that I also ned to do an ACK check here on the negedge so that I am
// ready to respond on the next posedge below
assign scl = (scl_en == 0) ? 1'b1 : ~clk;
always @(negedge clk) begin
if (reset == 1) begin
scl_en <= 0;
end else begin
if ((state == STATE_IDLE) || (state == STATE_START) || (state == STATE_STOP)) begin
scl_en <= 0;
end
else begin
scl_en <= 1;
end
//I need to check the ack on the rising scl edge (which is the neg edge of clk)
if (state == STATE_ACK) begin
if (0) begin
state <= STATE_IDLE;
end
end
end
end
//FSM
always @(posedge clk) begin
if (reset == 1) begin
state <= STATE_IDLE;
sda <= 1;
bit_count <= 8'd0;
addr <= 0;
data <= 0;
nbytes <= 0;
rw <= 0;
tx_data_req <= 0;
rx_data_ready <= 0;
end //if reset
else begin
case(state)
STATE_IDLE: begin //idle
sda <= 1;
if (start) begin
state <= STATE_START;
end //if start
end
STATE_START: begin //start
state <= STATE_ADDR;
sda <= 0; //send start condition
//latch in all the values
addr <= addr_in;
nbytes <= nbytes_in;
rw <= rw_in;
if (rw_in == WRITE) begin
tx_data_req <= 1; //request the first byte of data
end
bit_count <= 6; //addr is only 7 bits long, not 8
end //state_start
STATE_ADDR: begin //send slave address
sda <= addr[bit_count];
if (bit_count == 0) begin
state <= STATE_RW;
end
else begin
bit_count <= bit_count - 1'b1;
end
end //state_addr
STATE_RW: begin //send R/W bit
sda <= rw;
state <= STATE_ACK;
end //state_rw
STATE_ACK: begin
//release the sda line and await ack
sda <= 1;
//Ack is checked on the next rising edge of scl (neg edge of clk)
//So I just assume that it is all ok and set the next state here
//if there is no ack then the state will be overwritten when it is checked
tx_data_req <= 0; //time is up. if the data isn't in tx by now it is too late!
//now we have to decide what to do next.
if (nbytes == 0) begin
//there is no data left to read/write
if (start == 1) begin
//repeat start condition
sda <= 1;
state <= STATE_START;
end else begin
//we are done
sda <= 1; //idle state is high
state <= STATE_STOP;
end //if start == 1
end else begin
//we have more data to read/write
if (rw == WRITE) begin
data <= write_data; //latch in the new data byte
bit_count <= 7; //8 data bits
state <= STATE_TX_DATA;
end else begin
// Read data
bit_count <= 7; //8 data bits
state <= STATE_RX_DATA;
end //if rw_buf == WRITE
end //if nbytes_buf == 0
end //state_ack
STATE_TX_DATA: begin
sda <= data[bit_count];
if (nbytes > 0) begin
tx_data_req <= 1; //if there are more bytes to write, then request the next one
end
if (bit_count == 0) begin
//byte transfer complete
state <= STATE_ACK;
nbytes <= nbytes - 1'b1;
end
else begin
bit_count <= bit_count - 1'b1;
end
end //state_tx_data
STATE_RX_DATA: begin
data[bit_count] <= sda_w;
if (bit_count == 0) begin
//byte transfer complete
state <= STATE_ACK;
read_data[7:1] <= data[7:1];
read_data[0] <= sda_w;
rx_data_ready <= 1;
nbytes <= nbytes - 1'b1;
end
else begin
bit_count <= bit_count - 1'b1;
rx_data_ready <= 0;
end
end //state_rx_data
STATE_STOP: begin
sda <= 1;
state <= STATE_IDLE;
end //state_stop
endcase
end //if reset (else)
end //always
endmodule
|
//
// Copyright (c) 2014 Jan Adelsbach <[email protected]>.
// All Rights Reserved.
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
`include "nova_defs.v"
module nova_io(pclk, prst,
io_inst, io_op, io_result, io_skip, io_busy, io_pulse,
bs_stb, bs_we, bs_adr, bs_dout, bs_din);
input pclk;
input prst;
input [0:15] io_inst;
input [0:15] io_op;
output reg [0:15] io_result;
output reg io_skip;
output io_busy;
input io_pulse;
output reg bs_stb;
output reg bs_we;
output reg [0:7] bs_adr;
output reg [0:15] bs_dout;
input [0:15] bs_din;
// Decode
wire [0:1] inst_acc;
wire [0:2] inst_transfer;
wire [0:1] inst_control;
wire [0:5] inst_device;
assign inst_acc = io_inst[`NOVA_IO_ACC];
assign inst_transfer = io_inst[`NOVA_IO_TRANSFER];
assign inst_control = io_inst[`NOVA_IO_CONTROL];
assign inst_device = io_inst[`NOVA_IO_DEVICE];
wire [0:1] w_register;
assign w_register = (inst_transfer == `NOVA_IO_TRANSFER_DIA |
inst_transfer == `NOVA_IO_TRANSFER_DOA) ? 2'b01 :
(inst_transfer == `NOVA_IO_TRANSFER_DIB |
inst_transfer == `NOVA_IO_TRANSFER_DOB) ? 2'b10 :
(inst_transfer == `NOVA_IO_TRANSFER_DIC |
inst_transfer == `NOVA_IO_TRANSFER_DOC) ? 2'b11 :
(inst_transfer == `NOVA_IO_TRANSFER_SKP |
inst_transfer == `NOVA_IO_TRANSFER_NIO) ? 2'b00 :
2'bxx;
reg [0:2] r_state;
reg [0:2] r_state_next;
localparam SIDLE = 3'b000;
localparam SWAIT = 3'b001;
localparam SREAD = 3'b010;
localparam SSKIP = 3'b011;
localparam SCNTR = 3'b100;
assign io_busy = (|r_state) | io_pulse;
always @(posedge pclk) begin
if(prst) begin
io_result <= 16'h0000;
io_skip <= 1'b0;
//io_busy <= 1'b0;
bs_stb <= 1'b0;
bs_we <= 1'b0;
bs_adr <= 8'h00;
bs_dout <= 16'h0000;
r_state <= SIDLE;
r_state_next <= SIDLE;
end
else begin
case(r_state)
SIDLE:
begin
if(io_pulse) begin
io_skip <= 1'b0;
bs_adr <= {inst_device, w_register};
if(io_inst[0:2] == 3'b011) begin
if(inst_transfer == `NOVA_IO_TRANSFER_DIA |
inst_transfer == `NOVA_IO_TRANSFER_DIB |
inst_transfer == `NOVA_IO_TRANSFER_DIC) begin
bs_stb <= 1'b1;
bs_we <= 1'b0;
r_state <= SWAIT;
r_state_next <= SREAD;
end
else if(inst_transfer == `NOVA_IO_TRANSFER_DOA |
inst_transfer == `NOVA_IO_TRANSFER_DOB |
inst_transfer == `NOVA_IO_TRANSFER_DOC |
inst_transfer == `NOVA_IO_TRANSFER_NIO) begin
bs_stb <= 1'b1;
bs_we <= 1'b1;
bs_dout <= io_op;
if(|inst_control &
inst_transfer != `NOVA_IO_TRANSFER_NIO) begin
r_state <= SCNTR;
end
else begin
r_state <= SWAIT;
r_state_next <= SIDLE;
end
end // if (inst_transfer == `NOVA_IO_TRANSFER_DOA |...
else if(inst_transfer == `NOVA_IO_TRANSFER_SKP) begin
bs_stb <= 1'b1;
bs_we <= 1'b0;
r_state <= SWAIT;
r_state_next <= SSKIP;
end
end // if (io_inst[0:2] == 3'b011)
end
end // case: SIDLE
SREAD: begin
// TODO handle io errors (maybe?)
io_result <= bs_din;
if(|inst_control) begin
bs_we <= 1'b1;
bs_stb <= 1'b1;
bs_adr <= {inst_device, 2'b00};
bs_dout <= {14'h00, inst_control};
r_state <= SWAIT;
r_state_next <= SIDLE;
end
else
r_state <= SIDLE;
end
SCNTR:
begin
bs_adr <= {inst_device, 2'b00};
bs_dout <= {14'h00, inst_control};
bs_we <= 1'b1;
r_state <= SWAIT;
r_state_next <= SIDLE;
end
SWAIT:
begin
bs_stb <= 1'b0;
r_state <= r_state_next;
end
SSKIP:
begin
case(inst_control)
2'b00:
io_skip <= bs_din[0];
2'b01:
io_skip <= ~bs_din[0];
2'b10:
io_skip <= bs_din[1];
2'b11:
io_skip <= ~bs_din[1];
endcase // case (inst_control)
r_state <= SIDLE;
end
endcase // case (r_state)
end
end
endmodule // nova_io
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* FPGA top-level module
*/
module fpga (
/*
* Clock: 125MHz
* Reset: Push button, active low
*/
input wire enet_clk_125m,
input wire c10_resetn,
/*
* GPIO
*/
input wire [3:0] user_pb,
input wire [2:0] user_dip,
output wire [3:0] user_led,
/*
* Ethernet: 1000BASE-T RGMII
*/
input wire enet_rx_clk,
input wire [3:0] enet_rx_d,
input wire enet_rx_dv,
output wire enet_tx_clk,
output wire [3:0] enet_tx_d,
output wire enet_tx_en,
output wire enet_resetn,
input wire enet_int
);
// Clock and reset
// Internal 125 MHz clock
wire clk_int;
wire rst_int;
wire pll_rst = ~c10_resetn;
wire pll_locked;
wire clk90_int;
altpll #(
.bandwidth_type("AUTO"),
.clk0_divide_by(1),
.clk0_duty_cycle(50),
.clk0_multiply_by(1),
.clk0_phase_shift("0"),
.clk1_divide_by(1),
.clk1_duty_cycle(50),
.clk1_multiply_by(1),
.clk1_phase_shift("2000"),
.compensate_clock("CLK0"),
.inclk0_input_frequency(8000),
.intended_device_family("Cyclone 10 LP"),
.operation_mode("NORMAL"),
.pll_type("AUTO"),
.port_activeclock("PORT_UNUSED"),
.port_areset("PORT_USED"),
.port_clkbad0("PORT_UNUSED"),
.port_clkbad1("PORT_UNUSED"),
.port_clkloss("PORT_UNUSED"),
.port_clkswitch("PORT_UNUSED"),
.port_configupdate("PORT_UNUSED"),
.port_fbin("PORT_UNUSED"),
.port_inclk0("PORT_USED"),
.port_inclk1("PORT_UNUSED"),
.port_locked("PORT_USED"),
.port_pfdena("PORT_UNUSED"),
.port_phasecounterselect("PORT_UNUSED"),
.port_phasedone("PORT_UNUSED"),
.port_phasestep("PORT_UNUSED"),
.port_phaseupdown("PORT_UNUSED"),
.port_pllena("PORT_UNUSED"),
.port_scanaclr("PORT_UNUSED"),
.port_scanclk("PORT_UNUSED"),
.port_scanclkena("PORT_UNUSED"),
.port_scandata("PORT_UNUSED"),
.port_scandataout("PORT_UNUSED"),
.port_scandone("PORT_UNUSED"),
.port_scanread("PORT_UNUSED"),
.port_scanwrite("PORT_UNUSED"),
.port_clk0("PORT_USED"),
.port_clk1("PORT_USED"),
.port_clk2("PORT_UNUSED"),
.port_clk3("PORT_UNUSED"),
.port_clk4("PORT_UNUSED"),
.port_clk5("PORT_UNUSED"),
.port_clkena0("PORT_UNUSED"),
.port_clkena1("PORT_UNUSED"),
.port_clkena2("PORT_UNUSED"),
.port_clkena3("PORT_UNUSED"),
.port_clkena4("PORT_UNUSED"),
.port_clkena5("PORT_UNUSED"),
.port_extclk0("PORT_UNUSED"),
.port_extclk1("PORT_UNUSED"),
.port_extclk2("PORT_UNUSED"),
.port_extclk3("PORT_UNUSED"),
.self_reset_on_loss_lock("ON"),
.width_clock(5)
)
altpll_component (
.areset(pll_rst),
.inclk({1'b0, enet_clk_125m}),
.clk({clk90_int, clk_int}),
.locked(pll_locked),
.activeclock(),
.clkbad(),
.clkena({6{1'b1}}),
.clkloss(),
.clkswitch(1'b0),
.configupdate(1'b0),
.enable0(),
.enable1(),
.extclk(),
.extclkena({4{1'b1}}),
.fbin(1'b1),
.fbmimicbidir(),
.fbout(),
.fref(),
.icdrclk(),
.pfdena(1'b1),
.phasecounterselect({4{1'b1}}),
.phasedone(),
.phasestep(1'b1),
.phaseupdown(1'b1),
.pllena(1'b1),
.scanaclr(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0),
.scandataout(),
.scandone(),
.scanread(1'b0),
.scanwrite(1'b0),
.sclkout0(),
.sclkout1(),
.vcooverrange(),
.vcounderrange()
);
sync_reset #(
.N(4)
)
sync_reset_inst (
.clk(clk_int),
.rst(~pll_locked),
.out(rst_int)
);
// GPIO
wire [3:0] btn_int;
wire [2:0] sw_int;
wire [3:0] led_int;
debounce_switch #(
.WIDTH(7),
.N(4),
.RATE(125000)
)
debounce_switch_inst (
.clk(clk_int),
.rst(rst_int),
.in({user_pb,
user_dip}),
.out({btn_int,
sw_int})
);
assign user_led = ~led_int;
fpga_core #(
.TARGET("ALTERA")
)
core_inst (
/*
* Clock: 125MHz
* Synchronous reset
*/
.clk(clk_int),
.clk90(clk90_int),
.rst(rst_int),
/*
* GPIO
*/
.btn(btn_int),
.sw(sw_int),
.led(led_int),
/*
* Ethernet: 1000BASE-T RGMII
*/
.phy_rx_clk(enet_rx_clk),
.phy_rxd(enet_rx_d),
.phy_rx_ctl(enet_rx_dv),
.phy_tx_clk(enet_tx_clk),
.phy_txd(enet_tx_d),
.phy_tx_ctl(enet_tx_en),
.phy_reset_n(enet_resetn),
.phy_int_n(enet_int)
);
endmodule
|
`default_nettype none
module execute_jump(
input wire iCLOCK,
input wire inRESET,
input wire iRESET_SYNC,
//Event CTRL
input wire iEVENT_HOLD,
input wire iEVENT_START,
input wire iEVENT_IRQ_FRONT2BACK,
input wire iEVENT_IRQ_BACK2FRONT,
input wire iEVENT_END,
//State
input wire iSTATE_NORMAL,
//Previous - PREDICT
input wire iPREV_VALID,
input wire iPREV_EX_BRANCH,
input wire iPREV_EX_SYS_REG,
input wire [31:0] iPREV_PC,
input wire iPREV_BRANCH_PREDICT_ENA,
input wire iPREV_BRANCH_PREDICT_HIT,
//Ignore Predict
input wire iPREV_BRANCH_NORMAL_JUMP_INST,
//BRANCH
input wire iPREV_BRANCH_PREDICT_MISS_VALID, //not need jump, but predict jump
input wire iPREV_BRANCH_PREDICT_ADDR_MISS_VALID, //need jump, but predict addr is diffelent
input wire iPREV_BRANCH_IB_VALID,
input wire [31:0] iPREV_BRANCH_ADDR,
//SYSREG JUMP
input wire iPREV_SYSREG_IDT_VALID,
input wire iPREV_SYSREG_PDT_VALID,
input wire iPREV_SYSREG_PSR_VALID,
input wire [31:0] iPREV_SYSREG_ADDR,
/*************************************
Next
*************************************/
//Next
input wire iNEXT_BUSY,
output wire oNEXT_PREDICT_ENA,
output wire oNEXT_PREDICT_HIT,
output wire oNEXT_JUMP_VALID,
output wire [31:0] oNEXT_JUMP_ADDR,
//Ignore Predict
output wire oNEXT_NORMAL_JUMP_INST,
//Kaind of Jump
output wire oNEXT_TYPE_BRANCH_VALID,
output wire oNEXT_TYPE_BRANCH_IB_VALID,
output wire oNEXT_TYPE_SYSREG_IDT_VALID,
output wire oNEXT_TYPE_SYSREG_PDT_VALID,
output wire oNEXT_TYPE_SYSREG_PSR_VALID
);
wire jump_condition = iPREV_BRANCH_PREDICT_MISS_VALID || iPREV_BRANCH_PREDICT_ADDR_MISS_VALID;// || iPREV_BRANCH_IB_VALID || iPREV_SYSREG_IDT_VALID || iPREV_SYSREG_PDT_VALID || iPREV_SYSREG_PSR_VALID;
reg b_predict_ena;
reg b_predict_hit;
reg b_jump_valid;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_predict_ena <= 1'b0;
b_predict_hit <= 1'b0;
b_jump_valid <= 1'b0;
end
else if(iRESET_SYNC || iEVENT_HOLD || iEVENT_END)begin
b_predict_ena <= 1'b0;
b_predict_hit <= 1'b0;
b_jump_valid <= 1'b0;
end
else begin
if(iSTATE_NORMAL)begin
if(!iNEXT_BUSY)begin
if(iPREV_VALID && iPREV_EX_BRANCH)begin// && (b_state == PL_STT_IDLE))begin
b_predict_ena <= iPREV_BRANCH_PREDICT_ENA;
b_predict_hit <= iPREV_BRANCH_PREDICT_HIT;
b_jump_valid <= jump_condition;
end
else begin
b_predict_ena <= 1'b0;
b_predict_hit <= 1'b0;
b_jump_valid <= 1'b0;
end
end
end
else begin
b_predict_ena <= 1'b0;
b_predict_hit <= 1'b0;
b_jump_valid <= 1'b0;
end
end
end
reg [31:0] b_jump_addr;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_jump_addr <= 32'h0;
end
else if(iRESET_SYNC || iEVENT_HOLD || iEVENT_END)begin
b_jump_addr <= 32'h0;
end
else begin
if(iSTATE_NORMAL)begin
if(!iNEXT_BUSY)begin
if(iPREV_VALID)begin
if(iPREV_EX_BRANCH)begin
if(iPREV_BRANCH_PREDICT_ADDR_MISS_VALID || iPREV_BRANCH_IB_VALID)begin
b_jump_addr <= iPREV_BRANCH_ADDR;
end
else if(iPREV_BRANCH_PREDICT_MISS_VALID)begin
b_jump_addr <= iPREV_PC;
end
end
else if(iPREV_EX_SYS_REG) begin
b_jump_addr <= iPREV_SYSREG_ADDR;
end
end
else begin
b_jump_addr <= 32'h0;
end
end
end
else begin
b_jump_addr <= 32'h0;
end
end
end
reg b_branch_normal_valid;
reg b_branch_ib_valid;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_branch_normal_valid <= 1'b0;
b_branch_ib_valid <= 1'b0;
end
else if(iRESET_SYNC || iEVENT_HOLD || iEVENT_END)begin
b_branch_normal_valid <= 1'b0;
b_branch_ib_valid <= 1'b0;
end
else begin
if(iSTATE_NORMAL)begin
if(!iNEXT_BUSY)begin
if(iPREV_VALID && iPREV_EX_BRANCH)begin// && (b_state == PL_STT_IDLE))begin
b_branch_normal_valid <= iPREV_BRANCH_PREDICT_MISS_VALID || iPREV_BRANCH_PREDICT_ADDR_MISS_VALID;
b_branch_ib_valid <= iPREV_BRANCH_IB_VALID;
end
else begin
b_branch_normal_valid <= 1'b0;
b_branch_ib_valid <= 1'b0;
end
end
end
else begin
b_branch_normal_valid <= 1'b0;
b_branch_ib_valid <= 1'b0;
end
end
end
reg b_branch_normal_jump_inst;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_branch_normal_jump_inst <= 1'b0;
end
else if(iRESET_SYNC || iEVENT_HOLD || iEVENT_END)begin
b_branch_normal_jump_inst <= 1'b0;
end
else begin
if(iSTATE_NORMAL)begin
if(!iNEXT_BUSY)begin
if(iPREV_VALID && iPREV_EX_BRANCH)begin// && (b_state == PL_STT_IDLE))begin
b_branch_normal_jump_inst <= iPREV_BRANCH_NORMAL_JUMP_INST;
end
else begin
b_branch_normal_jump_inst <= 1'b0;
end
end
end
else begin
b_branch_normal_jump_inst <= 1'b0;
end
end
end
reg b_sysreg_idt_valid;
reg b_sysreg_pdt_valid;
reg b_sysreg_psr_valid;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_sysreg_idt_valid <= 1'b0;
b_sysreg_pdt_valid <= 1'b0;
b_sysreg_psr_valid <= 1'b0;
end
else if(iRESET_SYNC || iEVENT_HOLD || iEVENT_END)begin
b_sysreg_idt_valid <= 1'b0;
b_sysreg_pdt_valid <= 1'b0;
b_sysreg_psr_valid <= 1'b0;
end
else begin
if(iSTATE_NORMAL)begin
if(!iNEXT_BUSY)begin
if(iPREV_VALID && iPREV_EX_SYS_REG)begin// && (b_state == PL_STT_IDLE))begin
b_sysreg_idt_valid <= iPREV_SYSREG_IDT_VALID;
b_sysreg_pdt_valid <= iPREV_SYSREG_PDT_VALID;
b_sysreg_psr_valid <= iPREV_SYSREG_PSR_VALID;
end
else begin
b_sysreg_idt_valid <= 1'b0;
b_sysreg_pdt_valid <= 1'b0;
b_sysreg_psr_valid <= 1'b0;
end
end
end
else begin
b_sysreg_idt_valid <= 1'b0;
b_sysreg_pdt_valid <= 1'b0;
b_sysreg_psr_valid <= 1'b0;
end
end
end
assign oNEXT_PREDICT_ENA = b_predict_ena;
assign oNEXT_PREDICT_HIT = b_predict_hit;
assign oNEXT_JUMP_VALID = b_jump_valid;
assign oNEXT_JUMP_ADDR = b_jump_addr;
assign oNEXT_NORMAL_JUMP_INST = b_branch_normal_jump_inst;
//Kaind of Jump
assign oNEXT_TYPE_BRANCH_VALID = b_branch_normal_valid;
assign oNEXT_TYPE_BRANCH_IB_VALID = b_branch_ib_valid;
assign oNEXT_TYPE_SYSREG_IDT_VALID = b_sysreg_idt_valid;
assign oNEXT_TYPE_SYSREG_PDT_VALID = b_sysreg_pdt_valid;
assign oNEXT_TYPE_SYSREG_PSR_VALID = b_sysreg_psr_valid;
endmodule // execute_jump
`default_nettype wire
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_GPIO_OVTV2_PP_BLACKBOX_V
`define SKY130_FD_IO__TOP_GPIO_OVTV2_PP_BLACKBOX_V
/**
* top_gpio_ovtv2: General Purpose I/0.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_gpio_ovtv2 (
OUT ,
OE_N ,
HLD_H_N ,
ENABLE_H ,
ENABLE_INP_H ,
ENABLE_VDDA_H ,
ENABLE_VDDIO ,
ENABLE_VSWITCH_H,
INP_DIS ,
VTRIP_SEL ,
HYS_TRIM ,
SLOW ,
SLEW_CTL ,
HLD_OVR ,
ANALOG_EN ,
ANALOG_SEL ,
ANALOG_POL ,
DM ,
IB_MODE_SEL ,
VINREF ,
PAD ,
PAD_A_NOESD_H ,
PAD_A_ESD_0_H ,
PAD_A_ESD_1_H ,
AMUXBUS_A ,
AMUXBUS_B ,
IN ,
IN_H ,
TIE_HI_ESD ,
TIE_LO_ESD ,
VDDIO ,
VDDIO_Q ,
VDDA ,
VCCD ,
VSWITCH ,
VCCHIB ,
VSSA ,
VSSD ,
VSSIO_Q ,
VSSIO
);
input OUT ;
input OE_N ;
input HLD_H_N ;
input ENABLE_H ;
input ENABLE_INP_H ;
input ENABLE_VDDA_H ;
input ENABLE_VDDIO ;
input ENABLE_VSWITCH_H;
input INP_DIS ;
input VTRIP_SEL ;
input HYS_TRIM ;
input SLOW ;
input [1:0] SLEW_CTL ;
input HLD_OVR ;
input ANALOG_EN ;
input ANALOG_SEL ;
input ANALOG_POL ;
input [2:0] DM ;
input [1:0] IB_MODE_SEL ;
input VINREF ;
inout PAD ;
inout PAD_A_NOESD_H ;
inout PAD_A_ESD_0_H ;
inout PAD_A_ESD_1_H ;
inout AMUXBUS_A ;
inout AMUXBUS_B ;
output IN ;
output IN_H ;
output TIE_HI_ESD ;
output TIE_LO_ESD ;
inout VDDIO ;
inout VDDIO_Q ;
inout VDDA ;
inout VCCD ;
inout VSWITCH ;
inout VCCHIB ;
inout VSSA ;
inout VSSD ;
inout VSSIO_Q ;
inout VSSIO ;
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_GPIO_OVTV2_PP_BLACKBOX_V
|
module SDivider(q,r,m,v);
output [31:0]q;
output [31:0]r;
input [31:0]m;
input [31:0]v;
// input [63:0]d;
wire [63:0] d;
wire [31:0] zeros;
assign zeros[31:0] = 0;
assign d[31:0] = v[31:0];
assign d[63:32] = zeros[31:0];
wire [31:0] saksham1, saksham2, saksham3, saksham4, saksham5, saksham6, saksham7, saksham8, saksham9, saksham10, saksham11, saksham12, saksham13, saksham14, saksham15, saksham16, saksham17, saksham18, saksham19, saksham20, saksham21, saksham22, saksham23, saksham24, saksham25, saksham26, saksham27, saksham28, saksham29, saksham30, saksham31, saksham32,saksham33;
wire [31:0]w1;
wire a;
wire [31:0]w2;
wire [31:0]w3;
wire [31:0]w4;
wire [63:0]w5;
wire [31:0]w6;
wire [31:0]s1;
wire [31:0]sum1;
wire [31:0]s2;
wire [31:0]sum2;
wire [31:0]s3;
wire [31:0]sum3;
wire [31:0]s4;
wire [31:0]sum4;
wire [31:0]s5;
wire [31:0]sum5;
wire [31:0]s6;
wire [31:0]sum6;
wire [31:0]s7;
wire [31:0]sum7;
wire [31:0]s8;
wire [31:0]sum8;
wire [31:0]s9;
wire [31:0]sum9;
wire [31:0]s10;
wire [31:0]sum10;
wire [31:0]s11;
wire [31:0]sum11;
wire [31:0]s12;
wire [31:0]sum12;
wire [31:0]s13;
wire [31:0]sum13;
wire [31:0]s14;
wire [31:0]sum14;
wire [31:0]s15;
wire [31:0]sum15;
wire [31:0]s16;
wire [31:0]sum16;
wire [31:0]s17;
wire [31:0]sum17;
wire [31:0]s18;
wire [31:0]sum18;
wire [31:0]s19;
wire [31:0]sum19;
wire [31:0]s20;
wire [31:0]sum20;
wire [31:0]s21;
wire [31:0]sum21;
wire [31:0]s22;
wire [31:0]sum22;
wire [31:0]s23;
wire [31:0]sum23;
wire [31:0]s24;
wire [31:0]sum24;
wire [31:0]s25;
wire [31:0]sum25;
wire [31:0]s26;
wire [31:0]sum26;
wire [31:0]s27;
wire [31:0]sum27;
wire [31:0]s28;
wire [31:0]sum28;
wire [31:0]s29;
wire [31:0]sum29;
wire [31:0]s30;
wire [31:0]sum30;
wire [31:0]s31;
wire [31:0]sum31;
wire [31:0]s32;
wire [31:0]sum32;
wire [31:0]s33;
wire [31:0]sum33;
wire [31:0]sum34;
wire s34;
wire [32:0]q1;
wire [31:0]r1;
wire [32:0]w7;
wire [32:0]w8;
wire [31:0]w9;
wire [31:0]w10;
//converting divisor into normalised form//
xor(w1[31],m[31],m[31]);
xor(w1[30],m[31],m[30]);
xor(w1[29],m[31],m[29]);
xor(w1[28],m[31],m[28]);
xor(w1[27],m[31],m[27]);
xor(w1[26],m[31],m[26]);
xor(w1[25],m[31],m[25]);
xor(w1[24],m[31],m[24]);
xor(w1[23],m[31],m[23]);
xor(w1[22],m[31],m[22]);
xor(w1[21],m[31],m[21]);
xor(w1[20],m[31],m[20]);
xor(w1[19],m[31],m[19]);
xor(w1[18],m[31],m[18]);
xor(w1[17],m[31],m[17]);
xor(w1[16],m[31],m[16]);
xor(w1[15],m[31],m[15]);
xor(w1[14],m[31],m[14]);
xor(w1[13],m[31],m[13]);
xor(w1[12],m[31],m[12]);
xor(w1[11],m[31],m[11]);
xor(w1[10],m[31],m[10]);
xor(w1[9],m[31],m[9]);
xor(w1[8],m[31],m[8]);
xor(w1[7],m[31],m[7]);
xor(w1[6],m[31],m[6]);
xor(w1[5],m[31],m[5]);
xor(w1[4],m[31],m[4]);
xor(w1[3],m[31],m[3]);
xor(w1[2],m[31],m[2]);
xor(w1[1],m[31],m[1]);
xor(w1[0],m[31],m[0]);
//not n6[31:0](r,~w1);
halfadd hd1(w2[0],w3[0],w1[0],m[31]);
halfadd hd2(w2[1],w3[1],w1[1],w3[0]);
halfadd hd3(w2[2],w3[2],w1[2],w3[1]);
halfadd hd4(w2[3],w3[3],w1[3],w3[2]);
halfadd hd5(w2[4],w3[4],w1[4],w3[3]);
halfadd hd6(w2[5],w3[5],w1[5],w3[4]);
halfadd hd7(w2[6],w3[6],w1[6],w3[5]);
halfadd hd8(w2[7],w3[7],w1[7],w3[6]);
halfadd hd9(w2[8],w3[8],w1[8],w3[7]);
halfadd hd10(w2[9],w3[9],w1[9],w3[8]);
halfadd hd11(w2[10],w3[10],w1[10],w3[9]);
halfadd hd12(w2[11],w3[11],w1[11],w3[10]);
halfadd hd13(w2[12],w3[12],w1[12],w3[11]);
halfadd hd14(w2[13],w3[13],w1[13],w3[12]);
halfadd hd15(w2[14],w3[14],w1[14],w3[13]);
halfadd hd16(w2[15],w3[15],w1[15],w3[14]);
halfadd hd17(w2[16],w3[16],w1[16],w3[15]);
halfadd hd18(w2[17],w3[17],w1[17],w3[16]);
halfadd hd19(w2[18],w3[18],w1[18],w3[17]);
halfadd hd20(w2[19],w3[19],w1[19],w3[18]);
halfadd hd21(w2[20],w3[20],w1[20],w3[19]);
halfadd hd22(w2[21],w3[21],w1[21],w3[20]);
halfadd hd23(w2[22],w3[22],w1[22],w3[21]);
halfadd hd24(w2[23],w3[23],w1[23],w3[22]);
halfadd hd25(w2[24],w3[24],w1[24],w3[23]);
halfadd hd26(w2[25],w3[25],w1[25],w3[24]);
halfadd hd27(w2[26],w3[26],w1[26],w3[25]);
halfadd hd28(w2[27],w3[27],w1[27],w3[26]);
halfadd hd29(w2[28],w3[28],w1[28],w3[27]);
halfadd hd30(w2[29],w3[29],w1[29],w3[28]);
halfadd hd31(w2[30],w3[30],w1[30],w3[29]);
halfadd hd32(w2[31],w3[31],w1[31],w3[30]);
//not n6[31:0](r,~w2);
//converting dividend into normalised form//
xor(w4[31],d[31],d[31]);
xor(w4[30],d[31],d[30]);
xor(w4[29],d[31],d[29]);
xor(w4[28],d[31],d[28]);
xor(w4[27],d[31],d[27]);
xor(w4[26],d[31],d[26]);
xor(w4[25],d[31],d[25]);
xor(w4[24],d[31],d[24]);
xor(w4[23],d[31],d[23]);
xor(w4[22],d[31],d[22]);
xor(w4[21],d[31],d[21]);
xor(w4[20],d[31],d[20]);
xor(w4[19],d[31],d[19]);
xor(w4[18],d[31],d[18]);
xor(w4[17],d[31],d[17]);
xor(w4[16],d[31],d[16]);
xor(w4[15],d[31],d[15]);
xor(w4[14],d[31],d[14]);
xor(w4[13],d[31],d[13]);
xor(w4[12],d[31],d[12]);
xor(w4[11],d[31],d[11]);
xor(w4[10],d[31],d[10]);
xor(w4[9],d[31],d[9]);
xor(w4[8],d[31],d[8]);
xor(w4[7],d[31],d[7]);
xor(w4[6],d[31],d[6]);
xor(w4[5],d[31],d[5]);
xor(w4[4],d[31],d[4]);
xor(w4[3],d[31],d[3]);
xor(w4[2],d[31],d[2]);
xor(w4[1],d[31],d[1]);
xor(w4[0],d[31],d[0]);
//not n6[31:0](r,~w4);
halfadd h1(w5[0],w6[0],w4[0],d[31]);
halfadd h2(w5[1],w6[1],w4[1],w6[0]);
halfadd h3(w5[2],w6[2],w4[2],w6[1]);
halfadd h4(w5[3],w6[3],w4[3],w6[2]);
halfadd h5(w5[4],w6[4],w4[4],w6[3]);
halfadd h6(w5[5],w6[5],w4[5],w6[4]);
halfadd h7(w5[6],w6[6],w4[6],w6[5]);
halfadd h8(w5[7],w6[7],w4[7],w6[6]);
halfadd h9(w5[8],w6[8],w4[8],w6[7]);
halfadd h10(w5[9],w6[9],w4[9],w6[8]);
halfadd h11(w5[10],w6[10],w4[10],w6[9]);
halfadd h12(w5[11],w6[11],w4[11],w6[10]);
halfadd h13(w5[12],w6[12],w4[12],w6[11]);
halfadd h14(w5[13],w6[13],w4[13],w6[12]);
halfadd h15(w5[14],w6[14],w4[14],w6[13]);
halfadd h16(w5[15],w6[15],w4[15],w6[14]);
halfadd h17(w5[16],w6[16],w4[16],w6[15]);
halfadd h18(w5[17],w6[17],w4[17],w6[16]);
halfadd h19(w5[18],w6[18],w4[18],w6[17]);
halfadd h20(w5[19],w6[19],w4[19],w6[18]);
halfadd h21(w5[20],w6[20],w4[20],w6[19]);
halfadd h22(w5[21],w6[21],w4[21],w6[20]);
halfadd h23(w5[22],w6[22],w4[22],w6[21]);
halfadd h24(w5[23],w6[23],w4[23],w6[22]);
halfadd h25(w5[24],w6[24],w4[24],w6[23]);
halfadd h26(w5[25],w6[25],w4[25],w3[24]);
halfadd h27(w5[26],w6[26],w4[26],w6[25]);
halfadd h28(w5[27],w6[27],w4[27],w6[26]);
halfadd h29(w5[28],w6[28],w4[28],w6[27]);
halfadd h30(w5[29],w6[29],w4[29],w6[28]);
halfadd h31(w5[30],w6[30],w4[30],w6[29]);
halfadd h32(w5[31],w6[31],w4[31],w6[30]);
//not n6[31:0](r,~w5[31:0]);
//determining sign of quotient and remainder by taking msb bits of divisor and dividend//
xor(a,d[31],m[31]);
//division process//
wire ghj1;
assign ghj1 = 1;
xor(s1[31],w2[31],ghj1);
xor(s1[30],w2[30],ghj1);
xor(s1[29],w2[29],ghj1);
xor(s1[28],w2[28],ghj1);
xor(s1[27],w2[27],ghj1);
xor(s1[26],w2[26],ghj1);
xor(s1[25],w2[25],ghj1);
xor(s1[24],w2[24],ghj1);
xor(s1[23],w2[23],ghj1);
xor(s1[22],w2[22],ghj1);
xor(s1[21],w2[21],ghj1);
xor(s1[20],w2[20],ghj1);
xor(s1[19],w2[19],ghj1);
xor(s1[18],w2[18],ghj1);
xor(s1[17],w2[17],ghj1);
xor(s1[16],w2[16],ghj1);
xor(s1[15],w2[15],ghj1);
xor(s1[14],w2[14],ghj1);
xor(s1[13],w2[13],ghj1);
xor(s1[12],w2[12],ghj1);
xor(s1[11],w2[11],ghj1);
xor(s1[10],w2[10],ghj1);
xor(s1[9],w2[9],ghj1);
xor(s1[8],w2[8],ghj1);
xor(s1[7],w2[7],ghj1);
xor(s1[6],w2[6],ghj1);
xor(s1[5],w2[5],ghj1);
xor(s1[4],w2[4],ghj1);
xor(s1[3],w2[3],ghj1);
xor(s1[2],w2[2],ghj1);
xor(s1[1],w2[1],ghj1);
xor(s1[0],w2[0],ghj1);
wire ghj;
assign ghj = 1;
wire [31:0] sehaj,rathore;
//assign sehaj = w5[63:32];
not n2[31:0](w5[63:32],~(32'b0));
assign rathore = s1[31:0];
fulladd32bit fa34(sum1,q1[32],w5[63:32],rathore,ghj);
//not n6(r[0],~q1[32]);
xor(s2[31],w2[31],q1[32]);
xor(s2[30],w2[30],q1[32]);
xor(s2[29],w2[29],q1[32]);
xor(s2[28],w2[28],q1[32]);
xor(s2[27],w2[27],q1[32]);
xor(s2[26],w2[26],q1[32]);
xor(s2[25],w2[25],q1[32]);
xor(s2[24],w2[24],q1[32]);
xor(s2[23],w2[23],q1[32]);
xor(s2[22],w2[22],q1[32]);
xor(s2[21],w2[21],q1[32]);
xor(s2[20],w2[20],q1[32]);
xor(s2[19],w2[19],q1[32]);
xor(s2[18],w2[18],q1[32]);
xor(s2[17],w2[17],q1[32]);
xor(s2[16],w2[16],q1[32]);
xor(s2[15],w2[15],q1[32]);
xor(s2[14],w2[14],q1[32]);
xor(s2[13],w2[13],q1[32]);
xor(s2[12],w2[12],q1[32]);
xor(s2[11],w2[11],q1[32]);
xor(s2[10],w2[10],q1[32]);
xor(s2[9],w2[9],q1[32]);
xor(s2[8],w2[8],q1[32]);
xor(s2[7],w2[7],q1[32]);
xor(s2[6],w2[6],q1[32]);
xor(s2[5],w2[5],q1[32]);
xor(s2[4],w2[4],q1[32]);
xor(s2[3],w2[3],q1[32]);
xor(s2[2],w2[2],q1[32]);
xor(s2[1],w2[1],q1[32]);
xor(s2[0],w2[0],q1[32]);
shifter sh1(saksham1,sum1,w5[31]);
fulladd32bit fa33(sum2,q1[31],saksham1,s2,q1[32]);
xor(s3[31],w2[31],q1[31]);
xor(s3[30],w2[30],q1[31]);
xor(s3[29],w2[29],q1[31]);
xor(s3[28],w2[28],q1[31]);
xor(s3[27],w2[27],q1[31]);
xor(s3[26],w2[26],q1[31]);
xor(s3[25],w2[25],q1[31]);
xor(s3[24],w2[24],q1[31]);
xor(s3[23],w2[23],q1[31]);
xor(s3[22],w2[22],q1[31]);
xor(s3[21],w2[21],q1[31]);
xor(s3[20],w2[20],q1[31]);
xor(s3[19],w2[19],q1[31]);
xor(s3[18],w2[18],q1[31]);
xor(s3[17],w2[17],q1[31]);
xor(s3[16],w2[16],q1[31]);
xor(s3[15],w2[15],q1[31]);
xor(s3[14],w2[14],q1[31]);
xor(s3[13],w2[13],q1[31]);
xor(s3[12],w2[12],q1[31]);
xor(s3[11],w2[11],q1[31]);
xor(s3[10],w2[10],q1[31]);
xor(s3[9],w2[9],q1[31]);
xor(s3[8],w2[8],q1[31]);
xor(s3[7],w2[7],q1[31]);
xor(s3[6],w2[6],q1[31]);
xor(s3[5],w2[5],q1[31]);
xor(s3[4],w2[4],q1[31]);
xor(s3[3],w2[3],q1[31]);
xor(s3[2],w2[2],q1[31]);
xor(s3[1],w2[1],q1[31]);
xor(s3[0],w2[0],q1[31]);
shifter sh2(saksham2,sum2,w5[30]);
fulladd32bit fa32(sum3,q1[30],saksham2,s3,q1[31]);
xor(s4[31],w2[31],q1[30]);
xor(s4[30],w2[30],q1[30]);
xor(s4[29],w2[29],q1[30]);
xor(s4[28],w2[28],q1[30]);
xor(s4[27],w2[27],q1[30]);
xor(s4[26],w2[26],q1[30]);
xor(s4[25],w2[25],q1[30]);
xor(s4[24],w2[24],q1[30]);
xor(s4[23],w2[23],q1[30]);
xor(s4[22],w2[22],q1[30]);
xor(s4[21],w2[21],q1[30]);
xor(s4[20],w2[20],q1[30]);
xor(s4[19],w2[19],q1[30]);
xor(s4[18],w2[18],q1[30]);
xor(s4[17],w2[17],q1[30]);
xor(s4[16],w2[16],q1[30]);
xor(s4[15],w2[15],q1[30]);
xor(s4[14],w2[14],q1[30]);
xor(s4[13],w2[13],q1[30]);
xor(s4[12],w2[12],q1[30]);
xor(s4[11],w2[11],q1[30]);
xor(s4[10],w2[10],q1[30]);
xor(s4[9],w2[9],q1[30]);
xor(s4[8],w2[8],q1[30]);
xor(s4[7],w2[7],q1[30]);
xor(s4[6],w2[6],q1[30]);
xor(s4[5],w2[5],q1[30]);
xor(s4[4],w2[4],q1[30]);
xor(s4[3],w2[3],q1[30]);
xor(s4[2],w2[2],q1[30]);
xor(s4[1],w2[1],q1[30]);
xor(s4[0],w2[0],q1[30]);
shifter sh3(saksham3,sum3,w5[29]);
fulladd32bit fa31(sum4,q1[29],saksham3,s4,q1[30]);
xor(s5[31],w2[31],q1[29]);
xor(s5[30],w2[30],q1[29]);
xor(s5[29],w2[29],q1[29]);
xor(s5[28],w2[28],q1[29]);
xor(s5[27],w2[27],q1[29]);
xor(s5[26],w2[26],q1[29]);
xor(s5[25],w2[25],q1[29]);
xor(s5[24],w2[24],q1[29]);
xor(s5[23],w2[23],q1[29]);
xor(s5[22],w2[22],q1[29]);
xor(s5[21],w2[21],q1[29]);
xor(s5[20],w2[20],q1[29]);
xor(s5[19],w2[19],q1[29]);
xor(s5[18],w2[18],q1[29]);
xor(s5[17],w2[17],q1[29]);
xor(s5[16],w2[16],q1[29]);
xor(s5[15],w2[15],q1[29]);
xor(s5[14],w2[14],q1[29]);
xor(s5[13],w2[13],q1[29]);
xor(s5[12],w2[12],q1[29]);
xor(s5[11],w2[11],q1[29]);
xor(s5[10],w2[10],q1[29]);
xor(s5[9],w2[9],q1[29]);
xor(s5[8],w2[8],q1[29]);
xor(s5[7],w2[7],q1[29]);
xor(s5[6],w2[6],q1[29]);
xor(s5[5],w2[5],q1[29]);
xor(s5[4],w2[4],q1[29]);
xor(s5[3],w2[3],q1[29]);
xor(s5[2],w2[2],q1[29]);
xor(s5[1],w2[1],q1[29]);
xor(s5[0],w2[0],q1[29]);
shifter sh4(saksham4,sum4,w5[28]);
fulladd32bit fa30(sum5,q1[28],saksham4,s5,q1[29]);
xor(s6[31],w2[31],q1[28]);
xor(s6[30],w2[30],q1[28]);
xor(s6[29],w2[29],q1[28]);
xor(s6[28],w2[28],q1[28]);
xor(s6[27],w2[27],q1[28]);
xor(s6[26],w2[26],q1[28]);
xor(s6[25],w2[25],q1[28]);
xor(s6[24],w2[24],q1[28]);
xor(s6[23],w2[23],q1[28]);
xor(s6[22],w2[22],q1[28]);
xor(s6[21],w2[21],q1[28]);
xor(s6[20],w2[20],q1[28]);
xor(s6[19],w2[19],q1[28]);
xor(s6[18],w2[18],q1[28]);
xor(s6[17],w2[17],q1[28]);
xor(s6[16],w2[16],q1[28]);
xor(s6[15],w2[15],q1[28]);
xor(s6[14],w2[14],q1[28]);
xor(s6[13],w2[13],q1[28]);
xor(s6[12],w2[12],q1[28]);
xor(s6[11],w2[11],q1[28]);
xor(s6[10],w2[10],q1[28]);
xor(s6[9],w2[9],q1[28]);
xor(s6[8],w2[8],q1[28]);
xor(s6[7],w2[7],q1[28]);
xor(s6[6],w2[6],q1[28]);
xor(s6[5],w2[5],q1[28]);
xor(s6[4],w2[4],q1[28]);
xor(s6[3],w2[3],q1[28]);
xor(s6[2],w2[2],q1[28]);
xor(s6[1],w2[1],q1[28]);
xor(s6[0],w2[0],q1[28]);
shifter sh5(saksham5,sum5,w5[27]);
fulladd32bit fa29(sum6,q1[27],saksham5,s6,q1[28]);
xor(s7[31],w2[31],q1[27]);
xor(s7[30],w2[30],q1[27]);
xor(s7[29],w2[29],q1[27]);
xor(s7[28],w2[28],q1[27]);
xor(s7[27],w2[27],q1[27]);
xor(s7[26],w2[26],q1[27]);
xor(s7[25],w2[25],q1[27]);
xor(s7[24],w2[24],q1[27]);
xor(s7[23],w2[23],q1[27]);
xor(s7[22],w2[22],q1[27]);
xor(s7[21],w2[21],q1[27]);
xor(s7[20],w2[20],q1[27]);
xor(s7[19],w2[19],q1[27]);
xor(s7[18],w2[18],q1[27]);
xor(s7[17],w2[17],q1[27]);
xor(s7[16],w2[16],q1[27]);
xor(s7[15],w2[15],q1[27]);
xor(s7[14],w2[14],q1[27]);
xor(s7[13],w2[13],q1[27]);
xor(s7[12],w2[12],q1[27]);
xor(s7[11],w2[11],q1[27]);
xor(s7[10],w2[10],q1[27]);
xor(s7[9],w2[9],q1[27]);
xor(s7[8],w2[8],q1[27]);
xor(s7[7],w2[7],q1[27]);
xor(s7[6],w2[6],q1[27]);
xor(s7[5],w2[5],q1[27]);
xor(s7[4],w2[4],q1[27]);
xor(s7[3],w2[3],q1[27]);
xor(s7[2],w2[2],q1[27]);
xor(s7[1],w2[1],q1[27]);
xor(s7[0],w2[0],q1[27]);
shifter sh6(saksham6,sum6,w5[26]);
fulladd32bit fa28(sum7,q1[26],saksham6,s7,q1[27]);
xor(s8[31],w2[31],q1[26]);
xor(s8[30],w2[30],q1[26]);
xor(s8[29],w2[29],q1[26]);
xor(s8[28],w2[28],q1[26]);
xor(s8[27],w2[27],q1[26]);
xor(s8[26],w2[26],q1[26]);
xor(s8[25],w2[25],q1[26]);
xor(s8[24],w2[24],q1[26]);
xor(s8[23],w2[23],q1[26]);
xor(s8[22],w2[22],q1[26]);
xor(s8[21],w2[21],q1[26]);
xor(s8[20],w2[20],q1[26]);
xor(s8[19],w2[19],q1[26]);
xor(s8[18],w2[18],q1[26]);
xor(s8[17],w2[17],q1[26]);
xor(s8[16],w2[16],q1[26]);
xor(s8[15],w2[15],q1[26]);
xor(s8[14],w2[14],q1[26]);
xor(s8[13],w2[13],q1[26]);
xor(s8[12],w2[12],q1[26]);
xor(s8[11],w2[11],q1[26]);
xor(s8[10],w2[10],q1[26]);
xor(s8[9],w2[9],q1[26]);
xor(s8[8],w2[8],q1[26]);
xor(s8[7],w2[7],q1[26]);
xor(s8[6],w2[6],q1[26]);
xor(s8[5],w2[5],q1[26]);
xor(s8[4],w2[4],q1[26]);
xor(s8[3],w2[3],q1[26]);
xor(s8[2],w2[2],q1[26]);
xor(s8[1],w2[1],q1[26]);
xor(s8[0],w2[0],q1[26]);
//not n4[31:0](r,~(s8));
shifter sh7(saksham7,sum7,w5[25]);
fulladd32bit fa27(sum8,q1[25],saksham7,s8,q1[26]);
//not n4[31:0](r,~(sum8));
xor(s9[31],w2[31],q1[25]);
xor(s9[30],w2[30],q1[25]);
xor(s9[29],w2[29],q1[25]);
xor(s9[28],w2[28],q1[25]);
xor(s9[27],w2[27],q1[25]);
xor(s9[26],w2[26],q1[25]);
xor(s9[25],w2[25],q1[25]);
xor(s9[24],w2[24],q1[25]);
xor(s9[23],w2[23],q1[25]);
xor(s9[22],w2[22],q1[25]);
xor(s9[21],w2[21],q1[25]);
xor(s9[20],w2[20],q1[25]);
xor(s9[19],w2[19],q1[25]);
xor(s9[18],w2[18],q1[25]);
xor(s9[17],w2[17],q1[25]);
xor(s9[16],w2[16],q1[25]);
xor(s9[15],w2[15],q1[25]);
xor(s9[14],w2[14],q1[25]);
xor(s9[13],w2[13],q1[25]);
xor(s9[12],w2[12],q1[25]);
xor(s9[11],w2[11],q1[25]);
xor(s9[10],w2[10],q1[25]);
xor(s9[9],w2[9],q1[25]);
xor(s9[8],w2[8],q1[25]);
xor(s9[7],w2[7],q1[25]);
xor(s9[6],w2[6],q1[25]);
xor(s9[5],w2[5],q1[25]);
xor(s9[4],w2[4],q1[25]);
xor(s9[3],w2[3],q1[25]);
xor(s9[2],w2[2],q1[25]);
xor(s9[1],w2[1],q1[25]);
xor(s9[0],w2[0],q1[25]);
shifter sh8(saksham8,sum8,w5[24]);
fulladd32bit fa26(sum9,q1[24],saksham8,s9,q1[25]);
xor(s10[31],w2[31],q1[24]);
xor(s10[30],w2[30],q1[24]);
xor(s10[29],w2[29],q1[24]);
xor(s10[28],w2[28],q1[24]);
xor(s10[27],w2[27],q1[24]);
xor(s10[26],w2[26],q1[24]);
xor(s10[25],w2[25],q1[24]);
xor(s10[24],w2[24],q1[24]);
xor(s10[23],w2[23],q1[24]);
xor(s10[22],w2[22],q1[24]);
xor(s10[21],w2[21],q1[24]);
xor(s10[20],w2[20],q1[24]);
xor(s10[19],w2[19],q1[24]);
xor(s10[18],w2[18],q1[24]);
xor(s10[17],w2[17],q1[24]);
xor(s10[16],w2[16],q1[24]);
xor(s10[15],w2[15],q1[24]);
xor(s10[14],w2[14],q1[24]);
xor(s10[13],w2[13],q1[24]);
xor(s10[12],w2[12],q1[24]);
xor(s10[11],w2[11],q1[24]);
xor(s10[10],w2[10],q1[24]);
xor(s10[9],w2[9],q1[24]);
xor(s10[8],w2[8],q1[24]);
xor(s10[7],w2[7],q1[24]);
xor(s10[6],w2[6],q1[24]);
xor(s10[5],w2[5],q1[24]);
xor(s10[4],w2[4],q1[24]);
xor(s10[3],w2[3],q1[24]);
xor(s10[2],w2[2],q1[24]);
xor(s10[1],w2[1],q1[24]);
xor(s10[0],w2[0],q1[24]);
shifter sh9(saksham9,sum9,w5[23]);
fulladd32bit fa25(sum10,q1[23],saksham9,s10,q1[24]);
xor(s11[31],w2[31],q1[23]);
xor(s11[30],w2[30],q1[23]);
xor(s11[29],w2[29],q1[23]);
xor(s11[28],w2[28],q1[23]);
xor(s11[27],w2[27],q1[23]);
xor(s11[26],w2[26],q1[23]);
xor(s11[25],w2[25],q1[23]);
xor(s11[24],w2[24],q1[23]);
xor(s11[23],w2[23],q1[23]);
xor(s11[22],w2[22],q1[23]);
xor(s11[21],w2[21],q1[23]);
xor(s11[20],w2[20],q1[23]);
xor(s11[19],w2[19],q1[23]);
xor(s11[18],w2[18],q1[23]);
xor(s11[17],w2[17],q1[23]);
xor(s11[16],w2[16],q1[23]);
xor(s11[15],w2[15],q1[23]);
xor(s11[14],w2[14],q1[23]);
xor(s11[13],w2[13],q1[23]);
xor(s11[12],w2[12],q1[23]);
xor(s11[11],w2[11],q1[23]);
xor(s11[10],w2[10],q1[23]);
xor(s11[9],w2[9],q1[23]);
xor(s11[8],w2[8],q1[23]);
xor(s11[7],w2[7],q1[23]);
xor(s11[6],w2[6],q1[23]);
xor(s11[5],w2[5],q1[23]);
xor(s11[4],w2[4],q1[23]);
xor(s11[3],w2[3],q1[23]);
xor(s11[2],w2[2],q1[23]);
xor(s11[1],w2[1],q1[23]);
xor(s11[0],w2[0],q1[23]);
shifter sh10(saksham10,sum10,w5[22]);
fulladd32bit fa24(sum11,q1[22],saksham10,s11,q1[23]);
xor(s12[31],w2[31],q1[22]);
xor(s12[30],w2[30],q1[22]);
xor(s12[29],w2[29],q1[22]);
xor(s12[28],w2[28],q1[22]);
xor(s12[27],w2[27],q1[22]);
xor(s12[26],w2[26],q1[22]);
xor(s12[25],w2[25],q1[22]);
xor(s12[24],w2[24],q1[22]);
xor(s12[23],w2[23],q1[22]);
xor(s12[22],w2[22],q1[22]);
xor(s12[21],w2[21],q1[22]);
xor(s12[20],w2[20],q1[22]);
xor(s12[19],w2[19],q1[22]);
xor(s12[18],w2[18],q1[22]);
xor(s12[17],w2[17],q1[22]);
xor(s12[16],w2[16],q1[22]);
xor(s12[15],w2[15],q1[22]);
xor(s12[14],w2[14],q1[22]);
xor(s12[13],w2[13],q1[22]);
xor(s12[12],w2[12],q1[22]);
xor(s12[11],w2[11],q1[22]);
xor(s12[10],w2[10],q1[22]);
xor(s12[9],w2[9],q1[22]);
xor(s12[8],w2[8],q1[22]);
xor(s12[7],w2[7],q1[22]);
xor(s12[6],w2[6],q1[22]);
xor(s12[5],w2[5],q1[22]);
xor(s12[4],w2[4],q1[22]);
xor(s12[3],w2[3],q1[22]);
xor(s12[2],w2[2],q1[22]);
xor(s12[1],w2[1],q1[22]);
xor(s12[0],w2[0],q1[22]);
shifter sh11(saksham11,sum11,w5[21]);
fulladd32bit fa23(sum12,q1[21],saksham11,s12,q1[22]);
xor(s13[31],w2[31],q1[21]);
xor(s13[30],w2[30],q1[21]);
xor(s13[29],w2[29],q1[21]);
xor(s13[28],w2[28],q1[21]);
xor(s13[27],w2[27],q1[21]);
xor(s13[26],w2[26],q1[21]);
xor(s13[25],w2[25],q1[21]);
xor(s13[24],w2[24],q1[21]);
xor(s13[23],w2[23],q1[21]);
xor(s13[22],w2[22],q1[21]);
xor(s13[21],w2[21],q1[21]);
xor(s13[20],w2[20],q1[21]);
xor(s13[19],w2[19],q1[21]);
xor(s13[18],w2[18],q1[21]);
xor(s13[17],w2[17],q1[21]);
xor(s13[16],w2[16],q1[21]);
xor(s13[15],w2[15],q1[21]);
xor(s13[14],w2[14],q1[21]);
xor(s13[13],w2[13],q1[21]);
xor(s13[12],w2[12],q1[21]);
xor(s13[11],w2[11],q1[21]);
xor(s13[10],w2[10],q1[21]);
xor(s13[9],w2[9],q1[21]);
xor(s13[8],w2[8],q1[21]);
xor(s13[7],w2[7],q1[21]);
xor(s13[6],w2[6],q1[21]);
xor(s13[5],w2[5],q1[21]);
xor(s13[4],w2[4],q1[21]);
xor(s13[3],w2[3],q1[21]);
xor(s13[2],w2[2],q1[21]);
xor(s13[1],w2[1],q1[21]);
xor(s13[0],w2[0],q1[21]);
shifter sh12(saksham12,sum12,w5[20]);
fulladd32bit fa22(sum13,q1[20],saksham12,s13,q1[21]);
xor(s14[31],w2[31],q1[20]);
xor(s14[30],w2[30],q1[20]);
xor(s14[29],w2[29],q1[20]);
xor(s14[28],w2[28],q1[20]);
xor(s14[27],w2[27],q1[20]);
xor(s14[26],w2[26],q1[20]);
xor(s14[25],w2[25],q1[20]);
xor(s14[24],w2[24],q1[20]);
xor(s14[23],w2[23],q1[20]);
xor(s14[22],w2[22],q1[20]);
xor(s14[21],w2[21],q1[20]);
xor(s14[20],w2[20],q1[20]);
xor(s14[19],w2[19],q1[20]);
xor(s14[18],w2[18],q1[20]);
xor(s14[17],w2[17],q1[20]);
xor(s14[16],w2[16],q1[20]);
xor(s14[15],w2[15],q1[20]);
xor(s14[14],w2[14],q1[20]);
xor(s14[13],w2[13],q1[20]);
xor(s14[12],w2[12],q1[20]);
xor(s14[11],w2[11],q1[20]);
xor(s14[10],w2[10],q1[20]);
xor(s14[9],w2[9],q1[20]);
xor(s14[8],w2[8],q1[20]);
xor(s14[7],w2[7],q1[20]);
xor(s14[6],w2[6],q1[20]);
xor(s14[5],w2[5],q1[20]);
xor(s14[4],w2[4],q1[20]);
xor(s14[3],w2[3],q1[20]);
xor(s14[2],w2[2],q1[20]);
xor(s14[1],w2[1],q1[20]);
xor(s14[0],w2[0],q1[20]);
shifter sh13(saksham13,sum13,w5[19]);
fulladd32bit fa21(sum14,q1[19],saksham13,s14,q1[20]);
xor(s15[31],w2[31],q1[19]);
xor(s15[30],w2[30],q1[19]);
xor(s15[29],w2[29],q1[19]);
xor(s15[28],w2[28],q1[19]);
xor(s15[27],w2[27],q1[19]);
xor(s15[26],w2[26],q1[19]);
xor(s15[25],w2[25],q1[19]);
xor(s15[24],w2[24],q1[19]);
xor(s15[23],w2[23],q1[19]);
xor(s15[22],w2[22],q1[19]);
xor(s15[21],w2[21],q1[19]);
xor(s15[20],w2[20],q1[19]);
xor(s15[19],w2[19],q1[19]);
xor(s15[18],w2[18],q1[19]);
xor(s15[17],w2[17],q1[19]);
xor(s15[16],w2[16],q1[19]);
xor(s15[15],w2[15],q1[19]);
xor(s15[14],w2[14],q1[19]);
xor(s15[13],w2[13],q1[19]);
xor(s15[12],w2[12],q1[19]);
xor(s15[11],w2[11],q1[19]);
xor(s15[10],w2[10],q1[19]);
xor(s15[9],w2[9],q1[19]);
xor(s15[8],w2[8],q1[19]);
xor(s15[7],w2[7],q1[19]);
xor(s15[6],w2[6],q1[19]);
xor(s15[5],w2[5],q1[19]);
xor(s15[4],w2[4],q1[19]);
xor(s15[3],w2[3],q1[19]);
xor(s15[2],w2[2],q1[19]);
xor(s15[1],w2[1],q1[19]);
xor(s15[0],w2[0],q1[19]);
shifter sh14(saksham14,sum14,w5[18]);
fulladd32bit fa20(sum15,q1[18],saksham14,s15,q1[19]);
xor(s16[31],w2[31],q1[18]);
xor(s16[30],w2[30],q1[18]);
xor(s16[29],w2[29],q1[18]);
xor(s16[28],w2[28],q1[18]);
xor(s16[27],w2[27],q1[18]);
xor(s16[26],w2[26],q1[18]);
xor(s16[25],w2[25],q1[18]);
xor(s16[24],w2[24],q1[18]);
xor(s16[23],w2[23],q1[18]);
xor(s16[22],w2[22],q1[18]);
xor(s16[21],w2[21],q1[18]);
xor(s16[20],w2[20],q1[18]);
xor(s16[19],w2[19],q1[18]);
xor(s16[18],w2[18],q1[18]);
xor(s16[17],w2[17],q1[18]);
xor(s16[16],w2[16],q1[18]);
xor(s16[15],w2[15],q1[18]);
xor(s16[14],w2[14],q1[18]);
xor(s16[13],w2[13],q1[18]);
xor(s16[12],w2[12],q1[18]);
xor(s16[11],w2[11],q1[18]);
xor(s16[10],w2[10],q1[18]);
xor(s16[9],w2[9],q1[18]);
xor(s16[8],w2[8],q1[18]);
xor(s16[7],w2[7],q1[18]);
xor(s16[6],w2[6],q1[18]);
xor(s16[5],w2[5],q1[18]);
xor(s16[4],w2[4],q1[18]);
xor(s16[3],w2[3],q1[18]);
xor(s16[2],w2[2],q1[18]);
xor(s16[1],w2[1],q1[18]);
xor(s16[0],w2[0],q1[18]);
shifter sh15(saksham15,sum15,w5[17]);
fulladd32bit fa19(sum16,q1[17],saksham15,s16,q1[18]);
xor(s17[31],w2[31],q1[17]);
xor(s17[30],w2[30],q1[17]);
xor(s17[29],w2[29],q1[17]);
xor(s17[28],w2[28],q1[17]);
xor(s17[27],w2[27],q1[17]);
xor(s17[26],w2[26],q1[17]);
xor(s17[25],w2[25],q1[17]);
xor(s17[24],w2[24],q1[17]);
xor(s17[23],w2[23],q1[17]);
xor(s17[22],w2[22],q1[17]);
xor(s17[21],w2[21],q1[17]);
xor(s17[20],w2[20],q1[17]);
xor(s17[19],w2[19],q1[17]);
xor(s17[18],w2[18],q1[17]);
xor(s17[17],w2[17],q1[17]);
xor(s17[16],w2[16],q1[17]);
xor(s17[15],w2[15],q1[17]);
xor(s17[14],w2[14],q1[17]);
xor(s17[13],w2[13],q1[17]);
xor(s17[12],w2[12],q1[17]);
xor(s17[11],w2[11],q1[17]);
xor(s17[10],w2[10],q1[17]);
xor(s17[9],w2[9],q1[17]);
xor(s17[8],w2[8],q1[17]);
xor(s17[7],w2[7],q1[17]);
xor(s17[6],w2[6],q1[17]);
xor(s17[5],w2[5],q1[17]);
xor(s17[4],w2[4],q1[17]);
xor(s17[3],w2[3],q1[17]);
xor(s17[2],w2[2],q1[17]);
xor(s17[1],w2[1],q1[17]);
xor(s17[0],w2[0],q1[17]);
shifter sh16(saksham16,sum16,w5[16]);
fulladd32bit fa18(sum17,q1[16],saksham16,s17,q1[17]);
xor(s18[31],w2[31],q1[16]);
xor(s18[30],w2[30],q1[16]);
xor(s18[29],w2[29],q1[16]);
xor(s18[28],w2[28],q1[16]);
xor(s18[27],w2[27],q1[16]);
xor(s18[26],w2[26],q1[16]);
xor(s18[25],w2[25],q1[16]);
xor(s18[24],w2[24],q1[16]);
xor(s18[23],w2[23],q1[16]);
xor(s18[22],w2[22],q1[16]);
xor(s18[21],w2[21],q1[16]);
xor(s18[20],w2[20],q1[16]);
xor(s18[19],w2[19],q1[16]);
xor(s18[18],w2[18],q1[16]);
xor(s18[17],w2[17],q1[16]);
xor(s18[16],w2[16],q1[16]);
xor(s18[15],w2[15],q1[16]);
xor(s18[14],w2[14],q1[16]);
xor(s18[13],w2[13],q1[16]);
xor(s18[12],w2[12],q1[16]);
xor(s18[11],w2[11],q1[16]);
xor(s18[10],w2[10],q1[16]);
xor(s18[9],w2[9],q1[16]);
xor(s18[8],w2[8],q1[16]);
xor(s18[7],w2[7],q1[16]);
xor(s18[6],w2[6],q1[16]);
xor(s18[5],w2[5],q1[16]);
xor(s18[4],w2[4],q1[16]);
xor(s18[3],w2[3],q1[16]);
xor(s18[2],w2[2],q1[16]);
xor(s18[1],w2[1],q1[16]);
xor(s18[0],w2[0],q1[16]);
shifter sh17(saksham17,sum17,w5[15]);
fulladd32bit fa17(sum18,q1[15],saksham17,s18,q1[16]);
xor(s19[31],w2[31],q1[15]);
xor(s19[30],w2[30],q1[15]);
xor(s19[29],w2[29],q1[15]);
xor(s19[28],w2[28],q1[15]);
xor(s19[27],w2[27],q1[15]);
xor(s19[26],w2[26],q1[15]);
xor(s19[25],w2[25],q1[15]);
xor(s19[24],w2[24],q1[15]);
xor(s19[23],w2[23],q1[15]);
xor(s19[22],w2[22],q1[15]);
xor(s19[21],w2[21],q1[15]);
xor(s19[20],w2[20],q1[15]);
xor(s19[19],w2[19],q1[15]);
xor(s19[18],w2[18],q1[15]);
xor(s19[17],w2[17],q1[15]);
xor(s19[16],w2[16],q1[15]);
xor(s19[15],w2[15],q1[15]);
xor(s19[14],w2[14],q1[15]);
xor(s19[13],w2[13],q1[15]);
xor(s19[12],w2[12],q1[15]);
xor(s19[11],w2[11],q1[15]);
xor(s19[10],w2[10],q1[15]);
xor(s19[9],w2[9],q1[15]);
xor(s19[8],w2[8],q1[15]);
xor(s19[7],w2[7],q1[15]);
xor(s19[6],w2[6],q1[15]);
xor(s19[5],w2[5],q1[15]);
xor(s19[4],w2[4],q1[15]);
xor(s19[3],w2[3],q1[15]);
xor(s19[2],w2[2],q1[15]);
xor(s19[1],w2[1],q1[15]);
xor(s19[0],w2[0],q1[15]);
shifter sh18(saksham18,sum18,w5[14]);
fulladd32bit fa16(sum19,q1[14],saksham18,s19,q1[15]);
xor(s20[31],w2[31],q1[14]);
xor(s20[30],w2[30],q1[14]);
xor(s20[29],w2[29],q1[14]);
xor(s20[28],w2[28],q1[14]);
xor(s20[27],w2[27],q1[14]);
xor(s20[26],w2[26],q1[14]);
xor(s20[25],w2[25],q1[14]);
xor(s20[24],w2[24],q1[14]);
xor(s20[23],w2[23],q1[14]);
xor(s20[22],w2[22],q1[14]);
xor(s20[21],w2[21],q1[14]);
xor(s20[20],w2[20],q1[14]);
xor(s20[19],w2[19],q1[14]);
xor(s20[18],w2[18],q1[14]);
xor(s20[17],w2[17],q1[14]);
xor(s20[16],w2[16],q1[14]);
xor(s20[15],w2[15],q1[14]);
xor(s20[14],w2[14],q1[14]);
xor(s20[13],w2[13],q1[14]);
xor(s20[12],w2[12],q1[14]);
xor(s20[11],w2[11],q1[14]);
xor(s20[10],w2[10],q1[14]);
xor(s20[9],w2[9],q1[14]);
xor(s20[8],w2[8],q1[14]);
xor(s20[7],w2[7],q1[14]);
xor(s20[6],w2[6],q1[14]);
xor(s20[5],w2[5],q1[14]);
xor(s20[4],w2[4],q1[14]);
xor(s20[3],w2[3],q1[14]);
xor(s20[2],w2[2],q1[14]);
xor(s20[1],w2[1],q1[14]);
xor(s20[0],w2[0],q1[14]);
shifter sh19(saksham19,sum19,w5[13]);
fulladd32bit fa15(sum20,q1[13],saksham19,s20,q1[14]);
xor(s21[31],w2[31],q1[13]);
xor(s21[30],w2[30],q1[13]);
xor(s21[29],w2[29],q1[13]);
xor(s21[28],w2[28],q1[13]);
xor(s21[27],w2[27],q1[13]);
xor(s21[26],w2[26],q1[13]);
xor(s21[25],w2[25],q1[13]);
xor(s21[24],w2[24],q1[13]);
xor(s21[23],w2[23],q1[13]);
xor(s21[22],w2[22],q1[13]);
xor(s21[21],w2[21],q1[13]);
xor(s21[20],w2[20],q1[13]);
xor(s21[19],w2[19],q1[13]);
xor(s21[18],w2[18],q1[13]);
xor(s21[17],w2[17],q1[13]);
xor(s21[16],w2[16],q1[13]);
xor(s21[15],w2[15],q1[13]);
xor(s21[14],w2[14],q1[13]);
xor(s21[13],w2[13],q1[13]);
xor(s21[12],w2[12],q1[13]);
xor(s21[11],w2[11],q1[13]);
xor(s21[10],w2[10],q1[13]);
xor(s21[9],w2[9],q1[13]);
xor(s21[8],w2[8],q1[13]);
xor(s21[7],w2[7],q1[13]);
xor(s21[6],w2[6],q1[13]);
xor(s21[5],w2[5],q1[13]);
xor(s21[4],w2[4],q1[13]);
xor(s21[3],w2[3],q1[13]);
xor(s21[2],w2[2],q1[13]);
xor(s21[1],w2[1],q1[13]);
xor(s21[0],w2[0],q1[13]);
shifter sh20(saksham20,sum20,w5[12]);
fulladd32bit fa14(sum21,q1[12],saksham20,s21,q1[13]);
xor(s22[31],w2[31],q1[12]);
xor(s22[30],w2[30],q1[12]);
xor(s22[29],w2[29],q1[12]);
xor(s22[28],w2[28],q1[12]);
xor(s22[27],w2[27],q1[12]);
xor(s22[26],w2[26],q1[12]);
xor(s22[25],w2[25],q1[12]);
xor(s22[24],w2[24],q1[12]);
xor(s22[23],w2[23],q1[12]);
xor(s22[22],w2[22],q1[12]);
xor(s22[21],w2[21],q1[12]);
xor(s22[20],w2[20],q1[12]);
xor(s22[19],w2[19],q1[12]);
xor(s22[18],w2[18],q1[12]);
xor(s22[17],w2[17],q1[12]);
xor(s22[16],w2[16],q1[12]);
xor(s22[15],w2[15],q1[12]);
xor(s22[14],w2[14],q1[12]);
xor(s22[13],w2[13],q1[12]);
xor(s22[12],w2[12],q1[12]);
xor(s22[11],w2[11],q1[12]);
xor(s22[10],w2[10],q1[12]);
xor(s22[9],w2[9],q1[12]);
xor(s22[8],w2[8],q1[12]);
xor(s22[7],w2[7],q1[12]);
xor(s22[6],w2[6],q1[12]);
xor(s22[5],w2[5],q1[12]);
xor(s22[4],w2[4],q1[12]);
xor(s22[3],w2[3],q1[12]);
xor(s22[2],w2[2],q1[12]);
xor(s22[1],w2[1],q1[12]);
xor(s22[0],w2[0],q1[12]);
shifter sh21(saksham21,sum21,w5[11]);
fulladd32bit fa13(sum22,q1[11],saksham21,s22,q1[12]);
xor(s23[31],w2[31],q1[11]);
xor(s23[30],w2[30],q1[11]);
xor(s23[29],w2[29],q1[11]);
xor(s23[28],w2[28],q1[11]);
xor(s23[27],w2[27],q1[11]);
xor(s23[26],w2[26],q1[11]);
xor(s23[25],w2[25],q1[11]);
xor(s23[24],w2[24],q1[11]);
xor(s23[23],w2[23],q1[11]);
xor(s23[22],w2[22],q1[11]);
xor(s23[21],w2[21],q1[11]);
xor(s23[20],w2[20],q1[11]);
xor(s23[19],w2[19],q1[11]);
xor(s23[18],w2[18],q1[11]);
xor(s23[17],w2[17],q1[11]);
xor(s23[16],w2[16],q1[11]);
xor(s23[15],w2[15],q1[11]);
xor(s23[14],w2[14],q1[11]);
xor(s23[13],w2[13],q1[11]);
xor(s23[12],w2[12],q1[11]);
xor(s23[11],w2[11],q1[11]);
xor(s23[10],w2[10],q1[11]);
xor(s23[9],w2[9],q1[11]);
xor(s23[8],w2[8],q1[11]);
xor(s23[7],w2[7],q1[11]);
xor(s23[6],w2[6],q1[11]);
xor(s23[5],w2[5],q1[11]);
xor(s23[4],w2[4],q1[11]);
xor(s23[3],w2[3],q1[11]);
xor(s23[2],w2[2],q1[11]);
xor(s23[1],w2[1],q1[11]);
xor(s23[0],w2[0],q1[11]);
shifter sh22(saksham22,sum22,w5[10]);
fulladd32bit fa12(sum23,q1[10],saksham22,s23,q1[11]);
xor(s24[31],w2[31],q1[10]);
xor(s24[30],w2[30],q1[10]);
xor(s24[29],w2[29],q1[10]);
xor(s24[28],w2[28],q1[10]);
xor(s24[27],w2[27],q1[10]);
xor(s24[26],w2[26],q1[10]);
xor(s24[25],w2[25],q1[10]);
xor(s24[24],w2[24],q1[10]);
xor(s24[23],w2[23],q1[10]);
xor(s24[22],w2[22],q1[10]);
xor(s24[21],w2[21],q1[10]);
xor(s24[20],w2[20],q1[10]);
xor(s24[19],w2[19],q1[10]);
xor(s24[18],w2[18],q1[10]);
xor(s24[17],w2[17],q1[10]);
xor(s24[16],w2[16],q1[10]);
xor(s24[15],w2[15],q1[10]);
xor(s24[14],w2[14],q1[10]);
xor(s24[13],w2[13],q1[10]);
xor(s24[12],w2[12],q1[10]);
xor(s24[11],w2[11],q1[10]);
xor(s24[10],w2[10],q1[10]);
xor(s24[9],w2[9],q1[10]);
xor(s24[8],w2[8],q1[10]);
xor(s24[7],w2[7],q1[10]);
xor(s24[6],w2[6],q1[10]);
xor(s24[5],w2[5],q1[10]);
xor(s24[4],w2[4],q1[10]);
xor(s24[3],w2[3],q1[10]);
xor(s24[2],w2[2],q1[10]);
xor(s24[1],w2[1],q1[10]);
xor(s24[0],w2[0],q1[10]);
shifter sh23(saksham23,sum23,w5[9]);
fulladd32bit fa11(sum24,q1[9],saksham23,s24,q1[10]);
xor(s25[31],w2[31],q1[9]);
xor(s25[30],w2[30],q1[9]);
xor(s25[29],w2[29],q1[9]);
xor(s25[28],w2[28],q1[9]);
xor(s25[27],w2[27],q1[9]);
xor(s25[26],w2[26],q1[9]);
xor(s25[25],w2[25],q1[9]);
xor(s25[24],w2[24],q1[9]);
xor(s25[23],w2[23],q1[9]);
xor(s25[22],w2[22],q1[9]);
xor(s25[21],w2[21],q1[9]);
xor(s25[20],w2[20],q1[9]);
xor(s25[19],w2[19],q1[9]);
xor(s25[18],w2[18],q1[9]);
xor(s25[17],w2[17],q1[9]);
xor(s25[16],w2[16],q1[9]);
xor(s25[15],w2[15],q1[9]);
xor(s25[14],w2[14],q1[9]);
xor(s25[13],w2[13],q1[9]);
xor(s25[12],w2[12],q1[9]);
xor(s25[11],w2[11],q1[9]);
xor(s25[10],w2[10],q1[9]);
xor(s25[9],w2[9],q1[9]);
xor(s25[8],w2[8],q1[9]);
xor(s25[7],w2[7],q1[9]);
xor(s25[6],w2[6],q1[9]);
xor(s25[5],w2[5],q1[9]);
xor(s25[4],w2[4],q1[9]);
xor(s25[3],w2[3],q1[9]);
xor(s25[2],w2[2],q1[9]);
xor(s25[1],w2[1],q1[9]);
xor(s25[0],w2[0],q1[9]);
shifter sh24(saksham24,sum24,w5[8]);
fulladd32bit fa10(sum25,q1[8],saksham24,s25,q1[9]);
xor(s26[31],w2[31],q1[8]);
xor(s26[30],w2[30],q1[8]);
xor(s26[29],w2[29],q1[8]);
xor(s26[28],w2[28],q1[8]);
xor(s26[27],w2[27],q1[8]);
xor(s26[26],w2[26],q1[8]);
xor(s26[25],w2[25],q1[8]);
xor(s26[24],w2[24],q1[8]);
xor(s26[23],w2[23],q1[8]);
xor(s26[22],w2[22],q1[8]);
xor(s26[21],w2[21],q1[8]);
xor(s26[20],w2[20],q1[8]);
xor(s26[19],w2[19],q1[8]);
xor(s26[18],w2[18],q1[8]);
xor(s26[17],w2[17],q1[8]);
xor(s26[16],w2[16],q1[8]);
xor(s26[15],w2[15],q1[8]);
xor(s26[14],w2[14],q1[8]);
xor(s26[13],w2[13],q1[8]);
xor(s26[12],w2[12],q1[8]);
xor(s26[11],w2[11],q1[8]);
xor(s26[10],w2[10],q1[8]);
xor(s26[9],w2[9],q1[8]);
xor(s26[8],w2[8],q1[8]);
xor(s26[7],w2[7],q1[8]);
xor(s26[6],w2[6],q1[8]);
xor(s26[5],w2[5],q1[8]);
xor(s26[4],w2[4],q1[8]);
xor(s26[3],w2[3],q1[8]);
xor(s26[2],w2[2],q1[8]);
xor(s26[1],w2[1],q1[8]);
xor(s26[0],w2[0],q1[8]);
shifter sh25(saksham25,sum25,w5[7]);
fulladd32bit fa9(sum26,q1[7],saksham25,s26,q1[8]);
xor(s27[31],w2[31],q1[7]);
xor(s27[30],w2[30],q1[7]);
xor(s27[29],w2[29],q1[7]);
xor(s27[28],w2[28],q1[7]);
xor(s27[27],w2[27],q1[7]);
xor(s27[26],w2[26],q1[7]);
xor(s27[25],w2[25],q1[7]);
xor(s27[24],w2[24],q1[7]);
xor(s27[23],w2[23],q1[7]);
xor(s27[22],w2[22],q1[7]);
xor(s27[21],w2[21],q1[7]);
xor(s27[20],w2[20],q1[7]);
xor(s27[19],w2[19],q1[7]);
xor(s27[18],w2[18],q1[7]);
xor(s27[17],w2[17],q1[7]);
xor(s27[16],w2[16],q1[7]);
xor(s27[15],w2[15],q1[7]);
xor(s27[14],w2[14],q1[7]);
xor(s27[13],w2[13],q1[7]);
xor(s27[12],w2[12],q1[7]);
xor(s27[11],w2[11],q1[7]);
xor(s27[10],w2[10],q1[7]);
xor(s27[9],w2[9],q1[7]);
xor(s27[8],w2[8],q1[7]);
xor(s27[7],w2[7],q1[7]);
xor(s27[6],w2[6],q1[7]);
xor(s27[5],w2[5],q1[7]);
xor(s27[4],w2[4],q1[7]);
xor(s27[3],w2[3],q1[7]);
xor(s27[2],w2[2],q1[7]);
xor(s27[1],w2[1],q1[7]);
xor(s27[0],w2[0],q1[7]);
shifter sh26(saksham26,sum26,w5[6]);
fulladd32bit fa8(sum27,q1[6],saksham26,s27,q1[7]);
xor(s28[31],w2[31],q1[6]);
xor(s28[30],w2[30],q1[6]);
xor(s28[29],w2[29],q1[6]);
xor(s28[28],w2[28],q1[6]);
xor(s28[27],w2[27],q1[6]);
xor(s28[26],w2[26],q1[6]);
xor(s28[25],w2[25],q1[6]);
xor(s28[24],w2[24],q1[6]);
xor(s28[23],w2[23],q1[6]);
xor(s28[22],w2[22],q1[6]);
xor(s28[21],w2[21],q1[6]);
xor(s28[20],w2[20],q1[6]);
xor(s28[19],w2[19],q1[6]);
xor(s28[18],w2[18],q1[6]);
xor(s28[17],w2[17],q1[6]);
xor(s28[16],w2[16],q1[6]);
xor(s28[15],w2[15],q1[6]);
xor(s28[14],w2[14],q1[6]);
xor(s28[13],w2[13],q1[6]);
xor(s28[12],w2[12],q1[6]);
xor(s28[11],w2[11],q1[6]);
xor(s28[10],w2[10],q1[6]);
xor(s28[9],w2[9],q1[6]);
xor(s28[8],w2[8],q1[6]);
xor(s28[7],w2[7],q1[6]);
xor(s28[6],w2[6],q1[6]);
xor(s28[5],w2[5],q1[6]);
xor(s28[4],w2[4],q1[6]);
xor(s28[3],w2[3],q1[6]);
xor(s28[2],w2[2],q1[6]);
xor(s28[1],w2[1],q1[6]);
xor(s28[0],w2[0],q1[6]);
shifter sh27(saksham27,sum27,w5[5]);
fulladd32bit fa7(sum28,q1[5],saksham27,s28,q1[6]);
xor(s29[31],w2[31],q1[5]);
xor(s29[30],w2[30],q1[5]);
xor(s29[29],w2[29],q1[5]);
xor(s29[28],w2[28],q1[5]);
xor(s29[27],w2[27],q1[5]);
xor(s29[26],w2[26],q1[5]);
xor(s29[25],w2[25],q1[5]);
xor(s29[24],w2[24],q1[5]);
xor(s29[23],w2[23],q1[5]);
xor(s29[22],w2[22],q1[5]);
xor(s29[21],w2[21],q1[5]);
xor(s29[20],w2[20],q1[5]);
xor(s29[19],w2[19],q1[5]);
xor(s29[18],w2[18],q1[5]);
xor(s29[17],w2[17],q1[5]);
xor(s29[16],w2[16],q1[5]);
xor(s29[15],w2[15],q1[5]);
xor(s29[14],w2[14],q1[5]);
xor(s29[13],w2[13],q1[5]);
xor(s29[12],w2[12],q1[5]);
xor(s29[11],w2[11],q1[5]);
xor(s29[10],w2[10],q1[5]);
xor(s29[9],w2[9],q1[5]);
xor(s29[8],w2[8],q1[5]);
xor(s29[7],w2[7],q1[5]);
xor(s29[6],w2[6],q1[5]);
xor(s29[5],w2[5],q1[5]);
xor(s29[4],w2[4],q1[5]);
xor(s29[3],w2[3],q1[5]);
xor(s29[2],w2[2],q1[5]);
xor(s29[1],w2[1],q1[5]);
xor(s29[0],w2[0],q1[5]);
shifter sh28(saksham28,sum28,w5[4]);
fulladd32bit fa6(sum29,q1[4],saksham28,s29,q1[5]);
xor(s30[31],w2[31],q1[4]);
xor(s30[30],w2[30],q1[4]);
xor(s30[29],w2[29],q1[4]);
xor(s30[28],w2[28],q1[4]);
xor(s30[27],w2[27],q1[4]);
xor(s30[26],w2[26],q1[4]);
xor(s30[25],w2[25],q1[4]);
xor(s30[24],w2[24],q1[4]);
xor(s30[23],w2[23],q1[4]);
xor(s30[22],w2[22],q1[4]);
xor(s30[21],w2[21],q1[4]);
xor(s30[20],w2[20],q1[4]);
xor(s30[19],w2[19],q1[4]);
xor(s30[18],w2[18],q1[4]);
xor(s30[17],w2[17],q1[4]);
xor(s30[16],w2[16],q1[4]);
xor(s30[15],w2[15],q1[4]);
xor(s30[14],w2[14],q1[4]);
xor(s30[13],w2[13],q1[4]);
xor(s30[12],w2[12],q1[4]);
xor(s30[11],w2[11],q1[4]);
xor(s30[10],w2[10],q1[4]);
xor(s30[9],w2[9],q1[4]);
xor(s30[8],w2[8],q1[4]);
xor(s30[7],w2[7],q1[4]);
xor(s30[6],w2[6],q1[4]);
xor(s30[5],w2[5],q1[4]);
xor(s30[4],w2[4],q1[4]);
xor(s30[3],w2[3],q1[4]);
xor(s30[2],w2[2],q1[4]);
xor(s30[1],w2[1],q1[4]);
xor(s30[0],w2[0],q1[4]);
shifter sh29(saksham29,sum29,w5[3]);
fulladd32bit fa5(sum30,q1[3],saksham29,s30,q1[4]);
xor(s31[31],w2[31],q1[3]);
xor(s31[30],w2[30],q1[3]);
xor(s31[29],w2[29],q1[3]);
xor(s31[28],w2[28],q1[3]);
xor(s31[27],w2[27],q1[3]);
xor(s31[26],w2[26],q1[3]);
xor(s31[25],w2[25],q1[3]);
xor(s31[24],w2[24],q1[3]);
xor(s31[23],w2[23],q1[3]);
xor(s31[22],w2[22],q1[3]);
xor(s31[21],w2[21],q1[3]);
xor(s31[20],w2[20],q1[3]);
xor(s31[19],w2[19],q1[3]);
xor(s31[18],w2[18],q1[3]);
xor(s31[17],w2[17],q1[3]);
xor(s31[16],w2[16],q1[3]);
xor(s31[15],w2[15],q1[3]);
xor(s31[14],w2[14],q1[3]);
xor(s31[13],w2[13],q1[3]);
xor(s31[12],w2[12],q1[3]);
xor(s31[11],w2[11],q1[3]);
xor(s31[10],w2[10],q1[3]);
xor(s31[9],w2[9],q1[3]);
xor(s31[8],w2[8],q1[3]);
xor(s31[7],w2[7],q1[3]);
xor(s31[6],w2[6],q1[3]);
xor(s31[5],w2[5],q1[3]);
xor(s31[4],w2[4],q1[3]);
xor(s31[3],w2[3],q1[3]);
xor(s31[2],w2[2],q1[3]);
xor(s31[1],w2[1],q1[3]);
xor(s31[0],w2[0],q1[3]);
shifter sh30(saksham30,sum30,w5[2]);
fulladd32bit fa4(sum31,q1[2],saksham30,s31,q1[3]);
xor(s32[31],w2[31],q1[2]);
xor(s32[30],w2[30],q1[2]);
xor(s32[29],w2[29],q1[2]);
xor(s32[28],w2[28],q1[2]);
xor(s32[27],w2[27],q1[2]);
xor(s32[26],w2[26],q1[2]);
xor(s32[25],w2[25],q1[2]);
xor(s32[24],w2[24],q1[2]);
xor(s32[23],w2[23],q1[2]);
xor(s32[22],w2[22],q1[2]);
xor(s32[21],w2[21],q1[2]);
xor(s32[20],w2[20],q1[2]);
xor(s32[19],w2[19],q1[2]);
xor(s32[18],w2[18],q1[2]);
xor(s32[17],w2[17],q1[2]);
xor(s32[16],w2[16],q1[2]);
xor(s32[15],w2[15],q1[2]);
xor(s32[14],w2[14],q1[2]);
xor(s32[13],w2[13],q1[2]);
xor(s32[12],w2[12],q1[2]);
xor(s32[11],w2[11],q1[2]);
xor(s32[10],w2[10],q1[2]);
xor(s32[9],w2[9],q1[2]);
xor(s32[8],w2[8],q1[2]);
xor(s32[7],w2[7],q1[2]);
xor(s32[6],w2[6],q1[2]);
xor(s32[5],w2[5],q1[2]);
xor(s32[4],w2[4],q1[2]);
xor(s32[3],w2[3],q1[2]);
xor(s32[2],w2[2],q1[2]);
xor(s32[1],w2[1],q1[2]);
xor(s32[0],w2[0],q1[2]);
shifter sh31(saksham31,sum31,w5[1]);
fulladd32bit fa3(sum32,q1[1], saksham31, s32, q1[2]);
xor(s33[31],w2[31],q1[1]);
xor(s33[30],w2[30],q1[1]);
xor(s33[29],w2[29],q1[1]);
xor(s33[28],w2[28],q1[1]);
xor(s33[27],w2[27],q1[1]);
xor(s33[26],w2[26],q1[1]);
xor(s33[25],w2[25],q1[1]);
xor(s33[24],w2[24],q1[1]);
xor(s33[23],w2[23],q1[1]);
xor(s33[22],w2[22],q1[1]);
xor(s33[21],w2[21],q1[1]);
xor(s33[20],w2[20],q1[1]);
xor(s33[19],w2[19],q1[1]);
xor(s33[18],w2[18],q1[1]);
xor(s33[17],w2[17],q1[1]);
xor(s33[16],w2[16],q1[1]);
xor(s33[15],w2[15],q1[1]);
xor(s33[14],w2[14],q1[1]);
xor(s33[13],w2[13],q1[1]);
xor(s33[12],w2[12],q1[1]);
xor(s33[11],w2[11],q1[1]);
xor(s33[10],w2[10],q1[1]);
xor(s33[9],w2[9],q1[1]);
xor(s33[8],w2[8],q1[1]);
xor(s33[7],w2[7],q1[1]);
xor(s33[6],w2[6],q1[1]);
xor(s33[5],w2[5],q1[1]);
xor(s33[4],w2[4],q1[1]);
xor(s33[3],w2[3],q1[1]);
xor(s33[2],w2[2],q1[1]);
xor(s33[1],w2[1],q1[1]);
xor(s33[0],w2[0],q1[1]);
wire ghj2;
assign ghj2=0;
shifter sh32(saksham32,sum32,w5[0]);
assign saksham33= w2[31:0];
fulladd32bit fa2(sum33,q1[0],saksham32,s33,q1[1]);
fulladd32bit fa1(sum34,s34,sum33,saksham33,ghj2);
mux mx31(r1[31],sum33[31],sum34[31],sum33[31]);
mux mx30(r1[30],sum33[30],sum34[30],sum33[31]);
mux mx29(r1[29],sum33[29],sum34[29],sum33[31]);
mux mx28(r1[28],sum33[28],sum34[28],sum33[31]);
mux mx27(r1[27],sum33[27],sum34[27],sum33[31]);
mux mx26(r1[26],sum33[26],sum34[26],sum33[31]);
mux mx25(r1[25],sum33[25],sum34[25],sum33[31]);
mux mx24(r1[24],sum33[24],sum34[24],sum33[31]);
mux mx23(r1[23],sum33[23],sum34[23],sum33[31]);
mux mx22(r1[22],sum33[22],sum34[22],sum33[31]);
mux mx21(r1[21],sum33[21],sum34[21],sum33[31]);
mux mx20(r1[20],sum33[20],sum34[20],sum33[31]);
mux mx19(r1[19],sum33[19],sum34[19],sum33[31]);
mux mx18(r1[18],sum33[18],sum34[18],sum33[31]);
mux mx17(r1[17],sum33[17],sum34[17],sum33[31]);
mux mx16(r1[16],sum33[16],sum34[16],sum33[31]);
mux mx15(r1[15],sum33[15],sum34[15],sum33[31]);
mux mx14(r1[14],sum33[14],sum34[14],sum33[31]);
mux mx13(r1[13],sum33[13],sum34[13],sum33[31]);
mux mx12(r1[12],sum33[12],sum34[12],sum33[31]);
mux mx11(r1[11],sum33[11],sum34[11],sum33[31]);
mux mx10(r1[10],sum33[10],sum34[10],sum33[31]);
mux mx9(r1[9],sum33[9],sum34[9],sum33[31]);
mux mx8(r1[8],sum33[8],sum34[8],sum33[31]);
mux mx7(r1[7],sum33[7],sum34[7],sum33[31]);
mux mx6(r1[6],sum33[6],sum34[6],sum33[31]);
mux mx5(r1[5],sum33[5],sum34[5],sum33[31]);
mux mx4(r1[4],sum33[4],sum34[4],sum33[31]);
mux mx3(r1[3],sum33[3],sum34[3],sum33[31]);
mux mx2(r1[2],sum33[2],sum34[2],sum33[31]);
mux mx1(r1[1],sum33[1],sum34[1],sum33[31]);
mux mx0(r1[0],sum33[0],sum34[0],sum33[31]);
//not n6[31:0](r,~r1);
//not n6[31:0](r,~q1[31:0]);
//converting normalised form of quotient into output form//
//xor(w7[32],a,q1[32]);
//not n6(r[0],~w7[32]);
xor(w7[31],a,q1[31]);
//not n6(r[0],~w7[31]);
xor(w7[30],a,q1[30]);
xor(w7[29],a,q1[29]);
xor(w7[28],a,q1[28]);
xor(w7[27],a,q1[27]);
xor(w7[26],a,q1[26]);
xor(w7[25],a,q1[25]);
xor(w7[24],a,q1[24]);
xor(w7[23],a,q1[23]);
xor(w7[22],a,q1[22]);
xor(w7[21],a,q1[21]);
xor(w7[20],a,q1[20]);
xor(w7[19],a,q1[19]);
xor(w7[18],a,q1[18]);
xor(w7[17],a,q1[17]);
xor(w7[16],a,q1[16]);
xor(w7[15],a,q1[15]);
xor(w7[14],a,q1[14]);
xor(w7[13],a,q1[13]);
xor(w7[12],a,q1[12]);
xor(w7[11],a,q1[11]);
xor(w7[10],a,q1[10]);
xor(w7[9],a,q1[9]);
xor(w7[8],a,q1[8]);
xor(w7[7],a,q1[7]);
xor(w7[6],a,q1[6]);
xor(w7[5],a,q1[5]);
xor(w7[4],a,q1[4]);
xor(w7[3],a,q1[3]);
xor(w7[2],a,q1[2]);
xor(w7[1],a,q1[1]);
//not n6(r[0],~q1[1]);
xor(w7[0],a,q1[0]);
//not n6[31:0](r,~w7[31:0]);
//not n6(r[31],~a);
halfadd ha0(q[0],w8[0],w7[0],a);
halfadd ha1(q[1],w8[1],w7[1],w8[0]);
halfadd ha2(q[2],w8[2],w7[2],w8[1]);
halfadd ha3(q[3],w8[3],w7[3],w8[2]);
halfadd ha4(q[4],w8[4],w7[4],w8[3]);
halfadd ha5(q[5],w8[5],w7[5],w8[4]);
halfadd ha6(q[6],w8[6],w7[6],w8[5]);
halfadd ha7(q[7],w8[7],w7[7],w8[6]);
halfadd ha8(q[8],w8[8],w7[8],w8[7]);
halfadd ha9(q[9],w8[9],w7[9],w8[8]);
halfadd ha10(q[10],w8[10],w7[10],w8[9]);
halfadd ha11(q[11],w8[11],w7[11],w8[10]);
halfadd ha12(q[12],w8[12],w7[12],w8[11]);
halfadd ha13(q[13],w8[13],w7[13],w8[12]);
halfadd ha14(q[14],w8[14],w7[14],w8[13]);
halfadd ha15(q[15],w8[15],w7[15],w8[14]);
halfadd ha16(q[16],w8[16],w7[16],w8[15]);
halfadd ha17(q[17],w8[17],w7[17],w8[16]);
halfadd ha18(q[18],w8[18],w7[18],w8[17]);
halfadd ha19(q[19],w8[19],w7[19],w8[18]);
halfadd ha20(q[20],w8[20],w7[20],w8[19]);
halfadd ha21(q[21],w8[21],w7[21],w8[20]);
halfadd ha22(q[22],w8[22],w7[22],w8[21]);
halfadd ha23(q[23],w8[23],w7[23],w8[22]);
halfadd ha24(q[24],w8[24],w7[24],w8[23]);
halfadd ha25(q[25],w8[25],w7[25],w8[24]);
halfadd ha26(q[26],w8[26],w7[26],w8[25]);
halfadd ha27(q[27],w8[27],w7[27],w8[26]);
halfadd ha28(q[28],w8[28],w7[28],w8[27]);
halfadd ha29(q[29],w8[29],w7[29],w8[28]);
halfadd ha30(q[30],w8[30],w7[30],w8[29]);
halfadd ha31(q[31],w8[31],w7[31],w8[30]);
//halfadd ha32(q[32],w8[32],w7[32],w8[31]);
//not n6[31:0](r,~q[31:0]);
//converting normalised form of remainder into output form//
wire b;
wire c;
not(c,m[31]);
and(b,d[31],c);
xor(w9[31],b,r1[31]);
xor(w9[30],b,r1[30]);
xor(w9[29],b,r1[29]);
xor(w9[28],b,r1[28]);
xor(w9[27],b,r1[27]);
xor(w9[26],b,r1[26]);
xor(w9[25],b,r1[25]);
xor(w9[24],b,r1[24]);
xor(w9[23],b,r1[23]);
xor(w9[22],b,r1[22]);
xor(w9[21],b,r1[21]);
xor(w9[20],b,r1[20]);
xor(w9[19],b,r1[19]);
xor(w9[18],b,r1[18]);
xor(w9[17],b,r1[17]);
xor(w9[16],b,r1[16]);
xor(w9[15],b,r1[15]);
xor(w9[14],b,r1[14]);
xor(w9[13],b,r1[13]);
xor(w9[12],b,r1[12]);
xor(w9[11],b,r1[11]);
xor(w9[10],b,r1[10]);
xor(w9[9],b,r1[9]);
xor(w9[8],b,r1[8]);
xor(w9[7],b,r1[7]);
xor(w9[6],b,r1[6]);
xor(w9[5],b,r1[5]);
xor(w9[4],b,r1[4]);
xor(w9[3],b,r1[3]);
xor(w9[2],b,r1[2]);
xor(w9[1],b,r1[1]);
xor(w9[0],b,r1[0]);
halfadd hf0(r[0],w10[0],w9[0],b);
halfadd hf1(r[1],w10[1],w9[1],w10[0]);
halfadd hf2(r[2],w10[2],w9[2],w10[1]);
halfadd hf3(r[3],w10[3],w9[3],w10[2]);
halfadd hf4(r[4],w10[4],w9[4],w10[3]);
halfadd hf5(r[5],w10[5],w9[5],w10[4]);
halfadd hf6(r[6],w10[6],w9[6],w10[5]);
halfadd hf7(r[7],w10[7],w9[7],w10[6]);
halfadd hf8(r[8],w10[8],w9[8],w10[7]);
halfadd hf9(r[9],w10[9],w9[9],w10[8]);
halfadd hf10(r[10],w10[10],w9[10],w10[9]);
halfadd hf11(r[11],w10[11],w9[11],w10[10]);
halfadd hf12(r[12],w10[12],w9[12],w10[11]);
halfadd hf13(r[13],w10[13],w9[13],w10[12]);
halfadd hf14(r[14],w10[14],w9[14],w10[13]);
halfadd hf15(r[15],w10[15],w9[15],w10[14]);
halfadd hf16(r[16],w10[16],w9[16],w10[15]);
halfadd hf17(r[17],w10[17],w9[17],w10[16]);
halfadd hf18(r[18],w10[18],w9[18],w10[17]);
halfadd hf19(r[19],w10[19],w9[19],w10[18]);
halfadd hf20(r[20],w10[20],w9[20],w10[19]);
halfadd hf21(r[21],w10[21],w9[21],w10[20]);
halfadd hf22(r[22],w10[22],w9[22],w10[21]);
halfadd hf23(r[23],w10[23],w9[23],w10[22]);
halfadd hf24(r[24],w10[24],w9[24],w10[23]);
halfadd hf25(r[25],w10[25],w9[25],w10[24]);
halfadd hf26(r[26],w10[26],w9[26],w10[25]);
halfadd hf27(r[27],w10[27],w9[27],w10[26]);
halfadd hf28(r[28],w10[28],w9[28],w10[27]);
halfadd hf29(r[29],w10[29],w9[29],w10[28]);
halfadd hf30(r[30],w10[30],w9[30],w10[29]);
halfadd hf31(r[31],w10[31],w9[31],w10[30]);
/* edhar ko change kiya */
endmodule
/*
module fulladd(sum, c_out, a, b, c_in);
output sum;
output c_out;
input a;
input b;
input c_in;
wire s1, c1, c2;
xor(s1, a, b);
xor(sum, s1, c_in);
and(c1, a, b);
and(c2, s1, c_in);
or(c_out, c2, c1);
endmodule
*/
module halfadd(sum,c_out,a,b);
output sum,c_out;
input a,b;
xor(sum,a,b);
and(c_out,a,b);
endmodule
//Define 31-bit full adder
module fulladd32bit(sum, c_out, a, b, c_in);
// I/O port declaration
output [31:0] sum;
output c_out;
input [31:0]a;
input [31:0]b;
input c_in;
//internal nets
wire c1, c2, c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15,c16,c17,c18,c19,c20,c21,c22,c23,c24,c25,c26,c27,c28,c29,c30,c31;
//Instantiate four 1-bit adders
fulladd fa0(sum[0], c1, a[0], b[0], c_in);
fulladd fa1(sum[1], c2, a[1], b[1], c1);
fulladd fa2(sum[2], c3, a[2], b[2], c2);
fulladd fa3(sum[3], c4, a[3], b[3], c3);
fulladd fa4(sum[4], c5, a[4], b[4], c4);
fulladd fa5(sum[5], c6, a[5], b[5], c5);
fulladd fa6(sum[6], c7, a[6], b[6], c6);
fulladd fa7(sum[7], c8, a[7], b[7], c7);
fulladd fa8(sum[8], c9, a[8], b[8], c8);
fulladd fa9(sum[9], c10, a[9], b[9], c9);
fulladd fa10(sum[10], c11, a[10], b[10], c10);
fulladd fa11(sum[11], c12, a[11], b[11], c11);
fulladd fa12(sum[12], c13, a[12], b[12], c12);
fulladd fa13(sum[13], c14, a[13], b[13], c13);
fulladd fa14(sum[14], c15, a[14], b[14], c14);
fulladd fa15(sum[15], c16, a[15], b[15], c15);
fulladd fa16(sum[16], c17, a[16], b[16], c16);
fulladd fa17(sum[17], c18, a[17], b[17], c17);
fulladd fa18(sum[18], c19, a[18], b[18], c18);
fulladd fa19(sum[19], c20, a[19], b[19], c19);
fulladd fa20(sum[20], c21, a[20], b[20], c20);
fulladd fa21(sum[21], c22, a[21], b[21], c21);
fulladd fa22(sum[22], c23, a[22], b[22], c22);
fulladd fa23(sum[23], c24, a[23], b[23], c23);
fulladd fa24(sum[24], c25, a[24], b[24], c24);
fulladd fa25(sum[25], c26, a[25], b[25], c25);
fulladd fa26(sum[26], c27, a[26], b[26], c26);
fulladd fa27(sum[27], c28, a[27], b[27], c27);
fulladd fa28(sum[28], c29, a[28], b[28], c28);
fulladd fa29(sum[29], c30, a[29], b[29], c29);
fulladd fa30(sum[30], c31, a[30], b[30], c30);
fulladd fa31(sum[31], c_out, a[31], b[31], c31);
endmodule
module shifter(out,in,i);
output [31:0]out;
input [31:0]in;
input i;
assign out[31]=in[30];
assign out[30]=in[29];
assign out[29]=in[28];
assign out[28]=in[27];
assign out[27]=in[26];
assign out[26]=in[25];
assign out[25]=in[24];
assign out[24]=in[23];
assign out[23]=in[22];
assign out[22]=in[21];
assign out[21]=in[20];
assign out[20]=in[19];
assign out[19]=in[18];
assign out[18]=in[17];
assign out[17]=in[16];
assign out[16]=in[15];
assign out[15]=in[14];
assign out[14]=in[13];
assign out[13]=in[12];
assign out[12]=in[11];
assign out[11]=in[10];
assign out[10]=in[9];
assign out[9]=in[8];
assign out[8]=in[7];
assign out[7]=in[6];
assign out[6]=in[5];
assign out[5]=in[4];
assign out[4]=in[3];
assign out[3]=in[2];
assign out[2]=in[1];
assign out[1]=in[0];
assign out[0]=i;
endmodule
module mux(out,in1,in2,s);
output out;
input in1,in2;
input s;
wire w11,w12,w13;
not(w11,s);
and(w12,w11,in1);
and(w13,s,in2);
or(out,w12,w13);
endmodule
/*
module stimulus;
reg [31:0]m1;
reg [31:0]d1;
wire [31:0]q1;
wire [31:0]r2;
signeddivision1 sd1(q1,r2,m1,d1);
initial
begin
$monitor($time,":\ndivisor = %b,\ndividend = %b\nQuotient = %b,\nRemainder = %b", m1, d1,q1, r2);
end
initial
begin
m1= 32'd14; d1=32'd15;
#5 m1= -32'sd3; d1=32'd5;
#5 m1= 32'sd4; d1=-32'sd6;
#5 m1= -32'sd4; d1=-32'sd6;
end
endmodule */ |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIEBus_gt_top.v
// Version : 1.11
//-- Description: GTX module for 7-series Integrated PCIe Block
//--
//--
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module PCIEBus_gt_top #
(
parameter LINK_CAP_MAX_LINK_WIDTH = 8, // 1 - x1 , 2 - x2 , 4 - x4 , 8 - x8
parameter REF_CLK_FREQ = 0, // 0 - 100 MHz , 1 - 125 MHz , 2 - 250 MHz
parameter USER_CLK2_DIV2 = "FALSE", // "FALSE" => user_clk2 = user_clk
// "TRUE" => user_clk2 = user_clk/2, where user_clk = 500 or 250 MHz.
parameter integer USER_CLK_FREQ = 3, // 0 - 31.25 MHz , 1 - 62.5 MHz , 2 - 125 MHz , 3 - 250 MHz , 4 - 500Mhz
parameter PL_FAST_TRAIN = "FALSE", // Simulation Speedup
parameter PCIE_EXT_CLK = "FALSE", // Use External Clocking
parameter PCIE_USE_MODE = "1.0", // 1.0 = K325T IES, 1.1 = VX485T IES, 3.0 = K325T GES
parameter PCIE_GT_DEVICE = "GTX", // Select the GT to use (GTP for Artix-7, GTX for K7/V7)
parameter PCIE_PLL_SEL = "CPLL", // Select the PLL (CPLL or QPLL)
parameter PCIE_ASYNC_EN = "FALSE", // Asynchronous Clocking Enable
parameter PCIE_TXBUF_EN = "FALSE", // Use the Tansmit Buffer
parameter PCIE_CHAN_BOND = 0
)
(
//-----------------------------------------------------------------------------------------------------------------//
// pl ltssm
input wire [5:0] pl_ltssm_state ,
// Pipe Per-Link Signals
input wire pipe_tx_rcvr_det ,
input wire pipe_tx_reset ,
input wire pipe_tx_rate ,
input wire pipe_tx_deemph ,
input wire [2:0] pipe_tx_margin ,
input wire pipe_tx_swing ,
//-----------------------------------------------------------------------------------------------------------------//
// Clock Inputs //
//-----------------------------------------------------------------------------------------------------------------//
input PIPE_PCLK_IN,
input PIPE_RXUSRCLK_IN,
input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PIPE_RXOUTCLK_IN,
input PIPE_DCLK_IN,
input PIPE_USERCLK1_IN,
input PIPE_USERCLK2_IN,
input PIPE_OOBCLK_IN,
input PIPE_MMCM_LOCK_IN,
output PIPE_TXOUTCLK_OUT,
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PIPE_RXOUTCLK_OUT,
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PIPE_PCLK_SEL_OUT,
output PIPE_GEN3_OUT,
// Pipe Per-Lane Signals - Lane 0
output wire [ 1:0] pipe_rx0_char_is_k ,
output wire [15:0] pipe_rx0_data ,
output wire pipe_rx0_valid ,
output wire pipe_rx0_chanisaligned ,
output wire [ 2:0] pipe_rx0_status ,
output wire pipe_rx0_phy_status ,
output wire pipe_rx0_elec_idle ,
input wire pipe_rx0_polarity ,
input wire pipe_tx0_compliance ,
input wire [ 1:0] pipe_tx0_char_is_k ,
input wire [15:0] pipe_tx0_data ,
input wire pipe_tx0_elec_idle ,
input wire [ 1:0] pipe_tx0_powerdown ,
// Pipe Per-Lane Signals - Lane 1
output wire [ 1:0] pipe_rx1_char_is_k ,
output wire [15:0] pipe_rx1_data ,
output wire pipe_rx1_valid ,
output wire pipe_rx1_chanisaligned ,
output wire [ 2:0] pipe_rx1_status ,
output wire pipe_rx1_phy_status ,
output wire pipe_rx1_elec_idle ,
input wire pipe_rx1_polarity ,
input wire pipe_tx1_compliance ,
input wire [ 1:0] pipe_tx1_char_is_k ,
input wire [15:0] pipe_tx1_data ,
input wire pipe_tx1_elec_idle ,
input wire [ 1:0] pipe_tx1_powerdown ,
// Pipe Per-Lane Signals - Lane 2
output wire [ 1:0] pipe_rx2_char_is_k ,
output wire [15:0] pipe_rx2_data ,
output wire pipe_rx2_valid ,
output wire pipe_rx2_chanisaligned ,
output wire [ 2:0] pipe_rx2_status ,
output wire pipe_rx2_phy_status ,
output wire pipe_rx2_elec_idle ,
input wire pipe_rx2_polarity ,
input wire pipe_tx2_compliance ,
input wire [ 1:0] pipe_tx2_char_is_k ,
input wire [15:0] pipe_tx2_data ,
input wire pipe_tx2_elec_idle ,
input wire [ 1:0] pipe_tx2_powerdown ,
// Pipe Per-Lane Signals - Lane 3
output wire [ 1:0] pipe_rx3_char_is_k ,
output wire [15:0] pipe_rx3_data ,
output wire pipe_rx3_valid ,
output wire pipe_rx3_chanisaligned ,
output wire [ 2:0] pipe_rx3_status ,
output wire pipe_rx3_phy_status ,
output wire pipe_rx3_elec_idle ,
input wire pipe_rx3_polarity ,
input wire pipe_tx3_compliance ,
input wire [ 1:0] pipe_tx3_char_is_k ,
input wire [15:0] pipe_tx3_data ,
input wire pipe_tx3_elec_idle ,
input wire [ 1:0] pipe_tx3_powerdown ,
// Pipe Per-Lane Signals - Lane 4
output wire [ 1:0] pipe_rx4_char_is_k ,
output wire [15:0] pipe_rx4_data ,
output wire pipe_rx4_valid ,
output wire pipe_rx4_chanisaligned ,
output wire [ 2:0] pipe_rx4_status ,
output wire pipe_rx4_phy_status ,
output wire pipe_rx4_elec_idle ,
input wire pipe_rx4_polarity ,
input wire pipe_tx4_compliance ,
input wire [ 1:0] pipe_tx4_char_is_k ,
input wire [15:0] pipe_tx4_data ,
input wire pipe_tx4_elec_idle ,
input wire [ 1:0] pipe_tx4_powerdown ,
// Pipe Per-Lane Signals - Lane 5
output wire [ 1:0] pipe_rx5_char_is_k ,
output wire [15:0] pipe_rx5_data ,
output wire pipe_rx5_valid ,
output wire pipe_rx5_chanisaligned ,
output wire [ 2:0] pipe_rx5_status ,
output wire pipe_rx5_phy_status ,
output wire pipe_rx5_elec_idle ,
input wire pipe_rx5_polarity ,
input wire pipe_tx5_compliance ,
input wire [ 1:0] pipe_tx5_char_is_k ,
input wire [15:0] pipe_tx5_data ,
input wire pipe_tx5_elec_idle ,
input wire [ 1:0] pipe_tx5_powerdown ,
// Pipe Per-Lane Signals - Lane 6
output wire [ 1:0] pipe_rx6_char_is_k ,
output wire [15:0] pipe_rx6_data ,
output wire pipe_rx6_valid ,
output wire pipe_rx6_chanisaligned ,
output wire [ 2:0] pipe_rx6_status ,
output wire pipe_rx6_phy_status ,
output wire pipe_rx6_elec_idle ,
input wire pipe_rx6_polarity ,
input wire pipe_tx6_compliance ,
input wire [ 1:0] pipe_tx6_char_is_k ,
input wire [15:0] pipe_tx6_data ,
input wire pipe_tx6_elec_idle ,
input wire [ 1:0] pipe_tx6_powerdown ,
// Pipe Per-Lane Signals - Lane 7
output wire [ 1:0] pipe_rx7_char_is_k ,
output wire [15:0] pipe_rx7_data ,
output wire pipe_rx7_valid ,
output wire pipe_rx7_chanisaligned ,
output wire [ 2:0] pipe_rx7_status ,
output wire pipe_rx7_phy_status ,
output wire pipe_rx7_elec_idle ,
input wire pipe_rx7_polarity ,
input wire pipe_tx7_compliance ,
input wire [ 1:0] pipe_tx7_char_is_k ,
input wire [15:0] pipe_tx7_data ,
input wire pipe_tx7_elec_idle ,
input wire [ 1:0] pipe_tx7_powerdown ,
// PCI Express signals
output wire [ (LINK_CAP_MAX_LINK_WIDTH-1):0] pci_exp_txn ,
output wire [ (LINK_CAP_MAX_LINK_WIDTH-1):0] pci_exp_txp ,
input wire [ (LINK_CAP_MAX_LINK_WIDTH-1):0] pci_exp_rxn ,
input wire [ (LINK_CAP_MAX_LINK_WIDTH-1):0] pci_exp_rxp ,
// Non PIPE signals
input wire sys_clk ,
input wire sys_rst_n ,
input wire PIPE_MMCM_RST_N ,
output wire pipe_clk ,
output wire user_clk ,
output wire user_clk2 ,
output wire phy_rdy_n
);
parameter TCQ = 1; // clock to out delay model
localparam USERCLK2_FREQ = (USER_CLK2_DIV2 == "FALSE") ? USER_CLK_FREQ :
(USER_CLK_FREQ == 4) ? 3 :
(USER_CLK_FREQ == 3) ? 2 :
USER_CLK_FREQ;
localparam PCIE_LPM_DFE = (PL_FAST_TRAIN == "TRUE") ? "DFE" : "LPM";
localparam PCIE_LINK_SPEED = (PL_FAST_TRAIN == "TRUE") ? 2 : 3;
// The parameter PCIE_OOBCLK_MODE_ENABLE value should be "0" for simulation and for synthesis it should be 1
//localparam PCIE_OOBCLK_MODE_ENABLE = (PL_FAST_TRAIN == "TRUE") ? 0 : 1;
localparam PCIE_OOBCLK_MODE_ENABLE = 1;
localparam PCIE_TX_EIDLE_ASSERT_DELAY = (PL_FAST_TRAIN == "TRUE") ? 4 : 2;
wire [ 7:0] gt_rx_phy_status_wire ;
wire [ 7:0] gt_rxchanisaligned_wire ;
wire [ 31:0] gt_rx_data_k_wire ;
wire [255:0] gt_rx_data_wire ;
wire [ 7:0] gt_rx_elec_idle_wire ;
wire [ 23:0] gt_rx_status_wire ;
wire [ 7:0] gt_rx_valid_wire ;
wire [ 7:0] gt_rx_polarity ;
wire [ 15:0] gt_power_down ;
wire [ 7:0] gt_tx_char_disp_mode ;
wire [ 31:0] gt_tx_data_k ;
wire [255:0] gt_tx_data ;
wire gt_tx_detect_rx_loopback ;
wire [ 7:0] gt_tx_elec_idle ;
wire [ 7:0] gt_rx_elec_idle_reset ;
wire [LINK_CAP_MAX_LINK_WIDTH-1:0] plllkdet ;
wire [LINK_CAP_MAX_LINK_WIDTH-1:0] phystatus_rst ;
wire clock_locked ;
wire [ 7:0] gt_rx_phy_status_wire_filter ;
wire [ 31:0] gt_rx_data_k_wire_filter ;
wire [255:0] gt_rx_data_wire_filter ;
wire [ 7:0] gt_rx_elec_idle_wire_filter ;
wire [ 23:0] gt_rx_status_wire_filter ;
wire [ 7:0] gt_rx_valid_wire_filter ;
wire pipe_clk_int;
reg phy_rdy_n_int;
reg reg_clock_locked;
wire all_phystatus_rst;
reg [5:0] pl_ltssm_state_q;
always @(posedge pipe_clk_int or negedge clock_locked) begin
if (!clock_locked)
pl_ltssm_state_q <= #TCQ 6'b0;
else
pl_ltssm_state_q <= #TCQ pl_ltssm_state;
end
assign pipe_clk = pipe_clk_int ;
wire plm_in_l0 = (pl_ltssm_state_q == 6'h16);
wire plm_in_rl = (pl_ltssm_state_q == 6'h1c);
wire plm_in_dt = (pl_ltssm_state_q == 6'h2d);
wire plm_in_rs = (pl_ltssm_state_q == 6'h1f);
//-------------RX FILTER Instantiation----------------------------------------------------------//
genvar i;
generate for (i=0; i<LINK_CAP_MAX_LINK_WIDTH; i=i+1)
begin : gt_rx_valid_filter
PCIEBus_gt_rx_valid_filter_7x # (
.CLK_COR_MIN_LAT(28)
)
GT_RX_VALID_FILTER_7x_inst (
.USER_RXCHARISK ( gt_rx_data_k_wire [(2*i)+1 + (2*i):(2*i)+ (2*i)] ), //O
.USER_RXDATA ( gt_rx_data_wire [(16*i)+15+(16*i) :(16*i)+0 + (16*i)] ), //O
.USER_RXVALID ( gt_rx_valid_wire [i] ), //O
.USER_RXELECIDLE ( gt_rx_elec_idle_wire [i] ), //O
.USER_RX_STATUS ( gt_rx_status_wire [(3*i)+2:(3*i)] ), //O
.USER_RX_PHY_STATUS ( gt_rx_phy_status_wire [i] ), //O
.GT_RXCHARISK ( gt_rx_data_k_wire_filter [(2*i)+1+ (2*i):2*i+ (2*i)] ), //I
.GT_RXDATA ( gt_rx_data_wire_filter [(16*i)+15+(16*i) :(16*i)+0+(16*i)] ), //I
.GT_RXVALID ( gt_rx_valid_wire_filter [i] ), //I
.GT_RXELECIDLE ( gt_rx_elec_idle_wire_filter [i] ), //I
.GT_RX_STATUS ( gt_rx_status_wire_filter [(3*i)+2:(3*i)] ), //I
.GT_RX_PHY_STATUS ( gt_rx_phy_status_wire_filter [i] ),
.PLM_IN_L0 ( plm_in_l0 ), //I
.PLM_IN_RS ( plm_in_rs ), //I
.USER_CLK ( pipe_clk_int ), //I
.RESET ( phy_rdy_n_int ) //I
);
end
endgenerate
//---------- GT Instantiation ---------------------------------------------------------------
PCIEBus_pipe_wrapper #
(
.PCIE_SIM_MODE ( PL_FAST_TRAIN ),
// synthesis translate_off
.PCIE_SIM_SPEEDUP ( "TRUE" ),
// synthesis translate_on
.PCIE_EXT_CLK ( PCIE_EXT_CLK ),
.PCIE_TXBUF_EN ( PCIE_TXBUF_EN ),
.PCIE_ASYNC_EN ( PCIE_ASYNC_EN ),
.PCIE_CHAN_BOND ( PCIE_CHAN_BOND ),
.PCIE_PLL_SEL ( PCIE_PLL_SEL ),
.PCIE_GT_DEVICE ( PCIE_GT_DEVICE ),
.PCIE_USE_MODE ( PCIE_USE_MODE ),
.PCIE_LANE ( LINK_CAP_MAX_LINK_WIDTH ),
.PCIE_LPM_DFE ( PCIE_LPM_DFE ),
.PCIE_LINK_SPEED ( PCIE_LINK_SPEED ),
.PCIE_TX_EIDLE_ASSERT_DELAY ( PCIE_TX_EIDLE_ASSERT_DELAY ),
.PCIE_OOBCLK_MODE ( PCIE_OOBCLK_MODE_ENABLE ),
.PCIE_REFCLK_FREQ ( REF_CLK_FREQ ),
.PCIE_USERCLK1_FREQ ( USER_CLK_FREQ +1 ),
.PCIE_USERCLK2_FREQ ( USERCLK2_FREQ +1 )
) pipe_wrapper_i (
//---------- PIPE Clock & Reset Ports ------------------
.PIPE_CLK ( sys_clk ),
.PIPE_RESET_N ( sys_rst_n ),
.PIPE_PCLK ( pipe_clk_int ),
//---------- PIPE TX Data Ports ------------------
.PIPE_TXDATA ( gt_tx_data[((32*LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_TXDATAK ( gt_tx_data_k[((4*LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_TXP ( pci_exp_txp[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_TXN ( pci_exp_txn[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
//---------- PIPE RX Data Ports ------------------
.PIPE_RXP ( pci_exp_rxp[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RXN ( pci_exp_rxn[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RXDATA ( gt_rx_data_wire_filter[((32*LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RXDATAK ( gt_rx_data_k_wire_filter[((4*LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
//---------- PIPE Command Ports ------------------
.PIPE_TXDETECTRX ( gt_tx_detect_rx_loopback ),
.PIPE_TXELECIDLE ( gt_tx_elec_idle[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_TXCOMPLIANCE ( gt_tx_char_disp_mode[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RXPOLARITY ( gt_rx_polarity[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_POWERDOWN ( gt_power_down[((2*LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RATE ( {1'b0,pipe_tx_rate} ),
//---------- PIPE Electrical Command Ports ------------------
.PIPE_TXMARGIN ( pipe_tx_margin[2:0] ),
.PIPE_TXSWING ( pipe_tx_swing ),
.PIPE_TXDEEMPH ( {(LINK_CAP_MAX_LINK_WIDTH){pipe_tx_deemph}} ),
.PIPE_TXEQ_CONTROL ( {2*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_TXEQ_PRESET ( {4*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_TXEQ_PRESET_DEFAULT ( {4*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_RXEQ_CONTROL ( {2*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_RXEQ_PRESET ( {3*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_RXEQ_LFFS ( {6*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_RXEQ_TXPRESET ( {4*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_RXEQ_USER_EN ( {1*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_RXEQ_USER_TXCOEFF ( {18*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_RXEQ_USER_MODE ( {1*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_TXEQ_COEFF ( ),
.PIPE_TXEQ_DEEMPH ( {6*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_TXEQ_FS ( ),
.PIPE_TXEQ_LF ( ),
.PIPE_TXEQ_DONE ( ),
.PIPE_RXEQ_NEW_TXCOEFF ( ),
.PIPE_RXEQ_LFFS_SEL ( ),
.PIPE_RXEQ_ADAPT_DONE ( ),
.PIPE_RXEQ_DONE ( ),
//---------- PIPE Status Ports -------------------
.PIPE_RXVALID ( gt_rx_valid_wire_filter[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_PHYSTATUS ( gt_rx_phy_status_wire_filter[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_PHYSTATUS_RST ( phystatus_rst ),
.PIPE_RXELECIDLE ( gt_rx_elec_idle_wire_filter[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RXSTATUS ( gt_rx_status_wire_filter[((3*LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RXBUFSTATUS ( ),
//---------- PIPE User Ports ---------------------------
.PIPE_MMCM_RST_N ( PIPE_MMCM_RST_N ), // Async | Async
.PIPE_RXSLIDE ( {1*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_CPLL_LOCK ( plllkdet ),
.PIPE_QPLL_LOCK ( ),
.PIPE_PCLK_LOCK ( clock_locked ),
.PIPE_RXCDRLOCK ( ),
.PIPE_USERCLK1 ( user_clk ),
.PIPE_USERCLK2 ( user_clk2 ),
.PIPE_RXUSRCLK ( ),
.PIPE_RXOUTCLK ( ),
.PIPE_TXSYNC_DONE ( ),
.PIPE_RXSYNC_DONE ( ),
.PIPE_GEN3_RDY ( ),
.PIPE_RXCHANISALIGNED ( gt_rxchanisaligned_wire[LINK_CAP_MAX_LINK_WIDTH-1:0] ),
.PIPE_ACTIVE_LANE ( ),
//---------- External Clock Ports ---------------------------
.PIPE_PCLK_IN ( PIPE_PCLK_IN ),
.PIPE_RXUSRCLK_IN ( PIPE_RXUSRCLK_IN ),
.PIPE_RXOUTCLK_IN ( PIPE_RXOUTCLK_IN ),
.PIPE_DCLK_IN ( PIPE_DCLK_IN ),
.PIPE_USERCLK1_IN ( PIPE_USERCLK1_IN ),
.PIPE_USERCLK2_IN ( PIPE_USERCLK2_IN ),
.PIPE_OOBCLK_IN ( PIPE_OOBCLK_IN ),
.PIPE_JTAG_EN ( 1'b0 ),
.PIPE_JTAG_RDY ( ),
.PIPE_MMCM_LOCK_IN ( PIPE_MMCM_LOCK_IN ),
.PIPE_TXOUTCLK_OUT ( PIPE_TXOUTCLK_OUT ),
.PIPE_RXOUTCLK_OUT ( PIPE_RXOUTCLK_OUT ),
.PIPE_PCLK_SEL_OUT ( PIPE_PCLK_SEL_OUT ),
.PIPE_GEN3_OUT ( PIPE_GEN3_OUT ),
//---------- PRBS/Loopback Ports ---------------------------
.PIPE_TXPRBSSEL ( 3'b0 ),
.PIPE_RXPRBSSEL ( 3'b0 ),
.PIPE_TXPRBSFORCEERR ( 1'b0 ),
.PIPE_RXPRBSCNTRESET ( 1'b0 ),
.PIPE_LOOPBACK ( 3'b0 ),
.PIPE_RXPRBSERR ( ),
//---------- FSM Ports ---------------------------
.PIPE_RST_FSM ( ),
.PIPE_QRST_FSM ( ),
.PIPE_RATE_FSM ( ),
.PIPE_SYNC_FSM_TX ( ),
.PIPE_SYNC_FSM_RX ( ),
.PIPE_DRP_FSM ( ),
.PIPE_TXEQ_FSM ( ),
.PIPE_RXEQ_FSM ( ),
.PIPE_QDRP_FSM ( ),
.PIPE_RST_IDLE ( ),
.PIPE_QRST_IDLE ( ),
.PIPE_RATE_IDLE ( ),
//---------- DEBUG Ports ---------------------------
.PIPE_DEBUG_0 ( ),
.PIPE_DEBUG_1 ( ),
.PIPE_DEBUG_2 ( ),
.PIPE_DEBUG_3 ( ),
.PIPE_DEBUG_4 ( ),
.PIPE_DEBUG_5 ( ),
.PIPE_DEBUG_6 ( ),
.PIPE_DEBUG_7 ( ),
.PIPE_DEBUG_8 ( ),
.PIPE_DEBUG_9 ( ),
.PIPE_DEBUG ( ),
.PIPE_DMONITOROUT ( )
);
assign pipe_rx0_phy_status = gt_rx_phy_status_wire[0] ;
assign pipe_rx1_phy_status = (LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? gt_rx_phy_status_wire[1] : 1'b0;
assign pipe_rx2_phy_status = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_phy_status_wire[2] : 1'b0;
assign pipe_rx3_phy_status = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_phy_status_wire[3] : 1'b0;
assign pipe_rx4_phy_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_phy_status_wire[4] : 1'b0;
assign pipe_rx5_phy_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_phy_status_wire[5] : 1'b0;
assign pipe_rx6_phy_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_phy_status_wire[6] : 1'b0;
assign pipe_rx7_phy_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_phy_status_wire[7] : 1'b0;
assign pipe_rx0_chanisaligned = gt_rxchanisaligned_wire[0];
assign pipe_rx1_chanisaligned = (LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? gt_rxchanisaligned_wire[1] : 1'b0 ;
assign pipe_rx2_chanisaligned = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rxchanisaligned_wire[2] : 1'b0 ;
assign pipe_rx3_chanisaligned = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rxchanisaligned_wire[3] : 1'b0 ;
assign pipe_rx4_chanisaligned = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rxchanisaligned_wire[4] : 1'b0 ;
assign pipe_rx5_chanisaligned = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rxchanisaligned_wire[5] : 1'b0 ;
assign pipe_rx6_chanisaligned = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rxchanisaligned_wire[6] : 1'b0 ;
assign pipe_rx7_chanisaligned = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rxchanisaligned_wire[7] : 1'b0 ;
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
assign pipe_rx0_char_is_k = {gt_rx_data_k_wire[1], gt_rx_data_k_wire[0]};
assign pipe_rx1_char_is_k = (LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? {gt_rx_data_k_wire[5], gt_rx_data_k_wire[4]} : 2'b0 ;
assign pipe_rx2_char_is_k = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? {gt_rx_data_k_wire[9], gt_rx_data_k_wire[8]} : 2'b0 ;
assign pipe_rx3_char_is_k = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? {gt_rx_data_k_wire[13], gt_rx_data_k_wire[12]} : 2'b0 ;
assign pipe_rx4_char_is_k = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? {gt_rx_data_k_wire[17], gt_rx_data_k_wire[16]} : 2'b0 ;
assign pipe_rx5_char_is_k = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? {gt_rx_data_k_wire[21], gt_rx_data_k_wire[20]} : 2'b0 ;
assign pipe_rx6_char_is_k = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? {gt_rx_data_k_wire[25], gt_rx_data_k_wire[24]} : 2'b0 ;
assign pipe_rx7_char_is_k = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? {gt_rx_data_k_wire[29], gt_rx_data_k_wire[28]} : 2'b0 ;
assign pipe_rx0_data = {gt_rx_data_wire[ 15: 8], gt_rx_data_wire[ 7: 0]};
assign pipe_rx1_data = (LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? {gt_rx_data_wire[47:40], gt_rx_data_wire[39:32]} : 16'h0 ;
assign pipe_rx2_data = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? {gt_rx_data_wire[79:72], gt_rx_data_wire[71:64]} : 16'h0 ;
assign pipe_rx3_data = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? {gt_rx_data_wire[111:104], gt_rx_data_wire[103:96]} : 16'h0 ;
assign pipe_rx4_data = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? {gt_rx_data_wire[143:136], gt_rx_data_wire[135:128]} : 16'h0 ;
assign pipe_rx5_data = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? {gt_rx_data_wire[175:168], gt_rx_data_wire[167:160]} : 16'h0 ;
assign pipe_rx6_data = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? {gt_rx_data_wire[207:200], gt_rx_data_wire[199:192]} : 16'h0 ;
assign pipe_rx7_data = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? {gt_rx_data_wire[239:232], gt_rx_data_wire[231:224]} : 16'h0 ;
assign pipe_rx0_status = gt_rx_status_wire[ 2: 0];
assign pipe_rx1_status = (LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? gt_rx_status_wire[ 5: 3] : 3'b0 ;
assign pipe_rx2_status = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_status_wire[ 8: 6] : 3'b0 ;
assign pipe_rx3_status = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_status_wire[11: 9] : 3'b0 ;
assign pipe_rx4_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_status_wire[14:12] : 3'b0 ;
assign pipe_rx5_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_status_wire[17:15] : 3'b0 ;
assign pipe_rx6_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_status_wire[20:18] : 3'b0 ;
assign pipe_rx7_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_status_wire[23:21] : 3'b0 ;
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
assign pipe_rx0_elec_idle = gt_rx_elec_idle_wire[0];
assign pipe_rx1_elec_idle = (LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? gt_rx_elec_idle_wire[1] : 1'b1 ;
assign pipe_rx2_elec_idle = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_elec_idle_wire[2] : 1'b1 ;
assign pipe_rx3_elec_idle = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_elec_idle_wire[3] : 1'b1 ;
assign pipe_rx4_elec_idle = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_elec_idle_wire[4] : 1'b1 ;
assign pipe_rx5_elec_idle = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_elec_idle_wire[5] : 1'b1 ;
assign pipe_rx6_elec_idle = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_elec_idle_wire[6] : 1'b1 ;
assign pipe_rx7_elec_idle = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_elec_idle_wire[7] : 1'b1 ;
assign pipe_rx0_valid = gt_rx_valid_wire[0];
assign pipe_rx1_valid = (LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? gt_rx_valid_wire[1] : 1'b0 ;
assign pipe_rx2_valid = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_valid_wire[2] : 1'b0 ;
assign pipe_rx3_valid = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_valid_wire[3] : 1'b0 ;
assign pipe_rx4_valid = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_valid_wire[4] : 1'b0 ;
assign pipe_rx5_valid = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_valid_wire[5] : 1'b0 ;
assign pipe_rx6_valid = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_valid_wire[6] : 1'b0 ;
assign pipe_rx7_valid = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_valid_wire[7] : 1'b0 ;
assign gt_rx_polarity[0] = pipe_rx0_polarity;
assign gt_rx_polarity[1] = pipe_rx1_polarity;
assign gt_rx_polarity[2] = pipe_rx2_polarity;
assign gt_rx_polarity[3] = pipe_rx3_polarity;
assign gt_rx_polarity[4] = pipe_rx4_polarity;
assign gt_rx_polarity[5] = pipe_rx5_polarity;
assign gt_rx_polarity[6] = pipe_rx6_polarity;
assign gt_rx_polarity[7] = pipe_rx7_polarity;
assign gt_power_down[ 1: 0] = pipe_tx0_powerdown;
assign gt_power_down[ 3: 2] = pipe_tx1_powerdown;
assign gt_power_down[ 5: 4] = pipe_tx2_powerdown;
assign gt_power_down[ 7: 6] = pipe_tx3_powerdown;
assign gt_power_down[ 9: 8] = pipe_tx4_powerdown;
assign gt_power_down[11:10] = pipe_tx5_powerdown;
assign gt_power_down[13:12] = pipe_tx6_powerdown;
assign gt_power_down[15:14] = pipe_tx7_powerdown;
assign gt_tx_char_disp_mode = {pipe_tx7_compliance,
pipe_tx6_compliance,
pipe_tx5_compliance,
pipe_tx4_compliance,
pipe_tx3_compliance,
pipe_tx2_compliance,
pipe_tx1_compliance,
pipe_tx0_compliance};
assign gt_tx_data_k = {2'd0,
pipe_tx7_char_is_k,
2'd0,
pipe_tx6_char_is_k,
2'd0,
pipe_tx5_char_is_k,
2'd0,
pipe_tx4_char_is_k,
2'd0,
pipe_tx3_char_is_k,
2'd0,
pipe_tx2_char_is_k,
2'd0,
pipe_tx1_char_is_k,
2'd0,
pipe_tx0_char_is_k};
assign gt_tx_data = {16'd0,
pipe_tx7_data,
16'd0,
pipe_tx6_data,
16'd0,
pipe_tx5_data,
16'd0,
pipe_tx4_data,
16'd0,
pipe_tx3_data,
16'd0,
pipe_tx2_data,
16'd0,
pipe_tx1_data,
16'd0,
pipe_tx0_data};
assign gt_tx_detect_rx_loopback = pipe_tx_rcvr_det;
assign gt_tx_elec_idle = {pipe_tx7_elec_idle,
pipe_tx6_elec_idle,
pipe_tx5_elec_idle,
pipe_tx4_elec_idle,
pipe_tx3_elec_idle,
pipe_tx2_elec_idle,
pipe_tx1_elec_idle,
pipe_tx0_elec_idle};
always @(posedge pipe_clk_int or negedge clock_locked) begin
if (!clock_locked)
reg_clock_locked <= #TCQ 1'b0;
else
reg_clock_locked <= #TCQ 1'b1;
end
always @(posedge pipe_clk_int) begin
if (!reg_clock_locked)
phy_rdy_n_int <= #TCQ 1'b0;
else
phy_rdy_n_int <= #TCQ all_phystatus_rst;
end
assign all_phystatus_rst = (&phystatus_rst[LINK_CAP_MAX_LINK_WIDTH-1:0]);
assign phy_rdy_n = phy_rdy_n_int;
endmodule
|
//////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Ramdac Blank Generator
// File : blnk.v
// Author : Frank Bruno
// Created : 29-Dec-2005
// RCS File : $Source:$
// Status : $Id:$
//
//////////////////////////////////////////////////////////////////////////////
//
// Description :
// This module Process Active lines and frames and generates the
// controls for the pipeline, the active cursor display.
//
/////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
//
//////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module blnk
(
input pixclk,
input reset,
input blankx,
input misr_cntl,
input red_comp,
input grn_comp,
input blu_comp,
input vga_en,
output reg vsync,
output hsync,
output reg vsync_m1,
output reg misr_done,
output enable_crc,
output reg init_crc,
output reg lred_comp,
output reg lgrn_comp,
output reg lblu_comp,
output reg blankx4d,
output reg blankx6
);
// level changes required to support FDP
reg blankx5,
blankx1,
blankx2,
blankx3,
blankx4,
blankx4a,
blankx4b,
blankx4c,
enable_crc_i,
misr_cntl1,
misr_cntl2,
vsync1;
reg [11:0] pix_counter;
assign enable_crc = enable_crc_i & blankx6;
assign hsync = !blankx;
//---------DAC SNS controls-----------
always @(posedge pixclk or negedge reset)
if (!reset) begin
lblu_comp <= 1'b0;
lgrn_comp <= 1'b0;
lred_comp <= 1'b0;
end else if(!blankx5) begin // synchronized to the pipe
lblu_comp <= blu_comp;
lgrn_comp <= grn_comp;
lred_comp <= red_comp;
end
// generate pipelined blank control
always @(posedge pixclk or negedge reset) begin
if (!reset) begin
blankx1 <= 1'b0;
blankx2 <= 1'b0;
blankx3 <= 1'b0;
blankx4 <= 1'b0;
blankx4a <= 1'b0;
blankx4b <= 1'b0;
blankx4c <= 1'b0;
blankx4d <= 1'b0;
blankx5 <= 1'b0;
blankx6 <= 1'b0;
vsync1 <= 1'b0;
misr_cntl1 <= 1'b0;
misr_cntl2 <= 1'b0;
end else begin
misr_cntl1 <= misr_cntl;
misr_cntl2 <= misr_cntl1;
vsync1 <= vsync;
blankx1 <= blankx;
blankx2 <= blankx1;
blankx3 <= blankx2;
blankx4 <= blankx3;
blankx4a <= blankx4;
blankx4b <= blankx4a;
blankx4c <= blankx4b;
blankx4d <= (vga_en) ? blankx4c : blankx4; // FB: added to match new pip stage in pixel_dp
blankx5 <= blankx4d;
blankx6 <= blankx5;
end
end
// detect lines , vsync
always @(posedge pixclk or negedge reset)
if (!reset) pix_counter <= 12'h0;
else if (blankx == 1) pix_counter <= 12'h0; // reset pixel counter
else pix_counter <= pix_counter + 12'b1; // run pixel counter
always @(posedge pixclk or negedge reset) begin
if (!reset) vsync<= 1'b0;
// turn off vsync
else if (blankx == 1) vsync <= 1'b0;
// turn off vsync
else if ((blankx == 0) & (pix_counter == 12'd2050)) vsync <= 1'b1;
end
//-----------------------------------
always @(posedge pixclk or negedge reset) begin
if (!reset) vsync_m1 <= 1'b0;
// turn off vsync
else if (blankx == 1) vsync_m1 <= 1'b0;
// turn off vsync
else if ((blankx == 0) & (pix_counter == 12'd2049))vsync_m1 <= 1'b1;
end
//----------misr controls------------
always @(posedge pixclk or negedge reset) begin
if (!reset) init_crc <= 1'b0;
else if (vsync1 & !vsync & misr_cntl2) init_crc <= 1'b1;
else init_crc <= 1'b0; // one pulse crc
end
//----------misr controls------------
always @(posedge pixclk or negedge reset) begin
if (!reset) enable_crc_i <= 1'b0;
else if (init_crc) enable_crc_i <= 1'b1;
// stop at the next frame.
else if (vsync & !vsync1) enable_crc_i <= 1'b0;
end
//----------misr controls------------
always @(posedge pixclk or negedge reset) begin
if (!reset) misr_done <= 1'b0;
// reset at start of frame
else if (vsync1 & !vsync) misr_done <= 1'b0;
else if (enable_crc_i & vsync & !vsync1) misr_done <= 1'b1;
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_11_0_pcie_brams_7x.v
// Version : 1.11
// Description : pcie bram wrapper
// arrange and connect brams
// implement address decoding, datapath muxing and pipeline stages
//
// banks of brams are used for 1,2,4,8,18 brams
// brams are stacked for other values of NUM_BRAMS
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
module pcie_7x_v1_11_0_pcie_brams_7x
#(
parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1, // PCIe Link Speed : 1 - 2.5 GT/s; 2 - 5.0 GT/s
parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08, // PCIe Link Width : 1 / 2 / 4 / 8
parameter IMPL_TARGET = "HARD", // the implementation target : HARD, SOFT
// the number of BRAMs to use
// supported values are:
// 1,2,4,8,18
parameter NUM_BRAMS = 0,
// BRAM read address latency
//
// value meaning
// ====================================================
// 0 BRAM read address port sample
// 1 BRAM read address port sample and a pipeline stage on the address port
parameter RAM_RADDR_LATENCY = 1,
// BRAM read data latency
//
// value meaning
// ====================================================
// 1 no BRAM OREG
// 2 use BRAM OREG
// 3 use BRAM OREG and a pipeline stage on the data port
parameter RAM_RDATA_LATENCY = 1,
// BRAM write latency
// The BRAM write port is synchronous
//
// value meaning
// ====================================================
// 0 BRAM write port sample
// 1 BRAM write port sample plus pipeline stage
parameter RAM_WRITE_LATENCY = 1
)
(
input user_clk_i,
input reset_i,
input wen,
input [12:0] waddr,
input [71:0] wdata,
input ren,
input rce,
input [12:0] raddr,
output [71:0] rdata
);
// turn on the bram output register
localparam DOB_REG = (RAM_RDATA_LATENCY > 1) ? 1 : 0;
// calculate the data width of the individual brams
localparam [6:0] WIDTH = ((NUM_BRAMS == 1) ? 72 :
(NUM_BRAMS == 2) ? 36 :
(NUM_BRAMS == 4) ? 18 :
(NUM_BRAMS == 8) ? 9 :
4
);
parameter TCQ = 1;
wire wen_int;
wire [12:0] waddr_int;
wire [71:0] wdata_int;
wire ren_int;
wire [12:0] raddr_int;
wire [71:0] rdata_int;
//synthesis translate_off
initial
begin
$display("[%t] %m NUM_BRAMS %0d DOB_REG %0d WIDTH %0d RAM_WRITE_LATENCY %0d RAM_RADDR_LATENCY %0d RAM_RDATA_LATENCY %0d",
$time, NUM_BRAMS, DOB_REG, WIDTH, RAM_WRITE_LATENCY, RAM_RADDR_LATENCY, RAM_RDATA_LATENCY);
case (NUM_BRAMS)
1,2,4,8,18:;
default:
begin
$display("[%t] %m Error NUM_BRAMS %0d not supported", $time, NUM_BRAMS);
$finish;
end
endcase // case(NUM_BRAMS)
case (RAM_RADDR_LATENCY)
0,1:;
default:
begin
$display("[%t] %m Error RAM_READ_LATENCY %0d not supported", $time, RAM_RADDR_LATENCY);
$finish;
end
endcase // case (RAM_RADDR_LATENCY)
case (RAM_RDATA_LATENCY)
1,2,3:;
default:
begin
$display("[%t] %m Error RAM_READ_LATENCY %0d not supported", $time, RAM_RDATA_LATENCY);
$finish;
end
endcase // case (RAM_RDATA_LATENCY)
case (RAM_WRITE_LATENCY)
0,1:;
default:
begin
$display("[%t] %m Error RAM_WRITE_LATENCY %0d not supported", $time, RAM_WRITE_LATENCY);
$finish;
end
endcase // case(RAM_WRITE_LATENCY)
end
//synthesis translate_on
// model the delays for ram write latency
generate if (RAM_WRITE_LATENCY == 1) begin : wr_lat_2
reg wen_q;
reg [12:0] waddr_q;
reg [71:0] wdata_q;
always @(posedge user_clk_i) begin
if (reset_i)
begin
wen_q <= #TCQ 1'b0;
waddr_q <= #TCQ 13'b0;
// Disable Reset on Data Path @ BRAM i/f as I/O come from PCIe HB.
// wdata_q <= #TCQ 72'b0;
end
else
begin
wen_q <= #TCQ wen;
waddr_q <= #TCQ waddr;
wdata_q <= #TCQ wdata;
end
end
assign wen_int = wen_q;
assign waddr_int = waddr_q;
assign wdata_int = wdata_q;
end // if (RAM_WRITE_LATENCY == 1)
else if (RAM_WRITE_LATENCY == 0) begin : wr_lat_1
assign wen_int = wen;
assign waddr_int = waddr;
assign wdata_int = wdata;
end
endgenerate
// model the delays for ram read latency
generate if (RAM_RADDR_LATENCY == 1) begin : raddr_lat_2
reg ren_q;
reg [12:0] raddr_q;
always @(posedge user_clk_i) begin
if (reset_i)
begin
ren_q <= #TCQ 1'b0;
raddr_q <= #TCQ 13'b0;
end
else
begin
ren_q <= #TCQ ren;
raddr_q <= #TCQ raddr;
end // else: !if(reset_i)
end
assign ren_int = ren_q;
assign raddr_int = raddr_q;
end // block: rd_lat_addr_2
else begin : raddr_lat_1
assign ren_int = ren;
assign raddr_int = raddr;
end
endgenerate
generate if (RAM_RDATA_LATENCY == 3) begin : rdata_lat_3
reg [71:0] rdata_q;
always @(posedge user_clk_i) begin
// Disable Reset on Data Path @ BRAM i/f as I/O come from PCIe HB.
//if (reset_i)
//begin
// rdata_q <= #TCQ 72'b0;
//end
//else
//begin
rdata_q <= #TCQ rdata_int;
//end // else: !if(reset_i)
end
assign rdata = rdata_q;
end // block: rd_lat_data_3
else begin : rdata_lat_1_2
assign rdata = rdata_int;
end
endgenerate
// instantiate the brams
generate
genvar ii;
for (ii = 0; ii < NUM_BRAMS; ii = ii + 1) begin : brams
pcie_7x_v1_11_0_pcie_bram_7x #(
.LINK_CAP_MAX_LINK_WIDTH(LINK_CAP_MAX_LINK_WIDTH),
.LINK_CAP_MAX_LINK_SPEED(LINK_CAP_MAX_LINK_SPEED),
.IMPL_TARGET (IMPL_TARGET),
.DOB_REG (DOB_REG),
.WIDTH (WIDTH)
)
ram (
.user_clk_i(user_clk_i),
.reset_i(reset_i),
.wen_i(wen_int),
.waddr_i(waddr_int),
.wdata_i(wdata_int[(((ii + 1) * WIDTH) - 1): (ii * WIDTH)]),
.ren_i(ren_int),
.raddr_i(raddr_int),
.rdata_o(rdata_int[(((ii + 1) * WIDTH) - 1): (ii * WIDTH)]),
.rce_i(rce)
);
end
endgenerate
endmodule // pcie_brams_7x
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NOR2_PP_BLACKBOX_V
`define SKY130_FD_SC_HVL__NOR2_PP_BLACKBOX_V
/**
* nor2: 2-input NOR.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__nor2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NOR2_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A222OI_TB_V
`define SKY130_FD_SC_LS__A222OI_TB_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a222oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg C1;
reg C2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
C1 = 1'bX;
C2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 C1 = 1'b0;
#120 C2 = 1'b0;
#140 VGND = 1'b0;
#160 VNB = 1'b0;
#180 VPB = 1'b0;
#200 VPWR = 1'b0;
#220 A1 = 1'b1;
#240 A2 = 1'b1;
#260 B1 = 1'b1;
#280 B2 = 1'b1;
#300 C1 = 1'b1;
#320 C2 = 1'b1;
#340 VGND = 1'b1;
#360 VNB = 1'b1;
#380 VPB = 1'b1;
#400 VPWR = 1'b1;
#420 A1 = 1'b0;
#440 A2 = 1'b0;
#460 B1 = 1'b0;
#480 B2 = 1'b0;
#500 C1 = 1'b0;
#520 C2 = 1'b0;
#540 VGND = 1'b0;
#560 VNB = 1'b0;
#580 VPB = 1'b0;
#600 VPWR = 1'b0;
#620 VPWR = 1'b1;
#640 VPB = 1'b1;
#660 VNB = 1'b1;
#680 VGND = 1'b1;
#700 C2 = 1'b1;
#720 C1 = 1'b1;
#740 B2 = 1'b1;
#760 B1 = 1'b1;
#780 A2 = 1'b1;
#800 A1 = 1'b1;
#820 VPWR = 1'bx;
#840 VPB = 1'bx;
#860 VNB = 1'bx;
#880 VGND = 1'bx;
#900 C2 = 1'bx;
#920 C1 = 1'bx;
#940 B2 = 1'bx;
#960 B1 = 1'bx;
#980 A2 = 1'bx;
#1000 A1 = 1'bx;
end
sky130_fd_sc_ls__a222oi dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .C2(C2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A222OI_TB_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 13 12:43:39 2017
// Host : WK117 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_xbar_0/system_xbar_0_stub.v
// Design : system_xbar_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35ticsg324-1L
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_crossbar_v2_1_12_axi_crossbar,Vivado 2016.4" *)
module system_xbar_0(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize,
m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awregion, m_axi_awqos,
m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wvalid,
m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_arid, m_axi_araddr,
m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot,
m_axi_arregion, m_axi_arqos, m_axi_arvalid, m_axi_arready, m_axi_rid, m_axi_rdata,
m_axi_rresp, m_axi_rlast, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[1:0],s_axi_awaddr[63:0],s_axi_awlen[15:0],s_axi_awsize[5:0],s_axi_awburst[3:0],s_axi_awlock[1:0],s_axi_awcache[7:0],s_axi_awprot[5:0],s_axi_awqos[7:0],s_axi_awvalid[1:0],s_axi_awready[1:0],s_axi_wdata[255:0],s_axi_wstrb[31:0],s_axi_wlast[1:0],s_axi_wvalid[1:0],s_axi_wready[1:0],s_axi_bid[1:0],s_axi_bresp[3:0],s_axi_bvalid[1:0],s_axi_bready[1:0],s_axi_arid[1:0],s_axi_araddr[63:0],s_axi_arlen[15:0],s_axi_arsize[5:0],s_axi_arburst[3:0],s_axi_arlock[1:0],s_axi_arcache[7:0],s_axi_arprot[5:0],s_axi_arqos[7:0],s_axi_arvalid[1:0],s_axi_arready[1:0],s_axi_rid[1:0],s_axi_rdata[255:0],s_axi_rresp[3:0],s_axi_rlast[1:0],s_axi_rvalid[1:0],s_axi_rready[1:0],m_axi_awid[0:0],m_axi_awaddr[31:0],m_axi_awlen[7:0],m_axi_awsize[2:0],m_axi_awburst[1:0],m_axi_awlock[0:0],m_axi_awcache[3:0],m_axi_awprot[2:0],m_axi_awregion[3:0],m_axi_awqos[3:0],m_axi_awvalid[0:0],m_axi_awready[0:0],m_axi_wdata[127:0],m_axi_wstrb[15:0],m_axi_wlast[0:0],m_axi_wvalid[0:0],m_axi_wready[0:0],m_axi_bid[0:0],m_axi_bresp[1:0],m_axi_bvalid[0:0],m_axi_bready[0:0],m_axi_arid[0:0],m_axi_araddr[31:0],m_axi_arlen[7:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arlock[0:0],m_axi_arcache[3:0],m_axi_arprot[2:0],m_axi_arregion[3:0],m_axi_arqos[3:0],m_axi_arvalid[0:0],m_axi_arready[0:0],m_axi_rid[0:0],m_axi_rdata[127:0],m_axi_rresp[1:0],m_axi_rlast[0:0],m_axi_rvalid[0:0],m_axi_rready[0:0]" */;
input aclk;
input aresetn;
input [1:0]s_axi_awid;
input [63:0]s_axi_awaddr;
input [15:0]s_axi_awlen;
input [5:0]s_axi_awsize;
input [3:0]s_axi_awburst;
input [1:0]s_axi_awlock;
input [7:0]s_axi_awcache;
input [5:0]s_axi_awprot;
input [7:0]s_axi_awqos;
input [1:0]s_axi_awvalid;
output [1:0]s_axi_awready;
input [255:0]s_axi_wdata;
input [31:0]s_axi_wstrb;
input [1:0]s_axi_wlast;
input [1:0]s_axi_wvalid;
output [1:0]s_axi_wready;
output [1:0]s_axi_bid;
output [3:0]s_axi_bresp;
output [1:0]s_axi_bvalid;
input [1:0]s_axi_bready;
input [1:0]s_axi_arid;
input [63:0]s_axi_araddr;
input [15:0]s_axi_arlen;
input [5:0]s_axi_arsize;
input [3:0]s_axi_arburst;
input [1:0]s_axi_arlock;
input [7:0]s_axi_arcache;
input [5:0]s_axi_arprot;
input [7:0]s_axi_arqos;
input [1:0]s_axi_arvalid;
output [1:0]s_axi_arready;
output [1:0]s_axi_rid;
output [255:0]s_axi_rdata;
output [3:0]s_axi_rresp;
output [1:0]s_axi_rlast;
output [1:0]s_axi_rvalid;
input [1:0]s_axi_rready;
output [0:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awregion;
output [3:0]m_axi_awqos;
output [0:0]m_axi_awvalid;
input [0:0]m_axi_awready;
output [127:0]m_axi_wdata;
output [15:0]m_axi_wstrb;
output [0:0]m_axi_wlast;
output [0:0]m_axi_wvalid;
input [0:0]m_axi_wready;
input [0:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_bvalid;
output [0:0]m_axi_bready;
output [0:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arregion;
output [3:0]m_axi_arqos;
output [0:0]m_axi_arvalid;
input [0:0]m_axi_arready;
input [0:0]m_axi_rid;
input [127:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input [0:0]m_axi_rlast;
input [0:0]m_axi_rvalid;
output [0:0]m_axi_rready;
endmodule
|
/*
* Copyright (c) 2011-2012 Travis Geiselbrecht
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
* (the "Software"), to deal in the Software without restriction,
* including without limitation the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
module seven_segment
(
input [3:0] in,
output reg [6:0] led
);
always @ (in)
begin
case (in)
0: led = 7'b1000000;
1: led = 7'b1111001;
2: led = 7'b0100100;
3: led = 7'b0110000;
4: led = 7'b0011001;
5: led = 7'b0010010;
6: led = 7'b0000010;
7: led = 7'b1111000;
8: led = 7'b0000000;
9: led = 7'b0011000;
10: led = 7'b0001000;
11: led = 7'b0000011;
12: led = 7'b1000110;
13: led = 7'b0100001;
14: led = 7'b0000110;
15: led = 7'b0001110;
endcase
end
endmodule // led
|
module xyz (/*AUTOARG*/
// Outputs
signal_f, signal_c,
// Inputs
signal_e3, signal_b
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [2:0] signal_b; // To u_abc of abc.v
input signal_e3; // To u_def of def.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output signal_c; // From u_abc of abc.v
output signal_f; // From u_def of def.v
// End of automatics
/*AUTOWIRE*/
/* abc AUTO_TEMPLATE
(
// Outputs
.signal_c (signal_c),
// Inputs
.signal_a (signal_f), // AUTONOHOOKUP
.signal_b (signal_b[2:0]));
*/
abc u_abc
(/*AUTOINST*/
// Outputs
.signal_c (signal_c), // Templated
// Inputs
.signal_a (signal_f), // Templated AUTONOHOOKUP
.signal_b (signal_b[2:0])); // Templated
/* def AUTO_TEMPLATE
(// Outputs
.signal_f (signal_f),
// Inputs
.signal_d (signal_c), // AUTONOHOOKUP
.signal_e (signal_e), // AUTONOHOOKUP
.signal_e2 (signal_e2), // AUTONOHOOKUP
.signal_e3 ((signal_e3)),
);
*/
def u_def
(/*AUTOINST*/
// Outputs
.signal_f (signal_f), // Templated
// Inputs
.signal_d (signal_c), // Templated AUTONOHOOKUP
.signal_e (signal_e), // Templated AUTONOHOOKUP
.signal_e2 (signal_e2), // Templated AUTONOHOOKUP
.signal_e3 ((signal_e3))); // Templated
endmodule // xyz
module abc (/*AUTOARG*/
// Outputs
signal_c,
// Inputs
signal_a, signal_b
);
input [1:0] signal_a;
input [2:0] signal_b;
output signal_c;
endmodule // abc
module def (/*AUTOARG*/
// Outputs
signal_f,
// Inputs
signal_d, signal_e, signal_e2, signal_e3
);
input [1:0] signal_d;
input [2:0] signal_e;
input [3:0] signal_e2;
input [3:0] signal_e3;
output signal_f;
endmodule // def
|
`include "assert.vh"
`include "cpu.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 4;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("f64.reinterpret-i64.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
parameter HAS_FPU = 1;
parameter USE_64B = 1;
reg reset = 0;
wire [63:0] result;
wire [ 1:0] result_type;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.HAS_FPU(HAS_FPU),
.USE_64B(USE_64B),
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_type(result_type),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("f64.reinterpret-i64_tb.vcd");
$dumpvars(0, cpu_tb);
if(USE_64B) begin
#18
`assert(result, 64'hc000000000000000);
`assert(result_type, `f64);
`assert(result_empty, 0);
end
else begin
#12
`assert(trap, `NO_64B);
end
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__XNOR3_4_V
`define SKY130_FD_SC_MS__XNOR3_4_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog wrapper for xnor3 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__xnor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__xnor3_4 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__xnor3_4 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__XNOR3_4_V
|
module latch_mem_wb (
input clock ,
input reset ,
input [ 5:0] stall ,
input mem_register_write_enable ,
output reg wb_register_write_enable ,
input [ 4:0] mem_register_write_address ,
output reg [ 4:0] wb_register_write_address ,
input [31:0] mem_register_write_data ,
output reg [31:0] wb_register_write_data ,
input mem_register_hi_write_enable,
output reg wb_register_hi_write_enable ,
input [31:0] mem_register_hi_write_data ,
output reg [31:0] wb_register_hi_write_data ,
input mem_register_lo_write_enable,
output reg wb_register_lo_write_enable ,
input [31:0] mem_register_lo_write_data ,
output reg [31:0] wb_register_lo_write_data
);
always @ (posedge clock) begin
if (reset == `RESET_ENABLE || (stall[4] == `STALL_ENABLE && stall[5] == `STALL_DISABLE)) begin
wb_register_write_enable <= `WRITE_DISABLE;
wb_register_write_address <= 5'b0 ;
wb_register_write_data <= 32'b0 ;
wb_register_hi_write_enable <= `WRITE_DISABLE;
wb_register_hi_write_data <= 32'b0 ;
wb_register_lo_write_enable <= `WRITE_DISABLE;
wb_register_lo_write_data <= 32'b0 ;
end
else if (stall[4] == `STALL_DISABLE) begin
wb_register_write_enable <= mem_register_write_enable ;
wb_register_write_address <= mem_register_write_address ;
wb_register_write_data <= mem_register_write_data ;
wb_register_hi_write_enable <= mem_register_hi_write_enable;
wb_register_hi_write_data <= mem_register_hi_write_data ;
wb_register_lo_write_enable <= mem_register_lo_write_enable;
wb_register_lo_write_data <= mem_register_lo_write_data ;
end
end
endmodule |
`timescale 1ns / 1ps
/*
-- Module Name: Test Engine Core
-- Description: Nucleo para pruebas funcionales del acelerador basado
en multiples nucleos.
El objetivo del modulo no es llevar a cabo procesamiento
util, solo el generar modificaciones a un set de datos
pre definido.
El procesamiento esta dividido en diferentes rondas de
trabajo. El nuemero de rondas por prueba puede ser
modificado mediante el parametro ROUNDS. El proceso se
lleva a cabo en 2 registros definidos wordA y wordB.
El procesamiento esta definido por:
* wordA: wordA ^ swap(wordB)
* wordB: wordA
-- Dependencies: -- none
-- Parameters: -- ROUNDS: Numero de rondas de procesamiento que
se llevaran a cabo sobre un set de datos
-- Original Author: Héctor Cabrera
-- Current Author:
-- History:
-- Creacion 29 de noviembre 2015
*/
module test_engine #(
parameter ROUNDS = 16
)
(
input wire clk,
input wire reset,
// -- inputs ------------------------------------------------- >>>>>
input wire start_strobe_din,
input wire [63:0] wordA_din,
input wire [63:0] wordB_din,
// -- outputs ------------------------------------------------ >>>>>
output wire done_strobe_dout,
output wire active_test_engine_dout,
output wire [63:0] wordC_dout,
output wire [63:0] wordD_dout
);
// -- Local parameters ------------------------------------------- >>>>>
localparam IDLE = 1'b0;
localparam ACTIVE = 1'b1;
localparam RND_WIDTH = clog2(ROUNDS);
// -- Controlpath ------------------------------------------------ >>>>>
/*-- Contador de rondas -------------------------------------- >>>>>
-- Descripcion: Contador de rondas. El numero de rondas que se
han llevado a cabo durante la ejecucion en
curso.
El contador ejecuta la cuenta de manera inversa,
terminando su operacion al llegar a 0.
// -------------------------------------------------------------- */
reg [RND_WIDTH-1:0] round_counter_reg;
wire [RND_WIDTH-1:0] round_counter_next;
// -- Elemento de memoria ------------------------------- >>>>>
always @(posedge clk)
if (reset)
round_counter_reg <= ROUNDS;
else
round_counter_reg <= round_counter_next;
// -- Logica de estado siguiente ------------------------- >>>>>
assign round_counter_next = (state_reg == ACTIVE && state_next == ACTIVE) ? round_counter_reg - 1'b1 :
(state_reg == ACTIVE && state_next == IDLE) ? ROUNDS :
round_counter_reg;
// -- FSM ---------------------------------------------------- >>>>>
/* -- Elementos de memoria ------------------------------- >>>>>
-- Descripcion: Maquina de estados para el control de flujo
de datos a travez del datapath. Solo se
tienen 2 estados: IDLE y ACTIVE.
IDLE: Estado de reposo. No se lleva a cabo
trabajo durante este estado.
ACTIVE: Estado de trabajo, se ejecuta
durante ROUNDS + 1 ciclos de reloj.
El ciclo extra se utiliza para la
captura de los nuevos datos de
trabajo, los restantes son para el
procesamiento de los datos.
// ---------------------------------------------------------- */
reg state_reg;
reg state_next;
always @(posedge clk)
if (reset)
state_reg <= IDLE;
else
state_reg <= state_next;
// -- State Next logic ----------------------------------- >>>>>
always @(*)
begin
state_next = state_reg;
case (state_reg)
IDLE:
if (start_strobe_din)
state_next = ACTIVE;
ACTIVE:
if (~|round_counter_reg)
state_next = IDLE;
endcase
end
/* -- Logica de salida ---------------------------------- >>>>>
-- Descripcion: Señales de salida para datapath y para fuera
del modulo.
active_test_engine: indicador que el
nucleo se encuentra dentro de un loop de
procesamiento.
word_ena: Habilitador de registros de
trabajo (wordA y wordB).
done_strobe: pulso de finalizacion de
loop de procesamiento. Indica que los
datos en los puertos de salida wordC y
wordD son validos.
// ---------------------------------------------------------- */
wire word_ena;
assign active_test_engine_dout = (state_reg == ACTIVE) ? 1'b1 : 1'b0;
assign word_ena = (state_next == ACTIVE) ? 1'b1 : 1'b0;
assign done_strobe_dout = (state_reg == ACTIVE && state_next == IDLE) ? 1'b1 : 1'b0;
// -- Datapath --------------------------------------------------- >>>>>
// -- Registers ---------------------------------------------- >>>>>
reg [63:0] wordA_reg;
wire [63:0] wordA_next;
reg [63:0] wordB_reg;
wire [63:0] wordB_next;
// -- Registros A y B ---------------------------------------- >>>>>
always @(posedge clk)
if (word_ena)
wordA_reg <= wordA_next;
always @(posedge clk)
if (word_ena)
wordB_reg <= wordB_next;
/* -- Next State Logic --------------------------------------- >>>>>
-- Descripcion: Multiplexores para la seleccion de nuevos
valores para los registros de trabajo.
// -------------------------------------------------------------- */
assign wordA_next = (start_strobe_din) ? wordA_din : wordA_reg ^ {wordB_reg[31:0], wordB_reg[63:32]};
assign wordB_next = (start_strobe_din) ? wordB_din : wordA_reg;
// -- Salidas ------------------------------------------------ >>>>>
assign wordC_dout = wordA_reg;
assign wordD_dout = wordB_reg;
// -- Codigo no sintetizable ------------------------------------- >>>>>
// -- Funciones ---------------------------------------------- >>>>>
// Funcion de calculo: log2(x) ---------------------- >>>>>
function integer clog2;
input integer depth;
for (clog2=0; depth>0; clog2=clog2+1)
depth = depth >> 1;
endfunction
endmodule
/* -- Plantilla de instancia ------------------------------------ >>>>>>
reg clk;
reg reset;
reg start_strobe_din;
reg [63:0] wordA;
reg [63:0] wordB;
wire done_strobe;
wire active_test_engine;
wire [63:0] wordC;
wire [63:0] wordD;
test_engine
#(
.ROUNDS(16)
)
test_engine
(
.clk (clk),
.reset (reset),
// -- inputs ------------------------------------------------- >>>>>
.start_strobe_din (start_strobe),
.wordA_din (wordA),
.wordB_din (wordB),
// -- outputs ------------------------------------------------ >>>>>
.done_strobe_dout (done_strobe),
.active_test_engine_dout (active_test_engine),
.wordC_dout (wordC),
.wordD_dout (wordD)
);
// ------------------------------------------------------------------ */ |
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Down-Sizer
// Down-Sizer for generic SI- and MI-side data widths. This module instantiates
// Address, Write Data, Write Response and Read Data Down-Sizer modules, each one taking care
// of the channel specific tasks.
// The Address Down-Sizer can handle both AR and AW channels.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// downsizer
// a_downsizer
// axic_fifo
// fifo_gen
// fifo_coregen
// w_downsizer
// b_downsizer
// r_downsizer
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_dwidth_converter_v2_1_9_axi_downsizer #
(
parameter C_FAMILY = "none",
// FPGA Family.
parameter integer C_AXI_PROTOCOL = 0,
// Protocol of SI and MI (0=AXI4, 1=AXI3).
parameter integer C_S_AXI_ID_WIDTH = 1,
// Width of all ID signals on SI side of converter.
// Range: 1 - 32.
parameter integer C_SUPPORTS_ID = 0,
// Indicates whether SI-side ID needs to be stored and compared.
// 0 = No, SI is single-threaded, propagate all transactions.
// 1 = Yes, stall any transaction with ID different than outstanding transactions.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI.
// Range (AXI4, AXI3): 12 - 64.
parameter integer C_S_AXI_DATA_WIDTH = 64,
// Width of s_axi_wdata and s_axi_rdata.
// Range: 64, 128, 256, 512, 1024.
parameter integer C_M_AXI_DATA_WIDTH = 32,
// Width of m_axi_wdata and m_axi_rdata.
// Assume always smaller than C_S_AXI_DATA_WIDTH.
// Range: 32, 64, 128, 256, 512.
// S_DATA_WIDTH = M_DATA_WIDTH not allowed.
parameter integer C_AXI_SUPPORTS_WRITE = 1,
parameter integer C_AXI_SUPPORTS_READ = 1,
parameter integer C_MAX_SPLIT_BEATS = 256
// Max burst length after transaction splitting.
// Range: 0 (no splitting), 1 (convert to singles), 16, 256.
)
(
// Global Signals
input wire aresetn,
input wire aclk,
// Slave Interface Write Address Ports
input wire [C_S_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [8-1:0] s_axi_awlen,
input wire [3-1:0] s_axi_awsize,
input wire [2-1:0] s_axi_awburst,
input wire [2-1:0] s_axi_awlock,
input wire [4-1:0] s_axi_awcache,
input wire [3-1:0] s_axi_awprot,
input wire [4-1:0] s_axi_awregion,
input wire [4-1:0] s_axi_awqos,
input wire s_axi_awvalid,
output wire s_axi_awready,
// Slave Interface Write Data Ports
input wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [C_S_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input wire s_axi_wlast,
input wire s_axi_wvalid,
output wire s_axi_wready,
// Slave Interface Write Response Ports
output wire [C_S_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [2-1:0] s_axi_bresp,
output wire s_axi_bvalid,
input wire s_axi_bready,
// Slave Interface Read Address Ports
input wire [C_S_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [8-1:0] s_axi_arlen,
input wire [3-1:0] s_axi_arsize,
input wire [2-1:0] s_axi_arburst,
input wire [2-1:0] s_axi_arlock,
input wire [4-1:0] s_axi_arcache,
input wire [3-1:0] s_axi_arprot,
input wire [4-1:0] s_axi_arregion,
input wire [4-1:0] s_axi_arqos,
input wire s_axi_arvalid,
output wire s_axi_arready,
// Slave Interface Read Data Ports
output wire [C_S_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [2-1:0] s_axi_rresp,
output wire s_axi_rlast,
output wire s_axi_rvalid,
input wire s_axi_rready,
// Master Interface Write Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [8-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [2-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire m_axi_awvalid,
input wire m_axi_awready,
// Master Interface Write Data Ports
output wire [C_M_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_M_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire m_axi_wvalid,
input wire m_axi_wready,
// Master Interface Write Response Ports
input wire [2-1:0] m_axi_bresp,
input wire m_axi_bvalid,
output wire m_axi_bready,
// Master Interface Read Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [8-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [2-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire m_axi_arvalid,
input wire m_axi_arready,
// Master Interface Read Data Ports
input wire [C_M_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire m_axi_rvalid,
output wire m_axi_rready
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
// Log2.
function integer log2
(
input integer x
);
integer acc;
begin
acc=0;
while ((2**acc) < x)
acc = acc + 1;
log2 = acc;
end
endfunction
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Log2 of number of 32bit word on SI-side.
localparam integer C_S_AXI_BYTES_LOG = log2(C_S_AXI_DATA_WIDTH/8);
// Log2 of number of 32bit word on MI-side.
localparam integer C_M_AXI_BYTES_LOG = log2(C_M_AXI_DATA_WIDTH/8);
// Log2 of Up-Sizing ratio for data.
localparam integer C_RATIO = C_S_AXI_DATA_WIDTH / C_M_AXI_DATA_WIDTH;
localparam integer C_RATIO_LOG = log2(C_RATIO);
localparam integer P_AXI_ADDR_WIDTH = (C_AXI_ADDR_WIDTH < 13) ? 13 : C_AXI_ADDR_WIDTH;
wire [P_AXI_ADDR_WIDTH-1:0] s_axi_awaddr_i;
wire [P_AXI_ADDR_WIDTH-1:0] s_axi_araddr_i;
wire [P_AXI_ADDR_WIDTH-1:0] m_axi_awaddr_i;
wire [P_AXI_ADDR_WIDTH-1:0] m_axi_araddr_i;
assign s_axi_awaddr_i = s_axi_awaddr;
assign s_axi_araddr_i = s_axi_araddr;
assign m_axi_awaddr = m_axi_awaddr_i[0 +: C_AXI_ADDR_WIDTH] ;
assign m_axi_araddr = m_axi_araddr_i[0 +: C_AXI_ADDR_WIDTH];
localparam integer P_AXI4 = 0;
localparam integer P_AXI3 = 1;
localparam integer P_AXILITE = 2;
localparam integer P_MAX_SPLIT_BEATS = (C_MAX_SPLIT_BEATS >= 16) ? C_MAX_SPLIT_BEATS :
(C_AXI_PROTOCOL == P_AXI4) ? 256 : 16;
localparam integer P_MAX_SPLIT_BEATS_LOG = log2(P_MAX_SPLIT_BEATS);
/////////////////////////////////////////////////////////////////////////////
// Handle Write Channels (AW/W/B)
/////////////////////////////////////////////////////////////////////////////
generate
if (C_AXI_SUPPORTS_WRITE == 1) begin : USE_WRITE
// Write Channel Signals for Commands Queue Interface.
wire wr_cmd_valid;
wire wr_cmd_split;
wire wr_cmd_mirror;
wire wr_cmd_fix;
wire [C_S_AXI_BYTES_LOG-1:0] wr_cmd_first_word;
wire [C_S_AXI_BYTES_LOG-1:0] wr_cmd_offset;
wire [C_S_AXI_BYTES_LOG-1:0] wr_cmd_mask;
wire [C_M_AXI_BYTES_LOG:0] wr_cmd_step;
wire [3-1:0] wr_cmd_size;
wire [8-1:0] wr_cmd_length;
wire wr_cmd_ready;
wire wr_cmd_b_valid;
wire wr_cmd_b_split;
wire [8-1:0] wr_cmd_b_repeat ;
wire wr_cmd_b_ready;
wire [C_S_AXI_ID_WIDTH-1:0] wr_cmd_b_id;
wire [8-1:0] s_axi_awlen_i;
wire [2-1:0] s_axi_awlock_i;
assign s_axi_awlen_i = (C_AXI_PROTOCOL == P_AXI3) ? {4'b0000, s_axi_awlen[3:0]}: s_axi_awlen;
assign s_axi_awlock_i = (C_AXI_PROTOCOL == P_AXI3) ? s_axi_awlock : {1'b0, s_axi_awlock[0]};
// Write Address Channel.
axi_dwidth_converter_v2_1_9_a_downsizer #
(
.C_FAMILY (C_FAMILY),
.C_AXI_PROTOCOL (C_AXI_PROTOCOL),
.C_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_SUPPORTS_ID (C_SUPPORTS_ID),
.C_AXI_ADDR_WIDTH (P_AXI_ADDR_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_AXI_CHANNEL (0),
.C_MAX_SPLIT_BEATS (P_MAX_SPLIT_BEATS),
.C_MAX_SPLIT_BEATS_LOG (P_MAX_SPLIT_BEATS_LOG),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG),
.C_RATIO_LOG (C_RATIO_LOG)
) write_addr_inst
(
// Global Signals
.ARESET (!aresetn),
.ACLK (aclk),
// Command Interface (W)
.cmd_valid (wr_cmd_valid),
.cmd_split (wr_cmd_split),
.cmd_mirror (wr_cmd_mirror),
.cmd_fix (wr_cmd_fix),
.cmd_first_word (wr_cmd_first_word),
.cmd_offset (wr_cmd_offset),
.cmd_mask (wr_cmd_mask),
.cmd_step (wr_cmd_step),
.cmd_size (wr_cmd_size),
.cmd_length (wr_cmd_length),
.cmd_ready (wr_cmd_ready),
// Command Interface (B)
.cmd_b_valid (wr_cmd_b_valid),
.cmd_b_split (wr_cmd_b_split),
.cmd_b_repeat (wr_cmd_b_repeat),
.cmd_b_ready (wr_cmd_b_ready),
.cmd_id (wr_cmd_b_id),
// Slave Interface Write Address Ports
.S_AXI_AID (s_axi_awid),
.S_AXI_AADDR (s_axi_awaddr_i),
.S_AXI_ALEN (s_axi_awlen_i),
.S_AXI_ASIZE (s_axi_awsize),
.S_AXI_ABURST (s_axi_awburst),
.S_AXI_ALOCK (s_axi_awlock_i),
.S_AXI_ACACHE (s_axi_awcache),
.S_AXI_APROT (s_axi_awprot),
.S_AXI_AREGION (s_axi_awregion),
.S_AXI_AQOS (s_axi_awqos),
.S_AXI_AVALID (s_axi_awvalid),
.S_AXI_AREADY (s_axi_awready),
// Master Interface Write Address Port
.M_AXI_AADDR (m_axi_awaddr_i),
.M_AXI_ALEN (m_axi_awlen),
.M_AXI_ASIZE (m_axi_awsize),
.M_AXI_ABURST (m_axi_awburst),
.M_AXI_ALOCK (m_axi_awlock),
.M_AXI_ACACHE (m_axi_awcache),
.M_AXI_APROT (m_axi_awprot),
.M_AXI_AREGION (m_axi_awregion),
.M_AXI_AQOS (m_axi_awqos),
.M_AXI_AVALID (m_axi_awvalid),
.M_AXI_AREADY (m_axi_awready)
);
// Write Data channel.
axi_dwidth_converter_v2_1_9_w_downsizer #
(
.C_FAMILY (C_FAMILY),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG),
.C_RATIO_LOG (C_RATIO_LOG)
) write_data_inst
(
// Global Signals
.ARESET (!aresetn),
.ACLK (aclk),
// Command Interface
.cmd_valid (wr_cmd_valid),
.cmd_mirror (wr_cmd_mirror),
.cmd_fix (wr_cmd_fix),
.cmd_first_word (wr_cmd_first_word),
.cmd_offset (wr_cmd_offset),
.cmd_mask (wr_cmd_mask),
.cmd_step (wr_cmd_step),
.cmd_size (wr_cmd_size),
.cmd_length (wr_cmd_length),
.cmd_ready (wr_cmd_ready),
// Slave Interface Write Data Ports
.S_AXI_WDATA (s_axi_wdata),
.S_AXI_WSTRB (s_axi_wstrb),
.S_AXI_WLAST (s_axi_wlast),
.S_AXI_WVALID (s_axi_wvalid),
.S_AXI_WREADY (s_axi_wready),
// Master Interface Write Data Ports
.M_AXI_WDATA (m_axi_wdata),
.M_AXI_WSTRB (m_axi_wstrb),
.M_AXI_WLAST (m_axi_wlast),
.M_AXI_WVALID (m_axi_wvalid),
.M_AXI_WREADY (m_axi_wready)
);
// Write Response channel.
if ( P_MAX_SPLIT_BEATS > 0 ) begin : USE_SPLIT
axi_dwidth_converter_v2_1_9_b_downsizer #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH)
) write_resp_inst
(
// Global Signals
.ARESET (!aresetn),
.ACLK (aclk),
// Command Interface
.cmd_valid (wr_cmd_b_valid),
.cmd_split (wr_cmd_b_split),
.cmd_repeat (wr_cmd_b_repeat),
.cmd_ready (wr_cmd_b_ready),
.cmd_id (wr_cmd_b_id),
// Slave Interface Write Response Ports
.S_AXI_BID (s_axi_bid),
.S_AXI_BRESP (s_axi_bresp),
.S_AXI_BVALID (s_axi_bvalid),
.S_AXI_BREADY (s_axi_bready),
// Master Interface Write Response Ports
.M_AXI_BRESP (m_axi_bresp),
.M_AXI_BVALID (m_axi_bvalid),
.M_AXI_BREADY (m_axi_bready)
);
end else begin : NO_SPLIT
assign s_axi_bid = wr_cmd_b_id;
assign s_axi_bresp = m_axi_bresp;
assign s_axi_bvalid = m_axi_bvalid;
assign m_axi_bready = s_axi_bready;
end
end else begin : NO_WRITE
// Slave Interface Write Address Ports
assign s_axi_awready = 1'b0;
// Slave Interface Write Data Ports
assign s_axi_wready = 1'b0;
// Slave Interface Write Response Ports
assign s_axi_bid = {C_S_AXI_ID_WIDTH{1'b0}};
assign s_axi_bresp = 2'b0;
assign s_axi_bvalid = 1'b0;
// Master Interface Write Address Port
assign m_axi_awaddr_i = {P_AXI_ADDR_WIDTH{1'b0}};
assign m_axi_awlen = 8'b0;
assign m_axi_awsize = 3'b0;
assign m_axi_awburst = 2'b0;
assign m_axi_awlock = 2'b0;
assign m_axi_awcache = 4'b0;
assign m_axi_awprot = 3'b0;
assign m_axi_awregion = 4'b0;
assign m_axi_awqos = 4'b0;
assign m_axi_awvalid = 1'b0;
// Master Interface Write Data Ports
assign m_axi_wdata = {C_M_AXI_DATA_WIDTH{1'b0}};
assign m_axi_wstrb = {C_M_AXI_DATA_WIDTH/8{1'b0}};
assign m_axi_wlast = 1'b0;
// assign m_axi_wuser = {C_AXI_WUSER_WIDTH{1'b0}};
assign m_axi_wvalid = 1'b0;
// Master Interface Write Response Ports
assign m_axi_bready = 1'b0;
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Handle Read Channels (AR/R)
/////////////////////////////////////////////////////////////////////////////
generate
if (C_AXI_SUPPORTS_READ == 1) begin : USE_READ
// Read Channel Signals for Commands Queue Interface.
wire rd_cmd_valid;
wire rd_cmd_split;
wire rd_cmd_mirror;
wire rd_cmd_fix;
wire [C_S_AXI_BYTES_LOG-1:0] rd_cmd_first_word;
wire [C_S_AXI_BYTES_LOG-1:0] rd_cmd_offset;
wire [C_S_AXI_BYTES_LOG-1:0] rd_cmd_mask;
wire [C_M_AXI_BYTES_LOG:0] rd_cmd_step;
wire [3-1:0] rd_cmd_size;
wire [8-1:0] rd_cmd_length;
wire rd_cmd_ready;
wire [C_S_AXI_ID_WIDTH-1:0] rd_cmd_id;
wire [8-1:0] s_axi_arlen_i;
wire [2-1:0] s_axi_arlock_i;
assign s_axi_arlen_i = (C_AXI_PROTOCOL == P_AXI3) ? {4'b0000, s_axi_arlen[3:0]}: s_axi_arlen;
assign s_axi_arlock_i = (C_AXI_PROTOCOL == P_AXI3) ? s_axi_arlock : {1'b0, s_axi_arlock[0]};
// Write Address Channel.
axi_dwidth_converter_v2_1_9_a_downsizer #
(
.C_FAMILY (C_FAMILY),
.C_AXI_PROTOCOL (C_AXI_PROTOCOL),
.C_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_SUPPORTS_ID (C_SUPPORTS_ID),
.C_AXI_ADDR_WIDTH (P_AXI_ADDR_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_AXI_CHANNEL (1),
.C_MAX_SPLIT_BEATS (P_MAX_SPLIT_BEATS),
.C_MAX_SPLIT_BEATS_LOG (P_MAX_SPLIT_BEATS_LOG),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG),
.C_RATIO_LOG (C_RATIO_LOG)
) read_addr_inst
(
// Global Signals
.ARESET (!aresetn),
.ACLK (aclk),
// Command Interface (R)
.cmd_valid (rd_cmd_valid),
.cmd_split (rd_cmd_split),
.cmd_mirror (rd_cmd_mirror),
.cmd_fix (rd_cmd_fix),
.cmd_first_word (rd_cmd_first_word),
.cmd_offset (rd_cmd_offset),
.cmd_mask (rd_cmd_mask),
.cmd_step (rd_cmd_step),
.cmd_size (rd_cmd_size),
.cmd_length (rd_cmd_length),
.cmd_ready (rd_cmd_ready),
.cmd_id (rd_cmd_id),
// Command Interface (B)
.cmd_b_valid (),
.cmd_b_split (),
.cmd_b_repeat (),
.cmd_b_ready (1'b0),
// Slave Interface Write Address Ports
.S_AXI_AID (s_axi_arid),
.S_AXI_AADDR (s_axi_araddr_i),
.S_AXI_ALEN (s_axi_arlen_i),
.S_AXI_ASIZE (s_axi_arsize),
.S_AXI_ABURST (s_axi_arburst),
.S_AXI_ALOCK (s_axi_arlock_i),
.S_AXI_ACACHE (s_axi_arcache),
.S_AXI_APROT (s_axi_arprot),
.S_AXI_AREGION (s_axi_arregion),
.S_AXI_AQOS (s_axi_arqos),
.S_AXI_AVALID (s_axi_arvalid),
.S_AXI_AREADY (s_axi_arready),
// Master Interface Write Address Port
.M_AXI_AADDR (m_axi_araddr_i),
.M_AXI_ALEN (m_axi_arlen),
.M_AXI_ASIZE (m_axi_arsize),
.M_AXI_ABURST (m_axi_arburst),
.M_AXI_ALOCK (m_axi_arlock),
.M_AXI_ACACHE (m_axi_arcache),
.M_AXI_APROT (m_axi_arprot),
.M_AXI_AREGION (m_axi_arregion),
.M_AXI_AQOS (m_axi_arqos),
.M_AXI_AVALID (m_axi_arvalid),
.M_AXI_AREADY (m_axi_arready)
);
// Read Data channel.
axi_dwidth_converter_v2_1_9_r_downsizer #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG),
.C_RATIO_LOG (C_RATIO_LOG)
) read_data_inst
(
// Global Signals
.ARESET (!aresetn),
.ACLK (aclk),
// Command Interface
.cmd_valid (rd_cmd_valid),
.cmd_split (rd_cmd_split),
.cmd_mirror (rd_cmd_mirror),
.cmd_fix (rd_cmd_fix),
.cmd_first_word (rd_cmd_first_word),
.cmd_offset (rd_cmd_offset),
.cmd_mask (rd_cmd_mask),
.cmd_step (rd_cmd_step),
.cmd_size (rd_cmd_size),
.cmd_length (rd_cmd_length),
.cmd_ready (rd_cmd_ready),
.cmd_id (rd_cmd_id),
// Slave Interface Read Data Ports
.S_AXI_RID (s_axi_rid),
.S_AXI_RDATA (s_axi_rdata),
.S_AXI_RRESP (s_axi_rresp),
.S_AXI_RLAST (s_axi_rlast),
.S_AXI_RVALID (s_axi_rvalid),
.S_AXI_RREADY (s_axi_rready),
// Master Interface Read Data Ports
.M_AXI_RDATA (m_axi_rdata),
.M_AXI_RRESP (m_axi_rresp),
.M_AXI_RLAST (m_axi_rlast),
.M_AXI_RVALID (m_axi_rvalid),
.M_AXI_RREADY (m_axi_rready)
);
end else begin : NO_READ
// Slave Interface Read Address Ports
assign s_axi_arready = 1'b0;
// Slave Interface Read Data Ports
assign s_axi_rid = {C_S_AXI_ID_WIDTH{1'b0}};
assign s_axi_rdata = {C_S_AXI_DATA_WIDTH{1'b0}};
assign s_axi_rresp = 2'b0;
assign s_axi_rlast = 1'b0;
// assign s_axi_ruser = {C_AXI_RUSER_WIDTH{1'b0}};
assign s_axi_rvalid = 1'b0;
// Master Interface Read Address Port
assign m_axi_araddr_i = {P_AXI_ADDR_WIDTH{1'b0}};
assign m_axi_arlen = 8'b0;
assign m_axi_arsize = 3'b0;
assign m_axi_arburst = 2'b0;
assign m_axi_arlock = 2'b0;
assign m_axi_arcache = 4'b0;
assign m_axi_arprot = 3'b0;
assign m_axi_arregion = 4'b0;
assign m_axi_arqos = 4'b0;
assign m_axi_arvalid = 1'b0;
// Master Interface Read Data Ports
assign m_axi_rready = 1'b0;
end
endgenerate
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 20 02:48:27 2016
/////////////////////////////////////////////////////////////
module LOAGDA_St_N16_M4_P8 ( in1, in2, res );
input [15:0] in1;
input [15:0] in2;
output [16:0] res;
wire intadd_17_CI, intadd_17_n4, intadd_17_n3, intadd_17_n2, n37, n38, n39,
n40, n41, n42, n43, n44, n45, n46, n47, n48, n49, n50, n51, n52, n53,
n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65;
CMPR32X2TS intadd_17_U4 ( .A(in1[13]), .B(in2[13]), .C(intadd_17_n4), .CO(
intadd_17_n3), .S(res[13]) );
CMPR32X2TS intadd_17_U3 ( .A(in1[14]), .B(in2[14]), .C(intadd_17_n3), .CO(
intadd_17_n2), .S(res[14]) );
CMPR32X2TS intadd_17_U2 ( .A(in1[15]), .B(in2[15]), .C(intadd_17_n2), .CO(
res[16]), .S(res[15]) );
NOR2X1TS U47 ( .A(in1[5]), .B(in2[5]), .Y(n54) );
NAND2X1TS U48 ( .A(in2[10]), .B(in1[10]), .Y(n44) );
OAI2BB1X2TS U49 ( .A0N(in1[5]), .A1N(in2[5]), .B0(n40), .Y(n41) );
NOR2X2TS U50 ( .A(n56), .B(n55), .Y(n58) );
OAI2BB2X1TS U51 ( .B0(n38), .B1(n37), .A0N(in2[2]), .A1N(in1[2]), .Y(n39) );
NOR2X1TS U52 ( .A(in1[9]), .B(in2[9]), .Y(n45) );
OR2X1TS U53 ( .A(in1[0]), .B(in2[0]), .Y(res[0]) );
OR2X2TS U54 ( .A(in1[3]), .B(in2[3]), .Y(res[3]) );
OR2X2TS U55 ( .A(in2[4]), .B(in1[4]), .Y(n51) );
OAI22X2TS U56 ( .A0(n64), .A1(n60), .B0(in2[10]), .B1(in1[10]), .Y(n61) );
NOR2X4TS U57 ( .A(n54), .B(n53), .Y(n52) );
OAI21X2TS U58 ( .A0(in2[8]), .A1(in1[8]), .B0(n57), .Y(n46) );
OR2X2TS U59 ( .A(in2[2]), .B(in1[2]), .Y(res[2]) );
ADDFHX2TS U60 ( .A(in2[8]), .B(in1[8]), .CI(n59), .CO(n65), .S(res[8]) );
OAI2BB1X4TS U61 ( .A0N(in2[11]), .A1N(in1[11]), .B0(n49), .Y(intadd_17_CI)
);
OAI22X4TS U62 ( .A0(in1[11]), .A1(in2[11]), .B0(n60), .B1(n48), .Y(n49) );
OAI21X4TS U63 ( .A0(in2[4]), .A1(in1[4]), .B0(n50), .Y(n53) );
AO22X4TS U64 ( .A0(in1[3]), .A1(in2[3]), .B0(res[3]), .B1(n39), .Y(n50) );
OAI2BB2X4TS U65 ( .B0(n56), .B1(n43), .A0N(in1[7]), .A1N(in2[7]), .Y(n57) );
AOI22X4TS U66 ( .A0(in1[6]), .A1(in2[6]), .B0(n42), .B1(n41), .Y(n43) );
OR2X2TS U67 ( .A(in1[1]), .B(in2[1]), .Y(res[1]) );
AOI22X1TS U68 ( .A0(in1[1]), .A1(in2[1]), .B0(in1[0]), .B1(in2[0]), .Y(n38)
);
NAND2X1TS U69 ( .A(res[1]), .B(res[2]), .Y(n37) );
OR2X2TS U70 ( .A(in1[6]), .B(in2[6]), .Y(n42) );
NAND2X2TS U71 ( .A(n52), .B(n42), .Y(n55) );
OA21XLTS U72 ( .A0(n52), .A1(n42), .B0(n55), .Y(res[6]) );
INVX2TS U73 ( .A(n44), .Y(n60) );
AOI22X1TS U74 ( .A0(in2[8]), .A1(in1[8]), .B0(in1[9]), .B1(in2[9]), .Y(n47)
);
NOR2X2TS U75 ( .A(in1[7]), .B(in2[7]), .Y(n56) );
OAI211X1TS U76 ( .A0(in2[5]), .A1(in1[5]), .B0(in1[4]), .C0(in2[4]), .Y(n40)
);
OAI21X1TS U77 ( .A0(in2[10]), .A1(in1[10]), .B0(n44), .Y(n63) );
AOI211X1TS U78 ( .A0(n47), .A1(n46), .B0(n45), .C0(n63), .Y(n48) );
OA21XLTS U79 ( .A0(n51), .A1(n50), .B0(n53), .Y(res[4]) );
AOI21X1TS U80 ( .A0(n54), .A1(n53), .B0(n52), .Y(res[5]) );
AOI21X1TS U81 ( .A0(n56), .A1(n55), .B0(n58), .Y(res[7]) );
OR2X2TS U82 ( .A(n58), .B(n57), .Y(n59) );
XOR2X1TS U83 ( .A(in2[11]), .B(in1[11]), .Y(n62) );
XNOR2X1TS U84 ( .A(n62), .B(n61), .Y(res[11]) );
XNOR2X1TS U85 ( .A(n64), .B(n63), .Y(res[10]) );
CMPR32X2TS U86 ( .A(in1[9]), .B(in2[9]), .C(n65), .CO(n64), .S(res[9]) );
CMPR32X2TS U87 ( .A(in1[12]), .B(in2[12]), .C(intadd_17_CI), .CO(
intadd_17_n4), .S(res[12]) );
initial $sdf_annotate("LOAGDA_St_N16_M4_P8_syn.sdf");
endmodule
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* IPv4 and ARP block, ethernet frame interface
*/
module ip_complete #(
parameter ARP_CACHE_ADDR_WIDTH = 9,
parameter ARP_REQUEST_RETRY_COUNT = 4,
parameter ARP_REQUEST_RETRY_INTERVAL = 125000000*2,
parameter ARP_REQUEST_TIMEOUT = 125000000*30
)
(
input wire clk,
input wire rst,
/*
* Ethernet frame input
*/
input wire s_eth_hdr_valid,
output wire s_eth_hdr_ready,
input wire [47:0] s_eth_dest_mac,
input wire [47:0] s_eth_src_mac,
input wire [15:0] s_eth_type,
input wire [7:0] s_eth_payload_axis_tdata,
input wire s_eth_payload_axis_tvalid,
output wire s_eth_payload_axis_tready,
input wire s_eth_payload_axis_tlast,
input wire s_eth_payload_axis_tuser,
/*
* Ethernet frame output
*/
output wire m_eth_hdr_valid,
input wire m_eth_hdr_ready,
output wire [47:0] m_eth_dest_mac,
output wire [47:0] m_eth_src_mac,
output wire [15:0] m_eth_type,
output wire [7:0] m_eth_payload_axis_tdata,
output wire m_eth_payload_axis_tvalid,
input wire m_eth_payload_axis_tready,
output wire m_eth_payload_axis_tlast,
output wire m_eth_payload_axis_tuser,
/*
* IP input
*/
input wire s_ip_hdr_valid,
output wire s_ip_hdr_ready,
input wire [5:0] s_ip_dscp,
input wire [1:0] s_ip_ecn,
input wire [15:0] s_ip_length,
input wire [7:0] s_ip_ttl,
input wire [7:0] s_ip_protocol,
input wire [31:0] s_ip_source_ip,
input wire [31:0] s_ip_dest_ip,
input wire [7:0] s_ip_payload_axis_tdata,
input wire s_ip_payload_axis_tvalid,
output wire s_ip_payload_axis_tready,
input wire s_ip_payload_axis_tlast,
input wire s_ip_payload_axis_tuser,
/*
* IP output
*/
output wire m_ip_hdr_valid,
input wire m_ip_hdr_ready,
output wire [47:0] m_ip_eth_dest_mac,
output wire [47:0] m_ip_eth_src_mac,
output wire [15:0] m_ip_eth_type,
output wire [3:0] m_ip_version,
output wire [3:0] m_ip_ihl,
output wire [5:0] m_ip_dscp,
output wire [1:0] m_ip_ecn,
output wire [15:0] m_ip_length,
output wire [15:0] m_ip_identification,
output wire [2:0] m_ip_flags,
output wire [12:0] m_ip_fragment_offset,
output wire [7:0] m_ip_ttl,
output wire [7:0] m_ip_protocol,
output wire [15:0] m_ip_header_checksum,
output wire [31:0] m_ip_source_ip,
output wire [31:0] m_ip_dest_ip,
output wire [7:0] m_ip_payload_axis_tdata,
output wire m_ip_payload_axis_tvalid,
input wire m_ip_payload_axis_tready,
output wire m_ip_payload_axis_tlast,
output wire m_ip_payload_axis_tuser,
/*
* Status
*/
output wire rx_busy,
output wire tx_busy,
output wire rx_error_header_early_termination,
output wire rx_error_payload_early_termination,
output wire rx_error_invalid_header,
output wire rx_error_invalid_checksum,
output wire tx_error_payload_early_termination,
output wire tx_error_arp_failed,
/*
* Configuration
*/
input wire [47:0] local_mac,
input wire [31:0] local_ip,
input wire [31:0] gateway_ip,
input wire [31:0] subnet_mask,
input wire clear_arp_cache
);
/*
This module integrates the IP and ARP modules for a complete IP stack
*/
wire arp_request_valid;
wire arp_request_ready;
wire [31:0] arp_request_ip;
wire arp_response_valid;
wire arp_response_ready;
wire arp_response_error;
wire [47:0] arp_response_mac;
wire ip_rx_eth_hdr_valid;
wire ip_rx_eth_hdr_ready;
wire [47:0] ip_rx_eth_dest_mac;
wire [47:0] ip_rx_eth_src_mac;
wire [15:0] ip_rx_eth_type;
wire [7:0] ip_rx_eth_payload_axis_tdata;
wire ip_rx_eth_payload_axis_tvalid;
wire ip_rx_eth_payload_axis_tready;
wire ip_rx_eth_payload_axis_tlast;
wire ip_rx_eth_payload_axis_tuser;
wire ip_tx_eth_hdr_valid;
wire ip_tx_eth_hdr_ready;
wire [47:0] ip_tx_eth_dest_mac;
wire [47:0] ip_tx_eth_src_mac;
wire [15:0] ip_tx_eth_type;
wire [7:0] ip_tx_eth_payload_axis_tdata;
wire ip_tx_eth_payload_axis_tvalid;
wire ip_tx_eth_payload_axis_tready;
wire ip_tx_eth_payload_axis_tlast;
wire ip_tx_eth_payload_axis_tuser;
wire arp_rx_eth_hdr_valid;
wire arp_rx_eth_hdr_ready;
wire [47:0] arp_rx_eth_dest_mac;
wire [47:0] arp_rx_eth_src_mac;
wire [15:0] arp_rx_eth_type;
wire [7:0] arp_rx_eth_payload_axis_tdata;
wire arp_rx_eth_payload_axis_tvalid;
wire arp_rx_eth_payload_axis_tready;
wire arp_rx_eth_payload_axis_tlast;
wire arp_rx_eth_payload_axis_tuser;
wire arp_tx_eth_hdr_valid;
wire arp_tx_eth_hdr_ready;
wire [47:0] arp_tx_eth_dest_mac;
wire [47:0] arp_tx_eth_src_mac;
wire [15:0] arp_tx_eth_type;
wire [7:0] arp_tx_eth_payload_axis_tdata;
wire arp_tx_eth_payload_axis_tvalid;
wire arp_tx_eth_payload_axis_tready;
wire arp_tx_eth_payload_axis_tlast;
wire arp_tx_eth_payload_axis_tuser;
/*
* Input classifier (eth_type)
*/
wire s_select_ip = (s_eth_type == 16'h0800);
wire s_select_arp = (s_eth_type == 16'h0806);
wire s_select_none = !(s_select_ip || s_select_arp);
reg s_select_ip_reg = 1'b0;
reg s_select_arp_reg = 1'b0;
reg s_select_none_reg = 1'b0;
always @(posedge clk) begin
if (rst) begin
s_select_ip_reg <= 1'b0;
s_select_arp_reg <= 1'b0;
s_select_none_reg <= 1'b0;
end else begin
if (s_eth_payload_axis_tvalid) begin
if ((!s_select_ip_reg && !s_select_arp_reg && !s_select_none_reg) ||
(s_eth_payload_axis_tvalid && s_eth_payload_axis_tready && s_eth_payload_axis_tlast)) begin
s_select_ip_reg <= s_select_ip;
s_select_arp_reg <= s_select_arp;
s_select_none_reg <= s_select_none;
end
end else begin
s_select_ip_reg <= 1'b0;
s_select_arp_reg <= 1'b0;
s_select_none_reg <= 1'b0;
end
end
end
assign ip_rx_eth_hdr_valid = s_select_ip && s_eth_hdr_valid;
assign ip_rx_eth_dest_mac = s_eth_dest_mac;
assign ip_rx_eth_src_mac = s_eth_src_mac;
assign ip_rx_eth_type = 16'h0800;
assign ip_rx_eth_payload_axis_tdata = s_eth_payload_axis_tdata;
assign ip_rx_eth_payload_axis_tvalid = s_select_ip_reg && s_eth_payload_axis_tvalid;
assign ip_rx_eth_payload_axis_tlast = s_eth_payload_axis_tlast;
assign ip_rx_eth_payload_axis_tuser = s_eth_payload_axis_tuser;
assign arp_rx_eth_hdr_valid = s_select_arp && s_eth_hdr_valid;
assign arp_rx_eth_dest_mac = s_eth_dest_mac;
assign arp_rx_eth_src_mac = s_eth_src_mac;
assign arp_rx_eth_type = 16'h0806;
assign arp_rx_eth_payload_axis_tdata = s_eth_payload_axis_tdata;
assign arp_rx_eth_payload_axis_tvalid = s_select_arp_reg && s_eth_payload_axis_tvalid;
assign arp_rx_eth_payload_axis_tlast = s_eth_payload_axis_tlast;
assign arp_rx_eth_payload_axis_tuser = s_eth_payload_axis_tuser;
assign s_eth_hdr_ready = (s_select_ip && ip_rx_eth_hdr_ready) ||
(s_select_arp && arp_rx_eth_hdr_ready) ||
(s_select_none);
assign s_eth_payload_axis_tready = (s_select_ip_reg && ip_rx_eth_payload_axis_tready) ||
(s_select_arp_reg && arp_rx_eth_payload_axis_tready) ||
s_select_none_reg;
/*
* Output arbiter
*/
eth_arb_mux #(
.S_COUNT(2),
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.ARB_TYPE_ROUND_ROBIN(0),
.ARB_LSB_HIGH_PRIORITY(1)
)
eth_arb_mux_inst (
.clk(clk),
.rst(rst),
// Ethernet frame inputs
.s_eth_hdr_valid({ip_tx_eth_hdr_valid, arp_tx_eth_hdr_valid}),
.s_eth_hdr_ready({ip_tx_eth_hdr_ready, arp_tx_eth_hdr_ready}),
.s_eth_dest_mac({ip_tx_eth_dest_mac, arp_tx_eth_dest_mac}),
.s_eth_src_mac({ip_tx_eth_src_mac, arp_tx_eth_src_mac}),
.s_eth_type({ip_tx_eth_type, arp_tx_eth_type}),
.s_eth_payload_axis_tdata({ip_tx_eth_payload_axis_tdata, arp_tx_eth_payload_axis_tdata}),
.s_eth_payload_axis_tkeep(0),
.s_eth_payload_axis_tvalid({ip_tx_eth_payload_axis_tvalid, arp_tx_eth_payload_axis_tvalid}),
.s_eth_payload_axis_tready({ip_tx_eth_payload_axis_tready, arp_tx_eth_payload_axis_tready}),
.s_eth_payload_axis_tlast({ip_tx_eth_payload_axis_tlast, arp_tx_eth_payload_axis_tlast}),
.s_eth_payload_axis_tid(0),
.s_eth_payload_axis_tdest(0),
.s_eth_payload_axis_tuser({ip_tx_eth_payload_axis_tuser, arp_tx_eth_payload_axis_tuser}),
// Ethernet frame output
.m_eth_hdr_valid(m_eth_hdr_valid),
.m_eth_hdr_ready(m_eth_hdr_ready),
.m_eth_dest_mac(m_eth_dest_mac),
.m_eth_src_mac(m_eth_src_mac),
.m_eth_type(m_eth_type),
.m_eth_payload_axis_tdata(m_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(),
.m_eth_payload_axis_tvalid(m_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(m_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(m_eth_payload_axis_tlast),
.m_eth_payload_axis_tid(),
.m_eth_payload_axis_tdest(),
.m_eth_payload_axis_tuser(m_eth_payload_axis_tuser)
);
/*
* IP module
*/
ip
ip_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(ip_rx_eth_hdr_valid),
.s_eth_hdr_ready(ip_rx_eth_hdr_ready),
.s_eth_dest_mac(ip_rx_eth_dest_mac),
.s_eth_src_mac(ip_rx_eth_src_mac),
.s_eth_type(ip_rx_eth_type),
.s_eth_payload_axis_tdata(ip_rx_eth_payload_axis_tdata),
.s_eth_payload_axis_tvalid(ip_rx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(ip_rx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(ip_rx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(ip_rx_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(ip_tx_eth_hdr_valid),
.m_eth_hdr_ready(ip_tx_eth_hdr_ready),
.m_eth_dest_mac(ip_tx_eth_dest_mac),
.m_eth_src_mac(ip_tx_eth_src_mac),
.m_eth_type(ip_tx_eth_type),
.m_eth_payload_axis_tdata(ip_tx_eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid(ip_tx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(ip_tx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(ip_tx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(ip_tx_eth_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(m_ip_hdr_valid),
.m_ip_hdr_ready(m_ip_hdr_ready),
.m_ip_eth_dest_mac(m_ip_eth_dest_mac),
.m_ip_eth_src_mac(m_ip_eth_src_mac),
.m_ip_eth_type(m_ip_eth_type),
.m_ip_version(m_ip_version),
.m_ip_ihl(m_ip_ihl),
.m_ip_dscp(m_ip_dscp),
.m_ip_ecn(m_ip_ecn),
.m_ip_length(m_ip_length),
.m_ip_identification(m_ip_identification),
.m_ip_flags(m_ip_flags),
.m_ip_fragment_offset(m_ip_fragment_offset),
.m_ip_ttl(m_ip_ttl),
.m_ip_protocol(m_ip_protocol),
.m_ip_header_checksum(m_ip_header_checksum),
.m_ip_source_ip(m_ip_source_ip),
.m_ip_dest_ip(m_ip_dest_ip),
.m_ip_payload_axis_tdata(m_ip_payload_axis_tdata),
.m_ip_payload_axis_tvalid(m_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(m_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(m_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(m_ip_payload_axis_tuser),
// IP frame input
.s_ip_hdr_valid(s_ip_hdr_valid),
.s_ip_hdr_ready(s_ip_hdr_ready),
.s_ip_dscp(s_ip_dscp),
.s_ip_ecn(s_ip_ecn),
.s_ip_length(s_ip_length),
.s_ip_ttl(s_ip_ttl),
.s_ip_protocol(s_ip_protocol),
.s_ip_source_ip(s_ip_source_ip),
.s_ip_dest_ip(s_ip_dest_ip),
.s_ip_payload_axis_tdata(s_ip_payload_axis_tdata),
.s_ip_payload_axis_tvalid(s_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(s_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(s_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(s_ip_payload_axis_tuser),
// ARP requests
.arp_request_valid(arp_request_valid),
.arp_request_ready(arp_request_ready),
.arp_request_ip(arp_request_ip),
.arp_response_valid(arp_response_valid),
.arp_response_ready(arp_response_ready),
.arp_response_error(arp_response_error),
.arp_response_mac(arp_response_mac),
// Status
.rx_busy(rx_busy),
.tx_busy(tx_busy),
.rx_error_header_early_termination(rx_error_header_early_termination),
.rx_error_payload_early_termination(rx_error_payload_early_termination),
.rx_error_invalid_header(rx_error_invalid_header),
.rx_error_invalid_checksum(rx_error_invalid_checksum),
.tx_error_payload_early_termination(tx_error_payload_early_termination),
.tx_error_arp_failed(tx_error_arp_failed),
// Configuration
.local_mac(local_mac),
.local_ip(local_ip)
);
/*
* ARP module
*/
arp #(
.CACHE_ADDR_WIDTH(ARP_CACHE_ADDR_WIDTH),
.REQUEST_RETRY_COUNT(ARP_REQUEST_RETRY_COUNT),
.REQUEST_RETRY_INTERVAL(ARP_REQUEST_RETRY_INTERVAL),
.REQUEST_TIMEOUT(ARP_REQUEST_TIMEOUT)
)
arp_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(arp_rx_eth_hdr_valid),
.s_eth_hdr_ready(arp_rx_eth_hdr_ready),
.s_eth_dest_mac(arp_rx_eth_dest_mac),
.s_eth_src_mac(arp_rx_eth_src_mac),
.s_eth_type(arp_rx_eth_type),
.s_eth_payload_axis_tdata(arp_rx_eth_payload_axis_tdata),
.s_eth_payload_axis_tvalid(arp_rx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(arp_rx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(arp_rx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(arp_rx_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(arp_tx_eth_hdr_valid),
.m_eth_hdr_ready(arp_tx_eth_hdr_ready),
.m_eth_dest_mac(arp_tx_eth_dest_mac),
.m_eth_src_mac(arp_tx_eth_src_mac),
.m_eth_type(arp_tx_eth_type),
.m_eth_payload_axis_tdata(arp_tx_eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid(arp_tx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(arp_tx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(arp_tx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(arp_tx_eth_payload_axis_tuser),
// ARP requests
.arp_request_valid(arp_request_valid),
.arp_request_ready(arp_request_ready),
.arp_request_ip(arp_request_ip),
.arp_response_valid(arp_response_valid),
.arp_response_ready(arp_response_ready),
.arp_response_error(arp_response_error),
.arp_response_mac(arp_response_mac),
// Configuration
.local_mac(local_mac),
.local_ip(local_ip),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask),
.clear_cache(clear_arp_cache)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O2111AI_TB_V
`define SKY130_FD_SC_HD__O2111AI_TB_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o2111ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg C1;
reg D1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
D1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 C1 = 1'b0;
#100 D1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 B1 = 1'b1;
#260 C1 = 1'b1;
#280 D1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 B1 = 1'b0;
#440 C1 = 1'b0;
#460 D1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 D1 = 1'b1;
#660 C1 = 1'b1;
#680 B1 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 D1 = 1'bx;
#840 C1 = 1'bx;
#860 B1 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_hd__o2111ai dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .D1(D1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O2111AI_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XNOR3_PP_SYMBOL_V
`define SKY130_FD_SC_LP__XNOR3_PP_SYMBOL_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__xnor3 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__XNOR3_PP_SYMBOL_V
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 2
(* X_CORE_INFO = "xlconcat,Vivado 2016.2" *)
(* CHECK_LICENSE_TYPE = "dma_loopback_xlconcat_0_0,xlconcat,{}" *)
(* CORE_GENERATION_INFO = "dma_loopback_xlconcat_0_0,xlconcat,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=2,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WIDTH=1,IN2\
4_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=2,NUM_PORTS=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module dma_loopback_xlconcat_0_0 (
In0,
In1,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
output wire [1 : 0] dout;
xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(2),
.NUM_PORTS(2)
) inst (
.In0(In0),
.In1(In1),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
/*
Extended Text Mode display model.
Has 4|8kB of display memory, organized as 32-bit cells.
* 15:0, Char or Pixel Bits
* 29:16, Color or Effect Bits
* 31:30, Cell Mode
** 00, Text Cell, 8x8, uses Font Memory
** 01, Graphics Cell, 4x4x1
Mode 0/1:
* 21,16: ColorA
* 27,22: ColorB
** Colors: rrggbb
** 0, 85, 170, 255
Text Cell:
* 7:0, Glyph
* 11:8, Font
* 15:12, Effect
** Strike, Underline
*/
module ModFbTxt(clock, reset,
pixPosX, pixPosY, pixCy, pixCu, pixCv,
pixCellIx, cellData,
fontGlyph, fontData);
/* verilator lint_off UNUSED */
input clock;
input reset;
input[9:0] pixPosX;
input[9:0] pixPosY;
output[7:0] pixCy;
output[7:0] pixCu;
output[7:0] pixCv;
output[13:0] pixCellIx;
input[31:0] cellData;
output[15:0] fontGlyph;
input[63:0] fontData;
reg[9:0] tPixPosX;
reg[9:0] tPixPosY;
reg[13:0] tPixCellX; //base cell X
reg[13:0] tPixCellY; //base cell Y
reg[13:0] tPixCellIx; //base cell index
reg[3:0] tPixCellFx; //base cell index
reg[13:0] tPixCellNextIx; //base cell index
reg[3:0] tPixCellNextFx; //pixel index (4x4)
reg[5:0] tPixCellNextGx; //glyph pix index (8x8)
reg[31:0] tCellData;
reg[15:0] tFontGlyph;
reg[63:0] tFontData;
reg[5:0] tClrA;
reg[5:0] tClrB;
reg[8:0] tClr9A;
reg[8:0] tClr9B;
reg[11:0] tClrRgbA;
reg[11:0] tClrRgbB;
reg[11:0] tClrYuvA;
reg[11:0] tClrYuvB;
reg[11:0] tClrYuvC;
reg[7:0] tPixCy;
reg[7:0] tPixCu;
reg[7:0] tPixCv;
reg[11:0] cbClrTab[63:0];
reg useCol80;
assign pixCellIx = tPixCellIx;
assign fontGlyph = tFontGlyph;
assign pixCy = tPixCy;
assign pixCu = tPixCu;
assign pixCv = tPixCv;
initial
begin
cbClrTab[ 0]=12'h088; cbClrTab[ 1]=12'h1A8;
cbClrTab[ 2]=12'h2D8; cbClrTab[ 3]=12'h3F8;
cbClrTab[ 4]=12'h255; cbClrTab[ 5]=12'h385;
cbClrTab[ 6]=12'h5A5; cbClrTab[ 7]=12'h6D5;
cbClrTab[ 8]=12'h522; cbClrTab[ 9]=12'h652;
cbClrTab[10]=12'h782; cbClrTab[11]=12'h9A2;
cbClrTab[12]=12'h700; cbClrTab[13]=12'h920;
cbClrTab[14]=12'hA50; cbClrTab[15]=12'hB80;
cbClrTab[16]=12'h18A; cbClrTab[17]=12'h2AA;
cbClrTab[18]=12'h3DA; cbClrTab[19]=12'h5FA;
cbClrTab[20]=12'h358; cbClrTab[21]=12'h588;
cbClrTab[22]=12'h6A8; cbClrTab[23]=12'h7D8;
cbClrTab[24]=12'h625; cbClrTab[25]=12'h755;
cbClrTab[26]=12'h985; cbClrTab[27]=12'hAA5;
cbClrTab[28]=12'h902; cbClrTab[29]=12'hA22;
cbClrTab[30]=12'hB52; cbClrTab[31]=12'hD82;
cbClrTab[32]=12'h28D; cbClrTab[33]=12'h3AD;
cbClrTab[34]=12'h5DD; cbClrTab[35]=12'h6FD;
cbClrTab[36]=12'h55A; cbClrTab[37]=12'h68A;
cbClrTab[38]=12'h7AA; cbClrTab[39]=12'h9DA;
cbClrTab[40]=12'h728; cbClrTab[41]=12'h958;
cbClrTab[42]=12'hA88; cbClrTab[43]=12'hBA8;
cbClrTab[44]=12'hA05; cbClrTab[45]=12'hB25;
cbClrTab[46]=12'hD55; cbClrTab[47]=12'hE85;
cbClrTab[48]=12'h38F; cbClrTab[49]=12'h5AF;
cbClrTab[50]=12'h6DF; cbClrTab[51]=12'h7FF;
cbClrTab[52]=12'h65D; cbClrTab[53]=12'h78D;
cbClrTab[54]=12'h9AD; cbClrTab[55]=12'hADD;
cbClrTab[56]=12'h92A; cbClrTab[57]=12'hA5A;
cbClrTab[58]=12'hB8A; cbClrTab[59]=12'hDAA;
cbClrTab[60]=12'hB08; cbClrTab[61]=12'hD28;
cbClrTab[62]=12'hE58; cbClrTab[63]=12'hF88;
end
// always @ (clock)
always @*
begin
tPixCellX = 0;
tPixCellY = 0;
// useCol80 = 1;
useCol80 = 0;
tClrYuvC = 0;
if(useCol80)
begin
tPixCellX[6:0] = tPixPosX[9:3];
tPixCellY[6:0] = tPixPosY[9:3];
// tPixCellNextIx = tPixCellY*80 + tPixCellX;
tPixCellNextIx = tPixCellY*80 + tPixCellX - 160;
tPixCellNextFx[1:0] = 2'h2 - tPixPosX[2:1];
tPixCellNextFx[3:2] = 2'h2 - tPixPosY[2:1];
tPixCellNextGx[2:0] = 3'h7 - tPixPosX[2:0];
tPixCellNextGx[5:3] = 3'h7 - tPixPosY[2:0];
end
else
begin
tPixCellX[5:0] = tPixPosX[9:4];
tPixCellY[6:0] = tPixPosY[9:3];
tPixCellNextIx = tPixCellY*40 + tPixCellX - 80;
tPixCellNextFx[1:0] = 2'h3 - tPixPosX[3:2];
tPixCellNextFx[3:2] = 2'h3 - tPixPosY[2:1];
tPixCellNextGx[2:0] = 3'h7 - tPixPosX[3:1];
tPixCellNextGx[5:3] = 3'h7 - tPixPosY[2:0];
end
tCellData = cellData;
// tCellData = 32'h003F_0041;
// tCellData = 32'h000C_0041;
// tCellData[7:0]=tPixCellNextIx[7:0];
// tCellData[17] = !tPixCellY[0];
// tCellData[19] = !tPixCellY[1];
// tCellData[21] = !tPixCellY[2];
// tCellData[23] = tPixCellY[0];
// tCellData[25] = tPixCellY[1];
// tCellData[27] = tPixCellY[2];
if(tPixCellIx >= 2000)
tCellData = 0;
if(!useCol80 && (tPixCellIx>=1000))
tCellData = 0;
tFontGlyph = tCellData[15:0];
tClrA = tCellData[21:16];
tClrB = tCellData[27:22];
tClr9A = tCellData[18:10];
tClr9B = tCellData[27:19];
tClrRgbA = 0;
tClrRgbB = 0;
case(tCellData[29:28])
2'b00: begin
tClrRgbA[11:10]=tClrA[5:4];
tClrRgbA[ 9: 8]=tClrA[5:4];
tClrRgbA[ 7: 6]=tClrA[3:2];
tClrRgbA[ 5: 4]=tClrA[3:2];
tClrRgbA[ 3: 2]=tClrA[1:0];
tClrRgbA[ 1: 0]=tClrA[1:0];
tClrRgbB[11:10]=tClrB[5:4];
tClrRgbB[ 9: 8]=tClrB[5:4];
tClrRgbB[ 7: 6]=tClrB[3:2];
tClrRgbB[ 5: 4]=tClrB[3:2];
tClrRgbB[ 3: 2]=tClrB[1:0];
tClrRgbB[ 1: 0]=tClrB[1:0];
end
2'b10: begin
tClrRgbA[11: 9]=tClr9A[8:6];
tClrRgbA[ 7: 5]=tClr9A[5:3];
tClrRgbA[ 3: 1]=tClr9A[2:0];
tClrRgbB[11: 9]=tClr9B[8:6];
tClrRgbB[ 7: 5]=tClr9B[5:3];
tClrRgbB[ 3: 1]=tClr9B[2:0];
end
default: begin end
endcase
tClrYuvA[11:8]=
{1'b0, tClrRgbA[ 7: 5]}+
{2'b0, tClrRgbA[11:10]}+
{2'b0, tClrRgbA[ 3: 2]};
tClrYuvB[11:8]=
{1'b0, tClrRgbB[ 7: 5]}+
{2'b0, tClrRgbB[11:10]}+
{2'b0, tClrRgbB[ 3: 2]};
tClrYuvA[7:4]=4'h8+(tClrRgbA[ 3: 1]-tClrRgbA[ 7: 5]);
tClrYuvB[7:4]=4'h8+(tClrRgbB[ 3: 1]-tClrRgbB[ 7: 5]);
tClrYuvA[3:0]=4'h8+(tClrRgbA[11: 9]-tClrRgbA[ 7: 5]);
tClrYuvB[3:0]=4'h8+(tClrRgbB[11: 9]-tClrRgbB[ 7: 5]);
// tClrYuvA = cbClrTab[tClrA];
// tClrYuvB = cbClrTab[tClrB];
tFontData = fontData;
// tFontData = 64'h0010_3844_7C44_4400;
// tClrYuvA = 12'hF88;
if(cellData[31:30]==2'b00)
tClrYuvC = (tFontData[tPixCellNextGx]) ? tClrYuvA : tClrYuvB;
else if(cellData[31:30]==2'b01)
tClrYuvC = (tFontGlyph[tPixCellNextFx]) ? tClrYuvA : tClrYuvB;
tPixCy[7:4] = tClrYuvC[11:8]; tPixCy[3:0] = tClrYuvC[11:8];
tPixCu[7:4] = tClrYuvC[7:4]; tPixCu[3:0] = tClrYuvC[7:4];
tPixCv[7:4] = tClrYuvC[3:0]; tPixCv[3:0] = tClrYuvC[3:0];
// tPixCy=128;
// tPixCu=255;
// tPixCv=255;
end
always @ (posedge clock)
begin
tPixPosX <= pixPosX;
tPixPosY <= pixPosY;
tPixCellIx <= tPixCellNextIx;
tPixCellFx <= tPixCellNextFx;
end
endmodule
|
//--------------------------------------------------------------------------------
//-- Filename: BAR1_WR_ARBITER.v
//--
//-- Description: BAR1 Write Arbiter Module
//--
//-- The module designed to arbitrate different write port to BAR1.
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module BAR1_WR_ARBITER (
rst_n,
init_rst_i,
//write port 0
wr_en0_i,
addr0_i,
wr_be0_i,
wr_d0_i,
//write port 1
wr_en1_i,
addr1_i,
wr_be1_i,
wr_d1_i,
//write port 2
wr_en2_i,
addr2_i,
wr_be2_i,
wr_d2_i,
//write port 3
wr_en3_i,
addr3_i,
wr_be3_i,
wr_d3_i,
//read port 0
rd_be0_i,
rd_d0_o,
//write port arbitration output
wr_en_o,
addr_o,
wr_be_o,
wr_d_o,
//write port feedback signals
ack0_n_o,
ack1_n_o,
ack2_n_o,
ack3_n_o,
rd_be_o,
rd_d_i,
busy_o
);
input rst_n;
input init_rst_i;
input wr_en0_i;
input [6:0] addr0_i;
input [3:0] wr_be0_i;
input [31:0] wr_d0_i;
input wr_en1_i;
input [6:0] addr1_i;
input [3:0] wr_be1_i;
input [31:0] wr_d1_i;
input wr_en2_i;
input [6:0] addr2_i;
input [3:0] wr_be2_i;
input [31:0] wr_d2_i;
input wr_en3_i;
input [6:0] addr3_i;
input [3:0] wr_be3_i;
input [31:0] wr_d3_i;
input [3:0] rd_be0_i;
output [31:0] rd_d0_o;
output wr_en_o;
output [6:0] addr_o;
output [3:0] wr_be_o;
output [31:0] wr_d_o;
output ack0_n_o;
output ack1_n_o;
output ack2_n_o;
output ack3_n_o;
output [3:0] rd_be_o;
input [31:0] rd_d_i;
output busy_o;
reg [31:0] rd_d0_o;
reg wr_en_o;
reg [6:0] addr_o;
reg [3:0] wr_be_o;
reg [31:0] wr_d_o;
reg ack0_n_o;
reg ack1_n_o;
reg ack2_n_o;
reg ack3_n_o;
reg [3:0] rd_be_o;
assign busy_o = wr_en0_i | wr_en1_i | wr_en2_i | wr_en3_i;
//write port arbitration
always @( * ) begin
if( !rst_n | init_rst_i ) begin
wr_en_o = 1'b0;
addr_o = 7'b0;
wr_be_o = 4'b0;
wr_d_o = 32'b0;
ack0_n_o = 1'b1;
ack1_n_o = 1'b1;
ack2_n_o = 1'b1;
ack3_n_o = 1'b1;
end
else begin
//write priority: port0 > port1 > port2 > port3
if( wr_en0_i ) begin
wr_en_o = wr_en0_i;
addr_o = addr0_i;
wr_be_o = wr_be0_i;
wr_d_o = wr_d0_i;
ack0_n_o = 1'b0;
ack1_n_o = 1'b1;
ack2_n_o = 1'b1;
ack3_n_o = 1'b1;
end
else if( wr_en1_i ) begin
wr_en_o = wr_en1_i;
addr_o = addr1_i;
wr_be_o = wr_be1_i;
wr_d_o = wr_d1_i;
ack0_n_o = 1'b1;
ack1_n_o = 1'b0;
ack2_n_o = 1'b1;
ack3_n_o = 1'b1;
end
else if ( wr_en2_i ) begin
wr_en_o = wr_en2_i;
addr_o = addr2_i;
wr_be_o = wr_be2_i;
wr_d_o = wr_d2_i;
ack0_n_o = 1'b1;
ack1_n_o = 1'b1;
ack2_n_o = 1'b0;
ack3_n_o = 1'b1;
end
else if ( wr_en3_i ) begin
wr_en_o = wr_en3_i;
addr_o = addr3_i;
wr_be_o = wr_be3_i;
wr_d_o = wr_d3_i;
ack0_n_o = 1'b1;
ack1_n_o = 1'b1;
ack2_n_o = 1'b1;
ack3_n_o = 1'b0;
end
else begin
wr_en_o = 1'b0;
addr_o = 7'b0;
wr_be_o = 4'b0;
wr_d_o = 32'b0;
ack0_n_o = 1'b1;
ack1_n_o = 1'b1;
ack2_n_o = 1'b1;
ack3_n_o = 1'b1;
end //if( wr_en0_i )
end //if( !rst_n | !en )
end
//read port control
always @( * ) begin
if( !rst_n | init_rst_i ) begin
rd_be_o = 4'b0;
rd_d0_o = 32'b0;
end else begin
if( !wr_en1_i & !wr_en2_i & !wr_en3_i ) begin
rd_be_o = rd_be0_i;
rd_d0_o = rd_d_i;
end
else begin
rd_be_o = 4'b0;
rd_d0_o = 32'b0;
end //if( wr_en1_i & wr_en2_i & wr_en3_i )
end //if( !rst_n | !en )
end
endmodule |
/******************************************************************************/
/* Test Bench for FPGA Sort on VC707 Ryohei Kobayashi */
/* 2016-08-01 */
/******************************************************************************/
`default_nettype none
`include "define.vh"
`include "user_logic.v"
`include "sorter.v"
/******************************************************************************/
module tb_USER_LOGIC();
reg CLK, RST;
wire chnl_rx_clk;
wire chnl_rx;
wire chnl_rx_ack;
wire chnl_rx_last;
wire [31:0] chnl_rx_len;
wire [30:0] chnl_rx_off;
wire [128-1:0] chnl_rx_data;
wire chnl_rx_data_valid;
wire chnl_rx_data_ren;
wire chnl_tx_clk;
wire chnl_tx;
wire chnl_tx_ack;
wire chnl_tx_last;
wire [31:0] chnl_tx_len;
wire [30:0] chnl_tx_off;
wire [128-1:0] chnl_tx_data;
wire chnl_tx_data_vaild;
wire chnl_tx_data_ren = 1;
wire d_busy;
wire d_w;
wire [`DRAMW-1:0] d_din;
wire [`DRAMW-1:0] d_dout;
wire d_douten;
wire [1:0] d_req; // DRAM access request (read/write)
wire [31:0] d_initadr; // dram initial address for the access
wire [31:0] d_blocks; // the number of blocks per one access(read/write)
reg sortdone;
initial begin CLK=0; forever #50 CLK=~CLK; end
initial begin RST=1; #400 RST=0; end
reg [31:0] cnt;
always @(posedge CLK) cnt <= (RST) ? 0 : cnt + 1;
reg [31:0] cnt0, cnt1, cnt2, cnt3, cnt4, cnt5, cnt6, cnt7, cnt8, cnt9;
always @(posedge CLK) cnt0 <= (RST) ? 0 : (u.core.phase==0) ? cnt0 + 1 : cnt0;
always @(posedge CLK) cnt1 <= (RST) ? 0 : (u.core.phase==1) ? cnt1 + 1 : cnt1;
always @(posedge CLK) cnt2 <= (RST) ? 0 : (u.core.phase==2) ? cnt2 + 1 : cnt2;
always @(posedge CLK) cnt3 <= (RST) ? 0 : (u.core.phase==3) ? cnt3 + 1 : cnt3;
always @(posedge CLK) cnt4 <= (RST) ? 0 : (u.core.phase==4) ? cnt4 + 1 : cnt4;
always @(posedge CLK) cnt5 <= (RST) ? 0 : (u.core.phase==5) ? cnt5 + 1 : cnt5;
always @(posedge CLK) cnt6 <= (RST) ? 0 : (u.core.phase==6) ? cnt6 + 1 : cnt6;
always @(posedge CLK) cnt7 <= (RST) ? 0 : (u.core.phase==7) ? cnt7 + 1 : cnt7;
always @(posedge CLK) cnt8 <= (RST) ? 0 : (u.core.phase==8) ? cnt8 + 1 : cnt8;
always @(posedge CLK) cnt9 <= (RST) ? 0 : (u.core.phase==9) ? cnt9 + 1 : cnt9;
reg [31:0] rslt_cnt;
always @(posedge CLK) begin
if (RST) begin
rslt_cnt <= 0;
end else begin
if (chnl_tx_data_vaild) rslt_cnt <= rslt_cnt + 4;
end
end
always @(posedge CLK) begin
if (RST) sortdone <= 0;
else if (rslt_cnt == `SORT_ELM) sortdone <= 1;
end
// Debug Info
always @(posedge CLK) begin
if (!RST) begin
$write("%d|%d|P%d|%d%d%d|%d", cnt[19:0], u.core.elem, u.core.phase[2:0], u.core.iter_done, u.core.pchange, u.core.irst, u.core.ecnt);
$write("|");
if (d_douten) $write("%08x %08x ", d_dout[63:32], d_dout[31:0]); else $write(" ");
// $write("%d %d %x ", u.rState, u.rx_wait, u.core.req_pzero);
// if (u.idata_valid) $write("%08x %08x ", u.idata[63:32], u.idata[31:0]); else $write(" ");
// $write("|");
// if (u.core.doen_t) $write("%08x %08x ", u.core.dout_t[63:32], u.core.dout_t[31:0]); else $write(" ");
// $write("|");
// if (u.core.doen_tc) $write("%08x %08x ", u.core.dout_tc[63:32], u.core.dout_tc[31:0]); else $write(" ");
$write("|");
$write("[%d](%d)", u.core.req, u.core.state);
///////////////// can be parameterized
$write("| %d %d %d %d|",
u.core.im00.imf.cnt, u.core.im01.imf.cnt, u.core.im02.imf.cnt, u.core.im03.imf.cnt);
// $write("| %d %d %d %d|",
// u.core.im00.im_deq, u.core.im01.im_deq, u.core.im02.im_deq, u.core.im03.im_deq);
$write(" ");
if (u.core.F01_deq) $write("%08x %08x %08x %08x ", u.core.F01_dot[127:96], u.core.F01_dot[95:64], u.core.F01_dot[63:32], u.core.F01_dot[31:0]); else $write(" ");
// $write("| ");
// $write("%d", u.core.dcnt);
if (d.app_wdf_wren) $write(" |M%d %d ", d_din[63:32], d_din[31:0]);
$write("\n");
$fflush();
end
end
// checking the result
generate
if (`INITTYPE=="sorted" || `INITTYPE=="reverse") begin
reg [`MERGW-1:0] check_cnt;
always @(posedge CLK) begin
if (RST) begin
check_cnt[31 : 0] <= 1;
check_cnt[63 :32] <= 2;
check_cnt[95 :64] <= 3;
check_cnt[127:96] <= 4;
end else begin
if (chnl_tx_data_vaild) begin
if (check_cnt != chnl_tx_data) begin
$write("Error in sorter.v: %d %d\n", chnl_tx_data, check_cnt); // for simulation
$finish(); // for simulation
end
check_cnt[31 : 0] <= check_cnt[31 : 0] + 4;
check_cnt[63 :32] <= check_cnt[63 :32] + 4;
check_cnt[95 :64] <= check_cnt[95 :64] + 4;
check_cnt[127:96] <= check_cnt[127:96] + 4;
end
end
end
end else if (`INITTYPE=="xorshift") begin
integer fp;
initial begin fp = $fopen("log.txt", "w"); end
always @(posedge CLK) begin
if (chnl_tx_data_vaild) begin
$fwrite(fp, "%08x\n", chnl_tx_data[31:0]);
$fwrite(fp, "%08x\n", chnl_tx_data[63:32]);
$fwrite(fp, "%08x\n", chnl_tx_data[95:64]);
$fwrite(fp, "%08x\n", chnl_tx_data[127:96]);
$fflush();
end
if (sortdone) $fclose(fp);
end
end else begin
always @(posedge CLK) begin
$write("Error! INITTYPE is wrong.\n");
$write("Please make sure src/define.vh\n");
$finish();
end
end
endgenerate
// Show the elapsed cycles
always @(posedge CLK) begin
if(sortdone) begin : simulation_finish
$write("\nIt takes %d cycles\n", cnt);
$write("phase0: %d cycles\n", cnt0);
$write("phase1: %d cycles\n", cnt1);
$write("phase2: %d cycles\n", cnt2);
$write("phase3: %d cycles\n", cnt3);
$write("phase4: %d cycles\n", cnt4);
$write("phase5: %d cycles\n", cnt5);
$write("phase6: %d cycles\n", cnt6);
$write("phase7: %d cycles\n", cnt7);
$write("phase8: %d cycles\n", cnt8);
$write("phase9: %d cycles\n", cnt9);
$write("Sorting finished!\n");
$finish();
end
end
// Stub modules
/**********************************************************************************************/
Host_to_FPGA h2f(CLK, RST, chnl_rx_data_ren, chnl_rx, chnl_rx_data, chnl_rx_data_valid, chnl_rx_len);
DRAM d(CLK, RST, d_req, d_initadr, d_blocks, d_din, d_w, d_dout, d_douten, d_busy);
/***** Core Module Instantiation *****/
/**********************************************************************************************/
USER_LOGIC u(CLK,
RST,
chnl_rx_clk,
chnl_rx,
chnl_rx_ack,
chnl_rx_last,
chnl_rx_len,
chnl_rx_off,
chnl_rx_data,
chnl_rx_data_valid,
chnl_rx_data_ren,
chnl_tx_clk,
chnl_tx,
chnl_tx_ack,
chnl_tx_last,
chnl_tx_len,
chnl_tx_off,
chnl_tx_data,
chnl_tx_data_vaild,
chnl_tx_data_ren,
d_busy, // DRAM busy
d_din, // DRAM data in
d_w, // DRAM write flag
d_dout, // DRAM data out
d_douten, // DRAM data out enable
d_req, // DRAM REQ access request (read/write)
d_initadr, // DRAM REQ initial address for the access
d_blocks // DRAM REQ the number of blocks per one access
);
endmodule
/**************************************************************************************************/
/***** Xorshift *****/
/**************************************************************************************************/
module XORSHIFT #(parameter WIDTH = 32,
parameter SEED = 1)
(input wire CLK,
input wire RST,
input wire EN,
output wire [WIDTH-1:0] RAND_VAL);
reg [WIDTH-1:0] x;
reg [WIDTH-1:0] y;
reg [WIDTH-1:0] z;
reg [WIDTH-1:0] w;
wire [WIDTH-1:0] t = x^(x<<11);
// Mask MSB for not generating the maximum value
assign RAND_VAL = {1'b0, w[WIDTH-2:0]};
reg ocen;
always @(posedge CLK) ocen <= RST;
always @(posedge CLK) begin
if (RST) begin
x <= 123456789;
y <= 362436069;
z <= 521288629;
w <= 88675123 ^ SEED;
end else begin
if (EN || ocen) begin
x <= y;
y <= z;
z <= w;
w <= (w^(w>>19))^(t^(t>>8));
end
end
end
endmodule
/**************************************************************************************************/
module Host_to_FPGA(input wire CLK,
input wire RST,
input wire ren,
output reg chnl_rx,
output wire [`MERGW-1:0] dot,
output wire doten,
output wire [31:0] length);
reg rst_buf; always @(posedge CLK) rst_buf <= RST;
wire enq;
wire deq;
wire [`MERGW-1:0] din;
wire emp;
wire ful;
wire [4:0] cnt;
reg [`SORTW-1:0] i_d,i_c,i_b,i_a;
reg onetime;
reg [31:0] enqcnt;
reg enqstop;
wire [`SORTW-1:0] r15,r14,r13,r12,r11,r10,r09,r08,r07,r06,r05,r04,r03,r02,r01,r00;
reg [1:0] selector;
wire [`MERGW-1:0] din_xorshift = (selector == 0) ? {r03,r02,r01,r00} :
(selector == 1) ? {r07,r06,r05,r04} :
(selector == 2) ? {r11,r10,r09,r08} :
(selector == 3) ? {r15,r14,r13,r12} : 0;
SRL_FIFO #(4, `MERGW) fifo(CLK, rst_buf, enq, deq, din, dot, emp, ful, cnt);
assign enq = (!enqstop && !ful);
assign deq = (ren && !emp);
assign din = (`INITTYPE=="xorshift") ? din_xorshift : {i_d,i_c,i_b,i_a};
assign doten = deq;
assign length = `SORT_ELM;
always @(posedge CLK) begin
if (rst_buf) begin
chnl_rx <= 0;
onetime <= 1;
end else begin
chnl_rx <= onetime;
onetime <= 0;
end
end
always @(posedge CLK) begin
if (rst_buf) enqcnt <= 0;
else if (enq) enqcnt <= enqcnt + 4;
end
always @(posedge CLK) begin
if (rst_buf) enqstop <= 0;
else if (enq && (enqcnt == `SORT_ELM-4)) enqstop <= 1;
end
always @(posedge CLK) begin
if (rst_buf) selector <= 0;
else if (enq) selector <= selector + 1;
end
generate
if (`INITTYPE=="sorted") begin
always @(posedge CLK) begin
if (rst_buf) begin
i_a <= 1;
i_b <= 2;
i_c <= 3;
i_d <= 4;
end else begin
if (enq) begin
i_a <= i_a+4;
i_b <= i_b+4;
i_c <= i_c+4;
i_d <= i_d+4;
end
end
end
end else if (`INITTYPE=="reverse") begin
always @(posedge CLK) begin
if (rst_buf) begin
i_a <= `SORT_ELM;
i_b <= `SORT_ELM-1;
i_c <= `SORT_ELM-2;
i_d <= `SORT_ELM-3;
end else begin
if (enq) begin
i_a <= i_a-4;
i_b <= i_b-4;
i_c <= i_c-4;
i_d <= i_d-4;
end
end
end
end else if (`INITTYPE=="xorshift") begin
XORSHIFT #(`SORTW, 32'h00000001) xorshift00(CLK, RST, (enq && selector == 0), r00);
XORSHIFT #(`SORTW, 32'h00000002) xorshift01(CLK, RST, (enq && selector == 0), r01);
XORSHIFT #(`SORTW, 32'h00000004) xorshift02(CLK, RST, (enq && selector == 0), r02);
XORSHIFT #(`SORTW, 32'h00000008) xorshift03(CLK, RST, (enq && selector == 0), r03);
XORSHIFT #(`SORTW, 32'h00000010) xorshift04(CLK, RST, (enq && selector == 1), r04);
XORSHIFT #(`SORTW, 32'h00000020) xorshift05(CLK, RST, (enq && selector == 1), r05);
XORSHIFT #(`SORTW, 32'h00000040) xorshift06(CLK, RST, (enq && selector == 1), r06);
XORSHIFT #(`SORTW, 32'h00000080) xorshift07(CLK, RST, (enq && selector == 1), r07);
XORSHIFT #(`SORTW, 32'h00000100) xorshift08(CLK, RST, (enq && selector == 2), r08);
XORSHIFT #(`SORTW, 32'h00000200) xorshift09(CLK, RST, (enq && selector == 2), r09);
XORSHIFT #(`SORTW, 32'h00000400) xorshift10(CLK, RST, (enq && selector == 2), r10);
XORSHIFT #(`SORTW, 32'h00000800) xorshift11(CLK, RST, (enq && selector == 2), r11);
XORSHIFT #(`SORTW, 32'h00001000) xorshift12(CLK, RST, (enq && selector == 3), r12);
XORSHIFT #(`SORTW, 32'h00002000) xorshift13(CLK, RST, (enq && selector == 3), r13);
XORSHIFT #(`SORTW, 32'h00004000) xorshift14(CLK, RST, (enq && selector == 3), r14);
XORSHIFT #(`SORTW, 32'h00008000) xorshift15(CLK, RST, (enq && selector == 3), r15);
end
endgenerate
endmodule
/**************************************************************************************************/
module DRAM(input wire CLK, //
input wire RST, //
input wire [1:0] D_REQ, // dram request, load or store
input wire [31:0] D_INITADR, // dram request, initial address
input wire [31:0] D_ELEM, // dram request, the number of elements
input wire [`DRAMW-1:0] D_DIN, //
output wire D_W, //
output reg [`DRAMW-1:0] D_DOUT, //
output reg D_DOUTEN, //
output wire D_BUSY); //
/******* DRAM ******************************************************/
localparam M_REQ = 0;
localparam M_WRITE = 1;
localparam M_READ = 2;
///////////////////////////////////////////////////////////////////////////////////
reg [`DDR3_CMD] app_cmd;
reg app_en;
wire [`DRAMW-1:0] app_wdf_data;
reg app_wdf_wren;
wire app_wdf_end = app_wdf_wren;
// outputs of u_dram
wire [`DRAMW-1:0] app_rd_data;
wire app_rd_data_end;
wire app_rd_data_valid=1; // in simulation, always ready !!
wire app_rdy = 1; // in simulation, always ready !!
wire app_wdf_rdy = 1; // in simulation, always ready !!
wire ui_clk = CLK;
reg [1:0] mode;
reg [`DRAMW-1:0] app_wdf_data_buf;
reg [31:0] caddr; // check address
reg [31:0] remain, remain2; //
reg [7:0] req_state; //
///////////////////////////////////////////////////////////////////////////////////
reg [`DRAMW-1:0] mem [`DRAM_SIZE-1:0];
reg [31:0] app_addr;
reg [31:0] dram_addr;
always @(posedge CLK) dram_addr <= app_addr;
always @(posedge CLK) begin /***** DRAM WRITE *****/
if (RST) begin end
else if(app_wdf_wren) mem[dram_addr[27:3]] <= app_wdf_data;
end
assign app_rd_data = mem[app_addr[27:3]];
assign app_wdf_data = D_DIN;
assign D_BUSY = (mode!=M_REQ); // DRAM busy
assign D_W = (mode==M_WRITE && app_rdy && app_wdf_rdy); // store one element
///// READ & WRITE PORT CONTROL (begin) ////////////////////////////////////////////
always @(posedge ui_clk) begin
if (RST) begin
mode <= M_REQ;
{app_addr, app_cmd, app_en, app_wdf_wren} <= 0;
{D_DOUT, D_DOUTEN} <= 0;
{caddr, remain, remain2, req_state} <= 0;
end else begin
case (mode)
///////////////////////////////////////////////////////////////// request
M_REQ: begin
D_DOUTEN <= 0;
if(D_REQ==`DRAM_REQ_WRITE) begin ///// WRITE or STORE request
app_cmd <= `DRAM_CMD_WRITE;
mode <= M_WRITE;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // the number of blocks to be written
end
else if(D_REQ==`DRAM_REQ_READ) begin ///// READ or LOAD request
app_cmd <= `DRAM_CMD_READ;
mode <= M_READ;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // param, the number of blocks to be read
remain2 <= D_ELEM; // param, the number of blocks to be read
end
else begin
app_wdf_wren <= 0;
app_en <= 0;
end
end
//////////////////////////////////////////////////////////////////// read
M_READ: begin
if (app_rdy) begin // read request is accepted.
app_addr <= (app_addr==`MEM_LAST_ADDR) ? 0 : app_addr + 8;
remain2 <= remain2 - 1;
if(remain2==1) app_en <= 0;
end
D_DOUTEN <= app_rd_data_valid; // dram data_out enable
if (app_rd_data_valid) begin
D_DOUT <= app_rd_data;
caddr <= (caddr==`MEM_LAST_ADDR) ? 0 : caddr + 8;
remain <= remain - 1;
if(remain==1) begin
mode <= M_REQ;
end
end
end
/////////////////////////////////////////////////////////////////// write
M_WRITE: begin
if (app_rdy && app_wdf_rdy) begin
app_wdf_wren <= 1;
app_addr <= (app_addr==`MEM_LAST_ADDR) ? 0 : app_addr + 8;
remain <= remain - 1;
if(remain==1) begin
mode <= M_REQ;
app_en <= 0;
end
end
else app_wdf_wren <= 0;
end
endcase
end
end
///// READ & WRITE PORT CONTROL (end) //////////////////////////////////////
endmodule
/**************************************************************************************************/
`default_nettype wire
|
// cpu interface
module cpu_if
(
input CLK,
input RESET_X,
// CPU
input [7:0] ADR,
output reg [31:0] RDATA,
input RD,
input WR,
input [31:0] WDATA,
output reg INT,
//REGISTERS
output reg SOFT_RESET,
output reg START,
input FINISH,
//input RUNNING
output reg [1:0] OP, // 0:ADD 1:MUL 2:RQT
output reg [1:0] MSEL_INPUTA_SEL,
output reg [1:0] MSEL_INPUTB_SEL,
output reg [1:0] MSEL_OUTPUTC_SEL,
output reg INV_ASEL,
output reg INV_BSEL,
output reg [31:0] M0VAL,
output reg [9:0] M1POS,
output reg [9:0] M1SIZE,
output reg [9:0] M2POS,
output reg [9:0] M2SIZE,
output reg [9:0] M3POS,
output reg [9:0] M3SIZE,
//ADD
output reg [31:0] AD_GAIN,
output reg [31:0] AD_QPARAM,
//MULL CORE
output reg [31:0] MLC_GAGB,
output reg [31:0] MLC_GAOB,
output reg [31:0] MLC_GBOA,
// MULL ADD1
output reg [31:0] ML1_GAIN,
output reg [31:0] ML1_QPARAM,
output reg [31:0] ML2_GAIN,
output reg [31:0] ML2_QPARAM,
output reg [7:0] REQ_MID,
output reg [31:0] REQ_GAIN,
input [15:0] RMAX,
input [15:0] RMIN
);
reg run_r;
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
INT <= 0;
end else begin
INT <= FINISH;
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
START <= 0;
SOFT_RESET <= 0;
end else begin
if((ADR==8'h00) && WR)begin
START <= WDATA[1];
SOFT_RESET <= WDATA[0];
end else begin
START <= 0;
SOFT_RESET <= 0;
end
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
run_r <= 0;
end else begin
if(START)begin
run_r <= 1;
end else if(FINISH)begin
run_r <= 0;
end
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
OP <= 0;
end else begin
if((ADR==8'h08) && WR)begin
OP <= WDATA[1:0];
end
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
MSEL_INPUTA_SEL <= 0;
MSEL_INPUTB_SEL <= 0;
MSEL_OUTPUTC_SEL <= 0;
end else begin
if((ADR==8'h0C) && WR)begin
MSEL_INPUTA_SEL <= WDATA[1:0];
MSEL_INPUTB_SEL <= WDATA[3:2];
MSEL_OUTPUTC_SEL <= WDATA[5:4];
end
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
INV_ASEL <= 0;
INV_BSEL <= 0;
end else begin
if((ADR==8'h10) && WR)begin
INV_ASEL <= WDATA[0];
INV_BSEL <= WDATA[1];
end
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
M0VAL <= 0;
end else begin
if((ADR==8'h14) && WR)begin
M0VAL <= 0;
end
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
M1POS <= 0;
end else begin
if((ADR==8'h20) && WR)begin
M1POS <= WDATA[9:0];
end
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
M1SIZE <= 0;
end else begin
if((ADR==8'h24) && WR)begin
M1SIZE <= WDATA[9:0];
end
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
M2POS <= 0;
end else begin
if((ADR==8'h30) && WR)begin
M2POS <= WDATA[9:0];
end
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
M2SIZE <= 0;
end else begin
if((ADR==8'h34) && WR)begin
M2SIZE <= WDATA[9:0];
end
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
M3POS <= 0;
end else begin
if((ADR==8'h40) && WR)begin
M2POS <= WDATA[9:0];
end
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
M3SIZE <= 0;
end else begin
if((ADR==8'h44) && WR)begin
M3SIZE <= WDATA[9:0];
end
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
AD_GAIN <= 0;
end else begin
if((ADR==8'h50) && WR)begin
AD_GAIN <= WDATA;
end
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
AD_QPARAM <= 0;
end else begin
if((ADR==8'h54) && WR)begin
AD_QPARAM <= WDATA;
end
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
MLC_GAGB <= 0;
end else begin
if((ADR==8'h60) && WR)begin
MLC_GAGB <= WDATA;
end
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
MLC_GAOB <= 0;
end else begin
if((ADR==8'h64) && WR)begin
MLC_GAOB <= WDATA;
end
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
MLC_GBOA <= 0;
end else begin
if((ADR==8'h68) && WR)begin
MLC_GBOA <= WDATA;
end
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
ML1_GAIN <= 0;
end else begin
if((ADR==8'h70) && WR)begin
ML1_GAIN <= WDATA;
end
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
ML1_QPARAM <= 0;
end else begin
if((ADR==8'h74) && WR)begin
ML1_QPARAM <= WDATA;
end
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
ML2_GAIN <= 0;
end else begin
if((ADR==8'h78) && WR)begin
ML2_GAIN <= WDATA;
end
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
ML2_QPARAM <= 0;
end else begin
if((ADR==8'h7C) && WR)begin
ML2_QPARAM <= WDATA;
end
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
REQ_MID <= 0;
end else begin
if((ADR==8'h80) && WR)begin
REQ_MID <= WDATA[7:0];
end
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
REQ_GAIN <= 0;
end else begin
if((ADR==8'h84) && WR)begin
REQ_GAIN <= WDATA;
end
end
end
// RDATA
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
RDATA <= 0;
end else begin
if(RD)begin
case (ADR)
8'h04:begin
RDATA[31:2] <= 30'h00000000;
RDATA[1] <= run_r;
RDATA[0] <= FINISH;
end
8'hC0: begin
RDATA[31:16] <= 24'h000000;
RDATA[15:0] <= RMAX;
end
8'hC4: begin
RDATA[31:16] <= 24'h000000;
RDATA[15:0] <= RMIN;
end
default: RDATA <= 0;
endcase // case ADR
end
end
end
endmodule // cpu_if
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 20 02:55:40 2016
/////////////////////////////////////////////////////////////
module GeAr_N9_R4_P1 ( in1, in2, res );
input [8:0] in1;
input [8:0] in2;
output [9:0] res;
wire intadd_31_CI, intadd_31_n4, intadd_31_n3, intadd_31_n2, intadd_32_CI,
intadd_32_n3, intadd_32_n2, intadd_32_n1, n2;
CMPR32X2TS intadd_31_U5 ( .A(in2[5]), .B(in1[5]), .C(intadd_31_CI), .CO(
intadd_31_n4), .S(res[5]) );
CMPR32X2TS intadd_31_U4 ( .A(in2[6]), .B(in1[6]), .C(intadd_31_n4), .CO(
intadd_31_n3), .S(res[6]) );
CMPR32X2TS intadd_31_U3 ( .A(in2[7]), .B(in1[7]), .C(intadd_31_n3), .CO(
intadd_31_n2), .S(res[7]) );
CMPR32X2TS intadd_31_U2 ( .A(in2[8]), .B(in1[8]), .C(intadd_31_n2), .CO(
res[9]), .S(res[8]) );
CMPR32X2TS intadd_32_U4 ( .A(in2[1]), .B(in1[1]), .C(intadd_32_CI), .CO(
intadd_32_n3), .S(res[1]) );
CMPR32X2TS intadd_32_U3 ( .A(in2[2]), .B(in1[2]), .C(intadd_32_n3), .CO(
intadd_32_n2), .S(res[2]) );
CMPR32X2TS intadd_32_U2 ( .A(in2[3]), .B(in1[3]), .C(intadd_32_n2), .CO(
intadd_32_n1), .S(res[3]) );
CLKAND2X2TS U2 ( .A(in1[4]), .B(in2[4]), .Y(intadd_31_CI) );
CLKAND2X2TS U3 ( .A(in2[0]), .B(in1[0]), .Y(intadd_32_CI) );
AOI2BB1XLTS U4 ( .A0N(in1[4]), .A1N(in2[4]), .B0(intadd_31_CI), .Y(n2) );
AOI2BB1XLTS U5 ( .A0N(in2[0]), .A1N(in1[0]), .B0(intadd_32_CI), .Y(res[0])
);
XOR2XLTS U6 ( .A(n2), .B(intadd_32_n1), .Y(res[4]) );
initial $sdf_annotate("GeAr_N9_R4_P1_syn.sdf");
endmodule
|
//wishbone master interconnect testbench
/*
Distributed under the MIT licesnse.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
`timescale 1 ns/1 ps
module waveform(
clk,
rst,
wavelength,
pos,
value
);
input clk;
input rst;
input [7:0] pos;
output [7:0] wavelength;
output [15:0] value;
parameter WAVELENGTH = 44;
assign wavelength = WAVELENGTH;
assign value = wave[pos];
//register
wire [15:0] wave [WAVELENGTH:0];
assign wave[0] = 16'h0000;
assign wave[1] = 16'h1237;
assign wave[2] = 16'h240F;
assign wave[3] = 16'h352C;
assign wave[4] = 16'h4533;
assign wave[5] = 16'h53D2;
assign wave[6] = 16'h60BC;
assign wave[7] = 16'h6BAE;
assign wave[8] = 16'h746E;
assign wave[9] = 16'h7AD0;
assign wave[10] = 16'h7EB2;
assign wave[11] = 16'h7FFF;
assign wave[12] = 16'h7EB2;
assign wave[13] = 16'h7AD0;
assign wave[14] = 16'h746E;
assign wave[15] = 16'h6BAE;
assign wave[16] = 16'h60BC;
assign wave[17] = 16'h53D2;
assign wave[18] = 16'h4533;
assign wave[19] = 16'h352C;
assign wave[20] = 16'h240F;
assign wave[21] = 16'h1237;
assign wave[22] = 16'h0000;
assign wave[23] = 16'hEDC9;
assign wave[24] = 16'hDBF1;
assign wave[25] = 16'hCAD4;
assign wave[26] = 16'hBACD;
assign wave[27] = 16'hAC2E;
assign wave[28] = 16'h9F43;
assign wave[29] = 16'h9452;
assign wave[30] = 16'h8B92;
assign wave[31] = 16'h8530;
assign wave[32] = 16'h814E;
assign wave[33] = 16'h8001;
assign wave[34] = 16'h814E;
assign wave[35] = 16'h8530;
assign wave[36] = 16'h8B92;
assign wave[37] = 16'h9452;
assign wave[38] = 16'h9F43;
assign wave[39] = 16'hAC2E;
assign wave[40] = 16'hBACD;
assign wave[41] = 16'hCAD4;
assign wave[42] = 16'hDBF1;
assign wave[43] = 16'hEDC9;
endmodule
|
`timescale 1 ns/100 ps
// Version: 9.0 SP1 9.0.2.9
module dmem_128B(WD,RD,WEN,REN,WADDR,RADDR,RWCLK,RESET);
input [7:0] WD;
output [7:0] RD;
input WEN, REN;
input [6:0] WADDR, RADDR;
input RWCLK;
input RESET;
wire VCC, GND;
VCC VCC_1_net(.Y(VCC));
GND GND_1_net(.Y(GND));
RAM4K9 dmem_128B_R0C0(.ADDRA11(GND), .ADDRA10(GND), .ADDRA9(
GND), .ADDRA8(GND), .ADDRA7(GND), .ADDRA6(WADDR[6]),
.ADDRA5(WADDR[5]), .ADDRA4(WADDR[4]), .ADDRA3(WADDR[3]),
.ADDRA2(WADDR[2]), .ADDRA1(WADDR[1]), .ADDRA0(WADDR[0]),
.ADDRB11(GND), .ADDRB10(GND), .ADDRB9(GND), .ADDRB8(GND),
.ADDRB7(GND), .ADDRB6(RADDR[6]), .ADDRB5(RADDR[5]),
.ADDRB4(RADDR[4]), .ADDRB3(RADDR[3]), .ADDRB2(RADDR[2]),
.ADDRB1(RADDR[1]), .ADDRB0(RADDR[0]), .DINA8(GND), .DINA7(
WD[7]), .DINA6(WD[6]), .DINA5(WD[5]), .DINA4(WD[4]),
.DINA3(WD[3]), .DINA2(WD[2]), .DINA1(WD[1]), .DINA0(WD[0])
, .DINB8(GND), .DINB7(GND), .DINB6(GND), .DINB5(GND),
.DINB4(GND), .DINB3(GND), .DINB2(GND), .DINB1(GND),
.DINB0(GND), .WIDTHA0(VCC), .WIDTHA1(VCC), .WIDTHB0(VCC),
.WIDTHB1(VCC), .PIPEA(GND), .PIPEB(GND), .WMODEA(GND),
.WMODEB(GND), .BLKA(WEN), .BLKB(REN), .WENA(GND), .WENB(
VCC), .CLKA(RWCLK), .CLKB(RWCLK), .RESET(RESET), .DOUTA8(),
.DOUTA7(), .DOUTA6(), .DOUTA5(), .DOUTA4(), .DOUTA3(),
.DOUTA2(), .DOUTA1(), .DOUTA0(), .DOUTB8(), .DOUTB7(RD[7])
, .DOUTB6(RD[6]), .DOUTB5(RD[5]), .DOUTB4(RD[4]), .DOUTB3(
RD[3]), .DOUTB2(RD[2]), .DOUTB1(RD[1]), .DOUTB0(RD[0]));
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`ifdef OVL_ASSERT_ON
wire xzcheck_enable;
`ifdef OVL_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
assign xzcheck_enable = 1'b1;
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
generate
case (property_type)
`OVL_ASSERT_2STATE,
`OVL_ASSERT: begin: assert_checks
assert_zero_one_hot_assert #(
.width(width))
assert_zero_one_hot_assert (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr),
.xzcheck_enable(xzcheck_enable));
end
`OVL_ASSUME_2STATE,
`OVL_ASSUME: begin: assume_checks
assert_zero_one_hot_assume #(
.width(width))
assert_zero_one_hot_assume (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr),
.xzcheck_enable(xzcheck_enable));
end
`OVL_IGNORE: begin: ovl_ignore
//do nothing
end
default: initial ovl_error_t(`OVL_FIRE_2STATE,"");
endcase
endgenerate
`endif
`ifdef OVL_COVER_ON
wire [width-1:0] test_expr_1 = test_expr - {{width-1{1'b0}},1'b1};
reg [width-1:0] one_hots_checked;
always @(posedge clk)
if (`OVL_RESET_SIGNAL != 1'b1)
one_hots_checked <= {width{1'b0}};
else //check for known driven and zero one hot test_expr and update one_hots_checked
one_hots_checked <= ((test_expr ^ test_expr)=={width{1'b0}}) && ((test_expr & test_expr_1) == {width{1'b0}}) ?
one_hots_checked | test_expr : one_hots_checked;
wire all_one_hots_checked;
assign all_one_hots_checked = (one_hots_checked == {width{1'b1}});
generate
if (coverage_level != `OVL_COVER_NONE)
begin: cover_checks
assert_zero_one_hot_cover #(
.width(width),
.OVL_COVER_SANITY_ON(OVL_COVER_SANITY_ON),
.OVL_COVER_CORNER_ON(OVL_COVER_CORNER_ON))
assert_zero_one_hot_cover (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr),
.all_one_hots_checked(all_one_hots_checked));
end
endgenerate
`endif
`endmodule //Required to pair up with already used "`module" in file assert_zero_one_hot.vlib
//Module to be replicated for assert checks
//This module is bound to the PSL vunits with assert checks
module assert_zero_one_hot_assert (clk, reset_n, test_expr, xzcheck_enable);
parameter width = 1;
input clk, reset_n, xzcheck_enable;
input [width-1:0] test_expr;
endmodule
//Module to be replicated for assume checks
//This module is bound to a PSL vunits with assume checks
module assert_zero_one_hot_assume (clk, reset_n, test_expr, xzcheck_enable);
parameter width = 1;
input clk, reset_n, xzcheck_enable;
input [width-1:0] test_expr;
endmodule
//Module to be replicated for cover properties
//This module is bound to a PSL vunit with cover properties
module assert_zero_one_hot_cover (clk, reset_n, test_expr, all_one_hots_checked);
parameter width = 1;
parameter OVL_COVER_SANITY_ON = 1;
parameter OVL_COVER_CORNER_ON = 1;
input clk, reset_n, all_one_hots_checked;
input [width-1:0] test_expr;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR4B_4_V
`define SKY130_FD_SC_LS__NOR4B_4_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog wrapper for nor4b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nor4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nor4b_4 (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nor4b_4 (
Y ,
A ,
B ,
C ,
D_N
);
output Y ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR4B_4_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O41A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__O41A_FUNCTIONAL_PP_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o41a (
VPWR,
VGND,
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
// Local signals
wire A4 or0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
or or0 (or0_out , A4, A3, A2, A1 );
and and0 (and0_out_X , or0_out, B1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O41A_FUNCTIONAL_PP_V |
//-----------------------------------------------------------------
// RISC-V Top
// V0.6
// Ultra-Embedded.com
// Copyright 2014-2019
//
// [email protected]
//
// License: BSD
//-----------------------------------------------------------------
//
// Copyright (c) 2014, Ultra-Embedded.com
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer
// in the documentation and/or other materials provided with the
// distribution.
// - Neither the name of the author nor the names of its contributors
// may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
// SUCH DAMAGE.
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Generated File
//-----------------------------------------------------------------
module dcache_mux
(
// Inputs
input clk_i
,input rst_i
,input [ 31:0] mem_addr_i
,input [ 31:0] mem_data_wr_i
,input mem_rd_i
,input [ 3:0] mem_wr_i
,input mem_cacheable_i
,input [ 10:0] mem_req_tag_i
,input mem_invalidate_i
,input mem_writeback_i
,input mem_flush_i
,input [ 31:0] mem_cached_data_rd_i
,input mem_cached_accept_i
,input mem_cached_ack_i
,input mem_cached_error_i
,input [ 10:0] mem_cached_resp_tag_i
,input [ 31:0] mem_uncached_data_rd_i
,input mem_uncached_accept_i
,input mem_uncached_ack_i
,input mem_uncached_error_i
,input [ 10:0] mem_uncached_resp_tag_i
// Outputs
,output [ 31:0] mem_data_rd_o
,output mem_accept_o
,output mem_ack_o
,output mem_error_o
,output [ 10:0] mem_resp_tag_o
,output [ 31:0] mem_cached_addr_o
,output [ 31:0] mem_cached_data_wr_o
,output mem_cached_rd_o
,output [ 3:0] mem_cached_wr_o
,output mem_cached_cacheable_o
,output [ 10:0] mem_cached_req_tag_o
,output mem_cached_invalidate_o
,output mem_cached_writeback_o
,output mem_cached_flush_o
,output [ 31:0] mem_uncached_addr_o
,output [ 31:0] mem_uncached_data_wr_o
,output mem_uncached_rd_o
,output [ 3:0] mem_uncached_wr_o
,output mem_uncached_cacheable_o
,output [ 10:0] mem_uncached_req_tag_o
,output mem_uncached_invalidate_o
,output mem_uncached_writeback_o
,output mem_uncached_flush_o
,output cache_active_o
);
wire hold_w;
reg cache_access_q;
assign mem_cached_addr_o = mem_addr_i;
assign mem_cached_data_wr_o = mem_data_wr_i;
assign mem_cached_rd_o = (mem_cacheable_i & ~hold_w) ? mem_rd_i : 1'b0;
assign mem_cached_wr_o = (mem_cacheable_i & ~hold_w) ? mem_wr_i : 4'b0;
assign mem_cached_cacheable_o = mem_cacheable_i;
assign mem_cached_req_tag_o = mem_req_tag_i;
assign mem_cached_invalidate_o = (mem_cacheable_i & ~hold_w) ? mem_invalidate_i : 1'b0;
assign mem_cached_writeback_o = (mem_cacheable_i & ~hold_w) ? mem_writeback_i : 1'b0;
assign mem_cached_flush_o = (mem_cacheable_i & ~hold_w) ? mem_flush_i : 1'b0;
assign mem_uncached_addr_o = mem_addr_i;
assign mem_uncached_data_wr_o = mem_data_wr_i;
assign mem_uncached_rd_o = (~mem_cacheable_i & ~hold_w) ? mem_rd_i : 1'b0;
assign mem_uncached_wr_o = (~mem_cacheable_i & ~hold_w) ? mem_wr_i : 4'b0;
assign mem_uncached_cacheable_o = mem_cacheable_i;
assign mem_uncached_req_tag_o = mem_req_tag_i;
assign mem_uncached_invalidate_o = (~mem_cacheable_i & ~hold_w) ? mem_invalidate_i : 1'b0;
assign mem_uncached_writeback_o = (~mem_cacheable_i & ~hold_w) ? mem_writeback_i : 1'b0;
assign mem_uncached_flush_o = (~mem_cacheable_i & ~hold_w) ? mem_flush_i : 1'b0;
assign mem_accept_o =(mem_cacheable_i ? mem_cached_accept_i : mem_uncached_accept_i) & !hold_w;
assign mem_data_rd_o = cache_access_q ? mem_cached_data_rd_i : mem_uncached_data_rd_i;
assign mem_ack_o = cache_access_q ? mem_cached_ack_i : mem_uncached_ack_i;
assign mem_error_o = cache_access_q ? mem_cached_error_i : mem_uncached_error_i;
assign mem_resp_tag_o = cache_access_q ? mem_cached_resp_tag_i : mem_uncached_resp_tag_i;
wire request_w = mem_rd_i | mem_wr_i != 4'b0 | mem_flush_i | mem_invalidate_i | mem_writeback_i;
reg [4:0] pending_r;
reg [4:0] pending_q;
always @ *
begin
pending_r = pending_q;
if ((request_w && mem_accept_o) && !mem_ack_o)
pending_r = pending_r + 5'd1;
else if (!(request_w && mem_accept_o) && mem_ack_o)
pending_r = pending_r - 5'd1;
end
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
pending_q <= 5'b0;
else
pending_q <= pending_r;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
cache_access_q <= 1'b0;
else if (request_w && mem_accept_o)
cache_access_q <= mem_cacheable_i;
assign hold_w = (|pending_q) && (cache_access_q != mem_cacheable_i);
assign cache_active_o = (|pending_q) ? cache_access_q : mem_cacheable_i;
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_crossbar:2.1
// IP Revision: 6
(* X_CORE_INFO = "axi_crossbar_v2_1_axi_crossbar,Vivado 2015.2" *)
(* CHECK_LICENSE_TYPE = "system_xbar_0,axi_crossbar_v2_1_axi_crossbar,{}" *)
(* CORE_GENERATION_INFO = "system_xbar_0,axi_crossbar_v2_1_axi_crossbar,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_crossbar,x_ipVersion=2.1,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=VERILOG,C_FAMILY=zynq,C_NUM_SLAVE_SLOTS=1,C_NUM_MASTER_SLOTS=2,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_PROTOCOL=2,C_NUM_ADDR_RANGES=1,C_M_AXI_BASE_ADDR=0x00000000412100000000000041200000,C_M_AXI_ADDR_WIDTH=0x0000001000000010,C_S_AXI_BASE_ID=0x00000000,C_S_AXI_THREAD_ID_WIDTH=0x00000000,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_M_AXI_WRITE_CONNECTIVITY=0xFFFFFFFFFFFFFFFF,C_M_AXI_READ_CONNECTIVITY=0xFFFFFFFFFFFFFFFF,C_R_REGISTER=1,C_S_AXI_SINGLE_THREAD=0x00000001,C_S_AXI_WRITE_ACCEPTANCE=0x00000001,C_S_AXI_READ_ACCEPTANCE=0x00000001,C_M_AXI_WRITE_ISSUING=0x0000000100000001,C_M_AXI_READ_ISSUING=0x0000000100000001,C_S_AXI_ARB_PRIORITY=0x00000000,C_M_AXI_SECURE=0x00000000,C_CONNECTIVITY_MODE=0}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module system_xbar_0 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
input wire [0 : 0] s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
output wire [0 : 0] s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
input wire [0 : 0] s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
output wire [0 : 0] s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
output wire [0 : 0] s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
input wire [0 : 0] s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
input wire [0 : 0] s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
output wire [0 : 0] s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
output wire [0 : 0] s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
input wire [0 : 0] s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32]" *)
output wire [63 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3]" *)
output wire [5 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1]" *)
output wire [1 : 0] m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1]" *)
input wire [1 : 0] m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32]" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4]" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1]" *)
output wire [1 : 0] m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1]" *)
input wire [1 : 0] m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2]" *)
input wire [3 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1]" *)
input wire [1 : 0] m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1]" *)
output wire [1 : 0] m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32]" *)
output wire [63 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3]" *)
output wire [5 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1]" *)
output wire [1 : 0] m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1]" *)
input wire [1 : 0] m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32]" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2]" *)
input wire [3 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1]" *)
input wire [1 : 0] m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1]" *)
output wire [1 : 0] m_axi_rready;
axi_crossbar_v2_1_axi_crossbar #(
.C_FAMILY("zynq"),
.C_NUM_SLAVE_SLOTS(1),
.C_NUM_MASTER_SLOTS(2),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_PROTOCOL(2),
.C_NUM_ADDR_RANGES(1),
.C_M_AXI_BASE_ADDR(128'H00000000412100000000000041200000),
.C_M_AXI_ADDR_WIDTH(64'H0000001000000010),
.C_S_AXI_BASE_ID(32'H00000000),
.C_S_AXI_THREAD_ID_WIDTH(32'H00000000),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_M_AXI_WRITE_CONNECTIVITY(64'HFFFFFFFFFFFFFFFF),
.C_M_AXI_READ_CONNECTIVITY(64'HFFFFFFFFFFFFFFFF),
.C_R_REGISTER(1),
.C_S_AXI_SINGLE_THREAD(32'H00000001),
.C_S_AXI_WRITE_ACCEPTANCE(32'H00000001),
.C_S_AXI_READ_ACCEPTANCE(32'H00000001),
.C_M_AXI_WRITE_ISSUING(64'H0000000100000001),
.C_M_AXI_READ_ISSUING(64'H0000000100000001),
.C_S_AXI_ARB_PRIORITY(32'H00000000),
.C_M_AXI_SECURE(32'H00000000),
.C_CONNECTIVITY_MODE(0)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(8'H00),
.s_axi_awsize(3'H0),
.s_axi_awburst(2'H0),
.s_axi_awlock(1'H0),
.s_axi_awcache(4'H0),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(4'H0),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(1'H1),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(8'H00),
.s_axi_arsize(3'H0),
.s_axi_arburst(2'H0),
.s_axi_arlock(1'H0),
.s_axi_arcache(4'H0),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(4'H0),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(2'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(2'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(2'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(2'H3),
.m_axi_ruser(2'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND2_TB_V
`define SKY130_FD_SC_HDLL__AND2_TB_V
/**
* and2: 2-input AND.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__and2.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hdll__and2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND2_TB_V
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/* FIXME: this module does not work. Find out why. */
module vgafb_asfifo #(
/* NB: those are fixed in this implementation */
parameter DATA_WIDTH = 18,
parameter ADDRESS_WIDTH = 11
) (
/* Reading port */
output [17:0] Data_out,
output Empty_out,
input ReadEn_in,
input RClk,
/* Writing port */
input [17:0] Data_in,
output Full_out,
input WriteEn_in,
input WClk,
input Clear_in
);
wire full;
wire empty;
FIFO16 #(
.DATA_WIDTH(9),
.FIRST_WORD_FALL_THROUGH("TRUE")
) fifo_lo (
.ALMOSTEMPTY(),
.ALMOSTFULL(),
.DO(Data_out[7:0]),
.DOP(Data_out[8]),
.EMPTY(empty),
.FULL(full),
.RDCOUNT(),
.RDERR(),
.WRCOUNT(),
.WRERR(),
.DI(Data_in[7:0]),
.DIP(Data_in[8]),
.RDCLK(RClk),
.RDEN(ReadEn_in & ~empty & ~Clear_in),
.RST(Clear_in),
.WRCLK(WClk),
.WREN(WriteEn_in & ~full & ~Clear_in)
);
assign Empty_out = empty;
assign Full_out = full;
FIFO16 #(
.DATA_WIDTH(9),
.FIRST_WORD_FALL_THROUGH("TRUE")
) fifo_hi (
.ALMOSTEMPTY(),
.ALMOSTFULL(),
.DO(Data_out[16:9]),
.DOP(Data_out[17]),
.EMPTY(),
.FULL(),
.RDCOUNT(),
.RDERR(),
.WRCOUNT(),
.WRERR(),
.DI(Data_in[16:9]),
.DIP(Data_in[17]),
.RDCLK(RClk),
.RDEN(ReadEn_in & ~empty & ~Clear_in),
.RST(Clear_in),
.WRCLK(WClk),
.WREN(WriteEn_in & ~full & ~Clear_in)
);
endmodule
|
module Timer (rst, clk, Beg, Ready, Cycend, scrinit);
input rst;
input clk;
input Beg;
input [2:0] scrinit;
output reg Ready, Cycend;
reg temp_ready;
reg temp_cycend;
reg [20:0]temp;
initial begin
Ready=0;
temp=21'b111111111111111111111;
end
always @(negedge clk) begin
if(rst) begin
temp = 0;
temp_ready=0;
temp_cycend=0;
end
else begin
if(scrinit == 3'b110) begin
if(temp == 250000)begin
temp_ready = 1;
temp_cycend = 0;
temp = temp+1;
end
else begin
if(Beg) begin
temp = 0;
temp_ready=0;
temp_cycend = 0;
end
else begin
if(temp == 21'b111111111111111111111) begin
temp=0;
temp_ready=0;
temp_cycend=0;
end
else begin
if(temp == 260000) begin
temp = temp+1;
temp_ready=1;
temp_cycend=1;
end
else
temp = temp+1;
end
end
end
end
else begin
if(temp == 2060000)begin
temp_ready = 1;
temp_cycend = 0;
temp = temp+1;
end
else begin
if(Beg) begin
temp = 0;
temp_ready=0;
temp_cycend = 0;
end
else begin
if(temp == 21'b111111111111111111111) begin
temp=0;
temp_ready=0;
temp_cycend=0;
end
else begin
if(temp == 2097150) begin
temp = temp+1;
temp_ready=1;
temp_cycend=1;
end
else
temp = temp+1;
end
end
end
end
end
end
always @(temp_ready or temp_cycend) begin
Ready=temp_ready;
Cycend=temp_cycend;
end
endmodule
|
//
// Generated by Bluespec Compiler (build 0fccbb13)
//
//
// Ports:
// Name I/O size props
// RDY_set_verbosity O 1 const
// RDY_req_reset O 1 const
// RDY_rsp_reset O 1 const
// valid O 1
// word O 64
// CLK I 1 clock
// RST_N I 1 reset
// set_verbosity_verbosity I 4 reg
// req_is_OP_not_OP_32 I 1
// req_f3 I 3
// req_v1 I 64
// req_v2 I 64
// EN_set_verbosity I 1
// EN_req_reset I 1 unused
// EN_rsp_reset I 1 unused
// EN_req I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkRISCV_MBox(CLK,
RST_N,
set_verbosity_verbosity,
EN_set_verbosity,
RDY_set_verbosity,
EN_req_reset,
RDY_req_reset,
EN_rsp_reset,
RDY_rsp_reset,
req_is_OP_not_OP_32,
req_f3,
req_v1,
req_v2,
EN_req,
valid,
word);
input CLK;
input RST_N;
// action method set_verbosity
input [3 : 0] set_verbosity_verbosity;
input EN_set_verbosity;
output RDY_set_verbosity;
// action method req_reset
input EN_req_reset;
output RDY_req_reset;
// action method rsp_reset
input EN_rsp_reset;
output RDY_rsp_reset;
// action method req
input req_is_OP_not_OP_32;
input [2 : 0] req_f3;
input [63 : 0] req_v1;
input [63 : 0] req_v2;
input EN_req;
// value method valid
output valid;
// value method word
output [63 : 0] word;
// signals for module outputs
wire [63 : 0] word;
wire RDY_req_reset, RDY_rsp_reset, RDY_set_verbosity, valid;
// inlined wires
wire dw_valid$whas;
// register cfg_verbosity
reg [3 : 0] cfg_verbosity;
wire [3 : 0] cfg_verbosity$D_IN;
wire cfg_verbosity$EN;
// register intDiv_rg_denom2
reg [63 : 0] intDiv_rg_denom2;
reg [63 : 0] intDiv_rg_denom2$D_IN;
wire intDiv_rg_denom2$EN;
// register intDiv_rg_denom_is_signed
reg intDiv_rg_denom_is_signed;
wire intDiv_rg_denom_is_signed$D_IN, intDiv_rg_denom_is_signed$EN;
// register intDiv_rg_n
reg [63 : 0] intDiv_rg_n;
reg [63 : 0] intDiv_rg_n$D_IN;
wire intDiv_rg_n$EN;
// register intDiv_rg_numer_is_signed
reg intDiv_rg_numer_is_signed;
wire intDiv_rg_numer_is_signed$D_IN, intDiv_rg_numer_is_signed$EN;
// register intDiv_rg_quo
reg [63 : 0] intDiv_rg_quo;
reg [63 : 0] intDiv_rg_quo$D_IN;
wire intDiv_rg_quo$EN;
// register intDiv_rg_quoIsNeg
reg intDiv_rg_quoIsNeg;
wire intDiv_rg_quoIsNeg$D_IN, intDiv_rg_quoIsNeg$EN;
// register intDiv_rg_remIsNeg
reg intDiv_rg_remIsNeg;
wire intDiv_rg_remIsNeg$D_IN, intDiv_rg_remIsNeg$EN;
// register intDiv_rg_state
reg [2 : 0] intDiv_rg_state;
reg [2 : 0] intDiv_rg_state$D_IN;
wire intDiv_rg_state$EN;
// register rg_f3
reg [2 : 0] rg_f3;
wire [2 : 0] rg_f3$D_IN;
wire rg_f3$EN;
// register rg_is_OP_not_OP_32
reg rg_is_OP_not_OP_32;
wire rg_is_OP_not_OP_32$D_IN, rg_is_OP_not_OP_32$EN;
// register rg_result
reg [63 : 0] rg_result;
wire [63 : 0] rg_result$D_IN;
wire rg_result$EN;
// register rg_state
reg [1 : 0] rg_state;
wire [1 : 0] rg_state$D_IN;
wire rg_state$EN;
// register rg_v1
reg [63 : 0] rg_v1;
reg [63 : 0] rg_v1$D_IN;
wire rg_v1$EN;
// register rg_v2
reg [63 : 0] rg_v2;
wire [63 : 0] rg_v2$D_IN;
wire rg_v2$EN;
// rule scheduling signals
wire CAN_FIRE_RL_intDiv_rl_loop1,
CAN_FIRE_RL_intDiv_rl_loop2,
CAN_FIRE_RL_intDiv_rl_start_div_by_zero,
CAN_FIRE_RL_intDiv_rl_start_overflow,
CAN_FIRE_RL_intDiv_rl_start_s,
CAN_FIRE_RL_rg_div_rem,
CAN_FIRE_RL_rl_mul,
CAN_FIRE_RL_rl_mul2,
CAN_FIRE_req,
CAN_FIRE_req_reset,
CAN_FIRE_rsp_reset,
CAN_FIRE_set_verbosity,
WILL_FIRE_RL_intDiv_rl_loop1,
WILL_FIRE_RL_intDiv_rl_loop2,
WILL_FIRE_RL_intDiv_rl_start_div_by_zero,
WILL_FIRE_RL_intDiv_rl_start_overflow,
WILL_FIRE_RL_intDiv_rl_start_s,
WILL_FIRE_RL_rg_div_rem,
WILL_FIRE_RL_rl_mul,
WILL_FIRE_RL_rl_mul2,
WILL_FIRE_req,
WILL_FIRE_req_reset,
WILL_FIRE_rsp_reset,
WILL_FIRE_set_verbosity;
// inputs to muxes for submodule ports
wire [63 : 0] MUX_dw_result$wset_1__VAL_2,
MUX_intDiv_rg_denom2$write_1__VAL_1,
MUX_intDiv_rg_denom2$write_1__VAL_2,
MUX_intDiv_rg_denom2$write_1__VAL_3,
MUX_intDiv_rg_n$write_1__VAL_1,
MUX_intDiv_rg_n$write_1__VAL_2,
MUX_intDiv_rg_quo$write_1__VAL_1,
MUX_rg_v1$write_1__VAL_1,
MUX_rg_v1$write_1__VAL_2,
MUX_rg_v1$write_1__VAL_3,
MUX_rg_v2$write_1__VAL_1;
wire [1 : 0] MUX_rg_state$write_1__VAL_1;
wire MUX_intDiv_rg_denom2$write_1__SEL_1,
MUX_intDiv_rg_denom2$write_1__SEL_2,
MUX_intDiv_rg_quo$write_1__SEL_1,
MUX_intDiv_rg_state$write_1__SEL_1,
MUX_intDiv_rg_state$write_1__SEL_2,
MUX_intDiv_rg_state$write_1__SEL_3,
MUX_rg_v1$write_1__SEL_2;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h5665;
reg [31 : 0] v__h5659;
// synopsys translate_on
// remaining internal signals
wire [127 : 0] IF_rg_v1_BIT_63_5_EQ_rg_v2_BIT_63_0_6_THEN_pro_ETC__q8,
IF_rg_v1_BIT_63_THEN_prod___1263_ELSE_prod195__q6,
SEXT_rg_v1_BITS_31_TO_0_49_87_MUL_SEXT_rg_v2_B_ETC___d189,
_0x0_CONCAT_IF_rg_v1_BIT_63_5_THEN_INV_rg_v1_08_ETC___d118,
_0x0_CONCAT_IF_rg_v1_BIT_63_5_THEN_INV_rg_v1_08_ETC___d123,
_0x0_CONCAT_IF_rg_v1_BIT_63_5_THEN_INV_rg_v1_08_ETC___d129,
_0x0_CONCAT_IF_rg_v1_BIT_63_5_THEN_INV_rg_v1_08_ETC___d133,
_0x0_CONCAT_IF_rg_v1_BIT_63_5_THEN_INV_rg_v1_08_ETC___d167,
_0x0_CONCAT_IF_rg_v1_BIT_63_5_THEN_INV_rg_v1_08_ETC___d170,
_0x0_CONCAT_IF_rg_v1_BIT_63_5_THEN_INV_rg_v1_08_ETC___d174,
_0x0_CONCAT_IF_rg_v1_BIT_63_5_THEN_INV_rg_v1_08_ETC___d178,
_0x0_CONCAT_rg_v1_BITS_31_TO_0_49_50_MUL_0x0_CO_ETC___d151,
_0x0_CONCAT_rg_v1_BITS_31_TO_0_49_50_MUL_0x0_CO_ETC___d161,
_0x0_CONCAT_rg_v1_BITS_63_TO_32_42_43_MUL_0x0_C_ETC___d146,
_0x0_CONCAT_rg_v1_BITS_63_TO_32_42_43_MUL_0x0_C_ETC___d157,
prod___1__h4585,
prod___1__h5263,
prod__h4475,
prod__h5195,
rg_v1_MUL_rg_v2___d105,
x961_PLUS_y962__q7,
x__h4587,
x__h4617,
x__h4619,
x__h4621,
x__h4961,
x__h4963,
x__h4965,
x__h5265,
x__h5295,
x__h5297,
x__h5299,
y__h4618,
y__h4620,
y__h4622,
y__h4962,
y__h4964,
y__h4966,
y__h5296,
y__h5298,
y__h5300;
wire [63 : 0] IF_rg_f3_4_BIT_1_02_THEN_rg_v1_ELSE_intDiv_rg__ETC___d203,
IF_rg_v1_BIT_63_5_THEN_INV_rg_v1_08_PLUS_1_09__ETC___d110,
IF_rg_v2_BIT_63_0_THEN_INV_rg_v2_13_PLUS_1_14__ETC___d115,
_theResult___fst__h6159,
_theResult___fst__h6189,
_theResult___fst__h6215,
_theResult___fst__h765,
_theResult___snd__h6160,
_theResult___snd__h6190,
_theResult___snd__h6216,
_theResult___snd_fst__h760,
b__h4574,
b__h5253,
denom___1__h698,
numer___1__h697,
result___1__h5934,
v__h4455,
v__h4896,
v__h5175,
v__h5542,
v__h5559,
x__h3996,
x__h4100,
x__h4159,
x__h4174,
x__h4721,
x__h5072,
x__h5123,
x__h5303,
x__h5345,
x__h5387,
y__h3857,
y__h4626,
y__h4793,
y__h5388,
y__h5490;
wire [31 : 0] IF_rg_f3_4_BIT_1_02_THEN_rg_v1_ELSE_intDiv_rg__ETC__q9,
SEXT_rg_v1_BITS_31_TO_0_49_87_MUL_SEXT_rg_v2_B_ETC__q5,
req_v1_BITS_31_TO_0__q1,
req_v2_BITS_31_TO_0__q2,
rg_v1_BITS_31_TO_0__q3,
rg_v2_BITS_31_TO_0__q4;
wire IF_intDiv_rg_numer_is_signed_THEN_rg_v1_BIT_63_ETC___d39,
intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_63__ETC___d47,
rg_v1_BIT_63_5_EQ_rg_v2_BIT_63_0___d36,
rg_v1_ULT_intDiv_rg_denom2_4___d59,
rg_v1_ULT_rg_v2___d55;
// action method set_verbosity
assign RDY_set_verbosity = 1'd1 ;
assign CAN_FIRE_set_verbosity = 1'd1 ;
assign WILL_FIRE_set_verbosity = EN_set_verbosity ;
// action method req_reset
assign RDY_req_reset = 1'd1 ;
assign CAN_FIRE_req_reset = 1'd1 ;
assign WILL_FIRE_req_reset = EN_req_reset ;
// action method rsp_reset
assign RDY_rsp_reset = 1'd1 ;
assign CAN_FIRE_rsp_reset = 1'd1 ;
assign WILL_FIRE_rsp_reset = EN_rsp_reset ;
// action method req
assign CAN_FIRE_req = 1'd1 ;
assign WILL_FIRE_req = EN_req ;
// value method valid
assign valid = dw_valid$whas ;
// value method word
assign word =
WILL_FIRE_RL_rl_mul2 ? rg_result : MUX_dw_result$wset_1__VAL_2 ;
// rule RL_rl_mul
assign CAN_FIRE_RL_rl_mul = rg_state == 2'd0 ;
assign WILL_FIRE_RL_rl_mul = rg_state == 2'd0 ;
// rule RL_rl_mul2
assign CAN_FIRE_RL_rl_mul2 = rg_state == 2'd1 ;
assign WILL_FIRE_RL_rl_mul2 = CAN_FIRE_RL_rl_mul2 ;
// rule RL_rg_div_rem
assign CAN_FIRE_RL_rg_div_rem =
rg_state == 2'd2 && intDiv_rg_state == 3'd4 ;
assign WILL_FIRE_RL_rg_div_rem = CAN_FIRE_RL_rg_div_rem ;
// rule RL_intDiv_rl_start_div_by_zero
assign CAN_FIRE_RL_intDiv_rl_start_div_by_zero =
intDiv_rg_state == 3'd1 && rg_v2 == 64'd0 ;
assign WILL_FIRE_RL_intDiv_rl_start_div_by_zero =
CAN_FIRE_RL_intDiv_rl_start_div_by_zero ;
// rule RL_intDiv_rl_start_overflow
assign CAN_FIRE_RL_intDiv_rl_start_overflow =
intDiv_rg_state == 3'd1 && intDiv_rg_numer_is_signed &&
rg_v1 == 64'h8000000000000000 &&
intDiv_rg_denom_is_signed &&
rg_v2 == 64'hFFFFFFFFFFFFFFFF ;
assign WILL_FIRE_RL_intDiv_rl_start_overflow =
CAN_FIRE_RL_intDiv_rl_start_overflow ;
// rule RL_intDiv_rl_start_s
assign CAN_FIRE_RL_intDiv_rl_start_s =
intDiv_rg_state == 3'd1 && rg_v2 != 64'd0 &&
(!intDiv_rg_numer_is_signed || rg_v1 != 64'h8000000000000000 ||
!intDiv_rg_denom_is_signed ||
rg_v2 != 64'hFFFFFFFFFFFFFFFF) ;
assign WILL_FIRE_RL_intDiv_rl_start_s = CAN_FIRE_RL_intDiv_rl_start_s ;
// rule RL_intDiv_rl_loop1
assign CAN_FIRE_RL_intDiv_rl_loop1 = intDiv_rg_state == 3'd2 ;
assign WILL_FIRE_RL_intDiv_rl_loop1 = CAN_FIRE_RL_intDiv_rl_loop1 ;
// rule RL_intDiv_rl_loop2
assign CAN_FIRE_RL_intDiv_rl_loop2 = intDiv_rg_state == 3'd3 ;
assign WILL_FIRE_RL_intDiv_rl_loop2 = CAN_FIRE_RL_intDiv_rl_loop2 ;
// inputs to muxes for submodule ports
assign MUX_intDiv_rg_denom2$write_1__SEL_1 =
WILL_FIRE_RL_intDiv_rl_loop1 &&
intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_63__ETC___d47 ;
assign MUX_intDiv_rg_denom2$write_1__SEL_2 =
WILL_FIRE_RL_intDiv_rl_loop2 && !rg_v1_ULT_rg_v2___d55 &&
rg_v1_ULT_intDiv_rg_denom2_4___d59 ;
assign MUX_intDiv_rg_quo$write_1__SEL_1 =
WILL_FIRE_RL_intDiv_rl_loop2 &&
(rg_v1_ULT_rg_v2___d55 && intDiv_rg_quoIsNeg ||
!rg_v1_ULT_rg_v2___d55 && !rg_v1_ULT_intDiv_rg_denom2_4___d59) ;
assign MUX_intDiv_rg_state$write_1__SEL_1 = EN_req && req_f3[2] ;
assign MUX_intDiv_rg_state$write_1__SEL_2 =
WILL_FIRE_RL_intDiv_rl_loop2 && rg_v1_ULT_rg_v2___d55 ;
assign MUX_intDiv_rg_state$write_1__SEL_3 =
WILL_FIRE_RL_intDiv_rl_loop1 &&
!intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_63__ETC___d47 ;
assign MUX_rg_v1$write_1__SEL_2 =
WILL_FIRE_RL_intDiv_rl_loop2 &&
(rg_v1_ULT_rg_v2___d55 && intDiv_rg_remIsNeg ||
!rg_v1_ULT_rg_v2___d55 && !rg_v1_ULT_intDiv_rg_denom2_4___d59) ;
assign MUX_dw_result$wset_1__VAL_2 =
rg_is_OP_not_OP_32 ?
IF_rg_f3_4_BIT_1_02_THEN_rg_v1_ELSE_intDiv_rg__ETC___d203 :
result___1__h5934 ;
assign MUX_intDiv_rg_denom2$write_1__VAL_1 =
{ intDiv_rg_denom2[62:0], 1'd0 } ;
assign MUX_intDiv_rg_denom2$write_1__VAL_2 =
{ 1'd0, intDiv_rg_denom2[63:1] } ;
assign MUX_intDiv_rg_denom2$write_1__VAL_3 =
(intDiv_rg_numer_is_signed && intDiv_rg_denom_is_signed) ?
denom___1__h698 :
_theResult___snd_fst__h760 ;
assign MUX_intDiv_rg_n$write_1__VAL_1 = { intDiv_rg_n[62:0], 1'd0 } ;
assign MUX_intDiv_rg_n$write_1__VAL_2 = { 1'd0, intDiv_rg_n[63:1] } ;
assign MUX_intDiv_rg_quo$write_1__VAL_1 =
rg_v1_ULT_rg_v2___d55 ? x__h4100 : x__h4174 ;
assign MUX_rg_state$write_1__VAL_1 = req_f3[2] ? 2'd2 : 2'd0 ;
assign MUX_rg_v1$write_1__VAL_1 =
req_is_OP_not_OP_32 ? req_v1 : _theResult___fst__h6159 ;
assign MUX_rg_v1$write_1__VAL_2 =
rg_v1_ULT_rg_v2___d55 ? x__h4159 : x__h3996 ;
assign MUX_rg_v1$write_1__VAL_3 =
intDiv_rg_numer_is_signed ? numer___1__h697 : rg_v1 ;
assign MUX_rg_v2$write_1__VAL_1 =
req_is_OP_not_OP_32 ? req_v2 : _theResult___snd__h6160 ;
// inlined wires
assign dw_valid$whas = WILL_FIRE_RL_rg_div_rem || WILL_FIRE_RL_rl_mul2 ;
// register cfg_verbosity
assign cfg_verbosity$D_IN = set_verbosity_verbosity ;
assign cfg_verbosity$EN = EN_set_verbosity ;
// register intDiv_rg_denom2
always@(MUX_intDiv_rg_denom2$write_1__SEL_1 or
MUX_intDiv_rg_denom2$write_1__VAL_1 or
MUX_intDiv_rg_denom2$write_1__SEL_2 or
MUX_intDiv_rg_denom2$write_1__VAL_2 or
WILL_FIRE_RL_intDiv_rl_start_s or
MUX_intDiv_rg_denom2$write_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_intDiv_rg_denom2$write_1__SEL_1:
intDiv_rg_denom2$D_IN = MUX_intDiv_rg_denom2$write_1__VAL_1;
MUX_intDiv_rg_denom2$write_1__SEL_2:
intDiv_rg_denom2$D_IN = MUX_intDiv_rg_denom2$write_1__VAL_2;
WILL_FIRE_RL_intDiv_rl_start_s:
intDiv_rg_denom2$D_IN = MUX_intDiv_rg_denom2$write_1__VAL_3;
default: intDiv_rg_denom2$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign intDiv_rg_denom2$EN =
WILL_FIRE_RL_intDiv_rl_loop1 &&
intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_63__ETC___d47 ||
WILL_FIRE_RL_intDiv_rl_loop2 && !rg_v1_ULT_rg_v2___d55 &&
rg_v1_ULT_intDiv_rg_denom2_4___d59 ||
WILL_FIRE_RL_intDiv_rl_start_s ;
// register intDiv_rg_denom_is_signed
assign intDiv_rg_denom_is_signed$D_IN = !req_f3[0] ;
assign intDiv_rg_denom_is_signed$EN = MUX_intDiv_rg_state$write_1__SEL_1 ;
// register intDiv_rg_n
always@(MUX_intDiv_rg_denom2$write_1__SEL_1 or
MUX_intDiv_rg_n$write_1__VAL_1 or
MUX_intDiv_rg_denom2$write_1__SEL_2 or
MUX_intDiv_rg_n$write_1__VAL_2 or WILL_FIRE_RL_intDiv_rl_start_s)
begin
case (1'b1) // synopsys parallel_case
MUX_intDiv_rg_denom2$write_1__SEL_1:
intDiv_rg_n$D_IN = MUX_intDiv_rg_n$write_1__VAL_1;
MUX_intDiv_rg_denom2$write_1__SEL_2:
intDiv_rg_n$D_IN = MUX_intDiv_rg_n$write_1__VAL_2;
WILL_FIRE_RL_intDiv_rl_start_s: intDiv_rg_n$D_IN = 64'd1;
default: intDiv_rg_n$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign intDiv_rg_n$EN =
WILL_FIRE_RL_intDiv_rl_loop1 &&
intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_63__ETC___d47 ||
WILL_FIRE_RL_intDiv_rl_loop2 && !rg_v1_ULT_rg_v2___d55 &&
rg_v1_ULT_intDiv_rg_denom2_4___d59 ||
WILL_FIRE_RL_intDiv_rl_start_s ;
// register intDiv_rg_numer_is_signed
assign intDiv_rg_numer_is_signed$D_IN = !req_f3[0] ;
assign intDiv_rg_numer_is_signed$EN = MUX_intDiv_rg_state$write_1__SEL_1 ;
// register intDiv_rg_quo
always@(MUX_intDiv_rg_quo$write_1__SEL_1 or
MUX_intDiv_rg_quo$write_1__VAL_1 or
WILL_FIRE_RL_intDiv_rl_start_overflow or
rg_v1 or
WILL_FIRE_RL_intDiv_rl_start_s or
WILL_FIRE_RL_intDiv_rl_start_div_by_zero)
begin
case (1'b1) // synopsys parallel_case
MUX_intDiv_rg_quo$write_1__SEL_1:
intDiv_rg_quo$D_IN = MUX_intDiv_rg_quo$write_1__VAL_1;
WILL_FIRE_RL_intDiv_rl_start_overflow: intDiv_rg_quo$D_IN = rg_v1;
WILL_FIRE_RL_intDiv_rl_start_s: intDiv_rg_quo$D_IN = 64'd0;
WILL_FIRE_RL_intDiv_rl_start_div_by_zero:
intDiv_rg_quo$D_IN = 64'hFFFFFFFFFFFFFFFF;
default: intDiv_rg_quo$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign intDiv_rg_quo$EN =
MUX_intDiv_rg_quo$write_1__SEL_1 ||
WILL_FIRE_RL_intDiv_rl_start_overflow ||
WILL_FIRE_RL_intDiv_rl_start_s ||
WILL_FIRE_RL_intDiv_rl_start_div_by_zero ;
// register intDiv_rg_quoIsNeg
assign intDiv_rg_quoIsNeg$D_IN =
(intDiv_rg_numer_is_signed && intDiv_rg_denom_is_signed) ?
!rg_v1_BIT_63_5_EQ_rg_v2_BIT_63_0___d36 :
IF_intDiv_rg_numer_is_signed_THEN_rg_v1_BIT_63_ETC___d39 ;
assign intDiv_rg_quoIsNeg$EN = CAN_FIRE_RL_intDiv_rl_start_s ;
// register intDiv_rg_remIsNeg
assign intDiv_rg_remIsNeg$D_IN =
(intDiv_rg_numer_is_signed && intDiv_rg_denom_is_signed) ?
rg_v1[63] :
intDiv_rg_numer_is_signed && rg_v1[63] ;
assign intDiv_rg_remIsNeg$EN = CAN_FIRE_RL_intDiv_rl_start_s ;
// register intDiv_rg_state
always@(MUX_intDiv_rg_state$write_1__SEL_1 or
MUX_intDiv_rg_state$write_1__SEL_2 or
MUX_intDiv_rg_state$write_1__SEL_3 or
WILL_FIRE_RL_intDiv_rl_start_s or
WILL_FIRE_RL_intDiv_rl_start_overflow or
WILL_FIRE_RL_intDiv_rl_start_div_by_zero)
case (1'b1)
MUX_intDiv_rg_state$write_1__SEL_1: intDiv_rg_state$D_IN = 3'd1;
MUX_intDiv_rg_state$write_1__SEL_2: intDiv_rg_state$D_IN = 3'd4;
MUX_intDiv_rg_state$write_1__SEL_3: intDiv_rg_state$D_IN = 3'd3;
WILL_FIRE_RL_intDiv_rl_start_s: intDiv_rg_state$D_IN = 3'd2;
WILL_FIRE_RL_intDiv_rl_start_overflow ||
WILL_FIRE_RL_intDiv_rl_start_div_by_zero:
intDiv_rg_state$D_IN = 3'd4;
default: intDiv_rg_state$D_IN = 3'b010 /* unspecified value */ ;
endcase
assign intDiv_rg_state$EN =
WILL_FIRE_RL_intDiv_rl_loop2 && rg_v1_ULT_rg_v2___d55 ||
EN_req && req_f3[2] ||
WILL_FIRE_RL_intDiv_rl_loop1 &&
!intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_63__ETC___d47 ||
WILL_FIRE_RL_intDiv_rl_start_s ||
WILL_FIRE_RL_intDiv_rl_start_overflow ||
WILL_FIRE_RL_intDiv_rl_start_div_by_zero ;
// register rg_f3
assign rg_f3$D_IN = req_f3 ;
assign rg_f3$EN = EN_req ;
// register rg_is_OP_not_OP_32
assign rg_is_OP_not_OP_32$D_IN = req_is_OP_not_OP_32 ;
assign rg_is_OP_not_OP_32$EN = EN_req ;
// register rg_result
assign rg_result$D_IN =
(rg_is_OP_not_OP_32 && rg_f3 == 3'b0) ?
rg_v1_MUL_rg_v2___d105[63:0] :
v__h4455 ;
assign rg_result$EN = rg_state == 2'd0 ;
// register rg_state
assign rg_state$D_IN = EN_req ? MUX_rg_state$write_1__VAL_1 : 2'd1 ;
assign rg_state$EN = EN_req || WILL_FIRE_RL_rl_mul ;
// register rg_v1
always@(EN_req or
MUX_rg_v1$write_1__VAL_1 or
MUX_rg_v1$write_1__SEL_2 or
MUX_rg_v1$write_1__VAL_2 or
WILL_FIRE_RL_intDiv_rl_start_s or
MUX_rg_v1$write_1__VAL_3 or WILL_FIRE_RL_intDiv_rl_start_overflow)
case (1'b1)
EN_req: rg_v1$D_IN = MUX_rg_v1$write_1__VAL_1;
MUX_rg_v1$write_1__SEL_2: rg_v1$D_IN = MUX_rg_v1$write_1__VAL_2;
WILL_FIRE_RL_intDiv_rl_start_s: rg_v1$D_IN = MUX_rg_v1$write_1__VAL_3;
WILL_FIRE_RL_intDiv_rl_start_overflow: rg_v1$D_IN = 64'd0;
default: rg_v1$D_IN = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
assign rg_v1$EN =
MUX_rg_v1$write_1__SEL_2 || EN_req ||
WILL_FIRE_RL_intDiv_rl_start_s ||
WILL_FIRE_RL_intDiv_rl_start_overflow ;
// register rg_v2
assign rg_v2$D_IN =
EN_req ?
MUX_rg_v2$write_1__VAL_1 :
MUX_intDiv_rg_denom2$write_1__VAL_3 ;
assign rg_v2$EN = EN_req || WILL_FIRE_RL_intDiv_rl_start_s ;
// remaining internal signals
assign IF_intDiv_rg_numer_is_signed_THEN_rg_v1_BIT_63_ETC___d39 =
intDiv_rg_numer_is_signed ?
rg_v1[63] :
intDiv_rg_denom_is_signed && rg_v2[63] ;
assign IF_rg_f3_4_BIT_1_02_THEN_rg_v1_ELSE_intDiv_rg__ETC___d203 =
rg_f3[1] ? rg_v1 : intDiv_rg_quo ;
assign IF_rg_f3_4_BIT_1_02_THEN_rg_v1_ELSE_intDiv_rg__ETC__q9 =
IF_rg_f3_4_BIT_1_02_THEN_rg_v1_ELSE_intDiv_rg__ETC___d203[31:0] ;
assign IF_rg_v1_BIT_63_5_EQ_rg_v2_BIT_63_0_6_THEN_pro_ETC__q8 =
rg_v1_BIT_63_5_EQ_rg_v2_BIT_63_0___d36 ?
prod__h4475 :
prod___1__h4585 ;
assign IF_rg_v1_BIT_63_5_THEN_INV_rg_v1_08_PLUS_1_09__ETC___d110 =
rg_v1[63] ? b__h5253 : rg_v1 ;
assign IF_rg_v1_BIT_63_THEN_prod___1263_ELSE_prod195__q6 =
rg_v1[63] ? prod___1__h5263 : prod__h5195 ;
assign IF_rg_v2_BIT_63_0_THEN_INV_rg_v2_13_PLUS_1_14__ETC___d115 =
rg_v2[63] ? b__h4574 : rg_v2 ;
assign SEXT_rg_v1_BITS_31_TO_0_49_87_MUL_SEXT_rg_v2_B_ETC___d189 =
{ {32{rg_v1_BITS_31_TO_0__q3[31]}}, rg_v1_BITS_31_TO_0__q3 } *
{ {32{rg_v2_BITS_31_TO_0__q4[31]}}, rg_v2_BITS_31_TO_0__q4 } ;
assign SEXT_rg_v1_BITS_31_TO_0_49_87_MUL_SEXT_rg_v2_B_ETC__q5 =
SEXT_rg_v1_BITS_31_TO_0_49_87_MUL_SEXT_rg_v2_B_ETC___d189[31:0] ;
assign _0x0_CONCAT_IF_rg_v1_BIT_63_5_THEN_INV_rg_v1_08_ETC___d118 =
x__h5303 * y__h4626 ;
assign _0x0_CONCAT_IF_rg_v1_BIT_63_5_THEN_INV_rg_v1_08_ETC___d123 =
x__h5387 * y__h4626 ;
assign _0x0_CONCAT_IF_rg_v1_BIT_63_5_THEN_INV_rg_v1_08_ETC___d129 =
x__h5303 * y__h4793 ;
assign _0x0_CONCAT_IF_rg_v1_BIT_63_5_THEN_INV_rg_v1_08_ETC___d133 =
x__h5387 * y__h4793 ;
assign _0x0_CONCAT_IF_rg_v1_BIT_63_5_THEN_INV_rg_v1_08_ETC___d167 =
x__h5303 * y__h5388 ;
assign _0x0_CONCAT_IF_rg_v1_BIT_63_5_THEN_INV_rg_v1_08_ETC___d170 =
x__h5387 * y__h5388 ;
assign _0x0_CONCAT_IF_rg_v1_BIT_63_5_THEN_INV_rg_v1_08_ETC___d174 =
x__h5303 * y__h5490 ;
assign _0x0_CONCAT_IF_rg_v1_BIT_63_5_THEN_INV_rg_v1_08_ETC___d178 =
x__h5387 * y__h5490 ;
assign _0x0_CONCAT_rg_v1_BITS_31_TO_0_49_50_MUL_0x0_CO_ETC___d151 =
x__h5123 * y__h5388 ;
assign _0x0_CONCAT_rg_v1_BITS_31_TO_0_49_50_MUL_0x0_CO_ETC___d161 =
x__h5123 * y__h5490 ;
assign _0x0_CONCAT_rg_v1_BITS_63_TO_32_42_43_MUL_0x0_C_ETC___d146 =
x__h5072 * y__h5388 ;
assign _0x0_CONCAT_rg_v1_BITS_63_TO_32_42_43_MUL_0x0_C_ETC___d157 =
x__h5072 * y__h5490 ;
assign _theResult___fst__h6159 =
req_f3[0] ? _theResult___fst__h6215 : _theResult___fst__h6189 ;
assign _theResult___fst__h6189 =
{ {32{req_v1_BITS_31_TO_0__q1[31]}}, req_v1_BITS_31_TO_0__q1 } ;
assign _theResult___fst__h6215 = { 32'd0, req_v1[31:0] } ;
assign _theResult___fst__h765 =
intDiv_rg_denom_is_signed ? denom___1__h698 : rg_v2 ;
assign _theResult___snd__h6160 =
req_f3[0] ? _theResult___snd__h6216 : _theResult___snd__h6190 ;
assign _theResult___snd__h6190 =
{ {32{req_v2_BITS_31_TO_0__q2[31]}}, req_v2_BITS_31_TO_0__q2 } ;
assign _theResult___snd__h6216 = { 32'd0, req_v2[31:0] } ;
assign _theResult___snd_fst__h760 =
intDiv_rg_numer_is_signed ? rg_v2 : _theResult___fst__h765 ;
assign b__h4574 = x__h4721 + 64'd1 ;
assign b__h5253 = x__h5345 + 64'd1 ;
assign denom___1__h698 = rg_v2[63] ? -rg_v2 : rg_v2 ;
assign intDiv_rg_denom2_4_ULE_0_CONCAT_rg_v1_BITS_63__ETC___d47 =
intDiv_rg_denom2 <= y__h3857 ;
assign numer___1__h697 = rg_v1[63] ? x__h4159 : rg_v1 ;
assign prod___1__h4585 = x__h4587 + 128'd1 ;
assign prod___1__h5263 = x__h5265 + 128'd1 ;
assign prod__h4475 = x__h4617 + y__h4618 ;
assign prod__h5195 = x__h5295 + y__h5296 ;
assign req_v1_BITS_31_TO_0__q1 = req_v1[31:0] ;
assign req_v2_BITS_31_TO_0__q2 = req_v2[31:0] ;
assign result___1__h5934 =
{ {32{IF_rg_f3_4_BIT_1_02_THEN_rg_v1_ELSE_intDiv_rg__ETC__q9[31]}},
IF_rg_f3_4_BIT_1_02_THEN_rg_v1_ELSE_intDiv_rg__ETC__q9 } ;
assign rg_v1_BITS_31_TO_0__q3 = rg_v1[31:0] ;
assign rg_v1_BIT_63_5_EQ_rg_v2_BIT_63_0___d36 = rg_v1[63] == rg_v2[63] ;
assign rg_v1_MUL_rg_v2___d105 = rg_v1 * rg_v2 ;
assign rg_v1_ULT_intDiv_rg_denom2_4___d59 = rg_v1 < intDiv_rg_denom2 ;
assign rg_v1_ULT_rg_v2___d55 = rg_v1 < rg_v2 ;
assign rg_v2_BITS_31_TO_0__q4 = rg_v2[31:0] ;
assign v__h4455 =
(rg_is_OP_not_OP_32 && rg_f3 == 3'b001) ?
IF_rg_v1_BIT_63_5_EQ_rg_v2_BIT_63_0_6_THEN_pro_ETC__q8[127:64] :
v__h4896 ;
assign v__h4896 =
(rg_is_OP_not_OP_32 && rg_f3 == 3'b011) ?
x961_PLUS_y962__q7[127:64] :
v__h5175 ;
assign v__h5175 =
(rg_is_OP_not_OP_32 && rg_f3 == 3'b010) ?
IF_rg_v1_BIT_63_THEN_prod___1263_ELSE_prod195__q6[127:64] :
v__h5542 ;
assign v__h5542 =
(!rg_is_OP_not_OP_32 && rg_f3 == 3'b0) ?
v__h5559 :
64'hFFFFFFFFFFFFFFFF ;
assign v__h5559 =
{ {32{SEXT_rg_v1_BITS_31_TO_0_49_87_MUL_SEXT_rg_v2_B_ETC__q5[31]}},
SEXT_rg_v1_BITS_31_TO_0_49_87_MUL_SEXT_rg_v2_B_ETC__q5 } ;
assign x961_PLUS_y962__q7 = x__h4961 + y__h4962 ;
assign x__h3996 = rg_v1 - intDiv_rg_denom2 ;
assign x__h4100 = -intDiv_rg_quo ;
assign x__h4159 = -rg_v1 ;
assign x__h4174 = intDiv_rg_quo + intDiv_rg_n ;
assign x__h4587 = ~prod__h4475 ;
assign x__h4617 = x__h4619 + y__h4620 ;
assign x__h4619 = x__h4621 + y__h4622 ;
assign x__h4621 =
{ _0x0_CONCAT_IF_rg_v1_BIT_63_5_THEN_INV_rg_v1_08_ETC___d118[63:0],
64'h0 } ;
assign x__h4721 = ~rg_v2 ;
assign x__h4961 = x__h4963 + y__h4964 ;
assign x__h4963 = x__h4965 + y__h4966 ;
assign x__h4965 =
{ _0x0_CONCAT_rg_v1_BITS_63_TO_32_42_43_MUL_0x0_C_ETC___d146[63:0],
64'h0 } ;
assign x__h5072 = { 32'h0, rg_v1[63:32] } ;
assign x__h5123 = { 32'h0, rg_v1[31:0] } ;
assign x__h5265 = ~prod__h5195 ;
assign x__h5295 = x__h5297 + y__h5298 ;
assign x__h5297 = x__h5299 + y__h5300 ;
assign x__h5299 =
{ _0x0_CONCAT_IF_rg_v1_BIT_63_5_THEN_INV_rg_v1_08_ETC___d167[63:0],
64'h0 } ;
assign x__h5303 =
{ 32'h0,
IF_rg_v1_BIT_63_5_THEN_INV_rg_v1_08_PLUS_1_09__ETC___d110[63:32] } ;
assign x__h5345 = ~rg_v1 ;
assign x__h5387 =
{ 32'h0,
IF_rg_v1_BIT_63_5_THEN_INV_rg_v1_08_PLUS_1_09__ETC___d110[31:0] } ;
assign y__h3857 = { 1'd0, rg_v1[63:1] } ;
assign y__h4618 =
{ 64'h0,
_0x0_CONCAT_IF_rg_v1_BIT_63_5_THEN_INV_rg_v1_08_ETC___d133[63:0] } ;
assign y__h4620 =
{ 32'h0,
_0x0_CONCAT_IF_rg_v1_BIT_63_5_THEN_INV_rg_v1_08_ETC___d129[63:0],
32'h0 } ;
assign y__h4622 =
{ 32'h0,
_0x0_CONCAT_IF_rg_v1_BIT_63_5_THEN_INV_rg_v1_08_ETC___d123[63:0],
32'h0 } ;
assign y__h4626 =
{ 32'h0,
IF_rg_v2_BIT_63_0_THEN_INV_rg_v2_13_PLUS_1_14__ETC___d115[63:32] } ;
assign y__h4793 =
{ 32'h0,
IF_rg_v2_BIT_63_0_THEN_INV_rg_v2_13_PLUS_1_14__ETC___d115[31:0] } ;
assign y__h4962 =
{ 64'h0,
_0x0_CONCAT_rg_v1_BITS_31_TO_0_49_50_MUL_0x0_CO_ETC___d161[63:0] } ;
assign y__h4964 =
{ 32'h0,
_0x0_CONCAT_rg_v1_BITS_63_TO_32_42_43_MUL_0x0_C_ETC___d157[63:0],
32'h0 } ;
assign y__h4966 =
{ 32'h0,
_0x0_CONCAT_rg_v1_BITS_31_TO_0_49_50_MUL_0x0_CO_ETC___d151[63:0],
32'h0 } ;
assign y__h5296 =
{ 64'h0,
_0x0_CONCAT_IF_rg_v1_BIT_63_5_THEN_INV_rg_v1_08_ETC___d178[63:0] } ;
assign y__h5298 =
{ 32'h0,
_0x0_CONCAT_IF_rg_v1_BIT_63_5_THEN_INV_rg_v1_08_ETC___d174[63:0],
32'h0 } ;
assign y__h5300 =
{ 32'h0,
_0x0_CONCAT_IF_rg_v1_BIT_63_5_THEN_INV_rg_v1_08_ETC___d170[63:0],
32'h0 } ;
assign y__h5388 = { 32'h0, rg_v2[63:32] } ;
assign y__h5490 = { 32'h0, rg_v2[31:0] } ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
intDiv_rg_state <= `BSV_ASSIGNMENT_DELAY 3'd0;
end
else
begin
if (cfg_verbosity$EN)
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN;
if (intDiv_rg_state$EN)
intDiv_rg_state <= `BSV_ASSIGNMENT_DELAY intDiv_rg_state$D_IN;
end
if (intDiv_rg_denom2$EN)
intDiv_rg_denom2 <= `BSV_ASSIGNMENT_DELAY intDiv_rg_denom2$D_IN;
if (intDiv_rg_denom_is_signed$EN)
intDiv_rg_denom_is_signed <= `BSV_ASSIGNMENT_DELAY
intDiv_rg_denom_is_signed$D_IN;
if (intDiv_rg_n$EN) intDiv_rg_n <= `BSV_ASSIGNMENT_DELAY intDiv_rg_n$D_IN;
if (intDiv_rg_numer_is_signed$EN)
intDiv_rg_numer_is_signed <= `BSV_ASSIGNMENT_DELAY
intDiv_rg_numer_is_signed$D_IN;
if (intDiv_rg_quo$EN)
intDiv_rg_quo <= `BSV_ASSIGNMENT_DELAY intDiv_rg_quo$D_IN;
if (intDiv_rg_quoIsNeg$EN)
intDiv_rg_quoIsNeg <= `BSV_ASSIGNMENT_DELAY intDiv_rg_quoIsNeg$D_IN;
if (intDiv_rg_remIsNeg$EN)
intDiv_rg_remIsNeg <= `BSV_ASSIGNMENT_DELAY intDiv_rg_remIsNeg$D_IN;
if (rg_f3$EN) rg_f3 <= `BSV_ASSIGNMENT_DELAY rg_f3$D_IN;
if (rg_is_OP_not_OP_32$EN)
rg_is_OP_not_OP_32 <= `BSV_ASSIGNMENT_DELAY rg_is_OP_not_OP_32$D_IN;
if (rg_result$EN) rg_result <= `BSV_ASSIGNMENT_DELAY rg_result$D_IN;
if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN;
if (rg_v1$EN) rg_v1 <= `BSV_ASSIGNMENT_DELAY rg_v1$D_IN;
if (rg_v2$EN) rg_v2 <= `BSV_ASSIGNMENT_DELAY rg_v2$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
cfg_verbosity = 4'hA;
intDiv_rg_denom2 = 64'hAAAAAAAAAAAAAAAA;
intDiv_rg_denom_is_signed = 1'h0;
intDiv_rg_n = 64'hAAAAAAAAAAAAAAAA;
intDiv_rg_numer_is_signed = 1'h0;
intDiv_rg_quo = 64'hAAAAAAAAAAAAAAAA;
intDiv_rg_quoIsNeg = 1'h0;
intDiv_rg_remIsNeg = 1'h0;
intDiv_rg_state = 3'h2;
rg_f3 = 3'h2;
rg_is_OP_not_OP_32 = 1'h0;
rg_result = 64'hAAAAAAAAAAAAAAAA;
rg_state = 2'h2;
rg_v1 = 64'hAAAAAAAAAAAAAAAA;
rg_v2 = 64'hAAAAAAAAAAAAAAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_mul && cfg_verbosity > 4'd1)
$display(" RISCV_MBox.rl_mul");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_mul && (!rg_is_OP_not_OP_32 || rg_f3 != 3'b0) &&
(!rg_is_OP_not_OP_32 || rg_f3 != 3'b001) &&
(!rg_is_OP_not_OP_32 || rg_f3 != 3'b011) &&
(!rg_is_OP_not_OP_32 || rg_f3 != 3'b010) &&
(rg_is_OP_not_OP_32 || rg_f3 != 3'b0))
begin
v__h5665 = $stime;
#0;
end
v__h5659 = v__h5665 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_mul && (!rg_is_OP_not_OP_32 || rg_f3 != 3'b0) &&
(!rg_is_OP_not_OP_32 || rg_f3 != 3'b001) &&
(!rg_is_OP_not_OP_32 || rg_f3 != 3'b011) &&
(!rg_is_OP_not_OP_32 || rg_f3 != 3'b010) &&
(rg_is_OP_not_OP_32 || rg_f3 != 3'b0))
$display("%0d: ERROR: RISCV_MBox.rl_mul: illegal f3.", v__h5659);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_mul && (!rg_is_OP_not_OP_32 || rg_f3 != 3'b0) &&
(!rg_is_OP_not_OP_32 || rg_f3 != 3'b001) &&
(!rg_is_OP_not_OP_32 || rg_f3 != 3'b011) &&
(!rg_is_OP_not_OP_32 || rg_f3 != 3'b010) &&
(rg_is_OP_not_OP_32 || rg_f3 != 3'b0))
$display(" f3 0x%0h v1 0x%0h v2 0x%0h", rg_f3, rg_v1, rg_v2);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_mul && (!rg_is_OP_not_OP_32 || rg_f3 != 3'b0) &&
(!rg_is_OP_not_OP_32 || rg_f3 != 3'b001) &&
(!rg_is_OP_not_OP_32 || rg_f3 != 3'b011) &&
(!rg_is_OP_not_OP_32 || rg_f3 != 3'b010) &&
(rg_is_OP_not_OP_32 || rg_f3 != 3'b0))
$finish(32'd1);
end
// synopsys translate_on
endmodule // mkRISCV_MBox
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FAH_2_V
`define SKY130_FD_SC_HS__FAH_2_V
/**
* fah: Full adder.
*
* Verilog wrapper for fah with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__fah.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__fah_2 (
COUT,
SUM ,
A ,
B ,
CI ,
VPWR,
VGND
);
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR;
input VGND;
sky130_fd_sc_hs__fah base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__fah_2 (
COUT,
SUM ,
A ,
B ,
CI
);
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__fah base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__FAH_2_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__BUFINV_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__BUFINV_BEHAVIORAL_PP_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__bufinv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__BUFINV_BEHAVIORAL_PP_V |
// file: dacclk_mmcm_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge LOCKED)
module dacclk_mmcm_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 7.812*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bits of the sampling counters
wire [5:1] COUNT;
// Status and control signals
wire LOCKED;
reg COUNTER_RESET = 0;
wire [5:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
real period1;
real ref_period1;
localparam ref_period1_clkin1 = (7.812*1*8.000*1000/8.000);
time prev_rise1;
real period2;
real ref_period2;
localparam ref_period2_clkin1 = (7.812*1*8*1000/8.000);
time prev_rise2;
real period3;
real ref_period3;
localparam ref_period3_clkin1 = (7.812*1*8*1000/8.000);
time prev_rise3;
real period4;
real ref_period4;
localparam ref_period4_clkin1 = (7.812*1*8*1000/8.000);
time prev_rise4;
real period5;
real ref_period5;
localparam ref_period5_clkin1 = (7.812*1*4*1000/8.000);
time prev_rise5;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
COUNTER_RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*20)
COUNTER_RESET = 0;
test_phase = "counting";
#(PER1*COUNT_PHASE);
if ((period1 -ref_period1_clkin1) <= 100 && (period1 -ref_period1_clkin1) >= -100) begin
$display("Freq of CLK_OUT[1] ( in MHz ) : %0f\n", 1000000/period1);
end else
$display("ERROR: Freq of CLK_OUT[1] is not correct");
if ((period2 -ref_period2_clkin1) <= 100 && (period2 -ref_period2_clkin1) >= -100) begin
$display("Freq of CLK_OUT[2] ( in MHz ) : %0f\n", 1000000/period2);
end else
$display("ERROR: Freq of CLK_OUT[2] is not correct");
if ((period3 -ref_period3_clkin1) <= 100 && (period3 -ref_period3_clkin1) >= -100) begin
$display("Freq of CLK_OUT[3] ( in MHz ) : %0f\n", 1000000/period3);
end else
$display("ERROR: Freq of CLK_OUT[3] is not correct");
if ((period4 -ref_period4_clkin1) <= 100 && (period4 -ref_period4_clkin1) >= -100) begin
$display("Freq of CLK_OUT[4] ( in MHz ) : %0f\n", 1000000/period4);
end else
$display("ERROR: Freq of CLK_OUT[4] is not correct");
if ((period5 -ref_period5_clkin1) <= 100 && (period5 -ref_period5_clkin1) >= -100) begin
$display("Freq of CLK_OUT[5] ( in MHz ) : %0f\n", 1000000/period5);
end else
$display("ERROR: Freq of CLK_OUT[5] is not correct");
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
dacclk_mmcm_exdes
#(
.TCQ (TCQ)
) dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.LOCKED (LOCKED));
// Freq Check
initial
prev_rise1 = 0;
always @(posedge CLK_OUT[1])
begin
if (prev_rise1 != 0)
period1 = $time - prev_rise1;
prev_rise1 = $time;
end
initial
prev_rise2 = 0;
always @(posedge CLK_OUT[2])
begin
if (prev_rise2 != 0)
period2 = $time - prev_rise2;
prev_rise2 = $time;
end
initial
prev_rise3 = 0;
always @(posedge CLK_OUT[3])
begin
if (prev_rise3 != 0)
period3 = $time - prev_rise3;
prev_rise3 = $time;
end
initial
prev_rise4 = 0;
always @(posedge CLK_OUT[4])
begin
if (prev_rise4 != 0)
period4 = $time - prev_rise4;
prev_rise4 = $time;
end
initial
prev_rise5 = 0;
always @(posedge CLK_OUT[5])
begin
if (prev_rise5 != 0)
period5 = $time - prev_rise5;
prev_rise5 = $time;
end
endmodule
|
`timescale 1ns/1ps
module tb_cocotb (
//Virtual Host Interface Signals
input clk,
input sata_clk,
input rst,
output master_ready,
input in_ready,
input [31:0] in_command,
input [31:0] in_address,
input [31:0] in_data,
input [27:0] in_data_count,
input out_ready,
output out_en,
output [31:0] out_status,
output [31:0] out_address,
output [31:0] out_data,
output [27:0] out_data_count,
input [31:0] test_id,
input ih_reset,
output device_interrupt
);
//Parameters
//Registers/Wires
reg r_rst;
reg r_in_ready;
reg [31:0] r_in_command;
reg [31:0] r_in_address;
reg [31:0] r_in_data;
reg [27:0] r_in_data_count;
reg r_out_ready;
reg r_ih_reset;
//There is a bug in COCOTB when stiumlating a signal, sometimes it can be corrupted if not registered
always @ (*) r_rst = rst;
always @ (*) r_in_ready = in_ready;
always @ (*) r_in_command = in_command;
always @ (*) r_in_address = in_address;
always @ (*) r_in_data = in_data;
always @ (*) r_in_data_count = in_data_count;
always @ (*) r_out_ready = out_ready;
always @ (*) r_ih_reset = ih_reset;
//wishbone signals
wire w_wbp_we;
wire w_wbp_cyc;
wire w_wbp_stb;
wire [3:0] w_wbp_sel;
wire [31:0] w_wbp_adr;
wire [31:0] w_wbp_dat_o;
wire [31:0] w_wbp_dat_i;
wire w_wbp_ack;
wire w_wbp_int;
//Wishbone Slave 0 (SDB) signals
wire w_wbs0_we;
wire w_wbs0_cyc;
wire [31:0] w_wbs0_dat_o;
wire w_wbs0_stb;
wire [3:0] w_wbs0_sel;
wire w_wbs0_ack;
wire [31:0] w_wbs0_dat_i;
wire [31:0] w_wbs0_adr;
wire w_wbs0_int;
//mem slave 0
wire w_sm0_i_wbs_we;
wire w_sm0_i_wbs_cyc;
wire [31:0] w_sm0_i_wbs_dat;
wire [31:0] w_sm0_o_wbs_dat;
wire [31:0] w_sm0_i_wbs_adr;
wire w_sm0_i_wbs_stb;
wire [3:0] w_sm0_i_wbs_sel;
wire w_sm0_o_wbs_ack;
wire w_sm0_o_wbs_int;
//wishbone slave 1 (Unit Under Test) signals
wire w_wbs1_we;
wire w_wbs1_cyc;
wire w_wbs1_stb;
wire [3:0] w_wbs1_sel;
wire w_wbs1_ack;
wire [31:0] w_wbs1_dat_i;
wire [31:0] w_wbs1_dat_o;
wire [31:0] w_wbs1_adr;
wire w_wbs1_int;
//Memory Interface
wire w_mem_we_o;
wire w_mem_cyc_o;
wire w_mem_stb_o;
wire [3:0] w_mem_sel_o;
wire [31:0] w_mem_adr_o;
wire [31:0] w_mem_dat_i;
wire [31:0] w_mem_dat_o;
wire w_mem_ack_i;
wire w_mem_int_i;
wire w_arb0_i_wbs_stb;
wire w_arb0_i_wbs_cyc;
wire w_arb0_i_wbs_we;
wire [3:0] w_arb0_i_wbs_sel;
wire [31:0] w_arb0_i_wbs_dat;
wire [31:0] w_arb0_o_wbs_dat;
wire [31:0] w_arb0_i_wbs_adr;
wire w_arb0_o_wbs_ack;
wire w_arb0_o_wbs_int;
wire mem_o_we;
wire mem_o_stb;
wire mem_o_cyc;
wire [3:0] mem_o_sel;
wire [31:0] mem_o_adr;
wire [31:0] mem_o_dat;
wire [31:0] mem_i_dat;
wire mem_i_ack;
wire mem_i_int;
//Submodules
wishbone_master wm (
.clk (clk ),
.rst (r_rst ),
.i_ih_rst (r_ih_reset ),
.i_ready (r_in_ready ),
.i_command (r_in_command ),
.i_address (r_in_address ),
.i_data (r_in_data ),
.i_data_count (r_in_data_count),
.i_out_ready (r_out_ready ),
.o_en (out_en ),
.o_status (out_status ),
.o_address (out_address ),
.o_data (out_data ),
.o_data_count (out_data_count ),
.o_master_ready (master_ready ),
.o_per_we (w_wbp_we ),
.o_per_adr (w_wbp_adr ),
.o_per_dat (w_wbp_dat_i ),
.i_per_dat (w_wbp_dat_o ),
.o_per_stb (w_wbp_stb ),
.o_per_cyc (w_wbp_cyc ),
.o_per_msk (w_wbp_msk ),
.o_per_sel (w_wbp_sel ),
.i_per_ack (w_wbp_ack ),
.i_per_int (w_wbp_int ),
//memory interconnect signals
.o_mem_we (w_mem_we_o ),
.o_mem_adr (w_mem_adr_o ),
.o_mem_dat (w_mem_dat_o ),
.i_mem_dat (w_mem_dat_i ),
.o_mem_stb (w_mem_stb_o ),
.o_mem_cyc (w_mem_cyc_o ),
.o_mem_sel (w_mem_sel_o ),
.i_mem_ack (w_mem_ack_i ),
.i_mem_int (w_mem_int_i )
);
//slave 1
wb_tx1_pcie s1 (
.clk (clk ),
.rst (r_rst ),
.i_wbs_we (w_wbs1_we ),
.i_wbs_sel (4'b1111 ),
.i_wbs_cyc (w_wbs1_cyc ),
.i_wbs_dat (w_wbs1_dat_i ),
.i_wbs_stb (w_wbs1_stb ),
.o_wbs_ack (w_wbs1_ack ),
.o_wbs_dat (w_wbs1_dat_o ),
.i_wbs_adr (w_wbs1_adr ),
.o_wbs_int (w_wbs1_int )
);
wishbone_interconnect wi (
.clk (clk ),
.rst (r_rst ),
.i_m_we (w_wbp_we ),
.i_m_cyc (w_wbp_cyc ),
.i_m_stb (w_wbp_stb ),
.o_m_ack (w_wbp_ack ),
.i_m_dat (w_wbp_dat_i ),
.o_m_dat (w_wbp_dat_o ),
.i_m_adr (w_wbp_adr ),
.o_m_int (w_wbp_int ),
.o_s0_we (w_wbs0_we ),
.o_s0_cyc (w_wbs0_cyc ),
.o_s0_stb (w_wbs0_stb ),
.i_s0_ack (w_wbs0_ack ),
.o_s0_dat (w_wbs0_dat_i ),
.i_s0_dat (w_wbs0_dat_o ),
.o_s0_adr (w_wbs0_adr ),
.i_s0_int (w_wbs0_int ),
.o_s1_we (w_wbs1_we ),
.o_s1_cyc (w_wbs1_cyc ),
.o_s1_stb (w_wbs1_stb ),
.i_s1_ack (w_wbs1_ack ),
.o_s1_dat (w_wbs1_dat_i ),
.i_s1_dat (w_wbs1_dat_o ),
.o_s1_adr (w_wbs1_adr ),
.i_s1_int (w_wbs1_int )
);
wishbone_mem_interconnect wmi (
.clk (clk ),
.rst (r_rst ),
//master
.i_m_we (w_mem_we_o ),
.i_m_cyc (w_mem_cyc_o ),
.i_m_stb (w_mem_stb_o ),
.i_m_sel (w_mem_sel_o ),
.o_m_ack (w_mem_ack_i ),
.i_m_dat (w_mem_dat_o ),
.o_m_dat (w_mem_dat_i ),
.i_m_adr (w_mem_adr_o ),
.o_m_int (w_mem_int_i ),
//slave 0
.o_s0_we (w_sm0_i_wbs_we ),
.o_s0_cyc (w_sm0_i_wbs_cyc ),
.o_s0_stb (w_sm0_i_wbs_stb ),
.o_s0_sel (w_sm0_i_wbs_sel ),
.i_s0_ack (w_sm0_o_wbs_ack ),
.o_s0_dat (w_sm0_i_wbs_dat ),
.i_s0_dat (w_sm0_o_wbs_dat ),
.o_s0_adr (w_sm0_i_wbs_adr ),
.i_s0_int (w_sm0_o_wbs_int )
);
arbiter_2_masters arb0 (
.clk (clk ),
.rst (r_rst ),
//masters
.i_m1_we (mem_o_we ),
.i_m1_stb (mem_o_stb ),
.i_m1_cyc (mem_o_cyc ),
.i_m1_sel (mem_o_sel ),
.i_m1_dat (mem_o_dat ),
.i_m1_adr (mem_o_adr ),
.o_m1_dat (mem_i_dat ),
.o_m1_ack (mem_i_ack ),
.o_m1_int (mem_i_int ),
.i_m0_we (w_sm0_i_wbs_we ),
.i_m0_stb (w_sm0_i_wbs_stb ),
.i_m0_cyc (w_sm0_i_wbs_cyc ),
.i_m0_sel (w_sm0_i_wbs_sel ),
.i_m0_dat (w_sm0_i_wbs_dat ),
.i_m0_adr (w_sm0_i_wbs_adr ),
.o_m0_dat (w_sm0_o_wbs_dat ),
.o_m0_ack (w_sm0_o_wbs_ack ),
.o_m0_int (w_sm0_o_wbs_int ),
//slave
.o_s_we (w_arb0_i_wbs_we ),
.o_s_stb (w_arb0_i_wbs_stb ),
.o_s_cyc (w_arb0_i_wbs_cyc ),
.o_s_sel (w_arb0_i_wbs_sel ),
.o_s_dat (w_arb0_i_wbs_dat ),
.o_s_adr (w_arb0_i_wbs_adr ),
.i_s_dat (w_arb0_o_wbs_dat ),
.i_s_ack (w_arb0_o_wbs_ack ),
.i_s_int (w_arb0_o_wbs_int )
);
wb_bram #(
.DATA_WIDTH (32 ),
.ADDR_WIDTH (10 )
)bram(
.clk (clk ),
.rst (r_rst ),
.i_wbs_we (w_arb0_i_wbs_we ),
.i_wbs_sel (w_arb0_i_wbs_sel ),
.i_wbs_cyc (w_arb0_i_wbs_cyc ),
.i_wbs_dat (w_arb0_i_wbs_dat ),
.i_wbs_stb (w_arb0_i_wbs_stb ),
.i_wbs_adr (w_arb0_i_wbs_adr ),
.o_wbs_dat (w_arb0_o_wbs_dat ),
.o_wbs_ack (w_arb0_o_wbs_ack ),
.o_wbs_int (w_arb0_o_wbs_int )
);
//Disable Slave 0
assign w_wbs0_int = 0;
assign w_wbs0_ack = 0;
assign w_wbs0_dat_o = 0;
assign device_interrupt = w_wbp_int;
/*
READ ME IF YOUR MODULE WILL INTERFACE WITH MEMORY
If you want to talk to memory over the wishbone bus directly, your module must control the following signals:
(Your module will be a wishbone master)
mem_o_we
mem_o_stb
mem_o_cyc
mem_o_sel
mem_o_adr
mem_o_dat
mem_i_dat
mem_i_ack
mem_i_int
Currently this bus is disabled so if will not interface with memory these signals can be left
For a reference check out wb_sd_host
*/
assign mem_o_we = 0;
assign mem_o_stb = 0;
assign mem_o_cyc = 0;
assign mem_o_sel = 0;
assign mem_o_adr = 0;
assign mem_o_dat = 0;
//Submodules
//Asynchronous Logic
//Synchronous Logic
//Simulation Control
initial begin
$dumpfile ("design.vcd");
$dumpvars(0, tb_cocotb);
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV3SD2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__CLKDLYINV3SD2_FUNCTIONAL_PP_V
/**
* clkdlyinv3sd2: Clock Delay Inverter 3-stage 0.25um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__clkdlyinv3sd2 (
Y ,
A ,
VPWR,
VGND
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
// Local signals
wire not0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV3SD2_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FA_SYMBOL_V
`define SKY130_FD_SC_LS__FA_SYMBOL_V
/**
* fa: Full adder.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__fa (
//# {{data|Data Signals}}
input A ,
input B ,
input CIN ,
output COUT,
output SUM
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__FA_SYMBOL_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
ddr_addr,
ddr_ba,
ddr_cas_n,
ddr_ck_n,
ddr_ck_p,
ddr_cke,
ddr_cs_n,
ddr_dm,
ddr_dq,
ddr_dqs_n,
ddr_dqs_p,
ddr_odt,
ddr_ras_n,
ddr_reset_n,
ddr_we_n,
fixed_io_ddr_vrn,
fixed_io_ddr_vrp,
fixed_io_mio,
fixed_io_ps_clk,
fixed_io_ps_porb,
fixed_io_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
spdif,
iic_scl,
iic_sda,
rx_clk_in_p,
rx_clk_in_n,
rx_frame_in_p,
rx_frame_in_n,
rx_data_in_p,
rx_data_in_n,
tx_clk_out_p,
tx_clk_out_n,
tx_frame_out_p,
tx_frame_out_n,
tx_data_out_p,
tx_data_out_n,
gpio_txnrx,
gpio_enable,
gpio_resetb,
gpio_sync,
gpio_en_agc,
gpio_ctl,
gpio_status,
spi_csn,
spi_clk,
spi_mosi,
spi_miso);
inout [14:0] ddr_addr;
inout [ 2:0] ddr_ba;
inout ddr_cas_n;
inout ddr_ck_n;
inout ddr_ck_p;
inout ddr_cke;
inout ddr_cs_n;
inout [ 3:0] ddr_dm;
inout [31:0] ddr_dq;
inout [ 3:0] ddr_dqs_n;
inout [ 3:0] ddr_dqs_p;
inout ddr_odt;
inout ddr_ras_n;
inout ddr_reset_n;
inout ddr_we_n;
inout fixed_io_ddr_vrn;
inout fixed_io_ddr_vrp;
inout [53:0] fixed_io_mio;
inout fixed_io_ps_clk;
inout fixed_io_ps_porb;
inout fixed_io_ps_srstb;
inout [14:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [23:0] hdmi_data;
output spdif;
inout iic_scl;
inout iic_sda;
input rx_clk_in_p;
input rx_clk_in_n;
input rx_frame_in_p;
input rx_frame_in_n;
input [ 5:0] rx_data_in_p;
input [ 5:0] rx_data_in_n;
output tx_clk_out_p;
output tx_clk_out_n;
output tx_frame_out_p;
output tx_frame_out_n;
output [ 5:0] tx_data_out_p;
output [ 5:0] tx_data_out_n;
inout gpio_txnrx;
inout gpio_enable;
inout gpio_resetb;
inout gpio_sync;
inout gpio_en_agc;
inout [ 3:0] gpio_ctl;
inout [ 7:0] gpio_status;
output spi_csn;
output spi_clk;
output spi_mosi;
input spi_miso;
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire clk;
wire dma_dac_dunf;
wire core_dac_dunf;
wire [63:0] dma_dac_ddata;
wire [63:0] core_dac_ddata;
wire dma_dac_en;
wire core_dac_en;
wire dma_dac_dvalid;
wire core_dac_dvalid;
wire dma_adc_ovf;
wire core_adc_ovf;
wire [63:0] dma_adc_ddata;
wire [63:0] core_adc_ddata;
wire dma_adc_dwr;
wire core_adc_dwr;
wire dma_adc_dsync;
wire core_adc_dsync;
wire [31:0] adc_gpio_input;
wire [31:0] adc_gpio_output;
wire [31:0] dac_gpio_input;
wire [31:0] dac_gpio_output;
wire tdd_sync_t;
wire tdd_sync_o;
wire tdd_sync_i;
// instantiations
ad_iobuf #(.DATA_WIDTH(17)) i_iobuf (
.dio_t ({gpio_t[50:49], gpio_t[46:32]}),
.dio_i ({gpio_o[50:49], gpio_o[46:32]}),
.dio_o ({gpio_i[50:49], gpio_i[46:32]}),
.dio_p ({ gpio_muxout_tx, // 50:50
gpio_muxout_rx, // 49:49
gpio_resetb, // 46:46
gpio_sync, // 45:45
gpio_en_agc, // 44:44
gpio_ctl, // 43:40
gpio_status})); // 39:32
ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd (
.dio_t (gpio_t[14:0]),
.dio_i (gpio_o[14:0]),
.dio_o (gpio_i[14:0]),
.dio_p (gpio_bd));
ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_tdd_sync (
.dio_t (tdd_sync_t),
.dio_i (tdd_sync_o),
.dio_o (tdd_sync_i),
.dio_p (tdd_sync));
// prcfg instance
prcfg i_prcfg (
.clk(clk),
.adc_gpio_input(adc_gpio_input),
.adc_gpio_output(adc_gpio_output),
.dac_gpio_input(dac_gpio_input),
.dac_gpio_output(dac_gpio_output),
.dma_dac_en(dma_dac_en),
.dma_dac_dunf(dma_dac_dunf),
.dma_dac_ddata(dma_dac_ddata),
.dma_dac_dvalid(dma_dac_dvalid),
.core_dac_en(core_dac_en),
.core_dac_dunf(core_dac_dunf),
.core_dac_ddata(core_dac_ddata),
.core_dac_dvalid(core_dac_dvalid),
.core_adc_dwr(core_adc_dwr),
.core_adc_dsync(core_adc_dsync),
.core_adc_ddata(core_adc_ddata),
.core_adc_ovf(core_adc_ovf),
.dma_adc_dwr(dma_adc_dwr),
.dma_adc_dsync(dma_adc_dsync),
.dma_adc_ddata(dma_adc_ddata),
.dma_adc_ovf(dma_adc_ovf));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.enable (enable),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.ps_intr_11 (1'b0),
.rx_clk_in_n (rx_clk_in_n),
.rx_clk_in_p (rx_clk_in_p),
.rx_data_in_n (rx_data_in_n),
.rx_data_in_p (rx_data_in_p),
.rx_frame_in_n (rx_frame_in_n),
.rx_frame_in_p (rx_frame_in_p),
.spdif (spdif),
.spi0_clk_i (1'b0),
.spi0_clk_o (spi_clk),
.spi0_csn_0_o (spi_csn),
.spi0_csn_1_o (),
.spi0_csn_2_o (),
.spi0_csn_i (1'b1),
.spi0_sdi_i (spi_miso),
.spi0_sdo_i (1'b0),
.spi0_sdo_o (spi_mosi),
.tx_clk_out_n (tx_clk_out_n),
.tx_clk_out_p (tx_clk_out_p),
.tx_data_out_n (tx_data_out_n),
.tx_data_out_p (tx_data_out_p),
.tx_frame_out_n (tx_frame_out_n),
.tx_frame_out_p (tx_frame_out_p),
// pr related ports
.clk(clk),
.dma_dac_en(dma_dac_en),
.dma_dac_dunf(dma_dac_dunf),
.dma_dac_ddata(dma_dac_ddata),
.dma_dac_dvalid(dma_dac_dvalid),
.core_dac_en(core_dac_en),
.core_dac_dunf(core_dac_dunf),
.core_dac_ddata(core_dac_ddata),
.core_dac_dvalid(core_dac_dvalid),
.core_adc_dwr(core_adc_dwr),
.core_adc_dsync(core_adc_dsync),
.core_adc_ddata(core_adc_ddata),
.core_adc_ovf(core_adc_ovf),
.dma_adc_dwr(dma_adc_dwr),
.dma_adc_dsync(dma_adc_dsync),
.dma_adc_ddata(dma_adc_ddata),
.dma_adc_ovf(dma_adc_ovf),
.up_dac_gpio_in(dac_gpio_output),
.up_adc_gpio_in(adc_gpio_output),
.up_dac_gpio_out(dac_gpio_input),
.up_adc_gpio_out(adc_gpio_input)
);
endmodule
// ***************************************************************************
// ***************************************************************************
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_zero_one_hot (clock, reset, enable, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 32;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input [width-1:0] test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_ZERO_ONE_HOT";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/ovl_zero_one_hot_logic.v"
`endif
`ifdef OVL_SVA
`include "./sva05/ovl_zero_one_hot_logic.sv"
`endif
`ifdef OVL_PSL
`include "./psl05/assert_zero_one_hot_psl_logic.v"
`else
assign fire = {fire_cover, fire_xcheck, fire_2state};
`endmodule // ovl_zero_one_hot
`endif
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__XOR2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__XOR2_BEHAVIORAL_PP_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__xor2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xor0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X , B, A );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xor0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__XOR2_BEHAVIORAL_PP_V |
/*
* PicoSoC - A simple example SoC using PicoRV32
*
* This is a modified PicoSoC example which has removed the requirement
* for an external SPI flash. The PicoRV32 program is stored in ROM implemented
* as a number of case statements. The ROM file is generated using an external
* script.
*
*
* Copyright (C) 2017 Clifford Wolf <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
`ifndef PICORV32_REGS
`ifdef PICORV32_V
`error "picosoc.v must be read before picorv32.v!"
`endif
`define PICORV32_REGS picosoc_regs
`endif
module picosoc_noflash (
input clk,
input resetn,
output iomem_valid,
input iomem_ready,
output [ 3:0] iomem_wstrb,
output [31:0] iomem_addr,
output [31:0] iomem_wdata,
input [31:0] iomem_rdata,
input irq_5,
input irq_6,
input irq_7,
output ser_tx,
input ser_rx
);
parameter integer MEM_WORDS = 256;
parameter [31:0] STACKADDR = (4*MEM_WORDS); // end of memory
parameter [31:0] PROGADDR_RESET = 32'h 0010_0000; // 1 MB into flash
reg [31:0] irq;
wire irq_stall = 0;
wire irq_uart = 0;
always @* begin
irq = 0;
irq[3] = irq_stall;
irq[4] = irq_uart;
irq[5] = irq_5;
irq[6] = irq_6;
irq[7] = irq_7;
end
wire mem_valid;
wire mem_instr;
wire mem_ready;
wire [31:0] mem_addr;
wire [31:0] mem_wdata;
wire [3:0] mem_wstrb;
wire [31:0] mem_rdata;
wire progmem_ready;
wire [31:0] progmem_rdata;
reg ram_ready;
wire [31:0] ram_rdata;
assign iomem_valid = mem_valid && (mem_addr[31:24] > 8'h 01);
assign iomem_wstrb = mem_wstrb;
assign iomem_addr = mem_addr;
assign iomem_wdata = mem_wdata;
wire spimemio_cfgreg_sel = mem_valid && (mem_addr == 32'h 0200_0000);
wire simpleuart_reg_div_sel = mem_valid && (mem_addr == 32'h 0200_0004);
wire [31:0] simpleuart_reg_div_do;
wire simpleuart_reg_dat_sel = mem_valid && (mem_addr == 32'h 0200_0008);
wire [31:0] simpleuart_reg_dat_do;
wire simpleuart_reg_dat_wait;
assign mem_ready =
(iomem_valid && iomem_ready) || progmem_ready || ram_ready || spimemio_cfgreg_sel ||
simpleuart_reg_div_sel || (simpleuart_reg_dat_sel && !simpleuart_reg_dat_wait);
assign mem_rdata =
(iomem_valid && iomem_ready) ? iomem_rdata :
progmem_ready ? progmem_rdata :
ram_ready ? ram_rdata :
spimemio_cfgreg_sel ? 32'h0000_0000 : // Mockup, will always read 0
simpleuart_reg_div_sel ? simpleuart_reg_div_do :
simpleuart_reg_dat_sel ? simpleuart_reg_dat_do : 32'h 0000_0000;
`ifdef SIMULATION
wire trace_valid;
wire [35:0] trace_data;
integer trace_file;
`endif
picorv32 #(
.STACKADDR(STACKADDR),
.PROGADDR_RESET(PROGADDR_RESET),
.PROGADDR_IRQ(32'h 0000_0000),
.BARREL_SHIFTER(1),
.COMPRESSED_ISA(1),
.ENABLE_MUL(1),
.ENABLE_DIV(1),
.ENABLE_IRQ(1),
`ifdef SIMULATION
.ENABLE_IRQ_QREGS(0),
.ENABLE_TRACE(1)
`else
.ENABLE_IRQ_QREGS(0)
`endif
) cpu (
.clk (clk ),
.resetn (resetn ),
.mem_valid (mem_valid ),
.mem_instr (mem_instr ),
.mem_ready (mem_ready ),
.mem_addr (mem_addr ),
.mem_wdata (mem_wdata ),
.mem_wstrb (mem_wstrb ),
.mem_rdata (mem_rdata ),
`ifdef SIMULATION
.irq (irq ),
.trace_valid (trace_valid),
.trace_data (trace_data )
`else
.irq (irq )
`endif
);
// This it the program ROM memory for the PicoRV32
progmem progmem (
.clk (clk),
.rstn (resetn),
.valid (mem_valid && mem_addr >= 4*MEM_WORDS && mem_addr < 32'h 0200_0000),
.ready (progmem_ready),
.addr (mem_addr),
.rdata (progmem_rdata)
);
simpleuart simpleuart (
.clk (clk ),
.resetn (resetn ),
.ser_tx (ser_tx ),
.ser_rx (ser_rx ),
.reg_div_we (simpleuart_reg_div_sel ? mem_wstrb : 4'b 0000),
.reg_div_di (mem_wdata),
.reg_div_do (simpleuart_reg_div_do),
.reg_dat_we (simpleuart_reg_dat_sel ? mem_wstrb[0] : 1'b 0),
.reg_dat_re (simpleuart_reg_dat_sel && !mem_wstrb),
.reg_dat_di (mem_wdata),
.reg_dat_do (simpleuart_reg_dat_do),
.reg_dat_wait(simpleuart_reg_dat_wait)
);
always @(posedge clk)
ram_ready <= mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS;
picosoc_mem #(.WORDS(MEM_WORDS)) memory (
.clk(clk),
.wen((mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS) ? mem_wstrb : 4'b0),
.addr(mem_addr[23:2]),
.wdata(mem_wdata),
.rdata(ram_rdata)
);
// Simulation debug
`ifdef SIMULATION
always @(posedge clk)
if (resetn) begin
if ( mem_instr && mem_valid && mem_ready)
$display("Inst rd: [0x%08X] = 0x%08X", mem_addr, mem_rdata);
if (!mem_instr && mem_valid && mem_ready)
$display("Data rd: [0x%08X] = 0x%08X", mem_addr, mem_rdata);
end
// Trace
initial begin
trace_file = $fopen("testbench.trace", "w");
repeat (10) @(posedge clk);
while(1) begin
@(posedge clk)
if (resetn && trace_valid)
$fwrite(trace_file, "%x\n", trace_data);
$fflush(trace_file);
//$display("Trace : %09X", trace_data);
end
end
`endif // SIMULATION
endmodule
// Implementation note:
// Replace the following two modules with wrappers for your SRAM cells.
module picosoc_regs (
input clk, wen,
input [5:0] waddr,
input [5:0] raddr1,
input [5:0] raddr2,
input [31:0] wdata,
output [31:0] rdata1,
output [31:0] rdata2
);
(* ram_style = "distributed" *) reg [31:0] regs [0:31];
always @(posedge clk)
if (wen) regs[waddr[4:0]] <= wdata;
assign rdata1 = regs[raddr1[4:0]];
assign rdata2 = regs[raddr2[4:0]];
endmodule
module picosoc_mem #(
parameter integer WORDS = 256
) (
input clk,
input [3:0] wen,
input [21:0] addr,
input [31:0] wdata,
output reg [31:0] rdata
);
(* ram_style = "distributed" *) reg [31:0] mem [0:WORDS-1];
always @(posedge clk) begin
rdata <= mem[addr];
if (wen[0]) mem[addr][ 7: 0] <= wdata[ 7: 0];
if (wen[1]) mem[addr][15: 8] <= wdata[15: 8];
if (wen[2]) mem[addr][23:16] <= wdata[23:16];
if (wen[3]) mem[addr][31:24] <= wdata[31:24];
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2015(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module up_tdd_cntrl (
clk,
rst,
//rf tdd interface control
tdd_enable,
tdd_secondary,
tdd_rx_only,
tdd_tx_only,
tdd_gated_rx_dmapath,
tdd_gated_tx_dmapath,
tdd_burst_count,
tdd_counter_init,
tdd_frame_length,
tdd_terminal_type,
tdd_vco_rx_on_1,
tdd_vco_rx_off_1,
tdd_vco_tx_on_1,
tdd_vco_tx_off_1,
tdd_rx_on_1,
tdd_rx_off_1,
tdd_tx_on_1,
tdd_tx_off_1,
tdd_tx_dp_on_1,
tdd_tx_dp_off_1,
tdd_vco_rx_on_2,
tdd_vco_rx_off_2,
tdd_vco_tx_on_2,
tdd_vco_tx_off_2,
tdd_rx_on_2,
tdd_rx_off_2,
tdd_tx_on_2,
tdd_tx_off_2,
tdd_tx_dp_on_2,
tdd_tx_dp_off_2,
tdd_status,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
localparam PCORE_VERSION = 32'h00010001;
parameter PCORE_ID = 0;
input clk;
input rst;
output tdd_enable;
output tdd_secondary;
output tdd_rx_only;
output tdd_tx_only;
output tdd_gated_rx_dmapath;
output tdd_gated_tx_dmapath;
output [ 7:0] tdd_burst_count;
output [23:0] tdd_counter_init;
output [23:0] tdd_frame_length;
output tdd_terminal_type;
output [23:0] tdd_vco_rx_on_1;
output [23:0] tdd_vco_rx_off_1;
output [23:0] tdd_vco_tx_on_1;
output [23:0] tdd_vco_tx_off_1;
output [23:0] tdd_rx_on_1;
output [23:0] tdd_rx_off_1;
output [23:0] tdd_tx_on_1;
output [23:0] tdd_tx_off_1;
output [23:0] tdd_tx_dp_on_1;
output [23:0] tdd_tx_dp_off_1;
output [23:0] tdd_vco_rx_on_2;
output [23:0] tdd_vco_rx_off_2;
output [23:0] tdd_vco_tx_on_2;
output [23:0] tdd_vco_tx_off_2;
output [23:0] tdd_rx_on_2;
output [23:0] tdd_rx_off_2;
output [23:0] tdd_tx_on_2;
output [23:0] tdd_tx_off_2;
output [23:0] tdd_tx_dp_on_2;
output [23:0] tdd_tx_dp_off_2;
input [ 7:0] tdd_status;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg up_wack = 1'h0;
reg [31:0] up_scratch = 32'h0;
reg up_rack = 1'h0;
reg [31:0] up_rdata = 32'h0;
reg up_tdd_enable = 1'h0;
reg up_tdd_secondary = 1'h0;
reg up_tdd_rx_only = 1'h0;
reg up_tdd_tx_only = 1'h0;
reg up_tdd_gated_tx_dmapath = 1'h0;
reg up_tdd_gated_rx_dmapath = 1'h0;
reg up_tdd_terminal_type = 1'h0;
reg [ 7:0] up_tdd_burst_count = 8'h0;
reg [23:0] up_tdd_counter_init = 24'h0;
reg [23:0] up_tdd_frame_length = 24'h0;
reg [23:0] up_tdd_vco_rx_on_1 = 24'h0;
reg [23:0] up_tdd_vco_rx_off_1 = 24'h0;
reg [23:0] up_tdd_vco_tx_on_1 = 24'h0;
reg [23:0] up_tdd_vco_tx_off_1 = 24'h0;
reg [23:0] up_tdd_rx_on_1 = 24'h0;
reg [23:0] up_tdd_rx_off_1 = 24'h0;
reg [23:0] up_tdd_tx_on_1 = 24'h0;
reg [23:0] up_tdd_tx_off_1 = 24'h0;
reg [23:0] up_tdd_tx_dp_on_1 = 24'h0;
reg [23:0] up_tdd_tx_dp_off_1 = 24'h0;
reg [23:0] up_tdd_vco_rx_on_2 = 24'h0;
reg [23:0] up_tdd_vco_rx_off_2 = 24'h0;
reg [23:0] up_tdd_vco_tx_on_2 = 24'h0;
reg [23:0] up_tdd_vco_tx_off_2 = 24'h0;
reg [23:0] up_tdd_rx_on_2 = 24'h0;
reg [23:0] up_tdd_rx_off_2 = 24'h0;
reg [23:0] up_tdd_tx_on_2 = 24'h0;
reg [23:0] up_tdd_tx_off_2 = 24'h0;
reg [23:0] up_tdd_tx_dp_on_2 = 24'h0;
reg [23:0] up_tdd_tx_dp_off_2 = 24'h0;
// internal signals
wire up_wreq_s;
wire up_rreq_s;
wire [ 7:0] up_tdd_status_s;
// decode block select
assign up_wreq_s = (up_waddr[13:8] == 6'h20) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:8] == 6'h20) ? up_rreq : 1'b0;
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 1'h0;
up_scratch <= 32'h0;
up_tdd_enable <= 1'h0;
up_tdd_secondary <= 1'h0;
up_tdd_rx_only <= 1'h0;
up_tdd_tx_only <= 1'h0;
up_tdd_gated_tx_dmapath <= 1'h0;
up_tdd_gated_rx_dmapath <= 1'h0;
up_tdd_terminal_type <= 1'h0;
up_tdd_counter_init <= 24'h0;
up_tdd_frame_length <= 24'h0;
up_tdd_burst_count <= 8'h0;
up_tdd_vco_rx_on_1 <= 24'h0;
up_tdd_vco_rx_off_1 <= 24'h0;
up_tdd_vco_tx_on_1 <= 24'h0;
up_tdd_vco_tx_off_1 <= 24'h0;
up_tdd_rx_on_1 <= 24'h0;
up_tdd_rx_off_1 <= 24'h0;
up_tdd_tx_on_1 <= 24'h0;
up_tdd_tx_off_1 <= 24'h0;
up_tdd_tx_dp_on_1 <= 24'h0;
up_tdd_vco_rx_on_2 <= 24'h0;
up_tdd_vco_rx_off_2 <= 24'h0;
up_tdd_vco_tx_on_2 <= 24'h0;
up_tdd_vco_tx_off_2 <= 24'h0;
up_tdd_rx_on_2 <= 24'h0;
up_tdd_rx_off_2 <= 24'h0;
up_tdd_tx_on_2 <= 24'h0;
up_tdd_tx_off_2 <= 24'h0;
up_tdd_tx_dp_on_2 <= 24'h0;
end else begin
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
up_tdd_enable <= up_wdata[0];
up_tdd_secondary <= up_wdata[1];
up_tdd_rx_only <= up_wdata[2];
up_tdd_tx_only <= up_wdata[3];
up_tdd_gated_rx_dmapath <= up_wdata[4];
up_tdd_gated_tx_dmapath <= up_wdata[5];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
up_tdd_burst_count <= up_wdata[7:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h12)) begin
up_tdd_counter_init <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h13)) begin
up_tdd_frame_length <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin
up_tdd_terminal_type <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h20)) begin
up_tdd_vco_rx_on_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h23)) begin
up_tdd_vco_rx_off_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
up_tdd_vco_tx_on_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h23)) begin
up_tdd_vco_tx_off_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h24)) begin
up_tdd_rx_on_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h25)) begin
up_tdd_rx_off_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h26)) begin
up_tdd_tx_on_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h27)) begin
up_tdd_tx_off_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h28)) begin
up_tdd_tx_dp_on_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h29)) begin
up_tdd_tx_dp_off_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h20)) begin
up_tdd_vco_rx_on_2 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h21)) begin
up_tdd_vco_rx_off_2 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
up_tdd_vco_tx_on_2 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h23)) begin
up_tdd_vco_tx_off_2 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h32)) begin
up_tdd_rx_on_2 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h33)) begin
up_tdd_rx_off_2 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h34)) begin
up_tdd_tx_on_2 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h35)) begin
up_tdd_tx_off_2 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h36)) begin
up_tdd_tx_dp_on_2 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h37)) begin
up_tdd_tx_dp_off_2 <= up_wdata[23:0];
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rack <= 1'b0;
up_rdata <= 1'b0;
end else begin
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr[7:0])
8'h10: up_rdata <= {28'h0, up_tdd_gated_tx_dmapath,
up_tdd_gated_rx_dmapath,
up_tdd_tx_only,
up_tdd_rx_only,
up_tdd_secondary,
up_tdd_enable};
8'h11: up_rdata <= {24'h0, up_tdd_burst_count};
8'h12: up_rdata <= { 8'h0, up_tdd_counter_init};
8'h13: up_rdata <= { 8'h0, up_tdd_frame_length};
8'h14: up_rdata <= {31'h0, up_tdd_terminal_type};
8'h18: up_rdata <= {24'h0, up_tdd_status_s};
8'h20: up_rdata <= { 8'h0, up_tdd_vco_rx_on_1};
8'h21: up_rdata <= { 8'h0, up_tdd_vco_rx_off_1};
8'h22: up_rdata <= { 8'h0, up_tdd_vco_tx_on_1};
8'h23: up_rdata <= { 8'h0, up_tdd_vco_tx_off_1};
8'h24: up_rdata <= { 8'h0, up_tdd_rx_on_1};
8'h25: up_rdata <= { 8'h0, up_tdd_rx_off_1};
8'h26: up_rdata <= { 8'h0, up_tdd_tx_on_1};
8'h27: up_rdata <= { 8'h0, up_tdd_tx_off_1};
8'h28: up_rdata <= { 8'h0, up_tdd_tx_dp_on_1};
8'h29: up_rdata <= { 8'h0, up_tdd_tx_dp_off_1};
8'h30: up_rdata <= { 8'h0, up_tdd_vco_rx_on_2};
8'h31: up_rdata <= { 8'h0, up_tdd_vco_rx_off_2};
8'h32: up_rdata <= { 8'h0, up_tdd_vco_tx_on_2};
8'h33: up_rdata <= { 8'h0, up_tdd_vco_tx_off_2};
8'h34: up_rdata <= { 8'h0, up_tdd_rx_on_2};
8'h35: up_rdata <= { 8'h0, up_tdd_rx_off_2};
8'h36: up_rdata <= { 8'h0, up_tdd_tx_on_2};
8'h37: up_rdata <= { 8'h0, up_tdd_tx_off_2};
8'h38: up_rdata <= { 8'h0, up_tdd_tx_dp_on_2};
8'h39: up_rdata <= { 8'h0, up_tdd_tx_dp_off_2};
default: up_rdata <= 32'h0;
endcase
end
end
end
// rf tdd control signal CDC
up_xfer_cntrl #(.DATA_WIDTH(15)) i_tdd_control (
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_data_cntrl({up_tdd_enable,
up_tdd_secondary,
up_tdd_rx_only,
up_tdd_tx_only,
up_tdd_gated_rx_dmapath,
up_tdd_gated_tx_dmapath,
up_tdd_burst_count,
up_tdd_terminal_type
}),
.up_xfer_done(),
.d_rst(rst),
.d_clk(clk),
.d_data_cntrl({tdd_enable,
tdd_secondary,
tdd_rx_only,
tdd_tx_only,
tdd_gated_rx_dmapath,
tdd_gated_tx_dmapath,
tdd_burst_count,
tdd_terminal_type
}));
up_xfer_cntrl #(.DATA_WIDTH(528)) i_tdd_counter_values (
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_data_cntrl({up_tdd_counter_init,
up_tdd_frame_length,
up_tdd_vco_rx_on_1,
up_tdd_vco_rx_off_1,
up_tdd_vco_tx_on_1,
up_tdd_vco_tx_off_1,
up_tdd_rx_on_1,
up_tdd_rx_off_1,
up_tdd_tx_on_1,
up_tdd_tx_off_1,
up_tdd_tx_dp_on_1,
up_tdd_tx_dp_off_1,
up_tdd_vco_rx_on_2,
up_tdd_vco_rx_off_2,
up_tdd_vco_tx_on_2,
up_tdd_vco_tx_off_2,
up_tdd_rx_on_2,
up_tdd_rx_off_2,
up_tdd_tx_on_2,
up_tdd_tx_off_2,
up_tdd_tx_dp_on_2,
up_tdd_tx_dp_off_2
}),
.up_xfer_done(),
.d_rst(rst),
.d_clk(clk),
.d_data_cntrl({tdd_counter_init,
tdd_frame_length,
tdd_vco_rx_on_1,
tdd_vco_rx_off_1,
tdd_vco_tx_on_1,
tdd_vco_tx_off_1,
tdd_rx_on_1,
tdd_rx_off_1,
tdd_tx_on_1,
tdd_tx_off_1,
tdd_tx_dp_on_1,
tdd_tx_dp_off_1,
tdd_vco_rx_on_2,
tdd_vco_rx_off_2,
tdd_vco_tx_on_2,
tdd_vco_tx_off_2,
tdd_rx_on_2,
tdd_rx_off_2,
tdd_tx_on_2,
tdd_tx_off_2,
tdd_tx_dp_on_2,
tdd_tx_dp_off_2
}));
up_xfer_status #(.DATA_WIDTH(8)) i_tdd_status (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_status (up_tdd_status_s),
.d_rst (rst),
.d_clk (clk),
.d_data_status (tdd_status));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND4B_2_V
`define SKY130_FD_SC_LS__AND4B_2_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog wrapper for and4b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__and4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and4b_2 (
X ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__and4b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and4b_2 (
X ,
A_N,
B ,
C ,
D
);
output X ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__and4b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND4B_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND4BB_1_V
`define SKY130_FD_SC_LS__NAND4BB_1_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog wrapper for nand4bb with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nand4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand4bb_1 (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand4bb_1 (
Y ,
A_N,
B_N,
C ,
D
);
output Y ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND4BB_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EDFXBP_1_V
`define SKY130_FD_SC_LP__EDFXBP_1_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Verilog wrapper for edfxbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__edfxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__edfxbp_1 (
Q ,
Q_N ,
CLK ,
D ,
DE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__edfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.DE(DE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__edfxbp_1 (
Q ,
Q_N,
CLK,
D ,
DE
);
output Q ;
output Q_N;
input CLK;
input D ;
input DE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__edfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.DE(DE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__EDFXBP_1_V
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2015 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file RAM_ram_bank.v when simulating
// the core, RAM_ram_bank. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module RAM_ram_bank(
clka,
wea,
addra,
dina,
douta
);
input clka;
input [0 : 0] wea;
input [3 : 0] addra;
input [3 : 0] dina;
output [3 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(4),
.C_ADDRB_WIDTH(4),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(0),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(16),
.C_READ_DEPTH_B(16),
.C_READ_WIDTH_A(4),
.C_READ_WIDTH_B(4),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(16),
.C_WRITE_DEPTH_B(16),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(4),
.C_WRITE_WIDTH_B(4),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND3B_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__NAND3B_PP_BLACKBOX_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nand3b (
Y ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND3B_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DECAPHETAP_SYMBOL_V
`define SKY130_FD_SC_LS__DECAPHETAP_SYMBOL_V
/**
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__decaphetap ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DECAPHETAP_SYMBOL_V
|
`include "defines.v"
module mem(
//input
//MemControl
input wire[31:0] memData_i,
//MEM-WB
input wire[31:0] writeData_i,
//MEM
input wire[31:0] storeData_i,
input wire[2:0] memOp_i,
//Exception
input wire insValid_i,
input wire[31:0] insAddr_i,
input wire inDelaySlot_i,
input wire[3:0] exception_i,
input wire[31:0] badVAddr_i,
input wire[3:0] exceptionMC_i,
input wire timeInt_i,
input wire serialInt_i,
//WB
input wire writeReg_i,
input wire[4:0] writeRegAddr_i,
input wire[31:0] writeDataHi_i,
input wire[31:0] writeDataLo_i,
input wire writeRegHiLo_i,
input wire writeCP0_i,
input wire[4:0] writeCP0Addr_i,
//CP0
input wire[31:0] cp0_Status_i,
input wire[31:0] cp0_EntryHi_i,
input wire[31:0] cp0_Ebase_i,
input wire[31:0] cp0_EPC_i,
//output
//MemControl
output reg[2:0] memOp_o,
output reg[31:0] storeData_o,
output reg[31:0] memAddr_o,
//WB
output reg writeReg_o,
output reg[4:0] writeRegAddr_o,
output reg[31:0] writeData_o,
output reg[31:0] writeDataHi_o,
output reg[31:0] writeDataLo_o,
output reg writeRegHiLo_o,
output reg writeCP0_o,
output reg[4:0] writeCP0Addr_o,
//Exception Control
output reg flush_o,
output reg[31:0] excAddr_o,
//Exception
output reg[3:0] exception_o,
output reg inDelaySlot_o,
output reg[31:0] insAddr_o,
output reg[31:0] badVAddr_o
);
wire EXL = cp0_Status_i[`Status_EXL];
wire ERL = cp0_Status_i[`Status_ERL];
wire UM = cp0_Status_i[`Status_UM];
wire BEV = cp0_Status_i[`Status_BEV];
wire IE = cp0_Status_i[`Status_IE];
wire[7:0] IM = cp0_Status_i[`Status_IM];
wire isUserMode = (UM == 1'b1 && EXL == 1'b0 && ERL == 1'b0);
wire[7:0] pendingInt = {timeInt_i, 2'h0, serialInt_i, 4'h0};
wire[7:0] intVector = IM & pendingInt;
wire isIntEnable = (IE == 1'b1 && EXL == 1'b0 && ERL == 1'b0 && (|intVector) == 1'b1 && insValid_i == `Enable);
//Data Pass
always @(*) begin
//Exception
inDelaySlot_o = inDelaySlot_i;
insAddr_o = insAddr_i;
//WB
writeRegAddr_o = writeRegAddr_i;
writeDataHi_o = writeDataHi_i;
writeDataLo_o = writeDataLo_i;
writeCP0Addr_o = writeCP0Addr_i;
end
//Pre Exception
reg[3:0] preException;
always @(*) begin
if (isIntEnable == `Enable) begin
//INT
preException = `EXC_INT;
end else if (isUserMode == `Enable && (exception_i == `EXC_ERET || exception_i == `EXC_TLBWI || exception_i == `EXC_MC0)) begin
//CpU
preException = `EXC_CPU;
end else begin
preException = exception_i;
end
end
//Memory Operation
//memOp
reg[2:0] memOp;
always @(*) begin
if (preException == `EXC_NONE) begin
memOp = memOp_i;
end else begin
memOp = `MEM_NOP_OP;
end
end
//Data Fetch
wire[31:0] signData = {{24{memData_i[7]}}, memData_i[7:0]};
wire[31:0] zeroData = {24'h0, memData_i[7:0]};
reg[31:0] writeData;
always @(*) begin
//MMU
memOp_o = memOp;
storeData_o = `ZeroWord;
memAddr_o = `ZeroWord;
//Data
writeData = `ZeroWord;
case (memOp)
`MEM_NOP_OP: begin
//Data
writeData = writeData_i;
end
`MEM_LB_OP: begin
//MMU
memAddr_o = writeData_i;
//Data
writeData = signData;
end
`MEM_LBU_OP: begin
//MMU
memAddr_o = writeData_i;
//Data
writeData = zeroData;
end
`MEM_LW_OP: begin
//MMU
memAddr_o = writeData_i;
//Data
writeData = memData_i;
end
`MEM_SB_OP: begin
//MMU
storeData_o = storeData_i;
memAddr_o = writeData_i;
end
`MEM_SW_OP: begin
//MMU
storeData_o = storeData_i;
memAddr_o = writeData_i;
end
default: begin
end
endcase
end
//Post Exception
always @(*) begin
if (preException != `EXC_NONE) begin
exception_o = preException;
badVAddr_o = badVAddr_i;
end else begin
//Use MC Exception
//ADE, TLB, MCHECK
exception_o = exceptionMC_i;
badVAddr_o = writeData_i;
end
end
//Control-signal
always @(*) begin
if (exception_o == `EXC_NONE || exception_o == `EXC_MC0 || exception_o == `EXC_TLBWI) begin
//WB
writeReg_o = writeReg_i;
writeData_o = writeData;
writeRegHiLo_o = writeRegHiLo_i;
writeCP0_o = writeCP0_i;
//Exception Control
flush_o = `Disable;
excAddr_o = `ZeroWord;
end else begin
//Exception happeded
//WB
writeReg_o = `Disable;
writeData_o = {24'h0, intVector};
writeRegHiLo_o = `Disable;
writeCP0_o = `Disable;
//WB
flush_o = `Enable;
if (exception_o == `EXC_ERET) begin
excAddr_o = cp0_EPC_i;
end else begin
excAddr_o = cp0_Ebase_i;
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__XNOR2_FUNCTIONAL_V
`define SKY130_FD_SC_HS__XNOR2_FUNCTIONAL_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__xnor2 (
VPWR,
VGND,
Y ,
A ,
B
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
input B ;
// Local signals
wire xnor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y , A, B );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, xnor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__XNOR2_FUNCTIONAL_V |
/*
This file is part of Fusion-Core-ISA.
Fusion-Core-ISA is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
Fusion-Core-ISA is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with Fusion-Core-ISA. If not, see <http://www.gnu.org/licenses/>.
*/
module and_32(
input [31:0] a, //input values
input [31:0] b,
output [31:0] out //output value
);
//output is the AND of a and b
assign out[0] = a[0] & b[0];
assign out[1] = a[1] & b[1];
assign out[2] = a[2] & b[2];
assign out[3] = a[3] & b[3];
assign out[4] = a[4] & b[4];
assign out[5] = a[5] & b[5];
assign out[6] = a[6] & b[6];
assign out[7] = a[7] & b[7];
assign out[8] = a[8] & b[8];
assign out[9] = a[9] & b[9];
assign out[10] = a[10] & b[10];
assign out[11] = a[11] & b[11];
assign out[12] = a[12] & b[12];
assign out[13] = a[13] & b[13];
assign out[14] = a[14] & b[14];
assign out[15] = a[15] & b[15];
assign out[16] = a[16] & b[16];
assign out[17] = a[17] & b[17];
assign out[18] = a[18] & b[18];
assign out[19] = a[19] & b[19];
assign out[20] = a[20] & b[20];
assign out[21] = a[21] & b[21];
assign out[22] = a[22] & b[22];
assign out[23] = a[23] & b[23];
assign out[24] = a[24] & b[24];
assign out[25] = a[25] & b[25];
assign out[26] = a[26] & b[26];
assign out[27] = a[27] & b[27];
assign out[28] = a[28] & b[28];
assign out[29] = a[29] & b[29];
assign out[30] = a[30] & b[30];
assign out[31] = a[31] & b[31];
endmodule
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module rec_sync #(
parameter DSIZE = 10
) (
input wire reset,
input wire datain,
output reg [DSIZE-1:0] data,
input wire WCLK,
input wire FCLK,
output reg rec_sync_ready,
input wire decoder_err
);
wire BITSLIP_FLAG, BITSLIP_FLAG_FCLK;
flag_domain_crossing bitslip_flag_domain_crossing_inst (
.CLK_A(WCLK),
.CLK_B(FCLK),
.FLAG_IN_CLK_A(BITSLIP_FLAG),
.FLAG_OUT_CLK_B(BITSLIP_FLAG_FCLK)
);
reg [DSIZE-1:0] shift_reg;
always @(posedge FCLK)
shift_reg <= {shift_reg[DSIZE-2:0], datain};
reg [DSIZE-1:0] bitslip_cnt;
initial bitslip_cnt = 1;
always @(posedge FCLK)
if(BITSLIP_FLAG_FCLK)
bitslip_cnt <= {bitslip_cnt[DSIZE-3:0],bitslip_cnt[DSIZE-1:DSIZE-2]};
else
bitslip_cnt <= {bitslip_cnt[DSIZE-2:0],bitslip_cnt[DSIZE-1]};
reg [DSIZE-1:0] fdataout;
always @(posedge FCLK)
if(bitslip_cnt[0])
fdataout <= shift_reg;
else
fdataout <= fdataout;
// reg [DSIZE-1:0] old_data;
always @(posedge WCLK) begin
data <= fdataout;
// old_data <= data;
end
integer wait_cnt;
reg [2:0] state, next_state;
localparam START = 0,
WAIT = 1,
CHECK = 2,
BITSHIFT = 3,
IDLE = 4;
localparam K28_1P = 10'b00_1111_1001,
K28_1N = 10'b11_0000_0110;
always @(posedge WCLK) begin
if (reset) state <= START;
else state <= next_state;
end
always @(state or wait_cnt or decoder_err) begin // or data or old_data
case(state)
START:
next_state = WAIT;
WAIT:
if (wait_cnt == 2)
next_state = CHECK;
else
next_state = WAIT;
CHECK:
if (decoder_err == 1'b0)//(data == K28_1P && old_data == K28_1N) || (data == K28_1N && old_data == K28_1P))
next_state = IDLE;
else
next_state = BITSHIFT;
BITSHIFT:
next_state = WAIT;
IDLE:
if(decoder_err==1'b1)
next_state = WAIT;
else
next_state = IDLE;
default : next_state = START;
endcase
end
assign BITSLIP_FLAG = (state==CHECK && next_state==BITSHIFT);
//assign rec_sync_ready = (state==IDLE);
always @(posedge WCLK)
begin
if (reset) // get D-FF
begin
rec_sync_ready <= 1'b0;
wait_cnt <= 0;
end
else
begin
rec_sync_ready <= rec_sync_ready;
wait_cnt <= 0;
case (next_state)
START:
begin
rec_sync_ready <= 1'b0;
end
WAIT:
begin
if(decoder_err==1'b1)
rec_sync_ready <= 1'b0;
else
rec_sync_ready <= 1'b1;
wait_cnt <= wait_cnt+1;
end
CHECK:
begin
wait_cnt <= wait_cnt+1;
end
BITSHIFT:
begin
rec_sync_ready <= 1'b0;
end
IDLE:
begin
if(decoder_err==1'b1)
rec_sync_ready <= 1'b0;
else
rec_sync_ready <= 1'b1;
end
endcase
end
end
`ifdef SYNTHESIS_NOT
wire [35:0] control_bus;
chipscope_icon ichipscope_icon
(
.CONTROL0(control_bus)
);
chipscope_ila ichipscope_ila
(
.CONTROL(control_bus),
.CLK(WCLK),
.TRIG0({lck, eye_size, REC_SYNC_ERROR, data, BITSLIP_FLAG, state, pa_ready_flag, reset, pll_rst})
);
`endif
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:48:59 03/24/2015
// Design Name:
// Module Name: Adder32
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Adder16(
input [15:0] A,
input [15:0] B,
input C0,
output [3:0] P,
output [3:0] G,
output [15:0] sum,
output SF,
output CF,
output OF,
output PF,
output ZF
);
wire[15:0] p,g;
wire[4:0] C;
wire[3:0] sf,cf,of,pf,zf;
pg_to_PG pgtoPG(p,g,P,G);
ParallelCarry4 PC(P,G,C0,C);
Adder4 a1(A[3:0],B[3:0],C[0],p[3:0],g[3:0],sum[3:0],sf[0],cf[0],of[0],pf[0],zf[0]),
a2(A[7:4],B[7:4],C[1],p[7:4],g[7:4],sum[7:4],sf[1],cf[1],of[1],pf[1],zf[1]),
a3(A[11:8],B[11:8],C[2],p[11:8],g[11:8],sum[11:8],sf[2],cf[2],of[2],pf[2],zf[2]),
a4(A[15:12],B[15:12],C[3],p[15:12],g[15:12],sum[15:12],sf[3],cf[3],of[3],pf[3],zf[3]);
assign SF=sf[3],
CF=C[4],
OF=of[3],
PF=^pf[3:0],
ZF= ~|(~zf[3:0]);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NAND3_PP_SYMBOL_V
`define SKY130_FD_SC_HVL__NAND3_PP_SYMBOL_V
/**
* nand3: 3-input NAND.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__nand3 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NAND3_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EBUFN_BLACKBOX_V
`define SKY130_FD_SC_HD__EBUFN_BLACKBOX_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__ebufn (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__EBUFN_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__XOR2_2_V
`define SKY130_FD_SC_HDLL__XOR2_2_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog wrapper for xor2 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__xor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__xor2_2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__xor2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__xor2_2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__xor2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__XOR2_2_V
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 00:29:48 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_processing_system7_0_2/zynq_design_1_processing_system7_0_2_stub.v
// Design : zynq_design_1_processing_system7_0_2
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2017.2" *)
module zynq_design_1_processing_system7_0_2(TTC0_WAVE0_OUT, TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID,
M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n,
DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN,
DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output FCLK_CLK0;
output FCLK_RESET0_N;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
endmodule
|
module hf_compression (
input wire val_in,
output reg [3:0] hf_c,
output reg hf_c_valid,
input wire CLK,
input wire Reset
);
// parameter len = 4;
// The length of an uncompressed data amount
/* For constructing the Tree:
* the uncompressed length is 4
* that leaves 0 -> F
* Which is a total of 16 possibilities
* which means that the tree descriptor will need:
* The capacity to describe 16 possibilites
* which will need to say: this is 0, this is 1, this ....
* so any tree leaf will need 4 bits to describe the leaf's value
*/
// Because we have 16 symbols
// The worst case hf code length is 16 bits
// This can be reduced at the cost of compression
// Something like 6 - 8 might be an apropriate compromise
reg building_tree; // Building the tree
reg construct_tree; // Shifted in a page, construct a tree
reg import_tree; // tree constructed elsewhere, is being shifted in
reg [15:0] code;
always @ (posedge CLK or negedge Reset) begin
if(~Reset) begin
end
else begin
end
end
reg [15:0] leaf_A_code;
reg [15:0] leaf_B_code;
reg [15:0] leaf_C_code;
reg [15:0] leaf_D_code;
reg [15:0] leaf_E_code;
reg [15:0] leaf_F_code;
reg [15:0] leaf_G_code;
reg [15:0] leaf_H_code;
reg [15:0] leaf_I_code;
reg [15:0] leaf_J_code;
reg [15:0] leaf_K_code;
reg [15:0] leaf_L_code;
reg [15:0] leaf_M_code;
reg [15:0] leaf_N_code;
reg [15:0] leaf_O_code;
reg [15:0] leaf_P_code;
reg [3:0] leaf_A_value;
reg [3:0] leaf_B_value;
reg [3:0] leaf_C_value;
reg [3:0] leaf_D_value;
reg [3:0] leaf_E_value;
reg [3:0] leaf_F_value;
reg [3:0] leaf_G_value;
reg [3:0] leaf_H_value;
reg [3:0] leaf_I_value;
reg [3:0] leaf_J_value;
reg [3:0] leaf_K_value;
reg [3:0] leaf_L_value;
reg [3:0] leaf_M_value;
reg [3:0] leaf_N_value;
reg [3:0] leaf_O_value;
reg [3:0] leaf_P_value;
always @ (posedge CLK or negedge Reset) begin
if(~Reset) begin
leaf_A_code <= 16'b0;
leaf_B_code <= 16'b0;
leaf_C_code <= 16'b0;
leaf_D_code <= 16'b0;
leaf_E_code <= 16'b0;
leaf_F_code <= 16'b0;
leaf_G_code <= 16'b0;
leaf_H_code <= 16'b0;
leaf_I_code <= 16'b0;
leaf_J_code <= 16'b0;
leaf_K_code <= 16'b0;
leaf_L_code <= 16'b0;
leaf_M_code <= 16'b0;
leaf_N_code <= 16'b0;
leaf_O_code <= 16'b0;
leaf_P_code <= 16'b0;
leaf_A_value <= 4'b0;
leaf_B_value <= 4'b0;
leaf_C_value <= 4'b0;
leaf_D_value <= 4'b0;
leaf_E_value <= 4'b0;
leaf_F_value <= 4'b0;
leaf_G_value <= 4'b0;
leaf_H_value <= 4'b0;
leaf_I_value <= 4'b0;
leaf_J_value <= 4'b0;
leaf_K_value <= 4'b0;
leaf_L_value <= 4'b0;
leaf_M_value <= 4'b0;
leaf_N_value <= 4'b0;
leaf_O_value <= 4'b0;
leaf_P_value <= 4'b0;
end
else begin
if (building_tree) begin
end
else begin
leaf_A_code <= leaf_A_code;
leaf_B_code <= leaf_B_code;
leaf_C_code <= leaf_C_code;
leaf_D_code <= leaf_D_code;
leaf_E_code <= leaf_E_code;
leaf_F_code <= leaf_F_code;
leaf_G_code <= leaf_G_code;
leaf_H_code <= leaf_H_code;
leaf_I_code <= leaf_I_code;
leaf_J_code <= leaf_J_code;
leaf_K_code <= leaf_K_code;
leaf_L_code <= leaf_L_code;
leaf_M_code <= leaf_M_code;
leaf_N_code <= leaf_N_code;
leaf_O_code <= leaf_O_code;
leaf_P_code <= leaf_P_code;
leaf_A_value <= leaf_A_value;
leaf_B_value <= leaf_B_value;
leaf_C_value <= leaf_C_value;
leaf_D_value <= leaf_D_value;
leaf_E_value <= leaf_E_value;
leaf_F_value <= leaf_F_value;
leaf_G_value <= leaf_G_value;
leaf_H_value <= leaf_H_value;
leaf_I_value <= leaf_I_value;
leaf_J_value <= leaf_J_value;
leaf_K_value <= leaf_K_value;
leaf_L_value <= leaf_L_value;
leaf_M_value <= leaf_M_value;
leaf_N_value <= leaf_N_value;
leaf_O_value <= leaf_O_value;
leaf_P_value <= leaf_P_value;
end
end
end |
// "standard.v"
// $Id: standard.v,v 1.5 2009/10/22 22:30:36 fang Exp $
// original verilog definitions (e.g. from vendor's standard cell library)
// inverter
`celldefine
module INV (A, Z);
input A;
output Z;
not (Z, A);
specify
(A => Z)=(3, 3); // rise and fall times
endspecify
endmodule
`endcelldefine
// delay element
`celldefine
module DELAY (A, Z);
parameter delay = 10;
input A;
output Z;
assign #delay Z = A;
endmodule
`endcelldefine
// two-input and-gate
`celldefine
module AND2 (A1, A2, Z);
input A1, A2;
output Z;
and (Z, A1, A2); // plain AND gate
specify
(A1 => Z)=(5, 3); // rise and fall times
(A2 => Z)=(5, 3);
endspecify
endmodule
`endcelldefine
// N-input and-gate
`celldefine
module AND_N (A, Z);
parameter input_size = 2;
input [input_size-1:0] A;
output Z;
and (Z, A); // plain AND gate
specify
(A => Z)=(4+input_size, 2+input_size);
endspecify
endmodule
`endcelldefine
// two-input or gate
`celldefine
module OR2 (A1, A2, Z);
input A1, A2;
output Z;
or (Z, A1, A2); // plain OR gate
specify
(A1 => Z)=(6, 4); // rise and fall times
(A2 => Z)=(6, 4);
endspecify
endmodule
`endcelldefine
// simple flops
`celldefine
module POS_FLOP (CLK, D, Q);
input CLK;
input D;
output reg Q;
always @(posedge CLK)
begin
Q <= D;
end
endmodule
`endcelldefine
`celldefine
module NEG_FLOP (CLK, D, Q);
input CLK;
input D;
output reg Q;
always @(negedge CLK)
begin
Q <= D;
end
endmodule
`endcelldefine
// an array/bus test
`celldefine
module bus_array_test(CLK, A, B, C, D, E, F, G, H);
input CLK;
input A;
input [3:0] B;
input [7:0] C;
input [31:0] D;
output reg E;
output reg [3:0] F;
output reg [7:0] G;
output reg [31:0] H;
always @(posedge CLK)
begin
E <= A;
F <= B;
G <= C;
H <= D;
end
endmodule
`endcelldefine
`celldefine
// testing ignore extra wire keyword
module wire_port_test(
input wire in_a,
input wire [3:0] in_b,
output wire [3:0] out_x);
endmodule
`endcelldefine
|
/* This file is part of JT51.
JT51 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT51 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 27-10-2016
*/
module jt51_eg(
`ifdef TEST_SUPPORT
input test_eg,
`endif
input rst,
input clk,
input cen,
input zero,
// envelope configuration
input [4:0] keycode_III,
input [4:0] arate_II,
input [4:0] rate1_II,
input [4:0] rate2_II,
input [3:0] rrate_II,
input [3:0] d1l_I,
input [1:0] ks_III,
// envelope operation
input keyon_II,
output reg pg_rst_III,
// envelope number
input [6:0] tl_VII,
input [7:0] am,
input [1:0] ams_VII,
input amsen_VII,
output [9:0] eg_XI
);
// eg[9:6] -> direct attenuation (divide by 2)
// eg[5:0] -> mantisa attenuation (uses LUT)
// 1 LSB of eg is -0.09257 dB
localparam ATTACK=2'd0,
DECAY1=2'd1,
DECAY2=2'd2,
RELEASE=2'd3;
reg [ 4:0] d1level_II;
reg [ 2:0] cnt_V;
reg [ 5:0] rate_IV;
wire [ 9:0] eg_VI;
reg [ 9:0] eg_VII, eg_VIII;
wire [ 9:0] eg_II;
reg [11:0] sum_eg_tl_VII;
reg step_V, step_VI;
reg sum_up;
reg [5:0] rate_V;
reg [5:1] rate_VI;
// remember: { log_msb, pow_addr } <= log_val[11:0] + { tl, 5'd0 } + { eg, 2'd0 };
reg [ 1:0] eg_cnt_base;
reg [14:0] eg_cnt /*verilator public*/;
reg [ 9:0] am_final_VII;
always @(posedge clk) begin : envelope_counter
if( rst ) begin
eg_cnt_base <= 2'd0;
eg_cnt <=15'd0;
end
else if(cen) begin
if( zero ) begin
// envelope counter increases every 3 output samples,
// there is one sample every 32 clock ticks
if( eg_cnt_base == 2'd2 ) begin
eg_cnt <= eg_cnt + 1'b1;
eg_cnt_base <= 2'd0;
end
else eg_cnt_base <= eg_cnt_base + 1'b1;
end
end
end
wire cnt_out; // = all_cnt_last[3*31-1:3*30];
reg [6:0] pre_rate_III;
reg [4:0] kshift_III;
reg [4:0] cfg_III;
always @(*) begin : pre_rate_calc
kshift_III = keycode_III >> ~ks_III;
pre_rate_III = { 1'b0, cfg_III, 1'b0 } + { 2'b0, kshift_III };
end
reg [7:0] step_idx;
reg [1:0] state_in_III, state_in_IV, state_in_V, state_in_VI;
always @(*) begin : rate_step
if( rate_V[5:4]==2'b11 ) begin // 0 means 1x, 1 means 2x
if( rate_V[5:2]==4'hf && state_in_V == ATTACK)
step_idx = 8'b11111111; // Maximum attack speed, rates 60&61
else
case( rate_V[1:0] )
2'd0: step_idx = 8'b00000000;
2'd1: step_idx = 8'b10001000; // 2
2'd2: step_idx = 8'b10101010; // 4
2'd3: step_idx = 8'b11101110; // 6
endcase
end
else begin
if( rate_V[5:2]==4'd0 && state_in_V != ATTACK)
step_idx = 8'b11111110; // limit slowest decay rate_IV
else
case( rate_V[1:0] )
2'd0: step_idx = 8'b10101010; // 4
2'd1: step_idx = 8'b11101010; // 5
2'd2: step_idx = 8'b11101110; // 6
2'd3: step_idx = 8'b11111110; // 7
endcase
end
// a rate_IV of zero keeps the level still
step_V = rate_V[5:1]==5'd0 ? 1'b0 : step_idx[ cnt_V ];
end
wire ar_off_VI;
always @(posedge clk) if(cen) begin
// I
if( d1l_I == 4'd15 )
d1level_II <= 5'h10; // 48dB
else
d1level_II <= {1'b0,d1l_I};
end
// II
wire keyon_last_II;
wire keyon_now_II = !keyon_last_II && keyon_II;
wire keyoff_now_II = keyon_last_II && !keyon_II;
wire ar_off_II = keyon_now_II && (arate_II == 5'h1f);
wire [1:0] state_II;
always @(posedge clk) if(cen) begin
pg_rst_III <= keyon_now_II;
// trigger release
if( keyoff_now_II ) begin
cfg_III <= { rrate_II, 1'b1 };
state_in_III <= RELEASE;
end
else begin
// trigger 1st decay
if( keyon_now_II ) begin
cfg_III <= arate_II;
state_in_III <= ATTACK;
end
else begin : sel_rate
case ( state_II )
ATTACK: begin
if( eg_II==10'd0 ) begin
state_in_III <= DECAY1;
cfg_III <= rate1_II;
end
else begin
state_in_III <= state_II; // attack
cfg_III <= arate_II;
end
end
DECAY1: begin
if( eg_II[9:5] >= d1level_II ) begin
cfg_III <= rate2_II;
state_in_III <= DECAY2;
end
else begin
cfg_III <= rate1_II;
state_in_III <= state_II; // decay1
end
end
DECAY2: begin
cfg_III <= rate2_II;
state_in_III <= state_II; // decay2
end
RELEASE: begin
cfg_III <= { rrate_II, 1'b1 };
state_in_III <= state_II; // release
end
endcase
end
end
end
// III
always @(posedge clk) if(cen) begin
state_in_IV <= state_in_III;
rate_IV <= pre_rate_III[6] ? 6'd63 : pre_rate_III[5:0];
end
// IV
always @(posedge clk) if(cen) begin
state_in_V <= state_in_IV;
rate_V <= rate_IV;
if( state_in_IV == ATTACK )
case( rate_IV[5:2] )
4'h0: cnt_V <= eg_cnt[13:11];
4'h1: cnt_V <= eg_cnt[12:10];
4'h2: cnt_V <= eg_cnt[11: 9];
4'h3: cnt_V <= eg_cnt[10: 8];
4'h4: cnt_V <= eg_cnt[ 9: 7];
4'h5: cnt_V <= eg_cnt[ 8: 6];
4'h6: cnt_V <= eg_cnt[ 7: 5];
4'h7: cnt_V <= eg_cnt[ 6: 4];
4'h8: cnt_V <= eg_cnt[ 5: 3];
4'h9: cnt_V <= eg_cnt[ 4: 2];
4'ha: cnt_V <= eg_cnt[ 3: 1];
default: cnt_V <= eg_cnt[ 2: 0];
endcase
else
case( rate_IV[5:2] )
4'h0: cnt_V <= eg_cnt[14:12];
4'h1: cnt_V <= eg_cnt[13:11];
4'h2: cnt_V <= eg_cnt[12:10];
4'h3: cnt_V <= eg_cnt[11: 9];
4'h4: cnt_V <= eg_cnt[10: 8];
4'h5: cnt_V <= eg_cnt[ 9: 7];
4'h6: cnt_V <= eg_cnt[ 8: 6];
4'h7: cnt_V <= eg_cnt[ 7: 5];
4'h8: cnt_V <= eg_cnt[ 6: 4];
4'h9: cnt_V <= eg_cnt[ 5: 3];
4'ha: cnt_V <= eg_cnt[ 4: 2];
4'hb: cnt_V <= eg_cnt[ 3: 1];
default: cnt_V <= eg_cnt[ 2: 0];
endcase
end
// V
always @(posedge clk) if(cen) begin
state_in_VI <= state_in_V;
rate_VI <= rate_V[5:1];
sum_up <= cnt_V[0] != cnt_out;
step_VI <= step_V;
end
///////////////////////////////////////
// VI
reg [8:0] ar_sum0_VI;
reg [9:0] ar_result_VI, ar_sum_VI;
always @(*) begin : ar_calculation
casez( rate_VI[5:2] )
default: ar_sum0_VI = { 3'd0, eg_VI[9:4] } + 9'd1;
4'b1100: ar_sum0_VI = { 3'd0, eg_VI[9:4] } + 9'd1;
4'b1101: ar_sum0_VI = { 2'd0, eg_VI[9:3] } + 9'd1;
4'b111?: ar_sum0_VI = { 1'd0, eg_VI[9:2] } + 9'd1;
endcase
if( rate_VI[5:4] == 2'b11 )
ar_sum_VI = step_VI ? { ar_sum0_VI, 1'b0 } : { 1'b0, ar_sum0_VI };
else
ar_sum_VI = step_VI ? { 1'b0, ar_sum0_VI } : 10'd0;
ar_result_VI = ar_sum_VI<eg_VI ? eg_VI-ar_sum_VI : 10'd0;
end
always @(posedge clk) if(cen) begin
if( ar_off_VI )
eg_VII <= 10'd0;
else
if( state_in_VI == ATTACK ) begin
if( sum_up && eg_VI != 10'd0 )
if( rate_VI[5:1]==5'hf )
eg_VII <= 10'd0;
else
eg_VII <= ar_result_VI;
else
eg_VII <= eg_VI;
end
else begin : DECAY_SUM
if( sum_up ) begin
if ( eg_VI<= (10'd1023-10'd8) )
case( rate_VI[5:2] )
4'b1100: eg_VII <= eg_VI + { 8'd0, step_VI, ~step_VI }; // 12
4'b1101: eg_VII <= eg_VI + { 7'd0, step_VI, ~step_VI, 1'b0 }; // 13
4'b1110: eg_VII <= eg_VI + { 6'd0, step_VI, ~step_VI, 2'b0 }; // 14
4'b1111: eg_VII <= eg_VI + 10'd8;// 15
default: eg_VII <= eg_VI + { 8'd0, step_VI, 1'b0 };
endcase
else eg_VII <= 10'h3FF;
end
else eg_VII <= eg_VI;
end
end
// VII
always @(*) begin : sum_eg_and_tl
casez( {amsen_VII, ams_VII } )
3'b0_??,
3'b1_00: am_final_VII = 10'd0;
3'b1_01: am_final_VII = { 2'b0, am }; // 23.9 dB max
3'b1_10: am_final_VII = { 1'b0, am, 1'b0 }; // 47 dB
3'b1_11: am_final_VII = { am, 2'b0 }; // 95.6 dB
endcase
`ifdef TEST_SUPPORT
if( test_eg && tl_VII!=7'd0 )
sum_eg_tl_VII = 12'd0;
else
`endif
sum_eg_tl_VII = { 2'b0, tl_VII, 3'd0 } // 0.75 dB steps
+ { 2'b0, eg_VII } // 0.094 dB steps
+ { 2'b0, am_final_VII };
end
always @(posedge clk) if(cen) begin
eg_VIII <= |sum_eg_tl_VII[11:10] ? {10{1'b1}} : sum_eg_tl_VII[9:0];
end
jt51_sh #( .width(10), .stages(3) ) u_egpadding (
.rst ( rst ),
.clk ( clk ),
.cen ( cen ),
.din ( eg_VIII ),
.drop ( eg_XI )
);
// Shift registers
jt51_sh #( .width(10), .stages(32-7+2), .rstval(1'b1) ) u_eg1sh(
.rst ( rst ),
.clk ( clk ),
.cen ( cen ),
.din ( eg_VII ),
.drop ( eg_II )
);
jt51_sh #( .width(10), .stages(4), .rstval(1'b1) ) u_eg2sh(
.rst ( rst ),
.clk ( clk ),
.cen ( cen ),
.din ( eg_II ),
.drop ( eg_VI )
);
jt51_sh #( .width(1), .stages(4) ) u_aroffsh(
.rst ( rst ),
.clk ( clk ),
.cen ( cen ),
.din ( ar_off_II ),
.drop ( ar_off_VI )
);
jt51_sh #( .width(1), .stages(32) ) u_konsh(
.rst ( rst ),
.clk ( clk ),
.din ( keyon_II ),
.cen ( cen ),
.drop ( keyon_last_II )
);
jt51_sh #( .width(1), .stages(32) ) u_cntsh(
.rst ( rst ),
.clk ( clk ),
.cen ( cen ),
.din ( cnt_V[0] ),
.drop ( cnt_out )
);
jt51_sh #( .width(2), .stages(32-3+2), .rstval(1'b1) ) u_statesh(
.rst ( rst ),
.clk ( clk ),
.cen ( cen ),
.din ( state_in_III ),
.drop ( state_II )
);
`ifdef JT51_DEBUG
`ifdef SIMULATION
/* verilator lint_off PINMISSING */
wire [4:0] cnt;
sep32_cnt u_sep32_cnt (.clk(clk), .cen(cen), .zero(zero), .cnt(cnt));
sep32 #(.width(10),.stg(11)) sep_eg(
.clk ( clk ),
.cen ( cen ),
.mixed ( eg_XI ),
.cnt ( cnt )
);
sep32 #(.width(7),.stg(7)) sep_tl(
.clk ( clk ),
.cen ( cen ),
.mixed ( tl_VII ),
.cnt ( cnt )
);
sep32 #(.width(2),.stg(3)) sep_state(
.clk ( clk ),
.cen ( cen ),
.mixed ( state_in_III ),
.cnt ( cnt )
);
sep32 #(.width(5),.stg(6)) sep_rate(
.clk ( clk ),
.mixed ( rate_VI ),
.cnt ( cnt )
);
sep32 #(.width(10),.stg(7)) sep_amfinal(
.clk ( clk ),
.cen ( cen ),
.mixed ( am_final_VII ),
.cnt ( cnt )
);
sep32 #(.width(5),.stg(3)) sep_kcfinal(
.clk ( clk ),
.cen ( cen ),
.mixed ( keycode_III ),
.cnt ( cnt )
);
/* verilator lint_on PINMISSING */
`endif
`endif
endmodule
|
// -*- Mode: Verilog -*-
// Filename : wb_dsp_equation_sm.v
// Description : WB DSP Equation State Machine
// Author : Philip Tracton
// Created On : Fri Jan 8 13:47:49 2016
// Last Modified By: Philip Tracton
// Last Modified On: Fri Jan 8 13:47:49 2016
// Update Count : 0
// Status : Unknown, Use with caution!
`include "wb_dsp_slave_registers_include.vh"
module wb_dsp_algorithm_sm (/*AUTOARG*/
// Outputs
alg_start, alg_address, alg_selection, alg_write, alg_data_wr,
status_reg, equation_enable, base_address,
// Inputs
wb_clk, wb_rst, alg_data_rd, begin_equation, equation0_address_reg,
equation1_address_reg, equation2_address_reg,
equation3_address_reg, control_reg, equation_done, active
) ;
parameter dw = 32;
parameter aw = 32;
parameter DEBUG = 0;
input wb_clk;
input wb_rst;
output reg alg_start;
output reg [aw-1:0] alg_address;
output reg [3:0] alg_selection;
output reg alg_write;
output reg [dw-1:0] alg_data_wr;
input wire [dw-1:0] alg_data_rd;
input [3:0] begin_equation;
input [dw-1:0] equation0_address_reg;
input [dw-1:0] equation1_address_reg;
input [dw-1:0] equation2_address_reg;
input [dw-1:0] equation3_address_reg;
input [dw-1:0] control_reg;
output wire [dw-1:0] status_reg;
output reg [7:0] equation_enable;
input equation_done;
output reg [aw-1:0] base_address;
input active;
/*AUTOWIRE*/
/*AUTOREG*/
reg [dw-1:0] equation_control;
reg [dw-1:0] equation_status;
reg [dw-1:0] equation_next;
reg [4:0] state;
reg [4:0] next_state;
parameter STATE_IDLE = 5'h00;
parameter STATE_FETCH_CONTROL = 5'h01;
parameter STATE_FETCH_CONTROL_DONE = 5'h02;
parameter STATE_FETCH_STATUS = 5'h03;
parameter STATE_FETCH_STATUS_DONE = 5'h04;
parameter STATE_FETCH_NEXT = 5'h05;
parameter STATE_FETCH_NEXT_DONE = 5'h06;
parameter STATE_RUN_EQUATION = 5'h07;
parameter STATE_WRITE_STATUS = 5'h08;
parameter STATE_WRITE_STATUS_DONE = 5'h09;
parameter STATE_ERROR = 5'h1F;
wire equation_alg_active = (state != STATE_IDLE);
//
// Control Register Bits
//
wire manual_start_equation;
reg manual_start_equation_delay;
reg current;
reg previous;
always @(posedge wb_clk)
if (wb_rst) begin
current <=0;
previous <= 0;
manual_start_equation_delay <=0;
end else begin
previous <= manual_start_equation;
current<= |control_reg[`CONTROL_REG_BEGIN_EQUATION];
manual_start_equation_delay <= manual_start_equation;
end
assign manual_start_equation = (current & !previous) & !equation_alg_active;
//assign manual_start_equation = (current & !previous) & !equation_alg_active;
wire start_equation = (manual_start_equation |manual_start_equation_delay | begin_equation);
wire stop_equation = control_reg[`CONTROL_REG_STOP_EQUATION];
//
// Status Register Bits
//
assign status_reg[`STATUS_REG_ACTIVE] = active;
assign status_reg[31:1] = 0;
//
//
//
always @(posedge wb_clk)
if (wb_rst) begin
state <= STATE_IDLE;
end else begin
state <= next_state;
end
always @(*)
if (wb_rst) begin
next_state = STATE_IDLE;
alg_start = 0;
alg_address = 0;
alg_selection = 0;
alg_write = 0;
alg_data_wr = 0;
base_address = 0;
equation_control = 0;
equation_status = 0;
equation_next = 0;
equation_enable = 0;
end else begin
case (state)
STATE_IDLE: begin
alg_start = 0;
alg_address = 0;
alg_selection = 0;
alg_write = 0;
alg_data_wr = 0;
//base_address = 0;
equation_control = 0;
equation_status = 0;
equation_next = 0;
equation_enable = 0;
if (start_equation) begin
next_state = STATE_FETCH_CONTROL;
base_address = (begin_equation[0] | control_reg [0]) ? equation0_address_reg :
(begin_equation[1] | control_reg [1]) ? equation1_address_reg :
(begin_equation[2] | control_reg [2]) ? equation2_address_reg :
(begin_equation[3] | control_reg [3]) ? equation3_address_reg : 0;
end else begin
next_state = STATE_IDLE;
end
end // case: STATE_IDLE
STATE_FETCH_CONTROL: begin
alg_address = base_address + `EQUATION_CONTROL_OFFSET;
alg_selection = 4'hF;
alg_write = 0;
alg_start = 1;
next_state = STATE_FETCH_CONTROL_DONE;
end
STATE_FETCH_CONTROL_DONE: begin
alg_start = 0;
if (active) begin
next_state = STATE_FETCH_CONTROL_DONE;
end else begin
equation_control = alg_data_rd;
next_state = STATE_FETCH_STATUS;
end
end
STATE_FETCH_STATUS: begin
alg_address = base_address + `EQUATION_STATUS_OFFSET;
alg_selection = 4'hF;
alg_write = 0;
alg_start = 1;
next_state = STATE_FETCH_STATUS_DONE;
end
STATE_FETCH_STATUS_DONE: begin
alg_start = 0;
if (active) begin
next_state = STATE_FETCH_STATUS_DONE;
end else begin
equation_status = alg_data_rd;
next_state = STATE_FETCH_NEXT;
end
end
STATE_FETCH_NEXT: begin
alg_address = base_address + `EQUATION_NEXT_ADDRESS_OFFSET;
alg_selection = 4'hF;
alg_write = 0;
alg_start = 1;
next_state = STATE_FETCH_NEXT_DONE;
end
STATE_FETCH_NEXT_DONE: begin
alg_start = 0;
if (active) begin
next_state = STATE_FETCH_NEXT_DONE;
end else begin
equation_next = alg_data_rd;
next_state = STATE_RUN_EQUATION;
end
end
STATE_RUN_EQUATION:begin
equation_enable = equation_control[`CONTROL_EQUATION_EQUATION];
if (equation_done) begin
next_state = STATE_IDLE;
end else begin
next_state = STATE_RUN_EQUATION;
end
end
STATE_ERROR: begin
next_state = STATE_IDLE;
end
default begin
next_state = STATE_IDLE;
end
endcase // case (state)
end
`ifdef SIM
reg [32*8-1:0] state_name;
always @(*)
case (state)
STATE_IDLE: state_name = "STATE_IDLE";
STATE_FETCH_CONTROL: state_name = "STATE FETCH CONTROL";
STATE_FETCH_CONTROL_DONE: state_name = "STATE FETCH CONTROL DONE";
STATE_FETCH_STATUS: state_name = "STATE FETCH STATUS";
STATE_FETCH_STATUS_DONE: state_name = "STATE FETCH STATUS DONE";
STATE_FETCH_NEXT: state_name = "STATE FETCH NEXT";
STATE_FETCH_NEXT_DONE: state_name = "STATE FETCH NEXT DONE";
STATE_ERROR: state_name = "STATE_ERROR";
STATE_RUN_EQUATION: state_name = "STATE RUN EQUATION";
default: state_name = "DEFAULT";
endcase // case (state)
`endif
endmodule // wb_dsp_algorithm_sm
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S15_PP_SYMBOL_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S15_PP_SYMBOL_V
/**
* clkdlybuf4s15: Clock Delay Buffer 4-stage 0.15um length inner stage
* gates.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__clkdlybuf4s15 (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S15_PP_SYMBOL_V
|
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