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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR2B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__NOR2B_BEHAVIORAL_PP_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nor2b (
VPWR,
VGND,
Y ,
A ,
B_N
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
input B_N ;
// Local signals
wire Y not0_out ;
wire and0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A );
and and0 (and0_out_Y , not0_out, B_N );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR2B_BEHAVIORAL_PP_V |
// divmmc
//
// Total refactoring. Made module synchroneous. (Sorgelig)
//
module divmmc
(
input clk_sys,
input [1:0] mode,
// CPU interface
input nWR,
input nRD,
input nMREQ,
input nIORQ,
input nM1,
input [15:0] addr,
input [7:0] din,
output [7:0] dout,
// control
input enable,
output active_io,
// SD/MMC SPI
output reg spi_ss,
output spi_clk,
input spi_di,
output spi_do
);
assign active_io = port_io;
wire io_we = ~nIORQ & ~nWR & nM1;
wire io_rd = ~nIORQ & ~nRD & nM1;
wire port_cs = ((mode == 2'b01) && (addr[7:0] == 8'hE7)) ||
((mode == 2'b10) && (addr[7:0] == 8'h1F));
wire port_io = ((mode == 2'b01) && (addr[7:0] == 8'hEB)) ||
((mode == 2'b10) && (addr[7:0] == 8'h3F));
reg tx_strobe;
reg rx_strobe;
always @(posedge clk_sys) begin
reg old_we, old_rd, old_m1;
reg m1_trigger;
rx_strobe <= 0;
tx_strobe <= 0;
if(enable) begin
old_we <= io_we;
old_rd <= io_rd;
if(io_we & ~old_we) begin
if (port_cs) spi_ss <= din[0]; // SPI enable
if (port_io) tx_strobe <= 1'b1; // SPI write
end
// SPI read
if(io_rd & ~old_rd & port_io) rx_strobe <= 1;
end else begin
spi_ss <= 1;
end
end
spi spi
(
.clk_sys(clk_sys),
.tx(tx_strobe),
.rx(rx_strobe),
.din(din),
.dout(dout),
.spi_clk(spi_clk),
.spi_di(spi_di),
.spi_do(spi_do)
);
endmodule
module spi
(
input clk_sys,
input tx, // Byte ready to be transmitted
input rx, // request to read one byte
input [7:0] din,
output [7:0] dout,
output spi_clk,
input spi_di,
output spi_do
);
assign spi_clk = counter[0];
assign spi_do = io_byte[7]; // data is shifted up during transfer
assign dout = data;
reg [4:0] counter = 5'b10000; // tx/rx counter is idle
reg [7:0] io_byte, data;
always @(negedge clk_sys) begin
if(counter[4]) begin
if(rx | tx) begin
counter <= 0;
data <= io_byte;
io_byte <= tx ? din : 8'hff;
end
end else begin
if(spi_clk) io_byte <= { io_byte[6:0], spi_di };
counter <= counter + 2'd1;
end
end
endmodule
|
// soc_system_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.1 196
`timescale 1 ps / 1 ps
module soc_system_mm_interconnect_0 (
input wire [11:0] hps_0_h2f_axi_master_awid, // hps_0_h2f_axi_master.awid
input wire [29:0] hps_0_h2f_axi_master_awaddr, // .awaddr
input wire [3:0] hps_0_h2f_axi_master_awlen, // .awlen
input wire [2:0] hps_0_h2f_axi_master_awsize, // .awsize
input wire [1:0] hps_0_h2f_axi_master_awburst, // .awburst
input wire [1:0] hps_0_h2f_axi_master_awlock, // .awlock
input wire [3:0] hps_0_h2f_axi_master_awcache, // .awcache
input wire [2:0] hps_0_h2f_axi_master_awprot, // .awprot
input wire hps_0_h2f_axi_master_awvalid, // .awvalid
output wire hps_0_h2f_axi_master_awready, // .awready
input wire [11:0] hps_0_h2f_axi_master_wid, // .wid
input wire [63:0] hps_0_h2f_axi_master_wdata, // .wdata
input wire [7:0] hps_0_h2f_axi_master_wstrb, // .wstrb
input wire hps_0_h2f_axi_master_wlast, // .wlast
input wire hps_0_h2f_axi_master_wvalid, // .wvalid
output wire hps_0_h2f_axi_master_wready, // .wready
output wire [11:0] hps_0_h2f_axi_master_bid, // .bid
output wire [1:0] hps_0_h2f_axi_master_bresp, // .bresp
output wire hps_0_h2f_axi_master_bvalid, // .bvalid
input wire hps_0_h2f_axi_master_bready, // .bready
input wire [11:0] hps_0_h2f_axi_master_arid, // .arid
input wire [29:0] hps_0_h2f_axi_master_araddr, // .araddr
input wire [3:0] hps_0_h2f_axi_master_arlen, // .arlen
input wire [2:0] hps_0_h2f_axi_master_arsize, // .arsize
input wire [1:0] hps_0_h2f_axi_master_arburst, // .arburst
input wire [1:0] hps_0_h2f_axi_master_arlock, // .arlock
input wire [3:0] hps_0_h2f_axi_master_arcache, // .arcache
input wire [2:0] hps_0_h2f_axi_master_arprot, // .arprot
input wire hps_0_h2f_axi_master_arvalid, // .arvalid
output wire hps_0_h2f_axi_master_arready, // .arready
output wire [11:0] hps_0_h2f_axi_master_rid, // .rid
output wire [63:0] hps_0_h2f_axi_master_rdata, // .rdata
output wire [1:0] hps_0_h2f_axi_master_rresp, // .rresp
output wire hps_0_h2f_axi_master_rlast, // .rlast
output wire hps_0_h2f_axi_master_rvalid, // .rvalid
input wire hps_0_h2f_axi_master_rready, // .rready
input wire [11:0] hps_0_h2f_lw_axi_master_awid, // hps_0_h2f_lw_axi_master.awid
input wire [20:0] hps_0_h2f_lw_axi_master_awaddr, // .awaddr
input wire [3:0] hps_0_h2f_lw_axi_master_awlen, // .awlen
input wire [2:0] hps_0_h2f_lw_axi_master_awsize, // .awsize
input wire [1:0] hps_0_h2f_lw_axi_master_awburst, // .awburst
input wire [1:0] hps_0_h2f_lw_axi_master_awlock, // .awlock
input wire [3:0] hps_0_h2f_lw_axi_master_awcache, // .awcache
input wire [2:0] hps_0_h2f_lw_axi_master_awprot, // .awprot
input wire hps_0_h2f_lw_axi_master_awvalid, // .awvalid
output wire hps_0_h2f_lw_axi_master_awready, // .awready
input wire [11:0] hps_0_h2f_lw_axi_master_wid, // .wid
input wire [31:0] hps_0_h2f_lw_axi_master_wdata, // .wdata
input wire [3:0] hps_0_h2f_lw_axi_master_wstrb, // .wstrb
input wire hps_0_h2f_lw_axi_master_wlast, // .wlast
input wire hps_0_h2f_lw_axi_master_wvalid, // .wvalid
output wire hps_0_h2f_lw_axi_master_wready, // .wready
output wire [11:0] hps_0_h2f_lw_axi_master_bid, // .bid
output wire [1:0] hps_0_h2f_lw_axi_master_bresp, // .bresp
output wire hps_0_h2f_lw_axi_master_bvalid, // .bvalid
input wire hps_0_h2f_lw_axi_master_bready, // .bready
input wire [11:0] hps_0_h2f_lw_axi_master_arid, // .arid
input wire [20:0] hps_0_h2f_lw_axi_master_araddr, // .araddr
input wire [3:0] hps_0_h2f_lw_axi_master_arlen, // .arlen
input wire [2:0] hps_0_h2f_lw_axi_master_arsize, // .arsize
input wire [1:0] hps_0_h2f_lw_axi_master_arburst, // .arburst
input wire [1:0] hps_0_h2f_lw_axi_master_arlock, // .arlock
input wire [3:0] hps_0_h2f_lw_axi_master_arcache, // .arcache
input wire [2:0] hps_0_h2f_lw_axi_master_arprot, // .arprot
input wire hps_0_h2f_lw_axi_master_arvalid, // .arvalid
output wire hps_0_h2f_lw_axi_master_arready, // .arready
output wire [11:0] hps_0_h2f_lw_axi_master_rid, // .rid
output wire [31:0] hps_0_h2f_lw_axi_master_rdata, // .rdata
output wire [1:0] hps_0_h2f_lw_axi_master_rresp, // .rresp
output wire hps_0_h2f_lw_axi_master_rlast, // .rlast
output wire hps_0_h2f_lw_axi_master_rvalid, // .rvalid
input wire hps_0_h2f_lw_axi_master_rready, // .rready
input wire clk_0_clk_clk, // clk_0_clk.clk
input wire fpga_only_master_clk_reset_reset_bridge_in_reset_reset, // fpga_only_master_clk_reset_reset_bridge_in_reset.reset
input wire hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset, // hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
input wire onchip_memory2_0_reset1_reset_bridge_in_reset_reset, // onchip_memory2_0_reset1_reset_bridge_in_reset.reset
input wire [31:0] fpga_only_master_master_address, // fpga_only_master_master.address
output wire fpga_only_master_master_waitrequest, // .waitrequest
input wire [3:0] fpga_only_master_master_byteenable, // .byteenable
input wire fpga_only_master_master_read, // .read
output wire [31:0] fpga_only_master_master_readdata, // .readdata
output wire fpga_only_master_master_readdatavalid, // .readdatavalid
input wire fpga_only_master_master_write, // .write
input wire [31:0] fpga_only_master_master_writedata, // .writedata
output wire [0:0] intr_capturer_0_avalon_slave_0_address, // intr_capturer_0_avalon_slave_0.address
output wire intr_capturer_0_avalon_slave_0_read, // .read
input wire [31:0] intr_capturer_0_avalon_slave_0_readdata, // .readdata
output wire [0:0] jtag_uart_avalon_jtag_slave_address, // jtag_uart_avalon_jtag_slave.address
output wire jtag_uart_avalon_jtag_slave_write, // .write
output wire jtag_uart_avalon_jtag_slave_read, // .read
input wire [31:0] jtag_uart_avalon_jtag_slave_readdata, // .readdata
output wire [31:0] jtag_uart_avalon_jtag_slave_writedata, // .writedata
input wire jtag_uart_avalon_jtag_slave_waitrequest, // .waitrequest
output wire jtag_uart_avalon_jtag_slave_chipselect, // .chipselect
output wire [12:0] onchip_memory2_0_s1_address, // onchip_memory2_0_s1.address
output wire onchip_memory2_0_s1_write, // .write
input wire [63:0] onchip_memory2_0_s1_readdata, // .readdata
output wire [63:0] onchip_memory2_0_s1_writedata, // .writedata
output wire [7:0] onchip_memory2_0_s1_byteenable, // .byteenable
output wire onchip_memory2_0_s1_chipselect, // .chipselect
output wire onchip_memory2_0_s1_clken, // .clken
output wire rc4_avalon_interface_0_avalon_slave_0_write, // rc4_avalon_interface_0_avalon_slave_0.write
output wire rc4_avalon_interface_0_avalon_slave_0_read, // .read
input wire [31:0] rc4_avalon_interface_0_avalon_slave_0_readdata, // .readdata
output wire [31:0] rc4_avalon_interface_0_avalon_slave_0_writedata, // .writedata
output wire [3:0] rc4_avalon_interface_0_avalon_slave_0_byteenable, // .byteenable
output wire rc4_avalon_interface_0_avalon_slave_0_chipselect, // .chipselect
output wire reg32_avalon_interface_0_avalon_slave_0_write, // reg32_avalon_interface_0_avalon_slave_0.write
output wire reg32_avalon_interface_0_avalon_slave_0_read, // .read
input wire [31:0] reg32_avalon_interface_0_avalon_slave_0_readdata, // .readdata
output wire [31:0] reg32_avalon_interface_0_avalon_slave_0_writedata, // .writedata
output wire [3:0] reg32_avalon_interface_0_avalon_slave_0_byteenable, // .byteenable
output wire reg32_avalon_interface_0_avalon_slave_0_chipselect, // .chipselect
output wire [0:0] sysid_qsys_control_slave_address, // sysid_qsys_control_slave.address
input wire [31:0] sysid_qsys_control_slave_readdata // .readdata
);
wire rsp_mux_src_valid; // rsp_mux:src_valid -> hps_0_h2f_axi_master_agent:write_rp_valid
wire [164:0] rsp_mux_src_data; // rsp_mux:src_data -> hps_0_h2f_axi_master_agent:write_rp_data
wire rsp_mux_src_ready; // hps_0_h2f_axi_master_agent:write_rp_ready -> rsp_mux:src_ready
wire [5:0] rsp_mux_src_channel; // rsp_mux:src_channel -> hps_0_h2f_axi_master_agent:write_rp_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> hps_0_h2f_axi_master_agent:write_rp_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> hps_0_h2f_axi_master_agent:write_rp_endofpacket
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> hps_0_h2f_axi_master_agent:read_rp_valid
wire [164:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> hps_0_h2f_axi_master_agent:read_rp_data
wire rsp_mux_001_src_ready; // hps_0_h2f_axi_master_agent:read_rp_ready -> rsp_mux_001:src_ready
wire [5:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> hps_0_h2f_axi_master_agent:read_rp_channel
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> hps_0_h2f_axi_master_agent:read_rp_startofpacket
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> hps_0_h2f_axi_master_agent:read_rp_endofpacket
wire fpga_only_master_master_translator_avalon_universal_master_0_waitrequest; // fpga_only_master_master_agent:av_waitrequest -> fpga_only_master_master_translator:uav_waitrequest
wire [31:0] fpga_only_master_master_translator_avalon_universal_master_0_readdata; // fpga_only_master_master_agent:av_readdata -> fpga_only_master_master_translator:uav_readdata
wire fpga_only_master_master_translator_avalon_universal_master_0_debugaccess; // fpga_only_master_master_translator:uav_debugaccess -> fpga_only_master_master_agent:av_debugaccess
wire [31:0] fpga_only_master_master_translator_avalon_universal_master_0_address; // fpga_only_master_master_translator:uav_address -> fpga_only_master_master_agent:av_address
wire fpga_only_master_master_translator_avalon_universal_master_0_read; // fpga_only_master_master_translator:uav_read -> fpga_only_master_master_agent:av_read
wire [3:0] fpga_only_master_master_translator_avalon_universal_master_0_byteenable; // fpga_only_master_master_translator:uav_byteenable -> fpga_only_master_master_agent:av_byteenable
wire fpga_only_master_master_translator_avalon_universal_master_0_readdatavalid; // fpga_only_master_master_agent:av_readdatavalid -> fpga_only_master_master_translator:uav_readdatavalid
wire fpga_only_master_master_translator_avalon_universal_master_0_lock; // fpga_only_master_master_translator:uav_lock -> fpga_only_master_master_agent:av_lock
wire fpga_only_master_master_translator_avalon_universal_master_0_write; // fpga_only_master_master_translator:uav_write -> fpga_only_master_master_agent:av_write
wire [31:0] fpga_only_master_master_translator_avalon_universal_master_0_writedata; // fpga_only_master_master_translator:uav_writedata -> fpga_only_master_master_agent:av_writedata
wire [2:0] fpga_only_master_master_translator_avalon_universal_master_0_burstcount; // fpga_only_master_master_translator:uav_burstcount -> fpga_only_master_master_agent:av_burstcount
wire [63:0] onchip_memory2_0_s1_agent_m0_readdata; // onchip_memory2_0_s1_translator:uav_readdata -> onchip_memory2_0_s1_agent:m0_readdata
wire onchip_memory2_0_s1_agent_m0_waitrequest; // onchip_memory2_0_s1_translator:uav_waitrequest -> onchip_memory2_0_s1_agent:m0_waitrequest
wire onchip_memory2_0_s1_agent_m0_debugaccess; // onchip_memory2_0_s1_agent:m0_debugaccess -> onchip_memory2_0_s1_translator:uav_debugaccess
wire [31:0] onchip_memory2_0_s1_agent_m0_address; // onchip_memory2_0_s1_agent:m0_address -> onchip_memory2_0_s1_translator:uav_address
wire [7:0] onchip_memory2_0_s1_agent_m0_byteenable; // onchip_memory2_0_s1_agent:m0_byteenable -> onchip_memory2_0_s1_translator:uav_byteenable
wire onchip_memory2_0_s1_agent_m0_read; // onchip_memory2_0_s1_agent:m0_read -> onchip_memory2_0_s1_translator:uav_read
wire onchip_memory2_0_s1_agent_m0_readdatavalid; // onchip_memory2_0_s1_translator:uav_readdatavalid -> onchip_memory2_0_s1_agent:m0_readdatavalid
wire onchip_memory2_0_s1_agent_m0_lock; // onchip_memory2_0_s1_agent:m0_lock -> onchip_memory2_0_s1_translator:uav_lock
wire [63:0] onchip_memory2_0_s1_agent_m0_writedata; // onchip_memory2_0_s1_agent:m0_writedata -> onchip_memory2_0_s1_translator:uav_writedata
wire onchip_memory2_0_s1_agent_m0_write; // onchip_memory2_0_s1_agent:m0_write -> onchip_memory2_0_s1_translator:uav_write
wire [3:0] onchip_memory2_0_s1_agent_m0_burstcount; // onchip_memory2_0_s1_agent:m0_burstcount -> onchip_memory2_0_s1_translator:uav_burstcount
wire onchip_memory2_0_s1_agent_rf_source_valid; // onchip_memory2_0_s1_agent:rf_source_valid -> onchip_memory2_0_s1_agent_rsp_fifo:in_valid
wire [165:0] onchip_memory2_0_s1_agent_rf_source_data; // onchip_memory2_0_s1_agent:rf_source_data -> onchip_memory2_0_s1_agent_rsp_fifo:in_data
wire onchip_memory2_0_s1_agent_rf_source_ready; // onchip_memory2_0_s1_agent_rsp_fifo:in_ready -> onchip_memory2_0_s1_agent:rf_source_ready
wire onchip_memory2_0_s1_agent_rf_source_startofpacket; // onchip_memory2_0_s1_agent:rf_source_startofpacket -> onchip_memory2_0_s1_agent_rsp_fifo:in_startofpacket
wire onchip_memory2_0_s1_agent_rf_source_endofpacket; // onchip_memory2_0_s1_agent:rf_source_endofpacket -> onchip_memory2_0_s1_agent_rsp_fifo:in_endofpacket
wire onchip_memory2_0_s1_agent_rsp_fifo_out_valid; // onchip_memory2_0_s1_agent_rsp_fifo:out_valid -> onchip_memory2_0_s1_agent:rf_sink_valid
wire [165:0] onchip_memory2_0_s1_agent_rsp_fifo_out_data; // onchip_memory2_0_s1_agent_rsp_fifo:out_data -> onchip_memory2_0_s1_agent:rf_sink_data
wire onchip_memory2_0_s1_agent_rsp_fifo_out_ready; // onchip_memory2_0_s1_agent:rf_sink_ready -> onchip_memory2_0_s1_agent_rsp_fifo:out_ready
wire onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket; // onchip_memory2_0_s1_agent_rsp_fifo:out_startofpacket -> onchip_memory2_0_s1_agent:rf_sink_startofpacket
wire onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket; // onchip_memory2_0_s1_agent_rsp_fifo:out_endofpacket -> onchip_memory2_0_s1_agent:rf_sink_endofpacket
wire onchip_memory2_0_s1_agent_rdata_fifo_src_valid; // onchip_memory2_0_s1_agent:rdata_fifo_src_valid -> onchip_memory2_0_s1_agent_rdata_fifo:in_valid
wire [65:0] onchip_memory2_0_s1_agent_rdata_fifo_src_data; // onchip_memory2_0_s1_agent:rdata_fifo_src_data -> onchip_memory2_0_s1_agent_rdata_fifo:in_data
wire onchip_memory2_0_s1_agent_rdata_fifo_src_ready; // onchip_memory2_0_s1_agent_rdata_fifo:in_ready -> onchip_memory2_0_s1_agent:rdata_fifo_src_ready
wire [31:0] jtag_uart_avalon_jtag_slave_agent_m0_readdata; // jtag_uart_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_avalon_jtag_slave_agent:m0_readdata
wire jtag_uart_avalon_jtag_slave_agent_m0_waitrequest; // jtag_uart_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_avalon_jtag_slave_agent:m0_waitrequest
wire jtag_uart_avalon_jtag_slave_agent_m0_debugaccess; // jtag_uart_avalon_jtag_slave_agent:m0_debugaccess -> jtag_uart_avalon_jtag_slave_translator:uav_debugaccess
wire [31:0] jtag_uart_avalon_jtag_slave_agent_m0_address; // jtag_uart_avalon_jtag_slave_agent:m0_address -> jtag_uart_avalon_jtag_slave_translator:uav_address
wire [3:0] jtag_uart_avalon_jtag_slave_agent_m0_byteenable; // jtag_uart_avalon_jtag_slave_agent:m0_byteenable -> jtag_uart_avalon_jtag_slave_translator:uav_byteenable
wire jtag_uart_avalon_jtag_slave_agent_m0_read; // jtag_uart_avalon_jtag_slave_agent:m0_read -> jtag_uart_avalon_jtag_slave_translator:uav_read
wire jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid; // jtag_uart_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_avalon_jtag_slave_agent:m0_readdatavalid
wire jtag_uart_avalon_jtag_slave_agent_m0_lock; // jtag_uart_avalon_jtag_slave_agent:m0_lock -> jtag_uart_avalon_jtag_slave_translator:uav_lock
wire [31:0] jtag_uart_avalon_jtag_slave_agent_m0_writedata; // jtag_uart_avalon_jtag_slave_agent:m0_writedata -> jtag_uart_avalon_jtag_slave_translator:uav_writedata
wire jtag_uart_avalon_jtag_slave_agent_m0_write; // jtag_uart_avalon_jtag_slave_agent:m0_write -> jtag_uart_avalon_jtag_slave_translator:uav_write
wire [2:0] jtag_uart_avalon_jtag_slave_agent_m0_burstcount; // jtag_uart_avalon_jtag_slave_agent:m0_burstcount -> jtag_uart_avalon_jtag_slave_translator:uav_burstcount
wire jtag_uart_avalon_jtag_slave_agent_rf_source_valid; // jtag_uart_avalon_jtag_slave_agent:rf_source_valid -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_valid
wire [129:0] jtag_uart_avalon_jtag_slave_agent_rf_source_data; // jtag_uart_avalon_jtag_slave_agent:rf_source_data -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_data
wire jtag_uart_avalon_jtag_slave_agent_rf_source_ready; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_ready -> jtag_uart_avalon_jtag_slave_agent:rf_source_ready
wire jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket; // jtag_uart_avalon_jtag_slave_agent:rf_source_startofpacket -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_startofpacket
wire jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket; // jtag_uart_avalon_jtag_slave_agent:rf_source_endofpacket -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_endofpacket
wire jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_valid -> jtag_uart_avalon_jtag_slave_agent:rf_sink_valid
wire [129:0] jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_data -> jtag_uart_avalon_jtag_slave_agent:rf_sink_data
wire jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready; // jtag_uart_avalon_jtag_slave_agent:rf_sink_ready -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_ready
wire jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_startofpacket -> jtag_uart_avalon_jtag_slave_agent:rf_sink_startofpacket
wire jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_endofpacket -> jtag_uart_avalon_jtag_slave_agent:rf_sink_endofpacket
wire jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid; // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_valid -> jtag_uart_avalon_jtag_slave_agent_rdata_fifo:in_valid
wire [33:0] jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data; // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_data -> jtag_uart_avalon_jtag_slave_agent_rdata_fifo:in_data
wire jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready; // jtag_uart_avalon_jtag_slave_agent_rdata_fifo:in_ready -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_ready
wire [31:0] intr_capturer_0_avalon_slave_0_agent_m0_readdata; // intr_capturer_0_avalon_slave_0_translator:uav_readdata -> intr_capturer_0_avalon_slave_0_agent:m0_readdata
wire intr_capturer_0_avalon_slave_0_agent_m0_waitrequest; // intr_capturer_0_avalon_slave_0_translator:uav_waitrequest -> intr_capturer_0_avalon_slave_0_agent:m0_waitrequest
wire intr_capturer_0_avalon_slave_0_agent_m0_debugaccess; // intr_capturer_0_avalon_slave_0_agent:m0_debugaccess -> intr_capturer_0_avalon_slave_0_translator:uav_debugaccess
wire [31:0] intr_capturer_0_avalon_slave_0_agent_m0_address; // intr_capturer_0_avalon_slave_0_agent:m0_address -> intr_capturer_0_avalon_slave_0_translator:uav_address
wire [3:0] intr_capturer_0_avalon_slave_0_agent_m0_byteenable; // intr_capturer_0_avalon_slave_0_agent:m0_byteenable -> intr_capturer_0_avalon_slave_0_translator:uav_byteenable
wire intr_capturer_0_avalon_slave_0_agent_m0_read; // intr_capturer_0_avalon_slave_0_agent:m0_read -> intr_capturer_0_avalon_slave_0_translator:uav_read
wire intr_capturer_0_avalon_slave_0_agent_m0_readdatavalid; // intr_capturer_0_avalon_slave_0_translator:uav_readdatavalid -> intr_capturer_0_avalon_slave_0_agent:m0_readdatavalid
wire intr_capturer_0_avalon_slave_0_agent_m0_lock; // intr_capturer_0_avalon_slave_0_agent:m0_lock -> intr_capturer_0_avalon_slave_0_translator:uav_lock
wire [31:0] intr_capturer_0_avalon_slave_0_agent_m0_writedata; // intr_capturer_0_avalon_slave_0_agent:m0_writedata -> intr_capturer_0_avalon_slave_0_translator:uav_writedata
wire intr_capturer_0_avalon_slave_0_agent_m0_write; // intr_capturer_0_avalon_slave_0_agent:m0_write -> intr_capturer_0_avalon_slave_0_translator:uav_write
wire [2:0] intr_capturer_0_avalon_slave_0_agent_m0_burstcount; // intr_capturer_0_avalon_slave_0_agent:m0_burstcount -> intr_capturer_0_avalon_slave_0_translator:uav_burstcount
wire intr_capturer_0_avalon_slave_0_agent_rf_source_valid; // intr_capturer_0_avalon_slave_0_agent:rf_source_valid -> intr_capturer_0_avalon_slave_0_agent_rsp_fifo:in_valid
wire [129:0] intr_capturer_0_avalon_slave_0_agent_rf_source_data; // intr_capturer_0_avalon_slave_0_agent:rf_source_data -> intr_capturer_0_avalon_slave_0_agent_rsp_fifo:in_data
wire intr_capturer_0_avalon_slave_0_agent_rf_source_ready; // intr_capturer_0_avalon_slave_0_agent_rsp_fifo:in_ready -> intr_capturer_0_avalon_slave_0_agent:rf_source_ready
wire intr_capturer_0_avalon_slave_0_agent_rf_source_startofpacket; // intr_capturer_0_avalon_slave_0_agent:rf_source_startofpacket -> intr_capturer_0_avalon_slave_0_agent_rsp_fifo:in_startofpacket
wire intr_capturer_0_avalon_slave_0_agent_rf_source_endofpacket; // intr_capturer_0_avalon_slave_0_agent:rf_source_endofpacket -> intr_capturer_0_avalon_slave_0_agent_rsp_fifo:in_endofpacket
wire intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_valid; // intr_capturer_0_avalon_slave_0_agent_rsp_fifo:out_valid -> intr_capturer_0_avalon_slave_0_agent:rf_sink_valid
wire [129:0] intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_data; // intr_capturer_0_avalon_slave_0_agent_rsp_fifo:out_data -> intr_capturer_0_avalon_slave_0_agent:rf_sink_data
wire intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_ready; // intr_capturer_0_avalon_slave_0_agent:rf_sink_ready -> intr_capturer_0_avalon_slave_0_agent_rsp_fifo:out_ready
wire intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_startofpacket; // intr_capturer_0_avalon_slave_0_agent_rsp_fifo:out_startofpacket -> intr_capturer_0_avalon_slave_0_agent:rf_sink_startofpacket
wire intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_endofpacket; // intr_capturer_0_avalon_slave_0_agent_rsp_fifo:out_endofpacket -> intr_capturer_0_avalon_slave_0_agent:rf_sink_endofpacket
wire intr_capturer_0_avalon_slave_0_agent_rdata_fifo_src_valid; // intr_capturer_0_avalon_slave_0_agent:rdata_fifo_src_valid -> intr_capturer_0_avalon_slave_0_agent_rdata_fifo:in_valid
wire [33:0] intr_capturer_0_avalon_slave_0_agent_rdata_fifo_src_data; // intr_capturer_0_avalon_slave_0_agent:rdata_fifo_src_data -> intr_capturer_0_avalon_slave_0_agent_rdata_fifo:in_data
wire intr_capturer_0_avalon_slave_0_agent_rdata_fifo_src_ready; // intr_capturer_0_avalon_slave_0_agent_rdata_fifo:in_ready -> intr_capturer_0_avalon_slave_0_agent:rdata_fifo_src_ready
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> intr_capturer_0_avalon_slave_0_agent:cp_valid
wire [128:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> intr_capturer_0_avalon_slave_0_agent:cp_data
wire cmd_mux_002_src_ready; // intr_capturer_0_avalon_slave_0_agent:cp_ready -> cmd_mux_002:src_ready
wire [5:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> intr_capturer_0_avalon_slave_0_agent:cp_channel
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> intr_capturer_0_avalon_slave_0_agent:cp_startofpacket
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> intr_capturer_0_avalon_slave_0_agent:cp_endofpacket
wire [31:0] sysid_qsys_control_slave_agent_m0_readdata; // sysid_qsys_control_slave_translator:uav_readdata -> sysid_qsys_control_slave_agent:m0_readdata
wire sysid_qsys_control_slave_agent_m0_waitrequest; // sysid_qsys_control_slave_translator:uav_waitrequest -> sysid_qsys_control_slave_agent:m0_waitrequest
wire sysid_qsys_control_slave_agent_m0_debugaccess; // sysid_qsys_control_slave_agent:m0_debugaccess -> sysid_qsys_control_slave_translator:uav_debugaccess
wire [31:0] sysid_qsys_control_slave_agent_m0_address; // sysid_qsys_control_slave_agent:m0_address -> sysid_qsys_control_slave_translator:uav_address
wire [3:0] sysid_qsys_control_slave_agent_m0_byteenable; // sysid_qsys_control_slave_agent:m0_byteenable -> sysid_qsys_control_slave_translator:uav_byteenable
wire sysid_qsys_control_slave_agent_m0_read; // sysid_qsys_control_slave_agent:m0_read -> sysid_qsys_control_slave_translator:uav_read
wire sysid_qsys_control_slave_agent_m0_readdatavalid; // sysid_qsys_control_slave_translator:uav_readdatavalid -> sysid_qsys_control_slave_agent:m0_readdatavalid
wire sysid_qsys_control_slave_agent_m0_lock; // sysid_qsys_control_slave_agent:m0_lock -> sysid_qsys_control_slave_translator:uav_lock
wire [31:0] sysid_qsys_control_slave_agent_m0_writedata; // sysid_qsys_control_slave_agent:m0_writedata -> sysid_qsys_control_slave_translator:uav_writedata
wire sysid_qsys_control_slave_agent_m0_write; // sysid_qsys_control_slave_agent:m0_write -> sysid_qsys_control_slave_translator:uav_write
wire [2:0] sysid_qsys_control_slave_agent_m0_burstcount; // sysid_qsys_control_slave_agent:m0_burstcount -> sysid_qsys_control_slave_translator:uav_burstcount
wire sysid_qsys_control_slave_agent_rf_source_valid; // sysid_qsys_control_slave_agent:rf_source_valid -> sysid_qsys_control_slave_agent_rsp_fifo:in_valid
wire [129:0] sysid_qsys_control_slave_agent_rf_source_data; // sysid_qsys_control_slave_agent:rf_source_data -> sysid_qsys_control_slave_agent_rsp_fifo:in_data
wire sysid_qsys_control_slave_agent_rf_source_ready; // sysid_qsys_control_slave_agent_rsp_fifo:in_ready -> sysid_qsys_control_slave_agent:rf_source_ready
wire sysid_qsys_control_slave_agent_rf_source_startofpacket; // sysid_qsys_control_slave_agent:rf_source_startofpacket -> sysid_qsys_control_slave_agent_rsp_fifo:in_startofpacket
wire sysid_qsys_control_slave_agent_rf_source_endofpacket; // sysid_qsys_control_slave_agent:rf_source_endofpacket -> sysid_qsys_control_slave_agent_rsp_fifo:in_endofpacket
wire sysid_qsys_control_slave_agent_rsp_fifo_out_valid; // sysid_qsys_control_slave_agent_rsp_fifo:out_valid -> sysid_qsys_control_slave_agent:rf_sink_valid
wire [129:0] sysid_qsys_control_slave_agent_rsp_fifo_out_data; // sysid_qsys_control_slave_agent_rsp_fifo:out_data -> sysid_qsys_control_slave_agent:rf_sink_data
wire sysid_qsys_control_slave_agent_rsp_fifo_out_ready; // sysid_qsys_control_slave_agent:rf_sink_ready -> sysid_qsys_control_slave_agent_rsp_fifo:out_ready
wire sysid_qsys_control_slave_agent_rsp_fifo_out_startofpacket; // sysid_qsys_control_slave_agent_rsp_fifo:out_startofpacket -> sysid_qsys_control_slave_agent:rf_sink_startofpacket
wire sysid_qsys_control_slave_agent_rsp_fifo_out_endofpacket; // sysid_qsys_control_slave_agent_rsp_fifo:out_endofpacket -> sysid_qsys_control_slave_agent:rf_sink_endofpacket
wire sysid_qsys_control_slave_agent_rdata_fifo_src_valid; // sysid_qsys_control_slave_agent:rdata_fifo_src_valid -> sysid_qsys_control_slave_agent_rdata_fifo:in_valid
wire [33:0] sysid_qsys_control_slave_agent_rdata_fifo_src_data; // sysid_qsys_control_slave_agent:rdata_fifo_src_data -> sysid_qsys_control_slave_agent_rdata_fifo:in_data
wire sysid_qsys_control_slave_agent_rdata_fifo_src_ready; // sysid_qsys_control_slave_agent_rdata_fifo:in_ready -> sysid_qsys_control_slave_agent:rdata_fifo_src_ready
wire [31:0] reg32_avalon_interface_0_avalon_slave_0_agent_m0_readdata; // reg32_avalon_interface_0_avalon_slave_0_translator:uav_readdata -> reg32_avalon_interface_0_avalon_slave_0_agent:m0_readdata
wire reg32_avalon_interface_0_avalon_slave_0_agent_m0_waitrequest; // reg32_avalon_interface_0_avalon_slave_0_translator:uav_waitrequest -> reg32_avalon_interface_0_avalon_slave_0_agent:m0_waitrequest
wire reg32_avalon_interface_0_avalon_slave_0_agent_m0_debugaccess; // reg32_avalon_interface_0_avalon_slave_0_agent:m0_debugaccess -> reg32_avalon_interface_0_avalon_slave_0_translator:uav_debugaccess
wire [31:0] reg32_avalon_interface_0_avalon_slave_0_agent_m0_address; // reg32_avalon_interface_0_avalon_slave_0_agent:m0_address -> reg32_avalon_interface_0_avalon_slave_0_translator:uav_address
wire [3:0] reg32_avalon_interface_0_avalon_slave_0_agent_m0_byteenable; // reg32_avalon_interface_0_avalon_slave_0_agent:m0_byteenable -> reg32_avalon_interface_0_avalon_slave_0_translator:uav_byteenable
wire reg32_avalon_interface_0_avalon_slave_0_agent_m0_read; // reg32_avalon_interface_0_avalon_slave_0_agent:m0_read -> reg32_avalon_interface_0_avalon_slave_0_translator:uav_read
wire reg32_avalon_interface_0_avalon_slave_0_agent_m0_readdatavalid; // reg32_avalon_interface_0_avalon_slave_0_translator:uav_readdatavalid -> reg32_avalon_interface_0_avalon_slave_0_agent:m0_readdatavalid
wire reg32_avalon_interface_0_avalon_slave_0_agent_m0_lock; // reg32_avalon_interface_0_avalon_slave_0_agent:m0_lock -> reg32_avalon_interface_0_avalon_slave_0_translator:uav_lock
wire [31:0] reg32_avalon_interface_0_avalon_slave_0_agent_m0_writedata; // reg32_avalon_interface_0_avalon_slave_0_agent:m0_writedata -> reg32_avalon_interface_0_avalon_slave_0_translator:uav_writedata
wire reg32_avalon_interface_0_avalon_slave_0_agent_m0_write; // reg32_avalon_interface_0_avalon_slave_0_agent:m0_write -> reg32_avalon_interface_0_avalon_slave_0_translator:uav_write
wire [2:0] reg32_avalon_interface_0_avalon_slave_0_agent_m0_burstcount; // reg32_avalon_interface_0_avalon_slave_0_agent:m0_burstcount -> reg32_avalon_interface_0_avalon_slave_0_translator:uav_burstcount
wire reg32_avalon_interface_0_avalon_slave_0_agent_rf_source_valid; // reg32_avalon_interface_0_avalon_slave_0_agent:rf_source_valid -> reg32_avalon_interface_0_avalon_slave_0_agent_rsp_fifo:in_valid
wire [129:0] reg32_avalon_interface_0_avalon_slave_0_agent_rf_source_data; // reg32_avalon_interface_0_avalon_slave_0_agent:rf_source_data -> reg32_avalon_interface_0_avalon_slave_0_agent_rsp_fifo:in_data
wire reg32_avalon_interface_0_avalon_slave_0_agent_rf_source_ready; // reg32_avalon_interface_0_avalon_slave_0_agent_rsp_fifo:in_ready -> reg32_avalon_interface_0_avalon_slave_0_agent:rf_source_ready
wire reg32_avalon_interface_0_avalon_slave_0_agent_rf_source_startofpacket; // reg32_avalon_interface_0_avalon_slave_0_agent:rf_source_startofpacket -> reg32_avalon_interface_0_avalon_slave_0_agent_rsp_fifo:in_startofpacket
wire reg32_avalon_interface_0_avalon_slave_0_agent_rf_source_endofpacket; // reg32_avalon_interface_0_avalon_slave_0_agent:rf_source_endofpacket -> reg32_avalon_interface_0_avalon_slave_0_agent_rsp_fifo:in_endofpacket
wire reg32_avalon_interface_0_avalon_slave_0_agent_rsp_fifo_out_valid; // reg32_avalon_interface_0_avalon_slave_0_agent_rsp_fifo:out_valid -> reg32_avalon_interface_0_avalon_slave_0_agent:rf_sink_valid
wire [129:0] reg32_avalon_interface_0_avalon_slave_0_agent_rsp_fifo_out_data; // reg32_avalon_interface_0_avalon_slave_0_agent_rsp_fifo:out_data -> reg32_avalon_interface_0_avalon_slave_0_agent:rf_sink_data
wire reg32_avalon_interface_0_avalon_slave_0_agent_rsp_fifo_out_ready; // reg32_avalon_interface_0_avalon_slave_0_agent:rf_sink_ready -> reg32_avalon_interface_0_avalon_slave_0_agent_rsp_fifo:out_ready
wire reg32_avalon_interface_0_avalon_slave_0_agent_rsp_fifo_out_startofpacket; // reg32_avalon_interface_0_avalon_slave_0_agent_rsp_fifo:out_startofpacket -> reg32_avalon_interface_0_avalon_slave_0_agent:rf_sink_startofpacket
wire reg32_avalon_interface_0_avalon_slave_0_agent_rsp_fifo_out_endofpacket; // reg32_avalon_interface_0_avalon_slave_0_agent_rsp_fifo:out_endofpacket -> reg32_avalon_interface_0_avalon_slave_0_agent:rf_sink_endofpacket
wire reg32_avalon_interface_0_avalon_slave_0_agent_rdata_fifo_src_valid; // reg32_avalon_interface_0_avalon_slave_0_agent:rdata_fifo_src_valid -> reg32_avalon_interface_0_avalon_slave_0_agent_rdata_fifo:in_valid
wire [33:0] reg32_avalon_interface_0_avalon_slave_0_agent_rdata_fifo_src_data; // reg32_avalon_interface_0_avalon_slave_0_agent:rdata_fifo_src_data -> reg32_avalon_interface_0_avalon_slave_0_agent_rdata_fifo:in_data
wire reg32_avalon_interface_0_avalon_slave_0_agent_rdata_fifo_src_ready; // reg32_avalon_interface_0_avalon_slave_0_agent_rdata_fifo:in_ready -> reg32_avalon_interface_0_avalon_slave_0_agent:rdata_fifo_src_ready
wire [31:0] rc4_avalon_interface_0_avalon_slave_0_agent_m0_readdata; // rc4_avalon_interface_0_avalon_slave_0_translator:uav_readdata -> rc4_avalon_interface_0_avalon_slave_0_agent:m0_readdata
wire rc4_avalon_interface_0_avalon_slave_0_agent_m0_waitrequest; // rc4_avalon_interface_0_avalon_slave_0_translator:uav_waitrequest -> rc4_avalon_interface_0_avalon_slave_0_agent:m0_waitrequest
wire rc4_avalon_interface_0_avalon_slave_0_agent_m0_debugaccess; // rc4_avalon_interface_0_avalon_slave_0_agent:m0_debugaccess -> rc4_avalon_interface_0_avalon_slave_0_translator:uav_debugaccess
wire [31:0] rc4_avalon_interface_0_avalon_slave_0_agent_m0_address; // rc4_avalon_interface_0_avalon_slave_0_agent:m0_address -> rc4_avalon_interface_0_avalon_slave_0_translator:uav_address
wire [3:0] rc4_avalon_interface_0_avalon_slave_0_agent_m0_byteenable; // rc4_avalon_interface_0_avalon_slave_0_agent:m0_byteenable -> rc4_avalon_interface_0_avalon_slave_0_translator:uav_byteenable
wire rc4_avalon_interface_0_avalon_slave_0_agent_m0_read; // rc4_avalon_interface_0_avalon_slave_0_agent:m0_read -> rc4_avalon_interface_0_avalon_slave_0_translator:uav_read
wire rc4_avalon_interface_0_avalon_slave_0_agent_m0_readdatavalid; // rc4_avalon_interface_0_avalon_slave_0_translator:uav_readdatavalid -> rc4_avalon_interface_0_avalon_slave_0_agent:m0_readdatavalid
wire rc4_avalon_interface_0_avalon_slave_0_agent_m0_lock; // rc4_avalon_interface_0_avalon_slave_0_agent:m0_lock -> rc4_avalon_interface_0_avalon_slave_0_translator:uav_lock
wire [31:0] rc4_avalon_interface_0_avalon_slave_0_agent_m0_writedata; // rc4_avalon_interface_0_avalon_slave_0_agent:m0_writedata -> rc4_avalon_interface_0_avalon_slave_0_translator:uav_writedata
wire rc4_avalon_interface_0_avalon_slave_0_agent_m0_write; // rc4_avalon_interface_0_avalon_slave_0_agent:m0_write -> rc4_avalon_interface_0_avalon_slave_0_translator:uav_write
wire [2:0] rc4_avalon_interface_0_avalon_slave_0_agent_m0_burstcount; // rc4_avalon_interface_0_avalon_slave_0_agent:m0_burstcount -> rc4_avalon_interface_0_avalon_slave_0_translator:uav_burstcount
wire rc4_avalon_interface_0_avalon_slave_0_agent_rf_source_valid; // rc4_avalon_interface_0_avalon_slave_0_agent:rf_source_valid -> rc4_avalon_interface_0_avalon_slave_0_agent_rsp_fifo:in_valid
wire [129:0] rc4_avalon_interface_0_avalon_slave_0_agent_rf_source_data; // rc4_avalon_interface_0_avalon_slave_0_agent:rf_source_data -> rc4_avalon_interface_0_avalon_slave_0_agent_rsp_fifo:in_data
wire rc4_avalon_interface_0_avalon_slave_0_agent_rf_source_ready; // rc4_avalon_interface_0_avalon_slave_0_agent_rsp_fifo:in_ready -> rc4_avalon_interface_0_avalon_slave_0_agent:rf_source_ready
wire rc4_avalon_interface_0_avalon_slave_0_agent_rf_source_startofpacket; // rc4_avalon_interface_0_avalon_slave_0_agent:rf_source_startofpacket -> rc4_avalon_interface_0_avalon_slave_0_agent_rsp_fifo:in_startofpacket
wire rc4_avalon_interface_0_avalon_slave_0_agent_rf_source_endofpacket; // rc4_avalon_interface_0_avalon_slave_0_agent:rf_source_endofpacket -> rc4_avalon_interface_0_avalon_slave_0_agent_rsp_fifo:in_endofpacket
wire rc4_avalon_interface_0_avalon_slave_0_agent_rsp_fifo_out_valid; // rc4_avalon_interface_0_avalon_slave_0_agent_rsp_fifo:out_valid -> rc4_avalon_interface_0_avalon_slave_0_agent:rf_sink_valid
wire [129:0] rc4_avalon_interface_0_avalon_slave_0_agent_rsp_fifo_out_data; // rc4_avalon_interface_0_avalon_slave_0_agent_rsp_fifo:out_data -> rc4_avalon_interface_0_avalon_slave_0_agent:rf_sink_data
wire rc4_avalon_interface_0_avalon_slave_0_agent_rsp_fifo_out_ready; // rc4_avalon_interface_0_avalon_slave_0_agent:rf_sink_ready -> rc4_avalon_interface_0_avalon_slave_0_agent_rsp_fifo:out_ready
wire rc4_avalon_interface_0_avalon_slave_0_agent_rsp_fifo_out_startofpacket; // rc4_avalon_interface_0_avalon_slave_0_agent_rsp_fifo:out_startofpacket -> rc4_avalon_interface_0_avalon_slave_0_agent:rf_sink_startofpacket
wire rc4_avalon_interface_0_avalon_slave_0_agent_rsp_fifo_out_endofpacket; // rc4_avalon_interface_0_avalon_slave_0_agent_rsp_fifo:out_endofpacket -> rc4_avalon_interface_0_avalon_slave_0_agent:rf_sink_endofpacket
wire rc4_avalon_interface_0_avalon_slave_0_agent_rdata_fifo_src_valid; // rc4_avalon_interface_0_avalon_slave_0_agent:rdata_fifo_src_valid -> rc4_avalon_interface_0_avalon_slave_0_agent_rdata_fifo:in_valid
wire [33:0] rc4_avalon_interface_0_avalon_slave_0_agent_rdata_fifo_src_data; // rc4_avalon_interface_0_avalon_slave_0_agent:rdata_fifo_src_data -> rc4_avalon_interface_0_avalon_slave_0_agent_rdata_fifo:in_data
wire rc4_avalon_interface_0_avalon_slave_0_agent_rdata_fifo_src_ready; // rc4_avalon_interface_0_avalon_slave_0_agent_rdata_fifo:in_ready -> rc4_avalon_interface_0_avalon_slave_0_agent:rdata_fifo_src_ready
wire hps_0_h2f_axi_master_agent_write_cp_valid; // hps_0_h2f_axi_master_agent:write_cp_valid -> router:sink_valid
wire [164:0] hps_0_h2f_axi_master_agent_write_cp_data; // hps_0_h2f_axi_master_agent:write_cp_data -> router:sink_data
wire hps_0_h2f_axi_master_agent_write_cp_ready; // router:sink_ready -> hps_0_h2f_axi_master_agent:write_cp_ready
wire hps_0_h2f_axi_master_agent_write_cp_startofpacket; // hps_0_h2f_axi_master_agent:write_cp_startofpacket -> router:sink_startofpacket
wire hps_0_h2f_axi_master_agent_write_cp_endofpacket; // hps_0_h2f_axi_master_agent:write_cp_endofpacket -> router:sink_endofpacket
wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
wire [164:0] router_src_data; // router:src_data -> cmd_demux:sink_data
wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
wire [5:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
wire hps_0_h2f_axi_master_agent_read_cp_valid; // hps_0_h2f_axi_master_agent:read_cp_valid -> router_001:sink_valid
wire [164:0] hps_0_h2f_axi_master_agent_read_cp_data; // hps_0_h2f_axi_master_agent:read_cp_data -> router_001:sink_data
wire hps_0_h2f_axi_master_agent_read_cp_ready; // router_001:sink_ready -> hps_0_h2f_axi_master_agent:read_cp_ready
wire hps_0_h2f_axi_master_agent_read_cp_startofpacket; // hps_0_h2f_axi_master_agent:read_cp_startofpacket -> router_001:sink_startofpacket
wire hps_0_h2f_axi_master_agent_read_cp_endofpacket; // hps_0_h2f_axi_master_agent:read_cp_endofpacket -> router_001:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> cmd_demux_001:sink_valid
wire [164:0] router_001_src_data; // router_001:src_data -> cmd_demux_001:sink_data
wire router_001_src_ready; // cmd_demux_001:sink_ready -> router_001:src_ready
wire [5:0] router_001_src_channel; // router_001:src_channel -> cmd_demux_001:sink_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
wire fpga_only_master_master_agent_cp_valid; // fpga_only_master_master_agent:cp_valid -> router_002:sink_valid
wire [128:0] fpga_only_master_master_agent_cp_data; // fpga_only_master_master_agent:cp_data -> router_002:sink_data
wire fpga_only_master_master_agent_cp_ready; // router_002:sink_ready -> fpga_only_master_master_agent:cp_ready
wire fpga_only_master_master_agent_cp_startofpacket; // fpga_only_master_master_agent:cp_startofpacket -> router_002:sink_startofpacket
wire fpga_only_master_master_agent_cp_endofpacket; // fpga_only_master_master_agent:cp_endofpacket -> router_002:sink_endofpacket
wire hps_0_h2f_lw_axi_master_agent_write_cp_valid; // hps_0_h2f_lw_axi_master_agent:write_cp_valid -> router_003:sink_valid
wire [128:0] hps_0_h2f_lw_axi_master_agent_write_cp_data; // hps_0_h2f_lw_axi_master_agent:write_cp_data -> router_003:sink_data
wire hps_0_h2f_lw_axi_master_agent_write_cp_ready; // router_003:sink_ready -> hps_0_h2f_lw_axi_master_agent:write_cp_ready
wire hps_0_h2f_lw_axi_master_agent_write_cp_startofpacket; // hps_0_h2f_lw_axi_master_agent:write_cp_startofpacket -> router_003:sink_startofpacket
wire hps_0_h2f_lw_axi_master_agent_write_cp_endofpacket; // hps_0_h2f_lw_axi_master_agent:write_cp_endofpacket -> router_003:sink_endofpacket
wire hps_0_h2f_lw_axi_master_agent_read_cp_valid; // hps_0_h2f_lw_axi_master_agent:read_cp_valid -> router_004:sink_valid
wire [128:0] hps_0_h2f_lw_axi_master_agent_read_cp_data; // hps_0_h2f_lw_axi_master_agent:read_cp_data -> router_004:sink_data
wire hps_0_h2f_lw_axi_master_agent_read_cp_ready; // router_004:sink_ready -> hps_0_h2f_lw_axi_master_agent:read_cp_ready
wire hps_0_h2f_lw_axi_master_agent_read_cp_startofpacket; // hps_0_h2f_lw_axi_master_agent:read_cp_startofpacket -> router_004:sink_startofpacket
wire hps_0_h2f_lw_axi_master_agent_read_cp_endofpacket; // hps_0_h2f_lw_axi_master_agent:read_cp_endofpacket -> router_004:sink_endofpacket
wire onchip_memory2_0_s1_agent_rp_valid; // onchip_memory2_0_s1_agent:rp_valid -> router_005:sink_valid
wire [164:0] onchip_memory2_0_s1_agent_rp_data; // onchip_memory2_0_s1_agent:rp_data -> router_005:sink_data
wire onchip_memory2_0_s1_agent_rp_ready; // router_005:sink_ready -> onchip_memory2_0_s1_agent:rp_ready
wire onchip_memory2_0_s1_agent_rp_startofpacket; // onchip_memory2_0_s1_agent:rp_startofpacket -> router_005:sink_startofpacket
wire onchip_memory2_0_s1_agent_rp_endofpacket; // onchip_memory2_0_s1_agent:rp_endofpacket -> router_005:sink_endofpacket
wire router_005_src_valid; // router_005:src_valid -> rsp_demux:sink_valid
wire [164:0] router_005_src_data; // router_005:src_data -> rsp_demux:sink_data
wire router_005_src_ready; // rsp_demux:sink_ready -> router_005:src_ready
wire [5:0] router_005_src_channel; // router_005:src_channel -> rsp_demux:sink_channel
wire router_005_src_startofpacket; // router_005:src_startofpacket -> rsp_demux:sink_startofpacket
wire router_005_src_endofpacket; // router_005:src_endofpacket -> rsp_demux:sink_endofpacket
wire jtag_uart_avalon_jtag_slave_agent_rp_valid; // jtag_uart_avalon_jtag_slave_agent:rp_valid -> router_006:sink_valid
wire [128:0] jtag_uart_avalon_jtag_slave_agent_rp_data; // jtag_uart_avalon_jtag_slave_agent:rp_data -> router_006:sink_data
wire jtag_uart_avalon_jtag_slave_agent_rp_ready; // router_006:sink_ready -> jtag_uart_avalon_jtag_slave_agent:rp_ready
wire jtag_uart_avalon_jtag_slave_agent_rp_startofpacket; // jtag_uart_avalon_jtag_slave_agent:rp_startofpacket -> router_006:sink_startofpacket
wire jtag_uart_avalon_jtag_slave_agent_rp_endofpacket; // jtag_uart_avalon_jtag_slave_agent:rp_endofpacket -> router_006:sink_endofpacket
wire router_006_src_valid; // router_006:src_valid -> rsp_demux_001:sink_valid
wire [128:0] router_006_src_data; // router_006:src_data -> rsp_demux_001:sink_data
wire router_006_src_ready; // rsp_demux_001:sink_ready -> router_006:src_ready
wire [5:0] router_006_src_channel; // router_006:src_channel -> rsp_demux_001:sink_channel
wire router_006_src_startofpacket; // router_006:src_startofpacket -> rsp_demux_001:sink_startofpacket
wire router_006_src_endofpacket; // router_006:src_endofpacket -> rsp_demux_001:sink_endofpacket
wire intr_capturer_0_avalon_slave_0_agent_rp_valid; // intr_capturer_0_avalon_slave_0_agent:rp_valid -> router_007:sink_valid
wire [128:0] intr_capturer_0_avalon_slave_0_agent_rp_data; // intr_capturer_0_avalon_slave_0_agent:rp_data -> router_007:sink_data
wire intr_capturer_0_avalon_slave_0_agent_rp_ready; // router_007:sink_ready -> intr_capturer_0_avalon_slave_0_agent:rp_ready
wire intr_capturer_0_avalon_slave_0_agent_rp_startofpacket; // intr_capturer_0_avalon_slave_0_agent:rp_startofpacket -> router_007:sink_startofpacket
wire intr_capturer_0_avalon_slave_0_agent_rp_endofpacket; // intr_capturer_0_avalon_slave_0_agent:rp_endofpacket -> router_007:sink_endofpacket
wire router_007_src_valid; // router_007:src_valid -> rsp_demux_002:sink_valid
wire [128:0] router_007_src_data; // router_007:src_data -> rsp_demux_002:sink_data
wire router_007_src_ready; // rsp_demux_002:sink_ready -> router_007:src_ready
wire [5:0] router_007_src_channel; // router_007:src_channel -> rsp_demux_002:sink_channel
wire router_007_src_startofpacket; // router_007:src_startofpacket -> rsp_demux_002:sink_startofpacket
wire router_007_src_endofpacket; // router_007:src_endofpacket -> rsp_demux_002:sink_endofpacket
wire sysid_qsys_control_slave_agent_rp_valid; // sysid_qsys_control_slave_agent:rp_valid -> router_008:sink_valid
wire [128:0] sysid_qsys_control_slave_agent_rp_data; // sysid_qsys_control_slave_agent:rp_data -> router_008:sink_data
wire sysid_qsys_control_slave_agent_rp_ready; // router_008:sink_ready -> sysid_qsys_control_slave_agent:rp_ready
wire sysid_qsys_control_slave_agent_rp_startofpacket; // sysid_qsys_control_slave_agent:rp_startofpacket -> router_008:sink_startofpacket
wire sysid_qsys_control_slave_agent_rp_endofpacket; // sysid_qsys_control_slave_agent:rp_endofpacket -> router_008:sink_endofpacket
wire router_008_src_valid; // router_008:src_valid -> rsp_demux_003:sink_valid
wire [128:0] router_008_src_data; // router_008:src_data -> rsp_demux_003:sink_data
wire router_008_src_ready; // rsp_demux_003:sink_ready -> router_008:src_ready
wire [5:0] router_008_src_channel; // router_008:src_channel -> rsp_demux_003:sink_channel
wire router_008_src_startofpacket; // router_008:src_startofpacket -> rsp_demux_003:sink_startofpacket
wire router_008_src_endofpacket; // router_008:src_endofpacket -> rsp_demux_003:sink_endofpacket
wire reg32_avalon_interface_0_avalon_slave_0_agent_rp_valid; // reg32_avalon_interface_0_avalon_slave_0_agent:rp_valid -> router_009:sink_valid
wire [128:0] reg32_avalon_interface_0_avalon_slave_0_agent_rp_data; // reg32_avalon_interface_0_avalon_slave_0_agent:rp_data -> router_009:sink_data
wire reg32_avalon_interface_0_avalon_slave_0_agent_rp_ready; // router_009:sink_ready -> reg32_avalon_interface_0_avalon_slave_0_agent:rp_ready
wire reg32_avalon_interface_0_avalon_slave_0_agent_rp_startofpacket; // reg32_avalon_interface_0_avalon_slave_0_agent:rp_startofpacket -> router_009:sink_startofpacket
wire reg32_avalon_interface_0_avalon_slave_0_agent_rp_endofpacket; // reg32_avalon_interface_0_avalon_slave_0_agent:rp_endofpacket -> router_009:sink_endofpacket
wire router_009_src_valid; // router_009:src_valid -> rsp_demux_004:sink_valid
wire [128:0] router_009_src_data; // router_009:src_data -> rsp_demux_004:sink_data
wire router_009_src_ready; // rsp_demux_004:sink_ready -> router_009:src_ready
wire [5:0] router_009_src_channel; // router_009:src_channel -> rsp_demux_004:sink_channel
wire router_009_src_startofpacket; // router_009:src_startofpacket -> rsp_demux_004:sink_startofpacket
wire router_009_src_endofpacket; // router_009:src_endofpacket -> rsp_demux_004:sink_endofpacket
wire rc4_avalon_interface_0_avalon_slave_0_agent_rp_valid; // rc4_avalon_interface_0_avalon_slave_0_agent:rp_valid -> router_010:sink_valid
wire [128:0] rc4_avalon_interface_0_avalon_slave_0_agent_rp_data; // rc4_avalon_interface_0_avalon_slave_0_agent:rp_data -> router_010:sink_data
wire rc4_avalon_interface_0_avalon_slave_0_agent_rp_ready; // router_010:sink_ready -> rc4_avalon_interface_0_avalon_slave_0_agent:rp_ready
wire rc4_avalon_interface_0_avalon_slave_0_agent_rp_startofpacket; // rc4_avalon_interface_0_avalon_slave_0_agent:rp_startofpacket -> router_010:sink_startofpacket
wire rc4_avalon_interface_0_avalon_slave_0_agent_rp_endofpacket; // rc4_avalon_interface_0_avalon_slave_0_agent:rp_endofpacket -> router_010:sink_endofpacket
wire router_010_src_valid; // router_010:src_valid -> rsp_demux_005:sink_valid
wire [128:0] router_010_src_data; // router_010:src_data -> rsp_demux_005:sink_data
wire router_010_src_ready; // rsp_demux_005:sink_ready -> router_010:src_ready
wire [5:0] router_010_src_channel; // router_010:src_channel -> rsp_demux_005:sink_channel
wire router_010_src_startofpacket; // router_010:src_startofpacket -> rsp_demux_005:sink_startofpacket
wire router_010_src_endofpacket; // router_010:src_endofpacket -> rsp_demux_005:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> fpga_only_master_master_limiter:cmd_sink_valid
wire [128:0] router_002_src_data; // router_002:src_data -> fpga_only_master_master_limiter:cmd_sink_data
wire router_002_src_ready; // fpga_only_master_master_limiter:cmd_sink_ready -> router_002:src_ready
wire [5:0] router_002_src_channel; // router_002:src_channel -> fpga_only_master_master_limiter:cmd_sink_channel
wire router_002_src_startofpacket; // router_002:src_startofpacket -> fpga_only_master_master_limiter:cmd_sink_startofpacket
wire router_002_src_endofpacket; // router_002:src_endofpacket -> fpga_only_master_master_limiter:cmd_sink_endofpacket
wire [128:0] fpga_only_master_master_limiter_cmd_src_data; // fpga_only_master_master_limiter:cmd_src_data -> cmd_demux_002:sink_data
wire fpga_only_master_master_limiter_cmd_src_ready; // cmd_demux_002:sink_ready -> fpga_only_master_master_limiter:cmd_src_ready
wire [5:0] fpga_only_master_master_limiter_cmd_src_channel; // fpga_only_master_master_limiter:cmd_src_channel -> cmd_demux_002:sink_channel
wire fpga_only_master_master_limiter_cmd_src_startofpacket; // fpga_only_master_master_limiter:cmd_src_startofpacket -> cmd_demux_002:sink_startofpacket
wire fpga_only_master_master_limiter_cmd_src_endofpacket; // fpga_only_master_master_limiter:cmd_src_endofpacket -> cmd_demux_002:sink_endofpacket
wire rsp_mux_002_src_valid; // rsp_mux_002:src_valid -> fpga_only_master_master_limiter:rsp_sink_valid
wire [128:0] rsp_mux_002_src_data; // rsp_mux_002:src_data -> fpga_only_master_master_limiter:rsp_sink_data
wire rsp_mux_002_src_ready; // fpga_only_master_master_limiter:rsp_sink_ready -> rsp_mux_002:src_ready
wire [5:0] rsp_mux_002_src_channel; // rsp_mux_002:src_channel -> fpga_only_master_master_limiter:rsp_sink_channel
wire rsp_mux_002_src_startofpacket; // rsp_mux_002:src_startofpacket -> fpga_only_master_master_limiter:rsp_sink_startofpacket
wire rsp_mux_002_src_endofpacket; // rsp_mux_002:src_endofpacket -> fpga_only_master_master_limiter:rsp_sink_endofpacket
wire fpga_only_master_master_limiter_rsp_src_valid; // fpga_only_master_master_limiter:rsp_src_valid -> fpga_only_master_master_agent:rp_valid
wire [128:0] fpga_only_master_master_limiter_rsp_src_data; // fpga_only_master_master_limiter:rsp_src_data -> fpga_only_master_master_agent:rp_data
wire fpga_only_master_master_limiter_rsp_src_ready; // fpga_only_master_master_agent:rp_ready -> fpga_only_master_master_limiter:rsp_src_ready
wire [5:0] fpga_only_master_master_limiter_rsp_src_channel; // fpga_only_master_master_limiter:rsp_src_channel -> fpga_only_master_master_agent:rp_channel
wire fpga_only_master_master_limiter_rsp_src_startofpacket; // fpga_only_master_master_limiter:rsp_src_startofpacket -> fpga_only_master_master_agent:rp_startofpacket
wire fpga_only_master_master_limiter_rsp_src_endofpacket; // fpga_only_master_master_limiter:rsp_src_endofpacket -> fpga_only_master_master_agent:rp_endofpacket
wire router_003_src_valid; // router_003:src_valid -> hps_0_h2f_lw_axi_master_wr_limiter:cmd_sink_valid
wire [128:0] router_003_src_data; // router_003:src_data -> hps_0_h2f_lw_axi_master_wr_limiter:cmd_sink_data
wire router_003_src_ready; // hps_0_h2f_lw_axi_master_wr_limiter:cmd_sink_ready -> router_003:src_ready
wire [5:0] router_003_src_channel; // router_003:src_channel -> hps_0_h2f_lw_axi_master_wr_limiter:cmd_sink_channel
wire router_003_src_startofpacket; // router_003:src_startofpacket -> hps_0_h2f_lw_axi_master_wr_limiter:cmd_sink_startofpacket
wire router_003_src_endofpacket; // router_003:src_endofpacket -> hps_0_h2f_lw_axi_master_wr_limiter:cmd_sink_endofpacket
wire [128:0] hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_data; // hps_0_h2f_lw_axi_master_wr_limiter:cmd_src_data -> cmd_demux_003:sink_data
wire hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_ready; // cmd_demux_003:sink_ready -> hps_0_h2f_lw_axi_master_wr_limiter:cmd_src_ready
wire [5:0] hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_channel; // hps_0_h2f_lw_axi_master_wr_limiter:cmd_src_channel -> cmd_demux_003:sink_channel
wire hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_startofpacket; // hps_0_h2f_lw_axi_master_wr_limiter:cmd_src_startofpacket -> cmd_demux_003:sink_startofpacket
wire hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_endofpacket; // hps_0_h2f_lw_axi_master_wr_limiter:cmd_src_endofpacket -> cmd_demux_003:sink_endofpacket
wire rsp_mux_003_src_valid; // rsp_mux_003:src_valid -> hps_0_h2f_lw_axi_master_wr_limiter:rsp_sink_valid
wire [128:0] rsp_mux_003_src_data; // rsp_mux_003:src_data -> hps_0_h2f_lw_axi_master_wr_limiter:rsp_sink_data
wire rsp_mux_003_src_ready; // hps_0_h2f_lw_axi_master_wr_limiter:rsp_sink_ready -> rsp_mux_003:src_ready
wire [5:0] rsp_mux_003_src_channel; // rsp_mux_003:src_channel -> hps_0_h2f_lw_axi_master_wr_limiter:rsp_sink_channel
wire rsp_mux_003_src_startofpacket; // rsp_mux_003:src_startofpacket -> hps_0_h2f_lw_axi_master_wr_limiter:rsp_sink_startofpacket
wire rsp_mux_003_src_endofpacket; // rsp_mux_003:src_endofpacket -> hps_0_h2f_lw_axi_master_wr_limiter:rsp_sink_endofpacket
wire hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_valid; // hps_0_h2f_lw_axi_master_wr_limiter:rsp_src_valid -> hps_0_h2f_lw_axi_master_agent:write_rp_valid
wire [128:0] hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_data; // hps_0_h2f_lw_axi_master_wr_limiter:rsp_src_data -> hps_0_h2f_lw_axi_master_agent:write_rp_data
wire hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_ready; // hps_0_h2f_lw_axi_master_agent:write_rp_ready -> hps_0_h2f_lw_axi_master_wr_limiter:rsp_src_ready
wire [5:0] hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_channel; // hps_0_h2f_lw_axi_master_wr_limiter:rsp_src_channel -> hps_0_h2f_lw_axi_master_agent:write_rp_channel
wire hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_startofpacket; // hps_0_h2f_lw_axi_master_wr_limiter:rsp_src_startofpacket -> hps_0_h2f_lw_axi_master_agent:write_rp_startofpacket
wire hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_endofpacket; // hps_0_h2f_lw_axi_master_wr_limiter:rsp_src_endofpacket -> hps_0_h2f_lw_axi_master_agent:write_rp_endofpacket
wire router_004_src_valid; // router_004:src_valid -> hps_0_h2f_lw_axi_master_rd_limiter:cmd_sink_valid
wire [128:0] router_004_src_data; // router_004:src_data -> hps_0_h2f_lw_axi_master_rd_limiter:cmd_sink_data
wire router_004_src_ready; // hps_0_h2f_lw_axi_master_rd_limiter:cmd_sink_ready -> router_004:src_ready
wire [5:0] router_004_src_channel; // router_004:src_channel -> hps_0_h2f_lw_axi_master_rd_limiter:cmd_sink_channel
wire router_004_src_startofpacket; // router_004:src_startofpacket -> hps_0_h2f_lw_axi_master_rd_limiter:cmd_sink_startofpacket
wire router_004_src_endofpacket; // router_004:src_endofpacket -> hps_0_h2f_lw_axi_master_rd_limiter:cmd_sink_endofpacket
wire [128:0] hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_data; // hps_0_h2f_lw_axi_master_rd_limiter:cmd_src_data -> cmd_demux_004:sink_data
wire hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_ready; // cmd_demux_004:sink_ready -> hps_0_h2f_lw_axi_master_rd_limiter:cmd_src_ready
wire [5:0] hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_channel; // hps_0_h2f_lw_axi_master_rd_limiter:cmd_src_channel -> cmd_demux_004:sink_channel
wire hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_startofpacket; // hps_0_h2f_lw_axi_master_rd_limiter:cmd_src_startofpacket -> cmd_demux_004:sink_startofpacket
wire hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_endofpacket; // hps_0_h2f_lw_axi_master_rd_limiter:cmd_src_endofpacket -> cmd_demux_004:sink_endofpacket
wire rsp_mux_004_src_valid; // rsp_mux_004:src_valid -> hps_0_h2f_lw_axi_master_rd_limiter:rsp_sink_valid
wire [128:0] rsp_mux_004_src_data; // rsp_mux_004:src_data -> hps_0_h2f_lw_axi_master_rd_limiter:rsp_sink_data
wire rsp_mux_004_src_ready; // hps_0_h2f_lw_axi_master_rd_limiter:rsp_sink_ready -> rsp_mux_004:src_ready
wire [5:0] rsp_mux_004_src_channel; // rsp_mux_004:src_channel -> hps_0_h2f_lw_axi_master_rd_limiter:rsp_sink_channel
wire rsp_mux_004_src_startofpacket; // rsp_mux_004:src_startofpacket -> hps_0_h2f_lw_axi_master_rd_limiter:rsp_sink_startofpacket
wire rsp_mux_004_src_endofpacket; // rsp_mux_004:src_endofpacket -> hps_0_h2f_lw_axi_master_rd_limiter:rsp_sink_endofpacket
wire hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_valid; // hps_0_h2f_lw_axi_master_rd_limiter:rsp_src_valid -> hps_0_h2f_lw_axi_master_agent:read_rp_valid
wire [128:0] hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_data; // hps_0_h2f_lw_axi_master_rd_limiter:rsp_src_data -> hps_0_h2f_lw_axi_master_agent:read_rp_data
wire hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_ready; // hps_0_h2f_lw_axi_master_agent:read_rp_ready -> hps_0_h2f_lw_axi_master_rd_limiter:rsp_src_ready
wire [5:0] hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_channel; // hps_0_h2f_lw_axi_master_rd_limiter:rsp_src_channel -> hps_0_h2f_lw_axi_master_agent:read_rp_channel
wire hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_startofpacket; // hps_0_h2f_lw_axi_master_rd_limiter:rsp_src_startofpacket -> hps_0_h2f_lw_axi_master_agent:read_rp_startofpacket
wire hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_endofpacket; // hps_0_h2f_lw_axi_master_rd_limiter:rsp_src_endofpacket -> hps_0_h2f_lw_axi_master_agent:read_rp_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> onchip_memory2_0_s1_burst_adapter:sink0_valid
wire [164:0] cmd_mux_src_data; // cmd_mux:src_data -> onchip_memory2_0_s1_burst_adapter:sink0_data
wire cmd_mux_src_ready; // onchip_memory2_0_s1_burst_adapter:sink0_ready -> cmd_mux:src_ready
wire [5:0] cmd_mux_src_channel; // cmd_mux:src_channel -> onchip_memory2_0_s1_burst_adapter:sink0_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> onchip_memory2_0_s1_burst_adapter:sink0_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> onchip_memory2_0_s1_burst_adapter:sink0_endofpacket
wire onchip_memory2_0_s1_burst_adapter_source0_valid; // onchip_memory2_0_s1_burst_adapter:source0_valid -> onchip_memory2_0_s1_agent:cp_valid
wire [164:0] onchip_memory2_0_s1_burst_adapter_source0_data; // onchip_memory2_0_s1_burst_adapter:source0_data -> onchip_memory2_0_s1_agent:cp_data
wire onchip_memory2_0_s1_burst_adapter_source0_ready; // onchip_memory2_0_s1_agent:cp_ready -> onchip_memory2_0_s1_burst_adapter:source0_ready
wire [5:0] onchip_memory2_0_s1_burst_adapter_source0_channel; // onchip_memory2_0_s1_burst_adapter:source0_channel -> onchip_memory2_0_s1_agent:cp_channel
wire onchip_memory2_0_s1_burst_adapter_source0_startofpacket; // onchip_memory2_0_s1_burst_adapter:source0_startofpacket -> onchip_memory2_0_s1_agent:cp_startofpacket
wire onchip_memory2_0_s1_burst_adapter_source0_endofpacket; // onchip_memory2_0_s1_burst_adapter:source0_endofpacket -> onchip_memory2_0_s1_agent:cp_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> jtag_uart_avalon_jtag_slave_burst_adapter:sink0_valid
wire [128:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> jtag_uart_avalon_jtag_slave_burst_adapter:sink0_data
wire cmd_mux_001_src_ready; // jtag_uart_avalon_jtag_slave_burst_adapter:sink0_ready -> cmd_mux_001:src_ready
wire [5:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> jtag_uart_avalon_jtag_slave_burst_adapter:sink0_channel
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> jtag_uart_avalon_jtag_slave_burst_adapter:sink0_startofpacket
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> jtag_uart_avalon_jtag_slave_burst_adapter:sink0_endofpacket
wire jtag_uart_avalon_jtag_slave_burst_adapter_source0_valid; // jtag_uart_avalon_jtag_slave_burst_adapter:source0_valid -> jtag_uart_avalon_jtag_slave_agent:cp_valid
wire [128:0] jtag_uart_avalon_jtag_slave_burst_adapter_source0_data; // jtag_uart_avalon_jtag_slave_burst_adapter:source0_data -> jtag_uart_avalon_jtag_slave_agent:cp_data
wire jtag_uart_avalon_jtag_slave_burst_adapter_source0_ready; // jtag_uart_avalon_jtag_slave_agent:cp_ready -> jtag_uart_avalon_jtag_slave_burst_adapter:source0_ready
wire [5:0] jtag_uart_avalon_jtag_slave_burst_adapter_source0_channel; // jtag_uart_avalon_jtag_slave_burst_adapter:source0_channel -> jtag_uart_avalon_jtag_slave_agent:cp_channel
wire jtag_uart_avalon_jtag_slave_burst_adapter_source0_startofpacket; // jtag_uart_avalon_jtag_slave_burst_adapter:source0_startofpacket -> jtag_uart_avalon_jtag_slave_agent:cp_startofpacket
wire jtag_uart_avalon_jtag_slave_burst_adapter_source0_endofpacket; // jtag_uart_avalon_jtag_slave_burst_adapter:source0_endofpacket -> jtag_uart_avalon_jtag_slave_agent:cp_endofpacket
wire cmd_mux_003_src_valid; // cmd_mux_003:src_valid -> sysid_qsys_control_slave_burst_adapter:sink0_valid
wire [128:0] cmd_mux_003_src_data; // cmd_mux_003:src_data -> sysid_qsys_control_slave_burst_adapter:sink0_data
wire cmd_mux_003_src_ready; // sysid_qsys_control_slave_burst_adapter:sink0_ready -> cmd_mux_003:src_ready
wire [5:0] cmd_mux_003_src_channel; // cmd_mux_003:src_channel -> sysid_qsys_control_slave_burst_adapter:sink0_channel
wire cmd_mux_003_src_startofpacket; // cmd_mux_003:src_startofpacket -> sysid_qsys_control_slave_burst_adapter:sink0_startofpacket
wire cmd_mux_003_src_endofpacket; // cmd_mux_003:src_endofpacket -> sysid_qsys_control_slave_burst_adapter:sink0_endofpacket
wire sysid_qsys_control_slave_burst_adapter_source0_valid; // sysid_qsys_control_slave_burst_adapter:source0_valid -> sysid_qsys_control_slave_agent:cp_valid
wire [128:0] sysid_qsys_control_slave_burst_adapter_source0_data; // sysid_qsys_control_slave_burst_adapter:source0_data -> sysid_qsys_control_slave_agent:cp_data
wire sysid_qsys_control_slave_burst_adapter_source0_ready; // sysid_qsys_control_slave_agent:cp_ready -> sysid_qsys_control_slave_burst_adapter:source0_ready
wire [5:0] sysid_qsys_control_slave_burst_adapter_source0_channel; // sysid_qsys_control_slave_burst_adapter:source0_channel -> sysid_qsys_control_slave_agent:cp_channel
wire sysid_qsys_control_slave_burst_adapter_source0_startofpacket; // sysid_qsys_control_slave_burst_adapter:source0_startofpacket -> sysid_qsys_control_slave_agent:cp_startofpacket
wire sysid_qsys_control_slave_burst_adapter_source0_endofpacket; // sysid_qsys_control_slave_burst_adapter:source0_endofpacket -> sysid_qsys_control_slave_agent:cp_endofpacket
wire cmd_mux_004_src_valid; // cmd_mux_004:src_valid -> reg32_avalon_interface_0_avalon_slave_0_burst_adapter:sink0_valid
wire [128:0] cmd_mux_004_src_data; // cmd_mux_004:src_data -> reg32_avalon_interface_0_avalon_slave_0_burst_adapter:sink0_data
wire cmd_mux_004_src_ready; // reg32_avalon_interface_0_avalon_slave_0_burst_adapter:sink0_ready -> cmd_mux_004:src_ready
wire [5:0] cmd_mux_004_src_channel; // cmd_mux_004:src_channel -> reg32_avalon_interface_0_avalon_slave_0_burst_adapter:sink0_channel
wire cmd_mux_004_src_startofpacket; // cmd_mux_004:src_startofpacket -> reg32_avalon_interface_0_avalon_slave_0_burst_adapter:sink0_startofpacket
wire cmd_mux_004_src_endofpacket; // cmd_mux_004:src_endofpacket -> reg32_avalon_interface_0_avalon_slave_0_burst_adapter:sink0_endofpacket
wire reg32_avalon_interface_0_avalon_slave_0_burst_adapter_source0_valid; // reg32_avalon_interface_0_avalon_slave_0_burst_adapter:source0_valid -> reg32_avalon_interface_0_avalon_slave_0_agent:cp_valid
wire [128:0] reg32_avalon_interface_0_avalon_slave_0_burst_adapter_source0_data; // reg32_avalon_interface_0_avalon_slave_0_burst_adapter:source0_data -> reg32_avalon_interface_0_avalon_slave_0_agent:cp_data
wire reg32_avalon_interface_0_avalon_slave_0_burst_adapter_source0_ready; // reg32_avalon_interface_0_avalon_slave_0_agent:cp_ready -> reg32_avalon_interface_0_avalon_slave_0_burst_adapter:source0_ready
wire [5:0] reg32_avalon_interface_0_avalon_slave_0_burst_adapter_source0_channel; // reg32_avalon_interface_0_avalon_slave_0_burst_adapter:source0_channel -> reg32_avalon_interface_0_avalon_slave_0_agent:cp_channel
wire reg32_avalon_interface_0_avalon_slave_0_burst_adapter_source0_startofpacket; // reg32_avalon_interface_0_avalon_slave_0_burst_adapter:source0_startofpacket -> reg32_avalon_interface_0_avalon_slave_0_agent:cp_startofpacket
wire reg32_avalon_interface_0_avalon_slave_0_burst_adapter_source0_endofpacket; // reg32_avalon_interface_0_avalon_slave_0_burst_adapter:source0_endofpacket -> reg32_avalon_interface_0_avalon_slave_0_agent:cp_endofpacket
wire cmd_mux_005_src_valid; // cmd_mux_005:src_valid -> rc4_avalon_interface_0_avalon_slave_0_burst_adapter:sink0_valid
wire [128:0] cmd_mux_005_src_data; // cmd_mux_005:src_data -> rc4_avalon_interface_0_avalon_slave_0_burst_adapter:sink0_data
wire cmd_mux_005_src_ready; // rc4_avalon_interface_0_avalon_slave_0_burst_adapter:sink0_ready -> cmd_mux_005:src_ready
wire [5:0] cmd_mux_005_src_channel; // cmd_mux_005:src_channel -> rc4_avalon_interface_0_avalon_slave_0_burst_adapter:sink0_channel
wire cmd_mux_005_src_startofpacket; // cmd_mux_005:src_startofpacket -> rc4_avalon_interface_0_avalon_slave_0_burst_adapter:sink0_startofpacket
wire cmd_mux_005_src_endofpacket; // cmd_mux_005:src_endofpacket -> rc4_avalon_interface_0_avalon_slave_0_burst_adapter:sink0_endofpacket
wire rc4_avalon_interface_0_avalon_slave_0_burst_adapter_source0_valid; // rc4_avalon_interface_0_avalon_slave_0_burst_adapter:source0_valid -> rc4_avalon_interface_0_avalon_slave_0_agent:cp_valid
wire [128:0] rc4_avalon_interface_0_avalon_slave_0_burst_adapter_source0_data; // rc4_avalon_interface_0_avalon_slave_0_burst_adapter:source0_data -> rc4_avalon_interface_0_avalon_slave_0_agent:cp_data
wire rc4_avalon_interface_0_avalon_slave_0_burst_adapter_source0_ready; // rc4_avalon_interface_0_avalon_slave_0_agent:cp_ready -> rc4_avalon_interface_0_avalon_slave_0_burst_adapter:source0_ready
wire [5:0] rc4_avalon_interface_0_avalon_slave_0_burst_adapter_source0_channel; // rc4_avalon_interface_0_avalon_slave_0_burst_adapter:source0_channel -> rc4_avalon_interface_0_avalon_slave_0_agent:cp_channel
wire rc4_avalon_interface_0_avalon_slave_0_burst_adapter_source0_startofpacket; // rc4_avalon_interface_0_avalon_slave_0_burst_adapter:source0_startofpacket -> rc4_avalon_interface_0_avalon_slave_0_agent:cp_startofpacket
wire rc4_avalon_interface_0_avalon_slave_0_burst_adapter_source0_endofpacket; // rc4_avalon_interface_0_avalon_slave_0_burst_adapter:source0_endofpacket -> rc4_avalon_interface_0_avalon_slave_0_agent:cp_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire [164:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire [5:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux:sink1_valid
wire [164:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux:sink1_data
wire cmd_demux_001_src0_ready; // cmd_mux:sink1_ready -> cmd_demux_001:src0_ready
wire [5:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux:sink1_channel
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux:sink1_startofpacket
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux:sink1_endofpacket
wire cmd_demux_002_src1_valid; // cmd_demux_002:src1_valid -> cmd_mux_001:sink0_valid
wire [128:0] cmd_demux_002_src1_data; // cmd_demux_002:src1_data -> cmd_mux_001:sink0_data
wire cmd_demux_002_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux_002:src1_ready
wire [5:0] cmd_demux_002_src1_channel; // cmd_demux_002:src1_channel -> cmd_mux_001:sink0_channel
wire cmd_demux_002_src1_startofpacket; // cmd_demux_002:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
wire cmd_demux_002_src1_endofpacket; // cmd_demux_002:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
wire cmd_demux_002_src2_valid; // cmd_demux_002:src2_valid -> cmd_mux_002:sink0_valid
wire [128:0] cmd_demux_002_src2_data; // cmd_demux_002:src2_data -> cmd_mux_002:sink0_data
wire cmd_demux_002_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux_002:src2_ready
wire [5:0] cmd_demux_002_src2_channel; // cmd_demux_002:src2_channel -> cmd_mux_002:sink0_channel
wire cmd_demux_002_src2_startofpacket; // cmd_demux_002:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
wire cmd_demux_002_src2_endofpacket; // cmd_demux_002:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
wire cmd_demux_002_src3_valid; // cmd_demux_002:src3_valid -> cmd_mux_003:sink0_valid
wire [128:0] cmd_demux_002_src3_data; // cmd_demux_002:src3_data -> cmd_mux_003:sink0_data
wire cmd_demux_002_src3_ready; // cmd_mux_003:sink0_ready -> cmd_demux_002:src3_ready
wire [5:0] cmd_demux_002_src3_channel; // cmd_demux_002:src3_channel -> cmd_mux_003:sink0_channel
wire cmd_demux_002_src3_startofpacket; // cmd_demux_002:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
wire cmd_demux_002_src3_endofpacket; // cmd_demux_002:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
wire cmd_demux_003_src0_valid; // cmd_demux_003:src0_valid -> cmd_mux_001:sink1_valid
wire [128:0] cmd_demux_003_src0_data; // cmd_demux_003:src0_data -> cmd_mux_001:sink1_data
wire cmd_demux_003_src0_ready; // cmd_mux_001:sink1_ready -> cmd_demux_003:src0_ready
wire [5:0] cmd_demux_003_src0_channel; // cmd_demux_003:src0_channel -> cmd_mux_001:sink1_channel
wire cmd_demux_003_src0_startofpacket; // cmd_demux_003:src0_startofpacket -> cmd_mux_001:sink1_startofpacket
wire cmd_demux_003_src0_endofpacket; // cmd_demux_003:src0_endofpacket -> cmd_mux_001:sink1_endofpacket
wire cmd_demux_003_src1_valid; // cmd_demux_003:src1_valid -> cmd_mux_003:sink1_valid
wire [128:0] cmd_demux_003_src1_data; // cmd_demux_003:src1_data -> cmd_mux_003:sink1_data
wire cmd_demux_003_src1_ready; // cmd_mux_003:sink1_ready -> cmd_demux_003:src1_ready
wire [5:0] cmd_demux_003_src1_channel; // cmd_demux_003:src1_channel -> cmd_mux_003:sink1_channel
wire cmd_demux_003_src1_startofpacket; // cmd_demux_003:src1_startofpacket -> cmd_mux_003:sink1_startofpacket
wire cmd_demux_003_src1_endofpacket; // cmd_demux_003:src1_endofpacket -> cmd_mux_003:sink1_endofpacket
wire cmd_demux_003_src2_valid; // cmd_demux_003:src2_valid -> cmd_mux_004:sink0_valid
wire [128:0] cmd_demux_003_src2_data; // cmd_demux_003:src2_data -> cmd_mux_004:sink0_data
wire cmd_demux_003_src2_ready; // cmd_mux_004:sink0_ready -> cmd_demux_003:src2_ready
wire [5:0] cmd_demux_003_src2_channel; // cmd_demux_003:src2_channel -> cmd_mux_004:sink0_channel
wire cmd_demux_003_src2_startofpacket; // cmd_demux_003:src2_startofpacket -> cmd_mux_004:sink0_startofpacket
wire cmd_demux_003_src2_endofpacket; // cmd_demux_003:src2_endofpacket -> cmd_mux_004:sink0_endofpacket
wire cmd_demux_003_src3_valid; // cmd_demux_003:src3_valid -> cmd_mux_005:sink0_valid
wire [128:0] cmd_demux_003_src3_data; // cmd_demux_003:src3_data -> cmd_mux_005:sink0_data
wire cmd_demux_003_src3_ready; // cmd_mux_005:sink0_ready -> cmd_demux_003:src3_ready
wire [5:0] cmd_demux_003_src3_channel; // cmd_demux_003:src3_channel -> cmd_mux_005:sink0_channel
wire cmd_demux_003_src3_startofpacket; // cmd_demux_003:src3_startofpacket -> cmd_mux_005:sink0_startofpacket
wire cmd_demux_003_src3_endofpacket; // cmd_demux_003:src3_endofpacket -> cmd_mux_005:sink0_endofpacket
wire cmd_demux_004_src0_valid; // cmd_demux_004:src0_valid -> cmd_mux_001:sink2_valid
wire [128:0] cmd_demux_004_src0_data; // cmd_demux_004:src0_data -> cmd_mux_001:sink2_data
wire cmd_demux_004_src0_ready; // cmd_mux_001:sink2_ready -> cmd_demux_004:src0_ready
wire [5:0] cmd_demux_004_src0_channel; // cmd_demux_004:src0_channel -> cmd_mux_001:sink2_channel
wire cmd_demux_004_src0_startofpacket; // cmd_demux_004:src0_startofpacket -> cmd_mux_001:sink2_startofpacket
wire cmd_demux_004_src0_endofpacket; // cmd_demux_004:src0_endofpacket -> cmd_mux_001:sink2_endofpacket
wire cmd_demux_004_src1_valid; // cmd_demux_004:src1_valid -> cmd_mux_003:sink2_valid
wire [128:0] cmd_demux_004_src1_data; // cmd_demux_004:src1_data -> cmd_mux_003:sink2_data
wire cmd_demux_004_src1_ready; // cmd_mux_003:sink2_ready -> cmd_demux_004:src1_ready
wire [5:0] cmd_demux_004_src1_channel; // cmd_demux_004:src1_channel -> cmd_mux_003:sink2_channel
wire cmd_demux_004_src1_startofpacket; // cmd_demux_004:src1_startofpacket -> cmd_mux_003:sink2_startofpacket
wire cmd_demux_004_src1_endofpacket; // cmd_demux_004:src1_endofpacket -> cmd_mux_003:sink2_endofpacket
wire cmd_demux_004_src2_valid; // cmd_demux_004:src2_valid -> cmd_mux_004:sink1_valid
wire [128:0] cmd_demux_004_src2_data; // cmd_demux_004:src2_data -> cmd_mux_004:sink1_data
wire cmd_demux_004_src2_ready; // cmd_mux_004:sink1_ready -> cmd_demux_004:src2_ready
wire [5:0] cmd_demux_004_src2_channel; // cmd_demux_004:src2_channel -> cmd_mux_004:sink1_channel
wire cmd_demux_004_src2_startofpacket; // cmd_demux_004:src2_startofpacket -> cmd_mux_004:sink1_startofpacket
wire cmd_demux_004_src2_endofpacket; // cmd_demux_004:src2_endofpacket -> cmd_mux_004:sink1_endofpacket
wire cmd_demux_004_src3_valid; // cmd_demux_004:src3_valid -> cmd_mux_005:sink1_valid
wire [128:0] cmd_demux_004_src3_data; // cmd_demux_004:src3_data -> cmd_mux_005:sink1_data
wire cmd_demux_004_src3_ready; // cmd_mux_005:sink1_ready -> cmd_demux_004:src3_ready
wire [5:0] cmd_demux_004_src3_channel; // cmd_demux_004:src3_channel -> cmd_mux_005:sink1_channel
wire cmd_demux_004_src3_startofpacket; // cmd_demux_004:src3_startofpacket -> cmd_mux_005:sink1_startofpacket
wire cmd_demux_004_src3_endofpacket; // cmd_demux_004:src3_endofpacket -> cmd_mux_005:sink1_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire [164:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire [5:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_src1_valid; // rsp_demux:src1_valid -> rsp_mux_001:sink0_valid
wire [164:0] rsp_demux_src1_data; // rsp_demux:src1_data -> rsp_mux_001:sink0_data
wire rsp_demux_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux:src1_ready
wire [5:0] rsp_demux_src1_channel; // rsp_demux:src1_channel -> rsp_mux_001:sink0_channel
wire rsp_demux_src1_startofpacket; // rsp_demux:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
wire rsp_demux_src1_endofpacket; // rsp_demux:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux_002:sink1_valid
wire [128:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux_002:sink1_data
wire rsp_demux_001_src0_ready; // rsp_mux_002:sink1_ready -> rsp_demux_001:src0_ready
wire [5:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux_002:sink1_channel
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux_002:sink1_startofpacket
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux_002:sink1_endofpacket
wire rsp_demux_001_src1_valid; // rsp_demux_001:src1_valid -> rsp_mux_003:sink0_valid
wire [128:0] rsp_demux_001_src1_data; // rsp_demux_001:src1_data -> rsp_mux_003:sink0_data
wire rsp_demux_001_src1_ready; // rsp_mux_003:sink0_ready -> rsp_demux_001:src1_ready
wire [5:0] rsp_demux_001_src1_channel; // rsp_demux_001:src1_channel -> rsp_mux_003:sink0_channel
wire rsp_demux_001_src1_startofpacket; // rsp_demux_001:src1_startofpacket -> rsp_mux_003:sink0_startofpacket
wire rsp_demux_001_src1_endofpacket; // rsp_demux_001:src1_endofpacket -> rsp_mux_003:sink0_endofpacket
wire rsp_demux_001_src2_valid; // rsp_demux_001:src2_valid -> rsp_mux_004:sink0_valid
wire [128:0] rsp_demux_001_src2_data; // rsp_demux_001:src2_data -> rsp_mux_004:sink0_data
wire rsp_demux_001_src2_ready; // rsp_mux_004:sink0_ready -> rsp_demux_001:src2_ready
wire [5:0] rsp_demux_001_src2_channel; // rsp_demux_001:src2_channel -> rsp_mux_004:sink0_channel
wire rsp_demux_001_src2_startofpacket; // rsp_demux_001:src2_startofpacket -> rsp_mux_004:sink0_startofpacket
wire rsp_demux_001_src2_endofpacket; // rsp_demux_001:src2_endofpacket -> rsp_mux_004:sink0_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux_002:sink2_valid
wire [128:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux_002:sink2_data
wire rsp_demux_002_src0_ready; // rsp_mux_002:sink2_ready -> rsp_demux_002:src0_ready
wire [5:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux_002:sink2_channel
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux_002:sink2_startofpacket
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux_002:sink2_endofpacket
wire rsp_demux_003_src0_valid; // rsp_demux_003:src0_valid -> rsp_mux_002:sink3_valid
wire [128:0] rsp_demux_003_src0_data; // rsp_demux_003:src0_data -> rsp_mux_002:sink3_data
wire rsp_demux_003_src0_ready; // rsp_mux_002:sink3_ready -> rsp_demux_003:src0_ready
wire [5:0] rsp_demux_003_src0_channel; // rsp_demux_003:src0_channel -> rsp_mux_002:sink3_channel
wire rsp_demux_003_src0_startofpacket; // rsp_demux_003:src0_startofpacket -> rsp_mux_002:sink3_startofpacket
wire rsp_demux_003_src0_endofpacket; // rsp_demux_003:src0_endofpacket -> rsp_mux_002:sink3_endofpacket
wire rsp_demux_003_src1_valid; // rsp_demux_003:src1_valid -> rsp_mux_003:sink1_valid
wire [128:0] rsp_demux_003_src1_data; // rsp_demux_003:src1_data -> rsp_mux_003:sink1_data
wire rsp_demux_003_src1_ready; // rsp_mux_003:sink1_ready -> rsp_demux_003:src1_ready
wire [5:0] rsp_demux_003_src1_channel; // rsp_demux_003:src1_channel -> rsp_mux_003:sink1_channel
wire rsp_demux_003_src1_startofpacket; // rsp_demux_003:src1_startofpacket -> rsp_mux_003:sink1_startofpacket
wire rsp_demux_003_src1_endofpacket; // rsp_demux_003:src1_endofpacket -> rsp_mux_003:sink1_endofpacket
wire rsp_demux_003_src2_valid; // rsp_demux_003:src2_valid -> rsp_mux_004:sink1_valid
wire [128:0] rsp_demux_003_src2_data; // rsp_demux_003:src2_data -> rsp_mux_004:sink1_data
wire rsp_demux_003_src2_ready; // rsp_mux_004:sink1_ready -> rsp_demux_003:src2_ready
wire [5:0] rsp_demux_003_src2_channel; // rsp_demux_003:src2_channel -> rsp_mux_004:sink1_channel
wire rsp_demux_003_src2_startofpacket; // rsp_demux_003:src2_startofpacket -> rsp_mux_004:sink1_startofpacket
wire rsp_demux_003_src2_endofpacket; // rsp_demux_003:src2_endofpacket -> rsp_mux_004:sink1_endofpacket
wire rsp_demux_004_src0_valid; // rsp_demux_004:src0_valid -> rsp_mux_003:sink2_valid
wire [128:0] rsp_demux_004_src0_data; // rsp_demux_004:src0_data -> rsp_mux_003:sink2_data
wire rsp_demux_004_src0_ready; // rsp_mux_003:sink2_ready -> rsp_demux_004:src0_ready
wire [5:0] rsp_demux_004_src0_channel; // rsp_demux_004:src0_channel -> rsp_mux_003:sink2_channel
wire rsp_demux_004_src0_startofpacket; // rsp_demux_004:src0_startofpacket -> rsp_mux_003:sink2_startofpacket
wire rsp_demux_004_src0_endofpacket; // rsp_demux_004:src0_endofpacket -> rsp_mux_003:sink2_endofpacket
wire rsp_demux_004_src1_valid; // rsp_demux_004:src1_valid -> rsp_mux_004:sink2_valid
wire [128:0] rsp_demux_004_src1_data; // rsp_demux_004:src1_data -> rsp_mux_004:sink2_data
wire rsp_demux_004_src1_ready; // rsp_mux_004:sink2_ready -> rsp_demux_004:src1_ready
wire [5:0] rsp_demux_004_src1_channel; // rsp_demux_004:src1_channel -> rsp_mux_004:sink2_channel
wire rsp_demux_004_src1_startofpacket; // rsp_demux_004:src1_startofpacket -> rsp_mux_004:sink2_startofpacket
wire rsp_demux_004_src1_endofpacket; // rsp_demux_004:src1_endofpacket -> rsp_mux_004:sink2_endofpacket
wire rsp_demux_005_src0_valid; // rsp_demux_005:src0_valid -> rsp_mux_003:sink3_valid
wire [128:0] rsp_demux_005_src0_data; // rsp_demux_005:src0_data -> rsp_mux_003:sink3_data
wire rsp_demux_005_src0_ready; // rsp_mux_003:sink3_ready -> rsp_demux_005:src0_ready
wire [5:0] rsp_demux_005_src0_channel; // rsp_demux_005:src0_channel -> rsp_mux_003:sink3_channel
wire rsp_demux_005_src0_startofpacket; // rsp_demux_005:src0_startofpacket -> rsp_mux_003:sink3_startofpacket
wire rsp_demux_005_src0_endofpacket; // rsp_demux_005:src0_endofpacket -> rsp_mux_003:sink3_endofpacket
wire rsp_demux_005_src1_valid; // rsp_demux_005:src1_valid -> rsp_mux_004:sink3_valid
wire [128:0] rsp_demux_005_src1_data; // rsp_demux_005:src1_data -> rsp_mux_004:sink3_data
wire rsp_demux_005_src1_ready; // rsp_mux_004:sink3_ready -> rsp_demux_005:src1_ready
wire [5:0] rsp_demux_005_src1_channel; // rsp_demux_005:src1_channel -> rsp_mux_004:sink3_channel
wire rsp_demux_005_src1_startofpacket; // rsp_demux_005:src1_startofpacket -> rsp_mux_004:sink3_startofpacket
wire rsp_demux_005_src1_endofpacket; // rsp_demux_005:src1_endofpacket -> rsp_mux_004:sink3_endofpacket
wire cmd_demux_002_src0_valid; // cmd_demux_002:src0_valid -> fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter:in_valid
wire [128:0] cmd_demux_002_src0_data; // cmd_demux_002:src0_data -> fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter:in_data
wire cmd_demux_002_src0_ready; // fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter:in_ready -> cmd_demux_002:src0_ready
wire [5:0] cmd_demux_002_src0_channel; // cmd_demux_002:src0_channel -> fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter:in_channel
wire cmd_demux_002_src0_startofpacket; // cmd_demux_002:src0_startofpacket -> fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter:in_startofpacket
wire cmd_demux_002_src0_endofpacket; // cmd_demux_002:src0_endofpacket -> fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter:in_endofpacket
wire fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_valid; // fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter:out_valid -> cmd_mux:sink2_valid
wire [164:0] fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_data; // fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter:out_data -> cmd_mux:sink2_data
wire fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_ready; // cmd_mux:sink2_ready -> fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter:out_ready
wire [5:0] fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_channel; // fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter:out_channel -> cmd_mux:sink2_channel
wire fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_startofpacket; // fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter:out_startofpacket -> cmd_mux:sink2_startofpacket
wire fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_endofpacket; // fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter:out_endofpacket -> cmd_mux:sink2_endofpacket
wire rsp_demux_src2_valid; // rsp_demux:src2_valid -> onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter:in_valid
wire [164:0] rsp_demux_src2_data; // rsp_demux:src2_data -> onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter:in_data
wire rsp_demux_src2_ready; // onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter:in_ready -> rsp_demux:src2_ready
wire [5:0] rsp_demux_src2_channel; // rsp_demux:src2_channel -> onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter:in_channel
wire rsp_demux_src2_startofpacket; // rsp_demux:src2_startofpacket -> onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter:in_startofpacket
wire rsp_demux_src2_endofpacket; // rsp_demux:src2_endofpacket -> onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter:in_endofpacket
wire onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_valid; // onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter:out_valid -> rsp_mux_002:sink0_valid
wire [128:0] onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_data; // onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter:out_data -> rsp_mux_002:sink0_data
wire onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_ready; // rsp_mux_002:sink0_ready -> onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter:out_ready
wire [5:0] onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_channel; // onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter:out_channel -> rsp_mux_002:sink0_channel
wire onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_startofpacket; // onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter:out_startofpacket -> rsp_mux_002:sink0_startofpacket
wire onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_endofpacket; // onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter:out_endofpacket -> rsp_mux_002:sink0_endofpacket
wire [5:0] fpga_only_master_master_limiter_cmd_valid_data; // fpga_only_master_master_limiter:cmd_src_valid -> cmd_demux_002:sink_valid
wire [5:0] hps_0_h2f_lw_axi_master_wr_limiter_cmd_valid_data; // hps_0_h2f_lw_axi_master_wr_limiter:cmd_src_valid -> cmd_demux_003:sink_valid
wire [5:0] hps_0_h2f_lw_axi_master_rd_limiter_cmd_valid_data; // hps_0_h2f_lw_axi_master_rd_limiter:cmd_src_valid -> cmd_demux_004:sink_valid
wire onchip_memory2_0_s1_agent_rdata_fifo_out_valid; // onchip_memory2_0_s1_agent_rdata_fifo:out_valid -> avalon_st_adapter:in_0_valid
wire [65:0] onchip_memory2_0_s1_agent_rdata_fifo_out_data; // onchip_memory2_0_s1_agent_rdata_fifo:out_data -> avalon_st_adapter:in_0_data
wire onchip_memory2_0_s1_agent_rdata_fifo_out_ready; // avalon_st_adapter:in_0_ready -> onchip_memory2_0_s1_agent_rdata_fifo:out_ready
wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> onchip_memory2_0_s1_agent:rdata_fifo_sink_valid
wire [65:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> onchip_memory2_0_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_out_0_ready; // onchip_memory2_0_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> onchip_memory2_0_s1_agent:rdata_fifo_sink_error
wire jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_valid; // jtag_uart_avalon_jtag_slave_agent_rdata_fifo:out_valid -> avalon_st_adapter_001:in_0_valid
wire [33:0] jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_data; // jtag_uart_avalon_jtag_slave_agent_rdata_fifo:out_data -> avalon_st_adapter_001:in_0_data
wire jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_ready; // avalon_st_adapter_001:in_0_ready -> jtag_uart_avalon_jtag_slave_agent_rdata_fifo:out_ready
wire avalon_st_adapter_001_out_0_valid; // avalon_st_adapter_001:out_0_valid -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_001_out_0_data; // avalon_st_adapter_001:out_0_data -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_data
wire avalon_st_adapter_001_out_0_ready; // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready
wire [0:0] avalon_st_adapter_001_out_0_error; // avalon_st_adapter_001:out_0_error -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_error
wire intr_capturer_0_avalon_slave_0_agent_rdata_fifo_out_valid; // intr_capturer_0_avalon_slave_0_agent_rdata_fifo:out_valid -> avalon_st_adapter_002:in_0_valid
wire [33:0] intr_capturer_0_avalon_slave_0_agent_rdata_fifo_out_data; // intr_capturer_0_avalon_slave_0_agent_rdata_fifo:out_data -> avalon_st_adapter_002:in_0_data
wire intr_capturer_0_avalon_slave_0_agent_rdata_fifo_out_ready; // avalon_st_adapter_002:in_0_ready -> intr_capturer_0_avalon_slave_0_agent_rdata_fifo:out_ready
wire avalon_st_adapter_002_out_0_valid; // avalon_st_adapter_002:out_0_valid -> intr_capturer_0_avalon_slave_0_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_002_out_0_data; // avalon_st_adapter_002:out_0_data -> intr_capturer_0_avalon_slave_0_agent:rdata_fifo_sink_data
wire avalon_st_adapter_002_out_0_ready; // intr_capturer_0_avalon_slave_0_agent:rdata_fifo_sink_ready -> avalon_st_adapter_002:out_0_ready
wire [0:0] avalon_st_adapter_002_out_0_error; // avalon_st_adapter_002:out_0_error -> intr_capturer_0_avalon_slave_0_agent:rdata_fifo_sink_error
wire sysid_qsys_control_slave_agent_rdata_fifo_out_valid; // sysid_qsys_control_slave_agent_rdata_fifo:out_valid -> avalon_st_adapter_003:in_0_valid
wire [33:0] sysid_qsys_control_slave_agent_rdata_fifo_out_data; // sysid_qsys_control_slave_agent_rdata_fifo:out_data -> avalon_st_adapter_003:in_0_data
wire sysid_qsys_control_slave_agent_rdata_fifo_out_ready; // avalon_st_adapter_003:in_0_ready -> sysid_qsys_control_slave_agent_rdata_fifo:out_ready
wire avalon_st_adapter_003_out_0_valid; // avalon_st_adapter_003:out_0_valid -> sysid_qsys_control_slave_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_003_out_0_data; // avalon_st_adapter_003:out_0_data -> sysid_qsys_control_slave_agent:rdata_fifo_sink_data
wire avalon_st_adapter_003_out_0_ready; // sysid_qsys_control_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_003:out_0_ready
wire [0:0] avalon_st_adapter_003_out_0_error; // avalon_st_adapter_003:out_0_error -> sysid_qsys_control_slave_agent:rdata_fifo_sink_error
wire reg32_avalon_interface_0_avalon_slave_0_agent_rdata_fifo_out_valid; // reg32_avalon_interface_0_avalon_slave_0_agent_rdata_fifo:out_valid -> avalon_st_adapter_004:in_0_valid
wire [33:0] reg32_avalon_interface_0_avalon_slave_0_agent_rdata_fifo_out_data; // reg32_avalon_interface_0_avalon_slave_0_agent_rdata_fifo:out_data -> avalon_st_adapter_004:in_0_data
wire reg32_avalon_interface_0_avalon_slave_0_agent_rdata_fifo_out_ready; // avalon_st_adapter_004:in_0_ready -> reg32_avalon_interface_0_avalon_slave_0_agent_rdata_fifo:out_ready
wire avalon_st_adapter_004_out_0_valid; // avalon_st_adapter_004:out_0_valid -> reg32_avalon_interface_0_avalon_slave_0_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_004_out_0_data; // avalon_st_adapter_004:out_0_data -> reg32_avalon_interface_0_avalon_slave_0_agent:rdata_fifo_sink_data
wire avalon_st_adapter_004_out_0_ready; // reg32_avalon_interface_0_avalon_slave_0_agent:rdata_fifo_sink_ready -> avalon_st_adapter_004:out_0_ready
wire [0:0] avalon_st_adapter_004_out_0_error; // avalon_st_adapter_004:out_0_error -> reg32_avalon_interface_0_avalon_slave_0_agent:rdata_fifo_sink_error
wire rc4_avalon_interface_0_avalon_slave_0_agent_rdata_fifo_out_valid; // rc4_avalon_interface_0_avalon_slave_0_agent_rdata_fifo:out_valid -> avalon_st_adapter_005:in_0_valid
wire [33:0] rc4_avalon_interface_0_avalon_slave_0_agent_rdata_fifo_out_data; // rc4_avalon_interface_0_avalon_slave_0_agent_rdata_fifo:out_data -> avalon_st_adapter_005:in_0_data
wire rc4_avalon_interface_0_avalon_slave_0_agent_rdata_fifo_out_ready; // avalon_st_adapter_005:in_0_ready -> rc4_avalon_interface_0_avalon_slave_0_agent_rdata_fifo:out_ready
wire avalon_st_adapter_005_out_0_valid; // avalon_st_adapter_005:out_0_valid -> rc4_avalon_interface_0_avalon_slave_0_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_005_out_0_data; // avalon_st_adapter_005:out_0_data -> rc4_avalon_interface_0_avalon_slave_0_agent:rdata_fifo_sink_data
wire avalon_st_adapter_005_out_0_ready; // rc4_avalon_interface_0_avalon_slave_0_agent:rdata_fifo_sink_ready -> avalon_st_adapter_005:out_0_ready
wire [0:0] avalon_st_adapter_005_out_0_error; // avalon_st_adapter_005:out_0_error -> rc4_avalon_interface_0_avalon_slave_0_agent:rdata_fifo_sink_error
altera_merlin_master_translator #(
.AV_ADDRESS_W (32),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) fpga_only_master_master_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // reset.reset
.uav_address (fpga_only_master_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (fpga_only_master_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (fpga_only_master_master_translator_avalon_universal_master_0_read), // .read
.uav_write (fpga_only_master_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (fpga_only_master_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (fpga_only_master_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (fpga_only_master_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (fpga_only_master_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (fpga_only_master_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (fpga_only_master_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (fpga_only_master_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (fpga_only_master_master_address), // avalon_anti_master_0.address
.av_waitrequest (fpga_only_master_master_waitrequest), // .waitrequest
.av_byteenable (fpga_only_master_master_byteenable), // .byteenable
.av_read (fpga_only_master_master_read), // .read
.av_readdata (fpga_only_master_master_readdata), // .readdata
.av_readdatavalid (fpga_only_master_master_readdatavalid), // .readdatavalid
.av_write (fpga_only_master_master_write), // .write
.av_writedata (fpga_only_master_master_writedata), // .writedata
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (13),
.AV_DATA_W (64),
.UAV_DATA_W (64),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (8),
.UAV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (4),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) onchip_memory2_0_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // reset.reset
.uav_address (onchip_memory2_0_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (onchip_memory2_0_s1_agent_m0_burstcount), // .burstcount
.uav_read (onchip_memory2_0_s1_agent_m0_read), // .read
.uav_write (onchip_memory2_0_s1_agent_m0_write), // .write
.uav_waitrequest (onchip_memory2_0_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (onchip_memory2_0_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (onchip_memory2_0_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (onchip_memory2_0_s1_agent_m0_readdata), // .readdata
.uav_writedata (onchip_memory2_0_s1_agent_m0_writedata), // .writedata
.uav_lock (onchip_memory2_0_s1_agent_m0_lock), // .lock
.uav_debugaccess (onchip_memory2_0_s1_agent_m0_debugaccess), // .debugaccess
.av_address (onchip_memory2_0_s1_address), // avalon_anti_slave_0.address
.av_write (onchip_memory2_0_s1_write), // .write
.av_readdata (onchip_memory2_0_s1_readdata), // .readdata
.av_writedata (onchip_memory2_0_s1_writedata), // .writedata
.av_byteenable (onchip_memory2_0_s1_byteenable), // .byteenable
.av_chipselect (onchip_memory2_0_s1_chipselect), // .chipselect
.av_clken (onchip_memory2_0_s1_clken), // .clken
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) jtag_uart_avalon_jtag_slave_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // reset.reset
.uav_address (jtag_uart_avalon_jtag_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (jtag_uart_avalon_jtag_slave_agent_m0_burstcount), // .burstcount
.uav_read (jtag_uart_avalon_jtag_slave_agent_m0_read), // .read
.uav_write (jtag_uart_avalon_jtag_slave_agent_m0_write), // .write
.uav_waitrequest (jtag_uart_avalon_jtag_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (jtag_uart_avalon_jtag_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (jtag_uart_avalon_jtag_slave_agent_m0_readdata), // .readdata
.uav_writedata (jtag_uart_avalon_jtag_slave_agent_m0_writedata), // .writedata
.uav_lock (jtag_uart_avalon_jtag_slave_agent_m0_lock), // .lock
.uav_debugaccess (jtag_uart_avalon_jtag_slave_agent_m0_debugaccess), // .debugaccess
.av_address (jtag_uart_avalon_jtag_slave_address), // avalon_anti_slave_0.address
.av_write (jtag_uart_avalon_jtag_slave_write), // .write
.av_read (jtag_uart_avalon_jtag_slave_read), // .read
.av_readdata (jtag_uart_avalon_jtag_slave_readdata), // .readdata
.av_writedata (jtag_uart_avalon_jtag_slave_writedata), // .writedata
.av_waitrequest (jtag_uart_avalon_jtag_slave_waitrequest), // .waitrequest
.av_chipselect (jtag_uart_avalon_jtag_slave_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) intr_capturer_0_avalon_slave_0_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // reset.reset
.uav_address (intr_capturer_0_avalon_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (intr_capturer_0_avalon_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (intr_capturer_0_avalon_slave_0_agent_m0_read), // .read
.uav_write (intr_capturer_0_avalon_slave_0_agent_m0_write), // .write
.uav_waitrequest (intr_capturer_0_avalon_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (intr_capturer_0_avalon_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (intr_capturer_0_avalon_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (intr_capturer_0_avalon_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (intr_capturer_0_avalon_slave_0_agent_m0_writedata), // .writedata
.uav_lock (intr_capturer_0_avalon_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (intr_capturer_0_avalon_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (intr_capturer_0_avalon_slave_0_address), // avalon_anti_slave_0.address
.av_read (intr_capturer_0_avalon_slave_0_read), // .read
.av_readdata (intr_capturer_0_avalon_slave_0_readdata), // .readdata
.av_write (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sysid_qsys_control_slave_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sysid_qsys_control_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sysid_qsys_control_slave_agent_m0_burstcount), // .burstcount
.uav_read (sysid_qsys_control_slave_agent_m0_read), // .read
.uav_write (sysid_qsys_control_slave_agent_m0_write), // .write
.uav_waitrequest (sysid_qsys_control_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sysid_qsys_control_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sysid_qsys_control_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (sysid_qsys_control_slave_agent_m0_readdata), // .readdata
.uav_writedata (sysid_qsys_control_slave_agent_m0_writedata), // .writedata
.uav_lock (sysid_qsys_control_slave_agent_m0_lock), // .lock
.uav_debugaccess (sysid_qsys_control_slave_agent_m0_debugaccess), // .debugaccess
.av_address (sysid_qsys_control_slave_address), // avalon_anti_slave_0.address
.av_readdata (sysid_qsys_control_slave_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) reg32_avalon_interface_0_avalon_slave_0_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // reset.reset
.uav_address (reg32_avalon_interface_0_avalon_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (reg32_avalon_interface_0_avalon_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (reg32_avalon_interface_0_avalon_slave_0_agent_m0_read), // .read
.uav_write (reg32_avalon_interface_0_avalon_slave_0_agent_m0_write), // .write
.uav_waitrequest (reg32_avalon_interface_0_avalon_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (reg32_avalon_interface_0_avalon_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (reg32_avalon_interface_0_avalon_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (reg32_avalon_interface_0_avalon_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (reg32_avalon_interface_0_avalon_slave_0_agent_m0_writedata), // .writedata
.uav_lock (reg32_avalon_interface_0_avalon_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (reg32_avalon_interface_0_avalon_slave_0_agent_m0_debugaccess), // .debugaccess
.av_write (reg32_avalon_interface_0_avalon_slave_0_write), // avalon_anti_slave_0.write
.av_read (reg32_avalon_interface_0_avalon_slave_0_read), // .read
.av_readdata (reg32_avalon_interface_0_avalon_slave_0_readdata), // .readdata
.av_writedata (reg32_avalon_interface_0_avalon_slave_0_writedata), // .writedata
.av_byteenable (reg32_avalon_interface_0_avalon_slave_0_byteenable), // .byteenable
.av_chipselect (reg32_avalon_interface_0_avalon_slave_0_chipselect), // .chipselect
.av_address (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) rc4_avalon_interface_0_avalon_slave_0_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // reset.reset
.uav_address (rc4_avalon_interface_0_avalon_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (rc4_avalon_interface_0_avalon_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (rc4_avalon_interface_0_avalon_slave_0_agent_m0_read), // .read
.uav_write (rc4_avalon_interface_0_avalon_slave_0_agent_m0_write), // .write
.uav_waitrequest (rc4_avalon_interface_0_avalon_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (rc4_avalon_interface_0_avalon_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (rc4_avalon_interface_0_avalon_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (rc4_avalon_interface_0_avalon_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (rc4_avalon_interface_0_avalon_slave_0_agent_m0_writedata), // .writedata
.uav_lock (rc4_avalon_interface_0_avalon_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (rc4_avalon_interface_0_avalon_slave_0_agent_m0_debugaccess), // .debugaccess
.av_write (rc4_avalon_interface_0_avalon_slave_0_write), // avalon_anti_slave_0.write
.av_read (rc4_avalon_interface_0_avalon_slave_0_read), // .read
.av_readdata (rc4_avalon_interface_0_avalon_slave_0_readdata), // .readdata
.av_writedata (rc4_avalon_interface_0_avalon_slave_0_writedata), // .writedata
.av_byteenable (rc4_avalon_interface_0_avalon_slave_0_byteenable), // .byteenable
.av_chipselect (rc4_avalon_interface_0_avalon_slave_0_chipselect), // .chipselect
.av_address (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_axi_master_ni #(
.ID_WIDTH (12),
.ADDR_WIDTH (30),
.RDATA_WIDTH (64),
.WDATA_WIDTH (64),
.ADDR_USER_WIDTH (1),
.DATA_USER_WIDTH (1),
.AXI_BURST_LENGTH_WIDTH (4),
.AXI_LOCK_WIDTH (2),
.AXI_VERSION ("AXI3"),
.WRITE_ISSUING_CAPABILITY (8),
.READ_ISSUING_CAPABILITY (8),
.PKT_BEGIN_BURST (133),
.PKT_CACHE_H (159),
.PKT_CACHE_L (156),
.PKT_ADDR_SIDEBAND_H (131),
.PKT_ADDR_SIDEBAND_L (131),
.PKT_PROTECTION_H (155),
.PKT_PROTECTION_L (153),
.PKT_BURST_SIZE_H (128),
.PKT_BURST_SIZE_L (126),
.PKT_BURST_TYPE_H (130),
.PKT_BURST_TYPE_L (129),
.PKT_RESPONSE_STATUS_L (160),
.PKT_RESPONSE_STATUS_H (161),
.PKT_BURSTWRAP_H (125),
.PKT_BURSTWRAP_L (118),
.PKT_BYTE_CNT_H (117),
.PKT_BYTE_CNT_L (110),
.PKT_ADDR_H (103),
.PKT_ADDR_L (72),
.PKT_TRANS_EXCLUSIVE (109),
.PKT_TRANS_LOCK (108),
.PKT_TRANS_COMPRESSED_READ (104),
.PKT_TRANS_POSTED (105),
.PKT_TRANS_WRITE (106),
.PKT_TRANS_READ (107),
.PKT_DATA_H (63),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (71),
.PKT_BYTEEN_L (64),
.PKT_SRC_ID_H (137),
.PKT_SRC_ID_L (135),
.PKT_DEST_ID_H (140),
.PKT_DEST_ID_L (138),
.PKT_THREAD_ID_H (152),
.PKT_THREAD_ID_L (141),
.PKT_QOS_L (134),
.PKT_QOS_H (134),
.PKT_ORI_BURST_SIZE_L (162),
.PKT_ORI_BURST_SIZE_H (164),
.PKT_DATA_SIDEBAND_H (132),
.PKT_DATA_SIDEBAND_L (132),
.ST_DATA_W (165),
.ST_CHANNEL_W (6),
.ID (1)
) hps_0_h2f_axi_master_agent (
.aclk (clk_0_clk_clk), // clk.clk
.aresetn (~hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset_n
.write_cp_valid (hps_0_h2f_axi_master_agent_write_cp_valid), // write_cp.valid
.write_cp_data (hps_0_h2f_axi_master_agent_write_cp_data), // .data
.write_cp_startofpacket (hps_0_h2f_axi_master_agent_write_cp_startofpacket), // .startofpacket
.write_cp_endofpacket (hps_0_h2f_axi_master_agent_write_cp_endofpacket), // .endofpacket
.write_cp_ready (hps_0_h2f_axi_master_agent_write_cp_ready), // .ready
.write_rp_valid (rsp_mux_src_valid), // write_rp.valid
.write_rp_data (rsp_mux_src_data), // .data
.write_rp_channel (rsp_mux_src_channel), // .channel
.write_rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.write_rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.write_rp_ready (rsp_mux_src_ready), // .ready
.read_cp_valid (hps_0_h2f_axi_master_agent_read_cp_valid), // read_cp.valid
.read_cp_data (hps_0_h2f_axi_master_agent_read_cp_data), // .data
.read_cp_startofpacket (hps_0_h2f_axi_master_agent_read_cp_startofpacket), // .startofpacket
.read_cp_endofpacket (hps_0_h2f_axi_master_agent_read_cp_endofpacket), // .endofpacket
.read_cp_ready (hps_0_h2f_axi_master_agent_read_cp_ready), // .ready
.read_rp_valid (rsp_mux_001_src_valid), // read_rp.valid
.read_rp_data (rsp_mux_001_src_data), // .data
.read_rp_channel (rsp_mux_001_src_channel), // .channel
.read_rp_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.read_rp_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.read_rp_ready (rsp_mux_001_src_ready), // .ready
.awid (hps_0_h2f_axi_master_awid), // altera_axi_slave.awid
.awaddr (hps_0_h2f_axi_master_awaddr), // .awaddr
.awlen (hps_0_h2f_axi_master_awlen), // .awlen
.awsize (hps_0_h2f_axi_master_awsize), // .awsize
.awburst (hps_0_h2f_axi_master_awburst), // .awburst
.awlock (hps_0_h2f_axi_master_awlock), // .awlock
.awcache (hps_0_h2f_axi_master_awcache), // .awcache
.awprot (hps_0_h2f_axi_master_awprot), // .awprot
.awvalid (hps_0_h2f_axi_master_awvalid), // .awvalid
.awready (hps_0_h2f_axi_master_awready), // .awready
.wid (hps_0_h2f_axi_master_wid), // .wid
.wdata (hps_0_h2f_axi_master_wdata), // .wdata
.wstrb (hps_0_h2f_axi_master_wstrb), // .wstrb
.wlast (hps_0_h2f_axi_master_wlast), // .wlast
.wvalid (hps_0_h2f_axi_master_wvalid), // .wvalid
.wready (hps_0_h2f_axi_master_wready), // .wready
.bid (hps_0_h2f_axi_master_bid), // .bid
.bresp (hps_0_h2f_axi_master_bresp), // .bresp
.bvalid (hps_0_h2f_axi_master_bvalid), // .bvalid
.bready (hps_0_h2f_axi_master_bready), // .bready
.arid (hps_0_h2f_axi_master_arid), // .arid
.araddr (hps_0_h2f_axi_master_araddr), // .araddr
.arlen (hps_0_h2f_axi_master_arlen), // .arlen
.arsize (hps_0_h2f_axi_master_arsize), // .arsize
.arburst (hps_0_h2f_axi_master_arburst), // .arburst
.arlock (hps_0_h2f_axi_master_arlock), // .arlock
.arcache (hps_0_h2f_axi_master_arcache), // .arcache
.arprot (hps_0_h2f_axi_master_arprot), // .arprot
.arvalid (hps_0_h2f_axi_master_arvalid), // .arvalid
.arready (hps_0_h2f_axi_master_arready), // .arready
.rid (hps_0_h2f_axi_master_rid), // .rid
.rdata (hps_0_h2f_axi_master_rdata), // .rdata
.rresp (hps_0_h2f_axi_master_rresp), // .rresp
.rlast (hps_0_h2f_axi_master_rlast), // .rlast
.rvalid (hps_0_h2f_axi_master_rvalid), // .rvalid
.rready (hps_0_h2f_axi_master_rready), // .rready
.awuser (1'b0), // (terminated)
.aruser (1'b0), // (terminated)
.awqos (4'b0000), // (terminated)
.arqos (4'b0000), // (terminated)
.awregion (4'b0000), // (terminated)
.arregion (4'b0000), // (terminated)
.wuser (1'b0), // (terminated)
.ruser (), // (terminated)
.buser () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (128),
.PKT_ORI_BURST_SIZE_L (126),
.PKT_RESPONSE_STATUS_H (125),
.PKT_RESPONSE_STATUS_L (124),
.PKT_QOS_H (98),
.PKT_QOS_L (98),
.PKT_DATA_SIDEBAND_H (96),
.PKT_DATA_SIDEBAND_L (96),
.PKT_ADDR_SIDEBAND_H (95),
.PKT_ADDR_SIDEBAND_L (95),
.PKT_BURST_TYPE_H (94),
.PKT_BURST_TYPE_L (93),
.PKT_CACHE_H (123),
.PKT_CACHE_L (120),
.PKT_THREAD_ID_H (116),
.PKT_THREAD_ID_L (105),
.PKT_BURST_SIZE_H (92),
.PKT_BURST_SIZE_L (90),
.PKT_TRANS_EXCLUSIVE (73),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (97),
.PKT_PROTECTION_H (119),
.PKT_PROTECTION_L (117),
.PKT_BURSTWRAP_H (89),
.PKT_BURSTWRAP_L (82),
.PKT_BYTE_CNT_H (81),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (101),
.PKT_SRC_ID_L (99),
.PKT_DEST_ID_H (104),
.PKT_DEST_ID_L (102),
.ST_DATA_W (129),
.ST_CHANNEL_W (6),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (1),
.ID (0),
.BURSTWRAP_VALUE (255),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) fpga_only_master_master_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (fpga_only_master_master_translator_avalon_universal_master_0_address), // av.address
.av_write (fpga_only_master_master_translator_avalon_universal_master_0_write), // .write
.av_read (fpga_only_master_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (fpga_only_master_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (fpga_only_master_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (fpga_only_master_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (fpga_only_master_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (fpga_only_master_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (fpga_only_master_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (fpga_only_master_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (fpga_only_master_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (fpga_only_master_master_agent_cp_valid), // cp.valid
.cp_data (fpga_only_master_master_agent_cp_data), // .data
.cp_startofpacket (fpga_only_master_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (fpga_only_master_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (fpga_only_master_master_agent_cp_ready), // .ready
.rp_valid (fpga_only_master_master_limiter_rsp_src_valid), // rp.valid
.rp_data (fpga_only_master_master_limiter_rsp_src_data), // .data
.rp_channel (fpga_only_master_master_limiter_rsp_src_channel), // .channel
.rp_startofpacket (fpga_only_master_master_limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (fpga_only_master_master_limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (fpga_only_master_master_limiter_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_axi_master_ni #(
.ID_WIDTH (12),
.ADDR_WIDTH (21),
.RDATA_WIDTH (32),
.WDATA_WIDTH (32),
.ADDR_USER_WIDTH (1),
.DATA_USER_WIDTH (1),
.AXI_BURST_LENGTH_WIDTH (4),
.AXI_LOCK_WIDTH (2),
.AXI_VERSION ("AXI3"),
.WRITE_ISSUING_CAPABILITY (8),
.READ_ISSUING_CAPABILITY (8),
.PKT_BEGIN_BURST (97),
.PKT_CACHE_H (123),
.PKT_CACHE_L (120),
.PKT_ADDR_SIDEBAND_H (95),
.PKT_ADDR_SIDEBAND_L (95),
.PKT_PROTECTION_H (119),
.PKT_PROTECTION_L (117),
.PKT_BURST_SIZE_H (92),
.PKT_BURST_SIZE_L (90),
.PKT_BURST_TYPE_H (94),
.PKT_BURST_TYPE_L (93),
.PKT_RESPONSE_STATUS_L (124),
.PKT_RESPONSE_STATUS_H (125),
.PKT_BURSTWRAP_H (89),
.PKT_BURSTWRAP_L (82),
.PKT_BYTE_CNT_H (81),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_EXCLUSIVE (73),
.PKT_TRANS_LOCK (72),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (101),
.PKT_SRC_ID_L (99),
.PKT_DEST_ID_H (104),
.PKT_DEST_ID_L (102),
.PKT_THREAD_ID_H (116),
.PKT_THREAD_ID_L (105),
.PKT_QOS_L (98),
.PKT_QOS_H (98),
.PKT_ORI_BURST_SIZE_L (126),
.PKT_ORI_BURST_SIZE_H (128),
.PKT_DATA_SIDEBAND_H (96),
.PKT_DATA_SIDEBAND_L (96),
.ST_DATA_W (129),
.ST_CHANNEL_W (6),
.ID (2)
) hps_0_h2f_lw_axi_master_agent (
.aclk (clk_0_clk_clk), // clk.clk
.aresetn (~hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset_n
.write_cp_valid (hps_0_h2f_lw_axi_master_agent_write_cp_valid), // write_cp.valid
.write_cp_data (hps_0_h2f_lw_axi_master_agent_write_cp_data), // .data
.write_cp_startofpacket (hps_0_h2f_lw_axi_master_agent_write_cp_startofpacket), // .startofpacket
.write_cp_endofpacket (hps_0_h2f_lw_axi_master_agent_write_cp_endofpacket), // .endofpacket
.write_cp_ready (hps_0_h2f_lw_axi_master_agent_write_cp_ready), // .ready
.write_rp_valid (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_valid), // write_rp.valid
.write_rp_data (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_data), // .data
.write_rp_channel (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_channel), // .channel
.write_rp_startofpacket (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_startofpacket), // .startofpacket
.write_rp_endofpacket (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_endofpacket), // .endofpacket
.write_rp_ready (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_ready), // .ready
.read_cp_valid (hps_0_h2f_lw_axi_master_agent_read_cp_valid), // read_cp.valid
.read_cp_data (hps_0_h2f_lw_axi_master_agent_read_cp_data), // .data
.read_cp_startofpacket (hps_0_h2f_lw_axi_master_agent_read_cp_startofpacket), // .startofpacket
.read_cp_endofpacket (hps_0_h2f_lw_axi_master_agent_read_cp_endofpacket), // .endofpacket
.read_cp_ready (hps_0_h2f_lw_axi_master_agent_read_cp_ready), // .ready
.read_rp_valid (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_valid), // read_rp.valid
.read_rp_data (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_data), // .data
.read_rp_channel (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_channel), // .channel
.read_rp_startofpacket (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_startofpacket), // .startofpacket
.read_rp_endofpacket (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_endofpacket), // .endofpacket
.read_rp_ready (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_ready), // .ready
.awid (hps_0_h2f_lw_axi_master_awid), // altera_axi_slave.awid
.awaddr (hps_0_h2f_lw_axi_master_awaddr), // .awaddr
.awlen (hps_0_h2f_lw_axi_master_awlen), // .awlen
.awsize (hps_0_h2f_lw_axi_master_awsize), // .awsize
.awburst (hps_0_h2f_lw_axi_master_awburst), // .awburst
.awlock (hps_0_h2f_lw_axi_master_awlock), // .awlock
.awcache (hps_0_h2f_lw_axi_master_awcache), // .awcache
.awprot (hps_0_h2f_lw_axi_master_awprot), // .awprot
.awvalid (hps_0_h2f_lw_axi_master_awvalid), // .awvalid
.awready (hps_0_h2f_lw_axi_master_awready), // .awready
.wid (hps_0_h2f_lw_axi_master_wid), // .wid
.wdata (hps_0_h2f_lw_axi_master_wdata), // .wdata
.wstrb (hps_0_h2f_lw_axi_master_wstrb), // .wstrb
.wlast (hps_0_h2f_lw_axi_master_wlast), // .wlast
.wvalid (hps_0_h2f_lw_axi_master_wvalid), // .wvalid
.wready (hps_0_h2f_lw_axi_master_wready), // .wready
.bid (hps_0_h2f_lw_axi_master_bid), // .bid
.bresp (hps_0_h2f_lw_axi_master_bresp), // .bresp
.bvalid (hps_0_h2f_lw_axi_master_bvalid), // .bvalid
.bready (hps_0_h2f_lw_axi_master_bready), // .bready
.arid (hps_0_h2f_lw_axi_master_arid), // .arid
.araddr (hps_0_h2f_lw_axi_master_araddr), // .araddr
.arlen (hps_0_h2f_lw_axi_master_arlen), // .arlen
.arsize (hps_0_h2f_lw_axi_master_arsize), // .arsize
.arburst (hps_0_h2f_lw_axi_master_arburst), // .arburst
.arlock (hps_0_h2f_lw_axi_master_arlock), // .arlock
.arcache (hps_0_h2f_lw_axi_master_arcache), // .arcache
.arprot (hps_0_h2f_lw_axi_master_arprot), // .arprot
.arvalid (hps_0_h2f_lw_axi_master_arvalid), // .arvalid
.arready (hps_0_h2f_lw_axi_master_arready), // .arready
.rid (hps_0_h2f_lw_axi_master_rid), // .rid
.rdata (hps_0_h2f_lw_axi_master_rdata), // .rdata
.rresp (hps_0_h2f_lw_axi_master_rresp), // .rresp
.rlast (hps_0_h2f_lw_axi_master_rlast), // .rlast
.rvalid (hps_0_h2f_lw_axi_master_rvalid), // .rvalid
.rready (hps_0_h2f_lw_axi_master_rready), // .rready
.awuser (1'b0), // (terminated)
.aruser (1'b0), // (terminated)
.awqos (4'b0000), // (terminated)
.arqos (4'b0000), // (terminated)
.awregion (4'b0000), // (terminated)
.arregion (4'b0000), // (terminated)
.wuser (1'b0), // (terminated)
.ruser (), // (terminated)
.buser () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (164),
.PKT_ORI_BURST_SIZE_L (162),
.PKT_RESPONSE_STATUS_H (161),
.PKT_RESPONSE_STATUS_L (160),
.PKT_BURST_SIZE_H (128),
.PKT_BURST_SIZE_L (126),
.PKT_TRANS_LOCK (108),
.PKT_BEGIN_BURST (133),
.PKT_PROTECTION_H (155),
.PKT_PROTECTION_L (153),
.PKT_BURSTWRAP_H (125),
.PKT_BURSTWRAP_L (118),
.PKT_BYTE_CNT_H (117),
.PKT_BYTE_CNT_L (110),
.PKT_ADDR_H (103),
.PKT_ADDR_L (72),
.PKT_TRANS_COMPRESSED_READ (104),
.PKT_TRANS_POSTED (105),
.PKT_TRANS_WRITE (106),
.PKT_TRANS_READ (107),
.PKT_DATA_H (63),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (71),
.PKT_BYTEEN_L (64),
.PKT_SRC_ID_H (137),
.PKT_SRC_ID_L (135),
.PKT_DEST_ID_H (140),
.PKT_DEST_ID_L (138),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (6),
.ST_DATA_W (165),
.AVS_BURSTCOUNT_W (4),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) onchip_memory2_0_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (onchip_memory2_0_s1_agent_m0_address), // m0.address
.m0_burstcount (onchip_memory2_0_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (onchip_memory2_0_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (onchip_memory2_0_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (onchip_memory2_0_s1_agent_m0_lock), // .lock
.m0_readdata (onchip_memory2_0_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (onchip_memory2_0_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (onchip_memory2_0_s1_agent_m0_read), // .read
.m0_waitrequest (onchip_memory2_0_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (onchip_memory2_0_s1_agent_m0_writedata), // .writedata
.m0_write (onchip_memory2_0_s1_agent_m0_write), // .write
.rp_endofpacket (onchip_memory2_0_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (onchip_memory2_0_s1_agent_rp_ready), // .ready
.rp_valid (onchip_memory2_0_s1_agent_rp_valid), // .valid
.rp_data (onchip_memory2_0_s1_agent_rp_data), // .data
.rp_startofpacket (onchip_memory2_0_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (onchip_memory2_0_s1_burst_adapter_source0_ready), // cp.ready
.cp_valid (onchip_memory2_0_s1_burst_adapter_source0_valid), // .valid
.cp_data (onchip_memory2_0_s1_burst_adapter_source0_data), // .data
.cp_startofpacket (onchip_memory2_0_s1_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (onchip_memory2_0_s1_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (onchip_memory2_0_s1_burst_adapter_source0_channel), // .channel
.rf_sink_ready (onchip_memory2_0_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (onchip_memory2_0_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (onchip_memory2_0_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (onchip_memory2_0_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (onchip_memory2_0_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (onchip_memory2_0_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (onchip_memory2_0_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (onchip_memory2_0_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error
.rdata_fifo_src_ready (onchip_memory2_0_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (onchip_memory2_0_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (onchip_memory2_0_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (166),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) onchip_memory2_0_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (onchip_memory2_0_s1_agent_rf_source_data), // in.data
.in_valid (onchip_memory2_0_s1_agent_rf_source_valid), // .valid
.in_ready (onchip_memory2_0_s1_agent_rf_source_ready), // .ready
.in_startofpacket (onchip_memory2_0_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (onchip_memory2_0_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (onchip_memory2_0_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (onchip_memory2_0_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (onchip_memory2_0_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (66),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) onchip_memory2_0_s1_agent_rdata_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (onchip_memory2_0_s1_agent_rdata_fifo_src_data), // in.data
.in_valid (onchip_memory2_0_s1_agent_rdata_fifo_src_valid), // .valid
.in_ready (onchip_memory2_0_s1_agent_rdata_fifo_src_ready), // .ready
.out_data (onchip_memory2_0_s1_agent_rdata_fifo_out_data), // out.data
.out_valid (onchip_memory2_0_s1_agent_rdata_fifo_out_valid), // .valid
.out_ready (onchip_memory2_0_s1_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (128),
.PKT_ORI_BURST_SIZE_L (126),
.PKT_RESPONSE_STATUS_H (125),
.PKT_RESPONSE_STATUS_L (124),
.PKT_BURST_SIZE_H (92),
.PKT_BURST_SIZE_L (90),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (97),
.PKT_PROTECTION_H (119),
.PKT_PROTECTION_L (117),
.PKT_BURSTWRAP_H (89),
.PKT_BURSTWRAP_L (82),
.PKT_BYTE_CNT_H (81),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (101),
.PKT_SRC_ID_L (99),
.PKT_DEST_ID_H (104),
.PKT_DEST_ID_L (102),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (6),
.ST_DATA_W (129),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) jtag_uart_avalon_jtag_slave_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (jtag_uart_avalon_jtag_slave_agent_m0_address), // m0.address
.m0_burstcount (jtag_uart_avalon_jtag_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (jtag_uart_avalon_jtag_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (jtag_uart_avalon_jtag_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (jtag_uart_avalon_jtag_slave_agent_m0_lock), // .lock
.m0_readdata (jtag_uart_avalon_jtag_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (jtag_uart_avalon_jtag_slave_agent_m0_read), // .read
.m0_waitrequest (jtag_uart_avalon_jtag_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (jtag_uart_avalon_jtag_slave_agent_m0_writedata), // .writedata
.m0_write (jtag_uart_avalon_jtag_slave_agent_m0_write), // .write
.rp_endofpacket (jtag_uart_avalon_jtag_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (jtag_uart_avalon_jtag_slave_agent_rp_ready), // .ready
.rp_valid (jtag_uart_avalon_jtag_slave_agent_rp_valid), // .valid
.rp_data (jtag_uart_avalon_jtag_slave_agent_rp_data), // .data
.rp_startofpacket (jtag_uart_avalon_jtag_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (jtag_uart_avalon_jtag_slave_burst_adapter_source0_ready), // cp.ready
.cp_valid (jtag_uart_avalon_jtag_slave_burst_adapter_source0_valid), // .valid
.cp_data (jtag_uart_avalon_jtag_slave_burst_adapter_source0_data), // .data
.cp_startofpacket (jtag_uart_avalon_jtag_slave_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (jtag_uart_avalon_jtag_slave_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (jtag_uart_avalon_jtag_slave_burst_adapter_source0_channel), // .channel
.rf_sink_ready (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (jtag_uart_avalon_jtag_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (jtag_uart_avalon_jtag_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (jtag_uart_avalon_jtag_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_001_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_001_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_001_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_001_out_0_error), // .error
.rdata_fifo_src_ready (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (130),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) jtag_uart_avalon_jtag_slave_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (jtag_uart_avalon_jtag_slave_agent_rf_source_data), // in.data
.in_valid (jtag_uart_avalon_jtag_slave_agent_rf_source_valid), // .valid
.in_ready (jtag_uart_avalon_jtag_slave_agent_rf_source_ready), // .ready
.in_startofpacket (jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) jtag_uart_avalon_jtag_slave_agent_rdata_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data), // in.data
.in_valid (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid), // .valid
.in_ready (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready), // .ready
.out_data (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_data), // out.data
.out_valid (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_valid), // .valid
.out_ready (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (128),
.PKT_ORI_BURST_SIZE_L (126),
.PKT_RESPONSE_STATUS_H (125),
.PKT_RESPONSE_STATUS_L (124),
.PKT_BURST_SIZE_H (92),
.PKT_BURST_SIZE_L (90),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (97),
.PKT_PROTECTION_H (119),
.PKT_PROTECTION_L (117),
.PKT_BURSTWRAP_H (89),
.PKT_BURSTWRAP_L (82),
.PKT_BYTE_CNT_H (81),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (101),
.PKT_SRC_ID_L (99),
.PKT_DEST_ID_H (104),
.PKT_DEST_ID_L (102),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (6),
.ST_DATA_W (129),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) intr_capturer_0_avalon_slave_0_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (intr_capturer_0_avalon_slave_0_agent_m0_address), // m0.address
.m0_burstcount (intr_capturer_0_avalon_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (intr_capturer_0_avalon_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (intr_capturer_0_avalon_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (intr_capturer_0_avalon_slave_0_agent_m0_lock), // .lock
.m0_readdata (intr_capturer_0_avalon_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (intr_capturer_0_avalon_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (intr_capturer_0_avalon_slave_0_agent_m0_read), // .read
.m0_waitrequest (intr_capturer_0_avalon_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (intr_capturer_0_avalon_slave_0_agent_m0_writedata), // .writedata
.m0_write (intr_capturer_0_avalon_slave_0_agent_m0_write), // .write
.rp_endofpacket (intr_capturer_0_avalon_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (intr_capturer_0_avalon_slave_0_agent_rp_ready), // .ready
.rp_valid (intr_capturer_0_avalon_slave_0_agent_rp_valid), // .valid
.rp_data (intr_capturer_0_avalon_slave_0_agent_rp_data), // .data
.rp_startofpacket (intr_capturer_0_avalon_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_002_src_ready), // cp.ready
.cp_valid (cmd_mux_002_src_valid), // .valid
.cp_data (cmd_mux_002_src_data), // .data
.cp_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_002_src_channel), // .channel
.rf_sink_ready (intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (intr_capturer_0_avalon_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (intr_capturer_0_avalon_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (intr_capturer_0_avalon_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (intr_capturer_0_avalon_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (intr_capturer_0_avalon_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_002_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_002_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_002_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_002_out_0_error), // .error
.rdata_fifo_src_ready (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (130),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) intr_capturer_0_avalon_slave_0_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (intr_capturer_0_avalon_slave_0_agent_rf_source_data), // in.data
.in_valid (intr_capturer_0_avalon_slave_0_agent_rf_source_valid), // .valid
.in_ready (intr_capturer_0_avalon_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (intr_capturer_0_avalon_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (intr_capturer_0_avalon_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) intr_capturer_0_avalon_slave_0_agent_rdata_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_src_data), // in.data
.in_valid (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_src_valid), // .valid
.in_ready (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_src_ready), // .ready
.out_data (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_out_data), // out.data
.out_valid (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_out_valid), // .valid
.out_ready (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (128),
.PKT_ORI_BURST_SIZE_L (126),
.PKT_RESPONSE_STATUS_H (125),
.PKT_RESPONSE_STATUS_L (124),
.PKT_BURST_SIZE_H (92),
.PKT_BURST_SIZE_L (90),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (97),
.PKT_PROTECTION_H (119),
.PKT_PROTECTION_L (117),
.PKT_BURSTWRAP_H (89),
.PKT_BURSTWRAP_L (82),
.PKT_BYTE_CNT_H (81),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (101),
.PKT_SRC_ID_L (99),
.PKT_DEST_ID_H (104),
.PKT_DEST_ID_L (102),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (6),
.ST_DATA_W (129),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) sysid_qsys_control_slave_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sysid_qsys_control_slave_agent_m0_address), // m0.address
.m0_burstcount (sysid_qsys_control_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (sysid_qsys_control_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sysid_qsys_control_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (sysid_qsys_control_slave_agent_m0_lock), // .lock
.m0_readdata (sysid_qsys_control_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (sysid_qsys_control_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sysid_qsys_control_slave_agent_m0_read), // .read
.m0_waitrequest (sysid_qsys_control_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sysid_qsys_control_slave_agent_m0_writedata), // .writedata
.m0_write (sysid_qsys_control_slave_agent_m0_write), // .write
.rp_endofpacket (sysid_qsys_control_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sysid_qsys_control_slave_agent_rp_ready), // .ready
.rp_valid (sysid_qsys_control_slave_agent_rp_valid), // .valid
.rp_data (sysid_qsys_control_slave_agent_rp_data), // .data
.rp_startofpacket (sysid_qsys_control_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (sysid_qsys_control_slave_burst_adapter_source0_ready), // cp.ready
.cp_valid (sysid_qsys_control_slave_burst_adapter_source0_valid), // .valid
.cp_data (sysid_qsys_control_slave_burst_adapter_source0_data), // .data
.cp_startofpacket (sysid_qsys_control_slave_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (sysid_qsys_control_slave_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (sysid_qsys_control_slave_burst_adapter_source0_channel), // .channel
.rf_sink_ready (sysid_qsys_control_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sysid_qsys_control_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sysid_qsys_control_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sysid_qsys_control_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sysid_qsys_control_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sysid_qsys_control_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sysid_qsys_control_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sysid_qsys_control_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sysid_qsys_control_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sysid_qsys_control_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_003_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_003_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_003_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_003_out_0_error), // .error
.rdata_fifo_src_ready (sysid_qsys_control_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sysid_qsys_control_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sysid_qsys_control_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (130),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sysid_qsys_control_slave_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sysid_qsys_control_slave_agent_rf_source_data), // in.data
.in_valid (sysid_qsys_control_slave_agent_rf_source_valid), // .valid
.in_ready (sysid_qsys_control_slave_agent_rf_source_ready), // .ready
.in_startofpacket (sysid_qsys_control_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sysid_qsys_control_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (sysid_qsys_control_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (sysid_qsys_control_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (sysid_qsys_control_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sysid_qsys_control_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sysid_qsys_control_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sysid_qsys_control_slave_agent_rdata_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sysid_qsys_control_slave_agent_rdata_fifo_src_data), // in.data
.in_valid (sysid_qsys_control_slave_agent_rdata_fifo_src_valid), // .valid
.in_ready (sysid_qsys_control_slave_agent_rdata_fifo_src_ready), // .ready
.out_data (sysid_qsys_control_slave_agent_rdata_fifo_out_data), // out.data
.out_valid (sysid_qsys_control_slave_agent_rdata_fifo_out_valid), // .valid
.out_ready (sysid_qsys_control_slave_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (128),
.PKT_ORI_BURST_SIZE_L (126),
.PKT_RESPONSE_STATUS_H (125),
.PKT_RESPONSE_STATUS_L (124),
.PKT_BURST_SIZE_H (92),
.PKT_BURST_SIZE_L (90),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (97),
.PKT_PROTECTION_H (119),
.PKT_PROTECTION_L (117),
.PKT_BURSTWRAP_H (89),
.PKT_BURSTWRAP_L (82),
.PKT_BYTE_CNT_H (81),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (101),
.PKT_SRC_ID_L (99),
.PKT_DEST_ID_H (104),
.PKT_DEST_ID_L (102),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (6),
.ST_DATA_W (129),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) reg32_avalon_interface_0_avalon_slave_0_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (reg32_avalon_interface_0_avalon_slave_0_agent_m0_address), // m0.address
.m0_burstcount (reg32_avalon_interface_0_avalon_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (reg32_avalon_interface_0_avalon_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (reg32_avalon_interface_0_avalon_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (reg32_avalon_interface_0_avalon_slave_0_agent_m0_lock), // .lock
.m0_readdata (reg32_avalon_interface_0_avalon_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (reg32_avalon_interface_0_avalon_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (reg32_avalon_interface_0_avalon_slave_0_agent_m0_read), // .read
.m0_waitrequest (reg32_avalon_interface_0_avalon_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (reg32_avalon_interface_0_avalon_slave_0_agent_m0_writedata), // .writedata
.m0_write (reg32_avalon_interface_0_avalon_slave_0_agent_m0_write), // .write
.rp_endofpacket (reg32_avalon_interface_0_avalon_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (reg32_avalon_interface_0_avalon_slave_0_agent_rp_ready), // .ready
.rp_valid (reg32_avalon_interface_0_avalon_slave_0_agent_rp_valid), // .valid
.rp_data (reg32_avalon_interface_0_avalon_slave_0_agent_rp_data), // .data
.rp_startofpacket (reg32_avalon_interface_0_avalon_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (reg32_avalon_interface_0_avalon_slave_0_burst_adapter_source0_ready), // cp.ready
.cp_valid (reg32_avalon_interface_0_avalon_slave_0_burst_adapter_source0_valid), // .valid
.cp_data (reg32_avalon_interface_0_avalon_slave_0_burst_adapter_source0_data), // .data
.cp_startofpacket (reg32_avalon_interface_0_avalon_slave_0_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (reg32_avalon_interface_0_avalon_slave_0_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (reg32_avalon_interface_0_avalon_slave_0_burst_adapter_source0_channel), // .channel
.rf_sink_ready (reg32_avalon_interface_0_avalon_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (reg32_avalon_interface_0_avalon_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (reg32_avalon_interface_0_avalon_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (reg32_avalon_interface_0_avalon_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (reg32_avalon_interface_0_avalon_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (reg32_avalon_interface_0_avalon_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (reg32_avalon_interface_0_avalon_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (reg32_avalon_interface_0_avalon_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (reg32_avalon_interface_0_avalon_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (reg32_avalon_interface_0_avalon_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_004_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_004_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_004_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_004_out_0_error), // .error
.rdata_fifo_src_ready (reg32_avalon_interface_0_avalon_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (reg32_avalon_interface_0_avalon_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (reg32_avalon_interface_0_avalon_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (130),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) reg32_avalon_interface_0_avalon_slave_0_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (reg32_avalon_interface_0_avalon_slave_0_agent_rf_source_data), // in.data
.in_valid (reg32_avalon_interface_0_avalon_slave_0_agent_rf_source_valid), // .valid
.in_ready (reg32_avalon_interface_0_avalon_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (reg32_avalon_interface_0_avalon_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (reg32_avalon_interface_0_avalon_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (reg32_avalon_interface_0_avalon_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (reg32_avalon_interface_0_avalon_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (reg32_avalon_interface_0_avalon_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (reg32_avalon_interface_0_avalon_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (reg32_avalon_interface_0_avalon_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) reg32_avalon_interface_0_avalon_slave_0_agent_rdata_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (reg32_avalon_interface_0_avalon_slave_0_agent_rdata_fifo_src_data), // in.data
.in_valid (reg32_avalon_interface_0_avalon_slave_0_agent_rdata_fifo_src_valid), // .valid
.in_ready (reg32_avalon_interface_0_avalon_slave_0_agent_rdata_fifo_src_ready), // .ready
.out_data (reg32_avalon_interface_0_avalon_slave_0_agent_rdata_fifo_out_data), // out.data
.out_valid (reg32_avalon_interface_0_avalon_slave_0_agent_rdata_fifo_out_valid), // .valid
.out_ready (reg32_avalon_interface_0_avalon_slave_0_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (128),
.PKT_ORI_BURST_SIZE_L (126),
.PKT_RESPONSE_STATUS_H (125),
.PKT_RESPONSE_STATUS_L (124),
.PKT_BURST_SIZE_H (92),
.PKT_BURST_SIZE_L (90),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (97),
.PKT_PROTECTION_H (119),
.PKT_PROTECTION_L (117),
.PKT_BURSTWRAP_H (89),
.PKT_BURSTWRAP_L (82),
.PKT_BYTE_CNT_H (81),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (101),
.PKT_SRC_ID_L (99),
.PKT_DEST_ID_H (104),
.PKT_DEST_ID_L (102),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (6),
.ST_DATA_W (129),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) rc4_avalon_interface_0_avalon_slave_0_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (rc4_avalon_interface_0_avalon_slave_0_agent_m0_address), // m0.address
.m0_burstcount (rc4_avalon_interface_0_avalon_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (rc4_avalon_interface_0_avalon_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (rc4_avalon_interface_0_avalon_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (rc4_avalon_interface_0_avalon_slave_0_agent_m0_lock), // .lock
.m0_readdata (rc4_avalon_interface_0_avalon_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (rc4_avalon_interface_0_avalon_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (rc4_avalon_interface_0_avalon_slave_0_agent_m0_read), // .read
.m0_waitrequest (rc4_avalon_interface_0_avalon_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (rc4_avalon_interface_0_avalon_slave_0_agent_m0_writedata), // .writedata
.m0_write (rc4_avalon_interface_0_avalon_slave_0_agent_m0_write), // .write
.rp_endofpacket (rc4_avalon_interface_0_avalon_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (rc4_avalon_interface_0_avalon_slave_0_agent_rp_ready), // .ready
.rp_valid (rc4_avalon_interface_0_avalon_slave_0_agent_rp_valid), // .valid
.rp_data (rc4_avalon_interface_0_avalon_slave_0_agent_rp_data), // .data
.rp_startofpacket (rc4_avalon_interface_0_avalon_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (rc4_avalon_interface_0_avalon_slave_0_burst_adapter_source0_ready), // cp.ready
.cp_valid (rc4_avalon_interface_0_avalon_slave_0_burst_adapter_source0_valid), // .valid
.cp_data (rc4_avalon_interface_0_avalon_slave_0_burst_adapter_source0_data), // .data
.cp_startofpacket (rc4_avalon_interface_0_avalon_slave_0_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (rc4_avalon_interface_0_avalon_slave_0_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (rc4_avalon_interface_0_avalon_slave_0_burst_adapter_source0_channel), // .channel
.rf_sink_ready (rc4_avalon_interface_0_avalon_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (rc4_avalon_interface_0_avalon_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (rc4_avalon_interface_0_avalon_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (rc4_avalon_interface_0_avalon_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (rc4_avalon_interface_0_avalon_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (rc4_avalon_interface_0_avalon_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (rc4_avalon_interface_0_avalon_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (rc4_avalon_interface_0_avalon_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (rc4_avalon_interface_0_avalon_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (rc4_avalon_interface_0_avalon_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_005_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_005_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_005_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_005_out_0_error), // .error
.rdata_fifo_src_ready (rc4_avalon_interface_0_avalon_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (rc4_avalon_interface_0_avalon_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (rc4_avalon_interface_0_avalon_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (130),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) rc4_avalon_interface_0_avalon_slave_0_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (rc4_avalon_interface_0_avalon_slave_0_agent_rf_source_data), // in.data
.in_valid (rc4_avalon_interface_0_avalon_slave_0_agent_rf_source_valid), // .valid
.in_ready (rc4_avalon_interface_0_avalon_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (rc4_avalon_interface_0_avalon_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (rc4_avalon_interface_0_avalon_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (rc4_avalon_interface_0_avalon_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (rc4_avalon_interface_0_avalon_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (rc4_avalon_interface_0_avalon_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (rc4_avalon_interface_0_avalon_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (rc4_avalon_interface_0_avalon_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) rc4_avalon_interface_0_avalon_slave_0_agent_rdata_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (rc4_avalon_interface_0_avalon_slave_0_agent_rdata_fifo_src_data), // in.data
.in_valid (rc4_avalon_interface_0_avalon_slave_0_agent_rdata_fifo_src_valid), // .valid
.in_ready (rc4_avalon_interface_0_avalon_slave_0_agent_rdata_fifo_src_ready), // .ready
.out_data (rc4_avalon_interface_0_avalon_slave_0_agent_rdata_fifo_out_data), // out.data
.out_valid (rc4_avalon_interface_0_avalon_slave_0_agent_rdata_fifo_out_valid), // .valid
.out_ready (rc4_avalon_interface_0_avalon_slave_0_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
soc_system_mm_interconnect_0_router router (
.sink_ready (hps_0_h2f_axi_master_agent_write_cp_ready), // sink.ready
.sink_valid (hps_0_h2f_axi_master_agent_write_cp_valid), // .valid
.sink_data (hps_0_h2f_axi_master_agent_write_cp_data), // .data
.sink_startofpacket (hps_0_h2f_axi_master_agent_write_cp_startofpacket), // .startofpacket
.sink_endofpacket (hps_0_h2f_axi_master_agent_write_cp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_router router_001 (
.sink_ready (hps_0_h2f_axi_master_agent_read_cp_ready), // sink.ready
.sink_valid (hps_0_h2f_axi_master_agent_read_cp_valid), // .valid
.sink_data (hps_0_h2f_axi_master_agent_read_cp_data), // .data
.sink_startofpacket (hps_0_h2f_axi_master_agent_read_cp_startofpacket), // .startofpacket
.sink_endofpacket (hps_0_h2f_axi_master_agent_read_cp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_router_002 router_002 (
.sink_ready (fpga_only_master_master_agent_cp_ready), // sink.ready
.sink_valid (fpga_only_master_master_agent_cp_valid), // .valid
.sink_data (fpga_only_master_master_agent_cp_data), // .data
.sink_startofpacket (fpga_only_master_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (fpga_only_master_master_agent_cp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_router_003 router_003 (
.sink_ready (hps_0_h2f_lw_axi_master_agent_write_cp_ready), // sink.ready
.sink_valid (hps_0_h2f_lw_axi_master_agent_write_cp_valid), // .valid
.sink_data (hps_0_h2f_lw_axi_master_agent_write_cp_data), // .data
.sink_startofpacket (hps_0_h2f_lw_axi_master_agent_write_cp_startofpacket), // .startofpacket
.sink_endofpacket (hps_0_h2f_lw_axi_master_agent_write_cp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_router_003 router_004 (
.sink_ready (hps_0_h2f_lw_axi_master_agent_read_cp_ready), // sink.ready
.sink_valid (hps_0_h2f_lw_axi_master_agent_read_cp_valid), // .valid
.sink_data (hps_0_h2f_lw_axi_master_agent_read_cp_data), // .data
.sink_startofpacket (hps_0_h2f_lw_axi_master_agent_read_cp_startofpacket), // .startofpacket
.sink_endofpacket (hps_0_h2f_lw_axi_master_agent_read_cp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_router_005 router_005 (
.sink_ready (onchip_memory2_0_s1_agent_rp_ready), // sink.ready
.sink_valid (onchip_memory2_0_s1_agent_rp_valid), // .valid
.sink_data (onchip_memory2_0_s1_agent_rp_data), // .data
.sink_startofpacket (onchip_memory2_0_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (onchip_memory2_0_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_005_src_ready), // src.ready
.src_valid (router_005_src_valid), // .valid
.src_data (router_005_src_data), // .data
.src_channel (router_005_src_channel), // .channel
.src_startofpacket (router_005_src_startofpacket), // .startofpacket
.src_endofpacket (router_005_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_router_006 router_006 (
.sink_ready (jtag_uart_avalon_jtag_slave_agent_rp_ready), // sink.ready
.sink_valid (jtag_uart_avalon_jtag_slave_agent_rp_valid), // .valid
.sink_data (jtag_uart_avalon_jtag_slave_agent_rp_data), // .data
.sink_startofpacket (jtag_uart_avalon_jtag_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (jtag_uart_avalon_jtag_slave_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_006_src_ready), // src.ready
.src_valid (router_006_src_valid), // .valid
.src_data (router_006_src_data), // .data
.src_channel (router_006_src_channel), // .channel
.src_startofpacket (router_006_src_startofpacket), // .startofpacket
.src_endofpacket (router_006_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_router_007 router_007 (
.sink_ready (intr_capturer_0_avalon_slave_0_agent_rp_ready), // sink.ready
.sink_valid (intr_capturer_0_avalon_slave_0_agent_rp_valid), // .valid
.sink_data (intr_capturer_0_avalon_slave_0_agent_rp_data), // .data
.sink_startofpacket (intr_capturer_0_avalon_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (intr_capturer_0_avalon_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_007_src_ready), // src.ready
.src_valid (router_007_src_valid), // .valid
.src_data (router_007_src_data), // .data
.src_channel (router_007_src_channel), // .channel
.src_startofpacket (router_007_src_startofpacket), // .startofpacket
.src_endofpacket (router_007_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_router_006 router_008 (
.sink_ready (sysid_qsys_control_slave_agent_rp_ready), // sink.ready
.sink_valid (sysid_qsys_control_slave_agent_rp_valid), // .valid
.sink_data (sysid_qsys_control_slave_agent_rp_data), // .data
.sink_startofpacket (sysid_qsys_control_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sysid_qsys_control_slave_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_008_src_ready), // src.ready
.src_valid (router_008_src_valid), // .valid
.src_data (router_008_src_data), // .data
.src_channel (router_008_src_channel), // .channel
.src_startofpacket (router_008_src_startofpacket), // .startofpacket
.src_endofpacket (router_008_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_router_009 router_009 (
.sink_ready (reg32_avalon_interface_0_avalon_slave_0_agent_rp_ready), // sink.ready
.sink_valid (reg32_avalon_interface_0_avalon_slave_0_agent_rp_valid), // .valid
.sink_data (reg32_avalon_interface_0_avalon_slave_0_agent_rp_data), // .data
.sink_startofpacket (reg32_avalon_interface_0_avalon_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (reg32_avalon_interface_0_avalon_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_009_src_ready), // src.ready
.src_valid (router_009_src_valid), // .valid
.src_data (router_009_src_data), // .data
.src_channel (router_009_src_channel), // .channel
.src_startofpacket (router_009_src_startofpacket), // .startofpacket
.src_endofpacket (router_009_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_router_009 router_010 (
.sink_ready (rc4_avalon_interface_0_avalon_slave_0_agent_rp_ready), // sink.ready
.sink_valid (rc4_avalon_interface_0_avalon_slave_0_agent_rp_valid), // .valid
.sink_data (rc4_avalon_interface_0_avalon_slave_0_agent_rp_data), // .data
.sink_startofpacket (rc4_avalon_interface_0_avalon_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (rc4_avalon_interface_0_avalon_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_010_src_ready), // src.ready
.src_valid (router_010_src_valid), // .valid
.src_data (router_010_src_data), // .data
.src_channel (router_010_src_channel), // .channel
.src_startofpacket (router_010_src_startofpacket), // .startofpacket
.src_endofpacket (router_010_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (104),
.PKT_DEST_ID_L (102),
.PKT_SRC_ID_H (101),
.PKT_SRC_ID_L (99),
.PKT_BYTE_CNT_H (81),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.MAX_OUTSTANDING_RESPONSES (3),
.PIPELINED (0),
.ST_DATA_W (129),
.ST_CHANNEL_W (6),
.VALID_WIDTH (6),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.SUPPORTS_POSTED_WRITES (1),
.SUPPORTS_NONPOSTED_WRITES (0),
.REORDER (0)
) fpga_only_master_master_limiter (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_002_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_002_src_valid), // .valid
.cmd_sink_data (router_002_src_data), // .data
.cmd_sink_channel (router_002_src_channel), // .channel
.cmd_sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.cmd_src_ready (fpga_only_master_master_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (fpga_only_master_master_limiter_cmd_src_data), // .data
.cmd_src_channel (fpga_only_master_master_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (fpga_only_master_master_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (fpga_only_master_master_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_002_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_002_src_valid), // .valid
.rsp_sink_channel (rsp_mux_002_src_channel), // .channel
.rsp_sink_data (rsp_mux_002_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_002_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_002_src_endofpacket), // .endofpacket
.rsp_src_ready (fpga_only_master_master_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (fpga_only_master_master_limiter_rsp_src_valid), // .valid
.rsp_src_data (fpga_only_master_master_limiter_rsp_src_data), // .data
.rsp_src_channel (fpga_only_master_master_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (fpga_only_master_master_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (fpga_only_master_master_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (fpga_only_master_master_limiter_cmd_valid_data) // cmd_valid.data
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (104),
.PKT_DEST_ID_L (102),
.PKT_SRC_ID_H (101),
.PKT_SRC_ID_L (99),
.PKT_BYTE_CNT_H (81),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.MAX_OUTSTANDING_RESPONSES (3),
.PIPELINED (0),
.ST_DATA_W (129),
.ST_CHANNEL_W (6),
.VALID_WIDTH (6),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.SUPPORTS_POSTED_WRITES (1),
.SUPPORTS_NONPOSTED_WRITES (0),
.REORDER (0)
) hps_0_h2f_lw_axi_master_wr_limiter (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_003_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_003_src_valid), // .valid
.cmd_sink_data (router_003_src_data), // .data
.cmd_sink_channel (router_003_src_channel), // .channel
.cmd_sink_startofpacket (router_003_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_003_src_endofpacket), // .endofpacket
.cmd_src_ready (hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_data), // .data
.cmd_src_channel (hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_003_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_003_src_valid), // .valid
.rsp_sink_channel (rsp_mux_003_src_channel), // .channel
.rsp_sink_data (rsp_mux_003_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_003_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_003_src_endofpacket), // .endofpacket
.rsp_src_ready (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_valid), // .valid
.rsp_src_data (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_data), // .data
.rsp_src_channel (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (hps_0_h2f_lw_axi_master_wr_limiter_cmd_valid_data) // cmd_valid.data
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (104),
.PKT_DEST_ID_L (102),
.PKT_SRC_ID_H (101),
.PKT_SRC_ID_L (99),
.PKT_BYTE_CNT_H (81),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.MAX_OUTSTANDING_RESPONSES (3),
.PIPELINED (0),
.ST_DATA_W (129),
.ST_CHANNEL_W (6),
.VALID_WIDTH (6),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.SUPPORTS_POSTED_WRITES (1),
.SUPPORTS_NONPOSTED_WRITES (0),
.REORDER (0)
) hps_0_h2f_lw_axi_master_rd_limiter (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_004_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_004_src_valid), // .valid
.cmd_sink_data (router_004_src_data), // .data
.cmd_sink_channel (router_004_src_channel), // .channel
.cmd_sink_startofpacket (router_004_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_004_src_endofpacket), // .endofpacket
.cmd_src_ready (hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_data), // .data
.cmd_src_channel (hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_004_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_004_src_valid), // .valid
.rsp_sink_channel (rsp_mux_004_src_channel), // .channel
.rsp_sink_data (rsp_mux_004_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_004_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_004_src_endofpacket), // .endofpacket
.rsp_src_ready (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_valid), // .valid
.rsp_src_data (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_data), // .data
.rsp_src_channel (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (hps_0_h2f_lw_axi_master_rd_limiter_cmd_valid_data) // cmd_valid.data
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (103),
.PKT_ADDR_L (72),
.PKT_BEGIN_BURST (133),
.PKT_BYTE_CNT_H (117),
.PKT_BYTE_CNT_L (110),
.PKT_BYTEEN_H (71),
.PKT_BYTEEN_L (64),
.PKT_BURST_SIZE_H (128),
.PKT_BURST_SIZE_L (126),
.PKT_BURST_TYPE_H (130),
.PKT_BURST_TYPE_L (129),
.PKT_BURSTWRAP_H (125),
.PKT_BURSTWRAP_L (118),
.PKT_TRANS_COMPRESSED_READ (104),
.PKT_TRANS_WRITE (106),
.PKT_TRANS_READ (107),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (1),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (165),
.ST_CHANNEL_W (6),
.OUT_BYTE_CNT_H (113),
.OUT_BURSTWRAP_H (125),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (0),
.BURSTWRAP_CONST_VALUE (0),
.ADAPTER_VERSION ("13.1")
) onchip_memory2_0_s1_burst_adapter (
.clk (clk_0_clk_clk), // cr0.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_src_valid), // sink0.valid
.sink0_data (cmd_mux_src_data), // .data
.sink0_channel (cmd_mux_src_channel), // .channel
.sink0_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_src_ready), // .ready
.source0_valid (onchip_memory2_0_s1_burst_adapter_source0_valid), // source0.valid
.source0_data (onchip_memory2_0_s1_burst_adapter_source0_data), // .data
.source0_channel (onchip_memory2_0_s1_burst_adapter_source0_channel), // .channel
.source0_startofpacket (onchip_memory2_0_s1_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (onchip_memory2_0_s1_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (onchip_memory2_0_s1_burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (97),
.PKT_BYTE_CNT_H (81),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (92),
.PKT_BURST_SIZE_L (90),
.PKT_BURST_TYPE_H (94),
.PKT_BURST_TYPE_L (93),
.PKT_BURSTWRAP_H (89),
.PKT_BURSTWRAP_L (82),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (1),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (129),
.ST_CHANNEL_W (6),
.OUT_BYTE_CNT_H (76),
.OUT_BURSTWRAP_H (89),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (0),
.BURSTWRAP_CONST_VALUE (0),
.ADAPTER_VERSION ("13.1")
) jtag_uart_avalon_jtag_slave_burst_adapter (
.clk (clk_0_clk_clk), // cr0.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_001_src_valid), // sink0.valid
.sink0_data (cmd_mux_001_src_data), // .data
.sink0_channel (cmd_mux_001_src_channel), // .channel
.sink0_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_001_src_ready), // .ready
.source0_valid (jtag_uart_avalon_jtag_slave_burst_adapter_source0_valid), // source0.valid
.source0_data (jtag_uart_avalon_jtag_slave_burst_adapter_source0_data), // .data
.source0_channel (jtag_uart_avalon_jtag_slave_burst_adapter_source0_channel), // .channel
.source0_startofpacket (jtag_uart_avalon_jtag_slave_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (jtag_uart_avalon_jtag_slave_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (jtag_uart_avalon_jtag_slave_burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (97),
.PKT_BYTE_CNT_H (81),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (92),
.PKT_BURST_SIZE_L (90),
.PKT_BURST_TYPE_H (94),
.PKT_BURST_TYPE_L (93),
.PKT_BURSTWRAP_H (89),
.PKT_BURSTWRAP_L (82),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (1),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (129),
.ST_CHANNEL_W (6),
.OUT_BYTE_CNT_H (76),
.OUT_BURSTWRAP_H (89),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (0),
.BURSTWRAP_CONST_VALUE (0),
.ADAPTER_VERSION ("13.1")
) sysid_qsys_control_slave_burst_adapter (
.clk (clk_0_clk_clk), // cr0.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_003_src_valid), // sink0.valid
.sink0_data (cmd_mux_003_src_data), // .data
.sink0_channel (cmd_mux_003_src_channel), // .channel
.sink0_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_003_src_ready), // .ready
.source0_valid (sysid_qsys_control_slave_burst_adapter_source0_valid), // source0.valid
.source0_data (sysid_qsys_control_slave_burst_adapter_source0_data), // .data
.source0_channel (sysid_qsys_control_slave_burst_adapter_source0_channel), // .channel
.source0_startofpacket (sysid_qsys_control_slave_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (sysid_qsys_control_slave_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (sysid_qsys_control_slave_burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (97),
.PKT_BYTE_CNT_H (81),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (92),
.PKT_BURST_SIZE_L (90),
.PKT_BURST_TYPE_H (94),
.PKT_BURST_TYPE_L (93),
.PKT_BURSTWRAP_H (89),
.PKT_BURSTWRAP_L (82),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (1),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (129),
.ST_CHANNEL_W (6),
.OUT_BYTE_CNT_H (76),
.OUT_BURSTWRAP_H (89),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (0),
.BURSTWRAP_CONST_VALUE (0),
.ADAPTER_VERSION ("13.1")
) reg32_avalon_interface_0_avalon_slave_0_burst_adapter (
.clk (clk_0_clk_clk), // cr0.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_004_src_valid), // sink0.valid
.sink0_data (cmd_mux_004_src_data), // .data
.sink0_channel (cmd_mux_004_src_channel), // .channel
.sink0_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_004_src_ready), // .ready
.source0_valid (reg32_avalon_interface_0_avalon_slave_0_burst_adapter_source0_valid), // source0.valid
.source0_data (reg32_avalon_interface_0_avalon_slave_0_burst_adapter_source0_data), // .data
.source0_channel (reg32_avalon_interface_0_avalon_slave_0_burst_adapter_source0_channel), // .channel
.source0_startofpacket (reg32_avalon_interface_0_avalon_slave_0_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (reg32_avalon_interface_0_avalon_slave_0_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (reg32_avalon_interface_0_avalon_slave_0_burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (97),
.PKT_BYTE_CNT_H (81),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (92),
.PKT_BURST_SIZE_L (90),
.PKT_BURST_TYPE_H (94),
.PKT_BURST_TYPE_L (93),
.PKT_BURSTWRAP_H (89),
.PKT_BURSTWRAP_L (82),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (1),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (129),
.ST_CHANNEL_W (6),
.OUT_BYTE_CNT_H (76),
.OUT_BURSTWRAP_H (89),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (0),
.BURSTWRAP_CONST_VALUE (0),
.ADAPTER_VERSION ("13.1")
) rc4_avalon_interface_0_avalon_slave_0_burst_adapter (
.clk (clk_0_clk_clk), // cr0.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_005_src_valid), // sink0.valid
.sink0_data (cmd_mux_005_src_data), // .data
.sink0_channel (cmd_mux_005_src_channel), // .channel
.sink0_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_005_src_ready), // .ready
.source0_valid (rc4_avalon_interface_0_avalon_slave_0_burst_adapter_source0_valid), // source0.valid
.source0_data (rc4_avalon_interface_0_avalon_slave_0_burst_adapter_source0_data), // .data
.source0_channel (rc4_avalon_interface_0_avalon_slave_0_burst_adapter_source0_channel), // .channel
.source0_startofpacket (rc4_avalon_interface_0_avalon_slave_0_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (rc4_avalon_interface_0_avalon_slave_0_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (rc4_avalon_interface_0_avalon_slave_0_burst_adapter_source0_ready) // .ready
);
soc_system_mm_interconnect_0_cmd_demux cmd_demux (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_src_ready), // sink.ready
.sink_channel (router_src_channel), // .channel
.sink_data (router_src_data), // .data
.sink_startofpacket (router_src_startofpacket), // .startofpacket
.sink_endofpacket (router_src_endofpacket), // .endofpacket
.sink_valid (router_src_valid), // .valid
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_cmd_demux cmd_demux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_001_src_ready), // sink.ready
.sink_channel (router_001_src_channel), // .channel
.sink_data (router_001_src_data), // .data
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.sink_valid (router_001_src_valid), // .valid
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_cmd_demux_002 cmd_demux_002 (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (fpga_only_master_master_limiter_cmd_src_ready), // sink.ready
.sink_channel (fpga_only_master_master_limiter_cmd_src_channel), // .channel
.sink_data (fpga_only_master_master_limiter_cmd_src_data), // .data
.sink_startofpacket (fpga_only_master_master_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (fpga_only_master_master_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (fpga_only_master_master_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_002_src0_ready), // src0.ready
.src0_valid (cmd_demux_002_src0_valid), // .valid
.src0_data (cmd_demux_002_src0_data), // .data
.src0_channel (cmd_demux_002_src0_channel), // .channel
.src0_startofpacket (cmd_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_002_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_002_src1_ready), // src1.ready
.src1_valid (cmd_demux_002_src1_valid), // .valid
.src1_data (cmd_demux_002_src1_data), // .data
.src1_channel (cmd_demux_002_src1_channel), // .channel
.src1_startofpacket (cmd_demux_002_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_002_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_002_src2_ready), // src2.ready
.src2_valid (cmd_demux_002_src2_valid), // .valid
.src2_data (cmd_demux_002_src2_data), // .data
.src2_channel (cmd_demux_002_src2_channel), // .channel
.src2_startofpacket (cmd_demux_002_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_002_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_002_src3_ready), // src3.ready
.src3_valid (cmd_demux_002_src3_valid), // .valid
.src3_data (cmd_demux_002_src3_data), // .data
.src3_channel (cmd_demux_002_src3_channel), // .channel
.src3_startofpacket (cmd_demux_002_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_002_src3_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_cmd_demux_002 cmd_demux_003 (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_ready), // sink.ready
.sink_channel (hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_channel), // .channel
.sink_data (hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_data), // .data
.sink_startofpacket (hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (hps_0_h2f_lw_axi_master_wr_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_003_src0_ready), // src0.ready
.src0_valid (cmd_demux_003_src0_valid), // .valid
.src0_data (cmd_demux_003_src0_data), // .data
.src0_channel (cmd_demux_003_src0_channel), // .channel
.src0_startofpacket (cmd_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_003_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_003_src1_ready), // src1.ready
.src1_valid (cmd_demux_003_src1_valid), // .valid
.src1_data (cmd_demux_003_src1_data), // .data
.src1_channel (cmd_demux_003_src1_channel), // .channel
.src1_startofpacket (cmd_demux_003_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_003_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_003_src2_ready), // src2.ready
.src2_valid (cmd_demux_003_src2_valid), // .valid
.src2_data (cmd_demux_003_src2_data), // .data
.src2_channel (cmd_demux_003_src2_channel), // .channel
.src2_startofpacket (cmd_demux_003_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_003_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_003_src3_ready), // src3.ready
.src3_valid (cmd_demux_003_src3_valid), // .valid
.src3_data (cmd_demux_003_src3_data), // .data
.src3_channel (cmd_demux_003_src3_channel), // .channel
.src3_startofpacket (cmd_demux_003_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_003_src3_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_cmd_demux_002 cmd_demux_004 (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_ready), // sink.ready
.sink_channel (hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_channel), // .channel
.sink_data (hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_data), // .data
.sink_startofpacket (hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (hps_0_h2f_lw_axi_master_rd_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_004_src0_ready), // src0.ready
.src0_valid (cmd_demux_004_src0_valid), // .valid
.src0_data (cmd_demux_004_src0_data), // .data
.src0_channel (cmd_demux_004_src0_channel), // .channel
.src0_startofpacket (cmd_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_004_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_004_src1_ready), // src1.ready
.src1_valid (cmd_demux_004_src1_valid), // .valid
.src1_data (cmd_demux_004_src1_data), // .data
.src1_channel (cmd_demux_004_src1_channel), // .channel
.src1_startofpacket (cmd_demux_004_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_004_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_004_src2_ready), // src2.ready
.src2_valid (cmd_demux_004_src2_valid), // .valid
.src2_data (cmd_demux_004_src2_data), // .data
.src2_channel (cmd_demux_004_src2_channel), // .channel
.src2_startofpacket (cmd_demux_004_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_004_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_004_src3_ready), // src3.ready
.src3_valid (cmd_demux_004_src3_valid), // .valid
.src3_data (cmd_demux_004_src3_data), // .data
.src3_channel (cmd_demux_004_src3_channel), // .channel
.src3_startofpacket (cmd_demux_004_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_004_src3_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_cmd_mux cmd_mux (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src0_valid), // .valid
.sink1_channel (cmd_demux_001_src0_channel), // .channel
.sink1_data (cmd_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_ready), // sink2.ready
.sink2_valid (fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_valid), // .valid
.sink2_channel (fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_channel), // .channel
.sink2_data (fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_data), // .data
.sink2_startofpacket (fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_startofpacket), // .startofpacket
.sink2_endofpacket (fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_cmd_mux_001 cmd_mux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_002_src1_ready), // sink0.ready
.sink0_valid (cmd_demux_002_src1_valid), // .valid
.sink0_channel (cmd_demux_002_src1_channel), // .channel
.sink0_data (cmd_demux_002_src1_data), // .data
.sink0_startofpacket (cmd_demux_002_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_002_src1_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_003_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_003_src0_valid), // .valid
.sink1_channel (cmd_demux_003_src0_channel), // .channel
.sink1_data (cmd_demux_003_src0_data), // .data
.sink1_startofpacket (cmd_demux_003_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_003_src0_endofpacket), // .endofpacket
.sink2_ready (cmd_demux_004_src0_ready), // sink2.ready
.sink2_valid (cmd_demux_004_src0_valid), // .valid
.sink2_channel (cmd_demux_004_src0_channel), // .channel
.sink2_data (cmd_demux_004_src0_data), // .data
.sink2_startofpacket (cmd_demux_004_src0_startofpacket), // .startofpacket
.sink2_endofpacket (cmd_demux_004_src0_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_cmd_mux_002 cmd_mux_002 (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_002_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_002_src2_valid), // .valid
.sink0_channel (cmd_demux_002_src2_channel), // .channel
.sink0_data (cmd_demux_002_src2_data), // .data
.sink0_startofpacket (cmd_demux_002_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_002_src2_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_cmd_mux_001 cmd_mux_003 (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_003_src_ready), // src.ready
.src_valid (cmd_mux_003_src_valid), // .valid
.src_data (cmd_mux_003_src_data), // .data
.src_channel (cmd_mux_003_src_channel), // .channel
.src_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_002_src3_ready), // sink0.ready
.sink0_valid (cmd_demux_002_src3_valid), // .valid
.sink0_channel (cmd_demux_002_src3_channel), // .channel
.sink0_data (cmd_demux_002_src3_data), // .data
.sink0_startofpacket (cmd_demux_002_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_002_src3_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_003_src1_ready), // sink1.ready
.sink1_valid (cmd_demux_003_src1_valid), // .valid
.sink1_channel (cmd_demux_003_src1_channel), // .channel
.sink1_data (cmd_demux_003_src1_data), // .data
.sink1_startofpacket (cmd_demux_003_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_003_src1_endofpacket), // .endofpacket
.sink2_ready (cmd_demux_004_src1_ready), // sink2.ready
.sink2_valid (cmd_demux_004_src1_valid), // .valid
.sink2_channel (cmd_demux_004_src1_channel), // .channel
.sink2_data (cmd_demux_004_src1_data), // .data
.sink2_startofpacket (cmd_demux_004_src1_startofpacket), // .startofpacket
.sink2_endofpacket (cmd_demux_004_src1_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_cmd_mux_004 cmd_mux_004 (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_004_src_ready), // src.ready
.src_valid (cmd_mux_004_src_valid), // .valid
.src_data (cmd_mux_004_src_data), // .data
.src_channel (cmd_mux_004_src_channel), // .channel
.src_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_003_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_003_src2_valid), // .valid
.sink0_channel (cmd_demux_003_src2_channel), // .channel
.sink0_data (cmd_demux_003_src2_data), // .data
.sink0_startofpacket (cmd_demux_003_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_003_src2_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_004_src2_ready), // sink1.ready
.sink1_valid (cmd_demux_004_src2_valid), // .valid
.sink1_channel (cmd_demux_004_src2_channel), // .channel
.sink1_data (cmd_demux_004_src2_data), // .data
.sink1_startofpacket (cmd_demux_004_src2_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_004_src2_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_cmd_mux_004 cmd_mux_005 (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_005_src_ready), // src.ready
.src_valid (cmd_mux_005_src_valid), // .valid
.src_data (cmd_mux_005_src_data), // .data
.src_channel (cmd_mux_005_src_channel), // .channel
.src_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_003_src3_ready), // sink0.ready
.sink0_valid (cmd_demux_003_src3_valid), // .valid
.sink0_channel (cmd_demux_003_src3_channel), // .channel
.sink0_data (cmd_demux_003_src3_data), // .data
.sink0_startofpacket (cmd_demux_003_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_003_src3_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_004_src3_ready), // sink1.ready
.sink1_valid (cmd_demux_004_src3_valid), // .valid
.sink1_channel (cmd_demux_004_src3_channel), // .channel
.sink1_data (cmd_demux_004_src3_data), // .data
.sink1_startofpacket (cmd_demux_004_src3_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_004_src3_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_rsp_demux rsp_demux (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_005_src_ready), // sink.ready
.sink_channel (router_005_src_channel), // .channel
.sink_data (router_005_src_data), // .data
.sink_startofpacket (router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (router_005_src_endofpacket), // .endofpacket
.sink_valid (router_005_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_src1_ready), // src1.ready
.src1_valid (rsp_demux_src1_valid), // .valid
.src1_data (rsp_demux_src1_data), // .data
.src1_channel (rsp_demux_src1_channel), // .channel
.src1_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_src1_endofpacket), // .endofpacket
.src2_ready (rsp_demux_src2_ready), // src2.ready
.src2_valid (rsp_demux_src2_valid), // .valid
.src2_data (rsp_demux_src2_data), // .data
.src2_channel (rsp_demux_src2_channel), // .channel
.src2_startofpacket (rsp_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (rsp_demux_src2_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_rsp_demux_001 rsp_demux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_006_src_ready), // sink.ready
.sink_channel (router_006_src_channel), // .channel
.sink_data (router_006_src_data), // .data
.sink_startofpacket (router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (router_006_src_endofpacket), // .endofpacket
.sink_valid (router_006_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_001_src1_ready), // src1.ready
.src1_valid (rsp_demux_001_src1_valid), // .valid
.src1_data (rsp_demux_001_src1_data), // .data
.src1_channel (rsp_demux_001_src1_channel), // .channel
.src1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_001_src1_endofpacket), // .endofpacket
.src2_ready (rsp_demux_001_src2_ready), // src2.ready
.src2_valid (rsp_demux_001_src2_valid), // .valid
.src2_data (rsp_demux_001_src2_data), // .data
.src2_channel (rsp_demux_001_src2_channel), // .channel
.src2_startofpacket (rsp_demux_001_src2_startofpacket), // .startofpacket
.src2_endofpacket (rsp_demux_001_src2_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_rsp_demux_002 rsp_demux_002 (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_007_src_ready), // sink.ready
.sink_channel (router_007_src_channel), // .channel
.sink_data (router_007_src_data), // .data
.sink_startofpacket (router_007_src_startofpacket), // .startofpacket
.sink_endofpacket (router_007_src_endofpacket), // .endofpacket
.sink_valid (router_007_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_rsp_demux_001 rsp_demux_003 (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_008_src_ready), // sink.ready
.sink_channel (router_008_src_channel), // .channel
.sink_data (router_008_src_data), // .data
.sink_startofpacket (router_008_src_startofpacket), // .startofpacket
.sink_endofpacket (router_008_src_endofpacket), // .endofpacket
.sink_valid (router_008_src_valid), // .valid
.src0_ready (rsp_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_demux_003_src0_valid), // .valid
.src0_data (rsp_demux_003_src0_data), // .data
.src0_channel (rsp_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_003_src1_ready), // src1.ready
.src1_valid (rsp_demux_003_src1_valid), // .valid
.src1_data (rsp_demux_003_src1_data), // .data
.src1_channel (rsp_demux_003_src1_channel), // .channel
.src1_startofpacket (rsp_demux_003_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_003_src1_endofpacket), // .endofpacket
.src2_ready (rsp_demux_003_src2_ready), // src2.ready
.src2_valid (rsp_demux_003_src2_valid), // .valid
.src2_data (rsp_demux_003_src2_data), // .data
.src2_channel (rsp_demux_003_src2_channel), // .channel
.src2_startofpacket (rsp_demux_003_src2_startofpacket), // .startofpacket
.src2_endofpacket (rsp_demux_003_src2_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_rsp_demux_004 rsp_demux_004 (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_009_src_ready), // sink.ready
.sink_channel (router_009_src_channel), // .channel
.sink_data (router_009_src_data), // .data
.sink_startofpacket (router_009_src_startofpacket), // .startofpacket
.sink_endofpacket (router_009_src_endofpacket), // .endofpacket
.sink_valid (router_009_src_valid), // .valid
.src0_ready (rsp_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_demux_004_src0_valid), // .valid
.src0_data (rsp_demux_004_src0_data), // .data
.src0_channel (rsp_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_004_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_004_src1_ready), // src1.ready
.src1_valid (rsp_demux_004_src1_valid), // .valid
.src1_data (rsp_demux_004_src1_data), // .data
.src1_channel (rsp_demux_004_src1_channel), // .channel
.src1_startofpacket (rsp_demux_004_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_004_src1_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_rsp_demux_004 rsp_demux_005 (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_010_src_ready), // sink.ready
.sink_channel (router_010_src_channel), // .channel
.sink_data (router_010_src_data), // .data
.sink_startofpacket (router_010_src_startofpacket), // .startofpacket
.sink_endofpacket (router_010_src_endofpacket), // .endofpacket
.sink_valid (router_010_src_valid), // .valid
.src0_ready (rsp_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_demux_005_src0_valid), // .valid
.src0_data (rsp_demux_005_src0_data), // .data
.src0_channel (rsp_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_005_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_005_src1_ready), // src1.ready
.src1_valid (rsp_demux_005_src1_valid), // .valid
.src1_data (rsp_demux_005_src1_data), // .data
.src1_channel (rsp_demux_005_src1_channel), // .channel
.src1_startofpacket (rsp_demux_005_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_005_src1_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_rsp_mux rsp_mux (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_rsp_mux rsp_mux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_src1_valid), // .valid
.sink0_channel (rsp_demux_src1_channel), // .channel
.sink0_data (rsp_demux_src1_data), // .data
.sink0_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src1_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_rsp_mux_002 rsp_mux_002 (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_002_src_ready), // src.ready
.src_valid (rsp_mux_002_src_valid), // .valid
.src_data (rsp_mux_002_src_data), // .data
.src_channel (rsp_mux_002_src_channel), // .channel
.src_startofpacket (rsp_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_ready), // sink0.ready
.sink0_valid (onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_valid), // .valid
.sink0_channel (onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_channel), // .channel
.sink0_data (onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_data), // .data
.sink0_startofpacket (onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink0_endofpacket (onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src0_valid), // .valid
.sink1_channel (rsp_demux_001_src0_channel), // .channel
.sink1_data (rsp_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src0_valid), // .valid
.sink2_channel (rsp_demux_002_src0_channel), // .channel
.sink2_data (rsp_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_demux_003_src0_valid), // .valid
.sink3_channel (rsp_demux_003_src0_channel), // .channel
.sink3_data (rsp_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_003_src0_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_rsp_mux_002 rsp_mux_003 (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_003_src_ready), // src.ready
.src_valid (rsp_mux_003_src_valid), // .valid
.src_data (rsp_mux_003_src_data), // .data
.src_channel (rsp_mux_003_src_channel), // .channel
.src_startofpacket (rsp_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_001_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_001_src1_valid), // .valid
.sink0_channel (rsp_demux_001_src1_channel), // .channel
.sink0_data (rsp_demux_001_src1_data), // .data
.sink0_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_001_src1_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_003_src1_ready), // sink1.ready
.sink1_valid (rsp_demux_003_src1_valid), // .valid
.sink1_channel (rsp_demux_003_src1_channel), // .channel
.sink1_data (rsp_demux_003_src1_data), // .data
.sink1_startofpacket (rsp_demux_003_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_003_src1_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_004_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_004_src0_valid), // .valid
.sink2_channel (rsp_demux_004_src0_channel), // .channel
.sink2_data (rsp_demux_004_src0_data), // .data
.sink2_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_004_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_005_src0_ready), // sink3.ready
.sink3_valid (rsp_demux_005_src0_valid), // .valid
.sink3_channel (rsp_demux_005_src0_channel), // .channel
.sink3_data (rsp_demux_005_src0_data), // .data
.sink3_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_005_src0_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_rsp_mux_002 rsp_mux_004 (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_004_src_ready), // src.ready
.src_valid (rsp_mux_004_src_valid), // .valid
.src_data (rsp_mux_004_src_data), // .data
.src_channel (rsp_mux_004_src_channel), // .channel
.src_startofpacket (rsp_mux_004_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_001_src2_ready), // sink0.ready
.sink0_valid (rsp_demux_001_src2_valid), // .valid
.sink0_channel (rsp_demux_001_src2_channel), // .channel
.sink0_data (rsp_demux_001_src2_data), // .data
.sink0_startofpacket (rsp_demux_001_src2_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_001_src2_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_003_src2_ready), // sink1.ready
.sink1_valid (rsp_demux_003_src2_valid), // .valid
.sink1_channel (rsp_demux_003_src2_channel), // .channel
.sink1_data (rsp_demux_003_src2_data), // .data
.sink1_startofpacket (rsp_demux_003_src2_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_003_src2_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_004_src1_ready), // sink2.ready
.sink2_valid (rsp_demux_004_src1_valid), // .valid
.sink2_channel (rsp_demux_004_src1_channel), // .channel
.sink2_data (rsp_demux_004_src1_data), // .data
.sink2_startofpacket (rsp_demux_004_src1_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_004_src1_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_005_src1_ready), // sink3.ready
.sink3_valid (rsp_demux_005_src1_valid), // .valid
.sink3_channel (rsp_demux_005_src1_channel), // .channel
.sink3_data (rsp_demux_005_src1_data), // .data
.sink3_startofpacket (rsp_demux_005_src1_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_005_src1_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (67),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (81),
.IN_PKT_BYTE_CNT_L (74),
.IN_PKT_TRANS_COMPRESSED_READ (68),
.IN_PKT_TRANS_WRITE (70),
.IN_PKT_BURSTWRAP_H (89),
.IN_PKT_BURSTWRAP_L (82),
.IN_PKT_BURST_SIZE_H (92),
.IN_PKT_BURST_SIZE_L (90),
.IN_PKT_RESPONSE_STATUS_H (125),
.IN_PKT_RESPONSE_STATUS_L (124),
.IN_PKT_TRANS_EXCLUSIVE (73),
.IN_PKT_BURST_TYPE_H (94),
.IN_PKT_BURST_TYPE_L (93),
.IN_PKT_ORI_BURST_SIZE_L (126),
.IN_PKT_ORI_BURST_SIZE_H (128),
.IN_ST_DATA_W (129),
.OUT_PKT_ADDR_H (103),
.OUT_PKT_ADDR_L (72),
.OUT_PKT_DATA_H (63),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (71),
.OUT_PKT_BYTEEN_L (64),
.OUT_PKT_BYTE_CNT_H (117),
.OUT_PKT_BYTE_CNT_L (110),
.OUT_PKT_TRANS_COMPRESSED_READ (104),
.OUT_PKT_BURST_SIZE_H (128),
.OUT_PKT_BURST_SIZE_L (126),
.OUT_PKT_RESPONSE_STATUS_H (161),
.OUT_PKT_RESPONSE_STATUS_L (160),
.OUT_PKT_TRANS_EXCLUSIVE (109),
.OUT_PKT_BURST_TYPE_H (130),
.OUT_PKT_BURST_TYPE_L (129),
.OUT_PKT_ORI_BURST_SIZE_L (162),
.OUT_PKT_ORI_BURST_SIZE_H (164),
.OUT_ST_DATA_W (165),
.ST_CHANNEL_W (6),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (0),
.PACKING (0),
.ENABLE_ADDRESS_ALIGNMENT (1)
) fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_demux_002_src0_valid), // sink.valid
.in_channel (cmd_demux_002_src0_channel), // .channel
.in_startofpacket (cmd_demux_002_src0_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_002_src0_endofpacket), // .endofpacket
.in_ready (cmd_demux_002_src0_ready), // .ready
.in_data (cmd_demux_002_src0_data), // .data
.out_endofpacket (fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_data), // .data
.out_channel (fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_channel), // .channel
.out_valid (fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_valid), // .valid
.out_ready (fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (103),
.IN_PKT_ADDR_L (72),
.IN_PKT_DATA_H (63),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (71),
.IN_PKT_BYTEEN_L (64),
.IN_PKT_BYTE_CNT_H (117),
.IN_PKT_BYTE_CNT_L (110),
.IN_PKT_TRANS_COMPRESSED_READ (104),
.IN_PKT_TRANS_WRITE (106),
.IN_PKT_BURSTWRAP_H (125),
.IN_PKT_BURSTWRAP_L (118),
.IN_PKT_BURST_SIZE_H (128),
.IN_PKT_BURST_SIZE_L (126),
.IN_PKT_RESPONSE_STATUS_H (161),
.IN_PKT_RESPONSE_STATUS_L (160),
.IN_PKT_TRANS_EXCLUSIVE (109),
.IN_PKT_BURST_TYPE_H (130),
.IN_PKT_BURST_TYPE_L (129),
.IN_PKT_ORI_BURST_SIZE_L (162),
.IN_PKT_ORI_BURST_SIZE_H (164),
.IN_ST_DATA_W (165),
.OUT_PKT_ADDR_H (67),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (81),
.OUT_PKT_BYTE_CNT_L (74),
.OUT_PKT_TRANS_COMPRESSED_READ (68),
.OUT_PKT_BURST_SIZE_H (92),
.OUT_PKT_BURST_SIZE_L (90),
.OUT_PKT_RESPONSE_STATUS_H (125),
.OUT_PKT_RESPONSE_STATUS_L (124),
.OUT_PKT_TRANS_EXCLUSIVE (73),
.OUT_PKT_BURST_TYPE_H (94),
.OUT_PKT_BURST_TYPE_L (93),
.OUT_PKT_ORI_BURST_SIZE_L (126),
.OUT_PKT_ORI_BURST_SIZE_H (128),
.OUT_ST_DATA_W (129),
.ST_CHANNEL_W (6),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (0),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (1)
) onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (rsp_demux_src2_valid), // sink.valid
.in_channel (rsp_demux_src2_channel), // .channel
.in_startofpacket (rsp_demux_src2_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_src2_endofpacket), // .endofpacket
.in_ready (rsp_demux_src2_ready), // .ready
.in_data (rsp_demux_src2_data), // .data
.out_endofpacket (onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_data), // .data
.out_channel (onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_channel), // .channel
.out_valid (onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_valid), // .valid
.out_ready (onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
soc_system_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (66),
.inUsePackets (0),
.inDataWidth (66),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (66),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter (
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
.in_rst_0_reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (onchip_memory2_0_s1_agent_rdata_fifo_out_data), // in_0.data
.in_0_valid (onchip_memory2_0_s1_agent_rdata_fifo_out_valid), // .valid
.in_0_ready (onchip_memory2_0_s1_agent_rdata_fifo_out_ready), // .ready
.out_0_data (avalon_st_adapter_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_out_0_error) // .error
);
soc_system_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_001 (
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
.in_rst_0_reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_data), // in_0.data
.in_0_valid (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_valid), // .valid
.in_0_ready (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_ready), // .ready
.out_0_data (avalon_st_adapter_001_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_001_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_001_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_001_out_0_error) // .error
);
soc_system_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_002 (
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
.in_rst_0_reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_out_data), // in_0.data
.in_0_valid (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_out_valid), // .valid
.in_0_ready (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_out_ready), // .ready
.out_0_data (avalon_st_adapter_002_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_002_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_002_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_002_out_0_error) // .error
);
soc_system_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_003 (
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
.in_rst_0_reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (sysid_qsys_control_slave_agent_rdata_fifo_out_data), // in_0.data
.in_0_valid (sysid_qsys_control_slave_agent_rdata_fifo_out_valid), // .valid
.in_0_ready (sysid_qsys_control_slave_agent_rdata_fifo_out_ready), // .ready
.out_0_data (avalon_st_adapter_003_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_003_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_003_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_003_out_0_error) // .error
);
soc_system_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_004 (
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
.in_rst_0_reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (reg32_avalon_interface_0_avalon_slave_0_agent_rdata_fifo_out_data), // in_0.data
.in_0_valid (reg32_avalon_interface_0_avalon_slave_0_agent_rdata_fifo_out_valid), // .valid
.in_0_ready (reg32_avalon_interface_0_avalon_slave_0_agent_rdata_fifo_out_ready), // .ready
.out_0_data (avalon_st_adapter_004_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_004_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_004_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_004_out_0_error) // .error
);
soc_system_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_005 (
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
.in_rst_0_reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (rc4_avalon_interface_0_avalon_slave_0_agent_rdata_fifo_out_data), // in_0.data
.in_0_valid (rc4_avalon_interface_0_avalon_slave_0_agent_rdata_fifo_out_valid), // .valid
.in_0_ready (rc4_avalon_interface_0_avalon_slave_0_agent_rdata_fifo_out_ready), // .ready
.out_0_data (avalon_st_adapter_005_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_005_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_005_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_005_out_0_error) // .error
);
endmodule
|
//wishbone master interconnect testbench
/*
Distributed under the MIT licesnse.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/* Log
04/16/2013
-implement naming convention
08/30/2012
-Major overhall of the testbench
-modfied the way reads and writes happen, now each write requires the
number of 32-bit data packets even if the user sends only 1
-there is no more streaming as the data_count will implicity declare
that a read/write is streaming
-added the ih_reset which has not been formally defined within the
system, but will more than likely reset the entire statemachine
11/12/2011
-overhauled the design to behave more similar to a real I/O handler
-changed the timeout to 40 seconds to allow the wishbone master to catch
nacks
11/08/2011
-added interrupt support
*/
`timescale 1 ns/1 ps
`define TIMEOUT_COUNT 40
`define INPUT_FILE "sim/master_input_test_data.txt"
`define OUTPUT_FILE "sim/master_output_test_data.txt"
`define CLK_HALF_PERIOD 10
`define CLK_PERIOD (2 * `CLK_HALF_PERIOD)
`define SLEEP_HALF_CLK #(`CLK_HALF_PERIOD)
`define SLEEP_FULL_CLK #(`CLK_PERIOD)
//Sleep a number of clock cycles
`define SLEEP_CLK(x) #(x * `CLK_PERIOD)
module wishbone_master_tb (
);
//Virtual Host Interface Signals
reg clk = 0;
reg rst = 0;
wire w_master_ready;
reg r_in_ready = 0;
reg [31:0] r_in_command = 32'h00000000;
reg [31:0] r_in_address = 32'h00000000;
reg [31:0] r_in_data = 32'h00000000;
reg [27:0] r_in_data_count = 0;
reg r_out_ready = 0;
wire w_out_en;
wire [31:0] w_out_status;
wire [31:0] w_out_address;
wire [31:0] w_out_data;
wire [27:0] w_out_data_count;
reg r_ih_reset = 0;
//wishbone signals
wire w_wbp_we;
wire w_wbp_cyc;
wire w_wbp_stb;
wire [3:0] w_wbp_sel;
wire [31:0] w_wbp_adr;
wire [31:0] w_wbp_dat_o;
wire [31:0] w_wbp_dat_i;
wire w_wbp_ack;
wire w_wbp_int;
//Wishbone master mem bus
wire w_wbm_we;
wire w_wbm_cyc;
wire w_wbm_stb;
wire [3:0] w_wbm_sel;
wire [31:0] w_wbm_adr;
wire [31:0] w_wbm_dat_o;
wire [31:0] w_wbm_dat_i;
wire w_wbm_ack;
wire w_wbm_int;
//Wishbone Slave 0 (DRT) signals
wire w_wbs0_we;
wire w_wbs0_cyc;
wire [31:0] w_wbs0_dat_o;
wire w_wbs0_stb;
wire [3:0] w_wbs0_sel;
wire w_wbs0_ack;
wire [31:0] w_wbs0_dat_i;
wire [31:0] w_wbs0_adr;
wire w_wbs0_int;
//wishbone slave 1 (Unit Under Test) signals
wire w_wbs1_we;
wire w_wbs1_cyc;
wire w_wbs1_stb;
wire [3:0] w_wbs1_sel;
wire w_wbs1_ack;
wire [31:0] w_wbs1_dat_i;
wire [31:0] w_wbs1_dat_o;
wire [31:0] w_wbs1_adr;
wire w_wbs1_int;
//wishbone slave 0 signals
wire mem0_we_o;
wire mem0_cyc_o;
wire [31:0] mem0_dat_o;
wire mem0_stb_o;
wire [3:0] mem0_sel_o;
wire mem0_ack_i;
wire [31:0] mem0_dat_i;
wire [31:0] mem0_adr_o;
wire mem0_int_i;
wire sdram_clk;
wire sdram_cke;
wire sdram_cs_n;
wire sdram_ras;
wire sdram_cas;
wire sdram_we;
wire [11:0] sdram_addr;
wire [1:0] sdram_bank;
wire [15:0] sdram_data;
wire [1:0] sdram_data_mask;
wire sdram_ready;
reg [15:0] sdram_in_data;
wire w_arb0_i_wbs_stb;
wire w_arb0_i_wbs_cyc;
wire w_arb0_i_wbs_we;
wire [3:0] w_arb0_i_wbs_sel;
wire [31:0] w_arb0_i_wbs_dat;
wire [31:0] w_arb0_o_wbs_dat;
wire [31:0] w_arb0_i_wbs_adr;
wire w_arb0_o_wbs_ack;
wire w_arb0_o_wbs_int;
wire dma_rdr_mem_o_stb;
wire dma_rdr_mem_o_cyc;
wire dma_rdr_mem_o_we;
wire [3:0] dma_rdr_mem_o_sel;
wire [31:0] dma_rdr_mem_o_dat;
wire [31:0] dma_rdr_mem_o_adr;
wire [31:0] dma_rdr_mem_i_dat;
wire dma_rdr_mem_i_ack;
wire dma_rdr_mem_i_int;
//Local Parameters
localparam WAIT_FOR_SDRAM = 8'h00;
localparam IDLE = 8'h01;
localparam SEND_COMMAND = 8'h02;
localparam MASTER_READ_COMMAND = 8'h03;
localparam RESET = 8'h04;
localparam PING_RESPONSE = 8'h05;
localparam WRITE_DATA = 8'h06;
localparam WRITE_RESPONSE = 8'h07;
localparam GET_WRITE_DATA = 8'h08;
localparam READ_RESPONSE = 8'h09;
localparam READ_MORE_DATA = 8'h0A;
localparam FINISHED = 8'h0B;
//Registers/Wires/Simulation Integers
integer fd_in;
integer fd_out;
integer read_count;
integer timeout_count;
integer ch;
integer data_count;
reg [3:0] state = IDLE;
reg prev_int = 0;
reg execute_command;
reg command_finished;
reg request_more_data;
reg request_more_data_ack;
reg [27:0] data_write_count;
reg [27:0] data_read_count;
//mem slave 0
wire w_sm0_i_wbs_we;
wire w_sm0_i_wbs_cyc;
wire [31:0] w_sm0_i_wbs_dat;
wire [31:0] w_sm0_o_wbs_dat;
wire [31:0] w_sm0_i_wbs_adr;
wire w_sm0_i_wbs_stb;
wire [3:0] w_sm0_i_wbs_sel;
wire w_sm0_o_wbs_ack;
wire w_sm0_o_wbs_int;
wire w_mem_we_o;
wire w_mem_cyc_o;
wire w_mem_stb_o;
wire [3:0] w_mem_sel_o;
wire [31:0] w_mem_adr_o;
wire [31:0] w_mem_dat_i;
wire [31:0] w_mem_dat_o;
wire w_mem_ack_i;
wire w_mem_int_i;
wire w_dut_rst;
wire w_flash;
wire w_dut_in_clk;
wire w_pix_clk;
wire w_flash_strobe;
wire w_vsync;
wire w_hsync;
wire [7:0] w_pix_data;
wire start;
assign w_wbs0_int = 0;
//Submodules
wishbone_master wm (
.clk (clk ),
.rst (rst ),
.i_ih_rst (r_ih_reset ),
.i_ready (r_in_ready ),
.i_command (r_in_command ),
.i_address (r_in_address ),
.i_data (r_in_data ),
.i_data_count (r_in_data_count ),
.i_out_ready (r_out_ready ),
.o_en (w_out_en ),
.o_status (w_out_status ),
.o_address (w_out_address ),
.o_data (w_out_data ),
.o_data_count (w_out_data_count ),
.o_master_ready (w_master_ready ),
.o_per_we (w_wbp_we ),
.o_per_adr (w_wbp_adr ),
.o_per_dat (w_wbp_dat_i ),
.i_per_dat (w_wbp_dat_o ),
.o_per_stb (w_wbp_stb ),
.o_per_cyc (w_wbp_cyc ),
.o_per_sel (w_wbp_sel ),
.i_per_ack (w_wbp_ack ),
.i_per_int (w_wbp_int ),
//memory interconnect signals
.o_mem_we (w_mem_we_o ),
.o_mem_adr (w_mem_adr_o ),
.o_mem_dat (w_mem_dat_o ),
.i_mem_dat (w_mem_dat_i ),
.o_mem_stb (w_mem_stb_o ),
.o_mem_cyc (w_mem_cyc_o ),
.o_mem_sel (w_mem_sel_o ),
.i_mem_ack (w_mem_ack_i ),
.i_mem_int (w_mem_int_i )
);
wishbone_interconnect wi (
.clk (clk ),
.rst (rst ),
.i_m_we (w_wbp_we ),
.i_m_cyc (w_wbp_cyc ),
.i_m_stb (w_wbp_stb ),
.o_m_ack (w_wbp_ack ),
.i_m_dat (w_wbp_dat_i ),
.o_m_dat (w_wbp_dat_o ),
.i_m_adr (w_wbp_adr ),
.o_m_int (w_wbp_int ),
.o_s0_we (w_wbs0_we ),
.o_s0_cyc (w_wbs0_cyc ),
.o_s0_stb (w_wbs0_stb ),
.i_s0_ack (w_wbs0_ack ),
.o_s0_dat (w_wbs0_dat_i ),
.i_s0_dat (w_wbs0_dat_o ),
.o_s0_adr (w_wbs0_adr ),
.i_s0_int (w_wbs0_int ),
.o_s1_we (w_wbs1_we ),
.o_s1_cyc (w_wbs1_cyc ),
.o_s1_stb (w_wbs1_stb ),
.i_s1_ack (w_wbs1_ack ),
.o_s1_dat (w_wbs1_dat_i ),
.i_s1_dat (w_wbs1_dat_o ),
.o_s1_adr (w_wbs1_adr ),
.i_s1_int (w_wbs1_int )
);
wishbone_mem_interconnect wmi (
.clk (clk ),
.rst (rst ),
//master
.i_m_we (w_mem_we_o ),
.i_m_cyc (w_mem_cyc_o ),
.i_m_stb (w_mem_stb_o ),
.i_m_sel (w_mem_sel_o ),
.o_m_ack (w_mem_ack_i ),
.i_m_dat (w_mem_dat_o ),
.o_m_dat (w_mem_dat_i ),
.i_m_adr (w_mem_adr_o ),
.o_m_int (w_mem_int_i ),
//slave 0
.o_s0_we (w_sm0_i_wbs_we ),
.o_s0_cyc (w_sm0_i_wbs_cyc ),
.o_s0_stb (w_sm0_i_wbs_stb ),
.o_s0_sel (w_sm0_i_wbs_sel ),
.i_s0_ack (w_sm0_o_wbs_ack ),
.o_s0_dat (w_sm0_i_wbs_dat ),
.i_s0_dat (w_sm0_o_wbs_dat ),
.o_s0_adr (w_sm0_i_wbs_adr ),
.i_s0_int (w_sm0_o_wbs_int )
);
//slave 1
wb_dma_writer s1 (
.clk (clk ),
.rst (rst ),
.i_wbs_we (w_wbs1_we ),
.i_wbs_cyc (w_wbs1_cyc ),
.i_wbs_dat (w_wbs1_dat_i ),
.i_wbs_stb (w_wbs1_stb ),
.o_wbs_ack (w_wbs1_ack ),
.o_wbs_dat (w_wbs1_dat_o ),
.i_wbs_adr (w_wbs1_adr ),
.o_wbs_int (w_wbs1_int ),
.mem_o_cyc (dma_rdr_mem_o_cyc ),
.mem_o_stb (dma_rdr_mem_o_stb ),
.mem_o_we (dma_rdr_mem_o_we ),
.mem_i_ack (dma_rdr_mem_i_ack ),
.mem_o_sel (dma_rdr_mem_o_sel ),
.mem_o_adr (dma_rdr_mem_o_adr ),
.mem_o_dat (dma_rdr_mem_o_dat ),
.mem_i_dat (dma_rdr_mem_i_dat ),
.mem_i_int (dma_rdr_mem_i_int )
);
mt48lc4m16
ram (
.A11 (sdram_addr[11] ),
.A10 (sdram_addr[10] ),
.A9 (sdram_addr[9] ),
.A8 (sdram_addr[8] ),
.A7 (sdram_addr[7] ),
.A6 (sdram_addr[6] ),
.A5 (sdram_addr[5] ),
.A4 (sdram_addr[4] ),
.A3 (sdram_addr[3] ),
.A2 (sdram_addr[2] ),
.A1 (sdram_addr[1] ),
.A0 (sdram_addr[0] ),
.DQ15 (sdram_data[15] ),
.DQ14 (sdram_data[14] ),
.DQ13 (sdram_data[13] ),
.DQ12 (sdram_data[12] ),
.DQ11 (sdram_data[11] ),
.DQ10 (sdram_data[10] ),
.DQ9 (sdram_data[9] ),
.DQ8 (sdram_data[8] ),
.DQ7 (sdram_data[7] ),
.DQ6 (sdram_data[6] ),
.DQ5 (sdram_data[5] ),
.DQ4 (sdram_data[4] ),
.DQ3 (sdram_data[3] ),
.DQ2 (sdram_data[2] ),
.DQ1 (sdram_data[1] ),
.DQ0 (sdram_data[0] ),
.BA0 (sdram_bank[0] ),
.BA1 (sdram_bank[1] ),
.DQMH (sdram_data_mask[1] ),
.DQML (sdram_data_mask[0] ),
.CLK (sdram_clk ),
.CKE (sdram_cke ),
.WENeg (sdram_we ),
.RASNeg (sdram_ras ),
.CSNeg (sdram_cs_n ),
.CASNeg (sdram_cas )
);
//mem 0
wb_sdram m0 (
.clk (clk ),
.rst (rst ),
.i_wbs_cyc (w_arb0_i_wbs_cyc ),
.i_wbs_dat (w_arb0_i_wbs_dat ),
.i_wbs_we (w_arb0_i_wbs_we ),
.i_wbs_stb (w_arb0_i_wbs_stb ),
.i_wbs_sel (w_arb0_i_wbs_sel ),
.i_wbs_adr (w_arb0_i_wbs_adr ),
.o_wbs_dat (w_arb0_o_wbs_dat ),
.o_wbs_ack (w_arb0_o_wbs_ack ),
.o_wbs_int (w_arb0_o_wbs_int ),
.o_sdram_clk (sdram_clk ),
.o_sdram_cke (sdram_cke ),
.o_sdram_cs_n (sdram_cs_n ),
.o_sdram_ras (sdram_ras ),
.o_sdram_cas (sdram_cas ),
.o_sdram_we (sdram_we ),
.o_sdram_addr (sdram_addr ),
.o_sdram_bank (sdram_bank ),
.io_sdram_data (sdram_data ),
.o_sdram_data_mask (sdram_data_mask ),
.o_sdram_ready (sdram_ready )
);
arbiter_2_masters arb0 (
.clk (clk ),
.rst (rst ),
//masters
.i_m0_we (dma_rdr_mem_o_we ),
.i_m0_stb (dma_rdr_mem_o_stb ),
.i_m0_cyc (dma_rdr_mem_o_cyc ),
.i_m0_sel (dma_rdr_mem_o_sel ),
.i_m0_dat (dma_rdr_mem_o_dat ),
.i_m0_adr (dma_rdr_mem_o_adr ),
.o_m0_dat (dma_rdr_mem_i_dat ),
.o_m0_ack (dma_rdr_mem_i_ack ),
.o_m0_int (dma_rdr_mem_i_int ),
.i_m1_we (w_sm0_i_wbs_we ),
.i_m1_stb (w_sm0_i_wbs_stb ),
.i_m1_cyc (w_sm0_i_wbs_cyc ),
.i_m1_sel (w_sm0_i_wbs_sel ),
.i_m1_dat (w_sm0_i_wbs_dat ),
.i_m1_adr (w_sm0_i_wbs_adr ),
.o_m1_dat (w_sm0_o_wbs_dat ),
.o_m1_ack (w_sm0_o_wbs_ack ),
.o_m1_int (w_sm0_o_wbs_int ),
//slave
.o_s_we (w_arb0_i_wbs_we ),
.o_s_stb (w_arb0_i_wbs_stb ),
.o_s_cyc (w_arb0_i_wbs_cyc ),
.o_s_sel (w_arb0_i_wbs_sel ),
.o_s_dat (w_arb0_i_wbs_dat ),
.o_s_adr (w_arb0_i_wbs_adr ),
.i_s_dat (w_arb0_o_wbs_dat ),
.i_s_ack (w_arb0_o_wbs_ack ),
.i_s_int (w_arb0_o_wbs_int )
);
assign w_wbs0_ack = 0;
assign w_wbs0_dat_o = 0;
assign start = sdram_ready;
always #`CLK_HALF_PERIOD clk = ~clk;
initial begin
fd_out = 0;
read_count = 0;
data_count = 0;
timeout_count = 0;
request_more_data_ack <= 0;
execute_command <= 0;
$dumpfile ("design.vcd");
$dumpvars (0, wishbone_master_tb);
fd_in = $fopen(`INPUT_FILE, "r");
fd_out = $fopen(`OUTPUT_FILE, "w");
`SLEEP_HALF_CLK;
rst <= 0;
`SLEEP_CLK(100);
rst <= 1;
//clear the handler signals
r_in_ready <= 0;
r_in_command <= 0;
r_in_address <= 32'h0;
r_in_data <= 32'h0;
r_in_data_count <= 0;
r_out_ready <= 0;
//clear wishbone signals
`SLEEP_CLK(10);
rst <= 0;
r_out_ready <= 1;
if (fd_in == 0) begin
$display ("TB: input stimulus file was not found");
end
else begin
//while there is still data to be read from the file
while (!$feof(fd_in)) begin
//read in a command
read_count = $fscanf (fd_in, "%h:%h:%h:%h\n",
r_in_data_count,
r_in_command,
r_in_address,
r_in_data);
//Handle Frindge commands/comments
if (read_count != 4) begin
if (read_count == 0) begin
ch = $fgetc(fd_in);
if (ch == "\#") begin
//$display ("Eat a comment");
//Eat the line
while (ch != "\n") begin
ch = $fgetc(fd_in);
end
$display ("");
end
else begin
$display ("Error unrecognized line: %h" % ch);
//Eat the line
while (ch != "\n") begin
ch = $fgetc(fd_in);
end
end
end
else if (read_count == 1) begin
$display ("Sleep for %h Clock cycles", r_in_data_count);
`SLEEP_CLK(r_in_data_count);
$display ("Sleep Finished");
end
else begin
$display ("Error: read_count = %h != 4", read_count);
$display ("Character: %h", ch);
end
end
else begin
case (r_in_command)
0: $display ("TB: Executing PING commad");
1: $display ("TB: Executing WRITE command");
2: $display ("TB: Executing READ command");
3: $display ("TB: Executing RESET command");
endcase
$display ("Execute Command");
execute_command <= 1;
`SLEEP_CLK(1);
while (~command_finished) begin
request_more_data_ack <= 0;
if ((r_in_command & 32'h0000FFFF) == 1) begin
if (request_more_data && ~request_more_data_ack) begin
read_count = $fscanf(fd_in, "%h\n", r_in_data);
$display ("TB: reading a new double word: %h", r_in_data);
request_more_data_ack <= 1;
end
end
//so time porgresses wait a tick
`SLEEP_CLK(1);
//this doesn't need to be here, but there is a weird behavior in iverilog
//that wont allow me to put a delay in right before an 'end' statement
//execute_command <= 1;
end //while command is not finished
execute_command <= 0;
while (command_finished) begin
$display ("Command Finished");
`SLEEP_CLK(1);
execute_command <= 0;
end
`SLEEP_CLK(50);
$display ("TB: finished command");
end //end read_count == 4
end //end while ! eof
end //end not reset
`SLEEP_CLK(50);
$fclose (fd_in);
$fclose (fd_out);
$finish();
end
//initial begin
// $monitor("%t, state: %h", $time, state);
//end
//initial begin
// $monitor("%t, data: %h, state: %h, execute command: %h", $time, w_wbm_dat_o, state, execute_command);
//end
initial begin
//$monitor("%t, state: %h, execute: %h, cmd_fin: %h", $time, state, execute_command, command_finished);
//$monitor("%t, state: %h, write_size: %d, write_count: %d, execute: %h", $time, state, r_in_data_count, data_write_count, execute_command);
end
always @ (posedge clk) begin
if (rst) begin
state <= WAIT_FOR_SDRAM;
request_more_data <= 0;
timeout_count <= 0;
prev_int <= 0;
r_ih_reset <= 0;
data_write_count <= 0;
data_read_count <= 1;
command_finished <= 0;
end
else begin
r_ih_reset <= 0;
r_in_ready <= 0;
r_out_ready <= 1;
command_finished <= 0;
//Countdown the NACK timeout
if (execute_command && timeout_count < `TIMEOUT_COUNT) begin
timeout_count <= timeout_count + 1;
end
if (execute_command && timeout_count >= `TIMEOUT_COUNT) begin
case (r_in_command)
0: $display ("TB: Master timed out while executing PING commad");
1: $display ("TB: Master timed out while executing WRITE command");
2: $display ("TB: Master timed out while executing READ command");
3: $display ("TB: Master timed out while executing RESET command");
endcase
command_finished <= 1;
state <= IDLE;
timeout_count <= 0;
end //end reached the end of a timeout
case (state)
WAIT_FOR_SDRAM: begin
timeout_count <= 0;
r_in_ready <= 0;
//Uncomment 'start' conditional to wait for SDRAM to finish starting
//up
if (start) begin
$display ("TB: sdram is ready");
state <= IDLE;
end
end
IDLE: begin
timeout_count <= 0;
command_finished <= 0;
data_write_count <= 1;
if (execute_command && !command_finished) begin
state <= SEND_COMMAND;
end
data_read_count <= 1;
end
SEND_COMMAND: begin
timeout_count <= 0;
if (w_master_ready) begin
r_in_ready <= 1;
state <= MASTER_READ_COMMAND;
end
end
MASTER_READ_COMMAND: begin
r_in_ready <= 1;
if (!w_master_ready) begin
r_in_ready <= 0;
case (r_in_command & 32'h0000FFFF)
0: begin
state <= PING_RESPONSE;
end
1: begin
if (r_in_data_count > 1) begin
$display ("TB:\tWrote Double Word %d: %h", data_write_count, r_in_data);
if (data_write_count < r_in_data_count) begin
state <= WRITE_DATA;
timeout_count <= 0;
data_write_count<= data_write_count + 1;
end
else begin
$display ("TB: Finished Writing: %d 32bit words of %d size", r_in_data_count, data_write_count);
state <= WRITE_RESPONSE;
end
end
else begin
$display ("TB:\tWrote Double Word %d: %h", data_write_count, r_in_data);
$display ("TB: Finished Writing: %d 32bit words of %d size", r_in_data_count, data_write_count);
state <= WRITE_RESPONSE;
end
end
2: begin
state <= READ_RESPONSE;
end
3: begin
state <= RESET;
end
endcase
end
end
RESET: begin
r_ih_reset <= 1;
state <= RESET;
end
PING_RESPONSE: begin
if (w_out_en) begin
if (w_out_status[7:0] == 8'hFF) begin
$display ("TB: Ping Response Good");
end
else begin
$display ("TB: Ping Response Bad (Malformed response: %h)", w_out_status);
end
$display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data);
state <= FINISHED;
end
end
WRITE_DATA: begin
if (!r_in_ready && w_master_ready) begin
state <= GET_WRITE_DATA;
request_more_data <= 1;
end
end
WRITE_RESPONSE: begin
$display ("In Write Response");
if (w_out_en) begin
if (w_out_status[7:0] == (~(8'h01))) begin
$display ("TB: Write Response Good");
end
else begin
$display ("TB: Write Response Bad (Malformed response: %h)", w_out_status);
end
$display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data);
state <= FINISHED;
end
end
GET_WRITE_DATA: begin
if (request_more_data_ack) begin
request_more_data <= 0;
r_in_ready <= 1;
state <= SEND_COMMAND;
end
end
READ_RESPONSE: begin
if (w_out_en) begin
if (w_out_status[7:0] == (~(8'h02))) begin
$display ("TB: Read Response Good");
if (w_out_data_count > 0) begin
if (data_read_count < w_out_data_count) begin
state <= READ_MORE_DATA;
timeout_count <= 0;
data_read_count <= data_read_count + 1;
end
else begin
state <= FINISHED;
end
end
end
else begin
$display ("TB: Read Response Bad (Malformed response: %h)", w_out_status);
state <= FINISHED;
end
$display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data);
end
end
READ_MORE_DATA: begin
if (w_out_en) begin
timeout_count <= 0;
r_out_ready <= 0;
$display ("TB: Read a 32bit data packet");
$display ("TB: \tRead Data: %h", w_out_data);
data_read_count <= data_read_count + 1;
end
if (data_read_count >= r_in_data_count) begin
state <= FINISHED;
end
end
FINISHED: begin
command_finished <= 1;
if (!execute_command) begin
$display ("Execute Command is low");
command_finished <= 0;
state <= IDLE;
end
end
endcase
if (w_out_en && w_out_status == `PERIPH_INTERRUPT) begin
$display("TB: Output Handler Recieved interrupt");
$display("TB:\tcommand: %h", w_out_status);
$display("TB:\taddress: %h", w_out_address);
$display("TB:\tdata: %h", w_out_data);
end
end//not reset
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: cpx_buf_pm_even.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
`include "sys.h"
`include "iop.h"
module cpx_buf_pm_even(/*AUTOARG*/
// Outputs
arbcp0_cpxdp_grant_ca, arbcp0_cpxdp_q0_hold_ca_l,
arbcp0_cpxdp_qsel0_ca, arbcp0_cpxdp_qsel1_ca_l,
arbcp0_cpxdp_shift_cx, arbcp2_cpxdp_grant_ca,
arbcp2_cpxdp_q0_hold_ca_l, arbcp2_cpxdp_qsel0_ca,
arbcp2_cpxdp_qsel1_ca_l, arbcp2_cpxdp_shift_cx,
arbcp4_cpxdp_grant_ca, arbcp4_cpxdp_q0_hold_ca_l,
arbcp4_cpxdp_qsel0_ca, arbcp4_cpxdp_qsel1_ca_l,
arbcp4_cpxdp_shift_cx, arbcp6_cpxdp_grant_ca,
arbcp6_cpxdp_q0_hold_ca_l, arbcp6_cpxdp_qsel0_ca,
arbcp6_cpxdp_qsel1_ca_l, arbcp6_cpxdp_shift_cx,
// Inputs
arbcp0_cpxdp_grant_arbbf_ca_l, arbcp0_cpxdp_q0_hold_arbbf_ca,
arbcp0_cpxdp_qsel0_arbbf_ca_l, arbcp0_cpxdp_qsel1_arbbf_ca,
arbcp0_cpxdp_shift_arbbf_cx_l, arbcp2_cpxdp_grant_arbbf_ca_l,
arbcp2_cpxdp_q0_hold_arbbf_ca, arbcp2_cpxdp_qsel0_arbbf_ca_l,
arbcp2_cpxdp_qsel1_arbbf_ca, arbcp2_cpxdp_shift_arbbf_cx_l,
arbcp4_cpxdp_grant_arbbf_ca_l, arbcp4_cpxdp_q0_hold_arbbf_ca,
arbcp4_cpxdp_qsel0_arbbf_ca_l, arbcp4_cpxdp_qsel1_arbbf_ca,
arbcp4_cpxdp_shift_arbbf_cx_l, arbcp6_cpxdp_grant_arbbf_ca_l,
arbcp6_cpxdp_q0_hold_arbbf_ca, arbcp6_cpxdp_qsel0_arbbf_ca_l,
arbcp6_cpxdp_qsel1_arbbf_ca, arbcp6_cpxdp_shift_arbbf_cx_l
);
output arbcp0_cpxdp_grant_ca ;
output arbcp0_cpxdp_q0_hold_ca_l ;
output arbcp0_cpxdp_qsel0_ca ;
output arbcp0_cpxdp_qsel1_ca_l ;
output arbcp0_cpxdp_shift_cx ;
output arbcp2_cpxdp_grant_ca ;
output arbcp2_cpxdp_q0_hold_ca_l ;
output arbcp2_cpxdp_qsel0_ca ;
output arbcp2_cpxdp_qsel1_ca_l ;
output arbcp2_cpxdp_shift_cx ;
output arbcp4_cpxdp_grant_ca ;
output arbcp4_cpxdp_q0_hold_ca_l ;
output arbcp4_cpxdp_qsel0_ca ;
output arbcp4_cpxdp_qsel1_ca_l ;
output arbcp4_cpxdp_shift_cx ;
output arbcp6_cpxdp_grant_ca ;
output arbcp6_cpxdp_q0_hold_ca_l ;
output arbcp6_cpxdp_qsel0_ca ;
output arbcp6_cpxdp_qsel1_ca_l ;
output arbcp6_cpxdp_shift_cx ;
input arbcp0_cpxdp_grant_arbbf_ca_l;
input arbcp0_cpxdp_q0_hold_arbbf_ca;
input arbcp0_cpxdp_qsel0_arbbf_ca_l;
input arbcp0_cpxdp_qsel1_arbbf_ca;
input arbcp0_cpxdp_shift_arbbf_cx_l;
input arbcp2_cpxdp_grant_arbbf_ca_l;
input arbcp2_cpxdp_q0_hold_arbbf_ca;
input arbcp2_cpxdp_qsel0_arbbf_ca_l;
input arbcp2_cpxdp_qsel1_arbbf_ca;
input arbcp2_cpxdp_shift_arbbf_cx_l;
input arbcp4_cpxdp_grant_arbbf_ca_l;
input arbcp4_cpxdp_q0_hold_arbbf_ca;
input arbcp4_cpxdp_qsel0_arbbf_ca_l;
input arbcp4_cpxdp_qsel1_arbbf_ca;
input arbcp4_cpxdp_shift_arbbf_cx_l;
input arbcp6_cpxdp_grant_arbbf_ca_l;
input arbcp6_cpxdp_q0_hold_arbbf_ca;
input arbcp6_cpxdp_qsel0_arbbf_ca_l;
input arbcp6_cpxdp_qsel1_arbbf_ca;
input arbcp6_cpxdp_shift_arbbf_cx_l;
assign arbcp0_cpxdp_grant_ca = ~arbcp0_cpxdp_grant_arbbf_ca_l;
assign arbcp0_cpxdp_q0_hold_ca_l = ~arbcp0_cpxdp_q0_hold_arbbf_ca;
assign arbcp0_cpxdp_qsel0_ca = ~arbcp0_cpxdp_qsel0_arbbf_ca_l;
assign arbcp0_cpxdp_qsel1_ca_l = ~arbcp0_cpxdp_qsel1_arbbf_ca;
assign arbcp0_cpxdp_shift_cx = ~arbcp0_cpxdp_shift_arbbf_cx_l;
assign arbcp2_cpxdp_grant_ca = ~arbcp2_cpxdp_grant_arbbf_ca_l;
assign arbcp2_cpxdp_q0_hold_ca_l = ~arbcp2_cpxdp_q0_hold_arbbf_ca;
assign arbcp2_cpxdp_qsel0_ca = ~arbcp2_cpxdp_qsel0_arbbf_ca_l;
assign arbcp2_cpxdp_qsel1_ca_l = ~arbcp2_cpxdp_qsel1_arbbf_ca;
assign arbcp2_cpxdp_shift_cx = ~arbcp2_cpxdp_shift_arbbf_cx_l;
assign arbcp4_cpxdp_grant_ca = ~arbcp4_cpxdp_grant_arbbf_ca_l;
assign arbcp4_cpxdp_q0_hold_ca_l = ~arbcp4_cpxdp_q0_hold_arbbf_ca;
assign arbcp4_cpxdp_qsel0_ca = ~arbcp4_cpxdp_qsel0_arbbf_ca_l;
assign arbcp4_cpxdp_qsel1_ca_l = ~arbcp4_cpxdp_qsel1_arbbf_ca;
assign arbcp4_cpxdp_shift_cx = ~arbcp4_cpxdp_shift_arbbf_cx_l;
assign arbcp6_cpxdp_grant_ca = ~arbcp6_cpxdp_grant_arbbf_ca_l;
assign arbcp6_cpxdp_q0_hold_ca_l = ~arbcp6_cpxdp_q0_hold_arbbf_ca;
assign arbcp6_cpxdp_qsel0_ca = ~arbcp6_cpxdp_qsel0_arbbf_ca_l;
assign arbcp6_cpxdp_qsel1_ca_l = ~arbcp6_cpxdp_qsel1_arbbf_ca;
assign arbcp6_cpxdp_shift_cx = ~arbcp6_cpxdp_shift_arbbf_cx_l;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O221A_TB_V
`define SKY130_FD_SC_HS__O221A_TB_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o221a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg C1;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 B1 = 1'b1;
#220 B2 = 1'b1;
#240 C1 = 1'b1;
#260 VGND = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 B1 = 1'b0;
#360 B2 = 1'b0;
#380 C1 = 1'b0;
#400 VGND = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VGND = 1'b1;
#480 C1 = 1'b1;
#500 B2 = 1'b1;
#520 B1 = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VGND = 1'bx;
#620 C1 = 1'bx;
#640 B2 = 1'bx;
#660 B1 = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_hs__o221a dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O221A_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR3B_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__NOR3B_PP_BLACKBOX_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nor3b (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND
);
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR3B_PP_BLACKBOX_V
|
module module6(clk_, rst_, bar, foo);
input clk_;
input rst_;
input [1:0] bar;
output [1:0] foo;
parameter poser_tied = 1'b1;
parameter poser_width_in = 0+1-0+1;
parameter poser_width_out = 0+1-0+1;
parameter poser_grid_width = 4;
parameter poser_grid_depth = 1;
parameter [poser_grid_width-1:0] cellTypes [0:poser_grid_depth-1] = '{ 4'b0000 };
wire [poser_width_in-1:0] poser_inputs;
assign poser_inputs = { bar };
wire [poser_width_out-1:0] poser_outputs;
assign { foo } = poser_outputs;
wire [poser_grid_width-1:0] poser_grid_output [0:poser_grid_depth-1];
wire poser_clk;
assign poser_clk = clk_;
wire poser_rst;
assign poser_rst = rst_;
for (genvar D = 0; D < poser_grid_depth; D++) begin
for (genvar W = 0; W < poser_grid_width; W++) begin
if (D == 0) begin
if (W == 0) begin
poserCell #(.cellType(cellTypes[D][W]), .activeRst(0)) pc (.clk(poser_clk),
.rst(poser_rst),
.i(^{ poser_tied ,
poser_inputs[W%poser_width_in] }),
.o(poser_grid_output[D][W]));
end else begin
poserCell #(.cellType(cellTypes[D][W]), .activeRst(0)) pc (.clk(poser_clk),
.rst(poser_rst),
.i(^{ poser_grid_output[D][W-1],
poser_inputs[W%poser_width_in] }),
.o(poser_grid_output[D][W]));
end
end else begin
if (W == 0) begin
poserCell #(.cellType(cellTypes[D][W]), .activeRst(0)) pc (.clk(poser_clk),
.rst(poser_rst),
.i(^{ poser_grid_output[D-1][W],
poser_grid_output[D-1][poser_grid_depth-1] }),
.o(poser_grid_output[D][W]));
end else begin
poserCell #(.cellType(cellTypes[D][W]), .activeRst(0)) pc (.clk(poser_clk),
.rst(poser_rst),
.i(^{ poser_grid_output[D-1][W],
poser_grid_output[D][W-1] }),
.o(poser_grid_output[D][W]));
end
end
end
end
generate
if (poser_width_out == 1) begin
poserMux #(.poser_mux_width_in(poser_grid_width)) pm (.i(poser_grid_output[poser_grid_depth-1]),
.o(poser_outputs));
end
else if (poser_grid_width == poser_width_out) begin
assign poser_outputs = poser_grid_output[poser_grid_depth-1];
end
else if (poser_grid_width > poser_width_out) begin
wire [poser_grid_width-1:0] poser_grid_output_last;
assign poser_grid_output_last = poser_grid_output[poser_grid_depth-1];
poserMux #(.poser_mux_width_in((poser_grid_width - poser_width_out) + 1)) pm (.i(poser_grid_output_last[poser_grid_width-1:poser_width_out-1]),
.o(poser_outputs[poser_width_out-1]));
assign poser_outputs[poser_width_out-2:0] = poser_grid_output_last[poser_width_out-2:0];
end
endgenerate
endmodule
|
/*
* Copyright (c) Mercury Federal Systems, Inc., Arlington VA., 2009-2010
*
* Mercury Federal Systems, Incorporated
* 1901 South Bell Street
* Suite 402
* Arlington, Virginia 22202
* United States of America
* Telephone 703-413-0781
* FAX 703-413-0784
*
* This file is part of OpenCPI (www.opencpi.org).
* ____ __________ ____
* / __ \____ ___ ____ / ____/ __ \ / _/ ____ _________ _
* / / / / __ \/ _ \/ __ \/ / / /_/ / / / / __ \/ ___/ __ `/
* / /_/ / /_/ / __/ / / / /___/ ____/_/ / _/ /_/ / / / /_/ /
* \____/ .___/\___/_/ /_/\____/_/ /___/(_)____/_/ \__, /
* /_/ /____/
*
* OpenCPI is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published
* by the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* OpenCPI is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with OpenCPI. If not, see <http://www.gnu.org/licenses/>.
*/
//
// Generated by Bluespec Compiler, version 2009.11.beta2 (build 18693, 2009-11-24)
//
// On Thu Jul 1 08:55:56 EDT 2010
//
//
// Ports:
// Name I/O size props
// wciS0_SResp O 2 reg
// wciS0_SData O 32 reg
// wciS0_SThreadBusy O 1
// wciS0_SFlag O 2
// wsiS0_SThreadBusy O 1
// wsiS0_SReset_n O 1
// wsiM0_MCmd O 3
// wsiM0_MReqLast O 1
// wsiM0_MBurstPrecise O 1
// wsiM0_MBurstLength O 12
// wsiM0_MData O 256 reg
// wsiM0_MByteEn O 32 reg
// wsiM0_MReqInfo O 8
// wsiM0_MReset_n O 1
// wciS0_Clk I 1 clock
// wciS0_MReset_n I 1 reset
// wciS0_MCmd I 3
// wciS0_MAddrSpace I 1
// wciS0_MByteEn I 4
// wciS0_MAddr I 20
// wciS0_MData I 32
// wciS0_MFlag I 2 unused
// wsiS0_MCmd I 3
// wsiS0_MBurstLength I 12
// wsiS0_MData I 256
// wsiS0_MByteEn I 32
// wsiS0_MReqInfo I 8
// wsiS0_MReqLast I 1
// wsiS0_MBurstPrecise I 1
// wsiS0_MReset_n I 1 reg
// wsiM0_SThreadBusy I 1 reg
// wsiM0_SReset_n I 1 reg
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef ORIGINAL
module mkFrameGate32B(wciS0_Clk,
wciS0_MReset_n,
wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData,
wciS0_SResp,
wciS0_SData,
wciS0_SThreadBusy,
wciS0_SFlag,
wciS0_MFlag,
wsiS0_MCmd,
wsiS0_MReqLast,
wsiS0_MBurstPrecise,
wsiS0_MBurstLength,
wsiS0_MData,
wsiS0_MByteEn,
wsiS0_MReqInfo,
wsiS0_SThreadBusy,
wsiS0_SReset_n,
wsiS0_MReset_n,
wsiM0_MCmd,
wsiM0_MReqLast,
wsiM0_MBurstPrecise,
wsiM0_MBurstLength,
wsiM0_MData,
wsiM0_MByteEn,
wsiM0_MReqInfo,
wsiM0_SThreadBusy,
wsiM0_MReset_n,
wsiM0_SReset_n);
parameter [31 : 0] fgCtrlInit = 32'b0;
parameter [0 : 0] hasDebugLogic = 1'b0;
input wciS0_Clk;
input wciS0_MReset_n;
// action method wciS0_mCmd
input [2 : 0] wciS0_MCmd;
// action method wciS0_mAddrSpace
input wciS0_MAddrSpace;
// action method wciS0_mByteEn
input [3 : 0] wciS0_MByteEn;
// action method wciS0_mAddr
input [19 : 0] wciS0_MAddr;
// action method wciS0_mData
input [31 : 0] wciS0_MData;
// value method wciS0_sResp
output [1 : 0] wciS0_SResp;
// value method wciS0_sData
output [31 : 0] wciS0_SData;
// value method wciS0_sThreadBusy
output wciS0_SThreadBusy;
// value method wciS0_sFlag
output [1 : 0] wciS0_SFlag;
// action method wciS0_mFlag
input [1 : 0] wciS0_MFlag;
// action method wsiS0_mCmd
input [2 : 0] wsiS0_MCmd;
// action method wsiS0_mReqLast
input wsiS0_MReqLast;
// action method wsiS0_mBurstPrecise
input wsiS0_MBurstPrecise;
// action method wsiS0_mBurstLength
input [11 : 0] wsiS0_MBurstLength;
// action method wsiS0_mData
input [255 : 0] wsiS0_MData;
// action method wsiS0_mByteEn
input [31 : 0] wsiS0_MByteEn;
// action method wsiS0_mReqInfo
input [7 : 0] wsiS0_MReqInfo;
// action method wsiS0_mDataInfo
// value method wsiS0_sThreadBusy
output wsiS0_SThreadBusy;
// value method wsiS0_sReset_n
output wsiS0_SReset_n;
// action method wsiS0_mReset_n
input wsiS0_MReset_n;
// value method wsiM0_mCmd
output [2 : 0] wsiM0_MCmd;
// value method wsiM0_mReqLast
output wsiM0_MReqLast;
// value method wsiM0_mBurstPrecise
output wsiM0_MBurstPrecise;
// value method wsiM0_mBurstLength
output [11 : 0] wsiM0_MBurstLength;
// value method wsiM0_mData
output [255 : 0] wsiM0_MData;
// value method wsiM0_mByteEn
output [31 : 0] wsiM0_MByteEn;
// value method wsiM0_mReqInfo
output [7 : 0] wsiM0_MReqInfo;
// value method wsiM0_mDataInfo
// action method wsiM0_sThreadBusy
input wsiM0_SThreadBusy;
// value method wsiM0_mReset_n
output wsiM0_MReset_n;
// action method wsiM0_sReset_n
input wsiM0_SReset_n;
// signals for module outputs
wire [255 : 0] wsiM0_MData;
wire [31 : 0] wciS0_SData, wsiM0_MByteEn;
wire [11 : 0] wsiM0_MBurstLength;
wire [7 : 0] wsiM0_MReqInfo;
wire [2 : 0] wsiM0_MCmd;
wire [1 : 0] wciS0_SFlag, wciS0_SResp;
wire wciS0_SThreadBusy,
wsiM0_MBurstPrecise,
wsiM0_MReqLast,
wsiM0_MReset_n,
wsiS0_SReset_n,
wsiS0_SThreadBusy;
`else
`define NOT_EMPTY_framegate.v
`include "framegate_defs.v"
`endif
// inlined wires
wire [312 : 0] wsiM_reqFifo_x_wire$wget, wsiS_wsiReq$wget;
wire [255 : 0] wsi_Es_mData_w$wget;
wire [95 : 0] wsiM_extStatusW$wget, wsiS_extStatusW$wget;
wire [59 : 0] wci_wciReq$wget;
wire [33 : 0] wci_respF_x_wire$wget;
wire [31 : 0] wci_Es_mData_w$wget, wsi_Es_mByteEn_w$wget;
wire [19 : 0] wci_Es_mAddr_w$wget;
wire [11 : 0] wsi_Es_mBurstLength_w$wget;
wire [7 : 0] wsi_Es_mReqInfo_w$wget;
wire [3 : 0] wci_Es_mByteEn_w$wget;
wire [2 : 0] wci_Es_mCmd_w$wget, wci_wEdge$wget, wsi_Es_mCmd_w$wget;
wire wci_Es_mAddrSpace_w$wget,
wci_Es_mAddrSpace_w$whas,
wci_Es_mAddr_w$whas,
wci_Es_mByteEn_w$whas,
wci_Es_mCmd_w$whas,
wci_Es_mData_w$whas,
wci_ctlAckReg_1$wget,
wci_ctlAckReg_1$whas,
wci_reqF_r_clr$whas,
wci_reqF_r_deq$whas,
wci_reqF_r_enq$whas,
wci_respF_dequeueing$whas,
wci_respF_enqueueing$whas,
wci_respF_x_wire$whas,
wci_sFlagReg_1$wget,
wci_sFlagReg_1$whas,
wci_sThreadBusy_pw$whas,
wci_wEdge$whas,
wci_wciReq$whas,
wci_wci_cfrd_pw$whas,
wci_wci_cfwr_pw$whas,
wci_wci_ctrl_pw$whas,
wsiM_operateD_1$wget,
wsiM_operateD_1$whas,
wsiM_peerIsReady_1$wget,
wsiM_peerIsReady_1$whas,
wsiM_reqFifo_dequeueing$whas,
wsiM_reqFifo_enqueueing$whas,
wsiM_reqFifo_x_wire$whas,
wsiM_sThreadBusy_pw$whas,
wsiS_operateD_1$wget,
wsiS_operateD_1$whas,
wsiS_peerIsReady_1$wget,
wsiS_peerIsReady_1$whas,
wsiS_reqFifo_r_clr$whas,
wsiS_reqFifo_r_deq$whas,
wsiS_reqFifo_r_enq$whas,
wsiS_wsiReq$whas,
wsi_Es_mBurstLength_w$whas,
wsi_Es_mBurstPrecise_w$whas,
wsi_Es_mByteEn_w$whas,
wsi_Es_mCmd_w$whas,
wsi_Es_mDataInfo_w$whas,
wsi_Es_mData_w$whas,
wsi_Es_mReqInfo_w$whas,
wsi_Es_mReqLast_w$whas;
// register byteCount
reg [31 : 0] byteCount;
wire [31 : 0] byteCount$D_IN;
wire byteCount$EN;
// register frameGateCtrl
reg [31 : 0] frameGateCtrl;
wire [31 : 0] frameGateCtrl$D_IN;
wire frameGateCtrl$EN;
// register frameSize
reg [31 : 0] frameSize;
wire [31 : 0] frameSize$D_IN;
wire frameSize$EN;
// register gateSize
reg [31 : 0] gateSize;
wire [31 : 0] gateSize$D_IN;
wire gateSize$EN;
// register gated
reg gated;
wire gated$D_IN, gated$EN;
// register op0MesgCnt
reg [31 : 0] op0MesgCnt;
wire [31 : 0] op0MesgCnt$D_IN;
wire op0MesgCnt$EN;
// register otherMesgCnt
reg [31 : 0] otherMesgCnt;
wire [31 : 0] otherMesgCnt$D_IN;
wire otherMesgCnt$EN;
// register wci_cEdge
reg [2 : 0] wci_cEdge;
wire [2 : 0] wci_cEdge$D_IN;
wire wci_cEdge$EN;
// register wci_cState
reg [2 : 0] wci_cState;
wire [2 : 0] wci_cState$D_IN;
wire wci_cState$EN;
// register wci_ctlAckReg
reg wci_ctlAckReg;
wire wci_ctlAckReg$D_IN, wci_ctlAckReg$EN;
// register wci_ctlOpActive
reg wci_ctlOpActive;
wire wci_ctlOpActive$D_IN, wci_ctlOpActive$EN;
// register wci_illegalEdge
reg wci_illegalEdge;
wire wci_illegalEdge$D_IN, wci_illegalEdge$EN;
// register wci_nState
reg [2 : 0] wci_nState;
reg [2 : 0] wci_nState$D_IN;
wire wci_nState$EN;
// register wci_reqF_countReg
reg [1 : 0] wci_reqF_countReg;
wire [1 : 0] wci_reqF_countReg$D_IN;
wire wci_reqF_countReg$EN;
// register wci_respF_c_r
reg [1 : 0] wci_respF_c_r;
wire [1 : 0] wci_respF_c_r$D_IN;
wire wci_respF_c_r$EN;
// register wci_respF_q_0
reg [33 : 0] wci_respF_q_0;
reg [33 : 0] wci_respF_q_0$D_IN;
wire wci_respF_q_0$EN;
// register wci_respF_q_1
reg [33 : 0] wci_respF_q_1;
reg [33 : 0] wci_respF_q_1$D_IN;
wire wci_respF_q_1$EN;
// register wci_sFlagReg
reg wci_sFlagReg;
wire wci_sFlagReg$D_IN, wci_sFlagReg$EN;
// register wci_sThreadBusy_d
reg wci_sThreadBusy_d;
wire wci_sThreadBusy_d$D_IN, wci_sThreadBusy_d$EN;
// register wsiM_burstKind
reg [1 : 0] wsiM_burstKind;
wire [1 : 0] wsiM_burstKind$D_IN;
wire wsiM_burstKind$EN;
// register wsiM_errorSticky
reg wsiM_errorSticky;
wire wsiM_errorSticky$D_IN, wsiM_errorSticky$EN;
// register wsiM_iMesgCount
reg [31 : 0] wsiM_iMesgCount;
wire [31 : 0] wsiM_iMesgCount$D_IN;
wire wsiM_iMesgCount$EN;
// register wsiM_operateD
reg wsiM_operateD;
wire wsiM_operateD$D_IN, wsiM_operateD$EN;
// register wsiM_pMesgCount
reg [31 : 0] wsiM_pMesgCount;
wire [31 : 0] wsiM_pMesgCount$D_IN;
wire wsiM_pMesgCount$EN;
// register wsiM_peerIsReady
reg wsiM_peerIsReady;
wire wsiM_peerIsReady$D_IN, wsiM_peerIsReady$EN;
// register wsiM_reqFifo_c_r
reg [1 : 0] wsiM_reqFifo_c_r;
wire [1 : 0] wsiM_reqFifo_c_r$D_IN;
wire wsiM_reqFifo_c_r$EN;
// register wsiM_reqFifo_q_0
reg [312 : 0] wsiM_reqFifo_q_0;
reg [312 : 0] wsiM_reqFifo_q_0$D_IN;
wire wsiM_reqFifo_q_0$EN;
// register wsiM_reqFifo_q_1
reg [312 : 0] wsiM_reqFifo_q_1;
reg [312 : 0] wsiM_reqFifo_q_1$D_IN;
wire wsiM_reqFifo_q_1$EN;
// register wsiM_sThreadBusy_d
reg wsiM_sThreadBusy_d;
wire wsiM_sThreadBusy_d$D_IN, wsiM_sThreadBusy_d$EN;
// register wsiM_statusR
reg [7 : 0] wsiM_statusR;
wire [7 : 0] wsiM_statusR$D_IN;
wire wsiM_statusR$EN;
// register wsiM_tBusyCount
reg [31 : 0] wsiM_tBusyCount;
wire [31 : 0] wsiM_tBusyCount$D_IN;
wire wsiM_tBusyCount$EN;
// register wsiM_trafficSticky
reg wsiM_trafficSticky;
wire wsiM_trafficSticky$D_IN, wsiM_trafficSticky$EN;
// register wsiS_burstKind
reg [1 : 0] wsiS_burstKind;
wire [1 : 0] wsiS_burstKind$D_IN;
wire wsiS_burstKind$EN;
// register wsiS_errorSticky
reg wsiS_errorSticky;
wire wsiS_errorSticky$D_IN, wsiS_errorSticky$EN;
// register wsiS_iMesgCount
reg [31 : 0] wsiS_iMesgCount;
wire [31 : 0] wsiS_iMesgCount$D_IN;
wire wsiS_iMesgCount$EN;
// register wsiS_operateD
reg wsiS_operateD;
wire wsiS_operateD$D_IN, wsiS_operateD$EN;
// register wsiS_pMesgCount
reg [31 : 0] wsiS_pMesgCount;
wire [31 : 0] wsiS_pMesgCount$D_IN;
wire wsiS_pMesgCount$EN;
// register wsiS_peerIsReady
reg wsiS_peerIsReady;
wire wsiS_peerIsReady$D_IN, wsiS_peerIsReady$EN;
// register wsiS_reqFifo_countReg
reg [1 : 0] wsiS_reqFifo_countReg;
wire [1 : 0] wsiS_reqFifo_countReg$D_IN;
wire wsiS_reqFifo_countReg$EN;
// register wsiS_statusR
reg [7 : 0] wsiS_statusR;
wire [7 : 0] wsiS_statusR$D_IN;
wire wsiS_statusR$EN;
// register wsiS_tBusyCount
reg [31 : 0] wsiS_tBusyCount;
wire [31 : 0] wsiS_tBusyCount$D_IN;
wire wsiS_tBusyCount$EN;
// register wsiS_trafficSticky
reg wsiS_trafficSticky;
wire wsiS_trafficSticky$D_IN, wsiS_trafficSticky$EN;
// ports of submodule wci_isReset
wire wci_isReset$VAL;
// ports of submodule wci_reqF
wire [59 : 0] wci_reqF$D_IN, wci_reqF$D_OUT;
wire wci_reqF$CLR, wci_reqF$DEQ, wci_reqF$EMPTY_N, wci_reqF$ENQ;
// ports of submodule wsiM_isReset
wire wsiM_isReset$VAL;
// ports of submodule wsiS_isReset
wire wsiS_isReset$VAL;
// ports of submodule wsiS_reqFifo
wire [312 : 0] wsiS_reqFifo$D_IN, wsiS_reqFifo$D_OUT;
wire wsiS_reqFifo$CLR,
wsiS_reqFifo$DEQ,
wsiS_reqFifo$EMPTY_N,
wsiS_reqFifo$ENQ,
wsiS_reqFifo$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_operating_actions,
CAN_FIRE_RL_wci_Es_doAlways_Req,
CAN_FIRE_RL_wci_cfrd,
CAN_FIRE_RL_wci_cfwr,
CAN_FIRE_RL_wci_ctlAckReg__dreg_update,
CAN_FIRE_RL_wci_ctl_op_complete,
CAN_FIRE_RL_wci_ctl_op_start,
CAN_FIRE_RL_wci_ctrl_EiI,
CAN_FIRE_RL_wci_ctrl_IsO,
CAN_FIRE_RL_wci_ctrl_OrE,
CAN_FIRE_RL_wci_reqF__updateLevelCounter,
CAN_FIRE_RL_wci_reqF_enq,
CAN_FIRE_RL_wci_request_decode,
CAN_FIRE_RL_wci_respF_both,
CAN_FIRE_RL_wci_respF_decCtr,
CAN_FIRE_RL_wci_respF_deq,
CAN_FIRE_RL_wci_respF_incCtr,
CAN_FIRE_RL_wci_sFlagReg__dreg_update,
CAN_FIRE_RL_wci_sThreadBusy_reg,
CAN_FIRE_RL_wsiM_ext_status_assign,
CAN_FIRE_RL_wsiM_inc_tBusyCount,
CAN_FIRE_RL_wsiM_operateD__dreg_update,
CAN_FIRE_RL_wsiM_peerIsReady__dreg_update,
CAN_FIRE_RL_wsiM_reqFifo_both,
CAN_FIRE_RL_wsiM_reqFifo_decCtr,
CAN_FIRE_RL_wsiM_reqFifo_deq,
CAN_FIRE_RL_wsiM_reqFifo_incCtr,
CAN_FIRE_RL_wsiM_sThreadBusy_reg,
CAN_FIRE_RL_wsiM_update_statusR,
CAN_FIRE_RL_wsiS_ext_status_assign,
CAN_FIRE_RL_wsiS_inc_tBusyCount,
CAN_FIRE_RL_wsiS_operateD__dreg_update,
CAN_FIRE_RL_wsiS_peerIsReady__dreg_update,
CAN_FIRE_RL_wsiS_reqFifo__updateLevelCounter,
CAN_FIRE_RL_wsiS_reqFifo_enq,
CAN_FIRE_RL_wsiS_update_statusR,
CAN_FIRE_RL_wsi_Es_doAlways,
CAN_FIRE_RL_wsipass_doMessagePush,
CAN_FIRE_wciS0_mAddr,
CAN_FIRE_wciS0_mAddrSpace,
CAN_FIRE_wciS0_mByteEn,
CAN_FIRE_wciS0_mCmd,
CAN_FIRE_wciS0_mData,
CAN_FIRE_wciS0_mFlag,
CAN_FIRE_wsiM0_sReset_n,
CAN_FIRE_wsiM0_sThreadBusy,
CAN_FIRE_wsiS0_mBurstLength,
CAN_FIRE_wsiS0_mBurstPrecise,
CAN_FIRE_wsiS0_mByteEn,
CAN_FIRE_wsiS0_mCmd,
CAN_FIRE_wsiS0_mData,
CAN_FIRE_wsiS0_mDataInfo,
CAN_FIRE_wsiS0_mReqInfo,
CAN_FIRE_wsiS0_mReqLast,
CAN_FIRE_wsiS0_mReset_n,
WILL_FIRE_RL_operating_actions,
WILL_FIRE_RL_wci_Es_doAlways_Req,
WILL_FIRE_RL_wci_cfrd,
WILL_FIRE_RL_wci_cfwr,
WILL_FIRE_RL_wci_ctlAckReg__dreg_update,
WILL_FIRE_RL_wci_ctl_op_complete,
WILL_FIRE_RL_wci_ctl_op_start,
WILL_FIRE_RL_wci_ctrl_EiI,
WILL_FIRE_RL_wci_ctrl_IsO,
WILL_FIRE_RL_wci_ctrl_OrE,
WILL_FIRE_RL_wci_reqF__updateLevelCounter,
WILL_FIRE_RL_wci_reqF_enq,
WILL_FIRE_RL_wci_request_decode,
WILL_FIRE_RL_wci_respF_both,
WILL_FIRE_RL_wci_respF_decCtr,
WILL_FIRE_RL_wci_respF_deq,
WILL_FIRE_RL_wci_respF_incCtr,
WILL_FIRE_RL_wci_sFlagReg__dreg_update,
WILL_FIRE_RL_wci_sThreadBusy_reg,
WILL_FIRE_RL_wsiM_ext_status_assign,
WILL_FIRE_RL_wsiM_inc_tBusyCount,
WILL_FIRE_RL_wsiM_operateD__dreg_update,
WILL_FIRE_RL_wsiM_peerIsReady__dreg_update,
WILL_FIRE_RL_wsiM_reqFifo_both,
WILL_FIRE_RL_wsiM_reqFifo_decCtr,
WILL_FIRE_RL_wsiM_reqFifo_deq,
WILL_FIRE_RL_wsiM_reqFifo_incCtr,
WILL_FIRE_RL_wsiM_sThreadBusy_reg,
WILL_FIRE_RL_wsiM_update_statusR,
WILL_FIRE_RL_wsiS_ext_status_assign,
WILL_FIRE_RL_wsiS_inc_tBusyCount,
WILL_FIRE_RL_wsiS_operateD__dreg_update,
WILL_FIRE_RL_wsiS_peerIsReady__dreg_update,
WILL_FIRE_RL_wsiS_reqFifo__updateLevelCounter,
WILL_FIRE_RL_wsiS_reqFifo_enq,
WILL_FIRE_RL_wsiS_update_statusR,
WILL_FIRE_RL_wsi_Es_doAlways,
WILL_FIRE_RL_wsipass_doMessagePush,
WILL_FIRE_wciS0_mAddr,
WILL_FIRE_wciS0_mAddrSpace,
WILL_FIRE_wciS0_mByteEn,
WILL_FIRE_wciS0_mCmd,
WILL_FIRE_wciS0_mData,
WILL_FIRE_wciS0_mFlag,
WILL_FIRE_wsiM0_sReset_n,
WILL_FIRE_wsiM0_sThreadBusy,
WILL_FIRE_wsiS0_mBurstLength,
WILL_FIRE_wsiS0_mBurstPrecise,
WILL_FIRE_wsiS0_mByteEn,
WILL_FIRE_wsiS0_mCmd,
WILL_FIRE_wsiS0_mData,
WILL_FIRE_wsiS0_mDataInfo,
WILL_FIRE_wsiS0_mReqInfo,
WILL_FIRE_wsiS0_mReqLast,
WILL_FIRE_wsiS0_mReset_n;
// inputs to muxes for submodule ports
reg [33 : 0] MUX_wci_respF_q_0$write_1__VAL_2;
wire [312 : 0] MUX_wsiM_reqFifo_q_0$write_1__VAL_1,
MUX_wsiM_reqFifo_q_1$write_1__VAL_1;
wire [33 : 0] MUX_wci_respF_q_0$write_1__VAL_1,
MUX_wci_respF_q_1$write_1__VAL_1,
MUX_wci_respF_x_wire$wset_1__VAL_1,
MUX_wci_respF_x_wire$wset_1__VAL_2;
wire [1 : 0] MUX_wci_respF_c_r$write_1__VAL_1,
MUX_wci_respF_c_r$write_1__VAL_2,
MUX_wsiM_reqFifo_c_r$write_1__VAL_1,
MUX_wsiM_reqFifo_c_r$write_1__VAL_2;
wire MUX_wci_illegalEdge$write_1__SEL_1,
MUX_wci_illegalEdge$write_1__SEL_2,
MUX_wci_illegalEdge$write_1__VAL_2,
MUX_wci_respF_q_0$write_1__SEL_2,
MUX_wci_respF_q_1$write_1__SEL_2,
MUX_wsiM_reqFifo_q_0$write_1__SEL_2,
MUX_wsiM_reqFifo_q_1$write_1__SEL_2;
// remaining internal signals
reg [63 : 0] v__h2638, v__h2785, v__h3684, v__h9770;
reg [31 : 0] x_data__h9902;
wire [31 : 0] frameGateStatus__h9658,
rdat__h10036,
rdat__h10050,
rdat__h10058,
rdat__h10064,
rdat__h10078,
rdat__h10086,
rdat__h10092,
rdat__h10103,
rdat__h9936,
x__h9407;
wire [15 : 0] x__h9940;
wire NOT_gated_28_37_AND_byteCount_38_EQ_frameSize__ETC___d437,
NOT_wsiS_reqFifo_countReg_32_ULE_1_33___d234,
wsiS_reqFifo_i_notEmpty__22_AND_NOT_frameGateC_ETC___d135;
// action method wciS0_mCmd
assign CAN_FIRE_wciS0_mCmd = 1'd1 ;
assign WILL_FIRE_wciS0_mCmd = 1'd1 ;
// action method wciS0_mAddrSpace
assign CAN_FIRE_wciS0_mAddrSpace = 1'd1 ;
assign WILL_FIRE_wciS0_mAddrSpace = 1'd1 ;
// action method wciS0_mByteEn
assign CAN_FIRE_wciS0_mByteEn = 1'd1 ;
assign WILL_FIRE_wciS0_mByteEn = 1'd1 ;
// action method wciS0_mAddr
assign CAN_FIRE_wciS0_mAddr = 1'd1 ;
assign WILL_FIRE_wciS0_mAddr = 1'd1 ;
// action method wciS0_mData
assign CAN_FIRE_wciS0_mData = 1'd1 ;
assign WILL_FIRE_wciS0_mData = 1'd1 ;
// value method wciS0_sResp
assign wciS0_SResp = wci_respF_q_0[33:32] ;
// value method wciS0_sData
assign wciS0_SData = wci_respF_q_0[31:0] ;
// value method wciS0_sThreadBusy
assign wciS0_SThreadBusy = wci_reqF_countReg > 2'd1 || wci_isReset$VAL ;
// value method wciS0_sFlag
assign wciS0_SFlag = { 1'd1, wci_sFlagReg } ;
// action method wciS0_mFlag
assign CAN_FIRE_wciS0_mFlag = 1'd1 ;
assign WILL_FIRE_wciS0_mFlag = 1'd1 ;
// action method wsiS0_mCmd
assign CAN_FIRE_wsiS0_mCmd = 1'd1 ;
assign WILL_FIRE_wsiS0_mCmd = 1'd1 ;
// action method wsiS0_mReqLast
assign CAN_FIRE_wsiS0_mReqLast = 1'd1 ;
assign WILL_FIRE_wsiS0_mReqLast = wsiS0_MReqLast ;
// action method wsiS0_mBurstPrecise
assign WILL_FIRE_wsiS0_mBurstPrecise = wsiS0_MBurstPrecise ;
assign CAN_FIRE_wsiS0_mBurstPrecise = 1'd1 ;
// action method wsiS0_mBurstLength
assign CAN_FIRE_wsiS0_mBurstLength = 1'd1 ;
assign WILL_FIRE_wsiS0_mBurstLength = 1'd1 ;
// action method wsiS0_mData
assign CAN_FIRE_wsiS0_mData = 1'd1 ;
assign WILL_FIRE_wsiS0_mData = 1'd1 ;
// action method wsiS0_mByteEn
assign CAN_FIRE_wsiS0_mByteEn = 1'd1 ;
assign WILL_FIRE_wsiS0_mByteEn = 1'd1 ;
// action method wsiS0_mReqInfo
assign CAN_FIRE_wsiS0_mReqInfo = 1'd1 ;
assign WILL_FIRE_wsiS0_mReqInfo = 1'd1 ;
// action method wsiS0_mDataInfo
assign CAN_FIRE_wsiS0_mDataInfo = 1'd1 ;
assign WILL_FIRE_wsiS0_mDataInfo = 1'd1 ;
// value method wsiS0_sThreadBusy
assign wsiS0_SThreadBusy =
NOT_wsiS_reqFifo_countReg_32_ULE_1_33___d234 ||
wsiS_isReset$VAL ||
!wsiS_operateD ||
!wsiS_peerIsReady ;
// value method wsiS0_sReset_n
assign wsiS0_SReset_n = !wsiS_isReset$VAL && wsiS_operateD ;
// action method wsiS0_mReset_n
assign CAN_FIRE_wsiS0_mReset_n = 1'd1 ;
assign WILL_FIRE_wsiS0_mReset_n = wsiS0_MReset_n ;
// value method wsiM0_mCmd
assign wsiM0_MCmd = wsiM_sThreadBusy_d ? 3'd0 : wsiM_reqFifo_q_0[312:310] ;
// value method wsiM0_mReqLast
assign wsiM0_MReqLast = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[309] ;
// value method wsiM0_mBurstPrecise
assign wsiM0_MBurstPrecise = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[308] ;
// value method wsiM0_mBurstLength
assign wsiM0_MBurstLength =
wsiM_sThreadBusy_d ? 12'd0 : wsiM_reqFifo_q_0[307:296] ;
// value method wsiM0_mData
assign wsiM0_MData = wsiM_reqFifo_q_0[295:40] ;
// value method wsiM0_mByteEn
assign wsiM0_MByteEn = wsiM_reqFifo_q_0[39:8] ;
// value method wsiM0_mReqInfo
assign wsiM0_MReqInfo = wsiM_sThreadBusy_d ? 8'd0 : wsiM_reqFifo_q_0[7:0] ;
// action method wsiM0_sThreadBusy
assign CAN_FIRE_wsiM0_sThreadBusy = 1'd1 ;
assign WILL_FIRE_wsiM0_sThreadBusy = wsiM0_SThreadBusy ;
// value method wsiM0_mReset_n
assign wsiM0_MReset_n = !wsiM_isReset$VAL && wsiM_operateD ;
// action method wsiM0_sReset_n
assign CAN_FIRE_wsiM0_sReset_n = 1'd1 ;
assign WILL_FIRE_wsiM0_sReset_n = wsiM0_SReset_n ;
// submodule wci_isReset
ResetToBool wci_isReset(.RST(wciS0_MReset_n), .VAL(wci_isReset$VAL));
// submodule wci_reqF
SizedFIFO #(.p1width(32'd60),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wci_reqF(.RST_N(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wci_reqF$D_IN),
.ENQ(wci_reqF$ENQ),
.DEQ(wci_reqF$DEQ),
.CLR(wci_reqF$CLR),
.D_OUT(wci_reqF$D_OUT),
.FULL_N(),
.EMPTY_N(wci_reqF$EMPTY_N));
// submodule wsiM_isReset
ResetToBool wsiM_isReset(.RST(wciS0_MReset_n), .VAL(wsiM_isReset$VAL));
// submodule wsiS_isReset
ResetToBool wsiS_isReset(.RST(wciS0_MReset_n), .VAL(wsiS_isReset$VAL));
// submodule wsiS_reqFifo
SizedFIFO #(.p1width(32'd313),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wsiS_reqFifo(.RST_N(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wsiS_reqFifo$D_IN),
.ENQ(wsiS_reqFifo$ENQ),
.DEQ(wsiS_reqFifo$DEQ),
.CLR(wsiS_reqFifo$CLR),
.D_OUT(wsiS_reqFifo$D_OUT),
.FULL_N(wsiS_reqFifo$FULL_N),
.EMPTY_N(wsiS_reqFifo$EMPTY_N));
// rule RL_wci_request_decode
assign CAN_FIRE_RL_wci_request_decode = wci_reqF$EMPTY_N ;
assign WILL_FIRE_RL_wci_request_decode = wci_reqF$EMPTY_N ;
// rule RL_wci_ctl_op_start
assign CAN_FIRE_RL_wci_ctl_op_start =
wci_reqF$EMPTY_N && wci_wci_ctrl_pw$whas ;
assign WILL_FIRE_RL_wci_ctl_op_start =
CAN_FIRE_RL_wci_ctl_op_start &&
!WILL_FIRE_RL_wci_ctl_op_complete ;
// rule RL_wci_ctrl_EiI
assign CAN_FIRE_RL_wci_ctrl_EiI =
wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start &&
wci_cState == 3'd0 &&
wci_reqF$D_OUT[36:34] == 3'd0 ;
assign WILL_FIRE_RL_wci_ctrl_EiI = CAN_FIRE_RL_wci_ctrl_EiI ;
// rule RL_wci_ctrl_IsO
assign CAN_FIRE_RL_wci_ctrl_IsO =
wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start &&
wci_cState == 3'd1 &&
wci_reqF$D_OUT[36:34] == 3'd1 ;
assign WILL_FIRE_RL_wci_ctrl_IsO = CAN_FIRE_RL_wci_ctrl_IsO ;
// rule RL_wci_ctrl_OrE
assign CAN_FIRE_RL_wci_ctrl_OrE =
wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start &&
wci_cState == 3'd2 &&
wci_reqF$D_OUT[36:34] == 3'd3 ;
assign WILL_FIRE_RL_wci_ctrl_OrE = CAN_FIRE_RL_wci_ctrl_OrE ;
// rule RL_wsi_Es_doAlways
assign CAN_FIRE_RL_wsi_Es_doAlways = 1'd1 ;
assign WILL_FIRE_RL_wsi_Es_doAlways = 1'd1 ;
// rule RL_wci_Es_doAlways_Req
assign CAN_FIRE_RL_wci_Es_doAlways_Req = 1'd1 ;
assign WILL_FIRE_RL_wci_Es_doAlways_Req = 1'd1 ;
// rule RL_operating_actions
assign CAN_FIRE_RL_operating_actions = wci_cState == 3'd2 ;
assign WILL_FIRE_RL_operating_actions = CAN_FIRE_RL_operating_actions ;
// rule RL_wsiM_update_statusR
assign CAN_FIRE_RL_wsiM_update_statusR = 1'd1 ;
assign WILL_FIRE_RL_wsiM_update_statusR = 1'd1 ;
// rule RL_wsiM_ext_status_assign
assign CAN_FIRE_RL_wsiM_ext_status_assign = 1'd1 ;
assign WILL_FIRE_RL_wsiM_ext_status_assign = 1'd1 ;
// rule RL_wsiM_inc_tBusyCount
assign CAN_FIRE_RL_wsiM_inc_tBusyCount =
wsiM_operateD && wsiM_peerIsReady && wsiM_sThreadBusy_d ;
assign WILL_FIRE_RL_wsiM_inc_tBusyCount = CAN_FIRE_RL_wsiM_inc_tBusyCount ;
// rule RL_wsiM_reqFifo_deq
assign CAN_FIRE_RL_wsiM_reqFifo_deq =
wsiM_reqFifo_c_r != 2'd0 && !wsiM_sThreadBusy_d ;
assign WILL_FIRE_RL_wsiM_reqFifo_deq = CAN_FIRE_RL_wsiM_reqFifo_deq ;
// rule RL_wsiM_sThreadBusy_reg
assign CAN_FIRE_RL_wsiM_sThreadBusy_reg = 1'd1 ;
assign WILL_FIRE_RL_wsiM_sThreadBusy_reg = 1'd1 ;
// rule RL_wsiM_peerIsReady__dreg_update
assign CAN_FIRE_RL_wsiM_peerIsReady__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wsiM_peerIsReady__dreg_update = 1'd1 ;
// rule RL_wsiM_operateD__dreg_update
assign CAN_FIRE_RL_wsiM_operateD__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wsiM_operateD__dreg_update = 1'd1 ;
// rule RL_wsiS_update_statusR
assign CAN_FIRE_RL_wsiS_update_statusR = 1'd1 ;
assign WILL_FIRE_RL_wsiS_update_statusR = 1'd1 ;
// rule RL_wsiS_ext_status_assign
assign CAN_FIRE_RL_wsiS_ext_status_assign = 1'd1 ;
assign WILL_FIRE_RL_wsiS_ext_status_assign = 1'd1 ;
// rule RL_wci_cfrd
assign CAN_FIRE_RL_wci_cfrd =
wci_reqF$EMPTY_N && wci_respF_c_r != 2'd2 &&
wci_wci_cfrd_pw$whas ;
assign WILL_FIRE_RL_wci_cfrd =
CAN_FIRE_RL_wci_cfrd && !WILL_FIRE_RL_wci_ctl_op_start &&
!WILL_FIRE_RL_wci_ctl_op_complete ;
// rule RL_wsiS_inc_tBusyCount
assign CAN_FIRE_RL_wsiS_inc_tBusyCount =
wsiS_operateD && wsiS_peerIsReady &&
NOT_wsiS_reqFifo_countReg_32_ULE_1_33___d234 ;
assign WILL_FIRE_RL_wsiS_inc_tBusyCount = CAN_FIRE_RL_wsiS_inc_tBusyCount ;
// rule RL_wsiS_reqFifo_enq
assign CAN_FIRE_RL_wsiS_reqFifo_enq =
wsiS_operateD && wsiS_peerIsReady &&
wsiS_wsiReq$wget[312:310] == 3'd1 ;
assign WILL_FIRE_RL_wsiS_reqFifo_enq = CAN_FIRE_RL_wsiS_reqFifo_enq ;
// rule RL_wsipass_doMessagePush
assign CAN_FIRE_RL_wsipass_doMessagePush =
wsiS_reqFifo_i_notEmpty__22_AND_NOT_frameGateC_ETC___d135 &&
wci_cState == 3'd2 ;
assign WILL_FIRE_RL_wsipass_doMessagePush =
CAN_FIRE_RL_wsipass_doMessagePush ;
// rule RL_wci_ctl_op_complete
assign CAN_FIRE_RL_wci_ctl_op_complete =
wci_respF_c_r != 2'd2 && wci_ctlOpActive && wci_ctlAckReg ;
assign WILL_FIRE_RL_wci_ctl_op_complete = CAN_FIRE_RL_wci_ctl_op_complete ;
// rule RL_wci_cfwr
assign CAN_FIRE_RL_wci_cfwr =
wci_reqF$EMPTY_N && wci_respF_c_r != 2'd2 &&
wci_wci_cfwr_pw$whas ;
assign WILL_FIRE_RL_wci_cfwr =
CAN_FIRE_RL_wci_cfwr && !WILL_FIRE_RL_wci_ctl_op_start &&
!WILL_FIRE_RL_wci_ctl_op_complete ;
// rule RL_wsiM_reqFifo_both
assign CAN_FIRE_RL_wsiM_reqFifo_both =
((wsiM_reqFifo_c_r == 2'd1) ?
wsiM_reqFifo_enqueueing$whas :
wsiM_reqFifo_c_r != 2'd2 || wsiM_reqFifo_enqueueing$whas) &&
CAN_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_enqueueing$whas ;
assign WILL_FIRE_RL_wsiM_reqFifo_both = CAN_FIRE_RL_wsiM_reqFifo_both ;
// rule RL_wsiM_reqFifo_decCtr
assign CAN_FIRE_RL_wsiM_reqFifo_decCtr =
CAN_FIRE_RL_wsiM_reqFifo_deq && !wsiM_reqFifo_enqueueing$whas ;
assign WILL_FIRE_RL_wsiM_reqFifo_decCtr = CAN_FIRE_RL_wsiM_reqFifo_decCtr ;
// rule RL_wsiM_reqFifo_incCtr
assign CAN_FIRE_RL_wsiM_reqFifo_incCtr =
((wsiM_reqFifo_c_r == 2'd0) ?
wsiM_reqFifo_enqueueing$whas :
wsiM_reqFifo_c_r != 2'd1 || wsiM_reqFifo_enqueueing$whas) &&
wsiM_reqFifo_enqueueing$whas &&
!CAN_FIRE_RL_wsiM_reqFifo_deq ;
assign WILL_FIRE_RL_wsiM_reqFifo_incCtr = CAN_FIRE_RL_wsiM_reqFifo_incCtr ;
// rule RL_wsiS_peerIsReady__dreg_update
assign CAN_FIRE_RL_wsiS_peerIsReady__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wsiS_peerIsReady__dreg_update = 1'd1 ;
// rule RL_wsiS_operateD__dreg_update
assign CAN_FIRE_RL_wsiS_operateD__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wsiS_operateD__dreg_update = 1'd1 ;
// rule RL_wsiS_reqFifo__updateLevelCounter
assign CAN_FIRE_RL_wsiS_reqFifo__updateLevelCounter =
CAN_FIRE_RL_wsiS_reqFifo_enq !=
CAN_FIRE_RL_wsipass_doMessagePush ;
assign WILL_FIRE_RL_wsiS_reqFifo__updateLevelCounter =
CAN_FIRE_RL_wsiS_reqFifo__updateLevelCounter ;
// rule RL_wci_respF_deq
assign CAN_FIRE_RL_wci_respF_deq = 1'd1 ;
assign WILL_FIRE_RL_wci_respF_deq = 1'd1 ;
// rule RL_wci_reqF_enq
assign CAN_FIRE_RL_wci_reqF_enq = wci_wciReq$wget[59:57] != 3'd0 ;
assign WILL_FIRE_RL_wci_reqF_enq = CAN_FIRE_RL_wci_reqF_enq ;
// rule RL_wci_sThreadBusy_reg
assign CAN_FIRE_RL_wci_sThreadBusy_reg = 1'd1 ;
assign WILL_FIRE_RL_wci_sThreadBusy_reg = 1'd1 ;
// rule RL_wci_ctlAckReg__dreg_update
assign CAN_FIRE_RL_wci_ctlAckReg__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wci_ctlAckReg__dreg_update = 1'd1 ;
// rule RL_wci_sFlagReg__dreg_update
assign CAN_FIRE_RL_wci_sFlagReg__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wci_sFlagReg__dreg_update = 1'd1 ;
// rule RL_wci_respF_both
assign CAN_FIRE_RL_wci_respF_both =
((wci_respF_c_r == 2'd1) ?
wci_respF_x_wire$whas :
wci_respF_c_r != 2'd2 || wci_respF_x_wire$whas) &&
wci_respF_c_r != 2'd0 &&
wci_respF_enqueueing$whas ;
assign WILL_FIRE_RL_wci_respF_both = CAN_FIRE_RL_wci_respF_both ;
// rule RL_wci_respF_decCtr
assign CAN_FIRE_RL_wci_respF_decCtr =
wci_respF_c_r != 2'd0 && !wci_respF_enqueueing$whas ;
assign WILL_FIRE_RL_wci_respF_decCtr = CAN_FIRE_RL_wci_respF_decCtr ;
// rule RL_wci_respF_incCtr
assign CAN_FIRE_RL_wci_respF_incCtr =
((wci_respF_c_r == 2'd0) ?
wci_respF_x_wire$whas :
wci_respF_c_r != 2'd1 || wci_respF_x_wire$whas) &&
wci_respF_enqueueing$whas &&
!(wci_respF_c_r != 2'd0) ;
assign WILL_FIRE_RL_wci_respF_incCtr = CAN_FIRE_RL_wci_respF_incCtr ;
// rule RL_wci_reqF__updateLevelCounter
assign CAN_FIRE_RL_wci_reqF__updateLevelCounter =
(wci_wciReq$wget[59:57] != 3'd0) != wci_reqF_r_deq$whas ;
assign WILL_FIRE_RL_wci_reqF__updateLevelCounter =
CAN_FIRE_RL_wci_reqF__updateLevelCounter ;
// inputs to muxes for submodule ports
assign MUX_wci_illegalEdge$write_1__SEL_1 =
WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge ;
assign MUX_wci_illegalEdge$write_1__VAL_2 =
wci_reqF$D_OUT[36:34] != 3'd4 && wci_reqF$D_OUT[36:34] != 3'd5 &&
wci_reqF$D_OUT[36:34] != 3'd6 ;
assign MUX_wci_respF_c_r$write_1__VAL_1 = wci_respF_c_r - 2'd1 ;
assign MUX_wci_respF_c_r$write_1__VAL_2 = wci_respF_c_r + 2'd1 ;
assign MUX_wci_respF_x_wire$wset_1__VAL_1 =
wci_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ;
assign MUX_wsiM_reqFifo_c_r$write_1__VAL_1 = wsiM_reqFifo_c_r - 2'd1 ;
assign MUX_wsiM_reqFifo_c_r$write_1__VAL_2 = wsiM_reqFifo_c_r + 2'd1 ;
assign MUX_wsiM_reqFifo_q_0$write_1__VAL_1 =
(wsiM_reqFifo_c_r == 2'd1) ?
wsiS_reqFifo$D_OUT :
wsiM_reqFifo_q_1 ;
assign MUX_wsiM_reqFifo_q_1$write_1__VAL_1 =
(wsiM_reqFifo_c_r == 2'd2) ?
wsiS_reqFifo$D_OUT :
313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00 ;
assign MUX_wci_illegalEdge$write_1__SEL_2 =
WILL_FIRE_RL_wci_ctl_op_start &&
(wci_reqF$D_OUT[36:34] == 3'd0 && wci_cState != 3'd0 ||
wci_reqF$D_OUT[36:34] == 3'd1 && wci_cState != 3'd1 &&
wci_cState != 3'd3 ||
wci_reqF$D_OUT[36:34] == 3'd2 && wci_cState != 3'd2 ||
wci_reqF$D_OUT[36:34] == 3'd3 && wci_cState != 3'd3 &&
wci_cState != 3'd2 &&
wci_cState != 3'd1 ||
wci_reqF$D_OUT[36:34] == 3'd4 ||
wci_reqF$D_OUT[36:34] == 3'd5 ||
wci_reqF$D_OUT[36:34] == 3'd6 ||
wci_reqF$D_OUT[36:34] == 3'd7) ;
assign MUX_wci_respF_q_0$write_1__SEL_2 =
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd0 ;
assign MUX_wci_respF_q_1$write_1__SEL_2 =
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd1 ;
assign MUX_wci_respF_x_wire$wset_1__VAL_2 = { 2'd1, x_data__h9902 } ;
always@(WILL_FIRE_RL_wci_ctl_op_complete or
MUX_wci_respF_x_wire$wset_1__VAL_1 or
WILL_FIRE_RL_wci_cfrd or
MUX_wci_respF_x_wire$wset_1__VAL_2 or WILL_FIRE_RL_wci_cfwr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wci_ctl_op_complete:
MUX_wci_respF_q_0$write_1__VAL_2 =
MUX_wci_respF_x_wire$wset_1__VAL_1;
WILL_FIRE_RL_wci_cfrd:
MUX_wci_respF_q_0$write_1__VAL_2 =
MUX_wci_respF_x_wire$wset_1__VAL_2;
WILL_FIRE_RL_wci_cfwr: MUX_wci_respF_q_0$write_1__VAL_2 = 34'h1C0DE4201;
default: MUX_wci_respF_q_0$write_1__VAL_2 =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign MUX_wci_respF_q_0$write_1__VAL_1 =
(wci_respF_c_r == 2'd1) ?
MUX_wci_respF_q_0$write_1__VAL_2 :
wci_respF_q_1 ;
assign MUX_wci_respF_q_1$write_1__VAL_1 =
(wci_respF_c_r == 2'd2) ?
MUX_wci_respF_q_0$write_1__VAL_2 :
34'h0AAAAAAAA ;
assign MUX_wsiM_reqFifo_q_0$write_1__SEL_2 =
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ;
assign MUX_wsiM_reqFifo_q_1$write_1__SEL_2 =
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ;
// inlined wires
assign wci_wciReq$wget =
{ wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData } ;
assign wci_wciReq$whas = 1'd1 ;
assign wci_reqF_r_enq$whas = CAN_FIRE_RL_wci_reqF_enq ;
assign wci_reqF_r_clr$whas = 1'b0 ;
assign wci_respF_dequeueing$whas = wci_respF_c_r != 2'd0 ;
assign wci_sThreadBusy_pw$whas = 1'b0 ;
assign wci_wEdge$wget = wci_reqF$D_OUT[36:34] ;
assign wci_sFlagReg_1$wget = 1'b0 ;
assign wci_sFlagReg_1$whas = 1'b0 ;
assign wci_wci_cfwr_pw$whas =
wci_reqF$EMPTY_N && wci_reqF$D_OUT[56] &&
wci_reqF$D_OUT[59:57] == 3'd1 ;
assign wci_wci_cfrd_pw$whas =
wci_reqF$EMPTY_N && wci_reqF$D_OUT[56] &&
wci_reqF$D_OUT[59:57] == 3'd2 ;
assign wsiS_wsiReq$wget =
{ wsiS0_MCmd,
wsiS0_MReqLast,
wsiS0_MBurstPrecise,
wsiS0_MBurstLength,
wsiS0_MData,
wsiS0_MByteEn,
wsiS0_MReqInfo } ;
assign wci_wci_ctrl_pw$whas =
wci_reqF$EMPTY_N && !wci_reqF$D_OUT[56] &&
wci_reqF$D_OUT[59:57] == 3'd2 ;
assign wci_reqF_r_deq$whas =
WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr ||
WILL_FIRE_RL_wci_ctl_op_start ;
assign wci_respF_enqueueing$whas =
WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr ||
WILL_FIRE_RL_wci_ctl_op_complete ;
assign wci_respF_x_wire$whas =
WILL_FIRE_RL_wci_ctl_op_complete || WILL_FIRE_RL_wci_cfrd ||
WILL_FIRE_RL_wci_cfwr ;
assign wci_wEdge$whas = WILL_FIRE_RL_wci_ctl_op_start ;
assign wsiS_reqFifo_r_clr$whas = 1'b0 ;
assign wci_ctlAckReg_1$wget = 1'd1 ;
assign wci_ctlAckReg_1$whas =
WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO ||
WILL_FIRE_RL_wci_ctrl_EiI ;
assign wsiS_wsiReq$whas = 1'd1 ;
assign wsiS_reqFifo_r_enq$whas = CAN_FIRE_RL_wsiS_reqFifo_enq ;
assign wsiS_operateD_1$wget = 1'd1 ;
assign wsiS_operateD_1$whas = CAN_FIRE_RL_operating_actions ;
assign wsiS_peerIsReady_1$wget = 1'd1 ;
assign wsiS_peerIsReady_1$whas = wsiS0_MReset_n ;
assign wsiS_extStatusW$wget =
{ wsiS_pMesgCount, wsiS_iMesgCount, wsiS_tBusyCount } ;
assign wsiM_reqFifo_x_wire$wget = wsiS_reqFifo$D_OUT ;
assign wsiM_sThreadBusy_pw$whas = wsiM0_SThreadBusy ;
assign wsiM_reqFifo_dequeueing$whas = CAN_FIRE_RL_wsiM_reqFifo_deq ;
assign wsiM_operateD_1$wget = 1'd1 ;
assign wsiM_operateD_1$whas = CAN_FIRE_RL_operating_actions ;
assign wsiM_peerIsReady_1$wget = 1'd1 ;
assign wsiM_peerIsReady_1$whas = wsiM0_SReset_n ;
assign wsiM_extStatusW$wget =
{ wsiM_pMesgCount, wsiM_iMesgCount, wsiM_tBusyCount } ;
assign wci_Es_mCmd_w$wget = wciS0_MCmd ;
assign wci_Es_mCmd_w$whas = 1'd1 ;
assign wci_Es_mAddrSpace_w$wget = wciS0_MAddrSpace ;
assign wci_Es_mAddrSpace_w$whas = 1'd1 ;
assign wci_Es_mAddr_w$wget = wciS0_MAddr ;
assign wci_Es_mData_w$wget = wciS0_MData ;
assign wci_Es_mAddr_w$whas = 1'd1 ;
assign wci_Es_mData_w$whas = 1'd1 ;
assign wci_Es_mByteEn_w$wget = wciS0_MByteEn ;
assign wci_Es_mByteEn_w$whas = 1'd1 ;
assign wsi_Es_mCmd_w$whas = 1'd1 ;
assign wsi_Es_mCmd_w$wget = wsiS0_MCmd ;
assign wsi_Es_mReqLast_w$whas = wsiS0_MReqLast ;
assign wsi_Es_mBurstPrecise_w$whas = wsiS0_MBurstPrecise ;
assign wsi_Es_mBurstLength_w$wget = wsiS0_MBurstLength ;
assign wsi_Es_mBurstLength_w$whas = 1'd1 ;
assign wsi_Es_mData_w$whas = 1'd1 ;
assign wsi_Es_mData_w$wget = wsiS0_MData ;
assign wsi_Es_mByteEn_w$wget = wsiS0_MByteEn ;
assign wsi_Es_mByteEn_w$whas = 1'd1 ;
assign wsi_Es_mReqInfo_w$wget = wsiS0_MReqInfo ;
assign wsi_Es_mReqInfo_w$whas = 1'd1 ;
assign wsi_Es_mDataInfo_w$whas = 1'd1 ;
assign wci_respF_x_wire$wget = MUX_wci_respF_q_0$write_1__VAL_2 ;
assign wsiS_reqFifo_r_deq$whas = CAN_FIRE_RL_wsipass_doMessagePush ;
assign wsiM_reqFifo_enqueueing$whas =
WILL_FIRE_RL_wsipass_doMessagePush &&
(frameGateCtrl[3:0] == 4'h0 ||
frameGateCtrl[3:0] == 4'h1 && !gated) ;
assign wsiM_reqFifo_x_wire$whas = wsiM_reqFifo_enqueueing$whas ;
// register byteCount
assign byteCount$D_IN =
NOT_gated_28_37_AND_byteCount_38_EQ_frameSize__ETC___d437 ?
32'd32 :
x__h9407 ;
assign byteCount$EN = CAN_FIRE_RL_wsipass_doMessagePush ;
// register frameGateCtrl
assign frameGateCtrl$D_IN = wci_reqF$D_OUT[31:0] ;
assign frameGateCtrl$EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF$D_OUT[51:32] == 20'h00004 ;
// register frameSize
assign frameSize$D_IN = wci_reqF$D_OUT[31:0] ;
assign frameSize$EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF$D_OUT[51:32] == 20'h00008 ;
// register gateSize
assign gateSize$D_IN = wci_reqF$D_OUT[31:0] ;
assign gateSize$EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF$D_OUT[51:32] == 20'h0000C ;
// register gated
assign gated$D_IN = !gated && byteCount == frameSize ;
assign gated$EN =
WILL_FIRE_RL_wsipass_doMessagePush &&
NOT_gated_28_37_AND_byteCount_38_EQ_frameSize__ETC___d437 ;
// register op0MesgCnt
assign op0MesgCnt$D_IN = 32'h0 ;
assign op0MesgCnt$EN = 1'b0 ;
// register otherMesgCnt
assign otherMesgCnt$D_IN = 32'h0 ;
assign otherMesgCnt$EN = 1'b0 ;
// register wci_cEdge
assign wci_cEdge$D_IN = wci_reqF$D_OUT[36:34] ;
assign wci_cEdge$EN = WILL_FIRE_RL_wci_ctl_op_start ;
// register wci_cState
assign wci_cState$D_IN = wci_nState ;
assign wci_cState$EN =
WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge ;
// register wci_ctlAckReg
assign wci_ctlAckReg$D_IN = wci_ctlAckReg_1$whas ;
assign wci_ctlAckReg$EN = 1'd1 ;
// register wci_ctlOpActive
assign wci_ctlOpActive$D_IN = !WILL_FIRE_RL_wci_ctl_op_complete ;
assign wci_ctlOpActive$EN =
WILL_FIRE_RL_wci_ctl_op_complete ||
WILL_FIRE_RL_wci_ctl_op_start ;
// register wci_illegalEdge
assign wci_illegalEdge$D_IN =
!MUX_wci_illegalEdge$write_1__SEL_1 &&
MUX_wci_illegalEdge$write_1__VAL_2 ;
assign wci_illegalEdge$EN =
WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge ||
MUX_wci_illegalEdge$write_1__SEL_2 ;
// register wci_nState
always@(wci_reqF$D_OUT)
begin
case (wci_reqF$D_OUT[36:34])
3'd0: wci_nState$D_IN = 3'd1;
3'd1: wci_nState$D_IN = 3'd2;
3'd2: wci_nState$D_IN = 3'd3;
default: wci_nState$D_IN = 3'd0;
endcase
end
assign wci_nState$EN =
WILL_FIRE_RL_wci_ctl_op_start &&
(wci_reqF$D_OUT[36:34] == 3'd0 && wci_cState == 3'd0 ||
wci_reqF$D_OUT[36:34] == 3'd1 &&
(wci_cState == 3'd1 || wci_cState == 3'd3) ||
wci_reqF$D_OUT[36:34] == 3'd2 && wci_cState == 3'd2 ||
wci_reqF$D_OUT[36:34] == 3'd3 &&
(wci_cState == 3'd3 || wci_cState == 3'd2 ||
wci_cState == 3'd1)) ;
// register wci_reqF_countReg
assign wci_reqF_countReg$D_IN =
(wci_wciReq$wget[59:57] != 3'd0) ?
wci_reqF_countReg + 2'd1 :
wci_reqF_countReg - 2'd1 ;
assign wci_reqF_countReg$EN = CAN_FIRE_RL_wci_reqF__updateLevelCounter ;
// register wci_respF_c_r
assign wci_respF_c_r$D_IN =
WILL_FIRE_RL_wci_respF_decCtr ?
MUX_wci_respF_c_r$write_1__VAL_1 :
MUX_wci_respF_c_r$write_1__VAL_2 ;
assign wci_respF_c_r$EN =
WILL_FIRE_RL_wci_respF_decCtr || WILL_FIRE_RL_wci_respF_incCtr ;
// register wci_respF_q_0
assign wci_respF_q_0$EN =
WILL_FIRE_RL_wci_respF_both ||
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd0 ||
WILL_FIRE_RL_wci_respF_decCtr ;
always@(WILL_FIRE_RL_wci_respF_both or
MUX_wci_respF_q_0$write_1__VAL_1 or
MUX_wci_respF_q_0$write_1__SEL_2 or
MUX_wci_respF_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wci_respF_decCtr or wci_respF_q_1)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wci_respF_both:
wci_respF_q_0$D_IN = MUX_wci_respF_q_0$write_1__VAL_1;
MUX_wci_respF_q_0$write_1__SEL_2:
wci_respF_q_0$D_IN = MUX_wci_respF_q_0$write_1__VAL_2;
WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_0$D_IN = wci_respF_q_1;
default: wci_respF_q_0$D_IN = 34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
// register wci_respF_q_1
assign wci_respF_q_1$EN =
WILL_FIRE_RL_wci_respF_both ||
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd1 ||
WILL_FIRE_RL_wci_respF_decCtr ;
always@(WILL_FIRE_RL_wci_respF_both or
MUX_wci_respF_q_1$write_1__VAL_1 or
MUX_wci_respF_q_1$write_1__SEL_2 or
MUX_wci_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_respF_decCtr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wci_respF_both:
wci_respF_q_1$D_IN = MUX_wci_respF_q_1$write_1__VAL_1;
MUX_wci_respF_q_1$write_1__SEL_2:
wci_respF_q_1$D_IN = MUX_wci_respF_q_0$write_1__VAL_2;
WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_1$D_IN = 34'h0AAAAAAAA;
default: wci_respF_q_1$D_IN = 34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
// register wci_sFlagReg
assign wci_sFlagReg$D_IN = 1'b0 ;
assign wci_sFlagReg$EN = 1'd1 ;
// register wci_sThreadBusy_d
assign wci_sThreadBusy_d$D_IN = 1'b0 ;
assign wci_sThreadBusy_d$EN = 1'd1 ;
// register wsiM_burstKind
assign wsiM_burstKind$D_IN =
(wsiM_burstKind == 2'd0) ?
(wsiM_reqFifo_q_0[308] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsiM_burstKind$EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[312:310] == 3'd1 &&
(wsiM_burstKind == 2'd0 ||
(wsiM_burstKind == 2'd1 || wsiM_burstKind == 2'd2) &&
wsiM_reqFifo_q_0[309]) ;
// register wsiM_errorSticky
assign wsiM_errorSticky$D_IN = 1'b0 ;
assign wsiM_errorSticky$EN = 1'b0 ;
// register wsiM_iMesgCount
assign wsiM_iMesgCount$D_IN = wsiM_iMesgCount + 32'd1 ;
assign wsiM_iMesgCount$EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[312:310] == 3'd1 &&
wsiM_burstKind == 2'd2 &&
wsiM_reqFifo_q_0[309] ;
// register wsiM_operateD
assign wsiM_operateD$D_IN = CAN_FIRE_RL_operating_actions ;
assign wsiM_operateD$EN = 1'd1 ;
// register wsiM_pMesgCount
assign wsiM_pMesgCount$D_IN = wsiM_pMesgCount + 32'd1 ;
assign wsiM_pMesgCount$EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[312:310] == 3'd1 &&
wsiM_burstKind == 2'd1 &&
wsiM_reqFifo_q_0[309] ;
// register wsiM_peerIsReady
assign wsiM_peerIsReady$D_IN = wsiM0_SReset_n ;
assign wsiM_peerIsReady$EN = 1'd1 ;
// register wsiM_reqFifo_c_r
assign wsiM_reqFifo_c_r$D_IN =
WILL_FIRE_RL_wsiM_reqFifo_decCtr ?
MUX_wsiM_reqFifo_c_r$write_1__VAL_1 :
MUX_wsiM_reqFifo_c_r$write_1__VAL_2 ;
assign wsiM_reqFifo_c_r$EN =
WILL_FIRE_RL_wsiM_reqFifo_decCtr ||
WILL_FIRE_RL_wsiM_reqFifo_incCtr ;
// register wsiM_reqFifo_q_0
always@(WILL_FIRE_RL_wsiM_reqFifo_both or
MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or
MUX_wsiM_reqFifo_q_0$write_1__SEL_2 or
wsiS_reqFifo$D_OUT or
WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wsiM_reqFifo_both:
wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1;
MUX_wsiM_reqFifo_q_0$write_1__SEL_2:
wsiM_reqFifo_q_0$D_IN = wsiS_reqFifo$D_OUT;
WILL_FIRE_RL_wsiM_reqFifo_decCtr:
wsiM_reqFifo_q_0$D_IN = wsiM_reqFifo_q_1;
default: wsiM_reqFifo_q_0$D_IN =
313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsiM_reqFifo_q_0$EN =
WILL_FIRE_RL_wsiM_reqFifo_both ||
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ||
WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
// register wsiM_reqFifo_q_1
always@(WILL_FIRE_RL_wsiM_reqFifo_both or
MUX_wsiM_reqFifo_q_1$write_1__VAL_1 or
MUX_wsiM_reqFifo_q_1$write_1__SEL_2 or
wsiS_reqFifo$D_OUT or WILL_FIRE_RL_wsiM_reqFifo_decCtr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wsiM_reqFifo_both:
wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_1$write_1__VAL_1;
MUX_wsiM_reqFifo_q_1$write_1__SEL_2:
wsiM_reqFifo_q_1$D_IN = wsiS_reqFifo$D_OUT;
WILL_FIRE_RL_wsiM_reqFifo_decCtr:
wsiM_reqFifo_q_1$D_IN =
313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00;
default: wsiM_reqFifo_q_1$D_IN =
313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsiM_reqFifo_q_1$EN =
WILL_FIRE_RL_wsiM_reqFifo_both ||
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ||
WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
// register wsiM_sThreadBusy_d
assign wsiM_sThreadBusy_d$D_IN = wsiM0_SThreadBusy ;
assign wsiM_sThreadBusy_d$EN = 1'd1 ;
// register wsiM_statusR
assign wsiM_statusR$D_IN =
{ wsiM_isReset$VAL,
!wsiM_peerIsReady,
!wsiM_operateD,
wsiM_errorSticky,
wsiM_burstKind != 2'd0,
wsiM_sThreadBusy_d,
1'd0,
wsiM_trafficSticky } ;
assign wsiM_statusR$EN = 1'd1 ;
// register wsiM_tBusyCount
assign wsiM_tBusyCount$D_IN = wsiM_tBusyCount + 32'd1 ;
assign wsiM_tBusyCount$EN = CAN_FIRE_RL_wsiM_inc_tBusyCount ;
// register wsiM_trafficSticky
assign wsiM_trafficSticky$D_IN = 1'd1 ;
assign wsiM_trafficSticky$EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[312:310] == 3'd1 ;
// register wsiS_burstKind
assign wsiS_burstKind$D_IN =
(wsiS_burstKind == 2'd0) ?
(wsiS_wsiReq$wget[308] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsiS_burstKind$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq &&
(wsiS_burstKind == 2'd0 ||
(wsiS_burstKind == 2'd1 || wsiS_burstKind == 2'd2) &&
wsiS_wsiReq$wget[309]) ;
// register wsiS_errorSticky
assign wsiS_errorSticky$D_IN = 1'd1 ;
assign wsiS_errorSticky$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && !wsiS_reqFifo$FULL_N ;
// register wsiS_iMesgCount
assign wsiS_iMesgCount$D_IN = wsiS_iMesgCount + 32'd1 ;
assign wsiS_iMesgCount$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'd2 &&
wsiS_wsiReq$wget[309] ;
// register wsiS_operateD
assign wsiS_operateD$D_IN = CAN_FIRE_RL_operating_actions ;
assign wsiS_operateD$EN = 1'd1 ;
// register wsiS_pMesgCount
assign wsiS_pMesgCount$D_IN = wsiS_pMesgCount + 32'd1 ;
assign wsiS_pMesgCount$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'd1 &&
wsiS_wsiReq$wget[309] ;
// register wsiS_peerIsReady
assign wsiS_peerIsReady$D_IN = wsiS0_MReset_n ;
assign wsiS_peerIsReady$EN = 1'd1 ;
// register wsiS_reqFifo_countReg
assign wsiS_reqFifo_countReg$D_IN =
CAN_FIRE_RL_wsiS_reqFifo_enq ?
wsiS_reqFifo_countReg + 2'd1 :
wsiS_reqFifo_countReg - 2'd1 ;
assign wsiS_reqFifo_countReg$EN =
CAN_FIRE_RL_wsiS_reqFifo__updateLevelCounter ;
// register wsiS_statusR
assign wsiS_statusR$EN = 1'd1 ;
assign wsiS_statusR$D_IN =
{ wsiS_isReset$VAL,
!wsiS_peerIsReady,
!wsiS_operateD,
wsiS_errorSticky,
wsiS_burstKind != 2'd0,
NOT_wsiS_reqFifo_countReg_32_ULE_1_33___d234 ||
wsiS_isReset$VAL ||
!wsiS_operateD ||
!wsiS_peerIsReady,
1'd0,
wsiS_trafficSticky } ;
// register wsiS_tBusyCount
assign wsiS_tBusyCount$D_IN = wsiS_tBusyCount + 32'd1 ;
assign wsiS_tBusyCount$EN = CAN_FIRE_RL_wsiS_inc_tBusyCount ;
// register wsiS_trafficSticky
assign wsiS_trafficSticky$D_IN = 1'd1 ;
assign wsiS_trafficSticky$EN = CAN_FIRE_RL_wsiS_reqFifo_enq ;
// submodule wci_reqF
assign wci_reqF$D_IN = wci_wciReq$wget ;
assign wci_reqF$DEQ = wci_reqF_r_deq$whas ;
assign wci_reqF$ENQ = CAN_FIRE_RL_wci_reqF_enq ;
assign wci_reqF$CLR = 1'b0 ;
// submodule wsiS_reqFifo
assign wsiS_reqFifo$D_IN = wsiS_wsiReq$wget ;
assign wsiS_reqFifo$ENQ = CAN_FIRE_RL_wsiS_reqFifo_enq ;
assign wsiS_reqFifo$CLR = 1'b0 ;
assign wsiS_reqFifo$DEQ = CAN_FIRE_RL_wsipass_doMessagePush ;
// remaining internal signals
assign NOT_gated_28_37_AND_byteCount_38_EQ_frameSize__ETC___d437 =
!gated && byteCount == frameSize ||
gated && byteCount == gateSize ;
assign NOT_wsiS_reqFifo_countReg_32_ULE_1_33___d234 =
wsiS_reqFifo_countReg > 2'd1 ;
assign frameGateStatus__h9658 = { 31'd0, hasDebugLogic } ;
assign rdat__h10036 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ;
assign rdat__h10050 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ;
assign rdat__h10058 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ;
assign rdat__h10064 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ;
assign rdat__h10078 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ;
assign rdat__h10086 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ;
assign rdat__h10092 = hasDebugLogic ? op0MesgCnt : 32'd0 ;
assign rdat__h10103 = hasDebugLogic ? otherMesgCnt : 32'd0 ;
assign rdat__h9936 = hasDebugLogic ? { 16'd0, x__h9940 } : 32'd0 ;
assign wsiS_reqFifo_i_notEmpty__22_AND_NOT_frameGateC_ETC___d135 =
wsiS_reqFifo$EMPTY_N &&
(frameGateCtrl[3:0] != 4'h0 &&
(frameGateCtrl[3:0] != 4'h1 || gated) ||
wsiM_reqFifo_c_r != 2'd2) ;
assign x__h9407 = byteCount + 32'd32 ;
assign x__h9940 = { wsiS_statusR, wsiM_statusR } ;
always@(wci_reqF$D_OUT or
frameGateStatus__h9658 or
frameGateCtrl or
frameSize or
gateSize or
rdat__h9936 or
rdat__h10036 or
rdat__h10050 or
rdat__h10058 or
rdat__h10064 or
rdat__h10078 or rdat__h10086 or rdat__h10092 or rdat__h10103)
begin
case (wci_reqF$D_OUT[51:32])
20'h0: x_data__h9902 = frameGateStatus__h9658;
20'h00004: x_data__h9902 = frameGateCtrl;
20'h00008: x_data__h9902 = frameSize;
20'h0000C: x_data__h9902 = gateSize;
20'h00010: x_data__h9902 = rdat__h9936;
20'h00014: x_data__h9902 = rdat__h10036;
20'h00018: x_data__h9902 = rdat__h10050;
20'h0001C: x_data__h9902 = rdat__h10058;
20'h00020: x_data__h9902 = rdat__h10064;
20'h00024: x_data__h9902 = rdat__h10078;
20'h00028: x_data__h9902 = rdat__h10086;
20'h0002C: x_data__h9902 = rdat__h10092;
20'h00030: x_data__h9902 = rdat__h10103;
default: x_data__h9902 = 32'd0;
endcase
end
// handling of inlined registers
always@(posedge wciS0_Clk)
begin
if (!wciS0_MReset_n)
begin
byteCount <= `BSV_ASSIGNMENT_DELAY 32'd32;
frameGateCtrl <= `BSV_ASSIGNMENT_DELAY fgCtrlInit;
frameSize <= `BSV_ASSIGNMENT_DELAY 32'd0;
gateSize <= `BSV_ASSIGNMENT_DELAY 32'd0;
gated <= `BSV_ASSIGNMENT_DELAY 1'd0;
op0MesgCnt <= `BSV_ASSIGNMENT_DELAY 32'd0;
otherMesgCnt <= `BSV_ASSIGNMENT_DELAY 32'd0;
wci_cEdge <= `BSV_ASSIGNMENT_DELAY 3'd7;
wci_cState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_ctlAckReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_ctlOpActive <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_nState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY
313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00;
wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY
313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00;
wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (byteCount$EN) byteCount <= `BSV_ASSIGNMENT_DELAY byteCount$D_IN;
if (frameGateCtrl$EN)
frameGateCtrl <= `BSV_ASSIGNMENT_DELAY frameGateCtrl$D_IN;
if (frameSize$EN) frameSize <= `BSV_ASSIGNMENT_DELAY frameSize$D_IN;
if (gateSize$EN) gateSize <= `BSV_ASSIGNMENT_DELAY gateSize$D_IN;
if (gated$EN) gated <= `BSV_ASSIGNMENT_DELAY gated$D_IN;
if (op0MesgCnt$EN)
op0MesgCnt <= `BSV_ASSIGNMENT_DELAY op0MesgCnt$D_IN;
if (otherMesgCnt$EN)
otherMesgCnt <= `BSV_ASSIGNMENT_DELAY otherMesgCnt$D_IN;
if (wci_cEdge$EN) wci_cEdge <= `BSV_ASSIGNMENT_DELAY wci_cEdge$D_IN;
if (wci_cState$EN)
wci_cState <= `BSV_ASSIGNMENT_DELAY wci_cState$D_IN;
if (wci_ctlAckReg$EN)
wci_ctlAckReg <= `BSV_ASSIGNMENT_DELAY wci_ctlAckReg$D_IN;
if (wci_ctlOpActive$EN)
wci_ctlOpActive <= `BSV_ASSIGNMENT_DELAY wci_ctlOpActive$D_IN;
if (wci_illegalEdge$EN)
wci_illegalEdge <= `BSV_ASSIGNMENT_DELAY wci_illegalEdge$D_IN;
if (wci_nState$EN)
wci_nState <= `BSV_ASSIGNMENT_DELAY wci_nState$D_IN;
if (wci_reqF_countReg$EN)
wci_reqF_countReg <= `BSV_ASSIGNMENT_DELAY wci_reqF_countReg$D_IN;
if (wci_respF_c_r$EN)
wci_respF_c_r <= `BSV_ASSIGNMENT_DELAY wci_respF_c_r$D_IN;
if (wci_respF_q_0$EN)
wci_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_respF_q_0$D_IN;
if (wci_respF_q_1$EN)
wci_respF_q_1 <= `BSV_ASSIGNMENT_DELAY wci_respF_q_1$D_IN;
if (wci_sFlagReg$EN)
wci_sFlagReg <= `BSV_ASSIGNMENT_DELAY wci_sFlagReg$D_IN;
if (wci_sThreadBusy_d$EN)
wci_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wci_sThreadBusy_d$D_IN;
if (wsiM_burstKind$EN)
wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY wsiM_burstKind$D_IN;
if (wsiM_errorSticky$EN)
wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiM_errorSticky$D_IN;
if (wsiM_iMesgCount$EN)
wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_iMesgCount$D_IN;
if (wsiM_operateD$EN)
wsiM_operateD <= `BSV_ASSIGNMENT_DELAY wsiM_operateD$D_IN;
if (wsiM_pMesgCount$EN)
wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_pMesgCount$D_IN;
if (wsiM_peerIsReady$EN)
wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiM_peerIsReady$D_IN;
if (wsiM_reqFifo_c_r$EN)
wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_c_r$D_IN;
if (wsiM_reqFifo_q_0$EN)
wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_0$D_IN;
if (wsiM_reqFifo_q_1$EN)
wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_1$D_IN;
if (wsiM_sThreadBusy_d$EN)
wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wsiM_sThreadBusy_d$D_IN;
if (wsiM_tBusyCount$EN)
wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiM_tBusyCount$D_IN;
if (wsiM_trafficSticky$EN)
wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiM_trafficSticky$D_IN;
if (wsiS_burstKind$EN)
wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY wsiS_burstKind$D_IN;
if (wsiS_errorSticky$EN)
wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiS_errorSticky$D_IN;
if (wsiS_iMesgCount$EN)
wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_iMesgCount$D_IN;
if (wsiS_operateD$EN)
wsiS_operateD <= `BSV_ASSIGNMENT_DELAY wsiS_operateD$D_IN;
if (wsiS_pMesgCount$EN)
wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_pMesgCount$D_IN;
if (wsiS_peerIsReady$EN)
wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiS_peerIsReady$D_IN;
if (wsiS_reqFifo_countReg$EN)
wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY
wsiS_reqFifo_countReg$D_IN;
if (wsiS_tBusyCount$EN)
wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiS_tBusyCount$D_IN;
if (wsiS_trafficSticky$EN)
wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiS_trafficSticky$D_IN;
end
if (wsiM_statusR$EN)
wsiM_statusR <= `BSV_ASSIGNMENT_DELAY wsiM_statusR$D_IN;
if (wsiS_statusR$EN)
wsiS_statusR <= `BSV_ASSIGNMENT_DELAY wsiS_statusR$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
byteCount = 32'hAAAAAAAA;
frameGateCtrl = 32'hAAAAAAAA;
frameSize = 32'hAAAAAAAA;
gateSize = 32'hAAAAAAAA;
gated = 1'h0;
op0MesgCnt = 32'hAAAAAAAA;
otherMesgCnt = 32'hAAAAAAAA;
wci_cEdge = 3'h2;
wci_cState = 3'h2;
wci_ctlAckReg = 1'h0;
wci_ctlOpActive = 1'h0;
wci_illegalEdge = 1'h0;
wci_nState = 3'h2;
wci_reqF_countReg = 2'h2;
wci_respF_c_r = 2'h2;
wci_respF_q_0 = 34'h2AAAAAAAA;
wci_respF_q_1 = 34'h2AAAAAAAA;
wci_sFlagReg = 1'h0;
wci_sThreadBusy_d = 1'h0;
wsiM_burstKind = 2'h2;
wsiM_errorSticky = 1'h0;
wsiM_iMesgCount = 32'hAAAAAAAA;
wsiM_operateD = 1'h0;
wsiM_pMesgCount = 32'hAAAAAAAA;
wsiM_peerIsReady = 1'h0;
wsiM_reqFifo_c_r = 2'h2;
wsiM_reqFifo_q_0 =
313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wsiM_reqFifo_q_1 =
313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wsiM_sThreadBusy_d = 1'h0;
wsiM_statusR = 8'hAA;
wsiM_tBusyCount = 32'hAAAAAAAA;
wsiM_trafficSticky = 1'h0;
wsiS_burstKind = 2'h2;
wsiS_errorSticky = 1'h0;
wsiS_iMesgCount = 32'hAAAAAAAA;
wsiS_operateD = 1'h0;
wsiS_pMesgCount = 32'hAAAAAAAA;
wsiS_peerIsReady = 1'h0;
wsiS_reqFifo_countReg = 2'h2;
wsiS_statusR = 8'hAA;
wsiS_tBusyCount = 32'hAAAAAAAA;
wsiS_trafficSticky = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge wciS0_Clk)
begin
#0;
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctl_op_start)
begin
v__h3684 = $time;
#0;
end
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctl_op_start)
$display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x",
v__h3684,
wci_reqF$D_OUT[36:34],
wci_cState);
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctrl_IsO)
begin
v__h9770 = $time;
#0;
end
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctrl_IsO)
$display("[%0d]: %m: Starting FrameGate frameGateCtrl:%0x",
v__h9770,
frameGateCtrl);
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/FrameGate.bsv\", line 104, column 6: (R0001)\n Mutually exclusive rules RL_wci_ctrl_IsO and RL_wci_ctrl_EiI fired in the\n same clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctrl_OrE && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/FrameGate.bsv\", line 110, column 6: (R0001)\n Mutually exclusive rules RL_wci_ctrl_OrE and RL_wci_ctrl_IsO fired in the\n same clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctrl_OrE && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/FrameGate.bsv\", line 110, column 6: (R0001)\n Mutually exclusive rules RL_wci_ctrl_OrE and RL_wci_ctrl_EiI fired in the\n same clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/FrameGate.bsv\", line 83, column 6: (R0001)\n Mutually exclusive rules RL_wci_cfrd and RL_wci_ctrl_OrE fired in the same\n clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/FrameGate.bsv\", line 83, column 6: (R0001)\n Mutually exclusive rules RL_wci_cfrd and RL_wci_ctrl_IsO fired in the same\n clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/FrameGate.bsv\", line 83, column 6: (R0001)\n Mutually exclusive rules RL_wci_cfrd and RL_wci_ctrl_EiI fired in the same\n clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge)
begin
v__h2785 = $time;
#0;
end
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x",
v__h2785,
wci_cEdge,
wci_cState);
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge)
begin
v__h2638 = $time;
#0;
end
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x",
v__h2638,
wci_cEdge,
wci_cState,
wci_nState);
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/FrameGate.bsv\", line 72, column 6: (R0001)\n Mutually exclusive rules RL_wci_cfwr and RL_wci_ctrl_OrE fired in the same\n clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/FrameGate.bsv\", line 72, column 6: (R0001)\n Mutually exclusive rules RL_wci_cfwr and RL_wci_ctrl_IsO fired in the same\n clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/FrameGate.bsv\", line 72, column 6: (R0001)\n Mutually exclusive rules RL_wci_cfwr and RL_wci_ctrl_EiI fired in the same\n clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd)
$display("Error: \"bsv/FrameGate.bsv\", line 72, column 6: (R0001)\n Mutually exclusive rules RL_wci_cfwr and RL_wci_cfrd fired in the same clock\n cycle.\n");
end
// synopsys translate_on
endmodule // mkFrameGate32B
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:07:33 06/29/2015
// Design Name:
// Module Name: pc0
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module pc0(
clk,rst,interrupt_signal,cp_oper,cp_cd,return_addr,GPR,jump_en,CPR,jump_addr
);
input clk,rst;
input [1:0] interrupt_signal;
input [1:0] cp_oper;//10 ret 01 mtc
input [4:0] cp_cd;//read or write address rd
input [31:0] return_addr,GPR;//write data
output jump_en;//epc_ctrl;
output [31:0] CPR;//read data
output [31:0] jump_addr;//epc;
reg [31:0] mem [31:0];
wire inter;
assign inter=|interrupt_signal;
always @(negedge clk or posedge rst or posedge inter)
begin
if(rst)
begin
mem[0] <=32'b0;mem[1] <=32'b0;mem[2] <=32'b0;mem[3] <=32'b0;
mem[4] <=32'b0;mem[5] <=32'b0;mem[6] <=32'b0;mem[7] <=32'b0;
mem[8] <=32'b0;mem[9] <=32'b0;mem[10]<=32'b0;mem[11]<=32'b0;
mem[12]<=32'b0;mem[13]<=32'b0;mem[14]<=32'b0;mem[15]<=32'b0;
mem[16]<=32'b0;mem[17]<=32'b0;mem[18]<=32'b0;mem[19]<=32'b0;
mem[20]<=32'b0;mem[21]<=32'b0;mem[22]<=32'b0;mem[23]<=32'b0;
mem[24]<=32'b0;mem[25]<=32'b0;mem[26]<=32'b0;mem[27]<=32'b0;
mem[28]<=32'b0;mem[29]<=32'b0;mem[30]<=32'b0;mem[31]<=32'b0;
end
else if(inter)
begin
mem[13] <= {30'b0,interrupt_signal};
mem[14] <= return_addr;
end
else if(cp_oper[0])
mem[cp_cd]<=GPR;
end
assign CPR = mem[cp_cd];
assign jump_en = inter | cp_oper[1];
assign jump_addr = (inter)?mem[1]:mem[14];//ehb=mem[1] epc = mem[14]; //R14 EPC
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__TAPVGND_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__TAPVGND_BEHAVIORAL_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection 1
* row down.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__tapvgnd ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__TAPVGND_BEHAVIORAL_V |
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_cpu_s0_jtag_debug_module_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title :
// File :
// Author : Jim MacLeod
// Created : 01-Dec-2011
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module flt_div
(
input clk,
input rstn,
input [63:0] numer_denom,
output [31:0] div_result
);
wire [31:0] numer_d_fp;
wire [31:0] quot_fp;
// Float Divide (Seven Clock Cycles).
flt_recip u0_flt_recip(.clk(clk), .denom(numer_denom[31:0]), .recip(quot_fp));
gen_pipe #(32, 6) u0_gen_pipe(.clk(clk), .din(numer_denom[63:32]), .dout(numer_d_fp));
flt_mult u2_flt_mult(clk, rstn, numer_d_fp, quot_fp, div_result);
endmodule
|
//======================================================================
//
// Design Name: PRESENT Block Cipher
// Module Name: PRESENT_ENCRYPT_PBOX
// Language: Verilog-2001
//
// Description: Permutation Layer (p-Layer or p-box) of PRESENT Encryption
//
// Dependencies: none
//
// Designer: Saied H. Khayat
// Date: 3/2011
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// condition is met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
`timescale 1ns/1ps
module PRESENT_ENCRYPT_PBOX(
output [63:0] odat,
input [63:0] idat
);
assign odat[0 ] = idat[0 ];
assign odat[16] = idat[1 ];
assign odat[32] = idat[2 ];
assign odat[48] = idat[3 ];
assign odat[1 ] = idat[4 ];
assign odat[17] = idat[5 ];
assign odat[33] = idat[6 ];
assign odat[49] = idat[7 ];
assign odat[2 ] = idat[8 ];
assign odat[18] = idat[9 ];
assign odat[34] = idat[10];
assign odat[50] = idat[11];
assign odat[3 ] = idat[12];
assign odat[19] = idat[13];
assign odat[35] = idat[14];
assign odat[51] = idat[15];
assign odat[4 ] = idat[16];
assign odat[20] = idat[17];
assign odat[36] = idat[18];
assign odat[52] = idat[19];
assign odat[5 ] = idat[20];
assign odat[21] = idat[21];
assign odat[37] = idat[22];
assign odat[53] = idat[23];
assign odat[6 ] = idat[24];
assign odat[22] = idat[25];
assign odat[38] = idat[26];
assign odat[54] = idat[27];
assign odat[7 ] = idat[28];
assign odat[23] = idat[29];
assign odat[39] = idat[30];
assign odat[55] = idat[31];
assign odat[8 ] = idat[32];
assign odat[24] = idat[33];
assign odat[40] = idat[34];
assign odat[56] = idat[35];
assign odat[9 ] = idat[36];
assign odat[25] = idat[37];
assign odat[41] = idat[38];
assign odat[57] = idat[39];
assign odat[10] = idat[40];
assign odat[26] = idat[41];
assign odat[42] = idat[42];
assign odat[58] = idat[43];
assign odat[11] = idat[44];
assign odat[27] = idat[45];
assign odat[43] = idat[46];
assign odat[59] = idat[47];
assign odat[12] = idat[48];
assign odat[28] = idat[49];
assign odat[44] = idat[50];
assign odat[60] = idat[51];
assign odat[13] = idat[52];
assign odat[29] = idat[53];
assign odat[45] = idat[54];
assign odat[61] = idat[55];
assign odat[14] = idat[56];
assign odat[30] = idat[57];
assign odat[46] = idat[58];
assign odat[62] = idat[59];
assign odat[15] = idat[60];
assign odat[31] = idat[61];
assign odat[47] = idat[62];
assign odat[63] = idat[63];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O211AI_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__O211AI_PP_BLACKBOX_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o211ai (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O211AI_PP_BLACKBOX_V
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:module_ref:not_1bit:1.0
// IP Revision: 1
(* X_CORE_INFO = "not_1bit,Vivado 2016.2" *)
(* CHECK_LICENSE_TYPE = "image_processing_2d_design_not_1bit_0_0,not_1bit,{}" *)
(* CORE_GENERATION_INFO = "image_processing_2d_design_not_1bit_0_0,not_1bit,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=not_1bit,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module image_processing_2d_design_not_1bit_0_0 (
inp,
outp
);
input wire inp;
output wire outp;
not_1bit inst (
.inp(inp),
.outp(outp)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISO0N_BLACKBOX_V
`define SKY130_FD_SC_LP__ISO0N_BLACKBOX_V
/**
* iso0n: ????.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__iso0n (
X ,
A ,
SLEEP_B
);
output X ;
input A ;
input SLEEP_B;
// Voltage supply signals
supply1 VPWR ;
supply0 KAGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISO0N_BLACKBOX_V
|
//Legal Notice: (C)2019 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_dut_pio_1 (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 2: 0] address;
input clk;
input [ 31: 0] in_port;
input reset_n;
wire clk_en;
wire [ 31: 0] data_in;
wire [ 31: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {32 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O21BAI_PP_SYMBOL_V
`define SKY130_FD_SC_MS__O21BAI_PP_SYMBOL_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o21bai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1_N,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O21BAI_PP_SYMBOL_V
|
// mi_nios_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.1 186 at 2015.05.20.08:55:19
`timescale 1 ps / 1 ps
module mi_nios_mm_interconnect_0 (
input wire clk_50_clk_clk, // clk_50_clk.clk
input wire pll_c0_clk, // pll_c0.clk
input wire cpu_reset_n_reset_bridge_in_reset_reset, // cpu_reset_n_reset_bridge_in_reset.reset
input wire flash_reset_reset_bridge_in_reset_reset, // flash_reset_reset_bridge_in_reset.reset
input wire jtag_reset_reset_bridge_in_reset_reset, // jtag_reset_reset_bridge_in_reset.reset
input wire [24:0] cpu_data_master_address, // cpu_data_master.address
output wire cpu_data_master_waitrequest, // .waitrequest
input wire [3:0] cpu_data_master_byteenable, // .byteenable
input wire cpu_data_master_read, // .read
output wire [31:0] cpu_data_master_readdata, // .readdata
input wire cpu_data_master_write, // .write
input wire [31:0] cpu_data_master_writedata, // .writedata
input wire cpu_data_master_debugaccess, // .debugaccess
input wire [24:0] cpu_instruction_master_address, // cpu_instruction_master.address
output wire cpu_instruction_master_waitrequest, // .waitrequest
input wire cpu_instruction_master_read, // .read
output wire [31:0] cpu_instruction_master_readdata, // .readdata
output wire [8:0] cpu_jtag_debug_module_address, // cpu_jtag_debug_module.address
output wire cpu_jtag_debug_module_write, // .write
output wire cpu_jtag_debug_module_read, // .read
input wire [31:0] cpu_jtag_debug_module_readdata, // .readdata
output wire [31:0] cpu_jtag_debug_module_writedata, // .writedata
output wire [3:0] cpu_jtag_debug_module_byteenable, // .byteenable
input wire cpu_jtag_debug_module_waitrequest, // .waitrequest
output wire cpu_jtag_debug_module_debugaccess, // .debugaccess
output wire [8:0] flash_epcs_control_port_address, // flash_epcs_control_port.address
output wire flash_epcs_control_port_write, // .write
output wire flash_epcs_control_port_read, // .read
input wire [31:0] flash_epcs_control_port_readdata, // .readdata
output wire [31:0] flash_epcs_control_port_writedata, // .writedata
output wire flash_epcs_control_port_chipselect, // .chipselect
output wire [0:0] jtag_avalon_jtag_slave_address, // jtag_avalon_jtag_slave.address
output wire jtag_avalon_jtag_slave_write, // .write
output wire jtag_avalon_jtag_slave_read, // .read
input wire [31:0] jtag_avalon_jtag_slave_readdata, // .readdata
output wire [31:0] jtag_avalon_jtag_slave_writedata, // .writedata
input wire jtag_avalon_jtag_slave_waitrequest, // .waitrequest
output wire jtag_avalon_jtag_slave_chipselect, // .chipselect
output wire [1:0] LED_s1_address, // LED_s1.address
output wire LED_s1_write, // .write
input wire [31:0] LED_s1_readdata, // .readdata
output wire [31:0] LED_s1_writedata, // .writedata
output wire LED_s1_chipselect, // .chipselect
output wire [21:0] sdram_s1_address, // sdram_s1.address
output wire sdram_s1_write, // .write
output wire sdram_s1_read, // .read
input wire [15:0] sdram_s1_readdata, // .readdata
output wire [15:0] sdram_s1_writedata, // .writedata
output wire [1:0] sdram_s1_byteenable, // .byteenable
input wire sdram_s1_readdatavalid, // .readdatavalid
input wire sdram_s1_waitrequest, // .waitrequest
output wire sdram_s1_chipselect, // .chipselect
output wire [1:0] SW_s1_address, // SW_s1.address
input wire [31:0] SW_s1_readdata, // .readdata
output wire [0:0] sysid_control_slave_address, // sysid_control_slave.address
input wire [31:0] sysid_control_slave_readdata, // .readdata
output wire [2:0] timer_s1_address, // timer_s1.address
output wire timer_s1_write, // .write
input wire [15:0] timer_s1_readdata, // .readdata
output wire [15:0] timer_s1_writedata, // .writedata
output wire timer_s1_chipselect // .chipselect
);
wire cpu_data_master_translator_avalon_universal_master_0_waitrequest; // cpu_data_master_agent:av_waitrequest -> cpu_data_master_translator:uav_waitrequest
wire [31:0] cpu_data_master_translator_avalon_universal_master_0_readdata; // cpu_data_master_agent:av_readdata -> cpu_data_master_translator:uav_readdata
wire cpu_data_master_translator_avalon_universal_master_0_debugaccess; // cpu_data_master_translator:uav_debugaccess -> cpu_data_master_agent:av_debugaccess
wire [24:0] cpu_data_master_translator_avalon_universal_master_0_address; // cpu_data_master_translator:uav_address -> cpu_data_master_agent:av_address
wire cpu_data_master_translator_avalon_universal_master_0_read; // cpu_data_master_translator:uav_read -> cpu_data_master_agent:av_read
wire [3:0] cpu_data_master_translator_avalon_universal_master_0_byteenable; // cpu_data_master_translator:uav_byteenable -> cpu_data_master_agent:av_byteenable
wire cpu_data_master_translator_avalon_universal_master_0_readdatavalid; // cpu_data_master_agent:av_readdatavalid -> cpu_data_master_translator:uav_readdatavalid
wire cpu_data_master_translator_avalon_universal_master_0_lock; // cpu_data_master_translator:uav_lock -> cpu_data_master_agent:av_lock
wire cpu_data_master_translator_avalon_universal_master_0_write; // cpu_data_master_translator:uav_write -> cpu_data_master_agent:av_write
wire [31:0] cpu_data_master_translator_avalon_universal_master_0_writedata; // cpu_data_master_translator:uav_writedata -> cpu_data_master_agent:av_writedata
wire [2:0] cpu_data_master_translator_avalon_universal_master_0_burstcount; // cpu_data_master_translator:uav_burstcount -> cpu_data_master_agent:av_burstcount
wire rsp_mux_src_valid; // rsp_mux:src_valid -> cpu_data_master_agent:rp_valid
wire [100:0] rsp_mux_src_data; // rsp_mux:src_data -> cpu_data_master_agent:rp_data
wire rsp_mux_src_ready; // cpu_data_master_agent:rp_ready -> rsp_mux:src_ready
wire [7:0] rsp_mux_src_channel; // rsp_mux:src_channel -> cpu_data_master_agent:rp_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> cpu_data_master_agent:rp_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> cpu_data_master_agent:rp_endofpacket
wire cpu_instruction_master_translator_avalon_universal_master_0_waitrequest; // cpu_instruction_master_agent:av_waitrequest -> cpu_instruction_master_translator:uav_waitrequest
wire [31:0] cpu_instruction_master_translator_avalon_universal_master_0_readdata; // cpu_instruction_master_agent:av_readdata -> cpu_instruction_master_translator:uav_readdata
wire cpu_instruction_master_translator_avalon_universal_master_0_debugaccess; // cpu_instruction_master_translator:uav_debugaccess -> cpu_instruction_master_agent:av_debugaccess
wire [24:0] cpu_instruction_master_translator_avalon_universal_master_0_address; // cpu_instruction_master_translator:uav_address -> cpu_instruction_master_agent:av_address
wire cpu_instruction_master_translator_avalon_universal_master_0_read; // cpu_instruction_master_translator:uav_read -> cpu_instruction_master_agent:av_read
wire [3:0] cpu_instruction_master_translator_avalon_universal_master_0_byteenable; // cpu_instruction_master_translator:uav_byteenable -> cpu_instruction_master_agent:av_byteenable
wire cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid; // cpu_instruction_master_agent:av_readdatavalid -> cpu_instruction_master_translator:uav_readdatavalid
wire cpu_instruction_master_translator_avalon_universal_master_0_lock; // cpu_instruction_master_translator:uav_lock -> cpu_instruction_master_agent:av_lock
wire cpu_instruction_master_translator_avalon_universal_master_0_write; // cpu_instruction_master_translator:uav_write -> cpu_instruction_master_agent:av_write
wire [31:0] cpu_instruction_master_translator_avalon_universal_master_0_writedata; // cpu_instruction_master_translator:uav_writedata -> cpu_instruction_master_agent:av_writedata
wire [2:0] cpu_instruction_master_translator_avalon_universal_master_0_burstcount; // cpu_instruction_master_translator:uav_burstcount -> cpu_instruction_master_agent:av_burstcount
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> cpu_instruction_master_agent:rp_valid
wire [100:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> cpu_instruction_master_agent:rp_data
wire rsp_mux_001_src_ready; // cpu_instruction_master_agent:rp_ready -> rsp_mux_001:src_ready
wire [7:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> cpu_instruction_master_agent:rp_channel
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> cpu_instruction_master_agent:rp_startofpacket
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> cpu_instruction_master_agent:rp_endofpacket
wire [31:0] jtag_avalon_jtag_slave_agent_m0_readdata; // jtag_avalon_jtag_slave_translator:uav_readdata -> jtag_avalon_jtag_slave_agent:m0_readdata
wire jtag_avalon_jtag_slave_agent_m0_waitrequest; // jtag_avalon_jtag_slave_translator:uav_waitrequest -> jtag_avalon_jtag_slave_agent:m0_waitrequest
wire jtag_avalon_jtag_slave_agent_m0_debugaccess; // jtag_avalon_jtag_slave_agent:m0_debugaccess -> jtag_avalon_jtag_slave_translator:uav_debugaccess
wire [24:0] jtag_avalon_jtag_slave_agent_m0_address; // jtag_avalon_jtag_slave_agent:m0_address -> jtag_avalon_jtag_slave_translator:uav_address
wire [3:0] jtag_avalon_jtag_slave_agent_m0_byteenable; // jtag_avalon_jtag_slave_agent:m0_byteenable -> jtag_avalon_jtag_slave_translator:uav_byteenable
wire jtag_avalon_jtag_slave_agent_m0_read; // jtag_avalon_jtag_slave_agent:m0_read -> jtag_avalon_jtag_slave_translator:uav_read
wire jtag_avalon_jtag_slave_agent_m0_readdatavalid; // jtag_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_avalon_jtag_slave_agent:m0_readdatavalid
wire jtag_avalon_jtag_slave_agent_m0_lock; // jtag_avalon_jtag_slave_agent:m0_lock -> jtag_avalon_jtag_slave_translator:uav_lock
wire [31:0] jtag_avalon_jtag_slave_agent_m0_writedata; // jtag_avalon_jtag_slave_agent:m0_writedata -> jtag_avalon_jtag_slave_translator:uav_writedata
wire jtag_avalon_jtag_slave_agent_m0_write; // jtag_avalon_jtag_slave_agent:m0_write -> jtag_avalon_jtag_slave_translator:uav_write
wire [2:0] jtag_avalon_jtag_slave_agent_m0_burstcount; // jtag_avalon_jtag_slave_agent:m0_burstcount -> jtag_avalon_jtag_slave_translator:uav_burstcount
wire jtag_avalon_jtag_slave_agent_rf_source_valid; // jtag_avalon_jtag_slave_agent:rf_source_valid -> jtag_avalon_jtag_slave_agent_rsp_fifo:in_valid
wire [101:0] jtag_avalon_jtag_slave_agent_rf_source_data; // jtag_avalon_jtag_slave_agent:rf_source_data -> jtag_avalon_jtag_slave_agent_rsp_fifo:in_data
wire jtag_avalon_jtag_slave_agent_rf_source_ready; // jtag_avalon_jtag_slave_agent_rsp_fifo:in_ready -> jtag_avalon_jtag_slave_agent:rf_source_ready
wire jtag_avalon_jtag_slave_agent_rf_source_startofpacket; // jtag_avalon_jtag_slave_agent:rf_source_startofpacket -> jtag_avalon_jtag_slave_agent_rsp_fifo:in_startofpacket
wire jtag_avalon_jtag_slave_agent_rf_source_endofpacket; // jtag_avalon_jtag_slave_agent:rf_source_endofpacket -> jtag_avalon_jtag_slave_agent_rsp_fifo:in_endofpacket
wire jtag_avalon_jtag_slave_agent_rsp_fifo_out_valid; // jtag_avalon_jtag_slave_agent_rsp_fifo:out_valid -> jtag_avalon_jtag_slave_agent:rf_sink_valid
wire [101:0] jtag_avalon_jtag_slave_agent_rsp_fifo_out_data; // jtag_avalon_jtag_slave_agent_rsp_fifo:out_data -> jtag_avalon_jtag_slave_agent:rf_sink_data
wire jtag_avalon_jtag_slave_agent_rsp_fifo_out_ready; // jtag_avalon_jtag_slave_agent:rf_sink_ready -> jtag_avalon_jtag_slave_agent_rsp_fifo:out_ready
wire jtag_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket; // jtag_avalon_jtag_slave_agent_rsp_fifo:out_startofpacket -> jtag_avalon_jtag_slave_agent:rf_sink_startofpacket
wire jtag_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket; // jtag_avalon_jtag_slave_agent_rsp_fifo:out_endofpacket -> jtag_avalon_jtag_slave_agent:rf_sink_endofpacket
wire jtag_avalon_jtag_slave_agent_rdata_fifo_src_valid; // jtag_avalon_jtag_slave_agent:rdata_fifo_src_valid -> jtag_avalon_jtag_slave_agent_rdata_fifo:in_valid
wire [33:0] jtag_avalon_jtag_slave_agent_rdata_fifo_src_data; // jtag_avalon_jtag_slave_agent:rdata_fifo_src_data -> jtag_avalon_jtag_slave_agent_rdata_fifo:in_data
wire jtag_avalon_jtag_slave_agent_rdata_fifo_src_ready; // jtag_avalon_jtag_slave_agent_rdata_fifo:in_ready -> jtag_avalon_jtag_slave_agent:rdata_fifo_src_ready
wire jtag_avalon_jtag_slave_agent_rdata_fifo_out_valid; // jtag_avalon_jtag_slave_agent_rdata_fifo:out_valid -> jtag_avalon_jtag_slave_agent:rdata_fifo_sink_valid
wire [33:0] jtag_avalon_jtag_slave_agent_rdata_fifo_out_data; // jtag_avalon_jtag_slave_agent_rdata_fifo:out_data -> jtag_avalon_jtag_slave_agent:rdata_fifo_sink_data
wire jtag_avalon_jtag_slave_agent_rdata_fifo_out_ready; // jtag_avalon_jtag_slave_agent:rdata_fifo_sink_ready -> jtag_avalon_jtag_slave_agent_rdata_fifo:out_ready
wire cmd_mux_src_valid; // cmd_mux:src_valid -> jtag_avalon_jtag_slave_agent:cp_valid
wire [100:0] cmd_mux_src_data; // cmd_mux:src_data -> jtag_avalon_jtag_slave_agent:cp_data
wire cmd_mux_src_ready; // jtag_avalon_jtag_slave_agent:cp_ready -> cmd_mux:src_ready
wire [7:0] cmd_mux_src_channel; // cmd_mux:src_channel -> jtag_avalon_jtag_slave_agent:cp_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> jtag_avalon_jtag_slave_agent:cp_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> jtag_avalon_jtag_slave_agent:cp_endofpacket
wire [31:0] sysid_control_slave_agent_m0_readdata; // sysid_control_slave_translator:uav_readdata -> sysid_control_slave_agent:m0_readdata
wire sysid_control_slave_agent_m0_waitrequest; // sysid_control_slave_translator:uav_waitrequest -> sysid_control_slave_agent:m0_waitrequest
wire sysid_control_slave_agent_m0_debugaccess; // sysid_control_slave_agent:m0_debugaccess -> sysid_control_slave_translator:uav_debugaccess
wire [24:0] sysid_control_slave_agent_m0_address; // sysid_control_slave_agent:m0_address -> sysid_control_slave_translator:uav_address
wire [3:0] sysid_control_slave_agent_m0_byteenable; // sysid_control_slave_agent:m0_byteenable -> sysid_control_slave_translator:uav_byteenable
wire sysid_control_slave_agent_m0_read; // sysid_control_slave_agent:m0_read -> sysid_control_slave_translator:uav_read
wire sysid_control_slave_agent_m0_readdatavalid; // sysid_control_slave_translator:uav_readdatavalid -> sysid_control_slave_agent:m0_readdatavalid
wire sysid_control_slave_agent_m0_lock; // sysid_control_slave_agent:m0_lock -> sysid_control_slave_translator:uav_lock
wire [31:0] sysid_control_slave_agent_m0_writedata; // sysid_control_slave_agent:m0_writedata -> sysid_control_slave_translator:uav_writedata
wire sysid_control_slave_agent_m0_write; // sysid_control_slave_agent:m0_write -> sysid_control_slave_translator:uav_write
wire [2:0] sysid_control_slave_agent_m0_burstcount; // sysid_control_slave_agent:m0_burstcount -> sysid_control_slave_translator:uav_burstcount
wire sysid_control_slave_agent_rf_source_valid; // sysid_control_slave_agent:rf_source_valid -> sysid_control_slave_agent_rsp_fifo:in_valid
wire [101:0] sysid_control_slave_agent_rf_source_data; // sysid_control_slave_agent:rf_source_data -> sysid_control_slave_agent_rsp_fifo:in_data
wire sysid_control_slave_agent_rf_source_ready; // sysid_control_slave_agent_rsp_fifo:in_ready -> sysid_control_slave_agent:rf_source_ready
wire sysid_control_slave_agent_rf_source_startofpacket; // sysid_control_slave_agent:rf_source_startofpacket -> sysid_control_slave_agent_rsp_fifo:in_startofpacket
wire sysid_control_slave_agent_rf_source_endofpacket; // sysid_control_slave_agent:rf_source_endofpacket -> sysid_control_slave_agent_rsp_fifo:in_endofpacket
wire sysid_control_slave_agent_rsp_fifo_out_valid; // sysid_control_slave_agent_rsp_fifo:out_valid -> sysid_control_slave_agent:rf_sink_valid
wire [101:0] sysid_control_slave_agent_rsp_fifo_out_data; // sysid_control_slave_agent_rsp_fifo:out_data -> sysid_control_slave_agent:rf_sink_data
wire sysid_control_slave_agent_rsp_fifo_out_ready; // sysid_control_slave_agent:rf_sink_ready -> sysid_control_slave_agent_rsp_fifo:out_ready
wire sysid_control_slave_agent_rsp_fifo_out_startofpacket; // sysid_control_slave_agent_rsp_fifo:out_startofpacket -> sysid_control_slave_agent:rf_sink_startofpacket
wire sysid_control_slave_agent_rsp_fifo_out_endofpacket; // sysid_control_slave_agent_rsp_fifo:out_endofpacket -> sysid_control_slave_agent:rf_sink_endofpacket
wire sysid_control_slave_agent_rdata_fifo_src_valid; // sysid_control_slave_agent:rdata_fifo_src_valid -> sysid_control_slave_agent:rdata_fifo_sink_valid
wire [33:0] sysid_control_slave_agent_rdata_fifo_src_data; // sysid_control_slave_agent:rdata_fifo_src_data -> sysid_control_slave_agent:rdata_fifo_sink_data
wire sysid_control_slave_agent_rdata_fifo_src_ready; // sysid_control_slave_agent:rdata_fifo_sink_ready -> sysid_control_slave_agent:rdata_fifo_src_ready
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> sysid_control_slave_agent:cp_valid
wire [100:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> sysid_control_slave_agent:cp_data
wire cmd_mux_001_src_ready; // sysid_control_slave_agent:cp_ready -> cmd_mux_001:src_ready
wire [7:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> sysid_control_slave_agent:cp_channel
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> sysid_control_slave_agent:cp_startofpacket
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> sysid_control_slave_agent:cp_endofpacket
wire [31:0] flash_epcs_control_port_agent_m0_readdata; // flash_epcs_control_port_translator:uav_readdata -> flash_epcs_control_port_agent:m0_readdata
wire flash_epcs_control_port_agent_m0_waitrequest; // flash_epcs_control_port_translator:uav_waitrequest -> flash_epcs_control_port_agent:m0_waitrequest
wire flash_epcs_control_port_agent_m0_debugaccess; // flash_epcs_control_port_agent:m0_debugaccess -> flash_epcs_control_port_translator:uav_debugaccess
wire [24:0] flash_epcs_control_port_agent_m0_address; // flash_epcs_control_port_agent:m0_address -> flash_epcs_control_port_translator:uav_address
wire [3:0] flash_epcs_control_port_agent_m0_byteenable; // flash_epcs_control_port_agent:m0_byteenable -> flash_epcs_control_port_translator:uav_byteenable
wire flash_epcs_control_port_agent_m0_read; // flash_epcs_control_port_agent:m0_read -> flash_epcs_control_port_translator:uav_read
wire flash_epcs_control_port_agent_m0_readdatavalid; // flash_epcs_control_port_translator:uav_readdatavalid -> flash_epcs_control_port_agent:m0_readdatavalid
wire flash_epcs_control_port_agent_m0_lock; // flash_epcs_control_port_agent:m0_lock -> flash_epcs_control_port_translator:uav_lock
wire [31:0] flash_epcs_control_port_agent_m0_writedata; // flash_epcs_control_port_agent:m0_writedata -> flash_epcs_control_port_translator:uav_writedata
wire flash_epcs_control_port_agent_m0_write; // flash_epcs_control_port_agent:m0_write -> flash_epcs_control_port_translator:uav_write
wire [2:0] flash_epcs_control_port_agent_m0_burstcount; // flash_epcs_control_port_agent:m0_burstcount -> flash_epcs_control_port_translator:uav_burstcount
wire flash_epcs_control_port_agent_rf_source_valid; // flash_epcs_control_port_agent:rf_source_valid -> flash_epcs_control_port_agent_rsp_fifo:in_valid
wire [101:0] flash_epcs_control_port_agent_rf_source_data; // flash_epcs_control_port_agent:rf_source_data -> flash_epcs_control_port_agent_rsp_fifo:in_data
wire flash_epcs_control_port_agent_rf_source_ready; // flash_epcs_control_port_agent_rsp_fifo:in_ready -> flash_epcs_control_port_agent:rf_source_ready
wire flash_epcs_control_port_agent_rf_source_startofpacket; // flash_epcs_control_port_agent:rf_source_startofpacket -> flash_epcs_control_port_agent_rsp_fifo:in_startofpacket
wire flash_epcs_control_port_agent_rf_source_endofpacket; // flash_epcs_control_port_agent:rf_source_endofpacket -> flash_epcs_control_port_agent_rsp_fifo:in_endofpacket
wire flash_epcs_control_port_agent_rsp_fifo_out_valid; // flash_epcs_control_port_agent_rsp_fifo:out_valid -> flash_epcs_control_port_agent:rf_sink_valid
wire [101:0] flash_epcs_control_port_agent_rsp_fifo_out_data; // flash_epcs_control_port_agent_rsp_fifo:out_data -> flash_epcs_control_port_agent:rf_sink_data
wire flash_epcs_control_port_agent_rsp_fifo_out_ready; // flash_epcs_control_port_agent:rf_sink_ready -> flash_epcs_control_port_agent_rsp_fifo:out_ready
wire flash_epcs_control_port_agent_rsp_fifo_out_startofpacket; // flash_epcs_control_port_agent_rsp_fifo:out_startofpacket -> flash_epcs_control_port_agent:rf_sink_startofpacket
wire flash_epcs_control_port_agent_rsp_fifo_out_endofpacket; // flash_epcs_control_port_agent_rsp_fifo:out_endofpacket -> flash_epcs_control_port_agent:rf_sink_endofpacket
wire flash_epcs_control_port_agent_rdata_fifo_src_valid; // flash_epcs_control_port_agent:rdata_fifo_src_valid -> flash_epcs_control_port_agent:rdata_fifo_sink_valid
wire [33:0] flash_epcs_control_port_agent_rdata_fifo_src_data; // flash_epcs_control_port_agent:rdata_fifo_src_data -> flash_epcs_control_port_agent:rdata_fifo_sink_data
wire flash_epcs_control_port_agent_rdata_fifo_src_ready; // flash_epcs_control_port_agent:rdata_fifo_sink_ready -> flash_epcs_control_port_agent:rdata_fifo_src_ready
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> flash_epcs_control_port_agent:cp_valid
wire [100:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> flash_epcs_control_port_agent:cp_data
wire cmd_mux_002_src_ready; // flash_epcs_control_port_agent:cp_ready -> cmd_mux_002:src_ready
wire [7:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> flash_epcs_control_port_agent:cp_channel
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> flash_epcs_control_port_agent:cp_startofpacket
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> flash_epcs_control_port_agent:cp_endofpacket
wire [31:0] cpu_jtag_debug_module_agent_m0_readdata; // cpu_jtag_debug_module_translator:uav_readdata -> cpu_jtag_debug_module_agent:m0_readdata
wire cpu_jtag_debug_module_agent_m0_waitrequest; // cpu_jtag_debug_module_translator:uav_waitrequest -> cpu_jtag_debug_module_agent:m0_waitrequest
wire cpu_jtag_debug_module_agent_m0_debugaccess; // cpu_jtag_debug_module_agent:m0_debugaccess -> cpu_jtag_debug_module_translator:uav_debugaccess
wire [24:0] cpu_jtag_debug_module_agent_m0_address; // cpu_jtag_debug_module_agent:m0_address -> cpu_jtag_debug_module_translator:uav_address
wire [3:0] cpu_jtag_debug_module_agent_m0_byteenable; // cpu_jtag_debug_module_agent:m0_byteenable -> cpu_jtag_debug_module_translator:uav_byteenable
wire cpu_jtag_debug_module_agent_m0_read; // cpu_jtag_debug_module_agent:m0_read -> cpu_jtag_debug_module_translator:uav_read
wire cpu_jtag_debug_module_agent_m0_readdatavalid; // cpu_jtag_debug_module_translator:uav_readdatavalid -> cpu_jtag_debug_module_agent:m0_readdatavalid
wire cpu_jtag_debug_module_agent_m0_lock; // cpu_jtag_debug_module_agent:m0_lock -> cpu_jtag_debug_module_translator:uav_lock
wire [31:0] cpu_jtag_debug_module_agent_m0_writedata; // cpu_jtag_debug_module_agent:m0_writedata -> cpu_jtag_debug_module_translator:uav_writedata
wire cpu_jtag_debug_module_agent_m0_write; // cpu_jtag_debug_module_agent:m0_write -> cpu_jtag_debug_module_translator:uav_write
wire [2:0] cpu_jtag_debug_module_agent_m0_burstcount; // cpu_jtag_debug_module_agent:m0_burstcount -> cpu_jtag_debug_module_translator:uav_burstcount
wire cpu_jtag_debug_module_agent_rf_source_valid; // cpu_jtag_debug_module_agent:rf_source_valid -> cpu_jtag_debug_module_agent_rsp_fifo:in_valid
wire [101:0] cpu_jtag_debug_module_agent_rf_source_data; // cpu_jtag_debug_module_agent:rf_source_data -> cpu_jtag_debug_module_agent_rsp_fifo:in_data
wire cpu_jtag_debug_module_agent_rf_source_ready; // cpu_jtag_debug_module_agent_rsp_fifo:in_ready -> cpu_jtag_debug_module_agent:rf_source_ready
wire cpu_jtag_debug_module_agent_rf_source_startofpacket; // cpu_jtag_debug_module_agent:rf_source_startofpacket -> cpu_jtag_debug_module_agent_rsp_fifo:in_startofpacket
wire cpu_jtag_debug_module_agent_rf_source_endofpacket; // cpu_jtag_debug_module_agent:rf_source_endofpacket -> cpu_jtag_debug_module_agent_rsp_fifo:in_endofpacket
wire cpu_jtag_debug_module_agent_rsp_fifo_out_valid; // cpu_jtag_debug_module_agent_rsp_fifo:out_valid -> cpu_jtag_debug_module_agent:rf_sink_valid
wire [101:0] cpu_jtag_debug_module_agent_rsp_fifo_out_data; // cpu_jtag_debug_module_agent_rsp_fifo:out_data -> cpu_jtag_debug_module_agent:rf_sink_data
wire cpu_jtag_debug_module_agent_rsp_fifo_out_ready; // cpu_jtag_debug_module_agent:rf_sink_ready -> cpu_jtag_debug_module_agent_rsp_fifo:out_ready
wire cpu_jtag_debug_module_agent_rsp_fifo_out_startofpacket; // cpu_jtag_debug_module_agent_rsp_fifo:out_startofpacket -> cpu_jtag_debug_module_agent:rf_sink_startofpacket
wire cpu_jtag_debug_module_agent_rsp_fifo_out_endofpacket; // cpu_jtag_debug_module_agent_rsp_fifo:out_endofpacket -> cpu_jtag_debug_module_agent:rf_sink_endofpacket
wire cpu_jtag_debug_module_agent_rdata_fifo_src_valid; // cpu_jtag_debug_module_agent:rdata_fifo_src_valid -> cpu_jtag_debug_module_agent:rdata_fifo_sink_valid
wire [33:0] cpu_jtag_debug_module_agent_rdata_fifo_src_data; // cpu_jtag_debug_module_agent:rdata_fifo_src_data -> cpu_jtag_debug_module_agent:rdata_fifo_sink_data
wire cpu_jtag_debug_module_agent_rdata_fifo_src_ready; // cpu_jtag_debug_module_agent:rdata_fifo_sink_ready -> cpu_jtag_debug_module_agent:rdata_fifo_src_ready
wire cmd_mux_003_src_valid; // cmd_mux_003:src_valid -> cpu_jtag_debug_module_agent:cp_valid
wire [100:0] cmd_mux_003_src_data; // cmd_mux_003:src_data -> cpu_jtag_debug_module_agent:cp_data
wire cmd_mux_003_src_ready; // cpu_jtag_debug_module_agent:cp_ready -> cmd_mux_003:src_ready
wire [7:0] cmd_mux_003_src_channel; // cmd_mux_003:src_channel -> cpu_jtag_debug_module_agent:cp_channel
wire cmd_mux_003_src_startofpacket; // cmd_mux_003:src_startofpacket -> cpu_jtag_debug_module_agent:cp_startofpacket
wire cmd_mux_003_src_endofpacket; // cmd_mux_003:src_endofpacket -> cpu_jtag_debug_module_agent:cp_endofpacket
wire [31:0] timer_s1_agent_m0_readdata; // timer_s1_translator:uav_readdata -> timer_s1_agent:m0_readdata
wire timer_s1_agent_m0_waitrequest; // timer_s1_translator:uav_waitrequest -> timer_s1_agent:m0_waitrequest
wire timer_s1_agent_m0_debugaccess; // timer_s1_agent:m0_debugaccess -> timer_s1_translator:uav_debugaccess
wire [24:0] timer_s1_agent_m0_address; // timer_s1_agent:m0_address -> timer_s1_translator:uav_address
wire [3:0] timer_s1_agent_m0_byteenable; // timer_s1_agent:m0_byteenable -> timer_s1_translator:uav_byteenable
wire timer_s1_agent_m0_read; // timer_s1_agent:m0_read -> timer_s1_translator:uav_read
wire timer_s1_agent_m0_readdatavalid; // timer_s1_translator:uav_readdatavalid -> timer_s1_agent:m0_readdatavalid
wire timer_s1_agent_m0_lock; // timer_s1_agent:m0_lock -> timer_s1_translator:uav_lock
wire [31:0] timer_s1_agent_m0_writedata; // timer_s1_agent:m0_writedata -> timer_s1_translator:uav_writedata
wire timer_s1_agent_m0_write; // timer_s1_agent:m0_write -> timer_s1_translator:uav_write
wire [2:0] timer_s1_agent_m0_burstcount; // timer_s1_agent:m0_burstcount -> timer_s1_translator:uav_burstcount
wire timer_s1_agent_rf_source_valid; // timer_s1_agent:rf_source_valid -> timer_s1_agent_rsp_fifo:in_valid
wire [101:0] timer_s1_agent_rf_source_data; // timer_s1_agent:rf_source_data -> timer_s1_agent_rsp_fifo:in_data
wire timer_s1_agent_rf_source_ready; // timer_s1_agent_rsp_fifo:in_ready -> timer_s1_agent:rf_source_ready
wire timer_s1_agent_rf_source_startofpacket; // timer_s1_agent:rf_source_startofpacket -> timer_s1_agent_rsp_fifo:in_startofpacket
wire timer_s1_agent_rf_source_endofpacket; // timer_s1_agent:rf_source_endofpacket -> timer_s1_agent_rsp_fifo:in_endofpacket
wire timer_s1_agent_rsp_fifo_out_valid; // timer_s1_agent_rsp_fifo:out_valid -> timer_s1_agent:rf_sink_valid
wire [101:0] timer_s1_agent_rsp_fifo_out_data; // timer_s1_agent_rsp_fifo:out_data -> timer_s1_agent:rf_sink_data
wire timer_s1_agent_rsp_fifo_out_ready; // timer_s1_agent:rf_sink_ready -> timer_s1_agent_rsp_fifo:out_ready
wire timer_s1_agent_rsp_fifo_out_startofpacket; // timer_s1_agent_rsp_fifo:out_startofpacket -> timer_s1_agent:rf_sink_startofpacket
wire timer_s1_agent_rsp_fifo_out_endofpacket; // timer_s1_agent_rsp_fifo:out_endofpacket -> timer_s1_agent:rf_sink_endofpacket
wire timer_s1_agent_rdata_fifo_src_valid; // timer_s1_agent:rdata_fifo_src_valid -> timer_s1_agent_rdata_fifo:in_valid
wire [33:0] timer_s1_agent_rdata_fifo_src_data; // timer_s1_agent:rdata_fifo_src_data -> timer_s1_agent_rdata_fifo:in_data
wire timer_s1_agent_rdata_fifo_src_ready; // timer_s1_agent_rdata_fifo:in_ready -> timer_s1_agent:rdata_fifo_src_ready
wire timer_s1_agent_rdata_fifo_out_valid; // timer_s1_agent_rdata_fifo:out_valid -> timer_s1_agent:rdata_fifo_sink_valid
wire [33:0] timer_s1_agent_rdata_fifo_out_data; // timer_s1_agent_rdata_fifo:out_data -> timer_s1_agent:rdata_fifo_sink_data
wire timer_s1_agent_rdata_fifo_out_ready; // timer_s1_agent:rdata_fifo_sink_ready -> timer_s1_agent_rdata_fifo:out_ready
wire cmd_mux_004_src_valid; // cmd_mux_004:src_valid -> timer_s1_agent:cp_valid
wire [100:0] cmd_mux_004_src_data; // cmd_mux_004:src_data -> timer_s1_agent:cp_data
wire cmd_mux_004_src_ready; // timer_s1_agent:cp_ready -> cmd_mux_004:src_ready
wire [7:0] cmd_mux_004_src_channel; // cmd_mux_004:src_channel -> timer_s1_agent:cp_channel
wire cmd_mux_004_src_startofpacket; // cmd_mux_004:src_startofpacket -> timer_s1_agent:cp_startofpacket
wire cmd_mux_004_src_endofpacket; // cmd_mux_004:src_endofpacket -> timer_s1_agent:cp_endofpacket
wire [31:0] sw_s1_agent_m0_readdata; // SW_s1_translator:uav_readdata -> SW_s1_agent:m0_readdata
wire sw_s1_agent_m0_waitrequest; // SW_s1_translator:uav_waitrequest -> SW_s1_agent:m0_waitrequest
wire sw_s1_agent_m0_debugaccess; // SW_s1_agent:m0_debugaccess -> SW_s1_translator:uav_debugaccess
wire [24:0] sw_s1_agent_m0_address; // SW_s1_agent:m0_address -> SW_s1_translator:uav_address
wire [3:0] sw_s1_agent_m0_byteenable; // SW_s1_agent:m0_byteenable -> SW_s1_translator:uav_byteenable
wire sw_s1_agent_m0_read; // SW_s1_agent:m0_read -> SW_s1_translator:uav_read
wire sw_s1_agent_m0_readdatavalid; // SW_s1_translator:uav_readdatavalid -> SW_s1_agent:m0_readdatavalid
wire sw_s1_agent_m0_lock; // SW_s1_agent:m0_lock -> SW_s1_translator:uav_lock
wire [31:0] sw_s1_agent_m0_writedata; // SW_s1_agent:m0_writedata -> SW_s1_translator:uav_writedata
wire sw_s1_agent_m0_write; // SW_s1_agent:m0_write -> SW_s1_translator:uav_write
wire [2:0] sw_s1_agent_m0_burstcount; // SW_s1_agent:m0_burstcount -> SW_s1_translator:uav_burstcount
wire sw_s1_agent_rf_source_valid; // SW_s1_agent:rf_source_valid -> SW_s1_agent_rsp_fifo:in_valid
wire [101:0] sw_s1_agent_rf_source_data; // SW_s1_agent:rf_source_data -> SW_s1_agent_rsp_fifo:in_data
wire sw_s1_agent_rf_source_ready; // SW_s1_agent_rsp_fifo:in_ready -> SW_s1_agent:rf_source_ready
wire sw_s1_agent_rf_source_startofpacket; // SW_s1_agent:rf_source_startofpacket -> SW_s1_agent_rsp_fifo:in_startofpacket
wire sw_s1_agent_rf_source_endofpacket; // SW_s1_agent:rf_source_endofpacket -> SW_s1_agent_rsp_fifo:in_endofpacket
wire sw_s1_agent_rsp_fifo_out_valid; // SW_s1_agent_rsp_fifo:out_valid -> SW_s1_agent:rf_sink_valid
wire [101:0] sw_s1_agent_rsp_fifo_out_data; // SW_s1_agent_rsp_fifo:out_data -> SW_s1_agent:rf_sink_data
wire sw_s1_agent_rsp_fifo_out_ready; // SW_s1_agent:rf_sink_ready -> SW_s1_agent_rsp_fifo:out_ready
wire sw_s1_agent_rsp_fifo_out_startofpacket; // SW_s1_agent_rsp_fifo:out_startofpacket -> SW_s1_agent:rf_sink_startofpacket
wire sw_s1_agent_rsp_fifo_out_endofpacket; // SW_s1_agent_rsp_fifo:out_endofpacket -> SW_s1_agent:rf_sink_endofpacket
wire sw_s1_agent_rdata_fifo_src_valid; // SW_s1_agent:rdata_fifo_src_valid -> SW_s1_agent_rdata_fifo:in_valid
wire [33:0] sw_s1_agent_rdata_fifo_src_data; // SW_s1_agent:rdata_fifo_src_data -> SW_s1_agent_rdata_fifo:in_data
wire sw_s1_agent_rdata_fifo_src_ready; // SW_s1_agent_rdata_fifo:in_ready -> SW_s1_agent:rdata_fifo_src_ready
wire sw_s1_agent_rdata_fifo_out_valid; // SW_s1_agent_rdata_fifo:out_valid -> SW_s1_agent:rdata_fifo_sink_valid
wire [33:0] sw_s1_agent_rdata_fifo_out_data; // SW_s1_agent_rdata_fifo:out_data -> SW_s1_agent:rdata_fifo_sink_data
wire sw_s1_agent_rdata_fifo_out_ready; // SW_s1_agent:rdata_fifo_sink_ready -> SW_s1_agent_rdata_fifo:out_ready
wire cmd_mux_005_src_valid; // cmd_mux_005:src_valid -> SW_s1_agent:cp_valid
wire [100:0] cmd_mux_005_src_data; // cmd_mux_005:src_data -> SW_s1_agent:cp_data
wire cmd_mux_005_src_ready; // SW_s1_agent:cp_ready -> cmd_mux_005:src_ready
wire [7:0] cmd_mux_005_src_channel; // cmd_mux_005:src_channel -> SW_s1_agent:cp_channel
wire cmd_mux_005_src_startofpacket; // cmd_mux_005:src_startofpacket -> SW_s1_agent:cp_startofpacket
wire cmd_mux_005_src_endofpacket; // cmd_mux_005:src_endofpacket -> SW_s1_agent:cp_endofpacket
wire [31:0] led_s1_agent_m0_readdata; // LED_s1_translator:uav_readdata -> LED_s1_agent:m0_readdata
wire led_s1_agent_m0_waitrequest; // LED_s1_translator:uav_waitrequest -> LED_s1_agent:m0_waitrequest
wire led_s1_agent_m0_debugaccess; // LED_s1_agent:m0_debugaccess -> LED_s1_translator:uav_debugaccess
wire [24:0] led_s1_agent_m0_address; // LED_s1_agent:m0_address -> LED_s1_translator:uav_address
wire [3:0] led_s1_agent_m0_byteenable; // LED_s1_agent:m0_byteenable -> LED_s1_translator:uav_byteenable
wire led_s1_agent_m0_read; // LED_s1_agent:m0_read -> LED_s1_translator:uav_read
wire led_s1_agent_m0_readdatavalid; // LED_s1_translator:uav_readdatavalid -> LED_s1_agent:m0_readdatavalid
wire led_s1_agent_m0_lock; // LED_s1_agent:m0_lock -> LED_s1_translator:uav_lock
wire [31:0] led_s1_agent_m0_writedata; // LED_s1_agent:m0_writedata -> LED_s1_translator:uav_writedata
wire led_s1_agent_m0_write; // LED_s1_agent:m0_write -> LED_s1_translator:uav_write
wire [2:0] led_s1_agent_m0_burstcount; // LED_s1_agent:m0_burstcount -> LED_s1_translator:uav_burstcount
wire led_s1_agent_rf_source_valid; // LED_s1_agent:rf_source_valid -> LED_s1_agent_rsp_fifo:in_valid
wire [101:0] led_s1_agent_rf_source_data; // LED_s1_agent:rf_source_data -> LED_s1_agent_rsp_fifo:in_data
wire led_s1_agent_rf_source_ready; // LED_s1_agent_rsp_fifo:in_ready -> LED_s1_agent:rf_source_ready
wire led_s1_agent_rf_source_startofpacket; // LED_s1_agent:rf_source_startofpacket -> LED_s1_agent_rsp_fifo:in_startofpacket
wire led_s1_agent_rf_source_endofpacket; // LED_s1_agent:rf_source_endofpacket -> LED_s1_agent_rsp_fifo:in_endofpacket
wire led_s1_agent_rsp_fifo_out_valid; // LED_s1_agent_rsp_fifo:out_valid -> LED_s1_agent:rf_sink_valid
wire [101:0] led_s1_agent_rsp_fifo_out_data; // LED_s1_agent_rsp_fifo:out_data -> LED_s1_agent:rf_sink_data
wire led_s1_agent_rsp_fifo_out_ready; // LED_s1_agent:rf_sink_ready -> LED_s1_agent_rsp_fifo:out_ready
wire led_s1_agent_rsp_fifo_out_startofpacket; // LED_s1_agent_rsp_fifo:out_startofpacket -> LED_s1_agent:rf_sink_startofpacket
wire led_s1_agent_rsp_fifo_out_endofpacket; // LED_s1_agent_rsp_fifo:out_endofpacket -> LED_s1_agent:rf_sink_endofpacket
wire led_s1_agent_rdata_fifo_src_valid; // LED_s1_agent:rdata_fifo_src_valid -> LED_s1_agent_rdata_fifo:in_valid
wire [33:0] led_s1_agent_rdata_fifo_src_data; // LED_s1_agent:rdata_fifo_src_data -> LED_s1_agent_rdata_fifo:in_data
wire led_s1_agent_rdata_fifo_src_ready; // LED_s1_agent_rdata_fifo:in_ready -> LED_s1_agent:rdata_fifo_src_ready
wire led_s1_agent_rdata_fifo_out_valid; // LED_s1_agent_rdata_fifo:out_valid -> LED_s1_agent:rdata_fifo_sink_valid
wire [33:0] led_s1_agent_rdata_fifo_out_data; // LED_s1_agent_rdata_fifo:out_data -> LED_s1_agent:rdata_fifo_sink_data
wire led_s1_agent_rdata_fifo_out_ready; // LED_s1_agent:rdata_fifo_sink_ready -> LED_s1_agent_rdata_fifo:out_ready
wire cmd_mux_006_src_valid; // cmd_mux_006:src_valid -> LED_s1_agent:cp_valid
wire [100:0] cmd_mux_006_src_data; // cmd_mux_006:src_data -> LED_s1_agent:cp_data
wire cmd_mux_006_src_ready; // LED_s1_agent:cp_ready -> cmd_mux_006:src_ready
wire [7:0] cmd_mux_006_src_channel; // cmd_mux_006:src_channel -> LED_s1_agent:cp_channel
wire cmd_mux_006_src_startofpacket; // cmd_mux_006:src_startofpacket -> LED_s1_agent:cp_startofpacket
wire cmd_mux_006_src_endofpacket; // cmd_mux_006:src_endofpacket -> LED_s1_agent:cp_endofpacket
wire [15:0] sdram_s1_agent_m0_readdata; // sdram_s1_translator:uav_readdata -> sdram_s1_agent:m0_readdata
wire sdram_s1_agent_m0_waitrequest; // sdram_s1_translator:uav_waitrequest -> sdram_s1_agent:m0_waitrequest
wire sdram_s1_agent_m0_debugaccess; // sdram_s1_agent:m0_debugaccess -> sdram_s1_translator:uav_debugaccess
wire [24:0] sdram_s1_agent_m0_address; // sdram_s1_agent:m0_address -> sdram_s1_translator:uav_address
wire [1:0] sdram_s1_agent_m0_byteenable; // sdram_s1_agent:m0_byteenable -> sdram_s1_translator:uav_byteenable
wire sdram_s1_agent_m0_read; // sdram_s1_agent:m0_read -> sdram_s1_translator:uav_read
wire sdram_s1_agent_m0_readdatavalid; // sdram_s1_translator:uav_readdatavalid -> sdram_s1_agent:m0_readdatavalid
wire sdram_s1_agent_m0_lock; // sdram_s1_agent:m0_lock -> sdram_s1_translator:uav_lock
wire [15:0] sdram_s1_agent_m0_writedata; // sdram_s1_agent:m0_writedata -> sdram_s1_translator:uav_writedata
wire sdram_s1_agent_m0_write; // sdram_s1_agent:m0_write -> sdram_s1_translator:uav_write
wire [1:0] sdram_s1_agent_m0_burstcount; // sdram_s1_agent:m0_burstcount -> sdram_s1_translator:uav_burstcount
wire sdram_s1_agent_rf_source_valid; // sdram_s1_agent:rf_source_valid -> sdram_s1_agent_rsp_fifo:in_valid
wire [83:0] sdram_s1_agent_rf_source_data; // sdram_s1_agent:rf_source_data -> sdram_s1_agent_rsp_fifo:in_data
wire sdram_s1_agent_rf_source_ready; // sdram_s1_agent_rsp_fifo:in_ready -> sdram_s1_agent:rf_source_ready
wire sdram_s1_agent_rf_source_startofpacket; // sdram_s1_agent:rf_source_startofpacket -> sdram_s1_agent_rsp_fifo:in_startofpacket
wire sdram_s1_agent_rf_source_endofpacket; // sdram_s1_agent:rf_source_endofpacket -> sdram_s1_agent_rsp_fifo:in_endofpacket
wire sdram_s1_agent_rsp_fifo_out_valid; // sdram_s1_agent_rsp_fifo:out_valid -> sdram_s1_agent:rf_sink_valid
wire [83:0] sdram_s1_agent_rsp_fifo_out_data; // sdram_s1_agent_rsp_fifo:out_data -> sdram_s1_agent:rf_sink_data
wire sdram_s1_agent_rsp_fifo_out_ready; // sdram_s1_agent:rf_sink_ready -> sdram_s1_agent_rsp_fifo:out_ready
wire sdram_s1_agent_rsp_fifo_out_startofpacket; // sdram_s1_agent_rsp_fifo:out_startofpacket -> sdram_s1_agent:rf_sink_startofpacket
wire sdram_s1_agent_rsp_fifo_out_endofpacket; // sdram_s1_agent_rsp_fifo:out_endofpacket -> sdram_s1_agent:rf_sink_endofpacket
wire sdram_s1_agent_rdata_fifo_src_valid; // sdram_s1_agent:rdata_fifo_src_valid -> sdram_s1_agent_rdata_fifo:in_valid
wire [17:0] sdram_s1_agent_rdata_fifo_src_data; // sdram_s1_agent:rdata_fifo_src_data -> sdram_s1_agent_rdata_fifo:in_data
wire sdram_s1_agent_rdata_fifo_src_ready; // sdram_s1_agent_rdata_fifo:in_ready -> sdram_s1_agent:rdata_fifo_src_ready
wire sdram_s1_agent_rdata_fifo_out_valid; // sdram_s1_agent_rdata_fifo:out_valid -> sdram_s1_agent:rdata_fifo_sink_valid
wire [17:0] sdram_s1_agent_rdata_fifo_out_data; // sdram_s1_agent_rdata_fifo:out_data -> sdram_s1_agent:rdata_fifo_sink_data
wire sdram_s1_agent_rdata_fifo_out_ready; // sdram_s1_agent:rdata_fifo_sink_ready -> sdram_s1_agent_rdata_fifo:out_ready
wire cpu_data_master_agent_cp_valid; // cpu_data_master_agent:cp_valid -> router:sink_valid
wire [100:0] cpu_data_master_agent_cp_data; // cpu_data_master_agent:cp_data -> router:sink_data
wire cpu_data_master_agent_cp_ready; // router:sink_ready -> cpu_data_master_agent:cp_ready
wire cpu_data_master_agent_cp_startofpacket; // cpu_data_master_agent:cp_startofpacket -> router:sink_startofpacket
wire cpu_data_master_agent_cp_endofpacket; // cpu_data_master_agent:cp_endofpacket -> router:sink_endofpacket
wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
wire [100:0] router_src_data; // router:src_data -> cmd_demux:sink_data
wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
wire [7:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
wire cpu_instruction_master_agent_cp_valid; // cpu_instruction_master_agent:cp_valid -> router_001:sink_valid
wire [100:0] cpu_instruction_master_agent_cp_data; // cpu_instruction_master_agent:cp_data -> router_001:sink_data
wire cpu_instruction_master_agent_cp_ready; // router_001:sink_ready -> cpu_instruction_master_agent:cp_ready
wire cpu_instruction_master_agent_cp_startofpacket; // cpu_instruction_master_agent:cp_startofpacket -> router_001:sink_startofpacket
wire cpu_instruction_master_agent_cp_endofpacket; // cpu_instruction_master_agent:cp_endofpacket -> router_001:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> cmd_demux_001:sink_valid
wire [100:0] router_001_src_data; // router_001:src_data -> cmd_demux_001:sink_data
wire router_001_src_ready; // cmd_demux_001:sink_ready -> router_001:src_ready
wire [7:0] router_001_src_channel; // router_001:src_channel -> cmd_demux_001:sink_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
wire jtag_avalon_jtag_slave_agent_rp_valid; // jtag_avalon_jtag_slave_agent:rp_valid -> router_002:sink_valid
wire [100:0] jtag_avalon_jtag_slave_agent_rp_data; // jtag_avalon_jtag_slave_agent:rp_data -> router_002:sink_data
wire jtag_avalon_jtag_slave_agent_rp_ready; // router_002:sink_ready -> jtag_avalon_jtag_slave_agent:rp_ready
wire jtag_avalon_jtag_slave_agent_rp_startofpacket; // jtag_avalon_jtag_slave_agent:rp_startofpacket -> router_002:sink_startofpacket
wire jtag_avalon_jtag_slave_agent_rp_endofpacket; // jtag_avalon_jtag_slave_agent:rp_endofpacket -> router_002:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> rsp_demux:sink_valid
wire [100:0] router_002_src_data; // router_002:src_data -> rsp_demux:sink_data
wire router_002_src_ready; // rsp_demux:sink_ready -> router_002:src_ready
wire [7:0] router_002_src_channel; // router_002:src_channel -> rsp_demux:sink_channel
wire router_002_src_startofpacket; // router_002:src_startofpacket -> rsp_demux:sink_startofpacket
wire router_002_src_endofpacket; // router_002:src_endofpacket -> rsp_demux:sink_endofpacket
wire sysid_control_slave_agent_rp_valid; // sysid_control_slave_agent:rp_valid -> router_003:sink_valid
wire [100:0] sysid_control_slave_agent_rp_data; // sysid_control_slave_agent:rp_data -> router_003:sink_data
wire sysid_control_slave_agent_rp_ready; // router_003:sink_ready -> sysid_control_slave_agent:rp_ready
wire sysid_control_slave_agent_rp_startofpacket; // sysid_control_slave_agent:rp_startofpacket -> router_003:sink_startofpacket
wire sysid_control_slave_agent_rp_endofpacket; // sysid_control_slave_agent:rp_endofpacket -> router_003:sink_endofpacket
wire router_003_src_valid; // router_003:src_valid -> rsp_demux_001:sink_valid
wire [100:0] router_003_src_data; // router_003:src_data -> rsp_demux_001:sink_data
wire router_003_src_ready; // rsp_demux_001:sink_ready -> router_003:src_ready
wire [7:0] router_003_src_channel; // router_003:src_channel -> rsp_demux_001:sink_channel
wire router_003_src_startofpacket; // router_003:src_startofpacket -> rsp_demux_001:sink_startofpacket
wire router_003_src_endofpacket; // router_003:src_endofpacket -> rsp_demux_001:sink_endofpacket
wire flash_epcs_control_port_agent_rp_valid; // flash_epcs_control_port_agent:rp_valid -> router_004:sink_valid
wire [100:0] flash_epcs_control_port_agent_rp_data; // flash_epcs_control_port_agent:rp_data -> router_004:sink_data
wire flash_epcs_control_port_agent_rp_ready; // router_004:sink_ready -> flash_epcs_control_port_agent:rp_ready
wire flash_epcs_control_port_agent_rp_startofpacket; // flash_epcs_control_port_agent:rp_startofpacket -> router_004:sink_startofpacket
wire flash_epcs_control_port_agent_rp_endofpacket; // flash_epcs_control_port_agent:rp_endofpacket -> router_004:sink_endofpacket
wire router_004_src_valid; // router_004:src_valid -> rsp_demux_002:sink_valid
wire [100:0] router_004_src_data; // router_004:src_data -> rsp_demux_002:sink_data
wire router_004_src_ready; // rsp_demux_002:sink_ready -> router_004:src_ready
wire [7:0] router_004_src_channel; // router_004:src_channel -> rsp_demux_002:sink_channel
wire router_004_src_startofpacket; // router_004:src_startofpacket -> rsp_demux_002:sink_startofpacket
wire router_004_src_endofpacket; // router_004:src_endofpacket -> rsp_demux_002:sink_endofpacket
wire cpu_jtag_debug_module_agent_rp_valid; // cpu_jtag_debug_module_agent:rp_valid -> router_005:sink_valid
wire [100:0] cpu_jtag_debug_module_agent_rp_data; // cpu_jtag_debug_module_agent:rp_data -> router_005:sink_data
wire cpu_jtag_debug_module_agent_rp_ready; // router_005:sink_ready -> cpu_jtag_debug_module_agent:rp_ready
wire cpu_jtag_debug_module_agent_rp_startofpacket; // cpu_jtag_debug_module_agent:rp_startofpacket -> router_005:sink_startofpacket
wire cpu_jtag_debug_module_agent_rp_endofpacket; // cpu_jtag_debug_module_agent:rp_endofpacket -> router_005:sink_endofpacket
wire router_005_src_valid; // router_005:src_valid -> rsp_demux_003:sink_valid
wire [100:0] router_005_src_data; // router_005:src_data -> rsp_demux_003:sink_data
wire router_005_src_ready; // rsp_demux_003:sink_ready -> router_005:src_ready
wire [7:0] router_005_src_channel; // router_005:src_channel -> rsp_demux_003:sink_channel
wire router_005_src_startofpacket; // router_005:src_startofpacket -> rsp_demux_003:sink_startofpacket
wire router_005_src_endofpacket; // router_005:src_endofpacket -> rsp_demux_003:sink_endofpacket
wire timer_s1_agent_rp_valid; // timer_s1_agent:rp_valid -> router_006:sink_valid
wire [100:0] timer_s1_agent_rp_data; // timer_s1_agent:rp_data -> router_006:sink_data
wire timer_s1_agent_rp_ready; // router_006:sink_ready -> timer_s1_agent:rp_ready
wire timer_s1_agent_rp_startofpacket; // timer_s1_agent:rp_startofpacket -> router_006:sink_startofpacket
wire timer_s1_agent_rp_endofpacket; // timer_s1_agent:rp_endofpacket -> router_006:sink_endofpacket
wire router_006_src_valid; // router_006:src_valid -> rsp_demux_004:sink_valid
wire [100:0] router_006_src_data; // router_006:src_data -> rsp_demux_004:sink_data
wire router_006_src_ready; // rsp_demux_004:sink_ready -> router_006:src_ready
wire [7:0] router_006_src_channel; // router_006:src_channel -> rsp_demux_004:sink_channel
wire router_006_src_startofpacket; // router_006:src_startofpacket -> rsp_demux_004:sink_startofpacket
wire router_006_src_endofpacket; // router_006:src_endofpacket -> rsp_demux_004:sink_endofpacket
wire sw_s1_agent_rp_valid; // SW_s1_agent:rp_valid -> router_007:sink_valid
wire [100:0] sw_s1_agent_rp_data; // SW_s1_agent:rp_data -> router_007:sink_data
wire sw_s1_agent_rp_ready; // router_007:sink_ready -> SW_s1_agent:rp_ready
wire sw_s1_agent_rp_startofpacket; // SW_s1_agent:rp_startofpacket -> router_007:sink_startofpacket
wire sw_s1_agent_rp_endofpacket; // SW_s1_agent:rp_endofpacket -> router_007:sink_endofpacket
wire router_007_src_valid; // router_007:src_valid -> rsp_demux_005:sink_valid
wire [100:0] router_007_src_data; // router_007:src_data -> rsp_demux_005:sink_data
wire router_007_src_ready; // rsp_demux_005:sink_ready -> router_007:src_ready
wire [7:0] router_007_src_channel; // router_007:src_channel -> rsp_demux_005:sink_channel
wire router_007_src_startofpacket; // router_007:src_startofpacket -> rsp_demux_005:sink_startofpacket
wire router_007_src_endofpacket; // router_007:src_endofpacket -> rsp_demux_005:sink_endofpacket
wire led_s1_agent_rp_valid; // LED_s1_agent:rp_valid -> router_008:sink_valid
wire [100:0] led_s1_agent_rp_data; // LED_s1_agent:rp_data -> router_008:sink_data
wire led_s1_agent_rp_ready; // router_008:sink_ready -> LED_s1_agent:rp_ready
wire led_s1_agent_rp_startofpacket; // LED_s1_agent:rp_startofpacket -> router_008:sink_startofpacket
wire led_s1_agent_rp_endofpacket; // LED_s1_agent:rp_endofpacket -> router_008:sink_endofpacket
wire router_008_src_valid; // router_008:src_valid -> rsp_demux_006:sink_valid
wire [100:0] router_008_src_data; // router_008:src_data -> rsp_demux_006:sink_data
wire router_008_src_ready; // rsp_demux_006:sink_ready -> router_008:src_ready
wire [7:0] router_008_src_channel; // router_008:src_channel -> rsp_demux_006:sink_channel
wire router_008_src_startofpacket; // router_008:src_startofpacket -> rsp_demux_006:sink_startofpacket
wire router_008_src_endofpacket; // router_008:src_endofpacket -> rsp_demux_006:sink_endofpacket
wire sdram_s1_agent_rp_valid; // sdram_s1_agent:rp_valid -> router_009:sink_valid
wire [82:0] sdram_s1_agent_rp_data; // sdram_s1_agent:rp_data -> router_009:sink_data
wire sdram_s1_agent_rp_ready; // router_009:sink_ready -> sdram_s1_agent:rp_ready
wire sdram_s1_agent_rp_startofpacket; // sdram_s1_agent:rp_startofpacket -> router_009:sink_startofpacket
wire sdram_s1_agent_rp_endofpacket; // sdram_s1_agent:rp_endofpacket -> router_009:sink_endofpacket
wire sdram_s1_burst_adapter_source0_valid; // sdram_s1_burst_adapter:source0_valid -> sdram_s1_agent:cp_valid
wire [82:0] sdram_s1_burst_adapter_source0_data; // sdram_s1_burst_adapter:source0_data -> sdram_s1_agent:cp_data
wire sdram_s1_burst_adapter_source0_ready; // sdram_s1_agent:cp_ready -> sdram_s1_burst_adapter:source0_ready
wire [7:0] sdram_s1_burst_adapter_source0_channel; // sdram_s1_burst_adapter:source0_channel -> sdram_s1_agent:cp_channel
wire sdram_s1_burst_adapter_source0_startofpacket; // sdram_s1_burst_adapter:source0_startofpacket -> sdram_s1_agent:cp_startofpacket
wire sdram_s1_burst_adapter_source0_endofpacket; // sdram_s1_burst_adapter:source0_endofpacket -> sdram_s1_agent:cp_endofpacket
wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
wire [100:0] cmd_demux_src1_data; // cmd_demux:src1_data -> cmd_mux_001:sink0_data
wire cmd_demux_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
wire [7:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
wire cmd_demux_src2_valid; // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
wire [100:0] cmd_demux_src2_data; // cmd_demux:src2_data -> cmd_mux_002:sink0_data
wire cmd_demux_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
wire [7:0] cmd_demux_src2_channel; // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
wire cmd_demux_src2_startofpacket; // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
wire cmd_demux_src2_endofpacket; // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
wire cmd_demux_src3_valid; // cmd_demux:src3_valid -> cmd_mux_003:sink0_valid
wire [100:0] cmd_demux_src3_data; // cmd_demux:src3_data -> cmd_mux_003:sink0_data
wire cmd_demux_src3_ready; // cmd_mux_003:sink0_ready -> cmd_demux:src3_ready
wire [7:0] cmd_demux_src3_channel; // cmd_demux:src3_channel -> cmd_mux_003:sink0_channel
wire cmd_demux_src3_startofpacket; // cmd_demux:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
wire cmd_demux_src3_endofpacket; // cmd_demux:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
wire cmd_demux_src7_valid; // cmd_demux:src7_valid -> cmd_mux_007:sink0_valid
wire [100:0] cmd_demux_src7_data; // cmd_demux:src7_data -> cmd_mux_007:sink0_data
wire cmd_demux_src7_ready; // cmd_mux_007:sink0_ready -> cmd_demux:src7_ready
wire [7:0] cmd_demux_src7_channel; // cmd_demux:src7_channel -> cmd_mux_007:sink0_channel
wire cmd_demux_src7_startofpacket; // cmd_demux:src7_startofpacket -> cmd_mux_007:sink0_startofpacket
wire cmd_demux_src7_endofpacket; // cmd_demux:src7_endofpacket -> cmd_mux_007:sink0_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux_002:sink1_valid
wire [100:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux_002:sink1_data
wire cmd_demux_001_src0_ready; // cmd_mux_002:sink1_ready -> cmd_demux_001:src0_ready
wire [7:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux_002:sink1_channel
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux_002:sink1_startofpacket
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux_002:sink1_endofpacket
wire cmd_demux_001_src1_valid; // cmd_demux_001:src1_valid -> cmd_mux_003:sink1_valid
wire [100:0] cmd_demux_001_src1_data; // cmd_demux_001:src1_data -> cmd_mux_003:sink1_data
wire cmd_demux_001_src1_ready; // cmd_mux_003:sink1_ready -> cmd_demux_001:src1_ready
wire [7:0] cmd_demux_001_src1_channel; // cmd_demux_001:src1_channel -> cmd_mux_003:sink1_channel
wire cmd_demux_001_src1_startofpacket; // cmd_demux_001:src1_startofpacket -> cmd_mux_003:sink1_startofpacket
wire cmd_demux_001_src1_endofpacket; // cmd_demux_001:src1_endofpacket -> cmd_mux_003:sink1_endofpacket
wire cmd_demux_001_src2_valid; // cmd_demux_001:src2_valid -> cmd_mux_007:sink1_valid
wire [100:0] cmd_demux_001_src2_data; // cmd_demux_001:src2_data -> cmd_mux_007:sink1_data
wire cmd_demux_001_src2_ready; // cmd_mux_007:sink1_ready -> cmd_demux_001:src2_ready
wire [7:0] cmd_demux_001_src2_channel; // cmd_demux_001:src2_channel -> cmd_mux_007:sink1_channel
wire cmd_demux_001_src2_startofpacket; // cmd_demux_001:src2_startofpacket -> cmd_mux_007:sink1_startofpacket
wire cmd_demux_001_src2_endofpacket; // cmd_demux_001:src2_endofpacket -> cmd_mux_007:sink1_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
wire [100:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux:sink1_data
wire rsp_demux_001_src0_ready; // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
wire [7:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
wire [100:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux:sink2_data
wire rsp_demux_002_src0_ready; // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
wire [7:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
wire rsp_demux_002_src1_valid; // rsp_demux_002:src1_valid -> rsp_mux_001:sink0_valid
wire [100:0] rsp_demux_002_src1_data; // rsp_demux_002:src1_data -> rsp_mux_001:sink0_data
wire rsp_demux_002_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux_002:src1_ready
wire [7:0] rsp_demux_002_src1_channel; // rsp_demux_002:src1_channel -> rsp_mux_001:sink0_channel
wire rsp_demux_002_src1_startofpacket; // rsp_demux_002:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
wire rsp_demux_002_src1_endofpacket; // rsp_demux_002:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
wire rsp_demux_003_src0_valid; // rsp_demux_003:src0_valid -> rsp_mux:sink3_valid
wire [100:0] rsp_demux_003_src0_data; // rsp_demux_003:src0_data -> rsp_mux:sink3_data
wire rsp_demux_003_src0_ready; // rsp_mux:sink3_ready -> rsp_demux_003:src0_ready
wire [7:0] rsp_demux_003_src0_channel; // rsp_demux_003:src0_channel -> rsp_mux:sink3_channel
wire rsp_demux_003_src0_startofpacket; // rsp_demux_003:src0_startofpacket -> rsp_mux:sink3_startofpacket
wire rsp_demux_003_src0_endofpacket; // rsp_demux_003:src0_endofpacket -> rsp_mux:sink3_endofpacket
wire rsp_demux_003_src1_valid; // rsp_demux_003:src1_valid -> rsp_mux_001:sink1_valid
wire [100:0] rsp_demux_003_src1_data; // rsp_demux_003:src1_data -> rsp_mux_001:sink1_data
wire rsp_demux_003_src1_ready; // rsp_mux_001:sink1_ready -> rsp_demux_003:src1_ready
wire [7:0] rsp_demux_003_src1_channel; // rsp_demux_003:src1_channel -> rsp_mux_001:sink1_channel
wire rsp_demux_003_src1_startofpacket; // rsp_demux_003:src1_startofpacket -> rsp_mux_001:sink1_startofpacket
wire rsp_demux_003_src1_endofpacket; // rsp_demux_003:src1_endofpacket -> rsp_mux_001:sink1_endofpacket
wire rsp_demux_007_src0_valid; // rsp_demux_007:src0_valid -> rsp_mux:sink7_valid
wire [100:0] rsp_demux_007_src0_data; // rsp_demux_007:src0_data -> rsp_mux:sink7_data
wire rsp_demux_007_src0_ready; // rsp_mux:sink7_ready -> rsp_demux_007:src0_ready
wire [7:0] rsp_demux_007_src0_channel; // rsp_demux_007:src0_channel -> rsp_mux:sink7_channel
wire rsp_demux_007_src0_startofpacket; // rsp_demux_007:src0_startofpacket -> rsp_mux:sink7_startofpacket
wire rsp_demux_007_src0_endofpacket; // rsp_demux_007:src0_endofpacket -> rsp_mux:sink7_endofpacket
wire rsp_demux_007_src1_valid; // rsp_demux_007:src1_valid -> rsp_mux_001:sink2_valid
wire [100:0] rsp_demux_007_src1_data; // rsp_demux_007:src1_data -> rsp_mux_001:sink2_data
wire rsp_demux_007_src1_ready; // rsp_mux_001:sink2_ready -> rsp_demux_007:src1_ready
wire [7:0] rsp_demux_007_src1_channel; // rsp_demux_007:src1_channel -> rsp_mux_001:sink2_channel
wire rsp_demux_007_src1_startofpacket; // rsp_demux_007:src1_startofpacket -> rsp_mux_001:sink2_startofpacket
wire rsp_demux_007_src1_endofpacket; // rsp_demux_007:src1_endofpacket -> rsp_mux_001:sink2_endofpacket
wire router_009_src_valid; // router_009:src_valid -> sdram_s1_rsp_width_adapter:in_valid
wire [82:0] router_009_src_data; // router_009:src_data -> sdram_s1_rsp_width_adapter:in_data
wire router_009_src_ready; // sdram_s1_rsp_width_adapter:in_ready -> router_009:src_ready
wire [7:0] router_009_src_channel; // router_009:src_channel -> sdram_s1_rsp_width_adapter:in_channel
wire router_009_src_startofpacket; // router_009:src_startofpacket -> sdram_s1_rsp_width_adapter:in_startofpacket
wire router_009_src_endofpacket; // router_009:src_endofpacket -> sdram_s1_rsp_width_adapter:in_endofpacket
wire sdram_s1_rsp_width_adapter_src_valid; // sdram_s1_rsp_width_adapter:out_valid -> rsp_demux_007:sink_valid
wire [100:0] sdram_s1_rsp_width_adapter_src_data; // sdram_s1_rsp_width_adapter:out_data -> rsp_demux_007:sink_data
wire sdram_s1_rsp_width_adapter_src_ready; // rsp_demux_007:sink_ready -> sdram_s1_rsp_width_adapter:out_ready
wire [7:0] sdram_s1_rsp_width_adapter_src_channel; // sdram_s1_rsp_width_adapter:out_channel -> rsp_demux_007:sink_channel
wire sdram_s1_rsp_width_adapter_src_startofpacket; // sdram_s1_rsp_width_adapter:out_startofpacket -> rsp_demux_007:sink_startofpacket
wire sdram_s1_rsp_width_adapter_src_endofpacket; // sdram_s1_rsp_width_adapter:out_endofpacket -> rsp_demux_007:sink_endofpacket
wire cmd_mux_007_src_valid; // cmd_mux_007:src_valid -> sdram_s1_cmd_width_adapter:in_valid
wire [100:0] cmd_mux_007_src_data; // cmd_mux_007:src_data -> sdram_s1_cmd_width_adapter:in_data
wire cmd_mux_007_src_ready; // sdram_s1_cmd_width_adapter:in_ready -> cmd_mux_007:src_ready
wire [7:0] cmd_mux_007_src_channel; // cmd_mux_007:src_channel -> sdram_s1_cmd_width_adapter:in_channel
wire cmd_mux_007_src_startofpacket; // cmd_mux_007:src_startofpacket -> sdram_s1_cmd_width_adapter:in_startofpacket
wire cmd_mux_007_src_endofpacket; // cmd_mux_007:src_endofpacket -> sdram_s1_cmd_width_adapter:in_endofpacket
wire sdram_s1_cmd_width_adapter_src_valid; // sdram_s1_cmd_width_adapter:out_valid -> sdram_s1_burst_adapter:sink0_valid
wire [82:0] sdram_s1_cmd_width_adapter_src_data; // sdram_s1_cmd_width_adapter:out_data -> sdram_s1_burst_adapter:sink0_data
wire sdram_s1_cmd_width_adapter_src_ready; // sdram_s1_burst_adapter:sink0_ready -> sdram_s1_cmd_width_adapter:out_ready
wire [7:0] sdram_s1_cmd_width_adapter_src_channel; // sdram_s1_cmd_width_adapter:out_channel -> sdram_s1_burst_adapter:sink0_channel
wire sdram_s1_cmd_width_adapter_src_startofpacket; // sdram_s1_cmd_width_adapter:out_startofpacket -> sdram_s1_burst_adapter:sink0_startofpacket
wire sdram_s1_cmd_width_adapter_src_endofpacket; // sdram_s1_cmd_width_adapter:out_endofpacket -> sdram_s1_burst_adapter:sink0_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> crosser:in_valid
wire [100:0] cmd_demux_src0_data; // cmd_demux:src0_data -> crosser:in_data
wire cmd_demux_src0_ready; // crosser:in_ready -> cmd_demux:src0_ready
wire [7:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> crosser:in_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> crosser:in_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> crosser:in_endofpacket
wire crosser_out_valid; // crosser:out_valid -> cmd_mux:sink0_valid
wire [100:0] crosser_out_data; // crosser:out_data -> cmd_mux:sink0_data
wire crosser_out_ready; // cmd_mux:sink0_ready -> crosser:out_ready
wire [7:0] crosser_out_channel; // crosser:out_channel -> cmd_mux:sink0_channel
wire crosser_out_startofpacket; // crosser:out_startofpacket -> cmd_mux:sink0_startofpacket
wire crosser_out_endofpacket; // crosser:out_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src4_valid; // cmd_demux:src4_valid -> crosser_001:in_valid
wire [100:0] cmd_demux_src4_data; // cmd_demux:src4_data -> crosser_001:in_data
wire cmd_demux_src4_ready; // crosser_001:in_ready -> cmd_demux:src4_ready
wire [7:0] cmd_demux_src4_channel; // cmd_demux:src4_channel -> crosser_001:in_channel
wire cmd_demux_src4_startofpacket; // cmd_demux:src4_startofpacket -> crosser_001:in_startofpacket
wire cmd_demux_src4_endofpacket; // cmd_demux:src4_endofpacket -> crosser_001:in_endofpacket
wire crosser_001_out_valid; // crosser_001:out_valid -> cmd_mux_004:sink0_valid
wire [100:0] crosser_001_out_data; // crosser_001:out_data -> cmd_mux_004:sink0_data
wire crosser_001_out_ready; // cmd_mux_004:sink0_ready -> crosser_001:out_ready
wire [7:0] crosser_001_out_channel; // crosser_001:out_channel -> cmd_mux_004:sink0_channel
wire crosser_001_out_startofpacket; // crosser_001:out_startofpacket -> cmd_mux_004:sink0_startofpacket
wire crosser_001_out_endofpacket; // crosser_001:out_endofpacket -> cmd_mux_004:sink0_endofpacket
wire cmd_demux_src5_valid; // cmd_demux:src5_valid -> crosser_002:in_valid
wire [100:0] cmd_demux_src5_data; // cmd_demux:src5_data -> crosser_002:in_data
wire cmd_demux_src5_ready; // crosser_002:in_ready -> cmd_demux:src5_ready
wire [7:0] cmd_demux_src5_channel; // cmd_demux:src5_channel -> crosser_002:in_channel
wire cmd_demux_src5_startofpacket; // cmd_demux:src5_startofpacket -> crosser_002:in_startofpacket
wire cmd_demux_src5_endofpacket; // cmd_demux:src5_endofpacket -> crosser_002:in_endofpacket
wire crosser_002_out_valid; // crosser_002:out_valid -> cmd_mux_005:sink0_valid
wire [100:0] crosser_002_out_data; // crosser_002:out_data -> cmd_mux_005:sink0_data
wire crosser_002_out_ready; // cmd_mux_005:sink0_ready -> crosser_002:out_ready
wire [7:0] crosser_002_out_channel; // crosser_002:out_channel -> cmd_mux_005:sink0_channel
wire crosser_002_out_startofpacket; // crosser_002:out_startofpacket -> cmd_mux_005:sink0_startofpacket
wire crosser_002_out_endofpacket; // crosser_002:out_endofpacket -> cmd_mux_005:sink0_endofpacket
wire cmd_demux_src6_valid; // cmd_demux:src6_valid -> crosser_003:in_valid
wire [100:0] cmd_demux_src6_data; // cmd_demux:src6_data -> crosser_003:in_data
wire cmd_demux_src6_ready; // crosser_003:in_ready -> cmd_demux:src6_ready
wire [7:0] cmd_demux_src6_channel; // cmd_demux:src6_channel -> crosser_003:in_channel
wire cmd_demux_src6_startofpacket; // cmd_demux:src6_startofpacket -> crosser_003:in_startofpacket
wire cmd_demux_src6_endofpacket; // cmd_demux:src6_endofpacket -> crosser_003:in_endofpacket
wire crosser_003_out_valid; // crosser_003:out_valid -> cmd_mux_006:sink0_valid
wire [100:0] crosser_003_out_data; // crosser_003:out_data -> cmd_mux_006:sink0_data
wire crosser_003_out_ready; // cmd_mux_006:sink0_ready -> crosser_003:out_ready
wire [7:0] crosser_003_out_channel; // crosser_003:out_channel -> cmd_mux_006:sink0_channel
wire crosser_003_out_startofpacket; // crosser_003:out_startofpacket -> cmd_mux_006:sink0_startofpacket
wire crosser_003_out_endofpacket; // crosser_003:out_endofpacket -> cmd_mux_006:sink0_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> crosser_004:in_valid
wire [100:0] rsp_demux_src0_data; // rsp_demux:src0_data -> crosser_004:in_data
wire rsp_demux_src0_ready; // crosser_004:in_ready -> rsp_demux:src0_ready
wire [7:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> crosser_004:in_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> crosser_004:in_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> crosser_004:in_endofpacket
wire crosser_004_out_valid; // crosser_004:out_valid -> rsp_mux:sink0_valid
wire [100:0] crosser_004_out_data; // crosser_004:out_data -> rsp_mux:sink0_data
wire crosser_004_out_ready; // rsp_mux:sink0_ready -> crosser_004:out_ready
wire [7:0] crosser_004_out_channel; // crosser_004:out_channel -> rsp_mux:sink0_channel
wire crosser_004_out_startofpacket; // crosser_004:out_startofpacket -> rsp_mux:sink0_startofpacket
wire crosser_004_out_endofpacket; // crosser_004:out_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_004_src0_valid; // rsp_demux_004:src0_valid -> crosser_005:in_valid
wire [100:0] rsp_demux_004_src0_data; // rsp_demux_004:src0_data -> crosser_005:in_data
wire rsp_demux_004_src0_ready; // crosser_005:in_ready -> rsp_demux_004:src0_ready
wire [7:0] rsp_demux_004_src0_channel; // rsp_demux_004:src0_channel -> crosser_005:in_channel
wire rsp_demux_004_src0_startofpacket; // rsp_demux_004:src0_startofpacket -> crosser_005:in_startofpacket
wire rsp_demux_004_src0_endofpacket; // rsp_demux_004:src0_endofpacket -> crosser_005:in_endofpacket
wire crosser_005_out_valid; // crosser_005:out_valid -> rsp_mux:sink4_valid
wire [100:0] crosser_005_out_data; // crosser_005:out_data -> rsp_mux:sink4_data
wire crosser_005_out_ready; // rsp_mux:sink4_ready -> crosser_005:out_ready
wire [7:0] crosser_005_out_channel; // crosser_005:out_channel -> rsp_mux:sink4_channel
wire crosser_005_out_startofpacket; // crosser_005:out_startofpacket -> rsp_mux:sink4_startofpacket
wire crosser_005_out_endofpacket; // crosser_005:out_endofpacket -> rsp_mux:sink4_endofpacket
wire rsp_demux_005_src0_valid; // rsp_demux_005:src0_valid -> crosser_006:in_valid
wire [100:0] rsp_demux_005_src0_data; // rsp_demux_005:src0_data -> crosser_006:in_data
wire rsp_demux_005_src0_ready; // crosser_006:in_ready -> rsp_demux_005:src0_ready
wire [7:0] rsp_demux_005_src0_channel; // rsp_demux_005:src0_channel -> crosser_006:in_channel
wire rsp_demux_005_src0_startofpacket; // rsp_demux_005:src0_startofpacket -> crosser_006:in_startofpacket
wire rsp_demux_005_src0_endofpacket; // rsp_demux_005:src0_endofpacket -> crosser_006:in_endofpacket
wire crosser_006_out_valid; // crosser_006:out_valid -> rsp_mux:sink5_valid
wire [100:0] crosser_006_out_data; // crosser_006:out_data -> rsp_mux:sink5_data
wire crosser_006_out_ready; // rsp_mux:sink5_ready -> crosser_006:out_ready
wire [7:0] crosser_006_out_channel; // crosser_006:out_channel -> rsp_mux:sink5_channel
wire crosser_006_out_startofpacket; // crosser_006:out_startofpacket -> rsp_mux:sink5_startofpacket
wire crosser_006_out_endofpacket; // crosser_006:out_endofpacket -> rsp_mux:sink5_endofpacket
wire rsp_demux_006_src0_valid; // rsp_demux_006:src0_valid -> crosser_007:in_valid
wire [100:0] rsp_demux_006_src0_data; // rsp_demux_006:src0_data -> crosser_007:in_data
wire rsp_demux_006_src0_ready; // crosser_007:in_ready -> rsp_demux_006:src0_ready
wire [7:0] rsp_demux_006_src0_channel; // rsp_demux_006:src0_channel -> crosser_007:in_channel
wire rsp_demux_006_src0_startofpacket; // rsp_demux_006:src0_startofpacket -> crosser_007:in_startofpacket
wire rsp_demux_006_src0_endofpacket; // rsp_demux_006:src0_endofpacket -> crosser_007:in_endofpacket
wire crosser_007_out_valid; // crosser_007:out_valid -> rsp_mux:sink6_valid
wire [100:0] crosser_007_out_data; // crosser_007:out_data -> rsp_mux:sink6_data
wire crosser_007_out_ready; // rsp_mux:sink6_ready -> crosser_007:out_ready
wire [7:0] crosser_007_out_channel; // crosser_007:out_channel -> rsp_mux:sink6_channel
wire crosser_007_out_startofpacket; // crosser_007:out_startofpacket -> rsp_mux:sink6_startofpacket
wire crosser_007_out_endofpacket; // crosser_007:out_endofpacket -> rsp_mux:sink6_endofpacket
altera_merlin_master_translator #(
.AV_ADDRESS_W (25),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (25),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (1)
) cpu_data_master_translator (
.clk (pll_c0_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (cpu_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (cpu_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (cpu_data_master_translator_avalon_universal_master_0_read), // .read
.uav_write (cpu_data_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (cpu_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (cpu_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (cpu_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (cpu_data_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (cpu_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (cpu_data_master_address), // avalon_anti_master_0.address
.av_waitrequest (cpu_data_master_waitrequest), // .waitrequest
.av_byteenable (cpu_data_master_byteenable), // .byteenable
.av_read (cpu_data_master_read), // .read
.av_readdata (cpu_data_master_readdata), // .readdata
.av_write (cpu_data_master_write), // .write
.av_writedata (cpu_data_master_writedata), // .writedata
.av_debugaccess (cpu_data_master_debugaccess), // .debugaccess
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (25),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (25),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (1),
.AV_REGISTERINCOMINGSIGNALS (0)
) cpu_instruction_master_translator (
.clk (pll_c0_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (cpu_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (cpu_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (cpu_instruction_master_translator_avalon_universal_master_0_read), // .read
.uav_write (cpu_instruction_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (cpu_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (cpu_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (cpu_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (cpu_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (cpu_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (cpu_instruction_master_address), // avalon_anti_master_0.address
.av_waitrequest (cpu_instruction_master_waitrequest), // .waitrequest
.av_read (cpu_instruction_master_read), // .read
.av_readdata (cpu_instruction_master_readdata), // .readdata
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (25),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) jtag_avalon_jtag_slave_translator (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (jtag_avalon_jtag_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (jtag_avalon_jtag_slave_agent_m0_burstcount), // .burstcount
.uav_read (jtag_avalon_jtag_slave_agent_m0_read), // .read
.uav_write (jtag_avalon_jtag_slave_agent_m0_write), // .write
.uav_waitrequest (jtag_avalon_jtag_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (jtag_avalon_jtag_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (jtag_avalon_jtag_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (jtag_avalon_jtag_slave_agent_m0_readdata), // .readdata
.uav_writedata (jtag_avalon_jtag_slave_agent_m0_writedata), // .writedata
.uav_lock (jtag_avalon_jtag_slave_agent_m0_lock), // .lock
.uav_debugaccess (jtag_avalon_jtag_slave_agent_m0_debugaccess), // .debugaccess
.av_address (jtag_avalon_jtag_slave_address), // avalon_anti_slave_0.address
.av_write (jtag_avalon_jtag_slave_write), // .write
.av_read (jtag_avalon_jtag_slave_read), // .read
.av_readdata (jtag_avalon_jtag_slave_readdata), // .readdata
.av_writedata (jtag_avalon_jtag_slave_writedata), // .writedata
.av_waitrequest (jtag_avalon_jtag_slave_waitrequest), // .waitrequest
.av_chipselect (jtag_avalon_jtag_slave_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (25),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sysid_control_slave_translator (
.clk (pll_c0_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sysid_control_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sysid_control_slave_agent_m0_burstcount), // .burstcount
.uav_read (sysid_control_slave_agent_m0_read), // .read
.uav_write (sysid_control_slave_agent_m0_write), // .write
.uav_waitrequest (sysid_control_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sysid_control_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sysid_control_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (sysid_control_slave_agent_m0_readdata), // .readdata
.uav_writedata (sysid_control_slave_agent_m0_writedata), // .writedata
.uav_lock (sysid_control_slave_agent_m0_lock), // .lock
.uav_debugaccess (sysid_control_slave_agent_m0_debugaccess), // .debugaccess
.av_address (sysid_control_slave_address), // avalon_anti_slave_0.address
.av_readdata (sysid_control_slave_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (25),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (1),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) flash_epcs_control_port_translator (
.clk (pll_c0_clk), // clk.clk
.reset (flash_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (flash_epcs_control_port_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (flash_epcs_control_port_agent_m0_burstcount), // .burstcount
.uav_read (flash_epcs_control_port_agent_m0_read), // .read
.uav_write (flash_epcs_control_port_agent_m0_write), // .write
.uav_waitrequest (flash_epcs_control_port_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (flash_epcs_control_port_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (flash_epcs_control_port_agent_m0_byteenable), // .byteenable
.uav_readdata (flash_epcs_control_port_agent_m0_readdata), // .readdata
.uav_writedata (flash_epcs_control_port_agent_m0_writedata), // .writedata
.uav_lock (flash_epcs_control_port_agent_m0_lock), // .lock
.uav_debugaccess (flash_epcs_control_port_agent_m0_debugaccess), // .debugaccess
.av_address (flash_epcs_control_port_address), // avalon_anti_slave_0.address
.av_write (flash_epcs_control_port_write), // .write
.av_read (flash_epcs_control_port_read), // .read
.av_readdata (flash_epcs_control_port_readdata), // .readdata
.av_writedata (flash_epcs_control_port_writedata), // .writedata
.av_chipselect (flash_epcs_control_port_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (25),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) cpu_jtag_debug_module_translator (
.clk (pll_c0_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (cpu_jtag_debug_module_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (cpu_jtag_debug_module_agent_m0_burstcount), // .burstcount
.uav_read (cpu_jtag_debug_module_agent_m0_read), // .read
.uav_write (cpu_jtag_debug_module_agent_m0_write), // .write
.uav_waitrequest (cpu_jtag_debug_module_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_jtag_debug_module_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_jtag_debug_module_agent_m0_byteenable), // .byteenable
.uav_readdata (cpu_jtag_debug_module_agent_m0_readdata), // .readdata
.uav_writedata (cpu_jtag_debug_module_agent_m0_writedata), // .writedata
.uav_lock (cpu_jtag_debug_module_agent_m0_lock), // .lock
.uav_debugaccess (cpu_jtag_debug_module_agent_m0_debugaccess), // .debugaccess
.av_address (cpu_jtag_debug_module_address), // avalon_anti_slave_0.address
.av_write (cpu_jtag_debug_module_write), // .write
.av_read (cpu_jtag_debug_module_read), // .read
.av_readdata (cpu_jtag_debug_module_readdata), // .readdata
.av_writedata (cpu_jtag_debug_module_writedata), // .writedata
.av_byteenable (cpu_jtag_debug_module_byteenable), // .byteenable
.av_waitrequest (cpu_jtag_debug_module_waitrequest), // .waitrequest
.av_debugaccess (cpu_jtag_debug_module_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (3),
.AV_DATA_W (16),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (25),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) timer_s1_translator (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (timer_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (timer_s1_agent_m0_burstcount), // .burstcount
.uav_read (timer_s1_agent_m0_read), // .read
.uav_write (timer_s1_agent_m0_write), // .write
.uav_waitrequest (timer_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (timer_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (timer_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (timer_s1_agent_m0_readdata), // .readdata
.uav_writedata (timer_s1_agent_m0_writedata), // .writedata
.uav_lock (timer_s1_agent_m0_lock), // .lock
.uav_debugaccess (timer_s1_agent_m0_debugaccess), // .debugaccess
.av_address (timer_s1_address), // avalon_anti_slave_0.address
.av_write (timer_s1_write), // .write
.av_readdata (timer_s1_readdata), // .readdata
.av_writedata (timer_s1_writedata), // .writedata
.av_chipselect (timer_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (25),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sw_s1_translator (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sw_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sw_s1_agent_m0_burstcount), // .burstcount
.uav_read (sw_s1_agent_m0_read), // .read
.uav_write (sw_s1_agent_m0_write), // .write
.uav_waitrequest (sw_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sw_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sw_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (sw_s1_agent_m0_readdata), // .readdata
.uav_writedata (sw_s1_agent_m0_writedata), // .writedata
.uav_lock (sw_s1_agent_m0_lock), // .lock
.uav_debugaccess (sw_s1_agent_m0_debugaccess), // .debugaccess
.av_address (SW_s1_address), // avalon_anti_slave_0.address
.av_readdata (SW_s1_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (25),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) led_s1_translator (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (led_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (led_s1_agent_m0_burstcount), // .burstcount
.uav_read (led_s1_agent_m0_read), // .read
.uav_write (led_s1_agent_m0_write), // .write
.uav_waitrequest (led_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (led_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (led_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (led_s1_agent_m0_readdata), // .readdata
.uav_writedata (led_s1_agent_m0_writedata), // .writedata
.uav_lock (led_s1_agent_m0_lock), // .lock
.uav_debugaccess (led_s1_agent_m0_debugaccess), // .debugaccess
.av_address (LED_s1_address), // avalon_anti_slave_0.address
.av_write (LED_s1_write), // .write
.av_readdata (LED_s1_readdata), // .readdata
.av_writedata (LED_s1_writedata), // .writedata
.av_chipselect (LED_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (22),
.AV_DATA_W (16),
.UAV_DATA_W (16),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (2),
.UAV_BYTEENABLE_W (2),
.UAV_ADDRESS_W (25),
.UAV_BURSTCOUNT_W (2),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (2),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sdram_s1_translator (
.clk (pll_c0_clk), // clk.clk
.reset (flash_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sdram_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sdram_s1_agent_m0_burstcount), // .burstcount
.uav_read (sdram_s1_agent_m0_read), // .read
.uav_write (sdram_s1_agent_m0_write), // .write
.uav_waitrequest (sdram_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sdram_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sdram_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (sdram_s1_agent_m0_readdata), // .readdata
.uav_writedata (sdram_s1_agent_m0_writedata), // .writedata
.uav_lock (sdram_s1_agent_m0_lock), // .lock
.uav_debugaccess (sdram_s1_agent_m0_debugaccess), // .debugaccess
.av_address (sdram_s1_address), // avalon_anti_slave_0.address
.av_write (sdram_s1_write), // .write
.av_read (sdram_s1_read), // .read
.av_readdata (sdram_s1_readdata), // .readdata
.av_writedata (sdram_s1_writedata), // .writedata
.av_byteenable (sdram_s1_byteenable), // .byteenable
.av_readdatavalid (sdram_s1_readdatavalid), // .readdatavalid
.av_waitrequest (sdram_s1_waitrequest), // .waitrequest
.av_chipselect (sdram_s1_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (100),
.PKT_ORI_BURST_SIZE_L (98),
.PKT_RESPONSE_STATUS_H (97),
.PKT_RESPONSE_STATUS_L (96),
.PKT_QOS_H (81),
.PKT_QOS_L (81),
.PKT_DATA_SIDEBAND_H (79),
.PKT_DATA_SIDEBAND_L (79),
.PKT_ADDR_SIDEBAND_H (78),
.PKT_ADDR_SIDEBAND_L (78),
.PKT_BURST_TYPE_H (77),
.PKT_BURST_TYPE_L (76),
.PKT_CACHE_H (95),
.PKT_CACHE_L (92),
.PKT_THREAD_ID_H (88),
.PKT_THREAD_ID_L (88),
.PKT_BURST_SIZE_H (75),
.PKT_BURST_SIZE_L (73),
.PKT_TRANS_EXCLUSIVE (66),
.PKT_TRANS_LOCK (65),
.PKT_BEGIN_BURST (80),
.PKT_PROTECTION_H (91),
.PKT_PROTECTION_L (89),
.PKT_BURSTWRAP_H (72),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (67),
.PKT_ADDR_H (60),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (61),
.PKT_TRANS_POSTED (62),
.PKT_TRANS_WRITE (63),
.PKT_TRANS_READ (64),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (82),
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (85),
.ST_DATA_W (101),
.ST_CHANNEL_W (8),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) cpu_data_master_agent (
.clk (pll_c0_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (cpu_data_master_translator_avalon_universal_master_0_address), // av.address
.av_write (cpu_data_master_translator_avalon_universal_master_0_write), // .write
.av_read (cpu_data_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (cpu_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (cpu_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (cpu_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (cpu_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (cpu_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (cpu_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (cpu_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (cpu_data_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (cpu_data_master_agent_cp_valid), // cp.valid
.cp_data (cpu_data_master_agent_cp_data), // .data
.cp_startofpacket (cpu_data_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (cpu_data_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (cpu_data_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_src_valid), // rp.valid
.rp_data (rsp_mux_src_data), // .data
.rp_channel (rsp_mux_src_channel), // .channel
.rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (100),
.PKT_ORI_BURST_SIZE_L (98),
.PKT_RESPONSE_STATUS_H (97),
.PKT_RESPONSE_STATUS_L (96),
.PKT_QOS_H (81),
.PKT_QOS_L (81),
.PKT_DATA_SIDEBAND_H (79),
.PKT_DATA_SIDEBAND_L (79),
.PKT_ADDR_SIDEBAND_H (78),
.PKT_ADDR_SIDEBAND_L (78),
.PKT_BURST_TYPE_H (77),
.PKT_BURST_TYPE_L (76),
.PKT_CACHE_H (95),
.PKT_CACHE_L (92),
.PKT_THREAD_ID_H (88),
.PKT_THREAD_ID_L (88),
.PKT_BURST_SIZE_H (75),
.PKT_BURST_SIZE_L (73),
.PKT_TRANS_EXCLUSIVE (66),
.PKT_TRANS_LOCK (65),
.PKT_BEGIN_BURST (80),
.PKT_PROTECTION_H (91),
.PKT_PROTECTION_L (89),
.PKT_BURSTWRAP_H (72),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (67),
.PKT_ADDR_H (60),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (61),
.PKT_TRANS_POSTED (62),
.PKT_TRANS_WRITE (63),
.PKT_TRANS_READ (64),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (82),
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (85),
.ST_DATA_W (101),
.ST_CHANNEL_W (8),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (3),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) cpu_instruction_master_agent (
.clk (pll_c0_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (cpu_instruction_master_translator_avalon_universal_master_0_address), // av.address
.av_write (cpu_instruction_master_translator_avalon_universal_master_0_write), // .write
.av_read (cpu_instruction_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (cpu_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (cpu_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (cpu_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (cpu_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (cpu_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (cpu_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (cpu_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (cpu_instruction_master_agent_cp_valid), // cp.valid
.cp_data (cpu_instruction_master_agent_cp_data), // .data
.cp_startofpacket (cpu_instruction_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (cpu_instruction_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (cpu_instruction_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_001_src_valid), // rp.valid
.rp_data (rsp_mux_001_src_data), // .data
.rp_channel (rsp_mux_001_src_channel), // .channel
.rp_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_001_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (100),
.PKT_ORI_BURST_SIZE_L (98),
.PKT_RESPONSE_STATUS_H (97),
.PKT_RESPONSE_STATUS_L (96),
.PKT_BURST_SIZE_H (75),
.PKT_BURST_SIZE_L (73),
.PKT_TRANS_LOCK (65),
.PKT_BEGIN_BURST (80),
.PKT_PROTECTION_H (91),
.PKT_PROTECTION_L (89),
.PKT_BURSTWRAP_H (72),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (67),
.PKT_ADDR_H (60),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (61),
.PKT_TRANS_POSTED (62),
.PKT_TRANS_WRITE (63),
.PKT_TRANS_READ (64),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (82),
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (85),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (8),
.ST_DATA_W (101),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) jtag_avalon_jtag_slave_agent (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (jtag_avalon_jtag_slave_agent_m0_address), // m0.address
.m0_burstcount (jtag_avalon_jtag_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (jtag_avalon_jtag_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (jtag_avalon_jtag_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (jtag_avalon_jtag_slave_agent_m0_lock), // .lock
.m0_readdata (jtag_avalon_jtag_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (jtag_avalon_jtag_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (jtag_avalon_jtag_slave_agent_m0_read), // .read
.m0_waitrequest (jtag_avalon_jtag_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (jtag_avalon_jtag_slave_agent_m0_writedata), // .writedata
.m0_write (jtag_avalon_jtag_slave_agent_m0_write), // .write
.rp_endofpacket (jtag_avalon_jtag_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (jtag_avalon_jtag_slave_agent_rp_ready), // .ready
.rp_valid (jtag_avalon_jtag_slave_agent_rp_valid), // .valid
.rp_data (jtag_avalon_jtag_slave_agent_rp_data), // .data
.rp_startofpacket (jtag_avalon_jtag_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_src_ready), // cp.ready
.cp_valid (cmd_mux_src_valid), // .valid
.cp_data (cmd_mux_src_data), // .data
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_src_channel), // .channel
.rf_sink_ready (jtag_avalon_jtag_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (jtag_avalon_jtag_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (jtag_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (jtag_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (jtag_avalon_jtag_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (jtag_avalon_jtag_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (jtag_avalon_jtag_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (jtag_avalon_jtag_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (jtag_avalon_jtag_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (jtag_avalon_jtag_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (jtag_avalon_jtag_slave_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (jtag_avalon_jtag_slave_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (jtag_avalon_jtag_slave_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (jtag_avalon_jtag_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (jtag_avalon_jtag_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (jtag_avalon_jtag_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (102),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) jtag_avalon_jtag_slave_agent_rsp_fifo (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (jtag_avalon_jtag_slave_agent_rf_source_data), // in.data
.in_valid (jtag_avalon_jtag_slave_agent_rf_source_valid), // .valid
.in_ready (jtag_avalon_jtag_slave_agent_rf_source_ready), // .ready
.in_startofpacket (jtag_avalon_jtag_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (jtag_avalon_jtag_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (jtag_avalon_jtag_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (jtag_avalon_jtag_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (jtag_avalon_jtag_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (jtag_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (jtag_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) jtag_avalon_jtag_slave_agent_rdata_fifo (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (jtag_avalon_jtag_slave_agent_rdata_fifo_src_data), // in.data
.in_valid (jtag_avalon_jtag_slave_agent_rdata_fifo_src_valid), // .valid
.in_ready (jtag_avalon_jtag_slave_agent_rdata_fifo_src_ready), // .ready
.out_data (jtag_avalon_jtag_slave_agent_rdata_fifo_out_data), // out.data
.out_valid (jtag_avalon_jtag_slave_agent_rdata_fifo_out_valid), // .valid
.out_ready (jtag_avalon_jtag_slave_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (100),
.PKT_ORI_BURST_SIZE_L (98),
.PKT_RESPONSE_STATUS_H (97),
.PKT_RESPONSE_STATUS_L (96),
.PKT_BURST_SIZE_H (75),
.PKT_BURST_SIZE_L (73),
.PKT_TRANS_LOCK (65),
.PKT_BEGIN_BURST (80),
.PKT_PROTECTION_H (91),
.PKT_PROTECTION_L (89),
.PKT_BURSTWRAP_H (72),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (67),
.PKT_ADDR_H (60),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (61),
.PKT_TRANS_POSTED (62),
.PKT_TRANS_WRITE (63),
.PKT_TRANS_READ (64),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (82),
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (85),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (8),
.ST_DATA_W (101),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sysid_control_slave_agent (
.clk (pll_c0_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sysid_control_slave_agent_m0_address), // m0.address
.m0_burstcount (sysid_control_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (sysid_control_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sysid_control_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (sysid_control_slave_agent_m0_lock), // .lock
.m0_readdata (sysid_control_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (sysid_control_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sysid_control_slave_agent_m0_read), // .read
.m0_waitrequest (sysid_control_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sysid_control_slave_agent_m0_writedata), // .writedata
.m0_write (sysid_control_slave_agent_m0_write), // .write
.rp_endofpacket (sysid_control_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sysid_control_slave_agent_rp_ready), // .ready
.rp_valid (sysid_control_slave_agent_rp_valid), // .valid
.rp_data (sysid_control_slave_agent_rp_data), // .data
.rp_startofpacket (sysid_control_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_001_src_ready), // cp.ready
.cp_valid (cmd_mux_001_src_valid), // .valid
.cp_data (cmd_mux_001_src_data), // .data
.cp_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_001_src_channel), // .channel
.rf_sink_ready (sysid_control_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sysid_control_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sysid_control_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sysid_control_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sysid_control_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sysid_control_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sysid_control_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sysid_control_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sysid_control_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sysid_control_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sysid_control_slave_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sysid_control_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sysid_control_slave_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sysid_control_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sysid_control_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sysid_control_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (102),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sysid_control_slave_agent_rsp_fifo (
.clk (pll_c0_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sysid_control_slave_agent_rf_source_data), // in.data
.in_valid (sysid_control_slave_agent_rf_source_valid), // .valid
.in_ready (sysid_control_slave_agent_rf_source_ready), // .ready
.in_startofpacket (sysid_control_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sysid_control_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (sysid_control_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (sysid_control_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (sysid_control_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sysid_control_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sysid_control_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (100),
.PKT_ORI_BURST_SIZE_L (98),
.PKT_RESPONSE_STATUS_H (97),
.PKT_RESPONSE_STATUS_L (96),
.PKT_BURST_SIZE_H (75),
.PKT_BURST_SIZE_L (73),
.PKT_TRANS_LOCK (65),
.PKT_BEGIN_BURST (80),
.PKT_PROTECTION_H (91),
.PKT_PROTECTION_L (89),
.PKT_BURSTWRAP_H (72),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (67),
.PKT_ADDR_H (60),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (61),
.PKT_TRANS_POSTED (62),
.PKT_TRANS_WRITE (63),
.PKT_TRANS_READ (64),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (82),
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (85),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (8),
.ST_DATA_W (101),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) flash_epcs_control_port_agent (
.clk (pll_c0_clk), // clk.clk
.reset (flash_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (flash_epcs_control_port_agent_m0_address), // m0.address
.m0_burstcount (flash_epcs_control_port_agent_m0_burstcount), // .burstcount
.m0_byteenable (flash_epcs_control_port_agent_m0_byteenable), // .byteenable
.m0_debugaccess (flash_epcs_control_port_agent_m0_debugaccess), // .debugaccess
.m0_lock (flash_epcs_control_port_agent_m0_lock), // .lock
.m0_readdata (flash_epcs_control_port_agent_m0_readdata), // .readdata
.m0_readdatavalid (flash_epcs_control_port_agent_m0_readdatavalid), // .readdatavalid
.m0_read (flash_epcs_control_port_agent_m0_read), // .read
.m0_waitrequest (flash_epcs_control_port_agent_m0_waitrequest), // .waitrequest
.m0_writedata (flash_epcs_control_port_agent_m0_writedata), // .writedata
.m0_write (flash_epcs_control_port_agent_m0_write), // .write
.rp_endofpacket (flash_epcs_control_port_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (flash_epcs_control_port_agent_rp_ready), // .ready
.rp_valid (flash_epcs_control_port_agent_rp_valid), // .valid
.rp_data (flash_epcs_control_port_agent_rp_data), // .data
.rp_startofpacket (flash_epcs_control_port_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_002_src_ready), // cp.ready
.cp_valid (cmd_mux_002_src_valid), // .valid
.cp_data (cmd_mux_002_src_data), // .data
.cp_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_002_src_channel), // .channel
.rf_sink_ready (flash_epcs_control_port_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (flash_epcs_control_port_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (flash_epcs_control_port_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (flash_epcs_control_port_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (flash_epcs_control_port_agent_rsp_fifo_out_data), // .data
.rf_source_ready (flash_epcs_control_port_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (flash_epcs_control_port_agent_rf_source_valid), // .valid
.rf_source_startofpacket (flash_epcs_control_port_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (flash_epcs_control_port_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (flash_epcs_control_port_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (flash_epcs_control_port_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (flash_epcs_control_port_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (flash_epcs_control_port_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (flash_epcs_control_port_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (flash_epcs_control_port_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (flash_epcs_control_port_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (102),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) flash_epcs_control_port_agent_rsp_fifo (
.clk (pll_c0_clk), // clk.clk
.reset (flash_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (flash_epcs_control_port_agent_rf_source_data), // in.data
.in_valid (flash_epcs_control_port_agent_rf_source_valid), // .valid
.in_ready (flash_epcs_control_port_agent_rf_source_ready), // .ready
.in_startofpacket (flash_epcs_control_port_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (flash_epcs_control_port_agent_rf_source_endofpacket), // .endofpacket
.out_data (flash_epcs_control_port_agent_rsp_fifo_out_data), // out.data
.out_valid (flash_epcs_control_port_agent_rsp_fifo_out_valid), // .valid
.out_ready (flash_epcs_control_port_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (flash_epcs_control_port_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (flash_epcs_control_port_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (100),
.PKT_ORI_BURST_SIZE_L (98),
.PKT_RESPONSE_STATUS_H (97),
.PKT_RESPONSE_STATUS_L (96),
.PKT_BURST_SIZE_H (75),
.PKT_BURST_SIZE_L (73),
.PKT_TRANS_LOCK (65),
.PKT_BEGIN_BURST (80),
.PKT_PROTECTION_H (91),
.PKT_PROTECTION_L (89),
.PKT_BURSTWRAP_H (72),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (67),
.PKT_ADDR_H (60),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (61),
.PKT_TRANS_POSTED (62),
.PKT_TRANS_WRITE (63),
.PKT_TRANS_READ (64),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (82),
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (85),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (8),
.ST_DATA_W (101),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) cpu_jtag_debug_module_agent (
.clk (pll_c0_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (cpu_jtag_debug_module_agent_m0_address), // m0.address
.m0_burstcount (cpu_jtag_debug_module_agent_m0_burstcount), // .burstcount
.m0_byteenable (cpu_jtag_debug_module_agent_m0_byteenable), // .byteenable
.m0_debugaccess (cpu_jtag_debug_module_agent_m0_debugaccess), // .debugaccess
.m0_lock (cpu_jtag_debug_module_agent_m0_lock), // .lock
.m0_readdata (cpu_jtag_debug_module_agent_m0_readdata), // .readdata
.m0_readdatavalid (cpu_jtag_debug_module_agent_m0_readdatavalid), // .readdatavalid
.m0_read (cpu_jtag_debug_module_agent_m0_read), // .read
.m0_waitrequest (cpu_jtag_debug_module_agent_m0_waitrequest), // .waitrequest
.m0_writedata (cpu_jtag_debug_module_agent_m0_writedata), // .writedata
.m0_write (cpu_jtag_debug_module_agent_m0_write), // .write
.rp_endofpacket (cpu_jtag_debug_module_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (cpu_jtag_debug_module_agent_rp_ready), // .ready
.rp_valid (cpu_jtag_debug_module_agent_rp_valid), // .valid
.rp_data (cpu_jtag_debug_module_agent_rp_data), // .data
.rp_startofpacket (cpu_jtag_debug_module_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_003_src_ready), // cp.ready
.cp_valid (cmd_mux_003_src_valid), // .valid
.cp_data (cmd_mux_003_src_data), // .data
.cp_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_003_src_channel), // .channel
.rf_sink_ready (cpu_jtag_debug_module_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (cpu_jtag_debug_module_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (cpu_jtag_debug_module_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (cpu_jtag_debug_module_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (cpu_jtag_debug_module_agent_rsp_fifo_out_data), // .data
.rf_source_ready (cpu_jtag_debug_module_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (cpu_jtag_debug_module_agent_rf_source_valid), // .valid
.rf_source_startofpacket (cpu_jtag_debug_module_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (cpu_jtag_debug_module_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (cpu_jtag_debug_module_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (cpu_jtag_debug_module_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (cpu_jtag_debug_module_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (cpu_jtag_debug_module_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (cpu_jtag_debug_module_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (cpu_jtag_debug_module_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (cpu_jtag_debug_module_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (102),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) cpu_jtag_debug_module_agent_rsp_fifo (
.clk (pll_c0_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (cpu_jtag_debug_module_agent_rf_source_data), // in.data
.in_valid (cpu_jtag_debug_module_agent_rf_source_valid), // .valid
.in_ready (cpu_jtag_debug_module_agent_rf_source_ready), // .ready
.in_startofpacket (cpu_jtag_debug_module_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (cpu_jtag_debug_module_agent_rf_source_endofpacket), // .endofpacket
.out_data (cpu_jtag_debug_module_agent_rsp_fifo_out_data), // out.data
.out_valid (cpu_jtag_debug_module_agent_rsp_fifo_out_valid), // .valid
.out_ready (cpu_jtag_debug_module_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (cpu_jtag_debug_module_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (cpu_jtag_debug_module_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (100),
.PKT_ORI_BURST_SIZE_L (98),
.PKT_RESPONSE_STATUS_H (97),
.PKT_RESPONSE_STATUS_L (96),
.PKT_BURST_SIZE_H (75),
.PKT_BURST_SIZE_L (73),
.PKT_TRANS_LOCK (65),
.PKT_BEGIN_BURST (80),
.PKT_PROTECTION_H (91),
.PKT_PROTECTION_L (89),
.PKT_BURSTWRAP_H (72),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (67),
.PKT_ADDR_H (60),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (61),
.PKT_TRANS_POSTED (62),
.PKT_TRANS_WRITE (63),
.PKT_TRANS_READ (64),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (82),
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (85),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (8),
.ST_DATA_W (101),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) timer_s1_agent (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (timer_s1_agent_m0_address), // m0.address
.m0_burstcount (timer_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (timer_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (timer_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (timer_s1_agent_m0_lock), // .lock
.m0_readdata (timer_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (timer_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (timer_s1_agent_m0_read), // .read
.m0_waitrequest (timer_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (timer_s1_agent_m0_writedata), // .writedata
.m0_write (timer_s1_agent_m0_write), // .write
.rp_endofpacket (timer_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (timer_s1_agent_rp_ready), // .ready
.rp_valid (timer_s1_agent_rp_valid), // .valid
.rp_data (timer_s1_agent_rp_data), // .data
.rp_startofpacket (timer_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_004_src_ready), // cp.ready
.cp_valid (cmd_mux_004_src_valid), // .valid
.cp_data (cmd_mux_004_src_data), // .data
.cp_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_004_src_channel), // .channel
.rf_sink_ready (timer_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (timer_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (timer_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (timer_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (timer_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (timer_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (timer_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (timer_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (timer_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (timer_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (timer_s1_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (timer_s1_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (timer_s1_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (timer_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (timer_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (timer_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (102),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) timer_s1_agent_rsp_fifo (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (timer_s1_agent_rf_source_data), // in.data
.in_valid (timer_s1_agent_rf_source_valid), // .valid
.in_ready (timer_s1_agent_rf_source_ready), // .ready
.in_startofpacket (timer_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (timer_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (timer_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (timer_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (timer_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (timer_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (timer_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) timer_s1_agent_rdata_fifo (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (timer_s1_agent_rdata_fifo_src_data), // in.data
.in_valid (timer_s1_agent_rdata_fifo_src_valid), // .valid
.in_ready (timer_s1_agent_rdata_fifo_src_ready), // .ready
.out_data (timer_s1_agent_rdata_fifo_out_data), // out.data
.out_valid (timer_s1_agent_rdata_fifo_out_valid), // .valid
.out_ready (timer_s1_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (100),
.PKT_ORI_BURST_SIZE_L (98),
.PKT_RESPONSE_STATUS_H (97),
.PKT_RESPONSE_STATUS_L (96),
.PKT_BURST_SIZE_H (75),
.PKT_BURST_SIZE_L (73),
.PKT_TRANS_LOCK (65),
.PKT_BEGIN_BURST (80),
.PKT_PROTECTION_H (91),
.PKT_PROTECTION_L (89),
.PKT_BURSTWRAP_H (72),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (67),
.PKT_ADDR_H (60),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (61),
.PKT_TRANS_POSTED (62),
.PKT_TRANS_WRITE (63),
.PKT_TRANS_READ (64),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (82),
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (85),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (8),
.ST_DATA_W (101),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sw_s1_agent (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sw_s1_agent_m0_address), // m0.address
.m0_burstcount (sw_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (sw_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sw_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (sw_s1_agent_m0_lock), // .lock
.m0_readdata (sw_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (sw_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sw_s1_agent_m0_read), // .read
.m0_waitrequest (sw_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sw_s1_agent_m0_writedata), // .writedata
.m0_write (sw_s1_agent_m0_write), // .write
.rp_endofpacket (sw_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sw_s1_agent_rp_ready), // .ready
.rp_valid (sw_s1_agent_rp_valid), // .valid
.rp_data (sw_s1_agent_rp_data), // .data
.rp_startofpacket (sw_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_005_src_ready), // cp.ready
.cp_valid (cmd_mux_005_src_valid), // .valid
.cp_data (cmd_mux_005_src_data), // .data
.cp_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_005_src_channel), // .channel
.rf_sink_ready (sw_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sw_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sw_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sw_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sw_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sw_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sw_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sw_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sw_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sw_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sw_s1_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sw_s1_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (sw_s1_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (sw_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sw_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sw_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (102),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sw_s1_agent_rsp_fifo (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sw_s1_agent_rf_source_data), // in.data
.in_valid (sw_s1_agent_rf_source_valid), // .valid
.in_ready (sw_s1_agent_rf_source_ready), // .ready
.in_startofpacket (sw_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sw_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (sw_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (sw_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (sw_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sw_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sw_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sw_s1_agent_rdata_fifo (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sw_s1_agent_rdata_fifo_src_data), // in.data
.in_valid (sw_s1_agent_rdata_fifo_src_valid), // .valid
.in_ready (sw_s1_agent_rdata_fifo_src_ready), // .ready
.out_data (sw_s1_agent_rdata_fifo_out_data), // out.data
.out_valid (sw_s1_agent_rdata_fifo_out_valid), // .valid
.out_ready (sw_s1_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (100),
.PKT_ORI_BURST_SIZE_L (98),
.PKT_RESPONSE_STATUS_H (97),
.PKT_RESPONSE_STATUS_L (96),
.PKT_BURST_SIZE_H (75),
.PKT_BURST_SIZE_L (73),
.PKT_TRANS_LOCK (65),
.PKT_BEGIN_BURST (80),
.PKT_PROTECTION_H (91),
.PKT_PROTECTION_L (89),
.PKT_BURSTWRAP_H (72),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (67),
.PKT_ADDR_H (60),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (61),
.PKT_TRANS_POSTED (62),
.PKT_TRANS_WRITE (63),
.PKT_TRANS_READ (64),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (82),
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (85),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (8),
.ST_DATA_W (101),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) led_s1_agent (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (led_s1_agent_m0_address), // m0.address
.m0_burstcount (led_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (led_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (led_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (led_s1_agent_m0_lock), // .lock
.m0_readdata (led_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (led_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (led_s1_agent_m0_read), // .read
.m0_waitrequest (led_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (led_s1_agent_m0_writedata), // .writedata
.m0_write (led_s1_agent_m0_write), // .write
.rp_endofpacket (led_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (led_s1_agent_rp_ready), // .ready
.rp_valid (led_s1_agent_rp_valid), // .valid
.rp_data (led_s1_agent_rp_data), // .data
.rp_startofpacket (led_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_006_src_ready), // cp.ready
.cp_valid (cmd_mux_006_src_valid), // .valid
.cp_data (cmd_mux_006_src_data), // .data
.cp_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_006_src_channel), // .channel
.rf_sink_ready (led_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (led_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (led_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (led_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (led_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (led_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (led_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (led_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (led_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (led_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (led_s1_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (led_s1_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (led_s1_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (led_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (led_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (led_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (102),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) led_s1_agent_rsp_fifo (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (led_s1_agent_rf_source_data), // in.data
.in_valid (led_s1_agent_rf_source_valid), // .valid
.in_ready (led_s1_agent_rf_source_ready), // .ready
.in_startofpacket (led_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (led_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (led_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (led_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (led_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (led_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (led_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) led_s1_agent_rdata_fifo (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (led_s1_agent_rdata_fifo_src_data), // in.data
.in_valid (led_s1_agent_rdata_fifo_src_valid), // .valid
.in_ready (led_s1_agent_rdata_fifo_src_ready), // .ready
.out_data (led_s1_agent_rdata_fifo_out_data), // out.data
.out_valid (led_s1_agent_rdata_fifo_out_valid), // .valid
.out_ready (led_s1_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (82),
.PKT_ORI_BURST_SIZE_L (80),
.PKT_RESPONSE_STATUS_H (79),
.PKT_RESPONSE_STATUS_L (78),
.PKT_BURST_SIZE_H (57),
.PKT_BURST_SIZE_L (55),
.PKT_TRANS_LOCK (47),
.PKT_BEGIN_BURST (62),
.PKT_PROTECTION_H (73),
.PKT_PROTECTION_L (71),
.PKT_BURSTWRAP_H (54),
.PKT_BURSTWRAP_L (52),
.PKT_BYTE_CNT_H (51),
.PKT_BYTE_CNT_L (49),
.PKT_ADDR_H (42),
.PKT_ADDR_L (18),
.PKT_TRANS_COMPRESSED_READ (43),
.PKT_TRANS_POSTED (44),
.PKT_TRANS_WRITE (45),
.PKT_TRANS_READ (46),
.PKT_DATA_H (15),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_SRC_ID_H (66),
.PKT_SRC_ID_L (64),
.PKT_DEST_ID_H (69),
.PKT_DEST_ID_L (67),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (8),
.ST_DATA_W (83),
.AVS_BURSTCOUNT_W (2),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sdram_s1_agent (
.clk (pll_c0_clk), // clk.clk
.reset (flash_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sdram_s1_agent_m0_address), // m0.address
.m0_burstcount (sdram_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (sdram_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sdram_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (sdram_s1_agent_m0_lock), // .lock
.m0_readdata (sdram_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (sdram_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sdram_s1_agent_m0_read), // .read
.m0_waitrequest (sdram_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sdram_s1_agent_m0_writedata), // .writedata
.m0_write (sdram_s1_agent_m0_write), // .write
.rp_endofpacket (sdram_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sdram_s1_agent_rp_ready), // .ready
.rp_valid (sdram_s1_agent_rp_valid), // .valid
.rp_data (sdram_s1_agent_rp_data), // .data
.rp_startofpacket (sdram_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (sdram_s1_burst_adapter_source0_ready), // cp.ready
.cp_valid (sdram_s1_burst_adapter_source0_valid), // .valid
.cp_data (sdram_s1_burst_adapter_source0_data), // .data
.cp_startofpacket (sdram_s1_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (sdram_s1_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (sdram_s1_burst_adapter_source0_channel), // .channel
.rf_sink_ready (sdram_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sdram_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sdram_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sdram_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sdram_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sdram_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sdram_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sdram_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sdram_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sdram_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sdram_s1_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sdram_s1_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (sdram_s1_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (sdram_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sdram_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sdram_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (84),
.FIFO_DEPTH (8),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sdram_s1_agent_rsp_fifo (
.clk (pll_c0_clk), // clk.clk
.reset (flash_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sdram_s1_agent_rf_source_data), // in.data
.in_valid (sdram_s1_agent_rf_source_valid), // .valid
.in_ready (sdram_s1_agent_rf_source_ready), // .ready
.in_startofpacket (sdram_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sdram_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (sdram_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (sdram_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (sdram_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sdram_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sdram_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (18),
.FIFO_DEPTH (8),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (3),
.USE_MEMORY_BLOCKS (1),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sdram_s1_agent_rdata_fifo (
.clk (pll_c0_clk), // clk.clk
.reset (flash_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sdram_s1_agent_rdata_fifo_src_data), // in.data
.in_valid (sdram_s1_agent_rdata_fifo_src_valid), // .valid
.in_ready (sdram_s1_agent_rdata_fifo_src_ready), // .ready
.out_data (sdram_s1_agent_rdata_fifo_out_data), // out.data
.out_valid (sdram_s1_agent_rdata_fifo_out_valid), // .valid
.out_ready (sdram_s1_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
mi_nios_mm_interconnect_0_router router (
.sink_ready (cpu_data_master_agent_cp_ready), // sink.ready
.sink_valid (cpu_data_master_agent_cp_valid), // .valid
.sink_data (cpu_data_master_agent_cp_data), // .data
.sink_startofpacket (cpu_data_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_data_master_agent_cp_endofpacket), // .endofpacket
.clk (pll_c0_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_router_001 router_001 (
.sink_ready (cpu_instruction_master_agent_cp_ready), // sink.ready
.sink_valid (cpu_instruction_master_agent_cp_valid), // .valid
.sink_data (cpu_instruction_master_agent_cp_data), // .data
.sink_startofpacket (cpu_instruction_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_instruction_master_agent_cp_endofpacket), // .endofpacket
.clk (pll_c0_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_router_002 router_002 (
.sink_ready (jtag_avalon_jtag_slave_agent_rp_ready), // sink.ready
.sink_valid (jtag_avalon_jtag_slave_agent_rp_valid), // .valid
.sink_data (jtag_avalon_jtag_slave_agent_rp_data), // .data
.sink_startofpacket (jtag_avalon_jtag_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (jtag_avalon_jtag_slave_agent_rp_endofpacket), // .endofpacket
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_router_002 router_003 (
.sink_ready (sysid_control_slave_agent_rp_ready), // sink.ready
.sink_valid (sysid_control_slave_agent_rp_valid), // .valid
.sink_data (sysid_control_slave_agent_rp_data), // .data
.sink_startofpacket (sysid_control_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sysid_control_slave_agent_rp_endofpacket), // .endofpacket
.clk (pll_c0_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_router_004 router_004 (
.sink_ready (flash_epcs_control_port_agent_rp_ready), // sink.ready
.sink_valid (flash_epcs_control_port_agent_rp_valid), // .valid
.sink_data (flash_epcs_control_port_agent_rp_data), // .data
.sink_startofpacket (flash_epcs_control_port_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (flash_epcs_control_port_agent_rp_endofpacket), // .endofpacket
.clk (pll_c0_clk), // clk.clk
.reset (flash_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_router_004 router_005 (
.sink_ready (cpu_jtag_debug_module_agent_rp_ready), // sink.ready
.sink_valid (cpu_jtag_debug_module_agent_rp_valid), // .valid
.sink_data (cpu_jtag_debug_module_agent_rp_data), // .data
.sink_startofpacket (cpu_jtag_debug_module_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_jtag_debug_module_agent_rp_endofpacket), // .endofpacket
.clk (pll_c0_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_005_src_ready), // src.ready
.src_valid (router_005_src_valid), // .valid
.src_data (router_005_src_data), // .data
.src_channel (router_005_src_channel), // .channel
.src_startofpacket (router_005_src_startofpacket), // .startofpacket
.src_endofpacket (router_005_src_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_router_002 router_006 (
.sink_ready (timer_s1_agent_rp_ready), // sink.ready
.sink_valid (timer_s1_agent_rp_valid), // .valid
.sink_data (timer_s1_agent_rp_data), // .data
.sink_startofpacket (timer_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (timer_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_006_src_ready), // src.ready
.src_valid (router_006_src_valid), // .valid
.src_data (router_006_src_data), // .data
.src_channel (router_006_src_channel), // .channel
.src_startofpacket (router_006_src_startofpacket), // .startofpacket
.src_endofpacket (router_006_src_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_router_002 router_007 (
.sink_ready (sw_s1_agent_rp_ready), // sink.ready
.sink_valid (sw_s1_agent_rp_valid), // .valid
.sink_data (sw_s1_agent_rp_data), // .data
.sink_startofpacket (sw_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sw_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_007_src_ready), // src.ready
.src_valid (router_007_src_valid), // .valid
.src_data (router_007_src_data), // .data
.src_channel (router_007_src_channel), // .channel
.src_startofpacket (router_007_src_startofpacket), // .startofpacket
.src_endofpacket (router_007_src_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_router_002 router_008 (
.sink_ready (led_s1_agent_rp_ready), // sink.ready
.sink_valid (led_s1_agent_rp_valid), // .valid
.sink_data (led_s1_agent_rp_data), // .data
.sink_startofpacket (led_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (led_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_008_src_ready), // src.ready
.src_valid (router_008_src_valid), // .valid
.src_data (router_008_src_data), // .data
.src_channel (router_008_src_channel), // .channel
.src_startofpacket (router_008_src_startofpacket), // .startofpacket
.src_endofpacket (router_008_src_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_router_009 router_009 (
.sink_ready (sdram_s1_agent_rp_ready), // sink.ready
.sink_valid (sdram_s1_agent_rp_valid), // .valid
.sink_data (sdram_s1_agent_rp_data), // .data
.sink_startofpacket (sdram_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sdram_s1_agent_rp_endofpacket), // .endofpacket
.clk (pll_c0_clk), // clk.clk
.reset (flash_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_009_src_ready), // src.ready
.src_valid (router_009_src_valid), // .valid
.src_data (router_009_src_data), // .data
.src_channel (router_009_src_channel), // .channel
.src_startofpacket (router_009_src_startofpacket), // .startofpacket
.src_endofpacket (router_009_src_endofpacket) // .endofpacket
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (42),
.PKT_ADDR_L (18),
.PKT_BEGIN_BURST (62),
.PKT_BYTE_CNT_H (51),
.PKT_BYTE_CNT_L (49),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_BURST_SIZE_H (57),
.PKT_BURST_SIZE_L (55),
.PKT_BURST_TYPE_H (59),
.PKT_BURST_TYPE_L (58),
.PKT_BURSTWRAP_H (54),
.PKT_BURSTWRAP_L (52),
.PKT_TRANS_COMPRESSED_READ (43),
.PKT_TRANS_WRITE (45),
.PKT_TRANS_READ (46),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (0),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (83),
.ST_CHANNEL_W (8),
.OUT_BYTE_CNT_H (50),
.OUT_BURSTWRAP_H (54),
.COMPRESSED_READ_SUPPORT (0),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (3),
.BURSTWRAP_CONST_VALUE (3),
.ADAPTER_VERSION ("13.1")
) sdram_s1_burst_adapter (
.clk (pll_c0_clk), // cr0.clk
.reset (flash_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (sdram_s1_cmd_width_adapter_src_valid), // sink0.valid
.sink0_data (sdram_s1_cmd_width_adapter_src_data), // .data
.sink0_channel (sdram_s1_cmd_width_adapter_src_channel), // .channel
.sink0_startofpacket (sdram_s1_cmd_width_adapter_src_startofpacket), // .startofpacket
.sink0_endofpacket (sdram_s1_cmd_width_adapter_src_endofpacket), // .endofpacket
.sink0_ready (sdram_s1_cmd_width_adapter_src_ready), // .ready
.source0_valid (sdram_s1_burst_adapter_source0_valid), // source0.valid
.source0_data (sdram_s1_burst_adapter_source0_data), // .data
.source0_channel (sdram_s1_burst_adapter_source0_channel), // .channel
.source0_startofpacket (sdram_s1_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (sdram_s1_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (sdram_s1_burst_adapter_source0_ready) // .ready
);
mi_nios_mm_interconnect_0_cmd_demux cmd_demux (
.clk (pll_c0_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_src_ready), // sink.ready
.sink_channel (router_src_channel), // .channel
.sink_data (router_src_data), // .data
.sink_startofpacket (router_src_startofpacket), // .startofpacket
.sink_endofpacket (router_src_endofpacket), // .endofpacket
.sink_valid (router_src_valid), // .valid
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_src1_ready), // src1.ready
.src1_valid (cmd_demux_src1_valid), // .valid
.src1_data (cmd_demux_src1_data), // .data
.src1_channel (cmd_demux_src1_channel), // .channel
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_src2_ready), // src2.ready
.src2_valid (cmd_demux_src2_valid), // .valid
.src2_data (cmd_demux_src2_data), // .data
.src2_channel (cmd_demux_src2_channel), // .channel
.src2_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_src3_ready), // src3.ready
.src3_valid (cmd_demux_src3_valid), // .valid
.src3_data (cmd_demux_src3_data), // .data
.src3_channel (cmd_demux_src3_channel), // .channel
.src3_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_src3_endofpacket), // .endofpacket
.src4_ready (cmd_demux_src4_ready), // src4.ready
.src4_valid (cmd_demux_src4_valid), // .valid
.src4_data (cmd_demux_src4_data), // .data
.src4_channel (cmd_demux_src4_channel), // .channel
.src4_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_demux_src4_endofpacket), // .endofpacket
.src5_ready (cmd_demux_src5_ready), // src5.ready
.src5_valid (cmd_demux_src5_valid), // .valid
.src5_data (cmd_demux_src5_data), // .data
.src5_channel (cmd_demux_src5_channel), // .channel
.src5_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_demux_src5_endofpacket), // .endofpacket
.src6_ready (cmd_demux_src6_ready), // src6.ready
.src6_valid (cmd_demux_src6_valid), // .valid
.src6_data (cmd_demux_src6_data), // .data
.src6_channel (cmd_demux_src6_channel), // .channel
.src6_startofpacket (cmd_demux_src6_startofpacket), // .startofpacket
.src6_endofpacket (cmd_demux_src6_endofpacket), // .endofpacket
.src7_ready (cmd_demux_src7_ready), // src7.ready
.src7_valid (cmd_demux_src7_valid), // .valid
.src7_data (cmd_demux_src7_data), // .data
.src7_channel (cmd_demux_src7_channel), // .channel
.src7_startofpacket (cmd_demux_src7_startofpacket), // .startofpacket
.src7_endofpacket (cmd_demux_src7_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_cmd_demux_001 cmd_demux_001 (
.clk (pll_c0_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_001_src_ready), // sink.ready
.sink_channel (router_001_src_channel), // .channel
.sink_data (router_001_src_data), // .data
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.sink_valid (router_001_src_valid), // .valid
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_demux_001_src1_valid), // .valid
.src1_data (cmd_demux_001_src1_data), // .data
.src1_channel (cmd_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_001_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_001_src2_ready), // src2.ready
.src2_valid (cmd_demux_001_src2_valid), // .valid
.src2_data (cmd_demux_001_src2_data), // .data
.src2_channel (cmd_demux_001_src2_channel), // .channel
.src2_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_001_src2_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_cmd_mux cmd_mux (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (crosser_out_ready), // sink0.ready
.sink0_valid (crosser_out_valid), // .valid
.sink0_channel (crosser_out_channel), // .channel
.sink0_data (crosser_out_data), // .data
.sink0_startofpacket (crosser_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_out_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_cmd_mux cmd_mux_001 (
.clk (pll_c0_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_demux_src1_valid), // .valid
.sink0_channel (cmd_demux_src1_channel), // .channel
.sink0_data (cmd_demux_src1_data), // .data
.sink0_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src1_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_cmd_mux_002 cmd_mux_002 (
.clk (pll_c0_clk), // clk.clk
.reset (flash_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_src2_valid), // .valid
.sink0_channel (cmd_demux_src2_channel), // .channel
.sink0_data (cmd_demux_src2_data), // .data
.sink0_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src0_valid), // .valid
.sink1_channel (cmd_demux_001_src0_channel), // .channel
.sink1_data (cmd_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_cmd_mux_002 cmd_mux_003 (
.clk (pll_c0_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_003_src_ready), // src.ready
.src_valid (cmd_mux_003_src_valid), // .valid
.src_data (cmd_mux_003_src_data), // .data
.src_channel (cmd_mux_003_src_channel), // .channel
.src_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src3_ready), // sink0.ready
.sink0_valid (cmd_demux_src3_valid), // .valid
.sink0_channel (cmd_demux_src3_channel), // .channel
.sink0_data (cmd_demux_src3_data), // .data
.sink0_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src3_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src1_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src1_valid), // .valid
.sink1_channel (cmd_demux_001_src1_channel), // .channel
.sink1_data (cmd_demux_001_src1_data), // .data
.sink1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src1_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_cmd_mux cmd_mux_004 (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_004_src_ready), // src.ready
.src_valid (cmd_mux_004_src_valid), // .valid
.src_data (cmd_mux_004_src_data), // .data
.src_channel (cmd_mux_004_src_channel), // .channel
.src_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (crosser_001_out_ready), // sink0.ready
.sink0_valid (crosser_001_out_valid), // .valid
.sink0_channel (crosser_001_out_channel), // .channel
.sink0_data (crosser_001_out_data), // .data
.sink0_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_001_out_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_cmd_mux cmd_mux_005 (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_005_src_ready), // src.ready
.src_valid (cmd_mux_005_src_valid), // .valid
.src_data (cmd_mux_005_src_data), // .data
.src_channel (cmd_mux_005_src_channel), // .channel
.src_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.sink0_ready (crosser_002_out_ready), // sink0.ready
.sink0_valid (crosser_002_out_valid), // .valid
.sink0_channel (crosser_002_out_channel), // .channel
.sink0_data (crosser_002_out_data), // .data
.sink0_startofpacket (crosser_002_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_002_out_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_cmd_mux cmd_mux_006 (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_006_src_ready), // src.ready
.src_valid (cmd_mux_006_src_valid), // .valid
.src_data (cmd_mux_006_src_data), // .data
.src_channel (cmd_mux_006_src_channel), // .channel
.src_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
.sink0_ready (crosser_003_out_ready), // sink0.ready
.sink0_valid (crosser_003_out_valid), // .valid
.sink0_channel (crosser_003_out_channel), // .channel
.sink0_data (crosser_003_out_data), // .data
.sink0_startofpacket (crosser_003_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_003_out_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_cmd_mux_002 cmd_mux_007 (
.clk (pll_c0_clk), // clk.clk
.reset (flash_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_007_src_ready), // src.ready
.src_valid (cmd_mux_007_src_valid), // .valid
.src_data (cmd_mux_007_src_data), // .data
.src_channel (cmd_mux_007_src_channel), // .channel
.src_startofpacket (cmd_mux_007_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_007_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src7_ready), // sink0.ready
.sink0_valid (cmd_demux_src7_valid), // .valid
.sink0_channel (cmd_demux_src7_channel), // .channel
.sink0_data (cmd_demux_src7_data), // .data
.sink0_startofpacket (cmd_demux_src7_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src7_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src2_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src2_valid), // .valid
.sink1_channel (cmd_demux_001_src2_channel), // .channel
.sink1_data (cmd_demux_001_src2_data), // .data
.sink1_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src2_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_rsp_demux rsp_demux (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_002_src_ready), // sink.ready
.sink_channel (router_002_src_channel), // .channel
.sink_data (router_002_src_data), // .data
.sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.sink_valid (router_002_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_rsp_demux_001 rsp_demux_001 (
.clk (pll_c0_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_003_src_ready), // sink.ready
.sink_channel (router_003_src_channel), // .channel
.sink_data (router_003_src_data), // .data
.sink_startofpacket (router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (router_003_src_endofpacket), // .endofpacket
.sink_valid (router_003_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_rsp_demux_002 rsp_demux_002 (
.clk (pll_c0_clk), // clk.clk
.reset (flash_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_004_src_ready), // sink.ready
.sink_channel (router_004_src_channel), // .channel
.sink_data (router_004_src_data), // .data
.sink_startofpacket (router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (router_004_src_endofpacket), // .endofpacket
.sink_valid (router_004_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_002_src1_ready), // src1.ready
.src1_valid (rsp_demux_002_src1_valid), // .valid
.src1_data (rsp_demux_002_src1_data), // .data
.src1_channel (rsp_demux_002_src1_channel), // .channel
.src1_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_002_src1_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_rsp_demux_002 rsp_demux_003 (
.clk (pll_c0_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_005_src_ready), // sink.ready
.sink_channel (router_005_src_channel), // .channel
.sink_data (router_005_src_data), // .data
.sink_startofpacket (router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (router_005_src_endofpacket), // .endofpacket
.sink_valid (router_005_src_valid), // .valid
.src0_ready (rsp_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_demux_003_src0_valid), // .valid
.src0_data (rsp_demux_003_src0_data), // .data
.src0_channel (rsp_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_003_src1_ready), // src1.ready
.src1_valid (rsp_demux_003_src1_valid), // .valid
.src1_data (rsp_demux_003_src1_data), // .data
.src1_channel (rsp_demux_003_src1_channel), // .channel
.src1_startofpacket (rsp_demux_003_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_003_src1_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_rsp_demux rsp_demux_004 (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_006_src_ready), // sink.ready
.sink_channel (router_006_src_channel), // .channel
.sink_data (router_006_src_data), // .data
.sink_startofpacket (router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (router_006_src_endofpacket), // .endofpacket
.sink_valid (router_006_src_valid), // .valid
.src0_ready (rsp_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_demux_004_src0_valid), // .valid
.src0_data (rsp_demux_004_src0_data), // .data
.src0_channel (rsp_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_004_src0_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_rsp_demux rsp_demux_005 (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_007_src_ready), // sink.ready
.sink_channel (router_007_src_channel), // .channel
.sink_data (router_007_src_data), // .data
.sink_startofpacket (router_007_src_startofpacket), // .startofpacket
.sink_endofpacket (router_007_src_endofpacket), // .endofpacket
.sink_valid (router_007_src_valid), // .valid
.src0_ready (rsp_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_demux_005_src0_valid), // .valid
.src0_data (rsp_demux_005_src0_data), // .data
.src0_channel (rsp_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_005_src0_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_rsp_demux rsp_demux_006 (
.clk (clk_50_clk_clk), // clk.clk
.reset (jtag_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_008_src_ready), // sink.ready
.sink_channel (router_008_src_channel), // .channel
.sink_data (router_008_src_data), // .data
.sink_startofpacket (router_008_src_startofpacket), // .startofpacket
.sink_endofpacket (router_008_src_endofpacket), // .endofpacket
.sink_valid (router_008_src_valid), // .valid
.src0_ready (rsp_demux_006_src0_ready), // src0.ready
.src0_valid (rsp_demux_006_src0_valid), // .valid
.src0_data (rsp_demux_006_src0_data), // .data
.src0_channel (rsp_demux_006_src0_channel), // .channel
.src0_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_006_src0_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_rsp_demux_002 rsp_demux_007 (
.clk (pll_c0_clk), // clk.clk
.reset (flash_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (sdram_s1_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (sdram_s1_rsp_width_adapter_src_channel), // .channel
.sink_data (sdram_s1_rsp_width_adapter_src_data), // .data
.sink_startofpacket (sdram_s1_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (sdram_s1_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (sdram_s1_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_007_src0_ready), // src0.ready
.src0_valid (rsp_demux_007_src0_valid), // .valid
.src0_data (rsp_demux_007_src0_data), // .data
.src0_channel (rsp_demux_007_src0_channel), // .channel
.src0_startofpacket (rsp_demux_007_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_007_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_007_src1_ready), // src1.ready
.src1_valid (rsp_demux_007_src1_valid), // .valid
.src1_data (rsp_demux_007_src1_data), // .data
.src1_channel (rsp_demux_007_src1_channel), // .channel
.src1_startofpacket (rsp_demux_007_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_007_src1_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_rsp_mux rsp_mux (
.clk (pll_c0_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (crosser_004_out_ready), // sink0.ready
.sink0_valid (crosser_004_out_valid), // .valid
.sink0_channel (crosser_004_out_channel), // .channel
.sink0_data (crosser_004_out_data), // .data
.sink0_startofpacket (crosser_004_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_004_out_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src0_valid), // .valid
.sink1_channel (rsp_demux_001_src0_channel), // .channel
.sink1_data (rsp_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src0_valid), // .valid
.sink2_channel (rsp_demux_002_src0_channel), // .channel
.sink2_data (rsp_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_demux_003_src0_valid), // .valid
.sink3_channel (rsp_demux_003_src0_channel), // .channel
.sink3_data (rsp_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
.sink4_ready (crosser_005_out_ready), // sink4.ready
.sink4_valid (crosser_005_out_valid), // .valid
.sink4_channel (crosser_005_out_channel), // .channel
.sink4_data (crosser_005_out_data), // .data
.sink4_startofpacket (crosser_005_out_startofpacket), // .startofpacket
.sink4_endofpacket (crosser_005_out_endofpacket), // .endofpacket
.sink5_ready (crosser_006_out_ready), // sink5.ready
.sink5_valid (crosser_006_out_valid), // .valid
.sink5_channel (crosser_006_out_channel), // .channel
.sink5_data (crosser_006_out_data), // .data
.sink5_startofpacket (crosser_006_out_startofpacket), // .startofpacket
.sink5_endofpacket (crosser_006_out_endofpacket), // .endofpacket
.sink6_ready (crosser_007_out_ready), // sink6.ready
.sink6_valid (crosser_007_out_valid), // .valid
.sink6_channel (crosser_007_out_channel), // .channel
.sink6_data (crosser_007_out_data), // .data
.sink6_startofpacket (crosser_007_out_startofpacket), // .startofpacket
.sink6_endofpacket (crosser_007_out_endofpacket), // .endofpacket
.sink7_ready (rsp_demux_007_src0_ready), // sink7.ready
.sink7_valid (rsp_demux_007_src0_valid), // .valid
.sink7_channel (rsp_demux_007_src0_channel), // .channel
.sink7_data (rsp_demux_007_src0_data), // .data
.sink7_startofpacket (rsp_demux_007_src0_startofpacket), // .startofpacket
.sink7_endofpacket (rsp_demux_007_src0_endofpacket) // .endofpacket
);
mi_nios_mm_interconnect_0_rsp_mux_001 rsp_mux_001 (
.clk (pll_c0_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_002_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_002_src1_valid), // .valid
.sink0_channel (rsp_demux_002_src1_channel), // .channel
.sink0_data (rsp_demux_002_src1_data), // .data
.sink0_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_002_src1_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_003_src1_ready), // sink1.ready
.sink1_valid (rsp_demux_003_src1_valid), // .valid
.sink1_channel (rsp_demux_003_src1_channel), // .channel
.sink1_data (rsp_demux_003_src1_data), // .data
.sink1_startofpacket (rsp_demux_003_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_003_src1_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_007_src1_ready), // sink2.ready
.sink2_valid (rsp_demux_007_src1_valid), // .valid
.sink2_channel (rsp_demux_007_src1_channel), // .channel
.sink2_data (rsp_demux_007_src1_data), // .data
.sink2_startofpacket (rsp_demux_007_src1_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_007_src1_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (42),
.IN_PKT_ADDR_L (18),
.IN_PKT_DATA_H (15),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (17),
.IN_PKT_BYTEEN_L (16),
.IN_PKT_BYTE_CNT_H (51),
.IN_PKT_BYTE_CNT_L (49),
.IN_PKT_TRANS_COMPRESSED_READ (43),
.IN_PKT_BURSTWRAP_H (54),
.IN_PKT_BURSTWRAP_L (52),
.IN_PKT_BURST_SIZE_H (57),
.IN_PKT_BURST_SIZE_L (55),
.IN_PKT_RESPONSE_STATUS_H (79),
.IN_PKT_RESPONSE_STATUS_L (78),
.IN_PKT_TRANS_EXCLUSIVE (48),
.IN_PKT_BURST_TYPE_H (59),
.IN_PKT_BURST_TYPE_L (58),
.IN_PKT_ORI_BURST_SIZE_L (80),
.IN_PKT_ORI_BURST_SIZE_H (82),
.IN_ST_DATA_W (83),
.OUT_PKT_ADDR_H (60),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (69),
.OUT_PKT_BYTE_CNT_L (67),
.OUT_PKT_TRANS_COMPRESSED_READ (61),
.OUT_PKT_BURST_SIZE_H (75),
.OUT_PKT_BURST_SIZE_L (73),
.OUT_PKT_RESPONSE_STATUS_H (97),
.OUT_PKT_RESPONSE_STATUS_L (96),
.OUT_PKT_TRANS_EXCLUSIVE (66),
.OUT_PKT_BURST_TYPE_H (77),
.OUT_PKT_BURST_TYPE_L (76),
.OUT_PKT_ORI_BURST_SIZE_L (98),
.OUT_PKT_ORI_BURST_SIZE_H (100),
.OUT_ST_DATA_W (101),
.ST_CHANNEL_W (8),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sdram_s1_rsp_width_adapter (
.clk (pll_c0_clk), // clk.clk
.reset (flash_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_009_src_valid), // sink.valid
.in_channel (router_009_src_channel), // .channel
.in_startofpacket (router_009_src_startofpacket), // .startofpacket
.in_endofpacket (router_009_src_endofpacket), // .endofpacket
.in_ready (router_009_src_ready), // .ready
.in_data (router_009_src_data), // .data
.out_endofpacket (sdram_s1_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sdram_s1_rsp_width_adapter_src_data), // .data
.out_channel (sdram_s1_rsp_width_adapter_src_channel), // .channel
.out_valid (sdram_s1_rsp_width_adapter_src_valid), // .valid
.out_ready (sdram_s1_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (sdram_s1_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (60),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (69),
.IN_PKT_BYTE_CNT_L (67),
.IN_PKT_TRANS_COMPRESSED_READ (61),
.IN_PKT_BURSTWRAP_H (72),
.IN_PKT_BURSTWRAP_L (70),
.IN_PKT_BURST_SIZE_H (75),
.IN_PKT_BURST_SIZE_L (73),
.IN_PKT_RESPONSE_STATUS_H (97),
.IN_PKT_RESPONSE_STATUS_L (96),
.IN_PKT_TRANS_EXCLUSIVE (66),
.IN_PKT_BURST_TYPE_H (77),
.IN_PKT_BURST_TYPE_L (76),
.IN_PKT_ORI_BURST_SIZE_L (98),
.IN_PKT_ORI_BURST_SIZE_H (100),
.IN_ST_DATA_W (101),
.OUT_PKT_ADDR_H (42),
.OUT_PKT_ADDR_L (18),
.OUT_PKT_DATA_H (15),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (17),
.OUT_PKT_BYTEEN_L (16),
.OUT_PKT_BYTE_CNT_H (51),
.OUT_PKT_BYTE_CNT_L (49),
.OUT_PKT_TRANS_COMPRESSED_READ (43),
.OUT_PKT_BURST_SIZE_H (57),
.OUT_PKT_BURST_SIZE_L (55),
.OUT_PKT_RESPONSE_STATUS_H (79),
.OUT_PKT_RESPONSE_STATUS_L (78),
.OUT_PKT_TRANS_EXCLUSIVE (48),
.OUT_PKT_BURST_TYPE_H (59),
.OUT_PKT_BURST_TYPE_L (58),
.OUT_PKT_ORI_BURST_SIZE_L (80),
.OUT_PKT_ORI_BURST_SIZE_H (82),
.OUT_ST_DATA_W (83),
.ST_CHANNEL_W (8),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sdram_s1_cmd_width_adapter (
.clk (pll_c0_clk), // clk.clk
.reset (flash_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_007_src_valid), // sink.valid
.in_channel (cmd_mux_007_src_channel), // .channel
.in_startofpacket (cmd_mux_007_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_007_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_007_src_ready), // .ready
.in_data (cmd_mux_007_src_data), // .data
.out_endofpacket (sdram_s1_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sdram_s1_cmd_width_adapter_src_data), // .data
.out_channel (sdram_s1_cmd_width_adapter_src_channel), // .channel
.out_valid (sdram_s1_cmd_width_adapter_src_valid), // .valid
.out_ready (sdram_s1_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (sdram_s1_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (101),
.BITS_PER_SYMBOL (101),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (8),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser (
.in_clk (pll_c0_clk), // in_clk.clk
.in_reset (cpu_reset_n_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_50_clk_clk), // out_clk.clk
.out_reset (jtag_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_demux_src0_ready), // in.ready
.in_valid (cmd_demux_src0_valid), // .valid
.in_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.in_channel (cmd_demux_src0_channel), // .channel
.in_data (cmd_demux_src0_data), // .data
.out_ready (crosser_out_ready), // out.ready
.out_valid (crosser_out_valid), // .valid
.out_startofpacket (crosser_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_out_endofpacket), // .endofpacket
.out_channel (crosser_out_channel), // .channel
.out_data (crosser_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (101),
.BITS_PER_SYMBOL (101),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (8),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_001 (
.in_clk (pll_c0_clk), // in_clk.clk
.in_reset (cpu_reset_n_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_50_clk_clk), // out_clk.clk
.out_reset (jtag_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_demux_src4_ready), // in.ready
.in_valid (cmd_demux_src4_valid), // .valid
.in_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_src4_endofpacket), // .endofpacket
.in_channel (cmd_demux_src4_channel), // .channel
.in_data (cmd_demux_src4_data), // .data
.out_ready (crosser_001_out_ready), // out.ready
.out_valid (crosser_001_out_valid), // .valid
.out_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_001_out_endofpacket), // .endofpacket
.out_channel (crosser_001_out_channel), // .channel
.out_data (crosser_001_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (101),
.BITS_PER_SYMBOL (101),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (8),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_002 (
.in_clk (pll_c0_clk), // in_clk.clk
.in_reset (cpu_reset_n_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_50_clk_clk), // out_clk.clk
.out_reset (jtag_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_demux_src5_ready), // in.ready
.in_valid (cmd_demux_src5_valid), // .valid
.in_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_src5_endofpacket), // .endofpacket
.in_channel (cmd_demux_src5_channel), // .channel
.in_data (cmd_demux_src5_data), // .data
.out_ready (crosser_002_out_ready), // out.ready
.out_valid (crosser_002_out_valid), // .valid
.out_startofpacket (crosser_002_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_002_out_endofpacket), // .endofpacket
.out_channel (crosser_002_out_channel), // .channel
.out_data (crosser_002_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (101),
.BITS_PER_SYMBOL (101),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (8),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_003 (
.in_clk (pll_c0_clk), // in_clk.clk
.in_reset (cpu_reset_n_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_50_clk_clk), // out_clk.clk
.out_reset (jtag_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_demux_src6_ready), // in.ready
.in_valid (cmd_demux_src6_valid), // .valid
.in_startofpacket (cmd_demux_src6_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_src6_endofpacket), // .endofpacket
.in_channel (cmd_demux_src6_channel), // .channel
.in_data (cmd_demux_src6_data), // .data
.out_ready (crosser_003_out_ready), // out.ready
.out_valid (crosser_003_out_valid), // .valid
.out_startofpacket (crosser_003_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_003_out_endofpacket), // .endofpacket
.out_channel (crosser_003_out_channel), // .channel
.out_data (crosser_003_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (101),
.BITS_PER_SYMBOL (101),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (8),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_004 (
.in_clk (clk_50_clk_clk), // in_clk.clk
.in_reset (jtag_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (pll_c0_clk), // out_clk.clk
.out_reset (cpu_reset_n_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_demux_src0_ready), // in.ready
.in_valid (rsp_demux_src0_valid), // .valid
.in_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.in_channel (rsp_demux_src0_channel), // .channel
.in_data (rsp_demux_src0_data), // .data
.out_ready (crosser_004_out_ready), // out.ready
.out_valid (crosser_004_out_valid), // .valid
.out_startofpacket (crosser_004_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_004_out_endofpacket), // .endofpacket
.out_channel (crosser_004_out_channel), // .channel
.out_data (crosser_004_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (101),
.BITS_PER_SYMBOL (101),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (8),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_005 (
.in_clk (clk_50_clk_clk), // in_clk.clk
.in_reset (jtag_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (pll_c0_clk), // out_clk.clk
.out_reset (cpu_reset_n_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_demux_004_src0_ready), // in.ready
.in_valid (rsp_demux_004_src0_valid), // .valid
.in_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_004_src0_endofpacket), // .endofpacket
.in_channel (rsp_demux_004_src0_channel), // .channel
.in_data (rsp_demux_004_src0_data), // .data
.out_ready (crosser_005_out_ready), // out.ready
.out_valid (crosser_005_out_valid), // .valid
.out_startofpacket (crosser_005_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_005_out_endofpacket), // .endofpacket
.out_channel (crosser_005_out_channel), // .channel
.out_data (crosser_005_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (101),
.BITS_PER_SYMBOL (101),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (8),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_006 (
.in_clk (clk_50_clk_clk), // in_clk.clk
.in_reset (jtag_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (pll_c0_clk), // out_clk.clk
.out_reset (cpu_reset_n_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_demux_005_src0_ready), // in.ready
.in_valid (rsp_demux_005_src0_valid), // .valid
.in_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_005_src0_endofpacket), // .endofpacket
.in_channel (rsp_demux_005_src0_channel), // .channel
.in_data (rsp_demux_005_src0_data), // .data
.out_ready (crosser_006_out_ready), // out.ready
.out_valid (crosser_006_out_valid), // .valid
.out_startofpacket (crosser_006_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_006_out_endofpacket), // .endofpacket
.out_channel (crosser_006_out_channel), // .channel
.out_data (crosser_006_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (101),
.BITS_PER_SYMBOL (101),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (8),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_007 (
.in_clk (clk_50_clk_clk), // in_clk.clk
.in_reset (jtag_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (pll_c0_clk), // out_clk.clk
.out_reset (cpu_reset_n_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_demux_006_src0_ready), // in.ready
.in_valid (rsp_demux_006_src0_valid), // .valid
.in_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_006_src0_endofpacket), // .endofpacket
.in_channel (rsp_demux_006_src0_channel), // .channel
.in_data (rsp_demux_006_src0_data), // .data
.out_ready (crosser_007_out_ready), // out.ready
.out_valid (crosser_007_out_valid), // .valid
.out_startofpacket (crosser_007_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_007_out_endofpacket), // .endofpacket
.out_channel (crosser_007_out_channel), // .channel
.out_data (crosser_007_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
endmodule
|
/*
** -----------------------------------------------------------------------------**
** sensortrig.v
**
** Synchronization/triggering controller for sensor readout
**dsat
** Copyright (C) 2002-2008 Elphel, Inc.
**
** -----------------------------------------------------------------------------**
** This file is part of X353
** X353 is free software - hardware description language (HDL) code.
**
** This program is free software: you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation, either version 3 of the License, or
** (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with this program. If not, see <http://www.gnu.org/licenses/>.
** -----------------------------------------------------------------------------**
**
*/
module sensortrig (pclk,
sclk, // global
wlin, // decoded address, write last line # in frame (since trigger in external trigger mode)
wcmd, // decoded address, write command from d[3:0]:
// now wcmd, d[28:16] - number of lines to delay frame syn interrupt
// d[3] - 0 skip lines, 1 - skip frames
// d[2] - enable
// d[1] - external (0 - internal)
// d[0] - continuous
framesync_dly, // write frame sync (vacts_out) delay in lines
d, // [31:0][11:0] data in
compressed_frames, // [7:0] - bitmask of frames to compress (generate vacts15)
frame_num, // [2:0] current frame number (switches after vacts_sclk)
trig, // external trigger, 0->1 transition
hact, // hact (line active)
vacts_in, // single-cycle frame sync
vacts_out, // single-cycle frame sync (divided if needed in photofinish mode)
vacts15, // pulse from vacts active for 15 scan lines
sensor_en, // enable sensor output
trig_v, // [13:0] line number when trigger occured
trig_h, // [13:0] pixel number when trigger occured
status, // [2:0]: 00 - off, 01 - waiting for vacts to start, 10 - frame active, 11 - frame over
frame_run, // active while frame is being acquired (include all line_run)
xfer_over_irq, // pulse after transfer of specified number of lines (after trigger)
trig_irq, // single-cycle (pclk) pulse after external trigger
fillfactory, // fillfactory sensor mode
ystart, // start of frame (fillfactory sensor mode) - 3 cycles long;
yclock // start of line (fillfactory sensor mode) - 1 cycle long;
);
input pclk;
input sclk;
input wlin;
input wcmd;
input [15:0] d;
input [ 7:0] compressed_frames; //[7:0] - bitmask of frames to compress (generate vacts15)
input [ 2:0] frame_num;
input framesync_dly; // write frame sync (vacts_out) delay in lines
input trig;
input hact;
input vacts_in;
output vacts_out;
output vacts15;
output sensor_en;
output [13:0] trig_v;
output [13:0] trig_h; // can be 12'h800
output [2:0] status; // modify, MSB - "done"
output frame_run;
output xfer_over_irq;
output trig_irq;
input fillfactory; // fillfactory sensor mode
output ystart; // start of frame (fillfactory sensor mode) - 3 cycles long;
output yclock; // start of line (fillfactory sensor mode) - 1 cycle long;
wire fillfactory; // fillfactory sensor mode
reg ystart; // start of frame (fillfactory sensor mode) - 3 cycles long;
wire yclock; // start of line (fillfactory sensor mode) - 1 cycle long;
wire sensor_en;
wire [2:0] status;
reg [1:0] hact_dly;
reg nxt_line;
reg nxt_line1; // delayed
wire nxt_lf; // next line/frame (depending on cmd[3]
wire state1, // waiting vacts
state2, // got vacts, (==hact_en)
state3; // got external trigger (does not turn off state2)
wire trig0, // sync to trig
trig1, // first registered to pclk (not used by itself)
trig2; // registered by pclk, latency 2
wire start0, // sync to wclk
start1, // 1-st registered by pclk
start; // 2-nd registered by pclk
wire [3:0] cmd; // command register, written @wclk (wcmd=1'b1)
reg [13:0] nlines; // lines to acquire
reg [13:0] vact_dly; //delay vact irq by this number of lines
reg [13:0] vact_dly_cntr;
reg [13:0] trig_v;
reg [13:0] trig_h; // can be 12'h800
reg [13:0] lines_left;
wire xfer_over;
reg xfer_over_irq;
reg done;
wire sync_wr,sync_wr0,sync_wr1; // writing nlines in ff mode;
reg frame_run;
reg pre_vacts_out; //at the beginning of the frame
reg pre_vacts_out_d; // delayed by some 1 pre_vacts_out
reg vacts_out; // delayed by some lines (0 - next cycle after pre_vacts_out_d)
reg vacts_dly_on; // from pre_vacts till vacts;
wire wlin_pclks0;
reg [ 1:0] wlin_pclks;
reg [13:0] nff; // photofinish mode - number of sensor frames in one "frame"
reg [13:0] ff_count; // frame in frame counter
wire ff_count_eq0;
reg [3:0] vacts15_cntr;
reg vacts15;
reg set_lines_left;
assign yclock=nxt_line;
assign nxt_lf=(cmd[3])? pre_vacts_out: nxt_line; // next line/frame (depending on cmd[3]
reg en_vacts15_sclk,en_vacts15;
reg [7:0] frame_num_1shot;
always @ (negedge sclk) begin
frame_num_1shot <={frame_num[2:0]==3'h7,
frame_num[2:0]==3'h6,
frame_num[2:0]==3'h5,
frame_num[2:0]==3'h4,
frame_num[2:0]==3'h3,
frame_num[2:0]==3'h2,
frame_num[2:0]==3'h1,
frame_num[2:0]==3'h0};
en_vacts15_sclk <= | (frame_num_1shot[7:0] & compressed_frames[7:0]);
end
assign ff_count_eq0= (ff_count[13:0]==14'h0);
FDCE_1 i_wlin_pclks0 (.C(sclk),.CE(wlin),.CLR(wlin_pclks[1]), .D(1'b1), .Q(wlin_pclks0));
always @ (posedge pclk) begin
en_vacts15 <= en_vacts15_sclk;
wlin_pclks[1:0] <= {wlin_pclks[0] && !wlin_pclks[1], wlin_pclks0};
if (wlin_pclks[1] || (nff[13:0] == 14'h0) || (ff_count_eq0 && vacts_in)) ff_count[13:0] <= nff[13:0];
else if (vacts_in) ff_count[13:0] <= ff_count[13:0]-1;
pre_vacts_out <= vacts_in && ff_count_eq0;
pre_vacts_out_d <= pre_vacts_out;
if (pre_vacts_out) vact_dly_cntr[13:0] <= vact_dly[13:0];
else if (nxt_line && vacts_dly_on) vact_dly_cntr[13:0] <= vact_dly_cntr[13:0] -1 ;
if (pre_vacts_out) vacts_dly_on <= 1'b1;
else if (vacts_out) vacts_dly_on <= 1'b0;
vacts_out <= !vacts_out && vacts_dly_on &&
((pre_vacts_out_d && (vact_dly[13:0]==14'h0)) ||
(nxt_line && (vact_dly_cntr[13:0]==14'h0)));
// generate vacts15 - vacts_out delayed by 15 scan lines (before compressor could start)
if (vacts_out) vacts15_cntr[3:0] <= 4'hf;
else if (nxt_line && vacts15) vacts15_cntr[3:0] <= vacts15_cntr[3:0] -1 ;
if (vacts_out) vacts15 <= en_vacts15;
else if (nxt_line && (vacts15_cntr[3:0] ==4'h0)) vacts15 <= 1'b0 ;
end
FDE_1 i_cmd_0 (.C(sclk), .CE(wcmd), .D(d[0]), .Q(cmd[0]));
FDE_1 i_cmd_1 (.C(sclk), .CE(wcmd), .D(d[1]), .Q(cmd[1]));
FDE_1 i_cmd_2 (.C(sclk), .CE(wcmd), .D(d[2]), .Q(cmd[2]));
FDE_1 i_cmd_3 (.C(sclk), .CE(wcmd), .D(d[3]), .Q(cmd[3]));
always @ (negedge sclk) if (framesync_dly) vact_dly[13:0] <= d[13:0];
// write command synchronization
FDC_1 i_start0 (.C(sclk),.CLR(start), .D(start0 || wcmd), .Q(start0));
FDC i_start1 (.C(pclk), .CLR(start), .D(start0), .Q(start1));
FD i_start (.C(pclk), .D(start1), .Q(start ));
// write wlin synchronization
FDC_1 i_sync_wr0 (.C(sclk), .CLR(sync_wr), .D(sync_wr0 || (wlin && fillfactory)), .Q(sync_wr0));
FDC i_sync_wr1 (.C(pclk), .CLR(sync_wr), .D(sync_wr0), .Q(sync_wr1));
FD i_sync_wr (.C(pclk), .D(sync_wr1), .Q(sync_wr ));
// external trigger synchronization
// warnings for combinatorial input for trig ++++++++++++++++++++
FDC i_trig0 (.C(trig),.CLR(trig2 || !state2 || state3), .D(state2 && !state3 && cmd[1]),.Q(trig0));
FDC i_trig1 (.C(pclk), .CLR(trig2), .D(trig0), .Q(trig1));
FD i_trig2 (.C(pclk), .D(trig1), .Q(trig2));
// state transitions (state3 and state2 are NOT mutually exclusive)
FD i_state1 (.C(pclk), .D(cmd[2] && (state1? (!pre_vacts_out) : ((xfer_over && cmd[0]) || (start && !state2)))), .Q(state1));
FD i_state2 (.C(pclk), .D(cmd[2] && (state2? (!xfer_over) : (state1 && pre_vacts_out))), .Q(state2));
FD i_state3 (.C(pclk), .D(cmd[2] && (state3? (!xfer_over) : ((state1 && pre_vacts_out && !cmd[1]) || trig2))), .Q(state3));
always @ (negedge sclk) if (wlin && !d[14]) begin ///(d[14]==1) - write number of pixels in a line
if (d[15]) nff[13:0] <= d[13:0];
else nlines[13:0] <= d[13:0];
end
assign sensor_en=state2;
always @ (posedge pclk) begin
frame_run <= state2 && !state3;
hact_dly[1:0] <= {hact_dly[0],hact};
nxt_line <= (hact_dly[1] && !hact_dly[0]) || (fillfactory && ystart && !nxt_line && !nxt_line1);
// nxt_line1 <= nxt_line;
nxt_line1 <= yclock;
// sync_wr_d1 <= sync_wr;
// sync_wr_d2 <= sync_wr_d1;
ystart <= (((hact_dly[0] && !hact && (lines_left[13:0]==14'b1)) || sync_wr) || ystart) && !nxt_line1 && fillfactory; // 3 cycles long
// count_h[11:0] <= hact_dly[1]? (count_h[11:0]+(!state3)):12'b0; // will stop counting
end
always @ (posedge pclk)
if (pre_vacts_out && state1) trig_v[13:0] <= 14'b0;
else if (nxt_line && state2 && !state3 && !trig2) trig_v[13:0] <= trig_v[13:0]+1;
always @ (posedge pclk) if (state2 && !state3 && !trig2) begin
if (!hact_dly[1]) trig_h[13:0] <= 14'b0;
else trig_h[13:0] <= trig_h[13:0]+1;
end
always @ (posedge pclk)
set_lines_left <= state1 || (set_lines_left && !hact);
always @ (posedge pclk)
// if (fillfactory?(sync_wr || ((lines_left[13:0]==14'b0) && hact_dly[1] && !hact_dly[0])):state1) lines_left[13:0] <= nlines[13:0];
if (fillfactory?(sync_wr || ((lines_left[13:0]==14'b0) && hact_dly[1] && !hact_dly[0])):set_lines_left) lines_left[13:0] <= nlines[13:0];
else if (fillfactory ? nxt_line : (nxt_lf && (state3 || trig2))) lines_left[13:0] <= lines_left[13:0]-1;
// assign xfer_over=state3 && (lines_left[13:0]==14'h001) && nxt_lf;
assign xfer_over=state3 && (((lines_left[13:0]==14'h001) && nxt_lf) ||
(vacts_in && ff_count_eq0)); // abort input frame at the (next) frame sync
//vacts_in && ff_count_eq0
always @ (posedge pclk) xfer_over_irq <= xfer_over;
always @ (posedge pclk) done <= !start && (done || xfer_over);
assign status[2:0]= {done,state2,state1 || state3};
assign trig_irq=trig2;
// assign hact_en=state2;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFXTP_FUNCTIONAL_V
`define SKY130_FD_SC_LS__SDFXTP_FUNCTIONAL_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`include "../../models/udp_dff_p/sky130_fd_sc_ls__udp_dff_p.v"
`celldefine
module sky130_fd_sc_ls__sdfxtp (
Q ,
CLK,
D ,
SCD,
SCE
);
// Module ports
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_ls__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFXTP_FUNCTIONAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Case Western Reserve University
// Engineer: Matt McConnell
//
// Create Date: 00:48:00 01/25/2017
// Project Name: EECS301 Digital Design
// Design Name: Lab #3 Project
// Module Name: Key_Synchronizer_Module
// Target Devices: Altera Cyclone V
// Tool versions: Quartus v17.0
// Description: Key input signal synchronizer to align asynchronous key
// press signals to the system clock. Also, provides a
// key lockout so only one key press will be generated per
// lockout delay period.
// Dependencies:
//
//////////////////////////////////////////////////////////////////////////////////
module Key_Synchronizer_Module
#(
parameter CLK_RATE_HZ = 50000000, // Hz
parameter KEY_LOCK_DELAY = 800000000 // nS
)
(
// Input Signals
input KEY,
// Output Signals
output reg KEY_EVENT,
// System Signals
input CLK
);
// Include Standard Functions header file (needed for bit_index())
`include "StdFunctions.vh"
//
// Synchronize Key Input to System Clock
//
wire key_sync;
CDC_Input_Synchronizer
#(
.SYNC_REG_LEN( 2 )
)
key_synchronizer
(
// Input Signal
.ASYNC_IN( KEY ),
// Output Signal
.SYNC_OUT( key_sync ),
// System Signals
.CLK( CLK )
);
//
// Key Lockout Counter
//
localparam KEY_LOCK_DELAY_TICKS = (1.0 * KEY_LOCK_DELAY) / (1000000000.0 / CLK_RATE_HZ);
localparam KEY_LOCK_WIDTH = bit_index(KEY_LOCK_DELAY_TICKS);
localparam [KEY_LOCK_WIDTH:0] KEY_LOCK_LOADVAL = {1'b1, {(KEY_LOCK_WIDTH-1){1'b0}}, 1'b1} - KEY_LOCK_DELAY_TICKS;
localparam KEY_LOCK_CLEARVAL = {1'b1, {KEY_LOCK_WIDTH{1'b0}}};
wire key_lock_out;
reg [KEY_LOCK_WIDTH:0] key_lock_counter_reg;
assign key_lock_out = ~key_lock_counter_reg[KEY_LOCK_WIDTH];
initial
begin
// Startout with the key lockout disenabled
key_lock_counter_reg <= KEY_LOCK_CLEARVAL;
KEY_EVENT <= 1'b0;
end
always @(posedge CLK)
begin
if (~key_lock_out)
begin
if (key_sync)
key_lock_counter_reg <= KEY_LOCK_LOADVAL;
end
else
begin
if (~key_sync)
key_lock_counter_reg <= KEY_LOCK_CLEARVAL;
else
key_lock_counter_reg <= key_lock_counter_reg + 1'b1;
end
end
//
// Key Event Register
//
always @(posedge CLK)
begin
if (key_sync & ~key_lock_out)
KEY_EVENT <= 1'b1;
else
KEY_EVENT <= 1'b0;
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
//// ////
//// Project Name: SPI (Verilog) ////
//// ////
//// Module Name: spi_master ////
//// ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://opencores.com/project,spi_verilog_master_slave ////
//// ////
//// Author(s): ////
//// Santhosh G (santhg @ opencores.org) ////
//// ////
//// Refer to Readme.txt for more information ////
//// ////
////////////////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2014, 2015 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
////////////////////////////////////////////////////////////////////////////////
/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
SPI MODE 3
CHANGE DATA @ NEGEDGE
read data @ posedge
RSTB-active low asyn reset, CLK-clock, T_RB = 0-rx 1-TX,
mlb = 0-LSB 1st 1-msb 1st
START = 1- starts data transmission cdiv 0 = clk/4 1 = /8 2 = /131 3 = /32
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
`include "timescale.v"
module spi_master(rstb, clk, mlb, start, tdat, cdiv,
din, ss, sck, dout, done_r, rdata);
parameter state_idle = 4'd0;
parameter state_send = 4'd1;
parameter state_finish = 4'd2;
input rstb, clk, mlb, start;
input [31:0] tdat; //transmit data
input [1:0] cdiv; //clock divider
input din;
output reg ss;
output reg sck;
output reg dout;
output reg done_r;
output reg [31:0] rdata; //received data
wire [4:0] mid;
reg [3:0] current_state,next_state;
reg [31:0] treg,rreg;
reg [31:0] rdata_next;
reg [31:0] nbit;
reg [4:0] cnt;
reg shift, clr;
reg done;
assign mid = 1;
//state transistion
always @ (negedge clk or negedge rstb) begin
if (rstb == 0)
done_r <= 1'b0;
else
if (current_state == state_finish)
done_r <= 1'b1;
else
done_r <= 1'b0;
end
//state transistion
always @ (negedge clk or negedge rstb) begin
if (rstb == 0) begin
current_state <= state_finish;
rdata <= 0;
end
else begin
current_state <= next_state;
rdata <= rdata_next;
end
end
//FSM i/o
always @ (start or current_state or nbit or cdiv or rreg or rdata) begin
clr = 0;
shift = 0;
ss = 1;
// done = 0;
rdata_next = rdata;
next_state = current_state;
/* case (cdiv) // clk divider for spi sck
2'b00: mid = 2;
2'b01: mid = 4;
2'b10: mid = 8;
2'b11: mid = 131;
endcase*/
case(current_state)
state_idle: begin // 2'b00 = 0
#1 // to avoid infinite simulation loop
if (start == 1) begin
shift = 1;
next_state = state_send;
end
end
state_send: begin // 2'b10 = 2
ss = 0;
if (nbit != 32) begin
shift = 1;
end
else begin
rdata_next = rreg;
// done = 1'b1;
// next_state = state_wait_1;
next_state = state_finish;
end
end
state_finish: begin // 2'b11 = 3
shift = 0;
ss = 1;
clr = 1;
// done = 1'b1;
next_state = state_idle;
end
default: next_state = state_finish;
endcase
end
//setup falling edge (shift dout) sample rising edge (read din)
always @ (negedge clk or posedge clr) begin
if (clr == 1) begin
cnt = 5'd0;
sck = 0;
end
else begin
if (shift == 1) begin
cnt = cnt + 5'd1;
if (cnt == mid) begin
sck = ~sck;
cnt = 5'd0;
end
end
end
end
//sample @ rising edge (read din)
always @ (negedge sck or posedge clr ) begin // or negedge rstb
if (clr == 1) begin
nbit = 7'd0;
rreg = 32'hFFFF_FFFF;
end
else begin
if (mlb == 0) begin //LSB first, din @ msb -> right shift
rreg = { din, rreg[31:1] };
end
else begin //MSB first, din @ lsb -> left shift
rreg = { rreg[30:0], din };
end
nbit = nbit + 7'd1;
end
end
// shift dout @ falling edge (write dout)
always @ (posedge sck or posedge clr) begin
if (clr == 1) begin
treg = 32'h0;
dout = 0;
end
else begin
if (nbit == 0) begin //load data into TREG
treg = tdat;
dout = mlb ? treg[31] : treg[0];
end //nbit_if
else begin
if (mlb == 0) begin //LSB first, shift right
treg = { 1'b1, treg[31:1] };
dout = treg[0];
end
else begin //MSB first shift LEFT
treg = { treg[30:0], 1'b1 };
dout = treg[31];
end
end
end
end
endmodule
|
module ARM_CU_ALU_TestBench;
parameter sim_time = 750*2; // Num of Cycles * 2
reg MFC , Reset , Clk , MEMSTORE,MEMLOAD;
reg [31:0] MEMDAT;
wire MFA,READ_WRITE,WORD_BYTE;
wire [7:0] MEMADD;
//module ARM_CU_ALU( input MFC , Reset , Clk , MEMSTORE,MEMLOAD,MEMDAT, output MEMADD, MFA,READ_WRITE,WORD_BYTE);
ARM_CU_ALU CPU( MFC , Reset , Clk , MEMSTORE,MEMLOAD,MEMDAT,MEMADD, MFA,READ_WRITE,WORD_BYTE);
initial fork
Reset =1; Clk = 0; MEMSTORE=0;MEMLOAD=0;MEMDAT=0;MFC=0;
#1 Reset = 0;
join
always@(posedge MFA)begin
case(MEMADD)
8'h00:begin
#1 MEMDAT = 32'h0000CAFE ; MEMLOAD = 1;
#5 MFC = 1 ;
#7 MFC = 0 ;
end
8'h01:begin
#1 MEMDAT = 32'hCAFE0000 ; MEMLOAD = 1;
#5 MFC = 1 ;
#7 MFC = 0 ;
end
endcase
end
always
#1 Clk = ~Clk;
initial #sim_time $finish;
initial begin
$dumpfile("ARM_CU_ALU_TestBench.vcd");
$dumpvars(0,ARM_CU_ALU_TestBench);
$display(" Test Results" );
$monitor("input MFC =%d, Reset =%d, Clk =%d, MEMSTORE=%d,MEMLOAD=%d,MEMDAT=%d, output MEMADD=%d, MFA=%d,READ_WRITE=%d,WORD_BYTE=%d,",MFC , Reset , Clk , MEMSTORE,MEMLOAD,MEMDAT, MEMADD, MFA,READ_WRITE,WORD_BYTE);
end
endmodule
//iverilog ARM_ALU.v ARM_CU_ALU.v BarrelShifter.v Buffer32_32.v controlunit2.v Decoder4x16.v Multiplexer2x1_32b.v Register.v Register2.v RegisterFile.v Register2Buff.v ARM_CU_ALU_TestBench.v |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLXBN_BEHAVIORAL_V
`define SKY130_FD_SC_HD__DLXBN_BEHAVIORAL_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_hd__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dlxbn (
Q ,
Q_N ,
D ,
GATE_N
);
// Module ports
output Q ;
output Q_N ;
input D ;
input GATE_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire GATE ;
wire buf_Q ;
wire GATE_N_delayed;
wire D_delayed ;
reg notifier ;
wire awake ;
wire 1 ;
// Name Output Other arguments
not not0 (GATE , GATE_N_delayed );
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE, notifier, VPWR, VGND);
assign awake = ( VPWR === 1 );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLXBN_BEHAVIORAL_V |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : pcie_trn_128.v
// Version : 1.7
`timescale 1ps/1ps
module pcie_trn_128 #(
parameter TCQ = 100
)(
input user_clk,
input block_clk,
input rst_n_250,
input rst_n_500,
input [1:0] cfgpmcsrpowerstate,
//////////////////
// to/from user //
//////////////////
output [6:0] trn_rbar_hit_n_o,
output [127:0] trn_rd_o,
output trn_recrc_err_n_o,
output trn_rsof_n_o,
output trn_reof_n_o,
output trn_rerrfwd_n_o,
output [1:0] trn_rrem_n_o,
output trn_rsrc_dsc_n_o,
output trn_rsrc_rdy_n_o,
input trn_rdst_rdy_n_i,
input trn_rnpok_n_i,
output [5:0] trn_tbuf_av_o,
output trn_tdst_rdy_n_o,
output trn_terr_drop_n_o,
input [127:0] trn_td_i,
input trn_tecrc_gen_n_i,
input trn_terr_fwd_n_i,
input [1:0] trn_trem_n_i,
input trn_tsof_n_i,
input trn_teof_n_i,
input trn_tsrc_dsc_n_i,
input trn_tsrc_rdy_n_i,
input trn_tstr_n_i,
output [11:0] trn_fc_cpld_o,
output [7:0] trn_fc_cplh_o,
output [11:0] trn_fc_npd_o,
output [7:0] trn_fc_nph_o,
output [11:0] trn_fc_pd_o,
output [7:0] trn_fc_ph_o,
input [2:0] trn_fc_sel_i,
////////////////
// to/from EP //
////////////////
input [6:0] TRNRBARHITN_i,
input [63:0] TRNRD_i,
input TRNRECRCERRN_i,
input TRNRSOFN_i,
input TRNREOFN_i,
input TRNRERRFWDN_i,
input TRNRREMN_i,
input TRNRSRCDSCN_i,
input TRNRSRCRDYN_i,
output TRNRDSTRDYN_o,
output TRNRNPOKN_o,
input [5:0] TRNTBUFAV_i,
input TRNTCFGREQN_i,
input TRNTDSTRDYN_i,
input TRNTERRDROPN_i,
output TRNTCFGGNTN_o,
output [63:0] TRNTD_o,
output TRNTECRCGENN_o,
output TRNTERRFWDN_o,
output TRNTREMN_o,
output TRNTSOFN_o,
output TRNTEOFN_o,
output TRNTSRCDSCN_o,
output TRNTSRCRDYN_o,
output TRNTSTRN_o,
input [11:0] TRNFCCPLD_i,
input [7:0] TRNFCCPLH_i,
input [11:0] TRNFCNPD_i,
input [7:0] TRNFCNPH_i,
input [11:0] TRNFCPD_i,
input [7:0] TRNFCPH_i,
output [2:0] TRNFCSEL_o
);
reg [11:0] TRNFCCPLD_i_250;
reg [7:0] TRNFCCPLH_i_250;
reg [11:0] TRNFCNPD_i_250;
reg [7:0] TRNFCNPH_i_250;
reg [11:0] TRNFCPD_i_250;
reg [7:0] TRNFCPH_i_250;
reg [2:0] trn_fc_sel_i_250;
reg [2:0] trn_fc_sel_i_250_500;
assign trn_fc_cpld_o = TRNFCCPLD_i_250;
assign trn_fc_cplh_o = TRNFCCPLH_i_250;
assign trn_fc_npd_o = TRNFCNPD_i_250;
assign trn_fc_nph_o = TRNFCNPH_i_250;
assign trn_fc_pd_o = TRNFCPD_i_250;
assign trn_fc_ph_o = TRNFCPH_i_250;
assign TRNFCSEL_o = trn_fc_sel_i_250_500;
// -------------------------------------------------------------------------
// 500Mhz
// -------------------------------------------------------------------------
always @(posedge block_clk)
begin
if (~rst_n_500)
trn_fc_sel_i_250_500 <= #TCQ 3'd0;
else
trn_fc_sel_i_250_500 <= #TCQ trn_fc_sel_i_250;
end
// -------------------------------------------------------------------------
// 250Mhz
// -------------------------------------------------------------------------
always @(posedge user_clk)
begin
if (~rst_n_250)
begin
TRNFCCPLD_i_250 <= #TCQ 12'd0;
TRNFCCPLH_i_250 <= #TCQ 8'd0;
TRNFCNPD_i_250 <= #TCQ 12'd0;
TRNFCNPH_i_250 <= #TCQ 8'd0;
TRNFCPD_i_250 <= #TCQ 12'd0;
TRNFCPH_i_250 <= #TCQ 8'd0;
trn_fc_sel_i_250 <= #TCQ trn_fc_sel_i;
end else begin
TRNFCCPLD_i_250 <= #TCQ TRNFCCPLD_i;
TRNFCCPLH_i_250 <= #TCQ TRNFCCPLH_i;
TRNFCNPD_i_250 <= #TCQ TRNFCNPD_i;
TRNFCNPH_i_250 <= #TCQ TRNFCNPH_i;
TRNFCPD_i_250 <= #TCQ TRNFCPD_i;
TRNFCPH_i_250 <= #TCQ TRNFCPH_i;
trn_fc_sel_i_250 <= #TCQ trn_fc_sel_i;
end
end
//-------------------------------------------------------
// TX module
//-------------------------------------------------------
trn_tx_128 #(
.TCQ( TCQ )
) trn_tx_128_i (
.user_clk( user_clk ),
.block_clk( block_clk ),
.rst_n_250( rst_n_250 ),
.rst_n_500( rst_n_500 ),
.cfgpmcsrpowerstate( cfgpmcsrpowerstate ),
.trn_tbuf_av_o( trn_tbuf_av_o ),
.trn_tdst_rdy_n_o( trn_tdst_rdy_n_o ),
.trn_terr_drop_n_o( trn_terr_drop_n_o ),
.trn_td_i( trn_td_i ),
.trn_tecrc_gen_n_i( trn_tecrc_gen_n_i ),
.trn_terr_fwd_n_i( trn_terr_fwd_n_i ),
.trn_trem_n_i( trn_trem_n_i ),
.trn_tsof_n_i( trn_tsof_n_i ),
.trn_teof_n_i( trn_teof_n_i ),
.trn_tsrc_dsc_n_i( trn_tsrc_dsc_n_i ),
.trn_tsrc_rdy_n_i( trn_tsrc_rdy_n_i ),
.trn_tstr_n_i( trn_tstr_n_i ),
.TRNTBUFAV_i( TRNTBUFAV_i ),
.TRNTCFGREQN_i( TRNTCFGREQN_i ),
.TRNTDSTRDYN_i( TRNTDSTRDYN_i ),
.TRNTERRDROPN_i( TRNTERRDROPN_i ),
.TRNTCFGGNTN_o( TRNTCFGGNTN_o ),
.TRNTD_o( TRNTD_o ),
.TRNTECRCGENN_o( TRNTECRCGENN_o ),
.TRNTERRFWDN_o( TRNTERRFWDN_o ),
.TRNTREMN_o( TRNTREMN_o ),
.TRNTSOFN_o( TRNTSOFN_o ),
.TRNTEOFN_o( TRNTEOFN_o ),
.TRNTSRCDSCN_o( TRNTSRCDSCN_o ),
.TRNTSRCRDYN_o( TRNTSRCRDYN_o ),
.TRNTSTRN_o( TRNTSTRN_o )
);
//-------------------------------------------------------
// RX module
//-------------------------------------------------------
trn_rx_128 #(
.TCQ( TCQ )
) trn_rx_128_i (
.user_clk( user_clk ),
.block_clk( block_clk ),
.rst_n_250( rst_n_250 ),
.rst_n_500( rst_n_500 ),
.trn_rbar_hit_n_o( trn_rbar_hit_n_o ),
.trn_rd_o( trn_rd_o ),
.trn_recrc_err_n_o( trn_recrc_err_n_o ),
.trn_rsof_n_o( trn_rsof_n_o ),
.trn_reof_n_o( trn_reof_n_o ),
.trn_rerrfwd_n_o( trn_rerrfwd_n_o ),
.trn_rrem_n_o( trn_rrem_n_o ),
.trn_rsrc_dsc_n_o( trn_rsrc_dsc_n_o ),
.trn_rsrc_rdy_n_o( trn_rsrc_rdy_n_o ),
.trn_rdst_rdy_n_i( trn_rdst_rdy_n_i ),
.trn_rnpok_n_i( trn_rnpok_n_i ),
.TRNRBARHITN_i( TRNRBARHITN_i ),
.TRNRD_i( TRNRD_i ),
.TRNRECRCERRN_i( TRNRECRCERRN_i ),
.TRNRSOFN_i( TRNRSOFN_i ),
.TRNREOFN_i( TRNREOFN_i ),
.TRNRERRFWDN_i( TRNRERRFWDN_i ),
.TRNRREMN_i( TRNRREMN_i ),
.TRNRSRCDSCN_i( TRNRSRCDSCN_i ),
.TRNRSRCRDYN_i( TRNRSRCRDYN_i ),
.TRNRDSTRDYN_o( TRNRDSTRDYN_o ),
.TRNRNPOKN_o( TRNRNPOKN_o )
);
endmodule
|
/**
* ff_d.v - Microcoded Accumulator CPU
* Copyright (C) 2015 Orlando Arias, David Mascenik
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
module ff_d #(parameter WIDTH=8) (
input wire [WIDTH - 1 : 0] D, /* data input */
input wire en, /* enable */
input wire clk, /* clock */
input wire res, /* synchronous active high reset */
output wire [WIDTH - 1 : 0] Q /* output */
);
reg [WIDTH - 1 : 0] storage;
assign Q = storage;
always @(posedge clk) begin
if(res) /* handle synchronous reset */
storage <= {WIDTH{1'b0}};
else if(en) /* handle save data */
storage <= D;
end
endmodule
/* vim: set ts=4 tw=79 syntax=verilog */
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/18/2016 09:58:17 PM
// Design Name:
// Module Name: rcMC
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "global.vh"
`ifdef CARPOOL
module rcMC(
dstList,
preferPortVector
);
input [`DST_LIST_WIDTH-1:0] dstList;
output [`NUM_PORT-1:0] preferPortVector;
assign preferPortVector [0] = |(dstList & `N_MASK);
assign preferPortVector [1] = |(dstList & `E_MASK);
assign preferPortVector [2] = |(dstList & `S_MASK);
assign preferPortVector [3] = |(dstList & `W_MASK);
assign preferPortVector [4] = |(dstList & `L_MASK);
endmodule
`endif //CARPOOL
`ifdef CARPOOL_LK_AHEAD_RC_PS
module rcMC(
dstList,
outdir, // target output
preferPortVector
);
input [`DST_LIST_WIDTH-1:0] dstList;
input [`PC_INDEX_WIDTH-2:0] outdir;
output [`NUM_PORT-1:0] preferPortVector;
wire [`NUM_PORT-1:0] ppv_n, ppv_e, ppv_s, ppv_w;
assign ppv_n [0] = |(dstList & `N_MASK_N);
assign ppv_n [1] = |(dstList & `N_MASK_E);
assign ppv_n [2] = 1'b0;
assign ppv_n [3] = |(dstList & `N_MASK_W);
assign ppv_n [4] = |(dstList & `N_MASK_L);
assign ppv_e [0] = |(dstList & `E_MASK_N);
assign ppv_e [1] = |(dstList & `E_MASK_E);
assign ppv_e [2] = |(dstList & `E_MASK_S);
assign ppv_e [3] = 1'b0;
assign ppv_e [4] = |(dstList & `E_MASK_L);
assign ppv_s [0] = 1'b0;
assign ppv_s [1] = |(dstList & `S_MASK_E);
assign ppv_s [2] = |(dstList & `S_MASK_S);
assign ppv_s [3] = |(dstList & `S_MASK_W);
assign ppv_s [4] = |(dstList & `S_MASK_L);
assign ppv_w [0] = |(dstList & `W_MASK_N);
assign ppv_w [1] = 1'b0;
assign ppv_w [2] = |(dstList & `W_MASK_S);
assign ppv_w [3] = |(dstList & `W_MASK_W);
assign ppv_w [4] = |(dstList & `W_MASK_L);
assign preferPortVector = (outdir == 0) ? ppv_n :
(outdir == 1) ? ppv_e :
(outdir == 2) ? ppv_s :
(outdir == 3) ? ppv_w : `NUM_PORT'h0;
endmodule
`endif // End of `ifdef CARPOOL_LK_AHEAD_RC_PS
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A2111O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__A2111O_BEHAVIORAL_PP_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__a2111o (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , C1, B1, and0_out, D1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A2111O_BEHAVIORAL_PP_V |
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlslice:1.0
// IP Revision: 0
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xlslice_7_1 (
Din,
Dout
);
input wire [47 : 0] Din;
output wire [15 : 0] Dout;
xlslice #(
.DIN_WIDTH(48),
.DIN_FROM(38),
.DIN_TO(23)
) inst (
.Din(Din),
.Dout(Dout)
);
endmodule
|
// -*- Mode: Verilog -*-
// Filename : burst_00.v
// Description : Test burst read/write interfacing
// Author : Philip Tracton
// Created On : Tue Jun 28 11:31:45 2016
// Last Modified By: Philip Tracton
// Last Modified On: Tue Jun 28 11:31:45 2016
// Update Count : 0
// Status : Unknown, Use with caution!
`include "simulation_includes.vh"
module test_case (/*AUTOARG*/ ) ;
//
// Test Configuration
// These parameters need to be set for each test case
//
parameter simulation_name = "interrupts_00";
parameter number_of_tests = 28;
reg err;
reg [31:0] data_out;
reg [15:0] i;
reg [15:0] index ;
defparam `ADXL362_ACCELEROMETER.XDATA_FILE = "accelerometer_00_xdata.txt";
defparam `ADXL362_ACCELEROMETER.YDATA_FILE = "accelerometer_00_ydata.txt";
defparam `ADXL362_ACCELEROMETER.ZDATA_FILE = "accelerometer_00_zdata.txt";
defparam `ADXL362_ACCELEROMETER.TEMPERATURE_FILE = "accelerometer_00_temperature_data.txt";
//
// Can't pass memories to tasks, so gigantic arrays!
//
reg [(16*7):0] write_mem = 0;
reg [(16*7):0] read_mem = 0;
initial begin
$display("Interrupts 00 Case");
`TB.master_bfm.reset;
@(posedge `WB_RST);
@(negedge `WB_RST);
@(posedge `WB_CLK);
@(negedge `ADXL362_RESET);
`SIMPLE_SPI_INIT;
//
// INT1 goes high when data ready!
//
`ADXL362_WRITE_REGISTER(`ADXL362_INTMAP1, 8'h01);
@(posedge `ADXL362_INT1) begin
`ADXL362_CHECK_DOUBLE_REGISTER(`ADXL362_XDATA_LOW, 16'h0001);
`ADXL362_CHECK_DOUBLE_REGISTER(`ADXL362_YDATA_LOW, 16'h0011);
`ADXL362_CHECK_DOUBLE_REGISTER(`ADXL362_ZDATA_LOW, 16'h00f1);
`ADXL362_CHECK_DOUBLE_REGISTER(`ADXL362_TEMP_LOW, 16'h0047);
end
`TEST_COMPARE("INT1 After Data Read", `ADXL362_INT1, 0);
@(posedge `ADXL362_INT1) begin
`ADXL362_CHECK_DOUBLE_REGISTER(`ADXL362_XDATA_LOW, 16'h0002);
`ADXL362_CHECK_DOUBLE_REGISTER(`ADXL362_YDATA_LOW, 16'h0012);
`ADXL362_CHECK_DOUBLE_REGISTER(`ADXL362_ZDATA_LOW, 16'h00F2);
`ADXL362_CHECK_DOUBLE_REGISTER(`ADXL362_TEMP_LOW, 16'h0048);
end
`TEST_COMPARE("INT1 After Data Read", `ADXL362_INT1, 0);
//
// INT2 when data in FIFO
// FIFO the data
//
`ADXL362_WRITE_REGISTER(`ADXL362_INTMAP2, 8'h02);
`ADXL362_WRITE_REGISTER(`ADXL362_FIFO_CONTROL, 8'h06);
@(posedge `ADXL362_INT2) begin
`ADXL362_READ_BURST_FIFO(read_mem, 8);
`TEST_COMPARE("FIFO 0", 8'h03, read_mem[7:0]);
`TEST_COMPARE("FIFO 1", 8'h00, read_mem[15:8]);
`TEST_COMPARE("FIFO 2", 8'h13, read_mem[23:16]);
`TEST_COMPARE("FIFO 3", 8'h40, read_mem[31:24]);
`TEST_COMPARE("FIFO 4", 8'hF3, read_mem[39:32]);
`TEST_COMPARE("FIFO 5", 8'h80, read_mem[47:40]);
`TEST_COMPARE("FIFO 6", 8'h49, read_mem[55:48]);
`TEST_COMPARE("FIFO 7", 8'hC0, read_mem[63:56]);
end // UNMATCHED !!
repeat(5) @(posedge `WB_CLK);
`TEST_COMPARE("INT2 After Data Read", `ADXL362_INT2, 0);
@(posedge `ADXL362_INT2) begin
`ADXL362_READ_BURST_FIFO(read_mem, 8);
`TEST_COMPARE("FIFO 0", 8'h04, read_mem[7:0]);
`TEST_COMPARE("FIFO 1", 8'h00, read_mem[15:8]);
`TEST_COMPARE("FIFO 2", 8'h14, read_mem[23:16]);
`TEST_COMPARE("FIFO 3", 8'h40, read_mem[31:24]);
`TEST_COMPARE("FIFO 4", 8'hF4, read_mem[39:32]);
`TEST_COMPARE("FIFO 5", 8'h80, read_mem[47:40]);
`TEST_COMPARE("FIFO 6", 8'h4A, read_mem[55:48]);
`TEST_COMPARE("FIFO 7", 8'hC0, read_mem[63:56]);
end // UNMATCHED !!
repeat(5) @(posedge `WB_CLK);
`TEST_COMPARE("INT2 After Data Read", `ADXL362_INT2, 0);
repeat(10) @(posedge `WB_CLK);
`TEST_COMPLETE;
end
endmodule // test_case
|
//-----------------------------------------------------------------------------
// Title : GT Common wrapper
// Project : 10GBASE-R
//-----------------------------------------------------------------------------
// File : ten_gig_eth_pcs_pma_ip_GT_Common_wrapper.v
//-----------------------------------------------------------------------------
// Description: This file contains the
// 10GBASE-R Transceiver GT Common block.
//-----------------------------------------------------------------------------
// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
module ten_gig_eth_pcs_pma_ip_GT_Common_wrapper # (
parameter WRAPPER_SIM_GTRESET_SPEEDUP = "false" ) //Does not affect hardware
(
input refclk,
input qplllockdetclk,
input qpllreset,
output qplllock,
output qpllrefclklost,
output qplloutclk,
output qplloutrefclk
);
//***************************** Parameter Declarations ************************
parameter QPLL_FBDIV_TOP = 66;
parameter QPLL_FBDIV_IN = (QPLL_FBDIV_TOP == 16) ? 10'b0000100000 :
(QPLL_FBDIV_TOP == 20) ? 10'b0000110000 :
(QPLL_FBDIV_TOP == 32) ? 10'b0001100000 :
(QPLL_FBDIV_TOP == 40) ? 10'b0010000000 :
(QPLL_FBDIV_TOP == 64) ? 10'b0011100000 :
(QPLL_FBDIV_TOP == 66) ? 10'b0101000000 :
(QPLL_FBDIV_TOP == 80) ? 10'b0100100000 :
(QPLL_FBDIV_TOP == 100) ? 10'b0101110000 : 10'b0000000000;
parameter QPLL_FBDIV_RATIO = (QPLL_FBDIV_TOP == 16) ? 1'b1 :
(QPLL_FBDIV_TOP == 20) ? 1'b1 :
(QPLL_FBDIV_TOP == 32) ? 1'b1 :
(QPLL_FBDIV_TOP == 40) ? 1'b1 :
(QPLL_FBDIV_TOP == 64) ? 1'b1 :
(QPLL_FBDIV_TOP == 66) ? 1'b0 :
(QPLL_FBDIV_TOP == 80) ? 1'b1 :
(QPLL_FBDIV_TOP == 100) ? 1'b1 : 1'b1;
//***************************** Wire Declarations *****************************
// ground and vcc signals
wire tied_to_ground_i;
wire [63:0] tied_to_ground_vec_i;
wire tied_to_vcc_i;
wire [63:0] tied_to_vcc_vec_i;
//********************************* Main Body of Code**************************
assign tied_to_ground_i = 1'b0;
assign tied_to_ground_vec_i = 64'h0000000000000000;
assign tied_to_vcc_i = 1'b1;
assign tied_to_vcc_vec_i = 64'hffffffffffffffff;
wire GT0_GTREFCLK0_COMMON_IN;
wire GT0_QPLLLOCKDETCLK_IN;
wire GT0_QPLLRESET_IN;
wire GT0_QPLLLOCK_OUT;
wire GT0_QPLLREFCLKLOST_OUT;
wire gt0_qplloutclk_i;
wire gt0_qplloutrefclk_i;
assign GT0_GTREFCLK0_COMMON_IN = refclk;
assign GT0_QPLLLOCKDETCLK_IN = qplllockdetclk;
assign GT0_QPLLRESET_IN = qpllreset;
assign qplllock = GT0_QPLLLOCK_OUT;
assign qpllrefclklost = GT0_QPLLREFCLKLOST_OUT;
assign qplloutclk = gt0_qplloutclk_i;
assign qplloutrefclk = gt0_qplloutrefclk_i;
//_________________________________________________________________________
//_________________________________________________________________________
//_________________________GTHE2_COMMON____________________________________
GTHE2_COMMON #
(
// Simulation attributes
.SIM_RESET_SPEEDUP (WRAPPER_SIM_GTRESET_SPEEDUP),
.SIM_QPLLREFCLK_SEL (3'b001),
.SIM_VERSION ("2.0"),
//----------------COMMON BLOCK Attributes---------------
.BIAS_CFG (64'h0000040000001000),
.COMMON_CFG (32'h00000000),
.QPLL_CFG (27'h0480181),
.QPLL_CLKOUT_CFG (4'b0000),
.QPLL_COARSE_FREQ_OVRD (6'b010000),
.QPLL_COARSE_FREQ_OVRD_EN (1'b0),
.QPLL_CP (10'b0000011111),
.QPLL_CP_MONITOR_EN (1'b0),
.QPLL_DMONITOR_SEL (1'b0),
.QPLL_FBDIV (QPLL_FBDIV_IN),
.QPLL_FBDIV_MONITOR_EN (1'b0),
.QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
.QPLL_INIT_CFG (24'h000006),
.QPLL_LOCK_CFG (16'h05E8),
.QPLL_LPF (4'b1111),
.QPLL_REFCLK_DIV (1),
.RSVD_ATTR0 (16'h0000),
.RSVD_ATTR1 (16'h0000),
.QPLL_RP_COMP (1'b0),
.QPLL_VTRL_RESET (2'b00),
.RCAL_CFG (2'b00)
)
gthe2_common_0_i
(
//----------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
.DRPADDR (tied_to_ground_vec_i[7:0]),
.DRPCLK (tied_to_ground_i),
.DRPDI (tied_to_ground_vec_i[15:0]),
.DRPDO (),
.DRPEN (tied_to_ground_i),
.DRPRDY (),
.DRPWE (tied_to_ground_i),
//-------------------- Common Block - Ref Clock Ports ---------------------
.GTGREFCLK (tied_to_ground_i),
.GTNORTHREFCLK0 (tied_to_ground_i),
.GTNORTHREFCLK1 (tied_to_ground_i),
.GTREFCLK0 (GT0_GTREFCLK0_COMMON_IN),
.GTREFCLK1 (tied_to_ground_i),
.GTSOUTHREFCLK0 (tied_to_ground_i),
.GTSOUTHREFCLK1 (tied_to_ground_i),
//----------------------- Common Block - QPLL Ports ------------------------
.BGRCALOVRDENB (tied_to_vcc_i),
.PMARSVDOUT (),
.QPLLDMONITOR (),
.QPLLFBCLKLOST (),
.QPLLLOCK (GT0_QPLLLOCK_OUT),
.QPLLLOCKDETCLK (GT0_QPLLLOCKDETCLK_IN),
.QPLLLOCKEN (tied_to_vcc_i),
.QPLLOUTCLK (gt0_qplloutclk_i),
.QPLLOUTREFCLK (gt0_qplloutrefclk_i),
.QPLLOUTRESET (tied_to_ground_i),
.QPLLPD (tied_to_ground_i),
.QPLLREFCLKLOST (GT0_QPLLREFCLKLOST_OUT),
.QPLLREFCLKSEL (3'b001),
.QPLLRESET (GT0_QPLLRESET_IN),
.QPLLRSVD1 (16'b0000000000000000),
.QPLLRSVD2 (5'b11111),
.REFCLKOUTMONITOR (),
//--------------------------- Common Block Ports ---------------------------
.BGBYPASSB (tied_to_vcc_i),
.BGMONITORENB (tied_to_vcc_i),
.BGPDB (tied_to_vcc_i),
.BGRCALOVRD (5'b00000),
.PMARSVD (8'b00000000),
.RCALENB (tied_to_vcc_i)
);
endmodule |
(** * Imp: Simple Imperative Programs *)
(** In this chapter, we begin a new direction that will continue for
the rest of the course. Up to now most of our attention has been
focused on various aspects of Coq itself, while from now on we'll
mostly be using Coq to formalize other things. (We'll continue to
pause from time to time to introduce a few additional aspects of
Coq.)
Our first case study is a _simple imperative programming language_
called Imp, embodying a tiny core fragment of conventional
mainstream languages such as C and Java. Here is a familiar
mathematical function written in Imp.
Z ::= X;;
Y ::= 1;;
WHILE not (Z = 0) DO
Y ::= Y * Z;;
Z ::= Z - 1
END
*)
(** This chapter looks at how to define the _syntax_ and _semantics_
of Imp; the chapters that follow develop a theory of _program
equivalence_ and introduce _Hoare Logic_, a widely used logic for
reasoning about imperative programs. *)
(* ####################################################### *)
(** *** Sflib *)
(** A minor technical point: Instead of asking Coq to import our
earlier definitions from chapter [Logic], we import a small library
called [Sflib.v], containing just a few definitions and theorems
from earlier chapters that we'll actually use in the rest of the
course. This change should be nearly invisible, since most of what's
missing from Sflib has identical definitions in the Coq standard
library. The main reason for doing it is to tidy the global Coq
environment so that, for example, it is easier to search for
relevant theorems. *)
Require Export SfLib.
(* ####################################################### *)
(** * Arithmetic and Boolean Expressions *)
(** We'll present Imp in three parts: first a core language of
_arithmetic and boolean expressions_, then an extension of these
expressions with _variables_, and finally a language of _commands_
including assignment, conditions, sequencing, and loops. *)
(* ####################################################### *)
(** ** Syntax *)
Module AExp.
(** These two definitions specify the _abstract syntax_ of
arithmetic and boolean expressions. *)
Inductive aexp : Type :=
| ANum : nat -> aexp
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp.
Inductive bexp : Type :=
| BTrue : bexp
| BFalse : bexp
| BEq : aexp -> aexp -> bexp
| BLe : aexp -> aexp -> bexp
| BNot : bexp -> bexp
| BAnd : bexp -> bexp -> bexp.
(** In this chapter, we'll elide the translation from the
concrete syntax that a programmer would actually write to these
abstract syntax trees -- the process that, for example, would
translate the string ["1+2*3"] to the AST [APlus (ANum
1) (AMult (ANum 2) (ANum 3))]. The optional chapter [ImpParser]
develops a simple implementation of a lexical analyzer and parser
that can perform this translation. You do _not_ need to
understand that file to understand this one, but if you haven't
taken a course where these techniques are covered (e.g., a
compilers course) you may want to skim it. *)
(** *** *)
(** For comparison, here's a conventional BNF (Backus-Naur Form)
grammar defining the same abstract syntax:
a ::= nat
| a + a
| a - a
| a * a
b ::= true
| false
| a = a
| a <= a
| not b
| b and b
*)
(** Compared to the Coq version above...
- The BNF is more informal -- for example, it gives some
suggestions about the surface syntax of expressions (like the
fact that the addition operation is written [+] and is an
infix symbol) while leaving other aspects of lexical analysis
and parsing (like the relative precedence of [+], [-], and
[*]) unspecified. Some additional information -- and human
intelligence -- would be required to turn this description
into a formal definition (when implementing a compiler, for
example).
The Coq version consistently omits all this information and
concentrates on the abstract syntax only.
- On the other hand, the BNF version is lighter and
easier to read. Its informality makes it flexible, which is
a huge advantage in situations like discussions at the
blackboard, where conveying general ideas is more important
than getting every detail nailed down precisely.
Indeed, there are dozens of BNF-like notations and people
switch freely among them, usually without bothering to say which
form of BNF they're using because there is no need to: a
rough-and-ready informal understanding is all that's
needed. *)
(** It's good to be comfortable with both sorts of notations:
informal ones for communicating between humans and formal ones for
carrying out implementations and proofs. *)
(* ####################################################### *)
(** ** Evaluation *)
(** _Evaluating_ an arithmetic expression produces a number. *)
Fixpoint aeval (a : aexp) : nat :=
match a with
| ANum n => n
| APlus a1 a2 => (aeval a1) + (aeval a2)
| AMinus a1 a2 => (aeval a1) - (aeval a2)
| AMult a1 a2 => (aeval a1) * (aeval a2)
end.
Example test_aeval1:
aeval (APlus (ANum 2) (ANum 2)) = 4.
Proof. reflexivity. Qed.
(** *** *)
(** Similarly, evaluating a boolean expression yields a boolean. *)
Fixpoint beval (b : bexp) : bool :=
match b with
| BTrue => true
| BFalse => false
| BEq a1 a2 => beq_nat (aeval a1) (aeval a2)
| BLe a1 a2 => ble_nat (aeval a1) (aeval a2)
| BNot b1 => negb (beval b1)
| BAnd b1 b2 => andb (beval b1) (beval b2)
end.
(* ####################################################### *)
(** ** Optimization *)
(** We haven't defined very much yet, but we can already get
some mileage out of the definitions. Suppose we define a function
that takes an arithmetic expression and slightly simplifies it,
changing every occurrence of [0+e] (i.e., [(APlus (ANum 0) e])
into just [e]. *)
Fixpoint optimize_0plus (a:aexp) : aexp :=
match a with
| ANum n =>
ANum n
| APlus (ANum 0) e2 =>
optimize_0plus e2
| APlus e1 e2 =>
APlus (optimize_0plus e1) (optimize_0plus e2)
| AMinus e1 e2 =>
AMinus (optimize_0plus e1) (optimize_0plus e2)
| AMult e1 e2 =>
AMult (optimize_0plus e1) (optimize_0plus e2)
end.
(** To make sure our optimization is doing the right thing we
can test it on some examples and see if the output looks OK. *)
Example test_optimize_0plus:
optimize_0plus (APlus (ANum 2)
(APlus (ANum 0)
(APlus (ANum 0) (ANum 1))))
= APlus (ANum 2) (ANum 1).
Proof. reflexivity. Qed.
(** But if we want to be sure the optimization is correct --
i.e., that evaluating an optimized expression gives the same
result as the original -- we should prove it. *)
Theorem optimize_0plus_sound: forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a. induction a.
Case "ANum". reflexivity.
Case "APlus". destruct a1.
SCase "a1 = ANum n". destruct n.
SSCase "n = 0". simpl. apply IHa2.
SSCase "n <> 0". simpl. rewrite IHa2. reflexivity.
SCase "a1 = APlus a1_1 a1_2".
simpl. simpl in IHa1. rewrite IHa1.
rewrite IHa2. reflexivity.
SCase "a1 = AMinus a1_1 a1_2".
simpl. simpl in IHa1. rewrite IHa1.
rewrite IHa2. reflexivity.
SCase "a1 = AMult a1_1 a1_2".
simpl. simpl in IHa1. rewrite IHa1.
rewrite IHa2. reflexivity.
Case "AMinus".
simpl. rewrite IHa1. rewrite IHa2. reflexivity.
Case "AMult".
simpl. rewrite IHa1. rewrite IHa2. reflexivity. Qed.
Theorem optimize_0plus_sound':
forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a. induction a ; try (simpl; rewrite IHa1; rewrite IHa2; reflexivity).
Case "Anum". reflexivity.
Case "APlus". destruct a1; try (simpl; simpl in IHa1; rewrite IHa1; rewrite IHa2; reflexivity).
SCase "a1 = ANum n". destruct n; simpl; rewrite IHa2; reflexivity.
Qed.
Theorem optimize_0plus_sound'':
forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a.
induction a
; try (simpl; rewrite IHa1; rewrite IHa2; reflexivity)
; try reflexivity.
Case "APlus".
destruct a1 ; try (simpl; simpl in IHa1; rewrite IHa1; rewrite IHa2; reflexivity).
SCase "a1 = ANum n". destruct n; simpl; rewrite IHa2; reflexivity.
Qed.
(* ####################################################### *)
(** * Coq Automation *)
(** The repetition in this last proof is starting to be a little
annoying. If either the language of arithmetic expressions or the
optimization being proved sound were significantly more complex,
it would begin to be a real problem.
So far, we've been doing all our proofs using just a small handful
of Coq's tactics and completely ignoring its powerful facilities
for constructing parts of proofs automatically. This section
introduces some of these facilities, and we will see more over the
next several chapters. Getting used to them will take some
energy -- Coq's automation is a power tool -- but it will allow us
to scale up our efforts to more complex definitions and more
interesting properties without becoming overwhelmed by boring,
repetitive, low-level details. *)
(* ####################################################### *)
(** ** Tacticals *)
(** _Tacticals_ is Coq's term for tactics that take other tactics as
arguments -- "higher-order tactics," if you will. *)
(* ####################################################### *)
(** *** The [repeat] Tactical *)
(** The [repeat] tactical takes another tactic and keeps applying
this tactic until the tactic fails. Here is an example showing
that [100] is even using repeat. *)
Theorem ev100 : ev 100.
Proof.
repeat (apply ev_SS). (* applies ev_SS 50 times,
until [apply ev_SS] fails *)
apply ev_0.
Qed.
(* Print ev100. *)
(** The [repeat T] tactic never fails; if the tactic [T] doesn't apply
to the original goal, then repeat still succeeds without changing
the original goal (it repeats zero times). *)
Theorem ev100' : ev 100.
Proof.
repeat (apply ev_0). (* doesn't fail, applies ev_0 zero times *)
repeat (apply ev_SS). apply ev_0. (* we can continue the proof *)
Qed.
(** The [repeat T] tactic does not have any bound on the number of
times it applies [T]. If [T] is a tactic that always succeeds then
repeat [T] will loop forever (e.g. [repeat simpl] loops forever
since [simpl] always succeeds). While Coq's term language is
guaranteed to terminate, Coq's tactic language is not! *)
(* ####################################################### *)
(** *** The [try] Tactical *)
(** If [T] is a tactic, then [try T] is a tactic that is just like [T]
except that, if [T] fails, [try T] _successfully_ does nothing at
all (instead of failing). *)
Theorem silly1 : forall ae, aeval ae = aeval ae.
Proof. try reflexivity. (* this just does [reflexivity] *) Qed.
Theorem silly2 : forall (P : Prop), P -> P.
Proof.
intros P HP.
try reflexivity. (* just [reflexivity] would have failed *)
apply HP. (* we can still finish the proof in some other way *)
Qed.
(** Using [try] in a completely manual proof is a bit silly, but
we'll see below that [try] is very useful for doing automated
proofs in conjunction with the [;] tactical. *)
(* ####################################################### *)
(** *** The [;] Tactical (Simple Form) *)
(** In its most commonly used form, the [;] tactical takes two tactics
as argument: [T;T'] first performs the tactic [T] and then
performs the tactic [T'] on _each subgoal_ generated by [T]. *)
(** For example, consider the following trivial lemma: *)
Lemma foo : forall n, ble_nat 0 n = true.
Proof.
intros.
destruct n.
(* Leaves two subgoals, which are discharged identically... *)
Case "n=0". simpl. reflexivity.
Case "n=Sn'". simpl. reflexivity.
Qed.
(** We can simplify this proof using the [;] tactical: *)
Lemma foo' : forall n, ble_nat 0 n = true.
Proof.
intros.
destruct n; (* [destruct] the current goal *)
simpl; (* then [simpl] each resulting subgoal *)
reflexivity. (* and do [reflexivity] on each resulting subgoal *)
Qed.
(** Using [try] and [;] together, we can get rid of the repetition in
the proof that was bothering us a little while ago. *)
Theorem optimize_0plus_sound''': forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a.
induction a;
(* Most cases follow directly by the IH *)
try (simpl; rewrite IHa1; rewrite IHa2; reflexivity).
(* The remaining cases -- ANum and APlus -- are different *)
Case "ANum". reflexivity.
Case "APlus".
destruct a1;
(* Again, most cases follow directly by the IH *)
try (simpl; simpl in IHa1; rewrite IHa1;
rewrite IHa2; reflexivity).
(* The interesting case, on which the [try...] does nothing,
is when [e1 = ANum n]. In this case, we have to destruct
[n] (to see whether the optimization applies) and rewrite
with the induction hypothesis. *)
SCase "a1 = ANum n". destruct n;
simpl; rewrite IHa2; reflexivity. Qed.
(** Coq experts often use this "[...; try... ]" idiom after a tactic
like [induction] to take care of many similar cases all at once.
Naturally, this practice has an analog in informal proofs.
Here is an informal proof of this theorem that matches the
structure of the formal one:
_Theorem_: For all arithmetic expressions [a],
aeval (optimize_0plus a) = aeval a.
_Proof_: By induction on [a]. The [AMinus] and [AMult] cases
follow directly from the IH. The remaining cases are as follows:
- Suppose [a = ANum n] for some [n]. We must show
aeval (optimize_0plus (ANum n)) = aeval (ANum n).
This is immediate from the definition of [optimize_0plus].
- Suppose [a = APlus a1 a2] for some [a1] and [a2]. We
must show
aeval (optimize_0plus (APlus a1 a2))
= aeval (APlus a1 a2).
Consider the possible forms of [a1]. For most of them,
[optimize_0plus] simply calls itself recursively for the
subexpressions and rebuilds a new expression of the same form
as [a1]; in these cases, the result follows directly from the
IH.
The interesting case is when [a1 = ANum n] for some [n].
If [n = ANum 0], then
optimize_0plus (APlus a1 a2) = optimize_0plus a2
and the IH for [a2] is exactly what we need. On the other
hand, if [n = S n'] for some [n'], then again [optimize_0plus]
simply calls itself recursively, and the result follows from
the IH. [] *)
(** This proof can still be improved: the first case (for [a = ANum
n]) is very trivial -- even more trivial than the cases that we
said simply followed from the IH -- yet we have chosen to write it
out in full. It would be better and clearer to drop it and just
say, at the top, "Most cases are either immediate or direct from
the IH. The only interesting case is the one for [APlus]..." We
can make the same improvement in our formal proof too. Here's how
it looks: *)
Theorem optimize_0plus_sound'''': forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a.
induction a;
(* Most cases follow directly by the IH *)
try (simpl; rewrite IHa1; rewrite IHa2; reflexivity);
(* ... or are immediate by definition *)
try reflexivity.
(* The interesting case is when a = APlus a1 a2. *)
Case "APlus".
destruct a1; try (simpl; simpl in IHa1; rewrite IHa1;
rewrite IHa2; reflexivity).
SCase "a1 = ANum n". destruct n;
simpl; rewrite IHa2; reflexivity. Qed.
(* ####################################################### *)
(** *** The [;] Tactical (General Form) *)
(** The [;] tactical has a more general than the simple [T;T'] we've
seen above, which is sometimes also useful. If [T], [T1], ...,
[Tn] are tactics, then
T; [T1 | T2 | ... | Tn]
is a tactic that first performs [T] and then performs [T1] on the
first subgoal generated by [T], performs [T2] on the second
subgoal, etc.
So [T;T'] is just special notation for the case when all of the
[Ti]'s are the same tactic; i.e. [T;T'] is just a shorthand for:
T; [T' | T' | ... | T']
*)
(* ####################################################### *)
(** ** Defining New Tactic Notations *)
(** Coq also provides several ways of "programming" tactic scripts.
- The [Tactic Notation] idiom illustrated below gives a handy
way to define "shorthand tactics" that bundle several tactics
into a single command.
- For more sophisticated programming, Coq offers a small
built-in programming language called [Ltac] with primitives
that can examine and modify the proof state. The details are
a bit too complicated to get into here (and it is generally
agreed that [Ltac] is not the most beautiful part of Coq's
design!), but they can be found in the reference manual, and
there are many examples of [Ltac] definitions in the Coq
standard library that you can use as examples.
- There is also an OCaml API, which can be used to build tactics
that access Coq's internal structures at a lower level, but
this is seldom worth the trouble for ordinary Coq users.
The [Tactic Notation] mechanism is the easiest to come to grips with,
and it offers plenty of power for many purposes. Here's an example.
*)
Tactic Notation "simpl_and_try" tactic(c) :=
simpl;
try c.
(** This defines a new tactical called [simpl_and_try] which
takes one tactic [c] as an argument, and is defined to be
equivalent to the tactic [simpl; try c]. For example, writing
"[simpl_and_try reflexivity.]" in a proof would be the same as
writing "[simpl; try reflexivity.]" *)
(** The next subsection gives a more sophisticated use of this
feature... *)
(* ####################################################### *)
(** *** Bulletproofing Case Analyses *)
(** Being able to deal with most of the cases of an [induction]
or [destruct] all at the same time is very convenient, but it can
also be a little confusing. One problem that often comes up is
that _maintaining_ proofs written in this style can be difficult.
For example, suppose that, later, we extended the definition of
[aexp] with another constructor that also required a special
argument. The above proof might break because Coq generated the
subgoals for this constructor before the one for [APlus], so that,
at the point when we start working on the [APlus] case, Coq is
actually expecting the argument for a completely different
constructor. What we'd like is to get a sensible error message
saying "I was expecting the [AFoo] case at this point, but the
proof script is talking about [APlus]." Here's a nice trick (due
to Aaron Bohannon) that smoothly achieves this. *)
Tactic Notation "aexp_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ANum" | Case_aux c "APlus"
| Case_aux c "AMinus" | Case_aux c "AMult" ].
(** ([Case_aux] implements the common functionality of [Case],
[SCase], [SSCase], etc. For example, [Case "foo"] is defined as
[Case_aux Case "foo".) *)
(** For example, if [a] is a variable of type [aexp], then doing
aexp_cases (induction a) Case
will perform an induction on [a] (the same as if we had just typed
[induction a]) and _also_ add a [Case] tag to each subgoal
generated by the [induction], labeling which constructor it comes
from. For example, here is yet another proof of
[optimize_0plus_sound], using [aexp_cases]: *)
Theorem optimize_0plus_sound2''': forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a.
aexp_cases (induction a) Case;
try (simpl; rewrite IHa1; rewrite IHa2; reflexivity);
try reflexivity.
(* At this point, there is already an ["APlus"] case name
in the context. The [Case "APlus"] here in the proof
text has the effect of a sanity check: if the "Case"
string in the context is anything _other_ than ["APlus"]
(for example, because we added a clause to the definition
of [aexp] and forgot to change the proof) we'll get a
helpful error at this point telling us that this is now
the wrong case. *)
Case "APlus".
aexp_cases (destruct a1) SCase;
try (simpl; simpl in IHa1;
rewrite IHa1; rewrite IHa2; reflexivity).
SCase "ANum". destruct n;
simpl; rewrite IHa2; reflexivity. Qed.
(** **** Exercise: 3 stars (optimize_0plus_b) *)
(** Since the [optimize_0plus] tranformation doesn't change the value
of [aexp]s, we should be able to apply it to all the [aexp]s that
appear in a [bexp] without changing the [bexp]'s value. Write a
function which performs that transformation on [bexp]s, and prove
it is sound. Use the tacticals we've just seen to make the proof
as elegant as possible. *)
Fixpoint optimize_0plus_b (b : bexp) : bexp :=
match b with
| BTrue => BTrue
| BFalse => BFalse
| BEq a1 a2 => BEq (optimize_0plus a1) (optimize_0plus a2)
| BLe a1 a2 => BLe (optimize_0plus a1) (optimize_0plus a2)
| BNot b1 => BNot (optimize_0plus_b b1)
| BAnd b1 b2 => BAnd (optimize_0plus_b b1) (optimize_0plus_b b2)
end.
Tactic Notation "bexp_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "BTrue" | Case_aux c "BFalse" | Case_aux c "BEq" | Case_aux c "BLe"
| Case_aux c "BNot" | Case_aux c "BAnd" ].
Theorem optimize_0plus_b_sound : forall b,
beval (optimize_0plus_b b) = beval b.
Proof.
intros b.
bexp_cases (induction b) Case;
try (simpl; repeat (rewrite optimize_0plus_sound); reflexivity).
Case "BNot". simpl. rewrite IHb. reflexivity.
Case "BAnd". simpl. rewrite IHb1. rewrite IHb2. reflexivity.
Qed.
(** [] *)
Fixpoint optimize_lit_plus (a:aexp) : aexp :=
match a with
| ANum n => ANum n
| APlus (ANum n1) (ANum n2) =>
ANum (n1 + n2)
| APlus e1 e2 =>
APlus (optimize_lit_plus e1) (optimize_lit_plus e2)
| AMinus e1 e2 =>
AMinus (optimize_lit_plus e1) (optimize_lit_plus e2)
| AMult e1 e2 =>
AMult (optimize_lit_plus e1) (optimize_lit_plus e2)
end.
Example test_optimize_lit_plus :
optimize_lit_plus (APlus (ANum 2) (APlus (ANum 5) (ANum 3)))
= APlus (ANum 2) (ANum 8).
Proof. reflexivity. Qed.
Theorem optimize_lit_plus_sound :
forall a,
aeval (optimize_lit_plus a) = aeval a.
Proof.
intros a.
aexp_cases (induction a) Case; try (simpl; rewrite IHa1; rewrite IHa2; reflexivity).
Case "ANum". reflexivity.
Case "APlus". aexp_cases (destruct a1) SCase ; try (simpl; simpl in IHa1; simpl in IHa2; try rewrite IHa1; try rewrite IHa2; reflexivity).
SCase "ANum". aexp_cases (destruct a2) SSCase ; try (simpl; simpl in IHa1; simpl in IHa2; try rewrite IHa1; try rewrite IHa2; reflexivity).
Qed.
Fixpoint optimize_lit_plus2 (a:aexp) : aexp :=
match a with
| ANum n => ANum n
| APlus (ANum n1) (ANum n2) =>
ANum (n1 + n2)
| APlus e1 e2 => match (optimize_lit_plus2 e1, optimize_lit_plus2 e2) with
| (ANum n1, ANum n2) => ANum (n1 + n2)
| (a, b) => APlus a b
end
| AMinus e1 e2 =>
AMinus (optimize_lit_plus2 e1) (optimize_lit_plus2 e2)
| AMult e1 e2 =>
AMult (optimize_lit_plus2 e1) (optimize_lit_plus2 e2)
end.
Example test_optimize_lit_plus2 :
optimize_lit_plus2 (APlus (ANum 2) (APlus (ANum 5) (ANum 3)))
= (ANum 10).
Proof. compute. reflexivity. Qed.
Theorem optimize_lit_plus_sound2 :
forall a,
aeval (optimize_lit_plus2 a) = aeval a.
Proof.
intros a.
aexp_cases (induction a) Case; try (simpl; rewrite IHa1; rewrite IHa2; reflexivity).
Case "ANum". reflexivity.
Case "APlus". aexp_cases (destruct a1) SCase ; try (simpl; simpl in IHa1; simpl in IHa2; try rewrite IHa1; try rewrite IHa2; reflexivity).
SCase "ANum". aexp_cases (destruct a2) SSCase ; try (simpl; simpl in IHa1; simpl in IHa2; try rewrite IHa1; try rewrite IHa2; reflexivity).
inversion IHa2.
Abort.
(* Can't prove this because the fixpoint induction on the terms doesn't work. *)
(** **** Exercise: 4 stars, optional (optimizer) *)
(** _Design exercise_: The optimization implemented by our
[optimize_0plus] function is only one of many imaginable
optimizations on arithmetic and boolean expressions. Write a more
sophisticated optimizer and prove it correct.
(* FILL IN HERE *)
*)
(** [] *)
(* ####################################################### *)
(** ** The [omega] Tactic *)
(** The [omega] tactic implements a decision procedure for a subset of
first-order logic called _Presburger arithmetic_. It is based on
the Omega algorithm invented in 1992 by William Pugh.
If the goal is a universally quantified formula made out of
- numeric constants, addition ([+] and [S]), subtraction ([-]
and [pred]), and multiplication by constants (this is what
makes it Presburger arithmetic),
- equality ([=] and [<>]) and inequality ([<=]), and
- the logical connectives [/\], [\/], [~], and [->],
then invoking [omega] will either solve the goal or tell you that
it is actually false. *)
Require Import Omega.
Example silly_presburger_example : forall m n o p,
m + n <= n + o /\ o + 3 = p + 3 ->
m <= p.
Proof.
intros. omega.
Qed.
(** Leibniz wrote, "It is unworthy of excellent men to lose
hours like slaves in the labor of calculation which could be
relegated to anyone else if machines were used." We recommend
using the omega tactic whenever possible. *)
(* ####################################################### *)
(** ** A Few More Handy Tactics *)
(** Finally, here are some miscellaneous tactics that you may find
convenient.
- [clear H]: Delete hypothesis [H] from the context.
- [subst x]: Find an assumption [x = e] or [e = x] in the
context, replace [x] with [e] throughout the context and
current goal, and clear the assumption.
- [subst]: Substitute away _all_ assumptions of the form [x = e]
or [e = x].
- [rename... into...]: Change the name of a hypothesis in the
proof context. For example, if the context includes a variable
named [x], then [rename x into y] will change all occurrences
of [x] to [y].
- [assumption]: Try to find a hypothesis [H] in the context that
exactly matches the goal; if one is found, behave just like
[apply H].
- [contradiction]: Try to find a hypothesis [H] in the current
context that is logically equivalent to [False]. If one is
found, solve the goal.
- [constructor]: Try to find a constructor [c] (from some
[Inductive] definition in the current environment) that can be
applied to solve the current goal. If one is found, behave
like [apply c]. *)
(** We'll see many examples of these in the proofs below. *)
(* ####################################################### *)
(** * Evaluation as a Relation *)
(** We have presented [aeval] and [beval] as functions defined by
[Fixpoints]. Another way to think about evaluation -- one that we
will see is often more flexible -- is as a _relation_ between
expressions and their values. This leads naturally to [Inductive]
definitions like the following one for arithmetic
expressions... *)
Module aevalR_first_try.
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum : forall (n: nat),
aevalR (ANum n) n
| E_APlus : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (APlus e1 e2) (n1 + n2)
| E_AMinus: forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (AMinus e1 e2) (n1 - n2)
| E_AMult : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (AMult e1 e2) (n1 * n2).
(** As is often the case with relations, we'll find it
convenient to define infix notation for [aevalR]. We'll write [e
|| n] to mean that arithmetic expression [e] evaluates to value
[n]. (This notation is one place where the limitation to ASCII
symbols becomes a little bothersome. The standard notation for
the evaluation relation is a double down-arrow. We'll typeset it
like this in the HTML version of the notes and use a double
vertical bar as the closest approximation in [.v] files.) *)
Notation "e '||' n" := (aevalR e n) : type_scope.
End aevalR_first_try.
(** In fact, Coq provides a way to use this notation in the definition
of [aevalR] itself. This avoids situations where we're working on
a proof involving statements in the form [e || n] but we have to
refer back to a definition written using the form [aevalR e n].
We do this by first "reserving" the notation, then giving the
definition together with a declaration of what the notation
means. *)
Reserved Notation "e '||' n" (at level 50, left associativity).
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum : forall (n:nat),
(ANum n) || n
| E_APlus : forall (e1 e2: aexp) (n1 n2 : nat),
(e1 || n1) -> (e2 || n2) -> (APlus e1 e2) || (n1 + n2)
| E_AMinus : forall (e1 e2: aexp) (n1 n2 : nat),
(e1 || n1) -> (e2 || n2) -> (AMinus e1 e2) || (n1 - n2)
| E_AMult : forall (e1 e2: aexp) (n1 n2 : nat),
(e1 || n1) -> (e2 || n2) -> (AMult e1 e2) || (n1 * n2)
where "e '||' n" := (aevalR e n) : type_scope.
Tactic Notation "aevalR_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_ANum" | Case_aux c "E_APlus"
| Case_aux c "E_AMinus" | Case_aux c "E_AMult" ].
(* ####################################################### *)
(** ** Inference Rule Notation *)
(** In informal discussions, it is convenient to write the rules for
[aevalR] and similar relations in the more readable graphical form
of _inference rules_, where the premises above the line justify
the conclusion below the line (we have already seen them in the
Prop chapter). *)
(** For example, the constructor [E_APlus]...
| E_APlus : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (APlus e1 e2) (n1 + n2)
...would be written like this as an inference rule:
e1 || n1
e2 || n2
-------------------- (E_APlus)
APlus e1 e2 || n1+n2
*)
(** Formally, there is nothing very deep about inference rules:
they are just implications. You can read the rule name on the
right as the name of the constructor and read each of the
linebreaks between the premises above the line and the line itself
as [->]. All the variables mentioned in the rule ([e1], [n1],
etc.) are implicitly bound by universal quantifiers at the
beginning. (Such variables are often called _metavariables_ to
distinguish them from the variables of the language we are
defining. At the moment, our arithmetic expressions don't include
variables, but we'll soon be adding them.) The whole collection
of rules is understood as being wrapped in an [Inductive]
declaration (informally, this is either elided or else indicated
by saying something like "Let [aevalR] be the smallest relation
closed under the following rules..."). *)
(** For example, [||] is the smallest relation closed under these
rules:
----------- (E_ANum)
ANum n || n
e1 || n1
e2 || n2
-------------------- (E_APlus)
APlus e1 e2 || n1+n2
e1 || n1
e2 || n2
--------------------- (E_AMinus)
AMinus e1 e2 || n1-n2
e1 || n1
e2 || n2
-------------------- (E_AMult)
AMult e1 e2 || n1*n2
*)
(* ####################################################### *)
(** ** Equivalence of the Definitions *)
(** It is straightforward to prove that the relational and functional
definitions of evaluation agree on all possible arithmetic
expressions... *)
Theorem aeval_iff_aevalR : forall a n,
(a || n) <-> aeval a = n.
Proof.
split.
Case "->".
intros H.
aevalR_cases (induction H) SCase; simpl.
SCase "E_ANum".
reflexivity.
SCase "E_APlus".
rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
SCase "E_AMinus".
rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
SCase "E_AMult".
rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
Case "<-".
generalize dependent n.
aexp_cases (induction a) SCase;
simpl; intros; subst.
SCase "ANum".
apply E_ANum.
SCase "APlus".
apply E_APlus.
apply IHa1. reflexivity.
apply IHa2. reflexivity.
SCase "AMinus".
apply E_AMinus.
apply IHa1. reflexivity.
apply IHa2. reflexivity.
SCase "AMult".
apply E_AMult.
apply IHa1. reflexivity.
apply IHa2. reflexivity.
Qed.
(** Note: if you're reading the HTML file, you'll see an empty square box instead
of a proof for this theorem.
You can click on this box to "unfold" the text to see the proof.
Click on the unfolded to text to "fold" it back up to a box. We'll be using
this style frequently from now on to help keep the HTML easier to read.
The full proofs always appear in the .v files. *)
(** We can make the proof quite a bit shorter by making more
use of tacticals... *)
Theorem aeval_iff_aevalR' : forall a n,
(a || n) <-> aeval a = n.
Proof.
(* WORKED IN CLASS *)
split.
Case "->".
intros H; induction H; subst; reflexivity.
Case "<-".
generalize dependent n.
induction a; simpl; intros; subst; constructor;
try apply IHa1; try apply IHa2; reflexivity.
Qed.
(** **** Exercise: 3 stars (bevalR) *)
(** Write a relation [bevalR] in the same style as
[aevalR], and prove that it is equivalent to [beval].*)
Inductive bevalR : bexp -> bool -> Prop :=
| E_BTrue : BTrue || true
| E_BFalse : BFalse || false
| E_BEq : forall (a1 a2 : aexp) (n1 n2 : nat),
aevalR a1 n1 -> aevalR a2 n2 -> (BEq a1 a2) || (beq_nat n1 n2)
| E_BLe : forall (a1 a2 : aexp) (n1 n2 : nat),
aevalR a1 n1 -> aevalR a2 n2 -> (BLe a1 a2) || (ble_nat n1 n2)
| E_BAnd : forall (be1 be2: bexp) (b1 b2 : bool),
be1 || b1 -> be2 || b2 -> (BAnd be1 be2) || (andb b1 b2)
| E_BNot : forall (be : bexp) (b : bool),
be || b -> (BNot be) || negb b
where "e '||' n" := (bevalR e n) : type_scope.
Theorem beval_iff_bevalR' :
forall be b,
bevalR be b <-> beval be = b.
Proof.
split.
Case "->". intros H; induction H; subst; simpl; try reflexivity.
SCase "BEq". rewrite aeval_iff_aevalR' in H. rewrite aeval_iff_aevalR' in H0. rewrite H. rewrite H0. reflexivity.
SCase "BLe". rewrite aeval_iff_aevalR' in H. rewrite aeval_iff_aevalR' in H0. rewrite H. rewrite H0. reflexivity.
Case "<-".
generalize dependent b.
induction be; simpl; intros; subst; constructor; try (try apply IHbe ; try apply IHbe1 ; try apply IHbe2 ; reflexivity).
SCase "BEq".
rewrite aeval_iff_aevalR'; reflexivity.
rewrite aeval_iff_aevalR'; reflexivity.
SCase "BLe".
rewrite aeval_iff_aevalR'; reflexivity.
rewrite aeval_iff_aevalR'; reflexivity.
Qed.
Lemma APlus_eval_eq :
forall n1 n2,
aevalR (ANum n1) n2 <-> n1 = n2.
Proof.
split.
Case "->". intros H. inversion H. reflexivity.
Case "<-". intros H. rewrite H. constructor.
Qed.
Theorem optimize_lit_plus_sound2 :
forall a n,
aevalR a n -> aevalR (optimize_lit_plus a) n.
Proof.
intros.
induction H.
Case "ANum". simpl. constructor.
Case "APlus". simpl. induction e1.
SCase "ANum". apply APlus_eval_eq in H. induction e2.
SSCase "ANum". apply APlus_eval_eq in H0. simpl in IHaevalR1. simpl in IHaevalR2. simpl. rewrite H. rewrite H0. constructor.
Abort.
(** [] *)
End AExp.
(* ####################################################### *)
(** ** Computational vs. Relational Definitions *)
(** For the definitions of evaluation for arithmetic and boolean
expressions, the choice of whether to use functional or relational
definitions is mainly a matter of taste. In general, Coq has
somewhat better support for working with relations. On the other
hand, in some sense function definitions carry more information,
because functions are necessarily deterministic and defined on all
arguments; for a relation we have to show these properties
explicitly if we need them. Functions also take advantage of Coq's
computations mechanism.
However, there are circumstances where relational definitions of
evaluation are preferable to functional ones. *)
Module aevalR_division.
(** For example, suppose that we wanted to extend the arithmetic
operations by considering also a division operation:*)
Inductive aexp : Type :=
| ANum : nat -> aexp
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp
| ADiv : aexp -> aexp -> aexp. (* <--- new *)
(** Extending the definition of [aeval] to handle this new operation
would not be straightforward (what should we return as the result
of [ADiv (ANum 5) (ANum 0)]?). But extending [aevalR] is
straightforward. *)
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum : forall (n:nat),
(ANum n) || n
| E_APlus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (APlus a1 a2) || (n1 + n2)
| E_AMinus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (AMinus a1 a2) || (n1 - n2)
| E_AMult : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (AMult a1 a2) || (n1 * n2)
| E_ADiv : forall (a1 a2: aexp) (n1 n2 n3: nat),
(a1 || n1) -> (a2 || n2) -> (mult n2 n3 = n1) -> (ADiv a1 a2) || n3
where "a '||' n" := (aevalR a n) : type_scope.
End aevalR_division.
Module aevalR_extended.
(** Suppose, instead, that we want to extend the arithmetic operations
by a nondeterministic number generator [any]:*)
Inductive aexp : Type :=
| AAny : aexp (* <--- NEW *)
| ANum : nat -> aexp
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp.
(** Again, extending [aeval] would be tricky (because evaluation is
_not_ a deterministic function from expressions to numbers), but
extending [aevalR] is no problem: *)
Inductive aevalR : aexp -> nat -> Prop :=
| E_Any : forall (n:nat),
AAny || n (* <--- new *)
| E_ANum : forall (n:nat),
(ANum n) || n
| E_APlus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (APlus a1 a2) || (n1 + n2)
| E_AMinus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (AMinus a1 a2) || (n1 - n2)
| E_AMult : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (AMult a1 a2) || (n1 * n2)
where "a '||' n" := (aevalR a n) : type_scope.
End aevalR_extended.
(** * Expressions With Variables *)
(** Let's turn our attention back to defining Imp. The next thing we
need to do is to enrich our arithmetic and boolean expressions
with variables. To keep things simple, we'll assume that all
variables are global and that they only hold numbers. *)
(* ##################################################### *)
(** ** Identifiers *)
(** To begin, we'll need to formalize _identifiers_ such as program
variables. We could use strings for this -- or, in a real
compiler, fancier structures like pointers into a symbol table.
But for simplicity let's just use natural numbers as identifiers. *)
(** (We hide this section in a module because these definitions are
actually in [SfLib], but we want to repeat them here so that we
can explain them.) *)
Module Id.
(** We define a new inductive datatype [Id] so that we won't confuse
identifiers and numbers. We use [sumbool] to define a computable
equality operator on [Id]. *)
Inductive id : Type :=
Id : nat -> id.
Eval compute in {1 = 1} + {2 = 2}.
Theorem eq_id_dec : forall id1 id2 : id, {id1 = id2} + {id1 <> id2}.
Proof.
intros id1 id2.
destruct id1 as [n1]. destruct id2 as [n2].
destruct (eq_nat_dec n1 n2) as [Heq | Hneq].
Case "n1 = n2".
left. rewrite Heq. reflexivity.
Case "n1 <> n2".
right. intros contra. inversion contra. apply Hneq. apply H0.
Defined.
(** The following lemmas will be useful for rewriting terms involving [eq_id_dec]. *)
Lemma eq_id : forall (T:Type) x (p q:T),
(if eq_id_dec x x then p else q) = p.
Proof.
intros.
destruct (eq_id_dec x x).
Case "x = x".
reflexivity.
Case "x <> x (impossible)".
apply ex_falso_quodlibet; apply n; reflexivity. Qed.
(** **** Exercise: 1 star, optional (neq_id) *)
Lemma neq_id : forall (T:Type) x y (p q:T), x <> y ->
(if eq_id_dec x y then p else q) = q.
Proof.
intros.
destruct (eq_id_dec x y).
rewrite e in H. apply ex_falso_quodlibet. apply H. reflexivity.
reflexivity.
Qed.
(** [] *)
End Id.
(* ####################################################### *)
(** ** States *)
(** A _state_ represents the current values of _all_ the variables at
some point in the execution of a program. *)
(** For simplicity (to avoid dealing with partial functions), we
let the state be defined for _all_ variables, even though any
given program is only going to mention a finite number of them.
The state captures all of the information stored in memory. For Imp
programs, because each variable stores only a natural number, we
can represent the state as a mapping from identifiers to [nat].
For more complex programming languages, the state might have more
structure.
*)
Definition state := id -> nat.
Definition empty_state : state :=
fun _ => 0.
Definition update (st : state) (x : id) (n : nat) : state :=
fun x' => if eq_id_dec x x' then n else st x'.
(** For proofs involving states, we'll need several simple properties
of [update]. *)
(** **** Exercise: 1 star (update_eq) *)
Theorem update_eq : forall n x st,
(update st x n) x = n.
Proof.
intros n x st.
unfold update. rewrite eq_id. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 1 star (update_neq) *)
Theorem update_neq : forall x2 x1 n st,
x2 <> x1 ->
(update st x2 n) x1 = (st x1).
Proof.
intros. unfold update. rewrite neq_id. reflexivity.
apply H.
Qed.
(** [] *)
(** **** Exercise: 1 star (update_example) *)
(** Before starting to play with tactics, make sure you understand
exactly what the theorem is saying! *)
Theorem update_example : forall (n:nat),
(update empty_state (Id 2) n) (Id 3) = 0.
Proof.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 1 star (update_shadow) *)
Theorem update_shadow : forall n1 n2 x1 x2 (st : state),
(update (update st x2 n1) x2 n2) x1 = (update st x2 n2) x1.
Proof.
intros. unfold update. destruct (eq_id_dec x2 x1) eqn:H; reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars (update_same) *)
Theorem update_same : forall n1 x1 x2 (st : state),
st x1 = n1 ->
(update st x1 n1) x2 = st x2.
Proof.
intros. unfold update. destruct (eq_id_dec x1 x2).
Case "x1 = x2".
rewrite <- H. rewrite e. reflexivity.
Case "x1 != x2". reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars (update_permute) *)
Theorem update_permute : forall n1 n2 x1 x2 x3 st,
x2 <> x1 ->
(update (update st x2 n1) x1 n2) x3 = (update (update st x1 n2) x2 n1) x3.
Proof.
intros. unfold update.
destruct (eq_id_dec x1 x3); destruct (eq_id_dec x2 x3); try reflexivity.
Case "x1 = x3, x2 = x3, but x2 <> x1".
rewrite e in H. contradiction.
Qed.
(** [] *)
(* ################################################### *)
(** ** Syntax *)
(** We can add variables to the arithmetic expressions we had before by
simply adding one more constructor: *)
Inductive aexp : Type :=
| ANum : nat -> aexp
| AId : id -> aexp (* <----- NEW *)
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp.
Tactic Notation "aexp_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ANum" | Case_aux c "AId" | Case_aux c "APlus"
| Case_aux c "AMinus" | Case_aux c "AMult" ].
(** Defining a few variable names as notational shorthands will make
examples easier to read: *)
Definition X : id := Id 0.
Definition Y : id := Id 1.
Definition Z : id := Id 2.
(** (This convention for naming program variables ([X], [Y],
[Z]) clashes a bit with our earlier use of uppercase letters for
types. Since we're not using polymorphism heavily in this part of
the course, this overloading should not cause confusion.) *)
(** The definition of [bexp]s is the same as before (using the new
[aexp]s): *)
Inductive bexp : Type :=
| BTrue : bexp
| BFalse : bexp
| BEq : aexp -> aexp -> bexp
| BLe : aexp -> aexp -> bexp
| BNot : bexp -> bexp
| BAnd : bexp -> bexp -> bexp.
Tactic Notation "bexp_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "BTrue" | Case_aux c "BFalse" | Case_aux c "BEq"
| Case_aux c "BLe" | Case_aux c "BNot" | Case_aux c "BAnd" ].
(* ################################################### *)
(** ** Evaluation *)
(** The arith and boolean evaluators can be extended to handle
variables in the obvious way: *)
Fixpoint aeval (st : state) (a : aexp) : nat :=
match a with
| ANum n => n
| AId x => st x (* <----- NEW *)
| APlus a1 a2 => (aeval st a1) + (aeval st a2)
| AMinus a1 a2 => (aeval st a1) - (aeval st a2)
| AMult a1 a2 => (aeval st a1) * (aeval st a2)
end.
Fixpoint beval (st : state) (b : bexp) : bool :=
match b with
| BTrue => true
| BFalse => false
| BEq a1 a2 => beq_nat (aeval st a1) (aeval st a2)
| BLe a1 a2 => ble_nat (aeval st a1) (aeval st a2)
| BNot b1 => negb (beval st b1)
| BAnd b1 b2 => andb (beval st b1) (beval st b2)
end.
Example aexp1 :
aeval (update empty_state X 5)
(APlus (ANum 3) (AMult (AId X) (ANum 2)))
= 13.
Proof. reflexivity. Qed.
Example bexp1 :
beval (update empty_state X 5)
(BAnd BTrue (BNot (BLe (AId X) (ANum 4))))
= true.
Proof. reflexivity. Qed.
(* ####################################################### *)
(** * Commands *)
(** Now we are ready define the syntax and behavior of Imp
_commands_ (often called _statements_). *)
(* ################################################### *)
(** ** Syntax *)
(** Informally, commands [c] are described by the following BNF
grammar:
c ::= SKIP
| x ::= a
| c ;; c
| WHILE b DO c END
| IFB b THEN c ELSE c FI
]]
*)
(**
For example, here's the factorial function in Imp.
Z ::= X;;
Y ::= 1;;
WHILE not (Z = 0) DO
Y ::= Y * Z;;
Z ::= Z - 1
END
When this command terminates, the variable [Y] will contain the
factorial of the initial value of [X].
*)
(** Here is the formal definition of the syntax of commands: *)
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";;"
| Case_aux c "IFB" | Case_aux c "WHILE" ].
(** As usual, we can use a few [Notation] declarations to make things
more readable. We need to be a bit careful to avoid conflicts
with Coq's built-in notations, so we'll keep this light -- in
particular, we won't introduce any notations for [aexps] and
[bexps] to avoid confusion with the numerical and boolean
operators we've already defined. We use the keyword [IFB] for
conditionals instead of [IF], for similar reasons. *)
Notation "'SKIP'" :=
CSkip.
Notation "x '::=' a" :=
(CAss x a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' c1 'THEN' c2 'ELSE' c3 'FI'" :=
(CIf c1 c2 c3) (at level 80, right associativity).
(** For example, here is the factorial function again, written as a
formal definition to Coq: *)
Definition fact_in_coq : com :=
Z ::= AId X;;
Y ::= ANum 1;;
WHILE BNot (BEq (AId Z) (ANum 0)) DO
Y ::= AMult (AId Y) (AId Z);;
Z ::= AMinus (AId Z) (ANum 1)
END.
(* ####################################################### *)
(** ** Examples *)
(** Assignment: *)
Definition plus2 : com :=
X ::= (APlus (AId X) (ANum 2)).
Definition XtimesYinZ : com :=
Z ::= (AMult (AId X) (AId Y)).
Definition subtract_slowly_body : com :=
Z ::= AMinus (AId Z) (ANum 1) ;;
X ::= AMinus (AId X) (ANum 1).
(** *** Loops *)
Definition subtract_slowly : com :=
WHILE BNot (BEq (AId X) (ANum 0)) DO
subtract_slowly_body
END.
Definition subtract_3_from_5_slowly : com :=
X ::= ANum 3 ;;
Z ::= ANum 5 ;;
subtract_slowly.
(** *** An infinite loop: *)
Definition loop : com :=
WHILE BTrue DO
SKIP
END.
(* ################################################################ *)
(** * Evaluation *)
(** Next we need to define what it means to evaluate an Imp command.
The fact that [WHILE] loops don't necessarily terminate makes defining
an evaluation function tricky... *)
(* #################################### *)
(** ** Evaluation as a Function (Failed Attempt) *)
(** Here's an attempt at defining an evaluation function for commands,
omitting the [WHILE] case. *)
Fixpoint ceval_fun_no_while (st : state) (c : com) : state :=
match c with
| SKIP =>
st
| x ::= a1 =>
update st x (aeval st a1)
| c1 ;; c2 =>
let st' := ceval_fun_no_while st c1 in
ceval_fun_no_while st' c2
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_fun_no_while st c1
else ceval_fun_no_while st c2
| WHILE b DO c END =>
st (* bogus *)
end.
(** In a traditional functional programming language like ML or
Haskell we could write the [WHILE] case as follows:
<<
Fixpoint ceval_fun (st : state) (c : com) : state :=
match c with
...
| WHILE b DO c END =>
if (beval st b1)
then ceval_fun st (c1; WHILE b DO c END)
else st
end.
>>
Coq doesn't accept such a definition ("Error: Cannot guess
decreasing argument of fix") because the function we want to
define is not guaranteed to terminate. Indeed, it doesn't always
terminate: for example, the full version of the [ceval_fun]
function applied to the [loop] program above would never
terminate. Since Coq is not just a functional programming
language, but also a consistent logic, any potentially
non-terminating function needs to be rejected. Here is
an (invalid!) Coq program showing what would go wrong if Coq
allowed non-terminating recursive functions:
<<
Fixpoint loop_false (n : nat) : False := loop_false n.
>>
That is, propositions like [False] would become provable
(e.g. [loop_false 0] would be a proof of [False]), which
would be a disaster for Coq's logical consistency.
Thus, because it doesn't terminate on all inputs, the full version
of [ceval_fun] cannot be written in Coq -- at least not without
additional tricks (see chapter [ImpCEvalFun] if curious). *)
(* #################################### *)
(** ** Evaluation as a Relation *)
(** Here's a better way: we define [ceval] as a _relation_ rather than
a _function_ -- i.e., we define it in [Prop] instead of [Type], as
we did for [aevalR] above. *)
(** This is an important change. Besides freeing us from the awkward
workarounds that would be needed to define evaluation as a
function, it gives us a lot more flexibility in the definition.
For example, if we added concurrency features to the language,
we'd want the definition of evaluation to be non-deterministic --
i.e., not only would it not be total, it would not even be a
partial function! *)
(** We'll use the notation [c / st || st'] for our [ceval] relation:
[c / st || st'] means that executing program [c] in a starting
state [st] results in an ending state [st']. This can be
pronounced "[c] takes state [st] to [st']".
*)
(** *** Operational Semantics
---------------- (E_Skip)
SKIP / st || st
aeval st a1 = n
-------------------------------- (E_Ass)
x := a1 / st || (update st x n)
c1 / st || st'
c2 / st' || st''
------------------- (E_Seq)
c1;;c2 / st || st''
beval st b1 = true
c1 / st || st'
------------------------------------- (E_IfTrue)
IF b1 THEN c1 ELSE c2 FI / st || st'
beval st b1 = false
c2 / st || st'
------------------------------------- (E_IfFalse)
IF b1 THEN c1 ELSE c2 FI / st || st'
beval st b1 = false
------------------------------ (E_WhileEnd)
WHILE b DO c END / st || st
beval st b1 = true
c / st || st'
WHILE b DO c END / st' || st''
--------------------------------- (E_WhileLoop)
WHILE b DO c END / st || st''
*)
(** Here is the formal definition. (Make sure you understand
how it corresponds to the inference rules.) *)
Reserved Notation "c1 '/' st '||' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st,
SKIP / st || st
| E_Ass : forall st a1 n x,
aeval st a1 = n ->
(x ::= a1) / st || (update st x n)
| E_Seq : forall c1 c2 st st' st'',
c1 / st || st' ->
c2 / st' || st'' ->
(c1 ;; c2) / st || st''
| E_IfTrue : forall st st' b c1 c2,
beval st b = true ->
c1 / st || st' ->
(IFB b THEN c1 ELSE c2 FI) / st || st'
| E_IfFalse : forall st st' b c1 c2,
beval st b = false ->
c2 / st || st' ->
(IFB b THEN c1 ELSE c2 FI) / st || st'
| E_WhileEnd : forall b st c,
beval st b = false ->
(WHILE b DO c END) / st || st
| E_WhileLoop : forall st st' st'' b c,
beval st b = true ->
c / st || st' ->
(WHILE b DO c END) / st' || st'' ->
(WHILE b DO c END) / st || st''
where "c1 '/' st '||' st'" := (ceval c1 st st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass" | Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop" ].
(** *** *)
(** The cost of defining evaluation as a relation instead of a
function is that we now need to construct _proofs_ that some
program evaluates to some result state, rather than just letting
Coq's computation mechanism do it for us. *)
Example ceval_example1:
(X ::= ANum 2;;
IFB BLe (AId X) (ANum 1)
THEN Y ::= ANum 3
ELSE Z ::= ANum 4
FI)
/ empty_state
|| (update (update empty_state X 2) Z 4).
Proof.
(* We must supply the intermediate state *)
apply E_Seq with (update empty_state X 2).
Case "assignment command".
apply E_Ass. reflexivity.
Case "if command".
apply E_IfFalse.
reflexivity.
apply E_Ass. reflexivity. Qed.
(** **** Exercise: 2 stars (ceval_example2) *)
Example ceval_example2:
(X ::= ANum 0;; Y ::= ANum 1;; Z ::= ANum 2) / empty_state ||
(update (update (update empty_state X 0) Y 1) Z 2).
Proof.
apply E_Seq with (update empty_state X 0).
apply E_Ass. reflexivity.
apply E_Seq with (update (update empty_state X 0) Y 1).
apply E_Ass. reflexivity.
apply E_Ass. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced (pup_to_n) *)
(** Write an Imp program that sums the numbers from [1] to
[X] (inclusive: [1 + 2 + ... + X]) in the variable [Y].
Prove that this program executes as intended for X = 2
(this latter part is trickier than you might expect). *)
Definition pup_to_n : com :=
(Y ::= ANum 0 ;;
WHILE BLe (ANum 1) (AId X)
DO (Y ::= (APlus (AId Y) (AId X)) ;;
X ::= (AMinus (AId X) (ANum 1)))
END).
Theorem pup_to_2_ceval :
pup_to_n / (update empty_state X 2) ||
update (update (update (update (update (update empty_state
X 2) Y 0) Y 2) X 1) Y 3) X 0.
Proof.
unfold pup_to_n.
apply E_Seq with (update (update empty_state X 2) Y 0).
Case "y = 0". apply E_Ass. reflexivity.
apply E_WhileLoop with (update (update (update (update empty_state X 2) Y 0) Y 2) X 1).
Case "first iteration".
SCase "while check". reflexivity.
SCase "while body".
apply E_Seq with (update (update (update empty_state X 2) Y 0) Y 2).
SSCase "y += x".
apply E_Ass. reflexivity.
SSCase "x--".
apply E_Ass. reflexivity.
apply E_WhileLoop with (update
(update
(update (update (update (update empty_state X 2) Y 0) Y 2) X 1) Y
3) X 0).
Case "second iteration".
SCase "while check". reflexivity.
SCase "while body".
apply E_Seq with (update (update (update (update (update empty_state X 2) Y 0) Y 2) X 1) Y 3).
apply E_Ass. reflexivity.
apply E_Ass. reflexivity.
apply E_WhileEnd. reflexivity.
Qed.
(** [] *)
(* ####################################################### *)
(** ** Determinism of Evaluation *)
(** Changing from a computational to a relational definition of
evaluation is a good move because it allows us to escape from the
artificial requirement (imposed by Coq's restrictions on
[Fixpoint] definitions) that evaluation should be a total
function. But it also raises a question: Is the second definition
of evaluation actually a partial function? That is, is it
possible that, beginning from the same state [st], we could
evaluate some command [c] in different ways to reach two different
output states [st'] and [st'']?
In fact, this cannot happen: [ceval] is a partial function.
Here's the proof: *)
Theorem ceval_deterministic: forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2.
generalize dependent st2.
ceval_cases (induction E1) Case;
intros st2 E2; inversion E2; subst.
Case "E_Skip". reflexivity.
Case "E_Ass". reflexivity.
Case "E_Seq".
assert (st' = st'0) as EQ1.
SCase "Proof of assertion". apply IHE1_1. assumption.
subst st'0.
apply IHE1_2. assumption.
Case "E_IfTrue".
SCase "b1 evaluates to true".
apply IHE1. assumption.
SCase "b1 evaluates to false (contradiction)".
rewrite H in H5. inversion H5.
Case "E_IfFalse".
SCase "b1 evaluates to true (contradiction)".
rewrite H in H5. inversion H5.
SCase "b1 evaluates to false".
apply IHE1. assumption.
Case "E_WhileEnd".
SCase "b1 evaluates to false".
reflexivity.
SCase "b1 evaluates to true (contradiction)".
rewrite H in H2. inversion H2.
Case "E_WhileLoop".
SCase "b1 evaluates to false (contradiction)".
rewrite H in H4. inversion H4.
SCase "b1 evaluates to true".
assert (st' = st'0) as EQ1.
SSCase "Proof of assertion". apply IHE1_1; assumption.
subst st'0.
apply IHE1_2. assumption. Qed.
(* ####################################################### *)
(** * Reasoning About Imp Programs *)
(** We'll get much deeper into systematic techniques for reasoning
about Imp programs in the following chapters, but we can do quite
a bit just working with the bare definitions. *)
(* This section explores some examples. *)
Theorem plus2_spec : forall st n st',
st X = n ->
plus2 / st || st' ->
st' X = n + 2.
Proof.
intros st n st' HX Heval.
(* Inverting Heval essentially forces Coq to expand one
step of the ceval computation - in this case revealing
that st' must be st extended with the new value of X,
since plus2 is an assignment *)
inversion Heval. subst. clear Heval. simpl.
apply update_eq. Qed.
(** **** Exercise: 3 stars (XtimesYinZ_spec) *)
(** State and prove a specification of [XtimesYinZ]. *)
Theorem x_times_y_in_z_spec :
forall st n1 n2 st',
st X = n1 ->
st Y = n2 ->
XtimesYinZ / st || st' ->
st' Z = n1 * n2.
Proof.
intros st n1 n2 st'.
intros HX HY Heval.
inversion Heval. subst. simpl.
apply update_eq.
Qed.
(** [] *)
(** **** Exercise: 3 stars (loop_never_stops) *)
Theorem loop_never_stops : forall st st',
~(loop / st || st').
Proof.
intros st st' contra. unfold loop in contra.
remember (WHILE BTrue DO SKIP END) as loopdef eqn:Heqloopdef.
(* Proceed by induction on the assumed derivation showing that
[loopdef] terminates. Most of the cases are immediately
contradictory (and so can be solved in one step with
[inversion]). *)
induction contra; inversion Heqloopdef; subst.
Case "WHILE True". inversion H.
Case "WHILE End". apply IHcontra2 in Heqloopdef. inversion Heqloopdef.
Qed.
(** **** Exercise: 3 stars (no_whilesR) *)
(** Consider the definition of the [no_whiles] property below: *)
Fixpoint no_whiles (c : com) : bool :=
match c with
| SKIP => true
| _ ::= _ => true
| c1 ;; c2 => andb (no_whiles c1) (no_whiles c2)
| IFB _ THEN ct ELSE cf FI => andb (no_whiles ct) (no_whiles cf)
| WHILE _ DO _ END => false
end.
(** This property yields [true] just on programs that
have no while loops. Using [Inductive], write a property
[no_whilesR] such that [no_whilesR c] is provable exactly when [c]
is a program with no while loops. Then prove its equivalence
with [no_whiles]. *)
Inductive no_whilesR: com -> Prop :=
(* FILL IN HERE *)
| NW_Skip : no_whilesR SKIP
| NW_Ass : forall a x, no_whilesR (x ::= a)
| NW_Seq : forall c1 c2,
no_whilesR c1
-> no_whilesR c2
-> no_whilesR (c1 ;; c2)
| NW_IfTrue : forall b c1 c2,
no_whilesR c1
-> no_whilesR c2
-> no_whilesR (IFB b THEN c1 ELSE c2 FI).
Theorem no_whiles_eqv:
forall c, no_whiles c = true <-> no_whilesR c.
Proof.
split.
Case "->".
intros H.
induction c; simpl; try (constructor);
try (apply IHc1; apply andb_true_elim1 in H; apply H);
try (apply IHc2; apply andb_true_elim2 in H; apply H).
inversion H.
Case "<-".
induction c; simpl; try (reflexivity).
SCase "c1 ;; c2".
intros H. inversion H. subst. apply IHc1 in H2. apply IHc2 in H3. rewrite H2. rewrite H3. reflexivity.
SCase "IF".
intros H. inversion H. subst. apply IHc1 in H2. apply IHc2 in H4. rewrite H2. rewrite H4. reflexivity.
SCase "WHILE".
intros H. inversion H.
Qed.
(** [] *)
(** **** Exercise: 4 stars (no_whiles_terminating) *)
(** Imp programs that don't involve while loops always terminate.
State and prove a theorem [no_whiles_terminating] that says this. *)
(** (Use either [no_whiles] or [no_whilesR], as you prefer.) *)
Theorem no_whiles_terminating : forall prog st,
no_whilesR prog -> (exists st', prog / st || st').
Proof.
intros. generalize dependent st.
induction prog.
Case "SKIP". intros st. exists st. constructor.
Case "::=". intros st. exists (update st i (aeval st a)). constructor. reflexivity.
Case ";;". intros st. inversion H; subst.
assert (exists st', prog1 / st || st') as terminate_prog1. apply IHprog1. apply H2. inversion terminate_prog1 as [st'].
assert (exists st'', prog2 / st' || st'') as terminate_prog2. apply IHprog2. apply H3. inversion terminate_prog2 as [st''].
exists st''. apply E_Seq with st'; assumption.
Case "IF". intros st. inversion H; subst.
assert (exists st1, prog1 / st || st1) as terminate_prog1. apply IHprog1. apply H2. inversion terminate_prog1 as [st1].
assert (exists st2, prog2 / st || st2) as terminate_prog2. apply IHprog2. apply H4. inversion terminate_prog2 as [st2].
clear terminate_prog1. clear terminate_prog2. clear H2. clear H4.
destruct (beval st b) eqn:BE.
SCase "beval st b = true". exists st1. apply E_IfTrue. assumption. apply H0.
SCase "beval st b = false". exists st2. apply E_IfFalse. assumption. apply H1.
Case "WHILE". intros st. inversion H.
Qed.
(** [] *)
(* ####################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 3 stars (stack_compiler) *)
(** HP Calculators, programming languages like Forth and Postscript,
and abstract machines like the Java Virtual Machine all evaluate
arithmetic expressions using a stack. For instance, the expression
<<
(2*3)+(3*(4-2))
>>
would be entered as
<<
2 3 * 3 4 2 - * +
>>
and evaluated like this:
<<
[] | 2 3 * 3 4 2 - * +
[2] | 3 * 3 4 2 - * +
[3, 2] | * 3 4 2 - * +
[6] | 3 4 2 - * +
[3, 6] | 4 2 - * +
[4, 3, 6] | 2 - * +
[2, 4, 3, 6] | - * +
[2, 3, 6] | * +
[6, 6] | +
[12] |
>>
The task of this exercise is to write a small compiler that
translates [aexp]s into stack machine instructions.
The instruction set for our stack language will consist of the
following instructions:
- [SPush n]: Push the number [n] on the stack.
- [SLoad x]: Load the identifier [x] from the store and push it
on the stack
- [SPlus]: Pop the two top numbers from the stack, add them, and
push the result onto the stack.
- [SMinus]: Similar, but subtract.
- [SMult]: Similar, but multiply. *)
Inductive sinstr : Type :=
| SPush : nat -> sinstr
| SLoad : id -> sinstr
| SPlus : sinstr
| SMinus : sinstr
| SMult : sinstr.
Tactic Notation "sinstr_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SPush" | Case_aux c "SLoad" | Case_aux c "SPlus" | Case_aux c "SMinus" | Case_aux c "SMult" ].
(** Write a function to evaluate programs in the stack language. It
takes as input a state, a stack represented as a list of
numbers (top stack item is the head of the list), and a program
represented as a list of instructions, and returns the stack after
executing the program. Test your function on the examples below.
Note that the specification leaves unspecified what to do when
encountering an [SPlus], [SMinus], or [SMult] instruction if the
stack contains less than two elements. In a sense, it is
immaterial what we do, since our compiler will never emit such a
malformed program. *)
Definition s_execute_binop (stack : list nat) (op : nat -> nat -> nat) : list nat :=
match stack with
| nil => nil
| n :: nil => [n]
| n1 :: n2 :: t => (op n2 n1) :: t
end.
Fixpoint s_execute (st : state) (stack : list nat)
(prog : list sinstr)
: list nat :=
match prog with
| nil => stack
| h :: t => s_execute st (match h with
| SPush n => n :: stack
| SLoad id => (st id) :: stack
| SPlus => s_execute_binop stack plus
| SMinus => s_execute_binop stack minus
| SMult => s_execute_binop stack mult
end) t
end.
Example s_execute1 :
s_execute empty_state []
[SPush 5; SPush 3; SPush 1; SMinus]
= [2; 5].
Proof. reflexivity. Qed.
Example s_execute2 :
s_execute (update empty_state X 3) [3;4]
[SPush 4; SLoad X; SMult; SPlus]
= [15; 4].
Proof. simpl. reflexivity. Qed.
(** Next, write a function which compiles an [aexp] into a stack
machine program. The effect of running the program should be the
same as pushing the value of the expression on the stack. *)
Fixpoint s_compile (e : aexp) : list sinstr :=
match e with
| AId id => [SLoad id]
| ANum n => [SPush n]
| APlus a1 a2 => (s_compile a1) ++ (s_compile a2) ++ [SPlus]
| AMinus a1 a2 => (s_compile a1) ++ (s_compile a2) ++ [SMinus]
| AMult a1 a2 => (s_compile a1) ++ (s_compile a2) ++ [SMult]
end.
(** After you've defined [s_compile], prove the following to test
that it works. *)
Example s_compile1 :
s_compile (AMinus (AId X) (AMult (ANum 2) (AId Y)))
= [SLoad X; SPush 2; SLoad Y; SMult; SMinus].
Proof.
simpl. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced (stack_compiler_correct) *)
(** The task of this exercise is to prove the correctness of the
compiler implemented in the previous exercise. Remember that
the specification left unspecified what to do when encountering an
[SPlus], [SMinus], or [SMult] instruction if the stack contains
less than two elements. (In order to make your correctness proof
easier you may find it useful to go back and change your
implementation!)
Prove the following theorem, stating that the [compile] function
behaves correctly. You will need to start by stating a more
general lemma to get a usable induction hypothesis; the main
theorem will then be a simple corollary of this lemma. *)
Theorem s_compile_single : forall (st : state) (e : aexp) (l : list sinstr) (stack : list nat),
s_execute st stack (s_compile e ++ l) = s_execute st ((aeval st e)::stack) l.
Proof.
intros st e.
aexp_cases (induction e) Case; intros l stack; simpl;
try (repeat (rewrite <- app_assoc); rewrite IHe1; rewrite IHe2);
reflexivity.
Qed.
Theorem s_compile_correct : forall (st : state) (e : aexp),
s_execute st [] (s_compile e) = [ aeval st e ].
Proof.
intros st e.
aexp_cases (induction e) Case; simpl; try (repeat (rewrite s_compile_single)); reflexivity.
Qed.
(** [] *)
(** **** Exercise: 5 stars, advanced (break_imp) *)
Module BreakImp.
(** Imperative languages such as C or Java often have a [break] or
similar statement for interrupting the execution of loops. In this
exercise we will consider how to add [break] to Imp.
First, we need to enrich the language of commands with an
additional case. *)
Inductive com : Type :=
| CSkip : com
| CBreak : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "BREAK" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" ].
Notation "'SKIP'" :=
CSkip.
Notation "'BREAK'" :=
CBreak.
Notation "x '::=' a" :=
(CAss x a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' c1 'THEN' c2 'ELSE' c3 'FI'" :=
(CIf c1 c2 c3) (at level 80, right associativity).
(** Next, we need to define the behavior of [BREAK]. Informally,
whenever [BREAK] is executed in a sequence of commands, it stops
the execution of that sequence and signals that the innermost
enclosing loop (if any) should terminate. If there aren't any
enclosing loops, then the whole program simply terminates. The
final state should be the same as the one in which the [BREAK]
statement was executed.
One important point is what to do when there are multiple loops
enclosing a given [BREAK]. In those cases, [BREAK] should only
terminate the _innermost_ loop where it occurs. Thus, after
executing the following piece of code...
X ::= 0;;
Y ::= 1;;
WHILE 0 <> Y DO
WHILE TRUE DO
BREAK
END;;
X ::= 1;;
Y ::= Y - 1
END
... the value of [X] should be [1], and not [0].
One way of expressing this behavior is to add another parameter to
the evaluation relation that specifies whether evaluation of a
command executes a [BREAK] statement: *)
Inductive status : Type :=
| SContinue : status
| SBreak : status.
Reserved Notation "c1 '/' st '||' s '/' st'"
(at level 40, st, s at level 39).
(** Intuitively, [c / st || s / st'] means that, if [c] is started in
state [st], then it terminates in state [st'] and either signals
that any surrounding loop (or the whole program) should exit
immediately ([s = SBreak]) or that execution should continue
normally ([s = SContinue]).
The definition of the "[c / st || s / st']" relation is very
similar to the one we gave above for the regular evaluation
relation ([c / st || s / st']) -- we just need to handle the
termination signals appropriately:
- If the command is [SKIP], then the state doesn't change, and
execution of any enclosing loop can continue normally.
- If the command is [BREAK], the state stays unchanged, but we
signal a [SBreak].
- If the command is an assignment, then we update the binding for
that variable in the state accordingly and signal that execution
can continue normally.
- If the command is of the form [IF b THEN c1 ELSE c2 FI], then
the state is updated as in the original semantics of Imp, except
that we also propagate the signal from the execution of
whichever branch was taken.
- If the command is a sequence [c1 ; c2], we first execute
[c1]. If this yields a [SBreak], we skip the execution of [c2]
and propagate the [SBreak] signal to the surrounding context;
the resulting state should be the same as the one obtained by
executing [c1] alone. Otherwise, we execute [c2] on the state
obtained after executing [c1], and propagate the signal that was
generated there.
- Finally, for a loop of the form [WHILE b DO c END], the
semantics is almost the same as before. The only difference is
that, when [b] evaluates to true, we execute [c] and check the
signal that it raises. If that signal is [SContinue], then the
execution proceeds as in the original semantics. Otherwise, we
stop the execution of the loop, and the resulting state is the
same as the one resulting from the execution of the current
iteration. In either case, since [BREAK] only terminates the
innermost loop, [WHILE] signals [SContinue]. *)
(** Based on the above description, complete the definition of the
[ceval] relation. *)
Inductive ceval : com -> state -> status -> state -> Prop :=
| E_Skip : forall st,
CSkip / st || SContinue / st
(* FILL IN HERE *)
where "c1 '/' st '||' s '/' st'" := (ceval c1 st s st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip"
(* FILL IN HERE *)
].
(** Now the following properties of your definition of [ceval]: *)
Theorem break_ignore : forall c st st' s,
(BREAK;; c) / st || s / st' ->
st = st'.
Proof.
(* FILL IN HERE *) Admitted.
Theorem while_continue : forall b c st st' s,
(WHILE b DO c END) / st || s / st' ->
s = SContinue.
Proof.
(* FILL IN HERE *) Admitted.
Theorem while_stops_on_break : forall b c st st',
beval st b = true ->
c / st || SBreak / st' ->
(WHILE b DO c END) / st || SContinue / st'.
Proof.
(* FILL IN HERE *) Admitted.
(** **** Exercise: 3 stars, advanced, optional (while_break_true) *)
Theorem while_break_true : forall b c st st',
(WHILE b DO c END) / st || SContinue / st' ->
beval st' b = true ->
exists st'', c / st'' || SBreak / st'.
Proof.
(* FILL IN HERE *) Admitted.
(** **** Exercise: 4 stars, advanced, optional (ceval_deterministic) *)
Theorem ceval_deterministic: forall (c:com) st st1 st2 s1 s2,
c / st || s1 / st1 ->
c / st || s2 / st2 ->
st1 = st2 /\ s1 = s2.
Proof.
(* FILL IN HERE *) Admitted.
End BreakImp.
(** [] *)
(** **** Exercise: 3 stars, optional (short_circuit) *)
(** Most modern programming languages use a "short-circuit" evaluation
rule for boolean [and]: to evaluate [BAnd b1 b2], first evaluate
[b1]. If it evaluates to [false], then the entire [BAnd]
expression evaluates to [false] immediately, without evaluating
[b2]. Otherwise, [b2] is evaluated to determine the result of the
[BAnd] expression.
Write an alternate version of [beval] that performs short-circuit
evaluation of [BAnd] in this manner, and prove that it is
equivalent to [beval]. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 4 stars, optional (add_for_loop) *)
(** Add C-style [for] loops to the language of commands, update the
[ceval] definition to define the semantics of [for] loops, and add
cases for [for] loops as needed so that all the proofs in this file
are accepted by Coq.
A [for] loop should be parameterized by (a) a statement executed
initially, (b) a test that is run on each iteration of the loop to
determine whether the loop should continue, (c) a statement
executed at the end of each loop iteration, and (d) a statement
that makes up the body of the loop. (You don't need to worry
about making up a concrete Notation for [for] loops, but feel free
to play with this too if you like.) *)
(* FILL IN HERE *)
(** [] *)
(* <$Date: 2014-12-26 15:20:26 -0500 (Fri, 26 Dec 2014) $ *)
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:57:50 08/25/2009
// Design Name:
// Module Name: mcu_cmd
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mcu_cmd(
input clk,
input cmd_ready,
input param_ready,
input [7:0] cmd_data,
input [7:0] param_data,
output [2:0] mcu_mapper,
output reg mcu_rrq = 0,
output mcu_write,
output reg mcu_wrq = 0,
input mcu_rq_rdy,
output [7:0] mcu_data_out,
input [7:0] mcu_data_in,
output [7:0] spi_data_out,
input [31:0] spi_byte_cnt,
input [2:0] spi_bit_cnt,
output [23:0] addr_out,
output [23:0] saveram_mask_out,
output [23:0] rom_mask_out,
// SD "DMA" extension
output SD_DMA_EN,
input SD_DMA_STATUS,
input SD_DMA_NEXTADDR,
input [7:0] SD_DMA_SRAM_DATA,
input SD_DMA_SRAM_WE,
output [1:0] SD_DMA_TGT,
output SD_DMA_PARTIAL,
output [10:0] SD_DMA_PARTIAL_START,
output [10:0] SD_DMA_PARTIAL_END,
output reg SD_DMA_START_MID_BLOCK,
output reg SD_DMA_END_MID_BLOCK,
// DAC
output [10:0] dac_addr_out,
input DAC_STATUS,
output reg dac_play_out = 0,
output reg dac_reset_out = 0,
output reg [2:0] dac_vol_select_out = 3'b000,
output reg dac_palmode_out = 0,
output reg [8:0] dac_ptr_out = 0,
// MSU data
output [13:0] msu_addr_out,
input [7:0] MSU_STATUS,
output [5:0] msu_status_reset_out,
output [5:0] msu_status_set_out,
output msu_status_reset_we,
input [31:0] msu_addressrq,
input [15:0] msu_trackrq,
input [7:0] msu_volumerq,
output [13:0] msu_ptr_out,
output msu_reset_out,
// feature enable
output reg [7:0] featurebits_out,
// cx4
output reg cx4_reset_out,
output reg region_out,
// SNES sync/clk
input snes_sysclk,
// snes cmd interface
input [7:0] snescmd_data_in,
output reg [7:0] snescmd_data_out,
output reg [8:0] snescmd_addr_out,
output reg snescmd_we_out,
// cheat configuration
output reg [7:0] cheat_pgm_idx_out,
output reg [31:0] cheat_pgm_data_out,
output reg cheat_pgm_we_out,
// DSP core features
output reg [15:0] dsp_feat_out = 16'h0000
);
initial begin
cx4_reset_out = 1'b1;
region_out = 0;
SD_DMA_START_MID_BLOCK = 0;
SD_DMA_END_MID_BLOCK = 0;
end
wire [31:0] snes_sysclk_freq;
clk_test snes_clk_test (
.clk(clk),
.sysclk(snes_sysclk),
.snes_sysclk_freq(snes_sysclk_freq)
);
reg [2:0] MAPPER_BUF;
reg [23:0] ADDR_OUT_BUF;
reg [10:0] DAC_ADDR_OUT_BUF;
reg [7:0] DAC_VOL_OUT_BUF;
reg [13:0] MSU_ADDR_OUT_BUF;
reg [13:0] MSU_PTR_OUT_BUF;
reg [5:0] msu_status_set_out_buf;
reg [5:0] msu_status_reset_out_buf;
reg msu_status_reset_we_buf = 0;
reg MSU_RESET_OUT_BUF;
reg [31:0] SNES_SYSCLK_FREQ_BUF;
reg [7:0] MCU_DATA_OUT_BUF;
reg [7:0] MCU_DATA_IN_BUF;
reg [2:0] mcu_nextaddr_buf;
reg [7:0] dsp_feat_tmp;
wire mcu_nextaddr;
reg DAC_STATUSr;
reg SD_DMA_STATUSr;
reg [7:0] MSU_STATUSr;
always @(posedge clk) begin
DAC_STATUSr <= DAC_STATUS;
SD_DMA_STATUSr <= SD_DMA_STATUS;
MSU_STATUSr <= MSU_STATUS;
end
reg SD_DMA_PARTIALr;
assign SD_DMA_PARTIAL = SD_DMA_PARTIALr;
reg SD_DMA_ENr;
assign SD_DMA_EN = SD_DMA_ENr;
reg [1:0] SD_DMA_TGTr;
assign SD_DMA_TGT = SD_DMA_TGTr;
reg [10:0] SD_DMA_PARTIAL_STARTr;
reg [10:0] SD_DMA_PARTIAL_ENDr;
assign SD_DMA_PARTIAL_START = SD_DMA_PARTIAL_STARTr;
assign SD_DMA_PARTIAL_END = SD_DMA_PARTIAL_ENDr;
reg [23:0] SAVERAM_MASK;
reg [23:0] ROM_MASK;
assign spi_data_out = MCU_DATA_IN_BUF;
initial begin
ADDR_OUT_BUF = 0;
DAC_ADDR_OUT_BUF = 0;
MSU_ADDR_OUT_BUF = 0;
SD_DMA_ENr = 0;
SD_DMA_PARTIALr = 0;
end
// command interpretation
always @(posedge clk) begin
snescmd_we_out <= 1'b0;
cheat_pgm_we_out <= 1'b0;
dac_reset_out <= 1'b0;
MSU_RESET_OUT_BUF <= 1'b0;
if (cmd_ready) begin
case (cmd_data[7:4])
4'h4: begin// SD DMA
SD_DMA_ENr <= 1;
SD_DMA_TGTr <= cmd_data[1:0];
SD_DMA_PARTIALr <= cmd_data[2];
end
4'h8: SD_DMA_TGTr <= 2'b00;
4'h9: SD_DMA_TGTr <= 2'b00; // cmd_data[1:0]; // not implemented
// 4'hE:
// select memory unit
endcase
end else if (param_ready) begin
casex (cmd_data[7:0])
8'h1x:
case (spi_byte_cnt)
32'h2:
ROM_MASK[23:16] <= param_data;
32'h3:
ROM_MASK[15:8] <= param_data;
32'h4:
ROM_MASK[7:0] <= param_data;
endcase
8'h2x:
case (spi_byte_cnt)
32'h2:
SAVERAM_MASK[23:16] <= param_data;
32'h3:
SAVERAM_MASK[15:8] <= param_data;
32'h4:
SAVERAM_MASK[7:0] <= param_data;
endcase
8'h4x:
SD_DMA_ENr <= 1'b0;
8'h6x:
case (spi_byte_cnt)
32'h2: begin
SD_DMA_START_MID_BLOCK <= param_data[7];
SD_DMA_PARTIAL_STARTr[10:9] <= param_data[1:0];
end
32'h3:
SD_DMA_PARTIAL_STARTr[8:0] <= {param_data, 1'b0};
32'h4: begin
SD_DMA_END_MID_BLOCK <= param_data[7];
SD_DMA_PARTIAL_ENDr[10:9] <= param_data[1:0];
end
32'h5:
SD_DMA_PARTIAL_ENDr[8:0] <= {param_data, 1'b0};
endcase
8'h9x:
MCU_DATA_OUT_BUF <= param_data;
8'hd0:
case (spi_byte_cnt)
32'h2:
snescmd_addr_out[7:0] <= param_data;
32'h3:
snescmd_addr_out[8] <= param_data[0];
endcase
8'hd1:
snescmd_addr_out <= snescmd_addr_out + 1;
8'hd2: begin
case (spi_byte_cnt)
32'h2:
snescmd_we_out <= 1'b1;
32'h3:
snescmd_addr_out <= snescmd_addr_out + 1;
endcase
snescmd_data_out <= param_data;
end
8'hd3: begin
case (spi_byte_cnt)
32'h2:
cheat_pgm_idx_out <= param_data[2:0];
32'h3:
cheat_pgm_data_out[31:24] <= param_data;
32'h4:
cheat_pgm_data_out[23:16] <= param_data;
32'h5:
cheat_pgm_data_out[15:8] <= param_data;
32'h6: begin
cheat_pgm_data_out[7:0] <= param_data;
cheat_pgm_we_out <= 1'b1;
end
endcase
end
8'he0:
case (spi_byte_cnt)
32'h2: begin
msu_status_set_out_buf <= param_data[5:0];
end
32'h3: begin
msu_status_reset_out_buf <= param_data[5:0];
msu_status_reset_we_buf <= 1'b1;
end
32'h4:
msu_status_reset_we_buf <= 1'b0;
endcase
8'he1: // pause DAC
dac_play_out <= 1'b0;
8'he2: // resume DAC
dac_play_out <= 1'b1;
8'he3: // reset DAC (set DAC playback address = 0)
case (spi_byte_cnt)
32'h2:
dac_ptr_out[8] <= param_data[0];
32'h3: begin
dac_ptr_out[7:0] <= param_data;
dac_reset_out <= 1'b1; // reset by default value, see above
end
endcase
8'he4: // reset MSU read buffer pointer
case (spi_byte_cnt)
32'h2: begin
MSU_PTR_OUT_BUF[13:8] <= param_data[5:0];
MSU_PTR_OUT_BUF[7:0] <= 8'h0;
end
32'h3: begin
MSU_PTR_OUT_BUF[7:0] <= param_data;
MSU_RESET_OUT_BUF <= 1'b1;
end
endcase
8'heb: // put cx4 into reset
cx4_reset_out <= param_data[0];
8'hec: // set DAC properties
begin
dac_vol_select_out <= param_data[2:0];
dac_palmode_out <= param_data[7];
end
8'hed:
featurebits_out <= param_data;
8'hee:
region_out <= param_data[0];
8'hef:
case (spi_byte_cnt)
32'h2: dsp_feat_tmp <= param_data[7:0];
32'h3: begin
dsp_feat_out <= {dsp_feat_tmp, param_data[7:0]};
end
endcase
endcase
end
end
always @(posedge clk) begin
if(param_ready && cmd_data[7:4] == 4'h0) begin
case (cmd_data[1:0])
2'b01: begin
case (spi_byte_cnt)
32'h2: begin
DAC_ADDR_OUT_BUF[10:8] <= param_data[2:0];
DAC_ADDR_OUT_BUF[7:0] <= 8'b0;
end
32'h3:
DAC_ADDR_OUT_BUF[7:0] <= param_data;
endcase
end
2'b10: begin
case (spi_byte_cnt)
32'h2: begin
MSU_ADDR_OUT_BUF[13:8] <= param_data[5:0];
MSU_ADDR_OUT_BUF[7:0] <= 8'b0;
end
32'h3:
MSU_ADDR_OUT_BUF[7:0] <= param_data;
endcase
end
default:
case (spi_byte_cnt)
32'h2: begin
ADDR_OUT_BUF[23:16] <= param_data;
ADDR_OUT_BUF[15:0] <= 16'b0;
end
32'h3:
ADDR_OUT_BUF[15:8] <= param_data;
32'h4:
ADDR_OUT_BUF[7:0] <= param_data;
endcase
endcase
end else if (SD_DMA_NEXTADDR | (mcu_nextaddr & (cmd_data[7:5] == 3'h4)
&& (cmd_data[3])
&& (spi_byte_cnt >= (32'h1+cmd_data[4])))
) begin
case (SD_DMA_TGTr)
2'b00: ADDR_OUT_BUF <= ADDR_OUT_BUF + 1;
2'b01: DAC_ADDR_OUT_BUF <= DAC_ADDR_OUT_BUF + 1;
2'b10: MSU_ADDR_OUT_BUF <= MSU_ADDR_OUT_BUF + 1;
endcase
end
end
// value fetch during last SPI bit
always @(posedge clk) begin
if (cmd_data[7:4] == 4'h8 && mcu_nextaddr)
MCU_DATA_IN_BUF <= mcu_data_in;
else if (cmd_ready | param_ready /* bit_cnt == 7 */) begin
if (cmd_data[7:4] == 4'hA)
MCU_DATA_IN_BUF <= snescmd_data_in;
if (cmd_data[7:0] == 8'hF0)
MCU_DATA_IN_BUF <= 8'hA5;
else if (cmd_data[7:0] == 8'hF1)
case (spi_byte_cnt[0])
1'b1: // buffer status (1st byte)
MCU_DATA_IN_BUF <= {SD_DMA_STATUSr, DAC_STATUSr, MSU_STATUSr[7], 5'b0};
1'b0: // control status (2nd byte)
MCU_DATA_IN_BUF <= {1'b0, MSU_STATUSr[6:0]};
endcase
else if (cmd_data[7:0] == 8'hF2)
case (spi_byte_cnt)
32'h1:
MCU_DATA_IN_BUF <= msu_addressrq[31:24];
32'h2:
MCU_DATA_IN_BUF <= msu_addressrq[23:16];
32'h3:
MCU_DATA_IN_BUF <= msu_addressrq[15:8];
32'h4:
MCU_DATA_IN_BUF <= msu_addressrq[7:0];
endcase
else if (cmd_data[7:0] == 8'hF3)
case (spi_byte_cnt)
32'h1:
MCU_DATA_IN_BUF <= msu_trackrq[15:8];
32'h2:
MCU_DATA_IN_BUF <= msu_trackrq[7:0];
endcase
else if (cmd_data[7:0] == 8'hF4)
MCU_DATA_IN_BUF <= msu_volumerq;
else if (cmd_data[7:0] == 8'hFE)
case (spi_byte_cnt)
32'h1:
SNES_SYSCLK_FREQ_BUF <= snes_sysclk_freq;
32'h2:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[31:24];
32'h3:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[23:16];
32'h4:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[15:8];
32'h5:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[7:0];
endcase
else if (cmd_data[7:0] == 8'hFF)
MCU_DATA_IN_BUF <= param_data;
else if (cmd_data[7:0] == 8'hD1)
MCU_DATA_IN_BUF <= snescmd_data_in;
end
end
// nextaddr pulse generation
always @(posedge clk) begin
mcu_nextaddr_buf <= {mcu_nextaddr_buf[1:0], mcu_rq_rdy};
end
always @(posedge clk) begin
mcu_rrq <= 1'b0;
if((param_ready | cmd_ready) && cmd_data[7:4] == 4'h8) begin
mcu_rrq <= 1'b1;
end
end
always @(posedge clk) begin
mcu_wrq <= 1'b0;
if(param_ready && cmd_data[7:4] == 4'h9) begin
mcu_wrq <= 1'b1;
end
end
// trigger for nextaddr
assign mcu_nextaddr = mcu_nextaddr_buf == 2'b01;
assign mcu_write = SD_DMA_STATUS
?(SD_DMA_TGTr == 2'b00
? SD_DMA_SRAM_WE
: 1'b1
)
: 1'b1;
assign addr_out = ADDR_OUT_BUF;
assign dac_addr_out = DAC_ADDR_OUT_BUF;
assign msu_addr_out = MSU_ADDR_OUT_BUF;
assign msu_status_reset_we = msu_status_reset_we_buf;
assign msu_status_reset_out = msu_status_reset_out_buf;
assign msu_status_set_out = msu_status_set_out_buf;
assign msu_reset_out = MSU_RESET_OUT_BUF;
assign msu_ptr_out = MSU_PTR_OUT_BUF;
assign mcu_data_out = SD_DMA_STATUS ? SD_DMA_SRAM_DATA : MCU_DATA_OUT_BUF;
assign rom_mask_out = ROM_MASK;
assign saveram_mask_out = SAVERAM_MASK;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR4B_4_V
`define SKY130_FD_SC_LP__OR4B_4_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog wrapper for or4b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__or4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or4b_4 (
X ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or4b_4 (
X ,
A ,
B ,
C ,
D_N
);
output X ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR4B_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A32O_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__A32O_PP_BLACKBOX_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a32o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A32O_PP_BLACKBOX_V
|
Require Import Coq.Lists.List.
Require Import Coq.omega.Omega.
Require Import Coq.Arith.Peano_dec.
Require Import Coq.Classes.Morphisms.
Require Import Crypto.Tactics.VerdiTactics.
Require Import Coq.Numbers.Natural.Peano.NPeano.
Require Import Crypto.Util.NatUtil.
Require Export Crypto.Util.FixCoqMistakes.
Create HintDb distr_length discriminated.
Create HintDb simpl_set_nth discriminated.
Create HintDb simpl_update_nth discriminated.
Create HintDb simpl_nth_default discriminated.
Create HintDb simpl_nth_error discriminated.
Create HintDb simpl_firstn discriminated.
Create HintDb simpl_skipn discriminated.
Create HintDb simpl_fold_right discriminated.
Create HintDb simpl_sum_firstn discriminated.
Create HintDb pull_nth_error discriminated.
Create HintDb push_nth_error discriminated.
Create HintDb pull_nth_default discriminated.
Create HintDb push_nth_default discriminated.
Create HintDb pull_firstn discriminated.
Create HintDb push_firstn discriminated.
Create HintDb pull_skipn discriminated.
Create HintDb push_skipn discriminated.
Create HintDb pull_update_nth discriminated.
Create HintDb push_update_nth discriminated.
Create HintDb znonzero discriminated.
Hint Extern 1 => progress autorewrite with distr_length in * : distr_length.
Ltac distr_length := autorewrite with distr_length in *;
try solve [simpl in *; omega].
Module Export List.
Local Set Implicit Arguments.
Import ListNotations.
(** From the 8.6 Standard Library *)
Section Elts.
Variable A : Type.
(** Results about [nth_error] *)
Lemma nth_error_In l n (x : A) : nth_error l n = Some x -> In x l.
Proof.
revert n. induction l as [|a l IH]; intros [|n]; simpl; try easy.
- injection 1; auto.
- eauto.
Qed.
End Elts.
Section Map.
Variables (A : Type) (B : Type).
Variable f : A -> B.
Lemma map_cons (x:A)(l:list A) : map f (x::l) = (f x) :: (map f l).
Proof.
reflexivity.
Qed.
End Map.
Lemma in_seq len start n :
In n (seq start len) <-> start <= n < start+len.
Proof.
revert start. induction len; simpl; intros.
- rewrite <- plus_n_O. split;[easy|].
intros (H,H'). apply (Lt.lt_irrefl _ (Lt.le_lt_trans _ _ _ H H')).
- rewrite IHlen, <- plus_n_Sm; simpl; split.
* intros [H|H]; subst; intuition auto with arith.
* intros (H,H'). destruct (Lt.le_lt_or_eq _ _ H); intuition.
Qed.
Section Facts.
Variable A : Type.
Theorem length_zero_iff_nil (l : list A):
length l = 0 <-> l=[].
Proof.
split; [now destruct l | now intros ->].
Qed.
End Facts.
Section Repeat.
Variable A : Type.
Fixpoint repeat (x : A) (n: nat ) :=
match n with
| O => []
| S k => x::(repeat x k)
end.
Theorem repeat_length x n:
length (repeat x n) = n.
Proof.
induction n as [| k Hrec]; simpl; rewrite ?Hrec; reflexivity.
Qed.
Theorem repeat_spec n x y:
In y (repeat x n) -> y=x.
Proof.
induction n as [|k Hrec]; simpl; destruct 1; auto.
Qed.
End Repeat.
(******************************************************)
(** ** Operations on lists of pairs or lists of lists *)
(******************************************************)
Section ListPairs.
Variables (A : Type) (B : Type).
(** [split] derives two lists from a list of pairs *)
Fixpoint split (l:list (A*B)) : list A * list B :=
match l with
| [] => ([], [])
| (x,y) :: tl => let (left,right) := split tl in (x::left, y::right)
end.
Lemma in_split_l : forall (l:list (A*B))(p:A*B),
In p l -> In (fst p) (fst (split l)).
Proof.
induction l; simpl; intros; auto.
destruct p; destruct a; destruct (split l); simpl in *.
destruct H.
injection H; auto.
right; apply (IHl (_,_) H).
Qed.
Lemma in_split_r : forall (l:list (A*B))(p:A*B),
In p l -> In (snd p) (snd (split l)).
Proof.
induction l; simpl; intros; auto.
destruct p; destruct a; destruct (split l); simpl in *.
destruct H.
injection H; auto.
right; apply (IHl (_,_) H).
Qed.
Lemma split_nth : forall (l:list (A*B))(n:nat)(d:A*B),
nth n l d = (nth n (fst (split l)) (fst d), nth n (snd (split l)) (snd d)).
Proof.
induction l.
destruct n; destruct d; simpl; auto.
destruct n; destruct d; simpl; auto.
destruct a; destruct (split l); simpl; auto.
destruct (split l); simpl in *; auto.
apply IHl.
Qed.
Lemma split_length_l : forall (l:list (A*B)),
length (fst (split l)) = length l.
Proof.
induction l; simpl; auto.
Qed.
Lemma split_length_r : forall (l:list (A*B)),
length (snd (split l)) = length l.
Proof.
induction l; simpl; auto.
Qed.
(** [combine] is the opposite of [split].
Lists given to [combine] are meant to be of same length.
If not, [combine] stops on the shorter list *)
Fixpoint combine (l : list A) (l' : list B) : list (A*B) :=
match l,l' with
| x::tl, y::tl' => (x,y)::(combine tl tl')
| _, _ => nil
end.
Lemma split_combine : forall (l: list (A*B)),
let (l1,l2) := split l in combine l1 l2 = l.
Proof.
induction l.
simpl; auto.
destruct a; simpl.
destruct (split l); simpl in *.
f_equal; auto.
Qed.
Lemma combine_split : forall (l:list A)(l':list B), length l = length l' ->
split (combine l l') = (l,l').
Proof.
induction l, l'; simpl; trivial; try discriminate.
now intros [= ->%IHl].
Qed.
Lemma in_combine_l : forall (l:list A)(l':list B)(x:A)(y:B),
In (x,y) (combine l l') -> In x l.
Proof.
induction l.
simpl; auto.
destruct l'; simpl; auto; intros.
contradiction.
destruct H.
injection H; auto.
right; apply IHl with l' y; auto.
Qed.
Lemma in_combine_r : forall (l:list A)(l':list B)(x:A)(y:B),
In (x,y) (combine l l') -> In y l'.
Proof.
induction l.
simpl; intros; contradiction.
destruct l'; simpl; auto; intros.
destruct H.
injection H; auto.
right; apply IHl with x; auto.
Qed.
Lemma combine_length : forall (l:list A)(l':list B),
length (combine l l') = min (length l) (length l').
Proof.
induction l.
simpl; auto.
destruct l'; simpl; auto.
Qed.
Lemma combine_nth : forall (l:list A)(l':list B)(n:nat)(x:A)(y:B),
length l = length l' ->
nth n (combine l l') (x,y) = (nth n l x, nth n l' y).
Proof.
induction l; destruct l'; intros; try discriminate.
destruct n; simpl; auto.
destruct n; simpl in *; auto.
Qed.
(** [list_prod] has the same signature as [combine], but unlike
[combine], it adds every possible pairs, not only those at the
same position. *)
Fixpoint list_prod (l:list A) (l':list B) :
list (A * B) :=
match l with
| nil => nil
| cons x t => (map (fun y:B => (x, y)) l')++(list_prod t l')
end.
Lemma in_prod_aux :
forall (x:A) (y:B) (l:list B),
In y l -> In (x, y) (map (fun y0:B => (x, y0)) l).
Proof.
induction l;
[ simpl; auto
| simpl; destruct 1 as [H1| ];
[ left; rewrite H1; trivial | right; auto ] ].
Qed.
Lemma in_prod :
forall (l:list A) (l':list B) (x:A) (y:B),
In x l -> In y l' -> In (x, y) (list_prod l l').
Proof.
induction l;
[ simpl; tauto
| simpl; intros; apply in_or_app; destruct H;
[ left; rewrite H; apply in_prod_aux; assumption | right; auto ] ].
Qed.
Lemma in_prod_iff :
forall (l:list A)(l':list B)(x:A)(y:B),
In (x,y) (list_prod l l') <-> In x l /\ In y l'.
Proof.
split; [ | intros; apply in_prod; intuition ].
induction l; simpl; intros.
intuition.
destruct (in_app_or _ _ _ H); clear H.
destruct (in_map_iff (fun y : B => (a, y)) l' (x,y)) as (H1,_).
destruct (H1 H0) as (z,(H2,H3)); clear H0 H1.
injection H2 as -> ->; intuition.
intuition.
Qed.
Lemma prod_length : forall (l:list A)(l':list B),
length (list_prod l l') = (length l) * (length l').
Proof.
induction l; simpl; auto.
intros.
rewrite app_length.
rewrite map_length.
auto.
Qed.
End ListPairs.
Section Cutting.
Variable A : Type.
Local Notation firstn := (@firstn A).
Lemma firstn_nil n: firstn n [] = [].
Proof. induction n; now simpl. Qed.
Lemma firstn_cons n a l: firstn (S n) (a::l) = a :: (firstn n l).
Proof. now simpl. Qed.
Lemma firstn_all l: firstn (length l) l = l.
Proof. induction l as [| ? ? H]; simpl; [reflexivity | now rewrite H]. Qed.
Lemma firstn_all2 n: forall (l:list A), (length l) <= n -> firstn n l = l.
Proof. induction n as [|k iHk].
- intro. inversion 1 as [H1|?].
rewrite (length_zero_iff_nil l) in H1. subst. now simpl.
- destruct l as [|x xs]; simpl.
* now reflexivity.
* simpl. intro H. apply Peano.le_S_n in H. f_equal. apply iHk, H.
Qed.
Lemma firstn_O l: firstn 0 l = [].
Proof. now simpl. Qed.
Lemma firstn_le_length n: forall l:list A, length (firstn n l) <= n.
Proof.
induction n as [|k iHk]; simpl; [auto | destruct l as [|x xs]; simpl].
- auto with arith.
- apply le_n_S, iHk.
Qed.
Lemma firstn_length_le: forall l:list A, forall n:nat,
n <= length l -> length (firstn n l) = n.
Proof. induction l as [|x xs Hrec].
- simpl. intros n H. apply le_n_0_eq in H. rewrite <- H. now simpl.
- destruct n.
* now simpl.
* simpl. intro H. apply le_S_n in H. now rewrite (Hrec n H).
Qed.
Lemma firstn_app n:
forall l1 l2,
firstn n (l1 ++ l2) = (firstn n l1) ++ (firstn (n - length l1) l2).
Proof. induction n as [|k iHk]; intros l1 l2.
- now simpl.
- destruct l1 as [|x xs].
* unfold List.firstn at 2, length. now rewrite 2!app_nil_l, <- minus_n_O.
* rewrite <- app_comm_cons. simpl. f_equal. apply iHk.
Qed.
Lemma firstn_app_2 n:
forall l1 l2,
firstn ((length l1) + n) (l1 ++ l2) = l1 ++ firstn n l2.
Proof. induction n as [| k iHk];intros l1 l2.
- unfold List.firstn at 2. rewrite <- plus_n_O, app_nil_r.
rewrite firstn_app. rewrite <- minus_diag_reverse.
unfold List.firstn at 2. rewrite app_nil_r. apply firstn_all.
- destruct l2 as [|x xs].
* simpl. rewrite app_nil_r. apply firstn_all2. auto with arith.
* rewrite firstn_app. assert (H0 : (length l1 + S k - length l1) = S k).
auto with arith.
rewrite H0, firstn_all2; [reflexivity | auto with arith].
Qed.
Lemma firstn_firstn:
forall l:list A,
forall i j : nat,
firstn i (firstn j l) = firstn (min i j) l.
Proof. induction l as [|x xs Hl].
- intros. simpl. now rewrite ?firstn_nil.
- destruct i.
* intro. now simpl.
* destruct j.
+ now simpl.
+ simpl. f_equal. apply Hl.
Qed.
End Cutting.
End List.
Hint Rewrite
@app_length
@rev_length
@map_length
@seq_length
@fold_left_length
@split_length_l
@split_length_r
@firstn_length
@combine_length
@prod_length
: distr_length.
Hint Rewrite @firstn_skipn : simpl_firstn.
Hint Rewrite @firstn_skipn : simpl_skipn.
Hint Rewrite @firstn_nil @firstn_cons @List.firstn_all @firstn_O @firstn_app_2 @List.firstn_firstn : push_firstn.
Hint Rewrite @firstn_nil @firstn_cons @List.firstn_all @firstn_O @firstn_app_2 @List.firstn_firstn : simpl_firstn.
Hint Rewrite @firstn_app : push_firstn.
Hint Rewrite <- @firstn_cons @firstn_app @List.firstn_firstn : pull_firstn.
Hint Rewrite @firstn_all2 @removelast_firstn @firstn_removelast using omega : push_firstn.
Hint Rewrite @firstn_all2 @removelast_firstn @firstn_removelast using omega : simpl_firstn.
Local Arguments value / _ _.
Local Arguments error / _.
Definition sum_firstn l n := fold_right Z.add 0%Z (firstn n l).
Fixpoint map2 {A B C} (f : A -> B -> C) (la : list A) (lb : list B) : list C :=
match la with
| nil => nil
| a :: la' => match lb with
| nil => nil
| b :: lb' => f a b :: map2 f la' lb'
end
end.
(* xs[n] := f xs[n] *)
Fixpoint update_nth {T} n f (xs:list T) {struct n} :=
match n with
| O => match xs with
| nil => nil
| x'::xs' => f x'::xs'
end
| S n' => match xs with
| nil => nil
| x'::xs' => x'::update_nth n' f xs'
end
end.
(* xs[n] := x *)
Definition set_nth {T} n x (xs:list T)
:= update_nth n (fun _ => x) xs.
Definition splice_nth {T} n (x:T) xs := firstn n xs ++ x :: skipn (S n) xs.
Hint Unfold splice_nth.
Ltac boring :=
simpl; intuition auto with zarith datatypes;
repeat match goal with
| [ H : _ |- _ ] => rewrite H; clear H
| [ |- appcontext[match ?pf with end] ] => solve [ case pf ]
| _ => progress autounfold in *
| _ => progress autorewrite with core
| _ => progress simpl in *
| _ => progress intuition auto with zarith datatypes
end; eauto.
Ltac boring_list :=
repeat match goal with
| _ => progress boring
| _ => progress autorewrite with distr_length simpl_nth_default simpl_update_nth simpl_set_nth simpl_nth_error in *
end.
Lemma nth_default_cons : forall {T} (x u0 : T) us, nth_default x (u0 :: us) 0 = u0.
Proof. auto. Qed.
Hint Rewrite @nth_default_cons : simpl_nth_default.
Hint Rewrite @nth_default_cons : push_nth_default.
Lemma nth_default_cons_S : forall {A} us (u0 : A) n d,
nth_default d (u0 :: us) (S n) = nth_default d us n.
Proof. boring. Qed.
Hint Rewrite @nth_default_cons_S : simpl_nth_default.
Hint Rewrite @nth_default_cons_S : push_nth_default.
Lemma nth_default_nil : forall {T} n (d : T), nth_default d nil n = d.
Proof. induction n; boring. Qed.
Hint Rewrite @nth_default_nil : simpl_nth_default.
Hint Rewrite @nth_default_nil : push_nth_default.
Lemma nth_error_nil_error : forall {A} n, nth_error (@nil A) n = None.
Proof. induction n; boring. Qed.
Hint Rewrite @nth_error_nil_error : simpl_nth_error.
Ltac nth_tac' :=
intros; simpl in *; unfold error,value in *; repeat progress (match goal with
| [ |- context[nth_error nil ?n] ] => rewrite nth_error_nil_error
| [ H: ?x = Some _ |- context[match ?x with Some _ => ?a | None => ?a end ] ] => destruct x
| [ H: ?x = None _ |- context[match ?x with Some _ => ?a | None => ?a end ] ] => destruct x
| [ |- context[match ?x with Some _ => ?a | None => ?a end ] ] => destruct x
| [ |- context[match nth_error ?xs ?i with Some _ => _ | None => _ end ] ] => case_eq (nth_error xs i); intros
| [ |- context[(if lt_dec ?a ?b then _ else _) = _] ] => destruct (lt_dec a b)
| [ |- context[_ = (if lt_dec ?a ?b then _ else _)] ] => destruct (lt_dec a b)
| [ H: context[(if lt_dec ?a ?b then _ else _) = _] |- _ ] => destruct (lt_dec a b)
| [ H: context[_ = (if lt_dec ?a ?b then _ else _)] |- _ ] => destruct (lt_dec a b)
| [ H: _ /\ _ |- _ ] => destruct H
| [ H: Some _ = Some _ |- _ ] => injection H; clear H; intros; subst
| [ H: None = Some _ |- _ ] => inversion H
| [ H: Some _ = None |- _ ] => inversion H
| [ |- Some _ = Some _ ] => apply f_equal
end); eauto; try (autorewrite with list in *); try omega; eauto.
Lemma nth_error_map : forall A B (f:A->B) i xs y,
nth_error (map f xs) i = Some y ->
exists x, nth_error xs i = Some x /\ f x = y.
Proof.
induction i; destruct xs; nth_tac'.
Qed.
Lemma nth_error_seq : forall i start len,
nth_error (seq start len) i =
if lt_dec i len
then Some (start + i)
else None.
induction i; destruct len; nth_tac'; erewrite IHi; nth_tac'.
Qed.
Lemma nth_error_error_length : forall A i (xs:list A), nth_error xs i = None ->
i >= length xs.
Proof.
induction i; destruct xs; nth_tac'; try specialize (IHi _ H); omega.
Qed.
Lemma nth_error_value_length : forall A i (xs:list A) x, nth_error xs i = Some x ->
i < length xs.
Proof.
induction i; destruct xs; nth_tac'; try specialize (IHi _ _ H); omega.
Qed.
Lemma nth_error_length_error : forall A i (xs:list A),
i >= length xs ->
nth_error xs i = None.
Proof.
induction i; destruct xs; nth_tac'; rewrite IHi by omega; auto.
Qed.
Hint Resolve nth_error_length_error.
Hint Rewrite @nth_error_length_error using omega : simpl_nth_error.
Lemma map_nth_default : forall (A B : Type) (f : A -> B) n x y l,
(n < length l) -> nth_default y (map f l) n = f (nth_default x l n).
Proof.
intros.
unfold nth_default.
erewrite map_nth_error.
reflexivity.
nth_tac'.
pose proof (nth_error_error_length A n l H0).
omega.
Qed.
Lemma map_nil : forall A B (f : A -> B), map f nil = nil.
Proof. reflexivity. Qed.
(* Note: this is a duplicate of a lemma that exists in 8.5, included for
8.4 support *)
Lemma In_nth : forall {A} (x : A) d xs, In x xs ->
exists i, i < length xs /\ nth i xs d = x.
Proof.
induction xs; intros;
match goal with H : In _ _ |- _ => simpl in H; destruct H end.
+ subst. exists 0. simpl; split; auto || omega.
+ destruct IHxs as [i [ ]]; auto.
exists (S i).
split; auto; simpl; try omega.
Qed.
Hint Rewrite @map_nth_default using omega : push_nth_default.
Ltac nth_tac :=
repeat progress (try nth_tac'; try (match goal with
| [ H: nth_error (map _ _) _ = Some _ |- _ ] => destruct (nth_error_map _ _ _ _ _ _ H); clear H
| [ H: nth_error (seq _ _) _ = Some _ |- _ ] => rewrite nth_error_seq in H
| [H: nth_error _ _ = None |- _ ] => specialize (nth_error_error_length _ _ _ H); intro; clear H
end)).
Lemma app_cons_app_app : forall T xs (y:T) ys, xs ++ y :: ys = (xs ++ (y::nil)) ++ ys.
Proof. induction xs; boring. Qed.
Lemma unfold_set_nth {T} n x
: forall xs,
@set_nth T n x xs
= match n with
| O => match xs with
| nil => nil
| x'::xs' => x::xs'
end
| S n' => match xs with
| nil => nil
| x'::xs' => x'::set_nth n' x xs'
end
end.
Proof.
induction n; destruct xs; reflexivity.
Qed.
Lemma simpl_set_nth_0 {T} x
: forall xs,
@set_nth T 0 x xs
= match xs with
| nil => nil
| x'::xs' => x::xs'
end.
Proof. intro; rewrite unfold_set_nth; reflexivity. Qed.
Lemma simpl_set_nth_S {T} x n
: forall xs,
@set_nth T (S n) x xs
= match xs with
| nil => nil
| x'::xs' => x'::set_nth n x xs'
end.
Proof. intro; rewrite unfold_set_nth; reflexivity. Qed.
Hint Rewrite @simpl_set_nth_S @simpl_set_nth_0 : simpl_set_nth.
Lemma update_nth_ext {T} f g n
: forall xs, (forall x, nth_error xs n = Some x -> f x = g x)
-> @update_nth T n f xs = @update_nth T n g xs.
Proof.
induction n; destruct xs; simpl; intros H;
try rewrite IHn; try rewrite H;
try congruence; trivial.
Qed.
Global Instance update_nth_Proper {T}
: Proper (eq ==> pointwise_relation _ eq ==> eq ==> eq) (@update_nth T).
Proof. repeat intro; subst; apply update_nth_ext; trivial. Qed.
Lemma update_nth_id_eq_specific {T} f n
: forall (xs : list T) (H : forall x, nth_error xs n = Some x -> f x = x),
update_nth n f xs = xs.
Proof.
induction n; destruct xs; simpl; intros;
try rewrite IHn; try rewrite H; unfold value in *;
try congruence; assumption.
Qed.
Hint Rewrite @update_nth_id_eq_specific using congruence : simpl_update_nth.
Lemma update_nth_id_eq : forall {T} f (H : forall x, f x = x) n (xs : list T),
update_nth n f xs = xs.
Proof. intros; apply update_nth_id_eq_specific; trivial. Qed.
Hint Rewrite @update_nth_id_eq using congruence : simpl_update_nth.
Lemma update_nth_id : forall {T} n (xs : list T),
update_nth n (fun x => x) xs = xs.
Proof. intros; apply update_nth_id_eq; trivial. Qed.
Hint Rewrite @update_nth_id : simpl_update_nth.
Lemma nth_update_nth : forall m {T} (xs:list T) (n:nat) (f:T -> T),
nth_error (update_nth m f xs) n =
if eq_nat_dec n m
then option_map f (nth_error xs n)
else nth_error xs n.
Proof.
induction m.
{ destruct n, xs; auto. }
{ destruct xs, n; intros; simpl; auto;
[ | rewrite IHm ]; clear IHm;
edestruct eq_nat_dec; reflexivity. }
Qed.
Hint Rewrite @nth_update_nth : push_nth_error.
Hint Rewrite <- @nth_update_nth : pull_nth_error.
Lemma length_update_nth : forall {T} i f (xs:list T), length (update_nth i f xs) = length xs.
Proof.
induction i, xs; boring.
Qed.
Hint Rewrite @length_update_nth : distr_length.
(** TODO: this is in the stdlib in 8.5; remove this when we move to 8.5-only *)
Lemma nth_error_None : forall (A : Type) (l : list A) (n : nat), nth_error l n = None <-> length l <= n.
Proof.
intros A l n.
destruct (le_lt_dec (length l) n) as [H|H];
split; intro H';
try omega;
try (apply nth_error_length_error in H; tauto);
try (apply nth_error_error_length in H'; omega).
Qed.
(** TODO: this is in the stdlib in 8.5; remove this when we move to 8.5-only *)
Lemma nth_error_Some : forall (A : Type) (l : list A) (n : nat), nth_error l n <> None <-> n < length l.
Proof. intros; rewrite nth_error_None; split; omega. Qed.
Lemma nth_set_nth : forall m {T} (xs:list T) (n:nat) x,
nth_error (set_nth m x xs) n =
if eq_nat_dec n m
then (if lt_dec n (length xs) then Some x else None)
else nth_error xs n.
Proof.
intros; unfold set_nth; rewrite nth_update_nth.
destruct (nth_error xs n) eqn:?, (lt_dec n (length xs)) as [p|p];
rewrite <- nth_error_Some in p;
solve [ reflexivity
| exfalso; apply p; congruence ].
Qed.
Hint Rewrite @nth_set_nth : push_nth_error.
Lemma length_set_nth : forall {T} i x (xs:list T), length (set_nth i x xs) = length xs.
Proof. intros; apply length_update_nth. Qed.
Hint Rewrite @length_set_nth : distr_length.
Lemma nth_error_length_exists_value : forall {A} (i : nat) (xs : list A),
(i < length xs)%nat -> exists x, nth_error xs i = Some x.
Proof.
induction i, xs; boring; try omega.
Qed.
Lemma nth_error_length_not_error : forall {A} (i : nat) (xs : list A),
nth_error xs i = None -> (i < length xs)%nat -> False.
Proof.
intros.
destruct (nth_error_length_exists_value i xs); intuition; congruence.
Qed.
Lemma nth_error_value_eq_nth_default : forall {T} i (x : T) xs,
nth_error xs i = Some x -> forall d, nth_default d xs i = x.
Proof.
unfold nth_default; boring.
Qed.
Hint Rewrite @nth_error_value_eq_nth_default using eassumption : simpl_nth_default.
Lemma skipn0 : forall {T} (xs:list T), skipn 0 xs = xs.
Proof. auto. Qed.
Lemma destruct_repeat : forall {A} xs y, (forall x : A, In x xs -> x = y) ->
xs = nil \/ exists xs', xs = y :: xs' /\ (forall x : A, In x xs' -> x = y).
Proof.
destruct xs; intros; try tauto.
right.
exists xs; split.
+ f_equal; auto using in_eq.
+ intros; auto using in_cons.
Qed.
Lemma splice_nth_equiv_update_nth : forall {T} n f d (xs:list T),
splice_nth n (f (nth_default d xs n)) xs =
if lt_dec n (length xs)
then update_nth n f xs
else xs ++ (f d)::nil.
Proof.
induction n, xs; boring_list.
do 2 break_if; auto; omega.
Qed.
Lemma splice_nth_equiv_update_nth_update : forall {T} n f d (xs:list T),
n < length xs ->
splice_nth n (f (nth_default d xs n)) xs = update_nth n f xs.
Proof.
intros.
rewrite splice_nth_equiv_update_nth.
break_if; auto; omega.
Qed.
Lemma splice_nth_equiv_update_nth_snoc : forall {T} n f d (xs:list T),
n >= length xs ->
splice_nth n (f (nth_default d xs n)) xs = xs ++ (f d)::nil.
Proof.
intros.
rewrite splice_nth_equiv_update_nth.
break_if; auto; omega.
Qed.
Definition IMPOSSIBLE {T} : list T. exact nil. Qed.
Ltac remove_nth_error :=
repeat match goal with
| _ => exfalso; solve [ eauto using @nth_error_length_not_error ]
| [ |- context[match nth_error ?ls ?n with _ => _ end] ]
=> destruct (nth_error ls n) eqn:?
end.
Lemma update_nth_equiv_splice_nth: forall {T} n f (xs:list T),
update_nth n f xs =
if lt_dec n (length xs)
then match nth_error xs n with
| Some v => splice_nth n (f v) xs
| None => IMPOSSIBLE
end
else xs.
Proof.
induction n; destruct xs; intros;
autorewrite with simpl_update_nth simpl_nth_default in *; simpl in *;
try (erewrite IHn; clear IHn); auto.
repeat break_match; remove_nth_error; try reflexivity; try omega.
Qed.
Lemma splice_nth_equiv_set_nth : forall {T} n x (xs:list T),
splice_nth n x xs =
if lt_dec n (length xs)
then set_nth n x xs
else xs ++ x::nil.
Proof. intros; rewrite splice_nth_equiv_update_nth with (f := fun _ => x); auto. Qed.
Lemma splice_nth_equiv_set_nth_set : forall {T} n x (xs:list T),
n < length xs ->
splice_nth n x xs = set_nth n x xs.
Proof. intros; rewrite splice_nth_equiv_update_nth_update with (f := fun _ => x); auto. Qed.
Lemma splice_nth_equiv_set_nth_snoc : forall {T} n x (xs:list T),
n >= length xs ->
splice_nth n x xs = xs ++ x::nil.
Proof. intros; rewrite splice_nth_equiv_update_nth_snoc with (f := fun _ => x); auto. Qed.
Lemma set_nth_equiv_splice_nth: forall {T} n x (xs:list T),
set_nth n x xs =
if lt_dec n (length xs)
then splice_nth n x xs
else xs.
Proof.
intros; unfold set_nth; rewrite update_nth_equiv_splice_nth with (f := fun _ => x); auto.
repeat break_match; remove_nth_error; trivial.
Qed.
Lemma combine_update_nth : forall {A B} n f g (xs:list A) (ys:list B),
combine (update_nth n f xs) (update_nth n g ys) =
update_nth n (fun xy => (f (fst xy), g (snd xy))) (combine xs ys).
Proof.
induction n; destruct xs, ys; simpl; try rewrite IHn; reflexivity.
Qed.
(* grumble, grumble, [rewrite] is bad at inferring the identity function, and constant functions *)
Ltac rewrite_rev_combine_update_nth :=
let lem := match goal with
| [ |- appcontext[update_nth ?n (fun xy => (@?f xy, @?g xy)) (combine ?xs ?ys)] ]
=> let f := match (eval cbv [fst] in (fun y x => f (x, y))) with
| fun _ => ?f => f
end in
let g := match (eval cbv [snd] in (fun x y => g (x, y))) with
| fun _ => ?g => g
end in
constr:(@combine_update_nth _ _ n f g xs ys)
end in
rewrite <- lem.
Lemma combine_update_nth_l : forall {A B} n (f : A -> A) xs (ys:list B),
combine (update_nth n f xs) ys =
update_nth n (fun xy => (f (fst xy), snd xy)) (combine xs ys).
Proof.
intros ??? f xs ys.
etransitivity; [ | apply combine_update_nth with (g := fun x => x) ].
rewrite update_nth_id; reflexivity.
Qed.
Lemma combine_update_nth_r : forall {A B} n (g : B -> B) (xs:list A) (ys:list B),
combine xs (update_nth n g ys) =
update_nth n (fun xy => (fst xy, g (snd xy))) (combine xs ys).
Proof.
intros ??? g xs ys.
etransitivity; [ | apply combine_update_nth with (f := fun x => x) ].
rewrite update_nth_id; reflexivity.
Qed.
Lemma combine_set_nth : forall {A B} n (x:A) xs (ys:list B),
combine (set_nth n x xs) ys =
match nth_error ys n with
| None => combine xs ys
| Some y => set_nth n (x,y) (combine xs ys)
end.
Proof.
intros; unfold set_nth; rewrite combine_update_nth_l.
nth_tac;
[ repeat rewrite_rev_combine_update_nth; apply f_equal2
| assert (nth_error (combine xs ys) n = None)
by (apply nth_error_None; rewrite combine_length; omega * ) ];
autorewrite with simpl_update_nth; reflexivity.
Qed.
Lemma nth_error_value_In : forall {T} n xs (x:T),
nth_error xs n = Some x -> In x xs.
Proof.
induction n; destruct xs; nth_tac.
Qed.
Lemma In_nth_error_value : forall {T} xs (x:T),
In x xs -> exists n, nth_error xs n = Some x.
Proof.
induction xs; nth_tac; break_or_hyp.
- exists 0; reflexivity.
- edestruct IHxs; eauto. exists (S x0). eauto.
Qed.
Lemma nth_value_index : forall {T} i xs (x:T),
nth_error xs i = Some x -> In i (seq 0 (length xs)).
Proof.
induction i; destruct xs; nth_tac; right.
rewrite <- seq_shift; apply in_map; eapply IHi; eauto.
Qed.
Lemma nth_error_app : forall {T} n (xs ys:list T), nth_error (xs ++ ys) n =
if lt_dec n (length xs)
then nth_error xs n
else nth_error ys (n - length xs).
Proof.
induction n; destruct xs; nth_tac;
rewrite IHn; destruct (lt_dec n (length xs)); trivial; omega.
Qed.
Lemma nth_default_app : forall {T} n x (xs ys:list T), nth_default x (xs ++ ys) n =
if lt_dec n (length xs)
then nth_default x xs n
else nth_default x ys (n - length xs).
Proof.
intros.
unfold nth_default.
rewrite nth_error_app.
destruct (lt_dec n (length xs)); auto.
Qed.
Hint Rewrite @nth_default_app : push_nth_default.
Lemma combine_truncate_r : forall {A B} (xs : list A) (ys : list B),
combine xs ys = combine xs (firstn (length xs) ys).
Proof.
induction xs; destruct ys; boring.
Qed.
Lemma combine_truncate_l : forall {A B} (xs : list A) (ys : list B),
combine xs ys = combine (firstn (length ys) xs) ys.
Proof.
induction xs; destruct ys; boring.
Qed.
Lemma combine_app_samelength : forall {A B} (xs xs':list A) (ys ys':list B),
length xs = length ys ->
combine (xs ++ xs') (ys ++ ys') = combine xs ys ++ combine xs' ys'.
Proof.
induction xs, xs', ys, ys'; boring; omega.
Qed.
Lemma skipn_nil : forall {A} n, skipn n nil = @nil A.
Proof. destruct n; auto. Qed.
Hint Rewrite @skipn_nil : simpl_skipn.
Hint Rewrite @skipn_nil : push_skipn.
Lemma skipn_0 : forall {A} xs, @skipn A 0 xs = xs.
Proof. reflexivity. Qed.
Hint Rewrite @skipn_0 : simpl_skipn.
Hint Rewrite @skipn_0 : push_skipn.
Lemma skipn_cons_S : forall {A} n x xs, @skipn A (S n) (x::xs) = @skipn A n xs.
Proof. reflexivity. Qed.
Hint Rewrite @skipn_cons_S : simpl_skipn.
Hint Rewrite @skipn_cons_S : push_skipn.
Lemma skipn_app : forall {A} n (xs ys : list A),
skipn n (xs ++ ys) = skipn n xs ++ skipn (n - length xs) ys.
Proof.
induction n, xs, ys; boring.
Qed.
Hint Rewrite @skipn_app : push_skipn.
Lemma firstn_app_inleft : forall {A} n (xs ys : list A), (n <= length xs)%nat ->
firstn n (xs ++ ys) = firstn n xs.
Proof.
induction n, xs, ys; boring; try omega.
Qed.
Hint Rewrite @firstn_app_inleft using solve [ distr_length ] : simpl_firstn.
Hint Rewrite @firstn_app_inleft using solve [ distr_length ] : push_firstn.
Lemma skipn_app_inleft : forall {A} n (xs ys : list A), (n <= length xs)%nat ->
skipn n (xs ++ ys) = skipn n xs ++ ys.
Proof.
induction n, xs, ys; boring; try omega.
Qed.
Hint Rewrite @skipn_app_inleft using solve [ distr_length ] : push_skipn.
Lemma firstn_map : forall {A B} (f : A -> B) n (xs : list A), firstn n (map f xs) = map f (firstn n xs).
Proof. induction n, xs; boring. Qed.
Hint Rewrite @firstn_map : push_firstn.
Hint Rewrite <- @firstn_map : pull_firstn.
Lemma skipn_map : forall {A B} (f : A -> B) n (xs : list A), skipn n (map f xs) = map f (skipn n xs).
Proof. induction n, xs; boring. Qed.
Hint Rewrite @skipn_map : push_skipn.
Hint Rewrite <- @skipn_map : pull_skipn.
Lemma firstn_all : forall {A} n (xs:list A), n = length xs -> firstn n xs = xs.
Proof.
induction n, xs; boring; omega.
Qed.
Hint Rewrite @firstn_all using solve [ distr_length ] : simpl_firstn.
Hint Rewrite @firstn_all using solve [ distr_length ] : push_firstn.
Lemma skipn_all : forall {T} n (xs:list T),
(n >= length xs)%nat ->
skipn n xs = nil.
Proof.
induction n, xs; boring; omega.
Qed.
Hint Rewrite @skipn_all using solve [ distr_length ] : simpl_skipn.
Hint Rewrite @skipn_all using solve [ distr_length ] : push_skipn.
Lemma firstn_app_sharp : forall {A} n (l l': list A),
length l = n ->
firstn n (l ++ l') = l.
Proof.
intros.
rewrite firstn_app_inleft; auto using firstn_all; omega.
Qed.
Hint Rewrite @firstn_app_sharp using solve [ distr_length ] : simpl_firstn.
Hint Rewrite @firstn_app_sharp using solve [ distr_length ] : push_firstn.
Lemma skipn_app_sharp : forall {A} n (l l': list A),
length l = n ->
skipn n (l ++ l') = l'.
Proof.
intros.
rewrite skipn_app_inleft; try rewrite skipn_all; auto; omega.
Qed.
Hint Rewrite @skipn_app_sharp using solve [ distr_length ] : simpl_skipn.
Hint Rewrite @skipn_app_sharp using solve [ distr_length ] : push_skipn.
Lemma skipn_length : forall {A} n (xs : list A),
length (skipn n xs) = (length xs - n)%nat.
Proof.
induction n, xs; boring.
Qed.
Hint Rewrite @skipn_length : distr_length.
Lemma fold_right_cons : forall {A B} (f:B->A->A) a b bs,
fold_right f a (b::bs) = f b (fold_right f a bs).
Proof.
reflexivity.
Qed.
Hint Rewrite @fold_right_cons : simpl_fold_right.
Lemma length_cons : forall {T} (x:T) xs, length (x::xs) = S (length xs).
reflexivity.
Qed.
Hint Rewrite @length_cons : distr_length.
Lemma cons_length : forall A (xs : list A) a, length (a :: xs) = S (length xs).
Proof.
auto.
Qed.
Lemma length0_nil : forall {A} (xs : list A), length xs = 0%nat -> xs = nil.
Proof.
induction xs; boring; discriminate.
Qed.
Lemma length_snoc : forall {T} xs (x:T),
length xs = pred (length (xs++x::nil)).
Proof.
boring; simpl_list; boring.
Qed.
Lemma firstn_combine : forall {A B} n (xs:list A) (ys:list B),
firstn n (combine xs ys) = combine (firstn n xs) (firstn n ys).
Proof.
induction n, xs, ys; boring.
Qed.
Hint Rewrite @firstn_combine : push_firstn.
Hint Rewrite <- @firstn_combine : pull_firstn.
Lemma combine_nil_r : forall {A B} (xs:list A),
combine xs (@nil B) = nil.
Proof.
induction xs; boring.
Qed.
Lemma skipn_combine : forall {A B} n (xs:list A) (ys:list B),
skipn n (combine xs ys) = combine (skipn n xs) (skipn n ys).
Proof.
induction n, xs, ys; boring.
rewrite combine_nil_r; reflexivity.
Qed.
Hint Rewrite @skipn_combine : push_skipn.
Hint Rewrite <- @skipn_combine : pull_skipn.
Lemma break_list_last: forall {T} (xs:list T),
xs = nil \/ exists xs' y, xs = xs' ++ y :: nil.
Proof.
destruct xs using rev_ind; auto.
right; do 2 eexists; auto.
Qed.
Lemma break_list_first: forall {T} (xs:list T),
xs = nil \/ exists x xs', xs = x :: xs'.
Proof.
destruct xs; auto.
right; do 2 eexists; auto.
Qed.
Lemma list012 : forall {T} (xs:list T),
xs = nil
\/ (exists x, xs = x::nil)
\/ (exists x xs' y, xs = x::xs'++y::nil).
Proof.
destruct xs; auto.
right.
destruct xs using rev_ind. {
left; eexists; auto.
} {
right; repeat eexists; auto.
}
Qed.
Lemma nil_length0 : forall {T}, length (@nil T) = 0%nat.
Proof.
auto.
Qed.
Hint Rewrite @nil_length0 : distr_length.
Lemma nth_error_Some_nth_default : forall {T} i x (l : list T), (i < length l)%nat ->
nth_error l i = Some (nth_default x l i).
Proof.
intros ? ? ? ? i_lt_length.
destruct (nth_error_length_exists_value _ _ i_lt_length) as [k nth_err_k].
unfold nth_default.
rewrite nth_err_k.
reflexivity.
Qed.
Lemma update_nth_cons : forall {T} f (u0 : T) us, update_nth 0 f (u0 :: us) = (f u0) :: us.
Proof. reflexivity. Qed.
Hint Rewrite @update_nth_cons : simpl_update_nth.
Lemma set_nth_cons : forall {T} (x u0 : T) us, set_nth 0 x (u0 :: us) = x :: us.
Proof. intros; apply update_nth_cons. Qed.
Hint Rewrite @set_nth_cons : simpl_set_nth.
Lemma cons_update_nth : forall {T} n f (y : T) us,
y :: update_nth n f us = update_nth (S n) f (y :: us).
Proof.
induction n; boring.
Qed.
Hint Rewrite <- @cons_update_nth : simpl_update_nth.
Lemma update_nth_nil : forall {T} n f, update_nth n f (@nil T) = @nil T.
Proof.
induction n; boring.
Qed.
Hint Rewrite @update_nth_nil : simpl_update_nth.
Lemma cons_set_nth : forall {T} n (x y : T) us,
y :: set_nth n x us = set_nth (S n) x (y :: us).
Proof. intros; apply cons_update_nth. Qed.
Hint Rewrite <- @cons_set_nth : simpl_set_nth.
Lemma set_nth_nil : forall {T} n (x : T), set_nth n x nil = nil.
Proof. intros; apply update_nth_nil. Qed.
Hint Rewrite @set_nth_nil : simpl_set_nth.
Lemma skipn_nth_default : forall {T} n us (d : T), (n < length us)%nat ->
skipn n us = nth_default d us n :: skipn (S n) us.
Proof.
induction n; destruct us; intros; nth_tac.
rewrite (IHn us d) at 1 by omega.
nth_tac.
Qed.
Lemma nth_default_out_of_bounds : forall {T} n us (d : T), (n >= length us)%nat ->
nth_default d us n = d.
Proof.
induction n; unfold nth_default; nth_tac; destruct us; nth_tac.
assert (n >= length us)%nat by omega.
pose proof (nth_error_length_error _ n us H1).
rewrite H0 in H2.
congruence.
Qed.
Hint Rewrite @nth_default_out_of_bounds using omega : simpl_nth_default.
Ltac nth_error_inbounds :=
match goal with
| [ |- context[match nth_error ?xs ?i with Some _ => _ | None => _ end ] ] =>
case_eq (nth_error xs i);
match goal with
| [ |- forall _, nth_error xs i = Some _ -> _ ] =>
let x := fresh "x" in
let H := fresh "H" in
intros x H;
repeat progress erewrite H;
repeat progress erewrite (nth_error_value_eq_nth_default i xs x); auto
| [ |- nth_error xs i = None -> _ ] =>
let H := fresh "H" in
intros H;
destruct (nth_error_length_not_error _ _ H);
try solve [distr_length]
end;
idtac
end.
Ltac set_nth_inbounds :=
match goal with
| [ |- context[set_nth ?i ?x ?xs] ] =>
rewrite (set_nth_equiv_splice_nth i x xs);
destruct (lt_dec i (length xs));
match goal with
| [ H : ~ (i < (length xs))%nat |- _ ] => destruct H
| [ H : (i < (length xs))%nat |- _ ] => try solve [distr_length]
end
end.
Ltac update_nth_inbounds :=
match goal with
| [ |- context[update_nth ?i ?f ?xs] ] =>
rewrite (update_nth_equiv_splice_nth i f xs);
destruct (lt_dec i (length xs));
match goal with
| [ H : ~ (i < (length xs))%nat |- _ ] => destruct H
| [ H : (i < (length xs))%nat |- _ ] => remove_nth_error; try solve [distr_length]
end
end.
Ltac nth_inbounds := nth_error_inbounds || set_nth_inbounds || update_nth_inbounds.
Definition nth_dep {A} (ls : list A) (n : nat) (pf : n < length ls) : A.
Proof.
refine (match nth_error ls n as v return nth_error ls n = v -> A with
| Some v => fun _ => v
| None => fun bad => match _ : False with end
end eq_refl).
apply (proj1 (@nth_error_None _ _ _)) in bad; instantiate; generalize dependent (length ls); clear.
abstract (intros; omega).
Defined.
Lemma nth_error_nth_dep {A} ls n pf : nth_error ls n = Some (@nth_dep A ls n pf).
Proof.
unfold nth_dep.
generalize dependent (@nth_error_None A ls n).
edestruct nth_error; boring.
Qed.
Lemma nth_default_nth_dep {A} d ls n pf : nth_default d ls n = @nth_dep A ls n pf.
Proof.
unfold nth_dep.
generalize dependent (@nth_error_None A ls n).
destruct (nth_error ls n) eqn:?; boring.
erewrite nth_error_value_eq_nth_default by eassumption; reflexivity.
Qed.
Lemma nth_default_in_bounds : forall {T} (d' d : T) n us, (n < length us)%nat ->
nth_default d us n = nth_default d' us n.
Proof.
intros; erewrite !nth_default_nth_dep; reflexivity.
Grab Existential Variables.
assumption.
Qed.
Hint Resolve @nth_default_in_bounds : simpl_nth_default.
Lemma cons_eq_head : forall {T} (x y:T) xs ys, x::xs = y::ys -> x=y.
Proof.
intros; solve_by_inversion.
Qed.
Lemma cons_eq_tail : forall {T} (x y:T) xs ys, x::xs = y::ys -> xs=ys.
Proof.
intros; solve_by_inversion.
Qed.
Lemma map_nth_default_always {A B} (f : A -> B) (n : nat) (x : A) (l : list A)
: nth_default (f x) (map f l) n = f (nth_default x l n).
Proof.
revert n; induction l; simpl; intro n; destruct n; [ try reflexivity.. ].
nth_tac.
Qed.
Hint Rewrite @map_nth_default_always : push_nth_default.
Lemma fold_right_and_True_forall_In_iff : forall {T} (l : list T) (P : T -> Prop),
(forall x, In x l -> P x) <-> fold_right and True (map P l).
Proof.
induction l; intros; simpl; try tauto.
rewrite <- IHl.
intuition (subst; auto).
Qed.
Lemma fold_right_invariant : forall {A} P (f: A -> A -> A) l x,
P x -> (forall y, In y l -> forall z, P z -> P (f y z)) ->
P (fold_right f x l).
Proof.
induction l; intros ? ? step; auto.
simpl.
apply step; try apply in_eq.
apply IHl; auto.
intros y in_y_l.
apply (in_cons a) in in_y_l.
auto.
Qed.
Lemma In_firstn : forall {T} n l (x : T), In x (firstn n l) -> In x l.
Proof.
induction n; destruct l; boring.
Qed.
Lemma In_skipn : forall {T} n l (x : T), In x (skipn n l) -> In x l.
Proof.
induction n; destruct l; boring.
Qed.
Lemma firstn_firstn : forall {A} m n (l : list A), (n <= m)%nat ->
firstn n (firstn m l) = firstn n l.
Proof.
induction m; destruct n; intros; try omega; auto.
destruct l; auto.
simpl.
f_equal.
apply IHm; omega.
Qed.
Hint Rewrite @firstn_firstn using omega : push_firstn.
Lemma firstn_succ : forall {A} (d : A) n l, (n < length l)%nat ->
firstn (S n) l = (firstn n l) ++ nth_default d l n :: nil.
Proof.
induction n; destruct l; rewrite ?(@nil_length0 A); intros; try omega.
+ rewrite nth_default_cons; auto.
+ simpl.
rewrite nth_default_cons_S.
rewrite <-IHn by (rewrite cons_length in *; omega).
reflexivity.
Qed.
Lemma update_nth_out_of_bounds : forall {A} n f xs, n >= length xs -> @update_nth A n f xs = xs.
Proof.
induction n; destruct xs; simpl; try congruence; try omega; intros.
rewrite IHn by omega; reflexivity.
Qed.
Hint Rewrite @update_nth_out_of_bounds using omega : simpl_update_nth.
Lemma update_nth_nth_default_full : forall {A} (d:A) n f l i,
nth_default d (update_nth n f l) i =
if lt_dec i (length l) then
if (eq_nat_dec i n) then f (nth_default d l i)
else nth_default d l i
else d.
Proof.
induction n; (destruct l; simpl in *; [ intros; destruct i; simpl; try reflexivity; omega | ]);
intros; repeat break_if; subst; try destruct i;
repeat first [ progress break_if
| progress subst
| progress boring
| progress autorewrite with simpl_nth_default
| omega ].
Qed.
Hint Rewrite @update_nth_nth_default_full : push_nth_default.
Lemma update_nth_nth_default : forall {A} (d:A) n f l i, (0 <= i < length l)%nat ->
nth_default d (update_nth n f l) i =
if (eq_nat_dec i n) then f (nth_default d l i) else nth_default d l i.
Proof. intros; rewrite update_nth_nth_default_full; repeat break_if; boring. Qed.
Hint Rewrite @update_nth_nth_default using (omega || distr_length; omega) : push_nth_default.
Lemma set_nth_nth_default_full : forall {A} (d:A) n v l i,
nth_default d (set_nth n v l) i =
if lt_dec i (length l) then
if (eq_nat_dec i n) then v
else nth_default d l i
else d.
Proof. intros; apply update_nth_nth_default_full; assumption. Qed.
Hint Rewrite @set_nth_nth_default_full : push_nth_default.
Lemma set_nth_nth_default : forall {A} (d:A) n x l i, (0 <= i < length l)%nat ->
nth_default d (set_nth n x l) i =
if (eq_nat_dec i n) then x else nth_default d l i.
Proof. intros; apply update_nth_nth_default; assumption. Qed.
Hint Rewrite @set_nth_nth_default using (omega || distr_length; omega) : push_nth_default.
Lemma nth_default_preserves_properties : forall {A} (P : A -> Prop) l n d,
(forall x, In x l -> P x) -> P d -> P (nth_default d l n).
Proof.
intros; rewrite nth_default_eq.
destruct (nth_in_or_default n l d); auto.
congruence.
Qed.
Lemma nth_default_preserves_properties_length_dep :
forall {A} (P : A -> Prop) l n d,
(forall x, In x l -> n < (length l) -> P x) -> ((~ n < length l) -> P d) -> P (nth_default d l n).
Proof.
intros.
destruct (lt_dec n (length l)).
+ rewrite nth_default_eq; auto using nth_In.
+ rewrite nth_default_out_of_bounds by omega.
auto.
Qed.
Lemma nth_error_first : forall {T} (a b : T) l,
nth_error (a :: l) 0 = Some b -> a = b.
Proof.
intros; simpl in *.
unfold value in *.
congruence.
Qed.
Lemma nth_error_exists_first : forall {T} l (x : T) (H : nth_error l 0 = Some x),
exists l', l = x :: l'.
Proof.
induction l; try discriminate; eexists.
apply nth_error_first in H.
subst; eauto.
Qed.
Lemma list_elementwise_eq : forall {T} (l1 l2 : list T),
(forall i, nth_error l1 i = nth_error l2 i) -> l1 = l2.
Proof.
induction l1, l2; intros; try reflexivity;
pose proof (H 0%nat) as Hfirst; simpl in Hfirst; inversion Hfirst.
f_equal.
apply IHl1.
intros i; specialize (H (S i)).
boring.
Qed.
Lemma sum_firstn_all_succ : forall n l, (length l <= n)%nat ->
sum_firstn l (S n) = sum_firstn l n.
Proof.
unfold sum_firstn; intros.
autorewrite with push_firstn; reflexivity.
Qed.
Hint Rewrite @sum_firstn_all_succ using omega : simpl_sum_firstn.
Lemma sum_firstn_all : forall n l, (length l <= n)%nat ->
sum_firstn l n = sum_firstn l (length l).
Proof.
unfold sum_firstn; intros.
autorewrite with push_firstn; reflexivity.
Qed.
Hint Rewrite @sum_firstn_all using omega : simpl_sum_firstn.
Lemma sum_firstn_succ_default : forall l i,
sum_firstn l (S i) = (nth_default 0 l i + sum_firstn l i)%Z.
Proof.
unfold sum_firstn; induction l, i;
intros; autorewrite with simpl_nth_default simpl_firstn simpl_fold_right in *;
try reflexivity.
rewrite IHl; omega.
Qed.
Hint Rewrite @sum_firstn_succ_default : simpl_sum_firstn.
Lemma sum_firstn_0 : forall xs,
sum_firstn xs 0 = 0%Z.
Proof.
destruct xs; reflexivity.
Qed.
Hint Rewrite @sum_firstn_0 : simpl_sum_firstn.
Lemma sum_firstn_succ : forall l i x,
nth_error l i = Some x ->
sum_firstn l (S i) = (x + sum_firstn l i)%Z.
Proof.
intros; rewrite sum_firstn_succ_default.
erewrite nth_error_value_eq_nth_default by eassumption; reflexivity.
Qed.
Hint Rewrite @sum_firstn_succ using congruence : simpl_sum_firstn.
Lemma sum_firstn_succ_cons : forall x xs i,
sum_firstn (x :: xs) (S i) = (x + sum_firstn xs i)%Z.
Proof.
unfold sum_firstn; simpl; reflexivity.
Qed.
Hint Rewrite @sum_firstn_succ_cons : simpl_sum_firstn.
Lemma sum_firstn_nil : forall i,
sum_firstn nil i = 0%Z.
Proof. destruct i; reflexivity. Qed.
Hint Rewrite @sum_firstn_nil : simpl_sum_firstn.
Lemma sum_firstn_succ_default_rev : forall l i,
sum_firstn l i = (sum_firstn l (S i) - nth_default 0 l i)%Z.
Proof.
intros; rewrite sum_firstn_succ_default; omega.
Qed.
Lemma sum_firstn_succ_rev : forall l i x,
nth_error l i = Some x ->
sum_firstn l i = (sum_firstn l (S i) - x)%Z.
Proof.
intros; erewrite sum_firstn_succ by eassumption; omega.
Qed.
Lemma sum_firstn_nonnegative : forall n l, (forall x, In x l -> 0 <= x)%Z
-> (0 <= sum_firstn l n)%Z.
Proof.
induction n as [|n IHn]; destruct l as [|? l]; autorewrite with simpl_sum_firstn; simpl; try omega.
{ specialize (IHn l).
destruct n; simpl; autorewrite with simpl_sum_firstn simpl_nth_default in *;
intuition auto with zarith. }
Qed.
Hint Resolve sum_firstn_nonnegative : znonzero.
Lemma sum_firstn_app : forall xs ys n,
sum_firstn (xs ++ ys) n = (sum_firstn xs n + sum_firstn ys (n - length xs))%Z.
Proof.
induction xs; simpl.
{ intros ys n; autorewrite with simpl_sum_firstn; simpl.
f_equal; omega. }
{ intros ys [|n]; autorewrite with simpl_sum_firstn; simpl; [ reflexivity | ].
rewrite IHxs; omega. }
Qed.
Lemma sum_firstn_app_sum : forall xs ys n,
sum_firstn (xs ++ ys) (length xs + n) = (sum_firstn xs (length xs) + sum_firstn ys n)%Z.
Proof.
intros; rewrite sum_firstn_app; autorewrite with simpl_sum_firstn.
do 2 f_equal; omega.
Qed.
Hint Rewrite @sum_firstn_app_sum : simpl_sum_firstn.
Lemma nth_error_skipn : forall {A} n (l : list A) m,
nth_error (skipn n l) m = nth_error l (n + m).
Proof.
induction n; destruct l; boring.
apply nth_error_nil_error.
Qed.
Hint Rewrite @nth_error_skipn : push_nth_error.
Lemma nth_default_skipn : forall {A} (l : list A) d n m, nth_default d (skipn n l) m = nth_default d l (n + m).
Proof.
cbv [nth_default]; intros.
rewrite nth_error_skipn.
reflexivity.
Qed.
Hint Rewrite @nth_default_skipn : push_nth_default.
Lemma sum_firstn_skipn : forall l n m, sum_firstn l (n + m) = (sum_firstn l n + sum_firstn (skipn n l) m)%Z.
Proof.
induction m; intros.
+ rewrite sum_firstn_0. autorewrite with natsimplify. omega.
+ rewrite <-plus_n_Sm, !sum_firstn_succ_default.
rewrite nth_default_skipn.
omega.
Qed.
Lemma sum_firstn_prefix_le' : forall l n m, (forall x, In x l -> (0 <= x)%Z) ->
(sum_firstn l n <= sum_firstn l (n + m))%Z.
Proof.
intros.
rewrite sum_firstn_skipn.
pose proof (sum_firstn_nonnegative m (skipn n l)) as Hskipn_nonneg.
match type of Hskipn_nonneg with
?P -> _ => assert P as Q; [ | specialize (Hskipn_nonneg Q); omega ] end.
intros x HIn_skipn.
apply In_skipn in HIn_skipn.
auto.
Qed.
Lemma sum_firstn_prefix_le : forall l n m, (forall x, In x l -> (0 <= x)%Z) ->
(n <= m)%nat ->
(sum_firstn l n <= sum_firstn l m)%Z.
Proof.
intros.
replace m with (n + (m - n))%nat by omega.
auto using sum_firstn_prefix_le'.
Qed.
Lemma sum_firstn_pos_lt_succ : forall l n m, (forall x, In x l -> (0 <= x)%Z) ->
(n < length l)%nat ->
(sum_firstn l n < sum_firstn l (S m))%Z ->
(n <= m)%nat.
Proof.
intros.
destruct (le_dec n m); auto.
replace n with (m + (n - m))%nat in H1 by omega.
rewrite sum_firstn_skipn in H1.
rewrite sum_firstn_succ_default in *.
match goal with H : (?a + ?b < ?c + ?a)%Z |- _ => assert (b < c)%Z by omega end.
destruct (lt_dec m (length l)). {
rewrite skipn_nth_default with (d := 0%Z) in H2 by assumption.
replace (n - m)%nat with (S (n - S m))%nat in H2 by omega.
rewrite sum_firstn_succ_cons in H2.
pose proof (sum_firstn_nonnegative (n - S m) (skipn (S m) l)).
match type of H3 with
?P -> _ => assert P as Q; [ | specialize (H3 Q); omega ] end.
intros ? A.
apply In_skipn in A.
apply H in A.
omega.
} {
rewrite skipn_all, nth_default_out_of_bounds in H2 by omega.
rewrite sum_firstn_nil in H2; omega.
}
Qed.
Definition NotSum {T} (xs : list T) (v : nat) := True.
Ltac NotSum :=
lazymatch goal with
| [ |- NotSum ?xs (length ?xs + _)%nat ] => fail
| [ |- NotSum _ _ ] => exact I
end.
Lemma sum_firstn_app_hint : forall xs ys n, NotSum xs n ->
sum_firstn (xs ++ ys) n = (sum_firstn xs n + sum_firstn ys (n - length xs))%Z.
Proof. auto using sum_firstn_app. Qed.
Hint Rewrite sum_firstn_app_hint using solve [ NotSum ] : simpl_sum_firstn.
Lemma nth_default_map2 : forall {A B C} (f : A -> B -> C) ls1 ls2 i d d1 d2,
nth_default d (map2 f ls1 ls2) i =
if lt_dec i (min (length ls1) (length ls2))
then f (nth_default d1 ls1 i) (nth_default d2 ls2 i)
else d.
Proof.
induction ls1, ls2.
+ cbv [map2 length min].
intros.
break_if; try omega.
apply nth_default_nil.
+ cbv [map2 length min].
intros.
break_if; try omega.
apply nth_default_nil.
+ cbv [map2 length min].
intros.
break_if; try omega.
apply nth_default_nil.
+ simpl.
destruct i.
- intros. rewrite !nth_default_cons.
break_if; auto; omega.
- intros. rewrite !nth_default_cons_S.
rewrite IHls1 with (d1 := d1) (d2 := d2).
repeat break_if; auto; omega.
Qed.
Lemma map2_cons : forall A B C (f : A -> B -> C) ls1 ls2 a b,
map2 f (a :: ls1) (b :: ls2) = f a b :: map2 f ls1 ls2.
Proof.
reflexivity.
Qed.
Lemma map2_nil_l : forall A B C (f : A -> B -> C) ls2,
map2 f nil ls2 = nil.
Proof.
reflexivity.
Qed.
Lemma map2_nil_r : forall A B C (f : A -> B -> C) ls1,
map2 f ls1 nil = nil.
Proof.
destruct ls1; reflexivity.
Qed.
Local Hint Resolve map2_nil_r map2_nil_l.
Opaque map2.
Lemma map2_length : forall A B C (f : A -> B -> C) ls1 ls2,
length (map2 f ls1 ls2) = min (length ls1) (length ls2).
Proof.
induction ls1, ls2; intros; try solve [cbv; auto].
rewrite map2_cons, !length_cons, IHls1.
auto.
Qed.
Ltac simpl_list_lengths := repeat match goal with
| H : appcontext[length (@nil ?A)] |- _ => rewrite (@nil_length0 A) in H
| H : appcontext[length (_ :: _)] |- _ => rewrite length_cons in H
| |- appcontext[length (@nil ?A)] => rewrite (@nil_length0 A)
| |- appcontext[length (_ :: _)] => rewrite length_cons
end.
Lemma map2_app : forall A B C (f : A -> B -> C) ls1 ls2 ls1' ls2',
(length ls1 = length ls2) ->
map2 f (ls1 ++ ls1') (ls2 ++ ls2') = map2 f ls1 ls2 ++ map2 f ls1' ls2'.
Proof.
induction ls1, ls2; intros; rewrite ?map2_nil_r, ?app_nil_l; try congruence;
simpl_list_lengths; try omega.
rewrite <-!app_comm_cons, !map2_cons.
rewrite IHls1; auto.
Qed.
Lemma firstn_update_nth {A}
: forall f m n (xs : list A), firstn m (update_nth n f xs) = update_nth n f (firstn m xs).
Proof.
induction m; destruct n, xs;
autorewrite with simpl_firstn simpl_update_nth;
congruence.
Qed.
Hint Rewrite @firstn_update_nth : push_firstn.
Hint Rewrite @firstn_update_nth : pull_update_nth.
Hint Rewrite <- @firstn_update_nth : pull_firstn.
Hint Rewrite <- @firstn_update_nth : push_update_nth.
Require Import Coq.Lists.SetoidList.
Global Instance Proper_nth_default : forall A eq,
Proper (eq==>eqlistA eq==>Logic.eq==>eq) (nth_default (A:=A)).
Proof.
do 5 intro; subst; induction 1.
+ repeat intro; rewrite !nth_default_nil; assumption.
+ repeat intro; subst; destruct y0; rewrite ?nth_default_cons, ?nth_default_cons_S; auto.
Qed.
Lemma fold_right_andb_true_map_iff A (ls : list A) f
: List.fold_right andb true (List.map f ls) = true <-> forall i, List.In i ls -> f i = true.
Proof.
induction ls; simpl; [ | rewrite Bool.andb_true_iff, IHls ]; try tauto.
intuition (congruence || eauto).
Qed.
Lemma Forall2_forall_iff : forall {A} R (xs ys : list A) d, length xs = length ys ->
(Forall2 R xs ys <-> (forall i, (i < length xs)%nat -> R (nth_default d xs i) (nth_default d ys i))).
Proof.
split; intros.
+ revert xs ys H H0 H1.
induction i; intros; destruct H0; distr_length; autorewrite with push_nth_default; auto.
eapply IHi; auto. omega.
+ revert xs ys H H0; induction xs; intros; destruct ys; distr_length; econstructor.
- specialize (H0 0%nat).
autorewrite with push_nth_default in *; auto.
apply H0; omega.
- apply IHxs; try omega.
intros.
specialize (H0 (S i)).
autorewrite with push_nth_default in *; auto.
apply H0; omega.
Qed.
Lemma nth_default_firstn : forall {A} (d : A) l i n,
nth_default d (firstn n l) i = if le_dec n (length l)
then if lt_dec i n then nth_default d l i else d
else nth_default d l i.
Proof.
induction n; intros; break_if; autorewrite with push_nth_default; auto; try omega.
+ rewrite (firstn_succ d) by omega.
autorewrite with push_nth_default; repeat (break_if; distr_length);
rewrite Min.min_l in * by omega; try omega.
- apply IHn; omega.
- replace i with n in * by omega.
rewrite Nat.sub_diag.
autorewrite with push_nth_default; auto.
- rewrite nth_default_out_of_bounds; distr_length; auto.
+ rewrite firstn_all2 by omega.
auto.
Qed.
Hint Rewrite @nth_default_firstn : push_nth_default.
Lemma nth_error_repeat {T} x n i v : nth_error (@repeat T x n) i = Some v -> v = x.
Proof.
revert n x v; induction i as [|i IHi]; destruct n; simpl in *; eauto; congruence.
Qed.
Hint Rewrite repeat_length : distr_length.
Lemma repeat_spec_iff : forall {A} (ls : list A) x n,
(length ls = n /\ forall y, In y ls -> y = x) <-> ls = repeat x n.
Proof.
split; [ revert A ls x n | intro; subst; eauto using repeat_length, repeat_spec ].
induction ls, n; simpl; intros; intuition try congruence.
f_equal; auto.
Qed.
Lemma repeat_spec_eq : forall {A} (ls : list A) x n,
length ls = n
-> (forall y, In y ls -> y = x)
-> ls = repeat x n.
Proof.
intros; apply repeat_spec_iff; auto.
Qed.
Lemma tl_repeat {A} x n : tl (@repeat A x n) = repeat x (pred n).
Proof. destruct n; reflexivity. Qed.
Lemma firstn_repeat : forall {A} x n k, firstn k (@repeat A x n) = repeat x (min k n).
Proof. induction n, k; boring. Qed.
Hint Rewrite @firstn_repeat : push_firstn.
Lemma skipn_repeat : forall {A} x n k, skipn k (@repeat A x n) = repeat x (n - k).
Proof. induction n, k; boring. Qed.
Hint Rewrite @skipn_repeat : push_skipn.
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_t
//
// Generated
// by: wig
// on: Tue Jul 4 08:39:13 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_t.v,v 1.4 2007/03/05 13:33:58 wig Exp $
// $Date: 2007/03/05 13:33:58 $
// $Log: ent_t.v,v $
// Revision 1.4 2007/03/05 13:33:58 wig
// Updated testcase output (only comments)!
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_t
//
// No user `defines in this module
module ent_t
//
// Generated Module inst_t
//
(
sig_i_a,
sig_i_a2,
sig_i_ae,
sig_o_a,
sig_o_a2,
sig_o_ae
);
// Generated Module Inputs:
input sig_i_a;
input sig_i_a2;
input [6:0] sig_i_ae;
// Generated Module Outputs:
output sig_o_a;
output sig_o_a2;
output [7:0] sig_o_ae;
// Generated Wires:
wire sig_i_a;
wire sig_i_a2;
wire [6:0] sig_i_ae;
wire sig_o_a;
wire sig_o_a2;
wire [7:0] sig_o_ae;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire sig_01;
wire sig_03;
wire sig_04;
wire [3:0] sig_05;
wire [3:0] sig_06;
wire [5:0] sig_07;
wire [8:2] sig_08;
wire [4:0] sig_13;
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_a
ent_a inst_a (
.p_mix_sig_01_go(sig_01), // Use internally test1Will create p_mix_sig_1_go port
.p_mix_sig_03_go(sig_03), // Interhierachy link, will create p_mix_sig_3_go
.p_mix_sig_04_gi(sig_04), // Interhierachy link, will create p_mix_sig_4_gi
.p_mix_sig_05_2_1_go(sig_05[2:1]), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.p_mix_sig_06_gi(sig_06), // Conflicting definition (X2)
.p_mix_sig_i_ae_gi(sig_i_ae), // Input Bus
.p_mix_sig_o_ae_go(sig_o_ae), // Output Bus
.port_i_a(sig_i_a), // Input Port
.port_o_a(sig_o_a), // Output Port
.sig_07(sig_07), // Conflicting definition, IN false!
.sig_08(sig_08), // VHDL intermediate needed (port name)
.sig_13(sig_13), // Create internal signal name
.sig_i_a2(sig_i_a2), // Input Port
.sig_o_a2(sig_o_a2) // Output Port
);
// End of Generated Instance Port Map for inst_a
// Generated Instance Port Map for inst_b
ent_b inst_b (
.port_b_1(sig_01), // Use internally test1Will create p_mix_sig_1_go port
.port_b_3(sig_03), // Interhierachy link, will create p_mix_sig_3_go
.port_b_4(sig_04), // Interhierachy link, will create p_mix_sig_4_gi
.port_b_5_1(sig_05[2]), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.port_b_5_2(sig_05[1]), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.port_b_6i(sig_06), // Conflicting definition (X2)
.port_b_6o(sig_06), // Conflicting definition (X2)
.sig_07(sig_07), // Conflicting definition, IN false!
.sig_08(sig_08) // VHDL intermediate needed (port name)
);
// End of Generated Instance Port Map for inst_b
endmodule
//
// End of Generated Module rtl of ent_t
//
//
//!End of Module/s
// --------------------------------------------------------------
|
//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// ============================================================
// File Name: CLK_LOCK.v
// Megafunction Name(s):
// altclkctrl
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.0 Build 168 06/22/2005 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altclkctrl clock_type="Global Clock" DEVICE_FAMILY="CYCLONE II" clkselect ena inclk outclk
//VERSION_BEGIN 5.0 cbx_altclkbuf 2004:11:30:11:29:52:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
//synthesis_resources = clkctrl 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module CLK_LOCK_altclkctrl_tb8
(
clkselect,
ena,
inclk,
outclk) /* synthesis synthesis_clearbox=1 */;
input [1:0] clkselect;
input ena;
input [3:0] inclk;
output outclk;
wire wire_clkctrl1_outclk;
cycloneii_clkctrl clkctrl1
(
.clkselect(clkselect),
.ena(ena),
.inclk(inclk),
.outclk(wire_clkctrl1_outclk));
defparam
clkctrl1.clock_type = "Global Clock",
clkctrl1.ena_register_mode = "none",
clkctrl1.lpm_type = "cycloneii_clkctrl";
assign
outclk = wire_clkctrl1_outclk;
endmodule //CLK_LOCK_altclkctrl_tb8
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module CLK_LOCK (
inclk,
outclk)/* synthesis synthesis_clearbox = 1 */;
input inclk;
output outclk;
wire sub_wire0;
wire sub_wire1 = 1'h1;
wire [2:0] sub_wire4 = 3'h0;
wire [1:0] sub_wire5 = 2'h0;
wire outclk = sub_wire0;
wire sub_wire2 = inclk;
wire [3:0] sub_wire3 = {sub_wire4, sub_wire2};
CLK_LOCK_altclkctrl_tb8 CLK_LOCK_altclkctrl_tb8_component (
.ena (sub_wire1),
.inclk (sub_wire3),
.clkselect (sub_wire5),
.outclk (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: clock_inputs NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: clock_type STRING "Global Clock"
// Retrieval info: USED_PORT: outclk 0 0 0 0 OUTPUT NODEFVAL "outclk"
// Retrieval info: USED_PORT: inclk 0 0 0 0 INPUT NODEFVAL "inclk"
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk 0 0 0 0
// Retrieval info: CONNECT: @clkselect 0 0 2 0 GND 0 0 2 0
// Retrieval info: CONNECT: outclk 0 0 0 0 @outclk 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 3 1 GND 0 0 3 0
// Retrieval info: CONNECT: @ena 0 0 0 0 VCC 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL CLK_LOCK.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL CLK_LOCK.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL CLK_LOCK.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL CLK_LOCK.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL CLK_LOCK_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL CLK_LOCK_bb.v FALSE FALSE
|
/*
* These source files contain a hardware description of a network
* automatically generated by CONNECT (CONfigurable NEtwork Creation Tool).
*
* This product includes a hardware design developed by Carnegie Mellon
* University.
*
* Copyright (c) 2012 by Michael K. Papamichael, Carnegie Mellon University
*
* For more information, see the CONNECT project website at:
* http://www.ece.cmu.edu/~mpapamic/connect
*
* This design is provided for internal, non-commercial research use only,
* cannot be used for, or in support of, goods or services, and is not for
* redistribution, with or without modifications.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*
*/
//
// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17)
//
// On Mon Nov 14 15:54:45 EST 2016
//
// Method conflict info:
// Method: select
// Conflict-free: select
// Sequenced before: next
//
// Method: next
// Sequenced after: select
// Conflicts: next
//
//
// Ports:
// Name I/O size props
// select O 5
// CLK I 1 clock
// RST_N I 1 reset
// select_requests I 5
// EN_next I 1
//
// Combinational paths from inputs to outputs:
// select_requests -> select
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module mkInputArbiter(CLK,
RST_N,
select_requests,
select,
EN_next);
input CLK;
input RST_N;
// value method select
input [4 : 0] select_requests;
output [4 : 0] select;
// action method next
input EN_next;
// signals for module outputs
wire [4 : 0] select;
// register arb_token
reg [4 : 0] arb_token;
wire [4 : 0] arb_token$D_IN;
wire arb_token$EN;
// remaining internal signals
wire [1 : 0] ab__h1657,
ab__h1672,
ab__h1687,
ab__h1702,
ab__h1717,
ab__h3098,
ab__h3545,
ab__h3938,
ab__h4282,
ab__h4577;
wire NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d48,
NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d68,
NOT_gen_grant_carry_2_BIT_1_4_0_AND_NOT_gen_gr_ETC___d66,
NOT_gen_grant_carry_6_BIT_1_7_1_AND_NOT_gen_gr_ETC___d57,
ab_BIT_0___h2269,
ab_BIT_0___h2376,
ab_BIT_0___h2483,
ab_BIT_0___h2590,
ab_BIT_0___h3169,
ab_BIT_0___h3305,
ab_BIT_0___h3698,
ab_BIT_0___h4042,
ab_BIT_0___h4337,
arb_token_BIT_0___h2267,
arb_token_BIT_1___h2374,
arb_token_BIT_2___h2481,
arb_token_BIT_3___h2588,
arb_token_BIT_4___h2695;
// value method select
assign select =
{ ab__h1657[1] || ab__h3098[1],
!ab__h1657[1] && !ab__h3098[1] &&
(ab__h1672[1] || ab__h3545[1]),
NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d48,
!ab__h1657[1] && !ab__h3098[1] &&
NOT_gen_grant_carry_6_BIT_1_7_1_AND_NOT_gen_gr_ETC___d57,
NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d68 } ;
// register arb_token
assign arb_token$D_IN = { arb_token[0], arb_token[4:1] } ;
assign arb_token$EN = EN_next ;
// remaining internal signals
module_gen_grant_carry instance_gen_grant_carry_9(.gen_grant_carry_c(1'd0),
.gen_grant_carry_r(select_requests[0]),
.gen_grant_carry_p(arb_token_BIT_0___h2267),
.gen_grant_carry(ab__h1717));
module_gen_grant_carry instance_gen_grant_carry_1(.gen_grant_carry_c(ab_BIT_0___h2269),
.gen_grant_carry_r(select_requests[1]),
.gen_grant_carry_p(arb_token_BIT_1___h2374),
.gen_grant_carry(ab__h1702));
module_gen_grant_carry instance_gen_grant_carry_0(.gen_grant_carry_c(ab_BIT_0___h2376),
.gen_grant_carry_r(select_requests[2]),
.gen_grant_carry_p(arb_token_BIT_2___h2481),
.gen_grant_carry(ab__h1687));
module_gen_grant_carry instance_gen_grant_carry_2(.gen_grant_carry_c(ab_BIT_0___h2483),
.gen_grant_carry_r(select_requests[3]),
.gen_grant_carry_p(arb_token_BIT_3___h2588),
.gen_grant_carry(ab__h1672));
module_gen_grant_carry instance_gen_grant_carry_3(.gen_grant_carry_c(ab_BIT_0___h2590),
.gen_grant_carry_r(select_requests[4]),
.gen_grant_carry_p(arb_token_BIT_4___h2695),
.gen_grant_carry(ab__h1657));
module_gen_grant_carry instance_gen_grant_carry_4(.gen_grant_carry_c(ab_BIT_0___h3169),
.gen_grant_carry_r(select_requests[0]),
.gen_grant_carry_p(arb_token_BIT_0___h2267),
.gen_grant_carry(ab__h4577));
module_gen_grant_carry instance_gen_grant_carry_5(.gen_grant_carry_c(ab_BIT_0___h4337),
.gen_grant_carry_r(select_requests[1]),
.gen_grant_carry_p(arb_token_BIT_1___h2374),
.gen_grant_carry(ab__h4282));
module_gen_grant_carry instance_gen_grant_carry_6(.gen_grant_carry_c(ab_BIT_0___h4042),
.gen_grant_carry_r(select_requests[2]),
.gen_grant_carry_p(arb_token_BIT_2___h2481),
.gen_grant_carry(ab__h3938));
module_gen_grant_carry instance_gen_grant_carry_7(.gen_grant_carry_c(ab_BIT_0___h3698),
.gen_grant_carry_r(select_requests[3]),
.gen_grant_carry_p(arb_token_BIT_3___h2588),
.gen_grant_carry(ab__h3545));
module_gen_grant_carry instance_gen_grant_carry_8(.gen_grant_carry_c(ab_BIT_0___h3305),
.gen_grant_carry_r(select_requests[4]),
.gen_grant_carry_p(arb_token_BIT_4___h2695),
.gen_grant_carry(ab__h3098));
assign NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d48 =
!ab__h1657[1] && !ab__h3098[1] && !ab__h1672[1] &&
!ab__h3545[1] &&
(ab__h1687[1] || ab__h3938[1]) ;
assign NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d68 =
!ab__h1657[1] && !ab__h3098[1] && !ab__h1672[1] &&
!ab__h3545[1] &&
NOT_gen_grant_carry_2_BIT_1_4_0_AND_NOT_gen_gr_ETC___d66 ;
assign NOT_gen_grant_carry_2_BIT_1_4_0_AND_NOT_gen_gr_ETC___d66 =
!ab__h1687[1] && !ab__h3938[1] && !ab__h1702[1] &&
!ab__h4282[1] &&
(ab__h1717[1] || ab__h4577[1]) ;
assign NOT_gen_grant_carry_6_BIT_1_7_1_AND_NOT_gen_gr_ETC___d57 =
!ab__h1672[1] && !ab__h3545[1] && !ab__h1687[1] &&
!ab__h3938[1] &&
(ab__h1702[1] || ab__h4282[1]) ;
assign ab_BIT_0___h2269 = ab__h1717[0] ;
assign ab_BIT_0___h2376 = ab__h1702[0] ;
assign ab_BIT_0___h2483 = ab__h1687[0] ;
assign ab_BIT_0___h2590 = ab__h1672[0] ;
assign ab_BIT_0___h3169 = ab__h1657[0] ;
assign ab_BIT_0___h3305 = ab__h3545[0] ;
assign ab_BIT_0___h3698 = ab__h3938[0] ;
assign ab_BIT_0___h4042 = ab__h4282[0] ;
assign ab_BIT_0___h4337 = ab__h4577[0] ;
assign arb_token_BIT_0___h2267 = arb_token[0] ;
assign arb_token_BIT_1___h2374 = arb_token[1] ;
assign arb_token_BIT_2___h2481 = arb_token[2] ;
assign arb_token_BIT_3___h2588 = arb_token[3] ;
assign arb_token_BIT_4___h2695 = arb_token[4] ;
// handling of inlined registers
always@(posedge CLK)
begin
if (!RST_N)
begin
arb_token <= `BSV_ASSIGNMENT_DELAY 5'd1;
end
else
begin
if (arb_token$EN) arb_token <= `BSV_ASSIGNMENT_DELAY arb_token$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
arb_token = 5'h0A;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkInputArbiter
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND4B_TB_V
`define SKY130_FD_SC_LS__AND4B_TB_V
/**
* and4b: 4-input AND, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__and4b.v"
module top();
// Inputs are registered
reg A_N;
reg B;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A_N = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A_N = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A_N = 1'bx;
end
sky130_fd_sc_ls__and4b dut (.A_N(A_N), .B(B), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND4B_TB_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:26:35 03/30/2016
// Design Name:
// Module Name: MAIN
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MAIN(ALU_OP, AB_SW, F_LED_SW, LED
);
// TOP MODULE FOR TEST
input wire [2:0] ALU_OP;
input wire [2:0] AB_SW;
input [2:0] F_LED_SW;
output reg [7:0] LED;
wire [31:0] F;
wire ZF, OF;
reg[31:0] A,B;
always@(*)
begin
case(AB_SW)
3'b000:begin A=32'h0000_0000; B=32'h0000_0000; end
3'b001:begin A=32'h0000_0003; B=32'h0000_0607; end
3'b010:begin A=32'h8000_0000; B=32'h8000_0000; end
3'b011:begin A=32'h7FFF_FFFF; B=32'h7FFF_FFFF; end
3'b100:begin A=32'hFFFF_FFFF; B=32'hFFFF_FFFF; end
3'b101:begin A=32'h8000_0000; B=32'hFFFF_FFFF; end
3'b110:begin A=32'hFFFF_FFFF; B=32'h8000_0000; end
3'b111:begin A=32'h1234_5678; B=32'h3333_2222; end
default:
begin A = 32'h9ABC_DEF0; B = 32'h1111_2222; end
endcase
end
ALU ALU (
.A(A),
.B(B),
.ZF(ZF),
.OF(OF),
.F(F),
.ALU_OP(ALU_OP)
);
always@(*)
begin
case(F_LED_SW)
3'b000: begin LED = F[7:0]; end
3'b001: begin LED = F[15:8]; end
3'b010: begin LED = F[23:16]; end
3'b011: begin LED = F[31:24]; end
default:begin LED[7] = ZF; LED[0] = OF; LED[6:1] = 6'b0; end
endcase
end
endmodule
module ALU(A, B, ZF, OF, F, ALU_OP);
input [2:0] ALU_OP;
input [31:0] A, B;
output reg [31:0] F;
output reg ZF, OF;
reg C32;
always @(*)
begin
case(ALU_OP)
3'd0:begin //and
F = A&B;
OF = 0;
end
3'd1:begin //or
F = A|B;
OF = 0;
end
3'd2:begin //xor
F = A^B;
OF = 0;
end
3'd3:begin //nor
F = ~(A|B);
OF = 0;
end
3'd4:begin //add
{C32, F} = A + B;
OF = A[31]^B[31]^F[31]^C32;
end
3'd5:begin //sub
{C32, F} = A - B;
OF = A[31]^B[31]^F[31]^C32;
end
3'd6:begin //slt
if (A<B)
begin
F = 32'd1;
end
else
begin
F = 32'd0;
end
OF = 0;
end
3'd7:begin //sll
F=B<<A;
OF=0;
end
default:begin
F=A;
OF = 0;
end
endcase
if (F == 32'd0)
begin
ZF = 1;
end
else
begin
ZF = 0;
end
end
endmodule
|
/*
*******************************************************************************
* File Name : ada_reg_file.v
* Project : ADA processor
* Version : 0.1
* Date : Aug 2nd, 2014
* Author : Angel Terrones <[email protected]>
*
* Disclaimer : Copyright © 2014 Angel Terrones
* Release under the MIT License.
*
* Description : Regiser file for the ADA processor.
* Contains 32 general-purpose 32-bits registers,
* 2 read ports, and 1 write port.
* Register 0 always reads as Zero.
*******************************************************************************
*/
module ada_reg_file(
input clk, // clock
input [4:0] read_addr_a, // Address port A
input [4:0] read_addr_b, // Address port B
input [4:0] write_addr, // Write address
input [31:0] write_data, // Data to write
input we, // Write enable
output [31:0] read_data_a, // Data port A
output [31:0] read_data_b // Data port B
);
//--------------------------------------------------------------------------
// Signal Declaration: reg
//--------------------------------------------------------------------------
reg [31:0] registers [1:31]; // Register file of 32 32-bit registers. Register 0 is hardwired to 0s
//--------------------------------------------------------------------------
// Sequential (clocked) write.
//--------------------------------------------------------------------------
always @(posedge clk) begin
if (write_addr != 0)
registers[write_addr] <= (we) ? write_data : registers[write_addr];
end
//--------------------------------------------------------------------------
// Combinatorial Read. Register 0 is all 0s.
//--------------------------------------------------------------------------
assign read_data_a = (read_addr_a == 5'b0) ? 32'h0000_0000 : registers[read_addr_a];
assign read_data_b = (read_addr_b == 5'b0) ? 32'h0000_0000 : registers[read_addr_b];
endmodule
|
// CPU and memory bundled together,
// exposing the UART bare wires
module tiny1_cpu(
input clk,
input rst, // external reset button
input [7:0] uart_din,
input uart_valid,
input uart_ready,
output [7:0] uart_out,
output uart_rd,
output uart_wr,
output reg [7:0] leds
);
wire [15:0] for_mem_addr;
wire [15:0] for_mem_data_i_ram;
wire [15:0] for_mem_data_o;
wire for_mem_wr;
wire for_mem_re;
// 16kb ram, one for all of the following:
// 16x16 virtual registers
// 16x16 IRQ mode virtual registers
// 32x16 microcode handlers table
// large microcode buffer
// and everything else
ram16k ram(.clk(clk),
.addr(for_mem_addr[14:1]),
.data_out(for_mem_data_i_ram),
.data_in(for_mem_data_o),
.we(for_mem_wr),
.re(for_mem_re));
// May be a memory-mapped I/O instead of a genuine memory access
wire mem_wr_from_core;
wire mem_re_from_core;
// Thin UART interface via mmap
wire irqack;
wire [15:0] mem_data_i_for_core;
wire [15:0] mem_data_o_from_core;
wire [15:0] mem_addr_from_core;
assign for_mem_addr = mem_addr_from_core;
assign for_mem_data_o = mem_data_o_from_core;
reg irq;
tiny1_core cpu(.clk(clk),
.rst(rst),
.irq(/*irq*/ 1'b0),
.irqack(irqack),
.mem_addr(mem_addr_from_core),
.mem_data_o(mem_data_o_from_core),
.mem_data_i(mem_data_i_for_core),
.ram_data_i(for_mem_data_i_ram),
.mem_wr(mem_wr_from_core),
.mem_rd(mem_re_from_core));
reg [15:0] mem_data_i_mmap;
wire [15:0] data_i_mmap_cl;
wire mmap;
assign mmap = mem_addr_from_core[15]; // if bit 15 set, it's mmap io
assign for_mem_wr = !mmap?mem_wr_from_core:0;
assign for_mem_re = !mmap?mem_re_from_core:0;
assign mem_data_i_for_core = mmap?mem_data_i_mmap:for_mem_data_i_ram;
// IRQ logic:
// if uart_valid && !irqack, set IRQ
// mmap io:
// Read ports:
// IO_UART_VALID - valid input from UART
// IO_UART_DIN - 8 bits from UART
// IO_UART_READY - 1 if ready to send
// Write ports:
// IO_UART_DOUT - 8 bits to UART
parameter IO_UART_VALID = 0;
parameter IO_UART_DIN = 2;
parameter IO_UART_READY = 4;
parameter IO_UART_DOUT = 6;
parameter IO_LEDS = 8;
wire [10:0] mmapaddr;
assign mmapaddr = mem_addr_from_core[10:0];
assign data_i_mmap_cl = (mmapaddr == IO_UART_VALID)?{15'b0, uart_valid}:
(mmapaddr == IO_UART_DIN)?{8'b0,uart_din}:
(mmapaddr == IO_UART_READY)?{15'b0, uart_ready}:16'b0;
assign uart_wr = (mmap && mmapaddr == IO_UART_DOUT && mem_wr_from_core);
assign uart_rd = (mmap && mmapaddr == IO_UART_DIN && mem_re_from_core);
assign uart_out = mem_data_o_from_core[7:0];
// register the mmap output
always @(posedge clk)
begin
mem_data_i_mmap <= data_i_mmap_cl;
if (mmap && mmapaddr == IO_LEDS && mem_wr_from_core) begin
leds[7:0] <= mem_data_o_from_core[7:0];
end
end
always @(posedge clk)
if (!rst) begin
irq <= 0;
end else begin
if (!irq && uart_valid) begin
irq <= 1;
end else if (irq && irqack) begin
irq <= 0;
end
end
endmodule
module tiny1_soc(
input clk,
input rst, // external reset button
input RXD,
output TXD,
output LED1,
output LED2,
output LED3,
output LED4,
output LED5
`ifndef ICESTICK
,output LED6,
output LED7,
output LED8
`endif
);
reg [7:0] resetn_counter = 0;
wire resetn = &resetn_counter;
always @(posedge clk) begin
if (!resetn)
resetn_counter <= resetn_counter + 1;
end
wire [7:0] leds;
wire [7:0] rleds;
outpin led0 (.clk(clk), .we(1'b1), .pin(LED1), .wd(leds[0]), .rd(rleds[0]));
outpin led1 (.clk(clk), .we(1'b1), .pin(LED2), .wd(leds[1]), .rd(rleds[1]));
outpin led2 (.clk(clk), .we(1'b1), .pin(LED3), .wd(leds[2]), .rd(rleds[2]));
outpin led3 (.clk(clk), .we(1'b1), .pin(LED4), .wd(leds[3]), .rd(rleds[3]));
outpin led4 (.clk(clk), .we(1'b1), .pin(LED5), .wd(leds[4]), .rd(rleds[4]));
`ifndef ICESTICK
outpin led5 (.clk(clk), .we(1'b1), .pin(LED6), .wd(leds[5]), .rd(rleds[5]));
outpin led6 (.clk(clk), .we(1'b1), .pin(LED7), .wd(leds[6]), .rd(rleds[6]));
outpin led7 (.clk(clk), .we(1'b1), .pin(LED8), .wd(leds[7]), .rd(rleds[7]));
`endif
wire [7:0] uart_din;
wire uart_valid;
wire uart_ready;
wire uart_wr;
wire uart_rd;
wire [7:0] uart_dout;
tiny1_cpu cpu(.clk(clk),
.rst(resetn),
.uart_din(uart_din),
.uart_valid(uart_valid),
.uart_ready(uart_ready),
.uart_out(uart_dout),
.uart_rd(uart_rd),
.uart_wr(uart_wr),
.leds(leds)
);
wire uart_RXD;
inpin _rcxd(.clk(clk), .pin(RXD), .rd(uart_RXD));
wire uart_busy;
assign uart_ready = ~uart_busy;
buart _uart (
.clk(clk),
.resetq(1'b1),
.rx(uart_RXD),
.tx(TXD),
.rd(uart_rd),
.wr(uart_wr),
.valid(uart_valid),
.busy(uart_busy),
.tx_data(uart_dout),
.rx_data(uart_din));
endmodule
|
module lc3_pipeline_fsm(
input clk,
input reset,
input INT,
input [15:0] ExtINTvec,
input [15:0] IntINTvec,
output reg [5:0] stall,
output reg [5:0] state,
output reg [5:0] state_next,
output reg [15:0] pc,
/*memory control input output*/
input [2:0] memapply,
input memtype,
output reg [2:0] memload,
input [15:0] memaddrin0,
input [15:0] memaddrin1,
input [15:0] memaddrin2,
output reg [15:0] memaddrout,
output reg mem_rw,
input [15:0] memdatain,
inout reg [15:0] memdataout,
/*PSR*/
output [15:0] PSR,
input [15:0] SP,
input [3:2] setCC,
input NeedCC,
input [2:0] CCin,
input [2:0] CCinM,
input [1:0] Errtype,
input [4:3] inst_ld,
input [15:0] aluout,
input [19:0] sr1,
input [19:0] sr2,
input [19:0] dr2,
input [19:0] dr3,
input [19:0] dr4,
/*branch control*/
input Forcast_fail,
input [15:0] Checked_pc,
/*fetch control*/
output reg [1:0] ld_pc,
/*reg control*/
output reg [19:0] fsm_regctl,
output reg EXC
);
reg [15:0] saved_USP;
reg [15:0] saved_SSP;
reg Priv;
reg [2:0] Priority,Priority_tmp;
reg [2:0] CC;
assign PSR={Priv,4'b0,Priority,5'b0,CC};
//TODO ld_PSR
wire ld_PSR;
assign ld_PSR=(process==2'b11)&(process_step==3'b001);
reg [1:0] process,process_next;
reg [2:0] process_step,process_step_next;
wire INTvalid;
assign INTvalid=INT&(Priority==3'b000);
wire pipeline_empty;
assign pipeline_empty = ~(state[0]|state[1]|state[2]|state[3]|state[4]|state[5]);
wire inst_checked;
assign inst_checked=(state[2] & ~stall[2]);
wire [15:0] memdata;
assign memdata=memdataout;
reg [15:0] IntVec;
reg [1:0] ld_vec;
always@(negedge clk or posedge reset)begin
if(reset)begin
process<=2'b00;
process_step<=2'b00;
state<=6'b0;
pc<=15'h0060;
saved_USP<=16'b0;
saved_SSP<=16'h3000;
Priv<=1;
Priority<=3'b000;
CC<=3'b000;
EXC<=0;
end else begin
process<=process_next;
process_step<=process_step_next;
state<=state_next;
/* if(ld_pc==2'b01)
pc<=aluout;
else */if(ld_pc==2'b10)
pc<=memdata;
else if( (inst_checked) )
pc<=Checked_pc;
if(ld_vec[1])
{IntVec,Priority_tmp}<={ExtINTvec,3'b001};
else if(ld_vec[0])
{IntVec,Priority_tmp}<={IntINTvec,3'b010};
if(ld_PSR) begin
CC<=memdata[2:0];
Priv<=memdata[15];
Priority<=memdata[10:8];
end else if (setCC[2]&inst_checked)begin
CC<=CCin;
end else if (~setCC[3]&inst_ld[4]&state[4]) begin
CC<=CCinM;
end
if(process==2'b10)
EXC<=1;
if( (process==2'b10)&&(process_step==3'b010) )
Priority<=Priority_tmp;
end
end
/*pipeline state*/
reg TRAPvalid,UND_RTIEvalid,RTIvalid;
always@(*)begin
if(inst_checked) begin
case (Errtype)
2'b01:begin
{TRAPvalid,UND_RTIEvalid,RTIvalid}=3'b100;
ld_vec=2'b01;
end
2'b10:begin
{TRAPvalid,UND_RTIEvalid,RTIvalid}={1'b0,~Priv,Priv};
ld_vec=2'b01;
end
2'b11:begin
{TRAPvalid,UND_RTIEvalid,RTIvalid}=3'b010;
ld_vec=2'b01;
end
default:begin
{TRAPvalid,UND_RTIEvalid,RTIvalid}=3'b000;
ld_vec={INTvalid&(process==2'b00),1'b0};
end
endcase
end else begin
{TRAPvalid,UND_RTIEvalid,RTIvalid}=3'b000;
ld_vec={INTvalid&(process==2'b00),1'b0};
end
end
always@(*)begin
case(process)
2'b00:
begin
state_next[5]=(state[4]&~stall[4])|(state[5]&stall[5]); //never stalled
state_next[4]=(state[3]&~stall[3])|(state[4]&stall[4]); //never stalled
if(TRAPvalid) begin
state_next[3]=(state[2]&~stall[2])|(state[3]&stall[3]); //stalled when waiting memory
state_next[2]=state[2]& stall[2];
state_next[1:0]=2'b0;
process_next=2'b01; //TRAP
process_step_next=3'b0;
end
else if(UND_RTIEvalid) begin
state_next[3]=(state[2]&~stall[2])|(state[3]&stall[3]); //stalled when waiting memory
state_next[2]=state[2]&stall[2];
state_next[1:0]=2'b0;
process_next=2'b10;
process_step_next=3'b0;
end
else if(RTIvalid) begin
state_next[3]=(state[2]&~stall[2])|(state[3]&stall[3]); //stalled when waiting memory
state_next[2]=state[2]&stall[2];
state_next[1:0]=2'b0;
process_next=2'b11; //RTI
process_step_next=3'b0;
end
else if(Forcast_fail) begin
state_next[3]=(state[2]&~stall[2])|(state[3]&stall[3]); //stalled when waiting memory
state_next[2]=state[2]&stall[2];
state_next[1:0]=2'b01;
process_next=2'b00;
process_step_next=3'b0;
end
else if(INTvalid) begin
state_next[3]=(state[3]&stall[3]); //stalled when waiting memory
state_next[2]=state[2]&stall[2];
state_next[1:0]=2'b0; //punish
process_next=2'b10; //INT,UND,RTIerr
process_step_next=3'b0;
end
else begin
state_next[3]=(state[2]&~stall[2])|(state[3]&stall[3]); //stalled when waiting memory
state_next[2]=(state[1]&!stall[1])|(state[2]&stall[2]); //stalled when waiting data or pipeline3 stalled
state_next[1]=(state[0]&!stall[0])|(state[1]&stall[1]); //stalled when pipeline2 stalled
state_next[0]=1; //stalled or new inst
process_next=2'b00;
process_step_next=3'b0;
end
end
2'b01:
begin
if(pipeline_empty) begin
process_next=2'b00;
process_step_next=3'b000;
state_next=6'b000001;
end else begin
state_next[5]=(state[4]&!stall[4])|(state[5]&stall[5]); //never stalled
state_next[4]=(state[3]&!stall[3])|(state[4]&stall[4]); //never stalled
state_next[3]=(state[2]&!stall[2])|(state[3]&stall[3]); //stalled when waiting memory
state_next[2]=(state[1]&!stall[1])|(state[2]&stall[2]); //stalled when waiting data or pipeline3 stalled
state_next[1:0]=2'b00;
process_next=2'b01;
process_step_next=3'b0;
end
end
2'b10:
begin
if(pipeline_empty) begin
case(process_step)
3'b000:
begin
process_next=2'b10;
process_step_next=3'b001;
state_next=6'b000000;
end
3'b001:
begin
process_next=2'b10;
process_step_next=3'b010;
state_next=6'b000000;
end
3'b010:
begin
process_next=2'b00;
process_step_next=3'b000;
state_next=6'b000001;
end
default:
begin
process_next=2'b00;
process_step_next=3'b000;
state_next=6'b000001;
end
endcase
end else begin
state_next[5]=(state[4]&!stall[4])|(state[5]&stall[5]); //never stalled
state_next[4]=(state[3]&!stall[3])|(state[4]&stall[4]); //never stalled
state_next[3]=(state[2]&!stall[2])|(state[3]&stall[3]); //stalled when waiting memory
state_next[2]=(state[1]&!stall[1])|(state[2]&stall[2]); //stalled when waiting data or pipeline3 stalled
state_next[1:0]=2'b00;
process_next=2'b10;
process_step_next=3'b0;
end
end
2'b11:
begin
if(pipeline_empty) begin
case(process_step)
3'b000:
begin
process_next=2'b11;
process_step_next=3'b001;
state_next=6'b000000;
end
3'b001:
begin
process_next=2'b11;
process_step_next=3'b010;
state_next=6'b000000;
end
3'b010:
begin
process_next=2'b00;
process_step_next=3'b000;
state_next=6'b000001;
end
default:
begin
process_next=2'b00;
process_step_next=3'b000;
state_next=6'b000001;
end
endcase
end else begin
state_next[5]=(state[4]&!stall[4])|(state[5]&stall[5]); //never stalled
state_next[4]=(state[3]&!stall[3])|(state[4]&stall[4]); //never stalled
state_next[3]=(state[2]&!stall[2])|(state[3]&stall[3]); //stalled when waiting memory
state_next[2]=(state[1]&!stall[1])|(state[2]&stall[2]); //stalled when waiting data or pipeline3 stalled
state_next[1:0]=2'b00;
process_next=2'b11;
process_step_next=3'b0;
end
end
endcase
end
reg int_memapply;
reg [15:0] int_memaddr;
reg int_mem_rw;
reg [15:0] int_mem_data;
/*datapath control signal ld_pc fsm_regwr int_mem*/
always@(*)begin
case(process)
2'b00:
begin
int_memapply=0;
fsm_regctl={1'b0,19'bx};
if(Forcast_fail)
ld_pc=2'b01;
else if(stall[0])
ld_pc=2'b11;
else if(pipeline_empty)
ld_pc=2'b11;
else
ld_pc=2'b00;
end
2'b01:
begin
if(pipeline_empty) begin
int_memapply=1;
int_memaddr=IntVec;
int_mem_rw=0;
int_mem_data=16'bx;
fsm_regctl={1'b1,3'b111,pc};
ld_pc=2'b10; //pipeline0 ld pc from memory
end else begin
int_memapply=0;
fsm_regctl={1'b0,19'bx};
ld_pc=2'b11;
end
end
2'b10:
begin
if(pipeline_empty) begin
case(process_step)
3'b000:
begin
int_memapply=1;
int_memaddr=SP-1;
int_mem_rw=1;
int_mem_data=PSR;
fsm_regctl[19:16]={1'b1,3'b110};
fsm_regctl[15:0] =SP-1;
ld_pc=2'b11;
end
3'b001:
begin
int_memapply=1;
int_memaddr=SP-1;
int_mem_rw=1;
int_mem_data=pc;
fsm_regctl[19:16]={1'b1,3'b110};
fsm_regctl[15:0] =SP-1;
ld_pc=2'b11; //PC not changed
end
3'b010:
begin
int_memapply=1;
int_memaddr=IntVec;
int_mem_rw=0;
int_mem_data=16'bx;
fsm_regctl={1'b0,19'bx};
ld_pc=2'b10; //pipeline0 ld pc from memory
end
default:
begin
int_memapply=0;
fsm_regctl={1'b0,19'bx};
ld_pc=2'b11;
end
endcase
end else begin
int_memapply=0;
fsm_regctl={1'b0,19'bx};
ld_pc=2'b11;
end
end
2'b11:
begin
if(pipeline_empty) begin
case(process_step)
3'b000:
begin
int_memapply=1;
int_memaddr=SP;
int_mem_rw=0;
int_mem_data=16'bz;
fsm_regctl[19:16]={1'b1,3'b110};
fsm_regctl[15:0] =SP+1;
ld_pc=2'b10;
end
3'b001:
begin
int_memapply=1;
int_memaddr=SP;
int_mem_rw=0;
int_mem_data=16'bz;
fsm_regctl[19:16]={1'b1,3'b110};
fsm_regctl[15:0] =SP+1;
ld_pc=2'b11;
end
3'b010:
begin
int_memapply=0;
fsm_regctl={1'b0,19'bx};
ld_pc=2'b11; //pc not changed
end
default:
begin
int_memapply=0;
fsm_regctl={1'b0,19'bx};
ld_pc=2'b11;
end
endcase
end else begin
int_memapply=0;
fsm_regctl={1'b0,19'bx};
ld_pc=2'b00;
end
end
endcase
end
/*mem ctl*/
always@(*) begin
if(memapply[2] & state[4]) begin
memload=3'b100;
mem_rw=memtype;
memaddrout=memaddrin2;
memdataout=(memtype?memdatain:16'bz);
end else if (memapply[1] & state[3]) begin
memload=3'b010;
mem_rw=0;
memaddrout=memaddrin1;
memdataout=16'bz;
end else if (memapply[0] & state[0]) begin
memload=3'b001;
mem_rw=0;
memaddrout=memaddrin0;
memdataout=16'bz;
end else if (int_memapply) begin
memload=3'b000;
mem_rw=int_mem_rw;
memaddrout=int_memaddr;
memdataout=(int_mem_rw?int_mem_data:16'bz);
end else begin
memload=3'b000;
mem_rw=0;
memaddrout=16'bx;
memdataout=16'bz;
end
end
/*stall*/
wire waitdata;
always@(*)begin
stall[5]=0; //never stalled
stall[4]=0; //never stalled
if (memapply[1] & memapply[2] )
stall[3]=1; //wait memory
else
stall[3]=0;
if (waitdata | stall[3])
stall[2]=1;
else
stall[2]=0;
if (stall[2])
stall[1]=1;
else
stall[1]=0;
if (stall[1] | (memapply[0] & (memload!=3'b001) ) )
stall[0]=1;
else
stall[0]=0;
end
/*waitdata*/
wire [4:3] loading;
assign loading[4]=state[4] & inst_ld[4];
assign loading[3]=state[3] & inst_ld[3];
reg waitSR;
reg waitCC;
assign waitdata=waitSR|waitCC;
always@(*)begin
if(!state[2]) begin
waitSR=0;
end
else begin
if(loading==2'b00)
waitSR=0;
else if(loading[4]) begin
if(sr1[19]&& (dr4[18:16]==sr1[18:16]) )
waitSR=1;
else if(sr2[19] && (dr4[18:16]==sr2[18:16]) )
waitSR=1;
else if(dr2[19] && (dr4[18:16]==dr2[18:16]) )
waitSR=1;
else
waitSR=0;
end
else if(loading[3]) begin
if(sr1[19]&& (dr3[18:16]==sr1[18:16]) )
waitSR=1;
else if(sr2[19] && (dr3[18:16]==sr2[18:16]) )
waitSR=1;
else if(dr2[19] && (dr3[18:16]==dr2[18:16]) )
waitSR=1;
else
waitSR=0;
end else
waitSR=0;
end
end
always@(*)begin
if(!state[2]) begin
waitCC=0;
end
else if(!NeedCC) begin
waitCC=0;
end
else begin
if(loading==2'b00)
waitCC=0;
else
waitCC=1;
end
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:08:01 02/19/2016
// Design Name: tp_final
// Module Name: /home/poche002/Desktop/ArqComp/Trabajo_final/arquitectura_tpf/tp_final_tb.v
// Project Name: arquitectura_tpf
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: tp_final
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tp_final_tb;
// Inputs
reg clk;
reg reset;
reg rx;
// Outputs
wire tx;
//Para test
//wire [1:0] op;
wire ena_pip_test;
wire [31:0] pc_PC_out_test;
wire [31:0] instruction_IF_test;
wire [31:0] write_data_WB_out_test;
//wire stallF_HZ_out_test;
//wire [2:0] state_reg_test;
//wire rx_empty_test;
//wire rx_done_tick_test;
//wire [7:0] rx_data_out_test;
//wire [7:0] write_data_test;
//wire [3:0] byteN_test;
//wire [7:0] reg_0;
//wire [7:0] reg_1;
//wire [7:0] reg_2;
//wire [7:0] reg_3;
//wire tick_test;
integer ciclo;
//wire [7:0] fifo_data;
//wire fifo_full;
//wire [1:0] state_test;
wire [7:0] led;
// Instantiate the Unit Under Test (UUT)
tp_final uut (
.clk(clk),
.reset(reset),
.rx(rx),
.tx(tx),
.led(led),
//.op(op),
.ena_pip_test(ena_pip_test),
.pc_incrementado_PC_out_test(pc_PC_out_test),
.instruction_IF_test(instruction_IF_test),
.write_data_WB_out_test(write_data_WB_out_test)
//.stallF_HZ_out_test(stallF_HZ_out_test)
//.state_reg_test(state_reg_test)
//.rx_empty_test(rx_empty_test),
//.btn_read_reg_test(btn_read_reg_test),
//.write_data_test(write_data_test),
//.byteN_test(byteN_test)
//.reg_0(reg_0),
//.reg_1(reg_1),
//.reg_2(reg_2),
//.reg_3(reg_3),
//.rx_done_tick_test(rx_done_tick_test),
//.rx_data_out_test(rx_data_out_test),
//.tick_test(tick_test),
//.fifo_data(fifo_data),
//.fifo_full(fifo_full),
//.state_test(state_test)
);
initial begin
// Initialize Inputs
clk = 0;
rx = 1;
reset = 0;
ciclo= 0;
// Wait 100 ns for global reset to finish
#1 reset = 1;
#1 reset = 0;
//1 byte 0000_0010
/*
#64 rx=0;
#64 rx=0;
#64 rx=1;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=1;
#8000
//0000_0010
#64 rx=0;
#64 rx=0;
#64 rx=1;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=1;
#8000
//0000_0010
#64 rx=0;
#64 rx=0;
#64 rx=1;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=1;
#8000
//0000_0010
#64 rx=0;
#64 rx=0;
#64 rx=1;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=1;
#8000
//0000_0010
#64 rx=0;
#64 rx=0;
#64 rx=1;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=1;
#8000
//0000_0010
#64 rx=0;
#64 rx=0;
#64 rx=1;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=1;
#8000
//0000_0010
#64 rx=0;
#64 rx=0;
#64 rx=1;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=1;
#8000
//0000_0010
#64 rx=0;
#64 rx=0;
#64 rx=1;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=1;
#8000
//0000_0010
#64 rx=0;
#64 rx=0;
#64 rx=1;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=1;
*/
#8000
//0000_0010
#64 rx=0;
#64 rx=1;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=1;
//0000_0011
/*
#64 rx=0;
#64 rx=1;
#64 rx=1;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=1;
*/
//#10000 reset = 1'b1;
//#2 reset = 1'b0;
// Add stimulus here
end
always
begin
#1
clk=~clk;
#1
clk=~clk;
ciclo = ciclo + 1;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISO0N_TB_V
`define SKY130_FD_SC_LP__ISO0N_TB_V
/**
* iso0n: ????.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__iso0n.v"
module top();
// Inputs are registered
reg A;
reg SLEEP_B;
reg VPWR;
reg KAGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
KAGND = 1'bX;
SLEEP_B = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 KAGND = 1'b0;
#60 SLEEP_B = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 KAGND = 1'b1;
#180 SLEEP_B = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 KAGND = 1'b0;
#300 SLEEP_B = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 SLEEP_B = 1'b1;
#460 KAGND = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 SLEEP_B = 1'bx;
#580 KAGND = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_lp__iso0n dut (.A(A), .SLEEP_B(SLEEP_B), .VPWR(VPWR), .KAGND(KAGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISO0N_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XNOR2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__XNOR2_FUNCTIONAL_PP_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__xnor2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xnor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y , A, B );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, xnor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__XNOR2_FUNCTIONAL_PP_V |
`timescale 1 ns / 100 ps
// ********************************************************************/
// Actel Corporation Proprietary and Confidential
// Copyright 2009 Actel Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
// Description: AMBA BFMs
// AHB Lite BFM
//
// Revision Information:
// Date Description
// 01Sep07 Initial Release
// 14Sep07 Updated for 1.2 functionality
// 25Sep07 Updated for 1.3 functionality
// 09Nov07 Updated for 1.4 functionality
// 08May08 2.0 for Soft IP Usage
//
// SVN Revision Information:
// SVN $Revision: 21608 $
// SVN $Date: 2013-12-02 16:03:36 -0800 (Mon, 02 Dec 2013) $
//
//
// Resolved SARs
// SAR Date Who Description
//
//
// Notes:
// 28Nov07 IPB Updated to increase throughput
//
// *********************************************************************/
module BFM_APB2APB ( PCLK_PM, PRESETN_PM, PADDR_PM, PWRITE_PM, PENABLE_PM, PWDATA_PM, PRDATA_PM, PREADY_PM, PSLVERR_PM,
PCLK_SC, PSEL_SC, PADDR_SC, PWRITE_SC, PENABLE_SC, PWDATA_SC, PRDATA_SC, PREADY_SC, PSLVERR_SC);
parameter[9:0] TPD = 1;
localparam TPDns = TPD * 1;
input PCLK_PM;
input PRESETN_PM;
input[31:0] PADDR_PM;
input PWRITE_PM;
input PENABLE_PM;
input[31:0] PWDATA_PM;
output[31:0] PRDATA_PM;
reg[31:0] PRDATA_PM;
output PREADY_PM;
reg PREADY_PM;
output PSLVERR_PM;
reg PSLVERR_PM;
input PCLK_SC;
output[15:0] PSEL_SC;
wire[15:0] #TPDns PSEL_SC;
output[31:0] PADDR_SC;
wire[31:0] #TPDns PADDR_SC;
output PWRITE_SC;
wire #TPDns PWRITE_SC;
output PENABLE_SC;
wire #TPDns PENABLE_SC;
output[31:0] PWDATA_SC;
wire[31:0] #TPDns PWDATA_SC;
input[31:0] PRDATA_SC;
input PREADY_SC;
input PSLVERR_SC;
parameter[0:0] IDLE = 0;
parameter[0:0] ACTIVE = 1;
reg[0:0] STATE_PM;
parameter[1:0] T0 = 0;
parameter[1:0] T1 = 1;
parameter[1:0] T2 = 2;
reg[1:0] STATE_SC;
reg[15:0] PSEL_P0;
reg[31:0] PADDR_P0;
reg PWRITE_P0;
reg PENABLE_P0;
reg[31:0] PWDATA_P0;
reg PSELEN;
reg[31:0] PRDATA_HD;
reg PSLVERR_HD;
reg PENABLE_PM_P0;
reg TRIGGER;
reg DONE;
always @(posedge PCLK_PM or negedge PRESETN_PM)
begin
if (PRESETN_PM == 1'b0)
begin
STATE_PM <= IDLE ;
TRIGGER <= 1'b0 ;
PREADY_PM <= 1'b0 ;
PSLVERR_PM <= 1'b0 ;
PRDATA_PM <= {32{1'b0}} ;
PENABLE_PM_P0 <= 1'b0 ;
end
else
begin
PREADY_PM <= 1'b0 ;
PENABLE_PM_P0 <= PENABLE_PM ;
case (STATE_PM)
IDLE :
begin
if (PENABLE_PM == 1'b1 & PENABLE_PM_P0 == 1'b0)
begin
TRIGGER <= 1'b1 ;
STATE_PM <= ACTIVE ;
end
end
ACTIVE :
begin
if (DONE == 1'b1)
begin
STATE_PM <= IDLE ;
TRIGGER <= 1'b0 ;
PREADY_PM <= 1'b1 ;
PSLVERR_PM <= PSLVERR_HD ;
PRDATA_PM <= PRDATA_HD ;
end
end
endcase
end
end
always @(posedge PCLK_SC or negedge TRIGGER)
begin
if (TRIGGER == 1'b0)
begin
STATE_SC <= T0 ;
DONE <= 1'b0 ;
PRDATA_HD <= {32{1'b0}} ;
PSLVERR_HD <= 1'b0 ;
PSELEN <= 1'b0 ;
PENABLE_P0 <= 1'b0 ;
PADDR_P0 <= {32{1'b0}} ;
PWDATA_P0 <= {32{1'b0}} ;
PWRITE_P0 <= 1'b0 ;
end
else
begin
case (STATE_SC)
T0 :
begin
STATE_SC <= T1 ;
PADDR_P0 <= PADDR_PM ;
PWDATA_P0 <= PWDATA_PM ;
PWRITE_P0 <= PWRITE_PM ;
PSELEN <= 1'b1 ;
PENABLE_P0 <= 1'b0 ;
DONE <= 1'b0 ;
end
T1 :
begin
STATE_SC <= T2 ;
PENABLE_P0 <= 1'b1 ;
end
T2 :
begin
if (PREADY_SC == 1'b1)
begin
DONE <= 1'b1 ;
PRDATA_HD <= PRDATA_SC ;
PSLVERR_HD <= PSLVERR_SC ;
PSELEN <= 1'b0 ;
PENABLE_P0 <= 1'b0 ;
PADDR_P0 <= {32{1'b0}} ;
PWDATA_P0 <= {32{1'b0}} ;
PWRITE_P0 <= 1'b0 ;
end
end
endcase
end
end
always @(PADDR_P0 or PSELEN)
begin
PSEL_P0 <= {16{1'b0}} ;
if (PSELEN == 1'b1)
begin
begin : xhdl_5
integer i;
for(i = 0; i <= 15; i = i + 1)
begin
PSEL_P0[i] <= (PADDR_P0[27:24] == i);
end
end
end
end
assign PSEL_SC = PSEL_P0 ;
assign PADDR_SC = PADDR_P0 ;
assign PWRITE_SC = PWRITE_P0 ;
assign PENABLE_SC = PENABLE_P0 ;
assign PWDATA_SC = PWDATA_P0 ;
endmodule
|
//############################################################################
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// (C) Copyright Laboratory System Integration and Silicon Implementation
// All Right Reserved
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// ICLAB 2016 Fall
// Lab01-Practice : Polynomial Integrator
// Author : Chien-Tung, Shih ([email protected])
//
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// File Name : TESETBED.v
// Module Name : TESETBED
// Release version : V1.0 (Release Date: 2016-09)
//
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//############################################################################
`timescale 1ns/10ps
`include "PATTERN.v"
`ifdef RTL
`include "OT11_27.v"
`endif
`ifdef GATE
`include "OT11_27_SYN.v"
`endif
module TESTBED;
wire clk,rst_n,in_valid1,in_valid2;
wire [7:0]in,bomb;
wire [5:0]hit;
wire out_valid;
wire [6:0] out;
initial begin
`ifdef RTL
$fsdbDumpfile("OT11_27.fsdb");
$fsdbDumpvars();
`endif
`ifdef GATE
$sdf_annotate("OT11_27_SYN.sdf",U_OT11_27);
$fsdbDumpfile("OT11_27_SYN.fsdb");
$fsdbDumpvars();
`endif
end
OT11_27 U_OT11_27 (
clk,
rst_n,
in,
bomb,
in_valid1,
hit,
in_valid2,
// Input signals
out_valid,
out
);
PATTERN I_PATTERN(
clk,
rst_n,
in,
bomb,
in_valid1,
hit,
in_valid2,
// Input signals
out_valid,
out
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XOR3_TB_V
`define SKY130_FD_SC_LP__XOR3_TB_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__xor3.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_lp__xor3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__XOR3_TB_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:58:51 03/02/2016
// Design Name: aluCtr
// Module Name: G:/ceshi/lab3.2/test_for_aluCtr.v
// Project Name: lab3.2
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: aluCtr
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_for_aluCtr;
// Inputs
reg [1:0] aluOp;
reg [5:0] funct;
// Outputs
wire [3:0] aluCtr;
// Instantiate the Unit Under Test (UUT)
aluCtr uut (
.aluOp(aluOp),
.funct(funct),
.aluCtr(aluCtr)
);
initial begin
// Initialize Inputs
aluOp = 0;
funct = 0;
// Wait 100 ns for global reset to finish
#100;
#100 aluOp = 2'b00;
#100 aluOp = 2'b01;
#100 aluOp = 2'b10; funct = 6'b000000;
#100 aluOp = 2'b10; funct = 6'b000010;
#100 aluOp = 2'b10; funct = 6'b000010;
#100 aluOp = 2'b10; funct = 6'b000100;
#100 aluOp = 2'b10; funct = 6'b000101;
#100 aluOp = 2'b10; funct = 6'b001010;
// Add stimulus here
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_PWRGOOD_PP_PG_SYMBOL_V
`define SKY130_FD_SC_HDLL__UDP_PWRGOOD_PP_PG_SYMBOL_V
/**
* UDP_OUT :=x when VPWR!=1 or VGND!=0
* UDP_OUT :=UDP_IN when VPWR==1 and VGND==0
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__udp_pwrgood_pp$PG (
//# {{data|Data Signals}}
input UDP_IN ,
output UDP_OUT,
//# {{power|Power}}
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_PWRGOOD_PP_PG_SYMBOL_V
|
//Define 32 bit multiplexer
module UMultiplier(O, X, Y);
// I/O port declaration
input [31:0] X, Y;
output [63:0] O;
//internal nets
wire [1023:0] C;
wire [639:0]sum, carry;
wire [447:0] sum_1,carry_1;
wire [319:0] sum_2,carry_2;
wire [191:0] sum_3,carry_3;
wire [127:0] sum_4,carry_4;
wire [63:0] sum_5,carry_5;
wire [63:0] sum_6,carry_6;
wire [63:0] sum_7,carry_7;
wire [63:0] carry_8;
//Instantiate logic gate primitives
//1.1
//PP0
and (C[0], X[0], Y[0]);
and (C[1], X[1], Y[0]);
and (C[2], X[2], Y[0]);
and (C[3], X[3], Y[0]);
and (C[4], X[4], Y[0]);
and (C[5], X[5], Y[0]);
and (C[6], X[6], Y[0]);
and (C[7], X[7], Y[0]);
and (C[8], X[8], Y[0]);
and (C[9], X[9], Y[0]);
and (C[10], X[10], Y[0]);
and (C[11], X[11], Y[0]);
and (C[12], X[12], Y[0]);
and (C[13], X[13], Y[0]);
and (C[14], X[14], Y[0]);
and (C[15], X[15], Y[0]);
and (C[16], X[16], Y[0]);
and (C[17], X[17], Y[0]);
and (C[18], X[18], Y[0]);
and (C[19], X[19], Y[0]);
and (C[20], X[20], Y[0]);
and (C[21], X[21], Y[0]);
and (C[22], X[22], Y[0]);
and (C[23], X[23], Y[0]);
and (C[24], X[24], Y[0]);
and (C[25], X[25], Y[0]);
and (C[26], X[26], Y[0]);
and (C[27], X[27], Y[0]);
and (C[28], X[28], Y[0]);
and (C[29], X[29], Y[0]);
and (C[30], X[30], Y[0]);
and (C[31], X[31], Y[0]);
//PP1
and (C[32], X[0], Y[1]);
and (C[33], X[1], Y[1]);
and (C[34], X[2], Y[1]);
and (C[35], X[3], Y[1]);
and (C[36], X[4], Y[1]);
and (C[37], X[5], Y[1]);
and (C[38], X[6], Y[1]);
and (C[39], X[7], Y[1]);
and (C[40], X[8], Y[1]);
and (C[41], X[9], Y[1]);
and (C[42], X[10], Y[1]);
and (C[43], X[11], Y[1]);
and (C[44], X[12], Y[1]);
and (C[45], X[13], Y[1]);
and (C[46], X[14], Y[1]);
and (C[47], X[15], Y[1]);
and (C[48], X[16], Y[1]);
and (C[49], X[17], Y[1]);
and (C[50], X[18], Y[1]);
and (C[51], X[19], Y[1]);
and (C[52], X[20], Y[1]);
and (C[53], X[21], Y[1]);
and (C[54], X[22], Y[1]);
and (C[55], X[23], Y[1]);
and (C[56], X[24], Y[1]);
and (C[57], X[25], Y[1]);
and (C[58], X[26], Y[1]);
and (C[59], X[27], Y[1]);
and (C[60], X[28], Y[1]);
and (C[61], X[29], Y[1]);
and (C[62], X[30], Y[1]);
and (C[63], X[31], Y[1]);
//PP2
and (C[64], X[0], Y[2]);
and (C[65], X[1], Y[2]);
and (C[66], X[2], Y[2]);
and (C[67], X[3], Y[2]);
and (C[68], X[4], Y[2]);
and (C[69], X[5], Y[2]);
and (C[70], X[6], Y[2]);
and (C[71], X[7], Y[2]);
and (C[72], X[8], Y[2]);
and (C[73], X[9], Y[2]);
and (C[74], X[10], Y[2]);
and (C[75], X[11], Y[2]);
and (C[76], X[12], Y[2]);
and (C[77], X[13], Y[2]);
and (C[78], X[14], Y[2]);
and (C[79], X[15], Y[2]);
and (C[80], X[16], Y[2]);
and (C[81], X[17], Y[2]);
and (C[82], X[18], Y[2]);
and (C[83], X[19], Y[2]);
and (C[84], X[20], Y[2]);
and (C[85], X[21], Y[2]);
and (C[86], X[22], Y[2]);
and (C[87], X[23], Y[2]);
and (C[88], X[24], Y[2]);
and (C[89], X[25], Y[2]);
and (C[90], X[26], Y[2]);
and (C[91], X[27], Y[2]);
and (C[92], X[28], Y[2]);
and (C[93], X[29], Y[2]);
and (C[94], X[30], Y[2]);
and (C[95], X[31], Y[2]);
//PP3
and (C[96], X[0], Y[3]);
and (C[97], X[1], Y[3]);
and (C[98], X[2], Y[3]);
and (C[99], X[3], Y[3]);
and (C[100], X[4], Y[3]);
and (C[101], X[5], Y[3]);
and (C[102], X[6], Y[3]);
and (C[103], X[7], Y[3]);
and (C[104], X[8], Y[3]);
and (C[105], X[9], Y[3]);
and (C[106], X[10], Y[3]);
and (C[107], X[11], Y[3]);
and (C[108], X[12], Y[3]);
and (C[109], X[13], Y[3]);
and (C[110], X[14], Y[3]);
and (C[111], X[15], Y[3]);
and (C[112], X[16], Y[3]);
and (C[113], X[17], Y[3]);
and (C[114], X[18], Y[3]);
and (C[115], X[19], Y[3]);
and (C[116], X[20], Y[3]);
and (C[117], X[21], Y[3]);
and (C[118], X[22], Y[3]);
and (C[119], X[23], Y[3]);
and (C[120], X[24], Y[3]);
and (C[121], X[25], Y[3]);
and (C[122], X[26], Y[3]);
and (C[123], X[27], Y[3]);
and (C[124], X[28], Y[3]);
and (C[125], X[29], Y[3]);
and (C[126], X[30], Y[3]);
and (C[127], X[31], Y[3]);
//PP4
and (C[128], X[0], Y[4]);
and (C[129], X[1], Y[4]);
and (C[130], X[2], Y[4]);
and (C[131], X[3], Y[4]);
and (C[132], X[4], Y[4]);
and (C[133], X[5], Y[4]);
and (C[134], X[6], Y[4]);
and (C[135], X[7], Y[4]);
and (C[136], X[8], Y[4]);
and (C[137], X[9], Y[4]);
and (C[138], X[10], Y[4]);
and (C[139], X[11], Y[4]);
and (C[140], X[12], Y[4]);
and (C[141], X[13], Y[4]);
and (C[142], X[14], Y[4]);
and (C[143], X[15], Y[4]);
and (C[144], X[16], Y[4]);
and (C[145], X[17], Y[4]);
and (C[146], X[18], Y[4]);
and (C[147], X[19], Y[4]);
and (C[148], X[20], Y[4]);
and (C[149], X[21], Y[4]);
and (C[150], X[22], Y[4]);
and (C[151], X[23], Y[4]);
and (C[152], X[24], Y[4]);
and (C[153], X[25], Y[4]);
and (C[154], X[26], Y[4]);
and (C[155], X[27], Y[4]);
and (C[156], X[28], Y[4]);
and (C[157], X[29], Y[4]);
and (C[158], X[30], Y[4]);
and (C[159], X[31], Y[4]);
//PP5
and (C[160], X[0], Y[5]);
and (C[161], X[1], Y[5]);
and (C[162], X[2], Y[5]);
and (C[163], X[3], Y[5]);
and (C[164], X[4], Y[5]);
and (C[165], X[5], Y[5]);
and (C[166], X[6], Y[5]);
and (C[167], X[7], Y[5]);
and (C[168], X[8], Y[5]);
and (C[169], X[9], Y[5]);
and (C[170], X[10], Y[5]);
and (C[171], X[11], Y[5]);
and (C[172], X[12], Y[5]);
and (C[173], X[13], Y[5]);
and (C[174], X[14], Y[5]);
and (C[175], X[15], Y[5]);
and (C[176], X[16], Y[5]);
and (C[177], X[17], Y[5]);
and (C[178], X[18], Y[5]);
and (C[179], X[19], Y[5]);
and (C[180], X[20], Y[5]);
and (C[181], X[21], Y[5]);
and (C[182], X[22], Y[5]);
and (C[183], X[23], Y[5]);
and (C[184], X[24], Y[5]);
and (C[185], X[25], Y[5]);
and (C[186], X[26], Y[5]);
and (C[187], X[27], Y[5]);
and (C[188], X[28], Y[5]);
and (C[189], X[29], Y[5]);
and (C[190], X[30], Y[5]);
and (C[191], X[31], Y[5]);
//PP6
and (C[192], X[0], Y[6]);
and (C[193], X[1], Y[6]);
and (C[194], X[2], Y[6]);
and (C[195], X[3], Y[6]);
and (C[196], X[4], Y[6]);
and (C[197], X[5], Y[6]);
and (C[198], X[6], Y[6]);
and (C[199], X[7], Y[6]);
and (C[200], X[8], Y[6]);
and (C[201], X[9], Y[6]);
and (C[202], X[10], Y[6]);
and (C[203], X[11], Y[6]);
and (C[204], X[12], Y[6]);
and (C[205], X[13], Y[6]);
and (C[206], X[14], Y[6]);
and (C[207], X[15], Y[6]);
and (C[208], X[16], Y[6]);
and (C[209], X[17], Y[6]);
and (C[210], X[18], Y[6]);
and (C[211], X[19], Y[6]);
and (C[212], X[20], Y[6]);
and (C[213], X[21], Y[6]);
and (C[214], X[22], Y[6]);
and (C[215], X[23], Y[6]);
and (C[216], X[24], Y[6]);
and (C[217], X[25], Y[6]);
and (C[218], X[26], Y[6]);
and (C[219], X[27], Y[6]);
and (C[220], X[28], Y[6]);
and (C[221], X[29], Y[6]);
and (C[222], X[30], Y[6]);
and (C[223], X[31], Y[6]);
//PP7
and (C[224], X[0], Y[7]);
and (C[225], X[1], Y[7]);
and (C[226], X[2], Y[7]);
and (C[227], X[3], Y[7]);
and (C[228], X[4], Y[7]);
and (C[229], X[5], Y[7]);
and (C[230], X[6], Y[7]);
and (C[231], X[7], Y[7]);
and (C[232], X[8], Y[7]);
and (C[233], X[9], Y[7]);
and (C[234], X[10], Y[7]);
and (C[235], X[11], Y[7]);
and (C[236], X[12], Y[7]);
and (C[237], X[13], Y[7]);
and (C[238], X[14], Y[7]);
and (C[239], X[15], Y[7]);
and (C[240], X[16], Y[7]);
and (C[241], X[17], Y[7]);
and (C[242], X[18], Y[7]);
and (C[243], X[19], Y[7]);
and (C[244], X[20], Y[7]);
and (C[245], X[21], Y[7]);
and (C[246], X[22], Y[7]);
and (C[247], X[23], Y[7]);
and (C[248], X[24], Y[7]);
and (C[249], X[25], Y[7]);
and (C[250], X[26], Y[7]);
and (C[251], X[27], Y[7]);
and (C[252], X[28], Y[7]);
and (C[253], X[29], Y[7]);
and (C[254], X[30], Y[7]);
and (C[255], X[31], Y[7]);
//PP8
and (C[256], X[0], Y[8]);
and (C[257], X[1], Y[8]);
and (C[258], X[2], Y[8]);
and (C[259], X[3], Y[8]);
and (C[260], X[4], Y[8]);
and (C[261], X[5], Y[8]);
and (C[262], X[6], Y[8]);
and (C[263], X[7], Y[8]);
and (C[264], X[8], Y[8]);
and (C[265], X[9], Y[8]);
and (C[266], X[10], Y[8]);
and (C[267], X[11], Y[8]);
and (C[268], X[12], Y[8]);
and (C[269], X[13], Y[8]);
and (C[270], X[14], Y[8]);
and (C[271], X[15], Y[8]);
and (C[272], X[16], Y[8]);
and (C[273], X[17], Y[8]);
and (C[274], X[18], Y[8]);
and (C[275], X[19], Y[8]);
and (C[276], X[20], Y[8]);
and (C[277], X[21], Y[8]);
and (C[278], X[22], Y[8]);
and (C[279], X[23], Y[8]);
and (C[280], X[24], Y[8]);
and (C[281], X[25], Y[8]);
and (C[282], X[26], Y[8]);
and (C[283], X[27], Y[8]);
and (C[284], X[28], Y[8]);
and (C[285], X[29], Y[8]);
and (C[286], X[30], Y[8]);
and (C[287], X[31], Y[8]);
//PP9
and (C[288], X[0], Y[9]);
and (C[289], X[1], Y[9]);
and (C[290], X[2], Y[9]);
and (C[291], X[3], Y[9]);
and (C[292], X[4], Y[9]);
and (C[293], X[5], Y[9]);
and (C[294], X[6], Y[9]);
and (C[295], X[7], Y[9]);
and (C[296], X[8], Y[9]);
and (C[297], X[9], Y[9]);
and (C[298], X[10], Y[9]);
and (C[299], X[11], Y[9]);
and (C[300], X[12], Y[9]);
and (C[301], X[13], Y[9]);
and (C[302], X[14], Y[9]);
and (C[303], X[15], Y[9]);
and (C[304], X[16], Y[9]);
and (C[305], X[17], Y[9]);
and (C[306], X[18], Y[9]);
and (C[307], X[19], Y[9]);
and (C[308], X[20], Y[9]);
and (C[309], X[21], Y[9]);
and (C[310], X[22], Y[9]);
and (C[311], X[23], Y[9]);
and (C[312], X[24], Y[9]);
and (C[313], X[25], Y[9]);
and (C[314], X[26], Y[9]);
and (C[315], X[27], Y[9]);
and (C[316], X[28], Y[9]);
and (C[317], X[29], Y[9]);
and (C[318], X[30], Y[9]);
and (C[319], X[31], Y[9]);
//PP10
and (C[320], X[0], Y[10]);
and (C[321], X[1], Y[10]);
and (C[322], X[2], Y[10]);
and (C[323], X[3], Y[10]);
and (C[324], X[4], Y[10]);
and (C[325], X[5], Y[10]);
and (C[326], X[6], Y[10]);
and (C[327], X[7], Y[10]);
and (C[328], X[8], Y[10]);
and (C[329], X[9], Y[10]);
and (C[330], X[10], Y[10]);
and (C[331], X[11], Y[10]);
and (C[332], X[12], Y[10]);
and (C[333], X[13], Y[10]);
and (C[334], X[14], Y[10]);
and (C[335], X[15], Y[10]);
and (C[336], X[16], Y[10]);
and (C[337], X[17], Y[10]);
and (C[338], X[18], Y[10]);
and (C[339], X[19], Y[10]);
and (C[340], X[20], Y[10]);
and (C[341], X[21], Y[10]);
and (C[342], X[22], Y[10]);
and (C[343], X[23], Y[10]);
and (C[344], X[24], Y[10]);
and (C[345], X[25], Y[10]);
and (C[346], X[26], Y[10]);
and (C[347], X[27], Y[10]);
and (C[348], X[28], Y[10]);
and (C[349], X[29], Y[10]);
and (C[350], X[30], Y[10]);
and (C[351], X[31], Y[10]);
//PP11
and (C[352], X[0], Y[11]);
and (C[353], X[1], Y[11]);
and (C[354], X[2], Y[11]);
and (C[355], X[3], Y[11]);
and (C[356], X[4], Y[11]);
and (C[357], X[5], Y[11]);
and (C[358], X[6], Y[11]);
and (C[359], X[7], Y[11]);
and (C[360], X[8], Y[11]);
and (C[361], X[9], Y[11]);
and (C[362], X[10], Y[11]);
and (C[363], X[11], Y[11]);
and (C[364], X[12], Y[11]);
and (C[365], X[13], Y[11]);
and (C[366], X[14], Y[11]);
and (C[367], X[15], Y[11]);
and (C[368], X[16], Y[11]);
and (C[369], X[17], Y[11]);
and (C[370], X[18], Y[11]);
and (C[371], X[19], Y[11]);
and (C[372], X[20], Y[11]);
and (C[373], X[21], Y[11]);
and (C[374], X[22], Y[11]);
and (C[375], X[23], Y[11]);
and (C[376], X[24], Y[11]);
and (C[377], X[25], Y[11]);
and (C[378], X[26], Y[11]);
and (C[379], X[27], Y[11]);
and (C[380], X[28], Y[11]);
and (C[381], X[29], Y[11]);
and (C[382], X[30], Y[11]);
and (C[383], X[31], Y[11]);
//PP12
and (C[384], X[0], Y[12]);
and (C[385], X[1], Y[12]);
and (C[386], X[2], Y[12]);
and (C[387], X[3], Y[12]);
and (C[388], X[4], Y[12]);
and (C[389], X[5], Y[12]);
and (C[390], X[6], Y[12]);
and (C[391], X[7], Y[12]);
and (C[392], X[8], Y[12]);
and (C[393], X[9], Y[12]);
and (C[394], X[10], Y[12]);
and (C[395], X[11], Y[12]);
and (C[396], X[12], Y[12]);
and (C[397], X[13], Y[12]);
and (C[398], X[14], Y[12]);
and (C[399], X[15], Y[12]);
and (C[400], X[16], Y[12]);
and (C[401], X[17], Y[12]);
and (C[402], X[18], Y[12]);
and (C[403], X[19], Y[12]);
and (C[404], X[20], Y[12]);
and (C[405], X[21], Y[12]);
and (C[406], X[22], Y[12]);
and (C[407], X[23], Y[12]);
and (C[408], X[24], Y[12]);
and (C[409], X[25], Y[12]);
and (C[410], X[26], Y[12]);
and (C[411], X[27], Y[12]);
and (C[412], X[28], Y[12]);
and (C[413], X[29], Y[12]);
and (C[414], X[30], Y[12]);
and (C[415], X[31], Y[12]);
//PP13
and (C[416], X[0], Y[13]);
and (C[417], X[1], Y[13]);
and (C[418], X[2], Y[13]);
and (C[419], X[3], Y[13]);
and (C[420], X[4], Y[13]);
and (C[421], X[5], Y[13]);
and (C[422], X[6], Y[13]);
and (C[423], X[7], Y[13]);
and (C[424], X[8], Y[13]);
and (C[425], X[9], Y[13]);
and (C[426], X[10], Y[13]);
and (C[427], X[11], Y[13]);
and (C[428], X[12], Y[13]);
and (C[429], X[13], Y[13]);
and (C[430], X[14], Y[13]);
and (C[431], X[15], Y[13]);
and (C[432], X[16], Y[13]);
and (C[433], X[17], Y[13]);
and (C[434], X[18], Y[13]);
and (C[435], X[19], Y[13]);
and (C[436], X[20], Y[13]);
and (C[437], X[21], Y[13]);
and (C[438], X[22], Y[13]);
and (C[439], X[23], Y[13]);
and (C[440], X[24], Y[13]);
and (C[441], X[25], Y[13]);
and (C[442], X[26], Y[13]);
and (C[443], X[27], Y[13]);
and (C[444], X[28], Y[13]);
and (C[445], X[29], Y[13]);
and (C[446], X[30], Y[13]);
and (C[447], X[31], Y[13]);
//PP14
and (C[448], X[0], Y[14]);
and (C[449], X[1], Y[14]);
and (C[450], X[2], Y[14]);
and (C[451], X[3], Y[14]);
and (C[452], X[4], Y[14]);
and (C[453], X[5], Y[14]);
and (C[454], X[6], Y[14]);
and (C[455], X[7], Y[14]);
and (C[456], X[8], Y[14]);
and (C[457], X[9], Y[14]);
and (C[458], X[10], Y[14]);
and (C[459], X[11], Y[14]);
and (C[460], X[12], Y[14]);
and (C[461], X[13], Y[14]);
and (C[462], X[14], Y[14]);
and (C[463], X[15], Y[14]);
and (C[464], X[16], Y[14]);
and (C[465], X[17], Y[14]);
and (C[466], X[18], Y[14]);
and (C[467], X[19], Y[14]);
and (C[468], X[20], Y[14]);
and (C[469], X[21], Y[14]);
and (C[470], X[22], Y[14]);
and (C[471], X[23], Y[14]);
and (C[472], X[24], Y[14]);
and (C[473], X[25], Y[14]);
and (C[474], X[26], Y[14]);
and (C[475], X[27], Y[14]);
and (C[476], X[28], Y[14]);
and (C[477], X[29], Y[14]);
and (C[478], X[30], Y[14]);
and (C[479], X[31], Y[14]);
//PP15
and (C[480], X[0], Y[15]);
and (C[481], X[1], Y[15]);
and (C[482], X[2], Y[15]);
and (C[483], X[3], Y[15]);
and (C[484], X[4], Y[15]);
and (C[485], X[5], Y[15]);
and (C[486], X[6], Y[15]);
and (C[487], X[7], Y[15]);
and (C[488], X[8], Y[15]);
and (C[489], X[9], Y[15]);
and (C[490], X[10], Y[15]);
and (C[491], X[11], Y[15]);
and (C[492], X[12], Y[15]);
and (C[493], X[13], Y[15]);
and (C[494], X[14], Y[15]);
and (C[495], X[15], Y[15]);
and (C[496], X[16], Y[15]);
and (C[497], X[17], Y[15]);
and (C[498], X[18], Y[15]);
and (C[499], X[19], Y[15]);
and (C[500], X[20], Y[15]);
and (C[501], X[21], Y[15]);
and (C[502], X[22], Y[15]);
and (C[503], X[23], Y[15]);
and (C[504], X[24], Y[15]);
and (C[505], X[25], Y[15]);
and (C[506], X[26], Y[15]);
and (C[507], X[27], Y[15]);
and (C[508], X[28], Y[15]);
and (C[509], X[29], Y[15]);
and (C[510], X[30], Y[15]);
and (C[511], X[31], Y[15]);
//PP16
and (C[512], X[0], Y[16]);
and (C[513], X[1], Y[16]);
and (C[514], X[2], Y[16]);
and (C[515], X[3], Y[16]);
and (C[516], X[4], Y[16]);
and (C[517], X[5], Y[16]);
and (C[518], X[6], Y[16]);
and (C[519], X[7], Y[16]);
and (C[520], X[8], Y[16]);
and (C[521], X[9], Y[16]);
and (C[522], X[10], Y[16]);
and (C[523], X[11], Y[16]);
and (C[524], X[12], Y[16]);
and (C[525], X[13], Y[16]);
and (C[526], X[14], Y[16]);
and (C[527], X[15], Y[16]);
and (C[528], X[16], Y[16]);
and (C[529], X[17], Y[16]);
and (C[530], X[18], Y[16]);
and (C[531], X[19], Y[16]);
and (C[532], X[20], Y[16]);
and (C[533], X[21], Y[16]);
and (C[534], X[22], Y[16]);
and (C[535], X[23], Y[16]);
and (C[536], X[24], Y[16]);
and (C[537], X[25], Y[16]);
and (C[538], X[26], Y[16]);
and (C[539], X[27], Y[16]);
and (C[540], X[28], Y[16]);
and (C[541], X[29], Y[16]);
and (C[542], X[30], Y[16]);
and (C[543], X[31], Y[16]);
//PP17
and (C[544], X[0], Y[17]);
and (C[545], X[1], Y[17]);
and (C[546], X[2], Y[17]);
and (C[547], X[3], Y[17]);
and (C[548], X[4], Y[17]);
and (C[549], X[5], Y[17]);
and (C[550], X[6], Y[17]);
and (C[551], X[7], Y[17]);
and (C[552], X[8], Y[17]);
and (C[553], X[9], Y[17]);
and (C[554], X[10], Y[17]);
and (C[555], X[11], Y[17]);
and (C[556], X[12], Y[17]);
and (C[557], X[13], Y[17]);
and (C[558], X[14], Y[17]);
and (C[559], X[15], Y[17]);
and (C[560], X[16], Y[17]);
and (C[561], X[17], Y[17]);
and (C[562], X[18], Y[17]);
and (C[563], X[19], Y[17]);
and (C[564], X[20], Y[17]);
and (C[565], X[21], Y[17]);
and (C[566], X[22], Y[17]);
and (C[567], X[23], Y[17]);
and (C[568], X[24], Y[17]);
and (C[569], X[25], Y[17]);
and (C[570], X[26], Y[17]);
and (C[571], X[27], Y[17]);
and (C[572], X[28], Y[17]);
and (C[573], X[29], Y[17]);
and (C[574], X[30], Y[17]);
and (C[575], X[31], Y[17]);
//PP18
and (C[576], X[0], Y[18]);
and (C[577], X[1], Y[18]);
and (C[578], X[2], Y[18]);
and (C[579], X[3], Y[18]);
and (C[580], X[4], Y[18]);
and (C[581], X[5], Y[18]);
and (C[582], X[6], Y[18]);
and (C[583], X[7], Y[18]);
and (C[584], X[8], Y[18]);
and (C[585], X[9], Y[18]);
and (C[586], X[10], Y[18]);
and (C[587], X[11], Y[18]);
and (C[588], X[12], Y[18]);
and (C[589], X[13], Y[18]);
and (C[590], X[14], Y[18]);
and (C[591], X[15], Y[18]);
and (C[592], X[16], Y[18]);
and (C[593], X[17], Y[18]);
and (C[594], X[18], Y[18]);
and (C[595], X[19], Y[18]);
and (C[596], X[20], Y[18]);
and (C[597], X[21], Y[18]);
and (C[598], X[22], Y[18]);
and (C[599], X[23], Y[18]);
and (C[600], X[24], Y[18]);
and (C[601], X[25], Y[18]);
and (C[602], X[26], Y[18]);
and (C[603], X[27], Y[18]);
and (C[604], X[28], Y[18]);
and (C[605], X[29], Y[18]);
and (C[606], X[30], Y[18]);
and (C[607], X[31], Y[18]);
//PP19
and (C[608], X[0], Y[19]);
and (C[609], X[1], Y[19]);
and (C[610], X[2], Y[19]);
and (C[611], X[3], Y[19]);
and (C[612], X[4], Y[19]);
and (C[613], X[5], Y[19]);
and (C[614], X[6], Y[19]);
and (C[615], X[7], Y[19]);
and (C[616], X[8], Y[19]);
and (C[617], X[9], Y[19]);
and (C[618], X[10], Y[19]);
and (C[619], X[11], Y[19]);
and (C[620], X[12], Y[19]);
and (C[621], X[13], Y[19]);
and (C[622], X[14], Y[19]);
and (C[623], X[15], Y[19]);
and (C[624], X[16], Y[19]);
and (C[625], X[17], Y[19]);
and (C[626], X[18], Y[19]);
and (C[627], X[19], Y[19]);
and (C[628], X[20], Y[19]);
and (C[629], X[21], Y[19]);
and (C[630], X[22], Y[19]);
and (C[631], X[23], Y[19]);
and (C[632], X[24], Y[19]);
and (C[633], X[25], Y[19]);
and (C[634], X[26], Y[19]);
and (C[635], X[27], Y[19]);
and (C[636], X[28], Y[19]);
and (C[637], X[29], Y[19]);
and (C[638], X[30], Y[19]);
and (C[639], X[31], Y[19]);
//PP20
and (C[640], X[0], Y[20]);
and (C[641], X[1], Y[20]);
and (C[642], X[2], Y[20]);
and (C[643], X[3], Y[20]);
and (C[644], X[4], Y[20]);
and (C[645], X[5], Y[20]);
and (C[646], X[6], Y[20]);
and (C[647], X[7], Y[20]);
and (C[648], X[8], Y[20]);
and (C[649], X[9], Y[20]);
and (C[650], X[10], Y[20]);
and (C[651], X[11], Y[20]);
and (C[652], X[12], Y[20]);
and (C[653], X[13], Y[20]);
and (C[654], X[14], Y[20]);
and (C[655], X[15], Y[20]);
and (C[656], X[16], Y[20]);
and (C[657], X[17], Y[20]);
and (C[658], X[18], Y[20]);
and (C[659], X[19], Y[20]);
and (C[660], X[20], Y[20]);
and (C[661], X[21], Y[20]);
and (C[662], X[22], Y[20]);
and (C[663], X[23], Y[20]);
and (C[664], X[24], Y[20]);
and (C[665], X[25], Y[20]);
and (C[666], X[26], Y[20]);
and (C[667], X[27], Y[20]);
and (C[668], X[28], Y[20]);
and (C[669], X[29], Y[20]);
and (C[670], X[30], Y[20]);
and (C[671], X[31], Y[20]);
//PP21
and (C[672], X[0], Y[21]);
and (C[673], X[1], Y[21]);
and (C[674], X[2], Y[21]);
and (C[675], X[3], Y[21]);
and (C[676], X[4], Y[21]);
and (C[677], X[5], Y[21]);
and (C[678], X[6], Y[21]);
and (C[679], X[7], Y[21]);
and (C[680], X[8], Y[21]);
and (C[681], X[9], Y[21]);
and (C[682], X[10], Y[21]);
and (C[683], X[11], Y[21]);
and (C[684], X[12], Y[21]);
and (C[685], X[13], Y[21]);
and (C[686], X[14], Y[21]);
and (C[687], X[15], Y[21]);
and (C[688], X[16], Y[21]);
and (C[689], X[17], Y[21]);
and (C[690], X[18], Y[21]);
and (C[691], X[19], Y[21]);
and (C[692], X[20], Y[21]);
and (C[693], X[21], Y[21]);
and (C[694], X[22], Y[21]);
and (C[695], X[23], Y[21]);
and (C[696], X[24], Y[21]);
and (C[697], X[25], Y[21]);
and (C[698], X[26], Y[21]);
and (C[699], X[27], Y[21]);
and (C[700], X[28], Y[21]);
and (C[701], X[29], Y[21]);
and (C[702], X[30], Y[21]);
and (C[703], X[31], Y[21]);
//PP22
and (C[704], X[0], Y[22]);
and (C[705], X[1], Y[22]);
and (C[706], X[2], Y[22]);
and (C[707], X[3], Y[22]);
and (C[708], X[4], Y[22]);
and (C[709], X[5], Y[22]);
and (C[710], X[6], Y[22]);
and (C[711], X[7], Y[22]);
and (C[712], X[8], Y[22]);
and (C[713], X[9], Y[22]);
and (C[714], X[10], Y[22]);
and (C[715], X[11], Y[22]);
and (C[716], X[12], Y[22]);
and (C[717], X[13], Y[22]);
and (C[718], X[14], Y[22]);
and (C[719], X[15], Y[22]);
and (C[720], X[16], Y[22]);
and (C[721], X[17], Y[22]);
and (C[722], X[18], Y[22]);
and (C[723], X[19], Y[22]);
and (C[724], X[20], Y[22]);
and (C[725], X[21], Y[22]);
and (C[726], X[22], Y[22]);
and (C[727], X[23], Y[22]);
and (C[728], X[24], Y[22]);
and (C[729], X[25], Y[22]);
and (C[730], X[26], Y[22]);
and (C[731], X[27], Y[22]);
and (C[732], X[28], Y[22]);
and (C[733], X[29], Y[22]);
and (C[734], X[30], Y[22]);
and (C[735], X[31], Y[22]);
//PP23
and (C[736], X[0], Y[23]);
and (C[737], X[1], Y[23]);
and (C[738], X[2], Y[23]);
and (C[739], X[3], Y[23]);
and (C[740], X[4], Y[23]);
and (C[741], X[5], Y[23]);
and (C[742], X[6], Y[23]);
and (C[743], X[7], Y[23]);
and (C[744], X[8], Y[23]);
and (C[745], X[9], Y[23]);
and (C[746], X[10], Y[23]);
and (C[747], X[11], Y[23]);
and (C[748], X[12], Y[23]);
and (C[749], X[13], Y[23]);
and (C[750], X[14], Y[23]);
and (C[751], X[15], Y[23]);
and (C[752], X[16], Y[23]);
and (C[753], X[17], Y[23]);
and (C[754], X[18], Y[23]);
and (C[755], X[19], Y[23]);
and (C[756], X[20], Y[23]);
and (C[757], X[21], Y[23]);
and (C[758], X[22], Y[23]);
and (C[759], X[23], Y[23]);
and (C[760], X[24], Y[23]);
and (C[761], X[25], Y[23]);
and (C[762], X[26], Y[23]);
and (C[763], X[27], Y[23]);
and (C[764], X[28], Y[23]);
and (C[765], X[29], Y[23]);
and (C[766], X[30], Y[23]);
and (C[767], X[31], Y[23]);
//PP24
and (C[768], X[0], Y[24]);
and (C[769], X[1], Y[24]);
and (C[770], X[2], Y[24]);
and (C[771], X[3], Y[24]);
and (C[772], X[4], Y[24]);
and (C[773], X[5], Y[24]);
and (C[774], X[6], Y[24]);
and (C[775], X[7], Y[24]);
and (C[776], X[8], Y[24]);
and (C[777], X[9], Y[24]);
and (C[778], X[10], Y[24]);
and (C[779], X[11], Y[24]);
and (C[780], X[12], Y[24]);
and (C[781], X[13], Y[24]);
and (C[782], X[14], Y[24]);
and (C[783], X[15], Y[24]);
and (C[784], X[16], Y[24]);
and (C[785], X[17], Y[24]);
and (C[786], X[18], Y[24]);
and (C[787], X[19], Y[24]);
and (C[788], X[20], Y[24]);
and (C[789], X[21], Y[24]);
and (C[790], X[22], Y[24]);
and (C[791], X[23], Y[24]);
and (C[792], X[24], Y[24]);
and (C[793], X[25], Y[24]);
and (C[794], X[26], Y[24]);
and (C[795], X[27], Y[24]);
and (C[796], X[28], Y[24]);
and (C[797], X[29], Y[24]);
and (C[798], X[30], Y[24]);
and (C[799], X[31], Y[24]);
//PP25
and (C[800], X[0], Y[25]);
and (C[801], X[1], Y[25]);
and (C[802], X[2], Y[25]);
and (C[803], X[3], Y[25]);
and (C[804], X[4], Y[25]);
and (C[805], X[5], Y[25]);
and (C[806], X[6], Y[25]);
and (C[807], X[7], Y[25]);
and (C[808], X[8], Y[25]);
and (C[809], X[9], Y[25]);
and (C[810], X[10], Y[25]);
and (C[811], X[11], Y[25]);
and (C[812], X[12], Y[25]);
and (C[813], X[13], Y[25]);
and (C[814], X[14], Y[25]);
and (C[815], X[15], Y[25]);
and (C[816], X[16], Y[25]);
and (C[817], X[17], Y[25]);
and (C[818], X[18], Y[25]);
and (C[819], X[19], Y[25]);
and (C[820], X[20], Y[25]);
and (C[821], X[21], Y[25]);
and (C[822], X[22], Y[25]);
and (C[823], X[23], Y[25]);
and (C[824], X[24], Y[25]);
and (C[825], X[25], Y[25]);
and (C[826], X[26], Y[25]);
and (C[827], X[27], Y[25]);
and (C[828], X[28], Y[25]);
and (C[829], X[29], Y[25]);
and (C[830], X[30], Y[25]);
and (C[831], X[31], Y[25]);
//PP26
and (C[832], X[0], Y[26]);
and (C[833], X[1], Y[26]);
and (C[834], X[2], Y[26]);
and (C[835], X[3], Y[26]);
and (C[836], X[4], Y[26]);
and (C[837], X[5], Y[26]);
and (C[838], X[6], Y[26]);
and (C[839], X[7], Y[26]);
and (C[840], X[8], Y[26]);
and (C[841], X[9], Y[26]);
and (C[842], X[10], Y[26]);
and (C[843], X[11], Y[26]);
and (C[844], X[12], Y[26]);
and (C[845], X[13], Y[26]);
and (C[846], X[14], Y[26]);
and (C[847], X[15], Y[26]);
and (C[848], X[16], Y[26]);
and (C[849], X[17], Y[26]);
and (C[850], X[18], Y[26]);
and (C[851], X[19], Y[26]);
and (C[852], X[20], Y[26]);
and (C[853], X[21], Y[26]);
and (C[854], X[22], Y[26]);
and (C[855], X[23], Y[26]);
and (C[856], X[24], Y[26]);
and (C[857], X[25], Y[26]);
and (C[858], X[26], Y[26]);
and (C[859], X[27], Y[26]);
and (C[860], X[28], Y[26]);
and (C[861], X[29], Y[26]);
and (C[862], X[30], Y[26]);
and (C[863], X[31], Y[26]);
//PP27
and (C[864], X[0], Y[27]);
and (C[865], X[1], Y[27]);
and (C[866], X[2], Y[27]);
and (C[867], X[3], Y[27]);
and (C[868], X[4], Y[27]);
and (C[869], X[5], Y[27]);
and (C[870], X[6], Y[27]);
and (C[871], X[7], Y[27]);
and (C[872], X[8], Y[27]);
and (C[873], X[9], Y[27]);
and (C[874], X[10], Y[27]);
and (C[875], X[11], Y[27]);
and (C[876], X[12], Y[27]);
and (C[877], X[13], Y[27]);
and (C[878], X[14], Y[27]);
and (C[879], X[15], Y[27]);
and (C[880], X[16], Y[27]);
and (C[881], X[17], Y[27]);
and (C[882], X[18], Y[27]);
and (C[883], X[19], Y[27]);
and (C[884], X[20], Y[27]);
and (C[885], X[21], Y[27]);
and (C[886], X[22], Y[27]);
and (C[887], X[23], Y[27]);
and (C[888], X[24], Y[27]);
and (C[889], X[25], Y[27]);
and (C[890], X[26], Y[27]);
and (C[891], X[27], Y[27]);
and (C[892], X[28], Y[27]);
and (C[893], X[29], Y[27]);
and (C[894], X[30], Y[27]);
and (C[895], X[31], Y[27]);
//PP28
and (C[896], X[0], Y[28]);
and (C[897], X[1], Y[28]);
and (C[898], X[2], Y[28]);
and (C[899], X[3], Y[28]);
and (C[900], X[4], Y[28]);
and (C[901], X[5], Y[28]);
and (C[902], X[6], Y[28]);
and (C[903], X[7], Y[28]);
and (C[904], X[8], Y[28]);
and (C[905], X[9], Y[28]);
and (C[906], X[10], Y[28]);
and (C[907], X[11], Y[28]);
and (C[908], X[12], Y[28]);
and (C[909], X[13], Y[28]);
and (C[910], X[14], Y[28]);
and (C[911], X[15], Y[28]);
and (C[912], X[16], Y[28]);
and (C[913], X[17], Y[28]);
and (C[914], X[18], Y[28]);
and (C[915], X[19], Y[28]);
and (C[916], X[20], Y[28]);
and (C[917], X[21], Y[28]);
and (C[918], X[22], Y[28]);
and (C[919], X[23], Y[28]);
and (C[920], X[24], Y[28]);
and (C[921], X[25], Y[28]);
and (C[922], X[26], Y[28]);
and (C[923], X[27], Y[28]);
and (C[924], X[28], Y[28]);
and (C[925], X[29], Y[28]);
and (C[926], X[30], Y[28]);
and (C[927], X[31], Y[28]);
//PP29
and (C[928], X[0], Y[29]);
and (C[929], X[1], Y[29]);
and (C[930], X[2], Y[29]);
and (C[931], X[3], Y[29]);
and (C[932], X[4], Y[29]);
and (C[933], X[5], Y[29]);
and (C[934], X[6], Y[29]);
and (C[935], X[7], Y[29]);
and (C[936], X[8], Y[29]);
and (C[937], X[9], Y[29]);
and (C[938], X[10], Y[29]);
and (C[939], X[11], Y[29]);
and (C[940], X[12], Y[29]);
and (C[941], X[13], Y[29]);
and (C[942], X[14], Y[29]);
and (C[943], X[15], Y[29]);
and (C[944], X[16], Y[29]);
and (C[945], X[17], Y[29]);
and (C[946], X[18], Y[29]);
and (C[947], X[19], Y[29]);
and (C[948], X[20], Y[29]);
and (C[949], X[21], Y[29]);
and (C[950], X[22], Y[29]);
and (C[951], X[23], Y[29]);
and (C[952], X[24], Y[29]);
and (C[953], X[25], Y[29]);
and (C[954], X[26], Y[29]);
and (C[955], X[27], Y[29]);
and (C[956], X[28], Y[29]);
and (C[957], X[29], Y[29]);
and (C[958], X[30], Y[29]);
and (C[959], X[31], Y[29]);
//PP30
and (C[960], X[0], Y[30]);
and (C[961], X[1], Y[30]);
and (C[962], X[2], Y[30]);
and (C[963], X[3], Y[30]);
and (C[964], X[4], Y[30]);
and (C[965], X[5], Y[30]);
and (C[966], X[6], Y[30]);
and (C[967], X[7], Y[30]);
and (C[968], X[8], Y[30]);
and (C[969], X[9], Y[30]);
and (C[970], X[10], Y[30]);
and (C[971], X[11], Y[30]);
and (C[972], X[12], Y[30]);
and (C[973], X[13], Y[30]);
and (C[974], X[14], Y[30]);
and (C[975], X[15], Y[30]);
and (C[976], X[16], Y[30]);
and (C[977], X[17], Y[30]);
and (C[978], X[18], Y[30]);
and (C[979], X[19], Y[30]);
and (C[980], X[20], Y[30]);
and (C[981], X[21], Y[30]);
and (C[982], X[22], Y[30]);
and (C[983], X[23], Y[30]);
and (C[984], X[24], Y[30]);
and (C[985], X[25], Y[30]);
and (C[986], X[26], Y[30]);
and (C[987], X[27], Y[30]);
and (C[988], X[28], Y[30]);
and (C[989], X[29], Y[30]);
and (C[990], X[30], Y[30]);
and (C[991], X[31], Y[30]);
//PP31
and (C[992], X[0], Y[31]);
and (C[993], X[1], Y[31]);
and (C[994], X[2], Y[31]);
and (C[995], X[3], Y[31]);
and (C[996], X[4], Y[31]);
and (C[997], X[5], Y[31]);
and (C[998], X[6], Y[31]);
and (C[999], X[7], Y[31]);
and (C[1000], X[8], Y[31]);
and (C[1001], X[9], Y[31]);
and (C[1002], X[10], Y[31]);
and (C[1003], X[11], Y[31]);
and (C[1004], X[12], Y[31]);
and (C[1005], X[13], Y[31]);
and (C[1006], X[14], Y[31]);
and (C[1007], X[15], Y[31]);
and (C[1008], X[16], Y[31]);
and (C[1009], X[17], Y[31]);
and (C[1010], X[18], Y[31]);
and (C[1011], X[19], Y[31]);
and (C[1012], X[20], Y[31]);
and (C[1013], X[21], Y[31]);
and (C[1014], X[22], Y[31]);
and (C[1015], X[23], Y[31]);
and (C[1016], X[24], Y[31]);
and (C[1017], X[25], Y[31]);
and (C[1018], X[26], Y[31]);
and (C[1019], X[27], Y[31]);
and (C[1020], X[28], Y[31]);
and (C[1021], X[29], Y[31]);
and (C[1022], X[30], Y[31]);
and (C[1023], X[31], Y[31]);
//pp0,1,2
fulladd full00(sum[0], carry[0], C[0], 1'b0, 1'b0);
fulladd full01(sum[1], carry[1], C[1], C[32], 1'b0);
fulladd full02 (sum[2], carry[2], C[2], C[33], C[64] );
fulladd full03 (sum[3], carry[3], C[3], C[34], C[65] );
fulladd full04 (sum[4], carry[4], C[4], C[35], C[66] );
fulladd full05 (sum[5], carry[5], C[5], C[36], C[67] );
fulladd full06 (sum[6], carry[6], C[6], C[37], C[68] );
fulladd full07 (sum[7], carry[7], C[7], C[38], C[69] );
fulladd full08 (sum[8], carry[8], C[8], C[39], C[70] );
fulladd full09 (sum[9], carry[9], C[9], C[40], C[71] );
fulladd full010 (sum[10], carry[10], C[10], C[41], C[72] );
fulladd full011 (sum[11], carry[11], C[11], C[42], C[73] );
fulladd full012 (sum[12], carry[12], C[12], C[43], C[74] );
fulladd full013 (sum[13], carry[13], C[13], C[44], C[75] );
fulladd full014 (sum[14], carry[14], C[14], C[45], C[76] );
fulladd full015 (sum[15], carry[15], C[15], C[46], C[77] );
fulladd full016 (sum[16], carry[16], C[16], C[47], C[78] );
fulladd full017 (sum[17], carry[17], C[17], C[48], C[79] );
fulladd full018 (sum[18], carry[18], C[18], C[49], C[80] );
fulladd full019 (sum[19], carry[19], C[19], C[50], C[81] );
fulladd full020 (sum[20], carry[20], C[20], C[51], C[82] );
fulladd full021 (sum[21], carry[21], C[21], C[52], C[83] );
fulladd full022 (sum[22], carry[22], C[22], C[53], C[84] );
fulladd full023 (sum[23], carry[23], C[23], C[54], C[85] );
fulladd full024 (sum[24], carry[24], C[24], C[55], C[86] );
fulladd full025 (sum[25], carry[25], C[25], C[56], C[87] );
fulladd full026 (sum[26], carry[26], C[26], C[57], C[88] );
fulladd full027 (sum[27], carry[27], C[27], C[58], C[89] );
fulladd full028 (sum[28], carry[28], C[28], C[59], C[90] );
fulladd full029 (sum[29], carry[29], C[29], C[60], C[91] );
fulladd full030 (sum[30], carry[30], C[30], C[61], C[92] );
fulladd full031 (sum[31], carry[31], C[31], C[62], C[93] );
fulladd full032 (sum[32], carry[32], 1'b0, C[63], C[94] );
fulladd full033 (sum[33], carry[33], 1'b0, 1'b0, C[95] );
fulladd full034 (sum[34], carry[34], 1'b0, 1'b0, 1'b0 );
fulladd full035 (sum[35], carry[35], 1'b0, 1'b0, 1'b0 );
fulladd full036 (sum[36], carry[36], 1'b0, 1'b0, 1'b0 );
fulladd full037 (sum[37], carry[37], 1'b0, 1'b0, 1'b0 );
fulladd full038 (sum[38], carry[38], 1'b0, 1'b0, 1'b0 );
fulladd full039 (sum[39], carry[39], 1'b0, 1'b0, 1'b0 );
fulladd full040 (sum[40], carry[40], 1'b0, 1'b0, 1'b0 );
fulladd full041 (sum[41], carry[41], 1'b0, 1'b0, 1'b0 );
fulladd full042 (sum[42], carry[42], 1'b0, 1'b0, 1'b0 );
fulladd full043 (sum[43], carry[43], 1'b0, 1'b0, 1'b0 );
fulladd full044 (sum[44], carry[44], 1'b0, 1'b0, 1'b0 );
fulladd full045 (sum[45], carry[45], 1'b0, 1'b0, 1'b0 );
fulladd full046 (sum[46], carry[46], 1'b0, 1'b0, 1'b0 );
fulladd full047 (sum[47], carry[47], 1'b0, 1'b0, 1'b0 );
fulladd full048 (sum[48], carry[48], 1'b0, 1'b0, 1'b0 );
fulladd full049 (sum[49], carry[49], 1'b0, 1'b0, 1'b0 );
fulladd full050 (sum[50], carry[50], 1'b0, 1'b0, 1'b0 );
fulladd full051 (sum[51], carry[51], 1'b0, 1'b0, 1'b0 );
fulladd full052 (sum[52], carry[52], 1'b0, 1'b0, 1'b0 );
fulladd full053 (sum[53], carry[53], 1'b0, 1'b0, 1'b0 );
fulladd full054 (sum[54], carry[54], 1'b0, 1'b0, 1'b0 );
fulladd full055 (sum[55], carry[55], 1'b0, 1'b0, 1'b0 );
fulladd full056 (sum[56], carry[56], 1'b0, 1'b0, 1'b0 );
fulladd full057 (sum[57], carry[57], 1'b0, 1'b0, 1'b0 );
fulladd full058 (sum[58], carry[58], 1'b0, 1'b0, 1'b0 );
fulladd full059 (sum[59], carry[59], 1'b0, 1'b0, 1'b0 );
fulladd full060 (sum[60], carry[60], 1'b0, 1'b0, 1'b0 );
fulladd full061 (sum[61], carry[61], 1'b0, 1'b0, 1'b0 );
fulladd full062 (sum[62], carry[62], 1'b0, 1'b0, 1'b0 );
fulladd full063 (sum[63], carry[63], 1'b0, 1'b0, 1'b0 );
//pp3,4,5
fulladd full10(sum[64], carry[64], 1'b0, 1'b0, 1'b0);
fulladd full11(sum[65], carry[65], 1'b0, 1'b0, 1'b0);
fulladd full12(sum[66], carry[66], 1'b0, 1'b0, 1'b0);
fulladd full13(sum[67], carry[67], C[96], 1'b0, 1'b0);
fulladd full14(sum[68], carry[68], C[97], C[128], 1'b0);
fulladd full15 (sum[69], carry[69], C[98], C[129], C[160]);
fulladd full16 (sum[70], carry[70], C[99], C[130], C[161]);
fulladd full17 (sum[71], carry[71], C[100], C[131], C[162]);
fulladd full18 (sum[72], carry[72], C[101], C[132], C[163]);
fulladd full19 (sum[73], carry[73], C[102], C[133], C[164]);
fulladd full110 (sum[74], carry[74], C[103], C[134], C[165]);
fulladd full111 (sum[75], carry[75], C[104], C[135], C[166]);
fulladd full112 (sum[76], carry[76], C[105], C[136], C[167]);
fulladd full113 (sum[77], carry[77], C[106], C[137], C[168]);
fulladd full114 (sum[78], carry[78], C[107], C[138], C[169]);
fulladd full115 (sum[79], carry[79], C[108], C[139], C[170]);
fulladd full116 (sum[80], carry[80], C[109], C[140], C[171]);
fulladd full117 (sum[81], carry[81], C[110], C[141], C[172]);
fulladd full118 (sum[82], carry[82], C[111], C[142], C[173]);
fulladd full119 (sum[83], carry[83], C[112], C[143], C[174]);
fulladd full120 (sum[84], carry[84], C[113], C[144], C[175]);
fulladd full121 (sum[85], carry[85], C[114], C[145], C[176]);
fulladd full122 (sum[86], carry[86], C[115], C[146], C[177]);
fulladd full123 (sum[87], carry[87], C[116], C[147], C[178]);
fulladd full124 (sum[88], carry[88], C[117], C[148], C[179]);
fulladd full125 (sum[89], carry[89], C[118], C[149], C[180]);
fulladd full126 (sum[90], carry[90], C[119], C[150], C[181]);
fulladd full127 (sum[91], carry[91], C[120], C[151], C[182]);
fulladd full128 (sum[92], carry[92], C[121], C[152], C[183]);
fulladd full129 (sum[93], carry[93], C[122], C[153], C[184]);
fulladd full130 (sum[94], carry[94], C[123], C[154], C[185]);
fulladd full131 (sum[95], carry[95], C[124], C[155], C[186]);
fulladd full132 (sum[96], carry[96], C[125], C[156], C[187]);
fulladd full133 (sum[97], carry[97], C[126], C[157], C[188]);
fulladd full134 (sum[98], carry[98], C[127], C[158], C[189]);
fulladd full135 (sum[99], carry[99], 1'b0, C[159], C[190]);
fulladd full136 (sum[100], carry[100], 1'b0, 1'b0, C[191]);
fulladd full137 (sum[101], carry[101], 1'b0, 1'b0, 1'b0);
fulladd full138 (sum[102], carry[102], 1'b0, 1'b0, 1'b0);
fulladd full139 (sum[103], carry[103], 1'b0, 1'b0, 1'b0);
fulladd full140 (sum[104], carry[104], 1'b0, 1'b0, 1'b0);
fulladd full141 (sum[105], carry[105], 1'b0, 1'b0, 1'b0);
fulladd full142 (sum[106], carry[106], 1'b0, 1'b0, 1'b0);
fulladd full143 (sum[107], carry[107], 1'b0, 1'b0, 1'b0);
fulladd full144 (sum[108], carry[108], 1'b0, 1'b0, 1'b0);
fulladd full145 (sum[109], carry[109], 1'b0, 1'b0, 1'b0);
fulladd full146 (sum[110], carry[110], 1'b0, 1'b0, 1'b0);
fulladd full147 (sum[111], carry[111], 1'b0, 1'b0, 1'b0);
fulladd full148 (sum[112], carry[112], 1'b0, 1'b0, 1'b0);
fulladd full149 (sum[113], carry[113], 1'b0, 1'b0, 1'b0);
fulladd full150 (sum[114], carry[114], 1'b0, 1'b0, 1'b0);
fulladd full151 (sum[115], carry[115], 1'b0, 1'b0, 1'b0);
fulladd full152 (sum[116], carry[116], 1'b0, 1'b0, 1'b0);
fulladd full153 (sum[117], carry[117], 1'b0, 1'b0, 1'b0);
fulladd full154 (sum[118], carry[118], 1'b0, 1'b0, 1'b0);
fulladd full155 (sum[119], carry[119], 1'b0, 1'b0, 1'b0);
fulladd full156 (sum[120], carry[120], 1'b0, 1'b0, 1'b0);
fulladd full157 (sum[121], carry[121], 1'b0, 1'b0, 1'b0);
fulladd full158 (sum[122], carry[122], 1'b0, 1'b0, 1'b0);
fulladd full159 (sum[123], carry[123], 1'b0, 1'b0, 1'b0);
fulladd full160 (sum[124], carry[124], 1'b0, 1'b0, 1'b0);
fulladd full161 (sum[125], carry[125], 1'b0, 1'b0, 1'b0);
fulladd full162 (sum[126], carry[126], 1'b0, 1'b0, 1'b0);
fulladd full163 (sum[127], carry[127], 1'b0, 1'b0, 1'b0);
//pp6,7,8
fulladd full20 (sum[128], carry[128], 1'b0, 1'b0, 1'b0);
fulladd full21 (sum[129], carry[129], 1'b0, 1'b0, 1'b0);
fulladd full22 (sum[130], carry[130], 1'b0, 1'b0, 1'b0);
fulladd full23 (sum[131], carry[131], 1'b0, 1'b0, 1'b0);
fulladd full24 (sum[132], carry[132], 1'b0, 1'b0, 1'b0);
fulladd full25 (sum[133], carry[133], 1'b0, 1'b0, 1'b0);
fulladd full26 (sum[134], carry[134], C[192], 1'b0, 1'b0);
fulladd full27 (sum[135], carry[135], C[193], C[224], 1'b0);
fulladd full28 (sum[136], carry[136], C[194], C[225], C[256]);
fulladd full29 (sum[137], carry[137], C[195], C[226], C[257]);
fulladd full210 (sum[138], carry[138], C[196], C[227], C[258]);
fulladd full211 (sum[139], carry[139], C[197], C[228], C[259]);
fulladd full212 (sum[140], carry[140], C[198], C[229], C[260]);
fulladd full213 (sum[141], carry[141], C[199], C[230], C[261]);
fulladd full214 (sum[142], carry[142], C[200], C[231], C[262]);
fulladd full215 (sum[143], carry[143], C[201], C[232], C[263]);
fulladd full216 (sum[144], carry[144], C[202], C[233], C[264]);
fulladd full217 (sum[145], carry[145], C[203], C[234], C[265]);
fulladd full218 (sum[146], carry[146], C[204], C[235], C[266]);
fulladd full219 (sum[147], carry[147], C[205], C[236], C[267]);
fulladd full220 (sum[148], carry[148], C[206], C[237], C[268]);
fulladd full221 (sum[149], carry[149], C[207], C[238], C[269]);
fulladd full222 (sum[150], carry[150], C[208], C[239], C[270]);
fulladd full223 (sum[151], carry[151], C[209], C[240], C[271]);
fulladd full224 (sum[152], carry[152], C[210], C[241], C[272]);
fulladd full225 (sum[153], carry[153], C[211], C[242], C[273]);
fulladd full226 (sum[154], carry[154], C[212], C[243], C[274]);
fulladd full227 (sum[155], carry[155], C[213], C[244], C[275]);
fulladd full228 (sum[156], carry[156], C[214], C[245], C[276]);
fulladd full229 (sum[157], carry[157], C[215], C[246], C[277]);
fulladd full230 (sum[158], carry[158], C[216], C[247], C[278]);
fulladd full231 (sum[159], carry[159], C[217], C[248], C[279]);
fulladd full232 (sum[160], carry[160], C[218], C[249], C[280]);
fulladd full233 (sum[161], carry[161], C[219], C[250], C[281]);
fulladd full234 (sum[162], carry[162], C[220], C[251], C[282]);
fulladd full235 (sum[163], carry[163], C[221], C[252], C[283]);
fulladd full236 (sum[164], carry[164], C[222], C[253], C[284]);
fulladd full237 (sum[165], carry[165], C[223], C[254], C[285]);
fulladd full238 (sum[166], carry[166], 1'b0, C[255], C[286]);
fulladd full239 (sum[167], carry[167], 1'b0, 1'b0, C[287]);
fulladd full240 (sum[168], carry[168], 1'b0, 1'b0, 1'b0);
fulladd full241 (sum[169], carry[169], 1'b0, 1'b0, 1'b0);
fulladd full242 (sum[170], carry[170], 1'b0, 1'b0, 1'b0);
fulladd full243 (sum[171], carry[171], 1'b0, 1'b0, 1'b0);
fulladd full244 (sum[172], carry[172], 1'b0, 1'b0, 1'b0);
fulladd full245 (sum[173], carry[173], 1'b0, 1'b0, 1'b0);
fulladd full246 (sum[174], carry[174], 1'b0, 1'b0, 1'b0);
fulladd full247 (sum[175], carry[175], 1'b0, 1'b0, 1'b0);
fulladd full248 (sum[176], carry[176], 1'b0, 1'b0, 1'b0);
fulladd full249 (sum[177], carry[177], 1'b0, 1'b0, 1'b0);
fulladd full250 (sum[178], carry[178], 1'b0, 1'b0, 1'b0);
fulladd full251 (sum[179], carry[179], 1'b0, 1'b0, 1'b0);
fulladd full252 (sum[180], carry[180], 1'b0, 1'b0, 1'b0);
fulladd full253 (sum[181], carry[181], 1'b0, 1'b0, 1'b0);
fulladd full254 (sum[182], carry[182], 1'b0, 1'b0, 1'b0);
fulladd full255 (sum[183], carry[183], 1'b0, 1'b0, 1'b0);
fulladd full256 (sum[184], carry[184], 1'b0, 1'b0, 1'b0);
fulladd full257 (sum[185], carry[185], 1'b0, 1'b0, 1'b0);
fulladd full258 (sum[186], carry[186], 1'b0, 1'b0, 1'b0);
fulladd full259 (sum[187], carry[187], 1'b0, 1'b0, 1'b0);
fulladd full260 (sum[188], carry[188], 1'b0, 1'b0, 1'b0);
fulladd full261 (sum[189], carry[189], 1'b0, 1'b0, 1'b0);
fulladd full262 (sum[190], carry[190], 1'b0, 1'b0, 1'b0);
fulladd full263 (sum[191], carry[191], 1'b0, 1'b0, 1'b0);
//pp9,10,11
fulladd full30 (sum[192], carry[192], 1'b0, 1'b0, 1'b0);
fulladd full31 (sum[193], carry[193], 1'b0, 1'b0, 1'b0);
fulladd full32 (sum[194], carry[194], 1'b0, 1'b0, 1'b0);
fulladd full33 (sum[195], carry[195], 1'b0, 1'b0, 1'b0);
fulladd full34 (sum[196], carry[196], 1'b0, 1'b0, 1'b0);
fulladd full35 (sum[197], carry[197], 1'b0, 1'b0, 1'b0);
fulladd full36 (sum[198], carry[198], 1'b0, 1'b0, 1'b0);
fulladd full37 (sum[199], carry[199], 1'b0, 1'b0, 1'b0);
fulladd full38 (sum[200], carry[200], 1'b0, 1'b0, 1'b0);
fulladd full39 (sum[201], carry[201], C[288], 1'b0, 1'b0);
fulladd full310 (sum[202], carry[202], C[289], C[320], 1'b0);
fulladd full311 (sum[203], carry[203], C[290], C[321], C[352]);
fulladd full312 (sum[204], carry[204], C[291], C[322], C[353]);
fulladd full313 (sum[205], carry[205], C[292], C[323], C[354]);
fulladd full314 (sum[206], carry[206], C[293], C[324], C[355]);
fulladd full315 (sum[207], carry[207], C[294], C[325], C[356]);
fulladd full316 (sum[208], carry[208], C[295], C[326], C[357]);
fulladd full317 (sum[209], carry[209], C[296], C[327], C[358]);
fulladd full318 (sum[210], carry[210], C[297], C[328], C[359]);
fulladd full319 (sum[211], carry[211], C[298], C[329], C[360]);
fulladd full320 (sum[212], carry[212], C[299], C[330], C[361]);
fulladd full321 (sum[213], carry[213], C[300], C[331], C[362]);
fulladd full322 (sum[214], carry[214], C[301], C[332], C[363]);
fulladd full323 (sum[215], carry[215], C[302], C[333], C[364]);
fulladd full324 (sum[216], carry[216], C[303], C[334], C[365]);
fulladd full325 (sum[217], carry[217], C[304], C[335], C[366]);
fulladd full326 (sum[218], carry[218], C[305], C[336], C[367]);
fulladd full327 (sum[219], carry[219], C[306], C[337], C[368]);
fulladd full328 (sum[220], carry[220], C[307], C[338], C[369]);
fulladd full329 (sum[221], carry[221], C[308], C[339], C[370]);
fulladd full330 (sum[222], carry[222], C[309], C[340], C[371]);
fulladd full331 (sum[223], carry[223], C[310], C[341], C[372]);
fulladd full332 (sum[224], carry[224], C[311], C[342], C[373]);
fulladd full333 (sum[225], carry[225], C[312], C[343], C[374]);
fulladd full334 (sum[226], carry[226], C[313], C[344], C[375]);
fulladd full335 (sum[227], carry[227], C[314], C[345], C[376]);
fulladd full336 (sum[228], carry[228], C[315], C[346], C[377]);
fulladd full337 (sum[229], carry[229], C[316], C[347], C[378]);
fulladd full338 (sum[230], carry[230], C[317], C[348], C[379]);
fulladd full339 (sum[231], carry[231], C[318], C[349], C[380]);
fulladd full340 (sum[232], carry[232], C[319], C[350], C[381]);
fulladd full341 (sum[233], carry[233], 1'b0, C[351], C[382]);
fulladd full342 (sum[234], carry[234], 1'b0, 1'b0, C[383]);
fulladd full343 (sum[235], carry[235], 1'b0, 1'b0, 1'b0);
fulladd full344 (sum[236], carry[236], 1'b0, 1'b0, 1'b0);
fulladd full345 (sum[237], carry[237], 1'b0, 1'b0, 1'b0);
fulladd full346 (sum[238], carry[238], 1'b0, 1'b0, 1'b0);
fulladd full347 (sum[239], carry[239], 1'b0, 1'b0, 1'b0);
fulladd full348 (sum[240], carry[240], 1'b0, 1'b0, 1'b0);
fulladd full349 (sum[241], carry[241], 1'b0, 1'b0, 1'b0);
fulladd full350 (sum[242], carry[242], 1'b0, 1'b0, 1'b0);
fulladd full351 (sum[243], carry[243], 1'b0, 1'b0, 1'b0);
fulladd full352 (sum[244], carry[244], 1'b0, 1'b0, 1'b0);
fulladd full353 (sum[245], carry[245], 1'b0, 1'b0, 1'b0);
fulladd full354 (sum[246], carry[246], 1'b0, 1'b0, 1'b0);
fulladd full355 (sum[247], carry[247], 1'b0, 1'b0, 1'b0);
fulladd full356 (sum[248], carry[248], 1'b0, 1'b0, 1'b0);
fulladd full357 (sum[249], carry[249], 1'b0, 1'b0, 1'b0);
fulladd full358 (sum[250], carry[250], 1'b0, 1'b0, 1'b0);
fulladd full359 (sum[251], carry[251], 1'b0, 1'b0, 1'b0);
fulladd full360 (sum[252], carry[252], 1'b0, 1'b0, 1'b0);
fulladd full361 (sum[253], carry[253], 1'b0, 1'b0, 1'b0);
fulladd full362 (sum[254], carry[254], 1'b0, 1'b0, 1'b0);
fulladd full363 (sum[255], carry[255], 1'b0, 1'b0, 1'b0);
//pp12,13,14
fulladd full40 (sum[256], carry[256], 1'b0, 1'b0, 1'b0);
fulladd full41 (sum[257], carry[257], 1'b0, 1'b0, 1'b0);
fulladd full42 (sum[258], carry[258], 1'b0, 1'b0, 1'b0);
fulladd full43 (sum[259], carry[259], 1'b0, 1'b0, 1'b0);
fulladd full44 (sum[260], carry[260], 1'b0, 1'b0, 1'b0);
fulladd full45 (sum[261], carry[261], 1'b0, 1'b0, 1'b0);
fulladd full46 (sum[262], carry[262], 1'b0, 1'b0, 1'b0);
fulladd full47 (sum[263], carry[263], 1'b0, 1'b0, 1'b0);
fulladd full48 (sum[264], carry[264], 1'b0, 1'b0, 1'b0);
fulladd full49 (sum[265], carry[265], 1'b0, 1'b0, 1'b0);
fulladd full410 (sum[266], carry[266], 1'b0, 1'b0, 1'b0);
fulladd full411 (sum[267], carry[267], 1'b0, 1'b0, 1'b0);
fulladd full412 (sum[268], carry[268], C[384], 1'b0, 1'b0);
fulladd full413 (sum[269], carry[269], C[385], C[416], 1'b0);
fulladd full414 (sum[270], carry[270], C[386], C[417], C[448]);
fulladd full415 (sum[271], carry[271], C[387], C[418], C[449]);
fulladd full416 (sum[272], carry[272], C[388], C[419], C[450]);
fulladd full417 (sum[273], carry[273], C[389], C[420], C[451]);
fulladd full418 (sum[274], carry[274], C[390], C[421], C[452]);
fulladd full419 (sum[275], carry[275], C[391], C[422], C[453]);
fulladd full420 (sum[276], carry[276], C[392], C[423], C[454]);
fulladd full421 (sum[277], carry[277], C[393], C[424], C[455]);
fulladd full422 (sum[278], carry[278], C[394], C[425], C[456]);
fulladd full423 (sum[279], carry[279], C[395], C[426], C[457]);
fulladd full424 (sum[280], carry[280], C[396], C[427], C[458]);
fulladd full425 (sum[281], carry[281], C[397], C[428], C[459]);
fulladd full426 (sum[282], carry[282], C[398], C[429], C[460]);
fulladd full427 (sum[283], carry[283], C[399], C[430], C[461]);
fulladd full428 (sum[284], carry[284], C[400], C[431], C[462]);
fulladd full429 (sum[285], carry[285], C[401], C[432], C[463]);
fulladd full430 (sum[286], carry[286], C[402], C[433], C[464]);
fulladd full431 (sum[287], carry[287], C[403], C[434], C[465]);
fulladd full432 (sum[288], carry[288], C[404], C[435], C[466]);
fulladd full433 (sum[289], carry[289], C[405], C[436], C[467]);
fulladd full434 (sum[290], carry[290], C[406], C[437], C[468]);
fulladd full435 (sum[291], carry[291], C[407], C[438], C[469]);
fulladd full436 (sum[292], carry[292], C[408], C[439], C[470]);
fulladd full437 (sum[293], carry[293], C[409], C[440], C[471]);
fulladd full438 (sum[294], carry[294], C[410], C[441], C[472]);
fulladd full439 (sum[295], carry[295], C[411], C[442], C[473]);
fulladd full440 (sum[296], carry[296], C[412], C[443], C[474]);
fulladd full441 (sum[297], carry[297], C[413], C[444], C[475]);
fulladd full442 (sum[298], carry[298], C[414], C[445], C[476]);
fulladd full443 (sum[299], carry[299], C[415], C[446], C[477]);
fulladd full444 (sum[300], carry[300], 1'b0, C[477], C[478]);
fulladd full445 (sum[301], carry[301], 1'b0, 1'b0, C[479]);
fulladd full446 (sum[302], carry[302], 1'b0, 1'b0, 1'b0);
fulladd full447 (sum[303], carry[303], 1'b0, 1'b0, 1'b0);
fulladd full448 (sum[304], carry[304], 1'b0, 1'b0, 1'b0);
fulladd full449 (sum[305], carry[305], 1'b0, 1'b0, 1'b0);
fulladd full450 (sum[306], carry[306], 1'b0, 1'b0, 1'b0);
fulladd full451 (sum[307], carry[307], 1'b0, 1'b0, 1'b0);
fulladd full452 (sum[308], carry[308], 1'b0, 1'b0, 1'b0);
fulladd full453 (sum[309], carry[309], 1'b0, 1'b0, 1'b0);
fulladd full454 (sum[310], carry[310], 1'b0, 1'b0, 1'b0);
fulladd full455 (sum[311], carry[311], 1'b0, 1'b0, 1'b0);
fulladd full456 (sum[312], carry[312], 1'b0, 1'b0, 1'b0);
fulladd full457 (sum[313], carry[313], 1'b0, 1'b0, 1'b0);
fulladd full458 (sum[314], carry[314], 1'b0, 1'b0, 1'b0);
fulladd full459 (sum[315], carry[315], 1'b0, 1'b0, 1'b0);
fulladd full460 (sum[316], carry[316], 1'b0, 1'b0, 1'b0);
fulladd full461 (sum[317], carry[317], 1'b0, 1'b0, 1'b0);
fulladd full462 (sum[318], carry[318], 1'b0, 1'b0, 1'b0);
fulladd full463 (sum[319], carry[319], 1'b0, 1'b0, 1'b0);
//pp15,16,17
fulladd full50 (sum[320], carry[320], 1'b0, 1'b0, 1'b0);
fulladd full51 (sum[321], carry[321], 1'b0, 1'b0, 1'b0);
fulladd full52 (sum[322], carry[322], 1'b0, 1'b0, 1'b0);
fulladd full53 (sum[323], carry[323], 1'b0, 1'b0, 1'b0);
fulladd full54 (sum[324], carry[324], 1'b0, 1'b0, 1'b0);
fulladd full55 (sum[325], carry[325], 1'b0, 1'b0, 1'b0);
fulladd full56 (sum[326], carry[326], 1'b0, 1'b0, 1'b0);
fulladd full57 (sum[327], carry[327], 1'b0, 1'b0, 1'b0);
fulladd full58 (sum[328], carry[328], 1'b0, 1'b0, 1'b0);
fulladd full59 (sum[329], carry[329], 1'b0, 1'b0, 1'b0);
fulladd full510 (sum[330], carry[330], 1'b0, 1'b0, 1'b0);
fulladd full511 (sum[331], carry[331], 1'b0, 1'b0, 1'b0);
fulladd full512 (sum[332], carry[332], 1'b0, 1'b0, 1'b0);
fulladd full513 (sum[333], carry[333], 1'b0, 1'b0, 1'b0);
fulladd full514 (sum[334], carry[334], 1'b0, 1'b0, 1'b0);
fulladd full515 (sum[335], carry[335], C[480], 1'b0, 1'b0);
fulladd full516 (sum[336], carry[336], C[481], C[512], 1'b0);
fulladd full517 (sum[337], carry[337], C[482], C[513], C[544]);
fulladd full518 (sum[338], carry[338], C[483], C[514], C[545]);
fulladd full519 (sum[339], carry[339], C[484], C[515], C[546]);
fulladd full520 (sum[340], carry[340], C[485], C[516], C[547]);
fulladd full521 (sum[341], carry[341], C[486], C[517], C[548]);
fulladd full522 (sum[342], carry[342], C[487], C[518], C[549]);
fulladd full523 (sum[343], carry[343], C[488], C[519], C[550]);
fulladd full524 (sum[344], carry[344], C[489], C[520], C[551]);
fulladd full525 (sum[345], carry[345], C[490], C[521], C[552]);
fulladd full526 (sum[346], carry[346], C[491], C[522], C[553]);
fulladd full527 (sum[347], carry[347], C[492], C[523], C[554]);
fulladd full528 (sum[348], carry[348], C[493], C[524], C[555]);
fulladd full529 (sum[349], carry[349], C[494], C[525], C[556]);
fulladd full530 (sum[350], carry[350], C[495], C[526], C[557]);
fulladd full531 (sum[351], carry[351], C[496], C[527], C[558]);
fulladd full532 (sum[352], carry[352], C[497], C[528], C[559]);
fulladd full533 (sum[353], carry[353], C[498], C[529], C[560]);
fulladd full534 (sum[354], carry[354], C[499], C[530], C[561]);
fulladd full535 (sum[355], carry[355], C[500], C[531], C[562]);
fulladd full536 (sum[356], carry[356], C[501], C[532], C[563]);
fulladd full537 (sum[357], carry[357], C[502], C[533], C[564]);
fulladd full538 (sum[358], carry[358], C[503], C[534], C[565]);
fulladd full539 (sum[359], carry[359], C[504], C[535], C[566]);
fulladd full540 (sum[360], carry[360], C[505], C[536], C[567]);
fulladd full541 (sum[361], carry[361], C[506], C[537], C[568]);
fulladd full542 (sum[362], carry[362], C[507], C[538], C[569]);
fulladd full543 (sum[363], carry[363], C[508], C[539], C[570]);
fulladd full544 (sum[364], carry[364], C[509], C[540], C[571]);
fulladd full545 (sum[365], carry[365], C[510], C[541], C[572]);
fulladd full546 (sum[366], carry[366], C[511], C[542], C[573]);
fulladd full547 (sum[367], carry[367], 1'b0, C[543], C[574]);
fulladd full548 (sum[368], carry[368], 1'b0, 1'b0, C[575]);
fulladd full549 (sum[369], carry[369], 1'b0, 1'b0, 1'b0);
fulladd full550 (sum[370], carry[370], 1'b0, 1'b0, 1'b0);
fulladd full551 (sum[371], carry[371], 1'b0, 1'b0, 1'b0);
fulladd full552 (sum[372], carry[372], 1'b0, 1'b0, 1'b0);
fulladd full553 (sum[373], carry[373], 1'b0, 1'b0, 1'b0);
fulladd full554 (sum[374], carry[374], 1'b0, 1'b0, 1'b0);
fulladd full555 (sum[375], carry[375], 1'b0, 1'b0, 1'b0);
fulladd full556 (sum[376], carry[376], 1'b0, 1'b0, 1'b0);
fulladd full557 (sum[377], carry[377], 1'b0, 1'b0, 1'b0);
fulladd full558 (sum[378], carry[378], 1'b0, 1'b0, 1'b0);
fulladd full559 (sum[379], carry[379], 1'b0, 1'b0, 1'b0);
fulladd full560 (sum[380], carry[380], 1'b0, 1'b0, 1'b0);
fulladd full561 (sum[381], carry[381], 1'b0, 1'b0, 1'b0);
fulladd full562 (sum[382], carry[382], 1'b0, 1'b0, 1'b0);
fulladd full563 (sum[383], carry[383], 1'b0, 1'b0, 1'b0);
//pp18,19,20
fulladd full60 (sum[384], carry[384], 1'b0, 1'b0, 1'b0);
fulladd full61 (sum[385], carry[385], 1'b0, 1'b0, 1'b0);
fulladd full62 (sum[386], carry[386], 1'b0, 1'b0, 1'b0);
fulladd full63 (sum[387], carry[387], 1'b0, 1'b0, 1'b0);
fulladd full64 (sum[388], carry[388], 1'b0, 1'b0, 1'b0);
fulladd full65 (sum[389], carry[389], 1'b0, 1'b0, 1'b0);
fulladd full66 (sum[390], carry[390], 1'b0, 1'b0, 1'b0);
fulladd full67 (sum[391], carry[391], 1'b0, 1'b0, 1'b0);
fulladd full68 (sum[392], carry[392], 1'b0, 1'b0, 1'b0);
fulladd full69 (sum[393], carry[393], 1'b0, 1'b0, 1'b0);
fulladd full610 (sum[394], carry[394], 1'b0, 1'b0, 1'b0);
fulladd full611 (sum[395], carry[395], 1'b0, 1'b0, 1'b0);
fulladd full612 (sum[396], carry[396], 1'b0, 1'b0, 1'b0);
fulladd full613 (sum[397], carry[397], 1'b0, 1'b0, 1'b0);
fulladd full614 (sum[398], carry[398], 1'b0, 1'b0, 1'b0);
fulladd full615 (sum[399], carry[399], 1'b0, 1'b0, 1'b0);
fulladd full616 (sum[400], carry[400], 1'b0, 1'b0, 1'b0);
fulladd full617 (sum[401], carry[401], 1'b0, 1'b0, 1'b0);
fulladd full618 (sum[402], carry[402], C[576], 1'b0, 1'b0);
fulladd full619 (sum[403], carry[403], C[577], C[608], 1'b0);
fulladd full620 (sum[404], carry[404], C[578], C[609], C[640]);
fulladd full621 (sum[405], carry[405], C[579], C[610], C[641]);
fulladd full622 (sum[406], carry[406], C[580], C[611], C[642]);
fulladd full623 (sum[407], carry[407], C[581], C[612], C[643]);
fulladd full624 (sum[408], carry[408], C[582], C[613], C[644]);
fulladd full625 (sum[409], carry[409], C[583], C[614], C[645]);
fulladd full626 (sum[410], carry[410], C[584], C[615], C[646]);
fulladd full627 (sum[411], carry[411], C[585], C[616], C[647]);
fulladd full628 (sum[412], carry[412], C[586], C[617], C[648]);
fulladd full629 (sum[413], carry[413], C[587], C[618], C[649]);
fulladd full630 (sum[414], carry[414], C[588], C[619], C[650]);
fulladd full631 (sum[415], carry[415], C[589], C[620], C[651]);
fulladd full632 (sum[416], carry[416], C[590], C[621], C[652]);
fulladd full633 (sum[417], carry[417], C[591], C[622], C[653]);
fulladd full634 (sum[418], carry[418], C[592], C[623], C[654]);
fulladd full635 (sum[419], carry[419], C[593], C[624], C[655]);
fulladd full636 (sum[420], carry[420], C[594], C[625], C[656]);
fulladd full637 (sum[421], carry[421], C[595], C[626], C[657]);
fulladd full638 (sum[422], carry[422], C[596], C[627], C[658]);
fulladd full639 (sum[423], carry[423], C[597], C[628], C[659]);
fulladd full640 (sum[424], carry[424], C[598], C[629], C[660]);
fulladd full641 (sum[425], carry[425], C[599], C[630], C[661]);
fulladd full642 (sum[426], carry[426], C[600], C[631], C[662]);
fulladd full643 (sum[427], carry[427], C[601], C[632], C[663]);
fulladd full644 (sum[428], carry[428], C[602], C[633], C[664]);
fulladd full645 (sum[429], carry[429], C[603], C[634], C[665]);
fulladd full646 (sum[430], carry[430], C[604], C[635], C[666]);
fulladd full647 (sum[431], carry[431], C[605], C[636], C[667]);
fulladd full648 (sum[432], carry[432], C[606], C[637], C[668]);
fulladd full649 (sum[433], carry[433], 1'b0, C[638], C[669]);
fulladd full650 (sum[434], carry[434], 1'b0, 1'b0, C[670]);
fulladd full651 (sum[435], carry[435], 1'b0, 1'b0, 1'b0);
fulladd full652 (sum[436], carry[436], 1'b0, 1'b0, 1'b0);
fulladd full653 (sum[437], carry[437], 1'b0, 1'b0, 1'b0);
fulladd full654 (sum[438], carry[438], 1'b0, 1'b0, 1'b0);
fulladd full655 (sum[439], carry[439], 1'b0, 1'b0, 1'b0);
fulladd full656 (sum[440], carry[440], 1'b0, 1'b0, 1'b0);
fulladd full657 (sum[441], carry[441], 1'b0, 1'b0, 1'b0);
fulladd full658 (sum[442], carry[442], 1'b0, 1'b0, 1'b0);
fulladd full659 (sum[443], carry[443], 1'b0, 1'b0, 1'b0);
fulladd full660 (sum[444], carry[444], 1'b0, 1'b0, 1'b0);
fulladd full661 (sum[445], carry[445], 1'b0, 1'b0, 1'b0);
fulladd full662 (sum[446], carry[446], 1'b0, 1'b0, 1'b0);
fulladd full663 (sum[447], carry[447], 1'b0, 1'b0, 1'b0);
//pp21,22,23
fulladd full70 (sum[448], carry[448], 1'b0, 1'b0, 1'b0);
fulladd full71 (sum[449], carry[449], 1'b0, 1'b0, 1'b0);
fulladd full72 (sum[450], carry[450], 1'b0, 1'b0, 1'b0);
fulladd full73 (sum[451], carry[451], 1'b0, 1'b0, 1'b0);
fulladd full74 (sum[452], carry[452], 1'b0, 1'b0, 1'b0);
fulladd full75 (sum[453], carry[453], 1'b0, 1'b0, 1'b0);
fulladd full76 (sum[454], carry[454], 1'b0, 1'b0, 1'b0);
fulladd full77 (sum[455], carry[455], 1'b0, 1'b0, 1'b0);
fulladd full78 (sum[456], carry[456], 1'b0, 1'b0, 1'b0);
fulladd full79 (sum[457], carry[457], 1'b0, 1'b0, 1'b0);
fulladd full710 (sum[458], carry[458], 1'b0, 1'b0, 1'b0);
fulladd full711 (sum[459], carry[459], 1'b0, 1'b0, 1'b0);
fulladd full712 (sum[460], carry[460], 1'b0, 1'b0, 1'b0);
fulladd full713 (sum[461], carry[461], 1'b0, 1'b0, 1'b0);
fulladd full714 (sum[462], carry[462], 1'b0, 1'b0, 1'b0);
fulladd full715 (sum[463], carry[463], 1'b0, 1'b0, 1'b0);
fulladd full716 (sum[464], carry[464], 1'b0, 1'b0, 1'b0);
fulladd full717 (sum[465], carry[465], 1'b0, 1'b0, 1'b0);
fulladd full718 (sum[466], carry[466], 1'b0, 1'b0, 1'b0);
fulladd full719 (sum[467], carry[467], 1'b0, 1'b0, 1'b0);
fulladd full720 (sum[468], carry[468], 1'b0, 1'b0, 1'b0);
fulladd full721 (sum[469], carry[469], C[672], 1'b0, 1'b0);
fulladd full722 (sum[470], carry[470], C[673], C[704], 1'b0);
fulladd full723 (sum[471], carry[471], C[674], C[705], C[736]);
fulladd full724 (sum[472], carry[472], C[675], C[706], C[737]);
fulladd full725 (sum[473], carry[473], C[676], C[707], C[738]);
fulladd full726 (sum[474], carry[474], C[677], C[708], C[739]);
fulladd full727 (sum[475], carry[475], C[678], C[709], C[740]);
fulladd full728 (sum[476], carry[476], C[679], C[710], C[741]);
fulladd full729 (sum[477], carry[477], C[680], C[711], C[742]);
fulladd full730 (sum[478], carry[478], C[681], C[712], C[743]);
fulladd full731 (sum[479], carry[479], C[682], C[713], C[744]);
fulladd full732 (sum[480], carry[480], C[683], C[714], C[745]);
fulladd full733 (sum[481], carry[481], C[684], C[715], C[746]);
fulladd full734 (sum[482], carry[482], C[685], C[716], C[747]);
fulladd full735 (sum[483], carry[483], C[686], C[717], C[748]);
fulladd full736 (sum[484], carry[484], C[687], C[718], C[749]);
fulladd full737 (sum[485], carry[485], C[688], C[719], C[750]);
fulladd full738 (sum[486], carry[486], C[689], C[720], C[751]);
fulladd full739 (sum[487], carry[487], C[690], C[721], C[752]);
fulladd full740 (sum[488], carry[488], C[691], C[722], C[753]);
fulladd full741 (sum[489], carry[489], C[692], C[723], C[754]);
fulladd full742 (sum[490], carry[490], C[693], C[724], C[755]);
fulladd full743 (sum[491], carry[491], C[694], C[725], C[756]);
fulladd full744 (sum[492], carry[492], C[695], C[726], C[757]);
fulladd full745 (sum[493], carry[493], C[696], C[727], C[758]);
fulladd full746 (sum[494], carry[494], C[697], C[728], C[759]);
fulladd full747 (sum[495], carry[495], C[698], C[729], C[760]);
fulladd full748 (sum[496], carry[496], C[699], C[730], C[761]);
fulladd full749 (sum[497], carry[497], C[700], C[731], C[762]);
fulladd full750 (sum[498], carry[498], C[701], C[732], C[763]);
fulladd full751 (sum[499], carry[499], C[702], C[733], C[764]);
fulladd full752 (sum[500], carry[500], C[703], C[734], C[765]);
fulladd full753 (sum[501], carry[501], 1'b0, C[735], C[766]);
fulladd full754 (sum[502], carry[502], 1'b0, 1'b0, C[767]);
fulladd full755 (sum[503], carry[503], 1'b0, 1'b0, 1'b0);
fulladd full756 (sum[504], carry[504], 1'b0, 1'b0, 1'b0);
fulladd full757 (sum[505], carry[505], 1'b0, 1'b0, 1'b0);
fulladd full758 (sum[506], carry[506], 1'b0, 1'b0, 1'b0);
fulladd full759 (sum[507], carry[507], 1'b0, 1'b0, 1'b0);
fulladd full760 (sum[508], carry[508], 1'b0, 1'b0, 1'b0);
fulladd full761 (sum[509], carry[509], 1'b0, 1'b0, 1'b0);
fulladd full762 (sum[510], carry[510], 1'b0, 1'b0, 1'b0);
fulladd full763 (sum[511], carry[511], 1'b0, 1'b0, 1'b0);
//pp24,25,26
fulladd full80 (sum[512], carry[512], 1'b0, 1'b0, 1'b0);
fulladd full81 (sum[513], carry[513], 1'b0, 1'b0, 1'b0);
fulladd full82 (sum[514], carry[514], 1'b0, 1'b0, 1'b0);
fulladd full83 (sum[515], carry[515], 1'b0, 1'b0, 1'b0);
fulladd full84 (sum[516], carry[516], 1'b0, 1'b0, 1'b0);
fulladd full85 (sum[517], carry[517], 1'b0, 1'b0, 1'b0);
fulladd full86 (sum[518], carry[518], 1'b0, 1'b0, 1'b0);
fulladd full87 (sum[519], carry[519], 1'b0, 1'b0, 1'b0);
fulladd full88 (sum[520], carry[520], 1'b0, 1'b0, 1'b0);
fulladd full89 (sum[521], carry[521], 1'b0, 1'b0, 1'b0);
fulladd full810 (sum[522], carry[522], 1'b0, 1'b0, 1'b0);
fulladd full811 (sum[523], carry[523], 1'b0, 1'b0, 1'b0);
fulladd full812 (sum[524], carry[524], 1'b0, 1'b0, 1'b0);
fulladd full813 (sum[525], carry[525], 1'b0, 1'b0, 1'b0);
fulladd full814 (sum[526], carry[526], 1'b0, 1'b0, 1'b0);
fulladd full815 (sum[527], carry[527], 1'b0, 1'b0, 1'b0);
fulladd full816 (sum[528], carry[528], 1'b0, 1'b0, 1'b0);
fulladd full817 (sum[529], carry[529], 1'b0, 1'b0, 1'b0);
fulladd full818 (sum[530], carry[530], 1'b0, 1'b0, 1'b0);
fulladd full819 (sum[531], carry[531], 1'b0, 1'b0, 1'b0);
fulladd full820 (sum[532], carry[532], 1'b0, 1'b0, 1'b0);
fulladd full821 (sum[533], carry[533], 1'b0, 1'b0, 1'b0);
fulladd full822 (sum[534], carry[534], 1'b0, 1'b0, 1'b0);
fulladd full823 (sum[535], carry[535], 1'b0, 1'b0, 1'b0);
fulladd full824 (sum[536], carry[536], C[768], 1'b0, 1'b0);
fulladd full825 (sum[537], carry[537], C[769], C[800], 1'b0);
fulladd full826 (sum[538], carry[538], C[770], C[801], C[832]);
fulladd full827 (sum[539], carry[539], C[771], C[802], C[833]);
fulladd full828 (sum[540], carry[540], C[772], C[803], C[834]);
fulladd full829 (sum[541], carry[541], C[773], C[804], C[835]);
fulladd full830 (sum[542], carry[542], C[774], C[805], C[836]);
fulladd full831 (sum[543], carry[543], C[775], C[806], C[837]);
fulladd full832 (sum[544], carry[544], C[776], C[807], C[838]);
fulladd full833 (sum[545], carry[545], C[777], C[808], C[839]);
fulladd full834 (sum[546], carry[546], C[778], C[809], C[840]);
fulladd full835 (sum[547], carry[547], C[779], C[810], C[841]);
fulladd full836 (sum[548], carry[548], C[780], C[811], C[842]);
fulladd full837 (sum[549], carry[549], C[781], C[812], C[843]);
fulladd full838 (sum[550], carry[550], C[782], C[813], C[844]);
fulladd full839 (sum[551], carry[551], C[783], C[814], C[845]);
fulladd full840 (sum[552], carry[552], C[784], C[815], C[846]);
fulladd full841 (sum[553], carry[553], C[785], C[816], C[847]);
fulladd full842 (sum[554], carry[554], C[786], C[817], C[848]);
fulladd full843 (sum[555], carry[555], C[787], C[818], C[849]);
fulladd full844 (sum[556], carry[556], C[788], C[819], C[850]);
fulladd full845 (sum[557], carry[557], C[789], C[820], C[851]);
fulladd full846 (sum[558], carry[558], C[790], C[821], C[852]);
fulladd full847 (sum[559], carry[559], C[791], C[822], C[853]);
fulladd full848 (sum[560], carry[560], C[792], C[823], C[854]);
fulladd full849 (sum[561], carry[561], C[793], C[824], C[855]);
fulladd full850 (sum[562], carry[562], C[794], C[825], C[856]);
fulladd full851 (sum[563], carry[563], C[795], C[826], C[857]);
fulladd full852 (sum[564], carry[564], C[796], C[827], C[858]);
fulladd full853 (sum[565], carry[565], C[797], C[828], C[859]);
fulladd full854 (sum[566], carry[566], C[798], C[829], C[860]);
fulladd full855 (sum[567], carry[567], C[799], C[830], C[861]);
fulladd full856 (sum[568], carry[568], 1'b0, C[831], C[862]);
fulladd full857 (sum[569], carry[569], 1'b0, 1'b0, C[863]);
fulladd full858 (sum[570], carry[570], 1'b0, 1'b0, 1'b0);
fulladd full859 (sum[571], carry[571], 1'b0, 1'b0, 1'b0);
fulladd full860 (sum[572], carry[572], 1'b0, 1'b0, 1'b0);
fulladd full861 (sum[573], carry[573], 1'b0, 1'b0, 1'b0);
fulladd full862 (sum[574], carry[574], 1'b0, 1'b0, 1'b0);
fulladd full863 (sum[575], carry[575], 1'b0, 1'b0, 1'b0);
//pp27,28,29
fulladd full90 (sum[576], carry[576], 1'b0, 1'b0, 1'b0);
fulladd full91 (sum[577], carry[577], 1'b0, 1'b0, 1'b0);
fulladd full92 (sum[578], carry[578], 1'b0, 1'b0, 1'b0);
fulladd full93 (sum[579], carry[579], 1'b0, 1'b0, 1'b0);
fulladd full94 (sum[580], carry[580], 1'b0, 1'b0, 1'b0);
fulladd full95 (sum[581], carry[581], 1'b0, 1'b0, 1'b0);
fulladd full96 (sum[582], carry[582], 1'b0, 1'b0, 1'b0);
fulladd full97 (sum[583], carry[583], 1'b0, 1'b0, 1'b0);
fulladd full98 (sum[584], carry[584], 1'b0, 1'b0, 1'b0);
fulladd full99 (sum[585], carry[585], 1'b0, 1'b0, 1'b0);
fulladd full910 (sum[586], carry[586], 1'b0, 1'b0, 1'b0);
fulladd full911 (sum[587], carry[587], 1'b0, 1'b0, 1'b0);
fulladd full912 (sum[588], carry[588], 1'b0, 1'b0, 1'b0);
fulladd full913 (sum[589], carry[589], 1'b0, 1'b0, 1'b0);
fulladd full914 (sum[590], carry[590], 1'b0, 1'b0, 1'b0);
fulladd full915 (sum[591], carry[591], 1'b0, 1'b0, 1'b0);
fulladd full916 (sum[592], carry[592], 1'b0, 1'b0, 1'b0);
fulladd full917 (sum[593], carry[593], 1'b0, 1'b0, 1'b0);
fulladd full918 (sum[594], carry[594], 1'b0, 1'b0, 1'b0);
fulladd full919 (sum[595], carry[595], 1'b0, 1'b0, 1'b0);
fulladd full920 (sum[596], carry[596], 1'b0, 1'b0, 1'b0);
fulladd full921 (sum[597], carry[597], 1'b0, 1'b0, 1'b0);
fulladd full922 (sum[598], carry[598], 1'b0, 1'b0, 1'b0);
fulladd full923 (sum[599], carry[599], 1'b0, 1'b0, 1'b0);
fulladd full924 (sum[600], carry[600], 1'b0, 1'b0, 1'b0);
fulladd full925 (sum[601], carry[601], 1'b0, 1'b0, 1'b0);
fulladd full926 (sum[602], carry[602], 1'b0, 1'b0, 1'b0);
fulladd full927 (sum[603], carry[603], C[864], 1'b0, 1'b0);
fulladd full928 (sum[604], carry[604], C[865], C[896], 1'b0);
fulladd full929 (sum[605], carry[605], C[866], C[897], C[928]);
fulladd full930 (sum[606], carry[606], C[867], C[898], C[929]);
fulladd full931 (sum[607], carry[607], C[868], C[899], C[930]);
fulladd full932 (sum[608], carry[608], C[869], C[900], C[931]);
fulladd full933 (sum[609], carry[609], C[870], C[901], C[932]);
fulladd full934 (sum[610], carry[610], C[871], C[902], C[933]);
fulladd full935 (sum[611], carry[611], C[872], C[903], C[934]);
fulladd full936 (sum[612], carry[612], C[873], C[904], C[935]);
fulladd full937 (sum[613], carry[613], C[874], C[905], C[936]);
fulladd full938 (sum[614], carry[614], C[875], C[906], C[937]);
fulladd full939 (sum[615], carry[615], C[876], C[907], C[938]);
fulladd full940 (sum[616], carry[616], C[877], C[908], C[939]);
fulladd full941 (sum[617], carry[617], C[878], C[909], C[940]);
fulladd full942 (sum[618], carry[618], C[879], C[910], C[941]);
fulladd full943 (sum[619], carry[619], C[880], C[911], C[942]);
fulladd full944 (sum[620], carry[620], C[881], C[912], C[943]);
fulladd full945 (sum[621], carry[621], C[882], C[913], C[944]);
fulladd full946 (sum[622], carry[622], C[883], C[914], C[945]);
fulladd full947 (sum[623], carry[623], C[884], C[915], C[946]);
fulladd full948 (sum[624], carry[624], C[885], C[916], C[947]);
fulladd full949 (sum[625], carry[625], C[886], C[917], C[948]);
fulladd full950 (sum[626], carry[626], C[887], C[918], C[949]);
fulladd full951 (sum[627], carry[627], C[888], C[919], C[950]);
fulladd full952 (sum[628], carry[628], C[889], C[920], C[951]);
fulladd full953 (sum[629], carry[629], C[890], C[921], C[952]);
fulladd full954 (sum[630], carry[630], C[891], C[922], C[953]);
fulladd full955 (sum[631], carry[631], C[892], C[923], C[954]);
fulladd full956 (sum[632], carry[632], C[893], C[924], C[955]);
fulladd full957 (sum[633], carry[633], C[894], C[925], C[956]);
fulladd full958 (sum[634], carry[634], C[895], C[926], C[957]);
fulladd full959 (sum[635], carry[635], 1'b0, C[927], C[958]);
fulladd full960 (sum[636], carry[636], 1'b0, 1'b0, C[959]);
fulladd full961 (sum[637], carry[637], 1'b0, 1'b0, 1'b0);
fulladd full962 (sum[638], carry[638], 1'b0, 1'b0, 1'b0);
fulladd full963 (sum[639], carry[639], 1'b0, 1'b0, 1'b0);
//sum0/1/2
fulladd full1_00 (sum_1[0], carry_1[0], sum[0], sum[64], sum[128]);
fulladd full1_01 (sum_1[1], carry_1[1], sum[1], sum[65], sum[129]);
fulladd full1_02 (sum_1[2], carry_1[2], sum[2], sum[66], sum[130]);
fulladd full1_03 (sum_1[3], carry_1[3], sum[3], sum[67], sum[131]);
fulladd full1_04 (sum_1[4], carry_1[4], sum[4], sum[68], sum[132]);
fulladd full1_05 (sum_1[5], carry_1[5], sum[5], sum[69], sum[133]);
fulladd full1_06 (sum_1[6], carry_1[6], sum[6], sum[70], sum[134]);
fulladd full1_07 (sum_1[7], carry_1[7], sum[7], sum[71], sum[135]);
fulladd full1_08 (sum_1[8], carry_1[8], sum[8], sum[72], sum[136]);
fulladd full1_09 (sum_1[9], carry_1[9], sum[9], sum[73], sum[137]);
fulladd full1_010 (sum_1[10], carry_1[10], sum[10], sum[74], sum[138]);
fulladd full1_011 (sum_1[11], carry_1[11], sum[11], sum[75], sum[139]);
fulladd full1_012 (sum_1[12], carry_1[12], sum[12], sum[76], sum[140]);
fulladd full1_013 (sum_1[13], carry_1[13], sum[13], sum[77], sum[141]);
fulladd full1_014 (sum_1[14], carry_1[14], sum[14], sum[78], sum[142]);
fulladd full1_015 (sum_1[15], carry_1[15], sum[15], sum[79], sum[143]);
fulladd full1_016 (sum_1[16], carry_1[16], sum[16], sum[80], sum[144]);
fulladd full1_017 (sum_1[17], carry_1[17], sum[17], sum[81], sum[145]);
fulladd full1_018 (sum_1[18], carry_1[18], sum[18], sum[82], sum[146]);
fulladd full1_019 (sum_1[19], carry_1[19], sum[19], sum[83], sum[147]);
fulladd full1_020 (sum_1[20], carry_1[20], sum[20], sum[84], sum[148]);
fulladd full1_021 (sum_1[21], carry_1[21], sum[21], sum[85], sum[149]);
fulladd full1_022 (sum_1[22], carry_1[22], sum[22], sum[86], sum[150]);
fulladd full1_023 (sum_1[23], carry_1[23], sum[23], sum[87], sum[151]);
fulladd full1_024 (sum_1[24], carry_1[24], sum[24], sum[88], sum[152]);
fulladd full1_025 (sum_1[25], carry_1[25], sum[25], sum[89], sum[153]);
fulladd full1_026 (sum_1[26], carry_1[26], sum[26], sum[90], sum[154]);
fulladd full1_027 (sum_1[27], carry_1[27], sum[27], sum[91], sum[155]);
fulladd full1_028 (sum_1[28], carry_1[28], sum[28], sum[92], sum[156]);
fulladd full1_029 (sum_1[29], carry_1[29], sum[29], sum[93], sum[157]);
fulladd full1_030 (sum_1[30], carry_1[30], sum[30], sum[94], sum[158]);
fulladd full1_031 (sum_1[31], carry_1[31], sum[31], sum[95], sum[159]);
fulladd full1_032 (sum_1[32], carry_1[32], sum[32], sum[96], sum[160]);
fulladd full1_033 (sum_1[33], carry_1[33], sum[33], sum[97], sum[161]);
fulladd full1_034 (sum_1[34], carry_1[34], sum[34], sum[98], sum[162]);
fulladd full1_035 (sum_1[35], carry_1[35], sum[35], sum[99], sum[163]);
fulladd full1_036 (sum_1[36], carry_1[36], sum[36], sum[100], sum[164]);
fulladd full1_037 (sum_1[37], carry_1[37], sum[37], sum[101], sum[165]);
fulladd full1_038 (sum_1[38], carry_1[38], sum[38], sum[102], sum[166]);
fulladd full1_039 (sum_1[39], carry_1[39], sum[39], sum[103], sum[167]);
fulladd full1_040 (sum_1[40], carry_1[40], sum[40], sum[104], sum[168]);
fulladd full1_041 (sum_1[41], carry_1[41], sum[41], sum[105], sum[169]);
fulladd full1_042 (sum_1[42], carry_1[42], sum[42], sum[106], sum[170]);
fulladd full1_043 (sum_1[43], carry_1[43], sum[43], sum[107], sum[171]);
fulladd full1_044 (sum_1[44], carry_1[44], sum[44], sum[108], sum[172]);
fulladd full1_045 (sum_1[45], carry_1[45], sum[45], sum[109], sum[173]);
fulladd full1_046 (sum_1[46], carry_1[46], sum[46], sum[110], sum[174]);
fulladd full1_047 (sum_1[47], carry_1[47], sum[47], sum[111], sum[175]);
fulladd full1_048 (sum_1[48], carry_1[48], sum[48], sum[112], sum[176]);
fulladd full1_049 (sum_1[49], carry_1[49], sum[49], sum[113], sum[177]);
fulladd full1_050 (sum_1[50], carry_1[50], sum[50], sum[114], sum[178]);
fulladd full1_051 (sum_1[51], carry_1[51], sum[51], sum[115], sum[179]);
fulladd full1_052 (sum_1[52], carry_1[52], sum[52], sum[116], sum[180]);
fulladd full1_053 (sum_1[53], carry_1[53], sum[53], sum[117], sum[181]);
fulladd full1_054 (sum_1[54], carry_1[54], sum[54], sum[118], sum[182]);
fulladd full1_055 (sum_1[55], carry_1[55], sum[55], sum[119], sum[183]);
fulladd full1_056 (sum_1[56], carry_1[56], sum[56], sum[120], sum[184]);
fulladd full1_057 (sum_1[57], carry_1[57], sum[57], sum[121], sum[185]);
fulladd full1_058 (sum_1[58], carry_1[58], sum[58], sum[122], sum[186]);
fulladd full1_059 (sum_1[59], carry_1[59], sum[59], sum[123], sum[187]);
fulladd full1_060 (sum_1[60], carry_1[60], sum[60], sum[124], sum[188]);
fulladd full1_061 (sum_1[61], carry_1[61], sum[61], sum[125], sum[189]);
fulladd full1_062 (sum_1[62], carry_1[62], sum[62], sum[126], sum[190]);
fulladd full1_063 (sum_1[63], carry_1[63], sum[63], sum[127], sum[191]);
//sum3/4/5
fulladd full1_10 (sum_1[64], carry_1[64], sum[192], sum[256], sum[320]);
fulladd full1_11 (sum_1[65], carry_1[65], sum[193], sum[257], sum[321]);
fulladd full1_12 (sum_1[66], carry_1[66], sum[194], sum[258], sum[322]);
fulladd full1_13 (sum_1[67], carry_1[67], sum[195], sum[259], sum[323]);
fulladd full1_14 (sum_1[68], carry_1[68], sum[196], sum[260], sum[324]);
fulladd full1_15 (sum_1[69], carry_1[69], sum[197], sum[261], sum[325]);
fulladd full1_16 (sum_1[70], carry_1[70], sum[198], sum[262], sum[326]);
fulladd full1_17 (sum_1[71], carry_1[71], sum[199], sum[263], sum[327]);
fulladd full1_18 (sum_1[72], carry_1[72], sum[200], sum[264], sum[328]);
fulladd full1_19 (sum_1[73], carry_1[73], sum[201], sum[265], sum[329]);
fulladd full1_110 (sum_1[74], carry_1[74], sum[202], sum[266], sum[330]);
fulladd full1_111 (sum_1[75], carry_1[75], sum[203], sum[267], sum[331]);
fulladd full1_112 (sum_1[76], carry_1[76], sum[204], sum[268], sum[332]);
fulladd full1_113 (sum_1[77], carry_1[77], sum[205], sum[269], sum[333]);
fulladd full1_114 (sum_1[78], carry_1[78], sum[206], sum[270], sum[334]);
fulladd full1_115 (sum_1[79], carry_1[79], sum[207], sum[271], sum[335]);
fulladd full1_116 (sum_1[80], carry_1[80], sum[208], sum[272], sum[336]);
fulladd full1_117 (sum_1[81], carry_1[81], sum[209], sum[273], sum[337]);
fulladd full1_118 (sum_1[82], carry_1[82], sum[210], sum[274], sum[338]);
fulladd full1_119 (sum_1[83], carry_1[83], sum[211], sum[275], sum[339]);
fulladd full1_120 (sum_1[84], carry_1[84], sum[212], sum[276], sum[340]);
fulladd full1_121 (sum_1[85], carry_1[85], sum[213], sum[277], sum[341]);
fulladd full1_122 (sum_1[86], carry_1[86], sum[214], sum[278], sum[342]);
fulladd full1_123 (sum_1[87], carry_1[87], sum[215], sum[279], sum[343]);
fulladd full1_124 (sum_1[88], carry_1[88], sum[216], sum[280], sum[344]);
fulladd full1_125 (sum_1[89], carry_1[89], sum[217], sum[281], sum[345]);
fulladd full1_126 (sum_1[90], carry_1[90], sum[218], sum[282], sum[346]);
fulladd full1_127 (sum_1[91], carry_1[91], sum[219], sum[283], sum[347]);
fulladd full1_128 (sum_1[92], carry_1[92], sum[220], sum[284], sum[348]);
fulladd full1_129 (sum_1[93], carry_1[93], sum[221], sum[285], sum[349]);
fulladd full1_130 (sum_1[94], carry_1[94], sum[222], sum[286], sum[350]);
fulladd full1_131 (sum_1[95], carry_1[95], sum[223], sum[287], sum[351]);
fulladd full1_132 (sum_1[96], carry_1[96], sum[224], sum[288], sum[352]);
fulladd full1_133 (sum_1[97], carry_1[97], sum[225], sum[289], sum[353]);
fulladd full1_134 (sum_1[98], carry_1[98], sum[226], sum[290], sum[354]);
fulladd full1_135 (sum_1[99], carry_1[99], sum[227], sum[291], sum[355]);
fulladd full1_136 (sum_1[100], carry_1[100], sum[228], sum[292], sum[356]);
fulladd full1_137 (sum_1[101], carry_1[101], sum[229], sum[293], sum[357]);
fulladd full1_138 (sum_1[102], carry_1[102], sum[230], sum[294], sum[358]);
fulladd full1_139 (sum_1[103], carry_1[103], sum[231], sum[295], sum[359]);
fulladd full1_140 (sum_1[104], carry_1[104], sum[232], sum[296], sum[360]);
fulladd full1_141 (sum_1[105], carry_1[105], sum[233], sum[297], sum[361]);
fulladd full1_142 (sum_1[106], carry_1[106], sum[234], sum[298], sum[362]);
fulladd full1_143 (sum_1[107], carry_1[107], sum[235], sum[299], sum[363]);
fulladd full1_144 (sum_1[108], carry_1[108], sum[236], sum[300], sum[364]);
fulladd full1_145 (sum_1[109], carry_1[109], sum[237], sum[301], sum[365]);
fulladd full1_146 (sum_1[110], carry_1[110], sum[238], sum[302], sum[366]);
fulladd full1_147 (sum_1[111], carry_1[111], sum[239], sum[303], sum[367]);
fulladd full1_148 (sum_1[112], carry_1[112], sum[240], sum[304], sum[368]);
fulladd full1_149 (sum_1[113], carry_1[113], sum[241], sum[305], sum[369]);
fulladd full1_150 (sum_1[114], carry_1[114], sum[242], sum[306], sum[370]);
fulladd full1_151 (sum_1[115], carry_1[115], sum[243], sum[307], sum[371]);
fulladd full1_152 (sum_1[116], carry_1[116], sum[244], sum[308], sum[372]);
fulladd full1_153 (sum_1[117], carry_1[117], sum[245], sum[309], sum[373]);
fulladd full1_154 (sum_1[118], carry_1[118], sum[246], sum[310], sum[374]);
fulladd full1_155 (sum_1[119], carry_1[119], sum[247], sum[311], sum[375]);
fulladd full1_156 (sum_1[120], carry_1[120], sum[248], sum[312], sum[376]);
fulladd full1_157 (sum_1[121], carry_1[121], sum[249], sum[313], sum[377]);
fulladd full1_158 (sum_1[122], carry_1[122], sum[250], sum[314], sum[378]);
fulladd full1_159 (sum_1[123], carry_1[123], sum[251], sum[315], sum[379]);
fulladd full1_160 (sum_1[124], carry_1[124], sum[252], sum[316], sum[380]);
fulladd full1_161 (sum_1[125], carry_1[125], sum[253], sum[317], sum[381]);
fulladd full1_162 (sum_1[126], carry_1[126], sum[254], sum[318], sum[382]);
fulladd full1_163 (sum_1[127], carry_1[127], sum[255], sum[319], sum[383]);
//sum6/7/8
fulladd full1_20 (sum_1[128], carry_1[128], sum[384], sum[448], sum[512]);
fulladd full1_21 (sum_1[129], carry_1[129], sum[385], sum[449], sum[513]);
fulladd full1_22 (sum_1[130], carry_1[130], sum[386], sum[450], sum[514]);
fulladd full1_23 (sum_1[131], carry_1[131], sum[387], sum[451], sum[515]);
fulladd full1_24 (sum_1[132], carry_1[132], sum[388], sum[452], sum[516]);
fulladd full1_25 (sum_1[133], carry_1[133], sum[389], sum[453], sum[517]);
fulladd full1_26 (sum_1[134], carry_1[134], sum[390], sum[454], sum[518]);
fulladd full1_27 (sum_1[135], carry_1[135], sum[391], sum[455], sum[519]);
fulladd full1_28 (sum_1[136], carry_1[136], sum[392], sum[456], sum[520]);
fulladd full1_29 (sum_1[137], carry_1[137], sum[393], sum[457], sum[521]);
fulladd full1_210 (sum_1[138], carry_1[138], sum[394], sum[458], sum[522]);
fulladd full1_211 (sum_1[139], carry_1[139], sum[395], sum[459], sum[523]);
fulladd full1_212 (sum_1[140], carry_1[140], sum[396], sum[460], sum[524]);
fulladd full1_213 (sum_1[141], carry_1[141], sum[397], sum[461], sum[525]);
fulladd full1_214 (sum_1[142], carry_1[142], sum[398], sum[462], sum[526]);
fulladd full1_215 (sum_1[143], carry_1[143], sum[399], sum[463], sum[527]);
fulladd full1_216 (sum_1[144], carry_1[144], sum[400], sum[464], sum[528]);
fulladd full1_217 (sum_1[145], carry_1[145], sum[401], sum[465], sum[529]);
fulladd full1_218 (sum_1[146], carry_1[146], sum[402], sum[466], sum[530]);
fulladd full1_219 (sum_1[147], carry_1[147], sum[403], sum[467], sum[531]);
fulladd full1_220 (sum_1[148], carry_1[148], sum[404], sum[468], sum[532]);
fulladd full1_221 (sum_1[149], carry_1[149], sum[405], sum[469], sum[533]);
fulladd full1_222 (sum_1[150], carry_1[150], sum[406], sum[470], sum[534]);
fulladd full1_223 (sum_1[151], carry_1[151], sum[407], sum[471], sum[535]);
fulladd full1_224 (sum_1[152], carry_1[152], sum[408], sum[472], sum[536]);
fulladd full1_225 (sum_1[153], carry_1[153], sum[409], sum[473], sum[537]);
fulladd full1_226 (sum_1[154], carry_1[154], sum[410], sum[474], sum[538]);
fulladd full1_227 (sum_1[155], carry_1[155], sum[411], sum[475], sum[539]);
fulladd full1_228 (sum_1[156], carry_1[156], sum[412], sum[476], sum[540]);
fulladd full1_229 (sum_1[157], carry_1[157], sum[413], sum[477], sum[541]);
fulladd full1_230 (sum_1[158], carry_1[158], sum[414], sum[478], sum[542]);
fulladd full1_231 (sum_1[159], carry_1[159], sum[415], sum[479], sum[543]);
fulladd full1_232 (sum_1[160], carry_1[160], sum[416], sum[480], sum[544]);
fulladd full1_233 (sum_1[161], carry_1[161], sum[417], sum[481], sum[545]);
fulladd full1_234 (sum_1[162], carry_1[162], sum[418], sum[482], sum[546]);
fulladd full1_235 (sum_1[163], carry_1[163], sum[419], sum[483], sum[547]);
fulladd full1_236 (sum_1[164], carry_1[164], sum[420], sum[484], sum[548]);
fulladd full1_237 (sum_1[165], carry_1[165], sum[421], sum[485], sum[549]);
fulladd full1_238 (sum_1[166], carry_1[166], sum[422], sum[486], sum[550]);
fulladd full1_239 (sum_1[167], carry_1[167], sum[423], sum[487], sum[551]);
fulladd full1_240 (sum_1[168], carry_1[168], sum[424], sum[488], sum[552]);
fulladd full1_241 (sum_1[169], carry_1[169], sum[425], sum[489], sum[553]);
fulladd full1_242 (sum_1[170], carry_1[170], sum[426], sum[490], sum[554]);
fulladd full1_243 (sum_1[171], carry_1[171], sum[427], sum[491], sum[555]);
fulladd full1_244 (sum_1[172], carry_1[172], sum[428], sum[492], sum[556]);
fulladd full1_245 (sum_1[173], carry_1[173], sum[429], sum[493], sum[557]);
fulladd full1_246 (sum_1[174], carry_1[174], sum[430], sum[494], sum[558]);
fulladd full1_247 (sum_1[175], carry_1[175], sum[431], sum[495], sum[559]);
fulladd full1_248 (sum_1[176], carry_1[176], sum[432], sum[496], sum[560]);
fulladd full1_249 (sum_1[177], carry_1[177], sum[433], sum[497], sum[561]);
fulladd full1_250 (sum_1[178], carry_1[178], sum[434], sum[498], sum[562]);
fulladd full1_251 (sum_1[179], carry_1[179], sum[435], sum[499], sum[563]);
fulladd full1_252 (sum_1[180], carry_1[180], sum[436], sum[500], sum[564]);
fulladd full1_253 (sum_1[181], carry_1[181], sum[437], sum[501], sum[565]);
fulladd full1_254 (sum_1[182], carry_1[182], sum[438], sum[502], sum[566]);
fulladd full1_255 (sum_1[183], carry_1[183], sum[439], sum[503], sum[567]);
fulladd full1_256 (sum_1[184], carry_1[184], sum[440], sum[504], sum[568]);
fulladd full1_257 (sum_1[185], carry_1[185], sum[441], sum[505], sum[569]);
fulladd full1_258 (sum_1[186], carry_1[186], sum[442], sum[506], sum[570]);
fulladd full1_259 (sum_1[187], carry_1[187], sum[443], sum[507], sum[571]);
fulladd full1_260 (sum_1[188], carry_1[188], sum[444], sum[508], sum[572]);
fulladd full1_261 (sum_1[189], carry_1[189], sum[445], sum[509], sum[573]);
fulladd full1_262 (sum_1[190], carry_1[190], sum[446], sum[510], sum[574]);
fulladd full1_263 (sum_1[191], carry_1[191], sum[447], sum[511], sum[575]);
//carry0/1/2
fulladd full1_30 (sum_1[192], carry_1[192], 1'b0, 1'b0, 1'b0);
fulladd full1_31 (sum_1[193], carry_1[193], carry[0], carry[64], carry[128]);
fulladd full1_32 (sum_1[194], carry_1[194], carry[1], carry[65], carry[129]);
fulladd full1_33 (sum_1[195], carry_1[195], carry[2], carry[66], carry[130]);
fulladd full1_34 (sum_1[196], carry_1[196], carry[3], carry[67], carry[131]);
fulladd full1_35 (sum_1[197], carry_1[197], carry[4], carry[68], carry[132]);
fulladd full1_36 (sum_1[198], carry_1[198], carry[5], carry[69], carry[133]);
fulladd full1_37 (sum_1[199], carry_1[199], carry[6], carry[70], carry[134]);
fulladd full1_38 (sum_1[200], carry_1[200], carry[7], carry[71], carry[135]);
fulladd full1_39 (sum_1[201], carry_1[201], carry[8], carry[72], carry[136]);
fulladd full1_310 (sum_1[202], carry_1[202], carry[9], carry[73], carry[137]);
fulladd full1_311 (sum_1[203], carry_1[203], carry[10], carry[74], carry[138]);
fulladd full1_312 (sum_1[204], carry_1[204], carry[11], carry[75], carry[139]);
fulladd full1_313 (sum_1[205], carry_1[205], carry[12], carry[76], carry[140]);
fulladd full1_314 (sum_1[206], carry_1[206], carry[13], carry[77], carry[141]);
fulladd full1_315 (sum_1[207], carry_1[207], carry[14], carry[78], carry[142]);
fulladd full1_316 (sum_1[208], carry_1[208], carry[15], carry[79], carry[143]);
fulladd full1_317 (sum_1[209], carry_1[209], carry[16], carry[80], carry[144]);
fulladd full1_318 (sum_1[210], carry_1[210], carry[17], carry[81], carry[145]);
fulladd full1_319 (sum_1[211], carry_1[211], carry[18], carry[82], carry[146]);
fulladd full1_320 (sum_1[212], carry_1[212], carry[19], carry[83], carry[147]);
fulladd full1_321 (sum_1[213], carry_1[213], carry[20], carry[84], carry[148]);
fulladd full1_322 (sum_1[214], carry_1[214], carry[21], carry[85], carry[149]);
fulladd full1_323 (sum_1[215], carry_1[215], carry[22], carry[86], carry[150]);
fulladd full1_324 (sum_1[216], carry_1[216], carry[23], carry[87], carry[151]);
fulladd full1_325 (sum_1[217], carry_1[217], carry[24], carry[88], carry[152]);
fulladd full1_326 (sum_1[218], carry_1[218], carry[25], carry[89], carry[153]);
fulladd full1_327 (sum_1[219], carry_1[219], carry[26], carry[90], carry[154]);
fulladd full1_328 (sum_1[220], carry_1[220], carry[27], carry[91], carry[155]);
fulladd full1_329 (sum_1[221], carry_1[221], carry[28], carry[92], carry[156]);
fulladd full1_330 (sum_1[222], carry_1[222], carry[29], carry[93], carry[157]);
fulladd full1_331 (sum_1[223], carry_1[223], carry[30], carry[94], carry[158]);
fulladd full1_332 (sum_1[224], carry_1[224], carry[31], carry[95], carry[159]);
fulladd full1_333 (sum_1[225], carry_1[225], carry[32], carry[96], carry[160]);
fulladd full1_334 (sum_1[226], carry_1[226], carry[33], carry[97], carry[161]);
fulladd full1_335 (sum_1[227], carry_1[227], carry[34], carry[98], carry[162]);
fulladd full1_336 (sum_1[228], carry_1[228], carry[35], carry[99], carry[163]);
fulladd full1_337 (sum_1[229], carry_1[229], carry[36], carry[100], carry[164]);
fulladd full1_338 (sum_1[230], carry_1[230], carry[37], carry[101], carry[165]);
fulladd full1_339 (sum_1[231], carry_1[231], carry[38], carry[102], carry[166]);
fulladd full1_340 (sum_1[232], carry_1[232], carry[39], carry[103], carry[167]);
fulladd full1_341 (sum_1[233], carry_1[233], carry[40], carry[104], carry[168]);
fulladd full1_342 (sum_1[234], carry_1[234], carry[41], carry[105], carry[169]);
fulladd full1_343 (sum_1[235], carry_1[235], carry[42], carry[106], carry[170]);
fulladd full1_344 (sum_1[236], carry_1[236], carry[43], carry[107], carry[171]);
fulladd full1_345 (sum_1[237], carry_1[237], carry[44], carry[108], carry[172]);
fulladd full1_346 (sum_1[238], carry_1[238], carry[45], carry[109], carry[173]);
fulladd full1_347 (sum_1[239], carry_1[239], carry[46], carry[110], carry[174]);
fulladd full1_348 (sum_1[240], carry_1[240], carry[47], carry[111], carry[175]);
fulladd full1_349 (sum_1[241], carry_1[241], carry[48], carry[112], carry[176]);
fulladd full1_350 (sum_1[242], carry_1[242], carry[49], carry[113], carry[177]);
fulladd full1_351 (sum_1[243], carry_1[243], carry[50], carry[114], carry[178]);
fulladd full1_352 (sum_1[244], carry_1[244], carry[51], carry[115], carry[179]);
fulladd full1_353 (sum_1[245], carry_1[245], carry[52], carry[116], carry[180]);
fulladd full1_354 (sum_1[246], carry_1[246], carry[53], carry[117], carry[181]);
fulladd full1_355 (sum_1[247], carry_1[247], carry[54], carry[118], carry[182]);
fulladd full1_356 (sum_1[248], carry_1[248], carry[55], carry[119], carry[183]);
fulladd full1_357 (sum_1[249], carry_1[249], carry[56], carry[120], carry[184]);
fulladd full1_358 (sum_1[250], carry_1[250], carry[57], carry[121], carry[185]);
fulladd full1_359 (sum_1[251], carry_1[251], carry[58], carry[122], carry[186]);
fulladd full1_360 (sum_1[252], carry_1[252], carry[59], carry[123], carry[187]);
fulladd full1_361 (sum_1[253], carry_1[253], carry[60], carry[124], carry[188]);
fulladd full1_362 (sum_1[254], carry_1[254], carry[61], carry[125], carry[189]);
fulladd full1_363 (sum_1[255], carry_1[255], carry[62], carry[126], carry[190]);
//carry3/4/5
fulladd full1_40 (sum_1[256], carry_1[256], 1'b0, 1'b0, 1'b0);
fulladd full1_41 (sum_1[257], carry_1[257], carry[192], carry[256], carry[320]);
fulladd full1_42 (sum_1[258], carry_1[258], carry[193], carry[257], carry[321]);
fulladd full1_43 (sum_1[259], carry_1[259], carry[194], carry[258], carry[322]);
fulladd full1_44 (sum_1[260], carry_1[260], carry[195], carry[259], carry[323]);
fulladd full1_45 (sum_1[261], carry_1[261], carry[196], carry[260], carry[324]);
fulladd full1_46 (sum_1[262], carry_1[262], carry[197], carry[261], carry[325]);
fulladd full1_47 (sum_1[263], carry_1[263], carry[198], carry[262], carry[326]);
fulladd full1_48 (sum_1[264], carry_1[264], carry[199], carry[263], carry[327]);
fulladd full1_49 (sum_1[265], carry_1[265], carry[200], carry[264], carry[328]);
fulladd full1_410 (sum_1[266], carry_1[266], carry[201], carry[265], carry[329]);
fulladd full1_411 (sum_1[267], carry_1[267], carry[202], carry[266], carry[330]);
fulladd full1_412 (sum_1[268], carry_1[268], carry[203], carry[267], carry[331]);
fulladd full1_413 (sum_1[269], carry_1[269], carry[204], carry[268], carry[332]);
fulladd full1_414 (sum_1[270], carry_1[270], carry[205], carry[269], carry[333]);
fulladd full1_415 (sum_1[271], carry_1[271], carry[206], carry[270], carry[334]);
fulladd full1_416 (sum_1[272], carry_1[272], carry[207], carry[271], carry[335]);
fulladd full1_417 (sum_1[273], carry_1[273], carry[208], carry[272], carry[336]);
fulladd full1_418 (sum_1[274], carry_1[274], carry[209], carry[273], carry[337]);
fulladd full1_419 (sum_1[275], carry_1[275], carry[210], carry[274], carry[338]);
fulladd full1_420 (sum_1[276], carry_1[276], carry[211], carry[275], carry[339]);
fulladd full1_421 (sum_1[277], carry_1[277], carry[212], carry[276], carry[340]);
fulladd full1_422 (sum_1[278], carry_1[278], carry[213], carry[277], carry[341]);
fulladd full1_423 (sum_1[279], carry_1[279], carry[214], carry[278], carry[342]);
fulladd full1_424 (sum_1[280], carry_1[280], carry[215], carry[279], carry[343]);
fulladd full1_425 (sum_1[281], carry_1[281], carry[216], carry[280], carry[344]);
fulladd full1_426 (sum_1[282], carry_1[282], carry[217], carry[281], carry[345]);
fulladd full1_427 (sum_1[283], carry_1[283], carry[218], carry[282], carry[346]);
fulladd full1_428 (sum_1[284], carry_1[284], carry[219], carry[283], carry[347]);
fulladd full1_429 (sum_1[285], carry_1[285], carry[220], carry[284], carry[348]);
fulladd full1_430 (sum_1[286], carry_1[286], carry[221], carry[285], carry[349]);
fulladd full1_431 (sum_1[287], carry_1[287], carry[222], carry[286], carry[350]);
fulladd full1_432 (sum_1[288], carry_1[288], carry[223], carry[287], carry[351]);
fulladd full1_433 (sum_1[289], carry_1[289], carry[224], carry[288], carry[352]);
fulladd full1_434 (sum_1[290], carry_1[290], carry[225], carry[289], carry[353]);
fulladd full1_435 (sum_1[291], carry_1[291], carry[226], carry[290], carry[354]);
fulladd full1_436 (sum_1[292], carry_1[292], carry[227], carry[291], carry[355]);
fulladd full1_437 (sum_1[293], carry_1[293], carry[228], carry[292], carry[356]);
fulladd full1_438 (sum_1[294], carry_1[294], carry[229], carry[293], carry[357]);
fulladd full1_439 (sum_1[295], carry_1[295], carry[230], carry[294], carry[358]);
fulladd full1_440 (sum_1[296], carry_1[296], carry[231], carry[295], carry[359]);
fulladd full1_441 (sum_1[297], carry_1[297], carry[232], carry[296], carry[360]);
fulladd full1_442 (sum_1[298], carry_1[298], carry[233], carry[297], carry[361]);
fulladd full1_443 (sum_1[299], carry_1[299], carry[234], carry[298], carry[362]);
fulladd full1_444 (sum_1[300], carry_1[300], carry[235], carry[299], carry[363]);
fulladd full1_445 (sum_1[301], carry_1[301], carry[236], carry[300], carry[364]);
fulladd full1_446 (sum_1[302], carry_1[302], carry[237], carry[301], carry[365]);
fulladd full1_447 (sum_1[303], carry_1[303], carry[238], carry[302], carry[366]);
fulladd full1_448 (sum_1[304], carry_1[304], carry[239], carry[303], carry[367]);
fulladd full1_449 (sum_1[305], carry_1[305], carry[240], carry[304], carry[368]);
fulladd full1_450 (sum_1[306], carry_1[306], carry[241], carry[305], carry[369]);
fulladd full1_451 (sum_1[307], carry_1[307], carry[242], carry[306], carry[370]);
fulladd full1_452 (sum_1[308], carry_1[308], carry[243], carry[307], carry[371]);
fulladd full1_453 (sum_1[309], carry_1[309], carry[244], carry[308], carry[372]);
fulladd full1_454 (sum_1[310], carry_1[310], carry[245], carry[309], carry[373]);
fulladd full1_455 (sum_1[311], carry_1[311], carry[246], carry[310], carry[374]);
fulladd full1_456 (sum_1[312], carry_1[312], carry[247], carry[311], carry[375]);
fulladd full1_457 (sum_1[313], carry_1[313], carry[248], carry[312], carry[376]);
fulladd full1_458 (sum_1[314], carry_1[314], carry[249], carry[313], carry[377]);
fulladd full1_459 (sum_1[315], carry_1[315], carry[250], carry[314], carry[378]);
fulladd full1_460 (sum_1[316], carry_1[316], carry[251], carry[315], carry[379]);
fulladd full1_461 (sum_1[317], carry_1[317], carry[252], carry[316], carry[380]);
fulladd full1_462 (sum_1[318], carry_1[318], carry[253], carry[317], carry[381]);
fulladd full1_463 (sum_1[319], carry_1[319], carry[254], carry[318], carry[382]);
//carry6/7/8/
fulladd full1_50 (sum_1[320], carry_1[320], 1'b0, 1'b0, 1'b0);
fulladd full1_51 (sum_1[321], carry_1[321], carry[384], carry[448], carry[512]);
fulladd full1_52 (sum_1[322], carry_1[322], carry[385], carry[449], carry[513]);
fulladd full1_53 (sum_1[323], carry_1[323], carry[386], carry[450], carry[514]);
fulladd full1_54 (sum_1[324], carry_1[324], carry[387], carry[451], carry[515]);
fulladd full1_55 (sum_1[325], carry_1[325], carry[388], carry[452], carry[516]);
fulladd full1_56 (sum_1[326], carry_1[326], carry[389], carry[453], carry[517]);
fulladd full1_57 (sum_1[327], carry_1[327], carry[390], carry[454], carry[518]);
fulladd full1_58 (sum_1[328], carry_1[328], carry[391], carry[455], carry[519]);
fulladd full1_59 (sum_1[329], carry_1[329], carry[392], carry[456], carry[520]);
fulladd full1_510 (sum_1[330], carry_1[330], carry[393], carry[457], carry[521]);
fulladd full1_511 (sum_1[331], carry_1[331], carry[394], carry[458], carry[522]);
fulladd full1_512 (sum_1[332], carry_1[332], carry[395], carry[459], carry[523]);
fulladd full1_513 (sum_1[333], carry_1[333], carry[396], carry[460], carry[524]);
fulladd full1_514 (sum_1[334], carry_1[334], carry[397], carry[461], carry[525]);
fulladd full1_515 (sum_1[335], carry_1[335], carry[398], carry[462], carry[526]);
fulladd full1_516 (sum_1[336], carry_1[336], carry[399], carry[463], carry[527]);
fulladd full1_517 (sum_1[337], carry_1[337], carry[400], carry[464], carry[528]);
fulladd full1_518 (sum_1[338], carry_1[338], carry[401], carry[465], carry[529]);
fulladd full1_519 (sum_1[339], carry_1[339], carry[402], carry[466], carry[530]);
fulladd full1_520 (sum_1[340], carry_1[340], carry[403], carry[467], carry[531]);
fulladd full1_521 (sum_1[341], carry_1[341], carry[404], carry[468], carry[532]);
fulladd full1_522 (sum_1[342], carry_1[342], carry[405], carry[469], carry[533]);
fulladd full1_523 (sum_1[343], carry_1[343], carry[406], carry[470], carry[534]);
fulladd full1_524 (sum_1[344], carry_1[344], carry[407], carry[471], carry[535]);
fulladd full1_525 (sum_1[345], carry_1[345], carry[408], carry[472], carry[536]);
fulladd full1_526 (sum_1[346], carry_1[346], carry[409], carry[473], carry[537]);
fulladd full1_527 (sum_1[347], carry_1[347], carry[410], carry[474], carry[538]);
fulladd full1_528 (sum_1[348], carry_1[348], carry[411], carry[475], carry[539]);
fulladd full1_529 (sum_1[349], carry_1[349], carry[412], carry[476], carry[540]);
fulladd full1_530 (sum_1[350], carry_1[350], carry[413], carry[477], carry[541]);
fulladd full1_531 (sum_1[351], carry_1[351], carry[414], carry[478], carry[542]);
fulladd full1_532 (sum_1[352], carry_1[352], carry[415], carry[479], carry[543]);
fulladd full1_533 (sum_1[353], carry_1[353], carry[416], carry[480], carry[544]);
fulladd full1_534 (sum_1[354], carry_1[354], carry[417], carry[481], carry[545]);
fulladd full1_535 (sum_1[355], carry_1[355], carry[418], carry[482], carry[546]);
fulladd full1_536 (sum_1[356], carry_1[356], carry[419], carry[483], carry[547]);
fulladd full1_537 (sum_1[357], carry_1[357], carry[420], carry[484], carry[548]);
fulladd full1_538 (sum_1[358], carry_1[358], carry[421], carry[485], carry[549]);
fulladd full1_539 (sum_1[359], carry_1[359], carry[422], carry[486], carry[550]);
fulladd full1_540 (sum_1[360], carry_1[360], carry[423], carry[487], carry[551]);
fulladd full1_541 (sum_1[361], carry_1[361], carry[424], carry[488], carry[552]);
fulladd full1_542 (sum_1[362], carry_1[362], carry[425], carry[489], carry[553]);
fulladd full1_543 (sum_1[363], carry_1[363], carry[426], carry[490], carry[554]);
fulladd full1_544 (sum_1[364], carry_1[364], carry[427], carry[491], carry[555]);
fulladd full1_545 (sum_1[365], carry_1[365], carry[428], carry[492], carry[556]);
fulladd full1_546 (sum_1[366], carry_1[366], carry[429], carry[493], carry[557]);
fulladd full1_547 (sum_1[367], carry_1[367], carry[430], carry[494], carry[558]);
fulladd full1_548 (sum_1[368], carry_1[368], carry[431], carry[495], carry[559]);
fulladd full1_549 (sum_1[369], carry_1[369], carry[432], carry[496], carry[560]);
fulladd full1_550 (sum_1[370], carry_1[370], carry[433], carry[497], carry[561]);
fulladd full1_551 (sum_1[371], carry_1[371], carry[434], carry[498], carry[562]);
fulladd full1_552 (sum_1[372], carry_1[372], carry[435], carry[499], carry[563]);
fulladd full1_553 (sum_1[373], carry_1[373], carry[436], carry[500], carry[564]);
fulladd full1_554 (sum_1[374], carry_1[374], carry[437], carry[501], carry[565]);
fulladd full1_555 (sum_1[375], carry_1[375], carry[438], carry[502], carry[566]);
fulladd full1_556 (sum_1[376], carry_1[376], carry[439], carry[503], carry[567]);
fulladd full1_557 (sum_1[377], carry_1[377], carry[440], carry[504], carry[568]);
fulladd full1_558 (sum_1[378], carry_1[378], carry[441], carry[505], carry[569]);
fulladd full1_559 (sum_1[379], carry_1[379], carry[442], carry[506], carry[570]);
fulladd full1_560 (sum_1[380], carry_1[380], carry[443], carry[507], carry[571]);
fulladd full1_561 (sum_1[381], carry_1[381], carry[444], carry[508], carry[572]);
fulladd full1_562 (sum_1[382], carry_1[382], carry[445], carry[509], carry[573]);
fulladd full1_563 (sum_1[383], carry_1[383], carry[446], carry[510], carry[574]);
//sum9/carry9/pp30
fulladd full1_60 (sum_1[384], carry_1[384], sum[576], 1'b0, 1'b0);
fulladd full1_61 (sum_1[385], carry_1[385], sum[577], carry[576], 1'b0);
fulladd full1_62 (sum_1[386], carry_1[386], sum[578], carry[577], 1'b0);
fulladd full1_63 (sum_1[387], carry_1[387], sum[579], carry[578], 1'b0);
fulladd full1_64 (sum_1[388], carry_1[388], sum[580], carry[579], 1'b0);
fulladd full1_65 (sum_1[389], carry_1[389], sum[581], carry[580], 1'b0);
fulladd full1_66 (sum_1[390], carry_1[390], sum[582], carry[581], 1'b0);
fulladd full1_67 (sum_1[391], carry_1[391], sum[583], carry[582], 1'b0);
fulladd full1_68 (sum_1[392], carry_1[392], sum[584], carry[583], 1'b0);
fulladd full1_69 (sum_1[393], carry_1[393], sum[585], carry[584], 1'b0);
fulladd full1_610 (sum_1[394], carry_1[394], sum[586], carry[585], 1'b0);
fulladd full1_611 (sum_1[395], carry_1[395], sum[587], carry[586], 1'b0);
fulladd full1_612 (sum_1[396], carry_1[396], sum[588], carry[587], 1'b0);
fulladd full1_613 (sum_1[397], carry_1[397], sum[589], carry[588], 1'b0);
fulladd full1_614 (sum_1[398], carry_1[398], sum[590], carry[589], 1'b0);
fulladd full1_615 (sum_1[399], carry_1[399], sum[591], carry[590], 1'b0);
fulladd full1_616 (sum_1[400], carry_1[400], sum[592], carry[591], 1'b0);
fulladd full1_617 (sum_1[401], carry_1[401], sum[593], carry[592], 1'b0);
fulladd full1_618 (sum_1[402], carry_1[402], sum[594], carry[593], 1'b0);
fulladd full1_619 (sum_1[403], carry_1[403], sum[595], carry[594], 1'b0);
fulladd full1_620 (sum_1[404], carry_1[404], sum[596], carry[595], 1'b0);
fulladd full1_621 (sum_1[405], carry_1[405], sum[597], carry[596], 1'b0);
fulladd full1_622 (sum_1[406], carry_1[406], sum[598], carry[597], 1'b0);
fulladd full1_623 (sum_1[407], carry_1[407], sum[599], carry[598], 1'b0);
fulladd full1_624 (sum_1[408], carry_1[408], sum[600], carry[599], 1'b0);
fulladd full1_625 (sum_1[409], carry_1[409], sum[601], carry[600], 1'b0);
fulladd full1_626 (sum_1[410], carry_1[410], sum[602], carry[601], 1'b0);
fulladd full1_627 (sum_1[411], carry_1[411], sum[603], carry[602], 1'b0);
fulladd full1_628 (sum_1[412], carry_1[412], sum[604], carry[603], 1'b0);
fulladd full1_629 (sum_1[413], carry_1[413], sum[605], carry[604], 1'b0);
fulladd full1_630 (sum_1[414], carry_1[414], sum[606], carry[605], C[960]);
fulladd full1_631 (sum_1[415], carry_1[415], sum[607], carry[606], C[961]);
fulladd full1_632 (sum_1[416], carry_1[416], sum[608], carry[607], C[962]);
fulladd full1_633 (sum_1[417], carry_1[417], sum[609], carry[608], C[963]);
fulladd full1_634 (sum_1[418], carry_1[418], sum[610], carry[609], C[964]);
fulladd full1_635 (sum_1[419], carry_1[419], sum[611], carry[610], C[965]);
fulladd full1_636 (sum_1[420], carry_1[420], sum[612], carry[611], C[966]);
fulladd full1_637 (sum_1[421], carry_1[421], sum[613], carry[612], C[967]);
fulladd full1_638 (sum_1[422], carry_1[422], sum[614], carry[613], C[968]);
fulladd full1_639 (sum_1[423], carry_1[423], sum[615], carry[614], C[969]);
fulladd full1_640 (sum_1[424], carry_1[424], sum[616], carry[615], C[970]);
fulladd full1_641 (sum_1[425], carry_1[425], sum[617], carry[616], C[971]);
fulladd full1_642 (sum_1[426], carry_1[426], sum[618], carry[617], C[972]);
fulladd full1_643 (sum_1[427], carry_1[427], sum[619], carry[618], C[973]);
fulladd full1_644 (sum_1[428], carry_1[428], sum[620], carry[619], C[974]);
fulladd full1_645 (sum_1[429], carry_1[429], sum[621], carry[620], C[975]);
fulladd full1_646 (sum_1[430], carry_1[430], sum[622], carry[621], C[976]);
fulladd full1_647 (sum_1[431], carry_1[431], sum[623], carry[622], C[977]);
fulladd full1_648 (sum_1[432], carry_1[432], sum[624], carry[623], C[978]);
fulladd full1_649 (sum_1[433], carry_1[433], sum[625], carry[624], C[979]);
fulladd full1_650 (sum_1[434], carry_1[434], sum[626], carry[625], C[980]);
fulladd full1_651 (sum_1[435], carry_1[435], sum[627], carry[626], C[981]);
fulladd full1_652 (sum_1[436], carry_1[436], sum[628], carry[627], C[982]);
fulladd full1_653 (sum_1[437], carry_1[437], sum[629], carry[628], C[983]);
fulladd full1_654 (sum_1[438], carry_1[438], sum[630], carry[629], C[984]);
fulladd full1_655 (sum_1[439], carry_1[439], sum[631], carry[630], C[985]);
fulladd full1_656 (sum_1[440], carry_1[440], sum[632], carry[631], C[986]);
fulladd full1_657 (sum_1[441], carry_1[441], sum[633], carry[632], C[987]);
fulladd full1_658 (sum_1[442], carry_1[442], sum[634], carry[633], C[988]);
fulladd full1_659 (sum_1[443], carry_1[443], sum[635], carry[634], C[989]);
fulladd full1_660 (sum_1[444], carry_1[444], sum[636], carry[635], C[990]);
fulladd full1_661 (sum_1[445], carry_1[445], sum[637], carry[636], C[991]);
fulladd full1_662 (sum_1[446], carry_1[446], sum[638], carry[637], C[991]);
fulladd full1_663 (sum_1[447], carry_1[447], sum[639], carry[638], C[991]);
//sum_1/0/1/2
fulladd full2_00 (sum_2[0], carry_2[0], sum_1[0], sum_1[64], sum_1[128]);
fulladd full2_01 (sum_2[1], carry_2[1], sum_1[1], sum_1[65], sum_1[129]);
fulladd full2_02 (sum_2[2], carry_2[2], sum_1[2], sum_1[66], sum_1[130]);
fulladd full2_03 (sum_2[3], carry_2[3], sum_1[3], sum_1[67], sum_1[131]);
fulladd full2_04 (sum_2[4], carry_2[4], sum_1[4], sum_1[68], sum_1[132]);
fulladd full2_05 (sum_2[5], carry_2[5], sum_1[5], sum_1[69], sum_1[133]);
fulladd full2_06 (sum_2[6], carry_2[6], sum_1[6], sum_1[70], sum_1[134]);
fulladd full2_07 (sum_2[7], carry_2[7], sum_1[7], sum_1[71], sum_1[135]);
fulladd full2_08 (sum_2[8], carry_2[8], sum_1[8], sum_1[72], sum_1[136]);
fulladd full2_09 (sum_2[9], carry_2[9], sum_1[9], sum_1[73], sum_1[137]);
fulladd full2_010 (sum_2[10], carry_2[10], sum_1[10], sum_1[74], sum_1[138]);
fulladd full2_011 (sum_2[11], carry_2[11], sum_1[11], sum_1[75], sum_1[139]);
fulladd full2_012 (sum_2[12], carry_2[12], sum_1[12], sum_1[76], sum_1[140]);
fulladd full2_013 (sum_2[13], carry_2[13], sum_1[13], sum_1[77], sum_1[141]);
fulladd full2_014 (sum_2[14], carry_2[14], sum_1[14], sum_1[78], sum_1[142]);
fulladd full2_015 (sum_2[15], carry_2[15], sum_1[15], sum_1[79], sum_1[143]);
fulladd full2_016 (sum_2[16], carry_2[16], sum_1[16], sum_1[80], sum_1[144]);
fulladd full2_017 (sum_2[17], carry_2[17], sum_1[17], sum_1[81], sum_1[145]);
fulladd full2_018 (sum_2[18], carry_2[18], sum_1[18], sum_1[82], sum_1[146]);
fulladd full2_019 (sum_2[19], carry_2[19], sum_1[19], sum_1[83], sum_1[147]);
fulladd full2_020 (sum_2[20], carry_2[20], sum_1[20], sum_1[84], sum_1[148]);
fulladd full2_021 (sum_2[21], carry_2[21], sum_1[21], sum_1[85], sum_1[149]);
fulladd full2_022 (sum_2[22], carry_2[22], sum_1[22], sum_1[86], sum_1[150]);
fulladd full2_023 (sum_2[23], carry_2[23], sum_1[23], sum_1[87], sum_1[151]);
fulladd full2_024 (sum_2[24], carry_2[24], sum_1[24], sum_1[88], sum_1[152]);
fulladd full2_025 (sum_2[25], carry_2[25], sum_1[25], sum_1[89], sum_1[153]);
fulladd full2_026 (sum_2[26], carry_2[26], sum_1[26], sum_1[90], sum_1[154]);
fulladd full2_027 (sum_2[27], carry_2[27], sum_1[27], sum_1[91], sum_1[155]);
fulladd full2_028 (sum_2[28], carry_2[28], sum_1[28], sum_1[92], sum_1[156]);
fulladd full2_029 (sum_2[29], carry_2[29], sum_1[29], sum_1[93], sum_1[157]);
fulladd full2_030 (sum_2[30], carry_2[30], sum_1[30], sum_1[94], sum_1[158]);
fulladd full2_031 (sum_2[31], carry_2[31], sum_1[31], sum_1[95], sum_1[159]);
fulladd full2_032 (sum_2[32], carry_2[32], sum_1[32], sum_1[96], sum_1[160]);
fulladd full2_033 (sum_2[33], carry_2[33], sum_1[33], sum_1[97], sum_1[161]);
fulladd full2_034 (sum_2[34], carry_2[34], sum_1[34], sum_1[98], sum_1[162]);
fulladd full2_035 (sum_2[35], carry_2[35], sum_1[35], sum_1[99], sum_1[163]);
fulladd full2_036 (sum_2[36], carry_2[36], sum_1[36], sum_1[100], sum_1[164]);
fulladd full2_037 (sum_2[37], carry_2[37], sum_1[37], sum_1[101], sum_1[165]);
fulladd full2_038 (sum_2[38], carry_2[38], sum_1[38], sum_1[102], sum_1[166]);
fulladd full2_039 (sum_2[39], carry_2[39], sum_1[39], sum_1[103], sum_1[167]);
fulladd full2_040 (sum_2[40], carry_2[40], sum_1[40], sum_1[104], sum_1[168]);
fulladd full2_041 (sum_2[41], carry_2[41], sum_1[41], sum_1[105], sum_1[169]);
fulladd full2_042 (sum_2[42], carry_2[42], sum_1[42], sum_1[106], sum_1[170]);
fulladd full2_043 (sum_2[43], carry_2[43], sum_1[43], sum_1[107], sum_1[171]);
fulladd full2_044 (sum_2[44], carry_2[44], sum_1[44], sum_1[108], sum_1[172]);
fulladd full2_045 (sum_2[45], carry_2[45], sum_1[45], sum_1[109], sum_1[173]);
fulladd full2_046 (sum_2[46], carry_2[46], sum_1[46], sum_1[110], sum_1[174]);
fulladd full2_047 (sum_2[47], carry_2[47], sum_1[47], sum_1[111], sum_1[175]);
fulladd full2_048 (sum_2[48], carry_2[48], sum_1[48], sum_1[112], sum_1[176]);
fulladd full2_049 (sum_2[49], carry_2[49], sum_1[49], sum_1[113], sum_1[177]);
fulladd full2_050 (sum_2[50], carry_2[50], sum_1[50], sum_1[114], sum_1[178]);
fulladd full2_051 (sum_2[51], carry_2[51], sum_1[51], sum_1[115], sum_1[179]);
fulladd full2_052 (sum_2[52], carry_2[52], sum_1[52], sum_1[116], sum_1[180]);
fulladd full2_053 (sum_2[53], carry_2[53], sum_1[53], sum_1[117], sum_1[181]);
fulladd full2_054 (sum_2[54], carry_2[54], sum_1[54], sum_1[118], sum_1[182]);
fulladd full2_055 (sum_2[55], carry_2[55], sum_1[55], sum_1[119], sum_1[183]);
fulladd full2_056 (sum_2[56], carry_2[56], sum_1[56], sum_1[120], sum_1[184]);
fulladd full2_057 (sum_2[57], carry_2[57], sum_1[57], sum_1[121], sum_1[185]);
fulladd full2_058 (sum_2[58], carry_2[58], sum_1[58], sum_1[122], sum_1[186]);
fulladd full2_059 (sum_2[59], carry_2[59], sum_1[59], sum_1[123], sum_1[187]);
fulladd full2_060 (sum_2[60], carry_2[60], sum_1[60], sum_1[124], sum_1[188]);
fulladd full2_061 (sum_2[61], carry_2[61], sum_1[61], sum_1[125], sum_1[189]);
fulladd full2_062 (sum_2[62], carry_2[62], sum_1[62], sum_1[126], sum_1[190]);
fulladd full2_063 (sum_2[63], carry_2[63], sum_1[63], sum_1[127], sum_1[191]);
//sum_1/3/4/5
fulladd full2_10 (sum_2[64], carry_2[64], sum_1[192], sum_1[256], sum_1[320]);
fulladd full2_11 (sum_2[65], carry_2[65], sum_1[193], sum_1[257], sum_1[321]);
fulladd full2_12 (sum_2[66], carry_2[66], sum_1[194], sum_1[258], sum_1[322]);
fulladd full2_13 (sum_2[67], carry_2[67], sum_1[195], sum_1[259], sum_1[323]);
fulladd full2_14 (sum_2[68], carry_2[68], sum_1[196], sum_1[260], sum_1[324]);
fulladd full2_15 (sum_2[69], carry_2[69], sum_1[197], sum_1[261], sum_1[325]);
fulladd full2_16 (sum_2[70], carry_2[70], sum_1[198], sum_1[262], sum_1[326]);
fulladd full2_17 (sum_2[71], carry_2[71], sum_1[199], sum_1[263], sum_1[327]);
fulladd full2_18 (sum_2[72], carry_2[72], sum_1[200], sum_1[264], sum_1[328]);
fulladd full2_19 (sum_2[73], carry_2[73], sum_1[201], sum_1[265], sum_1[329]);
fulladd full2_110 (sum_2[74], carry_2[74], sum_1[202], sum_1[266], sum_1[330]);
fulladd full2_111 (sum_2[75], carry_2[75], sum_1[203], sum_1[267], sum_1[331]);
fulladd full2_112 (sum_2[76], carry_2[76], sum_1[204], sum_1[268], sum_1[332]);
fulladd full2_113 (sum_2[77], carry_2[77], sum_1[205], sum_1[269], sum_1[333]);
fulladd full2_114 (sum_2[78], carry_2[78], sum_1[206], sum_1[270], sum_1[334]);
fulladd full2_115 (sum_2[79], carry_2[79], sum_1[207], sum_1[271], sum_1[335]);
fulladd full2_116 (sum_2[80], carry_2[80], sum_1[208], sum_1[272], sum_1[336]);
fulladd full2_117 (sum_2[81], carry_2[81], sum_1[209], sum_1[273], sum_1[337]);
fulladd full2_118 (sum_2[82], carry_2[82], sum_1[210], sum_1[274], sum_1[338]);
fulladd full2_119 (sum_2[83], carry_2[83], sum_1[211], sum_1[275], sum_1[339]);
fulladd full2_120 (sum_2[84], carry_2[84], sum_1[212], sum_1[276], sum_1[340]);
fulladd full2_121 (sum_2[85], carry_2[85], sum_1[213], sum_1[277], sum_1[341]);
fulladd full2_122 (sum_2[86], carry_2[86], sum_1[214], sum_1[278], sum_1[342]);
fulladd full2_123 (sum_2[87], carry_2[87], sum_1[215], sum_1[279], sum_1[343]);
fulladd full2_124 (sum_2[88], carry_2[88], sum_1[216], sum_1[280], sum_1[344]);
fulladd full2_125 (sum_2[89], carry_2[89], sum_1[217], sum_1[281], sum_1[345]);
fulladd full2_126 (sum_2[90], carry_2[90], sum_1[218], sum_1[282], sum_1[346]);
fulladd full2_127 (sum_2[91], carry_2[91], sum_1[219], sum_1[283], sum_1[347]);
fulladd full2_128 (sum_2[92], carry_2[92], sum_1[220], sum_1[284], sum_1[348]);
fulladd full2_129 (sum_2[93], carry_2[93], sum_1[221], sum_1[285], sum_1[349]);
fulladd full2_130 (sum_2[94], carry_2[94], sum_1[222], sum_1[286], sum_1[350]);
fulladd full2_131 (sum_2[95], carry_2[95], sum_1[223], sum_1[287], sum_1[351]);
fulladd full2_132 (sum_2[96], carry_2[96], sum_1[224], sum_1[288], sum_1[352]);
fulladd full2_133 (sum_2[97], carry_2[97], sum_1[225], sum_1[289], sum_1[353]);
fulladd full2_134 (sum_2[98], carry_2[98], sum_1[226], sum_1[290], sum_1[354]);
fulladd full2_135 (sum_2[99], carry_2[99], sum_1[227], sum_1[291], sum_1[355]);
fulladd full2_136 (sum_2[100], carry_2[100], sum_1[228], sum_1[292], sum_1[356]);
fulladd full2_137 (sum_2[101], carry_2[101], sum_1[229], sum_1[293], sum_1[357]);
fulladd full2_138 (sum_2[102], carry_2[102], sum_1[230], sum_1[294], sum_1[358]);
fulladd full2_139 (sum_2[103], carry_2[103], sum_1[231], sum_1[295], sum_1[359]);
fulladd full2_140 (sum_2[104], carry_2[104], sum_1[232], sum_1[296], sum_1[360]);
fulladd full2_141 (sum_2[105], carry_2[105], sum_1[233], sum_1[297], sum_1[361]);
fulladd full2_142 (sum_2[106], carry_2[106], sum_1[234], sum_1[298], sum_1[362]);
fulladd full2_143 (sum_2[107], carry_2[107], sum_1[235], sum_1[299], sum_1[363]);
fulladd full2_144 (sum_2[108], carry_2[108], sum_1[236], sum_1[300], sum_1[364]);
fulladd full2_145 (sum_2[109], carry_2[109], sum_1[237], sum_1[301], sum_1[365]);
fulladd full2_146 (sum_2[110], carry_2[110], sum_1[238], sum_1[302], sum_1[366]);
fulladd full2_147 (sum_2[111], carry_2[111], sum_1[239], sum_1[303], sum_1[367]);
fulladd full2_148 (sum_2[112], carry_2[112], sum_1[240], sum_1[304], sum_1[368]);
fulladd full2_149 (sum_2[113], carry_2[113], sum_1[241], sum_1[305], sum_1[369]);
fulladd full2_150 (sum_2[114], carry_2[114], sum_1[242], sum_1[306], sum_1[370]);
fulladd full2_151 (sum_2[115], carry_2[115], sum_1[243], sum_1[307], sum_1[371]);
fulladd full2_152 (sum_2[116], carry_2[116], sum_1[244], sum_1[308], sum_1[372]);
fulladd full2_153 (sum_2[117], carry_2[117], sum_1[245], sum_1[309], sum_1[373]);
fulladd full2_154 (sum_2[118], carry_2[118], sum_1[246], sum_1[310], sum_1[374]);
fulladd full2_155 (sum_2[119], carry_2[119], sum_1[247], sum_1[311], sum_1[375]);
fulladd full2_156 (sum_2[120], carry_2[120], sum_1[248], sum_1[312], sum_1[376]);
fulladd full2_157 (sum_2[121], carry_2[121], sum_1[249], sum_1[313], sum_1[377]);
fulladd full2_158 (sum_2[122], carry_2[122], sum_1[250], sum_1[314], sum_1[378]);
fulladd full2_159 (sum_2[123], carry_2[123], sum_1[251], sum_1[315], sum_1[379]);
fulladd full2_160 (sum_2[124], carry_2[124], sum_1[252], sum_1[316], sum_1[380]);
fulladd full2_161 (sum_2[125], carry_2[125], sum_1[253], sum_1[317], sum_1[381]);
fulladd full2_162 (sum_2[126], carry_2[126], sum_1[254], sum_1[318], sum_1[382]);
fulladd full2_163 (sum_2[127], carry_2[127], sum_1[255], sum_1[319], sum_1[383]);
//carry_1/0/1/2
fulladd full2_20 (sum_2[128], carry_2[128], 1'b0, 1'b0, 1'b0);
fulladd full2_21 (sum_2[129], carry_2[129], carry_1[0], carry_1[64], carry_1[128]);
fulladd full2_22 (sum_2[130], carry_2[130], carry_1[1], carry_1[65], carry_1[129]);
fulladd full2_23 (sum_2[131], carry_2[131], carry_1[2], carry_1[66], carry_1[130]);
fulladd full2_24 (sum_2[132], carry_2[132], carry_1[3], carry_1[67], carry_1[131]);
fulladd full2_25 (sum_2[133], carry_2[133], carry_1[4], carry_1[68], carry_1[132]);
fulladd full2_26 (sum_2[134], carry_2[134], carry_1[5], carry_1[69], carry_1[133]);
fulladd full2_27 (sum_2[135], carry_2[135], carry_1[6], carry_1[70], carry_1[134]);
fulladd full2_28 (sum_2[136], carry_2[136], carry_1[7], carry_1[71], carry_1[135]);
fulladd full2_29 (sum_2[137], carry_2[137], carry_1[8], carry_1[72], carry_1[136]);
fulladd full2_210 (sum_2[138], carry_2[138], carry_1[9], carry_1[73], carry_1[137]);
fulladd full2_211 (sum_2[139], carry_2[139], carry_1[10], carry_1[74], carry_1[138]);
fulladd full2_212 (sum_2[140], carry_2[140], carry_1[11], carry_1[75], carry_1[139]);
fulladd full2_213 (sum_2[141], carry_2[141], carry_1[12], carry_1[76], carry_1[140]);
fulladd full2_214 (sum_2[142], carry_2[142], carry_1[13], carry_1[77], carry_1[141]);
fulladd full2_215 (sum_2[143], carry_2[143], carry_1[14], carry_1[78], carry_1[142]);
fulladd full2_216 (sum_2[144], carry_2[144], carry_1[15], carry_1[79], carry_1[143]);
fulladd full2_217 (sum_2[145], carry_2[145], carry_1[16], carry_1[80], carry_1[144]);
fulladd full2_218 (sum_2[146], carry_2[146], carry_1[17], carry_1[81], carry_1[145]);
fulladd full2_219 (sum_2[147], carry_2[147], carry_1[18], carry_1[82], carry_1[146]);
fulladd full2_220 (sum_2[148], carry_2[148], carry_1[19], carry_1[83], carry_1[147]);
fulladd full2_221 (sum_2[149], carry_2[149], carry_1[20], carry_1[84], carry_1[148]);
fulladd full2_222 (sum_2[150], carry_2[150], carry_1[21], carry_1[85], carry_1[149]);
fulladd full2_223 (sum_2[151], carry_2[151], carry_1[22], carry_1[86], carry_1[150]);
fulladd full2_224 (sum_2[152], carry_2[152], carry_1[23], carry_1[87], carry_1[151]);
fulladd full2_225 (sum_2[153], carry_2[153], carry_1[24], carry_1[88], carry_1[152]);
fulladd full2_226 (sum_2[154], carry_2[154], carry_1[25], carry_1[89], carry_1[153]);
fulladd full2_227 (sum_2[155], carry_2[155], carry_1[26], carry_1[90], carry_1[154]);
fulladd full2_228 (sum_2[156], carry_2[156], carry_1[27], carry_1[91], carry_1[155]);
fulladd full2_229 (sum_2[157], carry_2[157], carry_1[28], carry_1[92], carry_1[156]);
fulladd full2_230 (sum_2[158], carry_2[158], carry_1[29], carry_1[93], carry_1[157]);
fulladd full2_231 (sum_2[159], carry_2[159], carry_1[30], carry_1[94], carry_1[158]);
fulladd full2_232 (sum_2[160], carry_2[160], carry_1[31], carry_1[95], carry_1[159]);
fulladd full2_233 (sum_2[161], carry_2[161], carry_1[32], carry_1[96], carry_1[160]);
fulladd full2_234 (sum_2[162], carry_2[162], carry_1[33], carry_1[97], carry_1[161]);
fulladd full2_235 (sum_2[163], carry_2[163], carry_1[34], carry_1[98], carry_1[162]);
fulladd full2_236 (sum_2[164], carry_2[164], carry_1[35], carry_1[99], carry_1[163]);
fulladd full2_237 (sum_2[165], carry_2[165], carry_1[36], carry_1[100], carry_1[164]);
fulladd full2_238 (sum_2[166], carry_2[166], carry_1[37], carry_1[101], carry_1[165]);
fulladd full2_239 (sum_2[167], carry_2[167], carry_1[38], carry_1[102], carry_1[166]);
fulladd full2_240 (sum_2[168], carry_2[168], carry_1[39], carry_1[103], carry_1[167]);
fulladd full2_241 (sum_2[169], carry_2[169], carry_1[40], carry_1[104], carry_1[168]);
fulladd full2_242 (sum_2[170], carry_2[170], carry_1[41], carry_1[105], carry_1[169]);
fulladd full2_243 (sum_2[171], carry_2[171], carry_1[42], carry_1[106], carry_1[170]);
fulladd full2_244 (sum_2[172], carry_2[172], carry_1[43], carry_1[107], carry_1[171]);
fulladd full2_245 (sum_2[173], carry_2[173], carry_1[44], carry_1[108], carry_1[172]);
fulladd full2_246 (sum_2[174], carry_2[174], carry_1[45], carry_1[109], carry_1[173]);
fulladd full2_247 (sum_2[175], carry_2[175], carry_1[46], carry_1[110], carry_1[174]);
fulladd full2_248 (sum_2[176], carry_2[176], carry_1[47], carry_1[111], carry_1[175]);
fulladd full2_249 (sum_2[177], carry_2[177], carry_1[48], carry_1[112], carry_1[176]);
fulladd full2_250 (sum_2[178], carry_2[178], carry_1[49], carry_1[113], carry_1[177]);
fulladd full2_251 (sum_2[179], carry_2[179], carry_1[50], carry_1[114], carry_1[178]);
fulladd full2_252 (sum_2[180], carry_2[180], carry_1[51], carry_1[115], carry_1[179]);
fulladd full2_253 (sum_2[181], carry_2[181], carry_1[52], carry_1[116], carry_1[180]);
fulladd full2_254 (sum_2[182], carry_2[182], carry_1[53], carry_1[117], carry_1[181]);
fulladd full2_255 (sum_2[183], carry_2[183], carry_1[54], carry_1[118], carry_1[182]);
fulladd full2_256 (sum_2[184], carry_2[184], carry_1[55], carry_1[119], carry_1[183]);
fulladd full2_257 (sum_2[185], carry_2[185], carry_1[56], carry_1[120], carry_1[184]);
fulladd full2_258 (sum_2[186], carry_2[186], carry_1[57], carry_1[121], carry_1[185]);
fulladd full2_259 (sum_2[187], carry_2[187], carry_1[58], carry_1[122], carry_1[186]);
fulladd full2_260 (sum_2[188], carry_2[188], carry_1[59], carry_1[123], carry_1[187]);
fulladd full2_261 (sum_2[189], carry_2[189], carry_1[60], carry_1[124], carry_1[188]);
fulladd full2_262 (sum_2[190], carry_2[190], carry_1[61], carry_1[125], carry_1[189]);
fulladd full2_263 (sum_2[191], carry_2[191], carry_1[62], carry_1[126], carry_1[190]);
//carry_1/3/4/5
fulladd full2_30 (sum_2[192], carry_2[192], 1'b0, 1'b0, 1'b0);
fulladd full2_31 (sum_2[193], carry_2[193], carry_1[192], carry_1[256], carry_1[320]);
fulladd full2_32 (sum_2[194], carry_2[194], carry_1[193], carry_1[257], carry_1[321]);
fulladd full2_33 (sum_2[195], carry_2[195], carry_1[194], carry_1[258], carry_1[322]);
fulladd full2_34 (sum_2[196], carry_2[196], carry_1[195], carry_1[259], carry_1[323]);
fulladd full2_35 (sum_2[197], carry_2[197], carry_1[196], carry_1[260], carry_1[324]);
fulladd full2_36 (sum_2[198], carry_2[198], carry_1[197], carry_1[261], carry_1[325]);
fulladd full2_37 (sum_2[199], carry_2[199], carry_1[198], carry_1[262], carry_1[326]);
fulladd full2_38 (sum_2[200], carry_2[200], carry_1[199], carry_1[263], carry_1[327]);
fulladd full2_39 (sum_2[201], carry_2[201], carry_1[200], carry_1[264], carry_1[328]);
fulladd full2_310 (sum_2[202], carry_2[202], carry_1[201], carry_1[265], carry_1[329]);
fulladd full2_311 (sum_2[203], carry_2[203], carry_1[202], carry_1[266], carry_1[330]);
fulladd full2_312 (sum_2[204], carry_2[204], carry_1[203], carry_1[267], carry_1[331]);
fulladd full2_313 (sum_2[205], carry_2[205], carry_1[204], carry_1[268], carry_1[332]);
fulladd full2_314 (sum_2[206], carry_2[206], carry_1[205], carry_1[269], carry_1[333]);
fulladd full2_315 (sum_2[207], carry_2[207], carry_1[206], carry_1[270], carry_1[334]);
fulladd full2_316 (sum_2[208], carry_2[208], carry_1[207], carry_1[271], carry_1[335]);
fulladd full2_317 (sum_2[209], carry_2[209], carry_1[208], carry_1[272], carry_1[336]);
fulladd full2_318 (sum_2[210], carry_2[210], carry_1[209], carry_1[273], carry_1[337]);
fulladd full2_319 (sum_2[211], carry_2[211], carry_1[210], carry_1[274], carry_1[338]);
fulladd full2_320 (sum_2[212], carry_2[212], carry_1[211], carry_1[275], carry_1[339]);
fulladd full2_321 (sum_2[213], carry_2[213], carry_1[212], carry_1[276], carry_1[340]);
fulladd full2_322 (sum_2[214], carry_2[214], carry_1[213], carry_1[277], carry_1[341]);
fulladd full2_323 (sum_2[215], carry_2[215], carry_1[214], carry_1[278], carry_1[342]);
fulladd full2_324 (sum_2[216], carry_2[216], carry_1[215], carry_1[279], carry_1[343]);
fulladd full2_325 (sum_2[217], carry_2[217], carry_1[216], carry_1[280], carry_1[344]);
fulladd full2_326 (sum_2[218], carry_2[218], carry_1[217], carry_1[281], carry_1[345]);
fulladd full2_327 (sum_2[219], carry_2[219], carry_1[218], carry_1[282], carry_1[346]);
fulladd full2_328 (sum_2[220], carry_2[220], carry_1[219], carry_1[283], carry_1[347]);
fulladd full2_329 (sum_2[221], carry_2[221], carry_1[220], carry_1[284], carry_1[348]);
fulladd full2_330 (sum_2[222], carry_2[222], carry_1[221], carry_1[285], carry_1[349]);
fulladd full2_331 (sum_2[223], carry_2[223], carry_1[222], carry_1[286], carry_1[350]);
fulladd full2_332 (sum_2[224], carry_2[224], carry_1[223], carry_1[287], carry_1[351]);
fulladd full2_333 (sum_2[225], carry_2[225], carry_1[224], carry_1[288], carry_1[352]);
fulladd full2_334 (sum_2[226], carry_2[226], carry_1[225], carry_1[289], carry_1[353]);
fulladd full2_335 (sum_2[227], carry_2[227], carry_1[226], carry_1[290], carry_1[354]);
fulladd full2_336 (sum_2[228], carry_2[228], carry_1[227], carry_1[291], carry_1[355]);
fulladd full2_337 (sum_2[229], carry_2[229], carry_1[228], carry_1[292], carry_1[356]);
fulladd full2_338 (sum_2[230], carry_2[230], carry_1[229], carry_1[293], carry_1[357]);
fulladd full2_339 (sum_2[231], carry_2[231], carry_1[230], carry_1[294], carry_1[358]);
fulladd full2_340 (sum_2[232], carry_2[232], carry_1[231], carry_1[295], carry_1[359]);
fulladd full2_341 (sum_2[233], carry_2[233], carry_1[232], carry_1[296], carry_1[360]);
fulladd full2_342 (sum_2[234], carry_2[234], carry_1[233], carry_1[297], carry_1[361]);
fulladd full2_343 (sum_2[235], carry_2[235], carry_1[234], carry_1[298], carry_1[362]);
fulladd full2_344 (sum_2[236], carry_2[236], carry_1[235], carry_1[299], carry_1[363]);
fulladd full2_345 (sum_2[237], carry_2[237], carry_1[236], carry_1[300], carry_1[364]);
fulladd full2_346 (sum_2[238], carry_2[238], carry_1[237], carry_1[301], carry_1[365]);
fulladd full2_347 (sum_2[239], carry_2[239], carry_1[238], carry_1[302], carry_1[366]);
fulladd full2_348 (sum_2[240], carry_2[240], carry_1[239], carry_1[303], carry_1[367]);
fulladd full2_349 (sum_2[241], carry_2[241], carry_1[240], carry_1[304], carry_1[368]);
fulladd full2_350 (sum_2[242], carry_2[242], carry_1[241], carry_1[305], carry_1[369]);
fulladd full2_351 (sum_2[243], carry_2[243], carry_1[242], carry_1[306], carry_1[370]);
fulladd full2_352 (sum_2[244], carry_2[244], carry_1[243], carry_1[307], carry_1[371]);
fulladd full2_353 (sum_2[245], carry_2[245], carry_1[244], carry_1[308], carry_1[372]);
fulladd full2_354 (sum_2[246], carry_2[246], carry_1[245], carry_1[309], carry_1[373]);
fulladd full2_355 (sum_2[247], carry_2[247], carry_1[246], carry_1[310], carry_1[374]);
fulladd full2_356 (sum_2[248], carry_2[248], carry_1[247], carry_1[311], carry_1[375]);
fulladd full2_357 (sum_2[249], carry_2[249], carry_1[248], carry_1[312], carry_1[376]);
fulladd full2_358 (sum_2[250], carry_2[250], carry_1[249], carry_1[313], carry_1[377]);
fulladd full2_359 (sum_2[251], carry_2[251], carry_1[250], carry_1[314], carry_1[378]);
fulladd full2_360 (sum_2[252], carry_2[252], carry_1[251], carry_1[315], carry_1[379]);
fulladd full2_361 (sum_2[253], carry_2[253], carry_1[252], carry_1[316], carry_1[380]);
fulladd full2_362 (sum_2[254], carry_2[254], carry_1[253], carry_1[317], carry_1[381]);
fulladd full2_363 (sum_2[255], carry_2[255], carry_1[254], carry_1[318], carry_1[382]);
//sum_1/6.carry_1/6.pp31
fulladd full2_40 (sum_2[256], carry_2[256], sum_1[384], 1'b0, 1'b0);
fulladd full2_41 (sum_2[257], carry_2[257], sum_1[385], carry_1[384], 1'b0);
fulladd full2_42 (sum_2[258], carry_2[258], sum_1[386], carry_1[385], 1'b0);
fulladd full2_43 (sum_2[259], carry_2[259], sum_1[387], carry_1[386], 1'b0);
fulladd full2_44 (sum_2[260], carry_2[260], sum_1[388], carry_1[387], 1'b0);
fulladd full2_45 (sum_2[261], carry_2[261], sum_1[389], carry_1[388], 1'b0);
fulladd full2_46 (sum_2[262], carry_2[262], sum_1[390], carry_1[389], 1'b0);
fulladd full2_47 (sum_2[263], carry_2[263], sum_1[391], carry_1[390], 1'b0);
fulladd full2_48 (sum_2[264], carry_2[264], sum_1[392], carry_1[391], 1'b0);
fulladd full2_49 (sum_2[265], carry_2[265], sum_1[393], carry_1[392], 1'b0);
fulladd full2_410 (sum_2[266], carry_2[266], sum_1[394], carry_1[393], 1'b0);
fulladd full2_411 (sum_2[267], carry_2[267], sum_1[395], carry_1[394], 1'b0);
fulladd full2_412 (sum_2[268], carry_2[268], sum_1[396], carry_1[395], 1'b0);
fulladd full2_413 (sum_2[269], carry_2[269], sum_1[397], carry_1[396], 1'b0);
fulladd full2_414 (sum_2[270], carry_2[270], sum_1[398], carry_1[397], 1'b0);
fulladd full2_415 (sum_2[271], carry_2[271], sum_1[399], carry_1[398], 1'b0);
fulladd full2_416 (sum_2[272], carry_2[272], sum_1[400], carry_1[399], 1'b0);
fulladd full2_417 (sum_2[273], carry_2[273], sum_1[401], carry_1[400], 1'b0);
fulladd full2_418 (sum_2[274], carry_2[274], sum_1[402], carry_1[401], 1'b0);
fulladd full2_419 (sum_2[275], carry_2[275], sum_1[403], carry_1[402], 1'b0);
fulladd full2_420 (sum_2[276], carry_2[276], sum_1[404], carry_1[403], 1'b0);
fulladd full2_421 (sum_2[277], carry_2[277], sum_1[405], carry_1[404], 1'b0);
fulladd full2_422 (sum_2[278], carry_2[278], sum_1[406], carry_1[405], 1'b0);
fulladd full2_423 (sum_2[279], carry_2[279], sum_1[407], carry_1[406], 1'b0);
fulladd full2_424 (sum_2[280], carry_2[280], sum_1[408], carry_1[407], 1'b0);
fulladd full2_425 (sum_2[281], carry_2[281], sum_1[409], carry_1[408], 1'b0);
fulladd full2_426 (sum_2[282], carry_2[282], sum_1[410], carry_1[409], 1'b0);
fulladd full2_427 (sum_2[283], carry_2[283], sum_1[411], carry_1[410], 1'b0);
fulladd full2_428 (sum_2[284], carry_2[284], sum_1[412], carry_1[411], 1'b0);
fulladd full2_429 (sum_2[285], carry_2[285], sum_1[413], carry_1[412], 1'b0);
fulladd full2_430 (sum_2[286], carry_2[286], sum_1[414], carry_1[413], 1'b0);
fulladd full2_431 (sum_2[287], carry_2[287], sum_1[415], carry_1[414], C[992]);
fulladd full2_432 (sum_2[288], carry_2[288], sum_1[416], carry_1[415], C[993]);
fulladd full2_433 (sum_2[289], carry_2[289], sum_1[417], carry_1[416], C[994]);
fulladd full2_434 (sum_2[290], carry_2[290], sum_1[418], carry_1[417], C[995]);
fulladd full2_435 (sum_2[291], carry_2[291], sum_1[419], carry_1[418], C[996]);
fulladd full2_436 (sum_2[292], carry_2[292], sum_1[420], carry_1[419], C[997]);
fulladd full2_437 (sum_2[293], carry_2[293], sum_1[421], carry_1[420], C[998]);
fulladd full2_438 (sum_2[294], carry_2[294], sum_1[422], carry_1[421], C[999]);
fulladd full2_439 (sum_2[295], carry_2[295], sum_1[423], carry_1[422], C[1000]);
fulladd full2_440 (sum_2[296], carry_2[296], sum_1[424], carry_1[423], C[1001]);
fulladd full2_441 (sum_2[297], carry_2[297], sum_1[425], carry_1[424], C[1002]);
fulladd full2_442 (sum_2[298], carry_2[298], sum_1[426], carry_1[425], C[1003]);
fulladd full2_443 (sum_2[299], carry_2[299], sum_1[427], carry_1[426], C[1004]);
fulladd full2_444 (sum_2[300], carry_2[300], sum_1[428], carry_1[427], C[1005]);
fulladd full2_445 (sum_2[301], carry_2[301], sum_1[429], carry_1[428], C[1006]);
fulladd full2_446 (sum_2[302], carry_2[302], sum_1[430], carry_1[429], C[1007]);
fulladd full2_447 (sum_2[303], carry_2[303], sum_1[431], carry_1[430], C[1008]);
fulladd full2_448 (sum_2[304], carry_2[304], sum_1[432], carry_1[431], C[1009]);
fulladd full2_449 (sum_2[305], carry_2[305], sum_1[433], carry_1[432], C[1010]);
fulladd full2_450 (sum_2[306], carry_2[306], sum_1[434], carry_1[433], C[1011]);
fulladd full2_451 (sum_2[307], carry_2[307], sum_1[435], carry_1[434], C[1012]);
fulladd full2_452 (sum_2[308], carry_2[308], sum_1[436], carry_1[435], C[1013]);
fulladd full2_453 (sum_2[309], carry_2[309], sum_1[437], carry_1[436], C[1014]);
fulladd full2_454 (sum_2[310], carry_2[310], sum_1[438], carry_1[437], C[1015]);
fulladd full2_455 (sum_2[311], carry_2[311], sum_1[439], carry_1[438], C[1016]);
fulladd full2_456 (sum_2[312], carry_2[312], sum_1[440], carry_1[439], C[1017]);
fulladd full2_457 (sum_2[313], carry_2[313], sum_1[441], carry_1[440], C[1018]);
fulladd full2_458 (sum_2[314], carry_2[314], sum_1[442], carry_1[441], C[1019]);
fulladd full2_459 (sum_2[315], carry_2[315], sum_1[443], carry_1[442], C[1020]);
fulladd full2_460 (sum_2[316], carry_2[316], sum_1[444], carry_1[443], C[1021]);
fulladd full2_461 (sum_2[317], carry_2[317], sum_1[445], carry_1[444], C[1022]);
fulladd full2_462 (sum_2[318], carry_2[318], sum_1[446], carry_1[445], C[1023]);
fulladd full2_463 (sum_2[319], carry_2[319], sum_1[447], carry_1[446], C[1023]);
//sum_2/0/1/2
fulladd full3_00 (sum_3[0], carry_3[0], sum_2[0], sum_2[64], sum_2[128]);
fulladd full3_01 (sum_3[1], carry_3[1], sum_2[1], sum_2[65], sum_2[129]);
fulladd full3_02 (sum_3[2], carry_3[2], sum_2[2], sum_2[66], sum_2[130]);
fulladd full3_03 (sum_3[3], carry_3[3], sum_2[3], sum_2[67], sum_2[131]);
fulladd full3_04 (sum_3[4], carry_3[4], sum_2[4], sum_2[68], sum_2[132]);
fulladd full3_05 (sum_3[5], carry_3[5], sum_2[5], sum_2[69], sum_2[133]);
fulladd full3_06 (sum_3[6], carry_3[6], sum_2[6], sum_2[70], sum_2[134]);
fulladd full3_07 (sum_3[7], carry_3[7], sum_2[7], sum_2[71], sum_2[135]);
fulladd full3_08 (sum_3[8], carry_3[8], sum_2[8], sum_2[72], sum_2[136]);
fulladd full3_09 (sum_3[9], carry_3[9], sum_2[9], sum_2[73], sum_2[137]);
fulladd full3_010 (sum_3[10], carry_3[10], sum_2[10], sum_2[74], sum_2[138]);
fulladd full3_011 (sum_3[11], carry_3[11], sum_2[11], sum_2[75], sum_2[139]);
fulladd full3_012 (sum_3[12], carry_3[12], sum_2[12], sum_2[76], sum_2[140]);
fulladd full3_013 (sum_3[13], carry_3[13], sum_2[13], sum_2[77], sum_2[141]);
fulladd full3_014 (sum_3[14], carry_3[14], sum_2[14], sum_2[78], sum_2[142]);
fulladd full3_015 (sum_3[15], carry_3[15], sum_2[15], sum_2[79], sum_2[143]);
fulladd full3_016 (sum_3[16], carry_3[16], sum_2[16], sum_2[80], sum_2[144]);
fulladd full3_017 (sum_3[17], carry_3[17], sum_2[17], sum_2[81], sum_2[145]);
fulladd full3_018 (sum_3[18], carry_3[18], sum_2[18], sum_2[82], sum_2[146]);
fulladd full3_019 (sum_3[19], carry_3[19], sum_2[19], sum_2[83], sum_2[147]);
fulladd full3_020 (sum_3[20], carry_3[20], sum_2[20], sum_2[84], sum_2[148]);
fulladd full3_021 (sum_3[21], carry_3[21], sum_2[21], sum_2[85], sum_2[149]);
fulladd full3_022 (sum_3[22], carry_3[22], sum_2[22], sum_2[86], sum_2[150]);
fulladd full3_023 (sum_3[23], carry_3[23], sum_2[23], sum_2[87], sum_2[151]);
fulladd full3_024 (sum_3[24], carry_3[24], sum_2[24], sum_2[88], sum_2[152]);
fulladd full3_025 (sum_3[25], carry_3[25], sum_2[25], sum_2[89], sum_2[153]);
fulladd full3_026 (sum_3[26], carry_3[26], sum_2[26], sum_2[90], sum_2[154]);
fulladd full3_027 (sum_3[27], carry_3[27], sum_2[27], sum_2[91], sum_2[155]);
fulladd full3_028 (sum_3[28], carry_3[28], sum_2[28], sum_2[92], sum_2[156]);
fulladd full3_029 (sum_3[29], carry_3[29], sum_2[29], sum_2[93], sum_2[157]);
fulladd full3_030 (sum_3[30], carry_3[30], sum_2[30], sum_2[94], sum_2[158]);
fulladd full3_031 (sum_3[31], carry_3[31], sum_2[31], sum_2[95], sum_2[159]);
fulladd full3_032 (sum_3[32], carry_3[32], sum_2[32], sum_2[96], sum_2[160]);
fulladd full3_033 (sum_3[33], carry_3[33], sum_2[33], sum_2[97], sum_2[161]);
fulladd full3_034 (sum_3[34], carry_3[34], sum_2[34], sum_2[98], sum_2[162]);
fulladd full3_035 (sum_3[35], carry_3[35], sum_2[35], sum_2[99], sum_2[163]);
fulladd full3_036 (sum_3[36], carry_3[36], sum_2[36], sum_2[100], sum_2[164]);
fulladd full3_037 (sum_3[37], carry_3[37], sum_2[37], sum_2[101], sum_2[165]);
fulladd full3_038 (sum_3[38], carry_3[38], sum_2[38], sum_2[102], sum_2[166]);
fulladd full3_039 (sum_3[39], carry_3[39], sum_2[39], sum_2[103], sum_2[167]);
fulladd full3_040 (sum_3[40], carry_3[40], sum_2[40], sum_2[104], sum_2[168]);
fulladd full3_041 (sum_3[41], carry_3[41], sum_2[41], sum_2[105], sum_2[169]);
fulladd full3_042 (sum_3[42], carry_3[42], sum_2[42], sum_2[106], sum_2[170]);
fulladd full3_043 (sum_3[43], carry_3[43], sum_2[43], sum_2[107], sum_2[171]);
fulladd full3_044 (sum_3[44], carry_3[44], sum_2[44], sum_2[108], sum_2[172]);
fulladd full3_045 (sum_3[45], carry_3[45], sum_2[45], sum_2[109], sum_2[173]);
fulladd full3_046 (sum_3[46], carry_3[46], sum_2[46], sum_2[110], sum_2[174]);
fulladd full3_047 (sum_3[47], carry_3[47], sum_2[47], sum_2[111], sum_2[175]);
fulladd full3_048 (sum_3[48], carry_3[48], sum_2[48], sum_2[112], sum_2[176]);
fulladd full3_049 (sum_3[49], carry_3[49], sum_2[49], sum_2[113], sum_2[177]);
fulladd full3_050 (sum_3[50], carry_3[50], sum_2[50], sum_2[114], sum_2[178]);
fulladd full3_051 (sum_3[51], carry_3[51], sum_2[51], sum_2[115], sum_2[179]);
fulladd full3_052 (sum_3[52], carry_3[52], sum_2[52], sum_2[116], sum_2[180]);
fulladd full3_053 (sum_3[53], carry_3[53], sum_2[53], sum_2[117], sum_2[181]);
fulladd full3_054 (sum_3[54], carry_3[54], sum_2[54], sum_2[118], sum_2[182]);
fulladd full3_055 (sum_3[55], carry_3[55], sum_2[55], sum_2[119], sum_2[183]);
fulladd full3_056 (sum_3[56], carry_3[56], sum_2[56], sum_2[120], sum_2[184]);
fulladd full3_057 (sum_3[57], carry_3[57], sum_2[57], sum_2[121], sum_2[185]);
fulladd full3_058 (sum_3[58], carry_3[58], sum_2[58], sum_2[122], sum_2[186]);
fulladd full3_059 (sum_3[59], carry_3[59], sum_2[59], sum_2[123], sum_2[187]);
fulladd full3_060 (sum_3[60], carry_3[60], sum_2[60], sum_2[124], sum_2[188]);
fulladd full3_061 (sum_3[61], carry_3[61], sum_2[61], sum_2[125], sum_2[189]);
fulladd full3_062 (sum_3[62], carry_3[62], sum_2[62], sum_2[126], sum_2[190]);
fulladd full3_063 (sum_3[63], carry_3[63], sum_2[63], sum_2[127], sum_2[191]);
//carry_2/0/1/2
fulladd full3_10 (sum_3[64], carry_3[64], 1'b0, 1'b0, 1'b0);
fulladd full3_11 (sum_3[65], carry_3[65], carry_2[0], carry_2[64], carry_2[128]);
fulladd full3_12 (sum_3[66], carry_3[66], carry_2[1], carry_2[65], carry_2[129]);
fulladd full3_13 (sum_3[67], carry_3[67], carry_2[2], carry_2[66], carry_2[130]);
fulladd full3_14 (sum_3[68], carry_3[68], carry_2[3], carry_2[67], carry_2[131]);
fulladd full3_15 (sum_3[69], carry_3[69], carry_2[4], carry_2[68], carry_2[132]);
fulladd full3_16 (sum_3[70], carry_3[70], carry_2[5], carry_2[69], carry_2[133]);
fulladd full3_17 (sum_3[71], carry_3[71], carry_2[6], carry_2[70], carry_2[134]);
fulladd full3_18 (sum_3[72], carry_3[72], carry_2[7], carry_2[71], carry_2[135]);
fulladd full3_19 (sum_3[73], carry_3[73], carry_2[8], carry_2[72], carry_2[136]);
fulladd full3_110 (sum_3[74], carry_3[74], carry_2[9], carry_2[73], carry_2[137]);
fulladd full3_111 (sum_3[75], carry_3[75], carry_2[10], carry_2[74], carry_2[138]);
fulladd full3_112 (sum_3[76], carry_3[76], carry_2[11], carry_2[75], carry_2[139]);
fulladd full3_113 (sum_3[77], carry_3[77], carry_2[12], carry_2[76], carry_2[140]);
fulladd full3_114 (sum_3[78], carry_3[78], carry_2[13], carry_2[77], carry_2[141]);
fulladd full3_115 (sum_3[79], carry_3[79], carry_2[14], carry_2[78], carry_2[142]);
fulladd full3_116 (sum_3[80], carry_3[80], carry_2[15], carry_2[79], carry_2[143]);
fulladd full3_117 (sum_3[81], carry_3[81], carry_2[16], carry_2[80], carry_2[144]);
fulladd full3_118 (sum_3[82], carry_3[82], carry_2[17], carry_2[81], carry_2[145]);
fulladd full3_119 (sum_3[83], carry_3[83], carry_2[18], carry_2[82], carry_2[146]);
fulladd full3_120 (sum_3[84], carry_3[84], carry_2[19], carry_2[83], carry_2[147]);
fulladd full3_121 (sum_3[85], carry_3[85], carry_2[20], carry_2[84], carry_2[148]);
fulladd full3_122 (sum_3[86], carry_3[86], carry_2[21], carry_2[85], carry_2[149]);
fulladd full3_123 (sum_3[87], carry_3[87], carry_2[22], carry_2[86], carry_2[150]);
fulladd full3_124 (sum_3[88], carry_3[88], carry_2[23], carry_2[87], carry_2[151]);
fulladd full3_125 (sum_3[89], carry_3[89], carry_2[24], carry_2[88], carry_2[152]);
fulladd full3_126 (sum_3[90], carry_3[90], carry_2[25], carry_2[89], carry_2[153]);
fulladd full3_127 (sum_3[91], carry_3[91], carry_2[26], carry_2[90], carry_2[154]);
fulladd full3_128 (sum_3[92], carry_3[92], carry_2[27], carry_2[91], carry_2[155]);
fulladd full3_129 (sum_3[93], carry_3[93], carry_2[28], carry_2[92], carry_2[156]);
fulladd full3_130 (sum_3[94], carry_3[94], carry_2[29], carry_2[93], carry_2[157]);
fulladd full3_131 (sum_3[95], carry_3[95], carry_2[30], carry_2[94], carry_2[158]);
fulladd full3_132 (sum_3[96], carry_3[96], carry_2[31], carry_2[95], carry_2[159]);
fulladd full3_133 (sum_3[97], carry_3[97], carry_2[32], carry_2[96], carry_2[160]);
fulladd full3_134 (sum_3[98], carry_3[98], carry_2[33], carry_2[97], carry_2[161]);
fulladd full3_135 (sum_3[99], carry_3[99], carry_2[34], carry_2[98], carry_2[162]);
fulladd full3_136 (sum_3[100], carry_3[100], carry_2[35], carry_2[99], carry_2[163]);
fulladd full3_137 (sum_3[101], carry_3[101], carry_2[36], carry_2[100], carry_2[164]);
fulladd full3_138 (sum_3[102], carry_3[102], carry_2[37], carry_2[101], carry_2[165]);
fulladd full3_139 (sum_3[103], carry_3[103], carry_2[38], carry_2[102], carry_2[166]);
fulladd full3_140 (sum_3[104], carry_3[104], carry_2[39], carry_2[103], carry_2[167]);
fulladd full3_141 (sum_3[105], carry_3[105], carry_2[40], carry_2[104], carry_2[168]);
fulladd full3_142 (sum_3[106], carry_3[106], carry_2[41], carry_2[105], carry_2[169]);
fulladd full3_143 (sum_3[107], carry_3[107], carry_2[42], carry_2[106], carry_2[170]);
fulladd full3_144 (sum_3[108], carry_3[108], carry_2[43], carry_2[107], carry_2[171]);
fulladd full3_145 (sum_3[109], carry_3[109], carry_2[44], carry_2[108], carry_2[172]);
fulladd full3_146 (sum_3[110], carry_3[110], carry_2[45], carry_2[109], carry_2[173]);
fulladd full3_147 (sum_3[111], carry_3[111], carry_2[46], carry_2[110], carry_2[174]);
fulladd full3_148 (sum_3[112], carry_3[112], carry_2[47], carry_2[111], carry_2[175]);
fulladd full3_149 (sum_3[113], carry_3[113], carry_2[48], carry_2[112], carry_2[176]);
fulladd full3_150 (sum_3[114], carry_3[114], carry_2[49], carry_2[113], carry_2[177]);
fulladd full3_151 (sum_3[115], carry_3[115], carry_2[50], carry_2[114], carry_2[178]);
fulladd full3_152 (sum_3[116], carry_3[116], carry_2[51], carry_2[115], carry_2[179]);
fulladd full3_153 (sum_3[117], carry_3[117], carry_2[52], carry_2[116], carry_2[180]);
fulladd full3_154 (sum_3[118], carry_3[118], carry_2[53], carry_2[117], carry_2[181]);
fulladd full3_155 (sum_3[119], carry_3[119], carry_2[54], carry_2[118], carry_2[182]);
fulladd full3_156 (sum_3[120], carry_3[120], carry_2[55], carry_2[119], carry_2[183]);
fulladd full3_157 (sum_3[121], carry_3[121], carry_2[56], carry_2[120], carry_2[184]);
fulladd full3_158 (sum_3[122], carry_3[122], carry_2[57], carry_2[121], carry_2[185]);
fulladd full3_159 (sum_3[123], carry_3[123], carry_2[58], carry_2[122], carry_2[186]);
fulladd full3_160 (sum_3[124], carry_3[124], carry_2[59], carry_2[123], carry_2[187]);
fulladd full3_161 (sum_3[125], carry_3[125], carry_2[60], carry_2[124], carry_2[188]);
fulladd full3_162 (sum_3[126], carry_3[126], carry_2[61], carry_2[125], carry_2[189]);
fulladd full3_163 (sum_3[127], carry_3[127], carry_2[62], carry_2[126], carry_2[190]);
//sum_2/3/4.carry_3/3
fulladd full3_20 (sum_3[128], carry_3[128], sum_2[192], 1'b0, sum_2[256]);
fulladd full3_21 (sum_3[129], carry_3[129], sum_2[193], carry_2[192], sum_2[257]);
fulladd full3_22 (sum_3[130], carry_3[130], sum_2[194], carry_2[193], sum_2[258]);
fulladd full3_23 (sum_3[131], carry_3[131], sum_2[195], carry_2[194], sum_2[259]);
fulladd full3_24 (sum_3[132], carry_3[132], sum_2[196], carry_2[195], sum_2[260]);
fulladd full3_25 (sum_3[133], carry_3[133], sum_2[197], carry_2[196], sum_2[261]);
fulladd full3_26 (sum_3[134], carry_3[134], sum_2[198], carry_2[197], sum_2[262]);
fulladd full3_27 (sum_3[135], carry_3[135], sum_2[199], carry_2[198], sum_2[263]);
fulladd full3_28 (sum_3[136], carry_3[136], sum_2[200], carry_2[199], sum_2[264]);
fulladd full3_29 (sum_3[137], carry_3[137], sum_2[201], carry_2[200], sum_2[265]);
fulladd full3_210 (sum_3[138], carry_3[138], sum_2[202], carry_2[201], sum_2[266]);
fulladd full3_211 (sum_3[139], carry_3[139], sum_2[203], carry_2[202], sum_2[267]);
fulladd full3_212 (sum_3[140], carry_3[140], sum_2[204], carry_2[203], sum_2[268]);
fulladd full3_213 (sum_3[141], carry_3[141], sum_2[205], carry_2[204], sum_2[269]);
fulladd full3_214 (sum_3[142], carry_3[142], sum_2[206], carry_2[205], sum_2[270]);
fulladd full3_215 (sum_3[143], carry_3[143], sum_2[207], carry_2[206], sum_2[271]);
fulladd full3_216 (sum_3[144], carry_3[144], sum_2[208], carry_2[207], sum_2[272]);
fulladd full3_217 (sum_3[145], carry_3[145], sum_2[209], carry_2[208], sum_2[273]);
fulladd full3_218 (sum_3[146], carry_3[146], sum_2[210], carry_2[209], sum_2[274]);
fulladd full3_219 (sum_3[147], carry_3[147], sum_2[211], carry_2[210], sum_2[275]);
fulladd full3_220 (sum_3[148], carry_3[148], sum_2[212], carry_2[211], sum_2[276]);
fulladd full3_221 (sum_3[149], carry_3[149], sum_2[213], carry_2[212], sum_2[277]);
fulladd full3_222 (sum_3[150], carry_3[150], sum_2[214], carry_2[213], sum_2[278]);
fulladd full3_223 (sum_3[151], carry_3[151], sum_2[215], carry_2[214], sum_2[279]);
fulladd full3_224 (sum_3[152], carry_3[152], sum_2[216], carry_2[215], sum_2[280]);
fulladd full3_225 (sum_3[153], carry_3[153], sum_2[217], carry_2[216], sum_2[281]);
fulladd full3_226 (sum_3[154], carry_3[154], sum_2[218], carry_2[217], sum_2[282]);
fulladd full3_227 (sum_3[155], carry_3[155], sum_2[219], carry_2[218], sum_2[283]);
fulladd full3_228 (sum_3[156], carry_3[156], sum_2[220], carry_2[219], sum_2[284]);
fulladd full3_229 (sum_3[157], carry_3[157], sum_2[221], carry_2[220], sum_2[285]);
fulladd full3_230 (sum_3[158], carry_3[158], sum_2[222], carry_2[221], sum_2[286]);
fulladd full3_231 (sum_3[159], carry_3[159], sum_2[223], carry_2[222], sum_2[287]);
fulladd full3_232 (sum_3[160], carry_3[160], sum_2[224], carry_2[223], sum_2[288]);
fulladd full3_233 (sum_3[161], carry_3[161], sum_2[225], carry_2[224], sum_2[289]);
fulladd full3_234 (sum_3[162], carry_3[162], sum_2[226], carry_2[225], sum_2[290]);
fulladd full3_235 (sum_3[163], carry_3[163], sum_2[227], carry_2[226], sum_2[291]);
fulladd full3_236 (sum_3[164], carry_3[164], sum_2[228], carry_2[227], sum_2[292]);
fulladd full3_237 (sum_3[165], carry_3[165], sum_2[229], carry_2[228], sum_2[293]);
fulladd full3_238 (sum_3[166], carry_3[166], sum_2[230], carry_2[229], sum_2[294]);
fulladd full3_239 (sum_3[167], carry_3[167], sum_2[231], carry_2[230], sum_2[295]);
fulladd full3_240 (sum_3[168], carry_3[168], sum_2[232], carry_2[231], sum_2[296]);
fulladd full3_241 (sum_3[169], carry_3[169], sum_2[233], carry_2[232], sum_2[297]);
fulladd full3_242 (sum_3[170], carry_3[170], sum_2[234], carry_2[233], sum_2[298]);
fulladd full3_243 (sum_3[171], carry_3[171], sum_2[235], carry_2[234], sum_2[299]);
fulladd full3_244 (sum_3[172], carry_3[172], sum_2[236], carry_2[235], sum_2[300]);
fulladd full3_245 (sum_3[173], carry_3[173], sum_2[237], carry_2[236], sum_2[301]);
fulladd full3_246 (sum_3[174], carry_3[174], sum_2[238], carry_2[237], sum_2[302]);
fulladd full3_247 (sum_3[175], carry_3[175], sum_2[239], carry_2[238], sum_2[303]);
fulladd full3_248 (sum_3[176], carry_3[176], sum_2[240], carry_2[239], sum_2[304]);
fulladd full3_249 (sum_3[177], carry_3[177], sum_2[241], carry_2[240], sum_2[305]);
fulladd full3_250 (sum_3[178], carry_3[178], sum_2[242], carry_2[241], sum_2[306]);
fulladd full3_251 (sum_3[179], carry_3[179], sum_2[243], carry_2[242], sum_2[307]);
fulladd full3_252 (sum_3[180], carry_3[180], sum_2[244], carry_2[243], sum_2[308]);
fulladd full3_253 (sum_3[181], carry_3[181], sum_2[245], carry_2[244], sum_2[309]);
fulladd full3_254 (sum_3[182], carry_3[182], sum_2[246], carry_2[245], sum_2[310]);
fulladd full3_255 (sum_3[183], carry_3[183], sum_2[247], carry_2[246], sum_2[311]);
fulladd full3_256 (sum_3[184], carry_3[184], sum_2[248], carry_2[247], sum_2[312]);
fulladd full3_257 (sum_3[185], carry_3[185], sum_2[249], carry_2[248], sum_2[313]);
fulladd full3_258 (sum_3[186], carry_3[186], sum_2[250], carry_2[249], sum_2[314]);
fulladd full3_259 (sum_3[187], carry_3[187], sum_2[251], carry_2[250], sum_2[315]);
fulladd full3_260 (sum_3[188], carry_3[188], sum_2[252], carry_2[251], sum_2[316]);
fulladd full3_261 (sum_3[189], carry_3[189], sum_2[253], carry_2[252], sum_2[317]);
fulladd full3_262 (sum_3[190], carry_3[190], sum_2[254], carry_2[253], sum_2[318]);
fulladd full3_263 (sum_3[191], carry_3[191], sum_2[255], carry_2[254], sum_2[319]);
//sum_3/0/1/2
fulladd full4_00 (sum_4[0], carry_4[0], sum_3[0], sum_3[64], sum_3[128]);
fulladd full4_01 (sum_4[1], carry_4[1], sum_3[1], sum_3[65], sum_3[129]);
fulladd full4_02 (sum_4[2], carry_4[2], sum_3[2], sum_3[66], sum_3[130]);
fulladd full4_03 (sum_4[3], carry_4[3], sum_3[3], sum_3[67], sum_3[131]);
fulladd full4_04 (sum_4[4], carry_4[4], sum_3[4], sum_3[68], sum_3[132]);
fulladd full4_05 (sum_4[5], carry_4[5], sum_3[5], sum_3[69], sum_3[133]);
fulladd full4_06 (sum_4[6], carry_4[6], sum_3[6], sum_3[70], sum_3[134]);
fulladd full4_07 (sum_4[7], carry_4[7], sum_3[7], sum_3[71], sum_3[135]);
fulladd full4_08 (sum_4[8], carry_4[8], sum_3[8], sum_3[72], sum_3[136]);
fulladd full4_09 (sum_4[9], carry_4[9], sum_3[9], sum_3[73], sum_3[137]);
fulladd full4_010 (sum_4[10], carry_4[10], sum_3[10], sum_3[74], sum_3[138]);
fulladd full4_011 (sum_4[11], carry_4[11], sum_3[11], sum_3[75], sum_3[139]);
fulladd full4_012 (sum_4[12], carry_4[12], sum_3[12], sum_3[76], sum_3[140]);
fulladd full4_013 (sum_4[13], carry_4[13], sum_3[13], sum_3[77], sum_3[141]);
fulladd full4_014 (sum_4[14], carry_4[14], sum_3[14], sum_3[78], sum_3[142]);
fulladd full4_015 (sum_4[15], carry_4[15], sum_3[15], sum_3[79], sum_3[143]);
fulladd full4_016 (sum_4[16], carry_4[16], sum_3[16], sum_3[80], sum_3[144]);
fulladd full4_017 (sum_4[17], carry_4[17], sum_3[17], sum_3[81], sum_3[145]);
fulladd full4_018 (sum_4[18], carry_4[18], sum_3[18], sum_3[82], sum_3[146]);
fulladd full4_019 (sum_4[19], carry_4[19], sum_3[19], sum_3[83], sum_3[147]);
fulladd full4_020 (sum_4[20], carry_4[20], sum_3[20], sum_3[84], sum_3[148]);
fulladd full4_021 (sum_4[21], carry_4[21], sum_3[21], sum_3[85], sum_3[149]);
fulladd full4_022 (sum_4[22], carry_4[22], sum_3[22], sum_3[86], sum_3[150]);
fulladd full4_023 (sum_4[23], carry_4[23], sum_3[23], sum_3[87], sum_3[151]);
fulladd full4_024 (sum_4[24], carry_4[24], sum_3[24], sum_3[88], sum_3[152]);
fulladd full4_025 (sum_4[25], carry_4[25], sum_3[25], sum_3[89], sum_3[153]);
fulladd full4_026 (sum_4[26], carry_4[26], sum_3[26], sum_3[90], sum_3[154]);
fulladd full4_027 (sum_4[27], carry_4[27], sum_3[27], sum_3[91], sum_3[155]);
fulladd full4_028 (sum_4[28], carry_4[28], sum_3[28], sum_3[92], sum_3[156]);
fulladd full4_029 (sum_4[29], carry_4[29], sum_3[29], sum_3[93], sum_3[157]);
fulladd full4_030 (sum_4[30], carry_4[30], sum_3[30], sum_3[94], sum_3[158]);
fulladd full4_031 (sum_4[31], carry_4[31], sum_3[31], sum_3[95], sum_3[159]);
fulladd full4_032 (sum_4[32], carry_4[32], sum_3[32], sum_3[96], sum_3[160]);
fulladd full4_033 (sum_4[33], carry_4[33], sum_3[33], sum_3[97], sum_3[161]);
fulladd full4_034 (sum_4[34], carry_4[34], sum_3[34], sum_3[98], sum_3[162]);
fulladd full4_035 (sum_4[35], carry_4[35], sum_3[35], sum_3[99], sum_3[163]);
fulladd full4_036 (sum_4[36], carry_4[36], sum_3[36], sum_3[100], sum_3[164]);
fulladd full4_037 (sum_4[37], carry_4[37], sum_3[37], sum_3[101], sum_3[165]);
fulladd full4_038 (sum_4[38], carry_4[38], sum_3[38], sum_3[102], sum_3[166]);
fulladd full4_039 (sum_4[39], carry_4[39], sum_3[39], sum_3[103], sum_3[167]);
fulladd full4_040 (sum_4[40], carry_4[40], sum_3[40], sum_3[104], sum_3[168]);
fulladd full4_041 (sum_4[41], carry_4[41], sum_3[41], sum_3[105], sum_3[169]);
fulladd full4_042 (sum_4[42], carry_4[42], sum_3[42], sum_3[106], sum_3[170]);
fulladd full4_043 (sum_4[43], carry_4[43], sum_3[43], sum_3[107], sum_3[171]);
fulladd full4_044 (sum_4[44], carry_4[44], sum_3[44], sum_3[108], sum_3[172]);
fulladd full4_045 (sum_4[45], carry_4[45], sum_3[45], sum_3[109], sum_3[173]);
fulladd full4_046 (sum_4[46], carry_4[46], sum_3[46], sum_3[110], sum_3[174]);
fulladd full4_047 (sum_4[47], carry_4[47], sum_3[47], sum_3[111], sum_3[175]);
fulladd full4_048 (sum_4[48], carry_4[48], sum_3[48], sum_3[112], sum_3[176]);
fulladd full4_049 (sum_4[49], carry_4[49], sum_3[49], sum_3[113], sum_3[177]);
fulladd full4_050 (sum_4[50], carry_4[50], sum_3[50], sum_3[114], sum_3[178]);
fulladd full4_051 (sum_4[51], carry_4[51], sum_3[51], sum_3[115], sum_3[179]);
fulladd full4_052 (sum_4[52], carry_4[52], sum_3[52], sum_3[116], sum_3[180]);
fulladd full4_053 (sum_4[53], carry_4[53], sum_3[53], sum_3[117], sum_3[181]);
fulladd full4_054 (sum_4[54], carry_4[54], sum_3[54], sum_3[118], sum_3[182]);
fulladd full4_055 (sum_4[55], carry_4[55], sum_3[55], sum_3[119], sum_3[183]);
fulladd full4_056 (sum_4[56], carry_4[56], sum_3[56], sum_3[120], sum_3[184]);
fulladd full4_057 (sum_4[57], carry_4[57], sum_3[57], sum_3[121], sum_3[185]);
fulladd full4_058 (sum_4[58], carry_4[58], sum_3[58], sum_3[122], sum_3[186]);
fulladd full4_059 (sum_4[59], carry_4[59], sum_3[59], sum_3[123], sum_3[187]);
fulladd full4_060 (sum_4[60], carry_4[60], sum_3[60], sum_3[124], sum_3[188]);
fulladd full4_061 (sum_4[61], carry_4[61], sum_3[61], sum_3[125], sum_3[189]);
fulladd full4_062 (sum_4[62], carry_4[62], sum_3[62], sum_3[126], sum_3[190]);
fulladd full4_063 (sum_4[63], carry_4[63], sum_3[63], sum_3[127], sum_3[191]);
//carry_3/0/1/2
fulladd full4_10 (sum_4[64], carry_4[64], 1'b0, 1'b0, 1'b0);
fulladd full4_11 (sum_4[65], carry_4[65], carry_3[0], carry_3[64], carry_3[128]);
fulladd full4_12 (sum_4[66], carry_4[66], carry_3[1], carry_3[65], carry_3[129]);
fulladd full4_13 (sum_4[67], carry_4[67], carry_3[2], carry_3[66], carry_3[130]);
fulladd full4_14 (sum_4[68], carry_4[68], carry_3[3], carry_3[67], carry_3[131]);
fulladd full4_15 (sum_4[69], carry_4[69], carry_3[4], carry_3[68], carry_3[132]);
fulladd full4_16 (sum_4[70], carry_4[70], carry_3[5], carry_3[69], carry_3[133]);
fulladd full4_17 (sum_4[71], carry_4[71], carry_3[6], carry_3[70], carry_3[134]);
fulladd full4_18 (sum_4[72], carry_4[72], carry_3[7], carry_3[71], carry_3[135]);
fulladd full4_19 (sum_4[73], carry_4[73], carry_3[8], carry_3[72], carry_3[136]);
fulladd full4_110 (sum_4[74], carry_4[74], carry_3[9], carry_3[73], carry_3[137]);
fulladd full4_111 (sum_4[75], carry_4[75], carry_3[10], carry_3[74], carry_3[138]);
fulladd full4_112 (sum_4[76], carry_4[76], carry_3[11], carry_3[75], carry_3[139]);
fulladd full4_113 (sum_4[77], carry_4[77], carry_3[12], carry_3[76], carry_3[140]);
fulladd full4_114 (sum_4[78], carry_4[78], carry_3[13], carry_3[77], carry_3[141]);
fulladd full4_115 (sum_4[79], carry_4[79], carry_3[14], carry_3[78], carry_3[142]);
fulladd full4_116 (sum_4[80], carry_4[80], carry_3[15], carry_3[79], carry_3[143]);
fulladd full4_117 (sum_4[81], carry_4[81], carry_3[16], carry_3[80], carry_3[144]);
fulladd full4_118 (sum_4[82], carry_4[82], carry_3[17], carry_3[81], carry_3[145]);
fulladd full4_119 (sum_4[83], carry_4[83], carry_3[18], carry_3[82], carry_3[146]);
fulladd full4_120 (sum_4[84], carry_4[84], carry_3[19], carry_3[83], carry_3[147]);
fulladd full4_121 (sum_4[85], carry_4[85], carry_3[20], carry_3[84], carry_3[148]);
fulladd full4_122 (sum_4[86], carry_4[86], carry_3[21], carry_3[85], carry_3[149]);
fulladd full4_123 (sum_4[87], carry_4[87], carry_3[22], carry_3[86], carry_3[150]);
fulladd full4_124 (sum_4[88], carry_4[88], carry_3[23], carry_3[87], carry_3[151]);
fulladd full4_125 (sum_4[89], carry_4[89], carry_3[24], carry_3[88], carry_3[152]);
fulladd full4_126 (sum_4[90], carry_4[90], carry_3[25], carry_3[89], carry_3[153]);
fulladd full4_127 (sum_4[91], carry_4[91], carry_3[26], carry_3[90], carry_3[154]);
fulladd full4_128 (sum_4[92], carry_4[92], carry_3[27], carry_3[91], carry_3[155]);
fulladd full4_129 (sum_4[93], carry_4[93], carry_3[28], carry_3[92], carry_3[156]);
fulladd full4_130 (sum_4[94], carry_4[94], carry_3[29], carry_3[93], carry_3[157]);
fulladd full4_131 (sum_4[95], carry_4[95], carry_3[30], carry_3[94], carry_3[158]);
fulladd full4_132 (sum_4[96], carry_4[96], carry_3[31], carry_3[95], carry_3[159]);
fulladd full4_133 (sum_4[97], carry_4[97], carry_3[32], carry_3[96], carry_3[160]);
fulladd full4_134 (sum_4[98], carry_4[98], carry_3[33], carry_3[97], carry_3[161]);
fulladd full4_135 (sum_4[99], carry_4[99], carry_3[34], carry_3[98], carry_3[162]);
fulladd full4_136 (sum_4[100], carry_4[100], carry_3[35], carry_3[99], carry_3[163]);
fulladd full4_137 (sum_4[101], carry_4[101], carry_3[36], carry_3[100], carry_3[164]);
fulladd full4_138 (sum_4[102], carry_4[102], carry_3[37], carry_3[101], carry_3[165]);
fulladd full4_139 (sum_4[103], carry_4[103], carry_3[38], carry_3[102], carry_3[166]);
fulladd full4_140 (sum_4[104], carry_4[104], carry_3[39], carry_3[103], carry_3[167]);
fulladd full4_141 (sum_4[105], carry_4[105], carry_3[40], carry_3[104], carry_3[168]);
fulladd full4_142 (sum_4[106], carry_4[106], carry_3[41], carry_3[105], carry_3[169]);
fulladd full4_143 (sum_4[107], carry_4[107], carry_3[42], carry_3[106], carry_3[170]);
fulladd full4_144 (sum_4[108], carry_4[108], carry_3[43], carry_3[107], carry_3[171]);
fulladd full4_145 (sum_4[109], carry_4[109], carry_3[44], carry_3[108], carry_3[172]);
fulladd full4_146 (sum_4[110], carry_4[110], carry_3[45], carry_3[109], carry_3[173]);
fulladd full4_147 (sum_4[111], carry_4[111], carry_3[46], carry_3[110], carry_3[174]);
fulladd full4_148 (sum_4[112], carry_4[112], carry_3[47], carry_3[111], carry_3[175]);
fulladd full4_149 (sum_4[113], carry_4[113], carry_3[48], carry_3[112], carry_3[176]);
fulladd full4_150 (sum_4[114], carry_4[114], carry_3[49], carry_3[113], carry_3[177]);
fulladd full4_151 (sum_4[115], carry_4[115], carry_3[50], carry_3[114], carry_3[178]);
fulladd full4_152 (sum_4[116], carry_4[116], carry_3[51], carry_3[115], carry_3[179]);
fulladd full4_153 (sum_4[117], carry_4[117], carry_3[52], carry_3[116], carry_3[180]);
fulladd full4_154 (sum_4[118], carry_4[118], carry_3[53], carry_3[117], carry_3[181]);
fulladd full4_155 (sum_4[119], carry_4[119], carry_3[54], carry_3[118], carry_3[182]);
fulladd full4_156 (sum_4[120], carry_4[120], carry_3[55], carry_3[119], carry_3[183]);
fulladd full4_157 (sum_4[121], carry_4[121], carry_3[56], carry_3[120], carry_3[184]);
fulladd full4_158 (sum_4[122], carry_4[122], carry_3[57], carry_3[121], carry_3[185]);
fulladd full4_159 (sum_4[123], carry_4[123], carry_3[58], carry_3[122], carry_3[186]);
fulladd full4_160 (sum_4[124], carry_4[124], carry_3[59], carry_3[123], carry_3[187]);
fulladd full4_161 (sum_4[125], carry_4[125], carry_3[60], carry_3[124], carry_3[188]);
fulladd full4_162 (sum_4[126], carry_4[126], carry_3[61], carry_3[125], carry_3[189]);
fulladd full4_163 (sum_4[127], carry_4[127], carry_3[62], carry_3[126], carry_3[190]);
//sum_4/0/1.carry_4/0
fulladd full5_00 (sum_5[0], carry_5[0], sum_4[0], 1'b0, sum_4[64]);
fulladd full5_01 (sum_5[1], carry_5[1], sum_4[1], carry_4[0], sum_4[65]);
fulladd full5_02 (sum_5[2], carry_5[2], sum_4[2], carry_4[1], sum_4[66]);
fulladd full5_03 (sum_5[3], carry_5[3], sum_4[3], carry_4[2], sum_4[67]);
fulladd full5_04 (sum_5[4], carry_5[4], sum_4[4], carry_4[3], sum_4[68]);
fulladd full5_05 (sum_5[5], carry_5[5], sum_4[5], carry_4[4], sum_4[69]);
fulladd full5_06 (sum_5[6], carry_5[6], sum_4[6], carry_4[5], sum_4[70]);
fulladd full5_07 (sum_5[7], carry_5[7], sum_4[7], carry_4[6], sum_4[71]);
fulladd full5_08 (sum_5[8], carry_5[8], sum_4[8], carry_4[7], sum_4[72]);
fulladd full5_09 (sum_5[9], carry_5[9], sum_4[9], carry_4[8], sum_4[73]);
fulladd full5_010 (sum_5[10], carry_5[10], sum_4[10], carry_4[9], sum_4[74]);
fulladd full5_011 (sum_5[11], carry_5[11], sum_4[11], carry_4[10], sum_4[75]);
fulladd full5_012 (sum_5[12], carry_5[12], sum_4[12], carry_4[11], sum_4[76]);
fulladd full5_013 (sum_5[13], carry_5[13], sum_4[13], carry_4[12], sum_4[77]);
fulladd full5_014 (sum_5[14], carry_5[14], sum_4[14], carry_4[13], sum_4[78]);
fulladd full5_015 (sum_5[15], carry_5[15], sum_4[15], carry_4[14], sum_4[79]);
fulladd full5_016 (sum_5[16], carry_5[16], sum_4[16], carry_4[15], sum_4[80]);
fulladd full5_017 (sum_5[17], carry_5[17], sum_4[17], carry_4[16], sum_4[81]);
fulladd full5_018 (sum_5[18], carry_5[18], sum_4[18], carry_4[17], sum_4[82]);
fulladd full5_019 (sum_5[19], carry_5[19], sum_4[19], carry_4[18], sum_4[83]);
fulladd full5_020 (sum_5[20], carry_5[20], sum_4[20], carry_4[19], sum_4[84]);
fulladd full5_021 (sum_5[21], carry_5[21], sum_4[21], carry_4[20], sum_4[85]);
fulladd full5_022 (sum_5[22], carry_5[22], sum_4[22], carry_4[21], sum_4[86]);
fulladd full5_023 (sum_5[23], carry_5[23], sum_4[23], carry_4[22], sum_4[87]);
fulladd full5_024 (sum_5[24], carry_5[24], sum_4[24], carry_4[23], sum_4[88]);
fulladd full5_025 (sum_5[25], carry_5[25], sum_4[25], carry_4[24], sum_4[89]);
fulladd full5_026 (sum_5[26], carry_5[26], sum_4[26], carry_4[25], sum_4[90]);
fulladd full5_027 (sum_5[27], carry_5[27], sum_4[27], carry_4[26], sum_4[91]);
fulladd full5_028 (sum_5[28], carry_5[28], sum_4[28], carry_4[27], sum_4[92]);
fulladd full5_029 (sum_5[29], carry_5[29], sum_4[29], carry_4[28], sum_4[93]);
fulladd full5_030 (sum_5[30], carry_5[30], sum_4[30], carry_4[29], sum_4[94]);
fulladd full5_031 (sum_5[31], carry_5[31], sum_4[31], carry_4[30], sum_4[95]);
fulladd full5_032 (sum_5[32], carry_5[32], sum_4[32], carry_4[31], sum_4[96]);
fulladd full5_033 (sum_5[33], carry_5[33], sum_4[33], carry_4[32], sum_4[97]);
fulladd full5_034 (sum_5[34], carry_5[34], sum_4[34], carry_4[33], sum_4[98]);
fulladd full5_035 (sum_5[35], carry_5[35], sum_4[35], carry_4[34], sum_4[99]);
fulladd full5_036 (sum_5[36], carry_5[36], sum_4[36], carry_4[35], sum_4[100]);
fulladd full5_037 (sum_5[37], carry_5[37], sum_4[37], carry_4[36], sum_4[101]);
fulladd full5_038 (sum_5[38], carry_5[38], sum_4[38], carry_4[37], sum_4[102]);
fulladd full5_039 (sum_5[39], carry_5[39], sum_4[39], carry_4[38], sum_4[103]);
fulladd full5_040 (sum_5[40], carry_5[40], sum_4[40], carry_4[39], sum_4[104]);
fulladd full5_041 (sum_5[41], carry_5[41], sum_4[41], carry_4[40], sum_4[105]);
fulladd full5_042 (sum_5[42], carry_5[42], sum_4[42], carry_4[41], sum_4[106]);
fulladd full5_043 (sum_5[43], carry_5[43], sum_4[43], carry_4[42], sum_4[107]);
fulladd full5_044 (sum_5[44], carry_5[44], sum_4[44], carry_4[43], sum_4[108]);
fulladd full5_045 (sum_5[45], carry_5[45], sum_4[45], carry_4[44], sum_4[109]);
fulladd full5_046 (sum_5[46], carry_5[46], sum_4[46], carry_4[45], sum_4[110]);
fulladd full5_047 (sum_5[47], carry_5[47], sum_4[47], carry_4[46], sum_4[111]);
fulladd full5_048 (sum_5[48], carry_5[48], sum_4[48], carry_4[47], sum_4[112]);
fulladd full5_049 (sum_5[49], carry_5[49], sum_4[49], carry_4[48], sum_4[113]);
fulladd full5_050 (sum_5[50], carry_5[50], sum_4[50], carry_4[49], sum_4[114]);
fulladd full5_051 (sum_5[51], carry_5[51], sum_4[51], carry_4[50], sum_4[115]);
fulladd full5_052 (sum_5[52], carry_5[52], sum_4[52], carry_4[51], sum_4[116]);
fulladd full5_053 (sum_5[53], carry_5[53], sum_4[53], carry_4[52], sum_4[117]);
fulladd full5_054 (sum_5[54], carry_5[54], sum_4[54], carry_4[53], sum_4[118]);
fulladd full5_055 (sum_5[55], carry_5[55], sum_4[55], carry_4[54], sum_4[119]);
fulladd full5_056 (sum_5[56], carry_5[56], sum_4[56], carry_4[55], sum_4[120]);
fulladd full5_057 (sum_5[57], carry_5[57], sum_4[57], carry_4[56], sum_4[121]);
fulladd full5_058 (sum_5[58], carry_5[58], sum_4[58], carry_4[57], sum_4[122]);
fulladd full5_059 (sum_5[59], carry_5[59], sum_4[59], carry_4[58], sum_4[123]);
fulladd full5_060 (sum_5[60], carry_5[60], sum_4[60], carry_4[59], sum_4[124]);
fulladd full5_061 (sum_5[61], carry_5[61], sum_4[61], carry_4[60], sum_4[125]);
fulladd full5_062 (sum_5[62], carry_5[62], sum_4[62], carry_4[61], sum_4[126]);
fulladd full5_063 (sum_5[63], carry_5[63], sum_4[63], carry_4[62], sum_4[127]);
//sum_5/carry_5/carry_4
fulladd full6_00 (sum_6[0], carry_6[0], sum_5[0], 1'b0, 1'b0);
fulladd full6_01 (sum_6[1], carry_6[1], sum_5[1], carry_5[0], carry_4[64]);
fulladd full6_02 (sum_6[2], carry_6[2], sum_5[2], carry_5[1], carry_4[65]);
fulladd full6_03 (sum_6[3], carry_6[3], sum_5[3], carry_5[2], carry_4[66]);
fulladd full6_04 (sum_6[4], carry_6[4], sum_5[4], carry_5[3], carry_4[67]);
fulladd full6_05 (sum_6[5], carry_6[5], sum_5[5], carry_5[4], carry_4[68]);
fulladd full6_06 (sum_6[6], carry_6[6], sum_5[6], carry_5[5], carry_4[69]);
fulladd full6_07 (sum_6[7], carry_6[7], sum_5[7], carry_5[6], carry_4[70]);
fulladd full6_08 (sum_6[8], carry_6[8], sum_5[8], carry_5[7], carry_4[71]);
fulladd full6_09 (sum_6[9], carry_6[9], sum_5[9], carry_5[8], carry_4[72]);
fulladd full6_010 (sum_6[10], carry_6[10], sum_5[10], carry_5[9], carry_4[73]);
fulladd full6_011 (sum_6[11], carry_6[11], sum_5[11], carry_5[10], carry_4[74]);
fulladd full6_012 (sum_6[12], carry_6[12], sum_5[12], carry_5[11], carry_4[75]);
fulladd full6_013 (sum_6[13], carry_6[13], sum_5[13], carry_5[12], carry_4[76]);
fulladd full6_014 (sum_6[14], carry_6[14], sum_5[14], carry_5[13], carry_4[77]);
fulladd full6_015 (sum_6[15], carry_6[15], sum_5[15], carry_5[14], carry_4[78]);
fulladd full6_016 (sum_6[16], carry_6[16], sum_5[16], carry_5[15], carry_4[79]);
fulladd full6_017 (sum_6[17], carry_6[17], sum_5[17], carry_5[16], carry_4[80]);
fulladd full6_018 (sum_6[18], carry_6[18], sum_5[18], carry_5[17], carry_4[81]);
fulladd full6_019 (sum_6[19], carry_6[19], sum_5[19], carry_5[18], carry_4[82]);
fulladd full6_020 (sum_6[20], carry_6[20], sum_5[20], carry_5[19], carry_4[83]);
fulladd full6_021 (sum_6[21], carry_6[21], sum_5[21], carry_5[20], carry_4[84]);
fulladd full6_022 (sum_6[22], carry_6[22], sum_5[22], carry_5[21], carry_4[85]);
fulladd full6_023 (sum_6[23], carry_6[23], sum_5[23], carry_5[22], carry_4[86]);
fulladd full6_024 (sum_6[24], carry_6[24], sum_5[24], carry_5[23], carry_4[87]);
fulladd full6_025 (sum_6[25], carry_6[25], sum_5[25], carry_5[24], carry_4[88]);
fulladd full6_026 (sum_6[26], carry_6[26], sum_5[26], carry_5[25], carry_4[89]);
fulladd full6_027 (sum_6[27], carry_6[27], sum_5[27], carry_5[26], carry_4[90]);
fulladd full6_028 (sum_6[28], carry_6[28], sum_5[28], carry_5[27], carry_4[91]);
fulladd full6_029 (sum_6[29], carry_6[29], sum_5[29], carry_5[28], carry_4[92]);
fulladd full6_030 (sum_6[30], carry_6[30], sum_5[30], carry_5[29], carry_4[93]);
fulladd full6_031 (sum_6[31], carry_6[31], sum_5[31], carry_5[30], carry_4[94]);
fulladd full6_032 (sum_6[32], carry_6[32], sum_5[32], carry_5[31], carry_4[95]);
fulladd full6_033 (sum_6[33], carry_6[33], sum_5[33], carry_5[32], carry_4[96]);
fulladd full6_034 (sum_6[34], carry_6[34], sum_5[34], carry_5[33], carry_4[97]);
fulladd full6_035 (sum_6[35], carry_6[35], sum_5[35], carry_5[34], carry_4[98]);
fulladd full6_036 (sum_6[36], carry_6[36], sum_5[36], carry_5[35], carry_4[99]);
fulladd full6_037 (sum_6[37], carry_6[37], sum_5[37], carry_5[36], carry_4[100]);
fulladd full6_038 (sum_6[38], carry_6[38], sum_5[38], carry_5[37], carry_4[101]);
fulladd full6_039 (sum_6[39], carry_6[39], sum_5[39], carry_5[38], carry_4[102]);
fulladd full6_040 (sum_6[40], carry_6[40], sum_5[40], carry_5[39], carry_4[103]);
fulladd full6_041 (sum_6[41], carry_6[41], sum_5[41], carry_5[40], carry_4[104]);
fulladd full6_042 (sum_6[42], carry_6[42], sum_5[42], carry_5[41], carry_4[105]);
fulladd full6_043 (sum_6[43], carry_6[43], sum_5[43], carry_5[42], carry_4[106]);
fulladd full6_044 (sum_6[44], carry_6[44], sum_5[44], carry_5[43], carry_4[107]);
fulladd full6_045 (sum_6[45], carry_6[45], sum_5[45], carry_5[44], carry_4[108]);
fulladd full6_046 (sum_6[46], carry_6[46], sum_5[46], carry_5[45], carry_4[109]);
fulladd full6_047 (sum_6[47], carry_6[47], sum_5[47], carry_5[46], carry_4[110]);
fulladd full6_048 (sum_6[48], carry_6[48], sum_5[48], carry_5[47], carry_4[111]);
fulladd full6_049 (sum_6[49], carry_6[49], sum_5[49], carry_5[48], carry_4[112]);
fulladd full6_050 (sum_6[50], carry_6[50], sum_5[50], carry_5[49], carry_4[113]);
fulladd full6_051 (sum_6[51], carry_6[51], sum_5[51], carry_5[50], carry_4[114]);
fulladd full6_052 (sum_6[52], carry_6[52], sum_5[52], carry_5[51], carry_4[115]);
fulladd full6_053 (sum_6[53], carry_6[53], sum_5[53], carry_5[52], carry_4[116]);
fulladd full6_054 (sum_6[54], carry_6[54], sum_5[54], carry_5[53], carry_4[117]);
fulladd full6_055 (sum_6[55], carry_6[55], sum_5[55], carry_5[54], carry_4[118]);
fulladd full6_056 (sum_6[56], carry_6[56], sum_5[56], carry_5[55], carry_4[119]);
fulladd full6_057 (sum_6[57], carry_6[57], sum_5[57], carry_5[56], carry_4[120]);
fulladd full6_058 (sum_6[58], carry_6[58], sum_5[58], carry_5[57], carry_4[121]);
fulladd full6_059 (sum_6[59], carry_6[59], sum_5[59], carry_5[58], carry_4[122]);
fulladd full6_060 (sum_6[60], carry_6[60], sum_5[60], carry_5[59], carry_4[123]);
fulladd full6_061 (sum_6[61], carry_6[61], sum_5[61], carry_5[60], carry_4[124]);
fulladd full6_062 (sum_6[62], carry_6[62], sum_5[62], carry_5[61], carry_4[125]);
fulladd full6_063 (sum_6[63], carry_6[63], sum_5[63], carry_5[62], carry_4[126]);
//sum_6/carry_6/carry_2
fulladd full7_00 (sum_7[0], carry_7[0], sum_6[0], 1'b0, 1'b0);
fulladd full7_01 (sum_7[1], carry_7[1], sum_6[1], carry_6[0], carry_2[256]);
fulladd full7_02 (sum_7[2], carry_7[2], sum_6[2], carry_6[1], carry_2[257]);
fulladd full7_03 (sum_7[3], carry_7[3], sum_6[3], carry_6[2], carry_2[258]);
fulladd full7_04 (sum_7[4], carry_7[4], sum_6[4], carry_6[3], carry_2[259]);
fulladd full7_05 (sum_7[5], carry_7[5], sum_6[5], carry_6[4], carry_2[260]);
fulladd full7_06 (sum_7[6], carry_7[6], sum_6[6], carry_6[5], carry_2[261]);
fulladd full7_07 (sum_7[7], carry_7[7], sum_6[7], carry_6[6], carry_2[262]);
fulladd full7_08 (sum_7[8], carry_7[8], sum_6[8], carry_6[7], carry_2[263]);
fulladd full7_09 (sum_7[9], carry_7[9], sum_6[9], carry_6[8], carry_2[264]);
fulladd full7_010 (sum_7[10], carry_7[10], sum_6[10], carry_6[9], carry_2[265]);
fulladd full7_011 (sum_7[11], carry_7[11], sum_6[11], carry_6[10], carry_2[266]);
fulladd full7_012 (sum_7[12], carry_7[12], sum_6[12], carry_6[11], carry_2[267]);
fulladd full7_013 (sum_7[13], carry_7[13], sum_6[13], carry_6[12], carry_2[268]);
fulladd full7_014 (sum_7[14], carry_7[14], sum_6[14], carry_6[13], carry_2[269]);
fulladd full7_015 (sum_7[15], carry_7[15], sum_6[15], carry_6[14], carry_2[270]);
fulladd full7_016 (sum_7[16], carry_7[16], sum_6[16], carry_6[15], carry_2[271]);
fulladd full7_017 (sum_7[17], carry_7[17], sum_6[17], carry_6[16], carry_2[272]);
fulladd full7_018 (sum_7[18], carry_7[18], sum_6[18], carry_6[17], carry_2[273]);
fulladd full7_019 (sum_7[19], carry_7[19], sum_6[19], carry_6[18], carry_2[274]);
fulladd full7_020 (sum_7[20], carry_7[20], sum_6[20], carry_6[19], carry_2[275]);
fulladd full7_021 (sum_7[21], carry_7[21], sum_6[21], carry_6[20], carry_2[276]);
fulladd full7_022 (sum_7[22], carry_7[22], sum_6[22], carry_6[21], carry_2[277]);
fulladd full7_023 (sum_7[23], carry_7[23], sum_6[23], carry_6[22], carry_2[278]);
fulladd full7_024 (sum_7[24], carry_7[24], sum_6[24], carry_6[23], carry_2[279]);
fulladd full7_025 (sum_7[25], carry_7[25], sum_6[25], carry_6[24], carry_2[280]);
fulladd full7_026 (sum_7[26], carry_7[26], sum_6[26], carry_6[25], carry_2[281]);
fulladd full7_027 (sum_7[27], carry_7[27], sum_6[27], carry_6[26], carry_2[282]);
fulladd full7_028 (sum_7[28], carry_7[28], sum_6[28], carry_6[27], carry_2[283]);
fulladd full7_029 (sum_7[29], carry_7[29], sum_6[29], carry_6[28], carry_2[284]);
fulladd full7_030 (sum_7[30], carry_7[30], sum_6[30], carry_6[29], carry_2[285]);
fulladd full7_031 (sum_7[31], carry_7[31], sum_6[31], carry_6[30], carry_2[286]);
fulladd full7_032 (sum_7[32], carry_7[32], sum_6[32], carry_6[31], carry_2[287]);
fulladd full7_033 (sum_7[33], carry_7[33], sum_6[33], carry_6[32], carry_2[288]);
fulladd full7_034 (sum_7[34], carry_7[34], sum_6[34], carry_6[33], carry_2[289]);
fulladd full7_035 (sum_7[35], carry_7[35], sum_6[35], carry_6[34], carry_2[290]);
fulladd full7_036 (sum_7[36], carry_7[36], sum_6[36], carry_6[35], carry_2[291]);
fulladd full7_037 (sum_7[37], carry_7[37], sum_6[37], carry_6[36], carry_2[292]);
fulladd full7_038 (sum_7[38], carry_7[38], sum_6[38], carry_6[37], carry_2[293]);
fulladd full7_039 (sum_7[39], carry_7[39], sum_6[39], carry_6[38], carry_2[294]);
fulladd full7_040 (sum_7[40], carry_7[40], sum_6[40], carry_6[39], carry_2[295]);
fulladd full7_041 (sum_7[41], carry_7[41], sum_6[41], carry_6[40], carry_2[296]);
fulladd full7_042 (sum_7[42], carry_7[42], sum_6[42], carry_6[41], carry_2[297]);
fulladd full7_043 (sum_7[43], carry_7[43], sum_6[43], carry_6[42], carry_2[298]);
fulladd full7_044 (sum_7[44], carry_7[44], sum_6[44], carry_6[43], carry_2[299]);
fulladd full7_045 (sum_7[45], carry_7[45], sum_6[45], carry_6[44], carry_2[300]);
fulladd full7_046 (sum_7[46], carry_7[46], sum_6[46], carry_6[45], carry_2[301]);
fulladd full7_047 (sum_7[47], carry_7[47], sum_6[47], carry_6[46], carry_2[302]);
fulladd full7_048 (sum_7[48], carry_7[48], sum_6[48], carry_6[47], carry_2[303]);
fulladd full7_049 (sum_7[49], carry_7[49], sum_6[49], carry_6[48], carry_2[304]);
fulladd full7_050 (sum_7[50], carry_7[50], sum_6[50], carry_6[49], carry_2[305]);
fulladd full7_051 (sum_7[51], carry_7[51], sum_6[51], carry_6[50], carry_2[306]);
fulladd full7_052 (sum_7[52], carry_7[52], sum_6[52], carry_6[51], carry_2[307]);
fulladd full7_053 (sum_7[53], carry_7[53], sum_6[53], carry_6[52], carry_2[308]);
fulladd full7_054 (sum_7[54], carry_7[54], sum_6[54], carry_6[53], carry_2[309]);
fulladd full7_055 (sum_7[55], carry_7[55], sum_6[55], carry_6[54], carry_2[310]);
fulladd full7_056 (sum_7[56], carry_7[56], sum_6[56], carry_6[55], carry_2[311]);
fulladd full7_057 (sum_7[57], carry_7[57], sum_6[57], carry_6[56], carry_2[312]);
fulladd full7_058 (sum_7[58], carry_7[58], sum_6[58], carry_6[57], carry_2[313]);
fulladd full7_059 (sum_7[59], carry_7[59], sum_6[59], carry_6[58], carry_2[314]);
fulladd full7_060 (sum_7[60], carry_7[60], sum_6[60], carry_6[59], carry_2[315]);
fulladd full7_061 (sum_7[61], carry_7[61], sum_6[61], carry_6[60], carry_2[316]);
fulladd full7_062 (sum_7[62], carry_7[62], sum_6[62], carry_6[61], carry_2[317]);
fulladd full7_063 (sum_7[63], carry_7[63], sum_6[63], carry_6[62], carry_2[318]);
//final
fulladd full8_00 (O[0], carry_8[0], sum_7[0], 1'b0, 1'b0);
fulladd full8_01 (O[1], carry_8[1], sum_7[1], carry_7[0], carry_8[0]);
fulladd full8_02 (O[2], carry_8[2], sum_7[2], carry_7[1], carry_8[1]);
fulladd full8_03 (O[3], carry_8[3], sum_7[3], carry_7[2], carry_8[2]);
fulladd full8_04 (O[4], carry_8[4], sum_7[4], carry_7[3], carry_8[3]);
fulladd full8_05 (O[5], carry_8[5], sum_7[5], carry_7[4], carry_8[4]);
fulladd full8_06 (O[6], carry_8[6], sum_7[6], carry_7[5], carry_8[5]);
fulladd full8_07 (O[7], carry_8[7], sum_7[7], carry_7[6], carry_8[6]);
fulladd full8_08 (O[8], carry_8[8], sum_7[8], carry_7[7], carry_8[7]);
fulladd full8_09 (O[9], carry_8[9], sum_7[9], carry_7[8], carry_8[8]);
fulladd full8_010 (O[10], carry_8[10], sum_7[10], carry_7[9], carry_8[9]);
fulladd full8_011 (O[11], carry_8[11], sum_7[11], carry_7[10], carry_8[10]);
fulladd full8_012 (O[12], carry_8[12], sum_7[12], carry_7[11], carry_8[11]);
fulladd full8_013 (O[13], carry_8[13], sum_7[13], carry_7[12], carry_8[12]);
fulladd full8_014 (O[14], carry_8[14], sum_7[14], carry_7[13], carry_8[13]);
fulladd full8_015 (O[15], carry_8[15], sum_7[15], carry_7[14], carry_8[14]);
fulladd full8_016 (O[16], carry_8[16], sum_7[16], carry_7[15], carry_8[15]);
fulladd full8_017 (O[17], carry_8[17], sum_7[17], carry_7[16], carry_8[16]);
fulladd full8_018 (O[18], carry_8[18], sum_7[18], carry_7[17], carry_8[17]);
fulladd full8_019 (O[19], carry_8[19], sum_7[19], carry_7[18], carry_8[18]);
fulladd full8_020 (O[20], carry_8[20], sum_7[20], carry_7[19], carry_8[19]);
fulladd full8_021 (O[21], carry_8[21], sum_7[21], carry_7[20], carry_8[20]);
fulladd full8_022 (O[22], carry_8[22], sum_7[22], carry_7[21], carry_8[21]);
fulladd full8_023 (O[23], carry_8[23], sum_7[23], carry_7[22], carry_8[22]);
fulladd full8_024 (O[24], carry_8[24], sum_7[24], carry_7[23], carry_8[23]);
fulladd full8_025 (O[25], carry_8[25], sum_7[25], carry_7[24], carry_8[24]);
fulladd full8_026 (O[26], carry_8[26], sum_7[26], carry_7[25], carry_8[25]);
fulladd full8_027 (O[27], carry_8[27], sum_7[27], carry_7[26], carry_8[26]);
fulladd full8_028 (O[28], carry_8[28], sum_7[28], carry_7[27], carry_8[27]);
fulladd full8_029 (O[29], carry_8[29], sum_7[29], carry_7[28], carry_8[28]);
fulladd full8_030 (O[30], carry_8[30], sum_7[30], carry_7[29], carry_8[29]);
fulladd full8_031 (O[31], carry_8[31], sum_7[31], carry_7[30], carry_8[30]);
fulladd full8_032 (O[32], carry_8[32], sum_7[32], carry_7[31], carry_8[31]);
fulladd full8_033 (O[33], carry_8[33], sum_7[33], carry_7[32], carry_8[32]);
fulladd full8_034 (O[34], carry_8[34], sum_7[34], carry_7[33], carry_8[33]);
fulladd full8_035 (O[35], carry_8[35], sum_7[35], carry_7[34], carry_8[34]);
fulladd full8_036 (O[36], carry_8[36], sum_7[36], carry_7[35], carry_8[35]);
fulladd full8_037 (O[37], carry_8[37], sum_7[37], carry_7[36], carry_8[36]);
fulladd full8_038 (O[38], carry_8[38], sum_7[38], carry_7[37], carry_8[37]);
fulladd full8_039 (O[39], carry_8[39], sum_7[39], carry_7[38], carry_8[38]);
fulladd full8_040 (O[40], carry_8[40], sum_7[40], carry_7[39], carry_8[39]);
fulladd full8_041 (O[41], carry_8[41], sum_7[41], carry_7[40], carry_8[40]);
fulladd full8_042 (O[42], carry_8[42], sum_7[42], carry_7[41], carry_8[41]);
fulladd full8_043 (O[43], carry_8[43], sum_7[43], carry_7[42], carry_8[42]);
fulladd full8_044 (O[44], carry_8[44], sum_7[44], carry_7[43], carry_8[43]);
fulladd full8_045 (O[45], carry_8[45], sum_7[45], carry_7[44], carry_8[44]);
fulladd full8_046 (O[46], carry_8[46], sum_7[46], carry_7[45], carry_8[45]);
fulladd full8_047 (O[47], carry_8[47], sum_7[47], carry_7[46], carry_8[46]);
fulladd full8_048 (O[48], carry_8[48], sum_7[48], carry_7[47], carry_8[47]);
fulladd full8_049 (O[49], carry_8[49], sum_7[49], carry_7[48], carry_8[48]);
fulladd full8_050 (O[50], carry_8[50], sum_7[50], carry_7[49], carry_8[49]);
fulladd full8_051 (O[51], carry_8[51], sum_7[51], carry_7[50], carry_8[50]);
fulladd full8_052 (O[52], carry_8[52], sum_7[52], carry_7[51], carry_8[51]);
fulladd full8_053 (O[53], carry_8[53], sum_7[53], carry_7[52], carry_8[52]);
fulladd full8_054 (O[54], carry_8[54], sum_7[54], carry_7[53], carry_8[53]);
fulladd full8_055 (O[55], carry_8[55], sum_7[55], carry_7[54], carry_8[54]);
fulladd full8_056 (O[56], carry_8[56], sum_7[56], carry_7[55], carry_8[55]);
fulladd full8_057 (O[57], carry_8[57], sum_7[57], carry_7[56], carry_8[56]);
fulladd full8_058 (O[58], carry_8[58], sum_7[58], carry_7[57], carry_8[57]);
fulladd full8_059 (O[59], carry_8[59], sum_7[59], carry_7[58], carry_8[58]);
fulladd full8_060 (O[60], carry_8[60], sum_7[60], carry_7[59], carry_8[59]);
fulladd full8_061 (O[61], carry_8[61], sum_7[61], carry_7[60], carry_8[60]);
fulladd full8_062 (O[62], carry_8[62], sum_7[62], carry_7[61], carry_8[61]);
fulladd full8_063 (O[63], carry_8[63], sum_7[63], carry_7[62], carry_8[62]);
endmodule
|
//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name I/O size props
// mv_read O 64
// mav_write O 64
// CLK I 1 clock
// RST_N I 1 reset
// mav_write_misa I 28
// mav_write_wordxl I 64
// EN_reset I 1
// EN_mav_write I 1
//
// Combinational paths from inputs to outputs:
// (mav_write_misa, mav_write_wordxl) -> mav_write
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkCSR_MIE(CLK,
RST_N,
EN_reset,
mv_read,
mav_write_misa,
mav_write_wordxl,
EN_mav_write,
mav_write);
input CLK;
input RST_N;
// action method reset
input EN_reset;
// value method mv_read
output [63 : 0] mv_read;
// actionvalue method mav_write
input [27 : 0] mav_write_misa;
input [63 : 0] mav_write_wordxl;
input EN_mav_write;
output [63 : 0] mav_write;
// signals for module outputs
wire [63 : 0] mav_write, mv_read;
// register rg_mie
reg [11 : 0] rg_mie;
wire [11 : 0] rg_mie$D_IN;
wire rg_mie$EN;
// rule scheduling signals
wire CAN_FIRE_mav_write,
CAN_FIRE_reset,
WILL_FIRE_mav_write,
WILL_FIRE_reset;
// remaining internal signals
wire [11 : 0] mie__h88;
wire seie__h119, ssie__h113, stie__h116, ueie__h118, usie__h112, utie__h115;
// action method reset
assign CAN_FIRE_reset = 1'd1 ;
assign WILL_FIRE_reset = EN_reset ;
// value method mv_read
assign mv_read = { 52'd0, rg_mie } ;
// actionvalue method mav_write
assign mav_write = { 52'd0, mie__h88 } ;
assign CAN_FIRE_mav_write = 1'd1 ;
assign WILL_FIRE_mav_write = EN_mav_write ;
// register rg_mie
assign rg_mie$D_IN = EN_mav_write ? mie__h88 : 12'd0 ;
assign rg_mie$EN = EN_mav_write || EN_reset ;
// remaining internal signals
assign mie__h88 =
{ mav_write_wordxl[11],
1'b0,
seie__h119,
ueie__h118,
mav_write_wordxl[7],
1'b0,
stie__h116,
utie__h115,
mav_write_wordxl[3],
1'b0,
ssie__h113,
usie__h112 } ;
assign seie__h119 = mav_write_misa[18] && mav_write_wordxl[9] ;
assign ssie__h113 = mav_write_misa[18] && mav_write_wordxl[1] ;
assign stie__h116 = mav_write_misa[18] && mav_write_wordxl[5] ;
assign ueie__h118 = mav_write_misa[13] && mav_write_wordxl[8] ;
assign usie__h112 = mav_write_misa[13] && mav_write_wordxl[0] ;
assign utie__h115 = mav_write_misa[13] && mav_write_wordxl[4] ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
rg_mie <= `BSV_ASSIGNMENT_DELAY 12'd0;
end
else
begin
if (rg_mie$EN) rg_mie <= `BSV_ASSIGNMENT_DELAY rg_mie$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
rg_mie = 12'hAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkCSR_MIE
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Wed May 31 20:16:38 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_auto_us_1/system_auto_us_1_stub.v
// Design : system_auto_us_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_dwidth_converter_v2_1_11_top,Vivado 2016.4" *)
module system_auto_us_1(s_axi_aclk, s_axi_aresetn, s_axi_araddr,
s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache, s_axi_arprot,
s_axi_arregion, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_araddr, m_axi_arlen, m_axi_arsize,
m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot, m_axi_arregion, m_axi_arqos,
m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rlast, m_axi_rvalid,
m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arregion[3:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_araddr[31:0],m_axi_arlen[7:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arlock[0:0],m_axi_arcache[3:0],m_axi_arprot[2:0],m_axi_arregion[3:0],m_axi_arqos[3:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[63:0],m_axi_rresp[1:0],m_axi_rlast,m_axi_rvalid,m_axi_rready" */;
input s_axi_aclk;
input s_axi_aresetn;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arregion;
output [3:0]m_axi_arqos;
output m_axi_arvalid;
input m_axi_arready;
input [63:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
module avr_interface #(
parameter CLK_RATE = 50000000,
parameter SERIAL_BAUD_RATE = 500000
)(
input clk,
input rst,
// cclk, or configuration clock is used when the FPGA is begin configured.
// The AVR will hold cclk high when it has finished initializing.
// It is important not to drive the lines connecting to the AVR
// until cclk is high for a short period of time to avoid contention.
input cclk,
// AVR SPI Signals
output spi_miso,
input spi_mosi,
input spi_sck,
input spi_ss,
output [3:0] spi_channel,
// AVR Serial Signals
output tx,
input rx,
// ADC Interface Signals
input [3:0] channel,
output new_sample,
output [9:0] sample,
output [3:0] sample_channel,
// Serial TX User Interface
input [7:0] tx_data,
input new_tx_data,
output tx_busy,
input tx_block,
// Serial Rx User Interface
output [7:0] rx_data,
output new_rx_data
);
wire ready;
wire n_rdy = !ready;
wire spi_done;
wire [7:0] spi_dout;
wire tx_m;
wire spi_miso_m;
reg byte_ct_d, byte_ct_q;
reg [9:0] sample_d, sample_q;
reg new_sample_d, new_sample_q;
reg [3:0] sample_channel_d, sample_channel_q;
reg [3:0] block_d, block_q;
reg busy_d, busy_q;
// cclk_detector is used to detect when cclk is high signaling when
// the AVR is ready
cclk_detector #(.CLK_RATE(CLK_RATE)) cclk_detector (
.clk(clk),
.rst(rst),
.cclk(cclk),
.ready(ready)
);
spi_slave spi_slave (
.clk(clk),
.rst(n_rdy),
.ss(spi_ss),
.mosi(spi_mosi),
.miso(spi_miso_m),
.sck(spi_sck),
.done(spi_done),
.din(8'hff),
.dout(spi_dout)
);
// CLK_PER_BIT is the number of cycles each 'bit' lasts for
// rtoi converts a 'real' number to an 'integer'
localparam CLK_PER_BIT = 100; //$rtoi($ceil(CLK_RATE/SERIAL_BAUD_RATE));
serial_rx #(.CLK_PER_BIT(CLK_PER_BIT)) serial_rx (
.clk(clk),
.rst(n_rdy),
.rx(rx),
.data(rx_data),
.new_data(new_rx_data)
);
serial_tx #(.CLK_PER_BIT(CLK_PER_BIT)) serial_tx (
.clk(clk),
.rst(n_rdy),
.tx(tx_m),
.block(busy_q),
.busy(tx_busy),
.data(tx_data),
.new_data(new_tx_data)
);
// Output declarations
assign new_sample = new_sample_q;
assign sample = sample_q;
assign sample_channel = sample_channel_q;
// these signals connect to the AVR and should be Z when the AVR isn't ready
assign spi_channel = ready ? channel : 4'bZZZZ;
assign spi_miso = ready && !spi_ss ? spi_miso_m : 1'bZ;
assign tx = ready ? tx_m : 1'bZ;
always @(*) begin
byte_ct_d = byte_ct_q;
sample_d = sample_q;
new_sample_d = 1'b0;
sample_channel_d = sample_channel_q;
busy_d = busy_q;
block_d = {block_q[2:0], tx_block};
if (block_q[3] ^ block_q[2])
busy_d = 1'b0;
if (!tx_busy && new_tx_data)
busy_d = 1'b1;
if (spi_ss) begin // device is not selected
byte_ct_d = 1'b0;
end
if (spi_done) begin // sent/received data from SPI
if (byte_ct_q == 1'b0) begin
sample_d[7:0] = spi_dout; // first byte is the 8 LSB of the sample
byte_ct_d = 1'b1;
end else begin
sample_d[9:8] = spi_dout[1:0]; // second byte is the channel 2 MSB of the sample
sample_channel_d = spi_dout[7:4]; // and the channel that was sampled
byte_ct_d = 1'b1; // slave-select must be brought high before the next transfer
new_sample_d = 1'b1;
end
end
end
always @(posedge clk) begin
if (n_rdy) begin
byte_ct_q <= 1'b0;
sample_q <= 10'b0;
new_sample_q <= 1'b0;
end else begin
byte_ct_q <= byte_ct_d;
sample_q <= sample_d;
new_sample_q <= new_sample_d;
end
block_q <= block_d;
busy_q <= busy_d;
sample_channel_q <= sample_channel_d;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFBBN_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__SDFBBN_PP_BLACKBOX_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sdfbbn (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFBBN_PP_BLACKBOX_V
|
`timescale 1ns / 1ps
// UART wants the LSB first
// RX modified to accept 40 MHz clock and receive at 115200 bps
// Note 40e6 / 115200 = 347.2222 and 347.2 / 2 = 173.6 ~= 174 cycles
// For 460800
// 40e6 / 460800 = 86.8 and 86.8 / 2 =~= 43
// For 230400
// 40e6 / 230400 = 173.6 and 173.6/2 = 86.8
// Modified for 460800 baud rate
module uart_tx (
input reset,
input clk,
input [1:0] baud_rate,
input ld_tx_data,
input [7:0] tx_data,
input tx_enable,
(* IOB = "TRUE" *) output reg tx_out,
output reg tx_empty
);
parameter ML505 = 0; //default to 0 if not specified
// Internal registers
reg [7:0] tx_reg;
//reg tx_over_run ;
reg [3:0] tx_cnt;
reg [9:0] baud_cnt;
reg baud_clk;
// UART TX Logic
always @ (posedge clk) begin
if (reset) begin
baud_clk <= 1'b0;
baud_cnt <= 10'b0;
tx_reg <= 8'd0;
tx_empty <= 1'b1;
//tx_over_run <= 0;
tx_out <= 1'b1;
tx_cnt <= 4'd0;
end else begin // if (reset)
if (ML505) begin
if (baud_cnt == 10'd868) begin
baud_clk <= 1'b1;
baud_cnt <= 10'd0;
end else begin
baud_clk <= 1'b0;
baud_cnt <= baud_cnt + 1;
end
end else begin
case(baud_rate)
2'd0: begin // 115200 Baud
if (baud_cnt == 10'd347) begin
baud_clk <= 1'b1;
baud_cnt <= 10'd0;
end else begin
baud_clk <= 1'b0;
baud_cnt <= baud_cnt + 1;
end
end
2'd1: begin
if (baud_cnt == 10'd174) begin // 230400 Baud
baud_clk <= 1'b1;
baud_cnt <= 10'd0;
end else begin
baud_clk <= 1'b0;
baud_cnt <= baud_cnt + 1;
end
end
2'd2: begin
if (baud_cnt == 10'd87) begin // 460800 Baud
baud_clk <= 1'b1;
baud_cnt <= 10'd0;
end else begin
baud_clk <= 1'b0;
baud_cnt <= baud_cnt + 1;
end
end
default: begin // deafult to 115200 Baud
if (baud_cnt == 10'd347) begin
baud_clk <= 1'b1;
baud_cnt <= 10'd0;
end else begin
baud_clk <= 1'b0;
baud_cnt <= baud_cnt + 1;
end
end
endcase
end //if (~ML505)
if (tx_enable && baud_clk) begin
if (ld_tx_data && tx_empty) begin
tx_reg <= tx_data;
tx_empty <= 1'b0;
tx_out <= 1'b0; //Send start bit immediately
tx_cnt <= tx_cnt;
//tx_over_run <= 0; // um.... ??
end else if (!tx_empty) begin
tx_reg <= tx_reg;
if (tx_cnt == 4'd8) begin
tx_cnt <= 4'd0;
tx_out <= 1'b1;
tx_empty <= 1'b1;
end else begin
tx_cnt <= tx_cnt + 1;
tx_out <= tx_reg[tx_cnt];
tx_empty <= tx_empty;
end
end else begin
tx_reg <= tx_reg;
tx_cnt <= tx_cnt;
tx_out <= tx_out;
tx_empty <= tx_empty;
end
end else begin
tx_reg <= tx_reg;
tx_cnt <= tx_cnt;
tx_out <= tx_out;
tx_empty <= tx_empty;
end //if (~(tx_enable && baud_clk))
end //if (~reset)
end //always
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Tue May 30 22:39:44 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_vga_overlay_0_0 -prefix
// system_vga_overlay_0_0_ system_vga_overlay_0_0_stub.v
// Design : system_vga_overlay_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_overlay,Vivado 2016.4" *)
module system_vga_overlay_0_0(clk, rgb_0, rgb_1, rgb)
/* synthesis syn_black_box black_box_pad_pin="clk,rgb_0[23:0],rgb_1[23:0],rgb[23:0]" */;
input clk;
input [23:0]rgb_0;
input [23:0]rgb_1;
output [23:0]rgb;
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_gt_es (
lpm_dfe_n,
// drp interface
up_rstn,
up_clk,
up_es_drp_sel,
up_es_drp_wr,
up_es_drp_addr,
up_es_drp_wdata,
up_es_drp_rdata,
up_es_drp_ready,
// dma interface
up_es_dma_req,
up_es_dma_addr,
up_es_dma_data,
up_es_dma_ack,
// processor interface
up_es_start,
up_es_stop,
up_es_init,
up_es_sdata0,
up_es_sdata1,
up_es_sdata2,
up_es_sdata3,
up_es_sdata4,
up_es_qdata0,
up_es_qdata1,
up_es_qdata2,
up_es_qdata3,
up_es_qdata4,
up_es_prescale,
up_es_hoffset_min,
up_es_hoffset_max,
up_es_hoffset_step,
up_es_voffset_min,
up_es_voffset_max,
up_es_voffset_step,
up_es_voffset_range,
up_es_start_addr,
up_es_status);
// parameters
parameter integer GTH_OR_GTX_N = 0;
// gt address
localparam [11:0] ES_DRP_CTRL_ADDR = (GTH_OR_GTX_N == 1) ? 12'h03c : 12'h03d; // GTH-7 12'h03d
localparam [11:0] ES_DRP_SDATA0_ADDR = (GTH_OR_GTX_N == 1) ? 12'h049 : 12'h036; // GTH-7 12'h036
localparam [11:0] ES_DRP_SDATA1_ADDR = (GTH_OR_GTX_N == 1) ? 12'h04a : 12'h037; // GTH-7 12'h037
localparam [11:0] ES_DRP_SDATA2_ADDR = (GTH_OR_GTX_N == 1) ? 12'h04b : 12'h038; // GTH-7 12'h038
localparam [11:0] ES_DRP_SDATA3_ADDR = (GTH_OR_GTX_N == 1) ? 12'h04c : 12'h039; // GTH-7 12'h039
localparam [11:0] ES_DRP_SDATA4_ADDR = (GTH_OR_GTX_N == 1) ? 12'h04d : 12'h03a; // GTH-7 12'h03a
localparam [11:0] ES_DRP_QDATA0_ADDR = (GTH_OR_GTX_N == 1) ? 12'h044 : 12'h031; // GTH-7 12'h031
localparam [11:0] ES_DRP_QDATA1_ADDR = (GTH_OR_GTX_N == 1) ? 12'h045 : 12'h032; // GTH-7 12'h032
localparam [11:0] ES_DRP_QDATA2_ADDR = (GTH_OR_GTX_N == 1) ? 12'h046 : 12'h033; // GTH-7 12'h033
localparam [11:0] ES_DRP_QDATA3_ADDR = (GTH_OR_GTX_N == 1) ? 12'h047 : 12'h034; // GTH-7 12'h034
localparam [11:0] ES_DRP_QDATA4_ADDR = (GTH_OR_GTX_N == 1) ? 12'h048 : 12'h035; // GTH-7 12'h035
localparam [11:0] ES_DRP_HOFFSET_ADDR = (GTH_OR_GTX_N == 1) ? 12'h04f : 12'h03c; // GTH-7 12'h03c
localparam [11:0] ES_DRP_VOFFSET_ADDR = (GTH_OR_GTX_N == 1) ? 12'h097 : 12'h03b; // GTH-7 12'h03b
localparam [11:0] ES_DRP_STATUS_ADDR = (GTH_OR_GTX_N == 1) ? 12'h153 : 12'h151; // GTH-7 12'h153
localparam [11:0] ES_DRP_SCNT_ADDR = (GTH_OR_GTX_N == 1) ? 12'h152 : 12'h150; // GTH-7 12'h152
localparam [11:0] ES_DRP_ECNT_ADDR = (GTH_OR_GTX_N == 1) ? 12'h151 : 12'h14f; // GTH-7 12'h151
// state machine
localparam [ 5:0] ES_FSM_IDLE = 6'h00;
localparam [ 5:0] ES_FSM_STATUS = 6'h01;
localparam [ 5:0] ES_FSM_INIT = 6'h02;
localparam [ 5:0] ES_FSM_CTRLINIT_READ = 6'h03;
localparam [ 5:0] ES_FSM_CTRLINIT_RRDY = 6'h04;
localparam [ 5:0] ES_FSM_CTRLINIT_WRITE = 6'h05;
localparam [ 5:0] ES_FSM_CTRLINIT_WRDY = 6'h06;
localparam [ 5:0] ES_FSM_SDATA0_WRITE = 6'h07;
localparam [ 5:0] ES_FSM_SDATA0_WRDY = 6'h08;
localparam [ 5:0] ES_FSM_SDATA1_WRITE = 6'h09;
localparam [ 5:0] ES_FSM_SDATA1_WRDY = 6'h0a;
localparam [ 5:0] ES_FSM_SDATA2_WRITE = 6'h0b;
localparam [ 5:0] ES_FSM_SDATA2_WRDY = 6'h0c;
localparam [ 5:0] ES_FSM_SDATA3_WRITE = 6'h0d;
localparam [ 5:0] ES_FSM_SDATA3_WRDY = 6'h0e;
localparam [ 5:0] ES_FSM_SDATA4_WRITE = 6'h0f;
localparam [ 5:0] ES_FSM_SDATA4_WRDY = 6'h10;
localparam [ 5:0] ES_FSM_QDATA0_WRITE = 6'h11;
localparam [ 5:0] ES_FSM_QDATA0_WRDY = 6'h12;
localparam [ 5:0] ES_FSM_QDATA1_WRITE = 6'h13;
localparam [ 5:0] ES_FSM_QDATA1_WRDY = 6'h14;
localparam [ 5:0] ES_FSM_QDATA2_WRITE = 6'h15;
localparam [ 5:0] ES_FSM_QDATA2_WRDY = 6'h16;
localparam [ 5:0] ES_FSM_QDATA3_WRITE = 6'h17;
localparam [ 5:0] ES_FSM_QDATA3_WRDY = 6'h18;
localparam [ 5:0] ES_FSM_QDATA4_WRITE = 6'h19;
localparam [ 5:0] ES_FSM_QDATA4_WRDY = 6'h1a;
localparam [ 5:0] ES_FSM_HOFFSET_READ = 6'h1b;
localparam [ 5:0] ES_FSM_HOFFSET_RRDY = 6'h1c;
localparam [ 5:0] ES_FSM_HOFFSET_WRITE = 6'h1d;
localparam [ 5:0] ES_FSM_HOFFSET_WRDY = 6'h1e;
localparam [ 5:0] ES_FSM_VOFFSET_READ = 6'h1f;
localparam [ 5:0] ES_FSM_VOFFSET_RRDY = 6'h20;
localparam [ 5:0] ES_FSM_VOFFSET_WRITE = 6'h21;
localparam [ 5:0] ES_FSM_VOFFSET_WRDY = 6'h22;
localparam [ 5:0] ES_FSM_CTRLSTART_READ = 6'h23;
localparam [ 5:0] ES_FSM_CTRLSTART_RRDY = 6'h24;
localparam [ 5:0] ES_FSM_CTRLSTART_WRITE = 6'h25;
localparam [ 5:0] ES_FSM_CTRLSTART_WRDY = 6'h26;
localparam [ 5:0] ES_FSM_STATUS_READ = 6'h27;
localparam [ 5:0] ES_FSM_STATUS_RRDY = 6'h28;
localparam [ 5:0] ES_FSM_CTRLSTOP_READ = 6'h29;
localparam [ 5:0] ES_FSM_CTRLSTOP_RRDY = 6'h2a;
localparam [ 5:0] ES_FSM_CTRLSTOP_WRITE = 6'h2b;
localparam [ 5:0] ES_FSM_CTRLSTOP_WRDY = 6'h2c;
localparam [ 5:0] ES_FSM_SCNT_READ = 6'h2d;
localparam [ 5:0] ES_FSM_SCNT_RRDY = 6'h2e;
localparam [ 5:0] ES_FSM_ECNT_READ = 6'h2f;
localparam [ 5:0] ES_FSM_ECNT_RRDY = 6'h30;
localparam [ 5:0] ES_FSM_DMA_WRITE = 6'h31;
localparam [ 5:0] ES_FSM_DMA_READY = 6'h32;
localparam [ 5:0] ES_FSM_UPDATE = 6'h33;
input lpm_dfe_n;
// drp interface
input up_rstn;
input up_clk;
output up_es_drp_sel;
output up_es_drp_wr;
output [11:0] up_es_drp_addr;
output [15:0] up_es_drp_wdata;
input [15:0] up_es_drp_rdata;
input up_es_drp_ready;
// dma interface
output up_es_dma_req;
output [31:0] up_es_dma_addr;
output [31:0] up_es_dma_data;
input up_es_dma_ack;
// processor interface
input up_es_start;
input up_es_stop;
input up_es_init;
input [15:0] up_es_sdata0;
input [15:0] up_es_sdata1;
input [15:0] up_es_sdata2;
input [15:0] up_es_sdata3;
input [15:0] up_es_sdata4;
input [15:0] up_es_qdata0;
input [15:0] up_es_qdata1;
input [15:0] up_es_qdata2;
input [15:0] up_es_qdata3;
input [15:0] up_es_qdata4;
input [ 4:0] up_es_prescale;
input [11:0] up_es_hoffset_min;
input [11:0] up_es_hoffset_max;
input [11:0] up_es_hoffset_step;
input [ 7:0] up_es_voffset_min;
input [ 7:0] up_es_voffset_max;
input [ 7:0] up_es_voffset_step;
input [ 1:0] up_es_voffset_range;
input [31:0] up_es_start_addr;
output up_es_status;
// internal registers
reg up_es_dma_req = 'd0;
reg [31:0] up_es_dma_addr = 'd0;
reg [31:0] up_es_dma_data = 'd0;
reg up_es_status = 'd0;
reg up_es_ut = 'd0;
reg [31:0] up_es_addr = 'd0;
reg [11:0] up_es_hoffset = 'd0;
reg [ 7:0] up_es_voffset = 'd0;
reg [15:0] up_es_hoffset_rdata = 'd0;
reg [15:0] up_es_voffset_rdata = 'd0;
reg [15:0] up_es_ctrl_rdata = 'd0;
reg [15:0] up_es_scnt_rdata = 'd0;
reg [15:0] up_es_ecnt_rdata = 'd0;
reg [ 5:0] up_es_fsm = 'd0;
reg up_es_drp_sel = 'd0;
reg up_es_drp_wr = 'd0;
reg [11:0] up_es_drp_addr = 'd0;
reg [15:0] up_es_drp_wdata = 'd0;
// internal signals
wire up_es_heos_s;
wire up_es_eos_s;
wire up_es_ut_s;
wire [ 7:0] up_es_voffset_2_s;
wire [ 7:0] up_es_voffset_n_s;
wire [ 7:0] up_es_voffset_s;
// dma interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_es_dma_req <= 'b0;
up_es_dma_addr <= 'd0;
up_es_dma_data <= 'd0;
end else begin
if ((up_es_dma_req == 1'b1) && (up_es_dma_ack == 1'b1)) begin
up_es_dma_req <= 1'b0;
up_es_dma_addr <= 32'd0;
up_es_dma_data <= 32'd0;
end else if (up_es_fsm == ES_FSM_DMA_WRITE) begin
up_es_dma_req <= 1'b1;
up_es_dma_addr <= up_es_addr;
up_es_dma_data <= {up_es_scnt_rdata, up_es_ecnt_rdata};
end
end
end
// prescale, horizontal and vertical offsets
assign up_es_heos_s = (up_es_hoffset == up_es_hoffset_max) ? up_es_ut : 1'b0;
assign up_es_eos_s = (up_es_voffset == up_es_voffset_max) ? up_es_heos_s : 1'b0;
assign up_es_ut_s = up_es_ut & ~lpm_dfe_n;
assign up_es_voffset_2_s = ~up_es_voffset + 1'b1;
assign up_es_voffset_n_s = {1'b1, up_es_voffset_2_s[6:0]};
assign up_es_voffset_s = (up_es_voffset[7] == 1'b1) ? up_es_voffset_n_s : up_es_voffset;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_es_status <= 1'b0;
up_es_ut <= 'd0;
up_es_addr <= 'd0;
up_es_hoffset <= 'd0;
up_es_voffset <= 'd0;
end else begin
if (up_es_fsm == ES_FSM_IDLE) begin
up_es_status <= 1'b0;
end else begin
up_es_status <= 1'b1;
end
if (up_es_fsm == ES_FSM_IDLE) begin
up_es_ut <= lpm_dfe_n;
up_es_addr <= up_es_start_addr;
up_es_hoffset <= up_es_hoffset_min;
up_es_voffset <= up_es_voffset_min;
end else if (up_es_fsm == ES_FSM_UPDATE) begin
up_es_ut <= ~up_es_ut | lpm_dfe_n;
up_es_addr <= up_es_addr + 3'd4;
if (up_es_heos_s == 1'b1) begin
up_es_hoffset <= up_es_hoffset_min;
end else if (up_es_ut == 1'b1) begin
up_es_hoffset <= up_es_hoffset + up_es_hoffset_step;
end
if (up_es_heos_s == 1'b1) begin
up_es_voffset <= up_es_voffset + up_es_voffset_step;
end
end
end
end
// read-modify-write parameters (gt's are full of mixed up controls)
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_es_hoffset_rdata <= 'd0;
up_es_voffset_rdata <= 'd0;
up_es_ctrl_rdata <= 'd0;
up_es_scnt_rdata <= 'd0;
up_es_ecnt_rdata <= 'd0;
end else begin
if ((up_es_fsm == ES_FSM_HOFFSET_RRDY) && (up_es_drp_ready == 1'b1)) begin
up_es_hoffset_rdata <= up_es_drp_rdata;
end
if ((up_es_fsm == ES_FSM_VOFFSET_RRDY) && (up_es_drp_ready == 1'b1)) begin
up_es_voffset_rdata <= up_es_drp_rdata;
end
if (((up_es_fsm == ES_FSM_CTRLINIT_RRDY) || (up_es_fsm == ES_FSM_CTRLSTART_RRDY) ||
(up_es_fsm == ES_FSM_CTRLSTOP_RRDY)) && (up_es_drp_ready == 1'b1)) begin
up_es_ctrl_rdata <= up_es_drp_rdata;
end
if ((up_es_fsm == ES_FSM_SCNT_RRDY) && (up_es_drp_ready == 1'b1)) begin
up_es_scnt_rdata <= up_es_drp_rdata;
end
if ((up_es_fsm == ES_FSM_ECNT_RRDY) && (up_es_drp_ready == 1'b1)) begin
up_es_ecnt_rdata <= up_es_drp_rdata;
end
end
end
// eye scan state machine- write vertical and horizontal offsets
// and read back sample and error counters
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_es_fsm <= ES_FSM_IDLE;
end else begin
if (up_es_stop == 1'b1) begin
up_es_fsm <= ES_FSM_IDLE;
end else begin
case (up_es_fsm)
ES_FSM_IDLE: begin // idle
if (up_es_start == 1'b1) begin
up_es_fsm <= ES_FSM_STATUS;
end else begin
up_es_fsm <= ES_FSM_IDLE;
end
end
ES_FSM_STATUS: begin // set status
up_es_fsm <= ES_FSM_INIT;
end
ES_FSM_INIT: begin // initialize
if (up_es_init == 1'b1) begin
up_es_fsm <= ES_FSM_CTRLINIT_READ;
end else begin
up_es_fsm <= ES_FSM_HOFFSET_READ;
end
end
ES_FSM_CTRLINIT_READ: begin // control read
up_es_fsm <= ES_FSM_CTRLINIT_RRDY;
end
ES_FSM_CTRLINIT_RRDY: begin // control ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_CTRLINIT_WRITE;
end else begin
up_es_fsm <= ES_FSM_CTRLINIT_RRDY;
end
end
ES_FSM_CTRLINIT_WRITE: begin // control write
up_es_fsm <= ES_FSM_CTRLINIT_WRDY;
end
ES_FSM_CTRLINIT_WRDY: begin // control ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_SDATA0_WRITE;
end else begin
up_es_fsm <= ES_FSM_CTRLINIT_WRDY;
end
end
ES_FSM_SDATA0_WRITE: begin // sdata write
up_es_fsm <= ES_FSM_SDATA0_WRDY;
end
ES_FSM_SDATA0_WRDY: begin // sdata ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_SDATA1_WRITE;
end else begin
up_es_fsm <= ES_FSM_SDATA0_WRDY;
end
end
ES_FSM_SDATA1_WRITE: begin // sdata write
up_es_fsm <= ES_FSM_SDATA1_WRDY;
end
ES_FSM_SDATA1_WRDY: begin // sdata ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_SDATA2_WRITE;
end else begin
up_es_fsm <= ES_FSM_SDATA1_WRDY;
end
end
ES_FSM_SDATA2_WRITE: begin // sdata write
up_es_fsm <= ES_FSM_SDATA2_WRDY;
end
ES_FSM_SDATA2_WRDY: begin // sdata ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_SDATA3_WRITE;
end else begin
up_es_fsm <= ES_FSM_SDATA2_WRDY;
end
end
ES_FSM_SDATA3_WRITE: begin // sdata write
up_es_fsm <= ES_FSM_SDATA3_WRDY;
end
ES_FSM_SDATA3_WRDY: begin // sdata ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_SDATA4_WRITE;
end else begin
up_es_fsm <= ES_FSM_SDATA3_WRDY;
end
end
ES_FSM_SDATA4_WRITE: begin // sdata write
up_es_fsm <= ES_FSM_SDATA4_WRDY;
end
ES_FSM_SDATA4_WRDY: begin // sdata ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_QDATA0_WRITE;
end else begin
up_es_fsm <= ES_FSM_SDATA4_WRDY;
end
end
ES_FSM_QDATA0_WRITE: begin // qdata write
up_es_fsm <= ES_FSM_QDATA0_WRDY;
end
ES_FSM_QDATA0_WRDY: begin // qdata ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_QDATA1_WRITE;
end else begin
up_es_fsm <= ES_FSM_QDATA0_WRDY;
end
end
ES_FSM_QDATA1_WRITE: begin // qdata write
up_es_fsm <= ES_FSM_QDATA1_WRDY;
end
ES_FSM_QDATA1_WRDY: begin // qdata ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_QDATA2_WRITE;
end else begin
up_es_fsm <= ES_FSM_QDATA1_WRDY;
end
end
ES_FSM_QDATA2_WRITE: begin // qdata write
up_es_fsm <= ES_FSM_QDATA2_WRDY;
end
ES_FSM_QDATA2_WRDY: begin // qdata ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_QDATA3_WRITE;
end else begin
up_es_fsm <= ES_FSM_QDATA2_WRDY;
end
end
ES_FSM_QDATA3_WRITE: begin // qdata write
up_es_fsm <= ES_FSM_QDATA3_WRDY;
end
ES_FSM_QDATA3_WRDY: begin // qdata ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_QDATA4_WRITE;
end else begin
up_es_fsm <= ES_FSM_QDATA3_WRDY;
end
end
ES_FSM_QDATA4_WRITE: begin // qdata write
up_es_fsm <= ES_FSM_QDATA4_WRDY;
end
ES_FSM_QDATA4_WRDY: begin // qdata ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_HOFFSET_READ;
end else begin
up_es_fsm <= ES_FSM_QDATA4_WRDY;
end
end
ES_FSM_HOFFSET_READ: begin // horizontal offset read
up_es_fsm <= ES_FSM_HOFFSET_RRDY;
end
ES_FSM_HOFFSET_RRDY: begin // horizontal offset ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_HOFFSET_WRITE;
end else begin
up_es_fsm <= ES_FSM_HOFFSET_RRDY;
end
end
ES_FSM_HOFFSET_WRITE: begin // horizontal offset write
up_es_fsm <= ES_FSM_HOFFSET_WRDY;
end
ES_FSM_HOFFSET_WRDY: begin // horizontal offset ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_VOFFSET_READ;
end else begin
up_es_fsm <= ES_FSM_HOFFSET_WRDY;
end
end
ES_FSM_VOFFSET_READ: begin // vertical offset read
up_es_fsm <= ES_FSM_VOFFSET_RRDY;
end
ES_FSM_VOFFSET_RRDY: begin // vertical offset ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_VOFFSET_WRITE;
end else begin
up_es_fsm <= ES_FSM_VOFFSET_RRDY;
end
end
ES_FSM_VOFFSET_WRITE: begin // vertical offset write
up_es_fsm <= ES_FSM_VOFFSET_WRDY;
end
ES_FSM_VOFFSET_WRDY: begin // vertical offset ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_CTRLSTART_READ;
end else begin
up_es_fsm <= ES_FSM_VOFFSET_WRDY;
end
end
ES_FSM_CTRLSTART_READ: begin // control read
up_es_fsm <= ES_FSM_CTRLSTART_RRDY;
end
ES_FSM_CTRLSTART_RRDY: begin // control ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_CTRLSTART_WRITE;
end else begin
up_es_fsm <= ES_FSM_CTRLSTART_RRDY;
end
end
ES_FSM_CTRLSTART_WRITE: begin // control write
up_es_fsm <= ES_FSM_CTRLSTART_WRDY;
end
ES_FSM_CTRLSTART_WRDY: begin // control ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_STATUS_READ;
end else begin
up_es_fsm <= ES_FSM_CTRLSTART_WRDY;
end
end
ES_FSM_STATUS_READ: begin // status read
up_es_fsm <= ES_FSM_STATUS_RRDY;
end
ES_FSM_STATUS_RRDY: begin // status ready
if (up_es_drp_ready == 1'b0) begin
up_es_fsm <= ES_FSM_STATUS_RRDY;
end else if (up_es_drp_rdata[3:0] == 4'b0101) begin
up_es_fsm <= ES_FSM_CTRLSTOP_READ;
end else begin
up_es_fsm <= ES_FSM_STATUS_READ;
end
end
ES_FSM_CTRLSTOP_READ: begin // control read
up_es_fsm <= ES_FSM_CTRLSTOP_RRDY;
end
ES_FSM_CTRLSTOP_RRDY: begin // control ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_CTRLSTOP_WRITE;
end else begin
up_es_fsm <= ES_FSM_CTRLSTOP_RRDY;
end
end
ES_FSM_CTRLSTOP_WRITE: begin // control write
up_es_fsm <= ES_FSM_CTRLSTOP_WRDY;
end
ES_FSM_CTRLSTOP_WRDY: begin // control ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_SCNT_READ;
end else begin
up_es_fsm <= ES_FSM_CTRLSTOP_WRDY;
end
end
ES_FSM_SCNT_READ: begin // read sample count
up_es_fsm <= ES_FSM_SCNT_RRDY;
end
ES_FSM_SCNT_RRDY: begin // sample count ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_ECNT_READ;
end else begin
up_es_fsm <= ES_FSM_SCNT_RRDY;
end
end
ES_FSM_ECNT_READ: begin // read error count
up_es_fsm <= ES_FSM_ECNT_RRDY;
end
ES_FSM_ECNT_RRDY: begin // error count ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_DMA_WRITE;
end else begin
up_es_fsm <= ES_FSM_ECNT_RRDY;
end
end
ES_FSM_DMA_WRITE: begin // dma write
up_es_fsm <= ES_FSM_DMA_READY;
end
ES_FSM_DMA_READY: begin // dma ack
if (up_es_dma_ack == 1'b1) begin
up_es_fsm <= ES_FSM_UPDATE;
end else begin
up_es_fsm <= ES_FSM_DMA_READY;
end
end
ES_FSM_UPDATE: begin // update
if (up_es_eos_s == 1'b1) begin
up_es_fsm <= ES_FSM_IDLE;
end else if (up_es_ut == 1'b1) begin
up_es_fsm <= ES_FSM_HOFFSET_READ;
end else begin
up_es_fsm <= ES_FSM_VOFFSET_READ;
end
end
default: begin
up_es_fsm <= ES_FSM_IDLE;
end
endcase
end
end
end
// drp signals controlled by the fsm
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_es_drp_sel <= 'd0;
up_es_drp_wr <= 'd0;
up_es_drp_addr <= 'd0;
up_es_drp_wdata <= 'd0;
end else begin
case (up_es_fsm)
ES_FSM_CTRLINIT_READ: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b0;
up_es_drp_addr <= ES_DRP_CTRL_ADDR;
up_es_drp_wdata <= 16'h0000;
end
ES_FSM_CTRLINIT_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_CTRL_ADDR;
if (GTH_OR_GTX_N == 1) begin
up_es_drp_wdata <= {up_es_ctrl_rdata[15:10], 2'b11,
up_es_ctrl_rdata[7:5], up_es_prescale};
end else begin
up_es_drp_wdata <= {up_es_ctrl_rdata[15:10], 2'b11, up_es_ctrl_rdata[7:0]};
end
end
ES_FSM_SDATA0_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_SDATA0_ADDR;
up_es_drp_wdata <= up_es_sdata0;
end
ES_FSM_SDATA1_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_SDATA1_ADDR;
up_es_drp_wdata <= up_es_sdata1;
end
ES_FSM_SDATA2_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_SDATA2_ADDR;
up_es_drp_wdata <= up_es_sdata2;
end
ES_FSM_SDATA3_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_SDATA3_ADDR;
up_es_drp_wdata <= up_es_sdata3;
end
ES_FSM_SDATA4_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_SDATA4_ADDR;
up_es_drp_wdata <= up_es_sdata4;
end
ES_FSM_QDATA0_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_QDATA0_ADDR;
up_es_drp_wdata <= up_es_qdata0;
end
ES_FSM_QDATA1_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_QDATA1_ADDR;
up_es_drp_wdata <= up_es_qdata1;
end
ES_FSM_QDATA2_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_QDATA2_ADDR;
up_es_drp_wdata <= up_es_qdata2;
end
ES_FSM_QDATA3_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_QDATA3_ADDR;
up_es_drp_wdata <= up_es_qdata3;
end
ES_FSM_QDATA4_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_QDATA4_ADDR;
up_es_drp_wdata <= up_es_qdata4;
end
ES_FSM_HOFFSET_READ: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b0;
up_es_drp_addr <= ES_DRP_HOFFSET_ADDR;
up_es_drp_wdata <= 16'h0000;
end
ES_FSM_HOFFSET_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_HOFFSET_ADDR;
if (GTH_OR_GTX_N == 1) begin
up_es_drp_wdata <= {up_es_hoffset, up_es_hoffset_rdata[3:0]};
end else begin
up_es_drp_wdata <= {up_es_hoffset_rdata[15:12], up_es_hoffset};
end
end
ES_FSM_VOFFSET_READ: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b0;
up_es_drp_addr <= ES_DRP_VOFFSET_ADDR;
up_es_drp_wdata <= 16'h0000;
end
ES_FSM_VOFFSET_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_VOFFSET_ADDR;
if (GTH_OR_GTX_N == 1) begin
up_es_drp_wdata <= {up_es_voffset_rdata[15:11], up_es_voffset_s[7],
up_es_ut_s, up_es_voffset_s[6:0], up_es_voffset_range};
end else begin
up_es_drp_wdata <= {up_es_prescale, up_es_voffset_rdata[10:9],
up_es_ut_s, up_es_voffset_s};
end
end
ES_FSM_CTRLSTART_READ: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b0;
up_es_drp_addr <= ES_DRP_CTRL_ADDR;
up_es_drp_wdata <= 16'h0000;
end
ES_FSM_CTRLSTART_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_CTRL_ADDR;
if (GTH_OR_GTX_N == 1) begin
up_es_drp_wdata <= {6'd1, up_es_ctrl_rdata[9:0]};
end else begin
up_es_drp_wdata <= {up_es_ctrl_rdata[15:6], 6'd1};
end
end
ES_FSM_STATUS_READ: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b0;
up_es_drp_addr <= ES_DRP_STATUS_ADDR;
up_es_drp_wdata <= 16'h0000;
end
ES_FSM_CTRLSTOP_READ: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b0;
up_es_drp_addr <= ES_DRP_CTRL_ADDR;
up_es_drp_wdata <= 16'h0000;
end
ES_FSM_CTRLSTOP_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_CTRL_ADDR;
if (GTH_OR_GTX_N == 1) begin
up_es_drp_wdata <= {6'd0, up_es_ctrl_rdata[9:0]};
end else begin
up_es_drp_wdata <= {up_es_ctrl_rdata[15:6], 6'd0};
end
end
ES_FSM_SCNT_READ: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b0;
up_es_drp_addr <= ES_DRP_SCNT_ADDR;
up_es_drp_wdata <= 16'h0000;
end
ES_FSM_ECNT_READ: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b0;
up_es_drp_addr <= ES_DRP_ECNT_ADDR;
up_es_drp_wdata <= 16'h0000;
end
default: begin
up_es_drp_sel <= 1'b0;
up_es_drp_wr <= 1'b0;
up_es_drp_addr <= 9'h000;
up_es_drp_wdata <= 16'h0000;
end
endcase
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EINVN_BLACKBOX_V
`define SKY130_FD_SC_LS__EINVN_BLACKBOX_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__einvn (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__EINVN_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21BA_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__O21BA_PP_BLACKBOX_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o21ba (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21BA_PP_BLACKBOX_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 25 15:17:13 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_inverter_0_0/system_inverter_0_0_sim_netlist.v
// Design : system_inverter_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_inverter_0_0,inverter,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "inverter,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_inverter_0_0
(x,
x_not);
input x;
output x_not;
wire x;
wire x_not;
LUT1 #(
.INIT(2'h1))
x_not_INST_0
(.I0(x),
.O(x_not));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A311O_4_V
`define SKY130_FD_SC_MS__A311O_4_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog wrapper for a311o with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a311o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a311o_4 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a311o_4 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A311O_4_V
|
// lab3_master_0.v
// This file was auto-generated from altera_jtag_avalon_master_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 13.1.1 166 at 2014.04.26.23:17:38
`timescale 1 ps / 1 ps
module lab3_master_0 #(
parameter USE_PLI = 0,
parameter PLI_PORT = 50000,
parameter FIFO_DEPTHS = 2
) (
input wire clk_clk, // clk.clk
input wire clk_reset_reset, // clk_reset.reset
output wire [31:0] master_address, // master.address
input wire [31:0] master_readdata, // .readdata
output wire master_read, // .read
output wire master_write, // .write
output wire [31:0] master_writedata, // .writedata
input wire master_waitrequest, // .waitrequest
input wire master_readdatavalid, // .readdatavalid
output wire [3:0] master_byteenable, // .byteenable
output wire master_reset_reset // master_reset.reset
);
wire jtag_phy_embedded_in_jtag_master_src_valid; // jtag_phy_embedded_in_jtag_master:source_valid -> timing_adt:in_valid
wire [7:0] jtag_phy_embedded_in_jtag_master_src_data; // jtag_phy_embedded_in_jtag_master:source_data -> timing_adt:in_data
wire timing_adt_out_valid; // timing_adt:out_valid -> fifo:in_valid
wire [7:0] timing_adt_out_data; // timing_adt:out_data -> fifo:in_data
wire timing_adt_out_ready; // fifo:in_ready -> timing_adt:out_ready
wire fifo_out_valid; // fifo:out_valid -> b2p:in_valid
wire [7:0] fifo_out_data; // fifo:out_data -> b2p:in_data
wire fifo_out_ready; // b2p:in_ready -> fifo:out_ready
wire b2p_out_packets_stream_endofpacket; // b2p:out_endofpacket -> b2p_adapter:in_endofpacket
wire b2p_out_packets_stream_valid; // b2p:out_valid -> b2p_adapter:in_valid
wire b2p_out_packets_stream_startofpacket; // b2p:out_startofpacket -> b2p_adapter:in_startofpacket
wire [7:0] b2p_out_packets_stream_data; // b2p:out_data -> b2p_adapter:in_data
wire b2p_out_packets_stream_ready; // b2p_adapter:in_ready -> b2p:out_ready
wire [7:0] b2p_out_packets_stream_channel; // b2p:out_channel -> b2p_adapter:in_channel
wire b2p_adapter_out_endofpacket; // b2p_adapter:out_endofpacket -> transacto:in_endofpacket
wire b2p_adapter_out_valid; // b2p_adapter:out_valid -> transacto:in_valid
wire b2p_adapter_out_startofpacket; // b2p_adapter:out_startofpacket -> transacto:in_startofpacket
wire [7:0] b2p_adapter_out_data; // b2p_adapter:out_data -> transacto:in_data
wire b2p_adapter_out_ready; // transacto:in_ready -> b2p_adapter:out_ready
wire transacto_out_stream_endofpacket; // transacto:out_endofpacket -> p2b_adapter:in_endofpacket
wire transacto_out_stream_valid; // transacto:out_valid -> p2b_adapter:in_valid
wire transacto_out_stream_startofpacket; // transacto:out_startofpacket -> p2b_adapter:in_startofpacket
wire [7:0] transacto_out_stream_data; // transacto:out_data -> p2b_adapter:in_data
wire transacto_out_stream_ready; // p2b_adapter:in_ready -> transacto:out_ready
wire p2b_adapter_out_endofpacket; // p2b_adapter:out_endofpacket -> p2b:in_endofpacket
wire p2b_adapter_out_valid; // p2b_adapter:out_valid -> p2b:in_valid
wire p2b_adapter_out_startofpacket; // p2b_adapter:out_startofpacket -> p2b:in_startofpacket
wire [7:0] p2b_adapter_out_data; // p2b_adapter:out_data -> p2b:in_data
wire [7:0] p2b_adapter_out_channel; // p2b_adapter:out_channel -> p2b:in_channel
wire p2b_adapter_out_ready; // p2b:in_ready -> p2b_adapter:out_ready
wire p2b_out_bytes_stream_valid; // p2b:out_valid -> jtag_phy_embedded_in_jtag_master:sink_valid
wire [7:0] p2b_out_bytes_stream_data; // p2b:out_data -> jtag_phy_embedded_in_jtag_master:sink_data
wire p2b_out_bytes_stream_ready; // jtag_phy_embedded_in_jtag_master:sink_ready -> p2b:out_ready
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [b2p:reset_n, b2p_adapter:reset_n, fifo:reset, jtag_phy_embedded_in_jtag_master:reset_n, p2b:reset_n, p2b_adapter:reset_n, timing_adt:reset_n, transacto:reset_n]
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (USE_PLI != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
use_pli_check ( .error(1'b1) );
end
if (PLI_PORT != 50000)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
pli_port_check ( .error(1'b1) );
end
if (FIFO_DEPTHS != 2)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
fifo_depths_check ( .error(1'b1) );
end
endgenerate
altera_avalon_st_jtag_interface #(
.PURPOSE (1),
.UPSTREAM_FIFO_SIZE (0),
.DOWNSTREAM_FIFO_SIZE (64),
.MGMT_CHANNEL_WIDTH (-1),
.USE_PLI (0),
.PLI_PORT (50000)
) jtag_phy_embedded_in_jtag_master (
.clk (clk_clk), // clock.clk
.reset_n (~rst_controller_reset_out_reset), // clock_reset.reset_n
.source_data (jtag_phy_embedded_in_jtag_master_src_data), // src.data
.source_valid (jtag_phy_embedded_in_jtag_master_src_valid), // .valid
.sink_data (p2b_out_bytes_stream_data), // sink.data
.sink_valid (p2b_out_bytes_stream_valid), // .valid
.sink_ready (p2b_out_bytes_stream_ready), // .ready
.resetrequest (master_reset_reset) // resetrequest.reset
);
lab3_master_0_timing_adt timing_adt (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.in_valid (jtag_phy_embedded_in_jtag_master_src_valid), // in.valid
.in_data (jtag_phy_embedded_in_jtag_master_src_data), // .data
.out_valid (timing_adt_out_valid), // out.valid
.out_data (timing_adt_out_data), // .data
.out_ready (timing_adt_out_ready) // .ready
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (8),
.FIFO_DEPTH (64),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (3),
.USE_MEMORY_BLOCKS (1),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) fifo (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (timing_adt_out_data), // in.data
.in_valid (timing_adt_out_valid), // .valid
.in_ready (timing_adt_out_ready), // .ready
.out_data (fifo_out_data), // out.data
.out_valid (fifo_out_valid), // .valid
.out_ready (fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_st_bytes_to_packets #(
.CHANNEL_WIDTH (8),
.ENCODING (0)
) b2p (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // clk_reset.reset_n
.out_channel (b2p_out_packets_stream_channel), // out_packets_stream.channel
.out_ready (b2p_out_packets_stream_ready), // .ready
.out_valid (b2p_out_packets_stream_valid), // .valid
.out_data (b2p_out_packets_stream_data), // .data
.out_startofpacket (b2p_out_packets_stream_startofpacket), // .startofpacket
.out_endofpacket (b2p_out_packets_stream_endofpacket), // .endofpacket
.in_ready (fifo_out_ready), // in_bytes_stream.ready
.in_valid (fifo_out_valid), // .valid
.in_data (fifo_out_data) // .data
);
altera_avalon_st_packets_to_bytes #(
.CHANNEL_WIDTH (8),
.ENCODING (0)
) p2b (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // clk_reset.reset_n
.in_ready (p2b_adapter_out_ready), // in_packets_stream.ready
.in_valid (p2b_adapter_out_valid), // .valid
.in_data (p2b_adapter_out_data), // .data
.in_channel (p2b_adapter_out_channel), // .channel
.in_startofpacket (p2b_adapter_out_startofpacket), // .startofpacket
.in_endofpacket (p2b_adapter_out_endofpacket), // .endofpacket
.out_ready (p2b_out_bytes_stream_ready), // out_bytes_stream.ready
.out_valid (p2b_out_bytes_stream_valid), // .valid
.out_data (p2b_out_bytes_stream_data) // .data
);
altera_avalon_packets_to_master #(
.FAST_VER (0),
.FIFO_DEPTHS (2),
.FIFO_WIDTHU (1)
) transacto (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // clk_reset.reset_n
.out_ready (transacto_out_stream_ready), // out_stream.ready
.out_valid (transacto_out_stream_valid), // .valid
.out_data (transacto_out_stream_data), // .data
.out_startofpacket (transacto_out_stream_startofpacket), // .startofpacket
.out_endofpacket (transacto_out_stream_endofpacket), // .endofpacket
.in_ready (b2p_adapter_out_ready), // in_stream.ready
.in_valid (b2p_adapter_out_valid), // .valid
.in_data (b2p_adapter_out_data), // .data
.in_startofpacket (b2p_adapter_out_startofpacket), // .startofpacket
.in_endofpacket (b2p_adapter_out_endofpacket), // .endofpacket
.address (master_address), // avalon_master.address
.readdata (master_readdata), // .readdata
.read (master_read), // .read
.write (master_write), // .write
.writedata (master_writedata), // .writedata
.waitrequest (master_waitrequest), // .waitrequest
.readdatavalid (master_readdatavalid), // .readdatavalid
.byteenable (master_byteenable) // .byteenable
);
lab3_master_0_b2p_adapter b2p_adapter (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.in_ready (b2p_out_packets_stream_ready), // in.ready
.in_valid (b2p_out_packets_stream_valid), // .valid
.in_data (b2p_out_packets_stream_data), // .data
.in_channel (b2p_out_packets_stream_channel), // .channel
.in_startofpacket (b2p_out_packets_stream_startofpacket), // .startofpacket
.in_endofpacket (b2p_out_packets_stream_endofpacket), // .endofpacket
.out_ready (b2p_adapter_out_ready), // out.ready
.out_valid (b2p_adapter_out_valid), // .valid
.out_data (b2p_adapter_out_data), // .data
.out_startofpacket (b2p_adapter_out_startofpacket), // .startofpacket
.out_endofpacket (b2p_adapter_out_endofpacket) // .endofpacket
);
lab3_master_0_p2b_adapter p2b_adapter (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.in_ready (transacto_out_stream_ready), // in.ready
.in_valid (transacto_out_stream_valid), // .valid
.in_data (transacto_out_stream_data), // .data
.in_startofpacket (transacto_out_stream_startofpacket), // .startofpacket
.in_endofpacket (transacto_out_stream_endofpacket), // .endofpacket
.out_ready (p2b_adapter_out_ready), // out.ready
.out_valid (p2b_adapter_out_valid), // .valid
.out_data (p2b_adapter_out_data), // .data
.out_startofpacket (p2b_adapter_out_startofpacket), // .startofpacket
.out_endofpacket (p2b_adapter_out_endofpacket), // .endofpacket
.out_channel (p2b_adapter_out_channel) // .channel
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (clk_reset_reset), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O32A_2_V
`define SKY130_FD_SC_HS__O32A_2_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog wrapper for o32a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o32a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o32a_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o32a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o32a_2 (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o32a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O32A_2_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/25 08:06:58
// Design Name:
// Module Name: Parallel_in_serial_out_load_enable_behavior_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Parallel_in_serial_out_load_enable_behavior_tb(
);
reg [3:0] ParallelIn;
reg Clk, ShiftIn, load, ShiftEn;
wire [3:0] RegContent;
wire ShiftOut;
Parallel_in_serial_out_load_enable_behavior DUT (.Clk(Clk), .ShiftIn(ShiftIn), .ParallelIn(ParallelIn), .load(load), .ShiftEn(ShiftEn), .ShiftOut(ShiftOut), .RegContent(RegContent));
initial begin
#300 $finish;
end
initial begin
Clk = 0; ShiftIn = 1; ParallelIn = 0; load = 0; ShiftEn = 0;
#10 Clk = 1;
#10 Clk = 0; ParallelIn = 4'b0101;
#10 Clk = 1;
#10 Clk = 0;
#10 Clk = 1; // 50ns
#10 Clk = 0; load = 1;
#10 Clk = 1;
#10 Clk = 0; load = 0;
#10 Clk = 1;
#10 Clk = 0; ShiftEn = 1;// 100ns
#10 Clk = 1;
#10 Clk = 0;
#10 Clk = 1;
#10 Clk = 0;
#10 Clk = 1; // 150ns
#10 Clk = 0;
#10 Clk = 1;
#10 Clk = 0; ParallelIn = 4'b1001;
#10 Clk = 1;
#10 Clk = 0; load = 1;// 200ns
#10 Clk = 1;
#10 Clk = 0; load = 0;
#10 Clk = 1;
#10 Clk = 0;
#10 Clk = 1; //250ns
#10 Clk = 0;
#10 Clk = 1;
#5 load = 1;
#5 Clk = 0;
#10 Clk = 1;
#5 load = 0;
#5 Clk = 0; // 300ns
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DFF_PR_PP_PG_N_BLACKBOX_V
`define SKY130_FD_SC_LP__UDP_DFF_PR_PP_PG_N_BLACKBOX_V
/**
* udp_dff$PR_pp$PG$N: Positive edge triggered D flip-flop with active
* high
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_dff$PR_pp$PG$N (
Q ,
D ,
CLK ,
RESET ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input D ;
input CLK ;
input RESET ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DFF_PR_PP_PG_N_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A2BB2OI_1_V
`define SKY130_FD_SC_HD__A2BB2OI_1_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog wrapper for a2bb2oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a2bb2oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a2bb2oi_1 (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a2bb2oi_1 (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A2BB2OI_1_V
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.1 (win64) Build 1846317 Fri Apr 14 18:55:03 MDT 2017
// Date : Thu Aug 24 05:36:23 2017
// Host : ACER-BLUES running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// D:/Design_Project/E_elements/Project_BipedRobot/Project_BipedRobot.srcs/sources_1/ip/fifo_EEPROM/fifo_EEPROM_sim_netlist.v
// Design : fifo_EEPROM
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcsg324-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "fifo_EEPROM,fifo_generator_v13_1_4,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "fifo_generator_v13_1_4,Vivado 2017.1" *)
(* NotValidForBitStream *)
module fifo_EEPROM
(rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty);
input rst;
(* x_interface_info = "xilinx.com:signal:clock:1.0 write_clk CLK" *) input wr_clk;
(* x_interface_info = "xilinx.com:signal:clock:1.0 read_clk CLK" *) input rd_clk;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *) input [7:0]din;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *) input wr_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *) input rd_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *) output [7:0]dout;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *) output full;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *) output empty;
wire [7:0]din;
wire [7:0]dout;
wire empty;
wire full;
wire rd_clk;
wire rd_en;
wire rst;
wire wr_clk;
wire wr_en;
wire NLW_U0_almost_empty_UNCONNECTED;
wire NLW_U0_almost_full_UNCONNECTED;
wire NLW_U0_axi_ar_dbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_overflow_UNCONNECTED;
wire NLW_U0_axi_ar_prog_empty_UNCONNECTED;
wire NLW_U0_axi_ar_prog_full_UNCONNECTED;
wire NLW_U0_axi_ar_sbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_underflow_UNCONNECTED;
wire NLW_U0_axi_aw_dbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_overflow_UNCONNECTED;
wire NLW_U0_axi_aw_prog_empty_UNCONNECTED;
wire NLW_U0_axi_aw_prog_full_UNCONNECTED;
wire NLW_U0_axi_aw_sbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_underflow_UNCONNECTED;
wire NLW_U0_axi_b_dbiterr_UNCONNECTED;
wire NLW_U0_axi_b_overflow_UNCONNECTED;
wire NLW_U0_axi_b_prog_empty_UNCONNECTED;
wire NLW_U0_axi_b_prog_full_UNCONNECTED;
wire NLW_U0_axi_b_sbiterr_UNCONNECTED;
wire NLW_U0_axi_b_underflow_UNCONNECTED;
wire NLW_U0_axi_r_dbiterr_UNCONNECTED;
wire NLW_U0_axi_r_overflow_UNCONNECTED;
wire NLW_U0_axi_r_prog_empty_UNCONNECTED;
wire NLW_U0_axi_r_prog_full_UNCONNECTED;
wire NLW_U0_axi_r_sbiterr_UNCONNECTED;
wire NLW_U0_axi_r_underflow_UNCONNECTED;
wire NLW_U0_axi_w_dbiterr_UNCONNECTED;
wire NLW_U0_axi_w_overflow_UNCONNECTED;
wire NLW_U0_axi_w_prog_empty_UNCONNECTED;
wire NLW_U0_axi_w_prog_full_UNCONNECTED;
wire NLW_U0_axi_w_sbiterr_UNCONNECTED;
wire NLW_U0_axi_w_underflow_UNCONNECTED;
wire NLW_U0_axis_dbiterr_UNCONNECTED;
wire NLW_U0_axis_overflow_UNCONNECTED;
wire NLW_U0_axis_prog_empty_UNCONNECTED;
wire NLW_U0_axis_prog_full_UNCONNECTED;
wire NLW_U0_axis_sbiterr_UNCONNECTED;
wire NLW_U0_axis_underflow_UNCONNECTED;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_m_axi_arvalid_UNCONNECTED;
wire NLW_U0_m_axi_awvalid_UNCONNECTED;
wire NLW_U0_m_axi_bready_UNCONNECTED;
wire NLW_U0_m_axi_rready_UNCONNECTED;
wire NLW_U0_m_axi_wlast_UNCONNECTED;
wire NLW_U0_m_axi_wvalid_UNCONNECTED;
wire NLW_U0_m_axis_tlast_UNCONNECTED;
wire NLW_U0_m_axis_tvalid_UNCONNECTED;
wire NLW_U0_overflow_UNCONNECTED;
wire NLW_U0_prog_empty_UNCONNECTED;
wire NLW_U0_prog_full_UNCONNECTED;
wire NLW_U0_rd_rst_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_s_axis_tready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire NLW_U0_underflow_UNCONNECTED;
wire NLW_U0_valid_UNCONNECTED;
wire NLW_U0_wr_ack_UNCONNECTED;
wire NLW_U0_wr_rst_busy_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_wr_data_count_UNCONNECTED;
wire [5:0]NLW_U0_data_count_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_araddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_arburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_arlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_aruser_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_awaddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_awburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_awlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awuser_UNCONNECTED;
wire [63:0]NLW_U0_m_axi_wdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_wstrb_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wuser_UNCONNECTED;
wire [7:0]NLW_U0_m_axis_tdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tdest_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tid_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tkeep_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tstrb_UNCONNECTED;
wire [3:0]NLW_U0_m_axis_tuser_UNCONNECTED;
wire [5:0]NLW_U0_rd_data_count_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_buser_UNCONNECTED;
wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_ruser_UNCONNECTED;
wire [5:0]NLW_U0_wr_data_count_UNCONNECTED;
(* C_ADD_NGC_CONSTRAINT = "0" *)
(* C_APPLICATION_TYPE_AXIS = "0" *)
(* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *)
(* C_APPLICATION_TYPE_WACH = "0" *)
(* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *)
(* C_AXIS_TDATA_WIDTH = "8" *)
(* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *)
(* C_AXIS_TKEEP_WIDTH = "1" *)
(* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *)
(* C_AXIS_TYPE = "0" *)
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *)
(* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_COMMON_CLOCK = "0" *)
(* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "6" *)
(* C_DEFAULT_VALUE = "BlankString" *)
(* C_DIN_WIDTH = "8" *)
(* C_DIN_WIDTH_AXIS = "1" *)
(* C_DIN_WIDTH_RACH = "32" *)
(* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "1" *)
(* C_DIN_WIDTH_WDCH = "64" *)
(* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *)
(* C_DOUT_WIDTH = "8" *)
(* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *)
(* C_ERROR_INJECTION_TYPE_RACH = "0" *)
(* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *)
(* C_ERROR_INJECTION_TYPE_WDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "artix7" *)
(* C_FULL_FLAGS_RST_VAL = "1" *)
(* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *)
(* C_HAS_AXIS_TDATA = "1" *)
(* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *)
(* C_HAS_AXIS_TKEEP = "0" *)
(* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *)
(* C_HAS_AXIS_TSTRB = "0" *)
(* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *)
(* C_HAS_AXI_AWUSER = "0" *)
(* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_AXI_RD_CHANNEL = "1" *)
(* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *)
(* C_HAS_AXI_WUSER = "0" *)
(* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *)
(* C_HAS_DATA_COUNTS_AXIS = "0" *)
(* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *)
(* C_HAS_DATA_COUNTS_WACH = "0" *)
(* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *)
(* C_HAS_INT_CLK = "0" *)
(* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *)
(* C_HAS_OVERFLOW = "0" *)
(* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *)
(* C_HAS_PROG_FLAGS_RDCH = "0" *)
(* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *)
(* C_HAS_PROG_FLAGS_WRCH = "0" *)
(* C_HAS_RD_DATA_COUNT = "0" *)
(* C_HAS_RD_RST = "0" *)
(* C_HAS_RST = "1" *)
(* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "0" *)
(* C_HAS_UNDERFLOW = "0" *)
(* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *)
(* C_HAS_WR_DATA_COUNT = "0" *)
(* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "2" *)
(* C_IMPLEMENTATION_TYPE_AXIS = "1" *)
(* C_IMPLEMENTATION_TYPE_RACH = "1" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WACH = "1" *)
(* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "1" *)
(* C_INIT_WR_PNTR_VAL = "0" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "1" *)
(* C_MIF_FILE_NAME = "BlankString" *)
(* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *)
(* C_OVERFLOW_LOW = "0" *)
(* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "1" *)
(* C_PRELOAD_REGS = "0" *)
(* C_PRIM_FIFO_TYPE = "512x36" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *)
(* C_PRIM_FIFO_TYPE_RACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *)
(* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *)
(* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *)
(* C_PROG_EMPTY_TYPE_RACH = "0" *)
(* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *)
(* C_PROG_EMPTY_TYPE_WDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "61" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *)
(* C_PROG_FULL_THRESH_NEGATE_VAL = "60" *)
(* C_PROG_FULL_TYPE = "0" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *)
(* C_PROG_FULL_TYPE_RACH = "0" *)
(* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *)
(* C_PROG_FULL_TYPE_WDCH = "0" *)
(* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *)
(* C_RDCH_TYPE = "0" *)
(* C_RD_DATA_COUNT_WIDTH = "6" *)
(* C_RD_DEPTH = "64" *)
(* C_RD_FREQ = "1" *)
(* C_RD_PNTR_WIDTH = "6" *)
(* C_REG_SLICE_MODE_AXIS = "0" *)
(* C_REG_SLICE_MODE_RACH = "0" *)
(* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *)
(* C_REG_SLICE_MODE_WDCH = "0" *)
(* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SELECT_XPM = "0" *)
(* C_SYNCHRONIZER_STAGE = "2" *)
(* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *)
(* C_USE_COMMON_UNDERFLOW = "0" *)
(* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *)
(* C_USE_ECC = "0" *)
(* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *)
(* C_USE_ECC_RDCH = "0" *)
(* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *)
(* C_USE_ECC_WRCH = "0" *)
(* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *)
(* C_USE_FWFT_DATA_COUNT = "0" *)
(* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *)
(* C_WACH_TYPE = "0" *)
(* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *)
(* C_WR_ACK_LOW = "0" *)
(* C_WR_DATA_COUNT_WIDTH = "6" *)
(* C_WR_DEPTH = "64" *)
(* C_WR_DEPTH_AXIS = "1024" *)
(* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "1024" *)
(* C_WR_DEPTH_WACH = "16" *)
(* C_WR_DEPTH_WDCH = "1024" *)
(* C_WR_DEPTH_WRCH = "16" *)
(* C_WR_FREQ = "1" *)
(* C_WR_PNTR_WIDTH = "6" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *)
(* C_WR_PNTR_WIDTH_RACH = "4" *)
(* C_WR_PNTR_WIDTH_RDCH = "10" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *)
(* C_WR_PNTR_WIDTH_WDCH = "10" *)
(* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *)
fifo_EEPROM_fifo_generator_v13_1_4 U0
(.almost_empty(NLW_U0_almost_empty_UNCONNECTED),
.almost_full(NLW_U0_almost_full_UNCONNECTED),
.axi_ar_data_count(NLW_U0_axi_ar_data_count_UNCONNECTED[4:0]),
.axi_ar_dbiterr(NLW_U0_axi_ar_dbiterr_UNCONNECTED),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_injectsbiterr(1'b0),
.axi_ar_overflow(NLW_U0_axi_ar_overflow_UNCONNECTED),
.axi_ar_prog_empty(NLW_U0_axi_ar_prog_empty_UNCONNECTED),
.axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_prog_full(NLW_U0_axi_ar_prog_full_UNCONNECTED),
.axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_rd_data_count(NLW_U0_axi_ar_rd_data_count_UNCONNECTED[4:0]),
.axi_ar_sbiterr(NLW_U0_axi_ar_sbiterr_UNCONNECTED),
.axi_ar_underflow(NLW_U0_axi_ar_underflow_UNCONNECTED),
.axi_ar_wr_data_count(NLW_U0_axi_ar_wr_data_count_UNCONNECTED[4:0]),
.axi_aw_data_count(NLW_U0_axi_aw_data_count_UNCONNECTED[4:0]),
.axi_aw_dbiterr(NLW_U0_axi_aw_dbiterr_UNCONNECTED),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_overflow(NLW_U0_axi_aw_overflow_UNCONNECTED),
.axi_aw_prog_empty(NLW_U0_axi_aw_prog_empty_UNCONNECTED),
.axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_prog_full(NLW_U0_axi_aw_prog_full_UNCONNECTED),
.axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_rd_data_count(NLW_U0_axi_aw_rd_data_count_UNCONNECTED[4:0]),
.axi_aw_sbiterr(NLW_U0_axi_aw_sbiterr_UNCONNECTED),
.axi_aw_underflow(NLW_U0_axi_aw_underflow_UNCONNECTED),
.axi_aw_wr_data_count(NLW_U0_axi_aw_wr_data_count_UNCONNECTED[4:0]),
.axi_b_data_count(NLW_U0_axi_b_data_count_UNCONNECTED[4:0]),
.axi_b_dbiterr(NLW_U0_axi_b_dbiterr_UNCONNECTED),
.axi_b_injectdbiterr(1'b0),
.axi_b_injectsbiterr(1'b0),
.axi_b_overflow(NLW_U0_axi_b_overflow_UNCONNECTED),
.axi_b_prog_empty(NLW_U0_axi_b_prog_empty_UNCONNECTED),
.axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_prog_full(NLW_U0_axi_b_prog_full_UNCONNECTED),
.axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_rd_data_count(NLW_U0_axi_b_rd_data_count_UNCONNECTED[4:0]),
.axi_b_sbiterr(NLW_U0_axi_b_sbiterr_UNCONNECTED),
.axi_b_underflow(NLW_U0_axi_b_underflow_UNCONNECTED),
.axi_b_wr_data_count(NLW_U0_axi_b_wr_data_count_UNCONNECTED[4:0]),
.axi_r_data_count(NLW_U0_axi_r_data_count_UNCONNECTED[10:0]),
.axi_r_dbiterr(NLW_U0_axi_r_dbiterr_UNCONNECTED),
.axi_r_injectdbiterr(1'b0),
.axi_r_injectsbiterr(1'b0),
.axi_r_overflow(NLW_U0_axi_r_overflow_UNCONNECTED),
.axi_r_prog_empty(NLW_U0_axi_r_prog_empty_UNCONNECTED),
.axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_prog_full(NLW_U0_axi_r_prog_full_UNCONNECTED),
.axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_rd_data_count(NLW_U0_axi_r_rd_data_count_UNCONNECTED[10:0]),
.axi_r_sbiterr(NLW_U0_axi_r_sbiterr_UNCONNECTED),
.axi_r_underflow(NLW_U0_axi_r_underflow_UNCONNECTED),
.axi_r_wr_data_count(NLW_U0_axi_r_wr_data_count_UNCONNECTED[10:0]),
.axi_w_data_count(NLW_U0_axi_w_data_count_UNCONNECTED[10:0]),
.axi_w_dbiterr(NLW_U0_axi_w_dbiterr_UNCONNECTED),
.axi_w_injectdbiterr(1'b0),
.axi_w_injectsbiterr(1'b0),
.axi_w_overflow(NLW_U0_axi_w_overflow_UNCONNECTED),
.axi_w_prog_empty(NLW_U0_axi_w_prog_empty_UNCONNECTED),
.axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_prog_full(NLW_U0_axi_w_prog_full_UNCONNECTED),
.axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_rd_data_count(NLW_U0_axi_w_rd_data_count_UNCONNECTED[10:0]),
.axi_w_sbiterr(NLW_U0_axi_w_sbiterr_UNCONNECTED),
.axi_w_underflow(NLW_U0_axi_w_underflow_UNCONNECTED),
.axi_w_wr_data_count(NLW_U0_axi_w_wr_data_count_UNCONNECTED[10:0]),
.axis_data_count(NLW_U0_axis_data_count_UNCONNECTED[10:0]),
.axis_dbiterr(NLW_U0_axis_dbiterr_UNCONNECTED),
.axis_injectdbiterr(1'b0),
.axis_injectsbiterr(1'b0),
.axis_overflow(NLW_U0_axis_overflow_UNCONNECTED),
.axis_prog_empty(NLW_U0_axis_prog_empty_UNCONNECTED),
.axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_prog_full(NLW_U0_axis_prog_full_UNCONNECTED),
.axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_rd_data_count(NLW_U0_axis_rd_data_count_UNCONNECTED[10:0]),
.axis_sbiterr(NLW_U0_axis_sbiterr_UNCONNECTED),
.axis_underflow(NLW_U0_axis_underflow_UNCONNECTED),
.axis_wr_data_count(NLW_U0_axis_wr_data_count_UNCONNECTED[10:0]),
.backup(1'b0),
.backup_marker(1'b0),
.clk(1'b0),
.data_count(NLW_U0_data_count_UNCONNECTED[5:0]),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.int_clk(1'b0),
.m_aclk(1'b0),
.m_aclk_en(1'b0),
.m_axi_araddr(NLW_U0_m_axi_araddr_UNCONNECTED[31:0]),
.m_axi_arburst(NLW_U0_m_axi_arburst_UNCONNECTED[1:0]),
.m_axi_arcache(NLW_U0_m_axi_arcache_UNCONNECTED[3:0]),
.m_axi_arid(NLW_U0_m_axi_arid_UNCONNECTED[0]),
.m_axi_arlen(NLW_U0_m_axi_arlen_UNCONNECTED[7:0]),
.m_axi_arlock(NLW_U0_m_axi_arlock_UNCONNECTED[0]),
.m_axi_arprot(NLW_U0_m_axi_arprot_UNCONNECTED[2:0]),
.m_axi_arqos(NLW_U0_m_axi_arqos_UNCONNECTED[3:0]),
.m_axi_arready(1'b0),
.m_axi_arregion(NLW_U0_m_axi_arregion_UNCONNECTED[3:0]),
.m_axi_arsize(NLW_U0_m_axi_arsize_UNCONNECTED[2:0]),
.m_axi_aruser(NLW_U0_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(NLW_U0_m_axi_arvalid_UNCONNECTED),
.m_axi_awaddr(NLW_U0_m_axi_awaddr_UNCONNECTED[31:0]),
.m_axi_awburst(NLW_U0_m_axi_awburst_UNCONNECTED[1:0]),
.m_axi_awcache(NLW_U0_m_axi_awcache_UNCONNECTED[3:0]),
.m_axi_awid(NLW_U0_m_axi_awid_UNCONNECTED[0]),
.m_axi_awlen(NLW_U0_m_axi_awlen_UNCONNECTED[7:0]),
.m_axi_awlock(NLW_U0_m_axi_awlock_UNCONNECTED[0]),
.m_axi_awprot(NLW_U0_m_axi_awprot_UNCONNECTED[2:0]),
.m_axi_awqos(NLW_U0_m_axi_awqos_UNCONNECTED[3:0]),
.m_axi_awready(1'b0),
.m_axi_awregion(NLW_U0_m_axi_awregion_UNCONNECTED[3:0]),
.m_axi_awsize(NLW_U0_m_axi_awsize_UNCONNECTED[2:0]),
.m_axi_awuser(NLW_U0_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(NLW_U0_m_axi_awvalid_UNCONNECTED),
.m_axi_bid(1'b0),
.m_axi_bready(NLW_U0_m_axi_bready_UNCONNECTED),
.m_axi_bresp({1'b0,1'b0}),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rid(1'b0),
.m_axi_rlast(1'b0),
.m_axi_rready(NLW_U0_m_axi_rready_UNCONNECTED),
.m_axi_rresp({1'b0,1'b0}),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_wdata(NLW_U0_m_axi_wdata_UNCONNECTED[63:0]),
.m_axi_wid(NLW_U0_m_axi_wid_UNCONNECTED[0]),
.m_axi_wlast(NLW_U0_m_axi_wlast_UNCONNECTED),
.m_axi_wready(1'b0),
.m_axi_wstrb(NLW_U0_m_axi_wstrb_UNCONNECTED[7:0]),
.m_axi_wuser(NLW_U0_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(NLW_U0_m_axi_wvalid_UNCONNECTED),
.m_axis_tdata(NLW_U0_m_axis_tdata_UNCONNECTED[7:0]),
.m_axis_tdest(NLW_U0_m_axis_tdest_UNCONNECTED[0]),
.m_axis_tid(NLW_U0_m_axis_tid_UNCONNECTED[0]),
.m_axis_tkeep(NLW_U0_m_axis_tkeep_UNCONNECTED[0]),
.m_axis_tlast(NLW_U0_m_axis_tlast_UNCONNECTED),
.m_axis_tready(1'b0),
.m_axis_tstrb(NLW_U0_m_axis_tstrb_UNCONNECTED[0]),
.m_axis_tuser(NLW_U0_m_axis_tuser_UNCONNECTED[3:0]),
.m_axis_tvalid(NLW_U0_m_axis_tvalid_UNCONNECTED),
.overflow(NLW_U0_overflow_UNCONNECTED),
.prog_empty(NLW_U0_prog_empty_UNCONNECTED),
.prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full(NLW_U0_prog_full_UNCONNECTED),
.prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.rd_clk(rd_clk),
.rd_data_count(NLW_U0_rd_data_count_UNCONNECTED[5:0]),
.rd_en(rd_en),
.rd_rst(1'b0),
.rd_rst_busy(NLW_U0_rd_rst_busy_UNCONNECTED),
.rst(rst),
.s_aclk(1'b0),
.s_aclk_en(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arid(1'b0),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlock(1'b0),
.s_axi_arprot({1'b0,1'b0,1'b0}),
.s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awid(1'b0),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlock(1'b0),
.s_axi_awprot({1'b0,1'b0,1'b0}),
.s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_buser(NLW_U0_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_ruser(NLW_U0_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wid(1'b0),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axis_tdest(1'b0),
.s_axis_tid(1'b0),
.s_axis_tkeep(1'b0),
.s_axis_tlast(1'b0),
.s_axis_tready(NLW_U0_s_axis_tready_UNCONNECTED),
.s_axis_tstrb(1'b0),
.s_axis_tuser({1'b0,1'b0,1'b0,1'b0}),
.s_axis_tvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.sleep(1'b0),
.srst(1'b0),
.underflow(NLW_U0_underflow_UNCONNECTED),
.valid(NLW_U0_valid_UNCONNECTED),
.wr_ack(NLW_U0_wr_ack_UNCONNECTED),
.wr_clk(wr_clk),
.wr_data_count(NLW_U0_wr_data_count_UNCONNECTED[5:0]),
.wr_en(wr_en),
.wr_rst(1'b0),
.wr_rst_busy(NLW_U0_wr_rst_busy_UNCONNECTED));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module fifo_EEPROM_blk_mem_gen_generic_cstr
(dout,
rd_clk,
wr_clk,
tmp_ram_rd_en,
WEBWE,
out,
ADDRARDADDR,
Q,
din);
output [7:0]dout;
input rd_clk;
input wr_clk;
input tmp_ram_rd_en;
input [0:0]WEBWE;
input [0:0]out;
input [5:0]ADDRARDADDR;
input [5:0]Q;
input [7:0]din;
wire [5:0]ADDRARDADDR;
wire [5:0]Q;
wire [0:0]WEBWE;
wire [7:0]din;
wire [7:0]dout;
wire [0:0]out;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
fifo_EEPROM_blk_mem_gen_prim_width \ramloop[0].ram.r
(.ADDRARDADDR(ADDRARDADDR),
.Q(Q),
.WEBWE(WEBWE),
.din(din),
.dout(dout),
.out(out),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module fifo_EEPROM_blk_mem_gen_prim_width
(dout,
rd_clk,
wr_clk,
tmp_ram_rd_en,
WEBWE,
out,
ADDRARDADDR,
Q,
din);
output [7:0]dout;
input rd_clk;
input wr_clk;
input tmp_ram_rd_en;
input [0:0]WEBWE;
input [0:0]out;
input [5:0]ADDRARDADDR;
input [5:0]Q;
input [7:0]din;
wire [5:0]ADDRARDADDR;
wire [5:0]Q;
wire [0:0]WEBWE;
wire [7:0]din;
wire [7:0]dout;
wire [0:0]out;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
fifo_EEPROM_blk_mem_gen_prim_wrapper \prim_noinit.ram
(.ADDRARDADDR(ADDRARDADDR),
.Q(Q),
.WEBWE(WEBWE),
.din(din),
.dout(dout),
.out(out),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module fifo_EEPROM_blk_mem_gen_prim_wrapper
(dout,
rd_clk,
wr_clk,
tmp_ram_rd_en,
WEBWE,
out,
ADDRARDADDR,
Q,
din);
output [7:0]dout;
input rd_clk;
input wr_clk;
input tmp_ram_rd_en;
input [0:0]WEBWE;
input [0:0]out;
input [5:0]ADDRARDADDR;
input [5:0]Q;
input [7:0]din;
wire [5:0]ADDRARDADDR;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_1 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_10 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_11 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_12 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_13 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_16 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_17 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_18 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_19 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_2 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_20 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_21 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_24 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_25 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_26 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_27 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_28 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_29 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_3 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_32 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_33 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_34 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_35 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_4 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_5 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_8 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_9 ;
wire [5:0]Q;
wire [0:0]WEBWE;
wire [7:0]din;
wire [7:0]dout;
wire [0:0]out;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(0),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("SDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(0),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram
(.ADDRARDADDR({1'b0,1'b0,1'b0,ADDRARDADDR,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,Q,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CLKARDCLK(rd_clk),
.CLKBWRCLK(wr_clk),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[3:2],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[1:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:6],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[5:4]}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0}),
.DOADO({\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_0 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_1 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_2 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_3 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_4 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_5 ,dout[3:2],\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_8 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_9 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_10 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_11 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_12 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_13 ,dout[1:0]}),
.DOBDO({\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_16 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_17 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_18 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_19 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_20 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_21 ,dout[7:6],\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_24 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_25 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_26 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_27 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_28 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_29 ,dout[5:4]}),
.DOPADOP({\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_32 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_33 }),
.DOPBDOP({\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_34 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_35 }),
.ENARDEN(tmp_ram_rd_en),
.ENBWREN(WEBWE),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(out),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({1'b0,1'b0}),
.WEBWE({WEBWE,WEBWE,WEBWE,WEBWE}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module fifo_EEPROM_blk_mem_gen_top
(dout,
rd_clk,
wr_clk,
tmp_ram_rd_en,
WEBWE,
out,
ADDRARDADDR,
Q,
din);
output [7:0]dout;
input rd_clk;
input wr_clk;
input tmp_ram_rd_en;
input [0:0]WEBWE;
input [0:0]out;
input [5:0]ADDRARDADDR;
input [5:0]Q;
input [7:0]din;
wire [5:0]ADDRARDADDR;
wire [5:0]Q;
wire [0:0]WEBWE;
wire [7:0]din;
wire [7:0]dout;
wire [0:0]out;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
fifo_EEPROM_blk_mem_gen_generic_cstr \valid.cstr
(.ADDRARDADDR(ADDRARDADDR),
.Q(Q),
.WEBWE(WEBWE),
.din(din),
.dout(dout),
.out(out),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_3_6" *)
module fifo_EEPROM_blk_mem_gen_v8_3_6
(dout,
rd_clk,
wr_clk,
tmp_ram_rd_en,
WEBWE,
out,
ADDRARDADDR,
Q,
din);
output [7:0]dout;
input rd_clk;
input wr_clk;
input tmp_ram_rd_en;
input [0:0]WEBWE;
input [0:0]out;
input [5:0]ADDRARDADDR;
input [5:0]Q;
input [7:0]din;
wire [5:0]ADDRARDADDR;
wire [5:0]Q;
wire [0:0]WEBWE;
wire [7:0]din;
wire [7:0]dout;
wire [0:0]out;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
fifo_EEPROM_blk_mem_gen_v8_3_6_synth inst_blk_mem_gen
(.ADDRARDADDR(ADDRARDADDR),
.Q(Q),
.WEBWE(WEBWE),
.din(din),
.dout(dout),
.out(out),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_3_6_synth" *)
module fifo_EEPROM_blk_mem_gen_v8_3_6_synth
(dout,
rd_clk,
wr_clk,
tmp_ram_rd_en,
WEBWE,
out,
ADDRARDADDR,
Q,
din);
output [7:0]dout;
input rd_clk;
input wr_clk;
input tmp_ram_rd_en;
input [0:0]WEBWE;
input [0:0]out;
input [5:0]ADDRARDADDR;
input [5:0]Q;
input [7:0]din;
wire [5:0]ADDRARDADDR;
wire [5:0]Q;
wire [0:0]WEBWE;
wire [7:0]din;
wire [7:0]dout;
wire [0:0]out;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
fifo_EEPROM_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.ADDRARDADDR(ADDRARDADDR),
.Q(Q),
.WEBWE(WEBWE),
.din(din),
.dout(dout),
.out(out),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "clk_x_pntrs" *)
module fifo_EEPROM_clk_x_pntrs
(out,
ram_empty_fb_i_reg,
ram_empty_fb_i_reg_0,
ram_full_i_reg,
D,
Q,
\gc0.count_d1_reg[0] ,
rd_en,
ram_empty_fb_i_reg_1,
\gic0.gc0.count_d2_reg[5] ,
wr_clk,
AR,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ,
\gc0.count_d1_reg[5] );
output [5:0]out;
output ram_empty_fb_i_reg;
output [5:0]ram_empty_fb_i_reg_0;
output [5:0]ram_full_i_reg;
input [0:0]D;
input [5:0]Q;
input \gc0.count_d1_reg[0] ;
input rd_en;
input ram_empty_fb_i_reg_1;
input [5:0]\gic0.gc0.count_d2_reg[5] ;
input wr_clk;
input [0:0]AR;
input rd_clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
input [5:0]\gc0.count_d1_reg[5] ;
wire [0:0]AR;
wire [0:0]D;
wire [5:0]Q;
wire __2_n_0;
wire __3_n_0;
wire __4_n_0;
wire [4:0]bin2gray;
wire \gc0.count_d1_reg[0] ;
wire [5:0]\gc0.count_d1_reg[5] ;
wire [5:0]\gic0.gc0.count_d2_reg[5] ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ;
wire [3:1]gray2bin;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [5:0]out;
wire p_0_out;
wire [5:0]p_3_out;
wire [5:0]p_4_out;
wire [5:0]p_6_out;
wire ram_empty_fb_i_reg;
wire [5:0]ram_empty_fb_i_reg_0;
wire ram_empty_fb_i_reg_1;
wire ram_empty_i_i_2_n_0;
wire ram_empty_i_i_4_n_0;
wire [5:0]ram_full_i_reg;
wire rd_clk;
wire rd_en;
wire [5:0]rd_pntr_gc;
wire wr_clk;
wire [5:0]wr_pntr_gc;
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h96696996))
__0
(.I0(out[3]),
.I1(out[1]),
.I2(out[2]),
.I3(out[5]),
.I4(out[4]),
.O(gray2bin[1]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h6996))
__1
(.I0(out[3]),
.I1(out[2]),
.I2(out[5]),
.I3(out[4]),
.O(gray2bin[2]));
LUT6 #(
.INIT(64'h6996966996696996))
__2
(.I0(p_6_out[2]),
.I1(p_6_out[0]),
.I2(p_6_out[1]),
.I3(p_6_out[5]),
.I4(p_6_out[3]),
.I5(p_6_out[4]),
.O(__2_n_0));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h96696996))
__3
(.I0(p_6_out[3]),
.I1(p_6_out[1]),
.I2(p_6_out[2]),
.I3(p_6_out[5]),
.I4(p_6_out[4]),
.O(__3_n_0));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h6996))
__4
(.I0(p_6_out[3]),
.I1(p_6_out[2]),
.I2(p_6_out[5]),
.I3(p_6_out[4]),
.O(__4_n_0));
fifo_EEPROM_synchronizer_ff__parameterized0 \gnxpm_cdc.gsync_stage[1].rd_stg_inst
(.D(p_3_out),
.Q(wr_pntr_gc),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.rd_clk(rd_clk));
fifo_EEPROM_synchronizer_ff__parameterized0_3 \gnxpm_cdc.gsync_stage[1].wr_stg_inst
(.AR(AR),
.D(p_4_out),
.Q(rd_pntr_gc),
.wr_clk(wr_clk));
fifo_EEPROM_synchronizer_ff__parameterized0_4 \gnxpm_cdc.gsync_stage[2].rd_stg_inst
(.D({p_0_out,gray2bin[3]}),
.\Q_reg_reg[5]_0 (p_3_out),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.out(out),
.rd_clk(rd_clk));
fifo_EEPROM_synchronizer_ff__parameterized0_5 \gnxpm_cdc.gsync_stage[2].wr_stg_inst
(.AR(AR),
.D({\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 }),
.\Q_reg_reg[5]_0 (p_4_out),
.out(p_6_out),
.wr_clk(wr_clk));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(__2_n_0),
.Q(ram_full_i_reg[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(__3_n_0),
.Q(ram_full_i_reg[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(__4_n_0),
.Q(ram_full_i_reg[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ),
.Q(ram_full_i_reg[3]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ),
.Q(ram_full_i_reg[4]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(p_6_out[5]),
.Q(ram_full_i_reg[5]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gc0.count_d1_reg[5] [0]),
.Q(rd_pntr_gc[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gc0.count_d1_reg[5] [1]),
.Q(rd_pntr_gc[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gc0.count_d1_reg[5] [2]),
.Q(rd_pntr_gc[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gc0.count_d1_reg[5] [3]),
.Q(rd_pntr_gc[3]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gc0.count_d1_reg[5] [4]),
.Q(rd_pntr_gc[4]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gc0.count_d1_reg[5] [5]),
.Q(rd_pntr_gc[5]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D),
.Q(ram_empty_fb_i_reg_0[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin[1]),
.Q(ram_empty_fb_i_reg_0[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin[2]),
.Q(ram_empty_fb_i_reg_0[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin[3]),
.Q(ram_empty_fb_i_reg_0[3]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_out),
.Q(ram_empty_fb_i_reg_0[4]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(out[5]),
.Q(ram_empty_fb_i_reg_0[5]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[0]_i_1
(.I0(\gic0.gc0.count_d2_reg[5] [0]),
.I1(\gic0.gc0.count_d2_reg[5] [1]),
.O(bin2gray[0]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[1]_i_1
(.I0(\gic0.gc0.count_d2_reg[5] [1]),
.I1(\gic0.gc0.count_d2_reg[5] [2]),
.O(bin2gray[1]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[2]_i_1
(.I0(\gic0.gc0.count_d2_reg[5] [2]),
.I1(\gic0.gc0.count_d2_reg[5] [3]),
.O(bin2gray[2]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[3]_i_1
(.I0(\gic0.gc0.count_d2_reg[5] [3]),
.I1(\gic0.gc0.count_d2_reg[5] [4]),
.O(bin2gray[3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[4]_i_1
(.I0(\gic0.gc0.count_d2_reg[5] [4]),
.I1(\gic0.gc0.count_d2_reg[5] [5]),
.O(bin2gray[4]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[0]),
.Q(wr_pntr_gc[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[1]),
.Q(wr_pntr_gc[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[2]),
.Q(wr_pntr_gc[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[3]),
.Q(wr_pntr_gc[3]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[4]),
.Q(wr_pntr_gc[4]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[5] [5]),
.Q(wr_pntr_gc[5]));
LUT6 #(
.INIT(64'hFFFFFFFF82000082))
ram_empty_i_i_1
(.I0(ram_empty_i_i_2_n_0),
.I1(Q[0]),
.I2(ram_empty_fb_i_reg_0[0]),
.I3(Q[1]),
.I4(ram_empty_fb_i_reg_0[1]),
.I5(\gc0.count_d1_reg[0] ),
.O(ram_empty_fb_i_reg));
LUT5 #(
.INIT(32'h00008200))
ram_empty_i_i_2
(.I0(ram_empty_i_i_4_n_0),
.I1(ram_empty_fb_i_reg_0[5]),
.I2(Q[5]),
.I3(rd_en),
.I4(ram_empty_fb_i_reg_1),
.O(ram_empty_i_i_2_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
ram_empty_i_i_4
(.I0(ram_empty_fb_i_reg_0[4]),
.I1(Q[4]),
.I2(ram_empty_fb_i_reg_0[3]),
.I3(Q[3]),
.I4(Q[2]),
.I5(ram_empty_fb_i_reg_0[2]),
.O(ram_empty_i_i_4_n_0));
endmodule
(* ORIG_REF_NAME = "fifo_generator_ramfifo" *)
module fifo_EEPROM_fifo_generator_ramfifo
(wr_rst_busy,
dout,
empty,
full,
wr_en,
rd_clk,
wr_clk,
din,
rst,
rd_en);
output wr_rst_busy;
output [7:0]dout;
output empty;
output full;
input wr_en;
input rd_clk;
input wr_clk;
input [7:0]din;
input rst;
input rd_en;
wire [7:0]din;
wire [7:0]dout;
wire empty;
wire full;
wire \gntv_or_sync_fifo.gcx.clkx_n_6 ;
wire \gntv_or_sync_fifo.gl0.rd_n_10 ;
wire \gntv_or_sync_fifo.gl0.rd_n_11 ;
wire \gntv_or_sync_fifo.gl0.rd_n_12 ;
wire \gntv_or_sync_fifo.gl0.rd_n_13 ;
wire \gntv_or_sync_fifo.gl0.rd_n_14 ;
wire \gntv_or_sync_fifo.gl0.rd_n_20 ;
wire \gntv_or_sync_fifo.gl0.wr_n_1 ;
wire [0:0]gray2bin;
wire [5:0]p_0_out_0;
wire [5:0]p_12_out;
wire [5:0]p_22_out;
wire [5:0]p_23_out;
wire p_2_out;
wire [5:0]p_5_out;
wire rd_clk;
wire rd_en;
wire [5:0]rd_pntr_plus1;
wire [2:0]rd_rst_i;
wire rst;
wire rst_full_ff_i;
wire tmp_ram_rd_en;
wire wr_clk;
wire wr_en;
wire wr_rst_busy;
wire [1:0]wr_rst_i;
fifo_EEPROM_clk_x_pntrs \gntv_or_sync_fifo.gcx.clkx
(.AR(wr_rst_i[0]),
.D(gray2bin),
.Q(rd_pntr_plus1),
.\gc0.count_d1_reg[0] (\gntv_or_sync_fifo.gl0.rd_n_20 ),
.\gc0.count_d1_reg[5] ({p_0_out_0[5],\gntv_or_sync_fifo.gl0.rd_n_10 ,\gntv_or_sync_fifo.gl0.rd_n_11 ,\gntv_or_sync_fifo.gl0.rd_n_12 ,\gntv_or_sync_fifo.gl0.rd_n_13 ,\gntv_or_sync_fifo.gl0.rd_n_14 }),
.\gic0.gc0.count_d2_reg[5] (p_12_out),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (rd_rst_i[1]),
.out(p_5_out),
.ram_empty_fb_i_reg(\gntv_or_sync_fifo.gcx.clkx_n_6 ),
.ram_empty_fb_i_reg_0(p_22_out),
.ram_empty_fb_i_reg_1(p_2_out),
.ram_full_i_reg(p_23_out),
.rd_clk(rd_clk),
.rd_en(rd_en),
.wr_clk(wr_clk));
LUT6 #(
.INIT(64'h6996966996696996))
\gntv_or_sync_fifo.gcx.clkx/
(.I0(p_5_out[2]),
.I1(p_5_out[0]),
.I2(p_5_out[1]),
.I3(p_5_out[5]),
.I4(p_5_out[3]),
.I5(p_5_out[4]),
.O(gray2bin));
fifo_EEPROM_rd_logic \gntv_or_sync_fifo.gl0.rd
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ({p_0_out_0[5],\gntv_or_sync_fifo.gl0.rd_n_10 ,\gntv_or_sync_fifo.gl0.rd_n_11 ,\gntv_or_sync_fifo.gl0.rd_n_12 ,\gntv_or_sync_fifo.gl0.rd_n_13 ,\gntv_or_sync_fifo.gl0.rd_n_14 }),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 (p_0_out_0[4:0]),
.Q(rd_pntr_plus1),
.empty(empty),
.\gc0.count_reg[0] (\gntv_or_sync_fifo.gcx.clkx_n_6 ),
.\gnxpm_cdc.wr_pntr_bin_reg[5] (p_22_out),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ({rd_rst_i[2],rd_rst_i[0]}),
.out(p_2_out),
.ram_empty_fb_i_reg(\gntv_or_sync_fifo.gl0.rd_n_20 ),
.rd_clk(rd_clk),
.rd_en(rd_en),
.tmp_ram_rd_en(tmp_ram_rd_en));
fifo_EEPROM_wr_logic \gntv_or_sync_fifo.gl0.wr
(.AR(wr_rst_i[1]),
.Q(p_12_out),
.WEBWE(\gntv_or_sync_fifo.gl0.wr_n_1 ),
.full(full),
.\gnxpm_cdc.rd_pntr_bin_reg[5] (p_23_out),
.out(rst_full_ff_i),
.wr_clk(wr_clk),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
fifo_EEPROM_memory \gntv_or_sync_fifo.mem
(.ADDRARDADDR(p_0_out_0),
.Q(p_12_out),
.WEBWE(\gntv_or_sync_fifo.gl0.wr_n_1 ),
.din(din),
.dout(dout),
.out(rd_rst_i[0]),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
fifo_EEPROM_reset_blk_ramfifo rstblk
(.\gc0.count_reg[1] (rd_rst_i),
.\grstd1.grst_full.grst_f.rst_d3_reg_0 (rst_full_ff_i),
.out(wr_rst_i),
.rd_clk(rd_clk),
.rst(rst),
.wr_clk(wr_clk),
.wr_rst_busy(wr_rst_busy));
endmodule
(* ORIG_REF_NAME = "fifo_generator_top" *)
module fifo_EEPROM_fifo_generator_top
(wr_rst_busy,
dout,
empty,
full,
wr_en,
rd_clk,
wr_clk,
din,
rst,
rd_en);
output wr_rst_busy;
output [7:0]dout;
output empty;
output full;
input wr_en;
input rd_clk;
input wr_clk;
input [7:0]din;
input rst;
input rd_en;
wire [7:0]din;
wire [7:0]dout;
wire empty;
wire full;
wire rd_clk;
wire rd_en;
wire rst;
wire wr_clk;
wire wr_en;
wire wr_rst_busy;
fifo_EEPROM_fifo_generator_ramfifo \grf.rf
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
endmodule
(* C_ADD_NGC_CONSTRAINT = "0" *) (* C_APPLICATION_TYPE_AXIS = "0" *) (* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *) (* C_APPLICATION_TYPE_WACH = "0" *) (* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *) (* C_AXIS_TDATA_WIDTH = "8" *) (* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *) (* C_AXIS_TKEEP_WIDTH = "1" *) (* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *) (* C_AXIS_TYPE = "0" *) (* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_ID_WIDTH = "1" *) (* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *) (* C_COMMON_CLOCK = "0" *) (* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "6" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "8" *)
(* C_DIN_WIDTH_AXIS = "1" *) (* C_DIN_WIDTH_RACH = "32" *) (* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "1" *) (* C_DIN_WIDTH_WDCH = "64" *) (* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "8" *) (* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *) (* C_EN_SAFETY_CKT = "0" *) (* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *) (* C_ERROR_INJECTION_TYPE_RACH = "0" *) (* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *) (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "artix7" *) (* C_FULL_FLAGS_RST_VAL = "1" *) (* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *) (* C_HAS_AXIS_TDATA = "1" *) (* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *) (* C_HAS_AXIS_TKEEP = "0" *) (* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *) (* C_HAS_AXIS_TSTRB = "0" *) (* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *) (* C_HAS_AXI_AWUSER = "0" *) (* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *) (* C_HAS_AXI_RD_CHANNEL = "1" *) (* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *) (* C_HAS_AXI_WUSER = "0" *) (* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *) (* C_HAS_DATA_COUNTS_AXIS = "0" *) (* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *) (* C_HAS_DATA_COUNTS_WACH = "0" *) (* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *) (* C_HAS_INT_CLK = "0" *) (* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *) (* C_HAS_OVERFLOW = "0" *) (* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *) (* C_HAS_PROG_FLAGS_RDCH = "0" *) (* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *) (* C_HAS_PROG_FLAGS_WRCH = "0" *) (* C_HAS_RD_DATA_COUNT = "0" *)
(* C_HAS_RD_RST = "0" *) (* C_HAS_RST = "1" *) (* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "0" *) (* C_HAS_UNDERFLOW = "0" *) (* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *) (* C_HAS_WR_DATA_COUNT = "0" *) (* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "2" *) (* C_IMPLEMENTATION_TYPE_AXIS = "1" *) (* C_IMPLEMENTATION_TYPE_RACH = "1" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *) (* C_IMPLEMENTATION_TYPE_WACH = "1" *) (* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "1" *) (* C_INIT_WR_PNTR_VAL = "0" *) (* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "1" *) (* C_MIF_FILE_NAME = "BlankString" *) (* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *) (* C_OVERFLOW_LOW = "0" *) (* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "1" *) (* C_PRELOAD_REGS = "0" *) (* C_PRIM_FIFO_TYPE = "512x36" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *) (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) (* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *) (* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *) (* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *) (* C_PROG_EMPTY_TYPE_RACH = "0" *) (* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *) (* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "61" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) (* C_PROG_FULL_THRESH_NEGATE_VAL = "60" *) (* C_PROG_FULL_TYPE = "0" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *) (* C_PROG_FULL_TYPE_RACH = "0" *) (* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *) (* C_PROG_FULL_TYPE_WDCH = "0" *) (* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *) (* C_RDCH_TYPE = "0" *) (* C_RD_DATA_COUNT_WIDTH = "6" *)
(* C_RD_DEPTH = "64" *) (* C_RD_FREQ = "1" *) (* C_RD_PNTR_WIDTH = "6" *)
(* C_REG_SLICE_MODE_AXIS = "0" *) (* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *) (* C_REG_SLICE_MODE_WDCH = "0" *) (* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SELECT_XPM = "0" *) (* C_SYNCHRONIZER_STAGE = "2" *) (* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *) (* C_USE_COMMON_UNDERFLOW = "0" *) (* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *) (* C_USE_ECC = "0" *) (* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *) (* C_USE_ECC_RDCH = "0" *) (* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *) (* C_USE_ECC_WRCH = "0" *) (* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *) (* C_USE_FWFT_DATA_COUNT = "0" *) (* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *) (* C_WACH_TYPE = "0" *) (* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *) (* C_WR_ACK_LOW = "0" *) (* C_WR_DATA_COUNT_WIDTH = "6" *)
(* C_WR_DEPTH = "64" *) (* C_WR_DEPTH_AXIS = "1024" *) (* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "1024" *) (* C_WR_DEPTH_WACH = "16" *) (* C_WR_DEPTH_WDCH = "1024" *)
(* C_WR_DEPTH_WRCH = "16" *) (* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "6" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *) (* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "10" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *) (* C_WR_PNTR_WIDTH_WDCH = "10" *) (* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *) (* ORIG_REF_NAME = "fifo_generator_v13_1_4" *)
module fifo_EEPROM_fifo_generator_v13_1_4
(backup,
backup_marker,
clk,
rst,
srst,
wr_clk,
wr_rst,
rd_clk,
rd_rst,
din,
wr_en,
rd_en,
prog_empty_thresh,
prog_empty_thresh_assert,
prog_empty_thresh_negate,
prog_full_thresh,
prog_full_thresh_assert,
prog_full_thresh_negate,
int_clk,
injectdbiterr,
injectsbiterr,
sleep,
dout,
full,
almost_full,
wr_ack,
overflow,
empty,
almost_empty,
valid,
underflow,
data_count,
rd_data_count,
wr_data_count,
prog_full,
prog_empty,
sbiterr,
dbiterr,
wr_rst_busy,
rd_rst_busy,
m_aclk,
s_aclk,
s_aresetn,
m_aclk_en,
s_aclk_en,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awregion,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awregion,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arregion,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arregion,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tstrb,
s_axis_tkeep,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tstrb,
m_axis_tkeep,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser,
axi_aw_injectsbiterr,
axi_aw_injectdbiterr,
axi_aw_prog_full_thresh,
axi_aw_prog_empty_thresh,
axi_aw_data_count,
axi_aw_wr_data_count,
axi_aw_rd_data_count,
axi_aw_sbiterr,
axi_aw_dbiterr,
axi_aw_overflow,
axi_aw_underflow,
axi_aw_prog_full,
axi_aw_prog_empty,
axi_w_injectsbiterr,
axi_w_injectdbiterr,
axi_w_prog_full_thresh,
axi_w_prog_empty_thresh,
axi_w_data_count,
axi_w_wr_data_count,
axi_w_rd_data_count,
axi_w_sbiterr,
axi_w_dbiterr,
axi_w_overflow,
axi_w_underflow,
axi_w_prog_full,
axi_w_prog_empty,
axi_b_injectsbiterr,
axi_b_injectdbiterr,
axi_b_prog_full_thresh,
axi_b_prog_empty_thresh,
axi_b_data_count,
axi_b_wr_data_count,
axi_b_rd_data_count,
axi_b_sbiterr,
axi_b_dbiterr,
axi_b_overflow,
axi_b_underflow,
axi_b_prog_full,
axi_b_prog_empty,
axi_ar_injectsbiterr,
axi_ar_injectdbiterr,
axi_ar_prog_full_thresh,
axi_ar_prog_empty_thresh,
axi_ar_data_count,
axi_ar_wr_data_count,
axi_ar_rd_data_count,
axi_ar_sbiterr,
axi_ar_dbiterr,
axi_ar_overflow,
axi_ar_underflow,
axi_ar_prog_full,
axi_ar_prog_empty,
axi_r_injectsbiterr,
axi_r_injectdbiterr,
axi_r_prog_full_thresh,
axi_r_prog_empty_thresh,
axi_r_data_count,
axi_r_wr_data_count,
axi_r_rd_data_count,
axi_r_sbiterr,
axi_r_dbiterr,
axi_r_overflow,
axi_r_underflow,
axi_r_prog_full,
axi_r_prog_empty,
axis_injectsbiterr,
axis_injectdbiterr,
axis_prog_full_thresh,
axis_prog_empty_thresh,
axis_data_count,
axis_wr_data_count,
axis_rd_data_count,
axis_sbiterr,
axis_dbiterr,
axis_overflow,
axis_underflow,
axis_prog_full,
axis_prog_empty);
input backup;
input backup_marker;
input clk;
input rst;
input srst;
input wr_clk;
input wr_rst;
input rd_clk;
input rd_rst;
input [7:0]din;
input wr_en;
input rd_en;
input [5:0]prog_empty_thresh;
input [5:0]prog_empty_thresh_assert;
input [5:0]prog_empty_thresh_negate;
input [5:0]prog_full_thresh;
input [5:0]prog_full_thresh_assert;
input [5:0]prog_full_thresh_negate;
input int_clk;
input injectdbiterr;
input injectsbiterr;
input sleep;
output [7:0]dout;
output full;
output almost_full;
output wr_ack;
output overflow;
output empty;
output almost_empty;
output valid;
output underflow;
output [5:0]data_count;
output [5:0]rd_data_count;
output [5:0]wr_data_count;
output prog_full;
output prog_empty;
output sbiterr;
output dbiterr;
output wr_rst_busy;
output rd_rst_busy;
input m_aclk;
input s_aclk;
input s_aresetn;
input m_aclk_en;
input s_aclk_en;
input [0:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [3:0]s_axi_awregion;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [0:0]s_axi_wid;
input [63:0]s_axi_wdata;
input [7:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
output [0:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awqos;
output [3:0]m_axi_awregion;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [0:0]m_axi_wid;
output [63:0]m_axi_wdata;
output [7:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [0:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
input [0:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [3:0]s_axi_arregion;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [0:0]s_axi_rid;
output [63:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [0:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arqos;
output [3:0]m_axi_arregion;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [0:0]m_axi_rid;
input [63:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
input s_axis_tvalid;
output s_axis_tready;
input [7:0]s_axis_tdata;
input [0:0]s_axis_tstrb;
input [0:0]s_axis_tkeep;
input s_axis_tlast;
input [0:0]s_axis_tid;
input [0:0]s_axis_tdest;
input [3:0]s_axis_tuser;
output m_axis_tvalid;
input m_axis_tready;
output [7:0]m_axis_tdata;
output [0:0]m_axis_tstrb;
output [0:0]m_axis_tkeep;
output m_axis_tlast;
output [0:0]m_axis_tid;
output [0:0]m_axis_tdest;
output [3:0]m_axis_tuser;
input axi_aw_injectsbiterr;
input axi_aw_injectdbiterr;
input [3:0]axi_aw_prog_full_thresh;
input [3:0]axi_aw_prog_empty_thresh;
output [4:0]axi_aw_data_count;
output [4:0]axi_aw_wr_data_count;
output [4:0]axi_aw_rd_data_count;
output axi_aw_sbiterr;
output axi_aw_dbiterr;
output axi_aw_overflow;
output axi_aw_underflow;
output axi_aw_prog_full;
output axi_aw_prog_empty;
input axi_w_injectsbiterr;
input axi_w_injectdbiterr;
input [9:0]axi_w_prog_full_thresh;
input [9:0]axi_w_prog_empty_thresh;
output [10:0]axi_w_data_count;
output [10:0]axi_w_wr_data_count;
output [10:0]axi_w_rd_data_count;
output axi_w_sbiterr;
output axi_w_dbiterr;
output axi_w_overflow;
output axi_w_underflow;
output axi_w_prog_full;
output axi_w_prog_empty;
input axi_b_injectsbiterr;
input axi_b_injectdbiterr;
input [3:0]axi_b_prog_full_thresh;
input [3:0]axi_b_prog_empty_thresh;
output [4:0]axi_b_data_count;
output [4:0]axi_b_wr_data_count;
output [4:0]axi_b_rd_data_count;
output axi_b_sbiterr;
output axi_b_dbiterr;
output axi_b_overflow;
output axi_b_underflow;
output axi_b_prog_full;
output axi_b_prog_empty;
input axi_ar_injectsbiterr;
input axi_ar_injectdbiterr;
input [3:0]axi_ar_prog_full_thresh;
input [3:0]axi_ar_prog_empty_thresh;
output [4:0]axi_ar_data_count;
output [4:0]axi_ar_wr_data_count;
output [4:0]axi_ar_rd_data_count;
output axi_ar_sbiterr;
output axi_ar_dbiterr;
output axi_ar_overflow;
output axi_ar_underflow;
output axi_ar_prog_full;
output axi_ar_prog_empty;
input axi_r_injectsbiterr;
input axi_r_injectdbiterr;
input [9:0]axi_r_prog_full_thresh;
input [9:0]axi_r_prog_empty_thresh;
output [10:0]axi_r_data_count;
output [10:0]axi_r_wr_data_count;
output [10:0]axi_r_rd_data_count;
output axi_r_sbiterr;
output axi_r_dbiterr;
output axi_r_overflow;
output axi_r_underflow;
output axi_r_prog_full;
output axi_r_prog_empty;
input axis_injectsbiterr;
input axis_injectdbiterr;
input [9:0]axis_prog_full_thresh;
input [9:0]axis_prog_empty_thresh;
output [10:0]axis_data_count;
output [10:0]axis_wr_data_count;
output [10:0]axis_rd_data_count;
output axis_sbiterr;
output axis_dbiterr;
output axis_overflow;
output axis_underflow;
output axis_prog_full;
output axis_prog_empty;
wire \<const0> ;
wire \<const1> ;
wire [7:0]din;
wire [7:0]dout;
wire empty;
wire full;
wire rd_clk;
wire rd_en;
wire rst;
wire wr_clk;
wire wr_en;
wire wr_rst_busy;
assign almost_empty = \<const0> ;
assign almost_full = \<const0> ;
assign axi_ar_data_count[4] = \<const0> ;
assign axi_ar_data_count[3] = \<const0> ;
assign axi_ar_data_count[2] = \<const0> ;
assign axi_ar_data_count[1] = \<const0> ;
assign axi_ar_data_count[0] = \<const0> ;
assign axi_ar_dbiterr = \<const0> ;
assign axi_ar_overflow = \<const0> ;
assign axi_ar_prog_empty = \<const1> ;
assign axi_ar_prog_full = \<const0> ;
assign axi_ar_rd_data_count[4] = \<const0> ;
assign axi_ar_rd_data_count[3] = \<const0> ;
assign axi_ar_rd_data_count[2] = \<const0> ;
assign axi_ar_rd_data_count[1] = \<const0> ;
assign axi_ar_rd_data_count[0] = \<const0> ;
assign axi_ar_sbiterr = \<const0> ;
assign axi_ar_underflow = \<const0> ;
assign axi_ar_wr_data_count[4] = \<const0> ;
assign axi_ar_wr_data_count[3] = \<const0> ;
assign axi_ar_wr_data_count[2] = \<const0> ;
assign axi_ar_wr_data_count[1] = \<const0> ;
assign axi_ar_wr_data_count[0] = \<const0> ;
assign axi_aw_data_count[4] = \<const0> ;
assign axi_aw_data_count[3] = \<const0> ;
assign axi_aw_data_count[2] = \<const0> ;
assign axi_aw_data_count[1] = \<const0> ;
assign axi_aw_data_count[0] = \<const0> ;
assign axi_aw_dbiterr = \<const0> ;
assign axi_aw_overflow = \<const0> ;
assign axi_aw_prog_empty = \<const1> ;
assign axi_aw_prog_full = \<const0> ;
assign axi_aw_rd_data_count[4] = \<const0> ;
assign axi_aw_rd_data_count[3] = \<const0> ;
assign axi_aw_rd_data_count[2] = \<const0> ;
assign axi_aw_rd_data_count[1] = \<const0> ;
assign axi_aw_rd_data_count[0] = \<const0> ;
assign axi_aw_sbiterr = \<const0> ;
assign axi_aw_underflow = \<const0> ;
assign axi_aw_wr_data_count[4] = \<const0> ;
assign axi_aw_wr_data_count[3] = \<const0> ;
assign axi_aw_wr_data_count[2] = \<const0> ;
assign axi_aw_wr_data_count[1] = \<const0> ;
assign axi_aw_wr_data_count[0] = \<const0> ;
assign axi_b_data_count[4] = \<const0> ;
assign axi_b_data_count[3] = \<const0> ;
assign axi_b_data_count[2] = \<const0> ;
assign axi_b_data_count[1] = \<const0> ;
assign axi_b_data_count[0] = \<const0> ;
assign axi_b_dbiterr = \<const0> ;
assign axi_b_overflow = \<const0> ;
assign axi_b_prog_empty = \<const1> ;
assign axi_b_prog_full = \<const0> ;
assign axi_b_rd_data_count[4] = \<const0> ;
assign axi_b_rd_data_count[3] = \<const0> ;
assign axi_b_rd_data_count[2] = \<const0> ;
assign axi_b_rd_data_count[1] = \<const0> ;
assign axi_b_rd_data_count[0] = \<const0> ;
assign axi_b_sbiterr = \<const0> ;
assign axi_b_underflow = \<const0> ;
assign axi_b_wr_data_count[4] = \<const0> ;
assign axi_b_wr_data_count[3] = \<const0> ;
assign axi_b_wr_data_count[2] = \<const0> ;
assign axi_b_wr_data_count[1] = \<const0> ;
assign axi_b_wr_data_count[0] = \<const0> ;
assign axi_r_data_count[10] = \<const0> ;
assign axi_r_data_count[9] = \<const0> ;
assign axi_r_data_count[8] = \<const0> ;
assign axi_r_data_count[7] = \<const0> ;
assign axi_r_data_count[6] = \<const0> ;
assign axi_r_data_count[5] = \<const0> ;
assign axi_r_data_count[4] = \<const0> ;
assign axi_r_data_count[3] = \<const0> ;
assign axi_r_data_count[2] = \<const0> ;
assign axi_r_data_count[1] = \<const0> ;
assign axi_r_data_count[0] = \<const0> ;
assign axi_r_dbiterr = \<const0> ;
assign axi_r_overflow = \<const0> ;
assign axi_r_prog_empty = \<const1> ;
assign axi_r_prog_full = \<const0> ;
assign axi_r_rd_data_count[10] = \<const0> ;
assign axi_r_rd_data_count[9] = \<const0> ;
assign axi_r_rd_data_count[8] = \<const0> ;
assign axi_r_rd_data_count[7] = \<const0> ;
assign axi_r_rd_data_count[6] = \<const0> ;
assign axi_r_rd_data_count[5] = \<const0> ;
assign axi_r_rd_data_count[4] = \<const0> ;
assign axi_r_rd_data_count[3] = \<const0> ;
assign axi_r_rd_data_count[2] = \<const0> ;
assign axi_r_rd_data_count[1] = \<const0> ;
assign axi_r_rd_data_count[0] = \<const0> ;
assign axi_r_sbiterr = \<const0> ;
assign axi_r_underflow = \<const0> ;
assign axi_r_wr_data_count[10] = \<const0> ;
assign axi_r_wr_data_count[9] = \<const0> ;
assign axi_r_wr_data_count[8] = \<const0> ;
assign axi_r_wr_data_count[7] = \<const0> ;
assign axi_r_wr_data_count[6] = \<const0> ;
assign axi_r_wr_data_count[5] = \<const0> ;
assign axi_r_wr_data_count[4] = \<const0> ;
assign axi_r_wr_data_count[3] = \<const0> ;
assign axi_r_wr_data_count[2] = \<const0> ;
assign axi_r_wr_data_count[1] = \<const0> ;
assign axi_r_wr_data_count[0] = \<const0> ;
assign axi_w_data_count[10] = \<const0> ;
assign axi_w_data_count[9] = \<const0> ;
assign axi_w_data_count[8] = \<const0> ;
assign axi_w_data_count[7] = \<const0> ;
assign axi_w_data_count[6] = \<const0> ;
assign axi_w_data_count[5] = \<const0> ;
assign axi_w_data_count[4] = \<const0> ;
assign axi_w_data_count[3] = \<const0> ;
assign axi_w_data_count[2] = \<const0> ;
assign axi_w_data_count[1] = \<const0> ;
assign axi_w_data_count[0] = \<const0> ;
assign axi_w_dbiterr = \<const0> ;
assign axi_w_overflow = \<const0> ;
assign axi_w_prog_empty = \<const1> ;
assign axi_w_prog_full = \<const0> ;
assign axi_w_rd_data_count[10] = \<const0> ;
assign axi_w_rd_data_count[9] = \<const0> ;
assign axi_w_rd_data_count[8] = \<const0> ;
assign axi_w_rd_data_count[7] = \<const0> ;
assign axi_w_rd_data_count[6] = \<const0> ;
assign axi_w_rd_data_count[5] = \<const0> ;
assign axi_w_rd_data_count[4] = \<const0> ;
assign axi_w_rd_data_count[3] = \<const0> ;
assign axi_w_rd_data_count[2] = \<const0> ;
assign axi_w_rd_data_count[1] = \<const0> ;
assign axi_w_rd_data_count[0] = \<const0> ;
assign axi_w_sbiterr = \<const0> ;
assign axi_w_underflow = \<const0> ;
assign axi_w_wr_data_count[10] = \<const0> ;
assign axi_w_wr_data_count[9] = \<const0> ;
assign axi_w_wr_data_count[8] = \<const0> ;
assign axi_w_wr_data_count[7] = \<const0> ;
assign axi_w_wr_data_count[6] = \<const0> ;
assign axi_w_wr_data_count[5] = \<const0> ;
assign axi_w_wr_data_count[4] = \<const0> ;
assign axi_w_wr_data_count[3] = \<const0> ;
assign axi_w_wr_data_count[2] = \<const0> ;
assign axi_w_wr_data_count[1] = \<const0> ;
assign axi_w_wr_data_count[0] = \<const0> ;
assign axis_data_count[10] = \<const0> ;
assign axis_data_count[9] = \<const0> ;
assign axis_data_count[8] = \<const0> ;
assign axis_data_count[7] = \<const0> ;
assign axis_data_count[6] = \<const0> ;
assign axis_data_count[5] = \<const0> ;
assign axis_data_count[4] = \<const0> ;
assign axis_data_count[3] = \<const0> ;
assign axis_data_count[2] = \<const0> ;
assign axis_data_count[1] = \<const0> ;
assign axis_data_count[0] = \<const0> ;
assign axis_dbiterr = \<const0> ;
assign axis_overflow = \<const0> ;
assign axis_prog_empty = \<const1> ;
assign axis_prog_full = \<const0> ;
assign axis_rd_data_count[10] = \<const0> ;
assign axis_rd_data_count[9] = \<const0> ;
assign axis_rd_data_count[8] = \<const0> ;
assign axis_rd_data_count[7] = \<const0> ;
assign axis_rd_data_count[6] = \<const0> ;
assign axis_rd_data_count[5] = \<const0> ;
assign axis_rd_data_count[4] = \<const0> ;
assign axis_rd_data_count[3] = \<const0> ;
assign axis_rd_data_count[2] = \<const0> ;
assign axis_rd_data_count[1] = \<const0> ;
assign axis_rd_data_count[0] = \<const0> ;
assign axis_sbiterr = \<const0> ;
assign axis_underflow = \<const0> ;
assign axis_wr_data_count[10] = \<const0> ;
assign axis_wr_data_count[9] = \<const0> ;
assign axis_wr_data_count[8] = \<const0> ;
assign axis_wr_data_count[7] = \<const0> ;
assign axis_wr_data_count[6] = \<const0> ;
assign axis_wr_data_count[5] = \<const0> ;
assign axis_wr_data_count[4] = \<const0> ;
assign axis_wr_data_count[3] = \<const0> ;
assign axis_wr_data_count[2] = \<const0> ;
assign axis_wr_data_count[1] = \<const0> ;
assign axis_wr_data_count[0] = \<const0> ;
assign data_count[5] = \<const0> ;
assign data_count[4] = \<const0> ;
assign data_count[3] = \<const0> ;
assign data_count[2] = \<const0> ;
assign data_count[1] = \<const0> ;
assign data_count[0] = \<const0> ;
assign dbiterr = \<const0> ;
assign m_axi_araddr[31] = \<const0> ;
assign m_axi_araddr[30] = \<const0> ;
assign m_axi_araddr[29] = \<const0> ;
assign m_axi_araddr[28] = \<const0> ;
assign m_axi_araddr[27] = \<const0> ;
assign m_axi_araddr[26] = \<const0> ;
assign m_axi_araddr[25] = \<const0> ;
assign m_axi_araddr[24] = \<const0> ;
assign m_axi_araddr[23] = \<const0> ;
assign m_axi_araddr[22] = \<const0> ;
assign m_axi_araddr[21] = \<const0> ;
assign m_axi_araddr[20] = \<const0> ;
assign m_axi_araddr[19] = \<const0> ;
assign m_axi_araddr[18] = \<const0> ;
assign m_axi_araddr[17] = \<const0> ;
assign m_axi_araddr[16] = \<const0> ;
assign m_axi_araddr[15] = \<const0> ;
assign m_axi_araddr[14] = \<const0> ;
assign m_axi_araddr[13] = \<const0> ;
assign m_axi_araddr[12] = \<const0> ;
assign m_axi_araddr[11] = \<const0> ;
assign m_axi_araddr[10] = \<const0> ;
assign m_axi_araddr[9] = \<const0> ;
assign m_axi_araddr[8] = \<const0> ;
assign m_axi_araddr[7] = \<const0> ;
assign m_axi_araddr[6] = \<const0> ;
assign m_axi_araddr[5] = \<const0> ;
assign m_axi_araddr[4] = \<const0> ;
assign m_axi_araddr[3] = \<const0> ;
assign m_axi_araddr[2] = \<const0> ;
assign m_axi_araddr[1] = \<const0> ;
assign m_axi_araddr[0] = \<const0> ;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const0> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arprot[2] = \<const0> ;
assign m_axi_arprot[1] = \<const0> ;
assign m_axi_arprot[0] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const0> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_arvalid = \<const0> ;
assign m_axi_awaddr[31] = \<const0> ;
assign m_axi_awaddr[30] = \<const0> ;
assign m_axi_awaddr[29] = \<const0> ;
assign m_axi_awaddr[28] = \<const0> ;
assign m_axi_awaddr[27] = \<const0> ;
assign m_axi_awaddr[26] = \<const0> ;
assign m_axi_awaddr[25] = \<const0> ;
assign m_axi_awaddr[24] = \<const0> ;
assign m_axi_awaddr[23] = \<const0> ;
assign m_axi_awaddr[22] = \<const0> ;
assign m_axi_awaddr[21] = \<const0> ;
assign m_axi_awaddr[20] = \<const0> ;
assign m_axi_awaddr[19] = \<const0> ;
assign m_axi_awaddr[18] = \<const0> ;
assign m_axi_awaddr[17] = \<const0> ;
assign m_axi_awaddr[16] = \<const0> ;
assign m_axi_awaddr[15] = \<const0> ;
assign m_axi_awaddr[14] = \<const0> ;
assign m_axi_awaddr[13] = \<const0> ;
assign m_axi_awaddr[12] = \<const0> ;
assign m_axi_awaddr[11] = \<const0> ;
assign m_axi_awaddr[10] = \<const0> ;
assign m_axi_awaddr[9] = \<const0> ;
assign m_axi_awaddr[8] = \<const0> ;
assign m_axi_awaddr[7] = \<const0> ;
assign m_axi_awaddr[6] = \<const0> ;
assign m_axi_awaddr[5] = \<const0> ;
assign m_axi_awaddr[4] = \<const0> ;
assign m_axi_awaddr[3] = \<const0> ;
assign m_axi_awaddr[2] = \<const0> ;
assign m_axi_awaddr[1] = \<const0> ;
assign m_axi_awaddr[0] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const0> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awprot[2] = \<const0> ;
assign m_axi_awprot[1] = \<const0> ;
assign m_axi_awprot[0] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const0> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_awvalid = \<const0> ;
assign m_axi_bready = \<const0> ;
assign m_axi_rready = \<const0> ;
assign m_axi_wdata[63] = \<const0> ;
assign m_axi_wdata[62] = \<const0> ;
assign m_axi_wdata[61] = \<const0> ;
assign m_axi_wdata[60] = \<const0> ;
assign m_axi_wdata[59] = \<const0> ;
assign m_axi_wdata[58] = \<const0> ;
assign m_axi_wdata[57] = \<const0> ;
assign m_axi_wdata[56] = \<const0> ;
assign m_axi_wdata[55] = \<const0> ;
assign m_axi_wdata[54] = \<const0> ;
assign m_axi_wdata[53] = \<const0> ;
assign m_axi_wdata[52] = \<const0> ;
assign m_axi_wdata[51] = \<const0> ;
assign m_axi_wdata[50] = \<const0> ;
assign m_axi_wdata[49] = \<const0> ;
assign m_axi_wdata[48] = \<const0> ;
assign m_axi_wdata[47] = \<const0> ;
assign m_axi_wdata[46] = \<const0> ;
assign m_axi_wdata[45] = \<const0> ;
assign m_axi_wdata[44] = \<const0> ;
assign m_axi_wdata[43] = \<const0> ;
assign m_axi_wdata[42] = \<const0> ;
assign m_axi_wdata[41] = \<const0> ;
assign m_axi_wdata[40] = \<const0> ;
assign m_axi_wdata[39] = \<const0> ;
assign m_axi_wdata[38] = \<const0> ;
assign m_axi_wdata[37] = \<const0> ;
assign m_axi_wdata[36] = \<const0> ;
assign m_axi_wdata[35] = \<const0> ;
assign m_axi_wdata[34] = \<const0> ;
assign m_axi_wdata[33] = \<const0> ;
assign m_axi_wdata[32] = \<const0> ;
assign m_axi_wdata[31] = \<const0> ;
assign m_axi_wdata[30] = \<const0> ;
assign m_axi_wdata[29] = \<const0> ;
assign m_axi_wdata[28] = \<const0> ;
assign m_axi_wdata[27] = \<const0> ;
assign m_axi_wdata[26] = \<const0> ;
assign m_axi_wdata[25] = \<const0> ;
assign m_axi_wdata[24] = \<const0> ;
assign m_axi_wdata[23] = \<const0> ;
assign m_axi_wdata[22] = \<const0> ;
assign m_axi_wdata[21] = \<const0> ;
assign m_axi_wdata[20] = \<const0> ;
assign m_axi_wdata[19] = \<const0> ;
assign m_axi_wdata[18] = \<const0> ;
assign m_axi_wdata[17] = \<const0> ;
assign m_axi_wdata[16] = \<const0> ;
assign m_axi_wdata[15] = \<const0> ;
assign m_axi_wdata[14] = \<const0> ;
assign m_axi_wdata[13] = \<const0> ;
assign m_axi_wdata[12] = \<const0> ;
assign m_axi_wdata[11] = \<const0> ;
assign m_axi_wdata[10] = \<const0> ;
assign m_axi_wdata[9] = \<const0> ;
assign m_axi_wdata[8] = \<const0> ;
assign m_axi_wdata[7] = \<const0> ;
assign m_axi_wdata[6] = \<const0> ;
assign m_axi_wdata[5] = \<const0> ;
assign m_axi_wdata[4] = \<const0> ;
assign m_axi_wdata[3] = \<const0> ;
assign m_axi_wdata[2] = \<const0> ;
assign m_axi_wdata[1] = \<const0> ;
assign m_axi_wdata[0] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast = \<const0> ;
assign m_axi_wstrb[7] = \<const0> ;
assign m_axi_wstrb[6] = \<const0> ;
assign m_axi_wstrb[5] = \<const0> ;
assign m_axi_wstrb[4] = \<const0> ;
assign m_axi_wstrb[3] = \<const0> ;
assign m_axi_wstrb[2] = \<const0> ;
assign m_axi_wstrb[1] = \<const0> ;
assign m_axi_wstrb[0] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign m_axi_wvalid = \<const0> ;
assign m_axis_tdata[7] = \<const0> ;
assign m_axis_tdata[6] = \<const0> ;
assign m_axis_tdata[5] = \<const0> ;
assign m_axis_tdata[4] = \<const0> ;
assign m_axis_tdata[3] = \<const0> ;
assign m_axis_tdata[2] = \<const0> ;
assign m_axis_tdata[1] = \<const0> ;
assign m_axis_tdata[0] = \<const0> ;
assign m_axis_tdest[0] = \<const0> ;
assign m_axis_tid[0] = \<const0> ;
assign m_axis_tkeep[0] = \<const0> ;
assign m_axis_tlast = \<const0> ;
assign m_axis_tstrb[0] = \<const0> ;
assign m_axis_tuser[3] = \<const0> ;
assign m_axis_tuser[2] = \<const0> ;
assign m_axis_tuser[1] = \<const0> ;
assign m_axis_tuser[0] = \<const0> ;
assign m_axis_tvalid = \<const0> ;
assign overflow = \<const0> ;
assign prog_empty = \<const0> ;
assign prog_full = \<const0> ;
assign rd_data_count[5] = \<const0> ;
assign rd_data_count[4] = \<const0> ;
assign rd_data_count[3] = \<const0> ;
assign rd_data_count[2] = \<const0> ;
assign rd_data_count[1] = \<const0> ;
assign rd_data_count[0] = \<const0> ;
assign rd_rst_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_rdata[63] = \<const0> ;
assign s_axi_rdata[62] = \<const0> ;
assign s_axi_rdata[61] = \<const0> ;
assign s_axi_rdata[60] = \<const0> ;
assign s_axi_rdata[59] = \<const0> ;
assign s_axi_rdata[58] = \<const0> ;
assign s_axi_rdata[57] = \<const0> ;
assign s_axi_rdata[56] = \<const0> ;
assign s_axi_rdata[55] = \<const0> ;
assign s_axi_rdata[54] = \<const0> ;
assign s_axi_rdata[53] = \<const0> ;
assign s_axi_rdata[52] = \<const0> ;
assign s_axi_rdata[51] = \<const0> ;
assign s_axi_rdata[50] = \<const0> ;
assign s_axi_rdata[49] = \<const0> ;
assign s_axi_rdata[48] = \<const0> ;
assign s_axi_rdata[47] = \<const0> ;
assign s_axi_rdata[46] = \<const0> ;
assign s_axi_rdata[45] = \<const0> ;
assign s_axi_rdata[44] = \<const0> ;
assign s_axi_rdata[43] = \<const0> ;
assign s_axi_rdata[42] = \<const0> ;
assign s_axi_rdata[41] = \<const0> ;
assign s_axi_rdata[40] = \<const0> ;
assign s_axi_rdata[39] = \<const0> ;
assign s_axi_rdata[38] = \<const0> ;
assign s_axi_rdata[37] = \<const0> ;
assign s_axi_rdata[36] = \<const0> ;
assign s_axi_rdata[35] = \<const0> ;
assign s_axi_rdata[34] = \<const0> ;
assign s_axi_rdata[33] = \<const0> ;
assign s_axi_rdata[32] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_wready = \<const0> ;
assign s_axis_tready = \<const0> ;
assign sbiterr = \<const0> ;
assign underflow = \<const0> ;
assign valid = \<const0> ;
assign wr_ack = \<const0> ;
assign wr_data_count[5] = \<const0> ;
assign wr_data_count[4] = \<const0> ;
assign wr_data_count[3] = \<const0> ;
assign wr_data_count[2] = \<const0> ;
assign wr_data_count[1] = \<const0> ;
assign wr_data_count[0] = \<const0> ;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
fifo_EEPROM_fifo_generator_v13_1_4_synth inst_fifo_gen
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
endmodule
(* ORIG_REF_NAME = "fifo_generator_v13_1_4_synth" *)
module fifo_EEPROM_fifo_generator_v13_1_4_synth
(wr_rst_busy,
dout,
empty,
full,
wr_en,
rd_clk,
wr_clk,
din,
rst,
rd_en);
output wr_rst_busy;
output [7:0]dout;
output empty;
output full;
input wr_en;
input rd_clk;
input wr_clk;
input [7:0]din;
input rst;
input rd_en;
wire [7:0]din;
wire [7:0]dout;
wire empty;
wire full;
wire rd_clk;
wire rd_en;
wire rst;
wire wr_clk;
wire wr_en;
wire wr_rst_busy;
fifo_EEPROM_fifo_generator_top \gconvfifo.rf
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
endmodule
(* ORIG_REF_NAME = "memory" *)
module fifo_EEPROM_memory
(dout,
rd_clk,
wr_clk,
tmp_ram_rd_en,
WEBWE,
out,
ADDRARDADDR,
Q,
din);
output [7:0]dout;
input rd_clk;
input wr_clk;
input tmp_ram_rd_en;
input [0:0]WEBWE;
input [0:0]out;
input [5:0]ADDRARDADDR;
input [5:0]Q;
input [7:0]din;
wire [5:0]ADDRARDADDR;
wire [5:0]Q;
wire [0:0]WEBWE;
wire [7:0]din;
wire [7:0]dout;
wire [0:0]out;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
fifo_EEPROM_blk_mem_gen_v8_3_6 \gbm.gbmg.gbmga.ngecc.bmg
(.ADDRARDADDR(ADDRARDADDR),
.Q(Q),
.WEBWE(WEBWE),
.din(din),
.dout(dout),
.out(out),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "rd_bin_cntr" *)
module fifo_EEPROM_rd_bin_cntr
(Q,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 ,
ram_empty_fb_i_reg,
\gnxpm_cdc.wr_pntr_bin_reg[5] ,
E,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] );
output [5:0]Q;
output [5:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
output [4:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 ;
output ram_empty_fb_i_reg;
input [5:0]\gnxpm_cdc.wr_pntr_bin_reg[5] ;
input [0:0]E;
input rd_clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
wire [5:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
wire [4:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 ;
wire [0:0]E;
wire [5:0]Q;
wire [5:0]\gnxpm_cdc.wr_pntr_bin_reg[5] ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
wire [5:0]plusOp;
wire ram_empty_fb_i_reg;
wire ram_empty_i_i_5_n_0;
wire ram_empty_i_i_6_n_0;
wire rd_clk;
LUT1 #(
.INIT(2'h1))
\gc0.count[0]_i_1
(.I0(Q[0]),
.O(plusOp[0]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h6))
\gc0.count[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'h78))
\gc0.count[2]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.O(plusOp[2]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h7F80))
\gc0.count[3]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.O(plusOp[3]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gc0.count[4]_i_1
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[4]),
.O(plusOp[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\gc0.count[5]_i_1
(.I0(Q[4]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(Q[3]),
.I5(Q[5]),
.O(plusOp[5]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[0]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(Q[0]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 [0]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[1]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(Q[1]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 [1]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[2]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(Q[2]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 [2]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[3]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(Q[3]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 [3]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[4]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(Q[4]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 [4]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[5]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(Q[5]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [5]));
FDPE #(
.INIT(1'b1))
\gc0.count_reg[0]
(.C(rd_clk),
.CE(E),
.D(plusOp[0]),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[1]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(plusOp[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[2]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(plusOp[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[3]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(plusOp[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[4]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(plusOp[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[5]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(plusOp[5]),
.Q(Q[5]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[0]_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 [0]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 [1]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [0]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[1]_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 [1]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 [2]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [1]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[2]_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 [2]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 [3]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [2]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[3]_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 [3]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 [4]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [3]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[4]_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 [4]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [5]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [4]));
LUT6 #(
.INIT(64'h8200008200000000))
ram_empty_i_i_3
(.I0(ram_empty_i_i_5_n_0),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 [0]),
.I2(\gnxpm_cdc.wr_pntr_bin_reg[5] [0]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 [1]),
.I4(\gnxpm_cdc.wr_pntr_bin_reg[5] [1]),
.I5(ram_empty_i_i_6_n_0),
.O(ram_empty_fb_i_reg));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h9009))
ram_empty_i_i_5
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 [2]),
.I1(\gnxpm_cdc.wr_pntr_bin_reg[5] [2]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 [3]),
.I3(\gnxpm_cdc.wr_pntr_bin_reg[5] [3]),
.O(ram_empty_i_i_5_n_0));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'h9009))
ram_empty_i_i_6
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 [4]),
.I1(\gnxpm_cdc.wr_pntr_bin_reg[5] [4]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [5]),
.I3(\gnxpm_cdc.wr_pntr_bin_reg[5] [5]),
.O(ram_empty_i_i_6_n_0));
endmodule
(* ORIG_REF_NAME = "rd_logic" *)
module fifo_EEPROM_rd_logic
(empty,
out,
Q,
tmp_ram_rd_en,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 ,
ram_empty_fb_i_reg,
\gc0.count_reg[0] ,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ,
rd_en,
\gnxpm_cdc.wr_pntr_bin_reg[5] );
output empty;
output out;
output [5:0]Q;
output tmp_ram_rd_en;
output [5:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
output [4:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 ;
output ram_empty_fb_i_reg;
input \gc0.count_reg[0] ;
input rd_clk;
input [1:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
input rd_en;
input [5:0]\gnxpm_cdc.wr_pntr_bin_reg[5] ;
wire [5:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
wire [4:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 ;
wire [5:0]Q;
wire empty;
wire \gc0.count_reg[0] ;
wire [5:0]\gnxpm_cdc.wr_pntr_bin_reg[5] ;
wire [1:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
wire out;
wire p_7_out;
wire ram_empty_fb_i_reg;
wire rd_clk;
wire rd_en;
wire tmp_ram_rd_en;
fifo_EEPROM_rd_status_flags_as \gras.rsts
(.E(p_7_out),
.empty(empty),
.\gc0.count_reg[0] (\gc0.count_reg[0] ),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.out(out),
.rd_clk(rd_clk),
.rd_en(rd_en),
.tmp_ram_rd_en(tmp_ram_rd_en));
fifo_EEPROM_rd_bin_cntr rpntr
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_0 ),
.E(p_7_out),
.Q(Q),
.\gnxpm_cdc.wr_pntr_bin_reg[5] (\gnxpm_cdc.wr_pntr_bin_reg[5] ),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] [1]),
.ram_empty_fb_i_reg(ram_empty_fb_i_reg),
.rd_clk(rd_clk));
endmodule
(* ORIG_REF_NAME = "rd_status_flags_as" *)
module fifo_EEPROM_rd_status_flags_as
(empty,
out,
tmp_ram_rd_en,
E,
\gc0.count_reg[0] ,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ,
rd_en);
output empty;
output out;
output tmp_ram_rd_en;
output [0:0]E;
input \gc0.count_reg[0] ;
input rd_clk;
input [1:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
input rd_en;
wire [0:0]E;
wire \gc0.count_reg[0] ;
wire [1:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
(* DONT_TOUCH *) wire ram_empty_fb_i;
(* DONT_TOUCH *) wire ram_empty_i;
wire rd_clk;
wire rd_en;
wire tmp_ram_rd_en;
assign empty = ram_empty_i;
assign out = ram_empty_fb_i;
LUT3 #(
.INIT(8'hF4))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_1
(.I0(ram_empty_fb_i),
.I1(rd_en),
.I2(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] [0]),
.O(tmp_ram_rd_en));
LUT2 #(
.INIT(4'h2))
\gc0.count_d1[5]_i_1
(.I0(rd_en),
.I1(ram_empty_fb_i),
.O(E));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_fb_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(\gc0.count_reg[0] ),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] [1]),
.Q(ram_empty_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(\gc0.count_reg[0] ),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] [1]),
.Q(ram_empty_i));
endmodule
(* ORIG_REF_NAME = "reset_blk_ramfifo" *)
module fifo_EEPROM_reset_blk_ramfifo
(out,
\gc0.count_reg[1] ,
\grstd1.grst_full.grst_f.rst_d3_reg_0 ,
wr_rst_busy,
rd_clk,
wr_clk,
rst);
output [1:0]out;
output [2:0]\gc0.count_reg[1] ;
output \grstd1.grst_full.grst_f.rst_d3_reg_0 ;
output wr_rst_busy;
input rd_clk;
input wr_clk;
input rst;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ;
wire p_7_out;
wire p_8_out;
wire rd_clk;
wire rd_rst_asreg;
(* DONT_TOUCH *) wire [2:0]rd_rst_reg;
wire rst;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d3;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg2;
wire wr_clk;
wire wr_rst_asreg;
(* DONT_TOUCH *) wire [2:0]wr_rst_reg;
assign \gc0.count_reg[1] [2:0] = rd_rst_reg;
assign \grstd1.grst_full.grst_f.rst_d3_reg_0 = rst_d2;
assign out[1:0] = wr_rst_reg[1:0];
assign wr_rst_busy = rst_d3;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d1_reg
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst_wr_reg2),
.Q(rst_d1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d2_reg
(.C(wr_clk),
.CE(1'b1),
.D(rst_d1),
.PRE(rst_wr_reg2),
.Q(rst_d2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d3_reg
(.C(wr_clk),
.CE(1'b1),
.D(rst_d2),
.PRE(rst_wr_reg2),
.Q(rst_d3));
fifo_EEPROM_synchronizer_ff \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst
(.in0(rd_rst_asreg),
.\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg (\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ),
.out(p_7_out),
.rd_clk(rd_clk));
fifo_EEPROM_synchronizer_ff_0 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst
(.in0(wr_rst_asreg),
.\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg (\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ),
.out(p_8_out),
.wr_clk(wr_clk));
fifo_EEPROM_synchronizer_ff_1 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.in0(rd_rst_asreg),
.out(p_7_out),
.rd_clk(rd_clk));
fifo_EEPROM_synchronizer_ff_2 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.in0(wr_rst_asreg),
.out(p_8_out),
.wr_clk(wr_clk));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg
(.C(rd_clk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ),
.PRE(rst_rd_reg2),
.Q(rd_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.Q(rd_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.Q(rd_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.Q(rd_rst_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_rd_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg
(.C(rd_clk),
.CE(1'b1),
.D(rst_rd_reg1),
.PRE(rst),
.Q(rst_rd_reg2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_wr_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg
(.C(wr_clk),
.CE(1'b1),
.D(rst_wr_reg1),
.PRE(rst),
.Q(rst_wr_reg2));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
(.C(wr_clk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ),
.PRE(rst_wr_reg2),
.Q(wr_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.Q(wr_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.Q(wr_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.Q(wr_rst_reg[2]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module fifo_EEPROM_synchronizer_ff
(out,
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ,
in0,
rd_clk);
output out;
output \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ;
input [0:0]in0;
input rd_clk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ;
wire rd_clk;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1
(.I0(in0),
.I1(Q_reg),
.O(\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module fifo_EEPROM_synchronizer_ff_0
(out,
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ,
in0,
wr_clk);
output out;
output \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ;
input [0:0]in0;
input wr_clk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ;
wire wr_clk;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1
(.I0(in0),
.I1(Q_reg),
.O(\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module fifo_EEPROM_synchronizer_ff_1
(AS,
out,
rd_clk,
in0);
output [0:0]AS;
input out;
input rd_clk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire out;
wire rd_clk;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module fifo_EEPROM_synchronizer_ff_2
(AS,
out,
wr_clk,
in0);
output [0:0]AS;
input out;
input wr_clk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire out;
wire wr_clk;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module fifo_EEPROM_synchronizer_ff__parameterized0
(D,
Q,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [5:0]D;
input [5:0]Q;
input rd_clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [5:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [5:0]Q_reg;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire rd_clk;
assign D[5:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[5]),
.Q(Q_reg[5]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module fifo_EEPROM_synchronizer_ff__parameterized0_3
(D,
Q,
wr_clk,
AR);
output [5:0]D;
input [5:0]Q;
input wr_clk;
input [0:0]AR;
wire [0:0]AR;
wire [5:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [5:0]Q_reg;
wire wr_clk;
assign D[5:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[5]),
.Q(Q_reg[5]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module fifo_EEPROM_synchronizer_ff__parameterized0_4
(out,
D,
\Q_reg_reg[5]_0 ,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [5:0]out;
output [1:0]D;
input [5:0]\Q_reg_reg[5]_0 ;
input rd_clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [1:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [5:0]Q_reg;
wire [5:0]\Q_reg_reg[5]_0 ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire rd_clk;
assign out[5:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[5]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[5]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[5]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[5]_0 [3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[5]_0 [4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[5]_0 [5]),
.Q(Q_reg[5]));
LUT3 #(
.INIT(8'h96))
\gnxpm_cdc.wr_pntr_bin[3]_i_1
(.I0(Q_reg[4]),
.I1(Q_reg[3]),
.I2(Q_reg[5]),
.O(D[0]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_bin[4]_i_1
(.I0(Q_reg[4]),
.I1(Q_reg[5]),
.O(D[1]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module fifo_EEPROM_synchronizer_ff__parameterized0_5
(out,
D,
\Q_reg_reg[5]_0 ,
wr_clk,
AR);
output [5:0]out;
output [1:0]D;
input [5:0]\Q_reg_reg[5]_0 ;
input wr_clk;
input [0:0]AR;
wire [0:0]AR;
wire [1:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [5:0]Q_reg;
wire [5:0]\Q_reg_reg[5]_0 ;
wire wr_clk;
assign out[5:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[5]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[5]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[5]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[5]_0 [3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[5]_0 [4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[5]_0 [5]),
.Q(Q_reg[5]));
LUT3 #(
.INIT(8'h96))
\gnxpm_cdc.rd_pntr_bin[3]_i_1
(.I0(Q_reg[4]),
.I1(Q_reg[3]),
.I2(Q_reg[5]),
.O(D[0]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_bin[4]_i_1
(.I0(Q_reg[4]),
.I1(Q_reg[5]),
.O(D[1]));
endmodule
(* ORIG_REF_NAME = "wr_bin_cntr" *)
module fifo_EEPROM_wr_bin_cntr
(Q,
ram_full_i_reg,
E,
wr_clk,
AR,
wr_rst_busy,
out,
wr_en,
\gnxpm_cdc.rd_pntr_bin_reg[5] );
output [5:0]Q;
output ram_full_i_reg;
input [0:0]E;
input wr_clk;
input [0:0]AR;
input wr_rst_busy;
input out;
input wr_en;
input [5:0]\gnxpm_cdc.rd_pntr_bin_reg[5] ;
wire [0:0]AR;
wire [0:0]E;
wire [5:0]Q;
wire [5:0]\gnxpm_cdc.rd_pntr_bin_reg[5] ;
wire \gwas.wsts/comp1 ;
wire \gwas.wsts/comp2 ;
wire out;
wire [5:0]p_13_out;
wire [5:0]plusOp__0;
wire ram_full_i_i_4_n_0;
wire ram_full_i_i_5_n_0;
wire ram_full_i_i_6_n_0;
wire ram_full_i_i_7_n_0;
wire ram_full_i_reg;
wire wr_clk;
wire wr_en;
wire [5:0]wr_pntr_plus2;
wire wr_rst_busy;
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT1 #(
.INIT(2'h1))
\gic0.gc0.count[0]_i_1
(.I0(wr_pntr_plus2[0]),
.O(plusOp__0[0]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT2 #(
.INIT(4'h6))
\gic0.gc0.count[1]_i_1
(.I0(wr_pntr_plus2[0]),
.I1(wr_pntr_plus2[1]),
.O(plusOp__0[1]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'h78))
\gic0.gc0.count[2]_i_1
(.I0(wr_pntr_plus2[0]),
.I1(wr_pntr_plus2[1]),
.I2(wr_pntr_plus2[2]),
.O(plusOp__0[2]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'h7F80))
\gic0.gc0.count[3]_i_1
(.I0(wr_pntr_plus2[1]),
.I1(wr_pntr_plus2[0]),
.I2(wr_pntr_plus2[2]),
.I3(wr_pntr_plus2[3]),
.O(plusOp__0[3]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gic0.gc0.count[4]_i_1
(.I0(wr_pntr_plus2[2]),
.I1(wr_pntr_plus2[0]),
.I2(wr_pntr_plus2[1]),
.I3(wr_pntr_plus2[3]),
.I4(wr_pntr_plus2[4]),
.O(plusOp__0[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\gic0.gc0.count[5]_i_1
(.I0(wr_pntr_plus2[3]),
.I1(wr_pntr_plus2[1]),
.I2(wr_pntr_plus2[0]),
.I3(wr_pntr_plus2[2]),
.I4(wr_pntr_plus2[4]),
.I5(wr_pntr_plus2[5]),
.O(plusOp__0[5]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_d1_reg[0]
(.C(wr_clk),
.CE(E),
.D(wr_pntr_plus2[0]),
.PRE(AR),
.Q(p_13_out[0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[1]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(wr_pntr_plus2[1]),
.Q(p_13_out[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[2]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(wr_pntr_plus2[2]),
.Q(p_13_out[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[3]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(wr_pntr_plus2[3]),
.Q(p_13_out[3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[4]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(wr_pntr_plus2[4]),
.Q(p_13_out[4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[5]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(wr_pntr_plus2[5]),
.Q(p_13_out[5]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[0]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(p_13_out[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[1]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(p_13_out[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[2]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(p_13_out[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[3]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(p_13_out[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[4]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(p_13_out[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[5]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(p_13_out[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[0]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[0]),
.Q(wr_pntr_plus2[0]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_reg[1]
(.C(wr_clk),
.CE(E),
.D(plusOp__0[1]),
.PRE(AR),
.Q(wr_pntr_plus2[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[2]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[2]),
.Q(wr_pntr_plus2[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[3]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[3]),
.Q(wr_pntr_plus2[3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[4]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[4]),
.Q(wr_pntr_plus2[4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[5]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[5]),
.Q(wr_pntr_plus2[5]));
LUT5 #(
.INIT(32'h55550400))
ram_full_i_i_1
(.I0(wr_rst_busy),
.I1(\gwas.wsts/comp2 ),
.I2(out),
.I3(wr_en),
.I4(\gwas.wsts/comp1 ),
.O(ram_full_i_reg));
LUT6 #(
.INIT(64'h0000000000009009))
ram_full_i_i_2
(.I0(\gnxpm_cdc.rd_pntr_bin_reg[5] [5]),
.I1(wr_pntr_plus2[5]),
.I2(\gnxpm_cdc.rd_pntr_bin_reg[5] [4]),
.I3(wr_pntr_plus2[4]),
.I4(ram_full_i_i_4_n_0),
.I5(ram_full_i_i_5_n_0),
.O(\gwas.wsts/comp2 ));
LUT6 #(
.INIT(64'h0000000000009009))
ram_full_i_i_3
(.I0(\gnxpm_cdc.rd_pntr_bin_reg[5] [5]),
.I1(p_13_out[5]),
.I2(\gnxpm_cdc.rd_pntr_bin_reg[5] [4]),
.I3(p_13_out[4]),
.I4(ram_full_i_i_6_n_0),
.I5(ram_full_i_i_7_n_0),
.O(\gwas.wsts/comp1 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'h6FF6))
ram_full_i_i_4
(.I0(wr_pntr_plus2[1]),
.I1(\gnxpm_cdc.rd_pntr_bin_reg[5] [1]),
.I2(wr_pntr_plus2[0]),
.I3(\gnxpm_cdc.rd_pntr_bin_reg[5] [0]),
.O(ram_full_i_i_4_n_0));
LUT4 #(
.INIT(16'h6FF6))
ram_full_i_i_5
(.I0(wr_pntr_plus2[3]),
.I1(\gnxpm_cdc.rd_pntr_bin_reg[5] [3]),
.I2(wr_pntr_plus2[2]),
.I3(\gnxpm_cdc.rd_pntr_bin_reg[5] [2]),
.O(ram_full_i_i_5_n_0));
LUT4 #(
.INIT(16'h6FF6))
ram_full_i_i_6
(.I0(p_13_out[1]),
.I1(\gnxpm_cdc.rd_pntr_bin_reg[5] [1]),
.I2(p_13_out[0]),
.I3(\gnxpm_cdc.rd_pntr_bin_reg[5] [0]),
.O(ram_full_i_i_6_n_0));
LUT4 #(
.INIT(16'h6FF6))
ram_full_i_i_7
(.I0(p_13_out[3]),
.I1(\gnxpm_cdc.rd_pntr_bin_reg[5] [3]),
.I2(p_13_out[2]),
.I3(\gnxpm_cdc.rd_pntr_bin_reg[5] [2]),
.O(ram_full_i_i_7_n_0));
endmodule
(* ORIG_REF_NAME = "wr_logic" *)
module fifo_EEPROM_wr_logic
(full,
WEBWE,
Q,
wr_clk,
out,
wr_en,
AR,
wr_rst_busy,
\gnxpm_cdc.rd_pntr_bin_reg[5] );
output full;
output [0:0]WEBWE;
output [5:0]Q;
input wr_clk;
input out;
input wr_en;
input [0:0]AR;
input wr_rst_busy;
input [5:0]\gnxpm_cdc.rd_pntr_bin_reg[5] ;
wire [0:0]AR;
wire [5:0]Q;
wire [0:0]WEBWE;
wire full;
wire [5:0]\gnxpm_cdc.rd_pntr_bin_reg[5] ;
wire \gwas.wsts_n_1 ;
wire out;
wire wpntr_n_6;
wire wr_clk;
wire wr_en;
wire wr_rst_busy;
fifo_EEPROM_wr_status_flags_as \gwas.wsts
(.E(WEBWE),
.full(full),
.\grstd1.grst_full.grst_f.rst_d2_reg (out),
.\grstd1.grst_full.grst_f.rst_d3_reg (wpntr_n_6),
.out(\gwas.wsts_n_1 ),
.wr_clk(wr_clk),
.wr_en(wr_en));
fifo_EEPROM_wr_bin_cntr wpntr
(.AR(AR),
.E(WEBWE),
.Q(Q),
.\gnxpm_cdc.rd_pntr_bin_reg[5] (\gnxpm_cdc.rd_pntr_bin_reg[5] ),
.out(\gwas.wsts_n_1 ),
.ram_full_i_reg(wpntr_n_6),
.wr_clk(wr_clk),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
endmodule
(* ORIG_REF_NAME = "wr_status_flags_as" *)
module fifo_EEPROM_wr_status_flags_as
(full,
out,
E,
\grstd1.grst_full.grst_f.rst_d3_reg ,
wr_clk,
\grstd1.grst_full.grst_f.rst_d2_reg ,
wr_en);
output full;
output out;
output [0:0]E;
input \grstd1.grst_full.grst_f.rst_d3_reg ;
input wr_clk;
input \grstd1.grst_full.grst_f.rst_d2_reg ;
input wr_en;
wire [0:0]E;
wire \grstd1.grst_full.grst_f.rst_d2_reg ;
wire \grstd1.grst_full.grst_f.rst_d3_reg ;
(* DONT_TOUCH *) wire ram_full_fb_i;
(* DONT_TOUCH *) wire ram_full_i;
wire wr_clk;
wire wr_en;
assign full = ram_full_i;
assign out = ram_full_fb_i;
LUT2 #(
.INIT(4'h2))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_2
(.I0(wr_en),
.I1(ram_full_fb_i),
.O(E));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_fb_i_reg
(.C(wr_clk),
.CE(1'b1),
.D(\grstd1.grst_full.grst_f.rst_d3_reg ),
.PRE(\grstd1.grst_full.grst_f.rst_d2_reg ),
.Q(ram_full_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_i_reg
(.C(wr_clk),
.CE(1'b1),
.D(\grstd1.grst_full.grst_f.rst_d3_reg ),
.PRE(\grstd1.grst_full.grst_f.rst_d2_reg ),
.Q(ram_full_i));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR4BB_4_V
`define SKY130_FD_SC_HD__NOR4BB_4_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog wrapper for nor4bb with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nor4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nor4bb_4 (
Y ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nor4bb base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nor4bb_4 (
Y ,
A ,
B ,
C_N,
D_N
);
output Y ;
input A ;
input B ;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nor4bb base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR4BB_4_V
|
//Copyright 2014 Zeno Futurista ([email protected])
//
//Licensed under the Apache License, Version 2.0 (the "License");
//you may not use this file except in compliance with the License.
//You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
//Unless required by applicable law or agreed to in writing, software
//distributed under the License is distributed on an "AS IS" BASIS,
//WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
//See the License for the specific language governing permissions and
//limitations under the License.
//I hope this writings will be usefull for someone, i am trying to follow nice "variable" namings
//so that it should be easy to understand even for people not skilled in verilog
//external module declaration
extern module hmacqueue #(parameter elementWidth = 32, parameter elementCount = 8, parameter depth = 256) (input clk,input write, input read, input [(elementWidth-1):0] in[0:(elementCount-1)], output [(elementWidth-1):0] out[0:(elementCount-1)], output available, output full);
//this module has following functions:
//deserializer/serializer for input output serial wire format
//sha job controller and result filter
module hmac_core_prescrypt(
input clk,
//result from sha mix
input [7:0] hashResult[0:127],
//job which corresponds to result
input [31:0] jobIn,
//corresponding nonce
input [31:0] nonceIn,
//result available signal
input resultReady,
//input data available signal
input load,
//input data
input[7:0] in,
//transmitter ready signal
input read,
//output data for sha mix
output[7:0] dataToHash[0:79],
//job for mix
output [31:0] jobOut,
//output signal for mix to begin work
output reg startHashing,
output reg[7:0] available,
//signal for transmitter - there is result available - start sending
output jobReady,
//output data for transmitter
output [7:0] out
);
//serializer/deserializer pointers
reg[10:0] write_ptr;
reg[10:0] read_ptr;
//output job nonce pair wires
wire [7:0] jobNonceMem[0:127];
//assemble job ID from deserialized data
assign jobOut = {header[84], header[85], header[86], header[87]};
//target used to compare result
//actual haeader working header (contains btc protocol header, target and jobID - header = 80B, target = 4B, job = 4B)
reg[7:0] header[0:87];
//data to be hashed (first 80B of receive header)
assign dataToHash = header[0:79];
//internal states
//we hit last nonce, signal that we need new work
reg requestWorkEnable;
//after all results have been sent, do actual request
wire requestNewWork = (requestWorkEnable & ~jobReady);
//we need to drop one result from result queue
reg resultSent;
wire [7:0] zeros[0:127];
//queues result if difficulty is met
hmacqueue #(.elementWidth(8), .elementCount(128), .depth(256)) rq(clk, difficultyMet | requestNewWork, resultSent, requestNewWork ? zeros : resultBuffer, jobNonceMem, jobReady);
//result buffer
reg [7:0] resultBuffer[0:127];
//difficulty met signal register
reg difficultyMet;
//some initials
initial begin
write_ptr = 0;
read_ptr = 0;
startHashing = 0;
end
//set actual output byte
assign out = jobNonceMem[read_ptr];
always @(posedge clk) begin
available <= 128;
if(load) begin
//there is something to deserialize
header[write_ptr] <= in;
if(write_ptr == 87) begin
write_ptr <= 0;
//all work data ready, start mixing
startHashing <= 1;
end else begin
write_ptr <= write_ptr + 1;
end
end
//switch off startHashing signal after one cycle
if(startHashing) begin
startHashing <= 0;
end
//buffer input jobnonce
resultBuffer <= hashResult;
if(resultReady) begin
//job filter, decides if we met requested difficulty
//difficultyMet <= ({hashResult[31],hashResult[30],hashResult[29],hashResult[28]} == 0) & ({hashResult[27],hashResult[26],hashResult[25],hashResult[24]} <= target);
difficultyMet <= 1;
//result with last nonce occured, we need new work
if((nonceIn == 32'hffffffff) && (jobIn == jobOut)) begin
requestWorkEnable <= 1;
end
end else begin
//otherwise nothing happened
difficultyMet <= 0;
end
//queue request new work packet (8 zeros)
//client driver understands to this message and knows that it should schedule new work
//therefore job should not use zero ID
if(requestNewWork) begin
requestWorkEnable <= 0;
end
//wait one cycle after sending last byte
if(resultSent) begin
resultSent <= 0;
end
//this end part is responsible for setting data to be sent
//there must be some job waiting in queue, transmitter ready to read, and one cycle pause after previous result (queue drops, it is probably not neccessarry cause queue is passtrough)
if(jobReady & read & ~resultSent) begin
if(read_ptr == 127) begin
//end of packet
read_ptr <= 0;
resultSent <= 1;
end else begin
read_ptr <= read_ptr +1;
end
end
end
endmodule
module hmac_core_postscrypt(
input clk,
//result from sha mix
input [7:0] hashResult[0:31],
//job which corresponds to result
input [31:0] jobIn,
//corresponding nonce
input [31:0] nonceIn,
//result available signal
input resultReady,
//input data available signal
input load,
//input data
input[7:0] in,
//transmitter ready signal
input read,
//output data for sha mix
output[7:0] dataToHash[0:127],
//job for mix
output [31:0] jobOut,
//output signal for mix to begin work
output reg startHashing,
//signal for transmitter - there is result available - start sending
output jobReady,
//output data for transmitter
output [7:0] out
);
//serializer/deserializer pointers
reg[10:0] write_ptr;
reg[10:0] read_ptr;
//output job nonce pair wires
wire [7:0] jobNonceMem[0:31];
//assemble job ID from deserialized data
assign jobOut = {header[84], header[85], header[86], header[87]};
//target used to compare result
//actual haeader working header (contains btc protocol header, target and jobID - header = 80B, target = 4B, job = 4B)
reg[7:0] header[0:127];
//data to be hashed (first 80B of receive header)
assign dataToHash = header[0:127];
//internal states
//we hit last nonce, signal that we need new work
reg requestWorkEnable;
//after all results have been sent, do actual request
wire requestNewWork = (requestWorkEnable & ~jobReady);
//we need to drop one result from result queue
reg resultSent;
wire [7:0] zeros[0:31];
//queues result if difficulty is met
hmacqueue #(.elementWidth(8), .elementCount(32), .depth(256)) rq(clk, difficultyMet | requestNewWork, resultSent, requestNewWork ? zeros : resultBuffer, jobNonceMem, jobReady);
//result buffer
reg [7:0] resultBuffer[0:31];
//difficulty met signal register
reg difficultyMet;
//some initials
initial begin
write_ptr = 0;
read_ptr = 0;
startHashing = 0;
end
//set actual output byte
assign out = jobNonceMem[read_ptr];
always @(posedge clk) begin
if(load) begin
//there is something to deserialize
header[write_ptr] <= in;
if(write_ptr == 127) begin
write_ptr <= 0;
//all work data ready, start mixing
startHashing <= 1;
end else begin
write_ptr <= write_ptr + 1;
end
end
//switch off startHashing signal after one cycle
if(startHashing) begin
startHashing <= 0;
end
//buffer input jobnonce
resultBuffer <= hashResult;
if(resultReady) begin
//job filter, decides if we met requested difficulty
//difficultyMet <= ({hashResult[31],hashResult[30],hashResult[29],hashResult[28]} == 0) & ({hashResult[27],hashResult[26],hashResult[25],hashResult[24]} <= target);
difficultyMet <= 1;
//result with last nonce occured, we need new work
//if((nonceIn == 32'hffffffff) && (jobIn == jobOut)) begin
//requestWorkEnable <= 1;
//end
end else begin
//otherwise nothing happened
difficultyMet <= 0;
end
//queue request new work packet (8 zeros)
//client driver understands to this message and knows that it should schedule new work
//therefore job should not use zero ID
if(requestNewWork) begin
requestWorkEnable <= 0;
end
//wait one cycle after sending last byte
if(resultSent) begin
resultSent <= 0;
end
//this end part is responsible for setting data to be sent
//there must be some job waiting in queue, transmitter ready to read, and one cycle pause after previous result (queue drops, it is probably not neccessarry cause queue is passtrough)
if(jobReady & read) begin
if(read_ptr == 31) begin
//end of packet
read_ptr <= 0;
resultSent <= 1;
end else begin
read_ptr <= read_ptr +1;
end
end
end
endmodule
|
/*
* PCI Express to FIFO example
* Copyright (C) 2014 Harmon Instruments, LLC
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/
*/
`include "config.vh"
module vna_dsp
(
output [`NLANES-1:0] pcie_txp,
output [`NLANES-1:0] pcie_txn,
input [`NLANES-1:0] pcie_rxp,
input [`NLANES-1:0] pcie_rxn,
input pcie_refclk_p,
input pcie_refclk_n,
input pcie_rst_n,
// SPI configuration flash, sck is to STARTUP_E2
output cflash_sdi,
output cflash_cs,
input cflash_sdo,
output [1:0] cflash_high,
output reg [3:0] led = 4'h5
);
wire clock;
reg [63:0] tpc_data = 0;
reg tpc_write = 0;
wire [63:0] fpc_data;
reg fpc_read = 1'b0;
wire [7:0] fifo_ready, fifo_reset;
wire [63:0] seq_fpc_data, seq_tpc_data;
wire seq_read, seq_write;
reg [63:0] count = 0;
reg count_write = 0;
reg null_read = 0;
assign cflash_high = 2'b11;
wire cflash_sck;
`ifdef USE_GT_DRP
wire [9*`NLANES-1:0] gt_drp_address;
wire [`NLANES-1:0] gt_drp_en, gt_drp_ready, gt_drp_we;
wire [16*`NLANES-1:0] gt_drp_di, gt_drp_do;
wire gt_drp_clock;
wire [16:0] seq_gtdrpdata[`NLANES-1:0];
`endif
wire seq_rvalid, seq_wvalid;
wire [15:0] seq_address;
wire [63:0] seq_wdata;
reg [63:0] seq_rdata0, seq_rdata1;
reg [63:0] seq_test;
wire [7:0] seq_spidata;
wire [16:0] seq_xadcdata;
hififo_pcie hififo
(.pci_exp_txp(pcie_txp),
.pci_exp_txn(pcie_txn),
.pci_exp_rxp(pcie_rxp),
.pci_exp_rxn(pcie_rxn),
.sys_clk_p(pcie_refclk_p),
.sys_clk_n(pcie_refclk_n),
.sys_rst_n(pcie_rst_n),
.clock(clock),
`ifdef USE_GT_DRP
.gt_drp_address(gt_drp_address),
.gt_drp_en(gt_drp_en),
.gt_drp_di(gt_drp_di),
.gt_drp_do(gt_drp_do),
.gt_drp_ready(gt_drp_ready),
.gt_drp_we(gt_drp_we),
.gt_drp_clock(gt_drp_clock),
`endif
.fifo_clock({8{clock}}),
.fifo_reset(fifo_reset),
.fifo_ready(fifo_ready),
.fifo_rw({1'b1,
count_write,
seq_write,
tpc_write,
fifo_ready[3],
null_read,
seq_read,
fpc_read}),
.fifo_data_0(fpc_data),
.fifo_data_1(seq_fpc_data),
.fifo_data_2(),
.fifo_data_3(),
.fifo_data_4(tpc_data),
.fifo_data_5(seq_tpc_data),
.fifo_data_6(count),
.fifo_data_7(64'h0)
);
sequencer #(.ABITS(16)) sequencer
(.clock(clock),
.reset(fifo_reset[1]),
.fpc_read(seq_read),
.fpc_valid(fifo_ready[1]),
.fpc_data(seq_fpc_data),
.tpc_ready(fifo_ready[5]),
.tpc_write(seq_write),
.tpc_data(seq_tpc_data),
.rvalid(seq_rvalid),
.wvalid(seq_wvalid),
.address(seq_address),
.wdata(seq_wdata),
.rdata(seq_rdata1),
.status(16'h0)
);
xadc xadc
(
.clock(clock),
.write(seq_wvalid && (seq_address == 5)),
.din(seq_wdata),
.dout(seq_xadcdata)
);
`ifdef USE_GT_DRP
genvar i;
generate
for (i = 0; i < `NLANES; i = i+1) begin: gtdrp
gt_drp gt_drp_n
(
.clock(clock),
.drp_clock(gt_drp_clock),
.write(seq_wvalid && (seq_address == 8+i)),
.din(seq_wdata),
.dout(seq_gtdrpdata[i]),
.drp_address(gt_drp_address[8+9*i:9*i]),
.drp_en(gt_drp_en[i]),
.drp_di(gt_drp_di[15+16*i:16*i]),
.drp_do(gt_drp_do[15+16*i:16*i]),
.drp_ready(gt_drp_ready[i]),
.drp_we(gt_drp_we[i])
);
end
endgenerate
`endif
spi_8bit_rw spi_cflash
(
.clock(clock),
.write(seq_wvalid && (seq_address == 4)),
.din(seq_wdata[8:0]),
.dout(seq_spidata),
.cs(cflash_cs),
.sck(cflash_sck),
.mosi(cflash_sdi),
.miso(cflash_sdo));
`ifndef SIM
(*keep="TRUE"*) STARTUPE2 STARTUPE2
(
// outputs
.CFGCLK(), // Configuration main clock output
.CFGMCLK(), // Configuration internal oscillator
.EOS(), // End Of Startup.
.PREQ(), // PROGRAM request to fabric output
// inputs
.CLK(1'b0), // user start-up clock input
.GSR(1'b0), // Global Set/Reset input
.GTS(1'b0), // Global 3-state input
.KEYCLEARB(1'b0), // Clear AES Key
.PACK(1'b0), // PROGRAM acknowledge input
.USRCCLKO(cflash_sck), // User CCLK input
.USRCCLKTS(1'b0), // User CCLK 3-state enable input
.USRDONEO(1'b0), // User DONE pin output control
.USRDONETS(1'b0) // User DONE 3-state enable output
);
`endif
always @ (posedge clock)
begin
if(seq_wvalid && seq_address == 0)
seq_test <= seq_wdata;
seq_rdata1 <= seq_rdata0;
if(seq_rvalid)
case(seq_address)
0: seq_rdata0 <= seq_test;
1: seq_rdata0 <= 64'd1;
2: seq_rdata0 <= 64'd2;
3: seq_rdata0 <= 64'd3;
4: seq_rdata0 <= seq_spidata;
5: seq_rdata0 <= seq_xadcdata;
`ifdef USE_GT_DRP
8: seq_rdata0 <= seq_gtdrpdata[0];
9: seq_rdata0 <= seq_gtdrpdata[1];
10: seq_rdata0 <= seq_gtdrpdata[2];
11: seq_rdata0 <= seq_gtdrpdata[3];
`endif
default: seq_rdata0 <= seq_address;
endcase
count <= fifo_reset[6] ? 1'b0 : count + fifo_ready[6];
count_write <= fifo_ready[6];
if(fifo_ready[0])
led[3:0] <= fpc_data[3:0];
fpc_read <= fifo_ready[4];
tpc_write <= fifo_ready[0] && fpc_read;
tpc_data <= fpc_data;
null_read <= fifo_ready[2];
end
initial
begin
$dumpfile("dump.vcd");
$dumpvars(0);
end
endmodule
|
//-----------------------------------------------------
// Design Name : syn_fifo
// File Name : syn_fifo.v
// Function : Synchronous (single clock) FIFO
//-----------------------------------------------------
`default_nettype none
module sync_fifo #(
parameter DATA_WIDTH = 8,
parameter FIFO_DEPTH = 16
)(
input wire i_clk,
input wire i_rst,
input wire i_rd_en,
input wire i_wr_en,
input wire [DATA_WIDTH-1:0] i_data_in,
output wire o_full,
output wire o_empty,
output reg [DATA_WIDTH-1:0] o_data_out = 0
);
parameter ADDR_WIDTH = $clog2(FIFO_DEPTH);
//-----------Internal variables-------------------
reg [ADDR_WIDTH-1:0] wr_pointer = 0;
reg [ADDR_WIDTH-1:0] rd_pointer = 0;
reg [ADDR_WIDTH:0] status_cnt = 0;
reg [DATA_WIDTH-1:0] mem [FIFO_DEPTH-1:0];
//-----------Variable assignments---------------
assign o_full = (status_cnt == (FIFO_DEPTH-1));
assign o_empty = (status_cnt == 0);
//-----------Code Start---------------------------
always @ (posedge i_clk or posedge i_rst)
begin: WRITE_POINTER
if (i_rst)
wr_pointer <= 0;
else if (i_wr_en)
wr_pointer <= wr_pointer + 1;
end
always @ (posedge i_clk or posedge i_rst)
begin: READ_POINTER
if (i_rst)
rd_pointer <= 0;
else if (i_rd_en)
rd_pointer <= rd_pointer + 1;
end
always @ (posedge i_clk or posedge i_rst)
begin: STATUS_COUNTER
if (i_rst)
status_cnt <= 0;
else if (i_rd_en && (!i_wr_en) && (status_cnt != 0))
status_cnt <= status_cnt - 1;
else if (i_wr_en && (!i_rd_en) && (status_cnt != FIFO_DEPTH))
status_cnt <= status_cnt + 1;
end
always @ (posedge i_clk)
begin: RAM
if (i_wr_en)
mem[wr_pointer] <= i_data_in;
if (i_rd_en)
o_data_out <= mem[rd_pointer];
end
endmodule
`default_nettype wire
/*---------- Testbench ----------------
sync_fifo #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH)
) myFIFO (
.i_clk(i_clk),
.i_rst(i_rst),
.i_rd_en(i_rd_en),
.i_wr_en(i_wr_en),
.i_data_in(i_data_in),
.o_full(o_full),
.o_empty(o_empty),
.o_data_out(o_data_out)
);
-------------------------------------*/
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR2B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__OR2B_FUNCTIONAL_PP_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__or2b (
X ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , B_N );
or or0 (or0_out_X , not0_out, A );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR2B_FUNCTIONAL_PP_V |
/*
* This module is made for use in bsg_cams, managing the valids and tags for each entry.
* We separate v_rs and tags so that we can support reset with minimal hardware.
* This module does not protect against setting multiple entries to the same value -- this must be
* prevented at a higher protocol level, if desired
*/
`include "bsg_defines.v"
module bsg_cam_1r1w_tag_array
#(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter multiple_entries_p = 0
, parameter safe_els_lp = `BSG_MAX(els_p,1)
)
(input clk_i
, input reset_i
// zero or one-hot
, input [safe_els_lp-1:0] w_v_i
// Mutually exclusive set or clear
, input w_set_not_clear_i
// Tag to set or clear
, input [width_p-1:0] w_tag_i
// Vector of empty CAM entries
, output logic [safe_els_lp-1:0] w_empty_o
// Async read
, input r_v_i
// Tag to match on read
, input [width_p-1:0] r_tag_i
// one or zero-hot
, output logic [safe_els_lp-1:0] r_match_o
);
logic [safe_els_lp-1:0][width_p-1:0] tag_r;
logic [safe_els_lp-1:0] v_r;
if (els_p == 0)
begin : zero
assign w_empty_o = '0;
assign r_match_o = '0;
end
else
begin : nz
for (genvar i = 0; i < els_p; i++)
begin : tag_array
bsg_dff_reset_en
#(.width_p(1))
v_reg
(.clk_i(clk_i)
,.reset_i(reset_i)
,.en_i(w_v_i[i])
,.data_i(w_set_not_clear_i)
,.data_o(v_r[i])
);
bsg_dff_en
#(.width_p(width_p))
tag_r_reg
(.clk_i(clk_i)
,.en_i(w_v_i[i] & w_set_not_clear_i)
,.data_i(w_tag_i)
,.data_o(tag_r[i])
);
assign r_match_o[i] = r_v_i & v_r[i] & (tag_r[i] == r_tag_i);
assign w_empty_o[i] = ~v_r[i];
end
end
//synopsys translate_off
always_ff @(negedge clk_i) begin
assert(multiple_entries_p || reset_i || $countones(r_match_o) <= 1)
else $error("Multiple similar entries are found in match_array\
%x while multiple_entries_p parameter is %d\n", r_match_o,
multiple_entries_p);
assert(reset_i || $countones(w_v_i & {safe_els_lp{w_set_not_clear_i}}) <= 1)
else $error("Inv_r one-hot write address %b\n", w_v_i);
end
//synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_cam_1r1w_tag_array)
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// The dtcm_ctrl module control the DTCM access requests
//
// ====================================================================
`include "e203_defines.v"
`ifdef E203_HAS_DTCM //{
module e203_dtcm_ctrl(
output dtcm_active,
// The cgstop is coming from CSR (0xBFE mcgstop)'s filed 1
// // This register is our self-defined CSR register to disable the
// DTCM SRAM clock gating for debugging purpose
input tcm_cgstop,
// Note: the DTCM ICB interface only support the single-transaction
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// LSU ICB to DTCM
// * Bus cmd channel
input lsu2dtcm_icb_cmd_valid, // Handshake valid
output lsu2dtcm_icb_cmd_ready, // Handshake ready
// Note: The data on rdata or wdata channel must be naturally
// aligned, this is in line with the AXI definition
input [`E203_DTCM_ADDR_WIDTH-1:0] lsu2dtcm_icb_cmd_addr, // Bus transaction start addr
input lsu2dtcm_icb_cmd_read, // Read or write
input [32-1:0] lsu2dtcm_icb_cmd_wdata,
input [4-1:0] lsu2dtcm_icb_cmd_wmask,
// * Bus RSP channel
output lsu2dtcm_icb_rsp_valid, // Response valid
input lsu2dtcm_icb_rsp_ready, // Response ready
output lsu2dtcm_icb_rsp_err, // Response error
// Note: the RSP rdata is inline with AXI definition
output [32-1:0] lsu2dtcm_icb_rsp_rdata,
`ifdef E203_HAS_DTCM_EXTITF //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// External-agent ICB to DTCM
// * Bus cmd channel
input ext2dtcm_icb_cmd_valid, // Handshake valid
output ext2dtcm_icb_cmd_ready, // Handshake ready
// Note: The data on rdata or wdata channel must be naturally
// aligned, this is in line with the AXI definition
input [`E203_DTCM_ADDR_WIDTH-1:0] ext2dtcm_icb_cmd_addr, // Bus transaction start addr
input ext2dtcm_icb_cmd_read, // Read or write
input [32-1:0] ext2dtcm_icb_cmd_wdata,
input [ 4-1:0] ext2dtcm_icb_cmd_wmask,
// * Bus RSP channel
output ext2dtcm_icb_rsp_valid, // Response valid
input ext2dtcm_icb_rsp_ready, // Response ready
output ext2dtcm_icb_rsp_err, // Response error
// Note: the RSP rdata is inline with AXI definition
output [32-1:0] ext2dtcm_icb_rsp_rdata,
`endif//}
output dtcm_ram_cs,
output dtcm_ram_we,
output [`E203_DTCM_RAM_AW-1:0] dtcm_ram_addr,
output [`E203_DTCM_RAM_MW-1:0] dtcm_ram_wem,
output [`E203_DTCM_RAM_DW-1:0] dtcm_ram_din,
input [`E203_DTCM_RAM_DW-1:0] dtcm_ram_dout,
output clk_dtcm_ram,
input test_mode,
input clk,
input rst_n
);
wire arbt_icb_cmd_valid;
wire arbt_icb_cmd_ready;
wire [`E203_DTCM_ADDR_WIDTH-1:0] arbt_icb_cmd_addr;
wire arbt_icb_cmd_read;
wire [`E203_DTCM_DATA_WIDTH-1:0] arbt_icb_cmd_wdata;
wire [`E203_DTCM_WMSK_WIDTH-1:0] arbt_icb_cmd_wmask;
wire arbt_icb_rsp_valid;
wire arbt_icb_rsp_ready;
wire arbt_icb_rsp_err;
wire [`E203_DTCM_DATA_WIDTH-1:0] arbt_icb_rsp_rdata;
`ifdef E203_HAS_DTCM_EXTITF //{
localparam DTCM_ARBT_I_NUM = 2;
localparam DTCM_ARBT_I_PTR_W = 1;
`else//}{
localparam DTCM_ARBT_I_NUM = 1;
localparam DTCM_ARBT_I_PTR_W = 1;
`endif//}
wire [DTCM_ARBT_I_NUM*1-1:0] arbt_bus_icb_cmd_valid;
wire [DTCM_ARBT_I_NUM*1-1:0] arbt_bus_icb_cmd_ready;
wire [DTCM_ARBT_I_NUM*`E203_DTCM_ADDR_WIDTH-1:0] arbt_bus_icb_cmd_addr;
wire [DTCM_ARBT_I_NUM*1-1:0] arbt_bus_icb_cmd_read;
wire [DTCM_ARBT_I_NUM*`E203_DTCM_DATA_WIDTH-1:0] arbt_bus_icb_cmd_wdata;
wire [DTCM_ARBT_I_NUM*`E203_DTCM_WMSK_WIDTH-1:0] arbt_bus_icb_cmd_wmask;
wire [DTCM_ARBT_I_NUM*1-1:0] arbt_bus_icb_rsp_valid;
wire [DTCM_ARBT_I_NUM*1-1:0] arbt_bus_icb_rsp_ready;
wire [DTCM_ARBT_I_NUM*1-1:0] arbt_bus_icb_rsp_err;
wire [DTCM_ARBT_I_NUM*`E203_DTCM_DATA_WIDTH-1:0] arbt_bus_icb_rsp_rdata;
assign arbt_bus_icb_cmd_valid =
//LSU take higher priority
{
`ifdef E203_HAS_DTCM_EXTITF //{
ext2dtcm_icb_cmd_valid,
`endif//}
lsu2dtcm_icb_cmd_valid
} ;
assign arbt_bus_icb_cmd_addr =
{
`ifdef E203_HAS_DTCM_EXTITF //{
ext2dtcm_icb_cmd_addr,
`endif//}
lsu2dtcm_icb_cmd_addr
} ;
assign arbt_bus_icb_cmd_read =
{
`ifdef E203_HAS_DTCM_EXTITF //{
ext2dtcm_icb_cmd_read,
`endif//}
lsu2dtcm_icb_cmd_read
} ;
assign arbt_bus_icb_cmd_wdata =
{
`ifdef E203_HAS_DTCM_EXTITF //{
ext2dtcm_icb_cmd_wdata,
`endif//}
lsu2dtcm_icb_cmd_wdata
} ;
assign arbt_bus_icb_cmd_wmask =
{
`ifdef E203_HAS_DTCM_EXTITF //{
ext2dtcm_icb_cmd_wmask,
`endif//}
lsu2dtcm_icb_cmd_wmask
} ;
assign {
`ifdef E203_HAS_DTCM_EXTITF //{
ext2dtcm_icb_cmd_ready,
`endif//}
lsu2dtcm_icb_cmd_ready
} = arbt_bus_icb_cmd_ready;
assign {
`ifdef E203_HAS_DTCM_EXTITF //{
ext2dtcm_icb_rsp_valid,
`endif//}
lsu2dtcm_icb_rsp_valid
} = arbt_bus_icb_rsp_valid;
assign {
`ifdef E203_HAS_DTCM_EXTITF //{
ext2dtcm_icb_rsp_err,
`endif//}
lsu2dtcm_icb_rsp_err
} = arbt_bus_icb_rsp_err;
assign {
`ifdef E203_HAS_DTCM_EXTITF //{
ext2dtcm_icb_rsp_rdata,
`endif//}
lsu2dtcm_icb_rsp_rdata
} = arbt_bus_icb_rsp_rdata;
assign arbt_bus_icb_rsp_ready = {
`ifdef E203_HAS_DTCM_EXTITF //{
ext2dtcm_icb_rsp_ready,
`endif//}
lsu2dtcm_icb_rsp_ready
};
sirv_gnrl_icb_arbt # (
.ARBT_SCHEME (0),// Priority based
.ALLOW_0CYCL_RSP (0),// Dont allow the 0 cycle response because for ITCM and DTCM,
// Dcache, .etc, definitely they cannot reponse as 0 cycle
.FIFO_OUTS_NUM (`E203_DTCM_OUTS_NUM),
.FIFO_CUT_READY(0),
.USR_W (1),
.ARBT_NUM (DTCM_ARBT_I_NUM ),
.ARBT_PTR_W (DTCM_ARBT_I_PTR_W),
.AW (`E203_DTCM_ADDR_WIDTH),
.DW (`E203_DTCM_DATA_WIDTH)
) u_dtcm_icb_arbt(
.o_icb_cmd_valid (arbt_icb_cmd_valid ) ,
.o_icb_cmd_ready (arbt_icb_cmd_ready ) ,
.o_icb_cmd_read (arbt_icb_cmd_read ) ,
.o_icb_cmd_addr (arbt_icb_cmd_addr ) ,
.o_icb_cmd_wdata (arbt_icb_cmd_wdata ) ,
.o_icb_cmd_wmask (arbt_icb_cmd_wmask) ,
.o_icb_cmd_burst () ,
.o_icb_cmd_beat () ,
.o_icb_cmd_lock () ,
.o_icb_cmd_excl () ,
.o_icb_cmd_size () ,
.o_icb_cmd_usr () ,
.o_icb_rsp_valid (arbt_icb_rsp_valid ) ,
.o_icb_rsp_ready (arbt_icb_rsp_ready ) ,
.o_icb_rsp_err (arbt_icb_rsp_err) ,
.o_icb_rsp_rdata (arbt_icb_rsp_rdata ) ,
.o_icb_rsp_usr (1'b0),
.o_icb_rsp_excl_ok (1'b0),
.i_bus_icb_cmd_ready (arbt_bus_icb_cmd_ready ) ,
.i_bus_icb_cmd_valid (arbt_bus_icb_cmd_valid ) ,
.i_bus_icb_cmd_read (arbt_bus_icb_cmd_read ) ,
.i_bus_icb_cmd_addr (arbt_bus_icb_cmd_addr ) ,
.i_bus_icb_cmd_wdata (arbt_bus_icb_cmd_wdata ) ,
.i_bus_icb_cmd_wmask (arbt_bus_icb_cmd_wmask) ,
.i_bus_icb_cmd_burst ({2*DTCM_ARBT_I_NUM{1'b0}}) ,
.i_bus_icb_cmd_beat ({2*DTCM_ARBT_I_NUM{1'b0}}) ,
.i_bus_icb_cmd_lock ({1*DTCM_ARBT_I_NUM{1'b0}}),
.i_bus_icb_cmd_excl ({1*DTCM_ARBT_I_NUM{1'b0}}),
.i_bus_icb_cmd_size ({2*DTCM_ARBT_I_NUM{1'b0}}),
.i_bus_icb_cmd_usr ({1*DTCM_ARBT_I_NUM{1'b0}}),
.i_bus_icb_rsp_valid (arbt_bus_icb_rsp_valid ) ,
.i_bus_icb_rsp_ready (arbt_bus_icb_rsp_ready ) ,
.i_bus_icb_rsp_err (arbt_bus_icb_rsp_err) ,
.i_bus_icb_rsp_rdata (arbt_bus_icb_rsp_rdata ) ,
.i_bus_icb_rsp_usr (),
.i_bus_icb_rsp_excl_ok (),
.clk (clk ) ,
.rst_n (rst_n)
);
wire sram_icb_cmd_ready;
wire sram_icb_cmd_valid;
wire [`E203_DTCM_ADDR_WIDTH-1:0] sram_icb_cmd_addr;
wire sram_icb_cmd_read;
wire [`E203_DTCM_DATA_WIDTH-1:0] sram_icb_cmd_wdata;
wire [`E203_DTCM_WMSK_WIDTH-1:0] sram_icb_cmd_wmask;
assign arbt_icb_cmd_ready = sram_icb_cmd_ready;
assign sram_icb_cmd_valid = arbt_icb_cmd_valid;
assign sram_icb_cmd_addr = arbt_icb_cmd_addr;
assign sram_icb_cmd_read = arbt_icb_cmd_read;
assign sram_icb_cmd_wdata = arbt_icb_cmd_wdata;
assign sram_icb_cmd_wmask = arbt_icb_cmd_wmask;
wire sram_icb_rsp_valid;
wire sram_icb_rsp_ready;
wire [`E203_DTCM_DATA_WIDTH-1:0] sram_icb_rsp_rdata;
wire sram_icb_rsp_err;
wire dtcm_sram_ctrl_active;
wire sram_icb_rsp_read;
`ifndef E203_HAS_ECC //{
sirv_sram_icb_ctrl #(
.DW (`E203_DTCM_DATA_WIDTH),
.AW (`E203_DTCM_ADDR_WIDTH),
.MW (`E203_DTCM_WMSK_WIDTH),
.AW_LSB (2),// DTCM is 32bits wide, so the LSB is 2
.USR_W (1)
) u_sram_icb_ctrl (
.sram_ctrl_active (dtcm_sram_ctrl_active),
.tcm_cgstop (tcm_cgstop),
.i_icb_cmd_valid (sram_icb_cmd_valid),
.i_icb_cmd_ready (sram_icb_cmd_ready),
.i_icb_cmd_read (sram_icb_cmd_read ),
.i_icb_cmd_addr (sram_icb_cmd_addr ),
.i_icb_cmd_wdata (sram_icb_cmd_wdata),
.i_icb_cmd_wmask (sram_icb_cmd_wmask),
.i_icb_cmd_usr (sram_icb_cmd_read ),
.i_icb_rsp_valid (sram_icb_rsp_valid),
.i_icb_rsp_ready (sram_icb_rsp_ready),
.i_icb_rsp_rdata (sram_icb_rsp_rdata),
.i_icb_rsp_usr (sram_icb_rsp_read),
.ram_cs (dtcm_ram_cs ),
.ram_we (dtcm_ram_we ),
.ram_addr (dtcm_ram_addr),
.ram_wem (dtcm_ram_wem ),
.ram_din (dtcm_ram_din ),
.ram_dout (dtcm_ram_dout),
.clk_ram (clk_dtcm_ram ),
.test_mode(test_mode ),
.clk (clk ),
.rst_n(rst_n)
);
assign sram_icb_rsp_err = 1'b0;
`endif//}
assign sram_icb_rsp_ready = arbt_icb_rsp_ready;
assign arbt_icb_rsp_valid = sram_icb_rsp_valid;
assign arbt_icb_rsp_err = sram_icb_rsp_err;
assign arbt_icb_rsp_rdata = sram_icb_rsp_rdata;
assign dtcm_active = lsu2dtcm_icb_cmd_valid | dtcm_sram_ctrl_active
`ifdef E203_HAS_DTCM_EXTITF //{
| ext2dtcm_icb_cmd_valid
`endif//}
;
endmodule
`endif//}
|
/*
* Copyright 2012, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
module ram #(
parameter DATA = 198,
parameter ADDR = 6
) (
input clk,
// Port A
input wire a_wr,
input wire [ADDR-1:0] a_addr,
input wire [DATA-1:0] a_din,
output reg [DATA-1:0] a_dout,
// Port B
input wire b_wr,
input wire [ADDR-1:0] b_addr,
input wire [DATA-1:0] b_din,
output reg [DATA-1:0] b_dout
);
// Shared memory
reg [DATA-1:0] mem [(2**ADDR)-1:0];
initial begin : init
integer i;
for(i = 0; i < (2**ADDR); i = i + 1)
mem[i] = 0;
end
// Port A
always @(posedge clk) begin
a_dout <= mem[a_addr];
if(a_wr) begin
a_dout <= a_din;
mem[a_addr] <= a_din;
end
end
// Port B
always @(posedge clk) begin
b_dout <= mem[b_addr];
if(b_wr) begin
b_dout <= b_din;
mem[b_addr] <= b_din;
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:15:57 06/13/2016
// Design Name:
// Module Name: LZD_4bit
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module LZD_4bit( in, out, valid
);
input [3:0]in;
output reg [1:0]out;
output reg valid;
wire v1,v2, l1, l2; // wire is used to pass data
initial
begin // initializing values to zero
out<=2'b00;
valid<=0;
end
LZD_2bit d1( .in(in[1:0]), .out(l1), .valid(v1)); // instantiating LDZ_2bit
LZD_2bit d2( .in(in[3:2]), .out(l2), .valid(v2));
always@(in,v1,v2,l1,l2) // logic is carried out when ever change in input, v1,v2,l1,l2 occurs
begin
if(v2==0&& v1==1)
begin
out<={{~v2},{l1}} ;
end
/* condition
when v2=0
v2 is 0 => l2= 0
in that case we see for v1
if v1=0 => l1= 0
we get out=0, valid=0
if v1=1 => l1= x
we take ~v2 in 2^1 position and l1 in 2^0 position to get no of leading zero terms
eg- 0011 we should get 2 as output
here v2= 0, l2=0, v1=1, l1=0
out= {{~(0),{0}}
out= {1,0}= 2'b10= 2 in decimal
there are 2 leading zeros in 0011
*/
else if( v2==0&&v1==0)
begin
out<=0;
end
else
begin
out<={{~v2},{l2}};
end
/*if v2=1 we dont consider values from v1 so we take
~v2 in 2^1 position and l2 in 2^0 position
so that we get accurate no of leading zero's
eg- 0101 we should get 1 as output
here v2=1, l2= 1, v1=1, l1=1
out={~{1},{1}}= {0,1}=2'b01= 1
there is one leading zero in 0101
*/
valid<= v1|v2; // valid= in[3]|in[2]|in[1]|in[0]
end
endmodule
|
/*
* PicoSoC - A simple example SoC using PicoRV32
*
* Copyright (C) 2017 Clifford Wolf <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module top (
input clk,
output tx,
input rx,
input [15:0] sw,
output [15:0] led,
);
wire clk_bufg;
BUFG bufg (.I(clk), .O(clk_bufg));
reg [5:0] reset_cnt = 0;
wire resetn = &reset_cnt;
always @(posedge clk_bufg) begin
reset_cnt <= reset_cnt + !resetn;
end
wire iomem_valid;
reg iomem_ready;
wire [3:0] iomem_wstrb;
wire [31:0] iomem_addr;
wire [31:0] iomem_wdata;
reg [31:0] iomem_rdata;
reg [31:0] gpio;
assign led = gpio[15:0];
always @(posedge clk_bufg) begin
if (!resetn) begin
gpio <= 0;
end else begin
iomem_ready <= 0;
if (iomem_valid && !iomem_ready && iomem_addr[31:24] == 8'h 03) begin
iomem_ready <= 1;
iomem_rdata <= {sw, gpio[15:0]};
if (iomem_wstrb[0]) gpio[ 7: 0] <= iomem_wdata[ 7: 0];
if (iomem_wstrb[1]) gpio[15: 8] <= iomem_wdata[15: 8];
if (iomem_wstrb[2]) gpio[23:16] <= iomem_wdata[23:16];
if (iomem_wstrb[3]) gpio[31:24] <= iomem_wdata[31:24];
end
end
end
picosoc_noflash soc (
.clk (clk_bufg),
.resetn (resetn ),
.ser_tx (tx),
.ser_rx (rx),
.irq_5 (1'b0 ),
.irq_6 (1'b0 ),
.irq_7 (1'b0 ),
.iomem_valid (iomem_valid ),
.iomem_ready (iomem_ready ),
.iomem_wstrb (iomem_wstrb ),
.iomem_addr (iomem_addr ),
.iomem_wdata (iomem_wdata ),
.iomem_rdata (iomem_rdata )
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04/26/2016 08:42:14 AM
// Design Name:
// Module Name: ROM_test
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ROM_test #(parameter W=32)
(
input wire [9:0] address,
output reg [W-1:0] data
);
//localparam ROM_FILE32 = "F:/VECTOR_Rango.txt";
//localparam ROM_FILE32 = "/home/jjrojas/Documents/0.0066777-0.58495_HEX.txt";
localparam ROM_FILE32 = "/home/carlos/Documents/Theta_2_ptofijo.txt";
//localparam ROM_FILE32 = "/home/carlos/Documents/0.58495-1.3485856_HEX.txt";
//localparam ROM_FILE32 = "/home/jjrojas/Documents/VECTOR_V_NORM_HEX.txt";
localparam ROM_FILE64= "C:\Users\Adri�n\Desktop\RTL\NORMALIZACION_V.txt";
//(* rom_style="{distributed | block}" *)
reg [W-1:0] rom_test [1023:0];
generate
if(W==32)
initial
begin
$readmemb( ROM_FILE32 , rom_test, 0, 1023);
end
else
initial
begin
$readmemh(ROM_FILE64, rom_test, 0, 1023);
end
endgenerate
always @*
begin
data = rom_test[address];
end
endmodule
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module contains a color map for foreground and background of *
* characters. *
* *
******************************************************************************/
module altera_up_video_fb_color_rom (
// Inputs
clk,
clk_en,
color_index,
// Bidirectionals
// Outputs
red,
green,
blue
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input clk_en;
input [ 3: 0] color_index;
// Bidirectionals
// Outputs
output [ 9: 0] red;
output [ 9: 0] green;
output [ 9: 0] blue;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [29: 0] color_data;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
assign red = color_data[29:20];
assign green = color_data[19:10];
assign blue = color_data[ 9: 0];
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altsyncram color_data_rom (
// Inputs
.clock0 (clk),
.clocken0 (clk_en),
.address_a (color_index),
// Bidirectionals
// Outputs
.q_a (color_data),
// Unused
.aclr0 (1'b0),
.aclr1 (1'b0),
.q_b (),
.clocken1 (1'b1),
.data_b (1'b1),
.wren_a (1'b0),
.data_a (1'b1),
.rden_b (1'b1),
.address_b (1'b1),
.wren_b (1'b0),
.byteena_b (1'b1),
.addressstall_a (1'b0),
.byteena_a (1'b1),
.addressstall_b (1'b0),
.clock1 (1'b1)
);
defparam
color_data_rom.clock_enable_input_a = "NORMAL",
color_data_rom.clock_enable_output_a = "NORMAL",
color_data_rom.init_file = "altera_up_video_fb_color_rom.mif",
color_data_rom.intended_device_family = "Cyclone II",
color_data_rom.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
color_data_rom.lpm_type = "altsyncram",
color_data_rom.numwords_a = 16,
color_data_rom.operation_mode = "ROM",
color_data_rom.outdata_aclr_a = "NONE",
color_data_rom.outdata_reg_a = "CLOCK0",
color_data_rom.power_up_uninitialized = "FALSE",
color_data_rom.read_during_write_mode_mixed_ports = "DONT_CARE",
color_data_rom.widthad_a = 4,
color_data_rom.width_a = 30,
color_data_rom.width_byteena_a = 1;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XOR3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__XOR3_FUNCTIONAL_PP_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__xor3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xor0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X , A, B, C );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xor0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__XOR3_FUNCTIONAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR4B_BEHAVIORAL_V
`define SKY130_FD_SC_MS__OR4B_BEHAVIORAL_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__or4b (
X ,
A ,
B ,
C ,
D_N
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input D_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire or0_out_X;
// Name Output Other arguments
not not0 (not0_out , D_N );
or or0 (or0_out_X, not0_out, C, B, A);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR4B_BEHAVIORAL_V |
`default_nettype none
`timescale 1ns / 1ps
// This module implements the set of 31 64-bit wide registers for the CPU.
//
// Note that reading the register bank is _synchronous_, not asynchronous.
// This means you must present the desired register address prior to a clock
// edge, and the contents of the indicated register will appear after that
// edge.
//
// This module assumes you're targeting the iCE40HX series of FPGAs.
//
// Signal Descriptions
// ===================
//
// clk_i Processor clock (also Wishbone's clock).
//
// rd_i Destination register address (0-31).
// rdat_i 64-bit data word to write to the destination register.
// This value may be sign or zero extended as per the write-
// enables below.
//
// rwe_i 1 allows the register bank to store the specified sign-
// or zero-extended value on rdat_i into the register addr-
// essed by rd_i.
//
// Note: if none of the rwe_i bits are set, then no value is
// stored into the register set. This is indistinguishable from
// forcing rd_i equal to 0.
//
// ra_i Source register addresses (0-31).
// rb_i
//
// rdata_o 64-bit value currently stored at the specified register
// rdatb_o address. Note that register 0 is hardwired to the value 0.
//
`include "xrs.vh"
module xrs(
input clk_i,
input [4:0] rd_i,
input [63:0] rdat_i,
input [2:0] rwe_i,
output [63:0] rdata_o,
output [63:0] rdatb_o,
input [4:0] ra_i,
input [4:0] rb_i
);
wire [63:0] rx_dat = ((rwe_i == `XRS_RWE_U8) ? {56'd0, rdat_i[7:0]} : 0)
| ((rwe_i == `XRS_RWE_U16) ? {48'd0, rdat_i[15:0]} : 0)
| ((rwe_i == `XRS_RWE_U32) ? {32'd0, rdat_i[31:0]} : 0)
| ((rwe_i == `XRS_RWE_S8) ? {{56{rdat_i[7]}}, rdat_i[7:0]} : 0)
| ((rwe_i == `XRS_RWE_S16) ? {{48{rdat_i[15]}}, rdat_i[15:0]} : 0)
| ((rwe_i == `XRS_RWE_S32) ? {{32{rdat_i[31]}}, rdat_i[31:0]} : 0)
| ((rwe_i == `XRS_RWE_S64) ? rdat_i : 0)
;
wire wen = |rwe_i;
wire [63:0] data_o, datb_o;
reg [4:0] ra_r, rb_r;
assign rdata_o = (|ra_r) ? data_o : 0;
assign rdatb_o = (|rb_r) ? datb_o : 0;
always @(posedge clk_i) begin
ra_r <= ra_i;
rb_r <= rb_i;
end
ram64b port0(
.wdata(rx_dat),
.wen(wen),
.waddr(rd_i),
.wclk(clk_i),
.rdata(data_o),
.raddr(ra_i),
.rclk(clk_i)
);
ram64b port1(
.wdata(rx_dat),
.wen(wen),
.waddr(rd_i),
.wclk(clk_i),
.rdata(datb_o),
.raddr(rb_i),
.rclk(clk_i)
);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: tlu.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name:
// Description: Trap Logic and Memory Management Unit (TLU) :
// - Contains :
// - Trap Stack Array (TSA)
// - Trap Control Logic (TCL)
// - Mmu internal Register Array (MRA)
// - Mmu Control Logic (MCL)
//
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "tlu.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module tlu (/*AUTOARG*/
short_si0,short_si1,short_so0,short_so1,si0,si1,so0,so1,
tlu_sftint_vld, tlu_hintp_vld, tlu_rerr_vld, tlu_lsu_tl_zero,
tlu_lsu_stxa_ack, tlu_lsu_redmode_rst_d1, // tlu_lsu_async_ack_w2,
tlu_lsu_pstate_priv, tlu_lsu_pstate_cle, tlu_lsu_pstate_am, tlu_lsu_tid_m,
tlu_lsu_pcxpkt, tlu_lsu_ldxa_tid_w2, tlu_lsu_stxa_ack_tid, tlu_lsu_redmode,
tlu_lsu_asi_update_m, tlu_lsu_asi_m,
tlu_itlb_wr_vld_g, tlu_itlb_tte_tag_w2, tlu_itlb_tte_data_w2,
tlu_itlb_tag_rd_g, tlu_itlb_rw_index_vld_g, tlu_itlb_rw_index_g,
tlu_itlb_dmp_actxt_g, tlu_itlb_invalidate_all_g, tlu_itlb_dmp_vld_g,
tlu_itlb_dmp_all_g, tlu_itlb_dmp_nctxt_g, tlu_ifu_trapnpc_w2,
tlu_sscan_test_data, // tlu_sscan_pc,
tlu_itlb_data_rd_g, tlu_ifu_trappc_vld_w1, tlu_ifu_trappc_w2,
tlu_ifu_trapnpc_vld_w1, tlu_ifu_trap_tid_w1, tlu_ifu_rstthr_i2,
tlu_ifu_rstint_i2, tlu_ifu_resumint_i2, tlu_ifu_pstate_pef,
tlu_ifu_pstate_ie, tlu_ifu_nukeint_i2, // tlu_ifu_int_activate_i3,
tlu_ifu_hwint_i3, tlu_idtlb_dmp_thrid_g, tlu_idtlb_dmp_key_g,
tlu_exu_cwpccr_update_m, tlu_exu_cwp_retry_m,
tlu_exu_cwp_m, tlu_exu_ccr_m, tlu_exu_agp_swap, tlu_exu_agp,
tlu_dtlb_tte_tag_w2, tlu_dtlb_tte_data_w2,
tlu_dtlb_tag_rd_g, tlu_dtlb_rw_index_vld_g, tlu_dtlb_rw_index_g,
tlu_dtlb_invalidate_all_g, tlu_dtlb_dmp_vld_g, tlu_exu_rsr_data_m,
tlu_dtlb_dmp_sctxt_g, tlu_dtlb_dmp_pctxt_g, tlu_dtlb_dmp_nctxt_g,
tlu_dtlb_dmp_all_g, tlu_dtlb_dmp_actxt_g, tlu_dtlb_data_rd_g,
tlu_lsu_int_ldxa_vld_w2, tlu_lsu_ldxa_async_data_vld, // tlu_ifu_flush_pipe_w,
ifu_lsu_error_inj, tlu_exu_agp_tid, tlu_hpstate_priv, tlu_hpstate_ibe,
tlu_hpstate_enb, tlu_early_flush_pipe_w, tlu_exu_early_flush_pipe_w,
tlu_early_flush_pipe2_w, tlu_lsu_int_ldxa_data_w2, tlu_lsu_int_ld_ill_va_w2,
tlu_exu_priv_trap_m, tlu_exu_pic_onebelow_m, tlu_exu_pic_twobelow_m,
lsu_exu_ldxa_m, lsu_exu_ldxa_data_g, tlu_dsfsr_flt_vld, tlu_lsu_priv_trap_m,
// tlu_lsu_priv_trap_w,
// Inputs
se, arst_l, grst_l, sehold, mem_write_disable, // rst_tri_en,
mux_drive_disable, lsu_tlu_wtchpt_trp_g, ifu_tlu_flush_fd3_w,
lsu_tlu_ttype_vld_m2, ifu_tlu_flush_fd_w, ifu_tlu_flush_fd2_w,
lsu_tlu_ttype_m2, lsu_tlu_tlb_st_inst_m, // lsu_tlu_tte_ebit_g,
lsu_tlu_tlb_ldst_va_m, lsu_tlu_tlb_ld_inst_m, lsu_tlu_tlb_dmp_va_m,
lsu_tlu_tlb_asi_state_m, lsu_tlu_tlb_access_tid_m, ifu_tlu_flush_m,
lsu_tlu_st_rs3_data_g, lsu_tlu_early_flush_w, lsu_tlu_early_flush2_w,
lsu_tlu_priv_action_g, lsu_tlu_pcxpkt_ack, // lsu_tlu_priv_violtn_g,
lsu_tlu_pctxt_m, lsu_tlu_async_ttype_vld_g, // lsu_tlu_nonalt_ldst_m,
lsu_tlu_misalign_addr_ldst_atm_m, ctu_sscan_tid, lsu_tlu_intpkt,
lsu_tlu_async_ttype_g, lsu_tlu_rs3_data_g, lsu_tlu_defr_trp_taken_g,
lsu_tlu_dtlb_done, lsu_tlu_dside_ctxt_m, // lsu_tlu_flt_ld_nfo_pg_g,
lsu_tlu_dmmu_miss_g, lsu_tlu_daccess_prot_g, // lsu_tlu_derr_tid_g,
lsu_tlu_daccess_excptn_g, lsu_tlu_cpx_vld, ifu_tlu_pc_oor_e,
lsu_tlu_cpx_req, ifu_tlu_inst_vld_m_bf1, ifu_mmu_trap_m, ifu_tlu_trap_m,
lsu_asi_state, lsu_asi_reg3, lsu_asi_reg2, lsu_tlu_async_tid_g,
lsu_asi_reg1, lsu_asi_reg0, ifu_tlu_ttype_vld_m, ifu_tlu_ttype_m,
ifu_tlu_thrid_d, ifu_tlu_swint_m, ifu_tlu_sir_inst_m, ifu_tlu_l2imiss,
ifu_tlu_rstint_m, ifu_tlu_retry_inst_d, ifu_tlu_priv_violtn_m, ifu_tlu_pc_m,
ifu_tlu_npc_m, ifu_tlu_immu_miss_m, ifu_tlu_itlb_done, ifu_tlu_inst_vld_m,
ifu_tlu_hwint_m, ifu_lsu_imm_asi_d, ifu_lsu_imm_asi_vld_d, ifu_tlu_done_inst_d,
ifu_lsu_st_inst_e, ifu_lsu_memref_d, ifu_lsu_ld_inst_e, ffu_tlu_trap_ue,
ffu_tlu_trap_other, ffu_tlu_trap_ieee754, ffu_tlu_ill_inst_m, ffu_ifu_tid_w2,
exu_tlu_va_oor_jl_ret_m, exu_tlu_ttype_vld_m, exu_tlu_ttype_m, exu_tlu_va_oor_m,
exu_tlu_spill_tid, exu_tlu_spill, exu_tlu_spill_other, exu_tlu_spill_wtype,
exu_tlu_misalign_addr_jmpl_rtn_m, exu_tlu_cwp_retry, exu_mmu_early_va_e,
exu_tlu_cwp_cmplt_tid, // exu_tlu_spill_ttype, exu_tlu_cwp_fastcmplt_w,
exu_tlu_cwp_cmplt, exu_tlu_cwp3, exu_tlu_cwp2, exu_tlu_cwp1,
exu_tlu_cwp0, exu_tlu_ccr3_w, exu_tlu_ccr2_w, lsu_tlu_ldst_va_m,
exu_tlu_ccr1_w, exu_tlu_ccr0_w, exu_lsu_ldst_va_e, const_cpuid,
rclk, ifu_tlu_sraddr_d, ifu_tlu_rsr_inst_d, // ifu_tlu_wsr_inst_d,
exu_tlu_wsr_data_m, lsu_tlu_rsr_data_e, ifu_tlu_sraddr_d_v2,
ifu_lsu_alt_space_e, lsu_tlu_squash_va_oor_m, ifu_tlu_imiss_e,
lsu_tlu_dcache_miss_w2, lsu_tlu_l2_dmiss, lsu_tlu_stb_full_w2,
ffu_tlu_fpu_tid, ffu_tlu_fpu_cmplt, spu_tlu_rsrv_illgl_m,
lsu_pid_state0, lsu_pid_state1, lsu_pid_state2, lsu_pid_state3,
lsu_tlu_nucleus_ctxt_m,lsu_tlu_tte_pg_sz_g, exu_tlu_ue_trap_m,
lsu_ifu_inj_ack, ifu_tlu_alt_space_d, // lsu_tlu_ill_inst_m,
ifu_lsu_thrid_s,lsu_dsfsr_din_g,lsu_dmmu_sfsr_trp_wr,lsu_mmu_flush_pipe_w,
exu_lsu_priority_trap_m, lsu_tlu_wsr_inst_e, lsu_mmu_defr_trp_taken_g);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
//
// input clk; // To tlu_int of sparc_tlu_int.v, ...
input rclk; // To tlu_int of sparc_tlu_int.v, ...
input [3:0] const_cpuid; // To tlu_int of sparc_tlu_int.v, ...
input [`ASI_VA_WIDTH-1:0] exu_lsu_ldst_va_e; // To mmu_dp of tlu_mmu_dp.v
input [`TLU_ASI_VA_WIDTH-1:0] lsu_tlu_ldst_va_m; // To mmu_dp of tlu_mmu_dp.v
input [7:0] exu_mmu_early_va_e; // From exu of sparc_exu.v
input [7:0] exu_tlu_ccr0_w; // To tdp of tlu_tdp.v
input [7:0] exu_tlu_ccr1_w; // To tdp of tlu_tdp.v
input [7:0] exu_tlu_ccr2_w; // To tdp of tlu_tdp.v
input [7:0] exu_tlu_ccr3_w; // To tdp of tlu_tdp.v
// modified due to timing
// input [2:0] exu_tlu_cwp0_w; // To tdp of tlu_tdp.v
// input [2:0] exu_tlu_cwp1_w; // To tdp of tlu_tdp.v
// input [2:0] exu_tlu_cwp2_w; // To tdp of tlu_tdp.v
// input [2:0] exu_tlu_cwp3_w; // To tdp of tlu_tdp.v
input [2:0] exu_tlu_cwp0; // To tdp of tlu_tdp.v
input [2:0] exu_tlu_cwp1; // To tdp of tlu_tdp.v
input [2:0] exu_tlu_cwp2; // To tdp of tlu_tdp.v
input [2:0] exu_tlu_cwp3; // To tdp of tlu_tdp.v
input exu_tlu_cwp_cmplt; // To tcl of tlu_tcl.v
input [1:0] exu_tlu_cwp_cmplt_tid; // To tcl of tlu_tcl.v
// input exu_tlu_cwp_fastcmplt_w;// To tcl of tlu_tcl.v
input exu_tlu_cwp_retry; // To tcl of tlu_tcl.v
input exu_tlu_misalign_addr_jmpl_rtn_m;// To tcl of tlu_tcl.v
input exu_tlu_spill; // To tcl of tlu_tcl.v
input [1:0] exu_tlu_spill_tid; // To tcl of tlu_tcl.v
// derive the spill_ttype from spill_other and spill_wtype
// input [8:0] exu_tlu_spill_ttype; // To tcl of tlu_tcl.v
input exu_tlu_spill_other; // From exu of sparc_exu.v
input [2:0] exu_tlu_spill_wtype; // From exu of sparc_exu.v
input [8:0] exu_tlu_ttype_m; // To tcl of tlu_tcl.v
input exu_tlu_ttype_vld_m; // To tcl of tlu_tcl.v
input exu_tlu_ue_trap_m;// To tcl of tlu_tcl.v
input exu_tlu_va_oor_jl_ret_m;// To tcl of tlu_tcl.v
input exu_tlu_va_oor_m; // To tcl of tlu_tcl.v
input ffu_tlu_ill_inst_m; // new trap from ffu
input [1:0] ffu_ifu_tid_w2; // To tcl of tlu_tcl.v
input ffu_tlu_trap_ieee754; // To tcl of tlu_tcl.v
input ffu_tlu_trap_other; // To tcl of tlu_tcl.v
input ffu_tlu_trap_ue; // To tcl of tlu_tcl.v
input ifu_lsu_ld_inst_e; // To mmu_ctl of tlu_mmu_ctl.v
input ifu_lsu_memref_d; // To tcl of tlu_tcl.v
input ifu_lsu_st_inst_e; // To mmu_ctl of tlu_mmu_ctl.v
input ifu_tlu_done_inst_d; // To tcl of tlu_tcl.v
// input ifu_tlu_flsh_inst_e; // To tcl of tlu_tcl.v
input ifu_tlu_flush_m; // To tcl of tlu_tcl.v
input ifu_tlu_flush_fd_w; // To tcl of tlu_tcl.v
input ifu_tlu_flush_fd2_w; // To tcl of tlu_tcl.v
input ifu_tlu_flush_fd3_w; // To tcl of tlu_tcl.v
input lsu_tlu_early_flush_w; // To tcl of tlu_tcl.v
input lsu_tlu_early_flush2_w; // To tcl of tlu_tcl.v
input ifu_tlu_hwint_m; // To tcl of tlu_tcl.v
input ifu_tlu_immu_miss_m; // To tcl of tlu_tcl.v, ...
input ifu_tlu_pc_oor_e; // To tcl of tlu_tcl.v
input [`TLU_THRD_NUM-1:0] ifu_tlu_l2imiss; // To tcl of tlu_tcl.v, ...
input ifu_tlu_inst_vld_m; // To tcl of tlu_tcl.v
input ifu_tlu_inst_vld_m_bf1; // To tcl of tlu_tcl.v
input ifu_tlu_itlb_done; // To mmu_ctl of tlu_mmu_ctl.v
// input [1:0] ifu_tlu_ldst_size_e; // To mmu_ctl of tlu_mmu_ctl.v
// modified for bug 3017
input [48:0] ifu_tlu_npc_m; // To tdp of tlu_tdp.v
input [48:0] ifu_tlu_pc_m; // To tdp of tlu_tdp.v
// input [47:0] ifu_tlu_npc_m; // To tdp of tlu_tdp.v
// input [47:0] ifu_tlu_pc_m; // To tdp of tlu_tdp.v
input ifu_tlu_priv_violtn_m; // To tcl of tlu_tcl.v
input ifu_tlu_retry_inst_d; // To tcl of tlu_tcl.v
input ifu_tlu_rstint_m; // To tcl of tlu_tcl.v
input ifu_tlu_sir_inst_m; // To tcl of tlu_tcl.v
input ifu_tlu_swint_m; // To tcl of tlu_tcl.v
input [1:0] ifu_tlu_thrid_d; // To tcl of tlu_tcl.v
input [1:0] ifu_lsu_thrid_s; // To tcl of tlu_tcl.v
input [8:0] ifu_tlu_ttype_m; // To tcl of tlu_tcl.v
input ifu_tlu_ttype_vld_m; // To tcl of tlu_tcl.v
input ifu_mmu_trap_m; // To tcl of tlu_tcl.v
input ifu_tlu_trap_m; // To tcl of tlu_tcl.v
input [7:0] lsu_asi_reg0; // To tdp of tlu_tdp.v
input [7:0] lsu_asi_reg1; // To tdp of tlu_tdp.v
input [7:0] lsu_asi_reg2; // To tdp of tlu_tdp.v
input [7:0] lsu_asi_reg3; // To tdp of tlu_tdp.v
input [`TLU_ASI_STATE_WIDTH-1:0] lsu_asi_state; // To tcl of tlu_tcl.v, ...
// added asynchronize trap to handle correctable dmmu parity error
input lsu_tlu_async_ttype_vld_g; // lsu asynchronous trap valid
input lsu_tlu_defr_trp_taken_g; // lsu asynchronous trap valid
input lsu_mmu_defr_trp_taken_g; // lsu asynchronous trap valid
input [6:0] lsu_tlu_async_ttype_g; // lsu asynchronous trap type
input [1:0] lsu_tlu_async_tid_g; // asynchronous trap - thread
input [3:0] lsu_tlu_cpx_req; // To tlu_int of sparc_tlu_int.v
input lsu_tlu_cpx_vld; // To tlu_int of sparc_tlu_int.v
// input [2:0] lsu_tlu_ctxt_sel_m; // To tcl of tlu_tcl.v
input lsu_tlu_daccess_excptn_g;// To tcl of tlu_tcl.v, ...
input lsu_tlu_daccess_prot_g; // To tcl of tlu_tcl.v, ...
// input [1:0] lsu_tlu_derr_tid_g; // To tcl of tlu_tcl.v
input lsu_tlu_dmmu_miss_g; // To tcl of tlu_tcl.v, ...
input [12:0] lsu_tlu_dside_ctxt_m; // To mmu_dp of tlu_mmu_dp.v
input lsu_tlu_dtlb_done; // To mmu_ctl of tlu_mmu_ctl.v
// input lsu_tlu_flt_ld_nfo_pg_g;// To tcl of tlu_tcl.v
// input lsu_tlu_illegal_asi_action_g;// To tcl of tlu_tcl.v
input [17:0] lsu_tlu_intpkt; // To tlu_int of sparc_tlu_int.v
// modified for shadow scan
// input [3:0] lsu_tlu_iobrdge_pc_sel;
input [`TLU_THRD_NUM-1:0] ctu_sscan_tid;
input lsu_tlu_misalign_addr_ldst_atm_m;// To tcl of tlu_tcl.v
// input lsu_tlu_nonalt_ldst_m; // To tcl of tlu_tcl.v
input [12:0] lsu_tlu_pctxt_m; // To mmu_dp of tlu_mmu_dp.v
input lsu_tlu_pcxpkt_ack; // To tlu_int of sparc_tlu_int.v
input lsu_tlu_priv_action_g; // To tcl of tlu_tcl.v
// input lsu_tlu_priv_violtn_g; // To tcl of tlu_tcl.v
// input lsu_tlu_spec_access_epage_g;// To tcl of tlu_tcl.v
input [63:0] lsu_tlu_st_rs3_data_g; // To tlu_int of sparc_tlu_int.v, ...
input [63:0] lsu_tlu_rs3_data_g; // To tlu_int of sparc_tlu_int.v, ...
// added for timing
input [1:0] lsu_tlu_tlb_access_tid_m;// To mmu_ctl of tlu_mmu_ctl.v
input [7:0] lsu_tlu_tlb_asi_state_m;// To mmu_ctl of tlu_mmu_ctl.v
input [47:13] lsu_tlu_tlb_dmp_va_m; // To mmu_dp of tlu_mmu_dp.v
input lsu_tlu_tlb_ld_inst_m; // To mmu_ctl of tlu_mmu_ctl.v
input [10:0] lsu_tlu_tlb_ldst_va_m; // To mmu_ctl of tlu_mmu_ctl.v
input lsu_tlu_tlb_st_inst_m; // To mmu_ctl of tlu_mmu_ctl.v
// input lsu_tlu_tte_ebit_g; // To tcl of tlu_tcl.v
input [8:0] lsu_tlu_ttype_m2; // To tcl of tlu_tcl.v
// removed unused bits
// input [1:0] lsu_tlu_ttype_tid_m2; // To tcl of tlu_tcl.v
input lsu_tlu_ttype_vld_m2; // To tcl of tlu_tcl.v
// input lsu_tlu_uncache_atomic_g;// To tcl of tlu_tcl.v
// input lsu_tlu_write_op_m; // To tcl of tlu_tcl.v
input lsu_tlu_wtchpt_trp_g; // To tcl of tlu_tcl.v
// input lsu_tlu_xslating_ldst_m;// To tcl of tlu_tcl.v
// input reset; // To mmu_ctl of tlu_mmu_ctl.v
// input rst_l; // To tcl of tlu_tcl.v, ...
input grst_l; // To tcl of tlu_tcl.v, ...
input arst_l; // To tcl of tlu_tcl.v, ...
// input rst_tri_en; // To tcl of tlu_tcl.v, ...
input mem_write_disable; // To tcl of tlu_tcl.v, ...
input mux_drive_disable; // To tcl of tlu_tcl.v, ...
// input testmode_l; // To tcl of tlu_tcl.v, ...
input sehold; // To tlu_int of sparc_tlu_int.v, ...
input se; // To tlu_int of sparc_tlu_int.v, ...
input si0,si1,short_si0,short_si1; // To tlu_int of sparc_tlu_int.v, ...
// End of automatics
// Read/Write Privileged State Register Access.
input [`TLU_ASR_ADDR_WIDTH-1:0] ifu_tlu_sraddr_d; // addr of sr(st/pr)
input [`TLU_ASR_ADDR_WIDTH-1:0] ifu_tlu_sraddr_d_v2; // addr of sr(st/pr)
input ifu_tlu_rsr_inst_d ; // valid rd sr(st/pr)
// modified for timing
// input ifu_tlu_wsr_inst_d ; // valid wr sr(st/pr)
input lsu_tlu_wsr_inst_e ; // valid wr sr(st/pr)
input [63:0] exu_tlu_wsr_data_m ; // pr/st data to irf.
// input [1:0] ifu_tlu_thrid_e ; // Thread id.
input [7:0] lsu_tlu_rsr_data_e ; // sr/pr rd data from lsu.
input ifu_lsu_alt_space_e; // alt-space access
input ifu_tlu_alt_space_d; // alt-space access - d stage
input lsu_tlu_squash_va_oor_m;// squash va_oor for mem-op.
// input lsu_tlu_ill_inst_m; // new illegal instru from spu via lsu
//
// new interfaces to the pib
input ifu_tlu_imiss_e; // icache misses -- New interface
input [3:0] lsu_tlu_dcache_miss_w2; // dcache miss -- new interface
input [3:0] lsu_tlu_l2_dmiss; // l2 misses -- new interface
input [3:0] lsu_tlu_stb_full_w2; // store buffer full -- new interface
input [1:0] ffu_tlu_fpu_tid; // ThrdID for the FF instr_cmplt -- new
input ffu_tlu_fpu_cmplt; // FF instru complete -- new
//
// New trap from SPU
// removed for timing fix
input spu_tlu_rsrv_illgl_m; // illegal instruction from SPU
input [2:0] lsu_pid_state0 ; // pid thread0 ; global use
input [2:0] lsu_pid_state1 ; // pid thread1 ; global use
input [2:0] lsu_pid_state2 ; // pid thread2 ; global use
input [2:0] lsu_pid_state3 ; // pid thread3 ; global use
// input [48:0] ifu_tlu_pc_w;
input lsu_tlu_nucleus_ctxt_m ;// access is nucleus context
input [2:0] lsu_tlu_tte_pg_sz_g ; // page-size of tte
input [3:0] ifu_lsu_error_inj ; // inject parity error into tlb
input [8:0] ifu_lsu_imm_asi_d; // asi state value from imm
input ifu_lsu_imm_asi_vld_d; // valid asi state value from imm
input [23:0] lsu_dsfsr_din_g ; // now from lsu instead of tlu_tcl
input [3:0] lsu_dmmu_sfsr_trp_wr ; // now from lsu instead of tlu_tcl
input lsu_mmu_flush_pipe_w ; // full trap
input exu_lsu_priority_trap_m ;//fill,ue
// output [5:0] int_tlu_rstid_i2; // From tlu_int of sparc_tlu_int.v
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [63:0] tlu_lsu_int_ldxa_data_w2; // From tlu_int of sparc_tlu_int.v
output tlu_lsu_int_ld_ill_va_w2; // From tlu_int of sparc_tlu_int.v
output tlu_lsu_int_ldxa_vld_w2; // From tlu_int of sparc_tlu_int.v
output so0,so1,short_so0,short_so1; // From tlu_int of sparc_tlu_int.v, ...
output tlu_dtlb_data_rd_g; // From mmu_ctl of tlu_mmu_ctl.v
output tlu_dtlb_dmp_actxt_g; // From mmu_ctl of tlu_mmu_ctl.v
output tlu_dtlb_dmp_all_g; // From mmu_ctl of tlu_mmu_ctl.v
//output tlu_dtlb_dmp_by_ctxt_g; // From mmu_ctl of tlu_mmu_ctl.v
output tlu_dtlb_dmp_nctxt_g; // From mmu_ctl of tlu_mmu_ctl.v
output tlu_dtlb_dmp_pctxt_g; // From mmu_ctl of tlu_mmu_ctl.v
output tlu_dtlb_dmp_sctxt_g; // From mmu_ctl of tlu_mmu_ctl.v
output tlu_dtlb_dmp_vld_g; // From mmu_ctl of tlu_mmu_ctl.v
output tlu_dtlb_invalidate_all_g;// From mmu_ctl of tlu_mmu_ctl.v
output [5:0] tlu_dtlb_rw_index_g; // From mmu_ctl of tlu_mmu_ctl.v
output tlu_dtlb_rw_index_vld_g;// From mmu_ctl of tlu_mmu_ctl.v
output tlu_dtlb_tag_rd_g; // From mmu_ctl of tlu_mmu_ctl.v
output [42:0] tlu_dtlb_tte_data_w2; // From mmu_dp of tlu_mmu_dp.v
output [58:0] tlu_dtlb_tte_tag_w2; // From mmu_dp of tlu_mmu_dp.v
output[3:0] lsu_ifu_inj_ack ; // ack for tlb error injection.
//
// width modified for hypervisor support
// output [2:0] tlu_exu_agp; // From tcl of tlu_tcl.v
output [`TSA_GLOBAL_WIDTH-1:0] tlu_exu_agp; // From tcl of tlu_tcl.v
output tlu_exu_agp_swap; // From tcl of tlu_tcl.v
output [1:0] tlu_exu_agp_tid; // From tcl of tlu_tcl.v
output [7:0] tlu_exu_ccr_m; // From tcl of tlu_tcl.v
output [2:0] tlu_exu_cwp_m; // From tcl of tlu_tcl.v
output tlu_exu_cwp_retry_m; // From tcl of tlu_tcl.v
output tlu_exu_cwpccr_update_m;// From tcl of tlu_tcl.v
// tlu_exu_rsr_data_e being replaced by tlu_exu_rsr_data_m
// the bus will become obsolete
// output [`TLU_ASR_DATA_WIDTH-1:0] tlu_exu_rsr_data_e; // From tdp of tlu_tdp.v
output [`TLU_ASR_DATA_WIDTH-1:0] tlu_exu_rsr_data_m; // From tdp of tlu_tdp.v
output [40:0] tlu_idtlb_dmp_key_g; // From mmu_dp of tlu_mmu_dp.v
output [1:0] tlu_idtlb_dmp_thrid_g; // From mmu_ctl of tlu_mmu_ctl.v
output [3:0] tlu_ifu_hwint_i3; // From tlu_int of sparc_tlu_int.v
// removed - ifu will derive the signal internally
// output [3:0] tlu_ifu_int_activate_i3;// From tlu_int of sparc_tlu_int.v
output tlu_ifu_nukeint_i2; // From tlu_int of sparc_tlu_int.v
output [3:0] tlu_ifu_pstate_ie; // From tlu_int of sparc_tlu_int.v
output [3:0] tlu_ifu_pstate_pef; // From tdp of tlu_tdp.v
output tlu_ifu_resumint_i2; // From tlu_int of sparc_tlu_int.v
output tlu_ifu_rstint_i2; // From tlu_int of sparc_tlu_int.v
output [3:0] tlu_ifu_rstthr_i2; // From tlu_int of sparc_tlu_int.v
output [1:0] tlu_ifu_trap_tid_w1; // From tcl of tlu_tcl.v
output tlu_ifu_trapnpc_vld_w1; // From tdp of tlu_tdp.v
output [48:0] tlu_ifu_trapnpc_w2; // From tdp of tlu_tdp.v
output [48:0] tlu_ifu_trappc_w2; // From tdp of tlu_tdp.v
// output [47:0] tlu_ifu_trapnpc_w2; // From tdp of tlu_tdp.v
// output [47:0] tlu_ifu_trappc_w2; // From tdp of tlu_tdp.v
output tlu_ifu_trappc_vld_w1; // From tcl of tlu_tcl.v
output tlu_itlb_data_rd_g; // From mmu_ctl of tlu_mmu_ctl.v
output tlu_itlb_dmp_actxt_g; // From mmu_ctl of tlu_mmu_ctl.v
output tlu_itlb_dmp_all_g; // From mmu_ctl of tlu_mmu_ctl.v
output tlu_itlb_dmp_nctxt_g; // From mmu_ctl of tlu_mmu_ctl.v
output tlu_itlb_dmp_vld_g; // From mmu_ctl of tlu_mmu_ctl.v
output tlu_itlb_invalidate_all_g;// From mmu_ctl of tlu_mmu_ctl.v
output [5:0] tlu_itlb_rw_index_g; // From mmu_ctl of tlu_mmu_ctl.v
output tlu_itlb_rw_index_vld_g;// From mmu_ctl of tlu_mmu_ctl.v
output tlu_itlb_tag_rd_g; // From mmu_ctl of tlu_mmu_ctl.v
output [42:0] tlu_itlb_tte_data_w2; // From mmu_dp of tlu_mmu_dp.v
output [58:0] tlu_itlb_tte_tag_w2; // From mmu_dp of tlu_mmu_dp.v
output tlu_itlb_wr_vld_g; // From mmu_ctl of tlu_mmu_ctl.v
output [7:0] tlu_lsu_asi_m; // From tcl of tlu_tcl.v
output tlu_lsu_asi_update_m; // From tcl of tlu_tcl.v
// replaced by shadow scan signals
output [62:0] tlu_sscan_test_data;// From tdp of tlu_tdp.v
// output [47:0] tlu_sscan_pc;// From tdp of tlu_tdp.v
// output [63:0] tlu_lsu_ldxa_data_w2; // From mmu_dp of tlu_mmu_dp.v
output [1:0] tlu_lsu_ldxa_tid_w2; // From mmu_ctl of tlu_mmu_ctl.v
output [25:0] tlu_lsu_pcxpkt; // From tlu_int of sparc_tlu_int.v
output [3:0] tlu_lsu_pstate_am; // From tcl of tlu_tcl.v
output [3:0] tlu_lsu_pstate_cle; // From tdp of tlu_tdp.v
output [3:0] tlu_lsu_pstate_priv; // From tdp of tlu_tdp.v
output [3:0] tlu_lsu_redmode; // From tcl of tlu_tcl.v
// output [3:0] tlu_lsu_redmode_rst; // From tcl of tlu_tcl.v
output [3:0] tlu_lsu_redmode_rst_d1; // From tcl of tlu_tcl.v
// output [`TLU_THRD_NUM-1:0] tlu_lsu_async_ack_w2; // From tcl of tlu_tcl.v
output tlu_lsu_stxa_ack; // From mmu_ctl of tlu_mmu_ctl.v
output [1:0] tlu_lsu_stxa_ack_tid; // From mmu_ctl of tlu_mmu_ctl.v
output [1:0] tlu_lsu_tid_m; // From tcl of tlu_tcl.v
output [`TLU_THRD_NUM-1:0] tlu_lsu_tl_zero; // From tcl of tlu_tcl.v
output [`TLU_THRD_NUM-1:0] tlu_sftint_vld; // From tcl of tlu_tcl.v
output [`TLU_THRD_NUM-1:0] tlu_hintp_vld; // From tcl of tlu_tcl.v
output [`TLU_THRD_NUM-1:0] tlu_rerr_vld; // From tcl of tlu_tcl.v
// End of automatics
// Outputs
// End of automatics
// output tlu_ifu_flush_pipe_w; // From tcl of tlu_tcl.v
output tlu_early_flush_pipe_w; // From tcl of tlu_tcl.v
output tlu_early_flush_pipe2_w; // From tcl of tlu_tcl.v
output tlu_exu_early_flush_pipe_w; // From tcl of tlu_tcl.v
output tlu_lsu_ldxa_async_data_vld ; // tlu_lsu_ldxa_data_vld is for async op.
output [`TLU_THRD_NUM-1:0] tlu_hpstate_priv;
output [`TLU_THRD_NUM-1:0] tlu_hpstate_enb;
// added for hpstate.ibe ECO
output [`TLU_THRD_NUM-1:0] tlu_hpstate_ibe;
output tlu_exu_priv_trap_m; // local traps send to exu
output tlu_lsu_priv_trap_m; // local traps send to exu
// output tlu_lsu_priv_trap_w; // local traps send to exu
output tlu_exu_pic_onebelow_m; // local traps send to exu
output tlu_exu_pic_twobelow_m; // local traps send to exu
//
// added for MMU performance enhancement
output lsu_exu_ldxa_m ;
output [63:0] lsu_exu_ldxa_data_g ;
// Added to shift dsfsr logic from tlu to lsu.
output [3:0] tlu_dsfsr_flt_vld; // From mmu_dp of tlu_mmu_dp.v
//
// added to abide to the Niagara reset methodology
wire tlu_rst; // local active high reset - from tlu_tcl
wire rclk; // temprary clock name
wire [63:0] tlu_pib_rsr_data_e; // From tdp of tlu_tdp.v
// wire tlu_rst_l; // local active high reset - from tlu_tcl
wire int_rst_l; // local active high reset - from tlu_tcl
// wire pib_rst_l; // local active high reset - from tlu_tcl
wire [1:0] tlu_incr_tick; // From tcl of tlu_tcl.v
wire [1:0] tlu_tckctr_in; // From tcl of tlu_tcl.v
// wire [60:0] tlu_tick_incr_dout; // To tdp of tlu_tdp.v
wire [61:0] tlu_incr64_dout; // To tdp of tlu_tdp.v
wire [61:0] tlu_tick_incr_din; // From tdp of tlu_tdp.v
wire tlu_tick_ctl_din; // To tlu_int of sparc_tlu_int.v
// modified for bug 3017
wire [48:0] tlu_restore_pc_w1;
wire [48:0] tlu_restore_npc_w1;
wire [48:0] tlu_pc_new_w;
wire [48:0] tlu_npc_new_w;
wire [33:0] tlu_partial_trap_pc_w1;
wire [1:0] tlu_int_tid_m; // To tlu_int of sparc_tlu_int.v
wire [3:0] tlu_sftint_vld; // From tcl of tlu_tcl.v
wire tlu_asi_write_g; // From hyperv of tlu_hyperv.v
wire tlu_tte_real_g ; // tte is real
wire [`TLU_THRD_NUM-1:0] tlu_hpstate_tlz;
wire [`TLU_ASI_STATE_WIDTH-1:0] tlu_asi_state_e;
// modified due to memory macro swap
//
// wire [`TSA_MEM_WIDTH-1:0] tsa_dout;
wire [`TSA_MEM_WIDTH-1:0] tsa0_dout;
wire [`TSA_MEM_WIDTH-1:0] tsa1_dout;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [`TLU_ASR_DATA_WIDTH-1:0] tlu_wsr_data_w; // From tdp of tlu_tdp.v
wire dmmu_any_sfsr_wr; // From mmu_ctl of tlu_mmu_ctl.v
wire [3:0] dmmu_sfar_wr_en_l; // From mmu_ctl of tlu_mmu_ctl.v
// wire [3:0] dmmu_sfsr_trp_wr; // From tcl of tlu_tcl.v
wire [3:0] dmmu_sfsr_wr_en_l; // From mmu_ctl of tlu_mmu_ctl.v
wire immu_any_sfsr_wr; // From mmu_ctl of tlu_mmu_ctl.v
wire [3:0] immu_sfsr_trp_wr; // From tcl of tlu_tcl.v
wire [3:0] immu_sfsr_wr_en_l; // From mmu_ctl of tlu_mmu_ctl.v
wire [5:0] int_tlu_rstid_m; // From tlu_int of sparc_tlu_int.v
wire itlb_wr_vld_g; // From mmu_ctl of tlu_mmu_ctl.v
wire [7:0] lsu_tlu_rsr_data_mod_e; // From tcl of tlu_tcl.v
wire [19:0] mra_byte_wen; // From mmu_ctl of tlu_mmu_ctl.v
wire [3:0] mra_rd_ptr; // From mmu_ctl of tlu_mmu_ctl.v
wire mra_rd_vld; // From mmu_ctl of tlu_mmu_ctl.v
wire [159:10] mra_rdata; // From mra of tlu_mra.v
wire [155:0] mra_wdata; // From mmu_dp of tlu_mmu_dp.v
wire [3:0] mra_wr_ptr; // From mmu_ctl of tlu_mmu_ctl.v
wire mra_wr_vld; // From mmu_ctl of tlu_mmu_ctl.v
wire [2:0] tag_access_wdata_sel; // From mmu_ctl of tlu_mmu_ctl.v
wire tlb_access_rst_l; // From mmu_ctl of tlu_mmu_ctl.v
wire tlu_addr_msk_g; // From tcl of tlu_tcl.v
wire tlu_admp_key_sel; // From mmu_ctl of tlu_mmu_ctl.v
wire tlu_clr_sftint_l_g; // From tcl of tlu_tcl.v
wire [4:0] tlu_dmp_key_vld_g; // From mmu_ctl of tlu_mmu_ctl.v
wire [2:0] tlu_true_pc_sel_w;
wire [48:0] ifu_npc_w;
wire [3:0] tlu_dsfsr_flt_vld; // From mmu_dp of tlu_mmu_dp.v
wire [47:13] tlu_dtag_access_w2; // From mmu_dp of tlu_mmu_dp.v
wire [3:0] tlu_dtsb_size_w2; // From mmu_dp of tlu_mmu_dp.v
wire tlu_dtsb_split_w2; // From mmu_dp of tlu_mmu_dp.v
wire [1:0] tlu_agp_tid_w2; // From tcl of tlu_tcl.v
wire [`TSA_TTYPE_WIDTH-1:0] tlu_final_offset_w1; // From tcl of tlu_tcl.v
wire [`TSA_TTYPE_WIDTH-1:0] tlu_final_ttype_w2; // From tcl of tlu_tcl.v
wire tlu_full_flush_pipe_w2; // From tcl of tlu_tcl.v
wire tlu_tcc_inst_w; // From tcl of tlu_tcl.v
wire tlu_local_flush_w; // From tcl of tlu_tcl.v
wire [47:0] tlu_idtsb_8k_ptr; // From mmu_ctl of tlu_mmu_ctl.v
wire tlu_asi_data_nf_vld_w2; // From mmu_ctl of tlu_mmu_ctl.v
wire tlu_inst_vld_nq_m; // From tcl of tlu_tcl.v
wire tlu_int_asi_load; // From mmu_ctl of tlu_mmu_ctl.v
wire [1:0] tlu_int_asi_thrid; // From mmu_ctl of tlu_mmu_ctl.v
wire tlu_int_asi_vld; // From mmu_ctl of tlu_mmu_ctl.v
wire [3:0] tlu_int_pstate_ie; // From tdp of tlu_tdp.v
wire [3:0] tlu_int_redmode; // From tdp of tlu_tdp.v
wire [23:0] tlu_isfsr_din_g; // From tcl of tlu_tcl.v
wire [3:0] tlu_isfsr_flt_vld; // From mmu_dp of tlu_mmu_dp.v
//wire [47:13] tlu_itsb_base_w2; // From mmu_dp of tlu_mmu_dp.v
wire [3:0] tlu_itsb_size_w2; // From mmu_dp of tlu_mmu_dp.v
wire tlu_itsb_split_w2; // From mmu_dp of tlu_mmu_dp.v
wire [3:0] tlu_ldxa_l1mx1_sel; // From mmu_ctl of tlu_mmu_ctl.v
wire [3:0] tlu_ldxa_l1mx2_sel; // From mmu_ctl of tlu_mmu_ctl.v
wire [2:0] tlu_ldxa_l2mx1_sel; // From mmu_ctl of tlu_mmu_ctl.v
// wire tlu_mmu_sync_data_excp_g;// From mmu_ctl of tlu_mmu_ctl.v
wire [3:0] tlu_pil; // From tcl of tlu_tcl.v
wire tlu_tlb_tag_invrt_parity ;
wire tlu_tlb_data_invrt_parity ;
wire tlu_sun4r_tte_g ; // sun4r vs. sun4v tte
//
// modified for bug 1767
/*
wire [1:0] tlu_pstate0_mmodel; // From tdp of tlu_tdp.v
wire [1:0] tlu_pstate1_mmodel; // From tdp of tlu_tdp.v
wire [1:0] tlu_pstate2_mmodel; // From tdp of tlu_tdp.v
wire [1:0] tlu_pstate3_mmodel; // From tdp of tlu_tdp.v
wire [`TLU_THRD_NUM-1:0] tlu_pstate_tle; // From tdp of tlu_tdp.v
wire [`TLU_THRD_NUM-1:0] tlu_pstate_cle; // From tdp of tlu_tdp.v
*/
wire [`TLU_THRD_NUM-1:0] tlu_pstate_am; // From tdp of tlu_tdp.v
wire [1:0] tlu_pstate_din_sel0; // From tcl of tlu_tcl.v
wire [1:0] tlu_pstate_din_sel1; // From tcl of tlu_tcl.v
wire [1:0] tlu_pstate_din_sel2; // From tcl of tlu_tcl.v
wire [1:0] tlu_pstate_din_sel3; // From tcl of tlu_tcl.v
// wire [`TLU_THRD_NUM-1:0] tlu_pstate_priv; // From tdp of tlu_tdp.v
// wire tlu_retry_inst_m; // From tcl of tlu_tcl.v
//
// modified for hypervisor support and bug 1767
/*
wire tlu_select_alt_global; // From tcl of tlu_tcl.v
wire tlu_select_int_global; // From tcl of tlu_tcl.v
wire tlu_select_mmu_global; // From tcl of tlu_tcl.v
wire [1:0] tlu_select_mmodel; // From tcl of tlu_tcl.v
wire tlu_select_tle; // From tcl of tlu_tcl.v
*/
wire tlu_select_redmode; // From tcl of tlu_tcl.v
// wire tlu_select_tba_g; // From tcl of tlu_tcl.v
wire tlu_select_tba_w2; // From tcl of tlu_tcl.v
wire tdp_select_tba_w2; // From tcl of tlu_tcl.v
// wire tlu_self_boot_rst_g; // From tcl of tlu_tcl.v
// wire tlu_self_boot_rst_w2; // From tcl of tlu_tcl.v
wire tlu_set_sftint_l_g; // From tcl of tlu_tcl.v
wire [`TLU_THRD_NUM-1:0] tlu_sftint_en_l_g; // From tcl of tlu_tcl.v
wire [`TLU_THRD_NUM-1:0] tlu_sftint_mx_sel; // From tcl of tlu_tcl.v
wire [3:0] tlu_sftint_id; // From tdp of tlu_tdp.v
// wire [3:0] tlu_sftint_lvl14_int; // From tcl of tlu_tcl.v
wire [3:0] tlu_sftint_penc_sel; // From tcl of tlu_tcl.v
wire [3:0] tlu_slxa_thrd_sel; // From mmu_ctl of tlu_mmu_ctl.v
wire [2:0] tlu_tag_access_ctxt_sel_m;// From tcl of tlu_tcl.v
//wire tlu_tag_access_nctxt_g; // From mmu_dp of tlu_mmu_dp.v
wire [`TLU_THRD_NUM-1:0] tlu_tba_en_l; // From tcl of tlu_tcl.v
wire [`TLU_THRD_NUM-1:0] tlu_thrd_rsel_e; // From tcl of tlu_tcl.v
// wire [`TLU_THRD_NUM-1:0] tlu_thrd_rsel_g; // From tcl of tlu_tcl.v
// wire [`TLU_THRD_NUM-1:0] tlu_thrd_wsel_g; // From tcl of tlu_tcl.v
wire [`TLU_THRD_NUM-1:0] tlu_thrd_wsel_w2; // From tcl of tlu_tcl.v
wire [`TLU_THRD_NUM-1:0] tlu_thread_wsel_g; // From tcl of tlu_tcl.v
wire [`TLU_THRD_NUM-1:0] tlu_thread_inst_vld_g; // From tcl of tlu_tcl.v
// wire [`TLU_THRD_NUM-1:0] tlu_thread_inst_vld_w2; // From tcl of tlu_tcl.v
wire tlu_tick_en_l; // From tcl of tlu_tcl.v
// wire [`TLU_THRD_NUM-1:0] tlu_tick_int; // From tcl of tlu_tcl.v
// wire [`TLU_THRD_NUM-1:0] tlu_stick_int; // From tcl of tlu_tcl.v
// wire tlu_tick_match; // From tdp of tlu_tdp.v
wire tlu_tick_npt; // From tcl of tlu_tcl.v
wire [`TLU_THRD_NUM-1:0] tlu_tickcmp_en_l; // From tcl of tlu_tcl.v
// wire tlu_tickcmp_intdis; // From tcl of tlu_tcl.v
wire [`TLU_THRD_NUM-1:0] tlu_tickcmp_sel; // From tcl of tlu_tcl.v
// wire tlu_tl_gt_0_g; // From tcl of tlu_tcl.v
wire tlu_tl_gt_0_w2; // From tcl of tlu_tcl.v
wire [2:0] tlu_trp_lvl; // From tcl of tlu_tcl.v
wire [2:0] tlu_tte_tag_g; // From mmu_ctl of tlu_mmu_ctl.v
wire [2:0] tlu_tte_wr_pid_g; // From mmu_ctl of tlu_mmu_ctl.v
// wire [`TLU_THRD_NUM-1:0] tlu_update_pc_l_m; // From tcl of tlu_tcl.v
wire [`TLU_THRD_NUM-1:0] tlu_update_pc_l_w; // From tcl of tlu_tcl.v
wire [`TLU_THRD_NUM-1:0] tlu_trap_cwp_en; // From tcl of tlu_tcl.v
wire tlu_cwp_no_change_m; // From tcl of tlu_tcl.v
// modified due to timing
// wire [3:0] tlu_update_pstate_l_g; // From tcl of tlu_tcl.v
wire [3:0] tlu_update_pstate_l_w2; // From tcl of tlu_tcl.v
wire tlu_wr_sftint_l_g; // From tcl of tlu_tcl.v
// wire tlu_wsr_inst_g; // From tcl of tlu_tcl.v
wire tlu_wsr_inst_nq_g; // From tcl of tlu_tcl.v
// wire tlu_wr_tsa_inst_g; // From tcl of tlu_tcl.v
wire tlu_wr_tsa_inst_w2; // From tcl of tlu_tcl.v
wire tsa_npc_en; // From tcl of tlu_tcl.v
wire tsa_pc_en; // From tcl of tlu_tcl.v
wire [1:0] tsa_rd_tid; // From tcl of tlu_tcl.v
wire [2:0] tsa_rd_tpl; // From tcl of tlu_tcl.v
wire tsa_rd_vld_e; // From tcl of tlu_tcl.v
wire tsa_rd_en; // From tcl of tlu_tcl.v
// wire [`TLU_TSA_WIDTH-1:0] tsa_rdata; // From tsa of tlu_tsa.v
wire tsa_tstate_en; // From tcl of tlu_tcl.v
wire tsa_htstate_en; // From tlu_hyperv of tlu_hyperv.v
wire tsa_ttype_en; // From tcl of tlu_tcl.v
wire [`TLU_TSA_WIDTH-1:0] tsa_wdata; // From tdp of tlu_tdp.v
wire [1:0] tsa_wr_tid; // From tcl of tlu_tcl.v
wire [2:0] tsa_wr_tpl; // From tcl of tlu_tcl.v
// modified due to tsa memory swap
wire [1:0] tsa_wr_vld; // From tcl of tlu_tcl.v
wire tlu_htstate_rw_d; // From tlu_hyperv of tlu_hyperv.v
wire tlu_htstate_rw_g; // From tlu_hyperv of tlu_hyperv.v
// modified due to rsr mux recode
// wire tlu_htba_mx2_sel; // From tlu_hyperv of tlu_hyperv.v
wire tlu_htickcmp_rw_e; // From tlu_hyperv of tlu_hyperv.v
// End of automatics
wire [`TLU_ASI_QUE_WIDTH-1:0] tlu_asi_queue_rdata_g;
wire tlu_asi_queue_rd_vld_g;
wire tlu_ld_data_vld_g;
wire tlu_va_ill_g;
// wire tlu_va_all_zero_g;
//
// modified for timing fixes
// wire [3:0] pib_priv_act_trap ;
wire [3:0] pib_priv_act_trap_m ;
// wire [`QUE_TRAP_SEL_WIDTH-1:0] tlu_que_trap_sel_m;
wire [5:0] tlu_ctxt_cfg_w2; // To mmu_ctl of tlu_mmu_ctl.v
wire [`TLU_THRD_NUM-1:0] pib_picl_wrap; // To tcl of tlu_tcl.v
wire [`TLU_THRD_NUM-1:0] pib_pich_wrap; // To tcl of tlu_tcl.v
wire [`TLU_THRD_NUM-1:0] pich_wrap_flg; // To tcl of tlu_tcl.v
wire [`TLU_THRD_NUM-1:0] pich_onebelow_flg; // To tcl of tlu_tcl.v
wire [`TLU_THRD_NUM-1:0] pich_twobelow_flg; // To tcl of tlu_tcl.v
wire tlu_pic_onebelow_e; // To tcl of tlu_tcl.v
wire tlu_pic_twobelow_e; // To tcl of tlu_tcl.v
wire tlu_pic_wrap_e; // To tcl of tlu_tcl.v
//
// modified for bug 5436: Niagara 2.0
wire [`TLU_THRD_NUM-1:0] tlu_pcr_ut; // To tcl of tlu_tcl.v
wire [`TLU_THRD_NUM-1:0] tlu_pcr_st; // To tcl of tlu_tcl.v
// wire tlu_pcr_ut_e; // To tcl of tlu_tcl.v
// wire tlu_pcr_st_e; // To tcl of tlu_tcl.v
wire tlu_pic_cnt_en_m; // To tcl of tlu_tcl.v
// wire [`TLU_THRD_NUM-1:0] pich_threebelow_flg; // To tcl of tlu_tcl.v
//
// added for hypervisor support
wire [`TSA_GLOBAL_WIDTH-1:0] tlu_dnrtry_global_g;
// wire tlu_htick_match;
// wire tlu_stick_match;
wire tlu_trap_hpstate_enb;
wire [`TLU_THRD_NUM-1:0] local_hpstate_priv;
wire [`TLU_THRD_NUM-1:0] tcl_hpstate_priv;
wire [`TLU_THRD_NUM-1:0] local_hpstate_enb;
wire [`TLU_THRD_NUM-1:0] tcl_hpstate_enb;
wire [`TLU_THRD_NUM-1:0] local_pstate_priv;
wire [`TLU_THRD_NUM-1:0] local_pstate_ie;
wire [`TSA_GLOBAL_WIDTH-1:0] tlu_gl_lvl0;
wire [`TSA_GLOBAL_WIDTH-1:0] tlu_gl_lvl1;
wire [`TSA_GLOBAL_WIDTH-1:0] tlu_gl_lvl2;
wire [`TSA_GLOBAL_WIDTH-1:0] tlu_gl_lvl3;
// wire [`TLU_THRD_NUM-1:0] tlu_hintp_en_l_g;
wire [`TLU_THRD_NUM-1:0] tlu_htba_en_l;
wire [`TLU_THRD_NUM-1:0] tlu_htickcmp_en_l;
// wire [`TLU_THRD_NUM-1:0] tlu_set_hintp_g;
wire [`TLU_THRD_NUM-1:0] tlu_set_hintp_sel_g;
wire [`TLU_THRD_NUM-1:0] tlu_stickcmp_en_l;
// modified for timing
// wire [`TLU_THRD_NUM-1:0] tlu_update_hpstate_l_g;
wire [`TLU_THRD_NUM-1:0] tlu_update_hpstate_l_w2;
wire [`TLU_THRD_NUM-1:0] tlu_wr_hintp_g;
wire [`TLU_THRD_NUM-1:0] tlu_cpu_mondo_cmp;
wire [`TLU_THRD_NUM-1:0] tlu_dev_mondo_cmp;
wire [`TLU_THRD_NUM-1:0] tlu_resum_err_cmp;
wire [`TLU_THRD_NUM-1:0] tlu_hintp;
wire [1:0] tlu_hpstate_din_sel0;
wire [1:0] tlu_hpstate_din_sel1;
wire [1:0] tlu_hpstate_din_sel2;
wire [1:0] tlu_hpstate_din_sel3;
wire [4:0] tlu_hyperv_rdpr_sel;
wire [2:0] tlu_rdpr_mx1_sel;
wire [2:0] tlu_rdpr_mx2_sel;
wire [1:0] tlu_rdpr_mx3_sel;
wire [1:0] tlu_rdpr_mx4_sel;
wire [2:0] tlu_rdpr_mx5_sel;
wire [2:0] tlu_rdpr_mx6_sel;
wire [3:0] tlu_rdpr_mx7_sel;
// modified for timing
// wire tlu_ibrkpt_trap_g;
wire tlu_ibrkpt_trap_w2;
// wire tlu_select_htba_g;
// wire tlu_select_htba_w2;
wire [2:0] tlu_pc_mxsel_w2;
// wire tlu_stickcmp_intdis;
wire tlu_htickcmp_intdis;
// wire tlu_gl_rw_g;
wire tlu_gl_rw_m;
wire [`TLU_THRD_NUM-1:0] tlu_por_rstint_g;
// modified due to timing
// wire tlu_thrd0_traps, tlu_thrd1_traps;
// wire tlu_thrd2_traps, tlu_thrd3_traps;
wire [`TLU_THRD_NUM-1:0] tlu_thrd_traps_w2;
wire tlu_dnrtry0_inst_g, tlu_dnrtry1_inst_g;
wire tlu_dnrtry2_inst_g, tlu_dnrtry3_inst_g;
wire tlu_scpd_rd_vld_m; // tlu_scpd_rd_vld_g;
wire tlu_scpd_wr_vld_g;
wire tlu_hscpd_dacc_excpt_m;
wire tlu_qtail_dacc_excpt_m;
wire [`SCPD_RW_ADDR_WIDTH-1:0] tlu_scpd_rd_addr_m;
wire [`SCPD_RW_ADDR_WIDTH-1:0] tlu_scpd_wr_addr_g;
wire [79:0] tlu_scpd_asi_rdata_g;
//
// added for the change of hierarchy to promote sparc_tlu_intdp and
// sparc_tlu_intctl onto the tlu level
// wire inc_ind_asi_inrr; // From intctl of sparc_tlu_intctl.v
wire [3:0] tlu_asi_rdata_mxsel_g; // From intctl of sparc_tlu_intctl.v
wire [3:0] inc_ind_asi_rd_invr; // From intctl of sparc_tlu_intctl.v
// wire [3:0] inc_ind_asi_thr; // From intctl of sparc_tlu_intctl.v
wire [3:0] tlu_local_thrid_g; // From intctl of sparc_tlu_intctl.v
wire [3:0] inc_ind_asi_wr_indr; // From intctl of sparc_tlu_intctl.v
wire [3:0] inc_ind_asi_wr_inrr; // From intctl of sparc_tlu_intctl.v
wire [3:0] inc_ind_indr_grant; // From intctl of sparc_tlu_intctl.v
wire [3:0] inc_ind_ld_int_i1; // From intctl of sparc_tlu_intctl.v
wire [3:0] inc_ind_rstthr_i1; // From intctl of sparc_tlu_intctl.v
wire [3:0] inc_ind_thr_m; // From intctl of sparc_tlu_intctl.v
wire [1:0] inc_indr_req_thrid; // From intctl of sparc_tlu_intctl.v
wire inc_indr_req_valid; // From intctl of sparc_tlu_intctl.v
wire [4:0] ind_inc_thrid_i1; // From intdp of sparc_tlu_intdp.v
wire [1:0] ind_inc_type_i1; // From intdp of sparc_tlu_intdp.v
// wire indr_inc_rst_pkt; // From intdp of sparc_tlu_intdp.v
wire [3:0] int_pending_i2_l; // From intdp of sparc_tlu_intdp.v
// hypervisor lite indicator
// wire [`TLU_THRD_NUM-1:0] tlu_hyper_lite;
wire [12:0] tlu_tag_access_ctxt_g ;
wire tlu_lng_ltncy_en_l ;
wire tlu_tsb_rd_ps0_sel ;
wire [47:13] tlu_tsb_base_w2_d1 ;
// scan chain wires
wire scan1_1;
wire scan1_2;
wire scan1_3;
wire scan0_1;
wire short_scan0_1;
wire short_scan0_2;
wire short_scan0_3;
wire short_scan0_4;
wire short_scan0_5;
wire short_scan0_6;
//=====================================================================================
// DUMMY WIRES FOR VLINT. TO BE FILTERED OUT.
wire [9:0] dummy_mra_rdata;
//=====================================================================================
/*
sparc_tlu_int AUTO_TEMPLATE (
.tlu_int_asi_state(lsu_asi_state[`TLU_ASI_STATE_WIDTH-1:0]),
.lsu_tlu_pmode (1'b1),
.int_tlu_longop_done());
*/
//
// modified the hierarchy to bring sparc_tlu_intdp and sparc_tlu_intctl
// to the tlu level - eliminating sparc_tlu_int
/*
sparc_tlu_int tlu_int (
.tlu_int_asi_state(lsu_asi_state[`TLU_ASI_STATE_WIDTH-1:0]),
.lsu_tlu_pmode (1'b1), // enable partition mode
.int_tlu_longop_done(), // use to switch in thread
// .tlu_int_asi_store(tlu_int_asi_store),
// Outputs
.int_scpd_asi_data(int_scpd_asi_data[63:0]),
.int_scpd_asi_data_vld(int_scpd_asi_data_vld),
.int_tlu_rstid_m (int_tlu_rstid_m[5:0]),
.so (so),
.tlu_ifu_hwint_i3(tlu_ifu_hwint_i3[3:0]),
// .tlu_ifu_int_activate_i3(tlu_ifu_int_activate_i3[3:0]),
.tlu_ifu_nukeint_i2(tlu_ifu_nukeint_i2),
.tlu_ifu_pstate_ie(tlu_ifu_pstate_ie[3:0]),
.tlu_ifu_resumint_i2(tlu_ifu_resumint_i2),
.tlu_ifu_rstint_i2(tlu_ifu_rstint_i2),
.tlu_ifu_rstthr_i2(tlu_ifu_rstthr_i2[3:0]),
.tlu_lsu_pcxpkt (tlu_lsu_pcxpkt[25:0]),
// Inputs
.lsu_tlu_st_rs3_data_g(lsu_tlu_rs3_data_g[63:0]),
.clk (rclk),
.const_cpuid (const_cpuid[3:0]),
.lsu_tlu_cpx_req (lsu_tlu_cpx_req[3:0]),
.lsu_tlu_cpx_vld (lsu_tlu_cpx_vld),
.lsu_tlu_intpkt (lsu_tlu_intpkt[17:0]),
.lsu_tlu_pcxpkt_ack(lsu_tlu_pcxpkt_ack),
.tlu_rst_l (tlu_rst_l),
.se (se),
.si (si),
.tlu_int_asi_load(tlu_int_asi_load),
.tlu_int_asi_thrid(tlu_int_asi_thrid[1:0]),
.tlu_int_asi_vld (tlu_int_asi_vld),
.tlu_int_pstate_ie(tlu_int_pstate_ie[3:0]),
.tlu_int_redmode (tlu_int_redmode[3:0]),
.tlu_int_sftint_pend(tlu_int_sftint_pend[3:0]),
.tlu_int_tid_m (tlu_int_tid_m[1:0]));
*/
sparc_tlu_intdp intdp(
.lsu_ind_intpkt_id(lsu_tlu_intpkt[`INT_VEC_HI:`INT_VEC_LO]),
.lsu_ind_intpkt_type(lsu_tlu_intpkt[`INT_TYPE_HI:`INT_TYPE_LO]),
.lsu_ind_intpkt_thr(lsu_tlu_intpkt[`INT_THR_HI:`INT_THR_LO]),
.so (scan1_1),
.si (si1),
/*AUTOINST*/
// Outputs
.int_pending_i2_l(int_pending_i2_l[3:0]),
.ind_inc_thrid_i1(ind_inc_thrid_i1[4:0]),
.ind_inc_type_i1(ind_inc_type_i1[1:0]),
.int_tlu_rstid_m(int_tlu_rstid_m[5:0]),
.tlu_lsu_pcxpkt(tlu_lsu_pcxpkt[25:0]),
.tlu_lsu_int_ldxa_data_w2(tlu_lsu_int_ldxa_data_w2[63:0]),
// Inputs
.rclk (rclk),
.se (se),
.tlu_rst_l(int_rst_l),
.lsu_tlu_st_rs3_data_g(lsu_tlu_rs3_data_g[63:0]),
.tlu_asi_rdata_mxsel_g(tlu_asi_rdata_mxsel_g[3:0]),
.tlu_scpd_asi_rdata_g(tlu_scpd_asi_rdata_g[`TLU_SCPD_DATA_WIDTH-1:0]),
.tlu_asi_queue_rdata_g(tlu_asi_queue_rdata_g[`TLU_ASI_QUE_WIDTH-1:0]),
.inc_ind_ld_int_i1(inc_ind_ld_int_i1[3:0]),
.inc_ind_rstthr_i1(inc_ind_rstthr_i1[3:0]),
.inc_ind_asi_thr(tlu_local_thrid_g[`TLU_THRD_NUM-1:0]),
.inc_ind_asi_wr_indr(inc_ind_asi_wr_indr[3:0]),
.inc_ind_indr_grant(inc_ind_indr_grant[3:0]),
.inc_ind_thr_m(inc_ind_thr_m[3:0]),
.inc_ind_asi_wr_inrr(inc_ind_asi_wr_inrr[3:0]),
.inc_ind_asi_rd_invr(inc_ind_asi_rd_invr[3:0]),
.inc_indr_req_valid(inc_indr_req_valid),
.inc_indr_req_thrid(inc_indr_req_thrid[1:0]));
sparc_tlu_intctl intctl(
.so (scan0_1),
.si (si0),
.tlu_int_asi_store(tlu_asi_write_g),
/*AUTOINST*/
// Outputs
.tlu_ifu_hwint_i3(tlu_ifu_hwint_i3[3:0]),
.tlu_ifu_rstthr_i2(tlu_ifu_rstthr_i2[3:0]),
.tlu_ifu_rstint_i2(tlu_ifu_rstint_i2),
.tlu_ifu_nukeint_i2(tlu_ifu_nukeint_i2),
.tlu_ifu_resumint_i2(tlu_ifu_resumint_i2),
.tlu_ifu_pstate_ie(tlu_ifu_pstate_ie[3:0]),
.int_tlu_longop_done(),
.inc_ind_ld_int_i1(inc_ind_ld_int_i1[3:0]),
.inc_ind_rstthr_i1(inc_ind_rstthr_i1[3:0]),
.inc_ind_indr_grant(inc_ind_indr_grant[3:0]),
.inc_ind_thr_m(inc_ind_thr_m[3:0]),
.inc_indr_req_valid(inc_indr_req_valid),
.inc_indr_req_thrid(inc_indr_req_thrid[1:0]),
.tlu_asi_data_nf_vld_w2(tlu_asi_data_nf_vld_w2),
.tlu_lsu_int_ld_ill_va_w2(tlu_lsu_int_ld_ill_va_w2),
.tlu_asi_rdata_mxsel_g(tlu_asi_rdata_mxsel_g[3:0]),
.int_rst_l (int_rst_l),
// Inputs
.rclk (rclk),
.se (se),
.sehold (sehold),
.grst_l (grst_l),
.arst_l (arst_l),
.rst_tri_en (mux_drive_disable),
.const_cpuid(const_cpuid[3:0]),
.lsu_tlu_cpx_vld(lsu_tlu_cpx_vld),
.lsu_tlu_cpx_req(lsu_tlu_cpx_req[3:0]),
.lsu_tlu_pcxpkt_ack(lsu_tlu_pcxpkt_ack),
.ind_inc_thrid_i1(ind_inc_thrid_i1[4:0]),
.ind_inc_type_i1(ind_inc_type_i1[1:0]),
.tlu_int_asi_vld(tlu_int_asi_vld),
.tlu_int_asi_load(tlu_int_asi_load),
.tlu_int_asi_thrid(tlu_int_asi_thrid[1:0]),
.tlu_int_asi_state(lsu_asi_state[7:0]),
.tlu_int_tid_m(tlu_int_tid_m[1:0]),
.tlu_int_pstate_ie(tlu_int_pstate_ie[3:0]),
.tlu_asi_queue_rd_vld_g(tlu_asi_queue_rd_vld_g),
.tlu_ld_data_vld_g(tlu_ld_data_vld_g),
.tlu_va_ill_g(tlu_va_ill_g),
.int_pending_i2_l(int_pending_i2_l[3:0]));
tlu_misctl misctl (
// output
.tlu_exu_pic_onebelow_m (tlu_exu_pic_onebelow_m),
.tlu_exu_pic_twobelow_m (tlu_exu_pic_twobelow_m),
.tlu_exu_cwp_m (tlu_exu_cwp_m[`TSA_CWP_WIDTH-1:0]),
.tlu_exu_ccr_m (tlu_exu_ccr_m[`TSA_CCR_WIDTH-1:0]),
.tlu_lsu_asi_m (tlu_lsu_asi_m[`TLU_ASI_STATE_WIDTH-1:0]),
.tlu_cwp_no_change_m (tlu_cwp_no_change_m),
.tlu_sscan_misctl_data (tlu_sscan_test_data[`MISCTL_SSCAN_HI:`MISCTL_SSCAN_LO]),
.tlu_ifu_trappc_w2 (tlu_ifu_trappc_w2[48:0]),
.tlu_ifu_trapnpc_w2 (tlu_ifu_trapnpc_w2[48:0]),
.tlu_pc_new_w (tlu_pc_new_w[48:0]),
.tlu_npc_new_w (tlu_npc_new_w[48:0]),
.so (short_so0),
// inputs
.ctu_sscan_tid (ctu_sscan_tid[`TLU_THRD_NUM-1:0]),
.ifu_tlu_pc_m (ifu_tlu_pc_m[48:0]),
// .ifu_tlu_npc_m (ifu_tlu_npc_m[48:0]),
.ifu_npc_w (ifu_npc_w[48:0]),
.exu_tlu_cwp0 (exu_tlu_cwp0[`TSA_CWP_WIDTH-1:0]),
.exu_tlu_cwp1 (exu_tlu_cwp1[`TSA_CWP_WIDTH-1:0]),
.exu_tlu_cwp2 (exu_tlu_cwp2[`TSA_CWP_WIDTH-1:0]),
.exu_tlu_cwp3 (exu_tlu_cwp3[`TSA_CWP_WIDTH-1:0]),
.tlu_partial_trap_pc_w1 (tlu_partial_trap_pc_w1[33:0]),
.tlu_restore_pc_w1 (tlu_restore_pc_w1[48:0]),
.tlu_restore_npc_w1 (tlu_restore_npc_w1[48:0]),
.tlu_final_ttype_w2 (tlu_final_ttype_w2[`TSA_TTYPE_WIDTH-1:0]),
.tlu_final_offset_w1 (tlu_final_offset_w1[`TSA_TTYPE_WIDTH-1:0]),
.tlu_restore_pc_sel_w1 (tlu_restore_pc_sel_w1),
// .tlu_retry_inst_m (tlu_retry_inst_m),
// .tlu_done_inst_m (tlu_done_inst_m),
// .tlu_dnrtry_inst_m_l (tlu_dnrtry_inst_m_l),
.tlu_true_pc_sel_w (tlu_true_pc_sel_w[2:0]),
.tsa_wr_tid (tsa_wr_tid[1:0]),
.tsa1_wr_vld (tsa_wr_vld[1]),
.tsa_ttype_en (tsa_ttype_en),
.tsa_rd_vld_e (tsa_rd_vld_e),
// .tsa_rd_vld (tsa_rd_vld),
.tsa0_rdata_cwp (tsa0_dout[`TSA0_MEM_CWP_HI:`TSA0_MEM_CWP_LO]),
.tsa0_rdata_pstate (tsa0_dout[`TSA0_MEM_PSTATE_HI:`TSA0_MEM_PSTATE_LO]),
.tsa0_rdata_asi (tsa0_dout[`TSA0_MEM_ASI_HI:`TSA0_MEM_ASI_LO]),
.tsa0_rdata_ccr (tsa0_dout[`TSA0_MEM_CCR_HI:`TSA0_MEM_CCR_LO]),
.tsa0_rdata_gl (tsa0_dout[`TSA0_MEM_GL_HI:`TSA0_MEM_GL_LO]),
.tsa0_rdata_pc (tsa0_dout[`TSA0_TPC_HI:`TSA0_TPC_LO]),
.tsa1_rdata_ttype (tsa1_dout[`TSA1_TTYPE_HI:`TSA1_TTYPE_LO]),
.tsa1_rdata_npc (tsa1_dout[`TSA1_TNPC_HI:`TSA1_TNPC_LO]),
.tsa1_rdata_htstate (tsa1_dout[`TSA1_HTSTATE_HI:`TSA1_HTSTATE_LO]),
.tlu_thrd_rsel_e (tlu_thrd_rsel_e[`TLU_THRD_NUM-1:0]),
// experiement
.tlu_pic_onebelow_e (tlu_pic_onebelow_e),
.tlu_pic_twobelow_e (tlu_pic_twobelow_e),
.tlu_pic_cnt_en_m (tlu_pic_cnt_en_m),
// .pich_onebelow_flg (pich_onebelow_flg[`TLU_THRD_NUM-1:0]),
// .pich_twobelow_flg (pich_twobelow_flg[`TLU_THRD_NUM-1:0]),
// .pich_threebelow_flg (pich_threebelow_flg[`TLU_THRD_NUM-1:0]),
// .tlu_thread_inst_vld_w2 (tlu_thread_inst_vld_w2[`TLU_THRD_NUM-1:0]),
//
.tlu_rst (tlu_rst),
.se (se),
.si (short_scan0_6),
.rclk (rclk));
tlu_tcl tcl (
.so (short_so1),
.si (short_si1),
.tlu_wsr_data_b63_w (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-1]),
.tlu_itag_acc_sel_g (tlu_itag_acc_sel_g),
.pib_priv_act_trap_m (pib_priv_act_trap_m[3:0]),
.spu_tlu_rsrv_illgl_m (spu_tlu_rsrv_illgl_m),
.tlu_cpu_mondo_cmp (tlu_cpu_mondo_cmp[`TLU_THRD_NUM-1:0]),
.tlu_dev_mondo_cmp (tlu_dev_mondo_cmp[`TLU_THRD_NUM-1:0]),
.tlu_resum_err_cmp (tlu_resum_err_cmp[`TLU_THRD_NUM-1:0]),
.tlu_hintp (tlu_hintp),
.pich_wrap_flg (pich_wrap_flg[`TLU_THRD_NUM-1:0]),
.pich_onebelow_flg (pich_onebelow_flg[`TLU_THRD_NUM-1:0]),
.pich_twobelow_flg (pich_twobelow_flg[`TLU_THRD_NUM-1:0]),
// modified for bug 5436: Niagara 2.0
.tlu_pcr_ut (tlu_pcr_ut[`TLU_THRD_NUM-1:0]),
.tlu_pcr_st (tlu_pcr_st[`TLU_THRD_NUM-1:0]),
// .tlu_pcr_ut_e (tlu_pcr_ut_e),
// .tlu_pcr_st_e (tlu_pcr_st_e),
.tlu_pic_cnt_en_m (tlu_pic_cnt_en_m),
.tlu_pic_wrap_e (tlu_pic_wrap_e),
// .pich_threebelow_flg (pich_threebelow_flg[`TLU_THRD_NUM-1:0]),
.pib_picl_wrap (pib_picl_wrap[`TLU_THRD_NUM-1:0]),
.tlu_local_flush_w (tlu_local_flush_w),
.tlu_restore_pc_sel_w1 (tlu_restore_pc_sel_w1),
.tlu_final_offset_w1 (tlu_final_offset_w1[`TSA_TTYPE_WIDTH-1:0]),
// Outputs
.pib_pich_wrap (pib_pich_wrap[`TLU_THRD_NUM-1:0]),
.tlu_ibrkpt_trap_w2 (tlu_ibrkpt_trap_w2),
.tlu_early_flush_pipe_w (tlu_early_flush_pipe_w),
.tlu_early_flush_pipe2_w (tlu_early_flush_pipe2_w),
.tlu_exu_early_flush_pipe_w (tlu_exu_early_flush_pipe_w),
.tlu_ifu_trappc_vld_w1 (tlu_ifu_trappc_vld_w1),
.tlu_ifu_trapnpc_vld_w1 (tlu_ifu_trapnpc_vld_w1),
.tlu_ifu_trap_tid_w1 (tlu_ifu_trap_tid_w1[1:0]),
.tlu_trap_hpstate_enb (tlu_trap_hpstate_enb),
.tlu_exu_priv_trap_m (tlu_exu_priv_trap_m),
.tlu_lsu_priv_trap_m (tlu_lsu_priv_trap_m),
// .tlu_lsu_priv_trap_w (tlu_lsu_priv_trap_w),
// .tlu_exu_pic_onebelow_m (tlu_exu_pic_onebelow_m),
// .tlu_exu_pic_twobelow_m (tlu_exu_pic_twobelow_m),
.tsa_wr_tpl (tsa_wr_tpl[2:0]),
.tsa_rd_tid (tsa_rd_tid[1:0]),
.tsa_rd_tpl (tsa_rd_tpl[2:0]),
.tsa_wr_tid (tsa_wr_tid[1:0]),
.tsa_wr_vld (tsa_wr_vld[1:0]),
.tsa_rd_vld_e (tsa_rd_vld_e),
.tsa_rd_en (tsa_rd_en),
.tlu_lsu_tl_zero (tlu_lsu_tl_zero[3:0]),
.tlu_full_flush_pipe_w2 (tlu_full_flush_pipe_w2),
.tlu_exu_agp_tid (tlu_exu_agp_tid[1:0]),
.tlu_agp_tid_w2 (tlu_agp_tid_w2[1:0]),
.tlu_tcc_inst_w (tlu_tcc_inst_w),
.tsa_pc_en (tsa_pc_en),
.tsa_npc_en (tsa_npc_en),
.tsa_tstate_en (tsa_tstate_en),
.tsa_ttype_en (tsa_ttype_en),
.tsa_htstate_en (tsa_htstate_en),
.tlu_tl_gt_0_w2 (tlu_tl_gt_0_w2),
// .tlu_retry_inst_m (tlu_retry_inst_m),
// .tlu_done_inst_m (tlu_done_inst_m),
// .tlu_dnrtry_inst_m_l (tlu_dnrtry_inst_m_l),
.tlu_true_pc_sel_w (tlu_true_pc_sel_w[2:0]),
.tlu_tick_en_l (tlu_tick_en_l),
.tlu_tickcmp_en_l (tlu_tickcmp_en_l[`TLU_THRD_NUM-1:0]),
.tlu_tba_en_l (tlu_tba_en_l[`TLU_THRD_NUM-1:0]),
.tlu_thrd_wsel_w2 (tlu_thrd_wsel_w2[`TLU_THRD_NUM-1:0]),
.tlu_thread_wsel_g (tlu_thread_wsel_g[`TLU_THRD_NUM-1:0]),
.tlu_final_ttype_w2 (tlu_final_ttype_w2[`TSA_TTYPE_WIDTH-1:0]),
.tlu_thread_inst_vld_g (tlu_thread_inst_vld_g[`TLU_THRD_NUM-1:0]),
// .tlu_thread_inst_vld_w2 (tlu_thread_inst_vld_w2[`TLU_THRD_NUM-1:0]),
.tlu_update_pc_l_w (tlu_update_pc_l_w[`TLU_THRD_NUM-1:0]),
.tlu_select_redmode (tlu_select_redmode),
.tlu_pstate_din_sel0 (tlu_pstate_din_sel0[1:0]),
.tlu_pstate_din_sel1 (tlu_pstate_din_sel1[1:0]),
.tlu_pstate_din_sel2 (tlu_pstate_din_sel2[1:0]),
.tlu_pstate_din_sel3 (tlu_pstate_din_sel3[1:0]),
.tlu_update_pstate_l_w2 (tlu_update_pstate_l_w2[3:0]),
.tlu_trp_lvl (tlu_trp_lvl[2:0]),
.tlu_pil (tlu_pil[3:0]),
.tlu_wsr_inst_nq_g (tlu_wsr_inst_nq_g),
.tlu_wr_tsa_inst_w2 (tlu_wr_tsa_inst_w2),
.tlu_exu_cwp_retry_m (tlu_exu_cwp_retry_m),
.tlu_exu_cwpccr_update_m (tlu_exu_cwpccr_update_m),
.tlu_lsu_asi_update_m (tlu_lsu_asi_update_m),
.tlu_lsu_tid_m (tlu_lsu_tid_m[1:0]),
.tlu_select_tba_w2 (tlu_select_tba_w2),
.tdp_select_tba_w2 (tdp_select_tba_w2),
.tlu_set_sftint_l_g (tlu_set_sftint_l_g),
.tlu_clr_sftint_l_g (tlu_clr_sftint_l_g),
.tlu_wr_sftint_l_g (tlu_wr_sftint_l_g),
.tlu_sftint_en_l_g (tlu_sftint_en_l_g[`TLU_THRD_NUM-1:0]),
.tlu_sftint_mx_sel (tlu_sftint_mx_sel[`TLU_THRD_NUM-1:0]),
.tlu_sftint_penc_sel (tlu_sftint_penc_sel[`TLU_THRD_NUM-1:0]),
.tlu_sftint_vld (tlu_sftint_vld[`TLU_THRD_NUM-1:0]),
.tlu_hintp_vld (tlu_hintp_vld[`TLU_THRD_NUM-1:0]),
.tlu_rerr_vld (tlu_rerr_vld[`TLU_THRD_NUM-1:0]),
.tlu_int_tid_m (tlu_int_tid_m[1:0]),
.tlu_incr_tick (tlu_incr_tick[1:0]),
.tlu_tckctr_in (tlu_tckctr_in[1:0]),
.tlu_tickcmp_sel (tlu_tickcmp_sel[`TLU_THRD_NUM-1:0]),
.immu_sfsr_trp_wr (immu_sfsr_trp_wr[3:0]),
.tlu_isfsr_din_g (tlu_isfsr_din_g[23:0]),
.tlu_tick_npt (tlu_tick_npt),
.tlu_thrd_rsel_e (tlu_thrd_rsel_e[3:0]),
.tlu_inst_vld_nq_m (tlu_inst_vld_nq_m),
.tlu_lsu_pstate_am (tlu_lsu_pstate_am[3:0]),
.tlu_hyperv_rdpr_sel (tlu_hyperv_rdpr_sel[4:0]),
.tlu_rdpr_mx1_sel (tlu_rdpr_mx1_sel[2:0]),
.tlu_rdpr_mx2_sel (tlu_rdpr_mx2_sel[2:0]),
.tlu_rdpr_mx3_sel (tlu_rdpr_mx3_sel[1:0]),
.tlu_rdpr_mx4_sel (tlu_rdpr_mx4_sel[1:0]),
.tlu_rdpr_mx5_sel (tlu_rdpr_mx5_sel[2:0]),
.tlu_rdpr_mx6_sel (tlu_rdpr_mx6_sel[2:0]),
.tlu_rdpr_mx7_sel (tlu_rdpr_mx7_sel[3:0]),
.tlu_lsu_redmode_rst_d1 (tlu_lsu_redmode_rst_d1[3:0]),
.lsu_tlu_rsr_data_mod_e (lsu_tlu_rsr_data_mod_e[7:0]),
.tlu_addr_msk_g (tlu_addr_msk_g),
.tlu_stickcmp_en_l (tlu_stickcmp_en_l[`TLU_THRD_NUM-1:0]),
.tlu_htickcmp_en_l (tlu_htickcmp_en_l[`TLU_THRD_NUM-1:0]),
.tlu_htstate_rw_d (tlu_htstate_rw_d),
.tlu_htstate_rw_g (tlu_htstate_rw_g),
.tlu_dnrtry0_inst_g (tlu_dnrtry0_inst_g),
.tlu_dnrtry1_inst_g (tlu_dnrtry1_inst_g),
.tlu_dnrtry2_inst_g (tlu_dnrtry2_inst_g),
.tlu_dnrtry3_inst_g (tlu_dnrtry3_inst_g),
.tlu_thrd_traps_w2 (tlu_thrd_traps_w2[`TLU_THRD_NUM-1:0]),
.tlu_tick_ctl_din (tlu_tick_ctl_din),
.tlu_por_rstint_g (tlu_por_rstint_g[`TLU_THRD_NUM-1:0]),
.tlu_pc_mxsel_w2 (tlu_pc_mxsel_w2),
.ifu_npc_w (ifu_npc_w[48:0]),
.tlu_rst (tlu_rst),
// .tlu_rst_l (tlu_rst_l),
.tlu_sscan_tcl_data (tlu_sscan_test_data[`TCL_SSCAN_HI:`TCL_SSCAN_LO]),
// Inputs
.ifu_tlu_npc_m (ifu_tlu_npc_m[48:0]),
.ifu_tlu_pc_oor_e (ifu_tlu_pc_oor_e),
.lsu_tlu_early_flush_w (lsu_tlu_early_flush_w),
.ifu_tlu_flush_fd_w (ifu_tlu_flush_fd2_w),
.ifu_tlu_sraddr_d (ifu_tlu_sraddr_d[`TLU_ASR_ADDR_WIDTH-1:0]),
.ifu_tlu_rsr_inst_d (ifu_tlu_rsr_inst_d),
.lsu_tlu_wsr_inst_e (lsu_tlu_wsr_inst_e),
.tlu_wsr_data_w (tlu_wsr_data_w[3:0]),
.lsu_tlu_ttype_m2 (lsu_tlu_ttype_m2[8:0]),
.lsu_tlu_ttype_vld_m2 (lsu_tlu_ttype_vld_m2),
.ifu_tlu_done_inst_d (ifu_tlu_done_inst_d),
.ifu_tlu_retry_inst_d (ifu_tlu_retry_inst_d),
.ifu_tlu_ttype_m (ifu_tlu_ttype_m[8:0]),
.ifu_tlu_ttype_vld_m (ifu_tlu_ttype_vld_m),
.ifu_tlu_trap_m (ifu_tlu_trap_m),
.exu_tlu_ttype_m (exu_tlu_ttype_m[8:0]),
.exu_tlu_ttype_vld_m (exu_tlu_ttype_vld_m),
.exu_tlu_ue_trap_m (exu_tlu_ue_trap_m),
.exu_tlu_spill (exu_tlu_spill),
.exu_tlu_spill_tid (exu_tlu_spill_tid[1:0]),
.exu_tlu_spill_other (exu_tlu_spill_other),
.exu_tlu_spill_wtype (exu_tlu_spill_wtype),
.exu_tlu_va_oor_m (exu_tlu_va_oor_m),
.exu_tlu_va_oor_jl_ret_m (exu_tlu_va_oor_jl_ret_m),
.tlu_cwp_no_change_m (tlu_cwp_no_change_m),
.tlu_trap_cwp_en (tlu_trap_cwp_en[`TLU_THRD_NUM-1:0]),
.ifu_tlu_sir_inst_m (ifu_tlu_sir_inst_m),
.ifu_tlu_inst_vld_m (ifu_tlu_inst_vld_m),
.ifu_tlu_thrid_d (ifu_tlu_thrid_d[1:0]),
.lsu_tlu_async_ttype_vld_g (lsu_tlu_async_ttype_vld_g),
.lsu_tlu_defr_trp_taken_g (lsu_tlu_defr_trp_taken_g),
.lsu_tlu_async_ttype_g (lsu_tlu_async_ttype_g),
.lsu_tlu_async_tid_g (lsu_tlu_async_tid_g[1:0]),
.ifu_tlu_immu_miss_m (ifu_tlu_immu_miss_m),
.exu_tlu_cwp_cmplt (exu_tlu_cwp_cmplt),
.exu_tlu_cwp_retry (exu_tlu_cwp_retry),
.exu_tlu_cwp_cmplt_tid (exu_tlu_cwp_cmplt_tid[1:0]),
.ifu_tlu_rstint_m (ifu_tlu_rstint_m),
.ifu_tlu_hwint_m (ifu_tlu_hwint_m),
.ifu_tlu_swint_m (ifu_tlu_swint_m),
.int_tlu_rstid_m (int_tlu_rstid_m[5:0]),
.tlu_int_pstate_ie (local_pstate_ie[3:0]),
.tlu_int_redmode (tlu_int_redmode[3:0]),
.tlu_sftint_id (tlu_sftint_id[3:0]),
.lsu_tlu_misalign_addr_ldst_atm_m(lsu_tlu_misalign_addr_ldst_atm_m),
.exu_tlu_misalign_addr_jmpl_rtn_m(exu_tlu_misalign_addr_jmpl_rtn_m),
.lsu_tlu_priv_action_g (lsu_tlu_priv_action_g),
.lsu_tlu_wtchpt_trp_g (lsu_tlu_wtchpt_trp_g),
.ifu_tlu_priv_violtn_m (ifu_tlu_priv_violtn_m),
.ifu_lsu_memref_d (ifu_lsu_memref_d),
.tlu_pstate_priv (local_pstate_priv[`TLU_THRD_NUM-1:0]),
.tlu_pstate_am (tlu_pstate_am[3:0]),
.tlu_isfsr_flt_vld (tlu_isfsr_flt_vld[3:0]),
.ffu_tlu_trap_ieee754 (ffu_tlu_trap_ieee754),
.ffu_tlu_trap_other (ffu_tlu_trap_other),
.ffu_tlu_trap_ue (ffu_tlu_trap_ue),
.ffu_ifu_tid_w2 (ffu_ifu_tid_w2[1:0]),
.ffu_tlu_ill_inst_m (ffu_tlu_ill_inst_m), // new trap from ffu
.lsu_tlu_rsr_data_e (lsu_tlu_rsr_data_e[7:0]),
.lsu_tlu_squash_va_oor_m (lsu_tlu_squash_va_oor_m),
.tlu_hpstate_priv (tcl_hpstate_priv[`TLU_THRD_NUM-1:0]),
.tlu_hscpd_dacc_excpt_m(tlu_hscpd_dacc_excpt_m),
.tlu_qtail_dacc_excpt_m(tlu_qtail_dacc_excpt_m),
.tlu_htickcmp_rw_e (tlu_htickcmp_rw_e),
// .tlu_gl_rw_g (tlu_gl_rw_g),
.tlu_gl_rw_m (tlu_gl_rw_m),
.tlu_hpstate_enb (tcl_hpstate_enb[`TLU_THRD_NUM-1:0]),
.tlu_hpstate_tlz (tlu_hpstate_tlz[`TLU_THRD_NUM-1:0]),
.ctu_sscan_tid (ctu_sscan_tid[`TLU_THRD_NUM-1:0]),
.se (se),
.rclk (rclk),
.grst_l (grst_l),
.arst_l (arst_l),
.rst_tri_en (mux_drive_disable));
tlu_tdp tdp (
.so (scan1_2),
.si (scan1_1),
.tsa_rdata ({tsa1_dout[`TSA1_HTSTATE_HI:`TSA1_HTSTATE_LO],
// tsa0_dout[`TSA0_TPC_HI:`TSA0_TPC_LO],
// tsa1_dout[`TSA1_TNPC_HI:`TSA1_TNPC_LO],
tsa0_dout[`TSA0_TPC_HI-1:`TSA0_TPC_LO],
tsa1_dout[`TSA1_TNPC_HI-1:`TSA1_TNPC_LO],
tsa0_dout[`TSA0_TSTATE_HI:`TSA0_TSTATE_LO],
tsa1_dout[`TSA1_TTYPE_HI:`TSA1_TTYPE_LO]}),
.lsu_tlu_rsr_data_e (lsu_tlu_rsr_data_mod_e[7:0]),
.ifu_lsu_imm_asi_d (ifu_lsu_imm_asi_d[7:0]),
.ifu_lsu_imm_asi_vld_d (ifu_lsu_imm_asi_vld_d),
.tlu_lsu_redmode (tlu_lsu_redmode[3:0]),
.tlu_exu_rsr_data_m (tlu_exu_rsr_data_m[`TLU_ASR_DATA_WIDTH-1:0]),
/*AUTOINST*/
// Outputs
// modified for bug 3017
.tlu_restore_pc_w1 (tlu_restore_pc_w1[48:0]),
.tlu_restore_npc_w1 (tlu_restore_npc_w1[48:0]),
.tlu_partial_trap_pc_w1 (tlu_partial_trap_pc_w1[33:0]),
.tlu_pib_rsr_data_e (tlu_pib_rsr_data_e[63:0]),
.tlu_asi_state_e (tlu_asi_state_e[`TLU_ASI_STATE_WIDTH-1:0]),
.tsa_wdata (tsa_wdata[`TLU_TSA_WIDTH-1:0]),
.tlu_int_pstate_ie (tlu_int_pstate_ie[3:0]),
.local_pstate_ie (local_pstate_ie[3:0]),
.tlu_ifu_pstate_pef (tlu_ifu_pstate_pef[3:0]),
.tlu_lsu_pstate_cle (tlu_lsu_pstate_cle[3:0]),
.tlu_lsu_pstate_priv (tlu_lsu_pstate_priv[3:0]),
.tlu_int_redmode (tlu_int_redmode[3:0]),
.local_pstate_priv (local_pstate_priv[`TLU_THRD_NUM-1:0]),
.tlu_pstate_am (tlu_pstate_am[3:0]),
.tlu_sftint_id (tlu_sftint_id[3:0]),
.tlu_tick_incr_din (tlu_tick_incr_din[61:0]),
.tlu_sscan_test_data (tlu_sscan_test_data[`TDP_SSCAN_WIDTH-1:0]),
.tlu_dnrtry_global_g (tlu_dnrtry_global_g[`TSA_GLOBAL_WIDTH-1:0]),
.tlu_hpstate_enb (tlu_hpstate_enb[`TLU_THRD_NUM-1:0]),
.local_hpstate_enb (local_hpstate_enb[`TLU_THRD_NUM-1:0]),
.tcl_hpstate_enb (tcl_hpstate_enb[`TLU_THRD_NUM-1:0]),
.tlu_hpstate_tlz (tlu_hpstate_tlz[`TLU_THRD_NUM-1:0]),
.tlu_hpstate_priv (tlu_hpstate_priv[`TLU_THRD_NUM-1:0]),
.local_hpstate_priv (local_hpstate_priv[`TLU_THRD_NUM-1:0]),
.tcl_hpstate_priv (tcl_hpstate_priv[`TLU_THRD_NUM-1:0]),
.tlu_hpstate_ibe (tlu_hpstate_ibe[`TLU_THRD_NUM-1:0]),
.tlu_hintp (tlu_hintp),
// Inputs
.tlu_ibrkpt_trap_w2 (tlu_ibrkpt_trap_w2),
.pib_picl_wrap (pib_picl_wrap[`TLU_THRD_NUM-1:0]),
.pib_pich_wrap (pib_pich_wrap[`TLU_THRD_NUM-1:0]),
.tlu_por_rstint_g (tlu_por_rstint_g[`TLU_THRD_NUM-1:0]),
.rclk (rclk),
.tlu_rst (tlu_rst),
.tlu_trap_hpstate_enb (tlu_trap_hpstate_enb),
.tlu_thrd_wsel_w2 (tlu_thrd_wsel_w2[`TLU_THRD_NUM-1:0]),
.tlu_final_ttype_w2 (tlu_final_ttype_w2[`TSA_TTYPE_WIDTH-1:0]),
.tlu_pstate_din_sel0 (tlu_pstate_din_sel0[1:0]),
.tlu_pstate_din_sel1 (tlu_pstate_din_sel1[1:0]),
.tlu_pstate_din_sel2 (tlu_pstate_din_sel2[1:0]),
.tlu_pstate_din_sel3 (tlu_pstate_din_sel3[1:0]),
.tlu_wr_tsa_inst_w2 (tlu_wr_tsa_inst_w2),
.lsu_asi_reg0 (lsu_asi_reg0[7:0]),
.lsu_asi_reg1 (lsu_asi_reg1[7:0]),
.lsu_asi_reg2 (lsu_asi_reg2[7:0]),
.lsu_asi_reg3 (lsu_asi_reg3[7:0]),
.tlu_tickcmp_sel (tlu_tickcmp_sel[`TLU_THRD_NUM-1:0]),
.exu_tlu_ccr0_w (exu_tlu_ccr0_w[7:0]),
.exu_tlu_ccr1_w (exu_tlu_ccr1_w[7:0]),
.exu_tlu_ccr2_w (exu_tlu_ccr2_w[7:0]),
.exu_tlu_ccr3_w (exu_tlu_ccr3_w[7:0]),
.exu_tlu_cwp0 (exu_tlu_cwp0[2:0]),
.exu_tlu_cwp1 (exu_tlu_cwp1[2:0]),
.exu_tlu_cwp2 (exu_tlu_cwp2[2:0]),
.exu_tlu_cwp3 (exu_tlu_cwp3[2:0]),
.tlu_trap_cwp_en (tlu_trap_cwp_en[`TLU_THRD_NUM-1:0]),
// modified for bug 3017
// .ifu_tlu_pc_m (ifu_tlu_pc_m[48:0]),
// .ifu_tlu_npc_m (ifu_tlu_npc_m[48:0]),
.tlu_pc_new_w (tlu_pc_new_w[48:0]),
.tlu_npc_new_w (tlu_npc_new_w[48:0]),
.tlu_sftint_en_l_g (tlu_sftint_en_l_g[`TLU_THRD_NUM-1:0]),
.tlu_sftint_mx_sel (tlu_sftint_mx_sel[`TLU_THRD_NUM-1:0]),
.tlu_set_sftint_l_g (tlu_set_sftint_l_g),
.tlu_clr_sftint_l_g (tlu_clr_sftint_l_g),
.tlu_wr_sftint_l_g (tlu_wr_sftint_l_g),
.tlu_sftint_penc_sel (tlu_sftint_penc_sel[3:0]),
.tlu_tba_en_l (tlu_tba_en_l[3:0]),
.tlu_tick_en_l (tlu_tick_en_l),
.tlu_tickcmp_en_l (tlu_tickcmp_en_l[3:0]),
// .tlu_done_inst_m (tlu_done_inst_m),
// .tlu_dnrtry_inst_m (tlu_dnrtry_inst_m),
// .tlu_dnrtry_inst_m_l (tlu_dnrtry_inst_m_l),
.tlu_update_pc_l_w (tlu_update_pc_l_w[3:0]),
.tlu_tl_gt_0_w2 (tlu_tl_gt_0_w2),
.tlu_select_tba_w2 (tdp_select_tba_w2),
.tlu_select_redmode (tlu_select_redmode),
.tlu_update_pstate_l_w2 (tlu_update_pstate_l_w2[3:0]),
.tlu_pil (tlu_pil[3:0]),
.tlu_trp_lvl (tlu_trp_lvl[2:0]),
.tlu_tick_npt (tlu_tick_npt),
.tlu_thrd_rsel_e (tlu_thrd_rsel_e[3:0]),
.tlu_tick_incr_dout (tlu_incr64_dout[60:0]),
.tlu_rdpr_mx1_sel (tlu_rdpr_mx1_sel[2:0]),
.tlu_rdpr_mx2_sel (tlu_rdpr_mx2_sel[2:0]),
.tlu_rdpr_mx3_sel (tlu_rdpr_mx3_sel[1:0]),
.tlu_rdpr_mx4_sel (tlu_rdpr_mx4_sel[1:0]),
.tlu_rdpr_mx5_sel (tlu_rdpr_mx5_sel[2:0]),
.tlu_rdpr_mx6_sel (tlu_rdpr_mx6_sel[2:0]),
.tlu_rdpr_mx7_sel (tlu_rdpr_mx7_sel[3:0]),
.ctu_sscan_tid (ctu_sscan_tid[`TLU_THRD_NUM-1:0]),
.tlu_gl_lvl0 (tlu_gl_lvl0[`TSA_GLOBAL_WIDTH-1:0]),
.tlu_gl_lvl1 (tlu_gl_lvl1[`TSA_GLOBAL_WIDTH-1:0]),
.tlu_gl_lvl2 (tlu_gl_lvl2[`TSA_GLOBAL_WIDTH-1:0]),
.tlu_gl_lvl3 (tlu_gl_lvl3[`TSA_GLOBAL_WIDTH-1:0]),
.tlu_hpstate_din_sel0 (tlu_hpstate_din_sel0[1:0]),
.tlu_hpstate_din_sel1 (tlu_hpstate_din_sel1[1:0]),
.tlu_hpstate_din_sel2 (tlu_hpstate_din_sel2[1:0]),
.tlu_hpstate_din_sel3 (tlu_hpstate_din_sel3[1:0]),
.tlu_htba_en_l (tlu_htba_en_l[`TLU_THRD_NUM-1:0]),
.tlu_htickcmp_en_l (tlu_htickcmp_en_l[`TLU_THRD_NUM-1:0]),
.tlu_htickcmp_intdis (tlu_htickcmp_intdis),
.tlu_pc_mxsel_w2 (tlu_pc_mxsel_w2),
.tlu_set_hintp_sel_g (tlu_set_hintp_sel_g[`TLU_THRD_NUM-1:0]),
.tlu_stickcmp_en_l (tlu_stickcmp_en_l[`TLU_THRD_NUM-1:0]),
.tlu_update_hpstate_l_w2 (tlu_update_hpstate_l_w2[`TLU_THRD_NUM-1:0]),
.tlu_wr_hintp_g (tlu_wr_hintp_g[`TLU_THRD_NUM-1:0]),
.tlu_wsr_data_w (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-1:0]),
.se (se));
// modified for Niagara SRAMs methodology
bw_r_rf32x80 tsa0 (
// Outputs
.dout (tsa0_dout[`TSA_MEM_WIDTH-1:0]),
.so (short_scan0_1),
// Inputs
.wr_adr ({tsa_wr_tid[1:0],tsa_wr_tpl[2:0]}),
.wr_en (tsa_wr_vld[0]),
.nib_wr_en ({{12{tsa_pc_en}},
{ 8{tsa_tstate_en}}}),
.rd_adr ({tsa_rd_tid[1:0],tsa_rd_tpl[2:0]}),
.rd_en (tsa_rd_en),
.din ({1'b0, tsa_wdata[`TLU_PC_HI:`TLU_PC_LO],
3'b0, tsa_wdata[`TLU_GL_HI:`TLU_CWP_LO]}),
.reset_l (arst_l),
.rst_tri_en (mem_write_disable),
.sehold (sehold),
.se (se),
.si (short_si0),
.rclk (rclk));
bw_r_rf32x80 tsa1 (
// Outputs
.dout (tsa1_dout[`TSA_MEM_WIDTH-1:0]),
.so (short_scan0_2),
// Inputs
.wr_adr ({tsa_wr_tid[1:0],tsa_wr_tpl[2:0]}),
.wr_en (tsa_wr_vld[1]),
.nib_wr_en ({ 4'h0, // unused
{ 1{tsa_htstate_en}},
{12{tsa_npc_en}},
{ 3{tsa_ttype_en}}}),
.rd_adr ({tsa_rd_tid[1:0],tsa_rd_tpl[2:0]}),
.rd_en (tsa_rd_en),
.din ({16'h0000, // unused bits
tsa_wdata[`TLU_HTSTATE_HI:`TLU_HTSTATE_LO],
1'b0, tsa_wdata[`TLU_NPC_HI:`TLU_NPC_LO],
3'b0, tsa_wdata[`TLU_TT_HI:`TLU_TT_LO]}),
.reset_l (arst_l),
.rst_tri_en (mem_write_disable),
.sehold (sehold),
.se (se),
.si (short_scan0_1),
.rclk (rclk));
// replaced with softmacro from the library
tlu_incr64 tick_incr64 (
.out ({tlu_incr64_dout[61:0], tlu_tckctr_in[1:0]}),
.in ({tlu_tick_incr_din[61:0], tlu_incr_tick[1:0]})
);
/*
zzinc64 tick_incr64 (
.out ({tlu_incr64_dout[61:0], tlu_tckctr_in[1:0]}),
.in ({tlu_tick_incr_din[61:0], tlu_incr_tick[1:0]})
);
*/
tlu_mmu_ctl mmu_ctl (
.so (so0),
.si(scan0_1),
.lsu_tlu_st_rs3_data_b12t0_g(lsu_tlu_st_rs3_data_g[12:0]),
.lsu_tlu_st_rs3_data_b48_g(lsu_tlu_st_rs3_data_g[48]),
//.lsu_tlu_st_rs3_data_b10t8_g(lsu_tlu_st_rs3_data_g[10:8]),
.tlu_sun4r_tte_g (tlu_sun4r_tte_g),
.ifu_tlu_flush_m (ifu_tlu_flush_m),
.tlu_mmu_early_flush_pipe_w (tlu_exu_early_flush_pipe_w),
.lsu_mmu_early_flush_w (lsu_tlu_early_flush_w),
.lsu_mmu_flush_pipe_w (lsu_mmu_flush_pipe_w),
.dmmu_sfsr_trp_wr (lsu_dmmu_sfsr_trp_wr[3:0]),
.rst_tri_en (mux_drive_disable),
.ifu_tlu_priv_violtn_m (ifu_tlu_priv_violtn_m),
// MMU_ASI_RD_CHANGE
.lsu_exu_ldxa_m (lsu_exu_ldxa_m),
.ifu_lsu_memref_d (ifu_lsu_memref_d),
.ifu_lsu_imm_asi_d (ifu_lsu_imm_asi_d[8:0]),
.ifu_lsu_thrid_s (ifu_lsu_thrid_s[1:0]),
.lsu_asi_reg0 (lsu_asi_reg0[7:0]),
.lsu_asi_reg1 (lsu_asi_reg1[7:0]),
.lsu_asi_reg2 (lsu_asi_reg2[7:0]),
.lsu_asi_reg3 (lsu_asi_reg3[7:0]),
.tlu_lng_ltncy_en_l(tlu_lng_ltncy_en_l),
.tlu_tsb_rd_ps0_sel (tlu_tsb_rd_ps0_sel),
.tlu_tsb_base_w2_d1 (tlu_tsb_base_w2_d1[47:13]),
.tlu_lsu_pstate_am (tlu_lsu_pstate_am[3:0]),
.exu_tlu_va_oor_m (exu_tlu_va_oor_m),
.exu_tlu_va_oor_jl_ret_m (exu_tlu_va_oor_jl_ret_m),
.tlu_lsu_tl_zero (tlu_lsu_tl_zero[3:0]),
.lsu_mmu_defr_trp_taken_g (lsu_mmu_defr_trp_taken_g),
/*AUTOINST*/
// Outputs
.tlu_tlb_access_en_l_d1 (tlu_tlb_access_en_l_d1),
.mra_byte_wen (mra_byte_wen[19:0]),
.tlu_tag_access_ctxt_sel_m (tlu_tag_access_ctxt_sel_m[2:0]),
.tlu_tlb_tag_invrt_parity(tlu_tlb_tag_invrt_parity),
.tlu_tlb_data_invrt_parity(tlu_tlb_data_invrt_parity),
.lsu_ifu_inj_ack (lsu_ifu_inj_ack[3:0]),
.dmmu_any_sfsr_wr (dmmu_any_sfsr_wr),
.dmmu_sfsr_wr_en_l (dmmu_sfsr_wr_en_l[3:0]),
.dmmu_sfar_wr_en_l (dmmu_sfar_wr_en_l[3:0]),
.immu_any_sfsr_wr (immu_any_sfsr_wr),
.immu_sfsr_wr_en_l (immu_sfsr_wr_en_l[3:0]),
.tlu_tte_tag_g (tlu_tte_tag_g[2:0]),
.tlu_dtlb_rw_index_vld_g(tlu_dtlb_rw_index_vld_g),
.tlu_dtlb_rw_index_g(tlu_dtlb_rw_index_g[5:0]),
.tlu_dtlb_data_rd_g(tlu_dtlb_data_rd_g),
.tlu_dtlb_tag_rd_g (tlu_dtlb_tag_rd_g),
.tlu_itlb_rw_index_vld_g(tlu_itlb_rw_index_vld_g),
.tlu_itlb_wr_vld_g (tlu_itlb_wr_vld_g),
.itlb_wr_vld_g (itlb_wr_vld_g),
.tlu_itlb_rw_index_g(tlu_itlb_rw_index_g[5:0]),
.tlu_itlb_data_rd_g(tlu_itlb_data_rd_g),
.tlu_itlb_tag_rd_g (tlu_itlb_tag_rd_g),
.tlu_idtsb_8k_ptr (tlu_idtsb_8k_ptr[47:0]),
.tlu_dtlb_invalidate_all_g(tlu_dtlb_invalidate_all_g),
.tlu_itlb_invalidate_all_g(tlu_itlb_invalidate_all_g),
.tlu_slxa_thrd_sel (tlu_slxa_thrd_sel[3:0]),
.tlu_lsu_ldxa_tid_w2(tlu_lsu_ldxa_tid_w2[1:0]),
.tlu_itlb_dmp_vld_g(tlu_itlb_dmp_vld_g),
.tlu_itlb_dmp_all_g(tlu_itlb_dmp_all_g),
.tlu_itlb_dmp_actxt_g(tlu_itlb_dmp_actxt_g),
.tlu_itlb_dmp_nctxt_g(tlu_itlb_dmp_nctxt_g),
.tlu_dtlb_dmp_vld_g(tlu_dtlb_dmp_vld_g),
//.tlu_dtlb_dmp_by_ctxt_g(tlu_dtlb_dmp_by_ctxt_g),
.tlu_dtlb_dmp_all_g(tlu_dtlb_dmp_all_g),
.tlu_dtlb_dmp_pctxt_g(tlu_dtlb_dmp_pctxt_g),
.tlu_dtlb_dmp_sctxt_g(tlu_dtlb_dmp_sctxt_g),
.tlu_dtlb_dmp_nctxt_g(tlu_dtlb_dmp_nctxt_g),
.tlu_dtlb_dmp_actxt_g(tlu_dtlb_dmp_actxt_g),
.tlu_idtlb_dmp_thrid_g(tlu_idtlb_dmp_thrid_g[1:0]),
.tlu_dmp_key_vld_g (tlu_dmp_key_vld_g[4:0]),
.tlu_int_asi_load (tlu_int_asi_load),
// .tlu_int_asi_store (tlu_int_asi_store),
.tlu_int_asi_thrid (tlu_int_asi_thrid[1:0]),
.tlu_int_asi_vld (tlu_int_asi_vld),
.tlb_access_rst_l (tlb_access_rst_l),
.tlu_lsu_stxa_ack (tlu_lsu_stxa_ack),
.tlu_lsu_stxa_ack_tid(tlu_lsu_stxa_ack_tid[1:0]),
.mra_wr_ptr (mra_wr_ptr[3:0]),
.mra_rd_ptr (mra_rd_ptr[3:0]),
.mra_wr_vld (mra_wr_vld),
.mra_rd_vld (mra_rd_vld),
.tag_access_wdata_sel(tag_access_wdata_sel[2:0]),
.tlu_admp_key_sel (tlu_admp_key_sel),
// .tlu_mmu_sync_data_excp_g(tlu_mmu_sync_data_excp_g),
.tlu_tte_wr_pid_g (tlu_tte_wr_pid_g[2:0]),
.tlu_lsu_ldxa_async_data_vld(tlu_lsu_ldxa_async_data_vld),
.tlu_tte_real_g (tlu_tte_real_g),
.tlu_ldxa_l1mx1_sel(tlu_ldxa_l1mx1_sel[3:0]),
.tlu_ldxa_l1mx2_sel(tlu_ldxa_l1mx2_sel[3:0]),
.tlu_ldxa_l2mx1_sel(tlu_ldxa_l2mx1_sel[2:0]),
// Inputs
.tlu_itag_acc_sel_g (tlu_itag_acc_sel_g),
.sehold (sehold),
.spu_tlu_rsrv_illgl_m (1'b0),
.ifu_mmu_trap_m (ifu_mmu_trap_m),
.ffu_tlu_ill_inst_m(ffu_tlu_ill_inst_m),
.ifu_tlu_inst_vld_m (ifu_tlu_inst_vld_m_bf1),
.exu_lsu_priority_trap_m(exu_lsu_priority_trap_m),
.exu_mmu_early_va_e (exu_mmu_early_va_e[7:0]),
.tlu_tag_access_ctxt_g (tlu_tag_access_ctxt_g[12:0]),
.ifu_lsu_error_inj (ifu_lsu_error_inj[3:0]),
.lsu_tlu_nucleus_ctxt_m (lsu_tlu_nucleus_ctxt_m),
.lsu_tlu_tte_pg_sz_g (lsu_tlu_tte_pg_sz_g[2:0]),
.ifu_lsu_ld_inst_e (ifu_lsu_ld_inst_e),
.ifu_lsu_st_inst_e (ifu_lsu_st_inst_e),
.lsu_tlu_dmmu_miss_g(lsu_tlu_dmmu_miss_g),
.tlu_dtsb_split_w2 (tlu_dtsb_split_w2),
.tlu_dtsb_size_w2 (tlu_dtsb_size_w2[3:0]),
.tlu_dtag_access_w2(tlu_dtag_access_w2[47:13]),
.tlu_itsb_split_w2 (tlu_itsb_split_w2),
.tlu_itsb_size_w2 (tlu_itsb_size_w2[3:0]),
.tlu_ctxt_cfg_w2 (tlu_ctxt_cfg_w2[5:0]),
//.tlu_tag_access_nctxt_g(tlu_tag_access_nctxt_g),
.lsu_tlu_st_rs3_data_g(lsu_tlu_st_rs3_data_g[62:61]),
.ifu_tlu_immu_miss_m(ifu_tlu_immu_miss_m),
// .ifu_tlu_thrid_e (ifu_tlu_thrid_e[1:0]),
.ifu_lsu_alt_space_e(ifu_lsu_alt_space_e),
.ifu_tlu_alt_space_d(ifu_tlu_alt_space_d),
.lsu_tlu_dtlb_done (lsu_tlu_dtlb_done),
.ifu_tlu_itlb_done (ifu_tlu_itlb_done),
.lsu_tlu_tlb_asi_state_m(lsu_tlu_tlb_asi_state_m[7:0]),
.lsu_tlu_tlb_ldst_va_m(lsu_tlu_tlb_ldst_va_m[10:0]),
.lsu_tlu_tlb_ld_inst_m(lsu_tlu_tlb_ld_inst_m),
.lsu_tlu_tlb_st_inst_m(lsu_tlu_tlb_st_inst_m),
.lsu_tlu_tlb_access_tid_m(lsu_tlu_tlb_access_tid_m[1:0]),
.immu_sfsr_trp_wr (immu_sfsr_trp_wr[3:0]),
.lsu_tlu_daccess_excptn_g(lsu_tlu_daccess_excptn_g),
.lsu_tlu_daccess_prot_g(lsu_tlu_daccess_prot_g),
.lsu_pid_state0 (lsu_pid_state0[2:0]),
.lsu_pid_state1 (lsu_pid_state1[2:0]),
.lsu_pid_state2 (lsu_pid_state2[2:0]),
.lsu_pid_state3 (lsu_pid_state3[2:0]),
.rclk (rclk),
.se (se),
.grst_l (grst_l),
.arst_l (arst_l));
/*
tlu_mmu_dp AUTO_TEMPLATE ();
*/
tlu_mmu_dp mmu_dp (
.so (short_scan0_3),
.si (short_scan0_2),
.ifu_tlu_pc_m (ifu_tlu_pc_m[47:13]),
.lsu_exu_ldxa_data_g (lsu_exu_ldxa_data_g[63:0]),
.tlu_dsfsr_din_g (lsu_dsfsr_din_g[23:0]),
// MMU_ASI_RD_CHANGE
.tlu_lng_ltncy_en_l(tlu_lng_ltncy_en_l),
.tlu_tsb_rd_ps0_sel (tlu_tsb_rd_ps0_sel),
.tlu_tsb_base_w2_d1 (tlu_tsb_base_w2_d1[47:13]),
/*AUTOINST*/
// Outputs
.tlu_tag_access_ctxt_g (tlu_tag_access_ctxt_g[12:0]),
.tlu_ctxt_cfg_w2 (tlu_ctxt_cfg_w2[5:0]),
.tlu_dtsb_split_w2 (tlu_dtsb_split_w2),
.tlu_dtsb_size_w2 (tlu_dtsb_size_w2[3:0]),
.tlu_dtag_access_w2 (tlu_dtag_access_w2[47:13]),
.tlu_itsb_split_w2 (tlu_itsb_split_w2),
.tlu_itsb_size_w2 (tlu_itsb_size_w2[3:0]),
.tlu_itlb_tte_tag_w2 (tlu_itlb_tte_tag_w2[58:0]),
.tlu_itlb_tte_data_w2(tlu_itlb_tte_data_w2[42:0]),
.tlu_dtlb_tte_tag_w2 (tlu_dtlb_tte_tag_w2[58:0]),
.tlu_dtlb_tte_data_w2(tlu_dtlb_tte_data_w2[42:0]),
// .tlu_lsu_ldxa_data_w2(tlu_lsu_ldxa_data_w2[63:0]),
.tlu_idtlb_dmp_key_g (tlu_idtlb_dmp_key_g[40:0]),
.tlu_dsfsr_flt_vld (tlu_dsfsr_flt_vld[3:0]),
.tlu_isfsr_flt_vld (tlu_isfsr_flt_vld[3:0]),
//.tlu_tag_access_nctxt_g(tlu_tag_access_nctxt_g),
.mra_wdata (mra_wdata[155:0]),
// Inputs
.tlu_tlb_access_en_l_d1 (tlu_tlb_access_en_l_d1),
.tlu_sun4r_tte_g (tlu_sun4r_tte_g),
.tlu_tlb_tag_invrt_parity(tlu_tlb_tag_invrt_parity),
.tlu_tlb_data_invrt_parity(tlu_tlb_data_invrt_parity),
.tlu_addr_msk_g (tlu_addr_msk_g),
.dmmu_any_sfsr_wr (dmmu_any_sfsr_wr),
.dmmu_sfsr_wr_en_l (dmmu_sfsr_wr_en_l[3:0]),
.immu_any_sfsr_wr (immu_any_sfsr_wr),
.immu_sfsr_wr_en_l (immu_sfsr_wr_en_l[3:0]),
.lsu_tlu_dside_ctxt_m(lsu_tlu_dside_ctxt_m[12:0]),
.lsu_tlu_pctxt_m (lsu_tlu_pctxt_m[12:0]),
.tlu_tag_access_ctxt_sel_m(tlu_tag_access_ctxt_sel_m[2:0]),
.lsu_tlu_st_rs3_data_b63t59_g(lsu_tlu_st_rs3_data_g[63:59]),
.lsu_tlu_st_rs3_data_b47t0_g(lsu_tlu_st_rs3_data_g[47:0]),
.exu_lsu_ldst_va_e (exu_lsu_ldst_va_e[`ASI_VA_WIDTH-1:0]),
.tlu_idtsb_8k_ptr (tlu_idtsb_8k_ptr[47:0]),
.lsu_tlu_tlb_dmp_va_m(lsu_tlu_tlb_dmp_va_m[47:13]),
.tlu_slxa_thrd_sel (tlu_slxa_thrd_sel[3:0]),
.tlu_tte_tag_g (tlu_tte_tag_g[2:0]),
.tlu_dmp_key_vld_g (tlu_dmp_key_vld_g[4:0]),
.tlb_access_rst_l (tlb_access_rst_l),
.tag_access_wdata_sel(tag_access_wdata_sel[2:0]),
.mra_rdata (mra_rdata[159:10]),
.tlu_admp_key_sel (tlu_admp_key_sel),
.tlu_isfsr_din_g (tlu_isfsr_din_g[23:0]),
.tlu_tte_wr_pid_g (tlu_tte_wr_pid_g[2:0]),
.tlu_tte_real_g (tlu_tte_real_g),
.tlu_ldxa_l1mx1_sel (tlu_ldxa_l1mx1_sel[3:0]),
.tlu_ldxa_l1mx2_sel (tlu_ldxa_l1mx2_sel[3:0]),
.tlu_ldxa_l2mx1_sel (tlu_ldxa_l2mx1_sel[2:0]),
.rclk (rclk),
.arst_l (arst_l),
.grst_l (grst_l),
.se (se),
.dmmu_sfar_wr_en_l (dmmu_sfar_wr_en_l[3:0]));
// .rst_l (tlu_rst_l));
tlu_hyperv tlu_hyperv (/*AUTOINST*/
.so(scan1_3),
.si(scan1_2),
.grst_l (grst_l),
.arst_l (arst_l),
.rst_tri_en (mux_drive_disable),
// output
// modified for timing
// .tlu_gl_rw_g (tlu_gl_rw_g),
.tlu_gl_rw_m (tlu_gl_rw_m),
.tlu_gl_lvl0 (tlu_gl_lvl0[`TSA_GLOBAL_WIDTH-1:0]),
.tlu_gl_lvl1 (tlu_gl_lvl1[`TSA_GLOBAL_WIDTH-1:0]),
.tlu_gl_lvl2 (tlu_gl_lvl2[`TSA_GLOBAL_WIDTH-1:0]),
.tlu_gl_lvl3 (tlu_gl_lvl3[`TSA_GLOBAL_WIDTH-1:0]),
.tlu_hpstate_din_sel0 (tlu_hpstate_din_sel0[1:0]),
.tlu_hpstate_din_sel1 (tlu_hpstate_din_sel1[1:0]),
.tlu_hpstate_din_sel2 (tlu_hpstate_din_sel2[1:0]),
.tlu_hpstate_din_sel3 (tlu_hpstate_din_sel3[1:0]),
.tlu_htickcmp_rw_e (tlu_htickcmp_rw_e),
// .tlu_update_hpstate_l_g (tlu_update_hpstate_l_g[`TLU_THRD_NUM-1:0]),
.tlu_update_hpstate_l_w2 (tlu_update_hpstate_l_w2[`TLU_THRD_NUM-1:0]),
// .tlu_htickcmp_en_l (tlu_htickcmp_en_l[`TLU_THRD_NUM-1:0]),
.tlu_htickcmp_intdis (tlu_htickcmp_intdis),
// .tlu_hintp_en_l_g (tlu_hintp_en_l_g[`TLU_THRD_NUM-1:0]),
.tlu_wr_hintp_g (tlu_wr_hintp_g[`TLU_THRD_NUM-1:0]),
// .tlu_set_hintp_g (tlu_set_hintp_g[`TLU_THRD_NUM-1:0]),
.tlu_set_hintp_sel_g (tlu_set_hintp_sel_g[`TLU_THRD_NUM-1:0]),
.tlu_htba_en_l (tlu_htba_en_l[`TLU_THRD_NUM-1:0]),
// .tlu_hyper_lite (tlu_hyper_lite[`TLU_THRD_NUM-1:0]),
.tlu_hscpd_dacc_excpt_m (tlu_hscpd_dacc_excpt_m),
.tlu_qtail_dacc_excpt_m (tlu_qtail_dacc_excpt_m),
.tlu_scpd_rd_vld_m (tlu_scpd_rd_vld_m),
// .tlu_scpd_rd_vld_g (tlu_scpd_rd_vld_g),
.tlu_scpd_wr_vld_g (tlu_scpd_wr_vld_g),
.tlu_scpd_rd_addr_m (tlu_scpd_rd_addr_m[`SCPD_RW_ADDR_WIDTH-1:0]),
.tlu_scpd_wr_addr_g (tlu_scpd_wr_addr_g[`SCPD_RW_ADDR_WIDTH-1:0]),
.tlu_asi_queue_rdata_g(tlu_asi_queue_rdata_g[`TLU_ASI_QUE_WIDTH-1:0]),
.tlu_ld_data_vld_g(tlu_ld_data_vld_g),
.tlu_asi_queue_rd_vld_g(tlu_asi_queue_rd_vld_g),
// .tlu_va_all_zero_g(tlu_va_all_zero_g),
.tlu_va_ill_g(tlu_va_ill_g),
.tlu_htstate_rw_d (tlu_htstate_rw_d),
.tlu_htstate_rw_g (tlu_htstate_rw_g),
// .tlu_htba_mx2_sel (tlu_htba_mx2_sel),
// .tlu_rdpr_mx5_sel (tlu_rdpr_mx5_sel[3:0]),
.tlu_hyperv_rdpr_sel (tlu_hyperv_rdpr_sel[4:0]),
// .tlu_rdpr_mx5_active (tlu_rdpr_mx5_active),
.tlu_exu_agp (tlu_exu_agp[`TSA_GLOBAL_WIDTH-1:0]),
.tlu_exu_agp_swap (tlu_exu_agp_swap),
.tlu_cpu_mondo_cmp (tlu_cpu_mondo_cmp[`TLU_THRD_NUM-1:0]),
.tlu_dev_mondo_cmp (tlu_dev_mondo_cmp[`TLU_THRD_NUM-1:0]),
.tlu_resum_err_cmp (tlu_resum_err_cmp[`TLU_THRD_NUM-1:0]),
// .tlu_exu_agp_tid (tlu_exu_agp_tid[1:0]),
.tlu_asi_write_g (tlu_asi_write_g),
.inc_ind_asi_wr_inrr(inc_ind_asi_wr_inrr[`TLU_THRD_NUM-1:0]),
.inc_ind_asi_wr_indr(inc_ind_asi_wr_indr[`TLU_THRD_NUM-1:0]),
.inc_ind_asi_rd_invr(inc_ind_asi_rd_invr[`TLU_THRD_NUM-1:0]),
.tlu_local_thrid_g(tlu_local_thrid_g[`TLU_THRD_NUM-1:0]),
// input
.tlu_por_rstint_g (tlu_por_rstint_g[`TLU_THRD_NUM-1:0]),
// .tlu_wsr_inst_g (tlu_wsr_inst_g),
.tlu_wsr_inst_nq_g (tlu_wsr_inst_nq_g),
// .ifu_tlu_thrid_e (ifu_tlu_thrid_e[1:0]),
.ifu_tlu_thrid_d (ifu_tlu_thrid_d[1:0]),
.ifu_tlu_sraddr_d (ifu_tlu_sraddr_d_v2[`TLU_ASR_ADDR_WIDTH-1:0]),
.tlu_wsr_data_w_global (tlu_wsr_data_w[`TLU_GLOBAL_WIDTH-1:0]),
.tlu_dnrtry_global_g (tlu_dnrtry_global_g[`TSA_GLOBAL_WIDTH-1:0]),
.tlu_dnrtry0_inst_g (tlu_dnrtry0_inst_g),
.tlu_dnrtry1_inst_g (tlu_dnrtry1_inst_g),
.tlu_dnrtry2_inst_g (tlu_dnrtry2_inst_g),
.tlu_dnrtry3_inst_g (tlu_dnrtry3_inst_g),
// modified due to timing
// .tlu_thrd0_traps (tlu_thrd0_traps),
// .tlu_thrd1_traps (tlu_thrd1_traps),
// .tlu_thrd2_traps (tlu_thrd2_traps),
// .tlu_thrd3_traps (tlu_thrd3_traps),
// .tlu_select_tba_g (tlu_select_tba_g),
.tlu_thrd_traps_w2 (tlu_thrd_traps_w2[`TLU_THRD_NUM-1:0]),
.tlu_select_tba_w2 (tlu_select_tba_w2),
.tlu_tick_ctl_din (tlu_tick_ctl_din),
// .tlu_htick_match (tlu_htick_match),
.tlu_tickcmp_sel (tlu_tickcmp_sel[`TLU_THRD_NUM-1:0]),
.tlu_pstate_priv (local_pstate_priv[`TLU_THRD_NUM-1:0]),
.tlu_hpstate_priv (local_hpstate_priv[`TLU_THRD_NUM-1:0]),
.tlu_hpstate_enb (local_hpstate_enb[`TLU_THRD_NUM-1:0]),
.ifu_lsu_alt_space_e (ifu_lsu_alt_space_e),
.ifu_lsu_ld_inst_e (ifu_lsu_ld_inst_e),
.ifu_lsu_st_inst_e (ifu_lsu_st_inst_e),
.tlu_asi_state_e (tlu_asi_state_e[`TLU_ASI_STATE_WIDTH-1:0]),
// new signal to replace ifu_tlu_flush_w
// .ifu_tlu_flush_w (ifu_tlu_flush_w),
// .tlu_flush_pipe_w (tlu_flush_pipe_w),
// .tlu_flush_all_w (tlu_flush_all_w),
.lsu_tlu_early_flush_w (lsu_tlu_early_flush2_w),
.tlu_local_flush_w (tlu_local_flush_w),
.tlu_lsu_int_ldxa_vld_w2(tlu_lsu_int_ldxa_vld_w2),
.tlu_asi_data_nf_vld_w2 (tlu_asi_data_nf_vld_w2),
.ifu_tlu_flush_fd_w (ifu_tlu_flush_fd_w),
.tlu_inst_vld_m (tlu_inst_vld_nq_m),
// .exu_lsu_ldst_va_e (exu_lsu_ldst_va_e[`TLU_ASI_VA_WIDTH-1:0]),
.lsu_tlu_ldst_va_m (lsu_tlu_ldst_va_m[`TLU_ASI_VA_WIDTH-1:0]),
.tlu_asi_queue_data_g (lsu_tlu_rs3_data_g[`TLU_ASI_QUE_HI:`TLU_ASI_QUE_LO]),
// .tlu_exu_agp_tid (tlu_exu_agp_tid[1:0]),
// .tlu_agp_tid_g (tlu_agp_tid_g[1:0]),
.tlu_agp_tid_w2 (tlu_agp_tid_w2[1:0]),
.se(se),
// .tlu_rst_l (tlu_rst_l),
// .clk (clk));
.rclk (rclk));
/*
bw_r_rf16x160 AUTO_TEMPLATE (
.word_wen (4'b1111),
.rd_clk (rclk),
.wr_clk (rclk),
.reset_l (arst_l),
.din ({mra_wdata[155:0],4'b0000}),
//.si (),
.si_r (),
.si_w (),
.se (se),
.sehold (sehold),
//.so ());
.so_r (),
.so_w ());
*/
bw_r_rf16x160 mra (/*AUTOINST*/
// Outputs
.dout ({mra_rdata[159:10],dummy_mra_rdata[9:0]}),
//.so (),
.so_r (short_scan0_4),
.so_w (short_scan0_5),
// Inputs
.rd_clk (rclk),
.wr_clk (rclk),
.din ({mra_wdata[155:0],4'b0000}),
.rst_tri_en (mem_write_disable),
.word_wen (4'b1111),
.byte_wen (mra_byte_wen[19:0]),
.wr_adr (mra_wr_ptr[3:0]),
.rd_adr (mra_rd_ptr[3:0]),
.wr_en (mra_wr_vld),
.read_en (mra_rd_vld),
.reset_l (arst_l),
.sehold (sehold),
//.si (),
.si_w (short_scan0_4),
.si_r (short_scan0_3),
.se (se));
//tlu_mra mra (/*AUTOINST*/
// // Outputs
// .mra_rdata (mra_rdata[155:0]),
// // Inputs
// .mra_wr_ptr (mra_wr_ptr[3:0]),
// .mra_rd_ptr (mra_rd_ptr[3:0]),
// .mra_wr_vld (mra_wr_vld),
// .mra_rd_vld (mra_rd_vld),
// .mra_field1_en (mra_field1_en),
// .mra_field2_en (mra_field2_en),
// .mra_field3_en (mra_field3_en),
// .mra_field4_en (mra_field4_en),
// .mra_wdata (mra_wdata[155:0]),
// .clk (rclk));
/*
tlu_pib AUTO_TEMPLATE (
.ifu_tlu_imiss_m (ifu_tlu_imiss_m),
.lsu_tlu_dcache_miss_w2 (lsu_tlu_dcache_miss_w2[3:0]),
.lsu_tlu_l2_dmiss (lsu_tlu_l2_dmiss[3:0]),
.lsu_tlu_stb_full_w2 (lsu_tlu_stb_full_w2[3:0]));
.ffu_tlu_fpu_tid (ffu_tlu_fpu_tid[1:0]),
.ffu_tlu_fpu_cmplt (ffu_tlu_fpu_cmplt),
// .pib_pic_wrap (pib_pic_wrap[3:0]),
.pib_picl_wrap (pib_picl_wrap[`TLU_THRD_NUM-1:0]),
.pich_wrap_flg (pich_wrap_flg[`TLU_THRD_NUM-1:0]),
.pich_onebelow_flg (pich_onebelow_flg[`TLU_THRD_NUM-1:0]),
.pich_twobelow_flg (pich_twobelow_flg[`TLU_THRD_NUM-1:0]),
.tlu_pic_onebelow_e (tlu_pic_onebelow_e),
.tlu_pic_twobelow_e (tlu_pic_twobelow_e),
.tlu_pic_wrap_e (tlu_pic_wrap_e),
// modified for bug 5436: Niagara 2.0
.tlu_pcr_ut (tlu_pcr_ut[`TLU_THRD_NUM-1:0]),
.tlu_pcr_st (tlu_pcr_st[`TLU_THRD_NUM-1:0]),
//.tlu_pcr_ut_e (tlu_pcr_ut_e),
//.tlu_pcr_st_e (tlu_pcr_st_e),
// .pich_threebelow_flg (pich_threebelow_flg[`TLU_THRD_NUM-1:0]),
// modified for timing fixes
// .pib_priv_act_trap (pib_priv_act_trap[3:0]),
.pib_priv_act_trap_m (pib_priv_act_trap_m[3:0]),
*/
tlu_pib tlu_pib (/*AUTOINST*/
.so (so1),
.si (scan1_3),
.grst_l (grst_l),
.arst_l (arst_l),
.ifu_tlu_imiss_e (ifu_tlu_imiss_e),
.ifu_tlu_immu_miss_m (ifu_tlu_immu_miss_m),
.tlu_hpstate_enb (local_hpstate_enb[`TLU_THRD_NUM-1:0]),
.ifu_tlu_l2imiss (ifu_tlu_l2imiss[`TLU_THRD_NUM-1:0]),
.tlu_thread_inst_vld_g (tlu_thread_inst_vld_g[`TLU_THRD_NUM-1:0]),
.ifu_tlu_thrid_d (ifu_tlu_thrid_d[1:0]),
.exu_tlu_wsr_data_m (exu_tlu_wsr_data_m[`TLU_ASR_DATA_WIDTH-1:0]),
.tlu_full_flush_pipe_w2 (tlu_full_flush_pipe_w2),
.tlu_tcc_inst_w (tlu_tcc_inst_w),
.ifu_tlu_flush_fd_w (ifu_tlu_flush_fd3_w),
.ifu_tlu_sraddr_d (ifu_tlu_sraddr_d_v2[`TLU_ASR_ADDR_WIDTH-1:0]),
.ifu_tlu_rsr_inst_d (ifu_tlu_rsr_inst_d),
// .ifu_tlu_wsr_inst_d (ifu_tlu_wsr_inst_d),
.lsu_tlu_wsr_inst_e (lsu_tlu_wsr_inst_e),
.tlu_wsr_inst_nq_g (tlu_wsr_inst_nq_g),
.tlu_pib_rsr_data_e (tlu_pib_rsr_data_e[`TLU_ASR_DATA_WIDTH-1:0]),
.tlu_pstate_priv (local_pstate_priv[`TLU_THRD_NUM-1:0]),
.tlu_hpstate_priv (local_hpstate_priv[`TLU_THRD_NUM-1:0]),
.tlu_thread_wsel_g (tlu_thread_wsel_g[`TLU_THRD_NUM-1:0]),
.ffu_tlu_fpu_tid (ffu_tlu_fpu_tid[1:0]),
.ffu_tlu_fpu_cmplt (ffu_tlu_fpu_cmplt),
.lsu_tlu_dmmu_miss_g (lsu_tlu_dmmu_miss_g),
.lsu_tlu_dcache_miss_w2(lsu_tlu_dcache_miss_w2[`TLU_THRD_NUM-1:0]),
.lsu_tlu_l2_dmiss (lsu_tlu_l2_dmiss[`TLU_THRD_NUM-1:0]),
.lsu_tlu_stb_full_w2 (lsu_tlu_stb_full_w2[`TLU_THRD_NUM-1:0]),
.tlu_wsr_data_w (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-1:0]),
// modified for timing fixes
// .pib_priv_act_trap (pib_priv_act_trap[`TLU_THRD_NUM-1:0]),
.pib_priv_act_trap_m (pib_priv_act_trap_m[`TLU_THRD_NUM-1:0]),
// .pib_pic_wrap (pib_pic_wrap[`TLU_THRD_NUM-1:0]),
.pib_picl_wrap (pib_picl_wrap[`TLU_THRD_NUM-1:0]),
.pich_wrap_flg (pich_wrap_flg[`TLU_THRD_NUM-1:0]),
.pich_onebelow_flg (pich_onebelow_flg[`TLU_THRD_NUM-1:0]),
.pich_twobelow_flg (pich_twobelow_flg[`TLU_THRD_NUM-1:0]),
.tlu_pic_onebelow_e (tlu_pic_onebelow_e),
.tlu_pic_twobelow_e (tlu_pic_twobelow_e),
// modified for bug 5436: Niagara 2.0
.tlu_pcr_ut (tlu_pcr_ut[`TLU_THRD_NUM-1:0]),
.tlu_pcr_st (tlu_pcr_st[`TLU_THRD_NUM-1:0]),
//.tlu_pcr_ut_e (tlu_pcr_ut_e),
//.tlu_pcr_st_e (tlu_pcr_st_e),
.tlu_pic_wrap_e (tlu_pic_wrap_e),
// .pich_threebelow_flg (pich_threebelow_flg[`TLU_THRD_NUM-1:0]),
// .tlu_que_trap_sel_m (tlu_que_trap_sel_m[`QUE_TRAP_SEL_WIDTH-1:0]),
// .tlu_exu_rsr_data_e (tlu_exu_rsr_data_e[`TLU_ASR_DATA_WIDTH-1:0]),
//
// reset was removed to abide to the Niagara reset methodology
// .reset (reset),
.se (se),
// .tlu_rst_l (tlu_rst_l),
// .rst_tri_en (mux_drive_disable),
.rclk (rclk) );
// modified due to Niagara SRAM methodology
/*
tlu_scpd tlu_scpd (
.lsu_tlu_st_rs3_data_g (lsu_tlu_rs3_data_g[`TLU_SCPD_DATA_WIDTH-1:0]),
.tlu_scpd_rd_vld_m (tlu_scpd_rd_vld_m),
.tlu_scpd_wr_vld_g (tlu_scpd_wr_vld_g),
.tlu_scpd_rd_addr_m (tlu_scpd_rd_addr_m[`SCPD_RW_ADDR_WIDTH-1:0]),
.tlu_scpd_wr_addr_g (tlu_scpd_wr_addr_g[`SCPD_RW_ADDR_WIDTH-1:0]),
//
// reset was removed to abide to the Niagara reset methodology
// .reset (reset),
.tlu_rst (tlu_rst),
.clk (rclk),
.tlu_scpd_asi_rdata_g (tlu_scpd_asi_rdata_g[`TLU_SCPD_DATA_WIDTH-1:0]));
//
*/
bw_r_rf32x80 tlu_scpd (
// output
.dout (tlu_scpd_asi_rdata_g[79:0]),
.so (short_scan0_6),
// intput
.din ({{16{1'b0}}, // unused inputs
lsu_tlu_rs3_data_g[`TLU_SCPD_DATA_WIDTH-1:0]}),
.rd_en (tlu_scpd_rd_vld_m),
.wr_en (tlu_scpd_wr_vld_g),
.rd_adr (tlu_scpd_rd_addr_m[`SCPD_RW_ADDR_WIDTH-1:0]),
.wr_adr (tlu_scpd_wr_addr_g[`SCPD_RW_ADDR_WIDTH-1:0]),
.nib_wr_en (20'hfffff),
.reset_l (arst_l),
.rst_tri_en (mem_write_disable),
.sehold (sehold),
.se (se),
.si (short_scan0_5),
//.clk (clk));
.rclk (rclk));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../srams/rtl")
// End:
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ram_128_32x32_dp.v
// Megafunction Name(s):
// altsyncram
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.1 Build 176 10/26/2005 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ram_128_32x32_dp (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [127:0] data;
input [3:0] rdaddress;
input rdclock;
input [1:0] wraddress;
input wrclock;
input wren;
output [31:0] q;
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.wren_a (wren),
.clock0 (wrclock),
.clock1 (rdclock),
.address_a (wraddress),
.address_b (rdaddress),
.data_a (data),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.clocken1 (1'b1),
.clocken0 (1'b1),
.q_a (),
.data_b ({32{1'b1}}),
.rden_b (1'b1),
.wren_b (1'b0),
.byteena_b (1'b1),
.addressstall_a (1'b0),
.byteena_a (1'b1),
.addressstall_b (1'b0));
defparam
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4,
altsyncram_component.numwords_b = 16,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 2,
altsyncram_component.widthad_b = 4,
altsyncram_component.width_a = 128,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "1"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "512"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "128"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "128"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "2"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "128"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: data 0 0 128 0 INPUT NODEFVAL data[127..0]
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
// Retrieval info: USED_PORT: rdaddress 0 0 4 0 INPUT NODEFVAL rdaddress[3..0]
// Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL rdclock
// Retrieval info: USED_PORT: wraddress 0 0 2 0 INPUT NODEFVAL wraddress[1..0]
// Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT NODEFVAL wrclock
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
// Retrieval info: CONNECT: @data_a 0 0 128 0 data 0 0 128 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: CONNECT: @address_a 0 0 2 0 wraddress 0 0 2 0
// Retrieval info: CONNECT: @address_b 0 0 4 0 rdaddress 0 0 4 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_128_32x32_dp.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_128_32x32_dp.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_128_32x32_dp.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_128_32x32_dp.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_128_32x32_dp_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_128_32x32_dp_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_128_32x32_dp_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_128_32x32_dp_wave*.jpg FALSE
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* ---
*
* The Simulation Library.
*
* This Verilog library contains simple simulation models for the internal
* cells ($not, ...) generated by the frontends and used in most passes.
*
* This library can be used to verify the internal netlists as generated
* by the different frontends and passes.
*
* Note that memory can only be simulated when all $memrd and $memwr cells
* have been merged to stand-alone $mem cells (this is what the "memory_collect"
* pass is doing).
*
*/
// --------------------------------------------------------
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $not (A, Y)
//-
//- A bit-wise inverter. This corresponds to the Verilog unary prefix '~' operator.
//-
module \$not (A, Y);
parameter A_SIGNED = 0;
parameter A_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED) begin:BLOCK1
assign Y = ~$signed(A);
end else begin:BLOCK2
assign Y = ~A;
end
endgenerate
endmodule
// --------------------------------------------------------
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $pos (A, Y)
//-
//- A buffer. This corresponds to the Verilog unary prefix '+' operator.
//-
module \$pos (A, Y);
parameter A_SIGNED = 0;
parameter A_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED) begin:BLOCK1
assign Y = $signed(A);
end else begin:BLOCK2
assign Y = A;
end
endgenerate
endmodule
// --------------------------------------------------------
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $neg (A, Y)
//-
//- An arithmetic inverter. This corresponds to the Verilog unary prefix '-' operator.
//-
module \$neg (A, Y);
parameter A_SIGNED = 0;
parameter A_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED) begin:BLOCK1
assign Y = -$signed(A);
end else begin:BLOCK2
assign Y = -A;
end
endgenerate
endmodule
// --------------------------------------------------------
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $and (A, B, Y)
//-
//- A bit-wise AND. This corresponds to the Verilog '&' operator.
//-
module \$and (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign Y = $signed(A) & $signed(B);
end else begin:BLOCK2
assign Y = A & B;
end
endgenerate
endmodule
// --------------------------------------------------------
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $or (A, B, Y)
//-
//- A bit-wise OR. This corresponds to the Verilog '|' operator.
//-
module \$or (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign Y = $signed(A) | $signed(B);
end else begin:BLOCK2
assign Y = A | B;
end
endgenerate
endmodule
// --------------------------------------------------------
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $xor (A, B, Y)
//-
//- A bit-wise XOR. This corresponds to the Verilog '^' operator.
//-
module \$xor (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign Y = $signed(A) ^ $signed(B);
end else begin:BLOCK2
assign Y = A ^ B;
end
endgenerate
endmodule
// --------------------------------------------------------
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $xnor (A, B, Y)
//-
//- A bit-wise XNOR. This corresponds to the Verilog '~^' operator.
//-
module \$xnor (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign Y = $signed(A) ~^ $signed(B);
end else begin:BLOCK2
assign Y = A ~^ B;
end
endgenerate
endmodule
// --------------------------------------------------------
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $reduce_and (A, Y)
//-
//- An AND reduction. This corresponds to the Verilog unary prefix '&' operator.
//-
module \$reduce_and (A, Y);
parameter A_SIGNED = 0;
parameter A_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED) begin:BLOCK1
assign Y = &$signed(A);
end else begin:BLOCK2
assign Y = &A;
end
endgenerate
endmodule
// --------------------------------------------------------
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $reduce_or (A, Y)
//-
//- An OR reduction. This corresponds to the Verilog unary prefix '|' operator.
//-
module \$reduce_or (A, Y);
parameter A_SIGNED = 0;
parameter A_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED) begin:BLOCK1
assign Y = |$signed(A);
end else begin:BLOCK2
assign Y = |A;
end
endgenerate
endmodule
// --------------------------------------------------------
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $reduce_xor (A, Y)
//-
//- A XOR reduction. This corresponds to the Verilog unary prefix '^' operator.
//-
module \$reduce_xor (A, Y);
parameter A_SIGNED = 0;
parameter A_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED) begin:BLOCK1
assign Y = ^$signed(A);
end else begin:BLOCK2
assign Y = ^A;
end
endgenerate
endmodule
// --------------------------------------------------------
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $reduce_xnor (A, Y)
//-
//- A XNOR reduction. This corresponds to the Verilog unary prefix '~^' operator.
//-
module \$reduce_xnor (A, Y);
parameter A_SIGNED = 0;
parameter A_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED) begin:BLOCK1
assign Y = ~^$signed(A);
end else begin:BLOCK2
assign Y = ~^A;
end
endgenerate
endmodule
// --------------------------------------------------------
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $reduce_bool (A, Y)
//-
//- An OR reduction. This cell type is used instead of $reduce_or when a signal is
//- implicitly converted to a boolean signal, e.g. for operands of '&&' and '||'.
//-
module \$reduce_bool (A, Y);
parameter A_SIGNED = 0;
parameter A_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED) begin:BLOCK1
assign Y = !(!$signed(A));
end else begin:BLOCK2
assign Y = !(!A);
end
endgenerate
endmodule
// --------------------------------------------------------
module \$shl (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED) begin:BLOCK1
assign Y = $signed(A) << B;
end else begin:BLOCK2
assign Y = A << B;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$shr (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED) begin:BLOCK1
assign Y = $signed(A) >> B;
end else begin:BLOCK2
assign Y = A >> B;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$sshl (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED) begin:BLOCK1
assign Y = $signed(A) <<< B;
end else begin:BLOCK2
assign Y = A <<< B;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$sshr (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED) begin:BLOCK1
assign Y = $signed(A) >>> B;
end else begin:BLOCK2
assign Y = A >>> B;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$shift (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED) begin:BLOCK1
if (B_SIGNED) begin:BLOCK2
assign Y = $signed(B) < 0 ? $signed(A) << -B : $signed(A) >> B;
end else begin:BLOCK3
assign Y = $signed(A) >> B;
end
end else begin:BLOCK4
if (B_SIGNED) begin:BLOCK5
assign Y = $signed(B) < 0 ? A << -B : A >> B;
end else begin:BLOCK6
assign Y = A >> B;
end
end
endgenerate
endmodule
// --------------------------------------------------------
module \$shiftx (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (Y_WIDTH > 0)
if (B_SIGNED) begin:BLOCK1
assign Y = A[$signed(B) +: Y_WIDTH];
end else begin:BLOCK2
assign Y = A[B +: Y_WIDTH];
end
endgenerate
endmodule
// --------------------------------------------------------
module \$fa (A, B, C, X, Y);
parameter WIDTH = 1;
input [WIDTH-1:0] A, B, C;
output [WIDTH-1:0] X, Y;
wire [WIDTH-1:0] t1, t2, t3;
assign t1 = A ^ B, t2 = A & B, t3 = C & t1;
assign Y = t1 ^ C, X = (t2 | t3) ^ (Y ^ Y);
endmodule
// --------------------------------------------------------
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $lcu (P, G, CI, CO)
//-
//- Lookahead carry unit
//- A building block dedicated to fast computation of carry-bits used in binary
//- arithmetic operations. By replacing the ripple carry structure used in full-adder
//- blocks, the more significant bits of the sum can be expected to be computed more
//- quickly.
//- Typically created during `techmap` of $alu cells (see the "_90_alu" rule in
//- +/techmap.v).
module \$lcu (P, G, CI, CO);
parameter WIDTH = 1;
input [WIDTH-1:0] P; // Propagate
input [WIDTH-1:0] G; // Generate
input CI; // Carry-in
output reg [WIDTH-1:0] CO; // Carry-out
integer i;
always @* begin
CO = 'bx;
if (^{P, G, CI} !== 1'bx) begin
CO[0] = G[0] || (P[0] && CI);
for (i = 1; i < WIDTH; i = i+1)
CO[i] = G[i] || (P[i] && CO[i-1]);
end
end
endmodule
// --------------------------------------------------------
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $alu (A, B, CI, BI, X, Y, CO)
//-
//- Arithmetic logic unit.
//- A building block supporting both binary addition/subtraction operations, and
//- indirectly, comparison operations.
//- Typically created by the `alumacc` pass, which transforms:
//- $add, $sub, $lt, $le, $ge, $gt, $eq, $eqx, $ne, $nex
//- cells into this $alu cell.
//-
module \$alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A; // Input operand
input [B_WIDTH-1:0] B; // Input operand
output [Y_WIDTH-1:0] X; // A xor B (sign-extended, optional B inversion,
// used in combination with
// reduction-AND for $eq/$ne ops)
output [Y_WIDTH-1:0] Y; // Sum
input CI; // Carry-in (set for $sub)
input BI; // Invert-B (set for $sub)
output [Y_WIDTH-1:0] CO; // Carry-out
wire [Y_WIDTH-1:0] AA, BB;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign AA = $signed(A), BB = BI ? ~$signed(B) : $signed(B);
end else begin:BLOCK2
assign AA = $unsigned(A), BB = BI ? ~$unsigned(B) : $unsigned(B);
end
endgenerate
// this is 'x' if Y and CO should be all 'x', and '0' otherwise
wire y_co_undef = ^{A, A, B, B, CI, CI, BI, BI};
assign X = AA ^ BB;
// Full adder
assign Y = (AA + BB + CI) ^ {Y_WIDTH{y_co_undef}};
function get_carry;
input a, b, c;
get_carry = (a&b) | (a&c) | (b&c);
endfunction
genvar i;
generate
assign CO[0] = get_carry(AA[0], BB[0], CI) ^ y_co_undef;
for (i = 1; i < Y_WIDTH; i = i+1) begin:BLOCK3
assign CO[i] = get_carry(AA[i], BB[i], CO[i-1]) ^ y_co_undef;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$lt (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign Y = $signed(A) < $signed(B);
end else begin:BLOCK2
assign Y = A < B;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$le (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign Y = $signed(A) <= $signed(B);
end else begin:BLOCK2
assign Y = A <= B;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$eq (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign Y = $signed(A) == $signed(B);
end else begin:BLOCK2
assign Y = A == B;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$ne (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign Y = $signed(A) != $signed(B);
end else begin:BLOCK2
assign Y = A != B;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$eqx (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign Y = $signed(A) === $signed(B);
end else begin:BLOCK2
assign Y = A === B;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$nex (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign Y = $signed(A) !== $signed(B);
end else begin:BLOCK2
assign Y = A !== B;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$ge (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign Y = $signed(A) >= $signed(B);
end else begin:BLOCK2
assign Y = A >= B;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$gt (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign Y = $signed(A) > $signed(B);
end else begin:BLOCK2
assign Y = A > B;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$add (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign Y = $signed(A) + $signed(B);
end else begin:BLOCK2
assign Y = A + B;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$sub (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign Y = $signed(A) - $signed(B);
end else begin:BLOCK2
assign Y = A - B;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$mul (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign Y = $signed(A) * $signed(B);
end else begin:BLOCK2
assign Y = A * B;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$macc (A, B, Y);
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
parameter CONFIG = 4'b0000;
parameter CONFIG_WIDTH = 4;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output reg [Y_WIDTH-1:0] Y;
// Xilinx XSIM does not like $clog2() below..
function integer my_clog2;
input integer v;
begin
if (v > 0)
v = v - 1;
my_clog2 = 0;
while (v) begin
v = v >> 1;
my_clog2 = my_clog2 + 1;
end
end
endfunction
localparam integer num_bits = CONFIG[3:0] > 0 ? CONFIG[3:0] : 1;
localparam integer num_ports = (CONFIG_WIDTH-4) / (2 + 2*num_bits);
localparam integer num_abits = my_clog2(A_WIDTH) > 0 ? my_clog2(A_WIDTH) : 1;
function [2*num_ports*num_abits-1:0] get_port_offsets;
input [CONFIG_WIDTH-1:0] cfg;
integer i, cursor;
begin
cursor = 0;
get_port_offsets = 0;
for (i = 0; i < num_ports; i = i+1) begin
get_port_offsets[(2*i + 0)*num_abits +: num_abits] = cursor;
cursor = cursor + cfg[4 + i*(2 + 2*num_bits) + 2 +: num_bits];
get_port_offsets[(2*i + 1)*num_abits +: num_abits] = cursor;
cursor = cursor + cfg[4 + i*(2 + 2*num_bits) + 2 + num_bits +: num_bits];
end
end
endfunction
localparam [2*num_ports*num_abits-1:0] port_offsets = get_port_offsets(CONFIG);
`define PORT_IS_SIGNED (0 + CONFIG[4 + i*(2 + 2*num_bits)])
`define PORT_DO_SUBTRACT (0 + CONFIG[4 + i*(2 + 2*num_bits) + 1])
`define PORT_SIZE_A (0 + CONFIG[4 + i*(2 + 2*num_bits) + 2 +: num_bits])
`define PORT_SIZE_B (0 + CONFIG[4 + i*(2 + 2*num_bits) + 2 + num_bits +: num_bits])
`define PORT_OFFSET_A (0 + port_offsets[2*i*num_abits +: num_abits])
`define PORT_OFFSET_B (0 + port_offsets[2*i*num_abits + num_abits +: num_abits])
integer i, j;
reg [Y_WIDTH-1:0] tmp_a, tmp_b;
always @* begin
Y = 0;
for (i = 0; i < num_ports; i = i+1)
begin
tmp_a = 0;
tmp_b = 0;
for (j = 0; j < `PORT_SIZE_A; j = j+1)
tmp_a[j] = A[`PORT_OFFSET_A + j];
if (`PORT_IS_SIGNED && `PORT_SIZE_A > 0)
for (j = `PORT_SIZE_A; j < Y_WIDTH; j = j+1)
tmp_a[j] = tmp_a[`PORT_SIZE_A-1];
for (j = 0; j < `PORT_SIZE_B; j = j+1)
tmp_b[j] = A[`PORT_OFFSET_B + j];
if (`PORT_IS_SIGNED && `PORT_SIZE_B > 0)
for (j = `PORT_SIZE_B; j < Y_WIDTH; j = j+1)
tmp_b[j] = tmp_b[`PORT_SIZE_B-1];
if (`PORT_SIZE_B > 0)
tmp_a = tmp_a * tmp_b;
if (`PORT_DO_SUBTRACT)
Y = Y - tmp_a;
else
Y = Y + tmp_a;
end
for (i = 0; i < B_WIDTH; i = i+1) begin
Y = Y + B[i];
end
end
`undef PORT_IS_SIGNED
`undef PORT_DO_SUBTRACT
`undef PORT_SIZE_A
`undef PORT_SIZE_B
`undef PORT_OFFSET_A
`undef PORT_OFFSET_B
endmodule
// --------------------------------------------------------
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $div (A, B, Y)
//-
//- Division with truncated result (rounded towards 0).
//-
module \$div (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign Y = $signed(A) / $signed(B);
end else begin:BLOCK2
assign Y = A / B;
end
endgenerate
endmodule
// --------------------------------------------------------
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $mod (A, B, Y)
//-
//- Modulo/remainder of division with truncated result (rounded towards 0).
//-
//- Invariant: $div(A, B) * B + $mod(A, B) == A
//-
module \$mod (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign Y = $signed(A) % $signed(B);
end else begin:BLOCK2
assign Y = A % B;
end
endgenerate
endmodule
// --------------------------------------------------------
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $divfloor (A, B, Y)
//-
//- Division with floored result (rounded towards negative infinity).
//-
module \$divfloor (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
localparam WIDTH =
A_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :
B_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;
wire [WIDTH:0] A_buf, B_buf, N_buf;
assign A_buf = $signed(A);
assign B_buf = $signed(B);
assign N_buf = (A[A_WIDTH-1] == B[B_WIDTH-1]) || A == 0 ? A_buf : $signed(A_buf - (B[B_WIDTH-1] ? B_buf+1 : B_buf-1));
assign Y = $signed(N_buf) / $signed(B_buf);
end else begin:BLOCK2
assign Y = A / B;
end
endgenerate
endmodule
// --------------------------------------------------------
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $modfloor (A, B, Y)
//-
//- Modulo/remainder of division with floored result (rounded towards negative infinity).
//-
//- Invariant: $divfloor(A, B) * B + $modfloor(A, B) == A
//-
module \$modfloor (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
localparam WIDTH = B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;
wire [WIDTH-1:0] B_buf, Y_trunc;
assign B_buf = $signed(B);
assign Y_trunc = $signed(A) % $signed(B);
// flooring mod is the same as truncating mod for positive division results (A and B have
// the same sign), as well as when there's no remainder.
// For all other cases, they behave as `floor - trunc = B`
assign Y = (A[A_WIDTH-1] == B[B_WIDTH-1]) || Y_trunc == 0 ? Y_trunc : $signed(B_buf) + $signed(Y_trunc);
end else begin:BLOCK2
// no difference between truncating and flooring for unsigned
assign Y = A % B;
end
endgenerate
endmodule
// --------------------------------------------------------
`ifndef SIMLIB_NOPOW
module \$pow (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign Y = $signed(A) ** $signed(B);
end else if (A_SIGNED) begin:BLOCK2
assign Y = $signed(A) ** B;
end else if (B_SIGNED) begin:BLOCK3
assign Y = A ** $signed(B);
end else begin:BLOCK4
assign Y = A ** B;
end
endgenerate
endmodule
`endif
// --------------------------------------------------------
module \$logic_not (A, Y);
parameter A_SIGNED = 0;
parameter A_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED) begin:BLOCK1
assign Y = !$signed(A);
end else begin:BLOCK2
assign Y = !A;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$logic_and (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign Y = $signed(A) && $signed(B);
end else begin:BLOCK2
assign Y = A && B;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$logic_or (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign Y = $signed(A) || $signed(B);
end else begin:BLOCK2
assign Y = A || B;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$slice (A, Y);
parameter OFFSET = 0;
parameter A_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
assign Y = A >> OFFSET;
endmodule
// --------------------------------------------------------
module \$concat (A, B, Y);
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [A_WIDTH+B_WIDTH-1:0] Y;
assign Y = {B, A};
endmodule
// --------------------------------------------------------
module \$mux (A, B, S, Y);
parameter WIDTH = 0;
input [WIDTH-1:0] A, B;
input S;
output reg [WIDTH-1:0] Y;
always @* begin
if (S)
Y = B;
else
Y = A;
end
endmodule
// --------------------------------------------------------
module \$pmux (A, B, S, Y);
parameter WIDTH = 0;
parameter S_WIDTH = 0;
input [WIDTH-1:0] A;
input [WIDTH*S_WIDTH-1:0] B;
input [S_WIDTH-1:0] S;
output reg [WIDTH-1:0] Y;
integer i;
reg found_active_sel_bit;
always @* begin
Y = A;
found_active_sel_bit = 0;
for (i = 0; i < S_WIDTH; i = i+1)
if (S[i]) begin
Y = found_active_sel_bit ? 'bx : B >> (WIDTH*i);
found_active_sel_bit = 1;
end
end
endmodule
// --------------------------------------------------------
`ifndef SIMLIB_NOLUT
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
output reg Y;
wire lut0_out, lut1_out;
generate
if (WIDTH <= 1) begin:simple
assign {lut1_out, lut0_out} = LUT;
end else begin:complex
\$lut #( .WIDTH(WIDTH-1), .LUT(LUT ) ) lut0 ( .A(A[WIDTH-2:0]), .Y(lut0_out) );
\$lut #( .WIDTH(WIDTH-1), .LUT(LUT >> (2**(WIDTH-1))) ) lut1 ( .A(A[WIDTH-2:0]), .Y(lut1_out) );
end
if (WIDTH > 0) begin:lutlogic
always @* begin
casez ({A[WIDTH-1], lut0_out, lut1_out})
3'b?11: Y = 1'b1;
3'b?00: Y = 1'b0;
3'b0??: Y = lut0_out;
3'b1??: Y = lut1_out;
default: Y = 1'bx;
endcase
end
end
endgenerate
endmodule
`endif
// --------------------------------------------------------
module \$sop (A, Y);
parameter WIDTH = 0;
parameter DEPTH = 0;
parameter TABLE = 0;
input [WIDTH-1:0] A;
output reg Y;
integer i, j;
reg match;
always @* begin
Y = 0;
for (i = 0; i < DEPTH; i=i+1) begin
match = 1;
for (j = 0; j < WIDTH; j=j+1) begin
if (TABLE[2*WIDTH*i + 2*j + 0] && A[j]) match = 0;
if (TABLE[2*WIDTH*i + 2*j + 1] && !A[j]) match = 0;
end
if (match) Y = 1;
end
end
endmodule
// --------------------------------------------------------
module \$tribuf (A, EN, Y);
parameter WIDTH = 0;
input [WIDTH-1:0] A;
input EN;
output [WIDTH-1:0] Y;
assign Y = EN ? A : 'bz;
endmodule
// --------------------------------------------------------
module \$specify2 (EN, SRC, DST);
parameter FULL = 0;
parameter SRC_WIDTH = 1;
parameter DST_WIDTH = 1;
parameter SRC_DST_PEN = 0;
parameter SRC_DST_POL = 0;
parameter T_RISE_MIN = 0;
parameter T_RISE_TYP = 0;
parameter T_RISE_MAX = 0;
parameter T_FALL_MIN = 0;
parameter T_FALL_TYP = 0;
parameter T_FALL_MAX = 0;
input EN;
input [SRC_WIDTH-1:0] SRC;
input [DST_WIDTH-1:0] DST;
localparam SD = SRC_DST_PEN ? (SRC_DST_POL ? 1 : 2) : 0;
`ifdef SIMLIB_SPECIFY
specify
if (EN && SD==0 && !FULL) (SRC => DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && SD==0 && FULL) (SRC *> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && SD==1 && !FULL) (SRC +=> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && SD==1 && FULL) (SRC +*> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && SD==2 && !FULL) (SRC -=> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && SD==2 && FULL) (SRC -*> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
endspecify
`endif
endmodule
// --------------------------------------------------------
module \$specify3 (EN, SRC, DST, DAT);
parameter FULL = 0;
parameter SRC_WIDTH = 1;
parameter DST_WIDTH = 1;
parameter EDGE_EN = 0;
parameter EDGE_POL = 0;
parameter SRC_DST_PEN = 0;
parameter SRC_DST_POL = 0;
parameter DAT_DST_PEN = 0;
parameter DAT_DST_POL = 0;
parameter T_RISE_MIN = 0;
parameter T_RISE_TYP = 0;
parameter T_RISE_MAX = 0;
parameter T_FALL_MIN = 0;
parameter T_FALL_TYP = 0;
parameter T_FALL_MAX = 0;
input EN;
input [SRC_WIDTH-1:0] SRC;
input [DST_WIDTH-1:0] DST, DAT;
localparam ED = EDGE_EN ? (EDGE_POL ? 1 : 2) : 0;
localparam SD = SRC_DST_PEN ? (SRC_DST_POL ? 1 : 2) : 0;
localparam DD = DAT_DST_PEN ? (DAT_DST_POL ? 1 : 2) : 0;
`ifdef SIMLIB_SPECIFY
specify
// DD=0
if (EN && DD==0 && SD==0 && ED==0 && !FULL) ( SRC => (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==0 && SD==0 && ED==0 && FULL) ( SRC *> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==0 && SD==0 && ED==1 && !FULL) (posedge SRC => (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==0 && SD==0 && ED==1 && FULL) (posedge SRC *> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==0 && SD==0 && ED==2 && !FULL) (negedge SRC => (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==0 && SD==0 && ED==2 && FULL) (negedge SRC *> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==0 && SD==1 && ED==0 && !FULL) ( SRC +=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==0 && SD==1 && ED==0 && FULL) ( SRC +*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==0 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==0 && SD==1 && ED==1 && FULL) (posedge SRC +*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==0 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==0 && SD==1 && ED==2 && FULL) (negedge SRC +*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==0 && SD==2 && ED==0 && !FULL) ( SRC -=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==0 && SD==2 && ED==0 && FULL) ( SRC -*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==0 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==0 && SD==2 && ED==1 && FULL) (posedge SRC -*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==0 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==0 && SD==2 && ED==2 && FULL) (negedge SRC -*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
// DD=1
if (EN && DD==1 && SD==0 && ED==0 && !FULL) ( SRC => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==1 && SD==0 && ED==0 && FULL) ( SRC *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==1 && SD==0 && ED==1 && !FULL) (posedge SRC => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==1 && SD==0 && ED==1 && FULL) (posedge SRC *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==1 && SD==0 && ED==2 && !FULL) (negedge SRC => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==1 && SD==0 && ED==2 && FULL) (negedge SRC *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==1 && SD==1 && ED==0 && !FULL) ( SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==1 && SD==1 && ED==0 && FULL) ( SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==1 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==1 && SD==1 && ED==1 && FULL) (posedge SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==1 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==1 && SD==1 && ED==2 && FULL) (negedge SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==1 && SD==2 && ED==0 && !FULL) ( SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==1 && SD==2 && ED==0 && FULL) ( SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==1 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==1 && SD==2 && ED==1 && FULL) (posedge SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==1 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==1 && SD==2 && ED==2 && FULL) (negedge SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
// DD=2
if (EN && DD==2 && SD==0 && ED==0 && !FULL) ( SRC => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==2 && SD==0 && ED==0 && FULL) ( SRC *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==2 && SD==0 && ED==1 && !FULL) (posedge SRC => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==2 && SD==0 && ED==1 && FULL) (posedge SRC *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==2 && SD==0 && ED==2 && !FULL) (negedge SRC => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==2 && SD==0 && ED==2 && FULL) (negedge SRC *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==2 && SD==1 && ED==0 && !FULL) ( SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==2 && SD==1 && ED==0 && FULL) ( SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==2 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==2 && SD==1 && ED==1 && FULL) (posedge SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==2 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==2 && SD==1 && ED==2 && FULL) (negedge SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==2 && SD==2 && ED==0 && !FULL) ( SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==2 && SD==2 && ED==0 && FULL) ( SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==2 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==2 && SD==2 && ED==1 && FULL) (posedge SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==2 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
if (EN && DD==2 && SD==2 && ED==2 && FULL) (negedge SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
endspecify
`endif
endmodule
// --------------------------------------------------------
module \$specrule (EN_SRC, EN_DST, SRC, DST);
parameter TYPE = "";
parameter T_LIMIT = 0;
parameter T_LIMIT2 = 0;
parameter SRC_WIDTH = 1;
parameter DST_WIDTH = 1;
parameter SRC_PEN = 0;
parameter SRC_POL = 0;
parameter DST_PEN = 0;
parameter DST_POL = 0;
input EN_SRC, EN_DST;
input [SRC_WIDTH-1:0] SRC;
input [DST_WIDTH-1:0] DST;
`ifdef SIMLIB_SPECIFY
specify
// TBD
endspecify
`endif
endmodule
// --------------------------------------------------------
module \$assert (A, EN);
input A, EN;
`ifndef SIMLIB_NOCHECKS
always @* begin
if (A !== 1'b1 && EN === 1'b1) begin
$display("Assertion %m failed!");
$stop;
end
end
`endif
endmodule
// --------------------------------------------------------
module \$assume (A, EN);
input A, EN;
`ifndef SIMLIB_NOCHECKS
always @* begin
if (A !== 1'b1 && EN === 1'b1) begin
$display("Assumption %m failed!");
$stop;
end
end
`endif
endmodule
// --------------------------------------------------------
module \$live (A, EN);
input A, EN;
endmodule
// --------------------------------------------------------
module \$fair (A, EN);
input A, EN;
endmodule
// --------------------------------------------------------
module \$cover (A, EN);
input A, EN;
endmodule
// --------------------------------------------------------
module \$initstate (Y);
output reg Y = 1;
reg [3:0] cnt = 1;
reg trig = 0;
initial trig <= 1;
always @(cnt, trig) begin
Y <= |cnt;
cnt <= cnt + |cnt;
end
endmodule
// --------------------------------------------------------
module \$anyconst (Y);
parameter WIDTH = 0;
output [WIDTH-1:0] Y;
assign Y = 'bx;
endmodule
// --------------------------------------------------------
module \$anyseq (Y);
parameter WIDTH = 0;
output [WIDTH-1:0] Y;
assign Y = 'bx;
endmodule
// --------------------------------------------------------
module \$allconst (Y);
parameter WIDTH = 0;
output [WIDTH-1:0] Y;
assign Y = 'bx;
endmodule
// --------------------------------------------------------
module \$allseq (Y);
parameter WIDTH = 0;
output [WIDTH-1:0] Y;
assign Y = 'bx;
endmodule
// --------------------------------------------------------
module \$equiv (A, B, Y);
input A, B;
output Y;
assign Y = (A !== 1'bx && A !== B) ? 1'bx : A;
`ifndef SIMLIB_NOCHECKS
always @* begin
if (A !== 1'bx && A !== B) begin
$display("Equivalence failed!");
$stop;
end
end
`endif
endmodule
// --------------------------------------------------------
`ifndef SIMLIB_NOSR
module \$sr (SET, CLR, Q);
parameter WIDTH = 0;
parameter SET_POLARITY = 1'b1;
parameter CLR_POLARITY = 1'b1;
input [WIDTH-1:0] SET, CLR;
output reg [WIDTH-1:0] Q;
wire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;
wire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;
genvar i;
generate
for (i = 0; i < WIDTH; i = i+1) begin:bitslices
always @*
if (pos_clr[i])
Q[i] <= 0;
else if (pos_set[i])
Q[i] <= 1;
end
endgenerate
endmodule
`endif
// --------------------------------------------------------
`ifdef SIMLIB_FF
module \$ff (D, Q);
parameter WIDTH = 0;
input [WIDTH-1:0] D;
output reg [WIDTH-1:0] Q;
always @($global_clk) begin
Q <= D;
end
endmodule
`endif
// --------------------------------------------------------
module \$dff (CLK, D, Q);
parameter WIDTH = 0;
parameter CLK_POLARITY = 1'b1;
input CLK;
input [WIDTH-1:0] D;
output reg [WIDTH-1:0] Q;
wire pos_clk = CLK == CLK_POLARITY;
always @(posedge pos_clk) begin
Q <= D;
end
endmodule
// --------------------------------------------------------
module \$dffe (CLK, EN, D, Q);
parameter WIDTH = 0;
parameter CLK_POLARITY = 1'b1;
parameter EN_POLARITY = 1'b1;
input CLK, EN;
input [WIDTH-1:0] D;
output reg [WIDTH-1:0] Q;
wire pos_clk = CLK == CLK_POLARITY;
always @(posedge pos_clk) begin
if (EN == EN_POLARITY) Q <= D;
end
endmodule
// --------------------------------------------------------
`ifndef SIMLIB_NOSR
module \$dffsr (CLK, SET, CLR, D, Q);
parameter WIDTH = 0;
parameter CLK_POLARITY = 1'b1;
parameter SET_POLARITY = 1'b1;
parameter CLR_POLARITY = 1'b1;
input CLK;
input [WIDTH-1:0] SET, CLR, D;
output reg [WIDTH-1:0] Q;
wire pos_clk = CLK == CLK_POLARITY;
wire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;
wire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;
genvar i;
generate
for (i = 0; i < WIDTH; i = i+1) begin:bitslices
always @(posedge pos_set[i], posedge pos_clr[i], posedge pos_clk)
if (pos_clr[i])
Q[i] <= 0;
else if (pos_set[i])
Q[i] <= 1;
else
Q[i] <= D[i];
end
endgenerate
endmodule
// --------------------------------------------------------
module \$dffsre (CLK, SET, CLR, EN, D, Q);
parameter WIDTH = 0;
parameter CLK_POLARITY = 1'b1;
parameter SET_POLARITY = 1'b1;
parameter CLR_POLARITY = 1'b1;
parameter EN_POLARITY = 1'b1;
input CLK, EN;
input [WIDTH-1:0] SET, CLR, D;
output reg [WIDTH-1:0] Q;
wire pos_clk = CLK == CLK_POLARITY;
wire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;
wire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;
genvar i;
generate
for (i = 0; i < WIDTH; i = i+1) begin:bitslices
always @(posedge pos_set[i], posedge pos_clr[i], posedge pos_clk)
if (pos_clr[i])
Q[i] <= 0;
else if (pos_set[i])
Q[i] <= 1;
else if (EN == EN_POLARITY)
Q[i] <= D[i];
end
endgenerate
endmodule
`endif
// --------------------------------------------------------
module \$adff (CLK, ARST, D, Q);
parameter WIDTH = 0;
parameter CLK_POLARITY = 1'b1;
parameter ARST_POLARITY = 1'b1;
parameter ARST_VALUE = 0;
input CLK, ARST;
input [WIDTH-1:0] D;
output reg [WIDTH-1:0] Q;
wire pos_clk = CLK == CLK_POLARITY;
wire pos_arst = ARST == ARST_POLARITY;
always @(posedge pos_clk, posedge pos_arst) begin
if (pos_arst)
Q <= ARST_VALUE;
else
Q <= D;
end
endmodule
// --------------------------------------------------------
module \$aldff (CLK, ALOAD, AD, D, Q);
parameter WIDTH = 0;
parameter CLK_POLARITY = 1'b1;
parameter ALOAD_POLARITY = 1'b1;
input CLK, ALOAD;
input [WIDTH-1:0] AD;
input [WIDTH-1:0] D;
output reg [WIDTH-1:0] Q;
wire pos_clk = CLK == CLK_POLARITY;
wire pos_aload = ALOAD == ALOAD_POLARITY;
always @(posedge pos_clk, posedge pos_aload) begin
if (pos_aload)
Q <= AD;
else
Q <= D;
end
endmodule
// --------------------------------------------------------
module \$sdff (CLK, SRST, D, Q);
parameter WIDTH = 0;
parameter CLK_POLARITY = 1'b1;
parameter SRST_POLARITY = 1'b1;
parameter SRST_VALUE = 0;
input CLK, SRST;
input [WIDTH-1:0] D;
output reg [WIDTH-1:0] Q;
wire pos_clk = CLK == CLK_POLARITY;
wire pos_srst = SRST == SRST_POLARITY;
always @(posedge pos_clk) begin
if (pos_srst)
Q <= SRST_VALUE;
else
Q <= D;
end
endmodule
// --------------------------------------------------------
module \$adffe (CLK, ARST, EN, D, Q);
parameter WIDTH = 0;
parameter CLK_POLARITY = 1'b1;
parameter EN_POLARITY = 1'b1;
parameter ARST_POLARITY = 1'b1;
parameter ARST_VALUE = 0;
input CLK, ARST, EN;
input [WIDTH-1:0] D;
output reg [WIDTH-1:0] Q;
wire pos_clk = CLK == CLK_POLARITY;
wire pos_arst = ARST == ARST_POLARITY;
always @(posedge pos_clk, posedge pos_arst) begin
if (pos_arst)
Q <= ARST_VALUE;
else if (EN == EN_POLARITY)
Q <= D;
end
endmodule
// --------------------------------------------------------
module \$aldffe (CLK, ALOAD, AD, EN, D, Q);
parameter WIDTH = 0;
parameter CLK_POLARITY = 1'b1;
parameter EN_POLARITY = 1'b1;
parameter ALOAD_POLARITY = 1'b1;
input CLK, ALOAD, EN;
input [WIDTH-1:0] D;
input [WIDTH-1:0] AD;
output reg [WIDTH-1:0] Q;
wire pos_clk = CLK == CLK_POLARITY;
wire pos_aload = ALOAD == ALOAD_POLARITY;
always @(posedge pos_clk, posedge pos_aload) begin
if (pos_aload)
Q <= AD;
else if (EN == EN_POLARITY)
Q <= D;
end
endmodule
// --------------------------------------------------------
module \$sdffe (CLK, SRST, EN, D, Q);
parameter WIDTH = 0;
parameter CLK_POLARITY = 1'b1;
parameter EN_POLARITY = 1'b1;
parameter SRST_POLARITY = 1'b1;
parameter SRST_VALUE = 0;
input CLK, SRST, EN;
input [WIDTH-1:0] D;
output reg [WIDTH-1:0] Q;
wire pos_clk = CLK == CLK_POLARITY;
wire pos_srst = SRST == SRST_POLARITY;
always @(posedge pos_clk) begin
if (pos_srst)
Q <= SRST_VALUE;
else if (EN == EN_POLARITY)
Q <= D;
end
endmodule
// --------------------------------------------------------
module \$sdffce (CLK, SRST, EN, D, Q);
parameter WIDTH = 0;
parameter CLK_POLARITY = 1'b1;
parameter EN_POLARITY = 1'b1;
parameter SRST_POLARITY = 1'b1;
parameter SRST_VALUE = 0;
input CLK, SRST, EN;
input [WIDTH-1:0] D;
output reg [WIDTH-1:0] Q;
wire pos_clk = CLK == CLK_POLARITY;
wire pos_srst = SRST == SRST_POLARITY;
always @(posedge pos_clk) begin
if (EN == EN_POLARITY) begin
if (pos_srst)
Q <= SRST_VALUE;
else
Q <= D;
end
end
endmodule
// --------------------------------------------------------
module \$dlatch (EN, D, Q);
parameter WIDTH = 0;
parameter EN_POLARITY = 1'b1;
input EN;
input [WIDTH-1:0] D;
output reg [WIDTH-1:0] Q;
always @* begin
if (EN == EN_POLARITY)
Q = D;
end
endmodule
// --------------------------------------------------------
module \$adlatch (EN, ARST, D, Q);
parameter WIDTH = 0;
parameter EN_POLARITY = 1'b1;
parameter ARST_POLARITY = 1'b1;
parameter ARST_VALUE = 0;
input EN, ARST;
input [WIDTH-1:0] D;
output reg [WIDTH-1:0] Q;
always @* begin
if (ARST == ARST_POLARITY)
Q = ARST_VALUE;
else if (EN == EN_POLARITY)
Q = D;
end
endmodule
// --------------------------------------------------------
`ifndef SIMLIB_NOSR
module \$dlatchsr (EN, SET, CLR, D, Q);
parameter WIDTH = 0;
parameter EN_POLARITY = 1'b1;
parameter SET_POLARITY = 1'b1;
parameter CLR_POLARITY = 1'b1;
input EN;
input [WIDTH-1:0] SET, CLR, D;
output reg [WIDTH-1:0] Q;
wire pos_en = EN == EN_POLARITY;
wire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;
wire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;
genvar i;
generate
for (i = 0; i < WIDTH; i = i+1) begin:bitslices
always @*
if (pos_clr[i])
Q[i] = 0;
else if (pos_set[i])
Q[i] = 1;
else if (pos_en)
Q[i] = D[i];
end
endgenerate
endmodule
`endif
// --------------------------------------------------------
module \$fsm (CLK, ARST, CTRL_IN, CTRL_OUT);
parameter NAME = "";
parameter CLK_POLARITY = 1'b1;
parameter ARST_POLARITY = 1'b1;
parameter CTRL_IN_WIDTH = 1;
parameter CTRL_OUT_WIDTH = 1;
parameter STATE_BITS = 1;
parameter STATE_NUM = 1;
parameter STATE_NUM_LOG2 = 1;
parameter STATE_RST = 0;
parameter STATE_TABLE = 1'b0;
parameter TRANS_NUM = 1;
parameter TRANS_TABLE = 4'b0x0x;
input CLK, ARST;
input [CTRL_IN_WIDTH-1:0] CTRL_IN;
output reg [CTRL_OUT_WIDTH-1:0] CTRL_OUT;
wire pos_clk = CLK == CLK_POLARITY;
wire pos_arst = ARST == ARST_POLARITY;
reg [STATE_BITS-1:0] state;
reg [STATE_BITS-1:0] state_tmp;
reg [STATE_BITS-1:0] next_state;
reg [STATE_BITS-1:0] tr_state_in;
reg [STATE_BITS-1:0] tr_state_out;
reg [CTRL_IN_WIDTH-1:0] tr_ctrl_in;
reg [CTRL_OUT_WIDTH-1:0] tr_ctrl_out;
integer i;
task tr_fetch;
input [31:0] tr_num;
reg [31:0] tr_pos;
reg [STATE_NUM_LOG2-1:0] state_num;
begin
tr_pos = (2*STATE_NUM_LOG2+CTRL_IN_WIDTH+CTRL_OUT_WIDTH)*tr_num;
tr_ctrl_out = TRANS_TABLE >> tr_pos;
tr_pos = tr_pos + CTRL_OUT_WIDTH;
state_num = TRANS_TABLE >> tr_pos;
tr_state_out = STATE_TABLE >> (STATE_BITS*state_num);
tr_pos = tr_pos + STATE_NUM_LOG2;
tr_ctrl_in = TRANS_TABLE >> tr_pos;
tr_pos = tr_pos + CTRL_IN_WIDTH;
state_num = TRANS_TABLE >> tr_pos;
tr_state_in = STATE_TABLE >> (STATE_BITS*state_num);
tr_pos = tr_pos + STATE_NUM_LOG2;
end
endtask
always @(posedge pos_clk, posedge pos_arst) begin
if (pos_arst) begin
state_tmp = STATE_TABLE[STATE_BITS*(STATE_RST+1)-1:STATE_BITS*STATE_RST];
for (i = 0; i < STATE_BITS; i = i+1)
if (state_tmp[i] === 1'bz)
state_tmp[i] = 0;
state <= state_tmp;
end else begin
state_tmp = next_state;
for (i = 0; i < STATE_BITS; i = i+1)
if (state_tmp[i] === 1'bz)
state_tmp[i] = 0;
state <= state_tmp;
end
end
always @(state, CTRL_IN) begin
next_state <= STATE_TABLE[STATE_BITS*(STATE_RST+1)-1:STATE_BITS*STATE_RST];
CTRL_OUT <= 'bx;
// $display("---");
// $display("Q: %b %b", state, CTRL_IN);
for (i = 0; i < TRANS_NUM; i = i+1) begin
tr_fetch(i);
// $display("T: %b %b -> %b %b [%d]", tr_state_in, tr_ctrl_in, tr_state_out, tr_ctrl_out, i);
casez ({state, CTRL_IN})
{tr_state_in, tr_ctrl_in}: begin
// $display("-> %b %b <- MATCH", state, CTRL_IN);
{next_state, CTRL_OUT} <= {tr_state_out, tr_ctrl_out};
end
endcase
end
end
endmodule
// --------------------------------------------------------
`ifndef SIMLIB_NOMEM
module \$memrd (CLK, EN, ADDR, DATA);
parameter MEMID = "";
parameter ABITS = 8;
parameter WIDTH = 8;
parameter CLK_ENABLE = 0;
parameter CLK_POLARITY = 0;
parameter TRANSPARENT = 0;
input CLK, EN;
input [ABITS-1:0] ADDR;
output [WIDTH-1:0] DATA;
initial begin
if (MEMID != "") begin
$display("ERROR: Found non-simulatable instance of $memrd!");
$finish;
end
end
endmodule
module \$memrd_v2 (CLK, EN, ARST, SRST, ADDR, DATA);
parameter MEMID = "";
parameter ABITS = 8;
parameter WIDTH = 8;
parameter CLK_ENABLE = 0;
parameter CLK_POLARITY = 0;
parameter TRANSPARENCY_MASK = 0;
parameter COLLISION_X_MASK = 0;
parameter ARST_VALUE = 0;
parameter SRST_VALUE = 0;
parameter INIT_VALUE = 0;
parameter CE_OVER_SRST = 0;
input CLK, EN, ARST, SRST;
input [ABITS-1:0] ADDR;
output [WIDTH-1:0] DATA;
initial begin
if (MEMID != "") begin
$display("ERROR: Found non-simulatable instance of $memrd_v2!");
$finish;
end
end
endmodule
// --------------------------------------------------------
module \$memwr (CLK, EN, ADDR, DATA);
parameter MEMID = "";
parameter ABITS = 8;
parameter WIDTH = 8;
parameter CLK_ENABLE = 0;
parameter CLK_POLARITY = 0;
parameter PRIORITY = 0;
input CLK;
input [WIDTH-1:0] EN;
input [ABITS-1:0] ADDR;
input [WIDTH-1:0] DATA;
initial begin
if (MEMID != "") begin
$display("ERROR: Found non-simulatable instance of $memwr!");
$finish;
end
end
endmodule
module \$memwr_v2 (CLK, EN, ADDR, DATA);
parameter MEMID = "";
parameter ABITS = 8;
parameter WIDTH = 8;
parameter CLK_ENABLE = 0;
parameter CLK_POLARITY = 0;
parameter PORTID = 0;
parameter PRIORITY_MASK = 0;
input CLK;
input [WIDTH-1:0] EN;
input [ABITS-1:0] ADDR;
input [WIDTH-1:0] DATA;
initial begin
if (MEMID != "") begin
$display("ERROR: Found non-simulatable instance of $memwr_v2!");
$finish;
end
end
endmodule
// --------------------------------------------------------
module \$meminit (ADDR, DATA);
parameter MEMID = "";
parameter ABITS = 8;
parameter WIDTH = 8;
parameter WORDS = 1;
parameter PRIORITY = 0;
input [ABITS-1:0] ADDR;
input [WORDS*WIDTH-1:0] DATA;
initial begin
if (MEMID != "") begin
$display("ERROR: Found non-simulatable instance of $meminit!");
$finish;
end
end
endmodule
// --------------------------------------------------------
module \$meminit_v2 (ADDR, DATA, EN);
parameter MEMID = "";
parameter ABITS = 8;
parameter WIDTH = 8;
parameter WORDS = 1;
parameter PRIORITY = 0;
input [ABITS-1:0] ADDR;
input [WORDS*WIDTH-1:0] DATA;
input [WIDTH-1:0] EN;
initial begin
if (MEMID != "") begin
$display("ERROR: Found non-simulatable instance of $meminit_v2!");
$finish;
end
end
endmodule
// --------------------------------------------------------
module \$mem (RD_CLK, RD_EN, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);
parameter MEMID = "";
parameter signed SIZE = 4;
parameter signed OFFSET = 0;
parameter signed ABITS = 2;
parameter signed WIDTH = 8;
parameter signed INIT = 1'bx;
parameter signed RD_PORTS = 1;
parameter RD_CLK_ENABLE = 1'b1;
parameter RD_CLK_POLARITY = 1'b1;
parameter RD_TRANSPARENT = 1'b1;
parameter signed WR_PORTS = 1;
parameter WR_CLK_ENABLE = 1'b1;
parameter WR_CLK_POLARITY = 1'b1;
input [RD_PORTS-1:0] RD_CLK;
input [RD_PORTS-1:0] RD_EN;
input [RD_PORTS*ABITS-1:0] RD_ADDR;
output reg [RD_PORTS*WIDTH-1:0] RD_DATA;
input [WR_PORTS-1:0] WR_CLK;
input [WR_PORTS*WIDTH-1:0] WR_EN;
input [WR_PORTS*ABITS-1:0] WR_ADDR;
input [WR_PORTS*WIDTH-1:0] WR_DATA;
reg [WIDTH-1:0] memory [SIZE-1:0];
integer i, j;
reg [WR_PORTS-1:0] LAST_WR_CLK;
reg [RD_PORTS-1:0] LAST_RD_CLK;
function port_active;
input clk_enable;
input clk_polarity;
input last_clk;
input this_clk;
begin
casez ({clk_enable, clk_polarity, last_clk, this_clk})
4'b0???: port_active = 1;
4'b1101: port_active = 1;
4'b1010: port_active = 1;
default: port_active = 0;
endcase
end
endfunction
initial begin
for (i = 0; i < SIZE; i = i+1)
memory[i] = INIT >>> (i*WIDTH);
end
always @(RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA) begin
`ifdef SIMLIB_MEMDELAY
#`SIMLIB_MEMDELAY;
`endif
for (i = 0; i < RD_PORTS; i = i+1) begin
if (!RD_TRANSPARENT[i] && RD_CLK_ENABLE[i] && RD_EN[i] && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin
// $display("Read from %s: addr=%b data=%b", MEMID, RD_ADDR[i*ABITS +: ABITS], memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);
RD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];
end
end
for (i = 0; i < WR_PORTS; i = i+1) begin
if (port_active(WR_CLK_ENABLE[i], WR_CLK_POLARITY[i], LAST_WR_CLK[i], WR_CLK[i]))
for (j = 0; j < WIDTH; j = j+1)
if (WR_EN[i*WIDTH+j]) begin
// $display("Write to %s: addr=%b data=%b", MEMID, WR_ADDR[i*ABITS +: ABITS], WR_DATA[i*WIDTH+j]);
memory[WR_ADDR[i*ABITS +: ABITS] - OFFSET][j] = WR_DATA[i*WIDTH+j];
end
end
for (i = 0; i < RD_PORTS; i = i+1) begin
if ((RD_TRANSPARENT[i] || !RD_CLK_ENABLE[i]) && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin
// $display("Transparent read from %s: addr=%b data=%b", MEMID, RD_ADDR[i*ABITS +: ABITS], memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);
RD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];
end
end
LAST_RD_CLK <= RD_CLK;
LAST_WR_CLK <= WR_CLK;
end
endmodule
module \$mem_v2 (RD_CLK, RD_EN, RD_ARST, RD_SRST, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);
parameter MEMID = "";
parameter signed SIZE = 4;
parameter signed OFFSET = 0;
parameter signed ABITS = 2;
parameter signed WIDTH = 8;
parameter signed INIT = 1'bx;
parameter signed RD_PORTS = 1;
parameter RD_CLK_ENABLE = 1'b1;
parameter RD_CLK_POLARITY = 1'b1;
parameter RD_TRANSPARENCY_MASK = 1'b0;
parameter RD_COLLISION_X_MASK = 1'b0;
parameter RD_WIDE_CONTINUATION = 1'b0;
parameter RD_CE_OVER_SRST = 1'b0;
parameter RD_ARST_VALUE = 1'b0;
parameter RD_SRST_VALUE = 1'b0;
parameter RD_INIT_VALUE = 1'b0;
parameter signed WR_PORTS = 1;
parameter WR_CLK_ENABLE = 1'b1;
parameter WR_CLK_POLARITY = 1'b1;
parameter WR_PRIORITY_MASK = 1'b0;
parameter WR_WIDE_CONTINUATION = 1'b0;
input [RD_PORTS-1:0] RD_CLK;
input [RD_PORTS-1:0] RD_EN;
input [RD_PORTS-1:0] RD_ARST;
input [RD_PORTS-1:0] RD_SRST;
input [RD_PORTS*ABITS-1:0] RD_ADDR;
output reg [RD_PORTS*WIDTH-1:0] RD_DATA;
input [WR_PORTS-1:0] WR_CLK;
input [WR_PORTS*WIDTH-1:0] WR_EN;
input [WR_PORTS*ABITS-1:0] WR_ADDR;
input [WR_PORTS*WIDTH-1:0] WR_DATA;
reg [WIDTH-1:0] memory [SIZE-1:0];
integer i, j, k;
reg [WR_PORTS-1:0] LAST_WR_CLK;
reg [RD_PORTS-1:0] LAST_RD_CLK;
function port_active;
input clk_enable;
input clk_polarity;
input last_clk;
input this_clk;
begin
casez ({clk_enable, clk_polarity, last_clk, this_clk})
4'b0???: port_active = 1;
4'b1101: port_active = 1;
4'b1010: port_active = 1;
default: port_active = 0;
endcase
end
endfunction
initial begin
for (i = 0; i < SIZE; i = i+1)
memory[i] = INIT >>> (i*WIDTH);
RD_DATA = RD_INIT_VALUE;
end
always @(RD_CLK, RD_ARST, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA) begin
`ifdef SIMLIB_MEMDELAY
#`SIMLIB_MEMDELAY;
`endif
for (i = 0; i < RD_PORTS; i = i+1) begin
if (RD_CLK_ENABLE[i] && RD_EN[i] && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin
// $display("Read from %s: addr=%b data=%b", MEMID, RD_ADDR[i*ABITS +: ABITS], memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);
RD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];
for (j = 0; j < WR_PORTS; j = j+1) begin
if (RD_TRANSPARENCY_MASK[i*WR_PORTS + j] && port_active(WR_CLK_ENABLE[j], WR_CLK_POLARITY[j], LAST_WR_CLK[j], WR_CLK[j]) && RD_ADDR[i*ABITS +: ABITS] == WR_ADDR[j*ABITS +: ABITS])
for (k = 0; k < WIDTH; k = k+1)
if (WR_EN[j*WIDTH+k])
RD_DATA[i*WIDTH+k] <= WR_DATA[j*WIDTH+k];
if (RD_COLLISION_X_MASK[i*WR_PORTS + j] && port_active(WR_CLK_ENABLE[j], WR_CLK_POLARITY[j], LAST_WR_CLK[j], WR_CLK[j]) && RD_ADDR[i*ABITS +: ABITS] == WR_ADDR[j*ABITS +: ABITS])
for (k = 0; k < WIDTH; k = k+1)
if (WR_EN[j*WIDTH+k])
RD_DATA[i*WIDTH+k] <= 1'bx;
end
end
end
for (i = 0; i < WR_PORTS; i = i+1) begin
if (port_active(WR_CLK_ENABLE[i], WR_CLK_POLARITY[i], LAST_WR_CLK[i], WR_CLK[i]))
for (j = 0; j < WIDTH; j = j+1)
if (WR_EN[i*WIDTH+j]) begin
// $display("Write to %s: addr=%b data=%b", MEMID, WR_ADDR[i*ABITS +: ABITS], WR_DATA[i*WIDTH+j]);
memory[WR_ADDR[i*ABITS +: ABITS] - OFFSET][j] = WR_DATA[i*WIDTH+j];
end
end
for (i = 0; i < RD_PORTS; i = i+1) begin
if (!RD_CLK_ENABLE[i]) begin
// $display("Combinatorial read from %s: addr=%b data=%b", MEMID, RD_ADDR[i*ABITS +: ABITS], memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);
RD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];
end
end
for (i = 0; i < RD_PORTS; i = i+1) begin
if (RD_SRST[i] && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i]) && (RD_EN[i] || !RD_CE_OVER_SRST[i]))
RD_DATA[i*WIDTH +: WIDTH] <= RD_SRST_VALUE[i*WIDTH +: WIDTH];
if (RD_ARST[i])
RD_DATA[i*WIDTH +: WIDTH] <= RD_ARST_VALUE[i*WIDTH +: WIDTH];
end
LAST_RD_CLK <= RD_CLK;
LAST_WR_CLK <= WR_CLK;
end
endmodule
`endif
// --------------------------------------------------------
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: text_ram.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
// ************************************************************
//Copyright (C) 2018 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module text_ram (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [7:0] data;
input [9:0] rdaddress;
input rdclock;
input [9:0] wraddress;
input wrclock;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrclock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (wrclock),
.clock1 (rdclock),
.data_a (data),
.wren_a (wren),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({8{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.init_file = "ram/text_ram.mif",
altsyncram_component.intended_device_family = "Cyclone 10 LP",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.numwords_b = 1024,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "CLOCK1",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 10,
altsyncram_component.widthad_b = 10,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "1"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "ram/text_ram.mif"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "ram/text_ram.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 10 0 INPUT NODEFVAL "rdaddress[9..0]"
// Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock"
// Retrieval info: USED_PORT: wraddress 0 0 10 0 INPUT NODEFVAL "wraddress[9..0]"
// Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 10 0 wraddress 0 0 10 0
// Retrieval info: CONNECT: @address_b 0 0 10 0 rdaddress 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL text_ram.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL text_ram.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL text_ram.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL text_ram.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL text_ram_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL text_ram_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* Frame Generator
*
* Generate the replied package from Tag to Reader
* including Preamle, Replied Data, End-of-Signaling
*
* Support FM0 Encoder and Miller Encoder in M = 2, 4, 8
* the forms of encoding is depends on M
*
* Two forms of preamble, which is depends on Trext
*/
`timescale 1us / 1ns
module frmgen
(
output reg send_data,
output en_fm0,
output reg st_enc,
output pre_p_complete,
output p_complete,
output reg fg_complete,
input clk_frm,
input rst_for_new_package,
input reply_data,
input [15:0]crc_16,
input [1:0]m,
input trext,
input reply_complete,
input en_crc16_for_rpy
);
reg reply_complete_d;
reg [4:0]cnt_end;
reg [4:0]p_cnt;
reg [3:0]crc_cnt;
reg crc_complete;
assign en_fm0 = (m == 2'b00)? 1'b1 : 1'b0;
assign pre_p_complete = (p_cnt > (cnt_end - 5'h2))? 1'b1 : 1'b0;
assign p_complete = (p_cnt == cnt_end)? 1'b1 : 1'b0;
always@(posedge clk_frm or negedge rst_for_new_package) begin
if(~rst_for_new_package) st_enc <= 1'b0;
else st_enc <= 1'b1;
end
always@(posedge clk_frm or negedge rst_for_new_package) begin
if(~rst_for_new_package) reply_complete_d <= 1'b0;
else reply_complete_d <= reply_complete;
end
always@(*) begin
case({m, trext})
3'b000 : cnt_end = 5'h6;
3'b001 : cnt_end = 5'h12;
3'b010 : cnt_end = 5'ha;
3'b011 : cnt_end = 5'h16;
3'b100 : cnt_end = 5'ha;
3'b101 : cnt_end = 5'h16;
3'b110 : cnt_end = 5'ha;
3'b111 : cnt_end = 5'h16;
endcase
end
always@(posedge clk_frm or negedge rst_for_new_package) begin
if(~rst_for_new_package) p_cnt <= 5'h0;
else begin
if(p_cnt == cnt_end) p_cnt <= p_cnt;
else p_cnt <= p_cnt + 5'h1;
end
end
always@(posedge clk_frm or negedge rst_for_new_package) begin
if(~rst_for_new_package) send_data <= 1'b0;
else if(~en_crc16_for_rpy & reply_complete_d) send_data <= 1'b1;
else if(en_crc16_for_rpy & crc_complete) send_data <= 1'b1;
else if(reply_complete_d & en_crc16_for_rpy & ~crc_complete) send_data <= crc_16[crc_cnt];
else begin
if(p_cnt != cnt_end) begin
if(m == 2'b00) begin
if(~trext) begin
case(p_cnt)
5'h0 : send_data <= 1'b1;
5'h1 : send_data <= 1'b0;
5'h2 : send_data <= 1'b1;
5'h3 : send_data <= 1'b0;
5'h4 : send_data <= 1'b0;
5'h5 : send_data <= 1'b1;
endcase
end
else begin
case(p_cnt)
5'h0, 5'h1, 5'h2, 5'h3, 5'h4, 5'h5, 5'h6, 5'h7, 5'h8, 5'h9, 5'ha, 5'hb : send_data <= 1'b0;
5'hc : send_data <= 1'b1;
5'hd : send_data <= 1'b0;
5'he : send_data <= 1'b1;
5'hf : send_data <= 1'b0;
5'h10 : send_data <= 1'b0;
5'h11 : send_data <= 1'b1;
endcase
end
end
else begin
if(~trext) begin
case(p_cnt)
5'h0, 5'h1, 5'h2, 5'h3 : send_data <= 1'b0;
5'h4 : send_data <= 1'b0;
5'h5 : send_data <= 1'b1;
5'h6 : send_data <= 1'b0;
5'h7 : send_data <= 1'b1;
5'h8 : send_data <= 1'b1;
5'h9 : send_data <= 1'b1;
endcase
end
else begin
case(p_cnt)
5'h0, 5'h1, 5'h2, 5'h3, 5'h4, 5'h5, 5'h6, 5'h7, 5'h8, 5'h9, 5'ha, 5'hb, 5'hc, 5'hd, 5'he, 5'hf : send_data <= 1'b0;
5'h10 : send_data <= 1'b0;
5'h11 : send_data <= 1'b1;
5'h12 : send_data <= 1'b0;
5'h13 : send_data <= 1'b1;
5'h14 : send_data <= 1'b1;
5'h15 : send_data <= 1'b1;
endcase
end
end
end
else send_data <= reply_data;
end
end
always@(posedge clk_frm or negedge rst_for_new_package) begin
if(~rst_for_new_package) crc_cnt <= 4'hf;
else begin
if(crc_cnt == 4'h0) crc_cnt <= crc_cnt;
else if(reply_complete_d & en_crc16_for_rpy) crc_cnt <= crc_cnt - 4'h1;
end
end
always@(posedge clk_frm or negedge rst_for_new_package) begin
if(~rst_for_new_package) crc_complete <= 1'b0;
else if(crc_cnt == 4'h0) crc_complete <= 1'b1;
end
always@(posedge clk_frm or negedge rst_for_new_package) begin
if(~rst_for_new_package) fg_complete <= 1'b0;
else begin
if(reply_complete_d & ~en_crc16_for_rpy) fg_complete <= 1'b1;
else if(crc_complete & en_crc16_for_rpy) fg_complete <= 1'b1;
end
end
endmodule
|
// Copyright (C) 1991-2011 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// Quartus II 11.0 Build 157 04/27/2011
// ********** PRIMITIVE DEFINITIONS **********
`timescale 1 ps/1 ps
// ***** DFFE
primitive CYCLONE_PRIM_DFFE (Q, ENA, D, CLK, CLRN, PRN, notifier);
input D;
input CLRN;
input PRN;
input CLK;
input ENA;
input notifier;
output Q; reg Q;
initial Q = 1'b0;
table
// ENA D CLK CLRN PRN notifier : Qt : Qt+1
(??) ? ? 1 1 ? : ? : -; // pessimism
x ? ? 1 1 ? : ? : -; // pessimism
1 1 (01) 1 1 ? : ? : 1; // clocked data
1 1 (01) 1 x ? : ? : 1; // pessimism
1 1 ? 1 x ? : 1 : 1; // pessimism
1 0 0 1 x ? : 1 : 1; // pessimism
1 0 x 1 (?x) ? : 1 : 1; // pessimism
1 0 1 1 (?x) ? : 1 : 1; // pessimism
1 x 0 1 x ? : 1 : 1; // pessimism
1 x x 1 (?x) ? : 1 : 1; // pessimism
1 x 1 1 (?x) ? : 1 : 1; // pessimism
1 0 (01) 1 1 ? : ? : 0; // clocked data
1 0 (01) x 1 ? : ? : 0; // pessimism
1 0 ? x 1 ? : 0 : 0; // pessimism
0 ? ? x 1 ? : ? : -;
1 1 0 x 1 ? : 0 : 0; // pessimism
1 1 x (?x) 1 ? : 0 : 0; // pessimism
1 1 1 (?x) 1 ? : 0 : 0; // pessimism
1 x 0 x 1 ? : 0 : 0; // pessimism
1 x x (?x) 1 ? : 0 : 0; // pessimism
1 x 1 (?x) 1 ? : 0 : 0; // pessimism
// 1 1 (x1) 1 1 ? : 1 : 1; // reducing pessimism
// 1 0 (x1) 1 1 ? : 0 : 0;
1 ? (x1) 1 1 ? : ? : -; // spr 80166-ignore
// x->1 edge
1 1 (0x) 1 1 ? : 1 : 1;
1 0 (0x) 1 1 ? : 0 : 0;
? ? ? 0 0 ? : ? : 0; // clear wins preset
? ? ? 0 1 ? : ? : 0; // asynch clear
? ? ? 1 0 ? : ? : 1; // asynch set
1 ? (?0) 1 1 ? : ? : -; // ignore falling clock
1 ? (1x) 1 1 ? : ? : -; // ignore falling clock
1 * ? ? ? ? : ? : -; // ignore data edges
1 ? ? (?1) ? ? : ? : -; // ignore edges on
1 ? ? ? (?1) ? : ? : -; // set and clear
0 ? ? 1 1 ? : ? : -; // set and clear
? ? ? 1 1 * : ? : x; // spr 36954 - at any
// notifier event,
// output 'x'
endtable
endprimitive
primitive CYCLONE_PRIM_DFFEAS (q, d, clk, ena, clr, pre, ald, adt, sclr, sload, notifier );
input d,clk,ena,clr,pre,ald,adt,sclr,sload, notifier;
output q;
reg q;
initial
q = 1'b0;
table
////d,clk, ena,clr,pre,ald,adt,sclr,sload,notifier: q : q'
? ? ? 1 ? ? ? ? ? ? : ? : 0; // aclr
? ? ? 0 1 ? ? ? ? ? : ? : 1; // apre
? ? ? 0 0 1 0 ? ? ? : ? : 0; // aload 0
? ? ? 0 0 1 1 ? ? ? : ? : 1; // aload 1
0 (01) 1 0 0 0 ? 0 0 ? : ? : 0; // din 0
1 (01) 1 0 0 0 ? 0 0 ? : ? : 1; // din 1
? (01) 1 0 0 0 ? 1 ? ? : ? : 0; // sclr
? (01) 1 0 0 0 0 0 1 ? : ? : 0; // sload 0
? (01) 1 0 0 0 1 0 1 ? : ? : 1; // sload 1
? ? 0 0 0 0 ? ? ? ? : ? : -; // no asy no ena
* ? ? ? ? ? ? ? ? ? : ? : -; // data edges
? (?0) ? ? ? ? ? ? ? ? : ? : -; // ignore falling clk
? ? * ? ? ? ? ? ? ? : ? : -; // enable edges
? ? ? (?0)? ? ? ? ? ? : ? : -; // falling asynchs
? ? ? ? (?0) ? ? ? ? ? : ? : -;
? ? ? ? ? (?0) ? ? ? ? : ? : -;
? ? ? ? ? 0 * ? ? ? : ? : -; // ignore adata edges when not aloading
? ? ? ? ? ? ? * ? ? : ? : -; // sclr edges
? ? ? ? ? ? ? ? * ? : ? : -; // sload edges
? (x1) 1 0 0 0 ? 0 0 ? : ? : -; // ignore x->1 transition of clock
? ? 1 0 0 x ? 0 0 ? : ? : -; // ignore x input of aload
? ? ? 1 1 ? ? ? ? * : ? : x; // at any notifier event, output x
endtable
endprimitive
primitive CYCLONE_PRIM_DFFEAS_HIGH (q, d, clk, ena, clr, pre, ald, adt, sclr, sload, notifier );
input d,clk,ena,clr,pre,ald,adt,sclr,sload, notifier;
output q;
reg q;
initial
q = 1'b1;
table
////d,clk, ena,clr,pre,ald,adt,sclr,sload,notifier : q : q'
? ? ? 1 ? ? ? ? ? ? : ? : 0; // aclr
? ? ? 0 1 ? ? ? ? ? : ? : 1; // apre
? ? ? 0 0 1 0 ? ? ? : ? : 0; // aload 0
? ? ? 0 0 1 1 ? ? ? : ? : 1; // aload 1
0 (01) 1 0 0 0 ? 0 0 ? : ? : 0; // din 0
1 (01) 1 0 0 0 ? 0 0 ? : ? : 1; // din 1
? (01) 1 0 0 0 ? 1 ? ? : ? : 0; // sclr
? (01) 1 0 0 0 0 0 1 ? : ? : 0; // sload 0
? (01) 1 0 0 0 1 0 1 ? : ? : 1; // sload 1
? ? 0 0 0 0 ? ? ? ? : ? : -; // no asy no ena
* ? ? ? ? ? ? ? ? ? : ? : -; // data edges
? (?0) ? ? ? ? ? ? ? ? : ? : -; // ignore falling clk
? ? * ? ? ? ? ? ? ? : ? : -; // enable edges
? ? ? (?0)? ? ? ? ? ? : ? : -; // falling asynchs
? ? ? ? (?0) ? ? ? ? ? : ? : -;
? ? ? ? ? (?0) ? ? ? ? : ? : -;
? ? ? ? ? 0 * ? ? ? : ? : -; // ignore adata edges when not aloading
? ? ? ? ? ? ? * ? ? : ? : -; // sclr edges
? ? ? ? ? ? ? ? * ? : ? : -; // sload edges
? (x1) 1 0 0 0 ? 0 0 ? : ? : -; // ignore x->1 transition of clock
? ? 1 0 0 x ? 0 0 ? : ? : -; // ignore x input of aload
? ? ? 1 1 ? ? ? ? * : ? : x; // at any notifier event, output x
endtable
endprimitive
module cyclone_dffe ( Q, CLK, ENA, D, CLRN, PRN );
input D;
input CLK;
input CLRN;
input PRN;
input ENA;
output Q;
wire D_ipd;
wire ENA_ipd;
wire CLK_ipd;
wire PRN_ipd;
wire CLRN_ipd;
buf (D_ipd, D);
buf (ENA_ipd, ENA);
buf (CLK_ipd, CLK);
buf (PRN_ipd, PRN);
buf (CLRN_ipd, CLRN);
wire legal;
reg viol_notifier;
CYCLONE_PRIM_DFFE ( Q, ENA_ipd, D_ipd, CLK_ipd, CLRN_ipd, PRN_ipd, viol_notifier );
and(legal, ENA_ipd, CLRN_ipd, PRN_ipd);
specify
specparam TREG = 0;
specparam TREN = 0;
specparam TRSU = 0;
specparam TRH = 0;
specparam TRPR = 0;
specparam TRCL = 0;
$setup ( D, posedge CLK &&& legal, TRSU, viol_notifier ) ;
$hold ( posedge CLK &&& legal, D, TRH, viol_notifier ) ;
$setup ( ENA, posedge CLK &&& legal, TREN, viol_notifier ) ;
$hold ( posedge CLK &&& legal, ENA, 0, viol_notifier ) ;
( negedge CLRN => (Q +: 1'b0)) = ( TRCL, TRCL) ;
( negedge PRN => (Q +: 1'b1)) = ( TRPR, TRPR) ;
( posedge CLK => (Q +: D)) = ( TREG, TREG) ;
endspecify
endmodule
// ***** cyclone_mux21
module cyclone_mux21 (MO, A, B, S);
input A, B, S;
output MO;
wire A_in;
wire B_in;
wire S_in;
buf(A_in, A);
buf(B_in, B);
buf(S_in, S);
wire tmp_MO;
specify
(A => MO) = (0, 0);
(B => MO) = (0, 0);
(S => MO) = (0, 0);
endspecify
assign tmp_MO = (S_in == 1) ? B_in : A_in;
buf (MO, tmp_MO);
endmodule
// ***** cyclone_mux41
module cyclone_mux41 (MO, IN0, IN1, IN2, IN3, S);
input IN0;
input IN1;
input IN2;
input IN3;
input [1:0] S;
output MO;
wire IN0_in;
wire IN1_in;
wire IN2_in;
wire IN3_in;
wire S1_in;
wire S0_in;
buf(IN0_in, IN0);
buf(IN1_in, IN1);
buf(IN2_in, IN2);
buf(IN3_in, IN3);
buf(S1_in, S[1]);
buf(S0_in, S[0]);
wire tmp_MO;
specify
(IN0 => MO) = (0, 0);
(IN1 => MO) = (0, 0);
(IN2 => MO) = (0, 0);
(IN3 => MO) = (0, 0);
(S[1] => MO) = (0, 0);
(S[0] => MO) = (0, 0);
endspecify
assign tmp_MO = S1_in ? (S0_in ? IN3_in : IN2_in) : (S0_in ? IN1_in : IN0_in);
buf (MO, tmp_MO);
endmodule
// ***** cyclone_and1
module cyclone_and1 (Y, IN1);
input IN1;
output Y;
specify
(IN1 => Y) = (0, 0);
endspecify
buf (Y, IN1);
endmodule
// ***** cyclone_and16
module cyclone_and16 (Y, IN1);
input [15:0] IN1;
output [15:0] Y;
specify
(IN1 => Y) = (0, 0);
endspecify
buf (Y[0], IN1[0]);
buf (Y[1], IN1[1]);
buf (Y[2], IN1[2]);
buf (Y[3], IN1[3]);
buf (Y[4], IN1[4]);
buf (Y[5], IN1[5]);
buf (Y[6], IN1[6]);
buf (Y[7], IN1[7]);
buf (Y[8], IN1[8]);
buf (Y[9], IN1[9]);
buf (Y[10], IN1[10]);
buf (Y[11], IN1[11]);
buf (Y[12], IN1[12]);
buf (Y[13], IN1[13]);
buf (Y[14], IN1[14]);
buf (Y[15], IN1[15]);
endmodule
// ***** cyclone_bmux21
module cyclone_bmux21 (MO, A, B, S);
input [15:0] A, B;
input S;
output [15:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
// ***** cyclone_b17mux21
module cyclone_b17mux21 (MO, A, B, S);
input [16:0] A, B;
input S;
output [16:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
// ***** cyclone_nmux21
module cyclone_nmux21 (MO, A, B, S);
input A, B, S;
output MO;
assign MO = (S == 1) ? ~B : ~A;
endmodule
// ***** cyclone_b5mux21
module cyclone_b5mux21 (MO, A, B, S);
input [4:0] A, B;
input S;
output [4:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
// ********** END PRIMITIVE DEFINITIONS **********
///////////////////////////////////////////////////////////////////////
//
// Module Name : cyclone_asynch_lcell
//
// Description : Verilog simulation model for asynchronous LUT based
// module in Cyclone Lcell.
//
///////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module cyclone_asynch_lcell (
dataa,
datab,
datac,
datad,
cin,
cin0,
cin1,
inverta,
qfbkin,
regin,
combout,
cout,
cout0,
cout1
);
parameter operation_mode = "normal" ;
parameter sum_lutc_input = "datac";
parameter lut_mask = "ffff" ;
parameter cin_used = "false";
parameter cin0_used = "false";
parameter cin1_used = "false";
// INPUT PORTS
input dataa;
input datab;
input datac;
input datad ;
input cin;
input cin0;
input cin1;
input inverta;
input qfbkin;
// OUTPUT PORTS
output combout;
output cout;
output cout0;
output cout1;
output regin;
// INTERNAL VARIABLES
reg icout;
reg icout0;
reg icout1;
reg data;
reg lut_data;
reg inverta_dataa;
reg [15:0] bin_mask;
integer iop_mode;
reg [1:0] isum_lutc_input;
reg icin_used;
reg icin0_used;
reg icin1_used;
wire qfbk_mode;
// INPUT BUFFERS
wire idataa;
wire idatab;
wire idatac;
wire idatad;
wire icin;
wire icin0;
wire icin1;
wire iinverta;
buf (idataa, dataa);
buf (idatab, datab);
buf (idatac, datac);
buf (idatad, datad);
buf (icin, cin);
buf (icin0, cin0);
buf (icin1, cin1);
buf (iinverta, inverta);
assign qfbk_mode = (sum_lutc_input == "qfbk") ? 1'b1 : 1'b0;
specify
(dataa => combout) = (0, 0) ;
(datab => combout) = (0, 0) ;
(datac => combout) = (0, 0) ;
(datad => combout) = (0, 0) ;
(cin => combout) = (0, 0) ;
(cin0 => combout) = (0, 0) ;
(cin1 => combout) = (0, 0) ;
(inverta => combout) = (0, 0) ;
if (qfbk_mode == 1'b1)
(qfbkin => combout) = (0, 0) ;
(dataa => cout) = (0, 0);
(datab => cout) = (0, 0);
(cin => cout) = (0, 0) ;
(cin0 => cout) = (0, 0) ;
(cin1 => cout) = (0, 0) ;
(inverta => cout) = (0, 0);
(dataa => cout0) = (0, 0);
(datab => cout0) = (0, 0);
(cin0 => cout0) = (0, 0) ;
(inverta => cout0) = (0, 0);
(dataa => cout1) = (0, 0);
(datab => cout1) = (0, 0);
(cin1 => cout1) = (0, 0) ;
(inverta => cout1) = (0, 0);
(dataa => regin) = (0, 0) ;
(datab => regin) = (0, 0) ;
(datac => regin) = (0, 0) ;
(datad => regin) = (0, 0) ;
(cin => regin) = (0, 0) ;
(cin0 => regin) = (0, 0) ;
(cin1 => regin) = (0, 0) ;
(inverta => regin) = (0, 0) ;
if (qfbk_mode == 1'b1)
(qfbkin => regin) = (0, 0) ;
endspecify
function [16:1] str_to_bin ;
input [8*4:1] s;
reg [8*4:1] reg_s;
reg [4:1] digit [8:1];
reg [8:1] tmp;
integer m;
integer ivalue ;
begin
ivalue = 0;
reg_s = s;
for (m=1; m<=4; m= m+1 )
begin
tmp = reg_s[32:25];
digit[m] = tmp & 8'b00001111;
reg_s = reg_s << 8;
if (tmp[7] == 'b1)
digit[m] = digit[m] + 9;
end
str_to_bin = {digit[1], digit[2], digit[3], digit[4]};
end
endfunction
// 4-input LUT function
function lut4;
input [15:0] mask;
input dataa;
input datab;
input datac;
input datad;
begin
lut4 = datad ? ( datac ? ( datab ? ( dataa ? mask[15] : mask[14])
: ( dataa ? mask[13] : mask[12]))
: ( datab ? ( dataa ? mask[11] : mask[10])
: ( dataa ? mask[ 9] : mask[ 8])))
: ( datac ? ( datab ? ( dataa ? mask[ 7] : mask[ 6])
: ( dataa ? mask[ 5] : mask[ 4]))
: ( datab ? ( dataa ? mask[ 3] : mask[ 2])
: ( dataa ? mask[ 1] : mask[ 0])));
end
endfunction
initial
begin
bin_mask = str_to_bin(lut_mask);
if (operation_mode == "normal")
iop_mode = 0; // normal mode
else if (operation_mode == "arithmetic")
iop_mode = 1; // arithmetic mode
else
begin
$display ("Error: Invalid operation_mode specified\n");
$display ("Time: %0t Instance: %m", $time);
iop_mode = 2;
end
if (sum_lutc_input == "datac")
isum_lutc_input = 0;
else if (sum_lutc_input == "cin")
isum_lutc_input = 1;
else if (sum_lutc_input == "qfbk")
isum_lutc_input = 2;
else
begin
$display ("Error: Invalid sum_lutc_input specified\n");
$display ("Time: %0t Instance: %m", $time);
isum_lutc_input = 3;
end
if (cin_used == "true")
icin_used = 1;
else if (cin_used == "false")
icin_used = 0;
if (cin0_used == "true")
icin0_used = 1;
else if (cin0_used == "false")
icin0_used = 0;
if (cin1_used == "true")
icin1_used = 1;
else if (cin1_used == "false")
icin1_used = 0;
end
always @(idatad or idatac or idatab or idataa or icin or
icin0 or icin1 or iinverta or qfbkin)
begin
if (iinverta === 'b1) //invert dataa
inverta_dataa = !idataa;
else
inverta_dataa = idataa;
if (iop_mode == 0) // normal mode
begin
if (isum_lutc_input == 0) // datac
begin
data = lut4(bin_mask, inverta_dataa, idatab,
idatac, idatad);
end
else if (isum_lutc_input == 1) // cin
begin
if (icin0_used == 1 || icin1_used == 1)
begin
if (icin_used == 1)
data = (icin === 'b0) ?
lut4(bin_mask,
inverta_dataa,
idatab,
icin0,
idatad) :
lut4(bin_mask,
inverta_dataa,
idatab,
icin1,
idatad);
else // if cin is not used then inverta
// should be used in place of cin
data = (iinverta === 'b0) ?
lut4(bin_mask,
inverta_dataa,
idatab,
icin0,
idatad) :
lut4(bin_mask,
inverta_dataa,
idatab,
icin1,
idatad);
end
else
data = lut4(bin_mask, inverta_dataa, idatab,
icin, idatad);
end
else if(isum_lutc_input == 2) // qfbk
begin
data = lut4(bin_mask, inverta_dataa, idatab,
qfbkin, idatad);
end
end
else if (iop_mode == 1) // arithmetic mode
begin
// sum LUT
if (isum_lutc_input == 0) // datac
begin
data = lut4(bin_mask, inverta_dataa, idatab,
idatac, 'b1);
end
else if (isum_lutc_input == 1) // cin
begin
if (icin0_used == 1 || icin1_used == 1)
begin
if (icin_used == 1)
data = (icin === 'b0) ?
lut4(bin_mask,
inverta_dataa,
idatab,
icin0,
'b1) :
lut4(bin_mask,
inverta_dataa,
idatab,
icin1,
'b1);
else // if cin is not used then inverta
// should be used in place of cin
data = (iinverta === 'b0) ?
lut4(bin_mask,
inverta_dataa,
idatab,
icin0,
'b1) :
lut4(bin_mask,
inverta_dataa,
idatab,
icin1,
'b1);
end
else if (icin_used == 1)
data = lut4(bin_mask, inverta_dataa, idatab,
icin, 'b1);
else // cin is not used, inverta is used as cin
data = lut4(bin_mask, inverta_dataa, idatab,
iinverta, 'b1);
end
else if(isum_lutc_input == 2) // qfbk
begin
data = lut4(bin_mask, inverta_dataa, idatab,
qfbkin, 'b1);
end
// carry LUT
icout0 = lut4(bin_mask, inverta_dataa, idatab, icin0, 'b0);
icout1 = lut4(bin_mask, inverta_dataa, idatab, icin1, 'b0);
if (icin_used == 1)
begin
if (icin0_used == 1 || icin1_used == 1)
icout = (icin === 'b0) ? icout0 : icout1;
else
icout = lut4(bin_mask, inverta_dataa, idatab,
icin, 'b0);
end
else // inverta is used in place of cin
begin
if (icin0_used == 1 || icin1_used == 1)
icout = (iinverta === 'b0) ? icout0 : icout1;
else
icout = lut4(bin_mask, inverta_dataa, idatab,
iinverta, 'b0);
end
end
end
and (combout, data, 1'b1) ;
and (cout, icout, 1'b1) ;
and (cout0, icout0, 1'b1) ;
and (cout1, icout1, 1'b1) ;
and (regin, data, 1'b1) ;
endmodule
///////////////////////////////////////////////////////////////////////
//
// Module Name : cyclone_lcell_register
//
// Description : Verilog simulation model for register with control
// signals module in Cyclone Lcell.
//
///////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module cyclone_lcell_register (
clk,
aclr,
aload,
sclr,
sload,
ena,
datain,
datac,
regcascin,
devclrn,
devpor,
regout,
qfbkout
);
parameter synch_mode = "off";
parameter register_cascade_mode = "off";
parameter power_up = "low";
parameter x_on_violation = "on";
// INPUT PORTS
input clk;
input ena;
input aclr;
input aload;
input sclr;
input sload;
input datain;
input datac;
input regcascin;
input devclrn;
input devpor ;
// OUTPUT PORTS
output regout;
output qfbkout;
// INTERNAL VARIABLES
reg iregout;
wire reset;
wire nosload;
reg regcascin_viol;
reg datain_viol, datac_viol;
reg sclr_viol, sload_viol;
reg ena_viol, clk_per_viol;
reg violation;
reg clk_last_value;
reg ipower_up;
reg icascade_mode;
reg isynch_mode;
reg ix_on_violation;
// INPUT BUFFERS
wire clk_in;
wire iaclr;
wire iaload;
wire isclr;
wire isload;
wire iena;
wire idatac;
wire iregcascin;
wire idatain;
buf (clk_in, clk);
buf (iaclr, aclr);
buf (iaload, aload);
buf (isclr, sclr);
buf (isload, sload);
buf (iena, ena);
buf (idatac, datac);
buf (iregcascin, regcascin);
buf (idatain, datain);
assign reset = devpor && devclrn && (!iaclr) && (iena);
assign nosload = reset && (!isload);
specify
$setuphold (posedge clk &&& reset, regcascin, 0, 0, regcascin_viol) ;
$setuphold (posedge clk &&& nosload, datain, 0, 0, datain_viol) ;
$setuphold (posedge clk &&& reset, datac, 0, 0, datac_viol) ;
$setuphold (posedge clk &&& reset, sclr, 0, 0, sclr_viol) ;
$setuphold (posedge clk &&& reset, sload, 0, 0, sload_viol) ;
$setuphold (posedge clk &&& reset, ena, 0, 0, ena_viol) ;
(posedge clk => (regout +: iregout)) = 0 ;
(posedge aclr => (regout +: 1'b0)) = (0, 0) ;
(posedge aload => (regout +: iregout)) = (0, 0) ;
(datac => regout) = (0, 0) ;
(posedge clk => (qfbkout +: iregout)) = 0 ;
(posedge aclr => (qfbkout +: 1'b0)) = (0, 0) ;
(posedge aload => (qfbkout +: iregout)) = (0, 0) ;
(datac => qfbkout) = (0, 0) ;
endspecify
initial
begin
violation = 0;
clk_last_value = 'b0;
if (power_up == "low")
begin
iregout <= 'b0;
ipower_up = 0;
end
else if (power_up == "high")
begin
iregout <= 'b1;
ipower_up = 1;
end
if (register_cascade_mode == "on")
icascade_mode = 1;
else
icascade_mode = 0;
if (synch_mode == "on" )
isynch_mode = 1;
else
isynch_mode = 0;
if (x_on_violation == "on")
ix_on_violation = 1;
else
ix_on_violation = 0;
end
always @ (regcascin_viol or datain_viol or datac_viol or sclr_viol
or sload_viol or ena_viol or clk_per_viol)
begin
if (ix_on_violation == 1)
violation = 1;
end
always @ (clk_in or idatac or iaclr or posedge iaload
or devclrn or devpor or posedge violation)
begin
if (violation == 1'b1)
begin
violation = 0;
iregout <= 'bx;
end
else
begin
if (devpor == 'b0)
begin
if (ipower_up == 0) // "low"
iregout <= 'b0;
else if (ipower_up == 1) // "high"
iregout <= 'b1;
end
else if (devclrn == 'b0)
iregout <= 'b0;
else if (iaclr === 'b1)
iregout <= 'b0 ;
else if (iaload === 'b1)
iregout <= idatac;
else if (iena === 'b1 && clk_in === 'b1 &&
clk_last_value === 'b0)
begin
if (isynch_mode == 1)
begin
if (isclr === 'b1)
iregout <= 'b0 ;
else if (isload === 'b1)
iregout <= idatac;
else if (icascade_mode == 1)
iregout <= iregcascin;
else
iregout <= idatain;
end
else if (icascade_mode == 1)
iregout <= iregcascin;
else
iregout <= idatain;
end
end
clk_last_value = clk_in;
end
and (regout, iregout, 1'b1);
and (qfbkout, iregout, 1'b1);
endmodule
///////////////////////////////////////////////////////////////////////
//
// Module Name : cyclone_lcell
//
// Description : Verilog simulation model for Cyclone Lcell, including
// the following sub module(s):
// 1. cyclone_asynch_lcell
// 2. cyclone_lcell_register
//
///////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module cyclone_lcell (
clk,
dataa,
datab,
datac,
datad,
aclr,
aload,
sclr,
sload,
ena,
cin,
cin0,
cin1,
inverta,
regcascin,
devclrn,
devpor,
combout,
regout,
cout,
cout0,
cout1
);
parameter operation_mode = "normal" ;
parameter synch_mode = "off";
parameter register_cascade_mode = "off";
parameter sum_lutc_input = "datac";
parameter lut_mask = "ffff" ;
parameter power_up = "low";
parameter cin_used = "false";
parameter cin0_used = "false";
parameter cin1_used = "false";
parameter output_mode = "reg_and_comb";
parameter lpm_type = "cyclone_lcell";
parameter x_on_violation = "on";
// INPUT PORTS
input dataa;
input datab;
input datac;
input datad;
input clk;
input aclr;
input aload;
input sclr;
input sload;
input ena;
input cin;
input cin0;
input cin1;
input inverta;
input regcascin;
input devclrn;
input devpor ;
// OUTPUT PORTS
output combout;
output regout;
output cout;
output cout0;
output cout1;
tri1 devclrn;
tri1 devpor;
// INTERNAL VARIABLES
wire dffin, qfbkin;
cyclone_asynch_lcell lecomb (
.dataa(dataa),
.datab(datab),
.datac(datac),
.datad(datad),
.cin(cin),
.cin0(cin0),
.cin1(cin1),
.inverta(inverta),
.qfbkin(qfbkin),
.regin(dffin),
.combout(combout),
.cout(cout),
.cout0(cout0),
.cout1(cout1)
);
defparam lecomb.operation_mode = operation_mode;
defparam lecomb.sum_lutc_input = sum_lutc_input;
defparam lecomb.cin_used = cin_used;
defparam lecomb.cin0_used = cin0_used;
defparam lecomb.cin1_used = cin1_used;
defparam lecomb.lut_mask = lut_mask;
cyclone_lcell_register lereg (
.clk(clk),
.aclr(aclr),
.aload(aload),
.sclr(sclr),
.sload(sload),
.ena(ena),
.datain(dffin),
.datac(datac),
.regcascin(regcascin),
.devclrn(devclrn),
.devpor(devpor),
.regout(regout),
.qfbkout(qfbkin)
);
defparam lereg.synch_mode = synch_mode;
defparam lereg.register_cascade_mode = register_cascade_mode;
defparam lereg.power_up = power_up;
defparam lereg.x_on_violation = x_on_violation;
endmodule
//--------------------------------------------------------------------------
// Module Name : cyclone_ram_pulse_generator
// Description : Generate pulse to initiate memory read/write operations
//--------------------------------------------------------------------------
`timescale 1 ps/1 ps
module cyclone_ram_pulse_generator (
clk,
ena,
pulse,
cycle
);
input clk; // clock
input ena; // pulse enable
output pulse; // pulse
output cycle; // delayed clock
parameter start_delay = 1;
reg state;
reg clk_prev;
wire clk_ipd;
specify
specparam t_decode = 0,t_access = 0;
(posedge clk => (pulse +: state)) = (t_decode,t_access);
endspecify
buf #(start_delay) (clk_ipd,clk);
wire pulse_opd;
buf buf_pulse (pulse,pulse_opd);
initial clk_prev = 1'bx;
always @(clk_ipd or posedge pulse)
begin
if (pulse) state <= 1'b0;
else if (ena && clk_ipd === 1'b1 && clk_prev === 1'b0) state <= 1'b1;
clk_prev = clk_ipd;
end
assign cycle = clk_ipd;
assign pulse_opd = state;
endmodule
//--------------------------------------------------------------------------
// Module Name : cyclone_ram_register
// Description : Register module for RAM inputs/outputs
//--------------------------------------------------------------------------
`timescale 1 ps/1 ps
module cyclone_ram_register (
d,
clk,
aclr,
devclrn,
devpor,
ena,
q,
aclrout
);
parameter width = 1; // data width
parameter preset = 1'b0; // clear acts as preset
input [width - 1:0] d; // data
input clk; // clock
input aclr; // asynch clear
input devclrn,devpor; // device wide clear/reset
input ena; // clock enable
output [width - 1:0] q; // register output
output aclrout; // delayed asynch clear
wire ena_ipd;
wire clk_ipd;
wire aclr_ipd;
wire [width - 1:0] d_ipd;
buf buf_ena (ena_ipd,ena);
buf buf_clk (clk_ipd,clk);
buf buf_aclr (aclr_ipd,aclr);
buf buf_d [width - 1:0] (d_ipd,d);
wire [width - 1:0] q_opd;
buf buf_q [width - 1:0] (q,q_opd);
reg [width - 1:0] q_reg;
reg viol_notifier;
wire reset;
assign reset = devpor && devclrn && (!aclr_ipd) && (ena_ipd);
specify
$setup (d, posedge clk &&& reset, 0, viol_notifier);
$setup (aclr, posedge clk, 0, viol_notifier);
$setup (ena, posedge clk &&& reset, 0, viol_notifier );
$hold (posedge clk &&& reset, d , 0, viol_notifier);
$hold (posedge clk, aclr, 0, viol_notifier);
$hold (posedge clk &&& reset, ena , 0, viol_notifier );
(posedge clk => (q +: q_reg)) = (0,0);
(posedge aclr => (q +: q_reg)) = (0,0);
endspecify
initial q_reg <= (preset) ? {width{1'b1}} : 'b0;
always @(posedge clk_ipd or posedge aclr_ipd or negedge devclrn or negedge devpor)
begin
if (aclr_ipd || ~devclrn || ~devpor)
q_reg <= (preset) ? {width{1'b1}} : 'b0;
else if (ena_ipd)
q_reg <= d_ipd;
end
assign aclrout = aclr_ipd;
assign q_opd = q_reg;
endmodule
`timescale 1 ps/1 ps
`define PRIME 1
`define SEC 0
//--------------------------------------------------------------------------
// Module Name : cyclone_ram_block
// Description : Main RAM module
//--------------------------------------------------------------------------
module cyclone_ram_block
(
portadatain,
portaaddr,
portawe,
portbdatain,
portbaddr,
portbrewe,
clk0, clk1,
ena0, ena1,
clr0, clr1,
portabyteenamasks,
portbbyteenamasks,
devclrn,
devpor,
portadataout,
portbdataout
);
// -------- GLOBAL PARAMETERS ---------
parameter operation_mode = "single_port";
parameter mixed_port_feed_through_mode = "dont_care";
parameter ram_block_type = "auto";
parameter logical_ram_name = "ram_name";
parameter init_file = "init_file.hex";
parameter init_file_layout = "none";
parameter data_interleave_width_in_bits = 1;
parameter data_interleave_offset_in_bits = 1;
parameter port_a_logical_ram_depth = 0;
parameter port_a_logical_ram_width = 0;
parameter port_a_first_address = 0;
parameter port_a_last_address = 0;
parameter port_a_first_bit_number = 0;
parameter port_a_data_out_clear = "none";
parameter port_a_data_out_clock = "none";
parameter port_a_data_width = 1;
parameter port_a_address_width = 1;
parameter port_a_byte_enable_mask_width = 1;
parameter port_b_logical_ram_depth = 0;
parameter port_b_logical_ram_width = 0;
parameter port_b_first_address = 0;
parameter port_b_last_address = 0;
parameter port_b_first_bit_number = 0;
parameter port_b_data_in_clear = "none";
parameter port_b_address_clear = "none";
parameter port_b_read_enable_write_enable_clear = "none";
parameter port_b_byte_enable_clear = "none";
parameter port_b_data_out_clear = "none";
parameter port_b_data_in_clock = "clock1";
parameter port_b_address_clock = "clock1";
parameter port_b_read_enable_write_enable_clock = "clock1";
parameter port_b_byte_enable_clock = "clock1";
parameter port_b_data_out_clock = "none";
parameter port_b_data_width = 1;
parameter port_b_address_width = 1;
parameter port_b_byte_enable_mask_width = 1;
parameter power_up_uninitialized = "false";
parameter lpm_type = "cyclone_ram_block";
parameter lpm_hint = "true";
parameter connectivity_checking = "off";
parameter mem_init0 = 2048'b0;
parameter mem_init1 = 2560'b0;
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter port_a_data_in_clear = "none";
parameter port_a_address_clear = "none";
parameter port_a_write_enable_clear = "none";
parameter port_a_byte_enable_clear = "none";
parameter port_a_data_in_clock = "clock0";
parameter port_a_address_clock = "clock0";
parameter port_a_write_enable_clock = "clock0";
parameter port_a_byte_enable_clock = "clock0";
// SIMULATION_ONLY_PARAMETERS_END
// LOCAL_PARAMETERS_BEGIN
parameter primary_port_is_a = (port_b_data_width <= port_a_data_width) ? 1'b1 : 1'b0;
parameter primary_port_is_b = ~primary_port_is_a;
parameter mode_is_rom_or_sp = ((operation_mode == "rom") || (operation_mode == "single_port")) ? 1'b1 : 1'b0;
parameter data_width = (primary_port_is_a) ? port_a_data_width : port_b_data_width;
parameter data_unit_width = (mode_is_rom_or_sp | primary_port_is_b) ? port_a_data_width : port_b_data_width;
parameter address_width = (mode_is_rom_or_sp | primary_port_is_b) ? port_a_address_width : port_b_address_width;
parameter address_unit_width = (mode_is_rom_or_sp | primary_port_is_a) ? port_a_address_width : port_b_address_width;
parameter wired_mode = ((port_a_address_width == 1) && (port_a_address_width == port_b_address_width)
&& (port_a_data_width != port_b_data_width));
parameter num_rows = 1 << address_unit_width;
parameter num_cols = (mode_is_rom_or_sp) ? 1 : ( wired_mode ? 2 :
( (primary_port_is_a) ?
1 << (port_b_address_width - port_a_address_width) :
1 << (port_a_address_width - port_b_address_width) ) ) ;
parameter mask_width_prime = (primary_port_is_a) ?
port_a_byte_enable_mask_width : port_b_byte_enable_mask_width;
parameter mask_width_sec = (primary_port_is_a) ?
port_b_byte_enable_mask_width : port_a_byte_enable_mask_width;
parameter byte_size_a = port_a_data_width/port_a_byte_enable_mask_width;
parameter byte_size_b = port_b_data_width/port_b_byte_enable_mask_width;
parameter mode_is_dp = (operation_mode == "dual_port") ? 1'b1 : 1'b0;
// LOCAL_PARAMETERS_END
// -------- PORT DECLARATIONS ---------
input portawe;
input [port_a_data_width - 1:0] portadatain;
input [port_a_address_width - 1:0] portaaddr;
input [port_a_byte_enable_mask_width - 1:0] portabyteenamasks;
input portbrewe;
input [port_b_data_width - 1:0] portbdatain;
input [port_b_address_width - 1:0] portbaddr;
input [port_b_byte_enable_mask_width - 1:0] portbbyteenamasks;
input clr0,clr1;
input clk0,clk1;
input ena0,ena1;
input devclrn,devpor;
output [port_a_data_width - 1:0] portadataout;
output [port_b_data_width - 1:0] portbdataout;
tri0 portawe_int;
assign portawe_int = portawe;
tri0 [port_a_data_width - 1:0] portadatain_int;
assign portadatain_int = portadatain;
tri0 [port_a_address_width - 1:0] portaaddr_int;
assign portaaddr_int = portaaddr;
tri1 [port_a_byte_enable_mask_width - 1:0] portabyteenamasks_int;
assign portabyteenamasks_int = portabyteenamasks;
tri0 portbrewe_int;
assign portbrewe_int = portbrewe;
tri0 [port_b_data_width - 1:0] portbdatain_int;
assign portbdatain_int = portbdatain;
tri0 [port_b_address_width - 1:0] portbaddr_int;
assign portbaddr_int = portbaddr;
tri1 [port_b_byte_enable_mask_width - 1:0] portbbyteenamasks_int;
assign portbbyteenamasks_int = portbbyteenamasks;
tri0 clr0_int,clr1_int;
assign clr0_int = clr0;
assign clr1_int = clr1;
tri0 clk0_int,clk1_int;
assign clk0_int = clk0;
assign clk1_int = clk1;
tri1 ena0_int,ena1_int;
assign ena0_int = ena0;
assign ena1_int = ena1;
tri1 devclrn;
tri1 devpor;
// -------- INTERNAL signals ---------
// clock / clock enable
wire clk_a_in,clk_a_byteena,clk_a_out,clkena_a_out;
wire clk_b_in,clk_b_byteena,clk_b_out,clkena_b_out;
wire write_cycle_a,write_cycle_b;
// asynch clear
wire datain_a_clr,dataout_a_clr,datain_b_clr,dataout_b_clr;
wire addr_a_clr,addr_b_clr;
wire byteena_a_clr,byteena_b_clr;
wire we_a_clr,rewe_b_clr;
wire datain_a_clr_in,datain_b_clr_in;
wire addr_a_clr_in,addr_b_clr_in;
wire byteena_a_clr_in,byteena_b_clr_in;
wire we_a_clr_in,rewe_b_clr_in;
reg mem_invalidate;
wire [`PRIME:`SEC] clear_asserted_during_write;
reg clear_asserted_during_write_a,clear_asserted_during_write_b;
// port A registers
wire we_a_reg;
wire [port_a_address_width - 1:0] addr_a_reg;
wire [port_a_data_width - 1:0] datain_a_reg, dataout_a_reg;
reg [port_a_data_width - 1:0] dataout_a;
wire [port_a_byte_enable_mask_width - 1:0] byteena_a_reg;
reg out_a_is_reg;
// port B registers
wire rewe_b_reg;
wire [port_b_address_width - 1:0] addr_b_reg;
wire [port_b_data_width - 1:0] datain_b_reg, dataout_b_reg;
reg [port_b_data_width - 1:0] dataout_b;
wire [port_b_byte_enable_mask_width - 1:0] byteena_b_reg;
reg out_b_is_reg;
// placeholders for read/written data
reg [data_width - 1:0] read_data_latch;
reg [data_width - 1:0] mem_data;
reg [data_width - 1:0] old_mem_data;
reg [data_unit_width - 1:0] read_unit_data_latch;
reg [data_width - 1:0] mem_unit_data;
// pulses for A/B ports
wire write_pulse_a,write_pulse_b;
wire read_pulse_a,read_pulse_b;
wire read_pulse_a_feedthru,read_pulse_b_feedthru;
wire [address_unit_width - 1:0] addr_prime_reg; // registered address
wire [address_width - 1:0] addr_sec_reg;
wire [data_width - 1:0] datain_prime_reg; // registered data
wire [data_unit_width - 1:0] datain_sec_reg;
// pulses for primary/secondary ports
wire write_pulse_prime,write_pulse_sec;
wire read_pulse_prime,read_pulse_sec;
wire read_pulse_prime_feedthru,read_pulse_sec_feedthru;
reg [`PRIME:`SEC] dual_write; // simultaneous write to same location
// (row,column) coordinates
reg [address_unit_width - 1:0] row_sec;
reg [address_width + data_unit_width - address_unit_width - 1:0] col_sec;
// memory core
reg [data_width - 1:0] mem [num_rows - 1:0];
// byte enable
wire [data_width - 1:0] mask_vector_prime, mask_vector_prime_int;
wire [data_unit_width - 1:0] mask_vector_sec, mask_vector_sec_int;
reg [data_unit_width - 1:0] mask_vector_common_int;
reg [port_a_data_width - 1:0] mask_vector_a, mask_vector_a_int;
reg [port_b_data_width - 1:0] mask_vector_b, mask_vector_b_int;
// memory initialization
integer i,j,k,l;
integer addr_range_init;
reg [data_width - 1:0] init_mem_word;
reg [(port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1:0] mem_init;
// port active for read/write
wire active_a, active_b;
wire active_a_in, active_b_in;
wire active_write_a,active_write_b,active_write_clear_a,active_write_clear_b;
reg mode_is_rom,mode_is_sp,mode_is_bdp; // ram mode
reg ram_type; // ram type eg. MRAM
initial
begin
ram_type = (ram_block_type == "M-RAM" || ram_block_type == "m-ram" || ram_block_type == "MegaRAM" ||
(ram_block_type == "auto" && mixed_port_feed_through_mode == "dont_care" && port_b_read_enable_write_enable_clock == "clock0"));
mode_is_rom = (operation_mode == "rom");
mode_is_sp = (operation_mode == "single_port");
mode_is_bdp = (operation_mode == "bidir_dual_port");
out_a_is_reg = (port_a_data_out_clock == "none") ? 1'b0 : 1'b1;
out_b_is_reg = (port_b_data_out_clock == "none") ? 1'b0 : 1'b1;
// powerup output latches to 0
dataout_a = 'b0;
if (mode_is_dp || mode_is_bdp) dataout_b = 'b0;
for (i = 0; i < num_rows; i = i + 1) mem[i] = 'b0;
if ((init_file_layout == "port_a") || (init_file_layout == "port_b"))
begin
mem_init = {mem_init1,mem_init0};
addr_range_init = (primary_port_is_a) ?
port_a_last_address - port_a_first_address + 1 :
port_b_last_address - port_b_first_address + 1 ;
for (j = 0; j < addr_range_init; j = j + 1)
begin
for (k = 0; k < data_width; k = k + 1)
init_mem_word[k] = mem_init[j*data_width + k];
mem[j] = init_mem_word;
end
end
dual_write = 'b0;
end
assign clk_a_in = clk0_int;
assign clk_a_byteena = (port_a_byte_enable_clock == "none") ? 1'b0 : clk_a_in;
assign clk_a_out = (port_a_data_out_clock == "none") ? 1'b0 : (
(port_a_data_out_clock == "clock0") ? clk0_int : clk1_int);
assign clk_b_in = (port_b_read_enable_write_enable_clock == "clock0") ? clk0_int : clk1_int;
assign clk_b_byteena = (port_b_byte_enable_clock == "none") ? 1'b0 : (
(port_b_byte_enable_clock == "clock0") ? clk0_int : clk1_int);
assign clk_b_out = (port_b_data_out_clock == "none") ? 1'b0 : (
(port_b_data_out_clock == "clock0") ? clk0_int : clk1_int);
assign addr_a_clr_in = (port_a_address_clear == "none") ? 1'b0 : clr0_int;
assign addr_b_clr_in = (port_b_address_clear == "none") ? 1'b0 : (
(port_b_address_clear == "clear0") ? clr0_int : clr1_int);
assign datain_a_clr_in = (port_a_data_in_clear == "none") ? 1'b0 : clr0_int;
assign dataout_a_clr = (port_a_data_out_clear == "none") ? 1'b0 : (
(port_a_data_out_clear == "clear0") ? clr0_int : clr1_int);
assign datain_b_clr_in = (port_b_data_in_clear == "none") ? 1'b0 : (
(port_b_data_in_clear == "clear0") ? clr0_int : clr1_int);
assign dataout_b_clr = (port_b_data_out_clear == "none") ? 1'b0 : (
(port_b_data_out_clear == "clear0") ? clr0_int : clr1_int);
assign byteena_a_clr_in = (port_a_byte_enable_clear == "none") ? 1'b0 : clr0_int;
assign byteena_b_clr_in = (port_b_byte_enable_clear == "none") ? 1'b0 : (
(port_b_byte_enable_clear == "clear0") ? clr0_int : clr1_int);
assign we_a_clr_in = (port_a_write_enable_clear == "none") ? 1'b0 : clr0_int;
assign rewe_b_clr_in = (port_b_read_enable_write_enable_clear == "none") ? 1'b0 : (
(port_b_read_enable_write_enable_clear == "clear0") ? clr0_int : clr1_int);
assign active_a_in = ena0_int;
assign active_b_in = (port_b_read_enable_write_enable_clock == "clock0") ? ena0_int : ena1_int;
// Store clock enable value for SEAB/MEAB
// port A active
cyclone_ram_register active_port_a (
.d(active_a_in),
.clk(clk_a_in),
.aclr(1'b0),
.devclrn(1'b1),
.devpor(1'b1),
.ena(1'b1),
.q(active_a),.aclrout()
);
defparam active_port_a.width = 1;
assign active_write_a = active_a && (byteena_a_reg !== 'b0);
// port B active
cyclone_ram_register active_port_b (
.d(active_b_in),
.clk(clk_b_in),
.aclr(1'b0),
.devclrn(1'b1),
.devpor(1'b1),
.ena(1'b1),
.q(active_b),.aclrout()
);
defparam active_port_b.width = 1;
assign active_write_b = active_b && (byteena_b_reg !== 'b0);
// ------- A input registers -------
// write enable
cyclone_ram_register we_a_register (
.d(mode_is_rom ? 1'b0 : portawe_int),
.clk(clk_a_in),
.aclr(we_a_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_a_in),
.q(we_a_reg),
.aclrout(we_a_clr)
);
defparam we_a_register.width = 1;
// address
cyclone_ram_register addr_a_register (
.d(portaaddr_int),
.clk(clk_a_in),
.aclr(addr_a_clr_in),
.devclrn(devclrn),.devpor(devpor),
.ena(active_a_in),
.q(addr_a_reg),
.aclrout(addr_a_clr)
);
defparam addr_a_register.width = port_a_address_width;
// data
cyclone_ram_register datain_a_register (
.d(portadatain_int),
.clk(clk_a_in),
.aclr(datain_a_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_a_in),
.q(datain_a_reg),
.aclrout(datain_a_clr)
);
defparam datain_a_register.width = port_a_data_width;
// byte enable
cyclone_ram_register byteena_a_register (
.d(portabyteenamasks_int),
.clk(clk_a_byteena),
.aclr(byteena_a_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_a_in),
.q(byteena_a_reg),
.aclrout(byteena_a_clr)
);
defparam byteena_a_register.width = port_a_byte_enable_mask_width;
defparam byteena_a_register.preset = 1'b1;
// ------- B input registers -------
// read/write enable
cyclone_ram_register rewe_b_register (
.d(portbrewe_int),
.clk(clk_b_in),
.aclr(rewe_b_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_b_in),
.q(rewe_b_reg),
.aclrout(rewe_b_clr)
);
defparam rewe_b_register.width = 1;
defparam rewe_b_register.preset = mode_is_dp;
// address
cyclone_ram_register addr_b_register (
.d(portbaddr_int),
.clk(clk_b_in),
.aclr(addr_b_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_b_in),
.q(addr_b_reg),
.aclrout(addr_b_clr)
);
defparam addr_b_register.width = port_b_address_width;
// data
cyclone_ram_register datain_b_register (
.d(portbdatain_int),
.clk(clk_b_in),
.aclr(datain_b_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_b_in),
.q(datain_b_reg),
.aclrout(datain_b_clr)
);
defparam datain_b_register.width = port_b_data_width;
// byte enable
cyclone_ram_register byteena_b_register (
.d(portbbyteenamasks_int),
.clk(clk_b_byteena),
.aclr(byteena_b_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_b_in),
.q(byteena_b_reg),
.aclrout(byteena_b_clr)
);
defparam byteena_b_register.width = port_b_byte_enable_mask_width;
defparam byteena_b_register.preset = 1'b1;
assign datain_prime_reg = (primary_port_is_a) ? datain_a_reg : datain_b_reg;
assign addr_prime_reg = (primary_port_is_a) ? addr_a_reg : addr_b_reg;
assign datain_sec_reg = (primary_port_is_a) ? datain_b_reg : datain_a_reg;
assign addr_sec_reg = (primary_port_is_a) ? addr_b_reg : addr_a_reg;
assign mask_vector_prime = (primary_port_is_a) ? mask_vector_a : mask_vector_b;
assign mask_vector_prime_int = (primary_port_is_a) ? mask_vector_a_int : mask_vector_b_int;
assign mask_vector_sec = (primary_port_is_a) ? mask_vector_b : mask_vector_a;
assign mask_vector_sec_int = (primary_port_is_a) ? mask_vector_b_int : mask_vector_a_int;
// Write pulse generation
cyclone_ram_pulse_generator wpgen_a (
.clk(ram_type ? clk_a_in : ~clk_a_in),
.ena(active_write_a & we_a_reg),
.pulse(write_pulse_a),
.cycle(write_cycle_a)
);
cyclone_ram_pulse_generator wpgen_b (
.clk(ram_type ? clk_b_in : ~clk_b_in),
.ena(active_write_b & mode_is_bdp & rewe_b_reg),
.pulse(write_pulse_b),
.cycle(write_cycle_b)
);
// Read pulse generation
cyclone_ram_pulse_generator rpgen_a (
.clk(clk_a_in),
.ena(active_a & ~we_a_reg),
.pulse(read_pulse_a),
.cycle()
);
cyclone_ram_pulse_generator rpgen_b (
.clk(clk_b_in),
.ena(active_b & (mode_is_dp ? rewe_b_reg : ~rewe_b_reg)),
.pulse(read_pulse_b),
.cycle()
);
assign write_pulse_prime = (primary_port_is_a) ? write_pulse_a : write_pulse_b;
assign read_pulse_prime = (primary_port_is_a) ? read_pulse_a : read_pulse_b;
assign read_pulse_prime_feedthru = (primary_port_is_a) ? read_pulse_a_feedthru : read_pulse_b_feedthru;
assign write_pulse_sec = (primary_port_is_a) ? write_pulse_b : write_pulse_a;
assign read_pulse_sec = (primary_port_is_a) ? read_pulse_b : read_pulse_a;
assign read_pulse_sec_feedthru = (primary_port_is_a) ? read_pulse_b_feedthru : read_pulse_a_feedthru;
// Create internal masks for byte enable processing
always @(byteena_a_reg)
begin
for (i = 0; i < port_a_data_width; i = i + 1)
begin
mask_vector_a[i] = (byteena_a_reg[i/byte_size_a] === 1'b1) ? 1'b0 : 1'bx;
mask_vector_a_int[i] = (byteena_a_reg[i/byte_size_a] === 1'b0) ? 1'b0 : 1'bx;
end
end
always @(byteena_b_reg)
begin
for (l = 0; l < port_b_data_width; l = l + 1)
begin
mask_vector_b[l] = (byteena_b_reg[l/byte_size_b] === 1'b1) ? 1'b0 : 1'bx;
mask_vector_b_int[l] = (byteena_b_reg[l/byte_size_b] === 1'b0) ? 1'b0 : 1'bx;
end
end
always @(posedge write_pulse_prime or posedge write_pulse_sec or
posedge read_pulse_prime or posedge read_pulse_sec
)
begin
// Write stage 1 : write X to memory
if (write_pulse_prime)
begin
old_mem_data = mem[addr_prime_reg];
mem_data = mem[addr_prime_reg] ^ mask_vector_prime_int;
mem[addr_prime_reg] = mem_data;
end
if (write_pulse_sec)
begin
row_sec = addr_sec_reg / num_cols; col_sec = (addr_sec_reg % num_cols) * data_unit_width;
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
mem_unit_data[j] = mem_unit_data[j] ^ mask_vector_sec_int[j - col_sec];
mem[row_sec] = mem_unit_data;
end
if ((addr_prime_reg == row_sec) && write_pulse_prime && write_pulse_sec) dual_write = 2'b11;
// Read stage 1 : read data from memory
if (read_pulse_prime)
read_data_latch = mem[addr_prime_reg];
if (read_pulse_sec)
begin
row_sec = addr_sec_reg / num_cols; col_sec = (addr_sec_reg % num_cols) * data_unit_width;
if ((row_sec == addr_prime_reg) && (write_pulse_prime))
mem_unit_data = old_mem_data;
else
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
read_unit_data_latch[j - col_sec] = mem_unit_data[j];
end
end
// Simultaneous write to same/overlapping location by both ports
always @(dual_write)
begin
if (dual_write == 2'b11)
begin
for (i = 0; i < data_unit_width; i = i + 1)
mask_vector_common_int[i] = mask_vector_prime_int[col_sec + i] &
mask_vector_sec_int[i];
end
else if (dual_write == 2'b01) mem_unit_data = mem[row_sec];
else if (dual_write == 'b0)
begin
mem_data = mem[addr_prime_reg];
for (i = 0; i < data_unit_width; i = i + 1)
mem_data[col_sec + i] = mem_data[col_sec + i] ^ mask_vector_common_int[i];
mem[addr_prime_reg] = mem_data;
end
end
// Write stage 2 : Write actual data to memory
always @(negedge write_pulse_prime)
begin
if (clear_asserted_during_write[`PRIME] !== 1'b1)
begin
for (i = 0; i < data_width; i = i + 1)
if (mask_vector_prime[i] == 1'b0)
mem_data[i] = datain_prime_reg[i];
mem[addr_prime_reg] = mem_data;
end
dual_write[`PRIME] = 1'b0;
end
always @(negedge write_pulse_sec)
begin
if (clear_asserted_during_write[`SEC] !== 1'b1)
begin
for (i = 0; i < data_unit_width; i = i + 1)
if (mask_vector_sec[i] == 1'b0)
mem_unit_data[col_sec + i] = datain_sec_reg[i];
mem[row_sec] = mem_unit_data;
end
dual_write[`SEC] = 1'b0;
end
// Read stage 2 : Send data to output
always @(negedge read_pulse_prime)
begin
if (primary_port_is_a)
dataout_a = read_data_latch;
else
dataout_b = read_data_latch;
end
always @(negedge read_pulse_sec)
begin
if (primary_port_is_b)
dataout_a = read_unit_data_latch;
else
dataout_b = read_unit_data_latch;
end
// Same port feed through
cyclone_ram_pulse_generator ftpgen_a (
.clk(clk_a_in),
.ena(active_a & ~mode_is_dp & we_a_reg),
.pulse(read_pulse_a_feedthru),.cycle()
);
cyclone_ram_pulse_generator ftpgen_b (
.clk(clk_b_in),
.ena(active_b & mode_is_bdp & rewe_b_reg),
.pulse(read_pulse_b_feedthru),.cycle()
);
always @(negedge read_pulse_prime_feedthru)
begin
if (primary_port_is_a)
dataout_a = datain_prime_reg ^ mask_vector_prime;
else
dataout_b = datain_prime_reg ^ mask_vector_prime;
end
always @(negedge read_pulse_sec_feedthru)
begin
if (primary_port_is_b)
dataout_a = datain_sec_reg ^ mask_vector_sec;
else
dataout_b = datain_sec_reg ^ mask_vector_sec;
end
// Input register clears
always @(posedge addr_a_clr or posedge datain_a_clr or posedge we_a_clr)
clear_asserted_during_write_a = write_pulse_a;
assign active_write_clear_a = active_write_a & write_cycle_a;
always @(posedge addr_a_clr)
begin
if (active_write_clear_a & we_a_reg)
mem_invalidate = 1'b1;
else if (active_a & ~we_a_reg)
begin
if (primary_port_is_a)
begin
read_data_latch = 'bx;
end
else
begin
read_unit_data_latch = 'bx;
end
dataout_a = 'bx;
end
end
always @(posedge datain_a_clr or posedge we_a_clr)
begin
if (active_write_clear_a & we_a_reg)
begin
if (primary_port_is_a)
mem[addr_prime_reg] = 'bx;
else
begin
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
mem_unit_data[j] = 1'bx;
mem[row_sec] = mem_unit_data;
end
if (primary_port_is_a)
begin
read_data_latch = 'bx;
end
else
begin
read_unit_data_latch = 'bx;
end
end
end
assign active_write_clear_b = active_write_b & write_cycle_b;
always @(posedge addr_b_clr or posedge datain_b_clr or
posedge rewe_b_clr)
clear_asserted_during_write_b = write_pulse_b;
always @(posedge addr_b_clr)
begin
if (mode_is_bdp & active_write_clear_b & rewe_b_reg)
mem_invalidate = 1'b1;
else if (active_b & (mode_is_dp & rewe_b_reg || mode_is_bdp & ~rewe_b_reg))
begin
if (primary_port_is_b)
begin
read_data_latch = 'bx;
end
else
begin
read_unit_data_latch = 'bx;
end
dataout_b = 'bx;
end
end
always @(posedge datain_b_clr or posedge rewe_b_clr)
begin
if (mode_is_bdp & active_write_clear_b & rewe_b_reg)
begin
if (primary_port_is_b)
mem[addr_prime_reg] = 'bx;
else
begin
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
mem_unit_data[j] = 'bx;
mem[row_sec] = mem_unit_data;
end
if (primary_port_is_b)
begin
read_data_latch = 'bx;
end
else
begin
read_unit_data_latch = 'bx;
end
end
end
assign clear_asserted_during_write[primary_port_is_a] = clear_asserted_during_write_a;
assign clear_asserted_during_write[primary_port_is_b] = clear_asserted_during_write_b;
always @(posedge mem_invalidate)
begin
for (i = 0; i < num_rows; i = i + 1) mem[i] = 'bx;
mem_invalidate = 1'b0;
end
// ------- Output registers --------
assign clkena_a_out = (port_a_data_out_clock == "clock0") ? ena0_int : ena1_int;
cyclone_ram_register dataout_a_register (
.d(dataout_a),
.clk(clk_a_out),
.aclr(dataout_a_clr),
.devclrn(devclrn),
.devpor(devpor),
.ena(clkena_a_out),
.q(dataout_a_reg),.aclrout()
);
defparam dataout_a_register.width = port_a_data_width;
assign portadataout = (out_a_is_reg) ? dataout_a_reg : dataout_a;
assign clkena_b_out = (port_b_data_out_clock == "clock0") ? ena0_int : ena1_int;
cyclone_ram_register dataout_b_register (
.d( dataout_b ),
.clk(clk_b_out),
.aclr(dataout_b_clr),
.devclrn(devclrn),.devpor(devpor),
.ena(clkena_b_out),
.q(dataout_b_reg),.aclrout()
);
defparam dataout_b_register.width = port_b_data_width;
assign portbdataout = (out_b_is_reg) ? dataout_b_reg : dataout_b;
endmodule // cyclone_ram_block
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : cyclone_m_cntr
//
// Description : Timing simulation model for the M counter. This is the
// loop feedback counter for the Cyclone PLL.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module cyclone_m_cntr (clk,
reset,
cout,
initial_value,
modulus,
time_delay);
// INPUT PORTS
input clk;
input reset;
input [31:0] initial_value;
input [31:0] modulus;
input [31:0] time_delay;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg cout_tmp;
initial
begin
count = 1;
first_rising_edge = 1;
clk_last_value = 0;
end
always @(reset or clk)
begin
if (reset)
begin
count = 1;
tmp_cout = 0;
first_rising_edge = 1;
end
else begin
if (clk_last_value !== clk)
begin
if (clk === 1'b1 && first_rising_edge)
begin
first_rising_edge = 0;
tmp_cout = clk;
end
else if (first_rising_edge == 0)
begin
if (count < modulus)
count = count + 1;
else
begin
count = 1;
tmp_cout = ~tmp_cout;
end
end
end
end
clk_last_value = clk;
cout_tmp <= #(time_delay) tmp_cout;
end
and (cout, cout_tmp, 1'b1);
endmodule // cyclone_m_cntr
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : cyclone_n_cntr
//
// Description : Timing simulation model for the N counter. This is the
// input clock divide counter for the Cyclone PLL.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module cyclone_n_cntr (clk,
reset,
cout,
modulus,
time_delay);
// INPUT PORTS
input clk;
input reset;
input [31:0] modulus;
input [31:0] time_delay;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg clk_last_valid_value;
reg cout_tmp;
initial
begin
count = 1;
first_rising_edge = 1;
clk_last_value = 0;
end
always @(reset or clk)
begin
if (reset)
begin
count = 1;
tmp_cout = 0;
first_rising_edge = 1;
end
else begin
if (clk_last_value !== clk)
begin
if (clk === 1'bx)
begin
$display("Warning : Invalid transition to 'X' detected on PLL input clk. This edge will be ignored.");
$display("Time: %0t Instance: %m", $time);
end
else if ((clk === 1'b1) && first_rising_edge)
begin
first_rising_edge = 0;
tmp_cout = clk;
end
else if ((first_rising_edge == 0) && (clk_last_valid_value !== clk))
begin
if (count < modulus)
count = count + 1;
else
begin
count = 1;
tmp_cout = ~tmp_cout;
end
end
end
end
clk_last_value = clk;
if (clk !== 1'bx)
clk_last_valid_value = clk;
cout_tmp <= #(time_delay) tmp_cout;
end
and (cout, cout_tmp, 1'b1);
endmodule // cyclone_n_cntr
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : cyclone_scale_cntr
//
// Description : Timing simulation model for the output scale-down counters.
// This is a common model for the L0, L1, G0, G1, G2, G3, E0,
// E1, E2 and E3 output counters of the Cyclone PLL.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module cyclone_scale_cntr (clk,
reset,
cout,
high,
low,
initial_value,
mode,
time_delay,
ph_tap);
// INPUT PORTS
input clk;
input reset;
input [31:0] high;
input [31:0] low;
input [31:0] initial_value;
input [8*6:1] mode;
input [31:0] time_delay;
input [31:0] ph_tap;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg init;
integer count;
integer output_shift_count;
reg cout_tmp;
reg [31:0] high_reg;
reg [31:0] low_reg;
reg high_cnt_xfer_done;
initial
begin
count = 1;
first_rising_edge = 0;
tmp_cout = 0;
output_shift_count = 0;
high_cnt_xfer_done = 0;
end
always @(clk or reset)
begin
if (init !== 1'b1)
begin
high_reg = high;
low_reg = low;
clk_last_value = 0;
init = 1'b1;
end
if (reset)
begin
count = 1;
output_shift_count = 0;
tmp_cout = 0;
first_rising_edge = 0;
end
else if (clk_last_value !== clk)
begin
if (mode == "off")
tmp_cout = 0;
else if (mode == "bypass")
tmp_cout = clk;
else if (first_rising_edge == 0)
begin
if (clk == 1)
begin
output_shift_count = output_shift_count + 1;
if (output_shift_count == initial_value)
begin
tmp_cout = clk;
first_rising_edge = 1;
end
end
end
else if (output_shift_count < initial_value)
begin
if (clk == 1)
output_shift_count = output_shift_count + 1;
end
else
begin
count = count + 1;
if (mode == "even" && (count == (high_reg*2) + 1))
begin
tmp_cout = 0;
if (high_cnt_xfer_done === 1'b1)
begin
low_reg = low;
high_cnt_xfer_done = 0;
end
end
else if (mode == "odd" && (count == (high_reg*2)))
begin
tmp_cout = 0;
if (high_cnt_xfer_done === 1'b1)
begin
low_reg = low;
high_cnt_xfer_done = 0;
end
end
else if (count == (high_reg + low_reg)*2 + 1)
begin
tmp_cout = 1;
count = 1; // reset count
if (high_reg != high)
begin
high_reg = high;
high_cnt_xfer_done = 1;
end
end
end
end
clk_last_value = clk;
cout_tmp <= #(time_delay) tmp_cout;
end
and (cout, cout_tmp, 1'b1);
endmodule // cyclone_scale_cntr
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : cyclone_pll_reg
//
// Description : Simulation model for a simple DFF.
// This is required for the generation of the bit slip-signals.
// No timing, powers upto 0.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps / 1ps
module cyclone_pll_reg (q,
clk,
ena,
d,
clrn,
prn);
// INPUT PORTS
input d;
input clk;
input clrn;
input prn;
input ena;
// OUTPUT PORTS
output q;
// INTERNAL VARIABLES
reg q;
// DEFAULT VALUES THRO' PULLUPs
tri1 prn, clrn, ena;
initial q = 0;
always @ (posedge clk or negedge clrn or negedge prn )
begin
if (prn == 1'b0)
q <= 1;
else if (clrn == 1'b0)
q <= 0;
else if ((clk == 1) & (ena == 1'b1))
q <= d;
end
endmodule // cyclone_pll_reg
//////////////////////////////////////////////////////////////////////////////
//
// Module Name : cyclone_pll
//
// Description : Timing simulation model for the Cyclone StratixGX PLL.
// In the functional mode, it is also the model for the altpll
// megafunction.
//
// Limitations : Does not support Spread Spectrum and Bandwidth.
//
// Outputs : Up to 10 output clocks, each defined by its own set of
// parameters. Locked output (active high) indicates when the
// PLL locks. clkbad, clkloss and activeclock are used for
// clock switchover to indicate which input clock has gone
// bad, when the clock switchover initiates and which input
// clock is being used as the reference, respectively.
// scandataout is the data output of the serial scan chain.
//
//////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
`define WORD_LENGTH 18
module cyclone_pll (inclk,
fbin,
ena,
clkswitch,
areset,
pfdena,
clkena,
extclkena,
scanclk,
scanaclr,
scandata,
clk,
extclk,
clkbad,
activeclock,
locked,
clkloss,
scandataout,
// lvds mode specific ports
comparator,
enable0,
enable1);
parameter operation_mode = "normal";
parameter qualify_conf_done = "off";
parameter compensate_clock = "clk0";
parameter pll_type = "auto";
parameter scan_chain = "long";
parameter lpm_type = "cyclone_pll";
parameter clk0_multiply_by = 1;
parameter clk0_divide_by = 1;
parameter clk0_phase_shift = 0;
parameter clk0_time_delay = 0;
parameter clk0_duty_cycle = 50;
parameter clk1_multiply_by = 1;
parameter clk1_divide_by = 1;
parameter clk1_phase_shift = 0;
parameter clk1_time_delay = 0;
parameter clk1_duty_cycle = 50;
parameter clk2_multiply_by = 1;
parameter clk2_divide_by = 1;
parameter clk2_phase_shift = 0;
parameter clk2_time_delay = 0;
parameter clk2_duty_cycle = 50;
parameter clk3_multiply_by = 1;
parameter clk3_divide_by = 1;
parameter clk3_phase_shift = 0;
parameter clk3_time_delay = 0;
parameter clk3_duty_cycle = 50;
parameter clk4_multiply_by = 1;
parameter clk4_divide_by = 1;
parameter clk4_phase_shift = 0;
parameter clk4_time_delay = 0;
parameter clk4_duty_cycle = 50;
parameter clk5_multiply_by = 1;
parameter clk5_divide_by = 1;
parameter clk5_phase_shift = 0;
parameter clk5_time_delay = 0;
parameter clk5_duty_cycle = 50;
parameter extclk0_multiply_by = 1;
parameter extclk0_divide_by = 1;
parameter extclk0_phase_shift = 0;
parameter extclk0_time_delay = 0;
parameter extclk0_duty_cycle = 50;
parameter extclk1_multiply_by = 1;
parameter extclk1_divide_by = 1;
parameter extclk1_phase_shift = 0;
parameter extclk1_time_delay = 0;
parameter extclk1_duty_cycle = 50;
parameter extclk2_multiply_by = 1;
parameter extclk2_divide_by = 1;
parameter extclk2_phase_shift = 0;
parameter extclk2_time_delay = 0;
parameter extclk2_duty_cycle = 50;
parameter extclk3_multiply_by = 1;
parameter extclk3_divide_by = 1;
parameter extclk3_phase_shift = 0;
parameter extclk3_time_delay = 0;
parameter extclk3_duty_cycle = 50;
parameter primary_clock = "inclk0";
parameter inclk0_input_frequency = 10000;
parameter inclk1_input_frequency = 10000;
parameter gate_lock_signal = "no";
parameter gate_lock_counter = 1;
parameter valid_lock_multiplier = 5;
parameter invalid_lock_multiplier = 5;
parameter switch_over_on_lossclk = "off";
parameter switch_over_on_gated_lock = "off";
parameter switch_over_counter = 1;
parameter enable_switch_over_counter = "off";
parameter feedback_source = "extclk0";
parameter bandwidth = 0;
parameter bandwidth_type = "auto";
parameter spread_frequency = 0;
parameter common_rx_tx = "off";
parameter rx_outclock_resource = "auto";
parameter use_vco_bypass = "false";
parameter use_dc_coupling = "false";
parameter pfd_min = 0;
parameter pfd_max = 0;
parameter vco_min = 0;
parameter vco_max = 0;
parameter vco_center = 0;
// ADVANCED USE PARAMETERS
parameter m_initial = 1;
parameter m = 0;
parameter n = 1;
parameter m2 = 1;
parameter n2 = 1;
parameter ss = 0;
parameter l0_high = 1;
parameter l0_low = 1;
parameter l0_initial = 1;
parameter l0_mode = "bypass";
parameter l0_ph = 0;
parameter l0_time_delay = 0;
parameter l1_high = 1;
parameter l1_low = 1;
parameter l1_initial = 1;
parameter l1_mode = "bypass";
parameter l1_ph = 0;
parameter l1_time_delay = 0;
parameter g0_high = 1;
parameter g0_low = 1;
parameter g0_initial = 1;
parameter g0_mode = "bypass";
parameter g0_ph = 0;
parameter g0_time_delay = 0;
parameter g1_high = 1;
parameter g1_low = 1;
parameter g1_initial = 1;
parameter g1_mode = "bypass";
parameter g1_ph = 0;
parameter g1_time_delay = 0;
parameter g2_high = 1;
parameter g2_low = 1;
parameter g2_initial = 1;
parameter g2_mode = "bypass";
parameter g2_ph = 0;
parameter g2_time_delay = 0;
parameter g3_high = 1;
parameter g3_low = 1;
parameter g3_initial = 1;
parameter g3_mode = "bypass";
parameter g3_ph = 0;
parameter g3_time_delay = 0;
parameter e0_high = 1;
parameter e0_low = 1;
parameter e0_initial = 1;
parameter e0_mode = "bypass";
parameter e0_ph = 0;
parameter e0_time_delay = 0;
parameter e1_high = 1;
parameter e1_low = 1;
parameter e1_initial = 1;
parameter e1_mode = "bypass";
parameter e1_ph = 0;
parameter e1_time_delay = 0;
parameter e2_high = 1;
parameter e2_low = 1;
parameter e2_initial = 1;
parameter e2_mode = "bypass";
parameter e2_ph = 0;
parameter e2_time_delay = 0;
parameter e3_high = 1;
parameter e3_low = 1;
parameter e3_initial = 1;
parameter e3_mode = "bypass";
parameter e3_ph = 0;
parameter e3_time_delay = 0;
parameter m_ph = 0;
parameter m_time_delay = 0;
parameter n_time_delay = 0;
parameter extclk0_counter = "e0";
parameter extclk1_counter = "e1";
parameter extclk2_counter = "e2";
parameter extclk3_counter = "e3";
parameter clk0_counter = "g0";
parameter clk1_counter = "g1";
parameter clk2_counter = "g2";
parameter clk3_counter = "g3";
parameter clk4_counter = "l0";
parameter clk5_counter = "l1";
// LVDS mode parameters
parameter enable0_counter = "l0";
parameter enable1_counter = "l0";
parameter charge_pump_current = 0;
parameter loop_filter_r = "1.0";
parameter loop_filter_c = 1;
parameter pll_compensation_delay = 0;
parameter simulation_type = "timing";
parameter source_is_pll = "off";
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter down_spread = "0.0";
parameter clk0_phase_shift_num = 0;
parameter clk1_phase_shift_num = 0;
parameter clk2_phase_shift_num = 0;
parameter family_name = "Cyclone";
parameter skip_vco = "off";
parameter clk0_use_even_counter_mode = "off";
parameter clk1_use_even_counter_mode = "off";
parameter clk2_use_even_counter_mode = "off";
parameter clk3_use_even_counter_mode = "off";
parameter clk4_use_even_counter_mode = "off";
parameter clk5_use_even_counter_mode = "off";
parameter extclk0_use_even_counter_mode = "off";
parameter extclk1_use_even_counter_mode = "off";
parameter extclk2_use_even_counter_mode = "off";
parameter extclk3_use_even_counter_mode = "off";
parameter clk0_use_even_counter_value = "off";
parameter clk1_use_even_counter_value = "off";
parameter clk2_use_even_counter_value = "off";
parameter clk3_use_even_counter_value = "off";
parameter clk4_use_even_counter_value = "off";
parameter clk5_use_even_counter_value = "off";
parameter extclk0_use_even_counter_value = "off";
parameter extclk1_use_even_counter_value = "off";
parameter extclk2_use_even_counter_value = "off";
parameter extclk3_use_even_counter_value = "off";
// SIMULATION_ONLY_PARAMETERS_END
// INPUT PORTS
input [1:0] inclk;
input fbin;
input ena;
input clkswitch;
input areset;
input pfdena;
input [5:0] clkena;
input [3:0] extclkena;
input scanclk;
input scanaclr;
input scandata;
// lvds specific input ports
input comparator;
// OUTPUT PORTS
output [5:0] clk;
output [3:0] extclk;
output [1:0] clkbad;
output activeclock;
output locked;
output clkloss;
output scandataout;
// lvds specific output ports
output enable0;
output enable1;
// BUFFER INPUTS
wire inclk0_ipd;
wire inclk1_ipd;
wire ena_ipd;
wire fbin_ipd;
wire areset_ipd;
wire pfdena_ipd;
wire clkena0_ipd;
wire clkena1_ipd;
wire clkena2_ipd;
wire clkena3_ipd;
wire clkena4_ipd;
wire clkena5_ipd;
wire extclkena0_ipd;
wire extclkena1_ipd;
wire extclkena2_ipd;
wire extclkena3_ipd;
wire scanclk_ipd;
wire scanaclr_ipd;
wire scandata_ipd;
wire comparator_ipd;
wire clkswitch_ipd;
buf (inclk0_ipd, inclk[0]);
buf (inclk1_ipd, inclk[1]);
buf (ena_ipd, ena);
buf (fbin_ipd, fbin);
buf (areset_ipd, areset);
buf (pfdena_ipd, pfdena);
buf (clkena0_ipd, clkena[0]);
buf (clkena1_ipd, clkena[1]);
buf (clkena2_ipd, clkena[2]);
buf (clkena3_ipd, clkena[3]);
buf (clkena4_ipd, clkena[4]);
buf (clkena5_ipd, clkena[5]);
buf (extclkena0_ipd, extclkena[0]);
buf (extclkena1_ipd, extclkena[1]);
buf (extclkena2_ipd, extclkena[2]);
buf (extclkena3_ipd, extclkena[3]);
buf (scanclk_ipd, scanclk);
buf (scanaclr_ipd, scanaclr);
buf (scandata_ipd, scandata);
buf (comparator_ipd, comparator);
buf (clkswitch_ipd, clkswitch);
// INTERNAL VARIABLES AND NETS
integer scan_chain_length;
integer i;
integer j;
integer k;
integer l_index;
integer gate_count;
integer egpp_offset;
integer sched_time;
integer delay_chain;
integer low;
integer high;
integer initial_delay;
integer fbk_phase;
integer fbk_delay;
integer phase_shift[0:7];
integer last_phase_shift[0:7];
integer m_times_vco_period;
integer new_m_times_vco_period;
integer refclk_period;
integer fbclk_period;
integer primary_clock_frequency;
integer high_time;
integer low_time;
integer my_rem;
integer tmp_rem;
integer rem;
integer tmp_vco_per;
integer vco_per;
integer offset;
integer temp_offset;
integer cycles_to_lock;
integer cycles_to_unlock;
integer l0_count;
integer l1_count;
integer loop_xplier;
integer loop_initial;
integer loop_ph;
integer loop_time_delay;
integer cycle_to_adjust;
integer total_pull_back;
integer pull_back_M;
integer pull_back_ext_cntr;
time fbclk_time;
time first_fbclk_time;
time refclk_time;
time scanaclr_rising_time;
time scanaclr_falling_time;
reg got_first_refclk;
reg got_second_refclk;
reg got_first_fbclk;
reg refclk_last_value;
reg fbclk_last_value;
reg inclk_last_value;
reg pll_is_locked;
reg pll_about_to_lock;
reg locked_tmp;
reg l0_got_first_rising_edge;
reg l1_got_first_rising_edge;
reg vco_l0_last_value;
reg vco_l1_last_value;
reg areset_ipd_last_value;
reg ena_ipd_last_value;
reg pfdena_ipd_last_value;
reg inclk_out_of_range;
reg schedule_vco_last_value;
reg gate_out;
reg vco_val;
reg [31:0] m_initial_val;
reg [31:0] m_val;
reg [31:0] m_val_tmp;
reg [31:0] m2_val;
reg [31:0] n_val;
reg [31:0] n_val_tmp;
reg [31:0] n2_val;
reg [31:0] m_time_delay_val;
reg [31:0] n_time_delay_val;
reg [31:0] m_delay;
reg [8*6:1] m_mode_val;
reg [8*6:1] m2_mode_val;
reg [8*6:1] n_mode_val;
reg [8*6:1] n2_mode_val;
reg [31:0] l0_high_val;
reg [31:0] l0_low_val;
reg [31:0] l0_initial_val;
reg [31:0] l0_time_delay_val;
reg [8*6:1] l0_mode_val;
reg [31:0] l1_high_val;
reg [31:0] l1_low_val;
reg [31:0] l1_initial_val;
reg [31:0] l1_time_delay_val;
reg [8*6:1] l1_mode_val;
reg [31:0] g0_high_val;
reg [31:0] g0_low_val;
reg [31:0] g0_initial_val;
reg [31:0] g0_time_delay_val;
reg [8*6:1] g0_mode_val;
reg [31:0] g1_high_val;
reg [31:0] g1_low_val;
reg [31:0] g1_initial_val;
reg [31:0] g1_time_delay_val;
reg [8*6:1] g1_mode_val;
reg [31:0] g2_high_val;
reg [31:0] g2_low_val;
reg [31:0] g2_initial_val;
reg [31:0] g2_time_delay_val;
reg [8*6:1] g2_mode_val;
reg [31:0] g3_high_val;
reg [31:0] g3_low_val;
reg [31:0] g3_initial_val;
reg [31:0] g3_time_delay_val;
reg [8*6:1] g3_mode_val;
reg [31:0] e0_high_val;
reg [31:0] e0_low_val;
reg [31:0] e0_initial_val;
reg [31:0] e0_time_delay_val;
reg [8*6:1] e0_mode_val;
reg [31:0] e1_high_val;
reg [31:0] e1_low_val;
reg [31:0] e1_initial_val;
reg [31:0] e1_time_delay_val;
reg [8*6:1] e1_mode_val;
reg [31:0] e2_high_val;
reg [31:0] e2_low_val;
reg [31:0] e2_initial_val;
reg [31:0] e2_time_delay_val;
reg [8*6:1] e2_mode_val;
reg [31:0] e3_high_val;
reg [31:0] e3_low_val;
reg [31:0] e3_initial_val;
reg [31:0] e3_time_delay_val;
reg [8*6:1] e3_mode_val;
reg scanclk_last_value;
reg scanaclr_last_value;
reg transfer;
reg transfer_enable;
reg [288:0] scan_data;
reg schedule_vco;
reg schedule_offset;
reg stop_vco;
reg inclk_n;
reg [7:0] vco_out;
wire inclk_l0;
wire inclk_l1;
wire inclk_m;
wire clk0_tmp;
wire clk1_tmp;
wire clk2_tmp;
wire clk3_tmp;
wire clk4_tmp;
wire clk5_tmp;
wire extclk0_tmp;
wire extclk1_tmp;
wire extclk2_tmp;
wire extclk3_tmp;
wire nce_l0;
wire nce_l1;
wire nce_temp;
reg vco_l0;
reg vco_l1;
wire clk0;
wire clk1;
wire clk2;
wire clk3;
wire clk4;
wire clk5;
wire extclk0;
wire extclk1;
wire extclk2;
wire extclk3;
wire ena0;
wire ena1;
wire ena2;
wire ena3;
wire ena4;
wire ena5;
wire extena0;
wire extena1;
wire extena2;
wire extena3;
wire refclk;
wire fbclk;
wire l0_clk;
wire l1_clk;
wire g0_clk;
wire g1_clk;
wire g2_clk;
wire g3_clk;
wire e0_clk;
wire e1_clk;
wire e2_clk;
wire e3_clk;
wire dffa_out;
wire dffb_out;
wire dffc_out;
wire dffd_out;
wire lvds_dffb_clk;
wire lvds_dffc_clk;
wire lvds_dffd_clk;
reg first_schedule;
wire enable0_tmp;
wire enable1_tmp;
wire enable_0;
wire enable_1;
reg l0_tmp;
reg l1_tmp;
reg vco_period_was_phase_adjusted;
reg phase_adjust_was_scheduled;
// for external feedback mode
reg [31:0] ext_fbk_cntr_high;
reg [31:0] ext_fbk_cntr_low;
reg [31:0] ext_fbk_cntr_modulus;
reg [31:0] ext_fbk_cntr_delay;
reg [8*2:1] ext_fbk_cntr;
reg [8*6:1] ext_fbk_cntr_mode;
integer ext_fbk_cntr_ph;
integer ext_fbk_cntr_initial;
wire inclk_e0;
wire inclk_e1;
wire inclk_e2;
wire inclk_e3;
wire [31:0] cntr_e0_initial;
wire [31:0] cntr_e1_initial;
wire [31:0] cntr_e2_initial;
wire [31:0] cntr_e3_initial;
wire [31:0] cntr_e0_delay;
wire [31:0] cntr_e1_delay;
wire [31:0] cntr_e2_delay;
wire [31:0] cntr_e3_delay;
reg [31:0] ext_fbk_delay;
// variables for clk_switch
reg clk0_is_bad;
reg clk1_is_bad;
reg inclk0_last_value;
reg inclk1_last_value;
reg other_clock_value;
reg other_clock_last_value;
reg primary_clk_is_bad;
reg current_clk_is_bad;
reg external_switch;
// reg [8*6:1] current_clock;
reg active_clock;
reg clkloss_tmp;
reg got_curr_clk_falling_edge_after_clkswitch;
reg active_clk_was_switched;
integer clk0_count;
integer clk1_count;
integer switch_over_count;
reg scandataout_tmp;
reg scandataout_trigger;
integer quiet_time;
reg pll_in_quiet_period;
time start_quiet_time;
reg quiet_period_violation;
reg reconfig_err;
reg scanclr_violation;
reg scanclr_clk_violation;
reg got_first_scanclk_after_scanclr_inactive_edge;
reg error;
reg no_warn;
// LOCAL_PARAMETERS_BEGIN
parameter EGPP_SCAN_CHAIN = 289;
parameter GPP_SCAN_CHAIN = 193;
parameter TRST = 5000;
parameter TRSTCLK = 5000;
// LOCAL_PARAMETERS_END
// internal variables for scaling of multiply_by and divide_by values
integer i_clk0_mult_by;
integer i_clk0_div_by;
integer i_clk1_mult_by;
integer i_clk1_div_by;
integer i_clk2_mult_by;
integer i_clk2_div_by;
integer i_clk3_mult_by;
integer i_clk3_div_by;
integer i_clk4_mult_by;
integer i_clk4_div_by;
integer i_clk5_mult_by;
integer i_clk5_div_by;
integer i_extclk0_mult_by;
integer i_extclk0_div_by;
integer i_extclk1_mult_by;
integer i_extclk1_div_by;
integer i_extclk2_mult_by;
integer i_extclk2_div_by;
integer i_extclk3_mult_by;
integer i_extclk3_div_by;
integer max_d_value;
integer new_multiplier;
// internal variables for storing the phase shift number.(used in lvds mode only)
integer i_clk0_phase_shift;
integer i_clk1_phase_shift;
integer i_clk2_phase_shift;
// user to advanced internal signals
integer i_m_initial;
integer i_m;
integer i_n;
integer i_m2;
integer i_n2;
integer i_ss;
integer i_l0_high;
integer i_l1_high;
integer i_g0_high;
integer i_g1_high;
integer i_g2_high;
integer i_g3_high;
integer i_e0_high;
integer i_e1_high;
integer i_e2_high;
integer i_e3_high;
integer i_l0_low;
integer i_l1_low;
integer i_g0_low;
integer i_g1_low;
integer i_g2_low;
integer i_g3_low;
integer i_e0_low;
integer i_e1_low;
integer i_e2_low;
integer i_e3_low;
integer i_l0_initial;
integer i_l1_initial;
integer i_g0_initial;
integer i_g1_initial;
integer i_g2_initial;
integer i_g3_initial;
integer i_e0_initial;
integer i_e1_initial;
integer i_e2_initial;
integer i_e3_initial;
reg [8*6:1] i_l0_mode;
reg [8*6:1] i_l1_mode;
reg [8*6:1] i_g0_mode;
reg [8*6:1] i_g1_mode;
reg [8*6:1] i_g2_mode;
reg [8*6:1] i_g3_mode;
reg [8*6:1] i_e0_mode;
reg [8*6:1] i_e1_mode;
reg [8*6:1] i_e2_mode;
reg [8*6:1] i_e3_mode;
integer i_vco_min;
integer i_vco_max;
integer i_vco_center;
integer i_pfd_min;
integer i_pfd_max;
integer i_l0_ph;
integer i_l1_ph;
integer i_g0_ph;
integer i_g1_ph;
integer i_g2_ph;
integer i_g3_ph;
integer i_e0_ph;
integer i_e1_ph;
integer i_e2_ph;
integer i_e3_ph;
integer i_m_ph;
integer m_ph_val;
integer i_l0_time_delay;
integer i_l1_time_delay;
integer i_g0_time_delay;
integer i_g1_time_delay;
integer i_g2_time_delay;
integer i_g3_time_delay;
integer i_e0_time_delay;
integer i_e1_time_delay;
integer i_e2_time_delay;
integer i_e3_time_delay;
integer i_m_time_delay;
integer i_n_time_delay;
integer i_extclk3_counter;
integer i_extclk2_counter;
integer i_extclk1_counter;
integer i_extclk0_counter;
integer i_clk5_counter;
integer i_clk4_counter;
integer i_clk3_counter;
integer i_clk2_counter;
integer i_clk1_counter;
integer i_clk0_counter;
integer i_charge_pump_current;
integer i_loop_filter_r;
integer max_neg_abs;
integer output_count;
integer new_divisor;
reg pll_is_in_reset;
// uppercase to lowercase parameter values
reg [8*`WORD_LENGTH:1] l_operation_mode;
reg [8*`WORD_LENGTH:1] l_pll_type;
reg [8*`WORD_LENGTH:1] l_qualify_conf_done;
reg [8*`WORD_LENGTH:1] l_compensate_clock;
reg [8*`WORD_LENGTH:1] l_scan_chain;
reg [8*`WORD_LENGTH:1] l_primary_clock;
reg [8*`WORD_LENGTH:1] l_gate_lock_signal;
reg [8*`WORD_LENGTH:1] l_switch_over_on_lossclk;
reg [8*`WORD_LENGTH:1] l_switch_over_on_gated_lock;
reg [8*`WORD_LENGTH:1] l_enable_switch_over_counter;
reg [8*`WORD_LENGTH:1] l_feedback_source;
reg [8*`WORD_LENGTH:1] l_bandwidth_type;
reg [8*`WORD_LENGTH:1] l_simulation_type;
reg [8*`WORD_LENGTH:1] l_enable0_counter;
reg [8*`WORD_LENGTH:1] l_enable1_counter;
integer current_clock;
reg is_fast_pll;
reg op_mode;
reg init;
specify
endspecify
// finds the closest integer fraction of a given pair of numerator and denominator.
task find_simple_integer_fraction;
input numerator;
input denominator;
input max_denom;
output fraction_num;
output fraction_div;
parameter max_iter = 20;
integer numerator;
integer denominator;
integer max_denom;
integer fraction_num;
integer fraction_div;
integer quotient_array[max_iter-1:0];
integer int_loop_iter;
integer int_quot;
integer m_value;
integer d_value;
integer old_m_value;
integer swap;
integer loop_iter;
integer num;
integer den;
integer i_max_iter;
begin
loop_iter = 0;
num = numerator;
den = denominator;
i_max_iter = max_iter;
while (loop_iter < i_max_iter)
begin
int_quot = num / den;
quotient_array[loop_iter] = int_quot;
num = num - (den*int_quot);
loop_iter=loop_iter+1;
if ((num == 0) || (max_denom != -1) || (loop_iter == i_max_iter))
begin
// calculate the numerator and denominator if there is a restriction on the
// max denom value or if the loop is ending
m_value = 0;
d_value = 1;
// get the rounded value at this stage for the remaining fraction
if (den != 0)
begin
m_value = (2*num/den);
end
// calculate the fraction numerator and denominator at this stage
for (int_loop_iter = loop_iter-1; int_loop_iter >= 0; int_loop_iter=int_loop_iter-1)
begin
if (m_value == 0)
begin
m_value = quotient_array[int_loop_iter];
d_value = 1;
end
else
begin
old_m_value = m_value;
m_value = quotient_array[int_loop_iter]*m_value + d_value;
d_value = old_m_value;
end
end
// if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) || (max_denom == -1))
begin
if ((m_value == 0) || (d_value == 0))
begin
fraction_num = numerator;
fraction_div = denominator;
end
else
begin
fraction_num = m_value;
fraction_div = d_value;
end
end
// end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) && (max_denom != -1)) || (num == 0))
begin
i_max_iter = loop_iter;
end
end
// swap the numerator and denominator for the next round
swap = den;
den = num;
num = swap;
end
end
endtask // find_simple_integer_fraction
// get the absolute value
function integer abs;
input value;
integer value;
begin
if (value < 0)
abs = value * -1;
else abs = value;
end
endfunction
// find twice the period of the slowest clock
function integer slowest_clk;
input L0, L0_mode, L1, L1_mode, G0, G0_mode, G1, G1_mode, G2, G2_mode, G3, G3_mode, E0, E0_mode, E1, E1_mode, E2, E2_mode, E3, E3_mode, scan_chain, refclk, m_mod;
integer L0, L1, G0, G1, G2, G3, E0, E1, E2, E3;
reg [8*6:1] L0_mode, L1_mode, G0_mode, G1_mode, G2_mode, G3_mode, E0_mode, E1_mode, E2_mode, E3_mode;
reg [8*5:1] scan_chain;
integer refclk;
reg [31:0] m_mod;
integer max_modulus;
begin
max_modulus = 1;
if (L0_mode != "bypass" && L0_mode != " off")
max_modulus = L0;
if (L1 > max_modulus && L1_mode != "bypass" && L1_mode != " off")
max_modulus = L1;
if (G0 > max_modulus && G0_mode != "bypass" && G0_mode != " off")
max_modulus = G0;
if (G1 > max_modulus && G1_mode != "bypass" && G1_mode != " off")
max_modulus = G1;
if (G2 > max_modulus && G2_mode != "bypass" && G2_mode != " off")
max_modulus = G2;
if (G3 > max_modulus && G3_mode != "bypass" && G3_mode != " off")
max_modulus = G3;
if (scan_chain == "long")
begin
if (E0 > max_modulus && E0_mode != "bypass" && E0_mode != " off")
max_modulus = E0;
if (E1 > max_modulus && E1_mode != "bypass" && E1_mode != " off")
max_modulus = E1;
if (E2 > max_modulus && E2_mode != "bypass" && E2_mode != " off")
max_modulus = E2;
if (E3 > max_modulus && E3_mode != "bypass" && E3_mode != " off")
max_modulus = E3;
end
slowest_clk = ((refclk/m_mod) * max_modulus *2);
end
endfunction
// count the number of digits in the given integer
function integer count_digit;
input X;
integer X;
integer count, result;
begin
count = 0;
result = X;
while (result != 0)
begin
result = (result / 10);
count = count + 1;
end
count_digit = count;
end
endfunction
// reduce the given huge number(X) to Y significant digits
function integer scale_num;
input X, Y;
integer X, Y;
integer count;
integer fac_ten, lc;
begin
fac_ten = 1;
count = count_digit(X);
for (lc = 0; lc < (count-Y); lc = lc + 1)
fac_ten = fac_ten * 10;
scale_num = (X / fac_ten);
end
endfunction
// find the greatest common denominator of X and Y
function integer gcd;
input X,Y;
integer X,Y;
integer L, S, R, G;
begin
if (X < Y) // find which is smaller.
begin
S = X;
L = Y;
end
else
begin
S = Y;
L = X;
end
R = S;
while ( R > 1)
begin
S = L;
L = R;
R = S % L; // divide bigger number by smaller.
// remainder becomes smaller number.
end
if (R == 0) // if evenly divisible then L is gcd else it is 1.
G = L;
else
G = R;
gcd = G;
end
endfunction
// find the least common multiple of A1 to A10
function integer lcm;
input A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, P;
integer A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, P;
integer M1, M2, M3, M4, M5 , M6, M7, M8, M9, R;
begin
M1 = (A1 * A2)/gcd(A1, A2);
M2 = (M1 * A3)/gcd(M1, A3);
M3 = (M2 * A4)/gcd(M2, A4);
M4 = (M3 * A5)/gcd(M3, A5);
M5 = (M4 * A6)/gcd(M4, A6);
M6 = (M5 * A7)/gcd(M5, A7);
M7 = (M6 * A8)/gcd(M6, A8);
M8 = (M7 * A9)/gcd(M7, A9);
M9 = (M8 * A10)/gcd(M8, A10);
if (M9 < 3)
R = 10;
else if ((M9 <= 10) && (M9 >= 3))
R = 4 * M9;
else if (M9 > 1000)
R = scale_num(M9,3);
else
R = M9;
lcm = R;
end
endfunction
// find the factor of division of the output clock frequency
// compared to the VCO
function integer output_counter_value;
input clk_divide, clk_mult, M, N;
integer clk_divide, clk_mult, M, N;
integer R;
begin
R = (clk_divide * M)/(clk_mult * N);
output_counter_value = R;
end
endfunction
// find the mode of each of the PLL counters - bypass, even or odd
function [8*6:1] counter_mode;
input duty_cycle;
input output_counter_value;
integer duty_cycle;
integer output_counter_value;
integer half_cycle_high;
reg [8*6:1] R;
begin
half_cycle_high = (2*duty_cycle*output_counter_value)/100;
if (output_counter_value == 1)
R = "bypass";
else if ((half_cycle_high % 2) == 0)
R = "even";
else
R = "odd";
counter_mode = R;
end
endfunction
// find the number of VCO clock cycles to hold the output clock high
function integer counter_high;
input output_counter_value, duty_cycle;
integer output_counter_value, duty_cycle;
integer half_cycle_high;
integer tmp_counter_high;
integer mode;
begin
half_cycle_high = (2*duty_cycle*output_counter_value)/100;
mode = ((half_cycle_high % 2) == 0);
tmp_counter_high = half_cycle_high/2;
counter_high = tmp_counter_high + !mode;
end
endfunction
// find the number of VCO clock cycles to hold the output clock low
function integer counter_low;
input output_counter_value, duty_cycle;
integer output_counter_value, duty_cycle, counter_h;
integer half_cycle_high;
integer mode;
integer tmp_counter_high;
begin
half_cycle_high = (2*duty_cycle*output_counter_value)/100;
mode = ((half_cycle_high % 2) == 0);
tmp_counter_high = half_cycle_high/2;
counter_h = tmp_counter_high + !mode;
counter_low = output_counter_value - counter_h;
if (counter_low == 0)
counter_low = 1;
end
endfunction
// find the smallest time delay amongst t1 to t10
function integer mintimedelay;
input t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer m1,m2,m3,m4,m5,m6,m7,m8,m9;
begin
if (t1 < t2)
m1 = t1;
else
m1 = t2;
if (m1 < t3)
m2 = m1;
else
m2 = t3;
if (m2 < t4)
m3 = m2;
else
m3 = t4;
if (m3 < t5)
m4 = m3;
else
m4 = t5;
if (m4 < t6)
m5 = m4;
else
m5 = t6;
if (m5 < t7)
m6 = m5;
else
m6 = t7;
if (m6 < t8)
m7 = m6;
else
m7 = t8;
if (m7 < t9)
m8 = m7;
else
m8 = t9;
if (m8 < t10)
m9 = m8;
else
m9 = t10;
if (m9 > 0)
mintimedelay = m9;
else
mintimedelay = 0;
end
endfunction
// find the numerically largest negative number, and return its absolute value
function integer maxnegabs;
input t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer m1,m2,m3,m4,m5,m6,m7,m8,m9;
begin
if (t1 < t2) m1 = t1; else m1 = t2;
if (m1 < t3) m2 = m1; else m2 = t3;
if (m2 < t4) m3 = m2; else m3 = t4;
if (m3 < t5) m4 = m3; else m4 = t5;
if (m4 < t6) m5 = m4; else m5 = t6;
if (m5 < t7) m6 = m5; else m6 = t7;
if (m6 < t8) m7 = m6; else m7 = t8;
if (m7 < t9) m8 = m7; else m8 = t9;
if (m8 < t10) m9 = m8; else m9 = t10;
maxnegabs = (m9 < 0) ? 0 - m9 : 0;
end
endfunction
// adjust the given tap_phase by adding the largest negative number (ph_base)
function integer ph_adjust;
input tap_phase, ph_base;
integer tap_phase, ph_base;
begin
ph_adjust = tap_phase + ph_base;
end
endfunction
// find the actual time delay for each PLL counter
function integer counter_time_delay;
input clk_time_delay, m_time_delay, n_time_delay;
integer clk_time_delay, m_time_delay, n_time_delay;
begin
counter_time_delay = clk_time_delay + m_time_delay - n_time_delay;
end
endfunction
// find the number of VCO clock cycles to wait initially before the first
// rising edge of the output clock
function integer counter_initial;
input tap_phase, m, n;
integer tap_phase, m, n, phase;
begin
if (tap_phase < 0) tap_phase = 0 - tap_phase;
// adding 0.5 for rounding correction (required in order to round
// to the nearest integer instead of truncating)
phase = ((tap_phase * m) / (360 * n)) + 0.5;
counter_initial = phase;
end
endfunction
// find which VCO phase tap to align the rising edge of the output clock to
function integer counter_ph;
input tap_phase;
input m,n;
integer m,n, phase;
integer tap_phase;
begin
// adding 0.5 for rounding correction
phase = (tap_phase * m / n) + 0.5;
counter_ph = (phase % 360) / 45;
end
endfunction
// convert the given string to length 6 by padding with spaces
function [8*6:1] translate_string;
input mode;
reg [8*6:1] new_mode;
begin
if (mode == "bypass")
new_mode = "bypass";
else if (mode == "even")
new_mode = " even";
else if (mode == "odd")
new_mode = " odd";
translate_string = new_mode;
end
endfunction
// convert string to integer with sign
function integer str2int;
input [8*16:1] s;
reg [8*16:1] reg_s;
reg [8:1] digit;
reg [8:1] tmp;
integer m, magnitude;
integer sign;
begin
sign = 1;
magnitude = 0;
reg_s = s;
for (m=1; m<=16; m=m+1)
begin
tmp = reg_s[128:121];
digit = tmp & 8'b00001111;
reg_s = reg_s << 8;
// Accumulate ascii digits 0-9 only.
if ((tmp>=48) && (tmp<=57))
magnitude = (magnitude * 10) + digit;
if (tmp == 45)
sign = -1; // Found a '-' character, i.e. number is negative.
end
str2int = sign*magnitude;
end
endfunction
// this is for cyclone lvds only
// convert phase delay to integer
function integer get_int_phase_shift;
input [8*16:1] s;
input i_phase_shift;
integer i_phase_shift;
begin
if (i_phase_shift != 0)
begin
get_int_phase_shift = i_phase_shift;
end
else
begin
get_int_phase_shift = str2int(s);
end
end
endfunction
// calculate the given phase shift (in ps) in terms of degrees
function integer get_phase_degree;
input phase_shift;
integer phase_shift, result;
begin
result = (phase_shift * 360) / inclk0_input_frequency;
// this is to round up the calculation result
if ( result > 0 )
result = result + 1;
else if ( result < 0 )
result = result - 1;
else
result = 0;
// assign the rounded up result
get_phase_degree = result;
end
endfunction
// convert uppercase parameter values to lowercase
// assumes that the maximum character length of a parameter is 18
function [8*`WORD_LENGTH:1] alpha_tolower;
input [8*`WORD_LENGTH:1] given_string;
reg [8*`WORD_LENGTH:1] return_string;
reg [8*`WORD_LENGTH:1] reg_string;
reg [8:1] tmp;
reg [8:1] conv_char;
integer byte_count;
begin
return_string = " "; // initialise strings to spaces
conv_char = " ";
reg_string = given_string;
for (byte_count = `WORD_LENGTH; byte_count >= 1; byte_count = byte_count - 1)
begin
tmp = reg_string[8*`WORD_LENGTH:(8*(`WORD_LENGTH-1)+1)];
reg_string = reg_string << 8;
if ((tmp >= 65) && (tmp <= 90)) // ASCII number of 'A' is 65, 'Z' is 90
begin
conv_char = tmp + 32; // 32 is the difference in the position of 'A' and 'a' in the ASCII char set
return_string = {return_string, conv_char};
end
else
return_string = {return_string, tmp};
end
alpha_tolower = return_string;
end
endfunction
initial
begin
// convert string parameter values from uppercase to lowercase,
// as expected in this model
l_operation_mode = alpha_tolower(operation_mode);
l_pll_type = alpha_tolower(pll_type);
l_qualify_conf_done = alpha_tolower(qualify_conf_done);
l_compensate_clock = alpha_tolower(compensate_clock);
l_scan_chain = alpha_tolower(scan_chain);
l_primary_clock = alpha_tolower(primary_clock);
l_gate_lock_signal = alpha_tolower(gate_lock_signal);
l_switch_over_on_lossclk = alpha_tolower(switch_over_on_lossclk);
l_switch_over_on_gated_lock = alpha_tolower(switch_over_on_gated_lock);
l_enable_switch_over_counter = alpha_tolower(enable_switch_over_counter);
l_feedback_source = alpha_tolower(feedback_source);
l_bandwidth_type = alpha_tolower(bandwidth_type);
l_simulation_type = alpha_tolower(simulation_type);
l_enable0_counter = alpha_tolower(enable0_counter);
l_enable1_counter = alpha_tolower(enable1_counter);
if (m == 0)
begin
// set the limit of the divide_by value that can be returned by
// the following function.
max_d_value = 500;
// scale down the multiply_by and divide_by values provided by the design
// before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
find_simple_integer_fraction(clk5_multiply_by, clk5_divide_by,
max_d_value, i_clk5_mult_by, i_clk5_div_by);
find_simple_integer_fraction(extclk0_multiply_by, extclk0_divide_by,
max_d_value, i_extclk0_mult_by, i_extclk0_div_by);
find_simple_integer_fraction(extclk1_multiply_by, extclk1_divide_by,
max_d_value, i_extclk1_mult_by, i_extclk1_div_by);
find_simple_integer_fraction(extclk2_multiply_by, extclk2_divide_by,
max_d_value, i_extclk2_mult_by, i_extclk2_div_by);
find_simple_integer_fraction(extclk3_multiply_by, extclk3_divide_by,
max_d_value, i_extclk3_mult_by, i_extclk3_div_by);
// convert user parameters to advanced
i_n = 1;
if (l_pll_type == "lvds")
i_m = clk0_multiply_by;
else
i_m = lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by, i_clk5_mult_by,
i_extclk0_mult_by,
i_extclk1_mult_by, i_extclk2_mult_by,
i_extclk3_mult_by, inclk0_input_frequency);
i_m_time_delay = maxnegabs (str2int(clk0_time_delay),
str2int(clk1_time_delay),
str2int(clk2_time_delay),
str2int(clk3_time_delay),
str2int(clk4_time_delay),
str2int(clk5_time_delay),
str2int(extclk0_time_delay),
str2int(extclk1_time_delay),
str2int(extclk2_time_delay),
str2int(extclk3_time_delay));
i_n_time_delay = mintimedelay(str2int(clk0_time_delay),
str2int(clk1_time_delay),
str2int(clk2_time_delay),
str2int(clk3_time_delay),
str2int(clk4_time_delay),
str2int(clk5_time_delay),
str2int(extclk0_time_delay),
str2int(extclk1_time_delay),
str2int(extclk2_time_delay),
str2int(extclk3_time_delay));
if (l_pll_type == "lvds")
i_g0_high = counter_high(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
else
i_g0_high = counter_high(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_g1_high = counter_high(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_g2_high = counter_high(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_g3_high = counter_high(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
if (l_pll_type == "lvds")
begin
i_l0_high = i_g0_high;
i_l1_high = i_g0_high;
end
else
begin
i_l0_high = counter_high(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_l1_high = counter_high(output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
end
i_e0_high = counter_high(output_counter_value(i_extclk0_div_by,
i_extclk0_mult_by, i_m, i_n), extclk0_duty_cycle);
i_e1_high = counter_high(output_counter_value(i_extclk1_div_by,
i_extclk1_mult_by, i_m, i_n), extclk1_duty_cycle);
i_e2_high = counter_high(output_counter_value(i_extclk2_div_by,
i_extclk2_mult_by, i_m, i_n), extclk2_duty_cycle);
i_e3_high = counter_high(output_counter_value(i_extclk3_div_by,
i_extclk3_mult_by, i_m, i_n), extclk3_duty_cycle);
if (l_pll_type == "lvds")
i_g0_low = counter_low(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
else
i_g0_low = counter_low(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_g1_low = counter_low(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_g2_low = counter_low(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_g3_low = counter_low(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
if (l_pll_type == "lvds")
begin
i_l0_low = i_g0_low;
i_l1_low = i_g0_low;
end
else
begin
i_l0_low = counter_low(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_l1_low = counter_low(output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
end
i_e0_low = counter_low(output_counter_value(i_extclk0_div_by,
i_extclk0_mult_by, i_m, i_n), extclk0_duty_cycle);
i_e1_low = counter_low(output_counter_value(i_extclk1_div_by,
i_extclk1_mult_by, i_m, i_n), extclk1_duty_cycle);
i_e2_low = counter_low(output_counter_value(i_extclk2_div_by,
i_extclk2_mult_by, i_m, i_n), extclk2_duty_cycle);
i_e3_low = counter_low(output_counter_value(i_extclk3_div_by,
i_extclk3_mult_by, i_m, i_n), extclk3_duty_cycle);
if (l_pll_type == "flvds")
begin
// Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier = clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift = (clk0_phase_shift_num * new_multiplier);
i_clk1_phase_shift = (clk1_phase_shift_num * new_multiplier);
i_clk2_phase_shift = (clk2_phase_shift_num * new_multiplier);
end
else
begin
i_clk0_phase_shift = get_int_phase_shift(clk0_phase_shift, clk0_phase_shift_num);
i_clk1_phase_shift = get_int_phase_shift(clk1_phase_shift, clk1_phase_shift_num);
i_clk2_phase_shift = get_int_phase_shift(clk2_phase_shift, clk2_phase_shift_num);
end
max_neg_abs = maxnegabs(i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
str2int(clk3_phase_shift),
str2int(clk4_phase_shift),
str2int(clk5_phase_shift),
str2int(extclk0_phase_shift),
str2int(extclk1_phase_shift),
str2int(extclk2_phase_shift),
str2int(extclk3_phase_shift));
if (l_pll_type == "lvds")
i_g0_initial = counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs)), i_m, i_n);
else
i_g0_initial = counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs)), i_m, i_n);
i_g1_initial = counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs)), i_m, i_n);
i_g2_initial = counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs)), i_m, i_n);
i_g3_initial = counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs)), i_m, i_n);
if (l_pll_type == "lvds")
begin
i_l0_initial = i_g0_initial;
i_l1_initial = i_g0_initial;
end
else
begin
i_l0_initial = counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs)), i_m, i_n);
i_l1_initial = counter_initial(get_phase_degree(ph_adjust(str2int(clk5_phase_shift), max_neg_abs)), i_m, i_n);
end
i_e0_initial = counter_initial(get_phase_degree(ph_adjust(str2int(extclk0_phase_shift), max_neg_abs)), i_m, i_n);
i_e1_initial = counter_initial(get_phase_degree(ph_adjust(str2int(extclk1_phase_shift), max_neg_abs)), i_m, i_n);
i_e2_initial = counter_initial(get_phase_degree(ph_adjust(str2int(extclk2_phase_shift), max_neg_abs)), i_m, i_n);
i_e3_initial = counter_initial(get_phase_degree(ph_adjust(str2int(extclk3_phase_shift), max_neg_abs)), i_m, i_n);
if (l_pll_type == "lvds")
i_g0_mode = counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
else
i_g0_mode = counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
i_g1_mode = counter_mode(clk1_duty_cycle,output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_g2_mode = counter_mode(clk2_duty_cycle,output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_g3_mode = counter_mode(clk3_duty_cycle,output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
if (l_pll_type == "lvds")
begin
i_l0_mode = "bypass";
i_l1_mode = "bypass";
end
else
begin
i_l0_mode = counter_mode(clk4_duty_cycle,output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
i_l1_mode = counter_mode(clk5_duty_cycle,output_counter_value(i_clk5_div_by, i_clk5_mult_by, i_m, i_n));
end
i_e0_mode = counter_mode(extclk0_duty_cycle,output_counter_value(i_extclk0_div_by, i_extclk0_mult_by, i_m, i_n));
i_e1_mode = counter_mode(extclk1_duty_cycle,output_counter_value(i_extclk1_div_by, i_extclk1_mult_by, i_m, i_n));
i_e2_mode = counter_mode(extclk2_duty_cycle,output_counter_value(i_extclk2_div_by, i_extclk2_mult_by, i_m, i_n));
i_e3_mode = counter_mode(extclk3_duty_cycle,output_counter_value(i_extclk3_div_by, i_extclk3_mult_by, i_m, i_n));
i_m_ph = counter_ph(get_phase_degree(max_neg_abs), i_m, i_n);
i_m_initial = counter_initial(get_phase_degree(max_neg_abs), i_m, i_n);
if (l_pll_type == "lvds")
i_g0_ph = counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs)), i_m, i_n);
else
i_g0_ph = counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs)), i_m, i_n);
i_g1_ph = counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs)), i_m, i_n);
i_g2_ph = counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs)), i_m, i_n);
i_g3_ph = counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs)), i_m, i_n);
if (l_pll_type == "lvds")
begin
i_l0_ph = i_g0_ph;
i_l1_ph = i_g0_ph;
end
else
begin
i_l0_ph = counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs)), i_m, i_n);
i_l1_ph = counter_ph(get_phase_degree(ph_adjust(str2int(clk5_phase_shift),max_neg_abs)), i_m, i_n);
end
i_e0_ph = counter_ph(get_phase_degree(ph_adjust(str2int(extclk0_phase_shift),max_neg_abs)), i_m, i_n);
i_e1_ph = counter_ph(get_phase_degree(ph_adjust(str2int(extclk1_phase_shift),max_neg_abs)), i_m, i_n);
i_e2_ph = counter_ph(get_phase_degree(ph_adjust(str2int(extclk2_phase_shift),max_neg_abs)), i_m, i_n);
i_e3_ph = counter_ph(get_phase_degree(ph_adjust(str2int(extclk3_phase_shift),max_neg_abs)), i_m, i_n);
if (l_pll_type == "lvds")
i_g0_time_delay = counter_time_delay ( str2int(clk2_time_delay),
i_m_time_delay,
i_n_time_delay);
else
i_g0_time_delay = counter_time_delay ( str2int(clk0_time_delay),
i_m_time_delay,
i_n_time_delay);
i_g1_time_delay = counter_time_delay ( str2int(clk1_time_delay),
i_m_time_delay,
i_n_time_delay);
i_g2_time_delay = counter_time_delay ( str2int(clk2_time_delay),
i_m_time_delay,
i_n_time_delay);
i_g3_time_delay = counter_time_delay ( str2int(clk3_time_delay),
i_m_time_delay,
i_n_time_delay);
if (l_pll_type == "lvds")
begin
i_l0_time_delay = i_g0_time_delay;
i_l1_time_delay = i_g0_time_delay;
end
else
begin
i_l0_time_delay = counter_time_delay ( str2int(clk4_time_delay),
i_m_time_delay,
i_n_time_delay);
i_l1_time_delay = counter_time_delay ( str2int(clk5_time_delay),
i_m_time_delay,
i_n_time_delay);
end
i_e0_time_delay = counter_time_delay ( str2int( extclk0_time_delay),
i_m_time_delay,
i_n_time_delay);
i_e1_time_delay = counter_time_delay ( str2int( extclk1_time_delay),
i_m_time_delay,
i_n_time_delay);
i_e2_time_delay = counter_time_delay ( str2int( extclk2_time_delay),
i_m_time_delay,
i_n_time_delay);
i_e3_time_delay = counter_time_delay ( str2int( extclk3_time_delay),
i_m_time_delay,
i_n_time_delay);
i_extclk3_counter = "e3" ;
i_extclk2_counter = "e2" ;
i_extclk1_counter = "e1" ;
i_extclk0_counter = "e0" ;
i_clk5_counter = "l1" ;
i_clk4_counter = "l0" ;
i_clk3_counter = "g3" ;
i_clk2_counter = "g2" ;
i_clk1_counter = "g1" ;
if (l_pll_type == "lvds")
begin
l_enable0_counter = "l0";
l_enable1_counter = "l1";
i_clk0_counter = "l0" ;
end
else
i_clk0_counter = "g0" ;
// in external feedback mode, need to adjust M value to take
// into consideration the external feedback counter value
if (l_operation_mode == "external_feedback")
begin
// if there is a negative phase shift, m_initial can only be 1
if (max_neg_abs > 0)
i_m_initial = 1;
if (l_feedback_source == "extclk0")
begin
if (i_e0_mode == "bypass")
output_count = 1;
else
output_count = i_e0_high + i_e0_low;
end
else if (l_feedback_source == "extclk1")
begin
if (i_e1_mode == "bypass")
output_count = 1;
else
output_count = i_e1_high + i_e1_low;
end
else if (l_feedback_source == "extclk2")
begin
if (i_e2_mode == "bypass")
output_count = 1;
else
output_count = i_e2_high + i_e2_low;
end
else if (l_feedback_source == "extclk3")
begin
if (i_e3_mode == "bypass")
output_count = 1;
else
output_count = i_e3_high + i_e3_low;
end
else // default to e0
begin
if (i_e0_mode == "bypass")
output_count = 1;
else
output_count = i_e0_high + i_e0_low;
end
new_divisor = gcd(i_m, output_count);
i_m = i_m / new_divisor;
i_n = output_count / new_divisor;
end
end
else
begin // m != 0
i_n = n;
i_m = m;
i_l0_high = l0_high;
i_l1_high = l1_high;
i_g0_high = g0_high;
i_g1_high = g1_high;
i_g2_high = g2_high;
i_g3_high = g3_high;
i_e0_high = e0_high;
i_e1_high = e1_high;
i_e2_high = e2_high;
i_e3_high = e3_high;
i_l0_low = l0_low;
i_l1_low = l1_low;
i_g0_low = g0_low;
i_g1_low = g1_low;
i_g2_low = g2_low;
i_g3_low = g3_low;
i_e0_low = e0_low;
i_e1_low = e1_low;
i_e2_low = e2_low;
i_e3_low = e3_low;
i_l0_initial = l0_initial;
i_l1_initial = l1_initial;
i_g0_initial = g0_initial;
i_g1_initial = g1_initial;
i_g2_initial = g2_initial;
i_g3_initial = g3_initial;
i_e0_initial = e0_initial;
i_e1_initial = e1_initial;
i_e2_initial = e2_initial;
i_e3_initial = e3_initial;
i_l0_mode = alpha_tolower(l0_mode);
i_l1_mode = alpha_tolower(l1_mode);
i_g0_mode = alpha_tolower(g0_mode);
i_g1_mode = alpha_tolower(g1_mode);
i_g2_mode = alpha_tolower(g2_mode);
i_g3_mode = alpha_tolower(g3_mode);
i_e0_mode = alpha_tolower(e0_mode);
i_e1_mode = alpha_tolower(e1_mode);
i_e2_mode = alpha_tolower(e2_mode);
i_e3_mode = alpha_tolower(e3_mode);
i_l0_ph = l0_ph;
i_l1_ph = l1_ph;
i_g0_ph = g0_ph;
i_g1_ph = g1_ph;
i_g2_ph = g2_ph;
i_g3_ph = g3_ph;
i_e0_ph = e0_ph;
i_e1_ph = e1_ph;
i_e2_ph = e2_ph;
i_e3_ph = e3_ph;
i_m_ph = m_ph; // default
i_m_initial = m_initial;
i_l0_time_delay = l0_time_delay;
i_l1_time_delay = l1_time_delay;
i_g0_time_delay = g0_time_delay;
i_g1_time_delay = g1_time_delay;
i_g2_time_delay = g2_time_delay;
i_g3_time_delay = g3_time_delay;
i_e0_time_delay = e0_time_delay;
i_e1_time_delay = e1_time_delay;
i_e2_time_delay = e2_time_delay;
i_e3_time_delay = e3_time_delay;
i_m_time_delay = m_time_delay;
i_n_time_delay = n_time_delay;
i_extclk3_counter = alpha_tolower(extclk3_counter);
i_extclk2_counter = alpha_tolower(extclk2_counter);
i_extclk1_counter = alpha_tolower(extclk1_counter);
i_extclk0_counter = alpha_tolower(extclk0_counter);
i_clk5_counter = alpha_tolower(clk5_counter);
i_clk4_counter = alpha_tolower(clk4_counter);
i_clk3_counter = alpha_tolower(clk3_counter);
i_clk2_counter = alpha_tolower(clk2_counter);
i_clk1_counter = alpha_tolower(clk1_counter);
i_clk0_counter = alpha_tolower(clk0_counter);
end // user to advanced conversion
// set the scan_chain length
if (l_scan_chain == "long")
scan_chain_length = EGPP_SCAN_CHAIN;
else if (l_scan_chain == "short")
scan_chain_length = GPP_SCAN_CHAIN;
if (l_primary_clock == "inclk0")
begin
refclk_period = inclk0_input_frequency * i_n;
primary_clock_frequency = inclk0_input_frequency;
end
else if (l_primary_clock == "inclk1")
begin
refclk_period = inclk1_input_frequency * i_n;
primary_clock_frequency = inclk1_input_frequency;
end
m_times_vco_period = refclk_period;
new_m_times_vco_period = refclk_period;
fbclk_period = 0;
high_time = 0;
low_time = 0;
schedule_vco = 0;
schedule_offset = 1;
vco_out[7:0] = 8'b0;
fbclk_last_value = 0;
offset = 0;
temp_offset = 0;
got_first_refclk = 0;
got_first_fbclk = 0;
fbclk_time = 0;
first_fbclk_time = 0;
refclk_time = 0;
first_schedule = 1;
sched_time = 0;
vco_val = 0;
l0_got_first_rising_edge = 0;
l1_got_first_rising_edge = 0;
vco_l0_last_value = 0;
l0_count = 1;
l1_count = 1;
l0_tmp = 0;
l1_tmp = 0;
gate_count = 0;
gate_out = 0;
initial_delay = 0;
fbk_phase = 0;
for (i = 0; i <= 7; i = i + 1)
begin
phase_shift[i] = 0;
last_phase_shift[i] = 0;
end
fbk_delay = 0;
inclk_n = 0;
cycle_to_adjust = 0;
m_delay = 0;
vco_l0 = 0;
vco_l1 = 0;
total_pull_back = 0;
pull_back_M = 0;
pull_back_ext_cntr = 0;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
ena_ipd_last_value = 0;
inclk_out_of_range = 0;
scandataout_tmp = 0;
scandataout_trigger = 0;
schedule_vco_last_value = 0;
// set initial values for counter parameters
m_initial_val = i_m_initial;
m_val = i_m;
m_time_delay_val = i_m_time_delay;
n_val = i_n;
n_time_delay_val = i_n_time_delay;
m_ph_val = i_m_ph;
m2_val = m2;
n2_val = n2;
if (m_val == 1)
m_mode_val = "bypass";
if (m2_val == 1)
m2_mode_val = "bypass";
if (n_val == 1)
n_mode_val = "bypass";
if (n2_val == 1)
n2_mode_val = "bypass";
if (skip_vco == "on")
begin
m_val = 1;
m_initial_val = 1;
m_time_delay_val = 0;
m_ph_val = 0;
end
l0_high_val = i_l0_high;
l0_low_val = i_l0_low;
l0_initial_val = i_l0_initial;
l0_mode_val = i_l0_mode;
l0_time_delay_val = i_l0_time_delay;
l1_high_val = i_l1_high;
l1_low_val = i_l1_low;
l1_initial_val = i_l1_initial;
l1_mode_val = i_l1_mode;
l1_time_delay_val = i_l1_time_delay;
g0_high_val = i_g0_high;
g0_low_val = i_g0_low;
g0_initial_val = i_g0_initial;
g0_mode_val = i_g0_mode;
g0_time_delay_val = i_g0_time_delay;
g1_high_val = i_g1_high;
g1_low_val = i_g1_low;
g1_initial_val = i_g1_initial;
g1_mode_val = i_g1_mode;
g1_time_delay_val = i_g1_time_delay;
g2_high_val = i_g2_high;
g2_low_val = i_g2_low;
g2_initial_val = i_g2_initial;
g2_mode_val = i_g2_mode;
g2_time_delay_val = i_g2_time_delay;
g3_high_val = i_g3_high;
g3_low_val = i_g3_low;
g3_initial_val = i_g3_initial;
g3_mode_val = i_g3_mode;
g3_time_delay_val = i_g3_time_delay;
e0_high_val = i_e0_high;
e0_low_val = i_e0_low;
e0_initial_val = i_e0_initial;
e0_mode_val = i_e0_mode;
e0_time_delay_val = i_e0_time_delay;
e1_high_val = i_e1_high;
e1_low_val = i_e1_low;
e1_initial_val = i_e1_initial;
e1_mode_val = i_e1_mode;
e1_time_delay_val = i_e1_time_delay;
e2_high_val = i_e2_high;
e2_low_val = i_e2_low;
e2_initial_val = i_e2_initial;
e2_mode_val = i_e2_mode;
e2_time_delay_val = i_e2_time_delay;
e3_high_val = i_e3_high;
e3_low_val = i_e3_low;
e3_initial_val = i_e3_initial;
e3_mode_val = i_e3_mode;
e3_time_delay_val = i_e3_time_delay;
i = 0;
j = 0;
inclk_last_value = 0;
ext_fbk_cntr_ph = 0;
ext_fbk_cntr_initial = 1;
// initialize clkswitch variables
clk0_is_bad = 0;
clk1_is_bad = 0;
inclk0_last_value = 0;
inclk1_last_value = 0;
other_clock_value = 0;
other_clock_last_value = 0;
primary_clk_is_bad = 0;
current_clk_is_bad = 0;
external_switch = 0;
// current_clock = l_primary_clock;
if (l_primary_clock == "inclk0")
current_clock = 0;
else
current_clock = 1;
if (l_primary_clock == "inclk0")
active_clock = 0;
else
active_clock = 1;
clkloss_tmp = 0;
got_curr_clk_falling_edge_after_clkswitch = 0;
clk0_count = 0;
clk1_count = 0;
switch_over_count = 0;
active_clk_was_switched = 0;
// initialize quiet_time
quiet_time = slowest_clk ( l0_high_val+l0_low_val, l0_mode_val,
l1_high_val+l1_low_val, l1_mode_val,
g0_high_val+g0_low_val, g0_mode_val,
g1_high_val+g1_low_val, g1_mode_val,
g2_high_val+g2_low_val, g2_mode_val,
g3_high_val+g3_low_val, g3_mode_val,
e0_high_val+e0_low_val, e0_mode_val,
e1_high_val+e1_low_val, e1_mode_val,
e2_high_val+e2_low_val, e2_mode_val,
e3_high_val+e3_low_val, e3_mode_val,
l_scan_chain,
refclk_period, m_val);
pll_in_quiet_period = 0;
start_quiet_time = 0;
quiet_period_violation = 0;
reconfig_err = 0;
scanclr_violation = 0;
scanclr_clk_violation = 0;
got_first_scanclk_after_scanclr_inactive_edge = 0;
error = 0;
scanaclr_rising_time = 0;
scanaclr_falling_time = 0;
// VCO feedback loop settings for external feedback mode
// first find which ext counter is used for feedback
if (l_operation_mode == "external_feedback")
begin
if (l_feedback_source == "extclk0")
begin
if (i_extclk0_counter == "e0")
ext_fbk_cntr = "e0";
else if (i_extclk0_counter == "e1")
ext_fbk_cntr = "e1";
else if (i_extclk0_counter == "e2")
ext_fbk_cntr = "e2";
else if (i_extclk0_counter == "e3")
ext_fbk_cntr = "e3";
else ext_fbk_cntr = "e0";
end
else if (l_feedback_source == "extclk1")
begin
if (i_extclk1_counter == "e0")
ext_fbk_cntr = "e0";
else if (i_extclk1_counter == "e1")
ext_fbk_cntr = "e1";
else if (i_extclk1_counter == "e2")
ext_fbk_cntr = "e2";
else if (i_extclk1_counter == "e3")
ext_fbk_cntr = "e3";
else ext_fbk_cntr = "e0";
end
else if (l_feedback_source == "extclk2")
begin
if (i_extclk2_counter == "e0")
ext_fbk_cntr = "e0";
else if (i_extclk2_counter == "e1")
ext_fbk_cntr = "e1";
else if (i_extclk2_counter == "e2")
ext_fbk_cntr = "e2";
else if (i_extclk2_counter == "e3")
ext_fbk_cntr = "e3";
else ext_fbk_cntr = "e0";
end
else if (l_feedback_source == "extclk3")
begin
if (i_extclk3_counter == "e0")
ext_fbk_cntr = "e0";
else if (i_extclk3_counter == "e1")
ext_fbk_cntr = "e1";
else if (i_extclk3_counter == "e2")
ext_fbk_cntr = "e2";
else if (i_extclk3_counter == "e3")
ext_fbk_cntr = "e3";
else ext_fbk_cntr = "e0";
end
// now save this counter's parameters
if (ext_fbk_cntr == "e0")
begin
ext_fbk_cntr_high = e0_high_val;
ext_fbk_cntr_low = e0_low_val;
ext_fbk_cntr_ph = i_e0_ph;
ext_fbk_cntr_initial = i_e0_initial;
ext_fbk_cntr_delay = e0_time_delay_val;
ext_fbk_cntr_mode = e0_mode_val;
end
else if (ext_fbk_cntr == "e1")
begin
ext_fbk_cntr_high = e1_high_val;
ext_fbk_cntr_low = e1_low_val;
ext_fbk_cntr_ph = i_e1_ph;
ext_fbk_cntr_initial = i_e1_initial;
ext_fbk_cntr_delay = e1_time_delay_val;
ext_fbk_cntr_mode = e1_mode_val;
end
else if (ext_fbk_cntr == "e2")
begin
ext_fbk_cntr_high = e2_high_val;
ext_fbk_cntr_low = e2_low_val;
ext_fbk_cntr_ph = i_e2_ph;
ext_fbk_cntr_initial = i_e2_initial;
ext_fbk_cntr_delay = e2_time_delay_val;
ext_fbk_cntr_mode = e2_mode_val;
end
else if (ext_fbk_cntr == "e3")
begin
ext_fbk_cntr_high = e3_high_val;
ext_fbk_cntr_low = e3_low_val;
ext_fbk_cntr_ph = i_e3_ph;
ext_fbk_cntr_initial = i_e3_initial;
ext_fbk_cntr_delay = e3_time_delay_val;
ext_fbk_cntr_mode = e3_mode_val;
end
if (ext_fbk_cntr_mode == "bypass")
ext_fbk_cntr_modulus = 1;
else
ext_fbk_cntr_modulus = ext_fbk_cntr_high + ext_fbk_cntr_low;
end
l_index = 1;
stop_vco = 0;
cycles_to_lock = 0;
cycles_to_unlock = 0;
if (l_pll_type == "fast")
locked_tmp = 1;
else
locked_tmp = 0;
pll_is_locked = 0;
pll_about_to_lock = 0;
no_warn = 0;
m_val_tmp = m_val;
n_val_tmp = n_val;
pll_is_in_reset = 0;
if (l_pll_type == "fast" || l_pll_type == "lvds")
is_fast_pll = 1;
else is_fast_pll = 0;
end
assign inclk_m = l_operation_mode == "external_feedback" ? (l_feedback_source == "extclk0" ? extclk0_tmp :
l_feedback_source == "extclk1" ? extclk1_tmp :
l_feedback_source == "extclk2" ? extclk2_tmp :
l_feedback_source == "extclk3" ? extclk3_tmp : 1'b0) :
vco_out[m_ph_val];
cyclone_m_cntr m1 (.clk(inclk_m),
.reset(areset_ipd || (!ena_ipd) || stop_vco),
.cout(fbclk),
.initial_value(m_initial_val),
.modulus(m_val),
.time_delay(m_delay));
always @(clkswitch_ipd)
begin
if (clkswitch_ipd == 1'b1)
external_switch = 1;
clkloss_tmp <= clkswitch_ipd;
end
always @(inclk0_ipd or inclk1_ipd)
begin
// save the inclk event value
if (inclk0_ipd !== inclk0_last_value)
begin
if (current_clock !== 0)
other_clock_value = inclk0_ipd;
end
if (inclk1_ipd !== inclk1_last_value)
begin
if (current_clock !== 1)
other_clock_value = inclk1_ipd;
end
// check if either input clk is bad
if (inclk0_ipd === 1'b1 && inclk0_ipd !== inclk0_last_value)
begin
clk0_count = clk0_count + 1;
clk0_is_bad = 0;
if (current_clock == 0)
current_clk_is_bad = 0;
clk1_count = 0;
if (clk0_count > 2)
begin
// no event on other clk for 2 cycles
clk1_is_bad = 1;
if (current_clock == 1)
current_clk_is_bad = 1;
end
end
if (inclk1_ipd === 1'b1 && inclk1_ipd !== inclk1_last_value)
begin
clk1_count = clk1_count + 1;
clk1_is_bad = 0;
if (current_clock == 1)
current_clk_is_bad = 0;
clk0_count = 0;
if (clk1_count > 2)
begin
// no event on other clk for 2 cycles
clk0_is_bad = 1;
if (current_clock == 0)
current_clk_is_bad = 1;
end
end
// check if the bad clk is the primary clock
if (((l_primary_clock == "inclk0") && (clk0_is_bad == 1'b1)) || ((l_primary_clock == "inclk1") && (clk1_is_bad == 1'b1)))
primary_clk_is_bad = 1;
else
primary_clk_is_bad = 0;
// actual switching
if ((inclk0_ipd !== inclk0_last_value) && (current_clock == 0))
begin
if (external_switch == 1'b1)
begin
if (!got_curr_clk_falling_edge_after_clkswitch)
begin
if (inclk0_ipd === 1'b0)
got_curr_clk_falling_edge_after_clkswitch = 1;
inclk_n = inclk0_ipd;
end
end
else inclk_n = inclk0_ipd;
end
if ((inclk1_ipd !== inclk1_last_value) && (current_clock == 1))
begin
if (external_switch == 1'b1)
begin
if (!got_curr_clk_falling_edge_after_clkswitch)
begin
if (inclk1_ipd === 1'b0)
got_curr_clk_falling_edge_after_clkswitch = 1;
inclk_n = inclk1_ipd;
end
end
else inclk_n = inclk1_ipd;
end
if ((other_clock_value == 1'b1) && (other_clock_value != other_clock_last_value) && (l_switch_over_on_lossclk == "on") && (l_enable_switch_over_counter == "on") && primary_clk_is_bad)
switch_over_count = switch_over_count + 1;
if ((other_clock_value == 1'b0) && (other_clock_value != other_clock_last_value))
begin
if ((external_switch && (got_curr_clk_falling_edge_after_clkswitch || current_clk_is_bad)) || (l_switch_over_on_lossclk == "on" && primary_clk_is_bad && ((l_enable_switch_over_counter == "off" || switch_over_count == switch_over_counter))))
begin
got_curr_clk_falling_edge_after_clkswitch = 0;
if (current_clock == 0)
begin
current_clock = 1;
end
else
begin
current_clock = 0;
end
active_clock = ~active_clock;
active_clk_was_switched = 1;
switch_over_count = 0;
external_switch = 0;
current_clk_is_bad = 0;
end
end
if (l_switch_over_on_lossclk == "on" && (clkswitch_ipd != 1'b1))
begin
if (primary_clk_is_bad)
clkloss_tmp = 1;
else
clkloss_tmp = 0;
end
inclk0_last_value = inclk0_ipd;
inclk1_last_value = inclk1_ipd;
other_clock_last_value = other_clock_value;
end
and (clkbad[0], clk0_is_bad, 1'b1);
and (clkbad[1], clk1_is_bad, 1'b1);
and (activeclock, active_clock, 1'b1);
and (clkloss, clkloss_tmp, 1'b1);
cyclone_n_cntr n1 ( .clk(inclk_n),
.reset(areset_ipd),
.cout(refclk),
.modulus(n_val),
.time_delay(n_time_delay_val));
cyclone_scale_cntr l0 ( .clk(vco_out[i_l0_ph]),
.reset(areset_ipd || (!ena_ipd) || stop_vco),
.cout(l0_clk),
.high(l0_high_val),
.low(l0_low_val),
.initial_value(l0_initial_val),
.mode(l0_mode_val),
.time_delay(l0_time_delay_val),
.ph_tap(i_l0_ph));
cyclone_scale_cntr l1 ( .clk(vco_out[i_l1_ph]),
.reset(areset_ipd || (!ena_ipd) || stop_vco),
.cout(l1_clk),
.high(l1_high_val),
.low(l1_low_val),
.initial_value(l1_initial_val),
.mode(l1_mode_val),
.time_delay(l1_time_delay_val),
.ph_tap(i_l1_ph));
cyclone_scale_cntr g0 ( .clk(vco_out[i_g0_ph]),
.reset(areset_ipd || (!ena_ipd) || stop_vco),
.cout(g0_clk),
.high(g0_high_val),
.low(g0_low_val),
.initial_value(g0_initial_val),
.mode(g0_mode_val),
.time_delay(g0_time_delay_val),
.ph_tap(i_g0_ph));
cyclone_pll_reg lvds_dffa ( .d(comparator_ipd),
.clrn(1'b1),
.prn(1'b1),
.ena(1'b1),
.clk(g0_clk),
.q(dffa_out));
cyclone_pll_reg lvds_dffb ( .d(dffa_out),
.clrn(1'b1),
.prn(1'b1),
.ena(1'b1),
.clk(lvds_dffb_clk),
.q(dffb_out));
assign lvds_dffb_clk = (l_enable0_counter == "l0") ? l0_clk : (l_enable0_counter == "l1") ? l1_clk : 1'b0;
cyclone_pll_reg lvds_dffc ( .d(dffb_out),
.clrn(1'b1),
.prn(1'b1),
.ena(1'b1),
.clk(lvds_dffc_clk),
.q(dffc_out));
assign lvds_dffc_clk = (l_enable0_counter == "l0") ? l0_clk : (l_enable0_counter == "l1") ? l1_clk : 1'b0;
assign nce_temp = ~dffc_out && dffb_out;
cyclone_pll_reg lvds_dffd ( .d(nce_temp),
.clrn(1'b1),
.prn(1'b1),
.ena(1'b1),
.clk(~lvds_dffd_clk),
.q(dffd_out));
assign lvds_dffd_clk = (l_enable0_counter == "l0") ? l0_clk : (l_enable0_counter == "l1") ? l1_clk : 1'b0;
assign nce_l0 = (l_enable0_counter == "l0") ? dffd_out : 1'b0;
assign nce_l1 = (l_enable0_counter == "l1") ? dffd_out : 1'b0;
cyclone_scale_cntr g1 ( .clk(vco_out[i_g1_ph]),
.reset(areset_ipd || (!ena_ipd) || stop_vco),
.cout(g1_clk),
.high(g1_high_val),
.low(g1_low_val),
.initial_value(g1_initial_val),
.mode(g1_mode_val),
.time_delay(g1_time_delay_val),
.ph_tap(i_g1_ph));
cyclone_scale_cntr g2 ( .clk(vco_out[i_g2_ph]),
.reset(areset_ipd || (!ena_ipd) || stop_vco),
.cout(g2_clk),
.high(g2_high_val),
.low(g2_low_val),
.initial_value(g2_initial_val),
.mode(g2_mode_val),
.time_delay(g2_time_delay_val),
.ph_tap(i_g2_ph));
cyclone_scale_cntr g3 ( .clk(vco_out[i_g3_ph]),
.reset(areset_ipd || (!ena_ipd) || stop_vco),
.cout(g3_clk),
.high(g3_high_val),
.low(g3_low_val),
.initial_value(g3_initial_val),
.mode(g3_mode_val),
.time_delay(g3_time_delay_val),
.ph_tap(i_g3_ph));
assign cntr_e0_initial = (l_operation_mode == "external_feedback" && ext_fbk_cntr == "e0") ? 1 : e0_initial_val;
assign cntr_e0_delay = (l_operation_mode == "external_feedback" && ext_fbk_cntr == "e0") ? ext_fbk_delay : e0_time_delay_val;
cyclone_scale_cntr e0 ( .clk(vco_out[i_e0_ph]),
.reset(areset_ipd || (!ena_ipd) || stop_vco),
.cout(e0_clk),
.high(e0_high_val),
.low(e0_low_val),
.initial_value(cntr_e0_initial),
.mode(e0_mode_val),
.time_delay(cntr_e0_delay),
.ph_tap(i_e0_ph));
assign cntr_e1_initial = (l_operation_mode == "external_feedback" && ext_fbk_cntr == "e1") ? 1 : e1_initial_val;
assign cntr_e1_delay = (l_operation_mode == "external_feedback" && ext_fbk_cntr == "e1") ? ext_fbk_delay : e1_time_delay_val;
cyclone_scale_cntr e1 ( .clk(vco_out[i_e1_ph]),
.reset(areset_ipd || (!ena_ipd) || stop_vco),
.cout(e1_clk),
.high(e1_high_val),
.low(e1_low_val),
.initial_value(cntr_e1_initial),
.mode(e1_mode_val),
.time_delay(cntr_e1_delay),
.ph_tap(i_e1_ph));
assign cntr_e2_initial = (l_operation_mode == "external_feedback" && ext_fbk_cntr == "e2") ? 1 : e2_initial_val;
assign cntr_e2_delay = (l_operation_mode == "external_feedback" && ext_fbk_cntr == "e2") ? ext_fbk_delay : e2_time_delay_val;
cyclone_scale_cntr e2 ( .clk(vco_out[i_e2_ph]),
.reset(areset_ipd || (!ena_ipd) || stop_vco),
.cout(e2_clk),
.high(e2_high_val),
.low(e2_low_val),
.initial_value(cntr_e2_initial),
.mode(e2_mode_val),
.time_delay(cntr_e2_delay),
.ph_tap(i_e2_ph));
assign cntr_e3_initial = (l_operation_mode == "external_feedback" && ext_fbk_cntr == "e3") ? 1 : e3_initial_val;
assign cntr_e3_delay = (l_operation_mode == "external_feedback" && ext_fbk_cntr == "e3") ? ext_fbk_delay : e3_time_delay_val;
cyclone_scale_cntr e3 ( .clk(vco_out[i_e3_ph]),
.reset(areset_ipd || (!ena_ipd) || stop_vco),
.cout(e3_clk),
.high(e3_high_val),
.low(e3_low_val),
.initial_value(cntr_e3_initial),
.mode(e3_mode_val),
.time_delay(cntr_e3_delay),
.ph_tap(i_e3_ph));
always @((vco_out[i_l0_ph] && is_fast_pll) or posedge areset_ipd or negedge ena_ipd or stop_vco)
begin
if ((areset_ipd == 1'b1) || (ena_ipd == 1'b0) || (stop_vco == 1'b1))
begin
l0_count = 1;
l0_got_first_rising_edge = 0;
end
else begin
if (nce_l0 == 1'b0)
begin
if (l0_got_first_rising_edge == 1'b0)
begin
if (vco_out[i_l0_ph] == 1'b1 && vco_out[i_l0_ph] != vco_l0_last_value)
l0_got_first_rising_edge = 1;
end
else if (vco_out[i_l0_ph] != vco_l0_last_value)
begin
l0_count = l0_count + 1;
if (l0_count == (l0_high_val + l0_low_val) * 2)
l0_count = 1;
end
end
if (vco_out[i_l0_ph] == 1'b0 && vco_out[i_l0_ph] != vco_l0_last_value)
begin
if (l0_count == 1)
begin
l0_tmp = 1;
l0_got_first_rising_edge = 0;
end
else l0_tmp = 0;
end
end
vco_l0_last_value = vco_out[i_l0_ph];
end
always @((vco_out[i_l1_ph] && is_fast_pll) or posedge areset_ipd or negedge ena_ipd or stop_vco)
begin
if (areset_ipd == 1'b1 || ena_ipd == 1'b0 || stop_vco == 1'b1)
begin
l1_count = 1;
l1_got_first_rising_edge = 0;
end
else begin
if (nce_l1 == 1'b0)
begin
if (l1_got_first_rising_edge == 1'b0)
begin
if (vco_out[i_l1_ph] == 1'b1 && vco_out[i_l1_ph] != vco_l1_last_value)
l1_got_first_rising_edge = 1;
end
else if (vco_out[i_l1_ph] != vco_l1_last_value)
begin
l1_count = l1_count + 1;
if (l1_count == (l1_high_val + l1_low_val) * 2)
l1_count = 1;
end
end
if (vco_out[i_l1_ph] == 1'b0 && vco_out[i_l1_ph] != vco_l1_last_value)
begin
if (l1_count == 1)
begin
l1_tmp = 1;
l1_got_first_rising_edge = 0;
end
else l1_tmp = 0;
end
end
vco_l1_last_value = vco_out[i_l1_ph];
end
assign enable0_tmp = (l_enable0_counter == "l0") ? l0_tmp : l1_tmp;
assign enable1_tmp = (l_enable1_counter == "l0") ? l0_tmp : l1_tmp;
always @ (inclk_n or ena_ipd or areset_ipd)
begin
if (areset_ipd == 'b1)
begin
gate_count = 0;
gate_out = 0;
end
else if (inclk_n == 'b1 && inclk_last_value != inclk_n)
if (ena_ipd == 'b1)
begin
gate_count = gate_count + 1;
if (gate_count == gate_lock_counter)
gate_out = 1;
end
inclk_last_value = inclk_n;
end
assign locked = (l_gate_lock_signal == "yes") ? gate_out && locked_tmp : locked_tmp;
always @ (scanclk_ipd or scanaclr_ipd)
begin
if (scanaclr_ipd === 1'b1 && scanaclr_last_value === 1'b0)
scanaclr_rising_time = $time;
else if (scanaclr_ipd === 1'b0 && scanaclr_last_value === 1'b1)
begin
scanaclr_falling_time = $time;
// check for scanaclr active pulse width
if ($time - scanaclr_rising_time < TRST)
begin
scanclr_violation = 1;
$display ("Warning : Detected SCANACLR ACTIVE pulse width violation. Required is 5000 ps, actual is %0t. Reconfiguration may not work.", $time - scanaclr_rising_time);
$display ("Time: %0t Instance: %m", $time);
end
else begin
scanclr_violation = 0;
for (i = 0; i <= scan_chain_length; i = i + 1)
scan_data[i] = 0;
end
got_first_scanclk_after_scanclr_inactive_edge = 0;
end
else if ((scanclk_ipd === 'b1 && scanclk_last_value !== scanclk_ipd) && (got_first_scanclk_after_scanclr_inactive_edge === 1'b0) && ($time - scanaclr_falling_time < TRSTCLK))
begin
scanclr_clk_violation = 1;
$display ("Warning : Detected SCANACLR INACTIVE time violation before rising edge of SCANCLK. Required is 5000 ps, actual is %0t. Reconfiguration may not work.", $time - scanaclr_falling_time);
$display ("Time: %0t Instance: %m", $time);
got_first_scanclk_after_scanclr_inactive_edge = 1;
end
else if (scanclk_ipd == 'b1 && scanclk_last_value != scanclk_ipd && scanaclr_ipd === 1'b0)
begin
if (pll_in_quiet_period && ($time - start_quiet_time < quiet_time))
begin
$display("Time: %0t", $time, " Warning : Detected transition on SCANCLK during quiet time. PLL may not function correctly.");
$display ("Time: %0t Instance: %m", $time);
quiet_period_violation = 1;
end
else begin
pll_in_quiet_period = 0;
for (j = scan_chain_length-1; j >= 1; j = j - 1)
begin
scan_data[j] = scan_data[j - 1];
end
scan_data[0] = scandata_ipd;
end
if (got_first_scanclk_after_scanclr_inactive_edge === 1'b0)
begin
got_first_scanclk_after_scanclr_inactive_edge = 1;
scanclr_clk_violation = 0;
end
end
else if (scanclk_ipd === 1'b0 && scanclk_last_value !== scanclk_ipd && scanaclr_ipd === 1'b0)
begin
if (pll_in_quiet_period && ($time - start_quiet_time < quiet_time))
begin
$display("Time: %0t", $time, " Warning : Detected transition on SCANCLK during quiet time. PLL may not function correctly.");
$display ("Time: %0t Instance: %m", $time);
quiet_period_violation = 1;
end
else if (scan_data[scan_chain_length-1] == 1'b1)
begin
pll_in_quiet_period = 1;
quiet_period_violation = 0;
reconfig_err = 0;
start_quiet_time = $time;
// initiate transfer
scandataout_tmp <= 1'b1;
quiet_time = slowest_clk ( l0_high_val+l0_low_val, l0_mode_val,
l1_high_val+l1_low_val, l1_mode_val,
g0_high_val+g0_low_val, g0_mode_val,
g1_high_val+g1_low_val, g1_mode_val,
g2_high_val+g2_low_val, g2_mode_val,
g3_high_val+g3_low_val, g3_mode_val,
e0_high_val+e0_low_val, e0_mode_val,
e1_high_val+e1_low_val, e1_mode_val,
e2_high_val+e2_low_val, e2_mode_val,
e3_high_val+e3_low_val, e3_mode_val,
l_scan_chain,
refclk_period, m_val);
scandataout_trigger <= #(quiet_time) ~scandataout_trigger;
transfer <= 1;
end
end
scanclk_last_value = scanclk_ipd;
scanaclr_last_value = scanaclr_ipd;
end
always @(scandataout_trigger)
begin
if (areset_ipd === 1'b0)
scandataout_tmp <= 1'b0;
end
always @(posedge transfer)
begin
if (transfer == 1'b1)
begin
$display("NOTE : Reconfiguring PLL");
$display ("Time: %0t Instance: %m", $time);
if (l_scan_chain == "long")
begin
// cntr e3
error = 0;
if (scan_data[273] == 1'b1)
begin
e3_mode_val = "bypass";
if (scan_data[283] == 1'b1)
begin
e3_mode_val = "off";
$display("Warning : The specified bit settings will turn OFF the E3 counter. It cannot be turned on unless the part is re-initialized.");
$display ("Time: %0t Instance: %m", $time);
end
end
else if (scan_data[283] == 1'b1)
e3_mode_val = "odd";
else
e3_mode_val = "even";
// before reading delay bits, clear e3_time_delay_val
e3_time_delay_val = 32'b0;
e3_time_delay_val = scan_data[287:284];
e3_time_delay_val = e3_time_delay_val * 250;
if (e3_time_delay_val > 3000)
e3_time_delay_val = 3000;
e3_high_val[8:0] <= scan_data[272:264];
e3_low_val[8:0] <= scan_data[282:274];
if (scan_data[272:264] == 9'b000000000)
e3_high_val[9:0] <= 10'b1000000000;
else
e3_high_val[9] <= 1'b0;
if (scan_data[282:274] == 9'b000000000)
e3_low_val[9:0] <= 10'b1000000000;
else
e3_low_val[9] <= 1'b0;
if (ext_fbk_cntr == "e3")
begin
ext_fbk_cntr_high = e3_high_val;
ext_fbk_cntr_low = e3_low_val;
ext_fbk_cntr_delay = e3_time_delay_val;
ext_fbk_cntr_mode = e3_mode_val;
end
// cntr e2
if (scan_data[249] == 1'b1)
begin
e2_mode_val = "bypass";
if (scan_data[259] == 1'b1)
begin
e2_mode_val = "off";
$display("Warning : The specified bit settings will turn OFF the E2 counter. It cannot be turned on unless the part is re-initialized.");
$display ("Time: %0t Instance: %m", $time);
end
end
else if (scan_data[259] == 1'b1)
e2_mode_val = "odd";
else
e2_mode_val = "even";
e2_time_delay_val = 32'b0;
e2_time_delay_val = scan_data[263:260];
e2_time_delay_val = e2_time_delay_val * 250;
if (e2_time_delay_val > 3000)
e2_time_delay_val = 3000;
e2_high_val[8:0] <= scan_data[248:240];
e2_low_val[8:0] <= scan_data[258:250];
if (scan_data[248:240] == 9'b000000000)
e2_high_val[9:0] <= 10'b1000000000;
else
e2_high_val[9] <= 1'b0;
if (scan_data[258:250] == 9'b000000000)
e2_low_val[9:0] <= 10'b1000000000;
else
e2_low_val[9] <= 1'b0;
if (ext_fbk_cntr == "e2")
begin
ext_fbk_cntr_high = e2_high_val;
ext_fbk_cntr_low = e2_low_val;
ext_fbk_cntr_delay = e2_time_delay_val;
ext_fbk_cntr_mode = e2_mode_val;
end
// cntr e1
if (scan_data[225] == 1'b1)
begin
e1_mode_val = "bypass";
if (scan_data[235] == 1'b1)
begin
e1_mode_val = "off";
$display("Warning : The specified bit settings will turn OFF the E1 counter. It cannot be turned on unless the part is re-initialized.");
$display ("Time: %0t Instance: %m", $time);
end
end
else if (scan_data[235] == 1'b1)
e1_mode_val = "odd";
else
e1_mode_val = "even";
e1_time_delay_val = 32'b0;
e1_time_delay_val = scan_data[239:236];
e1_time_delay_val = e1_time_delay_val * 250;
if (e1_time_delay_val > 3000)
e1_time_delay_val = 3000;
e1_high_val[8:0] <= scan_data[224:216];
e1_low_val[8:0] <= scan_data[234:226];
if (scan_data[224:216] == 9'b000000000)
e1_high_val[9:0] <= 10'b1000000000;
else
e1_high_val[9] <= 1'b0;
if (scan_data[234:226] == 9'b000000000)
e1_low_val[9:0] <= 10'b1000000000;
else
e1_low_val[9] <= 1'b0;
if (ext_fbk_cntr == "e1")
begin
ext_fbk_cntr_high = e1_high_val;
ext_fbk_cntr_low = e1_low_val;
ext_fbk_cntr_delay = e1_time_delay_val;
ext_fbk_cntr_mode = e1_mode_val;
end
// cntr e0
if (scan_data[201] == 1'b1)
begin
e0_mode_val = "bypass";
if (scan_data[211] == 1'b1)
begin
e0_mode_val = "off";
$display("Warning : The specified bit settings will turn OFF the E0 counter. It cannot be turned on unless the part is re-initialized.");
$display ("Time: %0t Instance: %m", $time);
end
end
else if (scan_data[211] == 1'b1)
e0_mode_val = "odd";
else
e0_mode_val = "even";
e0_time_delay_val = 32'b0;
e0_time_delay_val = scan_data[215:212];
e0_time_delay_val = e0_time_delay_val * 250;
if (e0_time_delay_val > 3000)
e0_time_delay_val = 3000;
e0_high_val[8:0] <= scan_data[200:192];
e0_low_val[8:0] <= scan_data[210:202];
if (scan_data[200:192] == 9'b000000000)
e0_high_val[9:0] <= 10'b1000000000;
else
e0_high_val[9] <= 1'b0;
if (scan_data[210:202] == 9'b000000000)
e0_low_val[9:0] <= 10'b1000000000;
else
e0_low_val[9] <= 1'b0;
if (ext_fbk_cntr == "e0")
begin
ext_fbk_cntr_high = e0_high_val;
ext_fbk_cntr_low = e0_low_val;
ext_fbk_cntr_delay = e0_time_delay_val;
ext_fbk_cntr_mode = e0_mode_val;
end
end
// cntr l1
if (scan_data[177] == 1'b1)
begin
l1_mode_val = "bypass";
if (scan_data[187] == 1'b1)
begin
l1_mode_val = "off";
$display("Warning : The specified bit settings will turn OFF the L1 counter. It cannot be turned on unless the part is re-initialized.");
$display ("Time: %0t Instance: %m", $time);
end
end
else if (scan_data[187] == 1'b1)
l1_mode_val = "odd";
else
l1_mode_val = "even";
l1_time_delay_val = 32'b0;
l1_time_delay_val = scan_data[191:188];
l1_time_delay_val = l1_time_delay_val * 250;
if (l1_time_delay_val > 3000)
l1_time_delay_val = 3000;
l1_high_val[8:0] <= scan_data[176:168];
l1_low_val[8:0] <= scan_data[186:178];
if (scan_data[176:168] == 9'b000000000)
l1_high_val[9:0] <= 10'b1000000000;
else
l1_high_val[9] <= 1'b0;
if (scan_data[186:178] == 9'b000000000)
l1_low_val[9:0] <= 10'b1000000000;
else
l1_low_val[9] <= 1'b0;
// cntr l0
if (scan_data[153] == 1'b1)
begin
l0_mode_val = "bypass";
if (scan_data[163] == 1'b1)
begin
l0_mode_val = "off";
$display("Warning : The specified bit settings will turn OFF the L0 counter. It cannot be turned on unless the part is re-initialized.");
$display ("Time: %0t Instance: %m", $time);
end
end
else if (scan_data[163] == 1'b1)
l0_mode_val = "odd";
else
l0_mode_val = "even";
l0_time_delay_val = 32'b0;
l0_time_delay_val = scan_data[167:164];
l0_time_delay_val = l0_time_delay_val * 250;
if (l0_time_delay_val > 3000)
l0_time_delay_val = 3000;
l0_high_val[8:0] <= scan_data[152:144];
l0_low_val[8:0] <= scan_data[162:154];
if (scan_data[152:144] == 9'b000000000)
l0_high_val[9:0] <= 10'b1000000000;
else
l0_high_val[9] <= 1'b0;
if (scan_data[162:154] == 9'b000000000)
l0_low_val[9:0] <= 10'b1000000000;
else
l0_low_val[9] <= 1'b0;
// cntr g3
if (scan_data[129] == 1'b1)
begin
g3_mode_val = "bypass";
if (scan_data[139] == 1'b1)
begin
g3_mode_val = "off";
$display("Warning : The specified bit settings will turn OFF the G3 counter. It cannot be turned on unless the part is re-initialized.");
$display ("Time: %0t Instance: %m", $time);
end
end
else if (scan_data[139] == 1'b1)
g3_mode_val = "odd";
else
g3_mode_val = "even";
g3_time_delay_val = 32'b0;
g3_time_delay_val = scan_data[143:140];
g3_time_delay_val = g3_time_delay_val * 250;
if (g3_time_delay_val > 3000)
g3_time_delay_val = 3000;
g3_high_val[8:0] <= scan_data[128:120];
g3_low_val[8:0] <= scan_data[138:130];
if (scan_data[128:120] == 9'b000000000)
g3_high_val[9:0] <= 10'b1000000000;
else
g3_high_val[9] <= 1'b0;
if (scan_data[138:130] == 9'b000000000)
g3_low_val[9:0] <= 10'b1000000000;
else
g3_low_val[9] <= 1'b0;
// cntr g2
if (scan_data[105] == 1'b1)
begin
g2_mode_val = "bypass";
if (scan_data[115] == 1'b1)
begin
g2_mode_val = "off";
$display("Warning : The specified bit settings will turn OFF the G2 counter. It cannot be turned on unless the part is re-initialized.");
$display ("Time: %0t Instance: %m", $time);
end
end
else if (scan_data[115] == 1'b1)
g2_mode_val = "odd";
else
g2_mode_val = "even";
g2_time_delay_val = 32'b0;
g2_time_delay_val = scan_data[119:116];
g2_time_delay_val = g2_time_delay_val * 250;
if (g2_time_delay_val > 3000)
g2_time_delay_val = 3000;
g2_high_val[8:0] <= scan_data[104:96];
g2_low_val[8:0] <= scan_data[114:106];
if (scan_data[104:96] == 9'b000000000)
g2_high_val[9:0] <= 10'b1000000000;
else
g2_high_val[9] <= 1'b0;
if (scan_data[114:106] == 9'b000000000)
g2_low_val[9:0] <= 10'b1000000000;
else
g2_low_val[9] <= 1'b0;
// cntr g1
if (scan_data[81] == 1'b1)
begin
g1_mode_val = "bypass";
if (scan_data[91] == 1'b1)
begin
g1_mode_val = "off";
$display("Warning : The specified bit settings will turn OFF the G1 counter. It cannot be turned on unless the part is re-initialized.");
$display ("Time: %0t Instance: %m", $time);
end
end
else if (scan_data[91] == 1'b1)
g1_mode_val = "odd";
else
g1_mode_val = "even";
g1_time_delay_val = 32'b0;
g1_time_delay_val = scan_data[95:92];
g1_time_delay_val = g1_time_delay_val * 250;
if (g1_time_delay_val > 3000)
g1_time_delay_val = 3000;
g1_high_val[8:0] <= scan_data[80:72];
g1_low_val[8:0] <= scan_data[90:82];
if (scan_data[80:72] == 9'b000000000)
g1_high_val[9:0] <= 10'b1000000000;
else
g1_high_val[9] <= 1'b0;
if (scan_data[90:82] == 9'b000000000)
g1_low_val[9:0] <= 10'b1000000000;
else
g1_low_val[9] <= 1'b0;
// cntr g0
if (scan_data[57] == 1'b1)
begin
g0_mode_val = "bypass";
if (scan_data[67] == 1'b1)
begin
g0_mode_val = "off";
$display("Warning : The specified bit settings will turn OFF the G0 counter. It cannot be turned on unless the part is re-initialized.");
$display ("Time: %0t Instance: %m", $time);
end
end
else if (scan_data[67] == 1'b1)
g0_mode_val = "odd";
else
g0_mode_val = "even";
g0_time_delay_val = 32'b0;
g0_time_delay_val = scan_data[71:68];
g0_time_delay_val = g0_time_delay_val * 250;
if (g0_time_delay_val > 3000)
g0_time_delay_val = 3000;
g0_high_val[8:0] <= scan_data[56:48];
g0_low_val[8:0] <= scan_data[66:58];
if (scan_data[56:48] == 9'b000000000)
g0_high_val[9:0] <= 10'b1000000000;
else
g0_high_val[9] <= 1'b0;
if (scan_data[66:58] == 9'b000000000)
g0_low_val[9:0] <= 10'b1000000000;
else
g0_low_val[9] <= 1'b0;
// cntr M
error = 0;
m_val_tmp = 0;
m_val_tmp[8:0] = scan_data[32:24];
if (scan_data[33] !== 1'b1)
begin
if (m_val_tmp[8:0] == 9'b000000001)
begin
reconfig_err = 1;
error = 1;
$display ("Warning : Illegal 1 value for M counter. Instead, the M counter should be BYPASSED. Reconfiguration may not work.");
$display ("Time: %0t Instance: %m", $time);
end
else if (m_val_tmp[8:0] == 9'b000000000)
m_val_tmp[9:0] = 10'b1000000000;
if (error == 1'b0)
begin
if (m_mode_val === "bypass")
$display ("Warning : M counter switched from BYPASS mode to enabled (M modulus = %d). PLL may lose lock.", m_val_tmp[9:0]);
else
$display("PLL reconfigured with : M modulus = %d ", m_val_tmp[9:0]);
$display ("Time: %0t Instance: %m", $time);
m_mode_val = "";
end
end
else if (scan_data[33] == 1'b1)
begin
if (scan_data[24] !== 1'b0)
begin
reconfig_err = 1;
error = 1;
$display ("Warning : Illegal value for counter M in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work.");
$display ("Time: %0t Instance: %m", $time);
end
else begin
if (m_mode_val !== "bypass")
$display ("Warning : M counter switched from enabled to BYPASS mode. PLL may lose lock.");
m_val_tmp[9:0] = 10'b0000000001;
m_mode_val = "bypass";
$display("PLL reconfigured with : M modulus = %d ", m_val_tmp[9:0]);
$display ("Time: %0t Instance: %m", $time);
end
end
if (skip_vco == "on")
m_val_tmp[9:0] = 10'b0000000001;
// cntr M2
if (ss > 0)
begin
error = 0;
m2_val[8:0] = scan_data[42:34];
if (scan_data[43] !== 1'b1)
begin
if (m2_val[8:0] == 9'b000000001)
begin
reconfig_err = 1;
error = 1;
$display ("Warning : Illegal 1 value for M2 counter. Instead, the M2 counter should be BYPASSED. Reconfiguration may not work.");
$display ("Time: %0t Instance: %m", $time);
end
else if (m2_val[8:0] == 9'b000000000)
m2_val[9:0] = 10'b1000000000;
if (error == 1'b0)
begin
if (m2_mode_val === "bypass")
begin
$display ("Warning : M2 counter switched from BYPASS mode to enabled (M2 modulus = %d). Pll may lose lock.", m2_val[9:0]);
$display ("Time: %0t Instance: %m", $time);
end
else
begin
$display(" M2 modulus = %d ", m2_val[9:0]);
$display ("Time: %0t Instance: %m", $time);
end
m2_mode_val = "";
end
end
else if (scan_data[43] == 1'b1)
begin
if (scan_data[34] !== 1'b0)
begin
reconfig_err = 1;
error = 1;
$display ("Warning : Illegal value for counter M2 in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work.");
$display ("Time: %0t Instance: %m", $time);
end
else begin
if (m2_mode_val !== "bypass")
begin
$display ("Warning : M2 counter switched from enabled to BYPASS mode. PLL may lose lock.");
end
m2_val[9:0] = 10'b0000000001;
m2_mode_val = "bypass";
$display(" M2 modulus = %d ", m2_val[9:0]);
$display ("Time: %0t Instance: %m", $time);
end
end
if (m_mode_val != m2_mode_val)
begin
reconfig_err = 1;
error = 1;
$display ("Warning : Incompatible modes for M1/M2 counters. Either both should be BYASSED or both NON-BYPASSED. Reconfiguration may not work.");
$display ("Time: %0t Instance: %m", $time);
end
end
m_time_delay_val = 32'b0;
m_time_delay_val = scan_data[47:44];
m_time_delay_val = m_time_delay_val * 250;
if (m_time_delay_val > 3000)
m_time_delay_val = 3000;
if (skip_vco == "on")
m_time_delay_val = 32'b0;
$display(" M time delay = %0d", m_time_delay_val);
$display ("Time: %0t Instance: %m", $time);
// cntr N
error = 0;
n_val_tmp[8:0] = scan_data[8:0];
n_val_tmp[9] = 1'b0;
if (scan_data[9] !== 1'b1)
begin
if (n_val_tmp[8:0] == 9'b000000001)
begin
reconfig_err = 1;
error = 1;
$display ("Warning : Illegal 1 value for N counter. Instead, the N counter should be BYPASSED. Reconfiguration may not work.");
$display ("Time: %0t Instance: %m", $time);
end
else if (n_val_tmp[8:0] == 9'b000000000)
n_val_tmp[9:0] = 10'b1000000000;
if (error == 1'b0)
begin
if (n_mode_val === "bypass")
begin
$display ("Warning : N counter switched from BYPASS mode to enabled (N modulus = %d). PLL may lose lock.", n_val_tmp[9:0]);
$display ("Time: %0t Instance: %m", $time);
end
else
begin
$display(" N modulus = %d ", n_val_tmp[9:0]);
$display ("Time: %0t Instance: %m", $time);
end
n_mode_val = "";
end
end
else if (scan_data[9] == 1'b1) // bypass
begin
if (scan_data[0] !== 1'b0)
begin
reconfig_err = 1;
error = 1;
$display ("Warning : Illegal value for counter N in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work.");
$display ("Time: %0t Instance: %m", $time);
end
else begin
if (n_mode_val !== "bypass")
begin
$display ("Warning : N counter switched from enabled to BYPASS mode. PLL may lose lock.");
$display ("Time: %0t Instance: %m", $time);
end
n_val_tmp[9:0] = 10'b0000000001;
n_mode_val = "bypass";
$display(" N modulus = %d ", n_val_tmp[9:0]);
$display ("Time: %0t Instance: %m", $time);
end
end
// cntr N2
if (ss > 0)
begin
error = 0;
n2_val[8:0] = scan_data[18:10];
if (scan_data[19] !== 1'b1)
begin
if (n2_val[8:0] == 9'b000000001)
begin
reconfig_err = 1;
error = 1;
$display ("Warning : Illegal 1 value for N2 counter. Instead, the N2 counter should be BYPASSED. Reconfiguration may not work.");
$display ("Time: %0t Instance: %m", $time);
end
else if (n2_val[8:0] == 9'b000000000)
n2_val = 10'b1000000000;
if (error == 1'b0)
begin
if (n2_mode_val === "bypass")
begin
$display ("Warning : N2 counter switched from BYPASS mode to enabled (N2 modulus = %d). PLL may lose lock.", n2_val[9:0]);
$display ("Time: %0t Instance: %m", $time);
end
else
begin
$display(" N2 modulus = %d ", n2_val[9:0]);
$display ("Time: %0t Instance: %m", $time);
end
n2_mode_val = "";
end
end
else if (scan_data[19] == 1'b1) // bypass
begin
if (scan_data[10] !== 1'b0)
begin
reconfig_err = 1;
error = 1;
$display ("Warning : Illegal value for counter N2 in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work.");
$display ("Time: %0t Instance: %m", $time);
end
else begin
if (n2_mode_val !== "bypass")
begin
$display ("Warning : N2 counter switched from enabled to BYPASS mode. PLL may lose lock.");
$display ("Time: %0t Instance: %m", $time);
end
n2_val[9:0] = 10'b0000000001;
n2_mode_val = "bypass";
$display(" N2 modulus = %d ", n2_val[9:0]);
$display ("Time: %0t Instance: %m", $time);
end
end
if (n_mode_val != n2_mode_val)
begin
reconfig_err = 1;
error = 1;
$display ("Warning : Incompatible modes for N1/N2 counters. Either both should be BYASSED or both NON-BYPASSED.");
$display ("Time: %0t Instance: %m", $time);
end
end // ss > 0
n_time_delay_val = 32'b0;
n_time_delay_val = scan_data[23:20];
n_time_delay_val = n_time_delay_val * 250;
if (n_time_delay_val > 3000)
n_time_delay_val = 3000;
$display(" N time delay = %0d", n_time_delay_val);
$display ("Time: %0t Instance: %m", $time);
transfer <= 0;
// clear the scan_chain
for (i = 0; i <= scan_chain_length; i = i + 1)
scan_data[i] = 0;
end
end
always @(negedge transfer)
begin
if (l_scan_chain == "long")
begin
$display(" E3 high = %d, E3 low = %d, E3 mode = %s, E3 time delay = %0d", e3_high_val[9:0], e3_low_val[9:0], e3_mode_val, e3_time_delay_val);
$display(" E2 high = %d, E2 low = %d, E2 mode = %s, E2 time delay = %0d", e2_high_val[9:0], e2_low_val[9:0], e2_mode_val, e2_time_delay_val);
$display(" E1 high = %d, E1 low = %d, E1 mode = %s, E1 time delay = %0d", e1_high_val[9:0], e1_low_val[9:0], e1_mode_val, e1_time_delay_val);
$display(" E0 high = %d, E0 low = %d, E0 mode = %s, E0 time delay = %0d", e0_high_val[9:0], e0_low_val[9:0], e0_mode_val, e0_time_delay_val);
end
$display(" L1 high = %d, L1 low = %d, L1 mode = %s, L1 time delay = %0d", l1_high_val[9:0], l1_low_val[9:0], l1_mode_val, l1_time_delay_val);
$display(" L0 high = %d, L0 low = %d, L0 mode = %s, L0 time delay = %0d", l0_high_val[9:0], l0_low_val[9:0], l0_mode_val, l0_time_delay_val);
$display(" G3 high = %d, G3 low = %d, G3 mode = %s, G3 time delay = %0d", g3_high_val[9:0], g3_low_val[9:0], g3_mode_val, g3_time_delay_val);
$display(" G2 high = %d, G2 low = %d, G2 mode = %s, G2 time delay = %0d", g2_high_val[9:0], g2_low_val[9:0], g2_mode_val, g2_time_delay_val);
$display(" G1 high = %d, G1 low = %d, G1 mode = %s, G1 time delay = %0d", g1_high_val[9:0], g1_low_val[9:0], g1_mode_val, g1_time_delay_val);
$display(" G0 high = %d, G0 low = %d, G0 mode = %s, G0 time delay = %0d", g0_high_val[9:0], g0_low_val[9:0], g0_mode_val, g0_time_delay_val);
$display ("Time: %0t Instance: %m", $time);
end
always @(schedule_vco or areset_ipd or ena_ipd)
begin
sched_time = 0;
for (i = 0; i <= 7; i=i+1)
last_phase_shift[i] = phase_shift[i];
cycle_to_adjust = 0;
l_index = 1;
m_times_vco_period = new_m_times_vco_period;
// give appropriate messages
// if areset was asserted
if (areset_ipd == 1'b1 && areset_ipd_last_value !== areset_ipd)
begin
$display (" Note : %s PLL was reset", family_name);
$display ("Time: %0t Instance: %m", $time);
end
// if areset is deasserted
if (areset_ipd === 1'b0 && areset_ipd_last_value === 1'b1)
begin
// deassert scandataout now and allow reconfig to complete if
// areset was high during reconfig
if (scandataout_tmp === 1'b1)
scandataout_tmp <= #(quiet_time) 1'b0;
end
// if ena was deasserted
if (ena_ipd == 1'b0 && ena_ipd_last_value !== ena_ipd)
begin
$display (" Note : %s PLL was disabled", family_name);
$display ("Time: %0t Instance: %m", $time);
end
// illegal value on areset_ipd
if (areset_ipd === 1'bx && (areset_ipd_last_value === 1'b0 || areset_ipd_last_value === 1'b1))
begin
$display("Warning : Illegal value 'X' detected on ARESET input");
$display ("Time: %0t Instance: %m", $time);
end
if ((schedule_vco !== schedule_vco_last_value) && (areset_ipd == 1'b1 || ena_ipd == 1'b0 || stop_vco == 1'b1))
begin
if (areset_ipd === 1'b1)
pll_is_in_reset = 1;
// drop VCO taps to 0
for (i = 0; i <= 7; i=i+1)
begin
for (j = 0; j <= last_phase_shift[i] + 1; j=j+1)
vco_out[i] <= #(j) 1'b0;
phase_shift[i] = 0;
last_phase_shift[i] = 0;
end
// reset lock parameters
locked_tmp = 0;
if (l_pll_type == "fast")
locked_tmp = 1;
pll_is_locked = 0;
pll_about_to_lock = 0;
cycles_to_lock = 0;
cycles_to_unlock = 0;
got_first_refclk = 0;
got_second_refclk = 0;
refclk_time = 0;
got_first_fbclk = 0;
fbclk_time = 0;
first_fbclk_time = 0;
fbclk_period = 0;
first_schedule = 1;
schedule_offset = 1;
vco_val = 0;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
// reset enable0 and enable1 counter parameters
// l0_count = 1;
// l1_count = 1;
// l0_got_first_rising_edge = 0;
// l1_got_first_rising_edge = 0;
end else if (ena_ipd === 1'b1 && areset_ipd === 1'b0 && stop_vco === 1'b0)
begin
// else note areset deassert time
// note it as refclk_time to prevent false triggering
// of stop_vco after areset
if (areset_ipd === 1'b0 && areset_ipd_last_value === 1'b1 && pll_is_in_reset === 1'b1)
begin
refclk_time = $time;
pll_is_in_reset = 0;
end
// calculate loop_xplier : this will be different from m_val in ext. fbk mode
loop_xplier = m_val;
loop_initial = i_m_initial - 1;
loop_ph = i_m_ph;
loop_time_delay = m_time_delay_val;
if (l_operation_mode == "external_feedback")
begin
if (ext_fbk_cntr_mode == "bypass")
ext_fbk_cntr_modulus = 1;
else
ext_fbk_cntr_modulus = ext_fbk_cntr_high + ext_fbk_cntr_low;
loop_xplier = m_val * (ext_fbk_cntr_modulus);
loop_ph = ext_fbk_cntr_ph;
loop_initial = ext_fbk_cntr_initial - 1 + ((i_m_initial - 1) * (ext_fbk_cntr_modulus));
loop_time_delay = m_time_delay_val + ext_fbk_cntr_delay;
end
// convert initial value to delay
initial_delay = (loop_initial * m_times_vco_period)/loop_xplier;
// convert loop ph_tap to delay
rem = m_times_vco_period % loop_xplier;
vco_per = m_times_vco_period/loop_xplier;
if (rem != 0)
vco_per = vco_per + 1;
fbk_phase = (loop_ph * vco_per)/8;
if (l_operation_mode == "external_feedback")
begin
pull_back_ext_cntr = ext_fbk_cntr_delay + (ext_fbk_cntr_initial - 1) * (m_times_vco_period/loop_xplier) + fbk_phase;
while (pull_back_ext_cntr > refclk_period)
pull_back_ext_cntr = pull_back_ext_cntr - refclk_period;
pull_back_M = m_time_delay_val + (i_m_initial - 1) * (ext_fbk_cntr_modulus) * (m_times_vco_period/loop_xplier);
while (pull_back_M > refclk_period)
pull_back_M = pull_back_M - refclk_period;
end
else begin
pull_back_ext_cntr = 0;
pull_back_M = initial_delay + m_time_delay_val + fbk_phase;
end
total_pull_back = pull_back_M + pull_back_ext_cntr;
if (l_simulation_type == "timing")
total_pull_back = total_pull_back + pll_compensation_delay;
while (total_pull_back > refclk_period)
total_pull_back = total_pull_back - refclk_period;
if (total_pull_back > 0)
offset = refclk_period - total_pull_back;
if (l_operation_mode == "external_feedback")
begin
fbk_delay = pull_back_M;
if (l_simulation_type == "timing")
fbk_delay = fbk_delay + pll_compensation_delay;
ext_fbk_delay = pull_back_ext_cntr - fbk_phase;
end
else begin
fbk_delay = total_pull_back - fbk_phase;
if (fbk_delay < 0)
begin
offset = offset - fbk_phase;
fbk_delay = total_pull_back;
end
end
// assign m_delay
m_delay = fbk_delay;
for (i = 1; i <= loop_xplier; i=i+1)
begin
// adjust cycles
tmp_vco_per = m_times_vco_period/loop_xplier;
if (rem != 0 && l_index <= rem)
begin
tmp_rem = (loop_xplier * l_index) % rem;
cycle_to_adjust = (loop_xplier * l_index) / rem;
if (tmp_rem != 0)
cycle_to_adjust = cycle_to_adjust + 1;
end
if (cycle_to_adjust == i)
begin
tmp_vco_per = tmp_vco_per + 1;
l_index = l_index + 1;
end
// calculate high and low periods
high_time = tmp_vco_per/2;
if (tmp_vco_per % 2 != 0)
high_time = high_time + 1;
low_time = tmp_vco_per - high_time;
// schedule the rising and falling egdes
for (j=0; j<=1; j=j+1)
begin
vco_val = ~vco_val;
if (vco_val == 1'b0)
sched_time = sched_time + high_time;
else
sched_time = sched_time + low_time;
// add offset
if (schedule_offset == 1'b1)
begin
sched_time = sched_time + offset;
schedule_offset = 0;
end
// schedule taps with appropriate phase shifts
for (k = 0; k <= 7; k=k+1)
begin
phase_shift[k] = (k*tmp_vco_per)/8;
if (first_schedule)
vco_out[k] <= #(sched_time + phase_shift[k]) vco_val;
else
vco_out[k] <= #(sched_time + last_phase_shift[k]) vco_val;
end
end
end
if (first_schedule)
begin
vco_val = ~vco_val;
if (vco_val == 1'b0)
sched_time = sched_time + high_time;
else
sched_time = sched_time + low_time;
for (k = 0; k <= 7; k=k+1)
begin
phase_shift[k] = (k*tmp_vco_per)/8;
vco_out[k] <= #(sched_time+phase_shift[k]) vco_val;
end
first_schedule = 0;
end
// this may no longer be required
if (sched_time > 0)
schedule_vco <= #(sched_time) ~schedule_vco;
if (vco_period_was_phase_adjusted)
begin
m_times_vco_period = refclk_period;
new_m_times_vco_period = refclk_period;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 1;
tmp_vco_per = m_times_vco_period/loop_xplier;
for (k = 0; k <= 7; k=k+1)
phase_shift[k] = (k*tmp_vco_per)/8;
end
end
areset_ipd_last_value = areset_ipd;
ena_ipd_last_value = ena_ipd;
schedule_vco_last_value = schedule_vco;
end
always @(pfdena_ipd)
begin
if (pfdena_ipd === 1'b0)
begin
locked_tmp = 1'bx;
pll_is_locked = 0;
cycles_to_lock = 0;
$display (" Note : PFDENA was deasserted");
$display ("Time: %0t Instance: %m", $time);
end
else if (pfdena_ipd === 1'b1 && pfdena_ipd_last_value === 1'b0)
begin
// PFD was disabled, now enabled again
got_first_refclk = 0;
got_second_refclk = 0;
refclk_time = $time;
end
pfdena_ipd_last_value = pfdena_ipd;
end
always @(negedge refclk)
begin
refclk_last_value = refclk;
end
always @(negedge fbclk)
begin
fbclk_last_value = fbclk;
end
always @(posedge refclk or posedge fbclk)
begin
if (refclk == 1'b1 && refclk_last_value !== refclk && areset_ipd === 1'b0)
begin
n_val <= n_val_tmp;
if (! got_first_refclk)
begin
got_first_refclk = 1;
end else
begin
got_second_refclk = 1;
refclk_period = $time - refclk_time;
// check if incoming freq. will cause VCO range to be
// exceeded
if ( (vco_max != 0 && vco_min != 0) && (skip_vco == "off") && (pfdena_ipd === 1'b1) &&
((refclk_period/loop_xplier > vco_max) ||
(refclk_period/loop_xplier < vco_min)) )
begin
if (pll_is_locked == 1'b1)
begin
$display ("Warning : Input clock freq. is not within VCO range. PLL may lose lock");
$display ("Time: %0t Instance: %m", $time);
if (inclk_out_of_range === 1'b1)
begin
// unlock
pll_is_locked = 0;
locked_tmp = 0;
if (l_pll_type == "fast")
locked_tmp = 1;
pll_about_to_lock = 0;
cycles_to_lock = 0;
$display ("Note : %s PLL lost lock", family_name);
$display ("Time: %0t Instance: %m", $time);
first_schedule = 1;
schedule_offset = 1;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
end
end
else begin
if (no_warn == 0)
begin
$display ("Warning : Input clock freq. is not within VCO range. PLL may not lock");
$display ("Time: %0t Instance: %m", $time);
no_warn = 1;
end
end
inclk_out_of_range = 1;
end
else begin
inclk_out_of_range = 0;
end
end
if (stop_vco == 1'b1)
begin
stop_vco = 0;
schedule_vco = ~schedule_vco;
end
refclk_time = $time;
end
if (fbclk == 1'b1 && fbclk_last_value !== fbclk)
begin
m_val <= m_val_tmp;
if (!got_first_fbclk)
begin
got_first_fbclk = 1;
first_fbclk_time = $time;
end
else
fbclk_period = $time - fbclk_time;
// need refclk_period here, so initialized to proper value above
if ( ( ($time - refclk_time > 1.5 * refclk_period) && pfdena_ipd === 1'b1 && pll_is_locked == 1'b1) || ( ($time - refclk_time > 5 * refclk_period) && pfdena_ipd === 1'b1) )
begin
stop_vco = 1;
// reset
got_first_refclk = 0;
got_first_fbclk = 0;
got_second_refclk = 0;
if (pll_is_locked == 1'b1)
begin
pll_is_locked = 0;
locked_tmp = 0;
if (l_pll_type == "fast")
locked_tmp = 1;
$display ("Note : %s PLL lost lock due to loss of input clock", family_name);
$display ("Time: %0t Instance: %m", $time);
end
pll_about_to_lock = 0;
cycles_to_lock = 0;
cycles_to_unlock = 0;
first_schedule = 1;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
end
fbclk_time = $time;
end
if (got_second_refclk && pfdena_ipd === 1'b1 && (!inclk_out_of_range))
begin
// now we know actual incoming period
// if (abs(refclk_period - fbclk_period) > 2)
// begin
// new_m_times_vco_period = refclk_period;
// end
// else if (abs(fbclk_time - refclk_time) <= 2 || (refclk_period - abs(fbclk_time - refclk_time) <= 2))
if (abs(fbclk_time - refclk_time) <= 5 || (got_first_fbclk && abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5))
begin
// considered in phase
if (cycles_to_lock == valid_lock_multiplier - 1)
pll_about_to_lock <= 1;
if (cycles_to_lock == valid_lock_multiplier)
begin
if (pll_is_locked === 1'b0)
begin
$display (" Note : %s PLL locked to incoming clock", family_name);
$display ("Time: %0t Instance: %m", $time);
end
pll_is_locked = 1;
locked_tmp = 1;
if (l_pll_type == "fast")
locked_tmp = 0;
end
// increment lock counter only if the second part of the above
// time check is NOT true
if (!(abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5))
begin
cycles_to_lock = cycles_to_lock + 1;
end
// adjust m_times_vco_period
new_m_times_vco_period = refclk_period;
end else
begin
// if locked, begin unlock
if (pll_is_locked)
begin
cycles_to_unlock = cycles_to_unlock + 1;
if (cycles_to_unlock == invalid_lock_multiplier)
begin
pll_is_locked = 0;
locked_tmp = 0;
if (l_pll_type == "fast")
locked_tmp = 1;
pll_about_to_lock = 0;
cycles_to_lock = 0;
$display ("Note : %s PLL lost lock", family_name);
$display ("Time: %0t Instance: %m", $time);
first_schedule = 1;
schedule_offset = 1;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
end
end
if (abs(refclk_period - fbclk_period) <= 2)
begin
// frequency is still good
if ($time == fbclk_time && (!phase_adjust_was_scheduled))
begin
if (abs(fbclk_time - refclk_time) > refclk_period/2)
begin
if (abs(fbclk_time - refclk_time) > 1.5 * refclk_period)
begin
// input clock may have stopped : do nothing
end
else begin
new_m_times_vco_period = m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted = 1;
end
end else
begin
new_m_times_vco_period = m_times_vco_period - abs(fbclk_time - refclk_time);
vco_period_was_phase_adjusted = 1;
end
end
end else
begin
new_m_times_vco_period = refclk_period;
phase_adjust_was_scheduled = 0;
end
end
end
if (quiet_period_violation == 1'b1 || reconfig_err == 1'b1 || scanclr_violation == 1'b1 || scanclr_clk_violation == 1'b1)
begin
locked_tmp = 0;
if (l_pll_type == "fast")
locked_tmp = 1;
end
refclk_last_value = refclk;
fbclk_last_value = fbclk;
end
assign clk0_tmp = i_clk0_counter == "l0" ? l0_clk : i_clk0_counter == "l1" ? l1_clk : i_clk0_counter == "g0" ? g0_clk : i_clk0_counter == "g1" ? g1_clk : i_clk0_counter == "g2" ? g2_clk : i_clk0_counter == "g3" ? g3_clk : 1'b0;
assign clk0 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? clk0_tmp : 1'bx;
cyclone_dffe ena0_reg ( .D(clkena0_ipd),
.CLRN(1'b1),
.PRN(1'b1),
.ENA(1'b1),
.CLK(!clk0_tmp),
.Q(ena0));
assign clk1_tmp = i_clk1_counter == "l0" ? l0_clk : i_clk1_counter == "l1" ? l1_clk : i_clk1_counter == "g0" ? g0_clk : i_clk1_counter == "g1" ? g1_clk : i_clk1_counter == "g2" ? g2_clk : i_clk1_counter == "g3" ? g3_clk : 1'b0;
assign clk1 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? clk1_tmp : 1'bx;
cyclone_dffe ena1_reg ( .D(clkena1_ipd),
.CLRN(1'b1),
.PRN(1'b1),
.ENA(1'b1),
.CLK(!clk1_tmp),
.Q(ena1));
assign clk2_tmp = i_clk2_counter == "l0" ? l0_clk : i_clk2_counter == "l1" ? l1_clk : i_clk2_counter == "g0" ? g0_clk : i_clk2_counter == "g1" ? g1_clk : i_clk2_counter == "g2" ? g2_clk : i_clk2_counter == "g3" ? g3_clk : 1'b0;
assign clk2 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? clk2_tmp : 1'bx;
cyclone_dffe ena2_reg ( .D(clkena2_ipd),
.CLRN(1'b1),
.PRN(1'b1),
.ENA(1'b1),
.CLK(!clk2_tmp),
.Q(ena2));
assign clk3_tmp = i_clk3_counter == "l0" ? l0_clk : i_clk3_counter == "l1" ? l1_clk : i_clk3_counter == "g0" ? g0_clk : i_clk3_counter == "g1" ? g1_clk : i_clk3_counter == "g2" ? g2_clk : i_clk3_counter == "g3" ? g3_clk : 1'b0;
assign clk3 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? clk3_tmp : 1'bx;
cyclone_dffe ena3_reg ( .D(clkena3_ipd),
.CLRN(1'b1),
.PRN(1'b1),
.ENA(1'b1),
.CLK(!clk3_tmp),
.Q(ena3));
assign clk4_tmp = i_clk4_counter == "l0" ? l0_clk : i_clk4_counter == "l1" ? l1_clk : i_clk4_counter == "g0" ? g0_clk : i_clk4_counter == "g1" ? g1_clk : i_clk4_counter == "g2" ? g2_clk : i_clk4_counter == "g3" ? g3_clk : 1'b0;
assign clk4 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? clk4_tmp : 1'bx;
cyclone_dffe ena4_reg ( .D(clkena4_ipd),
.CLRN(1'b1),
.PRN(1'b1),
.ENA(1'b1),
.CLK(!clk4_tmp),
.Q(ena4));
assign clk5_tmp = i_clk5_counter == "l0" ? l0_clk : i_clk5_counter == "l1" ? l1_clk : i_clk5_counter == "g0" ? g0_clk : i_clk5_counter == "g1" ? g1_clk : i_clk5_counter == "g2" ? g2_clk : i_clk5_counter == "g3" ? g3_clk : 1'b0;
assign clk5 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? clk5_tmp : 1'bx;
cyclone_dffe ena5_reg ( .D(clkena5_ipd),
.CLRN(1'b1),
.PRN(1'b1),
.ENA(1'b1),
.CLK(!clk5_tmp),
.Q(ena5));
assign extclk0_tmp = i_extclk0_counter == "e0" ? e0_clk : i_extclk0_counter == "e1" ? e1_clk : i_extclk0_counter == "e2" ? e2_clk : i_extclk0_counter == "e3" ? e3_clk : i_extclk0_counter == "g0" ? g0_clk : 1'b0;
assign extclk0 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? extclk0_tmp : 1'bx;
cyclone_dffe extena0_reg ( .D(extclkena0_ipd),
.CLRN(1'b1),
.PRN(1'b1),
.ENA(1'b1),
.CLK(!extclk0_tmp),
.Q(extena0));
assign extclk1_tmp = i_extclk1_counter == "e0" ? e0_clk : i_extclk1_counter == "e1" ? e1_clk : i_extclk1_counter == "e2" ? e2_clk : i_extclk1_counter == "e3" ? e3_clk : i_extclk1_counter == "g0" ? g0_clk : 1'b0;
assign extclk1 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? extclk1_tmp : 1'bx;
cyclone_dffe extena1_reg ( .D(extclkena1_ipd),
.CLRN(1'b1),
.PRN(1'b1),
.ENA(1'b1),
.CLK(!extclk1_tmp),
.Q(extena1));
assign extclk2_tmp = i_extclk2_counter == "e0" ? e0_clk : i_extclk2_counter == "e1" ? e1_clk : i_extclk2_counter == "e2" ? e2_clk : i_extclk2_counter == "e3" ? e3_clk : i_extclk2_counter == "g0" ? g0_clk : 1'b0;
assign extclk2 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? extclk2_tmp : 1'bx;
cyclone_dffe extena2_reg ( .D(extclkena2_ipd),
.CLRN(1'b1),
.PRN(1'b1),
.ENA(1'b1),
.CLK(!extclk2_tmp),
.Q(extena2));
assign extclk3_tmp = i_extclk3_counter == "e0" ? e0_clk : i_extclk3_counter == "e1" ? e1_clk : i_extclk3_counter == "e2" ? e2_clk : i_extclk3_counter == "e3" ? e3_clk : i_extclk3_counter == "g0" ? g0_clk : 1'b0;
assign extclk3 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? extclk3_tmp : 1'bx;
cyclone_dffe extena3_reg ( .D(extclkena3_ipd),
.CLRN(1'b1),
.PRN(1'b1),
.ENA(1'b1),
.CLK(!extclk3_tmp),
.Q(extena3));
assign enable_0 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || pll_about_to_lock == 1'b1 ? enable0_tmp : 1'bx;
assign enable_1 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || pll_about_to_lock == 1'b1 ? enable1_tmp : 1'bx;
// ACCELERATE OUTPUTS
and (clk[0], ena0, clk0);
and (clk[1], ena1, clk1);
and (clk[2], ena2, clk2);
and (clk[3], ena3, clk3);
and (clk[4], ena4, clk4);
and (clk[5], ena5, clk5);
and (extclk[0], extena0, extclk0);
and (extclk[1], extena1, extclk1);
and (extclk[2], extena2, extclk2);
and (extclk[3], extena3, extclk3);
and (enable0, 1'b1, enable_0);
and (enable1, 1'b1, enable_1);
and (scandataout, 1'b1, scandataout_tmp);
endmodule // cyclone_pll
//////////////////////////////////////////////////////////////////////////////
//
// Module Name : cyclone_dll
//
// Description : Simulation model for the Cyclone DLL.
//
// Outputs : Delayctrlout output (active high) indicates when the
// DLL locks to the incoming clock
//
//////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module cyclone_dll (clk,
delayctrlout
);
// GLOBAL PARAMETERS
parameter input_frequency = "10000 ps";
parameter phase_shift = "0";
parameter sim_valid_lock = 1;
parameter sim_invalid_lock = 5;
parameter lpm_type = "cyclone_dll";
// INPUT PORTS
input clk;
// OUTPUT PORTS
output delayctrlout;
// INTERNAL NETS AND VARIABLES
reg clk_ipd_last_value;
reg got_first_rising_edge;
reg got_first_falling_edge;
reg dll_is_locked;
reg start_clk_detect;
reg start_clk_detect_last_value;
reg violation;
reg duty_cycle_warn;
reg input_freq_warn;
time clk_ipd_last_rising_edge;
time clk_ipd_last_falling_edge;
integer clk_per_tolerance;
integer duty_cycle;
integer clk_detect_count;
integer half_cycles_to_lock;
integer half_cycles_to_keep_lock;
integer input_period;
// BUFFER INPUTS
wire clk_ipd;
buf (clk_ipd, clk);
// FUNCTIONS
// convert string to integer with sign
function integer str2int;
input [8*16:1] s;
reg [8*16:1] reg_s;
reg [8:1] digit;
reg [8:1] tmp;
integer m, magnitude;
integer sign;
begin
sign = 1;
magnitude = 0;
reg_s = s;
for (m=1; m<=16; m=m+1)
begin
tmp = reg_s[128:121];
digit = tmp & 8'b00001111;
reg_s = reg_s << 8;
// Accumulate ascii digits 0-9 only.
if ((tmp>=48) && (tmp<=57))
magnitude = (magnitude * 10) + digit;
if (tmp == 45)
sign = -1; // Found a '-' character, i.e. number is negative.
end
str2int = sign*magnitude;
end
endfunction
initial
begin
clk_ipd_last_value = 0;
got_first_rising_edge = 0;
got_first_falling_edge = 0;
clk_ipd_last_rising_edge = 0;
clk_ipd_last_falling_edge = 0;
input_period = str2int(input_frequency);
duty_cycle = input_period/2;
clk_per_tolerance = input_period * 0.1;
// if sim_valid_lock == 0, DLL starts out locked.
if (sim_valid_lock == 0)
dll_is_locked = 1;
else
dll_is_locked = 0;
clk_detect_count = 0;
start_clk_detect = 0;
start_clk_detect_last_value = 0;
half_cycles_to_lock = 0;
half_cycles_to_keep_lock = 0;
violation = 0;
duty_cycle_warn = 1;
input_freq_warn = 1;
end
always @(clk_ipd)
begin
if (clk_ipd == 1'b1 && clk_ipd != clk_ipd_last_value)
begin
// rising edge
if (got_first_rising_edge == 1'b0)
begin
got_first_rising_edge = 1;
half_cycles_to_lock = half_cycles_to_lock + 1;
if (sim_valid_lock > 0 && half_cycles_to_lock >= sim_valid_lock && violation == 1'b0)
begin
dll_is_locked <= 1;
$display(" Note : DLL locked to incoming clock.");
$display("Time: %0t Instance: %m", $time);
end
// start the internal clock that will monitor
// the input clock
start_clk_detect <= 1;
end
else
begin
// reset clock event counter
clk_detect_count = 0;
// check for clk_period violation
if ( (($time - clk_ipd_last_rising_edge) < (input_period - clk_per_tolerance)) || (($time - clk_ipd_last_rising_edge) > (input_period + clk_per_tolerance)) )
begin
violation = 1;
if (input_freq_warn === 1'b1)
begin
$display(" Warning : Input frequency violation");
$display("Time: %0t Instance: %m", $time);
input_freq_warn = 0;
end
end
else if ( (($time - clk_ipd_last_falling_edge) < (duty_cycle - clk_per_tolerance/2)) || (($time - clk_ipd_last_falling_edge) > (duty_cycle + clk_per_tolerance/2)) )
begin
// duty cycle violation
violation = 1;
if (duty_cycle_warn === 1'b1)
begin
$display(" Warning : Duty Cycle violation");
$display("Time: %0t Instance: %m", $time);
duty_cycle_warn = 0;
end
end
else
violation = 0;
if (violation)
begin
if (dll_is_locked)
begin
half_cycles_to_keep_lock = half_cycles_to_keep_lock + 1;
if (half_cycles_to_keep_lock > sim_invalid_lock)
begin
dll_is_locked <= 0;
$display(" Warning : DLL lost lock due to input frequency/Duty cycle violation.");
$display("Time: %0t Instance: %m", $time);
// reset lock and unlock counters
half_cycles_to_lock = 0;
half_cycles_to_keep_lock = 0;
got_first_rising_edge = 0;
got_first_falling_edge = 0;
end
end
else
half_cycles_to_lock = 0;
end
else begin
if (dll_is_locked == 1'b0)
begin
// increment lock counter
half_cycles_to_lock = half_cycles_to_lock + 1;
if (half_cycles_to_lock > sim_valid_lock)
begin
dll_is_locked <= 1;
$display(" Note : DLL locked to incoming clock.");
$display("Time: %0t Instance: %m", $time);
end
end
else
half_cycles_to_keep_lock = 0;
end
end
clk_ipd_last_rising_edge = $time;
end
else if (clk_ipd == 1'b0 && clk_ipd != clk_ipd_last_value)
begin
// falling edge
// reset clock event counter
clk_detect_count = 0;
got_first_falling_edge = 1;
if (got_first_rising_edge == 1'b1)
begin
// check for duty cycle violation
if ( (($time - clk_ipd_last_rising_edge) < (duty_cycle - clk_per_tolerance/2)) || (($time - clk_ipd_last_rising_edge) > (duty_cycle + clk_per_tolerance/2)) )
begin
violation = 1;
if (duty_cycle_warn === 1'b1)
begin
$display(" Warning : Duty Cycle violation");
$display("Time: %0t Instance: %m", $time);
duty_cycle_warn = 0;
end
end
else
violation = 0;
if (dll_is_locked)
begin
if (violation)
begin
half_cycles_to_keep_lock = half_cycles_to_keep_lock + 1;
if (half_cycles_to_keep_lock > sim_invalid_lock)
begin
dll_is_locked <= 0;
$display(" Warning : DLL lost lock due to input frequency/Duty cycle violation.");
$display("Time: %0t Instance: %m", $time);
// reset lock and unlock counters
half_cycles_to_lock = 0;
half_cycles_to_keep_lock = 0;
got_first_rising_edge = 0;
got_first_falling_edge = 0;
end
end
else
half_cycles_to_keep_lock = 0;
end
else
begin
if (violation)
begin
// reset_lock_counter
half_cycles_to_lock = 0;
end
else
begin
// increment lock counter
half_cycles_to_lock = half_cycles_to_lock + 1;
end
end
end
else
begin
// first clk edge is falling edge, do nothing
end
clk_ipd_last_falling_edge = $time;
end
else
begin
// illegal value
if (dll_is_locked && (got_first_rising_edge == 1'b1 || got_first_falling_edge == 1'b1))
begin
dll_is_locked <= 0;
// reset lock and unlock counters
half_cycles_to_lock = 0;
half_cycles_to_keep_lock = 0;
got_first_rising_edge = 0;
got_first_falling_edge = 0;
$display(" Error : Illegal value detected on input clock. DLL will lose lock.");
$display("Time: %0t Instance: %m", $time);
end
else if (got_first_rising_edge == 1'b1 || got_first_falling_edge == 1'b1)
begin
// clock started up, then went to 'X'
// this is to weed out the 'X' at start of simulation
$display(" Error : Illegal value detected on input clock.");
$display("Time: %0t Instance: %m", $time);
// reset lock counter
half_cycles_to_lock = 0;
end
end
clk_ipd_last_value = clk_ipd;
end
// ********************************************************************
// The following block generates the internal clock that is used to
// track loss of input clock. A counter counts events on this internal
// clock, and is reset to 0 on event on input clock. If input clock
// flatlines, the counter will exceed the limit and DLL will lose lock.
// Events on internal clock are scheduled at the max. allowable input
// clock tolerance, to allow 'sim_invalid_lock' parameter value = 1.
// ********************************************************************
always @(start_clk_detect)
begin
if (start_clk_detect != start_clk_detect_last_value)
begin
// increment clock event counter
clk_detect_count = clk_detect_count + 1;
if (dll_is_locked)
begin
if (clk_detect_count > sim_invalid_lock)
begin
dll_is_locked = 0;
$display(" Warning : DLL lost lock due to loss of input clock.");
$display("Time: %0t Instance: %m", $time);
// reset lock and unlock counters
half_cycles_to_lock = 0;
half_cycles_to_keep_lock = 0;
got_first_rising_edge = 0;
got_first_falling_edge = 0;
clk_detect_count = 0;
start_clk_detect <= #(input_period/2) 1'b0;
end
else
start_clk_detect <= #(input_period/2 + clk_per_tolerance/2) ~start_clk_detect;
end
else if (clk_detect_count > 10)
begin
$display(" Warning : No input clock. DLL will not lock.");
$display("Time: %0t Instance: %m", $time);
clk_detect_count = 0;
end
else
start_clk_detect <= #(input_period/2 + clk_per_tolerance/2) ~start_clk_detect;
end
// save this event value
start_clk_detect_last_value = start_clk_detect;
end
// ACCELERATE OUTPUTS
and (delayctrlout, 1'b1, dll_is_locked);
endmodule
//--------------------------------------------------------------------
//
// Module Name : cyclone_jtag
//
// Description : Cyclone JTAG Verilog Simulation model
//
//--------------------------------------------------------------------
`timescale 1 ps/1 ps
module cyclone_jtag (
tms,
tck,
tdi,
ntrst,
tdoutap,
tdouser,
tdo,
tmsutap,
tckutap,
tdiutap,
shiftuser,
clkdruser,
updateuser,
runidleuser,
usr1user);
input tms;
input tck;
input tdi;
input ntrst;
input tdoutap;
input tdouser;
output tdo;
output tmsutap;
output tckutap;
output tdiutap;
output shiftuser;
output clkdruser;
output updateuser;
output runidleuser;
output usr1user;
parameter lpm_type = "cyclone_jtag";
endmodule
//--------------------------------------------------------------------
//
// Module Name : cyclone_crcblock
//
// Description : Cyclone CRCBLOCK Verilog Simulation model
//
//--------------------------------------------------------------------
`timescale 1 ps/1 ps
module cyclone_crcblock (
clk,
shiftnld,
ldsrc,
crcerror,
regout);
input clk;
input shiftnld;
input ldsrc;
output crcerror;
output regout;
assign crcerror = 1'b0;
assign regout = 1'b0;
parameter oscillator_divider = 1;
parameter lpm_type = "cyclone_crcblock";
endmodule
//------------------------------------------------------------------
//
// Module Name : cyclone_routing_wire
//
// Description : Simulation model for a simple routing wire
//
//------------------------------------------------------------------
`timescale 1ps / 1ps
module cyclone_routing_wire (
datain,
dataout
);
// INPUT PORTS
input datain;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES
wire dataout_tmp;
specify
(datain => dataout) = (0, 0) ;
endspecify
assign dataout_tmp = datain;
and (dataout, dataout_tmp, 1'b1);
endmodule // cyclone_routing_wire
///////////////////////////////////////////////////////////////////////
//
// Module Name : cyclone_asynch_io
//
// Description : Verilog simulation model for asynchronous submodule
// in Cyclone IO.
//
///////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module cyclone_asynch_io
(
datain,
oe,
regin,
padio,
combout,
regout
);
// INPUT/OUTPUT PORTS
inout padio;
// INPUT PORTS
input datain;
input oe;
input regin;
// OUTPUT PORTS
output combout;
output regout;
parameter operation_mode = "input";
parameter bus_hold = "false";
parameter open_drain_output = "false";
// INTERNAL VARIABLES
reg prev_value;
reg tmp_padio;
reg tmp_combout;
reg buf_control;
// INPUT BUFFERS
wire datain_in;
wire oe_in;
buf(datain_in, datain);
buf(oe_in, oe);
tri padio_tmp;
specify
(padio => combout) = (0,0);
(datain => padio) = (0, 0);
(posedge oe => (padio +: padio_tmp)) = (0, 0);
(negedge oe => (padio +: 1'bz)) = (0, 0);
(regin => regout) = (0, 0);
endspecify
initial
begin
prev_value = 'b0;
tmp_padio = 'bz;
end
always @(datain_in or oe_in or padio)
begin
if (bus_hold == "true" )
begin
buf_control = 'b1;
if ( operation_mode == "input")
begin
if (padio == 1'bz)
tmp_combout = prev_value;
else
begin
prev_value = padio;
tmp_combout = padio;
end
tmp_padio = 1'bz;
end
else
begin
if ( operation_mode == "output" || operation_mode == "bidir")
begin
if ( oe_in == 1)
begin
if ( open_drain_output == "true" )
begin
if (datain_in == 0)
begin
tmp_padio = 1'b0;
prev_value = 1'b0;
end
else if (datain_in == 1'bx)
begin
tmp_padio = 1'bx;
prev_value = 1'bx;
end
else // output of tri is 'Z'
begin
if ( operation_mode == "bidir")
prev_value = padio;
tmp_padio = 1'bz;
end
end
else // open drain_output = false;
begin
tmp_padio = datain_in;
prev_value = datain_in;
end
end
else if ( oe_in == 0 )
begin
if (operation_mode == "bidir")
prev_value = padio;
tmp_padio = 1'bz;
end
else // oe == 'X'
begin
tmp_padio = 1'bx;
prev_value = 1'bx;
end
end
if ( operation_mode == "output")
tmp_combout = 1'bz;
else
tmp_combout = padio;
end
end
else // bus hold is false
begin
buf_control = 'b0;
if ( operation_mode == "input")
begin
tmp_combout = padio;
end
else if (operation_mode == "output" || operation_mode == "bidir")
begin
if ( operation_mode == "bidir")
tmp_combout = padio;
if ( oe_in == 1 )
begin
if ( open_drain_output == "true" )
begin
if (datain_in == 0)
tmp_padio = 1'b0;
else if ( datain_in == 1'bx)
tmp_padio = 1'bx;
else
tmp_padio = 1'bz;
end
else
tmp_padio = datain_in;
end
else if ( oe_in == 0 )
tmp_padio = 1'bz;
else
tmp_padio = 1'bx;
end
else
begin
$display ("Error: Invalid operation_mode specified in cyclone io atom!\n");
$display ("Time: %0t Instance: %m", $time);
end
end
end
bufif1 (weak1, weak0) b(padio_tmp, prev_value, buf_control); //weak value
pmos (padio_tmp, tmp_padio, 'b0);
pmos (combout, tmp_combout, 'b0);
pmos (padio, padio_tmp, 'b0);
and (regout, regin, 1'b1);
endmodule
///////////////////////////////////////////////////////////////////////
//
// Module Name : cyclone_io
//
// Description : Verilog simulation model for Cyclone IO.
//
///////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module cyclone_io
(
datain,
oe,
outclk,
outclkena,
inclk,
inclkena,
areset,
sreset,
devclrn,
devpor,
devoe,
padio,
combout,
regout
);
parameter operation_mode = "input";
parameter open_drain_output = "false";
parameter bus_hold = "false";
parameter output_register_mode = "none";
parameter output_async_reset = "none";
parameter output_sync_reset = "none";
parameter output_power_up = "low";
parameter tie_off_output_clock_enable = "false";
parameter oe_register_mode = "none";
parameter oe_async_reset = "none";
parameter oe_sync_reset = "none";
parameter oe_power_up = "low";
parameter tie_off_oe_clock_enable = "false";
parameter input_register_mode = "none";
parameter input_async_reset = "none";
parameter input_sync_reset = "none";
parameter input_power_up = "low";
parameter lpm_type = "cyclone_io";
// INPUT/OUTPUT PORTS
inout padio;
// INPUT PORTS
input datain;
input oe;
input outclk;
input outclkena;
input inclk;
input inclkena;
input areset;
input sreset;
input devclrn;
input devpor;
input devoe;
// OUTPUT PORTS
output combout;
output regout;
tri1 devclrn;
tri1 devpor;
tri1 devoe;
// INTERNAL VARIABLES
wire out_reg_clk_ena;
wire oe_reg_clk_ena;
wire tmp_oe_reg_out;
wire tmp_input_reg_out;
wire tmp_output_reg_out;
wire inreg_sreset_is_used;
wire outreg_sreset_is_used;
wire oereg_sreset_is_used;
wire inreg_sreset;
wire outreg_sreset;
wire oereg_sreset;
wire in_reg_aclr;
wire in_reg_apreset;
wire oe_reg_aclr;
wire oe_reg_apreset;
wire oe_reg_sel;
wire out_reg_aclr;
wire out_reg_apreset;
wire out_reg_sel;
wire input_reg_pu_low;
wire output_reg_pu_low;
wire oe_reg_pu_low;
wire inreg_D;
wire outreg_D;
wire oereg_D;
wire tmp_datain;
wire tmp_oe;
wire iareset;
wire isreset;
assign input_reg_pu_low = ( input_power_up == "low") ? 'b0 : 'b1;
assign output_reg_pu_low = ( output_power_up == "low") ? 'b0 : 'b1;
assign oe_reg_pu_low = ( oe_power_up == "low") ? 'b0 : 'b1;
assign out_reg_sel = (output_register_mode == "register" ) ? 'b1 : 'b0;
assign oe_reg_sel = ( oe_register_mode == "register" ) ? 'b1 : 'b0;
assign iareset = ( areset === 'b0 || areset === 'b1 ) ? !areset : 'b1;
assign isreset = ( sreset === 'b0 || sreset === 'b1 ) ? sreset : 'b0;
// output register signals
assign out_reg_aclr = (output_async_reset == "clear") ? iareset : 'b1;
assign out_reg_apreset = ( output_async_reset == "preset") ? iareset : 'b1;
assign outreg_sreset_is_used = ( output_sync_reset == "none") ? 'b0 : 'b1;
assign outreg_sreset = (output_sync_reset == "clear") ? 'b0 : 'b1;
// oe register signals
assign oe_reg_aclr = ( oe_async_reset == "clear") ? iareset : 'b1;
assign oe_reg_apreset = ( oe_async_reset == "preset") ? iareset : 'b1;
assign oereg_sreset_is_used = ( oe_sync_reset == "none") ? 'b0 : 'b1;
assign oereg_sreset = (oe_sync_reset == "clear") ? 'b0 : 'b1;
// input register signals
assign in_reg_aclr = ( input_async_reset == "clear") ? iareset : 'b1;
assign in_reg_apreset = ( input_async_reset == "preset") ? iareset : 'b1;
assign inreg_sreset_is_used = ( input_sync_reset == "none") ? 'b0 : 'b1;
assign inreg_sreset = (input_sync_reset == "clear") ? 'b0 : 'b1;
// oe and output register clock enable signals
assign out_reg_clk_ena = ( tie_off_output_clock_enable == "true") ? 'b1 : outclkena;
assign oe_reg_clk_ena = ( tie_off_oe_clock_enable == "true") ? 'b1 : outclkena;
// input reg
cyclone_mux21 inreg_D_mux (
.MO (inreg_D),
.A (padio),
.B (inreg_sreset),
.S (isreset && inreg_sreset_is_used)
);
cyclone_dffe input_reg (
.Q (tmp_input_reg_out),
.CLK (inclk),
.ENA (inclkena),
.D (inreg_D),
.CLRN (in_reg_aclr && devclrn && (input_reg_pu_low || devpor)),
.PRN (in_reg_apreset && (!input_reg_pu_low || devpor))
);
//output reg
cyclone_mux21 outreg_D_mux (
.MO (outreg_D),
.A (datain),
.B (outreg_sreset),
.S (isreset && outreg_sreset_is_used)
);
cyclone_dffe output_reg (
.Q (tmp_output_reg_out),
.CLK (outclk),
.ENA (out_reg_clk_ena),
.D (outreg_D),
.CLRN (out_reg_aclr && devclrn && (output_reg_pu_low || devpor)),
.PRN (out_reg_apreset && (!output_reg_pu_low || devpor))
);
//oe reg
cyclone_mux21 oereg_D_mux (
.MO (oereg_D),
.A (oe),
.B (oereg_sreset),
.S (isreset && oereg_sreset_is_used)
);
cyclone_dffe oe_reg (
.Q (tmp_oe_reg_out),
.CLK (outclk),
.ENA (oe_reg_clk_ena),
.D (oereg_D),
.CLRN (oe_reg_aclr && devclrn && (oe_reg_pu_low || devpor)),
.PRN (oe_reg_apreset && (!oe_reg_pu_low || devpor))
);
// asynchronous block
assign tmp_oe = (oe_reg_sel == 'b1) ? tmp_oe_reg_out : oe;
assign tmp_datain = ((operation_mode == "output" ||
operation_mode == "bidir") &&
out_reg_sel == 'b1 ) ? tmp_output_reg_out : datain;
cyclone_asynch_io asynch_inst(
.datain(tmp_datain),
.oe(tmp_oe),
.regin(tmp_input_reg_out),
.padio(padio),
.combout(combout),
.regout(regout)
);
defparam asynch_inst.operation_mode = operation_mode;
defparam asynch_inst.bus_hold = bus_hold;
defparam asynch_inst.open_drain_output = open_drain_output;
endmodule
//---------------------------------------------------------------------
//
// Module Name : cyclone_asmiblock
//
// Description : Cyclone ASMIBLOCK Verilog Simulation model
//
//---------------------------------------------------------------------
`timescale 1 ps/1 ps
module cyclone_asmiblock
(
dclkin,
scein,
sdoin,
data0out,
oe
);
input dclkin;
input scein;
input sdoin;
input oe;
output data0out;
parameter lpm_type = "cyclone_asmiblock";
endmodule // cyclone_asmiblock
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND2B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__AND2B_FUNCTIONAL_PP_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__and2b (
X ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X , not0_out, B );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND2B_FUNCTIONAL_PP_V |
`include "riscv_functions.vh"
module riscv_ex_pipe (
input clk,
input rstn,
input id_ex_rdy,
input [`EX_FUNCT_W-1:0] id_ex_funct,
input [31:0] id_ex_op1,
input [31:0] id_ex_op2,
input [`MEM_FUNCT_W-1:0] id_ex_mem_funct,
input [31:0] id_ex_mem_data,
input [4:0] id_ex_wb_rsd,
input [31:0] data_bif_rdata,
input data_bif_ack,
output [31:0] data_bif_addr,
output data_bif_req,
output data_bif_rnw,
output [3:0] data_bif_wmask,
output [31:0] data_bif_wdata,
output [31:0] wb_rf_data,
output [4:0] wb_rf_rsd,
output wb_rf_write
);
//Wires for pipeline
wire id_ex_ack;
wire ex_mem_rdy;
wire ex_mem_ack;
wire [31:0] ex_mem_result;
wire [`MEM_FUNCT_W-1:0] ex_mem_funct;
wire [31:0] ex_mem_data;
wire [4:0] ex_mem_wb_rsd;
wire mem_wb_rdy;
wire mem_wb_ack;
wire [`LD_FUNCT_W-1:0] mem_wb_funct;
wire [1:0] mem_wb_baddr;
wire [31:0] mem_wb_data;
wire [4:0] mem_wb_rsd;
riscv_ex i_riscv_ex (
.clk (clk),
.rstn (rstn),
.id_ex_rdy (id_ex_rdy),
.id_ex_ack (id_ex_ack),
.id_ex_funct (id_ex_funct),
.id_ex_op1 (id_ex_op1),
.id_ex_op2 (id_ex_op2),
.id_ex_mem_funct (id_ex_mem_funct),
.id_ex_mem_data (id_ex_mem_data),
.id_ex_wb_rsd (id_ex_wb_rsd),
.ex_mem_rdy (ex_mem_rdy),
.ex_mem_ack (ex_mem_ack),
.ex_mem_result (ex_mem_result),
.ex_mem_funct (ex_mem_funct),
.ex_mem_data (ex_mem_data),
.ex_mem_wb_rsd (ex_mem_wb_rsd)
);
riscv_mem i_riscv_mem (
.clk (clk),
.rstn (rstn),
.ex_mem_rdy (ex_mem_rdy),
.ex_mem_ack (ex_mem_ack),
.ex_mem_result (ex_mem_result),
.ex_mem_funct (ex_mem_funct),
.ex_mem_data (ex_mem_data),
.ex_mem_wb_rsd (ex_mem_wb_rsd),
.mem_wb_rdy (mem_wb_rdy),
.mem_wb_ack (mem_wb_ack),
.data_bif_addr (data_bif_addr),
.data_bif_req (data_bif_req),
.data_bif_rnw (data_bif_rnw),
.data_bif_wmask (data_bif_wmask),
.data_bif_wdata (data_bif_wdata),
.mem_wb_funct (mem_wb_funct),
.mem_wb_baddr (mem_wb_baddr),
.mem_wb_data (mem_wb_data),
.mem_wb_rsd (mem_wb_rsd)
);
riscv_wb i_riscv_wb (
.clk (clk),
.rstn (rstn),
.mem_wb_rdy (mem_wb_rdy),
.mem_wb_ack (mem_wb_ack),
.data_bif_rdata (data_bif_rdata),
.data_bif_ack (data_bif_ack),
.mem_wb_funct (mem_wb_funct),
.mem_wb_data (mem_wb_data),
.mem_wb_rsd (mem_wb_rsd),
.wb_rf_data (wb_rf_data),
.wb_rf_rsd (wb_rf_rsd),
.wb_rf_write (wb_rf_write)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFRTP_BEHAVIORAL_V
`define SKY130_FD_SC_LS__DFRTP_BEHAVIORAL_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ls__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dfrtp (
Q ,
CLK ,
D ,
RESET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
reg notifier ;
wire D_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_ls__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFRTP_BEHAVIORAL_V |
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2010 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
Require Import Morphisms BinInt Zdiv_def ZDivEucl.
Local Open Scope Z_scope.
(** * Definitions of division for binary integers, Euclid convention. *)
(** In this convention, the remainder is always positive.
For other conventions, see file Zdiv_def.
To avoid collision with the other divisions, we place this one
under a module.
*)
Module ZEuclid.
Definition modulo a b := Zmod a (Zabs b).
Definition div a b := (Zsgn b) * (Zdiv a (Zabs b)).
Instance mod_wd : Proper (eq==>eq==>eq) modulo.
Proof. congruence. Qed.
Instance div_wd : Proper (eq==>eq==>eq) div.
Proof. congruence. Qed.
Theorem div_mod : forall a b, b<>0 ->
a = b*(div a b) + modulo a b.
Proof.
intros a b Hb. unfold div, modulo.
rewrite Zmult_assoc. rewrite Z.sgn_abs. apply Z.div_mod.
now destruct b.
Qed.
Lemma mod_always_pos : forall a b, b<>0 ->
0 <= modulo a b < Zabs b.
Proof.
intros a b Hb. unfold modulo.
apply Z.mod_pos_bound.
destruct b; compute; trivial. now destruct Hb.
Qed.
Lemma mod_bound_pos : forall a b, 0<=a -> 0<b -> 0 <= modulo a b < b.
Proof.
intros a b _ Hb. rewrite <- (Z.abs_eq b) at 3 by Z.order.
apply mod_always_pos. Z.order.
Qed.
Include ZEuclidProp Z Z Z.
End ZEuclid.
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 08:26:29 2016
/////////////////////////////////////////////////////////////
module CORDIC_Arch2v1_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_fsm_cordic,
ack_cordic, operation, data_in, shift_region_flag, ready_cordic,
data_output, beg_add_subt, ack_add_subt, add_subt_dataA,
add_subt_dataB, result_add_subt, op_add_subt, ready_add_subt );
input [31:0] data_in;
input [1:0] shift_region_flag;
output [31:0] data_output;
output [31:0] add_subt_dataA;
output [31:0] add_subt_dataB;
input [31:0] result_add_subt;
input clk, rst, beg_fsm_cordic, ack_cordic, operation, ready_add_subt;
output ready_cordic, beg_add_subt, ack_add_subt, op_add_subt;
wire d_ff1_operation_out, sel_mux_1_reg, d_ff3_sign_out, sel_mux_3_reg,
data_output2_31_, cordic_FSM_state_next_1_, n331, n336, n337, n338,
n339, n340, n341, n342, n343, n344, n345, n346, n347, n348, n349,
n350, n351, n352, n353, n354, n355, n356, n357, n358, n359, n360,
n361, n362, n363, n364, n365, n366, n367, n368, n369, n370, n371,
n372, n373, n374, n375, n376, n377, n378, n379, n380, n381, n382,
n383, n384, n385, n386, n387, n388, n389, n390, n391, n392, n393,
n394, n395, n396, n397, n398, n399, n400, n401, n402, n403, n404,
n405, n406, n407, n408, n409, n410, n411, n412, n413, n414, n415,
n416, n417, n418, n419, n420, n421, n422, n423, n424, n425, n426,
n427, n428, n429, n430, n431, n432, n433, n434, n435, n436, n437,
n438, n439, n440, n441, n442, n443, n444, n445, n446, n447, n448,
n449, n450, n451, n452, n453, n454, n455, n456, n457, n458, n459,
n460, n461, n462, n463, n464, n465, n466, n467, n468, n469, n470,
n471, n472, n473, n474, n475, n476, n477, n478, n479, n480, n481,
n482, n483, n484, n485, n486, n487, n488, n489, n490, n491, n492,
n493, n494, n495, n496, n497, n498, n499, n500, n501, n502, n503,
n504, n505, n506, n507, n508, n509, n510, n511, n512, n513, n514,
n515, n516, n517, n518, n519, n520, n521, n522, n523, n524, n525,
n526, n527, n528, n529, n530, n531, n532, n533, n534, n535, n536,
n537, n538, n539, n540, n541, n542, n543, n544, n545, n546, n547,
n548, n549, n550, n551, n552, n553, n554, n555, n556, n557, n558,
n559, n560, n561, n562, n563, n564, n565, n566, n567, n568, n569,
n570, n571, n572, n573, n574, n575, n576, n577, n578, n579, n580,
n581, n582, n583, n584, n585, n586, n587, n588, n589, n590, n591,
n592, n593, n594, n595, n596, n597, n598, n599, n600, n601, n602,
n603, n604, n605, n606, n607, n608, n609, n610, n611, n612, n613,
n614, n615, n616, n617, n618, n619, n620, n621, n622, n623, n624,
n625, n626, n627, n628, n629, n630, n631, n632, n633, n634, n635,
n636, n637, n638, n639, n640, n641, n642, n643, n644, n645, n646,
n647, n648, n649, n650, n651, n652, n653, n654, n655, n656, n657,
n658, n659, n660, n661, n662, n663, n664, n665, n666, n667, n668,
n669, n670, n671, n672, n673, n674, n675, n676, n677, n678, n679,
n680, n681, n682, n683, n684, n685, n686, n687, n688, n689, n690,
n691, n692, n693, n694, n695, n696, n697, n698, n699, n700, n701,
n702, n703, n704, n705, n706, n707, n708, n709, n710, n711, n712,
n713, n714, n715, n716, n717, n718, n719, n720, n721, n722, n723,
n724, n725, n726, n727, n728, n729, n730, n731, n732, n798, n799,
n800, n801, n802, n803, n804, n805, n806, n807, n808, n809, n810,
n811, n812, n813, n814, n815, n816, n817, n818, n819, n820, n821,
n822, n823, n824, n825, n826, n827, n828, n829, n830, n831, n832,
n833, n834, n835, n836, n837, n838, n839, n840, n841, n842, n843,
n844, n845, n846, n847, n848, n849, n850, n851, n852, n853, n854,
n855, n856, n857, n858, n859, n860, n861, n862, n863, n864, n865,
n866, n867, n868, n869, n870, n871, n872, n873, n874, n875, n876,
n877, n878, n879, n880, n881, n882, n883, n884, n885, n886, n887,
n888, n889, n890, n891, n892, n893, n894, n895, n896, n897, n898,
n899, n900, n901, n902, n903, n904, n905, n906, n907, n908, n909,
n910, n911, n912, n913, n914, n915, n916, n917, n918, n919, n920,
n921, n922, n923, n924, n925, n926, n927, n928, n929, n930, n931,
n932, n933, n934, n935, n936, n937, n938, n939, n940, n941, n942,
n943, n944, n945, n946, n947, n948, n949, n950, n951, n952, n953,
n954, n955, n956, n957, n958, n959, n960, n961, n962, n963, n964,
n965, n966, n967, n968, n969, n970, n971, n972, n973, n974, n975,
n976, n977, n978, n979, n980, n981, n982, n983, n984, n985, n986,
n987, n988, n989, n990, n991, n992, n993, n994, n995, n996, n997,
n998, n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006, n1007,
n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016, n1017,
n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026, n1027,
n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037,
n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047,
n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057,
n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066, n1067,
n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076, n1077,
n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086, n1087,
n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096, n1097,
n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106, n1107,
n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116, n1117,
n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126, n1127,
n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137,
n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147,
n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156, n1157,
n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167,
n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177,
n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187,
n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197,
n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207,
n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217,
n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227,
n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237,
n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247,
n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257,
n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267,
n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277,
n1278, n1279, n1280;
wire [1:0] d_ff1_shift_region_flag_out;
wire [1:0] cont_var_out;
wire [3:1] cont_iter_out;
wire [31:0] d_ff1_Z;
wire [31:0] d_ff_Xn;
wire [31:0] d_ff_Yn;
wire [31:0] d_ff_Zn;
wire [31:0] d_ff2_X;
wire [31:0] d_ff2_Y;
wire [31:0] d_ff2_Z;
wire [31:0] d_ff3_sh_x_out;
wire [31:0] d_ff3_sh_y_out;
wire [27:0] d_ff3_LUT_out;
wire [1:0] sel_mux_2_reg;
wire [30:0] sign_inv_out;
wire [3:0] cordic_FSM_state_reg;
DFFRXLTS cont_iter_count_reg_0_ ( .D(n728), .CK(clk), .RN(n1241), .QN(n809)
);
DFFRXLTS cont_iter_count_reg_2_ ( .D(n726), .CK(clk), .RN(n1265), .Q(
cont_iter_out[2]), .QN(n811) );
DFFRXLTS reg_Z0_Q_reg_1_ ( .D(n719), .CK(clk), .RN(n1261), .Q(d_ff1_Z[1]) );
DFFRXLTS reg_Z0_Q_reg_2_ ( .D(n718), .CK(clk), .RN(n1273), .Q(d_ff1_Z[2]) );
DFFRXLTS reg_Z0_Q_reg_3_ ( .D(n717), .CK(clk), .RN(n1259), .Q(d_ff1_Z[3]) );
DFFRXLTS reg_Z0_Q_reg_4_ ( .D(n716), .CK(clk), .RN(n1262), .Q(d_ff1_Z[4]) );
DFFRXLTS reg_Z0_Q_reg_5_ ( .D(n715), .CK(clk), .RN(n1272), .Q(d_ff1_Z[5]) );
DFFRXLTS reg_Z0_Q_reg_6_ ( .D(n714), .CK(clk), .RN(n1273), .Q(d_ff1_Z[6]) );
DFFRXLTS reg_Z0_Q_reg_7_ ( .D(n713), .CK(clk), .RN(n1259), .Q(d_ff1_Z[7]) );
DFFRXLTS reg_Z0_Q_reg_8_ ( .D(n712), .CK(clk), .RN(n1262), .Q(d_ff1_Z[8]) );
DFFRXLTS reg_Z0_Q_reg_9_ ( .D(n711), .CK(clk), .RN(n1272), .Q(d_ff1_Z[9]) );
DFFRXLTS reg_Z0_Q_reg_10_ ( .D(n710), .CK(clk), .RN(n1273), .Q(d_ff1_Z[10])
);
DFFRXLTS reg_Z0_Q_reg_11_ ( .D(n709), .CK(clk), .RN(n1259), .Q(d_ff1_Z[11])
);
DFFRXLTS reg_Z0_Q_reg_12_ ( .D(n708), .CK(clk), .RN(n1246), .Q(d_ff1_Z[12])
);
DFFRXLTS reg_Z0_Q_reg_13_ ( .D(n707), .CK(clk), .RN(n1247), .Q(d_ff1_Z[13])
);
DFFRXLTS reg_Z0_Q_reg_14_ ( .D(n706), .CK(clk), .RN(n1263), .Q(d_ff1_Z[14])
);
DFFRXLTS reg_Z0_Q_reg_15_ ( .D(n705), .CK(clk), .RN(n1242), .Q(d_ff1_Z[15])
);
DFFRXLTS reg_Z0_Q_reg_16_ ( .D(n704), .CK(clk), .RN(n1243), .Q(d_ff1_Z[16])
);
DFFRXLTS reg_Z0_Q_reg_17_ ( .D(n703), .CK(clk), .RN(n1242), .Q(d_ff1_Z[17])
);
DFFRXLTS reg_Z0_Q_reg_18_ ( .D(n702), .CK(clk), .RN(n1243), .Q(d_ff1_Z[18])
);
DFFRXLTS reg_Z0_Q_reg_19_ ( .D(n701), .CK(clk), .RN(n1246), .Q(d_ff1_Z[19])
);
DFFRXLTS reg_Z0_Q_reg_20_ ( .D(n700), .CK(clk), .RN(n1247), .Q(d_ff1_Z[20])
);
DFFRXLTS reg_Z0_Q_reg_21_ ( .D(n699), .CK(clk), .RN(n1263), .Q(d_ff1_Z[21])
);
DFFRXLTS reg_Z0_Q_reg_22_ ( .D(n698), .CK(clk), .RN(n1267), .Q(d_ff1_Z[22])
);
DFFRXLTS reg_Z0_Q_reg_23_ ( .D(n697), .CK(clk), .RN(n1270), .Q(d_ff1_Z[23])
);
DFFRXLTS reg_Z0_Q_reg_24_ ( .D(n696), .CK(clk), .RN(n1264), .Q(d_ff1_Z[24])
);
DFFRXLTS reg_Z0_Q_reg_25_ ( .D(n695), .CK(clk), .RN(n1266), .Q(d_ff1_Z[25])
);
DFFRXLTS reg_Z0_Q_reg_26_ ( .D(n694), .CK(clk), .RN(n1268), .Q(d_ff1_Z[26])
);
DFFRXLTS reg_Z0_Q_reg_27_ ( .D(n693), .CK(clk), .RN(n1269), .Q(d_ff1_Z[27])
);
DFFRXLTS reg_Z0_Q_reg_28_ ( .D(n692), .CK(clk), .RN(n1271), .Q(d_ff1_Z[28])
);
DFFRXLTS reg_Z0_Q_reg_29_ ( .D(n691), .CK(clk), .RN(n1267), .Q(d_ff1_Z[29])
);
DFFRXLTS reg_Z0_Q_reg_30_ ( .D(n690), .CK(clk), .RN(n1270), .Q(d_ff1_Z[30])
);
DFFRXLTS reg_Z0_Q_reg_31_ ( .D(n689), .CK(clk), .RN(n1264), .Q(d_ff1_Z[31])
);
DFFRXLTS d_ff4_Zn_Q_reg_0_ ( .D(n684), .CK(clk), .RN(n1264), .Q(d_ff_Zn[0])
);
DFFRXLTS d_ff4_Zn_Q_reg_1_ ( .D(n683), .CK(clk), .RN(n1260), .Q(d_ff_Zn[1])
);
DFFRXLTS d_ff4_Zn_Q_reg_2_ ( .D(n682), .CK(clk), .RN(n1260), .Q(d_ff_Zn[2])
);
DFFRXLTS d_ff4_Zn_Q_reg_3_ ( .D(n681), .CK(clk), .RN(n1245), .Q(d_ff_Zn[3])
);
DFFRXLTS d_ff4_Zn_Q_reg_4_ ( .D(n680), .CK(clk), .RN(n1261), .Q(d_ff_Zn[4])
);
DFFRXLTS d_ff4_Zn_Q_reg_5_ ( .D(n679), .CK(clk), .RN(n1261), .Q(d_ff_Zn[5])
);
DFFRXLTS d_ff4_Zn_Q_reg_6_ ( .D(n678), .CK(clk), .RN(n1261), .Q(d_ff_Zn[6])
);
DFFRXLTS d_ff4_Zn_Q_reg_7_ ( .D(n677), .CK(clk), .RN(n1268), .Q(d_ff_Zn[7])
);
DFFRXLTS d_ff4_Zn_Q_reg_8_ ( .D(n676), .CK(clk), .RN(n1269), .Q(d_ff_Zn[8])
);
DFFRXLTS d_ff4_Zn_Q_reg_9_ ( .D(n675), .CK(clk), .RN(n1271), .Q(d_ff_Zn[9])
);
DFFRXLTS d_ff4_Zn_Q_reg_10_ ( .D(n674), .CK(clk), .RN(n1267), .Q(d_ff_Zn[10]) );
DFFRXLTS d_ff4_Zn_Q_reg_11_ ( .D(n673), .CK(clk), .RN(n1270), .Q(d_ff_Zn[11]) );
DFFRXLTS d_ff4_Zn_Q_reg_12_ ( .D(n672), .CK(clk), .RN(n1264), .Q(d_ff_Zn[12]) );
DFFRXLTS d_ff4_Zn_Q_reg_13_ ( .D(n671), .CK(clk), .RN(n1266), .Q(d_ff_Zn[13]) );
DFFRXLTS d_ff4_Zn_Q_reg_14_ ( .D(n670), .CK(clk), .RN(n1268), .Q(d_ff_Zn[14]) );
DFFRXLTS d_ff4_Zn_Q_reg_15_ ( .D(n669), .CK(clk), .RN(n1269), .Q(d_ff_Zn[15]) );
DFFRXLTS d_ff4_Zn_Q_reg_16_ ( .D(n668), .CK(clk), .RN(n1271), .Q(d_ff_Zn[16]) );
DFFRXLTS d_ff4_Zn_Q_reg_17_ ( .D(n667), .CK(clk), .RN(n1271), .Q(d_ff_Zn[17]) );
DFFRXLTS d_ff4_Zn_Q_reg_18_ ( .D(n666), .CK(clk), .RN(n1267), .Q(d_ff_Zn[18]) );
DFFRXLTS d_ff4_Zn_Q_reg_19_ ( .D(n665), .CK(clk), .RN(n1270), .Q(d_ff_Zn[19]) );
DFFRXLTS d_ff4_Zn_Q_reg_20_ ( .D(n664), .CK(clk), .RN(n1264), .Q(d_ff_Zn[20]) );
DFFRXLTS d_ff4_Zn_Q_reg_21_ ( .D(n663), .CK(clk), .RN(n1266), .Q(d_ff_Zn[21]) );
DFFRXLTS d_ff4_Zn_Q_reg_22_ ( .D(n662), .CK(clk), .RN(n1268), .Q(d_ff_Zn[22]) );
DFFRXLTS d_ff4_Zn_Q_reg_23_ ( .D(n661), .CK(clk), .RN(n1269), .Q(d_ff_Zn[23]) );
DFFRXLTS d_ff4_Zn_Q_reg_24_ ( .D(n660), .CK(clk), .RN(n1271), .Q(d_ff_Zn[24]) );
DFFRXLTS d_ff4_Zn_Q_reg_25_ ( .D(n659), .CK(clk), .RN(n1267), .Q(d_ff_Zn[25]) );
DFFRXLTS d_ff4_Zn_Q_reg_26_ ( .D(n658), .CK(clk), .RN(n1270), .Q(d_ff_Zn[26]) );
DFFRXLTS d_ff4_Zn_Q_reg_27_ ( .D(n657), .CK(clk), .RN(n1270), .Q(d_ff_Zn[27]) );
DFFRXLTS d_ff4_Zn_Q_reg_28_ ( .D(n656), .CK(clk), .RN(n1264), .Q(d_ff_Zn[28]) );
DFFRXLTS d_ff4_Zn_Q_reg_29_ ( .D(n655), .CK(clk), .RN(n1266), .Q(d_ff_Zn[29]) );
DFFRXLTS d_ff4_Zn_Q_reg_30_ ( .D(n654), .CK(clk), .RN(n1268), .Q(d_ff_Zn[30]) );
DFFRXLTS d_ff4_Zn_Q_reg_31_ ( .D(n653), .CK(clk), .RN(n1269), .Q(d_ff_Zn[31]) );
DFFRXLTS d_ff4_Yn_Q_reg_0_ ( .D(n652), .CK(clk), .RN(n1271), .Q(d_ff_Yn[0]),
.QN(n1215) );
DFFRXLTS d_ff4_Yn_Q_reg_2_ ( .D(n650), .CK(clk), .RN(n1270), .Q(d_ff_Yn[2]),
.QN(n1217) );
DFFRXLTS d_ff4_Yn_Q_reg_3_ ( .D(n649), .CK(clk), .RN(n1264), .Q(d_ff_Yn[3]),
.QN(n1218) );
DFFRXLTS d_ff4_Yn_Q_reg_4_ ( .D(n648), .CK(clk), .RN(n1266), .Q(d_ff_Yn[4]),
.QN(n1219) );
DFFRXLTS d_ff4_Yn_Q_reg_5_ ( .D(n647), .CK(clk), .RN(n1269), .Q(d_ff_Yn[5]),
.QN(n1220) );
DFFRXLTS d_ff4_Yn_Q_reg_6_ ( .D(n646), .CK(clk), .RN(n1271), .Q(d_ff_Yn[6]),
.QN(n1221) );
DFFRXLTS d_ff4_Yn_Q_reg_8_ ( .D(n644), .CK(clk), .RN(n1270), .Q(d_ff_Yn[8]),
.QN(n1223) );
DFFRXLTS d_ff4_Yn_Q_reg_9_ ( .D(n643), .CK(clk), .RN(n1264), .Q(d_ff_Yn[9]),
.QN(n1224) );
DFFRXLTS d_ff4_Yn_Q_reg_10_ ( .D(n642), .CK(clk), .RN(n1266), .Q(d_ff_Yn[10]), .QN(n1225) );
DFFRXLTS d_ff4_Yn_Q_reg_11_ ( .D(n641), .CK(clk), .RN(n1268), .Q(d_ff_Yn[11]), .QN(n1226) );
DFFRXLTS d_ff4_Yn_Q_reg_12_ ( .D(n640), .CK(clk), .RN(n1269), .Q(d_ff_Yn[12]), .QN(n1227) );
DFFRXLTS d_ff4_Yn_Q_reg_13_ ( .D(n639), .CK(clk), .RN(n1271), .Q(d_ff_Yn[13]), .QN(n1228) );
DFFRXLTS d_ff4_Yn_Q_reg_15_ ( .D(n637), .CK(clk), .RN(n1266), .Q(d_ff_Yn[15]), .QN(n1230) );
DFFRXLTS d_ff4_Yn_Q_reg_16_ ( .D(n636), .CK(clk), .RN(n1268), .Q(d_ff_Yn[16]), .QN(n1231) );
DFFRXLTS d_ff4_Yn_Q_reg_17_ ( .D(n635), .CK(clk), .RN(n1269), .Q(d_ff_Yn[17]), .QN(n1232) );
DFFRXLTS d_ff4_Yn_Q_reg_18_ ( .D(n634), .CK(clk), .RN(n1271), .Q(d_ff_Yn[18]), .QN(n1233) );
DFFRXLTS d_ff4_Yn_Q_reg_19_ ( .D(n633), .CK(clk), .RN(n1267), .Q(d_ff_Yn[19]), .QN(n1234) );
DFFRXLTS d_ff4_Yn_Q_reg_20_ ( .D(n632), .CK(clk), .RN(n1270), .Q(d_ff_Yn[20]), .QN(n1235) );
DFFRXLTS d_ff4_Yn_Q_reg_21_ ( .D(n631), .CK(clk), .RN(n1278), .Q(d_ff_Yn[21]), .QN(n1236) );
DFFRXLTS d_ff4_Yn_Q_reg_22_ ( .D(n630), .CK(clk), .RN(n1276), .Q(d_ff_Yn[22]), .QN(n1237) );
DFFRXLTS d_ff4_Yn_Q_reg_23_ ( .D(n629), .CK(clk), .RN(n1278), .Q(d_ff_Yn[23]) );
DFFRXLTS d_ff4_Yn_Q_reg_24_ ( .D(n628), .CK(clk), .RN(n1279), .Q(d_ff_Yn[24]) );
DFFRXLTS d_ff4_Yn_Q_reg_25_ ( .D(n627), .CK(clk), .RN(n1277), .Q(d_ff_Yn[25]), .QN(n1238) );
DFFRXLTS d_ff4_Yn_Q_reg_27_ ( .D(n625), .CK(clk), .RN(n1276), .Q(d_ff_Yn[27]) );
DFFRXLTS d_ff4_Yn_Q_reg_28_ ( .D(n624), .CK(clk), .RN(n1279), .Q(d_ff_Yn[28]) );
DFFRXLTS d_ff4_Yn_Q_reg_29_ ( .D(n623), .CK(clk), .RN(n1277), .Q(d_ff_Yn[29]) );
DFFRXLTS d_ff4_Yn_Q_reg_30_ ( .D(n622), .CK(clk), .RN(n1275), .Q(d_ff_Yn[30]) );
DFFRXLTS d_ff4_Yn_Q_reg_31_ ( .D(n621), .CK(clk), .RN(n1277), .Q(d_ff_Yn[31]), .QN(n1240) );
DFFRXLTS d_ff5_Q_reg_0_ ( .D(n588), .CK(clk), .RN(n1279), .Q(sign_inv_out[0]) );
DFFRXLTS d_ff5_Q_reg_1_ ( .D(n586), .CK(clk), .RN(n1278), .Q(sign_inv_out[1]) );
DFFRXLTS d_ff5_Q_reg_2_ ( .D(n584), .CK(clk), .RN(n1278), .Q(sign_inv_out[2]) );
DFFRXLTS d_ff5_Q_reg_3_ ( .D(n582), .CK(clk), .RN(n1276), .Q(sign_inv_out[3]) );
DFFRXLTS d_ff5_Q_reg_4_ ( .D(n580), .CK(clk), .RN(n1277), .Q(sign_inv_out[4]) );
DFFRXLTS d_ff5_Q_reg_5_ ( .D(n578), .CK(clk), .RN(n1280), .Q(sign_inv_out[5]) );
DFFRXLTS d_ff5_Q_reg_6_ ( .D(n576), .CK(clk), .RN(n1275), .Q(sign_inv_out[6]) );
DFFRXLTS d_ff5_Q_reg_7_ ( .D(n574), .CK(clk), .RN(n1277), .Q(sign_inv_out[7]) );
DFFRXLTS d_ff5_Q_reg_8_ ( .D(n572), .CK(clk), .RN(n1275), .Q(sign_inv_out[8]) );
DFFRXLTS d_ff5_Q_reg_9_ ( .D(n570), .CK(clk), .RN(n1276), .Q(sign_inv_out[9]) );
DFFRXLTS d_ff5_Q_reg_10_ ( .D(n568), .CK(clk), .RN(n1277), .Q(
sign_inv_out[10]) );
DFFRXLTS d_ff5_Q_reg_11_ ( .D(n566), .CK(clk), .RN(n1279), .Q(
sign_inv_out[11]) );
DFFRXLTS d_ff5_Q_reg_12_ ( .D(n564), .CK(clk), .RN(n1278), .Q(
sign_inv_out[12]) );
DFFRXLTS d_ff5_Q_reg_13_ ( .D(n562), .CK(clk), .RN(n1277), .Q(
sign_inv_out[13]) );
DFFRXLTS d_ff5_Q_reg_14_ ( .D(n560), .CK(clk), .RN(n1274), .Q(
sign_inv_out[14]) );
DFFRXLTS d_ff5_Q_reg_15_ ( .D(n558), .CK(clk), .RN(n1249), .Q(
sign_inv_out[15]) );
DFFRXLTS d_ff5_Q_reg_16_ ( .D(n556), .CK(clk), .RN(n1250), .Q(
sign_inv_out[16]) );
DFFRXLTS d_ff5_Q_reg_17_ ( .D(n554), .CK(clk), .RN(n1273), .Q(
sign_inv_out[17]) );
DFFRXLTS d_ff5_Q_reg_18_ ( .D(n552), .CK(clk), .RN(n1262), .Q(
sign_inv_out[18]) );
DFFRXLTS d_ff5_Q_reg_19_ ( .D(n550), .CK(clk), .RN(n1273), .Q(
sign_inv_out[19]) );
DFFRXLTS d_ff5_Q_reg_20_ ( .D(n548), .CK(clk), .RN(n1262), .Q(
sign_inv_out[20]) );
DFFRXLTS d_ff5_Q_reg_21_ ( .D(n546), .CK(clk), .RN(n1273), .Q(
sign_inv_out[21]) );
DFFRXLTS d_ff5_Q_reg_22_ ( .D(n544), .CK(clk), .RN(n1262), .Q(
sign_inv_out[22]) );
DFFRXLTS d_ff5_Q_reg_23_ ( .D(n542), .CK(clk), .RN(n1262), .Q(
sign_inv_out[23]) );
DFFRXLTS d_ff5_Q_reg_24_ ( .D(n540), .CK(clk), .RN(n1267), .Q(
sign_inv_out[24]) );
DFFRXLTS d_ff5_Q_reg_25_ ( .D(n538), .CK(clk), .RN(n1268), .Q(
sign_inv_out[25]) );
DFFRXLTS d_ff5_Q_reg_26_ ( .D(n536), .CK(clk), .RN(n1264), .Q(
sign_inv_out[26]) );
DFFRXLTS d_ff5_Q_reg_27_ ( .D(n534), .CK(clk), .RN(n1268), .Q(
sign_inv_out[27]) );
DFFRXLTS d_ff5_Q_reg_28_ ( .D(n532), .CK(clk), .RN(n1276), .Q(
sign_inv_out[28]) );
DFFRXLTS d_ff5_Q_reg_29_ ( .D(n530), .CK(clk), .RN(n1260), .Q(
sign_inv_out[29]) );
DFFRXLTS d_ff5_Q_reg_30_ ( .D(n528), .CK(clk), .RN(n1265), .Q(
sign_inv_out[30]) );
DFFRXLTS reg_LUT_Q_reg_0_ ( .D(n524), .CK(clk), .RN(n1246), .Q(
d_ff3_LUT_out[0]) );
DFFRXLTS reg_LUT_Q_reg_2_ ( .D(n522), .CK(clk), .RN(n1263), .Q(
d_ff3_LUT_out[2]) );
DFFRXLTS reg_LUT_Q_reg_3_ ( .D(n521), .CK(clk), .RN(n1242), .Q(
d_ff3_LUT_out[3]) );
DFFRXLTS reg_LUT_Q_reg_4_ ( .D(n520), .CK(clk), .RN(n1243), .Q(
d_ff3_LUT_out[4]) );
DFFRXLTS reg_LUT_Q_reg_5_ ( .D(n519), .CK(clk), .RN(n1246), .Q(
d_ff3_LUT_out[5]) );
DFFRXLTS reg_LUT_Q_reg_7_ ( .D(n517), .CK(clk), .RN(n1263), .Q(
d_ff3_LUT_out[7]) );
DFFRXLTS reg_LUT_Q_reg_8_ ( .D(n516), .CK(clk), .RN(n1242), .Q(
d_ff3_LUT_out[8]) );
DFFRXLTS reg_LUT_Q_reg_9_ ( .D(n515), .CK(clk), .RN(n1243), .Q(
d_ff3_LUT_out[9]) );
DFFRXLTS reg_LUT_Q_reg_10_ ( .D(n514), .CK(clk), .RN(n1246), .Q(
d_ff3_LUT_out[10]) );
DFFRXLTS reg_LUT_Q_reg_12_ ( .D(n512), .CK(clk), .RN(n1263), .QN(n808) );
DFFRXLTS reg_LUT_Q_reg_13_ ( .D(n511), .CK(clk), .RN(n1242), .Q(
d_ff3_LUT_out[13]) );
DFFRXLTS reg_LUT_Q_reg_14_ ( .D(n510), .CK(clk), .RN(n1243), .Q(
d_ff3_LUT_out[14]) );
DFFRXLTS reg_LUT_Q_reg_15_ ( .D(n509), .CK(clk), .RN(n1246), .Q(
d_ff3_LUT_out[15]) );
DFFRXLTS reg_LUT_Q_reg_17_ ( .D(n507), .CK(clk), .RN(n1263), .Q(
d_ff3_LUT_out[17]) );
DFFRXLTS reg_LUT_Q_reg_18_ ( .D(n506), .CK(clk), .RN(n1242), .Q(
d_ff3_LUT_out[18]) );
DFFRXLTS reg_LUT_Q_reg_19_ ( .D(n505), .CK(clk), .RN(n1243), .Q(
d_ff3_LUT_out[19]) );
DFFRXLTS reg_LUT_Q_reg_20_ ( .D(n504), .CK(clk), .RN(n1244), .Q(
d_ff3_LUT_out[20]) );
DFFRXLTS reg_LUT_Q_reg_21_ ( .D(n503), .CK(clk), .RN(n1244), .Q(
d_ff3_LUT_out[21]) );
DFFRXLTS reg_LUT_Q_reg_22_ ( .D(n502), .CK(clk), .RN(n1244), .Q(
d_ff3_LUT_out[22]) );
DFFRXLTS reg_LUT_Q_reg_23_ ( .D(n501), .CK(clk), .RN(n1244), .Q(
d_ff3_LUT_out[23]) );
DFFRXLTS reg_LUT_Q_reg_24_ ( .D(n500), .CK(clk), .RN(n1244), .Q(
d_ff3_LUT_out[24]) );
DFFRXLTS reg_LUT_Q_reg_25_ ( .D(n499), .CK(clk), .RN(n1244), .Q(
d_ff3_LUT_out[25]) );
DFFRXLTS reg_LUT_Q_reg_26_ ( .D(n498), .CK(clk), .RN(n1244), .Q(
d_ff3_LUT_out[26]) );
DFFRXLTS reg_shift_y_Q_reg_23_ ( .D(n409), .CK(clk), .RN(n1244), .Q(
d_ff3_sh_y_out[23]) );
DFFRXLTS reg_shift_y_Q_reg_24_ ( .D(n408), .CK(clk), .RN(n1244), .Q(
d_ff3_sh_y_out[24]) );
DFFRXLTS reg_shift_y_Q_reg_25_ ( .D(n407), .CK(clk), .RN(n1245), .Q(
d_ff3_sh_y_out[25]) );
DFFRXLTS reg_shift_y_Q_reg_26_ ( .D(n406), .CK(clk), .RN(n1241), .Q(
d_ff3_sh_y_out[26]) );
DFFRXLTS reg_shift_y_Q_reg_27_ ( .D(n405), .CK(clk), .RN(n1245), .Q(
d_ff3_sh_y_out[27]) );
DFFRXLTS reg_shift_y_Q_reg_28_ ( .D(n404), .CK(clk), .RN(n1241), .Q(
d_ff3_sh_y_out[28]) );
DFFRXLTS reg_shift_y_Q_reg_29_ ( .D(n403), .CK(clk), .RN(n1260), .Q(
d_ff3_sh_y_out[29]) );
DFFRXLTS reg_shift_y_Q_reg_30_ ( .D(n402), .CK(clk), .RN(n1260), .Q(
d_ff3_sh_y_out[30]) );
DFFRXLTS reg_shift_x_Q_reg_23_ ( .D(n345), .CK(clk), .RN(n1261), .Q(
d_ff3_sh_x_out[23]) );
DFFRXLTS reg_shift_x_Q_reg_24_ ( .D(n344), .CK(clk), .RN(n1241), .Q(
d_ff3_sh_x_out[24]) );
DFFRXLTS reg_shift_x_Q_reg_25_ ( .D(n343), .CK(clk), .RN(n1245), .Q(
d_ff3_sh_x_out[25]) );
DFFRXLTS reg_shift_x_Q_reg_26_ ( .D(n342), .CK(clk), .RN(n1245), .Q(
d_ff3_sh_x_out[26]) );
DFFRXLTS reg_shift_x_Q_reg_27_ ( .D(n341), .CK(clk), .RN(n1246), .Q(
d_ff3_sh_x_out[27]) );
DFFRXLTS reg_shift_x_Q_reg_28_ ( .D(n340), .CK(clk), .RN(n1247), .QN(n807)
);
DFFRXLTS reg_shift_x_Q_reg_29_ ( .D(n339), .CK(clk), .RN(n1263), .QN(n802)
);
DFFRXLTS reg_shift_x_Q_reg_30_ ( .D(n338), .CK(clk), .RN(n1242), .Q(
d_ff3_sh_x_out[30]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_0_ ( .D(n496), .CK(clk), .RN(n1243), .Q(
d_ff2_Z[0]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_1_ ( .D(n495), .CK(clk), .RN(n1246), .Q(
d_ff2_Z[1]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_3_ ( .D(n493), .CK(clk), .RN(n1263), .Q(
d_ff2_Z[3]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_4_ ( .D(n492), .CK(clk), .RN(n1242), .Q(
d_ff2_Z[4]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_5_ ( .D(n491), .CK(clk), .RN(n1243), .Q(
d_ff2_Z[5]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_6_ ( .D(n490), .CK(clk), .RN(n1246), .Q(
d_ff2_Z[6]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_7_ ( .D(n489), .CK(clk), .RN(n1247), .Q(
d_ff2_Z[7]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_8_ ( .D(n488), .CK(clk), .RN(n1263), .Q(
d_ff2_Z[8]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_9_ ( .D(n487), .CK(clk), .RN(n1242), .Q(
d_ff2_Z[9]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_10_ ( .D(n486), .CK(clk), .RN(n1243), .Q(
d_ff2_Z[10]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_11_ ( .D(n485), .CK(clk), .RN(n1246), .Q(
d_ff2_Z[11]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_12_ ( .D(n484), .CK(clk), .RN(n1247), .Q(
d_ff2_Z[12]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_13_ ( .D(n483), .CK(clk), .RN(n1263), .Q(
d_ff2_Z[13]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_14_ ( .D(n482), .CK(clk), .RN(n1242), .Q(
d_ff2_Z[14]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_15_ ( .D(n481), .CK(clk), .RN(n1243), .Q(
d_ff2_Z[15]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_16_ ( .D(n480), .CK(clk), .RN(n1254), .Q(
d_ff2_Z[16]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_17_ ( .D(n479), .CK(clk), .RN(n1251), .Q(
d_ff2_Z[17]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_18_ ( .D(n478), .CK(clk), .RN(n1254), .Q(
d_ff2_Z[18]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_19_ ( .D(n477), .CK(clk), .RN(n1251), .Q(
d_ff2_Z[19]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_20_ ( .D(n476), .CK(clk), .RN(n806), .Q(
d_ff2_Z[20]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_26_ ( .D(n470), .CK(clk), .RN(n1274), .Q(
d_ff2_Z[26]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_27_ ( .D(n469), .CK(clk), .RN(n1249), .Q(
d_ff2_Z[27]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_30_ ( .D(n466), .CK(clk), .RN(n1249), .Q(
d_ff2_Z[30]) );
DFFRX1TS reg_sign_Q_reg_0_ ( .D(n464), .CK(clk), .RN(n1274), .Q(
d_ff3_sign_out) );
DFFRXLTS reg_shift_y_Q_reg_0_ ( .D(n462), .CK(clk), .RN(n1250), .Q(
d_ff3_sh_y_out[0]) );
DFFRXLTS reg_shift_y_Q_reg_1_ ( .D(n460), .CK(clk), .RN(n1274), .Q(
d_ff3_sh_y_out[1]) );
DFFRXLTS reg_shift_y_Q_reg_2_ ( .D(n458), .CK(clk), .RN(n1249), .Q(
d_ff3_sh_y_out[2]) );
DFFRXLTS reg_shift_y_Q_reg_3_ ( .D(n456), .CK(clk), .RN(n1250), .Q(
d_ff3_sh_y_out[3]) );
DFFRXLTS reg_shift_y_Q_reg_4_ ( .D(n454), .CK(clk), .RN(n1274), .Q(
d_ff3_sh_y_out[4]) );
DFFRXLTS reg_shift_y_Q_reg_5_ ( .D(n452), .CK(clk), .RN(n1249), .Q(
d_ff3_sh_y_out[5]) );
DFFRXLTS reg_shift_y_Q_reg_6_ ( .D(n450), .CK(clk), .RN(n1255), .Q(
d_ff3_sh_y_out[6]) );
DFFRXLTS reg_shift_y_Q_reg_7_ ( .D(n448), .CK(clk), .RN(n1256), .Q(
d_ff3_sh_y_out[7]) );
DFFRXLTS reg_shift_y_Q_reg_8_ ( .D(n446), .CK(clk), .RN(n1253), .Q(
d_ff3_sh_y_out[8]) );
DFFRXLTS reg_shift_y_Q_reg_9_ ( .D(n444), .CK(clk), .RN(n1252), .Q(
d_ff3_sh_y_out[9]) );
DFFRXLTS reg_shift_y_Q_reg_10_ ( .D(n442), .CK(clk), .RN(n1254), .Q(
d_ff3_sh_y_out[10]) );
DFFRXLTS reg_shift_y_Q_reg_11_ ( .D(n440), .CK(clk), .RN(n1251), .Q(
d_ff3_sh_y_out[11]) );
DFFRXLTS reg_shift_y_Q_reg_12_ ( .D(n438), .CK(clk), .RN(n806), .Q(
d_ff3_sh_y_out[12]) );
DFFRXLTS reg_shift_y_Q_reg_13_ ( .D(n436), .CK(clk), .RN(n1248), .Q(
d_ff3_sh_y_out[13]) );
DFFRXLTS reg_shift_y_Q_reg_14_ ( .D(n434), .CK(clk), .RN(n1253), .Q(
d_ff3_sh_y_out[14]) );
DFFRXLTS reg_shift_y_Q_reg_15_ ( .D(n432), .CK(clk), .RN(n1252), .Q(
d_ff3_sh_y_out[15]) );
DFFRXLTS reg_shift_y_Q_reg_16_ ( .D(n430), .CK(clk), .RN(n1255), .Q(
d_ff3_sh_y_out[16]) );
DFFRXLTS reg_shift_y_Q_reg_17_ ( .D(n428), .CK(clk), .RN(n1256), .Q(
d_ff3_sh_y_out[17]) );
DFFRXLTS reg_shift_y_Q_reg_18_ ( .D(n426), .CK(clk), .RN(n1253), .Q(
d_ff3_sh_y_out[18]) );
DFFRXLTS reg_shift_y_Q_reg_19_ ( .D(n424), .CK(clk), .RN(n1252), .Q(
d_ff3_sh_y_out[19]) );
DFFRXLTS reg_shift_y_Q_reg_20_ ( .D(n422), .CK(clk), .RN(n1251), .Q(
d_ff3_sh_y_out[20]) );
DFFRXLTS reg_shift_y_Q_reg_21_ ( .D(n420), .CK(clk), .RN(n1253), .Q(
d_ff3_sh_y_out[21]) );
DFFRXLTS reg_shift_y_Q_reg_22_ ( .D(n418), .CK(clk), .RN(n1252), .Q(
d_ff3_sh_y_out[22]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_28_ ( .D(n412), .CK(clk), .RN(n1254), .Q(
d_ff2_Y[28]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_30_ ( .D(n410), .CK(clk), .RN(n1256), .Q(
d_ff2_Y[30]), .QN(n1211) );
DFFRXLTS reg_shift_y_Q_reg_31_ ( .D(n400), .CK(clk), .RN(n1253), .Q(
d_ff3_sh_y_out[31]) );
DFFRXLTS reg_shift_x_Q_reg_0_ ( .D(n398), .CK(clk), .RN(n1252), .Q(
d_ff3_sh_x_out[0]) );
DFFRXLTS reg_shift_x_Q_reg_1_ ( .D(n396), .CK(clk), .RN(n1254), .Q(
d_ff3_sh_x_out[1]) );
DFFRXLTS reg_shift_x_Q_reg_2_ ( .D(n394), .CK(clk), .RN(n1255), .Q(
d_ff3_sh_x_out[2]) );
DFFRXLTS reg_shift_x_Q_reg_3_ ( .D(n392), .CK(clk), .RN(n1251), .Q(
d_ff3_sh_x_out[3]) );
DFFRXLTS reg_shift_x_Q_reg_4_ ( .D(n390), .CK(clk), .RN(n806), .Q(
d_ff3_sh_x_out[4]) );
DFFRXLTS reg_shift_x_Q_reg_5_ ( .D(n388), .CK(clk), .RN(n1248), .Q(
d_ff3_sh_x_out[5]) );
DFFRXLTS reg_shift_x_Q_reg_6_ ( .D(n386), .CK(clk), .RN(n1255), .Q(
d_ff3_sh_x_out[6]) );
DFFRXLTS reg_shift_x_Q_reg_7_ ( .D(n384), .CK(clk), .RN(n1256), .Q(
d_ff3_sh_x_out[7]) );
DFFRXLTS reg_shift_x_Q_reg_8_ ( .D(n382), .CK(clk), .RN(n1257), .Q(
d_ff3_sh_x_out[8]) );
DFFRXLTS reg_shift_x_Q_reg_9_ ( .D(n380), .CK(clk), .RN(n1257), .Q(
d_ff3_sh_x_out[9]) );
DFFRXLTS reg_shift_x_Q_reg_10_ ( .D(n378), .CK(clk), .RN(n1257), .Q(
d_ff3_sh_x_out[10]) );
DFFRXLTS reg_shift_x_Q_reg_11_ ( .D(n376), .CK(clk), .RN(n1257), .Q(
d_ff3_sh_x_out[11]) );
DFFRXLTS reg_shift_x_Q_reg_12_ ( .D(n374), .CK(clk), .RN(n1257), .Q(
d_ff3_sh_x_out[12]) );
DFFRXLTS reg_shift_x_Q_reg_13_ ( .D(n372), .CK(clk), .RN(n1258), .Q(
d_ff3_sh_x_out[13]) );
DFFRXLTS reg_shift_x_Q_reg_14_ ( .D(n370), .CK(clk), .RN(n1258), .Q(
d_ff3_sh_x_out[14]) );
DFFRXLTS reg_shift_x_Q_reg_15_ ( .D(n368), .CK(clk), .RN(n1258), .Q(
d_ff3_sh_x_out[15]) );
DFFRXLTS reg_shift_x_Q_reg_16_ ( .D(n366), .CK(clk), .RN(n1258), .Q(
d_ff3_sh_x_out[16]) );
DFFRXLTS reg_shift_x_Q_reg_17_ ( .D(n364), .CK(clk), .RN(n1258), .Q(
d_ff3_sh_x_out[17]) );
DFFRXLTS reg_shift_x_Q_reg_18_ ( .D(n362), .CK(clk), .RN(n1272), .Q(
d_ff3_sh_x_out[18]) );
DFFRXLTS reg_shift_x_Q_reg_19_ ( .D(n360), .CK(clk), .RN(n1273), .Q(
d_ff3_sh_x_out[19]) );
DFFRXLTS reg_shift_x_Q_reg_20_ ( .D(n358), .CK(clk), .RN(n1259), .Q(
d_ff3_sh_x_out[20]) );
DFFRXLTS reg_shift_x_Q_reg_21_ ( .D(n356), .CK(clk), .RN(n1262), .Q(
d_ff3_sh_x_out[21]) );
DFFRXLTS reg_shift_x_Q_reg_22_ ( .D(n354), .CK(clk), .RN(n1272), .Q(
d_ff3_sh_x_out[22]) );
DFFRXLTS reg_shift_x_Q_reg_31_ ( .D(n336), .CK(clk), .RN(n1260), .Q(
d_ff3_sh_x_out[31]) );
DFFRX2TS cordic_FSM_state_reg_reg_0_ ( .D(n730), .CK(clk), .RN(n331), .Q(
cordic_FSM_state_reg[0]), .QN(n1213) );
DFFRX1TS cont_var_count_reg_0_ ( .D(n724), .CK(clk), .RN(n1245), .Q(
cont_var_out[0]), .QN(n1208) );
DFFRX1TS reg_ch_mux_2_Q_reg_0_ ( .D(n686), .CK(clk), .RN(n1260), .Q(
sel_mux_2_reg[0]), .QN(n1205) );
DFFRXLTS d_ff5_data_out_Q_reg_0_ ( .D(n587), .CK(clk), .RN(n1275), .Q(
data_output[0]) );
DFFRXLTS d_ff5_data_out_Q_reg_1_ ( .D(n585), .CK(clk), .RN(n1276), .Q(
data_output[1]) );
DFFRXLTS d_ff5_data_out_Q_reg_2_ ( .D(n583), .CK(clk), .RN(n1275), .Q(
data_output[2]) );
DFFRXLTS d_ff5_data_out_Q_reg_3_ ( .D(n581), .CK(clk), .RN(n1280), .Q(
data_output[3]) );
DFFRXLTS d_ff5_data_out_Q_reg_4_ ( .D(n579), .CK(clk), .RN(n1280), .Q(
data_output[4]) );
DFFRXLTS d_ff5_data_out_Q_reg_5_ ( .D(n577), .CK(clk), .RN(n1280), .Q(
data_output[5]) );
DFFRXLTS d_ff5_data_out_Q_reg_6_ ( .D(n575), .CK(clk), .RN(n1280), .Q(
data_output[6]) );
DFFRXLTS d_ff5_data_out_Q_reg_7_ ( .D(n573), .CK(clk), .RN(n1279), .Q(
data_output[7]) );
DFFRXLTS d_ff5_data_out_Q_reg_8_ ( .D(n571), .CK(clk), .RN(n1278), .Q(
data_output[8]) );
DFFRXLTS d_ff5_data_out_Q_reg_9_ ( .D(n569), .CK(clk), .RN(n1276), .Q(
data_output[9]) );
DFFRXLTS d_ff5_data_out_Q_reg_10_ ( .D(n567), .CK(clk), .RN(n1275), .Q(
data_output[10]) );
DFFRXLTS d_ff5_data_out_Q_reg_11_ ( .D(n565), .CK(clk), .RN(n1278), .Q(
data_output[11]) );
DFFRXLTS d_ff5_data_out_Q_reg_12_ ( .D(n563), .CK(clk), .RN(n1276), .Q(
data_output[12]) );
DFFRXLTS d_ff5_data_out_Q_reg_13_ ( .D(n561), .CK(clk), .RN(n1275), .Q(
data_output[13]) );
DFFRXLTS d_ff5_data_out_Q_reg_14_ ( .D(n559), .CK(clk), .RN(n1250), .Q(
data_output[14]) );
DFFRXLTS d_ff5_data_out_Q_reg_15_ ( .D(n557), .CK(clk), .RN(n1274), .Q(
data_output[15]) );
DFFRXLTS d_ff5_data_out_Q_reg_16_ ( .D(n555), .CK(clk), .RN(n1249), .Q(
data_output[16]) );
DFFRXLTS d_ff5_data_out_Q_reg_17_ ( .D(n553), .CK(clk), .RN(n1259), .Q(
data_output[17]) );
DFFRXLTS d_ff5_data_out_Q_reg_18_ ( .D(n551), .CK(clk), .RN(n1262), .Q(
data_output[18]) );
DFFRXLTS d_ff5_data_out_Q_reg_19_ ( .D(n549), .CK(clk), .RN(n1272), .Q(
data_output[19]) );
DFFRXLTS d_ff5_data_out_Q_reg_20_ ( .D(n547), .CK(clk), .RN(n1262), .Q(
data_output[20]) );
DFFRXLTS d_ff5_data_out_Q_reg_21_ ( .D(n545), .CK(clk), .RN(n1272), .Q(
data_output[21]) );
DFFRXLTS d_ff5_data_out_Q_reg_22_ ( .D(n543), .CK(clk), .RN(n1273), .Q(
data_output[22]) );
DFFRXLTS d_ff5_data_out_Q_reg_23_ ( .D(n541), .CK(clk), .RN(n1259), .Q(
data_output[23]) );
DFFRXLTS d_ff5_data_out_Q_reg_24_ ( .D(n539), .CK(clk), .RN(n1264), .Q(
data_output[24]) );
DFFRXLTS d_ff5_data_out_Q_reg_25_ ( .D(n537), .CK(clk), .RN(n1266), .Q(
data_output[25]) );
DFFRXLTS d_ff5_data_out_Q_reg_26_ ( .D(n535), .CK(clk), .RN(n1268), .Q(
data_output[26]) );
DFFRXLTS d_ff5_data_out_Q_reg_27_ ( .D(n533), .CK(clk), .RN(n1269), .Q(
data_output[27]) );
DFFRXLTS d_ff5_data_out_Q_reg_28_ ( .D(n531), .CK(clk), .RN(n1250), .Q(
data_output[28]) );
DFFRXLTS d_ff5_data_out_Q_reg_29_ ( .D(n529), .CK(clk), .RN(n1265), .Q(
data_output[29]) );
DFFRXLTS d_ff5_data_out_Q_reg_30_ ( .D(n527), .CK(clk), .RN(n1265), .Q(
data_output[30]) );
DFFRXLTS d_ff5_data_out_Q_reg_31_ ( .D(n525), .CK(clk), .RN(n1241), .Q(
data_output[31]) );
DFFRX2TS cont_iter_count_reg_3_ ( .D(n725), .CK(clk), .RN(n1260), .Q(
cont_iter_out[3]), .QN(n1204) );
DFFRX4TS cordic_FSM_state_reg_reg_1_ ( .D(cordic_FSM_state_next_1_), .CK(clk), .RN(n331), .Q(cordic_FSM_state_reg[1]) );
DFFRX2TS reg_val_muxX_2stage_Q_reg_27_ ( .D(n349), .CK(clk), .RN(n1265), .Q(
d_ff2_X[27]) );
DFFRX2TS reg_val_muxX_2stage_Q_reg_24_ ( .D(n352), .CK(clk), .RN(n1245), .Q(
d_ff2_X[24]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_29_ ( .D(n347), .CK(clk), .RN(n1261), .Q(
d_ff2_X[29]) );
DFFRX1TS reg_LUT_Q_reg_27_ ( .D(n497), .CK(clk), .RN(n1244), .Q(
d_ff3_LUT_out[27]) );
DFFRX1TS reg_ch_mux_2_Q_reg_1_ ( .D(n685), .CK(clk), .RN(n1265), .Q(
sel_mux_2_reg[1]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_28_ ( .D(n348), .CK(clk), .RN(n1260), .Q(
d_ff2_X[28]) );
DFFRX1TS reg_region_flag_Q_reg_0_ ( .D(n722), .CK(clk), .RN(n1245), .Q(
d_ff1_shift_region_flag_out[0]), .QN(n1212) );
DFFRX1TS reg_region_flag_Q_reg_1_ ( .D(n721), .CK(clk), .RN(n1265), .Q(
d_ff1_shift_region_flag_out[1]), .QN(n1207) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_24_ ( .D(n416), .CK(clk), .RN(n806), .Q(
d_ff2_Y[24]), .QN(n799) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_26_ ( .D(n350), .CK(clk), .RN(n1265), .Q(
d_ff2_X[26]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_26_ ( .D(n414), .CK(clk), .RN(n1248), .Q(
d_ff2_Y[26]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_25_ ( .D(n415), .CK(clk), .RN(n806), .Q(
d_ff2_Y[25]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_31_ ( .D(n465), .CK(clk), .RN(n1250), .Q(
d_ff2_Z[31]) );
DFFRX1TS reg_ch_mux_3_Q_reg_0_ ( .D(n688), .CK(clk), .RN(n1241), .Q(
sel_mux_3_reg) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_23_ ( .D(n353), .CK(clk), .RN(n1245), .Q(
d_ff2_X[23]), .QN(n1214) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_30_ ( .D(n346), .CK(clk), .RN(n1241), .Q(
d_ff2_X[30]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_27_ ( .D(n413), .CK(clk), .RN(n1248), .Q(
d_ff2_Y[27]), .QN(n1209) );
DFFRX1TS reg_ch_mux_1_Q_reg_0_ ( .D(n687), .CK(clk), .RN(n1265), .Q(
sel_mux_1_reg) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_31_ ( .D(n401), .CK(clk), .RN(n1256), .Q(
d_ff2_Y[31]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_22_ ( .D(n419), .CK(clk), .RN(n1255), .Q(
d_ff2_Y[22]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_21_ ( .D(n421), .CK(clk), .RN(n1256), .Q(
d_ff2_Y[21]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_20_ ( .D(n423), .CK(clk), .RN(n1248), .Q(
d_ff2_Y[20]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_19_ ( .D(n425), .CK(clk), .RN(n1255), .Q(
d_ff2_Y[19]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_18_ ( .D(n427), .CK(clk), .RN(n1256), .Q(
d_ff2_Y[18]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_17_ ( .D(n429), .CK(clk), .RN(n1253), .Q(
d_ff2_Y[17]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_16_ ( .D(n431), .CK(clk), .RN(n1252), .Q(
d_ff2_Y[16]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_15_ ( .D(n433), .CK(clk), .RN(n1255), .Q(
d_ff2_Y[15]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_14_ ( .D(n435), .CK(clk), .RN(n1256), .Q(
d_ff2_Y[14]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_13_ ( .D(n437), .CK(clk), .RN(n1253), .Q(
d_ff2_Y[13]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_12_ ( .D(n439), .CK(clk), .RN(n1252), .Q(
d_ff2_Y[12]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_11_ ( .D(n441), .CK(clk), .RN(n806), .Q(
d_ff2_Y[11]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_10_ ( .D(n443), .CK(clk), .RN(n1254), .Q(
d_ff2_Y[10]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_9_ ( .D(n445), .CK(clk), .RN(n806), .Q(
d_ff2_Y[9]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_8_ ( .D(n447), .CK(clk), .RN(n1248), .Q(
d_ff2_Y[8]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_7_ ( .D(n449), .CK(clk), .RN(n1255), .Q(
d_ff2_Y[7]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_6_ ( .D(n451), .CK(clk), .RN(n1256), .Q(
d_ff2_Y[6]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_5_ ( .D(n453), .CK(clk), .RN(n1274), .Q(
d_ff2_Y[5]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_4_ ( .D(n455), .CK(clk), .RN(n1249), .Q(
d_ff2_Y[4]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_3_ ( .D(n457), .CK(clk), .RN(n1250), .Q(
d_ff2_Y[3]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_2_ ( .D(n459), .CK(clk), .RN(n1274), .Q(
d_ff2_Y[2]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_1_ ( .D(n461), .CK(clk), .RN(n1249), .Q(
d_ff2_Y[1]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_0_ ( .D(n463), .CK(clk), .RN(n1250), .Q(
d_ff2_Y[0]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_20_ ( .D(n359), .CK(clk), .RN(n1273), .Q(
d_ff2_X[20]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_19_ ( .D(n361), .CK(clk), .RN(n1272), .Q(
d_ff2_X[19]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_17_ ( .D(n365), .CK(clk), .RN(n1258), .Q(
d_ff2_X[17]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_16_ ( .D(n367), .CK(clk), .RN(n1258), .Q(
d_ff2_X[16]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_14_ ( .D(n371), .CK(clk), .RN(n1258), .Q(
d_ff2_X[14]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_13_ ( .D(n373), .CK(clk), .RN(n1258), .Q(
d_ff2_X[13]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_12_ ( .D(n375), .CK(clk), .RN(n1257), .Q(
d_ff2_X[12]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_10_ ( .D(n379), .CK(clk), .RN(n1257), .Q(
d_ff2_X[10]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_7_ ( .D(n385), .CK(clk), .RN(n1253), .Q(
d_ff2_X[7]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_6_ ( .D(n387), .CK(clk), .RN(n1252), .Q(
d_ff2_X[6]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_5_ ( .D(n389), .CK(clk), .RN(n806), .Q(
d_ff2_X[5]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_3_ ( .D(n393), .CK(clk), .RN(n1248), .Q(
d_ff2_X[3]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_2_ ( .D(n395), .CK(clk), .RN(n1253), .Q(
d_ff2_X[2]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_1_ ( .D(n397), .CK(clk), .RN(n1252), .Q(
d_ff2_X[1]) );
DFFRX1TS d_ff4_Xn_Q_reg_25_ ( .D(n595), .CK(clk), .RN(n1269), .Q(d_ff_Xn[25]) );
DFFRX1TS d_ff4_Xn_Q_reg_27_ ( .D(n593), .CK(clk), .RN(n1271), .Q(d_ff_Xn[27]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_22_ ( .D(n355), .CK(clk), .RN(n1259), .Q(
d_ff2_X[22]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_21_ ( .D(n357), .CK(clk), .RN(n1262), .Q(
d_ff2_X[21]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_18_ ( .D(n363), .CK(clk), .RN(n1273), .Q(
d_ff2_X[18]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_15_ ( .D(n369), .CK(clk), .RN(n1258), .Q(
d_ff2_X[15]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_11_ ( .D(n377), .CK(clk), .RN(n1257), .Q(
d_ff2_X[11]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_9_ ( .D(n381), .CK(clk), .RN(n1257), .Q(
d_ff2_X[9]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_8_ ( .D(n383), .CK(clk), .RN(n1257), .Q(
d_ff2_X[8]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_4_ ( .D(n391), .CK(clk), .RN(n1255), .Q(
d_ff2_X[4]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_0_ ( .D(n399), .CK(clk), .RN(n1251), .Q(
d_ff2_X[0]) );
DFFRX1TS d_ff4_Xn_Q_reg_31_ ( .D(n589), .CK(clk), .RN(n1260), .Q(d_ff_Xn[31]) );
DFFRX1TS cont_var_count_reg_1_ ( .D(n729), .CK(clk), .RN(n1261), .Q(
cont_var_out[1]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_29_ ( .D(n411), .CK(clk), .RN(n1254), .Q(
d_ff2_Y[29]), .QN(n1210) );
DFFRX1TS d_ff4_Xn_Q_reg_10_ ( .D(n610), .CK(clk), .RN(n1278), .Q(d_ff_Xn[10]) );
DFFRX1TS d_ff4_Xn_Q_reg_0_ ( .D(n620), .CK(clk), .RN(n1278), .Q(d_ff_Xn[0])
);
DFFRX1TS d_ff4_Yn_Q_reg_1_ ( .D(n651), .CK(clk), .RN(n1267), .Q(d_ff_Yn[1]),
.QN(n1216) );
DFFRX1TS d_ff4_Yn_Q_reg_14_ ( .D(n638), .CK(clk), .RN(n1267), .Q(d_ff_Yn[14]), .QN(n1229) );
DFFRX1TS d_ff4_Yn_Q_reg_7_ ( .D(n645), .CK(clk), .RN(n1267), .Q(d_ff_Yn[7]),
.QN(n1222) );
DFFRX1TS reg_LUT_Q_reg_16_ ( .D(n508), .CK(clk), .RN(n1247), .Q(
d_ff3_LUT_out[16]) );
DFFRX1TS reg_LUT_Q_reg_11_ ( .D(n513), .CK(clk), .RN(n1247), .Q(
d_ff3_LUT_out[11]) );
DFFRX1TS reg_LUT_Q_reg_6_ ( .D(n518), .CK(clk), .RN(n1247), .Q(
d_ff3_LUT_out[6]) );
DFFRX1TS reg_LUT_Q_reg_1_ ( .D(n523), .CK(clk), .RN(n1247), .Q(
d_ff3_LUT_out[1]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_2_ ( .D(n494), .CK(clk), .RN(n1247), .Q(
d_ff2_Z[2]) );
DFFRX1TS reg_operation_Q_reg_0_ ( .D(n723), .CK(clk), .RN(n1245), .Q(
d_ff1_operation_out), .QN(n1203) );
DFFRX1TS d_ff4_Xn_Q_reg_1_ ( .D(n619), .CK(clk), .RN(n1277), .Q(d_ff_Xn[1])
);
DFFRX1TS d_ff4_Xn_Q_reg_2_ ( .D(n618), .CK(clk), .RN(n1279), .Q(d_ff_Xn[2])
);
DFFRX1TS d_ff4_Xn_Q_reg_3_ ( .D(n617), .CK(clk), .RN(n1275), .Q(d_ff_Xn[3])
);
DFFRX1TS d_ff4_Xn_Q_reg_5_ ( .D(n615), .CK(clk), .RN(n1275), .Q(d_ff_Xn[5])
);
DFFRX1TS d_ff4_Xn_Q_reg_6_ ( .D(n614), .CK(clk), .RN(n1278), .Q(d_ff_Xn[6])
);
DFFRX1TS d_ff4_Xn_Q_reg_7_ ( .D(n613), .CK(clk), .RN(n1279), .Q(d_ff_Xn[7])
);
DFFRX1TS d_ff4_Xn_Q_reg_12_ ( .D(n608), .CK(clk), .RN(n1275), .Q(d_ff_Xn[12]) );
DFFRX1TS d_ff4_Xn_Q_reg_13_ ( .D(n607), .CK(clk), .RN(n1279), .Q(d_ff_Xn[13]) );
DFFRX1TS d_ff4_Xn_Q_reg_14_ ( .D(n606), .CK(clk), .RN(n1249), .Q(d_ff_Xn[14]) );
DFFRX1TS d_ff4_Xn_Q_reg_16_ ( .D(n604), .CK(clk), .RN(n1274), .Q(d_ff_Xn[16]) );
DFFRX1TS d_ff4_Xn_Q_reg_17_ ( .D(n603), .CK(clk), .RN(n1249), .Q(d_ff_Xn[17]) );
DFFRX1TS d_ff4_Xn_Q_reg_19_ ( .D(n601), .CK(clk), .RN(n1259), .Q(d_ff_Xn[19]) );
DFFRX1TS d_ff4_Xn_Q_reg_20_ ( .D(n600), .CK(clk), .RN(n1272), .Q(d_ff_Xn[20]) );
DFFRX1TS d_ff4_Xn_Q_reg_24_ ( .D(n596), .CK(clk), .RN(n1270), .Q(d_ff_Xn[24]) );
DFFRX1TS d_ff4_Xn_Q_reg_26_ ( .D(n594), .CK(clk), .RN(n1266), .Q(d_ff_Xn[26]) );
DFFRX1TS d_ff4_Xn_Q_reg_28_ ( .D(n592), .CK(clk), .RN(n1266), .Q(d_ff_Xn[28]) );
DFFRX1TS d_ff4_Xn_Q_reg_29_ ( .D(n591), .CK(clk), .RN(n1241), .Q(d_ff_Xn[29]) );
DFFRX1TS d_ff4_Xn_Q_reg_4_ ( .D(n616), .CK(clk), .RN(n1279), .Q(d_ff_Xn[4])
);
DFFRX1TS d_ff4_Xn_Q_reg_8_ ( .D(n612), .CK(clk), .RN(n1277), .Q(d_ff_Xn[8])
);
DFFRX1TS d_ff4_Xn_Q_reg_9_ ( .D(n611), .CK(clk), .RN(n1279), .Q(d_ff_Xn[9])
);
DFFRX1TS d_ff4_Xn_Q_reg_11_ ( .D(n609), .CK(clk), .RN(n1277), .Q(d_ff_Xn[11]) );
DFFRX1TS d_ff4_Xn_Q_reg_15_ ( .D(n605), .CK(clk), .RN(n1250), .Q(d_ff_Xn[15]) );
DFFRX1TS d_ff4_Xn_Q_reg_18_ ( .D(n602), .CK(clk), .RN(n1272), .Q(d_ff_Xn[18]) );
DFFRX1TS d_ff4_Xn_Q_reg_21_ ( .D(n599), .CK(clk), .RN(n1259), .Q(d_ff_Xn[21]) );
DFFRX1TS d_ff4_Xn_Q_reg_22_ ( .D(n598), .CK(clk), .RN(n1272), .Q(d_ff_Xn[22]) );
DFFRX1TS d_ff4_Xn_Q_reg_30_ ( .D(n590), .CK(clk), .RN(n1241), .Q(d_ff_Xn[30]) );
DFFRX1TS d_ff4_Xn_Q_reg_23_ ( .D(n597), .CK(clk), .RN(n1259), .Q(d_ff_Xn[23]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_31_ ( .D(n337), .CK(clk), .RN(n1241), .Q(
d_ff2_X[31]) );
DFFRX1TS d_ff4_Yn_Q_reg_26_ ( .D(n626), .CK(clk), .RN(n1276), .Q(d_ff_Yn[26]), .QN(n1239) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_23_ ( .D(n417), .CK(clk), .RN(n1251), .Q(
d_ff2_Y[23]), .QN(n801) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_25_ ( .D(n471), .CK(clk), .RN(n1252), .Q(
d_ff2_Z[25]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_28_ ( .D(n468), .CK(clk), .RN(n1250), .Q(
d_ff2_Z[28]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_29_ ( .D(n467), .CK(clk), .RN(n1274), .Q(
d_ff2_Z[29]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_23_ ( .D(n473), .CK(clk), .RN(n1256), .Q(
d_ff2_Z[23]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_24_ ( .D(n472), .CK(clk), .RN(n1253), .Q(
d_ff2_Z[24]) );
DFFRX4TS cordic_FSM_state_reg_reg_2_ ( .D(n731), .CK(clk), .RN(n331), .Q(
cordic_FSM_state_reg[2]), .QN(n1202) );
DFFRX1TS d_ff5_Q_reg_31_ ( .D(n526), .CK(clk), .RN(n1261), .Q(
data_output2_31_) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_21_ ( .D(n475), .CK(clk), .RN(n1248), .Q(
d_ff2_Z[21]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_22_ ( .D(n474), .CK(clk), .RN(n1255), .Q(
d_ff2_Z[22]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_25_ ( .D(n351), .CK(clk), .RN(n1261), .Q(
d_ff2_X[25]), .QN(n800) );
DFFRX2TS cordic_FSM_state_reg_reg_3_ ( .D(n732), .CK(clk), .RN(n331), .Q(
cordic_FSM_state_reg[3]), .QN(n1206) );
DFFRXLTS reg_Z0_Q_reg_0_ ( .D(n720), .CK(clk), .RN(n1261), .Q(d_ff1_Z[0]) );
DFFRX2TS cont_iter_count_reg_1_ ( .D(n727), .CK(clk), .RN(n1265), .Q(
cont_iter_out[1]), .QN(n798) );
CLKBUFX2TS U795 ( .A(n813), .Y(n1019) );
OAI32X1TS U796 ( .A0(n1191), .A1(n1104), .A2(n867), .B0(n1109), .B1(n1191),
.Y(n822) );
AOI222X1TS U797 ( .A0(n1198), .A1(d_ff2_Z[27]), .B0(n1009), .B1(d_ff1_Z[27]),
.C0(d_ff_Zn[27]), .C1(n1199), .Y(n998) );
AOI222X1TS U798 ( .A0(d_ff2_Z[1]), .A1(n951), .B0(d_ff2_Y[1]), .B1(n1023),
.C0(d_ff2_X[1]), .C1(n953), .Y(n877) );
AOI222X1TS U799 ( .A0(d_ff2_Z[3]), .A1(n960), .B0(d_ff2_Y[3]), .B1(n956),
.C0(d_ff2_X[3]), .C1(n876), .Y(n859) );
AOI222X1TS U800 ( .A0(d_ff2_Z[4]), .A1(n960), .B0(d_ff2_Y[4]), .B1(n956),
.C0(d_ff2_X[4]), .C1(n876), .Y(n852) );
AOI222X1TS U801 ( .A0(d_ff2_Z[5]), .A1(n960), .B0(d_ff2_Y[5]), .B1(n956),
.C0(d_ff2_X[5]), .C1(n876), .Y(n858) );
AOI222X1TS U802 ( .A0(d_ff2_Z[6]), .A1(n960), .B0(d_ff2_Y[6]), .B1(n956),
.C0(d_ff2_X[6]), .C1(n876), .Y(n851) );
AOI222X1TS U803 ( .A0(d_ff2_Z[7]), .A1(n960), .B0(d_ff2_Y[7]), .B1(n974),
.C0(d_ff2_X[7]), .C1(n876), .Y(n855) );
AOI222X1TS U804 ( .A0(d_ff2_Z[9]), .A1(n960), .B0(d_ff2_Y[9]), .B1(n956),
.C0(d_ff2_X[9]), .C1(n876), .Y(n854) );
AOI222X1TS U805 ( .A0(d_ff2_Z[8]), .A1(n966), .B0(d_ff2_Y[8]), .B1(n956),
.C0(d_ff2_X[8]), .C1(n876), .Y(n853) );
AOI222X1TS U806 ( .A0(d_ff2_Z[11]), .A1(n966), .B0(d_ff2_Y[11]), .B1(n956),
.C0(d_ff2_X[11]), .C1(n876), .Y(n856) );
AOI222X1TS U807 ( .A0(d_ff2_Z[12]), .A1(n966), .B0(d_ff2_Y[12]), .B1(n956),
.C0(d_ff2_X[12]), .C1(n876), .Y(n878) );
AOI222X1TS U808 ( .A0(d_ff2_Z[10]), .A1(n960), .B0(d_ff2_Y[10]), .B1(n956),
.C0(d_ff2_X[10]), .C1(n965), .Y(n957) );
AOI222X1TS U809 ( .A0(d_ff2_Z[13]), .A1(n966), .B0(d_ff2_Y[13]), .B1(n956),
.C0(d_ff2_X[13]), .C1(n965), .Y(n954) );
AOI222X1TS U810 ( .A0(d_ff2_Z[14]), .A1(n966), .B0(d_ff2_Y[14]), .B1(n974),
.C0(d_ff2_X[14]), .C1(n965), .Y(n967) );
AOI222X1TS U811 ( .A0(d_ff2_Z[15]), .A1(n966), .B0(d_ff2_Y[15]), .B1(n974),
.C0(d_ff2_X[15]), .C1(n965), .Y(n963) );
AOI222X1TS U812 ( .A0(d_ff2_Z[16]), .A1(n966), .B0(d_ff2_Y[16]), .B1(n974),
.C0(d_ff2_X[16]), .C1(n965), .Y(n955) );
AOI222X1TS U813 ( .A0(d_ff2_Z[17]), .A1(n966), .B0(d_ff2_Y[17]), .B1(n974),
.C0(d_ff2_X[17]), .C1(n965), .Y(n958) );
AOI222X1TS U814 ( .A0(d_ff2_Z[18]), .A1(n966), .B0(d_ff2_Y[18]), .B1(n974),
.C0(d_ff2_X[18]), .C1(n965), .Y(n962) );
AOI222X1TS U815 ( .A0(d_ff2_Z[19]), .A1(n966), .B0(d_ff2_Y[19]), .B1(n974),
.C0(d_ff2_X[19]), .C1(n965), .Y(n964) );
AOI222X1TS U816 ( .A0(d_ff2_Z[0]), .A1(n975), .B0(d_ff2_Y[0]), .B1(n971),
.C0(d_ff2_X[0]), .C1(n973), .Y(n972) );
AOI222X1TS U817 ( .A0(d_ff2_Z[20]), .A1(n975), .B0(d_ff2_Y[20]), .B1(n974),
.C0(d_ff2_X[20]), .C1(n973), .Y(n968) );
AOI222X1TS U818 ( .A0(d_ff2_Z[26]), .A1(n975), .B0(d_ff2_Y[26]), .B1(n974),
.C0(d_ff2_X[26]), .C1(n973), .Y(n976) );
AOI222X1TS U819 ( .A0(d_ff3_LUT_out[2]), .A1(n969), .B0(n1027), .B1(
d_ff3_sh_x_out[2]), .C0(n973), .C1(d_ff3_sh_y_out[2]), .Y(n924) );
AOI222X1TS U820 ( .A0(d_ff3_LUT_out[0]), .A1(n969), .B0(n1027), .B1(
d_ff3_sh_x_out[0]), .C0(n973), .C1(d_ff3_sh_y_out[0]), .Y(n923) );
AOI222X1TS U821 ( .A0(d_ff3_LUT_out[23]), .A1(n975), .B0(d_ff3_sh_y_out[23]),
.B1(n973), .C0(d_ff3_sh_x_out[23]), .C1(n1023), .Y(n921) );
AOI222X1TS U822 ( .A0(d_ff3_LUT_out[24]), .A1(n975), .B0(d_ff3_sh_y_out[24]),
.B1(n973), .C0(d_ff3_sh_x_out[24]), .C1(n1023), .Y(n922) );
AOI222X1TS U823 ( .A0(d_ff3_sh_x_out[25]), .A1(n971), .B0(d_ff3_LUT_out[25]),
.B1(n951), .C0(n950), .C1(d_ff3_sh_y_out[25]), .Y(n946) );
NOR2XLTS U824 ( .A(sel_mux_2_reg[0]), .B(sel_mux_2_reg[1]), .Y(n816) );
CLKBUFX3TS U825 ( .A(n1195), .Y(n1129) );
NAND3XLTS U826 ( .A(n1022), .B(n1177), .C(n1021), .Y(
cordic_FSM_state_next_1_) );
INVX4TS U827 ( .A(n809), .Y(n1110) );
INVX4TS U828 ( .A(n811), .Y(n1181) );
INVX1TS U829 ( .A(n810), .Y(n1089) );
AO22XLTS U830 ( .A0(n1158), .A1(n1147), .B0(n1160), .B1(d_ff3_sh_y_out[26]),
.Y(n406) );
ADDFX1TS U831 ( .A(n1204), .B(d_ff2_X[26]), .CI(n1183), .CO(n1188), .S(n1182) );
INVX2TS U832 ( .A(n1159), .Y(n1007) );
INVX2TS U833 ( .A(n1159), .Y(n1199) );
OAI211X2TS U834 ( .A0(n1181), .A1(n867), .B0(n1193), .C0(n1114), .Y(n1115)
);
AO22XLTS U835 ( .A0(n1158), .A1(d_ff2_Y[22]), .B0(n1160), .B1(
d_ff3_sh_y_out[22]), .Y(n418) );
AO22XLTS U836 ( .A0(n1133), .A1(d_ff2_Y[21]), .B0(n1200), .B1(
d_ff3_sh_y_out[21]), .Y(n420) );
AO22XLTS U837 ( .A0(n1158), .A1(d_ff2_Y[20]), .B0(n1200), .B1(
d_ff3_sh_y_out[20]), .Y(n422) );
AO22XLTS U838 ( .A0(n1187), .A1(d_ff2_Y[19]), .B0(n1200), .B1(
d_ff3_sh_y_out[19]), .Y(n424) );
AO22XLTS U839 ( .A0(n1201), .A1(d_ff2_Y[18]), .B0(n1200), .B1(
d_ff3_sh_y_out[18]), .Y(n426) );
AO22XLTS U840 ( .A0(n1133), .A1(d_ff2_Y[17]), .B0(n1200), .B1(
d_ff3_sh_y_out[17]), .Y(n428) );
AO22XLTS U841 ( .A0(n1197), .A1(d_ff2_Y[16]), .B0(n1200), .B1(
d_ff3_sh_y_out[16]), .Y(n430) );
AO22XLTS U842 ( .A0(n1133), .A1(d_ff2_Y[15]), .B0(n1200), .B1(
d_ff3_sh_y_out[15]), .Y(n432) );
AO22XLTS U843 ( .A0(n1201), .A1(d_ff2_Y[14]), .B0(n1200), .B1(
d_ff3_sh_y_out[14]), .Y(n434) );
AO22XLTS U844 ( .A0(n1187), .A1(d_ff2_Y[13]), .B0(n1200), .B1(
d_ff3_sh_y_out[13]), .Y(n436) );
AO22XLTS U845 ( .A0(n1201), .A1(d_ff2_Y[11]), .B0(n1131), .B1(
d_ff3_sh_y_out[11]), .Y(n440) );
AO22XLTS U846 ( .A0(n1197), .A1(d_ff2_Y[3]), .B0(n1131), .B1(
d_ff3_sh_y_out[3]), .Y(n456) );
AO22XLTS U847 ( .A0(n1197), .A1(d_ff2_Y[7]), .B0(n1131), .B1(
d_ff3_sh_y_out[7]), .Y(n448) );
AO22XLTS U848 ( .A0(n1201), .A1(d_ff2_Y[8]), .B0(n1131), .B1(
d_ff3_sh_y_out[8]), .Y(n446) );
AO22XLTS U849 ( .A0(n1201), .A1(d_ff2_Y[4]), .B0(n1131), .B1(
d_ff3_sh_y_out[4]), .Y(n454) );
AO22XLTS U850 ( .A0(n1158), .A1(d_ff2_Y[10]), .B0(n1131), .B1(
d_ff3_sh_y_out[10]), .Y(n442) );
ADDFX1TS U851 ( .A(d_ff2_Y[26]), .B(n1204), .CI(n1148), .CO(n1150), .S(n1147) );
AO22XLTS U852 ( .A0(n1197), .A1(d_ff2_Y[5]), .B0(n1131), .B1(
d_ff3_sh_y_out[5]), .Y(n452) );
AO22XLTS U853 ( .A0(n1201), .A1(d_ff2_Y[9]), .B0(n1131), .B1(
d_ff3_sh_y_out[9]), .Y(n444) );
NAND2BX2TS U854 ( .AN(n884), .B(sel_mux_3_reg), .Y(n886) );
NOR2X2TS U855 ( .A(sel_mux_3_reg), .B(n884), .Y(n860) );
INVX2TS U856 ( .A(n1191), .Y(n1133) );
INVX2TS U857 ( .A(n1191), .Y(n1187) );
CLKBUFX3TS U858 ( .A(n1195), .Y(n1119) );
AOI222X1TS U859 ( .A0(d_ff3_LUT_out[1]), .A1(n969), .B0(n1027), .B1(
d_ff3_sh_x_out[1]), .C0(n973), .C1(d_ff3_sh_y_out[1]), .Y(n926) );
ADDFX1TS U860 ( .A(d_ff2_Y[25]), .B(n804), .CI(n1146), .CO(n1148), .S(n1145)
);
INVX3TS U861 ( .A(n1191), .Y(n1193) );
AOI222X1TS U862 ( .A0(d_ff3_LUT_out[6]), .A1(n969), .B0(n1027), .B1(
d_ff3_sh_x_out[6]), .C0(n948), .C1(d_ff3_sh_y_out[6]), .Y(n941) );
NOR2X2TS U863 ( .A(sel_mux_1_reg), .B(n1004), .Y(n871) );
CLKBUFX3TS U864 ( .A(n960), .Y(n951) );
NAND2X2TS U865 ( .A(n1137), .B(sel_mux_1_reg), .Y(n1159) );
XOR2XLTS U866 ( .A(n1176), .B(n1175), .Y(n1178) );
INVX2TS U867 ( .A(n848), .Y(n956) );
NAND3X2TS U868 ( .A(n1040), .B(cordic_FSM_state_reg[0]), .C(
cordic_FSM_state_reg[3]), .Y(n884) );
XOR2XLTS U869 ( .A(data_output2_31_), .B(n826), .Y(n827) );
INVX2TS U870 ( .A(n1110), .Y(n1104) );
INVX3TS U871 ( .A(n841), .Y(n937) );
AND3X2TS U872 ( .A(n1036), .B(n1202), .C(n803), .Y(n812) );
CLKINVX2TS U873 ( .A(d_ff2_Y[28]), .Y(n1151) );
OR2X2TS U874 ( .A(n1205), .B(sel_mux_2_reg[1]), .Y(n848) );
NAND4XLTS U875 ( .A(n1206), .B(cordic_FSM_state_reg[1]), .C(
cordic_FSM_state_reg[2]), .D(cordic_FSM_state_reg[0]), .Y(n1015) );
BUFX3TS U876 ( .A(n816), .Y(n1024) );
BUFX3TS U877 ( .A(n848), .Y(n931) );
INVX2TS U878 ( .A(n1035), .Y(n1040) );
OAI21XLTS U879 ( .A0(cont_iter_out[1]), .A1(n1048), .B0(n1057), .Y(n1047) );
AO22XLTS U880 ( .A0(n1088), .A1(result_add_subt[23]), .B0(n1087), .B1(
d_ff_Xn[23]), .Y(n597) );
AO22XLTS U881 ( .A0(n1089), .A1(result_add_subt[30]), .B0(n810), .B1(
d_ff_Xn[30]), .Y(n590) );
AO22XLTS U882 ( .A0(n1088), .A1(result_add_subt[22]), .B0(n1087), .B1(
d_ff_Xn[22]), .Y(n598) );
AO22XLTS U883 ( .A0(n1088), .A1(result_add_subt[21]), .B0(n1087), .B1(
d_ff_Xn[21]), .Y(n599) );
AO22XLTS U884 ( .A0(n1086), .A1(result_add_subt[18]), .B0(n1087), .B1(
d_ff_Xn[18]), .Y(n602) );
AO22XLTS U885 ( .A0(n1086), .A1(result_add_subt[15]), .B0(n1085), .B1(
d_ff_Xn[15]), .Y(n605) );
AO22XLTS U886 ( .A0(n1086), .A1(result_add_subt[11]), .B0(n1085), .B1(
d_ff_Xn[11]), .Y(n609) );
AO22XLTS U887 ( .A0(n1084), .A1(result_add_subt[9]), .B0(n1085), .B1(
d_ff_Xn[9]), .Y(n611) );
AO22XLTS U888 ( .A0(n1084), .A1(result_add_subt[8]), .B0(n1085), .B1(
d_ff_Xn[8]), .Y(n612) );
AO22XLTS U889 ( .A0(n1084), .A1(result_add_subt[4]), .B0(n1083), .B1(
d_ff_Xn[4]), .Y(n616) );
AO22XLTS U890 ( .A0(n1088), .A1(result_add_subt[29]), .B0(n810), .B1(
d_ff_Xn[29]), .Y(n591) );
AO22XLTS U891 ( .A0(n1088), .A1(result_add_subt[28]), .B0(n810), .B1(
d_ff_Xn[28]), .Y(n592) );
AO22XLTS U892 ( .A0(n1088), .A1(result_add_subt[26]), .B0(n1087), .B1(
d_ff_Xn[26]), .Y(n594) );
AO22XLTS U893 ( .A0(n1088), .A1(result_add_subt[24]), .B0(n1087), .B1(
d_ff_Xn[24]), .Y(n596) );
AO22XLTS U894 ( .A0(n1088), .A1(result_add_subt[20]), .B0(n1087), .B1(
d_ff_Xn[20]), .Y(n600) );
AO22XLTS U895 ( .A0(n1086), .A1(result_add_subt[17]), .B0(n1085), .B1(
d_ff_Xn[17]), .Y(n603) );
AO22XLTS U896 ( .A0(n1086), .A1(result_add_subt[16]), .B0(n1085), .B1(
d_ff_Xn[16]), .Y(n604) );
AO22XLTS U897 ( .A0(n1086), .A1(result_add_subt[14]), .B0(n1085), .B1(
d_ff_Xn[14]), .Y(n606) );
AO22XLTS U898 ( .A0(n1086), .A1(result_add_subt[13]), .B0(n1085), .B1(
d_ff_Xn[13]), .Y(n607) );
AO22XLTS U899 ( .A0(n1086), .A1(result_add_subt[12]), .B0(n1085), .B1(
d_ff_Xn[12]), .Y(n608) );
AO22XLTS U900 ( .A0(n1084), .A1(result_add_subt[7]), .B0(n1083), .B1(
d_ff_Xn[7]), .Y(n613) );
AO22XLTS U901 ( .A0(n1084), .A1(result_add_subt[5]), .B0(n1083), .B1(
d_ff_Xn[5]), .Y(n615) );
AO22XLTS U902 ( .A0(n1084), .A1(result_add_subt[3]), .B0(n1083), .B1(
d_ff_Xn[3]), .Y(n617) );
AO22XLTS U903 ( .A0(n1084), .A1(result_add_subt[2]), .B0(n1083), .B1(
d_ff_Xn[2]), .Y(n618) );
AO22XLTS U904 ( .A0(n1084), .A1(result_add_subt[1]), .B0(n1083), .B1(
d_ff_Xn[1]), .Y(n619) );
AO22XLTS U905 ( .A0(n1084), .A1(result_add_subt[0]), .B0(n810), .B1(
d_ff_Xn[0]), .Y(n620) );
AO22XLTS U906 ( .A0(n1086), .A1(result_add_subt[10]), .B0(n1085), .B1(
d_ff_Xn[10]), .Y(n610) );
AO22XLTS U907 ( .A0(n1088), .A1(result_add_subt[27]), .B0(n1087), .B1(
d_ff_Xn[27]), .Y(n593) );
AO22XLTS U908 ( .A0(n1088), .A1(result_add_subt[25]), .B0(n1087), .B1(
d_ff_Xn[25]), .Y(n595) );
AO22XLTS U909 ( .A0(d_ff_Xn[30]), .A1(n1173), .B0(d_ff2_X[30]), .B1(n1172),
.Y(n346) );
AO22XLTS U910 ( .A0(d_ff2_X[23]), .A1(n1128), .B0(d_ff_Xn[23]), .B1(n1173),
.Y(n353) );
CLKINVX3TS U911 ( .A(n931), .Y(n943) );
CLKINVX3TS U912 ( .A(n931), .Y(n1027) );
CLKINVX3TS U913 ( .A(n848), .Y(n974) );
CLKINVX3TS U914 ( .A(n931), .Y(n971) );
INVX2TS U915 ( .A(n1169), .Y(n1172) );
INVX2TS U916 ( .A(n1169), .Y(n1004) );
INVX2TS U917 ( .A(d_ff_Yn[30]), .Y(n1140) );
INVX2TS U918 ( .A(d_ff_Yn[29]), .Y(n1139) );
INVX2TS U919 ( .A(d_ff_Yn[27]), .Y(n1136) );
INVX2TS U920 ( .A(d_ff_Yn[24]), .Y(n1135) );
INVX2TS U921 ( .A(d_ff_Yn[23]), .Y(n1134) );
AOI222X1TS U922 ( .A0(d_ff2_Z[2]), .A1(n960), .B0(d_ff2_Y[2]), .B1(n1023),
.C0(d_ff2_X[2]), .C1(n876), .Y(n857) );
OAI21XLTS U923 ( .A0(n799), .A1(n931), .B0(n850), .Y(add_subt_dataA[24]) );
AOI211X1TS U924 ( .A0(n1078), .A1(n1202), .B0(n1036), .C0(n1040), .Y(n1016)
);
AOI2BB2XLTS U925 ( .B0(n800), .B1(n1168), .A0N(d_ff_Xn[25]), .A1N(n1167),
.Y(n351) );
NAND4XLTS U926 ( .A(cordic_FSM_state_reg[3]), .B(n1202), .C(n1049), .D(n1032), .Y(n1033) );
AO22XLTS U927 ( .A0(d_ff_Xn[31]), .A1(n1007), .B0(d_ff2_X[31]), .B1(n1130),
.Y(n337) );
AO22XLTS U928 ( .A0(n1086), .A1(result_add_subt[19]), .B0(n1087), .B1(
d_ff_Xn[19]), .Y(n601) );
AO22XLTS U929 ( .A0(n1084), .A1(result_add_subt[6]), .B0(n1083), .B1(
d_ff_Xn[6]), .Y(n614) );
AO22XLTS U930 ( .A0(n1057), .A1(d_ff1_operation_out), .B0(n1060), .B1(
operation), .Y(n723) );
AOI222X1TS U931 ( .A0(n1168), .A1(d_ff2_Z[2]), .B0(n990), .B1(d_ff1_Z[2]),
.C0(d_ff_Zn[2]), .C1(n1007), .Y(n981) );
AO21XLTS U932 ( .A0(d_ff3_LUT_out[11]), .A1(n1129), .B0(n821), .Y(n513) );
OAI21XLTS U933 ( .A0(n1079), .A1(n1051), .B0(n1177), .Y(n1044) );
AO22XLTS U934 ( .A0(n1089), .A1(result_add_subt[31]), .B0(n810), .B1(
d_ff_Xn[31]), .Y(n589) );
AO22XLTS U935 ( .A0(d_ff_Xn[0]), .A1(n1161), .B0(d_ff2_X[0]), .B1(n1004),
.Y(n399) );
AO22XLTS U936 ( .A0(d_ff_Xn[4]), .A1(n1161), .B0(d_ff2_X[4]), .B1(n1172),
.Y(n391) );
AO22XLTS U937 ( .A0(d_ff_Xn[8]), .A1(n1161), .B0(d_ff2_X[8]), .B1(n1164),
.Y(n383) );
AO22XLTS U938 ( .A0(d_ff_Xn[9]), .A1(n1199), .B0(d_ff2_X[9]), .B1(n1164),
.Y(n381) );
AO22XLTS U939 ( .A0(d_ff_Xn[11]), .A1(n1173), .B0(d_ff2_X[11]), .B1(n1130),
.Y(n377) );
AO22XLTS U940 ( .A0(d_ff_Xn[15]), .A1(n1173), .B0(d_ff2_X[15]), .B1(n1198),
.Y(n369) );
AO22XLTS U941 ( .A0(d_ff_Xn[18]), .A1(n1173), .B0(d_ff2_X[18]), .B1(n1198),
.Y(n363) );
AO22XLTS U942 ( .A0(d_ff_Xn[21]), .A1(n1173), .B0(d_ff2_X[21]), .B1(n1128),
.Y(n357) );
AO22XLTS U943 ( .A0(d_ff_Xn[22]), .A1(n1173), .B0(d_ff2_X[22]), .B1(n1004),
.Y(n355) );
AO22XLTS U944 ( .A0(d_ff_Yn[0]), .A1(n1173), .B0(d_ff2_Y[0]), .B1(n1130),
.Y(n463) );
AO22XLTS U945 ( .A0(d_ff_Yn[1]), .A1(n1199), .B0(d_ff2_Y[1]), .B1(n1130),
.Y(n461) );
AO22XLTS U946 ( .A0(d_ff_Yn[2]), .A1(n1007), .B0(d_ff2_Y[2]), .B1(n1198),
.Y(n459) );
AO22XLTS U947 ( .A0(d_ff_Yn[3]), .A1(n1199), .B0(d_ff2_Y[3]), .B1(n1198),
.Y(n457) );
AO22XLTS U948 ( .A0(d_ff_Yn[4]), .A1(n1132), .B0(d_ff2_Y[4]), .B1(n1164),
.Y(n455) );
AO22XLTS U949 ( .A0(d_ff_Yn[5]), .A1(n1007), .B0(d_ff2_Y[5]), .B1(n1128),
.Y(n453) );
AO22XLTS U950 ( .A0(d_ff_Yn[6]), .A1(n1199), .B0(d_ff2_Y[6]), .B1(n1004),
.Y(n451) );
AO22XLTS U951 ( .A0(d_ff_Yn[7]), .A1(n1007), .B0(d_ff2_Y[7]), .B1(n1172),
.Y(n449) );
AO22XLTS U952 ( .A0(d_ff_Yn[8]), .A1(n1132), .B0(d_ff2_Y[8]), .B1(n1130),
.Y(n447) );
AO22XLTS U953 ( .A0(d_ff_Yn[9]), .A1(n1161), .B0(d_ff2_Y[9]), .B1(n1198),
.Y(n445) );
AO22XLTS U954 ( .A0(d_ff_Yn[10]), .A1(n1161), .B0(d_ff2_Y[10]), .B1(n1128),
.Y(n443) );
AO22XLTS U955 ( .A0(d_ff_Yn[11]), .A1(n1132), .B0(d_ff2_Y[11]), .B1(n1004),
.Y(n441) );
AO22XLTS U956 ( .A0(d_ff_Yn[12]), .A1(n1132), .B0(d_ff2_Y[12]), .B1(n1172),
.Y(n439) );
AO22XLTS U957 ( .A0(d_ff_Yn[13]), .A1(n1132), .B0(d_ff2_Y[13]), .B1(n1128),
.Y(n437) );
AO22XLTS U958 ( .A0(d_ff_Yn[14]), .A1(n1132), .B0(d_ff2_Y[14]), .B1(n1004),
.Y(n435) );
AO22XLTS U959 ( .A0(d_ff_Yn[15]), .A1(n1132), .B0(d_ff2_Y[15]), .B1(n1172),
.Y(n433) );
AO22XLTS U960 ( .A0(d_ff_Yn[16]), .A1(n1132), .B0(d_ff2_Y[16]), .B1(n1164),
.Y(n431) );
AO22XLTS U961 ( .A0(d_ff_Yn[17]), .A1(n1132), .B0(d_ff2_Y[17]), .B1(n1130),
.Y(n429) );
AO22XLTS U962 ( .A0(d_ff_Yn[18]), .A1(n1132), .B0(d_ff2_Y[18]), .B1(n1198),
.Y(n427) );
AO22XLTS U963 ( .A0(d_ff_Yn[19]), .A1(n1173), .B0(d_ff2_Y[19]), .B1(n1128),
.Y(n425) );
AO22XLTS U964 ( .A0(d_ff_Yn[20]), .A1(n1173), .B0(d_ff2_Y[20]), .B1(n1004),
.Y(n423) );
AO22XLTS U965 ( .A0(d_ff_Yn[21]), .A1(n1161), .B0(d_ff2_Y[21]), .B1(n1172),
.Y(n421) );
AO22XLTS U966 ( .A0(d_ff_Yn[22]), .A1(n1161), .B0(d_ff2_Y[22]), .B1(n1164),
.Y(n419) );
AO22XLTS U967 ( .A0(d_ff_Yn[31]), .A1(n1161), .B0(d_ff2_Y[31]), .B1(n1128),
.Y(n401) );
NAND3XLTS U968 ( .A(n836), .B(sel_mux_1_reg), .C(n1280), .Y(n835) );
NAND3XLTS U969 ( .A(cordic_FSM_state_reg[0]), .B(n1040), .C(n1206), .Y(n836)
);
NAND3XLTS U970 ( .A(n833), .B(sel_mux_3_reg), .C(n1280), .Y(n832) );
NAND3XLTS U971 ( .A(n1040), .B(cordic_FSM_state_reg[3]), .C(n1213), .Y(n833)
);
AO22XLTS U972 ( .A0(d_ff_Yn[25]), .A1(n1161), .B0(d_ff2_Y[25]), .B1(n1130),
.Y(n415) );
AO22XLTS U973 ( .A0(d_ff_Yn[26]), .A1(n1161), .B0(d_ff2_Y[26]), .B1(n1198),
.Y(n414) );
AO22XLTS U974 ( .A0(n1058), .A1(data_in[0]), .B0(n1057), .B1(d_ff1_Z[0]),
.Y(n720) );
AO22XLTS U975 ( .A0(n1057), .A1(d_ff1_shift_region_flag_out[1]), .B0(n1060),
.B1(shift_region_flag[1]), .Y(n721) );
AO22XLTS U976 ( .A0(n1057), .A1(d_ff1_shift_region_flag_out[0]), .B0(n1060),
.B1(shift_region_flag[0]), .Y(n722) );
NAND2BXLTS U977 ( .AN(d_ff3_LUT_out[27]), .B(n1177), .Y(n497) );
AO22XLTS U978 ( .A0(n1098), .A1(n827), .B0(n1097), .B1(data_output[31]), .Y(
n525) );
AO22XLTS U979 ( .A0(n1098), .A1(sign_inv_out[30]), .B0(n1097), .B1(
data_output[30]), .Y(n527) );
AO22XLTS U980 ( .A0(n1096), .A1(sign_inv_out[29]), .B0(n1097), .B1(
data_output[29]), .Y(n529) );
AO22XLTS U981 ( .A0(n1096), .A1(sign_inv_out[28]), .B0(n1097), .B1(
data_output[28]), .Y(n531) );
AO22XLTS U982 ( .A0(n1096), .A1(sign_inv_out[27]), .B0(n1097), .B1(
data_output[27]), .Y(n533) );
AO22XLTS U983 ( .A0(n1096), .A1(sign_inv_out[26]), .B0(n1097), .B1(
data_output[26]), .Y(n535) );
AO22XLTS U984 ( .A0(n1096), .A1(sign_inv_out[25]), .B0(n1097), .B1(
data_output[25]), .Y(n537) );
AO22XLTS U985 ( .A0(n1096), .A1(sign_inv_out[24]), .B0(n1095), .B1(
data_output[24]), .Y(n539) );
AO22XLTS U986 ( .A0(n1096), .A1(sign_inv_out[23]), .B0(n1095), .B1(
data_output[23]), .Y(n541) );
AO22XLTS U987 ( .A0(n1096), .A1(sign_inv_out[22]), .B0(n1094), .B1(
data_output[22]), .Y(n543) );
AO22XLTS U988 ( .A0(n1096), .A1(sign_inv_out[21]), .B0(n1093), .B1(
data_output[21]), .Y(n545) );
AO22XLTS U989 ( .A0(n1096), .A1(sign_inv_out[20]), .B0(n1092), .B1(
data_output[20]), .Y(n547) );
AO22XLTS U990 ( .A0(n1091), .A1(sign_inv_out[19]), .B0(n1093), .B1(
data_output[19]), .Y(n549) );
AO22XLTS U991 ( .A0(n1091), .A1(sign_inv_out[18]), .B0(n1093), .B1(
data_output[18]), .Y(n551) );
AO22XLTS U992 ( .A0(n1091), .A1(sign_inv_out[17]), .B0(n1092), .B1(
data_output[17]), .Y(n553) );
AO22XLTS U993 ( .A0(n1091), .A1(sign_inv_out[16]), .B0(n1092), .B1(
data_output[16]), .Y(n555) );
AO22XLTS U994 ( .A0(n1091), .A1(sign_inv_out[15]), .B0(n1092), .B1(
data_output[15]), .Y(n557) );
AO22XLTS U995 ( .A0(n1091), .A1(sign_inv_out[14]), .B0(n1092), .B1(
data_output[14]), .Y(n559) );
AO22XLTS U996 ( .A0(n1091), .A1(sign_inv_out[13]), .B0(n1092), .B1(
data_output[13]), .Y(n561) );
AO22XLTS U997 ( .A0(n1091), .A1(sign_inv_out[12]), .B0(n1092), .B1(
data_output[12]), .Y(n563) );
AO22XLTS U998 ( .A0(n1091), .A1(sign_inv_out[11]), .B0(n1092), .B1(
data_output[11]), .Y(n565) );
AO22XLTS U999 ( .A0(n1091), .A1(sign_inv_out[10]), .B0(n1093), .B1(
data_output[10]), .Y(n567) );
AO22XLTS U1000 ( .A0(n1090), .A1(sign_inv_out[9]), .B0(n1093), .B1(
data_output[9]), .Y(n569) );
AO22XLTS U1001 ( .A0(n1090), .A1(sign_inv_out[8]), .B0(n1094), .B1(
data_output[8]), .Y(n571) );
AO22XLTS U1002 ( .A0(n1090), .A1(sign_inv_out[7]), .B0(n1095), .B1(
data_output[7]), .Y(n573) );
AO22XLTS U1003 ( .A0(n1090), .A1(sign_inv_out[6]), .B0(n1095), .B1(
data_output[6]), .Y(n575) );
AO22XLTS U1004 ( .A0(n1090), .A1(sign_inv_out[5]), .B0(n1095), .B1(
data_output[5]), .Y(n577) );
AO22XLTS U1005 ( .A0(n1090), .A1(sign_inv_out[4]), .B0(n1095), .B1(
data_output[4]), .Y(n579) );
AO22XLTS U1006 ( .A0(n1090), .A1(sign_inv_out[3]), .B0(n1095), .B1(
data_output[3]), .Y(n581) );
AO22XLTS U1007 ( .A0(n1090), .A1(sign_inv_out[2]), .B0(n1095), .B1(
data_output[2]), .Y(n583) );
AO22XLTS U1008 ( .A0(n1090), .A1(sign_inv_out[1]), .B0(n1095), .B1(
data_output[1]), .Y(n585) );
AO22XLTS U1009 ( .A0(n1090), .A1(sign_inv_out[0]), .B0(n1094), .B1(
data_output[0]), .Y(n587) );
NOR3BXLTS U1010 ( .AN(n1051), .B(n1133), .C(n1050), .Y(n724) );
NAND4XLTS U1011 ( .A(n1043), .B(n1046), .C(n1042), .D(n1041), .Y(n730) );
AOI32X1TS U1012 ( .A0(n1038), .A1(n1202), .A2(n1037), .B0(n1036), .B1(
cordic_FSM_state_reg[2]), .Y(n1043) );
AO22XLTS U1013 ( .A0(n1201), .A1(d_ff2_X[31]), .B0(n1200), .B1(
d_ff3_sh_x_out[31]), .Y(n336) );
AO22XLTS U1014 ( .A0(n1197), .A1(d_ff2_X[22]), .B0(n1166), .B1(
d_ff3_sh_x_out[22]), .Y(n354) );
AO22XLTS U1015 ( .A0(n1179), .A1(d_ff2_X[21]), .B0(n1166), .B1(
d_ff3_sh_x_out[21]), .Y(n356) );
AO22XLTS U1016 ( .A0(n1165), .A1(d_ff2_X[20]), .B0(n1111), .B1(
d_ff3_sh_x_out[20]), .Y(n358) );
AO22XLTS U1017 ( .A0(n1165), .A1(d_ff2_X[19]), .B0(n1111), .B1(
d_ff3_sh_x_out[19]), .Y(n360) );
AO22XLTS U1018 ( .A0(n1165), .A1(d_ff2_X[18]), .B0(n1166), .B1(
d_ff3_sh_x_out[18]), .Y(n362) );
AO22XLTS U1019 ( .A0(n1179), .A1(d_ff2_X[17]), .B0(n820), .B1(
d_ff3_sh_x_out[17]), .Y(n364) );
AO22XLTS U1020 ( .A0(n1185), .A1(d_ff2_X[16]), .B0(n1191), .B1(
d_ff3_sh_x_out[16]), .Y(n366) );
AO22XLTS U1021 ( .A0(n1165), .A1(d_ff2_X[15]), .B0(n1166), .B1(
d_ff3_sh_x_out[15]), .Y(n368) );
AO22XLTS U1022 ( .A0(n1165), .A1(d_ff2_X[14]), .B0(n1111), .B1(
d_ff3_sh_x_out[14]), .Y(n370) );
AO22XLTS U1023 ( .A0(n1165), .A1(d_ff2_X[13]), .B0(n1111), .B1(
d_ff3_sh_x_out[13]), .Y(n372) );
AO22XLTS U1024 ( .A0(n1179), .A1(d_ff2_X[12]), .B0(n1163), .B1(
d_ff3_sh_x_out[12]), .Y(n374) );
AO22XLTS U1025 ( .A0(n1165), .A1(d_ff2_X[11]), .B0(n1163), .B1(
d_ff3_sh_x_out[11]), .Y(n376) );
AO22XLTS U1026 ( .A0(n1201), .A1(d_ff2_X[10]), .B0(n1163), .B1(
d_ff3_sh_x_out[10]), .Y(n378) );
AO22XLTS U1027 ( .A0(n1179), .A1(d_ff2_X[9]), .B0(n1163), .B1(
d_ff3_sh_x_out[9]), .Y(n380) );
AO22XLTS U1028 ( .A0(n1179), .A1(d_ff2_X[8]), .B0(n1163), .B1(
d_ff3_sh_x_out[8]), .Y(n382) );
AO22XLTS U1029 ( .A0(n1179), .A1(d_ff2_X[7]), .B0(n1163), .B1(
d_ff3_sh_x_out[7]), .Y(n384) );
AO22XLTS U1030 ( .A0(n1179), .A1(d_ff2_X[6]), .B0(n1163), .B1(
d_ff3_sh_x_out[6]), .Y(n386) );
AO22XLTS U1031 ( .A0(n1165), .A1(d_ff2_X[5]), .B0(n1163), .B1(
d_ff3_sh_x_out[5]), .Y(n388) );
AO22XLTS U1032 ( .A0(n1179), .A1(d_ff2_X[4]), .B0(n1163), .B1(
d_ff3_sh_x_out[4]), .Y(n390) );
AO22XLTS U1033 ( .A0(n1179), .A1(d_ff2_X[3]), .B0(n1163), .B1(
d_ff3_sh_x_out[3]), .Y(n392) );
AO22XLTS U1034 ( .A0(n1165), .A1(d_ff2_X[2]), .B0(n1160), .B1(
d_ff3_sh_x_out[2]), .Y(n394) );
AO22XLTS U1035 ( .A0(n1165), .A1(d_ff2_X[1]), .B0(n1160), .B1(
d_ff3_sh_x_out[1]), .Y(n396) );
AO22XLTS U1036 ( .A0(n1158), .A1(d_ff2_X[0]), .B0(n1160), .B1(
d_ff3_sh_x_out[0]), .Y(n398) );
AO22XLTS U1037 ( .A0(n1158), .A1(d_ff2_Y[31]), .B0(n1160), .B1(
d_ff3_sh_y_out[31]), .Y(n400) );
AO22XLTS U1038 ( .A0(n1201), .A1(d_ff2_Y[12]), .B0(n1131), .B1(
d_ff3_sh_y_out[12]), .Y(n438) );
AO22XLTS U1039 ( .A0(n1197), .A1(d_ff2_Y[6]), .B0(n1131), .B1(
d_ff3_sh_y_out[6]), .Y(n450) );
AO22XLTS U1040 ( .A0(n1197), .A1(d_ff2_Y[2]), .B0(n1129), .B1(
d_ff3_sh_y_out[2]), .Y(n458) );
AO22XLTS U1041 ( .A0(n1197), .A1(d_ff2_Y[1]), .B0(n1129), .B1(
d_ff3_sh_y_out[1]), .Y(n460) );
AO22XLTS U1042 ( .A0(n1201), .A1(d_ff2_Y[0]), .B0(n1129), .B1(
d_ff3_sh_y_out[0]), .Y(n462) );
AO22XLTS U1043 ( .A0(n1166), .A1(d_ff3_sign_out), .B0(n1185), .B1(
d_ff2_Z[31]), .Y(n464) );
AO22XLTS U1044 ( .A0(n1197), .A1(n1196), .B0(n1195), .B1(d_ff3_sh_x_out[30]),
.Y(n338) );
AOI2BB2XLTS U1045 ( .B0(n1187), .B1(n1186), .A0N(d_ff3_sh_x_out[27]), .A1N(
n1185), .Y(n341) );
AO22XLTS U1046 ( .A0(n1197), .A1(n1182), .B0(n1191), .B1(d_ff3_sh_x_out[26]),
.Y(n342) );
AO21XLTS U1047 ( .A0(d_ff3_sh_x_out[25]), .A1(n1129), .B0(n824), .Y(n343) );
AO22XLTS U1048 ( .A0(n1179), .A1(n1178), .B0(n1177), .B1(d_ff3_sh_x_out[24]),
.Y(n344) );
OAI21XLTS U1049 ( .A0(n1214), .A1(n1124), .B0(n831), .Y(n345) );
AO22XLTS U1050 ( .A0(n1158), .A1(n1157), .B0(n1160), .B1(d_ff3_sh_y_out[30]),
.Y(n402) );
AOI2BB2XLTS U1051 ( .B0(n1133), .B1(n1155), .A0N(d_ff3_sh_y_out[29]), .A1N(
n1185), .Y(n403) );
AO22XLTS U1052 ( .A0(n1158), .A1(n1153), .B0(n1160), .B1(d_ff3_sh_y_out[28]),
.Y(n404) );
OAI21XLTS U1053 ( .A0(n1152), .A1(n1151), .B0(n1154), .Y(n1153) );
AOI2BB2XLTS U1054 ( .B0(n1133), .B1(n1149), .A0N(d_ff3_sh_y_out[27]), .A1N(
n1185), .Y(n405) );
AO22XLTS U1055 ( .A0(n1158), .A1(n1145), .B0(n1160), .B1(d_ff3_sh_y_out[25]),
.Y(n407) );
AO22XLTS U1056 ( .A0(n1158), .A1(n1142), .B0(n1160), .B1(d_ff3_sh_y_out[24]),
.Y(n408) );
OAI21XLTS U1057 ( .A0(n1124), .A1(n801), .B0(n830), .Y(n409) );
AOI2BB1XLTS U1058 ( .A0N(n1133), .A1N(d_ff3_LUT_out[26]), .B0(n1127), .Y(
n498) );
OAI21XLTS U1059 ( .A0(n1099), .A1(n873), .B0(n864), .Y(n499) );
OAI21XLTS U1060 ( .A0(n1110), .A1(n1122), .B0(n874), .Y(n501) );
AOI2BB2XLTS U1061 ( .B0(n1117), .B1(n1116), .A0N(n1187), .A1N(
d_ff3_LUT_out[21]), .Y(n503) );
AO21XLTS U1062 ( .A0(d_ff3_LUT_out[18]), .A1(n1129), .B0(n1113), .Y(n506) );
AO21XLTS U1063 ( .A0(d_ff3_LUT_out[14]), .A1(n1129), .B0(n822), .Y(n510) );
AO21XLTS U1064 ( .A0(d_ff3_LUT_out[13]), .A1(n1129), .B0(n1113), .Y(n511) );
AOI2BB2XLTS U1065 ( .B0(n1117), .B1(n1107), .A0N(n1187), .A1N(
d_ff3_LUT_out[9]), .Y(n515) );
OAI21XLTS U1066 ( .A0(n1181), .A1(n1106), .B0(n1114), .Y(n1107) );
AO21XLTS U1067 ( .A0(d_ff3_LUT_out[8]), .A1(n1129), .B0(n863), .Y(n516) );
AO21XLTS U1068 ( .A0(d_ff3_LUT_out[7]), .A1(n1129), .B0(n821), .Y(n517) );
AO21XLTS U1069 ( .A0(d_ff3_LUT_out[5]), .A1(n1119), .B0(n822), .Y(n519) );
OAI21XLTS U1070 ( .A0(n867), .A1(n873), .B0(n866), .Y(n522) );
OAI21XLTS U1071 ( .A0(n1140), .A1(n886), .B0(n862), .Y(n528) );
OAI21XLTS U1072 ( .A0(n1139), .A1(n919), .B0(n914), .Y(n530) );
OAI21XLTS U1073 ( .A0(n1138), .A1(n919), .B0(n913), .Y(n532) );
OAI21XLTS U1074 ( .A0(n1136), .A1(n919), .B0(n918), .Y(n534) );
OAI21XLTS U1075 ( .A0(n1239), .A1(n919), .B0(n892), .Y(n536) );
OAI21XLTS U1076 ( .A0(n1238), .A1(n919), .B0(n911), .Y(n538) );
OAI21XLTS U1077 ( .A0(n1135), .A1(n919), .B0(n915), .Y(n540) );
OAI21XLTS U1078 ( .A0(n1134), .A1(n919), .B0(n912), .Y(n542) );
OAI21XLTS U1079 ( .A0(n1237), .A1(n919), .B0(n887), .Y(n544) );
OAI21XLTS U1080 ( .A0(n1236), .A1(n919), .B0(n888), .Y(n546) );
OAI21XLTS U1081 ( .A0(n1235), .A1(n919), .B0(n891), .Y(n548) );
OAI21XLTS U1082 ( .A0(n1233), .A1(n906), .B0(n885), .Y(n552) );
OAI21XLTS U1083 ( .A0(n1232), .A1(n906), .B0(n893), .Y(n554) );
OAI21XLTS U1084 ( .A0(n1231), .A1(n906), .B0(n894), .Y(n556) );
OAI21XLTS U1085 ( .A0(n1230), .A1(n906), .B0(n889), .Y(n558) );
OAI21XLTS U1086 ( .A0(n1229), .A1(n906), .B0(n899), .Y(n560) );
OAI21XLTS U1087 ( .A0(n1228), .A1(n906), .B0(n895), .Y(n562) );
OAI21XLTS U1088 ( .A0(n1227), .A1(n906), .B0(n897), .Y(n564) );
OAI21XLTS U1089 ( .A0(n1226), .A1(n906), .B0(n879), .Y(n566) );
OAI21XLTS U1090 ( .A0(n1225), .A1(n906), .B0(n905), .Y(n568) );
OAI21XLTS U1091 ( .A0(n1224), .A1(n910), .B0(n883), .Y(n570) );
OAI21XLTS U1092 ( .A0(n1223), .A1(n910), .B0(n882), .Y(n572) );
OAI21XLTS U1093 ( .A0(n1222), .A1(n910), .B0(n896), .Y(n574) );
OAI21XLTS U1094 ( .A0(n1220), .A1(n910), .B0(n902), .Y(n578) );
OAI21XLTS U1095 ( .A0(n1219), .A1(n910), .B0(n880), .Y(n580) );
OAI21XLTS U1096 ( .A0(n1218), .A1(n910), .B0(n909), .Y(n582) );
OAI21XLTS U1097 ( .A0(n1217), .A1(n910), .B0(n903), .Y(n584) );
OAI21XLTS U1098 ( .A0(n1216), .A1(n910), .B0(n901), .Y(n586) );
OAI21XLTS U1099 ( .A0(n1215), .A1(n910), .B0(n881), .Y(n588) );
AO22XLTS U1100 ( .A0(n1070), .A1(result_add_subt[31]), .B0(n1067), .B1(
d_ff_Zn[31]), .Y(n653) );
AO22XLTS U1101 ( .A0(n1070), .A1(result_add_subt[30]), .B0(n1069), .B1(
d_ff_Zn[30]), .Y(n654) );
AO22XLTS U1102 ( .A0(n1068), .A1(result_add_subt[29]), .B0(n1069), .B1(
d_ff_Zn[29]), .Y(n655) );
AO22XLTS U1103 ( .A0(n1068), .A1(result_add_subt[28]), .B0(n1069), .B1(
d_ff_Zn[28]), .Y(n656) );
AO22XLTS U1104 ( .A0(n1068), .A1(result_add_subt[27]), .B0(n1069), .B1(
d_ff_Zn[27]), .Y(n657) );
AO22XLTS U1105 ( .A0(n1068), .A1(result_add_subt[26]), .B0(n1069), .B1(
d_ff_Zn[26]), .Y(n658) );
AO22XLTS U1106 ( .A0(n1068), .A1(result_add_subt[25]), .B0(n1067), .B1(
d_ff_Zn[25]), .Y(n659) );
AO22XLTS U1107 ( .A0(n1068), .A1(result_add_subt[24]), .B0(n1067), .B1(
d_ff_Zn[24]), .Y(n660) );
AO22XLTS U1108 ( .A0(n1068), .A1(result_add_subt[23]), .B0(n1067), .B1(
d_ff_Zn[23]), .Y(n661) );
AO22XLTS U1109 ( .A0(n1068), .A1(result_add_subt[22]), .B0(n1067), .B1(
d_ff_Zn[22]), .Y(n662) );
AO22XLTS U1110 ( .A0(n1068), .A1(result_add_subt[21]), .B0(n1067), .B1(
d_ff_Zn[21]), .Y(n663) );
AO22XLTS U1111 ( .A0(n1068), .A1(result_add_subt[20]), .B0(n1067), .B1(
d_ff_Zn[20]), .Y(n664) );
AO22XLTS U1112 ( .A0(n1066), .A1(result_add_subt[19]), .B0(n1069), .B1(
d_ff_Zn[19]), .Y(n665) );
AO22XLTS U1113 ( .A0(n1066), .A1(result_add_subt[18]), .B0(n1069), .B1(
d_ff_Zn[18]), .Y(n666) );
AO22XLTS U1114 ( .A0(n1066), .A1(result_add_subt[17]), .B0(n1065), .B1(
d_ff_Zn[17]), .Y(n667) );
AO22XLTS U1115 ( .A0(n1066), .A1(result_add_subt[16]), .B0(n1065), .B1(
d_ff_Zn[16]), .Y(n668) );
AO22XLTS U1116 ( .A0(n1066), .A1(result_add_subt[15]), .B0(n1065), .B1(
d_ff_Zn[15]), .Y(n669) );
AO22XLTS U1117 ( .A0(n1066), .A1(result_add_subt[14]), .B0(n1065), .B1(
d_ff_Zn[14]), .Y(n670) );
AO22XLTS U1118 ( .A0(n1066), .A1(result_add_subt[13]), .B0(n1065), .B1(
d_ff_Zn[13]), .Y(n671) );
AO22XLTS U1119 ( .A0(n1066), .A1(result_add_subt[12]), .B0(n1065), .B1(
d_ff_Zn[12]), .Y(n672) );
AO22XLTS U1120 ( .A0(n1066), .A1(result_add_subt[11]), .B0(n1065), .B1(
d_ff_Zn[11]), .Y(n673) );
AO22XLTS U1121 ( .A0(n1066), .A1(result_add_subt[10]), .B0(n1065), .B1(
d_ff_Zn[10]), .Y(n674) );
AO22XLTS U1122 ( .A0(n1064), .A1(result_add_subt[9]), .B0(n1065), .B1(
d_ff_Zn[9]), .Y(n675) );
AO22XLTS U1123 ( .A0(n1064), .A1(result_add_subt[8]), .B0(n1065), .B1(
d_ff_Zn[8]), .Y(n676) );
AO22XLTS U1124 ( .A0(n1064), .A1(result_add_subt[7]), .B0(n1063), .B1(
d_ff_Zn[7]), .Y(n677) );
AO22XLTS U1125 ( .A0(n1064), .A1(result_add_subt[6]), .B0(n1063), .B1(
d_ff_Zn[6]), .Y(n678) );
AO22XLTS U1126 ( .A0(n1064), .A1(result_add_subt[5]), .B0(n1063), .B1(
d_ff_Zn[5]), .Y(n679) );
AO22XLTS U1127 ( .A0(n1064), .A1(result_add_subt[4]), .B0(n1063), .B1(
d_ff_Zn[4]), .Y(n680) );
AO22XLTS U1128 ( .A0(n1064), .A1(result_add_subt[3]), .B0(n1063), .B1(
d_ff_Zn[3]), .Y(n681) );
AO22XLTS U1129 ( .A0(n1064), .A1(result_add_subt[2]), .B0(n1063), .B1(
d_ff_Zn[2]), .Y(n682) );
AO22XLTS U1130 ( .A0(n1064), .A1(result_add_subt[1]), .B0(n1063), .B1(
d_ff_Zn[1]), .Y(n683) );
AO22XLTS U1131 ( .A0(n1064), .A1(result_add_subt[0]), .B0(n1063), .B1(
d_ff_Zn[0]), .Y(n684) );
AO22XLTS U1132 ( .A0(n1060), .A1(data_in[31]), .B0(n1059), .B1(d_ff1_Z[31]),
.Y(n689) );
AO22XLTS U1133 ( .A0(n1058), .A1(data_in[30]), .B0(n1057), .B1(d_ff1_Z[30]),
.Y(n690) );
AO22XLTS U1134 ( .A0(n1060), .A1(data_in[29]), .B0(n1056), .B1(d_ff1_Z[29]),
.Y(n691) );
AO22XLTS U1135 ( .A0(n1058), .A1(data_in[28]), .B0(n1056), .B1(d_ff1_Z[28]),
.Y(n692) );
AO22XLTS U1136 ( .A0(n1060), .A1(data_in[27]), .B0(n1056), .B1(d_ff1_Z[27]),
.Y(n693) );
AO22XLTS U1137 ( .A0(n1060), .A1(data_in[26]), .B0(n1056), .B1(d_ff1_Z[26]),
.Y(n694) );
AO22XLTS U1138 ( .A0(n1060), .A1(data_in[25]), .B0(n1056), .B1(d_ff1_Z[25]),
.Y(n695) );
AO22XLTS U1139 ( .A0(n1060), .A1(data_in[24]), .B0(n1056), .B1(d_ff1_Z[24]),
.Y(n696) );
AO22XLTS U1140 ( .A0(n1060), .A1(data_in[23]), .B0(n1056), .B1(d_ff1_Z[23]),
.Y(n697) );
AO22XLTS U1141 ( .A0(n1055), .A1(data_in[22]), .B0(n1056), .B1(d_ff1_Z[22]),
.Y(n698) );
AO22XLTS U1142 ( .A0(n1054), .A1(data_in[21]), .B0(n1056), .B1(d_ff1_Z[21]),
.Y(n699) );
AO22XLTS U1143 ( .A0(n1054), .A1(data_in[20]), .B0(n1056), .B1(d_ff1_Z[20]),
.Y(n700) );
AO22XLTS U1144 ( .A0(n1054), .A1(data_in[19]), .B0(n1059), .B1(d_ff1_Z[19]),
.Y(n701) );
AO22XLTS U1145 ( .A0(n1054), .A1(data_in[18]), .B0(n1059), .B1(d_ff1_Z[18]),
.Y(n702) );
AO22XLTS U1146 ( .A0(n1054), .A1(data_in[17]), .B0(n1059), .B1(d_ff1_Z[17]),
.Y(n703) );
AO22XLTS U1147 ( .A0(n1053), .A1(data_in[16]), .B0(n1059), .B1(d_ff1_Z[16]),
.Y(n704) );
AO22XLTS U1148 ( .A0(n1054), .A1(data_in[15]), .B0(n1059), .B1(d_ff1_Z[15]),
.Y(n705) );
AO22XLTS U1149 ( .A0(n1054), .A1(data_in[14]), .B0(n1059), .B1(d_ff1_Z[14]),
.Y(n706) );
AO22XLTS U1150 ( .A0(n1053), .A1(data_in[13]), .B0(n1059), .B1(d_ff1_Z[13]),
.Y(n707) );
AO22XLTS U1151 ( .A0(n1055), .A1(data_in[12]), .B0(n1059), .B1(d_ff1_Z[12]),
.Y(n708) );
AO22XLTS U1152 ( .A0(n1058), .A1(data_in[11]), .B0(n1059), .B1(d_ff1_Z[11]),
.Y(n709) );
AO22XLTS U1153 ( .A0(n1058), .A1(data_in[10]), .B0(n1052), .B1(d_ff1_Z[10]),
.Y(n710) );
AO22XLTS U1154 ( .A0(n1058), .A1(data_in[9]), .B0(n1052), .B1(d_ff1_Z[9]),
.Y(n711) );
AO22XLTS U1155 ( .A0(n1058), .A1(data_in[8]), .B0(n1052), .B1(d_ff1_Z[8]),
.Y(n712) );
AO22XLTS U1156 ( .A0(n1058), .A1(data_in[7]), .B0(n1052), .B1(d_ff1_Z[7]),
.Y(n713) );
AO22XLTS U1157 ( .A0(n1058), .A1(data_in[6]), .B0(n1052), .B1(d_ff1_Z[6]),
.Y(n714) );
AO22XLTS U1158 ( .A0(n1053), .A1(data_in[5]), .B0(n1052), .B1(d_ff1_Z[5]),
.Y(n715) );
AO22XLTS U1159 ( .A0(n1053), .A1(data_in[4]), .B0(n1052), .B1(d_ff1_Z[4]),
.Y(n716) );
AO22XLTS U1160 ( .A0(n1053), .A1(data_in[3]), .B0(n1052), .B1(d_ff1_Z[3]),
.Y(n717) );
AO22XLTS U1161 ( .A0(n1054), .A1(data_in[2]), .B0(n1052), .B1(d_ff1_Z[2]),
.Y(n718) );
AO22XLTS U1162 ( .A0(n1054), .A1(data_in[1]), .B0(n1052), .B1(d_ff1_Z[1]),
.Y(n719) );
BUFX3TS U1163 ( .A(n818), .Y(n814) );
BUFX3TS U1164 ( .A(n815), .Y(n813) );
INVX2TS U1165 ( .A(cordic_FSM_state_reg[3]), .Y(n803) );
INVX2TS U1166 ( .A(n1181), .Y(n804) );
INVX2TS U1167 ( .A(n804), .Y(n805) );
AOI222X1TS U1168 ( .A0(d_ff2_Z[22]), .A1(n960), .B0(d_ff2_Y[22]), .B1(n974),
.C0(d_ff2_X[22]), .C1(n965), .Y(n961) );
AOI222X1TS U1169 ( .A0(d_ff2_Z[21]), .A1(n975), .B0(d_ff2_Y[21]), .B1(n971),
.C0(d_ff2_X[21]), .C1(n965), .Y(n959) );
OAI21XLTS U1170 ( .A0(n1240), .A1(n886), .B0(n861), .Y(n526) );
OAI32X1TS U1171 ( .A0(n1020), .A1(n1019), .A2(n1205), .B0(n1018), .B1(n1017),
.Y(n686) );
NOR4X1TS U1172 ( .A(cordic_FSM_state_reg[1]), .B(n1202), .C(n1213), .D(n1206), .Y(ready_cordic) );
OAI31X1TS U1173 ( .A0(n1040), .A1(n1039), .A2(n1206), .B0(n1213), .Y(n1041)
);
NOR2X2TS U1174 ( .A(cordic_FSM_state_reg[1]), .B(cordic_FSM_state_reg[3]),
.Y(n1038) );
NOR2X2TS U1175 ( .A(cordic_FSM_state_reg[0]), .B(cordic_FSM_state_reg[3]),
.Y(n1031) );
AOI222X4TS U1176 ( .A0(n1130), .A1(d_ff2_Z[20]), .B0(n1012), .B1(d_ff1_Z[20]), .C0(d_ff_Zn[20]), .C1(n1011), .Y(n977) );
AOI222X4TS U1177 ( .A0(n1172), .A1(d_ff2_Z[30]), .B0(n1009), .B1(d_ff1_Z[30]), .C0(d_ff_Zn[30]), .C1(n1011), .Y(n989) );
AOI222X4TS U1178 ( .A0(n1164), .A1(d_ff2_Z[18]), .B0(n1012), .B1(d_ff1_Z[18]), .C0(d_ff_Zn[18]), .C1(n1011), .Y(n994) );
AOI222X4TS U1179 ( .A0(n1004), .A1(d_ff2_Z[26]), .B0(n1009), .B1(d_ff1_Z[26]), .C0(d_ff_Zn[26]), .C1(n1011), .Y(n995) );
CLKINVX3TS U1180 ( .A(n1159), .Y(n1003) );
CLKINVX3TS U1181 ( .A(n818), .Y(n1276) );
NOR2X4TS U1182 ( .A(cordic_FSM_state_reg[1]), .B(cordic_FSM_state_reg[0]),
.Y(n1036) );
AOI222X4TS U1183 ( .A0(n1168), .A1(d_ff2_Z[9]), .B0(n990), .B1(d_ff1_Z[9]),
.C0(d_ff_Zn[9]), .C1(n1007), .Y(n988) );
AOI222X4TS U1184 ( .A0(n1168), .A1(d_ff2_Z[7]), .B0(n990), .B1(d_ff1_Z[7]),
.C0(d_ff_Zn[7]), .C1(n1199), .Y(n986) );
AOI222X4TS U1185 ( .A0(n1168), .A1(d_ff2_Z[5]), .B0(n990), .B1(d_ff1_Z[5]),
.C0(d_ff_Zn[5]), .C1(n1003), .Y(n984) );
AOI222X4TS U1186 ( .A0(n1168), .A1(d_ff2_Z[3]), .B0(n990), .B1(d_ff1_Z[3]),
.C0(d_ff_Zn[3]), .C1(n1003), .Y(n982) );
AOI222X4TS U1187 ( .A0(n1168), .A1(d_ff2_Z[8]), .B0(n990), .B1(d_ff1_Z[8]),
.C0(d_ff_Zn[8]), .C1(n1007), .Y(n980) );
AOI222X4TS U1188 ( .A0(n1168), .A1(d_ff2_Z[4]), .B0(n990), .B1(d_ff1_Z[4]),
.C0(d_ff_Zn[4]), .C1(n1003), .Y(n979) );
AOI222X4TS U1189 ( .A0(n1168), .A1(d_ff2_Z[1]), .B0(n871), .B1(d_ff1_Z[1]),
.C0(d_ff_Zn[1]), .C1(n1199), .Y(n875) );
AOI222X4TS U1190 ( .A0(n1164), .A1(d_ff2_Z[0]), .B0(n1011), .B1(d_ff_Zn[0]),
.C0(n871), .C1(d_ff1_Z[0]), .Y(n872) );
AOI222X1TS U1191 ( .A0(d_ff2_Z[31]), .A1(n969), .B0(d_ff2_Y[31]), .B1(n971),
.C0(d_ff2_X[31]), .C1(n973), .Y(n970) );
OAI33X1TS U1192 ( .A0(d_ff1_shift_region_flag_out[1]), .A1(
d_ff1_operation_out), .A2(n1212), .B0(n1207), .B1(n1203), .B2(
d_ff1_shift_region_flag_out[0]), .Y(n826) );
BUFX3TS U1193 ( .A(n812), .Y(n818) );
CLKINVX3TS U1194 ( .A(n813), .Y(n1247) );
CLKINVX3TS U1195 ( .A(n814), .Y(n1267) );
CLKINVX3TS U1196 ( .A(n818), .Y(n1278) );
CLKINVX3TS U1197 ( .A(n818), .Y(n1277) );
CLKINVX3TS U1198 ( .A(n818), .Y(n1279) );
CLKINVX3TS U1199 ( .A(n818), .Y(n1275) );
CLKINVX3TS U1200 ( .A(n813), .Y(n1263) );
CLKINVX3TS U1201 ( .A(n814), .Y(n1266) );
CLKINVX3TS U1202 ( .A(n814), .Y(n1268) );
CLKINVX3TS U1203 ( .A(n814), .Y(n1269) );
CLKINVX3TS U1204 ( .A(n814), .Y(n1271) );
CLKINVX3TS U1205 ( .A(n814), .Y(n1264) );
CLKINVX3TS U1206 ( .A(n814), .Y(n1270) );
CLKINVX3TS U1207 ( .A(n813), .Y(n1244) );
CLKINVX3TS U1208 ( .A(n813), .Y(n1242) );
CLKINVX3TS U1209 ( .A(n813), .Y(n1243) );
CLKINVX3TS U1210 ( .A(n813), .Y(n1246) );
CLKINVX3TS U1211 ( .A(n812), .Y(n1273) );
CLKINVX3TS U1212 ( .A(n1019), .Y(n1241) );
CLKINVX3TS U1213 ( .A(n812), .Y(n1257) );
CLKINVX3TS U1214 ( .A(n812), .Y(n1259) );
CLKINVX3TS U1215 ( .A(n812), .Y(n1262) );
CLKINVX3TS U1216 ( .A(n812), .Y(n1272) );
CLKINVX3TS U1217 ( .A(n818), .Y(n1258) );
CLKINVX3TS U1218 ( .A(n815), .Y(n1249) );
CLKINVX3TS U1219 ( .A(n815), .Y(n1250) );
CLKINVX3TS U1220 ( .A(n815), .Y(n1274) );
INVX2TS U1221 ( .A(n818), .Y(n806) );
CLKINVX3TS U1222 ( .A(n818), .Y(n1256) );
CLKINVX3TS U1223 ( .A(n814), .Y(n1255) );
CLKINVX3TS U1224 ( .A(n814), .Y(n1252) );
CLKINVX3TS U1225 ( .A(n814), .Y(n1253) );
CLKINVX3TS U1226 ( .A(n1019), .Y(n1260) );
CLKINVX3TS U1227 ( .A(n1019), .Y(n1265) );
CLKINVX3TS U1228 ( .A(n1019), .Y(n1245) );
AOI32X4TS U1229 ( .A0(n1110), .A1(n1193), .A2(n1114), .B0(d_ff3_LUT_out[23]),
.B1(n1111), .Y(n874) );
AOI221X4TS U1230 ( .A0(n1121), .A1(n1193), .B0(d_ff3_LUT_out[24]), .B1(n1191), .C0(n1120), .Y(n1123) );
NOR2X2TS U1231 ( .A(d_ff2_Y[23]), .B(n1104), .Y(n1144) );
AOI222X4TS U1232 ( .A0(n1013), .A1(d_ff2_Z[17]), .B0(n1012), .B1(d_ff1_Z[17]), .C0(d_ff_Zn[17]), .C1(n1011), .Y(n1014) );
AOI222X4TS U1233 ( .A0(n1013), .A1(d_ff2_Z[15]), .B0(n1012), .B1(d_ff1_Z[15]), .C0(d_ff_Zn[15]), .C1(n1007), .Y(n1008) );
AOI222X4TS U1234 ( .A0(n1013), .A1(d_ff2_Z[13]), .B0(n1012), .B1(d_ff1_Z[13]), .C0(d_ff_Zn[13]), .C1(n1199), .Y(n1006) );
AOI222X4TS U1235 ( .A0(n1013), .A1(d_ff2_Z[19]), .B0(n1012), .B1(d_ff1_Z[19]), .C0(d_ff_Zn[19]), .C1(n1011), .Y(n999) );
AOI222X4TS U1236 ( .A0(n1013), .A1(d_ff2_Z[16]), .B0(n1012), .B1(d_ff1_Z[16]), .C0(d_ff_Zn[16]), .C1(n1007), .Y(n992) );
AOI222X4TS U1237 ( .A0(n1013), .A1(d_ff2_Z[11]), .B0(n990), .B1(d_ff1_Z[11]),
.C0(d_ff_Zn[11]), .C1(n1199), .Y(n991) );
AOI222X4TS U1238 ( .A0(n1013), .A1(d_ff2_Z[14]), .B0(n1012), .B1(d_ff1_Z[14]), .C0(d_ff_Zn[14]), .C1(n1011), .Y(n987) );
AOI222X4TS U1239 ( .A0(n1013), .A1(d_ff2_Z[12]), .B0(n1012), .B1(d_ff1_Z[12]), .C0(d_ff_Zn[12]), .C1(n1007), .Y(n985) );
AOI222X4TS U1240 ( .A0(n1013), .A1(d_ff2_Z[10]), .B0(n990), .B1(d_ff1_Z[10]),
.C0(d_ff_Zn[10]), .C1(n1011), .Y(n983) );
AOI222X4TS U1241 ( .A0(n1128), .A1(d_ff2_Z[6]), .B0(n990), .B1(d_ff1_Z[6]),
.C0(d_ff_Zn[6]), .C1(n1199), .Y(n978) );
NOR4X4TS U1242 ( .A(cordic_FSM_state_reg[2]), .B(cordic_FSM_state_reg[1]),
.C(n1213), .D(n1206), .Y(ack_add_subt) );
OAI21XLTS U1243 ( .A0(n837), .A1(n836), .B0(n835), .Y(n687) );
NOR2X2TS U1244 ( .A(d_ff2_X[23]), .B(n1104), .Y(n1176) );
OAI21XLTS U1245 ( .A0(n834), .A1(n833), .B0(n832), .Y(n688) );
AOI222X4TS U1246 ( .A0(n1164), .A1(d_ff2_Z[31]), .B0(n1009), .B1(d_ff1_Z[31]), .C0(d_ff_Zn[31]), .C1(n1011), .Y(n1010) );
CLKINVX3TS U1247 ( .A(n1019), .Y(n1261) );
OAI2BB2X2TS U1248 ( .B0(n798), .B1(d_ff2_X[24]), .A0N(n1176), .A1N(n1174),
.Y(n1180) );
OAI21XLTS U1249 ( .A0(d_ff2_X[24]), .A1(n798), .B0(n1174), .Y(n1175) );
BUFX3TS U1250 ( .A(n1024), .Y(n953) );
OR3X2TS U1251 ( .A(n1082), .B(n1081), .C(n1080), .Y(n810) );
BUFX3TS U1252 ( .A(n819), .Y(n1169) );
NOR2X1TS U1253 ( .A(n834), .B(n1049), .Y(n1082) );
NOR2XLTS U1254 ( .A(d_ff2_X[27]), .B(n1188), .Y(n1184) );
OAI21XLTS U1255 ( .A0(d_ff2_X[27]), .A1(n1188), .B0(d_ff2_X[28]), .Y(n1189)
);
INVX2TS U1256 ( .A(d_ff_Yn[28]), .Y(n1138) );
INVX2TS U1257 ( .A(n1062), .Y(n1067) );
CLKBUFX2TS U1258 ( .A(n1054), .Y(n1053) );
OAI21XLTS U1259 ( .A0(n1126), .A1(n1046), .B0(n1057), .Y(n920) );
OAI21XLTS U1260 ( .A0(cont_iter_out[3]), .A1(n873), .B0(n870), .Y(n523) );
OAI21XLTS U1261 ( .A0(n1234), .A1(n906), .B0(n890), .Y(n550) );
OAI21XLTS U1262 ( .A0(n1221), .A1(n910), .B0(n900), .Y(n576) );
OAI21XLTS U1263 ( .A0(n807), .A1(n931), .B0(n847), .Y(add_subt_dataB[28]) );
OAI21XLTS U1264 ( .A0(n801), .A1(n931), .B0(n846), .Y(add_subt_dataA[23]) );
OAI21XLTS U1265 ( .A0(n1151), .A1(n931), .B0(n844), .Y(add_subt_dataA[28])
);
CLKBUFX2TS U1266 ( .A(n812), .Y(n815) );
INVX2TS U1267 ( .A(n818), .Y(n1248) );
INVX2TS U1268 ( .A(n813), .Y(n1251) );
INVX2TS U1269 ( .A(n813), .Y(n1254) );
NAND2X1TS U1270 ( .A(n1205), .B(sel_mux_2_reg[1]), .Y(n841) );
AOI22X1TS U1271 ( .A0(n1027), .A1(d_ff3_sh_x_out[12]), .B0(n1024), .B1(
d_ff3_sh_y_out[12]), .Y(n817) );
OAI21XLTS U1272 ( .A0(n808), .A1(n841), .B0(n817), .Y(add_subt_dataB[12]) );
INVX2TS U1273 ( .A(n815), .Y(n1280) );
AND3X2TS U1274 ( .A(cordic_FSM_state_reg[2]), .B(n1036), .C(n803), .Y(n819)
);
BUFX3TS U1275 ( .A(n819), .Y(n1137) );
BUFX3TS U1276 ( .A(n1159), .Y(n1162) );
OA22X1TS U1277 ( .A0(n1137), .A1(d_ff2_X[27]), .B0(d_ff_Xn[27]), .B1(n1162),
.Y(n349) );
NAND3X1TS U1278 ( .A(cordic_FSM_state_reg[2]), .B(cordic_FSM_state_reg[0]),
.C(n1038), .Y(n820) );
BUFX3TS U1279 ( .A(n820), .Y(n1166) );
BUFX3TS U1280 ( .A(n1166), .Y(n1195) );
BUFX3TS U1281 ( .A(n820), .Y(n1111) );
BUFX3TS U1282 ( .A(n1111), .Y(n1191) );
NAND2X2TS U1283 ( .A(n798), .B(n1204), .Y(n867) );
NOR3X1TS U1284 ( .A(n1110), .B(n1181), .C(n867), .Y(n837) );
NAND2X1TS U1285 ( .A(n1193), .B(n837), .Y(n868) );
NAND2X2TS U1286 ( .A(n805), .B(cont_iter_out[3]), .Y(n1114) );
NAND2X1TS U1287 ( .A(n868), .B(n1115), .Y(n821) );
NOR2X2TS U1288 ( .A(cont_iter_out[3]), .B(n798), .Y(n1105) );
AOI222X1TS U1289 ( .A0(n1105), .A1(n1181), .B0(n1105), .B1(n1104), .C0(
cont_iter_out[3]), .C1(n804), .Y(n1109) );
NAND2X2TS U1290 ( .A(n1193), .B(n804), .Y(n869) );
INVX2TS U1291 ( .A(n869), .Y(n863) );
NAND2X2TS U1292 ( .A(n1181), .B(n1193), .Y(n873) );
NAND2X1TS U1293 ( .A(d_ff2_X[24]), .B(n798), .Y(n1174) );
XOR2X1TS U1294 ( .A(n1180), .B(n800), .Y(n823) );
MXI2X1TS U1295 ( .A(n869), .B(n873), .S0(n823), .Y(n824) );
INVX2TS U1296 ( .A(n1036), .Y(n825) );
OR3X2TS U1297 ( .A(n1202), .B(n803), .C(n825), .Y(n1092) );
CLKBUFX2TS U1298 ( .A(n1092), .Y(n1093) );
CLKBUFX2TS U1299 ( .A(n1093), .Y(n1094) );
INVX2TS U1300 ( .A(n1094), .Y(n1098) );
CLKBUFX2TS U1301 ( .A(n1092), .Y(n1097) );
NAND2X2TS U1302 ( .A(n1110), .B(cont_iter_out[1]), .Y(n1126) );
NOR2X4TS U1303 ( .A(n1126), .B(n1114), .Y(n1078) );
INVX2TS U1304 ( .A(n1078), .Y(n1049) );
XNOR2X1TS U1305 ( .A(d_ff1_shift_region_flag_out[1]), .B(d_ff1_operation_out), .Y(n828) );
XOR2X1TS U1306 ( .A(d_ff1_shift_region_flag_out[0]), .B(n828), .Y(n834) );
AOI21X1TS U1307 ( .A0(cont_var_out[0]), .A1(n1049), .B0(n1082), .Y(n1018) );
NAND4X1TS U1308 ( .A(cordic_FSM_state_reg[3]), .B(n1036), .C(ready_add_subt),
.D(n1202), .Y(n1080) );
NOR2X1TS U1309 ( .A(n1018), .B(n1080), .Y(n829) );
BUFX3TS U1310 ( .A(n829), .Y(n1071) );
BUFX3TS U1311 ( .A(n1071), .Y(n1072) );
BUFX3TS U1312 ( .A(n1072), .Y(n1074) );
OAI2BB2XLTS U1313 ( .B0(n1074), .B1(n1215), .A0N(n1071), .A1N(
result_add_subt[0]), .Y(n652) );
OAI2BB2XLTS U1314 ( .B0(n1072), .B1(n1140), .A0N(n1071), .A1N(
result_add_subt[30]), .Y(n622) );
BUFX3TS U1315 ( .A(n1072), .Y(n1075) );
OAI2BB2XLTS U1316 ( .B0(n1075), .B1(n1240), .A0N(n1071), .A1N(
result_add_subt[31]), .Y(n621) );
BUFX3TS U1317 ( .A(n1072), .Y(n1073) );
OAI2BB2XLTS U1318 ( .B0(n1073), .B1(n1216), .A0N(n1071), .A1N(
result_add_subt[1]), .Y(n651) );
INVX2TS U1319 ( .A(rst), .Y(n331) );
INVX2TS U1320 ( .A(n1015), .Y(beg_add_subt) );
NAND2X1TS U1321 ( .A(n1193), .B(n1104), .Y(n1124) );
BUFX3TS U1322 ( .A(n1166), .Y(n1177) );
AOI22X1TS U1323 ( .A0(n1187), .A1(n1144), .B0(d_ff3_sh_y_out[23]), .B1(n1177), .Y(n830) );
AOI22X1TS U1324 ( .A0(n1187), .A1(n1176), .B0(d_ff3_sh_x_out[23]), .B1(n1177), .Y(n831) );
NAND2X1TS U1325 ( .A(n1202), .B(cordic_FSM_state_reg[1]), .Y(n1035) );
NAND3X1TS U1326 ( .A(cordic_FSM_state_reg[2]), .B(cordic_FSM_state_reg[1]),
.C(n1031), .Y(n1017) );
INVX2TS U1327 ( .A(cont_var_out[1]), .Y(n1079) );
INVX2TS U1328 ( .A(n1017), .Y(n1020) );
NAND2X1TS U1329 ( .A(sel_mux_2_reg[1]), .B(n1280), .Y(n838) );
OAI32X1TS U1330 ( .A0(n1017), .A1(n1078), .A2(n1079), .B0(n1020), .B1(n838),
.Y(n685) );
OAI211XLTS U1331 ( .A0(n1110), .A1(cont_iter_out[3]), .B0(cont_iter_out[1]),
.C0(n804), .Y(n839) );
OAI21X1TS U1332 ( .A0(n1110), .A1(n867), .B0(n839), .Y(n1103) );
AOI22X1TS U1333 ( .A0(n1133), .A1(n1103), .B0(n1111), .B1(d_ff3_LUT_out[6]),
.Y(n840) );
OAI31X1TS U1334 ( .A0(n1104), .A1(n1204), .A2(n869), .B0(n840), .Y(n518) );
BUFX3TS U1335 ( .A(n937), .Y(n1028) );
AOI22X1TS U1336 ( .A0(n1028), .A1(d_ff2_Z[27]), .B0(d_ff2_X[27]), .B1(n1024),
.Y(n842) );
OAI21XLTS U1337 ( .A0(n1209), .A1(n931), .B0(n842), .Y(add_subt_dataA[27])
);
AOI22X1TS U1338 ( .A0(n1028), .A1(d_ff2_Z[30]), .B0(d_ff2_X[30]), .B1(n1024),
.Y(n843) );
OAI21XLTS U1339 ( .A0(n1211), .A1(n931), .B0(n843), .Y(add_subt_dataA[30])
);
AOI22X1TS U1340 ( .A0(d_ff2_Z[28]), .A1(n1028), .B0(d_ff2_X[28]), .B1(n1024),
.Y(n844) );
AOI22X1TS U1341 ( .A0(d_ff2_Z[29]), .A1(n1028), .B0(d_ff2_X[29]), .B1(n1024),
.Y(n845) );
OAI21XLTS U1342 ( .A0(n1210), .A1(n931), .B0(n845), .Y(add_subt_dataA[29])
);
AOI22X1TS U1343 ( .A0(d_ff2_X[23]), .A1(n1024), .B0(d_ff2_Z[23]), .B1(n1028),
.Y(n846) );
AOI22X1TS U1344 ( .A0(d_ff3_sh_y_out[28]), .A1(n953), .B0(d_ff3_LUT_out[27]),
.B1(n1028), .Y(n847) );
AOI22X1TS U1345 ( .A0(d_ff3_sh_y_out[29]), .A1(n953), .B0(d_ff3_LUT_out[27]),
.B1(n1028), .Y(n849) );
OAI21XLTS U1346 ( .A0(n802), .A1(n848), .B0(n849), .Y(add_subt_dataB[29]) );
AOI22X1TS U1347 ( .A0(d_ff2_X[24]), .A1(n1024), .B0(d_ff2_Z[24]), .B1(n1028),
.Y(n850) );
BUFX3TS U1348 ( .A(n937), .Y(n960) );
BUFX3TS U1349 ( .A(n1024), .Y(n876) );
INVX2TS U1350 ( .A(n851), .Y(add_subt_dataA[6]) );
INVX2TS U1351 ( .A(n852), .Y(add_subt_dataA[4]) );
BUFX3TS U1352 ( .A(n937), .Y(n966) );
INVX2TS U1353 ( .A(n853), .Y(add_subt_dataA[8]) );
INVX2TS U1354 ( .A(n854), .Y(add_subt_dataA[9]) );
INVX2TS U1355 ( .A(n855), .Y(add_subt_dataA[7]) );
INVX2TS U1356 ( .A(n856), .Y(add_subt_dataA[11]) );
INVX2TS U1357 ( .A(n848), .Y(n1023) );
INVX2TS U1358 ( .A(n857), .Y(add_subt_dataA[2]) );
INVX2TS U1359 ( .A(n858), .Y(add_subt_dataA[5]) );
INVX2TS U1360 ( .A(n859), .Y(add_subt_dataA[3]) );
BUFX3TS U1361 ( .A(n884), .Y(n916) );
AOI22X1TS U1362 ( .A0(d_ff_Xn[31]), .A1(n860), .B0(data_output2_31_), .B1(
n916), .Y(n861) );
AOI22X1TS U1363 ( .A0(d_ff_Xn[30]), .A1(n860), .B0(sign_inv_out[30]), .B1(
n916), .Y(n862) );
NAND3X1TS U1364 ( .A(cont_iter_out[1]), .B(n1110), .C(n1204), .Y(n1099) );
AOI22X1TS U1365 ( .A0(d_ff3_LUT_out[25]), .A1(n1111), .B0(n863), .B1(n1126),
.Y(n864) );
NOR3X1TS U1366 ( .A(n1078), .B(cont_var_out[0]), .C(n1079), .Y(n1061) );
NAND2X2TS U1367 ( .A(ack_add_subt), .B(n1061), .Y(n1046) );
AND2X2TS U1368 ( .A(n1040), .B(n1031), .Y(n1054) );
BUFX3TS U1369 ( .A(n1053), .Y(n1058) );
INVX2TS U1370 ( .A(n1058), .Y(n1057) );
NAND2X1TS U1371 ( .A(cont_iter_out[3]), .B(n1057), .Y(n865) );
OAI31X1TS U1372 ( .A0(n1046), .A1(n804), .A2(n1099), .B0(n865), .Y(n725) );
NOR2X1TS U1373 ( .A(n1126), .B(n869), .Y(n1120) );
AOI21X1TS U1374 ( .A0(d_ff3_LUT_out[2]), .A1(n1177), .B0(n1120), .Y(n866) );
OAI21X1TS U1375 ( .A0(n869), .A1(n1204), .B0(n868), .Y(n1100) );
AOI21X1TS U1376 ( .A0(d_ff3_LUT_out[1]), .A1(n1177), .B0(n1100), .Y(n870) );
INVX2TS U1377 ( .A(n1137), .Y(n1168) );
INVX2TS U1378 ( .A(n1162), .Y(n1011) );
INVX2TS U1379 ( .A(n872), .Y(n496) );
INVX2TS U1380 ( .A(n873), .Y(n1101) );
NAND2X1TS U1381 ( .A(cont_iter_out[3]), .B(n1101), .Y(n1122) );
INVX2TS U1382 ( .A(n875), .Y(n495) );
INVX2TS U1383 ( .A(n877), .Y(add_subt_dataA[1]) );
INVX2TS U1384 ( .A(n878), .Y(add_subt_dataA[12]) );
BUFX3TS U1385 ( .A(n886), .Y(n906) );
BUFX3TS U1386 ( .A(n860), .Y(n904) );
BUFX3TS U1387 ( .A(n884), .Y(n907) );
AOI22X1TS U1388 ( .A0(d_ff_Xn[11]), .A1(n904), .B0(sign_inv_out[11]), .B1(
n907), .Y(n879) );
BUFX3TS U1389 ( .A(n886), .Y(n910) );
BUFX3TS U1390 ( .A(n860), .Y(n908) );
AOI22X1TS U1391 ( .A0(d_ff_Xn[4]), .A1(n908), .B0(sign_inv_out[4]), .B1(n907), .Y(n880) );
AOI22X1TS U1392 ( .A0(d_ff_Xn[0]), .A1(n908), .B0(sign_inv_out[0]), .B1(n884), .Y(n881) );
AOI22X1TS U1393 ( .A0(d_ff_Xn[8]), .A1(n908), .B0(sign_inv_out[8]), .B1(n907), .Y(n882) );
AOI22X1TS U1394 ( .A0(d_ff_Xn[9]), .A1(n908), .B0(sign_inv_out[9]), .B1(n907), .Y(n883) );
BUFX3TS U1395 ( .A(n884), .Y(n898) );
AOI22X1TS U1396 ( .A0(d_ff_Xn[18]), .A1(n904), .B0(sign_inv_out[18]), .B1(
n898), .Y(n885) );
BUFX3TS U1397 ( .A(n886), .Y(n919) );
BUFX3TS U1398 ( .A(n860), .Y(n917) );
AOI22X1TS U1399 ( .A0(d_ff_Xn[22]), .A1(n917), .B0(sign_inv_out[22]), .B1(
n916), .Y(n887) );
AOI22X1TS U1400 ( .A0(d_ff_Xn[21]), .A1(n917), .B0(sign_inv_out[21]), .B1(
n898), .Y(n888) );
AOI22X1TS U1401 ( .A0(d_ff_Xn[15]), .A1(n904), .B0(sign_inv_out[15]), .B1(
n898), .Y(n889) );
AOI22X1TS U1402 ( .A0(d_ff_Xn[19]), .A1(n904), .B0(sign_inv_out[19]), .B1(
n898), .Y(n890) );
AOI22X1TS U1403 ( .A0(d_ff_Xn[20]), .A1(n917), .B0(sign_inv_out[20]), .B1(
n898), .Y(n891) );
AOI22X1TS U1404 ( .A0(d_ff_Xn[26]), .A1(n917), .B0(sign_inv_out[26]), .B1(
n916), .Y(n892) );
AOI22X1TS U1405 ( .A0(d_ff_Xn[17]), .A1(n904), .B0(sign_inv_out[17]), .B1(
n898), .Y(n893) );
AOI22X1TS U1406 ( .A0(d_ff_Xn[16]), .A1(n904), .B0(sign_inv_out[16]), .B1(
n898), .Y(n894) );
AOI22X1TS U1407 ( .A0(d_ff_Xn[13]), .A1(n904), .B0(sign_inv_out[13]), .B1(
n898), .Y(n895) );
AOI22X1TS U1408 ( .A0(d_ff_Xn[7]), .A1(n908), .B0(sign_inv_out[7]), .B1(n907), .Y(n896) );
AOI22X1TS U1409 ( .A0(d_ff_Xn[12]), .A1(n904), .B0(sign_inv_out[12]), .B1(
n898), .Y(n897) );
AOI22X1TS U1410 ( .A0(d_ff_Xn[14]), .A1(n904), .B0(sign_inv_out[14]), .B1(
n898), .Y(n899) );
AOI22X1TS U1411 ( .A0(d_ff_Xn[6]), .A1(n908), .B0(sign_inv_out[6]), .B1(n907), .Y(n900) );
AOI22X1TS U1412 ( .A0(d_ff_Xn[1]), .A1(n908), .B0(sign_inv_out[1]), .B1(n884), .Y(n901) );
AOI22X1TS U1413 ( .A0(d_ff_Xn[5]), .A1(n908), .B0(sign_inv_out[5]), .B1(n907), .Y(n902) );
AOI22X1TS U1414 ( .A0(d_ff_Xn[2]), .A1(n908), .B0(sign_inv_out[2]), .B1(n907), .Y(n903) );
AOI22X1TS U1415 ( .A0(d_ff_Xn[10]), .A1(n904), .B0(sign_inv_out[10]), .B1(
n907), .Y(n905) );
AOI22X1TS U1416 ( .A0(d_ff_Xn[3]), .A1(n908), .B0(sign_inv_out[3]), .B1(n907), .Y(n909) );
AOI22X1TS U1417 ( .A0(d_ff_Xn[25]), .A1(n917), .B0(sign_inv_out[25]), .B1(
n916), .Y(n911) );
AOI22X1TS U1418 ( .A0(d_ff_Xn[23]), .A1(n917), .B0(sign_inv_out[23]), .B1(
n916), .Y(n912) );
AOI22X1TS U1419 ( .A0(d_ff_Xn[28]), .A1(n917), .B0(sign_inv_out[28]), .B1(
n916), .Y(n913) );
AOI22X1TS U1420 ( .A0(d_ff_Xn[29]), .A1(n917), .B0(sign_inv_out[29]), .B1(
n916), .Y(n914) );
AOI22X1TS U1421 ( .A0(d_ff_Xn[24]), .A1(n917), .B0(sign_inv_out[24]), .B1(
n916), .Y(n915) );
AOI22X1TS U1422 ( .A0(d_ff_Xn[27]), .A1(n917), .B0(sign_inv_out[27]), .B1(
n916), .Y(n918) );
OAI32X1TS U1423 ( .A0(cont_iter_out[2]), .A1(n1126), .A2(n1046), .B0(n920),
.B1(n804), .Y(n726) );
BUFX3TS U1424 ( .A(n937), .Y(n975) );
BUFX3TS U1425 ( .A(n953), .Y(n973) );
INVX2TS U1426 ( .A(n921), .Y(add_subt_dataB[23]) );
INVX2TS U1427 ( .A(n922), .Y(add_subt_dataB[24]) );
BUFX3TS U1428 ( .A(n937), .Y(n969) );
INVX2TS U1429 ( .A(n923), .Y(add_subt_dataB[0]) );
INVX2TS U1430 ( .A(n924), .Y(add_subt_dataB[2]) );
AOI222X1TS U1431 ( .A0(d_ff3_LUT_out[13]), .A1(n975), .B0(n943), .B1(
d_ff3_sh_x_out[13]), .C0(n973), .C1(d_ff3_sh_y_out[13]), .Y(n925) );
INVX2TS U1432 ( .A(n925), .Y(add_subt_dataB[13]) );
INVX2TS U1433 ( .A(n926), .Y(add_subt_dataB[1]) );
BUFX3TS U1434 ( .A(n953), .Y(n948) );
AOI222X1TS U1435 ( .A0(d_ff3_LUT_out[14]), .A1(n937), .B0(n943), .B1(
d_ff3_sh_x_out[14]), .C0(n948), .C1(d_ff3_sh_y_out[14]), .Y(n927) );
INVX2TS U1436 ( .A(n927), .Y(add_subt_dataB[14]) );
BUFX3TS U1437 ( .A(n953), .Y(n950) );
AOI222X1TS U1438 ( .A0(d_ff3_LUT_out[15]), .A1(n951), .B0(n943), .B1(
d_ff3_sh_x_out[15]), .C0(n950), .C1(d_ff3_sh_y_out[15]), .Y(n928) );
INVX2TS U1439 ( .A(n928), .Y(add_subt_dataB[15]) );
AOI222X1TS U1440 ( .A0(d_ff3_LUT_out[7]), .A1(n969), .B0(n943), .B1(
d_ff3_sh_x_out[7]), .C0(n948), .C1(d_ff3_sh_y_out[7]), .Y(n929) );
INVX2TS U1441 ( .A(n929), .Y(add_subt_dataB[7]) );
AOI222X1TS U1442 ( .A0(d_ff3_LUT_out[16]), .A1(n937), .B0(n943), .B1(
d_ff3_sh_x_out[16]), .C0(n950), .C1(d_ff3_sh_y_out[16]), .Y(n930) );
INVX2TS U1443 ( .A(n930), .Y(add_subt_dataB[16]) );
AOI222X1TS U1444 ( .A0(d_ff3_LUT_out[26]), .A1(n975), .B0(n971), .B1(
d_ff3_sh_x_out[26]), .C0(n950), .C1(d_ff3_sh_y_out[26]), .Y(n932) );
INVX2TS U1445 ( .A(n932), .Y(add_subt_dataB[26]) );
AOI222X1TS U1446 ( .A0(d_ff3_LUT_out[20]), .A1(n975), .B0(n971), .B1(
d_ff3_sh_x_out[20]), .C0(n950), .C1(d_ff3_sh_y_out[20]), .Y(n933) );
INVX2TS U1447 ( .A(n933), .Y(add_subt_dataB[20]) );
AOI222X1TS U1448 ( .A0(d_ff3_LUT_out[21]), .A1(n975), .B0(n971), .B1(
d_ff3_sh_x_out[21]), .C0(n950), .C1(d_ff3_sh_y_out[21]), .Y(n934) );
INVX2TS U1449 ( .A(n934), .Y(add_subt_dataB[21]) );
AOI222X1TS U1450 ( .A0(d_ff3_LUT_out[3]), .A1(n969), .B0(n1027), .B1(
d_ff3_sh_x_out[3]), .C0(n948), .C1(d_ff3_sh_y_out[3]), .Y(n935) );
INVX2TS U1451 ( .A(n935), .Y(add_subt_dataB[3]) );
AOI222X1TS U1452 ( .A0(n1028), .A1(d_ff3_LUT_out[8]), .B0(n943), .B1(
d_ff3_sh_x_out[8]), .C0(n948), .C1(d_ff3_sh_y_out[8]), .Y(n936) );
INVX2TS U1453 ( .A(n936), .Y(add_subt_dataB[8]) );
AOI222X1TS U1454 ( .A0(d_ff3_LUT_out[11]), .A1(n937), .B0(n943), .B1(
d_ff3_sh_x_out[11]), .C0(n948), .C1(d_ff3_sh_y_out[11]), .Y(n938) );
INVX2TS U1455 ( .A(n938), .Y(add_subt_dataB[11]) );
AOI222X1TS U1456 ( .A0(n937), .A1(d_ff3_LUT_out[19]), .B0(n971), .B1(
d_ff3_sh_x_out[19]), .C0(n950), .C1(d_ff3_sh_y_out[19]), .Y(n939) );
INVX2TS U1457 ( .A(n939), .Y(add_subt_dataB[19]) );
AOI222X1TS U1458 ( .A0(d_ff3_LUT_out[9]), .A1(n951), .B0(n943), .B1(
d_ff3_sh_x_out[9]), .C0(n948), .C1(d_ff3_sh_y_out[9]), .Y(n940) );
INVX2TS U1459 ( .A(n940), .Y(add_subt_dataB[9]) );
INVX2TS U1460 ( .A(n941), .Y(add_subt_dataB[6]) );
AOI222X1TS U1461 ( .A0(d_ff3_LUT_out[17]), .A1(n969), .B0(n943), .B1(
d_ff3_sh_x_out[17]), .C0(n950), .C1(d_ff3_sh_y_out[17]), .Y(n942) );
INVX2TS U1462 ( .A(n942), .Y(add_subt_dataB[17]) );
AOI222X1TS U1463 ( .A0(d_ff3_LUT_out[10]), .A1(n951), .B0(n943), .B1(
d_ff3_sh_x_out[10]), .C0(n948), .C1(d_ff3_sh_y_out[10]), .Y(n944) );
INVX2TS U1464 ( .A(n944), .Y(add_subt_dataB[10]) );
AOI222X1TS U1465 ( .A0(d_ff3_LUT_out[18]), .A1(n951), .B0(n971), .B1(
d_ff3_sh_x_out[18]), .C0(n950), .C1(d_ff3_sh_y_out[18]), .Y(n945) );
INVX2TS U1466 ( .A(n945), .Y(add_subt_dataB[18]) );
INVX2TS U1467 ( .A(n946), .Y(add_subt_dataB[25]) );
AOI222X1TS U1468 ( .A0(d_ff3_LUT_out[5]), .A1(n969), .B0(n1027), .B1(
d_ff3_sh_x_out[5]), .C0(n948), .C1(d_ff3_sh_y_out[5]), .Y(n947) );
INVX2TS U1469 ( .A(n947), .Y(add_subt_dataB[5]) );
AOI222X1TS U1470 ( .A0(d_ff3_LUT_out[4]), .A1(n969), .B0(n1027), .B1(
d_ff3_sh_x_out[4]), .C0(n948), .C1(d_ff3_sh_y_out[4]), .Y(n949) );
INVX2TS U1471 ( .A(n949), .Y(add_subt_dataB[4]) );
AOI222X1TS U1472 ( .A0(n951), .A1(d_ff3_LUT_out[22]), .B0(n971), .B1(
d_ff3_sh_x_out[22]), .C0(n950), .C1(d_ff3_sh_y_out[22]), .Y(n952) );
INVX2TS U1473 ( .A(n952), .Y(add_subt_dataB[22]) );
BUFX3TS U1474 ( .A(n953), .Y(n965) );
INVX2TS U1475 ( .A(n954), .Y(add_subt_dataA[13]) );
INVX2TS U1476 ( .A(n955), .Y(add_subt_dataA[16]) );
INVX2TS U1477 ( .A(n957), .Y(add_subt_dataA[10]) );
INVX2TS U1478 ( .A(n958), .Y(add_subt_dataA[17]) );
INVX2TS U1479 ( .A(n959), .Y(add_subt_dataA[21]) );
INVX2TS U1480 ( .A(n961), .Y(add_subt_dataA[22]) );
INVX2TS U1481 ( .A(n962), .Y(add_subt_dataA[18]) );
INVX2TS U1482 ( .A(n963), .Y(add_subt_dataA[15]) );
INVX2TS U1483 ( .A(n964), .Y(add_subt_dataA[19]) );
INVX2TS U1484 ( .A(n967), .Y(add_subt_dataA[14]) );
INVX2TS U1485 ( .A(n968), .Y(add_subt_dataA[20]) );
INVX2TS U1486 ( .A(n970), .Y(add_subt_dataA[31]) );
INVX2TS U1487 ( .A(n972), .Y(add_subt_dataA[0]) );
INVX2TS U1488 ( .A(n976), .Y(add_subt_dataA[26]) );
BUFX3TS U1489 ( .A(n871), .Y(n1012) );
INVX2TS U1490 ( .A(n977), .Y(n476) );
INVX2TS U1491 ( .A(n1137), .Y(n1013) );
BUFX3TS U1492 ( .A(n871), .Y(n990) );
INVX2TS U1493 ( .A(n978), .Y(n490) );
INVX2TS U1494 ( .A(n979), .Y(n492) );
INVX2TS U1495 ( .A(n980), .Y(n488) );
INVX2TS U1496 ( .A(n981), .Y(n494) );
INVX2TS U1497 ( .A(n982), .Y(n493) );
INVX2TS U1498 ( .A(n983), .Y(n486) );
INVX2TS U1499 ( .A(n984), .Y(n491) );
INVX2TS U1500 ( .A(n985), .Y(n484) );
INVX2TS U1501 ( .A(n986), .Y(n489) );
INVX2TS U1502 ( .A(n987), .Y(n482) );
INVX2TS U1503 ( .A(n988), .Y(n487) );
BUFX3TS U1504 ( .A(n871), .Y(n1009) );
INVX2TS U1505 ( .A(n989), .Y(n466) );
INVX2TS U1506 ( .A(n991), .Y(n485) );
INVX2TS U1507 ( .A(n992), .Y(n480) );
AOI222X1TS U1508 ( .A0(n1172), .A1(d_ff2_Z[24]), .B0(n1009), .B1(d_ff1_Z[24]), .C0(d_ff_Zn[24]), .C1(n1003), .Y(n993) );
INVX2TS U1509 ( .A(n993), .Y(n472) );
INVX2TS U1510 ( .A(n994), .Y(n478) );
INVX2TS U1511 ( .A(n995), .Y(n470) );
AOI222X1TS U1512 ( .A0(n1164), .A1(d_ff2_Z[25]), .B0(n1009), .B1(d_ff1_Z[25]), .C0(d_ff_Zn[25]), .C1(n1003), .Y(n996) );
INVX2TS U1513 ( .A(n996), .Y(n471) );
AOI222X1TS U1514 ( .A0(n1130), .A1(d_ff2_Z[28]), .B0(n1009), .B1(d_ff1_Z[28]), .C0(d_ff_Zn[28]), .C1(n1003), .Y(n997) );
INVX2TS U1515 ( .A(n997), .Y(n468) );
INVX2TS U1516 ( .A(n998), .Y(n469) );
INVX2TS U1517 ( .A(n999), .Y(n477) );
AOI222X1TS U1518 ( .A0(n1198), .A1(d_ff2_Z[29]), .B0(n1009), .B1(d_ff1_Z[29]), .C0(d_ff_Zn[29]), .C1(n1003), .Y(n1000) );
INVX2TS U1519 ( .A(n1000), .Y(n467) );
AOI222X1TS U1520 ( .A0(n1128), .A1(d_ff2_Z[21]), .B0(n1012), .B1(d_ff1_Z[21]), .C0(d_ff_Zn[21]), .C1(n1003), .Y(n1001) );
INVX2TS U1521 ( .A(n1001), .Y(n475) );
AOI222X1TS U1522 ( .A0(n1004), .A1(d_ff2_Z[22]), .B0(n1009), .B1(d_ff1_Z[22]), .C0(d_ff_Zn[22]), .C1(n1003), .Y(n1002) );
INVX2TS U1523 ( .A(n1002), .Y(n474) );
AOI222X1TS U1524 ( .A0(n1172), .A1(d_ff2_Z[23]), .B0(n1009), .B1(d_ff1_Z[23]), .C0(d_ff_Zn[23]), .C1(n1003), .Y(n1005) );
INVX2TS U1525 ( .A(n1005), .Y(n473) );
INVX2TS U1526 ( .A(n1006), .Y(n483) );
INVX2TS U1527 ( .A(n1008), .Y(n481) );
INVX2TS U1528 ( .A(n1010), .Y(n465) );
INVX2TS U1529 ( .A(n1014), .Y(n479) );
OR4X2TS U1530 ( .A(ack_cordic), .B(n1202), .C(n1206), .D(
cordic_FSM_state_reg[1]), .Y(n1042) );
OAI211XLTS U1531 ( .A0(n1016), .A1(n1206), .B0(n1042), .C0(n1015), .Y(n732)
);
AOI31XLTS U1532 ( .A0(cordic_FSM_state_reg[0]), .A1(n1038), .A2(
beg_fsm_cordic), .B0(ack_add_subt), .Y(n1022) );
OAI211XLTS U1533 ( .A0(n1202), .A1(n1206), .B0(cordic_FSM_state_reg[1]),
.C0(n1213), .Y(n1021) );
AO22XLTS U1534 ( .A0(n1023), .A1(d_ff3_sh_x_out[31]), .B0(n953), .B1(
d_ff3_sh_y_out[31]), .Y(add_subt_dataB[31]) );
AO22XLTS U1535 ( .A0(d_ff3_sh_y_out[30]), .A1(n953), .B0(d_ff3_sh_x_out[30]),
.B1(n1023), .Y(add_subt_dataB[30]) );
AOI22X1TS U1536 ( .A0(n1027), .A1(d_ff3_sh_x_out[27]), .B0(n1024), .B1(
d_ff3_sh_y_out[27]), .Y(n1026) );
NAND2X1TS U1537 ( .A(d_ff3_LUT_out[27]), .B(n937), .Y(n1025) );
NAND2X1TS U1538 ( .A(n1026), .B(n1025), .Y(add_subt_dataB[27]) );
AOI22X1TS U1539 ( .A0(d_ff2_Z[25]), .A1(n1028), .B0(d_ff2_Y[25]), .B1(n1027),
.Y(n1029) );
OAI2BB1X1TS U1540 ( .A0N(d_ff2_X[25]), .A1N(n953), .B0(n1029), .Y(
add_subt_dataA[25]) );
AOI2BB2XLTS U1541 ( .B0(d_ff3_sign_out), .B1(n1208), .A0N(n1208), .A1N(
d_ff3_sign_out), .Y(op_add_subt) );
AOI31XLTS U1542 ( .A0(cordic_FSM_state_reg[3]), .A1(cordic_FSM_state_reg[0]),
.A2(ack_cordic), .B0(cordic_FSM_state_reg[1]), .Y(n1030) );
OAI21X1TS U1543 ( .A0(n1031), .A1(n1030), .B0(cordic_FSM_state_reg[2]), .Y(
n1034) );
NAND2X1TS U1544 ( .A(cont_var_out[1]), .B(n1208), .Y(n1032) );
AOI32X1TS U1545 ( .A0(n1035), .A1(n1034), .A2(n1033), .B0(n1213), .B1(n1034),
.Y(n731) );
INVX2TS U1546 ( .A(beg_fsm_cordic), .Y(n1037) );
NOR2BX1TS U1547 ( .AN(ready_add_subt), .B(cordic_FSM_state_reg[2]), .Y(n1039) );
NAND3X1TS U1548 ( .A(cont_var_out[0]), .B(ack_add_subt), .C(n1049), .Y(n1051) );
AOI21X1TS U1549 ( .A0(n1079), .A1(n1051), .B0(n1044), .Y(n729) );
NAND2X1TS U1550 ( .A(n1057), .B(n1046), .Y(n1045) );
AOI22X1TS U1551 ( .A0(n1110), .A1(n1045), .B0(n1046), .B1(n1104), .Y(n728)
);
NOR2X1TS U1552 ( .A(n1104), .B(n1046), .Y(n1048) );
AOI21X1TS U1553 ( .A0(cont_iter_out[1]), .A1(n1048), .B0(n1047), .Y(n727) );
AOI31XLTS U1554 ( .A0(ack_add_subt), .A1(n1049), .A2(n1079), .B0(
cont_var_out[0]), .Y(n1050) );
CLKBUFX2TS U1555 ( .A(n1053), .Y(n1055) );
BUFX3TS U1556 ( .A(n1055), .Y(n1060) );
INVX2TS U1557 ( .A(n1055), .Y(n1052) );
INVX2TS U1558 ( .A(n1055), .Y(n1059) );
INVX2TS U1559 ( .A(n1055), .Y(n1056) );
NOR2BX1TS U1560 ( .AN(n1061), .B(n1080), .Y(n1062) );
BUFX3TS U1561 ( .A(n1067), .Y(n1063) );
INVX2TS U1562 ( .A(n1063), .Y(n1064) );
BUFX3TS U1563 ( .A(n1067), .Y(n1069) );
BUFX3TS U1564 ( .A(n1067), .Y(n1065) );
INVX2TS U1565 ( .A(n1069), .Y(n1066) );
INVX2TS U1566 ( .A(n1069), .Y(n1068) );
INVX2TS U1567 ( .A(n1069), .Y(n1070) );
BUFX3TS U1568 ( .A(n1071), .Y(n1077) );
OAI2BB2XLTS U1569 ( .B0(n1074), .B1(n1217), .A0N(n1077), .A1N(
result_add_subt[2]), .Y(n650) );
OAI2BB2XLTS U1570 ( .B0(n1073), .B1(n1218), .A0N(n1077), .A1N(
result_add_subt[3]), .Y(n649) );
OAI2BB2XLTS U1571 ( .B0(n1073), .B1(n1219), .A0N(n1077), .A1N(
result_add_subt[4]), .Y(n648) );
BUFX3TS U1572 ( .A(n1072), .Y(n1076) );
OAI2BB2XLTS U1573 ( .B0(n1073), .B1(n1220), .A0N(n1076), .A1N(
result_add_subt[5]), .Y(n647) );
OAI2BB2XLTS U1574 ( .B0(n1073), .B1(n1221), .A0N(n1076), .A1N(
result_add_subt[6]), .Y(n646) );
OAI2BB2XLTS U1575 ( .B0(n1073), .B1(n1222), .A0N(n1076), .A1N(
result_add_subt[7]), .Y(n645) );
OAI2BB2XLTS U1576 ( .B0(n1073), .B1(n1223), .A0N(n1074), .A1N(
result_add_subt[8]), .Y(n644) );
OAI2BB2XLTS U1577 ( .B0(n1073), .B1(n1224), .A0N(n1076), .A1N(
result_add_subt[9]), .Y(n643) );
OAI2BB2XLTS U1578 ( .B0(n1073), .B1(n1225), .A0N(n1074), .A1N(
result_add_subt[10]), .Y(n642) );
OAI2BB2XLTS U1579 ( .B0(n1075), .B1(n1226), .A0N(n1074), .A1N(
result_add_subt[11]), .Y(n641) );
OAI2BB2XLTS U1580 ( .B0(n1075), .B1(n1227), .A0N(n1074), .A1N(
result_add_subt[12]), .Y(n640) );
OAI2BB2XLTS U1581 ( .B0(n1075), .B1(n1228), .A0N(n1074), .A1N(
result_add_subt[13]), .Y(n639) );
OAI2BB2XLTS U1582 ( .B0(n1075), .B1(n1229), .A0N(n1074), .A1N(
result_add_subt[14]), .Y(n638) );
OAI2BB2XLTS U1583 ( .B0(n1073), .B1(n1230), .A0N(n1076), .A1N(
result_add_subt[15]), .Y(n637) );
OAI2BB2XLTS U1584 ( .B0(n1075), .B1(n1231), .A0N(n1074), .A1N(
result_add_subt[16]), .Y(n636) );
OAI2BB2XLTS U1585 ( .B0(n1075), .B1(n1232), .A0N(n1074), .A1N(
result_add_subt[17]), .Y(n635) );
OAI2BB2XLTS U1586 ( .B0(n1075), .B1(n1233), .A0N(n1076), .A1N(
result_add_subt[18]), .Y(n634) );
OAI2BB2XLTS U1587 ( .B0(n1075), .B1(n1234), .A0N(n1076), .A1N(
result_add_subt[19]), .Y(n633) );
OAI2BB2XLTS U1588 ( .B0(n1075), .B1(n1235), .A0N(n1076), .A1N(
result_add_subt[20]), .Y(n632) );
OAI2BB2XLTS U1589 ( .B0(n1071), .B1(n1236), .A0N(n1077), .A1N(
result_add_subt[21]), .Y(n631) );
OAI2BB2XLTS U1590 ( .B0(n1071), .B1(n1237), .A0N(n1076), .A1N(
result_add_subt[22]), .Y(n630) );
OAI2BB2XLTS U1591 ( .B0(n1072), .B1(n1134), .A0N(n1076), .A1N(
result_add_subt[23]), .Y(n629) );
OAI2BB2XLTS U1592 ( .B0(n1072), .B1(n1135), .A0N(n1077), .A1N(
result_add_subt[24]), .Y(n628) );
OAI2BB2XLTS U1593 ( .B0(n1071), .B1(n1238), .A0N(n1077), .A1N(
result_add_subt[25]), .Y(n627) );
OAI2BB2XLTS U1594 ( .B0(n1071), .B1(n1239), .A0N(n1077), .A1N(
result_add_subt[26]), .Y(n626) );
OAI2BB2XLTS U1595 ( .B0(n1072), .B1(n1136), .A0N(n1077), .A1N(
result_add_subt[27]), .Y(n625) );
OAI2BB2XLTS U1596 ( .B0(n829), .B1(n1138), .A0N(n1077), .A1N(
result_add_subt[28]), .Y(n624) );
OAI2BB2XLTS U1597 ( .B0(n1072), .B1(n1139), .A0N(n1077), .A1N(
result_add_subt[29]), .Y(n623) );
AOI21X1TS U1598 ( .A0(n1208), .A1(n1079), .B0(n1078), .Y(n1081) );
BUFX3TS U1599 ( .A(n810), .Y(n1083) );
INVX2TS U1600 ( .A(n1083), .Y(n1084) );
BUFX3TS U1601 ( .A(n810), .Y(n1085) );
INVX2TS U1602 ( .A(n1083), .Y(n1086) );
BUFX3TS U1603 ( .A(n810), .Y(n1087) );
INVX2TS U1604 ( .A(n1083), .Y(n1088) );
BUFX3TS U1605 ( .A(n1093), .Y(n1095) );
INVX2TS U1606 ( .A(n1095), .Y(n1090) );
INVX2TS U1607 ( .A(n1094), .Y(n1091) );
INVX2TS U1608 ( .A(n1094), .Y(n1096) );
INVX2TS U1609 ( .A(n1099), .Y(n1121) );
AOI21X1TS U1610 ( .A0(n1121), .A1(n1193), .B0(n1100), .Y(n1108) );
AOI22X1TS U1611 ( .A0(n1105), .A1(n1101), .B0(n1111), .B1(d_ff3_LUT_out[0]),
.Y(n1102) );
NAND2X1TS U1612 ( .A(n1108), .B(n1102), .Y(n524) );
INVX2TS U1613 ( .A(n1105), .Y(n1106) );
OAI211X1TS U1614 ( .A0(n1106), .A1(n1181), .B0(n1114), .C0(n1193), .Y(n1112)
);
OAI2BB1X1TS U1615 ( .A0N(d_ff3_LUT_out[3]), .A1N(n1119), .B0(n1112), .Y(n521) );
OAI21X1TS U1616 ( .A0(n1181), .A1(cont_iter_out[3]), .B0(n1193), .Y(n1125)
);
OA22X1TS U1617 ( .A0(n1187), .A1(d_ff3_LUT_out[4]), .B0(n1125), .B1(n1103),
.Y(n520) );
AOI21X1TS U1618 ( .A0(n1105), .A1(n1104), .B0(n1177), .Y(n1117) );
OAI2BB1X1TS U1619 ( .A0N(d_ff3_LUT_out[10]), .A1N(n1119), .B0(n1108), .Y(
n514) );
AOI22X1TS U1620 ( .A0(n1133), .A1(n1109), .B0(n808), .B1(n1177), .Y(n512) );
OAI31X1TS U1621 ( .A0(n1110), .A1(n1181), .A2(cont_iter_out[3]), .B0(n1114),
.Y(n1116) );
NOR2X1TS U1622 ( .A(n1111), .B(n1116), .Y(n1113) );
OAI2BB1X1TS U1623 ( .A0N(d_ff3_LUT_out[15]), .A1N(n1119), .B0(n1115), .Y(
n509) );
OAI2BB1X1TS U1624 ( .A0N(d_ff3_LUT_out[16]), .A1N(n1119), .B0(n1112), .Y(
n508) );
OAI2BB1X1TS U1625 ( .A0N(d_ff3_LUT_out[17]), .A1N(n1119), .B0(n1115), .Y(
n507) );
NAND2X1TS U1626 ( .A(n1133), .B(n1114), .Y(n1118) );
OAI2BB1X1TS U1627 ( .A0N(d_ff3_LUT_out[19]), .A1N(n1119), .B0(n1118), .Y(
n505) );
OAI2BB1X1TS U1628 ( .A0N(d_ff3_LUT_out[20]), .A1N(n1119), .B0(n1115), .Y(
n504) );
OAI2BB1X1TS U1629 ( .A0N(d_ff3_LUT_out[22]), .A1N(n1119), .B0(n1118), .Y(
n502) );
AOI32X1TS U1630 ( .A0(n1124), .A1(n1123), .A2(n1122), .B0(cont_iter_out[1]),
.B1(n1123), .Y(n500) );
AOI21X1TS U1631 ( .A0(n1126), .A1(n1204), .B0(n1125), .Y(n1127) );
INVX2TS U1632 ( .A(n1166), .Y(n1185) );
INVX2TS U1633 ( .A(n1162), .Y(n1173) );
INVX2TS U1634 ( .A(n1195), .Y(n1201) );
INVX2TS U1635 ( .A(n1169), .Y(n1128) );
INVX2TS U1636 ( .A(n1195), .Y(n1197) );
INVX2TS U1637 ( .A(n1169), .Y(n1130) );
BUFX3TS U1638 ( .A(n1195), .Y(n1131) );
BUFX3TS U1639 ( .A(n1159), .Y(n1167) );
INVX2TS U1640 ( .A(n1167), .Y(n1132) );
INVX2TS U1641 ( .A(n1167), .Y(n1161) );
INVX2TS U1642 ( .A(n1195), .Y(n1158) );
INVX2TS U1643 ( .A(n1169), .Y(n1198) );
BUFX3TS U1644 ( .A(n1195), .Y(n1200) );
INVX2TS U1645 ( .A(n1169), .Y(n1164) );
BUFX3TS U1646 ( .A(n1166), .Y(n1160) );
OAI22X1TS U1647 ( .A0(n1137), .A1(n801), .B0(n1134), .B1(n1162), .Y(n417) );
OAI22X1TS U1648 ( .A0(n1137), .A1(n799), .B0(n1135), .B1(n1162), .Y(n416) );
OAI22X1TS U1649 ( .A0(n1137), .A1(n1209), .B0(n1136), .B1(n1162), .Y(n413)
);
OAI22X1TS U1650 ( .A0(n819), .A1(n1151), .B0(n1138), .B1(n1162), .Y(n412) );
OAI22X1TS U1651 ( .A0(n819), .A1(n1210), .B0(n1139), .B1(n1162), .Y(n411) );
OAI22X1TS U1652 ( .A0(n819), .A1(n1211), .B0(n1140), .B1(n1162), .Y(n410) );
AOI22X1TS U1653 ( .A0(cont_iter_out[1]), .A1(n799), .B0(d_ff2_Y[24]), .B1(
n798), .Y(n1141) );
XNOR2X1TS U1654 ( .A(n1144), .B(n1141), .Y(n1142) );
NAND2X1TS U1655 ( .A(d_ff2_Y[24]), .B(n798), .Y(n1143) );
AOI22X1TS U1656 ( .A0(cont_iter_out[1]), .A1(n799), .B0(n1144), .B1(n1143),
.Y(n1146) );
NOR2X1TS U1657 ( .A(d_ff2_Y[27]), .B(n1150), .Y(n1152) );
AOI21X1TS U1658 ( .A0(n1150), .A1(d_ff2_Y[27]), .B0(n1152), .Y(n1149) );
OR3X1TS U1659 ( .A(n1150), .B(d_ff2_Y[28]), .C(d_ff2_Y[27]), .Y(n1154) );
NOR2X1TS U1660 ( .A(d_ff2_Y[29]), .B(n1154), .Y(n1156) );
AOI21X1TS U1661 ( .A0(d_ff2_Y[29]), .A1(n1154), .B0(n1156), .Y(n1155) );
XOR2X1TS U1662 ( .A(d_ff2_Y[30]), .B(n1156), .Y(n1157) );
OA22X1TS U1663 ( .A0(n1169), .A1(d_ff2_X[1]), .B0(d_ff_Xn[1]), .B1(n1159),
.Y(n397) );
INVX2TS U1664 ( .A(n1195), .Y(n1165) );
BUFX3TS U1665 ( .A(n1169), .Y(n1171) );
OA22X1TS U1666 ( .A0(n1171), .A1(d_ff2_X[2]), .B0(d_ff_Xn[2]), .B1(n1167),
.Y(n395) );
OA22X1TS U1667 ( .A0(n1171), .A1(d_ff2_X[3]), .B0(d_ff_Xn[3]), .B1(n1167),
.Y(n393) );
INVX2TS U1668 ( .A(n1195), .Y(n1179) );
BUFX3TS U1669 ( .A(n1166), .Y(n1163) );
OA22X1TS U1670 ( .A0(n1171), .A1(d_ff2_X[5]), .B0(d_ff_Xn[5]), .B1(n1167),
.Y(n389) );
OA22X1TS U1671 ( .A0(n1171), .A1(d_ff2_X[6]), .B0(d_ff_Xn[6]), .B1(n1167),
.Y(n387) );
OA22X1TS U1672 ( .A0(n1171), .A1(d_ff2_X[7]), .B0(d_ff_Xn[7]), .B1(n1167),
.Y(n385) );
OA22X1TS U1673 ( .A0(n1171), .A1(d_ff2_X[10]), .B0(d_ff_Xn[10]), .B1(n1167),
.Y(n379) );
BUFX3TS U1674 ( .A(n1162), .Y(n1170) );
OA22X1TS U1675 ( .A0(n1171), .A1(d_ff2_X[12]), .B0(d_ff_Xn[12]), .B1(n1170),
.Y(n375) );
OA22X1TS U1676 ( .A0(n1171), .A1(d_ff2_X[13]), .B0(d_ff_Xn[13]), .B1(n1170),
.Y(n373) );
OA22X1TS U1677 ( .A0(n1137), .A1(d_ff2_X[14]), .B0(d_ff_Xn[14]), .B1(n1170),
.Y(n371) );
OA22X1TS U1678 ( .A0(n1137), .A1(d_ff2_X[16]), .B0(d_ff_Xn[16]), .B1(n1170),
.Y(n367) );
OA22X1TS U1679 ( .A0(n1137), .A1(d_ff2_X[17]), .B0(d_ff_Xn[17]), .B1(n1170),
.Y(n365) );
OA22X1TS U1680 ( .A0(n1169), .A1(d_ff2_X[19]), .B0(d_ff_Xn[19]), .B1(n1170),
.Y(n361) );
OA22X1TS U1681 ( .A0(n819), .A1(d_ff2_X[20]), .B0(d_ff_Xn[20]), .B1(n1170),
.Y(n359) );
OA22X1TS U1682 ( .A0(d_ff2_X[24]), .A1(n1171), .B0(d_ff_Xn[24]), .B1(n1170),
.Y(n352) );
OA22X1TS U1683 ( .A0(n819), .A1(d_ff2_X[26]), .B0(d_ff_Xn[26]), .B1(n1170),
.Y(n350) );
OA22X1TS U1684 ( .A0(n1169), .A1(d_ff2_X[28]), .B0(d_ff_Xn[28]), .B1(n1159),
.Y(n348) );
OA22X1TS U1685 ( .A0(n1171), .A1(d_ff2_X[29]), .B0(d_ff_Xn[29]), .B1(n1170),
.Y(n347) );
AOI222X1TS U1686 ( .A0(n1181), .A1(n1180), .B0(n805), .B1(n800), .C0(n1180),
.C1(n800), .Y(n1183) );
AOI21X1TS U1687 ( .A0(n1188), .A1(d_ff2_X[27]), .B0(n1184), .Y(n1186) );
OR3X1TS U1688 ( .A(d_ff2_X[28]), .B(d_ff2_X[27]), .C(n1188), .Y(n1190) );
AOI32X1TS U1689 ( .A0(n1190), .A1(n1187), .A2(n1189), .B0(n807), .B1(n1191),
.Y(n340) );
NOR2X1TS U1690 ( .A(d_ff2_X[29]), .B(n1190), .Y(n1194) );
AOI21X1TS U1691 ( .A0(d_ff2_X[29]), .A1(n1190), .B0(n1194), .Y(n1192) );
AOI22X1TS U1692 ( .A0(n1187), .A1(n1192), .B0(n802), .B1(n1191), .Y(n339) );
XOR2X1TS U1693 ( .A(d_ff2_X[30]), .B(n1194), .Y(n1196) );
initial $sdf_annotate("CORDIC_Arch2v1_ASIC_fpu_syn_constraints_clk10.tcl_syn.sdf");
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_dtl_padx12.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_dtl_padx12(ps_select_buf ,bypass_en_buf ,serial_out ,
serial_in ,bso ,to_core ,so ,pad ,por_l_buf ,oe_buf ,reset_l_buf ,
update_dr_buf ,cbu1 ,cbd1 ,up_open_buf ,bsr_si ,mode_ctl_buf ,
se_buf ,shift_dr_buf ,hiz_l_buf ,si ,rst_val_dn_buf ,down_25_buf ,
clk ,data ,clock_dr_buf ,rst_val_up_buf ,sel_bypass_buf ,vddo ,cbu0
,cbd0 ,ref ,rst_io_l_buf );
output [11:0] serial_out ;
output [11:0] to_core ;
input [1:0] ps_select_buf ;
input [1:0] bypass_en_buf ;
input [11:0] serial_in ;
input [1:0] por_l_buf ;
input [1:0] oe_buf ;
input [1:0] reset_l_buf ;
input [1:0] update_dr_buf ;
input [8:1] cbu1 ;
input [8:1] cbd1 ;
input [1:0] up_open_buf ;
input [1:0] mode_ctl_buf ;
input [1:0] se_buf ;
input [1:0] shift_dr_buf ;
input [1:0] hiz_l_buf ;
input [1:0] rst_val_dn_buf ;
input [1:0] down_25_buf ;
input [11:0] data ;
input [1:0] clock_dr_buf ;
input [1:0] rst_val_up_buf ;
input [1:0] sel_bypass_buf ;
input [8:1] cbu0 ;
input [8:1] cbd0 ;
input [1:0] rst_io_l_buf ;
inout [11:0] pad ;
output bso ;
output so ;
input bsr_si ;
input si ;
input clk ;
input vddo ;
input ref ;
supply1 vdd ;
supply0 vss ;
wire [11:1] bscan ;
wire [11:1] scan ;
wire ck0 ;
wire ck1 ;
wire ck2 ;
wire ck3 ;
bw_io_dtl_pad DTL_0_ (
.cbu ({cbu1 } ),
.cbd ({cbd1 } ),
.bypass_enable (bypass_en_buf[1] ),
.so (scan[1] ),
.por_l (por_l_buf[1] ),
.clock_dr (clock_dr_buf[1] ),
.bypass_in (serial_out[1] ),
.serial_in (serial_in[0] ),
.update_dr (update_dr_buf[1] ),
.clk (ck3 ),
.reset_l (reset_l_buf[1] ),
.hiz_l (hiz_l_buf[1] ),
.ps_select (ps_select_buf[1] ),
.out_type (vdd ),
.shift_dr (shift_dr_buf[1] ),
.rst_io_l (rst_io_l_buf[1] ),
.rst_val_up (rst_val_up_buf[1] ),
.bso (bscan[1] ),
.serial_out (serial_out[0] ),
.bsr_si (bscan[5] ),
.rst_val_dn (rst_val_dn_buf[1] ),
.mode_ctl (mode_ctl_buf[1] ),
.si (scan[5] ),
.oe (oe_buf[1] ),
.data (data[0] ),
.se (se_buf[1] ),
.up_open (up_open_buf[1] ),
.down_25 (down_25_buf[1] ),
.to_core (to_core[0] ),
.ref (ref ),
.pad (pad[0] ),
.vddo (vddo ),
.sel_bypass (sel_bypass_buf[1] ) );
bw_io_dtl_pad DTL_8_ (
.cbu ({cbu1 } ),
.cbd ({cbd1 } ),
.bypass_enable (bypass_en_buf[1] ),
.so (scan[8] ),
.por_l (por_l_buf[1] ),
.clock_dr (clock_dr_buf[1] ),
.bypass_in (serial_out[9] ),
.serial_in (serial_in[8] ),
.update_dr (update_dr_buf[1] ),
.clk (ck2 ),
.reset_l (reset_l_buf[1] ),
.hiz_l (hiz_l_buf[1] ),
.ps_select (ps_select_buf[1] ),
.out_type (vdd ),
.shift_dr (shift_dr_buf[1] ),
.rst_io_l (rst_io_l_buf[1] ),
.rst_val_up (rst_val_up_buf[1] ),
.bso (bscan[8] ),
.serial_out (serial_out[8] ),
.bsr_si (bscan[3] ),
.rst_val_dn (rst_val_dn_buf[1] ),
.mode_ctl (mode_ctl_buf[1] ),
.si (scan[3] ),
.oe (oe_buf[1] ),
.data (data[8] ),
.se (se_buf[1] ),
.up_open (up_open_buf[1] ),
.down_25 (down_25_buf[1] ),
.to_core (to_core[8] ),
.ref (ref ),
.pad (pad[8] ),
.vddo (vddo ),
.sel_bypass (sel_bypass_buf[1] ) );
bw_io_dtl_pad DTL_1_ (
.cbu ({cbu1 } ),
.cbd ({cbd1 } ),
.bypass_enable (bypass_en_buf[1] ),
.so (so ),
.por_l (por_l_buf[1] ),
.clock_dr (clock_dr_buf[1] ),
.bypass_in (vss ),
.serial_in (serial_in[1] ),
.update_dr (update_dr_buf[1] ),
.clk (ck3 ),
.reset_l (reset_l_buf[1] ),
.hiz_l (hiz_l_buf[1] ),
.ps_select (ps_select_buf[1] ),
.out_type (vss ),
.shift_dr (shift_dr_buf[1] ),
.rst_io_l (rst_io_l_buf[1] ),
.rst_val_up (rst_val_up_buf[1] ),
.bso (bso ),
.serial_out (serial_out[1] ),
.bsr_si (bscan[1] ),
.rst_val_dn (rst_val_dn_buf[1] ),
.mode_ctl (mode_ctl_buf[1] ),
.si (scan[1] ),
.oe (oe_buf[1] ),
.data (data[1] ),
.se (se_buf[1] ),
.up_open (up_open_buf[1] ),
.down_25 (down_25_buf[1] ),
.to_core (to_core[1] ),
.ref (ref ),
.pad (pad[1] ),
.vddo (vddo ),
.sel_bypass (sel_bypass_buf[1] ) );
bw_io_dtl_pad DTL_9_ (
.cbu ({cbu1 } ),
.cbd ({cbd1 } ),
.bypass_enable (bypass_en_buf[1] ),
.so (scan[9] ),
.por_l (por_l_buf[1] ),
.clock_dr (clock_dr_buf[1] ),
.bypass_in (vss ),
.serial_in (serial_in[9] ),
.update_dr (update_dr_buf[1] ),
.clk (ck2 ),
.reset_l (reset_l_buf[1] ),
.hiz_l (hiz_l_buf[1] ),
.ps_select (ps_select_buf[1] ),
.out_type (vss ),
.shift_dr (shift_dr_buf[1] ),
.rst_io_l (rst_io_l_buf[1] ),
.rst_val_up (rst_val_up_buf[1] ),
.bso (bscan[9] ),
.serial_out (serial_out[9] ),
.bsr_si (bscan[8] ),
.rst_val_dn (rst_val_dn_buf[1] ),
.mode_ctl (mode_ctl_buf[1] ),
.si (scan[8] ),
.oe (oe_buf[1] ),
.data (data[9] ),
.se (se_buf[1] ),
.up_open (up_open_buf[1] ),
.down_25 (down_25_buf[1] ),
.to_core (to_core[9] ),
.ref (ref ),
.pad (pad[9] ),
.vddo (vddo ),
.sel_bypass (sel_bypass_buf[1] ) );
bw_io_dtl_pad DTL_2_ (
.cbu ({cbu0 } ),
.cbd ({cbd0 } ),
.bypass_enable (bypass_en_buf[0] ),
.so (scan[2] ),
.por_l (por_l_buf[0] ),
.clock_dr (clock_dr_buf[0] ),
.bypass_in (serial_out[3] ),
.serial_in (serial_in[2] ),
.update_dr (update_dr_buf[0] ),
.clk (ck1 ),
.reset_l (reset_l_buf[0] ),
.hiz_l (hiz_l_buf[0] ),
.ps_select (ps_select_buf[0] ),
.out_type (vdd ),
.shift_dr (shift_dr_buf[0] ),
.rst_io_l (rst_io_l_buf[0] ),
.rst_val_up (rst_val_up_buf[0] ),
.bso (bscan[2] ),
.serial_out (serial_out[2] ),
.bsr_si (bscan[7] ),
.rst_val_dn (rst_val_dn_buf[0] ),
.mode_ctl (mode_ctl_buf[0] ),
.si (scan[7] ),
.oe (oe_buf[0] ),
.data (data[2] ),
.se (se_buf[0] ),
.up_open (up_open_buf[0] ),
.down_25 (down_25_buf[0] ),
.to_core (to_core[2] ),
.ref (ref ),
.pad (pad[2] ),
.vddo (vddo ),
.sel_bypass (sel_bypass_buf[0] ) );
bw_io_dtl_pad DTL_3_ (
.cbu ({cbu0 } ),
.cbd ({cbd0 } ),
.bypass_enable (bypass_en_buf[0] ),
.so (scan[3] ),
.por_l (por_l_buf[0] ),
.clock_dr (clock_dr_buf[0] ),
.bypass_in (vss ),
.serial_in (serial_in[3] ),
.update_dr (update_dr_buf[0] ),
.clk (ck1 ),
.reset_l (reset_l_buf[0] ),
.hiz_l (hiz_l_buf[0] ),
.ps_select (ps_select_buf[0] ),
.out_type (vss ),
.shift_dr (shift_dr_buf[0] ),
.rst_io_l (rst_io_l_buf[0] ),
.rst_val_up (rst_val_up_buf[0] ),
.bso (bscan[3] ),
.serial_out (serial_out[3] ),
.bsr_si (bscan[2] ),
.rst_val_dn (rst_val_dn_buf[0] ),
.mode_ctl (mode_ctl_buf[0] ),
.si (scan[2] ),
.oe (oe_buf[0] ),
.data (data[3] ),
.se (se_buf[0] ),
.up_open (up_open_buf[0] ),
.down_25 (down_25_buf[0] ),
.to_core (to_core[3] ),
.ref (ref ),
.pad (pad[3] ),
.vddo (vddo ),
.sel_bypass (sel_bypass_buf[0] ) );
bw_io_dtl_pad DTL_11_ (
.cbu ({cbu0 } ),
.cbd ({cbd0 } ),
.bypass_enable (bypass_en_buf[0] ),
.so (scan[11] ),
.por_l (por_l_buf[0] ),
.clock_dr (clock_dr_buf[0] ),
.bypass_in (vss ),
.serial_in (serial_in[11] ),
.update_dr (update_dr_buf[0] ),
.clk (ck0 ),
.reset_l (reset_l_buf[0] ),
.hiz_l (hiz_l_buf[0] ),
.ps_select (ps_select_buf[0] ),
.out_type (vss ),
.shift_dr (shift_dr_buf[0] ),
.rst_io_l (rst_io_l_buf[0] ),
.rst_val_up (rst_val_up_buf[0] ),
.bso (bscan[11] ),
.serial_out (serial_out[11] ),
.bsr_si (bscan[10] ),
.rst_val_dn (rst_val_dn_buf[0] ),
.mode_ctl (mode_ctl_buf[0] ),
.si (scan[10] ),
.oe (oe_buf[0] ),
.data (data[11] ),
.se (se_buf[0] ),
.up_open (up_open_buf[0] ),
.down_25 (down_25_buf[0] ),
.to_core (to_core[11] ),
.ref (ref ),
.pad (pad[11] ),
.vddo (vddo ),
.sel_bypass (sel_bypass_buf[0] ) );
bw_io_dtl_pad DTL_4_ (
.cbu ({cbu1 } ),
.cbd ({cbd1 } ),
.bypass_enable (bypass_en_buf[1] ),
.so (scan[4] ),
.por_l (por_l_buf[1] ),
.clock_dr (clock_dr_buf[1] ),
.bypass_in (serial_out[5] ),
.serial_in (serial_in[4] ),
.update_dr (update_dr_buf[1] ),
.clk (ck3 ),
.reset_l (reset_l_buf[1] ),
.hiz_l (hiz_l_buf[1] ),
.ps_select (ps_select_buf[1] ),
.out_type (vdd ),
.shift_dr (shift_dr_buf[1] ),
.rst_io_l (rst_io_l_buf[1] ),
.rst_val_up (rst_val_up_buf[1] ),
.bso (bscan[4] ),
.serial_out (serial_out[4] ),
.bsr_si (bscan[9] ),
.rst_val_dn (rst_val_dn_buf[1] ),
.mode_ctl (mode_ctl_buf[1] ),
.si (scan[9] ),
.oe (oe_buf[1] ),
.data (data[4] ),
.se (se_buf[1] ),
.up_open (up_open_buf[1] ),
.down_25 (down_25_buf[1] ),
.to_core (to_core[4] ),
.ref (ref ),
.pad (pad[4] ),
.vddo (vddo ),
.sel_bypass (sel_bypass_buf[1] ) );
bw_io_dtl_pad DTL_10_ (
.cbu ({cbu0 } ),
.cbd ({cbd0 } ),
.bypass_enable (bypass_en_buf[0] ),
.so (scan[10] ),
.por_l (por_l_buf[0] ),
.clock_dr (clock_dr_buf[0] ),
.bypass_in (serial_out[11] ),
.serial_in (serial_in[10] ),
.update_dr (update_dr_buf[0] ),
.clk (ck0 ),
.reset_l (reset_l_buf[0] ),
.hiz_l (hiz_l_buf[0] ),
.ps_select (ps_select_buf[0] ),
.out_type (vdd ),
.shift_dr (shift_dr_buf[0] ),
.rst_io_l (rst_io_l_buf[0] ),
.rst_val_up (rst_val_up_buf[0] ),
.bso (bscan[10] ),
.serial_out (serial_out[10] ),
.bsr_si (bsr_si ),
.rst_val_dn (rst_val_dn_buf[0] ),
.mode_ctl (mode_ctl_buf[0] ),
.si (si ),
.oe (oe_buf[0] ),
.data (data[10] ),
.se (se_buf[0] ),
.up_open (up_open_buf[0] ),
.down_25 (down_25_buf[0] ),
.to_core (to_core[10] ),
.ref (ref ),
.pad (pad[10] ),
.vddo (vddo ),
.sel_bypass (sel_bypass_buf[0] ) );
bw_io_dtl_pad DTL_5_ (
.cbu ({cbu1 } ),
.cbd ({cbd1 } ),
.bypass_enable (bypass_en_buf[1] ),
.so (scan[5] ),
.por_l (por_l_buf[1] ),
.clock_dr (clock_dr_buf[1] ),
.bypass_in (vss ),
.serial_in (serial_in[5] ),
.update_dr (update_dr_buf[1] ),
.clk (ck2 ),
.reset_l (reset_l_buf[1] ),
.hiz_l (hiz_l_buf[1] ),
.ps_select (ps_select_buf[1] ),
.out_type (vss ),
.shift_dr (shift_dr_buf[1] ),
.rst_io_l (rst_io_l_buf[1] ),
.rst_val_up (rst_val_up_buf[1] ),
.bso (bscan[5] ),
.serial_out (serial_out[5] ),
.bsr_si (bscan[4] ),
.rst_val_dn (rst_val_dn_buf[1] ),
.mode_ctl (mode_ctl_buf[1] ),
.si (scan[4] ),
.oe (oe_buf[1] ),
.data (data[5] ),
.se (se_buf[1] ),
.up_open (up_open_buf[1] ),
.down_25 (down_25_buf[1] ),
.to_core (to_core[5] ),
.ref (ref ),
.pad (pad[5] ),
.vddo (vddo ),
.sel_bypass (sel_bypass_buf[1] ) );
bw_io_dtl_pad DTL_6_ (
.cbu ({cbu0 } ),
.cbd ({cbd0 } ),
.bypass_enable (bypass_en_buf[0] ),
.so (scan[6] ),
.por_l (por_l_buf[0] ),
.clock_dr (clock_dr_buf[0] ),
.bypass_in (serial_out[7] ),
.serial_in (serial_in[6] ),
.update_dr (update_dr_buf[0] ),
.clk (ck1 ),
.reset_l (reset_l_buf[0] ),
.hiz_l (hiz_l_buf[0] ),
.ps_select (ps_select_buf[0] ),
.out_type (vdd ),
.shift_dr (shift_dr_buf[0] ),
.rst_io_l (rst_io_l_buf[0] ),
.rst_val_up (rst_val_up_buf[0] ),
.bso (bscan[6] ),
.serial_out (serial_out[6] ),
.bsr_si (bscan[11] ),
.rst_val_dn (rst_val_dn_buf[0] ),
.mode_ctl (mode_ctl_buf[0] ),
.si (scan[11] ),
.oe (oe_buf[0] ),
.data (data[6] ),
.se (se_buf[0] ),
.up_open (up_open_buf[0] ),
.down_25 (down_25_buf[0] ),
.to_core (to_core[6] ),
.ref (ref ),
.pad (pad[6] ),
.vddo (vddo ),
.sel_bypass (sel_bypass_buf[0] ) );
bw_u1_ckbuf_30x I46 (
.clk (ck0 ),
.rclk (clk ) );
bw_u1_ckbuf_30x I47 (
.clk (ck2 ),
.rclk (clk ) );
bw_u1_ckbuf_30x I48 (
.clk (ck3 ),
.rclk (clk ) );
bw_u1_ckbuf_30x I49 (
.clk (ck1 ),
.rclk (clk ) );
bw_io_dtl_pad DTL_7_ (
.cbu ({cbu0 } ),
.cbd ({cbd0 } ),
.bypass_enable (bypass_en_buf[0] ),
.so (scan[7] ),
.por_l (por_l_buf[0] ),
.clock_dr (clock_dr_buf[0] ),
.bypass_in (vss ),
.serial_in (serial_in[7] ),
.update_dr (update_dr_buf[0] ),
.clk (ck0 ),
.reset_l (reset_l_buf[0] ),
.hiz_l (hiz_l_buf[0] ),
.ps_select (ps_select_buf[0] ),
.out_type (vss ),
.shift_dr (shift_dr_buf[0] ),
.rst_io_l (rst_io_l_buf[0] ),
.rst_val_up (rst_val_up_buf[0] ),
.bso (bscan[7] ),
.serial_out (serial_out[7] ),
.bsr_si (bscan[6] ),
.rst_val_dn (rst_val_dn_buf[0] ),
.mode_ctl (mode_ctl_buf[0] ),
.si (scan[6] ),
.oe (oe_buf[0] ),
.data (data[7] ),
.se (se_buf[0] ),
.up_open (up_open_buf[0] ),
.down_25 (down_25_buf[0] ),
.to_core (to_core[7] ),
.ref (ref ),
.pad (pad[7] ),
.vddo (vddo ),
.sel_bypass (sel_bypass_buf[0] ) );
endmodule
|
module register_bank(
input wire [31:0] r00_D,
input wire [31:0] r01_D,
input wire [31:0] r02_D,
input wire [31:0] r03_D,
input wire [31:0] r04_D,
input wire [31:0] r05_D,
input wire [31:0] r06_D,
input wire [31:0] r07_D,
input wire [31:0] r08_D,
input wire [31:0] r09_D,
input wire [31:0] r10_D,
input wire [31:0] r11_D,
input wire [31:0] r12_D,
input wire [31:0] r13_D,
input wire [31:0] r14_D,
input wire [31:0] r15_D,
input wire [15:0] hold_D,
output wire [31:0] r00_Q,
output wire [31:0] r01_Q,
output wire [31:0] r02_Q,
output wire [31:0] r03_Q,
output wire [31:0] r04_Q,
output wire [31:0] r05_Q,
output wire [31:0] r06_Q,
output wire [31:0] r07_Q,
output wire [31:0] r08_Q,
output wire [31:0] r09_Q,
output wire [31:0] r10_Q,
output wire [31:0] r11_Q,
output wire [31:0] r12_Q,
output wire [31:0] r13_Q,
output wire [31:0] r14_Q,
output wire [31:0] r15_Q,
output wire [15:0] hold_Q,
input wire CLK,
input wire EN,
input wire Reset
);
register r00 (r00_D, hold_D[00], CLK, EN, Reset, r00_Q, hold_Q[00]);
register r01 (r01_D, hold_D[01], CLK, EN, Reset, r01_Q, hold_Q[01]);
register r02 (r02_D, hold_D[02], CLK, EN, Reset, r02_Q, hold_Q[02]);
register r03 (r03_D, hold_D[03], CLK, EN, Reset, r03_Q, hold_Q[03]);
register r04 (r04_D, hold_D[04], CLK, EN, Reset, r04_Q, hold_Q[04]);
register r05 (r05_D, hold_D[05], CLK, EN, Reset, r05_Q, hold_Q[05]);
register r06 (r06_D, hold_D[06], CLK, EN, Reset, r06_Q, hold_Q[06]);
register r07 (r07_D, hold_D[07], CLK, EN, Reset, r07_Q, hold_Q[07]);
register r08 (r08_D, hold_D[08], CLK, EN, Reset, r08_Q, hold_Q[08]);
register r09 (r09_D, hold_D[09], CLK, EN, Reset, r09_Q, hold_Q[09]);
register r10 (r10_D, hold_D[10], CLK, EN, Reset, r10_Q, hold_Q[10]);
register r11 (r11_D, hold_D[11], CLK, EN, Reset, r11_Q, hold_Q[11]);
register r12 (r12_D, hold_D[12], CLK, EN, Reset, r12_Q, hold_Q[12]);
register r13 (r13_D, hold_D[13], CLK, EN, Reset, r13_Q, hold_Q[13]);
register r14 (r14_D, hold_D[14], CLK, EN, Reset, r14_Q, hold_Q[14]);
register r15 (r15_D, hold_D[15], CLK, EN, Reset, r15_Q, hold_Q[15]);
endmodule
// #TODO How to solve the problem of writing to two reg at once |
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